libpfm-4.9.0/0000775000175000017500000000000013223402656012616 5ustar eranianeranianlibpfm-4.9.0/python/0000775000175000017500000000000013223402656014137 5ustar eranianeranianlibpfm-4.9.0/python/README0000664000175000017500000000041013223402656015012 0ustar eranianeranianRequirements: To use the python bindings, you need the following packages: 1. swig (http://www.swig.org) 2. python-dev (http://www.python.org) 3. module-linux (http://code.google.com/p/module-linux) linux.sched is python package that comes with module-linux. libpfm-4.9.0/python/Makefile0000664000175000017500000000276513223402656015611 0ustar eranianeranian# # Copyright (c) 2008 Google, Inc. # Contributed by Arun Sharma # # Permission is hereby granted, free of charge, to any person obtaining a copy # of this software and associated documentation files (the "Software"), to deal # in the Software without restriction, including without limitation the rights # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies # of the Software, and to permit persons to whom the Software is furnished to do so, # subject to the following conditions: # # The above copyright notice and this permission notice shall be included in all # copies or substantial portions of the Software. # # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, # INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A # PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT # HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF # CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE # OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # TOPDIR := $(shell if [ "$$PWD" != "" ]; then echo $$PWD; else pwd; fi)/.. include $(TOPDIR)/config.mk include $(TOPDIR)/rules.mk PYTHON_PREFIX=$(PREFIX) all: CFLAGS="-O2 -g" ./setup.py build install: CFLAGS="-O2 -g" ./setup.py install --prefix=$(DESTDIR)$(PYTHON_PREFIX) clean: $(RM) src/perfmon_int_wrap.c src/perfmon_int.py src/*.pyc $(RM) -r build libpfm-4.9.0/python/self.py0000775000175000017500000000406213223402656015447 0ustar eranianeranian#!/usr/bin/env python # # Copyright (c) 2008 Google, Inc. # Contributed by Arun Sharma # # Permission is hereby granted, free of charge, to any person obtaining a # copy of this software and associated documentation files (the "Software"), # to deal in the Software without restriction, including without limitation # the rights to use, copy, modify, merge, publish, distribute, sublicense, # and/or sell copies of the Software, and to permit persons to whom the # Software is furnished to do so, subject to the following conditions: # # The above copyright notice and this permission notice shall be included # in all copies or substantial portions of the Software. # # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL # THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR # OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, # ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR # OTHER DEALINGS IN THE SOFTWARE. # # Self monitoring example. Copied from self.c import os import optparse import random import errno import struct import perfmon if __name__ == '__main__': parser = optparse.OptionParser() parser.add_option("-e", "--events", help="Events to use", action="store", dest="events") parser.set_defaults(events="PERF_COUNT_HW_CPU_CYCLES") (options, args) = parser.parse_args() if options.events: events = options.events.split(",") else: raise "You need to specify events to monitor" s = perfmon.PerThreadSession(int(os.getpid()), events) s.start() # code to be measured # # note that this is not identical to what examples/self.c does # thus counts will be different in the end for i in range(1, 1000000): random.random() # read the counts for i in range(0, len(events)): count = struct.unpack("L", s.read(i))[0] print """%s\t%lu""" % (events[i], count) libpfm-4.9.0/python/src/0000775000175000017500000000000013223402656014726 5ustar eranianeranianlibpfm-4.9.0/python/src/__init__.py0000664000175000017500000000012413223402656017034 0ustar eranianeranianfrom perfmon_int import * from pmu import * from session import * pfm_initialize() libpfm-4.9.0/python/src/session.py0000664000175000017500000000472313223402656016771 0ustar eranianeranian# # Copyright (c) 2008 Google, Inc. # Contributed by Arun Sharma # # Permission is hereby granted, free of charge, to any person obtaining a # copy of this software and associated documentation files (the "Software"), # to deal in the Software without restriction, including without limitation # the rights to use, copy, modify, merge, publish, distribute, sublicense, # and/or sell copies of the Software, and to permit persons to whom the # Software is furnished to do so, subject to the following conditions: # # The above copyright notice and this permission notice shall be included # in all copies or substantial portions of the Software. # # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL # THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR # OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, # ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR # OTHER DEALINGS IN THE SOFTWARE. # from perfmon import * import os import sys # Common base class class Session: def __init__(self, events): self.system = System() self.event_names = events self.events = [] self.fds = [] for e in events: err, encoding = pfm_get_perf_event_encoding(e, PFM_PLM0 | PFM_PLM3, None, None) self.events.append(encoding) def __del__(self): pass def read(self, fd): # TODO: determine counter width return os.read(fd, 8) class SystemWideSession(Session): def __init__(self, cpus, events): self.cpus = cpus Session.__init__(self, events) def __del__(self): Session.__del__(self) def start(self): self.cpu_fds = [] for c in self.cpus: self.cpu_fds.append([]) cur_cpu_fds = self.cpu_fds[-1] for e in self.events: cur_cpu_fds.append(perf_event_open(e, -1, c, -1, 0)) def read(self, c, i): index = self.cpus.index(c) return Session.read(self, self.cpu_fds[index][i]) class PerThreadSession(Session): def __init__(self, pid, events): self.pid = pid Session.__init__(self, events) def __del__(self): Session.__del__(self) def start(self): for e in self.events: self.fds.append(perf_event_open(e, self.pid, -1, -1, 0)) def read(self, i): return Session.read(self, self.fds[i]) libpfm-4.9.0/python/src/pmu.py0000664000175000017500000000561113223402656016104 0ustar eranianeranian# # Copyright (c) 2008 Google, Inc. # Contributed by Arun Sharma # # Permission is hereby granted, free of charge, to any person obtaining a # copy of this software and associated documentation files (the "Software"), # to deal in the Software without restriction, including without limitation # the rights to use, copy, modify, merge, publish, distribute, sublicense, # and/or sell copies of the Software, and to permit persons to whom the # Software is furnished to do so, subject to the following conditions: # # The above copyright notice and this permission notice shall be included # in all copies or substantial portions of the Software. # # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL # THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR # OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, # ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR # OTHER DEALINGS IN THE SOFTWARE. # import os from perfmon import * def public_members(self): s = "{ " for k, v in self.__dict__.iteritems(): if not k[0] == '_': s += "%s : %s, " % (k, v) s += " }" return s class System: # Use the os that gives us everything os = PFM_OS_PERF_EVENT_EXT def __init__(self): self.ncpus = os.sysconf('SC_NPROCESSORS_ONLN') self.pmus = [] for i in range(0, PFM_PMU_MAX): try: pmu = PMU(i) except: pass else: self.pmus.append(pmu) def __repr__(self): return public_members(self) class Event: def __init__(self, info): self.info = info self.__attrs = [] def __repr__(self): return '\n' + public_members(self) def __parse_attrs(self): info = self.info for index in range(0, info.nattrs): self.__attrs.append(pfm_get_event_attr_info(info.idx, index, System.os)[1]) def attrs(self): if not self.__attrs: self.__parse_attrs() return self.__attrs class PMU: def __init__(self, i): self.info = pfm_get_pmu_info(i)[1] self.__events = [] def __parse_events(self): index = self.info.first_event while index != -1: self.__events.append(Event(pfm_get_event_info(index, System.os)[1])) index = pfm_get_event_next(index) def events(self): if not self.__events: self.__parse_events() return self.__events def __repr__(self): return public_members(self) if __name__ == '__main__': from perfmon import * s = System() for pmu in s.pmus: info = pmu.info if info.flags.is_present: print info.name, info.size, info.nevents for e in pmu.events(): print e.info.name, e.info.code for a in e.attrs(): print '\t\t', a.name, a.code libpfm-4.9.0/python/src/perfmon_int.i0000664000175000017500000000617013223402656017424 0ustar eranianeranian/* * * Copyright (c) 2008 Google, Inc. * Contributed by Arun Sharma * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Python Bindings for perfmon. */ %module perfmon_int %{ #include #define SWIG #include #include #include static PyObject *libpfm_err; %} %include "typemaps.i" %include "carrays.i" %include "cstring.i" %include /* Convert libpfm errors into exceptions */ %typemap(out) os_err_t { if (result == -1) { PyErr_SetFromErrno(PyExc_OSError); SWIG_fail; } resultobj = SWIG_From_int((int)(result)); }; %typemap(out) pfm_err_t { if (result != PFM_SUCCESS) { PyObject *obj = Py_BuildValue("(i,s)", result, pfm_strerror(result)); PyErr_SetObject(libpfm_err, obj); SWIG_fail; } else { PyErr_Clear(); } resultobj = SWIG_From_int((int)(result)); } /* Generic return structures via pointer output arguments */ %define ptr_argout(T) %typemap(argout) T* output { if (!PyTuple_Check($result)) { PyObject *x = $result; $result = PyTuple_New(1); PyTuple_SET_ITEM($result, 0, x); } PyObject *o = SWIG_NewPointerObj((void *)$1, $descriptor, 0); $result = SWIG_AppendOutput($result, o); } %typemap(in, numinputs=0) T* output { $1 = (T*) malloc(sizeof(T)); memset($1, 0, sizeof(T)); } %extend T { ~T() { free(self); } } %enddef ptr_argout(pfm_pmu_info_t); ptr_argout(pfm_event_info_t); ptr_argout(pfm_event_attr_info_t); %typedef int pid_t; /* Kernel interface */ %include ptr_argout(perf_event_attr_t); /* Library interface */ /* We never set the const char * members. So no memory leak */ #pragma SWIG nowarn=451 %include /* OS specific library interface */ extern pfm_err_t pfm_get_perf_event_encoding(const char *str, int dfl_plm, perf_event_attr_t *output, char **fstr, int *idx); %init %{ libpfm_err = PyErr_NewException("perfmon.libpfmError", NULL, NULL); PyDict_SetItemString(d, "libpfmError", libpfm_err); %} libpfm-4.9.0/python/setup.py0000775000175000017500000000124013223402656015651 0ustar eranianeranian#!/usr/bin/env python from distutils.core import setup, Extension from distutils.command.install_data import install_data setup(name='perfmon', version='4.0', author='Arun Sharma', author_email='arun.sharma@google.com', description='libpfm wrapper', packages=['perfmon'], package_dir={ 'perfmon' : 'src' }, py_modules=['perfmon.perfmon_int'], ext_modules=[Extension('perfmon._perfmon_int', sources = ['src/perfmon_int.i'], libraries = ['pfm'], library_dirs = ['../lib'], include_dirs = ['../include'], swig_opts=['-I../include'])]) libpfm-4.9.0/python/sys.py0000775000175000017500000000435513223402656015341 0ustar eranianeranian#!/usr/bin/env python # # Copyright (c) 2008 Google, Inc. # Contributed by Arun Sharma # # Permission is hereby granted, free of charge, to any person obtaining a # copy of this software and associated documentation files (the "Software"), # to deal in the Software without restriction, including without limitation # the rights to use, copy, modify, merge, publish, distribute, sublicense, # and/or sell copies of the Software, and to permit persons to whom the # Software is furnished to do so, subject to the following conditions: # # The above copyright notice and this permission notice shall be included # in all copies or substantial portions of the Software. # # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL # THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR # OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, # ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR # OTHER DEALINGS IN THE SOFTWARE. # # System wide monitoring example. Copied from syst.c # # Run as: ./sys.py -c cpulist -e eventlist import sys import os import optparse import time import struct import perfmon if __name__ == '__main__': parser = optparse.OptionParser() parser.add_option("-e", "--events", help="Events to use", action="store", dest="events") parser.add_option("-c", "--cpulist", help="CPUs to monitor", action="store", dest="cpulist") parser.set_defaults(cpulist="0") parser.set_defaults(events="PERF_COUNT_HW_CPU_CYCLES") (options, args) = parser.parse_args() cpus = options.cpulist.split(',') cpus = [ int(c) for c in cpus ] if options.events: events = options.events.split(",") else: raise "You need to specify events to monitor" s = perfmon.SystemWideSession(cpus, events) s.start() # Measuring loop while 1: time.sleep(1) # read the counts for c in cpus: for i in range(0, len(events)): count = struct.unpack("L", s.read(c, i))[0] print """CPU%d: %s\t%lu""" % (c, events[i], count) libpfm-4.9.0/README0000664000175000017500000001302313223402656013475 0ustar eranianeranian ------------------------------------------------------------ libpfm-4.x: a helper library to program the performance monitoring events ------------------------------------------------------------ Copyright (c) 2009 Google, Inc Contributed by Stephane Eranian Copyright (c) 2001-2007 Hewlett-Packard Development Company, L.P. Contributed by Stephane Eranian This package provides a library, called libpfm4 which is used to develop monitoring tools exploiting the performance monitoring events such as those provided by the Performance Monitoring Unit (PMU) of modern processors. This is a complete rewrite of libpfm3 and it is NOT backward compatible with it. Libpfm4 helps convert from an event name, expressed as a string, to the event encoding that is either the raw event as documented by HW vendor or the OS-specific encoding. In the latter case, the library is able to prepare the OS-specific data structures needed by the kernel to setup the event. The current libpfm4 provides support for the perf_events interface which was introduced in Linux v2.6.31. Perfmon support is not present yet. The library does not make any performance monitoring system calls. It is portable and supports other operating system environments beyond Linux, such as Mac OS X, and Windows. The library supports many PMUs. The current version can handle: - For AMD X86: AMD64 K7, K8 AMD64 Fam10h (Barcelona, Shanghai, Istanbul) AMD64 Fam11h (Turion) AMD64 Fam12h (Llano) AMD64 Fam14h (Bobcat) AMD64 Fam15h (Bulldozer) (core and uncore) AMD64 Fam16h (Jaguar) AMD64 Fam17h (Zen) - For Intel X86: Intel P6 (Pentium II, Pentium Pro, Pentium III, Pentium M) Intel Yonah (Core Duo/Core Solo), Intel Core (Merom, Penryn, Dunnington) Intel Atom Intel Nehalem, Westmere Intel Sandy Bridge Intel Ivy Bridge Intel Haswell Intel Broadwell Intel SkyLake Intel Silvermont Intel Airmont Intel Goldmont Intel RAPL (energy consumption) Intel Knights Corner Intel Knights Landing (core, uncore) Intel architectural perfmon v1, v2, v3 - For ARM: ARMV7 Cortex A8 ARMV7 Cortex A9 ARMV7 Cortex A15 ARMV8 Cortex A57, A53 Applied Micro X-Gene Qualcomm Krait - For SPARC Ultra I, II Ultra III, IIIi, III+ Ultra IV+ Niagara I, Niagara II - For IBM Power 4 Power 5 Power 6 Power 7 Power 8 Power 8 Nest Power 9 PPC970 Torrent System z (s390x) - For MIPS Mips 74k WHAT'S THERE ------------- - the library source code including support for all processors listed above - a set of generic examples showing how to list and query events. They are in examples. - a set of examples showing how the library can be used with the perf_events interface. They are in perf_examples. - a set of library header files used to compile the library and perf_examples - man pages for all the library entry points - Python bindings for the library - a SPEC file to build RPMs from the library - the Debian-style config file to build a .deb package from the library INSTALLATION ------------ - edit config.mk to : - update some of the configuration variables - select your compiler options - type make - type make install - The default installation location is /usr/local. You can specify a diffierent install location as follows: $ make PREFIX= install Depending on your install location, you may need to run the 'ldconfig' command or use LD_LIBRARY_PATH when you build and run tools that link to the libpfm4 library. - By default, libpfm library files are installed in /lib. If 'make' builds 64-bit libraries on your system, and your target architecture expects 64-bit libraries to be located in a library named "lib64", then you should use the LIBDIR variable when installing, as follows: $ make LIBDIR=/lib64 install - To compile and install the Python bindings, you need to go to the python sub-directory and type make. Python may not be systematically built. - to compile the library for another ABI (e.g. 32-bit x86 on a 64-bit x86) system, you can pass the ABI flag to the compiler as follows (assuming you have the multilib version of gcc): $ make OPTIM="-m32 -O2" PACKAGING --------- The library comes with the config files necessary to generate RPMs or Debian packages. The source code produces 3 packages: - libpfm : runtime library - libpfm-dev: development files (headers, manpages, static library) - libpfm-python: Python bindings for the library To generate the RPMs: $ rpmbuild -ba libpfm.spec To generate the Debian packages: $ debuild -i -us -uc -b You may need to install some extra packages to make Debian package generation possible. REQUIREMENTS: ------------- - to run the programs in the perf_examples subdir, you MUST be using a linux kernel with perf_events. That means v2.6.31 or later. - to compile the Python bindings, you need to have SWIG and the python development packages installed - To compile on Windows, you need the MinGW and MSYS compiler environment (see www.mingw.org). The environment needs to be augmented with the mingw regex user contributed package (mingw-libgnurx-2.5.1.dev.tar.gz). - To compile on Mac OS X, you need to have gmake installed. DOCUMENTATION ------------- - man pages for all entry points. It is recommended you start with: man libpfm - More information can be found on library web site: http://perfmon2.sf.net libpfm-4.9.0/Makefile0000664000175000017500000000501713223402656014261 0ustar eranianeranian# # Copyright (c) 2002-2006 Hewlett-Packard Development Company, L.P. # Contributed by Stephane Eranian # # Permission is hereby granted, free of charge, to any person obtaining a copy # of this software and associated documentation files (the "Software"), to deal # in the Software without restriction, including without limitation the rights # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies # of the Software, and to permit persons to whom the Software is furnished to do so, # subject to the following conditions: # # The above copyright notice and this permission notice shall be included in all # copies or substantial portions of the Software. # # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, # INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A # PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT # HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF # CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE # OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # # # Look in config.mk for options # TOPDIR := $(shell if [ "$$PWD" != "" ]; then echo $$PWD; else pwd; fi) include config.mk EXAMPLE_DIRS=examples DIRS=lib tests $(EXAMPLE_DIRS) include docs ifeq ($(SYS),Linux) EXAMPLE_DIRS +=perf_examples endif ifneq ($(CONFIG_PFMLIB_NOPYTHON),y) DIRS += python endif TAR=tar --exclude=.git --exclude=.gitignore CURDIR=$(shell basename "$$PWD") PKG=libpfm-4.$(REVISION).$(AGE) TARBALL=$(PKG).tar.gz all: @echo Compiling for \'$(ARCH)\' target @echo Compiling for \'$(SYS)\' system @set -e ; for d in $(DIRS) ; do $(MAKE) -C $$d $@ ; done lib: $(MAKE) -C lib clean: @set -e ; for d in $(DIRS) ; do $(MAKE) -C $$d $@ ; done distclean: clean @(cd debian; $(RM) -f *.log *.debhelper *.substvars; $(RM) -rf libpfm4-dev libpfm4 python-libpfm4 tmp files) $(RM) -f tags depend: @set -e ; for d in $(DIRS) ; do $(MAKE) -C $$d $@ ; done tar: clean ln -s $$PWD ../$(PKG) && cd .. && $(TAR) -zcf $(TARBALL) $(PKG)/. && rm $(PKG) @echo generated ../$(TARBALL) install: @echo installing in $(DESTDIR) @set -e ; for d in $(DIRS) ; do $(MAKE) -C $$d $@ ; done install_examples: @set -e ; for d in $(EXAMPLE_DIRS) ; do $(MAKE) -C $$d $@ ; done tags: @echo creating tags $(MAKE) -C lib $@ static: make all CONFIG_PFMLIB_SHARED=n .PHONY: all clean distclean depend tar install install_examples lib static # DO NOT DELETE libpfm-4.9.0/tests/0000775000175000017500000000000013223402656013760 5ustar eranianeranianlibpfm-4.9.0/tests/validate_arm64.c0000664000175000017500000001331113223402656016725 0ustar eranianeranian/* * validate_arm64.c - validate ARM64 event tables + encodings * * Copyright (c) 2014 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ #include #include #include #include #include #include #include #include #include #define MAX_ENCODING 1 #define SRC_LINE .line = __LINE__ typedef struct { const char *name; const char *fstr; uint64_t codes[MAX_ENCODING]; int ret, count, line; } test_event_t; static const test_event_t arm64_test_events[]={ { SRC_LINE, .name = "arm_ac57::CPU_CYCLES", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x8000011, .fstr = "arm_ac57::CPU_CYCLES:k=1:u=1:hv=0", }, { SRC_LINE, .name = "arm_ac57::CPU_CYCLES:k", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x88000011, .fstr = "arm_ac57::CPU_CYCLES:k=1:u=0:hv=0", }, { SRC_LINE, .name = "arm_ac57::CPU_CYCLES:k:u", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x8000011, .fstr = "arm_ac57::CPU_CYCLES:k=1:u=1:hv=0", }, { SRC_LINE, .name = "arm_ac57::INST_RETIRED", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x8000008, .fstr = "arm_ac57::INST_RETIRED:k=1:u=1:hv=0", }, { SRC_LINE, .name = "arm_ac53::CPU_CYCLES", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x8000011, .fstr = "arm_ac53::CPU_CYCLES:k=1:u=1:hv=0", }, { SRC_LINE, .name = "arm_ac53::CPU_CYCLES:k", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x88000011, .fstr = "arm_ac53::CPU_CYCLES:k=1:u=0:hv=0", }, { SRC_LINE, .name = "arm_ac53::CPU_CYCLES:k:u", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x8000011, .fstr = "arm_ac53::CPU_CYCLES:k=1:u=1:hv=0", }, { SRC_LINE, .name = "arm_ac53::INST_RETIRED", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x8000008, .fstr = "arm_ac53::INST_RETIRED:k=1:u=1:hv=0", }, { SRC_LINE, .name = "arm_ac53::LD_RETIRED", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x8000006, .fstr = "arm_ac53::LD_RETIRED:k=1:u=1:hv=0", }, { SRC_LINE, .name = "arm_ac53::ST_RETIRED", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x8000007, .fstr = "arm_ac53::ST_RETIRED:k=1:u=1:hv=0", }, { SRC_LINE, .name = "arm_xgene::CPU_CYCLES", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x8000011, .fstr = "arm_xgene::CPU_CYCLES:k=1:u=1:hv=0", }, { SRC_LINE, .name = "arm_xgene::CPU_CYCLES:k", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x88000011, .fstr = "arm_xgene::CPU_CYCLES:k=1:u=0:hv=0", }, { SRC_LINE, .name = "arm_xgene::CPU_CYCLES:k:u", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x8000011, .fstr = "arm_xgene::CPU_CYCLES:k=1:u=1:hv=0", }, { SRC_LINE, .name = "arm_xgene::INST_RETIRED", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x8000008, .fstr = "arm_xgene::INST_RETIRED:k=1:u=1:hv=0", }, }; #define NUM_TEST_EVENTS (int)(sizeof(arm64_test_events)/sizeof(test_event_t)) static int check_test_events(FILE *fp) { const test_event_t *e; char *fstr; uint64_t *codes; int count, i, j; int ret, errors = 0; for (i = 0, e = arm64_test_events; i < NUM_TEST_EVENTS; i++, e++) { codes = NULL; count = 0; fstr = NULL; ret = pfm_get_event_encoding(e->name, PFM_PLM0 | PFM_PLM3, &fstr, NULL, &codes, &count); if (ret != e->ret) { fprintf(fp,"Line %d, Event%d %s, ret=%s(%d) expected %s(%d)\n", e->line, i, e->name, pfm_strerror(ret), ret, pfm_strerror(e->ret), e->ret); errors++; } else { if (ret != PFM_SUCCESS) { if (fstr) { fprintf(fp,"Line %d, Event%d %s, expected fstr NULL but it is not\n", e->line, i, e->name); errors++; } if (count != 0) { fprintf(fp,"Line %d, Event%d %s, expected count=0 instead of %d\n", e->line, i, e->name, count); errors++; } if (codes) { fprintf(fp,"Line %d, Event%d %s, expected codes[] NULL but it is not\n", e->line, i, e->name); errors++; } } else { if (count != e->count) { fprintf(fp,"Line %d, Event%d %s, count=%d expected %d\n", e->line, i, e->name, count, e->count); errors++; } for (j=0; j < count; j++) { if (codes[j] != e->codes[j]) { fprintf(fp,"Line %d, Event%d %s, codes[%d]=%#"PRIx64" expected %#"PRIx64"\n", e->line, i, e->name, j, codes[j], e->codes[j]); errors++; } } if (e->fstr && strcmp(fstr, e->fstr)) { fprintf(fp,"Line %d, Event%d %s, fstr=%s expected %s\n", e->line, i, e->name, fstr, e->fstr); errors++; } } } if (codes) free(codes); if (fstr) free(fstr); } printf("\t %d ARM64 events: %d errors\n", i, errors); return errors; } int validate_arch(FILE *fp) { return check_test_events(fp); } libpfm-4.9.0/tests/Makefile0000664000175000017500000000400613223402656015420 0ustar eranianeranian# # Copyright (c) 2010 Google, Inc # Contributed by Stephane Eranian # # Permission is hereby granted, free of charge, to any person obtaining a copy # of this software and associated documentation files (the "Software"), to deal # in the Software without restriction, including without limitation the rights # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies # of the Software, and to permit persons to whom the Software is furnished to do so, # subject to the following conditions: # # The above copyright notice and this permission notice shall be included in all # copies or substantial portions of the Software. # # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, # INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A # PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT # HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF # CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE # OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # TOPDIR := $(shell if [ "$$PWD" != "" ]; then echo $$PWD; else pwd; fi)/.. include $(TOPDIR)/config.mk include $(TOPDIR)/rules.mk SRCS=validate.c ifeq ($(CONFIG_PFMLIB_ARCH_X86),y) SRCS += validate_x86.c endif ifeq ($(CONFIG_PFMLIB_ARCH_MIPS),y) SRCS += validate_mips.c endif ifeq ($(CONFIG_PFMLIB_ARCH_ARM),y) SRCS += validate_arm.c endif ifeq ($(CONFIG_PFMLIB_ARCH_ARM64),y) SRCS += validate_arm64.c endif ifeq ($(CONFIG_PFMLIB_ARCH_POWERPC),y) SRCS += validate_power.c endif CFLAGS+= -I. -D_GNU_SOURCE LIBS += -lm ifeq ($(SYS),Linux) CFLAGS+= -pthread endif OBJS=$(SRCS:.c=.o) TARGETS=validate all: $(TARGETS) validate: $(OBJS) $(PFMLIB) $(CC) $(CFLAGS) -o $@ $(LDFLAGS) $^ $(LIBS) clean: $(RM) -f *.o $(TARGETS) *~ distclean: clean # # examples are installed as part of the RPM install, typically in /usr/share/doc/libpfm-X.Y/ # .PHONY: install depend install_examples libpfm-4.9.0/tests/validate_x86.c0000664000175000017500000051157313223402656016436 0ustar eranianeranian/* * validate_x86.c - validate event tables + encodings * * Copyright (c) 2010 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. */ #include #include #include #include #include #include #include #include #include #define MAX_ENCODING 8 #define SRC_LINE .line = __LINE__ typedef struct { const char *name; const char *fstr; uint64_t codes[MAX_ENCODING]; int ret, count; int line; } test_event_t; static const test_event_t x86_test_events[]={ { SRC_LINE, .name = "core::INST_RETIRED:ANY_P", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x5300c0ull, }, { SRC_LINE, .name = "core::INST_RETIRED:ANY_P:ANY_P", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x5300c0ull, }, { SRC_LINE, .name = "core::INST_RETIRED:ANY_P:DEAD", .ret = PFM_ERR_ATTR, /* cannot know if it is umask or mod */ .count = 0, .codes[0] = 0ull, }, { SRC_LINE, .name = "core::INST_RETIRED:ANY_P:u:u", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x5100c0ull, }, { SRC_LINE, .name = "core::INST_RETIRED:ANY_P:u=0:k=1:u=1", .ret = PFM_ERR_ATTR_SET, .count = 0, .codes[0] = 0ull, }, { SRC_LINE, .name = "core::INST_RETIRED:ANY_P:c=1:i", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1d300c0ull, }, { SRC_LINE, .name = "core::INST_RETIRED:ANY_P:c=1:i=1", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1d300c0ull, }, { SRC_LINE, .name = "core::INST_RETIRED:ANY_P:c=2", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x25300c0ull, }, { SRC_LINE, .name = "core::INST_RETIRED:ANY_P:c=320", .ret = PFM_ERR_ATTR_VAL, .count = 0, .codes[0] = 0ull, }, { SRC_LINE, .name = "core::INST_RETIRED:ANY_P:t=1", .ret = PFM_ERR_ATTR, .count = 0, .codes[0] = 0ull, }, { SRC_LINE, .name = "core::L2_LINES_IN", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x537024ull, }, { SRC_LINE, .name = "core::L2_LINES_IN:SELF", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x537024ull, .fstr = "core::L2_LINES_IN:SELF:ANY:k=1:u=1:e=0:i=0:c=0", }, { SRC_LINE, .name = "core::L2_LINES_IN:SELF:BOTH_CORES", .ret = PFM_ERR_FEATCOMB, .count = 0, .codes[0] = 0ull, }, { SRC_LINE, .name = "core::L2_LINES_IN:SELF:PREFETCH", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x535024ull, }, { SRC_LINE, .name = "core::L2_LINES_IN:SELF:PREFETCH:ANY", .ret = PFM_ERR_FEATCOMB, .count = 0, .codes[0] = 0ull, }, { SRC_LINE, .name = "core::RS_UOPS_DISPATCHED_NONE", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1d300a0ull, }, { SRC_LINE, .name = "core::RS_UOPS_DISPATCHED_NONE:c=2", .ret = PFM_ERR_ATTR_SET, .count = 1, .codes[0] = 0ull, }, { SRC_LINE, .name = "core::branch_instructions_retired", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x5300c4ull, .fstr = "core::BR_INST_RETIRED:ANY:k=1:u=1:e=0:i=0:c=0" }, { SRC_LINE, .name = "nhm::branch_instructions_retired", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x5300c4ull, .fstr = "nhm::BR_INST_RETIRED:ALL_BRANCHES:k=1:u=1:e=0:i=0:c=0:t=0" }, { SRC_LINE, .name = "wsm::BRANCH_INSTRUCTIONS_RETIRED", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x5300c4ull, /* architected encoding, guaranteed to exist */ .fstr = "wsm::BR_INST_RETIRED:ALL_BRANCHES:k=1:u=1:e=0:i=0:c=0:t=0" }, { SRC_LINE, .name = "nhm::ARITH:DIV:k", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1d60114ull, .fstr = "nhm::ARITH:CYCLES_DIV_BUSY:k=1:u=0:e=1:i=1:c=1:t=0", }, { SRC_LINE, .name = "nhm::ARITH:CYCLES_DIV_BUSY:k=1:u=1:e=1:i=1:c=1:t=0", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1d70114ull, .fstr = "nhm::ARITH:CYCLES_DIV_BUSY:k=1:u=1:e=1:i=1:c=1:t=0", }, { SRC_LINE, .name = "wsm::UOPS_EXECUTED:CORE_STALL_COUNT:u", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1f53fb1ull, .fstr = "wsm::UOPS_EXECUTED:CORE_STALL_CYCLES:k=0:u=1:e=1:i=1:c=1:t=1", }, { SRC_LINE, .name = "wsm::UOPS_EXECUTED:CORE_STALL_COUNT:u:t=0", .ret = PFM_ERR_ATTR_SET, .count = 0, .codes[0] = 0ull, }, { SRC_LINE, .name = "wsm_unc::unc_qmc_writes:full_any:partial_any", .ret = PFM_ERR_FEATCOMB, .count = 0, .codes[0] = 0ull, }, { SRC_LINE, .name = "wsm_unc::unc_qmc_writes", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x50072full, .fstr = "wsm_unc::UNC_QMC_WRITES:FULL_ANY:e=0:i=0:c=0:o=0", }, { SRC_LINE, .name = "wsm_unc::unc_qmc_writes:full_any", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x50072full, .fstr = "wsm_unc::UNC_QMC_WRITES:FULL_ANY:e=0:i=0:c=0:o=0", }, { SRC_LINE, .name = "wsm_unc::unc_qmc_writes:full_ch0", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x50012full, .fstr = "wsm_unc::UNC_QMC_WRITES:FULL_CH0:e=0:i=0:c=0:o=0", }, { SRC_LINE, .name = "wsm_unc::unc_qmc_writes:partial_any", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x50382full, .fstr = "wsm_unc::UNC_QMC_WRITES:PARTIAL_ANY:e=0:i=0:c=0:o=0", }, { SRC_LINE, .name = "wsm_unc::unc_qmc_writes:partial_ch0", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x50082full, .fstr = "wsm_unc::UNC_QMC_WRITES:PARTIAL_CH0:e=0:i=0:c=0:o=0", }, { SRC_LINE, .name = "wsm_unc::unc_qmc_writes:partial_ch0:partial_ch1", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x50182full, .fstr = "wsm_unc::UNC_QMC_WRITES:PARTIAL_CH0:PARTIAL_CH1:e=0:i=0:c=0:o=0", }, { SRC_LINE, .name = "amd64_fam10h_barcelona::DISPATCHED_FPU", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x533f00ull, .fstr = "amd64_fam10h_barcelona::DISPATCHED_FPU:ALL:k=1:u=1:e=0:i=0:c=0:h=0:g=0" }, { SRC_LINE, .name = "amd64_fam10h_barcelona::DISPATCHED_FPU:k:u=0", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x523f00ull, .fstr = "amd64_fam10h_barcelona::DISPATCHED_FPU:ALL:k=1:u=0:e=0:i=0:c=0:h=0:g=0" }, { SRC_LINE, .name = "amd64_fam10h_barcelona::DISPATCHED_FPU:OPS_ADD:OPS_MULTIPLY", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x530300ull, .fstr = "amd64_fam10h_barcelona::DISPATCHED_FPU:OPS_ADD:OPS_MULTIPLY:k=1:u=1:e=0:i=0:c=0:h=0:g=0", }, { SRC_LINE, .name = "amd64_fam10h_barcelona::L2_CACHE_MISS:ALL:DATA", .ret = PFM_ERR_FEATCOMB, .count = 0, .codes[0] = 0ull, }, { SRC_LINE, .name = "amd64_fam10h_barcelona::MEMORY_CONTROLLER_REQUESTS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x10053fff0ull, .fstr = "amd64_fam10h_barcelona::MEMORY_CONTROLLER_REQUESTS:ALL:k=1:u=1:e=0:i=0:c=0:h=0:g=0", }, { SRC_LINE, .name = "amd64_k8_revb::RETURN_STACK_OVERFLOWS:g=1:u", .ret = PFM_ERR_ATTR, .count = 0, .codes[0] = 0ull, }, { SRC_LINE, .name = "amd64_k8_revb::RETURN_STACK_HITS:e=1", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x570088ull, .fstr = "amd64_k8_revb::RETURN_STACK_HITS:k=1:u=1:e=1:i=0:c=0", }, { SRC_LINE, .name = "amd64_k8_revb::PROBE:ALL", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x533fecull, .fstr = "amd64_k8_revb::PROBE:ALL:k=1:u=1:e=0:i=0:c=0", }, { SRC_LINE, .name = "amd64_k8_revc::PROBE:ALL", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x533fecull, .fstr = "amd64_k8_revc::PROBE:ALL:k=1:u=1:e=0:i=0:c=0", }, { SRC_LINE, .name = "amd64_k8_revd::PROBE:ALL", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x537fecull, .fstr = "amd64_k8_revd::PROBE:ALL:k=1:u=1:e=0:i=0:c=0" }, { SRC_LINE, .name = "amd64_k8_reve::PROBE:ALL", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x537fecull, .fstr = "amd64_k8_reve::PROBE:ALL:k=1:u=1:e=0:i=0:c=0" }, { SRC_LINE, .name = "amd64_k8_revf::PROBE:ALL", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x537fecull, .fstr = "amd64_k8_revf::PROBE:ALL:k=1:u=1:e=0:i=0:c=0" }, { SRC_LINE, .name = "amd64_k8_revg::PROBE:ALL", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x537fecull, .fstr = "amd64_k8_revg::PROBE:ALL:k=1:u=1:e=0:i=0:c=0" }, { SRC_LINE, .name = "amd64_fam10h_barcelona::L1_DTLB_MISS_AND_L2_DTLB_HIT:L2_1G_TLB_HIT", .ret = PFM_ERR_ATTR, .count = 0, .codes[0] = 0ull, }, { SRC_LINE, .name = "amd64_fam10h_barcelona::L1_DTLB_MISS_AND_L2_DTLB_HIT:ALL", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x530345ull, .fstr = "amd64_fam10h_barcelona::L1_DTLB_MISS_AND_L2_DTLB_HIT:ALL:k=1:u=1:e=0:i=0:c=0:h=0:g=0" }, { SRC_LINE, .name = "amd64_fam10h_shanghai::L1_DTLB_MISS_AND_L2_DTLB_HIT:ALL", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x530745ull, .fstr = "amd64_fam10h_shanghai::L1_DTLB_MISS_AND_L2_DTLB_HIT:ALL:k=1:u=1:e=0:i=0:c=0:h=0:g=0" }, { SRC_LINE, .name = "amd64_fam10h_istanbul::L1_DTLB_MISS_AND_L2_DTLB_HIT:ALL", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x530745ull, .fstr = "amd64_fam10h_istanbul::L1_DTLB_MISS_AND_L2_DTLB_HIT:ALL:k=1:u=1:e=0:i=0:c=0:h=0:g=0" }, { SRC_LINE, .name = "amd64_fam10h_barcelona::READ_REQUEST_TO_L3_CACHE", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x40053f7e0ull, .fstr = "amd64_fam10h_barcelona::READ_REQUEST_TO_L3_CACHE:ANY_READ:ALL_CORES:k=1:u=1:e=0:i=0:c=0:h=0:g=0", }, { SRC_LINE, .name = "amd64_fam10h_shanghai::READ_REQUEST_TO_L3_CACHE", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x40053f7e0ull, .fstr = "amd64_fam10h_shanghai::READ_REQUEST_TO_L3_CACHE:ANY_READ:ALL_CORES:k=1:u=1:e=0:i=0:c=0:h=0:g=0", }, { SRC_LINE, .name = "core::RAT_STALLS:ANY:u:c=1,cycles", /* must cut at comma */ .ret = PFM_ERR_INVAL, }, { SRC_LINE, .name = "wsm::mem_uncore_retired:remote_dram", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x53200f, .fstr = "wsm::MEM_UNCORE_RETIRED:REMOTE_DRAM:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "wsm_dp::mem_uncore_retired:remote_dram", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x53100f, .fstr = "wsm_dp::MEM_UNCORE_RETIRED:REMOTE_DRAM:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "wsm::mem_uncore_retired:local_dram", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x53100f, .fstr = "wsm::MEM_UNCORE_RETIRED:LOCAL_DRAM:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "wsm_dp::mem_uncore_retired:local_dram", .ret = PFM_ERR_ATTR, .count = 1, .codes[0] = 0, }, { SRC_LINE, .name = "nhm::mem_uncore_retired:uncacheable", .ret = PFM_ERR_ATTR, .count = 1, .codes[0] = 0, }, { SRC_LINE, .name = "nhm::mem_uncore_retired:l3_data_miss_unknown", .ret = PFM_ERR_ATTR, .count = 1, .codes[0] = 0, }, { SRC_LINE, .name = "nhm_ex::mem_uncore_retired:uncacheable", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x53800f, .fstr = "nhm_ex::MEM_UNCORE_RETIRED:UNCACHEABLE:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "nhm_ex::mem_uncore_retired:l3_data_miss_unknown", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x53010f, .fstr = "nhm_ex::MEM_UNCORE_RETIRED:L3_DATA_MISS_UNKNOWN:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "nhm::mem_uncore_retired:local_dram", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x53200f, .fstr = "nhm::MEM_UNCORE_RETIRED:LOCAL_DRAM:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "nhm_ex::mem_uncore_retired:local_dram", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x53200f, .fstr = "nhm_ex::MEM_UNCORE_RETIRED:LOCAL_DRAM:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "wsm::offcore_response_0:k", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5201b7, .codes[1] = 0xffff, .fstr = "wsm::OFFCORE_RESPONSE_0:ANY_REQUEST:ANY_RESPONSE:k=1:u=0:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "wsm::offcore_response_0:local_dram", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0x20ff, .fstr = "wsm::OFFCORE_RESPONSE_0:ANY_REQUEST:LOCAL_DRAM:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "wsm::offcore_response_0:PF_IFETCH", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0xff40, .fstr = "wsm::OFFCORE_RESPONSE_0:PF_IFETCH:ANY_RESPONSE:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "wsm::offcore_response_0:ANY_DATA:LOCAL_DRAM", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0x2033, .fstr = "wsm::OFFCORE_RESPONSE_0:DMND_DATA_RD:DMND_RFO:PF_DATA_RD:PF_RFO:LOCAL_DRAM:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "wsm::offcore_response_0:DMND_RFO:DMND_DATA_RD:LOCAL_DRAM:REMOTE_DRAM", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0x6003, .fstr = "wsm::OFFCORE_RESPONSE_0:DMND_DATA_RD:DMND_RFO:LOCAL_DRAM:REMOTE_DRAM:k=1:u=1:e=0:i=0:c=0:t=0" }, { SRC_LINE, .name = "wsm::offcore_response_1:local_dram", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301bb, .codes[1] = 0x20ff, .fstr = "wsm::OFFCORE_RESPONSE_1:ANY_REQUEST:LOCAL_DRAM:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "wsm::offcore_response_1:PF_IFETCH", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301bb, .codes[1] = 0xff40, .fstr = "wsm::OFFCORE_RESPONSE_1:PF_IFETCH:ANY_RESPONSE:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "wsm::offcore_response_1:ANY_DATA:LOCAL_DRAM", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301bb, .codes[1] = 0x2033, .fstr = "wsm::OFFCORE_RESPONSE_1:DMND_DATA_RD:DMND_RFO:PF_DATA_RD:PF_RFO:LOCAL_DRAM:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "wsm::offcore_response_1:DMND_RFO:DMND_DATA_RD:LOCAL_DRAM:REMOTE_DRAM", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301bb, .codes[1] = 0x6003, .fstr = "wsm::OFFCORE_RESPONSE_1:DMND_DATA_RD:DMND_RFO:LOCAL_DRAM:REMOTE_DRAM:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "wsm::offcore_response_0:ANY_LLC_MISS", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0xf8ff, .fstr = "wsm::OFFCORE_RESPONSE_0:ANY_REQUEST:REMOTE_CACHE_HITM:REMOTE_CACHE_FWD:LOCAL_DRAM:REMOTE_DRAM:NON_DRAM:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "wsm_dp::offcore_response_0:ANY_LLC_MISS", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0xf8ff, .fstr = "wsm_dp::OFFCORE_RESPONSE_0:ANY_REQUEST:REMOTE_CACHE_HITM:LOCAL_DRAM_AND_REMOTE_CACHE_HIT:REMOTE_DRAM:OTHER_LLC_MISS:NON_DRAM:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "wsm_dp::offcore_response_0:LOCAL_CACHE", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0x7ff, .fstr = "wsm_dp::OFFCORE_RESPONSE_0:ANY_REQUEST:UNCORE_HIT:OTHER_CORE_HIT_SNP:OTHER_CORE_HITM:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "wsm_dp::offcore_response_0:ANY_CACHE_DRAM", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0x7fff, .fstr = "wsm_dp::OFFCORE_RESPONSE_0:ANY_REQUEST:UNCORE_HIT:OTHER_CORE_HIT_SNP:OTHER_CORE_HITM:REMOTE_CACHE_HITM:LOCAL_DRAM_AND_REMOTE_CACHE_HIT:REMOTE_DRAM:OTHER_LLC_MISS:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "nhm::offcore_response_0:k", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5201b7, .codes[1] = 0xffff, .fstr = "nhm::OFFCORE_RESPONSE_0:ANY_REQUEST:ANY_RESPONSE:k=1:u=0:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "nhm::offcore_response_0:local_dram", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0x40ff, .fstr = "nhm::OFFCORE_RESPONSE_0:ANY_REQUEST:LOCAL_DRAM:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "nhm::offcore_response_0:any_llc_miss", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0xf8ff, .fstr = "nhm::OFFCORE_RESPONSE_0:ANY_REQUEST:REMOTE_CACHE_HITM:REMOTE_CACHE_FWD:REMOTE_DRAM:LOCAL_DRAM:NON_DRAM:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "nhm::offcore_response_0:any_dram", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0x60ff, .fstr = "nhm::OFFCORE_RESPONSE_0:ANY_REQUEST:REMOTE_DRAM:LOCAL_DRAM:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "nhm::offcore_response_0:PF_IFETCH", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0xff40, .fstr = "nhm::OFFCORE_RESPONSE_0:PF_IFETCH:ANY_RESPONSE:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "nhm::offcore_response_0:ANY_DATA:LOCAL_DRAM", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0x4033, .fstr = "nhm::OFFCORE_RESPONSE_0:DMND_DATA_RD:DMND_RFO:PF_DATA_RD:PF_RFO:LOCAL_DRAM:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "nhm::offcore_response_0:DMND_RFO:DMND_DATA_RD:LOCAL_DRAM:REMOTE_DRAM", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0x6003, .fstr = "nhm::OFFCORE_RESPONSE_0:DMND_DATA_RD:DMND_RFO:REMOTE_DRAM:LOCAL_DRAM:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "amd64_k8_revg::DISPATCHED_FPU:0xff:k", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x52ff00ull, .fstr = "amd64_k8_revg::DISPATCHED_FPU:0xff:k=1:u=0:e=0:i=0:c=0" }, { SRC_LINE, .name = "amd64_k8_revg::DISPATCHED_FPU:0x4ff", .ret = PFM_ERR_ATTR, .count = 0, }, { SRC_LINE, .name = "amd64_fam10h_barcelona::DISPATCHED_FPU:0x4ff:u", .ret = PFM_ERR_ATTR }, { SRC_LINE, .name = "amd64_fam10h_barcelona::DISPATCHED_FPU:0xff:u", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x51ff00ull, .fstr = "amd64_fam10h_barcelona::DISPATCHED_FPU:0xff:k=0:u=1:e=0:i=0:c=0:h=0:g=0" }, { SRC_LINE, .name = "wsm::inst_retired:0xff:k", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x52ffc0, .fstr = "wsm::INST_RETIRED:0xff:k=1:u=0:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "wsm::uops_issued:0xff:stall_cycles", .ret = PFM_ERR_ATTR, .count = 0, }, { SRC_LINE, .name = "wsm::uops_issued:0xff:0xf1", .ret = PFM_ERR_ATTR, .count = 0, }, { SRC_LINE, .name = "wsm::uops_issued:0xff=", .ret = PFM_ERR_ATTR_VAL, .count = 0, }, { SRC_LINE, .name = "wsm::uops_issued:123", .ret = PFM_ERR_ATTR, .count = 0, }, { SRC_LINE, .name = "wsm::uops_issued:0xfff", .ret = PFM_ERR_ATTR, .count = 0, }, { SRC_LINE, .name = "netburst::global_power_events", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x2600020f, .codes[1] = 0x3d000, .fstr = "netburst::global_power_events:RUNNING:k=1:u=1:e=0:cmpl=0:thr=0", }, { SRC_LINE, .name = "netburst::global_power_events:RUNNING:u:k", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x2600020f, .codes[1] = 0x3d000, .fstr = "netburst::global_power_events:RUNNING:k=1:u=1:e=0:cmpl=0:thr=0", }, { SRC_LINE, .name = "netburst::global_power_events:RUNNING:e", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x2600020f, .codes[1] = 0x107d000, .fstr = "netburst::global_power_events:RUNNING:k=1:u=1:e=1:cmpl=0:thr=0", }, { SRC_LINE, .name = "netburst::global_power_events:RUNNING:cmpl:e:u", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x26000205, .codes[1] = 0x10fd000, .fstr = "netburst::global_power_events:RUNNING:k=0:u=1:e=1:cmpl=1:thr=0", }, { SRC_LINE, .name = "netburst::global_power_events:RUNNING:cmpl:thr=8:u", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x26000205, .codes[1] = 0x8fd000, .fstr = "netburst::global_power_events:RUNNING:k=0:u=1:e=0:cmpl=1:thr=8", }, { SRC_LINE, .name = "netburst::global_power_events:RUNNING:cmpl:thr=32:u", .ret = PFM_ERR_ATTR_VAL, .count = 0, }, { SRC_LINE, .name = "netburst::instr_completed:nbogus", .ret = PFM_ERR_NOTFOUND, .count = 0, }, { SRC_LINE, .name = "netburst_p::instr_completed:nbogus", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0xe00020f, .codes[1] = 0x39000, .fstr = "netburst_p::instr_completed:NBOGUS:k=1:u=1:e=0:cmpl=0:thr=0", }, { SRC_LINE, .name = "snb::cpl_cycles:ring0_trans:u", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x155015c, .fstr = "snb::CPL_CYCLES:RING0:k=0:u=1:e=1:i=0:c=1:t=0", }, { SRC_LINE, .name = "snb::cpl_cycles:ring0_trans:e=1", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x157015cull, }, { SRC_LINE, .name = "snb::OFFCORE_REQUESTS_OUTSTanding:ALL_DATA_RD_CYCLES", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1530860, .fstr = "snb::OFFCORE_REQUESTS_OUTSTANDING:ALL_DATA_RD:k=1:u=1:e=0:i=0:c=1:t=0", }, { SRC_LINE, .name = "snb::uops_issued:core_stall_cycles:u:k", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1f3010e, .fstr = "snb::UOPS_ISSUED:ANY:k=1:u=1:e=0:i=1:c=1:t=1", }, { SRC_LINE, .name = "snb::LLC_REFERences:k:t=1", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x724f2e, .fstr = "snb::LAST_LEVEL_CACHE_REFERENCES:k=1:u=0:e=0:i=0:c=0:t=1", }, { SRC_LINE, .name = "snb::ITLB:0x1", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x5301ae, .fstr = "snb::ITLB:0x1:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "snb::offcore_response_0:DMND_RFO:ANY_RESPONSE", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0x10002, .fstr = "snb::OFFCORE_RESPONSE_0:DMND_RFO:ANY_RESPONSE:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "snb::offcore_response_0:DMND_RFO:ANY_REQUEST", .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0x18fff, }, { SRC_LINE, .name = "snb::offcore_response_0:DMND_RFO", .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0x10002, .fstr = "snb::OFFCORE_RESPONSE_0:DMND_RFO:ANY_RESPONSE:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "snb::offcore_response_0:any_response", .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0x18fff, .fstr = "snb::OFFCORE_RESPONSE_0:ANY_REQUEST:ANY_RESPONSE:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "snb::offcore_response_0:NO_SUPP:SNP_NONE:PF_RFO:PF_IFETCH", .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0x80020060, .fstr = "snb::OFFCORE_RESPONSE_0:PF_RFO:PF_IFETCH:NO_SUPP:SNP_NONE:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "snb::offcore_response_1:DMND_RFO:ANY_RESPONSE", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301bb, .codes[1] = 0x10002, .fstr = "snb::OFFCORE_RESPONSE_1:DMND_RFO:ANY_RESPONSE:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "snb::offcore_response_1:DMND_RFO:ANY_REQUEST", .count = 2, .codes[0] = 0x5301bb, .codes[1] = 0x18fff, }, { SRC_LINE, .name = "snb::offcore_response_1:DMND_RFO", .count = 2, .codes[0] = 0x5301bb, .codes[1] = 0x10002, .fstr = "snb::OFFCORE_RESPONSE_1:DMND_RFO:ANY_RESPONSE:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "snb::offcore_response_1:any_response", .count = 2, .codes[0] = 0x5301bb, .codes[1] = 0x18fff, .fstr = "snb::OFFCORE_RESPONSE_1:ANY_REQUEST:ANY_RESPONSE:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "snb::offcore_response_1:NO_SUPP:SNP_NONE:PF_RFO:PF_IFETCH", .count = 2, .codes[0] = 0x5301bb, .codes[1] = 0x80020060, .fstr = "snb::OFFCORE_RESPONSE_1:PF_RFO:PF_IFETCH:NO_SUPP:SNP_NONE:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "snb::offcore_response_1:ANY_REQUEST:LLC_MISS_LOCAL_DRAM", .count = 2, .codes[0] = 0x5301bb, .codes[1] = 0x3f80408fffull, .fstr = "snb::OFFCORE_RESPONSE_1:DMND_DATA_RD:DMND_RFO:DMND_IFETCH:WB:PF_DATA_RD:PF_RFO:PF_IFETCH:PF_LLC_DATA_RD:PF_LLC_RFO:PF_LLC_IFETCH:BUS_LOCKS:STRM_ST:OTHER:LLC_MISS_LOCAL_DRAM:SNP_ANY:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "amd64_fam14h_bobcat::MAB_REQUESTS:DC_BUFFER_0", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x530068, .fstr = "amd64_fam14h_bobcat::MAB_REQUESTS:DC_BUFFER_0:k=1:u=1:e=0:i=0:c=0:h=0:g=0", }, { SRC_LINE, .name = "amd64_fam14h_bobcat::MAB_REQUESTS:DC_BUFFER_0:DC_BUFFER_1", .ret = PFM_ERR_FEATCOMB, }, { SRC_LINE, .name = "amd64_fam14h_bobcat::MAB_REQUESTS:DC_BUFFER_0:IC_BUFFER_0", .ret = PFM_ERR_FEATCOMB, }, { SRC_LINE, .name = "amd64_fam14h_bobcat::MAB_REQUESTS:ANY_DC_BUFFER", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x530b68, .fstr = "amd64_fam14h_bobcat::MAB_REQUESTS:ANY_DC_BUFFER:k=1:u=1:e=0:i=0:c=0:h=0:g=0", }, { SRC_LINE, .name = "amd64_fam14h_bobcat::MAB_REQUESTS:ANY_IC_BUFFER", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x530a68, .fstr = "amd64_fam14h_bobcat::MAB_REQUESTS:ANY_IC_BUFFER:k=1:u=1:e=0:i=0:c=0:h=0:g=0", }, { SRC_LINE, .name = "amd64_fam14h_bobcat::MAB_REQUESTS:ANY_IC_BUFFER:IC_BUFFER_1", .ret = PFM_ERR_FEATCOMB, }, { SRC_LINE, .name = "core::INST_RETIRED:ANY_P:e", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "core::INST_RETIRED:ANY_P:e:c=1", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x15700c0ull, }, { SRC_LINE, .name = "atom::INST_RETIRED:ANY_P:e", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x5700c0ull, }, { SRC_LINE, .name = "atom::INST_RETIRED:ANY_P:e:c=1", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x15700c0ull, }, { SRC_LINE, .name = "nhm::INST_RETIRED:ANY_P:e", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "nhm::INST_RETIRED:ANY_P:e:c=1", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x15700c0ull, }, { SRC_LINE, .name = "wsm::INST_RETIRED:ANY_P:e", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "wsm::INST_RETIRED:ANY_P:e:c=1", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x15701c0ull, }, { SRC_LINE, .name = "snb::INST_RETIRED:ANY_P:e", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "snb::INST_RETIRED:ANY_P:e:c=1", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x15700c0ull, }, { SRC_LINE, .name = "snb::INST_RETIRED:ANY_P:e:c=1", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x15700c0ull, }, { SRC_LINE, .name = "snb::offcore_response_0:any_request", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7ull, .codes[1]= 0x18fffull, .fstr = "snb::OFFCORE_RESPONSE_0:DMND_DATA_RD:DMND_RFO:DMND_IFETCH:WB:PF_DATA_RD:PF_RFO:PF_IFETCH:PF_LLC_DATA_RD:PF_LLC_RFO:PF_LLC_IFETCH:BUS_LOCKS:STRM_ST:OTHER:ANY_RESPONSE:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "snb::offcore_response_0:dmnd_data_rd", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7ull, .codes[1]=0x10001ull, .fstr = "snb::OFFCORE_RESPONSE_0:DMND_DATA_RD:ANY_RESPONSE:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "snb::offcore_response_0:dmnd_data_rd:llc_hite", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7ull, .codes[1]=0x3f80080001ull, .fstr = "snb::OFFCORE_RESPONSE_0:DMND_DATA_RD:LLC_HITE:SNP_ANY:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "snb::offcore_response_0:dmnd_data_rd:llc_hite:snp_any", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7ull, .codes[1]=0x3f80080001ull, .fstr = "snb::OFFCORE_RESPONSE_0:DMND_DATA_RD:LLC_HITE:SNP_NONE:SNP_NOT_NEEDED:SNP_MISS:SNP_NO_FWD:SNP_FWD:HITM:NON_DRAM:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "snb::offcore_response_0:dmnd_data_rd:llc_hite:hitm", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7ull, .codes[1]=0x1000080001ull, .fstr = "snb::OFFCORE_RESPONSE_0:DMND_DATA_RD:LLC_HITE:HITM:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "snb::offcore_response_0:dmnd_data_rd:any_response", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7ull, .codes[1]=0x10001ull, .fstr = "snb::OFFCORE_RESPONSE_0:DMND_DATA_RD:ANY_RESPONSE:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "snb::offcore_response_0:dmnd_data_rd:any_response:snp_any", .ret = PFM_ERR_FEATCOMB, }, { SRC_LINE, .name = "snb::offcore_response_0:dmnd_data_rd:any_response:llc_hitmesf", .ret = PFM_ERR_FEATCOMB, }, { SRC_LINE, .name = "snb::offcore_response_0:any_response", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7ull, .codes[1]=0x18fffull, .fstr = "snb::OFFCORE_RESPONSE_0:ANY_REQUEST:ANY_RESPONSE:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "snb::offcore_response_0:l3_miss", .ret = PFM_SUCCESS, .count = 2, .codes[0] =0x5301b7, .codes[1] = 0x3f80408fffull, .fstr = "snb::OFFCORE_RESPONSE_0:ANY_REQUEST:LLC_MISS_LOCAL_DRAM:SNP_ANY:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "amd64_fam11h_turion::MAB_REQUESTS:DC_BUFFER_0", .ret = PFM_ERR_NOTFOUND, }, { SRC_LINE, .name = "amd64_fam11h_turion::RETIRED_INSTRUCTIONS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x5300c0, .fstr = "amd64_fam11h_turion::RETIRED_INSTRUCTIONS:k=1:u=1:e=0:i=0:c=0:h=0:g=0", }, { SRC_LINE, .name = "amd64_fam11h_turion::RETIRED_UOPS:k", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x5200c1, .fstr = "amd64_fam11h_turion::RETIRED_UOPS:k=1:u=0:e=0:i=0:c=0:h=0:g=0", }, { SRC_LINE, .name = "amd64_fam11h_turion::CPU_CLK_UNHALTED", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x530076, .fstr = "amd64_fam11h_turion::CPU_CLK_UNHALTED:k=1:u=1:e=0:i=0:c=0:h=0:g=0", }, { SRC_LINE, .name = "amd64_fam11h_turion::RETIRED_UOPS:c=1:i", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1d300c1, .fstr = "amd64_fam11h_turion::RETIRED_UOPS:k=1:u=1:e=0:i=1:c=1:h=0:g=0", }, { SRC_LINE, .name = "ivb::ARITH:FPU_DIV", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1570414, .fstr = "ivb::ARITH:FPU_DIV:k=1:u=1:e=1:i=0:c=1:t=0", }, { SRC_LINE, .name = "ivb::INST_RETIRED:ALL", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x5301c0, .fstr = "ivb::INST_RETIRED:ALL:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "ivb::INST_RETIRED:ALL:k", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x5201c0, .fstr = "ivb::INST_RETIRED:ALL:k=1:u=0:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "ivb::INST_RETIRED:ALL:u", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x5101c0, .fstr = "ivb::INST_RETIRED:ALL:k=0:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "ivb::TLB_ACCESS:LOAD_STLB_HIT", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x53045f, .fstr = "ivb::DTLB_LOAD_ACCESS:STLB_HIT:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "ivb::TLB_ACCESS:STLB_HIT", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x53045f, .fstr = "ivb::DTLB_LOAD_ACCESS:STLB_HIT:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "ivb::DTLB_LOAD_ACCESS:STLB_HIT", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x53045f, .fstr = "ivb::DTLB_LOAD_ACCESS:STLB_HIT:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "ivb::MOVE_ELIMINATION:INT_NOT_ELIMINATED", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x530158, .fstr = "ivb::MOVE_ELIMINATION:INT_NOT_ELIMINATED:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "ivb::RESOURCE_STALLS:SB:RS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x530ca2, .fstr = "ivb::RESOURCE_STALLS:RS:SB:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "ivb::RESOURCE_STALLS:ROB:RS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x5314a2, .fstr = "ivb::RESOURCE_STALLS:RS:ROB:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "ivb::UOPS_EXECUTED:THREAD", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x5301b1, .fstr = "ivb::UOPS_EXECUTED:THREAD:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "ivb::UOPS_EXECUTED:THREAD:e:c=1", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x15701b1, .fstr = "ivb::UOPS_EXECUTED:THREAD:k=1:u=1:e=1:i=0:c=1:t=0", }, { SRC_LINE, .name = "ivb::UOPS_EXECUTED:THREAD:e", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "ivb::UOPS_EXECUTED:THREAD:c=1:i", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1d301b1, .fstr = "ivb::UOPS_EXECUTED:THREAD:k=1:u=1:e=0:i=1:c=1:t=0", }, { SRC_LINE, .name = "ivb::CPU_CLK_UNHALTED:REF_P", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x53013c, .fstr = "ivb::CPU_CLK_UNHALTED:REF_XCLK:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "ivb::DTLB_LOAD_MISSES:DEMAND_LD_MISS_CAUSES_A_WALK", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x538108, .fstr = "ivb::DTLB_LOAD_MISSES:MISS_CAUSES_A_WALK:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "ivb::offcore_response_0:k", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5201b7, .codes[1] = 0x18fff, .fstr = "ivb::OFFCORE_RESPONSE_0:ANY_REQUEST:ANY_RESPONSE:k=1:u=0:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "ivb::offcore_response_0:LLC_MISS_LOCAL", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0x3f80408fffull, .fstr = "ivb::OFFCORE_RESPONSE_0:ANY_REQUEST:LLC_MISS_LOCAL:SNP_ANY:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "ivb::offcore_response_0:l3_miss", .ret = PFM_SUCCESS, .count = 2, .codes[0] =0x5301b7, .codes[1] = 0x3f80408fffull, .fstr = "ivb::OFFCORE_RESPONSE_0:ANY_REQUEST:LLC_MISS_LOCAL:SNP_ANY:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "ivb::DTLB_LOAD_MISSES:STLB_HIT", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x53045f, .fstr = "ivb::DTLB_LOAD_MISSES:STLB_HIT:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "ivb::DTLB_LOAD_MISSES:LARGE_WALK_COMPLETED:u", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x518808, .fstr = "ivb::DTLB_LOAD_MISSES:LARGE_WALK_COMPLETED:k=0:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "snb::l2_lines_in:i:i=1", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0xd301f1, .fstr = "snb::L2_LINES_IN:I:k=1:u=1:e=0:i=1:c=0:t=0", }, { SRC_LINE, .name = "snb::l2_lines_in:i=1:i", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0xd301f1, .fstr = "snb::L2_LINES_IN:I:k=1:u=1:e=0:i=1:c=0:t=0", }, { SRC_LINE, .name = "snb::l2_lines_in:i:i=0", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x5301f1, .fstr = "snb::L2_LINES_IN:I:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "snb::l2_lines_in:e:e=0", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x5304f1, .fstr = "snb::L2_LINES_IN:E:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "snb::l2_lines_in:e:e=1", .ret = PFM_ERR_ATTR, .count = 0, }, { SRC_LINE, .name = "snb::l2_lines_in:e:e=1:c=10", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0xa5704f1, .fstr = "snb::L2_LINES_IN:E:k=1:u=1:e=1:i=0:c=10:t=0", }, { SRC_LINE, .name = "snb_unc_cbo0::unc_clockticks", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x5000ff, .fstr = "snb_unc_cbo0::UNC_CLOCKTICKS", }, { SRC_LINE, .name = "snb_unc_cbo1::unc_clockticks", .ret = PFM_ERR_NOTFOUND }, { SRC_LINE, .name = "snb_unc_cbo2::unc_clockticks", .ret = PFM_ERR_NOTFOUND }, { SRC_LINE, .name = "snb_unc_cbo3::unc_clockticks", .ret = PFM_ERR_NOTFOUND }, { SRC_LINE, .name = "snb_unc_cbo1::UNC_CBO_CACHE_LOOKUP:STATE_MESI:READ_FILTER:c=1:i", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1d01f34, .fstr = "snb_unc_cbo1::UNC_CBO_CACHE_LOOKUP:STATE_MESI:READ_FILTER:e=0:i=1:c=1", }, { SRC_LINE, .name = "snbep_unc_cbo1::UNC_C_CLOCKTICKS:u", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "snbep_unc_cbo0::UNC_C_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x00, .fstr = "snbep_unc_cbo0::UNC_C_CLOCKTICKS", }, { SRC_LINE, .name = "snbep_unc_cbo0::UNC_C_LLC_LOOKUP:DATA_READ", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x334, .codes[1] = 0x7c0000, .fstr = "snbep_unc_cbo0::UNC_C_LLC_LOOKUP:DATA_READ:STATE_MESIF:e=0:i=0:t=0:tf=0:cf=0", }, { SRC_LINE, .name = "snbep_unc_cbo0::UNC_C_LLC_LOOKUP:ANY", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x1f34, .codes[1] = 0x7c0000, .fstr = "snbep_unc_cbo0::UNC_C_LLC_LOOKUP:ANY:STATE_MESIF:e=0:i=0:t=0:tf=0:cf=0", }, { SRC_LINE, .name = "snbep_unc_cbo0::UNC_C_LLC_LOOKUP:DATA_READ:nf=1", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "snbep_unc_cbo0::UNC_C_LLC_LOOKUP:DATA_READ:tid=1", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "snbep_unc_cbo0::UNC_C_LLC_LOOKUP:NID", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "snbep_unc_cbo0::UNC_C_LLC_LOOKUP:NID:STATE_M", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "snbep_unc_cbo0::UNC_C_LLC_LOOKUP:NID:nf=3", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x4334, .codes[1] = 0x7c0c00, .fstr = "snbep_unc_cbo0::UNC_C_LLC_LOOKUP:DATA_READ:NID:STATE_MESIF:e=0:i=0:t=0:tf=0:cf=0:nf=3", }, { SRC_LINE, .name = "snbep_unc_cbo0::UNC_C_LLC_LOOKUP:NID:STATE_M:nf=3", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x4334, .codes[1] = 0x200c00, .fstr = "snbep_unc_cbo0::UNC_C_LLC_LOOKUP:DATA_READ:NID:STATE_M:e=0:i=0:t=0:tf=0:cf=0:nf=3", }, { SRC_LINE, .name = "snbep_unc_cbo0::UNC_C_LLC_LOOKUP:NID:nf=3:tid=1", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "snbep_unc_cbo0::UNC_C_TOR_INSERTS:OPCODE", .ret = PFM_ERR_UMASK, }, { SRC_LINE, .name = "snbep_unc_cbo0::UNC_C_TOR_INSERTS:WB", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1035, .fstr = "snbep_unc_cbo0::UNC_C_TOR_INSERTS:WB:e=0:i=0:t=0:tf=0:cf=0", }, { SRC_LINE, .name = "snbep_unc_cbo0::UNC_C_TOR_INSERTS:OPCODE:OPC_PCIWILF", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x135, .codes[1] = 0xca000000, .fstr = "snbep_unc_cbo0::UNC_C_TOR_INSERTS:OPCODE:OPC_PCIWILF:e=0:i=0:t=0:tf=0:cf=0", }, { SRC_LINE, .name = "snbep_unc_cbo0::UNC_C_TOR_INSERTS:OPCODE:OPC_PCIWILF:nf=1", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "snbep_unc_cbo0::UNC_C_TOR_INSERTS:NID_OPCODE:OPC_PCIRDCUR:nf=1", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x4135, .codes[1] = 0xcf000400, .fstr = "snbep_unc_cbo0::UNC_C_TOR_INSERTS:NID_OPCODE:OPC_PCIRDCUR:e=0:i=0:t=0:tf=0:cf=0:nf=1", }, { SRC_LINE, .name = "snbep_unc_cbo0::UNC_C_TOR_INSERTS:OPC_RFO:NID_OPCODE:nf=1", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x4135, .codes[1] = 0xc0000400, .fstr = "snbep_unc_cbo0::UNC_C_TOR_INSERTS:NID_OPCODE:OPC_RFO:e=0:i=0:t=0:tf=0:cf=0:nf=1", }, { SRC_LINE, .name = "snbep_unc_ha::UNC_H_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x0, .fstr = "snbep_unc_ha::UNC_H_CLOCKTICKS:e=0:i=0:t=0", }, { SRC_LINE, .name = "snbep_unc_ha::UNC_H_REQUESTS:READS:t=1", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1000301, .fstr = "snbep_unc_ha::UNC_H_REQUESTS:READS:e=0:i=0:t=1", }, { SRC_LINE, .name = "snbep_unc_imc0::UNC_M_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0xff, .fstr = "snbep_unc_imc0::UNC_M_CLOCKTICKS", }, { SRC_LINE, .name = "snbep_unc_imc0::UNC_M_CLOCKTICKS:t=1", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "snbep_unc_imc0::UNC_M_CAS_COUNT:RD", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x0304, .fstr = "snbep_unc_imc0::UNC_M_CAS_COUNT:RD:e=0:i=0:t=0", }, { SRC_LINE, .name = "snbep_unc_imc0::UNC_M_POWER_CKE_CYCLES:RANK0", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x183, .fstr = "snbep_unc_imc0::UNC_M_POWER_CKE_CYCLES:RANK0:e=0:i=0:t=0", }, { SRC_LINE, .name = "snbep_unc_imc0::UNC_M_CAS_COUNT:WR", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0xc04, .fstr = "snbep_unc_imc0::UNC_M_CAS_COUNT:WR:e=0:i=0:t=0", }, { SRC_LINE, .name = "snbep_unc_pcu::UNC_P_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x0, .fstr = "snbep_unc_pcu::UNC_P_CLOCKTICKS:e=0:i=0:t=0", }, { SRC_LINE, .name = "snbep_unc_pcu::UNC_P_CLOCKTICKS:t=1", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1000000, .fstr = "snbep_unc_pcu::UNC_P_CLOCKTICKS:e=0:i=0:t=1", }, { SRC_LINE, .name = "snbep_unc_pcu::UNC_P_CORE0_TRANSITION_CYCLES", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x200003, .fstr = "snbep_unc_pcu::UNC_P_CORE0_TRANSITION_CYCLES:e=0:i=0:t=0", }, { SRC_LINE, .name = "snbep_unc_pcu::UNC_P_FREQ_BAND0_CYCLES", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "snbep_unc_pcu::UNC_P_FREQ_BAND1_CYCLES", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "snbep_unc_pcu::UNC_P_FREQ_BAND2_CYCLES", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "snbep_unc_pcu::UNC_P_FREQ_BAND3_CYCLES", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "snbep_unc_pcu::UNC_P_FREQ_BAND0_CYCLES:ff=32", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0xb, .codes[1] = 0x20, .fstr = "snbep_unc_pcu::UNC_P_FREQ_BAND0_CYCLES:e=0:i=0:t=0:ff=32", }, { SRC_LINE, .name = "snbep_unc_pcu::UNC_P_FREQ_BAND1_CYCLES:ff=16", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0xc, .codes[1] = 0x1000, .fstr = "snbep_unc_pcu::UNC_P_FREQ_BAND1_CYCLES:e=0:i=0:t=0:ff=16", }, { SRC_LINE, .name = "snbep_unc_pcu::UNC_P_FREQ_BAND2_CYCLES:ff=8", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0xd, .codes[1] = 0x80000, .fstr = "snbep_unc_pcu::UNC_P_FREQ_BAND2_CYCLES:e=0:i=0:t=0:ff=8", }, { SRC_LINE, .name = "snbep_unc_pcu::UNC_P_FREQ_BAND3_CYCLES:ff=40", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0xe, .codes[1] = 0x28000000, .fstr = "snbep_unc_pcu::UNC_P_FREQ_BAND3_CYCLES:e=0:i=0:t=0:ff=40", }, { SRC_LINE, .name = "snbep_unc_pcu::UNC_P_FREQ_BAND0_CYCLES:ff=32:e", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x4000b, .codes[1] = 0x20, .fstr = "snbep_unc_pcu::UNC_P_FREQ_BAND0_CYCLES:e=1:i=0:t=0:ff=32", }, { SRC_LINE, .name = "snbep_unc_pcu::UNC_P_FREQ_BAND0_CYCLES:ff=32:i", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x80000b, .codes[1] = 0x20, .fstr = "snbep_unc_pcu::UNC_P_FREQ_BAND0_CYCLES:e=0:i=1:t=0:ff=32", }, { SRC_LINE, .name = "snbep_unc_pcu::UNC_P_FREQ_BAND0_CYCLES:ff=32:e:i", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x84000b, .codes[1] = 0x20, .fstr = "snbep_unc_pcu::UNC_P_FREQ_BAND0_CYCLES:e=1:i=1:t=0:ff=32", }, { SRC_LINE, .name = "snbep_unc_pcu::UNC_P_FREQ_BAND0_CYCLES:ff=32:e:i:t=4", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x484000b, .codes[1] = 0x20, .fstr = "snbep_unc_pcu::UNC_P_FREQ_BAND0_CYCLES:e=1:i=1:t=4:ff=32", }, { SRC_LINE, .name = "SNBEP_UNC_PCU::UNC_P_POWER_STATE_OCCUPANCY:CORES_C0", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x4080, .fstr = "snbep_unc_pcu::UNC_P_POWER_STATE_OCCUPANCY:CORES_C0:e=0:i=0:t=0" }, { SRC_LINE, .name = "SNBEP_UNC_PCU::UNC_P_POWER_STATE_OCCUPANCY:CORES_C3", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x8080, .fstr = "snbep_unc_pcu::UNC_P_POWER_STATE_OCCUPANCY:CORES_C3:e=0:i=0:t=0", }, { SRC_LINE, .name = "SNBEP_UNC_PCU::UNC_P_POWER_STATE_OCCUPANCY:CORES_C6", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0xc080, .fstr = "snbep_unc_pcu::UNC_P_POWER_STATE_OCCUPANCY:CORES_C6:e=0:i=0:t=0" }, { SRC_LINE, .name = "SNBEP_UNC_PCU::UNC_P_POWER_STATE_OCCUPANCY:CORES_C0:i", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x40004080, .fstr = "snbep_unc_pcu::UNC_P_POWER_STATE_OCCUPANCY:CORES_C0:e=0:i=1:t=0" }, { SRC_LINE, .name = "snbep_unc_qpi0::UNC_Q_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x14, .fstr = "snbep_unc_qpi0::UNC_Q_CLOCKTICKS:e=0:i=0:t=0", }, { SRC_LINE, .name = "snbep_unc_qpi0::UNC_Q_RXL_FLITS_G0:DATA", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x201, .fstr = "snbep_unc_qpi0::UNC_Q_RXL_FLITS_G0:DATA:e=0:i=0:t=0", }, { SRC_LINE, .name = "snbep_unc_qpi0::UNC_Q_RXL_FLITS_G0:IDLE:t=1:i", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1800101, .fstr = "snbep_unc_qpi0::UNC_Q_RXL_FLITS_G0:IDLE:e=0:i=1:t=1", }, { SRC_LINE, .name = "snbep_unc_qpi0::UNC_Q_TXL_FLITS_G0:DATA", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x200, .fstr = "snbep_unc_qpi0::UNC_Q_TXL_FLITS_G0:DATA:e=0:i=0:t=0", }, { SRC_LINE, .name = "snbep_unc_qpi0::UNC_Q_RXL_FLITS_G1:HOM", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x200602, .fstr = "snbep_unc_qpi0::UNC_Q_RXL_FLITS_G1:HOM:e=0:i=0:t=0", }, { SRC_LINE, .name = "snbep_unc_qpi0::UNC_Q_TXL_FLITS_G1:HOM", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x200600, .fstr = "snbep_unc_qpi0::UNC_Q_TXL_FLITS_G1:HOM:e=0:i=0:t=0", }, { SRC_LINE, .name = "snbep_unc_ubo::UNC_U_LOCK_CYCLES", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x44, .fstr = "snbep_unc_ubo::UNC_U_LOCK_CYCLES:e=0:i=0:t=0", }, { SRC_LINE, .name = "snbep_unc_r2pcie::UNC_R2_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1, .fstr = "snbep_unc_r2pcie::UNC_R2_CLOCKTICKS:e=0:i=0:t=0", }, { SRC_LINE, .name = "snbep_unc_r2pcie::UNC_R2_RING_AD_USED:ANY", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0xf07, .fstr = "snbep_unc_r2pcie::UNC_R2_RING_AD_USED:ANY:e=0:i=0:t=0", }, { SRC_LINE, .name = "snbep_unc_r3qpi0::UNC_R3_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1, .fstr = "snbep_unc_r3qpi0::UNC_R3_CLOCKTICKS:e=0:i=0:t=0", }, { SRC_LINE, .name = "snbep_unc_r3qpi0::UNC_R3_TXR_CYCLES_FULL:e=0:i=0:t=0", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x25, .fstr = "snbep_unc_r3qpi0::UNC_R3_TXR_CYCLES_FULL:e=0:i=0:t=0", }, { SRC_LINE, .name = "snbep_unc_r3qpi1::UNC_R3_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1, .fstr = "snbep_unc_r3qpi1::UNC_R3_CLOCKTICKS:e=0:i=0:t=0", }, { SRC_LINE, .name = "snbep_unc_r3qpi1::UNC_R3_TXR_CYCLES_FULL:e=0:i=0:t=0", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x25, .fstr = "snbep_unc_r3qpi1::UNC_R3_TXR_CYCLES_FULL:e=0:i=0:t=0", }, { SRC_LINE, .name = "knc::cpu_clk_unhalted", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x53002a, .fstr = "knc::CPU_CLK_UNHALTED:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "knc::instructions_executed", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x530016, .fstr = "knc::INSTRUCTIONS_EXECUTED:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "knc::vpu_data_read", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x532000, .fstr = "knc::VPU_DATA_READ:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "knc::vpu_data_read:t:c=1:i", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1f32000, .fstr = "knc::VPU_DATA_READ:k=1:u=1:e=0:i=1:c=1:t=1", }, { SRC_LINE, .name = "snb_ep::cpl_cycles:ring0_trans:u", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x155015c, .fstr = "snb_ep::CPL_CYCLES:RING0:k=0:u=1:e=1:i=0:c=1:t=0", }, { SRC_LINE, .name = "snb_ep::cycle_activity:0x6:c=6", .count = 1, .codes[0] = 0x65306a3, .fstr = "snb_ep::CYCLE_ACTIVITY:0x6:k=1:u=1:e=0:i=0:c=6:t=0", }, { SRC_LINE, .name = "snb_ep::cpl_cycles:ring0_trans:e=1", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x157015cull, }, { SRC_LINE, .name = "snb_ep::OFFCORE_REQUESTS_OUTSTanding:ALL_DATA_RD_CYCLES", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1530860, .fstr = "snb_ep::OFFCORE_REQUESTS_OUTSTANDING:ALL_DATA_RD:k=1:u=1:e=0:i=0:c=1:t=0", }, { SRC_LINE, .name = "snb_ep::uops_issued:core_stall_cycles:u:k", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1f3010e, .fstr = "snb_ep::UOPS_ISSUED:ANY:k=1:u=1:e=0:i=1:c=1:t=1", }, { SRC_LINE, .name = "snb_ep::LLC_REFERences:k:t=1", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x724f2e, .fstr = "snb_ep::LAST_LEVEL_CACHE_REFERENCES:k=1:u=0:e=0:i=0:c=0:t=1", }, { SRC_LINE, .name = "snb_ep::ITLB:0x1", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x5301ae, .fstr = "snb_ep::ITLB:0x1:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "snb_ep::mem_load_uops_llc_miss_retired:local_dram", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x5301d3, .fstr = "snb_ep::MEM_LOAD_UOPS_LLC_MISS_RETIRED:LOCAL_DRAM:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "snb_ep::mem_load_uops_llc_miss_retired:remote_dram", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x5304d3, .fstr = "snb_ep::MEM_LOAD_UOPS_LLC_MISS_RETIRED:REMOTE_DRAM:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "snb_ep::offcore_response_0:DMND_RFO:ANY_RESPONSE", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0x10002, .fstr = "snb_ep::OFFCORE_RESPONSE_0:DMND_RFO:ANY_RESPONSE:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "snb_ep::offcore_response_0:DMND_RFO:ANY_REQUEST", .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0x18fff, }, { SRC_LINE, .name = "snb_ep::offcore_response_0:DMND_RFO", .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0x10002, .fstr = "snb_ep::OFFCORE_RESPONSE_0:DMND_RFO:ANY_RESPONSE:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "snb_ep::offcore_response_0:any_response", .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0x18fff, .fstr = "snb_ep::OFFCORE_RESPONSE_0:ANY_REQUEST:ANY_RESPONSE:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "snb_ep::offcore_response_0:NO_SUPP:SNP_NONE:PF_RFO:PF_IFETCH", .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0x80020060, .fstr = "snb_ep::OFFCORE_RESPONSE_0:PF_RFO:PF_IFETCH:NO_SUPP:SNP_NONE:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "snb_ep::offcore_response_1:DMND_RFO:ANY_RESPONSE", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301bb, .codes[1] = 0x10002, .fstr = "snb_ep::OFFCORE_RESPONSE_1:DMND_RFO:ANY_RESPONSE:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "snb_ep::offcore_response_1:DMND_RFO:ANY_REQUEST", .count = 2, .codes[0] = 0x5301bb, .codes[1] = 0x18fff, }, { SRC_LINE, .name = "snb_ep::offcore_response_1:DMND_RFO", .count = 2, .codes[0] = 0x5301bb, .codes[1] = 0x10002, .fstr = "snb_ep::OFFCORE_RESPONSE_1:DMND_RFO:ANY_RESPONSE:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "snb_ep::offcore_response_1:any_response", .count = 2, .codes[0] = 0x5301bb, .codes[1] = 0x18fff, .fstr = "snb_ep::OFFCORE_RESPONSE_1:ANY_REQUEST:ANY_RESPONSE:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "snb_ep::offcore_response_1:NO_SUPP:SNP_NONE:PF_RFO:PF_IFETCH", .count = 2, .codes[0] = 0x5301bb, .codes[1] = 0x80020060, .fstr = "snb_ep::OFFCORE_RESPONSE_1:PF_RFO:PF_IFETCH:NO_SUPP:SNP_NONE:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "snb_ep::offcore_response_1:ANY_REQUEST:LLC_MISS_LOCAL_DRAM", .count = 2, .codes[0] = 0x5301bb, .codes[1] = 0x3f80408fffull, .fstr = "snb_ep::OFFCORE_RESPONSE_1:DMND_DATA_RD:DMND_RFO:DMND_IFETCH:WB:PF_DATA_RD:PF_RFO:PF_IFETCH:PF_LLC_DATA_RD:PF_LLC_RFO:PF_LLC_IFETCH:BUS_LOCKS:STRM_ST:OTHER:LLC_MISS_LOCAL_DRAM:SNP_ANY:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "snb_ep::offcore_response_1:ANY_REQUEST:LLC_MISS_REMOTE_DRAM", .count = 2, .codes[0] = 0x5301bb, .codes[1] = 0x3fff808fffull, .fstr = "snb_ep::OFFCORE_RESPONSE_1:DMND_DATA_RD:DMND_RFO:DMND_IFETCH:WB:PF_DATA_RD:PF_RFO:PF_IFETCH:PF_LLC_DATA_RD:PF_LLC_RFO:PF_LLC_IFETCH:BUS_LOCKS:STRM_ST:OTHER:LLC_MISS_REMOTE_DRAM:SNP_ANY:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "snb_ep::offcore_response_0:l3_miss", .ret = PFM_SUCCESS, .count = 2, .codes[0] =0x5301b7, .codes[1] = 0x3fffc08fffull, .fstr = "snb_ep::OFFCORE_RESPONSE_0:ANY_REQUEST:LLC_MISS_LOCAL_DRAM:LLC_MISS_REMOTE_DRAM:SNP_ANY:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "snb_ep::mem_trans_retired:latency_above_threshold", .ret = PFM_SUCCESS, .count = 2, .codes[0]=0x5301cd, .codes[1] = 3, .fstr = "snb_ep::MEM_TRANS_RETIRED:LATENCY_ABOVE_THRESHOLD:k=1:u=1:e=0:i=0:c=0:t=0:ldlat=3", }, { SRC_LINE, .name = "snb_ep::mem_trans_retired:latency_above_threshold:ldlat=2", .ret = PFM_ERR_ATTR_VAL, }, { SRC_LINE, .name = "snb_ep::mem_trans_retired:latency_above_threshold:ldlat=3", .ret = PFM_SUCCESS, .count = 2, .codes[0]=0x5301cd, .codes[1] = 3, .fstr = "snb_ep::MEM_TRANS_RETIRED:LATENCY_ABOVE_THRESHOLD:k=1:u=1:e=0:i=0:c=0:t=0:ldlat=3", }, { SRC_LINE, .name = "snb_ep::mem_trans_retired:latency_above_threshold:ldlat=1000000", .ret = PFM_ERR_ATTR_VAL, }, { SRC_LINE, .name = "snb::mem_trans_retired:latency_above_threshold", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301cd, .codes[1] = 3, .fstr = "snb::MEM_TRANS_RETIRED:LATENCY_ABOVE_THRESHOLD:k=1:u=1:e=0:i=0:c=0:t=0:ldlat=3", }, { SRC_LINE, .name = "snb::mem_trans_retired:latency_above_threshold:ldlat=2", .ret = PFM_ERR_ATTR_VAL, }, { SRC_LINE, .name = "snb::mem_trans_retired:latency_above_threshold:ldlat=3", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301cd, .codes[1] = 3, .fstr = "snb::MEM_TRANS_RETIRED:LATENCY_ABOVE_THRESHOLD:k=1:u=1:e=0:i=0:c=0:t=0:ldlat=3", }, { SRC_LINE, .name = "snb::mem_trans_retired:latency_above_threshold:ldlat=1000000", .ret = PFM_ERR_ATTR_VAL, }, { SRC_LINE, .name = "snb::cycle_activity:0x6:c=6", .count = 1, .codes[0] = 0x65306a3, .fstr = "snb::CYCLE_ACTIVITY:0x6:k=1:u=1:e=0:i=0:c=6:t=0", }, { SRC_LINE, .name = "ivb::mem_trans_retired:latency_above_threshold", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301cd, .codes[1] = 3, .fstr = "ivb::MEM_TRANS_RETIRED:LATENCY_ABOVE_THRESHOLD:k=1:u=1:e=0:i=0:c=0:t=0:ldlat=3", }, { SRC_LINE, .name = "ivb::mem_trans_retired:latency_above_threshold:ldlat=2", .ret = PFM_ERR_ATTR_VAL, }, { SRC_LINE, .name = "ivb::mem_trans_retired:latency_above_threshold:ldlat=3:u", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5101cd, .codes[1] = 3, .fstr = "ivb::MEM_TRANS_RETIRED:LATENCY_ABOVE_THRESHOLD:k=0:u=1:e=0:i=0:c=0:t=0:ldlat=3", }, { SRC_LINE, .name = "ivb::mem_trans_retired:latency_above_threshold:ldlat=1000000", .ret = PFM_ERR_ATTR_VAL, }, { SRC_LINE, .name = "nhm::mem_inst_retired:latency_above_threshold", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x53100b, .codes[1] = 3, .fstr = "nhm::MEM_INST_RETIRED:LATENCY_ABOVE_THRESHOLD:k=1:u=1:e=0:i=0:c=0:t=0:ldlat=3", }, { SRC_LINE, .name = "nhm::mem_inst_retired:latency_above_threshold:ldlat=2", .ret = PFM_ERR_ATTR_VAL, }, { SRC_LINE, .name = "nhm::mem_inst_retired:latency_above_threshold:ldlat=3", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x53100b, .codes[1] = 3, .fstr = "nhm::MEM_INST_RETIRED:LATENCY_ABOVE_THRESHOLD:k=1:u=1:e=0:i=0:c=0:t=0:ldlat=3", }, { SRC_LINE, .name = "nhm::mem_inst_retired:latency_above_threshold:ldlat=1000000", .ret = PFM_ERR_ATTR_VAL, }, { SRC_LINE, .name = "wsm::mem_inst_retired:latency_above_threshold", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x53100b, .codes[1] = 3, .fstr = "wsm::MEM_INST_RETIRED:LATENCY_ABOVE_THRESHOLD:k=1:u=1:e=0:i=0:c=0:t=0:ldlat=3", }, { SRC_LINE, .name = "wsm::mem_inst_retired:latency_above_threshold:ldlat=2", .ret = PFM_ERR_ATTR_VAL, }, { SRC_LINE, .name = "wsm::mem_inst_retired:latency_above_threshold:ldlat=3", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x53100b, .codes[1] = 3, .fstr = "wsm::MEM_INST_RETIRED:LATENCY_ABOVE_THRESHOLD:k=1:u=1:e=0:i=0:c=0:t=0:ldlat=3", }, { SRC_LINE, .name = "wsm::mem_inst_retired:latency_above_threshold:ldlat=1000000", .ret = PFM_ERR_ATTR_VAL, }, { SRC_LINE, .name = "amd64_fam15h_interlagos::LINK_TRANSMIT_BANDWIDTH_LINK_0:NOP_DW_SENT", .ret = PFM_ERR_NOTFOUND, /* event in Northbridge PMU */ }, { SRC_LINE, .name = "amd64_fam15h_nb::LINK_TRANSMIT_BANDWIDTH_LINK_0:NOP_DW_SENT", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x5308f6, .fstr = "amd64_fam15h_nb::LINK_TRANSMIT_BANDWIDTH_LINK_0:NOP_DW_SENT:SUBLINK_0", }, { SRC_LINE, .name = "amd64_fam15h_nb::LINK_TRANSMIT_BANDWIDTH_LINK_0:ALL", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x533ff6, .fstr = "amd64_fam15h_nb::LINK_TRANSMIT_BANDWIDTH_LINK_0:ALL:SUBLINK_0", }, { SRC_LINE, .name = "amd64_fam15h_nb::LINK_TRANSMIT_BANDWIDTH_LINK_0:ALL:SUBLINK_1", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x53bff6, .fstr = "amd64_fam15h_nb::LINK_TRANSMIT_BANDWIDTH_LINK_0:ALL:SUBLINK_1", }, { SRC_LINE, .name = "amd64_fam15h_nb::LINK_TRANSMIT_BANDWIDTH_LINK_0:COMMAND_DW_SENT:DATA_DW_SENT", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x5303f6, .fstr = "amd64_fam15h_nb::LINK_TRANSMIT_BANDWIDTH_LINK_0:COMMAND_DW_SENT:DATA_DW_SENT:SUBLINK_0", }, { SRC_LINE, .name = "amd64_fam15h_interlagos::DISPATCHED_FPU_OPS:0x4ff:u", .ret = PFM_ERR_ATTR }, { SRC_LINE, .name = "amd64_fam15h_interlagos::DISPATCHED_FPU_OPS:0xff:u", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x51ff00ull, .fstr = "amd64_fam15h_interlagos::DISPATCHED_FPU_OPS:0xff:k=0:u=1:e=0:i=0:c=0:h=0:g=0" }, { SRC_LINE, .name = "amd64_fam15h_nb::READ_REQUEST_TO_L3_CACHE:read_block_modify:core_3", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x4005334e0ull, .fstr = "amd64_fam15h_nb::READ_REQUEST_TO_L3_CACHE:READ_BLOCK_MODIFY:CORE_3", }, { SRC_LINE, .name = "amd64_fam15h_nb::READ_REQUEST_TO_L3_CACHE", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x40053f7e0ull, .fstr = "amd64_fam15h_nb::READ_REQUEST_TO_L3_CACHE:READ_BLOCK_ANY:ANY_CORE", }, { SRC_LINE, .name = "amd64_fam15h_nb::READ_REQUEST_TO_L3_CACHE:READ_BLOCK_EXCLUSIVE:PREFETCH:READ_BLOCK_MODIFY:core_4", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x400534de0ull, .fstr = "amd64_fam15h_nb::READ_REQUEST_TO_L3_CACHE:READ_BLOCK_EXCLUSIVE:READ_BLOCK_MODIFY:PREFETCH:CORE_4", }, { SRC_LINE, .name = "amd64_fam15h_nb::READ_REQUEST_TO_L3_CACHE:read_block_any:prefetch:core_1", .ret = PFM_ERR_FEATCOMB, /* must use individual umasks to combine with prefetch */ }, { SRC_LINE, .name = "amd64_fam15h_nb::READ_REQUEST_TO_L3_CACHE:read_block_any:prefetch:core_1:core_3", .ret = PFM_ERR_FEATCOMB, /* core umasks cannot be combined */ }, { SRC_LINE, .name = "amd64_fam15h_nb::READ_REQUEST_TO_L3_CACHE:prefetch:core_0", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x4005308e0ull, .fstr = "amd64_fam15h_nb::READ_REQUEST_TO_L3_CACHE:PREFETCH:CORE_0", }, { SRC_LINE, .name = "ivb_ep::mem_load_uops_llc_miss_retired:local_dram", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x5301d3, .fstr = "ivb_ep::MEM_LOAD_UOPS_LLC_MISS_RETIRED:LOCAL_DRAM:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "ivb_ep::mem_load_uops_llc_miss_retired:remote_dram", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x530cd3, .fstr = "ivb_ep::MEM_LOAD_UOPS_LLC_MISS_RETIRED:REMOTE_DRAM:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "ivb_ep::mem_load_uops_llc_miss_retired:remote_hitm", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x5310d3, .fstr = "ivb_ep::MEM_LOAD_UOPS_LLC_MISS_RETIRED:REMOTE_HITM:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "ivb_ep::mem_load_uops_llc_miss_retired:remote_fwd", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x5320d3, .fstr = "ivb_ep::MEM_LOAD_UOPS_LLC_MISS_RETIRED:REMOTE_FWD:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "ivb::mem_load_uops_llc_miss_retired:remote_dram", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "ivb::cycle_activity:0x6:c=6", .count = 1, .codes[0] = 0x65306a3, .fstr = "ivb::CYCLE_ACTIVITY:0x6:k=1:u=1:e=0:i=0:c=6:t=0", }, { SRC_LINE, .name = "ivb_ep::offcore_response_0:any_request:LLC_MISS_REMOTE", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0x3fff808fffULL, .fstr = "ivb_ep::OFFCORE_RESPONSE_0:DMND_DATA_RD:DMND_RFO:DMND_IFETCH:WB:PF_DATA_RD:PF_RFO:PF_IFETCH:PF_LLC_DATA_RD:PF_LLC_RFO:PF_LLC_IFETCH:BUS_LOCKS:STRM_ST:OTHER:LLC_MISS_REMOTE_DRAM:SNP_ANY:k=1:u=1:e=0:i=0:c=0:t=0" }, { SRC_LINE, .name = "ivb_ep::offcore_response_0:l3_miss", .ret = PFM_SUCCESS, .count = 2, .codes[0] =0x5301b7, .codes[1] = 0x3fffc08fffull, .fstr = "ivb_ep::OFFCORE_RESPONSE_0:ANY_REQUEST:LLC_MISS_LOCAL:LLC_MISS_REMOTE_DRAM:SNP_ANY:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "hsw::mem_trans_retired:latency_above_threshold:ldlat=3:u", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5101cd, .codes[1] = 3, .fstr = "hsw::MEM_TRANS_RETIRED:LOAD_LATENCY:k=0:u=1:e=0:i=0:c=0:t=0:ldlat=3:intx=0:intxcp=0", }, { SRC_LINE, .name = "hsw::mem_trans_retired:latency_above_threshold:ldlat=1000000", .ret = PFM_ERR_ATTR_VAL, }, { SRC_LINE, .name = "hsw::mem_trans_retired:load_latency", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301cd, .codes[1] = 3, .fstr = "hsw::MEM_TRANS_RETIRED:LOAD_LATENCY:k=1:u=1:e=0:i=0:c=0:t=0:ldlat=3:intx=0:intxcp=0", }, { SRC_LINE, .name = "hsw::mem_trans_retired:load_latency:ldlat=1000000", .ret = PFM_ERR_ATTR_VAL, }, { SRC_LINE, .name = "hsw::mem_trans_retired:latency_above_threshold:ldlat=2:intx=0:intxcp=0", .ret = PFM_ERR_ATTR_VAL, }, { SRC_LINE, .name = "hsw::inst_Retired:any_p:intx", .count = 1, .codes[0] = 0x1005300c0ull, .fstr = "hsw::INST_RETIRED:ANY_P:k=1:u=1:e=0:i=0:c=0:t=0:intx=1:intxcp=0", }, { SRC_LINE, .name = "hsw::inst_Retired:any_p:intx:intxcp", .count = 1, .codes[0] = 0x3005300c0ull, .fstr = "hsw::INST_RETIRED:ANY_P:k=1:u=1:e=0:i=0:c=0:t=0:intx=1:intxcp=1", }, { SRC_LINE, .name = "hsw::inst_Retired:any_p:intx=0:intxcp", .count = 1, .codes[0] = 0x2005300c0ull, .fstr = "hsw::INST_RETIRED:ANY_P:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=1", }, { SRC_LINE, .name = "hsw::cycle_activity:cycles_l2_pending", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x15301a3, .fstr = "hsw::CYCLE_ACTIVITY:CYCLES_L2_PENDING:k=1:u=1:e=0:i=0:c=1:t=0:intx=0:intxcp=0", }, { SRC_LINE, .name = "hsw::cycle_activity:cycles_l2_pending:c=8", .ret = PFM_ERR_ATTR_SET }, { SRC_LINE, .name = "hsw::hle_retired:aborted", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x5304c8, .fstr = "hsw::HLE_RETIRED:ABORTED:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0", }, { SRC_LINE, .name = "hsw::rtm_retired:aborted", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x5304c9, .fstr = "hsw::RTM_RETIRED:ABORTED:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0", }, { SRC_LINE, .name = "hsw::offcore_response_0:k:intx=1", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x1005201b7ull, .codes[1] = 0x18fff, .fstr = "hsw::OFFCORE_RESPONSE_0:ANY_REQUEST:ANY_RESPONSE:k=1:u=0:e=0:i=0:c=0:t=0:intx=1:intxcp=0", }, { SRC_LINE, .name = "hsw::offcore_response_0:any_request", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0x18fff, .fstr = "hsw::OFFCORE_RESPONSE_0:DMND_DATA_RD:DMND_RFO:DMND_CODE_RD:WB:PF_DATA_RD:PF_RFO:PF_CODE_RD:PF_L3_DATA_RD:PF_L3_RFO:PF_L3_CODE_RD:SPLIT_LOCK_UC_LOCK:STRM_ST:OTHER:ANY_RESPONSE:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0", }, { SRC_LINE, .name = "hsw::offcore_response_0:any_request:any_response:L3_MISS_LOCAL", .ret = PFM_ERR_FEATCOMB, }, { SRC_LINE, .name = "hsw::offcore_response_0:split_lock_uc_lock", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0x10400, .fstr = "hsw::OFFCORE_RESPONSE_0:SPLIT_LOCK_UC_LOCK:ANY_RESPONSE:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0", }, { SRC_LINE, .name = "hsw::offcore_response_0:any_ifetch", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0x10240, .fstr = "hsw::OFFCORE_RESPONSE_0:ANY_IFETCH:ANY_RESPONSE:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0", }, { SRC_LINE, .name = "hsw::offcore_response_0:L3_HITF", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "hsw::offcore_response_0:LLC_MISS_LOCAL", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "hsw::offcore_response_0:L3_HIT:u", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5101b7, .codes[1] = 0x3f801c8fffull, .fstr = "hsw::OFFCORE_RESPONSE_0:ANY_REQUEST:L3_HITM:L3_HITE:L3_HITS:SNP_ANY:k=0:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0", }, { SRC_LINE, .name = "hsw::offcore_response_0:ANY_DATA", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0x10091, .fstr = "hsw::OFFCORE_RESPONSE_0:DMND_DATA_RD:PF_DATA_RD:PF_L3_DATA_RD:ANY_RESPONSE:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0", }, { SRC_LINE, .name = "hsw::offcore_response_0:DMND_DATA_RD:L3_HITS:SNP_FWD", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0x800100001ull, .fstr = "hsw::OFFCORE_RESPONSE_0:DMND_DATA_RD:L3_HITS:SNP_FWD:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0", }, { SRC_LINE, .name = "hsw::offcore_response_0:l3_miss", .ret = PFM_SUCCESS, .count = 2, .codes[0] =0x5301b7, .codes[1] = 0x3f80408fffull, .fstr = "hsw::OFFCORE_RESPONSE_0:ANY_REQUEST:L3_MISS_LOCAL:SNP_ANY:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0", }, { SRC_LINE, .name = "ivb_unc_cbo0::unc_clockticks", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x5000ff, .fstr = "ivb_unc_cbo0::UNC_CLOCKTICKS", }, { SRC_LINE, .name = "ivb_unc_cbo1::unc_clockticks", .ret = PFM_ERR_NOTFOUND }, /* * RAPL note: * we can only use the PKG event because it is the only one available * on all processors. The GPU is client only, the CORES is only certain early CPUs */ { SRC_LINE, .name = "rapl::rapl_energy_pkg", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x2, .fstr = "rapl::RAPL_ENERGY_PKG", }, { SRC_LINE, .name = "rapl::rapl_energy_pkg:u", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "slm::offcore_response_0:snp_hitm", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1]=0x100001ffffull, .fstr = "slm::OFFCORE_RESPONSE_0:ANY_REQUEST:ANY_RESPONSE:SNP_HITM:k=1:u=1:e=0:i=0:c=0", }, { SRC_LINE, .name = "slm::offcore_response_0:any_data", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1]=0x12011, .fstr = "slm::OFFCORE_RESPONSE_0:DMND_DATA_RD:PF_L2_DATA_RD:PF_L1_DATA_RD:ANY_RESPONSE:k=1:u=1:e=0:i=0:c=0", }, { SRC_LINE, .name = "slm::offcore_response_0:uc_ifetch", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1]=0x10200, .fstr = "slm::OFFCORE_RESPONSE_0:UC_IFETCH:ANY_RESPONSE:k=1:u=1:e=0:i=0:c=0", }, { SRC_LINE, .name = "slm::offcore_response_0:any_ifetch", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1]=0x10244, .fstr = "slm::OFFCORE_RESPONSE_0:DMND_IFETCH:PF_IFETCH:UC_IFETCH:ANY_RESPONSE:k=1:u=1:e=0:i=0:c=0", }, { SRC_LINE, .name = "slm::offcore_response_1:snp_hitm", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5302b7, .codes[1]=0x100001ffffull, .fstr = "slm::OFFCORE_RESPONSE_1:ANY_REQUEST:ANY_RESPONSE:SNP_HITM:k=1:u=1:e=0:i=0:c=0", }, { SRC_LINE, .name = "slm::offcore_response_1:any_data", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5302b7, .codes[1]=0x12011, .fstr = "slm::OFFCORE_RESPONSE_1:DMND_DATA_RD:PF_L2_DATA_RD:PF_L1_DATA_RD:ANY_RESPONSE:k=1:u=1:e=0:i=0:c=0", }, { SRC_LINE, .name = "slm::offcore_response_1:uc_ifetch", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5302b7, .codes[1]=0x10200, .fstr = "slm::OFFCORE_RESPONSE_1:UC_IFETCH:ANY_RESPONSE:k=1:u=1:e=0:i=0:c=0", }, { SRC_LINE, .name = "slm::offcore_response_1:any_ifetch", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5302b7, .codes[1]=0x10244, .fstr = "slm::OFFCORE_RESPONSE_1:DMND_IFETCH:PF_IFETCH:UC_IFETCH:ANY_RESPONSE:k=1:u=1:e=0:i=0:c=0", }, { SRC_LINE, .name = "slm::decode_restriction:predecode_wrong", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x5301e9, .fstr = "slm::DECODE_RESTRICTION:PREDECODE_WRONG:k=1:u=1:e=0:i=0:c=0", }, { SRC_LINE, .name = "slm::rs_full_stall:any", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x531fcb, .fstr = "slm::RS_FULL_STALL:ALL:k=1:u=1:e=0:i=0:c=0", }, { SRC_LINE, .name = "slm::no_alloc_cycles:any", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x533fca, .fstr = "slm::NO_ALLOC_CYCLES:ALL:k=1:u=1:e=0:i=0:c=0", }, { SRC_LINE, .name = "slm::no_alloc_cycles:any:t=1", .ret = PFM_ERR_ATTR }, { SRC_LINE, .name = "ivbep_unc_irp::unc_i_clockticks", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x0, .fstr = "ivbep_unc_irp::UNC_I_CLOCKTICKS:e=0:t=0", }, { SRC_LINE, .name = "ivbep_unc_irp::unc_i_transactions:reads", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x115, .fstr = "ivbep_unc_irp::UNC_I_TRANSACTIONS:READS:e=0:t=0", }, { SRC_LINE, .name = "ivbep_unc_irp::unc_i_transactions:reads:c=1:i", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "ivbep_unc_irp::unc_i_transactions:reads:t=6", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x6000115, .fstr = "ivbep_unc_irp::UNC_I_TRANSACTIONS:READS:e=0:t=6", }, { SRC_LINE, .name = "ivbep_unc_cbo1::UNC_C_CLOCKTICKS:u", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "ivbep_unc_cbo0::UNC_C_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x00, .fstr = "ivbep_unc_cbo0::UNC_C_CLOCKTICKS", }, { SRC_LINE, .name = "ivbep_unc_cbo0::UNC_C_LLC_LOOKUP:DATA_READ", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x334, .codes[1] = 0x7e0000, .fstr = "ivbep_unc_cbo0::UNC_C_LLC_LOOKUP:DATA_READ:STATE_MESIF:e=0:t=0:tf=0:cf=0", }, { SRC_LINE, .name = "ivbep_unc_cbo0::UNC_C_LLC_LOOKUP:DATA_READ:nf=1", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "ivbep_unc_cbo0::UNC_C_LLC_LOOKUP", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x1134, .codes[1] = 0x7e0000, .fstr = "ivbep_unc_cbo0::UNC_C_LLC_LOOKUP:ANY:STATE_MESIF:e=0:t=0:tf=0:cf=0", }, { SRC_LINE, .name = "ivbep_unc_cbo0::UNC_C_LLC_LOOKUP:NID:STATE_M", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "ivbep_unc_cbo0::UNC_C_LLC_LOOKUP:NID:nf=3", .ret = PFM_SUCCESS, .count = 3, .codes[0] = 0x5134, .codes[1] = 0x7e0000, .codes[2] = 0x3, .fstr = "ivbep_unc_cbo0::UNC_C_LLC_LOOKUP:ANY:NID:STATE_MESIF:e=0:t=0:tf=0:cf=0:nf=3", }, { SRC_LINE, .name = "ivbep_unc_cbo0::UNC_C_LLC_LOOKUP:NID:STATE_M:tid=1", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "ivbep_unc_cbo0::UNC_C_LLC_LOOKUP:DATA_READ:WRITE", .ret = PFM_ERR_FEATCOMB, }, { SRC_LINE, .name = "ivbep_unc_cbo0::UNC_C_LLC_LOOKUP:WRITE:NID:nf=3:tf=1:e:t=1", .ret = PFM_SUCCESS, .count = 3, .codes[0] = 0x10c4534, .codes[1] = 0x7e0001, .codes[2] = 0x3, .fstr = "ivbep_unc_cbo0::UNC_C_LLC_LOOKUP:WRITE:NID:STATE_MESIF:e=1:t=1:tf=1:cf=0:nf=3", }, { SRC_LINE, .name = "ivbep_unc_cbo0::UNC_C_LLC_VICTIMS", .ret = PFM_ERR_UMASK, }, { SRC_LINE, .name = "ivbep_unc_cbo0::UNC_C_LLC_VICTIMS:NID", .ret = PFM_ERR_UMASK, }, { SRC_LINE, .name = "ivbep_unc_cbo0::UNC_C_LLC_VICTIMS:NID:nf=1", .ret = PFM_ERR_UMASK, }, { SRC_LINE, .name = "ivbep_unc_cbo0::UNC_C_LLC_VICTIMS:STATE_M", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x137, .fstr = "ivbep_unc_cbo0::UNC_C_LLC_VICTIMS:STATE_M:e=0:t=0:tf=0:cf=0", }, { SRC_LINE, .name = "ivbep_unc_cbo0::UNC_C_LLC_VICTIMS:STATE_M:STATE_S", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x537, .fstr = "ivbep_unc_cbo0::UNC_C_LLC_VICTIMS:STATE_M:STATE_S:e=0:t=0:tf=0:cf=0", }, { SRC_LINE, .name = "ivbep_unc_cbo0::UNC_C_LLC_VICTIMS:STATE_M:STATE_S:NID:nf=1", .ret = PFM_SUCCESS, .count = 3, .codes[0] = 0x4537, .codes[1] = 0x0, .codes[2] = 0x1, .fstr = "ivbep_unc_cbo0::UNC_C_LLC_VICTIMS:STATE_M:STATE_S:NID:e=0:t=0:tf=0:cf=0:nf=1", }, { SRC_LINE, .name = "ivbep_unc_cbo0::UNC_C_TOR_INSERTS:OPCODE", .ret = PFM_ERR_UMASK, }, { SRC_LINE, .name = "ivbep_unc_cbo0::UNC_C_TOR_INSERTS:WB", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1035, .fstr = "ivbep_unc_cbo0::UNC_C_TOR_INSERTS:WB:e=0:t=0:tf=0:cf=0:isoc=0:nc=0", }, { SRC_LINE, .name = "ivbep_unc_cbo0::UNC_C_TOR_INSERTS:OPCODE:OPC_PCIWILF", .ret = PFM_SUCCESS, .count = 3, .codes[0] = 0x135, .codes[1] = 0x0, .codes[2] = 0x19400000ull, .fstr = "ivbep_unc_cbo0::UNC_C_TOR_INSERTS:OPCODE:OPC_PCIWILF:e=0:t=0:tf=0:cf=0:isoc=0:nc=0", }, { SRC_LINE, .name = "ivbep_unc_cbo0::UNC_C_TOR_INSERTS:OPCODE:OPC_PCIWILF:isoc=1", .ret = PFM_SUCCESS, .count = 3, .codes[0] = 0x135, .codes[1] = 0x0, .codes[2] = 0x99400000ull, .fstr = "ivbep_unc_cbo0::UNC_C_TOR_INSERTS:OPCODE:OPC_PCIWILF:e=0:t=0:tf=0:cf=0:isoc=1:nc=0", }, { SRC_LINE, .name = "ivbep_unc_cbo0::UNC_C_TOR_INSERTS:OPCODE:OPC_PCIWILF:nf=1", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "ivbep_unc_cbo0::UNC_C_TOR_INSERTS:NID_OPCODE:OPC_PCIRDCUR:nf=1", .ret = PFM_SUCCESS, .count = 3, .codes[0] = 0x4135, .codes[1] = 0x0, .codes[2] = 0x19e00001ull, .fstr = "ivbep_unc_cbo0::UNC_C_TOR_INSERTS:NID_OPCODE:OPC_PCIRDCUR:e=0:t=0:tf=0:cf=0:nf=1:isoc=0:nc=0", }, { SRC_LINE, .name = "ivbep_unc_cbo0::UNC_C_TOR_INSERTS:OPC_RFO:NID_OPCODE:nf=1", .ret = PFM_SUCCESS, .count = 3, .codes[0] = 0x4135, .codes[1] = 0x0, .codes[2] = 0x18000001ull, .fstr = "ivbep_unc_cbo0::UNC_C_TOR_INSERTS:NID_OPCODE:OPC_RFO:e=0:t=0:tf=0:cf=0:nf=1:isoc=0:nc=0", }, { SRC_LINE, .name = "ivbep_unc_cbo0::UNC_C_TOR_OCCUPANCY:MISS_REMOTE", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x8a36, .fstr = "ivbep_unc_cbo0::UNC_C_TOR_OCCUPANCY:MISS_REMOTE:e=0:t=0:tf=0:cf=0:isoc=0:nc=0", }, { SRC_LINE, .name = "ivbep_unc_pcu::UNC_P_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x0, .fstr = "ivbep_unc_pcu::UNC_P_CLOCKTICKS:e=0:t=0", }, { SRC_LINE, .name = "ivbep_unc_pcu::UNC_P_CLOCKTICKS:t=1", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1000000, .fstr = "ivbep_unc_pcu::UNC_P_CLOCKTICKS:e=0:t=1", }, { SRC_LINE, .name = "ivbep_unc_pcu::UNC_P_CORE0_TRANSITION_CYCLES", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x70, .fstr = "ivbep_unc_pcu::UNC_P_CORE0_TRANSITION_CYCLES:e=0:t=0", }, { SRC_LINE, .name = "ivbep_unc_pcu::UNC_P_FREQ_BAND0_CYCLES", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "ivbep_unc_pcu::UNC_P_FREQ_BAND1_CYCLES", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "ivbep_unc_pcu::UNC_P_FREQ_BAND2_CYCLES", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "ivbep_unc_pcu::UNC_P_FREQ_BAND3_CYCLES", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "ivbep_unc_pcu::UNC_P_FREQ_BAND0_CYCLES:ff=32", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0xb, .codes[1] = 0x20, .fstr = "ivbep_unc_pcu::UNC_P_FREQ_BAND0_CYCLES:e=0:t=0:ff=32", }, { SRC_LINE, .name = "ivbep_unc_pcu::UNC_P_FREQ_BAND1_CYCLES:ff=16", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0xc, .codes[1] = 0x1000, .fstr = "ivbep_unc_pcu::UNC_P_FREQ_BAND1_CYCLES:e=0:t=0:ff=16", }, { SRC_LINE, .name = "ivbep_unc_pcu::UNC_P_FREQ_BAND2_CYCLES:ff=8", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0xd, .codes[1] = 0x80000, .fstr = "ivbep_unc_pcu::UNC_P_FREQ_BAND2_CYCLES:e=0:t=0:ff=8", }, { SRC_LINE, .name = "ivbep_unc_pcu::UNC_P_FREQ_BAND3_CYCLES:ff=40", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0xe, .codes[1] = 0x28000000, .fstr = "ivbep_unc_pcu::UNC_P_FREQ_BAND3_CYCLES:e=0:t=0:ff=40", }, { SRC_LINE, .name = "ivbep_unc_pcu::UNC_P_FREQ_BAND0_CYCLES:ff=32:e", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x4000b, .codes[1] = 0x20, .fstr = "ivbep_unc_pcu::UNC_P_FREQ_BAND0_CYCLES:e=1:t=0:ff=32", }, { SRC_LINE, .name = "ivbep_unc_pcu::UNC_P_FREQ_BAND0_CYCLES:ff=32:t=24", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x1800000b, .codes[1] = 0x20, .fstr = "ivbep_unc_pcu::UNC_P_FREQ_BAND0_CYCLES:e=0:t=24:ff=32", }, { SRC_LINE, .name = "ivbep_unc_pcu::UNC_P_FREQ_BAND0_CYCLES:ff=32:e:t=4", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x404000b, .codes[1] = 0x20, .fstr = "ivbep_unc_pcu::UNC_P_FREQ_BAND0_CYCLES:e=1:t=4:ff=32", }, { SRC_LINE, .name = "ivbep_unc_pcu::UNC_P_POWER_STATE_OCCUPANCY:CORES_C0", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x4080, .fstr = "ivbep_unc_pcu::UNC_P_POWER_STATE_OCCUPANCY:CORES_C0:e=0:t=0" }, { SRC_LINE, .name = "ivbep_unc_pcu::UNC_P_POWER_STATE_OCCUPANCY:CORES_C3", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x8080, .fstr = "ivbep_unc_pcu::UNC_P_POWER_STATE_OCCUPANCY:CORES_C3:e=0:t=0", }, { SRC_LINE, .name = "IVBEP_UNC_PCU::UNC_P_POWER_STATE_OCCUPANCY:CORES_C6", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0xc080, .fstr = "ivbep_unc_pcu::UNC_P_POWER_STATE_OCCUPANCY:CORES_C6:e=0:t=0" }, { SRC_LINE, .name = "IVBEP_UNC_PCU::UNC_P_POWER_STATE_OCCUPANCY:CORES_C0:t=6", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x6004080, .fstr = "ivbep_unc_pcu::UNC_P_POWER_STATE_OCCUPANCY:CORES_C0:e=0:t=6" }, { SRC_LINE, .name = "ivbep_unc_pcu::UNC_P_DEMOTIONS_CORE10", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x42, .fstr = "ivbep_unc_pcu::UNC_P_DEMOTIONS_CORE10:e=0:t=0", }, { SRC_LINE, .name = "ivbep_unc_pcu::UNC_P_DEMOTIONS_CORE14", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x46, .fstr = "ivbep_unc_pcu::UNC_P_DEMOTIONS_CORE14:e=0:t=0", }, { SRC_LINE, .name = "ivbep_unc_ha0::UNC_H_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x0, .fstr = "ivbep_unc_ha0::UNC_H_CLOCKTICKS:e=0:t=0", }, { SRC_LINE, .name = "ivbep_unc_ha1::UNC_H_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x0, .fstr = "ivbep_unc_ha1::UNC_H_CLOCKTICKS:e=0:t=0", }, { SRC_LINE, .name = "ivbep_unc_ha1::UNC_H_REQUESTS:READS:t=1", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1000301, .fstr = "ivbep_unc_ha1::UNC_H_REQUESTS:READS:e=0:t=1", }, { SRC_LINE, .name = "ivbep_unc_ha0::UNC_H_IMC_WRITES:t=1", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1000f1a, .fstr = "ivbep_unc_ha0::UNC_H_IMC_WRITES:ALL:e=0:t=1", }, { SRC_LINE, .name = "ivbep_unc_ha0::UNC_H_IMC_READS:t=1", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1000117, .fstr = "ivbep_unc_ha0::UNC_H_IMC_READS:NORMAL:e=0:t=1", }, { SRC_LINE, .name = "ivbep_unc_imc0::UNC_M_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0xff, .fstr = "ivbep_unc_imc0::UNC_M_CLOCKTICKS", }, { SRC_LINE, .name = "ivbep_unc_imc0::UNC_M_CLOCKTICKS:t=1", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "ivbep_unc_imc0::UNC_M_DCLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x00, .fstr = "ivbep_unc_imc0::UNC_M_DCLOCKTICKS:e=0:t=0", }, { SRC_LINE, .name = "ivbep_unc_imc4::UNC_M_DCLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x00, .fstr = "ivbep_unc_imc4::UNC_M_DCLOCKTICKS:e=0:t=0", }, { SRC_LINE, .name = "ivbep_unc_imc0::UNC_M_CAS_COUNT:RD", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x0304, .fstr = "ivbep_unc_imc0::UNC_M_CAS_COUNT:RD:e=0:t=0", }, { SRC_LINE, .name = "ivbep_unc_imc0::UNC_M_PRE_COUNT:WR", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x0802, .fstr = "ivbep_unc_imc0::UNC_M_PRE_COUNT:WR:e=0:t=0", }, { SRC_LINE, .name = "ivbep_unc_imc0::UNC_M_POWER_CKE_CYCLES:RANK0", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x183, .fstr = "ivbep_unc_imc0::UNC_M_POWER_CKE_CYCLES:RANK0:e=0:t=0", }, { SRC_LINE, .name = "ivbep_unc_imc0::UNC_M_CAS_COUNT:WR", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0xc04, .fstr = "ivbep_unc_imc0::UNC_M_CAS_COUNT:WR:e=0:t=0", }, { SRC_LINE, .name = "ivbep_unc_imc0::UNC_M_RD_CAS_RANK0:BANK0", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1b0, .fstr = "ivbep_unc_imc0::UNC_M_RD_CAS_RANK0:BANK0:e=0:t=0", }, { SRC_LINE, .name = "ivbep_unc_imc0::UNC_M_RD_CAS_RANK4:BANK7", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x80b4, .fstr = "ivbep_unc_imc0::UNC_M_RD_CAS_RANK4:BANK7:e=0:t=0", }, { SRC_LINE, .name = "ivbep_unc_imc0::UNC_M_RD_CAS_RANK4:BANK7:t=1", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x10080b4, .fstr = "ivbep_unc_imc0::UNC_M_RD_CAS_RANK4:BANK7:e=0:t=1", }, { SRC_LINE, .name = "ivbep_unc_qpi0::UNC_Q_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x14, .fstr = "ivbep_unc_qpi0::UNC_Q_CLOCKTICKS:e=0:t=0", }, { SRC_LINE, .name = "ivbep_unc_qpi0::UNC_Q_RXL_FLITS_G0:DATA", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x201, .fstr = "ivbep_unc_qpi0::UNC_Q_RXL_FLITS_G0:DATA:e=0:t=0", }, { SRC_LINE, .name = "ivbep_unc_qpi0::UNC_Q_RXL_FLITS_G0:IDLE:t=1", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1000101, .fstr = "ivbep_unc_qpi0::UNC_Q_RXL_FLITS_G0:IDLE:e=0:t=1", }, { SRC_LINE, .name = "ivbep_unc_qpi0::UNC_Q_TXL_FLITS_G0:DATA", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x200, .fstr = "ivbep_unc_qpi0::UNC_Q_TXL_FLITS_G0:DATA:e=0:t=0", }, { SRC_LINE, .name = "ivbep_unc_qpi0::UNC_Q_RXL_FLITS_G1:HOM", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x200602, .fstr = "ivbep_unc_qpi0::UNC_Q_RXL_FLITS_G1:HOM:e=0:t=0", }, { SRC_LINE, .name = "ivbep_unc_qpi0::UNC_Q_TXL_FLITS_G1:HOM", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x200600, .fstr = "ivbep_unc_qpi0::UNC_Q_TXL_FLITS_G1:HOM:e=0:t=0", }, { SRC_LINE, .name = "ivbep_unc_ubo::UNC_U_LOCK_CYCLES", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x44, .fstr = "ivbep_unc_ubo::UNC_U_LOCK_CYCLES:e=0:t=0", }, { SRC_LINE, .name = "ivbep_unc_r2pcie::UNC_R2_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1, .fstr = "ivbep_unc_r2pcie::UNC_R2_CLOCKTICKS:e=0:t=0", }, { SRC_LINE, .name = "ivbep_unc_r2pcie::UNC_R2_RING_AD_USED:CW", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x3307, .fstr = "ivbep_unc_r2pcie::UNC_R2_RING_AD_USED:CW:e=0:t=0", }, { SRC_LINE, .name = "ivbep_unc_r3qpi0::UNC_R3_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1, .fstr = "ivbep_unc_r3qpi0::UNC_R3_CLOCKTICKS:e=0:t=0", }, { SRC_LINE, .name = "ivbep_unc_r3qpi0::UNC_R3_TXR_CYCLES_FULL:e=0:t=0", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x25, .fstr = "ivbep_unc_r3qpi0::UNC_R3_TXR_CYCLES_FULL:e=0:t=0", }, { SRC_LINE, .name = "ivbep_unc_r3qpi1::UNC_R3_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1, .fstr = "ivbep_unc_r3qpi1::UNC_R3_CLOCKTICKS:e=0:t=0", }, { SRC_LINE, .name = "ivbep_unc_r3qpi1::UNC_R3_TXR_CYCLES_FULL:e=0:t=0", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x25, .fstr = "ivbep_unc_r3qpi1::UNC_R3_TXR_CYCLES_FULL:e=0:t=0", }, { SRC_LINE, .name = "hsw_ep::mem_trans_retired:latency_above_threshold:ldlat=3:u", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5101cd, .codes[1] = 3, .fstr = "hsw_ep::MEM_TRANS_RETIRED:LOAD_LATENCY:k=0:u=1:e=0:i=0:c=0:t=0:ldlat=3:intx=0:intxcp=0", }, { SRC_LINE, .name = "hsw_ep::mem_trans_retired:latency_above_threshold:ldlat=1000000", .ret = PFM_ERR_ATTR_VAL, }, { SRC_LINE, .name = "hsw_ep::mem_trans_retired:load_latency", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301cd, .codes[1] = 3, .fstr = "hsw_ep::MEM_TRANS_RETIRED:LOAD_LATENCY:k=1:u=1:e=0:i=0:c=0:t=0:ldlat=3:intx=0:intxcp=0", }, { SRC_LINE, .name = "hsw_ep::cycle_activity:0x6:c=6", .count = 1, .codes[0] = 0x65306a3, .fstr = "hsw_ep::CYCLE_ACTIVITY:0x6:k=1:u=1:e=0:i=0:c=6:t=0:intx=0:intxcp=0", }, { SRC_LINE, .name = "hsw_ep::mem_trans_retired:load_latency:ldlat=1000000", .ret = PFM_ERR_ATTR_VAL, }, { SRC_LINE, .name = "hsw_ep::mem_trans_retired:latency_above_threshold:ldlat=2:intx=0:intxcp=0", .ret = PFM_ERR_ATTR_VAL, }, { SRC_LINE, .name = "hsw_ep::inst_Retired:any_p:intx", .count = 1, .codes[0] = 0x1005300c0ull, .fstr = "hsw_ep::INST_RETIRED:ANY_P:k=1:u=1:e=0:i=0:c=0:t=0:intx=1:intxcp=0", }, { SRC_LINE, .name = "hsw_ep::inst_Retired:any_p:intx:intxcp", .count = 1, .codes[0] = 0x3005300c0ull, .fstr = "hsw_ep::INST_RETIRED:ANY_P:k=1:u=1:e=0:i=0:c=0:t=0:intx=1:intxcp=1", }, { SRC_LINE, .name = "hsw_ep::inst_Retired:any_p:intx=0:intxcp", .count = 1, .codes[0] = 0x2005300c0ull, .fstr = "hsw_ep::INST_RETIRED:ANY_P:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=1", }, { SRC_LINE, .name = "hsw_ep::cycle_activity:cycles_l2_pending", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x15301a3, .fstr = "hsw_ep::CYCLE_ACTIVITY:CYCLES_L2_PENDING:k=1:u=1:e=0:i=0:c=1:t=0:intx=0:intxcp=0", }, { SRC_LINE, .name = "hsw_ep::cycle_activity:cycles_l2_pending:c=8", .ret = PFM_ERR_ATTR_SET, }, { SRC_LINE, .name = "hsw_ep::hle_retired:aborted", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x5304c8, .fstr = "hsw_ep::HLE_RETIRED:ABORTED:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0", }, { SRC_LINE, .name = "hsw_ep::mem_load_uops_l3_miss_retired:remote_dram", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x5304d3, .fstr = "hsw_ep::MEM_LOAD_UOPS_L3_MISS_RETIRED:REMOTE_DRAM:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0", }, { SRC_LINE, .name = "hsw_ep::offcore_response_0:any_data:L3_miss_local", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0x3f80400091ull, .fstr = "hsw_ep::OFFCORE_RESPONSE_0:DMND_DATA_RD:PF_DATA_RD:PF_L3_DATA_RD:L3_MISS_LOCAL:SNP_ANY:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0", }, { SRC_LINE, .name = "hsw_ep::offcore_response_0:any_data:L3_miss_remote", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0x3fb8000091ull, .fstr = "hsw_ep::OFFCORE_RESPONSE_0:DMND_DATA_RD:PF_DATA_RD:PF_L3_DATA_RD:L3_MISS_REMOTE_HOP0:L3_MISS_REMOTE_HOP1:L3_MISS_REMOTE_HOP2P:SNP_ANY:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0", }, { SRC_LINE, /* here SNP_ANY gets expanded when passed on the cmdline, but not when added automatically by library */ .name = "hsw_ep::OFFCORE_RESPONSE_0:DMND_DATA_RD:PF_DATA_RD:PF_L3_DATA_RD:L3_MISS_LOCAL:SNP_ANY:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0x3f80400091ull, .fstr = "hsw_ep::OFFCORE_RESPONSE_0:DMND_DATA_RD:PF_DATA_RD:PF_L3_DATA_RD:L3_MISS_LOCAL:SNP_NONE:SNP_NOT_NEEDED:SNP_MISS:SNP_NO_FWD:SNP_FWD:SNP_HITM:SNP_NON_DRAM:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0" }, { SRC_LINE, .name = "hsw_ep::offcore_response_0:any_data:LLC_miss_local", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "hsw_ep::offcore_response_0:any_data:LLC_miss_remote", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "hsw_ep::offcore_response_0:any_data:L3_HIT", .ret = PFM_SUCCESS, .count = 2, .codes[0] =0x5301b7, .codes[1] =0x3f803c0091ull, .fstr = "hsw_ep::OFFCORE_RESPONSE_0:DMND_DATA_RD:PF_DATA_RD:PF_L3_DATA_RD:L3_HITM:L3_HITE:L3_HITS:L3_HITF:SNP_ANY:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0", }, { SRC_LINE, .name = "hsw_ep::offcore_response_0:l3_miss", .ret = PFM_SUCCESS, .count = 2, .codes[0] =0x5301b7, .codes[1] = 0x3fb8408fffull, .fstr = "hsw_ep::OFFCORE_RESPONSE_0:ANY_REQUEST:L3_MISS_LOCAL:L3_MISS_REMOTE_HOP0:L3_MISS_REMOTE_HOP1:L3_MISS_REMOTE_HOP2P:SNP_ANY:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0", }, { SRC_LINE, .name = "bdw::mem_trans_retired:latency_above_threshold:ldlat=3:u", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5101cd, .codes[1] = 3, .fstr = "bdw::MEM_TRANS_RETIRED:LOAD_LATENCY:k=0:u=1:e=0:i=0:c=0:t=0:ldlat=3:intx=0:intxcp=0", }, { SRC_LINE, .name = "bdw::mem_trans_retired:latency_above_threshold:ldlat=1000000", .ret = PFM_ERR_ATTR_VAL, }, { SRC_LINE, .name = "bdw::mem_trans_retired:load_latency", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301cd, .codes[1] = 3, .fstr = "bdw::MEM_TRANS_RETIRED:LOAD_LATENCY:k=1:u=1:e=0:i=0:c=0:t=0:ldlat=3:intx=0:intxcp=0", }, { SRC_LINE, .name = "bdw::mem_trans_retired:load_latency:ldlat=1000000", .ret = PFM_ERR_ATTR_VAL, }, { SRC_LINE, .name = "bdw::mem_trans_retired:latency_above_threshold:ldlat=2:intx=0:intxcp=0", .ret = PFM_ERR_ATTR_VAL, }, { SRC_LINE, .name = "bdw::inst_Retired:any_p:intx", .count = 1, .codes[0] = 0x1005300c0ull, .fstr = "bdw::INST_RETIRED:ANY_P:k=1:u=1:e=0:i=0:c=0:t=0:intx=1:intxcp=0", }, { SRC_LINE, .name = "bdw::inst_Retired:any_p:intx:intxcp", .count = 1, .codes[0] = 0x3005300c0ull, .fstr = "bdw::INST_RETIRED:ANY_P:k=1:u=1:e=0:i=0:c=0:t=0:intx=1:intxcp=1", }, { SRC_LINE, .name = "bdw::cycle_activity:0x6:c=6", .count = 1, .codes[0] = 0x65306a3, .fstr = "bdw::CYCLE_ACTIVITY:0x6:k=1:u=1:e=0:i=0:c=6:t=0:intx=0:intxcp=0", }, { SRC_LINE, .name = "bdw::inst_Retired:any_p:intx=0:intxcp", .count = 1, .codes[0] = 0x2005300c0ull, .fstr = "bdw::INST_RETIRED:ANY_P:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=1", }, { SRC_LINE, .name = "bdw::cycle_activity:cycles_l2_pending", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x15301a3, .fstr = "bdw::CYCLE_ACTIVITY:CYCLES_L2_PENDING:k=1:u=1:e=0:i=0:c=1:t=0:intx=0:intxcp=0", }, { SRC_LINE, .name = "bdw::cycle_activity:stalls_ldm_pending", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x65306a3, .fstr = "bdw::CYCLE_ACTIVITY:STALLS_LDM_PENDING:k=1:u=1:e=0:i=0:c=6:t=0:intx=0:intxcp=0", }, { SRC_LINE, .name = "bdw::CYCLE_ACTIVITY:STALLS_LDM_PENDING:k=1:u=1:e=0:i=0:c=6:t=0:intx=0:intxcp=0", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x65306a3, .fstr = "bdw::CYCLE_ACTIVITY:STALLS_LDM_PENDING:k=1:u=1:e=0:i=0:c=6:t=0:intx=0:intxcp=0", }, { SRC_LINE, .name = "bdw::cycle_activity:cycles_l2_pending:c=8", .ret = PFM_ERR_ATTR_SET, }, { SRC_LINE, .name = "bdw::hle_retired:aborted", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x5304c8, .fstr = "bdw::HLE_RETIRED:ABORTED:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0", }, { SRC_LINE, .name = "bdw::rtm_retired:aborted", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x5304c9, .fstr = "bdw::RTM_RETIRED:ABORTED:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0", }, { SRC_LINE, .name = "bdw::arith:fpu_div_active", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x530114, .fstr = "bdw::ARITH:FPU_DIV_ACTIVE:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0", }, { SRC_LINE, .name = "bdw::inst_retired:prec_dist", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x5301c0, .fstr = "bdw::INST_RETIRED:PREC_DIST:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0", }, { SRC_LINE, .name = "bdw::rs_events:empty_end", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1d7015e, .fstr = "bdw::RS_EVENTS:EMPTY_END:k=1:u=1:e=1:i=1:c=1:t=0:intx=0:intxcp=0", }, { SRC_LINE, .name = "bdw::offcore_response_0:llc_hit", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0x3f803c8fffull, .fstr = "bdw::OFFCORE_RESPONSE_0:ANY_REQUEST:L3_HITM:L3_HITE:L3_HITS:L3_HITF:SNP_ANY:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0", }, { SRC_LINE, .name = "bdw::offcore_response_0:llc_miss_local", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0x3f84008fffull, .fstr = "bdw::OFFCORE_RESPONSE_0:ANY_REQUEST:L3_MISS_LOCAL:SNP_ANY:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0", }, { SRC_LINE, .name = "bdw::offcore_response_0:l3_miss_local", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0x3f84008fffull, .fstr = "bdw::OFFCORE_RESPONSE_0:ANY_REQUEST:L3_MISS_LOCAL:SNP_ANY:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0", }, { SRC_LINE, .name = "bdw::offcore_response_0:l3_miss", .ret = PFM_SUCCESS, .count = 2, .codes[0] =0x5301b7, .codes[1] = 0x3f84008fffull, .fstr = "bdw::OFFCORE_RESPONSE_0:ANY_REQUEST:L3_MISS_LOCAL:SNP_ANY:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0", }, { SRC_LINE, .name = "bdw::offcore_response_1:any_data", .ret = PFM_SUCCESS, .count = 2, .codes[0] =0x5301bb, .codes[1] = 0x10091, .fstr = "bdw::OFFCORE_RESPONSE_1:DMND_DATA_RD:PF_DATA_RD:PF_LLC_DATA_RD:ANY_RESPONSE:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0", }, { SRC_LINE, .name = "bdw_ep::offcore_response_0:l3_miss", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0x3fbc008fffull, .fstr = "bdw_ep::OFFCORE_RESPONSE_0:ANY_REQUEST:L3_MISS_LOCAL:L3_MISS_REMOTE_HOP0:L3_MISS_REMOTE_HOP1:L3_MISS_REMOTE_HOP2P:SNP_ANY:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0", }, { SRC_LINE, .name = "bdw_ep::offcore_response_1:l3_miss_remote", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301bb, .codes[1] = 0x3fb8008fffull, .fstr = "bdw_ep::OFFCORE_RESPONSE_1:ANY_REQUEST:L3_MISS_REMOTE_HOP0:L3_MISS_REMOTE_HOP1:L3_MISS_REMOTE_HOP2P:SNP_ANY:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0", }, { SRC_LINE, .name = "bdw_ep::offcore_response_0:L3_MISS_REMOTE_HOP0_DRAM", .ret = PFM_SUCCESS, .count = 2, .codes[0] =0x5301b7, .codes[1] = 0x3f88008fffull, .fstr = "bdw_ep::OFFCORE_RESPONSE_0:ANY_REQUEST:L3_MISS_REMOTE_HOP0:SNP_ANY:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0", }, { SRC_LINE, .name = "bdw::offcore_response_0:L3_MISS_REMOTE_HOP0_DRAM", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "hswep_unc_cbo1::UNC_C_CLOCKTICKS:u", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "hswep_unc_cbo0::UNC_C_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x00, .fstr = "hswep_unc_cbo0::UNC_C_CLOCKTICKS", }, { SRC_LINE, .name = "hswep_unc_cbo1::UNC_C_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x00, .fstr = "hswep_unc_cbo1::UNC_C_CLOCKTICKS", }, { SRC_LINE, .name = "hswep_unc_cbo2::UNC_C_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x00, .fstr = "hswep_unc_cbo2::UNC_C_CLOCKTICKS", }, { SRC_LINE, .name = "hswep_unc_cbo3::UNC_C_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x00, .fstr = "hswep_unc_cbo3::UNC_C_CLOCKTICKS", }, { SRC_LINE, .name = "hswep_unc_cbo4::UNC_C_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x00, .fstr = "hswep_unc_cbo4::UNC_C_CLOCKTICKS", }, { SRC_LINE, .name = "hswep_unc_cbo5::UNC_C_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x00, .fstr = "hswep_unc_cbo5::UNC_C_CLOCKTICKS", }, { SRC_LINE, .name = "hswep_unc_cbo6::UNC_C_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x00, .fstr = "hswep_unc_cbo6::UNC_C_CLOCKTICKS", }, { SRC_LINE, .name = "hswep_unc_cbo7::UNC_C_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x00, .fstr = "hswep_unc_cbo7::UNC_C_CLOCKTICKS", }, { SRC_LINE, .name = "hswep_unc_cbo8::UNC_C_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x00, .fstr = "hswep_unc_cbo8::UNC_C_CLOCKTICKS", }, { SRC_LINE, .name = "hswep_unc_cbo9::UNC_C_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x00, .fstr = "hswep_unc_cbo9::UNC_C_CLOCKTICKS", }, { SRC_LINE, .name = "hswep_unc_cbo10::UNC_C_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x00, .fstr = "hswep_unc_cbo10::UNC_C_CLOCKTICKS", }, { SRC_LINE, .name = "hswep_unc_cbo11::UNC_C_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x00, .fstr = "hswep_unc_cbo11::UNC_C_CLOCKTICKS", }, { SRC_LINE, .name = "hswep_unc_cbo12::UNC_C_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x00, .fstr = "hswep_unc_cbo12::UNC_C_CLOCKTICKS", }, { SRC_LINE, .name = "hswep_unc_cbo13::UNC_C_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x00, .fstr = "hswep_unc_cbo13::UNC_C_CLOCKTICKS", }, { SRC_LINE, .name = "hswep_unc_cbo14::UNC_C_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x00, .fstr = "hswep_unc_cbo14::UNC_C_CLOCKTICKS", }, { SRC_LINE, .name = "hswep_unc_cbo15::UNC_C_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x00, .fstr = "hswep_unc_cbo15::UNC_C_CLOCKTICKS", }, { SRC_LINE, .name = "hswep_unc_cbo16::UNC_C_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x00, .fstr = "hswep_unc_cbo16::UNC_C_CLOCKTICKS", }, { SRC_LINE, .name = "hswep_unc_cbo17::UNC_C_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x00, .fstr = "hswep_unc_cbo17::UNC_C_CLOCKTICKS", }, { SRC_LINE, .name = "hswep_unc_cbo0::UNC_C_LLC_LOOKUP:DATA_READ", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x334, .codes[1] = 0xfe0000, .fstr = "hswep_unc_cbo0::UNC_C_LLC_LOOKUP:DATA_READ:STATE_MESIFD:e=0:t=0:tf=0:cf=0", }, { SRC_LINE, .name = "hswep_unc_cbo0::UNC_C_LLC_LOOKUP:DATA_READ:nf=1", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "hswep_unc_cbo0::UNC_C_LLC_LOOKUP", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x1134, .codes[1] = 0xfe0000, .fstr = "hswep_unc_cbo0::UNC_C_LLC_LOOKUP:ANY:STATE_MESIFD:e=0:t=0:tf=0:cf=0", }, { SRC_LINE, .name = "hswep_unc_cbo0::UNC_C_LLC_LOOKUP:NID:STATE_M", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "hswep_unc_cbo0::UNC_C_LLC_LOOKUP:NID:nf=3", .ret = PFM_SUCCESS, .count = 3, .codes[0] = 0x5134, .codes[1] = 0xfe0000, .codes[2] = 0x3, .fstr = "hswep_unc_cbo0::UNC_C_LLC_LOOKUP:ANY:NID:STATE_MESIFD:e=0:t=0:tf=0:nf=3:cf=0", }, { SRC_LINE, .name = "hswep_unc_cbo0::UNC_C_LLC_LOOKUP:NID:STATE_M:tid=1", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "hswep_unc_cbo0::UNC_C_LLC_LOOKUP:DATA_READ:WRITE", .ret = PFM_ERR_FEATCOMB, }, { SRC_LINE, .name = "hswep_unc_cbo0::UNC_C_LLC_LOOKUP:WRITE:NID:nf=3:tf=1:e:t=1", .ret = PFM_SUCCESS, .count = 3, .codes[0] = 0x10c4534, .codes[1] = 0xfe0001, .codes[2] = 0x3, .fstr = "hswep_unc_cbo0::UNC_C_LLC_LOOKUP:WRITE:NID:STATE_MESIFD:e=1:t=1:tf=1:nf=3:cf=0", }, { SRC_LINE, .name = "hswep_unc_cbo0::UNC_C_LLC_VICTIMS", .ret = PFM_ERR_UMASK, }, { SRC_LINE, .name = "hswep_unc_cbo0::UNC_C_LLC_VICTIMS:NID", .ret = PFM_ERR_UMASK, }, { SRC_LINE, .name = "hswep_unc_cbo0::UNC_C_LLC_VICTIMS:NID:nf=1", .ret = PFM_ERR_UMASK, }, { SRC_LINE, .name = "hswep_unc_cbo0::UNC_C_LLC_VICTIMS:STATE_M", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x137, .fstr = "hswep_unc_cbo0::UNC_C_LLC_VICTIMS:STATE_M:e=0:t=0:tf=0:cf=0", }, { SRC_LINE, .name = "hswep_unc_cbo0::UNC_C_LLC_VICTIMS:STATE_M:STATE_S", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x537, .fstr = "hswep_unc_cbo0::UNC_C_LLC_VICTIMS:STATE_M:STATE_S:e=0:t=0:tf=0:cf=0", }, { SRC_LINE, .name = "hswep_unc_cbo0::UNC_C_LLC_VICTIMS:STATE_M:STATE_S:NID:nf=1", .ret = PFM_SUCCESS, .count = 3, .codes[0] = 0x4537, .codes[1] = 0x0, .codes[2] = 0x1, .fstr = "hswep_unc_cbo0::UNC_C_LLC_VICTIMS:STATE_M:STATE_S:NID:e=0:t=0:tf=0:nf=1:cf=0", }, { SRC_LINE, .name = "hswep_unc_cbo0::UNC_C_TOR_INSERTS:OPCODE", .ret = PFM_ERR_UMASK, }, { SRC_LINE, .name = "hswep_unc_cbo0::UNC_C_TOR_INSERTS:WB", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1035, .fstr = "hswep_unc_cbo0::UNC_C_TOR_INSERTS:WB:e=0:t=0:tf=0:isoc=0:nc=0:cf=0", }, { SRC_LINE, .name = "hswep_unc_cbo0::UNC_C_TOR_INSERTS:OPCODE:OPC_ITOM", .ret = PFM_SUCCESS, .count = 3, .codes[0] = 0x135, .codes[1] = 0x0, .codes[2] = 0x1c800000ull, .fstr = "hswep_unc_cbo0::UNC_C_TOR_INSERTS:OPCODE:OPC_ITOM:e=0:t=0:tf=0:isoc=0:nc=0:cf=0", }, { SRC_LINE, .name = "hswep_unc_cbo0::UNC_C_TOR_INSERTS:OPCODE:OPC_ITOM:isoc=1", .ret = PFM_SUCCESS, .count = 3, .codes[0] = 0x135, .codes[1] = 0x0, .codes[2] = 0x9c800000ull, .fstr = "hswep_unc_cbo0::UNC_C_TOR_INSERTS:OPCODE:OPC_ITOM:e=0:t=0:tf=0:isoc=1:nc=0:cf=0", }, { SRC_LINE, .name = "hswep_unc_cbo0::UNC_C_TOR_INSERTS:OPCODE:OPC_PCIWILF:nf=1", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "hswep_unc_cbo0::UNC_C_TOR_INSERTS:NID_OPCODE:OPC_PCIRDCUR:nf=1", .ret = PFM_SUCCESS, .count = 3, .codes[0] = 0x4135, .codes[1] = 0x0, .codes[2] = 0x19e00001ull, .fstr = "hswep_unc_cbo0::UNC_C_TOR_INSERTS:NID_OPCODE:OPC_PCIRDCUR:e=0:t=0:tf=0:nf=1:isoc=0:nc=0:cf=0", }, { SRC_LINE, .name = "hswep_unc_cbo0::UNC_C_TOR_INSERTS:OPC_RFO:NID_OPCODE:nf=1", .ret = PFM_SUCCESS, .count = 3, .codes[0] = 0x4135, .codes[1] = 0x0, .codes[2] = 0x18000001ull, .fstr = "hswep_unc_cbo0::UNC_C_TOR_INSERTS:NID_OPCODE:OPC_RFO:e=0:t=0:tf=0:nf=1:isoc=0:nc=0:cf=0", }, { SRC_LINE, .name = "hswep_unc_cbo0::UNC_C_TOR_OCCUPANCY:MISS_REMOTE", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x8a36, .fstr = "hswep_unc_cbo0::UNC_C_TOR_OCCUPANCY:MISS_REMOTE:e=0:t=0:tf=0:isoc=0:nc=0:cf=0", }, { SRC_LINE, .name = "hswep_unc_irp::unc_i_clockticks", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x0, .fstr = "hswep_unc_irp::UNC_I_CLOCKTICKS:e=0:i=0:t=0", }, { SRC_LINE, .name = "hswep_unc_irp::unc_i_coherent_ops:RFO", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x813, .fstr = "hswep_unc_irp::UNC_I_COHERENT_OPS:RFO:e=0:i=0:t=0", }, { SRC_LINE, .name = "hswep_unc_irp::unc_i_transactions:reads", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x116, .fstr = "hswep_unc_irp::UNC_I_TRANSACTIONS:READS:e=0:i=0:t=0", }, { SRC_LINE, .name = "hswep_unc_irp::unc_i_transactions:reads:c=1:i", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "hswep_unc_irp::unc_i_transactions:reads:t=6", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x6000116, .fstr = "hswep_unc_irp::UNC_I_TRANSACTIONS:READS:e=0:i=0:t=6", }, { SRC_LINE, .name = "hswep_unc_sbo0::unc_s_clockticks", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x0, .fstr = "hswep_unc_sbo0::UNC_S_CLOCKTICKS:e=0:i=0:t=0", }, { SRC_LINE, .name = "hswep_unc_sbo1::unc_s_clockticks", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x0, .fstr = "hswep_unc_sbo1::UNC_S_CLOCKTICKS:e=0:i=0:t=0", }, { SRC_LINE, .name = "hswep_unc_sbo2::unc_s_clockticks", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x0, .fstr = "hswep_unc_sbo2::UNC_S_CLOCKTICKS:e=0:i=0:t=0", }, { SRC_LINE, .name = "hswep_unc_sbo3::unc_s_clockticks", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x0, .fstr = "hswep_unc_sbo3::UNC_S_CLOCKTICKS:e=0:i=0:t=0", }, { SRC_LINE, .name = "hswep_unc_pcu::UNC_P_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x0, .fstr = "hswep_unc_pcu::UNC_P_CLOCKTICKS:e=0:i=0:t=0", }, { SRC_LINE, .name = "hswep_unc_pcu::UNC_P_CLOCKTICKS:t=1", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1000000, .fstr = "hswep_unc_pcu::UNC_P_CLOCKTICKS:e=0:i=0:t=1", }, { SRC_LINE, .name = "hswep_unc_pcu::UNC_P_CORE0_TRANSITION_CYCLES", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x60, .fstr = "hswep_unc_pcu::UNC_P_CORE0_TRANSITION_CYCLES:e=0:i=0:t=0", }, { SRC_LINE, .name = "hswep_unc_pcu::UNC_P_CORE17_TRANSITION_CYCLES", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x71, .fstr = "hswep_unc_pcu::UNC_P_CORE17_TRANSITION_CYCLES:e=0:i=0:t=0", }, { SRC_LINE, .name = "hswep_unc_pcu::UNC_P_FREQ_BAND0_CYCLES", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "hswep_unc_pcu::UNC_P_FREQ_BAND1_CYCLES", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "hswep_unc_pcu::UNC_P_FREQ_BAND2_CYCLES", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "hswep_unc_pcu::UNC_P_FREQ_BAND3_CYCLES", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "hswep_unc_pcu::UNC_P_FREQ_BAND0_CYCLES:ff=32", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0xb, .codes[1] = 0x20, .fstr = "hswep_unc_pcu::UNC_P_FREQ_BAND0_CYCLES:e=0:i=0:t=0:ff=32", }, { SRC_LINE, .name = "hswep_unc_pcu::UNC_P_FREQ_BAND1_CYCLES:ff=16", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0xc, .codes[1] = 0x1000, .fstr = "hswep_unc_pcu::UNC_P_FREQ_BAND1_CYCLES:e=0:i=0:t=0:ff=16", }, { SRC_LINE, .name = "hswep_unc_pcu::UNC_P_FREQ_BAND2_CYCLES:ff=8", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0xd, .codes[1] = 0x80000, .fstr = "hswep_unc_pcu::UNC_P_FREQ_BAND2_CYCLES:e=0:i=0:t=0:ff=8", }, { SRC_LINE, .name = "hswep_unc_pcu::UNC_P_FREQ_BAND3_CYCLES:ff=40", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0xe, .codes[1] = 0x28000000, .fstr = "hswep_unc_pcu::UNC_P_FREQ_BAND3_CYCLES:e=0:i=0:t=0:ff=40", }, { SRC_LINE, .name = "hswep_unc_pcu::UNC_P_FREQ_BAND0_CYCLES:ff=32:e", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x4000b, .codes[1] = 0x20, .fstr = "hswep_unc_pcu::UNC_P_FREQ_BAND0_CYCLES:e=1:i=0:t=0:ff=32", }, { SRC_LINE, .name = "hswep_unc_pcu::UNC_P_FREQ_BAND0_CYCLES:ff=32:t=24", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x1800000b, .codes[1] = 0x20, .fstr = "hswep_unc_pcu::UNC_P_FREQ_BAND0_CYCLES:e=0:i=0:t=24:ff=32", }, { SRC_LINE, .name = "hswep_unc_pcu::UNC_P_FREQ_BAND0_CYCLES:ff=32:e:t=4", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x404000b, .codes[1] = 0x20, .fstr = "hswep_unc_pcu::UNC_P_FREQ_BAND0_CYCLES:e=1:i=0:t=4:ff=32", }, { SRC_LINE, .name = "hswep_unc_pcu::UNC_P_POWER_STATE_OCCUPANCY:CORES_C0", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x4080, .fstr = "hswep_unc_pcu::UNC_P_POWER_STATE_OCCUPANCY:CORES_C0:e=0:i=0:t=0" }, { SRC_LINE, .name = "hswep_unc_pcu::UNC_P_POWER_STATE_OCCUPANCY:CORES_C3", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x8080, .fstr = "hswep_unc_pcu::UNC_P_POWER_STATE_OCCUPANCY:CORES_C3:e=0:i=0:t=0", }, { SRC_LINE, .name = "hswep_unc_pcu::UNC_P_POWER_STATE_OCCUPANCY:CORES_C6", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0xc080, .fstr = "hswep_unc_pcu::UNC_P_POWER_STATE_OCCUPANCY:CORES_C6:e=0:i=0:t=0" }, { SRC_LINE, .name = "hswep_unc_pcu::UNC_P_POWER_STATE_OCCUPANCY:CORES_C0:t=6:i", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x6804080, .fstr = "hswep_unc_pcu::UNC_P_POWER_STATE_OCCUPANCY:CORES_C0:e=0:i=1:t=6" }, { SRC_LINE, .name = "hswep_unc_pcu::UNC_P_POWER_STATE_OCCUPANCY:CORES_C0:t=6", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x6004080, .fstr = "hswep_unc_pcu::UNC_P_POWER_STATE_OCCUPANCY:CORES_C0:e=0:i=0:t=6" }, { SRC_LINE, .name = "hswep_unc_pcu::UNC_P_DEMOTIONS_CORE10", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x3a, .fstr = "hswep_unc_pcu::UNC_P_DEMOTIONS_CORE10:e=0:i=0:t=0", }, { SRC_LINE, .name = "hswep_unc_pcu::UNC_P_DEMOTIONS_CORE14", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x3e, .fstr = "hswep_unc_pcu::UNC_P_DEMOTIONS_CORE14:e=0:i=0:t=0", }, { SRC_LINE, .name = "hswep_unc_pcu::UNC_P_DEMOTIONS_CORE17", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x41, .fstr = "hswep_unc_pcu::UNC_P_DEMOTIONS_CORE17:e=0:i=0:t=0", }, { SRC_LINE, .name = "hswep_unc_ha0::UNC_H_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x0, .fstr = "hswep_unc_ha0::UNC_H_CLOCKTICKS:e=0:i=0:t=0", }, { SRC_LINE, .name = "hswep_unc_ha1::UNC_H_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x0, .fstr = "hswep_unc_ha1::UNC_H_CLOCKTICKS:e=0:i=0:t=0", }, { SRC_LINE, .name = "hswep_unc_ha1::UNC_H_REQUESTS:READS:t=1", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1000301, .fstr = "hswep_unc_ha1::UNC_H_REQUESTS:READS:e=0:i=0:t=1", }, { SRC_LINE, .name = "hswep_unc_ha0::UNC_H_IMC_WRITES:t=1", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1000f1a, .fstr = "hswep_unc_ha0::UNC_H_IMC_WRITES:ALL:e=0:i=0:t=1", }, { SRC_LINE, .name = "hswep_unc_ha0::UNC_H_IMC_READS:t=1", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1000117, .fstr = "hswep_unc_ha0::UNC_H_IMC_READS:NORMAL:e=0:i=0:t=1", }, { SRC_LINE, .name = "hswep_unc_imc0::UNC_M_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0xff, .fstr = "hswep_unc_imc0::UNC_M_CLOCKTICKS", }, { SRC_LINE, .name = "hswep_unc_imc0::UNC_M_CLOCKTICKS:t=1", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "hswep_unc_imc0::UNC_M_DCLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x00, .fstr = "hswep_unc_imc0::UNC_M_DCLOCKTICKS:e=0:i=0:t=0", }, { SRC_LINE, .name = "hswep_unc_imc4::UNC_M_DCLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x00, .fstr = "hswep_unc_imc4::UNC_M_DCLOCKTICKS:e=0:i=0:t=0", }, { SRC_LINE, .name = "hswep_unc_imc0::UNC_M_CAS_COUNT:RD", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x0304, .fstr = "hswep_unc_imc0::UNC_M_CAS_COUNT:RD:e=0:i=0:t=0", }, { SRC_LINE, .name = "hswep_unc_imc0::UNC_M_PRE_COUNT:WR", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x0802, .fstr = "hswep_unc_imc0::UNC_M_PRE_COUNT:WR:e=0:i=0:t=0", }, { SRC_LINE, .name = "hswep_unc_imc0::UNC_M_POWER_CKE_CYCLES:RANK0", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x183, .fstr = "hswep_unc_imc0::UNC_M_POWER_CKE_CYCLES:RANK0:e=0:i=0:t=0", }, { SRC_LINE, .name = "hswep_unc_imc0::UNC_M_CAS_COUNT:WR", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0xc04, .fstr = "hswep_unc_imc0::UNC_M_CAS_COUNT:WR:e=0:i=0:t=0", }, { SRC_LINE, .name = "hswep_unc_imc0::UNC_M_RD_CAS_RANK0:BANK0", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0xb0, .fstr = "hswep_unc_imc0::UNC_M_RD_CAS_RANK0:BANK0:e=0:i=0:t=0", }, { SRC_LINE, .name = "hswep_unc_imc0::UNC_M_RD_CAS_RANK0:ALLBANKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x10b0, .fstr = "hswep_unc_imc0::UNC_M_RD_CAS_RANK0:ALLBANKS:e=0:i=0:t=0", }, { SRC_LINE, .name = "hswep_unc_imc0::UNC_M_RD_CAS_RANK0:BANKG0", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x11b0, .fstr = "hswep_unc_imc0::UNC_M_RD_CAS_RANK0:BANKG0:e=0:i=0:t=0", }, { SRC_LINE, .name = "hswep_unc_imc0::UNC_M_RD_CAS_RANK4:BANK7", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x7b4, .fstr = "hswep_unc_imc0::UNC_M_RD_CAS_RANK4:BANK7:e=0:i=0:t=0", }, { SRC_LINE, .name = "hswep_unc_imc0::UNC_M_RD_CAS_RANK4:BANK7:t=1", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x10007b4, .fstr = "hswep_unc_imc0::UNC_M_RD_CAS_RANK4:BANK7:e=0:i=0:t=1", }, { SRC_LINE, .name = "hswep_unc_imc0::UNC_M_RD_CAS_RANK7:BANK7:t=1:i", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x18007b7, .fstr = "hswep_unc_imc0::UNC_M_RD_CAS_RANK7:BANK7:e=0:i=1:t=1", }, { SRC_LINE, .name = "hswep_unc_sbo0::UNC_S_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x0, .fstr = "hswep_unc_sbo0::UNC_S_CLOCKTICKS:e=0:i=0:t=0", }, { SRC_LINE, .name = "hswep_unc_sbo0::UNC_S_FAST_ASSERTED:t=1:i", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1800009, .fstr = "hswep_unc_sbo0::UNC_S_FAST_ASSERTED:e=0:i=1:t=1", }, { SRC_LINE, .name = "hswep_unc_sbo3::UNC_S_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x0, .fstr = "hswep_unc_sbo3::UNC_S_CLOCKTICKS:e=0:i=0:t=0", }, { SRC_LINE, .name = "hswep_unc_sbo3::UNC_S_FAST_ASSERTED:t=1:i", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1800009, .fstr = "hswep_unc_sbo3::UNC_S_FAST_ASSERTED:e=0:i=1:t=1", }, { SRC_LINE, .name = "hswep_unc_ubo::UNC_U_EVENT_MSG", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x842, .fstr = "hswep_unc_ubo::UNC_U_EVENT_MSG:DOORBELL_RCVD:e=0:i=0:t=0", }, { SRC_LINE, .name = "hswep_unc_qpi0::UNC_Q_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x14, .fstr = "hswep_unc_qpi0::UNC_Q_CLOCKTICKS:e=0:i=0:t=0", }, { SRC_LINE, .name = "hswep_unc_qpi0::UNC_Q_DIRECT2CORE:SUCCESS_RBT_HIT", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x113, .fstr = "hswep_unc_qpi0::UNC_Q_DIRECT2CORE:SUCCESS_RBT_HIT:e=0:i=0:t=0", }, { SRC_LINE, .name = "hswep_unc_qpi0::UNC_Q_RXL_FLITS_G1:DRS:i:t=1", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1a01802, .fstr = "hswep_unc_qpi0::UNC_Q_RXL_FLITS_G1:DRS:e=0:i=1:t=1", }, { SRC_LINE, .name = "hswep_unc_qpi0::UNC_Q_TXL_FLITS_G2:NDR_AD", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x200101, .fstr = "hswep_unc_qpi0::UNC_Q_TXL_FLITS_G2:NDR_AD:e=0:i=0:t=0", }, { SRC_LINE, .name = "hswep_unc_qpi0::UNC_Q_RXL_OCCUPANCY", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0xb, .fstr = "hswep_unc_qpi0::UNC_Q_RXL_OCCUPANCY:e=0:i=0:t=0", }, { SRC_LINE, .name = "hswep_unc_qpi0::UNC_Q_TXL_INSERTS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x4, .fstr = "hswep_unc_qpi0::UNC_Q_TXL_INSERTS:e=0:i=0:t=0", }, { SRC_LINE, .name = "hswep_unc_r2pcie::UNC_R2_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1, .fstr = "hswep_unc_r2pcie::UNC_R2_CLOCKTICKS:e=0:i=0:t=0", }, { SRC_LINE, .name = "hswep_unc_r2pcie::UNC_R2_RING_AD_USED:CW", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x307, .fstr = "hswep_unc_r2pcie::UNC_R2_RING_AD_USED:CW:e=0:i=0:t=0", }, { SRC_LINE, .name = "hswep_unc_r3qpi0::UNC_R3_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1, .fstr = "hswep_unc_r3qpi0::UNC_R3_CLOCKTICKS:e=0:i=0:t=0", }, { SRC_LINE, .name = "hswep_unc_r3qpi0::UNC_R3_RXR_CYCLES_NE:SNP:e=0:t=0", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x210, .fstr = "hswep_unc_r3qpi0::UNC_R3_RXR_CYCLES_NE:SNP:e=0:i=0:t=0", }, { SRC_LINE, .name = "hswep_unc_r3qpi1::UNC_R3_RING_SINK_STARVED", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x20e, .fstr = "hswep_unc_r3qpi1::UNC_R3_RING_SINK_STARVED:AK:e=0:i=0:t=0", }, { SRC_LINE, .name = "hswep_unc_r3qpi1::UNC_R3_HA_R2_BL_CREDITS_EMPTY:HA1:i:t=2", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x280022d, .fstr = "hswep_unc_r3qpi1::UNC_R3_HA_R2_BL_CREDITS_EMPTY:HA1:e=0:i=1:t=2", }, { SRC_LINE, .name = "skl::FRONTEND_RETIRED:DSB_MISS", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301c6, .codes[1] = 0x11, .fstr = "skl::FRONTEND_RETIRED:DSB_MISS:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0:fe_thres=0", }, { SRC_LINE, .name = "skl::MEM_LOAD_RETIRED:L3_MISS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x5320d1, .fstr = "skl::MEM_LOAD_RETIRED:L3_MISS:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0", }, { SRC_LINE, .name = "skl::FRONTEND_RETIRED:ITLB_MISS", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301c6, .codes[1] = 0x14, .fstr = "skl::FRONTEND_RETIRED:ITLB_MISS:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0:fe_thres=0", }, { SRC_LINE, .name = "skl::FRONTEND_RETIRED:L1I_MISS", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301c6, .codes[1] = 0x12, .fstr = "skl::FRONTEND_RETIRED:L1I_MISS:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0:fe_thres=0", }, { SRC_LINE, .name = "skl::FRONTEND_RETIRED:L2_MISS:u", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5101c6, .codes[1] = 0x13, .fstr = "skl::FRONTEND_RETIRED:L2_MISS:k=0:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0:fe_thres=0", }, { SRC_LINE, .name = "skl::FRONTEND_RETIRED:STLB_MISS:c=1:i", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x1d301c6, .codes[1] = 0x15, .fstr = "skl::FRONTEND_RETIRED:STLB_MISS:k=1:u=1:e=0:i=1:c=1:t=0:intx=0:intxcp=0:fe_thres=0", }, { SRC_LINE, .name = "skl::FRONTEND_RETIRED:IDQ_4_BUBBLES", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301c6, .codes[1] = 0x400106, .fstr = "skl::FRONTEND_RETIRED:IDQ_4_BUBBLES:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0:fe_thres=1", }, { SRC_LINE, .name = "skl::FRONTEND_RETIRED:IDQ_3_BUBBLES", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301c6, .codes[1] = 0x300106, .fstr = "skl::FRONTEND_RETIRED:IDQ_3_BUBBLES:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0:fe_thres=1", }, { SRC_LINE, .name = "skl::FRONTEND_RETIRED:IDQ_3_BUBBLES:fe_thres=8", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301c6, .codes[1] = 0x300806, .fstr = "skl::FRONTEND_RETIRED:IDQ_3_BUBBLES:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0:fe_thres=8", }, { SRC_LINE, .name = "skl::FRONTEND_RETIRED:IDQ_3_BUBBLES:fe_thres=4095", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301c6, .codes[1] = 0x3fff06, .fstr = "skl::FRONTEND_RETIRED:IDQ_3_BUBBLES:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0:fe_thres=4095", }, { SRC_LINE, .name = "skl::FRONTEND_RETIRED:IDQ_3_BUBBLES:fe_thres=4096", .ret = PFM_ERR_ATTR_VAL, }, { SRC_LINE, .name = "skl::FRONTEND_RETIRED:DSB_MISS:ITLB_MISS", .ret = PFM_ERR_FEATCOMB, }, { SRC_LINE, .name = "skl::offcore_response_0:any_request", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0x18007, .fstr = "skl::OFFCORE_RESPONSE_0:DMND_DATA_RD:DMND_RFO:DMND_CODE_RD:OTHER:ANY_RESPONSE:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0", }, { SRC_LINE, .name = "skl::offcore_response_0:l3_hitmes", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0x3f801d8007ull, .fstr = "skl::OFFCORE_RESPONSE_0:ANY_REQUEST:L3_HITM:L3_HITE:L3_HITS:SNP_ANY:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0", }, { SRC_LINE, .name = "skl::offcore_response_0:L4_HIT_LOCAL_L4", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0x3f80418007ull, .fstr = "skl::OFFCORE_RESPONSE_0:ANY_REQUEST:L4_HIT_LOCAL_L4:SNP_ANY:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0", }, { SRC_LINE, .name = "skl::offcore_response_0:L3_MISS_LOCAL", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0x3f84018007ull, .fstr = "skl::OFFCORE_RESPONSE_0:ANY_REQUEST:L3_MISS_LOCAL:SNP_ANY:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0", }, { SRC_LINE, .name = "skl::offcore_response_0:l3_miss", .ret = PFM_SUCCESS, .count = 2, .codes[0] =0x5301b7, .codes[1] = 0x3f84018007ull, .fstr = "skl::OFFCORE_RESPONSE_0:ANY_REQUEST:L3_MISS_LOCAL:SNP_ANY:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0", }, { SRC_LINE, .name = "skl::cycle_activity:0x6:c=6", .count = 1, .codes[0] = 0x65306a3, .fstr = "skl::CYCLE_ACTIVITY:0x6:k=1:u=1:e=0:i=0:c=6:t=0:intx=0:intxcp=0", }, { SRC_LINE, .name = "skl::dtlb_store_misses:walk_completed_2m_4m:c=1", .count = 1, .codes[0] = 0x1530449, .fstr = "skl::DTLB_STORE_MISSES:WALK_COMPLETED_2M_4M:k=1:u=1:e=0:i=0:c=1:t=0:intx=0:intxcp=0", }, { SRC_LINE, .name = "skl::rob_misc_events:lbr_inserts", .count = 1, .codes[0] = 0x5320cc, .fstr = "skl::ROB_MISC_EVENTS:LBR_INSERTS:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0", }, { SRC_LINE, .name = "skl::cycle_activity:stalls_mem_any:c=6", .ret = PFM_ERR_ATTR_SET, }, { SRC_LINE, .name = "skl::uops_dispatched_port:port_0", .count = 1, .codes[0] = 0x5301a1, .fstr = "skl::UOPS_DISPATCHED_PORT:PORT_0:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0", }, { SRC_LINE, .name = "skl::uops_dispatched:port_0", .count = 1, .codes[0] = 0x5301a1, .fstr = "skl::UOPS_DISPATCHED_PORT:PORT_0:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0", }, { SRC_LINE, .name = "hsw::CYCLE_ACTIVITY:CYCLES_L2_PENDING:k=1:u=1:e=0:i=0:c=1:t=0:intx=0:intxcp=0", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x15301a3, .fstr = "hsw::CYCLE_ACTIVITY:CYCLES_L2_PENDING:k=1:u=1:e=0:i=0:c=1:t=0:intx=0:intxcp=0", }, { SRC_LINE, .name = "hsw::CYCLE_ACTIVITY:CYCLES_L2_PENDING:c=1", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x15301a3, .fstr = "hsw::CYCLE_ACTIVITY:CYCLES_L2_PENDING:k=1:u=1:e=0:i=0:c=1:t=0:intx=0:intxcp=0", }, { SRC_LINE, .name = "glm::offcore_response_1:any_request", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5302b7, .codes[1] = 0x18000, .fstr = "glm::OFFCORE_RESPONSE_1:ANY_REQUEST:ANY_RESPONSE:k=1:u=1:e=0:i=0:c=0", }, { SRC_LINE, .name = "glm::offcore_response_1:any_rfo", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5302b7, .codes[1] = 0x10022, .fstr = "glm::OFFCORE_RESPONSE_1:DMND_RFO:PF_RFO:ANY_RESPONSE:k=1:u=1:e=0:i=0:c=0", }, { SRC_LINE, .name = "glm::offcore_response_1:any_rfo:l2_miss_snp_miss_or_no_snoop_needed", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5302b7, .codes[1] = 0x200010022ull, .fstr = "glm::OFFCORE_RESPONSE_1:DMND_RFO:PF_RFO:ANY_RESPONSE:L2_MISS_SNP_MISS_OR_NO_SNOOP_NEEDED:k=1:u=1:e=0:i=0:c=0", }, { SRC_LINE, .name = "glm::offcore_response_0:strm_st", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0x14800, .fstr = "glm::OFFCORE_RESPONSE_0:FULL_STRM_ST:PARTIAL_STRM_ST:ANY_RESPONSE:k=1:u=1:e=0:i=0:c=0", }, { SRC_LINE, .name = "glm::offcore_response_1:dmnd_data_rd:outstanding", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "glm::offcore_response_1:dmnd_data_rd:l2_hit:outstanding", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "glm::offcore_response_0:strm_st:outstanding", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0x4000004800ull, .fstr = "glm::OFFCORE_RESPONSE_0:FULL_STRM_ST:PARTIAL_STRM_ST:OUTSTANDING:k=1:u=1:e=0:i=0:c=0", }, { SRC_LINE, .name = "glm::offcore_response_0:outstanding:dmnd_data_rd:u", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5101b7, .codes[1] = 0x4000000001ull, .fstr = "glm::OFFCORE_RESPONSE_0:DMND_DATA_RD:OUTSTANDING:k=0:u=1:e=0:i=0:c=0", }, { SRC_LINE, .name = "glm::offcore_response_0:strm_st:l2_hit:outstanding", .ret = PFM_ERR_FEATCOMB, }, { SRC_LINE, .name = "glm::ISSUE_SLOTS_NOT_CONSUMED:RESOURCE_FULL", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x5301ca, .fstr = "glm::ISSUE_SLOTS_NOT_CONSUMED:RESOURCE_FULL:k=1:u=1:e=0:i=0:c=0", }, { SRC_LINE, .name = "glm::ISSUE_SLOTS_NOT_CONSUMED:RESOURCE_FULL:k:c=1:i", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1d201ca, .fstr = "glm::ISSUE_SLOTS_NOT_CONSUMED:RESOURCE_FULL:k=1:u=0:e=0:i=1:c=1", }, { SRC_LINE, .name = "glm::ISSUE_SLOTS_NOT_CONSUMED:RESOURCE_FULL:u:t", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "glm::ISSUE_SLOTS_NOT_CONSUMED:RESOURCE_FULL:u:intxcp", .ret = PFM_ERR_ATTR, }, /* * test delimiter options */ { SRC_LINE, .name = "glm::ISSUE_SLOTS_NOT_CONSUMED.RESOURCE_FULL.k=1.u=0.e=0.i=0.c=1", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x15201ca, .fstr = "glm::ISSUE_SLOTS_NOT_CONSUMED:RESOURCE_FULL:k=1:u=0:e=0:i=0:c=1", }, { SRC_LINE, .name = "glm::ISSUE_SLOTS_NOT_CONSUMED.RESOURCE_FULL:k=1:u=1:e=0:i=0:c=1", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x15301ca, .fstr = "glm::ISSUE_SLOTS_NOT_CONSUMED:RESOURCE_FULL:k=1:u=1:e=0:i=0:c=1", }, { SRC_LINE, .name = "glm::ISSUE_SLOTS_NOT_CONSUMED.RESOURCE_FULL:k=1:u=1:e=0.i=0.c=1", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x15301ca, .fstr = "glm::ISSUE_SLOTS_NOT_CONSUMED:RESOURCE_FULL:k=1:u=1:e=0:i=0:c=1", }, { SRC_LINE, .name = "knl::no_alloc_cycles:all", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x537fca, .fstr = "knl::NO_ALLOC_CYCLES:ALL:k=1:u=1:e=0:i=0:c=0", }, { SRC_LINE, .name = "knl::MEM_UOPS_RETIRED:DTLB_MISS_LOADS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x530804, .fstr = "knl::MEM_UOPS_RETIRED:DTLB_MISS_LOADS:k=1:u=1:e=0:i=0:c=0", }, { SRC_LINE, .name = "knl::uops_retired:any:t", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "knl::unhalted_reference_cycles:u:t", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x710300, .fstr = "knl::UNHALTED_REFERENCE_CYCLES:k=0:u=1:t=1", }, { SRC_LINE, .name = "knl::instructions_retired:k:t", .ret = PFM_SUCCESS, .count = 1, .codes[0] =0x7200c0, .fstr = "knl::INSTRUCTION_RETIRED:k=1:u=0:e=0:i=0:c=0:t=1", }, { SRC_LINE, .name = "knl::unhalted_core_cycles:k:t", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x72003c, .fstr = "knl::UNHALTED_CORE_CYCLES:k=1:u=0:e=0:i=0:c=0:t=1", }, { SRC_LINE, .name = "knl::offcore_response_1:any_request", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5302b7, .codes[1] = 0x18000, .fstr = "knl::OFFCORE_RESPONSE_1:ANY_REQUEST:ANY_RESPONSE:k=1:u=1:e=0:i=0:c=0", }, { SRC_LINE, .name = "knl::offcore_response_0:any_read", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0x132e7, .fstr = "knl::OFFCORE_RESPONSE_0:DMND_DATA_RD:DMND_RFO:DMND_CODE_RD:PF_L2_RFO:PF_L2_CODE_RD:PARTIAL_READS:UC_CODE_READS:PF_SOFTWARE:PF_L1_DATA_RD:ANY_RESPONSE:k=1:u=1:e=0:i=0:c=0", }, { SRC_LINE, .name = "knl::offcore_response_1:any_read", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5302b7, .codes[1] = 0x132e7, .fstr = "knl::OFFCORE_RESPONSE_1:DMND_DATA_RD:DMND_RFO:DMND_CODE_RD:PF_L2_RFO:PF_L2_CODE_RD:PARTIAL_READS:UC_CODE_READS:PF_SOFTWARE:PF_L1_DATA_RD:ANY_RESPONSE:k=1:u=1:e=0:i=0:c=0", }, { SRC_LINE, .name = "knl::offcore_response_0:any_request:ddr_near", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0x80808000ull, .fstr = "knl::OFFCORE_RESPONSE_0:ANY_REQUEST:DDR_NEAR:k=1:u=1:e=0:i=0:c=0", }, { SRC_LINE, .name = "knl::offcore_response_0:any_request:L2_HIT_NEAR_TILE:L2_HIT_FAR_TILE", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0x1800588000ull, .fstr = "knl::OFFCORE_RESPONSE_0:ANY_REQUEST:L2_HIT_NEAR_TILE:L2_HIT_FAR_TILE:k=1:u=1:e=0:i=0:c=0", }, { SRC_LINE, .name = "knl::offcore_response_0:dmnd_data_rd:outstanding", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0x4000000001ull, .fstr = "knl::OFFCORE_RESPONSE_0:DMND_DATA_RD:OUTSTANDING:k=1:u=1:e=0:i=0:c=0", }, { SRC_LINE, .name = "knl::offcore_response_0:dmnd_data_rd:ddr_near:outstanding", .ret = PFM_ERR_FEATCOMB, }, { SRC_LINE, .name = "knl::offcore_response_1:dmnd_data_rd:outstanding", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "knl_unc_imc0::UNC_M_D_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x00, .fstr = "knl_unc_imc0::UNC_M_D_CLOCKTICKS", }, { SRC_LINE, .name = "knl_unc_imc0::UNC_M_CAS_COUNT:RD", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x0103, .fstr = "knl_unc_imc0::UNC_M_CAS_COUNT:RD", }, { SRC_LINE, .name = "knl_unc_imc0::UNC_M_CAS_COUNT:WR", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x0203, .fstr = "knl_unc_imc0::UNC_M_CAS_COUNT:WR", }, { SRC_LINE, .name = "knl_unc_imc0::UNC_M_CAS_COUNT:ALL", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x0303, .fstr = "knl_unc_imc0::UNC_M_CAS_COUNT:ALL", }, { SRC_LINE, .name = "knl_unc_imc_uclk0::UNC_M_U_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x00, .fstr = "knl_unc_imc_uclk0::UNC_M_U_CLOCKTICKS", }, { SRC_LINE, .name = "knl_unc_edc_uclk0::UNC_E_U_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x00, .fstr = "knl_unc_edc_uclk0::UNC_E_U_CLOCKTICKS", }, { SRC_LINE, .name = "knl_unc_edc_uclk0::UNC_E_EDC_ACCESS:HIT_CLEAN", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x0102, .fstr = "knl_unc_edc_uclk0::UNC_E_EDC_ACCESS:HIT_CLEAN", }, { SRC_LINE, .name = "knl_unc_edc_uclk0::UNC_E_EDC_ACCESS:HIT_DIRTY", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x0202, .fstr = "knl_unc_edc_uclk0::UNC_E_EDC_ACCESS:HIT_DIRTY", }, { SRC_LINE, .name = "knl_unc_edc_uclk0::UNC_E_EDC_ACCESS:MISS_CLEAN", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x0402, .fstr = "knl_unc_edc_uclk0::UNC_E_EDC_ACCESS:MISS_CLEAN", }, { SRC_LINE, .name = "knl_unc_edc_uclk0::UNC_E_EDC_ACCESS:MISS_DIRTY", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x0802, .fstr = "knl_unc_edc_uclk0::UNC_E_EDC_ACCESS:MISS_DIRTY", }, { SRC_LINE, .name = "knl_unc_edc_uclk0::UNC_E_EDC_ACCESS:MISS_INVALID", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1002, .fstr = "knl_unc_edc_uclk0::UNC_E_EDC_ACCESS:MISS_INVALID", }, { SRC_LINE, .name = "knl_unc_edc_eclk0::UNC_E_E_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x00, .fstr = "knl_unc_edc_eclk0::UNC_E_E_CLOCKTICKS", }, { SRC_LINE, .name = "knl_unc_edc_eclk0::UNC_E_RPQ_INSERTS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x0101, .fstr = "knl_unc_edc_eclk0::UNC_E_RPQ_INSERTS", }, { SRC_LINE, .name = "knl_unc_cha0::UNC_H_U_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x00, .fstr = "knl_unc_cha0::UNC_H_U_CLOCKTICKS", }, { SRC_LINE, .name = "knl_unc_cha1::UNC_H_U_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x00, .fstr = "knl_unc_cha1::UNC_H_U_CLOCKTICKS", }, { SRC_LINE, .name = "knl_unc_cha10::UNC_H_U_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x00, .fstr = "knl_unc_cha10::UNC_H_U_CLOCKTICKS", }, { SRC_LINE, .name = "knl_unc_cha20::UNC_H_U_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x00, .fstr = "knl_unc_cha20::UNC_H_U_CLOCKTICKS", }, { SRC_LINE, .name = "knl_unc_cha25::UNC_H_U_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x00, .fstr = "knl_unc_cha25::UNC_H_U_CLOCKTICKS", }, { SRC_LINE, .name = "knl_unc_cha30::UNC_H_U_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x00, .fstr = "knl_unc_cha30::UNC_H_U_CLOCKTICKS", }, { SRC_LINE, .name = "knl_unc_cha37::UNC_H_U_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x00, .fstr = "knl_unc_cha37::UNC_H_U_CLOCKTICKS", }, { SRC_LINE, .name = "knl_unc_cha0::UNC_H_INGRESS_OCCUPANCY:IRQ", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x0111, .fstr = "knl_unc_cha0::UNC_H_INGRESS_OCCUPANCY:IRQ", }, { SRC_LINE, .name = "knl_unc_cha0::UNC_H_INGRESS_OCCUPANCY:IRQ_REJ", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x0211, .fstr = "knl_unc_cha0::UNC_H_INGRESS_OCCUPANCY:IRQ_REJ", }, { SRC_LINE, .name = "knl_unc_cha0::UNC_H_INGRESS_OCCUPANCY:IPQ", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x0411, .fstr = "knl_unc_cha0::UNC_H_INGRESS_OCCUPANCY:IPQ", }, { SRC_LINE, .name = "knl_unc_cha0::UNC_H_INGRESS_OCCUPANCY:PRQ", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1011, .fstr = "knl_unc_cha0::UNC_H_INGRESS_OCCUPANCY:PRQ", }, { SRC_LINE, .name = "knl_unc_cha0::UNC_H_INGRESS_OCCUPANCY:PRQ_REJ", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x2011, .fstr = "knl_unc_cha0::UNC_H_INGRESS_OCCUPANCY:PRQ_REJ", }, { SRC_LINE, .name = "knl_unc_cha0::UNC_H_INGRESS_INSERTS:IRQ", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x0113, .fstr = "knl_unc_cha0::UNC_H_INGRESS_INSERTS:IRQ", }, { SRC_LINE, .name = "knl_unc_cha0::UNC_H_INGRESS_INSERTS:IRQ_REJ", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x0213, .fstr = "knl_unc_cha0::UNC_H_INGRESS_INSERTS:IRQ_REJ", }, { SRC_LINE, .name = "knl_unc_cha0::UNC_H_INGRESS_INSERTS:IPQ", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x0413, .fstr = "knl_unc_cha0::UNC_H_INGRESS_INSERTS:IPQ", }, { SRC_LINE, .name = "knl_unc_cha0::UNC_H_INGRESS_INSERTS:PRQ", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1013, .fstr = "knl_unc_cha0::UNC_H_INGRESS_INSERTS:PRQ", }, { SRC_LINE, .name = "knl_unc_cha0::UNC_H_INGRESS_INSERTS:PRQ_REJ", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x2013, .fstr = "knl_unc_cha0::UNC_H_INGRESS_INSERTS:PRQ_REJ", }, { SRC_LINE, .name = "knl_unc_cha0::UNC_H_INGRESS_RETRY_IRQ0_REJECT:AD_RSP_VN0", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x0218, .fstr = "knl_unc_cha0::UNC_H_INGRESS_RETRY_IRQ0_REJECT:AD_RSP_VN0", }, { SRC_LINE, .name = "knl_unc_m2pcie::UNC_M2P_INGRESS_CYCLES_NE:ALL", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x0810, .fstr = "knl_unc_m2pcie::UNC_M2P_INGRESS_CYCLES_NE:ALL", }, { SRC_LINE, .name = "knl_unc_m2pcie::UNC_M2P_EGRESS_CYCLES_NE:AD_0", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x0123, .fstr = "knl_unc_m2pcie::UNC_M2P_EGRESS_CYCLES_NE:AD_0", }, { SRC_LINE, .name = "knl_unc_m2pcie::UNC_M2P_EGRESS_CYCLES_NE:AD_1", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x0823, .fstr = "knl_unc_m2pcie::UNC_M2P_EGRESS_CYCLES_NE:AD_1", }, { SRC_LINE, .name = "knl_unc_m2pcie::UNC_M2P_EGRESS_INSERTS:AD_0", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x0124, .fstr = "knl_unc_m2pcie::UNC_M2P_EGRESS_INSERTS:AD_0", }, { SRC_LINE, .name = "knl_unc_m2pcie::UNC_M2P_EGRESS_INSERTS:AD_1", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1024, .fstr = "knl_unc_m2pcie::UNC_M2P_EGRESS_INSERTS:AD_1", }, { SRC_LINE, .name = "knl_unc_m2pcie::UNC_M2P_EGRESS_CYCLES_FULL:AD_0", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x0125, .fstr = "knl_unc_m2pcie::UNC_M2P_EGRESS_CYCLES_FULL:AD_0", }, { SRC_LINE, .name = "knl_unc_m2pcie::UNC_M2P_EGRESS_CYCLES_FULL:AD_1", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x0825, .fstr = "knl_unc_m2pcie::UNC_M2P_EGRESS_CYCLES_FULL:AD_1", }, { SRC_LINE, .name = "wsm::offcore_response_0:0xf", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0xf, .fstr = "wsm::OFFCORE_RESPONSE_0:0xf:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "wsm::offcore_response_0:0xffff", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0xffff, .fstr = "wsm::OFFCORE_RESPONSE_0:0xffff:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "wsm::offcore_response_0:0x7fffffffff", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "snb::offcore_response_0:0xf", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0xf, .fstr = "snb::OFFCORE_RESPONSE_0:0xf:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "snb::offcore_response_0:0xfffffffff", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0xfffffffff, .fstr = "snb::OFFCORE_RESPONSE_0:0xffffffff:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "snb::offcore_response_0:0x7fffffffff", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "ivb_ep::offcore_response_0:0xf", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0xf, .fstr = "ivb_ep::OFFCORE_RESPONSE_0:0xf:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "ivb_ep::offcore_response_0:0xfffffffff", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0xfffffffff, .fstr = "ivb_ep::OFFCORE_RESPONSE_0:0xffffffff:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "ivb_ep::offcore_response_0:0x7fffffffff", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "hsw::offcore_response_0:0xf", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0xf, .fstr = "hsw::OFFCORE_RESPONSE_0:0xf:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0", }, { SRC_LINE, .name = "hsw::offcore_response_0:0xfffffffff", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0xfffffffff, .fstr = "hsw::OFFCORE_RESPONSE_0:0xffffffff:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0", }, { SRC_LINE, .name = "hsw::offcore_response_0:0x7fffffffff", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "bdw_ep::offcore_response_0:0xf", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0xf, .fstr = "bdw_ep::OFFCORE_RESPONSE_0:0xf:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0", }, { SRC_LINE, .name = "bdw_ep::offcore_response_0:0xfffffffff", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0xfffffffff, .fstr = "bdw_ep::OFFCORE_RESPONSE_0:0xffffffff:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0", }, { SRC_LINE, .name = "bdw_ep::offcore_response_0:0x7fffffffff", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "skl::offcore_response_0:0xf", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0xf, .fstr = "skl::OFFCORE_RESPONSE_0:0xf:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0", }, { SRC_LINE, .name = "skl::offcore_response_0:0xfffffffff", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0xfffffffff, .fstr = "skl::OFFCORE_RESPONSE_0:0xffffffff:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0", }, { SRC_LINE, .name = "skl::offcore_response_0:0x7fffffffff", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "wsm::offcore_response_1:0xfff", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301bb, .codes[1] = 0xfff, .fstr = "wsm::OFFCORE_RESPONSE_1:0xfff:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "wsm::offcore_response_1:0x7fffffffff", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "snb::offcore_response_1:0xf", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301bb, .codes[1] = 0xf, .fstr = "snb::OFFCORE_RESPONSE_1:0xf:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "snb::offcore_response_1:0xfffffffff", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301bb, .codes[1] = 0xfffffffff, .fstr = "snb::OFFCORE_RESPONSE_1:0xffffffff:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "snb::offcore_response_1:0x7fffffffff", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "ivb_ep::offcore_response_1:0xf", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301bb, .codes[1] = 0xf, .fstr = "ivb_ep::OFFCORE_RESPONSE_1:0xf:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "ivb_ep::offcore_response_1:0xfffffffff", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301bb, .codes[1] = 0xfffffffff, .fstr = "ivb_ep::OFFCORE_RESPONSE_1:0xffffffff:k=1:u=1:e=0:i=0:c=0:t=0", }, { SRC_LINE, .name = "ivb_ep::offcore_response_1:0x7fffffffff", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "hsw::offcore_response_1:0xf", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301bb, .codes[1] = 0xf, .fstr = "hsw::OFFCORE_RESPONSE_1:0xf:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0", }, { SRC_LINE, .name = "hsw::offcore_response_1:0xfffffffff", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301bb, .codes[1] = 0xfffffffff, .fstr = "hsw::OFFCORE_RESPONSE_1:0xffffffff:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0", }, { SRC_LINE, .name = "hsw::offcore_response_1:0x7fffffffff", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "bdw_ep::offcore_response_1:0xf", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301bb, .codes[1] = 0xf, .fstr = "bdw_ep::OFFCORE_RESPONSE_1:0xf:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0", }, { SRC_LINE, .name = "bdw_ep::offcore_response_1:0xfffffffff", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301bb, .codes[1] = 0xfffffffff, .fstr = "bdw_ep::OFFCORE_RESPONSE_1:0xffffffff:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0", }, { SRC_LINE, .name = "bdw_ep::offcore_response_1:0x7fffffffff", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "skl::offcore_response_1:0xf", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301bb, .codes[1] = 0xf, .fstr = "skl::OFFCORE_RESPONSE_1:0xf:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0", }, { SRC_LINE, .name = "skl::offcore_response_1:0xfffffffff", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301bb, .codes[1] = 0xfffffffff, .fstr = "skl::OFFCORE_RESPONSE_1:0xffffffff:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0", }, { SRC_LINE, .name = "skl::offcore_response_1:0x7fffffffff", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "bdx_unc_cbo1::UNC_C_CLOCKTICKS:u", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "bdx_unc_cbo0::UNC_C_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x00, .fstr = "bdx_unc_cbo0::UNC_C_CLOCKTICKS:e=0:t=0:tf=0:cf=0", }, { SRC_LINE, .name = "bdx_unc_cbo1::UNC_C_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x00, .fstr = "bdx_unc_cbo1::UNC_C_CLOCKTICKS:e=0:t=0:tf=0:cf=0", }, { SRC_LINE, .name = "bdx_unc_cbo2::UNC_C_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x00, .fstr = "bdx_unc_cbo2::UNC_C_CLOCKTICKS:e=0:t=0:tf=0:cf=0", }, { SRC_LINE, .name = "bdx_unc_cbo3::UNC_C_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x00, .fstr = "bdx_unc_cbo3::UNC_C_CLOCKTICKS:e=0:t=0:tf=0:cf=0", }, { SRC_LINE, .name = "bdx_unc_cbo4::UNC_C_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x00, .fstr = "bdx_unc_cbo4::UNC_C_CLOCKTICKS:e=0:t=0:tf=0:cf=0", }, { SRC_LINE, .name = "bdx_unc_cbo5::UNC_C_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x00, .fstr = "bdx_unc_cbo5::UNC_C_CLOCKTICKS:e=0:t=0:tf=0:cf=0", }, { SRC_LINE, .name = "bdx_unc_cbo6::UNC_C_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x00, .fstr = "bdx_unc_cbo6::UNC_C_CLOCKTICKS:e=0:t=0:tf=0:cf=0", }, { SRC_LINE, .name = "bdx_unc_cbo7::UNC_C_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x00, .fstr = "bdx_unc_cbo7::UNC_C_CLOCKTICKS:e=0:t=0:tf=0:cf=0", }, { SRC_LINE, .name = "bdx_unc_cbo8::UNC_C_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x00, .fstr = "bdx_unc_cbo8::UNC_C_CLOCKTICKS:e=0:t=0:tf=0:cf=0", }, { SRC_LINE, .name = "bdx_unc_cbo9::UNC_C_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x00, .fstr = "bdx_unc_cbo9::UNC_C_CLOCKTICKS:e=0:t=0:tf=0:cf=0", }, { SRC_LINE, .name = "bdx_unc_cbo10::UNC_C_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x00, .fstr = "bdx_unc_cbo10::UNC_C_CLOCKTICKS:e=0:t=0:tf=0:cf=0", }, { SRC_LINE, .name = "bdx_unc_cbo11::UNC_C_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x00, .fstr = "bdx_unc_cbo11::UNC_C_CLOCKTICKS:e=0:t=0:tf=0:cf=0", }, { SRC_LINE, .name = "bdx_unc_cbo12::UNC_C_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x00, .fstr = "bdx_unc_cbo12::UNC_C_CLOCKTICKS:e=0:t=0:tf=0:cf=0", }, { SRC_LINE, .name = "bdx_unc_cbo13::UNC_C_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x00, .fstr = "bdx_unc_cbo13::UNC_C_CLOCKTICKS:e=0:t=0:tf=0:cf=0", }, { SRC_LINE, .name = "bdx_unc_cbo14::UNC_C_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x00, .fstr = "bdx_unc_cbo14::UNC_C_CLOCKTICKS:e=0:t=0:tf=0:cf=0", }, { SRC_LINE, .name = "bdx_unc_cbo15::UNC_C_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x00, .fstr = "bdx_unc_cbo15::UNC_C_CLOCKTICKS:e=0:t=0:tf=0:cf=0", }, { SRC_LINE, .name = "bdx_unc_cbo16::UNC_C_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x00, .fstr = "bdx_unc_cbo16::UNC_C_CLOCKTICKS:e=0:t=0:tf=0:cf=0", }, { SRC_LINE, .name = "bdx_unc_cbo17::UNC_C_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x00, .fstr = "bdx_unc_cbo17::UNC_C_CLOCKTICKS:e=0:t=0:tf=0:cf=0", }, { SRC_LINE, .name = "bdx_unc_cbo18::UNC_C_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x00, .fstr = "bdx_unc_cbo18::UNC_C_CLOCKTICKS:e=0:t=0:tf=0:cf=0", }, { SRC_LINE, .name = "bdx_unc_cbo19::UNC_C_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x00, .fstr = "bdx_unc_cbo19::UNC_C_CLOCKTICKS:e=0:t=0:tf=0:cf=0", }, { SRC_LINE, .name = "bdx_unc_cbo20::UNC_C_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x00, .fstr = "bdx_unc_cbo20::UNC_C_CLOCKTICKS:e=0:t=0:tf=0:cf=0", }, { SRC_LINE, .name = "bdx_unc_cbo21::UNC_C_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x00, .fstr = "bdx_unc_cbo21::UNC_C_CLOCKTICKS:e=0:t=0:tf=0:cf=0", }, { SRC_LINE, .name = "bdx_unc_cbo0::UNC_C_LLC_LOOKUP:DATA_READ", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x334, .codes[1] = 0xfe0000, .fstr = "bdx_unc_cbo0::UNC_C_LLC_LOOKUP:DATA_READ:STATE_MESIFD:e=0:t=0:tf=0:cf=0", }, { SRC_LINE, .name = "bdx_unc_cbo0::UNC_C_LLC_LOOKUP:DATA_READ:nf=1", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "bdx_unc_cbo0::UNC_C_LLC_LOOKUP", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x1134, .codes[1] = 0xfe0000, .fstr = "bdx_unc_cbo0::UNC_C_LLC_LOOKUP:ANY:STATE_MESIFD:e=0:t=0:tf=0:cf=0", }, { SRC_LINE, .name = "bdx_unc_cbo0::UNC_C_LLC_LOOKUP:NID:STATE_M", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "bdx_unc_cbo0::UNC_C_LLC_LOOKUP:NID:nf=3", .ret = PFM_SUCCESS, .count = 3, .codes[0] = 0x5134, .codes[1] = 0xfe0000, .codes[2] = 0x3, .fstr = "bdx_unc_cbo0::UNC_C_LLC_LOOKUP:ANY:NID:STATE_MESIFD:e=0:t=0:tf=0:nf=3:cf=0", }, { SRC_LINE, .name = "bdx_unc_cbo0::UNC_C_LLC_LOOKUP:NID:STATE_M:tid=1", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "bdx_unc_cbo0::UNC_C_ring_iv_used:DN:UP", .ret = PFM_ERR_FEATCOMB, }, { SRC_LINE, .name = "bdx_unc_cbo0::UNC_C_LLC_LOOKUP:WRITE:NID:nf=3:tf=1:e:t=1", .ret = PFM_SUCCESS, .count = 3, .codes[0] = 0x10c4534, .codes[1] = 0xfe0001, .codes[2] = 0x3, .fstr = "bdx_unc_cbo0::UNC_C_LLC_LOOKUP:NID:WRITE:STATE_MESIFD:e=1:t=1:tf=1:nf=3:cf=0", }, { SRC_LINE, .name = "bdx_unc_cbo0::UNC_C_LLC_VICTIMS", .ret = PFM_ERR_UMASK, }, { SRC_LINE, .name = "bdx_unc_cbo0::UNC_C_LLC_VICTIMS:NID", .ret = PFM_ERR_UMASK, }, { SRC_LINE, .name = "bdx_unc_cbo0::UNC_C_LLC_VICTIMS:NID:nf=1", .ret = PFM_ERR_UMASK, }, { SRC_LINE, .name = "bdx_unc_cbo0::UNC_C_LLC_VICTIMS:M_STATE", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x137, .fstr = "bdx_unc_cbo0::UNC_C_LLC_VICTIMS:M_STATE:e=0:t=0:tf=0:cf=0", }, { SRC_LINE, .name = "bdx_unc_cbo0::UNC_C_LLC_VICTIMS:M_STATE:S_STATE", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x537, .fstr = "bdx_unc_cbo0::UNC_C_LLC_VICTIMS:S_STATE:M_STATE:e=0:t=0:tf=0:cf=0", }, { SRC_LINE, .name = "bdx_unc_cbo0::UNC_C_LLC_VICTIMS:M_STATE:S_STATE:NID:nf=1", .ret = PFM_SUCCESS, .count = 3, .codes[0] = 0x4537, .codes[1] = 0x0, .codes[2] = 0x1, .fstr = "bdx_unc_cbo0::UNC_C_LLC_VICTIMS:S_STATE:M_STATE:NID:e=0:t=0:tf=0:nf=1:cf=0", }, { SRC_LINE, .name = "bdx_unc_cbo0::UNC_C_TOR_INSERTS:OPCODE", .ret = PFM_ERR_UMASK, }, { SRC_LINE, .name = "bdx_unc_cbo0::UNC_C_TOR_INSERTS:WB", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1035, .fstr = "bdx_unc_cbo0::UNC_C_TOR_INSERTS:WB:e=0:t=0:tf=0:isoc=0:nc=0:cf=0", }, { SRC_LINE, .name = "bdx_unc_cbo0::UNC_C_TOR_INSERTS:OPCODE:OPC_ITOM", .ret = PFM_SUCCESS, .count = 3, .codes[0] = 0x135, .codes[1] = 0x0, .codes[2] = 0x1c800000ull, .fstr = "bdx_unc_cbo0::UNC_C_TOR_INSERTS:OPCODE:OPC_ITOM:e=0:t=0:tf=0:isoc=0:nc=0:cf=0", }, { SRC_LINE, .name = "bdx_unc_cbo0::UNC_C_TOR_INSERTS:OPCODE:OPC_ITOM:isoc=1", .ret = PFM_SUCCESS, .count = 3, .codes[0] = 0x135, .codes[1] = 0x0, .codes[2] = 0x9c800000ull, .fstr = "bdx_unc_cbo0::UNC_C_TOR_INSERTS:OPCODE:OPC_ITOM:e=0:t=0:tf=0:isoc=1:nc=0:cf=0", }, { SRC_LINE, .name = "bdx_unc_cbo0::UNC_C_TOR_INSERTS:OPCODE:OPC_PCIWILF:nf=1", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "bdx_unc_cbo0::UNC_C_TOR_INSERTS:NID_OPCODE:OPC_PCIRDCUR:nf=1", .ret = PFM_SUCCESS, .count = 3, .codes[0] = 0x4135, .codes[1] = 0x0, .codes[2] = 0x19e00001ull, .fstr = "bdx_unc_cbo0::UNC_C_TOR_INSERTS:NID_OPCODE:OPC_PCIRDCUR:e=0:t=0:tf=0:nf=1:isoc=0:nc=0:cf=0", }, { SRC_LINE, .name = "bdx_unc_cbo0::UNC_C_TOR_INSERTS:OPC_RFO:NID_OPCODE:nf=1", .ret = PFM_SUCCESS, .count = 3, .codes[0] = 0x4135, .codes[1] = 0x0, .codes[2] = 0x18000001ull, .fstr = "bdx_unc_cbo0::UNC_C_TOR_INSERTS:NID_OPCODE:OPC_RFO:e=0:t=0:tf=0:nf=1:isoc=0:nc=0:cf=0", }, { SRC_LINE, .name = "bdx_unc_cbo0::UNC_C_TOR_OCCUPANCY:MISS_REMOTE", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x8a36, .fstr = "bdx_unc_cbo0::UNC_C_TOR_OCCUPANCY:MISS_REMOTE:e=0:t=0:tf=0:isoc=0:nc=0:cf=0", }, { SRC_LINE, .name = "bdx_unc_irp::unc_i_clockticks", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x0, .fstr = "bdx_unc_irp::UNC_I_CLOCKTICKS:e=0:i=0:t=0", }, { SRC_LINE, .name = "bdx_unc_irp::unc_i_coherent_ops:RFO", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x813, .fstr = "bdx_unc_irp::UNC_I_COHERENT_OPS:RFO:e=0:i=0:t=0", }, { SRC_LINE, .name = "bdx_unc_irp::unc_i_transactions:reads", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x116, .fstr = "bdx_unc_irp::UNC_I_TRANSACTIONS:READS:e=0:i=0:t=0", }, { SRC_LINE, .name = "bdx_unc_irp::unc_i_transactions:reads:c=1:i", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "bdx_unc_irp::unc_i_transactions:reads:t=6", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x6000116, .fstr = "bdx_unc_irp::UNC_I_TRANSACTIONS:READS:e=0:i=0:t=6", }, { SRC_LINE, .name = "bdx_unc_sbo0::unc_s_clockticks", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x0, .fstr = "bdx_unc_sbo0::UNC_S_CLOCKTICKS:e=0:i=0:t=0", }, { SRC_LINE, .name = "bdx_unc_sbo1::unc_s_clockticks", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x0, .fstr = "bdx_unc_sbo1::UNC_S_CLOCKTICKS:e=0:i=0:t=0", }, { SRC_LINE, .name = "bdx_unc_sbo2::unc_s_clockticks", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x0, .fstr = "bdx_unc_sbo2::UNC_S_CLOCKTICKS:e=0:i=0:t=0", }, { SRC_LINE, .name = "bdx_unc_sbo3::unc_s_clockticks", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x0, .fstr = "bdx_unc_sbo3::UNC_S_CLOCKTICKS:e=0:i=0:t=0", }, { SRC_LINE, .name = "bdx_unc_pcu::UNC_P_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x0, .fstr = "bdx_unc_pcu::UNC_P_CLOCKTICKS:e=0:i=0:t=0", }, { SRC_LINE, .name = "bdx_unc_pcu::UNC_P_CLOCKTICKS:t=1", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1000000, .fstr = "bdx_unc_pcu::UNC_P_CLOCKTICKS:e=0:i=0:t=1", }, { SRC_LINE, .name = "bdx_unc_pcu::UNC_P_CORE0_TRANSITION_CYCLES", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x60, .fstr = "bdx_unc_pcu::UNC_P_CORE0_TRANSITION_CYCLES:e=0:i=0:t=0", }, { SRC_LINE, .name = "bdx_unc_pcu::UNC_P_CORE17_TRANSITION_CYCLES", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x71, .fstr = "bdx_unc_pcu::UNC_P_CORE17_TRANSITION_CYCLES:e=0:i=0:t=0", }, { SRC_LINE, .name = "bdx_unc_pcu::UNC_P_FREQ_BAND0_CYCLES", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "bdx_unc_pcu::UNC_P_FREQ_BAND1_CYCLES", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "bdx_unc_pcu::UNC_P_FREQ_BAND2_CYCLES", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "bdx_unc_pcu::UNC_P_FREQ_BAND3_CYCLES", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "bdx_unc_pcu::UNC_P_FREQ_BAND0_CYCLES:ff=32", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0xb, .codes[1] = 0x20, .fstr = "bdx_unc_pcu::UNC_P_FREQ_BAND0_CYCLES:e=0:i=0:t=0:ff=32", }, { SRC_LINE, .name = "bdx_unc_pcu::UNC_P_FREQ_BAND1_CYCLES:ff=16", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0xc, .codes[1] = 0x1000, .fstr = "bdx_unc_pcu::UNC_P_FREQ_BAND1_CYCLES:e=0:i=0:t=0:ff=16", }, { SRC_LINE, .name = "bdx_unc_pcu::UNC_P_FREQ_BAND2_CYCLES:ff=8", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0xd, .codes[1] = 0x80000, .fstr = "bdx_unc_pcu::UNC_P_FREQ_BAND2_CYCLES:e=0:i=0:t=0:ff=8", }, { SRC_LINE, .name = "bdx_unc_pcu::UNC_P_FREQ_BAND3_CYCLES:ff=40", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0xe, .codes[1] = 0x28000000, .fstr = "bdx_unc_pcu::UNC_P_FREQ_BAND3_CYCLES:e=0:i=0:t=0:ff=40", }, { SRC_LINE, .name = "bdx_unc_pcu::UNC_P_FREQ_BAND0_CYCLES:ff=32:e", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x4000b, .codes[1] = 0x20, .fstr = "bdx_unc_pcu::UNC_P_FREQ_BAND0_CYCLES:e=1:i=0:t=0:ff=32", }, { SRC_LINE, .name = "bdx_unc_pcu::UNC_P_FREQ_BAND0_CYCLES:ff=32:t=24", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x1800000b, .codes[1] = 0x20, .fstr = "bdx_unc_pcu::UNC_P_FREQ_BAND0_CYCLES:e=0:i=0:t=24:ff=32", }, { SRC_LINE, .name = "bdx_unc_pcu::UNC_P_FREQ_BAND0_CYCLES:ff=32:e:t=4", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x404000b, .codes[1] = 0x20, .fstr = "bdx_unc_pcu::UNC_P_FREQ_BAND0_CYCLES:e=1:i=0:t=4:ff=32", }, { SRC_LINE, .name = "bdx_unc_pcu::UNC_P_POWER_STATE_OCCUPANCY:CORES_C0", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x4080, .fstr = "bdx_unc_pcu::UNC_P_POWER_STATE_OCCUPANCY:CORES_C0:e=0:i=0:t=0" }, { SRC_LINE, .name = "bdx_unc_pcu::UNC_P_POWER_STATE_OCCUPANCY:CORES_C3", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x8080, .fstr = "bdx_unc_pcu::UNC_P_POWER_STATE_OCCUPANCY:CORES_C3:e=0:i=0:t=0", }, { SRC_LINE, .name = "bdx_unc_pcu::UNC_P_POWER_STATE_OCCUPANCY:CORES_C6", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0xc080, .fstr = "bdx_unc_pcu::UNC_P_POWER_STATE_OCCUPANCY:CORES_C6:e=0:i=0:t=0" }, { SRC_LINE, .name = "bdx_unc_pcu::UNC_P_POWER_STATE_OCCUPANCY:CORES_C0:t=6:i", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x6804080, .fstr = "bdx_unc_pcu::UNC_P_POWER_STATE_OCCUPANCY:CORES_C0:e=0:i=1:t=6" }, { SRC_LINE, .name = "bdx_unc_pcu::UNC_P_POWER_STATE_OCCUPANCY:CORES_C0:t=6", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x6004080, .fstr = "bdx_unc_pcu::UNC_P_POWER_STATE_OCCUPANCY:CORES_C0:e=0:i=0:t=6" }, { SRC_LINE, .name = "bdx_unc_pcu::UNC_P_DEMOTIONS_CORE10", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x3a, .fstr = "bdx_unc_pcu::UNC_P_DEMOTIONS_CORE10:e=0:i=0:t=0", }, { SRC_LINE, .name = "bdx_unc_pcu::UNC_P_DEMOTIONS_CORE14", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x3e, .fstr = "bdx_unc_pcu::UNC_P_DEMOTIONS_CORE14:e=0:i=0:t=0", }, { SRC_LINE, .name = "bdx_unc_pcu::UNC_P_DEMOTIONS_CORE17", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x41, .fstr = "bdx_unc_pcu::UNC_P_DEMOTIONS_CORE17:e=0:i=0:t=0", }, { SRC_LINE, .name = "bdx_unc_ha0::UNC_H_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x0, .fstr = "bdx_unc_ha0::UNC_H_CLOCKTICKS:e=0:i=0:t=0", }, { SRC_LINE, .name = "bdx_unc_ha1::UNC_H_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x0, .fstr = "bdx_unc_ha1::UNC_H_CLOCKTICKS:e=0:i=0:t=0", }, { SRC_LINE, .name = "bdx_unc_ha1::UNC_H_REQUESTS:READS:t=1", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1000301, .fstr = "bdx_unc_ha1::UNC_H_REQUESTS:READS:e=0:i=0:t=1", }, { SRC_LINE, .name = "bdx_unc_ha0::UNC_H_IMC_WRITES:t=1", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1000f1a, .fstr = "bdx_unc_ha0::UNC_H_IMC_WRITES:ALL:e=0:i=0:t=1", }, { SRC_LINE, .name = "bdx_unc_ha0::UNC_H_IMC_READS:t=1", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1000117, .fstr = "bdx_unc_ha0::UNC_H_IMC_READS:NORMAL:e=0:i=0:t=1", }, { SRC_LINE, .name = "bdx_unc_imc0::UNC_M_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0xff, .fstr = "bdx_unc_imc0::UNC_M_CLOCKTICKS", }, { SRC_LINE, .name = "bdx_unc_imc1::UNC_M_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0xff, .fstr = "bdx_unc_imc1::UNC_M_CLOCKTICKS", }, { SRC_LINE, .name = "bdx_unc_imc2::UNC_M_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0xff, .fstr = "bdx_unc_imc2::UNC_M_CLOCKTICKS", }, { SRC_LINE, .name = "bdx_unc_imc3::UNC_M_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0xff, .fstr = "bdx_unc_imc3::UNC_M_CLOCKTICKS", }, { SRC_LINE, .name = "bdx_unc_imc4::UNC_M_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0xff, .fstr = "bdx_unc_imc4::UNC_M_CLOCKTICKS", }, { SRC_LINE, .name = "bdx_unc_imc5::UNC_M_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0xff, .fstr = "bdx_unc_imc5::UNC_M_CLOCKTICKS", }, { SRC_LINE, .name = "bdx_unc_imc6::UNC_M_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0xff, .fstr = "bdx_unc_imc6::UNC_M_CLOCKTICKS", }, { SRC_LINE, .name = "bdx_unc_imc7::UNC_M_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0xff, .fstr = "bdx_unc_imc7::UNC_M_CLOCKTICKS", }, { SRC_LINE, .name = "bdx_unc_imc0::UNC_M_CLOCKTICKS:t=1", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "bdx_unc_imc0::UNC_M_DCLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x00, .fstr = "bdx_unc_imc0::UNC_M_DCLOCKTICKS:e=0:i=0:t=0", }, { SRC_LINE, .name = "bdx_unc_imc4::UNC_M_DCLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x00, .fstr = "bdx_unc_imc4::UNC_M_DCLOCKTICKS:e=0:i=0:t=0", }, { SRC_LINE, .name = "bdx_unc_imc0::UNC_M_CAS_COUNT:RD", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x0304, .fstr = "bdx_unc_imc0::UNC_M_CAS_COUNT:RD:e=0:i=0:t=0", }, { SRC_LINE, .name = "bdx_unc_imc0::UNC_M_PRE_COUNT:WR", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x0802, .fstr = "bdx_unc_imc0::UNC_M_PRE_COUNT:WR:e=0:i=0:t=0", }, { SRC_LINE, .name = "bdx_unc_imc0::UNC_M_POWER_CKE_CYCLES:RANK0", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x183, .fstr = "bdx_unc_imc0::UNC_M_POWER_CKE_CYCLES:RANK0:e=0:i=0:t=0", }, { SRC_LINE, .name = "bdx_unc_imc0::UNC_M_CAS_COUNT:WR", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0xc04, .fstr = "bdx_unc_imc0::UNC_M_CAS_COUNT:WR:e=0:i=0:t=0", }, { SRC_LINE, .name = "bdx_unc_imc0::UNC_M_RD_CAS_RANK0:BANK0", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0xb0, .fstr = "bdx_unc_imc0::UNC_M_RD_CAS_RANK0:BANK0:e=0:i=0:t=0", }, { SRC_LINE, .name = "bdx_unc_imc0::UNC_M_RD_CAS_RANK0:ALLBANKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x10b0, .fstr = "bdx_unc_imc0::UNC_M_RD_CAS_RANK0:ALLBANKS:e=0:i=0:t=0", }, { SRC_LINE, .name = "bdx_unc_imc0::UNC_M_RD_CAS_RANK0:BANKG0", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x11b0, .fstr = "bdx_unc_imc0::UNC_M_RD_CAS_RANK0:BANKG0:e=0:i=0:t=0", }, { SRC_LINE, .name = "bdx_unc_imc0::UNC_M_RD_CAS_RANK4:BANK7", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x7b4, .fstr = "bdx_unc_imc0::UNC_M_RD_CAS_RANK4:BANK7:e=0:i=0:t=0", }, { SRC_LINE, .name = "bdx_unc_imc0::UNC_M_RD_CAS_RANK4:BANK7:t=1", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x10007b4, .fstr = "bdx_unc_imc0::UNC_M_RD_CAS_RANK4:BANK7:e=0:i=0:t=1", }, { SRC_LINE, .name = "bdx_unc_imc0::UNC_M_RD_CAS_RANK7:BANK7:t=1:i", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x18007b7, .fstr = "bdx_unc_imc0::UNC_M_RD_CAS_RANK7:BANK7:e=0:i=1:t=1", }, { SRC_LINE, .name = "bdx_unc_sbo0::UNC_S_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x0, .fstr = "bdx_unc_sbo0::UNC_S_CLOCKTICKS:e=0:i=0:t=0", }, { SRC_LINE, .name = "bdx_unc_sbo0::UNC_S_FAST_ASSERTED:t=1:i", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1800009, .fstr = "bdx_unc_sbo0::UNC_S_FAST_ASSERTED:e=0:i=1:t=1", }, { SRC_LINE, .name = "bdx_unc_sbo3::UNC_S_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x0, .fstr = "bdx_unc_sbo3::UNC_S_CLOCKTICKS:e=0:i=0:t=0", }, { SRC_LINE, .name = "bdx_unc_sbo3::UNC_S_FAST_ASSERTED:t=1:i", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1800009, .fstr = "bdx_unc_sbo3::UNC_S_FAST_ASSERTED:e=0:i=1:t=1", }, { SRC_LINE, .name = "bdx_unc_ubo::UNC_U_EVENT_MSG", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x842, .fstr = "bdx_unc_ubo::UNC_U_EVENT_MSG:DOORBELL_RCVD:e=0:i=0:t=0", }, { SRC_LINE, .name = "bdx_unc_qpi0::UNC_Q_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x14, .fstr = "bdx_unc_qpi0::UNC_Q_CLOCKTICKS:e=0:i=0:t=0", }, { SRC_LINE, .name = "bdx_unc_qpi1::UNC_Q_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x14, .fstr = "bdx_unc_qpi1::UNC_Q_CLOCKTICKS:e=0:i=0:t=0", }, { SRC_LINE, .name = "bdx_unc_qpi2::UNC_Q_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x14, .fstr = "bdx_unc_qpi2::UNC_Q_CLOCKTICKS:e=0:i=0:t=0", }, { SRC_LINE, .name = "bdx_unc_qpi0::UNC_Q_DIRECT2CORE:SUCCESS_RBT_HIT", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x113, .fstr = "bdx_unc_qpi0::UNC_Q_DIRECT2CORE:SUCCESS_RBT_HIT:e=0:i=0:t=0", }, { SRC_LINE, .name = "bdx_unc_qpi0::UNC_Q_RXL_FLITS_G1:DRS:i:t=1", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1a01802, .fstr = "bdx_unc_qpi0::UNC_Q_RXL_FLITS_G1:DRS:e=0:i=1:t=1", }, { SRC_LINE, .name = "bdx_unc_qpi0::UNC_Q_TXL_FLITS_G2:NDR_AD", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x200101, .fstr = "bdx_unc_qpi0::UNC_Q_TXL_FLITS_G2:NDR_AD:e=0:i=0:t=0", }, { SRC_LINE, .name = "bdx_unc_qpi0::UNC_Q_RXL_OCCUPANCY", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0xb, .fstr = "bdx_unc_qpi0::UNC_Q_RXL_OCCUPANCY:e=0:i=0:t=0", }, { SRC_LINE, .name = "bdx_unc_qpi0::UNC_Q_TXL_INSERTS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x4, .fstr = "bdx_unc_qpi0::UNC_Q_TXL_INSERTS:e=0:i=0:t=0", }, { SRC_LINE, .name = "bdx_unc_r2pcie::UNC_R2_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1, .fstr = "bdx_unc_r2pcie::UNC_R2_CLOCKTICKS:e=0:i=0:t=0", }, { SRC_LINE, .name = "bdx_unc_r2pcie::UNC_R2_RING_AD_USED:CW", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x307, .fstr = "bdx_unc_r2pcie::UNC_R2_RING_AD_USED:CW:e=0:i=0:t=0", }, { SRC_LINE, .name = "bdx_unc_r3qpi0::UNC_R3_CLOCKTICKS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1, .fstr = "bdx_unc_r3qpi0::UNC_R3_CLOCKTICKS:e=0:i=0:t=0", }, { SRC_LINE, .name = "bdx_unc_r3qpi0::UNC_R3_RXR_CYCLES_NE:SNP:e=0:t=0", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x210, .fstr = "bdx_unc_r3qpi0::UNC_R3_RXR_CYCLES_NE:SNP:e=0:i=0:t=0", }, { SRC_LINE, .name = "bdx_unc_r3qpi1::UNC_R3_RING_SINK_STARVED", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x20e, .fstr = "bdx_unc_r3qpi1::UNC_R3_RING_SINK_STARVED:AK:e=0:i=0:t=0", }, { SRC_LINE, .name = "bdx_unc_r3qpi1::UNC_R3_HA_R2_BL_CREDITS_EMPTY:HA1:i:t=2", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x280022d, .fstr = "bdx_unc_r3qpi1::UNC_R3_HA_R2_BL_CREDITS_EMPTY:HA1:e=0:i=1:t=2", }, { SRC_LINE, .name = "amd64_fam17h::retired_uops", .count = 1, .codes[0] = 0x5300c1ull, .fstr = "amd64_fam17h::RETIRED_UOPS:k=1:u=1:e=0:i=0:c=0:h=0:g=0", }, { SRC_LINE, .name = "amd64_fam17h::cycles_not_in_halt", .count = 1, .codes[0] = 0x530076ull, .fstr = "amd64_fam17h::CYCLES_NOT_IN_HALT:k=1:u=1:e=0:i=0:c=0:h=0:g=0", }, { SRC_LINE, .name = "amd64_fam17h::locks:spec_lock", .count = 1, .codes[0] = 0x530425ull, .fstr = "amd64_fam17h::LOCKS:SPEC_LOCK:k=1:u=1:e=0:i=0:c=0:h=0:g=0", }, { SRC_LINE, .name = "amd64_fam17h::L1_DTLB_MISS:TLB_RELOAD_1G_L2_HIT:u", .count = 1, .codes[0] = 0x510845ull, .fstr = "amd64_fam17h::L1_DTLB_MISS:TLB_RELOAD_1G_L2_HIT:k=0:u=1:e=0:i=0:c=0:h=0:g=0", }, { SRC_LINE, .name = "amd64_fam16h::RETIRED_INSTRUCTIONS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x5300c0, .fstr = "amd64_fam16h::RETIRED_INSTRUCTIONS:k=1:u=1:e=0:i=0:c=0:h=0:g=0", }, { SRC_LINE, .name = "amd64_fam16h::CPU_CLK_UNHALTED:u", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x510076, .fstr = "amd64_fam16h::CPU_CLK_UNHALTED:k=0:u=1:e=0:i=0:c=0:h=0:g=0", }, { SRC_LINE, .name = "skx::offcore_response_1:pf_l1d_and_sw", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301bb, .codes[1] = 0x10400, .fstr = "skx::OFFCORE_RESPONSE_1:PF_L1D_AND_SW:ANY_RESPONSE:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0", }, { SRC_LINE, .name = "skx::offcore_response_0:any_request", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0x185b7, .fstr = "skx::OFFCORE_RESPONSE_0:DMND_DATA_RD:DMND_RFO:DMND_CODE_RD:PF_L2_DATA_RD:PF_L2_RFO:PF_L3_DATA_RD:PF_L3_RFO:PF_L1D_AND_SW:OTHER:ANY_RESPONSE:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0", }, { SRC_LINE, .name = "skx::offcore_response_0:snp_any", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0x3f800185b7ull, .fstr = "skx::OFFCORE_RESPONSE_0:ANY_REQUEST:ANY_RESPONSE:SNP_NONE:SNP_NOT_NEEDED:SNP_MISS:SNP_HIT_NO_FWD:SNP_HIT_WITH_FWD:SNP_HITM:SNP_NON_DRAM:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0", }, { SRC_LINE, .name = "skx::offcore_response_0:l3_hitmesf", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0x3f803c85b7ull, .fstr = "skx::OFFCORE_RESPONSE_0:ANY_REQUEST:L3_HITM:L3_HITE:L3_HITS:L3_HITF:SNP_ANY:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0", }, { SRC_LINE, .name = "skx::offcore_response_0:L4_HIT_LOCAL_L4", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "skx::offcore_response_0:L3_MISS_LOCAL", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0x3f840085b7ull, .fstr = "skx::OFFCORE_RESPONSE_0:ANY_REQUEST:L3_MISS_LOCAL:SNP_ANY:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0", }, { SRC_LINE, .name = "skx::offcore_response_0:l3_miss", .ret = PFM_SUCCESS, .count = 2, .codes[0] =0x5301b7, .codes[1] = 0x3f840085b7ull, .fstr = "skx::OFFCORE_RESPONSE_0:ANY_REQUEST:L3_MISS_LOCAL:SNP_ANY:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0", }, { SRC_LINE, .name = "skx::mem_load_uops_l3_miss_retired:remote_hitm", .ret = PFM_SUCCESS, .count = 1, .codes[0] =0x5304d3, .fstr = "skx::MEM_LOAD_UOPS_L3_MISS_RETIRED:REMOTE_HITM:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0", }, { SRC_LINE, .name = "skx::mem_load_uops_l3_miss_retired:local_dram", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x5301d3, .fstr = "skx::MEM_LOAD_UOPS_L3_MISS_RETIRED:LOCAL_DRAM:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0", }, }; #define NUM_TEST_EVENTS (int)(sizeof(x86_test_events)/sizeof(test_event_t)) static int check_pmu_supported(const char *evt) { pfm_pmu_info_t info; char *p; int i, ret; memset(&info, 0, sizeof(info)); info.size = sizeof(info); /* look for pmu_name::.... */ p = strchr(evt, ':'); if (!p) return 1; if (*(p+1) != ':') return 1; pfm_for_all_pmus(i) { ret = pfm_get_pmu_info(i, &info); if (ret != PFM_SUCCESS) continue; if (!strncmp(info.name, evt, p - evt)) return 1; } /* PMU not there */ return 0; } static int check_test_events(FILE *fp) { const test_event_t *e; char *fstr; uint64_t *codes; int count, i, j; int ret, errors = 0; for (i=0, e = x86_test_events; i < NUM_TEST_EVENTS; i++, e++) { codes = NULL; count = 0; fstr = NULL; ret = pfm_get_event_encoding(e->name, PFM_PLM0 | PFM_PLM3, &fstr, NULL, &codes, &count); if (ret != e->ret) { if (ret == PFM_ERR_NOTFOUND && !check_pmu_supported(e->name)) { fprintf(fp,"Line %d, Event%d %s, skipped because no PMU support\n", e->line, i, e->name); continue; } fprintf(fp,"Line %d, Event%d %s, ret=%s(%d) expected %s(%d)\n", e->line, i, e->name, pfm_strerror(ret), ret, pfm_strerror(e->ret), e->ret); errors++; } else { if (ret != PFM_SUCCESS) { if (fstr) { fprintf(fp,"Line %d, Event%d %s, expected fstr NULL but it is not\n", e->line, i, e->name); errors++; } if (count != 0) { fprintf(fp,"Line %d, Event%d %s, expected count=0 instead of %d\n", e->line, i, e->name, count); errors++; } if (codes) { fprintf(fp,"Line %d, Event%d %s, expected codes[] NULL but it is not\n", e->line, i, e->name); errors++; } } else { if (count != e->count) { fprintf(fp,"Line %d, Event%d %s, count=%d expected %d\n", e->line, i, e->name, count, e->count); errors++; } for (j=0; j < count; j++) { if (codes[j] != e->codes[j]) { fprintf(fp,"Line %d, Event%d %s, codes[%d]=%#"PRIx64" expected %#"PRIx64"\n", e->line, i, e->name, j, codes[j], e->codes[j]); errors++; } } if (e->fstr && strcmp(fstr, e->fstr)) { fprintf(fp,"Line %d, Event%d %s, fstr=%s expected %s\n", e->line, i, e->name, fstr, e->fstr); errors++; } } } if (codes) free(codes); if (fstr) free(fstr); } printf("\t %d x86 events: %d errors\n", i, errors); return errors; } int validate_arch(FILE *fp) { return check_test_events(fp); } libpfm-4.9.0/tests/validate.c0000664000175000017500000001725513223402656015727 0ustar eranianeranian/* * validate.c - validate event tables + encodings * * Copyright (c) 2010 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. */ #include #include #include #include #include #include #include #include #include #include #ifdef __linux__ #include #endif #define __weak_func __attribute__((weak)) #ifdef PFMLIB_WINDOWS int set_env_var(const char *var, const char *value, int ov) { size_t len; char *str; int ret; len = strlen(var) + 1 + strlen(value) + 1; str = malloc(len); if (!str) return PFM_ERR_NOMEM; sprintf(str, "%s=%s", var, value); ret = putenv(str); free(str); return ret ? PFM_ERR_INVAL : PFM_SUCCESS; } #else static inline int set_env_var(const char *var, const char *value, int ov) { return setenv(var, value, ov); } #endif __weak_func int validate_arch(FILE *fp) { return 0; } static struct { int valid_intern; int valid_arch; } options; static void usage(void) { printf("validate [-c] [-a] [-A]\n" "-c\trun the library validate events\n" "-a\trun architecture specific event tests\n" "-A\trun all tests\n" "-h\tget help\n"); } static int validate_event_tables(void) { pfm_pmu_info_t pinfo; int i, ret, errors = 0; memset(&pinfo, 0, sizeof(pinfo)); pinfo.size = sizeof(pinfo); pfm_for_all_pmus(i) { ret = pfm_get_pmu_info(i, &pinfo); if (ret != PFM_SUCCESS) continue; printf("\tchecking %s (%d events): ", pinfo.name, pinfo.nevents); fflush(stdout); ret = pfm_pmu_validate(i, stdout); if (ret != PFM_SUCCESS && ret != PFM_ERR_NOTSUPP) { printf("Failed\n"); errors++; } else if (ret == PFM_ERR_NOTSUPP) { printf("N/A\n"); } else { printf("Passed\n"); } } return errors; } #if __WORDSIZE == 64 #define STRUCT_MULT 8 #else #define STRUCT_MULT 4 #endif #define MAX_FIELDS 32 typedef struct { const char *name; size_t sz; } field_desc_t; typedef struct { const char *name; size_t sz; size_t bitfield_sz; size_t abi_sz; field_desc_t fields[MAX_FIELDS]; } struct_desc_t; #define LAST_STRUCT { .name = NULL, } #define FIELD(n, st) \ { .name = #n, \ .sz = sizeof(((st *)(0))->n), \ } #define LAST_FIELD { .name = NULL, } static const struct_desc_t pfmlib_structs[]={ { .name = "pfm_pmu_info_t", .sz = sizeof(pfm_pmu_info_t), .bitfield_sz = 4, .abi_sz = PFM_PMU_INFO_ABI0, .fields= { FIELD(name, pfm_pmu_info_t), FIELD(desc, pfm_pmu_info_t), FIELD(size, pfm_pmu_info_t), FIELD(pmu, pfm_pmu_info_t), FIELD(type, pfm_pmu_info_t), FIELD(nevents, pfm_pmu_info_t), FIELD(first_event, pfm_pmu_info_t), FIELD(max_encoding, pfm_pmu_info_t), FIELD(num_cntrs, pfm_pmu_info_t), FIELD(num_fixed_cntrs, pfm_pmu_info_t), LAST_FIELD }, }, { .name = "pfm_event_info_t", .sz = sizeof(pfm_event_info_t), .bitfield_sz = 4, .abi_sz = PFM_EVENT_INFO_ABI0, .fields= { FIELD(name, pfm_event_info_t), FIELD(desc, pfm_event_info_t), FIELD(equiv, pfm_event_info_t), FIELD(size, pfm_event_info_t), FIELD(code, pfm_event_info_t), FIELD(pmu, pfm_event_info_t), FIELD(dtype, pfm_event_info_t), FIELD(idx, pfm_event_info_t), FIELD(nattrs, pfm_event_info_t), FIELD(reserved, pfm_event_info_t), LAST_FIELD }, }, { .name = "pfm_event_attr_info_t", .sz = sizeof(pfm_event_attr_info_t), .bitfield_sz = 4+8, .abi_sz = PFM_ATTR_INFO_ABI0, .fields= { FIELD(name, pfm_event_attr_info_t), FIELD(desc, pfm_event_attr_info_t), FIELD(equiv, pfm_event_attr_info_t), FIELD(size, pfm_event_attr_info_t), FIELD(code, pfm_event_attr_info_t), FIELD(type, pfm_event_attr_info_t), FIELD(idx, pfm_event_attr_info_t), FIELD(ctrl, pfm_event_attr_info_t), LAST_FIELD }, }, { .name = "pfm_pmu_encode_arg_t", .sz = sizeof(pfm_pmu_encode_arg_t), .abi_sz = PFM_RAW_ENCODE_ABI0, .fields= { FIELD(codes, pfm_pmu_encode_arg_t), FIELD(fstr, pfm_pmu_encode_arg_t), FIELD(size, pfm_pmu_encode_arg_t), FIELD(count, pfm_pmu_encode_arg_t), FIELD(idx, pfm_pmu_encode_arg_t), LAST_FIELD }, }, #ifdef __linux__ { .name = "pfm_perf_encode_arg_t", .sz = sizeof(pfm_perf_encode_arg_t), .bitfield_sz = 0, .abi_sz = PFM_PERF_ENCODE_ABI0, .fields= { FIELD(attr, pfm_perf_encode_arg_t), FIELD(fstr, pfm_perf_encode_arg_t), FIELD(size, pfm_perf_encode_arg_t), FIELD(idx, pfm_perf_encode_arg_t), FIELD(cpu, pfm_perf_encode_arg_t), FIELD(flags, pfm_perf_encode_arg_t), FIELD(pad0, pfm_perf_encode_arg_t), LAST_FIELD }, }, #endif LAST_STRUCT }; static int validate_structs(void) { const struct_desc_t *d; const field_desc_t *f; size_t sz; int errors = 0; int abi = LIBPFM_ABI_VERSION; printf("\tlibpfm ABI version : %d\n", abi); for (d = pfmlib_structs; d->name; d++) { printf("\t%s : ", d->name); if (d->abi_sz != d->sz) { printf("struct size does not correspond to ABI size %zu vs. %zu)\n", d->abi_sz, d->sz); errors++; } if (d->sz % STRUCT_MULT) { printf("Failed (wrong mult size=%zu)\n", d->sz); errors++; } sz = d->bitfield_sz; for (f = d->fields; f->name; f++) { sz += f->sz; } if (sz != d->sz) { printf("Failed (invisible padding of %zu bytes, total struct size %zu bytes)\n", d->sz - sz, d->sz); errors++; continue; } printf("Passed\n"); } return errors; } int main(int argc, char **argv) { int ret, c, errors = 0; while ((c=getopt(argc, argv,"hcaA")) != -1) { switch(c) { case 'c': options.valid_intern = 1; break; case 'a': options.valid_arch = 1; break; case 'A': options.valid_arch = 1; options.valid_intern = 1; break; case 'h': usage(); exit(0); default: errx(1, "unknown option error"); } } /* to allow encoding of events from non detected PMU models */ ret = set_env_var("LIBPFM_ENCODE_INACTIVE", "1", 1); if (ret != PFM_SUCCESS) errx(1, "cannot force inactive encoding"); ret = pfm_initialize(); if (ret != PFM_SUCCESS) errx(1, "cannot initialize libpfm: %s", pfm_strerror(ret)); /* run everything by default */ if (!(options.valid_intern || options.valid_arch)) { options.valid_intern = 1; options.valid_arch = 1; } printf("Libpfm structure tests:\n"); errors += validate_structs(); if (options.valid_intern) { printf("Libpfm internal table tests:\n"); errors += validate_event_tables(); } if (options.valid_arch) { printf("Architecture specific tests:\n"); errors += validate_arch(stderr); } pfm_terminate(); if (errors) printf("Total %d errors\n", errors); else printf("All tests passed\n"); return errors; } libpfm-4.9.0/tests/validate_mips.c0000664000175000017500000001347213223402656016754 0ustar eranianeranian/* * validate_mips.c - validate MIPS event tables + encodings * * Copyright (c) 2011 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ #include #include #include #include #include #include #include #include #include #define MAX_ENCODING 2 #define SRC_LINE .line = __LINE__ typedef struct { const char *name; const char *fstr; uint64_t codes[MAX_ENCODING]; int ret, count, line; } test_event_t; static const test_event_t mips_test_events[]={ { SRC_LINE, .name = "mips_74k::cycles", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0xa, .codes[1] = 0xf, .fstr = "mips_74k::CYCLES:k=1:u=1:s=0:e=0", }, { SRC_LINE, .name = "mips_74k::cycles:k", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x2, .codes[1] = 0xf, .fstr = "mips_74k::CYCLES:k=1:u=0:s=0:e=0", }, { SRC_LINE, .name = "mips_74k::cycles:u", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x8, .codes[1] = 0xf, .fstr = "mips_74k::CYCLES:k=0:u=1:s=0:e=0", }, { SRC_LINE, .name = "mips_74k::cycles:s", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x4, .codes[1] = 0xf, .fstr = "mips_74k::CYCLES:k=0:u=0:s=1:e=0", }, { SRC_LINE, .name = "mips_74k::cycles:e", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x1, .codes[1] = 0xf, .fstr = "mips_74k::CYCLES:k=0:u=0:s=0:e=1", }, { SRC_LINE, .name = "mips_74k::cycles:u:k", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0xa, .codes[1] = 0xf, .fstr = "mips_74k::CYCLES:k=1:u=1:s=0:e=0", }, { SRC_LINE, .name = "mips_74k::instructions", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x2a, .codes[1] = 0xf, .fstr = "mips_74k::INSTRUCTIONS:k=1:u=1:s=0:e=0", }, { SRC_LINE, .name = "mips_74k::instructions:k", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x22, .codes[1] = 0xf, .fstr = "mips_74k::INSTRUCTIONS:k=1:u=0:s=0:e=0", }, { SRC_LINE, .name = "mips_74k::instructions:u", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x28, .codes[1] = 0xf, .fstr = "mips_74k::INSTRUCTIONS:k=0:u=1:s=0:e=0", }, { SRC_LINE, .name = "mips_74k::instructions:s", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x24, .codes[1] = 0xf, .fstr = "mips_74k::INSTRUCTIONS:k=0:u=0:s=1:e=0", }, { SRC_LINE, .name = "mips_74k::instructions:e", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x21, .codes[1] = 0xf, .fstr = "mips_74k::INSTRUCTIONS:k=0:u=0:s=0:e=1", }, { SRC_LINE, .name = "mips_74k::instructions:u:k", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x2a, .codes[1] = 0xf, .fstr = "mips_74k::INSTRUCTIONS:k=1:u=1:s=0:e=0", }, { SRC_LINE, .name = "mips_74k::PREDICTED_JR_31:u:k", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x4a, .codes[1] = 0x5, .fstr = "mips_74k::PREDICTED_JR_31:k=1:u=1:s=0:e=0", }, { SRC_LINE, .name = "mips_74k::JR_31_MISPREDICTIONS:s:e", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x45, .codes[1] = 0xa, .fstr = "mips_74k::JR_31_MISPREDICTIONS:k=0:u=0:s=1:e=1", }, }; #define NUM_TEST_EVENTS (int)(sizeof(mips_test_events)/sizeof(test_event_t)) static int check_test_events(FILE *fp) { const test_event_t *e; char *fstr; uint64_t *codes; int count, i, j; int ret, errors = 0; for (i = 0, e = mips_test_events; i < NUM_TEST_EVENTS; i++, e++) { codes = NULL; count = 0; fstr = NULL; ret = pfm_get_event_encoding(e->name, PFM_PLM0 | PFM_PLM3, &fstr, NULL, &codes, &count); if (ret != e->ret) { fprintf(fp,"Event%d %s, ret=%s(%d) expected %s(%d)\n", i, e->name, pfm_strerror(ret), ret, pfm_strerror(e->ret), e->ret); errors++; } else { if (ret != PFM_SUCCESS) { if (fstr) { fprintf(fp,"Event%d %s, expected fstr NULL but it is not\n", i, e->name); errors++; } if (count != 0) { fprintf(fp,"Event%d %s, expected count=0 instead of %d\n", i, e->name, count); errors++; } if (codes) { fprintf(fp,"Event%d %s, expected codes[] NULL but it is not\n", i, e->name); errors++; } } else { if (count != e->count) { fprintf(fp,"Event%d %s, count=%d expected %d\n", i, e->name, count, e->count); errors++; } for (j=0; j < count; j++) { if (codes[j] != e->codes[j]) { fprintf(fp,"Event%d %s, codes[%d]=%#"PRIx64" expected %#"PRIx64"\n", i, e->name, j, codes[j], e->codes[j]); errors++; } } if (e->fstr && strcmp(fstr, e->fstr)) { fprintf(fp,"Event%d %s, fstr=%s expected %s\n", i, e->name, fstr, e->fstr); errors++; } } } if (codes) free(codes); if (fstr) free(fstr); } printf("\t %d MIPS events: %d errors\n", i, errors); return errors; } int validate_arch(FILE *fp) { return check_test_events(fp); } libpfm-4.9.0/tests/validate_power.c0000664000175000017500000001571713223402656017144 0ustar eranianeranian/* * validate_power.c - validate PowerPC event tables + encodings * * Copyright (c) 2012 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ #include #include #include #include #include #include #include #include #include #define MAX_ENCODING 1 #define SRC_LINE .line = __LINE__ typedef struct { const char *name; const char *fstr; uint64_t codes[MAX_ENCODING]; int ret, count, line; } test_event_t; static const test_event_t ppc_test_events[]={ { SRC_LINE, .name = "ppc970::PM_CYC", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x7, .fstr = "ppc970::PM_CYC", }, { SRC_LINE, .name = "ppc970::PM_INST_DISP", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x320, .fstr = "ppc970::PM_INST_DISP", }, { SRC_LINE, .name = "ppc970mp::PM_CYC", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x7, .fstr = "ppc970mp::PM_CYC", }, { SRC_LINE, .name = "ppc970mp::PM_INST_DISP", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x320, .fstr = "ppc970mp::PM_INST_DISP", }, { SRC_LINE, .name = "power4::PM_CYC", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x7, .fstr = "power4::PM_CYC", }, { SRC_LINE, .name = "power4::PM_INST_DISP", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x221, .fstr = "power4::PM_INST_DISP", }, { SRC_LINE, .name = "power5::PM_CYC", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0xf, .fstr = "power5::PM_CYC", }, { SRC_LINE, .name = "power5::PM_INST_DISP", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x300009, .fstr = "power5::PM_INST_DISP", }, { SRC_LINE, .name = "power5p::PM_CYC", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0xf, .fstr = "power5p::PM_CYC", }, { SRC_LINE, .name = "power5p::PM_INST_DISP", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x300009, .fstr = "power5p::PM_INST_DISP", }, { SRC_LINE, .name = "power6::PM_INST_CMPL", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x2, .fstr = "power6::PM_INST_CMPL", }, { SRC_LINE, .name = "power6::PM_THRD_CONC_RUN_INST", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x300026, .fstr = "power6::PM_THRD_CONC_RUN_INST", }, { SRC_LINE, .name = "power7::PM_CYC", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1e, .fstr = "power7::PM_CYC", }, { SRC_LINE, .name = "power7::PM_INST_DISP", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x200f2, .fstr = "power7::PM_INST_DISP", }, { SRC_LINE, .name = "power8::PM_L1MISS_LAT_EXC_1024", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x67200301eaull, .fstr = "power8::PM_L1MISS_LAT_EXC_1024", }, { SRC_LINE, .name = "power8::PM_RC_LIFETIME_EXC_32", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0xde200201e6ull, .fstr = "power8::PM_RC_LIFETIME_EXC_32", }, { SRC_LINE, .name = "power9::PM_CYC", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1001e, .fstr = "power9::PM_CYC", }, { SRC_LINE, .name = "power9::PM_INST_DISP", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x200f2, .fstr = "power9::PM_INST_DISP", }, { SRC_LINE, .name = "power9::PM_CYC_ALT", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x2001e, .fstr = "power9::PM_CYC_ALT", }, { SRC_LINE, .name = "power9::PM_CYC_ALT2", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x3001e, .fstr = "power9::PM_CYC_ALT2", }, { SRC_LINE, .name = "power9::PM_INST_CMPL_ALT", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x20002, .fstr = "power9::PM_INST_CMPL_ALT", }, { SRC_LINE, .name = "power9::PM_L2_INST_MISS_ALT", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x4609e, .fstr = "power9::PM_L2_INST_MISS_ALT", }, { SRC_LINE, .name = "power9::PM_L2_INST_MISS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x36880, .fstr = "power9::PM_L2_INST_MISS", }, { SRC_LINE, .name = "powerpc_nest_mcs_read::MCS_00", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x118, .fstr = "powerpc_nest_mcs_read::MCS_00", }, { SRC_LINE, .name = "powerpc_nest_mcs_write::MCS_00", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x198, .fstr = "powerpc_nest_mcs_write::MCS_00", }, }; #define NUM_TEST_EVENTS (int)(sizeof(ppc_test_events)/sizeof(test_event_t)) static int check_test_events(FILE *fp) { const test_event_t *e; char *fstr; uint64_t *codes; int count, i, j; int ret, errors = 0; for (i = 0, e = ppc_test_events; i < NUM_TEST_EVENTS; i++, e++) { codes = NULL; count = 0; fstr = NULL; ret = pfm_get_event_encoding(e->name, PFM_PLM0 | PFM_PLM3, &fstr, NULL, &codes, &count); if (ret != e->ret) { fprintf(fp,"Event%d %s, ret=%s(%d) expected %s(%d)\n", i, e->name, pfm_strerror(ret), ret, pfm_strerror(e->ret), e->ret); errors++; } else { if (ret != PFM_SUCCESS) { if (fstr) { fprintf(fp,"Event%d %s, expected fstr NULL but it is not\n", i, e->name); errors++; } if (count != 0) { fprintf(fp,"Event%d %s, expected count=0 instead of %d\n", i, e->name, count); errors++; } if (codes) { fprintf(fp,"Event%d %s, expected codes[] NULL but it is not\n", i, e->name); errors++; } } else { if (count != e->count) { fprintf(fp,"Event%d %s, count=%d expected %d\n", i, e->name, count, e->count); errors++; } for (j=0; j < count; j++) { if (codes[j] != e->codes[j]) { fprintf(fp,"Event%d %s, codes[%d]=%#"PRIx64" expected %#"PRIx64"\n", i, e->name, j, codes[j], e->codes[j]); errors++; } } if (e->fstr && strcmp(fstr, e->fstr)) { fprintf(fp,"Event%d %s, fstr=%s expected %s\n", i, e->name, fstr, e->fstr); errors++; } } } if (codes) free(codes); if (fstr) free(fstr); } printf("\t %d PowerPC events: %d errors\n", i, errors); return errors; } int validate_arch(FILE *fp) { return check_test_events(fp); } libpfm-4.9.0/tests/validate_arm.c0000664000175000017500000002007413223402656016557 0ustar eranianeranian/* * validate_arm.c - validate ARM event tables + encodings * * Copyright (c) 2011 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ #include #include #include #include #include #include #include #include #include #define MAX_ENCODING 1 #define SRC_LINE .line = __LINE__ typedef struct { const char *name; const char *fstr; uint64_t codes[MAX_ENCODING]; int ret, count, line; } test_event_t; static const test_event_t arm_test_events[]={ { SRC_LINE, .name = "arm_ac7::CPU_CYCLES", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x8000011, .fstr = "arm_ac7::CPU_CYCLES:k=1:u=1:hv=0", }, { SRC_LINE, .name = "arm_ac7::CPU_CYCLES:k", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x88000011, .fstr = "arm_ac7::CPU_CYCLES:k=1:u=0:hv=0", }, { SRC_LINE, .name = "arm_ac7::CPU_CYCLES:k:u", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x8000011, .fstr = "arm_ac7::CPU_CYCLES:k=1:u=1:hv=0", }, { SRC_LINE, .name = "arm_ac7::INST_RETIRED", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x8000008, .fstr = "arm_ac7::INST_RETIRED:k=1:u=1:hv=0", }, { SRC_LINE, .name = "arm_ac8::NEON_CYCLES", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x5a, .fstr = "arm_ac8::NEON_CYCLES", }, { SRC_LINE, .name = "arm_ac8::NEON_CYCLES:k", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "arm_ac8::CPU_CYCLES", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0xff, .fstr = "arm_ac8::CPU_CYCLES", }, { SRC_LINE, .name = "arm_ac8::CPU_CYCLES_HALTED", .ret = PFM_ERR_NOTFOUND, }, { SRC_LINE, .name = "arm_ac9::CPU_CYCLES", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0xff, .fstr = "arm_ac9::CPU_CYCLES", }, { SRC_LINE, .name = "arm_ac9::DMB_DEP_STALL_CYCLES", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x86, .fstr = "arm_ac9::DMB_DEP_STALL_CYCLES", }, { SRC_LINE, .name = "arm_ac9::CPU_CYCLES:u", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "arm_ac9::JAVA_HW_BYTECODE_EXEC", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x40, .fstr = "arm_ac9::JAVA_HW_BYTECODE_EXEC", }, { SRC_LINE, .name = "arm_ac15::CPU_CYCLES", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x8000011, .fstr = "arm_ac15::CPU_CYCLES:k=1:u=1:hv=0", }, { SRC_LINE, .name = "arm_ac15::CPU_CYCLES:k", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x88000011, .fstr = "arm_ac15::CPU_CYCLES:k=1:u=0:hv=0", }, { SRC_LINE, .name = "arm_ac15::CPU_CYCLES:k:u", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x8000011, .fstr = "arm_ac15::CPU_CYCLES:k=1:u=1:hv=0", }, { SRC_LINE, .name = "arm_ac15::INST_RETIRED", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x8000008, .fstr = "arm_ac15::INST_RETIRED:k=1:u=1:hv=0", }, { SRC_LINE, .name = "arm_1176::CPU_CYCLES", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0xff, .fstr = "arm_1176::CPU_CYCLES", }, { SRC_LINE, .name = "arm_1176::CPU_CYCLES:k", .ret = PFM_ERR_ATTR, }, { SRC_LINE, .name = "arm_1176::INSTR_EXEC", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x07, .fstr = "arm_1176::INSTR_EXEC", }, { SRC_LINE, .name = "qcom_krait::CPU_CYCLES", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x80000ff, .fstr = "qcom_krait::CPU_CYCLES:k=1:u=1:hv=0", }, { SRC_LINE, .name = "qcom_krait::CPU_CYCLES:k:u", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x80000ff, .fstr = "qcom_krait::CPU_CYCLES:k=1:u=1:hv=0", }, { SRC_LINE, .name = "qcom_krait::CPU_CYCLES:u", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x480000ff, .fstr = "qcom_krait::CPU_CYCLES:k=0:u=1:hv=0", }, { SRC_LINE, .name = "arm_ac57::CPU_CYCLES", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x8000011, .fstr = "arm_ac57::CPU_CYCLES:k=1:u=1:hv=0", }, { SRC_LINE, .name = "arm_ac57::CPU_CYCLES:k", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x88000011, .fstr = "arm_ac57::CPU_CYCLES:k=1:u=0:hv=0", }, { SRC_LINE, .name = "arm_ac57::CPU_CYCLES:k:u", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x8000011, .fstr = "arm_ac57::CPU_CYCLES:k=1:u=1:hv=0", }, { SRC_LINE, .name = "arm_ac57::INST_RETIRED", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x8000008, .fstr = "arm_ac57::INST_RETIRED:k=1:u=1:hv=0", }, { SRC_LINE, .name = "arm_ac53::CPU_CYCLES", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x8000011, .fstr = "arm_ac53::CPU_CYCLES:k=1:u=1:hv=0", }, { SRC_LINE, .name = "arm_ac53::CPU_CYCLES:k", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x88000011, .fstr = "arm_ac53::CPU_CYCLES:k=1:u=0:hv=0", }, { SRC_LINE, .name = "arm_ac53::CPU_CYCLES:k:u", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x8000011, .fstr = "arm_ac53::CPU_CYCLES:k=1:u=1:hv=0", }, { SRC_LINE, .name = "arm_ac53::INST_RETIRED", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x8000008, .fstr = "arm_ac53::INST_RETIRED:k=1:u=1:hv=0", }, { SRC_LINE, .name = "arm_ac53::LD_RETIRED", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x8000006, .fstr = "arm_ac53::LD_RETIRED:k=1:u=1:hv=0", }, { SRC_LINE, .name = "arm_ac53::ST_RETIRED", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x8000007, .fstr = "arm_ac53::ST_RETIRED:k=1:u=1:hv=0", }, }; #define NUM_TEST_EVENTS (int)(sizeof(arm_test_events)/sizeof(test_event_t)) static int check_test_events(FILE *fp) { const test_event_t *e; char *fstr; uint64_t *codes; int count, i, j; int ret, errors = 0; for (i = 0, e = arm_test_events; i < NUM_TEST_EVENTS; i++, e++) { codes = NULL; count = 0; fstr = NULL; ret = pfm_get_event_encoding(e->name, PFM_PLM0 | PFM_PLM3, &fstr, NULL, &codes, &count); if (ret != e->ret) { fprintf(fp,"Event%d %s, ret=%s(%d) expected %s(%d)\n", i, e->name, pfm_strerror(ret), ret, pfm_strerror(e->ret), e->ret); errors++; } else { if (ret != PFM_SUCCESS) { if (fstr) { fprintf(fp,"Event%d %s, expected fstr NULL but it is not\n", i, e->name); errors++; } if (count != 0) { fprintf(fp,"Event%d %s, expected count=0 instead of %d\n", i, e->name, count); errors++; } if (codes) { fprintf(fp,"Event%d %s, expected codes[] NULL but it is not\n", i, e->name); errors++; } } else { if (count != e->count) { fprintf(fp,"Event%d %s, count=%d expected %d\n", i, e->name, count, e->count); errors++; } for (j=0; j < count; j++) { if (codes[j] != e->codes[j]) { fprintf(fp,"Event%d %s, codes[%d]=%#"PRIx64" expected %#"PRIx64"\n", i, e->name, j, codes[j], e->codes[j]); errors++; } } if (e->fstr && strcmp(fstr, e->fstr)) { fprintf(fp,"Event%d %s, fstr=%s expected %s\n", i, e->name, fstr, e->fstr); errors++; } } } if (codes) free(codes); if (fstr) free(fstr); } printf("\t %d ARM events: %d errors\n", i, errors); return errors; } int validate_arch(FILE *fp) { return check_test_events(fp); } libpfm-4.9.0/.gitignore0000664000175000017500000000135713223402656014614 0ustar eranianeranian# # NOTE! Don't add files that are generated in specific # subdirectories here. Add them in the ".gitignore" file # in that subdirectory instead. # # NOTE! Please use 'git ls-files -i --exclude-standard' # command after changing this file, to see if there are # any tracked files which get ignored after the change. # # Normal rules # .* *.o *.o.* *.a *.s *.lo *.ko *.so *.so.[0-9]* *.so.dbg *.mod.c *.i *.lst *.symtypes *.order modules.builtin *.elf *.bin *.gz *.bz2 *.lzma *.patch *.gcno CVS # # git files that we don't want to ignore even it they are dot-files # !.gitignore !.mailmap # stgit generated dirs patches-* # quilt's files patches series # cscope files cscope.* ncscope.* # gnu global files GPATH GRTAGS GSYMS GTAGS *.orig *~ \#*# libpfm-4.9.0/COPYING0000664000175000017500000000217613223402656013657 0ustar eranianeranianAll other files are published under the following license: Copyright (c) 2002-2006 Hewlett-Packard Development Company, L.P. Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. libpfm-4.9.0/lib/0000775000175000017500000000000013223402656013364 5ustar eranianeranianlibpfm-4.9.0/lib/pfmlib_intel_snbep_unc_imc.c0000664000175000017500000000534413223402656021066 0ustar eranianeranian/* * pfmlib_intel_snbep_unc_imc.c : Intel SandyBridge-EP Integrated Memory Controller (IMC) uncore PMU * * Copyright (c) 2012 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_intel_x86_priv.h" #include "pfmlib_intel_snbep_unc_priv.h" #include "events/intel_snbep_unc_imc_events.h" #define DEFINE_IMC_BOX(n) \ pfmlib_pmu_t intel_snbep_unc_imc##n##_support = { \ .desc = "Intel Sandy Bridge-EP IMC"#n" uncore", \ .name = "snbep_unc_imc"#n, \ .perf_name = "uncore_imc_"#n, \ .pmu = PFM_PMU_INTEL_SNBEP_UNC_IMC##n, \ .pme_count = LIBPFM_ARRAY_SIZE(intel_snbep_unc_m_pe), \ .type = PFM_PMU_TYPE_UNCORE, \ .num_cntrs = 4, \ .num_fixed_cntrs = 1, \ .max_encoding = 1, \ .pe = intel_snbep_unc_m_pe, \ .atdesc = snbep_unc_mods, \ .flags = PFMLIB_PMU_FL_RAW_UMASK\ | PFMLIB_PMU_FL_NO_SMPL,\ .pmu_detect = pfm_intel_snbep_unc_detect, \ .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding, \ PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding), \ .get_event_first = pfm_intel_x86_get_event_first, \ .get_event_next = pfm_intel_x86_get_event_next, \ .event_is_valid = pfm_intel_x86_event_is_valid, \ .validate_table = pfm_intel_x86_validate_table, \ .get_event_info = pfm_intel_x86_get_event_info, \ .get_event_attr_info = pfm_intel_x86_get_event_attr_info, \ PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs), \ .get_event_nattrs = pfm_intel_x86_get_event_nattrs, \ }; DEFINE_IMC_BOX(0); DEFINE_IMC_BOX(1); DEFINE_IMC_BOX(2); DEFINE_IMC_BOX(3); libpfm-4.9.0/lib/pfmlib_intel_ivbep_unc_pcu.c0000664000175000017500000000673513223402656021110 0ustar eranianeranian/* * pfmlib_intel_ivbep_unc_pcu.c : Intel IvyBridge-EP Power Control Unit (PCU) uncore PMU * * Copyright (c) 2014 Google Inc. All rights reserved * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_intel_x86_priv.h" #include "pfmlib_intel_snbep_unc_priv.h" #include "events/intel_ivbep_unc_pcu_events.h" static void display_pcu(void *this, pfmlib_event_desc_t *e, void *val) { const intel_x86_entry_t *pe = this_pe(this); pfm_snbep_unc_reg_t *reg = val; pfm_snbep_unc_reg_t f; __pfm_vbprintf("[UNC_PCU=0x%"PRIx64" event=0x%x sel_ext=%d occ_sel=0x%x en=%d " "edge=%d thres=%d occ_inv=%d occ_edge=%d] %s\n", reg->val, reg->ivbep_pcu.unc_event, reg->ivbep_pcu.unc_sel_ext, reg->ivbep_pcu.unc_occ, reg->ivbep_pcu.unc_en, reg->ivbep_pcu.unc_edge, reg->ivbep_pcu.unc_thres, reg->ivbep_pcu.unc_occ_inv, reg->ivbep_pcu.unc_occ_edge, pe[e->event].name); if (e->count == 1) return; f.val = e->codes[1]; __pfm_vbprintf("[UNC_PCU_FILTER=0x%"PRIx64" band0=%u band1=%u band2=%u band3=%u]\n", f.val, f.pcu_filt.filt0, f.pcu_filt.filt1, f.pcu_filt.filt2, f.pcu_filt.filt3); } pfmlib_pmu_t intel_ivbep_unc_pcu_support = { .desc = "Intel Ivy Bridge-EP PCU uncore", .name = "ivbep_unc_pcu", .perf_name = "uncore_pcu", .pmu = PFM_PMU_INTEL_IVBEP_UNC_PCU, .pme_count = LIBPFM_ARRAY_SIZE(intel_ivbep_unc_p_pe), .type = PFM_PMU_TYPE_UNCORE, .num_cntrs = 4, .num_fixed_cntrs = 0, .max_encoding = 2, .pe = intel_ivbep_unc_p_pe, .atdesc = snbep_unc_mods, .flags = PFMLIB_PMU_FL_RAW_UMASK, .pmu_detect = pfm_intel_ivbep_unc_detect, .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding, PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding), PFMLIB_OS_DETECT(pfm_intel_x86_perf_detect), .get_event_first = pfm_intel_x86_get_event_first, .get_event_next = pfm_intel_x86_get_event_next, .event_is_valid = pfm_intel_x86_event_is_valid, .validate_table = pfm_intel_x86_validate_table, .get_event_info = pfm_intel_x86_get_event_info, .get_event_attr_info = pfm_intel_x86_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs), .get_event_nattrs = pfm_intel_x86_get_event_nattrs, .can_auto_encode = pfm_intel_snbep_unc_can_auto_encode, .display_reg = display_pcu, }; libpfm-4.9.0/lib/pfmlib_intel_ivbep_unc_ubo.c0000664000175000017500000000510413223402656021073 0ustar eranianeranian/* * pfmlib_intel_ivbep_unc_ubo.c : Intel IvyBridge-EP U-Box uncore PMU * * Copyright (c) 2014 Google Inc. All rights reserved * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_intel_x86_priv.h" #include "pfmlib_intel_snbep_unc_priv.h" #include "events/intel_ivbep_unc_ubo_events.h" pfmlib_pmu_t intel_ivbep_unc_ubo_support = { .desc = "Intel Ivy Bridge-EP U-Box uncore", .name = "ivbep_unc_ubo", .perf_name = "uncore_ubox", .pmu = PFM_PMU_INTEL_IVBEP_UNC_UBOX, .pme_count = LIBPFM_ARRAY_SIZE(intel_ivbep_unc_u_pe), .type = PFM_PMU_TYPE_UNCORE, .num_cntrs = 2, .num_fixed_cntrs = 1, .max_encoding = 1, .pe = intel_ivbep_unc_u_pe, .atdesc = snbep_unc_mods, .flags = PFMLIB_PMU_FL_RAW_UMASK, .pmu_detect = pfm_intel_ivbep_unc_detect, .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding, PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding), PFMLIB_OS_DETECT(pfm_intel_x86_perf_detect), .get_event_first = pfm_intel_x86_get_event_first, .get_event_next = pfm_intel_x86_get_event_next, .event_is_valid = pfm_intel_x86_event_is_valid, .validate_table = pfm_intel_x86_validate_table, .get_event_info = pfm_intel_x86_get_event_info, .get_event_attr_info = pfm_intel_x86_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs), .get_event_nattrs = pfm_intel_x86_get_event_nattrs, }; libpfm-4.9.0/lib/pfmlib_intel_bdx_unc_pcu.c0000664000175000017500000000671013223402656020551 0ustar eranianeranian/* * pfmlib_intel_bdx_unc_pcu.c : Intel BroadwellX Power Control Unit (PCU) uncore PMU * * Copyright (c) 2017 Google Inc. All rights reserved * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_intel_x86_priv.h" #include "pfmlib_intel_snbep_unc_priv.h" #include "events/intel_bdx_unc_pcu_events.h" static void display_pcu(void *this, pfmlib_event_desc_t *e, void *val) { const intel_x86_entry_t *pe = this_pe(this); pfm_snbep_unc_reg_t *reg = val; pfm_snbep_unc_reg_t f; __pfm_vbprintf("[UNC_PCU=0x%"PRIx64" event=0x%x sel_ext=%d occ_sel=0x%x en=%d " "edge=%d thres=%d occ_inv=%d occ_edge=%d] %s\n", reg->val, reg->ivbep_pcu.unc_event, reg->ivbep_pcu.unc_sel_ext, reg->ivbep_pcu.unc_occ, reg->ivbep_pcu.unc_en, reg->ivbep_pcu.unc_edge, reg->ivbep_pcu.unc_thres, reg->ivbep_pcu.unc_occ_inv, reg->ivbep_pcu.unc_occ_edge, pe[e->event].name); if (e->count == 1) return; f.val = e->codes[1]; __pfm_vbprintf("[UNC_PCU_FILTER=0x%"PRIx64" band0=%u band1=%u band2=%u band3=%u]\n", f.val, f.pcu_filt.filt0, f.pcu_filt.filt1, f.pcu_filt.filt2, f.pcu_filt.filt3); } pfmlib_pmu_t intel_bdx_unc_pcu_support = { .desc = "Intel BroadwellX PCU uncore", .name = "bdx_unc_pcu", .perf_name = "uncore_pcu", .pmu = PFM_PMU_INTEL_BDX_UNC_PCU, .pme_count = LIBPFM_ARRAY_SIZE(intel_bdx_unc_p_pe), .type = PFM_PMU_TYPE_UNCORE, .num_cntrs = 4, .num_fixed_cntrs = 0, .max_encoding = 2, .pe = intel_bdx_unc_p_pe, .atdesc = snbep_unc_mods, .flags = PFMLIB_PMU_FL_RAW_UMASK, .pmu_detect = pfm_intel_bdx_unc_detect, .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding, PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding), PFMLIB_OS_DETECT(pfm_intel_x86_perf_detect), .get_event_first = pfm_intel_x86_get_event_first, .get_event_next = pfm_intel_x86_get_event_next, .event_is_valid = pfm_intel_x86_event_is_valid, .validate_table = pfm_intel_x86_validate_table, .get_event_info = pfm_intel_x86_get_event_info, .get_event_attr_info = pfm_intel_x86_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs), .get_event_nattrs = pfm_intel_x86_get_event_nattrs, .can_auto_encode = pfm_intel_snbep_unc_can_auto_encode, .display_reg = display_pcu, }; libpfm-4.9.0/lib/pfmlib_intel_knl_unc_edc.c0000664000175000017500000001053013223402656020517 0ustar eranianeranian/* * pfmlib_intel_knl_unc_edc.c : Intel KnightsLanding Integrated EDRAM uncore PMU * * Copyright (c) 2016 Intel Corp. All rights reserved * Contributed by Peinan Zhang * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_intel_x86_priv.h" #include "pfmlib_intel_snbep_unc_priv.h" #include "events/intel_knl_unc_edc_events.h" #define DEFINE_EDC_UCLK_BOX(n) \ pfmlib_pmu_t intel_knl_unc_edc_uclk##n##_support = { \ .desc = "Intel KnightLanding EDC_UCLK_"#n" uncore", \ .name = "knl_unc_edc_uclk"#n, \ .perf_name = "uncore_edc_uclk_"#n, \ .pmu = PFM_PMU_INTEL_KNL_UNC_EDC_UCLK##n, \ .pme_count = LIBPFM_ARRAY_SIZE(intel_knl_unc_edc_uclk_pe), \ .type = PFM_PMU_TYPE_UNCORE, \ .num_cntrs = 4, \ .num_fixed_cntrs = 0, \ .max_encoding = 1, \ .pe = intel_knl_unc_edc_uclk_pe, \ .atdesc = snbep_unc_mods, \ .flags = PFMLIB_PMU_FL_RAW_UMASK, \ .pmu_detect = pfm_intel_knl_unc_detect, \ .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding, \ PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding), \ PFMLIB_OS_DETECT(pfm_intel_x86_perf_detect), \ .get_event_first = pfm_intel_x86_get_event_first, \ .get_event_next = pfm_intel_x86_get_event_next, \ .event_is_valid = pfm_intel_x86_event_is_valid, \ .validate_table = pfm_intel_x86_validate_table, \ .get_event_info = pfm_intel_x86_get_event_info, \ .get_event_attr_info = pfm_intel_x86_get_event_attr_info, \ PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs), \ .get_event_nattrs = pfm_intel_x86_get_event_nattrs, \ }; DEFINE_EDC_UCLK_BOX(0); DEFINE_EDC_UCLK_BOX(1); DEFINE_EDC_UCLK_BOX(2); DEFINE_EDC_UCLK_BOX(3); DEFINE_EDC_UCLK_BOX(4); DEFINE_EDC_UCLK_BOX(5); DEFINE_EDC_UCLK_BOX(6); DEFINE_EDC_UCLK_BOX(7); #define DEFINE_EDC_ECLK_BOX(n) \ pfmlib_pmu_t intel_knl_unc_edc_eclk##n##_support = { \ .desc = "Intel KnightLanding EDC_ECLK_"#n" uncore", \ .name = "knl_unc_edc_eclk"#n, \ .perf_name = "uncore_edc_eclk_"#n, \ .pmu = PFM_PMU_INTEL_KNL_UNC_EDC_ECLK##n, \ .pme_count = LIBPFM_ARRAY_SIZE(intel_knl_unc_edc_eclk_pe), \ .type = PFM_PMU_TYPE_UNCORE, \ .num_cntrs = 4, \ .num_fixed_cntrs = 0, \ .max_encoding = 1, \ .pe = intel_knl_unc_edc_eclk_pe, \ .atdesc = snbep_unc_mods, \ .flags = PFMLIB_PMU_FL_RAW_UMASK, \ .pmu_detect = pfm_intel_knl_unc_detect, \ .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding, \ PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding), \ PFMLIB_OS_DETECT(pfm_intel_x86_perf_detect), \ .get_event_first = pfm_intel_x86_get_event_first, \ .get_event_next = pfm_intel_x86_get_event_next, \ .event_is_valid = pfm_intel_x86_event_is_valid, \ .validate_table = pfm_intel_x86_validate_table, \ .get_event_info = pfm_intel_x86_get_event_info, \ .get_event_attr_info = pfm_intel_x86_get_event_attr_info, \ PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs), \ .get_event_nattrs = pfm_intel_x86_get_event_nattrs, \ }; DEFINE_EDC_ECLK_BOX(0); DEFINE_EDC_ECLK_BOX(1); DEFINE_EDC_ECLK_BOX(2); DEFINE_EDC_ECLK_BOX(3); DEFINE_EDC_ECLK_BOX(4); DEFINE_EDC_ECLK_BOX(5); DEFINE_EDC_ECLK_BOX(6); DEFINE_EDC_ECLK_BOX(7); libpfm-4.9.0/lib/pfmlib_intel_glm.c0000664000175000017500000000502313223402656017033 0ustar eranianeranian/* * pfmlib_intel_glm.c : Intel Goldmont core PMU * * Copyright (c) 2016 Google * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_intel_x86_priv.h" #include "events/intel_glm_events.h" static const int glm_models[] = { 92, /* Goldmont */ 95, /* Goldmont Denverton */ 0 }; static int pfm_intel_glm_init(void *this) { pfm_intel_x86_cfg.arch_version = 3; return PFM_SUCCESS; } pfmlib_pmu_t intel_glm_support={ .desc = "Intel Goldmont", .name = "glm", .pmu = PFM_PMU_INTEL_GLM, .pme_count = LIBPFM_ARRAY_SIZE(intel_glm_pe), .type = PFM_PMU_TYPE_CORE, .num_cntrs = 4, .num_fixed_cntrs = 3, .max_encoding = 2, .pe = intel_glm_pe, .atdesc = intel_x86_mods, .flags = PFMLIB_PMU_FL_RAW_UMASK, .supported_plm = INTEL_X86_PLM, .cpu_family = 6, .cpu_models = glm_models, .pmu_detect = pfm_intel_x86_model_detect, .pmu_init = pfm_intel_glm_init, .get_event_encoding[PFM_OS_NONE] = pfm_intel_x86_get_encoding, PFMLIB_ENCODE_PERF(pfm_intel_x86_get_perf_encoding), .get_event_first = pfm_intel_x86_get_event_first, .get_event_next = pfm_intel_x86_get_event_next, .event_is_valid = pfm_intel_x86_event_is_valid, .validate_table = pfm_intel_x86_validate_table, .get_event_info = pfm_intel_x86_get_event_info, .get_event_attr_info = pfm_intel_x86_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_intel_x86_perf_validate_pattrs), .get_event_nattrs = pfm_intel_x86_get_event_nattrs, }; libpfm-4.9.0/lib/pfmlib_intel_netburst_perf_event.c0000664000175000017500000000560413223402656022344 0ustar eranianeranian/* pfmlib_intel_netburst_perf_event.c : perf_event Intel Netburst functions * * Copyright (c) 2011 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file implements the common code for all Intel X86 processors. */ #include #include #include #include #include /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_intel_netburst_priv.h" #include "pfmlib_perf_event_priv.h" int pfm_netburst_get_perf_encoding(void *this, pfmlib_event_desc_t *e) { const netburst_entry_t *pe = this_pe(this); struct perf_event_attr *attr = e->os_data; int perf_code = pe[e->event].perf_code; uint64_t escr; int ret; ret = pfm_netburst_get_encoding(this, e); if (ret != PFM_SUCCESS) return ret; attr->type = PERF_TYPE_RAW; /* * codes[0] = ESCR * codes[1] = CCCR * * cleanup event_select, and install perf specific code */ escr = e->codes[0] & ~(0x3full << 25); escr |= perf_code << 25; attr->config = (escr << 32) | e->codes[1]; return PFM_SUCCESS; } void pfm_netburst_perf_validate_pattrs(void *this, pfmlib_event_desc_t *e) { int i, compact; for (i = 0; i < e->npattrs; i++) { compact = 0; /* umasks never conflict */ if (e->pattrs[i].type == PFM_ATTR_UMASK) continue; /* * with perf_events, u and k are handled at the OS level * via exclude_user, exclude_kernel. */ if (e->pattrs[i].ctrl == PFM_ATTR_CTRL_PMU) { if (e->pattrs[i].idx == NETBURST_ATTR_U || e->pattrs[i].idx == NETBURST_ATTR_K) compact = 1; } if (e->pattrs[i].ctrl == PFM_ATTR_CTRL_PERF_EVENT) { /* no PEBS support (for now) */ if (e->pattrs[i].idx == PERF_ATTR_PR) compact = 1; /* * No hypervisor on Intel */ if (e->pattrs[i].idx == PERF_ATTR_H) compact = 1; } if (compact) { pfmlib_compact_pattrs(e, i); i--; } } } libpfm-4.9.0/lib/pfmlib_powerpc_nest.c0000664000175000017500000000460013223402656017571 0ustar eranianeranian/* * pfmlib_powerpc_nest.c */ #include "pfmlib_priv.h" #include "pfmlib_power_priv.h" #include "events/powerpc_nest_events.h" static int pfm_powerpc_nest_detect(void* this) { if (__is_processor(PV_POWER8)) return PFM_SUCCESS; return PFM_ERR_NOTSUPP; } pfmlib_pmu_t powerpc_nest_mcs_read_support={ .desc = "POWERPC_NEST_MCS_RD_BW", .name = "powerpc_nest_mcs_read", .pmu = PFM_PMU_POWERPC_NEST_MCS_READ_BW, .perf_name = "Nest_MCS_Read_BW", .pme_count = LIBPFM_ARRAY_SIZE(powerpc_nest_read_pe), .type = PFM_PMU_TYPE_UNCORE, .num_cntrs = 4, .num_fixed_cntrs = 0, .max_encoding = 1, .pe = powerpc_nest_read_pe, .pmu_detect = pfm_powerpc_nest_detect, .get_event_encoding[PFM_OS_NONE] = pfm_gen_powerpc_get_encoding, PFMLIB_ENCODE_PERF(pfm_gen_powerpc_get_nest_perf_encoding), PFMLIB_VALID_PERF_PATTRS(pfm_gen_powerpc_perf_validate_pattrs), .get_event_first = pfm_gen_powerpc_get_event_first, .get_event_next = pfm_gen_powerpc_get_event_next, .event_is_valid = pfm_gen_powerpc_event_is_valid, .validate_table = pfm_gen_powerpc_validate_table, .get_event_info = pfm_gen_powerpc_get_event_info, .get_event_attr_info = pfm_gen_powerpc_get_event_attr_info, }; pfmlib_pmu_t powerpc_nest_mcs_write_support={ .desc = "POWERPC_NEST_MCS_WR_BW", .name = "powerpc_nest_mcs_write", .pmu = PFM_PMU_POWERPC_NEST_MCS_WRITE_BW, .perf_name = "Nest_MCS_Write_BW", .pme_count = LIBPFM_ARRAY_SIZE(powerpc_nest_write_pe), .type = PFM_PMU_TYPE_UNCORE, .num_cntrs = 4, .num_fixed_cntrs = 0, .max_encoding = 1, .pe = powerpc_nest_write_pe, .pmu_detect = pfm_powerpc_nest_detect, .get_event_encoding[PFM_OS_NONE] = pfm_gen_powerpc_get_encoding, PFMLIB_ENCODE_PERF(pfm_gen_powerpc_get_nest_perf_encoding), PFMLIB_VALID_PERF_PATTRS(pfm_gen_powerpc_perf_validate_pattrs), .get_event_first = pfm_gen_powerpc_get_event_first, .get_event_next = pfm_gen_powerpc_get_event_next, .event_is_valid = pfm_gen_powerpc_event_is_valid, .validate_table = pfm_gen_powerpc_validate_table, .get_event_info = pfm_gen_powerpc_get_event_info, .get_event_attr_info = pfm_gen_powerpc_get_event_attr_info, }; libpfm-4.9.0/lib/pfmlib_intel_bdx_unc_qpi.c0000664000175000017500000000623313223402656020553 0ustar eranianeranian/* * pfmlib_intel_bdx_qpi.c : Intel BroadwellX QPI uncore PMU * * Copyright (c) 2017 Google Inc. All rights reserved * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_intel_x86_priv.h" #include "pfmlib_intel_snbep_unc_priv.h" #include "events/intel_bdx_unc_qpi_events.h" static void display_qpi(void *this, pfmlib_event_desc_t *e, void *val) { const intel_x86_entry_t *pe = this_pe(this); pfm_snbep_unc_reg_t *reg = val; __pfm_vbprintf("[UNC_QPI=0x%"PRIx64" event=0x%x sel_ext=%d umask=0x%x en=%d " "inv=%d edge=%d thres=%d] %s\n", reg->val, reg->qpi.unc_event, reg->qpi.unc_event_ext, reg->qpi.unc_umask, reg->qpi.unc_en, reg->qpi.unc_inv, reg->qpi.unc_edge, reg->qpi.unc_thres, pe[e->event].name); } #define DEFINE_QPI_BOX(n) \ pfmlib_pmu_t intel_bdx_unc_qpi##n##_support = {\ .desc = "Intel BroadwellX QPI"#n" uncore",\ .name = "bdx_unc_qpi"#n,\ .perf_name = "uncore_qpi_"#n,\ .pmu = PFM_PMU_INTEL_BDX_UNC_QPI##n,\ .pme_count = LIBPFM_ARRAY_SIZE(intel_bdx_unc_q_pe),\ .type = PFM_PMU_TYPE_UNCORE,\ .num_cntrs = 4,\ .num_fixed_cntrs = 0,\ .max_encoding = 3,\ .pe = intel_bdx_unc_q_pe,\ .atdesc = snbep_unc_mods,\ .flags = PFMLIB_PMU_FL_RAW_UMASK,\ .pmu_detect = pfm_intel_bdx_unc_detect,\ .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding,\ PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding),\ PFMLIB_OS_DETECT(pfm_intel_x86_perf_detect), \ .get_event_first = pfm_intel_x86_get_event_first,\ .get_event_next = pfm_intel_x86_get_event_next,\ .event_is_valid = pfm_intel_x86_event_is_valid,\ .validate_table = pfm_intel_x86_validate_table,\ .get_event_info = pfm_intel_x86_get_event_info,\ .get_event_attr_info = pfm_intel_x86_get_event_attr_info,\ PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs),\ .get_event_nattrs = pfm_intel_x86_get_event_nattrs,\ .display_reg = display_qpi,\ } DEFINE_QPI_BOX(0); DEFINE_QPI_BOX(1); DEFINE_QPI_BOX(2); libpfm-4.9.0/lib/pfmlib_intel_bdx_unc_ubo.c0000664000175000017500000000600013223402656020537 0ustar eranianeranian/* * pfmlib_intel_bdx_unc_ubo.c : Intel BroadwellX U-Box uncore PMU * * Copyright (c) 2017 Google Inc. All rights reserved * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_intel_x86_priv.h" #include "pfmlib_intel_snbep_unc_priv.h" #include "events/intel_bdx_unc_ubo_events.h" static void display_ubo(void *this, pfmlib_event_desc_t *e, void *val) { const intel_x86_entry_t *pe = this_pe(this); pfm_snbep_unc_reg_t *reg = val; __pfm_vbprintf("[UNC_UBO=0x%"PRIx64" event=0x%x umask=0x%x en=%d " "inv=%d edge=%d thres=%d] %s\n", reg->val, reg->com.unc_event, reg->com.unc_umask, reg->com.unc_en, reg->com.unc_inv, reg->com.unc_edge, reg->com.unc_thres, pe[e->event].name); } pfmlib_pmu_t intel_bdx_unc_ubo_support = { .desc = "Intel BroadwellX U-Box uncore", .name = "bdx_unc_ubo", .perf_name = "uncore_ubox", .pmu = PFM_PMU_INTEL_BDX_UNC_UBOX, .pme_count = LIBPFM_ARRAY_SIZE(intel_bdx_unc_u_pe), .type = PFM_PMU_TYPE_UNCORE, .num_cntrs = 2, .num_fixed_cntrs = 1, .max_encoding = 1, .pe = intel_bdx_unc_u_pe, .atdesc = snbep_unc_mods, .flags = PFMLIB_PMU_FL_RAW_UMASK, .pmu_detect = pfm_intel_bdx_unc_detect, .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding, PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding), PFMLIB_OS_DETECT(pfm_intel_x86_perf_detect), .get_event_first = pfm_intel_x86_get_event_first, .get_event_next = pfm_intel_x86_get_event_next, .event_is_valid = pfm_intel_x86_event_is_valid, .validate_table = pfm_intel_x86_validate_table, .get_event_info = pfm_intel_x86_get_event_info, .get_event_attr_info = pfm_intel_x86_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs), .get_event_nattrs = pfm_intel_x86_get_event_nattrs, .display_reg = display_ubo, }; libpfm-4.9.0/lib/Makefile0000664000175000017500000002550713223402656015035 0ustar eranianeranian# # Copyright (c) 2002-2006 Hewlett-Packard Development Company, L.P. # Contributed by Stephane Eranian # # Permission is hereby granted, free of charge, to any person obtaining a copy # of this software and associated documentation files (the "Software"), to deal # in the Software without restriction, including without limitation the rights # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies # of the Software, and to permit persons to whom the Software is furnished to do so, # subject to the following conditions: # # The above copyright notice and this permission notice shall be included in all # copies or substantial portions of the Software. # # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, # INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A # PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT # HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF # CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE # OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # TOPDIR := $(shell if [ "$$PWD" != "" ]; then echo $$PWD; else pwd; fi)/.. include $(TOPDIR)/config.mk include $(TOPDIR)/rules.mk # # Common files # SRCS=pfmlib_common.c ifeq ($(SYS),Linux) SRCS += pfmlib_perf_event_pmu.c pfmlib_perf_event.c pfmlib_perf_event_raw.c endif CFLAGS+=-D_REENTRANT -I. -fvisibility=hidden # # list all library support modules # ifeq ($(CONFIG_PFMLIB_ARCH_IA64),y) INCARCH = $(INC_IA64) #SRCS += pfmlib_gen_ia64.c pfmlib_itanium.c pfmlib_itanium2.c pfmlib_montecito.c CFLAGS += -DCONFIG_PFMLIB_ARCH_IA64 endif ifeq ($(CONFIG_PFMLIB_ARCH_X86),y) ifeq ($(SYS),Linux) SRCS += pfmlib_intel_x86_perf_event.c pfmlib_amd64_perf_event.c \ pfmlib_intel_netburst_perf_event.c \ pfmlib_intel_snbep_unc_perf_event.c endif INCARCH = $(INC_X86) SRCS += pfmlib_amd64.c pfmlib_intel_core.c pfmlib_intel_x86.c \ pfmlib_intel_x86_arch.c pfmlib_intel_atom.c \ pfmlib_intel_nhm_unc.c pfmlib_intel_nhm.c \ pfmlib_intel_wsm.c \ pfmlib_intel_snb.c pfmlib_intel_snb_unc.c \ pfmlib_intel_ivb.c pfmlib_intel_ivb_unc.c \ pfmlib_intel_hsw.c \ pfmlib_intel_bdw.c \ pfmlib_intel_skl.c \ pfmlib_intel_rapl.c \ pfmlib_intel_snbep_unc.c \ pfmlib_intel_snbep_unc_cbo.c \ pfmlib_intel_snbep_unc_ha.c \ pfmlib_intel_snbep_unc_imc.c \ pfmlib_intel_snbep_unc_pcu.c \ pfmlib_intel_snbep_unc_qpi.c \ pfmlib_intel_snbep_unc_ubo.c \ pfmlib_intel_snbep_unc_r2pcie.c \ pfmlib_intel_snbep_unc_r3qpi.c \ pfmlib_intel_ivbep_unc_cbo.c \ pfmlib_intel_ivbep_unc_ha.c \ pfmlib_intel_ivbep_unc_imc.c \ pfmlib_intel_ivbep_unc_pcu.c \ pfmlib_intel_ivbep_unc_qpi.c \ pfmlib_intel_ivbep_unc_ubo.c \ pfmlib_intel_ivbep_unc_r2pcie.c \ pfmlib_intel_ivbep_unc_r3qpi.c \ pfmlib_intel_ivbep_unc_irp.c \ pfmlib_intel_hswep_unc_cbo.c \ pfmlib_intel_hswep_unc_ha.c \ pfmlib_intel_hswep_unc_imc.c \ pfmlib_intel_hswep_unc_pcu.c \ pfmlib_intel_hswep_unc_qpi.c \ pfmlib_intel_hswep_unc_ubo.c \ pfmlib_intel_hswep_unc_r2pcie.c \ pfmlib_intel_hswep_unc_r3qpi.c \ pfmlib_intel_hswep_unc_irp.c \ pfmlib_intel_hswep_unc_sbo.c \ pfmlib_intel_bdx_unc_cbo.c \ pfmlib_intel_bdx_unc_ubo.c \ pfmlib_intel_bdx_unc_sbo.c \ pfmlib_intel_bdx_unc_ha.c \ pfmlib_intel_bdx_unc_imc.c \ pfmlib_intel_bdx_unc_irp.c \ pfmlib_intel_bdx_unc_pcu.c \ pfmlib_intel_bdx_unc_qpi.c \ pfmlib_intel_bdx_unc_r2pcie.c \ pfmlib_intel_bdx_unc_r3qpi.c \ pfmlib_intel_knc.c \ pfmlib_intel_slm.c \ pfmlib_intel_knl.c \ pfmlib_intel_knl_unc_imc.c \ pfmlib_intel_knl_unc_edc.c \ pfmlib_intel_knl_unc_cha.c \ pfmlib_intel_knl_unc_m2pcie.c \ pfmlib_intel_glm.c \ pfmlib_intel_netburst.c \ pfmlib_amd64_k7.c pfmlib_amd64_k8.c pfmlib_amd64_fam10h.c \ pfmlib_amd64_fam11h.c pfmlib_amd64_fam12h.c \ pfmlib_amd64_fam14h.c pfmlib_amd64_fam15h.c \ pfmlib_amd64_fam17h.c pfmlib_amd64_fam16h.c CFLAGS += -DCONFIG_PFMLIB_ARCH_X86 ifeq ($(CONFIG_PFMLIB_ARCH_I386),y) SRCS += pfmlib_intel_coreduo.c pfmlib_intel_p6.c CFLAGS += -DCONFIG_PFMLIB_ARCH_I386 endif ifeq ($(CONFIG_PFMLIB_ARCH_X86_64),y) CFLAGS += -DCONFIG_PFMLIB_ARCH_X86_64 endif endif ifeq ($(CONFIG_PFMLIB_ARCH_POWERPC),y) ifeq ($(SYS),Linux) SRCS += pfmlib_powerpc_perf_event.c endif INCARCH = $(INC_POWERPC) SRCS += pfmlib_powerpc.c pfmlib_power4.c pfmlib_ppc970.c pfmlib_power5.c pfmlib_power6.c pfmlib_power7.c pfmlib_torrent.c pfmlib_power8.c pfmlib_power9.c pfmlib_powerpc_nest.c CFLAGS += -DCONFIG_PFMLIB_ARCH_POWERPC endif ifeq ($(CONFIG_PFMLIB_ARCH_S390X),y) ifeq ($(SYS),Linux) SRCS += pfmlib_s390x_perf_event.c endif INCARCH = $(INC_S390X) SRCS += pfmlib_s390x_cpumf.c CFLAGS += -DCONFIG_PFMLIB_ARCH_S390X endif ifeq ($(CONFIG_PFMLIB_ARCH_SPARC),y) ifeq ($(SYS),Linux) SRCS += pfmlib_sparc_perf_event.c endif INCARCH = $(INC_SPARC) SRCS += pfmlib_sparc.c pfmlib_sparc_ultra12.c pfmlib_sparc_ultra3.c pfmlib_sparc_ultra4.c pfmlib_sparc_niagara.c CFLAGS += -DCONFIG_PFMLIB_ARCH_SPARC endif ifeq ($(CONFIG_PFMLIB_ARCH_ARM),y) ifeq ($(SYS),Linux) SRCS += pfmlib_arm_perf_event.c endif INCARCH = $(INC_ARM) SRCS += pfmlib_arm.c pfmlib_arm_armv7_pmuv1.c pfmlib_arm_armv6.c pfmlib_arm_armv8.c CFLAGS += -DCONFIG_PFMLIB_ARCH_ARM endif ifeq ($(CONFIG_PFMLIB_ARCH_ARM64),y) ifeq ($(SYS),Linux) SRCS += pfmlib_arm_perf_event.c endif INCARCH = $(INC_ARM64) SRCS += pfmlib_arm.c pfmlib_arm_armv8.c CFLAGS += -DCONFIG_PFMLIB_ARCH_ARM64 endif ifeq ($(CONFIG_PFMLIB_ARCH_MIPS),y) ifeq ($(SYS),Linux) SRCS += pfmlib_mips_perf_event.c endif INCARCH = $(INC_MIPS) SRCS += pfmlib_mips.c pfmlib_mips_74k.c CFLAGS += -DCONFIG_PFMLIB_ARCH_MIPS endif ifeq ($(CONFIG_PFMLIB_CELL),y) INCARCH = $(INC_CELL) #SRCS += pfmlib_cell.c CFLAGS += -DCONFIG_PFMLIB_CELL endif ifeq ($(SYS),Linux) SLDFLAGS=$(LDFLAGS) -shared -Wl,-soname -Wl,$(VLIBPFM) SLIBPFM=libpfm.so.$(VERSION).$(REVISION).$(AGE) VLIBPFM=libpfm.so.$(VERSION) SOLIBEXT=so endif CFLAGS+=-I. ALIBPFM=libpfm.a TARGETS=$(ALIBPFM) ifeq ($(CONFIG_PFMLIB_SHARED),y) TARGETS += $(SLIBPFM) endif OBJS=$(SRCS:.c=.o) SOBJS=$(OBJS:.o=.lo) INC_COMMON= $(PFMINCDIR)/perfmon/pfmlib.h pfmlib_priv.h ifeq ($(SYS),Linux) INC_COMMON += $(PFMINCDIR)/perfmon/perf_event.h events/perf_events.h endif INC_IA64=pfmlib_ia64_priv.h \ events/itanium_events.h \ events/itanium2_events.h \ events/montecito_events.h INC_X86= pfmlib_intel_x86_priv.h \ pfmlib_amd64_priv.h \ events/amd64_events_k7.h \ events/amd64_events_k8.h \ events/amd64_events_fam10h.h \ events/amd64_events_fam11h.h \ events/amd64_events_fam12h.h \ events/amd64_events_fam14h.h \ events/amd64_events_fam15h.h \ events/amd64_events_fam17h.h \ events/amd64_events_fam16h.h \ events/intel_p6_events.h \ events/intel_netburst_events.h \ events//intel_x86_arch_events.h \ events/intel_coreduo_events.h \ events/intel_core_events.h \ events/intel_atom_events.h \ events/intel_nhm_events.h \ events/intel_nhm_unc_events.h \ events/intel_wsm_events.h \ events/intel_wsm_unc_events.h \ events/intel_snb_events.h \ events/intel_snb_unc_events.h \ events/intel_ivb_events.h \ events/intel_hsw_events.h \ events/intel_bdw_events.h \ events/intel_skl_events.h \ events/intel_glm_events.h \ pfmlib_intel_snbep_unc_priv.h \ events/intel_snbep_unc_cbo_events.h \ events/intel_snbep_unc_ha_events.h \ events/intel_snbep_unc_imc_events.h \ events/intel_snbep_unc_pcu_events.h \ events/intel_snbep_unc_qpi_events.h \ events/intel_snbep_unc_ubo_events.h \ events/intel_snbep_unc_r2pcie_events.h \ events/intel_snbep_unc_r3qpi_events.h \ events/intel_knc_events.h \ events/intel_knl_events.h \ events/intel_ivbep_unc_cbo_events.h \ events/intel_ivbep_unc_ha_events.h \ events/intel_ivbep_unc_imc_events.h \ events/intel_ivbep_unc_pcu_events.h \ events/intel_ivbep_unc_qpi_events.h \ events/intel_ivbep_unc_ubo_events.h \ events/intel_ivbep_unc_r2pcie_events.h \ events/intel_ivbep_unc_r3qpi_events.h \ events/intel_ivbep_unc_irp_events.h \ events/intel_hswep_unc_cbo_events.h \ events/intel_hswep_unc_sbo_events.h \ events/intel_hswep_unc_ha_events.h \ events/intel_hswep_unc_imc_events.h \ events/intel_hswep_unc_pcu_events.h \ events/intel_hswep_unc_qpi_events.h \ events/intel_hswep_unc_ubo_events.h \ events/intel_hswep_unc_r2pcie_events.h \ events/intel_hswep_unc_r3qpi_events.h \ events/intel_hswep_unc_irp_events.h \ events/intel_bdx_unc_cbo_events.h \ events/intel_bdx_unc_ubo_events.h \ events/intel_bdx_unc_sbo_events.h \ events/intel_bdx_unc_ha_events.h \ events/intel_bdx_unc_imc_events.h \ events/intel_bdx_unc_irp_events.h \ events/intel_bdx_unc_pcu_events.h \ events/intel_bdx_unc_qpi_events.h \ events/intel_bdx_unc_r2pcie_events.h \ events/intel_bdx_unc_r3qpi_events.h \ events/intel_knl_unc_imc_events.h \ events/intel_knl_unc_edc_events.h \ events/intel_knl_unc_cha_events.h \ events/intel_knl_unc_m2pcie_events.h \ events/intel_slm_events.h INC_MIPS=events/mips_74k_events.h events/mips_74k_events.h INC_POWERPC=events/ppc970_events.h \ events/ppc970mp_events.h \ events/power4_events.h \ events/power5_events.h \ events/power5+_events.h \ events/power6_events.h \ events/power7_events.h \ events/power8_events.h \ events/power9_events.h \ events/torrent_events.h \ events/powerpc_nest_events.h INC_S390X=pfmlib_s390x_priv.h \ events/s390x_cpumf_events.h INC_SPARC=events/sparc_ultra12_events.h \ events/sparc_ultra3_events.h \ events/sparc_ultra3plus_events.h \ events/sparc_ultra3i_events.h \ events/sparc_ultra4plus_events.h \ events/sparc_niagara1_events.h \ events/sparc_niagara2_events.h INC_CELL=events/cell_events.h INC_ARM=events/arm_cortex_a8_events.h \ events/arm_cortex_a9_events.h \ events/arm_arm_xgene_events.h INC_ARM=pfmlib_arm_priv.h \ events/arm_cortex_a7_events.h \ events/arm_cortex_a8_events.h \ events/arm_cortex_a9_events.h \ events/arm_cortex_a15_events.h \ events/arm_cortex_a57_events.h \ events/arm_cortex_a53_events.h INC_ARM64=events/arm_cortex_a57_events.h \ events/arm_cortex_a53_events.h INCDEP=$(INC_COMMON) $(INCARCH) all: $(TARGETS) $(OBJS) $(SOBJS): $(TOPDIR)/config.mk $(TOPDIR)/rules.mk Makefile $(INCDEP) libpfm.a: $(OBJS) $(RM) $@ $(AR) cq $@ $(OBJS) $(SLIBPFM): $(SOBJS) $(CC) $(CFLAGS) $(SLDFLAGS) -o $@ $(SOBJS) $(LN) $@ $(VLIBPFM) $(LN) $@ libpfm.$(SOLIBEXT) clean: $(RM) -f *.o *.lo *.a *.so* *~ *.$(SOLIBEXT) distclean: clean depend: $(MKDEP) $(CFLAGS) $(SRCS) install: $(TARGETS) install: @echo building: $(TARGETS) -mkdir -p $(DESTDIR)$(LIBDIR) $(INSTALL) -m 644 $(ALIBPFM) $(DESTDIR)$(LIBDIR) ifeq ($(CONFIG_PFMLIB_SHARED),y) $(INSTALL) $(SLIBPFM) $(DESTDIR)$(LIBDIR) cd $(DESTDIR)$(LIBDIR); $(LN) $(SLIBPFM) $(VLIBPFM) cd $(DESTDIR)$(LIBDIR); $(LN) $(SLIBPFM) libpfm.$(SOLIBEXT) -$(LDCONFIG) endif tags: $(CTAGS) -o $(TOPDIR)/tags --tag-relative=yes $(SRCS) $(INCDEP) libpfm-4.9.0/lib/pfmlib_torrent.c0000664000175000017500000001545613223402656016571 0ustar eranianeranian/* * pfmlib_torrent.c : IBM Torrent support * * Copyright (C) IBM Corporation, 2010. All rights reserved. * Contributed by Corey Ashford (cjashfor@us.ibm.com) * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include "pfmlib_priv.h" #include "pfmlib_power_priv.h" #include "events/torrent_events.h" const pfmlib_attr_desc_t torrent_modifiers[] = { PFM_ATTR_I("type", "Counter type: 0 = 2x64-bit counters w/32-bit prescale, 1 = 4x32-bit counters w/16-bit prescale, 2 = 2x32-bit counters w/no prescale, 3 = 4x16-bit counters w/no prescale"), PFM_ATTR_I("sel", "Sample period / Cmd Increment select: 0 = 256 cycles/ +16, 1 = 512 cycles / +8, 2 = 1024 cycles / +4, 3 = 2048 cycles / +2"), PFM_ATTR_I("lo_cmp", "Low threshold compare: 0..31"), PFM_ATTR_I("hi_cmp", "High threshold compare: 0..31"), PFM_ATTR_NULL }; static inline int pfm_torrent_attr2mod(void *this, int pidx, int attr_idx) { const pme_torrent_entry_t *pe = this_pe(this); size_t x; int n; n = attr_idx; pfmlib_for_each_bit(x, pe[pidx].pme_modmsk) { if (n == 0) break; n--; } return x; } /** * torrent_pmu_detect * * Determine if this machine has a Torrent chip * **/ static int pfm_torrent_detect(void* this) { struct dirent *de; DIR *dir; int ret = PFM_ERR_NOTSUPP; /* If /proc/device-tree/hfi-iohub@ exists, * this machine has an accessible Torrent chip */ dir = opendir("/proc/device-tree"); if (!dir) return PFM_ERR_NOTSUPP; while ((de = readdir(dir)) != NULL) { if (!strncmp(de->d_name, "hfi-iohub@", 10)) { ret = PFM_SUCCESS; break; } } closedir(dir); return ret; } static int pfm_torrent_get_event_info(void *this, int pidx, pfm_event_info_t *info) { pfmlib_pmu_t *pmu = this; const pme_torrent_entry_t *pe = this_pe(this); info->name = pe[pidx].pme_name; info->desc = pe[pidx].pme_desc ? pe[pidx].pme_desc : ""; info->code = pe[pidx].pme_code; info->equiv = NULL; info->idx = pidx; /* private index */ info->pmu = pmu->pmu; info->dtype = PFM_DTYPE_UINT64; info->is_precise = 0; /* unit masks + modifiers */ info->nattrs = pfmlib_popcnt((unsigned long)pe[pidx].pme_modmsk); return PFM_SUCCESS; } static int pfm_torrent_get_event_attr_info(void *this, int idx, int attr_idx, pfmlib_event_attr_info_t *info) { int m; m = pfm_torrent_attr2mod(this, idx, attr_idx); info->name = modx(torrent_modifiers, m, name); info->desc = modx(torrent_modifiers, m, desc); info->code = m; info->type = modx(torrent_modifiers, m, type); info->equiv = NULL; info->is_dfl = 0; info->is_precise = 0; info->idx = m; info->dfl_val64 = 0; info->ctrl = PFM_ATTR_CTRL_PMU; return PFM_SUCCESS; } static int pfm_torrent_validate_table(void *this, FILE *fp) { pfmlib_pmu_t *pmu = this; const pme_torrent_entry_t *pe = this_pe(this); int i, ret = PFM_ERR_INVAL; for (i = 0; i < pmu->pme_count; i++) { if (!pe[i].pme_name) { fprintf(fp, "pmu: %s event%d: :: no name\n", pmu->name, i); goto error; } if (pe[i].pme_code == 0) { fprintf(fp, "pmu: %s event%d: %s :: event code is 0\n", pmu->name, i, pe[i].pme_name); goto error; } } ret = PFM_SUCCESS; error: return ret; } static int pfm_torrent_get_encoding(void *this, pfmlib_event_desc_t *e) { const pme_torrent_entry_t *pe = this_pe(this); uint32_t torrent_pmu; int i, mod; e->fstr[0] = '\0'; /* initialize the fully-qualified event string */ e->count = 1; e->codes[0] = (uint64_t)pe[e->event].pme_code; for (i = 0; i < e->nattrs; i++) { mod = pfm_torrent_attr2mod(this, e->event, e->attrs[i].id); torrent_pmu = pe[e->event].pme_code & (TORRENT_SPACE | TORRENT_PMU_MASK); switch (torrent_pmu) { case TORRENT_PBUS_MCD: switch (mod) { case TORRENT_ATTR_MCD_TYPE: if (e->attrs[i].ival <= 3) { e->codes[0] |= e->attrs[i].ival << TORRENT_ATTR_MCD_TYPE_SHIFT; } else { DPRINT("value of attribute \'type\' - %" PRIu64 " - is not in the range 0..3.\n", e->attrs[i].ival); return PFM_ERR_ATTR_VAL; } break; default: DPRINT("unknown attribute for TORRENT_POWERBUS_MCD - %d\n", mod); return PFM_ERR_ATTR; } break; case TORRENT_PBUS_UTIL: switch (mod) { case TORRENT_ATTR_UTIL_SEL: if (e->attrs[i].ival <= 3) { e->codes[0] |= e->attrs[i].ival << TORRENT_ATTR_UTIL_SEL_SHIFT; } else { DPRINT("value of attribute \'sel\' - %" PRIu64 " - is not in the range 0..3.\n", e->attrs[i].ival); return PFM_ERR_ATTR_VAL; } break; case TORRENT_ATTR_UTIL_LO_CMP: case TORRENT_ATTR_UTIL_HI_CMP: if (e->attrs[i].ival <= 31) { e->codes[0] |= e->attrs[i].ival << TORRENT_ATTR_UTIL_CMP_SHIFT; } else { if (mod == TORRENT_ATTR_UTIL_LO_CMP) DPRINT("value of attribute \'lo_cmp\' - %" PRIu64 " - is not in the range 0..31.\n", e->attrs[i].ival); else DPRINT("value of attribute \'hi_cmp\' - %" PRIu64 " - is not in the range 0..31.\n", e->attrs[i].ival); return PFM_ERR_ATTR_VAL; } } break; default: DPRINT("attributes are unsupported for this Torrent PMU - code = %" PRIx32 "\n", torrent_pmu); return PFM_ERR_ATTR; } } return PFM_SUCCESS; } pfmlib_pmu_t torrent_support = { .pmu = PFM_PMU_TORRENT, .name = "power_torrent", .desc = "IBM Power Torrent PMU", .pme_count = PME_TORRENT_EVENT_COUNT, .pe = torrent_pe, .max_encoding = 1, .get_event_first = pfm_gen_powerpc_get_event_first, .get_event_next = pfm_gen_powerpc_get_event_next, .event_is_valid = pfm_gen_powerpc_event_is_valid, .pmu_detect = pfm_torrent_detect, .get_event_encoding[PFM_OS_NONE] = pfm_torrent_get_encoding, PFMLIB_ENCODE_PERF(pfm_gen_powerpc_get_perf_encoding), PFMLIB_VALID_PERF_PATTRS(pfm_gen_powerpc_perf_validate_pattrs), .validate_table = pfm_torrent_validate_table, .get_event_info = pfm_torrent_get_event_info, .get_event_attr_info = pfm_torrent_get_event_attr_info, }; libpfm-4.9.0/lib/pfmlib_amd64_priv.h0000664000175000017500000001744513223402656017054 0ustar eranianeranian/* * Copyright (c) 2004-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. */ #ifndef __PFMLIB_AMD64_PRIV_H__ #define __PFMLIB_AMD64_PRIV_H__ #define AMD64_MAX_GRP 4 /* must be < 32 (int) */ typedef struct { const char *uname; /* unit mask name */ const char *udesc; /* event/umask description */ unsigned int ucode; /* unit mask code */ unsigned int uflags; /* unit mask flags */ unsigned int grpid; /* unit mask group id */ } amd64_umask_t; typedef struct { const char *name; /* event name */ const char *desc; /* event description */ const amd64_umask_t *umasks;/* list of umasks */ unsigned int code; /* event code */ unsigned int numasks;/* number of umasks */ unsigned int flags; /* flags */ unsigned int modmsk; /* modifiers bitmask */ unsigned int ngrp; /* number of unit masks groups */ } amd64_entry_t; /* * we keep an internal revision type to avoid * dealing with arbitrarily large pfm_pmu_t * which would not fit into the 8 bits reserved * in amd64_entry_t.flags or amd64_umask_t.flags */ #define AMD64_FAM10H AMD64_FAM10H_REV_B typedef enum { AMD64_CPU_UN = 0, AMD64_K7, AMD64_K8_REV_B, AMD64_K8_REV_C, AMD64_K8_REV_D, AMD64_K8_REV_E, AMD64_K8_REV_F, AMD64_K8_REV_G, AMD64_FAM10H_REV_B, AMD64_FAM10H_REV_C, AMD64_FAM10H_REV_D, AMD64_FAM14H_REV_B, } amd64_rev_t; typedef struct { pfm_pmu_t revision; int family; /* 0 means nothing detected yet */ int model; int stepping; } pfm_amd64_config_t; extern pfm_amd64_config_t pfm_amd64_cfg; /* * flags values (bottom 8 bits only) * bits 00-07: flags * bits 08-15: from revision * bits 16-23: till revision */ #define AMD64_FROM_REV(rev) ((rev)<<8) #define AMD64_TILL_REV(rev) ((rev)<<16) #define AMD64_NOT_SUPP 0x1ff00 #define AMD64_FL_NCOMBO 0x01 /* unit mask can be combined */ #define AMD64_FL_IBSFE 0x02 /* IBS fetch */ #define AMD64_FL_IBSOP 0x04 /* IBS op */ #define AMD64_FL_DFL 0x08 /* unit mask is default choice */ #define AMD64_FL_OMIT 0x10 /* umask can be omitted */ #define AMD64_FL_TILL_K8_REV_C AMD64_TILL_REV(AMD64_K8_REV_C) #define AMD64_FL_K8_REV_D AMD64_FROM_REV(AMD64_K8_REV_D) #define AMD64_FL_K8_REV_E AMD64_FROM_REV(AMD64_K8_REV_E) #define AMD64_FL_TILL_K8_REV_E AMD64_TILL_REV(AMD64_K8_REV_E) #define AMD64_FL_K8_REV_F AMD64_FROM_REV(AMD64_K8_REV_F) #define AMD64_FL_TILL_FAM10H_REV_B AMD64_TILL_REV(AMD64_FAM10H_REV_B) #define AMD64_FL_FAM10H_REV_C AMD64_FROM_REV(AMD64_FAM10H_REV_C) #define AMD64_FL_TILL_FAM10H_REV_C AMD64_TILL_REV(AMD64_FAM10H_REV_C) #define AMD64_FL_FAM10H_REV_D AMD64_FROM_REV(AMD64_FAM10H_REV_D) #define AMD64_ATTR_K 0 #define AMD64_ATTR_U 1 #define AMD64_ATTR_E 2 #define AMD64_ATTR_I 3 #define AMD64_ATTR_C 4 #define AMD64_ATTR_H 5 #define AMD64_ATTR_G 6 #define _AMD64_ATTR_U (1 << AMD64_ATTR_U) #define _AMD64_ATTR_K (1 << AMD64_ATTR_K) #define _AMD64_ATTR_I (1 << AMD64_ATTR_I) #define _AMD64_ATTR_E (1 << AMD64_ATTR_E) #define _AMD64_ATTR_C (1 << AMD64_ATTR_C) #define _AMD64_ATTR_H (1 << AMD64_ATTR_H) #define _AMD64_ATTR_G (1 << AMD64_ATTR_G) #define AMD64_BASIC_ATTRS \ (_AMD64_ATTR_I|_AMD64_ATTR_E|_AMD64_ATTR_C|_AMD64_ATTR_U|_AMD64_ATTR_K) #define AMD64_K8_ATTRS (AMD64_BASIC_ATTRS) #define AMD64_FAM10H_ATTRS (AMD64_BASIC_ATTRS|_AMD64_ATTR_H|_AMD64_ATTR_G) #define AMD64_FAM12H_ATTRS AMD64_FAM10H_ATTRS #define AMD64_FAM14H_ATTRS AMD64_FAM10H_ATTRS #define AMD64_FAM15H_ATTRS AMD64_FAM10H_ATTRS #define AMD64_FAM17H_ATTRS AMD64_FAM10H_ATTRS #define AMD64_FAM10H_PLM (PFM_PLM0|PFM_PLM3|PFM_PLMH) #define AMD64_K7_PLM (PFM_PLM0|PFM_PLM3) /* * AMD64 MSR definitions */ typedef union { uint64_t val; /* complete register value */ struct { uint64_t sel_event_mask:8; /* event mask */ uint64_t sel_unit_mask:8; /* unit mask */ uint64_t sel_usr:1; /* user level */ uint64_t sel_os:1; /* system level */ uint64_t sel_edge:1; /* edge detec */ uint64_t sel_pc:1; /* pin control */ uint64_t sel_int:1; /* enable APIC intr */ uint64_t sel_res1:1; /* reserved */ uint64_t sel_en:1; /* enable */ uint64_t sel_inv:1; /* invert counter mask */ uint64_t sel_cnt_mask:8; /* counter mask */ uint64_t sel_event_mask2:4; /* 10h only: event mask [11:8] */ uint64_t sel_res2:4; /* reserved */ uint64_t sel_guest:1; /* 10h only: guest only counter */ uint64_t sel_host:1; /* 10h only: host only counter */ uint64_t sel_res3:22; /* reserved */ } perfsel; struct { uint64_t maxcnt:16; uint64_t cnt:16; uint64_t lat:16; uint64_t en:1; uint64_t val:1; uint64_t comp:1; uint64_t icmiss:1; uint64_t phyaddrvalid:1; uint64_t l1tlbpgsz:2; uint64_t l1tlbmiss:1; uint64_t l2tlbmiss:1; uint64_t randen:1; uint64_t reserved:6; } ibsfetch; struct { uint64_t maxcnt:16; uint64_t reserved1:1; uint64_t en:1; uint64_t val:1; uint64_t reserved2:45; } ibsop; } pfm_amd64_reg_t; /* MSR 0xc001000-0xc001003 */ /* let's define some handy shortcuts! */ #define sel_event_mask perfsel.sel_event_mask #define sel_unit_mask perfsel.sel_unit_mask #define sel_usr perfsel.sel_usr #define sel_os perfsel.sel_os #define sel_edge perfsel.sel_edge #define sel_pc perfsel.sel_pc #define sel_int perfsel.sel_int #define sel_en perfsel.sel_en #define sel_inv perfsel.sel_inv #define sel_cnt_mask perfsel.sel_cnt_mask #define sel_event_mask2 perfsel.sel_event_mask2 #define sel_guest perfsel.sel_guest #define sel_host perfsel.sel_host #define IS_FAMILY_10H(p) (((pfmlib_pmu_t *)(p))->pmu_rev >= AMD64_FAM10H) #define IS_FAMILY_15H(p) (((pfmlib_pmu_t *)(p))->pmu == PFM_PMU_AMD64_FAM15H_INTERLAGOS) extern int pfm_amd64_get_encoding(void *this, pfmlib_event_desc_t *e); extern int pfm_amd64_get_event_first(void *this); extern int pfm_amd64_get_event_next(void *this, int idx); extern int pfm_amd64_event_is_valid(void *this, int idx); extern int pfm_amd64_get_event_attr_info(void *this, int idx, int attr_idx, pfmlib_event_attr_info_t *info); extern int pfm_amd64_get_event_info(void *this, int idx, pfm_event_info_t *info); extern int pfm_amd64_validate_table(void *this, FILE *fp); extern int pfm_amd64_detect(void *this); extern const pfmlib_attr_desc_t amd64_mods[]; extern unsigned int pfm_amd64_get_event_nattrs(void *this, int pidx); extern int pfm_amd64_get_num_events(void *this); extern int pfm_amd64_get_perf_encoding(void *this, pfmlib_event_desc_t *e); extern void pfm_amd64_perf_validate_pattrs(void *this, pfmlib_event_desc_t *e); extern void pfm_amd64_nb_perf_validate_pattrs(void *this, pfmlib_event_desc_t *e); extern int pfm_amd64_family_detect(void *this); #endif /* __PFMLIB_AMD64_PRIV_H__ */ libpfm-4.9.0/lib/pfmlib_intel_hswep_unc_sbo.c0000664000175000017500000000622613223402656021120 0ustar eranianeranian/* * pfmlib_intel_hswep_unc_sbo.c : Intel Haswell-EP S-Box uncore PMU * * Copyright (c) 2014 Google Inc. All rights reserved * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_intel_x86_priv.h" #include "pfmlib_intel_snbep_unc_priv.h" #include "events/intel_hswep_unc_sbo_events.h" static void display_sbo(void *this, pfmlib_event_desc_t *e, void *val) { const intel_x86_entry_t *pe = this_pe(this); pfm_snbep_unc_reg_t *reg = val; __pfm_vbprintf("[UNC_SBO=0x%"PRIx64" event=0x%x umask=0x%x en=%d " "inv=%d edge=%d thres=%d] %s\n", reg->val, reg->com.unc_event, reg->com.unc_umask, reg->com.unc_en, reg->com.unc_inv, reg->com.unc_edge, reg->com.unc_thres, pe[e->event].name); } #define DEFINE_S_BOX(n) \ pfmlib_pmu_t intel_hswep_unc_sb##n##_support = {\ .desc = "Intel Haswell-EP S-BOX"#n" uncore",\ .name = "hswep_unc_sbo"#n,\ .perf_name = "uncore_sbox_"#n,\ .pmu = PFM_PMU_INTEL_HSWEP_UNC_SB##n,\ .pme_count = LIBPFM_ARRAY_SIZE(intel_hswep_unc_s_pe),\ .type = PFM_PMU_TYPE_UNCORE,\ .num_cntrs = 4,\ .num_fixed_cntrs = 0,\ .max_encoding = 3,\ .pe = intel_hswep_unc_s_pe,\ .atdesc = snbep_unc_mods,\ .flags = PFMLIB_PMU_FL_RAW_UMASK,\ .pmu_detect = pfm_intel_hswep_unc_detect,\ .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding,\ PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding),\ PFMLIB_OS_DETECT(pfm_intel_x86_perf_detect), \ .get_event_first = pfm_intel_x86_get_event_first,\ .get_event_next = pfm_intel_x86_get_event_next,\ .event_is_valid = pfm_intel_x86_event_is_valid,\ .validate_table = pfm_intel_x86_validate_table,\ .get_event_info = pfm_intel_x86_get_event_info,\ .get_event_attr_info = pfm_intel_x86_get_event_attr_info,\ PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs),\ .get_event_nattrs = pfm_intel_x86_get_event_nattrs,\ .display_reg = display_sbo,\ } DEFINE_S_BOX(0); DEFINE_S_BOX(1); DEFINE_S_BOX(2); DEFINE_S_BOX(3); libpfm-4.9.0/lib/pfmlib_intel_rapl.c0000664000175000017500000001413013223402656017211 0ustar eranianeranian/* * pfmlib_intel_rapl.c : Intel RAPL PMU * * Copyright (c) 2013 Google, Inc * Contributed by Stephane Eranian * * Based on: * Copyright (c) 2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * RAPL PMU (SNB, IVB, HSW) */ /* private headers */ #include "pfmlib_priv.h" /* * for now, we reuse the x86 table entry format and callback to avoid duplicating * code. We may revisit this later on */ #include "pfmlib_intel_x86_priv.h" extern pfmlib_pmu_t intel_rapl_support; #define RAPL_COMMON_EVENTS \ { .name = "RAPL_ENERGY_CORES",\ .desc = "Number of Joules consumed by all cores on the package. Unit is 2^-32 Joules",\ .cntmsk = 0x1,\ .code = 0x1,\ },\ { .name = "RAPL_ENERGY_PKG",\ .desc = "Number of Joules consumed by all cores and Last level cache on the package. Unit is 2^-32 Joules",\ .cntmsk = 0x2,\ .code = 0x2,\ } static const intel_x86_entry_t intel_rapl_cln_pe[]={ RAPL_COMMON_EVENTS, { .name = "RAPL_ENERGY_GPU", .desc = "Number of Joules consumed by the builtin GPU. Unit is 2^-32 Joules", .cntmsk = 0x8, .code = 0x4, } }; static const intel_x86_entry_t intel_rapl_skl_cln_pe[]={ RAPL_COMMON_EVENTS, { .name = "RAPL_ENERGY_GPU", .desc = "Number of Joules consumed by the builtin GPU. Unit is 2^-32 Joules", .cntmsk = 0x8, .code = 0x4, }, { .name = "RAPL_ENERGY_PSYS", .desc = "Number of Joules consumed by the builtin PSYS. Unit is 2^-32 Joules", .cntmsk = 0x8, .code = 0x5, } }; static const intel_x86_entry_t intel_rapl_srv_pe[]={ RAPL_COMMON_EVENTS, { .name = "RAPL_ENERGY_DRAM", .desc = "Number of Joules consumed by the DRAM. Unit is 2^-32 Joules", .cntmsk = 0x4, .code = 0x3, }, }; static const intel_x86_entry_t intel_rapl_hswep_pe[]={ /* * RAPL_ENERGY_CORES not supported in HSW-EP */ { .name = "RAPL_ENERGY_PKG", .desc = "Number of Joules consumed by all cores and Last level cache on the package. Unit is 2^-32 Joules", .cntmsk = 0x2, .code = 0x2, }, { .name = "RAPL_ENERGY_DRAM", .desc = "Number of Joules consumed by the DRAM. Unit is 2^-32 Joules", .cntmsk = 0x4, .code = 0x3, }, }; static int pfm_rapl_detect(void *this) { int ret; ret = pfm_intel_x86_detect(); if (ret != PFM_SUCCESS) return ret; if (pfm_intel_x86_cfg.family != 6) return PFM_ERR_NOTSUPP; switch(pfm_intel_x86_cfg.model) { case 42: /* Sandy Bridge */ case 58: /* Ivy Bridge */ case 60: /* Haswell */ case 69: /* Haswell */ case 70: /* Haswell */ case 61: /* Broadwell */ case 71: /* Broadwell GT3E */ case 92: /* Goldmont */ /* already setup by default */ break; case 45: /* Sandy Bridg-EP */ case 62: /* Ivy Bridge-EP */ intel_rapl_support.pe = intel_rapl_srv_pe; intel_rapl_support.pme_count = LIBPFM_ARRAY_SIZE(intel_rapl_srv_pe); break; case 78: /* Skylake */ case 94: /* Skylake H/S */ case 142: /* Kabylake */ case 158: /* Kabylake */ intel_rapl_support.pe = intel_rapl_skl_cln_pe; intel_rapl_support.pme_count = LIBPFM_ARRAY_SIZE(intel_rapl_skl_cln_pe); break; case 63: /* Haswell-EP */ case 79: /* Broadwell-EP */ case 86: /* Broadwell D */ case 85: /* Skylake X */ intel_rapl_support.pe = intel_rapl_hswep_pe; intel_rapl_support.pme_count = LIBPFM_ARRAY_SIZE(intel_rapl_hswep_pe); break; default : return PFM_ERR_NOTSUPP; } return PFM_SUCCESS; } static int pfm_intel_rapl_get_encoding(void *this, pfmlib_event_desc_t *e) { const intel_x86_entry_t *pe; pe = this_pe(this); e->fstr[0] = '\0'; e->codes[0] = pe[e->event].code; e->count = 1; evt_strcat(e->fstr, "%s", pe[e->event].name); __pfm_vbprintf("[0x%"PRIx64" event=0x%x] %s\n", e->codes[0], e->codes[0], e->fstr); return PFM_SUCCESS; } /* * number modifiers for RAPL * define an empty modifier to avoid firing the * sanity pfm_intel_x86_validate_table(). We are * using this function to avoid duplicating code. */ static const pfmlib_attr_desc_t rapl_mods[]= {}; pfmlib_pmu_t intel_rapl_support={ .desc = "Intel RAPL", .name = "rapl", .perf_name = "power", .pmu = PFM_PMU_INTEL_RAPL, .pme_count = LIBPFM_ARRAY_SIZE(intel_rapl_cln_pe), .type = PFM_PMU_TYPE_UNCORE, .num_cntrs = 0, .num_fixed_cntrs = 3, .max_encoding = 1, .pe = intel_rapl_cln_pe, /* default, maybe updated */ .pmu_detect = pfm_rapl_detect, .atdesc = rapl_mods, .get_event_encoding[PFM_OS_NONE] = pfm_intel_rapl_get_encoding, PFMLIB_ENCODE_PERF(pfm_intel_x86_get_perf_encoding), PFMLIB_OS_DETECT(pfm_intel_x86_perf_detect), \ .get_event_first = pfm_intel_x86_get_event_first, .get_event_next = pfm_intel_x86_get_event_next, .event_is_valid = pfm_intel_x86_event_is_valid, .validate_table = pfm_intel_x86_validate_table, .get_event_info = pfm_intel_x86_get_event_info, .get_event_attr_info = pfm_intel_x86_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_intel_x86_perf_validate_pattrs), .get_event_nattrs = pfm_intel_x86_get_event_nattrs, }; libpfm-4.9.0/lib/pfmlib_amd64_fam11h.c0000664000175000017500000000467013223402656017140 0ustar eranianeranian/* * pfmlib_amd64_fam11h.c : AMD64 Family 11h * * Copyright (c) 2012 University of Tennessee * Contributed by Vince Weaver * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_amd64_priv.h" #include "events/amd64_events_fam11h.h" #define DEFINE_FAM11H_REV(d, n, r, pmuid) \ pfmlib_pmu_t amd64_fam11h_##n##_support={ \ .desc = "AMD64 Fam11h "#d, \ .name = "amd64_fam11h_"#n, \ .pmu = pmuid, \ .pmu_rev = r, \ .pme_count = LIBPFM_ARRAY_SIZE(amd64_fam11h_pe),\ .type = PFM_PMU_TYPE_CORE, \ .supported_plm = AMD64_FAM10H_PLM, \ .num_cntrs = 4, \ .max_encoding = 1, \ .pe = amd64_fam11h_pe, \ .atdesc = amd64_mods, \ .flags = PFMLIB_PMU_FL_RAW_UMASK, \ \ .cpu_family = pmuid, \ .pmu_detect = pfm_amd64_family_detect, \ .get_event_encoding[PFM_OS_NONE] = pfm_amd64_get_encoding,\ PFMLIB_ENCODE_PERF(pfm_amd64_get_perf_encoding), \ .get_event_first = pfm_amd64_get_event_first, \ .get_event_next = pfm_amd64_get_event_next, \ .event_is_valid = pfm_amd64_event_is_valid, \ .validate_table = pfm_amd64_validate_table, \ .get_event_info = pfm_amd64_get_event_info, \ .get_event_attr_info = pfm_amd64_get_event_attr_info,\ PFMLIB_VALID_PERF_PATTRS(pfm_amd64_perf_validate_pattrs),\ .get_event_nattrs = pfm_amd64_get_event_nattrs, \ } DEFINE_FAM11H_REV(Turion, turion, 0, PFM_PMU_AMD64_FAM11H_TURION); libpfm-4.9.0/lib/pfmlib_sparc_ultra3.c0000664000175000017500000000776213223402656017477 0ustar eranianeranian/* * pfmlib_sparc_ultra3.c : SPARC Ultra I, II * * Copyright (c) 2011 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * Core PMU = architectural perfmon v2 + PEBS */ /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_sparc_priv.h" #include "events/sparc_ultra3_events.h" #include "events/sparc_ultra3i_events.h" #include "events/sparc_ultra3plus_events.h" pfmlib_pmu_t sparc_ultra3_support={ .desc = "Ultra Sparc III", .name = "ultra3", .pmu = PFM_PMU_SPARC_ULTRA3, .pme_count = LIBPFM_ARRAY_SIZE(ultra3_pe), .type = PFM_PMU_TYPE_CORE, .supported_plm = SPARC_PLM, .max_encoding = 2, .num_cntrs = 2, .pe = ultra3_pe, .atdesc = NULL, .flags = 0, .pmu_detect = pfm_sparc_detect, .get_event_encoding[PFM_OS_NONE] = pfm_sparc_get_encoding, PFMLIB_ENCODE_PERF(pfm_sparc_get_perf_encoding), .get_event_first = pfm_sparc_get_event_first, .get_event_next = pfm_sparc_get_event_next, .event_is_valid = pfm_sparc_event_is_valid, .validate_table = pfm_sparc_validate_table, .get_event_info = pfm_sparc_get_event_info, .get_event_attr_info = pfm_sparc_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_sparc_perf_validate_pattrs), .get_event_nattrs = pfm_sparc_get_event_nattrs, }; pfmlib_pmu_t sparc_ultra3i_support={ .desc = "Ultra Sparc IIIi", .name = "ultra3i", .pmu = PFM_PMU_SPARC_ULTRA3I, .pme_count = LIBPFM_ARRAY_SIZE(ultra3i_pe), .type = PFM_PMU_TYPE_CORE, .supported_plm = SPARC_PLM, .num_cntrs = 2, .max_encoding = 2, .pe = ultra3i_pe, .atdesc = NULL, .flags = 0, .pmu_detect = pfm_sparc_detect, .get_event_encoding[PFM_OS_NONE] = pfm_sparc_get_encoding, PFMLIB_ENCODE_PERF(pfm_sparc_get_perf_encoding), .get_event_first = pfm_sparc_get_event_first, .get_event_next = pfm_sparc_get_event_next, .event_is_valid = pfm_sparc_event_is_valid, .validate_table = pfm_sparc_validate_table, .get_event_info = pfm_sparc_get_event_info, .get_event_attr_info = pfm_sparc_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_sparc_perf_validate_pattrs), .get_event_nattrs = pfm_sparc_get_event_nattrs, }; pfmlib_pmu_t sparc_ultra3plus_support={ .desc = "Ultra Sparc III+", .name = "ultra3p", .pmu = PFM_PMU_SPARC_ULTRA3PLUS, .pme_count = LIBPFM_ARRAY_SIZE(ultra3plus_pe), .type = PFM_PMU_TYPE_CORE, .supported_plm = SPARC_PLM, .max_encoding = 2, .num_cntrs = 2, .pe = ultra3plus_pe, .atdesc = NULL, .flags = 0, .pmu_detect = pfm_sparc_detect, .get_event_encoding[PFM_OS_NONE] = pfm_sparc_get_encoding, PFMLIB_ENCODE_PERF(pfm_sparc_get_perf_encoding), .get_event_first = pfm_sparc_get_event_first, .get_event_next = pfm_sparc_get_event_next, .event_is_valid = pfm_sparc_event_is_valid, .validate_table = pfm_sparc_validate_table, .get_event_info = pfm_sparc_get_event_info, .get_event_attr_info = pfm_sparc_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_sparc_perf_validate_pattrs), .get_event_nattrs = pfm_sparc_get_event_nattrs, }; libpfm-4.9.0/lib/pfmlib_intel_bdw.c0000664000175000017500000000771213223402656017037 0ustar eranianeranian/* * pfmlib_intel_bdw.c : Intel Broadwell core PMU * * Copyright (c) 2014 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_intel_x86_priv.h" #include "events/intel_bdw_events.h" static const int bdw_models[] = { 61, /* Broadwell Core-M */ 71, /* Broadwell + GT3e (Iris Pro graphics) */ 0 }; static const int bdwep_models[] = { 79, /* Broadwell-EP, Xeon */ 86, /* Broadwell-EP, Xeon D */ 0 }; static int pfm_bdw_init(void *this) { pfm_intel_x86_cfg.arch_version = 4; return PFM_SUCCESS; } pfmlib_pmu_t intel_bdw_support={ .desc = "Intel Broadwell", .name = "bdw", .pmu = PFM_PMU_INTEL_BDW, .pme_count = LIBPFM_ARRAY_SIZE(intel_bdw_pe), .type = PFM_PMU_TYPE_CORE, .supported_plm = INTEL_X86_PLM, .num_cntrs = 8, /* consider with HT off by default */ .num_fixed_cntrs = 3, .max_encoding = 2, /* offcore_response */ .pe = intel_bdw_pe, .atdesc = intel_x86_mods, .flags = PFMLIB_PMU_FL_RAW_UMASK | INTEL_X86_PMU_FL_ECMASK, .cpu_family = 6, .cpu_models = bdw_models, .pmu_detect = pfm_intel_x86_model_detect, .pmu_init = pfm_bdw_init, .get_event_encoding[PFM_OS_NONE] = pfm_intel_x86_get_encoding, PFMLIB_ENCODE_PERF(pfm_intel_x86_get_perf_encoding), .get_event_first = pfm_intel_x86_get_event_first, .get_event_next = pfm_intel_x86_get_event_next, .event_is_valid = pfm_intel_x86_event_is_valid, .validate_table = pfm_intel_x86_validate_table, .get_event_info = pfm_intel_x86_get_event_info, .get_event_attr_info = pfm_intel_x86_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_intel_x86_perf_validate_pattrs), .get_event_nattrs = pfm_intel_x86_get_event_nattrs, .can_auto_encode = pfm_intel_x86_can_auto_encode, }; pfmlib_pmu_t intel_bdw_ep_support={ .desc = "Intel Broadwell EP", .name = "bdw_ep", .pmu = PFM_PMU_INTEL_BDW_EP, .pme_count = LIBPFM_ARRAY_SIZE(intel_bdw_pe), .type = PFM_PMU_TYPE_CORE, .supported_plm = INTEL_X86_PLM, .num_cntrs = 8, /* consider with HT off by default */ .num_fixed_cntrs = 3, .max_encoding = 2, /* offcore_response */ .pe = intel_bdw_pe, .atdesc = intel_x86_mods, .flags = PFMLIB_PMU_FL_RAW_UMASK | INTEL_X86_PMU_FL_ECMASK, .cpu_family = 6, .cpu_models = bdwep_models, .pmu_detect = pfm_intel_x86_model_detect, .pmu_init = pfm_bdw_init, .get_event_encoding[PFM_OS_NONE] = pfm_intel_x86_get_encoding, PFMLIB_ENCODE_PERF(pfm_intel_x86_get_perf_encoding), .get_event_first = pfm_intel_x86_get_event_first, .get_event_next = pfm_intel_x86_get_event_next, .event_is_valid = pfm_intel_x86_event_is_valid, .validate_table = pfm_intel_x86_validate_table, .get_event_info = pfm_intel_x86_get_event_info, .get_event_attr_info = pfm_intel_x86_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_intel_x86_perf_validate_pattrs), .get_event_nattrs = pfm_intel_x86_get_event_nattrs, .can_auto_encode = pfm_intel_x86_can_auto_encode, }; libpfm-4.9.0/lib/pfmlib_itanium2_priv.h0000664000175000017500000001217113223402656017660 0ustar eranianeranian/* * Copyright (c) 2002-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux/ia64. */ #ifndef __PFMLIB_ITANIUM2_PRIV_H__ #define __PFMLIB_ITANIUM2_PRIV_H__ /* * Event type definitions * * The virtual events are not really defined in the specs but are an artifact used * to quickly and easily setup EAR and/or BTB. The event type encodes the exact feature * which must be configured in combination with a counting monitor. * For instance, DATA_EAR_CACHE_LAT4 is a virtual D-EAR cache event. If the user * requests this event, this will configure a counting monitor to count DATA_EAR_EVENTS * and PMC11 will be configured for cache mode. The latency is encoded in the umask, here * it would correspond to 4 cycles. * */ #define PFMLIB_ITA2_EVENT_NORMAL 0x0 /* standard counter */ #define PFMLIB_ITA2_EVENT_BTB 0x1 /* virtual event used with BTB configuration */ #define PFMLIB_ITA2_EVENT_IEAR_TLB 0x2 /* virtual event used for I-EAR TLB configuration */ #define PFMLIB_ITA2_EVENT_IEAR_CACHE 0x3 /* virtual event used for I-EAR cache configuration */ #define PFMLIB_ITA2_EVENT_DEAR_TLB 0x4 /* virtual event used for D-EAR TLB configuration */ #define PFMLIB_ITA2_EVENT_DEAR_CACHE 0x5 /* virtual event used for D-EAR cache configuration */ #define PFMLIB_ITA2_EVENT_DEAR_ALAT 0x6 /* virtual event used for D-EAR ALAT configuration */ #define event_is_ear(e) ((e)->pme_type >= PFMLIB_ITA2_EVENT_IEAR_TLB &&(e)->pme_type <= PFMLIB_ITA2_EVENT_DEAR_ALAT) #define event_is_iear(e) ((e)->pme_type == PFMLIB_ITA2_EVENT_IEAR_TLB || (e)->pme_type == PFMLIB_ITA2_EVENT_IEAR_CACHE) #define event_is_dear(e) ((e)->pme_type >= PFMLIB_ITA2_EVENT_DEAR_TLB && (e)->pme_type <= PFMLIB_ITA2_EVENT_DEAR_ALAT) #define event_is_ear_cache(e) ((e)->pme_type == PFMLIB_ITA2_EVENT_DEAR_CACHE || (e)->pme_type == PFMLIB_ITA2_EVENT_IEAR_CACHE) #define event_is_ear_tlb(e) ((e)->pme_type == PFMLIB_ITA2_EVENT_IEAR_TLB || (e)->pme_type == PFMLIB_ITA2_EVENT_DEAR_TLB) #define event_is_ear_alat(e) ((e)->pme_type == PFMLIB_ITA2_EVENT_DEAR_ALAT) #define event_is_btb(e) ((e)->pme_type == PFMLIB_ITA2_EVENT_BTB) /* * Itanium encoding structure * (code must be first 8 bits) */ typedef struct { unsigned long pme_code:8; /* major event code */ unsigned long pme_type:3; /* see definitions above */ unsigned long pme_ig1:5; /* ignored */ unsigned long pme_umask:16; /* unit mask*/ unsigned long pme_ig:32; /* ignored */ } pme_ita2_entry_code_t; typedef union { unsigned long pme_vcode; pme_ita2_entry_code_t pme_ita2_code; /* must not be larger than vcode */ } pme_ita2_code_t; typedef union { unsigned long qual; /* generic qualifier */ struct { unsigned long pme_iar:1; /* instruction address range supported */ unsigned long pme_opm:1; /* opcode match supported */ unsigned long pme_dar:1; /* data address range supported */ unsigned long pme_res1:13; /* reserved */ unsigned long pme_group:4; /* event group */ unsigned long pme_set:4; /* event feature set*/ unsigned long pme_res2:40; /* reserved */ } pme_qual; } pme_ita2_qualifiers_t; typedef struct { char *pme_name; pme_ita2_code_t pme_entry_code; unsigned long pme_counters; /* supported counters */ unsigned int pme_maxincr; pme_ita2_qualifiers_t pme_qualifiers; char *pme_desc; /* text description of the event */ } pme_ita2_entry_t; /* * We embed the umask value into the event code. Because it really is * like a subevent. * pme_code: * - lower 16 bits: major event code * - upper 16 bits: unit mask */ #define pme_code pme_entry_code.pme_ita2_code.pme_code #define pme_umask pme_entry_code.pme_ita2_code.pme_umask #define pme_used pme_qualifiers.pme_qual_struct.pme_used #define pme_type pme_entry_code.pme_ita2_code.pme_type #define event_opcm_ok(e) ((e)->pme_qualifiers.pme_qual.pme_opm==1) #define event_iarr_ok(e) ((e)->pme_qualifiers.pme_qual.pme_iar==1) #define event_darr_ok(e) ((e)->pme_qualifiers.pme_qual.pme_dar==1) #endif /* __PFMLIB_ITANIUM2_PRIV_H__ */ libpfm-4.9.0/lib/pfmlib_amd64_fam16h.c0000664000175000017500000000436413223402656017145 0ustar eranianeranian/* * pfmlib_amd64_fam16h.c : AMD64 Family 16h * * Copyright (c) 2017 by Vince Weaver * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_amd64_priv.h" #include "events/amd64_events_fam16h.h" pfmlib_pmu_t amd64_fam16h_support={ .desc = "AMD64 Fam16h Jaguar", .name = "amd64_fam16h", .pmu = PFM_PMU_AMD64_FAM16H, .pmu_rev = 0, .pme_count = LIBPFM_ARRAY_SIZE(amd64_fam16h_pe), .type = PFM_PMU_TYPE_CORE, .supported_plm = AMD64_FAM10H_PLM, .num_cntrs = 4, .max_encoding = 1, .pe = amd64_fam16h_pe, .atdesc = amd64_mods, .flags = PFMLIB_PMU_FL_RAW_UMASK, .cpu_family = PFM_PMU_AMD64_FAM16H, .pmu_detect = pfm_amd64_family_detect, .get_event_encoding[PFM_OS_NONE] = pfm_amd64_get_encoding, PFMLIB_ENCODE_PERF(pfm_amd64_get_perf_encoding), .get_event_first = pfm_amd64_get_event_first, .get_event_next = pfm_amd64_get_event_next, .event_is_valid = pfm_amd64_event_is_valid, .validate_table = pfm_amd64_validate_table, .get_event_info = pfm_amd64_get_event_info, .get_event_attr_info = pfm_amd64_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_amd64_perf_validate_pattrs), .get_event_nattrs = pfm_amd64_get_event_nattrs, }; libpfm-4.9.0/lib/pfmlib_power6.c0000664000175000017500000000435013223402656016305 0ustar eranianeranian/* * pfmlib_power6.c : IBM Power6 support * * Copyright (C) IBM Corporation, 2009. All rights reserved. * Contributed by Corey Ashford (cjashfor@us.ibm.com) * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_power_priv.h" #include "events/power6_events.h" static int pfm_power6_detect(void* this) { if (__is_processor(PV_POWER6)) return PFM_SUCCESS; return PFM_ERR_NOTSUPP; } pfmlib_pmu_t power6_support={ .desc = "POWER6", .name = "power6", .pmu = PFM_PMU_POWER6, .pme_count = LIBPFM_ARRAY_SIZE(power6_pe), .type = PFM_PMU_TYPE_CORE, .num_cntrs = 4, .num_fixed_cntrs = 2, .max_encoding = 1, .pe = power6_pe, .pmu_detect = pfm_power6_detect, .get_event_encoding[PFM_OS_NONE] = pfm_gen_powerpc_get_encoding, PFMLIB_ENCODE_PERF(pfm_gen_powerpc_get_perf_encoding), PFMLIB_VALID_PERF_PATTRS(pfm_gen_powerpc_perf_validate_pattrs), .get_event_first = pfm_gen_powerpc_get_event_first, .get_event_next = pfm_gen_powerpc_get_event_next, .event_is_valid = pfm_gen_powerpc_event_is_valid, .validate_table = pfm_gen_powerpc_validate_table, .get_event_info = pfm_gen_powerpc_get_event_info, .get_event_attr_info = pfm_gen_powerpc_get_event_attr_info, }; libpfm-4.9.0/lib/pfmlib_gen_ia64.c0000664000175000017500000003250613223402656016463 0ustar eranianeranian/* * pfmlib_gen_ia64.c : support default architected IA-64 PMU features * * Copyright (c) 2001-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include #include #include "pfmlib_priv.h" /* library private */ #include "pfmlib_priv_ia64.h" /* architecture private */ #define PMU_GEN_IA64_MAX_COUNTERS 4 /* * number of architected events */ #define PME_GEN_COUNT 2 /* * Description of the PMC register mappings use by * this module (as reported in pfmlib_reg_t.reg_num): * * 0 -> PMC0 * 1 -> PMC1 * n -> PMCn */ #define PFMLIB_GEN_IA64_PMC_BASE 0 /* * generic event as described by architecture */ typedef struct { unsigned long pme_code:8; /* major event code */ unsigned long pme_ig:56; /* ignored */ } pme_gen_ia64_code_t; /* * union of all possible entry codes. All encodings must fit in 64bit */ typedef union { unsigned long pme_vcode; pme_gen_ia64_code_t pme_gen_code; } pme_gen_ia64_entry_code_t; /* * entry in the event table (one table per implementation) */ typedef struct pme_entry { char *pme_name; pme_gen_ia64_entry_code_t pme_entry_code; /* event code */ pfmlib_regmask_t pme_counters; /* counter bitmask */ } pme_gen_ia64_entry_t; /* let's define some handy shortcuts ! */ #define pmc_plm pmc_gen_count_reg.pmc_plm #define pmc_ev pmc_gen_count_reg.pmc_ev #define pmc_oi pmc_gen_count_reg.pmc_oi #define pmc_pm pmc_gen_count_reg.pmc_pm #define pmc_es pmc_gen_count_reg.pmc_es /* * this table is patched by initialization code */ static pme_gen_ia64_entry_t generic_pe[PME_GEN_COUNT]={ #define PME_IA64_GEN_CPU_CYCLES 0 { "CPU_CYCLES", }, #define PME_IA64_GEN_INST_RETIRED 1 { "IA64_INST_RETIRED", }, }; static int pfm_gen_ia64_counter_width; static int pfm_gen_ia64_counters; static pfmlib_regmask_t pfm_gen_ia64_impl_pmcs; static pfmlib_regmask_t pfm_gen_ia64_impl_pmds; /* * Description of the PMC register mappings use by * this module (as reported in pfmlib_reg_t.reg_num): * * 0 -> PMC0 * 1 -> PMC1 * n -> PMCn * We do not use a mapping table, instead we make up the * values on the fly given the base. */ #define PFMLIB_GEN_IA64_PMC_BASE 0 /* * convert text range (e.g. 4-15 18 12-26) into actual bitmask * range argument is modified */ static int parse_counter_range(char *range, pfmlib_regmask_t *b) { char *p, c; int start, end; if (range[strlen(range)-1] == '\n') range[strlen(range)-1] = '\0'; while(range) { p = range; while (*p && *p != ' ' && *p != '-') p++; if (*p == '\0') break; c = *p; *p = '\0'; start = atoi(range); range = p+1; if (c == '-') { p++; while (*p && *p != ' ' && *p != '-') p++; if (*p) *p++ = '\0'; end = atoi(range); range = p; } else { end = start; } if (end >= PFMLIB_REG_MAX|| start >= PFMLIB_REG_MAX) goto invalid; for (; start <= end; start++) pfm_regmask_set(b, start); } return 0; invalid: fprintf(stderr, "%s.%s : bitmask too small need %d bits\n", __FILE__, __FUNCTION__, start); return -1; } static int pfm_gen_ia64_initialize(void) { FILE *fp; char *p; char buffer[64]; int matches = 0; fp = fopen("/proc/pal/cpu0/perfmon_info", "r"); if (fp == NULL) return PFMLIB_ERR_NOTSUPP; for (;;) { p = fgets(buffer, sizeof(buffer)-1, fp); if (p == NULL) break; if ((p = strchr(buffer, ':')) == NULL) break; *p = '\0'; if (!strncmp("Counter width", buffer, 13)) { pfm_gen_ia64_counter_width = atoi(p+2); matches++; continue; } if (!strncmp("PMC/PMD pairs", buffer, 13)) { pfm_gen_ia64_counters = atoi(p+2); matches++; continue; } if (!strncmp("Cycle event number", buffer, 18)) { generic_pe[0].pme_entry_code.pme_vcode = atoi(p+2); matches++; continue; } if (!strncmp("Retired event number", buffer, 20)) { generic_pe[1].pme_entry_code.pme_vcode = atoi(p+2); matches++; continue; } if (!strncmp("Cycles count capable", buffer, 20)) { if (parse_counter_range(p+2, &generic_pe[0].pme_counters) == -1) return -1; matches++; continue; } if (!strncmp("Retired bundles count capable", buffer, 29)) { if (parse_counter_range(p+2, &generic_pe[1].pme_counters) == -1) return -1; matches++; continue; } if (!strncmp("Implemented PMC", buffer, 15)) { if (parse_counter_range(p+2, &pfm_gen_ia64_impl_pmcs) == -1) return -1; matches++; continue; } if (!strncmp("Implemented PMD", buffer, 15)) { if (parse_counter_range(p+2, &pfm_gen_ia64_impl_pmds) == -1) return -1; matches++; continue; } } pfm_regmask_weight(&pfm_gen_ia64_impl_pmcs, &generic_ia64_support.pmc_count); pfm_regmask_weight(&pfm_gen_ia64_impl_pmds, &generic_ia64_support.pmd_count); fclose(fp); return matches == 8 ? PFMLIB_SUCCESS : PFMLIB_ERR_NOTSUPP; } static void pfm_gen_ia64_forced_initialize(void) { unsigned int i; pfm_gen_ia64_counter_width = 47; pfm_gen_ia64_counters = 4; generic_pe[0].pme_entry_code.pme_vcode = 18; generic_pe[1].pme_entry_code.pme_vcode = 8; memset(&pfm_gen_ia64_impl_pmcs, 0, sizeof(pfmlib_regmask_t)); memset(&pfm_gen_ia64_impl_pmds, 0, sizeof(pfmlib_regmask_t)); for(i=0; i < 8; i++) pfm_regmask_set(&pfm_gen_ia64_impl_pmcs, i); for(i=4; i < 8; i++) pfm_regmask_set(&pfm_gen_ia64_impl_pmds, i); memset(&generic_pe[0].pme_counters, 0, sizeof(pfmlib_regmask_t)); memset(&generic_pe[1].pme_counters, 0, sizeof(pfmlib_regmask_t)); for(i=4; i < 8; i++) { pfm_regmask_set(&generic_pe[0].pme_counters, i); pfm_regmask_set(&generic_pe[1].pme_counters, i); } generic_ia64_support.pmc_count = 8; generic_ia64_support.pmd_count = 4; generic_ia64_support.num_cnt = 4; } static int pfm_gen_ia64_detect(void) { /* PMU is architected, so guaranteed to be present */ return PFMLIB_SUCCESS; } static int pfm_gen_ia64_init(void) { if (forced_pmu != PFMLIB_NO_PMU) { pfm_gen_ia64_forced_initialize(); } else if (pfm_gen_ia64_initialize() == -1) return PFMLIB_ERR_NOTSUPP; return PFMLIB_SUCCESS; } static int valid_assign(unsigned int *as, pfmlib_regmask_t *r_pmcs, unsigned int cnt) { unsigned int i; for(i=0; i < cnt; i++) { if (as[i]==0) return 0; /* * take care of restricted PMC registers */ if (pfm_regmask_isset(r_pmcs, as[i])) return 0; } return 1; } /* * Automatically dispatch events to corresponding counters following constraints. * Upon return the pfarg_reg_t structure is ready to be submitted to kernel */ static int pfm_gen_ia64_dispatch_counters(pfmlib_input_param_t *inp, pfmlib_output_param_t *outp) { #define has_counter(e,b) (pfm_regmask_isset(&generic_pe[e].pme_counters, b) ? b : 0) unsigned int max_l0, max_l1, max_l2, max_l3; unsigned int assign[PMU_GEN_IA64_MAX_COUNTERS]; pfm_gen_ia64_pmc_reg_t reg; pfmlib_event_t *e; pfmlib_reg_t *pc, *pd; pfmlib_regmask_t *r_pmcs; unsigned int i,j,k,l; unsigned int cnt; e = inp->pfp_events; pc = outp->pfp_pmcs; pd = outp->pfp_pmds; cnt = inp->pfp_event_count; r_pmcs = &inp->pfp_unavail_pmcs; if (cnt > PMU_GEN_IA64_MAX_COUNTERS) return PFMLIB_ERR_TOOMANY; max_l0 = PMU_GEN_IA64_FIRST_COUNTER + PMU_GEN_IA64_MAX_COUNTERS; max_l1 = PMU_GEN_IA64_FIRST_COUNTER + PMU_GEN_IA64_MAX_COUNTERS*(cnt>1); max_l2 = PMU_GEN_IA64_FIRST_COUNTER + PMU_GEN_IA64_MAX_COUNTERS*(cnt>2); max_l3 = PMU_GEN_IA64_FIRST_COUNTER + PMU_GEN_IA64_MAX_COUNTERS*(cnt>3); if (PFMLIB_DEBUG()) { DPRINT("max_l0=%u max_l1=%u max_l2=%u max_l3=%u\n", max_l0, max_l1, max_l2, max_l3); } /* * This code needs fixing. It is not very pretty and * won't handle more than 4 counters if more become * available ! * For now, worst case in the loop nest: 4! (factorial) */ for (i=PMU_GEN_IA64_FIRST_COUNTER; i < max_l0; i++) { assign[0]= has_counter(e[0].event,i); if (max_l1 == PMU_GEN_IA64_FIRST_COUNTER && valid_assign(assign, r_pmcs, cnt)) goto done; for (j=PMU_GEN_IA64_FIRST_COUNTER; j < max_l1; j++) { if (j == i) continue; assign[1] = has_counter(e[1].event,j); if (max_l2 == PMU_GEN_IA64_FIRST_COUNTER && valid_assign(assign, r_pmcs, cnt)) goto done; for (k=PMU_GEN_IA64_FIRST_COUNTER; k < max_l2; k++) { if(k == i || k == j) continue; assign[2] = has_counter(e[2].event,k); if (max_l3 == PMU_GEN_IA64_FIRST_COUNTER && valid_assign(assign, r_pmcs, cnt)) goto done; for (l=PMU_GEN_IA64_FIRST_COUNTER; l < max_l3; l++) { if(l == i || l == j || l == k) continue; assign[3] = has_counter(e[3].event,l); if (valid_assign(assign, r_pmcs, cnt)) goto done; } } } } /* we cannot satisfy the constraints */ return PFMLIB_ERR_NOASSIGN; done: memset(pc, 0, cnt*sizeof(pfmlib_reg_t)); memset(pd, 0, cnt*sizeof(pfmlib_reg_t)); for (j=0; j < cnt ; j++ ) { reg.pmc_val = 0; /* clear all */ /* if not specified per event, then use default (could be zero: measure nothing) */ reg.pmc_plm = e[j].plm ? e[j].plm: inp->pfp_dfl_plm; reg.pmc_oi = 1; /* overflow interrupt */ reg.pmc_pm = inp->pfp_flags & PFMLIB_PFP_SYSTEMWIDE? 1 : 0; reg.pmc_es = generic_pe[e[j].event].pme_entry_code.pme_gen_code.pme_code; pc[j].reg_num = assign[j]; pc[j].reg_value = reg.pmc_val; pc[j].reg_addr = PFMLIB_GEN_IA64_PMC_BASE+j; pd[j].reg_num = assign[j]; pd[j].reg_addr = assign[j]; __pfm_vbprintf("[PMC%u(pmc%u)=0x%lx,es=0x%02x,plm=%d pm=%d] %s\n", assign[j], assign[j], reg.pmc_val, reg.pmc_es,reg.pmc_plm, reg.pmc_pm, generic_pe[e[j].event].pme_name); __pfm_vbprintf("[PMD%u(pmd%u)]\n", pd[j].reg_num, pd[j].reg_num); } /* number of PMC programmed */ outp->pfp_pmc_count = cnt; outp->pfp_pmd_count = cnt; return PFMLIB_SUCCESS; } static int pfm_gen_ia64_dispatch_events(pfmlib_input_param_t *inp, void *dummy1, pfmlib_output_param_t *outp, void *dummy2) { return pfm_gen_ia64_dispatch_counters(inp, outp); } static int pfm_gen_ia64_get_event_code(unsigned int i, unsigned int cnt, int *code) { if (cnt != PFMLIB_CNT_FIRST && (cnt < 4 || cnt > 7)) return PFMLIB_ERR_INVAL; *code = (int)generic_pe[i].pme_entry_code.pme_gen_code.pme_code; return PFMLIB_SUCCESS; } static char * pfm_gen_ia64_get_event_name(unsigned int i) { return generic_pe[i].pme_name; } static void pfm_gen_ia64_get_event_counters(unsigned int j, pfmlib_regmask_t *counters) { unsigned int i; memset(counters, 0, sizeof(*counters)); for(i=0; i < pfm_gen_ia64_counters; i++) { if (pfm_regmask_isset(&generic_pe[j].pme_counters, i)) pfm_regmask_set(counters, i); } } static void pfm_gen_ia64_get_impl_pmcs(pfmlib_regmask_t *impl_pmcs) { *impl_pmcs = pfm_gen_ia64_impl_pmcs; } static void pfm_gen_ia64_get_impl_pmds(pfmlib_regmask_t *impl_pmds) { *impl_pmds = pfm_gen_ia64_impl_pmds; } static void pfm_gen_ia64_get_impl_counters(pfmlib_regmask_t *impl_counters) { unsigned int i = 0; /* pmd4-pmd7 */ for(i=4; i < 8; i++) pfm_regmask_set(impl_counters, i); } static void pfm_gen_ia64_get_hw_counter_width(unsigned int *width) { *width = pfm_gen_ia64_counter_width; } static int pfm_gen_ia64_get_event_desc(unsigned int ev, char **str) { switch(ev) { case PME_IA64_GEN_CPU_CYCLES: *str = strdup("CPU cycles"); break; case PME_IA64_GEN_INST_RETIRED: *str = strdup("IA-64 instructions retired"); break; default: *str = NULL; } return PFMLIB_SUCCESS; } static int pfm_gen_ia64_get_cycle_event(pfmlib_event_t *e) { e->event = PME_IA64_GEN_CPU_CYCLES; return PFMLIB_SUCCESS; } static int pfm_gen_ia64_get_inst_retired(pfmlib_event_t *e) { e->event = PME_IA64_GEN_INST_RETIRED; return PFMLIB_SUCCESS; } pfm_pmu_support_t generic_ia64_support={ .pmu_name ="IA-64", .pmu_type = PFMLIB_GEN_IA64_PMU, .pme_count = PME_GEN_COUNT, .pmc_count = 4+4, .pmd_count = PMU_GEN_IA64_MAX_COUNTERS, .num_cnt = PMU_GEN_IA64_MAX_COUNTERS, .get_event_code = pfm_gen_ia64_get_event_code, .get_event_name = pfm_gen_ia64_get_event_name, .get_event_counters = pfm_gen_ia64_get_event_counters, .dispatch_events = pfm_gen_ia64_dispatch_events, .pmu_detect = pfm_gen_ia64_detect, .pmu_init = pfm_gen_ia64_init, .get_impl_pmcs = pfm_gen_ia64_get_impl_pmcs, .get_impl_pmds = pfm_gen_ia64_get_impl_pmds, .get_impl_counters = pfm_gen_ia64_get_impl_counters, .get_hw_counter_width = pfm_gen_ia64_get_hw_counter_width, .get_event_desc = pfm_gen_ia64_get_event_desc, .get_cycle_event = pfm_gen_ia64_get_cycle_event, .get_inst_retired_event = pfm_gen_ia64_get_inst_retired }; libpfm-4.9.0/lib/pfmlib_arm_priv.h0000664000175000017500000000706013223402656016710 0ustar eranianeranian/* * Copyright (c) 2010 University of Tennessee * Contributed by Vince Weaver * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. */ #ifndef __PFMLIB_ARM_PRIV_H__ #define __PFMLIB_ARM_PRIV_H__ /* * This file contains the definitions used for ARM processors */ /* * event description */ typedef struct { const char *name; /* event name */ const char *desc; /* event description */ unsigned int code; /* event code */ unsigned int modmsk; /* modifiers bitmask */ } arm_entry_t; typedef union pfm_arm_reg { unsigned int val; /* complete register value */ struct { unsigned int sel:8; unsigned int reserved1:19; unsigned int excl_hyp:1; unsigned int reserved2:2; unsigned int excl_pl1:1; unsigned int excl_usr:1; } evtsel; } pfm_arm_reg_t; typedef struct { int implementer; int architecture; int part; } pfm_arm_config_t; extern pfm_arm_config_t pfm_arm_cfg; extern int pfm_arm_detect(void *this); extern int pfm_arm_get_encoding(void *this, pfmlib_event_desc_t *e); extern int pfm_arm_get_event_first(void *this); extern int pfm_arm_get_event_next(void *this, int idx); extern int pfm_arm_event_is_valid(void *this, int pidx); extern int pfm_arm_validate_table(void *this, FILE *fp); extern int pfm_arm_get_event_attr_info(void *this, int pidx, int attr_idx, pfmlib_event_attr_info_t *info); extern int pfm_arm_get_event_info(void *this, int idx, pfm_event_info_t *info); extern unsigned int pfm_arm_get_event_nattrs(void *this, int pidx); extern void pfm_arm_perf_validate_pattrs(void *this, pfmlib_event_desc_t *e); extern int pfm_arm_get_perf_encoding(void *this, pfmlib_event_desc_t *e); #define ARM_ATTR_K 0 /* pl1 priv level */ #define ARM_ATTR_U 1 /* user priv level */ #define ARM_ATTR_HV 2 /* hypervisor priv level */ #define _ARM_ATTR_K (1 << ARM_ATTR_K) #define _ARM_ATTR_U (1 << ARM_ATTR_U) #define _ARM_ATTR_HV (1 << ARM_ATTR_HV) #define ARM_ATTR_PLM_ALL (_ARM_ATTR_K|_ARM_ATTR_U|_ARM_ATTR_HV) #define ARMV7_A15_ATTRS (_ARM_ATTR_K|_ARM_ATTR_U|_ARM_ATTR_HV) #define ARMV7_A15_PLM (PFM_PLM0|PFM_PLM3|PFM_PLMH) #define ARMV7_A7_ATTRS (_ARM_ATTR_K|_ARM_ATTR_U|_ARM_ATTR_HV) #define ARMV7_A7_PLM (PFM_PLM0|PFM_PLM3|PFM_PLMH) #define ARMV8_ATTRS (_ARM_ATTR_K|_ARM_ATTR_U|_ARM_ATTR_HV) #define ARMV8_PLM (PFM_PLM0|PFM_PLM3|PFM_PLMH) static inline int arm_has_plm(void *this, pfmlib_event_desc_t *e) { const arm_entry_t *pe = this_pe(this); return pe[e->event].modmsk & ARM_ATTR_PLM_ALL; } #endif /* __PFMLIB_ARM_PRIV_H__ */ libpfm-4.9.0/lib/pfmlib_montecito_priv.h0000664000175000017500000001274013223402656020133 0ustar eranianeranian/* * Copyright (c) 2005-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. */ #ifndef __PFMLIB_MONTECITO_PRIV_H__ #define __PFMLIB_MONTECITO_PRIV_H__ /* * Event type definitions * * The virtual events are not really defined in the specs but are an artifact used * to quickly and easily setup EAR and/or BTB. The event type encodes the exact feature * which must be configured in combination with a counting monitor. * For instance, DATA_EAR_CACHE_LAT4 is a virtual D-EAR cache event. If the user * requests this event, this will configure a counting monitor to count DATA_EAR_EVENTS * and PMC11 will be configured for cache mode. The latency is encoded in the umask, here * it would correspond to 4 cycles. * */ #define PFMLIB_MONT_EVENT_NORMAL 0x0 /* standard counter */ #define PFMLIB_MONT_EVENT_ETB 0x1 /* virtual event used with ETB configuration */ #define PFMLIB_MONT_EVENT_IEAR_TLB 0x2 /* virtual event used for I-EAR TLB configuration */ #define PFMLIB_MONT_EVENT_IEAR_CACHE 0x3 /* virtual event used for I-EAR cache configuration */ #define PFMLIB_MONT_EVENT_DEAR_TLB 0x4 /* virtual event used for D-EAR TLB configuration */ #define PFMLIB_MONT_EVENT_DEAR_CACHE 0x5 /* virtual event used for D-EAR cache configuration */ #define PFMLIB_MONT_EVENT_DEAR_ALAT 0x6 /* virtual event used for D-EAR ALAT configuration */ #define event_is_ear(e) ((e)->pme_type >= PFMLIB_MONT_EVENT_IEAR_TLB &&(e)->pme_type <= PFMLIB_MONT_EVENT_DEAR_ALAT) #define event_is_iear(e) ((e)->pme_type == PFMLIB_MONT_EVENT_IEAR_TLB || (e)->pme_type == PFMLIB_MONT_EVENT_IEAR_CACHE) #define event_is_dear(e) ((e)->pme_type >= PFMLIB_MONT_EVENT_DEAR_TLB && (e)->pme_type <= PFMLIB_MONT_EVENT_DEAR_ALAT) #define event_is_ear_cache(e) ((e)->pme_type == PFMLIB_MONT_EVENT_DEAR_CACHE || (e)->pme_type == PFMLIB_MONT_EVENT_IEAR_CACHE) #define event_is_ear_tlb(e) ((e)->pme_type == PFMLIB_MONT_EVENT_IEAR_TLB || (e)->pme_type == PFMLIB_MONT_EVENT_DEAR_TLB) #define event_is_ear_alat(e) ((e)->pme_type == PFMLIB_MONT_EVENT_DEAR_ALAT) #define event_is_etb(e) ((e)->pme_type == PFMLIB_MONT_EVENT_ETB) /* * Itanium encoding structure * (code must be first 8 bits) */ typedef struct { unsigned long pme_code:8; /* major event code */ unsigned long pme_type:3; /* see definitions above */ unsigned long pme_caf:2; /* Active, Floating, Causal, Self-Floating */ unsigned long pme_ig1:3; /* ignored */ unsigned long pme_umask:16; /* unit mask*/ unsigned long pme_ig:32; /* ignored */ } pme_mont_entry_code_t; typedef union { unsigned long pme_vcode; pme_mont_entry_code_t pme_mont_code; /* must not be larger than vcode */ } pme_mont_code_t; typedef union { unsigned long qual; /* generic qualifier */ struct { unsigned long pme_iar:1; /* instruction address range supported */ unsigned long pme_opm:1; /* opcode match supported */ unsigned long pme_dar:1; /* data address range supported */ unsigned long pme_all:1; /* supports all_thrd=1 */ unsigned long pme_mesi:1; /* event supports MESI */ unsigned long pme_res1:11; /* reserved */ unsigned long pme_group:3; /* event group */ unsigned long pme_set:4; /* event set*/ unsigned long pme_res2:41; /* reserved */ } pme_qual; } pme_mont_qualifiers_t; typedef struct { char *pme_name; pme_mont_code_t pme_entry_code; unsigned long pme_counters; /* supported counters */ unsigned int pme_maxincr; pme_mont_qualifiers_t pme_qualifiers; char *pme_desc; /* text description of the event */ } pme_mont_entry_t; /* * We embed the umask value into the event code. Because it really is * like a subevent. * pme_code: * - lower 16 bits: major event code * - upper 16 bits: unit mask */ #define pme_code pme_entry_code.pme_mont_code.pme_code #define pme_umask pme_entry_code.pme_mont_code.pme_umask #define pme_used pme_qualifiers.pme_qual_struct.pme_used #define pme_type pme_entry_code.pme_mont_code.pme_type #define pme_caf pme_entry_code.pme_mont_code.pme_caf #define event_opcm_ok(e) ((e)->pme_qualifiers.pme_qual.pme_opm==1) #define event_iarr_ok(e) ((e)->pme_qualifiers.pme_qual.pme_iar==1) #define event_darr_ok(e) ((e)->pme_qualifiers.pme_qual.pme_dar==1) #define event_all_ok(e) ((e)->pme_qualifiers.pme_qual.pme_all==1) #define event_mesi_ok(e) ((e)->pme_qualifiers.pme_qual.pme_mesi==1) #endif /* __PFMLIB_MONTECITO_PRIV_H__ */ libpfm-4.9.0/lib/pfmlib_common.c0000664000175000017500000013056013223402656016356 0ustar eranianeranian/* * pfmlib_common.c: set of functions common to all PMU models * * Copyright (c) 2009 Google, Inc * Contributed by Stephane Eranian * * Based on: * Copyright (c) 2001-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include #include #include #include #include "pfmlib_priv.h" static pfmlib_pmu_t *pfmlib_pmus[]= { #ifdef CONFIG_PFMLIB_ARCH_IA64 #if 0 &montecito_support, &itanium2_support, &itanium_support, &generic_ia64_support, /* must always be last for IA-64 */ #endif #endif #ifdef CONFIG_PFMLIB_ARCH_I386 /* 32-bit only processors */ &intel_pii_support, &intel_ppro_support, &intel_p6_support, &intel_pm_support, &intel_coreduo_support, #endif #ifdef CONFIG_PFMLIB_ARCH_X86 /* 32 and 64 bit processors */ &netburst_support, &netburst_p_support, &amd64_k7_support, &amd64_k8_revb_support, &amd64_k8_revc_support, &amd64_k8_revd_support, &amd64_k8_reve_support, &amd64_k8_revf_support, &amd64_k8_revg_support, &amd64_fam10h_barcelona_support, &amd64_fam10h_shanghai_support, &amd64_fam10h_istanbul_support, &amd64_fam11h_turion_support, &amd64_fam12h_llano_support, &amd64_fam14h_bobcat_support, &amd64_fam15h_interlagos_support, &amd64_fam15h_nb_support, &amd64_fam16h_support, &amd64_fam17h_support, &intel_core_support, &intel_atom_support, &intel_nhm_support, &intel_nhm_ex_support, &intel_nhm_unc_support, &intel_wsm_sp_support, &intel_wsm_dp_support, &intel_wsm_unc_support, &intel_snb_support, &intel_snb_unc_cbo0_support, &intel_snb_unc_cbo1_support, &intel_snb_unc_cbo2_support, &intel_snb_unc_cbo3_support, &intel_snb_ep_support, &intel_ivb_support, &intel_ivb_unc_cbo0_support, &intel_ivb_unc_cbo1_support, &intel_ivb_unc_cbo2_support, &intel_ivb_unc_cbo3_support, &intel_ivb_ep_support, &intel_hsw_support, &intel_hsw_ep_support, &intel_bdw_support, &intel_bdw_ep_support, &intel_skl_support, &intel_skx_support, &intel_rapl_support, &intel_snbep_unc_cb0_support, &intel_snbep_unc_cb1_support, &intel_snbep_unc_cb2_support, &intel_snbep_unc_cb3_support, &intel_snbep_unc_cb4_support, &intel_snbep_unc_cb5_support, &intel_snbep_unc_cb6_support, &intel_snbep_unc_cb7_support, &intel_snbep_unc_ha_support, &intel_snbep_unc_imc0_support, &intel_snbep_unc_imc1_support, &intel_snbep_unc_imc2_support, &intel_snbep_unc_imc3_support, &intel_snbep_unc_pcu_support, &intel_snbep_unc_qpi0_support, &intel_snbep_unc_qpi1_support, &intel_snbep_unc_ubo_support, &intel_snbep_unc_r2pcie_support, &intel_snbep_unc_r3qpi0_support, &intel_snbep_unc_r3qpi1_support, &intel_knc_support, &intel_slm_support, &intel_glm_support, &intel_ivbep_unc_cb0_support, &intel_ivbep_unc_cb1_support, &intel_ivbep_unc_cb2_support, &intel_ivbep_unc_cb3_support, &intel_ivbep_unc_cb4_support, &intel_ivbep_unc_cb5_support, &intel_ivbep_unc_cb6_support, &intel_ivbep_unc_cb7_support, &intel_ivbep_unc_cb8_support, &intel_ivbep_unc_cb9_support, &intel_ivbep_unc_cb10_support, &intel_ivbep_unc_cb11_support, &intel_ivbep_unc_cb12_support, &intel_ivbep_unc_cb13_support, &intel_ivbep_unc_cb14_support, &intel_ivbep_unc_ha0_support, &intel_ivbep_unc_ha1_support, &intel_ivbep_unc_imc0_support, &intel_ivbep_unc_imc1_support, &intel_ivbep_unc_imc2_support, &intel_ivbep_unc_imc3_support, &intel_ivbep_unc_imc4_support, &intel_ivbep_unc_imc5_support, &intel_ivbep_unc_imc6_support, &intel_ivbep_unc_imc7_support, &intel_ivbep_unc_pcu_support, &intel_ivbep_unc_qpi0_support, &intel_ivbep_unc_qpi1_support, &intel_ivbep_unc_qpi2_support, &intel_ivbep_unc_ubo_support, &intel_ivbep_unc_r2pcie_support, &intel_ivbep_unc_r3qpi0_support, &intel_ivbep_unc_r3qpi1_support, &intel_ivbep_unc_r3qpi2_support, &intel_ivbep_unc_irp_support, &intel_hswep_unc_cb0_support, &intel_hswep_unc_cb1_support, &intel_hswep_unc_cb2_support, &intel_hswep_unc_cb3_support, &intel_hswep_unc_cb4_support, &intel_hswep_unc_cb5_support, &intel_hswep_unc_cb6_support, &intel_hswep_unc_cb7_support, &intel_hswep_unc_cb8_support, &intel_hswep_unc_cb9_support, &intel_hswep_unc_cb10_support, &intel_hswep_unc_cb11_support, &intel_hswep_unc_cb12_support, &intel_hswep_unc_cb13_support, &intel_hswep_unc_cb14_support, &intel_hswep_unc_cb15_support, &intel_hswep_unc_cb16_support, &intel_hswep_unc_cb17_support, &intel_hswep_unc_ha0_support, &intel_hswep_unc_ha1_support, &intel_hswep_unc_imc0_support, &intel_hswep_unc_imc1_support, &intel_hswep_unc_imc2_support, &intel_hswep_unc_imc3_support, &intel_hswep_unc_imc4_support, &intel_hswep_unc_imc5_support, &intel_hswep_unc_imc6_support, &intel_hswep_unc_imc7_support, &intel_hswep_unc_pcu_support, &intel_hswep_unc_qpi0_support, &intel_hswep_unc_qpi1_support, &intel_hswep_unc_sb0_support, &intel_hswep_unc_sb1_support, &intel_hswep_unc_sb2_support, &intel_hswep_unc_sb3_support, &intel_hswep_unc_ubo_support, &intel_hswep_unc_r2pcie_support, &intel_hswep_unc_r3qpi0_support, &intel_hswep_unc_r3qpi1_support, &intel_hswep_unc_r3qpi2_support, &intel_hswep_unc_irp_support, &intel_knl_support, &intel_knl_unc_imc0_support, &intel_knl_unc_imc1_support, &intel_knl_unc_imc2_support, &intel_knl_unc_imc3_support, &intel_knl_unc_imc4_support, &intel_knl_unc_imc5_support, &intel_knl_unc_imc_uclk0_support, &intel_knl_unc_imc_uclk1_support, &intel_knl_unc_edc_uclk0_support, &intel_knl_unc_edc_uclk1_support, &intel_knl_unc_edc_uclk2_support, &intel_knl_unc_edc_uclk3_support, &intel_knl_unc_edc_uclk4_support, &intel_knl_unc_edc_uclk5_support, &intel_knl_unc_edc_uclk6_support, &intel_knl_unc_edc_uclk7_support, &intel_knl_unc_edc_eclk0_support, &intel_knl_unc_edc_eclk1_support, &intel_knl_unc_edc_eclk2_support, &intel_knl_unc_edc_eclk3_support, &intel_knl_unc_edc_eclk4_support, &intel_knl_unc_edc_eclk5_support, &intel_knl_unc_edc_eclk6_support, &intel_knl_unc_edc_eclk7_support, &intel_knl_unc_cha0_support, &intel_knl_unc_cha1_support, &intel_knl_unc_cha2_support, &intel_knl_unc_cha3_support, &intel_knl_unc_cha4_support, &intel_knl_unc_cha5_support, &intel_knl_unc_cha6_support, &intel_knl_unc_cha7_support, &intel_knl_unc_cha8_support, &intel_knl_unc_cha9_support, &intel_knl_unc_cha10_support, &intel_knl_unc_cha11_support, &intel_knl_unc_cha12_support, &intel_knl_unc_cha13_support, &intel_knl_unc_cha14_support, &intel_knl_unc_cha15_support, &intel_knl_unc_cha16_support, &intel_knl_unc_cha17_support, &intel_knl_unc_cha18_support, &intel_knl_unc_cha19_support, &intel_knl_unc_cha20_support, &intel_knl_unc_cha21_support, &intel_knl_unc_cha22_support, &intel_knl_unc_cha23_support, &intel_knl_unc_cha24_support, &intel_knl_unc_cha25_support, &intel_knl_unc_cha26_support, &intel_knl_unc_cha27_support, &intel_knl_unc_cha28_support, &intel_knl_unc_cha29_support, &intel_knl_unc_cha30_support, &intel_knl_unc_cha31_support, &intel_knl_unc_cha32_support, &intel_knl_unc_cha33_support, &intel_knl_unc_cha34_support, &intel_knl_unc_cha35_support, &intel_knl_unc_cha36_support, &intel_knl_unc_cha37_support, &intel_knl_unc_m2pcie_support, &intel_bdx_unc_cb0_support, &intel_bdx_unc_cb1_support, &intel_bdx_unc_cb2_support, &intel_bdx_unc_cb3_support, &intel_bdx_unc_cb4_support, &intel_bdx_unc_cb5_support, &intel_bdx_unc_cb6_support, &intel_bdx_unc_cb7_support, &intel_bdx_unc_cb8_support, &intel_bdx_unc_cb9_support, &intel_bdx_unc_cb10_support, &intel_bdx_unc_cb11_support, &intel_bdx_unc_cb12_support, &intel_bdx_unc_cb13_support, &intel_bdx_unc_cb14_support, &intel_bdx_unc_cb15_support, &intel_bdx_unc_cb16_support, &intel_bdx_unc_cb17_support, &intel_bdx_unc_cb18_support, &intel_bdx_unc_cb19_support, &intel_bdx_unc_cb20_support, &intel_bdx_unc_cb21_support, &intel_bdx_unc_cb22_support, &intel_bdx_unc_cb23_support, &intel_bdx_unc_ubo_support, &intel_bdx_unc_sbo0_support, &intel_bdx_unc_sbo1_support, &intel_bdx_unc_sbo2_support, &intel_bdx_unc_sbo3_support, &intel_bdx_unc_ha0_support, &intel_bdx_unc_ha1_support, &intel_bdx_unc_imc0_support, &intel_bdx_unc_imc1_support, &intel_bdx_unc_imc2_support, &intel_bdx_unc_imc3_support, &intel_bdx_unc_imc4_support, &intel_bdx_unc_imc5_support, &intel_bdx_unc_imc6_support, &intel_bdx_unc_imc7_support, &intel_bdx_unc_irp_support, &intel_bdx_unc_pcu_support, &intel_bdx_unc_qpi0_support, &intel_bdx_unc_qpi1_support, &intel_bdx_unc_qpi2_support, &intel_bdx_unc_r2pcie_support, &intel_bdx_unc_r3qpi0_support, &intel_bdx_unc_r3qpi1_support, &intel_bdx_unc_r3qpi2_support, &intel_x86_arch_support, /* must always be last for x86 */ #endif #ifdef CONFIG_PFMLIB_ARCH_MIPS &mips_74k_support, #endif #ifdef CONFIG_PFMLIB_ARCH_SICORTEX &sicortex_support, #endif #ifdef CONFIG_PFMLIB_ARCH_POWERPC &power4_support, &ppc970_support, &ppc970mp_support, &power5_support, &power5p_support, &power6_support, &power7_support, &power8_support, &power9_support, &torrent_support, &powerpc_nest_mcs_read_support, &powerpc_nest_mcs_write_support, #endif #ifdef CONFIG_PFMLIB_ARCH_SPARC &sparc_ultra12_support, &sparc_ultra3_support, &sparc_ultra3i_support, &sparc_ultra3plus_support, &sparc_ultra4plus_support, &sparc_niagara1_support, &sparc_niagara2_support, #endif #ifdef CONFIG_PFMLIB_CELL &cell_support, #endif #ifdef CONFIG_PFMLIB_ARCH_ARM &arm_cortex_a7_support, &arm_cortex_a8_support, &arm_cortex_a9_support, &arm_cortex_a15_support, &arm_1176_support, &arm_qcom_krait_support, &arm_cortex_a57_support, &arm_cortex_a53_support, &arm_xgene_support, #endif #ifdef CONFIG_PFMLIB_ARCH_ARM64 &arm_cortex_a57_support, &arm_cortex_a53_support, &arm_xgene_support, #endif #ifdef CONFIG_PFMLIB_ARCH_S390X &s390x_cpum_cf_support, &s390x_cpum_sf_support, #endif #ifdef __linux__ &perf_event_support, &perf_event_raw_support, #endif }; #define PFMLIB_NUM_PMUS (int)(sizeof(pfmlib_pmus)/sizeof(pfmlib_pmu_t *)) static pfmlib_os_t pfmlib_os_none; pfmlib_os_t *pfmlib_os = &pfmlib_os_none; static pfmlib_os_t *pfmlib_oses[]={ &pfmlib_os_none, #ifdef __linux__ &pfmlib_os_perf, &pfmlib_os_perf_ext, #endif }; #define PFMLIB_NUM_OSES (int)(sizeof(pfmlib_oses)/sizeof(pfmlib_os_t *)) /* * Mapping table from PMU index to pfmlib_pmu_t * table is populated from pfmlib_pmus[] when the library * is initialized. * * Some entries can be NULL if PMU is not implemented on host * architecture or if the initialization failed. */ static pfmlib_pmu_t *pfmlib_pmus_map[PFM_PMU_MAX]; #define pfmlib_for_each_pmu_event(p, e) \ for(e=(p)->get_event_first((p)); e != -1; e = (p)->get_event_next((p), e)) #define for_each_pmu_event_attr(u, i) \ for((u)=0; (u) < (i)->nattrs; (u) = (u)+1) #define pfmlib_for_each_pmu(x) \ for((x)= 0 ; (x) < PFMLIB_NUM_PMUS; (x)++) #define pfmlib_for_each_pmu(x) \ for((x)= 0 ; (x) < PFMLIB_NUM_PMUS; (x)++) #define pfmlib_for_each_os(x) \ for((x)= 0 ; (x) < PFMLIB_NUM_OSES; (x)++) pfmlib_config_t pfm_cfg; void __pfm_dbprintf(const char *fmt, ...) { va_list ap; if (pfm_cfg.debug == 0) return; va_start(ap, fmt); vfprintf(pfm_cfg.fp, fmt, ap); va_end(ap); } void __pfm_vbprintf(const char *fmt, ...) { va_list ap; if (pfm_cfg.verbose == 0) return; va_start(ap, fmt); vfprintf(pfm_cfg.fp, fmt, ap); va_end(ap); } /* * pfmlib_getl: our own equivalent to GNU getline() extension. * This avoids a dependency on having a C library with * support for getline(). */ int pfmlib_getl(char **buffer, size_t *len, FILE *fp) { #define GETL_DFL_LEN 32 char *b; int c; size_t maxsz, maxi, d, i = 0; if (!len || !fp || !buffer || (*buffer && *len < 2)) return -1; b = *buffer; if (!b) *len = 0; maxsz = *len; maxi = maxsz - 2; while ((c = fgetc(fp)) != EOF) { if (maxsz == 0 || i == maxi) { if (maxsz == 0) maxsz = GETL_DFL_LEN; else maxsz <<= 1; if (*buffer) d = &b[i] - *buffer; else d = 0; *buffer = realloc(*buffer, maxsz); if (!*buffer) return -1; b = *buffer + d; maxi = maxsz - d - 2; i = 0; *len = maxsz; } b[i++] = c; if (c == '\n') break; } b[i] = '\0'; return c != EOF ? 0 : -1; } /* * append fmt+args to str such that the string is no * more than max characters incl. null termination */ void pfmlib_strconcat(char *str, size_t max, const char *fmt, ...) { va_list ap; size_t len, todo; len = strlen(str); todo = max - strlen(str); va_start(ap, fmt); vsnprintf(str+len, todo, fmt, ap); va_end(ap); } /* * compact all pattrs starting from index i */ void pfmlib_compact_pattrs(pfmlib_event_desc_t *e, int i) { int j; for (j = i+1; j < e->npattrs; j++) e->pattrs[j - 1] = e->pattrs[j]; e->npattrs--; } static void pfmlib_compact_attrs(pfmlib_event_desc_t *e, int i) { int j; for (j = i+1; j < e->nattrs; j++) e->attrs[j - 1] = e->attrs[j]; e->nattrs--; } /* * 0 : different attribute * 1 : exactly same attribute (duplicate can be removed) * -1 : same attribute but value differ, this is an error */ static inline int pfmlib_same_attr(pfmlib_event_desc_t *d, int i, int j) { pfmlib_event_attr_info_t *a1, *a2; pfmlib_attr_t *b1, *b2; a1 = attr(d, i); a2 = attr(d, j); b1 = d->attrs+i; b2 = d->attrs+j; if (a1->idx == a2->idx && a1->type == a2->type && a1->ctrl == a2->ctrl) { if (b1->ival == b2->ival) return 1; return -1; } return 0; } static inline int pfmlib_pmu_active(pfmlib_pmu_t *pmu) { return !!(pmu->flags & PFMLIB_PMU_FL_ACTIVE); } static inline int pfmlib_pmu_initialized(pfmlib_pmu_t *pmu) { return !!(pmu->flags & PFMLIB_PMU_FL_INIT); } static inline pfm_pmu_t idx2pmu(int idx) { return (pfm_pmu_t)(idx >> PFMLIB_PMU_SHIFT) & PFMLIB_PMU_MASK; } static inline pfmlib_pmu_t * pmu2pmuidx(pfm_pmu_t pmu) { /* pfm_pmu_t is unsigned int enum, so * just need to check for upper bound */ if (pmu >= PFM_PMU_MAX) return NULL; return pfmlib_pmus_map[pmu]; } /* * external opaque idx -> PMU + internal idx */ static pfmlib_pmu_t * pfmlib_idx2pidx(int idx, int *pidx) { pfmlib_pmu_t *pmu; pfm_pmu_t pmu_id; if (PFMLIB_INITIALIZED() == 0) return NULL; if (idx < 0) return NULL; pmu_id = idx2pmu(idx); pmu = pmu2pmuidx(pmu_id); if (!pmu) return NULL; *pidx = idx & PFMLIB_PMU_PIDX_MASK; if (!pmu->event_is_valid(pmu, *pidx)) return NULL; return pmu; } static pfmlib_os_t * pfmlib_find_os(pfm_os_t id) { int o; pfmlib_os_t *os; pfmlib_for_each_os(o) { os = pfmlib_oses[o]; if (os->id == id && (os->flags & PFMLIB_OS_FL_ACTIVATED)) return os; } return NULL; } size_t pfmlib_check_struct(void *st, size_t usz, size_t refsz, size_t sz) { size_t rsz = sz; /* * if user size is zero, then use ABI0 size */ if (usz == 0) usz = refsz; /* * cannot be smaller than ABI0 size */ if (usz < refsz) { DPRINT("pfmlib_check_struct: user size too small %zu\n", usz); return 0; } /* * if bigger than current ABI, then check that none * of the extra bits are set. This is to avoid mistake * by caller assuming the library set those bits. */ if (usz > sz) { char *addr = (char *)st + sz; char *end = (char *)st + usz; while (addr != end) { if (*addr++) { DPRINT("pfmlib_check_struct: invalid extra bits\n"); return 0; } } } return rsz; } /* * check environment variables for: * LIBPFM_VERBOSE : enable verbose output (must be 1) * LIBPFM_DEBUG : enable debug output (must be 1) */ static void pfmlib_init_env(void) { char *str; pfm_cfg.fp = stderr; str = getenv("LIBPFM_VERBOSE"); if (str && isdigit((int)*str)) pfm_cfg.verbose = *str - '0'; str = getenv("LIBPFM_DEBUG"); if (str && isdigit((int)*str)) pfm_cfg.debug = *str - '0'; str = getenv("LIBPFM_DEBUG_STDOUT"); if (str) pfm_cfg.fp = stdout; pfm_cfg.forced_pmu = getenv("LIBPFM_FORCE_PMU"); str = getenv("LIBPFM_ENCODE_INACTIVE"); if (str) pfm_cfg.inactive = 1; str = getenv("LIBPFM_DISABLED_PMUS"); if (str) pfm_cfg.blacklist_pmus = str; } static int pfmlib_pmu_sanity_checks(pfmlib_pmu_t *p) { /* * check event can be encoded */ if (p->pme_count >= (1<< PFMLIB_PMU_SHIFT)) { DPRINT("too many events for %s\n", p->desc); return PFM_ERR_NOTSUPP; } if (p->max_encoding > PFMLIB_MAX_ENCODING) { DPRINT("max encoding too high (%d > %d) for %s\n", p->max_encoding, PFMLIB_MAX_ENCODING, p->desc); return PFM_ERR_NOTSUPP; } return PFM_SUCCESS; } int pfmlib_build_fstr(pfmlib_event_desc_t *e, char **fstr) { /* nothing to do */ if (!fstr) return PFM_SUCCESS; *fstr = malloc(strlen(e->fstr) + 2 + strlen(e->pmu->name) + 1); if (*fstr) sprintf(*fstr, "%s::%s", e->pmu->name, e->fstr); return *fstr ? PFM_SUCCESS : PFM_ERR_NOMEM; } static int pfmlib_pmu_activate(pfmlib_pmu_t *p) { int ret; if (p->pmu_init) { ret = p->pmu_init(p); if (ret != PFM_SUCCESS) return ret; } p->flags |= PFMLIB_PMU_FL_ACTIVE; DPRINT("activated %s\n", p->desc); return PFM_SUCCESS; } static inline int pfmlib_match_forced_pmu(const char *name) { const char *p; size_t l; /* skip any lower level specifier */ p = strchr(pfm_cfg.forced_pmu, ','); if (p) l = p - pfm_cfg.forced_pmu; else l = strlen(pfm_cfg.forced_pmu); return !strncasecmp(name, pfm_cfg.forced_pmu, l); } static int pfmlib_is_blacklisted_pmu(pfmlib_pmu_t *p) { char *q, *buffer; int ret = 1; if (!pfm_cfg.blacklist_pmus) return 0; /* * scan list for matching PMU names, we accept substrings. * for instance: snbep does match snbep* */ buffer = strdup(pfm_cfg.blacklist_pmus); if (!buffer) return 0; strcpy (buffer, pfm_cfg.blacklist_pmus); for (q = strtok (buffer, ","); q != NULL; q = strtok (NULL, ",")) { if (strstr (p->name, q) != NULL) { goto done; } } ret = 0; done: free(buffer); return ret; } static int pfmlib_init_pmus(void) { pfmlib_pmu_t *p; int i, ret; int nsuccess = 0; /* * activate all detected PMUs * when forced, only the designated PMU * is setup and activated */ pfmlib_for_each_pmu(i) { p = pfmlib_pmus[i]; DPRINT("trying %s\n", p->desc); ret = PFM_SUCCESS; if (!pfm_cfg.forced_pmu) ret = p->pmu_detect(p); else if (!pfmlib_match_forced_pmu(p->name)) ret = PFM_ERR_NOTSUPP; /* * basic checks * failure causes PMU to not be available */ if (pfmlib_pmu_sanity_checks(p) != PFM_SUCCESS) continue; if (pfmlib_is_blacklisted_pmu(p)) { DPRINT("%d PMU blacklisted, skipping initialization\n"); continue; } p->flags |= PFMLIB_PMU_FL_INIT; /* * populate mapping table */ pfmlib_pmus_map[p->pmu] = p; if (ret != PFM_SUCCESS) continue; /* * check if exported by OS if needed */ if (p->os_detect[pfmlib_os->id]) { ret = p->os_detect[pfmlib_os->id](p); if (ret != PFM_SUCCESS) { DPRINT("%s PMU not exported by OS\n", p->name); continue; } } ret = pfmlib_pmu_activate(p); if (ret == PFM_SUCCESS) nsuccess++; if (pfm_cfg.forced_pmu) { __pfm_vbprintf("PMU forced to %s (%s) : %s\n", p->name, p->desc, ret == PFM_SUCCESS ? "success" : "failure"); return ret; } } DPRINT("%d PMU detected out of %d supported\n", nsuccess, PFMLIB_NUM_PMUS); return PFM_SUCCESS; } static void pfmlib_init_os(void) { int o; pfmlib_os_t *os; pfmlib_for_each_os(o) { os = pfmlib_oses[o]; if (!os->detect) continue; if (os->detect(os) != PFM_SUCCESS) continue; if (os != &pfmlib_os_none && pfmlib_os == &pfmlib_os_none) pfmlib_os = os; DPRINT("OS layer %s activated\n", os->name); os->flags = PFMLIB_OS_FL_ACTIVATED; } DPRINT("default OS layer: %s\n", pfmlib_os->name); } int pfm_initialize(void) { int ret; /* * not atomic * if initialization already done, then reurn previous return value */ if (pfm_cfg.initdone) return pfm_cfg.initret; /* * generic sanity checks */ if (PFM_PMU_MAX & (~PFMLIB_PMU_MASK)) { DPRINT("PFM_PMU_MAX exceeds PFMLIB_PMU_MASK\n"); ret = PFM_ERR_NOTSUPP; } else { pfmlib_init_env(); /* must be done before pfmlib_init_pmus() */ pfmlib_init_os(); ret = pfmlib_init_pmus(); } pfm_cfg.initdone = 1; pfm_cfg.initret = ret; return ret; } void pfm_terminate(void) { pfmlib_pmu_t *pmu; int i; if (PFMLIB_INITIALIZED() == 0) return; pfmlib_for_each_pmu(i) { pmu = pfmlib_pmus[i]; if (!pfmlib_pmu_active(pmu)) continue; if (pmu->pmu_terminate) pmu->pmu_terminate(pmu); } pfm_cfg.initdone = 0; } int pfm_find_event(const char *str) { pfmlib_event_desc_t e; int ret; if (PFMLIB_INITIALIZED() == 0) return PFM_ERR_NOINIT; if (!str) return PFM_ERR_INVAL; memset(&e, 0, sizeof(e)); ret = pfmlib_parse_event(str, &e); if (ret == PFM_SUCCESS) { /* * save index so we can return it * and free the pattrs data that was * allocated in pfmlib_parse_event() */ ret = pfmlib_pidx2idx(e.pmu, e.event); pfmlib_release_event(&e); } return ret; } static int pfmlib_sanitize_event(pfmlib_event_desc_t *d) { int i, j, ret; /* * fail if duplicate attributes are found */ for(i=0; i < d->nattrs; i++) { for(j=i+1; j < d->nattrs; j++) { ret = pfmlib_same_attr(d, i, j); if (ret == 1) pfmlib_compact_attrs(d, j); else if (ret == -1) return PFM_ERR_ATTR_SET; } } return PFM_SUCCESS; } static int pfmlib_parse_event_attr(char *str, pfmlib_event_desc_t *d) { pfmlib_event_attr_info_t *ainfo; char *s, *p, *q, *endptr; char yes[2] = "y"; pfm_attr_t type; int aidx = 0, has_val, has_raw_um = 0, has_um = 0; int ret = PFM_ERR_INVAL; s = str; while(s) { p = s; strsep(&p, PFMLIB_ATTR_DELIM); /* if (p) *p++ = '\0'; */ q = strchr(s, '='); if (q) *q++ = '\0'; has_val = !!q; /* * check for raw umasks in hexdecimal only */ if (*s == '0' && tolower(*(s+1)) == 'x') { char *endptr = NULL; /* can only have one raw umask */ if (has_raw_um || has_um) { DPRINT("cannot mix raw umask with umask\n"); return PFM_ERR_ATTR; } if (!(d->pmu->flags & PFMLIB_PMU_FL_RAW_UMASK)) { DPRINT("PMU %s does not support RAW umasks\n", d->pmu->name); return PFM_ERR_ATTR; } /* we have reserved an entry at the end of pattrs */ aidx = d->npattrs; ainfo = d->pattrs + aidx; ainfo->name = "RAW_UMASK"; ainfo->type = PFM_ATTR_RAW_UMASK; ainfo->ctrl = PFM_ATTR_CTRL_PMU; /* can handle up to 64-bit raw umask */ ainfo->idx = strtoull(s, &endptr, 0); ainfo->equiv= NULL; if (*endptr) { DPRINT("raw umask (%s) is not a number\n"); return PFM_ERR_ATTR; } has_raw_um = 1; goto found_attr; } for(aidx = 0; aidx < d->npattrs; aidx++) { if (!strcasecmp(d->pattrs[aidx].name, s)) { ainfo = d->pattrs + aidx; /* disambiguate modifier and umask * with the same name : snb::L2_LINES_IN:I:I=1 */ if (has_val && ainfo->type == PFM_ATTR_UMASK) continue; goto found_attr; } } DPRINT("cannot find attribute %s\n", s); return PFM_ERR_ATTR; found_attr: type = ainfo->type; if (type == PFM_ATTR_UMASK) { has_um = 1; if (has_raw_um) { DPRINT("cannot mix raw umask with umask\n"); return PFM_ERR_ATTR; } } if (ainfo->equiv) { char *z; /* cannot have equiv for attributes with value */ if (has_val) return PFM_ERR_ATTR_VAL; /* copy because it is const */ z = strdup(ainfo->equiv); if (!z) return PFM_ERR_NOMEM; ret = pfmlib_parse_event_attr(z, d); free(z); if (ret != PFM_SUCCESS) return ret; s = p; continue; } /* * we tolerate missing value for boolean attributes. * Presence of the attribute is equivalent to * attr=1, i.e., attribute is set */ if (type != PFM_ATTR_UMASK && type != PFM_ATTR_RAW_UMASK && !has_val) { if (type != PFM_ATTR_MOD_BOOL) return PFM_ERR_ATTR_VAL; s = yes; /* no const */ goto handle_bool; } d->attrs[d->nattrs].ival = 0; if ((type == PFM_ATTR_UMASK || type == PFM_ATTR_RAW_UMASK) && has_val) return PFM_ERR_ATTR_VAL; if (has_val) { s = q; handle_bool: ret = PFM_ERR_ATTR_VAL; if (!strlen(s)) goto error; if (d->nattrs == PFMLIB_MAX_ATTRS) { DPRINT("too many attributes\n"); ret = PFM_ERR_TOOMANY; goto error; } endptr = NULL; switch(type) { case PFM_ATTR_MOD_BOOL: if (strlen(s) > 1) goto error; if (tolower((int)*s) == 'y' || tolower((int)*s) == 't' || *s == '1') d->attrs[d->nattrs].ival = 1; else if (tolower((int)*s) == 'n' || tolower((int)*s) == 'f' || *s == '0') d->attrs[d->nattrs].ival = 0; else goto error; break; case PFM_ATTR_MOD_INTEGER: d->attrs[d->nattrs].ival = strtoull(s, &endptr, 0); if (*endptr != '\0') goto error; break; default: goto error; } } d->attrs[d->nattrs].id = aidx; d->nattrs++; s = p; } ret = PFM_SUCCESS; error: return ret; } static int pfmlib_build_event_pattrs(pfmlib_event_desc_t *e) { pfmlib_pmu_t *pmu; pfmlib_os_t *os; int i, ret, pmu_nattrs = 0, os_nattrs = 0; int npattrs; /* * cannot satisfy request for an OS that was not activated */ os = pfmlib_find_os(e->osid); if (!os) return PFM_ERR_NOTSUPP; pmu = e->pmu; /* get actual PMU number of attributes for the event */ if (pmu->get_event_nattrs) pmu_nattrs = pmu->get_event_nattrs(pmu, e->event); if (os && os->get_os_nattrs) os_nattrs += os->get_os_nattrs(os, e); npattrs = pmu_nattrs + os_nattrs; /* * add extra entry for raw umask, if supported */ if (pmu->flags & PFMLIB_PMU_FL_RAW_UMASK) npattrs++; if (npattrs) { e->pattrs = malloc(npattrs * sizeof(*e->pattrs)); if (!e->pattrs) return PFM_ERR_NOMEM; } /* collect all actual PMU attrs */ for(i = 0; i < pmu_nattrs; i++) { ret = pmu->get_event_attr_info(pmu, e->event, i, e->pattrs+i); if (ret != PFM_SUCCESS) goto error; } e->npattrs = pmu_nattrs; if (os_nattrs) { if (e->osid == os->id && os->get_os_attr_info) { os->get_os_attr_info(os, e); /* * check for conflicts between HW and OS attributes */ if (pmu->validate_pattrs[e->osid]) pmu->validate_pattrs[e->osid](pmu, e); } } for (i = 0; i < e->npattrs; i++) DPRINT("%d %d %d %d %d %s\n", e->event, i, e->pattrs[i].type, e->pattrs[i].ctrl, e->pattrs[i].idx, e->pattrs[i].name); return PFM_SUCCESS; error: free(e->pattrs); e->pattrs = NULL; return ret; } void pfmlib_release_event(pfmlib_event_desc_t *e) { free(e->pattrs); e->pattrs = NULL; } static int match_event(void *this, pfmlib_event_desc_t *d, const char *e, const char *s) { return strcasecmp(e, s); } static int pfmlib_parse_equiv_event(const char *event, pfmlib_event_desc_t *d) { pfmlib_pmu_t *pmu = d->pmu; pfm_event_info_t einfo; int (*match)(void *this, pfmlib_event_desc_t *d, const char *e, const char *s); char *str, *s, *p; int i; int ret; /* * create copy because string is const */ s = str = strdup(event); if (!str) return PFM_ERR_NOMEM; p = s; strsep(&p, PFMLIB_ATTR_DELIM); /* if (p) *p++ = '\0'; */ match = pmu->match_event ? pmu->match_event : match_event; pfmlib_for_each_pmu_event(pmu, i) { ret = pmu->get_event_info(pmu, i, &einfo); if (ret != PFM_SUCCESS) goto error; if (!match(pmu, d, einfo.name, s)) goto found; } free(str); return PFM_ERR_NOTFOUND; found: d->pmu = pmu; d->event = i; /* private index */ /* * build_event_pattrs and parse_event_attr * cannot be factorized with pfmlib_parse_event() * because equivalent event may add its own attributes */ ret = pfmlib_build_event_pattrs(d); if (ret != PFM_SUCCESS) goto error; ret = pfmlib_parse_event_attr(p, d); if (ret == PFM_SUCCESS) ret = pfmlib_sanitize_event(d); error: free(str); if (ret != PFM_SUCCESS) pfmlib_release_event(d); return ret; } int pfmlib_parse_event(const char *event, pfmlib_event_desc_t *d) { pfm_event_info_t einfo; char *str, *s, *p; pfmlib_pmu_t *pmu; int (*match)(void *this, pfmlib_event_desc_t *d, const char *e, const char *s); const char *pname = NULL; int i, j, ret; /* * support only one event at a time. */ p = strpbrk(event, PFMLIB_EVENT_DELIM); if (p) return PFM_ERR_INVAL; /* * create copy because string is const */ s = str = strdup(event); if (!str) return PFM_ERR_NOMEM; /* check for optional PMU name */ p = strstr(s, PFMLIB_PMU_DELIM); if (p) { *p = '\0'; pname = s; s = p + strlen(PFMLIB_PMU_DELIM); } p = s; strsep(&p, PFMLIB_ATTR_DELIM); /* if (p) *p++ = '\0'; */ /* * for each pmu */ pfmlib_for_each_pmu(j) { pmu = pfmlib_pmus[j]; /* * if no explicit PMU name is given, then * only look for active PMU models */ if (!pname && !pfmlib_pmu_active(pmu)) continue; /* * check for requested PMU name, */ if (pname && strcasecmp(pname, pmu->name)) continue; /* * only allow event on inactive PMU if enabled via * environement variable */ if (pname && !pfmlib_pmu_active(pmu) && !pfm_cfg.inactive) continue; match = pmu->match_event ? pmu->match_event : match_event; /* * for each event */ pfmlib_for_each_pmu_event(pmu, i) { ret = pmu->get_event_info(pmu, i, &einfo); if (ret != PFM_SUCCESS) goto error; if (!match(pmu, d, einfo.name, s)) goto found; } } free(str); return PFM_ERR_NOTFOUND; found: d->pmu = pmu; /* * handle equivalence */ if (einfo.equiv) { ret = pfmlib_parse_equiv_event(einfo.equiv, d); if (ret != PFM_SUCCESS) goto error; } else { d->event = i; /* private index */ ret = pfmlib_build_event_pattrs(d); if (ret != PFM_SUCCESS) goto error; } /* * parse attributes from original event */ ret = pfmlib_parse_event_attr(p, d); if (ret == PFM_SUCCESS) ret = pfmlib_sanitize_event(d); for (i = 0; i < d->nattrs; i++) { pfmlib_event_attr_info_t *a = attr(d, i); if (a->type != PFM_ATTR_RAW_UMASK) DPRINT("%d %d %d %s\n", d->event, i, a->idx, d->pattrs[d->attrs[i].id].name); else DPRINT("%d %d RAW_UMASK (0x%x)\n", d->event, i, a->idx); } error: free(str); if (ret != PFM_SUCCESS) pfmlib_release_event(d); return ret; } /* sorry, only English supported at this point! */ static const char *pfmlib_err_list[]= { "success", "not supported", "invalid parameters", "pfmlib not initialized", "event not found", "invalid combination of model specific features", "invalid or missing unit mask", "out of memory", "invalid event attribute", "invalid event attribute value", "attribute value already set", "too many parameters", "parameter is too small", }; static int pfmlib_err_count = (int)sizeof(pfmlib_err_list)/sizeof(char *); const char * pfm_strerror(int code) { code = -code; if (code <0 || code >= pfmlib_err_count) return "unknown error code"; return pfmlib_err_list[code]; } int pfm_get_version(void) { return LIBPFM_VERSION; } int pfm_get_event_next(int idx) { pfmlib_pmu_t *pmu; int pidx; pmu = pfmlib_idx2pidx(idx, &pidx); if (!pmu) return -1; pidx = pmu->get_event_next(pmu, pidx); return pidx == -1 ? -1 : pfmlib_pidx2idx(pmu, pidx); } int pfm_get_os_event_encoding(const char *str, int dfl_plm, pfm_os_t uos, void *args) { pfmlib_os_t *os; if (PFMLIB_INITIALIZED() == 0) return PFM_ERR_NOINIT; if (!(args && str)) return PFM_ERR_INVAL; if (dfl_plm & ~(PFM_PLM_ALL)) return PFM_ERR_INVAL; os = pfmlib_find_os(uos); if (!os) return PFM_ERR_NOTSUPP; return os->encode(os, str, dfl_plm, args); } /* * old API maintained for backward compatibility with existing apps * prefer pfm_get_os_event_encoding() */ int pfm_get_event_encoding(const char *str, int dfl_plm, char **fstr, int *idx, uint64_t **codes, int *count) { pfm_pmu_encode_arg_t arg; int ret; if (!(str && codes && count)) return PFM_ERR_INVAL; if ((*codes && !*count) || (!*codes && *count)) return PFM_ERR_INVAL; memset(&arg, 0, sizeof(arg)); arg.fstr = fstr; arg.codes = *codes; arg.count = *count; arg.size = sizeof(arg); /* * request RAW PMU encoding */ ret = pfm_get_os_event_encoding(str, dfl_plm, PFM_OS_NONE, &arg); if (ret != PFM_SUCCESS) return ret; /* handle the case where the array was allocated */ *codes = arg.codes; *count = arg.count; if (idx) *idx = arg.idx; return PFM_SUCCESS; } static int pfmlib_check_event_pattrs(pfmlib_pmu_t *pmu, int pidx, pfm_os_t osid, FILE *fp) { pfmlib_event_desc_t e; int i, j, ret; memset(&e, 0, sizeof(e)); e.event = pidx; e.osid = osid; e.pmu = pmu; ret = pfmlib_build_event_pattrs(&e); if (ret != PFM_SUCCESS) { fprintf(fp, "invalid pattrs for event %d\n", pidx); return ret; } ret = PFM_ERR_ATTR; for (i = 0; i < e.npattrs; i++) { for (j = i+1; j < e.npattrs; j++) { if (!strcmp(e.pattrs[i].name, e.pattrs[j].name)) { fprintf(fp, "event %d duplicate pattrs %s\n", pidx, e.pattrs[i].name); goto error; } } } ret = PFM_SUCCESS; error: /* * release resources allocated for event */ pfmlib_release_event(&e); return ret; } static int pfmlib_validate_encoding(char *buf, int plm) { uint64_t *codes = NULL; int count = 0, ret; ret = pfm_get_event_encoding(buf, plm, NULL, NULL, &codes, &count); if (ret != PFM_SUCCESS) { int i; DPRINT("%s ", buf); for(i=0; i < count; i++) __pfm_dbprintf(" %#"PRIx64, codes[i]); __pfm_dbprintf("\n"); } if (codes) free(codes); return ret; } static int pfmlib_pmu_validate_encoding(pfmlib_pmu_t *pmu, FILE *fp) { pfm_event_info_t einfo; pfmlib_event_attr_info_t ainfo; char *buf; size_t maxlen = 0, len; int i, u, n = 0, um; int ret, retval = PFM_SUCCESS; pfmlib_for_each_pmu_event(pmu, i) { ret = pmu->get_event_info(pmu, i, &einfo); if (ret != PFM_SUCCESS) return ret; ret = pfmlib_check_event_pattrs(pmu, i, PFM_OS_NONE, fp); if (ret != PFM_SUCCESS) return ret; len = strlen(einfo.name); if (len > maxlen) maxlen = len; for_each_pmu_event_attr(u, &einfo) { ret = pmu->get_event_attr_info(pmu, i, u, &ainfo); if (ret != PFM_SUCCESS) return ret; if (ainfo.type != PFM_ATTR_UMASK) continue; len = strlen(einfo.name) + strlen(ainfo.name); if (len > maxlen) maxlen = len; } } /* 2 = ::, 1=:, 1=eol */ maxlen += strlen(pmu->name) + 2 + 1 + 1; buf = malloc(maxlen); if (!buf) return PFM_ERR_NOMEM; pfmlib_for_each_pmu_event(pmu, i) { ret = pmu->get_event_info(pmu, i, &einfo); if (ret != PFM_SUCCESS) { retval = ret; continue; } um = 0; for_each_pmu_event_attr(u, &einfo) { ret = pmu->get_event_attr_info(pmu, i, u, &ainfo); if (ret != PFM_SUCCESS) { retval = ret; continue; } if (ainfo.type != PFM_ATTR_UMASK) continue; /* * XXX: some events may require more than one umasks to encode */ sprintf(buf, "%s::%s:%s", pmu->name, einfo.name, ainfo.name); ret = pfmlib_validate_encoding(buf, PFM_PLM3|PFM_PLM0); if (ret != PFM_SUCCESS) { if (pmu->can_auto_encode) { if (!pmu->can_auto_encode(pmu, i, u)) continue; } /* * some PMU may not support raw encoding */ if (ret != PFM_ERR_NOTSUPP) { fprintf(fp, "cannot encode event %s : %s\n", buf, pfm_strerror(ret)); retval = ret; } continue; } um++; } if (um == 0) { sprintf(buf, "%s::%s", pmu->name, einfo.name); ret = pfmlib_validate_encoding(buf, PFM_PLM3|PFM_PLM0); if (ret != PFM_SUCCESS) { if (pmu->can_auto_encode) { if (!pmu->can_auto_encode(pmu, i, u)) continue; } if (ret != PFM_ERR_NOTSUPP) { fprintf(fp, "cannot encode event %s : %s\n", buf, pfm_strerror(ret)); retval = ret; } continue; } } n++; } free(buf); return retval; } int pfm_pmu_validate(pfm_pmu_t pmu_id, FILE *fp) { pfmlib_pmu_t *pmu, *pmx; int nos = 0; int i, ret; if (fp == NULL) return PFM_ERR_INVAL; pmu = pmu2pmuidx(pmu_id); if (!pmu) return PFM_ERR_INVAL; if (!pfmlib_pmu_initialized(pmu)) { fprintf(fp, "pmu: %s :: initialization failed\n", pmu->name); return PFM_ERR_INVAL; } if (!pmu->name) { fprintf(fp, "pmu id: %d :: no name\n", pmu->pmu); return PFM_ERR_INVAL; } if (!pmu->desc) { fprintf(fp, "pmu: %s :: no description\n", pmu->name); return PFM_ERR_INVAL; } if (pmu->pmu >= PFM_PMU_MAX) { fprintf(fp, "pmu: %s :: invalid PMU id\n", pmu->name); return PFM_ERR_INVAL; } if (pmu->max_encoding >= PFMLIB_MAX_ENCODING) { fprintf(fp, "pmu: %s :: max encoding too high\n", pmu->name); return PFM_ERR_INVAL; } if (pfmlib_pmu_active(pmu) && !pmu->pme_count) { fprintf(fp, "pmu: %s :: no events\n", pmu->name); return PFM_ERR_INVAL; } if (!pmu->pmu_detect) { fprintf(fp, "pmu: %s :: missing pmu_detect callback\n", pmu->name); return PFM_ERR_INVAL; } if (!pmu->get_event_first) { fprintf(fp, "pmu: %s :: missing get_event_first callback\n", pmu->name); return PFM_ERR_INVAL; } if (!pmu->get_event_next) { fprintf(fp, "pmu: %s :: missing get_event_next callback\n", pmu->name); return PFM_ERR_INVAL; } if (!pmu->get_event_info) { fprintf(fp, "pmu: %s :: missing get_event_info callback\n", pmu->name); return PFM_ERR_INVAL; } if (!pmu->get_event_attr_info) { fprintf(fp, "pmu: %s :: missing get_event_attr_info callback\n", pmu->name); return PFM_ERR_INVAL; } for (i = PFM_OS_NONE; i < PFM_OS_MAX; i++) { if (pmu->get_event_encoding[i]) nos++; } if (!nos) { fprintf(fp, "pmu: %s :: no os event encoding callback\n", pmu->name); return PFM_ERR_INVAL; } if (!pmu->max_encoding) { fprintf(fp, "pmu: %s :: max_encoding is zero\n", pmu->name); return PFM_ERR_INVAL; } /* look for duplicate names, id */ pfmlib_for_each_pmu(i) { pmx = pfmlib_pmus[i]; if (!pfmlib_pmu_active(pmx)) continue; if (pmx == pmu) continue; if (!strcasecmp(pmx->name, pmu->name)) { fprintf(fp, "pmu: %s :: duplicate name\n", pmu->name); return PFM_ERR_INVAL; } if (pmx->pmu == pmu->pmu) { fprintf(fp, "pmu: %s :: duplicate id\n", pmu->name); return PFM_ERR_INVAL; } } if (pmu->validate_table) { ret = pmu->validate_table(pmu, fp); if (ret != PFM_SUCCESS) return ret; } return pfmlib_pmu_validate_encoding(pmu, fp); } int pfm_get_event_info(int idx, pfm_os_t os, pfm_event_info_t *uinfo) { pfm_event_info_t info; pfmlib_event_desc_t e; pfmlib_pmu_t *pmu; size_t sz = sizeof(info); int pidx, ret; if (!PFMLIB_INITIALIZED()) return PFM_ERR_NOINIT; if (os >= PFM_OS_MAX) return PFM_ERR_INVAL; pmu = pfmlib_idx2pidx(idx, &pidx); if (!pmu) return PFM_ERR_INVAL; if (!uinfo) return PFM_ERR_INVAL; sz = pfmlib_check_struct(uinfo, uinfo->size, PFM_EVENT_INFO_ABI0, sz); if (!sz) return PFM_ERR_INVAL; memset(&info, 0, sizeof(info)); info.size = sz; /* default data type is uint64 */ info.dtype = PFM_DTYPE_UINT64; /* reset flags */ info.is_precise = 0; ret = pmu->get_event_info(pmu, pidx, &info); if (ret != PFM_SUCCESS) return ret; info.pmu = pmu->pmu; info.idx = idx; memset(&e, 0, sizeof(e)); e.event = pidx; e.osid = os; e.pmu = pmu; ret = pfmlib_build_event_pattrs(&e); if (ret == PFM_SUCCESS) { info.nattrs = e.npattrs; memcpy(uinfo, &info, sz); } pfmlib_release_event(&e); return ret; } int pfm_get_event_attr_info(int idx, int attr_idx, pfm_os_t os, pfm_event_attr_info_t *uinfo) { pfmlib_event_attr_info_t info; pfmlib_event_desc_t e; pfmlib_pmu_t *pmu; size_t sz = sizeof(info); int pidx, ret; if (!PFMLIB_INITIALIZED()) return PFM_ERR_NOINIT; if (attr_idx < 0) return PFM_ERR_INVAL; if (os >= PFM_OS_MAX) return PFM_ERR_INVAL; pmu = pfmlib_idx2pidx(idx, &pidx); if (!pmu) return PFM_ERR_INVAL; if (!uinfo) return PFM_ERR_INVAL; sz = pfmlib_check_struct(uinfo, uinfo->size, PFM_ATTR_INFO_ABI0, sz); if (!sz) return PFM_ERR_INVAL; memset(&e, 0, sizeof(e)); e.event = pidx; e.osid = os; e.pmu = pmu; ret = pfmlib_build_event_pattrs(&e); if (ret != PFM_SUCCESS) return ret; ret = PFM_ERR_INVAL; if (attr_idx >= e.npattrs) goto error; /* * copy event_attr_info */ info = e.pattrs[attr_idx]; /* * info.idx = private, namespace specific index, * should not be visible externally, so override * with public index * * cannot memcpy() info into uinfo as they do not * have the same size, cf. idx field (uint64 vs, uint32) */ uinfo->name = info.name; uinfo->desc = info.desc; uinfo->equiv = info.equiv; uinfo->size = sz; uinfo->code = info.code; uinfo->type = info.type; uinfo->idx = attr_idx; uinfo->ctrl = info.ctrl; uinfo->is_dfl= info.is_dfl; uinfo->is_precise = info.is_precise; uinfo->reserved_bits = 0; uinfo->dfl_val64 = info.dfl_val64; ret = PFM_SUCCESS; error: pfmlib_release_event(&e); return ret; } int pfm_get_pmu_info(pfm_pmu_t pmuid, pfm_pmu_info_t *uinfo) { pfm_pmu_info_t info; pfmlib_pmu_t *pmu; size_t sz = sizeof(info); int pidx; if (!PFMLIB_INITIALIZED()) return PFM_ERR_NOINIT; if (pmuid >= PFM_PMU_MAX) return PFM_ERR_INVAL; if (!uinfo) return PFM_ERR_INVAL; sz = pfmlib_check_struct(uinfo, uinfo->size, PFM_PMU_INFO_ABI0, sz); if (!sz) return PFM_ERR_INVAL; pmu = pfmlib_pmus_map[pmuid]; if (!pmu) return PFM_ERR_NOTSUPP; info.name = pmu->name; info.desc = pmu->desc; info.pmu = pmuid; info.size = sz; info.max_encoding = pmu->max_encoding; info.num_cntrs = pmu->num_cntrs; info.num_fixed_cntrs = pmu->num_fixed_cntrs; pidx = pmu->get_event_first(pmu); if (pidx == -1) info.first_event = -1; else info.first_event = pfmlib_pidx2idx(pmu, pidx); /* * XXX: pme_count only valid when PMU is detected */ info.is_present = pfmlib_pmu_active(pmu); info.is_dfl = !!(pmu->flags & PFMLIB_PMU_FL_ARCH_DFL); info.type = pmu->type; if (pmu->get_num_events) info.nevents = pmu->get_num_events(pmu); else info.nevents = pmu->pme_count; memcpy(uinfo, &info, sz); return PFM_SUCCESS; } pfmlib_pmu_t * pfmlib_get_pmu_by_type(pfm_pmu_type_t t) { pfmlib_pmu_t *pmu; int i; pfmlib_for_each_pmu(i) { pmu = pfmlib_pmus[i]; if (!pfmlib_pmu_active(pmu)) continue; /* first match */ if (pmu->type != t) continue; return pmu; } return NULL; } static int pfmlib_compare_attr_id(const void *a, const void *b) { const pfmlib_attr_t *t1 = a; const pfmlib_attr_t *t2 = b; if (t1->id < t2->id) return -1; return t1->id == t2->id ? 0 : 1; } void pfmlib_sort_attr(pfmlib_event_desc_t *e) { qsort(e->attrs, e->nattrs, sizeof(pfmlib_attr_t), pfmlib_compare_attr_id); } static int pfmlib_raw_pmu_encode(void *this, const char *str, int dfl_plm, void *data) { pfm_pmu_encode_arg_t arg; pfm_pmu_encode_arg_t *uarg = data; pfmlib_pmu_t *pmu; pfmlib_event_desc_t e; size_t sz = sizeof(arg); int ret, i; sz = pfmlib_check_struct(uarg, uarg->size, PFM_RAW_ENCODE_ABI0, sz); if (!sz) return PFM_ERR_INVAL; memset(&arg, 0, sizeof(arg)); /* * get input data */ memcpy(&arg, uarg, sz); memset(&e, 0, sizeof(e)); e.osid = PFM_OS_NONE; e.dfl_plm = dfl_plm; ret = pfmlib_parse_event(str, &e); if (ret != PFM_SUCCESS) return ret; pmu = e.pmu; if (!pmu->get_event_encoding[PFM_OS_NONE]) { DPRINT("PMU %s does not support PFM_OS_NONE\n", pmu->name); ret = PFM_ERR_NOTSUPP; goto error; } ret = pmu->get_event_encoding[PFM_OS_NONE](pmu, &e); if (ret != PFM_SUCCESS) goto error; /* * return opaque event identifier */ arg.idx = pfmlib_pidx2idx(e.pmu, e.event); if (arg.codes == NULL) { ret = PFM_ERR_NOMEM; arg.codes = malloc(sizeof(uint64_t) * e.count); if (!arg.codes) goto error_fstr; } else if (arg.count < e.count) { ret = PFM_ERR_TOOSMALL; goto error_fstr; } arg.count = e.count; for (i = 0; i < e.count; i++) arg.codes[i] = e.codes[i]; if (arg.fstr) { ret = pfmlib_build_fstr(&e, arg.fstr); if (ret != PFM_SUCCESS) goto error; } ret = PFM_SUCCESS; /* copy out results */ memcpy(uarg, &arg, sz); error_fstr: if (ret != PFM_SUCCESS) free(arg.fstr); error: /* * release resources allocated for event */ pfmlib_release_event(&e); return ret; } static int pfmlib_raw_pmu_detect(void *this) { return PFM_SUCCESS; } static pfmlib_os_t pfmlib_os_none= { .name = "No OS (raw PMU)", .id = PFM_OS_NONE, .flags = PFMLIB_OS_FL_ACTIVATED, .encode = pfmlib_raw_pmu_encode, .detect = pfmlib_raw_pmu_detect, }; libpfm-4.9.0/lib/pfmlib_intel_x86_arch.c0000664000175000017500000001366513223402656017711 0ustar eranianeranian/* * pfmlib_intel_x86_arch.c : Intel architectural PMU v1, v2, v3 * * Copyright (c) 2005-2007 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * * This file implements supports for the IA-32 architectural PMU as specified * in the following document: * "IA-32 Intel Architecture Software Developer's Manual - Volume 3B: System * Programming Guide" */ #include #include #include #include #include /* private headers */ #include "pfmlib_priv.h" /* library private */ #include "pfmlib_intel_x86_priv.h" /* architecture private */ #include "events/intel_x86_arch_events.h" /* architected event table */ extern pfmlib_pmu_t intel_x86_arch_support; static intel_x86_entry_t *x86_arch_pe; /* * .byte 0x53 == push ebx. it's universal for 32 and 64 bit * .byte 0x5b == pop ebx. * Some gcc's (4.1.2 on Core2) object to pairing push/pop and ebx in 64 bit mode. * Using the opcode directly avoids this problem. */ static inline void cpuid(unsigned int op, unsigned int *a, unsigned int *b, unsigned int *c, unsigned int *d) { __asm__ __volatile__ (".byte 0x53\n\tcpuid\n\tmovl %%ebx, %%esi\n\t.byte 0x5b" : "=a" (*a), "=S" (*b), "=c" (*c), "=d" (*d) : "a" (op)); } /* * create architected event table */ static int create_arch_event_table(unsigned int mask, int version) { intel_x86_entry_t *pe; int i, num_events = 0; int m; DPRINT("version=%d evt_msk=0x%x\n", version, mask); /* * first pass: count the number of supported events */ m = mask; for(i=0; i < 7; i++, m>>=1) { if ((m & 0x1) == 0) num_events++; } intel_x86_arch_support.pme_count = num_events; pe = calloc(num_events, sizeof(intel_x86_entry_t)); if (pe == NULL) return PFM_ERR_NOTSUPP; x86_arch_pe = pe; intel_x86_arch_support.pe = pe; /* * second pass: populate the table */ m = mask; for(i=0; i < 7; i++, m>>=1) { if (!(m & 0x1)) { *pe = intel_x86_arch_pe[i]; switch(version) { case 3: pe->modmsk = INTEL_V3_ATTRS; break; default: pe->modmsk = INTEL_V2_ATTRS; break; } pe++; } } return PFM_SUCCESS; } static int check_arch_pmu(int family) { union { unsigned int val; intel_x86_pmu_eax_t eax; intel_x86_pmu_edx_t edx; } eax, ecx, edx, ebx; /* * check family number to reject for processors * older than Pentium (family=5). Those processors * did not have the CPUID instruction */ if (family < 5 || family == 15) return PFM_ERR_NOTSUPP; /* * check if CPU supports 0xa function of CPUID * 0xa started with Core Duo. Needed to detect if * architected PMU is present */ cpuid(0x0, &eax.val, &ebx.val, &ecx.val, &edx.val); if (eax.val < 0xa) return PFM_ERR_NOTSUPP; /* * extract architected PMU information */ cpuid(0xa, &eax.val, &ebx.val, &ecx.val, &edx.val); /* * version must be greater than zero */ return eax.eax.version < 1 ? PFM_ERR_NOTSUPP : PFM_SUCCESS; } static int pfm_intel_x86_arch_detect(void *this) { int ret; ret = pfm_intel_x86_detect(); if (ret != PFM_SUCCESS) return ret; return check_arch_pmu(pfm_intel_x86_cfg.family); } static int pfm_intel_x86_arch_init(void *this) { union { unsigned int val; intel_x86_pmu_eax_t eax; intel_x86_pmu_edx_t edx; } eax, ecx, edx, ebx; /* * extract architected PMU information */ if (!pfm_cfg.forced_pmu) { cpuid(0xa, &eax.val, &ebx.val, &ecx.val, &edx.val); intel_x86_arch_support.num_cntrs = eax.eax.num_cnt; intel_x86_arch_support.num_fixed_cntrs = edx.edx.num_cnt; } else { eax.eax.version = 3; ebx.val = 0; /* no restriction */ intel_x86_arch_support.num_cntrs = 0; intel_x86_arch_support.num_fixed_cntrs = 0; } /* * must be called after impl_cntrs has been initialized */ return create_arch_event_table(ebx.val, eax.eax.version); } void pfm_intel_x86_arch_terminate(void *this) { /* workaround const void for intel_x86_arch_support.pe */ if (x86_arch_pe) free(x86_arch_pe); } /* architected PMU */ pfmlib_pmu_t intel_x86_arch_support={ .desc = "Intel X86 architectural PMU", .name = "ix86arch", .pmu = PFM_PMU_INTEL_X86_ARCH, .pme_count = 0, .pe = NULL, .atdesc = intel_x86_mods, .flags = PFMLIB_PMU_FL_RAW_UMASK | PFMLIB_PMU_FL_ARCH_DFL, .type = PFM_PMU_TYPE_CORE, .max_encoding = 1, .pmu_detect = pfm_intel_x86_arch_detect, .pmu_init = pfm_intel_x86_arch_init, .pmu_terminate = pfm_intel_x86_arch_terminate, .get_event_encoding[PFM_OS_NONE] = pfm_intel_x86_get_encoding, PFMLIB_ENCODE_PERF(pfm_intel_x86_get_perf_encoding), .get_event_first = pfm_intel_x86_get_event_first, .get_event_next = pfm_intel_x86_get_event_next, .event_is_valid = pfm_intel_x86_event_is_valid, .get_event_info = pfm_intel_x86_get_event_info, .get_event_attr_info = pfm_intel_x86_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_intel_x86_perf_validate_pattrs), .get_event_nattrs = pfm_intel_x86_get_event_nattrs, }; libpfm-4.9.0/lib/pfmlib_power9.c0000664000175000017500000000441413223402656016311 0ustar eranianeranian/* * pfmlib_power9.c : IBM Power9 support * * Copyright (C) IBM Corporation, 2017. All rights reserved. * Contributed by Will Schmidt (will_schmidt@vnet.ibm.com) * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_power_priv.h" #include "events/power9_events.h" static int pfm_power9_detect(void* this) { if (__is_processor(PV_POWER9)) return PFM_SUCCESS; return PFM_ERR_NOTSUPP; } pfmlib_pmu_t power9_support={ .desc = "POWER9", .name = "power9", .pmu = PFM_PMU_POWER9, .pme_count = LIBPFM_ARRAY_SIZE(power9_pe), .type = PFM_PMU_TYPE_CORE, .supported_plm = POWER9_PLM, .num_cntrs = 4, .num_fixed_cntrs = 2, .max_encoding = 1, .pe = power9_pe, .pmu_detect = pfm_power9_detect, .get_event_encoding[PFM_OS_NONE] = pfm_gen_powerpc_get_encoding, PFMLIB_ENCODE_PERF(pfm_gen_powerpc_get_perf_encoding), PFMLIB_VALID_PERF_PATTRS(pfm_gen_powerpc_perf_validate_pattrs), .get_event_first = pfm_gen_powerpc_get_event_first, .get_event_next = pfm_gen_powerpc_get_event_next, .event_is_valid = pfm_gen_powerpc_event_is_valid, .validate_table = pfm_gen_powerpc_validate_table, .get_event_info = pfm_gen_powerpc_get_event_info, .get_event_attr_info = pfm_gen_powerpc_get_event_attr_info, }; libpfm-4.9.0/lib/pfmlib_intel_atom.c0000664000175000017500000000572413223402656017224 0ustar eranianeranian/* * pfmlib_intel_atom.c : Intel Atom PMU * * Copyright (c) 2008 Google, Inc * Contributed by Stephane Eranian * * Based on work: * Copyright (c) 2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * * This file implements support for Intel Core PMU as specified in the following document: * "IA-32 Intel Architecture Software Developer's Manual - Volume 3B: System * Programming Guide" * * Intel Atom = architectural v3 + PEBS */ /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_intel_x86_priv.h" #include "events/intel_atom_events.h" static const int atom_models[] = { 28, /* Pineview/Silverthorne */ 38, /* Lincroft */ 39, /* Penwell */ 53, /* Cloverview */ 54, /* Cedarview */ 0 }; static int pfm_intel_atom_init(void *this) { pfm_intel_x86_cfg.arch_version = 3; return PFM_SUCCESS; } pfmlib_pmu_t intel_atom_support={ .desc = "Intel Atom", .name = "atom", .pmu = PFM_PMU_INTEL_ATOM, .pme_count = LIBPFM_ARRAY_SIZE(intel_atom_pe), .type = PFM_PMU_TYPE_CORE, .num_cntrs = 2, .num_fixed_cntrs = 3, .max_encoding = 1, .pe = intel_atom_pe, .atdesc = intel_x86_mods, .flags = PFMLIB_PMU_FL_RAW_UMASK, .supported_plm = INTEL_X86_PLM, .cpu_family = 6, .cpu_models = atom_models, .pmu_detect = pfm_intel_x86_model_detect, .pmu_init = pfm_intel_atom_init, .get_event_encoding[PFM_OS_NONE] = pfm_intel_x86_get_encoding, PFMLIB_ENCODE_PERF(pfm_intel_x86_get_perf_encoding), .get_event_first = pfm_intel_x86_get_event_first, .get_event_next = pfm_intel_x86_get_event_next, .event_is_valid = pfm_intel_x86_event_is_valid, .validate_table = pfm_intel_x86_validate_table, .get_event_info = pfm_intel_x86_get_event_info, .get_event_attr_info = pfm_intel_x86_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_intel_x86_perf_validate_pattrs), .get_event_nattrs = pfm_intel_x86_get_event_nattrs, }; libpfm-4.9.0/lib/pfmlib_intel_ivbep_unc_irp.c0000664000175000017500000000575613223402656021115 0ustar eranianeranian/* * pfmlib_intel_ivbep_irp.c : Intel IvyBridge-EP IRP uncore PMU * * Copyright (c) 2014 Google Inc. All rights reserved * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_intel_x86_priv.h" #include "pfmlib_intel_snbep_unc_priv.h" #include "events/intel_ivbep_unc_irp_events.h" static void display_irp(void *this, pfmlib_event_desc_t *e, void *val) { const intel_x86_entry_t *pe = this_pe(this); pfm_snbep_unc_reg_t *reg = val; __pfm_vbprintf("[UNC_IRP=0x%"PRIx64" event=0x%x umask=0x%x en=%d " "edge=%d thres=%d] %s\n", reg->val, reg->irp.unc_event, reg->irp.unc_umask, reg->irp.unc_en, reg->irp.unc_edge, reg->irp.unc_thres, pe[e->event].name); } pfmlib_pmu_t intel_ivbep_unc_irp_support = { .desc = "Intel Ivy Bridge-EP IRP uncore", .name = "ivbep_unc_irp", .perf_name = "uncore_irp", .pmu = PFM_PMU_INTEL_IVBEP_UNC_IRP, .pme_count = LIBPFM_ARRAY_SIZE(intel_ivbep_unc_i_pe), .type = PFM_PMU_TYPE_UNCORE, .num_cntrs = 4, .num_fixed_cntrs = 0, .max_encoding = 3, .pe = intel_ivbep_unc_i_pe, .atdesc = snbep_unc_mods, .flags = PFMLIB_PMU_FL_RAW_UMASK, .pmu_detect = pfm_intel_ivbep_unc_detect, .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding, PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding), PFMLIB_OS_DETECT(pfm_intel_x86_perf_detect), .get_event_first = pfm_intel_x86_get_event_first, .get_event_next = pfm_intel_x86_get_event_next, .event_is_valid = pfm_intel_x86_event_is_valid, .validate_table = pfm_intel_x86_validate_table, .get_event_info = pfm_intel_x86_get_event_info, .get_event_attr_info = pfm_intel_x86_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs), .get_event_nattrs = pfm_intel_x86_get_event_nattrs, .display_reg = display_irp, }; libpfm-4.9.0/lib/pfmlib_power4.c0000664000175000017500000000436013223402656016304 0ustar eranianeranian/* * pfmlib_power4.c : IBM Power4 support * * Copyright (C) IBM Corporation, 2009. All rights reserved. * Contributed by Corey Ashford (cjashfor@us.ibm.com) * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_power_priv.h" #include "events/power4_events.h" static int pfm_power4_detect(void* this) { if (__is_processor(PV_POWER4) || __is_processor(PV_POWER4p)) return PFM_SUCCESS; return PFM_ERR_NOTSUPP; } pfmlib_pmu_t power4_support={ .desc = "POWER4", .name = "power4", .pmu = PFM_PMU_POWER4, .pme_count = LIBPFM_ARRAY_SIZE(power4_pe), .type = PFM_PMU_TYPE_CORE, .num_cntrs = 8, .max_encoding = 1, .pe = power4_pe, .pmu_detect = pfm_power4_detect, .get_event_encoding[PFM_OS_NONE] = pfm_gen_powerpc_get_encoding, PFMLIB_ENCODE_PERF(pfm_gen_powerpc_get_perf_encoding), PFMLIB_VALID_PERF_PATTRS(pfm_gen_powerpc_perf_validate_pattrs), .get_event_first = pfm_gen_powerpc_get_event_first, .get_event_next = pfm_gen_powerpc_get_event_next, .event_is_valid = pfm_gen_powerpc_event_is_valid, .validate_table = pfm_gen_powerpc_validate_table, .get_event_info = pfm_gen_powerpc_get_event_info, .get_event_attr_info = pfm_gen_powerpc_get_event_attr_info, }; libpfm-4.9.0/lib/pfmlib_intel_snbep_unc_r3qpi.c0000664000175000017500000000523513223402656021353 0ustar eranianeranian/* * pfmlib_intel_snbep_r3qpi.c : Intel SandyBridge-EP R3QPI uncore PMU * * Copyright (c) 2012 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_intel_x86_priv.h" #include "pfmlib_intel_snbep_unc_priv.h" #include "events/intel_snbep_unc_r3qpi_events.h" #define DEFINE_R3QPI_BOX(n) \ pfmlib_pmu_t intel_snbep_unc_r3qpi##n##_support = {\ .desc = "Intel Sandy Bridge-EP R3QPI"#n" uncore", \ .name = "snbep_unc_r3qpi"#n,\ .perf_name = "uncore_r3qpi_"#n, \ .pmu = PFM_PMU_INTEL_SNBEP_UNC_R3QPI##n, \ .pme_count = LIBPFM_ARRAY_SIZE(intel_snbep_unc_r3_pe),\ .type = PFM_PMU_TYPE_UNCORE,\ .num_cntrs = 3,\ .num_fixed_cntrs = 0,\ .max_encoding = 1,\ .pe = intel_snbep_unc_r3_pe,\ .atdesc = snbep_unc_mods,\ .flags = PFMLIB_PMU_FL_RAW_UMASK\ | PFMLIB_PMU_FL_NO_SMPL,\ .pmu_detect = pfm_intel_snbep_unc_detect,\ .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding,\ PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding),\ .get_event_first = pfm_intel_x86_get_event_first,\ .get_event_next = pfm_intel_x86_get_event_next,\ .event_is_valid = pfm_intel_x86_event_is_valid,\ .validate_table = pfm_intel_x86_validate_table,\ .get_event_info = pfm_intel_x86_get_event_info,\ .get_event_attr_info = pfm_intel_x86_get_event_attr_info,\ PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs),\ .get_event_nattrs = pfm_intel_x86_get_event_nattrs,\ } DEFINE_R3QPI_BOX(0); DEFINE_R3QPI_BOX(1); libpfm-4.9.0/lib/pfmlib_itanium2.c0000664000175000017500000017343013223402656016621 0ustar eranianeranian/* * pfmlib_itanium2.c : support for the Itanium2 PMU family * * Copyright (c) 2002-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include /* public headers */ #include /* private headers */ #include "pfmlib_priv.h" /* library private */ #include "pfmlib_priv_ia64.h" /* architecture private */ #include "pfmlib_itanium2_priv.h" /* PMU private */ #include "itanium2_events.h" /* PMU private */ #define is_ear(i) event_is_ear(itanium2_pe+(i)) #define is_ear_tlb(i) event_is_ear_tlb(itanium2_pe+(i)) #define is_ear_alat(i) event_is_ear_alat(itanium2_pe+(i)) #define is_ear_cache(i) event_is_ear_cache(itanium2_pe+(i)) #define is_iear(i) event_is_iear(itanium2_pe+(i)) #define is_dear(i) event_is_dear(itanium2_pe+(i)) #define is_btb(i) event_is_btb(itanium2_pe+(i)) #define has_opcm(i) event_opcm_ok(itanium2_pe+(i)) #define has_iarr(i) event_iarr_ok(itanium2_pe+(i)) #define has_darr(i) event_darr_ok(itanium2_pe+(i)) #define evt_use_opcm(e) ((e)->pfp_ita2_pmc8.opcm_used != 0 || (e)->pfp_ita2_pmc9.opcm_used !=0) #define evt_use_irange(e) ((e)->pfp_ita2_irange.rr_used) #define evt_use_drange(e) ((e)->pfp_ita2_drange.rr_used) #define evt_grp(e) (int)itanium2_pe[e].pme_qualifiers.pme_qual.pme_group #define evt_set(e) (int)itanium2_pe[e].pme_qualifiers.pme_qual.pme_set #define evt_umask(e) itanium2_pe[e].pme_umask #define FINE_MODE_BOUNDARY_BITS 12 #define FINE_MODE_MASK ~((1U<<12)-1) /* let's define some handy shortcuts! */ #define pmc_plm pmc_ita2_counter_reg.pmc_plm #define pmc_ev pmc_ita2_counter_reg.pmc_ev #define pmc_oi pmc_ita2_counter_reg.pmc_oi #define pmc_pm pmc_ita2_counter_reg.pmc_pm #define pmc_es pmc_ita2_counter_reg.pmc_es #define pmc_umask pmc_ita2_counter_reg.pmc_umask #define pmc_thres pmc_ita2_counter_reg.pmc_thres #define pmc_ism pmc_ita2_counter_reg.pmc_ism static char * pfm_ita2_get_event_name(unsigned int i); /* * Description of the PMC register mappings use by * this module (as reported in pfmlib_reg_t.reg_num): * * 0 -> PMC0 * 1 -> PMC1 * n -> PMCn * * The following are in the model specific rr_br[]: * IBR0 -> 0 * IBR1 -> 1 * ... * IBR7 -> 7 * DBR0 -> 0 * DBR1 -> 1 * ... * DBR7 -> 7 * * We do not use a mapping table, instead we make up the * values on the fly given the base. */ /* * The Itanium2 PMU has a bug in the fine mode implementation. * It only sees ranges with a granularity of two bundles. * So we prepare for the day they fix it. */ static int has_fine_mode_bug; static int pfm_ita2_detect(void) { int tmp; int ret = PFMLIB_ERR_NOTSUPP; tmp = pfm_ia64_get_cpu_family(); if (tmp == 0x1f) { has_fine_mode_bug = 1; ret = PFMLIB_SUCCESS; } return ret; } /* * Check the event for incompatibilities. This is useful * for L1 and L2 related events. Due to wire limitations, * some caches events are separated into sets. There * are 5 sets for the L1D cache group and 6 sets for L2 group. * It is NOT possible to simultaneously measure events from * differents sets within a group. For instance, you cannot * measure events from set0 and set1 in L1D cache group. However * it is possible to measure set0 in L1D and set1 in L2 at the same * time. * * This function verifies that the set constraint are respected. */ static int check_cross_groups_and_umasks(pfmlib_input_param_t *inp) { unsigned long ref_umask, umask; int g, s; unsigned int cnt = inp->pfp_event_count; pfmlib_event_t *e = inp->pfp_events; unsigned int i, j; /* * XXX: could possibly be optimized */ for (i=0; i < cnt; i++) { g = evt_grp(e[i].event); s = evt_set(e[i].event); if (g == PFMLIB_ITA2_EVT_NO_GRP) continue; ref_umask = evt_umask(e[i].event); for (j=i+1; j < cnt; j++) { if (evt_grp(e[j].event) != g) continue; if (evt_set(e[j].event) != s) return PFMLIB_ERR_EVTSET; /* only care about L2 cache group */ if (g != PFMLIB_ITA2_EVT_L2_CACHE_GRP || (s == 1 || s == 2)) continue; umask = evt_umask(e[j].event); /* * there is no assignement possible if the event in PMC4 * has a umask (ref_umask) and an event (from the same * set) also has a umask AND it is different. For some * sets, the umasks are shared, therefore the value * programmed into PMC4 determines the umask for all * the other events (with umask) from the set. */ if (umask && ref_umask != umask) return PFMLIB_ERR_NOASSIGN; } } return PFMLIB_SUCCESS; } /* * Certain prefetch events must be treated specially when instruction range restriction * is in use because they can only be constrained by IBRP1 in fine-mode. Other events * will use IBRP0 if tagged as a demand fetch OR IBPR1 if tagged as a prefetch match. * From the library's point of view there is no way of distinguishing this, so we leave * it up to the user to interpret the results. * * Events which can be qualified by the two pairs depending on their tag: * - IBP_BUNPAIRS_IN * - L1I_FETCH_RAB_HIT * - L1I_FETCH_ISB_HIT * - L1I_FILLS * * This function returns the number of qualifying prefetch events found * * XXX: not clear which events do qualify as prefetch events. */ static int prefetch_events[]={ PME_ITA2_L1I_PREFETCHES, PME_ITA2_L1I_STRM_PREFETCHES, PME_ITA2_L2_INST_PREFETCHES }; #define NPREFETCH_EVENTS sizeof(prefetch_events)/sizeof(int) static int check_prefetch_events(pfmlib_input_param_t *inp) { int code; int prefetch_codes[NPREFETCH_EVENTS]; unsigned int i, j, count; int c; int found = 0; for(i=0; i < NPREFETCH_EVENTS; i++) { pfm_get_event_code(prefetch_events[i], &code); prefetch_codes[i] = code; } count = inp->pfp_event_count; for(i=0; i < count; i++) { pfm_get_event_code(inp->pfp_events[i].event, &c); for(j=0; j < NPREFETCH_EVENTS; j++) { if (c == prefetch_codes[j]) found++; } } return found; } /* * IA64_INST_RETIRED (and subevents) is the only event which can be measured on all * 4 IBR when non-fine mode is not possible. * * This function returns: * - the number of events matching the IA64_INST_RETIRED code * - in retired_mask the bottom 4 bits indicates which of the 4 INST_RETIRED event * is present */ static unsigned int check_inst_retired_events(pfmlib_input_param_t *inp, unsigned long *retired_mask) { int code; int c; unsigned int i, count, found = 0; unsigned long umask, mask; pfm_get_event_code(PME_ITA2_IA64_INST_RETIRED_THIS, &code); count = inp->pfp_event_count; mask = 0; for(i=0; i < count; i++) { pfm_get_event_code(inp->pfp_events[i].event, &c); if (c == code) { pfm_ita2_get_event_umask(inp->pfp_events[i].event, &umask); switch(umask) { case 0: mask |= 1; break; case 1: mask |= 2; break; case 2: mask |= 4; break; case 3: mask |= 8; break; } found++; } } if (retired_mask) *retired_mask = mask; return found; } static int check_fine_mode_possible(pfmlib_ita2_input_rr_t *rr, int n) { pfmlib_ita2_input_rr_desc_t *lim = rr->rr_limits; int i; for(i=0; i < n; i++) { if ((lim[i].rr_start & FINE_MODE_MASK) != (lim[i].rr_end & FINE_MODE_MASK)) return 0; } return 1; } /* * mode = 0 -> check code (enforce bundle alignment) * mode = 1 -> check data */ static int check_intervals(pfmlib_ita2_input_rr_t *irr, int mode, unsigned int *n_intervals) { unsigned int i; pfmlib_ita2_input_rr_desc_t *lim = irr->rr_limits; for(i=0; i < 4; i++) { /* end marker */ if (lim[i].rr_start == 0 && lim[i].rr_end == 0) break; /* invalid entry */ if (lim[i].rr_start >= lim[i].rr_end) return PFMLIB_ERR_IRRINVAL; if (mode == 0 && (lim[i].rr_start & 0xf || lim[i].rr_end & 0xf)) return PFMLIB_ERR_IRRALIGN; } *n_intervals = i; return PFMLIB_SUCCESS; } static int valid_assign(pfmlib_event_t *e, unsigned int *as, pfmlib_regmask_t *r_pmcs, unsigned int cnt) { unsigned long pmc4_umask = 0, umask; char *name; int l1_grp_present = 0, l2_grp_present = 0; unsigned int i; int c, failure; int need_pmc5, need_pmc4; int pmc5_evt = -1, pmc4_evt = -1; if (PFMLIB_DEBUG()) { unsigned int j; for(j=0;jpfp_event_count; for(i=0; i < count; i++) { for (j=0; j < NCANCEL_EVENTS; j++) { pfm_get_event_code(inp->pfp_events[i].event, &code); if (code == cancel_codes[j]) { if (idx != -1) { return PFMLIB_ERR_INVAL; } idx = inp->pfp_events[i].event; } } } return PFMLIB_SUCCESS; } /* * Automatically dispatch events to corresponding counters following constraints. * Upon return the pfarg_regt structure is ready to be submitted to kernel */ static int pfm_ita2_dispatch_counters(pfmlib_input_param_t *inp, pfmlib_ita2_input_param_t *mod_in, pfmlib_output_param_t *outp) { #define has_counter(e,b) (itanium2_pe[e].pme_counters & (1 << (b)) ? (b) : 0) pfmlib_ita2_input_param_t *param = mod_in; pfm_ita2_pmc_reg_t reg; pfmlib_event_t *e; pfmlib_reg_t *pc, *pd; pfmlib_regmask_t *r_pmcs; unsigned int i,j,k,l; int ret; unsigned int max_l0, max_l1, max_l2, max_l3; unsigned int assign[PMU_ITA2_NUM_COUNTERS]; unsigned int m, cnt; e = inp->pfp_events; pc = outp->pfp_pmcs; pd = outp->pfp_pmds; cnt = inp->pfp_event_count; r_pmcs = &inp->pfp_unavail_pmcs; if (PFMLIB_DEBUG()) for (m=0; m < cnt; m++) { DPRINT("ev[%d]=%s counters=0x%lx\n", m, itanium2_pe[e[m].event].pme_name, itanium2_pe[e[m].event].pme_counters); } if (cnt > PMU_ITA2_NUM_COUNTERS) return PFMLIB_ERR_TOOMANY; ret = check_cross_groups_and_umasks(inp); if (ret != PFMLIB_SUCCESS) return ret; ret = check_cancel_events(inp); if (ret != PFMLIB_SUCCESS) return ret; max_l0 = PMU_ITA2_FIRST_COUNTER + PMU_ITA2_NUM_COUNTERS; max_l1 = PMU_ITA2_FIRST_COUNTER + PMU_ITA2_NUM_COUNTERS*(cnt>1); max_l2 = PMU_ITA2_FIRST_COUNTER + PMU_ITA2_NUM_COUNTERS*(cnt>2); max_l3 = PMU_ITA2_FIRST_COUNTER + PMU_ITA2_NUM_COUNTERS*(cnt>3); DPRINT("max_l0=%u max_l1=%u max_l2=%u max_l3=%u\n", max_l0, max_l1, max_l2, max_l3); /* * For now, worst case in the loop nest: 4! (factorial) */ for (i=PMU_ITA2_FIRST_COUNTER; i < max_l0; i++) { assign[0] = has_counter(e[0].event,i); if (max_l1 == PMU_ITA2_FIRST_COUNTER && valid_assign(e, assign, r_pmcs, cnt) == PFMLIB_SUCCESS) goto done; for (j=PMU_ITA2_FIRST_COUNTER; j < max_l1; j++) { if (j == i) continue; assign[1] = has_counter(e[1].event,j); if (max_l2 == PMU_ITA2_FIRST_COUNTER && valid_assign(e, assign, r_pmcs, cnt) == PFMLIB_SUCCESS) goto done; for (k=PMU_ITA2_FIRST_COUNTER; k < max_l2; k++) { if(k == i || k == j) continue; assign[2] = has_counter(e[2].event,k); if (max_l3 == PMU_ITA2_FIRST_COUNTER && valid_assign(e, assign, r_pmcs, cnt) == PFMLIB_SUCCESS) goto done; for (l=PMU_ITA2_FIRST_COUNTER; l < max_l3; l++) { if(l == i || l == j || l == k) continue; assign[3] = has_counter(e[3].event,l); if (valid_assign(e, assign, r_pmcs, cnt) == PFMLIB_SUCCESS) goto done; } } } } /* we cannot satisfy the constraints */ return PFMLIB_ERR_NOASSIGN; done: for (j=0; j < cnt ; j++ ) { reg.pmc_val = 0; /* clear all, bits 26-27 must be zero for proper operations */ /* if plm is 0, then assume not specified per-event and use default */ reg.pmc_plm = inp->pfp_events[j].plm ? inp->pfp_events[j].plm : inp->pfp_dfl_plm; reg.pmc_oi = 1; /* overflow interrupt */ reg.pmc_pm = inp->pfp_flags & PFMLIB_PFP_SYSTEMWIDE ? 1 : 0; reg.pmc_thres = param ? param->pfp_ita2_counters[j].thres: 0; reg.pmc_ism = param ? param->pfp_ita2_counters[j].ism : PFMLIB_ITA2_ISM_BOTH; reg.pmc_umask = is_ear(e[j].event) ? 0x0 : itanium2_pe[e[j].event].pme_umask; reg.pmc_es = itanium2_pe[e[j].event].pme_code; /* * Note that we don't force PMC4.pmc_ena = 1 because the kernel takes care of this for us. * This way we don't have to program something in PMC4 even when we don't use it */ pc[j].reg_num = assign[j]; pc[j].reg_value = reg.pmc_val; pc[j].reg_addr = pc[j].reg_alt_addr = assign[j]; pd[j].reg_num = assign[j]; pd[j].reg_addr = pd[j].reg_addr = assign[j]; __pfm_vbprintf("[PMC%u(pmc%u)=0x%06lx thres=%d es=0x%02x plm=%d umask=0x%x pm=%d ism=0x%x oi=%d] %s\n", assign[j], assign[j], reg.pmc_val, reg.pmc_thres, reg.pmc_es,reg.pmc_plm, reg.pmc_umask, reg.pmc_pm, reg.pmc_ism, reg.pmc_oi, itanium2_pe[e[j].event].pme_name); __pfm_vbprintf("[PMD%u(pmd%u)]\n", pd[j].reg_num, pd[j].reg_num); } /* number of PMC registers programmed */ outp->pfp_pmc_count = cnt; outp->pfp_pmd_count = cnt; return PFMLIB_SUCCESS; } static int pfm_dispatch_iear(pfmlib_input_param_t *inp, pfmlib_ita2_input_param_t *mod_in, pfmlib_output_param_t *outp) { pfm_ita2_pmc_reg_t reg; pfmlib_ita2_input_param_t *param = mod_in; pfmlib_reg_t *pc, *pd; pfmlib_ita2_input_param_t fake_param; unsigned int pos1, pos2; unsigned int i, count; pc = outp->pfp_pmcs; pd = outp->pfp_pmds; pos1 = outp->pfp_pmc_count; pos2 = outp->pfp_pmd_count; count = inp->pfp_event_count; for (i=0; i < count; i++) { if (is_iear(inp->pfp_events[i].event)) break; } if (param == NULL || param->pfp_ita2_iear.ear_used == 0) { /* * case 3: no I-EAR event, no (or nothing) in param->pfp_ita2_iear.ear_used */ if (i == count) return PFMLIB_SUCCESS; memset(&fake_param, 0, sizeof(fake_param)); param = &fake_param; /* * case 1: extract all information for event (name) */ pfm_ita2_get_ear_mode(inp->pfp_events[i].event, ¶m->pfp_ita2_iear.ear_mode); param->pfp_ita2_iear.ear_umask = evt_umask(inp->pfp_events[i].event); param->pfp_ita2_iear.ear_ism = PFMLIB_ITA2_ISM_BOTH; /* force both instruction sets */ DPRINT("I-EAR event with no info\n"); } /* * case 2: ear_used=1, event is defined, we use the param info as it is more precise * case 4: ear_used=1, no event (free running I-EAR), use param info */ reg.pmc_val = 0; if (param->pfp_ita2_iear.ear_mode == PFMLIB_ITA2_EAR_TLB_MODE) { /* if plm is 0, then assume not specified per-event and use default */ reg.pmc10_ita2_tlb_reg.iear_plm = param->pfp_ita2_iear.ear_plm ? param->pfp_ita2_iear.ear_plm : inp->pfp_dfl_plm; reg.pmc10_ita2_tlb_reg.iear_pm = inp->pfp_flags & PFMLIB_PFP_SYSTEMWIDE ? 1 : 0; reg.pmc10_ita2_tlb_reg.iear_ct = 0x0; reg.pmc10_ita2_tlb_reg.iear_umask = param->pfp_ita2_iear.ear_umask; reg.pmc10_ita2_tlb_reg.iear_ism = param->pfp_ita2_iear.ear_ism; } else if (param->pfp_ita2_iear.ear_mode == PFMLIB_ITA2_EAR_CACHE_MODE) { /* if plm is 0, then assume not specified per-event and use default */ reg.pmc10_ita2_cache_reg.iear_plm = param->pfp_ita2_iear.ear_plm ? param->pfp_ita2_iear.ear_plm : inp->pfp_dfl_plm; reg.pmc10_ita2_cache_reg.iear_pm = inp->pfp_flags & PFMLIB_PFP_SYSTEMWIDE ? 1 : 0; reg.pmc10_ita2_cache_reg.iear_ct = 0x1; reg.pmc10_ita2_cache_reg.iear_umask = param->pfp_ita2_iear.ear_umask; reg.pmc10_ita2_cache_reg.iear_ism = param->pfp_ita2_iear.ear_ism; } else { DPRINT("ALAT mode not supported in I-EAR mode\n"); return PFMLIB_ERR_INVAL; } if (pfm_regmask_isset(&inp->pfp_unavail_pmcs, 10)) return PFMLIB_ERR_NOASSIGN; pc[pos1].reg_num = 10; /* PMC10 is I-EAR config register */ pc[pos1].reg_value = reg.pmc_val; pc[pos1].reg_addr = pc[pos1].reg_alt_addr = 10; pos1++; pd[pos2].reg_num = 0; pd[pos2].reg_addr = pd[pos2].reg_alt_addr= 0; pos2++; pd[pos2].reg_num = 1; pd[pos2].reg_addr = pd[pos2].reg_alt_addr = 1; pos2++; if (param->pfp_ita2_iear.ear_mode == PFMLIB_ITA2_EAR_TLB_MODE) { __pfm_vbprintf("[PMC10(pmc10)=0x%lx ctb=tlb plm=%d pm=%d ism=0x%x umask=0x%x]\n", reg.pmc_val, reg.pmc10_ita2_tlb_reg.iear_plm, reg.pmc10_ita2_tlb_reg.iear_pm, reg.pmc10_ita2_tlb_reg.iear_ism, reg.pmc10_ita2_tlb_reg.iear_umask); } else { __pfm_vbprintf("[PMC10(pmc10)=0x%lx ctb=cache plm=%d pm=%d ism=0x%x umask=0x%x]\n", reg.pmc_val, reg.pmc10_ita2_cache_reg.iear_plm, reg.pmc10_ita2_cache_reg.iear_pm, reg.pmc10_ita2_cache_reg.iear_ism, reg.pmc10_ita2_cache_reg.iear_umask); } __pfm_vbprintf("[PMD0(pmd0)]\n[PMD1(pmd1)\n"); /* update final number of entries used */ outp->pfp_pmc_count = pos1; outp->pfp_pmd_count = pos2; return PFMLIB_SUCCESS; } static int pfm_dispatch_dear(pfmlib_input_param_t *inp, pfmlib_ita2_input_param_t *mod_in, pfmlib_output_param_t *outp) { pfm_ita2_pmc_reg_t reg; pfmlib_ita2_input_param_t *param = mod_in; pfmlib_reg_t *pc, *pd; pfmlib_ita2_input_param_t fake_param; unsigned int pos1, pos2; unsigned int i, count; pc = outp->pfp_pmcs; pd = outp->pfp_pmds; pos1 = outp->pfp_pmc_count; pos2 = outp->pfp_pmd_count; count = inp->pfp_event_count; for (i=0; i < count; i++) { if (is_dear(inp->pfp_events[i].event)) break; } if (param == NULL || param->pfp_ita2_dear.ear_used == 0) { /* * case 3: no D-EAR event, no (or nothing) in param->pfp_ita2_dear.ear_used */ if (i == count) return PFMLIB_SUCCESS; memset(&fake_param, 0, sizeof(fake_param)); param = &fake_param; /* * case 1: extract all information for event (name) */ pfm_ita2_get_ear_mode(inp->pfp_events[i].event, ¶m->pfp_ita2_dear.ear_mode); param->pfp_ita2_dear.ear_umask = evt_umask(inp->pfp_events[i].event); param->pfp_ita2_dear.ear_ism = PFMLIB_ITA2_ISM_BOTH; /* force both instruction sets */ DPRINT("D-EAR event with no info\n"); } /* sanity check on the mode */ if ( param->pfp_ita2_dear.ear_mode != PFMLIB_ITA2_EAR_CACHE_MODE && param->pfp_ita2_dear.ear_mode != PFMLIB_ITA2_EAR_TLB_MODE && param->pfp_ita2_dear.ear_mode != PFMLIB_ITA2_EAR_ALAT_MODE) return PFMLIB_ERR_INVAL; /* * case 2: ear_used=1, event is defined, we use the param info as it is more precise * case 4: ear_used=1, no event (free running D-EAR), use param info */ reg.pmc_val = 0; /* if plm is 0, then assume not specified per-event and use default */ reg.pmc11_ita2_reg.dear_plm = param->pfp_ita2_dear.ear_plm ? param->pfp_ita2_dear.ear_plm : inp->pfp_dfl_plm; reg.pmc11_ita2_reg.dear_pm = inp->pfp_flags & PFMLIB_PFP_SYSTEMWIDE ? 1 : 0; reg.pmc11_ita2_reg.dear_mode = param->pfp_ita2_dear.ear_mode; reg.pmc11_ita2_reg.dear_umask = param->pfp_ita2_dear.ear_umask; reg.pmc11_ita2_reg.dear_ism = param->pfp_ita2_dear.ear_ism; if (pfm_regmask_isset(&inp->pfp_unavail_pmcs, 11)) return PFMLIB_ERR_NOASSIGN; pc[pos1].reg_num = 11; /* PMC11 is D-EAR config register */ pc[pos1].reg_value = reg.pmc_val; pc[pos1].reg_addr = pc[pos1].reg_alt_addr = 11; pos1++; pd[pos2].reg_num = 2; pd[pos2].reg_addr = pd[pos2].reg_alt_addr = 2; pos2++; pd[pos2].reg_num = 3; pd[pos2].reg_addr = pd[pos2].reg_alt_addr = 3; pos2++; pd[pos2].reg_num = 17; pd[pos2].reg_addr = pd[pos2].reg_alt_addr = 17; pos2++; __pfm_vbprintf("[PMC11(pmc11)=0x%lx mode=%s plm=%d pm=%d ism=0x%x umask=0x%x]\n", reg.pmc_val, reg.pmc11_ita2_reg.dear_mode == 0 ? "L1D" : (reg.pmc11_ita2_reg.dear_mode == 1 ? "L1DTLB" : "ALAT"), reg.pmc11_ita2_reg.dear_plm, reg.pmc11_ita2_reg.dear_pm, reg.pmc11_ita2_reg.dear_ism, reg.pmc11_ita2_reg.dear_umask); __pfm_vbprintf("[PMD2(pmd2)]\n[PMD3(pmd3)\nPMD17(pmd17)\n"); /* update final number of entries used */ outp->pfp_pmc_count = pos1; outp->pfp_pmd_count = pos2; return PFMLIB_SUCCESS; } static int pfm_dispatch_opcm(pfmlib_input_param_t *inp, pfmlib_ita2_input_param_t *mod_in, pfmlib_output_param_t *outp, pfmlib_ita2_output_param_t *mod_out) { pfmlib_ita2_input_param_t *param = mod_in; pfmlib_reg_t *pc = outp->pfp_pmcs; pfm_ita2_pmc_reg_t reg, pmc15; unsigned int i, has_1st_pair, has_2nd_pair, count; unsigned int pos = outp->pfp_pmc_count; if (param == NULL) return PFMLIB_SUCCESS; /* not constrained by PMC8 nor PMC9 */ pmc15.pmc_val = 0xffffffff; /* XXX: use PAL instead. PAL value is 0xfffffff0 */ if (param->pfp_ita2_irange.rr_used && mod_out == NULL) return PFMLIB_ERR_INVAL; if (param->pfp_ita2_pmc8.opcm_used || (param->pfp_ita2_irange.rr_used && mod_out->pfp_ita2_irange.rr_nbr_used!=0) ) { reg.pmc_val = param->pfp_ita2_pmc8.opcm_used ? param->pfp_ita2_pmc8.pmc_val : 0xffffffff3fffffff; if (param->pfp_ita2_irange.rr_used) { reg.pmc8_9_ita2_reg.opcm_ig_ad = 0; reg.pmc8_9_ita2_reg.opcm_inv = param->pfp_ita2_irange.rr_flags & PFMLIB_ITA2_RR_INV ? 1 : 0; } else { /* clear range restriction fields when none is used */ reg.pmc8_9_ita2_reg.opcm_ig_ad = 1; reg.pmc8_9_ita2_reg.opcm_inv = 0; } /* force bit 2 to 1 */ reg.pmc8_9_ita2_reg.opcm_bit2 = 1; if (pfm_regmask_isset(&inp->pfp_unavail_pmcs, 8)) return PFMLIB_ERR_NOASSIGN; pc[pos].reg_num = 8; pc[pos].reg_value = reg.pmc_val; pc[pos].reg_addr = pc[pos].reg_addr = 8; pos++; /* * will be constrained by PMC8 */ if (param->pfp_ita2_pmc8.opcm_used) { has_1st_pair = has_2nd_pair = 0; count = inp->pfp_event_count; for(i=0; i < count; i++) { if (inp->pfp_events[i].event == PME_ITA2_IA64_TAGGED_INST_RETIRED_IBRP0_PMC8) has_1st_pair=1; if (inp->pfp_events[i].event == PME_ITA2_IA64_TAGGED_INST_RETIRED_IBRP2_PMC8) has_2nd_pair=1; } if (has_1st_pair || has_2nd_pair == 0) pmc15.pmc15_ita2_reg.opcmc_ibrp0_pmc8 = 0; if (has_2nd_pair || has_1st_pair == 0) pmc15.pmc15_ita2_reg.opcmc_ibrp2_pmc8 = 0; } __pfm_vbprintf("[PMC8(pmc8)=0x%lx m=%d i=%d f=%d b=%d match=0x%x mask=0x%x inv=%d ig_ad=%d]\n", reg.pmc_val, reg.pmc8_9_ita2_reg.opcm_m, reg.pmc8_9_ita2_reg.opcm_i, reg.pmc8_9_ita2_reg.opcm_f, reg.pmc8_9_ita2_reg.opcm_b, reg.pmc8_9_ita2_reg.opcm_match, reg.pmc8_9_ita2_reg.opcm_mask, reg.pmc8_9_ita2_reg.opcm_inv, reg.pmc8_9_ita2_reg.opcm_ig_ad); } if (param->pfp_ita2_pmc9.opcm_used) { /* * PMC9 can only be used to qualify IA64_INST_RETIRED_* events */ if (check_inst_retired_events(inp, NULL) != inp->pfp_event_count) return PFMLIB_ERR_FEATCOMB; reg.pmc_val = param->pfp_ita2_pmc9.pmc_val; /* ig_ad, inv are ignored for PMC9, to avoid confusion we force default values */ reg.pmc8_9_ita2_reg.opcm_ig_ad = 1; reg.pmc8_9_ita2_reg.opcm_inv = 0; /* force bit 2 to 1 */ reg.pmc8_9_ita2_reg.opcm_bit2 = 1; if (pfm_regmask_isset(&inp->pfp_unavail_pmcs, 9)) return PFMLIB_ERR_NOASSIGN; pc[pos].reg_num = 9; pc[pos].reg_value = reg.pmc_val; pc[pos].reg_addr = pc[pos].reg_alt_addr = 9; pos++; /* * will be constrained by PMC9 */ has_1st_pair = has_2nd_pair = 0; count = inp->pfp_event_count; for(i=0; i < count; i++) { if (inp->pfp_events[i].event == PME_ITA2_IA64_TAGGED_INST_RETIRED_IBRP1_PMC9) has_1st_pair=1; if (inp->pfp_events[i].event == PME_ITA2_IA64_TAGGED_INST_RETIRED_IBRP3_PMC9) has_2nd_pair=1; } if (has_1st_pair || has_2nd_pair == 0) pmc15.pmc15_ita2_reg.opcmc_ibrp1_pmc9 = 0; if (has_2nd_pair || has_1st_pair == 0) pmc15.pmc15_ita2_reg.opcmc_ibrp3_pmc9 = 0; __pfm_vbprintf("[PMC9(pmc9)=0x%lx m=%d i=%d f=%d b=%d match=0x%x mask=0x%x]\n", reg.pmc_val, reg.pmc8_9_ita2_reg.opcm_m, reg.pmc8_9_ita2_reg.opcm_i, reg.pmc8_9_ita2_reg.opcm_f, reg.pmc8_9_ita2_reg.opcm_b, reg.pmc8_9_ita2_reg.opcm_match, reg.pmc8_9_ita2_reg.opcm_mask); } if (pfm_regmask_isset(&inp->pfp_unavail_pmcs, 15)) return PFMLIB_ERR_NOASSIGN; pc[pos].reg_num = 15; pc[pos].reg_value = pmc15.pmc_val; pc[pos].reg_addr = pc[pos].reg_alt_addr = 15; pos++; __pfm_vbprintf("[PMC15(pmc15)=0x%lx ibrp0_pmc8=%d ibrp1_pmc9=%d ibrp2_pmc8=%d ibrp3_pmc9=%d]\n", pmc15.pmc_val, pmc15.pmc15_ita2_reg.opcmc_ibrp0_pmc8, pmc15.pmc15_ita2_reg.opcmc_ibrp1_pmc9, pmc15.pmc15_ita2_reg.opcmc_ibrp2_pmc8, pmc15.pmc15_ita2_reg.opcmc_ibrp3_pmc9); outp->pfp_pmc_count = pos; return PFMLIB_SUCCESS; } static int pfm_dispatch_btb(pfmlib_input_param_t *inp, pfmlib_ita2_input_param_t *mod_in, pfmlib_output_param_t *outp) { pfmlib_event_t *e= inp->pfp_events; pfm_ita2_pmc_reg_t reg; pfmlib_ita2_input_param_t *param = mod_in; pfmlib_reg_t *pc, *pd; pfmlib_ita2_input_param_t fake_param; int found_btb = 0, found_bad_dear = 0; int has_btb_param; unsigned int i, pos1, pos2; unsigned int count; pc = outp->pfp_pmcs; pd = outp->pfp_pmds; pos1 = outp->pfp_pmc_count; pos2 = outp->pfp_pmd_count; /* * explicit BTB settings */ has_btb_param = param && param->pfp_ita2_btb.btb_used; reg.pmc_val = 0UL; /* * we need to scan all events looking for DEAR ALAT/TLB due to incompatibility */ count = inp->pfp_event_count; for (i=0; i < count; i++) { if (is_btb(e[i].event)) found_btb = 1; /* * keep track of the first BTB event */ /* look only for DEAR TLB */ if (is_dear(e[i].event) && (is_ear_tlb(e[i].event) || is_ear_alat(e[i].event))) { found_bad_dear = 1; } } DPRINT("found_btb=%d found_bar_dear=%d\n", found_btb, found_bad_dear); /* * did not find D-EAR TLB/ALAT event, need to check param structure */ if (found_bad_dear == 0 && param && param->pfp_ita2_dear.ear_used == 1) { if ( param->pfp_ita2_dear.ear_mode == PFMLIB_ITA2_EAR_TLB_MODE || param->pfp_ita2_dear.ear_mode == PFMLIB_ITA2_EAR_ALAT_MODE) found_bad_dear = 1; } /* * no explicit BTB event and no special case to deal with (cover part of case 3) */ if (found_btb == 0 && has_btb_param == 0 && found_bad_dear == 0) return PFMLIB_SUCCESS; if (has_btb_param == 0) { /* * case 3: no BTB event, btb_used=0 but found_bad_dear=1, need to cleanup PMC12 */ if (found_btb == 0) goto assign_zero; /* * case 1: we have a BTB event but no param, default setting is to capture * all branches. */ memset(&fake_param, 0, sizeof(fake_param)); param = &fake_param; param->pfp_ita2_btb.btb_ds = 0; /* capture branch targets */ param->pfp_ita2_btb.btb_tm = 0x3; /* all branches */ param->pfp_ita2_btb.btb_ptm = 0x3; /* all branches */ param->pfp_ita2_btb.btb_ppm = 0x3; /* all branches */ param->pfp_ita2_btb.btb_brt = 0x0; /* all branches */ DPRINT("BTB event with no info\n"); } /* * case 2: BTB event in the list, param provided * case 4: no BTB event, param provided (free running mode) */ reg.pmc12_ita2_reg.btbc_plm = param->pfp_ita2_btb.btb_plm ? param->pfp_ita2_btb.btb_plm : inp->pfp_dfl_plm; reg.pmc12_ita2_reg.btbc_pm = inp->pfp_flags & PFMLIB_PFP_SYSTEMWIDE ? 1 : 0; reg.pmc12_ita2_reg.btbc_ds = param->pfp_ita2_btb.btb_ds & 0x1; reg.pmc12_ita2_reg.btbc_tm = param->pfp_ita2_btb.btb_tm & 0x3; reg.pmc12_ita2_reg.btbc_ptm = param->pfp_ita2_btb.btb_ptm & 0x3; reg.pmc12_ita2_reg.btbc_ppm = param->pfp_ita2_btb.btb_ppm & 0x3; reg.pmc12_ita2_reg.btbc_brt = param->pfp_ita2_btb.btb_brt & 0x3; /* * if DEAR-ALAT or DEAR-TLB is set then PMC12 must be set to zero (see documentation p. 87) * * D-EAR ALAT/TLB and BTB cannot be used at the same time. * From documentation: PMC12 must be zero in this mode; else the wrong IP for misses * coming right after a mispredicted branch. * * D-EAR cache is fine. */ assign_zero: if (found_bad_dear && reg.pmc_val != 0UL) return PFMLIB_ERR_EVTINCOMP; if (pfm_regmask_isset(&inp->pfp_unavail_pmcs, 12)) return PFMLIB_ERR_NOASSIGN; memset(pc+pos1, 0, sizeof(pfmlib_reg_t)); pc[pos1].reg_num = 12; pc[pos1].reg_value = reg.pmc_val; pc[pos1].reg_addr = pc[pos1].reg_alt_addr = 12; pos1++; __pfm_vbprintf("[PMC12(pmc12)=0x%lx plm=%d pm=%d ds=%d tm=%d ptm=%d ppm=%d brt=%d]\n", reg.pmc_val, reg.pmc12_ita2_reg.btbc_plm, reg.pmc12_ita2_reg.btbc_pm, reg.pmc12_ita2_reg.btbc_ds, reg.pmc12_ita2_reg.btbc_tm, reg.pmc12_ita2_reg.btbc_ptm, reg.pmc12_ita2_reg.btbc_ppm, reg.pmc12_ita2_reg.btbc_brt); /* * only add BTB PMD when actually using BTB. * Not needed when dealing with D-EAR TLB and DEAR-ALAT * PMC12 restriction */ if (found_btb || has_btb_param) { /* * PMD16 is included in list of used PMD */ for(i=8; i < 17; i++, pos2++) { pd[pos2].reg_num = i; pd[pos2].reg_addr = pd[pos2].reg_alt_addr = i; __pfm_vbprintf("[PMD%u(pmd%u)]\n", pd[pos2].reg_num, pd[pos2].reg_num); } } /* update final number of entries used */ outp->pfp_pmc_count = pos1; outp->pfp_pmd_count = pos2; return PFMLIB_SUCCESS; } static void do_normal_rr(unsigned long start, unsigned long end, pfmlib_reg_t *br, int nbr, int dir, int *idx, int *reg_idx, int plm) { unsigned long size, l_addr, c; unsigned long l_offs = 0, r_offs = 0; unsigned long l_size, r_size; dbreg_t db; int p2; if (nbr < 1 || end <= start) return; size = end - start; DPRINT("start=0x%016lx end=0x%016lx size=0x%lx bytes (%lu bundles) nbr=%d dir=%d\n", start, end, size, size >> 4, nbr, dir); p2 = pfm_ia64_fls(size); c = ALIGN_DOWN(end, p2); DPRINT("largest power of two possible: 2^%d=0x%lx, crossing=0x%016lx\n", p2, 1UL << p2, c); if ((c - (1UL<= start) { l_addr = c - (1UL << p2); } else { p2--; if ((c + (1UL<>l_offs: 0x%lx\n", l_offs); } } else if (dir == 1 && r_size != 0 && nbr == 1) { p2++; l_addr = start; if (PFMLIB_DEBUG()) { r_offs = l_addr+(1UL<>r_offs: 0x%lx\n", r_offs); } } l_size = l_addr - start; r_size = end - l_addr-(1UL<>largest chunk: 2^%d @0x%016lx-0x%016lx\n", p2, l_addr, l_addr+(1UL<>before: 0x%016lx-0x%016lx\n", start, l_addr); if (r_size && !r_offs) printf(">>after : 0x%016lx-0x%016lx\n", l_addr+(1UL<>1; if (nbr & 0x1) { /* * our simple heuristic is: * we assign the largest number of registers to the largest * of the two chunks */ if (l_size > r_size) { l_nbr++; } else { r_nbr++; } } do_normal_rr(start, l_addr, br, l_nbr, 0, idx, reg_idx, plm); do_normal_rr(l_addr+(1UL<rr_start, in_rr->rr_end, n_pairs, fine_mode ? ", fine_mode" : "", rr_flags & PFMLIB_ITA2_RR_INV ? ", inversed" : ""); __pfm_vbprintf("start offset: -0x%lx end_offset: +0x%lx\n", out_rr->rr_soff, out_rr->rr_eoff); for (j=0; j < n_pairs; j++, base_idx+=2) { d.val = dbr[base_idx+1].reg_value; r_end = dbr[base_idx].reg_value+((~(d.db.db_mask)) & ~(0xffUL << 56)); if (fine_mode) __pfm_vbprintf("brp%u: db%u: 0x%016lx db%u: plm=0x%x mask=0x%016lx\n", dbr[base_idx].reg_num>>1, dbr[base_idx].reg_num, dbr[base_idx].reg_value, dbr[base_idx+1].reg_num, d.db.db_plm, d.db.db_mask); else __pfm_vbprintf("brp%u: db%u: 0x%016lx db%u: plm=0x%x mask=0x%016lx end=0x%016lx\n", dbr[base_idx].reg_num>>1, dbr[base_idx].reg_num, dbr[base_idx].reg_value, dbr[base_idx+1].reg_num, d.db.db_plm, d.db.db_mask, r_end); } } /* * base_idx = base register index to use (for IBRP1, base_idx = 2) */ static int compute_fine_rr(pfmlib_ita2_input_rr_t *irr, int dfl_plm, int n, int *base_idx, pfmlib_ita2_output_rr_t *orr) { int i; pfmlib_reg_t *br; pfmlib_ita2_input_rr_desc_t *in_rr; pfmlib_ita2_output_rr_desc_t *out_rr; unsigned long addr; int reg_idx; dbreg_t db; in_rr = irr->rr_limits; out_rr = orr->rr_infos; br = orr->rr_br+orr->rr_nbr_used; reg_idx = *base_idx; db.val = 0; db.db.db_mask = FINE_MODE_MASK; if (n > 2) return PFMLIB_ERR_IRRTOOMANY; for (i=0; i < n; i++, reg_idx += 2, in_rr++, br+= 4) { /* * setup lower limit pair * * because of the PMU bug, we must align down to the closest bundle-pair * aligned address. 5 => 32-byte aligned address */ addr = has_fine_mode_bug ? ALIGN_DOWN(in_rr->rr_start, 5) : in_rr->rr_start; out_rr->rr_soff = in_rr->rr_start - addr; /* * adjust plm for each range */ db.db.db_plm = in_rr->rr_plm ? in_rr->rr_plm : (unsigned long)dfl_plm; br[0].reg_num = reg_idx; br[0].reg_value = addr; br[0].reg_addr = br[0].reg_alt_addr = reg_idx; br[1].reg_num = reg_idx+1; br[1].reg_value = db.val; br[1].reg_addr = br[1].reg_alt_addr = reg_idx+1; /* * setup upper limit pair * * * In fine mode, the bundle address stored in the upper limit debug * registers is included in the count, so we substract 0x10 to exclude it. * * because of the PMU bug, we align the (corrected) end to the nearest * 32-byte aligned address + 0x10. With this correction and depending * on the correction, we may count one * * */ addr = in_rr->rr_end - 0x10; if (has_fine_mode_bug && (addr & 0x1f) == 0) addr += 0x10; out_rr->rr_eoff = addr - in_rr->rr_end + 0x10; br[2].reg_num = reg_idx+4; br[2].reg_value = addr; br[2].reg_addr = br[2].reg_alt_addr = reg_idx+4; br[3].reg_num = reg_idx+5; br[3].reg_value = db.val; br[3].reg_addr = br[3].reg_alt_addr = reg_idx+5; if (PFMLIB_VERBOSE()) print_one_range(in_rr, out_rr, br, 0, 2, 1, irr->rr_flags); } orr->rr_nbr_used += i<<2; /* update base_idx, for subsequent calls */ *base_idx = reg_idx; return PFMLIB_SUCCESS; } /* * base_idx = base register index to use (for IBRP1, base_idx = 2) */ static int compute_single_rr(pfmlib_ita2_input_rr_t *irr, int dfl_plm, int *base_idx, pfmlib_ita2_output_rr_t *orr) { unsigned long size, end, start; unsigned long p_start, p_end; pfmlib_ita2_input_rr_desc_t *in_rr; pfmlib_ita2_output_rr_desc_t *out_rr; pfmlib_reg_t *br; dbreg_t db; int reg_idx; int l, m; in_rr = irr->rr_limits; out_rr = orr->rr_infos; br = orr->rr_br+orr->rr_nbr_used; start = in_rr->rr_start; end = in_rr->rr_end; size = end - start; reg_idx = *base_idx; l = pfm_ia64_fls(size); m = l; if (size & ((1UL << l)-1)) { if (l>62) { printf("range: [0x%lx-0x%lx] too big\n", start, end); return PFMLIB_ERR_IRRTOOBIG; } m++; } DPRINT("size=%ld, l=%d m=%d, internal: 0x%lx full: 0x%lx\n", size, l, m, 1UL << l, 1UL << m); for (; m < 64; m++) { p_start = ALIGN_DOWN(start, m); p_end = p_start+(1UL<= end) goto found; } return PFMLIB_ERR_IRRINVAL; found: DPRINT("m=%d p_start=0x%lx p_end=0x%lx\n", m, p_start,p_end); /* when the event is not IA64_INST_RETIRED, then we MUST use ibrp0 */ br[0].reg_num = reg_idx; br[0].reg_value = p_start; br[0].reg_addr = br[0].reg_alt_addr = reg_idx; db.val = 0; db.db.db_mask = ~((1UL << m)-1); db.db.db_plm = in_rr->rr_plm ? in_rr->rr_plm : (unsigned long)dfl_plm; br[1].reg_num = reg_idx + 1; br[1].reg_value = db.val; br[1].reg_addr = br[1].reg_alt_addr = reg_idx + 1; out_rr->rr_soff = start - p_start; out_rr->rr_eoff = p_end - end; if (PFMLIB_VERBOSE()) print_one_range(in_rr, out_rr, br, 0, 1, 0, irr->rr_flags); orr->rr_nbr_used += 2; /* update base_idx, for subsequent calls */ *base_idx = reg_idx; return PFMLIB_SUCCESS; } static int compute_normal_rr(pfmlib_ita2_input_rr_t *irr, int dfl_plm, int n, int *base_idx, pfmlib_ita2_output_rr_t *orr) { pfmlib_ita2_input_rr_desc_t *in_rr; pfmlib_ita2_output_rr_desc_t *out_rr; unsigned long r_end; pfmlib_reg_t *br; dbreg_t d; int i, j; int br_index, reg_idx, prev_index; in_rr = irr->rr_limits; out_rr = orr->rr_infos; br = orr->rr_br+orr->rr_nbr_used; reg_idx = *base_idx; br_index = 0; for (i=0; i < n; i++, in_rr++, out_rr++) { /* * running out of registers */ if (br_index == 8) break; prev_index = br_index; do_normal_rr( in_rr->rr_start, in_rr->rr_end, br, 4 - (reg_idx>>1), /* how many pairs available */ 0, &br_index, ®_idx, in_rr->rr_plm ? in_rr->rr_plm : dfl_plm); DPRINT("br_index=%d reg_idx=%d\n", br_index, reg_idx); /* * compute offsets */ out_rr->rr_soff = out_rr->rr_eoff = 0; for(j=prev_index; j < br_index; j+=2) { d.val = br[j+1].reg_value; r_end = br[j].reg_value+((~(d.db.db_mask)+1) & ~(0xffUL << 56)); if (br[j].reg_value <= in_rr->rr_start) out_rr->rr_soff = in_rr->rr_start - br[j].reg_value; if (r_end >= in_rr->rr_end) out_rr->rr_eoff = r_end - in_rr->rr_end; } if (PFMLIB_VERBOSE()) print_one_range(in_rr, out_rr, br, prev_index, (br_index-prev_index)>>1, 0, irr->rr_flags); } /* do not have enough registers to cover all the ranges */ if (br_index == 8 && i < n) return PFMLIB_ERR_TOOMANY; orr->rr_nbr_used += br_index; /* update base_idx, for subsequent calls */ *base_idx = reg_idx; return PFMLIB_SUCCESS; } static int pfm_dispatch_irange(pfmlib_input_param_t *inp, pfmlib_ita2_input_param_t *mod_in, pfmlib_output_param_t *outp, pfmlib_ita2_output_param_t *mod_out) { pfm_ita2_pmc_reg_t reg; pfmlib_ita2_input_param_t *param = mod_in; pfmlib_ita2_input_rr_t *irr; pfmlib_ita2_output_rr_t *orr; pfmlib_reg_t *pc = outp->pfp_pmcs; unsigned int i, pos = outp->pfp_pmc_count, count; int ret; unsigned int retired_only, retired_count, fine_mode, prefetch_count; unsigned int n_intervals; int base_idx = 0; unsigned long retired_mask; if (param == NULL) return PFMLIB_SUCCESS; if (param->pfp_ita2_irange.rr_used == 0) return PFMLIB_SUCCESS; if (mod_out == NULL) return PFMLIB_ERR_INVAL; irr = ¶m->pfp_ita2_irange; orr = &mod_out->pfp_ita2_irange; ret = check_intervals(irr, 0, &n_intervals); if (ret != PFMLIB_SUCCESS) return ret; if (n_intervals < 1) return PFMLIB_ERR_IRRINVAL; retired_count = check_inst_retired_events(inp, &retired_mask); retired_only = retired_count == inp->pfp_event_count; prefetch_count = check_prefetch_events(inp); fine_mode = irr->rr_flags & PFMLIB_ITA2_RR_NO_FINE_MODE ? 0 : check_fine_mode_possible(irr, n_intervals); DPRINT("n_intervals=%d retired_only=%d retired_count=%d prefetch_count=%d fine_mode=%d\n", n_intervals, retired_only, retired_count, prefetch_count, fine_mode); /* * On Itanium2, there are more constraints on what can be measured with irange. * * - The fine mode is the best because you directly set the lower and upper limits of * the range. This uses 2 ibr pairs for range (ibrp0/ibrp2 and ibp1/ibrp3). Therefore * at most 2 fine mode ranges can be defined. There is a limit on the size and alignment * of the range to allow fine mode: the range must be less than 4KB in size AND the lower * and upper limits must NOT cross a 4KB page boundary. The fine mode works will all events. * * - if the fine mode fails, then for all events, except IA64_TAGGED_INST_RETIRED_*, only * the first pair of ibr is available: ibrp0. This imposes some severe restrictions on the * size and alignement of the range. It can be bigger than 4KB and must be properly aligned * on its size. The library relaxes these constraints by allowing the covered areas to be * larger than the expected range. It may start before and end after. You can determine how * far off the range is in either direction for each range by looking at the rr_soff (start * offset) and rr_eoff (end offset). * * - if the events include certain prefetch events then only IBRP1 can be used in fine mode * See 10.3.5.1 Exception 1. * * - Finally, when the events are ONLY IA64_TAGGED_INST_RETIRED_* then all IBR pairs can be used * to cover the range giving us more flexibility to approximate the range when it is not * properly aligned on its size (see 10.3.5.2 Exception 2). */ if (fine_mode == 0 && retired_only == 0 && n_intervals > 1) return PFMLIB_ERR_IRRTOOMANY; /* we do not default to non-fine mode to support more ranges */ if (n_intervals > 2 && fine_mode == 1) return PFMLIB_ERR_IRRTOOMANY; if (fine_mode == 0) { if (retired_only) { ret = compute_normal_rr(irr, inp->pfp_dfl_plm, n_intervals, &base_idx, orr); } else { /* unless we have only prefetch and instruction retired events, * we cannot satisfy the request because the other events cannot * be measured on anything but IBRP0. */ if (prefetch_count && (prefetch_count+retired_count) != inp->pfp_event_count) return PFMLIB_ERR_FEATCOMB; base_idx = prefetch_count ? 2 : 0; ret = compute_single_rr(irr, inp->pfp_dfl_plm, &base_idx, orr); } } else { if (prefetch_count && n_intervals != 1) return PFMLIB_ERR_IRRTOOMANY; base_idx = prefetch_count ? 2 : 0; ret = compute_fine_rr(irr, inp->pfp_dfl_plm, n_intervals, &base_idx, orr); } if (ret != PFMLIB_SUCCESS) { return ret == PFMLIB_ERR_TOOMANY ? PFMLIB_ERR_IRRTOOMANY : ret; } reg.pmc_val = 0xdb6; /* default value */ count = orr->rr_nbr_used; for (i=0; i < count; i++) { switch(orr->rr_br[i].reg_num) { case 0: reg.pmc14_ita2_reg.iarc_ibrp0 = 0; break; case 2: reg.pmc14_ita2_reg.iarc_ibrp1 = 0; break; case 4: reg.pmc14_ita2_reg.iarc_ibrp2 = 0; break; case 6: reg.pmc14_ita2_reg.iarc_ibrp3 = 0; break; } } if (retired_only && (param->pfp_ita2_pmc8.opcm_used ||param->pfp_ita2_pmc9.opcm_used)) { /* * PMC8 + IA64_INST_RETIRED only works if irange on IBRP0 and/or IBRP2 * PMC9 + IA64_INST_RETIRED only works if irange on IBRP1 and/or IBRP3 */ count = orr->rr_nbr_used; for (i=0; i < count; i++) { if (orr->rr_br[i].reg_num == 0 && param->pfp_ita2_pmc9.opcm_used) return PFMLIB_ERR_FEATCOMB; if (orr->rr_br[i].reg_num == 2 && param->pfp_ita2_pmc8.opcm_used) return PFMLIB_ERR_FEATCOMB; if (orr->rr_br[i].reg_num == 4 && param->pfp_ita2_pmc9.opcm_used) return PFMLIB_ERR_FEATCOMB; if (orr->rr_br[i].reg_num == 6 && param->pfp_ita2_pmc8.opcm_used) return PFMLIB_ERR_FEATCOMB; } } if (fine_mode) { reg.pmc14_ita2_reg.iarc_fine = 1; } else if (retired_only) { /* * we need to check that the user provided all the events needed to cover * all the ibr pairs used to cover the range */ if ((retired_mask & 0x1) == 0 && reg.pmc14_ita2_reg.iarc_ibrp0 == 0) return PFMLIB_ERR_IRRINVAL; if ((retired_mask & 0x2) == 0 && reg.pmc14_ita2_reg.iarc_ibrp1 == 0) return PFMLIB_ERR_IRRINVAL; if ((retired_mask & 0x4) == 0 && reg.pmc14_ita2_reg.iarc_ibrp2 == 0) return PFMLIB_ERR_IRRINVAL; if ((retired_mask & 0x8) == 0 && reg.pmc14_ita2_reg.iarc_ibrp3 == 0) return PFMLIB_ERR_IRRINVAL; } /* initialize pmc request slot */ memset(pc+pos, 0, sizeof(pfmlib_reg_t)); if (pfm_regmask_isset(&inp->pfp_unavail_pmcs, 14)) return PFMLIB_ERR_NOASSIGN; pc[pos].reg_num = 14; pc[pos].reg_value = reg.pmc_val; pc[pos].reg_addr = pc[pos].reg_alt_addr = 14; pos++; __pfm_vbprintf("[PMC14(pmc14)=0x%lx ibrp0=%d ibrp1=%d ibrp2=%d ibrp3=%d fine=%d]\n", reg.pmc_val, reg.pmc14_ita2_reg.iarc_ibrp0, reg.pmc14_ita2_reg.iarc_ibrp1, reg.pmc14_ita2_reg.iarc_ibrp2, reg.pmc14_ita2_reg.iarc_ibrp3, reg.pmc14_ita2_reg.iarc_fine); outp->pfp_pmc_count = pos; return PFMLIB_SUCCESS; } static const unsigned long iod_tab[8]={ /* --- */ 3, /* --D */ 2, /* -O- */ 3, /* should not be used */ /* -OD */ 0, /* =IOD safe because default IBR is harmless */ /* I-- */ 1, /* =IO safe because by defaut OPC is turned off */ /* I-D */ 0, /* =IOD safe because by default opc is turned off */ /* IO- */ 1, /* IOD */ 0 }; /* * IMPORTANT: MUST BE CALLED *AFTER* pfm_dispatch_irange() to make sure we see * the irange programming to adjust pmc13. */ static int pfm_dispatch_drange(pfmlib_input_param_t *inp, pfmlib_ita2_input_param_t *mod_in, pfmlib_output_param_t *outp, pfmlib_ita2_output_param_t *mod_out) { pfmlib_ita2_input_param_t *param = mod_in; pfmlib_reg_t *pc = outp->pfp_pmcs; pfmlib_ita2_input_rr_t *irr; pfmlib_ita2_output_rr_t *orr, *orr2; pfm_ita2_pmc_reg_t pmc13; pfm_ita2_pmc_reg_t pmc14; unsigned int i, pos = outp->pfp_pmc_count; int iod_codes[4], dfl_val_pmc8, dfl_val_pmc9; unsigned int n_intervals; int ret; int base_idx = 0; int fine_mode = 0; #define DR_USED 0x1 /* data range is used */ #define OP_USED 0x2 /* opcode matching is used */ #define IR_USED 0x4 /* code range is used */ if (param == NULL) return PFMLIB_SUCCESS; /* * if only pmc8/pmc9 opcode matching is used, we do not need to change * the default value of pmc13 regardless of the events being measured. */ if ( param->pfp_ita2_drange.rr_used == 0 && param->pfp_ita2_irange.rr_used == 0) return PFMLIB_SUCCESS; /* * it seems like the ignored bits need to have special values * otherwise this does not work. */ pmc13.pmc_val = 0x2078fefefefe; /* * initialize iod codes */ iod_codes[0] = iod_codes[1] = iod_codes[2] = iod_codes[3] = 0; /* * setup default iod value, we need to separate because * if drange is used we do not know in advance which DBR will be used * therefore we need to apply dfl_val later */ dfl_val_pmc8 = param->pfp_ita2_pmc8.opcm_used ? OP_USED : 0; dfl_val_pmc9 = param->pfp_ita2_pmc9.opcm_used ? OP_USED : 0; if (param->pfp_ita2_drange.rr_used == 1) { if (mod_out == NULL) return PFMLIB_ERR_INVAL; irr = ¶m->pfp_ita2_drange; orr = &mod_out->pfp_ita2_drange; ret = check_intervals(irr, 1, &n_intervals); if (ret != PFMLIB_SUCCESS) return ret; if (n_intervals < 1) return PFMLIB_ERR_DRRINVAL; ret = compute_normal_rr(irr, inp->pfp_dfl_plm, n_intervals, &base_idx, orr); if (ret != PFMLIB_SUCCESS) { return ret == PFMLIB_ERR_TOOMANY ? PFMLIB_ERR_DRRTOOMANY : ret; } /* * Update iod_codes to reflect the use of the DBR constraint. */ for (i=0; i < orr->rr_nbr_used; i++) { if (orr->rr_br[i].reg_num == 0) iod_codes[0] |= DR_USED | dfl_val_pmc8; if (orr->rr_br[i].reg_num == 2) iod_codes[1] |= DR_USED | dfl_val_pmc9; if (orr->rr_br[i].reg_num == 4) iod_codes[2] |= DR_USED | dfl_val_pmc8; if (orr->rr_br[i].reg_num == 6) iod_codes[3] |= DR_USED | dfl_val_pmc9; } } /* * XXX: assume dispatch_irange executed before calling this function */ if (param->pfp_ita2_irange.rr_used == 1) { orr2 = &mod_out->pfp_ita2_irange; if (mod_out == NULL) return PFMLIB_ERR_INVAL; /* * we need to find out whether or not the irange is using * fine mode. If this is the case, then we only need to * program pmc13 for the ibr pairs which designate the lower * bounds of a range. For instance, if IBRP0/IBRP2 are used, * then we only need to program pmc13.cfg_dbrp0 and pmc13.ena_dbrp0, * the PMU will automatically use IBRP2, even though pmc13.ena_dbrp2=0. */ for(i=0; i <= pos; i++) { if (pc[i].reg_num == 14) { pmc14.pmc_val = pc[i].reg_value; if (pmc14.pmc14_ita2_reg.iarc_fine == 1) fine_mode = 1; break; } } /* * Update to reflect the use of the IBR constraint */ for (i=0; i < orr2->rr_nbr_used; i++) { if (orr2->rr_br[i].reg_num == 0) iod_codes[0] |= IR_USED | dfl_val_pmc8; if (orr2->rr_br[i].reg_num == 2) iod_codes[1] |= IR_USED | dfl_val_pmc9; if (fine_mode == 0 && orr2->rr_br[i].reg_num == 4) iod_codes[2] |= IR_USED | dfl_val_pmc8; if (fine_mode == 0 && orr2->rr_br[i].reg_num == 6) iod_codes[3] |= IR_USED | dfl_val_pmc9; } } if (param->pfp_ita2_irange.rr_used == 0 && param->pfp_ita2_drange.rr_used ==0) { iod_codes[0] = iod_codes[2] = dfl_val_pmc8; iod_codes[1] = iod_codes[3] = dfl_val_pmc9; } /* * update the cfg dbrpX field. If we put a constraint on a cfg dbrp, then * we must enable it in the corresponding ena_dbrpX */ pmc13.pmc13_ita2_reg.darc_ena_dbrp0 = iod_codes[0] ? 1 : 0; pmc13.pmc13_ita2_reg.darc_cfg_dbrp0 = iod_tab[iod_codes[0]]; pmc13.pmc13_ita2_reg.darc_ena_dbrp1 = iod_codes[1] ? 1 : 0; pmc13.pmc13_ita2_reg.darc_cfg_dbrp1 = iod_tab[iod_codes[1]]; pmc13.pmc13_ita2_reg.darc_ena_dbrp2 = iod_codes[2] ? 1 : 0; pmc13.pmc13_ita2_reg.darc_cfg_dbrp2 = iod_tab[iod_codes[2]]; pmc13.pmc13_ita2_reg.darc_ena_dbrp3 = iod_codes[3] ? 1 : 0; pmc13.pmc13_ita2_reg.darc_cfg_dbrp3 = iod_tab[iod_codes[3]]; if (pfm_regmask_isset(&inp->pfp_unavail_pmcs, 13)) return PFMLIB_ERR_NOASSIGN; pc[pos].reg_num = 13; pc[pos].reg_value = pmc13.pmc_val; pc[pos].reg_addr = pc[pos].reg_alt_addr = 13; pos++; __pfm_vbprintf("[PMC13(pmc13)=0x%lx cfg_dbrp0=%d cfg_dbrp1=%d cfg_dbrp2=%d cfg_dbrp3=%d ena_dbrp0=%d ena_dbrp1=%d ena_dbrp2=%d ena_dbrp3=%d]\n", pmc13.pmc_val, pmc13.pmc13_ita2_reg.darc_cfg_dbrp0, pmc13.pmc13_ita2_reg.darc_cfg_dbrp1, pmc13.pmc13_ita2_reg.darc_cfg_dbrp2, pmc13.pmc13_ita2_reg.darc_cfg_dbrp3, pmc13.pmc13_ita2_reg.darc_ena_dbrp0, pmc13.pmc13_ita2_reg.darc_ena_dbrp1, pmc13.pmc13_ita2_reg.darc_ena_dbrp2, pmc13.pmc13_ita2_reg.darc_ena_dbrp3); outp->pfp_pmc_count = pos; return PFMLIB_SUCCESS; } static int check_qualifier_constraints(pfmlib_input_param_t *inp, pfmlib_ita2_input_param_t *mod_in) { pfmlib_ita2_input_param_t *param = mod_in; pfmlib_event_t *e = inp->pfp_events; unsigned int i, count; count = inp->pfp_event_count; for(i=0; i < count; i++) { /* * skip check for counter which requested it. Use at your own risk. * No all counters have necessarily been validated for use with * qualifiers. Typically the event is counted as if no constraint * existed. */ if (param->pfp_ita2_counters[i].flags & PFMLIB_ITA2_FL_EVT_NO_QUALCHECK) continue; if (evt_use_irange(param) && has_iarr(e[i].event) == 0) return PFMLIB_ERR_FEATCOMB; if (evt_use_drange(param) && has_darr(e[i].event) == 0) return PFMLIB_ERR_FEATCOMB; if (evt_use_opcm(param) && has_opcm(e[i].event) == 0) return PFMLIB_ERR_FEATCOMB; } return PFMLIB_SUCCESS; } static int check_range_plm(pfmlib_input_param_t *inp, pfmlib_ita2_input_param_t *mod_in) { pfmlib_ita2_input_param_t *param = mod_in; unsigned int i, count; if (param->pfp_ita2_drange.rr_used == 0 && param->pfp_ita2_irange.rr_used == 0) return PFMLIB_SUCCESS; /* * range restriction applies to all events, therefore we must have a consistent * set of plm and they must match the pfp_dfl_plm which is used to setup the debug * registers */ count = inp->pfp_event_count; for(i=0; i < count; i++) { if (inp->pfp_events[i].plm && inp->pfp_events[i].plm != inp->pfp_dfl_plm) return PFMLIB_ERR_FEATCOMB; } return PFMLIB_SUCCESS; } static int pfm_ita2_dispatch_events(pfmlib_input_param_t *inp, void *model_in, pfmlib_output_param_t *outp, void *model_out) { int ret; pfmlib_ita2_input_param_t *mod_in = (pfmlib_ita2_input_param_t *)model_in; pfmlib_ita2_output_param_t *mod_out = (pfmlib_ita2_output_param_t *)model_out; /* * nothing will come out of this combination */ if (mod_out && mod_in == NULL) return PFMLIB_ERR_INVAL; /* check opcode match, range restriction qualifiers */ if (mod_in && check_qualifier_constraints(inp, mod_in) != PFMLIB_SUCCESS) return PFMLIB_ERR_FEATCOMB; /* check for problems with raneg restriction and per-event plm */ if (mod_in && check_range_plm(inp, mod_in) != PFMLIB_SUCCESS) return PFMLIB_ERR_FEATCOMB; ret = pfm_ita2_dispatch_counters(inp, mod_in, outp); if (ret != PFMLIB_SUCCESS) return ret; /* now check for I-EAR */ ret = pfm_dispatch_iear(inp, mod_in, outp); if (ret != PFMLIB_SUCCESS) return ret; /* now check for D-EAR */ ret = pfm_dispatch_dear(inp, mod_in, outp); if (ret != PFMLIB_SUCCESS) return ret; /* XXX: must be done before dispatch_opcm() and dispatch_drange() */ ret = pfm_dispatch_irange(inp, mod_in, outp, mod_out);; if (ret != PFMLIB_SUCCESS) return ret; ret = pfm_dispatch_drange(inp, mod_in, outp, mod_out);; if (ret != PFMLIB_SUCCESS) return ret; /* now check for Opcode matchers */ ret = pfm_dispatch_opcm(inp, mod_in, outp, mod_out); if (ret != PFMLIB_SUCCESS) return ret; ret = pfm_dispatch_btb(inp, mod_in, outp); return ret; } /* XXX: return value is also error code */ int pfm_ita2_get_event_maxincr(unsigned int i, unsigned int *maxincr) { if (i >= PME_ITA2_EVENT_COUNT || maxincr == NULL) return PFMLIB_ERR_INVAL; *maxincr = itanium2_pe[i].pme_maxincr; return PFMLIB_SUCCESS; } int pfm_ita2_is_ear(unsigned int i) { return i < PME_ITA2_EVENT_COUNT && is_ear(i); } int pfm_ita2_is_dear(unsigned int i) { return i < PME_ITA2_EVENT_COUNT && is_dear(i); } int pfm_ita2_is_dear_tlb(unsigned int i) { return i < PME_ITA2_EVENT_COUNT && is_dear(i) && is_ear_tlb(i); } int pfm_ita2_is_dear_cache(unsigned int i) { return i < PME_ITA2_EVENT_COUNT && is_dear(i) && is_ear_cache(i); } int pfm_ita2_is_dear_alat(unsigned int i) { return i < PME_ITA2_EVENT_COUNT && is_ear_alat(i); } int pfm_ita2_is_iear(unsigned int i) { return i < PME_ITA2_EVENT_COUNT && is_iear(i); } int pfm_ita2_is_iear_tlb(unsigned int i) { return i < PME_ITA2_EVENT_COUNT && is_iear(i) && is_ear_tlb(i); } int pfm_ita2_is_iear_cache(unsigned int i) { return i < PME_ITA2_EVENT_COUNT && is_iear(i) && is_ear_cache(i); } int pfm_ita2_is_btb(unsigned int i) { return i < PME_ITA2_EVENT_COUNT && is_btb(i); } int pfm_ita2_support_iarr(unsigned int i) { return i < PME_ITA2_EVENT_COUNT && has_iarr(i); } int pfm_ita2_support_darr(unsigned int i) { return i < PME_ITA2_EVENT_COUNT && has_darr(i); } int pfm_ita2_support_opcm(unsigned int i) { return i < PME_ITA2_EVENT_COUNT && has_opcm(i); } int pfm_ita2_get_ear_mode(unsigned int i, pfmlib_ita2_ear_mode_t *m) { pfmlib_ita2_ear_mode_t r; if (!is_ear(i) || m == NULL) return PFMLIB_ERR_INVAL; r = PFMLIB_ITA2_EAR_TLB_MODE; if (is_ear_tlb(i)) goto done; r = PFMLIB_ITA2_EAR_CACHE_MODE; if (is_ear_cache(i)) goto done; r = PFMLIB_ITA2_EAR_ALAT_MODE; if (is_ear_alat(i)) goto done; return PFMLIB_ERR_INVAL; done: *m = r; return PFMLIB_SUCCESS; } static int pfm_ita2_get_event_code(unsigned int i, unsigned int cnt, int *code) { if (cnt != PFMLIB_CNT_FIRST && (cnt < 4 || cnt > 7)) return PFMLIB_ERR_INVAL; *code = (int)itanium2_pe[i].pme_code; return PFMLIB_SUCCESS; } /* * This function is accessible directly to the user */ int pfm_ita2_get_event_umask(unsigned int i, unsigned long *umask) { if (i >= PME_ITA2_EVENT_COUNT || umask == NULL) return PFMLIB_ERR_INVAL; *umask = evt_umask(i); return PFMLIB_SUCCESS; } int pfm_ita2_get_event_group(unsigned int i, int *grp) { if (i >= PME_ITA2_EVENT_COUNT || grp == NULL) return PFMLIB_ERR_INVAL; *grp = evt_grp(i); return PFMLIB_SUCCESS; } int pfm_ita2_get_event_set(unsigned int i, int *set) { if (i >= PME_ITA2_EVENT_COUNT || set == NULL) return PFMLIB_ERR_INVAL; *set = evt_set(i) == 0xf ? PFMLIB_ITA2_EVT_NO_SET : evt_set(i); return PFMLIB_SUCCESS; } /* external interface */ int pfm_ita2_irange_is_fine(pfmlib_output_param_t *outp, pfmlib_ita2_output_param_t *mod_out) { pfmlib_ita2_output_param_t *param = mod_out; pfm_ita2_pmc_reg_t reg; unsigned int i, count; /* some sanity checks */ if (outp == NULL || param == NULL) return 0; if (outp->pfp_pmc_count >= PFMLIB_MAX_PMCS) return 0; if (param->pfp_ita2_irange.rr_nbr_used == 0) return 0; /* * we look for pmc14 as it contains the bit indicating if fine mode is used */ count = outp->pfp_pmc_count; for(i=0; i < count; i++) { if (outp->pfp_pmcs[i].reg_num == 14) goto found; } return 0; found: reg.pmc_val = outp->pfp_pmcs[i].reg_value; return reg.pmc14_ita2_reg.iarc_fine ? 1 : 0; } static char * pfm_ita2_get_event_name(unsigned int i) { return itanium2_pe[i].pme_name; } static void pfm_ita2_get_event_counters(unsigned int j, pfmlib_regmask_t *counters) { unsigned int i; unsigned long m; memset(counters, 0, sizeof(*counters)); m =itanium2_pe[j].pme_counters; for(i=0; m ; i++, m>>=1) { if (m & 0x1) pfm_regmask_set(counters, i); } } static void pfm_ita2_get_impl_pmcs(pfmlib_regmask_t *impl_pmcs) { unsigned int i = 0; /* all pmcs are contiguous */ for(i=0; i < PMU_ITA2_NUM_PMCS; i++) pfm_regmask_set(impl_pmcs, i); } static void pfm_ita2_get_impl_pmds(pfmlib_regmask_t *impl_pmds) { unsigned int i = 0; /* all pmds are contiguous */ for(i=0; i < PMU_ITA2_NUM_PMDS; i++) pfm_regmask_set(impl_pmds, i); } static void pfm_ita2_get_impl_counters(pfmlib_regmask_t *impl_counters) { unsigned int i = 0; /* counting pmds are contiguous */ for(i=4; i < 8; i++) pfm_regmask_set(impl_counters, i); } static void pfm_ita2_get_hw_counter_width(unsigned int *width) { *width = PMU_ITA2_COUNTER_WIDTH; } static int pfm_ita2_get_event_description(unsigned int ev, char **str) { char *s; s = itanium2_pe[ev].pme_desc; if (s) { *str = strdup(s); } else { *str = NULL; } return PFMLIB_SUCCESS; } static int pfm_ita2_get_cycle_event(pfmlib_event_t *e) { e->event = PME_ITA2_CPU_CYCLES; return PFMLIB_SUCCESS; } static int pfm_ita2_get_inst_retired(pfmlib_event_t *e) { e->event = PME_ITA2_IA64_INST_RETIRED; return PFMLIB_SUCCESS; } pfm_pmu_support_t itanium2_support={ .pmu_name = "itanium2", .pmu_type = PFMLIB_ITANIUM2_PMU, .pme_count = PME_ITA2_EVENT_COUNT, .pmc_count = PMU_ITA2_NUM_PMCS, .pmd_count = PMU_ITA2_NUM_PMDS, .num_cnt = PMU_ITA2_NUM_COUNTERS, .get_event_code = pfm_ita2_get_event_code, .get_event_name = pfm_ita2_get_event_name, .get_event_counters = pfm_ita2_get_event_counters, .dispatch_events = pfm_ita2_dispatch_events, .pmu_detect = pfm_ita2_detect, .get_impl_pmcs = pfm_ita2_get_impl_pmcs, .get_impl_pmds = pfm_ita2_get_impl_pmds, .get_impl_counters = pfm_ita2_get_impl_counters, .get_hw_counter_width = pfm_ita2_get_hw_counter_width, .get_event_desc = pfm_ita2_get_event_description, .get_cycle_event = pfm_ita2_get_cycle_event, .get_inst_retired_event = pfm_ita2_get_inst_retired }; libpfm-4.9.0/lib/pfmlib_intel_skl.c0000664000175000017500000000765513223402656017062 0ustar eranianeranian/* * pfmlib_intel_skl.c : Intel Skylake core PMU * * Copyright (c) 2015 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_intel_x86_priv.h" #include "events/intel_skl_events.h" static const int skl_models[] = { 78, /* Skylake mobile */ 94, /* Skylake desktop */ 142,/* KabyLake mobile */ 158,/* KabyLake desktop */ 0 }; static const int skx_models[] = { 85, /* Skylake X */ 0 }; static int pfm_skl_init(void *this) { pfm_intel_x86_cfg.arch_version = 4; return PFM_SUCCESS; } pfmlib_pmu_t intel_skl_support={ .desc = "Intel Skylake", .name = "skl", .pmu = PFM_PMU_INTEL_SKL, .pme_count = LIBPFM_ARRAY_SIZE(intel_skl_pe), .type = PFM_PMU_TYPE_CORE, .supported_plm = INTEL_X86_PLM, .num_cntrs = 8, /* consider with HT off by default */ .num_fixed_cntrs = 3, .max_encoding = 2, /* offcore_response */ .pe = intel_skl_pe, .atdesc = intel_x86_mods, .flags = PFMLIB_PMU_FL_RAW_UMASK | INTEL_X86_PMU_FL_ECMASK, .cpu_family = 6, .cpu_models = skl_models, .pmu_detect = pfm_intel_x86_model_detect, .pmu_init = pfm_skl_init, .get_event_encoding[PFM_OS_NONE] = pfm_intel_x86_get_encoding, PFMLIB_ENCODE_PERF(pfm_intel_x86_get_perf_encoding), .get_event_first = pfm_intel_x86_get_event_first, .get_event_next = pfm_intel_x86_get_event_next, .event_is_valid = pfm_intel_x86_event_is_valid, .validate_table = pfm_intel_x86_validate_table, .get_event_info = pfm_intel_x86_get_event_info, .get_event_attr_info = pfm_intel_x86_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_intel_x86_perf_validate_pattrs), .get_event_nattrs = pfm_intel_x86_get_event_nattrs, .can_auto_encode = pfm_intel_x86_can_auto_encode, }; pfmlib_pmu_t intel_skx_support={ .desc = "Intel Skylake X", .name = "skx", .pmu = PFM_PMU_INTEL_SKX, .pme_count = LIBPFM_ARRAY_SIZE(intel_skl_pe), .type = PFM_PMU_TYPE_CORE, .supported_plm = INTEL_X86_PLM, .num_cntrs = 8, /* consider with HT off by default */ .num_fixed_cntrs = 3, .max_encoding = 2, /* offcore_response */ .pe = intel_skl_pe, .atdesc = intel_x86_mods, .flags = PFMLIB_PMU_FL_RAW_UMASK | INTEL_X86_PMU_FL_ECMASK, .cpu_family = 6, .cpu_models = skx_models, .pmu_detect = pfm_intel_x86_model_detect, .pmu_init = pfm_skl_init, .get_event_encoding[PFM_OS_NONE] = pfm_intel_x86_get_encoding, PFMLIB_ENCODE_PERF(pfm_intel_x86_get_perf_encoding), .get_event_first = pfm_intel_x86_get_event_first, .get_event_next = pfm_intel_x86_get_event_next, .event_is_valid = pfm_intel_x86_event_is_valid, .validate_table = pfm_intel_x86_validate_table, .get_event_info = pfm_intel_x86_get_event_info, .get_event_attr_info = pfm_intel_x86_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_intel_x86_perf_validate_pattrs), .get_event_nattrs = pfm_intel_x86_get_event_nattrs, .can_auto_encode = pfm_intel_x86_can_auto_encode, }; libpfm-4.9.0/lib/pfmlib_intel_netburst_priv.h0000664000175000017500000001621713223402656021176 0ustar eranianeranian/* * Copyright (c) 2006 IBM Corp. * Contributed by Kevin Corry * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * * pfmlib_netburst_priv.h * * Structures and definitions for use in the Pentium4/Xeon/EM64T libpfm code. */ #ifndef _PFMLIB_INTEL_NETBURST_PRIV_H_ #define _PFMLIB_INTEL_NETBURST_PRIV_H_ /* ESCR: Event Selection Control Register * * These registers are used to select which event to count along with options * for that event. There are (up to) 45 ESCRs, but each data counter is * restricted to a specific set of ESCRs. */ /** * netburst_escr_value_t * * Bit-wise breakdown of the ESCR registers. * * Bits Description * ------- ----------- * 63 - 31 Reserved * 30 - 25 Event Select * 24 - 9 Event Mask * 8 - 5 Tag Value * 4 Tag Enable * 3 T0 OS - Enable counting in kernel mode (thread 0) * 2 T0 USR - Enable counting in user mode (thread 0) * 1 T1 OS - Enable counting in kernel mode (thread 1) * 0 T1 USR - Enable counting in user mode (thread 1) **/ #define EVENT_MASK_BITS 16 #define EVENT_SELECT_BITS 6 typedef union { unsigned long long val; struct { unsigned long t1_usr:1; unsigned long t1_os:1; unsigned long t0_usr:1; unsigned long t0_os:1; unsigned long tag_enable:1; unsigned long tag_value:4; unsigned long event_mask:EVENT_MASK_BITS; unsigned long event_select:EVENT_SELECT_BITS; unsigned long reserved:1; } bits; } netburst_escr_value_t; /* CCCR: Counter Configuration Control Register * * These registers are used to configure the data counters. There are 18 * CCCRs, one for each data counter. */ /** * netburst_cccr_value_t * * Bit-wise breakdown of the CCCR registers. * * Bits Description * ------- ----------- * 63 - 32 Reserved * 31 OVF - The data counter overflowed. * 30 Cascade - Enable cascading of data counter when alternate * counter overflows. * 29 - 28 Reserved * 27 OVF_PMI_T1 - Generate interrupt for LP1 on counter overflow * 26 OVF_PMI_T0 - Generate interrupt for LP0 on counter overflow * 25 FORCE_OVF - Force interrupt on every counter increment * 24 Edge - Enable rising edge detection of the threshold comparison * output for filtering event counts. * 23 - 20 Threshold Value - Select the threshold value for comparing to * incoming event counts. * 19 Complement - Select how incoming event count is compared with * the threshold value. * 18 Compare - Enable filtering of event counts. * 17 - 16 Active Thread - Only used with HT enabled. * 00 - None: Count when neither LP is active. * 01 - Single: Count when only one LP is active. * 10 - Both: Count when both LPs are active. * 11 - Any: Count when either LP is active. * 15 - 13 ESCR Select - Select which ESCR to use for selecting the * event to count. * 12 Enable - Turns the data counter on or off. * 11 - 0 Reserved **/ typedef union { unsigned long long val; struct { unsigned long reserved1:12; unsigned long enable:1; unsigned long escr_select:3; unsigned long active_thread:2; unsigned long compare:1; unsigned long complement:1; unsigned long threshold:4; unsigned long edge:1; unsigned long force_ovf:1; unsigned long ovf_pmi_t0:1; unsigned long ovf_pmi_t1:1; unsigned long reserved2:2; unsigned long cascade:1; unsigned long overflow:1; } bits; } netburst_cccr_value_t; /** * netburst_event_mask_t * * Defines one bit of the event-mask for one Pentium4 event. * * @name: Event mask name * @desc: Event mask description * @bit: The bit position within the event_mask field. **/ typedef struct { const char *name; const char *desc; unsigned int bit; unsigned int flags; } netburst_event_mask_t; /* * netburst_event_mask_t->flags */ #define NETBURST_FL_DFL 0x1 /* event mask is default */ #define MAX_ESCRS_PER_EVENT 2 /* * These are the unique event codes used by perf_events. * The need to be encoded in the ESCR.event_select field when * programming for perf_events */ enum netburst_events { P4_EVENT_TC_DELIVER_MODE, P4_EVENT_BPU_FETCH_REQUEST, P4_EVENT_ITLB_REFERENCE, P4_EVENT_MEMORY_CANCEL, P4_EVENT_MEMORY_COMPLETE, P4_EVENT_LOAD_PORT_REPLAY, P4_EVENT_STORE_PORT_REPLAY, P4_EVENT_MOB_LOAD_REPLAY, P4_EVENT_PAGE_WALK_TYPE, P4_EVENT_BSQ_CACHE_REFERENCE, P4_EVENT_IOQ_ALLOCATION, P4_EVENT_IOQ_ACTIVE_ENTRIES, P4_EVENT_FSB_DATA_ACTIVITY, P4_EVENT_BSQ_ALLOCATION, P4_EVENT_BSQ_ACTIVE_ENTRIES, P4_EVENT_SSE_INPUT_ASSIST, P4_EVENT_PACKED_SP_UOP, P4_EVENT_PACKED_DP_UOP, P4_EVENT_SCALAR_SP_UOP, P4_EVENT_SCALAR_DP_UOP, P4_EVENT_64BIT_MMX_UOP, P4_EVENT_128BIT_MMX_UOP, P4_EVENT_X87_FP_UOP, P4_EVENT_TC_MISC, P4_EVENT_GLOBAL_POWER_EVENTS, P4_EVENT_TC_MS_XFER, P4_EVENT_UOP_QUEUE_WRITES, P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, P4_EVENT_RETIRED_BRANCH_TYPE, P4_EVENT_RESOURCE_STALL, P4_EVENT_WC_BUFFER, P4_EVENT_B2B_CYCLES, P4_EVENT_BNR, P4_EVENT_SNOOP, P4_EVENT_RESPONSE, P4_EVENT_FRONT_END_EVENT, P4_EVENT_EXECUTION_EVENT, P4_EVENT_REPLAY_EVENT, P4_EVENT_INSTR_RETIRED, P4_EVENT_UOPS_RETIRED, P4_EVENT_UOP_TYPE, P4_EVENT_BRANCH_RETIRED, P4_EVENT_MISPRED_BRANCH_RETIRED, P4_EVENT_X87_ASSIST, P4_EVENT_MACHINE_CLEAR, P4_EVENT_INSTR_COMPLETED, }; typedef struct { const char *name; const char *desc; unsigned int event_select; unsigned int escr_select; enum netburst_events perf_code; /* perf_event event code, enum P4_EVENTS */ int allowed_escrs[MAX_ESCRS_PER_EVENT]; netburst_event_mask_t event_masks[EVENT_MASK_BITS]; } netburst_entry_t; #define NETBURST_ATTR_U 0 #define NETBURST_ATTR_K 1 #define NETBURST_ATTR_C 2 #define NETBURST_ATTR_E 3 #define NETBURST_ATTR_T 4 #define _NETBURST_ATTR_U (1 << NETBURST_ATTR_U) #define _NETBURST_ATTR_K (1 << NETBURST_ATTR_K) #define P4_REPLAY_REAL_MASK 0x00000003 extern int pfm_netburst_get_encoding(void *this, pfmlib_event_desc_t *e); extern int pfm_netburst_get_perf_encoding(void *this, pfmlib_event_desc_t *e); extern void pfm_netburst_perf_validate_pattrs(void *this, pfmlib_event_desc_t *e); #endif libpfm-4.9.0/lib/pfmlib_arm_armv7_pmuv1.c0000664000175000017500000001661413223402656020114 0ustar eranianeranian/* * pfmlib_arm_armv7_pmuv1.c : support for ARMV7 chips * * Copyright (c) 2010 University of Tennessee * Contributed by Vince Weaver * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ #include #include #include #include #include /* private headers */ #include "pfmlib_priv.h" /* library private */ #include "pfmlib_arm_priv.h" #include "events/arm_cortex_a7_events.h" /* event tables */ #include "events/arm_cortex_a8_events.h" #include "events/arm_cortex_a9_events.h" #include "events/arm_cortex_a15_events.h" #include "events/arm_qcom_krait_events.h" static int pfm_arm_detect_cortex_a7(void *this) { int ret; ret = pfm_arm_detect(this); if (ret != PFM_SUCCESS) return PFM_ERR_NOTSUPP; if ((pfm_arm_cfg.implementer == 0x41) && /* ARM */ (pfm_arm_cfg.part == 0xc07)) { /* Cortex-A7 */ return PFM_SUCCESS; } return PFM_ERR_NOTSUPP; } static int pfm_arm_detect_cortex_a8(void *this) { int ret; ret = pfm_arm_detect(this); if (ret != PFM_SUCCESS) return PFM_ERR_NOTSUPP; if ((pfm_arm_cfg.implementer == 0x41) && /* ARM */ (pfm_arm_cfg.part == 0xc08)) { /* Cortex-A8 */ return PFM_SUCCESS; } return PFM_ERR_NOTSUPP; } static int pfm_arm_detect_cortex_a9(void *this) { int ret; ret = pfm_arm_detect(this); if (ret != PFM_SUCCESS) return PFM_ERR_NOTSUPP; if ((pfm_arm_cfg.implementer == 0x41) && /* ARM */ (pfm_arm_cfg.part==0xc09)) { /* Cortex-A8 */ return PFM_SUCCESS; } return PFM_ERR_NOTSUPP; } static int pfm_arm_detect_cortex_a15(void *this) { int ret; ret = pfm_arm_detect(this); if (ret != PFM_SUCCESS) return PFM_ERR_NOTSUPP; if ((pfm_arm_cfg.implementer == 0x41) && /* ARM */ (pfm_arm_cfg.part==0xc0f)) { /* Cortex-A15 */ return PFM_SUCCESS; } return PFM_ERR_NOTSUPP; } static int pfm_arm_detect_krait(void *this) { int ret; ret = pfm_arm_detect(this); if (ret != PFM_SUCCESS) return PFM_ERR_NOTSUPP; /* Check for Qualcomm */ if (pfm_arm_cfg.implementer == 0x51) { /* Check that [15:10] of midr is 0x01 which */ /* indicates Krait rather than Scorpion CPU */ /* pfm_arm_cfg.part is (midr>>4)&0xfff */ if (pfm_arm_cfg.part >> 6 == 0x1) { return PFM_SUCCESS; } } return PFM_ERR_NOTSUPP; } /* Cortex A7 support */ pfmlib_pmu_t arm_cortex_a7_support={ .desc = "ARM Cortex A7", .name = "arm_ac7", .pmu = PFM_PMU_ARM_CORTEX_A7, .pme_count = LIBPFM_ARRAY_SIZE(arm_cortex_a7_pe), .type = PFM_PMU_TYPE_CORE, .pe = arm_cortex_a7_pe, .pmu_detect = pfm_arm_detect_cortex_a7, .max_encoding = 1, .num_cntrs = 4, .supported_plm = ARMV7_A7_PLM, .get_event_encoding[PFM_OS_NONE] = pfm_arm_get_encoding, PFMLIB_ENCODE_PERF(pfm_arm_get_perf_encoding), .get_event_first = pfm_arm_get_event_first, .get_event_next = pfm_arm_get_event_next, .event_is_valid = pfm_arm_event_is_valid, .validate_table = pfm_arm_validate_table, .get_event_info = pfm_arm_get_event_info, .get_event_attr_info = pfm_arm_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_arm_perf_validate_pattrs), .get_event_nattrs = pfm_arm_get_event_nattrs, }; /* Cortex A8 support */ pfmlib_pmu_t arm_cortex_a8_support={ .desc = "ARM Cortex A8", .name = "arm_ac8", .pmu = PFM_PMU_ARM_CORTEX_A8, .pme_count = LIBPFM_ARRAY_SIZE(arm_cortex_a8_pe), .type = PFM_PMU_TYPE_CORE, .pe = arm_cortex_a8_pe, .pmu_detect = pfm_arm_detect_cortex_a8, .max_encoding = 1, .num_cntrs = 2, .get_event_encoding[PFM_OS_NONE] = pfm_arm_get_encoding, PFMLIB_ENCODE_PERF(pfm_arm_get_perf_encoding), .get_event_first = pfm_arm_get_event_first, .get_event_next = pfm_arm_get_event_next, .event_is_valid = pfm_arm_event_is_valid, .validate_table = pfm_arm_validate_table, .get_event_info = pfm_arm_get_event_info, .get_event_attr_info = pfm_arm_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_arm_perf_validate_pattrs), .get_event_nattrs = pfm_arm_get_event_nattrs, }; /* Cortex A9 support */ pfmlib_pmu_t arm_cortex_a9_support={ .desc = "ARM Cortex A9", .name = "arm_ac9", .pmu = PFM_PMU_ARM_CORTEX_A9, .pme_count = LIBPFM_ARRAY_SIZE(arm_cortex_a9_pe), .type = PFM_PMU_TYPE_CORE, .pe = arm_cortex_a9_pe, .pmu_detect = pfm_arm_detect_cortex_a9, .max_encoding = 1, .num_cntrs = 2, .get_event_encoding[PFM_OS_NONE] = pfm_arm_get_encoding, PFMLIB_ENCODE_PERF(pfm_arm_get_perf_encoding), .get_event_first = pfm_arm_get_event_first, .get_event_next = pfm_arm_get_event_next, .event_is_valid = pfm_arm_event_is_valid, .validate_table = pfm_arm_validate_table, .get_event_info = pfm_arm_get_event_info, .get_event_attr_info = pfm_arm_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_arm_perf_validate_pattrs), .get_event_nattrs = pfm_arm_get_event_nattrs, }; /* Cortex A15 support */ pfmlib_pmu_t arm_cortex_a15_support={ .desc = "ARM Cortex A15", .name = "arm_ac15", .pmu = PFM_PMU_ARM_CORTEX_A15, .pme_count = LIBPFM_ARRAY_SIZE(arm_cortex_a15_pe), .type = PFM_PMU_TYPE_CORE, .pe = arm_cortex_a15_pe, .pmu_detect = pfm_arm_detect_cortex_a15, .max_encoding = 1, .num_cntrs = 6, .supported_plm = ARMV7_A15_PLM, .get_event_encoding[PFM_OS_NONE] = pfm_arm_get_encoding, PFMLIB_ENCODE_PERF(pfm_arm_get_perf_encoding), .get_event_first = pfm_arm_get_event_first, .get_event_next = pfm_arm_get_event_next, .event_is_valid = pfm_arm_event_is_valid, .validate_table = pfm_arm_validate_table, .get_event_info = pfm_arm_get_event_info, .get_event_attr_info = pfm_arm_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_arm_perf_validate_pattrs), .get_event_nattrs = pfm_arm_get_event_nattrs, }; /* Qualcomm Krait support */ pfmlib_pmu_t arm_qcom_krait_support={ .desc = "ARM Qualcomm Krait", .name = "qcom_krait", .pmu = PFM_PMU_ARM_QCOM_KRAIT, .pme_count = LIBPFM_ARRAY_SIZE(arm_qcom_krait_pe), .type = PFM_PMU_TYPE_CORE, .pe = arm_qcom_krait_pe, .pmu_detect = pfm_arm_detect_krait, .max_encoding = 1, .num_cntrs = 5, .supported_plm = ARMV7_A15_PLM, .get_event_encoding[PFM_OS_NONE] = pfm_arm_get_encoding, PFMLIB_ENCODE_PERF(pfm_arm_get_perf_encoding), .get_event_first = pfm_arm_get_event_first, .get_event_next = pfm_arm_get_event_next, .event_is_valid = pfm_arm_event_is_valid, .validate_table = pfm_arm_validate_table, .get_event_info = pfm_arm_get_event_info, .get_event_attr_info = pfm_arm_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_arm_perf_validate_pattrs), .get_event_nattrs = pfm_arm_get_event_nattrs, }; libpfm-4.9.0/lib/pfmlib_intel_knl_unc_cha.c0000664000175000017500000000665013223402656020527 0ustar eranianeranian/* * pfmlib_intel_knl_unc_cha.c : Intel KnightsLanding CHA uncore PMU * * Copyright (c) 2016 Intel Corp. All rights reserved * Contributed by Peinan Zhang * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_intel_x86_priv.h" #include "pfmlib_intel_snbep_unc_priv.h" #include "events/intel_knl_unc_cha_events.h" #define DEFINE_CHA_BOX(n) \ pfmlib_pmu_t intel_knl_unc_cha##n##_support = { \ .desc = "Intel KnightLanding CHA "#n" uncore", \ .name = "knl_unc_cha"#n, \ .perf_name = "uncore_cha_"#n, \ .pmu = PFM_PMU_INTEL_KNL_UNC_CHA##n, \ .pme_count = LIBPFM_ARRAY_SIZE(intel_knl_unc_cha_pe), \ .type = PFM_PMU_TYPE_UNCORE, \ .num_cntrs = 4, \ .num_fixed_cntrs = 0, \ .max_encoding = 1, \ .pe = intel_knl_unc_cha_pe, \ .atdesc = snbep_unc_mods, \ .flags = PFMLIB_PMU_FL_RAW_UMASK, \ .pmu_detect = pfm_intel_knl_unc_detect, \ .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding, \ PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding), \ PFMLIB_OS_DETECT(pfm_intel_x86_perf_detect), \ .get_event_first = pfm_intel_x86_get_event_first, \ .get_event_next = pfm_intel_x86_get_event_next, \ .event_is_valid = pfm_intel_x86_event_is_valid, \ .validate_table = pfm_intel_x86_validate_table, \ .get_event_info = pfm_intel_x86_get_event_info, \ .get_event_attr_info = pfm_intel_x86_get_event_attr_info, \ PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs), \ .get_event_nattrs = pfm_intel_x86_get_event_nattrs, \ }; DEFINE_CHA_BOX(0); DEFINE_CHA_BOX(1); DEFINE_CHA_BOX(2); DEFINE_CHA_BOX(3); DEFINE_CHA_BOX(4); DEFINE_CHA_BOX(5); DEFINE_CHA_BOX(6); DEFINE_CHA_BOX(7); DEFINE_CHA_BOX(8); DEFINE_CHA_BOX(9); DEFINE_CHA_BOX(10); DEFINE_CHA_BOX(11); DEFINE_CHA_BOX(12); DEFINE_CHA_BOX(13); DEFINE_CHA_BOX(14); DEFINE_CHA_BOX(15); DEFINE_CHA_BOX(16); DEFINE_CHA_BOX(17); DEFINE_CHA_BOX(18); DEFINE_CHA_BOX(19); DEFINE_CHA_BOX(20); DEFINE_CHA_BOX(21); DEFINE_CHA_BOX(22); DEFINE_CHA_BOX(23); DEFINE_CHA_BOX(24); DEFINE_CHA_BOX(25); DEFINE_CHA_BOX(26); DEFINE_CHA_BOX(27); DEFINE_CHA_BOX(28); DEFINE_CHA_BOX(29); DEFINE_CHA_BOX(30); DEFINE_CHA_BOX(31); DEFINE_CHA_BOX(32); DEFINE_CHA_BOX(33); DEFINE_CHA_BOX(34); DEFINE_CHA_BOX(35); DEFINE_CHA_BOX(36); DEFINE_CHA_BOX(37); libpfm-4.9.0/lib/pfmlib_power_priv.h0000664000175000017500000000733313223402656017270 0ustar eranianeranian/****************************/ /* THIS IS OPEN SOURCE CODE */ /****************************/ #ifndef __PFMLIB_POWER_PRIV_H__ #define __PFMLIB_POWER_PRIV_H__ /* * File: pfmlib_power_priv.h * CVS: * Author: Corey Ashford * cjashfor@us.ibm.com * Mods: * * * (C) Copyright IBM Corporation, 2009. All Rights Reserved. * Contributed by Corey Ashford * */ typedef struct { uint64_t pme_code; const char *pme_name; const char *pme_short_desc; const char *pme_long_desc; } pme_power_entry_t; typedef struct { const char *pme_name; const char *pme_desc; unsigned pme_code; uint64_t pme_modmsk; } pme_torrent_entry_t; /* Attribute "type "for PowerBus MCD events */ #define TORRENT_ATTR_MCD_TYPE 0 /* Attribute "sel" for PowerBus bus utilization events */ #define TORRENT_ATTR_UTIL_SEL 1 /* Attribute "lo_cmp" for PowerBus utilization events */ #define TORRENT_ATTR_UTIL_LO_CMP 2 /* Attribute "hi_cmp" for PowerBus utilization events */ #define TORRENT_ATTR_UTIL_HI_CMP 3 #define _TORRENT_ATTR_MCD_TYPE (1 << TORRENT_ATTR_MCD_TYPE) #define _TORRENT_ATTR_MCD (_TORRENT_ATTR_MCD_TYPE) #define _TORRENT_ATTR_UTIL_SEL (1 << TORRENT_ATTR_UTIL_SEL) #define _TORRENT_ATTR_UTIL_LO_CMP (1 << TORRENT_ATTR_UTIL_LO_CMP) #define _TORRENT_ATTR_UTIL_HI_CMP (1 << TORRENT_ATTR_UTIL_HI_CMP) #define _TORRENT_ATTR_UTIL_LO (_TORRENT_ATTR_UTIL_SEL | \ _TORRENT_ATTR_UTIL_LO_CMP) #define _TORRENT_ATTR_UTIL_HI (_TORRENT_ATTR_UTIL_SEL | \ _TORRENT_ATTR_UTIL_HI_CMP) /* * These definitions were taken from the reg.h file which, until Linux * 2.6.18, resided in /usr/include/asm-ppc64. Most of the unneeded * definitions have been removed, but there are still a few in this file * that are currently unused by libpfm. */ #ifndef _POWER_REG_H #define _POWER_REG_H #define __stringify_1(x) #x #define __stringify(x) __stringify_1(x) #ifdef __powerpc__ #define mfspr(rn) ({unsigned long rval; \ asm volatile("mfspr %0," __stringify(rn) \ : "=r" (rval)); rval;}) #else #define mfspr(rn) (0) #endif /* Special Purpose Registers (SPRNs)*/ #define SPRN_PVR 0x11F /* Processor Version Register */ /* Processor Version Register (PVR) field extraction */ #define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */ #define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revision field */ #define __is_processor(pv) (PVR_VER(mfspr(SPRN_PVR)) == (pv)) /* 64-bit processors */ #define PV_POWER4 0x0035 #define PV_POWER4p 0x0038 #define PV_970 0x0039 #define PV_POWER5 0x003A #define PV_POWER5p 0x003B #define PV_970FX 0x003C #define PV_POWER6 0x003E #define PV_POWER7 0x003F #define PV_POWER7p 0x004a #define PV_970MP 0x0044 #define PV_970GX 0x0045 #define PV_POWER8E 0x004b #define PV_POWER8NVL 0x004c #define PV_POWER8 0x004d #define PV_POWER9 0x004e #define POWER_PLM (PFM_PLM0|PFM_PLM3) #define POWER8_PLM (POWER_PLM|PFM_PLMH) #define POWER9_PLM (POWER_PLM|PFM_PLMH) extern int pfm_gen_powerpc_get_event_info(void *this, int pidx, pfm_event_info_t *info); extern int pfm_gen_powerpc_get_event_attr_info(void *this, int pidx, int umask_idx, pfmlib_event_attr_info_t *info); extern int pfm_gen_powerpc_get_encoding(void *this, pfmlib_event_desc_t *e); extern int pfm_gen_powerpc_get_event_first(void *this); extern int pfm_gen_powerpc_get_event_next(void *this, int idx); extern int pfm_gen_powerpc_event_is_valid(void *this, int pidx); extern int pfm_gen_powerpc_validate_table(void *this, FILE *fp); extern void pfm_gen_powerpc_perf_validate_pattrs(void *this, pfmlib_event_desc_t *e); extern int pfm_gen_powerpc_get_perf_encoding(void *this, pfmlib_event_desc_t *e); extern int pfm_gen_powerpc_get_nest_perf_encoding(void *this, pfmlib_event_desc_t *e); #endif /* _POWER_REG_H */ #endif libpfm-4.9.0/lib/pfmlib_intel_ivbep_unc_ha.c0000664000175000017500000000670513223402656020706 0ustar eranianeranian/* * pfmlib_intel_ivbep_unc_ha.c : Intel IvyBridge-EP Home Agent (HA) uncore PMU * * Copyright (c) 2014 Google Inc. All rights reserved * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_intel_x86_priv.h" #include "pfmlib_intel_snbep_unc_priv.h" #include "events/intel_ivbep_unc_ha_events.h" static void display_ha(void *this, pfmlib_event_desc_t *e, void *val) { const intel_x86_entry_t *pe = this_pe(this); pfm_snbep_unc_reg_t *reg = val; pfm_snbep_unc_reg_t f; __pfm_vbprintf("[UNC_HA=0x%"PRIx64" event=0x%x umask=0x%x en=%d " "inv=%d edge=%d thres=%d] %s\n", reg->val, reg->com.unc_event, reg->com.unc_umask, reg->com.unc_en, reg->com.unc_inv, reg->com.unc_edge, reg->com.unc_thres, pe[e->event].name); if (e->count == 1) return; f.val = e->codes[1]; __pfm_vbprintf("[UNC_HA_ADDR=0x%"PRIx64" lo_addr=0x%x hi_addr=0x%x]\n", f.val, f.ha_addr.lo_addr, f.ha_addr.hi_addr); f.val = e->codes[2]; __pfm_vbprintf("[UNC_HA_OPC=0x%"PRIx64" opc=0x%x]\n", f.val, f.ha_opc.opc); } #define DEFINE_HA_BOX(n) \ pfmlib_pmu_t intel_ivbep_unc_ha##n##_support = {\ .desc = "Intel Ivy Bridge-EP HA "#n" uncore",\ .name = "ivbep_unc_ha"#n,\ .perf_name = "uncore_ha_"#n,\ .pmu = PFM_PMU_INTEL_IVBEP_UNC_HA##n,\ .pme_count = LIBPFM_ARRAY_SIZE(intel_ivbep_unc_h_pe),\ .type = PFM_PMU_TYPE_UNCORE,\ .num_cntrs = 4,\ .num_fixed_cntrs = 0,\ .max_encoding = 3, /* address matchers */\ .pe = intel_ivbep_unc_h_pe,\ .atdesc = snbep_unc_mods,\ .flags = PFMLIB_PMU_FL_RAW_UMASK,\ .pmu_detect = pfm_intel_ivbep_unc_detect,\ .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding,\ PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding),\ PFMLIB_OS_DETECT(pfm_intel_x86_perf_detect), \ .get_event_first = pfm_intel_x86_get_event_first,\ .get_event_next = pfm_intel_x86_get_event_next,\ .event_is_valid = pfm_intel_x86_event_is_valid,\ .validate_table = pfm_intel_x86_validate_table,\ .get_event_info = pfm_intel_x86_get_event_info,\ .get_event_attr_info = pfm_intel_x86_get_event_attr_info,\ PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs),\ .get_event_nattrs = pfm_intel_x86_get_event_nattrs,\ .display_reg = display_ha,\ } DEFINE_HA_BOX(0); DEFINE_HA_BOX(1); libpfm-4.9.0/lib/pfmlib_amd64_k7.c0000664000175000017500000000434013223402656016376 0ustar eranianeranian/* * pfmlib_amd64_k7.c : AMD64 K7 * * Copyright (c) 2010 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_amd64_priv.h" #include "events/amd64_events_k7.h" pfmlib_pmu_t amd64_k7_support={ .desc = "AMD64 K7", .name = "amd64_k7", .pmu = PFM_PMU_AMD64_K7, .pmu_rev = AMD64_K7, .pme_count = LIBPFM_ARRAY_SIZE(amd64_k7_pe), .type = PFM_PMU_TYPE_CORE, .supported_plm = AMD64_K7_PLM, .num_cntrs = 4, .max_encoding = 1, .pe = amd64_k7_pe, .atdesc = amd64_mods, .flags = PFMLIB_PMU_FL_RAW_UMASK, .cpu_family = PFM_PMU_AMD64_K7, .pmu_detect = pfm_amd64_family_detect, .get_event_encoding[PFM_OS_NONE] = pfm_amd64_get_encoding, PFMLIB_ENCODE_PERF(pfm_amd64_get_perf_encoding), .get_event_first = pfm_amd64_get_event_first, .get_event_next = pfm_amd64_get_event_next, .event_is_valid = pfm_amd64_event_is_valid, .validate_table = pfm_amd64_validate_table, .get_event_info = pfm_amd64_get_event_info, .get_event_attr_info = pfm_amd64_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_amd64_perf_validate_pattrs), .get_event_nattrs = pfm_amd64_get_event_nattrs, }; libpfm-4.9.0/lib/pfmlib_mips_priv.h0000664000175000017500000001021413223402656017074 0ustar eranianeranian/* * Copyright (c) 2011 Samara Technology Group, Inc * Contributed by Philip Mucci * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. */ #ifndef __PFMLIB_MIPS_PRIV_H__ #define __PFMLIB_MIPS_PRIV_H__ /* * This file contains the definitions used for MIPS processors */ /* * event description */ typedef struct { const char *name; /* event name */ const char *desc; /* event description */ unsigned int mask; /* which counters event lives on */ unsigned int code; /* event code */ } mips_entry_t; #if __BYTE_ORDER == __LITTLE_ENDIAN typedef union { uint64_t val; /* complete register value */ struct { unsigned long sel_exl:1; /* int level */ unsigned long sel_os:1; /* system level */ unsigned long sel_sup:1; /* supervisor level */ unsigned long sel_usr:1; /* user level */ unsigned long sel_int:1; /* enable intr */ unsigned long sel_event_mask:7; /* event mask */ unsigned long sel_res1:20; /* reserved */ unsigned long sel_res2:32; /* reserved */ } perfsel64; } pfm_mips_sel_reg_t; #elif __BYTE_ORDER == __BIG_ENDIAN typedef union { uint64_t val; /* complete register value */ struct { unsigned long sel_res2:32; /* reserved */ unsigned long sel_res1:20; /* reserved */ unsigned long sel_event_mask:7; /* event mask */ unsigned long sel_int:1; /* enable intr */ unsigned long sel_usr:1; /* user level */ unsigned long sel_sup:1; /* supervisor level */ unsigned long sel_os:1; /* system level */ unsigned long sel_exl:1; /* int level */ } perfsel64; } pfm_mips_sel_reg_t; #else #error "cannot determine endianess" #endif typedef struct { char model[1024]; int implementer; int architecture; int part; } pfm_mips_config_t; extern pfm_mips_config_t pfm_mips_cfg; #define MIPS_ATTR_K 0 /* system level */ #define MIPS_ATTR_U 1 /* user level */ #define MIPS_ATTR_S 2 /* supervisor level */ #define MIPS_ATTR_E 3 /* exception level */ #define MIPS_NUM_ATTRS 4 #define _MIPS_ATTR_K (1 << MIPS_ATTR_K) #define _MIPS_ATTR_U (1 << MIPS_ATTR_U) #define _MIPS_ATTR_S (1 << MIPS_ATTR_S) #define _MIPS_ATTR_E (1 << MIPS_ATTR_E) #define MIPS_PLM_ALL ( _MIPS_ATTR_K |\ _MIPS_ATTR_U |\ _MIPS_ATTR_S |\ _MIPS_ATTR_E) extern int pfm_mips_detect(void *this); extern int pfm_mips_get_encoding(void *this, pfmlib_event_desc_t *e); extern int pfm_mips_get_event_first(void *this); extern int pfm_mips_get_event_next(void *this, int idx); extern int pfm_mips_event_is_valid(void *this, int pidx); extern int pfm_mips_validate_table(void *this, FILE *fp); extern int pfm_mips_get_event_attr_info(void *this, int pidx, int attr_idx, pfmlib_event_attr_info_t *info); extern int pfm_mips_get_event_info(void *this, int idx, pfm_event_info_t *info); extern unsigned int pfm_mips_get_event_nattrs(void *this, int pidx); extern void pfm_mips_perf_validate_pattrs(void *this, pfmlib_event_desc_t *e); extern int pfm_mips_get_perf_encoding(void *this, pfmlib_event_desc_t *e); #endif /* __PFMLIB_MIPS_PRIV_H__ */ libpfm-4.9.0/lib/pfmlib_perf_event_priv.h0000664000175000017500000000463113223402656020267 0ustar eranianeranian/* * pfmlib_perf_events_priv.h: perf_event public attributes * * Copyright (c) 2011 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef __PERF_EVENT_PRIV_H__ #define __PERF_EVENT_PRIV_H__ #include "pfmlib_priv.h" #include "perfmon/pfmlib_perf_event.h" #define PERF_ATTR_U 0 /* monitor at user privilege levels */ #define PERF_ATTR_K 1 /* monitor at kernel privilege levels */ #define PERF_ATTR_H 2 /* monitor at hypervisor levels */ #define PERF_ATTR_PE 3 /* sampling period */ #define PERF_ATTR_FR 4 /* average target sampling rate */ #define PERF_ATTR_PR 5 /* precise sampling mode */ #define PERF_ATTR_EX 6 /* exclusive event */ #define PERF_ATTR_MG 7 /* monitor guest execution */ #define PERF_ATTR_MH 8 /* monitor host execution */ #define PERF_ATTR_CPU 9 /* CPU to program */ #define PERF_ATTR_PIN 10 /* pin event to CPU */ #define _PERF_ATTR_U (1 << PERF_ATTR_U) #define _PERF_ATTR_K (1 << PERF_ATTR_K) #define _PERF_ATTR_H (1 << PERF_ATTR_H) #define _PERF_ATTR_PE (1 << PERF_ATTR_PE) #define _PERF_ATTR_FR (1 << PERF_ATTR_FR) #define _PERF_ATTR_PR (1 << PERF_ATTR_PR) #define _PERF_ATTR_EX (1 << PERF_ATTR_EX) #define _PERF_ATTR_MG (1 << PERF_ATTR_MG) #define _PERF_ATTR_MH (1 << PERF_ATTR_MH) #define _PERF_ATTR_CPU (1 << PERF_ATTR_CPU) #define _PERF_ATTR_PIN (1 << PERF_ATTR_PIN) #define PERF_PLM_ALL (PFM_PLM0|PFM_PLM3|PFM_PLMH) #endif libpfm-4.9.0/lib/pfmlib_montecito.c0000664000175000017500000021172613223402656017073 0ustar eranianeranian/* * pfmlib_montecito.c : support for the Dual-Core Itanium2 processor * * Copyright (c) 2005-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include /* public headers */ #include /* private headers */ #include "pfmlib_priv.h" /* library private */ #include "pfmlib_priv_ia64.h" /* architecture private */ #include "pfmlib_montecito_priv.h" /* PMU private */ #include "montecito_events.h" /* PMU private */ #define is_ear(i) event_is_ear(montecito_pe+(i)) #define is_ear_tlb(i) event_is_ear_tlb(montecito_pe+(i)) #define is_ear_alat(i) event_is_ear_alat(montecito_pe+(i)) #define is_ear_cache(i) event_is_ear_cache(montecito_pe+(i)) #define is_iear(i) event_is_iear(montecito_pe+(i)) #define is_dear(i) event_is_dear(montecito_pe+(i)) #define is_etb(i) event_is_etb(montecito_pe+(i)) #define has_opcm(i) event_opcm_ok(montecito_pe+(i)) #define has_iarr(i) event_iarr_ok(montecito_pe+(i)) #define has_darr(i) event_darr_ok(montecito_pe+(i)) #define has_all(i) event_all_ok(montecito_pe+(i)) #define has_mesi(i) event_mesi_ok(montecito_pe+(i)) #define evt_use_opcm(e) ((e)->pfp_mont_opcm1.opcm_used != 0 || (e)->pfp_mont_opcm2.opcm_used !=0) #define evt_use_irange(e) ((e)->pfp_mont_irange.rr_used) #define evt_use_drange(e) ((e)->pfp_mont_drange.rr_used) #define evt_grp(e) (int)montecito_pe[e].pme_qualifiers.pme_qual.pme_group #define evt_set(e) (int)montecito_pe[e].pme_qualifiers.pme_qual.pme_set #define evt_umask(e) montecito_pe[e].pme_umask #define evt_type(e) (int)montecito_pe[e].pme_type #define evt_caf(e) (int)montecito_pe[e].pme_caf #define FINE_MODE_BOUNDARY_BITS 16 #define FINE_MODE_MASK ~((1U< PMC0 * 1 -> PMC1 * n -> PMCn * * The following are in the model specific rr_br[]: * IBR0 -> 0 * IBR1 -> 1 * ... * IBR7 -> 7 * DBR0 -> 0 * DBR1 -> 1 * ... * DBR7 -> 7 * * We do not use a mapping table, instead we make up the * values on the fly given the base. */ static int pfm_mont_detect(void) { int tmp; int ret = PFMLIB_ERR_NOTSUPP; tmp = pfm_ia64_get_cpu_family(); if (tmp == 0x20) { ret = PFMLIB_SUCCESS; } return ret; } /* * Check the event for incompatibilities. This is useful * for L1D and L2D related events. Due to wire limitations, * some caches events are separated into sets. There * are 6 sets for the L1D cache group and 8 sets for L2D group. * It is NOT possible to simultaneously measure events from * differents sets for L1D. For instance, you cannot * measure events from set0 and set1 in L1D cache group. The L2D * group allows up to two different sets to be active at the same * time. The first set is selected by the event in PMC4 and the second * set by the event in PMC6. Once the set is selected for PMC4, * the same set is locked for PMC5 and PMC8. Similarly, once the * set is selected for PMC6, the same set is locked for PMC7 and * PMC9. * * This function verifies that only one set of L1D is selected * and that no more than 2 sets are selected for L2D */ static int check_cross_groups(pfmlib_input_param_t *inp, unsigned int *l1d_event, unsigned long *l2d_set1_mask, unsigned long *l2d_set2_mask) { int g, s, s1, s2; unsigned int cnt = inp->pfp_event_count; pfmlib_event_t *e = inp->pfp_events; unsigned int i, j; unsigned long l2d_mask1 = 0, l2d_mask2 = 0; unsigned int l1d_event_idx = UNEXISTING_SET; /* * Let check the L1D constraint first * * There is no umask restriction for this group */ for (i=0; i < cnt; i++) { g = evt_grp(e[i].event); s = evt_set(e[i].event); if (g != PFMLIB_MONT_EVT_L1D_CACHE_GRP) continue; DPRINT("i=%u g=%d s=%d\n", i, g, s); l1d_event_idx = i; for (j=i+1; j < cnt; j++) { if (evt_grp(e[j].event) != g) continue; /* * if there is another event from the same group * but with a different set, then we return an error */ if (evt_set(e[j].event) != s) return PFMLIB_ERR_EVTSET; } } /* * Check that we have only up to two distinct * sets for L2D */ s1 = s2 = -1; for (i=0; i < cnt; i++) { g = evt_grp(e[i].event); if (g != PFMLIB_MONT_EVT_L2D_CACHE_GRP) continue; s = evt_set(e[i].event); /* * we have seen this set before, continue */ if (s1 == s) { l2d_mask1 |= 1UL << i; continue; } if (s2 == s) { l2d_mask2 |= 1UL << i; continue; } /* * record first of second set seen */ if (s1 == -1) { s1 = s; l2d_mask1 |= 1UL << i; } else if (s2 == -1) { s2 = s; l2d_mask2 |= 1UL << i; } else { /* * found a third set, that's not possible */ return PFMLIB_ERR_EVTSET; } } *l1d_event = l1d_event_idx; *l2d_set1_mask = l2d_mask1; *l2d_set2_mask = l2d_mask2; return PFMLIB_SUCCESS; } /* * Certain prefetch events must be treated specially when instruction range restriction * is used because they can only be constrained by IBRP1 in fine-mode. Other events * will use IBRP0 if tagged as a demand fetch OR IBPR1 if tagged as a prefetch match. * * Events which can be qualified by the two pairs depending on their tag: * - ISB_BUNPAIRS_IN * - L1I_FETCH_RAB_HIT * - L1I_FETCH_ISB_HIT * - L1I_FILLS * * This function returns the number of qualifying prefetch events found */ static int prefetch_events[]={ PME_MONT_L1I_PREFETCHES, PME_MONT_L1I_STRM_PREFETCHES, PME_MONT_L2I_PREFETCHES }; #define NPREFETCH_EVENTS sizeof(prefetch_events)/sizeof(int) static int prefetch_dual_events[]= { PME_MONT_ISB_BUNPAIRS_IN, PME_MONT_L1I_FETCH_RAB_HIT, PME_MONT_L1I_FETCH_ISB_HIT, PME_MONT_L1I_FILLS }; #define NPREFETCH_DUAL_EVENTS sizeof(prefetch_dual_events)/sizeof(int) /* * prefetch events must use IBRP1, unless they are dual and the user specified * PFMLIB_MONT_IRR_DEMAND_FETCH in rr_flags */ static int check_prefetch_events(pfmlib_input_param_t *inp, pfmlib_mont_input_rr_t *irr, unsigned int *count, int *base_idx, int *dup) { int code; int prefetch_codes[NPREFETCH_EVENTS]; int prefetch_dual_codes[NPREFETCH_DUAL_EVENTS]; unsigned int i, j; int c, flags; int found = 0, found_ibrp0 = 0, found_ibrp1 = 0; flags = irr->rr_flags & (PFMLIB_MONT_IRR_DEMAND_FETCH|PFMLIB_MONT_IRR_PREFETCH_MATCH); for(i=0; i < NPREFETCH_EVENTS; i++) { pfm_get_event_code(prefetch_events[i], &code); prefetch_codes[i] = code; } for(i=0; i < NPREFETCH_DUAL_EVENTS; i++) { pfm_get_event_code(prefetch_dual_events[i], &code); prefetch_dual_codes[i] = code; } for(i=0; i < inp->pfp_event_count; i++) { pfm_get_event_code(inp->pfp_events[i].event, &c); for(j=0; j < NPREFETCH_EVENTS; j++) { if (c == prefetch_codes[j]) { found++; found_ibrp1++; } } /* * for the dual events, users must specify one or both of the * PFMLIB_MONT_IRR_DEMAND_FETCH or PFMLIB_MONT_IRR_PREFETCH_MATCH */ for(j=0; j < NPREFETCH_DUAL_EVENTS; j++) { if (c == prefetch_dual_codes[j]) { found++; if (flags == 0) return PFMLIB_ERR_IRRFLAGS; if (flags & PFMLIB_MONT_IRR_DEMAND_FETCH) found_ibrp0++; if (flags & PFMLIB_MONT_IRR_PREFETCH_MATCH) found_ibrp1++; } } } *count = found; *dup = 0; /* * if both found_ibrp0 and found_ibrp1 > 0, then we need to duplicate * the range in ibrp0 to ibrp1. */ if (found) { *base_idx = found_ibrp0 ? 0 : 2; if (found_ibrp1 && found_ibrp0) *dup = 1; } return 0; } /* * look for CPU_OP_CYCLES_QUAL * Return: * 1 if found * 0 otherwise */ static int has_cpu_cycles_qual(pfmlib_input_param_t *inp) { unsigned int i; int code, c; pfm_get_event_code(PME_MONT_CPU_OP_CYCLES_QUAL, &code); for(i=0; i < inp->pfp_event_count; i++) { pfm_get_event_code(inp->pfp_events[i].event, &c); if (c == code) return 1; } return 0; } /* * IA64_INST_RETIRED (and subevents) is the only event which can be measured on all * 4 IBR when non-fine mode is not possible. * * This function returns: * - the number of events match the IA64_INST_RETIRED code * - in retired_mask to bottom 4 bits indicates which of the 4 INST_RETIRED event * is present */ static unsigned int check_inst_retired_events(pfmlib_input_param_t *inp, unsigned long *retired_mask) { int code; int c; unsigned int i, count, found = 0; unsigned long umask, mask; pfm_get_event_code(PME_MONT_IA64_INST_RETIRED, &code); count = inp->pfp_event_count; mask = 0; for(i=0; i < count; i++) { pfm_get_event_code(inp->pfp_events[i].event, &c); if (c == code) { pfm_mont_get_event_umask(inp->pfp_events[i].event, &umask); switch(umask) { case 0: mask |= 1; break; case 1: mask |= 2; break; case 2: mask |= 4; break; case 3: mask |= 8; break; } found++; } } if (retired_mask) *retired_mask = mask; return found; } static int check_fine_mode_possible(pfmlib_mont_input_rr_t *rr, int n) { pfmlib_mont_input_rr_desc_t *lim = rr->rr_limits; int i; for(i=0; i < n; i++) { if ((lim[i].rr_start & FINE_MODE_MASK) != (lim[i].rr_end & FINE_MODE_MASK)) return 0; } return 1; } /* * mode = 0 -> check code (enforce bundle alignment) * mode = 1 -> check data */ static int check_intervals(pfmlib_mont_input_rr_t *irr, int mode, unsigned int *n_intervals) { unsigned int i; pfmlib_mont_input_rr_desc_t *lim = irr->rr_limits; for(i=0; i < 4; i++) { /* end marker */ if (lim[i].rr_start == 0 && lim[i].rr_end == 0) break; /* invalid entry */ if (lim[i].rr_start >= lim[i].rr_end) return PFMLIB_ERR_IRRINVAL; if (mode == 0 && (lim[i].rr_start & 0xf || lim[i].rr_end & 0xf)) return PFMLIB_ERR_IRRALIGN; } *n_intervals = i; return PFMLIB_SUCCESS; } /* * It is not possible to measure more than one of the * L2D_OZQ_CANCELS0, L2D_OZQ_CANCELS1 at the same time. */ static int cancel_events[]= { PME_MONT_L2D_OZQ_CANCELS0_ACQ, PME_MONT_L2D_OZQ_CANCELS1_ANY }; #define NCANCEL_EVENTS sizeof(cancel_events)/sizeof(int) static int check_cancel_events(pfmlib_input_param_t *inp) { unsigned int i, j, count; int code; int cancel_codes[NCANCEL_EVENTS]; int idx = -1; for(i=0; i < NCANCEL_EVENTS; i++) { pfm_get_event_code(cancel_events[i], &code); cancel_codes[i] = code; } count = inp->pfp_event_count; for(i=0; i < count; i++) { for (j=0; j < NCANCEL_EVENTS; j++) { pfm_get_event_code(inp->pfp_events[i].event, &code); if (code == cancel_codes[j]) { if (idx != -1) { return PFMLIB_ERR_INVAL; } idx = inp->pfp_events[i].event; } } } return PFMLIB_SUCCESS; } /* * Automatically dispatch events to corresponding counters following constraints. */ static unsigned int l2d_set1_cnts[]={ 4, 5, 8 }; static unsigned int l2d_set2_cnts[]={ 6, 7, 9 }; static int pfm_mont_dispatch_counters(pfmlib_input_param_t *inp, pfmlib_mont_input_param_t *mod_in, pfmlib_output_param_t *outp) { pfmlib_mont_input_param_t *param = mod_in; pfm_mont_pmc_reg_t reg; pfmlib_event_t *e; pfmlib_reg_t *pc, *pd; pfmlib_regmask_t avail_cntrs, impl_cntrs; unsigned int i,j, k, max_cnt; unsigned int assign[PMU_MONT_NUM_COUNTERS]; unsigned int m, cnt; unsigned int l1d_set; unsigned long l2d_set1_mask, l2d_set2_mask, evt_mask, mesi; unsigned long not_assigned_events, cnt_mask; int l2d_set1_p, l2d_set2_p; int ret; e = inp->pfp_events; pc = outp->pfp_pmcs; pd = outp->pfp_pmds; cnt = inp->pfp_event_count; if (PFMLIB_DEBUG()) for (m=0; m < cnt; m++) { DPRINT("ev[%d]=%s counters=0x%lx\n", m, montecito_pe[e[m].event].pme_name, montecito_pe[e[m].event].pme_counters); } if (cnt > PMU_MONT_NUM_COUNTERS) return PFMLIB_ERR_TOOMANY; l1d_set = UNEXISTING_SET; ret = check_cross_groups(inp, &l1d_set, &l2d_set1_mask, &l2d_set2_mask); if (ret != PFMLIB_SUCCESS) return ret; ret = check_cancel_events(inp); if (ret != PFMLIB_SUCCESS) return ret; /* * at this point, we know that: * - we have at most 1 L1D set * - we have at most 2 L2D sets * - cancel events are compatible */ DPRINT("l1d_set=%u l2d_set1_mask=0x%lx l2d_set2_mask=0x%lx\n", l1d_set, l2d_set1_mask, l2d_set2_mask); /* * first, place L1D cache event in PMC5 * * this is the strongest constraint */ pfm_get_impl_counters(&impl_cntrs); pfm_regmask_andnot(&avail_cntrs, &impl_cntrs, &inp->pfp_unavail_pmcs); not_assigned_events = 0; DPRINT("avail_cntrs=0x%lx\n", avail_cntrs.bits[0]); /* * we do not check ALL_THRD here because at least * one event has to be in PMC5 for this group */ if (l1d_set != UNEXISTING_SET) { if (!pfm_regmask_isset(&avail_cntrs, 5)) return PFMLIB_ERR_NOASSIGN; assign[l1d_set] = 5; pfm_regmask_clr(&avail_cntrs, 5); } l2d_set1_p = l2d_set2_p = 0; /* * assign L2D set1 and set2 counters */ for (i=0; i < cnt ; i++) { evt_mask = 1UL << i; /* * place l2d set1 events. First 3 go to designated * counters, the rest is placed elsewhere in the final * pass */ if (l2d_set1_p < 3 && (l2d_set1_mask & evt_mask)) { assign[i] = l2d_set1_cnts[l2d_set1_p]; if (!pfm_regmask_isset(&avail_cntrs, assign[i])) return PFMLIB_ERR_NOASSIGN; pfm_regmask_clr(&avail_cntrs, assign[i]); l2d_set1_p++; continue; } /* * same as above but for l2d set2 */ if (l2d_set2_p < 3 && (l2d_set2_mask & evt_mask)) { assign[i] = l2d_set2_cnts[l2d_set2_p]; if (!pfm_regmask_isset(&avail_cntrs, assign[i])) return PFMLIB_ERR_NOASSIGN; pfm_regmask_clr(&avail_cntrs, assign[i]); l2d_set2_p++; continue; } /* * if not l2d nor l1d, then defer placement until final pass */ if (i != l1d_set) not_assigned_events |= evt_mask; DPRINT("phase 1: i=%u avail_cntrs=0x%lx l2d_set1_p=%d l2d_set2_p=%d not_assigned=0x%lx\n", i, avail_cntrs.bits[0], l2d_set1_p, l2d_set2_p, not_assigned_events); } /* * assign BUS_* ER_* events (work only in PMC4-PMC9) */ evt_mask = not_assigned_events; for (i=0; evt_mask ; i++, evt_mask >>=1) { if ((evt_mask & 0x1) == 0) continue; cnt_mask = montecito_pe[e[i].event].pme_counters; /* * only interested in events with restricted set of counters */ if (cnt_mask == 0xfff0) continue; for(j=0; cnt_mask; j++, cnt_mask >>=1) { if ((cnt_mask & 0x1) == 0) continue; DPRINT("phase 2: i=%d j=%d cnt_mask=0x%lx avail_cntrs=0x%lx not_assigned_evnts=0x%lx\n", i, j, cnt_mask, avail_cntrs.bits[0], not_assigned_events); if (!pfm_regmask_isset(&avail_cntrs, j)) continue; assign[i] = j; not_assigned_events &= ~(1UL << i); pfm_regmask_clr(&avail_cntrs, j); break; } if (cnt_mask == 0) return PFMLIB_ERR_NOASSIGN; } /* * assign the rest of the events (no constraints) */ evt_mask = not_assigned_events; max_cnt = PMU_MONT_FIRST_COUNTER + PMU_MONT_NUM_COUNTERS; for (i=0, j=0; evt_mask ; i++, evt_mask >>=1) { DPRINT("phase 3a: i=%d j=%d evt_mask=0x%lx avail_cntrs=0x%lx not_assigned_evnts=0x%lx\n", i, j, evt_mask, avail_cntrs.bits[0], not_assigned_events); if ((evt_mask & 0x1) == 0) continue; while(j < max_cnt && !pfm_regmask_isset(&avail_cntrs, j)) { DPRINT("phase 3: i=%d j=%d evt_mask=0x%lx avail_cntrs=0x%lx not_assigned_evnts=0x%lx\n", i, j, evt_mask, avail_cntrs.bits[0], not_assigned_events); j++; } if (j == max_cnt) return PFMLIB_ERR_NOASSIGN; assign[i] = j; j++; } for (j=0; j < cnt ; j++ ) { mesi = 0; /* * XXX: we do not support .all placement just yet */ if (param && param->pfp_mont_counters[j].flags & PFMLIB_MONT_FL_EVT_ALL_THRD) { DPRINT(".all mode is not yet supported by libpfm\n"); return PFMLIB_ERR_NOTSUPP; } if (has_mesi(e[j].event)) { for(k=0;k< e[j].num_masks; k++) { mesi |= 1UL << e[j].unit_masks[k]; } /* by default we capture everything */ if (mesi == 0) mesi = 0xf; } reg.pmc_val = 0; /* clear all, bits 26-27 must be zero for proper operations */ /* if plm is 0, then assume not specified per-event and use default */ reg.pmc_plm = inp->pfp_events[j].plm ? inp->pfp_events[j].plm : inp->pfp_dfl_plm; reg.pmc_oi = 0; /* let the user/OS deal with this field */ reg.pmc_pm = inp->pfp_flags & PFMLIB_PFP_SYSTEMWIDE ? 1 : 0; reg.pmc_thres = param ? param->pfp_mont_counters[j].thres: 0; reg.pmc_ism = 0x2; /* force IA-64 mode */ reg.pmc_umask = is_ear(e[j].event) ? 0x0 : montecito_pe[e[j].event].pme_umask; reg.pmc_es = montecito_pe[e[j].event].pme_code; reg.pmc_all = 0; /* XXX force self for now */ reg.pmc_m = (mesi>>3) & 0x1; reg.pmc_e = (mesi>>2) & 0x1; reg.pmc_s = (mesi>>1) & 0x1; reg.pmc_i = mesi & 0x1; /* * Note that we don't force PMC4.pmc_ena = 1 because the kernel takes care of this for us. * This way we don't have to program something in PMC4 even when we don't use it */ pc[j].reg_num = assign[j]; pc[j].reg_value = reg.pmc_val; pc[j].reg_addr = pc[j].reg_alt_addr = assign[j]; pd[j].reg_num = assign[j]; pd[j].reg_addr = pd[j].reg_alt_addr = assign[j]; __pfm_vbprintf("[PMC%u(pmc%u)=0x%06lx m=%d e=%d s=%d i=%d thres=%d all=%d es=0x%02x plm=%d umask=0x%x pm=%d ism=0x%x oi=%d] %s\n", assign[j], assign[j], reg.pmc_val, reg.pmc_m, reg.pmc_e, reg.pmc_s, reg.pmc_i, reg.pmc_thres, reg.pmc_all, reg.pmc_es,reg.pmc_plm, reg.pmc_umask, reg.pmc_pm, reg.pmc_ism, reg.pmc_oi, montecito_pe[e[j].event].pme_name); __pfm_vbprintf("[PMD%u(pmd%u)]\n", pd[j].reg_num, pd[j].reg_num); } /* number of PMC registers programmed */ outp->pfp_pmc_count = cnt; outp->pfp_pmd_count = cnt; return PFMLIB_SUCCESS; } static int pfm_dispatch_iear(pfmlib_input_param_t *inp, pfmlib_mont_input_param_t *mod_in, pfmlib_output_param_t *outp) { pfm_mont_pmc_reg_t reg; pfmlib_mont_input_param_t *param = mod_in; pfmlib_reg_t *pc, *pd; pfmlib_mont_input_param_t fake_param; unsigned int pos1, pos2; unsigned int i, count; pc = outp->pfp_pmcs; pd = outp->pfp_pmds; pos1 = outp->pfp_pmc_count; pos2 = outp->pfp_pmd_count; count = inp->pfp_event_count; for (i=0; i < count; i++) { if (is_iear(inp->pfp_events[i].event)) break; } if (param == NULL || param->pfp_mont_iear.ear_used == 0) { /* * case 3: no I-EAR event, no (or nothing) in param->pfp_mont_iear.ear_used */ if (i == count) return PFMLIB_SUCCESS; memset(&fake_param, 0, sizeof(fake_param)); param = &fake_param; /* * case 1: extract all information for event (name) */ pfm_mont_get_ear_mode(inp->pfp_events[i].event, ¶m->pfp_mont_iear.ear_mode); param->pfp_mont_iear.ear_umask = evt_umask(inp->pfp_events[i].event); DPRINT("I-EAR event with no info\n"); } /* * case 2: ear_used=1, event is defined, we use the param info as it is more precise * case 4: ear_used=1, no event (free running I-EAR), use param info */ reg.pmc_val = 0; if (param->pfp_mont_iear.ear_mode == PFMLIB_MONT_EAR_TLB_MODE) { /* if plm is 0, then assume not specified per-event and use default */ reg.pmc37_mont_tlb_reg.iear_plm = param->pfp_mont_iear.ear_plm ? param->pfp_mont_iear.ear_plm : inp->pfp_dfl_plm; reg.pmc37_mont_tlb_reg.iear_pm = inp->pfp_flags & PFMLIB_PFP_SYSTEMWIDE ? 1 : 0; reg.pmc37_mont_tlb_reg.iear_ct = 0x0; reg.pmc37_mont_tlb_reg.iear_umask = param->pfp_mont_iear.ear_umask; } else if (param->pfp_mont_iear.ear_mode == PFMLIB_MONT_EAR_CACHE_MODE) { /* if plm is 0, then assume not specified per-event and use default */ reg.pmc37_mont_cache_reg.iear_plm = param->pfp_mont_iear.ear_plm ? param->pfp_mont_iear.ear_plm : inp->pfp_dfl_plm; reg.pmc37_mont_cache_reg.iear_pm = inp->pfp_flags & PFMLIB_PFP_SYSTEMWIDE ? 1 : 0; reg.pmc37_mont_cache_reg.iear_ct = 0x1; reg.pmc37_mont_cache_reg.iear_umask = param->pfp_mont_iear.ear_umask; } else { DPRINT("ALAT mode not supported in I-EAR mode\n"); return PFMLIB_ERR_INVAL; } if (pfm_regmask_isset(&inp->pfp_unavail_pmcs, 37)) return PFMLIB_ERR_NOASSIGN; pc[pos1].reg_num = 37; /* PMC37 is I-EAR config register */ pc[pos1].reg_value = reg.pmc_val; pc[pos1].reg_addr = pc[pos1].reg_addr = 37; pos1++; pd[pos2].reg_num = 34; pd[pos2].reg_addr = pd[pos2].reg_alt_addr = 34; pos2++; pd[pos2].reg_num = 35; pd[pos2].reg_addr = pd[pos2].reg_alt_addr = 35; pos2++; if (param->pfp_mont_iear.ear_mode == PFMLIB_MONT_EAR_TLB_MODE) { __pfm_vbprintf("[PMC37(pmc37)=0x%lx ctb=tlb plm=%d pm=%d umask=0x%x]\n", reg.pmc_val, reg.pmc37_mont_tlb_reg.iear_plm, reg.pmc37_mont_tlb_reg.iear_pm, reg.pmc37_mont_tlb_reg.iear_umask); } else { __pfm_vbprintf("[PMC37(pmc37)=0x%lx ctb=cache plm=%d pm=%d umask=0x%x]\n", reg.pmc_val, reg.pmc37_mont_cache_reg.iear_plm, reg.pmc37_mont_cache_reg.iear_pm, reg.pmc37_mont_cache_reg.iear_umask); } __pfm_vbprintf("[PMD34(pmd34)]\n[PMD35(pmd35)\n"); /* update final number of entries used */ outp->pfp_pmc_count = pos1; outp->pfp_pmd_count = pos2; return PFMLIB_SUCCESS; } static int pfm_dispatch_dear(pfmlib_input_param_t *inp, pfmlib_mont_input_param_t *mod_in, pfmlib_output_param_t *outp) { pfm_mont_pmc_reg_t reg; pfmlib_mont_input_param_t *param = mod_in; pfmlib_reg_t *pc, *pd; pfmlib_mont_input_param_t fake_param; unsigned int pos1, pos2; unsigned int i, count; pc = outp->pfp_pmcs; pd = outp->pfp_pmds; pos1 = outp->pfp_pmc_count; pos2 = outp->pfp_pmd_count; count = inp->pfp_event_count; for (i=0; i < count; i++) { if (is_dear(inp->pfp_events[i].event)) break; } if (param == NULL || param->pfp_mont_dear.ear_used == 0) { /* * case 3: no D-EAR event, no (or nothing) in param->pfp_mont_dear.ear_used */ if (i == count) return PFMLIB_SUCCESS; memset(&fake_param, 0, sizeof(fake_param)); param = &fake_param; /* * case 1: extract all information for event (name) */ pfm_mont_get_ear_mode(inp->pfp_events[i].event, ¶m->pfp_mont_dear.ear_mode); param->pfp_mont_dear.ear_umask = evt_umask(inp->pfp_events[i].event); DPRINT("D-EAR event with no info\n"); } /* sanity check on the mode */ if ( param->pfp_mont_dear.ear_mode != PFMLIB_MONT_EAR_CACHE_MODE && param->pfp_mont_dear.ear_mode != PFMLIB_MONT_EAR_TLB_MODE && param->pfp_mont_dear.ear_mode != PFMLIB_MONT_EAR_ALAT_MODE) return PFMLIB_ERR_INVAL; /* * case 2: ear_used=1, event is defined, we use the param info as it is more precise * case 4: ear_used=1, no event (free running D-EAR), use param info */ reg.pmc_val = 0; /* if plm is 0, then assume not specified per-event and use default */ reg.pmc40_mont_reg.dear_plm = param->pfp_mont_dear.ear_plm ? param->pfp_mont_dear.ear_plm : inp->pfp_dfl_plm; reg.pmc40_mont_reg.dear_pm = inp->pfp_flags & PFMLIB_PFP_SYSTEMWIDE ? 1 : 0; reg.pmc40_mont_reg.dear_mode = param->pfp_mont_dear.ear_mode; reg.pmc40_mont_reg.dear_umask = param->pfp_mont_dear.ear_umask; reg.pmc40_mont_reg.dear_ism = 0x2; /* force IA-64 mode */ if (pfm_regmask_isset(&inp->pfp_unavail_pmcs, 40)) return PFMLIB_ERR_NOASSIGN; pc[pos1].reg_num = 40; /* PMC11 is D-EAR config register */ pc[pos1].reg_value = reg.pmc_val; pc[pos1].reg_addr = pc[pos1].reg_alt_addr = 40; pos1++; pd[pos2].reg_num = 32; pd[pos2].reg_addr = pd[pos2].reg_alt_addr = 32; pos2++; pd[pos2].reg_num = 33; pd[pos2].reg_addr = pd[pos2].reg_alt_addr = 33; pos2++; pd[pos2].reg_num = 36; pd[pos2].reg_addr = pd[pos2].reg_alt_addr = 36; pos2++; __pfm_vbprintf("[PMC40(pmc40)=0x%lx mode=%s plm=%d pm=%d ism=0x%x umask=0x%x]\n", reg.pmc_val, reg.pmc40_mont_reg.dear_mode == 0 ? "L1D" : (reg.pmc40_mont_reg.dear_mode == 1 ? "L1DTLB" : "ALAT"), reg.pmc40_mont_reg.dear_plm, reg.pmc40_mont_reg.dear_pm, reg.pmc40_mont_reg.dear_ism, reg.pmc40_mont_reg.dear_umask); __pfm_vbprintf("[PMD32(pmd32)]\n[PMD33(pmd33)\nPMD36(pmd36)\n"); /* update final number of entries used */ outp->pfp_pmc_count = pos1; outp->pfp_pmd_count = pos2; return PFMLIB_SUCCESS; } static int pfm_dispatch_opcm(pfmlib_input_param_t *inp, pfmlib_mont_input_param_t *mod_in, pfmlib_output_param_t *outp, pfmlib_mont_output_param_t *mod_out) { pfmlib_mont_input_param_t *param = mod_in; pfmlib_reg_t *pc = outp->pfp_pmcs; pfm_mont_pmc_reg_t reg1, reg2, pmc36; unsigned int i, has_1st_pair, has_2nd_pair, count; unsigned int pos = outp->pfp_pmc_count; int used_pmc32, used_pmc34; if (param == NULL) return PFMLIB_SUCCESS; #define PMC36_DFL_VAL 0xfffffff0 /* * mandatory default value for PMC36 as described in the documentation * all monitoring is opcode constrained. Better make sure the match/mask * is set to match everything! It looks weird for the default value! */ pmc36.pmc_val = PMC36_DFL_VAL; reg1.pmc_val = 0x030f01ffffffffff; reg2.pmc_val = 0; used_pmc32 = param->pfp_mont_opcm1.opcm_used; used_pmc34 = param->pfp_mont_opcm2.opcm_used; /* * check in any feature is used. * PMC36 must be setup when opcode matching is used OR when code range restriction is used */ if (used_pmc32 == 0 && used_pmc34 == 0 && param->pfp_mont_irange.rr_used == 0) return 0; /* * check for rr_nbr_used to make sure that the range request produced something on output */ if (used_pmc32 || (param->pfp_mont_irange.rr_used && mod_out->pfp_mont_irange.rr_nbr_used) ) { /* * if not used, ignore all bits */ if (used_pmc32) { reg1.pmc32_34_mont_reg.opcm_mask = param->pfp_mont_opcm1.opcm_mask; reg1.pmc32_34_mont_reg.opcm_b = param->pfp_mont_opcm1.opcm_b; reg1.pmc32_34_mont_reg.opcm_f = param->pfp_mont_opcm1.opcm_f; reg1.pmc32_34_mont_reg.opcm_i = param->pfp_mont_opcm1.opcm_i; reg1.pmc32_34_mont_reg.opcm_m = param->pfp_mont_opcm1.opcm_m; reg2.pmc33_35_mont_reg.opcm_match = param->pfp_mont_opcm1.opcm_match; } if (param->pfp_mont_irange.rr_used) { reg1.pmc32_34_mont_reg.opcm_ig_ad = 0; reg1.pmc32_34_mont_reg.opcm_inv = param->pfp_mont_irange.rr_flags & PFMLIB_MONT_RR_INV ? 1 : 0; } else { /* clear range restriction fields when none is used */ reg1.pmc32_34_mont_reg.opcm_ig_ad = 1; reg1.pmc32_34_mont_reg.opcm_inv = 0; } if (pfm_regmask_isset(&inp->pfp_unavail_pmcs, 32)) return PFMLIB_ERR_NOASSIGN; pc[pos].reg_num = 32; pc[pos].reg_value = reg1.pmc_val; pc[pos].reg_addr = pc[pos].reg_alt_addr = 32; pos++; /* * will be constrained by PMC32 */ if (used_pmc32) { if (pfm_regmask_isset(&inp->pfp_unavail_pmcs, 33)) return PFMLIB_ERR_NOASSIGN; /* * used pmc33 only when we have active opcode matching */ pc[pos].reg_num = 33; pc[pos].reg_value = reg2.pmc_val; pc[pos].reg_addr = pc[pos].reg_alt_addr = 33; pos++; has_1st_pair = has_2nd_pair = 0; count = inp->pfp_event_count; for(i=0; i < count; i++) { if (inp->pfp_events[i].event == PME_MONT_IA64_TAGGED_INST_RETIRED_IBRP0_PMC32_33) has_1st_pair=1; if (inp->pfp_events[i].event == PME_MONT_IA64_TAGGED_INST_RETIRED_IBRP2_PMC32_33) has_2nd_pair=1; } if (has_1st_pair || has_2nd_pair == 0) pmc36.pmc36_mont_reg.opcm_ch0_ig_opcm = 0; if (has_2nd_pair || has_1st_pair == 0) pmc36.pmc36_mont_reg.opcm_ch2_ig_opcm = 0; } __pfm_vbprintf("[PMC32(pmc32)=0x%lx m=%d i=%d f=%d b=%d mask=0x%lx inv=%d ig_ad=%d]\n", reg1.pmc_val, reg1.pmc32_34_mont_reg.opcm_m, reg1.pmc32_34_mont_reg.opcm_i, reg1.pmc32_34_mont_reg.opcm_f, reg1.pmc32_34_mont_reg.opcm_b, reg1.pmc32_34_mont_reg.opcm_mask, reg1.pmc32_34_mont_reg.opcm_inv, reg1.pmc32_34_mont_reg.opcm_ig_ad); if (used_pmc32) __pfm_vbprintf("[PMC33(pmc33)=0x%lx match=0x%lx]\n", reg2.pmc_val, reg2.pmc33_35_mont_reg.opcm_match); } /* * will be constrained by PMC34 */ if (used_pmc34) { reg1.pmc_val = 0x01ffffffffff; /* pmc34 default value */ reg2.pmc_val = 0; reg1.pmc32_34_mont_reg.opcm_mask = param->pfp_mont_opcm2.opcm_mask; reg1.pmc32_34_mont_reg.opcm_b = param->pfp_mont_opcm2.opcm_b; reg1.pmc32_34_mont_reg.opcm_f = param->pfp_mont_opcm2.opcm_f; reg1.pmc32_34_mont_reg.opcm_i = param->pfp_mont_opcm2.opcm_i; reg1.pmc32_34_mont_reg.opcm_m = param->pfp_mont_opcm2.opcm_m; reg2.pmc33_35_mont_reg.opcm_match = param->pfp_mont_opcm2.opcm_match; if (pfm_regmask_isset(&inp->pfp_unavail_pmcs, 34)) return PFMLIB_ERR_NOASSIGN; if (pfm_regmask_isset(&inp->pfp_unavail_pmcs, 35)) return PFMLIB_ERR_NOASSIGN; pc[pos].reg_num = 34; pc[pos].reg_value = reg1.pmc_val; pc[pos].reg_addr = pc[pos].reg_alt_addr = 34; pos++; pc[pos].reg_num = 35; pc[pos].reg_value = reg2.pmc_val; pc[pos].reg_addr = pc[pos].reg_alt_addr = 35; pos++; has_1st_pair = has_2nd_pair = 0; count = inp->pfp_event_count; for(i=0; i < count; i++) { if (inp->pfp_events[i].event == PME_MONT_IA64_TAGGED_INST_RETIRED_IBRP1_PMC34_35) has_1st_pair=1; if (inp->pfp_events[i].event == PME_MONT_IA64_TAGGED_INST_RETIRED_IBRP3_PMC34_35) has_2nd_pair=1; } if (has_1st_pair || has_2nd_pair == 0) pmc36.pmc36_mont_reg.opcm_ch1_ig_opcm = 0; if (has_2nd_pair || has_1st_pair == 0) pmc36.pmc36_mont_reg.opcm_ch3_ig_opcm = 0; __pfm_vbprintf("[PMC34(pmc34)=0x%lx m=%d i=%d f=%d b=%d mask=0x%lx]\n", reg1.pmc_val, reg1.pmc32_34_mont_reg.opcm_m, reg1.pmc32_34_mont_reg.opcm_i, reg1.pmc32_34_mont_reg.opcm_f, reg1.pmc32_34_mont_reg.opcm_b, reg1.pmc32_34_mont_reg.opcm_mask); __pfm_vbprintf("[PMC35(pmc35)=0x%lx match=0x%lx]\n", reg2.pmc_val, reg2.pmc33_35_mont_reg.opcm_match); } if (pmc36.pmc_val != PMC36_DFL_VAL) { if (pfm_regmask_isset(&inp->pfp_unavail_pmcs, 36)) return PFMLIB_ERR_NOASSIGN; pc[pos].reg_num = 36; pc[pos].reg_value = pmc36.pmc_val; pc[pos].reg_addr = pc[pos].reg_alt_addr = 36; pos++; __pfm_vbprintf("[PMC36(pmc36)=0x%lx ch0_ig_op=%d ch1_ig_op=%d ch2_ig_op=%d ch3_ig_op=%d]\n", pmc36.pmc_val, pmc36.pmc36_mont_reg.opcm_ch0_ig_opcm, pmc36.pmc36_mont_reg.opcm_ch1_ig_opcm, pmc36.pmc36_mont_reg.opcm_ch2_ig_opcm, pmc36.pmc36_mont_reg.opcm_ch3_ig_opcm); } outp->pfp_pmc_count = pos; return PFMLIB_SUCCESS; } static int pfm_dispatch_etb(pfmlib_input_param_t *inp, pfmlib_mont_input_param_t *mod_in, pfmlib_output_param_t *outp) { pfmlib_event_t *e= inp->pfp_events; pfm_mont_pmc_reg_t reg; pfmlib_mont_input_param_t *param = mod_in; pfmlib_reg_t *pc, *pd; pfmlib_mont_input_param_t fake_param; int found_etb = 0, found_bad_dear = 0; int has_etb_param; unsigned int i, pos1, pos2; unsigned int count; pc = outp->pfp_pmcs; pd = outp->pfp_pmds; pos1 = outp->pfp_pmc_count; pos2 = outp->pfp_pmd_count; /* * explicit ETB settings */ has_etb_param = param && param->pfp_mont_etb.etb_used; reg.pmc_val = 0UL; /* * we need to scan all events looking for DEAR ALAT/TLB due to incompatibility. * In this case PMC39 must be forced to zero */ count = inp->pfp_event_count; for (i=0; i < count; i++) { if (is_etb(e[i].event)) found_etb = 1; /* * keep track of the first ETB event */ /* look only for DEAR TLB */ if (is_dear(e[i].event) && (is_ear_tlb(e[i].event) || is_ear_alat(e[i].event))) { found_bad_dear = 1; } } DPRINT("found_etb=%d found_bar_dear=%d\n", found_etb, found_bad_dear); /* * did not find D-EAR TLB/ALAT event, need to check param structure */ if (found_bad_dear == 0 && param && param->pfp_mont_dear.ear_used == 1) { if ( param->pfp_mont_dear.ear_mode == PFMLIB_MONT_EAR_TLB_MODE || param->pfp_mont_dear.ear_mode == PFMLIB_MONT_EAR_ALAT_MODE) found_bad_dear = 1; } /* * no explicit ETB event and no special case to deal with (cover part of case 3) */ if (found_etb == 0 && has_etb_param == 0 && found_bad_dear == 0) return PFMLIB_SUCCESS; if (has_etb_param == 0) { /* * case 3: no ETB event, etb_used=0 but found_bad_dear=1, need to cleanup PMC12 */ if (found_etb == 0) goto assign_zero; /* * case 1: we have a ETB event but no param, default setting is to capture * all branches. */ memset(&fake_param, 0, sizeof(fake_param)); param = &fake_param; param->pfp_mont_etb.etb_tm = 0x3; /* all branches */ param->pfp_mont_etb.etb_ptm = 0x3; /* all branches */ param->pfp_mont_etb.etb_ppm = 0x3; /* all branches */ param->pfp_mont_etb.etb_brt = 0x0; /* all branches */ DPRINT("ETB event with no info\n"); } /* * case 2: ETB event in the list, param provided * case 4: no ETB event, param provided (free running mode) */ reg.pmc39_mont_reg.etbc_plm = param->pfp_mont_etb.etb_plm ? param->pfp_mont_etb.etb_plm : inp->pfp_dfl_plm; reg.pmc39_mont_reg.etbc_pm = inp->pfp_flags & PFMLIB_PFP_SYSTEMWIDE ? 1 : 0; reg.pmc39_mont_reg.etbc_ds = 0; /* 1 is reserved */ reg.pmc39_mont_reg.etbc_tm = param->pfp_mont_etb.etb_tm & 0x3; reg.pmc39_mont_reg.etbc_ptm = param->pfp_mont_etb.etb_ptm & 0x3; reg.pmc39_mont_reg.etbc_ppm = param->pfp_mont_etb.etb_ppm & 0x3; reg.pmc39_mont_reg.etbc_brt = param->pfp_mont_etb.etb_brt & 0x3; /* * if DEAR-ALAT or DEAR-TLB is set then PMC12 must be set to zero (see documentation p. 87) * * D-EAR ALAT/TLB and ETB cannot be used at the same time. * From documentation: PMC12 must be zero in this mode; else the wrong IP for misses * coming right after a mispredicted branch. * * D-EAR cache is fine. */ assign_zero: if (found_bad_dear && reg.pmc_val != 0UL) return PFMLIB_ERR_EVTINCOMP; if (pfm_regmask_isset(&inp->pfp_unavail_pmcs, 39)) return PFMLIB_ERR_NOASSIGN; pc[pos1].reg_num = 39; pc[pos1].reg_value = reg.pmc_val; pc[pos1].reg_addr = pc[pos1].reg_alt_addr = 39; pos1++; __pfm_vbprintf("[PMC39(pmc39)=0x%lx plm=%d pm=%d ds=%d tm=%d ptm=%d ppm=%d brt=%d]\n", reg.pmc_val, reg.pmc39_mont_reg.etbc_plm, reg.pmc39_mont_reg.etbc_pm, reg.pmc39_mont_reg.etbc_ds, reg.pmc39_mont_reg.etbc_tm, reg.pmc39_mont_reg.etbc_ptm, reg.pmc39_mont_reg.etbc_ppm, reg.pmc39_mont_reg.etbc_brt); /* * only add ETB PMDs when actually using BTB. * Not needed when dealing with D-EAR TLB and DEAR-ALAT * PMC39 restriction */ if (found_etb || has_etb_param) { pd[pos2].reg_num = 38; pd[pos2].reg_addr = pd[pos2].reg_alt_addr = 38; pos2++; pd[pos2].reg_num = 39; pd[pos2].reg_addr = pd[pos2].reg_alt_addr = 39; pos2++; __pfm_vbprintf("[PMD38(pmd38)]\n[PMD39(pmd39)\n"); for(i=48; i < 64; i++, pos2++) { pd[pos2].reg_num = i; pd[pos2].reg_addr = pd[pos2].reg_alt_addr = i; __pfm_vbprintf("[PMD%u(pmd%u)]\n", pd[pos2].reg_num, pd[pos2].reg_num); } } /* update final number of entries used */ outp->pfp_pmc_count = pos1; outp->pfp_pmd_count = pos2; return PFMLIB_SUCCESS; } static void do_normal_rr(unsigned long start, unsigned long end, pfmlib_reg_t *br, int nbr, int dir, int *idx, int *reg_idx, int plm) { unsigned long size, l_addr, c; unsigned long l_offs = 0, r_offs = 0; unsigned long l_size, r_size; dbreg_t db; int p2; if (nbr < 1 || end <= start) return; size = end - start; DPRINT("start=0x%016lx end=0x%016lx size=0x%lx bytes (%lu bundles) nbr=%d dir=%d\n", start, end, size, size >> 4, nbr, dir); p2 = pfm_ia64_fls(size); c = ALIGN_DOWN(end, p2); DPRINT("largest power of two possible: 2^%d=0x%lx, crossing=0x%016lx\n", p2, 1UL << p2, c); if ((c - (1UL<= start) { l_addr = c - (1UL << p2); } else { p2--; if ((c + (1UL<>l_offs: 0x%lx\n", l_offs); } } else if (dir == 1 && r_size != 0 && nbr == 1) { p2++; l_addr = start; if (PFMLIB_DEBUG()) { r_offs = l_addr+(1UL<>r_offs: 0x%lx\n", r_offs); } } l_size = l_addr - start; r_size = end - l_addr-(1UL<>largest chunk: 2^%d @0x%016lx-0x%016lx\n", p2, l_addr, l_addr+(1UL<>before: 0x%016lx-0x%016lx\n", start, l_addr); if (r_size && !r_offs) printf(">>after : 0x%016lx-0x%016lx\n", l_addr+(1UL<>1; if (nbr & 0x1) { /* * our simple heuristic is: * we assign the largest number of registers to the largest * of the two chunks */ if (l_size > r_size) { l_nbr++; } else { r_nbr++; } } do_normal_rr(start, l_addr, br, l_nbr, 0, idx, reg_idx, plm); do_normal_rr(l_addr+(1UL<rr_start, in_rr->rr_end, n_pairs, fine_mode ? ", fine_mode" : "", rr_flags & PFMLIB_MONT_RR_INV ? ", inversed" : ""); __pfm_vbprintf("start offset: -0x%lx end_offset: +0x%lx\n", out_rr->rr_soff, out_rr->rr_eoff); for (j=0; j < n_pairs; j++, base_idx+=2) { d.val = dbr[base_idx+1].reg_value; r_end = dbr[base_idx].reg_value+((~(d.db.db_mask)) & ~(0xffUL << 56)); if (fine_mode) __pfm_vbprintf("brp%u: db%u: 0x%016lx db%u: plm=0x%x mask=0x%016lx\n", dbr[base_idx].reg_num>>1, dbr[base_idx].reg_num, dbr[base_idx].reg_value, dbr[base_idx+1].reg_num, d.db.db_plm, d.db.db_mask); else __pfm_vbprintf("brp%u: db%u: 0x%016lx db%u: plm=0x%x mask=0x%016lx end=0x%016lx\n", dbr[base_idx].reg_num>>1, dbr[base_idx].reg_num, dbr[base_idx].reg_value, dbr[base_idx+1].reg_num, d.db.db_plm, d.db.db_mask, r_end); } } /* * base_idx = base register index to use (for IBRP1, base_idx = 2) */ static int compute_fine_rr(pfmlib_mont_input_rr_t *irr, int dfl_plm, int n, int *base_idx, pfmlib_mont_output_rr_t *orr) { int i; pfmlib_reg_t *br; pfmlib_mont_input_rr_desc_t *in_rr; pfmlib_mont_output_rr_desc_t *out_rr; unsigned long addr; int reg_idx; dbreg_t db; in_rr = irr->rr_limits; out_rr = orr->rr_infos; br = orr->rr_br+orr->rr_nbr_used; reg_idx = *base_idx; db.val = 0; db.db.db_mask = FINE_MODE_MASK; if (n > 2) return PFMLIB_ERR_IRRTOOMANY; for (i=0; i < n; i++, reg_idx += 2, in_rr++, br+= 4) { /* * setup lower limit pair * * because of the PMU can only see addresses on a 2-bundle boundary, we must align * down to the closest bundle-pair aligned address. 5 => 32-byte aligned address */ addr = ALIGN_DOWN(in_rr->rr_start, 5); out_rr->rr_soff = in_rr->rr_start - addr; /* * adjust plm for each range */ db.db.db_plm = in_rr->rr_plm ? in_rr->rr_plm : (unsigned long)dfl_plm; br[0].reg_num = reg_idx; br[0].reg_value = addr; br[0].reg_addr = br[0].reg_alt_addr = 1+reg_idx; br[1].reg_num = reg_idx+1; br[1].reg_value = db.val; br[1].reg_addr = br[1].reg_alt_addr = 1+reg_idx+1; /* * setup upper limit pair * * * In fine mode, the bundle address stored in the upper limit debug * registers is included in the count, so we substract 0x10 to exclude it. * * because of the PMU bug, we align the (corrected) end to the nearest * 32-byte aligned address + 0x10. With this correction and depending * on the correction, we may count one * * */ addr = in_rr->rr_end - 0x10; if ((addr & 0x1f) == 0) addr += 0x10; out_rr->rr_eoff = addr - in_rr->rr_end + 0x10; br[2].reg_num = reg_idx+4; br[2].reg_value = addr; br[2].reg_addr = br[2].reg_alt_addr = 1+reg_idx+4; br[3].reg_num = reg_idx+5; br[3].reg_value = db.val; br[3].reg_addr = br[3].reg_alt_addr = 1+reg_idx+5; if (PFMLIB_VERBOSE()) print_one_range(in_rr, out_rr, br, 0, 2, 1, irr->rr_flags); } orr->rr_nbr_used += i<<2; /* update base_idx, for subsequent calls */ *base_idx = reg_idx; return PFMLIB_SUCCESS; } /* * base_idx = base register index to use (for IBRP1, base_idx = 2) */ static int compute_single_rr(pfmlib_mont_input_rr_t *irr, int dfl_plm, int *base_idx, pfmlib_mont_output_rr_t *orr) { unsigned long size, end, start; unsigned long p_start, p_end; pfmlib_mont_input_rr_desc_t *in_rr; pfmlib_mont_output_rr_desc_t *out_rr; pfmlib_reg_t *br; dbreg_t db; int reg_idx; int l, m; in_rr = irr->rr_limits; out_rr = orr->rr_infos; br = orr->rr_br+orr->rr_nbr_used; start = in_rr->rr_start; end = in_rr->rr_end; size = end - start; reg_idx = *base_idx; l = pfm_ia64_fls(size); m = l; if (size & ((1UL << l)-1)) { if (l>62) { printf("range: [0x%lx-0x%lx] too big\n", start, end); return PFMLIB_ERR_IRRTOOBIG; } m++; } DPRINT("size=%ld, l=%d m=%d, internal: 0x%lx full: 0x%lx\n", size, l, m, 1UL << l, 1UL << m); for (; m < 64; m++) { p_start = ALIGN_DOWN(start, m); p_end = p_start+(1UL<= end) goto found; } return PFMLIB_ERR_IRRINVAL; found: DPRINT("m=%d p_start=0x%lx p_end=0x%lx\n", m, p_start,p_end); /* when the event is not IA64_INST_RETIRED, then we MUST use ibrp0 */ br[0].reg_num = reg_idx; br[0].reg_value = p_start; br[0].reg_addr = br[0].reg_alt_addr = 1+reg_idx; db.val = 0; db.db.db_mask = ~((1UL << m)-1); db.db.db_plm = in_rr->rr_plm ? in_rr->rr_plm : (unsigned long)dfl_plm; br[1].reg_num = reg_idx + 1; br[1].reg_value = db.val; br[1].reg_addr = br[1].reg_alt_addr = 1+reg_idx+1; out_rr->rr_soff = start - p_start; out_rr->rr_eoff = p_end - end; if (PFMLIB_VERBOSE()) print_one_range(in_rr, out_rr, br, 0, 1, 0, irr->rr_flags); orr->rr_nbr_used += 2; /* update base_idx, for subsequent calls */ *base_idx = reg_idx; return PFMLIB_SUCCESS; } static int compute_normal_rr(pfmlib_mont_input_rr_t *irr, int dfl_plm, int n, int *base_idx, pfmlib_mont_output_rr_t *orr) { pfmlib_mont_input_rr_desc_t *in_rr; pfmlib_mont_output_rr_desc_t *out_rr; unsigned long r_end; pfmlib_reg_t *br; dbreg_t d; int i, j; int br_index, reg_idx, prev_index; in_rr = irr->rr_limits; out_rr = orr->rr_infos; br = orr->rr_br+orr->rr_nbr_used; reg_idx = *base_idx; br_index = 0; for (i=0; i < n; i++, in_rr++, out_rr++) { /* * running out of registers */ if (br_index == 8) break; prev_index = br_index; do_normal_rr( in_rr->rr_start, in_rr->rr_end, br, 4 - (reg_idx>>1), /* how many pairs available */ 0, &br_index, ®_idx, in_rr->rr_plm ? in_rr->rr_plm : dfl_plm); DPRINT("br_index=%d reg_idx=%d\n", br_index, reg_idx); /* * compute offsets */ out_rr->rr_soff = out_rr->rr_eoff = 0; for(j=prev_index; j < br_index; j+=2) { d.val = br[j+1].reg_value; r_end = br[j].reg_value+((~(d.db.db_mask)+1) & ~(0xffUL << 56)); if (br[j].reg_value <= in_rr->rr_start) out_rr->rr_soff = in_rr->rr_start - br[j].reg_value; if (r_end >= in_rr->rr_end) out_rr->rr_eoff = r_end - in_rr->rr_end; } if (PFMLIB_VERBOSE()) print_one_range(in_rr, out_rr, br, prev_index, (br_index-prev_index)>>1, 0, irr->rr_flags); } /* do not have enough registers to cover all the ranges */ if (br_index == 8 && i < n) return PFMLIB_ERR_TOOMANY; orr->rr_nbr_used += br_index; /* update base_idx, for subsequent calls */ *base_idx = reg_idx; return PFMLIB_SUCCESS; } static int pfm_dispatch_irange(pfmlib_input_param_t *inp, pfmlib_mont_input_param_t *mod_in, pfmlib_output_param_t *outp, pfmlib_mont_output_param_t *mod_out) { pfm_mont_pmc_reg_t reg; pfmlib_mont_input_param_t *param = mod_in; pfmlib_mont_input_rr_t *irr; pfmlib_mont_output_rr_t *orr; pfmlib_reg_t *pc = outp->pfp_pmcs; unsigned long retired_mask; unsigned int i, pos = outp->pfp_pmc_count, count; unsigned int retired_only, retired_count, fine_mode, prefetch_count; unsigned int n_intervals; int base_idx = 0, dup = 0; int ret; if (param == NULL) return PFMLIB_SUCCESS; if (param->pfp_mont_irange.rr_used == 0) return PFMLIB_SUCCESS; if (mod_out == NULL) return PFMLIB_ERR_INVAL; irr = ¶m->pfp_mont_irange; orr = &mod_out->pfp_mont_irange; ret = check_intervals(irr, 0, &n_intervals); if (ret != PFMLIB_SUCCESS) return ret; if (n_intervals < 1) return PFMLIB_ERR_IRRINVAL; retired_count = check_inst_retired_events(inp, &retired_mask); retired_only = retired_count == inp->pfp_event_count; fine_mode = irr->rr_flags & PFMLIB_MONT_RR_NO_FINE_MODE ? 0 : check_fine_mode_possible(irr, n_intervals); DPRINT("n_intervals=%d retired_only=%d retired_count=%d fine_mode=%d\n", n_intervals, retired_only, retired_count, fine_mode); /* * On montecito, there are more constraints on what can be measured with irange. * * - The fine mode is the best because you directly set the lower and upper limits of * the range. This uses 2 ibr pairs for range (ibrp0/ibrp2 and ibp1/ibrp3). Therefore * at most 2 fine mode ranges can be defined. The boundaries of the range must be in the * same 64KB page. The fine mode works will all events. * * - if the fine mode fails, then for all events, except IA64_TAGGED_INST_RETIRED_*, only * the first pair of ibr is available: ibrp0. This imposes some severe restrictions on the * size and alignement of the range. It can be bigger than 64KB and must be properly aligned * on its size. The library relaxes these constraints by allowing the covered areas to be * larger than the expected range. It may start before and end after the requested range. * You can determine the amount of overrun in either direction for each range by looking at * the rr_soff (start offset) and rr_eoff (end offset). * * - if the events include certain prefetch events then only IBRP1 can be used. * See 3.3.5.2 Exception 1. * * - Finally, when the events are ONLY IA64_TAGGED_INST_RETIRED_* then all IBR pairs can be used * to cover the range giving us more flexibility to approximate the range when it is not * properly aligned on its size (see 10.3.5.2 Exception 2). But the corresponding * IA64_TAGGED_INST_RETIRED_* must be present. */ if (fine_mode == 0 && retired_only == 0 && n_intervals > 1) return PFMLIB_ERR_IRRTOOMANY; /* we do not default to non-fine mode to support more ranges */ if (n_intervals > 2 && fine_mode == 1) return PFMLIB_ERR_IRRTOOMANY; ret = check_prefetch_events(inp, irr, &prefetch_count, &base_idx, &dup); if (ret) return ret; DPRINT("prefetch_count=%u base_idx=%d dup=%d\n", prefetch_count, base_idx, dup); /* * CPU_OP_CYCLES.QUAL supports code range restrictions but it returns * meaningful values (fine/coarse mode) only when IBRP1 is not used. */ if ((base_idx > 0 || dup) && has_cpu_cycles_qual(inp)) return PFMLIB_ERR_FEATCOMB; if (fine_mode == 0) { if (retired_only) { /* can take multiple intervals */ ret = compute_normal_rr(irr, inp->pfp_dfl_plm, n_intervals, &base_idx, orr); } else { /* unless we have only prefetch and instruction retired events, * we cannot satisfy the request because the other events cannot * be measured on anything but IBRP0. */ if ((prefetch_count+retired_count) != inp->pfp_event_count) return PFMLIB_ERR_FEATCOMB; ret = compute_single_rr(irr, inp->pfp_dfl_plm, &base_idx, orr); if (ret == PFMLIB_SUCCESS && dup) ret = compute_single_rr(irr, inp->pfp_dfl_plm, &base_idx, orr); } } else { if (prefetch_count && n_intervals != 1) return PFMLIB_ERR_IRRTOOMANY; /* except is retired_only, can take only one interval */ ret = compute_fine_rr(irr, inp->pfp_dfl_plm, n_intervals, &base_idx, orr); if (ret == PFMLIB_SUCCESS && dup) ret = compute_fine_rr(irr, inp->pfp_dfl_plm, n_intervals, &base_idx, orr); } if (ret != PFMLIB_SUCCESS) return ret == PFMLIB_ERR_TOOMANY ? PFMLIB_ERR_IRRTOOMANY : ret; reg.pmc_val = 0xdb6; /* default value */ count = orr->rr_nbr_used; for (i=0; i < count; i++) { switch(orr->rr_br[i].reg_num) { case 0: reg.pmc38_mont_reg.iarc_ig_ibrp0 = 0; break; case 2: reg.pmc38_mont_reg.iarc_ig_ibrp1 = 0; break; case 4: reg.pmc38_mont_reg.iarc_ig_ibrp2 = 0; break; case 6: reg.pmc38_mont_reg.iarc_ig_ibrp3 = 0; break; } } if (fine_mode) { reg.pmc38_mont_reg.iarc_fine = 1; } else if (retired_only) { /* * we need to check that the user provided all the events needed to cover * all the ibr pairs used to cover the range */ if ((retired_mask & 0x1) == 0 && reg.pmc38_mont_reg.iarc_ig_ibrp0 == 0) return PFMLIB_ERR_IRRINVAL; if ((retired_mask & 0x2) == 0 && reg.pmc38_mont_reg.iarc_ig_ibrp1 == 0) return PFMLIB_ERR_IRRINVAL; if ((retired_mask & 0x4) == 0 && reg.pmc38_mont_reg.iarc_ig_ibrp2 == 0) return PFMLIB_ERR_IRRINVAL; if ((retired_mask & 0x8) == 0 && reg.pmc38_mont_reg.iarc_ig_ibrp3 == 0) return PFMLIB_ERR_IRRINVAL; } if (pfm_regmask_isset(&inp->pfp_unavail_pmcs, 38)) return PFMLIB_ERR_NOASSIGN; pc[pos].reg_num = 38; pc[pos].reg_value = reg.pmc_val; pc[pos].reg_addr = pc[pos].reg_alt_addr = 38; pos++; __pfm_vbprintf("[PMC38(pmc38)=0x%lx ig_ibrp0=%d ig_ibrp1=%d ig_ibrp2=%d ig_ibrp3=%d fine=%d]\n", reg.pmc_val, reg.pmc38_mont_reg.iarc_ig_ibrp0, reg.pmc38_mont_reg.iarc_ig_ibrp1, reg.pmc38_mont_reg.iarc_ig_ibrp2, reg.pmc38_mont_reg.iarc_ig_ibrp3, reg.pmc38_mont_reg.iarc_fine); outp->pfp_pmc_count = pos; return PFMLIB_SUCCESS; } static const unsigned long iod_tab[8]={ /* --- */ 3, /* --D */ 2, /* -O- */ 3, /* should not be used */ /* -OD */ 0, /* =IOD safe because default IBR is harmless */ /* I-- */ 1, /* =IO safe because by defaut OPC is turned off */ /* I-D */ 0, /* =IOD safe because by default opc is turned off */ /* IO- */ 1, /* IOD */ 0 }; /* * IMPORTANT: MUST BE CALLED *AFTER* pfm_dispatch_irange() to make sure we see * the irange programming to adjust pmc41. */ static int pfm_dispatch_drange(pfmlib_input_param_t *inp, pfmlib_mont_input_param_t *mod_in, pfmlib_output_param_t *outp, pfmlib_mont_output_param_t *mod_out) { pfmlib_mont_input_param_t *param = mod_in; pfmlib_reg_t *pc = outp->pfp_pmcs; pfmlib_mont_input_rr_t *irr; pfmlib_mont_output_rr_t *orr, *orr2; pfm_mont_pmc_reg_t pmc38; pfm_mont_pmc_reg_t reg; unsigned int i, pos = outp->pfp_pmc_count; int iod_codes[4], dfl_val_pmc32, dfl_val_pmc34; unsigned int n_intervals; int ret; int base_idx = 0; int fine_mode = 0; #define DR_USED 0x1 /* data range is used */ #define OP_USED 0x2 /* opcode matching is used */ #define IR_USED 0x4 /* code range is used */ if (param == NULL) return PFMLIB_SUCCESS; /* * if only pmc32/pmc33 opcode matching is used, we do not need to change * the default value of pmc41 regardless of the events being measured. */ if ( param->pfp_mont_drange.rr_used == 0 && param->pfp_mont_irange.rr_used == 0) return PFMLIB_SUCCESS; /* * it seems like the ignored bits need to have special values * otherwise this does not work. */ reg.pmc_val = 0x2078fefefefe; /* * initialize iod codes */ iod_codes[0] = iod_codes[1] = iod_codes[2] = iod_codes[3] = 0; /* * setup default iod value, we need to separate because * if drange is used we do not know in advance which DBR will be used * therefore we need to apply dfl_val later */ dfl_val_pmc32 = param->pfp_mont_opcm1.opcm_used ? OP_USED : 0; dfl_val_pmc34 = param->pfp_mont_opcm2.opcm_used ? OP_USED : 0; if (param->pfp_mont_drange.rr_used == 1) { if (mod_out == NULL) return PFMLIB_ERR_INVAL; irr = ¶m->pfp_mont_drange; orr = &mod_out->pfp_mont_drange; ret = check_intervals(irr, 1, &n_intervals); if (ret != PFMLIB_SUCCESS) return ret; if (n_intervals < 1) return PFMLIB_ERR_DRRINVAL; ret = compute_normal_rr(irr, inp->pfp_dfl_plm, n_intervals, &base_idx, orr); if (ret != PFMLIB_SUCCESS) { return ret == PFMLIB_ERR_TOOMANY ? PFMLIB_ERR_DRRTOOMANY : ret; } /* * Update iod_codes to reflect the use of the DBR constraint. */ for (i=0; i < orr->rr_nbr_used; i++) { if (orr->rr_br[i].reg_num == 0) iod_codes[0] |= DR_USED | dfl_val_pmc32; if (orr->rr_br[i].reg_num == 2) iod_codes[1] |= DR_USED | dfl_val_pmc34; if (orr->rr_br[i].reg_num == 4) iod_codes[2] |= DR_USED | dfl_val_pmc32; if (orr->rr_br[i].reg_num == 6) iod_codes[3] |= DR_USED | dfl_val_pmc34; } } /* * XXX: assume dispatch_irange executed before calling this function */ if (param->pfp_mont_irange.rr_used == 1) { orr2 = &mod_out->pfp_mont_irange; if (mod_out == NULL) return PFMLIB_ERR_INVAL; /* * we need to find out whether or not the irange is using * fine mode. If this is the case, then we only need to * program pmc41 for the ibr pairs which designate the lower * bounds of a range. For instance, if IBRP0/IBRP2 are used, * then we only need to program pmc13.cfg_dbrp0 and pmc13.ena_dbrp0, * the PMU will automatically use IBRP2, even though pmc13.ena_dbrp2=0. */ for(i=0; i <= pos; i++) { if (pc[i].reg_num == 38) { pmc38.pmc_val = pc[i].reg_value; if (pmc38.pmc38_mont_reg.iarc_fine == 1) fine_mode = 1; break; } } /* * Update to reflect the use of the IBR constraint */ for (i=0; i < orr2->rr_nbr_used; i++) { if (orr2->rr_br[i].reg_num == 0) iod_codes[0] |= IR_USED | dfl_val_pmc32; if (orr2->rr_br[i].reg_num == 2) iod_codes[1] |= IR_USED | dfl_val_pmc34; if (fine_mode == 0 && orr2->rr_br[i].reg_num == 4) iod_codes[2] |= IR_USED | dfl_val_pmc32; if (fine_mode == 0 && orr2->rr_br[i].reg_num == 6) iod_codes[3] |= IR_USED | dfl_val_pmc34; } } if (param->pfp_mont_irange.rr_used == 0 && param->pfp_mont_drange.rr_used ==0) { iod_codes[0] = iod_codes[2] = dfl_val_pmc32; iod_codes[1] = iod_codes[3] = dfl_val_pmc34; } /* * update the cfg dbrpX field. If we put a constraint on a cfg dbrp, then * we must enable it in the corresponding ena_dbrpX */ reg.pmc41_mont_reg.darc_ena_dbrp0 = iod_codes[0] ? 1 : 0; reg.pmc41_mont_reg.darc_cfg_dtag0 = iod_tab[iod_codes[0]]; reg.pmc41_mont_reg.darc_ena_dbrp1 = iod_codes[1] ? 1 : 0; reg.pmc41_mont_reg.darc_cfg_dtag1 = iod_tab[iod_codes[1]]; reg.pmc41_mont_reg.darc_ena_dbrp2 = iod_codes[2] ? 1 : 0; reg.pmc41_mont_reg.darc_cfg_dtag2 = iod_tab[iod_codes[2]]; reg.pmc41_mont_reg.darc_ena_dbrp3 = iod_codes[3] ? 1 : 0; reg.pmc41_mont_reg.darc_cfg_dtag3 = iod_tab[iod_codes[3]]; if (pfm_regmask_isset(&inp->pfp_unavail_pmcs, 41)) return PFMLIB_ERR_NOASSIGN; pc[pos].reg_num = 41; pc[pos].reg_value = reg.pmc_val; pc[pos].reg_addr = pc[pos].reg_alt_addr = 41; pos++; __pfm_vbprintf("[PMC41(pmc41)=0x%lx cfg_dtag0=%d cfg_dtag1=%d cfg_dtag2=%d cfg_dtag3=%d ena_dbrp0=%d ena_dbrp1=%d ena_dbrp2=%d ena_dbrp3=%d]\n", reg.pmc_val, reg.pmc41_mont_reg.darc_cfg_dtag0, reg.pmc41_mont_reg.darc_cfg_dtag1, reg.pmc41_mont_reg.darc_cfg_dtag2, reg.pmc41_mont_reg.darc_cfg_dtag3, reg.pmc41_mont_reg.darc_ena_dbrp0, reg.pmc41_mont_reg.darc_ena_dbrp1, reg.pmc41_mont_reg.darc_ena_dbrp2, reg.pmc41_mont_reg.darc_ena_dbrp3); outp->pfp_pmc_count = pos; return PFMLIB_SUCCESS; } static int check_qualifier_constraints(pfmlib_input_param_t *inp, pfmlib_mont_input_param_t *mod_in) { pfmlib_mont_input_param_t *param = mod_in; pfmlib_event_t *e = inp->pfp_events; unsigned int i, count; count = inp->pfp_event_count; for(i=0; i < count; i++) { /* * skip check for counter which requested it. Use at your own risk. * No all counters have necessarily been validated for use with * qualifiers. Typically the event is counted as if no constraint * existed. */ if (param->pfp_mont_counters[i].flags & PFMLIB_MONT_FL_EVT_NO_QUALCHECK) continue; if (evt_use_irange(param) && has_iarr(e[i].event) == 0) return PFMLIB_ERR_FEATCOMB; if (evt_use_drange(param) && has_darr(e[i].event) == 0) return PFMLIB_ERR_FEATCOMB; if (evt_use_opcm(param) && has_opcm(e[i].event) == 0) return PFMLIB_ERR_FEATCOMB; } return PFMLIB_SUCCESS; } static int check_range_plm(pfmlib_input_param_t *inp, pfmlib_mont_input_param_t *mod_in) { pfmlib_mont_input_param_t *param = mod_in; unsigned int i, count; if (param->pfp_mont_drange.rr_used == 0 && param->pfp_mont_irange.rr_used == 0) return PFMLIB_SUCCESS; /* * range restriction applies to all events, therefore we must have a consistent * set of plm and they must match the pfp_dfl_plm which is used to setup the debug * registers */ count = inp->pfp_event_count; for(i=0; i < count; i++) { if (inp->pfp_events[i].plm && inp->pfp_events[i].plm != inp->pfp_dfl_plm) return PFMLIB_ERR_FEATCOMB; } return PFMLIB_SUCCESS; } static int pfm_dispatch_ipear(pfmlib_input_param_t *inp, pfmlib_mont_input_param_t *mod_in, pfmlib_output_param_t *outp) { pfm_mont_pmc_reg_t reg; pfmlib_mont_input_param_t *param = mod_in; pfmlib_event_t *e = inp->pfp_events; pfmlib_reg_t *pc, *pd; unsigned int pos1, pos2; unsigned int i, count; pc = outp->pfp_pmcs; pd = outp->pfp_pmds; pos1 = outp->pfp_pmc_count; pos2 = outp->pfp_pmd_count; /* * check if there is something to do */ if (param == NULL || param->pfp_mont_ipear.ipear_used == 0) return PFMLIB_SUCCESS; /* * we need to look for use of ETB, because IP-EAR and ETB cannot be used at the * same time */ if (param->pfp_mont_etb.etb_used) return PFMLIB_ERR_FEATCOMB; /* * look for implicit ETB used because of BRANCH_EVENT */ count = inp->pfp_event_count; for (i=0; i < count; i++) { if (is_etb(e[i].event)) return PFMLIB_ERR_FEATCOMB; } reg.pmc_val = 0; reg.pmc42_mont_reg.ipear_plm = param->pfp_mont_ipear.ipear_plm ? param->pfp_mont_ipear.ipear_plm : inp->pfp_dfl_plm; reg.pmc42_mont_reg.ipear_pm = inp->pfp_flags & PFMLIB_PFP_SYSTEMWIDE ? 1 : 0; reg.pmc42_mont_reg.ipear_mode = 4; reg.pmc42_mont_reg.ipear_delay = param->pfp_mont_ipear.ipear_delay; if (pfm_regmask_isset(&inp->pfp_unavail_pmcs, 42)) return PFMLIB_ERR_NOASSIGN; pc[pos1].reg_num = 42; pc[pos1].reg_value = reg.pmc_val; pc[pos1].reg_addr = pc[pos1].reg_alt_addr = 42; pos1++; __pfm_vbprintf("[PMC42(pmc42)=0x%lx plm=%d pm=%d mode=%d delay=%d]\n", reg.pmc_val, reg.pmc42_mont_reg.ipear_plm, reg.pmc42_mont_reg.ipear_pm, reg.pmc42_mont_reg.ipear_mode, reg.pmc42_mont_reg.ipear_delay); pd[pos2].reg_num = 38; pd[pos2].reg_addr = pd[pos2].reg_alt_addr = 38; pos2++; pd[pos2].reg_num = 39; pd[pos2].reg_addr = pd[pos2].reg_alt_addr = 39; pos2++; __pfm_vbprintf("[PMD38(pmd38)]\n[PMD39(pmd39)\n"); for(i=48; i < 64; i++, pos2++) { pd[pos2].reg_num = i; pd[pos2].reg_addr = pd[pos2].reg_alt_addr = i; __pfm_vbprintf("[PMD%u(pmd%u)]\n", pd[pos2].reg_num, pd[pos2].reg_num); } outp->pfp_pmc_count = pos1; outp->pfp_pmd_count = pos2; return PFMLIB_SUCCESS; } static int pfm_mont_dispatch_events(pfmlib_input_param_t *inp, void *model_in, pfmlib_output_param_t *outp, void *model_out) { int ret; pfmlib_mont_input_param_t *mod_in = (pfmlib_mont_input_param_t *)model_in; pfmlib_mont_output_param_t *mod_out = (pfmlib_mont_output_param_t *)model_out; /* * nothing will come out of this combination */ if (mod_out && mod_in == NULL) return PFMLIB_ERR_INVAL; /* check opcode match, range restriction qualifiers */ if (mod_in && check_qualifier_constraints(inp, mod_in) != PFMLIB_SUCCESS) return PFMLIB_ERR_FEATCOMB; /* check for problems with range restriction and per-event plm */ if (mod_in && check_range_plm(inp, mod_in) != PFMLIB_SUCCESS) return PFMLIB_ERR_FEATCOMB; ret = pfm_mont_dispatch_counters(inp, mod_in, outp); if (ret != PFMLIB_SUCCESS) return ret; /* now check for I-EAR */ ret = pfm_dispatch_iear(inp, mod_in, outp); if (ret != PFMLIB_SUCCESS) return ret; /* now check for D-EAR */ ret = pfm_dispatch_dear(inp, mod_in, outp); if (ret != PFMLIB_SUCCESS) return ret; /* XXX: must be done before dispatch_opcm() and dispatch_drange() */ ret = pfm_dispatch_irange(inp, mod_in, outp, mod_out);; if (ret != PFMLIB_SUCCESS) return ret; ret = pfm_dispatch_drange(inp, mod_in, outp, mod_out);; if (ret != PFMLIB_SUCCESS) return ret; /* now check for Opcode matchers */ ret = pfm_dispatch_opcm(inp, mod_in, outp, mod_out); if (ret != PFMLIB_SUCCESS) return ret; /* now check for ETB */ ret = pfm_dispatch_etb(inp, mod_in, outp); if (ret != PFMLIB_SUCCESS) return ret; /* now check for IP-EAR */ ret = pfm_dispatch_ipear(inp, mod_in, outp); return ret; } /* XXX: return value is also error code */ int pfm_mont_get_event_maxincr(unsigned int i, unsigned int *maxincr) { if (i >= PME_MONT_EVENT_COUNT || maxincr == NULL) return PFMLIB_ERR_INVAL; *maxincr = montecito_pe[i].pme_maxincr; return PFMLIB_SUCCESS; } int pfm_mont_is_ear(unsigned int i) { return i < PME_MONT_EVENT_COUNT && is_ear(i); } int pfm_mont_is_dear(unsigned int i) { return i < PME_MONT_EVENT_COUNT && is_dear(i); } int pfm_mont_is_dear_tlb(unsigned int i) { return i < PME_MONT_EVENT_COUNT && is_dear(i) && is_ear_tlb(i); } int pfm_mont_is_dear_cache(unsigned int i) { return i < PME_MONT_EVENT_COUNT && is_dear(i) && is_ear_cache(i); } int pfm_mont_is_dear_alat(unsigned int i) { return i < PME_MONT_EVENT_COUNT && is_ear_alat(i); } int pfm_mont_is_iear(unsigned int i) { return i < PME_MONT_EVENT_COUNT && is_iear(i); } int pfm_mont_is_iear_tlb(unsigned int i) { return i < PME_MONT_EVENT_COUNT && is_iear(i) && is_ear_tlb(i); } int pfm_mont_is_iear_cache(unsigned int i) { return i < PME_MONT_EVENT_COUNT && is_iear(i) && is_ear_cache(i); } int pfm_mont_is_etb(unsigned int i) { return i < PME_MONT_EVENT_COUNT && is_etb(i); } int pfm_mont_support_iarr(unsigned int i) { return i < PME_MONT_EVENT_COUNT && has_iarr(i); } int pfm_mont_support_darr(unsigned int i) { return i < PME_MONT_EVENT_COUNT && has_darr(i); } int pfm_mont_support_opcm(unsigned int i) { return i < PME_MONT_EVENT_COUNT && has_opcm(i); } int pfm_mont_support_all(unsigned int i) { return i < PME_MONT_EVENT_COUNT && has_all(i); } int pfm_mont_get_ear_mode(unsigned int i, pfmlib_mont_ear_mode_t *m) { pfmlib_mont_ear_mode_t r; if (!is_ear(i) || m == NULL) return PFMLIB_ERR_INVAL; r = PFMLIB_MONT_EAR_TLB_MODE; if (is_ear_tlb(i)) goto done; r = PFMLIB_MONT_EAR_CACHE_MODE; if (is_ear_cache(i)) goto done; r = PFMLIB_MONT_EAR_ALAT_MODE; if (is_ear_alat(i)) goto done; return PFMLIB_ERR_INVAL; done: *m = r; return PFMLIB_SUCCESS; } static int pfm_mont_get_event_code(unsigned int i, unsigned int cnt, int *code) { if (cnt != PFMLIB_CNT_FIRST && (cnt < 4 || cnt > 15)) return PFMLIB_ERR_INVAL; *code = (int)montecito_pe[i].pme_code; return PFMLIB_SUCCESS; } /* * This function is accessible directly to the user */ int pfm_mont_get_event_umask(unsigned int i, unsigned long *umask) { if (i >= PME_MONT_EVENT_COUNT || umask == NULL) return PFMLIB_ERR_INVAL; *umask = evt_umask(i); return PFMLIB_SUCCESS; } int pfm_mont_get_event_group(unsigned int i, int *grp) { if (i >= PME_MONT_EVENT_COUNT || grp == NULL) return PFMLIB_ERR_INVAL; *grp = evt_grp(i); return PFMLIB_SUCCESS; } int pfm_mont_get_event_set(unsigned int i, int *set) { if (i >= PME_MONT_EVENT_COUNT || set == NULL) return PFMLIB_ERR_INVAL; *set = evt_set(i) == 0xf ? PFMLIB_MONT_EVT_NO_SET : evt_set(i); return PFMLIB_SUCCESS; } int pfm_mont_get_event_type(unsigned int i, int *type) { if (i >= PME_MONT_EVENT_COUNT || type == NULL) return PFMLIB_ERR_INVAL; *type = evt_caf(i); return PFMLIB_SUCCESS; } /* external interface */ int pfm_mont_irange_is_fine(pfmlib_output_param_t *outp, pfmlib_mont_output_param_t *mod_out) { pfmlib_mont_output_param_t *param = mod_out; pfm_mont_pmc_reg_t reg; unsigned int i, count; /* some sanity checks */ if (outp == NULL || param == NULL) return 0; if (outp->pfp_pmc_count >= PFMLIB_MAX_PMCS) return 0; if (param->pfp_mont_irange.rr_nbr_used == 0) return 0; /* * we look for pmc38 as it contains the bit indicating if fine mode is used */ count = outp->pfp_pmc_count; for(i=0; i < count; i++) { if (outp->pfp_pmcs[i].reg_num == 38) goto found; } return 0; found: reg.pmc_val = outp->pfp_pmcs[i].reg_value; return reg.pmc38_mont_reg.iarc_fine ? 1 : 0; } static char * pfm_mont_get_event_name(unsigned int i) { return montecito_pe[i].pme_name; } static void pfm_mont_get_event_counters(unsigned int j, pfmlib_regmask_t *counters) { unsigned int i; unsigned long m; memset(counters, 0, sizeof(*counters)); m =montecito_pe[j].pme_counters; for(i=0; m ; i++, m>>=1) { if (m & 0x1) pfm_regmask_set(counters, i); } } static void pfm_mont_get_impl_pmcs(pfmlib_regmask_t *impl_pmcs) { unsigned int i = 0; for(i=0; i < 16; i++) pfm_regmask_set(impl_pmcs, i); for(i=32; i < 43; i++) pfm_regmask_set(impl_pmcs, i); } static void pfm_mont_get_impl_pmds(pfmlib_regmask_t *impl_pmds) { unsigned int i = 0; for(i=4; i < 16; i++) pfm_regmask_set(impl_pmds, i); for(i=32; i < 40; i++) pfm_regmask_set(impl_pmds, i); for(i=48; i < 64; i++) pfm_regmask_set(impl_pmds, i); } static void pfm_mont_get_impl_counters(pfmlib_regmask_t *impl_counters) { unsigned int i = 0; /* counter pmds are contiguous */ for(i=4; i < 16; i++) pfm_regmask_set(impl_counters, i); } static void pfm_mont_get_hw_counter_width(unsigned int *width) { *width = PMU_MONT_COUNTER_WIDTH; } static int pfm_mont_get_event_description(unsigned int ev, char **str) { char *s; s = montecito_pe[ev].pme_desc; if (s) { *str = strdup(s); } else { *str = NULL; } return PFMLIB_SUCCESS; } static int pfm_mont_get_cycle_event(pfmlib_event_t *e) { e->event = PME_MONT_CPU_OP_CYCLES_ALL; return PFMLIB_SUCCESS; } static int pfm_mont_get_inst_retired(pfmlib_event_t *e) { e->event = PME_MONT_IA64_INST_RETIRED; return PFMLIB_SUCCESS; } static unsigned int pfm_mont_get_num_event_masks(unsigned int event) { return has_mesi(event) ? 4 : 0; } static char * pfm_mont_get_event_mask_name(unsigned int event, unsigned int mask) { switch(mask) { case 0: return "I"; case 1: return "S"; case 2: return "E"; case 3: return "M"; } return NULL; } static int pfm_mont_get_event_mask_desc(unsigned int event, unsigned int mask, char **desc) { switch(mask) { case 0: *desc = strdup("invalid"); break; case 1: *desc = strdup("shared"); break; case 2: *desc = strdup("exclusive"); break; case 3: *desc = strdup("modified"); break; default: return PFMLIB_ERR_INVAL; } return PFMLIB_SUCCESS; } static int pfm_mont_get_event_mask_code(unsigned int event, unsigned int mask, unsigned int *code) { *code = mask; return PFMLIB_SUCCESS; } pfm_pmu_support_t montecito_support={ .pmu_name = "dual-core Itanium 2", .pmu_type = PFMLIB_MONTECITO_PMU, .pme_count = PME_MONT_EVENT_COUNT, .pmc_count = PMU_MONT_NUM_PMCS, .pmd_count = PMU_MONT_NUM_PMDS, .num_cnt = PMU_MONT_NUM_COUNTERS, .get_event_code = pfm_mont_get_event_code, .get_event_name = pfm_mont_get_event_name, .get_event_counters = pfm_mont_get_event_counters, .dispatch_events = pfm_mont_dispatch_events, .pmu_detect = pfm_mont_detect, .get_impl_pmcs = pfm_mont_get_impl_pmcs, .get_impl_pmds = pfm_mont_get_impl_pmds, .get_impl_counters = pfm_mont_get_impl_counters, .get_hw_counter_width = pfm_mont_get_hw_counter_width, .get_event_desc = pfm_mont_get_event_description, .get_cycle_event = pfm_mont_get_cycle_event, .get_inst_retired_event = pfm_mont_get_inst_retired, .get_num_event_masks = pfm_mont_get_num_event_masks, .get_event_mask_name = pfm_mont_get_event_mask_name, .get_event_mask_desc = pfm_mont_get_event_mask_desc, .get_event_mask_code = pfm_mont_get_event_mask_code }; libpfm-4.9.0/lib/pfmlib_s390x_cpumf.c0000664000175000017500000002076613223402656017154 0ustar eranianeranian/* * PMU support for the CPU-measurement facilities * * Copyright IBM Corp. 2012, 2014 * Contributed by Hendrik Brueckner * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include /* private library and arch headers */ #include "pfmlib_priv.h" #include "pfmlib_s390x_priv.h" #include "pfmlib_perf_event_priv.h" #include "events/s390x_cpumf_events.h" #define CPUM_CF_DEVICE_DIR "/sys/bus/event_source/devices/cpum_cf" #define CPUM_SF_DEVICE_DIR "/sys/bus/event_source/devices/cpum_sf" #define SYS_INFO "/proc/sysinfo" /* CPU-measurement counter list (pmu events) */ static pme_cpumf_ctr_t *cpumcf_pe = NULL; /* Detect the CPU-measurement counter and sampling facilities */ static int pfm_cpumcf_detect(void *this) { if (access(CPUM_CF_DEVICE_DIR, R_OK)) return PFM_ERR_NOTSUPP; return PFM_SUCCESS; } static int pfm_cpumsf_detect(void *this) { if (access(CPUM_SF_DEVICE_DIR, R_OK)) return PFM_ERR_NOTSUPP; return PFM_SUCCESS; } /* Parses the machine type that identifies an IBM mainframe. * These kind of information are from /proc/sysinfo. */ static long get_machine_type(void) { long machine_type; size_t buflen, len; char *buffer, *tmp; FILE *fp; machine_type = 0; fp = fopen(SYS_INFO, "r"); if (fp == NULL) goto out; buffer = NULL; while (pfmlib_getl(&buffer, &buflen, fp) != -1) { /* skip empty lines */ if (*buffer == '\n') continue; /* look for 'Type:' entry */ if (!strncmp("Type:", buffer, 5)) { tmp = buffer + 5; /* set ptr after ':' */ /* skip leading blanks */ while (isspace(*tmp)) tmp++; /* skip trailing blanks */ len = strlen(tmp); while (len > 0 && isspace(tmp[len])) len--; tmp[len+1] = '\0'; machine_type = strtol(tmp, NULL, 10); break; } } fclose(fp); free(buffer); out: return machine_type; } /* Initialize the PMU representation for CPUMF. * * Set up the PMU events array based on * - generic (basic, problem-state, and crypto-activaty) counter sets * - the extended counter depending on the machine type */ static int pfm_cpumcf_init(void *this) { pfmlib_pmu_t *pmu = this; const pme_cpumf_ctr_t *ext_set; size_t generic_count, ext_set_count; /* check and assign a machine-specific extended counter set */ switch (get_machine_type()) { case 2097: /* IBM System z10 EC */ case 2098: /* IBM System z10 BC */ ext_set = cpumcf_z10_counters, ext_set_count = LIBPFM_ARRAY_SIZE(cpumcf_z10_counters); break; case 2817: /* IBM zEnterprise 196 */ case 2818: /* IBM zEnterprise 114 */ ext_set = cpumcf_z196_counters; ext_set_count = LIBPFM_ARRAY_SIZE(cpumcf_z196_counters); break; case 2827: /* IBM zEnterprise EC12 */ case 2828: /* IBM zEnterprise BC12 */ ext_set = cpumcf_zec12_counters; ext_set_count = LIBPFM_ARRAY_SIZE(cpumcf_zec12_counters); break; case 2964: /* IBM z13 */ case 2965: /* IBM z13s */ ext_set = cpumcf_z13_counters; ext_set_count = LIBPFM_ARRAY_SIZE(cpumcf_z13_counters); break; default: /* No extended counter set for this machine type or there * was an error retrieving the machine type */ ext_set = NULL; ext_set_count = 0; break; } generic_count = LIBPFM_ARRAY_SIZE(cpumcf_generic_counters); cpumcf_pe = calloc(sizeof(*cpumcf_pe), generic_count + ext_set_count); if (cpumcf_pe == NULL) return PFM_ERR_NOMEM; memcpy(cpumcf_pe, cpumcf_generic_counters, sizeof(*cpumcf_pe) * generic_count); if (ext_set_count) memcpy((void *) (cpumcf_pe + generic_count), ext_set, sizeof(*cpumcf_pe) * ext_set_count); pmu->pe = cpumcf_pe; pmu->pme_count = generic_count + ext_set_count; return PFM_SUCCESS; } static void pfm_cpumcf_exit(void *this) { pfmlib_pmu_t *pmu = this; pmu->pme_count = 0; pmu->pe = NULL; free(cpumcf_pe); } static int pfm_cpumf_get_encoding(void *this, pfmlib_event_desc_t *e) { const pme_cpumf_ctr_t *pe = this_pe(this); e->count = 1; /* number of encoded entries in e->codes */ e->codes[0] = pe[e->event].ctrnum; evt_strcat(e->fstr, "%s", pe[e->event].name); return PFM_SUCCESS; } static int pfm_cpumf_get_event_first(void *this) { return 0; } static int pfm_cpumf_get_event_next(void *this, int idx) { pfmlib_pmu_t *pmu = this; if (idx >= (pmu->pme_count - 1)) return -1; return idx + 1; } static int pfm_cpumf_event_is_valid(void *this, int idx) { pfmlib_pmu_t *pmu = this; return (idx >= 0 && idx < pmu->pme_count); } static int pfm_cpumf_validate_table(void *this, FILE *fp) { pfmlib_pmu_t *pmu = this; const pme_cpumf_ctr_t *pe = this_pe(this); int i, rc; rc = PFM_ERR_INVAL; for (i = 0; i < pmu->pme_count; i++) { if (!pe[i].name) { fprintf(fp, "pmu: %s event: %i: No name\n", pmu->name, i); goto failed; } if (!pe[i].desc) { fprintf(fp, "pmu: %s event: %i: No description\n", pmu->name, i); goto failed; } } rc = PFM_SUCCESS; failed: return rc; } static int pfm_cpumcf_validate_table(void *this, FILE *fp) { pfmlib_pmu_t *pmu = this; if (pmu->pme_count > CPUMF_COUNTER_MAX) { fprintf(fp, "pmu: %s: pme number exceeded maximum\n", pmu->name); return PFM_ERR_INVAL; } return pfm_cpumf_validate_table(this, fp); } static int pfm_cpumf_get_event_info(void *this, int idx, pfm_event_info_t *info) { pfmlib_pmu_t *pmu = this; const pme_cpumf_ctr_t *pe = this_pe(this); info->name = pe[idx].name; info->desc = pe[idx].desc; info->code = pe[idx].ctrnum; info->equiv = NULL; info->idx = idx; info->pmu = pmu->pmu; info->is_precise = 0; info->nattrs = 0; /* attributes are not supported */ return PFM_SUCCESS; } static int pfm_cpumf_get_event_attr_info(void *this, int idx, int umask_idx, pfmlib_event_attr_info_t *info) { /* Attributes are not supported */ return PFM_ERR_ATTR; } pfmlib_pmu_t s390x_cpum_cf_support = { .desc = "CPU-measurement counter facility", .name = "cpum_cf", .pmu = PFM_PMU_S390X_CPUM_CF, .type = PFM_PMU_TYPE_CORE, .flags = PFMLIB_PMU_FL_ARCH_DFL, .num_cntrs = 0, /* no general-purpose counters */ .num_fixed_cntrs = CPUMF_COUNTER_MAX, /* fixed counters only */ .max_encoding = 1, .pe = cpumcf_generic_counters, .pme_count = LIBPFM_ARRAY_SIZE(cpumcf_generic_counters), .pmu_detect = pfm_cpumcf_detect, .pmu_init = pfm_cpumcf_init, .pmu_terminate = pfm_cpumcf_exit, .get_event_encoding[PFM_OS_NONE] = pfm_cpumf_get_encoding, PFMLIB_ENCODE_PERF(pfm_s390x_get_perf_encoding), .get_event_first = pfm_cpumf_get_event_first, .get_event_next = pfm_cpumf_get_event_next, .event_is_valid = pfm_cpumf_event_is_valid, .validate_table = pfm_cpumcf_validate_table, .get_event_info = pfm_cpumf_get_event_info, .get_event_attr_info = pfm_cpumf_get_event_attr_info, }; pfmlib_pmu_t s390x_cpum_sf_support = { .desc = "CPU-measurement sampling facility", .name = "cpum_sf", .pmu = PFM_PMU_S390X_CPUM_SF, .type = PFM_PMU_TYPE_CORE, .flags = PFMLIB_PMU_FL_ARCH_DFL, .num_cntrs = 0, /* no general-purpose counters */ .num_fixed_cntrs = 2, /* fixed counters only */ .max_encoding = 1, .pe = cpumsf_counters, .pme_count = LIBPFM_ARRAY_SIZE(cpumsf_counters), .pmu_detect = pfm_cpumsf_detect, .get_event_encoding[PFM_OS_NONE] = pfm_cpumf_get_encoding, PFMLIB_ENCODE_PERF(pfm_s390x_get_perf_encoding), .get_event_first = pfm_cpumf_get_event_first, .get_event_next = pfm_cpumf_get_event_next, .event_is_valid = pfm_cpumf_event_is_valid, .validate_table = pfm_cpumf_validate_table, .get_event_info = pfm_cpumf_get_event_info, .get_event_attr_info = pfm_cpumf_get_event_attr_info, }; libpfm-4.9.0/lib/pfmlib_intel_ivbep_unc_qpi.c0000664000175000017500000000626013223402656021103 0ustar eranianeranian/* * pfmlib_intel_ivbep_qpi.c : Intel IvyBridge-EP QPI uncore PMU * * Copyright (c) 2014 Google Inc. All rights reserved * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_intel_x86_priv.h" #include "pfmlib_intel_snbep_unc_priv.h" #include "events/intel_ivbep_unc_qpi_events.h" static void display_qpi(void *this, pfmlib_event_desc_t *e, void *val) { const intel_x86_entry_t *pe = this_pe(this); pfm_snbep_unc_reg_t *reg = val; __pfm_vbprintf("[UNC_QPI=0x%"PRIx64" event=0x%x sel_ext=%d umask=0x%x en=%d " "inv=%d edge=%d thres=%d] %s\n", reg->val, reg->qpi.unc_event, reg->qpi.unc_event_ext, reg->qpi.unc_umask, reg->qpi.unc_en, reg->qpi.unc_inv, reg->qpi.unc_edge, reg->qpi.unc_thres, pe[e->event].name); } #define DEFINE_QPI_BOX(n) \ pfmlib_pmu_t intel_ivbep_unc_qpi##n##_support = {\ .desc = "Intel Ivy Bridge-EP QPI"#n" uncore",\ .name = "ivbep_unc_qpi"#n,\ .perf_name = "uncore_qpi_"#n,\ .pmu = PFM_PMU_INTEL_IVBEP_UNC_QPI##n,\ .pme_count = LIBPFM_ARRAY_SIZE(intel_ivbep_unc_q_pe),\ .type = PFM_PMU_TYPE_UNCORE,\ .num_cntrs = 4,\ .num_fixed_cntrs = 0,\ .max_encoding = 3,\ .pe = intel_ivbep_unc_q_pe,\ .atdesc = snbep_unc_mods,\ .flags = PFMLIB_PMU_FL_RAW_UMASK,\ .pmu_detect = pfm_intel_ivbep_unc_detect,\ .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding,\ PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding),\ PFMLIB_OS_DETECT(pfm_intel_x86_perf_detect), \ .get_event_first = pfm_intel_x86_get_event_first,\ .get_event_next = pfm_intel_x86_get_event_next,\ .event_is_valid = pfm_intel_x86_event_is_valid,\ .validate_table = pfm_intel_x86_validate_table,\ .get_event_info = pfm_intel_x86_get_event_info,\ .get_event_attr_info = pfm_intel_x86_get_event_attr_info,\ PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs),\ .get_event_nattrs = pfm_intel_x86_get_event_nattrs,\ .display_reg = display_qpi,\ } DEFINE_QPI_BOX(0); DEFINE_QPI_BOX(1); DEFINE_QPI_BOX(2); libpfm-4.9.0/lib/pfmlib_mips_74k.c0000664000175000017500000000551413223402656016523 0ustar eranianeranian/* * pfmlib_mips_74k.c : support for MIPS chips * * Copyright (c) 2011 Samara Technology Group, Inc * Contributed by Philip Mucci * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ #include #include #include "pfmlib_priv.h" /* library private */ #include "pfmlib_mips_priv.h" #include "events/mips_74k_events.h" /* event tables */ /* root@redhawk_RT-N16:/proc# more cpuinfo system type : Broadcom BCM4716 chip rev 1 processor : 0 cpu model : MIPS 74K V4.0 BogoMIPS : 239.20 wait instruction : no microsecond timers : yes tlb_entries : 64 */ static int pfm_mips_detect_74k(void *this) { int ret; DPRINT("mips_detect_74k\n"); ret = pfm_mips_detect(this); if (ret != PFM_SUCCESS) return PFM_ERR_NOTSUPP; if (strstr(pfm_mips_cfg.model,"MIPS 74K")) return PFM_SUCCESS; return PFM_ERR_NOTSUPP; } /* Cortex A8 support */ pfmlib_pmu_t mips_74k_support={ .desc = "MIPS 74k", .name = "mips_74k", .pmu = PFM_PMU_MIPS_74K, .pme_count = LIBPFM_ARRAY_SIZE(mips_74k_pe), .type = PFM_PMU_TYPE_CORE, .pe = mips_74k_pe, .pmu_detect = pfm_mips_detect_74k, .max_encoding = 2, /* event encoding + counter bitmask */ .num_cntrs = 4, .get_event_encoding[PFM_OS_NONE] = pfm_mips_get_encoding, PFMLIB_ENCODE_PERF(pfm_mips_get_perf_encoding), .get_event_first = pfm_mips_get_event_first, .get_event_next = pfm_mips_get_event_next, .event_is_valid = pfm_mips_event_is_valid, .validate_table = pfm_mips_validate_table, .get_event_info = pfm_mips_get_event_info, .get_event_attr_info = pfm_mips_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_mips_perf_validate_pattrs), .get_event_nattrs = pfm_mips_get_event_nattrs, .supported_plm = PFM_PLM0|PFM_PLM3|PFM_PLMH, }; libpfm-4.9.0/lib/pfmlib_intel_hswep_unc_irp.c0000664000175000017500000000575213223402656021132 0ustar eranianeranian /* * pfmlib_intel_hswep_irp.c : Intel Haswell-EP IRP uncore PMU * * Copyright (c) 2014 Google Inc. All rights reserved * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_intel_x86_priv.h" #include "pfmlib_intel_snbep_unc_priv.h" #include "events/intel_hswep_unc_irp_events.h" static void display_irp(void *this, pfmlib_event_desc_t *e, void *val) { const intel_x86_entry_t *pe = this_pe(this); pfm_snbep_unc_reg_t *reg = val; __pfm_vbprintf("[UNC_IRP=0x%"PRIx64" event=0x%x umask=0x%x en=%d " "edge=%d thres=%d] %s\n", reg->val, reg->irp.unc_event, reg->irp.unc_umask, reg->irp.unc_en, reg->irp.unc_edge, reg->irp.unc_thres, pe[e->event].name); } pfmlib_pmu_t intel_hswep_unc_irp_support = { .desc = "Intel Haswell-EP IRP uncore", .name = "hswep_unc_irp", .perf_name = "uncore_irp", .pmu = PFM_PMU_INTEL_HSWEP_UNC_IRP, .pme_count = LIBPFM_ARRAY_SIZE(intel_hswep_unc_i_pe), .type = PFM_PMU_TYPE_UNCORE, .num_cntrs = 4, .num_fixed_cntrs = 0, .max_encoding = 3, .pe = intel_hswep_unc_i_pe, .atdesc = snbep_unc_mods, .flags = PFMLIB_PMU_FL_RAW_UMASK, .pmu_detect = pfm_intel_hswep_unc_detect, .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding, PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding), PFMLIB_OS_DETECT(pfm_intel_x86_perf_detect), .get_event_first = pfm_intel_x86_get_event_first, .get_event_next = pfm_intel_x86_get_event_next, .event_is_valid = pfm_intel_x86_event_is_valid, .validate_table = pfm_intel_x86_validate_table, .get_event_info = pfm_intel_x86_get_event_info, .get_event_attr_info = pfm_intel_x86_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs), .get_event_nattrs = pfm_intel_x86_get_event_nattrs, .display_reg = display_irp, }; libpfm-4.9.0/lib/pfmlib_intel_snbep_unc_perf_event.c0000664000175000017500000001002313223402656022441 0ustar eranianeranian/* pfmlib_intel_snbep_unc_perf.c : perf_events SNB-EP uncore support * * Copyright (c) 2012 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include #include /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_intel_x86_priv.h" #include "pfmlib_intel_snbep_unc_priv.h" #include "pfmlib_perf_event_priv.h" static int find_pmu_type_by_name(const char *name) { char filename[PATH_MAX]; FILE *fp; int ret, type; if (!name) return PFM_ERR_NOTSUPP; sprintf(filename, "/sys/bus/event_source/devices/%s/type", name); fp = fopen(filename, "r"); if (!fp) return PFM_ERR_NOTSUPP; ret = fscanf(fp, "%d", &type); if (ret != 1) type = PFM_ERR_NOTSUPP; fclose(fp); return type; } int pfm_intel_snbep_unc_get_perf_encoding(void *this, pfmlib_event_desc_t *e) { pfmlib_pmu_t *pmu = this; struct perf_event_attr *attr = e->os_data; pfm_intel_x86_reg_t reg; int ret; if (!pmu->get_event_encoding[PFM_OS_NONE]) return PFM_ERR_NOTSUPP; ret = pmu->get_event_encoding[PFM_OS_NONE](this, e); if (ret != PFM_SUCCESS) return ret; ret = find_pmu_type_by_name(pmu->perf_name); if (ret < 0) return ret; attr->type = ret; reg.val = e->codes[0]; attr->config = reg.val; if (is_cbo_filt_event(this, reg) && e->count > 1) { if (e->count >= 2) attr->config1 = e->codes[1]; if (e->count >= 3) attr->config1 |= e->codes[2] << 32; } else { /* * various filters */ if (e->count >= 2) attr->config1 = e->codes[1]; if (e->count >= 3) attr->config2 = e->codes[2]; } /* * uncore measures at all priv levels * * user cannot set per-event priv levels because * attributes are simply not there * * dfl_plm is ignored in this case */ attr->exclude_hv = 0; attr->exclude_kernel = 0; attr->exclude_user = 0; return PFM_SUCCESS; } void pfm_intel_snbep_unc_perf_validate_pattrs(void *this, pfmlib_event_desc_t *e) { pfmlib_pmu_t *pmu = this; int no_smpl = pmu->flags & PFMLIB_PMU_FL_NO_SMPL; int i, compact; for (i = 0; i < e->npattrs; i++) { compact = 0; /* umasks never conflict */ if (e->pattrs[i].type == PFM_ATTR_UMASK) continue; if (e->pattrs[i].ctrl == PFM_ATTR_CTRL_PERF_EVENT) { /* No precise sampling mode for uncore */ if (e->pattrs[i].idx == PERF_ATTR_PR) compact = 1; /* * No hypervisor for uncore */ if (e->pattrs[i].idx == PERF_ATTR_H) compact = 1; if (no_smpl && ( e->pattrs[i].idx == PERF_ATTR_FR || e->pattrs[i].idx == PERF_ATTR_PR || e->pattrs[i].idx == PERF_ATTR_PE)) compact = 1; /* * uncore has no priv level support */ if (pmu->supported_plm == 0 && ( e->pattrs[i].idx == PERF_ATTR_U || e->pattrs[i].idx == PERF_ATTR_K || e->pattrs[i].idx == PERF_ATTR_MG || e->pattrs[i].idx == PERF_ATTR_MH)) compact = 1; } if (compact) { pfmlib_compact_pattrs(e, i); i--; } } } libpfm-4.9.0/lib/pfmlib_mips_perf_event.c0000664000175000017500000000640413223402656020252 0ustar eranianeranian/* * pfmlib_mips_perf_event.c : perf_event MIPS functions * * Copyright (c) 2011 Samara Technology Group, Inc * Contributed by Philip Mucci * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include "pfmlib_priv.h" #include "pfmlib_mips_priv.h" #include "pfmlib_perf_event_priv.h" int pfm_mips_get_perf_encoding(void *this, pfmlib_event_desc_t *e) { struct perf_event_attr *attr = e->os_data; int ret; ret = pfm_mips_get_encoding(this, e); if (ret != PFM_SUCCESS) return ret; if (e->count != 2) { DPRINT("unexpected encoding count=%d\n", e->count); return PFM_ERR_INVAL; } attr->type = PERF_TYPE_RAW; /* * priv levels are ignored because they are managed * directly through perf excl_*. */ attr->config = e->codes[0] >> 5; /* * codes[1] contains counter mask supported by the event. * Events support either odd or even indexed counters * except for cycles (code = 0) and instructions (code =1) * which work on all counters. * * The kernel expects bit 7 of config to indicate whether * the event works only on odd-indexed counters */ if ((e->codes[1] & 0x2) && attr->config > 1) attr->config |= 1ULL << 7; return PFM_SUCCESS; } void pfm_mips_perf_validate_pattrs(void *this, pfmlib_event_desc_t *e) { int i, compact; for (i = 0; i < e->npattrs; i++) { compact = 0; /* umasks never conflict */ if (e->pattrs[i].type == PFM_ATTR_UMASK) continue; /* * remove PMU-provided attributes which are either * not accessible under perf_events or fully controlled * by perf_events, e.g., priv levels filters */ if (e->pattrs[i].ctrl == PFM_ATTR_CTRL_PMU) { /* * with perf_event, priv levels under full * control of perf_event. */ if ( e->pattrs[i].idx == MIPS_ATTR_K ||e->pattrs[i].idx == MIPS_ATTR_U ||e->pattrs[i].idx == MIPS_ATTR_S ||e->pattrs[i].idx == MIPS_ATTR_E) compact = 1; } /* * remove perf_event generic attributes not supported * by MIPS */ if (e->pattrs[i].ctrl == PFM_ATTR_CTRL_PERF_EVENT) { /* no precise sampling on MIPS */ if (e->pattrs[i].idx == PERF_ATTR_PR) compact = 1; } if (compact) { pfmlib_compact_pattrs(e, i); i--; } } } libpfm-4.9.0/lib/pfmlib_intel_hswep_unc_r3qpi.c0000664000175000017500000000624213223402656021371 0ustar eranianeranian/* * pfmlib_intel_hswep_r3qpi.c : Intel Haswell-EP R3QPI uncore PMU * * Copyright (c) 2014 Google Inc. All rights reserved * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_intel_x86_priv.h" #include "pfmlib_intel_snbep_unc_priv.h" #include "events/intel_hswep_unc_r3qpi_events.h" static void display_r3(void *this, pfmlib_event_desc_t *e, void *val) { const intel_x86_entry_t *pe = this_pe(this); pfm_snbep_unc_reg_t *reg = val; __pfm_vbprintf("[UNC_R3QPI=0x%"PRIx64" event=0x%x umask=0x%x en=%d " "inv=%d edge=%d thres=%d] %s\n", reg->val, reg->com.unc_event, reg->com.unc_umask, reg->com.unc_en, reg->com.unc_inv, reg->com.unc_edge, reg->com.unc_thres, pe[e->event].name); } #define DEFINE_R3QPI_BOX(n) \ pfmlib_pmu_t intel_hswep_unc_r3qpi##n##_support = {\ .desc = "Intel Haswell-EP R3QPI"#n" uncore", \ .name = "hswep_unc_r3qpi"#n,\ .perf_name = "uncore_r3qpi_"#n, \ .pmu = PFM_PMU_INTEL_HSWEP_UNC_R3QPI##n, \ .pme_count = LIBPFM_ARRAY_SIZE(intel_hswep_unc_r3_pe),\ .type = PFM_PMU_TYPE_UNCORE,\ .num_cntrs = 3,\ .num_fixed_cntrs = 0,\ .max_encoding = 1,\ .pe = intel_hswep_unc_r3_pe,\ .atdesc = snbep_unc_mods,\ .flags = PFMLIB_PMU_FL_RAW_UMASK,\ .pmu_detect = pfm_intel_hswep_unc_detect,\ .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding,\ PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding),\ PFMLIB_OS_DETECT(pfm_intel_x86_perf_detect), \ .get_event_first = pfm_intel_x86_get_event_first,\ .get_event_next = pfm_intel_x86_get_event_next,\ .event_is_valid = pfm_intel_x86_event_is_valid,\ .validate_table = pfm_intel_x86_validate_table,\ .get_event_info = pfm_intel_x86_get_event_info,\ .get_event_attr_info = pfm_intel_x86_get_event_attr_info,\ PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs),\ .get_event_nattrs = pfm_intel_x86_get_event_nattrs,\ .display_reg = display_r3,\ } DEFINE_R3QPI_BOX(0); DEFINE_R3QPI_BOX(1); DEFINE_R3QPI_BOX(2); libpfm-4.9.0/lib/pfmlib_intel_wsm.c0000664000175000017500000000755513223402656017076 0ustar eranianeranian/* * pfmlib_intel_wsm.c : Intel Westmere core PMU * * Copyright (c) 2009 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_intel_x86_priv.h" #include "events/intel_wsm_events.h" static const int wsm_models[] = { 37, /* Clarkdale */ 0, }; static const int wsm_dp_models[] = { 44, /* Westmere-EP, Gulftown */ 47, /* Westmere E7 */ 0, }; static int pfm_wsm_init(void *this) { pfm_intel_x86_cfg.arch_version = 3; return PFM_SUCCESS; } pfmlib_pmu_t intel_wsm_sp_support={ .desc = "Intel Westmere (single-socket)", .name = "wsm", .pmu = PFM_PMU_INTEL_WSM, .pme_count = LIBPFM_ARRAY_SIZE(intel_wsm_pe), .type = PFM_PMU_TYPE_CORE, .supported_plm = INTEL_X86_PLM, .num_cntrs = 4, .num_fixed_cntrs = 3, .max_encoding = 2, /* because of OFFCORE_RESPONSE */ .pe = intel_wsm_pe, .atdesc = intel_x86_mods, .flags = PFMLIB_PMU_FL_RAW_UMASK | INTEL_X86_PMU_FL_ECMASK, .cpu_family = 6, .cpu_models = wsm_models, .pmu_detect = pfm_intel_x86_model_detect, .pmu_init = pfm_wsm_init, .get_event_encoding[PFM_OS_NONE] = pfm_intel_x86_get_encoding, PFMLIB_ENCODE_PERF(pfm_intel_x86_get_perf_encoding), .get_event_first = pfm_intel_x86_get_event_first, .get_event_next = pfm_intel_x86_get_event_next, .event_is_valid = pfm_intel_x86_event_is_valid, .validate_table = pfm_intel_x86_validate_table, .get_event_info = pfm_intel_x86_get_event_info, .get_event_attr_info = pfm_intel_x86_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_intel_x86_perf_validate_pattrs), .get_event_nattrs = pfm_intel_x86_get_event_nattrs, .can_auto_encode = pfm_intel_x86_can_auto_encode, }; pfmlib_pmu_t intel_wsm_dp_support={ .desc = "Intel Westmere DP", .name = "wsm_dp", .pmu = PFM_PMU_INTEL_WSM_DP, .pme_count = LIBPFM_ARRAY_SIZE(intel_wsm_pe), .type = PFM_PMU_TYPE_CORE, .supported_plm = INTEL_X86_PLM, .num_cntrs = 4, .num_fixed_cntrs = 3, .max_encoding = 2, /* because of OFFCORE_RESPONSE */ .pe = intel_wsm_pe, .atdesc = intel_x86_mods, .flags = PFMLIB_PMU_FL_RAW_UMASK | INTEL_X86_PMU_FL_ECMASK, .cpu_family = 6, .cpu_models = wsm_dp_models, .pmu_detect = pfm_intel_x86_model_detect, .pmu_init = pfm_wsm_init, .get_event_encoding[PFM_OS_NONE] = pfm_intel_x86_get_encoding, PFMLIB_ENCODE_PERF(pfm_intel_x86_get_perf_encoding), .get_event_first = pfm_intel_x86_get_event_first, .get_event_next = pfm_intel_x86_get_event_next, .event_is_valid = pfm_intel_x86_event_is_valid, .validate_table = pfm_intel_x86_validate_table, .get_event_info = pfm_intel_x86_get_event_info, .get_event_attr_info = pfm_intel_x86_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_intel_x86_perf_validate_pattrs), .get_event_nattrs = pfm_intel_x86_get_event_nattrs, .can_auto_encode = pfm_intel_x86_can_auto_encode, }; libpfm-4.9.0/lib/pfmlib_amd64_fam15h.c0000664000175000017500000000657513223402656017152 0ustar eranianeranian/* * pfmlib_amd64_fam15h.c : AMD64 Family 15h * * Copyright (c) 2011 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_amd64_priv.h" #include "events/amd64_events_fam15h.h" #include "events/amd64_events_fam15h_nb.h" pfmlib_pmu_t amd64_fam15h_interlagos_support={ .desc = "AMD64 Fam15h Interlagos", .name = "amd64_fam15h_interlagos", .pmu = PFM_PMU_AMD64_FAM15H_INTERLAGOS, .pmu_rev = 0, .pme_count = LIBPFM_ARRAY_SIZE(amd64_fam15h_pe), .type = PFM_PMU_TYPE_CORE, .supported_plm = AMD64_FAM10H_PLM, .num_cntrs = 6, .max_encoding = 1, .pe = amd64_fam15h_pe, .atdesc = amd64_mods, .flags = PFMLIB_PMU_FL_RAW_UMASK, .cpu_family = PFM_PMU_AMD64_FAM15H_INTERLAGOS, .pmu_detect = pfm_amd64_family_detect, .get_event_encoding[PFM_OS_NONE] = pfm_amd64_get_encoding, PFMLIB_ENCODE_PERF(pfm_amd64_get_perf_encoding), .get_event_first = pfm_amd64_get_event_first, .get_event_next = pfm_amd64_get_event_next, .event_is_valid = pfm_amd64_event_is_valid, .validate_table = pfm_amd64_validate_table, .get_event_info = pfm_amd64_get_event_info, .get_event_attr_info = pfm_amd64_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_amd64_perf_validate_pattrs), .get_event_nattrs = pfm_amd64_get_event_nattrs, }; pfmlib_pmu_t amd64_fam15h_nb_support={ .desc = "AMD64 Fam15h NorthBridge", .name = "amd64_fam15h_nb", .pmu = PFM_PMU_AMD64_FAM15H_NB, .perf_name = "amd_nb", .pmu_rev = 0, .pme_count = LIBPFM_ARRAY_SIZE(amd64_fam15h_nb_pe), .type = PFM_PMU_TYPE_UNCORE, .supported_plm = 0, /* no plm support */ .num_cntrs = 4, .max_encoding = 1, .pe = amd64_fam15h_nb_pe, .atdesc = amd64_mods, .flags = PFMLIB_PMU_FL_RAW_UMASK, .cpu_family = PFM_PMU_AMD64_FAM15H_INTERLAGOS, .pmu_detect = pfm_amd64_family_detect, .get_event_encoding[PFM_OS_NONE] = pfm_amd64_get_encoding, PFMLIB_ENCODE_PERF(pfm_amd64_get_perf_encoding), .get_event_first = pfm_amd64_get_event_first, .get_event_next = pfm_amd64_get_event_next, .event_is_valid = pfm_amd64_event_is_valid, .validate_table = pfm_amd64_validate_table, .get_event_info = pfm_amd64_get_event_info, .get_event_attr_info = pfm_amd64_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_amd64_nb_perf_validate_pattrs), .get_event_nattrs = pfm_amd64_get_event_nattrs, }; libpfm-4.9.0/lib/pfmlib_intel_netburst.c0000664000175000017500000003151313223402656020125 0ustar eranianeranian/* * Copyright (c) 2005-2006 Hewlett-Packard Development Company, L.P. * Copyright (c) 2006 IBM Corp. * Contributed by Kevin Corry * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * * pfmlib_intel_netburst.c * * Support for the Pentium4/Xeon/EM64T processor family (family=15). */ /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_intel_netburst_priv.h" #include "pfmlib_intel_x86_priv.h" #include "events/intel_netburst_events.h" const pfmlib_attr_desc_t netburst_mods[]={ PFM_ATTR_B("u", "monitor at priv level 1, 2, 3"), /* monitor priv level 1, 2, 3 */ PFM_ATTR_B("k", "monitor at priv level 0"), /* monitor priv level 0 */ PFM_ATTR_B("cmpl", "complement"), /* set: <=, clear: > */ PFM_ATTR_B("e", "edge"), /* edge */ PFM_ATTR_I("thr", "event threshold in range [0-15]"), /* threshold */ }; #define NETBURST_MODS_COUNT (sizeof(netburst_mods)/sizeof(pfmlib_attr_desc_t)) extern pfmlib_pmu_t netburst_support; static inline int netburst_get_numasks(int pidx) { int i = 0; /* * name = NULL is end-marker */ while (netburst_events[pidx].event_masks[i].name) i++; return i; } static void netburst_display_reg(pfmlib_event_desc_t *e) { netburst_escr_value_t escr; netburst_cccr_value_t cccr; escr.val = e->codes[0]; cccr.val = e->codes[1]; __pfm_vbprintf("[0x%"PRIx64" 0x%"PRIx64" 0x%"PRIx64" usr=%d os=%d tag_ena=%d tag_val=%d " "evmask=0x%x evsel=0x%x escr_sel=0x%x comp=%d cmpl=%d thr=%d e=%d", escr, cccr, e->codes[2], /* perf_event code */ escr.bits.t0_usr, /* t1 is identical */ escr.bits.t0_os, /* t1 is identical */ escr.bits.tag_enable, escr.bits.tag_value, escr.bits.event_mask, escr.bits.event_select, cccr.bits.escr_select, cccr.bits.compare, cccr.bits.complement, cccr.bits.threshold, cccr.bits.edge); __pfm_vbprintf("] %s\n", e->fstr); } static int netburst_add_defaults(pfmlib_event_desc_t *e, unsigned int *evmask) { int i, n; n = netburst_get_numasks(e->event); for (i = 0; i < n; i++) { if (netburst_events[e->event].event_masks[i].flags & NETBURST_FL_DFL) goto found; } return PFM_ERR_ATTR; found: *evmask = 1 << netburst_events[e->event].event_masks[i].bit; n = e->nattrs; e->attrs[n].id = i; e->attrs[n].ival = i; e->nattrs = n+1; return PFM_SUCCESS; } int pfm_netburst_get_encoding(void *this, pfmlib_event_desc_t *e) { pfmlib_event_attr_info_t *a; netburst_escr_value_t escr; netburst_cccr_value_t cccr; unsigned int evmask = 0; unsigned int plmmsk = 0; int umask_done = 0; const char *n; int k, id, bit, ret; int tag_enable = 0, tag_value = 0; e->fstr[0] = '\0'; escr.val = 0; cccr.val = 0; for(k=0; k < e->nattrs; k++) { a = attr(e, k); if (a->ctrl != PFM_ATTR_CTRL_PMU) continue; if (a->type == PFM_ATTR_UMASK) { bit = netburst_events[e->event].event_masks[a->idx].bit; n = netburst_events[e->event].event_masks[a->idx].name; /* * umask combination seems possible, although it does * not always make sense, e.g., BOGUS vs. NBOGUS */ if (bit < EVENT_MASK_BITS && n) { evmask |= (1 << bit); } else if (bit >= EVENT_MASK_BITS && n) { tag_value |= (1 << (bit - EVENT_MASK_BITS)); tag_enable = 1; } umask_done = 1; } else if (a->type == PFM_ATTR_RAW_UMASK) { /* should not happen */ return PFM_ERR_ATTR; } else { uint64_t ival = e->attrs[k].ival; switch (a->idx) { case NETBURST_ATTR_U: escr.bits.t1_usr = !!ival; escr.bits.t0_usr = !!ival; plmmsk |= _NETBURST_ATTR_U; break; case NETBURST_ATTR_K: escr.bits.t1_os = !!ival; escr.bits.t0_os = !!ival; plmmsk |= _NETBURST_ATTR_K; break; case NETBURST_ATTR_E: if (ival) { cccr.bits.compare = 1; cccr.bits.edge = 1; } break; case NETBURST_ATTR_C: if (ival) { cccr.bits.compare = 1; cccr.bits.complement = 1; } break; case NETBURST_ATTR_T: if (ival > 15) return PFM_ERR_ATTR_VAL; if (ival) { cccr.bits.compare = 1; cccr.bits.threshold = ival; } break; default: return PFM_ERR_ATTR; } } } /* * handle case where no priv level mask was passed. * then we use the dfl_plm */ if (!(plmmsk & (_NETBURST_ATTR_K|_NETBURST_ATTR_U))) { if (e->dfl_plm & PFM_PLM0) { escr.bits.t1_os = 1; escr.bits.t0_os = 1; } if (e->dfl_plm & PFM_PLM3) { escr.bits.t1_usr = 1; escr.bits.t0_usr = 1; } } if (!umask_done) { ret = netburst_add_defaults(e, &evmask); if (ret != PFM_SUCCESS) return ret; } escr.bits.tag_enable = tag_enable; escr.bits.tag_value = tag_value; escr.bits.event_mask = evmask; escr.bits.event_select = netburst_events[e->event].event_select; cccr.bits.enable = 1; cccr.bits.escr_select = netburst_events[e->event].escr_select; cccr.bits.active_thread = 3; if (e->event == PME_REPLAY_EVENT) escr.bits.event_mask &= P4_REPLAY_REAL_MASK; /* remove virtual mask bits */ /* * reorder all the attributes such that the fstr appears always * the same regardless of how the attributes were submitted. */ evt_strcat(e->fstr, "%s", netburst_events[e->event].name); pfmlib_sort_attr(e); for(k=0; k < e->nattrs; k++) { a = attr(e, k); if (a->ctrl != PFM_ATTR_CTRL_PMU) continue; if (a->type == PFM_ATTR_UMASK) { id = e->attrs[k].id; evt_strcat(e->fstr, ":%s", netburst_events[e->event].event_masks[id].name); } } evt_strcat(e->fstr, ":%s=%lu", netburst_mods[NETBURST_ATTR_K].name, escr.bits.t0_os); evt_strcat(e->fstr, ":%s=%lu", netburst_mods[NETBURST_ATTR_U].name, escr.bits.t0_usr); evt_strcat(e->fstr, ":%s=%lu", netburst_mods[NETBURST_ATTR_E].name, cccr.bits.edge); evt_strcat(e->fstr, ":%s=%lu", netburst_mods[NETBURST_ATTR_C].name, cccr.bits.complement); evt_strcat(e->fstr, ":%s=%lu", netburst_mods[NETBURST_ATTR_T].name, cccr.bits.threshold); e->count = 2; e->codes[0] = escr.val; e->codes[1] = cccr.val; netburst_display_reg(e); return PFM_SUCCESS; } static int pfm_netburst_detect(void *this) { int ret; int model; ret = pfm_intel_x86_detect(); if (ret != PFM_SUCCESS) return ret; if (pfm_intel_x86_cfg.family != 15) return PFM_ERR_NOTSUPP; model = pfm_intel_x86_cfg.model; if (model == 3 || model == 4 || model == 6) return PFM_ERR_NOTSUPP; return PFM_SUCCESS; } static int pfm_netburst_detect_prescott(void *this) { int ret; int model; ret = pfm_intel_x86_detect(); if (ret != PFM_SUCCESS) return ret; if (pfm_intel_x86_cfg.family != 15) return PFM_ERR_NOTSUPP; /* * prescott has one more event (instr_completed) */ model = pfm_intel_x86_cfg.model; if (model != 3 && model != 4 && model != 6) return PFM_ERR_NOTSUPP; return PFM_SUCCESS; } static int pfm_netburst_get_event_first(void *this) { pfmlib_pmu_t *p = this; return p->pme_count ? 0 : -1; } static int pfm_netburst_get_event_next(void *this, int idx) { pfmlib_pmu_t *p = this; if (idx >= (p->pme_count-1)) return -1; return idx+1; } static int pfm_netburst_event_is_valid(void *this, int pidx) { pfmlib_pmu_t *p = this; return pidx >= 0 && pidx < p->pme_count; } static int pfm_netburst_get_event_attr_info(void *this, int pidx, int attr_idx, pfmlib_event_attr_info_t *info) { const netburst_entry_t *pe = this_pe(this); int numasks, idx; numasks = netburst_get_numasks(pidx); if (attr_idx < numasks) { //idx = pfm_intel_x86_attr2umask(this, pidx, attr_idx); idx = attr_idx; info->name = pe[pidx].event_masks[idx].name; info->desc = pe[pidx].event_masks[idx].desc; info->equiv= NULL; info->code = pe[pidx].event_masks[idx].bit; info->type = PFM_ATTR_UMASK; info->is_dfl = !!(pe[pidx].event_masks[idx].flags & NETBURST_FL_DFL); } else { idx = attr_idx - numasks; info->name = netburst_mods[idx].name; info->desc = netburst_mods[idx].desc; info->equiv= NULL; info->code = idx; info->type = netburst_mods[idx].type; info->is_dfl = 0; } info->ctrl = PFM_ATTR_CTRL_PMU; info->idx = idx; /* namespace specific index */ info->dfl_val64 = 0; return PFM_SUCCESS; } static int pfm_netburst_get_event_info(void *this, int idx, pfm_event_info_t *info) { const netburst_entry_t *pe = this_pe(this); pfmlib_pmu_t *pmu = this; /* * pmu and idx filled out by caller */ info->name = pe[idx].name; info->desc = pe[idx].desc; info->code = pe[idx].event_select | (pe[idx].escr_select << 8); info->equiv = NULL; info->idx = idx; /* private index */ info->pmu = pmu->pmu; info->nattrs = netburst_get_numasks(idx); info->nattrs += NETBURST_MODS_COUNT; return PFM_SUCCESS; } static int pfm_netburst_validate_table(void *this, FILE *fp) { pfmlib_pmu_t *pmu = this; const netburst_entry_t *pe = netburst_events; const char *name = pmu->name; int i, j, noname, ndfl; int error = 0; for(i=0; i < pmu->pme_count; i++) { if (!pe[i].name) { fprintf(fp, "pmu: %s event%d: :: no name (prev event was %s)\n", pmu->name, i, i > 1 ? pe[i-1].name : "??"); error++; } if (!pe[i].desc) { fprintf(fp, "pmu: %s event%d: %s :: no description\n", name, i, pe[i].name); error++; } noname = ndfl = 0; /* name = NULL is end-marker, veryfy there is at least one */ for(j= 0; j < EVENT_MASK_BITS; j++) { if (!pe[i].event_masks[j].name) noname++; if (pe[i].event_masks[j].name) { if (!pe[i].event_masks[j].desc) { fprintf(fp, "pmu: %s event%d:%s umask%d: %s :: no description\n", name, i, pe[i].name, j, pe[i].event_masks[j].name); error++; } if (pe[i].event_masks[j].bit >= (EVENT_MASK_BITS+4)) { fprintf(fp, "pmu: %s event%d:%s umask%d: %s :: invalid bit field\n", name, i, pe[i].name, j, pe[i].event_masks[j].name); error++; } if (pe[i].event_masks[j].flags & NETBURST_FL_DFL) ndfl++; } } if (ndfl > 1) { fprintf(fp, "pmu: %s event%d:%s :: more than one default umask\n", name, i, pe[i].name); error++; } if (!noname) { fprintf(fp, "pmu: %s event%d:%s :: no event mask end-marker\n", name, i, pe[i].name); error++; } } return error ? PFM_ERR_INVAL : PFM_SUCCESS; } static unsigned int pfm_netburst_get_event_nattrs(void *this, int pidx) { unsigned int nattrs; nattrs = netburst_get_numasks(pidx); nattrs += NETBURST_MODS_COUNT; return nattrs; } pfmlib_pmu_t netburst_support = { .desc = "Pentium4", .name = "netburst", .pmu = PFM_PMU_INTEL_NETBURST, .pme_count = LIBPFM_ARRAY_SIZE(netburst_events) - 1, .type = PFM_PMU_TYPE_CORE, .supported_plm = INTEL_X86_PLM, .atdesc = netburst_mods, .pe = netburst_events, .max_encoding = 3, .num_cntrs = 18, .pmu_detect = pfm_netburst_detect, .get_event_encoding[PFM_OS_NONE] = pfm_netburst_get_encoding, PFMLIB_ENCODE_PERF(pfm_netburst_get_perf_encoding), .get_event_first = pfm_netburst_get_event_first, .get_event_next = pfm_netburst_get_event_next, .event_is_valid = pfm_netburst_event_is_valid, .validate_table = pfm_netburst_validate_table, .get_event_info = pfm_netburst_get_event_info, .get_event_attr_info = pfm_netburst_get_event_attr_info, .get_event_nattrs = pfm_netburst_get_event_nattrs, PFMLIB_VALID_PERF_PATTRS(pfm_netburst_perf_validate_pattrs), }; pfmlib_pmu_t netburst_p_support = { .desc = "Pentium4 (Prescott)", .name = "netburst_p", .pmu = PFM_PMU_INTEL_NETBURST_P, .pme_count = LIBPFM_ARRAY_SIZE(netburst_events), .type = PFM_PMU_TYPE_CORE, .supported_plm = INTEL_X86_PLM, .atdesc = netburst_mods, .pe = netburst_events, .max_encoding = 3, .num_cntrs = 18, .pmu_detect = pfm_netburst_detect_prescott, .get_event_encoding[PFM_OS_NONE] = pfm_netburst_get_encoding, PFMLIB_ENCODE_PERF(pfm_netburst_get_perf_encoding), .get_event_first = pfm_netburst_get_event_first, .get_event_next = pfm_netburst_get_event_next, .event_is_valid = pfm_netburst_event_is_valid, .validate_table = pfm_netburst_validate_table, .get_event_info = pfm_netburst_get_event_info, .get_event_attr_info = pfm_netburst_get_event_attr_info, .get_event_nattrs = pfm_netburst_get_event_nattrs, PFMLIB_VALID_PERF_PATTRS(pfm_netburst_perf_validate_pattrs), }; libpfm-4.9.0/lib/pfmlib_powerpc_perf_event.c0000664000175000017500000000723213223402656020761 0ustar eranianeranian/* * pfmlib_powerpc_perf_event.c : perf_event IBM Power/Torrent functions * * Copyright (c) 2011 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include /* private headers */ #include "pfmlib_priv.h" /* library private */ #include "pfmlib_power_priv.h" /* architecture private */ #include "pfmlib_perf_event_priv.h" int pfm_gen_powerpc_get_perf_encoding(void *this, pfmlib_event_desc_t *e) { pfmlib_pmu_t *pmu = this; struct perf_event_attr *attr = e->os_data; int ret; if (!pmu->get_event_encoding[PFM_OS_NONE]) return PFM_ERR_NOTSUPP; /* * encoding routine changes based on PMU model */ ret = pmu->get_event_encoding[PFM_OS_NONE](this, e); if (ret != PFM_SUCCESS) return ret; attr->type = PERF_TYPE_RAW; attr->config = e->codes[0]; return PFM_SUCCESS; } static int find_pmu_type_by_name(const char *name) { char filename[PATH_MAX]; FILE *fp; int ret, type; if (!name) return PFM_ERR_NOTSUPP; sprintf(filename, "/sys/bus/event_source/devices/%s/type", name); fp = fopen(filename, "r"); if (!fp) return PFM_ERR_NOTSUPP; ret = fscanf(fp, "%d", &type); if (ret != 1) type = PFM_ERR_NOTSUPP; fclose(fp); return type; } int pfm_gen_powerpc_get_nest_perf_encoding(void *this, pfmlib_event_desc_t *e) { pfmlib_pmu_t *pmu = this; struct perf_event_attr *attr = e->os_data; int ret; if (!pmu->get_event_encoding[PFM_OS_NONE]) return PFM_ERR_NOTSUPP; /* * encoding routine changes based on PMU model */ ret = pmu->get_event_encoding[PFM_OS_NONE](this, e); if (ret != PFM_SUCCESS) return ret; ret = find_pmu_type_by_name(pmu->perf_name); if (ret < 0) return ret; attr->type = ret; attr->config = e->codes[0]; return PFM_SUCCESS; } void pfm_gen_powerpc_perf_validate_pattrs(void *this, pfmlib_event_desc_t *e) { int i, compact; for (i = 0; i < e->npattrs; i++) { compact = 0; /* umasks never conflict */ if (e->pattrs[i].type == PFM_ATTR_UMASK) continue; /* * remove PMU-provided attributes which are either * not accessible under perf_events or fully controlled * by perf_events, e.g., priv levels filters */ if (e->pattrs[i].ctrl == PFM_ATTR_CTRL_PMU) { } /* * remove perf_event generic attributes not supported * by PPC */ if (e->pattrs[i].ctrl == PFM_ATTR_CTRL_PERF_EVENT) { /* no precise sampling */ if (e->pattrs[i].idx == PERF_ATTR_PR) compact = 1; } if (compact) { pfmlib_compact_pattrs(e, i); i--; } } } libpfm-4.9.0/lib/pfmlib_intel_ivbep_unc_cbo.c0000664000175000017500000000772713223402656021066 0ustar eranianeranian/* * pfmlib_intel_ivbep_unc_cbo.c : Intel IvyBridge-EP C-Box uncore PMU * * Copyright (c) 2014 Google Inc. All rights reserved * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_intel_x86_priv.h" #include "pfmlib_intel_snbep_unc_priv.h" #include "events/intel_ivbep_unc_cbo_events.h" static void display_cbo(void *this, pfmlib_event_desc_t *e, void *val) { const intel_x86_entry_t *pe = this_pe(this); pfm_snbep_unc_reg_t *reg = val; pfm_snbep_unc_reg_t f; __pfm_vbprintf("[UNC_CBO=0x%"PRIx64" event=0x%x umask=0x%x en=%d " "inv=%d edge=%d thres=%d tid_en=%d] %s\n", reg->val, reg->cbo.unc_event, reg->cbo.unc_umask, reg->cbo.unc_en, reg->cbo.unc_inv, reg->cbo.unc_edge, reg->cbo.unc_thres, reg->cbo.unc_tid, pe[e->event].name); if (e->count == 1) return; f.val = e->codes[1]; __pfm_vbprintf("[UNC_CBOX_FILTER0=0x%"PRIx64" tid=%d core=0x%x" " state=0x%x]\n", f.val, f.ivbep_cbo_filt0.tid, f.ivbep_cbo_filt0.cid, f.ivbep_cbo_filt0.state); if (e->count == 2) return; f.val = e->codes[2]; __pfm_vbprintf("[UNC_CBOX_FILTER1=0x%"PRIx64" nid=%d opc=0x%x" " nc=0x%x isoc=0x%x]\n", f.val, f.ivbep_cbo_filt1.nid, f.ivbep_cbo_filt1.opc, f.ivbep_cbo_filt1.nc, f.ivbep_cbo_filt1.isoc); } #define DEFINE_C_BOX(n) \ pfmlib_pmu_t intel_ivbep_unc_cb##n##_support = {\ .desc = "Intel Ivy Bridge-EP C-Box "#n" uncore",\ .name = "ivbep_unc_cbo"#n,\ .perf_name = "uncore_cbox_"#n,\ .pmu = PFM_PMU_INTEL_IVBEP_UNC_CB##n,\ .pme_count = LIBPFM_ARRAY_SIZE(intel_ivbep_unc_c_pe),\ .type = PFM_PMU_TYPE_UNCORE,\ .num_cntrs = 4,\ .num_fixed_cntrs = 0,\ .max_encoding = 2,\ .pe = intel_ivbep_unc_c_pe,\ .atdesc = snbep_unc_mods,\ .flags = PFMLIB_PMU_FL_RAW_UMASK|INTEL_PMU_FL_UNC_CBO,\ .pmu_detect = pfm_intel_ivbep_unc_detect,\ .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding,\ PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding),\ PFMLIB_OS_DETECT(pfm_intel_x86_perf_detect), \ .get_event_first = pfm_intel_x86_get_event_first,\ .get_event_next = pfm_intel_x86_get_event_next,\ .event_is_valid = pfm_intel_x86_event_is_valid,\ .validate_table = pfm_intel_x86_validate_table,\ .get_event_info = pfm_intel_x86_get_event_info,\ .get_event_attr_info = pfm_intel_x86_get_event_attr_info,\ PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs),\ .get_event_nattrs = pfm_intel_x86_get_event_nattrs,\ .can_auto_encode = pfm_intel_x86_can_auto_encode, \ .display_reg = display_cbo,\ } DEFINE_C_BOX(0); DEFINE_C_BOX(1); DEFINE_C_BOX(2); DEFINE_C_BOX(3); DEFINE_C_BOX(4); DEFINE_C_BOX(5); DEFINE_C_BOX(6); DEFINE_C_BOX(7); DEFINE_C_BOX(8); DEFINE_C_BOX(9); DEFINE_C_BOX(10); DEFINE_C_BOX(11); DEFINE_C_BOX(12); DEFINE_C_BOX(13); DEFINE_C_BOX(14); libpfm-4.9.0/lib/pfmlib_intel_hswep_unc_pcu.c0000664000175000017500000000673013223402656021124 0ustar eranianeranian/* * pfmlib_intel_hswep_unc_pcu.c : Intel Haswell-EP Power Control Unit (PCU) uncore PMU * * Copyright (c) 2014 Google Inc. All rights reserved * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_intel_x86_priv.h" #include "pfmlib_intel_snbep_unc_priv.h" #include "events/intel_hswep_unc_pcu_events.h" static void display_pcu(void *this, pfmlib_event_desc_t *e, void *val) { const intel_x86_entry_t *pe = this_pe(this); pfm_snbep_unc_reg_t *reg = val; pfm_snbep_unc_reg_t f; __pfm_vbprintf("[UNC_PCU=0x%"PRIx64" event=0x%x sel_ext=%d occ_sel=0x%x en=%d " "edge=%d thres=%d occ_inv=%d occ_edge=%d] %s\n", reg->val, reg->ivbep_pcu.unc_event, reg->ivbep_pcu.unc_sel_ext, reg->ivbep_pcu.unc_occ, reg->ivbep_pcu.unc_en, reg->ivbep_pcu.unc_edge, reg->ivbep_pcu.unc_thres, reg->ivbep_pcu.unc_occ_inv, reg->ivbep_pcu.unc_occ_edge, pe[e->event].name); if (e->count == 1) return; f.val = e->codes[1]; __pfm_vbprintf("[UNC_PCU_FILTER=0x%"PRIx64" band0=%u band1=%u band2=%u band3=%u]\n", f.val, f.pcu_filt.filt0, f.pcu_filt.filt1, f.pcu_filt.filt2, f.pcu_filt.filt3); } pfmlib_pmu_t intel_hswep_unc_pcu_support = { .desc = "Intel Haswell-EP PCU uncore", .name = "hswep_unc_pcu", .perf_name = "uncore_pcu", .pmu = PFM_PMU_INTEL_HSWEP_UNC_PCU, .pme_count = LIBPFM_ARRAY_SIZE(intel_hswep_unc_p_pe), .type = PFM_PMU_TYPE_UNCORE, .num_cntrs = 4, .num_fixed_cntrs = 0, .max_encoding = 2, .pe = intel_hswep_unc_p_pe, .atdesc = snbep_unc_mods, .flags = PFMLIB_PMU_FL_RAW_UMASK, .pmu_detect = pfm_intel_hswep_unc_detect, .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding, PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding), PFMLIB_OS_DETECT(pfm_intel_x86_perf_detect), .get_event_first = pfm_intel_x86_get_event_first, .get_event_next = pfm_intel_x86_get_event_next, .event_is_valid = pfm_intel_x86_event_is_valid, .validate_table = pfm_intel_x86_validate_table, .get_event_info = pfm_intel_x86_get_event_info, .get_event_attr_info = pfm_intel_x86_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs), .get_event_nattrs = pfm_intel_x86_get_event_nattrs, .can_auto_encode = pfm_intel_snbep_unc_can_auto_encode, .display_reg = display_pcu, }; libpfm-4.9.0/lib/pfmlib_intel_snbep_unc_ha.c0000664000175000017500000000646413223402656020712 0ustar eranianeranian/* * pfmlib_intel_snb_unc_ha.c : Intel SandyBridge-EP Home Agent (HA) uncore PMU * * Copyright (c) 2012 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_intel_x86_priv.h" #include "pfmlib_intel_snbep_unc_priv.h" #include "events/intel_snbep_unc_ha_events.h" static void display_ha(void *this, pfmlib_event_desc_t *e, void *val) { const intel_x86_entry_t *pe = this_pe(this); pfm_snbep_unc_reg_t *reg = val; pfm_snbep_unc_reg_t f; __pfm_vbprintf("[UNC_HA=0x%"PRIx64" event=0x%x umask=0x%x en=%d " "inv=%d edge=%d thres=%d] %s\n", reg->val, reg->com.unc_event, reg->com.unc_umask, reg->com.unc_en, reg->com.unc_inv, reg->com.unc_edge, reg->com.unc_thres, pe[e->event].name); if (e->count == 1) return; f.val = e->codes[1]; __pfm_vbprintf("[UNC_HA_ADDR=0x%"PRIx64" lo_addr=0x%x hi_addr=0x%x]\n", f.val, f.ha_addr.lo_addr, f.ha_addr.hi_addr); f.val = e->codes[2]; __pfm_vbprintf("[UNC_HA_OPC=0x%"PRIx64" opc=0x%x]\n", f.val, f.ha_opc.opc); } pfmlib_pmu_t intel_snbep_unc_ha_support = { .desc = "Intel Sandy Bridge-EP HA uncore", .name = "snbep_unc_ha", .perf_name = "uncore_ha", .pmu = PFM_PMU_INTEL_SNBEP_UNC_HA, .pme_count = LIBPFM_ARRAY_SIZE(intel_snbep_unc_h_pe), .type = PFM_PMU_TYPE_UNCORE, .num_cntrs = 4, .num_fixed_cntrs = 0, .max_encoding = 3, /* address matchers */ .pe = intel_snbep_unc_h_pe, .atdesc = snbep_unc_mods, .flags = PFMLIB_PMU_FL_RAW_UMASK | PFMLIB_PMU_FL_NO_SMPL, .pmu_detect = pfm_intel_snbep_unc_detect, .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding, PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding), .get_event_first = pfm_intel_x86_get_event_first, .get_event_next = pfm_intel_x86_get_event_next, .event_is_valid = pfm_intel_x86_event_is_valid, .validate_table = pfm_intel_x86_validate_table, .get_event_info = pfm_intel_x86_get_event_info, .get_event_attr_info = pfm_intel_x86_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs), .get_event_nattrs = pfm_intel_x86_get_event_nattrs, .display_reg = display_ha, }; libpfm-4.9.0/lib/pfmlib_amd64_fam14h.c0000664000175000017500000000470113223402656017136 0ustar eranianeranian/* * pfmlib_amd64_fam14h.c : AMD64 Family 14h * * Copyright (c) 2011 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_amd64_priv.h" #include "events/amd64_events_fam14h.h" #define DEFINE_FAM14H_REV(d, n, r, pmuid) \ pfmlib_pmu_t amd64_fam14h_##n##_support={ \ .desc = "AMD64 Fam14h "#d, \ .name = "amd64_fam14h_"#n, \ .pmu = pmuid, \ .pmu_rev = r, \ .pme_count = LIBPFM_ARRAY_SIZE(amd64_fam14h_pe),\ .type = PFM_PMU_TYPE_CORE, \ .supported_plm = AMD64_FAM10H_PLM, \ .num_cntrs = 4, \ .max_encoding = 1, \ .pe = amd64_fam14h_pe, \ .atdesc = amd64_mods, \ .flags = PFMLIB_PMU_FL_RAW_UMASK, \ \ .cpu_family = pmuid, \ .pmu_detect = pfm_amd64_family_detect, \ .get_event_encoding[PFM_OS_NONE] = pfm_amd64_get_encoding,\ PFMLIB_ENCODE_PERF(pfm_amd64_get_perf_encoding), \ .get_event_first = pfm_amd64_get_event_first, \ .get_event_next = pfm_amd64_get_event_next, \ .event_is_valid = pfm_amd64_event_is_valid, \ .validate_table = pfm_amd64_validate_table, \ .get_event_info = pfm_amd64_get_event_info, \ .get_event_attr_info = pfm_amd64_get_event_attr_info,\ PFMLIB_VALID_PERF_PATTRS(pfm_amd64_perf_validate_pattrs),\ .get_event_nattrs = pfm_amd64_get_event_nattrs, \ } DEFINE_FAM14H_REV(Bobcat, bobcat, AMD64_FAM14H_REV_B, PFM_PMU_AMD64_FAM14H_BOBCAT); libpfm-4.9.0/lib/pfmlib_sicortex.c0000664000175000017500000005051713223402656016731 0ustar eranianeranian/* * pfmlib_sicortex.c : support for the generic MIPS64 PMU family * * Contributed by Philip Mucci based on code from * Copyright (c) 2005-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include #include #include #include #include /* public headers */ #include #include /* private headers */ #include "pfmlib_priv.h" /* library private */ #include "pfmlib_sicortex_priv.h" /* architecture private */ #include "sicortex/ice9a/ice9a_all_spec_pme.h" #include "sicortex/ice9b/ice9b_all_spec_pme.h" #include "sicortex/ice9/ice9_scb_spec_sw.h" /* let's define some handy shortcuts! */ #define sel_event_mask perfsel.sel_event_mask #define sel_exl perfsel.sel_exl #define sel_os perfsel.sel_os #define sel_usr perfsel.sel_usr #define sel_sup perfsel.sel_sup #define sel_int perfsel.sel_int static pme_sicortex_entry_t *sicortex_pe = NULL; // CHANGE FOR ICET #define core_counters 2 #define MAX_ICE9_PMCS 2+4+256 #define MAX_ICE9_PMDS 2+4+256 static int compute_ice9_counters(int type) { int i; int bound = 0; pme_gen_mips64_entry_t *gen_mips64_pe = NULL; sicortex_support.pmd_count = 0; sicortex_support.pmc_count = 0; for (i=0;i 2) { /* Account for 4 sampling PMD registers */ sicortex_support.num_cnt = sicortex_support.pmd_count - 4; sicortex_support.pme_count = bound; } else { sicortex_support.pme_count = 0; /* Count up CPU only events */ for (i=0;i> (cntr*8)) & 0xff; pc[j].reg_addr = cntr*2; pc[j].reg_value = reg.val; pc[j].reg_num = cntr; __pfm_vbprintf("[CP0_25_%u(pmc%u)=0x%"PRIx64" event_mask=0x%x usr=%d os=%d sup=%d exl=%d int=1] %s\n", pc[j].reg_addr, pc[j].reg_num, pc[j].reg_value, reg.sel_event_mask, reg.sel_usr, reg.sel_os, reg.sel_sup, reg.sel_exl, sicortex_pe[e[j].event].pme_name); pd[j].reg_num = cntr; pd[j].reg_addr = cntr*2 + 1; __pfm_vbprintf("[CP0_25_%u(pmd%u)]\n", pc[j].reg_addr, pc[j].reg_num); } /* SCB event */ else { pmc_sicortex_scb_reg_t scbreg; int k; scbreg.val = 0; scbreg.sicortex_ScbPerfBucket_reg.event = sicortex_pe[e[j].event].pme_code >> 16; for (k=0;kflags & PFMLIB_SICORTEX_INPUT_SCB_INTERVAL)) { two.sicortex_ScbPerfCtl_reg.Interval = mod_in->pfp_sicortex_scb_global.Interval; } else { two.sicortex_ScbPerfCtl_reg.Interval = 6; /* 2048 cycles */ } if (mod_in && (mod_in->flags & PFMLIB_SICORTEX_INPUT_SCB_NOINC)) { two.sicortex_ScbPerfCtl_reg.NoInc = mod_in->pfp_sicortex_scb_global.NoInc; } else { two.sicortex_ScbPerfCtl_reg.NoInc = 0; } two.sicortex_ScbPerfCtl_reg.IntBit = 31; /* Interrupt on last bit */ two.sicortex_ScbPerfCtl_reg.MagicEvent = 0; two.sicortex_ScbPerfCtl_reg.AddrAssert = 1; __pfm_vbprintf("[Scb%s(pmc%u)=0x%"PRIx64" Interval=0x%x IntBit=0x%x NoInc=%d AddrAssert=%d MagicEvent=0x%x]\n","PerfCtl", pc[num].reg_num, two.val, two.sicortex_ScbPerfCtl_reg.Interval, two.sicortex_ScbPerfCtl_reg.IntBit, two.sicortex_ScbPerfCtl_reg.NoInc, two.sicortex_ScbPerfCtl_reg.AddrAssert, two.sicortex_ScbPerfCtl_reg.MagicEvent); pc[num].reg_value = two.val; /*ScbPerfHist */ pc[++num].reg_num = 3; pc[num].reg_addr = 3; three.val = 0; if (mod_in && (mod_in->flags & PFMLIB_SICORTEX_INPUT_SCB_HISTGTE)) three.sicortex_ScbPerfHist_reg.HistGte = mod_in->pfp_sicortex_scb_global.HistGte; else three.sicortex_ScbPerfHist_reg.HistGte = 1; __pfm_vbprintf("[Scb%s(pmc%u)=0x%"PRIx64" HistGte=0x%x]\n","PerfHist", pc[num].reg_num, three.val, three.sicortex_ScbPerfHist_reg.HistGte); pc[num].reg_value = three.val; /*ScbPerfBuckNum */ pc[++num].reg_num = 4; pc[num].reg_addr = 4; four.val = 0; if (mod_in && (mod_in->flags & PFMLIB_SICORTEX_INPUT_SCB_BUCKET)) four.sicortex_ScbPerfBuckNum_reg.Bucket = mod_in->pfp_sicortex_scb_global.Bucket; else four.sicortex_ScbPerfBuckNum_reg.Bucket = 0; __pfm_vbprintf("[Scb%s(pmc%u)=0x%"PRIx64" Bucket=0x%x]\n","PerfBuckNum", pc[num].reg_num, four.val, four.sicortex_ScbPerfBuckNum_reg.Bucket); pc[num].reg_value = four.val; /*ScbPerfEna */ pc[++num].reg_num = 5; pc[num].reg_addr = 5; five.val = 0; five.sicortex_ScbPerfEna_reg.ena = 1; __pfm_vbprintf("[Scb%s(pmc%u)=0x%"PRIx64" ena=%d]\n","PerfEna", pc[num].reg_num, five.val, five.sicortex_ScbPerfEna_reg.ena); pc[num].reg_value = five.val; ++num; return(num); } /* * Automatically dispatch events to corresponding counters following constraints. * Upon return the pfarg_regt structure is ready to be submitted to kernel */ static int pfm_sicortex_dispatch_counters(pfmlib_input_param_t *inp, pfmlib_sicortex_input_param_t *mod_in, pfmlib_output_param_t *outp) { /* pfmlib_sicortex_input_param_t *param = mod_in; */ pfmlib_event_t *e = inp->pfp_events; pfmlib_reg_t *pc, *pd; unsigned int i, j, cnt = inp->pfp_event_count; unsigned int used = 0; extern pfm_pmu_support_t sicortex_support; unsigned int cntr, avail; pc = outp->pfp_pmcs; pd = outp->pfp_pmds; /* Degree N rank based allocation */ if (cnt > sicortex_support.pmc_count) return PFMLIB_ERR_TOOMANY; if (PFMLIB_DEBUG()) { for (j=0; j < cnt; j++) { DPRINT("ev[%d]=%s, counters=0x%x\n", j, sicortex_pe[e[j].event].pme_name,sicortex_pe[e[j].event].pme_counters); } } /* Do rank based allocation, counters that live on 1 reg before counters that live on 2 regs etc. */ /* CPU counters first */ for (i=1;i<=core_counters;i++) { for (j=0; j < cnt;j++) { /* CPU counters first */ if ((sicortex_pe[e[j].event].pme_counters & ((1<pfp_dfl_plm,pc,pd,cntr,j,mod_in); used |= (1 << cntr); DPRINT("Rank %d: Used counters 0x%x\n",i, used); } } } /* SCB counters can live anywhere */ used = 0; for (j=0; j < cnt;j++) { unsigned int cntr; /* CPU counters first */ if (sicortex_pe[e[j].event].pme_counters & (1<pfp_dfl_plm,pc,pd,cntr,j,mod_in); used++; DPRINT("SCB(%d): Used counters %d\n",j,used); } } if (used) { outp->pfp_pmc_count = stuff_sicortex_scb_control_regs(pc,pd,cnt,mod_in); outp->pfp_pmd_count = cnt; return PFMLIB_SUCCESS; } /* number of evtsel registers programmed */ outp->pfp_pmc_count = cnt; outp->pfp_pmd_count = cnt; return PFMLIB_SUCCESS; } static int pfm_sicortex_dispatch_events(pfmlib_input_param_t *inp, void *model_in, pfmlib_output_param_t *outp, void *model_out) { pfmlib_sicortex_input_param_t *mod_sicortex_in = (pfmlib_sicortex_input_param_t *)model_in; return pfm_sicortex_dispatch_counters(inp, mod_sicortex_in, outp); } static int pfm_sicortex_get_event_code(unsigned int i, unsigned int cnt, int *code) { extern pfm_pmu_support_t sicortex_support; /* check validity of counter index */ if (cnt != PFMLIB_CNT_FIRST) { if (cnt < 0 || cnt >= sicortex_support.pmc_count) return PFMLIB_ERR_INVAL; } else { cnt = ffs(sicortex_pe[i].pme_counters)-1; if (cnt == -1) return(PFMLIB_ERR_INVAL); } /* if cnt == 1, shift right by 0, if cnt == 2, shift right by 8 */ /* Works on both 5k anf 20K */ unsigned int tmp = sicortex_pe[i].pme_counters; /* CPU event */ if (tmp & ((1<> (cnt*8)); else return PFMLIB_ERR_INVAL; } /* SCB event */ else { if ((cnt < 6) || (cnt >= sicortex_support.pmc_count)) return PFMLIB_ERR_INVAL; *code = 0xffff & (sicortex_pe[i].pme_code >> 16); } return PFMLIB_SUCCESS; } /* * This function is accessible directly to the user */ int pfm_sicortex_get_event_umask(unsigned int i, unsigned long *umask) { extern pfm_pmu_support_t sicortex_support; if (i >= sicortex_support.pme_count || umask == NULL) return PFMLIB_ERR_INVAL; *umask = 0; //evt_umask(i); return PFMLIB_SUCCESS; } static void pfm_sicortex_get_event_counters(unsigned int j, pfmlib_regmask_t *counters) { extern pfm_pmu_support_t sicortex_support; unsigned int tmp; memset(counters, 0, sizeof(*counters)); tmp = sicortex_pe[j].pme_counters; /* CPU counter */ if (tmp & ((1< core_counters) { /* counting pmds are not contiguous on ICE9*/ for(i=6; i < sicortex_support.pmd_count; i++) pfm_regmask_set(impl_counters, i); } } static void pfm_sicortex_get_hw_counter_width(unsigned int *width) { *width = PMU_GEN_MIPS64_COUNTER_WIDTH; } static char * pfm_sicortex_get_event_name(unsigned int i) { return sicortex_pe[i].pme_name; } static int pfm_sicortex_get_event_description(unsigned int ev, char **str) { char *s; s = sicortex_pe[ev].pme_desc; if (s) { *str = strdup(s); } else { *str = NULL; } return PFMLIB_SUCCESS; } static int pfm_sicortex_get_cycle_event(pfmlib_event_t *e) { return pfm_find_full_event("CPU_CYCLES",e); } static int pfm_sicortex_get_inst_retired(pfmlib_event_t *e) { return pfm_find_full_event("CPU_INSEXEC",e); } /* SiCortex specific functions */ /* CPU counter */ int pfm_sicortex_is_cpu(unsigned int i) { if (i < sicortex_support.pme_count) { unsigned int tmp = sicortex_pe[i].pme_counters; return !(tmp & (1< * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include /* private headers */ #include "pfmlib_priv.h" /* library private */ #include "pfmlib_sparc_priv.h" /* architecture private */ #include "pfmlib_perf_event_priv.h" int pfm_sparc_get_perf_encoding(void *this, pfmlib_event_desc_t *e) { struct perf_event_attr *attr = e->os_data; int ret; ret = pfm_sparc_get_encoding(this, e); if (ret != PFM_SUCCESS) return ret; attr->type = PERF_TYPE_RAW; attr->config = (e->codes[0] << 16) | e->codes[1]; return PFM_SUCCESS; } void pfm_sparc_perf_validate_pattrs(void *this, pfmlib_event_desc_t *e) { int i, compact; for (i = 0; i < e->npattrs; i++) { compact = 0; /* umasks never conflict */ if (e->pattrs[i].type == PFM_ATTR_UMASK) continue; /* * with perf_events, u and k are handled at the OS level * via attr.exclude_* fields */ if (e->pattrs[i].ctrl == PFM_ATTR_CTRL_PMU) { if (e->pattrs[i].idx == SPARC_ATTR_U || e->pattrs[i].idx == SPARC_ATTR_K || e->pattrs[i].idx == SPARC_ATTR_H) compact = 1; } if (e->pattrs[i].ctrl == PFM_ATTR_CTRL_PERF_EVENT) { /* No precise mode on SPARC */ if (e->pattrs[i].idx == PERF_ATTR_PR) compact = 1; } if (compact) { pfmlib_compact_pattrs(e, i); i--; } } } libpfm-4.9.0/lib/pfmlib_perf_event_pmu.c0000664000175000017500000005477313223402656020117 0ustar eranianeranian/* * pfmlib_perf_pmu.c: support for perf_events event table * * Copyright (c) 2009 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include #include #include #include #ifdef __linux__ #include /* for openat() */ #include #endif /* * looks like several distributions do not have * the latest libc with openat support, so disable * for now */ #undef HAS_OPENAT #include "pfmlib_priv.h" #include "pfmlib_perf_event_priv.h" #define PERF_MAX_UMASKS 8 typedef struct { const char *uname; /* unit mask name */ const char *udesc; /* unit mask desc */ uint64_t uid; /* unit mask id */ int uflags; /* umask options */ int grpid; /* group identifier */ } perf_umask_t; typedef struct { const char *name; /* name */ const char *desc; /* description */ const char *equiv; /* event is aliased to */ uint64_t id; /* perf_hw_id or equivalent */ int modmsk; /* modifiers bitmask */ int type; /* perf_type_id */ int numasks; /* number of unit masls */ int ngrp; /* number of umasks groups */ unsigned long umask_ovfl_idx; /* base index of overflow unit masks */ perf_umask_t umasks[PERF_MAX_UMASKS];/* first unit masks */ } perf_event_t; /* * umask options: uflags */ #define PERF_FL_DEFAULT 0x1 /* umask is default for group */ #define PERF_INVAL_OVFL_IDX ((unsigned long)-1) #define PCL_EVT(f, t, m) \ { .name = #f, \ .id = (f), \ .type = (t), \ .desc = #f, \ .equiv = NULL, \ .numasks = 0, \ .modmsk = (m), \ .ngrp = 0, \ .umask_ovfl_idx = PERF_INVAL_OVFL_IDX,\ } #define PCL_EVTA(f, t, m, a) \ { .name = #f, \ .id = a, \ .type = t, \ .desc = #a, \ .equiv = #a, \ .numasks = 0, \ .modmsk = m, \ .ngrp = 0, \ .umask_ovfl_idx = PERF_INVAL_OVFL_IDX,\ } #define PCL_EVT_HW(n) PCL_EVT(PERF_COUNT_HW_##n, PERF_TYPE_HARDWARE, PERF_ATTR_HW) #define PCL_EVT_SW(n) PCL_EVT(PERF_COUNT_SW_##n, PERF_TYPE_SOFTWARE, PERF_ATTR_SW) #define PCL_EVT_AHW(n, a) PCL_EVTA(n, PERF_TYPE_HARDWARE, PERF_ATTR_HW, PERF_COUNT_HW_##a) #define PCL_EVT_ASW(n, a) PCL_EVTA(n, PERF_TYPE_SOFTWARE, PERF_ATTR_SW, PERF_COUNT_SW_##a) #ifndef MAXPATHLEN #define MAXPATHLEN 1024 #endif static char debugfs_mnt[MAXPATHLEN]; #define PERF_ATTR_HW 0 #define PERF_ATTR_SW 0 #include "events/perf_events.h" #define perf_nevents (perf_event_support.pme_count) static perf_event_t *perf_pe = perf_static_events; static perf_event_t *perf_pe_free, *perf_pe_end; static perf_umask_t *perf_um, *perf_um_free, *perf_um_end; static int perf_pe_count, perf_um_count; static inline int pfm_perf_pmu_supported_plm(void *this) { pfmlib_pmu_t *pmu; pmu = pfmlib_get_pmu_by_type(PFM_PMU_TYPE_CORE); if (!pmu) { DPRINT("no core CPU PMU, going with default\n"); pmu = this; } else { DPRINT("guessing plm from %s PMU plm=0x%x\n", pmu->name, pmu->supported_plm); } return pmu->supported_plm; } static inline unsigned long perf_get_ovfl_umask_idx(perf_umask_t *um) { return um - perf_um; } static inline perf_umask_t * perf_get_ovfl_umask(int pidx) { return perf_um+perf_pe[pidx].umask_ovfl_idx; } static inline perf_umask_t * perf_attridx2um(int idx, int attr_idx) { perf_umask_t *um; if (attr_idx < PERF_MAX_UMASKS) { um = &perf_pe[idx].umasks[attr_idx]; } else { um = perf_get_ovfl_umask(idx); um += attr_idx - PERF_MAX_UMASKS; } return um; } /* * figure out the mount point of the debugfs filesystem * * returns -1 if none is found */ static int get_debugfs_mnt(void) { FILE *fp; char *buffer = NULL; size_t len = 0; char *q, *mnt, *fs; int res = -1; fp = fopen("/proc/mounts", "r"); if (!fp) return -1; while(pfmlib_getl(&buffer, &len, fp) != -1) { q = strchr(buffer, ' '); if (!q) continue; mnt = ++q; q = strchr(q, ' '); if (!q) continue; *q = '\0'; fs = ++q; q = strchr(q, ' '); if (!q) continue; *q = '\0'; if (!strcmp(fs, "debugfs")) { strncpy(debugfs_mnt, mnt, MAXPATHLEN); debugfs_mnt[MAXPATHLEN-1]= '\0'; res = 0; break; } } if (buffer) free(buffer); fclose(fp); return res; } #define PERF_ALLOC_EVENT_COUNT (512) #define PERF_ALLOC_UMASK_COUNT (1024) /* * clone static event table into a dynamic * event table * * Used for tracepoints */ static perf_event_t * perf_table_clone(void) { perf_event_t *addr; perf_pe_count = perf_nevents + PERF_ALLOC_EVENT_COUNT; addr = calloc(perf_pe_count, sizeof(perf_event_t)); if (addr) { memcpy(addr, perf_static_events, perf_nevents * sizeof(perf_event_t)); perf_pe_free = addr + perf_nevents; perf_pe_end = perf_pe_free + PERF_ALLOC_EVENT_COUNT; perf_pe = addr; } return addr; } /* * allocate space for one new event in event table * * returns NULL if out-of-memory * * may realloc existing table if necessary for growth */ static perf_event_t * perf_table_alloc_event(void) { perf_event_t *new_pe; retry: if (perf_pe_free < perf_pe_end) return perf_pe_free++; perf_pe_count += PERF_ALLOC_EVENT_COUNT; new_pe = realloc(perf_pe, perf_pe_count * sizeof(perf_event_t)); if (!new_pe) return NULL; perf_pe_free = new_pe + (perf_pe_free - perf_pe); perf_pe_end = perf_pe_free + PERF_ALLOC_EVENT_COUNT; perf_pe = new_pe; goto retry; } /* * allocate space for overflow new unit masks * * Each event can hold up to PERF_MAX_UMASKS. * But gievn we can dynamically add events * which may have more unit masks, then we * put them into a separate overflow unit * masks, table which can grow on demand. * In that case the first PERF_MAX_UMASKS * are in the event, the rest in the overflow * table at index pointed to by event->umask_ovfl_idx * All unit masks for an event are contiguous in the * overflow table. */ static perf_umask_t * perf_table_alloc_umask(void) { perf_umask_t *new_um; retry: if (perf_um_free < perf_um_end) return perf_um_free++; perf_um_count += PERF_ALLOC_UMASK_COUNT; new_um = realloc(perf_um, perf_um_count * sizeof(*new_um)); if (!new_um) return NULL; perf_um_free = new_um + (perf_um_free - perf_um); perf_um_end = perf_um_free + PERF_ALLOC_UMASK_COUNT; perf_um = new_um; goto retry; } #ifdef __GNUC__ #define POTENTIALLY_UNUSED __attribute__((unused)) #endif static void gen_tracepoint_table(void) { DIR *dir1, *dir2; struct dirent *d1, *d2; perf_event_t *p; perf_umask_t *um; char d2path[MAXPATHLEN]; char idpath[MAXPATHLEN]; char id_str[32]; uint64_t id; int fd, err; int POTENTIALLY_UNUSED dir2_fd; int reuse_event = 0; int numasks; char *tracepoint_name; err = get_debugfs_mnt(); if (err == -1) return; strncat(debugfs_mnt, "/tracing/events", MAXPATHLEN-1); debugfs_mnt[MAXPATHLEN-1]= '\0'; dir1 = opendir(debugfs_mnt); if (!dir1) return; p = perf_table_clone(); err = 0; while((d1 = readdir(dir1)) && err >= 0) { if (!strcmp(d1->d_name, ".")) continue; if (!strcmp(d1->d_name, "..")) continue; snprintf(d2path, MAXPATHLEN, "%s/%s", debugfs_mnt, d1->d_name); /* fails if d2path is not a directory */ dir2 = opendir(d2path); if (!dir2) continue; dir2_fd = dirfd(dir2); /* * if a subdir did not fit our expected * tracepoint format, then we reuse the * allocated space (with have no free) */ if (!reuse_event) p = perf_table_alloc_event(); if (!p) break; if (p) p->name = tracepoint_name = strdup(d1->d_name); if (!(p && p->name)) { closedir(dir2); err = -1; continue; } p->desc = "tracepoint"; p->id = -1; p->type = PERF_TYPE_TRACEPOINT; p->umask_ovfl_idx = PERF_INVAL_OVFL_IDX; p->modmsk = 0, p->ngrp = 1; numasks = 0; reuse_event = 0; while((d2 = readdir(dir2))) { if (!strcmp(d2->d_name, ".")) continue; if (!strcmp(d2->d_name, "..")) continue; #ifdef HAS_OPENAT snprintf(idpath, MAXPATHLEN, "%s/id", d2->d_name); fd = openat(dir2_fd, idpath, O_RDONLY); #else snprintf(idpath, MAXPATHLEN, "%s/%s/id", d2path, d2->d_name); fd = open(idpath, O_RDONLY); #endif if (fd == -1) continue; err = read(fd, id_str, sizeof(id_str)); close(fd); if (err < 0) continue; id = strtoull(id_str, NULL, 0); if (numasks < PERF_MAX_UMASKS) um = p->umasks+numasks; else { um = perf_table_alloc_umask(); if (numasks == PERF_MAX_UMASKS) p->umask_ovfl_idx = perf_get_ovfl_umask_idx(um); } if (!um) { err = -1; break; } /* * tracepoint have no event codes * the code is in the unit masks */ p->id = 0; um->uname = strdup(d2->d_name); if (!um->uname) { err = -1; break; } um->udesc = um->uname; um->uid = id; um->grpid = 0; DPRINT("idpath=%s:%s id=%"PRIu64"\n", p->name, um->uname, id); numasks++; } p->numasks = numasks; closedir(dir2); /* * directory was not pointing * to a tree structure we know about */ if (!numasks) { free(tracepoint_name); reuse_event =1; continue; } /* * update total number of events * only when no error is reported */ if (err >= 0) perf_nevents++; reuse_event = 0; } closedir(dir1); } static int pfm_perf_detect(void *this) { #ifdef __linux__ /* ought to find a better way of detecting PERF */ #define PERF_OLD_PROC_FILE "/proc/sys/kernel/perf_counter_paranoid" #define PERF_PROC_FILE "/proc/sys/kernel/perf_event_paranoid" return !(access(PERF_PROC_FILE, F_OK) && access(PERF_OLD_PROC_FILE, F_OK)) ? PFM_SUCCESS: PFM_ERR_NOTSUPP; #else return PFM_SUCCESS; #endif } static int pfm_perf_init(void *this) { pfmlib_pmu_t *pmu = this; perf_pe = perf_static_events; /* * we force the value of pme_count by hand because * the library could be initialized mutltiple times * due to pfm_terminate() and thus we need to start * from the default count */ perf_event_support.pme_count = PME_PERF_EVENT_COUNT; /* must dynamically add tracepoints */ gen_tracepoint_table(); /* dynamically patch supported plm based on CORE PMU plm */ pmu->supported_plm = pfm_perf_pmu_supported_plm(pmu); return PFM_SUCCESS; } static int pfm_perf_get_event_first(void *this) { return 0; } static int pfm_perf_get_event_next(void *this, int idx) { if (idx < 0 || idx >= (perf_nevents-1)) return -1; return idx+1; } static int pfm_perf_add_defaults(pfmlib_event_desc_t *e, unsigned int msk, uint64_t *umask) { perf_event_t *ent; perf_umask_t *um; int i, j, k, added; k = e->nattrs; ent = perf_pe+e->event; for(i=0; msk; msk >>=1, i++) { if (!(msk & 0x1)) continue; added = 0; for(j=0; j < ent->numasks; j++) { if (j < PERF_MAX_UMASKS) { um = &perf_pe[e->event].umasks[j]; } else { um = perf_get_ovfl_umask(e->event); um += j - PERF_MAX_UMASKS; } if (um->grpid != i) continue; if (um->uflags & PERF_FL_DEFAULT) { DPRINT("added default %s for group %d\n", um->uname, i); *umask |= um->uid; e->attrs[k].id = j; e->attrs[k].ival = 0; k++; added++; } } if (!added) { DPRINT("no default found for event %s unit mask group %d\n", ent->name, i); return PFM_ERR_UMASK; } } e->nattrs = k; return PFM_SUCCESS; } static int pfmlib_perf_encode_tp(pfmlib_event_desc_t *e) { perf_umask_t *um; pfmlib_event_attr_info_t *a; int i, nu = 0; e->fstr[0] = '\0'; e->count = 1; evt_strcat(e->fstr, "%s", perf_pe[e->event].name); /* * look for tracepoints */ for(i=0; i < e->nattrs; i++) { a = attr(e, i); if (a->ctrl != PFM_ATTR_CTRL_PMU) continue; if (a->type == PFM_ATTR_UMASK) { /* * tracepoint unit masks cannot be combined */ if (++nu > 1) return PFM_ERR_FEATCOMB; if (a->idx < PERF_MAX_UMASKS) { e->codes[0] = perf_pe[e->event].umasks[a->idx].uid; evt_strcat(e->fstr, ":%s", perf_pe[e->event].umasks[a->idx].uname); } else { um = perf_get_ovfl_umask(e->event); e->codes[0] = um[a->idx - PERF_MAX_UMASKS].uid; evt_strcat(e->fstr, ":%s", um[a->idx - PERF_MAX_UMASKS].uname); } } else return PFM_ERR_ATTR; } return PFM_SUCCESS; } static int pfmlib_perf_encode_hw_cache(pfmlib_event_desc_t *e) { pfmlib_event_attr_info_t *a; perf_event_t *ent; unsigned int msk, grpmsk; uint64_t umask = 0; int i, ret; grpmsk = (1 << perf_pe[e->event].ngrp)-1; ent = perf_pe + e->event; e->codes[0] = ent->id; e->count = 1; e->fstr[0] = '\0'; for(i=0; i < e->nattrs; i++) { a = attr(e, i); if (a->ctrl != PFM_ATTR_CTRL_PMU) continue; if (a->type == PFM_ATTR_UMASK) { e->codes[0] |= ent->umasks[a->idx].uid; msk = 1 << ent->umasks[a->idx].grpid; /* umask cannot be combined in each group */ if ((grpmsk & msk) == 0) return PFM_ERR_UMASK; grpmsk &= ~msk; } else return PFM_ERR_ATTR; /* no mod, no raw umask */ } /* check for missing default umasks */ if (grpmsk) { ret = pfm_perf_add_defaults(e, grpmsk, &umask); if (ret != PFM_SUCCESS) return ret; e->codes[0] |= umask; } /* * reorder all the attributes such that the fstr appears always * the same regardless of how the attributes were submitted. * * cannot sort attr until after we have added the default umasks */ evt_strcat(e->fstr, "%s", ent->name); pfmlib_sort_attr(e); for(i=0; i < e->nattrs; i++) { a = attr(e, i); if (a->ctrl != PFM_ATTR_CTRL_PMU) continue; if (a->type == PFM_ATTR_UMASK) evt_strcat(e->fstr, ":%s", ent->umasks[a->idx].uname); } return PFM_SUCCESS; } static int pfm_perf_get_encoding(void *this, pfmlib_event_desc_t *e) { int ret; switch(perf_pe[e->event].type) { case PERF_TYPE_TRACEPOINT: ret = pfmlib_perf_encode_tp(e); break; case PERF_TYPE_HW_CACHE: ret = pfmlib_perf_encode_hw_cache(e); break; case PERF_TYPE_HARDWARE: case PERF_TYPE_SOFTWARE: ret = PFM_SUCCESS; e->codes[0] = perf_pe[e->event].id; e->count = 1; e->fstr[0] = '\0'; evt_strcat(e->fstr, "%s", perf_pe[e->event].name); break; default: DPRINT("unsupported event type=%d\n", perf_pe[e->event].type); return PFM_ERR_NOTSUPP; } return ret; } static int pfm_perf_get_perf_encoding(void *this, pfmlib_event_desc_t *e) { struct perf_event_attr *attr; int ret; switch(perf_pe[e->event].type) { case PERF_TYPE_TRACEPOINT: ret = pfmlib_perf_encode_tp(e); break; case PERF_TYPE_HW_CACHE: ret = pfmlib_perf_encode_hw_cache(e); break; case PERF_TYPE_HARDWARE: case PERF_TYPE_SOFTWARE: ret = PFM_SUCCESS; e->codes[0] = perf_pe[e->event].id; e->count = 1; e->fstr[0] = '\0'; evt_strcat(e->fstr, "%s", perf_pe[e->event].name); break; default: DPRINT("unsupported event type=%d\n", perf_pe[e->event].type); return PFM_ERR_NOTSUPP; } attr = e->os_data; attr->type = perf_pe[e->event].type; attr->config = e->codes[0]; return ret; } static int pfm_perf_event_is_valid(void *this, int idx) { return idx >= 0 && idx < perf_nevents; } static int pfm_perf_get_event_attr_info(void *this, int idx, int attr_idx, pfmlib_event_attr_info_t *info) { perf_umask_t *um; /* only supports umasks, modifiers handled at OS layer */ um = perf_attridx2um(idx, attr_idx); info->name = um->uname; info->desc = um->udesc; info->equiv= NULL; info->code = um->uid; info->type = PFM_ATTR_UMASK; info->ctrl = PFM_ATTR_CTRL_PMU; info->is_precise = 0; info->is_dfl = 0; info->idx = attr_idx; info->dfl_val64 = 0; return PFM_SUCCESS; } static int pfm_perf_get_event_info(void *this, int idx, pfm_event_info_t *info) { pfmlib_pmu_t *pmu = this; info->name = perf_pe[idx].name; info->desc = perf_pe[idx].desc; info->code = perf_pe[idx].id; info->equiv = perf_pe[idx].equiv; info->idx = idx; info->pmu = pmu->pmu; info->is_precise = 0; /* unit masks + modifiers */ info->nattrs = perf_pe[idx].numasks; return PFM_SUCCESS; } static void pfm_perf_terminate(void *this) { perf_event_t *p; int i, j; if (!(perf_pe && perf_um)) return; /* * free tracepoints name + unit mask names * which are dynamically allocated */ for (i=0; i < perf_nevents; i++) { p = &perf_pe[i]; if (p->type != PERF_TYPE_TRACEPOINT) continue; /* cast to keep compiler happy, we are * freeing the dynamically allocated clone * table, not the static one. We do not want * to create a specific data type */ free((void *)p->name); /* * first PERF_MAX_UMASKS are pre-allocated * the rest is in a separate dynamic table */ for (j=0; j < p->numasks; j++) { if (j == PERF_MAX_UMASKS) break; free((void *)p->umasks[j].uname); } } /* * perf_pe is systematically allocated */ free(perf_pe); perf_pe = NULL; perf_pe_free = perf_pe_end = NULL; if (perf_um) { int n; /* * free the dynamic umasks' uname */ n = perf_um_free - perf_um; for(i=0; i < n; i++) { free((void *)(perf_um[i].uname)); } free(perf_um); perf_um = NULL; perf_um_free = perf_um_end = NULL; } } static int pfm_perf_validate_table(void *this, FILE *fp) { const char *name = perf_event_support.name; perf_umask_t *um; int i, j; int error = 0; for(i=0; i < perf_event_support.pme_count; i++) { if (!perf_pe[i].name) { fprintf(fp, "pmu: %s event%d: :: no name (prev event was %s)\n", name, i, i > 1 ? perf_pe[i-1].name : "??"); error++; } if (!perf_pe[i].desc) { fprintf(fp, "pmu: %s event%d: %s :: no description\n", name, i, perf_pe[i].name); error++; } if (perf_pe[i].type < PERF_TYPE_HARDWARE || perf_pe[i].type >= PERF_TYPE_MAX) { fprintf(fp, "pmu: %s event%d: %s :: invalid type\n", name, i, perf_pe[i].name); error++; } if (perf_pe[i].numasks > PERF_MAX_UMASKS && perf_pe[i].umask_ovfl_idx == PERF_INVAL_OVFL_IDX) { fprintf(fp, "pmu: %s event%d: %s :: numasks too big (<%d)\n", name, i, perf_pe[i].name, PERF_MAX_UMASKS); error++; } if (perf_pe[i].numasks < PERF_MAX_UMASKS && perf_pe[i].umask_ovfl_idx != PERF_INVAL_OVFL_IDX) { fprintf(fp, "pmu: %s event%d: %s :: overflow umask idx defined but not needed (<%d)\n", name, i, perf_pe[i].name, PERF_MAX_UMASKS); error++; } if (perf_pe[i].numasks && perf_pe[i].ngrp == 0) { fprintf(fp, "pmu: %s event%d: %s :: ngrp cannot be zero\n", name, i, perf_pe[i].name); error++; } if (perf_pe[i].numasks == 0 && perf_pe[i].ngrp) { fprintf(fp, "pmu: %s event%d: %s :: ngrp must be zero\n", name, i, perf_pe[i].name); error++; } for(j = 0; j < perf_pe[i].numasks; j++) { if (j < PERF_MAX_UMASKS){ um = perf_pe[i].umasks+j; } else { um = perf_get_ovfl_umask(i); um += j - PERF_MAX_UMASKS; } if (!um->uname) { fprintf(fp, "pmu: %s event%d: %s umask%d :: no name\n", name, i, perf_pe[i].name, j); error++; } if (!um->udesc) { fprintf(fp, "pmu: %s event%d:%s umask%d: %s :: no description\n", name, i, perf_pe[i].name, j, um->uname); error++; } if (perf_pe[i].ngrp && um->grpid >= perf_pe[i].ngrp) { fprintf(fp, "pmu: %s event%d: %s umask%d: %s :: invalid grpid %d (must be < %d)\n", name, i, perf_pe[i].name, j, um->uname, um->grpid, perf_pe[i].ngrp); error++; } } /* check for excess unit masks */ for(; j < PERF_MAX_UMASKS; j++) { if (perf_pe[i].umasks[j].uname || perf_pe[i].umasks[j].udesc) { fprintf(fp, "pmu: %s event%d: %s :: numasks (%d) invalid more events exists\n", name, i, perf_pe[i].name, perf_pe[i].numasks); error++; } } } return error ? PFM_ERR_INVAL : PFM_SUCCESS; } static unsigned int pfm_perf_get_event_nattrs(void *this, int idx) { return perf_pe[idx].numasks; } /* * this function tries to figure out what the underlying core PMU * priv level masks are. It looks for a TYPE_CORE PMU and uses the * first event to determine supported priv level masks. */ /* * remove attrs which are in conflicts (or duplicated) with os layer */ static void pfm_perf_perf_validate_pattrs(void *this, pfmlib_event_desc_t *e) { pfmlib_pmu_t *pmu = this; int i, compact, type; int plm = pmu->supported_plm; for (i = 0; i < e->npattrs; i++) { compact = 0; /* umasks never conflict */ if (e->pattrs[i].type == PFM_ATTR_UMASK) continue; if (e->pattrs[i].ctrl != PFM_ATTR_CTRL_PERF_EVENT) continue; /* * only PERF_TYPE_HARDWARE/HW_CACHE may have * precise mode or hypervisor mode * * there is no way to know for sure for those events * so we allow the modifiers and leave it to the kernel * to decide */ type = perf_pe[e->event].type; if (type == PERF_TYPE_HARDWARE || type == PERF_TYPE_HW_CACHE) { /* no hypervisor mode */ if (e->pattrs[i].idx == PERF_ATTR_H && !(plm & PFM_PLMH)) compact = 1; /* no user mode */ if (e->pattrs[i].idx == PERF_ATTR_U && !(plm & PFM_PLM3)) compact = 1; /* no kernel mode */ if (e->pattrs[i].idx == PERF_ATTR_K && !(plm & PFM_PLM0)) compact = 1; } else { if (e->pattrs[i].idx == PERF_ATTR_PR) compact = 1; /* no hypervisor mode */ if (e->pattrs[i].idx == PERF_ATTR_H) compact = 1; } if (compact) { pfmlib_compact_pattrs(e, i); i--; } } } pfmlib_pmu_t perf_event_support={ .desc = "perf_events generic PMU", .name = "perf", .pmu = PFM_PMU_PERF_EVENT, .pme_count = PME_PERF_EVENT_COUNT, .type = PFM_PMU_TYPE_OS_GENERIC, .max_encoding = 1, .supported_plm = PERF_PLM_ALL, .pmu_detect = pfm_perf_detect, .pmu_init = pfm_perf_init, .pmu_terminate = pfm_perf_terminate, .get_event_encoding[PFM_OS_NONE] = pfm_perf_get_encoding, PFMLIB_ENCODE_PERF(pfm_perf_get_perf_encoding), .get_event_first = pfm_perf_get_event_first, .get_event_next = pfm_perf_get_event_next, .event_is_valid = pfm_perf_event_is_valid, .get_event_info = pfm_perf_get_event_info, .get_event_attr_info = pfm_perf_get_event_attr_info, .validate_table = pfm_perf_validate_table, .get_event_nattrs = pfm_perf_get_event_nattrs, PFMLIB_VALID_PERF_PATTRS(pfm_perf_perf_validate_pattrs), }; libpfm-4.9.0/lib/pfmlib_amd64_fam12h.c0000664000175000017500000000466513223402656017145 0ustar eranianeranian/* * pfmlib_amd64_fam12h.c : AMD64 Family 12h * * Copyright (c) 2011 University of Tennessee * Contributed by Vince Weaver * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_amd64_priv.h" #include "events/amd64_events_fam12h.h" #define DEFINE_FAM12H_REV(d, n, r, pmuid) \ pfmlib_pmu_t amd64_fam12h_##n##_support={ \ .desc = "AMD64 Fam12h "#d, \ .name = "amd64_fam12h_"#n, \ .pmu = pmuid, \ .pmu_rev = r, \ .pme_count = LIBPFM_ARRAY_SIZE(amd64_fam12h_pe),\ .type = PFM_PMU_TYPE_CORE, \ .supported_plm = AMD64_FAM10H_PLM, \ .num_cntrs = 4, \ .max_encoding = 1, \ .pe = amd64_fam12h_pe, \ .atdesc = amd64_mods, \ .flags = PFMLIB_PMU_FL_RAW_UMASK, \ \ .cpu_family = pmuid, \ .pmu_detect = pfm_amd64_family_detect, \ .get_event_encoding[PFM_OS_NONE] = pfm_amd64_get_encoding,\ PFMLIB_ENCODE_PERF(pfm_amd64_get_perf_encoding), \ .get_event_first = pfm_amd64_get_event_first, \ .get_event_next = pfm_amd64_get_event_next, \ .event_is_valid = pfm_amd64_event_is_valid, \ .validate_table = pfm_amd64_validate_table, \ .get_event_info = pfm_amd64_get_event_info, \ .get_event_attr_info = pfm_amd64_get_event_attr_info,\ PFMLIB_VALID_PERF_PATTRS(pfm_amd64_perf_validate_pattrs),\ .get_event_nattrs = pfm_amd64_get_event_nattrs, \ } DEFINE_FAM12H_REV(Llano, llano, 0, PFM_PMU_AMD64_FAM12H_LLANO); libpfm-4.9.0/lib/pfmlib_sparc.c0000664000175000017500000001707113223402656016177 0ustar eranianeranian/* * pfmlib_sparc.c : support for SPARC processors * * Copyright (c) 2011 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * */ #include #include #include #include #include /* private headers */ #include "pfmlib_priv.h" /* library private */ #include "pfmlib_sparc_priv.h" const pfmlib_attr_desc_t sparc_mods[]={ PFM_ATTR_B("k", "monitor at priv level 0"), /* monitor priv level 0 */ PFM_ATTR_B("u", "monitor at priv level 1, 2, 3"), /* monitor priv level 1, 2, 3 */ PFM_ATTR_B("h", "monitor in hypervisor"), /* monitor in hypervisor*/ PFM_ATTR_NULL /* end-marker to avoid exporting number of entries */ }; #define SPARC_NUM_MODS (sizeof(sparc_mods)/sizeof(pfmlib_attr_desc_t) - 1) #ifdef CONFIG_PFMLIB_OS_LINUX /* * helper function to retrieve one value from /proc/cpuinfo * for internal libpfm use only * attr: the attribute (line) to look for * ret_buf: a buffer to store the value of the attribute (as a string) * maxlen : number of bytes of capacity in ret_buf * * ret_buf is null terminated. * * Return: * 0 : attribute found, ret_buf populated * -1: attribute not found */ static int pfmlib_getcpuinfo_attr(const char *attr, char *ret_buf, size_t maxlen) { FILE *fp = NULL; int ret = -1; size_t attr_len, buf_len = 0; char *p, *value = NULL; char *buffer = NULL; if (attr == NULL || ret_buf == NULL || maxlen < 1) return -1; attr_len = strlen(attr); fp = fopen("/proc/cpuinfo", "r"); if (fp == NULL) return -1; while(pfmlib_getl(&buffer, &buf_len, fp) != -1){ /* skip blank lines */ if (*buffer == '\n') continue; p = strchr(buffer, ':'); if (p == NULL) goto error; /* * p+2: +1 = space, +2= firt character * strlen()-1 gets rid of \n */ *p = '\0'; value = p+2; value[strlen(value)-1] = '\0'; if (!strncmp(attr, buffer, attr_len)) break; } strncpy(ret_buf, value, maxlen-1); ret_buf[maxlen-1] = '\0'; ret = 0; error: free(buffer); fclose(fp); return ret; } #else static int pfmlib_getcpuinfo_attr(const char *attr, char *ret_buf, size_t maxlen) { return -1; } #endif static pfm_pmu_t pmu_name_to_pmu_type(char *name) { if (!strcmp(name, "ultra12")) return PFM_PMU_SPARC_ULTRA12; if (!strcmp(name, "ultra3")) return PFM_PMU_SPARC_ULTRA3; if (!strcmp(name, "ultra3i")) return PFM_PMU_SPARC_ULTRA3I; if (!strcmp(name, "ultra3+")) return PFM_PMU_SPARC_ULTRA3PLUS; if (!strcmp(name, "ultra4+")) return PFM_PMU_SPARC_ULTRA4PLUS; if (!strcmp(name, "niagara2")) return PFM_PMU_SPARC_NIAGARA2; if (!strcmp(name, "niagara")) return PFM_PMU_SPARC_NIAGARA1; return PFM_PMU_NONE; } int pfm_sparc_detect(void *this) { pfmlib_pmu_t *pmu = this; pfm_pmu_t model; int ret; char buffer[32]; ret = pfmlib_getcpuinfo_attr("pmu", buffer, sizeof(buffer)); if (ret == -1) return PFM_ERR_NOTSUPP; model = pmu_name_to_pmu_type(buffer); return model == pmu->pmu ? PFM_SUCCESS : PFM_ERR_NOTSUPP; } void pfm_sparc_display_reg(void *this, pfmlib_event_desc_t *e, pfm_sparc_reg_t reg) { __pfm_vbprintf("[0x%x umask=0x%x code=0x%x ctrl_s1=%d ctrl_s0=%d] %s\n", reg.val, reg.config.umask, reg.config.code, reg.config.ctrl_s1, reg.config.ctrl_s0, e->fstr); } int pfm_sparc_get_encoding(void *this, pfmlib_event_desc_t *e) { const sparc_entry_t *pe = this_pe(this); pfmlib_event_attr_info_t *a; pfm_sparc_reg_t reg; int i; //reg.val = pe[e->event].code << 16 | pe[e->event].ctrl; reg.val = pe[e->event].code; for (i = 0; i < e->nattrs; i++) { a = attr(e, i); if (a->ctrl != PFM_ATTR_CTRL_PMU) continue; if (a->type == PFM_ATTR_UMASK) reg.config.umask |= 1 << pe[e->event].umasks[a->idx].ubit; } e->count = 2; e->codes[0] = reg.val; e->codes[1] = pe[e->event].ctrl; evt_strcat(e->fstr, "%s", pe[e->event].name); pfmlib_sort_attr(e); for (i = 0; i < e->nattrs; i++) { a = attr(e, i); if (a->ctrl != PFM_ATTR_CTRL_PMU) continue; if (a->type == PFM_ATTR_UMASK) evt_strcat(e->fstr, ":%s", pe[e->event].umasks[a->idx].uname); } pfm_sparc_display_reg(this, e, reg); return PFM_SUCCESS; } int pfm_sparc_get_event_first(void *this) { return 0; } int pfm_sparc_get_event_next(void *this, int idx) { pfmlib_pmu_t *p = this; if (idx >= (p->pme_count-1)) return -1; return idx+1; } int pfm_sparc_event_is_valid(void *this, int pidx) { pfmlib_pmu_t *p = this; return pidx >= 0 && pidx < p->pme_count; } int pfm_sparc_validate_table(void *this, FILE *fp) { pfmlib_pmu_t *pmu = this; const sparc_entry_t *pe = this_pe(this); int i, j, error = 0; for(i=0; i < pmu->pme_count; i++) { if (!pe[i].name) { fprintf(fp, "pmu: %s event%d: :: no name (prev event was %s)\n", pmu->name, i, i > 1 ? pe[i-1].name : "??"); error++; } if (!pe[i].desc) { fprintf(fp, "pmu: %s event%d: %s :: no description\n", pmu->name, i, pe[i].name); error++; } for(j=i+1; j < pmu->pme_count; j++) { if (pe[i].code == pe[j].code && pe[i].ctrl == pe[j].ctrl) { fprintf(fp, "pmu: %s event%d: %s code: 0x%x is duplicated in event%d : %s\n", pmu->name, i, pe[i].name, pe[i].code, j, pe[j].name); error++; } } } return error ? PFM_ERR_INVAL : PFM_SUCCESS; } int pfm_sparc_get_event_attr_info(void *this, int pidx, int attr_idx, pfmlib_event_attr_info_t *info) { const sparc_entry_t *pe = this_pe(this); int idx; if (attr_idx < pe[pidx].numasks) { info->name = pe[pidx].umasks[attr_idx].uname; info->desc = pe[pidx].umasks[attr_idx].udesc; info->name = pe[pidx].umasks[attr_idx].uname; info->equiv= NULL; info->code = 1 << pe[pidx].umasks[attr_idx].ubit; info->type = PFM_ATTR_UMASK; info->idx = attr_idx; } else { /* * all mods implemented by ALL events */ idx = attr_idx - pe[pidx].numasks; info->name = sparc_mods[idx].name; info->desc = sparc_mods[idx].desc; info->type = sparc_mods[idx].type; info->code = idx; info->type = sparc_mods[idx].type; } info->is_dfl = 0; info->is_precise = 0; info->ctrl = PFM_ATTR_CTRL_PMU;; return PFM_SUCCESS; } int pfm_sparc_get_event_info(void *this, int idx, pfm_event_info_t *info) { pfmlib_pmu_t *pmu = this; const sparc_entry_t *pe = this_pe(this); /* * pmu and idx filled out by caller */ info->name = pe[idx].name; info->desc = pe[idx].desc; info->code = pe[idx].code; info->equiv = NULL; info->idx = idx; /* private index */ info->pmu = pmu->pmu; info->is_precise = 0; info->nattrs = pe[idx].numasks; return PFM_SUCCESS; } unsigned int pfm_sparc_get_event_nattrs(void *this, int pidx) { const sparc_entry_t *pe = this_pe(this); return SPARC_NUM_MODS + pe[pidx].numasks; } libpfm-4.9.0/lib/pfmlib_ppc970.c0000664000175000017500000000615713223402656016114 0ustar eranianeranian/* * pfmlib_ppc970.c : IBM Power 970/970mp support * * Copyright (C) IBM Corporation, 2009. All rights reserved. * Contributed by Corey Ashford (cjashfor@us.ibm.com) * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_power_priv.h" #include "events/ppc970_events.h" #include "events/ppc970mp_events.h" static int pfm_ppc970_detect(void* this) { if (__is_processor(PV_970) || __is_processor(PV_970FX) || __is_processor(PV_970GX)) return PFM_SUCCESS; return PFM_ERR_NOTSUPP; } static int pfm_ppc970mp_detect(void* this) { if (__is_processor(PV_970MP)) return PFM_SUCCESS; return PFM_ERR_NOTSUPP; } pfmlib_pmu_t ppc970_support={ .desc = "PPC970", .name = "ppc970", .pmu = PFM_PMU_PPC970, .pme_count = LIBPFM_ARRAY_SIZE(ppc970_pe), .max_encoding = 1, .pe = ppc970_pe, .pmu_detect = pfm_ppc970_detect, .get_event_encoding[PFM_OS_NONE] = pfm_gen_powerpc_get_encoding, PFMLIB_ENCODE_PERF(pfm_gen_powerpc_get_perf_encoding), PFMLIB_VALID_PERF_PATTRS(pfm_gen_powerpc_perf_validate_pattrs), .get_event_first = pfm_gen_powerpc_get_event_first, .get_event_next = pfm_gen_powerpc_get_event_next, .event_is_valid = pfm_gen_powerpc_event_is_valid, .validate_table = pfm_gen_powerpc_validate_table, .get_event_info = pfm_gen_powerpc_get_event_info, .get_event_attr_info = pfm_gen_powerpc_get_event_attr_info, }; pfmlib_pmu_t ppc970mp_support={ .desc = "PPC970MP", .name = "ppc970mp", .pmu = PFM_PMU_PPC970MP, .pme_count = LIBPFM_ARRAY_SIZE(ppc970mp_pe), .max_encoding = 1, .pe = ppc970mp_pe, .pmu_detect = pfm_ppc970mp_detect, .get_event_encoding[PFM_OS_NONE] = pfm_gen_powerpc_get_encoding, PFMLIB_ENCODE_PERF(pfm_gen_powerpc_get_perf_encoding), PFMLIB_VALID_PERF_PATTRS(pfm_gen_powerpc_perf_validate_pattrs), .get_event_first = pfm_gen_powerpc_get_event_first, .get_event_next = pfm_gen_powerpc_get_event_next, .event_is_valid = pfm_gen_powerpc_event_is_valid, .validate_table = pfm_gen_powerpc_validate_table, .get_event_info = pfm_gen_powerpc_get_event_info, .get_event_attr_info = pfm_gen_powerpc_get_event_attr_info, }; libpfm-4.9.0/lib/pfmlib_perf_event_raw.c0000664000175000017500000001070713223402656020074 0ustar eranianeranian/* * pfmlib_perf_events_raw.c: support for raw event syntax * * Copyright (c) 2014 Google, Inc. All rights reserved * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include #include #include "pfmlib_priv.h" #include "pfmlib_perf_event_priv.h" static int pfm_perf_raw_detect(void *this) { #ifdef __linux__ /* ought to find a better way of detecting PERF */ #define PERF_OLD_PROC_FILE "/proc/sys/kernel/perf_counter_paranoid" #define PERF_PROC_FILE "/proc/sys/kernel/perf_event_paranoid" return !(access(PERF_PROC_FILE, F_OK) && access(PERF_OLD_PROC_FILE, F_OK)) ? PFM_SUCCESS: PFM_ERR_NOTSUPP; #else return PFM_SUCCESS; #endif } static int pfm_perf_raw_get_event_first(void *this) { return 0; } static int pfm_perf_raw_get_event_next(void *this, int idx) { /* only one pseudo event */ return -1; } static int pfm_perf_raw_get_encoding(void *this, pfmlib_event_desc_t *e) { /* * actual enoding done in pfm_perf_raw_match_event() */ e->fstr[0] = '\0'; evt_strcat(e->fstr, "r%"PRIx64, e->codes[0]); return PFM_SUCCESS; } static int pfm_perf_raw_get_perf_encoding(void *this, pfmlib_event_desc_t *e) { struct perf_event_attr *attr; attr = e->os_data; attr->type = PERF_TYPE_RAW; attr->config = e->codes[0]; attr->config1 = e->codes[1]; attr->config2 = e->codes[2]; return PFM_SUCCESS; } static int pfm_perf_raw_event_is_valid(void *this, int idx) { return idx == 0; } static int pfm_perf_raw_get_event_attr_info(void *this, int idx, int attr_idx, pfmlib_event_attr_info_t *info) { return PFM_ERR_ATTR; } static int pfm_perf_raw_get_event_info(void *this, int idx, pfm_event_info_t *info) { pfmlib_pmu_t *pmu = this; info->name = "r0000"; info->desc = "perf_events raw event syntax: r[0-9a-fA-F]+", info->code = 0; info->equiv = NULL; info->idx = 0; info->pmu = pmu->pmu; info->is_precise = 0; /* unit masks + modifiers */ info->nattrs = 0; return PFM_SUCCESS; } static unsigned int pfm_perf_raw_get_event_nattrs(void *this, int idx) { return 0; } /* * remove attrs which are in conflicts (or duplicated) with os layer */ static void pfm_perf_raw_perf_validate_pattrs(void *this, pfmlib_event_desc_t *e) { } /* * returns 0 if match (like strcmp()) */ static int pfm_perf_raw_match_event(void *this, pfmlib_event_desc_t *d, const char *e, const char *s) { uint64_t code; int ret; if (*s != 'r' || !isxdigit(*(s+1))) return 1; ret = sscanf(s+1, "%"PRIx64, &code); if (ret != 1) return 1; /* * stash code in final position */ d->codes[0] = code; d->count = 1; return 0; } pfmlib_pmu_t perf_event_raw_support={ .desc = "perf_events raw PMU", .name = "perf_raw", .pmu = PFM_PMU_PERF_EVENT_RAW, .pme_count = 1, .type = PFM_PMU_TYPE_OS_GENERIC, .max_encoding = 1, .supported_plm = PERF_PLM_ALL, .pmu_detect = pfm_perf_raw_detect, .get_event_encoding[PFM_OS_NONE] = pfm_perf_raw_get_encoding, PFMLIB_ENCODE_PERF(pfm_perf_raw_get_perf_encoding), .get_event_first = pfm_perf_raw_get_event_first, .get_event_next = pfm_perf_raw_get_event_next, .event_is_valid = pfm_perf_raw_event_is_valid, .get_event_info = pfm_perf_raw_get_event_info, .get_event_attr_info = pfm_perf_raw_get_event_attr_info, .get_event_nattrs = pfm_perf_raw_get_event_nattrs, .match_event = pfm_perf_raw_match_event, PFMLIB_VALID_PERF_PATTRS(pfm_perf_raw_perf_validate_pattrs), }; libpfm-4.9.0/lib/pfmlib_intel_snbep_unc_priv.h0000664000175000017500000003100713223402656021276 0ustar eranianeranian/* * pfmlib_intel_snbep_unc_priv.c : Intel SandyBridge/IvyBridge-EP common definitions * * Copyright (c) 2012 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef __PFMLIB_INTEL_SNBEP_UNC_PRIV_H__ #define __PFMLIB_INTEL_SNBEP_UNC_PRIV_H__ /* * Intel x86 specific pmu flags (pmu->flags 16 MSB) */ #define INTEL_PMU_FL_UNC_OCC 0x10000 /* PMU has occupancy counter filters */ #define INTEL_PMU_FL_UNC_CBO 0x20000 /* PMU is Cbox */ #define SNBEP_UNC_ATTR_E 0 #define SNBEP_UNC_ATTR_I 1 #define SNBEP_UNC_ATTR_T8 2 #define SNBEP_UNC_ATTR_T5 3 #define SNBEP_UNC_ATTR_TF 4 #define SNBEP_UNC_ATTR_CF 5 #define SNBEP_UNC_ATTR_NF 6 /* for filter0 */ #define SNBEP_UNC_ATTR_FF 7 #define SNBEP_UNC_ATTR_A 8 #define SNBEP_UNC_ATTR_NF1 9 /* for filter1 */ #define SNBEP_UNC_ATTR_ISOC 10 /* isochronous */ #define SNBEP_UNC_ATTR_NC 11 /* non-coherent */ #define SNBEP_UNC_ATTR_CF1 12 /* core-filter hswep */ #define _SNBEP_UNC_ATTR_I (1 << SNBEP_UNC_ATTR_I) #define _SNBEP_UNC_ATTR_E (1 << SNBEP_UNC_ATTR_E) #define _SNBEP_UNC_ATTR_T8 (1 << SNBEP_UNC_ATTR_T8) #define _SNBEP_UNC_ATTR_T5 (1 << SNBEP_UNC_ATTR_T5) #define _SNBEP_UNC_ATTR_TF (1 << SNBEP_UNC_ATTR_TF) #define _SNBEP_UNC_ATTR_CF (1 << SNBEP_UNC_ATTR_CF) #define _SNBEP_UNC_ATTR_NF (1 << SNBEP_UNC_ATTR_NF) #define _SNBEP_UNC_ATTR_FF (1 << SNBEP_UNC_ATTR_FF) #define _SNBEP_UNC_ATTR_A (1 << SNBEP_UNC_ATTR_A) #define _SNBEP_UNC_ATTR_NF1 (1 << SNBEP_UNC_ATTR_NF1) #define _SNBEP_UNC_ATTR_ISOC (1 << SNBEP_UNC_ATTR_ISOC) #define _SNBEP_UNC_ATTR_NC (1 << SNBEP_UNC_ATTR_NC) #define _SNBEP_UNC_ATTR_CF1 (1 << SNBEP_UNC_ATTR_CF1) #define SNBEP_UNC_IRP_ATTRS \ (_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8) #define HSWEP_UNC_IRP_ATTRS \ (_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8|_SNBEP_UNC_ATTR_I) #define BDX_UNC_IRP_ATTRS HSWEP_UNC_IRP_ATTRS #define SNBEP_UNC_R3QPI_ATTRS \ (_SNBEP_UNC_ATTR_I|_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8) #define HSWEP_UNC_R3QPI_ATTRS SNBEP_UNC_R3QPI_ATTRS #define BDX_UNC_R3QPI_ATTRS SNBEP_UNC_R3QPI_ATTRS #define IVBEP_UNC_R3QPI_ATTRS \ (_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8) #define SNBEP_UNC_R2PCIE_ATTRS \ (_SNBEP_UNC_ATTR_I|_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8) #define HSWEP_UNC_R2PCIE_ATTRS SNBEP_UNC_R2PCIE_ATTRS #define BDX_UNC_R2PCIE_ATTRS SNBEP_UNC_R2PCIE_ATTRS #define IVBEP_UNC_R2PCIE_ATTRS \ (_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8) #define SNBEP_UNC_QPI_ATTRS \ (_SNBEP_UNC_ATTR_I|_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8) #define IVBEP_UNC_QPI_ATTRS \ (_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8) #define HSWEP_UNC_QPI_ATTRS SNBEP_UNC_QPI_ATTRS #define BDX_UNC_QPI_ATTRS SNBEP_UNC_QPI_ATTRS #define SNBEP_UNC_UBO_ATTRS \ (_SNBEP_UNC_ATTR_I|_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8) #define IVBEP_UNC_UBO_ATTRS \ (_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8) #define HSWEP_UNC_UBO_ATTRS SNBEP_UNC_UBO_ATTRS #define BDX_UNC_UBO_ATTRS SNBEP_UNC_UBO_ATTRS #define SNBEP_UNC_PCU_ATTRS \ (_SNBEP_UNC_ATTR_I|_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T5) #define IVBEP_UNC_PCU_ATTRS \ (_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T5) #define HSWEP_UNC_PCU_ATTRS SNBEP_UNC_PCU_ATTRS #define BDX_UNC_PCU_ATTRS \ (_SNBEP_UNC_ATTR_I|_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8) #define SNBEP_UNC_PCU_BAND_ATTRS \ (SNBEP_UNC_PCU_ATTRS | _SNBEP_UNC_ATTR_FF) #define IVBEP_UNC_PCU_BAND_ATTRS \ (IVBEP_UNC_PCU_ATTRS | _SNBEP_UNC_ATTR_FF) #define HSWEP_UNC_PCU_BAND_ATTRS SNBEP_UNC_PCU_BAND_ATTRS #define BDX_UNC_PCU_BAND_ATTRS SNBEP_UNC_PCU_BAND_ATTRS #define SNBEP_UNC_IMC_ATTRS \ (_SNBEP_UNC_ATTR_I|_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8) #define IVBEP_UNC_IMC_ATTRS \ (_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8) #define HSWEP_UNC_IMC_ATTRS SNBEP_UNC_IMC_ATTRS #define BDX_UNC_IMC_ATTRS SNBEP_UNC_IMC_ATTRS #define SNBEP_UNC_CBO_ATTRS \ (_SNBEP_UNC_ATTR_I |\ _SNBEP_UNC_ATTR_E |\ _SNBEP_UNC_ATTR_T8 |\ _SNBEP_UNC_ATTR_CF |\ _SNBEP_UNC_ATTR_TF) #define IVBEP_UNC_CBO_ATTRS \ (_SNBEP_UNC_ATTR_E |\ _SNBEP_UNC_ATTR_T8 |\ _SNBEP_UNC_ATTR_CF |\ _SNBEP_UNC_ATTR_TF) #define HSWEP_UNC_CBO_ATTRS \ (_SNBEP_UNC_ATTR_E |\ _SNBEP_UNC_ATTR_T8 |\ _SNBEP_UNC_ATTR_CF1 |\ _SNBEP_UNC_ATTR_TF) #define BDX_UNC_CBO_ATTRS HSWEP_UNC_CBO_ATTRS #define SNBEP_UNC_CBO_NID_ATTRS \ (SNBEP_UNC_CBO_ATTRS|_SNBEP_UNC_ATTR_NF) #define IVBEP_UNC_CBO_NID_ATTRS \ (IVBEP_UNC_CBO_ATTRS|_SNBEP_UNC_ATTR_NF1) #define HSWEP_UNC_CBO_NID_ATTRS \ (HSWEP_UNC_CBO_ATTRS | _SNBEP_UNC_ATTR_NF1) #define BDX_UNC_CBO_NID_ATTRS HSWEP_UNC_CBO_NID_ATTRS #define SNBEP_UNC_HA_ATTRS \ (_SNBEP_UNC_ATTR_I|_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8) #define IVBEP_UNC_HA_ATTRS \ (_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8) #define HSWEP_UNC_HA_ATTRS \ (_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8|_SNBEP_UNC_ATTR_I) #define BDX_UNC_HA_ATTRS \ (_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8|_SNBEP_UNC_ATTR_I) #define SNBEP_UNC_HA_OPC_ATTRS \ (SNBEP_UNC_HA_ATTRS|_SNBEP_UNC_ATTR_A) #define HSWEP_UNC_SBO_ATTRS \ (_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8|_SNBEP_UNC_ATTR_I) #define BDX_UNC_SBO_ATTRS \ (_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8|_SNBEP_UNC_ATTR_I) #define KNL_UNC_CHA_TOR_ATTRS _SNBEP_UNC_ATTR_NF1 typedef union { uint64_t val; struct { unsigned long unc_event:8; /* event code */ unsigned long unc_umask:8; /* unit mask */ unsigned long unc_res1:1; /* reserved */ unsigned long unc_rst:1; /* reset */ unsigned long unc_edge:1; /* edge detec */ unsigned long unc_res2:3; /* reserved */ unsigned long unc_en:1; /* enable */ unsigned long unc_inv:1; /* invert counter mask */ unsigned long unc_thres:8; /* counter mask */ unsigned long unc_res3:32; /* reserved */ } com; /* covers common fields for cbox, ha, imc, ubox, r2pcie, r3qpi, sbox */ struct { unsigned long unc_event:8; /* event code */ unsigned long unc_umask:8; /* unit mask */ unsigned long unc_res1:1; /* reserved */ unsigned long unc_rst:1; /* reset */ unsigned long unc_edge:1; /* edge detect */ unsigned long unc_tid:1; /* tid filter enable */ unsigned long unc_res2:2; /* reserved */ unsigned long unc_en:1; /* enable */ unsigned long unc_inv:1; /* invert counter mask */ unsigned long unc_thres:8; /* counter mask */ unsigned long unc_res3:32; /* reserved */ } cbo; /* covers c-box */ struct { unsigned long unc_event:8; /* event code */ unsigned long unc_res1:6; /* reserved */ unsigned long unc_occ:2; /* occ select */ unsigned long unc_res2:1; /* reserved */ unsigned long unc_rst:1; /* reset */ unsigned long unc_edge:1; /* edge detec */ unsigned long unc_res3:1; /* reserved */ unsigned long unc_res4:2; /* reserved */ unsigned long unc_en:1; /* enable */ unsigned long unc_inv:1; /* invert counter mask */ unsigned long unc_thres:5; /* threshold */ unsigned long unc_res5:1; /* reserved */ unsigned long unc_occ_inv:1; /* occupancy invert */ unsigned long unc_occ_edge:1; /* occupancy edge detect */ unsigned long unc_res6:32; /* reserved */ } pcu; /* covers pcu */ struct { unsigned long unc_event:8; /* event code */ unsigned long unc_res1:6; /* reserved */ unsigned long unc_occ:2; /* occ select */ unsigned long unc_res2:1; /* reserved */ unsigned long unc_rst:1; /* reset */ unsigned long unc_edge:1; /* edge detec */ unsigned long unc_res3:1; /* reserved */ unsigned long unc_ov_en:1; /* overflow enable */ unsigned long unc_sel_ext:1; /* event_sel extension */ unsigned long unc_en:1; /* enable */ unsigned long unc_res4:1; /* reserved */ unsigned long unc_thres:5; /* threshold */ unsigned long unc_res5:1; /* reserved */ unsigned long unc_occ_inv:1; /* occupancy invert */ unsigned long unc_occ_edge:1; /* occupancy edge detect */ unsigned long unc_res6:32; /* reserved */ } ivbep_pcu; /* covers ivb-ep pcu */ struct { unsigned long unc_event:8; /* event code */ unsigned long unc_umask:8; /* unit maks */ unsigned long unc_res1:1; /* reserved */ unsigned long unc_rst:1; /* reset */ unsigned long unc_edge:1; /* edge detec */ unsigned long unc_res2:1; /* reserved */ unsigned long unc_res3:1; /* reserved */ unsigned long unc_event_ext:1; /* event code extension */ unsigned long unc_en:1; /* enable */ unsigned long unc_inv:1; /* invert counter mask */ unsigned long unc_thres:8; /* threshold */ unsigned long unc_res4:32; /* reserved */ } qpi; /* covers qpi */ struct { unsigned long tid:1; unsigned long cid:3; unsigned long res0:1; unsigned long res1:3; unsigned long res2:2; unsigned long nid:8; unsigned long state:5; unsigned long opc:9; unsigned long res3:1; unsigned long res4:32; } cbo_filt; /* cbox filter */ struct { unsigned long tid:1; unsigned long cid:4; unsigned long res0:12; unsigned long state:6; unsigned long res1:9; unsigned long res2:32; } ivbep_cbo_filt0; /* ivbep cbox filter0 */ struct { unsigned long nid:16; unsigned long res0:4; unsigned long opc:9; unsigned long res1:1; unsigned long nc:1; unsigned long isoc:1; unsigned long res2:32; } ivbep_cbo_filt1; /* ivbep cbox filter1 */ struct { unsigned long tid:1; unsigned long cid:5; unsigned long res0:11; unsigned long state:7; unsigned long res1:8; unsigned long res2:32; } hswep_cbo_filt0; /* hswep cbox filter0 */ struct { unsigned long nid:16; unsigned long res0:4; unsigned long opc:9; unsigned long res1:1; unsigned long nc:1; unsigned long isoc:1; unsigned long res2:32; } hswep_cbo_filt1; /* hswep cbox filter1 */ struct { unsigned long filt0:8; /* band0 freq filter */ unsigned long filt1:8; /* band1 freq filter */ unsigned long filt2:8; /* band2 freq filter */ unsigned long filt3:8; /* band3 freq filter */ unsigned long res1:32; /* reserved */ } pcu_filt; struct { unsigned long res1:6; unsigned long lo_addr:26; /* lo order 26b */ unsigned long hi_addr:14; /* hi order 14b */ unsigned long res2:18; /* reserved */ } ha_addr; struct { unsigned long opc:6; /* opcode match */ unsigned long res1:26; /* reserved */ unsigned long res2:32; /* reserved */ } ha_opc; struct { unsigned long unc_event:8; /* event code */ unsigned long unc_umask:8; /* unit mask */ unsigned long unc_res1:1; /* reserved */ unsigned long unc_rst:1; /* reset */ unsigned long unc_edge:1; /* edge detec */ unsigned long unc_res2:3; /* reserved */ unsigned long unc_en:1; /* enable */ unsigned long unc_res3:1; /* reserved */ unsigned long unc_thres:8; /* counter mask */ unsigned long unc_res4:32; /* reserved */ } irp; /* covers irp */ } pfm_snbep_unc_reg_t; extern void pfm_intel_snbep_unc_perf_validate_pattrs(void *this, pfmlib_event_desc_t *e); extern int pfm_intel_snbep_unc_get_encoding(void *this, pfmlib_event_desc_t *e); extern const pfmlib_attr_desc_t snbep_unc_mods[]; extern int pfm_intel_snbep_unc_detect(void *this); extern int pfm_intel_ivbep_unc_detect(void *this); extern int pfm_intel_hswep_unc_detect(void *this); extern int pfm_intel_knl_unc_detect(void *this); extern int pfm_intel_bdx_unc_detect(void *this); extern int pfm_intel_snbep_unc_get_perf_encoding(void *this, pfmlib_event_desc_t *e); extern int pfm_intel_snbep_unc_can_auto_encode(void *this, int pidx, int uidx); extern int pfm_intel_snbep_unc_get_event_attr_info(void *this, int pidx, int attr_idx, pfmlib_event_attr_info_t *info); static inline int is_cbo_filt_event(void *this, pfm_intel_x86_reg_t reg) { pfmlib_pmu_t *pmu = this; uint64_t sel = reg.sel_event_select; /* * umask bit 0 must be 1 (OPCODE) * TOR_INSERT: event code 0x35 * TOR_OCCUPANCY: event code 0x36 * LLC_LOOKUP : event code 0x34 */ return (pmu->flags & INTEL_PMU_FL_UNC_CBO) && (reg.sel_unit_mask & 0x1) && (sel == 0x35 || sel == 0x36 || sel == 0x34); } #endif /* __PFMLIB_INTEL_SNBEP_UNC_PRIV_H__ */ libpfm-4.9.0/lib/pfmlib_ia64_priv.h0000664000175000017500000010033513223402656016673 0ustar eranianeranian/* * Copyright (c) 2003-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux/ia64. */ #ifndef __PFMLIB_PRIV_IA64_H__ #define __PFMLIB_PRIV_IA64_H__ /* * architected PMC register structure */ typedef union { unsigned long pmc_val; /* generic PMC register */ struct { unsigned long pmc_plm:4; /* privilege level mask */ unsigned long pmc_ev:1; /* external visibility */ unsigned long pmc_oi:1; /* overflow interrupt */ unsigned long pmc_pm:1; /* privileged monitor */ unsigned long pmc_ig1:1; /* reserved */ unsigned long pmc_es:8; /* event select */ unsigned long pmc_ig2:48; /* reserved */ } pmc_gen_count_reg; /* This is the Itanium-specific PMC layout for counter config */ struct { unsigned long pmc_plm:4; /* privilege level mask */ unsigned long pmc_ev:1; /* external visibility */ unsigned long pmc_oi:1; /* overflow interrupt */ unsigned long pmc_pm:1; /* privileged monitor */ unsigned long pmc_ig1:1; /* reserved */ unsigned long pmc_es:7; /* event select */ unsigned long pmc_ig2:1; /* reserved */ unsigned long pmc_umask:4; /* unit mask */ unsigned long pmc_thres:3; /* threshold */ unsigned long pmc_ig3:1; /* reserved (missing from table on p6-17) */ unsigned long pmc_ism:2; /* instruction set mask */ unsigned long pmc_ig4:38; /* reserved */ } pmc_ita_count_reg; /* Opcode matcher */ struct { unsigned long ignored1:3; unsigned long mask:27; /* mask encoding bits {40:27}{12:0} */ unsigned long ignored2:3; unsigned long match:27; /* match encoding bits {40:27}{12:0} */ unsigned long b:1; /* B-syllable */ unsigned long f:1; /* F-syllable */ unsigned long i:1; /* I-syllable */ unsigned long m:1; /* M-syllable */ } pmc8_9_ita_reg; /* Instruction Event Address Registers */ struct { unsigned long iear_plm:4; /* privilege level mask */ unsigned long iear_ig1:2; /* reserved */ unsigned long iear_pm:1; /* privileged monitor */ unsigned long iear_tlb:1; /* cache/tlb mode */ unsigned long iear_ig2:8; /* reserved */ unsigned long iear_umask:4; /* unit mask */ unsigned long iear_ig3:4; /* reserved */ unsigned long iear_ism:2; /* instruction set */ unsigned long iear_ig4:38; /* reserved */ } pmc10_ita_reg; /* Data Event Address Registers */ struct { unsigned long dear_plm:4; /* privilege level mask */ unsigned long dear_ig1:2; /* reserved */ unsigned long dear_pm:1; /* privileged monitor */ unsigned long dear_tlb:1; /* cache/tlb mode */ unsigned long dear_ig2:8; /* reserved */ unsigned long dear_umask:4; /* unit mask */ unsigned long dear_ig3:4; /* reserved */ unsigned long dear_ism:2; /* instruction set */ unsigned long dear_ig4:2; /* reserved */ unsigned long dear_pt:1; /* pass tags */ unsigned long dear_ig5:35; /* reserved */ } pmc11_ita_reg; /* Branch Trace Buffer registers */ struct { unsigned long btbc_plm:4; /* privilege level */ unsigned long btbc_ig1:2; unsigned long btbc_pm:1; /* privileged monitor */ unsigned long btbc_tar:1; /* target address register */ unsigned long btbc_tm:2; /* taken mask */ unsigned long btbc_ptm:2; /* predicted taken address mask */ unsigned long btbc_ppm:2; /* predicted predicate mask */ unsigned long btbc_bpt:1; /* branch prediction table */ unsigned long btbc_bac:1; /* branch address calculator */ unsigned long btbc_ig2:48; } pmc12_ita_reg; struct { unsigned long irange_ta:1; /* tag all bit */ unsigned long irange_ig:63; } pmc13_ita_reg; /* This is the Itanium2-specific PMC layout for counter config */ struct { unsigned long pmc_plm:4; /* privilege level mask */ unsigned long pmc_ev:1; /* external visibility */ unsigned long pmc_oi:1; /* overflow interrupt */ unsigned long pmc_pm:1; /* privileged monitor */ unsigned long pmc_ig1:1; /* reserved */ unsigned long pmc_es:8; /* event select */ unsigned long pmc_umask:4; /* unit mask */ unsigned long pmc_thres:3; /* threshold */ unsigned long pmc_enable:1; /* pmc4 only: power enable bit */ unsigned long pmc_ism:2; /* instruction set mask */ unsigned long pmc_ig2:38; /* reserved */ } pmc_ita2_counter_reg; /* opcode matchers */ struct { unsigned long opcm_ig_ad:1; /* ignore instruction address range checking */ unsigned long opcm_inv:1; /* invert range check */ unsigned long opcm_bit2:1; /* must be 1 */ unsigned long opcm_mask:27; /* mask encoding bits {41:27}{12:0} */ unsigned long opcm_ig1:3; /* reserved */ unsigned long opcm_match:27; /* match encoding bits {41:27}{12:0} */ unsigned long opcm_b:1; /* B-syllable */ unsigned long opcm_f:1; /* F-syllable */ unsigned long opcm_i:1; /* I-syllable */ unsigned long opcm_m:1; /* M-syllable */ } pmc8_9_ita2_reg; /* * instruction event address register configuration * * The register has two layout depending on the value of the ct field. * In cache mode(ct=1x): * - ct is 1 bit, umask is 8 bits * In TLB mode (ct=00): * - ct is 2 bits, umask is 7 bits * ct=11 <=> cache mode and use a latency with eighth bit set * ct=01 => nothing monitored * * The ct=01 value is the only reason why we cannot fix the layout * to ct 1 bit and umask 8 bits. Even though in TLB mode, only 6 bits * are effectively used for the umask, if the user inadvertently use * a umask with the most significant bit set, it would be equivalent * to no monitoring. */ struct { unsigned long iear_plm:4; /* privilege level mask */ unsigned long iear_pm:1; /* privileged monitor */ unsigned long iear_umask:8; /* event unit mask: 7 bits in TLB mode, 8 bits in cache mode */ unsigned long iear_ct:1; /* cache tlb bit13: 0 for TLB mode, 1 for cache mode */ unsigned long iear_ism:2; /* instruction set */ unsigned long iear_ig4:48; /* reserved */ } pmc10_ita2_cache_reg; struct { unsigned long iear_plm:4; /* privilege level mask */ unsigned long iear_pm:1; /* privileged monitor */ unsigned long iear_umask:7; /* event unit mask: 7 bits in TLB mode, 8 bits in cache mode */ unsigned long iear_ct:2; /* cache tlb bit13: 0 for TLB mode, 1 for cache mode */ unsigned long iear_ism:2; /* instruction set */ unsigned long iear_ig4:48; /* reserved */ } pmc10_ita2_tlb_reg; /* data event address register configuration */ struct { unsigned long dear_plm:4; /* privilege level mask */ unsigned long dear_ig1:2; /* reserved */ unsigned long dear_pm:1; /* privileged monitor */ unsigned long dear_mode:2; /* mode */ unsigned long dear_ig2:7; /* reserved */ unsigned long dear_umask:4; /* unit mask */ unsigned long dear_ig3:4; /* reserved */ unsigned long dear_ism:2; /* instruction set */ unsigned long dear_ig4:38; /* reserved */ } pmc11_ita2_reg; /* branch trace buffer configuration register */ struct { unsigned long btbc_plm:4; /* privilege level */ unsigned long btbc_ig1:2; unsigned long btbc_pm:1; /* privileged monitor */ unsigned long btbc_ds:1; /* data selector */ unsigned long btbc_tm:2; /* taken mask */ unsigned long btbc_ptm:2; /* predicted taken address mask */ unsigned long btbc_ppm:2; /* predicted predicate mask */ unsigned long btbc_brt:2; /* branch type mask */ unsigned long btbc_ig2:48; } pmc12_ita2_reg; /* data address range configuration register */ struct { unsigned long darc_ig1:3; unsigned long darc_cfg_dbrp0:2; /* constraint on dbr0 */ unsigned long darc_ig2:6; unsigned long darc_cfg_dbrp1:2; /* constraint on dbr1 */ unsigned long darc_ig3:6; unsigned long darc_cfg_dbrp2:2; /* constraint on dbr2 */ unsigned long darc_ig4:6; unsigned long darc_cfg_dbrp3:2; /* constraint on dbr3 */ unsigned long darc_ig5:16; unsigned long darc_ena_dbrp0:1; /* enable constraint dbr0 */ unsigned long darc_ena_dbrp1:1; /* enable constraint dbr1 */ unsigned long darc_ena_dbrp2:1; /* enable constraint dbr2 */ unsigned long darc_ena_dbrp3:1; /* enable constraint dbr3 */ unsigned long darc_ig6:15; } pmc13_ita2_reg; /* instruction address range configuration register */ struct { unsigned long iarc_ig1:1; unsigned long iarc_ibrp0:1; /* constrained by ibr0 */ unsigned long iarc_ig2:2; unsigned long iarc_ibrp1:1; /* constrained by ibr1 */ unsigned long iarc_ig3:2; unsigned long iarc_ibrp2:1; /* constrained by ibr2 */ unsigned long iarc_ig4:2; unsigned long iarc_ibrp3:1; /* constrained by ibr3 */ unsigned long iarc_ig5:2; unsigned long iarc_fine:1; /* fine mode */ unsigned long iarc_ig6:50; } pmc14_ita2_reg; /* opcode matcher configuration register */ struct { unsigned long opcmc_ibrp0_pmc8:1; unsigned long opcmc_ibrp1_pmc9:1; unsigned long opcmc_ibrp2_pmc8:1; unsigned long opcmc_ibrp3_pmc9:1; unsigned long opcmc_ig1:60; } pmc15_ita2_reg; /* This is the Montecito-specific PMC layout for counters PMC4-PMC15 */ struct { unsigned long pmc_plm:4; /* privilege level mask */ unsigned long pmc_ev:1; /* external visibility */ unsigned long pmc_oi:1; /* overflow interrupt */ unsigned long pmc_pm:1; /* privileged monitor */ unsigned long pmc_ig1:1; /* ignored */ unsigned long pmc_es:8; /* event select */ unsigned long pmc_umask:4; /* unit mask */ unsigned long pmc_thres:3; /* threshold */ unsigned long pmc_ig2:1; /* ignored */ unsigned long pmc_ism:2; /* instruction set: must be 2 */ unsigned long pmc_all:1; /* 0=only self, 1=both threads */ unsigned long pmc_i:1; /* Invalidate */ unsigned long pmc_s:1; /* Shared */ unsigned long pmc_e:1; /* Exclusive */ unsigned long pmc_m:1; /* Modified */ unsigned long pmc_res3:33; /* reserved */ } pmc_mont_counter_reg; /* opcode matchers mask registers */ struct { unsigned long opcm_mask:41; /* opcode mask */ unsigned long opcm_ig1:7; /* ignored */ unsigned long opcm_b:1; /* B-syllable */ unsigned long opcm_f:1; /* F-syllable */ unsigned long opcm_i:1; /* I-syllable */ unsigned long opcm_m:1; /* M-syllable */ unsigned long opcm_ig2:4; /* ignored */ unsigned long opcm_inv:1; /* inverse range for ibrp0 */ unsigned long opcm_ig_ad:1; /* ignore address range restrictions */ unsigned long opcm_ig3:6; /* ignored */ } pmc32_34_mont_reg; /* opcode matchers match registers */ struct { unsigned long opcm_match:41; /* opcode match */ unsigned long opcm_ig1:23; /* ignored */ } pmc33_35_mont_reg; /* opcode matcher config register */ struct { unsigned long opcm_ch0_ig_opcm:1; /* chan0 opcode constraint */ unsigned long opcm_ch1_ig_opcm:1; /* chan1 opcode constraint */ unsigned long opcm_ch2_ig_opcm:1; /* chan2 opcode constraint */ unsigned long opcm_ch3_ig_opcm:1; /* chan3 opcode constraint */ unsigned long opcm_res:28; /* reserved */ unsigned long opcm_ig:32; /* ignored */ } pmc36_mont_reg; /* * instruction event address register configuration (I-EAR) * * The register has two layouts depending on the value of the ct field. * In cache mode(ct=1x): * - ct is 1 bit, umask is 8 bits * In TLB mode (ct=0x): * - ct is 2 bits, umask is 7 bits * ct=11 => cache mode using a latency filter with eighth bit set * ct=01 => nothing monitored * * The ct=01 value is the only reason why we cannot fix the layout * to ct 1 bit and umask 8 bits. Even though in TLB mode, only 6 bits * are effectively used for the umask, if the user inadvertently sets * a umask with the most significant bit set, it would be equivalent * to no monitoring. */ struct { unsigned long iear_plm:4; /* privilege level mask */ unsigned long iear_pm:1; /* privileged monitor */ unsigned long iear_umask:8; /* event unit mask */ unsigned long iear_ct:1; /* =1 for i-cache */ unsigned long iear_res:2; /* reserved */ unsigned long iear_ig:48; /* ignored */ } pmc37_mont_cache_reg; struct { unsigned long iear_plm:4; /* privilege level mask */ unsigned long iear_pm:1; /* privileged monitor */ unsigned long iear_umask:7; /* event unit mask */ unsigned long iear_ct:2; /* 00=i-tlb, 01=nothing 1x=illegal */ unsigned long iear_res:50; /* reserved */ } pmc37_mont_tlb_reg; /* data event address register configuration (D-EAR) */ struct { unsigned long dear_plm:4; /* privilege level mask */ unsigned long dear_ig1:2; /* ignored */ unsigned long dear_pm:1; /* privileged monitor */ unsigned long dear_mode:2; /* mode */ unsigned long dear_ig2:7; /* ignored */ unsigned long dear_umask:4; /* unit mask */ unsigned long dear_ig3:4; /* ignored */ unsigned long dear_ism:2; /* instruction set: must be 2 */ unsigned long dear_ig4:38; /* ignored */ } pmc40_mont_reg; /* IP event address register (IP-EAR) */ struct { unsigned long ipear_plm:4; /* privilege level mask */ unsigned long ipear_ig1:2; /* ignored */ unsigned long ipear_pm:1; /* privileged monitor */ unsigned long ipear_ig2:1; /* ignored */ unsigned long ipear_mode:3; /* mode */ unsigned long ipear_delay:8; /* delay */ unsigned long ipear_ig3:45; /* reserved */ } pmc42_mont_reg; /* execution trace buffer configuration register (ETB) */ struct { unsigned long etbc_plm:4; /* privilege level */ unsigned long etbc_res1:2; /* reserved */ unsigned long etbc_pm:1; /* privileged monitor */ unsigned long etbc_ds:1; /* data selector */ unsigned long etbc_tm:2; /* taken mask */ unsigned long etbc_ptm:2; /* predicted taken address mask */ unsigned long etbc_ppm:2; /* predicted predicate mask */ unsigned long etbc_brt:2; /* branch type mask */ unsigned long etbc_ig:48; /* ignored */ } pmc39_mont_reg; /* data address range configuration register */ struct { unsigned long darc_res1:3; /* reserved */ unsigned long darc_cfg_dtag0:2; /* constraints on dbrp0 */ unsigned long darc_res2:6; /* reserved */ unsigned long darc_cfg_dtag1:2; /* constraints on dbrp1 */ unsigned long darc_res3:6; /* reserved */ unsigned long darc_cfg_dtag2:2; /* constraints on dbrp2 */ unsigned long darc_res4:6; /* reserved */ unsigned long darc_cfg_dtag3:2; /* constraints on dbrp3 */ unsigned long darc_res5:16; /* reserved */ unsigned long darc_ena_dbrp0:1; /* enable constraints dbrp0 */ unsigned long darc_ena_dbrp1:1; /* enable constraints dbrp1 */ unsigned long darc_ena_dbrp2:1; /* enable constraints dbrp2 */ unsigned long darc_ena_dbrp3:1; /* enable constraint dbr3 */ unsigned long darc_res6:15; } pmc41_mont_reg; /* instruction address range configuration register */ struct { unsigned long iarc_res1:1; /* reserved */ unsigned long iarc_ig_ibrp0:1; /* constrained by ibrp0 */ unsigned long iarc_res2:2; /* reserved */ unsigned long iarc_ig_ibrp1:1; /* constrained by ibrp1 */ unsigned long iarc_res3:2; /* reserved */ unsigned long iarc_ig_ibrp2:1; /* constrained by ibrp2 */ unsigned long iarc_res4:2; /* reserved */ unsigned long iarc_ig_ibrp3:1; /* constrained by ibrp3 */ unsigned long iarc_res5:2; /* reserved */ unsigned long iarc_fine:1; /* fine mode */ unsigned long iarc_ig6:50; /* reserved */ } pmc38_mont_reg; } pfm_gen_ia64_pmc_reg_t; typedef struct { unsigned long pmd_val; /* generic counter value */ /* counting pmd register */ struct { unsigned long pmd_count:32; /* 32-bit hardware counter */ unsigned long pmd_sxt32:32; /* sign extension of bit 32 */ } pmd_ita_counter_reg; struct { unsigned long iear_v:1; /* valid bit */ unsigned long iear_tlb:1; /* tlb miss bit */ unsigned long iear_ig1:3; /* reserved */ unsigned long iear_icla:59; /* instruction cache line address {60:51} sxt {50}*/ } pmd0_ita_reg; struct { unsigned long iear_lat:12; /* latency */ unsigned long iear_ig1:52; /* reserved */ } pmd1_ita_reg; struct { unsigned long dear_daddr; /* data address */ } pmd2_ita_reg; struct { unsigned long dear_latency:12; /* latency */ unsigned long dear_ig1:50; /* reserved */ unsigned long dear_level:2; /* level */ } pmd3_ita_reg; struct { unsigned long btb_b:1; /* branch bit */ unsigned long btb_mp:1; /* mispredict bit */ unsigned long btb_slot:2; /* which slot, 3=not taken branch */ unsigned long btb_addr:60; /* b=1, bundle address, b=0 target address */ } pmd8_15_ita_reg; struct { unsigned long btbi_bbi:3; /* branch buffer index */ unsigned long btbi_full:1; /* full bit (sticky) */ unsigned long btbi_ignored:60; } pmd16_ita_reg; struct { unsigned long dear_vl:1; /* valid bit */ unsigned long dear_ig1:1; /* reserved */ unsigned long dear_slot:2; /* slot number */ unsigned long dear_iaddr:60; /* instruction address */ } pmd17_ita_reg; /* counting pmd register */ struct { unsigned long pmd_count:47; /* 47-bit hardware counter */ unsigned long pmd_sxt47:17; /* sign extension of bit 46 */ } pmd_ita2_counter_reg; /* instruction event address register: data address register */ struct { unsigned long iear_stat:2; /* status bit */ unsigned long iear_ig1:3; unsigned long iear_iaddr:59; /* instruction cache line address {60:51} sxt {50}*/ } pmd0_ita2_reg; /* instruction event address register: data address register */ struct { unsigned long iear_latency:12; /* latency */ unsigned long iear_overflow:1; /* latency overflow */ unsigned long iear_ig1:51; /* reserved */ } pmd1_ita2_reg; /* data event address register: data address register */ struct { unsigned long dear_daddr; /* data address */ } pmd2_ita2_reg; /* data event address register: data address register */ struct { unsigned long dear_latency:13; /* latency */ unsigned long dear_overflow:1; /* overflow */ unsigned long dear_stat:2; /* status */ unsigned long dear_ig1:48; /* ignored */ } pmd3_ita2_reg; /* branch trace buffer data register when pmc12.ds == 0 */ struct { unsigned long btb_b:1; /* branch bit */ unsigned long btb_mp:1; /* mispredict bit */ unsigned long btb_slot:2; /* which slot, 3=not taken branch */ unsigned long btb_addr:60; /* bundle address(b=1), target address(b=0) */ } pmd8_15_ita2_reg; /* branch trace buffer data register when pmc12.ds == 1 */ struct { unsigned long btb_b:1; /* branch bit */ unsigned long btb_mp:1; /* mispredict bit */ unsigned long btb_slot:2; /* which slot, 3=not taken branch */ unsigned long btb_loaddr:37; /* b=1, bundle address, b=0 target address */ unsigned long btb_pred:20; /* low 20bits of L1IBR */ unsigned long btb_hiaddr:3; /* hi 3bits of bundle address(b=1) or target address (b=0)*/ } pmd8_15_ds_ita2_reg; /* branch trace buffer index register */ struct { unsigned long btbi_bbi:3; /* next entry index */ unsigned long btbi_full:1; /* full bit (sticky) */ unsigned long btbi_pmd8ext_b1:1; /* pmd8 ext */ unsigned long btbi_pmd8ext_bruflush:1; /* pmd8 ext */ unsigned long btbi_pmd8ext_ig:2; /* pmd8 ext */ unsigned long btbi_pmd9ext_b1:1; /* pmd9 ext */ unsigned long btbi_pmd9ext_bruflush:1; /* pmd9 ext */ unsigned long btbi_pmd9ext_ig:2; /* pmd9 ext */ unsigned long btbi_pmd10ext_b1:1; /* pmd10 ext */ unsigned long btbi_pmd10ext_bruflush:1; /* pmd10 ext */ unsigned long btbi_pmd10ext_ig:2; /* pmd10 ext */ unsigned long btbi_pmd11ext_b1:1; /* pmd11 ext */ unsigned long btbi_pmd11ext_bruflush:1; /* pmd11 ext */ unsigned long btbi_pmd11ext_ig:2; /* pmd11 ext */ unsigned long btbi_pmd12ext_b1:1; /* pmd12 ext */ unsigned long btbi_pmd12ext_bruflush:1; /* pmd12 ext */ unsigned long btbi_pmd12ext_ig:2; /* pmd12 ext */ unsigned long btbi_pmd13ext_b1:1; /* pmd13 ext */ unsigned long btbi_pmd13ext_bruflush:1; /* pmd13 ext */ unsigned long btbi_pmd13ext_ig:2; /* pmd13 ext */ unsigned long btbi_pmd14ext_b1:1; /* pmd14 ext */ unsigned long btbi_pmd14ext_bruflush:1; /* pmd14 ext */ unsigned long btbi_pmd14ext_ig:2; /* pmd14 ext */ unsigned long btbi_pmd15ext_b1:1; /* pmd15 ext */ unsigned long btbi_pmd15ext_bruflush:1; /* pmd15 ext */ unsigned long btbi_pmd15ext_ig:2; /* pmd15 ext */ unsigned long btbi_ignored:28; } pmd16_ita2_reg; /* data event address register: data address register */ struct { unsigned long dear_slot:2; /* slot */ unsigned long dear_bn:1; /* bundle bit (if 1 add 16 to address) */ unsigned long dear_vl:1; /* valid */ unsigned long dear_iaddr:60; /* instruction address (2-bundle window)*/ } pmd17_ita2_reg; struct { unsigned long pmd_count:47; /* 47-bit hardware counter */ unsigned long pmd_sxt47:17; /* sign extension of bit 46 */ } pmd_mont_counter_reg; /* data event address register */ struct { unsigned long dear_daddr; /* data address */ } pmd32_mont_reg; /* data event address register (D-EAR) */ struct { unsigned long dear_latency:13; /* latency */ unsigned long dear_ov:1; /* latency overflow */ unsigned long dear_stat:2; /* status */ unsigned long dear_ig:48; /* ignored */ } pmd33_mont_reg; /* instruction event address register (I-EAR) */ struct { unsigned long iear_stat:2; /* status bit */ unsigned long iear_ig:3; /* ignored */ unsigned long iear_iaddr:59; /* instruction cache line address {60:51} sxt {50}*/ } pmd34_mont_reg; /* instruction event address register (I-EAR) */ struct { unsigned long iear_latency:12; /* latency */ unsigned long iear_ov:1; /* latency overflow */ unsigned long iear_ig:51; /* ignored */ } pmd35_mont_reg; /* data event address register (D-EAR) */ struct { unsigned long dear_slot:2; /* slot */ unsigned long dear_bn:1; /* bundle bit (if 1 add 16 to iaddr) */ unsigned long dear_vl:1; /* valid */ unsigned long dear_iaddr:60; /* instruction address (2-bundle window)*/ } pmd36_mont_reg; /* execution trace buffer index register (ETB) */ struct { unsigned long etbi_ebi:4; /* next entry index */ unsigned long etbi_ig1:1; /* ignored */ unsigned long etbi_full:1; /* ETB overflowed at least once */ unsigned long etbi_ig2:58; /* ignored */ } pmd38_mont_reg; /* execution trace buffer extension register (ETB) */ struct { unsigned long etb_pmd48ext_b1:1; /* pmd48 ext */ unsigned long etb_pmd48ext_bruflush:1; /* pmd48 ext */ unsigned long etb_pmd48ext_res:2; /* reserved */ unsigned long etb_pmd56ext_b1:1; /* pmd56 ext */ unsigned long etb_pmd56ext_bruflush:1; /* pmd56 ext */ unsigned long etb_pmd56ext_res:2; /* reserved */ unsigned long etb_pmd49ext_b1:1; /* pmd49 ext */ unsigned long etb_pmd49ext_bruflush:1; /* pmd49 ext */ unsigned long etb_pmd49ext_res:2; /* reserved */ unsigned long etb_pmd57ext_b1:1; /* pmd57 ext */ unsigned long etb_pmd57ext_bruflush:1; /* pmd57 ext */ unsigned long etb_pmd57ext_res:2; /* reserved */ unsigned long etb_pmd50ext_b1:1; /* pmd50 ext */ unsigned long etb_pmd50ext_bruflush:1; /* pmd50 ext */ unsigned long etb_pmd50ext_res:2; /* reserved */ unsigned long etb_pmd58ext_b1:1; /* pmd58 ext */ unsigned long etb_pmd58ext_bruflush:1; /* pmd58 ext */ unsigned long etb_pmd58ext_res:2; /* reserved */ unsigned long etb_pmd51ext_b1:1; /* pmd51 ext */ unsigned long etb_pmd51ext_bruflush:1; /* pmd51 ext */ unsigned long etb_pmd51ext_res:2; /* reserved */ unsigned long etb_pmd59ext_b1:1; /* pmd59 ext */ unsigned long etb_pmd59ext_bruflush:1; /* pmd59 ext */ unsigned long etb_pmd59ext_res:2; /* reserved */ unsigned long etb_pmd52ext_b1:1; /* pmd52 ext */ unsigned long etb_pmd52ext_bruflush:1; /* pmd52 ext */ unsigned long etb_pmd52ext_res:2; /* reserved */ unsigned long etb_pmd60ext_b1:1; /* pmd60 ext */ unsigned long etb_pmd60ext_bruflush:1; /* pmd60 ext */ unsigned long etb_pmd60ext_res:2; /* reserved */ unsigned long etb_pmd53ext_b1:1; /* pmd53 ext */ unsigned long etb_pmd53ext_bruflush:1; /* pmd53 ext */ unsigned long etb_pmd53ext_res:2; /* reserved */ unsigned long etb_pmd61ext_b1:1; /* pmd61 ext */ unsigned long etb_pmd61ext_bruflush:1; /* pmd61 ext */ unsigned long etb_pmd61ext_res:2; /* reserved */ unsigned long etb_pmd54ext_b1:1; /* pmd54 ext */ unsigned long etb_pmd54ext_bruflush:1; /* pmd54 ext */ unsigned long etb_pmd54ext_res:2; /* reserved */ unsigned long etb_pmd62ext_b1:1; /* pmd62 ext */ unsigned long etb_pmd62ext_bruflush:1; /* pmd62 ext */ unsigned long etb_pmd62ext_res:2; /* reserved */ unsigned long etb_pmd55ext_b1:1; /* pmd55 ext */ unsigned long etb_pmd55ext_bruflush:1; /* pmd55 ext */ unsigned long etb_pmd55ext_res:2; /* reserved */ unsigned long etb_pmd63ext_b1:1; /* pmd63 ext */ unsigned long etb_pmd63ext_bruflush:1; /* pmd63 ext */ unsigned long etb_pmd63ext_res:2; /* reserved */ } pmd39_mont_reg; /* * execution trace buffer extension register when used with IP-EAR * * to be used in conjunction with pmd48_63_ipear_reg (see below) */ struct { unsigned long ipear_pmd48ext_cycles:2; /* pmd48 upper 2 bits of cycles */ unsigned long ipear_pmd48ext_f:1; /* pmd48 flush bit */ unsigned long ipear_pmd48ext_ef:1; /* pmd48 early freeze */ unsigned long ipear_pmd56ext_cycles:2; /* pmd56 upper 2 bits of cycles */ unsigned long ipear_pmd56ext_f:1; /* pmd56 flush bit */ unsigned long ipear_pmd56ext_ef:1; /* pmd56 early freeze */ unsigned long ipear_pmd49ext_cycles:2; /* pmd49 upper 2 bits of cycles */ unsigned long ipear_pmd49ext_f:1; /* pmd49 flush bit */ unsigned long ipear_pmd49ext_ef:1; /* pmd49 early freeze */ unsigned long ipear_pmd57ext_cycles:2; /* pmd57 upper 2 bits of cycles */ unsigned long ipear_pmd57ext_f:1; /* pmd57 flush bit */ unsigned long ipear_pmd57ext_ef:1; /* pmd57 early freeze */ unsigned long ipear_pmd50ext_cycles:2; /* pmd50 upper 2 bits of cycles */ unsigned long ipear_pmd50ext_f:1; /* pmd50 flush bit */ unsigned long ipear_pmd50ext_ef:1; /* pmd50 early freeze */ unsigned long ipear_pmd58ext_cycles:2; /* pmd58 upper 2 bits of cycles */ unsigned long ipear_pmd58ext_f:1; /* pmd58 flush bit */ unsigned long ipear_pmd58ext_ef:1; /* pmd58 early freeze */ unsigned long ipear_pmd51ext_cycles:2; /* pmd51 upper 2 bits of cycles */ unsigned long ipear_pmd51ext_f:1; /* pmd51 flush bit */ unsigned long ipear_pmd51ext_ef:1; /* pmd51 early freeze */ unsigned long ipear_pmd59ext_cycles:2; /* pmd59 upper 2 bits of cycles */ unsigned long ipear_pmd59ext_f:1; /* pmd59 flush bit */ unsigned long ipear_pmd59ext_ef:1; /* pmd59 early freeze */ unsigned long ipear_pmd52ext_cycles:2; /* pmd52 upper 2 bits of cycles */ unsigned long ipear_pmd52ext_f:1; /* pmd52 flush bit */ unsigned long ipear_pmd52ext_ef:1; /* pmd52 early freeze */ unsigned long ipear_pmd60ext_cycles:2; /* pmd60 upper 2 bits of cycles */ unsigned long ipear_pmd60ext_f:1; /* pmd60 flush bit */ unsigned long ipear_pmd60ext_ef:1; /* pmd60 early freeze */ unsigned long ipear_pmd53ext_cycles:2; /* pmd53 upper 2 bits of cycles */ unsigned long ipear_pmd53ext_f:1; /* pmd53 flush bit */ unsigned long ipear_pmd53ext_ef:1; /* pmd53 early freeze */ unsigned long ipear_pmd61ext_cycles:2; /* pmd61 upper 2 bits of cycles */ unsigned long ipear_pmd61ext_f:1; /* pmd61 flush bit */ unsigned long ipear_pmd61ext_ef:1; /* pmd61 early freeze */ unsigned long ipear_pmd54ext_cycles:2; /* pmd54 upper 2 bits of cycles */ unsigned long ipear_pmd54ext_f:1; /* pmd54 flush bit */ unsigned long ipear_pmd54ext_ef:1; /* pmd54 early freeze */ unsigned long ipear_pmd62ext_cycles:2; /* pmd62 upper 2 bits of cycles */ unsigned long ipear_pmd62ext_f:1; /* pmd62 flush bit */ unsigned long ipear_pmd62ext_ef:1; /* pmd62 early freeze */ unsigned long ipear_pmd55ext_cycles:2; /* pmd55 upper 2 bits of cycles */ unsigned long ipear_pmd55ext_f:1; /* pmd55 flush bit */ unsigned long ipear_pmd55ext_ef:1; /* pmd55 early freeze */ unsigned long ipear_pmd63ext_cycles:2; /* pmd63 upper 2 bits of cycles */ unsigned long ipear_pmd63ext_f:1; /* pmd63 flush bit */ unsigned long ipear_pmd63ext_ef:1; /* pmd63 early freeze */ } pmd39_ipear_mont_reg; /* * execution trace buffer data register (ETB) * * when pmc39.ds == 0: pmd48-63 contains branch targets * when pmc39.ds == 1: pmd48-63 content is undefined */ struct { unsigned long etb_s:1; /* source bit */ unsigned long etb_mp:1; /* mispredict bit */ unsigned long etb_slot:2; /* which slot, 3=not taken branch */ unsigned long etb_addr:60; /* bundle address(s=1), target address(s=0) */ } pmd48_63_etb_mont_reg; /* * execution trace buffer when used with IP-EAR with PMD48-63.ef=0 * * The cycles field straddles pmdXX and corresponding extension in * pmd39 (pmd39_ipear_mont_reg). For instance, cycles for pmd48: * * cycles= pmd39_ipear_mont_reg.etb_pmd48ext_cycles << 4 * | pmd48_63_etb_ipear_mont_reg.etb_cycles */ struct { unsigned long ipear_addr:60; /* retired IP[63:4] */ unsigned long ipear_cycles:4; /* lower 4 bit of cycles */ } pmd48_63_ipear_mont_reg; /* * execution trace buffer when used with IP-EAR with PMD48-63.ef=1 * * The cycles field straddles pmdXX and corresponding extension in * pmd39 (pmd39_ipear_mont_reg). For instance, cycles for pmd48: * * cycles= pmd39_ipear_mont_reg.etb_pmd48ext_cycles << 4 * | pmd48_63_etb_ipear_ef_mont_reg.etb_cycles */ struct { unsigned long ipear_delay:8; /* delay count */ unsigned long ipear_addr:52; /* retired IP[61:12] */ unsigned long ipear_cycles:4; /* lower 5 bit of cycles */ } pmd48_63_ipear_ef_mont_reg; } pfm_gen_ia64_pmd_reg_t; #define PFMLIB_ITA2_FL_EVT_NO_QUALCHECK 0x1 /* don't check qualifier constraints */ #define PFMLIB_ITA2_RR_INV 0x1 /* inverse instruction ranges (iranges only) */ #define PFMLIB_ITA2_RR_NO_FINE_MODE 0x2 /* force non fine mode for instruction ranges */ #define PFMLIB_ITA2_EVT_NO_GRP 0 /* event does not belong to a group */ #define PFMLIB_ITA2_EVT_L1_CACHE_GRP 1 /* event belongs to L1 Cache group */ #define PFMLIB_ITA2_EVT_L2_CACHE_GRP 2 /* event belongs to L2 Cache group */ #define PFMLIB_ITA2_EVT_NO_SET -1 /* event does not belong to a set */ /* * counter specific flags */ #define PFMLIB_MONT_FL_EVT_NO_QUALCHECK 0x1 /* don't check qualifier constraints */ #define PFMLIB_MONT_FL_EVT_ALL_THRD 0x2 /* event measured for both threads */ #define PFMLIB_MONT_FL_EVT_ACTIVE_ONLY 0x4 /* measure the event only when the thread is active */ #define PFMLIB_MONT_FL_EVT_ALWAYS 0x8 /* measure the event at all times (active or inactive) */ #define PFMLIB_MONT_RR_INV 0x1 /* inverse instruction ranges (iranges only) */ #define PFMLIB_MONT_RR_NO_FINE_MODE 0x2 /* force non fine mode for instruction ranges */ #define PFMLIB_MONT_IRR_DEMAND_FETCH 0x4 /* demand fetch only for dual events */ #define PFMLIB_MONT_IRR_PREFETCH_MATCH 0x8 /* regular prefetches for dual events */ #define PFMLIB_MONT_EVT_NO_GRP 0 /* event does not belong to a group */ #define PFMLIB_MONT_EVT_L1D_CACHE_GRP 1 /* event belongs to L1D Cache group */ #define PFMLIB_MONT_EVT_L2D_CACHE_GRP 2 /* event belongs to L2D Cache group */ #define PFMLIB_MONT_EVT_NO_SET -1 /* event does not belong to a set */ #define PFMLIB_MONT_EVT_ACTIVE 0 /* event measures only when thread is active */ #define PFMLIB_MONT_EVT_FLOATING 1 #define PFMLIB_MONT_EVT_CAUSAL 2 #define PFMLIB_MONT_EVT_SELF_FLOATING 3 /* floating with .self, causal otherwise */ typedef struct { unsigned long db_mask:56; unsigned long db_plm:4; unsigned long db_ig:2; unsigned long db_w:1; unsigned long db_rx:1; } br_mask_reg_t; typedef union { unsigned long val; br_mask_reg_t db; } dbreg_t; static inline int pfm_ia64_get_cpu_family(void) { return (int)((ia64_get_cpuid(3) >> 24) & 0xff); } static inline int pfm_ia64_get_cpu_model(void) { return (int)((ia64_get_cpuid(3) >> 16) & 0xff); } /* * find last bit set */ static inline int pfm_ia64_fls (unsigned long x) { double d = x; long exp; exp = ia64_getf(d); return exp - 0xffff; } #endif /* __PFMLIB_PRIV_IA64_H__ */ libpfm-4.9.0/lib/pfmlib_amd64.c0000664000175000017500000005317713223402656016011 0ustar eranianeranian/* * pfmlib_amd64.c : support for the AMD64 architected PMU * (for both 64 and 32 bit modes) * * Copyright (c) 2009 Google, Inc * Contributed by Stephane Eranian * * Based on: * Copyright (c) 2005-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include /* private headers */ #include "pfmlib_priv.h" /* library private */ #include "pfmlib_amd64_priv.h" /* architecture private */ const pfmlib_attr_desc_t amd64_mods[]={ PFM_ATTR_B("k", "monitor at priv level 0"), /* monitor priv level 0 */ PFM_ATTR_B("u", "monitor at priv level 1, 2, 3"), /* monitor priv level 1, 2, 3 */ PFM_ATTR_B("e", "edge level"), /* edge */ PFM_ATTR_B("i", "invert"), /* invert */ PFM_ATTR_I("c", "counter-mask in range [0-255]"), /* counter-mask */ PFM_ATTR_B("h", "monitor in hypervisor"), /* monitor in hypervisor*/ PFM_ATTR_B("g", "measure in guest"), /* monitor in guest */ PFM_ATTR_NULL /* end-marker to avoid exporting number of entries */ }; pfmlib_pmu_t amd64_support; pfm_amd64_config_t pfm_amd64_cfg; static int amd64_num_mods(void *this, int idx) { const amd64_entry_t *pe = this_pe(this); unsigned int mask; mask = pe[idx].modmsk; return pfmlib_popcnt(mask); } static inline int amd64_eflag(void *this, int idx, int flag) { const amd64_entry_t *pe = this_pe(this); return !!(pe[idx].flags & flag); } static inline int amd64_uflag(void *this, int idx, int attr, int flag) { const amd64_entry_t *pe = this_pe(this); return !!(pe[idx].umasks[attr].uflags & flag); } static inline int amd64_event_ibsfetch(void *this, int idx) { return amd64_eflag(this, idx, AMD64_FL_IBSFE); } static inline int amd64_event_ibsop(void *this, int idx) { return amd64_eflag(this, idx, AMD64_FL_IBSOP); } static inline int amd64_from_rev(unsigned int flags) { return ((flags) >> 8) & 0xff; } static inline int amd64_till_rev(unsigned int flags) { int till = (((flags)>>16) & 0xff); if (!till) return 0xff; return till; } static void amd64_get_revision(pfm_amd64_config_t *cfg) { pfm_pmu_t rev = PFM_PMU_NONE; if (cfg->family == 6) { cfg->revision = PFM_PMU_AMD64_K7; return; } if (cfg->family == 15) { switch (cfg->model >> 4) { case 0: if (cfg->model == 5 && cfg->stepping < 2) { rev = PFM_PMU_AMD64_K8_REVB; break; } if (cfg->model == 4 && cfg->stepping == 0) { rev = PFM_PMU_AMD64_K8_REVB; break; } rev = PFM_PMU_AMD64_K8_REVC; break; case 1: rev = PFM_PMU_AMD64_K8_REVD; break; case 2: case 3: rev = PFM_PMU_AMD64_K8_REVE; break; case 4: case 5: case 0xc: rev = PFM_PMU_AMD64_K8_REVF; break; case 6: case 7: case 8: rev = PFM_PMU_AMD64_K8_REVG; break; default: rev = PFM_PMU_AMD64_K8_REVB; } } else if (cfg->family == 16) { /* family 10h */ switch (cfg->model) { case 4: case 5: case 6: rev = PFM_PMU_AMD64_FAM10H_SHANGHAI; break; case 8: case 9: rev = PFM_PMU_AMD64_FAM10H_ISTANBUL; break; default: rev = PFM_PMU_AMD64_FAM10H_BARCELONA; } } else if (cfg->family == 17) { /* family 11h */ switch (cfg->model) { default: rev = PFM_PMU_AMD64_FAM11H_TURION; } } else if (cfg->family == 18) { /* family 12h */ switch (cfg->model) { default: rev = PFM_PMU_AMD64_FAM12H_LLANO; } } else if (cfg->family == 20) { /* family 14h */ switch (cfg->model) { default: rev = PFM_PMU_AMD64_FAM14H_BOBCAT; } } else if (cfg->family == 21) { /* family 15h */ rev = PFM_PMU_AMD64_FAM15H_INTERLAGOS; } else if (cfg->family == 23) { /* family 17h */ rev = PFM_PMU_AMD64_FAM17H; } else if (cfg->family == 22) { /* family 16h */ rev = PFM_PMU_AMD64_FAM16H; } cfg->revision = rev; } /* * .byte 0x53 == push ebx. it's universal for 32 and 64 bit * .byte 0x5b == pop ebx. * Some gcc's (4.1.2 on Core2) object to pairing push/pop and ebx in 64 bit mode. * Using the opcode directly avoids this problem. */ static inline void cpuid(unsigned int op, unsigned int *a, unsigned int *b, unsigned int *c, unsigned int *d) { __asm__ __volatile__ (".byte 0x53\n\tcpuid\n\tmovl %%ebx, %%esi\n\t.byte 0x5b" : "=a" (*a), "=S" (*b), "=c" (*c), "=d" (*d) : "a" (op)); } static int amd64_event_valid(void *this, int i) { const amd64_entry_t *pe = this_pe(this); pfmlib_pmu_t *pmu = this; int flags; flags = pe[i].flags; if (pmu->pmu_rev < amd64_from_rev(flags)) return 0; if (pmu->pmu_rev > amd64_till_rev(flags)) return 0; /* no restrictions or matches restrictions */ return 1; } static int amd64_umask_valid(void *this, int i, int attr) { pfmlib_pmu_t *pmu = this; const amd64_entry_t *pe = this_pe(this); int flags; flags = pe[i].umasks[attr].uflags; if (pmu->pmu_rev < amd64_from_rev(flags)) return 0; if (pmu->pmu_rev > amd64_till_rev(flags)) return 0; /* no restrictions or matches restrictions */ return 1; } static unsigned int amd64_num_umasks(void *this, int pidx) { const amd64_entry_t *pe = this_pe(this); unsigned int i, n = 0; /* unit masks + modifiers */ for (i = 0; i < pe[pidx].numasks; i++) if (amd64_umask_valid(this, pidx, i)) n++; return n; } static int amd64_get_umask(void *this, int pidx, int attr_idx) { const amd64_entry_t *pe = this_pe(this); unsigned int i; int n; for (i=0, n = 0; i < pe[pidx].numasks; i++) { if (!amd64_umask_valid(this, pidx, i)) continue; if (n++ == attr_idx) return i; } return -1; } static inline int amd64_attr2mod(void *this, int pidx, int attr_idx) { const amd64_entry_t *pe = this_pe(this); size_t x; int n; n = attr_idx - amd64_num_umasks(this, pidx); pfmlib_for_each_bit(x, pe[pidx].modmsk) { if (n == 0) break; n--; } return x; } void amd64_display_reg(void *this, pfmlib_event_desc_t *e, pfm_amd64_reg_t reg) { pfmlib_pmu_t *pmu = this; if (IS_FAMILY_10H(pmu) || IS_FAMILY_15H(pmu)) __pfm_vbprintf("[0x%"PRIx64" event_sel=0x%x umask=0x%x os=%d usr=%d en=%d int=%d inv=%d edge=%d cnt_mask=%d guest=%d host=%d] %s\n", reg.val, reg.sel_event_mask | (reg.sel_event_mask2 << 8), reg.sel_unit_mask, reg.sel_os, reg.sel_usr, reg.sel_en, reg.sel_int, reg.sel_inv, reg.sel_edge, reg.sel_cnt_mask, reg.sel_guest, reg.sel_host, e->fstr); else __pfm_vbprintf("[0x%"PRIx64" event_sel=0x%x umask=0x%x os=%d usr=%d en=%d int=%d inv=%d edge=%d cnt_mask=%d] %s\n", reg.val, reg.sel_event_mask, reg.sel_unit_mask, reg.sel_os, reg.sel_usr, reg.sel_en, reg.sel_int, reg.sel_inv, reg.sel_edge, reg.sel_cnt_mask, e->fstr); } int pfm_amd64_detect(void *this) { unsigned int a, b, c, d; char buffer[128]; if (pfm_amd64_cfg.family) return PFM_SUCCESS; cpuid(0, &a, &b, &c, &d); strncpy(&buffer[0], (char *)(&b), 4); strncpy(&buffer[4], (char *)(&d), 4); strncpy(&buffer[8], (char *)(&c), 4); buffer[12] = '\0'; if (strcmp(buffer, "AuthenticAMD")) return PFM_ERR_NOTSUPP; cpuid(1, &a, &b, &c, &d); pfm_amd64_cfg.family = (a >> 8) & 0x0000000f; // bits 11 - 8 pfm_amd64_cfg.model = (a >> 4) & 0x0000000f; // Bits 7 - 4 if (pfm_amd64_cfg.family == 0xf) { pfm_amd64_cfg.family += (a >> 20) & 0x000000ff; // Extended family pfm_amd64_cfg.model |= (a >> 12) & 0x000000f0; // Extended model } pfm_amd64_cfg.stepping= a & 0x0000000f; // bits 3 - 0 amd64_get_revision(&pfm_amd64_cfg); if (pfm_amd64_cfg.revision == PFM_PMU_NONE) return PFM_ERR_NOTSUPP; return PFM_SUCCESS; } int pfm_amd64_family_detect(void *this) { struct pfmlib_pmu *pmu = this; int ret; ret = pfm_amd64_detect(this); if (ret != PFM_SUCCESS) return ret; ret = pfm_amd64_cfg.revision; return ret == pmu->cpu_family ? PFM_SUCCESS : PFM_ERR_NOTSUPP; } static int amd64_add_defaults(void *this, pfmlib_event_desc_t *e, unsigned int msk, uint64_t *umask) { const amd64_entry_t *ent, *pe = this_pe(this); unsigned int i; int j, k, added, omit, numasks_grp; int idx; k = e->nattrs; ent = pe+e->event; for(i=0; msk; msk >>=1, i++) { if (!(msk & 0x1)) continue; added = omit = numasks_grp = 0; for (j = 0; j < e->npattrs; j++) { if (e->pattrs[j].ctrl != PFM_ATTR_CTRL_PMU) continue; if (e->pattrs[j].type != PFM_ATTR_UMASK) continue; idx = e->pattrs[j].idx; if (ent->umasks[idx].grpid != i) continue; /* number of umasks in this group */ numasks_grp++; if (amd64_uflag(this, e->event, idx, AMD64_FL_DFL)) { DPRINT("added default for %s j=%d idx=%d\n", ent->umasks[idx].uname, j, idx); *umask |= ent->umasks[idx].ucode; e->attrs[k].id = j; /* pattrs index */ e->attrs[k].ival = 0; k++; added++; } if (amd64_uflag(this, e->event, idx, AMD64_FL_OMIT)) omit++; } /* * fail if no default was found AND at least one umasks cannot be omitted * in the group */ if (!added && omit != numasks_grp) { DPRINT("no default found for event %s unit mask group %d\n", ent->name, i); return PFM_ERR_UMASK; } } e->nattrs = k; return PFM_SUCCESS; } int pfm_amd64_get_encoding(void *this, pfmlib_event_desc_t *e) { const amd64_entry_t *pe = this_pe(this); pfm_amd64_reg_t reg; pfmlib_event_attr_info_t *a; uint64_t umask = 0; unsigned int plmmsk = 0; int k, ret, grpid; unsigned int grpmsk, ugrpmsk = 0; int grpcounts[AMD64_MAX_GRP]; int ncombo[AMD64_MAX_GRP]; memset(grpcounts, 0, sizeof(grpcounts)); memset(ncombo, 0, sizeof(ncombo)); e->fstr[0] = '\0'; reg.val = 0; /* assume reserved bits are zerooed */ grpmsk = (1 << pe[e->event].ngrp)-1; if (amd64_event_ibsfetch(this, e->event)) reg.ibsfetch.en = 1; else if (amd64_event_ibsop(this, e->event)) reg.ibsop.en = 1; else { reg.sel_event_mask = pe[e->event].code; reg.sel_event_mask2 = pe[e->event].code >> 8; reg.sel_en = 1; /* force enable */ reg.sel_int = 1; /* force APIC */ } for(k=0; k < e->nattrs; k++) { a = attr(e, k); if (a->ctrl != PFM_ATTR_CTRL_PMU) continue; if (a->type == PFM_ATTR_UMASK) { grpid = pe[e->event].umasks[a->idx].grpid; ++grpcounts[grpid]; /* * upper layer has removed duplicates * so if we come here more than once, it is for two * diinct umasks */ if (amd64_uflag(this, e->event, a->idx, AMD64_FL_NCOMBO)) ncombo[grpid] = 1; /* * if more than one umask in this group but one is marked * with ncombo, then fail. It is okay to combine umask within * a group as long as none is tagged with NCOMBO */ if (grpcounts[grpid] > 1 && ncombo[grpid]) { DPRINT("event does not support unit mask combination within a group\n"); return PFM_ERR_FEATCOMB; } umask |= pe[e->event].umasks[a->idx].ucode; ugrpmsk |= 1 << pe[e->event].umasks[a->idx].grpid; } else if (a->type == PFM_ATTR_RAW_UMASK) { /* there can only be one RAW_UMASK per event */ /* sanity checks */ if (a->idx & ~0xff) { DPRINT("raw umask is invalid\n"); return PFM_ERR_ATTR; } /* override umask */ umask = a->idx & 0xff; ugrpmsk = grpmsk; } else { /* modifiers */ uint64_t ival = e->attrs[k].ival; switch(a->idx) { //amd64_attr2mod(this, e->osid, e->event, a->idx)) { case AMD64_ATTR_I: /* invert */ reg.sel_inv = !!ival; break; case AMD64_ATTR_E: /* edge */ reg.sel_edge = !!ival; break; case AMD64_ATTR_C: /* counter-mask */ if (ival > 255) return PFM_ERR_ATTR_VAL; reg.sel_cnt_mask = ival; break; case AMD64_ATTR_U: /* USR */ reg.sel_usr = !!ival; plmmsk |= _AMD64_ATTR_U; break; case AMD64_ATTR_K: /* OS */ reg.sel_os = !!ival; plmmsk |= _AMD64_ATTR_K; break; case AMD64_ATTR_G: /* GUEST */ reg.sel_guest = !!ival; plmmsk |= _AMD64_ATTR_G; break; case AMD64_ATTR_H: /* HOST */ reg.sel_host = !!ival; plmmsk |= _AMD64_ATTR_H; break; } } } /* * handle case where no priv level mask was passed. * then we use the dfl_plm */ if (!(plmmsk & (_AMD64_ATTR_K|_AMD64_ATTR_U|_AMD64_ATTR_H))) { if (e->dfl_plm & PFM_PLM0) reg.sel_os = 1; if (e->dfl_plm & PFM_PLM3) reg.sel_usr = 1; if ((IS_FAMILY_10H(this) || IS_FAMILY_15H(this)) && e->dfl_plm & PFM_PLMH) reg.sel_host = 1; } /* * check that there is at least of unit mask in each unit * mask group */ if (ugrpmsk != grpmsk) { ugrpmsk ^= grpmsk; ret = amd64_add_defaults(this, e, ugrpmsk, &umask); if (ret != PFM_SUCCESS) return ret; } reg.sel_unit_mask = umask; e->codes[0] = reg.val; e->count = 1; /* * reorder all the attributes such that the fstr appears always * the same regardless of how the attributes were submitted. */ evt_strcat(e->fstr, "%s", pe[e->event].name); pfmlib_sort_attr(e); for (k = 0; k < e->nattrs; k++) { a = attr(e, k); if (a->ctrl != PFM_ATTR_CTRL_PMU) continue; if (a->type == PFM_ATTR_UMASK) evt_strcat(e->fstr, ":%s", pe[e->event].umasks[a->idx].uname); else if (a->type == PFM_ATTR_RAW_UMASK) evt_strcat(e->fstr, ":0x%x", a->idx); } for (k = 0; k < e->npattrs; k++) { int idx; if (e->pattrs[k].ctrl != PFM_ATTR_CTRL_PMU) continue; if (e->pattrs[k].type == PFM_ATTR_UMASK) continue; idx = e->pattrs[k].idx; switch(idx) { case AMD64_ATTR_K: evt_strcat(e->fstr, ":%s=%lu", amd64_mods[idx].name, reg.sel_os); break; case AMD64_ATTR_U: evt_strcat(e->fstr, ":%s=%lu", amd64_mods[idx].name, reg.sel_usr); break; case AMD64_ATTR_E: evt_strcat(e->fstr, ":%s=%lu", amd64_mods[idx].name, reg.sel_edge); break; case AMD64_ATTR_I: evt_strcat(e->fstr, ":%s=%lu", amd64_mods[idx].name, reg.sel_inv); break; case AMD64_ATTR_C: evt_strcat(e->fstr, ":%s=%lu", amd64_mods[idx].name, reg.sel_cnt_mask); break; case AMD64_ATTR_H: evt_strcat(e->fstr, ":%s=%lu", amd64_mods[idx].name, reg.sel_host); break; case AMD64_ATTR_G: evt_strcat(e->fstr, ":%s=%lu", amd64_mods[idx].name, reg.sel_guest); break; } } amd64_display_reg(this, e, reg); return PFM_SUCCESS; } int pfm_amd64_get_event_first(void *this) { pfmlib_pmu_t *pmu = this; int idx; for(idx=0; idx < pmu->pme_count; idx++) if (amd64_event_valid(this, idx)) return idx; return -1; } int pfm_amd64_get_event_next(void *this, int idx) { pfmlib_pmu_t *pmu = this; /* basic validity checks on idx down by caller */ if (idx >= (pmu->pme_count-1)) return -1; /* validate event fo this host PMU */ if (!amd64_event_valid(this, idx)) return -1; for(++idx; idx < pmu->pme_count; idx++) { if (amd64_event_valid(this, idx)) return idx; } return -1; } int pfm_amd64_event_is_valid(void *this, int pidx) { pfmlib_pmu_t *pmu = this; if (pidx < 0 || pidx >= pmu->pme_count) return 0; /* valid revision */ return amd64_event_valid(this, pidx); } int pfm_amd64_get_event_attr_info(void *this, int pidx, int attr_idx, pfmlib_event_attr_info_t *info) { const amd64_entry_t *pe = this_pe(this); int numasks, idx; numasks = amd64_num_umasks(this, pidx); if (attr_idx < numasks) { idx = amd64_get_umask(this, pidx, attr_idx); if (idx == -1) return PFM_ERR_ATTR; info->name = pe[pidx].umasks[idx].uname; info->desc = pe[pidx].umasks[idx].udesc; info->code = pe[pidx].umasks[idx].ucode; info->type = PFM_ATTR_UMASK; info->is_dfl = amd64_uflag(this, pidx, idx, AMD64_FL_DFL); } else { idx = amd64_attr2mod(this, pidx, attr_idx); info->name = amd64_mods[idx].name; info->desc = amd64_mods[idx].desc; info->type = amd64_mods[idx].type; info->code = idx; info->is_dfl = 0; } info->is_precise = 0; info->equiv = NULL; info->ctrl = PFM_ATTR_CTRL_PMU; info->idx = idx; /* namespace specific index */ info->dfl_val64 = 0; return PFM_SUCCESS; } int pfm_amd64_get_event_info(void *this, int idx, pfm_event_info_t *info) { pfmlib_pmu_t *pmu = this; const amd64_entry_t *pe = this_pe(this); info->name = pe[idx].name; info->desc = pe[idx].desc; info->equiv = NULL; info->code = pe[idx].code; info->idx = idx; info->pmu = pmu->pmu; info->is_precise = 0; info->nattrs = amd64_num_umasks(this, idx); info->nattrs += amd64_num_mods(this, idx); return PFM_SUCCESS; } int pfm_amd64_validate_table(void *this, FILE *fp) { pfmlib_pmu_t *pmu = this; const amd64_entry_t *pe = this_pe(this); const char *name = pmu->name; unsigned int j, k; int i, ndfl; int error = 0; if (!pmu->atdesc) { fprintf(fp, "pmu: %s missing attr_desc\n", pmu->name); error++; } if (!pmu->supported_plm && pmu->type == PFM_PMU_TYPE_CORE) { fprintf(fp, "pmu: %s supported_plm not set\n", pmu->name); error++; } for(i=0; i < pmu->pme_count; i++) { if (!pe[i].name) { fprintf(fp, "pmu: %s event%d: :: no name (prev event was %s)\n", pmu->name, i, i > 1 ? pe[i-1].name : "??"); error++; } if (!pe[i].desc) { fprintf(fp, "pmu: %s event%d: %s :: no description\n", name, i, pe[i].name); error++; } if (pe[i].numasks && pe[i].umasks == NULL) { fprintf(fp, "pmu: %s event%d: %s :: numasks but no umasks\n", pmu->name, i, pe[i].name); error++; } if (pe[i].numasks == 0 && pe[i].umasks) { fprintf(fp, "pmu: %s event%d: %s :: numasks=0 but umasks defined\n", pmu->name, i, pe[i].name); error++; } if (pe[i].numasks && pe[i].ngrp == 0) { fprintf(fp, "pmu: %s event%d: %s :: ngrp cannot be zero\n", name, i, pe[i].name); error++; } if (pe[i].numasks == 0 && pe[i].ngrp) { fprintf(fp, "pmu: %s event%d: %s :: ngrp must be zero\n", name, i, pe[i].name); error++; } if (pe[i].ngrp >= AMD64_MAX_GRP) { fprintf(fp, "pmu: %s event%d: %s :: ngrp too big (max=%d)\n", name, i, pe[i].name, AMD64_MAX_GRP); error++; } for(ndfl = 0, j= 0; j < pe[i].numasks; j++) { if (!pe[i].umasks[j].uname) { fprintf(fp, "pmu: %s event%d: %s umask%d :: no name\n", pmu->name, i, pe[i].name, j); error++; } if (!pe[i].umasks[j].udesc) { fprintf(fp, "pmu: %s event%d:%s umask%d: %s :: no description\n", name, i, pe[i].name, j, pe[i].umasks[j].uname); error++; } if (pe[i].ngrp && pe[i].umasks[j].grpid >= pe[i].ngrp) { fprintf(fp, "pmu: %s event%d: %s umask%d: %s :: invalid grpid %d (must be < %d)\n", name, i, pe[i].name, j, pe[i].umasks[j].uname, pe[i].umasks[j].grpid, pe[i].ngrp); error++; } if (pe[i].umasks[j].uflags & AMD64_FL_DFL) { for(k=0; k < j; k++) if ((pe[i].umasks[k].uflags == pe[i].umasks[j].uflags) && (pe[i].umasks[k].grpid == pe[i].umasks[j].grpid)) ndfl++; if (pe[i].numasks == 1) ndfl = 1; } } if (pe[i].numasks > 1 && ndfl) { fprintf(fp, "pmu: %s event%d: %s :: more than one default unit mask with same code\n", name, i, pe[i].name); error++; } /* if only one umask, then ought to be default */ if (pe[i].numasks == 1 && ndfl != 1) { fprintf(fp, "pmu: %s event%d: %s, only one umask but no default\n", pmu->name, i, pe[i].name); error++; } if (pe[i].flags & AMD64_FL_NCOMBO) { fprintf(fp, "pmu: %s event%d: %s :: NCOMBO is unit mask only flag\n", name, i, pe[i].name); error++; } for(j=0; j < pe[i].numasks; j++) { if (pe[i].umasks[j].uflags & AMD64_FL_NCOMBO) continue; for(k=j+1; k < pe[i].numasks; k++) { if (pe[i].umasks[k].uflags & AMD64_FL_NCOMBO) continue; if ((pe[i].umasks[j].ucode & pe[i].umasks[k].ucode)) { fprintf(fp, "pmu: %s event%d: %s :: umask %s and %s have overlapping code bits\n", name, i, pe[i].name, pe[i].umasks[j].uname, pe[i].umasks[k].uname); error++; } } } } return error ? PFM_ERR_INVAL : PFM_SUCCESS; } unsigned int pfm_amd64_get_event_nattrs(void *this, int pidx) { unsigned int nattrs; nattrs = amd64_num_umasks(this, pidx); nattrs += amd64_num_mods(this, pidx); return nattrs; } int pfm_amd64_get_num_events(void *this) { pfmlib_pmu_t *pmu = this; int i, num = 0; /* * count actual number of events for specific PMU. * Table may contain more events for the family than * what a specific model actually supports. */ for (i = 0; i < pmu->pme_count; i++) if (amd64_event_valid(this, i)) num++; return num; } libpfm-4.9.0/lib/pfmlib_priv.h0000664000175000017500000006070313223402656016054 0ustar eranianeranian/* * Copyright (c) 2002-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. */ #ifndef __PFMLIB_PRIV_H__ #define __PFMLIB_PRIV_H__ #include #include #define PFM_PLM_ALL (PFM_PLM0|PFM_PLM1|PFM_PLM2|PFM_PLM3|PFM_PLMH) #define PFMLIB_ATTR_DELIM ":." /* event attribute delimiter possible */ #define PFMLIB_PMU_DELIM "::" /* pmu to event delimiter */ #define PFMLIB_EVENT_DELIM ", \t\n"/* event to event delimiters */ #define PFM_ATTR_I(y, d) { .name = (y), .type = PFM_ATTR_MOD_INTEGER, .desc = (d) } #define PFM_ATTR_B(y, d) { .name = (y), .type = PFM_ATTR_MOD_BOOL, .desc = (d) } #define PFM_ATTR_SKIP { .name = "" } /* entry not populated (skipped) */ #define PFM_ATTR_NULL { .name = NULL } #define PFMLIB_EVT_MAX_NAME_LEN 256 /* * event identifier encoding: * bit 00-20 : event table specific index (2097152 possibilities) * bit 21-30 : PMU identifier (1024 possibilities) * bit 31 : reserved (to distinguish from a negative error code) */ #define PFMLIB_PMU_SHIFT 21 #define PFMLIB_PMU_MASK 0x3ff /* must fit PFM_PMU_MAX */ #define PFMLIB_PMU_PIDX_MASK ((1<< PFMLIB_PMU_SHIFT)-1) typedef struct { const char *name; /* name */ const char *desc; /* description */ pfm_attr_t type; /* used to validate value (if any) */ } pfmlib_attr_desc_t; typedef struct { const char *name; /* attribute symbolic name */ const char *desc; /* attribute description */ const char *equiv; /* attribute is equivalent to */ size_t size; /* struct sizeof */ uint64_t code; /* attribute code */ pfm_attr_t type; /* attribute type */ pfm_attr_ctrl_t ctrl; /* what is providing attr */ uint64_t idx; /* attribute opaque index */ struct { unsigned int is_dfl:1; /* is default umask */ unsigned int is_precise:1; /* Intel X86: supports PEBS */ unsigned int reserved_bits:30; }; union { uint64_t dfl_val64; /* default 64-bit value */ const char *dfl_str; /* default string value */ int dfl_bool; /* default boolean value */ int dfl_int; /* default integer value */ }; } pfmlib_event_attr_info_t; /* * attribute description passed to model-specific layer */ typedef struct { int id; /* attribute index */ union { uint64_t ival; /* integer value (incl. bool) */ char *sval; /* string */ }; } pfmlib_attr_t; /* * must be big enough to hold all possible priv level attributes */ #define PFMLIB_MAX_ATTRS 64 /* max attributes per event desc */ #define PFMLIB_MAX_ENCODING 4 /* max encoding length */ /* * we add one entry to hold any raw umask users may specify * the last entry in pattrs[] hold that raw umask info */ #define PFMLIB_MAX_PATTRS (PFMLIB_MAX_ATTRS+1) struct pfmlib_pmu; typedef struct { struct pfmlib_pmu *pmu; /* pmu */ int dfl_plm; /* default priv level mask */ int event; /* pidx */ int npattrs; /* number of attrs in pattrs[] */ int nattrs; /* number of attrs in attrs[] */ pfm_os_t osid; /* OS API requested */ int count; /* number of entries in codes[] */ pfmlib_attr_t attrs[PFMLIB_MAX_ATTRS]; /* list of requested attributes */ pfmlib_event_attr_info_t *pattrs; /* list of possible attributes */ char fstr[PFMLIB_EVT_MAX_NAME_LEN]; /* fully qualified event string */ uint64_t codes[PFMLIB_MAX_ENCODING]; /* event encoding */ void *os_data; } pfmlib_event_desc_t; #define modx(atdesc, a, z) (atdesc[(a)].z) #define attr(e, k) ((e)->pattrs + (e)->attrs[k].id) typedef struct pfmlib_pmu { const char *desc; /* PMU description */ const char *name; /* pmu short name */ const char *perf_name; /* perf_event pmu name (optional) */ pfm_pmu_t pmu; /* PMU model */ int pme_count; /* number of events */ int max_encoding; /* max number of uint64_t to encode an event */ int flags; /* 16 LSB: common, 16 MSB: arch spec*/ int pmu_rev; /* PMU model specific revision */ int num_cntrs; /* number of generic counters */ int num_fixed_cntrs; /* number of fixed counters */ int supported_plm; /* supported priv levels */ pfm_pmu_type_t type; /* PMU type */ const void *pe; /* pointer to event table */ const pfmlib_attr_desc_t *atdesc; /* pointer to attrs table */ const int cpu_family; /* cpu family number for detection */ const int *cpu_models; /* cpu model numbers for detection (zero terminated) */ int (*pmu_detect)(void *this); int (*pmu_init)(void *this); /* optional */ void (*pmu_terminate)(void *this); /* optional */ int (*get_event_first)(void *this); int (*get_event_next)(void *this, int pidx); int (*get_event_info)(void *this, int pidx, pfm_event_info_t *info); unsigned int (*get_event_nattrs)(void *this, int pidx); int (*event_is_valid)(void *this, int pidx); int (*can_auto_encode)(void *this, int pidx, int uidx); int (*get_event_attr_info)(void *this, int pidx, int umask_idx, pfmlib_event_attr_info_t *info); int (*get_event_encoding[PFM_OS_MAX])(void *this, pfmlib_event_desc_t *e); void (*validate_pattrs[PFM_OS_MAX])(void *this, pfmlib_event_desc_t *e); int (*os_detect[PFM_OS_MAX])(void *this); int (*validate_table)(void *this, FILE *fp); /* * optional callbacks */ int (*get_num_events)(void *this); void (*display_reg)(void *this, pfmlib_event_desc_t *e, void *val); int (*match_event)(void *this, pfmlib_event_desc_t *d, const char *e, const char *s); } pfmlib_pmu_t; typedef struct { const char *name; const pfmlib_attr_desc_t *atdesc; pfm_os_t id; int flags; int (*detect)(void *this); int (*get_os_attr_info)(void *this, pfmlib_event_desc_t *e); int (*get_os_nattrs)(void *this, pfmlib_event_desc_t *e); int (*encode)(void *this, const char *str, int dfl_plm, void *args); } pfmlib_os_t; #define PFMLIB_OS_FL_ACTIVATED 0x1 /* OS layer detected */ /* * pfmlib_pmu_t common flags (LSB 16 bits) */ #define PFMLIB_PMU_FL_INIT 0x1 /* PMU initialized correctly */ #define PFMLIB_PMU_FL_ACTIVE 0x2 /* PMU is initialized + detected on host */ #define PFMLIB_PMU_FL_RAW_UMASK 0x4 /* PMU supports PFM_ATTR_RAW_UMASKS */ #define PFMLIB_PMU_FL_ARCH_DFL 0x8 /* PMU is arch default */ #define PFMLIB_PMU_FL_NO_SMPL 0x10 /* PMU does not support sampling */ typedef struct { int initdone; int initret; /* initial return value from pfm_initialize() */ int verbose; int debug; int inactive; char *forced_pmu; char *blacklist_pmus; FILE *fp; /* verbose and debug file descriptor, default stderr or PFMLIB_DEBUG_STDOUT */ } pfmlib_config_t; #define PFMLIB_INITIALIZED() (pfm_cfg.initdone && pfm_cfg.initret == PFM_SUCCESS) extern pfmlib_config_t pfm_cfg; extern void __pfm_vbprintf(const char *fmt,...); extern void __pfm_dbprintf(const char *fmt,...); extern void pfmlib_strconcat(char *str, size_t max, const char *fmt, ...); extern int pfmlib_getl(char **buffer, size_t *len, FILE *fp); extern void pfmlib_compact_pattrs(pfmlib_event_desc_t *e, int i); #define evt_strcat(str, fmt, a...) pfmlib_strconcat(str, PFMLIB_EVT_MAX_NAME_LEN, fmt, a) extern int pfmlib_parse_event(const char *event, pfmlib_event_desc_t *d); extern int pfmlib_build_fstr(pfmlib_event_desc_t *e, char **fstr); extern void pfmlib_sort_attr(pfmlib_event_desc_t *e); extern pfmlib_pmu_t * pfmlib_get_pmu_by_type(pfm_pmu_type_t t); extern void pfmlib_release_event(pfmlib_event_desc_t *e); extern size_t pfmlib_check_struct(void *st, size_t usz, size_t refsz, size_t sz); #ifdef CONFIG_PFMLIB_DEBUG #define DPRINT(fmt, a...) \ do { \ __pfm_dbprintf("%s (%s.%d): " fmt, __FILE__, __func__, __LINE__, ## a); \ } while (0) #else #define DPRINT(fmt, a...) #endif extern pfmlib_pmu_t montecito_support; extern pfmlib_pmu_t itanium2_support; extern pfmlib_pmu_t itanium_support; extern pfmlib_pmu_t generic_ia64_support; extern pfmlib_pmu_t amd64_k7_support; extern pfmlib_pmu_t amd64_k8_revb_support; extern pfmlib_pmu_t amd64_k8_revc_support; extern pfmlib_pmu_t amd64_k8_revd_support; extern pfmlib_pmu_t amd64_k8_reve_support; extern pfmlib_pmu_t amd64_k8_revf_support; extern pfmlib_pmu_t amd64_k8_revg_support; extern pfmlib_pmu_t amd64_fam10h_barcelona_support; extern pfmlib_pmu_t amd64_fam10h_shanghai_support; extern pfmlib_pmu_t amd64_fam10h_istanbul_support; extern pfmlib_pmu_t amd64_fam11h_turion_support; extern pfmlib_pmu_t amd64_fam12h_llano_support; extern pfmlib_pmu_t amd64_fam14h_bobcat_support; extern pfmlib_pmu_t amd64_fam15h_interlagos_support; extern pfmlib_pmu_t amd64_fam15h_nb_support; extern pfmlib_pmu_t amd64_fam16h_support; extern pfmlib_pmu_t amd64_fam17h_support; extern pfmlib_pmu_t intel_p6_support; extern pfmlib_pmu_t intel_ppro_support; extern pfmlib_pmu_t intel_pii_support; extern pfmlib_pmu_t intel_pm_support; extern pfmlib_pmu_t sicortex_support; extern pfmlib_pmu_t netburst_support; extern pfmlib_pmu_t netburst_p_support; extern pfmlib_pmu_t intel_coreduo_support; extern pfmlib_pmu_t intel_core_support; extern pfmlib_pmu_t intel_x86_arch_support; extern pfmlib_pmu_t intel_atom_support; extern pfmlib_pmu_t intel_nhm_support; extern pfmlib_pmu_t intel_nhm_ex_support; extern pfmlib_pmu_t intel_nhm_unc_support; extern pfmlib_pmu_t intel_snb_support; extern pfmlib_pmu_t intel_snb_unc_cbo0_support; extern pfmlib_pmu_t intel_snb_unc_cbo1_support; extern pfmlib_pmu_t intel_snb_unc_cbo2_support; extern pfmlib_pmu_t intel_snb_unc_cbo3_support; extern pfmlib_pmu_t intel_snb_ep_support; extern pfmlib_pmu_t intel_ivb_support; extern pfmlib_pmu_t intel_ivb_unc_cbo0_support; extern pfmlib_pmu_t intel_ivb_unc_cbo1_support; extern pfmlib_pmu_t intel_ivb_unc_cbo2_support; extern pfmlib_pmu_t intel_ivb_unc_cbo3_support; extern pfmlib_pmu_t intel_ivb_ep_support; extern pfmlib_pmu_t intel_hsw_support; extern pfmlib_pmu_t intel_hsw_ep_support; extern pfmlib_pmu_t intel_bdw_support; extern pfmlib_pmu_t intel_bdw_ep_support; extern pfmlib_pmu_t intel_skl_support; extern pfmlib_pmu_t intel_skx_support; extern pfmlib_pmu_t intel_rapl_support; extern pfmlib_pmu_t intel_snbep_unc_cb0_support; extern pfmlib_pmu_t intel_snbep_unc_cb1_support; extern pfmlib_pmu_t intel_snbep_unc_cb2_support; extern pfmlib_pmu_t intel_snbep_unc_cb3_support; extern pfmlib_pmu_t intel_snbep_unc_cb4_support; extern pfmlib_pmu_t intel_snbep_unc_cb5_support; extern pfmlib_pmu_t intel_snbep_unc_cb6_support; extern pfmlib_pmu_t intel_snbep_unc_cb7_support; extern pfmlib_pmu_t intel_snbep_unc_ha_support; extern pfmlib_pmu_t intel_snbep_unc_imc0_support; extern pfmlib_pmu_t intel_snbep_unc_imc1_support; extern pfmlib_pmu_t intel_snbep_unc_imc2_support; extern pfmlib_pmu_t intel_snbep_unc_imc3_support; extern pfmlib_pmu_t intel_snbep_unc_pcu_support; extern pfmlib_pmu_t intel_snbep_unc_qpi0_support; extern pfmlib_pmu_t intel_snbep_unc_qpi1_support; extern pfmlib_pmu_t intel_snbep_unc_ubo_support; extern pfmlib_pmu_t intel_snbep_unc_r2pcie_support; extern pfmlib_pmu_t intel_snbep_unc_r3qpi0_support; extern pfmlib_pmu_t intel_snbep_unc_r3qpi1_support; extern pfmlib_pmu_t intel_ivbep_unc_cb0_support; extern pfmlib_pmu_t intel_ivbep_unc_cb1_support; extern pfmlib_pmu_t intel_ivbep_unc_cb2_support; extern pfmlib_pmu_t intel_ivbep_unc_cb3_support; extern pfmlib_pmu_t intel_ivbep_unc_cb4_support; extern pfmlib_pmu_t intel_ivbep_unc_cb5_support; extern pfmlib_pmu_t intel_ivbep_unc_cb6_support; extern pfmlib_pmu_t intel_ivbep_unc_cb7_support; extern pfmlib_pmu_t intel_ivbep_unc_cb8_support; extern pfmlib_pmu_t intel_ivbep_unc_cb9_support; extern pfmlib_pmu_t intel_ivbep_unc_cb10_support; extern pfmlib_pmu_t intel_ivbep_unc_cb11_support; extern pfmlib_pmu_t intel_ivbep_unc_cb12_support; extern pfmlib_pmu_t intel_ivbep_unc_cb13_support; extern pfmlib_pmu_t intel_ivbep_unc_cb14_support; extern pfmlib_pmu_t intel_ivbep_unc_ha0_support; extern pfmlib_pmu_t intel_ivbep_unc_ha1_support; extern pfmlib_pmu_t intel_ivbep_unc_imc0_support; extern pfmlib_pmu_t intel_ivbep_unc_imc1_support; extern pfmlib_pmu_t intel_ivbep_unc_imc2_support; extern pfmlib_pmu_t intel_ivbep_unc_imc3_support; extern pfmlib_pmu_t intel_ivbep_unc_imc4_support; extern pfmlib_pmu_t intel_ivbep_unc_imc5_support; extern pfmlib_pmu_t intel_ivbep_unc_imc6_support; extern pfmlib_pmu_t intel_ivbep_unc_imc7_support; extern pfmlib_pmu_t intel_ivbep_unc_pcu_support; extern pfmlib_pmu_t intel_ivbep_unc_qpi0_support; extern pfmlib_pmu_t intel_ivbep_unc_qpi1_support; extern pfmlib_pmu_t intel_ivbep_unc_qpi2_support; extern pfmlib_pmu_t intel_ivbep_unc_ubo_support; extern pfmlib_pmu_t intel_ivbep_unc_r2pcie_support; extern pfmlib_pmu_t intel_ivbep_unc_r3qpi0_support; extern pfmlib_pmu_t intel_ivbep_unc_r3qpi1_support; extern pfmlib_pmu_t intel_ivbep_unc_r3qpi2_support; extern pfmlib_pmu_t intel_ivbep_unc_irp_support; extern pfmlib_pmu_t intel_hswep_unc_cb0_support; extern pfmlib_pmu_t intel_hswep_unc_cb1_support; extern pfmlib_pmu_t intel_hswep_unc_cb2_support; extern pfmlib_pmu_t intel_hswep_unc_cb3_support; extern pfmlib_pmu_t intel_hswep_unc_cb4_support; extern pfmlib_pmu_t intel_hswep_unc_cb5_support; extern pfmlib_pmu_t intel_hswep_unc_cb6_support; extern pfmlib_pmu_t intel_hswep_unc_cb7_support; extern pfmlib_pmu_t intel_hswep_unc_cb8_support; extern pfmlib_pmu_t intel_hswep_unc_cb9_support; extern pfmlib_pmu_t intel_hswep_unc_cb10_support; extern pfmlib_pmu_t intel_hswep_unc_cb11_support; extern pfmlib_pmu_t intel_hswep_unc_cb12_support; extern pfmlib_pmu_t intel_hswep_unc_cb13_support; extern pfmlib_pmu_t intel_hswep_unc_cb14_support; extern pfmlib_pmu_t intel_hswep_unc_cb15_support; extern pfmlib_pmu_t intel_hswep_unc_cb16_support; extern pfmlib_pmu_t intel_hswep_unc_cb17_support; extern pfmlib_pmu_t intel_hswep_unc_ha0_support; extern pfmlib_pmu_t intel_hswep_unc_ha1_support; extern pfmlib_pmu_t intel_hswep_unc_imc0_support; extern pfmlib_pmu_t intel_hswep_unc_imc1_support; extern pfmlib_pmu_t intel_hswep_unc_imc2_support; extern pfmlib_pmu_t intel_hswep_unc_imc3_support; extern pfmlib_pmu_t intel_hswep_unc_imc4_support; extern pfmlib_pmu_t intel_hswep_unc_imc5_support; extern pfmlib_pmu_t intel_hswep_unc_imc6_support; extern pfmlib_pmu_t intel_hswep_unc_imc7_support; extern pfmlib_pmu_t intel_hswep_unc_pcu_support; extern pfmlib_pmu_t intel_hswep_unc_qpi0_support; extern pfmlib_pmu_t intel_hswep_unc_qpi1_support; extern pfmlib_pmu_t intel_hswep_unc_sb0_support; extern pfmlib_pmu_t intel_hswep_unc_sb1_support; extern pfmlib_pmu_t intel_hswep_unc_sb2_support; extern pfmlib_pmu_t intel_hswep_unc_sb3_support; extern pfmlib_pmu_t intel_hswep_unc_ubo_support; extern pfmlib_pmu_t intel_hswep_unc_r2pcie_support; extern pfmlib_pmu_t intel_hswep_unc_r3qpi0_support; extern pfmlib_pmu_t intel_hswep_unc_r3qpi1_support; extern pfmlib_pmu_t intel_hswep_unc_r3qpi2_support; extern pfmlib_pmu_t intel_hswep_unc_irp_support; extern pfmlib_pmu_t intel_knc_support; extern pfmlib_pmu_t intel_slm_support; extern pfmlib_pmu_t intel_knl_support; extern pfmlib_pmu_t intel_knl_unc_imc0_support; extern pfmlib_pmu_t intel_knl_unc_imc1_support; extern pfmlib_pmu_t intel_knl_unc_imc2_support; extern pfmlib_pmu_t intel_knl_unc_imc3_support; extern pfmlib_pmu_t intel_knl_unc_imc4_support; extern pfmlib_pmu_t intel_knl_unc_imc5_support; extern pfmlib_pmu_t intel_knl_unc_imc_uclk0_support; extern pfmlib_pmu_t intel_knl_unc_imc_uclk1_support; extern pfmlib_pmu_t intel_knl_unc_edc_uclk0_support; extern pfmlib_pmu_t intel_knl_unc_edc_uclk1_support; extern pfmlib_pmu_t intel_knl_unc_edc_uclk2_support; extern pfmlib_pmu_t intel_knl_unc_edc_uclk3_support; extern pfmlib_pmu_t intel_knl_unc_edc_uclk4_support; extern pfmlib_pmu_t intel_knl_unc_edc_uclk5_support; extern pfmlib_pmu_t intel_knl_unc_edc_uclk6_support; extern pfmlib_pmu_t intel_knl_unc_edc_uclk7_support; extern pfmlib_pmu_t intel_knl_unc_edc_eclk0_support; extern pfmlib_pmu_t intel_knl_unc_edc_eclk1_support; extern pfmlib_pmu_t intel_knl_unc_edc_eclk2_support; extern pfmlib_pmu_t intel_knl_unc_edc_eclk3_support; extern pfmlib_pmu_t intel_knl_unc_edc_eclk4_support; extern pfmlib_pmu_t intel_knl_unc_edc_eclk5_support; extern pfmlib_pmu_t intel_knl_unc_edc_eclk6_support; extern pfmlib_pmu_t intel_knl_unc_edc_eclk7_support; extern pfmlib_pmu_t intel_knl_unc_cha0_support; extern pfmlib_pmu_t intel_knl_unc_cha1_support; extern pfmlib_pmu_t intel_knl_unc_cha2_support; extern pfmlib_pmu_t intel_knl_unc_cha3_support; extern pfmlib_pmu_t intel_knl_unc_cha4_support; extern pfmlib_pmu_t intel_knl_unc_cha5_support; extern pfmlib_pmu_t intel_knl_unc_cha6_support; extern pfmlib_pmu_t intel_knl_unc_cha7_support; extern pfmlib_pmu_t intel_knl_unc_cha8_support; extern pfmlib_pmu_t intel_knl_unc_cha9_support; extern pfmlib_pmu_t intel_knl_unc_cha10_support; extern pfmlib_pmu_t intel_knl_unc_cha11_support; extern pfmlib_pmu_t intel_knl_unc_cha12_support; extern pfmlib_pmu_t intel_knl_unc_cha13_support; extern pfmlib_pmu_t intel_knl_unc_cha14_support; extern pfmlib_pmu_t intel_knl_unc_cha15_support; extern pfmlib_pmu_t intel_knl_unc_cha16_support; extern pfmlib_pmu_t intel_knl_unc_cha17_support; extern pfmlib_pmu_t intel_knl_unc_cha18_support; extern pfmlib_pmu_t intel_knl_unc_cha19_support; extern pfmlib_pmu_t intel_knl_unc_cha20_support; extern pfmlib_pmu_t intel_knl_unc_cha21_support; extern pfmlib_pmu_t intel_knl_unc_cha22_support; extern pfmlib_pmu_t intel_knl_unc_cha23_support; extern pfmlib_pmu_t intel_knl_unc_cha24_support; extern pfmlib_pmu_t intel_knl_unc_cha25_support; extern pfmlib_pmu_t intel_knl_unc_cha26_support; extern pfmlib_pmu_t intel_knl_unc_cha27_support; extern pfmlib_pmu_t intel_knl_unc_cha28_support; extern pfmlib_pmu_t intel_knl_unc_cha29_support; extern pfmlib_pmu_t intel_knl_unc_cha30_support; extern pfmlib_pmu_t intel_knl_unc_cha31_support; extern pfmlib_pmu_t intel_knl_unc_cha32_support; extern pfmlib_pmu_t intel_knl_unc_cha33_support; extern pfmlib_pmu_t intel_knl_unc_cha34_support; extern pfmlib_pmu_t intel_knl_unc_cha35_support; extern pfmlib_pmu_t intel_knl_unc_cha36_support; extern pfmlib_pmu_t intel_knl_unc_cha37_support; extern pfmlib_pmu_t intel_knl_unc_m2pcie_support; extern pfmlib_pmu_t intel_bdx_unc_cb0_support; extern pfmlib_pmu_t intel_bdx_unc_cb1_support; extern pfmlib_pmu_t intel_bdx_unc_cb2_support; extern pfmlib_pmu_t intel_bdx_unc_cb3_support; extern pfmlib_pmu_t intel_bdx_unc_cb4_support; extern pfmlib_pmu_t intel_bdx_unc_cb5_support; extern pfmlib_pmu_t intel_bdx_unc_cb6_support; extern pfmlib_pmu_t intel_bdx_unc_cb7_support; extern pfmlib_pmu_t intel_bdx_unc_cb8_support; extern pfmlib_pmu_t intel_bdx_unc_cb9_support; extern pfmlib_pmu_t intel_bdx_unc_cb10_support; extern pfmlib_pmu_t intel_bdx_unc_cb11_support; extern pfmlib_pmu_t intel_bdx_unc_cb12_support; extern pfmlib_pmu_t intel_bdx_unc_cb13_support; extern pfmlib_pmu_t intel_bdx_unc_cb14_support; extern pfmlib_pmu_t intel_bdx_unc_cb15_support; extern pfmlib_pmu_t intel_bdx_unc_cb16_support; extern pfmlib_pmu_t intel_bdx_unc_cb17_support; extern pfmlib_pmu_t intel_bdx_unc_cb18_support; extern pfmlib_pmu_t intel_bdx_unc_cb19_support; extern pfmlib_pmu_t intel_bdx_unc_cb20_support; extern pfmlib_pmu_t intel_bdx_unc_cb21_support; extern pfmlib_pmu_t intel_bdx_unc_cb22_support; extern pfmlib_pmu_t intel_bdx_unc_cb23_support; extern pfmlib_pmu_t intel_bdx_unc_ha0_support; extern pfmlib_pmu_t intel_bdx_unc_ha1_support; extern pfmlib_pmu_t intel_bdx_unc_imc0_support; extern pfmlib_pmu_t intel_bdx_unc_imc1_support; extern pfmlib_pmu_t intel_bdx_unc_imc2_support; extern pfmlib_pmu_t intel_bdx_unc_imc3_support; extern pfmlib_pmu_t intel_bdx_unc_imc4_support; extern pfmlib_pmu_t intel_bdx_unc_imc5_support; extern pfmlib_pmu_t intel_bdx_unc_imc6_support; extern pfmlib_pmu_t intel_bdx_unc_imc7_support; extern pfmlib_pmu_t intel_bdx_unc_pcu_support; extern pfmlib_pmu_t intel_bdx_unc_qpi0_support; extern pfmlib_pmu_t intel_bdx_unc_qpi1_support; extern pfmlib_pmu_t intel_bdx_unc_qpi2_support; extern pfmlib_pmu_t intel_bdx_unc_sbo0_support; extern pfmlib_pmu_t intel_bdx_unc_sbo1_support; extern pfmlib_pmu_t intel_bdx_unc_sbo2_support; extern pfmlib_pmu_t intel_bdx_unc_sbo3_support; extern pfmlib_pmu_t intel_bdx_unc_ubo_support; extern pfmlib_pmu_t intel_bdx_unc_r2pcie_support; extern pfmlib_pmu_t intel_bdx_unc_r3qpi0_support; extern pfmlib_pmu_t intel_bdx_unc_r3qpi1_support; extern pfmlib_pmu_t intel_bdx_unc_r3qpi2_support; extern pfmlib_pmu_t intel_bdx_unc_irp_support; extern pfmlib_pmu_t intel_glm_support; extern pfmlib_pmu_t power4_support; extern pfmlib_pmu_t ppc970_support; extern pfmlib_pmu_t ppc970mp_support; extern pfmlib_pmu_t power5_support; extern pfmlib_pmu_t power5p_support; extern pfmlib_pmu_t power6_support; extern pfmlib_pmu_t power7_support; extern pfmlib_pmu_t power8_support; extern pfmlib_pmu_t power9_support; extern pfmlib_pmu_t torrent_support; extern pfmlib_pmu_t powerpc_nest_mcs_read_support; extern pfmlib_pmu_t powerpc_nest_mcs_write_support; extern pfmlib_pmu_t sparc_support; extern pfmlib_pmu_t sparc_ultra12_support; extern pfmlib_pmu_t sparc_ultra3_support; extern pfmlib_pmu_t sparc_ultra3i_support; extern pfmlib_pmu_t sparc_ultra3plus_support; extern pfmlib_pmu_t sparc_ultra4plus_support; extern pfmlib_pmu_t sparc_niagara1_support; extern pfmlib_pmu_t sparc_niagara2_support; extern pfmlib_pmu_t cell_support; extern pfmlib_pmu_t perf_event_support; extern pfmlib_pmu_t perf_event_raw_support; extern pfmlib_pmu_t intel_wsm_sp_support; extern pfmlib_pmu_t intel_wsm_dp_support; extern pfmlib_pmu_t intel_wsm_unc_support; extern pfmlib_pmu_t arm_cortex_a7_support; extern pfmlib_pmu_t arm_cortex_a8_support; extern pfmlib_pmu_t arm_cortex_a9_support; extern pfmlib_pmu_t arm_cortex_a15_support; extern pfmlib_pmu_t arm_1176_support; extern pfmlib_pmu_t arm_qcom_krait_support; extern pfmlib_pmu_t arm_cortex_a57_support; extern pfmlib_pmu_t arm_cortex_a53_support; extern pfmlib_pmu_t arm_xgene_support; extern pfmlib_pmu_t mips_74k_support; extern pfmlib_pmu_t s390x_cpum_cf_support; extern pfmlib_pmu_t s390x_cpum_sf_support; extern pfmlib_os_t *pfmlib_os; extern pfmlib_os_t pfmlib_os_perf; extern pfmlib_os_t pfmlib_os_perf_ext; extern char *pfmlib_forced_pmu; #define this_pe(t) (((pfmlib_pmu_t *)t)->pe) #define this_atdesc(t) (((pfmlib_pmu_t *)t)->atdesc) #define LIBPFM_ARRAY_SIZE(a) (sizeof(a) / sizeof(typeof(*(a)))) /* * population count (number of bits set) */ static inline int pfmlib_popcnt(unsigned long v) { int sum = 0; for(; v ; v >>=1) { if (v & 0x1) sum++; } return sum; } /* * find next bit set */ static inline size_t pfmlib_fnb(unsigned long value, size_t nbits, int p) { unsigned long m; size_t i; for(i=p; i < nbits; i++) { m = 1 << i; if (value & m) return i; } return i; } /* * PMU + internal idx -> external opaque idx */ static inline int pfmlib_pidx2idx(pfmlib_pmu_t *pmu, int pidx) { int idx; idx = pmu->pmu << PFMLIB_PMU_SHIFT; idx |= pidx; return idx; } #define pfmlib_for_each_bit(x, m) \ for((x) = pfmlib_fnb((m), (sizeof(m)<<3), 0); (x) < (sizeof(m)<<3); (x) = pfmlib_fnb((m), (sizeof(m)<<3), (x)+1)) #ifdef __linux__ #define PFMLIB_VALID_PERF_PATTRS(f) \ .validate_pattrs[PFM_OS_PERF_EVENT] = f, \ .validate_pattrs[PFM_OS_PERF_EVENT_EXT] = f #define PFMLIB_ENCODE_PERF(f) \ .get_event_encoding[PFM_OS_PERF_EVENT] = f, \ .get_event_encoding[PFM_OS_PERF_EVENT_EXT] = f #define PFMLIB_OS_DETECT(f) \ .os_detect[PFM_OS_PERF_EVENT] = f, \ .os_detect[PFM_OS_PERF_EVENT_EXT] = f #else #define PFMLIB_VALID_PERF_PATTRS(f) \ .validate_pattrs[PFM_OS_PERF_EVENT] = NULL, \ .validate_pattrs[PFM_OS_PERF_EVENT_EXT] = NULL #define PFMLIB_ENCODE_PERF(f) \ .get_event_encoding[PFM_OS_PERF_EVENT] = NULL, \ .get_event_encoding[PFM_OS_PERF_EVENT_EXT] = NULL #define PFMLIB_OS_DETECT(f) \ .os_detect[PFM_OS_PERF_EVENT] = NULL, \ .os_detect[PFM_OS_PERF_EVENT_EXT] = NULL #endif static inline int is_empty_attr(const pfmlib_attr_desc_t *a) { return !a || !a->name || strlen(a->name) == 0 ? 1 : 0; } #endif /* __PFMLIB_PRIV_H__ */ libpfm-4.9.0/lib/pfmlib_intel_hswep_unc_ubo.c0000664000175000017500000000602013223402656021112 0ustar eranianeranian/* * pfmlib_intel_hswep_unc_ubo.c : Intel Haswell-EP U-Box uncore PMU * * Copyright (c) 2014 Google Inc. All rights reserved * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_intel_x86_priv.h" #include "pfmlib_intel_snbep_unc_priv.h" #include "events/intel_hswep_unc_ubo_events.h" static void display_ubo(void *this, pfmlib_event_desc_t *e, void *val) { const intel_x86_entry_t *pe = this_pe(this); pfm_snbep_unc_reg_t *reg = val; __pfm_vbprintf("[UNC_UBO=0x%"PRIx64" event=0x%x umask=0x%x en=%d " "inv=%d edge=%d thres=%d] %s\n", reg->val, reg->com.unc_event, reg->com.unc_umask, reg->com.unc_en, reg->com.unc_inv, reg->com.unc_edge, reg->com.unc_thres, pe[e->event].name); } pfmlib_pmu_t intel_hswep_unc_ubo_support = { .desc = "Intel Haswell-EP U-Box uncore", .name = "hswep_unc_ubo", .perf_name = "uncore_ubox", .pmu = PFM_PMU_INTEL_HSWEP_UNC_UBOX, .pme_count = LIBPFM_ARRAY_SIZE(intel_hswep_unc_u_pe), .type = PFM_PMU_TYPE_UNCORE, .num_cntrs = 2, .num_fixed_cntrs = 1, .max_encoding = 1, .pe = intel_hswep_unc_u_pe, .atdesc = snbep_unc_mods, .flags = PFMLIB_PMU_FL_RAW_UMASK, .pmu_detect = pfm_intel_hswep_unc_detect, .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding, PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding), PFMLIB_OS_DETECT(pfm_intel_x86_perf_detect), .get_event_first = pfm_intel_x86_get_event_first, .get_event_next = pfm_intel_x86_get_event_next, .event_is_valid = pfm_intel_x86_event_is_valid, .validate_table = pfm_intel_x86_validate_table, .get_event_info = pfm_intel_x86_get_event_info, .get_event_attr_info = pfm_intel_x86_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs), .get_event_nattrs = pfm_intel_x86_get_event_nattrs, .display_reg = display_ubo, }; libpfm-4.9.0/lib/pfmlib_intel_knc.c0000664000175000017500000000457313223402656017040 0ustar eranianeranian/* * pfmlib_intel_knc.c : Intel Knights Corner (Xeon Phi) * * Copyright (c) 2012, Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ /* private headers */ #include "pfmlib_priv.h" /* library private */ #include "pfmlib_intel_x86_priv.h" /* architecture private */ #include "events/intel_knc_events.h" static const int knc_models[] = { 1, /* Knights Corner */ 0 }; pfmlib_pmu_t intel_knc_support={ .desc = "Intel Knights Corner", .name = "knc", .pmu = PFM_PMU_INTEL_KNC, .pme_count = LIBPFM_ARRAY_SIZE(intel_knc_pe), .type = PFM_PMU_TYPE_CORE, .num_cntrs = 2, .max_encoding = 1, .pe = intel_knc_pe, .atdesc = intel_x86_mods, .supported_plm = INTEL_X86_PLM, .cpu_family = 11, .cpu_models = knc_models, .pmu_detect = pfm_intel_x86_model_detect, .get_event_encoding[PFM_OS_NONE] = pfm_intel_x86_get_encoding, PFMLIB_ENCODE_PERF(pfm_intel_x86_get_perf_encoding), .get_event_first = pfm_intel_x86_get_event_first, .get_event_next = pfm_intel_x86_get_event_next, .event_is_valid = pfm_intel_x86_event_is_valid, .validate_table = pfm_intel_x86_validate_table, .get_event_info = pfm_intel_x86_get_event_info, .get_event_attr_info = pfm_intel_x86_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_intel_x86_perf_validate_pattrs), .get_event_nattrs = pfm_intel_x86_get_event_nattrs, }; libpfm-4.9.0/lib/pfmlib_arm_armv8.c0000664000175000017500000001166113223402656016762 0ustar eranianeranian/* * pfmlib_arm_armv8.c : support for ARMv8 processors * * Copyright (c) 2014 Google Inc. All rights reserved * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ #include #include #include /* private headers */ #include "pfmlib_priv.h" /* library private */ #include "pfmlib_arm_priv.h" #include "events/arm_cortex_a57_events.h" /* A57 event tables */ #include "events/arm_cortex_a53_events.h" /* A53 event tables */ #include "events/arm_xgene_events.h" /* Applied Micro X-Gene tables */ static int pfm_arm_detect_cortex_a57(void *this) { int ret; ret = pfm_arm_detect(this); if (ret != PFM_SUCCESS) return PFM_ERR_NOTSUPP; if ((pfm_arm_cfg.implementer == 0x41) && /* ARM */ (pfm_arm_cfg.part == 0xd07)) { /* Cortex A57 */ return PFM_SUCCESS; } return PFM_ERR_NOTSUPP; } static int pfm_arm_detect_cortex_a53(void *this) { int ret; ret = pfm_arm_detect(this); if (ret != PFM_SUCCESS) return PFM_ERR_NOTSUPP; if ((pfm_arm_cfg.implementer == 0x41) && /* ARM */ (pfm_arm_cfg.part == 0xd03)) { /* Cortex A53 */ return PFM_SUCCESS; } return PFM_ERR_NOTSUPP; } static int pfm_arm_detect_xgene(void *this) { int ret; ret = pfm_arm_detect(this); if (ret != PFM_SUCCESS) return PFM_ERR_NOTSUPP; if ((pfm_arm_cfg.implementer == 0x50) && /* Applied Micro */ (pfm_arm_cfg.part == 0x000)) { /* Applied Micro X-Gene */ return PFM_SUCCESS; } return PFM_ERR_NOTSUPP; } /* ARM Cortex A57 support */ pfmlib_pmu_t arm_cortex_a57_support={ .desc = "ARM Cortex A57", .name = "arm_ac57", .pmu = PFM_PMU_ARM_CORTEX_A57, .pme_count = LIBPFM_ARRAY_SIZE(arm_cortex_a57_pe), .type = PFM_PMU_TYPE_CORE, .pe = arm_cortex_a57_pe, .pmu_detect = pfm_arm_detect_cortex_a57, .max_encoding = 1, .num_cntrs = 6, .get_event_encoding[PFM_OS_NONE] = pfm_arm_get_encoding, PFMLIB_ENCODE_PERF(pfm_arm_get_perf_encoding), .get_event_first = pfm_arm_get_event_first, .get_event_next = pfm_arm_get_event_next, .event_is_valid = pfm_arm_event_is_valid, .validate_table = pfm_arm_validate_table, .get_event_info = pfm_arm_get_event_info, .get_event_attr_info = pfm_arm_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_arm_perf_validate_pattrs), .get_event_nattrs = pfm_arm_get_event_nattrs, }; /* ARM Cortex A53 support */ pfmlib_pmu_t arm_cortex_a53_support={ .desc = "ARM Cortex A53", .name = "arm_ac53", .pmu = PFM_PMU_ARM_CORTEX_A53, .pme_count = LIBPFM_ARRAY_SIZE(arm_cortex_a53_pe), .type = PFM_PMU_TYPE_CORE, .pe = arm_cortex_a53_pe, .pmu_detect = pfm_arm_detect_cortex_a53, .max_encoding = 1, .num_cntrs = 6, .get_event_encoding[PFM_OS_NONE] = pfm_arm_get_encoding, PFMLIB_ENCODE_PERF(pfm_arm_get_perf_encoding), .get_event_first = pfm_arm_get_event_first, .get_event_next = pfm_arm_get_event_next, .event_is_valid = pfm_arm_event_is_valid, .validate_table = pfm_arm_validate_table, .get_event_info = pfm_arm_get_event_info, .get_event_attr_info = pfm_arm_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_arm_perf_validate_pattrs), .get_event_nattrs = pfm_arm_get_event_nattrs, }; /* Applied Micro X-Gene support */ pfmlib_pmu_t arm_xgene_support={ .desc = "Applied Micro X-Gene", .name = "arm_xgene", .pmu = PFM_PMU_ARM_XGENE, .pme_count = LIBPFM_ARRAY_SIZE(arm_xgene_pe), .type = PFM_PMU_TYPE_CORE, .pe = arm_xgene_pe, .pmu_detect = pfm_arm_detect_xgene, .max_encoding = 1, .num_cntrs = 4, .get_event_encoding[PFM_OS_NONE] = pfm_arm_get_encoding, PFMLIB_ENCODE_PERF(pfm_arm_get_perf_encoding), .get_event_first = pfm_arm_get_event_first, .get_event_next = pfm_arm_get_event_next, .event_is_valid = pfm_arm_event_is_valid, .validate_table = pfm_arm_validate_table, .get_event_info = pfm_arm_get_event_info, .get_event_attr_info = pfm_arm_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_arm_perf_validate_pattrs), .get_event_nattrs = pfm_arm_get_event_nattrs, }; libpfm-4.9.0/lib/pfmlib_intel_bdx_unc_r2pcie.c0000664000175000017500000000602013223402656021140 0ustar eranianeranian/* * pfmlib_intel_bdx_r2pcie.c : Intel BroadwellX R2PCIe uncore PMU * * Copyright (c) 2017 Google Inc. All rights reserved * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_intel_x86_priv.h" #include "pfmlib_intel_snbep_unc_priv.h" #include "events/intel_bdx_unc_r2pcie_events.h" static void display_r2(void *this, pfmlib_event_desc_t *e, void *val) { const intel_x86_entry_t *pe = this_pe(this); pfm_snbep_unc_reg_t *reg = val; __pfm_vbprintf("[UNC_R2PCIE=0x%"PRIx64" event=0x%x umask=0x%x en=%d " "inv=%d edge=%d thres=%d] %s\n", reg->val, reg->com.unc_event, reg->com.unc_umask, reg->com.unc_en, reg->com.unc_inv, reg->com.unc_edge, reg->com.unc_thres, pe[e->event].name); } pfmlib_pmu_t intel_bdx_unc_r2pcie_support = { .desc = "Intel BroadwellX R2PCIe uncore", .name = "bdx_unc_r2pcie", .perf_name = "uncore_r2pcie", .pmu = PFM_PMU_INTEL_BDX_UNC_R2PCIE, .pme_count = LIBPFM_ARRAY_SIZE(intel_bdx_unc_r2_pe), .type = PFM_PMU_TYPE_UNCORE, .num_cntrs = 4, .num_fixed_cntrs = 0, .max_encoding = 1, .pe = intel_bdx_unc_r2_pe, .atdesc = snbep_unc_mods, .flags = PFMLIB_PMU_FL_RAW_UMASK, .pmu_detect = pfm_intel_bdx_unc_detect, .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding, PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding), PFMLIB_OS_DETECT(pfm_intel_x86_perf_detect), .get_event_first = pfm_intel_x86_get_event_first, .get_event_next = pfm_intel_x86_get_event_next, .event_is_valid = pfm_intel_x86_event_is_valid, .validate_table = pfm_intel_x86_validate_table, .get_event_info = pfm_intel_x86_get_event_info, .get_event_attr_info = pfm_intel_x86_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs), .get_event_nattrs = pfm_intel_x86_get_event_nattrs, .display_reg = display_r2, }; libpfm-4.9.0/lib/pfmlib_intel_ivb.c0000664000175000017500000000760013223402656017037 0ustar eranianeranian/* * pfmlib_intel_ivb.c : Intel Ivy Bridge core PMU * * Copyright (c) 2012 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_intel_x86_priv.h" #include "events/intel_ivb_events.h" static int pfm_ivb_init(void *this) { pfm_intel_x86_cfg.arch_version = 3; return PFM_SUCCESS; } static const int ivb_models[] = { 58, /* IvyBridge (Core i3/i5/i7 3xxx) */ 0 }; static const int ivbep_models[] = { 62, /* Ivytown */ 0 }; pfmlib_pmu_t intel_ivb_support={ .desc = "Intel Ivy Bridge", .name = "ivb", .pmu = PFM_PMU_INTEL_IVB, .pme_count = LIBPFM_ARRAY_SIZE(intel_ivb_pe), .type = PFM_PMU_TYPE_CORE, .supported_plm = INTEL_X86_PLM, .num_cntrs = 8, /* consider with HT off by default */ .num_fixed_cntrs = 3, .max_encoding = 2, /* offcore_response */ .pe = intel_ivb_pe, .atdesc = intel_x86_mods, .flags = PFMLIB_PMU_FL_RAW_UMASK | INTEL_X86_PMU_FL_ECMASK, .cpu_family = 6, .cpu_models = ivb_models, .pmu_detect = pfm_intel_x86_model_detect, .pmu_init = pfm_ivb_init, .get_event_encoding[PFM_OS_NONE] = pfm_intel_x86_get_encoding, PFMLIB_ENCODE_PERF(pfm_intel_x86_get_perf_encoding), .get_event_first = pfm_intel_x86_get_event_first, .get_event_next = pfm_intel_x86_get_event_next, .event_is_valid = pfm_intel_x86_event_is_valid, .validate_table = pfm_intel_x86_validate_table, .get_event_info = pfm_intel_x86_get_event_info, .get_event_attr_info = pfm_intel_x86_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_intel_x86_perf_validate_pattrs), .get_event_nattrs = pfm_intel_x86_get_event_nattrs, .can_auto_encode = pfm_intel_x86_can_auto_encode, }; pfmlib_pmu_t intel_ivb_ep_support={ .desc = "Intel Ivy Bridge EP", .name = "ivb_ep", .pmu = PFM_PMU_INTEL_IVB_EP, .pme_count = LIBPFM_ARRAY_SIZE(intel_ivb_pe), .type = PFM_PMU_TYPE_CORE, .supported_plm = INTEL_X86_PLM, .num_cntrs = 8, /* consider with HT off by default */ .num_fixed_cntrs = 3, .max_encoding = 2, /* offcore_response */ .pe = intel_ivb_pe, .atdesc = intel_x86_mods, .flags = PFMLIB_PMU_FL_RAW_UMASK | INTEL_X86_PMU_FL_ECMASK, .cpu_family = 6, .cpu_models = ivbep_models, .pmu_detect = pfm_intel_x86_model_detect, .pmu_init = pfm_ivb_init, .get_event_encoding[PFM_OS_NONE] = pfm_intel_x86_get_encoding, PFMLIB_ENCODE_PERF(pfm_intel_x86_get_perf_encoding), .get_event_first = pfm_intel_x86_get_event_first, .get_event_next = pfm_intel_x86_get_event_next, .event_is_valid = pfm_intel_x86_event_is_valid, .validate_table = pfm_intel_x86_validate_table, .get_event_info = pfm_intel_x86_get_event_info, .get_event_attr_info = pfm_intel_x86_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_intel_x86_perf_validate_pattrs), .get_event_nattrs = pfm_intel_x86_get_event_nattrs, .can_auto_encode = pfm_intel_x86_can_auto_encode, }; libpfm-4.9.0/lib/pfmlib_intel_hswep_unc_imc.c0000664000175000017500000000552013223402656021101 0ustar eranianeranian/* * pfmlib_intel_hswep_unc_imc.c : Intel Haswell-EP Integrated Memory Controller (IMC) uncore PMU * * Copyright (c) 2014 Google Inc. All rights reserved * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_intel_x86_priv.h" #include "pfmlib_intel_snbep_unc_priv.h" #include "events/intel_hswep_unc_imc_events.h" #define DEFINE_IMC_BOX(n) \ pfmlib_pmu_t intel_hswep_unc_imc##n##_support = { \ .desc = "Intel Haswell-EP IMC"#n" uncore", \ .name = "hswep_unc_imc"#n, \ .perf_name = "uncore_imc_"#n, \ .pmu = PFM_PMU_INTEL_HSWEP_UNC_IMC##n, \ .pme_count = LIBPFM_ARRAY_SIZE(intel_hswep_unc_m_pe), \ .type = PFM_PMU_TYPE_UNCORE, \ .num_cntrs = 4, \ .num_fixed_cntrs = 1, \ .max_encoding = 1, \ .pe = intel_hswep_unc_m_pe, \ .atdesc = snbep_unc_mods, \ .flags = PFMLIB_PMU_FL_RAW_UMASK, \ .pmu_detect = pfm_intel_hswep_unc_detect, \ .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding, \ PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding), \ PFMLIB_OS_DETECT(pfm_intel_x86_perf_detect), \ .get_event_first = pfm_intel_x86_get_event_first, \ .get_event_next = pfm_intel_x86_get_event_next, \ .event_is_valid = pfm_intel_x86_event_is_valid, \ .validate_table = pfm_intel_x86_validate_table, \ .get_event_info = pfm_intel_x86_get_event_info, \ .get_event_attr_info = pfm_intel_x86_get_event_attr_info, \ PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs), \ .get_event_nattrs = pfm_intel_x86_get_event_nattrs, \ }; DEFINE_IMC_BOX(0); DEFINE_IMC_BOX(1); DEFINE_IMC_BOX(2); DEFINE_IMC_BOX(3); DEFINE_IMC_BOX(4); DEFINE_IMC_BOX(5); DEFINE_IMC_BOX(6); DEFINE_IMC_BOX(7); libpfm-4.9.0/lib/pfmlib_intel_snbep_unc.c0000664000175000017500000004701313223402656020235 0ustar eranianeranian/* * pfmlib_intel_snbep_unc.c : Intel SandyBridge-EP uncore PMU common code * * Copyright (c) 2012 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_intel_x86_priv.h" #include "pfmlib_intel_snbep_unc_priv.h" const pfmlib_attr_desc_t snbep_unc_mods[]={ PFM_ATTR_B("e", "edge detect"), /* edge */ PFM_ATTR_B("i", "invert"), /* invert */ PFM_ATTR_I("t", "threshold in range [0-255]"), /* threshold */ PFM_ATTR_I("t", "threshold in range [0-31]"), /* threshold */ PFM_ATTR_I("tf", "thread id filter [0-1]"), /* thread id */ PFM_ATTR_I("cf", "core id filter, includes non-thread data in bit 4 [0-15]"), /* core id (ivbep) */ PFM_ATTR_I("nf", "node id bitmask filter [0-255]"),/* nodeid mask filter0 */ PFM_ATTR_I("ff", "frequency >= 100Mhz * [0-255]"),/* freq filter */ PFM_ATTR_I("addr", "physical address matcher [40 bits]"),/* address matcher */ PFM_ATTR_I("nf", "node id bitmask filter [0-255]"),/* nodeid mask filter1 */ PFM_ATTR_B("isoc", "match isochronous requests"), /* isochronous */ PFM_ATTR_B("nc", "match non-coherent requests"), /* non-coherent */ PFM_ATTR_I("cf", "core id filter, includes non-thread data in bit 5 [0-63]"), /* core id (hswep) */ PFM_ATTR_NULL }; int pfm_intel_snbep_unc_detect(void *this) { int ret; ret = pfm_intel_x86_detect(); if (ret != PFM_SUCCESS) if (pfm_intel_x86_cfg.family != 6) return PFM_ERR_NOTSUPP; switch(pfm_intel_x86_cfg.model) { case 45: /* SandyBridge-EP */ break; default: return PFM_ERR_NOTSUPP; } return PFM_SUCCESS; } int pfm_intel_ivbep_unc_detect(void *this) { int ret; ret = pfm_intel_x86_detect(); if (ret != PFM_SUCCESS) if (pfm_intel_x86_cfg.family != 6) return PFM_ERR_NOTSUPP; switch(pfm_intel_x86_cfg.model) { case 62: /* SandyBridge-EP */ break; default: return PFM_ERR_NOTSUPP; } return PFM_SUCCESS; } int pfm_intel_hswep_unc_detect(void *this) { int ret; ret = pfm_intel_x86_detect(); if (ret != PFM_SUCCESS) if (pfm_intel_x86_cfg.family != 6) return PFM_ERR_NOTSUPP; switch(pfm_intel_x86_cfg.model) { case 63: /* Haswell-EP */ break; default: return PFM_ERR_NOTSUPP; } return PFM_SUCCESS; } int pfm_intel_knl_unc_detect(void *this) { int ret; ret = pfm_intel_x86_detect(); if (ret != PFM_SUCCESS) if (pfm_intel_x86_cfg.family != 6) return PFM_ERR_NOTSUPP; switch(pfm_intel_x86_cfg.model) { case 87: /* Knights Landing */ break; default: return PFM_ERR_NOTSUPP; } return PFM_SUCCESS; } int pfm_intel_bdx_unc_detect(void *this) { int ret; ret = pfm_intel_x86_detect(); if (ret != PFM_SUCCESS) if (pfm_intel_x86_cfg.family != 6) return PFM_ERR_NOTSUPP; switch(pfm_intel_x86_cfg.model) { case 79: /* Broadwell X */ case 86: /* Broadwell X */ break; default: return PFM_ERR_NOTSUPP; } return PFM_SUCCESS; } static void display_com(void *this, pfmlib_event_desc_t *e, void *val) { const intel_x86_entry_t *pe = this_pe(this); pfm_snbep_unc_reg_t *reg = val; __pfm_vbprintf("[UNC=0x%"PRIx64" event=0x%x umask=0x%x en=%d " "inv=%d edge=%d thres=%d] %s\n", reg->val, reg->com.unc_event, reg->com.unc_umask, reg->com.unc_en, reg->com.unc_inv, reg->com.unc_edge, reg->com.unc_thres, pe[e->event].name); } static void display_reg(void *this, pfmlib_event_desc_t *e, pfm_snbep_unc_reg_t reg) { pfmlib_pmu_t *pmu = this; if (pmu->display_reg) pmu->display_reg(this, e, ®); else display_com(this, e, ®); } static inline int is_occ_event(void *this, int idx) { pfmlib_pmu_t *pmu = this; const intel_x86_entry_t *pe = this_pe(this); return (pmu->flags & INTEL_PMU_FL_UNC_OCC) && (pe[idx].code & 0x80); } static inline int get_pcu_filt_band(void *this, pfm_snbep_unc_reg_t reg) { #define PCU_FREQ_BAND0_CODE 0xb /* event code for UNC_P_FREQ_BAND0_CYCLES */ return reg.pcu.unc_event - PCU_FREQ_BAND0_CODE; } int snbep_unc_add_defaults(void *this, pfmlib_event_desc_t *e, unsigned int msk, uint64_t *umask, pfm_snbep_unc_reg_t *filters, unsigned short max_grpid) { const intel_x86_entry_t *pe = this_pe(this); const intel_x86_entry_t *ent; unsigned int i; int j, k, added, skip; int idx; k = e->nattrs; ent = pe+e->event; for(i=0; msk; msk >>=1, i++) { if (!(msk & 0x1)) continue; added = skip = 0; for (j = 0; j < e->npattrs; j++) { if (e->pattrs[j].ctrl != PFM_ATTR_CTRL_PMU) continue; if (e->pattrs[j].type != PFM_ATTR_UMASK) continue; idx = e->pattrs[j].idx; if (ent->umasks[idx].grpid != i) continue; if (max_grpid != INTEL_X86_MAX_GRPID && i > max_grpid) { skip = 1; continue; } if (intel_x86_uflag(this, e->event, idx, INTEL_X86_GRP_DFL_NONE)) { skip = 1; continue; } /* umask is default for group */ if (intel_x86_uflag(this, e->event, idx, INTEL_X86_DFL)) { DPRINT("added default %s for group %d j=%d idx=%d ucode=0x%"PRIx64"\n", ent->umasks[idx].uname, i, j, idx, ent->umasks[idx].ucode); /* * default could be an alias, but * ucode must reflect actual code */ *umask |= ent->umasks[idx].ucode >> 8; filters[0].val |= pe[e->event].umasks[idx].ufilters[0]; filters[1].val |= pe[e->event].umasks[idx].ufilters[1]; e->attrs[k].id = j; /* pattrs index */ e->attrs[k].ival = 0; k++; added++; if (intel_x86_eflag(this, e->event, INTEL_X86_GRP_EXCL)) goto done; if (intel_x86_uflag(this, e->event, idx, INTEL_X86_EXCL_GRP_GT)) { if (max_grpid != INTEL_X86_MAX_GRPID) { DPRINT("two max_grpid, old=%d new=%d\n", max_grpid, ent->umasks[idx].grpid); return PFM_ERR_UMASK; } max_grpid = ent->umasks[idx].grpid; } } } if (!added && !skip) { DPRINT("no default found for event %s unit mask group %d (max_grpid=%d, i=%d)\n", ent->name, i, max_grpid, i); return PFM_ERR_UMASK; } } DPRINT("max_grpid=%d nattrs=%d k=%d umask=0x%"PRIx64"\n", max_grpid, e->nattrs, k, *umask); done: e->nattrs = k; return PFM_SUCCESS; } /* * common encoding routine */ int pfm_intel_snbep_unc_get_encoding(void *this, pfmlib_event_desc_t *e) { const intel_x86_entry_t *pe = this_pe(this); unsigned int grpmsk, ugrpmsk = 0; unsigned short max_grpid = INTEL_X86_MAX_GRPID; unsigned short last_grpid = INTEL_X86_MAX_GRPID; int umodmsk = 0, modmsk_r = 0; int pcu_filt_band = -1; pfm_snbep_unc_reg_t reg; pfm_snbep_unc_reg_t filters[INTEL_X86_MAX_FILTERS]; pfm_snbep_unc_reg_t addr; pfmlib_event_attr_info_t *a; uint64_t val, umask1, umask2; int k, ret; int has_cbo_tid = 0; unsigned short grpid; int grpcounts[INTEL_X86_NUM_GRP]; int ncombo[INTEL_X86_NUM_GRP]; char umask_str[PFMLIB_EVT_MAX_NAME_LEN]; memset(grpcounts, 0, sizeof(grpcounts)); memset(ncombo, 0, sizeof(ncombo)); memset(filters, 0, sizeof(filters)); addr.val = 0; pe = this_pe(this); umask_str[0] = e->fstr[0] = '\0'; reg.val = val = pe[e->event].code; /* take into account hardcoded umask */ umask1 = (val >> 8) & 0xff; umask2 = umask1; grpmsk = (1 << pe[e->event].ngrp)-1; modmsk_r = pe[e->event].modmsk_req; for(k=0; k < e->nattrs; k++) { a = attr(e, k); if (a->ctrl != PFM_ATTR_CTRL_PMU) continue; if (a->type == PFM_ATTR_UMASK) { uint64_t um; grpid = pe[e->event].umasks[a->idx].grpid; /* * certain event groups are meant to be * exclusive, i.e., only unit masks of one group * can be used */ if (last_grpid != INTEL_X86_MAX_GRPID && grpid != last_grpid && intel_x86_eflag(this, e->event, INTEL_X86_GRP_EXCL)) { DPRINT("exclusive unit mask group error\n"); return PFM_ERR_FEATCOMB; } /* * selecting certain umasks in a group may exclude any umasks * from any groups with a higher index * * enforcement requires looking at the grpid of all the umasks */ if (intel_x86_uflag(this, e->event, a->idx, INTEL_X86_EXCL_GRP_GT)) max_grpid = grpid; /* * certain event groups are meant to be * exclusive, i.e., only unit masks of one group * can be used */ if (last_grpid != INTEL_X86_MAX_GRPID && grpid != last_grpid && intel_x86_eflag(this, e->event, INTEL_X86_GRP_EXCL)) { DPRINT("exclusive unit mask group error\n"); return PFM_ERR_FEATCOMB; } /* * upper layer has removed duplicates * so if we come here more than once, it is for two * disinct umasks * * NCOMBO=no combination of unit masks within the same * umask group */ ++grpcounts[grpid]; /* mark that we have a umask with NCOMBO in this group */ if (intel_x86_uflag(this, e->event, a->idx, INTEL_X86_NCOMBO)) ncombo[grpid] = 1; /* * if more than one umask in this group but one is marked * with ncombo, then fail. It is okay to combine umask within * a group as long as none is tagged with NCOMBO */ if (grpcounts[grpid] > 1 && ncombo[grpid]) { DPRINT("umask %s does not support unit mask combination within group %d\n", pe[e->event].umasks[a->idx].uname, grpid); return PFM_ERR_FEATCOMB; } last_grpid = grpid; um = pe[e->event].umasks[a->idx].ucode; filters[0].val |= pe[e->event].umasks[a->idx].ufilters[0]; filters[1].val |= pe[e->event].umasks[a->idx].ufilters[1]; um >>= 8; umask2 |= um; ugrpmsk |= 1 << pe[e->event].umasks[a->idx].grpid; /* PCU occ event */ if (is_occ_event(this, e->event)) { reg.pcu.unc_occ = umask2 >> 6; umask2 = 0; } else reg.val |= umask2 << 8; evt_strcat(umask_str, ":%s", pe[e->event].umasks[a->idx].uname); modmsk_r |= pe[e->event].umasks[a->idx].umodmsk_req; } else if (a->type == PFM_ATTR_RAW_UMASK) { /* there can only be one RAW_UMASK per event */ /* sanity check */ if (a->idx & ~0xff) { DPRINT("raw umask is 8-bit wide\n"); return PFM_ERR_ATTR; } /* override umask */ umask2 = a->idx & 0xff; ugrpmsk = grpmsk; } else { uint64_t ival = e->attrs[k].ival; switch(a->idx) { case SNBEP_UNC_ATTR_I: /* invert */ if (is_occ_event(this, e->event)) reg.pcu.unc_occ_inv = !!ival; else reg.com.unc_inv = !!ival; umodmsk |= _SNBEP_UNC_ATTR_I; break; case SNBEP_UNC_ATTR_E: /* edge */ if (is_occ_event(this, e->event)) reg.pcu.unc_occ_edge = !!ival; else reg.com.unc_edge = !!ival; umodmsk |= _SNBEP_UNC_ATTR_E; break; case SNBEP_UNC_ATTR_T8: /* counter-mask */ /* already forced, cannot overwrite */ if (ival > 255) return PFM_ERR_ATTR_VAL; reg.com.unc_thres = ival; umodmsk |= _SNBEP_UNC_ATTR_T8; break; case SNBEP_UNC_ATTR_T5: /* pcu counter-mask */ /* already forced, cannot overwrite */ if (ival > 31) return PFM_ERR_ATTR_VAL; reg.pcu.unc_thres = ival; umodmsk |= _SNBEP_UNC_ATTR_T5; break; case SNBEP_UNC_ATTR_TF: /* thread id */ if (ival > 1) { DPRINT("invalid thread id, must be < 1"); return PFM_ERR_ATTR_VAL; } reg.cbo.unc_tid = 1; has_cbo_tid = 1; filters[0].cbo_filt.tid = ival; umodmsk |= _SNBEP_UNC_ATTR_TF; break; case SNBEP_UNC_ATTR_CF: /* core id */ if (ival > 15) return PFM_ERR_ATTR_VAL; reg.cbo.unc_tid = 1; filters[0].cbo_filt.cid = ival; has_cbo_tid = 1; umodmsk |= _SNBEP_UNC_ATTR_CF; break; case SNBEP_UNC_ATTR_CF1: /* core id */ if (ival > 63) return PFM_ERR_ATTR_VAL; reg.cbo.unc_tid = 1; filters[0].hswep_cbo_filt0.cid = ival; /* includes non-thread data */ has_cbo_tid = 1; umodmsk |= _SNBEP_UNC_ATTR_CF1; break; case SNBEP_UNC_ATTR_NF: /* node id filter0 */ if (ival > 255 || ival == 0) { DPRINT("invalid nf, 0 < nf < 256\n"); return PFM_ERR_ATTR_VAL; } filters[0].cbo_filt.nid = ival; umodmsk |= _SNBEP_UNC_ATTR_NF; break; case SNBEP_UNC_ATTR_NF1: /* node id filter1 */ if (ival > 255 || ival == 0) { DPRINT("invalid nf, 0 < nf < 256\n"); return PFM_ERR_ATTR_VAL; } filters[1].ivbep_cbo_filt1.nid = ival; umodmsk |= _SNBEP_UNC_ATTR_NF1; break; case SNBEP_UNC_ATTR_FF: /* freq band filter */ if (ival > 255) return PFM_ERR_ATTR_VAL; pcu_filt_band = get_pcu_filt_band(this, reg); filters[0].val = ival << (pcu_filt_band * 8); umodmsk |= _SNBEP_UNC_ATTR_FF; break; case SNBEP_UNC_ATTR_A: /* addr filter */ if (ival & ~((1ULL << 40)-1)) { DPRINT("address filter 40bits max\n"); return PFM_ERR_ATTR_VAL; } addr.ha_addr.lo_addr = ival; /* LSB 26 bits */ addr.ha_addr.hi_addr = (ival >> 26) & ((1ULL << 14)-1); umodmsk |= _SNBEP_UNC_ATTR_A; break; case SNBEP_UNC_ATTR_ISOC: /* isoc filter */ filters[1].ivbep_cbo_filt1.isoc = !!ival; break; case SNBEP_UNC_ATTR_NC: /* nc filter */ filters[1].ivbep_cbo_filt1.nc = !!ival; break; } } } /* * check that there is at least of unit mask in each unit mask group */ if (pe[e->event].numasks && (ugrpmsk != grpmsk || ugrpmsk == 0)) { uint64_t um = 0; ugrpmsk ^= grpmsk; ret = snbep_unc_add_defaults(this, e, ugrpmsk, &um, filters, max_grpid); if (ret != PFM_SUCCESS) return ret; umask2 |= um; } /* * nf= is only required on some events in CBO */ if (!(modmsk_r & _SNBEP_UNC_ATTR_NF) && (umodmsk & _SNBEP_UNC_ATTR_NF)) { DPRINT("using nf= on an umask which does not require it\n"); return PFM_ERR_ATTR; } if (!(modmsk_r & _SNBEP_UNC_ATTR_NF1) && (umodmsk & _SNBEP_UNC_ATTR_NF1)) { DPRINT("using nf= on an umask which does not require it\n"); return PFM_ERR_ATTR; } if (modmsk_r && !(umodmsk & modmsk_r)) { DPRINT("required modifiers missing: 0x%x\n", modmsk_r); return PFM_ERR_ATTR; } evt_strcat(e->fstr, "%s", pe[e->event].name); pfmlib_sort_attr(e); for(k = 0; k < e->nattrs; k++) { a = attr(e, k); if (a->ctrl != PFM_ATTR_CTRL_PMU) continue; if (a->type == PFM_ATTR_UMASK) evt_strcat(e->fstr, ":%s", pe[e->event].umasks[a->idx].uname); else if (a->type == PFM_ATTR_RAW_UMASK) evt_strcat(e->fstr, ":0x%x", a->idx); } DPRINT("umask2=0x%"PRIx64" umask1=0x%"PRIx64"\n", umask2, umask1); e->count = 0; reg.val |= (umask1 | umask2) << 8; e->codes[e->count++] = reg.val; /* * handles C-box filter */ if (filters[0].val || filters[1].val || has_cbo_tid) e->codes[e->count++] = filters[0].val; if (filters[1].val) e->codes[e->count++] = filters[1].val; /* HA address matcher */ if (addr.val) e->codes[e->count++] = addr.val; for (k = 0; k < e->npattrs; k++) { int idx; if (e->pattrs[k].ctrl != PFM_ATTR_CTRL_PMU) continue; if (e->pattrs[k].type == PFM_ATTR_UMASK) continue; idx = e->pattrs[k].idx; switch(idx) { case SNBEP_UNC_ATTR_E: if (is_occ_event(this, e->event)) evt_strcat(e->fstr, ":%s=%lu", snbep_unc_mods[idx].name, reg.pcu.unc_occ_edge); else evt_strcat(e->fstr, ":%s=%lu", snbep_unc_mods[idx].name, reg.com.unc_edge); break; case SNBEP_UNC_ATTR_I: if (is_occ_event(this, e->event)) evt_strcat(e->fstr, ":%s=%lu", snbep_unc_mods[idx].name, reg.pcu.unc_occ_inv); else evt_strcat(e->fstr, ":%s=%lu", snbep_unc_mods[idx].name, reg.com.unc_inv); break; case SNBEP_UNC_ATTR_T8: evt_strcat(e->fstr, ":%s=%lu", snbep_unc_mods[idx].name, reg.com.unc_thres); break; case SNBEP_UNC_ATTR_T5: evt_strcat(e->fstr, ":%s=%lu", snbep_unc_mods[idx].name, reg.pcu.unc_thres); break; case SNBEP_UNC_ATTR_TF: evt_strcat(e->fstr, ":%s=%lu", snbep_unc_mods[idx].name, reg.cbo.unc_tid); break; case SNBEP_UNC_ATTR_CF: evt_strcat(e->fstr, ":%s=%lu", snbep_unc_mods[idx].name, filters[0].cbo_filt.cid); break; case SNBEP_UNC_ATTR_CF1: evt_strcat(e->fstr, ":%s=%lu", snbep_unc_mods[idx].name, filters[0].hswep_cbo_filt0.cid); break; case SNBEP_UNC_ATTR_FF: evt_strcat(e->fstr, ":%s=%lu", snbep_unc_mods[idx].name, (filters[0].val >> (pcu_filt_band*8)) & 0xff); break; case SNBEP_UNC_ATTR_ISOC: evt_strcat(e->fstr, ":%s=%lu", snbep_unc_mods[idx].name, filters[1].ivbep_cbo_filt1.isoc); break; case SNBEP_UNC_ATTR_NC: evt_strcat(e->fstr, ":%s=%lu", snbep_unc_mods[idx].name, filters[1].ivbep_cbo_filt1.nc); break; case SNBEP_UNC_ATTR_NF: if (modmsk_r & _SNBEP_UNC_ATTR_NF) evt_strcat(e->fstr, ":%s=%lu", snbep_unc_mods[idx].name, filters[0].cbo_filt.nid); break; case SNBEP_UNC_ATTR_NF1: if (modmsk_r & _SNBEP_UNC_ATTR_NF1) evt_strcat(e->fstr, ":%s=%lu", snbep_unc_mods[idx].name, filters[1].ivbep_cbo_filt1.nid); break; case SNBEP_UNC_ATTR_A: evt_strcat(e->fstr, ":%s=0x%lx", snbep_unc_mods[idx].name, addr.ha_addr.hi_addr << 26 | addr.ha_addr.lo_addr); break; } } display_reg(this, e, reg); return PFM_SUCCESS; } int pfm_intel_snbep_unc_can_auto_encode(void *this, int pidx, int uidx) { if (intel_x86_eflag(this, pidx, INTEL_X86_NO_AUTOENCODE)) return 0; return !intel_x86_uflag(this, pidx, uidx, INTEL_X86_NO_AUTOENCODE); } int pfm_intel_snbep_unc_get_event_attr_info(void *this, int pidx, int attr_idx, pfmlib_event_attr_info_t *info) { const intel_x86_entry_t *pe = this_pe(this); const pfmlib_attr_desc_t *atdesc = this_atdesc(this); int numasks, idx; numasks = intel_x86_num_umasks(this, pidx); if (attr_idx < numasks) { idx = intel_x86_attr2umask(this, pidx, attr_idx); info->name = pe[pidx].umasks[idx].uname; info->desc = pe[pidx].umasks[idx].udesc; info->equiv= pe[pidx].umasks[idx].uequiv; info->code = pe[pidx].umasks[idx].ucode; if (!intel_x86_uflag(this, pidx, idx, INTEL_X86_CODE_OVERRIDE)) info->code >>= 8; if (info->code == 0) info->code = pe[pidx].umasks[idx].ufilters[0]; info->type = PFM_ATTR_UMASK; info->is_dfl = intel_x86_uflag(this, pidx, idx, INTEL_X86_DFL); info->is_precise = intel_x86_uflag(this, pidx, idx, INTEL_X86_PEBS); } else { idx = intel_x86_attr2mod(this, pidx, attr_idx); info->name = atdesc[idx].name; info->desc = atdesc[idx].desc; info->type = atdesc[idx].type; info->equiv= NULL; info->code = idx; info->is_dfl = 0; info->is_precise = 0; } info->ctrl = PFM_ATTR_CTRL_PMU; info->idx = idx; /* namespace specific index */ info->dfl_val64 = 0; return PFM_SUCCESS; } libpfm-4.9.0/lib/pfmlib_itanium_priv.h0000664000175000017500000000714713223402656017605 0ustar eranianeranian/* * Copyright (c) 2001-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux/ia64. */ #ifndef __PFMLIB_ITANIUM_PRIV_H__ #define __PFMLIB_ITANIUM_PRIV_H__ /* * Itanium encoding structure * (code must be first 8 bits) */ typedef struct { unsigned long pme_code:8; /* major event code */ unsigned long pme_ear:1; /* is EAR event */ unsigned long pme_dear:1; /* 1=Data 0=Instr */ unsigned long pme_tlb:1; /* 1=TLB 0=Cache */ unsigned long pme_btb:1; /* 1=BTB */ unsigned long pme_ig1:4; /* ignored */ unsigned long pme_umask:16; /* unit mask*/ unsigned long pme_ig:32; /* ignored */ } pme_ita_entry_code_t; #define PME_UMASK_NONE 0x0 typedef union { unsigned long pme_vcode; pme_ita_entry_code_t pme_ita_code; /* must not be larger than vcode */ } pme_ita_code_t; typedef union { unsigned long qual; /* generic qualifier */ struct { unsigned long pme_iar:1; /* instruction address range supported */ unsigned long pme_opm:1; /* opcode match supported */ unsigned long pme_dar:1; /* data address range supported */ unsigned long pme_reserved:61; /* not used */ } pme_qual; } pme_ita_qualifiers_t; typedef struct { char *pme_name; pme_ita_code_t pme_entry_code; unsigned long pme_counters; /* supported counters */ unsigned int pme_maxincr; pme_ita_qualifiers_t pme_qualifiers; char *pme_desc; } pme_ita_entry_t; /* * We embed the umask value into the event code. Because it really is * like a subevent. * pme_code: * - lower 16 bits: major event code * - upper 16 bits: unit mask */ #define pme_code pme_entry_code.pme_ita_code.pme_code #define pme_ear pme_entry_code.pme_ita_code.pme_ear #define pme_dear pme_entry_code.pme_ita_code.pme_dear #define pme_tlb pme_entry_code.pme_ita_code.pme_tlb #define pme_btb pme_entry_code.pme_ita_code.pme_btb #define pme_umask pme_entry_code.pme_ita_code.pme_umask #define pme_used pme_qualifiers.pme_qual_struct.pme_used #define event_is_ear(e) ((e)->pme_ear == 1) #define event_is_iear(e) ((e)->pme_ear == 1 && (e)->pme_dear==0) #define event_is_dear(e) ((e)->pme_ear == 1 && (e)->pme_dear==1) #define event_is_tlb_ear(e) ((e)->pme_ear == 1 && (e)->pme_tlb==1) #define event_is_btb(e) ((e)->pme_btb) #define event_opcm_ok(e) ((e)->pme_qualifiers.pme_qual.pme_opm==1) #define event_iarr_ok(e) ((e)->pme_qualifiers.pme_qual.pme_iar==1) #define event_darr_ok(e) ((e)->pme_qualifiers.pme_qual.pme_dar==1) #endif /* __PFMLIB_ITANIUM_PRIV_H__ */ libpfm-4.9.0/lib/pfmlib_intel_bdx_unc_imc.c0000664000175000017500000000550013223402656020526 0ustar eranianeranian/* * pfmlib_intel_bdx_unc_imc.c : Intel BroadwellX Integrated Memory Controller (IMC) uncore PMU * * Copyright (c) 2017 Google Inc. All rights reserved * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_intel_x86_priv.h" #include "pfmlib_intel_snbep_unc_priv.h" #include "events/intel_bdx_unc_imc_events.h" #define DEFINE_IMC_BOX(n) \ pfmlib_pmu_t intel_bdx_unc_imc##n##_support = { \ .desc = "Intel BroadwellX IMC"#n" uncore", \ .name = "bdx_unc_imc"#n, \ .perf_name = "uncore_imc_"#n, \ .pmu = PFM_PMU_INTEL_BDX_UNC_IMC##n, \ .pme_count = LIBPFM_ARRAY_SIZE(intel_bdx_unc_m_pe), \ .type = PFM_PMU_TYPE_UNCORE, \ .num_cntrs = 4, \ .num_fixed_cntrs = 1, \ .max_encoding = 1, \ .pe = intel_bdx_unc_m_pe, \ .atdesc = snbep_unc_mods, \ .flags = PFMLIB_PMU_FL_RAW_UMASK, \ .pmu_detect = pfm_intel_bdx_unc_detect, \ .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding, \ PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding), \ PFMLIB_OS_DETECT(pfm_intel_x86_perf_detect), \ .get_event_first = pfm_intel_x86_get_event_first, \ .get_event_next = pfm_intel_x86_get_event_next, \ .event_is_valid = pfm_intel_x86_event_is_valid, \ .validate_table = pfm_intel_x86_validate_table, \ .get_event_info = pfm_intel_x86_get_event_info, \ .get_event_attr_info = pfm_intel_x86_get_event_attr_info, \ PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs), \ .get_event_nattrs = pfm_intel_x86_get_event_nattrs, \ }; DEFINE_IMC_BOX(0); DEFINE_IMC_BOX(1); DEFINE_IMC_BOX(2); DEFINE_IMC_BOX(3); DEFINE_IMC_BOX(4); DEFINE_IMC_BOX(5); DEFINE_IMC_BOX(6); DEFINE_IMC_BOX(7); libpfm-4.9.0/lib/pfmlib_intel_core.c0000664000175000017500000000535113223402656017210 0ustar eranianeranian/* * pfmlib_intel_core.c : Intel Core PMU * * Copyright (c) 2009 Google, Inc * Contributed by Stephane Eranian * * Based on: * Copyright (c) 2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * Core PMU = architectural perfmon v2 + PEBS */ /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_intel_x86_priv.h" #include "events/intel_core_events.h" static const int core_models[] = { 15, /* Merom */ 23, /* Penryn */ 29, /* Dunnington */ 0 }; static int pfm_core_init(void *this) { pfm_intel_x86_cfg.arch_version = 2; return PFM_SUCCESS; } pfmlib_pmu_t intel_core_support={ .desc = "Intel Core", .name = "core", .pmu = PFM_PMU_INTEL_CORE, .pme_count = LIBPFM_ARRAY_SIZE(intel_core_pe), .type = PFM_PMU_TYPE_CORE, .num_cntrs = 2, .num_fixed_cntrs = 3, .max_encoding = 1, .supported_plm = INTEL_X86_PLM, .pe = intel_core_pe, .atdesc = intel_x86_mods, .flags = PFMLIB_PMU_FL_RAW_UMASK | INTEL_X86_PMU_FL_ECMASK, .cpu_family = 6, .cpu_models = core_models, .pmu_detect = pfm_intel_x86_model_detect, .pmu_init = pfm_core_init, .get_event_encoding[PFM_OS_NONE] = pfm_intel_x86_get_encoding, PFMLIB_ENCODE_PERF(pfm_intel_x86_get_perf_encoding), .get_event_first = pfm_intel_x86_get_event_first, .get_event_next = pfm_intel_x86_get_event_next, .event_is_valid = pfm_intel_x86_event_is_valid, .validate_table = pfm_intel_x86_validate_table, .get_event_info = pfm_intel_x86_get_event_info, .get_event_attr_info = pfm_intel_x86_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_intel_x86_perf_validate_pattrs), .get_event_nattrs = pfm_intel_x86_get_event_nattrs, }; libpfm-4.9.0/lib/pfmlib_intel_snb.c0000664000175000017500000000762313223402656017046 0ustar eranianeranian/* * pfmlib_intel_snb.c : Intel Sandy Bridge core PMU * * Copyright (c) 2010 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_intel_x86_priv.h" #include "events/intel_snb_events.h" static const int snb_models[] = { 42, /* Sandy Bridge (Core i7 26xx, 25xx) */ 0 }; static const int snb_ep_models[] = { 45, /* Sandy Bridge EP */ 0 }; static int pfm_snb_init(void *this) { pfm_intel_x86_cfg.arch_version = 3; return PFM_SUCCESS; } pfmlib_pmu_t intel_snb_support={ .desc = "Intel Sandy Bridge", .name = "snb", .pmu = PFM_PMU_INTEL_SNB, .pme_count = LIBPFM_ARRAY_SIZE(intel_snb_pe), .type = PFM_PMU_TYPE_CORE, .supported_plm = INTEL_X86_PLM, .num_cntrs = 8, /* consider with HT off by default */ .num_fixed_cntrs = 3, .max_encoding = 2, /* offcore_response */ .pe = intel_snb_pe, .atdesc = intel_x86_mods, .flags = PFMLIB_PMU_FL_RAW_UMASK | INTEL_X86_PMU_FL_ECMASK, .cpu_family = 6, .cpu_models = snb_models, .pmu_detect = pfm_intel_x86_model_detect, .pmu_init = pfm_snb_init, .get_event_encoding[PFM_OS_NONE] = pfm_intel_x86_get_encoding, PFMLIB_ENCODE_PERF(pfm_intel_x86_get_perf_encoding), .get_event_first = pfm_intel_x86_get_event_first, .get_event_next = pfm_intel_x86_get_event_next, .event_is_valid = pfm_intel_x86_event_is_valid, .validate_table = pfm_intel_x86_validate_table, .get_event_info = pfm_intel_x86_get_event_info, .get_event_attr_info = pfm_intel_x86_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_intel_x86_perf_validate_pattrs), .get_event_nattrs = pfm_intel_x86_get_event_nattrs, .can_auto_encode = pfm_intel_x86_can_auto_encode, }; pfmlib_pmu_t intel_snb_ep_support={ .desc = "Intel Sandy Bridge EP", .name = "snb_ep", .pmu = PFM_PMU_INTEL_SNB_EP, .pme_count = LIBPFM_ARRAY_SIZE(intel_snb_pe), .type = PFM_PMU_TYPE_CORE, .supported_plm = INTEL_X86_PLM, .num_cntrs = 8, /* consider with HT off by default */ .num_fixed_cntrs = 3, .max_encoding = 2, /* offcore_response */ .pe = intel_snb_pe, .atdesc = intel_x86_mods, .flags = PFMLIB_PMU_FL_RAW_UMASK | INTEL_X86_PMU_FL_ECMASK, .cpu_family = 6, .cpu_models = snb_ep_models, .pmu_detect = pfm_intel_x86_model_detect, .pmu_init = pfm_snb_init, .get_event_encoding[PFM_OS_NONE] = pfm_intel_x86_get_encoding, PFMLIB_ENCODE_PERF(pfm_intel_x86_get_perf_encoding), .get_event_first = pfm_intel_x86_get_event_first, .get_event_next = pfm_intel_x86_get_event_next, .event_is_valid = pfm_intel_x86_event_is_valid, .validate_table = pfm_intel_x86_validate_table, .get_event_info = pfm_intel_x86_get_event_info, .get_event_attr_info = pfm_intel_x86_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_intel_x86_perf_validate_pattrs), .get_event_nattrs = pfm_intel_x86_get_event_nattrs, .can_auto_encode = pfm_intel_x86_can_auto_encode, }; libpfm-4.9.0/lib/pfmlib_mips.c0000664000175000017500000002143513223402656016036 0ustar eranianeranian/* * pfmlib_mips.c : support for MIPS chips * * Copyright (c) 2011 Samara Technology Group, Inc * Contributed by Philip Mucci * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ #include #include #include #include #include /* private headers */ #include "pfmlib_priv.h" /* library private */ #include "pfmlib_mips_priv.h" pfm_mips_config_t pfm_mips_cfg; static const pfmlib_attr_desc_t mips_mods[]={ PFM_ATTR_B("k", "monitor at system level"), PFM_ATTR_B("u", "monitor at user level"), PFM_ATTR_B("s", "monitor at supervisor level"), PFM_ATTR_B("e", "monitor at exception level "), PFM_ATTR_NULL /* end-marker to avoid exporting number of entries */ }; #ifdef CONFIG_PFMLIB_OS_LINUX /* * helper function to retrieve one value from /proc/cpuinfo * for internal libpfm use only * attr: the attribute (line) to look for * ret_buf: a buffer to store the value of the attribute (as a string) * maxlen : number of bytes of capacity in ret_buf * * ret_buf is null terminated. * * Return: * 0 : attribute found, ret_buf populated * -1: attribute not found */ static int pfmlib_getcpuinfo_attr(const char *attr, char *ret_buf, size_t maxlen) { FILE *fp = NULL; int ret = -1; size_t attr_len, buf_len = 0; char *p, *value = NULL; char *buffer = NULL; if (attr == NULL || ret_buf == NULL || maxlen < 1) return -1; attr_len = strlen(attr); fp = fopen("/proc/cpuinfo", "r"); if (fp == NULL) return -1; while(pfmlib_getl(&buffer, &buf_len, fp) != -1){ /* skip blank lines */ if (*buffer == '\n') continue; p = strchr(buffer, ':'); if (p == NULL) goto error; /* * p+2: +1 = space, +2= firt character * strlen()-1 gets rid of \n */ *p = '\0'; value = p+2; value[strlen(value)-1] = '\0'; if (!strncmp(attr, buffer, attr_len)) break; } strncpy(ret_buf, value, maxlen-1); ret_buf[maxlen-1] = '\0'; ret = 0; error: free(buffer); fclose(fp); return ret; } #else static int pfmlib_getcpuinfo_attr(const char *attr, char *ret_buf, size_t maxlen) { DPRINT("/proc/cpuinfo ignored\n"); } #endif static void pfm_mips_display_reg(pfm_mips_sel_reg_t reg, uint64_t cntrs, char *fstr) { __pfm_vbprintf("[0x%"PRIx64" mask=0x%x usr=%d sys=%d sup=%d int=%d cntrs=0x%"PRIx64"] %s\n", reg.val, reg.perfsel64.sel_event_mask, reg.perfsel64.sel_usr, reg.perfsel64.sel_os, reg.perfsel64.sel_sup, reg.perfsel64.sel_exl, cntrs, fstr); } int pfm_mips_detect(void *this) { int ret; char buffer[1024]; DPRINT("mips_detect\n"); ret = pfmlib_getcpuinfo_attr("cpu model", buffer, sizeof(buffer)); if (ret == -1) return PFM_ERR_NOTSUPP; if (strstr(buffer,"MIPS") == NULL) return PFM_ERR_NOTSUPP; strncpy(pfm_mips_cfg.model,buffer,strlen(buffer)); /* ret = pfmlib_getcpuinfo_attr("CPU implementer", buffer, sizeof(buffer)); if (ret == -1) return PFM_ERR_NOTSUPP; pfm_mips_cfg.implementer = strtol(buffer, NULL, 16); ret = pfmlib_getcpuinfo_attr("CPU part", buffer, sizeof(buffer)); if (ret == -1) return PFM_ERR_NOTSUPP; pfm_mips_cfg.part = strtol(buffer, NULL, 16); ret = pfmlib_getcpuinfo_attr("CPU architecture", buffer, sizeof(buffer)); if (ret == -1) return PFM_ERR_NOTSUPP; pfm_mips_cfg.architecture = strtol(buffer, NULL, 16); */ return PFM_SUCCESS; } int pfm_mips_get_encoding(void *this, pfmlib_event_desc_t *e) { pfmlib_pmu_t *pmu = this; const mips_entry_t *pe = this_pe(this); pfmlib_event_attr_info_t *a; pfm_mips_sel_reg_t reg; uint64_t ival, cntmask = 0; int plmmsk = 0, code; int k, id; reg.val = 0; code = pe[e->event].code; /* truncates bit 7 (counter info) */ reg.perfsel64.sel_event_mask = code; for (k = 0; k < e->nattrs; k++) { a = attr(e, k); if (a->ctrl != PFM_ATTR_CTRL_PMU) continue; ival = e->attrs[k].ival; switch(a->idx) { case MIPS_ATTR_K: /* os */ reg.perfsel64.sel_os = !!ival; plmmsk |= _MIPS_ATTR_K; break; case MIPS_ATTR_U: /* user */ reg.perfsel64.sel_usr = !!ival; plmmsk |= _MIPS_ATTR_U; break; case MIPS_ATTR_S: /* supervisor */ reg.perfsel64.sel_sup = !!ival; plmmsk |= _MIPS_ATTR_S; break; case MIPS_ATTR_E: /* int */ reg.perfsel64.sel_exl = !!ival; plmmsk |= _MIPS_ATTR_E; } } /* * handle case where no priv level mask was passed. * then we use the dfl_plm */ if (!(plmmsk & MIPS_PLM_ALL)) { if (e->dfl_plm & PFM_PLM0) reg.perfsel64.sel_os = 1; if (e->dfl_plm & PFM_PLM1) reg.perfsel64.sel_sup = 1; if (e->dfl_plm & PFM_PLM2) reg.perfsel64.sel_exl = 1; if (e->dfl_plm & PFM_PLM3) reg.perfsel64.sel_usr = 1; } evt_strcat(e->fstr, "%s", pe[e->event].name); for (k = 0; k < e->npattrs; k++) { if (e->pattrs[k].ctrl != PFM_ATTR_CTRL_PMU) continue; id = e->pattrs[k].idx; switch(id) { case MIPS_ATTR_K: evt_strcat(e->fstr, ":%s=%lu", mips_mods[id].name, reg.perfsel64.sel_os); break; case MIPS_ATTR_U: evt_strcat(e->fstr, ":%s=%lu", mips_mods[id].name, reg.perfsel64.sel_usr); break; case MIPS_ATTR_S: evt_strcat(e->fstr, ":%s=%lu", mips_mods[id].name, reg.perfsel64.sel_sup); break; case MIPS_ATTR_E: evt_strcat(e->fstr, ":%s=%lu", mips_mods[id].name, reg.perfsel64.sel_exl); break; } } e->codes[0] = reg.val; /* cycles and instructions support all counters */ if (code == 0 || code == 1) { cntmask = (1ULL << pmu->num_cntrs) -1; } else { /* event work on odd counters only */ for (k = !!(code & 0x80) ; k < pmu->num_cntrs; k+=2) { cntmask |= 1ULL << k; } } e->codes[1] = cntmask; e->count = 2; pfm_mips_display_reg(reg, cntmask, e->fstr); return PFM_SUCCESS; } int pfm_mips_get_event_first(void *this) { return 0; } int pfm_mips_get_event_next(void *this, int idx) { pfmlib_pmu_t *p = this; if (idx >= (p->pme_count-1)) return -1; return idx+1; } int pfm_mips_event_is_valid(void *this, int pidx) { pfmlib_pmu_t *p = this; return pidx >= 0 && pidx < p->pme_count; } int pfm_mips_validate_table(void *this, FILE *fp) { pfmlib_pmu_t *pmu = this; const mips_entry_t *pe = this_pe(this); int i, j, error = 0; for(i=0; i < pmu->pme_count; i++) { if (!pe[i].name) { fprintf(fp, "pmu: %s event%d: :: no name (prev event was %s)\n", pmu->name, i, i > 1 ? pe[i-1].name : "??"); error++; } if (!pe[i].desc) { fprintf(fp, "pmu: %s event%d: %s :: no description\n", pmu->name, i, pe[i].name); error++; } for (j=i+1; j < pmu->pme_count; j++) { if (pe[i].code == pe[j].code) { fprintf(fp, "pmu: %s events %s and %s have the same code 0x%x\n", pmu->name, pe[i].name, pe[j].name, pe[i].code); error++; } } } if (!pmu->supported_plm) { fprintf(fp, "pmu: %s supported_plm=0, is that right?\n", pmu->name); error++; } return error ? PFM_ERR_INVAL : PFM_SUCCESS; } unsigned int pfm_mips_get_event_nattrs(void *this, int pidx) { /* assume all pmus have the same number of attributes */ return MIPS_NUM_ATTRS; } int pfm_mips_get_event_attr_info(void *this, int pidx, int attr_idx, pfmlib_event_attr_info_t *info) { /* no umasks, so all attrs are modifiers */ info->name = mips_mods[attr_idx].name; info->desc = mips_mods[attr_idx].desc; info->type = mips_mods[attr_idx].type; info->type = mips_mods[attr_idx].type; info->equiv= NULL; info->idx = attr_idx; /* private index */ info->code = attr_idx; info->is_dfl = 0; info->is_precise = 0; info->ctrl = PFM_ATTR_CTRL_PMU;; return PFM_SUCCESS; } int pfm_mips_get_event_info(void *this, int idx, pfm_event_info_t *info) { pfmlib_pmu_t *pmu = this; const mips_entry_t *pe = this_pe(this); info->name = pe[idx].name; info->desc = pe[idx].desc; info->code = pe[idx].code; info->equiv = NULL; info->idx = idx; /* private index */ info->pmu = pmu->pmu; info->is_precise = 0; /* no attributes defined for MIPS yet */ info->nattrs = pfm_mips_get_event_nattrs(this, idx); return PFM_SUCCESS; } libpfm-4.9.0/lib/pfmlib_intel_ivbep_unc_imc.c0000664000175000017500000000552513223402656021065 0ustar eranianeranian/* * pfmlib_intel_ivbep_unc_imc.c : Intel IvyBridge-EP Integrated Memory Controller (IMC) uncore PMU * * Copyright (c) 2014 Google Inc. All rights reserved * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_intel_x86_priv.h" #include "pfmlib_intel_snbep_unc_priv.h" #include "events/intel_ivbep_unc_imc_events.h" #define DEFINE_IMC_BOX(n) \ pfmlib_pmu_t intel_ivbep_unc_imc##n##_support = { \ .desc = "Intel Iyy Bridge-EP IMC"#n" uncore", \ .name = "ivbep_unc_imc"#n, \ .perf_name = "uncore_imc_"#n, \ .pmu = PFM_PMU_INTEL_IVBEP_UNC_IMC##n, \ .pme_count = LIBPFM_ARRAY_SIZE(intel_ivbep_unc_m_pe), \ .type = PFM_PMU_TYPE_UNCORE, \ .num_cntrs = 4, \ .num_fixed_cntrs = 1, \ .max_encoding = 1, \ .pe = intel_ivbep_unc_m_pe, \ .atdesc = snbep_unc_mods, \ .flags = PFMLIB_PMU_FL_RAW_UMASK, \ .pmu_detect = pfm_intel_ivbep_unc_detect, \ .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding, \ PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding), \ PFMLIB_OS_DETECT(pfm_intel_x86_perf_detect), \ .get_event_first = pfm_intel_x86_get_event_first, \ .get_event_next = pfm_intel_x86_get_event_next, \ .event_is_valid = pfm_intel_x86_event_is_valid, \ .validate_table = pfm_intel_x86_validate_table, \ .get_event_info = pfm_intel_x86_get_event_info, \ .get_event_attr_info = pfm_intel_x86_get_event_attr_info, \ PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs), \ .get_event_nattrs = pfm_intel_x86_get_event_nattrs, \ }; DEFINE_IMC_BOX(0); DEFINE_IMC_BOX(1); DEFINE_IMC_BOX(2); DEFINE_IMC_BOX(3); DEFINE_IMC_BOX(4); DEFINE_IMC_BOX(5); DEFINE_IMC_BOX(6); DEFINE_IMC_BOX(7); libpfm-4.9.0/lib/pfmlib_intel_p6.c0000664000175000017500000001404013223402656016600 0ustar eranianeranian/* * pfmlib_i386_p6.c : support for the P6 processor family (family=6) * incl. Pentium II, Pentium III, Pentium Pro, Pentium M * * Copyright (c) 2005-2007 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ /* private headers */ #include "pfmlib_priv.h" /* library private */ #include "pfmlib_intel_x86_priv.h" /* architecture private */ #include "events/intel_p6_events.h" /* generic P6 (PIII) */ #include "events/intel_pii_events.h" /* Pentium II */ #include "events/intel_ppro_events.h" /* Pentium Pro */ #include "events/intel_pm_events.h" /* Pentium M */ static const int pii_models[] = { 3, /* Pentium II */ 5, /* Pentium II Deschutes */ 6, /* Pentium II Mendocino */ 0 }; static const int ppro_models[] = { 1, /* Pentium Pro */ 0 }; static const int piii_models[] = { 7, /* Pentium III Katmai */ 8, /* Pentium III Coppermine */ 10,/* Pentium III Cascades */ 11,/* Pentium III Tualatin */ 0 }; static const int pm_models[] = { 9, /* Pentium M */ 13, /* Pentium III Coppermine */ 0 }; /* Pentium II support */ pfmlib_pmu_t intel_pii_support={ .desc = "Intel Pentium II", .name = "pii", .pmu = PFM_PMU_INTEL_PII, .pme_count = LIBPFM_ARRAY_SIZE(intel_pii_pe), .pe = intel_pii_pe, .atdesc = intel_x86_mods, .flags = PFMLIB_PMU_FL_RAW_UMASK, .type = PFM_PMU_TYPE_CORE, .supported_plm = INTEL_X86_PLM, .cpu_family = 6, .cpu_models = pii_models, .pmu_detect = pfm_intel_x86_model_detect, .num_cntrs = 2, .max_encoding = 1, .get_event_encoding[PFM_OS_NONE] = pfm_intel_x86_get_encoding, PFMLIB_ENCODE_PERF(pfm_intel_x86_get_perf_encoding), .get_event_first = pfm_intel_x86_get_event_first, .get_event_next = pfm_intel_x86_get_event_next, .event_is_valid = pfm_intel_x86_event_is_valid, .validate_table = pfm_intel_x86_validate_table, .get_event_info = pfm_intel_x86_get_event_info, .get_event_attr_info = pfm_intel_x86_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_intel_x86_perf_validate_pattrs), .get_event_nattrs = pfm_intel_x86_get_event_nattrs, }; pfmlib_pmu_t intel_p6_support={ .desc = "Intel P6 Processor Family", .name = "p6", .pmu = PFM_PMU_I386_P6, .pme_count = LIBPFM_ARRAY_SIZE(intel_p6_pe), .pe = intel_p6_pe, .atdesc = intel_x86_mods, .flags = PFMLIB_PMU_FL_RAW_UMASK, .type = PFM_PMU_TYPE_CORE, .supported_plm = INTEL_X86_PLM, .cpu_family = 6, .cpu_models = piii_models, .pmu_detect = pfm_intel_x86_model_detect, .num_cntrs = 2, .max_encoding = 1, .get_event_encoding[PFM_OS_NONE] = pfm_intel_x86_get_encoding, PFMLIB_ENCODE_PERF(pfm_intel_x86_get_perf_encoding), .get_event_first = pfm_intel_x86_get_event_first, .get_event_next = pfm_intel_x86_get_event_next, .event_is_valid = pfm_intel_x86_event_is_valid, .validate_table = pfm_intel_x86_validate_table, .get_event_info = pfm_intel_x86_get_event_info, .get_event_attr_info = pfm_intel_x86_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_intel_x86_perf_validate_pattrs), .get_event_nattrs = pfm_intel_x86_get_event_nattrs, }; pfmlib_pmu_t intel_ppro_support={ .desc = "Intel Pentium Pro", .name = "ppro", .pmu = PFM_PMU_INTEL_PPRO, .pme_count = LIBPFM_ARRAY_SIZE(intel_ppro_pe), .pe = intel_ppro_pe, .atdesc = intel_x86_mods, .flags = PFMLIB_PMU_FL_RAW_UMASK, .type = PFM_PMU_TYPE_CORE, .supported_plm = INTEL_X86_PLM, .cpu_family = 6, .cpu_models = ppro_models, .pmu_detect = pfm_intel_x86_model_detect, .num_cntrs = 2, .max_encoding = 1, .get_event_encoding[PFM_OS_NONE] = pfm_intel_x86_get_encoding, PFMLIB_ENCODE_PERF(pfm_intel_x86_get_perf_encoding), .get_event_first = pfm_intel_x86_get_event_first, .get_event_next = pfm_intel_x86_get_event_next, .event_is_valid = pfm_intel_x86_event_is_valid, .validate_table = pfm_intel_x86_validate_table, .get_event_info = pfm_intel_x86_get_event_info, .get_event_attr_info = pfm_intel_x86_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_intel_x86_perf_validate_pattrs), .get_event_nattrs = pfm_intel_x86_get_event_nattrs, }; /* Pentium M support */ pfmlib_pmu_t intel_pm_support={ .desc = "Intel Pentium M", .name = "pm", .pmu = PFM_PMU_I386_PM, .pe = intel_pm_pe, .atdesc = intel_x86_mods, .flags = PFMLIB_PMU_FL_RAW_UMASK, .supported_plm = INTEL_X86_PLM, .cpu_family = 6, .cpu_models = pm_models, .pmu_detect = pfm_intel_x86_model_detect, .pme_count = LIBPFM_ARRAY_SIZE(intel_pm_pe), .type = PFM_PMU_TYPE_CORE, .num_cntrs = 2, .max_encoding = 1, .get_event_encoding[PFM_OS_NONE] = pfm_intel_x86_get_encoding, PFMLIB_ENCODE_PERF(pfm_intel_x86_get_perf_encoding), .get_event_first = pfm_intel_x86_get_event_first, .get_event_next = pfm_intel_x86_get_event_next, .event_is_valid = pfm_intel_x86_event_is_valid, .validate_table = pfm_intel_x86_validate_table, .get_event_info = pfm_intel_x86_get_event_info, .get_event_attr_info = pfm_intel_x86_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_intel_x86_perf_validate_pattrs), .get_event_nattrs = pfm_intel_x86_get_event_nattrs, }; libpfm-4.9.0/lib/pfmlib_intel_bdx_unc_irp.c0000664000175000017500000000573113223402656020556 0ustar eranianeranian/* * pfmlib_intel_bdx_irp.c : Intel BroadwellX IRP uncore PMU * * Copyright (c) 2017 Google Inc. All rights reserved * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_intel_x86_priv.h" #include "pfmlib_intel_snbep_unc_priv.h" #include "events/intel_bdx_unc_irp_events.h" static void display_irp(void *this, pfmlib_event_desc_t *e, void *val) { const intel_x86_entry_t *pe = this_pe(this); pfm_snbep_unc_reg_t *reg = val; __pfm_vbprintf("[UNC_IRP=0x%"PRIx64" event=0x%x umask=0x%x en=%d " "edge=%d thres=%d] %s\n", reg->val, reg->irp.unc_event, reg->irp.unc_umask, reg->irp.unc_en, reg->irp.unc_edge, reg->irp.unc_thres, pe[e->event].name); } pfmlib_pmu_t intel_bdx_unc_irp_support = { .desc = "Intel BroadwellX IRP uncore", .name = "bdx_unc_irp", .perf_name = "uncore_irp", .pmu = PFM_PMU_INTEL_BDX_UNC_IRP, .pme_count = LIBPFM_ARRAY_SIZE(intel_bdx_unc_i_pe), .type = PFM_PMU_TYPE_UNCORE, .num_cntrs = 4, .num_fixed_cntrs = 0, .max_encoding = 3, .pe = intel_bdx_unc_i_pe, .atdesc = snbep_unc_mods, .flags = PFMLIB_PMU_FL_RAW_UMASK, .pmu_detect = pfm_intel_bdx_unc_detect, .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding, PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding), PFMLIB_OS_DETECT(pfm_intel_x86_perf_detect), .get_event_first = pfm_intel_x86_get_event_first, .get_event_next = pfm_intel_x86_get_event_next, .event_is_valid = pfm_intel_x86_event_is_valid, .validate_table = pfm_intel_x86_validate_table, .get_event_info = pfm_intel_x86_get_event_info, .get_event_attr_info = pfm_intel_x86_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs), .get_event_nattrs = pfm_intel_x86_get_event_nattrs, .display_reg = display_irp, }; libpfm-4.9.0/lib/pfmlib_s390x_perf_event.c0000664000175000017500000000351413223402656020167 0ustar eranianeranian/* * perf_event for Linux on IBM System z * * Copyright IBM Corp. 2012 * Contributed by Hendrik Brueckner * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include /* private library and arch headers */ #include "pfmlib_priv.h" #include "pfmlib_s390x_priv.h" #include "pfmlib_perf_event_priv.h" int pfm_s390x_get_perf_encoding(void *this, pfmlib_event_desc_t *e) { pfmlib_pmu_t *pmu = this; struct perf_event_attr *attr = e->os_data; int rc; if (!pmu->get_event_encoding[PFM_OS_NONE]) return PFM_ERR_NOTSUPP; /* set up raw pmu event encoding */ rc = pmu->get_event_encoding[PFM_OS_NONE](this, e); if (rc == PFM_SUCCESS) { /* currently use raw events only */ attr->type = PERF_TYPE_RAW; attr->config = e->codes[0]; } return rc; } libpfm-4.9.0/lib/pfmlib_powerpc.c0000664000175000017500000000612413223402656016543 0ustar eranianeranian/* * Copyright (C) IBM Corporation, 2009. All rights reserved. * Contributed by Corey Ashford (cjashfor@us.ibm.com) * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * * pfmlib_gen_powerpc.c * * Support for libpfm4 for the PowerPC 970, 970MP, Power4,4+,5,5+,6,7 processors. */ #include #include /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_power_priv.h" int pfm_gen_powerpc_get_event_info(void *this, int pidx, pfm_event_info_t *info) { pfmlib_pmu_t *pmu = this; const pme_power_entry_t *pe = this_pe(this); /* * pmu and idx filled out by caller */ info->name = pe[pidx].pme_name; info->desc = pe[pidx].pme_long_desc; info->code = pe[pidx].pme_code; info->equiv = NULL; info->idx = pidx; /* private index */ info->pmu = pmu->pmu; info->is_precise = 0; info->nattrs = 0; return PFM_SUCCESS; } int pfm_gen_powerpc_get_event_attr_info(void *this, int pidx, int umask_idx, pfmlib_event_attr_info_t *info) { /* No attributes are supported */ return PFM_ERR_ATTR; } int pfm_gen_powerpc_get_encoding(void *this, pfmlib_event_desc_t *e) { const pme_power_entry_t *pe = this_pe(this); e->count = 1; e->codes[0] = (uint64_t)pe[e->event].pme_code; evt_strcat(e->fstr, "%s", pe[e->event].pme_name); return PFM_SUCCESS; } int pfm_gen_powerpc_get_event_first(void *this) { return 0; } int pfm_gen_powerpc_get_event_next(void *this, int idx) { pfmlib_pmu_t *p = this; if (idx >= (p->pme_count-1)) return -1; return idx+1; } int pfm_gen_powerpc_event_is_valid(void *this, int pidx) { pfmlib_pmu_t *p = this; return pidx >= 0 && pidx < p->pme_count; } int pfm_gen_powerpc_validate_table(void *this, FILE *fp) { pfmlib_pmu_t *pmu = this; const pme_power_entry_t *pe = this_pe(this); int i; int ret = PFM_ERR_INVAL; for(i=0; i < pmu->pme_count; i++) { if (!pe[i].pme_name) { fprintf(fp, "pmu: %s event%d: :: no name\n", pmu->name, i); goto error; } if (!pe[i].pme_long_desc) { fprintf(fp, "pmu: %s event%d: %s :: no description\n", pmu->name, i, pe[i].pme_name); goto error; } } ret = PFM_SUCCESS; error: return ret; } libpfm-4.9.0/lib/pfmlib_intel_hsw.c0000664000175000017500000000761013223402656017061 0ustar eranianeranian/* * pfmlib_intel_hsw.c : Intel Haswell core PMU * * Copyright (c) 2012 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_intel_x86_priv.h" #include "events/intel_hsw_events.h" static const int hsw_models[] = { 60, /* Haswell */ 69, /* Haswell */ 70, /* Haswell */ 0 }; static const int hsw_ep_models[] = { 63, /* Haswell */ 0 }; static int pfm_hsw_init(void *this) { pfm_intel_x86_cfg.arch_version = 4; return PFM_SUCCESS; } pfmlib_pmu_t intel_hsw_support={ .desc = "Intel Haswell", .name = "hsw", .pmu = PFM_PMU_INTEL_HSW, .pme_count = LIBPFM_ARRAY_SIZE(intel_hsw_pe), .type = PFM_PMU_TYPE_CORE, .supported_plm = INTEL_X86_PLM, .num_cntrs = 8, /* consider with HT off by default */ .num_fixed_cntrs = 3, .max_encoding = 2, /* offcore_response */ .pe = intel_hsw_pe, .atdesc = intel_x86_mods, .flags = PFMLIB_PMU_FL_RAW_UMASK | INTEL_X86_PMU_FL_ECMASK, .cpu_family = 6, .cpu_models = hsw_models, .pmu_detect = pfm_intel_x86_model_detect, .pmu_init = pfm_hsw_init, .get_event_encoding[PFM_OS_NONE] = pfm_intel_x86_get_encoding, PFMLIB_ENCODE_PERF(pfm_intel_x86_get_perf_encoding), .get_event_first = pfm_intel_x86_get_event_first, .get_event_next = pfm_intel_x86_get_event_next, .event_is_valid = pfm_intel_x86_event_is_valid, .validate_table = pfm_intel_x86_validate_table, .get_event_info = pfm_intel_x86_get_event_info, .get_event_attr_info = pfm_intel_x86_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_intel_x86_perf_validate_pattrs), .get_event_nattrs = pfm_intel_x86_get_event_nattrs, .can_auto_encode = pfm_intel_x86_can_auto_encode, }; pfmlib_pmu_t intel_hsw_ep_support={ .desc = "Intel Haswell EP", .name = "hsw_ep", .pmu = PFM_PMU_INTEL_HSW_EP, .pme_count = LIBPFM_ARRAY_SIZE(intel_hsw_pe), .type = PFM_PMU_TYPE_CORE, .supported_plm = INTEL_X86_PLM, .num_cntrs = 8, /* consider with HT off by default */ .num_fixed_cntrs = 3, .max_encoding = 2, /* offcore_response */ .pe = intel_hsw_pe, .atdesc = intel_x86_mods, .flags = PFMLIB_PMU_FL_RAW_UMASK | INTEL_X86_PMU_FL_ECMASK, .cpu_family = 6, .cpu_models = hsw_ep_models, .pmu_detect = pfm_intel_x86_model_detect, .pmu_init = pfm_hsw_init, .get_event_encoding[PFM_OS_NONE] = pfm_intel_x86_get_encoding, PFMLIB_ENCODE_PERF(pfm_intel_x86_get_perf_encoding), .get_event_first = pfm_intel_x86_get_event_first, .get_event_next = pfm_intel_x86_get_event_next, .event_is_valid = pfm_intel_x86_event_is_valid, .validate_table = pfm_intel_x86_validate_table, .get_event_info = pfm_intel_x86_get_event_info, .get_event_attr_info = pfm_intel_x86_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_intel_x86_perf_validate_pattrs), .get_event_nattrs = pfm_intel_x86_get_event_nattrs, .can_auto_encode = pfm_intel_x86_can_auto_encode, }; libpfm-4.9.0/lib/pfmlib_amd64_perf_event.c0000664000175000017500000001005013223402656020205 0ustar eranianeranian/* * pfmlib_amd64_perf_event.c : perf_event AMD64 functions * * Copyright (c) 2011 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include /* private headers */ #include "pfmlib_priv.h" /* library private */ #include "pfmlib_amd64_priv.h" /* architecture private */ #include "pfmlib_perf_event_priv.h" static int find_pmu_type_by_name(const char *name) { char filename[PATH_MAX]; FILE *fp; int ret, type; if (!name) return PFM_ERR_NOTSUPP; sprintf(filename, "/sys/bus/event_source/devices/%s/type", name); fp = fopen(filename, "r"); if (!fp) return PFM_ERR_NOTSUPP; ret = fscanf(fp, "%d", &type); if (ret != 1) type = PFM_ERR_NOTSUPP; fclose(fp); return type; } int pfm_amd64_get_perf_encoding(void *this, pfmlib_event_desc_t *e) { pfmlib_pmu_t *pmu = this; struct perf_event_attr *attr = e->os_data; int ret; if (!pmu->get_event_encoding[PFM_OS_NONE]) return PFM_ERR_NOTSUPP; /* * use generic raw encoding function first */ ret = pmu->get_event_encoding[PFM_OS_NONE](this, e); if (ret != PFM_SUCCESS) return ret; if (e->count > 1) { DPRINT("%s: unsupported count=%d\n", e->count); return PFM_ERR_NOTSUPP; } ret = PERF_TYPE_RAW; /* * if specific perf PMU is provided then try to locate it * otherwise assume core PMU and thus type RAW */ if (pmu->perf_name) { /* greab PMU type from sysfs */ ret = find_pmu_type_by_name(pmu->perf_name); if (ret < 0) return ret; } DPRINT("amd64_get_perf_encoding: PMU type=%d\n", ret); attr->type = ret; attr->config = e->codes[0]; return PFM_SUCCESS; } void pfm_amd64_perf_validate_pattrs(void *this, pfmlib_event_desc_t *e) { pfmlib_pmu_t *pmu = this; int i, compact; for (i=0; i < e->npattrs; i++) { compact = 0; /* umasks never conflict */ if (e->pattrs[i].type == PFM_ATTR_UMASK) continue; /* * with perf_events, u and k are handled at the OS level * via attr.exclude_* fields */ if (e->pattrs[i].ctrl == PFM_ATTR_CTRL_PMU) { if (e->pattrs[i].idx == AMD64_ATTR_U || e->pattrs[i].idx == AMD64_ATTR_K || e->pattrs[i].idx == AMD64_ATTR_H) compact = 1; } if (e->pattrs[i].ctrl == PFM_ATTR_CTRL_PERF_EVENT) { /* No precise mode on AMD */ if (e->pattrs[i].idx == PERF_ATTR_PR) compact = 1; /* older processors do not support hypervisor priv level */ if (!IS_FAMILY_10H(pmu) && e->pattrs[i].idx == PERF_ATTR_H) compact = 1; } if (compact) { pfmlib_compact_pattrs(e, i); i--; } } } void pfm_amd64_nb_perf_validate_pattrs(void *this, pfmlib_event_desc_t *e) { int i, compact; for (i=0; i < e->npattrs; i++) { compact = 0; /* umasks never conflict */ if (e->pattrs[i].type == PFM_ATTR_UMASK) continue; /* * no perf_events attr is supported by AMD64 Northbridge PMU * sampling is not supported */ if (e->pattrs[i].ctrl == PFM_ATTR_CTRL_PERF_EVENT) { compact = 1; } if (compact) { pfmlib_compact_pattrs(e, i); i--; } } } libpfm-4.9.0/lib/pfmlib_intel_nhm.c0000664000175000017500000001436113223402656017043 0ustar eranianeranian/* * pfmlib_intel_nhm.c : Intel Nehalem core PMU * * Copyright (c) 2008 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * Nehalem PMU = architectural perfmon v3 + OFFCORE + PEBS v2 + LBR */ /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_intel_x86_priv.h" #if 0 static int pfm_nhm_lbr_encode(void *this, pfmlib_event_desc_t *e, uint64_t *codes, int *count, pfmlib_perf_attr_t *attrs); static int pfm_nhm_offcore_encode(void *this, pfmlib_event_desc_t *e, uint64_t *codes, int *count, pfmlib_perf_attr_t *attrs); #endif #include "events/intel_nhm_events.h" static const int nhm_models[] = { 26, 30, 31, 0 }; static const int nhm_ex_models[] = { 46, 0 }; static int pfm_nhm_init(void *this) { pfm_intel_x86_cfg.arch_version = 3; return PFM_SUCCESS; } /* * the following function implement the model * specific API directly available to user */ static const char *data_src_encodings[]={ /* 0 */ "unknown L3 cache miss", /* 1 */ "minimal latency core cache hit. Request was satisfied by L1 data cache", /* 2 */ "pending core cache HIT. Outstanding core cache miss to same cacheline address already underway", /* 3 */ "data request satisfied by the L2", /* 4 */ "L3 HIT. Local or remote home request that hit L3 in the uncore with no coherency actions required (snooping)", /* 5 */ "L3 HIT. Local or remote home request that hit L3 and was serviced by another core with a cross core snoop where no modified copy was found (clean)", /* 6 */ "L3 HIT. Local or remote home request that hit L3 and was serviced by another core with a cross core snoop where modified copies were found (HITM)", /* 7 */ "reserved", /* 8 */ "L3 MISS. Local homed request that missed L3 and was serviced by forwarded data following a cross package snoop where no modified copy was found (remote home requests are not counted)", /* 9 */ "reserved", /* 10 */ "L3 MISS. Local homed request that missed L3 and was serviced by local DRAM (go to shared state)", /* 11 */ "L3 MISS. Remote homed request that missed L3 and was serviced by remote DRAM (go to shared state)", /* 12 */ "L3 MISS. Local homed request that missed L3 and was serviced by local DRAM (go to exclusive state)", /* 13 */ "L3 MISS. Remote homed request that missed L3 and was serviced by remote DRAM (go to exclusive state)", /* 14 */ "reserved", /* 15 */ "request to uncacheable memory" }; /* * return data source encoding based on index in val * To be used with PEBS load latency filtering to decode * source of the load miss */ const char * pfm_nhm_data_src_desc(int val) { if (val > 15 || val < 0) return NULL; return data_src_encodings[val]; } #if 0 static int pfm_nhm_lbr_encode(void *this, pfmlib_event_desc_t *e, uint64_t *codes, int *count, pfmlib_perf_attr_t *attrs) { return PFM_ERR_NOTSUPP; } static int pfm_nhm_offcore_encode(void *this, pfmlib_event_desc_t *e, uint64_t *codes, int *count, pfmlib_perf_attr_t *attrs) { return PFM_ERR_NOTSUPP; } #endif pfmlib_pmu_t intel_nhm_support={ .desc = "Intel Nehalem", .name = "nhm", .pmu = PFM_PMU_INTEL_NHM, .pme_count = LIBPFM_ARRAY_SIZE(intel_nhm_pe), .type = PFM_PMU_TYPE_CORE, .supported_plm = INTEL_X86_PLM, .num_cntrs = 4, .num_fixed_cntrs = 3, .max_encoding = 2, /* because of OFFCORE_RESPONSE */ .pe = intel_nhm_pe, .atdesc = intel_x86_mods, .flags = PFMLIB_PMU_FL_RAW_UMASK | INTEL_X86_PMU_FL_ECMASK, .cpu_family = 6, .cpu_models = nhm_models, .pmu_detect = pfm_intel_x86_model_detect, .pmu_init = pfm_nhm_init, .get_event_encoding[PFM_OS_NONE] = pfm_intel_x86_get_encoding, PFMLIB_ENCODE_PERF(pfm_intel_x86_get_perf_encoding), .get_event_first = pfm_intel_x86_get_event_first, .get_event_next = pfm_intel_x86_get_event_next, .event_is_valid = pfm_intel_x86_event_is_valid, .validate_table = pfm_intel_x86_validate_table, .get_event_info = pfm_intel_x86_get_event_info, .get_event_attr_info = pfm_intel_x86_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_intel_x86_perf_validate_pattrs), .get_event_nattrs = pfm_intel_x86_get_event_nattrs, .can_auto_encode = pfm_intel_x86_can_auto_encode, }; pfmlib_pmu_t intel_nhm_ex_support={ .desc = "Intel Nehalem EX", .name = "nhm_ex", .pmu = PFM_PMU_INTEL_NHM_EX, .pme_count = LIBPFM_ARRAY_SIZE(intel_nhm_pe), .type = PFM_PMU_TYPE_CORE, .supported_plm = INTEL_X86_PLM, .num_cntrs = 4, .num_fixed_cntrs = 3, .max_encoding = 2, /* because of OFFCORE_RESPONSE */ .pe = intel_nhm_pe, .atdesc = intel_x86_mods, .flags = PFMLIB_PMU_FL_RAW_UMASK | INTEL_X86_PMU_FL_ECMASK, .cpu_family = 6, .cpu_models = nhm_ex_models, .pmu_detect = pfm_intel_x86_model_detect, .pmu_init = pfm_nhm_init, .get_event_encoding[PFM_OS_NONE] = pfm_intel_x86_get_encoding, PFMLIB_ENCODE_PERF(pfm_intel_x86_get_perf_encoding), .get_event_first = pfm_intel_x86_get_event_first, .get_event_next = pfm_intel_x86_get_event_next, .event_is_valid = pfm_intel_x86_event_is_valid, .validate_table = pfm_intel_x86_validate_table, .get_event_info = pfm_intel_x86_get_event_info, .get_event_attr_info = pfm_intel_x86_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_intel_x86_perf_validate_pattrs), .get_event_nattrs = pfm_intel_x86_get_event_nattrs, .can_auto_encode = pfm_intel_x86_can_auto_encode, }; libpfm-4.9.0/lib/pfmlib_intel_bdx_unc_ha.c0000664000175000017500000000666013223402656020356 0ustar eranianeranian/* * pfmlib_intel_bdx_unc_ha.c : Intel BroadwellX Home Agent (HA) uncore PMU * * Copyright (c) 2017 Google Inc. All rights reserved * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_intel_x86_priv.h" #include "pfmlib_intel_snbep_unc_priv.h" #include "events/intel_bdx_unc_ha_events.h" static void display_ha(void *this, pfmlib_event_desc_t *e, void *val) { const intel_x86_entry_t *pe = this_pe(this); pfm_snbep_unc_reg_t *reg = val; pfm_snbep_unc_reg_t f; __pfm_vbprintf("[UNC_HA=0x%"PRIx64" event=0x%x umask=0x%x en=%d " "inv=%d edge=%d thres=%d] %s\n", reg->val, reg->com.unc_event, reg->com.unc_umask, reg->com.unc_en, reg->com.unc_inv, reg->com.unc_edge, reg->com.unc_thres, pe[e->event].name); if (e->count == 1) return; f.val = e->codes[1]; __pfm_vbprintf("[UNC_HA_ADDR=0x%"PRIx64" lo_addr=0x%x hi_addr=0x%x]\n", f.val, f.ha_addr.lo_addr, f.ha_addr.hi_addr); f.val = e->codes[2]; __pfm_vbprintf("[UNC_HA_OPC=0x%"PRIx64" opc=0x%x]\n", f.val, f.ha_opc.opc); } #define DEFINE_HA_BOX(n) \ pfmlib_pmu_t intel_bdx_unc_ha##n##_support = {\ .desc = "Intel BroadwellX HA "#n" uncore",\ .name = "bdx_unc_ha"#n,\ .perf_name = "uncore_ha_"#n,\ .pmu = PFM_PMU_INTEL_BDX_UNC_HA##n,\ .pme_count = LIBPFM_ARRAY_SIZE(intel_bdx_unc_h_pe),\ .type = PFM_PMU_TYPE_UNCORE,\ .num_cntrs = 4,\ .num_fixed_cntrs = 0,\ .max_encoding = 3, /* address matchers */\ .pe = intel_bdx_unc_h_pe,\ .atdesc = snbep_unc_mods,\ .flags = PFMLIB_PMU_FL_RAW_UMASK,\ .pmu_detect = pfm_intel_bdx_unc_detect,\ .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding,\ PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding),\ PFMLIB_OS_DETECT(pfm_intel_x86_perf_detect), \ .get_event_first = pfm_intel_x86_get_event_first,\ .get_event_next = pfm_intel_x86_get_event_next,\ .event_is_valid = pfm_intel_x86_event_is_valid,\ .validate_table = pfm_intel_x86_validate_table,\ .get_event_info = pfm_intel_x86_get_event_info,\ .get_event_attr_info = pfm_intel_x86_get_event_attr_info,\ PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs),\ .get_event_nattrs = pfm_intel_x86_get_event_nattrs,\ .display_reg = display_ha,\ } DEFINE_HA_BOX(0); DEFINE_HA_BOX(1); libpfm-4.9.0/lib/pfmlib_power8.c0000664000175000017500000000450713223402656016313 0ustar eranianeranian/* * pfmlib_power8.c : IBM Power8 support * * Copyright (C) IBM Corporation, 2013-2016. All rights reserved. * Contributed by Carl Love (carll@us.ibm.com) * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_power_priv.h" #include "events/power8_events.h" static int pfm_power8_detect(void* this) { if (__is_processor(PV_POWER8) || __is_processor(PV_POWER8E) || __is_processor(PV_POWER8NVL)) return PFM_SUCCESS; return PFM_ERR_NOTSUPP; } pfmlib_pmu_t power8_support={ .desc = "POWER8", .name = "power8", .pmu = PFM_PMU_POWER8, .pme_count = LIBPFM_ARRAY_SIZE(power8_pe), .type = PFM_PMU_TYPE_CORE, .supported_plm = POWER8_PLM, .num_cntrs = 4, .num_fixed_cntrs = 2, .max_encoding = 1, .pe = power8_pe, .pmu_detect = pfm_power8_detect, .get_event_encoding[PFM_OS_NONE] = pfm_gen_powerpc_get_encoding, PFMLIB_ENCODE_PERF(pfm_gen_powerpc_get_perf_encoding), PFMLIB_VALID_PERF_PATTRS(pfm_gen_powerpc_perf_validate_pattrs), .get_event_first = pfm_gen_powerpc_get_event_first, .get_event_next = pfm_gen_powerpc_get_event_next, .event_is_valid = pfm_gen_powerpc_event_is_valid, .validate_table = pfm_gen_powerpc_validate_table, .get_event_info = pfm_gen_powerpc_get_event_info, .get_event_attr_info = pfm_gen_powerpc_get_event_attr_info, }; libpfm-4.9.0/lib/pfmlib_intel_hswep_unc_cbo.c0000664000175000017500000001001013223402656021062 0ustar eranianeranian/* * pfmlib_intel_hswep_unc_cbo.c : Intel Haswell-EP C-Box uncore PMU * * Copyright (c) 2014 Google Inc. All rights reserved * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_intel_x86_priv.h" #include "pfmlib_intel_snbep_unc_priv.h" #include "events/intel_hswep_unc_cbo_events.h" static void display_cbo(void *this, pfmlib_event_desc_t *e, void *val) { const intel_x86_entry_t *pe = this_pe(this); pfm_snbep_unc_reg_t *reg = val; pfm_snbep_unc_reg_t f; __pfm_vbprintf("[UNC_CBO=0x%"PRIx64" event=0x%x umask=0x%x en=%d " "inv=%d edge=%d thres=%d tid_en=%d] %s\n", reg->val, reg->cbo.unc_event, reg->cbo.unc_umask, reg->cbo.unc_en, reg->cbo.unc_inv, reg->cbo.unc_edge, reg->cbo.unc_thres, reg->cbo.unc_tid, pe[e->event].name); if (e->count == 1) return; f.val = e->codes[1]; __pfm_vbprintf("[UNC_CBOX_FILTER0=0x%"PRIx64" tid=%d core=0x%x" " state=0x%x]\n", f.val, f.ivbep_cbo_filt0.tid, f.ivbep_cbo_filt0.cid, f.ivbep_cbo_filt0.state); if (e->count == 2) return; f.val = e->codes[2]; __pfm_vbprintf("[UNC_CBOX_FILTER1=0x%"PRIx64" nid=%d opc=0x%x" " nc=0x%x isoc=0x%x]\n", f.val, f.ivbep_cbo_filt1.nid, f.ivbep_cbo_filt1.opc, f.ivbep_cbo_filt1.nc, f.ivbep_cbo_filt1.isoc); } #define DEFINE_C_BOX(n) \ pfmlib_pmu_t intel_hswep_unc_cb##n##_support = {\ .desc = "Intel Haswell-EP C-Box "#n" uncore",\ .name = "hswep_unc_cbo"#n,\ .perf_name = "uncore_cbox_"#n,\ .pmu = PFM_PMU_INTEL_HSWEP_UNC_CB##n,\ .pme_count = LIBPFM_ARRAY_SIZE(intel_hswep_unc_c_pe),\ .type = PFM_PMU_TYPE_UNCORE,\ .num_cntrs = 4,\ .num_fixed_cntrs = 0,\ .max_encoding = 2,\ .pe = intel_hswep_unc_c_pe,\ .atdesc = snbep_unc_mods,\ .flags = PFMLIB_PMU_FL_RAW_UMASK|INTEL_PMU_FL_UNC_CBO,\ .pmu_detect = pfm_intel_hswep_unc_detect,\ .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding,\ PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding),\ PFMLIB_OS_DETECT(pfm_intel_x86_perf_detect), \ .get_event_first = pfm_intel_x86_get_event_first,\ .get_event_next = pfm_intel_x86_get_event_next,\ .event_is_valid = pfm_intel_x86_event_is_valid,\ .validate_table = pfm_intel_x86_validate_table,\ .get_event_info = pfm_intel_x86_get_event_info,\ .get_event_attr_info = pfm_intel_x86_get_event_attr_info,\ PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs),\ .get_event_nattrs = pfm_intel_x86_get_event_nattrs,\ .can_auto_encode = pfm_intel_x86_can_auto_encode, \ .display_reg = display_cbo,\ } DEFINE_C_BOX(0); DEFINE_C_BOX(1); DEFINE_C_BOX(2); DEFINE_C_BOX(3); DEFINE_C_BOX(4); DEFINE_C_BOX(5); DEFINE_C_BOX(6); DEFINE_C_BOX(7); DEFINE_C_BOX(8); DEFINE_C_BOX(9); DEFINE_C_BOX(10); DEFINE_C_BOX(11); DEFINE_C_BOX(12); DEFINE_C_BOX(13); DEFINE_C_BOX(14); DEFINE_C_BOX(15); DEFINE_C_BOX(16); DEFINE_C_BOX(17); libpfm-4.9.0/lib/pfmlib_intel_bdx_unc_sbo.c0000664000175000017500000000620713223402656020546 0ustar eranianeranian/* * pfmlib_intel_bdx_unc_sbo.c : Intel BroadwellX S-Box uncore PMU * * Copyright (c) 2017 Google Inc. All rights reserved * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_intel_x86_priv.h" #include "pfmlib_intel_snbep_unc_priv.h" #include "events/intel_bdx_unc_sbo_events.h" static void display_sbo(void *this, pfmlib_event_desc_t *e, void *val) { const intel_x86_entry_t *pe = this_pe(this); pfm_snbep_unc_reg_t *reg = val; __pfm_vbprintf("[UNC_SBO=0x%"PRIx64" event=0x%x umask=0x%x en=%d " "inv=%d edge=%d thres=%d] %s\n", reg->val, reg->com.unc_event, reg->com.unc_umask, reg->com.unc_en, reg->com.unc_inv, reg->com.unc_edge, reg->com.unc_thres, pe[e->event].name); } #define DEFINE_S_BOX(n) \ pfmlib_pmu_t intel_bdx_unc_sbo##n##_support = {\ .desc = "Intel BroadwellX S-BOX"#n" uncore",\ .name = "bdx_unc_sbo"#n,\ .perf_name = "uncore_sbox_"#n,\ .pmu = PFM_PMU_INTEL_BDX_UNC_SB##n,\ .pme_count = LIBPFM_ARRAY_SIZE(intel_bdx_unc_s_pe),\ .type = PFM_PMU_TYPE_UNCORE,\ .num_cntrs = 4,\ .num_fixed_cntrs = 0,\ .max_encoding = 3,\ .pe = intel_bdx_unc_s_pe,\ .atdesc = snbep_unc_mods,\ .flags = PFMLIB_PMU_FL_RAW_UMASK,\ .pmu_detect = pfm_intel_bdx_unc_detect,\ .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding,\ PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding),\ PFMLIB_OS_DETECT(pfm_intel_x86_perf_detect), \ .get_event_first = pfm_intel_x86_get_event_first,\ .get_event_next = pfm_intel_x86_get_event_next,\ .event_is_valid = pfm_intel_x86_event_is_valid,\ .validate_table = pfm_intel_x86_validate_table,\ .get_event_info = pfm_intel_x86_get_event_info,\ .get_event_attr_info = pfm_intel_x86_get_event_attr_info,\ PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs),\ .get_event_nattrs = pfm_intel_x86_get_event_nattrs,\ .display_reg = display_sbo,\ } DEFINE_S_BOX(0); DEFINE_S_BOX(1); DEFINE_S_BOX(2); DEFINE_S_BOX(3); libpfm-4.9.0/lib/pfmlib_intel_x86_perf_event.c0000664000175000017500000001752613223402656021131 0ustar eranianeranian/* pfmlib_intel_x86_perf.c : perf_event Intel X86 functions * * Copyright (c) 2011 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include #include /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_intel_x86_priv.h" #include "pfmlib_perf_event_priv.h" static int find_pmu_type_by_name(const char *name) { char filename[PATH_MAX]; FILE *fp; int ret, type; if (!name) return PFM_ERR_NOTSUPP; sprintf(filename, "/sys/bus/event_source/devices/%s/type", name); fp = fopen(filename, "r"); if (!fp) return PFM_ERR_NOTSUPP; ret = fscanf(fp, "%d", &type); if (ret != 1) type = PFM_ERR_NOTSUPP; fclose(fp); return type; } static int has_ldlat(void *this, pfmlib_event_desc_t *e) { pfmlib_event_attr_info_t *a; int i; for (i = 0; i < e->nattrs; i++) { a = attr(e, i); if (a->ctrl != PFM_ATTR_CTRL_PMU) continue; if (a->type != PFM_ATTR_UMASK) continue; if (intel_x86_uflag(this, e->event, a->idx, INTEL_X86_LDLAT)) return 1; } return 0; } int pfm_intel_x86_get_perf_encoding(void *this, pfmlib_event_desc_t *e) { pfmlib_pmu_t *pmu = this; struct perf_event_attr *attr = e->os_data; int ret; if (!pmu->get_event_encoding[PFM_OS_NONE]) return PFM_ERR_NOTSUPP; /* * first, we need to do the generic encoding */ ret = pmu->get_event_encoding[PFM_OS_NONE](this, e); if (ret != PFM_SUCCESS) return ret; if (e->count > 2) { DPRINT("%s: unsupported count=%d\n", e->count); return PFM_ERR_NOTSUPP; } /* default PMU type */ attr->type = PERF_TYPE_RAW; /* * if PMU specifies a perf PMU name, then grab the type * from sysfs as it is most likely dynamically assigned. * This allows this function to use used by some uncore PMUs */ if (pmu->perf_name) { int type = find_pmu_type_by_name(pmu->perf_name); if (type == PFM_ERR_NOTSUPP) { DPRINT("perf PMU %s, not supported by OS\n", pmu->perf_name); } else { DPRINT("PMU %s perf type=%d\n", pmu->name, type); attr->type = type; } } attr->config = e->codes[0]; if (e->count > 1) { /* * Nehalem/Westmere/Sandy Bridge OFFCORE_RESPONSE events * take two MSRs. Lower level returns two codes: * - codes[0] goes to regular counter config * - codes[1] goes into extra MSR */ if (intel_x86_eflag(this, e->event, INTEL_X86_NHM_OFFCORE)) { if (e->count != 2) { DPRINT("perf_encoding: offcore=1 count=%d\n", e->count); return PFM_ERR_INVAL; } attr->config1 = e->codes[1]; } /* * SkyLake FRONTEND_RETIRED event * takes two MSRs. Lower level returns two codes: * - codes[0] goes to regular counter config * - codes[1] goes into extra MSR */ if (intel_x86_eflag(this, e->event, INTEL_X86_FRONTEND)) { if (e->count != 2) { DPRINT("perf_encoding: frontend_retired=1 count=%d\n", e->count); return PFM_ERR_INVAL; } attr->config1 = e->codes[1]; } /* * Load Latency threshold (NHM/WSM/SNB) * - codes[0] goes to regular counter config * - codes[1] LD_LAT MSR value (LSB 16 bits) */ if (has_ldlat(this, e)) { if (e->count != 2) { DPRINT("perf_encoding: ldlat count=%d\n", e->count); return PFM_ERR_INVAL; } attr->config1 = e->codes[1]; } } return PFM_SUCCESS; } int pfm_intel_nhm_unc_get_perf_encoding(void *this, pfmlib_event_desc_t *e) { pfmlib_pmu_t *pmu = this; struct perf_event_attr *attr = e->os_data; pfm_intel_x86_reg_t reg; int ret; if (!pmu->get_event_encoding[PFM_OS_NONE]) return PFM_ERR_NOTSUPP; ret = pmu->get_event_encoding[PFM_OS_NONE](this, e); if (ret != PFM_SUCCESS) return ret; ret = find_pmu_type_by_name(pmu->perf_name); if (ret < 0) return ret; attr->type = ret; reg.val = e->codes[0]; /* * encoder treats all events as using the generic * counters. * perf_events override the enable and int bits, so * drop them here. * * also makes fixed counter special encoding 0xff * work. kernel checking for perfect match. */ reg.nhm_unc.usel_en = 0; reg.nhm_unc.usel_int = 0; attr->config = reg.val; /* * uncore measures at all priv levels * * user cannot set per-event priv levels because * attributes are simply not there * * dfl_plm is ignored in this case */ attr->exclude_hv = 0; attr->exclude_kernel = 0; attr->exclude_user = 0; return PFM_SUCCESS; } int pfm_intel_x86_requesting_pebs(pfmlib_event_desc_t *e) { pfmlib_event_attr_info_t *a; int i; for (i = 0; i < e->nattrs; i++) { a = attr(e, i); if (a->ctrl != PFM_ATTR_CTRL_PERF_EVENT) continue; if (a->idx == PERF_ATTR_PR && e->attrs[i].ival) return 1; } return 0; } static int intel_x86_event_has_pebs(void *this, pfmlib_event_desc_t *e) { pfmlib_event_attr_info_t *a; int i; /* first check at the event level */ if (intel_x86_eflag(e->pmu, e->event, INTEL_X86_PEBS)) return 1; /* check umasks */ for(i=0; i < e->npattrs; i++) { a = e->pattrs+i; if (a->ctrl != PFM_ATTR_CTRL_PMU || a->type != PFM_ATTR_UMASK) continue; if (intel_x86_uflag(e->pmu, e->event, a->idx, INTEL_X86_PEBS)) return 1; } return 0; } /* * remove attrs which are in conflicts (or duplicated) with os layer */ void pfm_intel_x86_perf_validate_pattrs(void *this, pfmlib_event_desc_t *e) { pfmlib_pmu_t *pmu = this; int i, compact; int has_pebs = intel_x86_event_has_pebs(this, e); int no_smpl = pmu->flags & PFMLIB_PMU_FL_NO_SMPL; for (i = 0; i < e->npattrs; i++) { compact = 0; /* umasks never conflict */ if (e->pattrs[i].type == PFM_ATTR_UMASK) continue; /* * with perf_events, u and k are handled at the OS level * via exclude_user, exclude_kernel. */ if (e->pattrs[i].ctrl == PFM_ATTR_CTRL_PMU) { if (e->pattrs[i].idx == INTEL_X86_ATTR_U || e->pattrs[i].idx == INTEL_X86_ATTR_K) compact = 1; } if (e->pattrs[i].ctrl == PFM_ATTR_CTRL_PERF_EVENT) { /* Precise mode, subject to PEBS */ if (e->pattrs[i].idx == PERF_ATTR_PR && !has_pebs) compact = 1; /* * No hypervisor on Intel */ if (e->pattrs[i].idx == PERF_ATTR_H) compact = 1; if (no_smpl && ( e->pattrs[i].idx == PERF_ATTR_FR || e->pattrs[i].idx == PERF_ATTR_PR || e->pattrs[i].idx == PERF_ATTR_PE)) compact = 1; /* * no priv level support */ if (pmu->supported_plm == 0 && ( e->pattrs[i].idx == PERF_ATTR_U || e->pattrs[i].idx == PERF_ATTR_K || e->pattrs[i].idx == PERF_ATTR_MG || e->pattrs[i].idx == PERF_ATTR_MH)) compact = 1; } if (compact) { /* e->npattrs modified by call */ pfmlib_compact_pattrs(e, i); /* compensate for i++ */ i--; } } } int pfm_intel_x86_perf_detect(void *this) { pfmlib_pmu_t *pmu = this; char file[64]; snprintf(file,sizeof(file), "/sys/devices/%s", pmu->perf_name); return access(file, R_OK|X_OK) ? PFM_ERR_NOTSUPP : PFM_SUCCESS; } libpfm-4.9.0/lib/pfmlib_power5.c0000664000175000017500000000626613223402656016314 0ustar eranianeranian/* * pfmlib_power5.c : IBM Power5 support * * Copyright (C) IBM Corporation, 2009. All rights reserved. * Contributed by Corey Ashford (cjashfor@us.ibm.com) * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_power_priv.h" #include "events/power5_events.h" #include "events/power5+_events.h" static int pfm_power5_detect(void* this) { if (__is_processor(PV_POWER5)) return PFM_SUCCESS; return PFM_ERR_NOTSUPP; } static int pfm_power5p_detect(void* this) { if (__is_processor(PV_POWER5p)) return PFM_SUCCESS; return PFM_ERR_NOTSUPP; } pfmlib_pmu_t power5_support={ .desc = "POWER5", .name = "power5", .pmu = PFM_PMU_POWER5, .pme_count = LIBPFM_ARRAY_SIZE(power5_pe), .type = PFM_PMU_TYPE_CORE, .num_cntrs = 4, .num_fixed_cntrs = 2, .max_encoding = 1, .pe = power5_pe, .pmu_detect = pfm_power5_detect, .get_event_encoding[PFM_OS_NONE] = pfm_gen_powerpc_get_encoding, PFMLIB_ENCODE_PERF(pfm_gen_powerpc_get_perf_encoding), PFMLIB_VALID_PERF_PATTRS(pfm_gen_powerpc_perf_validate_pattrs), .get_event_first = pfm_gen_powerpc_get_event_first, .get_event_next = pfm_gen_powerpc_get_event_next, .event_is_valid = pfm_gen_powerpc_event_is_valid, .validate_table = pfm_gen_powerpc_validate_table, .get_event_info = pfm_gen_powerpc_get_event_info, .get_event_attr_info = pfm_gen_powerpc_get_event_attr_info, }; pfmlib_pmu_t power5p_support={ .desc = "POWER5+", .name = "power5p", .pmu = PFM_PMU_POWER5p, .pme_count = LIBPFM_ARRAY_SIZE(power5p_pe), .type = PFM_PMU_TYPE_CORE, .num_cntrs = 4, .num_fixed_cntrs = 2, .max_encoding = 1, .pe = power5p_pe, .pmu_detect = pfm_power5p_detect, .get_event_encoding[PFM_OS_NONE] = pfm_gen_powerpc_get_encoding, PFMLIB_ENCODE_PERF(pfm_gen_powerpc_get_perf_encoding), PFMLIB_VALID_PERF_PATTRS(pfm_gen_powerpc_perf_validate_pattrs), .get_event_first = pfm_gen_powerpc_get_event_first, .get_event_next = pfm_gen_powerpc_get_event_next, .event_is_valid = pfm_gen_powerpc_event_is_valid, .validate_table = pfm_gen_powerpc_validate_table, .get_event_info = pfm_gen_powerpc_get_event_info, .get_event_attr_info = pfm_gen_powerpc_get_event_attr_info, }; libpfm-4.9.0/lib/pfmlib_intel_ivbep_unc_r2pcie.c0000664000175000017500000000512413223402656021474 0ustar eranianeranian/* * pfmlib_intel_ivbep_r2pcie.c : Intel IvyBridge-EP R2PCIe uncore PMU * * Copyright (c) 2014 Google Inc. All rights reserved * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_intel_x86_priv.h" #include "pfmlib_intel_snbep_unc_priv.h" #include "events/intel_ivbep_unc_r2pcie_events.h" pfmlib_pmu_t intel_ivbep_unc_r2pcie_support = { .desc = "Intel Ivy Bridge-EP R2PCIe uncore", .name = "ivbep_unc_r2pcie", .perf_name = "uncore_r2pcie", .pmu = PFM_PMU_INTEL_IVBEP_UNC_R2PCIE, .pme_count = LIBPFM_ARRAY_SIZE(intel_ivbep_unc_r2_pe), .type = PFM_PMU_TYPE_UNCORE, .num_cntrs = 4, .num_fixed_cntrs = 0, .max_encoding = 1, .pe = intel_ivbep_unc_r2_pe, .atdesc = snbep_unc_mods, .flags = PFMLIB_PMU_FL_RAW_UMASK, .pmu_detect = pfm_intel_ivbep_unc_detect, .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding, PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding), PFMLIB_OS_DETECT(pfm_intel_x86_perf_detect), .get_event_first = pfm_intel_x86_get_event_first, .get_event_next = pfm_intel_x86_get_event_next, .event_is_valid = pfm_intel_x86_event_is_valid, .validate_table = pfm_intel_x86_validate_table, .get_event_info = pfm_intel_x86_get_event_info, .get_event_attr_info = pfm_intel_x86_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs), .get_event_nattrs = pfm_intel_x86_get_event_nattrs, }; libpfm-4.9.0/lib/pfmlib_cell_priv.h0000664000175000017500000000565713223402656017062 0ustar eranianeranian/* * Copyright (c) 2007 TOSHIBA CORPORATION based on code from * Copyright (c) 2001-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef __PFMLIB_CELL_PRIV_H__ #define __PFMLIB_CELL_PRIV_H__ #define PFM_CELL_PME_FREQ_PPU_MFC 0 #define PFM_CELL_PME_FREQ_SPU 1 #define PFM_CELL_PME_FREQ_HALF 2 typedef struct { char *pme_name; /* event name */ char *pme_desc; /* event description */ unsigned long long pme_code; /* event code */ unsigned int pme_type; /* count type */ unsigned int pme_freq; /* debug_bus_control's frequency value */ unsigned int pme_enable_word; } pme_cell_entry_t; /* PMC register */ #define REG_PM0_CONTROL 0x0000 #define REG_PM1_CONTROL 0x0001 #define REG_PM2_CONTROL 0x0002 #define REG_PM3_CONTROL 0x0003 #define REG_PM4_CONTROL 0x0004 #define REG_PM5_CONTROL 0x0005 #define REG_PM6_CONTROL 0x0006 #define REG_PM7_CONTROL 0x0007 #define REG_PM0_EVENT 0x0008 #define REG_PM1_EVENT 0x0009 #define REG_PM2_EVENT 0x000A #define REG_PM3_EVENT 0x000B #define REG_PM4_EVENT 0x000C #define REG_PM5_EVENT 0x000D #define REG_PM6_EVENT 0x000E #define REG_PM7_EVENT 0x000F #define REG_GROUP_CONTROL 0x0010 #define REG_DEBUG_BUS_CONTROL 0x0011 #define REG_TRACE_ADDRESS 0x0012 #define REG_EXT_TRACE_TIMER 0x0013 #define REG_PM_STATUS 0x0014 #define REG_PM_CONTROL 0x0015 #define REG_PM_INTERVAL 0x0016 #define REG_PM_START_STOP 0x0017 #define NONE_SIGNAL 0x0000 #define SIGNAL_SPU 41 #define SIGNAL_SPU_TRIGGER 42 #define SIGNAL_SPU_EVENT 43 #define COUNT_TYPE_BOTH_TYPE 1 #define COUNT_TYPE_CUMULATIVE_LEN 2 #define COUNT_TYPE_OCCURRENCE 3 #define COUNT_TYPE_MULTI_CYCLE 4 #define COUNT_TYPE_SINGLE_CYCLE 5 #define WORD_0_ONLY 1 /* 0001 */ #define WORD_2_ONLY 4 /* 0100 */ #define WORD_0_AND_1 3 /* 0011 */ #define WORD_0_AND_2 5 /* 0101 */ #define WORD_NONE 0 #endif /* __PFMLIB_CELL_PRIV_H__ */ libpfm-4.9.0/lib/pfmlib_intel_snbep_unc_pcu.c0000664000175000017500000000663013223402656021104 0ustar eranianeranian/* * pfmlib_intel_snbep_unc_pcu.c : Intel SandyBridge-EP Power Control Unit (PCU) uncore PMU * * Copyright (c) 2012 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_intel_x86_priv.h" #include "pfmlib_intel_snbep_unc_priv.h" #include "events/intel_snbep_unc_pcu_events.h" static void display_pcu(void *this, pfmlib_event_desc_t *e, void *val) { const intel_x86_entry_t *pe = this_pe(this); pfm_snbep_unc_reg_t *reg = val; pfm_snbep_unc_reg_t f; __pfm_vbprintf("[UNC_PCU=0x%"PRIx64" event=0x%x occ_sel=0x%x en=%d " "inv=%d edge=%d thres=%d occ_inv=%d occ_edge=%d] %s\n", reg->val, reg->pcu.unc_event, reg->pcu.unc_occ, reg->pcu.unc_en, reg->pcu.unc_inv, reg->pcu.unc_edge, reg->pcu.unc_thres, reg->pcu.unc_occ_inv, reg->pcu.unc_occ_edge, pe[e->event].name); if (e->count == 1) return; f.val = e->codes[1]; __pfm_vbprintf("[UNC_PCU_FILTER=0x%"PRIx64" band0=%u band1=%u band2=%u band3=%u]\n", f.val, f.pcu_filt.filt0, f.pcu_filt.filt1, f.pcu_filt.filt2, f.pcu_filt.filt3); } pfmlib_pmu_t intel_snbep_unc_pcu_support = { .desc = "Intel Sandy Bridge-EP PCU uncore", .name = "snbep_unc_pcu", .perf_name = "uncore_pcu", .pmu = PFM_PMU_INTEL_SNBEP_UNC_PCU, .pme_count = LIBPFM_ARRAY_SIZE(intel_snbep_unc_p_pe), .type = PFM_PMU_TYPE_UNCORE, .num_cntrs = 4, .num_fixed_cntrs = 0, .max_encoding = 2, .pe = intel_snbep_unc_p_pe, .atdesc = snbep_unc_mods, .flags = PFMLIB_PMU_FL_RAW_UMASK | INTEL_PMU_FL_UNC_OCC | PFMLIB_PMU_FL_NO_SMPL, .pmu_detect = pfm_intel_snbep_unc_detect, .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding, PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding), .get_event_first = pfm_intel_x86_get_event_first, .get_event_next = pfm_intel_x86_get_event_next, .event_is_valid = pfm_intel_x86_event_is_valid, .validate_table = pfm_intel_x86_validate_table, .get_event_info = pfm_intel_x86_get_event_info, .get_event_attr_info = pfm_intel_x86_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs), .get_event_nattrs = pfm_intel_x86_get_event_nattrs, .can_auto_encode = pfm_intel_snbep_unc_can_auto_encode, .display_reg = display_pcu, }; libpfm-4.9.0/lib/pfmlib_arm_perf_event.c0000664000175000017500000000523113223402656020056 0ustar eranianeranian/* * pfmlib_arm_perf_event.c : perf_event ARM functions * * Copyright (c) 2011 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include /* private headers */ #include "pfmlib_priv.h" /* library private */ #include "pfmlib_arm_priv.h" #include "pfmlib_perf_event_priv.h" int pfm_arm_get_perf_encoding(void *this, pfmlib_event_desc_t *e) { pfmlib_pmu_t *pmu = this; struct perf_event_attr *attr = e->os_data; int ret; if (!pmu->get_event_encoding[PFM_OS_NONE]) return PFM_ERR_NOTSUPP; /* * use generic raw encoding function first */ ret = pmu->get_event_encoding[PFM_OS_NONE](this, e); if (ret != PFM_SUCCESS) return ret; if (e->count > 1) { DPRINT("%s: unsupported count=%d\n", e->count); return PFM_ERR_NOTSUPP; } attr->type = PERF_TYPE_RAW; attr->config = e->codes[0]; return PFM_SUCCESS; } void pfm_arm_perf_validate_pattrs(void *this, pfmlib_event_desc_t *e) { int i, compact; for (i = 0; i < e->npattrs; i++) { compact = 0; /* umasks never conflict */ if (e->pattrs[i].type == PFM_ATTR_UMASK) continue; /* * with perf_events, u and k, hv are handled at the OS * level via attr.exclude_* fields */ if (arm_has_plm(this, e) && e->pattrs[i].ctrl == PFM_ATTR_CTRL_PMU) { if ( e->pattrs[i].idx == ARM_ATTR_U || e->pattrs[i].idx == ARM_ATTR_K || e->pattrs[i].idx == ARM_ATTR_HV) compact = 1; } if (e->pattrs[i].ctrl == PFM_ATTR_CTRL_PERF_EVENT) { if (e->pattrs[i].idx == PERF_ATTR_PR) compact = 1; } if (compact) { pfmlib_compact_pattrs(e, i); i--; } } } libpfm-4.9.0/lib/pfmlib_intel_slm.c0000664000175000017500000000515313223402656017053 0ustar eranianeranian/* * pfmlib_intel_slm.c : Intel Silvermont core PMU * * Copyright (c) 2013 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * Based on Intel Software Optimization Guide June 2013 */ /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_intel_x86_priv.h" #include "events/intel_slm_events.h" static const int slm_models[] = { 55, /* Silvermont */ 77, /* Silvermont Avoton */ 76, /* Airmont */ 0 }; static int pfm_intel_slm_init(void *this) { pfm_intel_x86_cfg.arch_version = 2; return PFM_SUCCESS; } pfmlib_pmu_t intel_slm_support={ .desc = "Intel Silvermont", .name = "slm", .pmu = PFM_PMU_INTEL_SLM, .pme_count = LIBPFM_ARRAY_SIZE(intel_slm_pe), .type = PFM_PMU_TYPE_CORE, .num_cntrs = 4, .num_fixed_cntrs = 3, .max_encoding = 2, .pe = intel_slm_pe, .atdesc = intel_x86_mods, .flags = PFMLIB_PMU_FL_RAW_UMASK, .supported_plm = INTEL_X86_PLM, .cpu_family = 6, .cpu_models = slm_models, .pmu_detect = pfm_intel_x86_model_detect, .pmu_init = pfm_intel_slm_init, .get_event_encoding[PFM_OS_NONE] = pfm_intel_x86_get_encoding, PFMLIB_ENCODE_PERF(pfm_intel_x86_get_perf_encoding), .get_event_first = pfm_intel_x86_get_event_first, .get_event_next = pfm_intel_x86_get_event_next, .event_is_valid = pfm_intel_x86_event_is_valid, .validate_table = pfm_intel_x86_validate_table, .get_event_info = pfm_intel_x86_get_event_info, .get_event_attr_info = pfm_intel_x86_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_intel_x86_perf_validate_pattrs), .get_event_nattrs = pfm_intel_x86_get_event_nattrs, }; libpfm-4.9.0/lib/pfmlib_intel_bdx_unc_cbo.c0000664000175000017500000001011113223402656020513 0ustar eranianeranian/* * pfmlib_intel_bdx_unc_cbo.c : Intel BDX C-Box uncore PMU * * Copyright (c) 2017 Google Inc. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_intel_x86_priv.h" #include "pfmlib_intel_snbep_unc_priv.h" #include "events/intel_bdx_unc_cbo_events.h" static void display_cbo(void *this, pfmlib_event_desc_t *e, void *val) { const intel_x86_entry_t *pe = this_pe(this); pfm_snbep_unc_reg_t *reg = val; pfm_snbep_unc_reg_t f; __pfm_vbprintf("[UNC_CBO=0x%"PRIx64" event=0x%x umask=0x%x en=%d " "inv=%d edge=%d thres=%d tid_en=%d] %s\n", reg->val, reg->cbo.unc_event, reg->cbo.unc_umask, reg->cbo.unc_en, reg->cbo.unc_inv, reg->cbo.unc_edge, reg->cbo.unc_thres, reg->cbo.unc_tid, pe[e->event].name); if (e->count == 1) return; f.val = e->codes[1]; __pfm_vbprintf("[UNC_CBOX_FILTER0=0x%"PRIx64" tid=%d core=0x%x" " state=0x%x]\n", f.val, f.ivbep_cbo_filt0.tid, f.ivbep_cbo_filt0.cid, f.ivbep_cbo_filt0.state); if (e->count == 2) return; f.val = e->codes[2]; __pfm_vbprintf("[UNC_CBOX_FILTER1=0x%"PRIx64" nid=%d opc=0x%x" " nc=0x%x isoc=0x%x]\n", f.val, f.ivbep_cbo_filt1.nid, f.ivbep_cbo_filt1.opc, f.ivbep_cbo_filt1.nc, f.ivbep_cbo_filt1.isoc); } #define DEFINE_C_BOX(n) \ pfmlib_pmu_t intel_bdx_unc_cb##n##_support = {\ .desc = "Intel BroadwellX C-Box "#n" uncore",\ .name = "bdx_unc_cbo"#n,\ .perf_name = "uncore_cbox_"#n,\ .pmu = PFM_PMU_INTEL_BDX_UNC_CB##n,\ .pme_count = LIBPFM_ARRAY_SIZE(intel_bdx_unc_c_pe),\ .type = PFM_PMU_TYPE_UNCORE,\ .num_cntrs = 4,\ .num_fixed_cntrs = 0,\ .max_encoding = 2,\ .pe = intel_bdx_unc_c_pe,\ .atdesc = snbep_unc_mods,\ .flags = PFMLIB_PMU_FL_RAW_UMASK|INTEL_PMU_FL_UNC_CBO,\ .pmu_detect = pfm_intel_bdx_unc_detect,\ .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding,\ PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding),\ PFMLIB_OS_DETECT(pfm_intel_x86_perf_detect), \ .get_event_first = pfm_intel_x86_get_event_first,\ .get_event_next = pfm_intel_x86_get_event_next,\ .event_is_valid = pfm_intel_x86_event_is_valid,\ .validate_table = pfm_intel_x86_validate_table,\ .get_event_info = pfm_intel_x86_get_event_info,\ .get_event_attr_info = pfm_intel_x86_get_event_attr_info,\ PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs),\ .get_event_nattrs = pfm_intel_x86_get_event_nattrs,\ .can_auto_encode = pfm_intel_x86_can_auto_encode, \ .display_reg = display_cbo,\ } DEFINE_C_BOX(0); DEFINE_C_BOX(1); DEFINE_C_BOX(2); DEFINE_C_BOX(3); DEFINE_C_BOX(4); DEFINE_C_BOX(5); DEFINE_C_BOX(6); DEFINE_C_BOX(7); DEFINE_C_BOX(8); DEFINE_C_BOX(9); DEFINE_C_BOX(10); DEFINE_C_BOX(11); DEFINE_C_BOX(12); DEFINE_C_BOX(13); DEFINE_C_BOX(14); DEFINE_C_BOX(15); DEFINE_C_BOX(16); DEFINE_C_BOX(17); DEFINE_C_BOX(18); DEFINE_C_BOX(19); DEFINE_C_BOX(20); DEFINE_C_BOX(21); DEFINE_C_BOX(22); DEFINE_C_BOX(23); libpfm-4.9.0/lib/pfmlib_intel_knl.c0000664000175000017500000000517113223402656017044 0ustar eranianeranian/* * pfmlib_intel_knl.c : Intel Knights Landing core PMU * * Copyright (c) 2016 Intel Corp. All rights reserved * Contributed by Peinan Zhang * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * Based on Intel Software Optimization Guide 2015 */ /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_intel_x86_priv.h" #include "events/intel_knl_events.h" static const int knl_models[] = { 87, /* knights landing */ 0 }; static int pfm_intel_knl_init(void *this) { pfm_intel_x86_cfg.arch_version = 2; return PFM_SUCCESS; } pfmlib_pmu_t intel_knl_support={ .desc = "Intel Knights Landing", .name = "knl", .pmu = PFM_PMU_INTEL_KNL, .pme_count = LIBPFM_ARRAY_SIZE(intel_knl_pe), .type = PFM_PMU_TYPE_CORE, .num_cntrs = 2, .num_fixed_cntrs = 3, .max_encoding = 2, .pe = intel_knl_pe, .atdesc = intel_x86_mods, .flags = PFMLIB_PMU_FL_RAW_UMASK | INTEL_X86_PMU_FL_ECMASK, .supported_plm = INTEL_X86_PLM, .cpu_family = 6, .cpu_models = knl_models, .pmu_detect = pfm_intel_x86_model_detect, .pmu_init = pfm_intel_knl_init, .get_event_encoding[PFM_OS_NONE] = pfm_intel_x86_get_encoding, PFMLIB_ENCODE_PERF(pfm_intel_x86_get_perf_encoding), .get_event_first = pfm_intel_x86_get_event_first, .get_event_next = pfm_intel_x86_get_event_next, .event_is_valid = pfm_intel_x86_event_is_valid, .validate_table = pfm_intel_x86_validate_table, .get_event_info = pfm_intel_x86_get_event_info, .get_event_attr_info = pfm_intel_x86_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_intel_x86_perf_validate_pattrs), .get_event_nattrs = pfm_intel_x86_get_event_nattrs, }; libpfm-4.9.0/lib/pfmlib_sparc_niagara.c0000664000175000017500000000615313223402656017660 0ustar eranianeranian/* * pfmlib_sparc_niagara.c : SPARC Niagara I, II * * Copyright (c) 2011 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * Core PMU = architectural perfmon v2 + PEBS */ /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_sparc_priv.h" #include "events/sparc_niagara1_events.h" #include "events/sparc_niagara2_events.h" pfmlib_pmu_t sparc_niagara1_support={ .desc = "Sparc Niagara I", .name = "niagara1", .pmu = PFM_PMU_SPARC_NIAGARA1, .pme_count = LIBPFM_ARRAY_SIZE(niagara1_pe), .type = PFM_PMU_TYPE_CORE, .supported_plm = SPARC_PLM, .max_encoding = 2, .num_cntrs = 2, .pe = niagara1_pe, .atdesc = NULL, .flags = 0, .pmu_detect = pfm_sparc_detect, .get_event_encoding[PFM_OS_NONE] = pfm_sparc_get_encoding, PFMLIB_ENCODE_PERF(pfm_sparc_get_perf_encoding), .get_event_first = pfm_sparc_get_event_first, .get_event_next = pfm_sparc_get_event_next, .event_is_valid = pfm_sparc_event_is_valid, .validate_table = pfm_sparc_validate_table, .get_event_info = pfm_sparc_get_event_info, .get_event_attr_info = pfm_sparc_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_sparc_perf_validate_pattrs), .get_event_nattrs = pfm_sparc_get_event_nattrs, }; pfmlib_pmu_t sparc_niagara2_support={ .desc = "Sparc Niagara II", .name = "niagara2", .pmu = PFM_PMU_SPARC_NIAGARA2, .pme_count = LIBPFM_ARRAY_SIZE(niagara2_pe), .type = PFM_PMU_TYPE_CORE, .supported_plm = NIAGARA2_PLM, .num_cntrs = 2, .max_encoding = 2, .pe = niagara2_pe, .atdesc = NULL, .flags = 0, .pmu_detect = pfm_sparc_detect, .get_event_encoding[PFM_OS_NONE] = pfm_sparc_get_encoding, PFMLIB_ENCODE_PERF(pfm_sparc_get_perf_encoding), .get_event_first = pfm_sparc_get_event_first, .get_event_next = pfm_sparc_get_event_next, .event_is_valid = pfm_sparc_event_is_valid, .validate_table = pfm_sparc_validate_table, .get_event_info = pfm_sparc_get_event_info, .get_event_attr_info = pfm_sparc_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_sparc_perf_validate_pattrs), .get_event_nattrs = pfm_sparc_get_event_nattrs, }; libpfm-4.9.0/lib/pfmlib_intel_hswep_unc_qpi.c0000664000175000017500000000623013223402656021121 0ustar eranianeranian/* * pfmlib_intel_hswep_qpi.c : Intel Haswell-EP QPI uncore PMU * * Copyright (c) 2014 Google Inc. All rights reserved * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_intel_x86_priv.h" #include "pfmlib_intel_snbep_unc_priv.h" #include "events/intel_hswep_unc_qpi_events.h" static void display_qpi(void *this, pfmlib_event_desc_t *e, void *val) { const intel_x86_entry_t *pe = this_pe(this); pfm_snbep_unc_reg_t *reg = val; __pfm_vbprintf("[UNC_QPI=0x%"PRIx64" event=0x%x sel_ext=%d umask=0x%x en=%d " "inv=%d edge=%d thres=%d] %s\n", reg->val, reg->qpi.unc_event, reg->qpi.unc_event_ext, reg->qpi.unc_umask, reg->qpi.unc_en, reg->qpi.unc_inv, reg->qpi.unc_edge, reg->qpi.unc_thres, pe[e->event].name); } #define DEFINE_QPI_BOX(n) \ pfmlib_pmu_t intel_hswep_unc_qpi##n##_support = {\ .desc = "Intel Haswell-EP QPI"#n" uncore",\ .name = "hswep_unc_qpi"#n,\ .perf_name = "uncore_qpi_"#n,\ .pmu = PFM_PMU_INTEL_HSWEP_UNC_QPI##n,\ .pme_count = LIBPFM_ARRAY_SIZE(intel_hswep_unc_q_pe),\ .type = PFM_PMU_TYPE_UNCORE,\ .num_cntrs = 4,\ .num_fixed_cntrs = 0,\ .max_encoding = 3,\ .pe = intel_hswep_unc_q_pe,\ .atdesc = snbep_unc_mods,\ .flags = PFMLIB_PMU_FL_RAW_UMASK,\ .pmu_detect = pfm_intel_hswep_unc_detect,\ .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding,\ PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding),\ PFMLIB_OS_DETECT(pfm_intel_x86_perf_detect), \ .get_event_first = pfm_intel_x86_get_event_first,\ .get_event_next = pfm_intel_x86_get_event_next,\ .event_is_valid = pfm_intel_x86_event_is_valid,\ .validate_table = pfm_intel_x86_validate_table,\ .get_event_info = pfm_intel_x86_get_event_info,\ .get_event_attr_info = pfm_intel_x86_get_event_attr_info,\ PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs),\ .get_event_nattrs = pfm_intel_x86_get_event_nattrs,\ .display_reg = display_qpi,\ } DEFINE_QPI_BOX(0); DEFINE_QPI_BOX(1); libpfm-4.9.0/lib/pfmlib_intel_snbep_unc_qpi.c0000664000175000017500000000617113223402656021106 0ustar eranianeranian/* * pfmlib_intel_snbep_qpi.c : Intel SandyBridge-EP QPI uncore PMU * * Copyright (c) 2012 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_intel_x86_priv.h" #include "pfmlib_intel_snbep_unc_priv.h" #include "events/intel_snbep_unc_qpi_events.h" static void display_qpi(void *this, pfmlib_event_desc_t *e, void *val) { const intel_x86_entry_t *pe = this_pe(this); pfm_snbep_unc_reg_t *reg = val; __pfm_vbprintf("[UNC_QPI=0x%"PRIx64" event=0x%x sel_ext=%d umask=0x%x en=%d " "inv=%d edge=%d thres=%d] %s\n", reg->val, reg->qpi.unc_event, reg->qpi.unc_event_ext, reg->qpi.unc_umask, reg->qpi.unc_en, reg->qpi.unc_inv, reg->qpi.unc_edge, reg->qpi.unc_thres, pe[e->event].name); } #define DEFINE_QPI_BOX(n) \ pfmlib_pmu_t intel_snbep_unc_qpi##n##_support = {\ .desc = "Intel Sandy Bridge-EP QPI"#n" uncore",\ .name = "snbep_unc_qpi"#n,\ .perf_name = "uncore_qpi_"#n,\ .pmu = PFM_PMU_INTEL_SNBEP_UNC_QPI##n,\ .pme_count = LIBPFM_ARRAY_SIZE(intel_snbep_unc_q_pe),\ .type = PFM_PMU_TYPE_UNCORE,\ .num_cntrs = 4,\ .num_fixed_cntrs = 0,\ .max_encoding = 3,\ .pe = intel_snbep_unc_q_pe,\ .atdesc = snbep_unc_mods,\ .flags = PFMLIB_PMU_FL_RAW_UMASK\ | PFMLIB_PMU_FL_NO_SMPL,\ .pmu_detect = pfm_intel_snbep_unc_detect,\ .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding,\ PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding),\ .get_event_first = pfm_intel_x86_get_event_first,\ .get_event_next = pfm_intel_x86_get_event_next,\ .event_is_valid = pfm_intel_x86_event_is_valid,\ .validate_table = pfm_intel_x86_validate_table,\ .get_event_info = pfm_intel_x86_get_event_info,\ .get_event_attr_info = pfm_intel_x86_get_event_attr_info,\ PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs),\ .get_event_nattrs = pfm_intel_x86_get_event_nattrs,\ .display_reg = display_qpi,\ } DEFINE_QPI_BOX(0); DEFINE_QPI_BOX(1); libpfm-4.9.0/lib/pfmlib_s390x_priv.h0000664000175000017500000000071213223402656017014 0ustar eranianeranian#ifndef __PFMLIB_S390X_PRIV_H__ #define __PFMLIB_S390X_PRIV_H__ #define CPUMF_COUNTER_MAX 256 typedef struct { uint64_t ctrnum; /* counter number */ unsigned int ctrset; /* counter set */ char *name; /* counter ID */ char *desc; /* short description */ } pme_cpumf_ctr_t; #define min(a, b) ((a) < (b) ? (a) : (b)) extern int pfm_s390x_get_perf_encoding(void *this, pfmlib_event_desc_t *e); #endif /* __PFMLIB_S390X_PRIV_H__ */ libpfm-4.9.0/lib/pfmlib_sicortex_priv.h0000664000175000017500000001111313223402656017763 0ustar eranianeranian/* * Contributed by Philip Mucci based on code from * Copyright (c) 2004-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux/ia64. */ #ifndef __PFMLIB_SICORTEX_PRIV_H__ #define __PFMLIB_SICORTEX_PRIV_H__ #include "pfmlib_gen_mips64_priv.h" #define PFMLIB_SICORTEX_MAX_UMASK 5 typedef struct { char *pme_uname; /* unit mask name */ char *pme_udesc; /* event/umask description */ unsigned int pme_ucode; /* unit mask code */ } pme_sicortex_umask_t; typedef struct { char *pme_name; char *pme_desc; /* text description of the event */ unsigned int pme_code; /* event mask, holds room for four events, low 8 bits cntr0, ... high 8 bits cntr3 */ unsigned int pme_counters; /* Which counter event lives on */ unsigned int pme_numasks; /* number of umasks */ pme_sicortex_umask_t pme_umasks[PFMLIB_SICORTEX_MAX_UMASK]; /* umask desc */ } pme_sicortex_entry_t; /* * SiCortex specific */ typedef union { uint64_t val; /* complete register value */ struct { unsigned long sel_exl:1; /* int level */ unsigned long sel_os:1; /* system level */ unsigned long sel_sup:1; /* supervisor level */ unsigned long sel_usr:1; /* user level */ unsigned long sel_int:1; /* enable intr */ unsigned long sel_event_mask:6; /* event mask */ unsigned long sel_res1:23; /* reserved */ unsigned long sel_res2:32; /* reserved */ } perfsel; } pfm_sicortex_sel_reg_t; #define PMU_SICORTEX_SCB_NUM_COUNTERS 256 typedef union { uint64_t val; struct { unsigned long Interval:4; unsigned long IntBit:5; unsigned long NoInc:1; unsigned long AddrAssert:1; unsigned long MagicEvent:2; unsigned long Reserved:19; } sicortex_ScbPerfCtl_reg; struct { unsigned long HistGte:20; unsigned long Reserved:12; } sicortex_ScbPerfHist_reg; struct { unsigned long Bucket:8; unsigned long Reserved:24; } sicortex_ScbPerfBuckNum_reg; struct { unsigned long ena:1; unsigned long Reserved:31; } sicortex_ScbPerfEna_reg; struct { unsigned long event:15; unsigned long hist:1; unsigned long ifOther:2; unsigned long Reserved:15; } sicortex_ScbPerfBucket_reg; } pmc_sicortex_scb_reg_t; typedef union { uint64_t val; struct { unsigned long Reserved:2; uint64_t VPCL:38; unsigned long VPCH:2; } sicortex_CpuPerfVPC_reg; struct { unsigned long Reserved:5; unsigned long PEA:31; unsigned long Reserved2:12; unsigned long ASID:8; unsigned long L2STOP:4; unsigned long L2STATE:3; unsigned long L2HIT:1; } sicortex_CpuPerfPEA_reg; } pmd_sicortex_cpu_reg_t; #define PFMLIB_SICORTEX_INPUT_SCB_NONE (unsigned long)0x0 #define PFMLIB_SICORTEX_INPUT_SCB_INTERVAL (unsigned long)0x1 #define PFMLIB_SICORTEX_INPUT_SCB_NOINC (unsigned long)0x2 #define PFMLIB_SICORTEX_INPUT_SCB_HISTGTE (unsigned long)0x4 #define PFMLIB_SICORTEX_INPUT_SCB_BUCKET (unsigned long)0x8 static pme_sicortex_umask_t sicortex_scb_umasks[PFMLIB_SICORTEX_MAX_UMASK] = { { "IFOTHER_NONE","Both buckets count independently",0x00 }, { "IFOTHER_AND","Increment where this event counts and the opposite bucket counts",0x02 }, { "IFOTHER_ANDNOT","Increment where this event counts and the opposite bucket does not",0x04 }, { "HIST_NONE","Count cycles where the event is asserted",0x0 }, { "HIST_EDGE","Histogram on edges of the specified event",0x1 } }; #endif /* __PFMLIB_GEN_MIPS64_PRIV_H__ */ libpfm-4.9.0/lib/pfmlib_intel_x86_priv.h0000664000175000017500000003235513223402656017756 0ustar eranianeranian/* * Copyright (c) 2009 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. */ #ifndef __PFMLIB_INTEL_X86_PRIV_H__ #define __PFMLIB_INTEL_X86_PRIV_H__ /* * This file contains the definitions used for all Intel X86 processors */ /* * maximum number of unit masks groups per event */ #define INTEL_X86_NUM_GRP 8 #define INTEL_X86_MAX_FILTERS 3 /* * unit mask description */ typedef struct { const char *uname; /* unit mask name */ const char *udesc; /* unit umask description */ const char *uequiv;/* name of event from which this one is derived, NULL if none */ uint64_t ucntmsk;/* supported counters for umask (if set, supersedes cntmsk) */ uint64_t ucode; /* unit mask code */ uint64_t ufilters[INTEL_X86_MAX_FILTERS]; /* extra encoding for event */ unsigned int uflags; /* unit mask flags */ unsigned short umodel; /* only available on this PMU model */ unsigned short grpid; /* unit mask group id */ unsigned int modhw; /* hardwired modifiers, cannot be changed */ unsigned int umodmsk_req; /* bitmask of required modifiers */ } intel_x86_umask_t; #define INTEL_X86_MAX_GRPID ((unsigned short)(~0)) /* * event description */ typedef struct { const char *name; /* event name */ const char *desc; /* event description */ const char *equiv; /* name of event from which this one is derived, NULL if none */ uint64_t cntmsk; /* supported counters */ unsigned int code; /* event code */ unsigned int numasks;/* number of umasks */ unsigned int flags; /* flags */ unsigned int modmsk; /* bitmask of modifiers for this event */ unsigned int modmsk_req; /* bitmask of required modifiers */ unsigned short ngrp; /* number of unit masks groups */ unsigned short model; /* only available on this PMU model */ const intel_x86_umask_t *umasks; /* umask desc */ } intel_x86_entry_t; /* * pme_flags value (event and unit mask) */ #define INTEL_X86_NCOMBO 0x0001 /* unit masks within group cannot be combined */ #define INTEL_X86_FALLBACK_GEN 0x0002 /* fallback from fixed to generic counter possible */ #define INTEL_X86_PEBS 0x0004 /* event supports PEBS or at least one umask supports PEBS */ #define INTEL_X86_DFL 0x0008 /* unit mask is default choice */ #define INTEL_X86_GRP_EXCL 0x0010 /* only one unit mask group can be selected */ #define INTEL_X86_NHM_OFFCORE 0x0020 /* Nehalem/Westmere offcore_response */ #define INTEL_X86_EXCL_GRP_GT 0x0040 /* exclude use of grp with id > own grp */ #define INTEL_X86_FIXED 0x0080 /* fixed counter only event */ #define INTEL_X86_NO_AUTOENCODE 0x0100 /* does not support auto encoding validation */ #define INTEL_X86_CODE_OVERRIDE 0x0200 /* umask overrides event code */ #define INTEL_X86_LDLAT 0x0400 /* needs load latency modifier (ldlat) */ #define INTEL_X86_GRP_DFL_NONE 0x0800 /* ok if umask group defaults to no umask */ #define INTEL_X86_FRONTEND 0x1000 /* Skylake Precise frontend */ #define INTEL_X86_FETHR 0x2000 /* precise frontend umask requires threshold modifier (fe_thres) */ #define INTEL_X86_EXCL_GRP_BUT_0 0x4000 /* exclude all groups except self and grpid = 0 */ typedef union pfm_intel_x86_reg { unsigned long long val; /* complete register value */ struct { unsigned long sel_event_select:8; /* event mask */ unsigned long sel_unit_mask:8; /* unit mask */ unsigned long sel_usr:1; /* user level */ unsigned long sel_os:1; /* system level */ unsigned long sel_edge:1; /* edge detec */ unsigned long sel_pc:1; /* pin control */ unsigned long sel_int:1; /* enable APIC intr */ unsigned long sel_anythr:1; /* measure any thread */ unsigned long sel_en:1; /* enable */ unsigned long sel_inv:1; /* invert counter mask */ unsigned long sel_cnt_mask:8; /* counter mask */ unsigned long sel_intx:1; /* only in tx region */ unsigned long sel_intxcp:1; /* excl. aborted tx region */ unsigned long sel_res2:30; } perfevtsel; struct { unsigned long usel_event:8; /* event select */ unsigned long usel_umask:8; /* event unit mask */ unsigned long usel_res1:1; /* reserved */ unsigned long usel_occ:1; /* occupancy reset */ unsigned long usel_edge:1; /* edge detection */ unsigned long usel_res2:1; /* reserved */ unsigned long usel_int:1; /* PMI enable */ unsigned long usel_res3:1; /* reserved */ unsigned long usel_en:1; /* enable */ unsigned long usel_inv:1; /* invert */ unsigned long usel_cnt_mask:8; /* counter mask */ unsigned long usel_res4:32; /* reserved */ } nhm_unc; struct { unsigned long usel_en:1; /* enable */ unsigned long usel_res1:1; unsigned long usel_int:1; /* PMI enable */ unsigned long usel_res2:32; unsigned long usel_res3:29; } nhm_unc_fixed; struct { unsigned long cpl_eq0:1; /* filter out branches at pl0 */ unsigned long cpl_neq0:1; /* filter out branches at pl1-pl3 */ unsigned long jcc:1; /* filter out condition branches */ unsigned long near_rel_call:1; /* filter out near relative calls */ unsigned long near_ind_call:1; /* filter out near indirect calls */ unsigned long near_ret:1; /* filter out near returns */ unsigned long near_ind_jmp:1; /* filter out near unconditional jmp/calls */ unsigned long near_rel_jmp:1; /* filter out near uncoditional relative jmp */ unsigned long far_branch:1; /* filter out far branches */ unsigned long reserved1:23; /* reserved */ unsigned long reserved2:32; /* reserved */ } nhm_lbr_select; } pfm_intel_x86_reg_t; #define INTEL_X86_ATTR_K 0 /* kernel (0) */ #define INTEL_X86_ATTR_U 1 /* user (1, 2, 3) */ #define INTEL_X86_ATTR_E 2 /* edge */ #define INTEL_X86_ATTR_I 3 /* invert */ #define INTEL_X86_ATTR_C 4 /* counter mask */ #define INTEL_X86_ATTR_T 5 /* any thread */ #define INTEL_X86_ATTR_LDLAT 6 /* load latency threshold */ #define INTEL_X86_ATTR_INTX 7 /* in transaction */ #define INTEL_X86_ATTR_INTXCP 8 /* not aborted transaction */ #define INTEL_X86_ATTR_FETHR 9 /* precise frontend latency theshold */ #define _INTEL_X86_ATTR_U (1 << INTEL_X86_ATTR_U) #define _INTEL_X86_ATTR_K (1 << INTEL_X86_ATTR_K) #define _INTEL_X86_ATTR_I (1 << INTEL_X86_ATTR_I) #define _INTEL_X86_ATTR_E (1 << INTEL_X86_ATTR_E) #define _INTEL_X86_ATTR_C (1 << INTEL_X86_ATTR_C) #define _INTEL_X86_ATTR_T (1 << INTEL_X86_ATTR_T) #define _INTEL_X86_ATTR_INTX (1 << INTEL_X86_ATTR_INTX) #define _INTEL_X86_ATTR_INTXCP (1 << INTEL_X86_ATTR_INTXCP) #define _INTEL_X86_ATTR_LDLAT (1 << INTEL_X86_ATTR_LDLAT) #define _INTEL_X86_ATTR_FETHR (1 << INTEL_X86_ATTR_FETHR) #define INTEL_X86_ATTRS \ (_INTEL_X86_ATTR_I|_INTEL_X86_ATTR_E|_INTEL_X86_ATTR_C|_INTEL_X86_ATTR_U|_INTEL_X86_ATTR_K) #define INTEL_V1_ATTRS INTEL_X86_ATTRS #define INTEL_V2_ATTRS INTEL_X86_ATTRS #define INTEL_FIXED2_ATTRS (_INTEL_X86_ATTR_U|_INTEL_X86_ATTR_K) #define INTEL_FIXED3_ATTRS (INTEL_FIXED2_ATTRS|_INTEL_X86_ATTR_T) #define INTEL_V3_ATTRS (INTEL_V2_ATTRS|_INTEL_X86_ATTR_T) #define INTEL_V4_ATTRS (INTEL_V3_ATTRS | _INTEL_X86_ATTR_INTX | _INTEL_X86_ATTR_INTXCP) #define INTEL_SKL_FE_ATTRS (INTEL_V4_ATTRS | _INTEL_X86_ATTR_FETHR) /* let's define some handy shortcuts! */ #define sel_event_select perfevtsel.sel_event_select #define sel_unit_mask perfevtsel.sel_unit_mask #define sel_usr perfevtsel.sel_usr #define sel_os perfevtsel.sel_os #define sel_edge perfevtsel.sel_edge #define sel_pc perfevtsel.sel_pc #define sel_int perfevtsel.sel_int #define sel_en perfevtsel.sel_en #define sel_inv perfevtsel.sel_inv #define sel_cnt_mask perfevtsel.sel_cnt_mask #define sel_anythr perfevtsel.sel_anythr #define sel_intx perfevtsel.sel_intx #define sel_intxcp perfevtsel.sel_intxcp /* * shift relative to start of register */ #define INTEL_X86_EDGE_BIT 18 #define INTEL_X86_ANY_BIT 21 #define INTEL_X86_INV_BIT 23 #define INTEL_X86_CMASK_BIT 24 #define INTEL_X86_MOD_EDGE (1 << INTEL_X86_EDGE_BIT) #define INTEL_X86_MOD_ANY (1 << INTEL_X86_ANY_BIT) #define INTEL_X86_MOD_INV (1 << INTEL_X86_INV_BIT) /* intel x86 core PMU supported plm */ #define INTEL_X86_PLM (PFM_PLM0|PFM_PLM3) /* * Intel x86 specific pmu flags (pmu->flags 16 MSB) */ #define INTEL_X86_PMU_FL_ECMASK 0x10000 /* edge requires cmask >=1 */ /* * default ldlat value for PEBS-LL events. Used when ldlat= is missing */ #define INTEL_X86_LDLAT_DEFAULT 3 /* default ldlat value in core cycles */ #define INTEL_X86_FETHR_DEFAULT 1 /* default fe_thres value in core cycles */ typedef struct { unsigned int version:8; unsigned int num_cnt:8; unsigned int cnt_width:8; unsigned int ebx_length:8; } intel_x86_pmu_eax_t; typedef struct { unsigned int num_cnt:6; unsigned int cnt_width:6; unsigned int reserved:20; } intel_x86_pmu_edx_t; typedef struct { unsigned int no_core_cycle:1; unsigned int no_inst_retired:1; unsigned int no_ref_cycle:1; unsigned int no_llc_ref:1; unsigned int no_llc_miss:1; unsigned int no_br_retired:1; unsigned int no_br_mispred_retired:1; unsigned int reserved:25; } intel_x86_pmu_ebx_t; typedef struct { int model; int family; /* 0 means nothing detected yet */ int arch_version; int stepping; } pfm_intel_x86_config_t; extern pfm_intel_x86_config_t pfm_intel_x86_cfg; extern const pfmlib_attr_desc_t intel_x86_mods[]; static inline int intel_x86_eflag(void *this, int idx, int flag) { const intel_x86_entry_t *pe = this_pe(this); return !!(pe[idx].flags & flag); } static inline int is_model_event(void *this, int pidx) { pfmlib_pmu_t *pmu = this; const intel_x86_entry_t *pe = this_pe(this); unsigned short model; model = pe[pidx].model; return model == 0 || model == pmu->pmu; } static inline int is_model_umask(void *this, int pidx, int attr) { pfmlib_pmu_t *pmu = this; const intel_x86_entry_t *pe = this_pe(this); const intel_x86_entry_t *ent; unsigned short model; ent = pe + pidx; model = ent->umasks[attr].umodel; return model == 0 || model == pmu->pmu; } static inline int intel_x86_uflag(void *this, int idx, int attr, int flag) { const intel_x86_entry_t *pe = this_pe(this); return !!(pe[idx].umasks[attr].uflags & flag); } static inline unsigned int intel_x86_num_umasks(void *this, int pidx) { pfmlib_pmu_t *pmu = this; const intel_x86_entry_t *pe = this_pe(this); unsigned int i, n = 0; unsigned short model; /* * some umasks may be model specific */ for (i = 0; i < pe[pidx].numasks; i++) { model = pe[pidx].umasks[i].umodel; if (model && model != pmu->pmu) continue; n++; } return n; } /* * find actual index of umask based on attr_idx */ static inline int intel_x86_attr2umask(void *this, int pidx, int attr_idx) { const intel_x86_entry_t *pe = this_pe(this); unsigned int i; for (i = 0; i < pe[pidx].numasks; i++) { if (!is_model_umask(this, pidx, i)) continue; if (attr_idx == 0) break; attr_idx--; } return i; } extern int pfm_intel_x86_detect(void); extern int pfm_intel_x86_add_defaults(void *this, pfmlib_event_desc_t *e, unsigned int msk, uint64_t *umask, unsigned short max_grpid, int excl_grp_but_0); extern int pfm_intel_x86_event_is_valid(void *this, int pidx); extern int pfm_intel_x86_get_encoding(void *this, pfmlib_event_desc_t *e); extern int pfm_intel_x86_get_event_first(void *this); extern int pfm_intel_x86_get_event_next(void *this, int idx); extern int pfm_intel_x86_get_event_umask_first(void *this, int idx); extern int pfm_intel_x86_get_event_umask_next(void *this, int idx, int attr); extern int pfm_intel_x86_validate_table(void *this, FILE *fp); extern int pfm_intel_x86_get_event_attr_info(void *this, int idx, int attr_idx, pfmlib_event_attr_info_t *info); extern int pfm_intel_x86_get_event_info(void *this, int idx, pfm_event_info_t *info); extern int pfm_intel_x86_valid_pebs(pfmlib_event_desc_t *e); extern int pfm_intel_x86_perf_event_encoding(pfmlib_event_desc_t *e, void *data); extern int pfm_intel_x86_perf_detect(void *this); extern unsigned int pfm_intel_x86_get_event_nattrs(void *this, int pidx); extern int intel_x86_attr2mod(void *this, int pidx, int attr_idx); extern int pfm_intel_x86_get_perf_encoding(void *this, pfmlib_event_desc_t *e); extern int pfm_intel_nhm_unc_get_perf_encoding(void *this, pfmlib_event_desc_t *e); extern void pfm_intel_x86_perf_validate_pattrs(void *this, pfmlib_event_desc_t *e); extern int pfm_intel_x86_can_auto_encode(void *this, int pidx, int uidx); extern int pfm_intel_x86_model_detect(void *this); #endif /* __PFMLIB_INTEL_X86_PRIV_H__ */ libpfm-4.9.0/lib/pfmlib_intel_knl_unc_imc.c0000664000175000017500000001013513223402656020535 0ustar eranianeranian/* * pfmlib_intel_knl_unc_imc.c : Intel KnightsLanding Integrated Memory Controller (IMC) uncore PMU * * Copyright (c) 2016 Intel Corp. All rights reserved * Contributed by Peinan Zhang * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_intel_x86_priv.h" #include "pfmlib_intel_snbep_unc_priv.h" #include "events/intel_knl_unc_imc_events.h" #define DEFINE_IMC_BOX(n) \ pfmlib_pmu_t intel_knl_unc_imc##n##_support = { \ .desc = "Intel KnightLanding IMC "#n" uncore", \ .name = "knl_unc_imc"#n, \ .perf_name = "uncore_imc_"#n, \ .pmu = PFM_PMU_INTEL_KNL_UNC_IMC##n, \ .pme_count = LIBPFM_ARRAY_SIZE(intel_knl_unc_imc_pe), \ .type = PFM_PMU_TYPE_UNCORE, \ .num_cntrs = 4, \ .num_fixed_cntrs = 1, \ .max_encoding = 1, \ .pe = intel_knl_unc_imc_pe, \ .atdesc = snbep_unc_mods, \ .flags = PFMLIB_PMU_FL_RAW_UMASK, \ .pmu_detect = pfm_intel_knl_unc_detect, \ .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding, \ PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding), \ PFMLIB_OS_DETECT(pfm_intel_x86_perf_detect), \ .get_event_first = pfm_intel_x86_get_event_first, \ .get_event_next = pfm_intel_x86_get_event_next, \ .event_is_valid = pfm_intel_x86_event_is_valid, \ .validate_table = pfm_intel_x86_validate_table, \ .get_event_info = pfm_intel_x86_get_event_info, \ .get_event_attr_info = pfm_intel_x86_get_event_attr_info, \ PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs), \ .get_event_nattrs = pfm_intel_x86_get_event_nattrs, \ }; DEFINE_IMC_BOX(0); DEFINE_IMC_BOX(1); DEFINE_IMC_BOX(2); DEFINE_IMC_BOX(3); DEFINE_IMC_BOX(4); DEFINE_IMC_BOX(5); #define DEFINE_IMC_UCLK_BOX(n) \ pfmlib_pmu_t intel_knl_unc_imc_uclk##n##_support = { \ .desc = "Intel KnightLanding IMC UCLK "#n" uncore", \ .name = "knl_unc_imc_uclk"#n, \ .perf_name = "uncore_mc_uclk_"#n, \ .pmu = PFM_PMU_INTEL_KNL_UNC_IMC_UCLK##n, \ .pme_count = LIBPFM_ARRAY_SIZE(intel_knl_unc_imc_uclk_pe), \ .type = PFM_PMU_TYPE_UNCORE, \ .num_cntrs = 4, \ .num_fixed_cntrs = 1, \ .max_encoding = 1, \ .pe = intel_knl_unc_imc_uclk_pe, \ .atdesc = snbep_unc_mods, \ .flags = PFMLIB_PMU_FL_RAW_UMASK, \ .pmu_detect = pfm_intel_knl_unc_detect, \ .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding, \ PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding), \ PFMLIB_OS_DETECT(pfm_intel_x86_perf_detect), \ .get_event_first = pfm_intel_x86_get_event_first, \ .get_event_next = pfm_intel_x86_get_event_next, \ .event_is_valid = pfm_intel_x86_event_is_valid, \ .validate_table = pfm_intel_x86_validate_table, \ .get_event_info = pfm_intel_x86_get_event_info, \ .get_event_attr_info = pfm_intel_x86_get_event_attr_info, \ PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs), \ .get_event_nattrs = pfm_intel_x86_get_event_nattrs, \ }; DEFINE_IMC_UCLK_BOX(0); DEFINE_IMC_UCLK_BOX(1); libpfm-4.9.0/lib/pfmlib_intel_coreduo.c0000664000175000017500000000540013223402656017713 0ustar eranianeranian/* * pfmlib_intel_coreduo.c : Intel Core Duo/Solo (Yonah) * * Copyright (c) 2009, Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ /* private headers */ #include "pfmlib_priv.h" /* library private */ #include "pfmlib_intel_x86_priv.h" /* architecture private */ #include "events/intel_coreduo_events.h" static int pfm_coreduo_detect(void *this) { int ret; ret = pfm_intel_x86_detect(); if (ret != PFM_SUCCESS) return ret; /* * check for core solo/core duo */ if (pfm_intel_x86_cfg.family != 6) return PFM_ERR_NOTSUPP; if (pfm_intel_x86_cfg.model != 14) return PFM_ERR_NOTSUPP; return PFM_SUCCESS; } static int pfm_coreduo_init(void *this) { pfm_intel_x86_cfg.arch_version = 1; return PFM_SUCCESS; } pfmlib_pmu_t intel_coreduo_support={ .desc = "Intel Core Duo/Core Solo", .name = "coreduo", .pmu = PFM_PMU_COREDUO, .pme_count = LIBPFM_ARRAY_SIZE(intel_coreduo_pe), .type = PFM_PMU_TYPE_CORE, .num_cntrs = 2, .max_encoding = 1, .pe = intel_coreduo_pe, .atdesc = intel_x86_mods, .flags = PFMLIB_PMU_FL_RAW_UMASK, .supported_plm = INTEL_X86_PLM, .pmu_detect = pfm_coreduo_detect, .pmu_init = pfm_coreduo_init, .get_event_encoding[PFM_OS_NONE] = pfm_intel_x86_get_encoding, PFMLIB_ENCODE_PERF(pfm_intel_x86_get_perf_encoding), .get_event_first = pfm_intel_x86_get_event_first, .get_event_next = pfm_intel_x86_get_event_next, .event_is_valid = pfm_intel_x86_event_is_valid, .validate_table = pfm_intel_x86_validate_table, .get_event_info = pfm_intel_x86_get_event_info, .get_event_attr_info = pfm_intel_x86_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_intel_x86_perf_validate_pattrs), .get_event_nattrs = pfm_intel_x86_get_event_nattrs, }; libpfm-4.9.0/lib/pfmlib_arm_armv6.c0000664000175000017500000000476213223402656016764 0ustar eranianeranian/* * pfmlib_arm_armv6.c : support for ARMv6 chips * * Copyright (c) 2013 by Vince Weaver * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ #include #include #include #include #include /* private headers */ #include "pfmlib_priv.h" /* library private */ #include "pfmlib_arm_priv.h" #include "events/arm_1176_events.h" /* event tables */ static int pfm_arm_detect_1176(void *this) { int ret; ret = pfm_arm_detect(this); if (ret != PFM_SUCCESS) return PFM_ERR_NOTSUPP; if ((pfm_arm_cfg.implementer == 0x41) && /* ARM */ (pfm_arm_cfg.part==0xb76)) { /* 1176 */ return PFM_SUCCESS; } return PFM_ERR_NOTSUPP; } /* ARM1176 support */ pfmlib_pmu_t arm_1176_support={ .desc = "ARM1176", .name = "arm_1176", .pmu = PFM_PMU_ARM_1176, .pme_count = LIBPFM_ARRAY_SIZE(arm_1176_pe), .type = PFM_PMU_TYPE_CORE, .pe = arm_1176_pe, .pmu_detect = pfm_arm_detect_1176, .max_encoding = 1, .num_cntrs = 2, .get_event_encoding[PFM_OS_NONE] = pfm_arm_get_encoding, PFMLIB_ENCODE_PERF(pfm_arm_get_perf_encoding), .get_event_first = pfm_arm_get_event_first, .get_event_next = pfm_arm_get_event_next, .event_is_valid = pfm_arm_event_is_valid, .validate_table = pfm_arm_validate_table, .get_event_info = pfm_arm_get_event_info, .get_event_attr_info = pfm_arm_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_arm_perf_validate_pattrs), .get_event_nattrs = pfm_arm_get_event_nattrs, }; libpfm-4.9.0/lib/pfmlib_intel_nhm_unc.c0000664000175000017500000002375113223402656017713 0ustar eranianeranian/* * pfmlib_intel_nhm_unc.c : Intel Nehalem/Westmere uncore PMU * * Copyright (c) 2008 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_intel_x86_priv.h" #define NHM_UNC_ATTR_E 0 #define NHM_UNC_ATTR_I 1 #define NHM_UNC_ATTR_C 2 #define NHM_UNC_ATTR_O 3 #define _NHM_UNC_ATTR_I (1 << NHM_UNC_ATTR_I) #define _NHM_UNC_ATTR_E (1 << NHM_UNC_ATTR_E) #define _NHM_UNC_ATTR_C (1 << NHM_UNC_ATTR_C) #define _NHM_UNC_ATTR_O (1 << NHM_UNC_ATTR_O) #define NHM_UNC_ATTRS \ (_NHM_UNC_ATTR_I|_NHM_UNC_ATTR_E|_NHM_UNC_ATTR_C|_NHM_UNC_ATTR_O) #define NHM_UNC_MOD_OCC_BIT 17 #define NHM_UNC_MOD_EDGE_BIT 18 #define NHM_UNC_MOD_INV_BIT 23 #define NHM_UNC_MOD_CMASK_BIT 24 #define NHM_UNC_MOD_OCC (1 << NHM_UNC_MOD_OCC_BIT) #define NHM_UNC_MOD_EDGE (1 << NHM_UNC_MOD_EDGE_BIT) #define NHM_UNC_MOD_INV (1 << NHM_UNC_MOD_INV_BIT) /* Intel Nehalem/Westmere uncore event table */ #include "events/intel_nhm_unc_events.h" #include "events/intel_wsm_unc_events.h" static const pfmlib_attr_desc_t nhm_unc_mods[]={ PFM_ATTR_B("e", "edge level"), /* edge */ PFM_ATTR_B("i", "invert"), /* invert */ PFM_ATTR_I("c", "counter-mask in range [0-255]"), /* counter-mask */ PFM_ATTR_B("o", "queue occupancy"), /* queue occupancy */ PFM_ATTR_NULL }; static const int nhm_models[] = { 26, 30, 31, 0 }; static const int wsm_dp_models[] = { 44, /* Westmere-EP, Gulftown */ 47, /* Westmere E7 */ 0, }; static int pfm_nhm_unc_get_encoding(void *this, pfmlib_event_desc_t *e) { pfm_intel_x86_reg_t reg; pfmlib_event_attr_info_t *a; const intel_x86_entry_t *pe = this_pe(this); unsigned int grpmsk, ugrpmsk = 0; int umodmsk = 0, modmsk_r = 0; uint64_t val; uint64_t umask; unsigned int modhw = 0; int k, ret, grpid, last_grpid = -1; int grpcounts[INTEL_X86_NUM_GRP]; int ncombo[INTEL_X86_NUM_GRP]; char umask_str[PFMLIB_EVT_MAX_NAME_LEN]; memset(grpcounts, 0, sizeof(grpcounts)); memset(ncombo, 0, sizeof(ncombo)); pe = this_pe(this); umask_str[0] = e->fstr[0] = '\0'; reg.val = 0; val = pe[e->event].code; grpmsk = (1 << pe[e->event].ngrp)-1; reg.val |= val; /* preset some filters from code */ /* take into account hardcoded umask */ umask = (val >> 8) & 0xff; modmsk_r = pe[e->event].modmsk_req; for(k=0; k < e->nattrs; k++) { a = attr(e, k); if (a->ctrl != PFM_ATTR_CTRL_PMU) continue; if (a->type == PFM_ATTR_UMASK) { grpid = pe[e->event].umasks[a->idx].grpid; /* * cfor certain events groups are meant to be * exclusive, i.e., only unit masks of one group * can be used */ if (last_grpid != -1 && grpid != last_grpid && intel_x86_eflag(this, e->event, INTEL_X86_GRP_EXCL)) { DPRINT("exclusive unit mask group error\n"); return PFM_ERR_FEATCOMB; } /* * upper layer has removed duplicates * so if we come here more than once, it is for two * disinct umasks * * NCOMBO=no combination of unit masks within the same * umask group */ ++grpcounts[grpid]; if (intel_x86_uflag(this, e->event, a->idx, INTEL_X86_NCOMBO)) ncombo[grpid] = 1; if (grpcounts[grpid] > 1 && ncombo[grpid]) { DPRINT("event does not support unit mask combination within a group\n"); return PFM_ERR_FEATCOMB; } evt_strcat(umask_str, ":%s", pe[e->event].umasks[a->idx].uname); last_grpid = grpid; modhw |= pe[e->event].umasks[a->idx].modhw; umask |= pe[e->event].umasks[a->idx].ucode >> 8; ugrpmsk |= 1 << pe[e->event].umasks[a->idx].grpid; reg.val |= umask << 8; modmsk_r |= pe[e->event].umasks[a->idx].umodmsk_req; } else if (a->type == PFM_ATTR_RAW_UMASK) { /* there can only be one RAW_UMASK per event */ /* sanity check */ if (a->idx & ~0xff) { DPRINT("raw umask is 8-bit wide\n"); return PFM_ERR_ATTR; } /* override umask */ umask = a->idx & 0xff; ugrpmsk = grpmsk; } else { uint64_t ival = e->attrs[k].ival; switch(a->idx) { case NHM_UNC_ATTR_I: /* invert */ reg.nhm_unc.usel_inv = !!ival; umodmsk |= _NHM_UNC_ATTR_I; break; case NHM_UNC_ATTR_E: /* edge */ reg.nhm_unc.usel_edge = !!ival; umodmsk |= _NHM_UNC_ATTR_E; break; case NHM_UNC_ATTR_C: /* counter-mask */ /* already forced, cannot overwrite */ if (ival > 255) return PFM_ERR_INVAL; reg.nhm_unc.usel_cnt_mask = ival; umodmsk |= _NHM_UNC_ATTR_C; break; case NHM_UNC_ATTR_O: /* occupancy */ reg.nhm_unc.usel_occ = !!ival; umodmsk |= _NHM_UNC_ATTR_O; break; } } } if ((modhw & _NHM_UNC_ATTR_I) && reg.nhm_unc.usel_inv) return PFM_ERR_ATTR_SET; if ((modhw & _NHM_UNC_ATTR_E) && reg.nhm_unc.usel_edge) return PFM_ERR_ATTR_SET; if ((modhw & _NHM_UNC_ATTR_C) && reg.nhm_unc.usel_cnt_mask) return PFM_ERR_ATTR_SET; if ((modhw & _NHM_UNC_ATTR_O) && reg.nhm_unc.usel_occ) return PFM_ERR_ATTR_SET; /* * check that there is at least of unit mask in each unit * mask group */ if ((ugrpmsk != grpmsk && !intel_x86_eflag(this, e->event, INTEL_X86_GRP_EXCL)) || ugrpmsk == 0) { ugrpmsk ^= grpmsk; ret = pfm_intel_x86_add_defaults(this, e, ugrpmsk, &umask, -1, -1); if (ret != PFM_SUCCESS) return ret; } if (modmsk_r && (umodmsk ^ modmsk_r)) { DPRINT("required modifiers missing: 0x%x\n", modmsk_r); return PFM_ERR_ATTR; } evt_strcat(e->fstr, "%s", pe[e->event].name); pfmlib_sort_attr(e); for(k=0; k < e->nattrs; k++) { a = attr(e, k); if (a->ctrl != PFM_ATTR_CTRL_PMU) continue; if (a->type == PFM_ATTR_UMASK) evt_strcat(e->fstr, ":%s", pe[e->event].umasks[a->idx].uname); else if (a->type == PFM_ATTR_RAW_UMASK) evt_strcat(e->fstr, ":0x%x", a->idx); } reg.val |= umask << 8; reg.nhm_unc.usel_en = 1; /* force enable bit to 1 */ reg.nhm_unc.usel_int = 1; /* force APIC int to 1 */ e->codes[0] = reg.val; e->count = 1; for (k = 0; k < e->npattrs; k++) { int idx; if (e->pattrs[k].ctrl != PFM_ATTR_CTRL_PMU) continue; if (e->pattrs[k].type == PFM_ATTR_UMASK) continue; idx = e->pattrs[k].idx; switch(idx) { case NHM_UNC_ATTR_E: evt_strcat(e->fstr, ":%s=%lu", nhm_unc_mods[idx].name, reg.nhm_unc.usel_edge); break; case NHM_UNC_ATTR_I: evt_strcat(e->fstr, ":%s=%lu", nhm_unc_mods[idx].name, reg.nhm_unc.usel_inv); break; case NHM_UNC_ATTR_C: evt_strcat(e->fstr, ":%s=%lu", nhm_unc_mods[idx].name, reg.nhm_unc.usel_cnt_mask); break; case NHM_UNC_ATTR_O: evt_strcat(e->fstr, ":%s=%lu", nhm_unc_mods[idx].name, reg.nhm_unc.usel_occ); break; } } __pfm_vbprintf("[UNC_PERFEVTSEL=0x%"PRIx64" event=0x%x umask=0x%x en=%d int=%d inv=%d edge=%d occ=%d cnt_msk=%d] %s\n", reg.val, reg.nhm_unc.usel_event, reg.nhm_unc.usel_umask, reg.nhm_unc.usel_en, reg.nhm_unc.usel_int, reg.nhm_unc.usel_inv, reg.nhm_unc.usel_edge, reg.nhm_unc.usel_occ, reg.nhm_unc.usel_cnt_mask, pe[e->event].name); return PFM_SUCCESS; } pfmlib_pmu_t intel_nhm_unc_support={ .desc = "Intel Nehalem uncore", .name = "nhm_unc", .perf_name = "uncore", .pmu = PFM_PMU_INTEL_NHM_UNC, .pme_count = LIBPFM_ARRAY_SIZE(intel_nhm_unc_pe), .type = PFM_PMU_TYPE_UNCORE, .num_cntrs = 8, .num_fixed_cntrs = 1, .max_encoding = 1, .pe = intel_nhm_unc_pe, .atdesc = nhm_unc_mods, .flags = PFMLIB_PMU_FL_RAW_UMASK, .cpu_family = 6, .cpu_models = nhm_models, .pmu_detect = pfm_intel_x86_model_detect, .get_event_encoding[PFM_OS_NONE] = pfm_nhm_unc_get_encoding, PFMLIB_ENCODE_PERF(pfm_intel_nhm_unc_get_perf_encoding), .get_event_first = pfm_intel_x86_get_event_first, .get_event_next = pfm_intel_x86_get_event_next, .event_is_valid = pfm_intel_x86_event_is_valid, .validate_table = pfm_intel_x86_validate_table, .get_event_info = pfm_intel_x86_get_event_info, .get_event_attr_info = pfm_intel_x86_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_intel_x86_perf_validate_pattrs), .get_event_nattrs = pfm_intel_x86_get_event_nattrs, }; pfmlib_pmu_t intel_wsm_unc_support={ .desc = "Intel Westmere uncore", .name = "wsm_unc", .perf_name = "uncore", .pmu = PFM_PMU_INTEL_WSM_UNC, .pme_count = LIBPFM_ARRAY_SIZE(intel_wsm_unc_pe), .type = PFM_PMU_TYPE_UNCORE, .num_cntrs = 8, .num_fixed_cntrs = 1, .max_encoding = 1, .pe = intel_wsm_unc_pe, .atdesc = nhm_unc_mods, .flags = PFMLIB_PMU_FL_RAW_UMASK, .cpu_family = 6, .cpu_models = wsm_dp_models, .pmu_detect = pfm_intel_x86_model_detect, .get_event_encoding[PFM_OS_NONE] = pfm_nhm_unc_get_encoding, PFMLIB_ENCODE_PERF(pfm_intel_nhm_unc_get_perf_encoding), .get_event_first = pfm_intel_x86_get_event_first, .get_event_next = pfm_intel_x86_get_event_next, .event_is_valid = pfm_intel_x86_event_is_valid, .validate_table = pfm_intel_x86_validate_table, .get_event_info = pfm_intel_x86_get_event_info, .get_event_attr_info = pfm_intel_x86_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_intel_x86_perf_validate_pattrs), .get_event_nattrs = pfm_intel_x86_get_event_nattrs, }; libpfm-4.9.0/lib/events/0000775000175000017500000000000013223402656014670 5ustar eranianeranianlibpfm-4.9.0/lib/events/arm_qcom_krait_events.h0000664000175000017500000000430613223402656021420 0ustar eranianeranian/* * Copyright (c) 2014 by Vince Weaver * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * Qualcomm Krait Chips * based on info in the thread on linux-kernel: * [PATCH 0/7] Support Krait CPU PMUs */ static const arm_entry_t arm_qcom_krait_pe[]={ {.name = "L1D_CACHE_REFILL", .modmsk = ARMV7_A15_ATTRS, .code = 0x03, .desc = "Level 1 data cache refill" }, {.name = "L1D_CACHE_ACCESS", .modmsk = ARMV7_A15_ATTRS, .code = 0x04, .desc = "Level 1 data cache access" }, {.name = "INSTR_EXECUTED", .modmsk = ARMV7_A15_ATTRS, .code = 0x08, .desc = "Instructions architecturally executed" }, {.name = "PC_WRITE", .modmsk = ARMV7_A15_ATTRS, .code = 0x0c, .desc = "Software change of PC. Equivalent to branches" }, {.name = "PC_BRANCH_MIS_PRED", .modmsk = ARMV7_A15_ATTRS, .code = 0x10, .desc = "Branches mispredicted or not predicted" }, {.name = "CLOCK_CYCLES", .modmsk = ARMV7_A15_ATTRS, .code = 0x11, .desc = "Cycles" }, {.name = "BRANCH_PRED", .modmsk = ARMV7_A15_ATTRS, .code = 0x12, .desc = "Predictable branch speculatively executed" }, {.name = "CPU_CYCLES", .modmsk = ARMV7_A15_ATTRS, .code = 0xff, .desc = "Cycles" }, }; libpfm-4.9.0/lib/events/amd64_events_fam11h.h0000664000175000017500000011520013223402656020474 0ustar eranianeranian/* * Copyright (c) 2012 University of Tennessee * Contributed by Vince Weaver * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * PMU: amd64_fam11h (AMD64 Fam11h) */ static const amd64_umask_t amd64_fam11h_dispatched_fpu[]={ { .uname = "OPS_ADD", .udesc = "Add pipe ops excluding load ops and SSE move ops", .ucode = 0x1, }, { .uname = "OPS_MULTIPLY", .udesc = "Multiply pipe ops excluding load ops and SSE move ops", .ucode = 0x2, }, { .uname = "OPS_STORE", .udesc = "Store pipe ops excluding load ops and SSE move ops", .ucode = 0x4, }, { .uname = "OPS_ADD_PIPE_LOAD_OPS", .udesc = "Add pipe load ops and SSE move ops", .ucode = 0x8, }, { .uname = "OPS_MULTIPLY_PIPE_LOAD_OPS", .udesc = "Multiply pipe load ops and SSE move ops", .ucode = 0x10, }, { .uname = "OPS_STORE_PIPE_LOAD_OPS", .udesc = "Store pipe load ops and SSE move ops", .ucode = 0x20, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam11h_segment_register_loads[]={ { .uname = "ES", .udesc = "ES", .ucode = 0x1, }, { .uname = "CS", .udesc = "CS", .ucode = 0x2, }, { .uname = "SS", .udesc = "SS", .ucode = 0x4, }, { .uname = "DS", .udesc = "DS", .ucode = 0x8, }, { .uname = "FS", .udesc = "FS", .ucode = 0x10, }, { .uname = "GS", .udesc = "GS", .ucode = 0x20, }, { .uname = "HS", .udesc = "HS", .ucode = 0x40, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x7f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam11h_locked_ops[]={ { .uname = "EXECUTED", .udesc = "The number of locked instructions executed", .ucode = 0x1, }, { .uname = "CYCLES_SPECULATIVE_PHASE", .udesc = "The number of cycles spent in speculative phase", .ucode = 0x2, }, { .uname = "CYCLES_NON_SPECULATIVE_PHASE", .udesc = "The number of cycles spent in non-speculative phase (including cache miss penalty)", .ucode = 0x4, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x7, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam11h_data_cache_refills[]={ { .uname = "SYSTEM", .udesc = "Refill from the Northbridge", .ucode = 0x1, }, { .uname = "L2_SHARED", .udesc = "Shared-state line from L2", .ucode = 0x2, }, { .uname = "L2_EXCLUSIVE", .udesc = "Exclusive-state line from L2", .ucode = 0x4, }, { .uname = "L2_OWNED", .udesc = "Owned-state line from L2", .ucode = 0x8, }, { .uname = "L2_MODIFIED", .udesc = "Modified-state line from L2", .ucode = 0x10, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x1f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam11h_data_cache_refills_from_system[]={ { .uname = "INVALID", .udesc = "Invalid", .ucode = 0x1, }, { .uname = "SHARED", .udesc = "Shared", .ucode = 0x2, }, { .uname = "EXCLUSIVE", .udesc = "Exclusive", .ucode = 0x4, }, { .uname = "OWNED", .udesc = "Owned", .ucode = 0x8, }, { .uname = "MODIFIED", .udesc = "Modified", .ucode = 0x10, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x1f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam11h_data_cache_lines_evicted[]={ { .uname = "INVALID", .udesc = "Invalid", .ucode = 0x1, }, { .uname = "SHARED", .udesc = "Shared", .ucode = 0x2, }, { .uname = "EXCLUSIVE", .udesc = "Exclusive", .ucode = 0x4, }, { .uname = "OWNED", .udesc = "Owned", .ucode = 0x8, }, { .uname = "MODIFIED", .udesc = "Modified", .ucode = 0x10, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x1f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam11h_scrubber_single_bit_ecc_errors[]={ { .uname = "SCRUBBER_ERROR", .udesc = "Scrubber error", .ucode = 0x1, }, { .uname = "PIGGYBACK_ERROR", .udesc = "Piggyback scrubber errors", .ucode = 0x2, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam11h_prefetch_instructions_dispatched[]={ { .uname = "LOAD", .udesc = "Load (Prefetch, PrefetchT0/T1/T2)", .ucode = 0x1, }, { .uname = "STORE", .udesc = "Store (PrefetchW)", .ucode = 0x2, }, { .uname = "NTA", .udesc = "NTA (PrefetchNTA)", .ucode = 0x4, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x7, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam11h_dcache_misses_by_locked_instructions[]={ { .uname = "DATA_CACHE_MISSES_BY_LOCKED_INSTRUCTIONS", .udesc = "Data cache misses by locked instructions", .ucode = 0x2, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x2, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam11h_memory_requests[]={ { .uname = "NON_CACHEABLE", .udesc = "Requests to non-cacheable (UC) memory", .ucode = 0x1, }, { .uname = "WRITE_COMBINING", .udesc = "Requests to write-combining (WC) memory or WC buffer flushes to WB memory", .ucode = 0x2, }, { .uname = "STREAMING_STORE", .udesc = "Streaming store (SS) requests", .ucode = 0x80, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x83, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam11h_data_prefetches[]={ { .uname = "CANCELLED", .udesc = "Cancelled prefetches", .ucode = 0x1, }, { .uname = "ATTEMPTED", .udesc = "Prefetch attempts", .ucode = 0x2, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam11h_system_read_responses[]={ { .uname = "EXCLUSIVE", .udesc = "Exclusive", .ucode = 0x1, }, { .uname = "MODIFIED", .udesc = "Modified", .ucode = 0x2, }, { .uname = "SHARED", .udesc = "Shared", .ucode = 0x4, }, { .uname = "DATA_ERROR", .udesc = "Data Error", .ucode = 0x10, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x17, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam11h_quadwords_written_to_system[]={ { .uname = "QUADWORD_WRITE_TRANSFER", .udesc = "Quadword write transfer", .ucode = 0x1, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x1, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam11h_requests_to_l2[]={ { .uname = "INSTRUCTIONS", .udesc = "IC fill", .ucode = 0x1, }, { .uname = "DATA", .udesc = "DC fill", .ucode = 0x2, }, { .uname = "TLB_WALK", .udesc = "TLB fill (page table walks)", .ucode = 0x4, }, { .uname = "SNOOP", .udesc = "Tag snoop request", .ucode = 0x8, }, { .uname = "CANCELLED", .udesc = "Cancelled request", .ucode = 0x10, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x1f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam11h_l2_cache_miss[]={ { .uname = "INSTRUCTIONS", .udesc = "IC fill", .ucode = 0x1, }, { .uname = "DATA", .udesc = "DC fill (includes possible replays, whereas EventSelect 041h does not)", .ucode = 0x2, }, { .uname = "TLB_WALK", .udesc = "TLB page table walk", .ucode = 0x4, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x7, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam11h_l2_fill_writeback[]={ { .uname = "L2_FILLS", .udesc = "L2 fills (victims from L1 caches, TLB page table walks and data prefetches)", .ucode = 0x1, }, { .uname = "L2_WRITEBACKS", .udesc = "L2 Writebacks to system.", .ucode = 0x2, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam11h_retired_mmx_and_fp_instructions[]={ { .uname = "X87", .udesc = "X87 instructions", .ucode = 0x1, }, { .uname = "MMX_AND_3DNOW", .udesc = "MMX and 3DNow! instructions", .ucode = 0x2, }, { .uname = "PACKED_SSE_AND_SSE2", .udesc = "Packed SSE and SSE2 instructions", .ucode = 0x4, }, { .uname = "SCALAR_SSE_AND_SSE2", .udesc = "Scalar SSE and SSE2 instructions", .ucode = 0x8, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xf, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam11h_retired_fastpath_double_op_instructions[]={ { .uname = "POSITION_0", .udesc = "With low op in position 0", .ucode = 0x1, }, { .uname = "POSITION_1", .udesc = "With low op in position 1", .ucode = 0x2, }, { .uname = "POSITION_2", .udesc = "With low op in position 2", .ucode = 0x4, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x7, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam11h_interrupt_events[]={ { .uname = "FIXED_AND_LPA", .udesc = "Fixed and LPA", .ucode = 0x1, }, { .uname = "LPA", .udesc = "LPA", .ucode = 0x2, }, { .uname = "SMI", .udesc = "SMI", .ucode = 0x4, }, { .uname = "NMI", .udesc = "NMI", .ucode = 0x8, }, { .uname = "INIT", .udesc = "INIT", .ucode = 0x10, }, { .uname = "STARTUP", .udesc = "STARTUP", .ucode = 0x20, }, { .uname = "INT", .udesc = "INT", .ucode = 0x40, }, { .uname = "EOI", .udesc = "EOI", .ucode = 0x80, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xff, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam11h_sideband_signals[]={ { .uname = "HALT", .udesc = "HALT", .ucode = 0x1, }, { .uname = "STOPGRANT", .udesc = "STOPGRANT", .ucode = 0x2, }, { .uname = "SHUTDOWN", .udesc = "SHUTDOWN", .ucode = 0x4, }, { .uname = "WBINVD", .udesc = "WBINVD", .ucode = 0x8, }, { .uname = "INVD", .udesc = "INVD", .ucode = 0x10, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x1f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam11h_fpu_exceptions[]={ { .uname = "X87_RECLASS_MICROFAULTS", .udesc = "X87 reclass microfaults", .ucode = 0x1, }, { .uname = "SSE_RETYPE_MICROFAULTS", .udesc = "SSE retype microfaults", .ucode = 0x2, }, { .uname = "SSE_RECLASS_MICROFAULTS", .udesc = "SSE reclass microfaults", .ucode = 0x4, }, { .uname = "SSE_AND_X87_MICROTRAPS", .udesc = "SSE and x87 microtraps", .ucode = 0x8, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xf, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam11h_dram_accesses[]={ { .uname = "DCT0_PAGE_HIT", .udesc = "DCT0 Page hit", .ucode = 0x1, }, { .uname = "DCT0_PAGE_MISS", .udesc = "DCT0 Page Miss", .ucode = 0x2, }, { .uname = "DCT0_PAGE_CONFLICT", .udesc = "DCT0 Page Conflict", .ucode = 0x4, }, { .uname = "DCT1_PAGE_HIT", .udesc = "DCT1 Page hit", .ucode = 0x8, }, { .uname = "DCT1_PAGE_MISS", .udesc = "DCT1 Page Miss", .ucode = 0x10, }, { .uname = "DCT1_PAGE_CONFLICT", .udesc = "DCT1 Page Conflict", .ucode = 0x20, }, { .uname = "WRITE_REQUEST", .udesc = "Write request.", .ucode = 0x40, }, { .uname = "READ_REQUEST", .udesc = "Read request.", .ucode = 0x80, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xff, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam11h_dram_controller_page_table_events[]={ { .uname = "DCT_PAGE_TABLE_OVERFLOW", .udesc = "DCT Page Table Overflow", .ucode = 0x1, }, { .uname = "STALE_TABLE_ENTRY_HITS", .udesc = "Number of stale table entry hits. (hit on a page closed too soon).", .ucode = 0x2, }, { .uname = "PAGE_TABLE_IDLE_CYCLE_LIMIT_INCREMENTED", .udesc = "Page table idle cycle limit incremented.", .ucode = 0x4, }, { .uname = "PAGE_TABLE_IDLE_CYCLE_LIMIT_DECREMENTED", .udesc = "Page table idle cycle limit decremented.", .ucode = 0x8, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xf, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam11h_memory_controller_turnarounds[]={ { .uname = "DCT0_READ_TO_WRITE", .udesc = "DCT0 read-to-write turnaround.", .ucode = 0x1, }, { .uname = "DCT0_WRITE_TO_READ", .udesc = "DCT0 write-to-read turnaround", .ucode = 0x2, }, { .uname = "DCT0_DIMM", .udesc = "DCT0 DIMM (chip select) turnaround", .ucode = 0x4, }, { .uname = "DCT1_READ_TO_WRITE", .udesc = "DCT1 read-to-write turnaround.", .ucode = 0x8, }, { .uname = "DCT1_WRITE_TO_READ", .udesc = "DCT1 write-to-read turnaround", .ucode = 0x10, }, { .uname = "DCT1_DIMM", .udesc = "DCT1 DIMM (chip select) turnaround", .ucode = 0x20, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam11h_memory_rbd_queue[]={ { .uname = "COUNTER_REACHED", .udesc = "F2x[1,0]94[DcqBypassMax] counter reached.", .ucode = 0x4, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x4, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam11h_thermal_status[]={ { .uname = "MEMHOT_L_ASSERTIONS", .udesc = "Number of clocks MEMHOT_L is asserted.", .ucode = 0x1, }, { .uname = "HTC_TRANSITIONS", .udesc = "Number of times the HTC transitions from inactive to active.", .ucode = 0x4, }, { .uname = "CLOCKS_HTC_P_STATE_INACTIVE", .udesc = "Number of clocks HTC P-state is inactive.", .ucode = 0x20, }, { .uname = "CLOCKS_HTC_P_STATE_ACTIVE", .udesc = "Number of clocks HTC P-state is active", .ucode = 0x40, }, { .uname = "PROCHOT_L_ASSERTIONS", .udesc = "PROCHOT_L asserted by an external source and the assertion causes a P-state change.", .ucode = 0x80, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xe5, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam11h_cpu_io_requests_to_memory_io[]={ { .uname = "I_O_TO_I_O", .udesc = "IO to IO", .ucode = 0xa1, .uflags= AMD64_FL_NCOMBO, }, { .uname = "I_O_TO_MEM", .udesc = "IO to Mem", .ucode = 0xa2, .uflags= AMD64_FL_NCOMBO, }, { .uname = "CPU_TO_I_O", .udesc = "CPU to IO", .ucode = 0xa4, .uflags= AMD64_FL_NCOMBO, }, { .uname = "CPU_TO_MEM", .udesc = "CPU to Mem", .ucode = 0xa8, .uflags= AMD64_FL_NCOMBO, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xaf, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam11h_cache_block[]={ { .uname = "VICTIM_WRITEBACK", .udesc = "Victim Block (Writeback)", .ucode = 0x1, }, { .uname = "DCACHE_LOAD_MISS", .udesc = "Read Block (Dcache load miss refill)", .ucode = 0x4, }, { .uname = "SHARED_ICACHE_REFILL", .udesc = "Read Block Shared (Icache refill)", .ucode = 0x8, }, { .uname = "READ_BLOCK_MODIFIED", .udesc = "Read Block Modified (Dcache store miss refill)", .ucode = 0x10, }, { .uname = "READ_TO_DIRTY", .udesc = "Change-to-Dirty (first store to clean block already in cache)", .ucode = 0x20, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3d, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam11h_sized_commands[]={ { .uname = "NON_POSTED_WRITE_BYTE", .udesc = "Non-Posted SzWr Byte (1-32 bytes) Legacy or mapped IO, typically 1-4 bytes", .ucode = 0x1, }, { .uname = "NON_POSTED_WRITE_DWORD", .udesc = "Non-Posted SzWr DW (1-16 dwords) Legacy or mapped IO, typically 1 DWORD", .ucode = 0x2, }, { .uname = "POSTED_WRITE_BYTE", .udesc = "Posted SzWr Byte (1-32 bytes) Subcache-line DMA writes, size varies; also flushes of partially-filled Write Combining buffer", .ucode = 0x4, }, { .uname = "POSTED_WRITE_DWORD", .udesc = "Posted SzWr DW (1-16 dwords) Block-oriented DMA writes, often cache-line sized; also processor Write Combining buffer flushes", .ucode = 0x8, }, { .uname = "READ_BYTE_4_BYTES", .udesc = "SzRd Byte (4 bytes) Legacy or mapped IO", .ucode = 0x10, }, { .uname = "READ_DWORD_1_16_DWORDS", .udesc = "SzRd DW (1-16 dwords) Block-oriented DMA reads, typically cache-line size", .ucode = 0x20, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam11h_probe[]={ { .uname = "MISS", .udesc = "Probe miss", .ucode = 0x1, }, { .uname = "HIT_CLEAN", .udesc = "Probe hit clean", .ucode = 0x2, }, { .uname = "HIT_DIRTY_NO_MEMORY_CANCEL", .udesc = "Probe hit dirty without memory cancel (probed by Sized Write or Change2Dirty)", .ucode = 0x4, }, { .uname = "HIT_DIRTY_WITH_MEMORY_CANCEL", .udesc = "Probe hit dirty with memory cancel (probed by DMA read or cache refill request)", .ucode = 0x8, }, { .uname = "UPSTREAM_DISPLAY_REFRESH_READS", .udesc = "Upstream display refresh/ISOC reads.", .ucode = 0x10, }, { .uname = "UPSTREAM_NON_DISPLAY_REFRESH_READS", .udesc = "Upstream non-display refresh reads.", .ucode = 0x20, }, { .uname = "UPSTREAM_ISOC_WRITES", .udesc = "Upstream ISOC writes.", .ucode = 0x40, }, { .uname = "UPSTREAM_NON_ISOC_WRITES", .udesc = "Upstream non-ISOC writes.", .ucode = 0x80, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xff, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam11h_dev[]={ { .uname = "DEV_HIT", .udesc = "DEV hit", .ucode = 0x10, }, { .uname = "DEV_MISS", .udesc = "DEV miss", .ucode = 0x20, }, { .uname = "DEV_ERROR", .udesc = "DEV error", .ucode = 0x40, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x70, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam11h_memory_controller_requests[]={ { .uname = "32_BYTES_WRITES", .udesc = "32 Bytes Sized Writes", .ucode = 0x8, }, { .uname = "64_BYTES_WRITES", .udesc = "64 Bytes Sized Writes", .ucode = 0x10, }, { .uname = "32_BYTES_READS", .udesc = "32 Bytes Sized Reads", .ucode = 0x20, }, { .uname = "64_BYTES_READS", .udesc = "64 Byte Sized Reads", .ucode = 0x40, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x78, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam11h_hypertransport_link0[]={ { .uname = "COMMAND_DWORD_SENT", .udesc = "Command DWORD sent", .ucode = 0x1, .grpid = 0, }, { .uname = "ADDRESS_DWORD_SENT", .udesc = "Address DWORD sent", .ucode = 0x2, .grpid = 0, }, { .uname = "DATA_DWORD_SENT", .udesc = "Data DWORD sent", .ucode = 0x4, .grpid = 0, }, { .uname = "BUFFER_RELEASE_DWORD_SENT", .udesc = "Buffer release DWORD sent", .ucode = 0x8, .grpid = 0, }, { .uname = "NOP_DWORD_SENT", .udesc = "Nop DW sent (idle)", .ucode = 0x10, .grpid = 0, }, { .uname = "PER_PACKET_CRC_SENT", .udesc = "Per packet CRC sent", .ucode = 0x20, .grpid = 0, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, .grpid = 0, }, }; static const amd64_entry_t amd64_fam11h_pe[]={ { .name = "DISPATCHED_FPU", .desc = "Dispatched FPU Operations", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x0, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_dispatched_fpu), .ngrp = 1, .umasks = amd64_fam11h_dispatched_fpu, }, { .name = "CYCLES_NO_FPU_OPS_RETIRED", .desc = "Cycles in which the FPU is Empty", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x1, }, { .name = "DISPATCHED_FPU_OPS_FAST_FLAG", .desc = "Dispatched Fast Flag FPU Operations", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x2, }, { .name = "SEGMENT_REGISTER_LOADS", .desc = "Segment Register Loads", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x20, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_segment_register_loads), .ngrp = 1, .umasks = amd64_fam11h_segment_register_loads, }, { .name = "PIPELINE_RESTART_DUE_TO_SELF_MODIFYING_CODE", .desc = "Pipeline Restart Due to Self-Modifying Code", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x21, }, { .name = "PIPELINE_RESTART_DUE_TO_PROBE_HIT", .desc = "Pipeline Restart Due to Probe Hit", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x22, }, { .name = "LS_BUFFER_2_FULL_CYCLES", .desc = "LS Buffer 2 Full", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x23, }, { .name = "LOCKED_OPS", .desc = "Locked Operations", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x24, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_locked_ops), .ngrp = 1, .umasks = amd64_fam11h_locked_ops, }, { .name = "RETIRED_CLFLUSH_INSTRUCTIONS", .desc = "Retired CLFLUSH Instructions", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x26, }, { .name = "RETIRED_CPUID_INSTRUCTIONS", .desc = "Retired CPUID Instructions", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x27, }, { .name = "DATA_CACHE_ACCESSES", .desc = "Data Cache Accesses", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x40, }, { .name = "DATA_CACHE_MISSES", .desc = "Data Cache Misses", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x41, }, { .name = "DATA_CACHE_REFILLS", .desc = "Data Cache Refills from L2 or System", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x42, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_data_cache_refills), .ngrp = 1, .umasks = amd64_fam11h_data_cache_refills, }, { .name = "DATA_CACHE_REFILLS_FROM_SYSTEM", .desc = "Data Cache Refills from the System", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x43, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_data_cache_refills_from_system), .ngrp = 1, .umasks = amd64_fam11h_data_cache_refills_from_system, }, { .name = "DATA_CACHE_LINES_EVICTED", .desc = "Data Cache Lines Evicted", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x44, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_data_cache_lines_evicted), .ngrp = 1, .umasks = amd64_fam11h_data_cache_lines_evicted, }, { .name = "L1_DTLB_MISS_AND_L2_DTLB_HIT", .desc = "Number of data cache accesses that miss in L1 DTLB and hit in L2 DTLB", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x45, }, { .name = "L1_DTLB_AND_L2_DTLB_MISS", .desc = "Number of data cache accesses that miss both the L1 and L2 DTLBs", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x46, }, { .name = "MISALIGNED_ACCESSES", .desc = "Misaligned Accesses", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x47, }, { .name = "MICROARCHITECTURAL_LATE_CANCEL_OF_AN_ACCESS", .desc = "Microarchitectural Late Cancel of an Access", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x48, }, { .name = "MICROARCHITECTURAL_EARLY_CANCEL_OF_AN_ACCESS", .desc = "Microarchitectural Early Cancel of an Access", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x49, }, { .name = "SCRUBBER_SINGLE_BIT_ECC_ERRORS", .desc = "Single-bit ECC Errors Recorded by Scrubber", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x4a, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_scrubber_single_bit_ecc_errors), .ngrp = 1, .umasks = amd64_fam11h_scrubber_single_bit_ecc_errors, }, { .name = "PREFETCH_INSTRUCTIONS_DISPATCHED", .desc = "Prefetch Instructions Dispatched", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x4b, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_prefetch_instructions_dispatched), .ngrp = 1, .umasks = amd64_fam11h_prefetch_instructions_dispatched, }, { .name = "DCACHE_MISSES_BY_LOCKED_INSTRUCTIONS", .desc = "DCACHE Misses by Locked Instructions", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x4c, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_dcache_misses_by_locked_instructions), .ngrp = 1, .umasks = amd64_fam11h_dcache_misses_by_locked_instructions, }, { .name = "MEMORY_REQUESTS", .desc = "Memory Requests by Type", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x65, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_memory_requests), .ngrp = 1, .umasks = amd64_fam11h_memory_requests, }, { .name = "DATA_PREFETCHES", .desc = "Data Prefetcher", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x67, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_data_prefetches), .ngrp = 1, .umasks = amd64_fam11h_data_prefetches, }, { .name = "SYSTEM_READ_RESPONSES", .desc = "System Read Responses by Coherency State", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x6c, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_system_read_responses), .ngrp = 1, .umasks = amd64_fam11h_system_read_responses, }, { .name = "QUADWORDS_WRITTEN_TO_SYSTEM", .desc = "Quadwords Written to System", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x6d, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_quadwords_written_to_system), .ngrp = 1, .umasks = amd64_fam11h_quadwords_written_to_system, }, { .name = "CPU_CLK_UNHALTED", .desc = "CPU Clocks not Halted", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x76, }, { .name = "REQUESTS_TO_L2", .desc = "Requests to L2 Cache", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x7d, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_requests_to_l2), .ngrp = 1, .umasks = amd64_fam11h_requests_to_l2, }, { .name = "L2_CACHE_MISS", .desc = "L2 Cache Misses", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x7e, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_l2_cache_miss), .ngrp = 1, .umasks = amd64_fam11h_l2_cache_miss, }, { .name = "L2_FILL_WRITEBACK", .desc = "L2 Fill/Writeback", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x7f, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_l2_fill_writeback), .ngrp = 1, .umasks = amd64_fam11h_l2_fill_writeback, }, { .name = "INSTRUCTION_CACHE_FETCHES", .desc = "Instruction Cache Fetches", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x80, }, { .name = "INSTRUCTION_CACHE_MISSES", .desc = "Instruction Cache Misses", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x81, }, { .name = "INSTRUCTION_CACHE_REFILLS_FROM_L2", .desc = "Instruction Cache Refills from L2", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x82, }, { .name = "INSTRUCTION_CACHE_REFILLS_FROM_SYSTEM", .desc = "Instruction Cache Refills from System", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x83, }, { .name = "L1_ITLB_MISS_AND_L2_ITLB_HIT", .desc = "L1 ITLB Miss and L2 ITLB Hit", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x84, }, { .name = "L1_ITLB_MISS_AND_L2_ITLB_MISS", .desc = "L1 ITLB Miss and L2 ITLB Miss", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x85, }, { .name = "PIPELINE_RESTART_DUE_TO_INSTRUCTION_STREAM_PROBE", .desc = "Pipeline Restart Due to Instruction Stream Probe", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x86, }, { .name = "INSTRUCTION_FETCH_STALL", .desc = "Instruction Fetch Stall", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x87, }, { .name = "RETURN_STACK_HITS", .desc = "Return Stack Hits", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x88, }, { .name = "RETURN_STACK_OVERFLOWS", .desc = "Return Stack Overflows", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x89, }, { .name = "RETIRED_INSTRUCTIONS", .desc = "Retired Instructions", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xc0, }, { .name = "RETIRED_UOPS", .desc = "Retired uops", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xc1, }, { .name = "RETIRED_BRANCH_INSTRUCTIONS", .desc = "Retired Branch Instructions", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xc2, }, { .name = "RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS", .desc = "Retired Mispredicted Branch Instructions", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xc3, }, { .name = "RETIRED_TAKEN_BRANCH_INSTRUCTIONS", .desc = "Retired Taken Branch Instructions", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xc4, }, { .name = "RETIRED_TAKEN_BRANCH_INSTRUCTIONS_MISPREDICTED", .desc = "Retired Taken Branch Instructions Mispredicted", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xc5, }, { .name = "RETIRED_FAR_CONTROL_TRANSFERS", .desc = "Retired Far Control Transfers", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xc6, }, { .name = "RETIRED_BRANCH_RESYNCS", .desc = "Retired Branch Resyncs", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xc7, }, { .name = "RETIRED_NEAR_RETURNS", .desc = "Retired Near Returns", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xc8, }, { .name = "RETIRED_NEAR_RETURNS_MISPREDICTED", .desc = "Retired Near Returns Mispredicted", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xc9, }, { .name = "RETIRED_INDIRECT_BRANCHES_MISPREDICTED", .desc = "Retired Indirect Branches Mispredicted", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xca, }, { .name = "RETIRED_MMX_AND_FP_INSTRUCTIONS", .desc = "Retired MMX/FP Instructions", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xcb, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_retired_mmx_and_fp_instructions), .ngrp = 1, .umasks = amd64_fam11h_retired_mmx_and_fp_instructions, }, { .name = "RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS", .desc = "Retired Fastpath Double Op Instructions", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xcc, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_retired_fastpath_double_op_instructions), .ngrp = 1, .umasks = amd64_fam11h_retired_fastpath_double_op_instructions, }, { .name = "INTERRUPTS_MASKED_CYCLES", .desc = "Interrupts-Masked Cycles", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xcd, }, { .name = "INTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDING", .desc = "Interrupts-Masked Cycles with Interrupt Pending", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xce, }, { .name = "INTERRUPTS_TAKEN", .desc = "Interrupts Taken", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xcf, }, { .name = "DECODER_EMPTY", .desc = "Decoder Empty", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xd0, }, { .name = "DISPATCH_STALLS", .desc = "Dispatch Stalls", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xd1, }, { .name = "DISPATCH_STALL_FOR_BRANCH_ABORT", .desc = "Dispatch Stall for Branch Abort to Retire", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xd2, }, { .name = "DISPATCH_STALL_FOR_SERIALIZATION", .desc = "Dispatch Stall for Serialization", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xd3, }, { .name = "DISPATCH_STALL_FOR_SEGMENT_LOAD", .desc = "Dispatch Stall for Segment Load", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xd4, }, { .name = "DISPATCH_STALL_FOR_REORDER_BUFFER_FULL", .desc = "Dispatch Stall for Reorder Buffer Full", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xd5, }, { .name = "DISPATCH_STALL_FOR_RESERVATION_STATION_FULL", .desc = "Dispatch Stall for Reservation Station Full", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xd6, }, { .name = "DISPATCH_STALL_FOR_FPU_FULL", .desc = "Dispatch Stall for FPU Full", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xd7, }, { .name = "DISPATCH_STALL_FOR_LS_FULL", .desc = "Dispatch Stall for LS Full", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xd8, }, { .name = "DISPATCH_STALL_WAITING_FOR_ALL_QUIET", .desc = "Dispatch Stall Waiting for All Quiet", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xd9, }, { .name = "DISPATCH_STALL_FOR_FAR_TRANSFER_OR_RSYNC", .desc = "Dispatch Stall for Far Transfer or Resync to Retire", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xda, }, { .name = "FPU_EXCEPTIONS", .desc = "FPU Exceptions", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xdb, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_fpu_exceptions), .ngrp = 1, .umasks = amd64_fam11h_fpu_exceptions, }, { .name = "DR0_BREAKPOINT_MATCHES", .desc = "DR0 Breakpoint Matches", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xdc, }, { .name = "DR1_BREAKPOINT_MATCHES", .desc = "DR1 Breakpoint Matches", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xdd, }, { .name = "DR2_BREAKPOINT_MATCHES", .desc = "DR2 Breakpoint Matches", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xde, }, { .name = "DR3_BREAKPOINT_MATCHES", .desc = "DR3 Breakpoint Matches", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xdf, }, { .name = "DRAM_ACCESSES", .desc = "DRAM Accesses", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xe0, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_dram_accesses), .ngrp = 1, .umasks = amd64_fam11h_dram_accesses, }, { .name = "DRAM_CONTROLLER_PAGE_TABLE_EVENTS", .desc = "DRAM Controller Page Table Events", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xe1, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_dram_controller_page_table_events), .ngrp = 1, .umasks = amd64_fam11h_dram_controller_page_table_events, }, { .name = "MEMORY_CONTROLLER_TURNAROUNDS", .desc = "Memory Controller Turnarounds", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xe3, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_memory_controller_turnarounds), .ngrp = 1, .umasks = amd64_fam11h_memory_controller_turnarounds, }, { .name = "MEMORY_CONTROLLER_RBD_QUEUE", .desc = "Memory Controller RBD Queue Events", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xe4, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_memory_rbd_queue), .ngrp = 1, .umasks = amd64_fam11h_memory_rbd_queue, }, { .name = "THERMAL_STATUS", .desc = "Thermal Status", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xe8, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_thermal_status), .ngrp = 1, .umasks = amd64_fam11h_thermal_status, }, { .name = "CPU_IO_REQUESTS_TO_MEMORY_IO", .desc = "CPU/IO Requests to Memory/IO", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xe9, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_cpu_io_requests_to_memory_io), .ngrp = 1, .umasks = amd64_fam11h_cpu_io_requests_to_memory_io, }, { .name = "CACHE_BLOCK", .desc = "Cache Block Commands", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xea, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_cache_block), .ngrp = 1, .umasks = amd64_fam11h_cache_block, }, { .name = "SIZED_COMMANDS", .desc = "Sized Commands", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xeb, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_sized_commands), .ngrp = 1, .umasks = amd64_fam11h_sized_commands, }, { .name = "PROBE", .desc = "Probe Responses and Upstream Requests", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xec, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_probe), .ngrp = 1, .umasks = amd64_fam11h_probe, }, { .name = "DEV", .desc = "DEV Events", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xee, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_dev), .ngrp = 1, .umasks = amd64_fam11h_dev, }, { .name = "HYPERTRANSPORT_LINK0", .desc = "HyperTransport Link 0 Transmit Bandwidth", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xf6, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_hypertransport_link0), .ngrp = 1, .umasks = amd64_fam11h_hypertransport_link0, }, { .name = "MEMORY_CONTROLLER_REQUESTS", .desc = "Memory Controller Requests", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x1f0, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_memory_controller_requests), .ngrp = 1, .umasks = amd64_fam11h_memory_controller_requests, }, { .name = "SIDEBAND_SIGNALS", .desc = "Sideband Signals and Special Cycles", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x1e9, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_sideband_signals), .ngrp = 1, .umasks = amd64_fam11h_sideband_signals, }, { .name = "INTERRUPT_EVENTS", .desc = "Interrupt Events", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x1ea, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_interrupt_events), .ngrp = 1, .umasks = amd64_fam11h_interrupt_events, }, }; libpfm-4.9.0/lib/events/intel_bdx_unc_cbo_events.h0000664000175000017500000011160413223402656022070 0ustar eranianeranian/* * Copyright (c) 2017 Google Inc. All rights reserved * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * PMU: bdx_unc_cbo */ #define CBO_FILT_MESIF(a, b, c, d) \ { .uname = "STATE_"#a,\ .udesc = #b" cacheline state",\ .ufilters[0] = 1ULL << (17 + (c)),\ .grpid = d, \ } #define CBO_FILT_MESIFS(d) \ CBO_FILT_MESIF(I, Invalid, 0, d), \ CBO_FILT_MESIF(S, Shared, 1, d), \ CBO_FILT_MESIF(E, Exclusive, 2, d), \ CBO_FILT_MESIF(M, Modified, 3, d), \ CBO_FILT_MESIF(F, Forward, 4, d), \ CBO_FILT_MESIF(D, Debug, 5, d), \ { .uname = "STATE_MP",\ .udesc = "Cacheline is modified but never written, was forwarded in modified state",\ .ufilters[0] = 0x1ULL << (17+6),\ .grpid = d, \ .uflags = INTEL_X86_NCOMBO, \ }, \ { .uname = "STATE_MESIFD",\ .udesc = "Any cache line state",\ .ufilters[0] = 0x7fULL << 17,\ .grpid = d, \ .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, \ } #define CBO_FILT_OPC(d) \ { .uname = "OPC_RFO",\ .udesc = "Demand data RFO (combine with any OPCODE umask)",\ .ufilters[1] = 0x180ULL << 20, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_CRD",\ .udesc = "Demand code read (combine with any OPCODE umask)",\ .ufilters[1] = 0x181ULL << 20, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_DRD",\ .udesc = "Demand data read (combine with any OPCODE umask)",\ .ufilters[1] = 0x182ULL << 20, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_PRD",\ .udesc = "Partial reads (UC) (combine with any OPCODE umask)",\ .ufilters[1] = 0x187ULL << 20, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_WCILF",\ .udesc = "Full Stream store (combine with any OPCODE umask)", \ .ufilters[1] = 0x18cULL << 20, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_WCIL",\ .udesc = "Partial Stream store (combine with any OPCODE umask)", \ .ufilters[1] = 0x18dULL << 20, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_WIL",\ .udesc = "Write Invalidate Line (Partial) (combine with any OPCODE umask)", \ .ufilters[1] = 0x18fULL << 20, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_PF_RFO",\ .udesc = "Prefetch RFO into LLC but do not pass to L2 (includes hints) (combine with any OPCODE umask)", \ .ufilters[1] = 0x190ULL << 20, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_PF_CODE",\ .udesc = "Prefetch code into LLC but do not pass to L2 (includes hints) (combine with any OPCODE umask)", \ .ufilters[1] = 0x191ULL << 20, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_PF_DATA",\ .udesc = "Prefetch data into LLC but do not pass to L2 (includes hints) (combine with any OPCODE umask)", \ .ufilters[1] = 0x192ULL << 20, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_PCIWIL",\ .udesc = "PCIe write (partial, non-allocating) - partial line MMIO write transactions from IIO (P2P). Not used for coherent transacions. Uncacheable. (combine with any OPCODE umask)", \ .ufilters[1] = 0x193ULL << 20, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_PCIWIF",\ .udesc = "PCIe write (full, non-allocating) - full line MMIO write transactions from IIO (P2P). Not used for coherent transacions. Uncacheable. (combine with any OPCODE umask)", \ .ufilters[1] = 0x194ULL << 20, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_PCIITOM",\ .udesc = "PCIe write (allocating) (combine with any OPCODE umask)", \ .ufilters[1] = 0x19cULL << 20, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_PCIRDCUR",\ .udesc = "PCIe read current (combine with any OPCODE umask)", \ .ufilters[1] = 0x19eULL << 20, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_WBMTOI",\ .udesc = "Request writeback modified invalidate line (combine with any OPCODE umask)", \ .ufilters[1] = 0x1c4ULL << 20, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_WBMTOE",\ .udesc = "Request writeback modified set to exclusive (combine with any OPCODE umask)", \ .ufilters[1] = 0x1c5ULL << 20, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_ITOM",\ .udesc = "Request invalidate line. Request exclusive ownership of the line (combine with any OPCODE umask)", \ .ufilters[1] = 0x1c8ULL << 20, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_PCINSRD",\ .udesc = "PCIe non-snoop read (combine with any OPCODE umask)", \ .ufilters[1] = 0x1e4ULL << 20, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_PCINSWR",\ .udesc = "PCIe non-snoop write (partial) (combine with any OPCODE umask)", \ .ufilters[1] = 0x1e5ULL << 20, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_PCINSWRF",\ .udesc = "PCIe non-snoop write (full) (combine with any OPCODE umask)", \ .ufilters[1] = 0x1e6ULL << 20, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ } static intel_x86_umask_t bdx_unc_c_llc_lookup[]={ { .uname = "ANY", .ucode = 0x1100, .udesc = "Cache Lookups -- Any Request", .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, .grpid = 0, }, { .uname = "DATA_READ", .ucode = 0x300, .udesc = "Cache Lookups -- Data Read Request", .grpid = 0, }, { .uname = "NID", .ucode = 0x4100, .udesc = "Cache Lookups -- Lookups that Match NID", .umodmsk_req = _SNBEP_UNC_ATTR_NF1, .grpid = 1, .uflags = INTEL_X86_GRP_DFL_NONE }, { .uname = "READ", .ucode = 0x2100, .udesc = "Cache Lookups -- Any Read Request", .grpid = 0, }, { .uname = "REMOTE_SNOOP", .ucode = 0x900, .udesc = "Cache Lookups -- External Snoop Request", .grpid = 0, }, { .uname = "WRITE", .ucode = 0x500, .udesc = "Cache Lookups -- Write Requests", .grpid = 0, }, CBO_FILT_MESIFS(2), }; static intel_x86_umask_t bdx_unc_c_llc_victims[]={ { .uname = "F_STATE", .ucode = 0x800, .udesc = "Lines in Forward state", .grpid = 0, }, { .uname = "I_STATE", .ucode = 0x400, .udesc = "Lines in S State", .grpid = 0, }, { .uname = "S_STATE", .ucode = 0x400, .udesc = "Lines in S state", .grpid = 0, }, { .uname = "E_STATE", .ucode = 0x200, .udesc = "Lines in E state", .grpid = 0, }, { .uname = "M_STATE", .ucode = 0x100, .udesc = "Lines in M state", .grpid = 0, }, { .uname = "MISS", .ucode = 0x1000, .udesc = "Lines Victimized", .grpid = 0, }, { .uname = "NID", .ucode = 0x4000, .udesc = "Lines Victimized -- Victimized Lines that Match NID", .uflags = INTEL_X86_GRP_DFL_NONE, .umodmsk_req = _SNBEP_UNC_ATTR_NF1, .grpid = 1, }, }; static intel_x86_umask_t bdx_unc_c_misc[]={ { .uname = "CVZERO_PREFETCH_MISS", .ucode = 0x2000, .udesc = "Cbo Misc -- DRd hitting non-M with raw CV=0", }, { .uname = "CVZERO_PREFETCH_VICTIM", .ucode = 0x1000, .udesc = "Cbo Misc -- Clean Victim with raw CV=0", }, { .uname = "RFO_HIT_S", .ucode = 0x800, .udesc = "Cbo Misc -- RFO HitS", }, { .uname = "RSPI_WAS_FSE", .ucode = 0x100, .udesc = "Cbo Misc -- Silent Snoop Eviction", }, { .uname = "STARTED", .ucode = 0x400, .udesc = "Cbo Misc -- ", }, { .uname = "WC_ALIASING", .ucode = 0x200, .udesc = "Cbo Misc -- Write Combining Aliasing", }, }; static intel_x86_umask_t bdx_unc_c_ring_ad_used[]={ { .uname = "ALL", .ucode = 0xf00, .udesc = "AD Ring In Use -- All", }, { .uname = "CCW", .ucode = 0xc00, .udesc = "AD Ring In Use -- Down", }, { .uname = "CW", .ucode = 0x300, .udesc = "AD Ring In Use -- Up", }, { .uname = "DOWN_EVEN", .ucode = 0x400, .udesc = "AD Ring In Use -- Down and Even", }, { .uname = "DOWN_ODD", .ucode = 0x800, .udesc = "AD Ring In Use -- Down and Odd", }, { .uname = "UP_EVEN", .ucode = 0x100, .udesc = "AD Ring In Use -- Up and Even", }, { .uname = "UP_ODD", .ucode = 0x200, .udesc = "AD Ring In Use -- Up and Odd", }, }; static intel_x86_umask_t bdx_unc_c_ring_ak_used[]={ { .uname = "ALL", .ucode = 0xf00, .udesc = "AK Ring In Use -- All", }, { .uname = "CCW", .ucode = 0xc00, .udesc = "AK Ring In Use -- Down", }, { .uname = "CW", .ucode = 0x300, .udesc = "AK Ring In Use -- Up", }, { .uname = "DOWN_EVEN", .ucode = 0x400, .udesc = "AK Ring In Use -- Down and Even", }, { .uname = "DOWN_ODD", .ucode = 0x800, .udesc = "AK Ring In Use -- Down and Odd", }, { .uname = "UP_EVEN", .ucode = 0x100, .udesc = "AK Ring In Use -- Up and Even", }, { .uname = "UP_ODD", .ucode = 0x200, .udesc = "AK Ring In Use -- Up and Odd", }, }; static intel_x86_umask_t bdx_unc_c_ring_bl_used[]={ { .uname = "ALL", .ucode = 0xf00, .udesc = "BL Ring in Use -- Down", }, { .uname = "CCW", .ucode = 0xc00, .udesc = "BL Ring in Use -- Down", }, { .uname = "CW", .ucode = 0x300, .udesc = "BL Ring in Use -- Up", }, { .uname = "DOWN_EVEN", .ucode = 0x400, .udesc = "BL Ring in Use -- Down and Even", }, { .uname = "DOWN_ODD", .ucode = 0x800, .udesc = "BL Ring in Use -- Down and Odd", }, { .uname = "UP_EVEN", .ucode = 0x100, .udesc = "BL Ring in Use -- Up and Even", }, { .uname = "UP_ODD", .ucode = 0x200, .udesc = "BL Ring in Use -- Up and Odd", }, }; static intel_x86_umask_t bdx_unc_c_ring_bounces[]={ { .uname = "AD", .ucode = 0x100, .udesc = "Number of LLC responses that bounced on the Ring. -- AD", }, { .uname = "AK", .ucode = 0x200, .udesc = "Number of LLC responses that bounced on the Ring. -- AK", }, { .uname = "BL", .ucode = 0x400, .udesc = "Number of LLC responses that bounced on the Ring. -- BL", }, { .uname = "IV", .ucode = 0x1000, .udesc = "Number of LLC responses that bounced on the Ring. -- Snoops of processors cachee.", }, }; static intel_x86_umask_t bdx_unc_c_ring_iv_used[]={ { .uname = "ANY", .ucode = 0xf00, .udesc = "BL Ring in Use -- Any", .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "DN", .ucode = 0xc00, .udesc = "BL Ring in Use -- Any", .uflags = INTEL_X86_NCOMBO, }, { .uname = "DOWN", .ucode = 0xcc00, .udesc = "BL Ring in Use -- Down", .uflags = INTEL_X86_NCOMBO, }, { .uname = "UP", .ucode = 0x300, .udesc = "BL Ring in Use -- Any", .uflags = INTEL_X86_NCOMBO, }, }; static intel_x86_umask_t bdx_unc_c_rxr_ext_starved[]={ { .uname = "IPQ", .ucode = 0x200, .udesc = "Ingress Arbiter Blocking Cycles -- IRQ", }, { .uname = "IRQ", .ucode = 0x100, .udesc = "Ingress Arbiter Blocking Cycles -- IPQ", }, { .uname = "ISMQ_BIDS", .ucode = 0x800, .udesc = "Ingress Arbiter Blocking Cycles -- ISMQ_BID", }, { .uname = "PRQ", .ucode = 0x400, .udesc = "Ingress Arbiter Blocking Cycles -- PRQ", }, }; static intel_x86_umask_t bdx_unc_c_rxr_inserts[]={ { .uname = "IPQ", .ucode = 0x400, .udesc = "Ingress Allocations -- IPQ", }, { .uname = "IRQ", .ucode = 0x100, .udesc = "Ingress Allocations -- IRQ", }, { .uname = "IRQ_REJ", .ucode = 0x200, .udesc = "Ingress Allocations -- IRQ Rejected", }, { .uname = "PRQ", .ucode = 0x1000, .udesc = "Ingress Allocations -- PRQ", }, { .uname = "PRQ_REJ", .ucode = 0x2000, .udesc = "Ingress Allocations -- PRQ", }, }; static intel_x86_umask_t bdx_unc_c_rxr_ipq_retry[]={ { .uname = "ADDR_CONFLICT", .ucode = 0x400, .udesc = "Probe Queue Retries -- Address Conflict", }, { .uname = "ANY", .ucode = 0x100, .udesc = "Probe Queue Retries -- Any Reject", .uflags = INTEL_X86_DFL, }, { .uname = "FULL", .ucode = 0x200, .udesc = "Probe Queue Retries -- No Egress Credits", }, { .uname = "QPI_CREDITS", .ucode = 0x1000, .udesc = "Probe Queue Retries -- No QPI Credits", }, }; static intel_x86_umask_t bdx_unc_c_rxr_ipq_retry2[]={ { .uname = "AD_SBO", .ucode = 0x100, .udesc = "Probe Queue Retries -- No AD Sbo Credits", }, { .uname = "TARGET", .ucode = 0x4000, .udesc = "Probe Queue Retries -- Target Node Filter", }, }; static intel_x86_umask_t bdx_unc_c_rxr_irq_retry[]={ { .uname = "ADDR_CONFLICT", .ucode = 0x400, .udesc = "Ingress Request Queue Rejects -- Address Conflict", }, { .uname = "ANY", .ucode = 0x100, .udesc = "Ingress Request Queue Rejects -- Any Reject", .uflags = INTEL_X86_DFL, }, { .uname = "FULL", .ucode = 0x200, .udesc = "Ingress Request Queue Rejects -- No Egress Credits", }, { .uname = "IIO_CREDITS", .ucode = 0x2000, .udesc = "Ingress Request Queue Rejects -- No IIO Credits", }, { .uname = "NID", .ucode = 0x4000, .udesc = "Ingress Request Queue Rejects -- ", }, { .uname = "QPI_CREDITS", .ucode = 0x1000, .udesc = "Ingress Request Queue Rejects -- No QPI Credits", }, { .uname = "RTID", .ucode = 0x800, .udesc = "Ingress Request Queue Rejects -- No RTIDs", }, }; static intel_x86_umask_t bdx_unc_c_rxr_irq_retry2[]={ { .uname = "AD_SBO", .ucode = 0x100, .udesc = "Ingress Request Queue Rejects -- No AD Sbo Credits", }, { .uname = "BL_SBO", .ucode = 0x200, .udesc = "Ingress Request Queue Rejects -- No BL Sbo Credits", }, { .uname = "TARGET", .ucode = 0x4000, .udesc = "Ingress Request Queue Rejects -- Target Node Filter", }, }; static intel_x86_umask_t bdx_unc_c_rxr_ismq_retry[]={ { .uname = "ANY", .ucode = 0x100, .udesc = "ISMQ Retries -- Any Reject", .uflags = INTEL_X86_DFL, }, { .uname = "FULL", .ucode = 0x200, .udesc = "ISMQ Retries -- No Egress Credits", }, { .uname = "IIO_CREDITS", .ucode = 0x2000, .udesc = "ISMQ Retries -- No IIO Credits", }, { .uname = "NID", .ucode = 0x4000, .udesc = "ISMQ Retries -- ", }, { .uname = "QPI_CREDITS", .ucode = 0x1000, .udesc = "ISMQ Retries -- No QPI Credits", }, { .uname = "RTID", .ucode = 0x800, .udesc = "ISMQ Retries -- No RTIDs", }, { .uname = "WB_CREDITS", .ucode = 0x8000, .udesc = "ISMQ Retries -- ", }, }; static intel_x86_umask_t bdx_unc_c_rxr_ismq_retry2[]={ { .uname = "AD_SBO", .ucode = 0x100, .udesc = "ISMQ Request Queue Rejects -- No AD Sbo Credits", }, { .uname = "BL_SBO", .ucode = 0x200, .udesc = "ISMQ Request Queue Rejects -- No BL Sbo Credits", }, { .uname = "TARGET", .ucode = 0x4000, .udesc = "ISMQ Request Queue Rejects -- Target Node Filter", }, }; static intel_x86_umask_t bdx_unc_c_rxr_occupancy[]={ { .uname = "IPQ", .ucode = 0x400, .udesc = "Ingress Occupancy -- IPQ", .uflags = INTEL_X86_NCOMBO, }, { .uname = "IRQ", .ucode = 0x100, .udesc = "Ingress Occupancy -- IRQ", .uflags = INTEL_X86_NCOMBO, }, { .uname = "IRQ_REJ", .ucode = 0x200, .udesc = "Ingress Occupancy -- IRQ Rejected", .uflags = INTEL_X86_NCOMBO, }, { .uname = "PRQ_REJ", .ucode = 0x2000, .udesc = "Ingress Occupancy -- PRQ Rejects", .uflags = INTEL_X86_NCOMBO, }, }; static intel_x86_umask_t bdx_unc_c_sbo_credits_acquired[]={ { .uname = "AD", .ucode = 0x100, .udesc = "SBo Credits Acquired -- For AD Ring", }, { .uname = "BL", .ucode = 0x200, .udesc = "SBo Credits Acquired -- For BL Ring", }, }; static intel_x86_umask_t bdx_unc_c_sbo_credit_occupancy[]={ { .uname = "AD", .ucode = 0x100, .udesc = "SBo Credits Occupancy -- For AD Ring", }, { .uname = "BL", .ucode = 0x200, .udesc = "SBo Credits Occupancy -- For BL Ring", }, }; static intel_x86_umask_t bdx_unc_c_tor_inserts[]={ { .uname = "ALL", .ucode = 0x800, .udesc = "All", .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL | INTEL_X86_EXCL_GRP_GT, .grpid = 0, }, { .uname = "EVICTION", .ucode = 0x400, .udesc = "Evictions", .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, .grpid = 0, }, { .uname = "LOCAL", .ucode = 0x2800, .udesc = "Local Memory", .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, .grpid = 0, }, { .uname = "LOCAL_OPCODE", .ucode = 0x2100, .udesc = "Local Memory - Opcode Matched", .uflags = INTEL_X86_NCOMBO, .grpid = 0, }, { .uname = "MISS_LOCAL", .ucode = 0x2a00, .udesc = "Misses to Local Memory", .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, .grpid = 0, }, { .uname = "MISS_LOCAL_OPCODE", .ucode = 0x2300, .udesc = "Misses to Local Memory - Opcode Matched", .uflags = INTEL_X86_NCOMBO, .grpid = 0, }, { .uname = "MISS_OPCODE", .ucode = 0x300, .udesc = "Miss Opcode Match", .uflags = INTEL_X86_NCOMBO, .grpid = 0, }, { .uname = "MISS_REMOTE", .ucode = 0x8a00, .udesc = "Misses to Remote Memory", .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, .grpid = 0, }, { .uname = "MISS_REMOTE_OPCODE", .ucode = 0x8300, .udesc = "Misses to Remote Memory - Opcode Matched", .uflags = INTEL_X86_NCOMBO, .grpid = 0, }, { .uname = "NID_ALL", .ucode = 0x4800, .udesc = "NID Matched", .umodmsk_req = _SNBEP_UNC_ATTR_NF1, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, .grpid = 0, }, { .uname = "NID_EVICTION", .ucode = 0x4400, .udesc = "NID Matched Evictions", .umodmsk_req = _SNBEP_UNC_ATTR_NF1, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, .grpid = 0, }, { .uname = "NID_MISS_ALL", .ucode = 0x4a00, .udesc = "NID Matched Miss All", .umodmsk_req = _SNBEP_UNC_ATTR_NF1, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, .grpid = 0, }, { .uname = "NID_MISS_OPCODE", .ucode = 0x4300, .udesc = "NID and Opcode Matched Miss", .umodmsk_req = _SNBEP_UNC_ATTR_NF1, .uflags = INTEL_X86_NCOMBO, .grpid = 0, }, { .uname = "NID_OPCODE", .ucode = 0x4100, .udesc = "NID and Opcode Matched", .umodmsk_req = _SNBEP_UNC_ATTR_NF1, .uflags = INTEL_X86_NCOMBO, .grpid = 0, }, { .uname = "NID_WB", .ucode = 0x5000, .udesc = "NID Matched Writebacks", .umodmsk_req = _SNBEP_UNC_ATTR_NF1, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, .grpid = 0, }, { .uname = "OPCODE", .ucode = 0x100, .udesc = "Opcode Match", .uflags = INTEL_X86_NCOMBO, .grpid = 0, }, { .uname = "REMOTE", .ucode = 0x8800, .udesc = "Remote Memory", .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, .grpid = 0, }, { .uname = "REMOTE_OPCODE", .ucode = 0x8100, .udesc = "Remote Memory - Opcode Matched", .uflags = INTEL_X86_NCOMBO, .grpid = 0, }, { .uname = "WB", .ucode = 0x1000, .udesc = "Writebacks", .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, .grpid = 0, }, CBO_FILT_OPC(1) }; static intel_x86_umask_t bdx_unc_c_tor_occupancy[]={ { .uname = "ALL", .ucode = 0x800, .udesc = "Any", .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL | INTEL_X86_EXCL_GRP_GT, .grpid = 0, }, { .uname = "EVICTION", .ucode = 0x400, .udesc = "Evictions", .grpid = 0, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, }, { .uname = "LOCAL", .ucode = 0x2800, .udesc = "Number of transactions in the TOR that are satisfied by locally homed memory", .grpid = 0, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, }, { .uname = "LOCAL_OPCODE", .ucode = 0x2100, .udesc = "Local Memory - Opcode Matched", .grpid = 0, }, { .uname = "MISS_ALL", .ucode = 0xa00, .udesc = "Miss All", .grpid = 0, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, }, { .uname = "MISS_LOCAL", .ucode = 0x2a00, .udesc = "Number of miss transactions in the TOR that are satisfied by locally homed memory", .grpid = 0, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, }, { .uname = "MISS_LOCAL_OPCODE", .ucode = 0x2300, .udesc = "Number of miss opcode-matched transactions inserted into the TOR that are satisfied by locally homed memory", .grpid = 0, }, { .uname = "MISS_OPCODE", .ucode = 0x300, .udesc = "Number of miss transactions inserted into the TOR that match an opcode (must provide opc_* umask)", .grpid = 0, }, { .uname = "MISS_REMOTE_OPCODE", .ucode = 0x8300, .udesc = "Number of miss opcode-matched transactions inserted into the TOR that are satisfied by remote caches or memory", .grpid = 0, }, { .uname = "NID_ALL", .ucode = 0x4800, .udesc = "Number of NID-matched transactions inserted into the TOR (must provide nf=X modifier)", .grpid = 0, }, { .uname = "NID_EVICTION", .ucode = 0x4400, .udesc = "Number of NID-matched eviction transactions inserted into the TOR (must provide nf=X modifier)", .grpid = 0, .umodmsk_req = _SNBEP_UNC_ATTR_NF1, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, }, { .uname = "NID_MISS_ALL", .ucode = 0x4a00, .udesc = "Number of NID-matched miss transactions that were inserted into the TOR (must provide nf=X modifier)", .grpid = 0, .umodmsk_req = _SNBEP_UNC_ATTR_NF1, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, }, { .uname = "NID_MISS_OPCODE", .ucode = 0x4300, .udesc = "Number of NID and opcode matched miss transactions inserted into the TOR (must provide opc_* umask and nf=X modifier)", .grpid = 0, .umodmsk_req = _SNBEP_UNC_ATTR_NF1, .uflags = INTEL_X86_NCOMBO, }, { .uname = "NID_OPCODE", .ucode = 0x4100, .udesc = "Number of transactions inserted into the TOR that match a NID and opcode (must provide opc_* umask and nf=X modifier)", .grpid = 0, .umodmsk_req = _SNBEP_UNC_ATTR_NF1, .uflags = INTEL_X86_NCOMBO, }, { .uname = "NID_WB", .ucode = 0x5000, .udesc = "Number of NID-matched write back transactions inserted into the TOR (must provide nf=X modifier)", .grpid = 0, .umodmsk_req = _SNBEP_UNC_ATTR_NF1, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, }, { .uname = "OPCODE", .ucode = 0x100, .udesc = "Number of transactions inserted into the TOR that match an opcode (must provide opc_* umask)", .grpid = 0, .uflags = INTEL_X86_NCOMBO, }, { .uname = "REMOTE", .ucode = 0x8800, .udesc = "Number of transactions inserted into the TOR that are satisfied by remote caches or memory", .grpid = 0, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, }, { .uname = "REMOTE_OPCODE", .ucode = 0x8100, .udesc = "Number of opcode-matched transactions inserted into the TOR that are satisfied by remote caches or memory", .grpid = 0, .uflags = INTEL_X86_NCOMBO, }, { .uname = "WB", .ucode = 0x1000, .udesc = "Number of write transactions inserted into the TOR", .grpid = 0, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, }, { .uname = "MISS_REMOTE", .ucode = 0x8a00, .udesc = "Number of miss transactions inserted into the TOR that are satisfied by remote caches or memory", .grpid = 0, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, }, CBO_FILT_OPC(1) }; static intel_x86_umask_t bdx_unc_c_txr_ads_used[]={ { .uname = "AD", .ucode = 0x100, .udesc = "Onto AD Ring", }, { .uname = "AK", .ucode = 0x200, .udesc = "Onto AK Ring", }, { .uname = "BL", .ucode = 0x400, .udesc = "Onto BL Ring", }, }; static intel_x86_umask_t bdx_unc_c_txr_inserts[]={ { .uname = "AD_CACHE", .ucode = 0x100, .udesc = "Egress Allocations -- AD - Cachebo", }, { .uname = "AD_CORE", .ucode = 0x1000, .udesc = "Egress Allocations -- AD - Corebo", }, { .uname = "AK_CACHE", .ucode = 0x200, .udesc = "Egress Allocations -- AK - Cachebo", }, { .uname = "AK_CORE", .ucode = 0x2000, .udesc = "Egress Allocations -- AK - Corebo", }, { .uname = "BL_CACHE", .ucode = 0x400, .udesc = "Egress Allocations -- BL - Cacheno", }, { .uname = "BL_CORE", .ucode = 0x4000, .udesc = "Egress Allocations -- BL - Corebo", }, { .uname = "IV_CACHE", .ucode = 0x800, .udesc = "Egress Allocations -- IV - Cachebo", }, }; static intel_x86_entry_t intel_bdx_unc_c_pe[]={ { .name = "UNC_C_BOUNCE_CONTROL", .code = 0xa, .desc = "TBD", .modmsk = BDX_UNC_CBO_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_C_CLOCKTICKS", .code = 0x0, .desc = "Clock ticks", .modmsk = BDX_UNC_CBO_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_C_COUNTER0_OCCUPANCY", .code = 0x1f, .desc = "Since occupancy counts can only be captured in the Cbos 0 counter, this event allows a user to capture occupancy related information by filtering the Cb0 occupancy count captured in Counter 0. The filtering available is found in the control register - threshold, invert and edge detect. E.g. setting threshold to 1 can effectively monitor how many cycles the monitored queue has an entryy.", .modmsk = BDX_UNC_CBO_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_C_FAST_ASSERTED", .code = 0x9, .desc = "Counts the number of cycles either the local distress or incoming distress signals are asserted. Incoming distress includes both up and dn.", .modmsk = BDX_UNC_CBO_ATTRS, .cntmsk = 0x3, }, { .name = "UNC_C_LLC_LOOKUP", .code = 0x34, .desc = "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.", .modmsk = BDX_UNC_CBO_NID_ATTRS, .flags = INTEL_X86_NO_AUTOENCODE, .cntmsk = 0xf, .ngrp = 3, .umasks = bdx_unc_c_llc_lookup, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_c_llc_lookup), }, { .name = "UNC_C_LLC_VICTIMS", .code = 0x37, .desc = "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", .modmsk = BDX_UNC_CBO_NID_ATTRS, .flags = INTEL_X86_NO_AUTOENCODE, .cntmsk = 0xf, .ngrp = 2, .umasks = bdx_unc_c_llc_victims, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_c_llc_victims), }, { .name = "UNC_C_MISC", .code = 0x39, .desc = "Miscellaneous events in the Cbo.", .modmsk = BDX_UNC_CBO_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_c_misc, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_c_misc), }, { .name = "UNC_C_RING_AD_USED", .code = 0x1b, .desc = "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the rhe ring.", .modmsk = BDX_UNC_CBO_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_c_ring_ad_used, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_c_ring_ad_used), }, { .name = "UNC_C_RING_AK_USED", .code = 0x1c, .desc = "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the rhe ring.", .modmsk = BDX_UNC_CBO_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_c_ring_ak_used, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_c_ring_ak_used), }, { .name = "UNC_C_RING_BL_USED", .code = 0x1d, .desc = "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the rhe ring.", .modmsk = BDX_UNC_CBO_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_c_ring_bl_used, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_c_ring_bl_used), }, { .name = "UNC_C_RING_BOUNCES", .code = 0x5, .desc = "", .modmsk = BDX_UNC_CBO_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_c_ring_bounces, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_c_ring_bounces), }, { .name = "UNC_C_RING_IV_USED", .code = 0x1e, .desc = "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring in BDX Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ DN_ODD.", .modmsk = BDX_UNC_CBO_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_c_ring_iv_used, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_c_ring_iv_used), }, { .name = "UNC_C_RING_SRC_THRTL", .code = 0x7, .desc = "", .modmsk = BDX_UNC_CBO_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_C_RXR_EXT_STARVED", .code = 0x12, .desc = "Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues.", .modmsk = BDX_UNC_CBO_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_c_rxr_ext_starved, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_c_rxr_ext_starved), }, { .name = "UNC_C_RXR_INSERTS", .code = 0x13, .desc = "Counts number of allocations per cycle into the specified Ingress queue.", .modmsk = BDX_UNC_CBO_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_c_rxr_inserts, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_c_rxr_inserts), }, { .name = "UNC_C_RXR_IPQ_RETRY", .code = 0x31, .desc = "Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries.", .modmsk = BDX_UNC_CBO_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_c_rxr_ipq_retry, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_c_rxr_ipq_retry), }, { .name = "UNC_C_RXR_IPQ_RETRY2", .code = 0x28, .desc = "Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries.", .modmsk = BDX_UNC_CBO_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_c_rxr_ipq_retry2, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_c_rxr_ipq_retry2), }, { .name = "UNC_C_RXR_IRQ_RETRY", .code = 0x32, .desc = "", .modmsk = BDX_UNC_CBO_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_c_rxr_irq_retry, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_c_rxr_irq_retry), }, { .name = "UNC_C_RXR_IRQ_RETRY2", .code = 0x29, .desc = "", .modmsk = BDX_UNC_CBO_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_c_rxr_irq_retry2, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_c_rxr_irq_retry2), }, { .name = "UNC_C_RXR_ISMQ_RETRY", .code = 0x33, .desc = "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", .modmsk = BDX_UNC_CBO_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_c_rxr_ismq_retry, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_c_rxr_ismq_retry), }, { .name = "UNC_C_RXR_ISMQ_RETRY2", .code = 0x2a, .desc = "", .modmsk = BDX_UNC_CBO_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_c_rxr_ismq_retry2, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_c_rxr_ismq_retry2), }, { .name = "UNC_C_RXR_OCCUPANCY", .code = 0x11, .desc = "Counts number of entries in the specified Ingress queue in each cycle.", .modmsk = BDX_UNC_CBO_ATTRS, .cntmsk = 0x1, .ngrp = 1, .umasks = bdx_unc_c_rxr_occupancy, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_c_rxr_occupancy), }, { .name = "UNC_C_SBO_CREDITS_ACQUIRED", .code = 0x3d, .desc = "Number of Sbo credits acquired in a given cycle, per ring. Each Cbo is assigned an Sbo it can communicate with.", .modmsk = BDX_UNC_CBO_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_c_sbo_credits_acquired, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_c_sbo_credits_acquired), }, { .name = "UNC_C_SBO_CREDIT_OCCUPANCY", .code = 0x3e, .desc = "Number of Sbo credits in use in a given cycle, per ring. Each Cbo is assigned an Sbo it can communicate with.", .modmsk = BDX_UNC_CBO_ATTRS, .cntmsk = 0x1, .ngrp = 1, .umasks = bdx_unc_c_sbo_credit_occupancy, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_c_sbo_credit_occupancy), }, { .name = "UNC_C_TOR_INSERTS", .code = 0x35, .desc = "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent filters but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x1(0x182).", .modmsk = BDX_UNC_CBO_NID_ATTRS | _SNBEP_UNC_ATTR_ISOC | _SNBEP_UNC_ATTR_NC, .flags = INTEL_X86_NO_AUTOENCODE, .cntmsk = 0xf, .ngrp = 2, .umasks = bdx_unc_c_tor_inserts, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_c_tor_inserts), }, { .name = "UNC_C_TOR_OCCUPANCY", .code = 0x36, .desc = "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent filters but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x (0x182)", .modmsk = BDX_UNC_CBO_NID_ATTRS | _SNBEP_UNC_ATTR_ISOC | _SNBEP_UNC_ATTR_NC, .flags = INTEL_X86_NO_AUTOENCODE, .cntmsk = 0x1, .ngrp = 2, .umasks = bdx_unc_c_tor_occupancy, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_c_tor_occupancy), }, { .name = "UNC_C_TXR_ADS_USED", .code = 0x4, .desc = "", .modmsk = BDX_UNC_CBO_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_c_txr_ads_used, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_c_txr_ads_used), }, { .name = "UNC_C_TXR_INSERTS", .code = 0x2, .desc = "Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.", .modmsk = BDX_UNC_CBO_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_c_txr_inserts, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_c_txr_inserts), }, }; libpfm-4.9.0/lib/events/intel_pm_events.h0000664000175000017500000007336313223402656020250 0ustar eranianeranian/* * Copyright (c) 2011 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * This file has been automatically generated. * * PMU: pm (Intel Pentium M) */ static const intel_x86_umask_t pm_l2_ifetch[]={ { .uname = "I", .udesc = "Invalid state", .ucode = 0x100, }, { .uname = "S", .udesc = "Shared state", .ucode = 0x200, }, { .uname = "E", .udesc = "Exclusive state", .ucode = 0x400, }, { .uname = "M", .udesc = "Modified state", .ucode = 0x800, }, }; static const intel_x86_umask_t pm_bus_drdy_clocks[]={ { .uname = "SELF", .udesc = "Clocks when processor is driving bus", .ucode = 0x0, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "ANY", .udesc = "Clocks when any agent is driving bus", .ucode = 0x2000, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t pm_mmx_instr_type_exec[]={ { .uname = "MUL", .udesc = "MMX packed multiply instructions executed", .ucode = 0x100, }, { .uname = "SHIFT", .udesc = "MMX packed shift instructions executed", .ucode = 0x200, }, { .uname = "PACK", .udesc = "MMX pack operation instructions executed", .ucode = 0x400, }, { .uname = "UNPACK", .udesc = "MMX unpack operation instructions executed", .ucode = 0x800, }, { .uname = "LOGICAL", .udesc = "MMX packed logical instructions executed", .ucode = 0x1000, }, { .uname = "ARITH", .udesc = "MMX packed arithmetic instructions executed", .ucode = 0x2000, }, }; static const intel_x86_umask_t pm_fp_mmx_trans[]={ { .uname = "TO_FP", .udesc = "From MMX instructions to floating-point instructions", .ucode = 0x0, .uflags= INTEL_X86_NCOMBO, }, { .uname = "TO_MMX", .udesc = "From floating-point instructions to MMX instructions", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t pm_seg_rename_stalls[]={ { .uname = "ES", .udesc = "Segment register ES", .ucode = 0x100, }, { .uname = "DS", .udesc = "Segment register DS", .ucode = 0x200, }, { .uname = "FS", .udesc = "Segment register FS", .ucode = 0x400, }, { .uname = "GS", .udesc = "Segment register GS", .ucode = 0x800, }, }; static const intel_x86_umask_t pm_emon_kni_pref_dispatched[]={ { .uname = "NTA", .udesc = "Prefetch NTA", .ucode = 0x0, .uflags= INTEL_X86_NCOMBO, }, { .uname = "T1", .udesc = "Prefetch T1", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "T2", .udesc = "Prefetch T2", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "WEAK", .udesc = "Weakly ordered stores", .ucode = 0x300, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t pm_emon_est_trans[]={ { .uname = "ALL", .udesc = "All transitions", .ucode = 0x0, }, { .uname = "FREQ", .udesc = "Only frequency transitions", .ucode = 0x200, }, }; static const intel_x86_umask_t pm_emon_fused_uops_ret[]={ { .uname = "ALL", .udesc = "All fused micro-ops", .ucode = 0x0, }, { .uname = "LD_OP", .udesc = "Only load+Op micro-ops", .ucode = 0x100, }, { .uname = "STD_STA", .udesc = "Only std+sta micro-ops", .ucode = 0x200, }, }; static const intel_x86_umask_t pm_emon_sse_sse2_inst_retired[]={ { .uname = "SSE_PACKED_SCALAR_SINGLE", .udesc = "SSE Packed Single and Scalar Single", .ucode = 0x0, .uflags= INTEL_X86_NCOMBO, }, { .uname = "SSE_SCALAR_SINGLE", .udesc = "SSE Scalar Single", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "SSE2_PACKED_DOUBLE", .udesc = "SSE2 Packed Double", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "SSE2_SCALAR_DOUBLE", .udesc = "SSE2 Scalar Double", .ucode = 0x300, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t pm_l2_ld[]={ { .uname = "I", .udesc = "Invalid state", .ucode = 0x100, }, { .uname = "S", .udesc = "Shared state", .ucode = 0x200, }, { .uname = "E", .udesc = "Exclusive state", .ucode = 0x400, }, { .uname = "M", .udesc = "Modified state", .ucode = 0x800, }, { .uname = "EXCL_HW_PREFETCH", .udesc = "Exclude hardware prefetched lines", .ucode = 0x0, }, { .uname = "ONLY_HW_PREFETCH", .udesc = "Only hardware prefetched lines", .ucode = 0x1000, }, { .uname = "NON_HW_PREFETCH", .udesc = "Non hardware prefetched lines", .ucode = 0x2000, }, }; static const intel_x86_entry_t intel_pm_pe[]={ { .name = "CPU_CLK_UNHALTED", .desc = "Number cycles during which the processor is not halted and not in a thermal trip", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x79, }, { .name = "INST_RETIRED", .desc = "Number of instructions retired", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xc0, }, { .name = "DATA_MEM_REFS", .desc = "All loads from any memory type. All stores to any memory typeEach part of a split is counted separately. The internal logic counts not only memory loads and stores but also internal retries. 80-bit floating point accesses are double counted, since they are decomposed into a 16-bit exponent load and a 64-bit mantissa load. Memory accesses are only counted when they are actually performed (such as a load that gets squashed because a previous cache miss is outstanding to the same address, and which finally gets performed, is only counted once). Does not include I/O accesses or other non-memory accesses", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x43, }, { .name = "DCU_LINES_IN", .desc = "Total lines allocated in the DCU", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x45, }, { .name = "DCU_M_LINES_IN", .desc = "Number of M state lines allocated in the DCU", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x46, }, { .name = "DCU_M_LINES_OUT", .desc = "Number of M state lines evicted from the DCU. This includes evictions via snoop HITM, intervention or replacement", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x47, }, { .name = "DCU_MISS_OUTSTANDING", .desc = "Weighted number of cycle while a DCU miss is outstanding, incremented by the number of cache misses at any particular time. Cacheable read requests only are considered. Uncacheable requests are excluded Read-for-ownerships are counted, as well as line fills, invalidates, and stores", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x48, }, { .name = "IFU_IFETCH", .desc = "Number of instruction fetches, both cacheable and noncacheable including UC fetches", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x80, }, { .name = "IFU_IFETCH_MISS", .desc = "Number of instruction fetch misses. All instructions fetches that do not hit the IFU (i.e., that produce memory requests). Includes UC accesses", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x81, }, { .name = "ITLB_MISS", .desc = "Number of ITLB misses", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x85, }, { .name = "IFU_MEM_STALL", .desc = "Number of cycles instruction fetch is stalled for any reason. Includes IFU cache misses, ITLB misses, ITLB faults, and other minor stalls", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x86, }, { .name = "ILD_STALL", .desc = "Number of cycles that the instruction length decoder is stalled", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x87, }, { .name = "L2_IFETCH", .desc = "Number of L2 instruction fetches. This event indicates that a normal instruction fetch was received by the L2. The count includes only L2 cacheable instruction fetches: it does not include UC instruction fetches It does not include ITLB miss accesses", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x28, .numasks = LIBPFM_ARRAY_SIZE(pm_l2_ifetch), .ngrp = 1, .umasks = pm_l2_ifetch, }, { .name = "L2_ST", .desc = "Number of L2 data stores. This event indicates that a normal, unlocked, store memory access was received by the L2. Specifically, it indicates that the DCU sent a read-for ownership request to the L2. It also includes Invalid to Modified requests sent by the DCU to the L2. It includes only L2 cacheable memory accesses; it does not include I/O accesses, other non-memory accesses, or memory accesses such as UC/WT memory accesses. It does include L2 cacheable TLB miss memory accesses", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x2a, .numasks = LIBPFM_ARRAY_SIZE(pm_l2_ifetch), .ngrp = 1, .umasks = pm_l2_ifetch, /* identical to actual umasks list for this event */ }, { .name = "L2_M_LINES_INM", .desc = "Number of modified lines allocated in the L2", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x25, }, { .name = "L2_RQSTS", .desc = "Total number of L2 requests", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x2e, .numasks = LIBPFM_ARRAY_SIZE(pm_l2_ifetch), .ngrp = 1, .umasks = pm_l2_ifetch, /* identical to actual umasks list for this event */ }, { .name = "L2_ADS", .desc = "Number of L2 address strobes", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x21, }, { .name = "L2_DBUS_BUSY", .desc = "Number of cycles during which the L2 cache data bus was busy", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x22, }, { .name = "L2_DBUS_BUSY_RD", .desc = "Number of cycles during which the data bus was busy transferring read data from L2 to the processor", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x23, }, { .name = "BUS_DRDY_CLOCKS", .desc = "Number of clocks during which DRDY# is asserted. Utilization of the external system data bus during data transfers", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x62, .numasks = LIBPFM_ARRAY_SIZE(pm_bus_drdy_clocks), .ngrp = 1, .umasks = pm_bus_drdy_clocks, }, { .name = "BUS_LOCK_CLOCKS", .desc = "Number of clocks during which LOCK# is asserted on the external system bus", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x63, .numasks = LIBPFM_ARRAY_SIZE(pm_bus_drdy_clocks), .ngrp = 1, .umasks = pm_bus_drdy_clocks, /* identical to actual umasks list for this event */ }, { .name = "BUS_REQ_OUTSTANDING", .desc = "Number of bus requests outstanding. This counter is incremented by the number of cacheable read bus requests outstanding in any given cycle", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x60, }, { .name = "BUS_TRANS_BRD", .desc = "Number of burst read transactions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x65, .numasks = LIBPFM_ARRAY_SIZE(pm_bus_drdy_clocks), .ngrp = 1, .umasks = pm_bus_drdy_clocks, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRANS_RFO", .desc = "Number of completed read for ownership transactions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x66, .numasks = LIBPFM_ARRAY_SIZE(pm_bus_drdy_clocks), .ngrp = 1, .umasks = pm_bus_drdy_clocks, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRANS_WB", .desc = "Number of completed write back transactions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x67, .numasks = LIBPFM_ARRAY_SIZE(pm_bus_drdy_clocks), .ngrp = 1, .umasks = pm_bus_drdy_clocks, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRAN_IFETCH", .desc = "Number of completed instruction fetch transactions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x68, .numasks = LIBPFM_ARRAY_SIZE(pm_bus_drdy_clocks), .ngrp = 1, .umasks = pm_bus_drdy_clocks, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRAN_INVAL", .desc = "Number of completed invalidate transactions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x69, .numasks = LIBPFM_ARRAY_SIZE(pm_bus_drdy_clocks), .ngrp = 1, .umasks = pm_bus_drdy_clocks, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRAN_PWR", .desc = "Number of completed partial write transactions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x6a, .numasks = LIBPFM_ARRAY_SIZE(pm_bus_drdy_clocks), .ngrp = 1, .umasks = pm_bus_drdy_clocks, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRANS_P", .desc = "Number of completed partial transactions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x6b, .numasks = LIBPFM_ARRAY_SIZE(pm_bus_drdy_clocks), .ngrp = 1, .umasks = pm_bus_drdy_clocks, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRANS_IO", .desc = "Number of completed I/O transactions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x6c, .numasks = LIBPFM_ARRAY_SIZE(pm_bus_drdy_clocks), .ngrp = 1, .umasks = pm_bus_drdy_clocks, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRAN_DEF", .desc = "Number of completed deferred transactions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x6d, .numasks = LIBPFM_ARRAY_SIZE(pm_bus_drdy_clocks), .ngrp = 1, .umasks = pm_bus_drdy_clocks, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRAN_BURST", .desc = "Number of completed burst transactions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x6e, .numasks = LIBPFM_ARRAY_SIZE(pm_bus_drdy_clocks), .ngrp = 1, .umasks = pm_bus_drdy_clocks, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRAN_ANY", .desc = "Number of all completed bus transactions. Address bus utilization can be calculated knowing the minimum address bus occupancy. Includes special cycles, etc.", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x70, .numasks = LIBPFM_ARRAY_SIZE(pm_bus_drdy_clocks), .ngrp = 1, .umasks = pm_bus_drdy_clocks, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRAN_MEM", .desc = "Number of completed memory transactions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x6f, .numasks = LIBPFM_ARRAY_SIZE(pm_bus_drdy_clocks), .ngrp = 1, .umasks = pm_bus_drdy_clocks, /* identical to actual umasks list for this event */ }, { .name = "BUS_DATA_RECV", .desc = "Number of bus clock cycles during which this processor is receiving data", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x64, }, { .name = "BUS_BNR_DRV", .desc = "Number of bus clock cycles during which this processor is driving the BNR# pin", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x61, }, { .name = "BUS_HIT_DRV", .desc = "Number of bus clock cycles during which this processor is driving the HIT# pin", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x7a, }, { .name = "BUS_HITM_DRV", .desc = "Number of bus clock cycles during which this processor is driving the HITM# pin", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x7b, }, { .name = "BUS_SNOOP_STALL", .desc = "Number of clock cycles during which the bus is snoop stalled", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x7e, }, { .name = "FLOPS", .desc = "Number of computational floating-point operations retired. Excludes floating-point computational operations that cause traps or assists. Includes internal sub-operations for complex floating-point instructions like transcendentals. Excludes floating point loads and stores", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x1, .code = 0xc1, }, { .name = "FP_COMP_OPS_EXE", .desc = "Number of computational floating-point operations executed. The number of FADD, FSUB, FCOM, FMULs, integer MULs and IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This number does not include the number of cycles, but the number of operations. This event does not distinguish an FADD used in the middle of a transcendental flow from a separate FADD instruction", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x1, .code = 0x10, }, { .name = "FP_ASSIST", .desc = "Number of floating-point exception cases handled by microcode.", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x2, .code = 0x11, }, { .name = "MUL", .desc = "Number of multiplies.This count includes integer as well as FP multiplies and is speculative", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x2, .code = 0x12, }, { .name = "DIV", .desc = "Number of divides.This count includes integer as well as FP divides and is speculative", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x2, .code = 0x13, }, { .name = "CYCLES_DIV_BUSY", .desc = "Number of cycles during which the divider is busy, and cannot accept new divides. This includes integer and FP divides, FPREM, FPSQRT, etc. and is speculative", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x1, .code = 0x14, }, { .name = "LD_BLOCKS", .desc = "Number of load operations delayed due to store buffer blocks. Includes counts caused by preceding stores whose addresses are unknown, preceding stores whose addresses are known but whose data is unknown, and preceding stores that conflicts with the load but which incompletely overlap the load", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x3, }, { .name = "SB_DRAINS", .desc = "Number of store buffer drain cycles. Incremented every cycle the store buffer is draining. Draining is caused by serializing operations like CPUID, synchronizing operations like XCHG, interrupt acknowledgment, as well as other conditions (such as cache flushing).", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x4, }, { .name = "MISALIGN_MEM_REF", .desc = "Number of misaligned data memory references. Incremented by 1 every cycle during which, either the processor's load or store pipeline dispatches a misaligned micro-op Counting is performed if it is the first or second half or if it is blocked, squashed, or missed. In this context, misaligned means crossing a 64-bit boundary", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x5, }, { .name = "UOPS_RETIRED", .desc = "Number of micro-ops retired", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xc2, }, { .name = "INST_DECODED", .desc = "Number of instructions decoded", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xd0, }, { .name = "HW_INT_RX", .desc = "Number of hardware interrupts received", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xc8, }, { .name = "CYCLES_INT_MASKED", .desc = "Number of processor cycles for which interrupts are disabled", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xc6, }, { .name = "CYCLES_INT_PENDING_AND_MASKED", .desc = "Number of processor cycles for which interrupts are disabled and interrupts are pending.", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xc7, }, { .name = "BR_INST_RETIRED", .desc = "Number of branch instructions retired", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xc4, }, { .name = "BR_MISS_PRED_RETIRED", .desc = "Number of mispredicted branches retired", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xc5, }, { .name = "BR_TAKEN_RETIRED", .desc = "Number of taken branches retired", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xc9, }, { .name = "BR_MISS_PRED_TAKEN_RET", .desc = "Number of taken mispredicted branches retired", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xca, }, { .name = "BR_INST_DECODED", .desc = "Number of branch instructions decoded", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xe0, }, { .name = "BTB_MISSES", .desc = "Number of branches for which the BTB did not produce a prediction", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xe2, }, { .name = "BR_BOGUS", .desc = "Number of bogus branches", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xe4, }, { .name = "BACLEARS", .desc = "Number of times BACLEAR is asserted. This is the number of times that a static branch prediction was made, in which the branch decoder decided to make a branch prediction because the BTB did not", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xe6, }, { .name = "RESOURCE_STALLS", .desc = "Incremented by 1 during every cycle for which there is a resource related stall. Includes register renaming buffer entries, memory buffer entries. Does not include stalls due to bus queue full, too many cache misses, etc. In addition to resource related stalls, this event counts some other events. Includes stalls arising during branch misprediction recovery, such as if retirement of the mispredicted branch is delayed and stalls arising while store buffer is draining from synchronizing operations", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xa2, }, { .name = "PARTIAL_RAT_STALLS", .desc = "Number of cycles or events for partial stalls. This includes flag partial stalls", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xd2, }, { .name = "SEGMENT_REG_LOADS", .desc = "Number of segment register loads.", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x6, }, { .name = "MMX_SAT_INSTR_EXEC", .desc = "Number of MMX saturating instructions executed", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xb1, }, { .name = "MMX_UOPS_EXEC", .desc = "Number of MMX micro-ops executed", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xb2, }, { .name = "MMX_INSTR_TYPE_EXEC", .desc = "Number of MMX instructions executed by type", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xb3, .numasks = LIBPFM_ARRAY_SIZE(pm_mmx_instr_type_exec), .ngrp = 1, .umasks = pm_mmx_instr_type_exec, }, { .name = "FP_MMX_TRANS", .desc = "Number of MMX transitions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xcc, .numasks = LIBPFM_ARRAY_SIZE(pm_fp_mmx_trans), .ngrp = 1, .umasks = pm_fp_mmx_trans, }, { .name = "MMX_ASSIST", .desc = "Number of MMX micro-ops executed", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xcd, }, { .name = "SEG_RENAME_STALLS", .desc = "Number of Segment Register Renaming Stalls", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xd4, .numasks = LIBPFM_ARRAY_SIZE(pm_seg_rename_stalls), .ngrp = 1, .umasks = pm_seg_rename_stalls, }, { .name = "SEG_REG_RENAMES", .desc = "Number of Segment Register Renames", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xd5, .numasks = LIBPFM_ARRAY_SIZE(pm_seg_rename_stalls), .ngrp = 1, .umasks = pm_seg_rename_stalls, /* identical to actual umasks list for this event */ }, { .name = "RET_SEG_RENAMES", .desc = "Number of segment register rename events retired", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xd6, }, { .name = "EMON_KNI_PREF_DISPATCHED", .desc = "Number of Streaming SIMD extensions prefetch/weakly-ordered instructions dispatched (speculative prefetches are included in counting). Pentium III and later", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x7, .numasks = LIBPFM_ARRAY_SIZE(pm_emon_kni_pref_dispatched), .ngrp = 1, .umasks = pm_emon_kni_pref_dispatched, }, { .name = "EMON_KNI_PREF_MISS", .desc = "Number of prefetch/weakly-ordered instructions that miss all caches. Pentium III and later", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x4b, .numasks = LIBPFM_ARRAY_SIZE(pm_emon_kni_pref_dispatched), .ngrp = 1, .umasks = pm_emon_kni_pref_dispatched, /* identical to actual umasks list for this event */ }, { .name = "EMON_EST_TRANS", .desc = "Number of Enhanced Intel SpeedStep technology transitions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x58, .numasks = LIBPFM_ARRAY_SIZE(pm_emon_est_trans), .ngrp = 1, .umasks = pm_emon_est_trans, }, { .name = "EMON_THERMAL_TRIP", .desc = "Duration/occurrences in thermal trip; to count the number of thermal trips; edge detect must be used", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x59, }, { .name = "BR_INST_EXEC", .desc = "Branch instructions executed (not necessarily retired)", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x88, }, { .name = "BR_MISSP_EXEC", .desc = "Branch instructions executed that were mispredicted at execution", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x89, }, { .name = "BR_BAC_MISSP_EXEC", .desc = "Branch instructions executed that were mispredicted at Front End (BAC)", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x8a, }, { .name = "BR_CND_EXEC", .desc = "Conditional branch instructions executed", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x8b, }, { .name = "BR_CND_MISSP_EXEC", .desc = "Conditional branch instructions executed that were mispredicted", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x8c, }, { .name = "BR_IND_EXEC", .desc = "Indirect branch instructions executed", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x8d, }, { .name = "BR_IND_MISSP_EXEC", .desc = "Indirect branch instructions executed that were mispredicted", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x8e, }, { .name = "BR_RET_EXEC", .desc = "Return branch instructions executed", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x8f, }, { .name = "BR_RET_MISSP_EXEC", .desc = "Return branch instructions executed that were mispredicted at Execution", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x90, }, { .name = "BR_RET_BAC_MISSP_EXEC", .desc = "Return branch instructions executed that were mispredicted at Front End (BAC)", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x91, }, { .name = "BR_CALL_EXEC", .desc = "CALL instructions executed", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x92, }, { .name = "BR_CALL_MISSP_EXEC", .desc = "CALL instructions executed that were mispredicted", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x93, }, { .name = "BR_IND_CALL_EXEC", .desc = "Indirect CALL instructions executed", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x94, }, { .name = "EMON_SIMD_INSTR_RETIRED", .desc = "Number of retired MMX instructions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xce, }, { .name = "EMON_SYNCH_UOPS", .desc = "Sync micro-ops", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xd3, }, { .name = "EMON_ESP_UOPS", .desc = "Total number of micro-ops", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xd7, }, { .name = "EMON_FUSED_UOPS_RET", .desc = "Total number of micro-ops", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xda, .numasks = LIBPFM_ARRAY_SIZE(pm_emon_fused_uops_ret), .ngrp = 1, .umasks = pm_emon_fused_uops_ret, }, { .name = "EMON_UNFUSION", .desc = "Number of unfusion events in the ROB, happened on a FP exception to a fused micro-op", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xdb, }, { .name = "EMON_PREF_RQSTS_UP", .desc = "Number of upward prefetches issued", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xf0, }, { .name = "EMON_PREF_RQSTS_DN", .desc = "Number of downward prefetches issued", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xf8, }, { .name = "EMON_SSE_SSE2_INST_RETIRED", .desc = "Streaming SIMD extensions instructions retired", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xd8, .numasks = LIBPFM_ARRAY_SIZE(pm_emon_sse_sse2_inst_retired), .ngrp = 1, .umasks = pm_emon_sse_sse2_inst_retired, }, { .name = "EMON_SSE_SSE2_COMP_INST_RETIRED", .desc = "Computational SSE instructions retired", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xd9, .numasks = LIBPFM_ARRAY_SIZE(pm_emon_sse_sse2_inst_retired), .ngrp = 1, .umasks = pm_emon_sse_sse2_inst_retired, /* identical to actual umasks list for this event */ }, { .name = "L2_LD", .desc = "Number of L2 data loads", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x29, .numasks = LIBPFM_ARRAY_SIZE(pm_l2_ld), .ngrp = 1, .umasks = pm_l2_ld, }, { .name = "L2_LINES_IN", .desc = "Number of L2 lines allocated", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x24, .numasks = LIBPFM_ARRAY_SIZE(pm_l2_ld), .ngrp = 1, .umasks = pm_l2_ld, /* identical to actual umasks list for this event */ }, { .name = "L2_LINES_OUT", .desc = "Number of L2 lines evicted", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x26, .numasks = LIBPFM_ARRAY_SIZE(pm_l2_ld), .ngrp = 1, .umasks = pm_l2_ld, /* identical to actual umasks list for this event */ }, { .name = "L2_M_LINES_OUT", .desc = "Number of L2 M-state lines evicted", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x27, .numasks = LIBPFM_ARRAY_SIZE(pm_l2_ld), .ngrp = 1, .umasks = pm_l2_ld, /* identical to actual umasks list for this event */ }, }; libpfm-4.9.0/lib/events/cell_events.h0000664000175000017500000033644113223402656017357 0ustar eranianeranian/* * Copyright (c) 2007 TOSHIBA CORPORATION based on code from * Copyright (c) 2001-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ static pme_cell_entry_t cell_pe[] = { {.pme_name = "CYCLES", .pme_desc = "CPU cycles", .pme_code = 0x0, /* 0 */ .pme_enable_word = WORD_NONE, .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "BRANCH_COMMIT_TH0", .pme_desc = "Branch instruction committed.", .pme_code = 0x834, /* 2100 */ .pme_enable_word = WORD_0_AND_1, .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "BRANCH_FLUSH_TH0", .pme_desc = "Branch instruction that caused a misprediction flush is committed. Branch misprediction includes", .pme_code = 0x835, /* 2101 */ .pme_enable_word = WORD_0_AND_1, .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "INST_BUFF_EMPTY_TH0", .pme_desc = "Instruction buffer empty.", .pme_code = 0x836, /* 2102 */ .pme_enable_word = WORD_0_AND_1, .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "INST_ERAT_MISS_TH0", .pme_desc = "Instruction effective-address-to-real-address translation (I-ERAT) miss.", .pme_code = 0x837, /* 2103 */ .pme_enable_word = WORD_0_AND_1, .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "L1_ICACHE_MISS_CYCLES_TH0", .pme_desc = "L1 Instruction cache miss cycles. Counts the cycles from the miss event until the returned instruction is dispatched or cancelled due to branch misprediction, completion restart, or exceptions.", .pme_code = 0x838, /* 2104 */ .pme_enable_word = WORD_0_AND_1, .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "DISPATCH_BLOCKED_TH0", .pme_desc = "Valid instruction available for dispatch, but dispatch is blocked.", .pme_code = 0x83a, /* 2106 */ .pme_enable_word = WORD_0_AND_1, .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "INST_FLUSH_TH0", .pme_desc = "Instruction in pipeline stage EX7 causes a flush.", .pme_code = 0x83d, /* 2109 */ .pme_enable_word = WORD_0_AND_1, .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "PPC_INST_COMMIT_TH0", .pme_desc = "Two PowerPC instructions committed. For microcode sequences, only the last microcode operation is counted. Committed instructions are counted two at a time. If only one instruction has committed for a given cycle, this event will not be raised until another instruction has been committed in a future cycle.", .pme_code = 0x83f, /* 2111 */ .pme_enable_word = WORD_0_AND_1, .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "BRANCH_COMMIT_TH1", .pme_desc = "Branch instruction committed.", .pme_code = 0x847, /* 2119 */ .pme_enable_word = WORD_0_AND_1, .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "BRANCH_FLUSH_TH1", .pme_desc = "Branch instruction that caused a misprediction flush is committed. Branch misprediction includes", .pme_code = 0x848, /* 2120 */ .pme_enable_word = WORD_0_AND_1, .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "INST_BUFF_EMPTY_TH1", .pme_desc = "Instruction buffer empty.", .pme_code = 0x849, /* 2121 */ .pme_enable_word = WORD_0_AND_1, .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "INST_ERAT_MISS_TH1", .pme_desc = "Instruction effective-address-to-real-address translation (I-ERAT) miss.", .pme_code = 0x84a, /* 2122 */ .pme_enable_word = WORD_0_AND_1, .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "L1_ICACHE_MISS_CYCLES_TH1", .pme_desc = "L1 Instruction cache miss cycles. Counts the cycles from the miss event until the returned instruction is dispatched or cancelled due to branch misprediction, completion restart, or exceptions.", .pme_code = 0x84b, /* 2123 */ .pme_enable_word = WORD_0_AND_1, .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "DISPATCH_BLOCKED_TH1", .pme_desc = "Valid instruction available for dispatch, but dispatch is blocked.", .pme_code = 0x84d, /* 2125 */ .pme_enable_word = WORD_0_AND_1, .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "INST_FLUSH_TH1", .pme_desc = "Instruction in pipeline stage EX7 causes a flush.", .pme_code = 0x850, /* 2128 */ .pme_enable_word = WORD_0_AND_1, .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "PPC_INST_COMMIT_TH1", .pme_desc = "Two PowerPC instructions committed. For microcode sequences, only the last microcode operation is counted. Committed instructions are counted two at a time. If only one instruction has committed for a given cycle, this event will not be raised until another instruction has been committed in a future cycle.", .pme_code = 0x852, /* 2130 */ .pme_enable_word = WORD_0_AND_1, .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "DATA_ERAT_MISS_TH0", .pme_desc = "Data effective-address-to-real-address translation (D-ERAT) miss. Not speculative.", .pme_code = 0x89a, /* 2202 */ .pme_enable_word = WORD_0_AND_1, .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "ST_REQ_TH0", .pme_desc = "Store request counted at the L2 interface. Counts microcoded PPE sequences more than once. (Thread 0 and 1)", .pme_code = 0x89b, /* 2203 */ .pme_enable_word = WORD_0_AND_1, .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "LD_VALID_TH0", .pme_desc = "Load valid at a particular pipe stage. Speculative, since flushed operations are counted as well. Counts microcoded PPE sequences more than once. Misaligned flushes might be counted the first time as well. Load operations include all loads that read data from the cache, dcbt and dcbtst. Does not include load Vector/SIMD multimedia extension pattern instructions.", .pme_code = 0x89c, /* 2204 */ .pme_enable_word = WORD_0_AND_1, .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "L1_DCACHE_MISS_TH0", .pme_desc = "L1 D-cache load miss. Pulsed when there is a miss request that has a tag miss but not an ERAT miss. Speculative, since flushed operations are counted as well.", .pme_code = 0x89d, /* 2205 */ .pme_enable_word = WORD_0_AND_1, .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "DATA_ERAT_MISS_TH1", .pme_desc = "Data effective-address-to-real-address translation (D-ERAT) miss. Not speculative.", .pme_code = 0x8aa, /* 2218 */ .pme_enable_word = WORD_0_AND_1, .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "LD_VALID_TH1", .pme_desc = "Load valid at a particular pipe stage. Speculative, since flushed operations are counted as well. Counts microcoded PPE sequences more than once. Misaligned flushes might be counted the first time as well. Load operations include all loads that read data from the cache, dcbt and dcbtst. Does not include load Vector/SIMD multimedia extension pattern instructions.", .pme_code = 0x8ac, /* 2220 */ .pme_enable_word = WORD_0_AND_1, .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "DATA_ERAT_MISS_TH1", .pme_desc = "L1 D-cache load miss. Pulsed when there is a miss request that has a tag miss but not an ERAT miss. Speculative, since flushed operations are counted as well.", .pme_code = 0x8ad, /* 2221 */ .pme_enable_word = WORD_0_AND_1, .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "LD_MFC_MMIO", .pme_desc = "Load from MFC memory-mapped I/O (MMIO) space.", .pme_code = 0xc1c, /* 3100 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "ST_MFC_MMIO", .pme_desc = "Stores to MFC MMIO space.", .pme_code = 0xc1d, /* 3101 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "REQ_TOKEN_TYPE", .pme_desc = "Request token for even memory bank numbers 0-14.", .pme_code = 0xc22, /* 3106 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "RCV_8BEAT_DATA", .pme_desc = "Receive 8-beat data from the Element Interconnect Bus (EIB).", .pme_code = 0xc2b, /* 3115 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "SEND_8BEAT_DATA", .pme_desc = "Send 8-beat data to the EIB.", .pme_code = 0xc2c, /* 3116 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "SEND_CMD", .pme_desc = "Send a command to the EIB; includes retried commands.", .pme_code = 0xc2d, /* 3117 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "DATA_GRANT_CYCLES", .pme_desc = "Cycles between data request and data grant.", .pme_code = 0xc2e, /* 3118 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "NCU_ST_Q_NOT_EMPTY_CYCLES", .pme_desc = "The five-entry Non-Cacheable Unit (NCU) Store Command queue not empty.", .pme_code = 0xc33, /* 3123 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "L2_CACHE_HIT", .pme_desc = "Cache hit for core interface unit (CIU) loads and stores.", .pme_code = 0xc80, /* 3200 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "L2_CACHE_MISS", .pme_desc = "Cache miss for CIU loads and stores.", .pme_code = 0xc81, /* 3201 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "L2_LD_MISS", .pme_desc = "CIU load miss.", .pme_code = 0xc84, /* 3204 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "L2_ST_MISS", .pme_desc = "CIU store to Invalid state (miss).", .pme_code = 0xc85, /* 3205 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "L2_LWARX_LDARX_MISS_TH0", .pme_desc = "Load word and reserve indexed (lwarx/ldarx) for Thread 0 hits Invalid cache state", .pme_code = 0xc87, /* 3207 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "L2_STWCX_STDCX_MISS_TH0", .pme_desc = "Store word conditional indexed (stwcx/stdcx) for Thread 0 hits Invalid cache state when reservation is set.", .pme_code = 0xc8e, /* 3214 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "L2_ALL_SNOOP_SM_BUSY", .pme_desc = "All four snoop state machines busy.", .pme_code = 0xc99, /* 3225 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "L2_DCLAIM_GOOD", .pme_desc = "Data line claim (dclaim) that received good combined response; includes store/stcx/dcbz to Shared (S), Shared Last (SL),or Tagged (T) cache state; does not include dcbz to Invalid (I) cache state.", .pme_code = 0xce8, /* 3304 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "L2_DCLAIM_TO_RWITM", .pme_desc = "Dclaim converted into rwitm; may still not get to the bus if stcx is aborted .", .pme_code = 0xcef, /* 3311 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "L2_ST_TO_M_MU_E", .pme_desc = "Store to modified (M), modified unsolicited (MU), or exclusive (E) cache state.", .pme_code = 0xcf0, /* 3312 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "L2_ST_Q_FULL", .pme_desc = "8-entry store queue (STQ) full.", .pme_code = 0xcf1, /* 3313 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "L2_ST_TO_RC_ACKED", .pme_desc = "Store dispatched to RC machine is acknowledged.", .pme_code = 0xcf2, /* 3314 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "L2_GATHERABLE_ST", .pme_desc = "Gatherable store (type = 00000) received from CIU.", .pme_code = 0xcf3, /* 3315 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "L2_SNOOP_PUSH", .pme_desc = "Snoop push.", .pme_code = 0xcf6, /* 3318 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "L2_INTERVENTION_FROM_SL_E_SAME_MODE", .pme_desc = "Send intervention from (SL | E) cache state to a destination within the same CBE chip.", .pme_code = 0xcf7, /* 3319 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "L2_INTERVENTION_FROM_M_MU_SAME_MODE", .pme_desc = "Send intervention from (M | MU) cache state to a destination within the same CBE chip.", .pme_code = 0xcf8, /* 3320 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "L2_SNOOP_RETRY_CONFLICTS", .pme_desc = "Respond with Retry to a snooped request due to one of the following conflicts", .pme_code = 0xcfd, /* 3325 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "L2_SNOOP_RETRY_BUSY", .pme_desc = "Respond with Retry to a snooped request because all snoop machines are busy.", .pme_code = 0xcfe, /* 3326 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "L2_SNOOP_RESP_MMU_TO_EST", .pme_desc = "Snooped response causes a cache state transition from (M | MU) to (E | S | T).", .pme_code = 0xcff, /* 3327 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "L2_SNOOP_RESP_E_TO_S", .pme_desc = "Snooped response causes a cache state transition from E to S.", .pme_code = 0xd00, /* 3328 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "L2_SNOOP_RESP_ESLST_TO_I", .pme_desc = "Snooped response causes a cache state transition from (E | SL | S | T) to Invalid (I).", .pme_code = 0xd01, /* 3329 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "L2_SNOOP_RESP_MMU_TO_I", .pme_desc = "Snooped response causes a cache state transition from (M | MU) to I.", .pme_code = 0xd02, /* 3330 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "L2_LWARX_LDARX_MISS_TH1", .pme_desc = "Load and reserve indexed (lwarx/ldarx) for Thread 1 hits Invalid cache state.", .pme_code = 0xd54, /* 3412 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "L2_STWCX_STDCX_MISS_TH1", .pme_desc = "Store conditional indexed (stwcx/stdcx) for Thread 1 hits Invalid cache state.", .pme_code = 0xd5b, /* 3419 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "NCU_NON_CACHEABLE_ST_ALL", .pme_desc = "Non-cacheable store request received from CIU; includes all synchronization operations such as sync and eieio.", .pme_code = 0xdac, /* 3500 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "NCU_SYNC_REQ", .pme_desc = "sync received from CIU.", .pme_code = 0xdad, /* 3501 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "NCU_NON_CACHEABLE_ST", .pme_desc = "Non-cacheable store request received from CIU; includes only stores.", .pme_code = 0xdb0, /* 3504 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "NCU_EIEIO_REQ", .pme_desc = "eieio received from CIU.", .pme_code = 0xdb2, /* 3506 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "NCU_TLBIE_REQ", .pme_desc = "tlbie received from CIU.", .pme_code = 0xdb3, /* 3507 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "NCU_SYNC_WAIT", .pme_desc = "sync at the bottom of the store queue, while waiting on st_done signal from the Bus Interface Unit (BIU) and sync_done signal from L2.", .pme_code = 0xdb4, /* 3508 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "NCU_LWSYNC_WAIT", .pme_desc = "lwsync at the bottom of the store queue, while waiting for a sync_done signal from the L2.", .pme_code = 0xdb5, /* 3509 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "NCU_EIEIO_WAIT", .pme_desc = "eieio at the bottom of the store queue, while waiting for a st_done signal from the BIU and a sync_done signal from the L2.", .pme_code = 0xdb6, /* 3510 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "NCU_TLBIE_WAIT", .pme_desc = "tlbie at the bottom of the store queue, while waiting for a st_done signal from the BIU.", .pme_code = 0xdb7, /* 3511 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "NCU_COMBINED_NON_CACHEABLE_ST", .pme_desc = "Non-cacheable store combined with the previous non-cacheable store with a contiguous address.", .pme_code = 0xdb8, /* 3512 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "NCU_ALL_ST_GATHER_BUFFS_FULL", .pme_desc = "All four store-gather buffers full.", .pme_code = 0xdbb, /* 3515 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "NCU_LD_REQ", .pme_desc = "Non-cacheable load request received from CIU; includes instruction and data fetches.", .pme_code = 0xdbc, /* 3516 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "NCU_ST_Q_NOT_EMPTY", .pme_desc = "The four-deep store queue not empty.", .pme_code = 0xdbd, /* 3517 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "NCU_ST_Q_FULL", .pme_desc = "The four-deep store queue full.", .pme_code = 0xdbe, /* 3518 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "NCU_AT_LEAST_ONE_ST_GATHER_BUFF_NOT_EMPTY", .pme_desc = "At least one store gather buffer not empty.", .pme_code = 0xdbf, /* 3519 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "SPU_DUAL_INST_COMMITTED", .pme_desc = "A dual instruction is committed.", .pme_code = 0x1004, /* 4100 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_SPU, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "SPU_SINGLE_INST_COMMITTED", .pme_desc = "A single instruction is committed.", .pme_code = 0x1005, /* 4101 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_SPU, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "SPU_PIPE0_INST_COMMITTED", .pme_desc = "A pipeline 0 instruction is committed.", .pme_code = 0x1006, /* 4102 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_SPU, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "SPU_PIPE1_INST_COMMITTED", .pme_desc = "A pipeline 1 instruction is committed.", .pme_code = 0x1007, /* 4103 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_SPU, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "SPU_LS_BUSY", .pme_desc = "Local storage is busy.", .pme_code = 0x1009, /* 4105 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_SPU, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "SPU_DMA_CONFLICT_LD_ST", .pme_desc = "A direct memory access (DMA) might conflict with a load or store.", .pme_code = 0x100a, /* 4106 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_SPU, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "SPU_LS_ST", .pme_desc = "A store instruction to local storage is issued.", .pme_code = 0x100b, /* 4107 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_SPU, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "SPU_LS_LD", .pme_desc = "A load instruction from local storage is issued.", .pme_code = 0x100c, /* 4108 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_SPU, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "SPU_FP_EXCEPTION", .pme_desc = "A floating-point unit exception occurred.", .pme_code = 0x100d, /* 4109 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_SPU, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "SPU_BRANCH_COMMIT", .pme_desc = "A branch instruction is committed.", .pme_code = 0x100e, /* 4110 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_SPU, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "SPU_NON_SEQ_PC", .pme_desc = "A nonsequential change of the SPU program counter has occurred. This can be caused by branch, asynchronous interrupt, stalled wait on channel, error-correction code (ECC) error, and so forth.", .pme_code = 0x100f, /* 4111 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_SPU, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "SPU_BRANCH_NOT_TAKEN", .pme_desc = "A branch was not taken.", .pme_code = 0x1010, /* 4112 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_SPU, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "SPU_BRANCH_MISS_PREDICTION", .pme_desc = "Branch miss prediction. This count is not exact. Certain other code sequences can cause additional pulses on this signal.", .pme_code = 0x1011, /* 4113 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_SPU, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "SPU_BRANCH_HINT_MISS_PREDICTION", .pme_desc = "Branch hint miss prediction. This count is not exact. Certain other code sequences can cause additional pulses on this signal.", .pme_code = 0x1012, /* 4114 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_SPU, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "SPU_INST_SEQ_ERROR", .pme_desc = "Instruction sequence error", .pme_code = 0x1013, /* 4115 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_SPU, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "SPU_STALL_CH_WRITE", .pme_desc = "Stalled waiting on any blocking channel write.", .pme_code = 0x1015, /* 4117 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_SPU, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "SPU_STALL_EXTERNAL_EVENT_CH0", .pme_desc = "Stalled waiting on external event status (Channel 0).", .pme_code = 0x1016, /* 4118 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_SPU, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "SPU_STALL_SIGNAL_1_CH3", .pme_desc = "Stalled waiting on SPU Signal Notification 1 (Channel 3).", .pme_code = 0x1017, /* 4119 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_SPU, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "SPU_STALL_SIGNAL_2_CH4", .pme_desc = "Stalled waiting on SPU Signal Notification 2 (Channel 4).", .pme_code = 0x1018, /* 4120 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_SPU, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "SPU_STALL_DMA_CH21", .pme_desc = "Stalled waiting on DMA Command Opcode or ClassID Register (Channel 21).", .pme_code = 0x1019, /* 4121 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_SPU, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "SPU_STALL_MFC_READ_CH24", .pme_desc = "Stalled waiting on memory flow control (MFC) Read Tag-Group Status (Channel 24).", .pme_code = 0x101a, /* 4122 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_SPU, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "SPU_STALL_MFC_READ_CH25", .pme_desc = "Stalled waiting on MFC Read List Stall-and-Notify Tag Status (Channel 25).", .pme_code = 0x101b, /* 4123 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_SPU, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "SPU_STALL_OUTBOUND_MAILBOX_WRITE_CH28", .pme_desc = "Stalled waiting on SPU Write Outbound Mailbox (Channel 28).", .pme_code = 0x101c, /* 4124 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_SPU, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "SPU_STALL_MAILBOX_CH29", .pme_desc = "Stalled waiting on SPU Mailbox (Channel 29).", .pme_code = 0x1022, /* 4130 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_SPU, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "SPU_TR_STALL_CH", .pme_desc = "Stalled waiting on a channel operation.", .pme_code = 0x10a1, /* 4257 */ .pme_enable_word = WORD_NONE, .pme_freq = PFM_CELL_PME_FREQ_SPU, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "SPU_EV_INST_FETCH_STALL", .pme_desc = "Instruction fetch stall", .pme_code = 0x1107, /* 4359 */ .pme_enable_word = WORD_NONE, .pme_freq = PFM_CELL_PME_FREQ_SPU, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "SPU_EV_ADDR_TRACE", .pme_desc = "Serialized SPU address (program counter) trace.", .pme_code = 0x110b, /* 4363 */ .pme_enable_word = 0xF, .pme_freq = PFM_CELL_PME_FREQ_SPU, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "MFC_ATOMIC_LD", .pme_desc = "An atomic load was received from direct memory access controller (DMAC).", .pme_code = 0x13ed, /* 5101 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "MFC_ATOMIC_DCLAIM", .pme_desc = "An atomic dclaim was sent to synergistic bus interface (SBI); includes retried requests.", .pme_code = 0x13ee, /* 5102 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "MFC_ATOMIC_RWITM", .pme_desc = "An atomic rwitm performed was sent to SBI; includes retried requests.", .pme_code = 0x13ef, /* 5103 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "MFC_ATOMIC_LD_CACHE_MISS_MU", .pme_desc = "An atomic load miss caused MU cache state.", .pme_code = 0x13f0, /* 5104 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "MFC_ATOMIC_LD_CACHE_MISS_E", .pme_desc = "An atomic load miss caused E cache state.", .pme_code = 0x13f1, /* 5105 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "MFC_ATOMIC_LD_CACHE_MISS_SL", .pme_desc = "An atomic load miss caused SL cache state.", .pme_code = 0x13f2, /* 5106 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "MFC_ATOMIC_LD_CACHE_HIT", .pme_desc = "An atomic load hits cache.", .pme_code = 0x13f3, /* 5107 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "MFC_ATOMIC_LD_CACHE_MISS_INTERVENTION", .pme_desc = "Atomic load misses cache with data intervention; sum of signals 4 and 6 in this group.", .pme_code = 0x13f4, /* 5108 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "MFC_ATOMIC_PUTLLXC_CACHE_MISS_WO_INTERVENTION", .pme_desc = "putllc or putlluc misses cache without data intervention; for putllc, counts only when reservation is set for the address.", .pme_code = 0x13fa, /* 5114 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "MFC_SNOOP_MACHINE_BUSY", .pme_desc = "Snoop machine busy.", .pme_code = 0x13fd, /* 5117 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MFC_SNOOP_MMU_TO_I", .pme_desc = "A snoop caused cache transition from [M | MU] to I.", .pme_code = 0x13ff, /* 5119 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "MFC_SNOOP_ESSL_TO_I", .pme_desc = "A snoop caused cache transition from [E | S | SL] to I.", .pme_code = 0x1401, /* 5121 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "MFC_SNOOP_MU_TO_T", .pme_desc = "A snoop caused cache transition from MU to T cache state.", .pme_code = 0x1403, /* 5123 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "MFC_SENT_INTERVENTION_LOCAL", .pme_desc = "Sent modified data intervention to a destination within the same CBE chip.", .pme_code = 0x1407, /* 5127 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "MFC_ANY_DMA_GET", .pme_desc = "Any flavor of DMA get[] command issued to Synergistic Bus Interface (SBI); sum of signals 17-25 in this group.", .pme_code = 0x1450, /* 5200 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "MFC_ANY_DMA_PUT", .pme_desc = "Any flavor of DMA put[] command issued to SBI; sum of signals 2-16 in this group.", .pme_code = 0x1451, /* 5201 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "MFC_DMA_PUT", .pme_desc = "DMA put (put) is issued to SBI.", .pme_code = 0x1452, /* 5202 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "MFC_DMA_GET", .pme_desc = "DMA get data from effective address to local storage (get) issued to SBI.", .pme_code = 0x1461, /* 5217 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "MFC_LD_REQ", .pme_desc = "Load request sent to element interconnect bus (EIB); includes read, read atomic, rwitm, rwitm atomic, and retried commands.", .pme_code = 0x14b8, /* 5304 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "MFC_ST_REQ", .pme_desc = "Store request sent to EIB; includes wwf, wwc, wwk, dclaim, dclaim atomic, and retried commands.", .pme_code = 0x14b9, /* 5305 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "MFC_RECV_DATA", .pme_desc = "Received data from EIB, including partial cache line data.", .pme_code = 0x14ba, /* 5306 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "MFC_SENT_DATA", .pme_desc = "Sent data to EIB, both as a master and a snooper.", .pme_code = 0x14bb, /* 5307 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "MFC_SBI_Q_NOT_EMPTY", .pme_desc = "16-deep synergistic bus interface (SBI) queue with outgoing requests not empty; does not include atomic requests.", .pme_code = 0x14bc, /* 5308 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MFC_SBI_Q_FULL", .pme_desc = "16-deep SBI queue with outgoing requests full; does not include atomic requests.", .pme_code = 0x14bd, /* 5309 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MFC_SENT_REQ", .pme_desc = "Sent request to EIB.", .pme_code = 0x14be, /* 5310 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "MFC_RECV_DATA_BUS_GRANT", .pme_desc = "Received data bus grant; includes data sent for MMIO operations.", .pme_code = 0x14c0, /* 5312 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "MFC_WAIT_DATA_BUS_GRANT", .pme_desc = "Cycles between data bus request and data bus grant.", .pme_code = 0x14c1, /* 5313 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MFC_CMD_O_MEM", .pme_desc = "Command (read or write) for an odd-numbered memory bank; valid only when resource allocation is turned on.", .pme_code = 0x14c2, /* 5314 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "MFC_CMD_E_MEM", .pme_desc = "Command (read or write) for an even-numbered memory bank; valid only when resource allocation is turned on.", .pme_code = 0x14c3, /* 5315 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "MFC_RECV_RETRY_RESP", .pme_desc = "Request gets the Retry response; includes local and global requests.", .pme_code = 0x14c6, /* 5318 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "MFC_SENT_DATA_BUS_REQ", .pme_desc = "Sent data bus request to EIB.", .pme_code = 0x14c7, /* 5319 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "MFC_TLB_MISS", .pme_desc = "Translation Lookaside Buffer (TLB) miss without parity or protection errors.", .pme_code = 0x1518, /* 5400 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "MFC_TLB_CYCLES", .pme_desc = "TLB miss (cycles).", .pme_code = 0x1519, /* 5401 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MFC_TLB_HIT", .pme_desc = "TLB hit.", .pme_code = 0x151a, /* 5402 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_READ_RWITM_1", .pme_desc = "Number of read and rwitm commands (including atomic) AC1 to AC0. (Group 1)", .pme_code = 0x17d4, /* 6100 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_DCLAIM_1", .pme_desc = "Number of dclaim commands (including atomic) AC1 to AC0. (Group 1)", .pme_code = 0x17d5, /* 6101 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_WWK_WWC_WWF_1", .pme_desc = "Number of wwk, wwc, and wwf commands from AC1 to AC0. (Group 1)", .pme_code = 0x17d6, /* 6102 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_SYNC_TLBSYNC_EIEIO_1", .pme_desc = "Number of sync, tlbsync, and eieio commands from AC1 to AC0. (Group 1)", .pme_code = 0x17d7, /* 6103 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_TLBIE_1", .pme_desc = "Number of tlbie commands from AC1 to AC0. (Group 1)", .pme_code = 0x17d8, /* 6104 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_PAAM_CAM_HIT_1", .pme_desc = "Previous adjacent address match (PAAM) Content Addressable Memory (CAM) hit. (Group 1)", .pme_code = 0x17df, /* 6111 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_PAAM_CAM_MISS_1", .pme_desc = "PAAM CAM miss. (Group 1)", .pme_code = 0x17e0, /* 6112 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_CMD_REFLECTED_1", .pme_desc = "Command reflected. (Group 1)", .pme_code = 0x17e2, /* 6114 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_READ_RWITM_2", .pme_desc = "Number of read and rwitm commands (including atomic) AC1 to AC0. (Group 2)", .pme_code = 0x17e4, /* 6116 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_DCLAIM_2", .pme_desc = "Number of dclaim commands (including atomic) AC1 to AC0. (Group 2)", .pme_code = 0x17e5, /* 6117 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_WWK_WWC_WWF_2", .pme_desc = "Number of wwk, wwc, and wwf commands from AC1 to AC0. (Group 2)", .pme_code = 0x17e6, /* 6118 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_SYNC_TLBSYNC_EIEIO_2", .pme_desc = "Number of sync, tlbsync, and eieio commands from AC1 to AC0. (Group 2)", .pme_code = 0x17e7, /* 6119 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_TLBIE_2", .pme_desc = "Number of tlbie commands from AC1 to AC0. (Group 2)", .pme_code = 0x17e8, /* 6120 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_PAAM_CAM_HIT_2", .pme_desc = "PAAM CAM hit. (Group 2)", .pme_code = 0x17ef, /* 6127 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_PAAM_CAM_MISS_2", .pme_desc = "PAAM CAM miss. (Group 2)", .pme_code = 0x17f0, /* 6128 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_CMD_REFLECTED_2", .pme_desc = "Command reflected. (Group 2)", .pme_code = 0x17f2, /* 6130 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_LOCAL_CMD_FROM_SPE6", .pme_desc = "Local command from SPE 6.", .pme_code = 0x1839, /* 6201 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_LOCAL_CMD_FROM_SPE4", .pme_desc = "Local command from SPE 4.", .pme_code = 0x183a, /* 6202 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_LOCAL_CME_FROM_SPE2", .pme_desc = "Local command from SPE 2.", .pme_code = 0x183b, /* 6203 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_LOCAL_CMD_FROM_PPE", .pme_desc = "Local command from PPE.", .pme_code = 0x183d, /* 6205 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_LOCAL_CMD_FROM_SPE1", .pme_desc = "Local command from SPE 1.", .pme_code = 0x183e, /* 6206 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_LOCAL_CMD_FROM_SPE3", .pme_desc = "Local command from SPE 3.", .pme_code = 0x183f, /* 6207 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_LOCAL_CMD_FROM_SPE5", .pme_desc = "Local command from SPE 5.", .pme_code = 0x1840, /* 6208 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_LOCAL_CMD_FROM_SPE7", .pme_desc = "Local command from SPE 7.", .pme_code = 0x1841, /* 6209 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_GLOBAL_CMD_FROM_SPE6", .pme_desc = "AC1-to-AC0 global command from SPE 6.", .pme_code = 0x1844, /* 6212 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_GLOBAL_CMD_FROM_SPE4", .pme_desc = "AC1-to-AC0 global command from SPE 4.", .pme_code = 0x1845, /* 6213 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_GLOBAL_CMD_FROM_SPE2", .pme_desc = "AC1-to-AC0 global command from SPE 2.", .pme_code = 0x1846, /* 6214 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_GLOBAL_CMD_FROM_SPE0", .pme_desc = "AC1-to-AC0 global command from SPE 0.", .pme_code = 0x1847, /* 6215 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_GLOBAL_CMD_FROM_PPE", .pme_desc = "AC1-to-AC0 global command from PPE.", .pme_code = 0x1848, /* 6216 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_GLOBAL_CMD_FROM_SPE1", .pme_desc = "AC1-to-AC0 global command from SPE 1.", .pme_code = 0x1849, /* 6217 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_GLOBAL_CMD_FROM_SPE3", .pme_desc = "AC1-to-AC0 global command from SPE 3.", .pme_code = 0x184a, /* 6218 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_GLOBAL_CMD_FROM_SPE5", .pme_desc = "AC1-to-AC0 global command from SPE 5.", .pme_code = 0x184b, /* 6219 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_GLOBAL_CMD_FROM_SPE7", .pme_desc = "AC1-to-AC0 global command from SPE 7", .pme_code = 0x184c, /* 6220 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_AC1_REFLECTING_LOCAL_CMD", .pme_desc = "AC1 is reflecting any local command.", .pme_code = 0x184e, /* 6222 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_AC1_SEND_GLOBAL_CMD", .pme_desc = "AC1 sends a global command to AC0.", .pme_code = 0x184f, /* 6223 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_AC0_REFLECT_GLOBAL_CMD", .pme_desc = "AC0 reflects a global command back to AC1.", .pme_code = 0x1850, /* 6224 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_AC1_REFLECT_CMD_TO_BM", .pme_desc = "AC1 reflects a command back to the bus masters.", .pme_code = 0x1851, /* 6225 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_GRANT_DATA_RING0_1", .pme_desc = "Grant on data ring 0.", .pme_code = 0x189c, /* 6300 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_GRANT_DATA_RING1_1", .pme_desc = "Grant on data ring 1.", .pme_code = 0x189d, /* 6301 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_GRANT_DATA_RING2_1", .pme_desc = "Grant on data ring 2.", .pme_code = 0x189e, /* 6302 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_GRANT_DATA_RING3_1", .pme_desc = "Grant on data ring 3.", .pme_code = 0x189f, /* 6303 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_DATA_RING0_INUSE_1", .pme_desc = "Data ring 0 is in use.", .pme_code = 0x18a0, /* 6304 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_DATA_RING1_INUSE_1", .pme_desc = "Data ring 1 is in use.", .pme_code = 0x18a1, /* 6305 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_DATA_RING2_INUSE_1", .pme_desc = "Data ring 2 is in use.", .pme_code = 0x18a2, /* 6306 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_DATA_RING3_INUSE_1", .pme_desc = "Data ring 3 is in use.", .pme_code = 0x18a3, /* 6307 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_ALL_DATA_RINGS_IDLE_1", .pme_desc = "All data rings are idle.", .pme_code = 0x18a4, /* 6308 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_ONE_DATA_RING_BUSY_1", .pme_desc = "One data ring is busy.", .pme_code = 0x18a5, /* 6309 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_TWO_OR_THREE_DATA_RINGS_BUSY_1", .pme_desc = "Two or three data rings are busy.", .pme_code = 0x18a6, /* 6310 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_ALL_DATA_RINGS_BUSY_1", .pme_desc = "All data rings are busy.", .pme_code = 0x18a7, /* 6311 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_IOIF0_DATA_REQ_PENDING_1", .pme_desc = "BIC(IOIF0) data request pending.", .pme_code = 0x18a8, /* 6312 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "EIB_SPE6_DATA_REQ_PENDING_1", .pme_desc = "SPE 6 data request pending.", .pme_code = 0x18a9, /* 6313 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "EIB_SPE4_DATA_REQ_PENDING_1", .pme_desc = "SPE 4 data request pending.", .pme_code = 0x18aa, /* 6314 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "EIB_SPE2_DATA_REQ_PENDING_1", .pme_desc = "SPE 2 data request pending.", .pme_code = 0x18ab, /* 6315 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "EIB_SPE0_DATA_REQ_PENDING_1", .pme_desc = "SPE 0 data request pending.", .pme_code = 0x18ac, /* 6316 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "EIB_MIC_DATA_REQ_PENDING_1", .pme_desc = "MIC data request pending.", .pme_code = 0x18ad, /* 6317 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "EIB_PPE_DATA_REQ_PENDING_1", .pme_desc = "PPE data request pending.", .pme_code = 0x18ae, /* 6318 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "EIB_SPE1_DATA_REQ_PENDING_1", .pme_desc = "SPE 1 data request pending.", .pme_code = 0x18af, /* 6319 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "EIB_SPE3_DATA_REQ_PENDING_1", .pme_desc = "SPE 3 data request pending.", .pme_code = 0x18b0, /* 6320 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "EIB_SPE5_DATA_REQ_PENDING_1", .pme_desc = "SPE 5 data request pending.", .pme_code = 0x18b1, /* 6321 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "EIB_SPE7_DATA_REQ_PENDING_1", .pme_desc = "SPE 7 data request pending.", .pme_code = 0x18b2, /* 6322 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "EIB_IOIF0_DATA_DEST_1", .pme_desc = "IOIF0 is data destination.", .pme_code = 0x18b4, /* 6324 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_SPE6_DATA_DEST_1", .pme_desc = "SPE 6 is data destination.", .pme_code = 0x18b5, /* 6325 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_SPE4_DATA_DEST_1", .pme_desc = "SPE 4 is data destination.", .pme_code = 0x18b6, /* 6326 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_SPE2_DATA_DEST_1", .pme_desc = "SPE 2 is data destination.", .pme_code = 0x18b7, /* 6327 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_SPE0_DATA_DEST_1", .pme_desc = "SPE 0 is data destination.", .pme_code = 0x18b8, /* 6328 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_MIC_DATA_DEST_1", .pme_desc = "MIC is data destination.", .pme_code = 0x18b9, /* 6329 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_PPE_DATA_DEST_1", .pme_desc = "PPE is data destination.", .pme_code = 0x18ba, /* 6330 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_SPE1_DATA_DEST_1", .pme_desc = "SPE 1 is data destination.", .pme_code = 0x18bb, /* 6331 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_IOIF0_DATA_REQ_PENDING_2", .pme_desc = "BIC(IOIF0) data request pending.", .pme_code = 0x1900, /* 6400 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "EIB_SPE6_DATA_REQ_PENDING_2", .pme_desc = "SPE 6 data request pending.", .pme_code = 0x1901, /* 6401 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "EIB_SPE4_DATA_REQ_PENDING_2", .pme_desc = "SPE 4 data request pending.", .pme_code = 0x1902, /* 6402 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "EIB_SPE2_DATA_REQ_PENDING_2", .pme_desc = "SPE 2 data request pending.", .pme_code = 0x1903, /* 6403 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "EIB_SPE0_DATA_REQ_PENDING_2", .pme_desc = "SPE 0 data request pending.", .pme_code = 0x1904, /* 6404 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "EIB_MIC_DATA_REQ_PENDING_2", .pme_desc = "MIC data request pending.", .pme_code = 0x1905, /* 6405 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "EIB_PPE_DATA_REQ_PENDING_2", .pme_desc = "PPE data request pending.", .pme_code = 0x1906, /* 6406 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "EIB_SPE1_DATA_REQ_PENDING_2", .pme_desc = "SPE 1 data request pending.", .pme_code = 0x1907, /* 6407 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "EIB_SPE3_DATA_REQ_PENDING_2", .pme_desc = "SPE 3 data request pending.", .pme_code = 0x1908, /* 6408 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "EIB_SPE5_DATA_REQ_PENDING_2", .pme_desc = "SPE 5 data request pending.", .pme_code = 0x1909, /* 6409 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "EIB_SPE7_DATA_REQ_PENDING_2", .pme_desc = "SPE 7 data request pending.", .pme_code = 0x190a, /* 6410 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "EIB_IOIF1_DATA_REQ_PENDING_2", .pme_desc = "IOIF1 data request pending.", .pme_code = 0x190b, /* 6411 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "EIB_IOIF0_DATA_DEST_2", .pme_desc = "IOIF0 is data destination.", .pme_code = 0x190c, /* 6412 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_SPE6_DATA_DEST_2", .pme_desc = "SPE 6 is data destination.", .pme_code = 0x190d, /* 6413 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_SPE4_DATA_DEST_2", .pme_desc = "SPE 4 is data destination.", .pme_code = 0x190e, /* 6414 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_SPE2_DATA_DEST_2", .pme_desc = "SPE 2 is data destination.", .pme_code = 0x190f, /* 6415 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_SPE0_DATA_DEST_2", .pme_desc = "SPE 0 is data destination.", .pme_code = 0x1910, /* 6416 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_MIC_DATA_DEST_2", .pme_desc = "MIC is data destination.", .pme_code = 0x1911, /* 6417 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_PPE_DATA_DEST_2", .pme_desc = "PPE is data destination.", .pme_code = 0x1912, /* 6418 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_SPE1_DATA_DEST_2", .pme_desc = "SPE 1 is data destination.", .pme_code = 0x1913, /* 6419 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_SPE3_DATA_DEST_2", .pme_desc = "SPE 3 is data destination.", .pme_code = 0x1914, /* 6420 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_SPE5_DATA_DEST_2", .pme_desc = "SPE 5 is data destination.", .pme_code = 0x1915, /* 6421 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_SPE7_DATA_DEST_2", .pme_desc = "SPE 7 is data destination.", .pme_code = 0x1916, /* 6422 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_IOIF1_DATA_DEST_2", .pme_desc = "IOIF1 is data destination.", .pme_code = 0x1917, /* 6423 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_GRANT_DATA_RING0_2", .pme_desc = "Grant on data ring 0.", .pme_code = 0x1918, /* 6424 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_GRANT_DATA_RING1_2", .pme_desc = "Grant on data ring 1.", .pme_code = 0x1919, /* 6425 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_GRANT_DATA_RING2_2", .pme_desc = "Grant on data ring 2.", .pme_code = 0x191a, /* 6426 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_GRANT_DATA_RING3_2", .pme_desc = "Grant on data ring 3.", .pme_code = 0x191b, /* 6427 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_ALL_DATA_RINGS_IDLE_2", .pme_desc = "All data rings are idle.", .pme_code = 0x191c, /* 6428 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_ONE_DATA_RING_BUSY_2", .pme_desc = "One data ring is busy.", .pme_code = 0x191d, /* 6429 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_TWO_OR_THREE_DATA_RINGS_BUSY_2", .pme_desc = "Two or three data rings are busy.", .pme_code = 0x191e, /* 6430 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_ALL_DATA_RINGS_BUSY_2", .pme_desc = "All four data rings are busy.", .pme_code = 0x191f, /* 6431 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG0_E_XIO_UNUSED", .pme_desc = "Even XIO token unused by RAG 0.", .pme_code = 0xfe4c, /* 65100 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG0_O_XIO_UNUSED", .pme_desc = "Odd XIO token unused by RAG 0.", .pme_code = 0xfe4d, /* 65101 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG0_E_BANK_UNUSED", .pme_desc = "Even bank token unused by RAG 0.", .pme_code = 0xfe4e, /* 65102 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG0_O_BANK_UNUSED", .pme_desc = "Odd bank token unused by RAG 0.", .pme_code = 0xfe4f, /* 65103 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_TOKEN_GRANTED_SPE0", .pme_desc = "Token granted for SPE 0.", .pme_code = 0xfe54, /* 65108 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_TOKEN_GRANTED_SPE1", .pme_desc = "Token granted for SPE 1.", .pme_code = 0xfe55, /* 65109 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_TOKEN_GRANTED_SPE2", .pme_desc = "Token granted for SPE 2.", .pme_code = 0xfe56, /* 65110 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_TOKEN_GRANTED_SPE3", .pme_desc = "Token granted for SPE 3.", .pme_code = 0xfe57, /* 65111 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_TOKEN_GRANTED_SPE4", .pme_desc = "Token granted for SPE 4.", .pme_code = 0xfe58, /* 65112 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_TOKEN_GRANTED_SPE5", .pme_desc = "Token granted for SPE 5.", .pme_code = 0xfe59, /* 65113 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_TOKEN_GRANTED_SPE6", .pme_desc = "Token granted for SPE 6.", .pme_code = 0xfe5a, /* 65114 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_TOKEN_GRANTED_SPE7", .pme_desc = "Token granted for SPE 7.", .pme_code = 0xfe5b, /* 65115 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG0_E_XIO_WASTED", .pme_desc = "Even XIO token wasted by RAG 0; valid only when Unused Enable (UE) = 1 in TKM_CR register.", .pme_code = 0xfeb0, /* 65200 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG0_O_XIO_WASTED", .pme_desc = "Odd XIO token wasted by RAG 0; valid only when Unused Enable (UE) = 1 in TKM_CR register.", .pme_code = 0xfeb1, /* 65201 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG0_E_BANK_WASTED", .pme_desc = "Even bank token wasted by RAG 0; valid only when Unused Enable (UE) = 1 in TKM_CR register.", .pme_code = 0xfeb2, /* 65202 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG0_O_BANK_WASTED", .pme_desc = "Odd bank token wasted by RAG 0; valid only when Unused Enable (UE) = 1 in TKM_CR register.", .pme_code = 0xfeb3, /* 65203 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAGU_E_XIO_WASTED", .pme_desc = "Even XIO token wasted by RAG U.", .pme_code = 0xfebc, /* 65212 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAGU_O_XIO_WASTED", .pme_desc = "Odd XIO token wasted by RAG U.", .pme_code = 0xfebd, /* 65213 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAGU_E_BANK_WASTED", .pme_desc = "Even bank token wasted by RAG U.", .pme_code = 0xfebe, /* 65214 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAGU_O_BANK_WASTED", .pme_desc = "Odd bank token wasted by RAG U.", .pme_code = 0xfebf, /* 65215 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG0_E_XIO_RAG1", .pme_desc = "Even XIO token from RAG 0 shared with RAG 1", .pme_code = 0xff14, /* 65300 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG0_E_XIO_RAG2", .pme_desc = "Even XIO token from RAG 0 shared with RAG 2", .pme_code = 0xff15, /* 65301 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG0_E_XIO_RAG3", .pme_desc = "Even XIO token from RAG 0 shared with RAG 3", .pme_code = 0xff16, /* 65302 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG0_O_XIO_RAG1", .pme_desc = "Odd XIO token from RAG 0 shared with RAG 1", .pme_code = 0xff17, /* 65303 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG0_O_XIO_RAG2", .pme_desc = "Odd XIO token from RAG 0 shared with RAG 2", .pme_code = 0xff18, /* 65304 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG0_O_XIO_RAG3", .pme_desc = "Odd XIO token from RAG 0 shared with RAG 3", .pme_code = 0xff19, /* 65305 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG0_E_BANK_RAG1", .pme_desc = "Even bank token from RAG 0 shared with RAG 1", .pme_code = 0xff1a, /* 65306 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG0_E_BANK_RAG2", .pme_desc = "Even bank token from RAG 0 shared with RAG 2", .pme_code = 0xff1b, /* 65307 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG0_E_BANK_RAG3", .pme_desc = "Even bank token from RAG 0 shared with RAG 3", .pme_code = 0xff1c, /* 65308 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG0_O_BANK_RAG1", .pme_desc = "Odd bank token from RAG 0 shared with RAG 1", .pme_code = 0xff1d, /* 65309 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG0_O_BANK_RAG2", .pme_desc = "Odd bank token from RAG 0 shared with RAG 2", .pme_code = 0xff1e, /* 65310 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG0_O_BANK_RAG3", .pme_desc = "Odd bank token from RAG 0 shared with RAG 3", .pme_code = 0xff1f, /* 65311 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG1_E_XIO_UNUSED", .pme_desc = "Even XIO token was unused by RAG 1.", .pme_code = 0xff88, /* 65416 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG1_O_XIO_UNUSED", .pme_desc = "Odd XIO token was unused by RAG 1.", .pme_code = 0xff89, /* 65417 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG1_E_BANK_UNUSED", .pme_desc = "Even bank token was unused by RAG 1.", .pme_code = 0xff8a, /* 65418 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG1_O_BANK_UNUSED", .pme_desc = "Odd bank token was unused by RAG 1.", .pme_code = 0xff8b, /* 65419 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_TOKEN_GRANTED_IOC0", .pme_desc = "Token was granted for IOC0.", .pme_code = 0xff91, /* 65425 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_TOKEN_GRANTED_IOC1", .pme_desc = "Token was granted for IOC1.", .pme_code = 0xff92, /* 65426 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG1_E_XIO_WASTED", .pme_desc = "Even XIO token was wasted by RAG 1. This is valid only when UE = 1 in TKM_CR.", .pme_code = 0xffec, /* 65516 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG1_O_XIO_WASTED", .pme_desc = "Odd XIO token was wasted by RAG 1. This is valid only when UE = 1 in TKM_CR.", .pme_code = 0xffed, /* 65517 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG1_E_BANK_WASTED", .pme_desc = "Even bank token was wasted by RAG 1. This is valid only when UE = 1 in TKM_CR.", .pme_code = 0xffee, /* 65518 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG1_O_BANK_WASTED", .pme_desc = "Odd bank token was wasted by RAG 1. This is valid only when UE = 1 in TKM_CR.", .pme_code = 0xffef, /* 65519 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG1_E_XIO_RAG0", .pme_desc = "Even XIO token from RAG 1 shared with RAG 0", .pme_code = 0x10050, /* 65616 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG1_E_XIO_RAG2", .pme_desc = "Even XIO token from RAG 1 shared with RAG 2", .pme_code = 0x10051, /* 65617 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG1_E_XIO_RAG3", .pme_desc = "Even XIO token from RAG 1 shared with RAG 3", .pme_code = 0x10052, /* 65618 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG1_O_XIO_RAG0", .pme_desc = "Odd XIO token from RAG 1 shared with RAG 0", .pme_code = 0x10053, /* 65619 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG1_O_XIO_RAG2", .pme_desc = "Odd XIO token from RAG 1 shared with RAG 2", .pme_code = 0x10054, /* 65620 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG1_O_XIO_RAG3", .pme_desc = "Odd XIO token from RAG 1 shared with RAG 3", .pme_code = 0x10055, /* 65621 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG1_E_BANK_RAG0", .pme_desc = "Even bank token from RAG 1 shared with RAG 0", .pme_code = 0x10056, /* 65622 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG1_E_BANK_RAG2", .pme_desc = "Even bank token from RAG 1 shared with RAG 2", .pme_code = 0x10057, /* 65623 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG1_E_BANK_RAG3", .pme_desc = "Even bank token from RAG 1 shared with RAG 3", .pme_code = 0x10058, /* 65624 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG1_O_BANK_RAG0", .pme_desc = "Odd bank token from RAG 1 shared with RAG 0", .pme_code = 0x10059, /* 65625 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG1_O_BANK_RAG2", .pme_desc = "Odd bank token from RAG 1 shared with RAG 2", .pme_code = 0x1005a, /* 65626 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG1_O_BANK_RAG3", .pme_desc = "Odd bank token from RAG 1 shared with RAG 3", .pme_code = 0x1005b, /* 65627 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAGU_E_XIO_RAG1", .pme_desc = "Even XIO token from RAG U shared with RAG 1", .pme_code = 0x1005c, /* 65628 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAGU_O_XIO_RAG1", .pme_desc = "Odd XIO token from RAG U shared with RAG 1", .pme_code = 0x1005d, /* 65629 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAGU_E_BANK_RAG1", .pme_desc = "Even bank token from RAG U shared with RAG 1", .pme_code = 0x1005e, /* 65630 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAGU_O_BANK_RAG1", .pme_desc = "Odd bank token from RAG U shared with RAG 1", .pme_code = 0x1005f, /* 65631 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG2_E_XIO_UNUSED", .pme_desc = "Even XIO token unused by RAG 2", .pme_code = 0x100e4, /* 65764 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG2_O_XIO_UNUSED", .pme_desc = "Odd XIO token unused by RAG 2", .pme_code = 0x100e5, /* 65765 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG2_E_BANK_UNUSED", .pme_desc = "Even bank token unused by RAG 2", .pme_code = 0x100e6, /* 65766 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG2_O_BANK_UNUSED", .pme_desc = "Odd bank token unused by RAG 2", .pme_code = 0x100e7, /* 65767 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG0_IOIF0_IN_TOKEN_UNUSED", .pme_desc = "IOIF0 In token unused by RAG 0", .pme_code = 0x100e8, /* 65768 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG0_IOIF0_OUT_TOKEN_UNUSED", .pme_desc = "IOIF0 Out token unused by RAG 0", .pme_code = 0x100e9, /* 65769 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG0_IOIF1_IN_TOKEN_UNUSED", .pme_desc = "IOIF1 In token unused by RAG 0", .pme_code = 0x100ea, /* 65770 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG0_IOIF1_OUT_TOKEN_UNUSED", .pme_desc = "IOIF1 Out token unused by RAG 0", .pme_code = 0x100eb, /* 65771 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG2_E_XIO_WASTED", .pme_desc = "Even XIO token wasted by RAG 2", .pme_code = 0x10148, /* 65864 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG2_O_XIO_WASTED", .pme_desc = "Odd XIO token wasted by RAG 2", .pme_code = 0x10149, /* 65865 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG2_E_BANK_WASTED", .pme_desc = "Even bank token wasted by RAG 2", .pme_code = 0x1014a, /* 65866 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG2_O_BANK_WASTED", .pme_desc = "Odd bank token wasted by RAG 2", .pme_code = 0x1014b, /* 65867 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG2_E_XIO_RAG0", .pme_desc = "Even XIO token from RAG 2 shared with RAG 0", .pme_code = 0x101ac, /* 65964 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG2_E_XIO_RAG1", .pme_desc = "Even XIO token from RAG 2 shared with RAG 1", .pme_code = 0x101ad, /* 65965 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG2_E_XIO_RAG3", .pme_desc = "Even XIO token from RAG 2 shared with RAG 3", .pme_code = 0x101ae, /* 65966 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG2_O_XIO_RAG0", .pme_desc = "Odd XIO token from RAG 2 shared with RAG 0", .pme_code = 0x101af, /* 65967 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG2_O_XIO_RAG1", .pme_desc = "Odd XIO token from RAG 2 shared with RAG 1", .pme_code = 0x101b0, /* 65968 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG2_O_XIO_RAG3", .pme_desc = "Odd XIO token from RAG 2 shared with RAG 3", .pme_code = 0x101b1, /* 65969 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG2_E_BANK_RAG0", .pme_desc = "Even bank token from RAG 2 shared with RAG 0", .pme_code = 0x101b2, /* 65970 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG2_E_BANK_RAG1", .pme_desc = "Even bank token from RAG 2 shared with RAG 1", .pme_code = 0x101b3, /* 65971 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG2_E_BANK_RAG3", .pme_desc = "Even bank token from RAG 2 shared with RAG 3", .pme_code = 0x101b4, /* 65972 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG2_O_BANK_RAG0", .pme_desc = "Odd bank token from RAG 2 shared with RAG 0", .pme_code = 0x101b5, /* 65973 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG2_O_BANK_RAG1", .pme_desc = "Odd bank token from RAG 2 shared with RAG 1", .pme_code = 0x101b6, /* 65974 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG2_O_BANK_RAG3", .pme_desc = "Odd bank token from RAG 2 shared with RAG 3", .pme_code = 0x101b7, /* 65975 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG0_IOIF0_IN_TOKEN_WASTED", .pme_desc = "IOIF0 In token wasted by RAG 0", .pme_code = 0x9ef38, /* 651064 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG0_IOIF0_OUT_TOKEN_WASTED", .pme_desc = "IOIF0 Out token wasted by RAG 0", .pme_code = 0x9ef39, /* 651065 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG0_IOIF1_IN_TOKEN_WASTED", .pme_desc = "IOIF1 In token wasted by RAG 0", .pme_code = 0x9ef3a, /* 651066 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG0_IOIF1_OUT_TOKEN_WASTED", .pme_desc = "IOIF1 Out token wasted by RAG 0", .pme_code = 0x9ef3b, /* 651067 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG3_E_XIO_UNUSED", .pme_desc = "Even XIO token was unused by RAG 3.", .pme_code = 0x9efac, /* 651180 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG3_O_XIO_UNUSED", .pme_desc = "Odd XIO token was unused by RAG 3.", .pme_code = 0x9efad, /* 651181 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG3_E_BANK_UNUSED", .pme_desc = "Even bank token was unused by RAG 3.", .pme_code = 0x9efae, /* 651182 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG3_O_BANK_UNUSED", .pme_desc = "Odd bank token was unused by RAG 3.", .pme_code = 0x9efaf, /* 651183 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG3_E_XIO_WASTED", .pme_desc = "Even XIO token wasted by RAG 3", .pme_code = 0x9f010, /* 651280 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG3_O_XIO_WASTED", .pme_desc = "Odd XIO token wasted by RAG 3", .pme_code = 0x9f011, /* 651281 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG3_E_BANK_WASTED", .pme_desc = "Even bank token wasted by RAG 3", .pme_code = 0x9f012, /* 651282 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG3_O_BANK_WASTED", .pme_desc = "Odd bank token wasted by RAG 3", .pme_code = 0x9f013, /* 651283 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG3_E_XIO_RAG0", .pme_desc = "Even XIO token from RAG 3 shared with RAG 0", .pme_code = 0x9f074, /* 651380 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG3_E_XIO_RAG1", .pme_desc = "Even XIO token from RAG 3 shared with RAG 1", .pme_code = 0x9f075, /* 651381 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG3_E_XIO_RAG2", .pme_desc = "Even XIO token from RAG 3 shared with RAG 2", .pme_code = 0x9f076, /* 651382 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG3_O_XIO_RAG0", .pme_desc = "Odd XIO token from RAG 3 shared with RAG 0", .pme_code = 0x9f077, /* 651383 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG3_O_XIO_RAG1", .pme_desc = "Odd XIO token from RAG 3 shared with RAG 1", .pme_code = 0x9f078, /* 651384 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG3_O_XIO_RAG2", .pme_desc = "Odd XIO token from RAG 3 shared with RAG 2", .pme_code = 0x9f079, /* 651385 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG3_E_BANK_RAG0", .pme_desc = "Even bank token from RAG 3 shared with RAG 0", .pme_code = 0x9f07a, /* 651386 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG3_E_BANK_RAG1", .pme_desc = "Even bank token from RAG 3 shared with RAG 1", .pme_code = 0x9f07b, /* 651387 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG3_E_BANK_RAG2", .pme_desc = "Even bank token from RAG 3 shared with RAG 2", .pme_code = 0x9f07c, /* 651388 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG3_O_BANK_RAG0", .pme_desc = "Odd bank token from RAG 3 shared with RAG 0", .pme_code = 0x9f07d, /* 651389 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG3_O_BANK_RAG1", .pme_desc = "Odd bank token from RAG 3 shared with RAG 1", .pme_code = 0x9f07e, /* 651390 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG3_O_BANK_RAG2", .pme_desc = "Odd bank token from RAG 3 shared with RAG 2", .pme_code = 0x9f07f, /* 651391 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MIC_XIO1_READ_CMD_Q_EMPTY", .pme_desc = "XIO1 - Read command queue is empty.", .pme_code = 0x1bc5, /* 7109 */ .pme_enable_word = 0xF, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MIC_XIO1_WRITE_CMD_Q_EMPTY", .pme_desc = "XIO1 - Write command queue is empty.", .pme_code = 0x1bc6, /* 7110 */ .pme_enable_word = 0xF, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MIC_XIO1_READ_CMD_Q_FULL", .pme_desc = "XIO1 - Read command queue is full.", .pme_code = 0x1bc8, /* 7112 */ .pme_enable_word = 0xF, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MIC_XIO1_RESPONDS_READ_RETRY", .pme_desc = "XIO1 - MIC responds with a Retry for a read command because the read command queue is full.", .pme_code = 0x1bc9, /* 7113 */ .pme_enable_word = 0xF, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MIC_XIO1_WRITE_CMD_Q_FULL", .pme_desc = "XIO1 - Write command queue is full.", .pme_code = 0x1bca, /* 7114 */ .pme_enable_word = 0xF, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MIC_XIO1_RESPONDS_WRITE_RETRY", .pme_desc = "XIO1 - MIC responds with a Retry for a write command because the write command queue is full.", .pme_code = 0x1bcb, /* 7115 */ .pme_enable_word = 0xF, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MIC_XIO1_READ_CMD_DISPATCHED", .pme_desc = "XIO1 - Read command dispatched; includes high-priority and fast-path reads.", .pme_code = 0x1bde, /* 7134 */ .pme_enable_word = 0xF, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MIC_XIO1_WRITE_CMD_DISPATCHED", .pme_desc = "XIO1 - Write command dispatched.", .pme_code = 0x1bdf, /* 7135 */ .pme_enable_word = 0xF, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MIC_XIO1_READ_MOD_WRITE_CMD_DISPATCHED", .pme_desc = "XIO1 - Read-Modify-Write command (data size < 16 bytes) dispatched.", .pme_code = 0x1be0, /* 7136 */ .pme_enable_word = 0xF, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MIC_XIO1_REFRESH_DISPATCHED", .pme_desc = "XIO1 - Refresh dispatched.", .pme_code = 0x1be1, /* 7137 */ .pme_enable_word = 0xF, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MIC_XIO1_BYTE_MSK_WRITE_CMD_DISPATCHED", .pme_desc = "XIO1 - Byte-masking write command (data size >= 16 bytes) dispatched.", .pme_code = 0x1be3, /* 7139 */ .pme_enable_word = 0xF, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MIC_XIO1_WRITE_CMD_DISPATCHED_AFTER_READ", .pme_desc = "XIO1 - Write command dispatched after a read command was previously dispatched.", .pme_code = 0x1be5, /* 7141 */ .pme_enable_word = 0xF, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MIC_XIO1_READ_CMD_DISPATCHED_AFTER_WRITE", .pme_desc = "XIO1 - Read command dispatched after a write command was previously dispatched.", .pme_code = 0x1be6, /* 7142 */ .pme_enable_word = 0xF, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MIC_XIO0_READ_CMD_Q_EMPTY", .pme_desc = "XIO0 - Read command queue is empty.", .pme_code = 0x1c29, /* 7209 */ .pme_enable_word = 0xF, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MIC_XIO0_WRITE_CMD_Q_EMPTY", .pme_desc = "XIO0 - Write command queue is empty.", .pme_code = 0x1c2a, /* 7210 */ .pme_enable_word = 0xF, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MIC_XIO0_READ_CMD_Q_FULL", .pme_desc = "XIO0 - Read command queue is full.", .pme_code = 0x1c2c, /* 7212 */ .pme_enable_word = 0xF, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MIC_XIO0_RESPONDS_READ_RETRY", .pme_desc = "XIO0 - MIC responds with a Retry for a read command because the read command queue is full.", .pme_code = 0x1c2d, /* 7213 */ .pme_enable_word = 0xF, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MIC_XIO0_WRITE_CMD_Q_FULL", .pme_desc = "XIO0 - Write command queue is full.", .pme_code = 0x1c2e, /* 7214 */ .pme_enable_word = 0xF, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MIC_XIO0_RESPONDS_WRITE_RETRY", .pme_desc = "XIO0 - MIC responds with a Retry for a write command because the write command queue is full.", .pme_code = 0x1c2f, /* 7215 */ .pme_enable_word = 0xF, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MIC_XIO0_READ_CMD_DISPATCHED", .pme_desc = "XIO0 - Read command dispatched; includes high-priority and fast-path reads.", .pme_code = 0x1c42, /* 7234 */ .pme_enable_word = 0xF, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MIC_XIO0_WRITE_CMD_DISPATCHED", .pme_desc = "XIO0 - Write command dispatched.", .pme_code = 0x1c43, /* 7235 */ .pme_enable_word = 0xF, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MIC_XIO0_READ_MOD_WRITE_CMD_DISPATCHED", .pme_desc = "XIO0 - Read-Modify-Write command (data size < 16 bytes) dispatched.", .pme_code = 0x1c44, /* 7236 */ .pme_enable_word = 0xF, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MIC_XIO0_REFRESH_DISPATCHED", .pme_desc = "XIO0 - Refresh dispatched.", .pme_code = 0x1c45, /* 7237 */ .pme_enable_word = 0xF, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MIC_XIO0_WRITE_CMD_DISPATCHED_AFTER_READ", .pme_desc = "XIO0 - Write command dispatched after a read command was previously dispatched.", .pme_code = 0x1c49, /* 7241 */ .pme_enable_word = 0xF, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MIC_XIO0_READ_CMD_DISPATCHED_AFTER_WRITE", .pme_desc = "XIO0 - Read command dispatched after a write command was previously dispatched.", .pme_code = 0x1c4a, /* 7242 */ .pme_enable_word = 0xF, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MIC_XIO0_WRITE_CMD_DISPATCHED_2", .pme_desc = "XIO0 - Write command dispatched.", .pme_code = 0x1ca7, /* 7335 */ .pme_enable_word = 0xF, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MIC_XIO0_READ_MOD_WRITE_CMD_DISPATCHED_2", .pme_desc = "XIO0 - Read-Modify-Write command (data size < 16 bytes) dispatched.", .pme_code = 0x1ca8, /* 7336 */ .pme_enable_word = 0xF, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MIC_XIO0_REFRESH_DISPATCHED_2", .pme_desc = "XIO0 - Refresh dispatched.", .pme_code = 0x1ca9, /* 7337 */ .pme_enable_word = 0xF, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MIC_XIO0_BYTE_MSK_WRITE_CMD_DISPATCHED", .pme_desc = "XIO0 - Byte-masking write command (data size >= 16 bytes) dispatched.", .pme_code = 0x1cab, /* 7339 */ .pme_enable_word = 0xF, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "BIF_IOIF0_TYPEA_DATA_PLG", .pme_desc = "Type A data physical layer group (PLG). Does not include header-only or credit-only data PLGs. In IOIF mode, counts I/O device read data; in BIF mode, counts all outbound data.", .pme_code = 0x1fb0, /* 8112 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "BIF_IOIF0_TYPEB_DATA_PLG", .pme_desc = "Type B data PLG. In IOIF mode, counts I/O device read data; in BIF mode, counts all outbound data.", .pme_code = 0x1fb1, /* 8113 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "BIF_IOIF0_IOIF_TYPEA_DATA_PLG", .pme_desc = "Type A data PLG. Does not include header-only or credit-only PLGs. In IOIF mode, counts CBE store data to I/O device. Does not apply in BIF mode.", .pme_code = 0x1fb2, /* 8114 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "BIF_IOIF0_IOIF_TYPEB_DATA_PLG", .pme_desc = "Type B data PLG. In IOIF mode, counts CBE store data to an I/O device. Does not apply in BIF mode.", .pme_code = 0x1fb3, /* 8115 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "BIF_IOIF0_DATA_PLG", .pme_desc = "Data PLG. Does not include header-only or credit-only PLGs.", .pme_code = 0x1fb4, /* 8116 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "BIF_IOIF0_CMD_PLG", .pme_desc = "Command PLG (no credit-only PLG). In IOIF mode, counts I/O command or reply PLGs. In BIF mode, counts command/ reflected command or snoop/combined responses.", .pme_code = 0x1fb5, /* 8117 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "BIF_IOIF0_TYPEA_TRANSFER", .pme_desc = "Type A data transfer regardless of length. Can also be used to count Type A data header PLGs (but not credit-only PLGs).", .pme_code = 0x1fb6, /* 8118 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "BIF_IOIF0_TYPEB_TRANSFER", .pme_desc = "Type B data transfer.", .pme_code = 0x1fb7, /* 8119 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "BIF_IOIF0_CMD_GREDIT_ONLY_PLG", .pme_desc = "Command-credit-only command PLG in either IOIF or BIF mode.", .pme_code = 0x1fb8, /* 8120 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "BIF_IOIF0_DATA_CREDIT_ONLY_PLG", .pme_desc = "Data-credit-only data PLG sent in either IOIF or BIF mode.", .pme_code = 0x1fb9, /* 8121 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "BIF_IOIF0_NON_NULL_ENVLP_SENT", .pme_desc = "Non-null envelope sent (does not include long envelopes).", .pme_code = 0x1fba, /* 8122 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "BIF_IOIF0_NULL_ENVLP_SENT", .pme_desc = "Null envelope sent.", .pme_code = 0x1fbc, /* 8124 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "BIF_IOIF0_NO_VALID_DATA_SENT", .pme_desc = "No valid data sent this cycle.", .pme_code = 0x1fbd, /* 8125 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "BIF_IOIF0_NORMAL_ENVLP_SENT", .pme_desc = "Normal envelope sent.", .pme_code = 0x1fbe, /* 8126 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "BIF_IOIF0_LONG_ENVLP_SENT", .pme_desc = "Long envelope sent.", .pme_code = 0x1fbf, /* 8127 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "BIF_IOIF0_NULL_PLG_INSERTED", .pme_desc = "A Null PLG inserted in an outgoing envelope.", .pme_code = 0x1fc0, /* 8128 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "BIF_IOIF0_OUTBOUND_ENV_ARRAY_FULL", .pme_desc = "Outbound envelope array is full.", .pme_code = 0x1fc1, /* 8129 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "BIF_IOIF1_TYPEB_TRANSFER", .pme_desc = "Type B data transfer.", .pme_code = 0x201b, /* 8219 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "BIF_IOIF0_NULL_ENVLP_RECV", .pme_desc = "Null envelope received.", .pme_code = 0x206d, /* 8301 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "BIF_IOIF0_CMD_PLG_2", .pme_desc = "Command PLG, but not credit-only PLG. In IOIF mode, counts I/O command or reply PLGs. In BIF mode, counts command/reflected command or snoop/combined responses.", .pme_code = 0x207a, /* 8314 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "BIF_IOIF0_CMD_GREDIT_ONLY_PLG_2", .pme_desc = "Command-credit-only command PLG.", .pme_code = 0x207b, /* 8315 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "BIF_IOIF0_NORMAL_ENVLP_RECV", .pme_desc = "Normal envelope received is good.", .pme_code = 0x2080, /* 8320 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "BIF_IOIF0_LONG_ENVLP_RECV", .pme_desc = "Long envelope received is good.", .pme_code = 0x2081, /* 8321 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "BIF_IOIF0_DATA_GREDIT_ONLY_PLG_2", .pme_desc = "Data-credit-only data PLG in either IOIF or BIF mode; will count a maximum of one per envelope.", .pme_code = 0x2082, /* 8322 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "BIF_IOIF0_NON_NULL_ENVLP", .pme_desc = "Non-null envelope; does not include long envelopes; includes retried envelopes.", .pme_code = 0x2083, /* 8323 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "BIF_IOIF0_DATA_GRANT_RECV", .pme_desc = "Data grant received.", .pme_code = 0x2084, /* 8324 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "BIF_IOIF0_DATA_PLG_2", .pme_desc = "Data PLG. Does not include header-only or credit-only PLGs.", .pme_code = 0x2088, /* 8328 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "BIF_IOIF0_TYPEA_TRANSFER_2", .pme_desc = "Type A data transfer regardless of length. Can also be used to count Type A data header PLGs, but not credit-only PLGs.", .pme_code = 0x2089, /* 8329 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "BIF_IOIF0_TYPEB_TRANSFER_2", .pme_desc = "Type B data transfer.", .pme_code = 0x208a, /* 8330 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "BIF_IOIF1_NULL_ENVLP_RECV", .pme_desc = "Null envelope received.", .pme_code = 0x20d1, /* 8401 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "BIF_IOIF1_CMD_PLG_2", .pme_desc = "Command PLG (no credit-only PLG). Counts I/O command or reply PLGs.", .pme_code = 0x20de, /* 8414 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "BIF_IOIF1_CMD_GREDIT_ONLY_PLG_2", .pme_desc = "Command-credit-only command PLG.", .pme_code = 0x20df, /* 8415 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "BIF_IOIF1_NORMAL_ENVLP_RECV", .pme_desc = "Normal envelope received is good.", .pme_code = 0x20e4, /* 8420 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "BIF_IOIF1_LONG_ENVLP_RECV", .pme_desc = "Long envelope received is good.", .pme_code = 0x20e5, /* 8421 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "BIF_IOIF1_DATA_GREDIT_ONLY_PLG_2", .pme_desc = "Data-credit-only data PLG received; will count a maximum of one per envelope.", .pme_code = 0x20e6, /* 8422 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "BIF_IOIF1_NON_NULL_ENVLP", .pme_desc = "Non-Null envelope received; does not include long envelopes; includes retried envelopes.", .pme_code = 0x20e7, /* 8423 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "BIF_IOIF1_DATA_GRANT_RECV", .pme_desc = "Data grant received.", .pme_code = 0x20e8, /* 8424 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "BIF_IOIF1_DATA_PLG_2", .pme_desc = "Data PLG received. Does not include header-only or credit-only PLGs.", .pme_code = 0x20ec, /* 8428 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "BIF_IOIF1_TYPEA_TRANSFER_2", .pme_desc = "Type I A data transfer regardless of length. Can also be used to count Type A data header PLGs (but not credit-only PLGs).", .pme_code = 0x20ed, /* 8429 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "BIF_IOIF1_TYPEB_TRANSFER_2", .pme_desc = "Type B data transfer received.", .pme_code = 0x20ee, /* 8430 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "IOC_MMIO_READ_IOIF1", .pme_desc = "Received MMIO read targeted to IOIF1.", .pme_code = 0x213c, /* 8508 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "IOC_MMIO_WRITE_IOIF1", .pme_desc = "Received MMIO write targeted to IOIF1.", .pme_code = 0x213d, /* 8509 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "IOC_MMIO_READ_IOIF0", .pme_desc = "Received MMIO read targeted to IOIF0.", .pme_code = 0x213e, /* 8510 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "IOC_MMIO_WRITE_IOIF0", .pme_desc = "Received MMIO write targeted to IOIF0.", .pme_code = 0x213f, /* 8511 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "IOC_CMD_TO_IOIF0", .pme_desc = "Sent command to IOIF0.", .pme_code = 0x2140, /* 8512 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "IOC_CMD_TO_IOIF1", .pme_desc = "Sent command to IOIF1.", .pme_code = 0x2141, /* 8513 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "IOC_IOIF0_MATRIX3_OCCUPIED", .pme_desc = "IOIF0 Dependency Matrix 3 is occupied by a dependent command.", .pme_code = 0x219d, /* 8605 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "IOC_IOIF0_MATRIX4_OCCUPIED", .pme_desc = "IOIF0 Dependency Matrix 4 is occupied by a dependent command.", .pme_code = 0x219e, /* 8606 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "IOC_IOIF0_MATRIX5_OCCUPIED", .pme_desc = "IOIF0 Dependency Matrix 5 is occupied by a dependent command.", .pme_code = 0x219f, /* 8607 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "IOC_DMA_READ_IOIF0", .pme_desc = "Received read request from IOIF0.", .pme_code = 0x21a2, /* 8610 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "IOC_DMA_WRITE_IOIF0", .pme_desc = "Received write request from IOIF0.", .pme_code = 0x21a3, /* 8611 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "IOC_INTERRUPT_IOIF0", .pme_desc = "Received interrupt from the IOIF0.", .pme_code = 0x21a6, /* 8614 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "IOC_IOIF0_REQ_TOKEN_E_MEM", .pme_desc = "IOIF0 request for token for even memory banks 0-14.", .pme_code = 0x220c, /* 8716 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "IOC_IOIF0_REQ_TOKEN_O_MEM", .pme_desc = "IOIF0 request for token for odd memory banks 1-15.", .pme_code = 0x220d, /* 8717 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "IOC_IOIF0_REQ_TOKEN_1357", .pme_desc = "IOIF0 request for token type 1, 3, 5, or 7.", .pme_code = 0x220e, /* 8718 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "IOC_IOIF0_REQ_TOKEN_9111315", .pme_desc = "IOIF0 request for token type 9, 11, 13, or 15.", .pme_code = 0x220f, /* 8719 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "IOC_IOIF0_REQ_TOKEN_16", .pme_desc = "IOIF0 request for token type 16.", .pme_code = 0x2214, /* 8724 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "IOC_IOIF0_REQ_TOKEN_17", .pme_desc = "IOIF0 request for token type 17.", .pme_code = 0x2215, /* 8725 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "IOC_IOIF0_REQ_TOKEN_18", .pme_desc = "IOIF0 request for token type 18.", .pme_code = 0x2216, /* 8726 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "IOC_IOIF0_REQ_TOKEN_19", .pme_desc = "IOIF0 request for token type 19.", .pme_code = 0x2217, /* 8727 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "IOC_IOPT_CACHE_HIT", .pme_desc = "I/O page table cache hit for commands from IOIF.", .pme_code = 0x2260, /* 8800 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "IOC_IOPT_CACHE_MISS", .pme_desc = "I/O page table cache miss for commands from IOIF.", .pme_code = 0x2261, /* 8801 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "IOC_IOST_CACHE_HIT", .pme_desc = "I/O segment table cache hit.", .pme_code = 0x2263, /* 8803 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "IOC_IOST_CACHE_MISS", .pme_desc = "I/O segment table cache miss.", .pme_code = 0x2264, /* 8804 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "IOC_INTERRUPT_FROM_SPU", .pme_desc = "Interrupt received from any SPU (reflected cmd when IIC has sent ACK response).", .pme_code = 0x2278, /* 8824 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "IOC_IIC_INTERRUPT_TO_PPU_TH0", .pme_desc = "Internal interrupt controller (IIC) generated interrupt to PPU thread 0.", .pme_code = 0x2279, /* 8825 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "IOC_IIC_INTERRUPT_TO_PPU_TH1", .pme_desc = "IIC generated interrupt to PPU thread 1.", .pme_code = 0x227a, /* 8826 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "IOC_RECV_EXTERNAL_INTERRUPT_TO_TH0", .pme_desc = "Received external interrupt (using MMIO) from PPU to PPU thread 0.", .pme_code = 0x227b, /* 8827 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "IOC_RECV_EXTERNAL_INTERRUPT_TO_TH1", .pme_desc = "Received external interrupt (using MMIO) from PPU to PPU thread 1.", .pme_code = 0x227c, /* 8828 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, }; /*--- The number of events : 435 ---*/ #define PME_CELL_EVENT_COUNT (sizeof(cell_pe)/sizeof(pme_cell_entry_t)) libpfm-4.9.0/lib/events/intel_bdx_unc_r3qpi_events.h0000664000175000017500000006444013223402656022370 0ustar eranianeranian/* * Copyright (c) 2017 Google Inc. All rights reserved * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * PMU: bdx_unc_r3qpi */ static intel_x86_umask_t bdx_unc_r3_c_hi_ad_credits_empty[]={ { .uname = "CBO10", .ucode = 0x400, .udesc = "CBox AD Credits Empty", }, { .uname = "CBO11", .ucode = 0x800, .udesc = "CBox AD Credits Empty", }, { .uname = "CBO12", .ucode = 0x1000, .udesc = "CBox AD Credits Empty", }, { .uname = "CBO13", .ucode = 0x2000, .udesc = "CBox AD Credits Empty", }, { .uname = "CBO14_16", .ucode = 0x4000, .udesc = "CBox AD Credits Empty", }, { .uname = "CBO8", .ucode = 0x100, .udesc = "CBox AD Credits Empty", }, { .uname = "CBO9", .ucode = 0x200, .udesc = "CBox AD Credits Empty", }, { .uname = "CBO_15_17", .ucode = 0x8000, .udesc = "CBox AD Credits Empty", }, }; static intel_x86_umask_t bdx_unc_r3_c_lo_ad_credits_empty[]={ { .uname = "CBO0", .ucode = 0x100, .udesc = "CBox AD Credits Empty", }, { .uname = "CBO1", .ucode = 0x200, .udesc = "CBox AD Credits Empty", }, { .uname = "CBO2", .ucode = 0x400, .udesc = "CBox AD Credits Empty", }, { .uname = "CBO3", .ucode = 0x800, .udesc = "CBox AD Credits Empty", }, { .uname = "CBO4", .ucode = 0x1000, .udesc = "CBox AD Credits Empty", }, { .uname = "CBO5", .ucode = 0x2000, .udesc = "CBox AD Credits Empty", }, { .uname = "CBO6", .ucode = 0x4000, .udesc = "CBox AD Credits Empty", }, { .uname = "CBO7", .ucode = 0x8000, .udesc = "CBox AD Credits Empty", }, }; static intel_x86_umask_t bdx_unc_r3_ha_r2_bl_credits_empty[]={ { .uname = "HA0", .ucode = 0x100, .udesc = "HA/R2 AD Credits Empty", }, { .uname = "HA1", .ucode = 0x200, .udesc = "HA/R2 AD Credits Empty", }, { .uname = "R2_NCB", .ucode = 0x400, .udesc = "HA/R2 AD Credits Empty", }, { .uname = "R2_NCS", .ucode = 0x800, .udesc = "HA/R2 AD Credits Empty", }, }; static intel_x86_umask_t bdx_unc_r3_qpi0_ad_credits_empty[]={ { .uname = "VN0_HOM", .ucode = 0x200, .udesc = "VN0 HOM messages", }, { .uname = "VN0_NDR", .ucode = 0x800, .udesc = "VN0 NDR messages", }, { .uname = "VN0_SNP", .ucode = 0x400, .udesc = "VN0 SNP messages", }, { .uname = "VN1_HOM", .ucode = 0x1000, .udesc = "VN1 HOM messages", }, { .uname = "VN1_NDR", .ucode = 0x4000, .udesc = "VN1 NDR messages", }, { .uname = "VN1_SNP", .ucode = 0x2000, .udesc = "VN1 SNP messages", }, { .uname = "VNA", .ucode = 0x100, .udesc = "VNA messages", }, }; static intel_x86_umask_t bdx_unc_r3_qpi0_bl_credits_empty[]={ { .uname = "VN1_HOM", .ucode = 0x1000, .udesc = "QPIx BL Credits Empty", }, { .uname = "VN1_NDR", .ucode = 0x4000, .udesc = "QPIx BL Credits Empty", }, { .uname = "VN1_SNP", .ucode = 0x2000, .udesc = "QPIx BL Credits Empty", }, { .uname = "VNA", .ucode = 0x100, .udesc = "QPIx BL Credits Empty", }, }; static intel_x86_umask_t bdx_unc_r3_ring_ad_used[]={ { .uname = "CCW", .ucode = 0xc00, .udesc = "Counterclockwise", .uflags = INTEL_X86_NCOMBO, }, { .uname = "CCW_EVEN", .ucode = 0x400, .udesc = "Counterclockwise and Even", }, { .uname = "CCW_ODD", .ucode = 0x800, .udesc = "Counterclockwise and Odd", }, { .uname = "CW", .ucode = 0x300, .udesc = "Clockwise", .uflags = INTEL_X86_NCOMBO, }, { .uname = "CW_EVEN", .ucode = 0x100, .udesc = "Clockwise and Even", }, { .uname = "CW_ODD", .ucode = 0x200, .udesc = "Clockwise and Odd", }, }; static intel_x86_umask_t bdx_unc_r3_ring_iv_used[]={ { .uname = "ANY", .ucode = 0xf00, .udesc = "Any", .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "CW", .ucode = 0x300, .udesc = "Clockwise", .uflags = INTEL_X86_NCOMBO, }, }; static intel_x86_umask_t bdx_unc_r3_ring_sink_starved[]={ { .uname = "AK", .ucode = 0x200, .udesc = "AK", .uflags = INTEL_X86_DFL, }, }; static intel_x86_umask_t bdx_unc_r3_rxr_cycles_ne[]={ { .uname = "HOM", .ucode = 0x100, .udesc = "Ingress Cycles Not Empty -- HOM", }, { .uname = "NDR", .ucode = 0x400, .udesc = "Ingress Cycles Not Empty -- NDR", }, { .uname = "SNP", .ucode = 0x200, .udesc = "Ingress Cycles Not Empty -- SNP", }, }; static intel_x86_umask_t bdx_unc_r3_rxr_cycles_ne_vn1[]={ { .uname = "DRS", .ucode = 0x800, .udesc = "VN1 Ingress Cycles Not Empty -- DRS", }, { .uname = "HOM", .ucode = 0x100, .udesc = "VN1 Ingress Cycles Not Empty -- HOM", }, { .uname = "NCB", .ucode = 0x1000, .udesc = "VN1 Ingress Cycles Not Empty -- NCB", }, { .uname = "NCS", .ucode = 0x2000, .udesc = "VN1 Ingress Cycles Not Empty -- NCS", }, { .uname = "NDR", .ucode = 0x400, .udesc = "VN1 Ingress Cycles Not Empty -- NDR", }, { .uname = "SNP", .ucode = 0x200, .udesc = "VN1 Ingress Cycles Not Empty -- SNP", }, }; static intel_x86_umask_t bdx_unc_r3_rxr_inserts[]={ { .uname = "DRS", .ucode = 0x800, .udesc = "Ingress Allocations -- DRS", }, { .uname = "HOM", .ucode = 0x100, .udesc = "Ingress Allocations -- HOM", }, { .uname = "NCB", .ucode = 0x1000, .udesc = "Ingress Allocations -- NCB", }, { .uname = "NCS", .ucode = 0x2000, .udesc = "Ingress Allocations -- NCS", }, { .uname = "NDR", .ucode = 0x400, .udesc = "Ingress Allocations -- NDR", }, { .uname = "SNP", .ucode = 0x200, .udesc = "Ingress Allocations -- SNP", }, }; static intel_x86_umask_t bdx_unc_r3_sbo0_credits_acquired[]={ { .uname = "AD", .ucode = 0x100, .udesc = "SBo0 Credits Acquired -- For AD Ring", }, { .uname = "BL", .ucode = 0x200, .udesc = "SBo0 Credits Acquired -- For BL Ring", }, }; static intel_x86_umask_t bdx_unc_r3_sbo1_credits_acquired[]={ { .uname = "AD", .ucode = 0x100, .udesc = "SBo1 Credits Acquired -- For AD Ring", }, { .uname = "BL", .ucode = 0x200, .udesc = "SBo1 Credits Acquired -- For BL Ring", }, }; static intel_x86_umask_t bdx_unc_r3_stall_no_sbo_credit[]={ { .uname = "SBO0_AD", .ucode = 0x100, .udesc = "Stall on No Sbo Credits -- For SBo0, AD Ring", }, { .uname = "SBO0_BL", .ucode = 0x400, .udesc = "Stall on No Sbo Credits -- For SBo0, BL Ring", }, { .uname = "SBO1_AD", .ucode = 0x200, .udesc = "Stall on No Sbo Credits -- For SBo1, AD Ring", }, { .uname = "SBO1_BL", .ucode = 0x800, .udesc = "Stall on No Sbo Credits -- For SBo1, BL Ring", }, }; static intel_x86_umask_t bdx_unc_r3_txr_nack[]={ { .uname = "DN_AD", .ucode = 0x100, .udesc = "Egress CCW NACK -- AD CCW", }, { .uname = "DN_AK", .ucode = 0x400, .udesc = "Egress CCW NACK -- AK CCW", }, { .uname = "DN_BL", .ucode = 0x200, .udesc = "Egress CCW NACK -- BL CCW", }, { .uname = "UP_AD", .ucode = 0x800, .udesc = "Egress CCW NACK -- AK CCW", }, { .uname = "UP_AK", .ucode = 0x2000, .udesc = "Egress CCW NACK -- BL CW", }, { .uname = "UP_BL", .ucode = 0x1000, .udesc = "Egress CCW NACK -- BL CCW", }, }; static intel_x86_umask_t bdx_unc_r3_vn0_credits_reject[]={ { .uname = "DRS", .ucode = 0x800, .udesc = "VN0 Credit Acquisition Failed on DRS -- DRS Message Class", }, { .uname = "HOM", .ucode = 0x100, .udesc = "VN0 Credit Acquisition Failed on DRS -- HOM Message Class", }, { .uname = "NCB", .ucode = 0x1000, .udesc = "VN0 Credit Acquisition Failed on DRS -- NCB Message Class", }, { .uname = "NCS", .ucode = 0x2000, .udesc = "VN0 Credit Acquisition Failed on DRS -- NCS Message Class", }, { .uname = "NDR", .ucode = 0x400, .udesc = "VN0 Credit Acquisition Failed on DRS -- NDR Message Class", }, { .uname = "SNP", .ucode = 0x200, .udesc = "VN0 Credit Acquisition Failed on DRS -- SNP Message Class", }, }; static intel_x86_umask_t bdx_unc_r3_vn0_credits_used[]={ { .uname = "DRS", .ucode = 0x800, .udesc = "VN0 Credit Used -- DRS Message Class", }, { .uname = "HOM", .ucode = 0x100, .udesc = "VN0 Credit Used -- HOM Message Class", }, { .uname = "NCB", .ucode = 0x1000, .udesc = "VN0 Credit Used -- NCB Message Class", }, { .uname = "NCS", .ucode = 0x2000, .udesc = "VN0 Credit Used -- NCS Message Class", }, { .uname = "NDR", .ucode = 0x400, .udesc = "VN0 Credit Used -- NDR Message Class", }, { .uname = "SNP", .ucode = 0x200, .udesc = "VN0 Credit Used -- SNP Message Class", }, }; static intel_x86_umask_t bdx_unc_r3_vn1_credits_reject[]={ { .uname = "DRS", .ucode = 0x800, .udesc = "VN1 Credit Acquisition Failed on DRS -- DRS Message Class", }, { .uname = "HOM", .ucode = 0x100, .udesc = "VN1 Credit Acquisition Failed on DRS -- HOM Message Class", }, { .uname = "NCB", .ucode = 0x1000, .udesc = "VN1 Credit Acquisition Failed on DRS -- NCB Message Class", }, { .uname = "NCS", .ucode = 0x2000, .udesc = "VN1 Credit Acquisition Failed on DRS -- NCS Message Class", }, { .uname = "NDR", .ucode = 0x400, .udesc = "VN1 Credit Acquisition Failed on DRS -- NDR Message Class", }, { .uname = "SNP", .ucode = 0x200, .udesc = "VN1 Credit Acquisition Failed on DRS -- SNP Message Class", }, }; static intel_x86_umask_t bdx_unc_r3_vn1_credits_used[]={ { .uname = "DRS", .ucode = 0x800, .udesc = "VN1 Credit Used -- DRS Message Class", }, { .uname = "HOM", .ucode = 0x100, .udesc = "VN1 Credit Used -- HOM Message Class", }, { .uname = "NCB", .ucode = 0x1000, .udesc = "VN1 Credit Used -- NCB Message Class", }, { .uname = "NCS", .ucode = 0x2000, .udesc = "VN1 Credit Used -- NCS Message Class", }, { .uname = "NDR", .ucode = 0x400, .udesc = "VN1 Credit Used -- NDR Message Class", }, { .uname = "SNP", .ucode = 0x200, .udesc = "VN1 Credit Used -- SNP Message Class", }, }; static intel_x86_umask_t bdx_unc_r3_vna_credits_acquired[]={ { .uname = "AD", .ucode = 0x100, .udesc = "VNA credit Acquisitions -- HOM Message Class", }, { .uname = "BL", .ucode = 0x400, .udesc = "VNA credit Acquisitions -- HOM Message Class", }, }; static intel_x86_umask_t bdx_unc_r3_vna_credits_reject[]={ { .uname = "DRS", .ucode = 0x800, .udesc = "VNA Credit Reject -- DRS Message Class", }, { .uname = "HOM", .ucode = 0x100, .udesc = "VNA Credit Reject -- HOM Message Class", }, { .uname = "NCB", .ucode = 0x1000, .udesc = "VNA Credit Reject -- NCB Message Class", }, { .uname = "NCS", .ucode = 0x2000, .udesc = "VNA Credit Reject -- NCS Message Class", }, { .uname = "NDR", .ucode = 0x400, .udesc = "VNA Credit Reject -- NDR Message Class", }, { .uname = "SNP", .ucode = 0x200, .udesc = "VNA Credit Reject -- SNP Message Class", }, }; static intel_x86_entry_t intel_bdx_unc_r3_pe[]={ { .name = "UNC_R3_CLOCKTICKS", .code = 0x1, .desc = "Counts the number of uclks in the QPI uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the QPI Agent is close to the Ubox, they generally should not diverge by more than a handful of cycles.", .modmsk = BDX_UNC_R3QPI_ATTRS, .cntmsk = 0x7, }, { .name = "UNC_R3_C_HI_AD_CREDITS_EMPTY", .code = 0x1f, .desc = "No credits available to send to Cbox on the AD Ring (covers higher CBoxes)", .modmsk = BDX_UNC_R3QPI_ATTRS, .cntmsk = 0x3, .ngrp = 1, .umasks = bdx_unc_r3_c_hi_ad_credits_empty, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_r3_c_hi_ad_credits_empty), }, { .name = "UNC_R3_C_LO_AD_CREDITS_EMPTY", .code = 0x22, .desc = "No credits available to send to Cbox on the AD Ring (covers lower CBoxes)", .modmsk = BDX_UNC_R3QPI_ATTRS, .cntmsk = 0x3, .ngrp = 1, .umasks = bdx_unc_r3_c_lo_ad_credits_empty, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_r3_c_lo_ad_credits_empty), }, { .name = "UNC_R3_HA_R2_BL_CREDITS_EMPTY", .code = 0x2d, .desc = "No credits available to send to either HA or R2 on the BL Ring", .modmsk = BDX_UNC_R3QPI_ATTRS, .cntmsk = 0x3, .ngrp = 1, .umasks = bdx_unc_r3_ha_r2_bl_credits_empty, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_r3_ha_r2_bl_credits_empty), }, { .name = "UNC_R3_QPI0_AD_CREDITS_EMPTY", .code = 0x20, .desc = "No credits available to send to QPI0 on the AD Ring", .modmsk = BDX_UNC_R3QPI_ATTRS, .cntmsk = 0x3, .ngrp = 1, .umasks = bdx_unc_r3_qpi0_ad_credits_empty, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_r3_qpi0_ad_credits_empty), }, { .name = "UNC_R3_QPI0_BL_CREDITS_EMPTY", .code = 0x21, .desc = "No credits available to send to QPI0 on the BL Ring", .modmsk = BDX_UNC_R3QPI_ATTRS, .cntmsk = 0x3, .ngrp = 1, .umasks = bdx_unc_r3_qpi0_bl_credits_empty, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_r3_qpi0_bl_credits_empty), }, { .name = "UNC_R3_QPI1_AD_CREDITS_EMPTY", .code = 0x2e, .desc = "No credits available to send to QPI1 on the AD Ring", .modmsk = BDX_UNC_R3QPI_ATTRS, .cntmsk = 0x3, .ngrp = 1, .umasks = bdx_unc_r3_qpi0_ad_credits_empty, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_r3_qpi0_ad_credits_empty), }, { .name = "UNC_R3_QPI1_BL_CREDITS_EMPTY", .code = 0x2f, .desc = "No credits available to send to QPI1 on the BL Ring", .modmsk = BDX_UNC_R3QPI_ATTRS, .cntmsk = 0x3, .ngrp = 1, .umasks = bdx_unc_r3_qpi0_ad_credits_empty, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_r3_qpi0_ad_credits_empty), }, { .name = "UNC_R3_RING_AD_USED", .code = 0x7, .desc = "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", .modmsk = BDX_UNC_R3QPI_ATTRS, .cntmsk = 0x7, .ngrp = 1, .umasks = bdx_unc_r3_ring_ad_used, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_r3_ring_ad_used), }, { .name = "UNC_R3_RING_AK_USED", .code = 0x8, .desc = "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", .modmsk = BDX_UNC_R3QPI_ATTRS, .cntmsk = 0x7, .ngrp = 1, .umasks = bdx_unc_r3_ring_ad_used, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_r3_ring_ad_used), }, { .name = "UNC_R3_RING_BL_USED", .code = 0x9, .desc = "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", .modmsk = BDX_UNC_R3QPI_ATTRS, .cntmsk = 0x7, .ngrp = 1, .umasks = bdx_unc_r3_ring_ad_used, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_r3_ring_ad_used), }, { .name = "UNC_R3_RING_IV_USED", .code = 0xa, .desc = "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.", .modmsk = BDX_UNC_R3QPI_ATTRS, .cntmsk = 0x7, .ngrp = 1, .umasks = bdx_unc_r3_ring_iv_used, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_r3_ring_iv_used), }, { .name = "UNC_R3_RING_SINK_STARVED", .code = 0xe, .desc = "Number of cycles the ringstop is in starvation (per ring)", .modmsk = BDX_UNC_R3QPI_ATTRS, .cntmsk = 0x7, .ngrp = 1, .umasks = bdx_unc_r3_ring_sink_starved, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_r3_ring_sink_starved), }, { .name = "UNC_R3_RXR_CYCLES_NE", .code = 0x10, .desc = "Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.", .modmsk = BDX_UNC_R3QPI_ATTRS, .cntmsk = 0x3, .ngrp = 1, .umasks = bdx_unc_r3_rxr_cycles_ne, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_r3_rxr_cycles_ne), }, { .name = "UNC_R3_RXR_CYCLES_NE_VN1", .code = 0x14, .desc = "Counts the number of cycles when the QPI VN1 Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.", .modmsk = BDX_UNC_R3QPI_ATTRS, .cntmsk = 0x3, .ngrp = 1, .umasks = bdx_unc_r3_rxr_cycles_ne_vn1, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_r3_rxr_cycles_ne_vn1), }, { .name = "UNC_R3_RXR_INSERTS", .code = 0x11, .desc = "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.", .modmsk = BDX_UNC_R3QPI_ATTRS, .cntmsk = 0x3, .ngrp = 1, .umasks = bdx_unc_r3_rxr_inserts, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_r3_rxr_inserts), }, { .name = "UNC_R3_RXR_INSERTS_VN1", .code = 0x15, .desc = "Counts the number of allocations into the QPI VN1 Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.", .modmsk = BDX_UNC_R3QPI_ATTRS, .cntmsk = 0x3, .ngrp = 1, .umasks = bdx_unc_r3_rxr_inserts, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_r3_rxr_inserts), }, { .name = "UNC_R3_RXR_OCCUPANCY_VN1", .code = 0x13, .desc = "Accumulates the occupancy of a given QPI VN1 Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI VN1 Ingress Not Empty event to calculate average occupancy or the QPI VN1 Ingress Allocations event in order to calculate average queuing latency.", .modmsk = BDX_UNC_R3QPI_ATTRS, .cntmsk = 0x1, .ngrp = 1, .umasks = bdx_unc_r3_rxr_inserts, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_r3_rxr_inserts), }, { .name = "UNC_R3_SBO0_CREDITS_ACQUIRED", .code = 0x28, .desc = "Number of Sbo 0 credits acquired in a given cycle, per ring.", .modmsk = BDX_UNC_R3QPI_ATTRS, .cntmsk = 0x3, .ngrp = 1, .umasks = bdx_unc_r3_sbo0_credits_acquired, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_r3_sbo0_credits_acquired), }, { .name = "UNC_R3_SBO1_CREDITS_ACQUIRED", .code = 0x29, .desc = "Number of Sbo 1 credits acquired in a given cycle, per ring.", .modmsk = BDX_UNC_R3QPI_ATTRS, .cntmsk = 0x3, .ngrp = 1, .umasks = bdx_unc_r3_sbo1_credits_acquired, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_r3_sbo1_credits_acquired), }, { .name = "UNC_R3_STALL_NO_SBO_CREDIT", .code = 0x2c, .desc = "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.", .modmsk = BDX_UNC_R3QPI_ATTRS, .cntmsk = 0x3, .ngrp = 1, .umasks = bdx_unc_r3_stall_no_sbo_credit, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_r3_stall_no_sbo_credit), }, { .name = "UNC_R3_TXR_NACK", .code = 0x26, .desc = "", .modmsk = BDX_UNC_R3QPI_ATTRS, .cntmsk = 0x3, .ngrp = 1, .umasks = bdx_unc_r3_txr_nack, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_r3_txr_nack), }, { .name = "UNC_R3_VN0_CREDITS_REJECT", .code = 0x37, .desc = "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.", .modmsk = BDX_UNC_R3QPI_ATTRS, .cntmsk = 0x3, .ngrp = 1, .umasks = bdx_unc_r3_vn0_credits_reject, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_r3_vn0_credits_reject), }, { .name = "UNC_R3_VN0_CREDITS_USED", .code = 0x36, .desc = "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.", .modmsk = BDX_UNC_R3QPI_ATTRS, .cntmsk = 0x3, .ngrp = 1, .umasks = bdx_unc_r3_vn0_credits_used, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_r3_vn0_credits_used), }, { .name = "UNC_R3_VN1_CREDITS_REJECT", .code = 0x39, .desc = "Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.", .modmsk = BDX_UNC_R3QPI_ATTRS, .cntmsk = 0x3, .ngrp = 1, .umasks = bdx_unc_r3_vn1_credits_reject, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_r3_vn1_credits_reject), }, { .name = "UNC_R3_VN1_CREDITS_USED", .code = 0x38, .desc = "Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.", .modmsk = BDX_UNC_R3QPI_ATTRS, .cntmsk = 0x3, .ngrp = 1, .umasks = bdx_unc_r3_vn1_credits_used, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_r3_vn1_credits_used), }, { .name = "UNC_R3_VNA_CREDITS_ACQUIRED", .code = 0x33, .desc = "Number of QPI VNA Credit acquisitions. This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder. VNA credits are used by all message classes in order to communicate across QPI. If a packet is unable to acquire credits, it will then attempt to use credts from the VN0 pool. Note that a single packet may require multiple flit buffers (i.e. when data is being transfered). Therefore, this event will increment by the number of credits acquired in each cycle. Filtering based on message class is not provided. One can count the number of packets transfered in a given message class using an qfclk event.", .modmsk = BDX_UNC_R3QPI_ATTRS, .cntmsk = 0x3, .ngrp = 1, .umasks = bdx_unc_r3_vna_credits_acquired, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_r3_vna_credits_acquired), }, { .name = "UNC_R3_VNA_CREDITS_REJECT", .code = 0x34, .desc = "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.", .modmsk = BDX_UNC_R3QPI_ATTRS, .cntmsk = 0x3, .ngrp = 1, .umasks = bdx_unc_r3_vna_credits_reject, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_r3_vna_credits_reject), }, }; libpfm-4.9.0/lib/events/intel_ivb_events.h0000664000175000017500000025237613223402656020417 0ustar eranianeranian/* * Copyright (c) 2012 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * This file has been automatically generated. * * PMU: ivb (Intel Ivy Bridge) * PMU: ivb_ep (Intel Ivy Bridge EP) */ static const intel_x86_umask_t ivb_arith[]={ { .uname = "FPU_DIV_ACTIVE", .udesc = "Cycles that the divider is active, includes integer and floating point", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "FPU_DIV", .udesc = "Number of cycles the divider is activated, includes integer and floating point", .ucode = 0x400 | INTEL_X86_MOD_EDGE | (1 << INTEL_X86_CMASK_BIT), .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_E | _INTEL_X86_ATTR_C, }, }; static const intel_x86_umask_t ivb_br_inst_exec[]={ { .uname = "NONTAKEN_COND", .udesc = "All macro conditional non-taken branch instructions", .ucode = 0x4100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "TAKEN_COND", .udesc = "All macro conditional taken branch instructions", .ucode = 0x8100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "TAKEN_DIRECT_JUMP", .udesc = "All macro unconditional taken branch instructions, excluding calls and indirects", .ucode = 0x8200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "TAKEN_INDIRECT_JUMP_NON_CALL_RET", .udesc = "All taken indirect branches that are not calls nor returns", .ucode = 0x8400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "TAKEN_NEAR_RETURN", .udesc = "All taken indirect branches that have a return mnemonic", .ucode = 0x8800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "TAKEN_DIRECT_NEAR_CALL", .udesc = "All taken non-indirect calls", .ucode = 0x9000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "TAKEN_INDIRECT_NEAR_CALL", .udesc = "All taken indirect calls, including both register and memory indirect", .ucode = 0xa000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ALL_BRANCHES", .udesc = "All near executed branches instructions (not necessarily retired)", .ucode = 0xff00, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "ALL_COND", .udesc = "All macro conditional branch instructions", .ucode = 0xc100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ANY_COND", .udesc = "All macro conditional branch instructions", .ucode = 0xc100, .uequiv = "ALL_COND", .uflags= INTEL_X86_NCOMBO, }, { .uname = "ANY_INDIRECT_JUMP_NON_CALL_RET", .udesc = "All indirect branches that are not calls nor returns", .ucode = 0xc400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ANY_DIRECT_NEAR_CALL", .udesc = "All non-indirect calls", .ucode = 0xd000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ANY_DIRECT_JUMP", .udesc = "All direct jumps", .ucode = 0xc200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ANY_INDIRECT_NEAR_RET", .udesc = "All indirect near returns", .ucode = 0xc800, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t ivb_br_inst_retired[]={ { .uname = "ALL_BRANCHES", .udesc = "All taken and not taken macro branches including far branches (Precise Event)", .ucode = 0x0000, /* architectural encoding */ .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS | INTEL_X86_DFL, }, { .uname = "COND", .udesc = "All taken and not taken macro conditional branch instructions (Precise Event)", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "FAR_BRANCH", .udesc = "Number of far branch instructions retired (Precise Event)", .ucode = 0x4000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "NEAR_CALL", .udesc = "All macro direct and indirect near calls, does not count far calls (Precise Event)", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "NEAR_RETURN", .udesc = "Number of near ret instructions retired (Precise Event)", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "NEAR_TAKEN", .udesc = "Number of near branch taken instructions retired (Precise Event)", .ucode = 0x2000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "NOT_TAKEN", .udesc = "All not taken macro branch instructions retired (Precise Event)", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, }; static const intel_x86_umask_t ivb_br_misp_exec[]={ { .uname = "NONTAKEN_COND", .udesc = "All non-taken mispredicted macro conditional branch instructions", .ucode = 0x4100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "TAKEN_COND", .udesc = "All taken mispredicted macro conditional branch instructions", .ucode = 0x8100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "TAKEN_INDIRECT_JUMP_NON_CALL_RET", .udesc = "All taken mispredicted indirect branches that are not calls nor returns", .ucode = 0x8400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "TAKEN_NEAR_RETURN", .udesc = "All taken mispredicted indirect branches that have a return mnemonic", .ucode = 0x8800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "TAKEN_RETURN_NEAR", .udesc = "All taken mispredicted indirect branches that have a return mnemonic", .ucode = 0x8800, .uequiv ="TAKEN_NEAR_RETURN", .uflags= INTEL_X86_NCOMBO, }, { .uname = "TAKEN_INDIRECT_NEAR_CALL", .udesc = "All taken mispredicted indirect calls, including both register and memory indirect", .ucode = 0xa000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ANY_COND", .udesc = "All mispredicted macro conditional branch instructions", .ucode = 0xc100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ANY_INDIRECT_JUMP_NON_CALL_RET", .udesc = "All mispredicted indirect branches that are not calls nor returns", .ucode = 0xc400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ALL_BRANCHES", .udesc = "All mispredicted branch instructions", .ucode = 0xff00, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t ivb_br_misp_retired[]={ { .uname = "ALL_BRANCHES", .udesc = "All mispredicted macro branches (Precise Event)", .ucode = 0x0000, /* architectural encoding */ .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS | INTEL_X86_DFL, }, { .uname = "COND", .udesc = "All mispredicted macro conditional branch instructions (Precise Event)", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "CONDITIONAL", .udesc = "All mispredicted macro conditional branch instructions (Precise Event)", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, .uequiv = "COND", }, { .uname = "NEAR_TAKEN", .udesc = "Number of branch instructions retired that were mispredicted and taken (Precise Event)", .ucode = 0x2000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, }; static const intel_x86_umask_t ivb_lock_cycles[]={ { .uname = "SPLIT_LOCK_UC_LOCK_DURATION", .udesc = "Cycles in which the L1D and L2 are locked, due to a UC lock or split lock", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "CACHE_LOCK_DURATION", .udesc = "Cycles in which the L1D is locked", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t ivb_cpl_cycles[]={ { .uname = "RING0", .udesc = "Unhalted core cycles the thread was in ring 0", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "RING0_TRANS", .udesc = "Transitions from rings 1, 2, or 3 to ring 0", .uequiv = "RING0:c=1:e=1", .ucode = 0x100 | INTEL_X86_MOD_EDGE | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, }, { .uname = "RING123", .udesc = "Unhalted core cycles the thread was in rings 1, 2, or 3", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t ivb_cpu_clk_unhalted[]={ { .uname = "REF_P", .udesc = "Cycles when the core is unhalted (count at 100 Mhz)", .ucode = 0x100, .uequiv = "REF_XCLK", .uflags= INTEL_X86_NCOMBO, }, { .uname = "REF_XCLK", .udesc = "Count Xclk pulses (100Mhz) when the core is unhalted", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "REF_XCLK_ANY", .udesc = "Count Xclk pulses (100Mhz) when the at least one thread on the physical core is unhalted", .ucode = 0x100 | INTEL_X86_MOD_ANY, /* any=1 */ .uequiv = "REF_XCLK:t", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_T, }, { .uname = "THREAD_P", .udesc = "Cycles when thread is not halted", .ucode = 0x0, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "ONE_THREAD_ACTIVE", .udesc = "Counts Xclk (100Mhz) pulses when this thread is unhalted and the other thread is halted", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t ivb_dsb2mite_switches[]={ { .uname = "COUNT", .udesc = "Number of DSB to MITE switches", .ucode = 0x0100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PENALTY_CYCLES", .udesc = "Number of DSB to MITE switch true penalty cycles", .ucode = 0x0200, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t ivb_dsb_fill[]={ { .uname = "EXCEED_DSB_LINES", .udesc = "DSB Fill encountered > 3 DSB lines", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t ivb_dtlb_load_misses[]={ { .uname = "MISS_CAUSES_A_WALK", .udesc = "Demand load miss in all TLB levels which causes a page walk of any page size", .ucode = 0x8100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "WALK_COMPLETED", .udesc = "Demand load miss in all TLB levels which causes a page walk that completes for any page size", .ucode = 0x8200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "WALK_DURATION", .udesc = "Cycles PMH is busy with a walk due to demand loads", .ucode = 0x8400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DEMAND_LD_MISS_CAUSES_A_WALK", .udesc = "Demand load miss in all TLB levels which causes a page walk of any page size", .ucode = 0x8100, .uequiv = "MISS_CAUSES_A_WALK", .uflags = INTEL_X86_NCOMBO, }, { .uname = "DEMAND_LD_WALK_COMPLETED", .udesc = "Demand load miss in all TLB levels which causes a page walk that completes for any page size", .ucode = 0x8200, .uequiv = "WALK_COMPLETED", .uflags = INTEL_X86_NCOMBO, }, { .uname = "DEMAND_LD_WALK_DURATION", .udesc = "Cycles PMH is busy with a walk due to demand loads", .ucode = 0x8400, .uequiv = "WALK_DURATION", .uflags = INTEL_X86_NCOMBO, }, { .uname = "STLB_HIT", .udesc = "Number of load operations that missed L1TLB but hit L2TLB", .ucode = 0x45f, /* override event code */ .uflags= INTEL_X86_NCOMBO | INTEL_X86_CODE_OVERRIDE, }, { .uname = "LARGE_WALK_COMPLETED", .udesc = "Number of large page walks completed for demand loads", .ucode = 0x8800, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t ivb_itlb_misses[]={ { .uname = "MISS_CAUSES_A_WALK", .udesc = "Miss in all TLB levels that causes a page walk of any page size (4K/2M/4M/1G)", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "CAUSES_A_WALK", .udesc = "Miss in all TLB levels that causes a page walk of any page size (4K/2M/4M/1G)", .ucode = 0x100, .uequiv = "MISS_CAUSES_A_WALK", .uflags= INTEL_X86_NCOMBO, }, { .uname = "STLB_HIT", .udesc = "First level miss but second level hit; no page walk. Only relevant if multiple levels", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "WALK_COMPLETED", .udesc = "Miss in all TLB levels that causes a page walk that completes of any page size (4K/2M/4M/1G)", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "WALK_DURATION", .udesc = "Cycles PMH is busy with this walk", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "LARGE_PAGE_WALK_COMPLETED", .udesc = "Number of completed page walks in ITLB due to STLB load misses for large pages", .ucode = 0x8000, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t ivb_dtlb_store_misses[]={ { .uname = "MISS_CAUSES_A_WALK", .udesc = "Miss in all TLB levels that causes a page walk of any page size (4K/2M/4M/1G)", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "CAUSES_A_WALK", .udesc = "Miss in all TLB levels that causes a page walk of any page size (4K/2M/4M/1G)", .ucode = 0x100, .uequiv = "MISS_CAUSES_A_WALK", .uflags= INTEL_X86_NCOMBO, }, { .uname = "STLB_HIT", .udesc = "First level miss but second level hit; no page walk. Only relevant if multiple levels", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "WALK_COMPLETED", .udesc = "Miss in all TLB levels that causes a page walk that completes of any page size (4K/2M/4M/1G)", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "WALK_DURATION", .udesc = "Cycles PMH is busy with this walk", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t ivb_fp_assist[]={ { .uname = "ANY", .udesc = "Cycles with any input/output SSE or FP assists", .ucode = 0x1e00 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */ .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "SIMD_INPUT", .udesc = "Number of SIMD FP assists due to input values", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "SIMD_OUTPUT", .udesc = "Number of SIMD FP assists due to output values", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "X87_INPUT", .udesc = "Number of X87 assists due to input value", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "X87_OUTPUT", .udesc = "Number of X87 assists due to output value", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t ivb_icache[]={ { .uname = "MISSES", .udesc = "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes UC accesses", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "IFETCH_STALL", .udesc = "Number of cycles wher a code-fetch stalled due to L1 instruction cache miss or iTLB miss", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "HIT", .udesc = "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. Includes cacheable and uncacheable accesses and uncacheable fetches", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t ivb_idq[]={ { .uname = "EMPTY", .udesc = "Cycles IDQ is empty", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "MITE_UOPS", .udesc = "Number of uops delivered to IDQ from MITE path", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DSB_UOPS", .udesc = "Number of uops delivered to IDQ from DSB path", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "MS_DSB_UOPS", .udesc = "Number of uops delivered to IDQ when MS busy by DSB", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "MS_MITE_UOPS", .udesc = "Number of uops delivered to IDQ when MS busy by MITE", .ucode = 0x2000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "MS_UOPS", .udesc = "Number of uops were delivered to IDQ from MS by either DSB or MITE", .ucode = 0x3000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "MITE_UOPS_CYCLES", .udesc = "Cycles where uops are delivered to IDQ from MITE (MITE active)", .uequiv = "MITE_UOPS:c=1", .ucode = 0x400 | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, }, { .uname = "DSB_UOPS_CYCLES", .udesc = "Cycles where uops are delivered to IDQ from DSB (DSB active)", .ucode = 0x800 | (0x1 << INTEL_X86_CMASK_BIT), .modhw = _INTEL_X86_ATTR_C, .uflags= INTEL_X86_NCOMBO, }, { .uname = "MS_DSB_UOPS_CYCLES", .udesc = "Cycles where uops delivered to IDQ when MS busy by DSB", .uequiv = "MS_DSB_UOPS:c=1", .ucode = 0x1000 | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, }, { .uname = "MS_MITE_UOPS_CYCLES", .udesc = "Cycles where uops delivered to IDQ when MS busy by MITE", .uequiv = "MS_MITE_UOPS:c=1", .ucode = 0x2000 | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, }, { .uname = "MS_UOPS_CYCLES", .udesc = "Cycles where uops delivered to IDQ from MS by either BSD or MITE", .uequiv = "MS_UOPS:c=1", .ucode = 0x3000 | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, }, { .uname = "MS_SWITCHES", .udesc = "Number of cycles that Uops were delivered into Instruction Decode Queue (IDQ) when MS_Busy, initiated by Decode Stream Buffer (DSB) or MITE", .ucode = 0x3000 | INTEL_X86_MOD_EDGE | (1 << INTEL_X86_CMASK_BIT), /* edge=1 cnt=1 */ .uequiv = "MS_UOPS:c=1:e", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_E | _INTEL_X86_ATTR_C, }, { .uname = "ALL_DSB_UOPS", .udesc = "Number of uops delivered from either DSB paths", .ucode = 0x1800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ALL_DSB_CYCLES", .udesc = "Cycles MITE/MS delivered anything", .ucode = 0x1800 | (0x1 << INTEL_X86_CMASK_BIT), .modhw = _INTEL_X86_ATTR_C, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ALL_DSB_CYCLES_4_UOPS", .udesc = "Cycles MITE/MS delivered 4 uops", .ucode = 0x1800 | (0x4 << INTEL_X86_CMASK_BIT), .modhw = _INTEL_X86_ATTR_C, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ALL_MITE_UOPS", .udesc = "Number of uops delivered from either MITE paths", .ucode = 0x2400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ALL_MITE_CYCLES", .udesc = "Cycles DSB/MS delivered anything", .ucode = 0x2400 | (0x1 << INTEL_X86_CMASK_BIT), .modhw = _INTEL_X86_ATTR_C, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ALL_MITE_CYCLES_4_UOPS", .udesc = "Cycles MITE is delivering 4 uops", .ucode = 0x2400 | (0x4 << INTEL_X86_CMASK_BIT), .modhw = _INTEL_X86_ATTR_C, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ANY_UOPS", .udesc = "Number of uops delivered to IDQ from any path", .ucode = 0x3c00, .uflags= INTEL_X86_NCOMBO, }, { .uname = "MS_DSB_UOPS_OCCUR", .udesc = "Occurrences of DSB MS going active", .uequiv = "MS_DSB_UOPS:c=1:e=1", .ucode = 0x1000 | INTEL_X86_MOD_EDGE | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t ivb_idq_uops_not_delivered[]={ { .uname = "CORE", .udesc = "Number of non-delivered uops to RAT (use cmask to qualify further)", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "CYCLES_0_UOPS_DELIV_CORE", .udesc = "Cycles per thread when 4 or more uops are not delivered to the Resource Allocation Table (RAT) when backend is not stalled", .ucode = 0x100 | (4 << INTEL_X86_CMASK_BIT), /* cnt=4 */ .uflags = INTEL_X86_NCOMBO, .uequiv = "CORE:c=4", .modhw = _INTEL_X86_ATTR_C, }, { .uname = "CYCLES_LE_1_UOP_DELIV_CORE", .udesc = "Cycles per thread when 3 or more uops are not delivered to the Resource Allocation Table (RAT) when backend is not stalled", .ucode = 0x100 | (3 << INTEL_X86_CMASK_BIT), /* cnt=3 */ .uequiv = "CORE:c=3", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "CYCLES_LE_2_UOP_DELIV_CORE", .udesc = "Cycles with less than 2 uops delivered by the front end", .ucode = 0x100 | (2 << INTEL_X86_CMASK_BIT), /* cnt=2 */ .uequiv = "CORE:c=2", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "CYCLES_LE_3_UOP_DELIV_CORE", .udesc = "Cycles with less than 3 uops delivered by the front end", .ucode = 0x100 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */ .uequiv = "CORE:c=1", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "CYCLES_FE_WAS_OK", .udesc = "Cycles Front-End (FE) delivered 4 uops or Resource Allocation Table (RAT) was stalling FE", .ucode = 0x100 | INTEL_X86_MOD_INV | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 inv=1 */ .uequiv = "CORE:c=1:i", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C | _INTEL_X86_ATTR_I, }, }; static const intel_x86_umask_t ivb_ild_stall[]={ { .uname = "LCP", .udesc = "Stall caused by changing prefix length of the instruction", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "IQ_FULL", .udesc = "Stall cycles due to IQ full", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t ivb_inst_retired[]={ { .uname = "ANY_P", .udesc = "Number of instructions retired", .ucode = 0x0, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "ALL", .udesc = "Precise instruction retired event to reduce effect of PEBS shadow IP distribution (Precise Event)", .ucntmsk = 0x2, .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "PREC_DIST", .udesc = "Precise instruction retired event to reduce effect of PEBS shadow IP distribution (Precise Event)", .ucntmsk = 0x2, .uequiv = "ALL", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, }; static const intel_x86_umask_t ivb_itlb[]={ { .uname = "ITLB_FLUSH", .udesc = "Number of ITLB flushes, includes 4k/2M/4M pages", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "FLUSH", .udesc = "Number of ITLB flushes, includes 4k/2M/4M pages", .ucode = 0x100, .uequiv = "ITLB_FLUSH", .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t ivb_l1d[]={ { .uname = "REPLACEMENT", .udesc = "Number of cache lines brought into the L1D cache", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t ivb_move_elimination[]={ { .uname = "INT_NOT_ELIMINATED", .udesc = "Number of integer Move Elimination candidate uops that were not eliminated", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "SIMD_NOT_ELIMINATED", .udesc = "Number of SIMD Move Elimination candidate uops that were not eliminated", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "INT_ELIMINATED", .udesc = "Number of integer Move Elimination candidate uops that were eliminated", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "SIMD_ELIMINATED", .udesc = "Number of SIMD Move Elimination candidate uops that were eliminated", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t ivb_l1d_pend_miss[]={ { .uname = "OCCURRENCES", .udesc = "Occurrences of L1D_PEND_MISS going active", .uequiv = "PENDING:e=1:c=1", .ucode = 0x100 | INTEL_X86_MOD_EDGE | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, }, { .uname = "EDGE", .udesc = "Occurrences of L1D_PEND_MISS going active", .uequiv = "OCCURRENCES", .ucode = 0x100 | INTEL_X86_MOD_EDGE | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, }, { .uname = "PENDING", .udesc = "Number of L1D load misses outstanding every cycle", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PENDING_CYCLES", .udesc = "Cycles with L1D load misses outstanding", .uequiv = "PENDING:c=1", .ucode = 0x100 | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, }, { .uname = "PENDING_CYCLES_ANY", .udesc = "Cycles with L1D load misses outstanding from any thread on the physical core", .uequiv = "PENDING:c=1:t", .ucode = 0x100 | (0x1 << INTEL_X86_CMASK_BIT) | INTEL_X86_MOD_ANY, .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C | _INTEL_X86_ATTR_T, }, { .uname = "FB_FULL", .udesc = "Number of cycles a demand request was blocked due to Fill Buffer (FB) unavailability", .ucode = 0x200 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */ .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, }; static const intel_x86_umask_t ivb_l2_l1d_wb_rqsts[]={ { .uname = "HIT_E", .udesc = "Non rejected writebacks from L1D to L2 cache lines in E state", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "HIT_M", .udesc = "Non rejected writebacks from L1D to L2 cache lines in M state", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "MISS", .udesc = "Not rejected writebacks that missed LLC", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ALL", .udesc = "Not rejected writebacks from L1D to L2 cache lines in any state", .ucode = 0xf00, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t ivb_l2_lines_in[]={ { .uname = "ANY", .udesc = "L2 cache lines filling (counting does not cover rejects)", .ucode = 0x700, .uequiv = "ALL", .uflags= INTEL_X86_NCOMBO, }, { .uname = "ALL", .udesc = "L2 cache lines filling (counting does not cover rejects)", .ucode = 0x700, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "E", .udesc = "L2 cache lines in E state (counting does not cover rejects)", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "I", .udesc = "L2 cache lines in I state (counting does not cover rejects)", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "S", .udesc = "L2 cache lines in S state (counting does not cover rejects)", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t ivb_l2_lines_out[]={ { .uname = "DEMAND_CLEAN", .udesc = "L2 clean line evicted by a demand", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DEMAND_DIRTY", .udesc = "L2 dirty line evicted by a demand", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PREFETCH_CLEAN", .udesc = "L2 clean line evicted by a prefetch", .ucode = 0x400, .uequiv = "PF_CLEAN", .uflags= INTEL_X86_NCOMBO, }, { .uname = "PF_CLEAN", .udesc = "L2 clean line evicted by a prefetch", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PREFETCH_DIRTY", .udesc = "L2 dirty line evicted by an MLC Prefetch", .ucode = 0x800, .uequiv = "PF_DIRTY", .uflags= INTEL_X86_NCOMBO, }, { .uname = "PF_DIRTY", .udesc = "L2 dirty line evicted by an MLC Prefetch", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DIRTY_ANY", .udesc = "Any L2 dirty line evicted (does not cover rejects)", .ucode = 0xa00, .uequiv = "DIRTY_ALL", .uflags= INTEL_X86_NCOMBO, }, { .uname = "DIRTY_ALL", .udesc = "Any L2 dirty line evicted (does not cover rejects)", .ucode = 0xa00, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t ivb_l2_rqsts[]={ { .uname = "ALL_CODE_RD", .udesc = "Any code request to L2 cache", .ucode = 0x3000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "CODE_RD_HIT", .udesc = "L2 cache hits when fetching instructions", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "CODE_RD_MISS", .udesc = "L2 cache misses when fetching instructions", .ucode = 0x2000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ALL_DEMAND_DATA_RD", .udesc = "Demand data read requests to L2 cache", .ucode = 0x300, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DEMAND_DATA_RD_HIT", .udesc = "Demand data read requests that hit L2", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ALL_PF", .udesc = "Any L2 HW prefetch request to L2 cache", .ucode = 0xc000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PF_HIT", .udesc = "Requests from the L2 hardware prefetchers that hit L2 cache", .ucode = 0x4000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PF_MISS", .udesc = "Requests from the L2 hardware prefetchers that miss L2 cache", .ucode = 0x8000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ALL_RFO", .udesc = "Any RFO requests to L2 cache", .ucode = 0xc00, .uflags= INTEL_X86_NCOMBO, }, { .uname = "RFO_HIT", .udesc = "Store RFO requests that hit L2 cache", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "RFO_MISS", .udesc = "RFO requests that miss L2 cache", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t ivb_l2_store_lock_rqsts[]={ { .uname = "MISS", .udesc = "RFOs that miss cache (I state)", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "HIT_M", .udesc = "RFOs that hit cache lines in M state", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ALL", .udesc = "RFOs that access cache lines in any state", .ucode = 0xf00, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t ivb_l2_trans[]={ { .uname = "ALL", .udesc = "Transactions accessing the L2 pipe", .ucode = 0x8000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "CODE_RD", .udesc = "L2 cache accesses when fetching instructions", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "L1D_WB", .udesc = "L1D writebacks that access the L2 cache", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DMND_DATA_RD", .udesc = "Demand Data Read requests that access the L2 cache", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "L2_FILL", .udesc = "L2 fill requests that access the L2 cache", .ucode = 0x2000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "L2_WB", .udesc = "L2 writebacks that access the L2 cache", .ucode = 0x4000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ALL_PREFETCH", .udesc = "L2 or L3 HW prefetches that access the L2 cache (including rejects)", .ucode = 0x800, .uequiv = "ALL_PF", .uflags= INTEL_X86_NCOMBO, }, { .uname = "ALL_PF", .udesc = "L2 or L3 HW prefetches that access the L2 cache (including rejects)", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "RFO", .udesc = "RFO requests that access the L2 cache", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t ivb_ld_blocks[]={ { .uname = "STORE_FORWARD", .udesc = "Loads blocked by overlapping with store buffer that cannot be forwarded", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "NO_SR", .udesc = "Number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t ivb_ld_blocks_partial[]={ { .uname = "ADDRESS_ALIAS", .udesc = "False dependencies in MOB due to partial compare on address", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t ivb_load_hit_pre[]={ { .uname = "HW_PF", .udesc = "Non sw-prefetch load dispatches that hit the fill buffer allocated for HW prefetch", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "SW_PF", .udesc = "Non sw-prefetch load dispatches that hit the fill buffer allocated for SW prefetch", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t ivb_l3_lat_cache[]={ { .uname = "MISS", .udesc = "Core-originated cacheable demand requests missed L3", .ucode = 0x4100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "REFERENCE", .udesc = "Core-originated cacheable demand requests that refer to L3", .ucode = 0x4f00, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t ivb_machine_clears[]={ { .uname = "MASKMOV", .udesc = "The number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0", .ucode = 0x2000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "MEMORY_ORDERING", .udesc = "Number of Memory Ordering Machine Clears detected", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "SMC", .udesc = "Self-Modifying Code detected", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "COUNT", .udesc = "Number of machine clears (nukes) of any type", .ucode = 0x100 | INTEL_X86_MOD_EDGE | (1 << INTEL_X86_CMASK_BIT), /* edge=1 cnt=1 */ .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_E | _INTEL_X86_ATTR_C, }, }; static const intel_x86_umask_t ivb_mem_load_uops_llc_hit_retired[]={ { .uname = "XSNP_HIT", .udesc = "Load LLC Hit and a cross-core Snoop hits in on-pkg core cache (Precise Event)", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "XSNP_HITM", .udesc = "Load had HitM Response from a core on same socket (shared LLC) (Precise Event)", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "XSNP_MISS", .udesc = "Load LLC Hit and a cross-core Snoop missed in on-pkg core cache (Precise Event)", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "XSNP_NONE", .udesc = "Load hit in last-level (L3) cache with no snoop needed (Precise Event)", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, }; static const intel_x86_umask_t ivb_mem_load_uops_llc_miss_retired[]={ { .uname = "LOCAL_DRAM", .udesc = "Number of retired load uops that missed L3 but were service by local RAM. Does not count hardware prefetches (Precise Event)", .ucode = 0x100, .uflags = INTEL_X86_DFL | INTEL_X86_PEBS, }, { .uname = "REMOTE_DRAM", .udesc = "Number of retired load uops that missed L3 but were service by remote RAM, snoop not needed, snoop miss, snoop hit data not forwarded (Precise Event)", .ucode = 0xc00, .umodel = PFM_PMU_INTEL_IVB_EP, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "REMOTE_HITM", .udesc = "Number of retired load uops whose data sources was remote HITM (Precise Event)", .ucode = 0x1000, .umodel = PFM_PMU_INTEL_IVB_EP, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "REMOTE_FWD", .udesc = "Load uops that miss in the L3 whose data source was forwarded from a remote cache (Precise Event)", .ucode = 0x2000, .umodel = PFM_PMU_INTEL_IVB_EP, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, }; static const intel_x86_umask_t ivb_mem_load_uops_retired[]={ { .uname = "HIT_LFB", .udesc = "A load missed L1D but hit the Fill Buffer (Precise Event)", .ucode = 0x4000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "L1_MISS", .udesc = "Load miss in nearest-level (L1D) cache (Precise Event)", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "L1_HIT", .udesc = "Load hit in nearest-level (L1D) cache (Precise Event)", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "L2_HIT", .udesc = "Load hit in mid-level (L2) cache (Precise Event)", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "L2_MISS", .udesc = "Load misses in mid-level (L2) cache (Precise Event)", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "L3_HIT", .udesc = "Load hit in last-level (L3) cache with no snoop needed (Precise Event)", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "L3_MISS", .udesc = "Load miss in last-level (L3) cache (Precise Event)", .ucode = 0x2000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, }; static const intel_x86_umask_t ivb_mem_trans_retired[]={ { .uname = "LATENCY_ABOVE_THRESHOLD", .udesc = "Memory load instructions retired above programmed clocks, minimum threshold value is 3 (Precise Event and ldlat required)", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS | INTEL_X86_LDLAT, }, { .uname = "PRECISE_STORE", .udesc = "Capture where stores occur, must use with PEBS (Precise Event required)", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, }; static const intel_x86_umask_t ivb_mem_uops_retired[]={ { .uname = "ALL_LOADS", .udesc = "Any retired loads (Precise Event)", .ucode = 0x8100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "ANY_LOADS", .udesc = "Any retired loads (Precise Event)", .ucode = 0x8100, .uequiv = "ALL_LOADS", .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "ALL_STORES", .udesc = "Any retired stores (Precise Event)", .ucode = 0x8200, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "LOCK_LOADS", .udesc = "Locked retired loads (Precise Event)", .ucode = 0x2100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "ANY_STORES", .udesc = "Any retired stores (Precise Event)", .ucode = 0x8200, .uequiv = "ALL_STORES", .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "SPLIT_LOADS", .udesc = "Retired loads causing cacheline splits (Precise Event)", .ucode = 0x4100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "SPLIT_STORES", .udesc = "Retired stores causing cacheline splits (Precise Event)", .ucode = 0x4200, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "STLB_MISS_LOADS", .udesc = "STLB misses dues to retired loads (Precise Event)", .ucode = 0x1100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "STLB_MISS_STORES", .udesc = "STLB misses dues to retired stores (Precise Event)", .ucode = 0x1200, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, }; static const intel_x86_umask_t ivb_misalign_mem_ref[]={ { .uname = "LOADS", .udesc = "Speculative cache-line split load uops dispatched to the L1D", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "STORES", .udesc = "Speculative cache-line split Store-address uops dispatched to L1D", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t ivb_offcore_requests[]={ { .uname = "ALL_DATA_RD", .udesc = "Demand and prefetch read requests sent to uncore", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ALL_DATA_READ", .udesc = "Demand and prefetch read requests sent to uncore", .uequiv = "ALL_DATA_RD", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DEMAND_CODE_RD", .udesc = "Offcore code read requests, including cacheable and un-cacheables", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DEMAND_DATA_RD", .udesc = "Demand Data Read requests sent to uncore", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DEMAND_RFO", .udesc = "Offcore Demand RFOs, includes regular RFO, Locks, ItoM", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t ivb_offcore_requests_outstanding[]={ { .uname = "ALL_DATA_RD_CYCLES", .udesc = "Cycles with cacheable data read transactions in the superQ", .uequiv = "ALL_DATA_RD:c=1", .ucode = 0x800 | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, }, { .uname = "DEMAND_CODE_RD_CYCLES", .udesc = "Cycles with demand code reads transactions in the superQ", .uequiv = "DEMAND_CODE_RD:c=1", .ucode = 0x200 | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, }, { .uname = "DEMAND_DATA_RD_CYCLES", .udesc = "Cycles with demand data read transactions in the superQ", .uequiv = "DEMAND_DATA_RD:c=1", .ucode = 0x100 | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, }, { .uname = "ALL_DATA_RD", .udesc = "Cacheable data read transactions in the superQ every cycle", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DEMAND_CODE_RD", .udesc = "Code read transactions in the superQ every cycle", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DEMAND_DATA_RD", .udesc = "Demand data read transactions in the superQ every cycle", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DEMAND_DATA_RD_GE_6", .udesc = "Cycles with at lesat 6 offcore outstanding demand data read requests in the uncore queue", .uequiv = "DEMAND_DATA_RD:c=6", .ucode = 0x100 | (6 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "DEMAND_RFO", .udesc = "Outstanding RFO (store) transactions in the superQ every cycle", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DEMAND_RFO_CYCLES", .udesc = "Cycles with outstanding RFO (store) transactions in the superQ", .uequiv = "DEMAND_RFO:c=1", .ucode = 0x400 | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t ivb_other_assists[]={ { .uname = "AVX_TO_SSE", .udesc = "Number of transitions from AVX-256 to legacy SSE when penalty applicable", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "SSE_TO_AVX", .udesc = "Number of transitions from legacy SSE to AVX-256 when penalty applicable", .ucode = 0x2000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "AVX_STORE", .udesc = "Number of assists associated with 256-bit AVX stores", .ucode = 0x0800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "WB", .udesc = "Number of times the microcode assist is invoked by hardware upon uop writeback", .ucode = 0x8000, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t ivb_resource_stalls[]={ { .uname = "ANY", .udesc = "Cycles stalled due to Resource Related reason", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "RS", .udesc = "Cycles stalled due to no eligible RS entry available", .ucode = 0x400, }, { .uname = "SB", .udesc = "Cycles stalled due to no store buffers available (not including draining from sync)", .ucode = 0x800, }, { .uname = "ROB", .udesc = "Cycles stalled due to re-order buffer full", .ucode = 0x1000, }, }; static const intel_x86_umask_t ivb_rob_misc_events[]={ { .uname = "LBR_INSERTS", .udesc = "Count each time an new LBR record is saved by HW", .ucode = 0x2000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t ivb_rs_events[]={ { .uname = "EMPTY_CYCLES", .udesc = "Cycles the RS is empty for this thread", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "EMPTY_END", .udesc = "Counts number of time the Reservation Station (RS) goes from empty to non-empty", .ucode = 0x100 | INTEL_X86_MOD_INV | INTEL_X86_MOD_EDGE | (1 << INTEL_X86_CMASK_BIT), /* inv=1 edge=1 cnt=1 */ .uequiv = "EMPTY_CYCLES:c=1:e:i", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_E | _INTEL_X86_ATTR_I | _INTEL_X86_ATTR_C, }, }; static const intel_x86_umask_t ivb_tlb_access[]={ { .uname = "STLB_HIT", .udesc = "Number of load operations that missed L1TLB but hit L2TLB", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "LOAD_STLB_HIT", .udesc = "Number of load operations that missed L1TLB but hit L2TLB", .ucode = 0x400, .uequiv= "STLB_HIT", .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t ivb_tlb_flush[]={ { .uname = "DTLB_THREAD", .udesc = "Number of DTLB flushes of thread-specific entries", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "STLB_ANY", .udesc = "Number of STLB flushes", .ucode = 0x2000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t ivb_uops_executed[]={ { .uname = "CORE", .udesc = "Counts total number of uops executed from any thread per cycle", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "THREAD", .udesc = "Counts total number of uops executed per thread each cycle", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "STALL_CYCLES", .udesc = "Number of cycles with no uops executed", .ucode = 0x100 | INTEL_X86_MOD_INV | (1 << INTEL_X86_CMASK_BIT), /* inv=1 cnt=1 */ .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_I | _INTEL_X86_ATTR_C, }, { .uname = "CYCLES_GE_1_UOP_EXEC", .udesc = "Cycles where at least 1 uop was executed per thread", .ucode = 0x100 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */ .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "CYCLES_GE_2_UOPS_EXEC", .udesc = "Cycles where at least 2 uops were executed per thread", .ucode = 0x100 | (2 << INTEL_X86_CMASK_BIT), /* cnt=2 */ .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "CYCLES_GE_3_UOPS_EXEC", .udesc = "Cycles where at least 3 uops were executed per thread", .ucode = 0x100 | (3 << INTEL_X86_CMASK_BIT), /* cnt=3 */ .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "CYCLES_GE_4_UOPS_EXEC", .udesc = "Cycles where at least 4 uops were executed per thread", .ucode = 0x100 | (4 << INTEL_X86_CMASK_BIT), /* cnt=4 */ .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "CORE_CYCLES_GE_1", .udesc = "Cycles where at least 1 uop was executed from any thread", .ucode = 0x200 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */ .uequiv = "CORE:c=1", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "CORE_CYCLES_GE_2", .udesc = "Cycles where at least 2 uops were executed from any thread", .ucode = 0x200 | (2 << INTEL_X86_CMASK_BIT), /* cnt=2 */ .uequiv = "CORE:c=2", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "CORE_CYCLES_GE_3", .udesc = "Cycles where at least 3 uops were executed from any thread", .ucode = 0x200 | (3 << INTEL_X86_CMASK_BIT), /* cnt=3 */ .uequiv = "CORE:c=3", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "CORE_CYCLES_GE_4", .udesc = "Cycles where at least 4 uops were executed from any thread", .ucode = 0x200 | (4 << INTEL_X86_CMASK_BIT), /* cnt=4 */ .uequiv = "CORE:c=4", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "CORE_CYCLES_NONE", .udesc = "Cycles where no uop is executed on any thread", .ucode = 0x200 | INTEL_X86_MOD_INV, /* inv=1 */ .uequiv = "CORE:i", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_I, }, }; static const intel_x86_umask_t ivb_uops_dispatched_port[]={ { .uname = "PORT_0", .udesc = "Cycles in which a uop is dispatched on port 0", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PORT_1", .udesc = "Cycles in which a uop is dispatched on port 1", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PORT_2", .udesc = "Cycles in which a uop is dispatched on port 2", .ucode = 0xc00, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PORT_3", .udesc = "Cycles in which a uop is dispatched on port 3", .ucode = 0x3000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PORT_4", .udesc = "Cycles in which a uop is dispatched on port 4", .ucode = 0x4000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PORT_5", .udesc = "Cycles in which a uop is dispatched on port 5", .ucode = 0x8000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PORT_0_CORE", .udesc = "Cycles in which a uop is dispatched on port 0 for any thread", .ucode = 0x100 | INTEL_X86_MOD_ANY, /* any=1 */ .uequiv = "PORT_0:t", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_T, }, { .uname = "PORT_1_CORE", .udesc = "Cycles in which a uop is dispatched on port 1 for any thread", .ucode = 0x200 | INTEL_X86_MOD_ANY, /* any=1 */ .uequiv = "PORT_1:t", .uflags= INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_T, }, { .uname = "PORT_2_CORE", .udesc = "Cycles in which a uop is dispatched on port 2 for any thread", .ucode = 0xc00 | INTEL_X86_MOD_ANY, /* any=1 */ .uequiv = "PORT_2:t", .uflags= INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_T, }, { .uname = "PORT_3_CORE", .udesc = "Cycles in which a uop is dispatched on port 3 for any thread", .ucode = 0x3000 | INTEL_X86_MOD_ANY, /* any=1 */ .uequiv = "PORT_3:t", .uflags= INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_T, }, { .uname = "PORT_4_CORE", .udesc = "Cycles in which a uop is dispatched on port 4 for any thread", .ucode = 0x4000 | INTEL_X86_MOD_ANY, /* any=1 */ .uequiv = "PORT_4:t", .uflags= INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_T, }, { .uname = "PORT_5_CORE", .udesc = "Cycles in which a uop is dispatched on port 5 for any thread", .ucode = 0x8000 | INTEL_X86_MOD_ANY, /* any=1 */ .uequiv = "PORT_5:t", .uflags= INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_T, }, }; static const intel_x86_umask_t ivb_uops_issued[]={ { .uname = "ANY", .udesc = "Number of uops issued by the RAT to the Reservation Station (RS)", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "CORE_STALL_CYCLES", .udesc = "Cycles no uops issued on this core (by any thread)", .uequiv = "ANY:c=1:i=1:t=1", .ucode = 0x100 | INTEL_X86_MOD_ANY | INTEL_X86_MOD_INV | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, }, { .uname = "STALL_CYCLES", .udesc = "Cycles no uops issued by this thread", .uequiv = "ANY:c=1:i=1", .ucode = 0x100 | INTEL_X86_MOD_INV | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, }, { .uname = "FLAGS_MERGE", .udesc = "Number of flags-merge uops allocated. Such uops adds delay", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "SLOW_LEA", .udesc = "Number of slow LEA or similar uops allocated", .ucode = 0x2000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "SINGLE_MUL", .udesc = "Number of multiply packed/scalar single precision uops allocated", .ucode = 0x4000, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t ivb_uops_retired[]={ { .uname = "ALL", .udesc = "All uops that actually retired (Precise Event)", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS | INTEL_X86_DFL, }, { .uname = "ANY", .udesc = "All uops that actually retired (Precise Event)", .ucode = 0x100, .uequiv= "ALL", .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "RETIRE_SLOTS", .udesc = "Number of retirement slots used (Precise Event)", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "STALL_CYCLES", .udesc = "Cycles no executable uop retired (Precise Event)", .uequiv = "ALL:c=1:i=1", .ucode = 0x100 | INTEL_X86_MOD_INV | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "TOTAL_CYCLES", .udesc = "Total cycles using precise uop retired event (Precise Event)", .ucode = 0x100 | INTEL_X86_MOD_INV | (10 << INTEL_X86_CMASK_BIT), /* inv=1 cnt=10 */ .uequiv = "ALL:c=10:i", .modhw = _INTEL_X86_ATTR_I | _INTEL_X86_ATTR_C, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, }; static const intel_x86_umask_t ivb_offcore_response[]={ { .uname = "DMND_DATA_RD", .udesc = "Request: number of demand and DCU prefetch data reads of full and partial cachelines as well as demand data page table entry cacheline reads. Does not count L2 data read prefetches or instruction fetches", .ucode = 1ULL << (0 + 8), .grpid = 0, }, { .uname = "DMND_RFO", .udesc = "Request: number of demand and DCU prefetch reads for ownership (RFO) requests generated by a write to data cacheline. Does not count L2 RFO prefetches", .ucode = 1ULL << (1 + 8), .grpid = 0, }, { .uname = "DMND_IFETCH", .udesc = "Request: number of demand and DCU prefetch instruction cacheline reads. Does not count L2 code read prefetches", .ucode = 1ULL << (2 + 8), .grpid = 0, }, { .uname = "WB", .udesc = "Request: number of writebacks (modified to exclusive) transactions", .ucode = 1ULL << (3 + 8), .grpid = 0, }, { .uname = "PF_DATA_RD", .udesc = "Request: number of data cacheline reads generated by L2 prefetchers", .ucode = 1ULL << (4 + 8), .grpid = 0, }, { .uname = "PF_RFO", .udesc = "Request: number of RFO requests generated by L2 prefetchers", .ucode = 1ULL << (5 + 8), .grpid = 0, }, { .uname = "PF_IFETCH", .udesc = "Request: number of code reads generated by L2 prefetchers", .ucode = 1ULL << (6 + 8), .grpid = 0, }, { .uname = "PF_LLC_DATA_RD", .udesc = "Request: number of L3 prefetcher requests to L2 for loads", .ucode = 1ULL << (7 + 8), .grpid = 0, }, { .uname = "PF_LLC_RFO", .udesc = "Request: number of RFO requests generated by L2 prefetcher", .ucode = 1ULL << (8 + 8), .grpid = 0, }, { .uname = "PF_LLC_IFETCH", .udesc = "Request: number of L2 prefetcher requests to L3 for instruction fetches", .ucode = 1ULL << (9 + 8), .grpid = 0, }, { .uname = "BUS_LOCKS", .udesc = "Request: number bus lock and split lock requests", .ucode = 1ULL << (10 + 8), .grpid = 0, }, { .uname = "STRM_ST", .udesc = "Request: number of streaming store requests", .ucode = 1ULL << (11 + 8), .grpid = 0, }, { .uname = "OTHER", .udesc = "Request: counts one of the following transaction types, including L3 invalidate, I/O, full or partial writes, WC or non-temporal stores, CLFLUSH, Fences, lock, unlock, split lock", .ucode = 1ULL << (15+8), .grpid = 0, }, { .uname = "ANY_IFETCH", .udesc = "Request: combination of PF_IFETCH | DMND_IFETCH | PF_LLC_IFETCH", .uequiv = "PF_IFETCH:DMND_IFETCH:PF_LLC_IFETCH", .ucode = 0x24400, .grpid = 0, }, { .uname = "ANY_REQUEST", .udesc = "Request: combination of all request umasks", .uequiv = "DMND_DATA_RD:DMND_RFO:DMND_IFETCH:WB:PF_DATA_RD:PF_RFO:PF_IFETCH:PF_LLC_DATA_RD:PF_LLC_RFO:PF_LLC_IFETCH:BUS_LOCKS:STRM_ST:OTHER", .ucode = 0x8fff00, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, .grpid = 0, }, { .uname = "ANY_DATA", .udesc = "Request: combination of DMND_DATA | PF_DATA_RD | PF_LLC_DATA_RD", .uequiv = "DMND_DATA_RD:PF_DATA_RD:PF_LLC_DATA_RD", .ucode = 0x9100, .grpid = 0, }, { .uname = "ANY_RFO", .udesc = "Request: combination of DMND_RFO | PF_RFO | PF_LLC_RFO", .uequiv = "DMND_RFO:PF_RFO:PF_LLC_RFO", .ucode = 0x12200, .grpid = 0, }, { .uname = "ANY_RESPONSE", .udesc = "Response: count any response type", .ucode = 1ULL << (16+8), .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL | INTEL_X86_EXCL_GRP_GT, .grpid = 1, }, { .uname = "NO_SUPP", .udesc = "Supplier: counts number of times supplier information is not available", .ucode = 1ULL << (17+8), .grpid = 1, }, { .uname = "LLC_HITM", .udesc = "Supplier: counts L3 hits in M-state (initial lookup)", .ucode = 1ULL << (18+8), .grpid = 1, }, { .uname = "LLC_HITE", .udesc = "Supplier: counts L3 hits in E-state", .ucode = 1ULL << (19+8), .grpid = 1, }, { .uname = "LLC_HITS", .udesc = "Supplier: counts L3 hits in S-state", .ucode = 1ULL << (20+8), .grpid = 1, }, { .uname = "LLC_HITF", .udesc = "Supplier: counts L3 hits in F-state", .ucode = 1ULL << (21+8), .grpid = 1, }, { .uname = "LLC_MISS_LOCAL", .udesc = "Supplier: counts L3 misses to local DRAM", .ucode = 1ULL << (22+8), .grpid = 1, }, { .uname = "LLC_MISS_REMOTE", .udesc = "Supplier: counts L3 misses to remote DRAM", .ucode = 0xffULL << (23+8), .uequiv = "LLC_MISS_REMOTE_DRAM", .umodel = PFM_PMU_INTEL_IVB_EP, .grpid = 1, }, { .uname = "L3_MISS", .udesc = "Supplier: counts L3 misses to local DRAM", .ucode = 0x1ULL << (22+8), .grpid = 1, .uequiv = "LLC_MISS_LOCAL", .umodel = PFM_PMU_INTEL_IVB, }, { .uname = "L3_MISS", .udesc = "Supplier: counts L3 misses to local or remote DRAM", .ucode = 0x3ULL << (22+8), .uequiv = "LLC_MISS_LOCAL:LLC_MISS_REMOTE", .umodel = PFM_PMU_INTEL_IVB_EP, .grpid = 1, }, { .uname = "LLC_MISS_REMOTE_DRAM", .udesc = "Supplier: counts L3 misses to remote DRAM", .ucode = 0xffULL << (23+8), .umodel = PFM_PMU_INTEL_IVB_EP, .grpid = 1, }, { .uname = "LLC_HITMESF", .udesc = "Supplier: counts L3 hits in any state (M, E, S, F)", .ucode = 0xfULL << (18+8), .uequiv = "LLC_HITM:LLC_HITE:LLC_HITS:LLC_HITF", .grpid = 1, }, { .uname = "SNP_NONE", .udesc = "Snoop: counts number of times no snoop-related information is available", .ucode = 1ULL << (31+8), .grpid = 2, }, { .uname = "SNP_NOT_NEEDED", .udesc = "Snoop: counts the number of times no snoop was needed to satisfy the request", .ucode = 1ULL << (32+8), .grpid = 2, }, { .uname = "SNP_MISS", .udesc = "Snoop: counts number of times a snoop was needed and it missed all snooped caches", .ucode = 1ULL << (33+8), .grpid = 2, }, { .uname = "SNP_NO_FWD", .udesc = "Snoop: counts number of times a snoop was needed and it hit in at leas one snooped cache", .ucode = 1ULL << (34+8), .grpid = 2, }, { .uname = "SNP_FWD", .udesc = "Snoop: counts number of times a snoop was needed and data was forwarded from a remote socket", .ucode = 1ULL << (35+8), .grpid = 2, }, { .uname = "HITM", .udesc = "Snoop: counts number of times a snoop was needed and it hitM-ed in local or remote cache", .ucode = 1ULL << (36+8), .grpid = 2, }, { .uname = "NON_DRAM", .udesc = "Snoop: counts number of times target was a non-DRAM system address. This includes MMIO transactions", .ucode = 1ULL << (37+8), .grpid = 2, }, { .uname = "SNP_ANY", .udesc = "Snoop: any snoop reason", .ucode = 0x7fULL << (31+8), .uequiv = "SNP_NONE:SNP_NOT_NEEDED:SNP_MISS:SNP_NO_FWD:SNP_FWD:HITM:NON_DRAM", .uflags= INTEL_X86_DFL, .grpid = 2, }, }; static const intel_x86_umask_t ivb_baclears[]={ { .uname = "ANY", .udesc = "Counts the number of times the front end is re-steered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end", .ucode = 0x1f00, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t ivb_cycle_activity[]={ { .uname = "CYCLES_L2_PENDING", .udesc = "Cycles with pending L2 miss loads", .ucode = 0x0100 | (0x1 << INTEL_X86_CMASK_BIT), .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, .ucntmsk= 0xf, }, { .uname = "CYCLES_LDM_PENDING", .udesc = "Cycles with pending memory loads", .ucode = 0x0200 | (0x2 << INTEL_X86_CMASK_BIT), .modhw = _INTEL_X86_ATTR_C, .uflags = INTEL_X86_NCOMBO, .ucntmsk= 0xf, }, { .uname = "CYCLES_L1D_PENDING", .udesc = "Cycles with pending L1D load cache misses", .ucode = 0x0800 | (0x8 << INTEL_X86_CMASK_BIT), .ucntmsk= 0x4, .modhw = _INTEL_X86_ATTR_C, .uflags = INTEL_X86_NCOMBO, }, { .uname = "CYCLES_NO_EXECUTE", .udesc = "Cycles of dispatch stalls", .ucode = 0x0400 | (0x4 << INTEL_X86_CMASK_BIT), .modhw = _INTEL_X86_ATTR_C, .ucntmsk= 0xf, .uflags = INTEL_X86_NCOMBO, }, { .uname = "STALLS_L2_PENDING", .udesc = "Execution stalls due to L2 pending loads", .ucode = 0x0500 | (0x5 << INTEL_X86_CMASK_BIT), .ucntmsk= 0xf, .modhw = _INTEL_X86_ATTR_C, .uflags = INTEL_X86_NCOMBO, }, { .uname = "STALLS_L1D_PENDING", .udesc = "Execution stalls due to L1D pending loads", .ucode = 0x0c00 | (0xc << INTEL_X86_CMASK_BIT), .ucntmsk= 0x4, .modhw = _INTEL_X86_ATTR_C, .uflags = INTEL_X86_NCOMBO, }, { .uname = "STALLS_LDM_PENDING", .udesc = "Execution stalls due to memory loads", .ucode = 0x0600 | (0x6 << INTEL_X86_CMASK_BIT), .ucntmsk= 0xf, .modhw = _INTEL_X86_ATTR_C, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t ivb_fp_comp_ops_exe[]={ { .uname = "X87", .udesc = "Number of X87 uops executed", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "SSE_FP_PACKED_DOUBLE", .udesc = "Number of SSE or AVX-128 double precision FP packed uops executed", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "SSE_FP_SCALAR_SINGLE", .udesc = "Number of SSE or AVX-128 single precision FP scalar uops executed", .ucode = 0x2000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "SSE_PACKED_SINGLE", .udesc = "Number of SSE or AVX-128 single precision FP packed uops executed", .ucode = 0x4000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "SSE_SCALAR_DOUBLE", .udesc = "Number of SSE or AVX-128 double precision FP scalar uops executed", .ucode = 0x8000, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t ivb_simd_fp_256[]={ { .uname = "PACKED_SINGLE", .udesc = "Counts 256-bit packed single-precision", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PACKED_DOUBLE", .udesc = "Counts 256-bit packed double-precision", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t ivb_lsd[]={ { .uname = "UOPS", .udesc = "Number of uops delivered by the Loop Stream Detector (LSD)", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "ACTIVE", .udesc = "Cycles with uops delivered by the LSD but which did not come from decoder", .ucode = 0x100 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */ .uequiv = "UOPS:c=1", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "CYCLES_4_UOPS", .udesc = "Cycles with 4 uops delivered by the LSD but which did not come from decoder", .ucode = 0x100 | (4 << INTEL_X86_CMASK_BIT), /* cnt=4 */ .uequiv = "UOPS:c=4", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, }; static const intel_x86_umask_t ivb_int_misc[]={ { .uname = "RECOVERY_CYCLES", .udesc = "Cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...)", .ucode = 0x300 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */ .modhw = _INTEL_X86_ATTR_C, }, { .uname = "RECOVERY_CYCLES_ANY", .udesc = "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke)", .ucode = 0x300 | (1 << INTEL_X86_CMASK_BIT) | INTEL_X86_MOD_ANY, /* cnt=1 any=1 */ .uequiv = "RECOVERY_CYCLES:t", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C | _INTEL_X86_ATTR_T, }, { .uname = "RECOVERY_STALLS_COUNT", .udesc = "Number of occurrences waiting for Machine Clears", .ucode = 0x300 | INTEL_X86_MOD_EDGE | (1 << INTEL_X86_CMASK_BIT), /* edge=1 cnt=1 */ .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_E | _INTEL_X86_ATTR_C, }, }; static const intel_x86_umask_t ivb_ept[]={ { .uname = "WALK_CYCLES", .udesc = "Cycles for an extended page table walk", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t ivb_page_walks[]={ { .uname = "LLC_MISS", .udesc = "Number of page walks with a LLC miss", .ucode = 0x100, .uflags= INTEL_X86_DFL, }, }; static const intel_x86_umask_t ivb_offcore_requests_buffer[]={ { .uname = "SQ_FULL", .udesc = "Number of cycles the offcore requests buffer is full", .ucode = 0x0100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t ivb_sq_misc[]={ { .uname = "SPLIT_LOCK", .udesc = "Number of split locks in the super queue (SQ)", .ucode = 0x1000, .uflags = INTEL_X86_DFL, }, }; static const intel_x86_entry_t intel_ivb_pe[]={ { .name = "ARITH", .desc = "Counts arithmetic multiply operations", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0x14, .numasks = LIBPFM_ARRAY_SIZE(ivb_arith), .ngrp = 1, .umasks = ivb_arith, }, { .name = "BACLEARS", .desc = "Branch re-steered", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xe6, .numasks = LIBPFM_ARRAY_SIZE(ivb_baclears), .ngrp = 1, .umasks = ivb_baclears, }, { .name = "BR_INST_EXEC", .desc = "Branch instructions executed", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0x88, .numasks = LIBPFM_ARRAY_SIZE(ivb_br_inst_exec), .ngrp = 1, .umasks = ivb_br_inst_exec, }, { .name = "BR_INST_RETIRED", .desc = "Retired branch instructions", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xc4, .flags= INTEL_X86_PEBS, .numasks = LIBPFM_ARRAY_SIZE(ivb_br_inst_retired), .ngrp = 1, .umasks = ivb_br_inst_retired, }, { .name = "BR_MISP_EXEC", .desc = "Mispredicted branches executed", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0x89, .numasks = LIBPFM_ARRAY_SIZE(ivb_br_misp_exec), .ngrp = 1, .umasks = ivb_br_misp_exec, }, { .name = "BR_MISP_RETIRED", .desc = "Mispredicted retired branches", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xc5, .flags= INTEL_X86_PEBS, .numasks = LIBPFM_ARRAY_SIZE(ivb_br_misp_retired), .ngrp = 1, .umasks = ivb_br_misp_retired, }, { .name = "BRANCH_INSTRUCTIONS_RETIRED", .desc = "Count branch instructions at retirement. Specifically, this event counts the retirement of the last micro-op of a branch instruction", .modmsk = INTEL_V3_ATTRS, .equiv = "BR_INST_RETIRED:ALL_BRANCHES", .cntmsk = 0xff, .code = 0xc4, }, { .name = "MISPREDICTED_BRANCH_RETIRED", .desc = "Count mispredicted branch instructions at retirement. Specifically, this event counts at retirement of the last micro-op of a branch instruction in the architectural path of the execution and experienced misprediction in the branch prediction hardware", .modmsk = INTEL_V3_ATTRS, .equiv = "BR_MISP_RETIRED:ALL_BRANCHES", .cntmsk = 0xff, .code = 0xc5, }, { .name = "LOCK_CYCLES", .desc = "Locked cycles in L1D and L2", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0x63, .numasks = LIBPFM_ARRAY_SIZE(ivb_lock_cycles), .ngrp = 1, .umasks = ivb_lock_cycles, }, { .name = "CPL_CYCLES", .desc = "Unhalted core cycles at a specific ring level", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0x5c, .numasks = LIBPFM_ARRAY_SIZE(ivb_cpl_cycles), .ngrp = 1, .umasks = ivb_cpl_cycles, }, { .name = "CPU_CLK_UNHALTED", .desc = "Cycles when processor is not in halted state", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0x3c, .numasks = LIBPFM_ARRAY_SIZE(ivb_cpu_clk_unhalted), .ngrp = 1, .umasks = ivb_cpu_clk_unhalted, }, { .name = "DSB2MITE_SWITCHES", .desc = "Number of DSB to MITE switches", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xab, .numasks = LIBPFM_ARRAY_SIZE(ivb_dsb2mite_switches), .ngrp = 1, .umasks = ivb_dsb2mite_switches, }, { .name = "DSB_FILL", .desc = "DSB fills", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xac, .numasks = LIBPFM_ARRAY_SIZE(ivb_dsb_fill), .ngrp = 1, .umasks = ivb_dsb_fill, }, { .name = "DTLB_LOAD_MISSES", .desc = "Data TLB load misses", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0x8, .numasks = LIBPFM_ARRAY_SIZE(ivb_dtlb_load_misses), .ngrp = 1, .umasks = ivb_dtlb_load_misses, }, { .name = "DTLB_STORE_MISSES", .desc = "Data TLB store misses", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0x49, .numasks = LIBPFM_ARRAY_SIZE(ivb_dtlb_store_misses), .ngrp = 1, .umasks = ivb_dtlb_store_misses, }, { .name = "FP_ASSIST", .desc = "X87 Floating point assists", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xca, .numasks = LIBPFM_ARRAY_SIZE(ivb_fp_assist), .ngrp = 1, .umasks = ivb_fp_assist, }, { .name = "ICACHE", .desc = "Instruction Cache accesses", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0x80, .numasks = LIBPFM_ARRAY_SIZE(ivb_icache), .ngrp = 1, .umasks = ivb_icache, }, { .name = "IDQ", .desc = "IDQ operations", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0x79, .numasks = LIBPFM_ARRAY_SIZE(ivb_idq), .ngrp = 1, .umasks = ivb_idq, }, { .name = "IDQ_UOPS_NOT_DELIVERED", .desc = "Uops not delivered", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0x9c, .numasks = LIBPFM_ARRAY_SIZE(ivb_idq_uops_not_delivered), .ngrp = 1, .umasks = ivb_idq_uops_not_delivered, }, { .name = "ILD_STALL", .desc = "Instruction Length Decoder stalls", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0x87, .numasks = LIBPFM_ARRAY_SIZE(ivb_ild_stall), .ngrp = 1, .umasks = ivb_ild_stall, }, { .name = "INST_RETIRED", .desc = "Instructions retired", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xc0, .flags= INTEL_X86_PEBS, .numasks = LIBPFM_ARRAY_SIZE(ivb_inst_retired), .ngrp = 1, .umasks = ivb_inst_retired, }, { .name = "INSTRUCTION_RETIRED", .desc = "Number of instructions at retirement", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x10000000full, .code = 0xc0, }, { .name = "INSTRUCTIONS_RETIRED", .desc = "This is an alias for INSTRUCTION_RETIRED", .modmsk = INTEL_V3_ATTRS, .equiv = "INSTRUCTION_RETIRED", .cntmsk = 0x10000000full, .code = 0xc0, }, { .name = "ITLB", .desc = "Instruction TLB", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xae, .numasks = LIBPFM_ARRAY_SIZE(ivb_itlb), .ngrp = 1, .umasks = ivb_itlb, }, { .name = "ITLB_MISSES", .desc = "Instruction TLB misses", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0x85, .numasks = LIBPFM_ARRAY_SIZE(ivb_itlb_misses), .ngrp = 1, .umasks = ivb_itlb_misses, }, { .name = "L1D", .desc = "L1D cache", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0x51, .numasks = LIBPFM_ARRAY_SIZE(ivb_l1d), .ngrp = 1, .umasks = ivb_l1d, }, { .name = "MOVE_ELIMINATION", .desc = "Move Elimination", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0x58, .numasks = LIBPFM_ARRAY_SIZE(ivb_move_elimination), .ngrp = 1, .umasks = ivb_move_elimination, }, { .name = "L1D_PEND_MISS", .desc = "L1D pending misses", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x4, .code = 0x48, .numasks = LIBPFM_ARRAY_SIZE(ivb_l1d_pend_miss), .ngrp = 1, .umasks = ivb_l1d_pend_miss, }, { .name = "L2_L1D_WB_RQSTS", .desc = "Writeback requests from L1D to L2", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0x28, .numasks = LIBPFM_ARRAY_SIZE(ivb_l2_l1d_wb_rqsts), .ngrp = 1, .umasks = ivb_l2_l1d_wb_rqsts, }, { .name = "L2_LINES_IN", .desc = "L2 lines allocated", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xf1, .numasks = LIBPFM_ARRAY_SIZE(ivb_l2_lines_in), .ngrp = 1, .umasks = ivb_l2_lines_in, }, { .name = "L2_LINES_OUT", .desc = "L2 lines evicted", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xf2, .numasks = LIBPFM_ARRAY_SIZE(ivb_l2_lines_out), .ngrp = 1, .umasks = ivb_l2_lines_out, }, { .name = "L2_RQSTS", .desc = "L2 requests", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0x24, .numasks = LIBPFM_ARRAY_SIZE(ivb_l2_rqsts), .ngrp = 1, .umasks = ivb_l2_rqsts, }, { .name = "L2_STORE_LOCK_RQSTS", .desc = "L2 store lock requests", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0x27, .numasks = LIBPFM_ARRAY_SIZE(ivb_l2_store_lock_rqsts), .ngrp = 1, .umasks = ivb_l2_store_lock_rqsts, }, { .name = "L2_TRANS", .desc = "L2 transactions", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xf0, .numasks = LIBPFM_ARRAY_SIZE(ivb_l2_trans), .ngrp = 1, .umasks = ivb_l2_trans, }, { .name = "LAST_LEVEL_CACHE_MISSES", .desc = "This is an alias for L3_LAT_CACHE:MISS", .modmsk = INTEL_V3_ATTRS, .equiv = "L3_LAT_CACHE:MISS", .cntmsk = 0xff, .code = 0x412e, }, { .name = "LLC_MISSES", .desc = "Alias for LAST_LEVEL_CACHE_MISSES", .modmsk = INTEL_V3_ATTRS, .equiv = "LAST_LEVEL_CACHE_MISSES", .cntmsk = 0xff, .code = 0x412e, }, { .name = "LAST_LEVEL_CACHE_REFERENCES", .desc = "This is an alias for L3_LAT_CACHE:REFERENCE", .modmsk = INTEL_V3_ATTRS, .equiv = "L3_LAT_CACHE:REFERENCE", .cntmsk = 0xff, .code = 0x4f2e, }, { .name = "LLC_REFERENCES", .desc = "Alias for LAST_LEVEL_CACHE_REFERENCES", .modmsk = INTEL_V3_ATTRS, .equiv = "LAST_LEVEL_CACHE_REFERENCES", .cntmsk = 0xff, .code = 0x4f2e, }, { .name = "LD_BLOCKS", .desc = "Blocking loads", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0x3, .numasks = LIBPFM_ARRAY_SIZE(ivb_ld_blocks), .ngrp = 1, .umasks = ivb_ld_blocks, }, { .name = "LD_BLOCKS_PARTIAL", .desc = "Partial load blocks", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0x7, .numasks = LIBPFM_ARRAY_SIZE(ivb_ld_blocks_partial), .ngrp = 1, .umasks = ivb_ld_blocks_partial, }, { .name = "LOAD_HIT_PRE", .desc = "Load dispatches that hit fill buffer", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0x4c, .numasks = LIBPFM_ARRAY_SIZE(ivb_load_hit_pre), .ngrp = 1, .umasks = ivb_load_hit_pre, }, { .name = "L3_LAT_CACHE", .desc = "Core-originated cacheable demand requests to L3", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0x2e, .numasks = LIBPFM_ARRAY_SIZE(ivb_l3_lat_cache), .ngrp = 1, .umasks = ivb_l3_lat_cache, }, { .name = "LONGEST_LAT_CACHE", .desc = "Core-originated cacheable demand requests to L3", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0x2e, .numasks = LIBPFM_ARRAY_SIZE(ivb_l3_lat_cache), .ngrp = 1, .equiv = "L3_LAT_CACHE", .umasks = ivb_l3_lat_cache, }, { .name = "MACHINE_CLEARS", .desc = "Machine clear asserted", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xc3, .numasks = LIBPFM_ARRAY_SIZE(ivb_machine_clears), .ngrp = 1, .umasks = ivb_machine_clears, }, { .name = "MEM_LOAD_UOPS_LLC_HIT_RETIRED", .desc = "L3 hit loads uops retired", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xd2, .flags= INTEL_X86_PEBS, .numasks = LIBPFM_ARRAY_SIZE(ivb_mem_load_uops_llc_hit_retired), .ngrp = 1, .umasks = ivb_mem_load_uops_llc_hit_retired, }, { .name = "MEM_LOAD_LLC_HIT_RETIRED", .desc = "L3 hit loads uops retired (deprecated use MEM_LOAD_UOPS_LLC_HIT_RETIRED)", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xd2, .equiv = "MEM_LOAD_UOPS_LLC_HIT_RETIRED", .flags= INTEL_X86_PEBS, .numasks = LIBPFM_ARRAY_SIZE(ivb_mem_load_uops_llc_hit_retired), .ngrp = 1, .umasks = ivb_mem_load_uops_llc_hit_retired, }, { .name = "MEM_LOAD_UOPS_LLC_MISS_RETIRED", .desc = "Load uops retired that missed the LLC", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xd3, .flags= INTEL_X86_PEBS, .numasks = LIBPFM_ARRAY_SIZE(ivb_mem_load_uops_llc_miss_retired), .ngrp = 1, .umasks = ivb_mem_load_uops_llc_miss_retired, }, { .name = "MEM_LOAD_UOPS_RETIRED", .desc = "Memory loads uops retired", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xd1, .flags= INTEL_X86_PEBS, .numasks = LIBPFM_ARRAY_SIZE(ivb_mem_load_uops_retired), .ngrp = 1, .umasks = ivb_mem_load_uops_retired, }, { .name = "MEM_LOAD_RETIRED", .desc = "Memory loads uops retired (deprecated use MEM_LOAD_UOPS_RETIRED)", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xd1, .equiv = "MEM_LOAD_UOPS_RETIRED", .flags= INTEL_X86_PEBS, .numasks = LIBPFM_ARRAY_SIZE(ivb_mem_load_uops_retired), .ngrp = 1, .umasks = ivb_mem_load_uops_retired, }, { .name = "MEM_TRANS_RETIRED", .desc = "Memory transactions retired", .modmsk = INTEL_V3_ATTRS | _INTEL_X86_ATTR_LDLAT, .cntmsk = 0x8, .code = 0xcd, .flags= INTEL_X86_PEBS, .numasks = LIBPFM_ARRAY_SIZE(ivb_mem_trans_retired), .ngrp = 1, .umasks = ivb_mem_trans_retired, }, { .name = "MEM_UOPS_RETIRED", .desc = "Memory uops retired", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xd0, .flags= INTEL_X86_PEBS, .numasks = LIBPFM_ARRAY_SIZE(ivb_mem_uops_retired), .ngrp = 1, .umasks = ivb_mem_uops_retired, }, { .name = "MEM_UOP_RETIRED", .desc = "Memory uops retired (deprecated use MEM_UOPS_RETIRED)", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xd0, .equiv = "MEM_UOPS_RETIRED", .flags= INTEL_X86_PEBS, .numasks = LIBPFM_ARRAY_SIZE(ivb_mem_uops_retired), .ngrp = 1, .umasks = ivb_mem_uops_retired, }, { .name = "MISALIGN_MEM_REF", .desc = "Misaligned memory references", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0x5, .numasks = LIBPFM_ARRAY_SIZE(ivb_misalign_mem_ref), .ngrp = 1, .umasks = ivb_misalign_mem_ref, }, { .name = "OFFCORE_REQUESTS", .desc = "Offcore requests", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xb0, .numasks = LIBPFM_ARRAY_SIZE(ivb_offcore_requests), .ngrp = 1, .umasks = ivb_offcore_requests, }, { .name = "OFFCORE_REQUESTS_OUTSTANDING", .desc = "Outstanding offcore requests", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0x60, .numasks = LIBPFM_ARRAY_SIZE(ivb_offcore_requests_outstanding), .ngrp = 1, .umasks = ivb_offcore_requests_outstanding, }, { .name = "OTHER_ASSISTS", .desc = "Count hardware assists", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xc1, .numasks = LIBPFM_ARRAY_SIZE(ivb_other_assists), .ngrp = 1, .umasks = ivb_other_assists, }, { .name = "RESOURCE_STALLS", .desc = "Resource related stall cycles", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xa2, .numasks = LIBPFM_ARRAY_SIZE(ivb_resource_stalls), .ngrp = 1, .umasks = ivb_resource_stalls, }, { .name = "CYCLE_ACTIVITY", .desc = "Stalled cycles", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xa3, .numasks = LIBPFM_ARRAY_SIZE(ivb_cycle_activity), .ngrp = 1, .umasks = ivb_cycle_activity, }, { .name = "ROB_MISC_EVENTS", .desc = "Reorder buffer events", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xcc, .numasks = LIBPFM_ARRAY_SIZE(ivb_rob_misc_events), .ngrp = 1, .umasks = ivb_rob_misc_events, }, { .name = "RS_EVENTS", .desc = "Reservation station events", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0x5e, .numasks = LIBPFM_ARRAY_SIZE(ivb_rs_events), .ngrp = 1, .umasks = ivb_rs_events, }, { .name = "DTLB_LOAD_ACCESS", .desc = "TLB access", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0x5f, .numasks = LIBPFM_ARRAY_SIZE(ivb_tlb_access), .ngrp = 1, .umasks = ivb_tlb_access, }, { .name = "TLB_ACCESS", .desc = "TLB access", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0x5f, .numasks = LIBPFM_ARRAY_SIZE(ivb_tlb_access), .ngrp = 1, .equiv = "DTLB_LOAD_ACCESS", .umasks = ivb_tlb_access, }, { .name = "TLB_FLUSH", .desc = "TLB flushes", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xbd, .numasks = LIBPFM_ARRAY_SIZE(ivb_tlb_flush), .ngrp = 1, .umasks = ivb_tlb_flush, }, { .name = "UNHALTED_CORE_CYCLES", .desc = "Count core clock cycles whenever the clock signal on the specific core is running (not halted)", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x20000000full, .code = 0x3c, }, { .name = "UNHALTED_REFERENCE_CYCLES", .desc = "Unhalted reference cycles", .modmsk = INTEL_FIXED3_ATTRS, .cntmsk = 0x400000000ull, .code = 0x0300, /* pseudo encoding */ .flags = INTEL_X86_FIXED, }, { .name = "UOPS_EXECUTED", .desc = "Uops executed", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xb1, .numasks = LIBPFM_ARRAY_SIZE(ivb_uops_executed), .ngrp = 1, .umasks = ivb_uops_executed, }, { .name = "UOPS_DISPATCHED_PORT", .desc = "Uops dispatch to specific ports", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xa1, .numasks = LIBPFM_ARRAY_SIZE(ivb_uops_dispatched_port), .ngrp = 1, .umasks = ivb_uops_dispatched_port, }, { .name = "UOPS_ISSUED", .desc = "Uops issued", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xe, .numasks = LIBPFM_ARRAY_SIZE(ivb_uops_issued), .ngrp = 1, .umasks = ivb_uops_issued, }, { .name = "UOPS_RETIRED", .desc = "Uops retired", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xc2, .flags= INTEL_X86_PEBS, .numasks = LIBPFM_ARRAY_SIZE(ivb_uops_retired), .ngrp = 1, .umasks = ivb_uops_retired, }, { .name = "FP_COMP_OPS_EXE", .desc = "Counts number of floating point events", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0x10, .numasks = LIBPFM_ARRAY_SIZE(ivb_fp_comp_ops_exe), .ngrp = 1, .umasks = ivb_fp_comp_ops_exe, }, { .name = "SIMD_FP_256", .desc = "Counts 256-bit packed floating point instructions", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0x11, .numasks = LIBPFM_ARRAY_SIZE(ivb_simd_fp_256), .ngrp = 1, .umasks = ivb_simd_fp_256, }, { .name = "LSD", .desc = "Loop stream detector", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xa8, .numasks = LIBPFM_ARRAY_SIZE(ivb_lsd), .ngrp = 1, .umasks = ivb_lsd, }, { .name = "EPT", .desc = "Extended page table", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0x4f, .numasks = LIBPFM_ARRAY_SIZE(ivb_ept), .ngrp = 1, .umasks = ivb_ept, }, { .name = "PAGE_WALKS", .desc = "page walker", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xbe, .numasks = LIBPFM_ARRAY_SIZE(ivb_page_walks), .ngrp = 1, .umasks = ivb_page_walks, }, { .name = "INT_MISC", .desc = "Miscellaneous interruptions", .code = 0xd, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V3_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivb_int_misc), .umasks = ivb_int_misc }, { .name = "OFFCORE_REQUESTS_BUFFER", .desc = "Offcore reqest buffer", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xb2, .numasks = LIBPFM_ARRAY_SIZE(ivb_offcore_requests_buffer), .ngrp = 1, .umasks = ivb_offcore_requests_buffer, }, { .name = "SQ_MISC", .desc = "SuperQueue miscellaneous", .modmsk = INTEL_V4_ATTRS, .cntmsk = 0xf, .code = 0xf4, .numasks = LIBPFM_ARRAY_SIZE(ivb_sq_misc), .ngrp = 1, .umasks = ivb_sq_misc, }, { .name = "OFFCORE_RESPONSE_0", .desc = "Offcore response event (must provide at least one request type and either any_response or any combination of supplier + snoop)", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x1b7, .flags= INTEL_X86_NHM_OFFCORE, .numasks = LIBPFM_ARRAY_SIZE(ivb_offcore_response), .ngrp = 3, .umasks = ivb_offcore_response, }, { .name = "OFFCORE_RESPONSE_1", .desc = "Offcore response event (must provide at least one request type and either any_response or any combination of supplier + snoop)", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x1bb, .flags= INTEL_X86_NHM_OFFCORE, .numasks = LIBPFM_ARRAY_SIZE(ivb_offcore_response), .ngrp = 3, .umasks = ivb_offcore_response, /* identical to actual umasks list for this event */ }, }; libpfm-4.9.0/lib/events/intel_ivbep_unc_pcu_events.h0000664000175000017500000003307113223402656022445 0ustar eranianeranian/* * Copyright (c) 2014 Google Inc. All rights reserved * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * PMU: ivbep_unc_pcu (Intel IvyBridge-EP PCU uncore) */ static const intel_x86_umask_t ivbep_unc_p_power_state_occupancy[]={ { .uname = "CORES_C0", .udesc = "Counts number of cores in C0", .ucode = 0x4000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "CORES_C3", .udesc = "Counts number of cores in C3", .ucode = 0x8000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "CORES_C6", .udesc = "Counts number of cores in C6", .ucode = 0xc000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_entry_t intel_ivbep_unc_p_pe[]={ { .name = "UNC_P_CLOCKTICKS", .desc = "PCU Uncore clockticks", .modmsk = IVBEP_UNC_PCU_ATTRS, .cntmsk = 0xf, .code = 0x00, }, { .name = "UNC_P_CORE0_TRANSITION_CYCLES", .desc = "Core 0 C State Transition Cycles", .code = 0x70, .cntmsk = 0xf, .modmsk = IVBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_CORE1_TRANSITION_CYCLES", .desc = "Core 1 C State Transition Cycles", .code = 0x71, .cntmsk = 0xf, .modmsk = IVBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_CORE2_TRANSITION_CYCLES", .desc = "Core 2 C State Transition Cycles", .code = 0x72, .cntmsk = 0xf, .modmsk = IVBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_CORE3_TRANSITION_CYCLES", .desc = "Core 3 C State Transition Cycles", .code = 0x73, .cntmsk = 0xf, .modmsk = IVBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_CORE4_TRANSITION_CYCLES", .desc = "Core 4 C State Transition Cycles", .code = 0x74, .cntmsk = 0xf, .modmsk = IVBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_CORE5_TRANSITION_CYCLES", .desc = "Core 5 C State Transition Cycles", .code = 0x75, .cntmsk = 0xf, .modmsk = IVBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_CORE6_TRANSITION_CYCLES", .desc = "Core 6 C State Transition Cycles", .code = 0x76, .cntmsk = 0xf, .modmsk = IVBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_CORE7_TRANSITION_CYCLES", .desc = "Core 7 C State Transition Cycles", .code = 0x77, .cntmsk = 0xf, .modmsk = IVBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_CORE8_TRANSITION_CYCLES", .desc = "Core 8 C State Transition Cycles", .code = 0x78, .cntmsk = 0xf, .modmsk = IVBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_CORE9_TRANSITION_CYCLES", .desc = "Core 9 C State Transition Cycles", .code = 0x79, .cntmsk = 0xf, .modmsk = IVBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_CORE10_TRANSITION_CYCLES", .desc = "Core 10 C State Transition Cycles", .code = 0x7a, .cntmsk = 0xf, .modmsk = IVBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_CORE11_TRANSITION_CYCLES", .desc = "Core 11 C State Transition Cycles", .code = 0x7b, .cntmsk = 0xf, .modmsk = IVBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_CORE12_TRANSITION_CYCLES", .desc = "Core 12 C State Transition Cycles", .code = 0x7c, .cntmsk = 0xf, .modmsk = IVBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_CORE13_TRANSITION_CYCLES", .desc = "Core 13 C State Transition Cycles", .code = 0x7d, .cntmsk = 0xf, .modmsk = IVBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_CORE14_TRANSITION_CYCLES", .desc = "Core 14 C State Transition Cycles", .code = 0x7e, .cntmsk = 0xf, .modmsk = IVBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_DELAYED_C_STATE_ABORT_CORE0", .desc = "Deep C state rejection Core 0", .code = 0x17 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = IVBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_DELAYED_C_STATE_ABORT_CORE1", .desc = "Deep C state rejection Core 1", .code = 0x18 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = IVBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_DELAYED_C_STATE_ABORT_CORE2", .desc = "Deep C state rejection Core 2", .code = 0x19 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = IVBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_DELAYED_C_STATE_ABORT_CORE3", .desc = "Deep C state rejection Core 3", .code = 0x1a | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = IVBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_DELAYED_C_STATE_ABORT_CORE4", .desc = "Deep C state rejection Core 4", .code = 0x1b | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = IVBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_DELAYED_C_STATE_ABORT_CORE5", .desc = "Deep C state rejection Core 5", .code = 0x1c | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = IVBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_DELAYED_C_STATE_ABORT_CORE6", .desc = "Deep C state rejection Core 6", .code = 0x1d | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = IVBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_DELAYED_C_STATE_ABORT_CORE7", .desc = "Deep C state rejection Core 7", .code = 0x1e | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = IVBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_DELAYED_C_STATE_ABORT_CORE8", .desc = "Deep C state rejection Core 8", .code = 0x1f | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = IVBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_DELAYED_C_STATE_ABORT_CORE9", .desc = "Deep C state rejection Core 9", .code = 0x20 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = IVBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_DELAYED_C_STATE_ABORT_CORE10", .desc = "Deep C state rejection Core 10", .code = 0x21 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = IVBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_DELAYED_C_STATE_ABORT_CORE11", .desc = "Deep C state rejection Core 11", .code = 0x22 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = IVBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_DELAYED_C_STATE_ABORT_CORE12", .desc = "Deep C state rejection Core 12", .code = 0x23 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = IVBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_DELAYED_C_STATE_ABORT_CORE13", .desc = "Deep C state rejection Core 13", .code = 0x24 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = IVBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_DELAYED_C_STATE_ABORT_CORE14", .desc = "Deep C state rejection Core 14", .code = 0x25 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = IVBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_DEMOTIONS_CORE0", .desc = "Core 0 C State Demotions", .code = 0x1e, .cntmsk = 0xf, .modmsk = IVBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_DEMOTIONS_CORE1", .desc = "Core 1 C State Demotions", .code = 0x1f, .cntmsk = 0xf, .modmsk = IVBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_DEMOTIONS_CORE2", .desc = "Core 2 C State Demotions", .code = 0x20, .cntmsk = 0xf, .modmsk = IVBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_DEMOTIONS_CORE3", .desc = "Core 3 C State Demotions", .code = 0x21, .cntmsk = 0xf, .modmsk = IVBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_DEMOTIONS_CORE4", .desc = "Core 4 C State Demotions", .code = 0x22, .cntmsk = 0xf, .modmsk = IVBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_DEMOTIONS_CORE5", .desc = "Core 5 C State Demotions", .code = 0x23, .cntmsk = 0xf, .modmsk = IVBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_DEMOTIONS_CORE6", .desc = "Core 6 C State Demotions", .code = 0x24, .cntmsk = 0xf, .modmsk = IVBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_DEMOTIONS_CORE7", .desc = "Core 7 C State Demotions", .code = 0x25, .cntmsk = 0xf, .modmsk = IVBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_DEMOTIONS_CORE8", .desc = "Core 8 C State Demotions", .code = 0x40, .cntmsk = 0xf, .modmsk = IVBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_DEMOTIONS_CORE9", .desc = "Core 9 C State Demotions", .code = 0x41, .cntmsk = 0xf, .modmsk = IVBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_DEMOTIONS_CORE10", .desc = "Core 10 C State Demotions", .code = 0x42, .cntmsk = 0xf, .modmsk = IVBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_DEMOTIONS_CORE11", .desc = "Core 11 C State Demotions", .code = 0x43, .cntmsk = 0xf, .modmsk = IVBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_DEMOTIONS_CORE12", .desc = "Core 12 C State Demotions", .code = 0x44, .cntmsk = 0xf, .modmsk = IVBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_DEMOTIONS_CORE13", .desc = "Core 13 C State Demotions", .code = 0x45, .cntmsk = 0xf, .modmsk = IVBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_DEMOTIONS_CORE14", .desc = "Core 14 C State Demotions", .code = 0x46, .cntmsk = 0xf, .modmsk = IVBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_FREQ_BAND0_CYCLES", .desc = "Frequency Residency", .code = 0xb, .cntmsk = 0xf, .flags = INTEL_X86_NO_AUTOENCODE, .modmsk = IVBEP_UNC_PCU_BAND_ATTRS, .modmsk_req = _SNBEP_UNC_ATTR_FF, }, { .name = "UNC_P_FREQ_BAND1_CYCLES", .desc = "Frequency Residency", .code = 0xc, .cntmsk = 0xf, .flags = INTEL_X86_NO_AUTOENCODE, .modmsk = IVBEP_UNC_PCU_BAND_ATTRS, .modmsk_req = _SNBEP_UNC_ATTR_FF, }, { .name = "UNC_P_FREQ_BAND2_CYCLES", .desc = "Frequency Residency", .code = 0xd, .cntmsk = 0xf, .flags = INTEL_X86_NO_AUTOENCODE, .modmsk = IVBEP_UNC_PCU_BAND_ATTRS, .modmsk_req = _SNBEP_UNC_ATTR_FF, }, { .name = "UNC_P_FREQ_BAND3_CYCLES", .desc = "Frequency Residency", .code = 0xe, .cntmsk = 0xf, .flags = INTEL_X86_NO_AUTOENCODE, .modmsk = IVBEP_UNC_PCU_BAND_ATTRS, .modmsk_req = _SNBEP_UNC_ATTR_FF, }, { .name = "UNC_P_FREQ_MAX_CURRENT_CYCLES", .desc = "Current Strongest Upper Limit Cycles", .code = 0x7, .cntmsk = 0xf, .modmsk = IVBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES", .desc = "Thermal Strongest Upper Limit Cycles", .code = 0x4, .cntmsk = 0xf, .modmsk = IVBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_FREQ_MAX_OS_CYCLES", .desc = "OS Strongest Upper Limit Cycles", .code = 0x6, .cntmsk = 0xf, .modmsk = IVBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_FREQ_MAX_POWER_CYCLES", .desc = "Power Strongest Upper Limit Cycles", .code = 0x5, .cntmsk = 0xf, .modmsk = IVBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_FREQ_MIN_PERF_P_CYCLES", .desc = "Perf P Limit Strongest Lower Limit Cycles", .code = 0x02 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = IVBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_FREQ_MIN_IO_P_CYCLES", .desc = "IO P Limit Strongest Lower Limit Cycles", .code = 0x61, .cntmsk = 0xf, .modmsk = IVBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_FREQ_TRANS_CYCLES", .desc = "Cycles spent changing Frequency", .code = 0x60, .cntmsk = 0xf, .modmsk = IVBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES", .desc = "Memory Phase Shedding Cycles", .code = 0x2f, .cntmsk = 0xf, .modmsk = IVBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_PKG_C_EXIT_LATENCY", .desc = "Package C state exit latency. Counts cycles the package is transitioning from C2 to C3", .code = 0x26 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = IVBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_POWER_STATE_OCCUPANCY", .desc = "Number of cores in C0", .code = 0x80, .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_PCU_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_p_power_state_occupancy), .umasks = ivbep_unc_p_power_state_occupancy }, { .name = "UNC_P_PROCHOT_EXTERNAL_CYCLES", .desc = "External Prochot", .code = 0xa, .cntmsk = 0xf, .modmsk = IVBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_PROCHOT_INTERNAL_CYCLES", .desc = "Internal Prochot", .code = 0x9, .cntmsk = 0xf, .modmsk = IVBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_TOTAL_TRANSITION_CYCLES", .desc = "Total Core C State Transition Cycles", .code = 0x63, .cntmsk = 0xf, .modmsk = IVBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_VOLT_TRANS_CYCLES_CHANGE", .desc = "Cycles Changing Voltage", .code = 0x3, .cntmsk = 0xf, .modmsk = IVBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_VOLT_TRANS_CYCLES_DECREASE", .desc = "Cycles Decreasing Voltage", .code = 0x2, .cntmsk = 0xf, .modmsk = IVBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_VOLT_TRANS_CYCLES_INCREASE", .desc = "Cycles Increasing Voltage", .code = 0x1, .cntmsk = 0xf, .modmsk = IVBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_VR_HOT_CYCLES", .desc = "VR Hot", .code = 0x32, .cntmsk = 0xf, .modmsk = IVBEP_UNC_PCU_ATTRS, }, }; libpfm-4.9.0/lib/events/arm_cortex_a8_events.h0000664000175000017500000001460313223402656021164 0ustar eranianeranian/* * Copyright (c) 2010 University of Tennessee * Contributed by Vince Weaver * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. */ /* * the various event names are the same as those given in the * file linux-2.6/arch/arm/kernel/perf_event.c */ /* * Cortex A8 Event Table */ static const arm_entry_t arm_cortex_a8_pe []={ {.name = "PMNC_SW_INCR", .code = 0x00, .desc = "Incremented by writes to the Software Increment Register" }, {.name = "IFETCH_MISS", .code = 0x01, .desc = "Instruction fetches that cause lowest-level cache miss" }, {.name = "ITLB_MISS", .code = 0x02, .desc = "Instruction fetches that cause lowest-level TLB miss" }, {.name = "DCACHE_REFILL", .code = 0x03, .desc = "Data read or writes that cause lowest-level cache miss" }, {.name = "DCACHE_ACCESS", .code = 0x04, .desc = "Data read or writes that cause lowest-level cache access" }, {.name = "DTLB_REFILL", .code = 0x05, .desc = "Data read or writes that cause lowest-level TLB refill" }, {.name = "DREAD", .code = 0x06, .desc = "Data read architecturally executed" }, {.name = "DWRITE", .code = 0x07, .desc = "Data write architecturally executed" }, {.name = "INSTR_EXECUTED", .code = 0x08, .desc = "Instructions architecturally executed" }, {.name = "EXC_TAKEN", .code = 0x09, .desc = "Counts each exception taken" }, {.name = "EXC_EXECUTED", .code = 0x0a, .desc = "Exception returns architecturally executed" }, {.name = "CID_WRITE", .code = 0x0b, .desc = "Instruction writes to Context ID Register, architecturally executed" }, {.name = "PC_WRITE", .code = 0x0c, .desc = "Software change of PC. Equivalent to branches" }, {.name = "PC_IMM_BRANCH", .code = 0x0d, .desc = "Immediate branches architecturally executed" }, {.name = "PC_PROC_RETURN", .code = 0x0e, .desc = "Procedure returns architecturally executed" }, {.name = "UNALIGNED_ACCESS", .code = 0x0f, .desc = "Unaligned accesses architecturally executed" }, {.name = "PC_BRANCH_MIS_PRED", .code = 0x10, .desc = "Branches mispredicted or not predicted" }, {.name = "CLOCK_CYCLES", /* this isn't in the Cortex-A8 tech doc */ .code = 0x11, /* but is in linux kernel */ .desc = "Clock cycles" }, {.name = "PC_BRANCH_MIS_USED", .code = 0x12, .desc = "Branches that could have been predicted" }, {.name = "WRITE_BUFFER_FULL", .code = 0x40, .desc = "Cycles Write buffer full" }, {.name = "L2_STORE_MERGED", .code = 0x41, .desc = "Stores merged in L2" }, {.name = "L2_STORE_BUFF", .code = 0x42, .desc = "Bufferable store transactions to L2" }, {.name = "L2_ACCESS", .code = 0x43, .desc = "Accesses to L2 cache" }, {.name = "L2_CACHE_MISS", .code = 0x44, .desc = "L2 cache misses" }, {.name = "AXI_READ_CYCLES", .code = 0x45, .desc = "Cycles with active AXI read channel transactions" }, {.name = "AXI_WRITE_CYCLES", .code = 0x46, .desc = "Cycles with Active AXI write channel transactions" }, {.name = "MEMORY_REPLAY", .code = 0x47, .desc = "Memory replay events" }, {.name = "UNALIGNED_ACCESS_REPLAY", .code = 0x48, .desc = "Unaligned accesses causing replays" }, {.name = "L1_DATA_MISS", .code = 0x49, .desc = "L1 data misses due to hashing algorithm" }, {.name = "L1_INST_MISS", .code = 0x4a, .desc = "L1 instruction misses due to hashing algorithm" }, {.name = "L1_DATA_COLORING", .code = 0x4b, .desc = "L1 data access where page color alias occurs" }, {.name = "L1_NEON_DATA", .code = 0x4c, .desc = "NEON accesses that hit in L1 cache" }, {.name = "L1_NEON_CACH_DATA", .code = 0x4d, .desc = "NEON cache accesses for L1 cache" }, {.name = "L2_NEON", .code = 0x4e, .desc = "L2 accesses caused by NEON" }, {.name = "L2_NEON_HIT", .code = 0x4f, .desc = "L2 hits caused by NEON" }, {.name = "L1_INST", .code = 0x50, .desc = "L1 instruction cache accesses" }, {.name = "PC_RETURN_MIS_PRED", .code = 0x51, .desc = "Return stack mispredictions" }, {.name = "PC_BRANCH_FAILED", .code = 0x52, .desc = "Branch prediction failures" }, {.name = "PC_BRANCH_TAKEN", .code = 0x53, .desc = "Branches predicted taken" }, {.name = "PC_BRANCH_EXECUTED", .code = 0x54, .desc = "Taken branches executed" }, {.name = "OP_EXECUTED", .code = 0x55, .desc = "Operations executed (includes sub-ops in multi-cycle instructions)" }, {.name = "CYCLES_INST_STALL", .code = 0x56, .desc = "Cycles no instruction is available for issue" }, {.name = "CYCLES_INST", .code = 0x57, .desc = "Number of instructions issued in cycle" }, {.name = "CYCLES_NEON_DATA_STALL", .code = 0x58, .desc = "Cycles stalled waiting on NEON MRC data" }, {.name = "CYCLES_NEON_INST_STALL", .code = 0x59, .desc = "Cycles stalled due to full NEON queues" }, {.name = "NEON_CYCLES", .code = 0x5a, .desc = "Cycles NEON and integer processors both not idle" }, {.name = "PMU0_EVENTS", .code = 0x70, .desc = "External PMUEXTIN[0] event" }, {.name = "PMU1_EVENTS", .code = 0x71, .desc = "External PMUEXTIN[1] event" }, {.name = "PMU_EVENTS", .code = 0x72, .desc = "External PMUEXTIN[0] or PMUEXTIN[1] event" }, {.name = "CPU_CYCLES", .code = 0xff, .desc = "CPU cycles" }, }; #define ARM_CORTEX_A8_EVENT_COUNT (sizeof(arm_cortex_a8_pe)/sizeof(arm_entry_t)) libpfm-4.9.0/lib/events/intel_hswep_unc_pcu_events.h0000664000175000017500000002674113223402656022474 0ustar eranianeranian/* * Copyright (c) 2014 Google Inc. All rights reserved * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * PMU: hswep_unc_pcu (Intel Haswell-EP PCU uncore) */ static const intel_x86_umask_t hswep_unc_p_power_state_occupancy[]={ { .uname = "CORES_C0", .udesc = "Counts number of cores in C0", .ucode = 0x4000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "CORES_C3", .udesc = "Counts number of cores in C3", .ucode = 0x8000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "CORES_C6", .udesc = "Counts number of cores in C6", .ucode = 0xc000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_entry_t intel_hswep_unc_p_pe[]={ { .name = "UNC_P_CLOCKTICKS", .desc = "PCU Uncore clockticks", .modmsk = HSWEP_UNC_PCU_ATTRS, .cntmsk = 0xf, .code = 0x00, }, { .name = "UNC_P_CORE0_TRANSITION_CYCLES", .desc = "Core 0 C State Transition Cycles", .code = 0x60, .cntmsk = 0xf, .modmsk = HSWEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_CORE1_TRANSITION_CYCLES", .desc = "Core 1 C State Transition Cycles", .code = 0x61, .cntmsk = 0xf, .modmsk = HSWEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_CORE2_TRANSITION_CYCLES", .desc = "Core 2 C State Transition Cycles", .code = 0x62, .cntmsk = 0xf, .modmsk = HSWEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_CORE3_TRANSITION_CYCLES", .desc = "Core 3 C State Transition Cycles", .code = 0x63, .cntmsk = 0xf, .modmsk = HSWEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_CORE4_TRANSITION_CYCLES", .desc = "Core 4 C State Transition Cycles", .code = 0x64, .cntmsk = 0xf, .modmsk = HSWEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_CORE5_TRANSITION_CYCLES", .desc = "Core 5 C State Transition Cycles", .code = 0x65, .cntmsk = 0xf, .modmsk = HSWEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_CORE6_TRANSITION_CYCLES", .desc = "Core 6 C State Transition Cycles", .code = 0x66, .cntmsk = 0xf, .modmsk = HSWEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_CORE7_TRANSITION_CYCLES", .desc = "Core 7 C State Transition Cycles", .code = 0x67, .cntmsk = 0xf, .modmsk = HSWEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_CORE8_TRANSITION_CYCLES", .desc = "Core 8 C State Transition Cycles", .code = 0x68, .cntmsk = 0xf, .modmsk = HSWEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_CORE9_TRANSITION_CYCLES", .desc = "Core 9 C State Transition Cycles", .code = 0x69, .cntmsk = 0xf, .modmsk = HSWEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_CORE10_TRANSITION_CYCLES", .desc = "Core 10 C State Transition Cycles", .code = 0x6a, .cntmsk = 0xf, .modmsk = HSWEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_CORE11_TRANSITION_CYCLES", .desc = "Core 11 C State Transition Cycles", .code = 0x6b, .cntmsk = 0xf, .modmsk = HSWEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_CORE12_TRANSITION_CYCLES", .desc = "Core 12 C State Transition Cycles", .code = 0x6c, .cntmsk = 0xf, .modmsk = HSWEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_CORE13_TRANSITION_CYCLES", .desc = "Core 13 C State Transition Cycles", .code = 0x6d, .cntmsk = 0xf, .modmsk = HSWEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_CORE14_TRANSITION_CYCLES", .desc = "Core 14 C State Transition Cycles", .code = 0x6e, .cntmsk = 0xf, .modmsk = HSWEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_CORE15_TRANSITION_CYCLES", .desc = "Core 15 C State Transition Cycles", .code = 0x6f, .cntmsk = 0xf, .modmsk = HSWEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_CORE16_TRANSITION_CYCLES", .desc = "Core 16 C State Transition Cycles", .code = 0x70, .cntmsk = 0xf, .modmsk = HSWEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_CORE17_TRANSITION_CYCLES", .desc = "Core 17 C State Transition Cycles", .code = 0x71, .cntmsk = 0xf, .modmsk = HSWEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_DEMOTIONS_CORE0", .desc = "Core 0 C State Demotions", .code = 0x30, .cntmsk = 0xf, .modmsk = HSWEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_DEMOTIONS_CORE1", .desc = "Core 1 C State Demotions", .code = 0x31, .cntmsk = 0xf, .modmsk = HSWEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_DEMOTIONS_CORE2", .desc = "Core 2 C State Demotions", .code = 0x32, .cntmsk = 0xf, .modmsk = HSWEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_DEMOTIONS_CORE3", .desc = "Core 3 C State Demotions", .code = 0x33, .cntmsk = 0xf, .modmsk = HSWEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_DEMOTIONS_CORE4", .desc = "Core 4 C State Demotions", .code = 0x34, .cntmsk = 0xf, .modmsk = HSWEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_DEMOTIONS_CORE5", .desc = "Core 5 C State Demotions", .code = 0x35, .cntmsk = 0xf, .modmsk = HSWEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_DEMOTIONS_CORE6", .desc = "Core 6 C State Demotions", .code = 0x36, .cntmsk = 0xf, .modmsk = HSWEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_DEMOTIONS_CORE7", .desc = "Core 7 C State Demotions", .code = 0x37, .cntmsk = 0xf, .modmsk = HSWEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_DEMOTIONS_CORE8", .desc = "Core 8 C State Demotions", .code = 0x38, .cntmsk = 0xf, .modmsk = HSWEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_DEMOTIONS_CORE9", .desc = "Core 9 C State Demotions", .code = 0x39, .cntmsk = 0xf, .modmsk = HSWEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_DEMOTIONS_CORE10", .desc = "Core 10 C State Demotions", .code = 0x3a, .cntmsk = 0xf, .modmsk = HSWEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_DEMOTIONS_CORE11", .desc = "Core 11 C State Demotions", .code = 0x3b, .cntmsk = 0xf, .modmsk = HSWEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_DEMOTIONS_CORE12", .desc = "Core 12 C State Demotions", .code = 0x3c, .cntmsk = 0xf, .modmsk = HSWEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_DEMOTIONS_CORE13", .desc = "Core 13 C State Demotions", .code = 0x3d, .cntmsk = 0xf, .modmsk = HSWEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_DEMOTIONS_CORE14", .desc = "Core 14 C State Demotions", .code = 0x3e, .cntmsk = 0xf, .modmsk = HSWEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_DEMOTIONS_CORE15", .desc = "Core 15 C State Demotions", .code = 0x3f, .cntmsk = 0xf, .modmsk = HSWEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_DEMOTIONS_CORE16", .desc = "Core 16 C State Demotions", .code = 0x40, .cntmsk = 0xf, .modmsk = HSWEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_DEMOTIONS_CORE17", .desc = "Core 17 C State Demotions", .code = 0x41, .cntmsk = 0xf, .modmsk = HSWEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_FREQ_BAND0_CYCLES", .desc = "Frequency Residency", .code = 0xb, .cntmsk = 0xf, .flags = INTEL_X86_NO_AUTOENCODE, .modmsk = HSWEP_UNC_PCU_BAND_ATTRS, .modmsk_req = _SNBEP_UNC_ATTR_FF, }, { .name = "UNC_P_FREQ_BAND1_CYCLES", .desc = "Frequency Residency", .code = 0xc, .cntmsk = 0xf, .flags = INTEL_X86_NO_AUTOENCODE, .modmsk = HSWEP_UNC_PCU_BAND_ATTRS, .modmsk_req = _SNBEP_UNC_ATTR_FF, }, { .name = "UNC_P_FREQ_BAND2_CYCLES", .desc = "Frequency Residency", .code = 0xd, .cntmsk = 0xf, .flags = INTEL_X86_NO_AUTOENCODE, .modmsk = HSWEP_UNC_PCU_BAND_ATTRS, .modmsk_req = _SNBEP_UNC_ATTR_FF, }, { .name = "UNC_P_FREQ_BAND3_CYCLES", .desc = "Frequency Residency", .code = 0xe, .cntmsk = 0xf, .flags = INTEL_X86_NO_AUTOENCODE, .modmsk = HSWEP_UNC_PCU_BAND_ATTRS, .modmsk_req = _SNBEP_UNC_ATTR_FF, }, { .name = "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES", .desc = "Thermal Strongest Upper Limit Cycles", .code = 0x4, .cntmsk = 0xf, .modmsk = HSWEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_FREQ_MAX_OS_CYCLES", .desc = "OS Strongest Upper Limit Cycles", .code = 0x6, .cntmsk = 0xf, .modmsk = HSWEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_FREQ_MAX_POWER_CYCLES", .desc = "Power Strongest Upper Limit Cycles", .code = 0x5, .cntmsk = 0xf, .modmsk = HSWEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_FREQ_MIN_IO_P_CYCLES", .desc = "IO P Limit Strongest Lower Limit Cycles", .code = 0x73, .cntmsk = 0xf, .modmsk = HSWEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_FREQ_TRANS_CYCLES", .desc = "Cycles spent changing Frequency", .code = 0x74, .cntmsk = 0xf, .modmsk = HSWEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_PKG_RESIDENCY_C0_CYCLES", .desc = "Package C State residency - C0", .code = 0x2a, .cntmsk = 0xf, .modmsk = HSWEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_PKG_RESIDENCY_C1E_CYCLES", .desc = "Package C State residency - C1E", .code = 0x4e, .cntmsk = 0xf, .modmsk = HSWEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_PKG_RESIDENCY_C2E_CYCLES", .desc = "Package C State residency - C2E", .code = 0x2b, .cntmsk = 0xf, .modmsk = HSWEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_PKG_RESIDENCY_C3_CYCLES", .desc = "Package C State residency - C3", .code = 0x2c, .cntmsk = 0xf, .modmsk = HSWEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_PKG_RESIDENCY_C6_CYCLES", .desc = "Package C State residency - C6", .code = 0x2d, .cntmsk = 0xf, .modmsk = HSWEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_PKG_RESIDENCY_C7_CYCLES", .desc = "Package C State residency - C7", .code = 0x2e, .cntmsk = 0xf, .modmsk = HSWEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES", .desc = "Memory Phase Shedding Cycles", .code = 0x2f, .cntmsk = 0xf, .modmsk = HSWEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_POWER_STATE_OCCUPANCY", .desc = "Number of cores in C0", .code = 0x80, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_PCU_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_p_power_state_occupancy), .umasks = hswep_unc_p_power_state_occupancy }, { .name = "UNC_P_PROCHOT_EXTERNAL_CYCLES", .desc = "External Prochot", .code = 0xa, .cntmsk = 0xf, .modmsk = HSWEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_PROCHOT_INTERNAL_CYCLES", .desc = "Internal Prochot", .code = 0x9, .cntmsk = 0xf, .modmsk = HSWEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_TOTAL_TRANSITION_CYCLES", .desc = "Total Core C State Transition Cycles", .code = 0x72, .cntmsk = 0xf, .modmsk = HSWEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_VR_HOT_CYCLES", .desc = "VR Hot", .code = 0x42, .cntmsk = 0xf, .modmsk = HSWEP_UNC_PCU_ATTRS, }, }; libpfm-4.9.0/lib/events/power8_events.h0000664000175000017500000130122413223402656017654 0ustar eranianeranian/****************************/ /* THIS IS OPEN SOURCE CODE */ /****************************/ #ifndef __POWER8_EVENTS_H__ #define __POWER8_EVENTS_H__ /* * File: power8_events.h * CVS: * Author: Carl Love * carll.ibm.com * Mods: * * * (C) Copyright IBM Corporation, 2013. All Rights Reserved. * Contributed by * * Note: This code was automatically generated and should not be modified by * hand. * * Documentation on the PMU events will be published at: * http://www.power.org/documentation */ #define POWER8_PME_PM_1LPAR_CYC 0 #define POWER8_PME_PM_1PLUS_PPC_CMPL 1 #define POWER8_PME_PM_1PLUS_PPC_DISP 2 #define POWER8_PME_PM_2LPAR_CYC 3 #define POWER8_PME_PM_4LPAR_CYC 4 #define POWER8_PME_PM_ALL_CHIP_PUMP_CPRED 5 #define POWER8_PME_PM_ALL_GRP_PUMP_CPRED 6 #define POWER8_PME_PM_ALL_GRP_PUMP_MPRED 7 #define POWER8_PME_PM_ALL_GRP_PUMP_MPRED_RTY 8 #define POWER8_PME_PM_ALL_PUMP_CPRED 9 #define POWER8_PME_PM_ALL_PUMP_MPRED 10 #define POWER8_PME_PM_ALL_SYS_PUMP_CPRED 11 #define POWER8_PME_PM_ALL_SYS_PUMP_MPRED 12 #define POWER8_PME_PM_ALL_SYS_PUMP_MPRED_RTY 13 #define POWER8_PME_PM_ANY_THRD_RUN_CYC 14 #define POWER8_PME_PM_BACK_BR_CMPL 15 #define POWER8_PME_PM_BANK_CONFLICT 16 #define POWER8_PME_PM_BRU_FIN 17 #define POWER8_PME_PM_BR_2PATH 18 #define POWER8_PME_PM_BR_BC_8 19 #define POWER8_PME_PM_BR_BC_8_CONV 20 #define POWER8_PME_PM_BR_CMPL 21 #define POWER8_PME_PM_BR_MPRED_CCACHE 22 #define POWER8_PME_PM_BR_MPRED_CMPL 23 #define POWER8_PME_PM_BR_MPRED_CR 24 #define POWER8_PME_PM_BR_MPRED_LSTACK 25 #define POWER8_PME_PM_BR_MPRED_TA 26 #define POWER8_PME_PM_BR_MRK_2PATH 27 #define POWER8_PME_PM_BR_PRED_BR0 28 #define POWER8_PME_PM_BR_PRED_BR1 29 #define POWER8_PME_PM_BR_PRED_BR_CMPL 30 #define POWER8_PME_PM_BR_PRED_CCACHE_BR0 31 #define POWER8_PME_PM_BR_PRED_CCACHE_BR1 32 #define POWER8_PME_PM_BR_PRED_CCACHE_CMPL 33 #define POWER8_PME_PM_BR_PRED_CR_BR0 34 #define POWER8_PME_PM_BR_PRED_CR_BR1 35 #define POWER8_PME_PM_BR_PRED_CR_CMPL 36 #define POWER8_PME_PM_BR_PRED_LSTACK_BR0 37 #define POWER8_PME_PM_BR_PRED_LSTACK_BR1 38 #define POWER8_PME_PM_BR_PRED_LSTACK_CMPL 39 #define POWER8_PME_PM_BR_PRED_TA_BR0 40 #define POWER8_PME_PM_BR_PRED_TA_BR1 41 #define POWER8_PME_PM_BR_PRED_TA_CMPL 42 #define POWER8_PME_PM_BR_TAKEN_CMPL 43 #define POWER8_PME_PM_BR_UNCOND_BR0 44 #define POWER8_PME_PM_BR_UNCOND_BR1 45 #define POWER8_PME_PM_BR_UNCOND_CMPL 46 #define POWER8_PME_PM_CASTOUT_ISSUED 47 #define POWER8_PME_PM_CASTOUT_ISSUED_GPR 48 #define POWER8_PME_PM_CHIP_PUMP_CPRED 49 #define POWER8_PME_PM_CLB_HELD 50 #define POWER8_PME_PM_CMPLU_STALL 51 #define POWER8_PME_PM_CMPLU_STALL_BRU 52 #define POWER8_PME_PM_CMPLU_STALL_BRU_CRU 53 #define POWER8_PME_PM_CMPLU_STALL_COQ_FULL 54 #define POWER8_PME_PM_CMPLU_STALL_DCACHE_MISS 55 #define POWER8_PME_PM_CMPLU_STALL_DMISS_L21_L31 56 #define POWER8_PME_PM_CMPLU_STALL_DMISS_L2L3 57 #define POWER8_PME_PM_CMPLU_STALL_DMISS_L2L3_CONFLICT 58 #define POWER8_PME_PM_CMPLU_STALL_DMISS_L3MISS 59 #define POWER8_PME_PM_CMPLU_STALL_DMISS_LMEM 60 #define POWER8_PME_PM_CMPLU_STALL_DMISS_REMOTE 61 #define POWER8_PME_PM_CMPLU_STALL_ERAT_MISS 62 #define POWER8_PME_PM_CMPLU_STALL_FLUSH 63 #define POWER8_PME_PM_CMPLU_STALL_FXLONG 64 #define POWER8_PME_PM_CMPLU_STALL_FXU 65 #define POWER8_PME_PM_CMPLU_STALL_HWSYNC 66 #define POWER8_PME_PM_CMPLU_STALL_LOAD_FINISH 67 #define POWER8_PME_PM_CMPLU_STALL_LSU 68 #define POWER8_PME_PM_CMPLU_STALL_LWSYNC 69 #define POWER8_PME_PM_CMPLU_STALL_MEM_ECC_DELAY 70 #define POWER8_PME_PM_CMPLU_STALL_NO_NTF 71 #define POWER8_PME_PM_CMPLU_STALL_NTCG_FLUSH 72 #define POWER8_PME_PM_CMPLU_STALL_OTHER_CMPL 73 #define POWER8_PME_PM_CMPLU_STALL_REJECT 74 #define POWER8_PME_PM_CMPLU_STALL_REJECT_LHS 75 #define POWER8_PME_PM_CMPLU_STALL_REJ_LMQ_FULL 76 #define POWER8_PME_PM_CMPLU_STALL_SCALAR 77 #define POWER8_PME_PM_CMPLU_STALL_SCALAR_LONG 78 #define POWER8_PME_PM_CMPLU_STALL_STORE 79 #define POWER8_PME_PM_CMPLU_STALL_ST_FWD 80 #define POWER8_PME_PM_CMPLU_STALL_THRD 81 #define POWER8_PME_PM_CMPLU_STALL_VECTOR 82 #define POWER8_PME_PM_CMPLU_STALL_VECTOR_LONG 83 #define POWER8_PME_PM_CMPLU_STALL_VSU 84 #define POWER8_PME_PM_CO0_ALLOC 85 #define POWER8_PME_PM_CO0_BUSY 86 #define POWER8_PME_PM_CO_DISP_FAIL 87 #define POWER8_PME_PM_CO_TM_SC_FOOTPRINT 88 #define POWER8_PME_PM_CO_USAGE 89 #define POWER8_PME_PM_CRU_FIN 90 #define POWER8_PME_PM_CYC 91 #define POWER8_PME_PM_DATA_ALL_CHIP_PUMP_CPRED 92 #define POWER8_PME_PM_DATA_ALL_FROM_DL2L3_MOD 93 #define POWER8_PME_PM_DATA_ALL_FROM_DL2L3_SHR 94 #define POWER8_PME_PM_DATA_ALL_FROM_DL4 95 #define POWER8_PME_PM_DATA_ALL_FROM_DMEM 96 #define POWER8_PME_PM_DATA_ALL_FROM_L2 97 #define POWER8_PME_PM_DATA_ALL_FROM_L21_MOD 98 #define POWER8_PME_PM_DATA_ALL_FROM_L21_SHR 99 #define POWER8_PME_PM_DATA_ALL_FROM_L2MISS_MOD 100 #define POWER8_PME_PM_DATA_ALL_FROM_L2_DISP_CONFLICT_LDHITST 101 #define POWER8_PME_PM_DATA_ALL_FROM_L2_DISP_CONFLICT_OTHER 102 #define POWER8_PME_PM_DATA_ALL_FROM_L2_MEPF 103 #define POWER8_PME_PM_DATA_ALL_FROM_L2_NO_CONFLICT 104 #define POWER8_PME_PM_DATA_ALL_FROM_L3 105 #define POWER8_PME_PM_DATA_ALL_FROM_L31_ECO_MOD 106 #define POWER8_PME_PM_DATA_ALL_FROM_L31_ECO_SHR 107 #define POWER8_PME_PM_DATA_ALL_FROM_L31_MOD 108 #define POWER8_PME_PM_DATA_ALL_FROM_L31_SHR 109 #define POWER8_PME_PM_DATA_ALL_FROM_L3MISS_MOD 110 #define POWER8_PME_PM_DATA_ALL_FROM_L3_DISP_CONFLICT 111 #define POWER8_PME_PM_DATA_ALL_FROM_L3_MEPF 112 #define POWER8_PME_PM_DATA_ALL_FROM_L3_NO_CONFLICT 113 #define POWER8_PME_PM_DATA_ALL_FROM_LL4 114 #define POWER8_PME_PM_DATA_ALL_FROM_LMEM 115 #define POWER8_PME_PM_DATA_ALL_FROM_MEMORY 116 #define POWER8_PME_PM_DATA_ALL_FROM_OFF_CHIP_CACHE 117 #define POWER8_PME_PM_DATA_ALL_FROM_ON_CHIP_CACHE 118 #define POWER8_PME_PM_DATA_ALL_FROM_RL2L3_MOD 119 #define POWER8_PME_PM_DATA_ALL_FROM_RL2L3_SHR 120 #define POWER8_PME_PM_DATA_ALL_FROM_RL4 121 #define POWER8_PME_PM_DATA_ALL_FROM_RMEM 122 #define POWER8_PME_PM_DATA_ALL_GRP_PUMP_CPRED 123 #define POWER8_PME_PM_DATA_ALL_GRP_PUMP_MPRED 124 #define POWER8_PME_PM_DATA_ALL_GRP_PUMP_MPRED_RTY 125 #define POWER8_PME_PM_DATA_ALL_PUMP_CPRED 126 #define POWER8_PME_PM_DATA_ALL_PUMP_MPRED 127 #define POWER8_PME_PM_DATA_ALL_SYS_PUMP_CPRED 128 #define POWER8_PME_PM_DATA_ALL_SYS_PUMP_MPRED 129 #define POWER8_PME_PM_DATA_ALL_SYS_PUMP_MPRED_RTY 130 #define POWER8_PME_PM_DATA_CHIP_PUMP_CPRED 131 #define POWER8_PME_PM_DATA_FROM_DL2L3_MOD 132 #define POWER8_PME_PM_DATA_FROM_DL2L3_SHR 133 #define POWER8_PME_PM_DATA_FROM_DL4 134 #define POWER8_PME_PM_DATA_FROM_DMEM 135 #define POWER8_PME_PM_DATA_FROM_L2 136 #define POWER8_PME_PM_DATA_FROM_L21_MOD 137 #define POWER8_PME_PM_DATA_FROM_L21_SHR 138 #define POWER8_PME_PM_DATA_FROM_L2MISS 139 #define POWER8_PME_PM_DATA_FROM_L2MISS_MOD 140 #define POWER8_PME_PM_DATA_FROM_L2_DISP_CONFLICT_LDHITST 141 #define POWER8_PME_PM_DATA_FROM_L2_DISP_CONFLICT_OTHER 142 #define POWER8_PME_PM_DATA_FROM_L2_MEPF 143 #define POWER8_PME_PM_DATA_FROM_L2_NO_CONFLICT 144 #define POWER8_PME_PM_DATA_FROM_L3 145 #define POWER8_PME_PM_DATA_FROM_L31_ECO_MOD 146 #define POWER8_PME_PM_DATA_FROM_L31_ECO_SHR 147 #define POWER8_PME_PM_DATA_FROM_L31_MOD 148 #define POWER8_PME_PM_DATA_FROM_L31_SHR 149 #define POWER8_PME_PM_DATA_FROM_L3MISS 150 #define POWER8_PME_PM_DATA_FROM_L3MISS_MOD 151 #define POWER8_PME_PM_DATA_FROM_L3_DISP_CONFLICT 152 #define POWER8_PME_PM_DATA_FROM_L3_MEPF 153 #define POWER8_PME_PM_DATA_FROM_L3_NO_CONFLICT 154 #define POWER8_PME_PM_DATA_FROM_LL4 155 #define POWER8_PME_PM_DATA_FROM_LMEM 156 #define POWER8_PME_PM_DATA_FROM_MEM 157 #define POWER8_PME_PM_DATA_FROM_MEMORY 158 #define POWER8_PME_PM_DATA_FROM_OFF_CHIP_CACHE 159 #define POWER8_PME_PM_DATA_FROM_ON_CHIP_CACHE 160 #define POWER8_PME_PM_DATA_FROM_RL2L3_MOD 161 #define POWER8_PME_PM_DATA_FROM_RL2L3_SHR 162 #define POWER8_PME_PM_DATA_FROM_RL4 163 #define POWER8_PME_PM_DATA_FROM_RMEM 164 #define POWER8_PME_PM_DATA_GRP_PUMP_CPRED 165 #define POWER8_PME_PM_DATA_GRP_PUMP_MPRED 166 #define POWER8_PME_PM_DATA_GRP_PUMP_MPRED_RTY 167 #define POWER8_PME_PM_DATA_PUMP_CPRED 168 #define POWER8_PME_PM_DATA_PUMP_MPRED 169 #define POWER8_PME_PM_DATA_SYS_PUMP_CPRED 170 #define POWER8_PME_PM_DATA_SYS_PUMP_MPRED 171 #define POWER8_PME_PM_DATA_SYS_PUMP_MPRED_RTY 172 #define POWER8_PME_PM_DATA_TABLEWALK_CYC 173 #define POWER8_PME_PM_DC_COLLISIONS 174 #define POWER8_PME_PM_DC_PREF_STREAM_ALLOC 175 #define POWER8_PME_PM_DC_PREF_STREAM_CONF 176 #define POWER8_PME_PM_DC_PREF_STREAM_FUZZY_CONF 177 #define POWER8_PME_PM_DC_PREF_STREAM_STRIDED_CONF 178 #define POWER8_PME_PM_DERAT_MISS_16G 179 #define POWER8_PME_PM_DERAT_MISS_16M 180 #define POWER8_PME_PM_DERAT_MISS_4K 181 #define POWER8_PME_PM_DERAT_MISS_64K 182 #define POWER8_PME_PM_DFU 183 #define POWER8_PME_PM_DFU_DCFFIX 184 #define POWER8_PME_PM_DFU_DENBCD 185 #define POWER8_PME_PM_DFU_MC 186 #define POWER8_PME_PM_DISP_CLB_HELD_BAL 187 #define POWER8_PME_PM_DISP_CLB_HELD_RES 188 #define POWER8_PME_PM_DISP_CLB_HELD_SB 189 #define POWER8_PME_PM_DISP_CLB_HELD_SYNC 190 #define POWER8_PME_PM_DISP_CLB_HELD_TLBIE 191 #define POWER8_PME_PM_DISP_HELD 192 #define POWER8_PME_PM_DISP_HELD_IQ_FULL 193 #define POWER8_PME_PM_DISP_HELD_MAP_FULL 194 #define POWER8_PME_PM_DISP_HELD_SRQ_FULL 195 #define POWER8_PME_PM_DISP_HELD_SYNC_HOLD 196 #define POWER8_PME_PM_DISP_HOLD_GCT_FULL 197 #define POWER8_PME_PM_DISP_WT 198 #define POWER8_PME_PM_DPTEG_FROM_DL2L3_MOD 199 #define POWER8_PME_PM_DPTEG_FROM_DL2L3_SHR 200 #define POWER8_PME_PM_DPTEG_FROM_DL4 201 #define POWER8_PME_PM_DPTEG_FROM_DMEM 202 #define POWER8_PME_PM_DPTEG_FROM_L2 203 #define POWER8_PME_PM_DPTEG_FROM_L21_MOD 204 #define POWER8_PME_PM_DPTEG_FROM_L21_SHR 205 #define POWER8_PME_PM_DPTEG_FROM_L2MISS 206 #define POWER8_PME_PM_DPTEG_FROM_L2_DISP_CONFLICT_LDHITST 207 #define POWER8_PME_PM_DPTEG_FROM_L2_DISP_CONFLICT_OTHER 208 #define POWER8_PME_PM_DPTEG_FROM_L2_MEPF 209 #define POWER8_PME_PM_DPTEG_FROM_L2_NO_CONFLICT 210 #define POWER8_PME_PM_DPTEG_FROM_L3 211 #define POWER8_PME_PM_DPTEG_FROM_L31_ECO_MOD 212 #define POWER8_PME_PM_DPTEG_FROM_L31_ECO_SHR 213 #define POWER8_PME_PM_DPTEG_FROM_L31_MOD 214 #define POWER8_PME_PM_DPTEG_FROM_L31_SHR 215 #define POWER8_PME_PM_DPTEG_FROM_L3MISS 216 #define POWER8_PME_PM_DPTEG_FROM_L3_DISP_CONFLICT 217 #define POWER8_PME_PM_DPTEG_FROM_L3_MEPF 218 #define POWER8_PME_PM_DPTEG_FROM_L3_NO_CONFLICT 219 #define POWER8_PME_PM_DPTEG_FROM_LL4 220 #define POWER8_PME_PM_DPTEG_FROM_LMEM 221 #define POWER8_PME_PM_DPTEG_FROM_MEMORY 222 #define POWER8_PME_PM_DPTEG_FROM_OFF_CHIP_CACHE 223 #define POWER8_PME_PM_DPTEG_FROM_ON_CHIP_CACHE 224 #define POWER8_PME_PM_DPTEG_FROM_RL2L3_MOD 225 #define POWER8_PME_PM_DPTEG_FROM_RL2L3_SHR 226 #define POWER8_PME_PM_DPTEG_FROM_RL4 227 #define POWER8_PME_PM_DPTEG_FROM_RMEM 228 #define POWER8_PME_PM_DSLB_MISS 229 #define POWER8_PME_PM_DTLB_MISS 230 #define POWER8_PME_PM_DTLB_MISS_16G 231 #define POWER8_PME_PM_DTLB_MISS_16M 232 #define POWER8_PME_PM_DTLB_MISS_4K 233 #define POWER8_PME_PM_DTLB_MISS_64K 234 #define POWER8_PME_PM_EAT_FORCE_MISPRED 235 #define POWER8_PME_PM_EAT_FULL_CYC 236 #define POWER8_PME_PM_EE_OFF_EXT_INT 237 #define POWER8_PME_PM_EXT_INT 238 #define POWER8_PME_PM_FAV_TBEGIN 239 #define POWER8_PME_PM_FLOP 240 #define POWER8_PME_PM_FLOP_SUM_SCALAR 241 #define POWER8_PME_PM_FLOP_SUM_VEC 242 #define POWER8_PME_PM_FLUSH 243 #define POWER8_PME_PM_FLUSH_BR_MPRED 244 #define POWER8_PME_PM_FLUSH_COMPLETION 245 #define POWER8_PME_PM_FLUSH_DISP 246 #define POWER8_PME_PM_FLUSH_DISP_SB 247 #define POWER8_PME_PM_FLUSH_DISP_SYNC 248 #define POWER8_PME_PM_FLUSH_DISP_TLBIE 249 #define POWER8_PME_PM_FLUSH_LSU 250 #define POWER8_PME_PM_FLUSH_PARTIAL 251 #define POWER8_PME_PM_FPU0_FCONV 252 #define POWER8_PME_PM_FPU0_FEST 253 #define POWER8_PME_PM_FPU0_FRSP 254 #define POWER8_PME_PM_FPU1_FCONV 255 #define POWER8_PME_PM_FPU1_FEST 256 #define POWER8_PME_PM_FPU1_FRSP 257 #define POWER8_PME_PM_FREQ_DOWN 258 #define POWER8_PME_PM_FREQ_UP 259 #define POWER8_PME_PM_FUSION_TOC_GRP0_1 260 #define POWER8_PME_PM_FUSION_TOC_GRP0_2 261 #define POWER8_PME_PM_FUSION_TOC_GRP0_3 262 #define POWER8_PME_PM_FUSION_TOC_GRP1_1 263 #define POWER8_PME_PM_FUSION_VSX_GRP0_1 264 #define POWER8_PME_PM_FUSION_VSX_GRP0_2 265 #define POWER8_PME_PM_FUSION_VSX_GRP0_3 266 #define POWER8_PME_PM_FUSION_VSX_GRP1_1 267 #define POWER8_PME_PM_FXU0_BUSY_FXU1_IDLE 268 #define POWER8_PME_PM_FXU0_FIN 269 #define POWER8_PME_PM_FXU1_BUSY_FXU0_IDLE 270 #define POWER8_PME_PM_FXU1_FIN 271 #define POWER8_PME_PM_FXU_BUSY 272 #define POWER8_PME_PM_FXU_IDLE 273 #define POWER8_PME_PM_GCT_EMPTY_CYC 274 #define POWER8_PME_PM_GCT_MERGE 275 #define POWER8_PME_PM_GCT_NOSLOT_BR_MPRED 276 #define POWER8_PME_PM_GCT_NOSLOT_BR_MPRED_ICMISS 277 #define POWER8_PME_PM_GCT_NOSLOT_CYC 278 #define POWER8_PME_PM_GCT_NOSLOT_DISP_HELD_ISSQ 279 #define POWER8_PME_PM_GCT_NOSLOT_DISP_HELD_MAP 280 #define POWER8_PME_PM_GCT_NOSLOT_DISP_HELD_OTHER 281 #define POWER8_PME_PM_GCT_NOSLOT_DISP_HELD_SRQ 282 #define POWER8_PME_PM_GCT_NOSLOT_IC_L3MISS 283 #define POWER8_PME_PM_GCT_NOSLOT_IC_MISS 284 #define POWER8_PME_PM_GCT_UTIL_11_14_ENTRIES 285 #define POWER8_PME_PM_GCT_UTIL_15_17_ENTRIES 286 #define POWER8_PME_PM_GCT_UTIL_18_ENTRIES 287 #define POWER8_PME_PM_GCT_UTIL_1_2_ENTRIES 288 #define POWER8_PME_PM_GCT_UTIL_3_6_ENTRIES 289 #define POWER8_PME_PM_GCT_UTIL_7_10_ENTRIES 290 #define POWER8_PME_PM_GRP_BR_MPRED_NONSPEC 291 #define POWER8_PME_PM_GRP_CMPL 292 #define POWER8_PME_PM_GRP_DISP 293 #define POWER8_PME_PM_GRP_IC_MISS_NONSPEC 294 #define POWER8_PME_PM_GRP_MRK 295 #define POWER8_PME_PM_GRP_NON_FULL_GROUP 296 #define POWER8_PME_PM_GRP_PUMP_CPRED 297 #define POWER8_PME_PM_GRP_PUMP_MPRED 298 #define POWER8_PME_PM_GRP_PUMP_MPRED_RTY 299 #define POWER8_PME_PM_GRP_TERM_2ND_BRANCH 300 #define POWER8_PME_PM_GRP_TERM_FPU_AFTER_BR 301 #define POWER8_PME_PM_GRP_TERM_NOINST 302 #define POWER8_PME_PM_GRP_TERM_OTHER 303 #define POWER8_PME_PM_GRP_TERM_SLOT_LIMIT 304 #define POWER8_PME_PM_HV_CYC 305 #define POWER8_PME_PM_IBUF_FULL_CYC 306 #define POWER8_PME_PM_IC_DEMAND_CYC 307 #define POWER8_PME_PM_IC_DEMAND_L2_BHT_REDIRECT 308 #define POWER8_PME_PM_IC_DEMAND_L2_BR_REDIRECT 309 #define POWER8_PME_PM_IC_DEMAND_REQ 310 #define POWER8_PME_PM_IC_INVALIDATE 311 #define POWER8_PME_PM_IC_PREF_CANCEL_HIT 312 #define POWER8_PME_PM_IC_PREF_CANCEL_L2 313 #define POWER8_PME_PM_IC_PREF_CANCEL_PAGE 314 #define POWER8_PME_PM_IC_PREF_REQ 315 #define POWER8_PME_PM_IC_PREF_WRITE 316 #define POWER8_PME_PM_IC_RELOAD_PRIVATE 317 #define POWER8_PME_PM_IERAT_RELOAD 318 #define POWER8_PME_PM_IERAT_RELOAD_16M 319 #define POWER8_PME_PM_IERAT_RELOAD_4K 320 #define POWER8_PME_PM_IERAT_RELOAD_64K 321 #define POWER8_PME_PM_IFETCH_THROTTLE 322 #define POWER8_PME_PM_IFU_L2_TOUCH 323 #define POWER8_PME_PM_INST_ALL_CHIP_PUMP_CPRED 324 #define POWER8_PME_PM_INST_ALL_FROM_DL2L3_MOD 325 #define POWER8_PME_PM_INST_ALL_FROM_DL2L3_SHR 326 #define POWER8_PME_PM_INST_ALL_FROM_DL4 327 #define POWER8_PME_PM_INST_ALL_FROM_DMEM 328 #define POWER8_PME_PM_INST_ALL_FROM_L2 329 #define POWER8_PME_PM_INST_ALL_FROM_L21_MOD 330 #define POWER8_PME_PM_INST_ALL_FROM_L21_SHR 331 #define POWER8_PME_PM_INST_ALL_FROM_L2MISS 332 #define POWER8_PME_PM_INST_ALL_FROM_L2_DISP_CONFLICT_LDHITST 333 #define POWER8_PME_PM_INST_ALL_FROM_L2_DISP_CONFLICT_OTHER 334 #define POWER8_PME_PM_INST_ALL_FROM_L2_MEPF 335 #define POWER8_PME_PM_INST_ALL_FROM_L2_NO_CONFLICT 336 #define POWER8_PME_PM_INST_ALL_FROM_L3 337 #define POWER8_PME_PM_INST_ALL_FROM_L31_ECO_MOD 338 #define POWER8_PME_PM_INST_ALL_FROM_L31_ECO_SHR 339 #define POWER8_PME_PM_INST_ALL_FROM_L31_MOD 340 #define POWER8_PME_PM_INST_ALL_FROM_L31_SHR 341 #define POWER8_PME_PM_INST_ALL_FROM_L3MISS_MOD 342 #define POWER8_PME_PM_INST_ALL_FROM_L3_DISP_CONFLICT 343 #define POWER8_PME_PM_INST_ALL_FROM_L3_MEPF 344 #define POWER8_PME_PM_INST_ALL_FROM_L3_NO_CONFLICT 345 #define POWER8_PME_PM_INST_ALL_FROM_LL4 346 #define POWER8_PME_PM_INST_ALL_FROM_LMEM 347 #define POWER8_PME_PM_INST_ALL_FROM_MEMORY 348 #define POWER8_PME_PM_INST_ALL_FROM_OFF_CHIP_CACHE 349 #define POWER8_PME_PM_INST_ALL_FROM_ON_CHIP_CACHE 350 #define POWER8_PME_PM_INST_ALL_FROM_RL2L3_MOD 351 #define POWER8_PME_PM_INST_ALL_FROM_RL2L3_SHR 352 #define POWER8_PME_PM_INST_ALL_FROM_RL4 353 #define POWER8_PME_PM_INST_ALL_FROM_RMEM 354 #define POWER8_PME_PM_INST_ALL_GRP_PUMP_CPRED 355 #define POWER8_PME_PM_INST_ALL_GRP_PUMP_MPRED 356 #define POWER8_PME_PM_INST_ALL_GRP_PUMP_MPRED_RTY 357 #define POWER8_PME_PM_INST_ALL_PUMP_CPRED 358 #define POWER8_PME_PM_INST_ALL_PUMP_MPRED 359 #define POWER8_PME_PM_INST_ALL_SYS_PUMP_CPRED 360 #define POWER8_PME_PM_INST_ALL_SYS_PUMP_MPRED 361 #define POWER8_PME_PM_INST_ALL_SYS_PUMP_MPRED_RTY 362 #define POWER8_PME_PM_INST_CHIP_PUMP_CPRED 363 #define POWER8_PME_PM_INST_CMPL 364 #define POWER8_PME_PM_INST_DISP 365 #define POWER8_PME_PM_INST_FROM_DL2L3_MOD 366 #define POWER8_PME_PM_INST_FROM_DL2L3_SHR 367 #define POWER8_PME_PM_INST_FROM_DL4 368 #define POWER8_PME_PM_INST_FROM_DMEM 369 #define POWER8_PME_PM_INST_FROM_L1 370 #define POWER8_PME_PM_INST_FROM_L2 371 #define POWER8_PME_PM_INST_FROM_L21_MOD 372 #define POWER8_PME_PM_INST_FROM_L21_SHR 373 #define POWER8_PME_PM_INST_FROM_L2MISS 374 #define POWER8_PME_PM_INST_FROM_L2_DISP_CONFLICT_LDHITST 375 #define POWER8_PME_PM_INST_FROM_L2_DISP_CONFLICT_OTHER 376 #define POWER8_PME_PM_INST_FROM_L2_MEPF 377 #define POWER8_PME_PM_INST_FROM_L2_NO_CONFLICT 378 #define POWER8_PME_PM_INST_FROM_L3 379 #define POWER8_PME_PM_INST_FROM_L31_ECO_MOD 380 #define POWER8_PME_PM_INST_FROM_L31_ECO_SHR 381 #define POWER8_PME_PM_INST_FROM_L31_MOD 382 #define POWER8_PME_PM_INST_FROM_L31_SHR 383 #define POWER8_PME_PM_INST_FROM_L3MISS 384 #define POWER8_PME_PM_INST_FROM_L3MISS_MOD 385 #define POWER8_PME_PM_INST_FROM_L3_DISP_CONFLICT 386 #define POWER8_PME_PM_INST_FROM_L3_MEPF 387 #define POWER8_PME_PM_INST_FROM_L3_NO_CONFLICT 388 #define POWER8_PME_PM_INST_FROM_LL4 389 #define POWER8_PME_PM_INST_FROM_LMEM 390 #define POWER8_PME_PM_INST_FROM_MEMORY 391 #define POWER8_PME_PM_INST_FROM_OFF_CHIP_CACHE 392 #define POWER8_PME_PM_INST_FROM_ON_CHIP_CACHE 393 #define POWER8_PME_PM_INST_FROM_RL2L3_MOD 394 #define POWER8_PME_PM_INST_FROM_RL2L3_SHR 395 #define POWER8_PME_PM_INST_FROM_RL4 396 #define POWER8_PME_PM_INST_FROM_RMEM 397 #define POWER8_PME_PM_INST_GRP_PUMP_CPRED 398 #define POWER8_PME_PM_INST_GRP_PUMP_MPRED 399 #define POWER8_PME_PM_INST_GRP_PUMP_MPRED_RTY 400 #define POWER8_PME_PM_INST_IMC_MATCH_CMPL 401 #define POWER8_PME_PM_INST_IMC_MATCH_DISP 402 #define POWER8_PME_PM_INST_PUMP_CPRED 403 #define POWER8_PME_PM_INST_PUMP_MPRED 404 #define POWER8_PME_PM_INST_SYS_PUMP_CPRED 405 #define POWER8_PME_PM_INST_SYS_PUMP_MPRED 406 #define POWER8_PME_PM_INST_SYS_PUMP_MPRED_RTY 407 #define POWER8_PME_PM_IOPS_CMPL 408 #define POWER8_PME_PM_IOPS_DISP 409 #define POWER8_PME_PM_IPTEG_FROM_DL2L3_MOD 410 #define POWER8_PME_PM_IPTEG_FROM_DL2L3_SHR 411 #define POWER8_PME_PM_IPTEG_FROM_DL4 412 #define POWER8_PME_PM_IPTEG_FROM_DMEM 413 #define POWER8_PME_PM_IPTEG_FROM_L2 414 #define POWER8_PME_PM_IPTEG_FROM_L21_MOD 415 #define POWER8_PME_PM_IPTEG_FROM_L21_SHR 416 #define POWER8_PME_PM_IPTEG_FROM_L2MISS 417 #define POWER8_PME_PM_IPTEG_FROM_L2_DISP_CONFLICT_LDHITST 418 #define POWER8_PME_PM_IPTEG_FROM_L2_DISP_CONFLICT_OTHER 419 #define POWER8_PME_PM_IPTEG_FROM_L2_MEPF 420 #define POWER8_PME_PM_IPTEG_FROM_L2_NO_CONFLICT 421 #define POWER8_PME_PM_IPTEG_FROM_L3 422 #define POWER8_PME_PM_IPTEG_FROM_L31_ECO_MOD 423 #define POWER8_PME_PM_IPTEG_FROM_L31_ECO_SHR 424 #define POWER8_PME_PM_IPTEG_FROM_L31_MOD 425 #define POWER8_PME_PM_IPTEG_FROM_L31_SHR 426 #define POWER8_PME_PM_IPTEG_FROM_L3MISS 427 #define POWER8_PME_PM_IPTEG_FROM_L3_DISP_CONFLICT 428 #define POWER8_PME_PM_IPTEG_FROM_L3_MEPF 429 #define POWER8_PME_PM_IPTEG_FROM_L3_NO_CONFLICT 430 #define POWER8_PME_PM_IPTEG_FROM_LL4 431 #define POWER8_PME_PM_IPTEG_FROM_LMEM 432 #define POWER8_PME_PM_IPTEG_FROM_MEMORY 433 #define POWER8_PME_PM_IPTEG_FROM_OFF_CHIP_CACHE 434 #define POWER8_PME_PM_IPTEG_FROM_ON_CHIP_CACHE 435 #define POWER8_PME_PM_IPTEG_FROM_RL2L3_MOD 436 #define POWER8_PME_PM_IPTEG_FROM_RL2L3_SHR 437 #define POWER8_PME_PM_IPTEG_FROM_RL4 438 #define POWER8_PME_PM_IPTEG_FROM_RMEM 439 #define POWER8_PME_PM_ISIDE_DISP 440 #define POWER8_PME_PM_ISIDE_DISP_FAIL 441 #define POWER8_PME_PM_ISIDE_DISP_FAIL_OTHER 442 #define POWER8_PME_PM_ISIDE_L2MEMACC 443 #define POWER8_PME_PM_ISIDE_MRU_TOUCH 444 #define POWER8_PME_PM_ISLB_MISS 445 #define POWER8_PME_PM_ISU_REF_FX0 446 #define POWER8_PME_PM_ISU_REF_FX1 447 #define POWER8_PME_PM_ISU_REF_FXU 448 #define POWER8_PME_PM_ISU_REF_LS0 449 #define POWER8_PME_PM_ISU_REF_LS1 450 #define POWER8_PME_PM_ISU_REF_LS2 451 #define POWER8_PME_PM_ISU_REF_LS3 452 #define POWER8_PME_PM_ISU_REJECTS_ALL 453 #define POWER8_PME_PM_ISU_REJECT_RES_NA 454 #define POWER8_PME_PM_ISU_REJECT_SAR_BYPASS 455 #define POWER8_PME_PM_ISU_REJECT_SRC_NA 456 #define POWER8_PME_PM_ISU_REJ_VS0 457 #define POWER8_PME_PM_ISU_REJ_VS1 458 #define POWER8_PME_PM_ISU_REJ_VSU 459 #define POWER8_PME_PM_ISYNC 460 #define POWER8_PME_PM_ITLB_MISS 461 #define POWER8_PME_PM_L1MISS_LAT_EXC_1024 462 #define POWER8_PME_PM_L1MISS_LAT_EXC_2048 463 #define POWER8_PME_PM_L1MISS_LAT_EXC_256 464 #define POWER8_PME_PM_L1MISS_LAT_EXC_32 465 #define POWER8_PME_PM_L1PF_L2MEMACC 466 #define POWER8_PME_PM_L1_DCACHE_RELOADED_ALL 467 #define POWER8_PME_PM_L1_DCACHE_RELOAD_VALID 468 #define POWER8_PME_PM_L1_DEMAND_WRITE 469 #define POWER8_PME_PM_L1_ICACHE_MISS 470 #define POWER8_PME_PM_L1_ICACHE_RELOADED_ALL 471 #define POWER8_PME_PM_L1_ICACHE_RELOADED_PREF 472 #define POWER8_PME_PM_L2_CASTOUT_MOD 473 #define POWER8_PME_PM_L2_CASTOUT_SHR 474 #define POWER8_PME_PM_L2_CHIP_PUMP 475 #define POWER8_PME_PM_L2_DC_INV 476 #define POWER8_PME_PM_L2_DISP_ALL_L2MISS 477 #define POWER8_PME_PM_L2_GROUP_PUMP 478 #define POWER8_PME_PM_L2_GRP_GUESS_CORRECT 479 #define POWER8_PME_PM_L2_GRP_GUESS_WRONG 480 #define POWER8_PME_PM_L2_IC_INV 481 #define POWER8_PME_PM_L2_INST 482 #define POWER8_PME_PM_L2_INST_MISS 483 #define POWER8_PME_PM_L2_LD 484 #define POWER8_PME_PM_L2_LD_DISP 485 #define POWER8_PME_PM_L2_LD_HIT 486 #define POWER8_PME_PM_L2_LD_MISS 487 #define POWER8_PME_PM_L2_LOC_GUESS_CORRECT 488 #define POWER8_PME_PM_L2_LOC_GUESS_WRONG 489 #define POWER8_PME_PM_L2_RCLD_DISP 490 #define POWER8_PME_PM_L2_RCLD_DISP_FAIL_ADDR 491 #define POWER8_PME_PM_L2_RCLD_DISP_FAIL_OTHER 492 #define POWER8_PME_PM_L2_RCST_DISP 493 #define POWER8_PME_PM_L2_RCST_DISP_FAIL_ADDR 494 #define POWER8_PME_PM_L2_RCST_DISP_FAIL_OTHER 495 #define POWER8_PME_PM_L2_RC_ST_DONE 496 #define POWER8_PME_PM_L2_RTY_LD 497 #define POWER8_PME_PM_L2_RTY_ST 498 #define POWER8_PME_PM_L2_SN_M_RD_DONE 499 #define POWER8_PME_PM_L2_SN_M_WR_DONE 500 #define POWER8_PME_PM_L2_SN_SX_I_DONE 501 #define POWER8_PME_PM_L2_ST 502 #define POWER8_PME_PM_L2_ST_DISP 503 #define POWER8_PME_PM_L2_ST_HIT 504 #define POWER8_PME_PM_L2_ST_MISS 505 #define POWER8_PME_PM_L2_SYS_GUESS_CORRECT 506 #define POWER8_PME_PM_L2_SYS_GUESS_WRONG 507 #define POWER8_PME_PM_L2_SYS_PUMP 508 #define POWER8_PME_PM_L2_TM_REQ_ABORT 509 #define POWER8_PME_PM_L2_TM_ST_ABORT_SISTER 510 #define POWER8_PME_PM_L3_CINJ 511 #define POWER8_PME_PM_L3_CI_HIT 512 #define POWER8_PME_PM_L3_CI_MISS 513 #define POWER8_PME_PM_L3_CI_USAGE 514 #define POWER8_PME_PM_L3_CO 515 #define POWER8_PME_PM_L3_CO0_ALLOC 516 #define POWER8_PME_PM_L3_CO0_BUSY 517 #define POWER8_PME_PM_L3_CO_L31 518 #define POWER8_PME_PM_L3_CO_LCO 519 #define POWER8_PME_PM_L3_CO_MEM 520 #define POWER8_PME_PM_L3_CO_MEPF 521 #define POWER8_PME_PM_L3_GRP_GUESS_CORRECT 522 #define POWER8_PME_PM_L3_GRP_GUESS_WRONG_HIGH 523 #define POWER8_PME_PM_L3_GRP_GUESS_WRONG_LOW 524 #define POWER8_PME_PM_L3_HIT 525 #define POWER8_PME_PM_L3_L2_CO_HIT 526 #define POWER8_PME_PM_L3_L2_CO_MISS 527 #define POWER8_PME_PM_L3_LAT_CI_HIT 528 #define POWER8_PME_PM_L3_LAT_CI_MISS 529 #define POWER8_PME_PM_L3_LD_HIT 530 #define POWER8_PME_PM_L3_LD_MISS 531 #define POWER8_PME_PM_L3_LD_PREF 532 #define POWER8_PME_PM_L3_LOC_GUESS_CORRECT 533 #define POWER8_PME_PM_L3_LOC_GUESS_WRONG 534 #define POWER8_PME_PM_L3_MISS 535 #define POWER8_PME_PM_L3_P0_CO_L31 536 #define POWER8_PME_PM_L3_P0_CO_MEM 537 #define POWER8_PME_PM_L3_P0_CO_RTY 538 #define POWER8_PME_PM_L3_P0_GRP_PUMP 539 #define POWER8_PME_PM_L3_P0_LCO_DATA 540 #define POWER8_PME_PM_L3_P0_LCO_NO_DATA 541 #define POWER8_PME_PM_L3_P0_LCO_RTY 542 #define POWER8_PME_PM_L3_P0_NODE_PUMP 543 #define POWER8_PME_PM_L3_P0_PF_RTY 544 #define POWER8_PME_PM_L3_P0_SN_HIT 545 #define POWER8_PME_PM_L3_P0_SN_INV 546 #define POWER8_PME_PM_L3_P0_SN_MISS 547 #define POWER8_PME_PM_L3_P0_SYS_PUMP 548 #define POWER8_PME_PM_L3_P1_CO_L31 549 #define POWER8_PME_PM_L3_P1_CO_MEM 550 #define POWER8_PME_PM_L3_P1_CO_RTY 551 #define POWER8_PME_PM_L3_P1_GRP_PUMP 552 #define POWER8_PME_PM_L3_P1_LCO_DATA 553 #define POWER8_PME_PM_L3_P1_LCO_NO_DATA 554 #define POWER8_PME_PM_L3_P1_LCO_RTY 555 #define POWER8_PME_PM_L3_P1_NODE_PUMP 556 #define POWER8_PME_PM_L3_P1_PF_RTY 557 #define POWER8_PME_PM_L3_P1_SN_HIT 558 #define POWER8_PME_PM_L3_P1_SN_INV 559 #define POWER8_PME_PM_L3_P1_SN_MISS 560 #define POWER8_PME_PM_L3_P1_SYS_PUMP 561 #define POWER8_PME_PM_L3_PF0_ALLOC 562 #define POWER8_PME_PM_L3_PF0_BUSY 563 #define POWER8_PME_PM_L3_PF_HIT_L3 564 #define POWER8_PME_PM_L3_PF_MISS_L3 565 #define POWER8_PME_PM_L3_PF_OFF_CHIP_CACHE 566 #define POWER8_PME_PM_L3_PF_OFF_CHIP_MEM 567 #define POWER8_PME_PM_L3_PF_ON_CHIP_CACHE 568 #define POWER8_PME_PM_L3_PF_ON_CHIP_MEM 569 #define POWER8_PME_PM_L3_PF_USAGE 570 #define POWER8_PME_PM_L3_PREF_ALL 571 #define POWER8_PME_PM_L3_RD0_ALLOC 572 #define POWER8_PME_PM_L3_RD0_BUSY 573 #define POWER8_PME_PM_L3_RD_USAGE 574 #define POWER8_PME_PM_L3_SN0_ALLOC 575 #define POWER8_PME_PM_L3_SN0_BUSY 576 #define POWER8_PME_PM_L3_SN_USAGE 577 #define POWER8_PME_PM_L3_ST_PREF 578 #define POWER8_PME_PM_L3_SW_PREF 579 #define POWER8_PME_PM_L3_SYS_GUESS_CORRECT 580 #define POWER8_PME_PM_L3_SYS_GUESS_WRONG 581 #define POWER8_PME_PM_L3_TRANS_PF 582 #define POWER8_PME_PM_L3_WI0_ALLOC 583 #define POWER8_PME_PM_L3_WI0_BUSY 584 #define POWER8_PME_PM_L3_WI_USAGE 585 #define POWER8_PME_PM_LARX_FIN 586 #define POWER8_PME_PM_LD_CMPL 587 #define POWER8_PME_PM_LD_L3MISS_PEND_CYC 588 #define POWER8_PME_PM_LD_MISS_L1 589 #define POWER8_PME_PM_LD_REF_L1 590 #define POWER8_PME_PM_LD_REF_L1_LSU0 591 #define POWER8_PME_PM_LD_REF_L1_LSU1 592 #define POWER8_PME_PM_LD_REF_L1_LSU2 593 #define POWER8_PME_PM_LD_REF_L1_LSU3 594 #define POWER8_PME_PM_LINK_STACK_INVALID_PTR 595 #define POWER8_PME_PM_LINK_STACK_WRONG_ADD_PRED 596 #define POWER8_PME_PM_LS0_ERAT_MISS_PREF 597 #define POWER8_PME_PM_LS0_L1_PREF 598 #define POWER8_PME_PM_LS0_L1_SW_PREF 599 #define POWER8_PME_PM_LS1_ERAT_MISS_PREF 600 #define POWER8_PME_PM_LS1_L1_PREF 601 #define POWER8_PME_PM_LS1_L1_SW_PREF 602 #define POWER8_PME_PM_LSU0_FLUSH_LRQ 603 #define POWER8_PME_PM_LSU0_FLUSH_SRQ 604 #define POWER8_PME_PM_LSU0_FLUSH_ULD 605 #define POWER8_PME_PM_LSU0_FLUSH_UST 606 #define POWER8_PME_PM_LSU0_L1_CAM_CANCEL 607 #define POWER8_PME_PM_LSU0_LARX_FIN 608 #define POWER8_PME_PM_LSU0_LMQ_LHR_MERGE 609 #define POWER8_PME_PM_LSU0_NCLD 610 #define POWER8_PME_PM_LSU0_PRIMARY_ERAT_HIT 611 #define POWER8_PME_PM_LSU0_REJECT 612 #define POWER8_PME_PM_LSU0_SRQ_STFWD 613 #define POWER8_PME_PM_LSU0_STORE_REJECT 614 #define POWER8_PME_PM_LSU0_TMA_REQ_L2 615 #define POWER8_PME_PM_LSU0_TM_L1_HIT 616 #define POWER8_PME_PM_LSU0_TM_L1_MISS 617 #define POWER8_PME_PM_LSU1_FLUSH_LRQ 618 #define POWER8_PME_PM_LSU1_FLUSH_SRQ 619 #define POWER8_PME_PM_LSU1_FLUSH_ULD 620 #define POWER8_PME_PM_LSU1_FLUSH_UST 621 #define POWER8_PME_PM_LSU1_L1_CAM_CANCEL 622 #define POWER8_PME_PM_LSU1_LARX_FIN 623 #define POWER8_PME_PM_LSU1_LMQ_LHR_MERGE 624 #define POWER8_PME_PM_LSU1_NCLD 625 #define POWER8_PME_PM_LSU1_PRIMARY_ERAT_HIT 626 #define POWER8_PME_PM_LSU1_REJECT 627 #define POWER8_PME_PM_LSU1_SRQ_STFWD 628 #define POWER8_PME_PM_LSU1_STORE_REJECT 629 #define POWER8_PME_PM_LSU1_TMA_REQ_L2 630 #define POWER8_PME_PM_LSU1_TM_L1_HIT 631 #define POWER8_PME_PM_LSU1_TM_L1_MISS 632 #define POWER8_PME_PM_LSU2_FLUSH_LRQ 633 #define POWER8_PME_PM_LSU2_FLUSH_SRQ 634 #define POWER8_PME_PM_LSU2_FLUSH_ULD 635 #define POWER8_PME_PM_LSU2_L1_CAM_CANCEL 636 #define POWER8_PME_PM_LSU2_LARX_FIN 637 #define POWER8_PME_PM_LSU2_LDF 638 #define POWER8_PME_PM_LSU2_LDX 639 #define POWER8_PME_PM_LSU2_LMQ_LHR_MERGE 640 #define POWER8_PME_PM_LSU2_PRIMARY_ERAT_HIT 641 #define POWER8_PME_PM_LSU2_REJECT 642 #define POWER8_PME_PM_LSU2_SRQ_STFWD 643 #define POWER8_PME_PM_LSU2_TMA_REQ_L2 644 #define POWER8_PME_PM_LSU2_TM_L1_HIT 645 #define POWER8_PME_PM_LSU2_TM_L1_MISS 646 #define POWER8_PME_PM_LSU3_FLUSH_LRQ 647 #define POWER8_PME_PM_LSU3_FLUSH_SRQ 648 #define POWER8_PME_PM_LSU3_FLUSH_ULD 649 #define POWER8_PME_PM_LSU3_L1_CAM_CANCEL 650 #define POWER8_PME_PM_LSU3_LARX_FIN 651 #define POWER8_PME_PM_LSU3_LDF 652 #define POWER8_PME_PM_LSU3_LDX 653 #define POWER8_PME_PM_LSU3_LMQ_LHR_MERGE 654 #define POWER8_PME_PM_LSU3_PRIMARY_ERAT_HIT 655 #define POWER8_PME_PM_LSU3_REJECT 656 #define POWER8_PME_PM_LSU3_SRQ_STFWD 657 #define POWER8_PME_PM_LSU3_TMA_REQ_L2 658 #define POWER8_PME_PM_LSU3_TM_L1_HIT 659 #define POWER8_PME_PM_LSU3_TM_L1_MISS 660 #define POWER8_PME_PM_LSU_DERAT_MISS 661 #define POWER8_PME_PM_LSU_ERAT_MISS_PREF 662 #define POWER8_PME_PM_LSU_FIN 663 #define POWER8_PME_PM_LSU_FLUSH_UST 664 #define POWER8_PME_PM_LSU_FOUR_TABLEWALK_CYC 665 #define POWER8_PME_PM_LSU_FX_FIN 666 #define POWER8_PME_PM_LSU_L1_PREF 667 #define POWER8_PME_PM_LSU_L1_SW_PREF 668 #define POWER8_PME_PM_LSU_LDF 669 #define POWER8_PME_PM_LSU_LDX 670 #define POWER8_PME_PM_LSU_LMQ_FULL_CYC 671 #define POWER8_PME_PM_LSU_LMQ_S0_ALLOC 672 #define POWER8_PME_PM_LSU_LMQ_S0_VALID 673 #define POWER8_PME_PM_LSU_LMQ_SRQ_EMPTY_ALL_CYC 674 #define POWER8_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC 675 #define POWER8_PME_PM_LSU_LRQ_S0_ALLOC 676 #define POWER8_PME_PM_LSU_LRQ_S0_VALID 677 #define POWER8_PME_PM_LSU_LRQ_S43_ALLOC 678 #define POWER8_PME_PM_LSU_LRQ_S43_VALID 679 #define POWER8_PME_PM_LSU_MRK_DERAT_MISS 680 #define POWER8_PME_PM_LSU_NCLD 681 #define POWER8_PME_PM_LSU_NCST 682 #define POWER8_PME_PM_LSU_REJECT 683 #define POWER8_PME_PM_LSU_REJECT_ERAT_MISS 684 #define POWER8_PME_PM_LSU_REJECT_LHS 685 #define POWER8_PME_PM_LSU_REJECT_LMQ_FULL 686 #define POWER8_PME_PM_LSU_SET_MPRED 687 #define POWER8_PME_PM_LSU_SRQ_EMPTY_CYC 688 #define POWER8_PME_PM_LSU_SRQ_FULL_CYC 689 #define POWER8_PME_PM_LSU_SRQ_S0_ALLOC 690 #define POWER8_PME_PM_LSU_SRQ_S0_VALID 691 #define POWER8_PME_PM_LSU_SRQ_S39_ALLOC 692 #define POWER8_PME_PM_LSU_SRQ_S39_VALID 693 #define POWER8_PME_PM_LSU_SRQ_SYNC 694 #define POWER8_PME_PM_LSU_SRQ_SYNC_CYC 695 #define POWER8_PME_PM_LSU_STORE_REJECT 696 #define POWER8_PME_PM_LSU_TWO_TABLEWALK_CYC 697 #define POWER8_PME_PM_LWSYNC 698 #define POWER8_PME_PM_LWSYNC_HELD 699 #define POWER8_PME_PM_MEM_CO 700 #define POWER8_PME_PM_MEM_LOC_THRESH_IFU 701 #define POWER8_PME_PM_MEM_LOC_THRESH_LSU_HIGH 702 #define POWER8_PME_PM_MEM_LOC_THRESH_LSU_MED 703 #define POWER8_PME_PM_MEM_PREF 704 #define POWER8_PME_PM_MEM_READ 705 #define POWER8_PME_PM_MEM_RWITM 706 #define POWER8_PME_PM_MRK_BACK_BR_CMPL 707 #define POWER8_PME_PM_MRK_BRU_FIN 708 #define POWER8_PME_PM_MRK_BR_CMPL 709 #define POWER8_PME_PM_MRK_BR_MPRED_CMPL 710 #define POWER8_PME_PM_MRK_BR_TAKEN_CMPL 711 #define POWER8_PME_PM_MRK_CRU_FIN 712 #define POWER8_PME_PM_MRK_DATA_FROM_DL2L3_MOD 713 #define POWER8_PME_PM_MRK_DATA_FROM_DL2L3_MOD_CYC 714 #define POWER8_PME_PM_MRK_DATA_FROM_DL2L3_SHR 715 #define POWER8_PME_PM_MRK_DATA_FROM_DL2L3_SHR_CYC 716 #define POWER8_PME_PM_MRK_DATA_FROM_DL4 717 #define POWER8_PME_PM_MRK_DATA_FROM_DL4_CYC 718 #define POWER8_PME_PM_MRK_DATA_FROM_DMEM 719 #define POWER8_PME_PM_MRK_DATA_FROM_DMEM_CYC 720 #define POWER8_PME_PM_MRK_DATA_FROM_L2 721 #define POWER8_PME_PM_MRK_DATA_FROM_L21_MOD 722 #define POWER8_PME_PM_MRK_DATA_FROM_L21_MOD_CYC 723 #define POWER8_PME_PM_MRK_DATA_FROM_L21_SHR 724 #define POWER8_PME_PM_MRK_DATA_FROM_L21_SHR_CYC 725 #define POWER8_PME_PM_MRK_DATA_FROM_L2MISS 726 #define POWER8_PME_PM_MRK_DATA_FROM_L2MISS_CYC 727 #define POWER8_PME_PM_MRK_DATA_FROM_L2_CYC 728 #define POWER8_PME_PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST 729 #define POWER8_PME_PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST_CYC 730 #define POWER8_PME_PM_MRK_DATA_FROM_L2_DISP_CONFLICT_OTHER 731 #define POWER8_PME_PM_MRK_DATA_FROM_L2_DISP_CONFLICT_OTHER_CYC 732 #define POWER8_PME_PM_MRK_DATA_FROM_L2_MEPF 733 #define POWER8_PME_PM_MRK_DATA_FROM_L2_MEPF_CYC 734 #define POWER8_PME_PM_MRK_DATA_FROM_L2_NO_CONFLICT 735 #define POWER8_PME_PM_MRK_DATA_FROM_L2_NO_CONFLICT_CYC 736 #define POWER8_PME_PM_MRK_DATA_FROM_L3 737 #define POWER8_PME_PM_MRK_DATA_FROM_L31_ECO_MOD 738 #define POWER8_PME_PM_MRK_DATA_FROM_L31_ECO_MOD_CYC 739 #define POWER8_PME_PM_MRK_DATA_FROM_L31_ECO_SHR 740 #define POWER8_PME_PM_MRK_DATA_FROM_L31_ECO_SHR_CYC 741 #define POWER8_PME_PM_MRK_DATA_FROM_L31_MOD 742 #define POWER8_PME_PM_MRK_DATA_FROM_L31_MOD_CYC 743 #define POWER8_PME_PM_MRK_DATA_FROM_L31_SHR 744 #define POWER8_PME_PM_MRK_DATA_FROM_L31_SHR_CYC 745 #define POWER8_PME_PM_MRK_DATA_FROM_L3MISS 746 #define POWER8_PME_PM_MRK_DATA_FROM_L3MISS_CYC 747 #define POWER8_PME_PM_MRK_DATA_FROM_L3_CYC 748 #define POWER8_PME_PM_MRK_DATA_FROM_L3_DISP_CONFLICT 749 #define POWER8_PME_PM_MRK_DATA_FROM_L3_DISP_CONFLICT_CYC 750 #define POWER8_PME_PM_MRK_DATA_FROM_L3_MEPF 751 #define POWER8_PME_PM_MRK_DATA_FROM_L3_MEPF_CYC 752 #define POWER8_PME_PM_MRK_DATA_FROM_L3_NO_CONFLICT 753 #define POWER8_PME_PM_MRK_DATA_FROM_L3_NO_CONFLICT_CYC 754 #define POWER8_PME_PM_MRK_DATA_FROM_LL4 755 #define POWER8_PME_PM_MRK_DATA_FROM_LL4_CYC 756 #define POWER8_PME_PM_MRK_DATA_FROM_LMEM 757 #define POWER8_PME_PM_MRK_DATA_FROM_LMEM_CYC 758 #define POWER8_PME_PM_MRK_DATA_FROM_MEM 759 #define POWER8_PME_PM_MRK_DATA_FROM_MEMORY 760 #define POWER8_PME_PM_MRK_DATA_FROM_MEMORY_CYC 761 #define POWER8_PME_PM_MRK_DATA_FROM_OFF_CHIP_CACHE 762 #define POWER8_PME_PM_MRK_DATA_FROM_OFF_CHIP_CACHE_CYC 763 #define POWER8_PME_PM_MRK_DATA_FROM_ON_CHIP_CACHE 764 #define POWER8_PME_PM_MRK_DATA_FROM_ON_CHIP_CACHE_CYC 765 #define POWER8_PME_PM_MRK_DATA_FROM_RL2L3_MOD 766 #define POWER8_PME_PM_MRK_DATA_FROM_RL2L3_MOD_CYC 767 #define POWER8_PME_PM_MRK_DATA_FROM_RL2L3_SHR 768 #define POWER8_PME_PM_MRK_DATA_FROM_RL2L3_SHR_CYC 769 #define POWER8_PME_PM_MRK_DATA_FROM_RL4 770 #define POWER8_PME_PM_MRK_DATA_FROM_RL4_CYC 771 #define POWER8_PME_PM_MRK_DATA_FROM_RMEM 772 #define POWER8_PME_PM_MRK_DATA_FROM_RMEM_CYC 773 #define POWER8_PME_PM_MRK_DCACHE_RELOAD_INTV 774 #define POWER8_PME_PM_MRK_DERAT_MISS 775 #define POWER8_PME_PM_MRK_DERAT_MISS_16G 776 #define POWER8_PME_PM_MRK_DERAT_MISS_16M 777 #define POWER8_PME_PM_MRK_DERAT_MISS_4K 778 #define POWER8_PME_PM_MRK_DERAT_MISS_64K 779 #define POWER8_PME_PM_MRK_DFU_FIN 780 #define POWER8_PME_PM_MRK_DPTEG_FROM_DL2L3_MOD 781 #define POWER8_PME_PM_MRK_DPTEG_FROM_DL2L3_SHR 782 #define POWER8_PME_PM_MRK_DPTEG_FROM_DL4 783 #define POWER8_PME_PM_MRK_DPTEG_FROM_DMEM 784 #define POWER8_PME_PM_MRK_DPTEG_FROM_L2 785 #define POWER8_PME_PM_MRK_DPTEG_FROM_L21_MOD 786 #define POWER8_PME_PM_MRK_DPTEG_FROM_L21_SHR 787 #define POWER8_PME_PM_MRK_DPTEG_FROM_L2MISS 788 #define POWER8_PME_PM_MRK_DPTEG_FROM_L2_DISP_CONFLICT_LDHITST 789 #define POWER8_PME_PM_MRK_DPTEG_FROM_L2_DISP_CONFLICT_OTHER 790 #define POWER8_PME_PM_MRK_DPTEG_FROM_L2_MEPF 791 #define POWER8_PME_PM_MRK_DPTEG_FROM_L2_NO_CONFLICT 792 #define POWER8_PME_PM_MRK_DPTEG_FROM_L3 793 #define POWER8_PME_PM_MRK_DPTEG_FROM_L31_ECO_MOD 794 #define POWER8_PME_PM_MRK_DPTEG_FROM_L31_ECO_SHR 795 #define POWER8_PME_PM_MRK_DPTEG_FROM_L31_MOD 796 #define POWER8_PME_PM_MRK_DPTEG_FROM_L31_SHR 797 #define POWER8_PME_PM_MRK_DPTEG_FROM_L3MISS 798 #define POWER8_PME_PM_MRK_DPTEG_FROM_L3_DISP_CONFLICT 799 #define POWER8_PME_PM_MRK_DPTEG_FROM_L3_MEPF 800 #define POWER8_PME_PM_MRK_DPTEG_FROM_L3_NO_CONFLICT 801 #define POWER8_PME_PM_MRK_DPTEG_FROM_LL4 802 #define POWER8_PME_PM_MRK_DPTEG_FROM_LMEM 803 #define POWER8_PME_PM_MRK_DPTEG_FROM_MEMORY 804 #define POWER8_PME_PM_MRK_DPTEG_FROM_OFF_CHIP_CACHE 805 #define POWER8_PME_PM_MRK_DPTEG_FROM_ON_CHIP_CACHE 806 #define POWER8_PME_PM_MRK_DPTEG_FROM_RL2L3_MOD 807 #define POWER8_PME_PM_MRK_DPTEG_FROM_RL2L3_SHR 808 #define POWER8_PME_PM_MRK_DPTEG_FROM_RL4 809 #define POWER8_PME_PM_MRK_DPTEG_FROM_RMEM 810 #define POWER8_PME_PM_MRK_DTLB_MISS 811 #define POWER8_PME_PM_MRK_DTLB_MISS_16G 812 #define POWER8_PME_PM_MRK_DTLB_MISS_16M 813 #define POWER8_PME_PM_MRK_DTLB_MISS_4K 814 #define POWER8_PME_PM_MRK_DTLB_MISS_64K 815 #define POWER8_PME_PM_MRK_FAB_RSP_BKILL 816 #define POWER8_PME_PM_MRK_FAB_RSP_BKILL_CYC 817 #define POWER8_PME_PM_MRK_FAB_RSP_CLAIM_RTY 818 #define POWER8_PME_PM_MRK_FAB_RSP_DCLAIM 819 #define POWER8_PME_PM_MRK_FAB_RSP_DCLAIM_CYC 820 #define POWER8_PME_PM_MRK_FAB_RSP_MATCH 821 #define POWER8_PME_PM_MRK_FAB_RSP_MATCH_CYC 822 #define POWER8_PME_PM_MRK_FAB_RSP_RD_RTY 823 #define POWER8_PME_PM_MRK_FAB_RSP_RD_T_INTV 824 #define POWER8_PME_PM_MRK_FAB_RSP_RWITM_CYC 825 #define POWER8_PME_PM_MRK_FAB_RSP_RWITM_RTY 826 #define POWER8_PME_PM_MRK_FILT_MATCH 827 #define POWER8_PME_PM_MRK_FIN_STALL_CYC 828 #define POWER8_PME_PM_MRK_FXU_FIN 829 #define POWER8_PME_PM_MRK_GRP_CMPL 830 #define POWER8_PME_PM_MRK_GRP_IC_MISS 831 #define POWER8_PME_PM_MRK_GRP_NTC 832 #define POWER8_PME_PM_MRK_INST_CMPL 833 #define POWER8_PME_PM_MRK_INST_DECODED 834 #define POWER8_PME_PM_MRK_INST_DISP 835 #define POWER8_PME_PM_MRK_INST_FIN 836 #define POWER8_PME_PM_MRK_INST_FROM_L3MISS 837 #define POWER8_PME_PM_MRK_INST_ISSUED 838 #define POWER8_PME_PM_MRK_INST_TIMEO 839 #define POWER8_PME_PM_MRK_L1_ICACHE_MISS 840 #define POWER8_PME_PM_MRK_L1_RELOAD_VALID 841 #define POWER8_PME_PM_MRK_L2_RC_DISP 842 #define POWER8_PME_PM_MRK_L2_RC_DONE 843 #define POWER8_PME_PM_MRK_LARX_FIN 844 #define POWER8_PME_PM_MRK_LD_MISS_EXPOSED 845 #define POWER8_PME_PM_MRK_LD_MISS_EXPOSED_CYC 846 #define POWER8_PME_PM_MRK_LD_MISS_L1 847 #define POWER8_PME_PM_MRK_LD_MISS_L1_CYC 848 #define POWER8_PME_PM_MRK_LSU_FIN 849 #define POWER8_PME_PM_MRK_LSU_FLUSH 850 #define POWER8_PME_PM_MRK_LSU_FLUSH_LRQ 851 #define POWER8_PME_PM_MRK_LSU_FLUSH_SRQ 852 #define POWER8_PME_PM_MRK_LSU_FLUSH_ULD 853 #define POWER8_PME_PM_MRK_LSU_FLUSH_UST 854 #define POWER8_PME_PM_MRK_LSU_REJECT 855 #define POWER8_PME_PM_MRK_LSU_REJECT_ERAT_MISS 856 #define POWER8_PME_PM_MRK_NTF_FIN 857 #define POWER8_PME_PM_MRK_RUN_CYC 858 #define POWER8_PME_PM_MRK_SRC_PREF_TRACK_EFF 859 #define POWER8_PME_PM_MRK_SRC_PREF_TRACK_INEFF 860 #define POWER8_PME_PM_MRK_SRC_PREF_TRACK_MOD 861 #define POWER8_PME_PM_MRK_SRC_PREF_TRACK_MOD_L2 862 #define POWER8_PME_PM_MRK_SRC_PREF_TRACK_MOD_L3 863 #define POWER8_PME_PM_MRK_STALL_CMPLU_CYC 864 #define POWER8_PME_PM_MRK_STCX_FAIL 865 #define POWER8_PME_PM_MRK_ST_CMPL 866 #define POWER8_PME_PM_MRK_ST_CMPL_INT 867 #define POWER8_PME_PM_MRK_ST_DRAIN_TO_L2DISP_CYC 868 #define POWER8_PME_PM_MRK_ST_FWD 869 #define POWER8_PME_PM_MRK_ST_L2DISP_TO_CMPL_CYC 870 #define POWER8_PME_PM_MRK_ST_NEST 871 #define POWER8_PME_PM_MRK_TGT_PREF_TRACK_EFF 872 #define POWER8_PME_PM_MRK_TGT_PREF_TRACK_INEFF 873 #define POWER8_PME_PM_MRK_TGT_PREF_TRACK_MOD 874 #define POWER8_PME_PM_MRK_TGT_PREF_TRACK_MOD_L2 875 #define POWER8_PME_PM_MRK_TGT_PREF_TRACK_MOD_L3 876 #define POWER8_PME_PM_MRK_VSU_FIN 877 #define POWER8_PME_PM_MULT_MRK 878 #define POWER8_PME_PM_NESTED_TEND 879 #define POWER8_PME_PM_NEST_REF_CLK 880 #define POWER8_PME_PM_NON_FAV_TBEGIN 881 #define POWER8_PME_PM_NON_TM_RST_SC 882 #define POWER8_PME_PM_NTCG_ALL_FIN 883 #define POWER8_PME_PM_OUTER_TBEGIN 884 #define POWER8_PME_PM_OUTER_TEND 885 #define POWER8_PME_PM_PMC1_OVERFLOW 886 #define POWER8_PME_PM_PMC2_OVERFLOW 887 #define POWER8_PME_PM_PMC2_REWIND 888 #define POWER8_PME_PM_PMC2_SAVED 889 #define POWER8_PME_PM_PMC3_OVERFLOW 890 #define POWER8_PME_PM_PMC4_OVERFLOW 891 #define POWER8_PME_PM_PMC4_REWIND 892 #define POWER8_PME_PM_PMC4_SAVED 893 #define POWER8_PME_PM_PMC5_OVERFLOW 894 #define POWER8_PME_PM_PMC6_OVERFLOW 895 #define POWER8_PME_PM_PREF_TRACKED 896 #define POWER8_PME_PM_PREF_TRACK_EFF 897 #define POWER8_PME_PM_PREF_TRACK_INEFF 898 #define POWER8_PME_PM_PREF_TRACK_MOD 899 #define POWER8_PME_PM_PREF_TRACK_MOD_L2 900 #define POWER8_PME_PM_PREF_TRACK_MOD_L3 901 #define POWER8_PME_PM_PROBE_NOP_DISP 902 #define POWER8_PME_PM_PTE_PREFETCH 903 #define POWER8_PME_PM_PUMP_CPRED 904 #define POWER8_PME_PM_PUMP_MPRED 905 #define POWER8_PME_PM_RC0_ALLOC 906 #define POWER8_PME_PM_RC0_BUSY 907 #define POWER8_PME_PM_RC_LIFETIME_EXC_1024 908 #define POWER8_PME_PM_RC_LIFETIME_EXC_2048 909 #define POWER8_PME_PM_RC_LIFETIME_EXC_256 910 #define POWER8_PME_PM_RC_LIFETIME_EXC_32 911 #define POWER8_PME_PM_RC_USAGE 912 #define POWER8_PME_PM_RD_CLEARING_SC 913 #define POWER8_PME_PM_RD_FORMING_SC 914 #define POWER8_PME_PM_RD_HIT_PF 915 #define POWER8_PME_PM_REAL_SRQ_FULL 916 #define POWER8_PME_PM_RUN_CYC 917 #define POWER8_PME_PM_RUN_CYC_SMT2_MODE 918 #define POWER8_PME_PM_RUN_CYC_SMT2_SHRD_MODE 919 #define POWER8_PME_PM_RUN_CYC_SMT2_SPLIT_MODE 920 #define POWER8_PME_PM_RUN_CYC_SMT4_MODE 921 #define POWER8_PME_PM_RUN_CYC_SMT8_MODE 922 #define POWER8_PME_PM_RUN_CYC_ST_MODE 923 #define POWER8_PME_PM_RUN_INST_CMPL 924 #define POWER8_PME_PM_RUN_PURR 925 #define POWER8_PME_PM_RUN_SPURR 926 #define POWER8_PME_PM_SEC_ERAT_HIT 927 #define POWER8_PME_PM_SHL_CREATED 928 #define POWER8_PME_PM_SHL_ST_CONVERT 929 #define POWER8_PME_PM_SHL_ST_DISABLE 930 #define POWER8_PME_PM_SN0_ALLOC 931 #define POWER8_PME_PM_SN0_BUSY 932 #define POWER8_PME_PM_SNOOP_TLBIE 933 #define POWER8_PME_PM_SNP_TM_HIT_M 934 #define POWER8_PME_PM_SNP_TM_HIT_T 935 #define POWER8_PME_PM_SN_USAGE 936 #define POWER8_PME_PM_STALL_END_GCT_EMPTY 937 #define POWER8_PME_PM_STCX_FAIL 938 #define POWER8_PME_PM_STCX_LSU 939 #define POWER8_PME_PM_ST_CAUSED_FAIL 940 #define POWER8_PME_PM_ST_CMPL 941 #define POWER8_PME_PM_ST_FIN 942 #define POWER8_PME_PM_ST_FWD 943 #define POWER8_PME_PM_ST_MISS_L1 944 #define POWER8_PME_PM_SUSPENDED 945 #define POWER8_PME_PM_SWAP_CANCEL 946 #define POWER8_PME_PM_SWAP_CANCEL_GPR 947 #define POWER8_PME_PM_SWAP_COMPLETE 948 #define POWER8_PME_PM_SWAP_COMPLETE_GPR 949 #define POWER8_PME_PM_SYNC_MRK_BR_LINK 950 #define POWER8_PME_PM_SYNC_MRK_BR_MPRED 951 #define POWER8_PME_PM_SYNC_MRK_FX_DIVIDE 952 #define POWER8_PME_PM_SYNC_MRK_L2HIT 953 #define POWER8_PME_PM_SYNC_MRK_L2MISS 954 #define POWER8_PME_PM_SYNC_MRK_L3MISS 955 #define POWER8_PME_PM_SYNC_MRK_PROBE_NOP 956 #define POWER8_PME_PM_SYS_PUMP_CPRED 957 #define POWER8_PME_PM_SYS_PUMP_MPRED 958 #define POWER8_PME_PM_SYS_PUMP_MPRED_RTY 959 #define POWER8_PME_PM_TABLEWALK_CYC 960 #define POWER8_PME_PM_TABLEWALK_CYC_PREF 961 #define POWER8_PME_PM_TABORT_TRECLAIM 962 #define POWER8_PME_PM_TB_BIT_TRANS 963 #define POWER8_PME_PM_TEND_PEND_CYC 964 #define POWER8_PME_PM_THRD_ALL_RUN_CYC 965 #define POWER8_PME_PM_THRD_CONC_RUN_INST 966 #define POWER8_PME_PM_THRD_GRP_CMPL_BOTH_CYC 967 #define POWER8_PME_PM_THRD_PRIO_0_1_CYC 968 #define POWER8_PME_PM_THRD_PRIO_2_3_CYC 969 #define POWER8_PME_PM_THRD_PRIO_4_5_CYC 970 #define POWER8_PME_PM_THRD_PRIO_6_7_CYC 971 #define POWER8_PME_PM_THRD_REBAL_CYC 972 #define POWER8_PME_PM_THRESH_EXC_1024 973 #define POWER8_PME_PM_THRESH_EXC_128 974 #define POWER8_PME_PM_THRESH_EXC_2048 975 #define POWER8_PME_PM_THRESH_EXC_256 976 #define POWER8_PME_PM_THRESH_EXC_32 977 #define POWER8_PME_PM_THRESH_EXC_4096 978 #define POWER8_PME_PM_THRESH_EXC_512 979 #define POWER8_PME_PM_THRESH_EXC_64 980 #define POWER8_PME_PM_THRESH_MET 981 #define POWER8_PME_PM_THRESH_NOT_MET 982 #define POWER8_PME_PM_TLBIE_FIN 983 #define POWER8_PME_PM_TLB_MISS 984 #define POWER8_PME_PM_TM_BEGIN_ALL 985 #define POWER8_PME_PM_TM_CAM_OVERFLOW 986 #define POWER8_PME_PM_TM_CAP_OVERFLOW 987 #define POWER8_PME_PM_TM_END_ALL 988 #define POWER8_PME_PM_TM_FAIL_CONF_NON_TM 989 #define POWER8_PME_PM_TM_FAIL_CON_TM 990 #define POWER8_PME_PM_TM_FAIL_DISALLOW 991 #define POWER8_PME_PM_TM_FAIL_FOOTPRINT_OVERFLOW 992 #define POWER8_PME_PM_TM_FAIL_NON_TX_CONFLICT 993 #define POWER8_PME_PM_TM_FAIL_SELF 994 #define POWER8_PME_PM_TM_FAIL_TLBIE 995 #define POWER8_PME_PM_TM_FAIL_TX_CONFLICT 996 #define POWER8_PME_PM_TM_FAV_CAUSED_FAIL 997 #define POWER8_PME_PM_TM_LD_CAUSED_FAIL 998 #define POWER8_PME_PM_TM_LD_CONF 999 #define POWER8_PME_PM_TM_RST_SC 1000 #define POWER8_PME_PM_TM_SC_CO 1001 #define POWER8_PME_PM_TM_ST_CAUSED_FAIL 1002 #define POWER8_PME_PM_TM_ST_CONF 1003 #define POWER8_PME_PM_TM_TBEGIN 1004 #define POWER8_PME_PM_TM_TRANS_RUN_CYC 1005 #define POWER8_PME_PM_TM_TRANS_RUN_INST 1006 #define POWER8_PME_PM_TM_TRESUME 1007 #define POWER8_PME_PM_TM_TSUSPEND 1008 #define POWER8_PME_PM_TM_TX_PASS_RUN_CYC 1009 #define POWER8_PME_PM_TM_TX_PASS_RUN_INST 1010 #define POWER8_PME_PM_UP_PREF_L3 1011 #define POWER8_PME_PM_UP_PREF_POINTER 1012 #define POWER8_PME_PM_VSU0_16FLOP 1013 #define POWER8_PME_PM_VSU0_1FLOP 1014 #define POWER8_PME_PM_VSU0_2FLOP 1015 #define POWER8_PME_PM_VSU0_4FLOP 1016 #define POWER8_PME_PM_VSU0_8FLOP 1017 #define POWER8_PME_PM_VSU0_COMPLEX_ISSUED 1018 #define POWER8_PME_PM_VSU0_CY_ISSUED 1019 #define POWER8_PME_PM_VSU0_DD_ISSUED 1020 #define POWER8_PME_PM_VSU0_DP_2FLOP 1021 #define POWER8_PME_PM_VSU0_DP_FMA 1022 #define POWER8_PME_PM_VSU0_DP_FSQRT_FDIV 1023 #define POWER8_PME_PM_VSU0_DQ_ISSUED 1024 #define POWER8_PME_PM_VSU0_EX_ISSUED 1025 #define POWER8_PME_PM_VSU0_FIN 1026 #define POWER8_PME_PM_VSU0_FMA 1027 #define POWER8_PME_PM_VSU0_FPSCR 1028 #define POWER8_PME_PM_VSU0_FSQRT_FDIV 1029 #define POWER8_PME_PM_VSU0_PERMUTE_ISSUED 1030 #define POWER8_PME_PM_VSU0_SCALAR_DP_ISSUED 1031 #define POWER8_PME_PM_VSU0_SIMPLE_ISSUED 1032 #define POWER8_PME_PM_VSU0_SINGLE 1033 #define POWER8_PME_PM_VSU0_SQ 1034 #define POWER8_PME_PM_VSU0_STF 1035 #define POWER8_PME_PM_VSU0_VECTOR_DP_ISSUED 1036 #define POWER8_PME_PM_VSU0_VECTOR_SP_ISSUED 1037 #define POWER8_PME_PM_VSU1_16FLOP 1038 #define POWER8_PME_PM_VSU1_1FLOP 1039 #define POWER8_PME_PM_VSU1_2FLOP 1040 #define POWER8_PME_PM_VSU1_4FLOP 1041 #define POWER8_PME_PM_VSU1_8FLOP 1042 #define POWER8_PME_PM_VSU1_COMPLEX_ISSUED 1043 #define POWER8_PME_PM_VSU1_CY_ISSUED 1044 #define POWER8_PME_PM_VSU1_DD_ISSUED 1045 #define POWER8_PME_PM_VSU1_DP_2FLOP 1046 #define POWER8_PME_PM_VSU1_DP_FMA 1047 #define POWER8_PME_PM_VSU1_DP_FSQRT_FDIV 1048 #define POWER8_PME_PM_VSU1_DQ_ISSUED 1049 #define POWER8_PME_PM_VSU1_EX_ISSUED 1050 #define POWER8_PME_PM_VSU1_FIN 1051 #define POWER8_PME_PM_VSU1_FMA 1052 #define POWER8_PME_PM_VSU1_FPSCR 1053 #define POWER8_PME_PM_VSU1_FSQRT_FDIV 1054 #define POWER8_PME_PM_VSU1_PERMUTE_ISSUED 1055 #define POWER8_PME_PM_VSU1_SCALAR_DP_ISSUED 1056 #define POWER8_PME_PM_VSU1_SIMPLE_ISSUED 1057 #define POWER8_PME_PM_VSU1_SINGLE 1058 #define POWER8_PME_PM_VSU1_SQ 1059 #define POWER8_PME_PM_VSU1_STF 1060 #define POWER8_PME_PM_VSU1_VECTOR_DP_ISSUED 1061 #define POWER8_PME_PM_VSU1_VECTOR_SP_ISSUED 1062 static const pme_power_entry_t power8_pe[] = { [ POWER8_PME_PM_1LPAR_CYC ] = { .pme_name = "PM_1LPAR_CYC", .pme_code = 0x1f05e, .pme_short_desc = "Number of cycles in single lpar mode. All threads in the core are assigned to the same lpar", .pme_long_desc = "Number of cycles in single lpar mode.", }, [ POWER8_PME_PM_1PLUS_PPC_CMPL ] = { .pme_name = "PM_1PLUS_PPC_CMPL", .pme_code = 0x100f2, .pme_short_desc = "1 or more ppc insts finished", .pme_long_desc = "1 or more ppc insts finished (completed).", }, [ POWER8_PME_PM_1PLUS_PPC_DISP ] = { .pme_name = "PM_1PLUS_PPC_DISP", .pme_code = 0x400f2, .pme_short_desc = "Cycles at least one Instr Dispatched", .pme_long_desc = "Cycles at least one Instr Dispatched. Could be a group with only microcode. Issue HW016521", }, [ POWER8_PME_PM_2LPAR_CYC ] = { .pme_name = "PM_2LPAR_CYC", .pme_code = 0x2006e, .pme_short_desc = "Cycles in 2-lpar mode. Threads 0-3 belong to Lpar0 and threads 4-7 belong to Lpar1", .pme_long_desc = "Number of cycles in 2 lpar mode.", }, [ POWER8_PME_PM_4LPAR_CYC ] = { .pme_name = "PM_4LPAR_CYC", .pme_code = 0x4e05e, .pme_short_desc = "Number of cycles in 4 LPAR mode. Threads 0-1 belong to lpar0, threads 2-3 belong to lpar1, threads 4-5 belong to lpar2, and threads 6-7 belong to lpar3", .pme_long_desc = "Number of cycles in 4 LPAR mode.", }, [ POWER8_PME_PM_ALL_CHIP_PUMP_CPRED ] = { .pme_name = "PM_ALL_CHIP_PUMP_CPRED", .pme_code = 0x610050, .pme_short_desc = "Initial and Final Pump Scope was chip pump (prediction=correct) for all data types (demand load,data prefetch,inst prefetch,inst fetch,xlate)", .pme_long_desc = "Initial and Final Pump Scope and data sourced across this scope was chip pump (prediction=correct) for all data types ( demand load,data,inst prefetch,inst fetch,xlate (I or d)", }, [ POWER8_PME_PM_ALL_GRP_PUMP_CPRED ] = { .pme_name = "PM_ALL_GRP_PUMP_CPRED", .pme_code = 0x520050, .pme_short_desc = "Initial and Final Pump Scope and data sourced across this scope was group pump for all data types (demand load,data prefetch,inst prefetch,inst fetch,xlate)", .pme_long_desc = "Initial and Final Pump Scope and data sourced across this scope was group pump for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)", }, [ POWER8_PME_PM_ALL_GRP_PUMP_MPRED ] = { .pme_name = "PM_ALL_GRP_PUMP_MPRED", .pme_code = 0x620052, .pme_short_desc = "Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for all data types (demand load,data prefetch,inst prefetch,inst fetch,xlate)", .pme_long_desc = "Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope OR Final Pump Scope(Group) got data from source that was at smaller scope(Chip) Final pump was group pump and initial pump was chip or final and initial pump was gro", }, [ POWER8_PME_PM_ALL_GRP_PUMP_MPRED_RTY ] = { .pme_name = "PM_ALL_GRP_PUMP_MPRED_RTY", .pme_code = 0x610052, .pme_short_desc = "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for all data types (demand load,data prefetch,inst prefetch,inst fetch,xlate)", .pme_long_desc = "Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope (Chip) Final pump was group pump and initial pump was chip pumpfor all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)", }, [ POWER8_PME_PM_ALL_PUMP_CPRED ] = { .pme_name = "PM_ALL_PUMP_CPRED", .pme_code = 0x610054, .pme_short_desc = "Pump prediction correct. Counts across all types of pumps for all data types (demand load,data prefetch,inst prefetch,inst fetch,xlate)", .pme_long_desc = "Pump prediction correct. Counts across all types of pumpsfor all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)", }, [ POWER8_PME_PM_ALL_PUMP_MPRED ] = { .pme_name = "PM_ALL_PUMP_MPRED", .pme_code = 0x640052, .pme_short_desc = "Pump misprediction. Counts across all types of pumps for all data types (demand load,data prefetch,inst prefetch,inst fetch,xlate)", .pme_long_desc = "Pump Mis prediction Counts across all types of pumpsfor all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)", }, [ POWER8_PME_PM_ALL_SYS_PUMP_CPRED ] = { .pme_name = "PM_ALL_SYS_PUMP_CPRED", .pme_code = 0x630050, .pme_short_desc = "Initial and Final Pump Scope was system pump for all data types (demand load,data prefetch,inst prefetch,inst fetch,xlate)", .pme_long_desc = "Initial and Final Pump Scope and data sourced across this scope was system pump for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)", }, [ POWER8_PME_PM_ALL_SYS_PUMP_MPRED ] = { .pme_name = "PM_ALL_SYS_PUMP_MPRED", .pme_code = 0x630052, .pme_short_desc = "Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for all data types (demand load,data prefetch,inst prefetch,inst fetch,xlate)", .pme_long_desc = "Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope(Chip/Group) OR Final Pump Scope(system) got data from source that was at smaller scope(Chip/group) Final pump was system pump and initial pump was chip or group or", }, [ POWER8_PME_PM_ALL_SYS_PUMP_MPRED_RTY ] = { .pme_name = "PM_ALL_SYS_PUMP_MPRED_RTY", .pme_code = 0x640050, .pme_short_desc = "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for all data types (demand load,data prefetch,inst prefetch,inst fetch,xlate)", .pme_long_desc = "Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope (Chip or Group) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)", }, [ POWER8_PME_PM_ANY_THRD_RUN_CYC ] = { .pme_name = "PM_ANY_THRD_RUN_CYC", .pme_code = 0x100fa, .pme_short_desc = "One of threads in run_cycles", .pme_long_desc = "Any thread in run_cycles (was one thread in run_cycles).", }, [ POWER8_PME_PM_BACK_BR_CMPL ] = { .pme_name = "PM_BACK_BR_CMPL", .pme_code = 0x2505e, .pme_short_desc = "Branch instruction completed with a target address less than current instruction address", .pme_long_desc = "Branch instruction completed with a target address less than current instruction address.", }, [ POWER8_PME_PM_BANK_CONFLICT ] = { .pme_name = "PM_BANK_CONFLICT", .pme_code = 0x4082, .pme_short_desc = "Read blocked due to interleave conflict. The ifar logic will detect an interleave conflict and kill the data that was read that cycle.", .pme_long_desc = "Read blocked due to interleave conflict. The ifar logic will detect an interleave conflict and kill the data that was read that cycle.", }, [ POWER8_PME_PM_BRU_FIN ] = { .pme_name = "PM_BRU_FIN", .pme_code = 0x10068, .pme_short_desc = "Branch Instruction Finished", .pme_long_desc = "Branch Instruction Finished .", }, [ POWER8_PME_PM_BR_2PATH ] = { .pme_name = "PM_BR_2PATH", .pme_code = 0x20036, .pme_short_desc = "two path branch", .pme_long_desc = "two path branch.", }, [ POWER8_PME_PM_BR_BC_8 ] = { .pme_name = "PM_BR_BC_8", .pme_code = 0x5086, .pme_short_desc = "Pairable BC+8 branch that has not been converted to a Resolve Finished in the BRU pipeline", .pme_long_desc = "Pairable BC+8 branch that has not been converted to a Resolve Finished in the BRU pipeline", }, [ POWER8_PME_PM_BR_BC_8_CONV ] = { .pme_name = "PM_BR_BC_8_CONV", .pme_code = 0x5084, .pme_short_desc = "Pairable BC+8 branch that was converted to a Resolve Finished in the BRU pipeline.", .pme_long_desc = "Pairable BC+8 branch that was converted to a Resolve Finished in the BRU pipeline.", }, [ POWER8_PME_PM_BR_CMPL ] = { .pme_name = "PM_BR_CMPL", .pme_code = 0x40060, .pme_short_desc = "Branch Instruction completed", .pme_long_desc = "Branch Instruction completed.", }, [ POWER8_PME_PM_BR_MPRED_CCACHE ] = { .pme_name = "PM_BR_MPRED_CCACHE", .pme_code = 0x40ac, .pme_short_desc = "Conditional Branch Completed that was Mispredicted due to the Count Cache Target Prediction", .pme_long_desc = "Conditional Branch Completed that was Mispredicted due to the Count Cache Target Prediction", }, [ POWER8_PME_PM_BR_MPRED_CMPL ] = { .pme_name = "PM_BR_MPRED_CMPL", .pme_code = 0x400f6, .pme_short_desc = "Number of Branch Mispredicts", .pme_long_desc = "Number of Branch Mispredicts.", }, [ POWER8_PME_PM_BR_MPRED_CR ] = { .pme_name = "PM_BR_MPRED_CR", .pme_code = 0x40b8, .pme_short_desc = "Conditional Branch Completed that was Mispredicted due to the BHT Direction Prediction (taken/not taken).", .pme_long_desc = "Conditional Branch Completed that was Mispredicted due to the BHT Direction Prediction (taken/not taken).", }, [ POWER8_PME_PM_BR_MPRED_LSTACK ] = { .pme_name = "PM_BR_MPRED_LSTACK", .pme_code = 0x40ae, .pme_short_desc = "Conditional Branch Completed that was Mispredicted due to the Link Stack Target Prediction", .pme_long_desc = "Conditional Branch Completed that was Mispredicted due to the Link Stack Target Prediction", }, [ POWER8_PME_PM_BR_MPRED_TA ] = { .pme_name = "PM_BR_MPRED_TA", .pme_code = 0x40ba, .pme_short_desc = "Conditional Branch Completed that was Mispredicted due to the Target Address Prediction from the Count Cache or Link Stack. Only XL-form branches that resolved Taken set this event.", .pme_long_desc = "Conditional Branch Completed that was Mispredicted due to the Target Address Prediction from the Count Cache or Link Stack. Only XL-form branches that resolved Taken set this event.", }, [ POWER8_PME_PM_BR_MRK_2PATH ] = { .pme_name = "PM_BR_MRK_2PATH", .pme_code = 0x10138, .pme_short_desc = "marked two path branch", .pme_long_desc = "marked two path branch.", }, [ POWER8_PME_PM_BR_PRED_BR0 ] = { .pme_name = "PM_BR_PRED_BR0", .pme_code = 0x409c, .pme_short_desc = "Conditional Branch Completed on BR0 (1st branch in group) in which the HW predicted the Direction or Target", .pme_long_desc = "Conditional Branch Completed on BR0 (1st branch in group) in which the HW predicted the Direction or Target", }, [ POWER8_PME_PM_BR_PRED_BR1 ] = { .pme_name = "PM_BR_PRED_BR1", .pme_code = 0x409e, .pme_short_desc = "Conditional Branch Completed on BR1 (2nd branch in group) in which the HW predicted the Direction or Target. Note: BR1 can only be used in Single Thread Mode. In all of the SMT modes, only one branch can complete, thus BR1 is unused.", .pme_long_desc = "Conditional Branch Completed on BR1 (2nd branch in group) in which the HW predicted the Direction or Target. Note: BR1 can only be used in Single Thread Mode. In all of the SMT modes, only one branch can complete, thus BR1 is unused.", }, [ POWER8_PME_PM_BR_PRED_BR_CMPL ] = { .pme_name = "PM_BR_PRED_BR_CMPL", .pme_code = 0x489c, .pme_short_desc = "Completion Time Event. This event can also be calculated from the direct bus as follows: if_pc_br0_br_pred(0) OR if_pc_br0_br_pred(1).", .pme_long_desc = "IFU", }, [ POWER8_PME_PM_BR_PRED_CCACHE_BR0 ] = { .pme_name = "PM_BR_PRED_CCACHE_BR0", .pme_code = 0x40a4, .pme_short_desc = "Conditional Branch Completed on BR0 that used the Count Cache for Target Prediction", .pme_long_desc = "Conditional Branch Completed on BR0 that used the Count Cache for Target Prediction", }, [ POWER8_PME_PM_BR_PRED_CCACHE_BR1 ] = { .pme_name = "PM_BR_PRED_CCACHE_BR1", .pme_code = 0x40a6, .pme_short_desc = "Conditional Branch Completed on BR1 that used the Count Cache for Target Prediction", .pme_long_desc = "Conditional Branch Completed on BR1 that used the Count Cache for Target Prediction", }, [ POWER8_PME_PM_BR_PRED_CCACHE_CMPL ] = { .pme_name = "PM_BR_PRED_CCACHE_CMPL", .pme_code = 0x48a4, .pme_short_desc = "Completion Time Event. This event can also be calculated from the direct bus as follows: if_pc_br0_br_pred(0) AND if_pc_br0_pred_type.", .pme_long_desc = "IFU", }, [ POWER8_PME_PM_BR_PRED_CR_BR0 ] = { .pme_name = "PM_BR_PRED_CR_BR0", .pme_code = 0x40b0, .pme_short_desc = "Conditional Branch Completed on BR0 that had its direction predicted. I-form branches do not set this event. In addition, B-form branches which do not use the BHT do not set this event - these are branches with BO-field set to 'always taken' and branches", .pme_long_desc = "Conditional Branch Completed on BR0 that had its direction predicted. I-form branches do not set this event. In addition, B-form branches which do not use the BHT do not set this event - these are branches with BO-field set to 'always taken' and bra", }, [ POWER8_PME_PM_BR_PRED_CR_BR1 ] = { .pme_name = "PM_BR_PRED_CR_BR1", .pme_code = 0x40b2, .pme_short_desc = "Conditional Branch Completed on BR1 that had its direction predicted. I-form branches do not set this event. In addition, B-form branches which do not use the BHT do not set this event - these are branches with BO-field set to 'always taken' and branches", .pme_long_desc = "Conditional Branch Completed on BR1 that had its direction predicted. I-form branches do not set this event. In addition, B-form branches which do not use the BHT do not set this event - these are branches with BO-field set to 'always taken' and bra", }, [ POWER8_PME_PM_BR_PRED_CR_CMPL ] = { .pme_name = "PM_BR_PRED_CR_CMPL", .pme_code = 0x48b0, .pme_short_desc = "Completion Time Event. This event can also be calculated from the direct bus as follows: if_pc_br0_br_pred(1)='1'.", .pme_long_desc = "IFU", }, [ POWER8_PME_PM_BR_PRED_LSTACK_BR0 ] = { .pme_name = "PM_BR_PRED_LSTACK_BR0", .pme_code = 0x40a8, .pme_short_desc = "Conditional Branch Completed on BR0 that used the Link Stack for Target Prediction", .pme_long_desc = "Conditional Branch Completed on BR0 that used the Link Stack for Target Prediction", }, [ POWER8_PME_PM_BR_PRED_LSTACK_BR1 ] = { .pme_name = "PM_BR_PRED_LSTACK_BR1", .pme_code = 0x40aa, .pme_short_desc = "Conditional Branch Completed on BR1 that used the Link Stack for Target Prediction", .pme_long_desc = "Conditional Branch Completed on BR1 that used the Link Stack for Target Prediction", }, [ POWER8_PME_PM_BR_PRED_LSTACK_CMPL ] = { .pme_name = "PM_BR_PRED_LSTACK_CMPL", .pme_code = 0x48a8, .pme_short_desc = "Completion Time Event. This event can also be calculated from the direct bus as follows: if_pc_br0_br_pred(0) AND (not if_pc_br0_pred_type).", .pme_long_desc = "IFU", }, [ POWER8_PME_PM_BR_PRED_TA_BR0 ] = { .pme_name = "PM_BR_PRED_TA_BR0", .pme_code = 0x40b4, .pme_short_desc = "Conditional Branch Completed on BR0 that had its target address predicted. Only XL-form branches set this event.", .pme_long_desc = "Conditional Branch Completed on BR0 that had its target address predicted. Only XL-form branches set this event.", }, [ POWER8_PME_PM_BR_PRED_TA_BR1 ] = { .pme_name = "PM_BR_PRED_TA_BR1", .pme_code = 0x40b6, .pme_short_desc = "Conditional Branch Completed on BR1 that had its target address predicted. Only XL-form branches set this event.", .pme_long_desc = "Conditional Branch Completed on BR1 that had its target address predicted. Only XL-form branches set this event.", }, [ POWER8_PME_PM_BR_PRED_TA_CMPL ] = { .pme_name = "PM_BR_PRED_TA_CMPL", .pme_code = 0x48b4, .pme_short_desc = "Completion Time Event. This event can also be calculated from the direct bus as follows: if_pc_br0_br_pred(0)='1'.", .pme_long_desc = "IFU", }, [ POWER8_PME_PM_BR_TAKEN_CMPL ] = { .pme_name = "PM_BR_TAKEN_CMPL", .pme_code = 0x200fa, .pme_short_desc = "New event for Branch Taken", .pme_long_desc = "Branch Taken.", }, [ POWER8_PME_PM_BR_UNCOND_BR0 ] = { .pme_name = "PM_BR_UNCOND_BR0", .pme_code = 0x40a0, .pme_short_desc = "Unconditional Branch Completed on BR0. HW branch prediction was not used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch always, or a B-form branch which was coverted to a Resolve.", .pme_long_desc = "Unconditional Branch Completed on BR0. HW branch prediction was not used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch always, or a B-form branch which was coverted to a Resolve.", }, [ POWER8_PME_PM_BR_UNCOND_BR1 ] = { .pme_name = "PM_BR_UNCOND_BR1", .pme_code = 0x40a2, .pme_short_desc = "Unconditional Branch Completed on BR1. HW branch prediction was not used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch always, or a B-form branch which was coverted to a Resolve.", .pme_long_desc = "Unconditional Branch Completed on BR1. HW branch prediction was not used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch always, or a B-form branch which was coverted to a Resolve.", }, [ POWER8_PME_PM_BR_UNCOND_CMPL ] = { .pme_name = "PM_BR_UNCOND_CMPL", .pme_code = 0x48a0, .pme_short_desc = "Completion Time Event. This event can also be calculated from the direct bus as follows: if_pc_br0_br_pred=00 AND if_pc_br0_completed.", .pme_long_desc = "IFU", }, [ POWER8_PME_PM_CASTOUT_ISSUED ] = { .pme_name = "PM_CASTOUT_ISSUED", .pme_code = 0x3094, .pme_short_desc = "Castouts issued", .pme_long_desc = "Castouts issued", }, [ POWER8_PME_PM_CASTOUT_ISSUED_GPR ] = { .pme_name = "PM_CASTOUT_ISSUED_GPR", .pme_code = 0x3096, .pme_short_desc = "Castouts issued GPR", .pme_long_desc = "Castouts issued GPR", }, [ POWER8_PME_PM_CHIP_PUMP_CPRED ] = { .pme_name = "PM_CHIP_PUMP_CPRED", .pme_code = 0x10050, .pme_short_desc = "Initial and Final Pump Scope was chip pump (prediction=correct) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)", .pme_long_desc = "Initial and Final Pump Scope and data sourced across this scope was chip pump (prediction=correct) for all data types ( demand load,data,inst prefetch,inst fetch,xlate (I or d).", }, [ POWER8_PME_PM_CLB_HELD ] = { .pme_name = "PM_CLB_HELD", .pme_code = 0x2090, .pme_short_desc = "CLB Hold: Any Reason", .pme_long_desc = "CLB Hold: Any Reason", }, [ POWER8_PME_PM_CMPLU_STALL ] = { .pme_name = "PM_CMPLU_STALL", .pme_code = 0x4000a, .pme_short_desc = "Completion stall", .pme_long_desc = "Completion stall.", }, [ POWER8_PME_PM_CMPLU_STALL_BRU ] = { .pme_name = "PM_CMPLU_STALL_BRU", .pme_code = 0x4d018, .pme_short_desc = "Completion stall due to a Branch Unit", .pme_long_desc = "Completion stall due to a Branch Unit.", }, [ POWER8_PME_PM_CMPLU_STALL_BRU_CRU ] = { .pme_name = "PM_CMPLU_STALL_BRU_CRU", .pme_code = 0x2d018, .pme_short_desc = "Completion stall due to IFU", .pme_long_desc = "Completion stall due to IFU.", }, [ POWER8_PME_PM_CMPLU_STALL_COQ_FULL ] = { .pme_name = "PM_CMPLU_STALL_COQ_FULL", .pme_code = 0x30026, .pme_short_desc = "Completion stall due to CO q full", .pme_long_desc = "Completion stall due to CO q full.", }, [ POWER8_PME_PM_CMPLU_STALL_DCACHE_MISS ] = { .pme_name = "PM_CMPLU_STALL_DCACHE_MISS", .pme_code = 0x2c012, .pme_short_desc = "Completion stall by Dcache miss", .pme_long_desc = "Completion stall by Dcache miss.", }, [ POWER8_PME_PM_CMPLU_STALL_DMISS_L21_L31 ] = { .pme_name = "PM_CMPLU_STALL_DMISS_L21_L31", .pme_code = 0x2c018, .pme_short_desc = "Completion stall by Dcache miss which resolved on chip ( excluding local L2/L3)", .pme_long_desc = "Completion stall by Dcache miss which resolved on chip ( excluding local L2/L3).", }, [ POWER8_PME_PM_CMPLU_STALL_DMISS_L2L3 ] = { .pme_name = "PM_CMPLU_STALL_DMISS_L2L3", .pme_code = 0x2c016, .pme_short_desc = "Completion stall by Dcache miss which resolved in L2/L3", .pme_long_desc = "Completion stall by Dcache miss which resolved in L2/L3.", }, [ POWER8_PME_PM_CMPLU_STALL_DMISS_L2L3_CONFLICT ] = { .pme_name = "PM_CMPLU_STALL_DMISS_L2L3_CONFLICT", .pme_code = 0x4c016, .pme_short_desc = "Completion stall due to cache miss that resolves in the L2 or L3 with a conflict", .pme_long_desc = "Completion stall due to cache miss resolving in core's L2/L3 with a conflict.", }, [ POWER8_PME_PM_CMPLU_STALL_DMISS_L3MISS ] = { .pme_name = "PM_CMPLU_STALL_DMISS_L3MISS", .pme_code = 0x4c01a, .pme_short_desc = "Completion stall due to cache miss resolving missed the L3", .pme_long_desc = "Completion stall due to cache miss resolving missed the L3.", }, [ POWER8_PME_PM_CMPLU_STALL_DMISS_LMEM ] = { .pme_name = "PM_CMPLU_STALL_DMISS_LMEM", .pme_code = 0x4c018, .pme_short_desc = "Completion stall due to cache miss that resolves in local memory", .pme_long_desc = "Completion stall due to cache miss resolving in core's Local Memory.", }, [ POWER8_PME_PM_CMPLU_STALL_DMISS_REMOTE ] = { .pme_name = "PM_CMPLU_STALL_DMISS_REMOTE", .pme_code = 0x2c01c, .pme_short_desc = "Completion stall by Dcache miss which resolved from remote chip (cache or memory)", .pme_long_desc = "Completion stall by Dcache miss which resolved on chip ( excluding local L2/L3).", }, [ POWER8_PME_PM_CMPLU_STALL_ERAT_MISS ] = { .pme_name = "PM_CMPLU_STALL_ERAT_MISS", .pme_code = 0x4c012, .pme_short_desc = "Completion stall due to LSU reject ERAT miss", .pme_long_desc = "Completion stall due to LSU reject ERAT miss.", }, [ POWER8_PME_PM_CMPLU_STALL_FLUSH ] = { .pme_name = "PM_CMPLU_STALL_FLUSH", .pme_code = 0x30038, .pme_short_desc = "completion stall due to flush by own thread", .pme_long_desc = "completion stall due to flush by own thread.", }, [ POWER8_PME_PM_CMPLU_STALL_FXLONG ] = { .pme_name = "PM_CMPLU_STALL_FXLONG", .pme_code = 0x4d016, .pme_short_desc = "Completion stall due to a long latency fixed point instruction", .pme_long_desc = "Completion stall due to a long latency fixed point instruction.", }, [ POWER8_PME_PM_CMPLU_STALL_FXU ] = { .pme_name = "PM_CMPLU_STALL_FXU", .pme_code = 0x2d016, .pme_short_desc = "Completion stall due to FXU", .pme_long_desc = "Completion stall due to FXU.", }, [ POWER8_PME_PM_CMPLU_STALL_HWSYNC ] = { .pme_name = "PM_CMPLU_STALL_HWSYNC", .pme_code = 0x30036, .pme_short_desc = "completion stall due to hwsync", .pme_long_desc = "completion stall due to hwsync.", }, [ POWER8_PME_PM_CMPLU_STALL_LOAD_FINISH ] = { .pme_name = "PM_CMPLU_STALL_LOAD_FINISH", .pme_code = 0x4d014, .pme_short_desc = "Completion stall due to a Load finish", .pme_long_desc = "Completion stall due to a Load finish.", }, [ POWER8_PME_PM_CMPLU_STALL_LSU ] = { .pme_name = "PM_CMPLU_STALL_LSU", .pme_code = 0x2c010, .pme_short_desc = "Completion stall by LSU instruction", .pme_long_desc = "Completion stall by LSU instruction.", }, [ POWER8_PME_PM_CMPLU_STALL_LWSYNC ] = { .pme_name = "PM_CMPLU_STALL_LWSYNC", .pme_code = 0x10036, .pme_short_desc = "completion stall due to isync/lwsync", .pme_long_desc = "completion stall due to isync/lwsync.", }, [ POWER8_PME_PM_CMPLU_STALL_MEM_ECC_DELAY ] = { .pme_name = "PM_CMPLU_STALL_MEM_ECC_DELAY", .pme_code = 0x30028, .pme_short_desc = "Completion stall due to mem ECC delay", .pme_long_desc = "Completion stall due to mem ECC delay.", }, [ POWER8_PME_PM_CMPLU_STALL_NO_NTF ] = { .pme_name = "PM_CMPLU_STALL_NO_NTF", .pme_code = 0x2e01c, .pme_short_desc = "Completion stall due to nop", .pme_long_desc = "Completion stall due to nop.", }, [ POWER8_PME_PM_CMPLU_STALL_NTCG_FLUSH ] = { .pme_name = "PM_CMPLU_STALL_NTCG_FLUSH", .pme_code = 0x2e01e, .pme_short_desc = "Completion stall due to ntcg flush", .pme_long_desc = "Completion stall due to reject (load hit store).", }, [ POWER8_PME_PM_CMPLU_STALL_OTHER_CMPL ] = { .pme_name = "PM_CMPLU_STALL_OTHER_CMPL", .pme_code = 0x30006, .pme_short_desc = "Instructions core completed while this tread was stalled", .pme_long_desc = "Instructions core completed while this thread was stalled.", }, [ POWER8_PME_PM_CMPLU_STALL_REJECT ] = { .pme_name = "PM_CMPLU_STALL_REJECT", .pme_code = 0x4c010, .pme_short_desc = "Completion stall due to LSU reject", .pme_long_desc = "Completion stall due to LSU reject.", }, [ POWER8_PME_PM_CMPLU_STALL_REJECT_LHS ] = { .pme_name = "PM_CMPLU_STALL_REJECT_LHS", .pme_code = 0x2c01a, .pme_short_desc = "Completion stall due to reject (load hit store)", .pme_long_desc = "Completion stall due to reject (load hit store).", }, [ POWER8_PME_PM_CMPLU_STALL_REJ_LMQ_FULL ] = { .pme_name = "PM_CMPLU_STALL_REJ_LMQ_FULL", .pme_code = 0x4c014, .pme_short_desc = "Completion stall due to LSU reject LMQ full", .pme_long_desc = "Completion stall due to LSU reject LMQ full.", }, [ POWER8_PME_PM_CMPLU_STALL_SCALAR ] = { .pme_name = "PM_CMPLU_STALL_SCALAR", .pme_code = 0x4d010, .pme_short_desc = "Completion stall due to VSU scalar instruction", .pme_long_desc = "Completion stall due to VSU scalar instruction.", }, [ POWER8_PME_PM_CMPLU_STALL_SCALAR_LONG ] = { .pme_name = "PM_CMPLU_STALL_SCALAR_LONG", .pme_code = 0x2d010, .pme_short_desc = "Completion stall due to VSU scalar long latency instruction", .pme_long_desc = "Completion stall due to VSU scalar long latency instruction.", }, [ POWER8_PME_PM_CMPLU_STALL_STORE ] = { .pme_name = "PM_CMPLU_STALL_STORE", .pme_code = 0x2c014, .pme_short_desc = "Completion stall by stores this includes store agen finishes in pipe LS0/LS1 and store data finishes in LS2/LS3", .pme_long_desc = "Completion stall by stores.", }, [ POWER8_PME_PM_CMPLU_STALL_ST_FWD ] = { .pme_name = "PM_CMPLU_STALL_ST_FWD", .pme_code = 0x4c01c, .pme_short_desc = "Completion stall due to store forward", .pme_long_desc = "Completion stall due to store forward.", }, [ POWER8_PME_PM_CMPLU_STALL_THRD ] = { .pme_name = "PM_CMPLU_STALL_THRD", .pme_code = 0x1001c, .pme_short_desc = "Completion Stalled due to thread conflict. Group ready to complete but it was another thread's turn", .pme_long_desc = "Completion stall due to thread conflict.", }, [ POWER8_PME_PM_CMPLU_STALL_VECTOR ] = { .pme_name = "PM_CMPLU_STALL_VECTOR", .pme_code = 0x2d014, .pme_short_desc = "Completion stall due to VSU vector instruction", .pme_long_desc = "Completion stall due to VSU vector instruction.", }, [ POWER8_PME_PM_CMPLU_STALL_VECTOR_LONG ] = { .pme_name = "PM_CMPLU_STALL_VECTOR_LONG", .pme_code = 0x4d012, .pme_short_desc = "Completion stall due to VSU vector long instruction", .pme_long_desc = "Completion stall due to VSU vector long instruction.", }, [ POWER8_PME_PM_CMPLU_STALL_VSU ] = { .pme_name = "PM_CMPLU_STALL_VSU", .pme_code = 0x2d012, .pme_short_desc = "Completion stall due to VSU instruction", .pme_long_desc = "Completion stall due to VSU instruction.", }, [ POWER8_PME_PM_CO0_ALLOC ] = { .pme_name = "PM_CO0_ALLOC", .pme_code = 0x16083, .pme_short_desc = "CO mach 0 Busy. Used by PMU to sample ave RC livetime(mach0 used as sample point)", .pme_long_desc = "0.0", }, [ POWER8_PME_PM_CO0_BUSY ] = { .pme_name = "PM_CO0_BUSY", .pme_code = 0x16082, .pme_short_desc = "CO mach 0 Busy. Used by PMU to sample ave RC livetime(mach0 used as sample point)", .pme_long_desc = "CO mach 0 Busy. Used by PMU to sample ave RC livetime(mach0 used as sample point)", }, [ POWER8_PME_PM_CO_DISP_FAIL ] = { .pme_name = "PM_CO_DISP_FAIL", .pme_code = 0x517082, .pme_short_desc = "CO dispatch failed due to all CO machines being busy", .pme_long_desc = "CO dispatch failed due to all CO machines being busy", }, [ POWER8_PME_PM_CO_TM_SC_FOOTPRINT ] = { .pme_name = "PM_CO_TM_SC_FOOTPRINT", .pme_code = 0x527084, .pme_short_desc = "L2 did a cleanifdirty CO to the L3 (ie created an SC line in the L3)", .pme_long_desc = "L2 did a cleanifdirty CO to the L3 (ie created an SC line in the L3)", }, [ POWER8_PME_PM_CO_USAGE ] = { .pme_name = "PM_CO_USAGE", .pme_code = 0x3608a, .pme_short_desc = "Continuous 16 cycle(2to1) window where this signals rotates thru sampling each L2 CO machine busy. PMU uses this wave to then do 16 cyc count to sample total number of machs running", .pme_long_desc = "Continuous 16 cycle(2to1) window where this signals rotates thru sampling each L2 CO machine busy. PMU uses this wave to then do 16 cyc count to sample total number of machs running", }, [ POWER8_PME_PM_CRU_FIN ] = { .pme_name = "PM_CRU_FIN", .pme_code = 0x40066, .pme_short_desc = "IFU Finished a (non-branch) instruction", .pme_long_desc = "IFU Finished a (non-branch) instruction.", }, [ POWER8_PME_PM_CYC ] = { .pme_name = "PM_CYC", .pme_code = 0x1e, .pme_short_desc = "Cycles", .pme_long_desc = "Cycles .", }, [ POWER8_PME_PM_DATA_ALL_CHIP_PUMP_CPRED ] = { .pme_name = "PM_DATA_ALL_CHIP_PUMP_CPRED", .pme_code = 0x61c050, .pme_short_desc = "Initial and Final Pump Scope was chip pump (prediction=correct) for either demand loads or data prefetch", .pme_long_desc = "Initial and Final Pump Scope and data sourced across this scope was chip pump (prediction=correct) for a demand load", }, [ POWER8_PME_PM_DATA_ALL_FROM_DL2L3_MOD ] = { .pme_name = "PM_DATA_ALL_FROM_DL2L3_MOD", .pme_code = 0x64c048, .pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either demand loads or data prefetch", .pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1", }, [ POWER8_PME_PM_DATA_ALL_FROM_DL2L3_SHR ] = { .pme_name = "PM_DATA_ALL_FROM_DL2L3_SHR", .pme_code = 0x63c048, .pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either demand loads or data prefetch", .pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1", }, [ POWER8_PME_PM_DATA_ALL_FROM_DL4 ] = { .pme_name = "PM_DATA_ALL_FROM_DL4", .pme_code = 0x63c04c, .pme_short_desc = "The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to either demand loads or data prefetch", .pme_long_desc = "The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1", }, [ POWER8_PME_PM_DATA_ALL_FROM_DMEM ] = { .pme_name = "PM_DATA_ALL_FROM_DMEM", .pme_code = 0x64c04c, .pme_short_desc = "The processor's data cache was reloaded from another chip's memory on the same Node or Group (Distant) due to either demand loads or data prefetch", .pme_long_desc = "The processor's data cache was reloaded from another chip's memory on the same Node or Group (Distant) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1", }, [ POWER8_PME_PM_DATA_ALL_FROM_L2 ] = { .pme_name = "PM_DATA_ALL_FROM_L2", .pme_code = 0x61c042, .pme_short_desc = "The processor's data cache was reloaded from local core's L2 due to either demand loads or data prefetch", .pme_long_desc = "The processor's data cache was reloaded from local core's L2 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1", }, [ POWER8_PME_PM_DATA_ALL_FROM_L21_MOD ] = { .pme_name = "PM_DATA_ALL_FROM_L21_MOD", .pme_code = 0x64c046, .pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another core's L2 on the same chip due to either demand loads or data prefetch", .pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another core's L2 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1", }, [ POWER8_PME_PM_DATA_ALL_FROM_L21_SHR ] = { .pme_name = "PM_DATA_ALL_FROM_L21_SHR", .pme_code = 0x63c046, .pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to either demand loads or data prefetch", .pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1", }, [ POWER8_PME_PM_DATA_ALL_FROM_L2MISS_MOD ] = { .pme_name = "PM_DATA_ALL_FROM_L2MISS_MOD", .pme_code = 0x61c04e, .pme_short_desc = "The processor's data cache was reloaded from a localtion other than the local core's L2 due to either demand loads or data prefetch", .pme_long_desc = "The processor's data cache was reloaded from a localtion other than the local core's L2 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1", }, [ POWER8_PME_PM_DATA_ALL_FROM_L2_DISP_CONFLICT_LDHITST ] = { .pme_name = "PM_DATA_ALL_FROM_L2_DISP_CONFLICT_LDHITST", .pme_code = 0x63c040, .pme_short_desc = "The processor's data cache was reloaded from local core's L2 with load hit store conflict due to either demand loads or data prefetch", .pme_long_desc = "The processor's data cache was reloaded from local core's L2 with load hit store conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1", }, [ POWER8_PME_PM_DATA_ALL_FROM_L2_DISP_CONFLICT_OTHER ] = { .pme_name = "PM_DATA_ALL_FROM_L2_DISP_CONFLICT_OTHER", .pme_code = 0x64c040, .pme_short_desc = "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to either demand loads or data prefetch", .pme_long_desc = "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1", }, [ POWER8_PME_PM_DATA_ALL_FROM_L2_MEPF ] = { .pme_name = "PM_DATA_ALL_FROM_L2_MEPF", .pme_code = 0x62c040, .pme_short_desc = "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state due to either demand loads or data prefetch", .pme_long_desc = "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1", }, [ POWER8_PME_PM_DATA_ALL_FROM_L2_NO_CONFLICT ] = { .pme_name = "PM_DATA_ALL_FROM_L2_NO_CONFLICT", .pme_code = 0x61c040, .pme_short_desc = "The processor's data cache was reloaded from local core's L2 without conflict due to either demand loads or data prefetch", .pme_long_desc = "The processor's data cache was reloaded from local core's L2 without conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1", }, [ POWER8_PME_PM_DATA_ALL_FROM_L3 ] = { .pme_name = "PM_DATA_ALL_FROM_L3", .pme_code = 0x64c042, .pme_short_desc = "The processor's data cache was reloaded from local core's L3 due to either demand loads or data prefetch", .pme_long_desc = "The processor's data cache was reloaded from local core's L3 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1", }, [ POWER8_PME_PM_DATA_ALL_FROM_L31_ECO_MOD ] = { .pme_name = "PM_DATA_ALL_FROM_L31_ECO_MOD", .pme_code = 0x64c044, .pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to either demand loads or data prefetch", .pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1", }, [ POWER8_PME_PM_DATA_ALL_FROM_L31_ECO_SHR ] = { .pme_name = "PM_DATA_ALL_FROM_L31_ECO_SHR", .pme_code = 0x63c044, .pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to either demand loads or data prefetch", .pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1", }, [ POWER8_PME_PM_DATA_ALL_FROM_L31_MOD ] = { .pme_name = "PM_DATA_ALL_FROM_L31_MOD", .pme_code = 0x62c044, .pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another core's L3 on the same chip due to either demand loads or data prefetch", .pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another core's L3 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1", }, [ POWER8_PME_PM_DATA_ALL_FROM_L31_SHR ] = { .pme_name = "PM_DATA_ALL_FROM_L31_SHR", .pme_code = 0x61c046, .pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another core's L3 on the same chip due to either demand loads or data prefetch", .pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another core's L3 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1", }, [ POWER8_PME_PM_DATA_ALL_FROM_L3MISS_MOD ] = { .pme_name = "PM_DATA_ALL_FROM_L3MISS_MOD", .pme_code = 0x64c04e, .pme_short_desc = "The processor's data cache was reloaded from a localtion other than the local core's L3 due to either demand loads or data prefetch", .pme_long_desc = "The processor's data cache was reloaded from a localtion other than the local core's L3 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1", }, [ POWER8_PME_PM_DATA_ALL_FROM_L3_DISP_CONFLICT ] = { .pme_name = "PM_DATA_ALL_FROM_L3_DISP_CONFLICT", .pme_code = 0x63c042, .pme_short_desc = "The processor's data cache was reloaded from local core's L3 with dispatch conflict due to either demand loads or data prefetch", .pme_long_desc = "The processor's data cache was reloaded from local core's L3 with dispatch conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1", }, [ POWER8_PME_PM_DATA_ALL_FROM_L3_MEPF ] = { .pme_name = "PM_DATA_ALL_FROM_L3_MEPF", .pme_code = 0x62c042, .pme_short_desc = "The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state due to either demand loads or data prefetch", .pme_long_desc = "The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1", }, [ POWER8_PME_PM_DATA_ALL_FROM_L3_NO_CONFLICT ] = { .pme_name = "PM_DATA_ALL_FROM_L3_NO_CONFLICT", .pme_code = 0x61c044, .pme_short_desc = "The processor's data cache was reloaded from local core's L3 without conflict due to either demand loads or data prefetch", .pme_long_desc = "The processor's data cache was reloaded from local core's L3 without conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1", }, [ POWER8_PME_PM_DATA_ALL_FROM_LL4 ] = { .pme_name = "PM_DATA_ALL_FROM_LL4", .pme_code = 0x61c04c, .pme_short_desc = "The processor's data cache was reloaded from the local chip's L4 cache due to either demand loads or data prefetch", .pme_long_desc = "The processor's data cache was reloaded from the local chip's L4 cache due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1", }, [ POWER8_PME_PM_DATA_ALL_FROM_LMEM ] = { .pme_name = "PM_DATA_ALL_FROM_LMEM", .pme_code = 0x62c048, .pme_short_desc = "The processor's data cache was reloaded from the local chip's Memory due to either demand loads or data prefetch", .pme_long_desc = "The processor's data cache was reloaded from the local chip's Memory due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1", }, [ POWER8_PME_PM_DATA_ALL_FROM_MEMORY ] = { .pme_name = "PM_DATA_ALL_FROM_MEMORY", .pme_code = 0x62c04c, .pme_short_desc = "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to either demand loads or data prefetch", .pme_long_desc = "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1", }, [ POWER8_PME_PM_DATA_ALL_FROM_OFF_CHIP_CACHE ] = { .pme_name = "PM_DATA_ALL_FROM_OFF_CHIP_CACHE", .pme_code = 0x64c04a, .pme_short_desc = "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to either demand loads or data prefetch", .pme_long_desc = "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1", }, [ POWER8_PME_PM_DATA_ALL_FROM_ON_CHIP_CACHE ] = { .pme_name = "PM_DATA_ALL_FROM_ON_CHIP_CACHE", .pme_code = 0x61c048, .pme_short_desc = "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to either demand loads or data prefetch", .pme_long_desc = "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1", }, [ POWER8_PME_PM_DATA_ALL_FROM_RL2L3_MOD ] = { .pme_name = "PM_DATA_ALL_FROM_RL2L3_MOD", .pme_code = 0x62c046, .pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either demand loads or data prefetch", .pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1", }, [ POWER8_PME_PM_DATA_ALL_FROM_RL2L3_SHR ] = { .pme_name = "PM_DATA_ALL_FROM_RL2L3_SHR", .pme_code = 0x61c04a, .pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either demand loads or data prefetch", .pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1", }, [ POWER8_PME_PM_DATA_ALL_FROM_RL4 ] = { .pme_name = "PM_DATA_ALL_FROM_RL4", .pme_code = 0x62c04a, .pme_short_desc = "The processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to either demand loads or data prefetch", .pme_long_desc = "The processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1", }, [ POWER8_PME_PM_DATA_ALL_FROM_RMEM ] = { .pme_name = "PM_DATA_ALL_FROM_RMEM", .pme_code = 0x63c04a, .pme_short_desc = "The processor's data cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to either demand loads or data prefetch", .pme_long_desc = "The processor's data cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1", }, [ POWER8_PME_PM_DATA_ALL_GRP_PUMP_CPRED ] = { .pme_name = "PM_DATA_ALL_GRP_PUMP_CPRED", .pme_code = 0x62c050, .pme_short_desc = "Initial and Final Pump Scope was group pump (prediction=correct) for either demand loads or data prefetch", .pme_long_desc = "Initial and Final Pump Scope and data sourced across this scope was group pump for a demand load", }, [ POWER8_PME_PM_DATA_ALL_GRP_PUMP_MPRED ] = { .pme_name = "PM_DATA_ALL_GRP_PUMP_MPRED", .pme_code = 0x62c052, .pme_short_desc = "Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for either demand loads or data prefetch", .pme_long_desc = "Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope OR Final Pump Scope(Group) got data from source that was at smaller scope(Chip) Final pump was group pump and initial pump was chip or final and initial pump was gro", }, [ POWER8_PME_PM_DATA_ALL_GRP_PUMP_MPRED_RTY ] = { .pme_name = "PM_DATA_ALL_GRP_PUMP_MPRED_RTY", .pme_code = 0x61c052, .pme_short_desc = "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for either demand loads or data prefetch", .pme_long_desc = "Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope (Chip) Final pump was group pump and initial pump was chip pumpfor a demand load", }, [ POWER8_PME_PM_DATA_ALL_PUMP_CPRED ] = { .pme_name = "PM_DATA_ALL_PUMP_CPRED", .pme_code = 0x61c054, .pme_short_desc = "Pump prediction correct. Counts across all types of pumps for either demand loads or data prefetch", .pme_long_desc = "Pump prediction correct. Counts across all types of pumps for a demand load", }, [ POWER8_PME_PM_DATA_ALL_PUMP_MPRED ] = { .pme_name = "PM_DATA_ALL_PUMP_MPRED", .pme_code = 0x64c052, .pme_short_desc = "Pump misprediction. Counts across all types of pumps for either demand loads or data prefetch", .pme_long_desc = "Pump Mis prediction Counts across all types of pumpsfor a demand load", }, [ POWER8_PME_PM_DATA_ALL_SYS_PUMP_CPRED ] = { .pme_name = "PM_DATA_ALL_SYS_PUMP_CPRED", .pme_code = 0x63c050, .pme_short_desc = "Initial and Final Pump Scope was system pump (prediction=correct) for either demand loads or data prefetch", .pme_long_desc = "Initial and Final Pump Scope and data sourced across this scope was system pump for a demand load", }, [ POWER8_PME_PM_DATA_ALL_SYS_PUMP_MPRED ] = { .pme_name = "PM_DATA_ALL_SYS_PUMP_MPRED", .pme_code = 0x63c052, .pme_short_desc = "Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for either demand loads or data prefetch", .pme_long_desc = "Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope(Chip/Group) OR Final Pump Scope(system) got data from source that was at smaller scope(Chip/group) Final pump was system pump and initial pump was chip or group or", }, [ POWER8_PME_PM_DATA_ALL_SYS_PUMP_MPRED_RTY ] = { .pme_name = "PM_DATA_ALL_SYS_PUMP_MPRED_RTY", .pme_code = 0x64c050, .pme_short_desc = "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for either demand loads or data prefetch", .pme_long_desc = "Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope (Chip or Group) for a demand load", }, [ POWER8_PME_PM_DATA_CHIP_PUMP_CPRED ] = { .pme_name = "PM_DATA_CHIP_PUMP_CPRED", .pme_code = 0x1c050, .pme_short_desc = "Initial and Final Pump Scope was chip pump (prediction=correct) for a demand load", .pme_long_desc = "Initial and Final Pump Scope and data sourced across this scope was chip pump (prediction=correct) for a demand load.", }, [ POWER8_PME_PM_DATA_FROM_DL2L3_MOD ] = { .pme_name = "PM_DATA_FROM_DL2L3_MOD", .pme_code = 0x4c048, .pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load", .pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.", }, [ POWER8_PME_PM_DATA_FROM_DL2L3_SHR ] = { .pme_name = "PM_DATA_FROM_DL2L3_SHR", .pme_code = 0x3c048, .pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load", .pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.", }, [ POWER8_PME_PM_DATA_FROM_DL4 ] = { .pme_name = "PM_DATA_FROM_DL4", .pme_code = 0x3c04c, .pme_short_desc = "The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to a demand load", .pme_long_desc = "The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.", }, [ POWER8_PME_PM_DATA_FROM_DMEM ] = { .pme_name = "PM_DATA_FROM_DMEM", .pme_code = 0x4c04c, .pme_short_desc = "The processor's data cache was reloaded from another chip's memory on the same Node or Group (Distant) due to a demand load", .pme_long_desc = "The processor's data cache was reloaded from another chip's memory on the same Node or Group (Distant) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.", }, [ POWER8_PME_PM_DATA_FROM_L2 ] = { .pme_name = "PM_DATA_FROM_L2", .pme_code = 0x1c042, .pme_short_desc = "The processor's data cache was reloaded from local core's L2 due to a demand load", .pme_long_desc = "The processor's data cache was reloaded from local core's L2 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.", }, [ POWER8_PME_PM_DATA_FROM_L21_MOD ] = { .pme_name = "PM_DATA_FROM_L21_MOD", .pme_code = 0x4c046, .pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another core's L2 on the same chip due to a demand load", .pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another core's L2 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.", }, [ POWER8_PME_PM_DATA_FROM_L21_SHR ] = { .pme_name = "PM_DATA_FROM_L21_SHR", .pme_code = 0x3c046, .pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to a demand load", .pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.", }, [ POWER8_PME_PM_DATA_FROM_L2MISS ] = { .pme_name = "PM_DATA_FROM_L2MISS", .pme_code = 0x200fe, .pme_short_desc = "Demand LD - L2 Miss (not L2 hit)", .pme_long_desc = "Demand LD - L2 Miss (not L2 hit).", }, [ POWER8_PME_PM_DATA_FROM_L2MISS_MOD ] = { .pme_name = "PM_DATA_FROM_L2MISS_MOD", .pme_code = 0x1c04e, .pme_short_desc = "The processor's data cache was reloaded from a localtion other than the local core's L2 due to a demand load", .pme_long_desc = "The processor's data cache was reloaded from a localtion other than the local core's L2 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.", }, [ POWER8_PME_PM_DATA_FROM_L2_DISP_CONFLICT_LDHITST ] = { .pme_name = "PM_DATA_FROM_L2_DISP_CONFLICT_LDHITST", .pme_code = 0x3c040, .pme_short_desc = "The processor's data cache was reloaded from local core's L2 with load hit store conflict due to a demand load", .pme_long_desc = "The processor's data cache was reloaded from local core's L2 with load hit store conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.", }, [ POWER8_PME_PM_DATA_FROM_L2_DISP_CONFLICT_OTHER ] = { .pme_name = "PM_DATA_FROM_L2_DISP_CONFLICT_OTHER", .pme_code = 0x4c040, .pme_short_desc = "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to a demand load", .pme_long_desc = "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.", }, [ POWER8_PME_PM_DATA_FROM_L2_MEPF ] = { .pme_name = "PM_DATA_FROM_L2_MEPF", .pme_code = 0x2c040, .pme_short_desc = "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state due to a demand load", .pme_long_desc = "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.", }, [ POWER8_PME_PM_DATA_FROM_L2_NO_CONFLICT ] = { .pme_name = "PM_DATA_FROM_L2_NO_CONFLICT", .pme_code = 0x1c040, .pme_short_desc = "The processor's data cache was reloaded from local core's L2 without conflict due to a demand load", .pme_long_desc = "The processor's data cache was reloaded from local core's L2 without conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1 .", }, [ POWER8_PME_PM_DATA_FROM_L3 ] = { .pme_name = "PM_DATA_FROM_L3", .pme_code = 0x4c042, .pme_short_desc = "The processor's data cache was reloaded from local core's L3 due to a demand load", .pme_long_desc = "The processor's data cache was reloaded from local core's L3 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.", }, [ POWER8_PME_PM_DATA_FROM_L31_ECO_MOD ] = { .pme_name = "PM_DATA_FROM_L31_ECO_MOD", .pme_code = 0x4c044, .pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to a demand load", .pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.", }, [ POWER8_PME_PM_DATA_FROM_L31_ECO_SHR ] = { .pme_name = "PM_DATA_FROM_L31_ECO_SHR", .pme_code = 0x3c044, .pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to a demand load", .pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.", }, [ POWER8_PME_PM_DATA_FROM_L31_MOD ] = { .pme_name = "PM_DATA_FROM_L31_MOD", .pme_code = 0x2c044, .pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another core's L3 on the same chip due to a demand load", .pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another core's L3 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.", }, [ POWER8_PME_PM_DATA_FROM_L31_SHR ] = { .pme_name = "PM_DATA_FROM_L31_SHR", .pme_code = 0x1c046, .pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another core's L3 on the same chip due to a demand load", .pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another core's L3 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.", }, [ POWER8_PME_PM_DATA_FROM_L3MISS ] = { .pme_name = "PM_DATA_FROM_L3MISS", .pme_code = 0x300fe, .pme_short_desc = "Demand LD - L3 Miss (not L2 hit and not L3 hit)", .pme_long_desc = "Demand LD - L3 Miss (not L2 hit and not L3 hit).", }, [ POWER8_PME_PM_DATA_FROM_L3MISS_MOD ] = { .pme_name = "PM_DATA_FROM_L3MISS_MOD", .pme_code = 0x4c04e, .pme_short_desc = "The processor's data cache was reloaded from a localtion other than the local core's L3 due to a demand load", .pme_long_desc = "The processor's data cache was reloaded from a localtion other than the local core's L3 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.", }, [ POWER8_PME_PM_DATA_FROM_L3_DISP_CONFLICT ] = { .pme_name = "PM_DATA_FROM_L3_DISP_CONFLICT", .pme_code = 0x3c042, .pme_short_desc = "The processor's data cache was reloaded from local core's L3 with dispatch conflict due to a demand load", .pme_long_desc = "The processor's data cache was reloaded from local core's L3 with dispatch conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.", }, [ POWER8_PME_PM_DATA_FROM_L3_MEPF ] = { .pme_name = "PM_DATA_FROM_L3_MEPF", .pme_code = 0x2c042, .pme_short_desc = "The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state due to a demand load", .pme_long_desc = "The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.", }, [ POWER8_PME_PM_DATA_FROM_L3_NO_CONFLICT ] = { .pme_name = "PM_DATA_FROM_L3_NO_CONFLICT", .pme_code = 0x1c044, .pme_short_desc = "The processor's data cache was reloaded from local core's L3 without conflict due to a demand load", .pme_long_desc = "The processor's data cache was reloaded from local core's L3 without conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.", }, [ POWER8_PME_PM_DATA_FROM_LL4 ] = { .pme_name = "PM_DATA_FROM_LL4", .pme_code = 0x1c04c, .pme_short_desc = "The processor's data cache was reloaded from the local chip's L4 cache due to a demand load", .pme_long_desc = "The processor's data cache was reloaded from the local chip's L4 cache due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.", }, [ POWER8_PME_PM_DATA_FROM_LMEM ] = { .pme_name = "PM_DATA_FROM_LMEM", .pme_code = 0x2c048, .pme_short_desc = "The processor's data cache was reloaded from the local chip's Memory due to a demand load", .pme_long_desc = "The processor's data cache was reloaded from the local chip's Memory due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.", }, [ POWER8_PME_PM_DATA_FROM_MEM ] = { .pme_name = "PM_DATA_FROM_MEM", .pme_code = 0x400fe, .pme_short_desc = "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a demand load", .pme_long_desc = "Data cache reload from memory (including L4).", }, [ POWER8_PME_PM_DATA_FROM_MEMORY ] = { .pme_name = "PM_DATA_FROM_MEMORY", .pme_code = 0x2c04c, .pme_short_desc = "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a demand load", .pme_long_desc = "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.", }, [ POWER8_PME_PM_DATA_FROM_OFF_CHIP_CACHE ] = { .pme_name = "PM_DATA_FROM_OFF_CHIP_CACHE", .pme_code = 0x4c04a, .pme_short_desc = "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a demand load", .pme_long_desc = "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.", }, [ POWER8_PME_PM_DATA_FROM_ON_CHIP_CACHE ] = { .pme_name = "PM_DATA_FROM_ON_CHIP_CACHE", .pme_code = 0x1c048, .pme_short_desc = "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to a demand load", .pme_long_desc = "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.", }, [ POWER8_PME_PM_DATA_FROM_RL2L3_MOD ] = { .pme_name = "PM_DATA_FROM_RL2L3_MOD", .pme_code = 0x2c046, .pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a demand load", .pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.", }, [ POWER8_PME_PM_DATA_FROM_RL2L3_SHR ] = { .pme_name = "PM_DATA_FROM_RL2L3_SHR", .pme_code = 0x1c04a, .pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a demand load", .pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.", }, [ POWER8_PME_PM_DATA_FROM_RL4 ] = { .pme_name = "PM_DATA_FROM_RL4", .pme_code = 0x2c04a, .pme_short_desc = "The processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to a demand load", .pme_long_desc = "The processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.", }, [ POWER8_PME_PM_DATA_FROM_RMEM ] = { .pme_name = "PM_DATA_FROM_RMEM", .pme_code = 0x3c04a, .pme_short_desc = "The processor's data cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to a demand load", .pme_long_desc = "The processor's data cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.", }, [ POWER8_PME_PM_DATA_GRP_PUMP_CPRED ] = { .pme_name = "PM_DATA_GRP_PUMP_CPRED", .pme_code = 0x2c050, .pme_short_desc = "Initial and Final Pump Scope was group pump (prediction=correct) for a demand load", .pme_long_desc = "Initial and Final Pump Scope and data sourced across this scope was group pump for a demand load.", }, [ POWER8_PME_PM_DATA_GRP_PUMP_MPRED ] = { .pme_name = "PM_DATA_GRP_PUMP_MPRED", .pme_code = 0x2c052, .pme_short_desc = "Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for a demand load", .pme_long_desc = "Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope OR Final Pump Scope(Group) got data from source that was at smaller scope(Chip) Final pump was group pump and initial pump was chip or final and initial pump was gro", }, [ POWER8_PME_PM_DATA_GRP_PUMP_MPRED_RTY ] = { .pme_name = "PM_DATA_GRP_PUMP_MPRED_RTY", .pme_code = 0x1c052, .pme_short_desc = "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for a demand load", .pme_long_desc = "Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope (Chip) Final pump was group pump and initial pump was chip pumpfor a demand load.", }, [ POWER8_PME_PM_DATA_PUMP_CPRED ] = { .pme_name = "PM_DATA_PUMP_CPRED", .pme_code = 0x1c054, .pme_short_desc = "Pump prediction correct. Counts across all types of pumps for a demand load", .pme_long_desc = "Pump prediction correct. Counts across all types of pumps for a demand load.", }, [ POWER8_PME_PM_DATA_PUMP_MPRED ] = { .pme_name = "PM_DATA_PUMP_MPRED", .pme_code = 0x4c052, .pme_short_desc = "Pump misprediction. Counts across all types of pumps for a demand load", .pme_long_desc = "Pump Mis prediction Counts across all types of pumpsfor a demand load.", }, [ POWER8_PME_PM_DATA_SYS_PUMP_CPRED ] = { .pme_name = "PM_DATA_SYS_PUMP_CPRED", .pme_code = 0x3c050, .pme_short_desc = "Initial and Final Pump Scope was system pump (prediction=correct) for a demand load", .pme_long_desc = "Initial and Final Pump Scope and data sourced across this scope was system pump for a demand load.", }, [ POWER8_PME_PM_DATA_SYS_PUMP_MPRED ] = { .pme_name = "PM_DATA_SYS_PUMP_MPRED", .pme_code = 0x3c052, .pme_short_desc = "Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for a demand load", .pme_long_desc = "Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope(Chip/Group) OR Final Pump Scope(system) got data from source that was at smaller scope(Chip/group) Final pump was system pump and initial pump was chip or group or", }, [ POWER8_PME_PM_DATA_SYS_PUMP_MPRED_RTY ] = { .pme_name = "PM_DATA_SYS_PUMP_MPRED_RTY", .pme_code = 0x4c050, .pme_short_desc = "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for a demand load", .pme_long_desc = "Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope (Chip or Group) for a demand load.", }, [ POWER8_PME_PM_DATA_TABLEWALK_CYC ] = { .pme_name = "PM_DATA_TABLEWALK_CYC", .pme_code = 0x3001a, .pme_short_desc = "Tablwalk Cycles (could be 1 or 2 active)", .pme_long_desc = "Data Tablewalk Active.", }, [ POWER8_PME_PM_DC_COLLISIONS ] = { .pme_name = "PM_DC_COLLISIONS", .pme_code = 0xe0bc, .pme_short_desc = "DATA Cache collisions", .pme_long_desc = "DATA Cache collisions42", }, [ POWER8_PME_PM_DC_PREF_STREAM_ALLOC ] = { .pme_name = "PM_DC_PREF_STREAM_ALLOC", .pme_code = 0x1e050, .pme_short_desc = "Stream marked valid. The stream could have been allocated through the hardware prefetch mechanism or through software. This is combined ls0 and ls1", .pme_long_desc = "Stream marked valid. The stream could have been allocated through the hardware prefetch mechanism or through software. This is combined ls0 and ls1.", }, [ POWER8_PME_PM_DC_PREF_STREAM_CONF ] = { .pme_name = "PM_DC_PREF_STREAM_CONF", .pme_code = 0x2e050, .pme_short_desc = "A demand load referenced a line in an active prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software. Combine up + down", .pme_long_desc = "A demand load referenced a line in an active prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software. Combine up + down.", }, [ POWER8_PME_PM_DC_PREF_STREAM_FUZZY_CONF ] = { .pme_name = "PM_DC_PREF_STREAM_FUZZY_CONF", .pme_code = 0x4e050, .pme_short_desc = "A demand load referenced a line in an active fuzzy prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software.Fuzzy stream confirm (out of order effects, or pf cant keep up)", .pme_long_desc = "A demand load referenced a line in an active fuzzy prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software.Fuzzy stream confirm (out of order effects, or pf cant keep up).", }, [ POWER8_PME_PM_DC_PREF_STREAM_STRIDED_CONF ] = { .pme_name = "PM_DC_PREF_STREAM_STRIDED_CONF", .pme_code = 0x3e050, .pme_short_desc = "A demand load referenced a line in an active strided prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software.", .pme_long_desc = "A demand load referenced a line in an active strided prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software..", }, [ POWER8_PME_PM_DERAT_MISS_16G ] = { .pme_name = "PM_DERAT_MISS_16G", .pme_code = 0x4c054, .pme_short_desc = "Data ERAT Miss (Data TLB Access) page size 16G", .pme_long_desc = "Data ERAT Miss (Data TLB Access) page size 16G.", }, [ POWER8_PME_PM_DERAT_MISS_16M ] = { .pme_name = "PM_DERAT_MISS_16M", .pme_code = 0x3c054, .pme_short_desc = "Data ERAT Miss (Data TLB Access) page size 16M", .pme_long_desc = "Data ERAT Miss (Data TLB Access) page size 16M.", }, [ POWER8_PME_PM_DERAT_MISS_4K ] = { .pme_name = "PM_DERAT_MISS_4K", .pme_code = 0x1c056, .pme_short_desc = "Data ERAT Miss (Data TLB Access) page size 4K", .pme_long_desc = "Data ERAT Miss (Data TLB Access) page size 4K.", }, [ POWER8_PME_PM_DERAT_MISS_64K ] = { .pme_name = "PM_DERAT_MISS_64K", .pme_code = 0x2c054, .pme_short_desc = "Data ERAT Miss (Data TLB Access) page size 64K", .pme_long_desc = "Data ERAT Miss (Data TLB Access) page size 64K.", }, [ POWER8_PME_PM_DFU ] = { .pme_name = "PM_DFU", .pme_code = 0xb0ba, .pme_short_desc = "Finish DFU (all finish)", .pme_long_desc = "Finish DFU (all finish)", }, [ POWER8_PME_PM_DFU_DCFFIX ] = { .pme_name = "PM_DFU_DCFFIX", .pme_code = 0xb0be, .pme_short_desc = "Convert from fixed opcode finish (dcffix,dcffixq)", .pme_long_desc = "Convert from fixed opcode finish (dcffix,dcffixq)", }, [ POWER8_PME_PM_DFU_DENBCD ] = { .pme_name = "PM_DFU_DENBCD", .pme_code = 0xb0bc, .pme_short_desc = "BCD->DPD opcode finish (denbcd, denbcdq)", .pme_long_desc = "BCD->DPD opcode finish (denbcd, denbcdq)", }, [ POWER8_PME_PM_DFU_MC ] = { .pme_name = "PM_DFU_MC", .pme_code = 0xb0b8, .pme_short_desc = "Finish DFU multicycle", .pme_long_desc = "Finish DFU multicycle", }, [ POWER8_PME_PM_DISP_CLB_HELD_BAL ] = { .pme_name = "PM_DISP_CLB_HELD_BAL", .pme_code = 0x2092, .pme_short_desc = "Dispatch/CLB Hold: Balance", .pme_long_desc = "Dispatch/CLB Hold: Balance", }, [ POWER8_PME_PM_DISP_CLB_HELD_RES ] = { .pme_name = "PM_DISP_CLB_HELD_RES", .pme_code = 0x2094, .pme_short_desc = "Dispatch/CLB Hold: Resource", .pme_long_desc = "Dispatch/CLB Hold: Resource", }, [ POWER8_PME_PM_DISP_CLB_HELD_SB ] = { .pme_name = "PM_DISP_CLB_HELD_SB", .pme_code = 0x20a8, .pme_short_desc = "Dispatch/CLB Hold: Scoreboard", .pme_long_desc = "Dispatch/CLB Hold: Scoreboard", }, [ POWER8_PME_PM_DISP_CLB_HELD_SYNC ] = { .pme_name = "PM_DISP_CLB_HELD_SYNC", .pme_code = 0x2098, .pme_short_desc = "Dispatch/CLB Hold: Sync type instruction", .pme_long_desc = "Dispatch/CLB Hold: Sync type instruction", }, [ POWER8_PME_PM_DISP_CLB_HELD_TLBIE ] = { .pme_name = "PM_DISP_CLB_HELD_TLBIE", .pme_code = 0x2096, .pme_short_desc = "Dispatch Hold: Due to TLBIE", .pme_long_desc = "Dispatch Hold: Due to TLBIE", }, [ POWER8_PME_PM_DISP_HELD ] = { .pme_name = "PM_DISP_HELD", .pme_code = 0x10006, .pme_short_desc = "Dispatch Held", .pme_long_desc = "Dispatch Held.", }, [ POWER8_PME_PM_DISP_HELD_IQ_FULL ] = { .pme_name = "PM_DISP_HELD_IQ_FULL", .pme_code = 0x20006, .pme_short_desc = "Dispatch held due to Issue q full", .pme_long_desc = "Dispatch held due to Issue q full.", }, [ POWER8_PME_PM_DISP_HELD_MAP_FULL ] = { .pme_name = "PM_DISP_HELD_MAP_FULL", .pme_code = 0x1002a, .pme_short_desc = "Dispatch for this thread was held because the Mappers were full", .pme_long_desc = "Dispatch held due to Mapper full.", }, [ POWER8_PME_PM_DISP_HELD_SRQ_FULL ] = { .pme_name = "PM_DISP_HELD_SRQ_FULL", .pme_code = 0x30018, .pme_short_desc = "Dispatch held due SRQ no room", .pme_long_desc = "Dispatch held due SRQ no room.", }, [ POWER8_PME_PM_DISP_HELD_SYNC_HOLD ] = { .pme_name = "PM_DISP_HELD_SYNC_HOLD", .pme_code = 0x4003c, .pme_short_desc = "Dispatch held due to SYNC hold", .pme_long_desc = "Dispatch held due to SYNC hold.", }, [ POWER8_PME_PM_DISP_HOLD_GCT_FULL ] = { .pme_name = "PM_DISP_HOLD_GCT_FULL", .pme_code = 0x30a6, .pme_short_desc = "Dispatch Hold Due to no space in the GCT", .pme_long_desc = "Dispatch Hold Due to no space in the GCT", }, [ POWER8_PME_PM_DISP_WT ] = { .pme_name = "PM_DISP_WT", .pme_code = 0x30008, .pme_short_desc = "Dispatched Starved", .pme_long_desc = "Dispatched Starved (not held, nothing to dispatch).", }, [ POWER8_PME_PM_DPTEG_FROM_DL2L3_MOD ] = { .pme_name = "PM_DPTEG_FROM_DL2L3_MOD", .pme_code = 0x4e048, .pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request.", }, [ POWER8_PME_PM_DPTEG_FROM_DL2L3_SHR ] = { .pme_name = "PM_DPTEG_FROM_DL2L3_SHR", .pme_code = 0x3e048, .pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request.", }, [ POWER8_PME_PM_DPTEG_FROM_DL4 ] = { .pme_name = "PM_DPTEG_FROM_DL4", .pme_code = 0x3e04c, .pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a data side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a data side request.", }, [ POWER8_PME_PM_DPTEG_FROM_DMEM ] = { .pme_name = "PM_DPTEG_FROM_DMEM", .pme_code = 0x4e04c, .pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a data side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a data side request.", }, [ POWER8_PME_PM_DPTEG_FROM_L2 ] = { .pme_name = "PM_DPTEG_FROM_L2", .pme_code = 0x1e042, .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 due to a data side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 due to a data side request.", }, [ POWER8_PME_PM_DPTEG_FROM_L21_MOD ] = { .pme_name = "PM_DPTEG_FROM_L21_MOD", .pme_code = 0x4e046, .pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a data side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a data side request.", }, [ POWER8_PME_PM_DPTEG_FROM_L21_SHR ] = { .pme_name = "PM_DPTEG_FROM_L21_SHR", .pme_code = 0x3e046, .pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a data side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a data side request.", }, [ POWER8_PME_PM_DPTEG_FROM_L2MISS ] = { .pme_name = "PM_DPTEG_FROM_L2MISS", .pme_code = 0x1e04e, .pme_short_desc = "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L2 due to a data side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L2 due to a data side request.", }, [ POWER8_PME_PM_DPTEG_FROM_L2_DISP_CONFLICT_LDHITST ] = { .pme_name = "PM_DPTEG_FROM_L2_DISP_CONFLICT_LDHITST", .pme_code = 0x3e040, .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 with load hit store conflict due to a data side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 with load hit store conflict due to a data side request.", }, [ POWER8_PME_PM_DPTEG_FROM_L2_DISP_CONFLICT_OTHER ] = { .pme_name = "PM_DPTEG_FROM_L2_DISP_CONFLICT_OTHER", .pme_code = 0x4e040, .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 with dispatch conflict due to a data side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 with dispatch conflict due to a data side request.", }, [ POWER8_PME_PM_DPTEG_FROM_L2_MEPF ] = { .pme_name = "PM_DPTEG_FROM_L2_MEPF", .pme_code = 0x2e040, .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a data side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a data side request.", }, [ POWER8_PME_PM_DPTEG_FROM_L2_NO_CONFLICT ] = { .pme_name = "PM_DPTEG_FROM_L2_NO_CONFLICT", .pme_code = 0x1e040, .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a data side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a data side request.", }, [ POWER8_PME_PM_DPTEG_FROM_L3 ] = { .pme_name = "PM_DPTEG_FROM_L3", .pme_code = 0x4e042, .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 due to a data side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 due to a data side request.", }, [ POWER8_PME_PM_DPTEG_FROM_L31_ECO_MOD ] = { .pme_name = "PM_DPTEG_FROM_L31_ECO_MOD", .pme_code = 0x4e044, .pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a data side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a data side request.", }, [ POWER8_PME_PM_DPTEG_FROM_L31_ECO_SHR ] = { .pme_name = "PM_DPTEG_FROM_L31_ECO_SHR", .pme_code = 0x3e044, .pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a data side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a data side request.", }, [ POWER8_PME_PM_DPTEG_FROM_L31_MOD ] = { .pme_name = "PM_DPTEG_FROM_L31_MOD", .pme_code = 0x2e044, .pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a data side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a data side request.", }, [ POWER8_PME_PM_DPTEG_FROM_L31_SHR ] = { .pme_name = "PM_DPTEG_FROM_L31_SHR", .pme_code = 0x1e046, .pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a data side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a data side request.", }, [ POWER8_PME_PM_DPTEG_FROM_L3MISS ] = { .pme_name = "PM_DPTEG_FROM_L3MISS", .pme_code = 0x4e04e, .pme_short_desc = "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L3 due to a data side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L3 due to a data side request.", }, [ POWER8_PME_PM_DPTEG_FROM_L3_DISP_CONFLICT ] = { .pme_name = "PM_DPTEG_FROM_L3_DISP_CONFLICT", .pme_code = 0x3e042, .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a data side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a data side request.", }, [ POWER8_PME_PM_DPTEG_FROM_L3_MEPF ] = { .pme_name = "PM_DPTEG_FROM_L3_MEPF", .pme_code = 0x2e042, .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a data side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a data side request.", }, [ POWER8_PME_PM_DPTEG_FROM_L3_NO_CONFLICT ] = { .pme_name = "PM_DPTEG_FROM_L3_NO_CONFLICT", .pme_code = 0x1e044, .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a data side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a data side request.", }, [ POWER8_PME_PM_DPTEG_FROM_LL4 ] = { .pme_name = "PM_DPTEG_FROM_LL4", .pme_code = 0x1e04c, .pme_short_desc = "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a data side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a data side request.", }, [ POWER8_PME_PM_DPTEG_FROM_LMEM ] = { .pme_name = "PM_DPTEG_FROM_LMEM", .pme_code = 0x2e048, .pme_short_desc = "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a data side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a data side request.", }, [ POWER8_PME_PM_DPTEG_FROM_MEMORY ] = { .pme_name = "PM_DPTEG_FROM_MEMORY", .pme_code = 0x2e04c, .pme_short_desc = "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a data side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a data side request.", }, [ POWER8_PME_PM_DPTEG_FROM_OFF_CHIP_CACHE ] = { .pme_name = "PM_DPTEG_FROM_OFF_CHIP_CACHE", .pme_code = 0x4e04a, .pme_short_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a data side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a data side request.", }, [ POWER8_PME_PM_DPTEG_FROM_ON_CHIP_CACHE ] = { .pme_name = "PM_DPTEG_FROM_ON_CHIP_CACHE", .pme_code = 0x1e048, .pme_short_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a data side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a data side request.", }, [ POWER8_PME_PM_DPTEG_FROM_RL2L3_MOD ] = { .pme_name = "PM_DPTEG_FROM_RL2L3_MOD", .pme_code = 0x2e046, .pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a data side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a data side request.", }, [ POWER8_PME_PM_DPTEG_FROM_RL2L3_SHR ] = { .pme_name = "PM_DPTEG_FROM_RL2L3_SHR", .pme_code = 0x1e04a, .pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a data side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a data side request.", }, [ POWER8_PME_PM_DPTEG_FROM_RL4 ] = { .pme_name = "PM_DPTEG_FROM_RL4", .pme_code = 0x2e04a, .pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a data side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a data side request.", }, [ POWER8_PME_PM_DPTEG_FROM_RMEM ] = { .pme_name = "PM_DPTEG_FROM_RMEM", .pme_code = 0x3e04a, .pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a data side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a data side request.", }, [ POWER8_PME_PM_DSLB_MISS ] = { .pme_name = "PM_DSLB_MISS", .pme_code = 0xd094, .pme_short_desc = "Data SLB Miss - Total of all segment sizes", .pme_long_desc = "Data SLB Miss - Total of all segment sizesData SLB misses", }, [ POWER8_PME_PM_DTLB_MISS ] = { .pme_name = "PM_DTLB_MISS", .pme_code = 0x300fc, .pme_short_desc = "Data PTEG reload", .pme_long_desc = "Data PTEG Reloaded (DTLB Miss).", }, [ POWER8_PME_PM_DTLB_MISS_16G ] = { .pme_name = "PM_DTLB_MISS_16G", .pme_code = 0x1c058, .pme_short_desc = "Data TLB Miss page size 16G", .pme_long_desc = "Data TLB Miss page size 16G.", }, [ POWER8_PME_PM_DTLB_MISS_16M ] = { .pme_name = "PM_DTLB_MISS_16M", .pme_code = 0x4c056, .pme_short_desc = "Data TLB Miss page size 16M", .pme_long_desc = "Data TLB Miss page size 16M.", }, [ POWER8_PME_PM_DTLB_MISS_4K ] = { .pme_name = "PM_DTLB_MISS_4K", .pme_code = 0x2c056, .pme_short_desc = "Data TLB Miss page size 4k", .pme_long_desc = "Data TLB Miss page size 4k.", }, [ POWER8_PME_PM_DTLB_MISS_64K ] = { .pme_name = "PM_DTLB_MISS_64K", .pme_code = 0x3c056, .pme_short_desc = "Data TLB Miss page size 64K", .pme_long_desc = "Data TLB Miss page size 64K.", }, [ POWER8_PME_PM_EAT_FORCE_MISPRED ] = { .pme_name = "PM_EAT_FORCE_MISPRED", .pme_code = 0x50a8, .pme_short_desc = "XL-form branch was mispredicted due to the predicted target address missing from EAT. The EAT forces a mispredict in this case since there is no predicated target to validate. This is a rare case that may occur when the EAT is full and a branch is issue", .pme_long_desc = "XL-form branch was mispredicted due to the predicted target address missing from EAT. The EAT forces a mispredict in this case since there is no predicated target to validate. This is a rare case that may occur when the EAT is full and a branch is", }, [ POWER8_PME_PM_EAT_FULL_CYC ] = { .pme_name = "PM_EAT_FULL_CYC", .pme_code = 0x4084, .pme_short_desc = "Cycles No room in EAT", .pme_long_desc = "Cycles No room in EATSet on bank conflict and case where no ibuffers available.", }, [ POWER8_PME_PM_EE_OFF_EXT_INT ] = { .pme_name = "PM_EE_OFF_EXT_INT", .pme_code = 0x2080, .pme_short_desc = "Ee off and external interrupt", .pme_long_desc = "Ee off and external interrupt", }, [ POWER8_PME_PM_EXT_INT ] = { .pme_name = "PM_EXT_INT", .pme_code = 0x200f8, .pme_short_desc = "external interrupt", .pme_long_desc = "external interrupt.", }, [ POWER8_PME_PM_FAV_TBEGIN ] = { .pme_name = "PM_FAV_TBEGIN", .pme_code = 0x20b4, .pme_short_desc = "Dispatch time Favored tbegin", .pme_long_desc = "Dispatch time Favored tbegin", }, [ POWER8_PME_PM_FLOP ] = { .pme_name = "PM_FLOP", .pme_code = 0x100f4, .pme_short_desc = "Floating Point Operation Finished", .pme_long_desc = "Floating Point Operations Finished.", }, [ POWER8_PME_PM_FLOP_SUM_SCALAR ] = { .pme_name = "PM_FLOP_SUM_SCALAR", .pme_code = 0xa0ae, .pme_short_desc = "flops summary scalar instructions", .pme_long_desc = "flops summary scalar instructions", }, [ POWER8_PME_PM_FLOP_SUM_VEC ] = { .pme_name = "PM_FLOP_SUM_VEC", .pme_code = 0xa0ac, .pme_short_desc = "flops summary vector instructions", .pme_long_desc = "flops summary vector instructions", }, [ POWER8_PME_PM_FLUSH ] = { .pme_name = "PM_FLUSH", .pme_code = 0x400f8, .pme_short_desc = "Flush (any type)", .pme_long_desc = "Flush (any type).", }, [ POWER8_PME_PM_FLUSH_BR_MPRED ] = { .pme_name = "PM_FLUSH_BR_MPRED", .pme_code = 0x2084, .pme_short_desc = "Flush caused by branch mispredict", .pme_long_desc = "Flush caused by branch mispredict", }, [ POWER8_PME_PM_FLUSH_COMPLETION ] = { .pme_name = "PM_FLUSH_COMPLETION", .pme_code = 0x30012, .pme_short_desc = "Completion Flush", .pme_long_desc = "Completion Flush.", }, [ POWER8_PME_PM_FLUSH_DISP ] = { .pme_name = "PM_FLUSH_DISP", .pme_code = 0x2082, .pme_short_desc = "Dispatch flush", .pme_long_desc = "Dispatch flush", }, [ POWER8_PME_PM_FLUSH_DISP_SB ] = { .pme_name = "PM_FLUSH_DISP_SB", .pme_code = 0x208c, .pme_short_desc = "Dispatch Flush: Scoreboard", .pme_long_desc = "Dispatch Flush: Scoreboard", }, [ POWER8_PME_PM_FLUSH_DISP_SYNC ] = { .pme_name = "PM_FLUSH_DISP_SYNC", .pme_code = 0x2088, .pme_short_desc = "Dispatch Flush: Sync", .pme_long_desc = "Dispatch Flush: Sync", }, [ POWER8_PME_PM_FLUSH_DISP_TLBIE ] = { .pme_name = "PM_FLUSH_DISP_TLBIE", .pme_code = 0x208a, .pme_short_desc = "Dispatch Flush: TLBIE", .pme_long_desc = "Dispatch Flush: TLBIE", }, [ POWER8_PME_PM_FLUSH_LSU ] = { .pme_name = "PM_FLUSH_LSU", .pme_code = 0x208e, .pme_short_desc = "Flush initiated by LSU", .pme_long_desc = "Flush initiated by LSU", }, [ POWER8_PME_PM_FLUSH_PARTIAL ] = { .pme_name = "PM_FLUSH_PARTIAL", .pme_code = 0x2086, .pme_short_desc = "Partial flush", .pme_long_desc = "Partial flush", }, [ POWER8_PME_PM_FPU0_FCONV ] = { .pme_name = "PM_FPU0_FCONV", .pme_code = 0xa0b0, .pme_short_desc = "Convert instruction executed", .pme_long_desc = "Convert instruction executed", }, [ POWER8_PME_PM_FPU0_FEST ] = { .pme_name = "PM_FPU0_FEST", .pme_code = 0xa0b8, .pme_short_desc = "Estimate instruction executed", .pme_long_desc = "Estimate instruction executed", }, [ POWER8_PME_PM_FPU0_FRSP ] = { .pme_name = "PM_FPU0_FRSP", .pme_code = 0xa0b4, .pme_short_desc = "Round to single precision instruction executed", .pme_long_desc = "Round to single precision instruction executed", }, [ POWER8_PME_PM_FPU1_FCONV ] = { .pme_name = "PM_FPU1_FCONV", .pme_code = 0xa0b2, .pme_short_desc = "Convert instruction executed", .pme_long_desc = "Convert instruction executed", }, [ POWER8_PME_PM_FPU1_FEST ] = { .pme_name = "PM_FPU1_FEST", .pme_code = 0xa0ba, .pme_short_desc = "Estimate instruction executed", .pme_long_desc = "Estimate instruction executed", }, [ POWER8_PME_PM_FPU1_FRSP ] = { .pme_name = "PM_FPU1_FRSP", .pme_code = 0xa0b6, .pme_short_desc = "Round to single precision instruction executed", .pme_long_desc = "Round to single precision instruction executed", }, [ POWER8_PME_PM_FREQ_DOWN ] = { .pme_name = "PM_FREQ_DOWN", .pme_code = 0x3000c, .pme_short_desc = "Power Management: Below Threshold B", .pme_long_desc = "Frequency is being slewed down due to Power Management.", }, [ POWER8_PME_PM_FREQ_UP ] = { .pme_name = "PM_FREQ_UP", .pme_code = 0x4000c, .pme_short_desc = "Power Management: Above Threshold A", .pme_long_desc = "Frequency is being slewed up due to Power Management.", }, [ POWER8_PME_PM_FUSION_TOC_GRP0_1 ] = { .pme_name = "PM_FUSION_TOC_GRP0_1", .pme_code = 0x50b0, .pme_short_desc = "One pair of instructions fused with TOC in Group0", .pme_long_desc = "One pair of instructions fused with TOC in Group0", }, [ POWER8_PME_PM_FUSION_TOC_GRP0_2 ] = { .pme_name = "PM_FUSION_TOC_GRP0_2", .pme_code = 0x50ae, .pme_short_desc = "Two pairs of instructions fused with TOCin Group0", .pme_long_desc = "Two pairs of instructions fused with TOCin Group0", }, [ POWER8_PME_PM_FUSION_TOC_GRP0_3 ] = { .pme_name = "PM_FUSION_TOC_GRP0_3", .pme_code = 0x50ac, .pme_short_desc = "Three pairs of instructions fused with TOC in Group0", .pme_long_desc = "Three pairs of instructions fused with TOC in Group0", }, [ POWER8_PME_PM_FUSION_TOC_GRP1_1 ] = { .pme_name = "PM_FUSION_TOC_GRP1_1", .pme_code = 0x50b2, .pme_short_desc = "One pair of instructions fused with TOX in Group1", .pme_long_desc = "One pair of instructions fused with TOX in Group1", }, [ POWER8_PME_PM_FUSION_VSX_GRP0_1 ] = { .pme_name = "PM_FUSION_VSX_GRP0_1", .pme_code = 0x50b8, .pme_short_desc = "One pair of instructions fused with VSX in Group0", .pme_long_desc = "One pair of instructions fused with VSX in Group0", }, [ POWER8_PME_PM_FUSION_VSX_GRP0_2 ] = { .pme_name = "PM_FUSION_VSX_GRP0_2", .pme_code = 0x50b6, .pme_short_desc = "Two pairs of instructions fused with VSX in Group0", .pme_long_desc = "Two pairs of instructions fused with VSX in Group0", }, [ POWER8_PME_PM_FUSION_VSX_GRP0_3 ] = { .pme_name = "PM_FUSION_VSX_GRP0_3", .pme_code = 0x50b4, .pme_short_desc = "Three pairs of instructions fused with VSX in Group0", .pme_long_desc = "Three pairs of instructions fused with VSX in Group0", }, [ POWER8_PME_PM_FUSION_VSX_GRP1_1 ] = { .pme_name = "PM_FUSION_VSX_GRP1_1", .pme_code = 0x50ba, .pme_short_desc = "One pair of instructions fused with VSX in Group1", .pme_long_desc = "One pair of instructions fused with VSX in Group1", }, [ POWER8_PME_PM_FXU0_BUSY_FXU1_IDLE ] = { .pme_name = "PM_FXU0_BUSY_FXU1_IDLE", .pme_code = 0x3000e, .pme_short_desc = "fxu0 busy and fxu1 idle", .pme_long_desc = "fxu0 busy and fxu1 idle.", }, [ POWER8_PME_PM_FXU0_FIN ] = { .pme_name = "PM_FXU0_FIN", .pme_code = 0x10004, .pme_short_desc = "The fixed point unit Unit 0 finished an instruction. Instructions that finish may not necessary complete.", .pme_long_desc = "FXU0 Finished.", }, [ POWER8_PME_PM_FXU1_BUSY_FXU0_IDLE ] = { .pme_name = "PM_FXU1_BUSY_FXU0_IDLE", .pme_code = 0x4000e, .pme_short_desc = "fxu0 idle and fxu1 busy.", .pme_long_desc = "fxu0 idle and fxu1 busy. .", }, [ POWER8_PME_PM_FXU1_FIN ] = { .pme_name = "PM_FXU1_FIN", .pme_code = 0x40004, .pme_short_desc = "FXU1 Finished", .pme_long_desc = "FXU1 Finished.", }, [ POWER8_PME_PM_FXU_BUSY ] = { .pme_name = "PM_FXU_BUSY", .pme_code = 0x2000e, .pme_short_desc = "fxu0 busy and fxu1 busy.", .pme_long_desc = "fxu0 busy and fxu1 busy..", }, [ POWER8_PME_PM_FXU_IDLE ] = { .pme_name = "PM_FXU_IDLE", .pme_code = 0x1000e, .pme_short_desc = "fxu0 idle and fxu1 idle", .pme_long_desc = "fxu0 idle and fxu1 idle.", }, [ POWER8_PME_PM_GCT_EMPTY_CYC ] = { .pme_name = "PM_GCT_EMPTY_CYC", .pme_code = 0x20008, .pme_short_desc = "No itags assigned either thread (GCT Empty)", .pme_long_desc = "No itags assigned either thread (GCT Empty).", }, [ POWER8_PME_PM_GCT_MERGE ] = { .pme_name = "PM_GCT_MERGE", .pme_code = 0x30a4, .pme_short_desc = "Group dispatched on a merged GCT empty. GCT entries can be merged only within the same thread", .pme_long_desc = "Group dispatched on a merged GCT empty. GCT entries can be merged only within the same thread", }, [ POWER8_PME_PM_GCT_NOSLOT_BR_MPRED ] = { .pme_name = "PM_GCT_NOSLOT_BR_MPRED", .pme_code = 0x4d01e, .pme_short_desc = "Gct empty for this thread due to branch mispred", .pme_long_desc = "Gct empty for this thread due to branch mispred.", }, [ POWER8_PME_PM_GCT_NOSLOT_BR_MPRED_ICMISS ] = { .pme_name = "PM_GCT_NOSLOT_BR_MPRED_ICMISS", .pme_code = 0x4d01a, .pme_short_desc = "Gct empty for this thread due to Icache Miss and branch mispred", .pme_long_desc = "Gct empty for this thread due to Icache Miss and branch mispred.", }, [ POWER8_PME_PM_GCT_NOSLOT_CYC ] = { .pme_name = "PM_GCT_NOSLOT_CYC", .pme_code = 0x100f8, .pme_short_desc = "No itags assigned", .pme_long_desc = "Pipeline empty (No itags assigned , no GCT slots used).", }, [ POWER8_PME_PM_GCT_NOSLOT_DISP_HELD_ISSQ ] = { .pme_name = "PM_GCT_NOSLOT_DISP_HELD_ISSQ", .pme_code = 0x2d01e, .pme_short_desc = "Gct empty for this thread due to dispatch hold on this thread due to Issue q full", .pme_long_desc = "Gct empty for this thread due to dispatch hold on this thread due to Issue q full.", }, [ POWER8_PME_PM_GCT_NOSLOT_DISP_HELD_MAP ] = { .pme_name = "PM_GCT_NOSLOT_DISP_HELD_MAP", .pme_code = 0x4d01c, .pme_short_desc = "Gct empty for this thread due to dispatch hold on this thread due to Mapper full", .pme_long_desc = "Gct empty for this thread due to dispatch hold on this thread due to Mapper full.", }, [ POWER8_PME_PM_GCT_NOSLOT_DISP_HELD_OTHER ] = { .pme_name = "PM_GCT_NOSLOT_DISP_HELD_OTHER", .pme_code = 0x2e010, .pme_short_desc = "Gct empty for this thread due to dispatch hold on this thread due to sync", .pme_long_desc = "Gct empty for this thread due to dispatch hold on this thread due to sync.", }, [ POWER8_PME_PM_GCT_NOSLOT_DISP_HELD_SRQ ] = { .pme_name = "PM_GCT_NOSLOT_DISP_HELD_SRQ", .pme_code = 0x2d01c, .pme_short_desc = "Gct empty for this thread due to dispatch hold on this thread due to SRQ full", .pme_long_desc = "Gct empty for this thread due to dispatch hold on this thread due to SRQ full.", }, [ POWER8_PME_PM_GCT_NOSLOT_IC_L3MISS ] = { .pme_name = "PM_GCT_NOSLOT_IC_L3MISS", .pme_code = 0x4e010, .pme_short_desc = "Gct empty for this thread due to icach l3 miss", .pme_long_desc = "Gct empty for this thread due to icach l3 miss.", }, [ POWER8_PME_PM_GCT_NOSLOT_IC_MISS ] = { .pme_name = "PM_GCT_NOSLOT_IC_MISS", .pme_code = 0x2d01a, .pme_short_desc = "Gct empty for this thread due to Icache Miss", .pme_long_desc = "Gct empty for this thread due to Icache Miss.", }, [ POWER8_PME_PM_GCT_UTIL_11_14_ENTRIES ] = { .pme_name = "PM_GCT_UTIL_11_14_ENTRIES", .pme_code = 0x20a2, .pme_short_desc = "GCT Utilization 11-14 entries", .pme_long_desc = "GCT Utilization 11-14 entries", }, [ POWER8_PME_PM_GCT_UTIL_15_17_ENTRIES ] = { .pme_name = "PM_GCT_UTIL_15_17_ENTRIES", .pme_code = 0x20a4, .pme_short_desc = "GCT Utilization 15-17 entries", .pme_long_desc = "GCT Utilization 15-17 entries", }, [ POWER8_PME_PM_GCT_UTIL_18_ENTRIES ] = { .pme_name = "PM_GCT_UTIL_18_ENTRIES", .pme_code = 0x20a6, .pme_short_desc = "GCT Utilization 18+ entries", .pme_long_desc = "GCT Utilization 18+ entries", }, [ POWER8_PME_PM_GCT_UTIL_1_2_ENTRIES ] = { .pme_name = "PM_GCT_UTIL_1_2_ENTRIES", .pme_code = 0x209c, .pme_short_desc = "GCT Utilization 1-2 entries", .pme_long_desc = "GCT Utilization 1-2 entries", }, [ POWER8_PME_PM_GCT_UTIL_3_6_ENTRIES ] = { .pme_name = "PM_GCT_UTIL_3_6_ENTRIES", .pme_code = 0x209e, .pme_short_desc = "GCT Utilization 3-6 entries", .pme_long_desc = "GCT Utilization 3-6 entries", }, [ POWER8_PME_PM_GCT_UTIL_7_10_ENTRIES ] = { .pme_name = "PM_GCT_UTIL_7_10_ENTRIES", .pme_code = 0x20a0, .pme_short_desc = "GCT Utilization 7-10 entries", .pme_long_desc = "GCT Utilization 7-10 entries", }, [ POWER8_PME_PM_GRP_BR_MPRED_NONSPEC ] = { .pme_name = "PM_GRP_BR_MPRED_NONSPEC", .pme_code = 0x1000a, .pme_short_desc = "Group experienced non-speculative branch redirect", .pme_long_desc = "Group experienced Non-speculative br mispredicct.", }, [ POWER8_PME_PM_GRP_CMPL ] = { .pme_name = "PM_GRP_CMPL", .pme_code = 0x30004, .pme_short_desc = "group completed", .pme_long_desc = "group completed.", }, [ POWER8_PME_PM_GRP_DISP ] = { .pme_name = "PM_GRP_DISP", .pme_code = 0x3000a, .pme_short_desc = "group dispatch", .pme_long_desc = "dispatch_success (Group Dispatched).", }, [ POWER8_PME_PM_GRP_IC_MISS_NONSPEC ] = { .pme_name = "PM_GRP_IC_MISS_NONSPEC", .pme_code = 0x1000c, .pme_short_desc = "Group experienced non-speculative I cache miss", .pme_long_desc = "Group experi enced Non-specu lative I cache miss.", }, [ POWER8_PME_PM_GRP_MRK ] = { .pme_name = "PM_GRP_MRK", .pme_code = 0x10130, .pme_short_desc = "Instruction Marked", .pme_long_desc = "Instruction marked in idu.", }, [ POWER8_PME_PM_GRP_NON_FULL_GROUP ] = { .pme_name = "PM_GRP_NON_FULL_GROUP", .pme_code = 0x509c, .pme_short_desc = "GROUPs where we did not have 6 non branch instructions in the group(ST mode), in SMT mode 3 non branches", .pme_long_desc = "GROUPs where we did not have 6 non branch instructions in the group(ST mode), in SMT mode 3 non branches", }, [ POWER8_PME_PM_GRP_PUMP_CPRED ] = { .pme_name = "PM_GRP_PUMP_CPRED", .pme_code = 0x20050, .pme_short_desc = "Initial and Final Pump Scope and data sourced across this scope was group pump for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)", .pme_long_desc = "Initial and Final Pump Scope and data sourced across this scope was group pump for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate).", }, [ POWER8_PME_PM_GRP_PUMP_MPRED ] = { .pme_name = "PM_GRP_PUMP_MPRED", .pme_code = 0x20052, .pme_short_desc = "Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)", .pme_long_desc = "Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope OR Final Pump Scope(Group) got data from source that was at smaller scope(Chip) Final pump was group pump and initial pump was chip or final and initial pump was gro", }, [ POWER8_PME_PM_GRP_PUMP_MPRED_RTY ] = { .pme_name = "PM_GRP_PUMP_MPRED_RTY", .pme_code = 0x10052, .pme_short_desc = "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)", .pme_long_desc = "Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope (Chip) Final pump was group pump and initial pump was chip pumpfor all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate).", }, [ POWER8_PME_PM_GRP_TERM_2ND_BRANCH ] = { .pme_name = "PM_GRP_TERM_2ND_BRANCH", .pme_code = 0x50a4, .pme_short_desc = "There were enough instructions in the Ibuffer, but 2nd branch ends group", .pme_long_desc = "There were enough instructions in the Ibuffer, but 2nd branch ends group", }, [ POWER8_PME_PM_GRP_TERM_FPU_AFTER_BR ] = { .pme_name = "PM_GRP_TERM_FPU_AFTER_BR", .pme_code = 0x50a6, .pme_short_desc = "There were enough instructions in the Ibuffer, but FPU OP IN same group after a branch terminates a group, cant do partial flushes", .pme_long_desc = "There were enough instructions in the Ibuffer, but FPU OP IN same group after a branch terminates a group, cant do partial flushes", }, [ POWER8_PME_PM_GRP_TERM_NOINST ] = { .pme_name = "PM_GRP_TERM_NOINST", .pme_code = 0x509e, .pme_short_desc = "Do not fill every slot in the group, Not enough instructions in the Ibuffer. This includes cases where the group started with enough instructions, but some got knocked out by a cache miss or branch redirect (which would also empty the Ibuffer).", .pme_long_desc = "Do not fill every slot in the group, Not enough instructions in the Ibuffer. This includes cases where the group started with enough instructions, but some got knocked out by a cache miss or branch redirect (which would also empty the Ibuffer).", }, [ POWER8_PME_PM_GRP_TERM_OTHER ] = { .pme_name = "PM_GRP_TERM_OTHER", .pme_code = 0x50a0, .pme_short_desc = "There were enough instructions in the Ibuffer, but the group terminated early for some other reason, most likely due to a First or Last.", .pme_long_desc = "There were enough instructions in the Ibuffer, but the group terminated early for some other reason, most likely due to a First or Last.", }, [ POWER8_PME_PM_GRP_TERM_SLOT_LIMIT ] = { .pme_name = "PM_GRP_TERM_SLOT_LIMIT", .pme_code = 0x50a2, .pme_short_desc = "There were enough instructions in the Ibuffer, but 3 src RA/RB/RC , 2 way crack caused a group termination", .pme_long_desc = "There were enough instructions in the Ibuffer, but 3 src RA/RB/RC , 2 way crack caused a group termination", }, [ POWER8_PME_PM_HV_CYC ] = { .pme_name = "PM_HV_CYC", .pme_code = 0x2000a, .pme_short_desc = "Cycles in which msr_hv is high. Note that this event does not take msr_pr into consideration", .pme_long_desc = "cycles in hypervisor mode .", }, [ POWER8_PME_PM_IBUF_FULL_CYC ] = { .pme_name = "PM_IBUF_FULL_CYC", .pme_code = 0x4086, .pme_short_desc = "Cycles No room in ibuff", .pme_long_desc = "Cycles No room in ibufffully qualified tranfer (if5 valid).", }, [ POWER8_PME_PM_IC_DEMAND_CYC ] = { .pme_name = "PM_IC_DEMAND_CYC", .pme_code = 0x10018, .pme_short_desc = "Cycles when a demand ifetch was pending", .pme_long_desc = "Demand ifetch pending.", }, [ POWER8_PME_PM_IC_DEMAND_L2_BHT_REDIRECT ] = { .pme_name = "PM_IC_DEMAND_L2_BHT_REDIRECT", .pme_code = 0x4098, .pme_short_desc = "L2 I cache demand request due to BHT redirect, branch redirect ( 2 bubbles 3 cycles)", .pme_long_desc = "L2 I cache demand request due to BHT redirect, branch redirect ( 2 bubbles 3 cycles)", }, [ POWER8_PME_PM_IC_DEMAND_L2_BR_REDIRECT ] = { .pme_name = "PM_IC_DEMAND_L2_BR_REDIRECT", .pme_code = 0x409a, .pme_short_desc = "L2 I cache demand request due to branch Mispredict ( 15 cycle path)", .pme_long_desc = "L2 I cache demand request due to branch Mispredict ( 15 cycle path)", }, [ POWER8_PME_PM_IC_DEMAND_REQ ] = { .pme_name = "PM_IC_DEMAND_REQ", .pme_code = 0x4088, .pme_short_desc = "Demand Instruction fetch request", .pme_long_desc = "Demand Instruction fetch request", }, [ POWER8_PME_PM_IC_INVALIDATE ] = { .pme_name = "PM_IC_INVALIDATE", .pme_code = 0x508a, .pme_short_desc = "Ic line invalidated", .pme_long_desc = "Ic line invalidated", }, [ POWER8_PME_PM_IC_PREF_CANCEL_HIT ] = { .pme_name = "PM_IC_PREF_CANCEL_HIT", .pme_code = 0x4092, .pme_short_desc = "Prefetch Canceled due to icache hit", .pme_long_desc = "Prefetch Canceled due to icache hit", }, [ POWER8_PME_PM_IC_PREF_CANCEL_L2 ] = { .pme_name = "PM_IC_PREF_CANCEL_L2", .pme_code = 0x4094, .pme_short_desc = "L2 Squashed request", .pme_long_desc = "L2 Squashed request", }, [ POWER8_PME_PM_IC_PREF_CANCEL_PAGE ] = { .pme_name = "PM_IC_PREF_CANCEL_PAGE", .pme_code = 0x4090, .pme_short_desc = "Prefetch Canceled due to page boundary", .pme_long_desc = "Prefetch Canceled due to page boundary", }, [ POWER8_PME_PM_IC_PREF_REQ ] = { .pme_name = "PM_IC_PREF_REQ", .pme_code = 0x408a, .pme_short_desc = "Instruction prefetch requests", .pme_long_desc = "Instruction prefetch requests", }, [ POWER8_PME_PM_IC_PREF_WRITE ] = { .pme_name = "PM_IC_PREF_WRITE", .pme_code = 0x408e, .pme_short_desc = "Instruction prefetch written into IL1", .pme_long_desc = "Instruction prefetch written into IL1", }, [ POWER8_PME_PM_IC_RELOAD_PRIVATE ] = { .pme_name = "PM_IC_RELOAD_PRIVATE", .pme_code = 0x4096, .pme_short_desc = "Reloading line was brought in private for a specific thread. Most lines are brought in shared for all eight thrreads. If RA does not match then invalidates and then brings it shared to other thread. In P7 line brought in private , then line was invalidat", .pme_long_desc = "Reloading line was brought in private for a specific thread. Most lines are brought in shared for all eight thrreads. If RA does not match then invalidates and then brings it shared to other thread. In P7 line brought in private , then line was inv", }, [ POWER8_PME_PM_IERAT_RELOAD ] = { .pme_name = "PM_IERAT_RELOAD", .pme_code = 0x100f6, .pme_short_desc = "Number of I-ERAT reloads", .pme_long_desc = "IERAT Reloaded (Miss).", }, [ POWER8_PME_PM_IERAT_RELOAD_16M ] = { .pme_name = "PM_IERAT_RELOAD_16M", .pme_code = 0x4006a, .pme_short_desc = "IERAT Reloaded (Miss) for a 16M page", .pme_long_desc = "IERAT Reloaded (Miss) for a 16M page.", }, [ POWER8_PME_PM_IERAT_RELOAD_4K ] = { .pme_name = "PM_IERAT_RELOAD_4K", .pme_code = 0x20064, .pme_short_desc = "IERAT Miss (Not implemented as DI on POWER6)", .pme_long_desc = "IERAT Reloaded (Miss) for a 4k page.", }, [ POWER8_PME_PM_IERAT_RELOAD_64K ] = { .pme_name = "PM_IERAT_RELOAD_64K", .pme_code = 0x3006a, .pme_short_desc = "IERAT Reloaded (Miss) for a 64k page", .pme_long_desc = "IERAT Reloaded (Miss) for a 64k page.", }, [ POWER8_PME_PM_IFETCH_THROTTLE ] = { .pme_name = "PM_IFETCH_THROTTLE", .pme_code = 0x3405e, .pme_short_desc = "Cycles in which Instruction fetch throttle was active", .pme_long_desc = "Cycles instruction fecth was throttled in IFU.", }, [ POWER8_PME_PM_IFU_L2_TOUCH ] = { .pme_name = "PM_IFU_L2_TOUCH", .pme_code = 0x5088, .pme_short_desc = "L2 touch to update MRU on a line", .pme_long_desc = "L2 touch to update MRU on a line", }, [ POWER8_PME_PM_INST_ALL_CHIP_PUMP_CPRED ] = { .pme_name = "PM_INST_ALL_CHIP_PUMP_CPRED", .pme_code = 0x514050, .pme_short_desc = "Initial and Final Pump Scope was chip pump (prediction=correct) for instruction fetches and prefetches", .pme_long_desc = "Initial and Final Pump Scope and data sourced across this scope was chip pump (prediction=correct) for an instruction fetch", }, [ POWER8_PME_PM_INST_ALL_FROM_DL2L3_MOD ] = { .pme_name = "PM_INST_ALL_FROM_DL2L3_MOD", .pme_code = 0x544048, .pme_short_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to instruction fetches and prefetches", .pme_long_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1", }, [ POWER8_PME_PM_INST_ALL_FROM_DL2L3_SHR ] = { .pme_name = "PM_INST_ALL_FROM_DL2L3_SHR", .pme_code = 0x534048, .pme_short_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to instruction fetches and prefetches", .pme_long_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1", }, [ POWER8_PME_PM_INST_ALL_FROM_DL4 ] = { .pme_name = "PM_INST_ALL_FROM_DL4", .pme_code = 0x53404c, .pme_short_desc = "The processor's Instruction cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to instruction fetches and prefetches", .pme_long_desc = "The processor's Instruction cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1", }, [ POWER8_PME_PM_INST_ALL_FROM_DMEM ] = { .pme_name = "PM_INST_ALL_FROM_DMEM", .pme_code = 0x54404c, .pme_short_desc = "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group (Distant) due to instruction fetches and prefetches", .pme_long_desc = "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group (Distant) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1", }, [ POWER8_PME_PM_INST_ALL_FROM_L2 ] = { .pme_name = "PM_INST_ALL_FROM_L2", .pme_code = 0x514042, .pme_short_desc = "The processor's Instruction cache was reloaded from local core's L2 due to instruction fetches and prefetches", .pme_long_desc = "The processor's Instruction cache was reloaded from local core's L2 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1", }, [ POWER8_PME_PM_INST_ALL_FROM_L21_MOD ] = { .pme_name = "PM_INST_ALL_FROM_L21_MOD", .pme_code = 0x544046, .pme_short_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another core's L2 on the same chip due to instruction fetches and prefetches", .pme_long_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another core's L2 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1", }, [ POWER8_PME_PM_INST_ALL_FROM_L21_SHR ] = { .pme_name = "PM_INST_ALL_FROM_L21_SHR", .pme_code = 0x534046, .pme_short_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another core's L2 on the same chip due to instruction fetches and prefetches", .pme_long_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another core's L2 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1", }, [ POWER8_PME_PM_INST_ALL_FROM_L2MISS ] = { .pme_name = "PM_INST_ALL_FROM_L2MISS", .pme_code = 0x51404e, .pme_short_desc = "The processor's Instruction cache was reloaded from a localtion other than the local core's L2 due to instruction fetches and prefetches", .pme_long_desc = "The processor's Instruction cache was reloaded from a localtion other than the local core's L2 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1", }, [ POWER8_PME_PM_INST_ALL_FROM_L2_DISP_CONFLICT_LDHITST ] = { .pme_name = "PM_INST_ALL_FROM_L2_DISP_CONFLICT_LDHITST", .pme_code = 0x534040, .pme_short_desc = "The processor's Instruction cache was reloaded from local core's L2 with load hit store conflict due to instruction fetches and prefetches", .pme_long_desc = "The processor's Instruction cache was reloaded from local core's L2 with load hit store conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1", }, [ POWER8_PME_PM_INST_ALL_FROM_L2_DISP_CONFLICT_OTHER ] = { .pme_name = "PM_INST_ALL_FROM_L2_DISP_CONFLICT_OTHER", .pme_code = 0x544040, .pme_short_desc = "The processor's Instruction cache was reloaded from local core's L2 with dispatch conflict due to instruction fetches and prefetches", .pme_long_desc = "The processor's Instruction cache was reloaded from local core's L2 with dispatch conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1", }, [ POWER8_PME_PM_INST_ALL_FROM_L2_MEPF ] = { .pme_name = "PM_INST_ALL_FROM_L2_MEPF", .pme_code = 0x524040, .pme_short_desc = "The processor's Instruction cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state. due to instruction fetches and prefetches", .pme_long_desc = "The processor's Instruction cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state. due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1", }, [ POWER8_PME_PM_INST_ALL_FROM_L2_NO_CONFLICT ] = { .pme_name = "PM_INST_ALL_FROM_L2_NO_CONFLICT", .pme_code = 0x514040, .pme_short_desc = "The processor's Instruction cache was reloaded from local core's L2 without conflict due to instruction fetches and prefetches", .pme_long_desc = "The processor's Instruction cache was reloaded from local core's L2 without conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1", }, [ POWER8_PME_PM_INST_ALL_FROM_L3 ] = { .pme_name = "PM_INST_ALL_FROM_L3", .pme_code = 0x544042, .pme_short_desc = "The processor's Instruction cache was reloaded from local core's L3 due to instruction fetches and prefetches", .pme_long_desc = "The processor's Instruction cache was reloaded from local core's L3 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1", }, [ POWER8_PME_PM_INST_ALL_FROM_L31_ECO_MOD ] = { .pme_name = "PM_INST_ALL_FROM_L31_ECO_MOD", .pme_code = 0x544044, .pme_short_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to instruction fetches and prefetches", .pme_long_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1", }, [ POWER8_PME_PM_INST_ALL_FROM_L31_ECO_SHR ] = { .pme_name = "PM_INST_ALL_FROM_L31_ECO_SHR", .pme_code = 0x534044, .pme_short_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to instruction fetches and prefetches", .pme_long_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1", }, [ POWER8_PME_PM_INST_ALL_FROM_L31_MOD ] = { .pme_name = "PM_INST_ALL_FROM_L31_MOD", .pme_code = 0x524044, .pme_short_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another core's L3 on the same chip due to instruction fetches and prefetches", .pme_long_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another core's L3 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1", }, [ POWER8_PME_PM_INST_ALL_FROM_L31_SHR ] = { .pme_name = "PM_INST_ALL_FROM_L31_SHR", .pme_code = 0x514046, .pme_short_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another core's L3 on the same chip due to instruction fetches and prefetches", .pme_long_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another core's L3 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1", }, [ POWER8_PME_PM_INST_ALL_FROM_L3MISS_MOD ] = { .pme_name = "PM_INST_ALL_FROM_L3MISS_MOD", .pme_code = 0x54404e, .pme_short_desc = "The processor's Instruction cache was reloaded from a localtion other than the local core's L3 due to a instruction fetch", .pme_long_desc = "The processor's Instruction cache was reloaded from a localtion other than the local core's L3 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1", }, [ POWER8_PME_PM_INST_ALL_FROM_L3_DISP_CONFLICT ] = { .pme_name = "PM_INST_ALL_FROM_L3_DISP_CONFLICT", .pme_code = 0x534042, .pme_short_desc = "The processor's Instruction cache was reloaded from local core's L3 with dispatch conflict due to instruction fetches and prefetches", .pme_long_desc = "The processor's Instruction cache was reloaded from local core's L3 with dispatch conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1", }, [ POWER8_PME_PM_INST_ALL_FROM_L3_MEPF ] = { .pme_name = "PM_INST_ALL_FROM_L3_MEPF", .pme_code = 0x524042, .pme_short_desc = "The processor's Instruction cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to instruction fetches and prefetches", .pme_long_desc = "The processor's Instruction cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1", }, [ POWER8_PME_PM_INST_ALL_FROM_L3_NO_CONFLICT ] = { .pme_name = "PM_INST_ALL_FROM_L3_NO_CONFLICT", .pme_code = 0x514044, .pme_short_desc = "The processor's Instruction cache was reloaded from local core's L3 without conflict due to instruction fetches and prefetches", .pme_long_desc = "The processor's Instruction cache was reloaded from local core's L3 without conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1", }, [ POWER8_PME_PM_INST_ALL_FROM_LL4 ] = { .pme_name = "PM_INST_ALL_FROM_LL4", .pme_code = 0x51404c, .pme_short_desc = "The processor's Instruction cache was reloaded from the local chip's L4 cache due to instruction fetches and prefetches", .pme_long_desc = "The processor's Instruction cache was reloaded from the local chip's L4 cache due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1", }, [ POWER8_PME_PM_INST_ALL_FROM_LMEM ] = { .pme_name = "PM_INST_ALL_FROM_LMEM", .pme_code = 0x524048, .pme_short_desc = "The processor's Instruction cache was reloaded from the local chip's Memory due to instruction fetches and prefetches", .pme_long_desc = "The processor's Instruction cache was reloaded from the local chip's Memory due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1", }, [ POWER8_PME_PM_INST_ALL_FROM_MEMORY ] = { .pme_name = "PM_INST_ALL_FROM_MEMORY", .pme_code = 0x52404c, .pme_short_desc = "The processor's Instruction cache was reloaded from a memory location including L4 from local remote or distant due to instruction fetches and prefetches", .pme_long_desc = "The processor's Instruction cache was reloaded from a memory location including L4 from local remote or distant due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1", }, [ POWER8_PME_PM_INST_ALL_FROM_OFF_CHIP_CACHE ] = { .pme_name = "PM_INST_ALL_FROM_OFF_CHIP_CACHE", .pme_code = 0x54404a, .pme_short_desc = "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to instruction fetches and prefetches", .pme_long_desc = "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1", }, [ POWER8_PME_PM_INST_ALL_FROM_ON_CHIP_CACHE ] = { .pme_name = "PM_INST_ALL_FROM_ON_CHIP_CACHE", .pme_code = 0x514048, .pme_short_desc = "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to instruction fetches and prefetches", .pme_long_desc = "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1", }, [ POWER8_PME_PM_INST_ALL_FROM_RL2L3_MOD ] = { .pme_name = "PM_INST_ALL_FROM_RL2L3_MOD", .pme_code = 0x524046, .pme_short_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to instruction fetches and prefetches", .pme_long_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1", }, [ POWER8_PME_PM_INST_ALL_FROM_RL2L3_SHR ] = { .pme_name = "PM_INST_ALL_FROM_RL2L3_SHR", .pme_code = 0x51404a, .pme_short_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to instruction fetches and prefetches", .pme_long_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1", }, [ POWER8_PME_PM_INST_ALL_FROM_RL4 ] = { .pme_name = "PM_INST_ALL_FROM_RL4", .pme_code = 0x52404a, .pme_short_desc = "The processor's Instruction cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to instruction fetches and prefetches", .pme_long_desc = "The processor's Instruction cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1", }, [ POWER8_PME_PM_INST_ALL_FROM_RMEM ] = { .pme_name = "PM_INST_ALL_FROM_RMEM", .pme_code = 0x53404a, .pme_short_desc = "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to instruction fetches and prefetches", .pme_long_desc = "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1", }, [ POWER8_PME_PM_INST_ALL_GRP_PUMP_CPRED ] = { .pme_name = "PM_INST_ALL_GRP_PUMP_CPRED", .pme_code = 0x524050, .pme_short_desc = "Initial and Final Pump Scope was group pump (prediction=correct) for instruction fetches and prefetches", .pme_long_desc = "Initial and Final Pump Scope and data sourced across this scope was group pump for an instruction fetch", }, [ POWER8_PME_PM_INST_ALL_GRP_PUMP_MPRED ] = { .pme_name = "PM_INST_ALL_GRP_PUMP_MPRED", .pme_code = 0x524052, .pme_short_desc = "Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for instruction fetches and prefetches", .pme_long_desc = "Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope OR Final Pump Scope(Group) got data from source that was at smaller scope(Chip) Final pump was group pump and initial pump was chip or final and initial pump was gro", }, [ POWER8_PME_PM_INST_ALL_GRP_PUMP_MPRED_RTY ] = { .pme_name = "PM_INST_ALL_GRP_PUMP_MPRED_RTY", .pme_code = 0x514052, .pme_short_desc = "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for instruction fetches and prefetches", .pme_long_desc = "Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope (Chip) Final pump was group pump and initial pump was chip pumpfor an instruction fetch", }, [ POWER8_PME_PM_INST_ALL_PUMP_CPRED ] = { .pme_name = "PM_INST_ALL_PUMP_CPRED", .pme_code = 0x514054, .pme_short_desc = "Pump prediction correct. Counts across all types of pumps for instruction fetches and prefetches", .pme_long_desc = "Pump prediction correct. Counts across all types of pumpsfor an instruction fetch", }, [ POWER8_PME_PM_INST_ALL_PUMP_MPRED ] = { .pme_name = "PM_INST_ALL_PUMP_MPRED", .pme_code = 0x544052, .pme_short_desc = "Pump misprediction. Counts across all types of pumps for instruction fetches and prefetches", .pme_long_desc = "Pump Mis prediction Counts across all types of pumpsfor an instruction fetch", }, [ POWER8_PME_PM_INST_ALL_SYS_PUMP_CPRED ] = { .pme_name = "PM_INST_ALL_SYS_PUMP_CPRED", .pme_code = 0x534050, .pme_short_desc = "Initial and Final Pump Scope was system pump (prediction=correct) for instruction fetches and prefetches", .pme_long_desc = "Initial and Final Pump Scope and data sourced across this scope was system pump for an instruction fetch", }, [ POWER8_PME_PM_INST_ALL_SYS_PUMP_MPRED ] = { .pme_name = "PM_INST_ALL_SYS_PUMP_MPRED", .pme_code = 0x534052, .pme_short_desc = "Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for instruction fetches and prefetches", .pme_long_desc = "Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope(Chip/Group) OR Final Pump Scope(system) got data from source that was at smaller scope(Chip/group) Final pump was system pump and initial pump was chip or group or", }, [ POWER8_PME_PM_INST_ALL_SYS_PUMP_MPRED_RTY ] = { .pme_name = "PM_INST_ALL_SYS_PUMP_MPRED_RTY", .pme_code = 0x544050, .pme_short_desc = "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for instruction fetches and prefetches", .pme_long_desc = "Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope (Chip or Group) for an instruction fetch", }, [ POWER8_PME_PM_INST_CHIP_PUMP_CPRED ] = { .pme_name = "PM_INST_CHIP_PUMP_CPRED", .pme_code = 0x14050, .pme_short_desc = "Initial and Final Pump Scope was chip pump (prediction=correct) for an instruction fetch", .pme_long_desc = "Initial and Final Pump Scope and data sourced across this scope was chip pump (prediction=correct) for an instruction fetch.", }, [ POWER8_PME_PM_INST_CMPL ] = { .pme_name = "PM_INST_CMPL", .pme_code = 0x2, .pme_short_desc = "Number of PowerPC Instructions that completed.", .pme_long_desc = "PPC Instructions Finished (completed).", }, [ POWER8_PME_PM_INST_DISP ] = { .pme_name = "PM_INST_DISP", .pme_code = 0x200f2, .pme_short_desc = "PPC Dispatched", .pme_long_desc = "PPC Dispatched.", }, [ POWER8_PME_PM_INST_FROM_DL2L3_MOD ] = { .pme_name = "PM_INST_FROM_DL2L3_MOD", .pme_code = 0x44048, .pme_short_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to an instruction fetch (not prefetch)", .pme_long_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .", }, [ POWER8_PME_PM_INST_FROM_DL2L3_SHR ] = { .pme_name = "PM_INST_FROM_DL2L3_SHR", .pme_code = 0x34048, .pme_short_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to an instruction fetch (not prefetch)", .pme_long_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .", }, [ POWER8_PME_PM_INST_FROM_DL4 ] = { .pme_name = "PM_INST_FROM_DL4", .pme_code = 0x3404c, .pme_short_desc = "The processor's Instruction cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to an instruction fetch (not prefetch)", .pme_long_desc = "The processor's Instruction cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .", }, [ POWER8_PME_PM_INST_FROM_DMEM ] = { .pme_name = "PM_INST_FROM_DMEM", .pme_code = 0x4404c, .pme_short_desc = "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group (Distant) due to an instruction fetch (not prefetch)", .pme_long_desc = "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group (Distant) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .", }, [ POWER8_PME_PM_INST_FROM_L1 ] = { .pme_name = "PM_INST_FROM_L1", .pme_code = 0x4080, .pme_short_desc = "Instruction fetches from L1", .pme_long_desc = "Instruction fetches from L1", }, [ POWER8_PME_PM_INST_FROM_L2 ] = { .pme_name = "PM_INST_FROM_L2", .pme_code = 0x14042, .pme_short_desc = "The processor's Instruction cache was reloaded from local core's L2 due to an instruction fetch (not prefetch)", .pme_long_desc = "The processor's Instruction cache was reloaded from local core's L2 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .", }, [ POWER8_PME_PM_INST_FROM_L21_MOD ] = { .pme_name = "PM_INST_FROM_L21_MOD", .pme_code = 0x44046, .pme_short_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another core's L2 on the same chip due to an instruction fetch (not prefetch)", .pme_long_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another core's L2 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .", }, [ POWER8_PME_PM_INST_FROM_L21_SHR ] = { .pme_name = "PM_INST_FROM_L21_SHR", .pme_code = 0x34046, .pme_short_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another core's L2 on the same chip due to an instruction fetch (not prefetch)", .pme_long_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another core's L2 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .", }, [ POWER8_PME_PM_INST_FROM_L2MISS ] = { .pme_name = "PM_INST_FROM_L2MISS", .pme_code = 0x1404e, .pme_short_desc = "The processor's Instruction cache was reloaded from a localtion other than the local core's L2 due to an instruction fetch (not prefetch)", .pme_long_desc = "The processor's Instruction cache was reloaded from a localtion other than the local core's L2 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .", }, [ POWER8_PME_PM_INST_FROM_L2_DISP_CONFLICT_LDHITST ] = { .pme_name = "PM_INST_FROM_L2_DISP_CONFLICT_LDHITST", .pme_code = 0x34040, .pme_short_desc = "The processor's Instruction cache was reloaded from local core's L2 with load hit store conflict due to an instruction fetch (not prefetch)", .pme_long_desc = "The processor's Instruction cache was reloaded from local core's L2 with load hit store conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .", }, [ POWER8_PME_PM_INST_FROM_L2_DISP_CONFLICT_OTHER ] = { .pme_name = "PM_INST_FROM_L2_DISP_CONFLICT_OTHER", .pme_code = 0x44040, .pme_short_desc = "The processor's Instruction cache was reloaded from local core's L2 with dispatch conflict due to an instruction fetch (not prefetch)", .pme_long_desc = "The processor's Instruction cache was reloaded from local core's L2 with dispatch conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .", }, [ POWER8_PME_PM_INST_FROM_L2_MEPF ] = { .pme_name = "PM_INST_FROM_L2_MEPF", .pme_code = 0x24040, .pme_short_desc = "The processor's Instruction cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state. due to an instruction fetch (not prefetch)", .pme_long_desc = "The processor's Instruction cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state. due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .", }, [ POWER8_PME_PM_INST_FROM_L2_NO_CONFLICT ] = { .pme_name = "PM_INST_FROM_L2_NO_CONFLICT", .pme_code = 0x14040, .pme_short_desc = "The processor's Instruction cache was reloaded from local core's L2 without conflict due to an instruction fetch (not prefetch)", .pme_long_desc = "The processor's Instruction cache was reloaded from local core's L2 without conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .", }, [ POWER8_PME_PM_INST_FROM_L3 ] = { .pme_name = "PM_INST_FROM_L3", .pme_code = 0x44042, .pme_short_desc = "The processor's Instruction cache was reloaded from local core's L3 due to an instruction fetch (not prefetch)", .pme_long_desc = "The processor's Instruction cache was reloaded from local core's L3 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .", }, [ POWER8_PME_PM_INST_FROM_L31_ECO_MOD ] = { .pme_name = "PM_INST_FROM_L31_ECO_MOD", .pme_code = 0x44044, .pme_short_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to an instruction fetch (not prefetch)", .pme_long_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .", }, [ POWER8_PME_PM_INST_FROM_L31_ECO_SHR ] = { .pme_name = "PM_INST_FROM_L31_ECO_SHR", .pme_code = 0x34044, .pme_short_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to an instruction fetch (not prefetch)", .pme_long_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .", }, [ POWER8_PME_PM_INST_FROM_L31_MOD ] = { .pme_name = "PM_INST_FROM_L31_MOD", .pme_code = 0x24044, .pme_short_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another core's L3 on the same chip due to an instruction fetch (not prefetch)", .pme_long_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another core's L3 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .", }, [ POWER8_PME_PM_INST_FROM_L31_SHR ] = { .pme_name = "PM_INST_FROM_L31_SHR", .pme_code = 0x14046, .pme_short_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another core's L3 on the same chip due to an instruction fetch (not prefetch)", .pme_long_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another core's L3 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .", }, [ POWER8_PME_PM_INST_FROM_L3MISS ] = { .pme_name = "PM_INST_FROM_L3MISS", .pme_code = 0x300fa, .pme_short_desc = "Marked instruction was reloaded from a location beyond the local chiplet", .pme_long_desc = "Inst from L3 miss.", }, [ POWER8_PME_PM_INST_FROM_L3MISS_MOD ] = { .pme_name = "PM_INST_FROM_L3MISS_MOD", .pme_code = 0x4404e, .pme_short_desc = "The processor's Instruction cache was reloaded from a localtion other than the local core's L3 due to a instruction fetch", .pme_long_desc = "The processor's Instruction cache was reloaded from a localtion other than the local core's L3 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .", }, [ POWER8_PME_PM_INST_FROM_L3_DISP_CONFLICT ] = { .pme_name = "PM_INST_FROM_L3_DISP_CONFLICT", .pme_code = 0x34042, .pme_short_desc = "The processor's Instruction cache was reloaded from local core's L3 with dispatch conflict due to an instruction fetch (not prefetch)", .pme_long_desc = "The processor's Instruction cache was reloaded from local core's L3 with dispatch conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .", }, [ POWER8_PME_PM_INST_FROM_L3_MEPF ] = { .pme_name = "PM_INST_FROM_L3_MEPF", .pme_code = 0x24042, .pme_short_desc = "The processor's Instruction cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to an instruction fetch (not prefetch)", .pme_long_desc = "The processor's Instruction cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .", }, [ POWER8_PME_PM_INST_FROM_L3_NO_CONFLICT ] = { .pme_name = "PM_INST_FROM_L3_NO_CONFLICT", .pme_code = 0x14044, .pme_short_desc = "The processor's Instruction cache was reloaded from local core's L3 without conflict due to an instruction fetch (not prefetch)", .pme_long_desc = "The processor's Instruction cache was reloaded from local core's L3 without conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .", }, [ POWER8_PME_PM_INST_FROM_LL4 ] = { .pme_name = "PM_INST_FROM_LL4", .pme_code = 0x1404c, .pme_short_desc = "The processor's Instruction cache was reloaded from the local chip's L4 cache due to an instruction fetch (not prefetch)", .pme_long_desc = "The processor's Instruction cache was reloaded from the local chip's L4 cache due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .", }, [ POWER8_PME_PM_INST_FROM_LMEM ] = { .pme_name = "PM_INST_FROM_LMEM", .pme_code = 0x24048, .pme_short_desc = "The processor's Instruction cache was reloaded from the local chip's Memory due to an instruction fetch (not prefetch)", .pme_long_desc = "The processor's Instruction cache was reloaded from the local chip's Memory due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .", }, [ POWER8_PME_PM_INST_FROM_MEMORY ] = { .pme_name = "PM_INST_FROM_MEMORY", .pme_code = 0x2404c, .pme_short_desc = "The processor's Instruction cache was reloaded from a memory location including L4 from local remote or distant due to an instruction fetch (not prefetch)", .pme_long_desc = "The processor's Instruction cache was reloaded from a memory location including L4 from local remote or distant due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .", }, [ POWER8_PME_PM_INST_FROM_OFF_CHIP_CACHE ] = { .pme_name = "PM_INST_FROM_OFF_CHIP_CACHE", .pme_code = 0x4404a, .pme_short_desc = "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to an instruction fetch (not prefetch)", .pme_long_desc = "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .", }, [ POWER8_PME_PM_INST_FROM_ON_CHIP_CACHE ] = { .pme_name = "PM_INST_FROM_ON_CHIP_CACHE", .pme_code = 0x14048, .pme_short_desc = "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to an instruction fetch (not prefetch)", .pme_long_desc = "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .", }, [ POWER8_PME_PM_INST_FROM_RL2L3_MOD ] = { .pme_name = "PM_INST_FROM_RL2L3_MOD", .pme_code = 0x24046, .pme_short_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction fetch (not prefetch)", .pme_long_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .", }, [ POWER8_PME_PM_INST_FROM_RL2L3_SHR ] = { .pme_name = "PM_INST_FROM_RL2L3_SHR", .pme_code = 0x1404a, .pme_short_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction fetch (not prefetch)", .pme_long_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .", }, [ POWER8_PME_PM_INST_FROM_RL4 ] = { .pme_name = "PM_INST_FROM_RL4", .pme_code = 0x2404a, .pme_short_desc = "The processor's Instruction cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to an instruction fetch (not prefetch)", .pme_long_desc = "The processor's Instruction cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .", }, [ POWER8_PME_PM_INST_FROM_RMEM ] = { .pme_name = "PM_INST_FROM_RMEM", .pme_code = 0x3404a, .pme_short_desc = "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to an instruction fetch (not prefetch)", .pme_long_desc = "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .", }, [ POWER8_PME_PM_INST_GRP_PUMP_CPRED ] = { .pme_name = "PM_INST_GRP_PUMP_CPRED", .pme_code = 0x24050, .pme_short_desc = "Initial and Final Pump Scope was group pump (prediction=correct) for an instruction fetch", .pme_long_desc = "Initial and Final Pump Scope and data sourced across this scope was group pump for an instruction fetch.", }, [ POWER8_PME_PM_INST_GRP_PUMP_MPRED ] = { .pme_name = "PM_INST_GRP_PUMP_MPRED", .pme_code = 0x24052, .pme_short_desc = "Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for an instruction fetch", .pme_long_desc = "Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope OR Final Pump Scope(Group) got data from source that was at smaller scope(Chip) Final pump was group pump and initial pump was chip or final and initial pump was gro", }, [ POWER8_PME_PM_INST_GRP_PUMP_MPRED_RTY ] = { .pme_name = "PM_INST_GRP_PUMP_MPRED_RTY", .pme_code = 0x14052, .pme_short_desc = "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for an instruction fetch", .pme_long_desc = "Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope (Chip) Final pump was group pump and initial pump was chip pumpfor an instruction fetch.", }, [ POWER8_PME_PM_INST_IMC_MATCH_CMPL ] = { .pme_name = "PM_INST_IMC_MATCH_CMPL", .pme_code = 0x1003a, .pme_short_desc = "IMC Match Count ( Not architected in P8)", .pme_long_desc = "IMC Match Count.", }, [ POWER8_PME_PM_INST_IMC_MATCH_DISP ] = { .pme_name = "PM_INST_IMC_MATCH_DISP", .pme_code = 0x30016, .pme_short_desc = "Matched Instructions Dispatched", .pme_long_desc = "IMC Matches dispatched.", }, [ POWER8_PME_PM_INST_PUMP_CPRED ] = { .pme_name = "PM_INST_PUMP_CPRED", .pme_code = 0x14054, .pme_short_desc = "Pump prediction correct. Counts across all types of pumps for an instruction fetch", .pme_long_desc = "Pump prediction correct. Counts across all types of pumpsfor an instruction fetch.", }, [ POWER8_PME_PM_INST_PUMP_MPRED ] = { .pme_name = "PM_INST_PUMP_MPRED", .pme_code = 0x44052, .pme_short_desc = "Pump misprediction. Counts across all types of pumps for an instruction fetch", .pme_long_desc = "Pump Mis prediction Counts across all types of pumpsfor an instruction fetch.", }, [ POWER8_PME_PM_INST_SYS_PUMP_CPRED ] = { .pme_name = "PM_INST_SYS_PUMP_CPRED", .pme_code = 0x34050, .pme_short_desc = "Initial and Final Pump Scope was system pump (prediction=correct) for an instruction fetch", .pme_long_desc = "Initial and Final Pump Scope and data sourced across this scope was system pump for an instruction fetch.", }, [ POWER8_PME_PM_INST_SYS_PUMP_MPRED ] = { .pme_name = "PM_INST_SYS_PUMP_MPRED", .pme_code = 0x34052, .pme_short_desc = "Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for an instruction fetch", .pme_long_desc = "Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope(Chip/Group) OR Final Pump Scope(system) got data from source that was at smaller scope(Chip/group) Final pump was system pump and initial pump was chip or group or", }, [ POWER8_PME_PM_INST_SYS_PUMP_MPRED_RTY ] = { .pme_name = "PM_INST_SYS_PUMP_MPRED_RTY", .pme_code = 0x44050, .pme_short_desc = "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for an instruction fetch", .pme_long_desc = "Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope (Chip or Group) for an instruction fetch.", }, [ POWER8_PME_PM_IOPS_CMPL ] = { .pme_name = "PM_IOPS_CMPL", .pme_code = 0x10014, .pme_short_desc = "Internal Operations completed", .pme_long_desc = "IOPS Completed.", }, [ POWER8_PME_PM_IOPS_DISP ] = { .pme_name = "PM_IOPS_DISP", .pme_code = 0x30014, .pme_short_desc = "Internal Operations dispatched", .pme_long_desc = "IOPS dispatched.", }, [ POWER8_PME_PM_IPTEG_FROM_DL2L3_MOD ] = { .pme_name = "PM_IPTEG_FROM_DL2L3_MOD", .pme_code = 0x45048, .pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a instruction side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a instruction side request.", }, [ POWER8_PME_PM_IPTEG_FROM_DL2L3_SHR ] = { .pme_name = "PM_IPTEG_FROM_DL2L3_SHR", .pme_code = 0x35048, .pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a instruction side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a instruction side request.", }, [ POWER8_PME_PM_IPTEG_FROM_DL4 ] = { .pme_name = "PM_IPTEG_FROM_DL4", .pme_code = 0x3504c, .pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a instruction side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a instruction side request.", }, [ POWER8_PME_PM_IPTEG_FROM_DMEM ] = { .pme_name = "PM_IPTEG_FROM_DMEM", .pme_code = 0x4504c, .pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a instruction side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a instruction side request.", }, [ POWER8_PME_PM_IPTEG_FROM_L2 ] = { .pme_name = "PM_IPTEG_FROM_L2", .pme_code = 0x15042, .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 due to a instruction side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 due to a instruction side request.", }, [ POWER8_PME_PM_IPTEG_FROM_L21_MOD ] = { .pme_name = "PM_IPTEG_FROM_L21_MOD", .pme_code = 0x45046, .pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a instruction side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a instruction side request.", }, [ POWER8_PME_PM_IPTEG_FROM_L21_SHR ] = { .pme_name = "PM_IPTEG_FROM_L21_SHR", .pme_code = 0x35046, .pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a instruction side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a instruction side request.", }, [ POWER8_PME_PM_IPTEG_FROM_L2MISS ] = { .pme_name = "PM_IPTEG_FROM_L2MISS", .pme_code = 0x1504e, .pme_short_desc = "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L2 due to a instruction side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L2 due to a instruction side request.", }, [ POWER8_PME_PM_IPTEG_FROM_L2_DISP_CONFLICT_LDHITST ] = { .pme_name = "PM_IPTEG_FROM_L2_DISP_CONFLICT_LDHITST", .pme_code = 0x35040, .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 with load hit store conflict due to a instruction side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 with load hit store conflict due to a instruction side request.", }, [ POWER8_PME_PM_IPTEG_FROM_L2_DISP_CONFLICT_OTHER ] = { .pme_name = "PM_IPTEG_FROM_L2_DISP_CONFLICT_OTHER", .pme_code = 0x45040, .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 with dispatch conflict due to a instruction side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 with dispatch conflict due to a instruction side request.", }, [ POWER8_PME_PM_IPTEG_FROM_L2_MEPF ] = { .pme_name = "PM_IPTEG_FROM_L2_MEPF", .pme_code = 0x25040, .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a instruction side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a instruction side request.", }, [ POWER8_PME_PM_IPTEG_FROM_L2_NO_CONFLICT ] = { .pme_name = "PM_IPTEG_FROM_L2_NO_CONFLICT", .pme_code = 0x15040, .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a instruction side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a instruction side request.", }, [ POWER8_PME_PM_IPTEG_FROM_L3 ] = { .pme_name = "PM_IPTEG_FROM_L3", .pme_code = 0x45042, .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 due to a instruction side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 due to a instruction side request.", }, [ POWER8_PME_PM_IPTEG_FROM_L31_ECO_MOD ] = { .pme_name = "PM_IPTEG_FROM_L31_ECO_MOD", .pme_code = 0x45044, .pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a instruction side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a instruction side request.", }, [ POWER8_PME_PM_IPTEG_FROM_L31_ECO_SHR ] = { .pme_name = "PM_IPTEG_FROM_L31_ECO_SHR", .pme_code = 0x35044, .pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a instruction side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a instruction side request.", }, [ POWER8_PME_PM_IPTEG_FROM_L31_MOD ] = { .pme_name = "PM_IPTEG_FROM_L31_MOD", .pme_code = 0x25044, .pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a instruction side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a instruction side request.", }, [ POWER8_PME_PM_IPTEG_FROM_L31_SHR ] = { .pme_name = "PM_IPTEG_FROM_L31_SHR", .pme_code = 0x15046, .pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a instruction side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a instruction side request.", }, [ POWER8_PME_PM_IPTEG_FROM_L3MISS ] = { .pme_name = "PM_IPTEG_FROM_L3MISS", .pme_code = 0x4504e, .pme_short_desc = "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L3 due to a instruction side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L3 due to a instruction side request.", }, [ POWER8_PME_PM_IPTEG_FROM_L3_DISP_CONFLICT ] = { .pme_name = "PM_IPTEG_FROM_L3_DISP_CONFLICT", .pme_code = 0x35042, .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a instruction side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a instruction side request.", }, [ POWER8_PME_PM_IPTEG_FROM_L3_MEPF ] = { .pme_name = "PM_IPTEG_FROM_L3_MEPF", .pme_code = 0x25042, .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a instruction side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a instruction side request.", }, [ POWER8_PME_PM_IPTEG_FROM_L3_NO_CONFLICT ] = { .pme_name = "PM_IPTEG_FROM_L3_NO_CONFLICT", .pme_code = 0x15044, .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a instruction side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a instruction side request.", }, [ POWER8_PME_PM_IPTEG_FROM_LL4 ] = { .pme_name = "PM_IPTEG_FROM_LL4", .pme_code = 0x1504c, .pme_short_desc = "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a instruction side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a instruction side request.", }, [ POWER8_PME_PM_IPTEG_FROM_LMEM ] = { .pme_name = "PM_IPTEG_FROM_LMEM", .pme_code = 0x25048, .pme_short_desc = "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a instruction side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a instruction side request.", }, [ POWER8_PME_PM_IPTEG_FROM_MEMORY ] = { .pme_name = "PM_IPTEG_FROM_MEMORY", .pme_code = 0x2504c, .pme_short_desc = "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a instruction side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a instruction side request.", }, [ POWER8_PME_PM_IPTEG_FROM_OFF_CHIP_CACHE ] = { .pme_name = "PM_IPTEG_FROM_OFF_CHIP_CACHE", .pme_code = 0x4504a, .pme_short_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a instruction side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a instruction side request.", }, [ POWER8_PME_PM_IPTEG_FROM_ON_CHIP_CACHE ] = { .pme_name = "PM_IPTEG_FROM_ON_CHIP_CACHE", .pme_code = 0x15048, .pme_short_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a instruction side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a instruction side request.", }, [ POWER8_PME_PM_IPTEG_FROM_RL2L3_MOD ] = { .pme_name = "PM_IPTEG_FROM_RL2L3_MOD", .pme_code = 0x25046, .pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request.", }, [ POWER8_PME_PM_IPTEG_FROM_RL2L3_SHR ] = { .pme_name = "PM_IPTEG_FROM_RL2L3_SHR", .pme_code = 0x1504a, .pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request.", }, [ POWER8_PME_PM_IPTEG_FROM_RL4 ] = { .pme_name = "PM_IPTEG_FROM_RL4", .pme_code = 0x2504a, .pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a instruction side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a instruction side request.", }, [ POWER8_PME_PM_IPTEG_FROM_RMEM ] = { .pme_name = "PM_IPTEG_FROM_RMEM", .pme_code = 0x3504a, .pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a instruction side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a instruction side request.", }, [ POWER8_PME_PM_ISIDE_DISP ] = { .pme_name = "PM_ISIDE_DISP", .pme_code = 0x617082, .pme_short_desc = "All i-side dispatch attempts", .pme_long_desc = "All i-side dispatch attempts", }, [ POWER8_PME_PM_ISIDE_DISP_FAIL ] = { .pme_name = "PM_ISIDE_DISP_FAIL", .pme_code = 0x627084, .pme_short_desc = "All i-side dispatch attempts that failed due to a addr collision with another machine", .pme_long_desc = "All i-side dispatch attempts that failed due to a addr collision with another machine", }, [ POWER8_PME_PM_ISIDE_DISP_FAIL_OTHER ] = { .pme_name = "PM_ISIDE_DISP_FAIL_OTHER", .pme_code = 0x627086, .pme_short_desc = "All i-side dispatch attempts that failed due to a reason other than addrs collision", .pme_long_desc = "All i-side dispatch attempts that failed due to a reason other than addrs collision", }, [ POWER8_PME_PM_ISIDE_L2MEMACC ] = { .pme_name = "PM_ISIDE_L2MEMACC", .pme_code = 0x4608e, .pme_short_desc = "valid when first beat of data comes in for an i-side fetch where data came from mem(or L4)", .pme_long_desc = "valid when first beat of data comes in for an i-side fetch where data came from mem(or L4)", }, [ POWER8_PME_PM_ISIDE_MRU_TOUCH ] = { .pme_name = "PM_ISIDE_MRU_TOUCH", .pme_code = 0x44608e, .pme_short_desc = "Iside L2 MRU touch", .pme_long_desc = "Iside L2 MRU touch", }, [ POWER8_PME_PM_ISLB_MISS ] = { .pme_name = "PM_ISLB_MISS", .pme_code = 0xd096, .pme_short_desc = "I SLB Miss.", .pme_long_desc = "I SLB Miss.", }, [ POWER8_PME_PM_ISU_REF_FX0 ] = { .pme_name = "PM_ISU_REF_FX0", .pme_code = 0x30ac, .pme_short_desc = "FX0 ISU reject", .pme_long_desc = "FX0 ISU reject", }, [ POWER8_PME_PM_ISU_REF_FX1 ] = { .pme_name = "PM_ISU_REF_FX1", .pme_code = 0x30ae, .pme_short_desc = "FX1 ISU reject", .pme_long_desc = "FX1 ISU reject", }, [ POWER8_PME_PM_ISU_REF_FXU ] = { .pme_name = "PM_ISU_REF_FXU", .pme_code = 0x38ac, .pme_short_desc = "FXU ISU reject from either pipe", .pme_long_desc = "ISU", }, [ POWER8_PME_PM_ISU_REF_LS0 ] = { .pme_name = "PM_ISU_REF_LS0", .pme_code = 0x30b0, .pme_short_desc = "LS0 ISU reject", .pme_long_desc = "LS0 ISU reject", }, [ POWER8_PME_PM_ISU_REF_LS1 ] = { .pme_name = "PM_ISU_REF_LS1", .pme_code = 0x30b2, .pme_short_desc = "LS1 ISU reject", .pme_long_desc = "LS1 ISU reject", }, [ POWER8_PME_PM_ISU_REF_LS2 ] = { .pme_name = "PM_ISU_REF_LS2", .pme_code = 0x30b4, .pme_short_desc = "LS2 ISU reject", .pme_long_desc = "LS2 ISU reject", }, [ POWER8_PME_PM_ISU_REF_LS3 ] = { .pme_name = "PM_ISU_REF_LS3", .pme_code = 0x30b6, .pme_short_desc = "LS3 ISU reject", .pme_long_desc = "LS3 ISU reject", }, [ POWER8_PME_PM_ISU_REJECTS_ALL ] = { .pme_name = "PM_ISU_REJECTS_ALL", .pme_code = 0x309c, .pme_short_desc = "All isu rejects could be more than 1 per cycle", .pme_long_desc = "All isu rejects could be more than 1 per cycle", }, [ POWER8_PME_PM_ISU_REJECT_RES_NA ] = { .pme_name = "PM_ISU_REJECT_RES_NA", .pme_code = 0x30a2, .pme_short_desc = "ISU reject due to resource not available", .pme_long_desc = "ISU reject due to resource not available", }, [ POWER8_PME_PM_ISU_REJECT_SAR_BYPASS ] = { .pme_name = "PM_ISU_REJECT_SAR_BYPASS", .pme_code = 0x309e, .pme_short_desc = "Reject because of SAR bypass", .pme_long_desc = "Reject because of SAR bypass", }, [ POWER8_PME_PM_ISU_REJECT_SRC_NA ] = { .pme_name = "PM_ISU_REJECT_SRC_NA", .pme_code = 0x30a0, .pme_short_desc = "ISU reject due to source not available", .pme_long_desc = "ISU reject due to source not available", }, [ POWER8_PME_PM_ISU_REJ_VS0 ] = { .pme_name = "PM_ISU_REJ_VS0", .pme_code = 0x30a8, .pme_short_desc = "VS0 ISU reject", .pme_long_desc = "VS0 ISU reject", }, [ POWER8_PME_PM_ISU_REJ_VS1 ] = { .pme_name = "PM_ISU_REJ_VS1", .pme_code = 0x30aa, .pme_short_desc = "VS1 ISU reject", .pme_long_desc = "VS1 ISU reject", }, [ POWER8_PME_PM_ISU_REJ_VSU ] = { .pme_name = "PM_ISU_REJ_VSU", .pme_code = 0x38a8, .pme_short_desc = "VSU ISU reject from either pipe", .pme_long_desc = "ISU", }, [ POWER8_PME_PM_ISYNC ] = { .pme_name = "PM_ISYNC", .pme_code = 0x30b8, .pme_short_desc = "Isync count per thread", .pme_long_desc = "Isync count per thread", }, [ POWER8_PME_PM_ITLB_MISS ] = { .pme_name = "PM_ITLB_MISS", .pme_code = 0x400fc, .pme_short_desc = "ITLB Reloaded (always zero on POWER6)", .pme_long_desc = "ITLB Reloaded.", }, [ POWER8_PME_PM_L1MISS_LAT_EXC_1024 ] = { .pme_name = "PM_L1MISS_LAT_EXC_1024", .pme_code = 0x67200301eaull, .pme_short_desc = "L1 misses that took longer than 1024 cyles to resolve (miss to reload)", .pme_long_desc = "Reload latency exceeded 1024 cyc", }, [ POWER8_PME_PM_L1MISS_LAT_EXC_2048 ] = { .pme_name = "PM_L1MISS_LAT_EXC_2048", .pme_code = 0x67200401ecull, .pme_short_desc = "L1 misses that took longer than 2048 cyles to resolve (miss to reload)", .pme_long_desc = "Reload latency exceeded 2048 cyc", }, [ POWER8_PME_PM_L1MISS_LAT_EXC_256 ] = { .pme_name = "PM_L1MISS_LAT_EXC_256", .pme_code = 0x67200101e8ull, .pme_short_desc = "L1 misses that took longer than 256 cyles to resolve (miss to reload)", .pme_long_desc = "Reload latency exceeded 256 cyc", }, [ POWER8_PME_PM_L1MISS_LAT_EXC_32 ] = { .pme_name = "PM_L1MISS_LAT_EXC_32", .pme_code = 0x67200201e6ull, .pme_short_desc = "L1 misses that took longer than 32 cyles to resolve (miss to reload)", .pme_long_desc = "Reload latency exceeded 32 cyc", }, [ POWER8_PME_PM_L1PF_L2MEMACC ] = { .pme_name = "PM_L1PF_L2MEMACC", .pme_code = 0x26086, .pme_short_desc = "valid when first beat of data comes in for an L1pref where data came from mem(or L4)", .pme_long_desc = "valid when first beat of data comes in for an L1pref where data came from mem(or L4)", }, [ POWER8_PME_PM_L1_DCACHE_RELOADED_ALL ] = { .pme_name = "PM_L1_DCACHE_RELOADED_ALL", .pme_code = 0x1002c, .pme_short_desc = "L1 data cache reloaded for demand or prefetch", .pme_long_desc = "L1 data cache reloaded for demand or prefetch .", }, [ POWER8_PME_PM_L1_DCACHE_RELOAD_VALID ] = { .pme_name = "PM_L1_DCACHE_RELOAD_VALID", .pme_code = 0x300f6, .pme_short_desc = "DL1 reloaded due to Demand Load", .pme_long_desc = "DL1 reloaded due to Demand Load .", }, [ POWER8_PME_PM_L1_DEMAND_WRITE ] = { .pme_name = "PM_L1_DEMAND_WRITE", .pme_code = 0x408c, .pme_short_desc = "Instruction Demand sectors wriittent into IL1", .pme_long_desc = "Instruction Demand sectors wriittent into IL1", }, [ POWER8_PME_PM_L1_ICACHE_MISS ] = { .pme_name = "PM_L1_ICACHE_MISS", .pme_code = 0x200fd, .pme_short_desc = "Demand iCache Miss", .pme_long_desc = "Demand iCache Miss.", }, [ POWER8_PME_PM_L1_ICACHE_RELOADED_ALL ] = { .pme_name = "PM_L1_ICACHE_RELOADED_ALL", .pme_code = 0x40012, .pme_short_desc = "Counts all Icache reloads includes demand, prefetchm prefetch turned into demand and demand turned into prefetch", .pme_long_desc = "Counts all Icache reloads includes demand, prefetchm prefetch turned into demand and demand turned into prefetch.", }, [ POWER8_PME_PM_L1_ICACHE_RELOADED_PREF ] = { .pme_name = "PM_L1_ICACHE_RELOADED_PREF", .pme_code = 0x30068, .pme_short_desc = "Counts all Icache prefetch reloads ( includes demand turned into prefetch)", .pme_long_desc = "Counts all Icache prefetch reloads ( includes demand turned into prefetch).", }, [ POWER8_PME_PM_L2_CASTOUT_MOD ] = { .pme_name = "PM_L2_CASTOUT_MOD", .pme_code = 0x417080, .pme_short_desc = "L2 Castouts - Modified (M, Mu, Me)", .pme_long_desc = "L2 Castouts - Modified (M, Mu, Me)", }, [ POWER8_PME_PM_L2_CASTOUT_SHR ] = { .pme_name = "PM_L2_CASTOUT_SHR", .pme_code = 0x417082, .pme_short_desc = "L2 Castouts - Shared (T, Te, Si, S)", .pme_long_desc = "L2 Castouts - Shared (T, Te, Si, S)", }, [ POWER8_PME_PM_L2_CHIP_PUMP ] = { .pme_name = "PM_L2_CHIP_PUMP", .pme_code = 0x27084, .pme_short_desc = "RC requests that were local on chip pump attempts", .pme_long_desc = "RC requests that were local on chip pump attempts", }, [ POWER8_PME_PM_L2_DC_INV ] = { .pme_name = "PM_L2_DC_INV", .pme_code = 0x427086, .pme_short_desc = "Dcache invalidates from L2", .pme_long_desc = "Dcache invalidates from L2", }, [ POWER8_PME_PM_L2_DISP_ALL_L2MISS ] = { .pme_name = "PM_L2_DISP_ALL_L2MISS", .pme_code = 0x44608c, .pme_short_desc = "All successful Ld/St dispatches for this thread that were an L2miss.", .pme_long_desc = "All successful Ld/St dispatches for this thread that were an L2miss.", }, [ POWER8_PME_PM_L2_GROUP_PUMP ] = { .pme_name = "PM_L2_GROUP_PUMP", .pme_code = 0x27086, .pme_short_desc = "RC requests that were on Node Pump attempts", .pme_long_desc = "RC requests that were on Node Pump attempts", }, [ POWER8_PME_PM_L2_GRP_GUESS_CORRECT ] = { .pme_name = "PM_L2_GRP_GUESS_CORRECT", .pme_code = 0x626084, .pme_short_desc = "L2 guess grp and guess was correct (data intra-6chip AND ^on-chip)", .pme_long_desc = "L2 guess grp and guess was correct (data intra-6chip AND ^on-chip)", }, [ POWER8_PME_PM_L2_GRP_GUESS_WRONG ] = { .pme_name = "PM_L2_GRP_GUESS_WRONG", .pme_code = 0x626086, .pme_short_desc = "L2 guess grp and guess was not correct (ie data on-chip OR beyond-6chip)", .pme_long_desc = "L2 guess grp and guess was not correct (ie data on-chip OR beyond-6chip)", }, [ POWER8_PME_PM_L2_IC_INV ] = { .pme_name = "PM_L2_IC_INV", .pme_code = 0x427084, .pme_short_desc = "Icache Invalidates from L2", .pme_long_desc = "Icache Invalidates from L2", }, [ POWER8_PME_PM_L2_INST ] = { .pme_name = "PM_L2_INST", .pme_code = 0x436088, .pme_short_desc = "All successful I-side dispatches for this thread (excludes i_l2mru_tch reqs)", .pme_long_desc = "All successful I-side dispatches for this thread (excludes i_l2mru_tch reqs)", }, [ POWER8_PME_PM_L2_INST_MISS ] = { .pme_name = "PM_L2_INST_MISS", .pme_code = 0x43608a, .pme_short_desc = "All successful i-side dispatches that were an L2miss for this thread (excludes i_l2mru_tch reqs)", .pme_long_desc = "All successful i-side dispatches that were an L2miss for this thread (excludes i_l2mru_tch reqs)", }, [ POWER8_PME_PM_L2_LD ] = { .pme_name = "PM_L2_LD", .pme_code = 0x416080, .pme_short_desc = "All successful D-side Load dispatches for this thread", .pme_long_desc = "All successful D-side Load dispatches for this thread", }, [ POWER8_PME_PM_L2_LD_DISP ] = { .pme_name = "PM_L2_LD_DISP", .pme_code = 0x437088, .pme_short_desc = "All successful load dispatches", .pme_long_desc = "All successful load dispatches", }, [ POWER8_PME_PM_L2_LD_HIT ] = { .pme_name = "PM_L2_LD_HIT", .pme_code = 0x43708a, .pme_short_desc = "All successful load dispatches that were L2 hits", .pme_long_desc = "All successful load dispatches that were L2 hits", }, [ POWER8_PME_PM_L2_LD_MISS ] = { .pme_name = "PM_L2_LD_MISS", .pme_code = 0x426084, .pme_short_desc = "All successful D-Side Load dispatches that were an L2miss for this thread", .pme_long_desc = "All successful D-Side Load dispatches that were an L2miss for this thread", }, [ POWER8_PME_PM_L2_LOC_GUESS_CORRECT ] = { .pme_name = "PM_L2_LOC_GUESS_CORRECT", .pme_code = 0x616080, .pme_short_desc = "L2 guess loc and guess was correct (ie data local)", .pme_long_desc = "L2 guess loc and guess was correct (ie data local)", }, [ POWER8_PME_PM_L2_LOC_GUESS_WRONG ] = { .pme_name = "PM_L2_LOC_GUESS_WRONG", .pme_code = 0x616082, .pme_short_desc = "L2 guess loc and guess was not correct (ie data not on chip)", .pme_long_desc = "L2 guess loc and guess was not correct (ie data not on chip)", }, [ POWER8_PME_PM_L2_RCLD_DISP ] = { .pme_name = "PM_L2_RCLD_DISP", .pme_code = 0x516080, .pme_short_desc = "L2 RC load dispatch attempt", .pme_long_desc = "L2 RC load dispatch attempt", }, [ POWER8_PME_PM_L2_RCLD_DISP_FAIL_ADDR ] = { .pme_name = "PM_L2_RCLD_DISP_FAIL_ADDR", .pme_code = 0x516082, .pme_short_desc = "L2 RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ", .pme_long_desc = "L2 RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ", }, [ POWER8_PME_PM_L2_RCLD_DISP_FAIL_OTHER ] = { .pme_name = "PM_L2_RCLD_DISP_FAIL_OTHER", .pme_code = 0x526084, .pme_short_desc = "L2 RC load dispatch attempt failed due to other reasons", .pme_long_desc = "L2 RC load dispatch attempt failed due to other reasons", }, [ POWER8_PME_PM_L2_RCST_DISP ] = { .pme_name = "PM_L2_RCST_DISP", .pme_code = 0x536088, .pme_short_desc = "L2 RC store dispatch attempt", .pme_long_desc = "L2 RC store dispatch attempt", }, [ POWER8_PME_PM_L2_RCST_DISP_FAIL_ADDR ] = { .pme_name = "PM_L2_RCST_DISP_FAIL_ADDR", .pme_code = 0x53608a, .pme_short_desc = "L2 RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ", .pme_long_desc = "L2 RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ", }, [ POWER8_PME_PM_L2_RCST_DISP_FAIL_OTHER ] = { .pme_name = "PM_L2_RCST_DISP_FAIL_OTHER", .pme_code = 0x54608c, .pme_short_desc = "L2 RC store dispatch attempt failed due to other reasons", .pme_long_desc = "L2 RC store dispatch attempt failed due to other reasons", }, [ POWER8_PME_PM_L2_RC_ST_DONE ] = { .pme_name = "PM_L2_RC_ST_DONE", .pme_code = 0x537088, .pme_short_desc = "RC did st to line that was Tx or Sx", .pme_long_desc = "RC did st to line that was Tx or Sx", }, [ POWER8_PME_PM_L2_RTY_LD ] = { .pme_name = "PM_L2_RTY_LD", .pme_code = 0x63708a, .pme_short_desc = "RC retries on PB for any load from core", .pme_long_desc = "RC retries on PB for any load from core", }, [ POWER8_PME_PM_L2_RTY_ST ] = { .pme_name = "PM_L2_RTY_ST", .pme_code = 0x3708a, .pme_short_desc = "RC retries on PB for any store from core", .pme_long_desc = "RC retries on PB for any store from core", }, [ POWER8_PME_PM_L2_SN_M_RD_DONE ] = { .pme_name = "PM_L2_SN_M_RD_DONE", .pme_code = 0x54708c, .pme_short_desc = "SNP dispatched for a read and was M", .pme_long_desc = "SNP dispatched for a read and was M", }, [ POWER8_PME_PM_L2_SN_M_WR_DONE ] = { .pme_name = "PM_L2_SN_M_WR_DONE", .pme_code = 0x54708e, .pme_short_desc = "SNP dispatched for a write and was M", .pme_long_desc = "SNP dispatched for a write and was M", }, [ POWER8_PME_PM_L2_SN_SX_I_DONE ] = { .pme_name = "PM_L2_SN_SX_I_DONE", .pme_code = 0x53708a, .pme_short_desc = "SNP dispatched and went from Sx or Tx to Ix", .pme_long_desc = "SNP dispatched and went from Sx or Tx to Ix", }, [ POWER8_PME_PM_L2_ST ] = { .pme_name = "PM_L2_ST", .pme_code = 0x17080, .pme_short_desc = "All successful D-side store dispatches for this thread", .pme_long_desc = "All successful D-side store dispatches for this thread", }, [ POWER8_PME_PM_L2_ST_DISP ] = { .pme_name = "PM_L2_ST_DISP", .pme_code = 0x44708c, .pme_short_desc = "All successful store dispatches", .pme_long_desc = "All successful store dispatches", }, [ POWER8_PME_PM_L2_ST_HIT ] = { .pme_name = "PM_L2_ST_HIT", .pme_code = 0x44708e, .pme_short_desc = "All successful store dispatches that were L2Hits", .pme_long_desc = "All successful store dispatches that were L2Hits", }, [ POWER8_PME_PM_L2_ST_MISS ] = { .pme_name = "PM_L2_ST_MISS", .pme_code = 0x17082, .pme_short_desc = "All successful D-side store dispatches for this thread that were L2 Miss", .pme_long_desc = "All successful D-side store dispatches for this thread that were L2 Miss", }, [ POWER8_PME_PM_L2_SYS_GUESS_CORRECT ] = { .pme_name = "PM_L2_SYS_GUESS_CORRECT", .pme_code = 0x636088, .pme_short_desc = "L2 guess sys and guess was correct (ie data beyond-6chip)", .pme_long_desc = "L2 guess sys and guess was correct (ie data beyond-6chip)", }, [ POWER8_PME_PM_L2_SYS_GUESS_WRONG ] = { .pme_name = "PM_L2_SYS_GUESS_WRONG", .pme_code = 0x63608a, .pme_short_desc = "L2 guess sys and guess was not correct (ie data ^beyond-6chip)", .pme_long_desc = "L2 guess sys and guess was not correct (ie data ^beyond-6chip)", }, [ POWER8_PME_PM_L2_SYS_PUMP ] = { .pme_name = "PM_L2_SYS_PUMP", .pme_code = 0x617080, .pme_short_desc = "RC requests that were system pump attempts", .pme_long_desc = "RC requests that were system pump attempts", }, [ POWER8_PME_PM_L2_TM_REQ_ABORT ] = { .pme_name = "PM_L2_TM_REQ_ABORT", .pme_code = 0x1e05e, .pme_short_desc = "TM abort", .pme_long_desc = "TM abort.", }, [ POWER8_PME_PM_L2_TM_ST_ABORT_SISTER ] = { .pme_name = "PM_L2_TM_ST_ABORT_SISTER", .pme_code = 0x3e05c, .pme_short_desc = "TM marked store abort", .pme_long_desc = "TM marked store abort.", }, [ POWER8_PME_PM_L3_CINJ ] = { .pme_name = "PM_L3_CINJ", .pme_code = 0x23808a, .pme_short_desc = "l3 ci of cache inject", .pme_long_desc = "l3 ci of cache inject", }, [ POWER8_PME_PM_L3_CI_HIT ] = { .pme_name = "PM_L3_CI_HIT", .pme_code = 0x128084, .pme_short_desc = "L3 Castins Hit (total count", .pme_long_desc = "L3 Castins Hit (total count", }, [ POWER8_PME_PM_L3_CI_MISS ] = { .pme_name = "PM_L3_CI_MISS", .pme_code = 0x128086, .pme_short_desc = "L3 castins miss (total count", .pme_long_desc = "L3 castins miss (total count", }, [ POWER8_PME_PM_L3_CI_USAGE ] = { .pme_name = "PM_L3_CI_USAGE", .pme_code = 0x819082, .pme_short_desc = "rotating sample of 16 CI or CO actives", .pme_long_desc = "rotating sample of 16 CI or CO actives", }, [ POWER8_PME_PM_L3_CO ] = { .pme_name = "PM_L3_CO", .pme_code = 0x438088, .pme_short_desc = "l3 castout occuring ( does not include casthrough or log writes (cinj/dmaw)", .pme_long_desc = "l3 castout occuring ( does not include casthrough or log writes (cinj/dmaw)", }, [ POWER8_PME_PM_L3_CO0_ALLOC ] = { .pme_name = "PM_L3_CO0_ALLOC", .pme_code = 0x83908b, .pme_short_desc = "lifetime, sample of CO machine 0 valid", .pme_long_desc = "0.0", }, [ POWER8_PME_PM_L3_CO0_BUSY ] = { .pme_name = "PM_L3_CO0_BUSY", .pme_code = 0x83908a, .pme_short_desc = "lifetime, sample of CO machine 0 valid", .pme_long_desc = "lifetime, sample of CO machine 0 valid", }, [ POWER8_PME_PM_L3_CO_L31 ] = { .pme_name = "PM_L3_CO_L31", .pme_code = 0x28086, .pme_short_desc = "L3 CO to L3.1 OR of port 0 and 1 ( lossy)", .pme_long_desc = "L3 CO to L3.1 OR of port 0 and 1 ( lossy)", }, [ POWER8_PME_PM_L3_CO_LCO ] = { .pme_name = "PM_L3_CO_LCO", .pme_code = 0x238088, .pme_short_desc = "Total L3 castouts occurred on LCO", .pme_long_desc = "Total L3 castouts occurred on LCO", }, [ POWER8_PME_PM_L3_CO_MEM ] = { .pme_name = "PM_L3_CO_MEM", .pme_code = 0x28084, .pme_short_desc = "L3 CO to memory OR of port 0 and 1 ( lossy)", .pme_long_desc = "L3 CO to memory OR of port 0 and 1 ( lossy)", }, [ POWER8_PME_PM_L3_CO_MEPF ] = { .pme_name = "PM_L3_CO_MEPF", .pme_code = 0x18082, .pme_short_desc = "L3 CO of line in Mep state ( includes casthrough", .pme_long_desc = "L3 CO of line in Mep state ( includes casthrough", }, [ POWER8_PME_PM_L3_GRP_GUESS_CORRECT ] = { .pme_name = "PM_L3_GRP_GUESS_CORRECT", .pme_code = 0xb19082, .pme_short_desc = "Initial scope=group and data from same group (near) (pred successful)", .pme_long_desc = "Initial scope=group and data from same group (near) (pred successful)", }, [ POWER8_PME_PM_L3_GRP_GUESS_WRONG_HIGH ] = { .pme_name = "PM_L3_GRP_GUESS_WRONG_HIGH", .pme_code = 0xb3908a, .pme_short_desc = "Initial scope=group but data from local node. Predition too high", .pme_long_desc = "Initial scope=group but data from local node. Predition too high", }, [ POWER8_PME_PM_L3_GRP_GUESS_WRONG_LOW ] = { .pme_name = "PM_L3_GRP_GUESS_WRONG_LOW", .pme_code = 0xb39088, .pme_short_desc = "Initial scope=group but data from outside group (far or rem). Prediction too Low", .pme_long_desc = "Initial scope=group but data from outside group (far or rem). Prediction too Low", }, [ POWER8_PME_PM_L3_HIT ] = { .pme_name = "PM_L3_HIT", .pme_code = 0x218080, .pme_short_desc = "L3 Hits", .pme_long_desc = "L3 Hits", }, [ POWER8_PME_PM_L3_L2_CO_HIT ] = { .pme_name = "PM_L3_L2_CO_HIT", .pme_code = 0x138088, .pme_short_desc = "L2 castout hits", .pme_long_desc = "L2 castout hits", }, [ POWER8_PME_PM_L3_L2_CO_MISS ] = { .pme_name = "PM_L3_L2_CO_MISS", .pme_code = 0x13808a, .pme_short_desc = "L2 castout miss", .pme_long_desc = "L2 castout miss", }, [ POWER8_PME_PM_L3_LAT_CI_HIT ] = { .pme_name = "PM_L3_LAT_CI_HIT", .pme_code = 0x14808c, .pme_short_desc = "L3 Lateral Castins Hit", .pme_long_desc = "L3 Lateral Castins Hit", }, [ POWER8_PME_PM_L3_LAT_CI_MISS ] = { .pme_name = "PM_L3_LAT_CI_MISS", .pme_code = 0x14808e, .pme_short_desc = "L3 Lateral Castins Miss", .pme_long_desc = "L3 Lateral Castins Miss", }, [ POWER8_PME_PM_L3_LD_HIT ] = { .pme_name = "PM_L3_LD_HIT", .pme_code = 0x228084, .pme_short_desc = "L3 demand LD Hits", .pme_long_desc = "L3 demand LD Hits", }, [ POWER8_PME_PM_L3_LD_MISS ] = { .pme_name = "PM_L3_LD_MISS", .pme_code = 0x228086, .pme_short_desc = "L3 demand LD Miss", .pme_long_desc = "L3 demand LD Miss", }, [ POWER8_PME_PM_L3_LD_PREF ] = { .pme_name = "PM_L3_LD_PREF", .pme_code = 0x1e052, .pme_short_desc = "L3 Load Prefetches", .pme_long_desc = "L3 Load Prefetches.", }, [ POWER8_PME_PM_L3_LOC_GUESS_CORRECT ] = { .pme_name = "PM_L3_LOC_GUESS_CORRECT", .pme_code = 0xb19080, .pme_short_desc = "initial scope=node/chip and data from local node (local) (pred successful)", .pme_long_desc = "initial scope=node/chip and data from local node (local) (pred successful)", }, [ POWER8_PME_PM_L3_LOC_GUESS_WRONG ] = { .pme_name = "PM_L3_LOC_GUESS_WRONG", .pme_code = 0xb29086, .pme_short_desc = "Initial scope=node but data from out side local node (near or far or rem). Prediction too Low", .pme_long_desc = "Initial scope=node but data from out side local node (near or far or rem). Prediction too Low", }, [ POWER8_PME_PM_L3_MISS ] = { .pme_name = "PM_L3_MISS", .pme_code = 0x218082, .pme_short_desc = "L3 Misses", .pme_long_desc = "L3 Misses", }, [ POWER8_PME_PM_L3_P0_CO_L31 ] = { .pme_name = "PM_L3_P0_CO_L31", .pme_code = 0x54808c, .pme_short_desc = "l3 CO to L3.1 (lco) port 0", .pme_long_desc = "l3 CO to L3.1 (lco) port 0", }, [ POWER8_PME_PM_L3_P0_CO_MEM ] = { .pme_name = "PM_L3_P0_CO_MEM", .pme_code = 0x538088, .pme_short_desc = "l3 CO to memory port 0", .pme_long_desc = "l3 CO to memory port 0", }, [ POWER8_PME_PM_L3_P0_CO_RTY ] = { .pme_name = "PM_L3_P0_CO_RTY", .pme_code = 0x929084, .pme_short_desc = "L3 CO received retry port 0", .pme_long_desc = "L3 CO received retry port 0", }, [ POWER8_PME_PM_L3_P0_GRP_PUMP ] = { .pme_name = "PM_L3_P0_GRP_PUMP", .pme_code = 0xa29084, .pme_short_desc = "L3 pf sent with grp scope port 0", .pme_long_desc = "L3 pf sent with grp scope port 0", }, [ POWER8_PME_PM_L3_P0_LCO_DATA ] = { .pme_name = "PM_L3_P0_LCO_DATA", .pme_code = 0x528084, .pme_short_desc = "lco sent with data port 0", .pme_long_desc = "lco sent with data port 0", }, [ POWER8_PME_PM_L3_P0_LCO_NO_DATA ] = { .pme_name = "PM_L3_P0_LCO_NO_DATA", .pme_code = 0x518080, .pme_short_desc = "dataless l3 lco sent port 0", .pme_long_desc = "dataless l3 lco sent port 0", }, [ POWER8_PME_PM_L3_P0_LCO_RTY ] = { .pme_name = "PM_L3_P0_LCO_RTY", .pme_code = 0xa4908c, .pme_short_desc = "L3 LCO received retry port 0", .pme_long_desc = "L3 LCO received retry port 0", }, [ POWER8_PME_PM_L3_P0_NODE_PUMP ] = { .pme_name = "PM_L3_P0_NODE_PUMP", .pme_code = 0xa19080, .pme_short_desc = "L3 pf sent with nodal scope port 0", .pme_long_desc = "L3 pf sent with nodal scope port 0", }, [ POWER8_PME_PM_L3_P0_PF_RTY ] = { .pme_name = "PM_L3_P0_PF_RTY", .pme_code = 0x919080, .pme_short_desc = "L3 PF received retry port 0", .pme_long_desc = "L3 PF received retry port 0", }, [ POWER8_PME_PM_L3_P0_SN_HIT ] = { .pme_name = "PM_L3_P0_SN_HIT", .pme_code = 0x939088, .pme_short_desc = "L3 snoop hit port 0", .pme_long_desc = "L3 snoop hit port 0", }, [ POWER8_PME_PM_L3_P0_SN_INV ] = { .pme_name = "PM_L3_P0_SN_INV", .pme_code = 0x118080, .pme_short_desc = "Port0 snooper detects someone doing a store to a line thats Sx", .pme_long_desc = "Port0 snooper detects someone doing a store to a line thats Sx", }, [ POWER8_PME_PM_L3_P0_SN_MISS ] = { .pme_name = "PM_L3_P0_SN_MISS", .pme_code = 0x94908c, .pme_short_desc = "L3 snoop miss port 0", .pme_long_desc = "L3 snoop miss port 0", }, [ POWER8_PME_PM_L3_P0_SYS_PUMP ] = { .pme_name = "PM_L3_P0_SYS_PUMP", .pme_code = 0xa39088, .pme_short_desc = "L3 pf sent with sys scope port 0", .pme_long_desc = "L3 pf sent with sys scope port 0", }, [ POWER8_PME_PM_L3_P1_CO_L31 ] = { .pme_name = "PM_L3_P1_CO_L31", .pme_code = 0x54808e, .pme_short_desc = "l3 CO to L3.1 (lco) port 1", .pme_long_desc = "l3 CO to L3.1 (lco) port 1", }, [ POWER8_PME_PM_L3_P1_CO_MEM ] = { .pme_name = "PM_L3_P1_CO_MEM", .pme_code = 0x53808a, .pme_short_desc = "l3 CO to memory port 1", .pme_long_desc = "l3 CO to memory port 1", }, [ POWER8_PME_PM_L3_P1_CO_RTY ] = { .pme_name = "PM_L3_P1_CO_RTY", .pme_code = 0x929086, .pme_short_desc = "L3 CO received retry port 1", .pme_long_desc = "L3 CO received retry port 1", }, [ POWER8_PME_PM_L3_P1_GRP_PUMP ] = { .pme_name = "PM_L3_P1_GRP_PUMP", .pme_code = 0xa29086, .pme_short_desc = "L3 pf sent with grp scope port 1", .pme_long_desc = "L3 pf sent with grp scope port 1", }, [ POWER8_PME_PM_L3_P1_LCO_DATA ] = { .pme_name = "PM_L3_P1_LCO_DATA", .pme_code = 0x528086, .pme_short_desc = "lco sent with data port 1", .pme_long_desc = "lco sent with data port 1", }, [ POWER8_PME_PM_L3_P1_LCO_NO_DATA ] = { .pme_name = "PM_L3_P1_LCO_NO_DATA", .pme_code = 0x518082, .pme_short_desc = "dataless l3 lco sent port 1", .pme_long_desc = "dataless l3 lco sent port 1", }, [ POWER8_PME_PM_L3_P1_LCO_RTY ] = { .pme_name = "PM_L3_P1_LCO_RTY", .pme_code = 0xa4908e, .pme_short_desc = "L3 LCO received retry port 1", .pme_long_desc = "L3 LCO received retry port 1", }, [ POWER8_PME_PM_L3_P1_NODE_PUMP ] = { .pme_name = "PM_L3_P1_NODE_PUMP", .pme_code = 0xa19082, .pme_short_desc = "L3 pf sent with nodal scope port 1", .pme_long_desc = "L3 pf sent with nodal scope port 1", }, [ POWER8_PME_PM_L3_P1_PF_RTY ] = { .pme_name = "PM_L3_P1_PF_RTY", .pme_code = 0x919082, .pme_short_desc = "L3 PF received retry port 1", .pme_long_desc = "L3 PF received retry port 1", }, [ POWER8_PME_PM_L3_P1_SN_HIT ] = { .pme_name = "PM_L3_P1_SN_HIT", .pme_code = 0x93908a, .pme_short_desc = "L3 snoop hit port 1", .pme_long_desc = "L3 snoop hit port 1", }, [ POWER8_PME_PM_L3_P1_SN_INV ] = { .pme_name = "PM_L3_P1_SN_INV", .pme_code = 0x118082, .pme_short_desc = "Port1 snooper detects someone doing a store to a line thats Sx", .pme_long_desc = "Port1 snooper detects someone doing a store to a line thats Sx", }, [ POWER8_PME_PM_L3_P1_SN_MISS ] = { .pme_name = "PM_L3_P1_SN_MISS", .pme_code = 0x94908e, .pme_short_desc = "L3 snoop miss port 1", .pme_long_desc = "L3 snoop miss port 1", }, [ POWER8_PME_PM_L3_P1_SYS_PUMP ] = { .pme_name = "PM_L3_P1_SYS_PUMP", .pme_code = 0xa3908a, .pme_short_desc = "L3 pf sent with sys scope port 1", .pme_long_desc = "L3 pf sent with sys scope port 1", }, [ POWER8_PME_PM_L3_PF0_ALLOC ] = { .pme_name = "PM_L3_PF0_ALLOC", .pme_code = 0x84908d, .pme_short_desc = "lifetime, sample of PF machine 0 valid", .pme_long_desc = "0.0", }, [ POWER8_PME_PM_L3_PF0_BUSY ] = { .pme_name = "PM_L3_PF0_BUSY", .pme_code = 0x84908c, .pme_short_desc = "lifetime, sample of PF machine 0 valid", .pme_long_desc = "lifetime, sample of PF machine 0 valid", }, [ POWER8_PME_PM_L3_PF_HIT_L3 ] = { .pme_name = "PM_L3_PF_HIT_L3", .pme_code = 0x428084, .pme_short_desc = "l3 pf hit in l3", .pme_long_desc = "l3 pf hit in l3", }, [ POWER8_PME_PM_L3_PF_MISS_L3 ] = { .pme_name = "PM_L3_PF_MISS_L3", .pme_code = 0x18080, .pme_short_desc = "L3 Prefetch missed in L3", .pme_long_desc = "L3 Prefetch missed in L3", }, [ POWER8_PME_PM_L3_PF_OFF_CHIP_CACHE ] = { .pme_name = "PM_L3_PF_OFF_CHIP_CACHE", .pme_code = 0x3808a, .pme_short_desc = "L3 Prefetch from Off chip cache", .pme_long_desc = "L3 Prefetch from Off chip cache", }, [ POWER8_PME_PM_L3_PF_OFF_CHIP_MEM ] = { .pme_name = "PM_L3_PF_OFF_CHIP_MEM", .pme_code = 0x4808e, .pme_short_desc = "L3 Prefetch from Off chip memory", .pme_long_desc = "L3 Prefetch from Off chip memory", }, [ POWER8_PME_PM_L3_PF_ON_CHIP_CACHE ] = { .pme_name = "PM_L3_PF_ON_CHIP_CACHE", .pme_code = 0x38088, .pme_short_desc = "L3 Prefetch from On chip cache", .pme_long_desc = "L3 Prefetch from On chip cache", }, [ POWER8_PME_PM_L3_PF_ON_CHIP_MEM ] = { .pme_name = "PM_L3_PF_ON_CHIP_MEM", .pme_code = 0x4808c, .pme_short_desc = "L3 Prefetch from On chip memory", .pme_long_desc = "L3 Prefetch from On chip memory", }, [ POWER8_PME_PM_L3_PF_USAGE ] = { .pme_name = "PM_L3_PF_USAGE", .pme_code = 0x829084, .pme_short_desc = "rotating sample of 32 PF actives", .pme_long_desc = "rotating sample of 32 PF actives", }, [ POWER8_PME_PM_L3_PREF_ALL ] = { .pme_name = "PM_L3_PREF_ALL", .pme_code = 0x4e052, .pme_short_desc = "Total HW L3 prefetches(Load+store)", .pme_long_desc = "Total HW L3 prefetches(Load+store).", }, [ POWER8_PME_PM_L3_RD0_ALLOC ] = { .pme_name = "PM_L3_RD0_ALLOC", .pme_code = 0x84908f, .pme_short_desc = "lifetime, sample of RD machine 0 valid", .pme_long_desc = "0.0", }, [ POWER8_PME_PM_L3_RD0_BUSY ] = { .pme_name = "PM_L3_RD0_BUSY", .pme_code = 0x84908e, .pme_short_desc = "lifetime, sample of RD machine 0 valid", .pme_long_desc = "lifetime, sample of RD machine 0 valid", }, [ POWER8_PME_PM_L3_RD_USAGE ] = { .pme_name = "PM_L3_RD_USAGE", .pme_code = 0x829086, .pme_short_desc = "rotating sample of 16 RD actives", .pme_long_desc = "rotating sample of 16 RD actives", }, [ POWER8_PME_PM_L3_SN0_ALLOC ] = { .pme_name = "PM_L3_SN0_ALLOC", .pme_code = 0x839089, .pme_short_desc = "lifetime, sample of snooper machine 0 valid", .pme_long_desc = "0.0", }, [ POWER8_PME_PM_L3_SN0_BUSY ] = { .pme_name = "PM_L3_SN0_BUSY", .pme_code = 0x839088, .pme_short_desc = "lifetime, sample of snooper machine 0 valid", .pme_long_desc = "lifetime, sample of snooper machine 0 valid", }, [ POWER8_PME_PM_L3_SN_USAGE ] = { .pme_name = "PM_L3_SN_USAGE", .pme_code = 0x819080, .pme_short_desc = "rotating sample of 8 snoop valids", .pme_long_desc = "rotating sample of 8 snoop valids", }, [ POWER8_PME_PM_L3_ST_PREF ] = { .pme_name = "PM_L3_ST_PREF", .pme_code = 0x2e052, .pme_short_desc = "L3 store Prefetches", .pme_long_desc = "L3 store Prefetches.", }, [ POWER8_PME_PM_L3_SW_PREF ] = { .pme_name = "PM_L3_SW_PREF", .pme_code = 0x3e052, .pme_short_desc = "Data stream touchto L3", .pme_long_desc = "Data stream touchto L3.", }, [ POWER8_PME_PM_L3_SYS_GUESS_CORRECT ] = { .pme_name = "PM_L3_SYS_GUESS_CORRECT", .pme_code = 0xb29084, .pme_short_desc = "Initial scope=system and data from outside group (far or rem)(pred successful)", .pme_long_desc = "Initial scope=system and data from outside group (far or rem)(pred successful)", }, [ POWER8_PME_PM_L3_SYS_GUESS_WRONG ] = { .pme_name = "PM_L3_SYS_GUESS_WRONG", .pme_code = 0xb4908c, .pme_short_desc = "Initial scope=system but data from local or near. Predction too high", .pme_long_desc = "Initial scope=system but data from local or near. Predction too high", }, [ POWER8_PME_PM_L3_TRANS_PF ] = { .pme_name = "PM_L3_TRANS_PF", .pme_code = 0x24808e, .pme_short_desc = "L3 Transient prefetch", .pme_long_desc = "L3 Transient prefetch", }, [ POWER8_PME_PM_L3_WI0_ALLOC ] = { .pme_name = "PM_L3_WI0_ALLOC", .pme_code = 0x18081, .pme_short_desc = "lifetime, sample of Write Inject machine 0 valid", .pme_long_desc = "0.0", }, [ POWER8_PME_PM_L3_WI0_BUSY ] = { .pme_name = "PM_L3_WI0_BUSY", .pme_code = 0x418080, .pme_short_desc = "lifetime, sample of Write Inject machine 0 valid", .pme_long_desc = "lifetime, sample of Write Inject machine 0 valid", }, [ POWER8_PME_PM_L3_WI_USAGE ] = { .pme_name = "PM_L3_WI_USAGE", .pme_code = 0x418082, .pme_short_desc = "rotating sample of 8 WI actives", .pme_long_desc = "rotating sample of 8 WI actives", }, [ POWER8_PME_PM_LARX_FIN ] = { .pme_name = "PM_LARX_FIN", .pme_code = 0x3c058, .pme_short_desc = "Larx finished", .pme_long_desc = "Larx finished .", }, [ POWER8_PME_PM_LD_CMPL ] = { .pme_name = "PM_LD_CMPL", .pme_code = 0x1002e, .pme_short_desc = "count of Loads completed", .pme_long_desc = "count of Loads completed.", }, [ POWER8_PME_PM_LD_L3MISS_PEND_CYC ] = { .pme_name = "PM_LD_L3MISS_PEND_CYC", .pme_code = 0x10062, .pme_short_desc = "Cycles L3 miss was pending for this thread", .pme_long_desc = "Cycles L3 miss was pending for this thread.", }, [ POWER8_PME_PM_LD_MISS_L1 ] = { .pme_name = "PM_LD_MISS_L1", .pme_code = 0x3e054, .pme_short_desc = "Load Missed L1", .pme_long_desc = "Load Missed L1.", }, [ POWER8_PME_PM_LD_REF_L1 ] = { .pme_name = "PM_LD_REF_L1", .pme_code = 0x100ee, .pme_short_desc = "All L1 D cache load references counted at finish, gated by reject", .pme_long_desc = "Load Ref count combined for all units.", }, [ POWER8_PME_PM_LD_REF_L1_LSU0 ] = { .pme_name = "PM_LD_REF_L1_LSU0", .pme_code = 0xc080, .pme_short_desc = "LS0 L1 D cache load references counted at finish, gated by reject", .pme_long_desc = "LS0 L1 D cache load references counted at finish, gated by rejectLSU0 L1 D cache load references", }, [ POWER8_PME_PM_LD_REF_L1_LSU1 ] = { .pme_name = "PM_LD_REF_L1_LSU1", .pme_code = 0xc082, .pme_short_desc = "LS1 L1 D cache load references counted at finish, gated by reject", .pme_long_desc = "LS1 L1 D cache load references counted at finish, gated by rejectLSU1 L1 D cache load references", }, [ POWER8_PME_PM_LD_REF_L1_LSU2 ] = { .pme_name = "PM_LD_REF_L1_LSU2", .pme_code = 0xc094, .pme_short_desc = "LS2 L1 D cache load references counted at finish, gated by reject", .pme_long_desc = "LS2 L1 D cache load references counted at finish, gated by reject42", }, [ POWER8_PME_PM_LD_REF_L1_LSU3 ] = { .pme_name = "PM_LD_REF_L1_LSU3", .pme_code = 0xc096, .pme_short_desc = "LS3 L1 D cache load references counted at finish, gated by reject", .pme_long_desc = "LS3 L1 D cache load references counted at finish, gated by reject42", }, [ POWER8_PME_PM_LINK_STACK_INVALID_PTR ] = { .pme_name = "PM_LINK_STACK_INVALID_PTR", .pme_code = 0x509a, .pme_short_desc = "A flush were LS ptr is invalid, results in a pop , A lot of interrupts between push and pops", .pme_long_desc = "A flush were LS ptr is invalid, results in a pop , A lot of interrupts between push and pops", }, [ POWER8_PME_PM_LINK_STACK_WRONG_ADD_PRED ] = { .pme_name = "PM_LINK_STACK_WRONG_ADD_PRED", .pme_code = 0x5098, .pme_short_desc = "Link stack predicts wrong address, because of link stack design limitation.", .pme_long_desc = "Link stack predicts wrong address, because of link stack design limitation.", }, [ POWER8_PME_PM_LS0_ERAT_MISS_PREF ] = { .pme_name = "PM_LS0_ERAT_MISS_PREF", .pme_code = 0xe080, .pme_short_desc = "LS0 Erat miss due to prefetch", .pme_long_desc = "LS0 Erat miss due to prefetch42", }, [ POWER8_PME_PM_LS0_L1_PREF ] = { .pme_name = "PM_LS0_L1_PREF", .pme_code = 0xd0b8, .pme_short_desc = "LS0 L1 cache data prefetches", .pme_long_desc = "LS0 L1 cache data prefetches42", }, [ POWER8_PME_PM_LS0_L1_SW_PREF ] = { .pme_name = "PM_LS0_L1_SW_PREF", .pme_code = 0xc098, .pme_short_desc = "Software L1 Prefetches, including SW Transient Prefetches", .pme_long_desc = "Software L1 Prefetches, including SW Transient Prefetches42", }, [ POWER8_PME_PM_LS1_ERAT_MISS_PREF ] = { .pme_name = "PM_LS1_ERAT_MISS_PREF", .pme_code = 0xe082, .pme_short_desc = "LS1 Erat miss due to prefetch", .pme_long_desc = "LS1 Erat miss due to prefetch42", }, [ POWER8_PME_PM_LS1_L1_PREF ] = { .pme_name = "PM_LS1_L1_PREF", .pme_code = 0xd0ba, .pme_short_desc = "LS1 L1 cache data prefetches", .pme_long_desc = "LS1 L1 cache data prefetches42", }, [ POWER8_PME_PM_LS1_L1_SW_PREF ] = { .pme_name = "PM_LS1_L1_SW_PREF", .pme_code = 0xc09a, .pme_short_desc = "Software L1 Prefetches, including SW Transient Prefetches", .pme_long_desc = "Software L1 Prefetches, including SW Transient Prefetches42", }, [ POWER8_PME_PM_LSU0_FLUSH_LRQ ] = { .pme_name = "PM_LSU0_FLUSH_LRQ", .pme_code = 0xc0b0, .pme_short_desc = "LS0 Flush: LRQ", .pme_long_desc = "LS0 Flush: LRQLSU0 LRQ flushes", }, [ POWER8_PME_PM_LSU0_FLUSH_SRQ ] = { .pme_name = "PM_LSU0_FLUSH_SRQ", .pme_code = 0xc0b8, .pme_short_desc = "LS0 Flush: SRQ", .pme_long_desc = "LS0 Flush: SRQLSU0 SRQ lhs flushes", }, [ POWER8_PME_PM_LSU0_FLUSH_ULD ] = { .pme_name = "PM_LSU0_FLUSH_ULD", .pme_code = 0xc0a4, .pme_short_desc = "LS0 Flush: Unaligned Load", .pme_long_desc = "LS0 Flush: Unaligned LoadLSU0 unaligned load flushes", }, [ POWER8_PME_PM_LSU0_FLUSH_UST ] = { .pme_name = "PM_LSU0_FLUSH_UST", .pme_code = 0xc0ac, .pme_short_desc = "LS0 Flush: Unaligned Store", .pme_long_desc = "LS0 Flush: Unaligned StoreLSU0 unaligned store flushes", }, [ POWER8_PME_PM_LSU0_L1_CAM_CANCEL ] = { .pme_name = "PM_LSU0_L1_CAM_CANCEL", .pme_code = 0xf088, .pme_short_desc = "ls0 l1 tm cam cancel", .pme_long_desc = "ls0 l1 tm cam cancel42", }, [ POWER8_PME_PM_LSU0_LARX_FIN ] = { .pme_name = "PM_LSU0_LARX_FIN", .pme_code = 0x1e056, .pme_short_desc = "Larx finished in LSU pipe0", .pme_long_desc = ".", }, [ POWER8_PME_PM_LSU0_LMQ_LHR_MERGE ] = { .pme_name = "PM_LSU0_LMQ_LHR_MERGE", .pme_code = 0xd08c, .pme_short_desc = "LS0 Load Merged with another cacheline request", .pme_long_desc = "LS0 Load Merged with another cacheline request42", }, [ POWER8_PME_PM_LSU0_NCLD ] = { .pme_name = "PM_LSU0_NCLD", .pme_code = 0xc08c, .pme_short_desc = "LS0 Non-cachable Loads counted at finish", .pme_long_desc = "LS0 Non-cachable Loads counted at finishLSU0 non-cacheable loads", }, [ POWER8_PME_PM_LSU0_PRIMARY_ERAT_HIT ] = { .pme_name = "PM_LSU0_PRIMARY_ERAT_HIT", .pme_code = 0xe090, .pme_short_desc = "Primary ERAT hit", .pme_long_desc = "Primary ERAT hit42", }, [ POWER8_PME_PM_LSU0_REJECT ] = { .pme_name = "PM_LSU0_REJECT", .pme_code = 0x1e05a, .pme_short_desc = "LSU0 reject", .pme_long_desc = "LSU0 reject .", }, [ POWER8_PME_PM_LSU0_SRQ_STFWD ] = { .pme_name = "PM_LSU0_SRQ_STFWD", .pme_code = 0xc09c, .pme_short_desc = "LS0 SRQ forwarded data to a load", .pme_long_desc = "LS0 SRQ forwarded data to a loadLSU0 SRQ store forwarded", }, [ POWER8_PME_PM_LSU0_STORE_REJECT ] = { .pme_name = "PM_LSU0_STORE_REJECT", .pme_code = 0xf084, .pme_short_desc = "ls0 store reject", .pme_long_desc = "ls0 store reject42", }, [ POWER8_PME_PM_LSU0_TMA_REQ_L2 ] = { .pme_name = "PM_LSU0_TMA_REQ_L2", .pme_code = 0xe0a8, .pme_short_desc = "addrs only req to L2 only on the first one,Indication that Load footprint is not expanding", .pme_long_desc = "addrs only req to L2 only on the first one,Indication that Load footprint is not expanding42", }, [ POWER8_PME_PM_LSU0_TM_L1_HIT ] = { .pme_name = "PM_LSU0_TM_L1_HIT", .pme_code = 0xe098, .pme_short_desc = "Load tm hit in L1", .pme_long_desc = "Load tm hit in L142", }, [ POWER8_PME_PM_LSU0_TM_L1_MISS ] = { .pme_name = "PM_LSU0_TM_L1_MISS", .pme_code = 0xe0a0, .pme_short_desc = "Load tm L1 miss", .pme_long_desc = "Load tm L1 miss42", }, [ POWER8_PME_PM_LSU1_FLUSH_LRQ ] = { .pme_name = "PM_LSU1_FLUSH_LRQ", .pme_code = 0xc0b2, .pme_short_desc = "LS1 Flush: LRQ", .pme_long_desc = "LS1 Flush: LRQLSU1 LRQ flushes", }, [ POWER8_PME_PM_LSU1_FLUSH_SRQ ] = { .pme_name = "PM_LSU1_FLUSH_SRQ", .pme_code = 0xc0ba, .pme_short_desc = "LS1 Flush: SRQ", .pme_long_desc = "LS1 Flush: SRQLSU1 SRQ lhs flushes", }, [ POWER8_PME_PM_LSU1_FLUSH_ULD ] = { .pme_name = "PM_LSU1_FLUSH_ULD", .pme_code = 0xc0a6, .pme_short_desc = "LS 1 Flush: Unaligned Load", .pme_long_desc = "LS 1 Flush: Unaligned LoadLSU1 unaligned load flushes", }, [ POWER8_PME_PM_LSU1_FLUSH_UST ] = { .pme_name = "PM_LSU1_FLUSH_UST", .pme_code = 0xc0ae, .pme_short_desc = "LS1 Flush: Unaligned Store", .pme_long_desc = "LS1 Flush: Unaligned StoreLSU1 unaligned store flushes", }, [ POWER8_PME_PM_LSU1_L1_CAM_CANCEL ] = { .pme_name = "PM_LSU1_L1_CAM_CANCEL", .pme_code = 0xf08a, .pme_short_desc = "ls1 l1 tm cam cancel", .pme_long_desc = "ls1 l1 tm cam cancel42", }, [ POWER8_PME_PM_LSU1_LARX_FIN ] = { .pme_name = "PM_LSU1_LARX_FIN", .pme_code = 0x2e056, .pme_short_desc = "Larx finished in LSU pipe1", .pme_long_desc = "Larx finished in LSU pipe1.", }, [ POWER8_PME_PM_LSU1_LMQ_LHR_MERGE ] = { .pme_name = "PM_LSU1_LMQ_LHR_MERGE", .pme_code = 0xd08e, .pme_short_desc = "LS1 Load Merge with another cacheline request", .pme_long_desc = "LS1 Load Merge with another cacheline request42", }, [ POWER8_PME_PM_LSU1_NCLD ] = { .pme_name = "PM_LSU1_NCLD", .pme_code = 0xc08e, .pme_short_desc = "LS1 Non-cachable Loads counted at finish", .pme_long_desc = "LS1 Non-cachable Loads counted at finishLSU1 non-cacheable loads", }, [ POWER8_PME_PM_LSU1_PRIMARY_ERAT_HIT ] = { .pme_name = "PM_LSU1_PRIMARY_ERAT_HIT", .pme_code = 0xe092, .pme_short_desc = "Primary ERAT hit", .pme_long_desc = "Primary ERAT hit42", }, [ POWER8_PME_PM_LSU1_REJECT ] = { .pme_name = "PM_LSU1_REJECT", .pme_code = 0x2e05a, .pme_short_desc = "LSU1 reject", .pme_long_desc = "LSU1 reject .", }, [ POWER8_PME_PM_LSU1_SRQ_STFWD ] = { .pme_name = "PM_LSU1_SRQ_STFWD", .pme_code = 0xc09e, .pme_short_desc = "LS1 SRQ forwarded data to a load", .pme_long_desc = "LS1 SRQ forwarded data to a loadLSU1 SRQ store forwarded", }, [ POWER8_PME_PM_LSU1_STORE_REJECT ] = { .pme_name = "PM_LSU1_STORE_REJECT", .pme_code = 0xf086, .pme_short_desc = "ls1 store reject", .pme_long_desc = "ls1 store reject42", }, [ POWER8_PME_PM_LSU1_TMA_REQ_L2 ] = { .pme_name = "PM_LSU1_TMA_REQ_L2", .pme_code = 0xe0aa, .pme_short_desc = "addrs only req to L2 only on the first one,Indication that Load footprint is not expanding", .pme_long_desc = "addrs only req to L2 only on the first one,Indication that Load footprint is not expanding42", }, [ POWER8_PME_PM_LSU1_TM_L1_HIT ] = { .pme_name = "PM_LSU1_TM_L1_HIT", .pme_code = 0xe09a, .pme_short_desc = "Load tm hit in L1", .pme_long_desc = "Load tm hit in L142", }, [ POWER8_PME_PM_LSU1_TM_L1_MISS ] = { .pme_name = "PM_LSU1_TM_L1_MISS", .pme_code = 0xe0a2, .pme_short_desc = "Load tm L1 miss", .pme_long_desc = "Load tm L1 miss42", }, [ POWER8_PME_PM_LSU2_FLUSH_LRQ ] = { .pme_name = "PM_LSU2_FLUSH_LRQ", .pme_code = 0xc0b4, .pme_short_desc = "LS02Flush: LRQ", .pme_long_desc = "LS02Flush: LRQ42", }, [ POWER8_PME_PM_LSU2_FLUSH_SRQ ] = { .pme_name = "PM_LSU2_FLUSH_SRQ", .pme_code = 0xc0bc, .pme_short_desc = "LS2 Flush: SRQ", .pme_long_desc = "LS2 Flush: SRQ42", }, [ POWER8_PME_PM_LSU2_FLUSH_ULD ] = { .pme_name = "PM_LSU2_FLUSH_ULD", .pme_code = 0xc0a8, .pme_short_desc = "LS3 Flush: Unaligned Load", .pme_long_desc = "LS3 Flush: Unaligned Load42", }, [ POWER8_PME_PM_LSU2_L1_CAM_CANCEL ] = { .pme_name = "PM_LSU2_L1_CAM_CANCEL", .pme_code = 0xf08c, .pme_short_desc = "ls2 l1 tm cam cancel", .pme_long_desc = "ls2 l1 tm cam cancel42", }, [ POWER8_PME_PM_LSU2_LARX_FIN ] = { .pme_name = "PM_LSU2_LARX_FIN", .pme_code = 0x3e056, .pme_short_desc = "Larx finished in LSU pipe2", .pme_long_desc = "Larx finished in LSU pipe2.", }, [ POWER8_PME_PM_LSU2_LDF ] = { .pme_name = "PM_LSU2_LDF", .pme_code = 0xc084, .pme_short_desc = "LS2 Scalar Loads", .pme_long_desc = "LS2 Scalar Loads42", }, [ POWER8_PME_PM_LSU2_LDX ] = { .pme_name = "PM_LSU2_LDX", .pme_code = 0xc088, .pme_short_desc = "LS0 Vector Loads", .pme_long_desc = "LS0 Vector Loads42", }, [ POWER8_PME_PM_LSU2_LMQ_LHR_MERGE ] = { .pme_name = "PM_LSU2_LMQ_LHR_MERGE", .pme_code = 0xd090, .pme_short_desc = "LS0 Load Merged with another cacheline request", .pme_long_desc = "LS0 Load Merged with another cacheline request42", }, [ POWER8_PME_PM_LSU2_PRIMARY_ERAT_HIT ] = { .pme_name = "PM_LSU2_PRIMARY_ERAT_HIT", .pme_code = 0xe094, .pme_short_desc = "Primary ERAT hit", .pme_long_desc = "Primary ERAT hit42", }, [ POWER8_PME_PM_LSU2_REJECT ] = { .pme_name = "PM_LSU2_REJECT", .pme_code = 0x3e05a, .pme_short_desc = "LSU2 reject", .pme_long_desc = "LSU2 reject .", }, [ POWER8_PME_PM_LSU2_SRQ_STFWD ] = { .pme_name = "PM_LSU2_SRQ_STFWD", .pme_code = 0xc0a0, .pme_short_desc = "LS2 SRQ forwarded data to a load", .pme_long_desc = "LS2 SRQ forwarded data to a load42", }, [ POWER8_PME_PM_LSU2_TMA_REQ_L2 ] = { .pme_name = "PM_LSU2_TMA_REQ_L2", .pme_code = 0xe0ac, .pme_short_desc = "addrs only req to L2 only on the first one,Indication that Load footprint is not expanding", .pme_long_desc = "addrs only req to L2 only on the first one,Indication that Load footprint is not expanding42", }, [ POWER8_PME_PM_LSU2_TM_L1_HIT ] = { .pme_name = "PM_LSU2_TM_L1_HIT", .pme_code = 0xe09c, .pme_short_desc = "Load tm hit in L1", .pme_long_desc = "Load tm hit in L142", }, [ POWER8_PME_PM_LSU2_TM_L1_MISS ] = { .pme_name = "PM_LSU2_TM_L1_MISS", .pme_code = 0xe0a4, .pme_short_desc = "Load tm L1 miss", .pme_long_desc = "Load tm L1 miss42", }, [ POWER8_PME_PM_LSU3_FLUSH_LRQ ] = { .pme_name = "PM_LSU3_FLUSH_LRQ", .pme_code = 0xc0b6, .pme_short_desc = "LS3 Flush: LRQ", .pme_long_desc = "LS3 Flush: LRQ42", }, [ POWER8_PME_PM_LSU3_FLUSH_SRQ ] = { .pme_name = "PM_LSU3_FLUSH_SRQ", .pme_code = 0xc0be, .pme_short_desc = "LS13 Flush: SRQ", .pme_long_desc = "LS13 Flush: SRQ42", }, [ POWER8_PME_PM_LSU3_FLUSH_ULD ] = { .pme_name = "PM_LSU3_FLUSH_ULD", .pme_code = 0xc0aa, .pme_short_desc = "LS 14Flush: Unaligned Load", .pme_long_desc = "LS 14Flush: Unaligned Load42", }, [ POWER8_PME_PM_LSU3_L1_CAM_CANCEL ] = { .pme_name = "PM_LSU3_L1_CAM_CANCEL", .pme_code = 0xf08e, .pme_short_desc = "ls3 l1 tm cam cancel", .pme_long_desc = "ls3 l1 tm cam cancel42", }, [ POWER8_PME_PM_LSU3_LARX_FIN ] = { .pme_name = "PM_LSU3_LARX_FIN", .pme_code = 0x4e056, .pme_short_desc = "Larx finished in LSU pipe3", .pme_long_desc = "Larx finished in LSU pipe3.", }, [ POWER8_PME_PM_LSU3_LDF ] = { .pme_name = "PM_LSU3_LDF", .pme_code = 0xc086, .pme_short_desc = "LS3 Scalar Loads", .pme_long_desc = "LS3 Scalar Loads 42", }, [ POWER8_PME_PM_LSU3_LDX ] = { .pme_name = "PM_LSU3_LDX", .pme_code = 0xc08a, .pme_short_desc = "LS1 Vector Loads", .pme_long_desc = "LS1 Vector Loads42", }, [ POWER8_PME_PM_LSU3_LMQ_LHR_MERGE ] = { .pme_name = "PM_LSU3_LMQ_LHR_MERGE", .pme_code = 0xd092, .pme_short_desc = "LS1 Load Merge with another cacheline request", .pme_long_desc = "LS1 Load Merge with another cacheline request42", }, [ POWER8_PME_PM_LSU3_PRIMARY_ERAT_HIT ] = { .pme_name = "PM_LSU3_PRIMARY_ERAT_HIT", .pme_code = 0xe096, .pme_short_desc = "Primary ERAT hit", .pme_long_desc = "Primary ERAT hit42", }, [ POWER8_PME_PM_LSU3_REJECT ] = { .pme_name = "PM_LSU3_REJECT", .pme_code = 0x4e05a, .pme_short_desc = "LSU3 reject", .pme_long_desc = "LSU3 reject .", }, [ POWER8_PME_PM_LSU3_SRQ_STFWD ] = { .pme_name = "PM_LSU3_SRQ_STFWD", .pme_code = 0xc0a2, .pme_short_desc = "LS3 SRQ forwarded data to a load", .pme_long_desc = "LS3 SRQ forwarded data to a load42", }, [ POWER8_PME_PM_LSU3_TMA_REQ_L2 ] = { .pme_name = "PM_LSU3_TMA_REQ_L2", .pme_code = 0xe0ae, .pme_short_desc = "addrs only req to L2 only on the first one,Indication that Load footprint is not expanding", .pme_long_desc = "addrs only req to L2 only on the first one,Indication that Load footprint is not expanding42", }, [ POWER8_PME_PM_LSU3_TM_L1_HIT ] = { .pme_name = "PM_LSU3_TM_L1_HIT", .pme_code = 0xe09e, .pme_short_desc = "Load tm hit in L1", .pme_long_desc = "Load tm hit in L142", }, [ POWER8_PME_PM_LSU3_TM_L1_MISS ] = { .pme_name = "PM_LSU3_TM_L1_MISS", .pme_code = 0xe0a6, .pme_short_desc = "Load tm L1 miss", .pme_long_desc = "Load tm L1 miss42", }, [ POWER8_PME_PM_LSU_DERAT_MISS ] = { .pme_name = "PM_LSU_DERAT_MISS", .pme_code = 0x200f6, .pme_short_desc = "DERAT Reloaded due to a DERAT miss", .pme_long_desc = "DERAT Reloaded (Miss).", }, [ POWER8_PME_PM_LSU_ERAT_MISS_PREF ] = { .pme_name = "PM_LSU_ERAT_MISS_PREF", .pme_code = 0xe880, .pme_short_desc = "Erat miss due to prefetch, on either pipe", .pme_long_desc = "LSU", }, [ POWER8_PME_PM_LSU_FIN ] = { .pme_name = "PM_LSU_FIN", .pme_code = 0x30066, .pme_short_desc = "LSU Finished an instruction (up to 2 per cycle)", .pme_long_desc = "LSU Finished an instruction (up to 2 per cycle).", }, [ POWER8_PME_PM_LSU_FLUSH_UST ] = { .pme_name = "PM_LSU_FLUSH_UST", .pme_code = 0xc8ac, .pme_short_desc = "Unaligned Store Flush on either pipe", .pme_long_desc = "LSU", }, [ POWER8_PME_PM_LSU_FOUR_TABLEWALK_CYC ] = { .pme_name = "PM_LSU_FOUR_TABLEWALK_CYC", .pme_code = 0xd0a4, .pme_short_desc = "Cycles when four tablewalks pending on this thread", .pme_long_desc = "Cycles when four tablewalks pending on this thread42", }, [ POWER8_PME_PM_LSU_FX_FIN ] = { .pme_name = "PM_LSU_FX_FIN", .pme_code = 0x10066, .pme_short_desc = "LSU Finished a FX operation (up to 2 per cycle", .pme_long_desc = "LSU Finished a FX operation (up to 2 per cycle.", }, [ POWER8_PME_PM_LSU_L1_PREF ] = { .pme_name = "PM_LSU_L1_PREF", .pme_code = 0xd8b8, .pme_short_desc = "hw initiated , include sw streaming forms as well , include sw streams as a separate event", .pme_long_desc = "LSU", }, [ POWER8_PME_PM_LSU_L1_SW_PREF ] = { .pme_name = "PM_LSU_L1_SW_PREF", .pme_code = 0xc898, .pme_short_desc = "Software L1 Prefetches, including SW Transient Prefetches, on both pipes", .pme_long_desc = "LSU", }, [ POWER8_PME_PM_LSU_LDF ] = { .pme_name = "PM_LSU_LDF", .pme_code = 0xc884, .pme_short_desc = "FPU loads only on LS2/LS3 ie LU0/LU1", .pme_long_desc = "LSU", }, [ POWER8_PME_PM_LSU_LDX ] = { .pme_name = "PM_LSU_LDX", .pme_code = 0xc888, .pme_short_desc = "Vector loads can issue only on LS2/LS3", .pme_long_desc = "LSU", }, [ POWER8_PME_PM_LSU_LMQ_FULL_CYC ] = { .pme_name = "PM_LSU_LMQ_FULL_CYC", .pme_code = 0xd0a2, .pme_short_desc = "LMQ full", .pme_long_desc = "LMQ fullCycles LMQ full,", }, [ POWER8_PME_PM_LSU_LMQ_S0_ALLOC ] = { .pme_name = "PM_LSU_LMQ_S0_ALLOC", .pme_code = 0xd0a1, .pme_short_desc = "Per thread - use edge detect to count allocates On a per thread basis, level signal indicating Slot 0 is valid. By instrumenting a single slot we can calculate service time for that slot. Previous machines required a separate signal indicating the slot was allocated. Because any signal can be routed to any counter in P8, we can count level in one PMC and edge detect in another PMC using the same signal", .pme_long_desc = "0.0", }, [ POWER8_PME_PM_LSU_LMQ_S0_VALID ] = { .pme_name = "PM_LSU_LMQ_S0_VALID", .pme_code = 0xd0a0, .pme_short_desc = "Slot 0 of LMQ valid", .pme_long_desc = "Slot 0 of LMQ validLMQ slot 0 valid", }, [ POWER8_PME_PM_LSU_LMQ_SRQ_EMPTY_ALL_CYC ] = { .pme_name = "PM_LSU_LMQ_SRQ_EMPTY_ALL_CYC", .pme_code = 0x3001c, .pme_short_desc = "ALL threads lsu empty (lmq and srq empty)", .pme_long_desc = "ALL threads lsu empty (lmq and srq empty). Issue HW016541", }, [ POWER8_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC ] = { .pme_name = "PM_LSU_LMQ_SRQ_EMPTY_CYC", .pme_code = 0x2003e, .pme_short_desc = "LSU empty (lmq and srq empty)", .pme_long_desc = "LSU empty (lmq and srq empty).", }, [ POWER8_PME_PM_LSU_LRQ_S0_ALLOC ] = { .pme_name = "PM_LSU_LRQ_S0_ALLOC", .pme_code = 0xd09f, .pme_short_desc = "Per thread - use edge detect to count allocates On a per thread basis, level signal indicating Slot 0 is valid. By instrumenting a single slot we can calculate service time for that slot. Previous machines required a separate signal indicating the slot was allocated. Because any signal can be routed to any counter in P8, we can count level in one PMC and edge detect in another PMC using the same signal", .pme_long_desc = "0.0", }, [ POWER8_PME_PM_LSU_LRQ_S0_VALID ] = { .pme_name = "PM_LSU_LRQ_S0_VALID", .pme_code = 0xd09e, .pme_short_desc = "Slot 0 of LRQ valid", .pme_long_desc = "Slot 0 of LRQ validLRQ slot 0 valid", }, [ POWER8_PME_PM_LSU_LRQ_S43_ALLOC ] = { .pme_name = "PM_LSU_LRQ_S43_ALLOC", .pme_code = 0xf091, .pme_short_desc = "LRQ slot 43 was released", .pme_long_desc = "0.0", }, [ POWER8_PME_PM_LSU_LRQ_S43_VALID ] = { .pme_name = "PM_LSU_LRQ_S43_VALID", .pme_code = 0xf090, .pme_short_desc = "LRQ slot 43 was busy", .pme_long_desc = "LRQ slot 43 was busy42", }, [ POWER8_PME_PM_LSU_MRK_DERAT_MISS ] = { .pme_name = "PM_LSU_MRK_DERAT_MISS", .pme_code = 0x30162, .pme_short_desc = "DERAT Reloaded (Miss)", .pme_long_desc = "DERAT Reloaded (Miss).", }, [ POWER8_PME_PM_LSU_NCLD ] = { .pme_name = "PM_LSU_NCLD", .pme_code = 0xc88c, .pme_short_desc = "count at finish so can return only on ls0 or ls1", .pme_long_desc = "LSU", }, [ POWER8_PME_PM_LSU_NCST ] = { .pme_name = "PM_LSU_NCST", .pme_code = 0xc092, .pme_short_desc = "Non-cachable Stores sent to nest", .pme_long_desc = "Non-cachable Stores sent to nest42", }, [ POWER8_PME_PM_LSU_REJECT ] = { .pme_name = "PM_LSU_REJECT", .pme_code = 0x10064, .pme_short_desc = "LSU Reject (up to 4 per cycle)", .pme_long_desc = "LSU Reject (up to 4 per cycle).", }, [ POWER8_PME_PM_LSU_REJECT_ERAT_MISS ] = { .pme_name = "PM_LSU_REJECT_ERAT_MISS", .pme_code = 0x2e05c, .pme_short_desc = "LSU Reject due to ERAT (up to 4 per cycles)", .pme_long_desc = "LSU Reject due to ERAT (up to 4 per cycles).", }, [ POWER8_PME_PM_LSU_REJECT_LHS ] = { .pme_name = "PM_LSU_REJECT_LHS", .pme_code = 0x4e05c, .pme_short_desc = "LSU Reject due to LHS (up to 4 per cycle)", .pme_long_desc = "LSU Reject due to LHS (up to 4 per cycle).", }, [ POWER8_PME_PM_LSU_REJECT_LMQ_FULL ] = { .pme_name = "PM_LSU_REJECT_LMQ_FULL", .pme_code = 0x1e05c, .pme_short_desc = "LSU reject due to LMQ full ( 4 per cycle)", .pme_long_desc = "LSU reject due to LMQ full ( 4 per cycle).", }, [ POWER8_PME_PM_LSU_SET_MPRED ] = { .pme_name = "PM_LSU_SET_MPRED", .pme_code = 0xd082, .pme_short_desc = "Line already in cache at reload time", .pme_long_desc = "Line already in cache at reload time42", }, [ POWER8_PME_PM_LSU_SRQ_EMPTY_CYC ] = { .pme_name = "PM_LSU_SRQ_EMPTY_CYC", .pme_code = 0x40008, .pme_short_desc = "ALL threads srq empty", .pme_long_desc = "All threads srq empty.", }, [ POWER8_PME_PM_LSU_SRQ_FULL_CYC ] = { .pme_name = "PM_LSU_SRQ_FULL_CYC", .pme_code = 0x1001a, .pme_short_desc = "Storage Queue is full and is blocking dispatch", .pme_long_desc = "SRQ is Full.", }, [ POWER8_PME_PM_LSU_SRQ_S0_ALLOC ] = { .pme_name = "PM_LSU_SRQ_S0_ALLOC", .pme_code = 0xd09d, .pme_short_desc = "Per thread - use edge detect to count allocates On a per thread basis, level signal indicating Slot 0 is valid. By instrumenting a single slot we can calculate service time for that slot. Previous machines required a separate signal indicating the slot was allocated. Because any signal can be routed to any counter in P8, we can count level in one PMC and edge detect in another PMC using the same signal", .pme_long_desc = "0.0", }, [ POWER8_PME_PM_LSU_SRQ_S0_VALID ] = { .pme_name = "PM_LSU_SRQ_S0_VALID", .pme_code = 0xd09c, .pme_short_desc = "Slot 0 of SRQ valid", .pme_long_desc = "Slot 0 of SRQ validSRQ slot 0 valid", }, [ POWER8_PME_PM_LSU_SRQ_S39_ALLOC ] = { .pme_name = "PM_LSU_SRQ_S39_ALLOC", .pme_code = 0xf093, .pme_short_desc = "SRQ slot 39 was released", .pme_long_desc = "0.0", }, [ POWER8_PME_PM_LSU_SRQ_S39_VALID ] = { .pme_name = "PM_LSU_SRQ_S39_VALID", .pme_code = 0xf092, .pme_short_desc = "SRQ slot 39 was busy", .pme_long_desc = "SRQ slot 39 was busy42", }, [ POWER8_PME_PM_LSU_SRQ_SYNC ] = { .pme_name = "PM_LSU_SRQ_SYNC", .pme_code = 0xd09b, .pme_short_desc = "A sync in the SRQ ended", .pme_long_desc = "0.0", }, [ POWER8_PME_PM_LSU_SRQ_SYNC_CYC ] = { .pme_name = "PM_LSU_SRQ_SYNC_CYC", .pme_code = 0xd09a, .pme_short_desc = "A sync is in the SRQ (edge detect to count)", .pme_long_desc = "A sync is in the SRQ (edge detect to count)SRQ sync duration", }, [ POWER8_PME_PM_LSU_STORE_REJECT ] = { .pme_name = "PM_LSU_STORE_REJECT", .pme_code = 0xf084, .pme_short_desc = "Store reject on either pipe", .pme_long_desc = "LSU", }, [ POWER8_PME_PM_LSU_TWO_TABLEWALK_CYC ] = { .pme_name = "PM_LSU_TWO_TABLEWALK_CYC", .pme_code = 0xd0a6, .pme_short_desc = "Cycles when two tablewalks pending on this thread", .pme_long_desc = "Cycles when two tablewalks pending on this thread42", }, [ POWER8_PME_PM_LWSYNC ] = { .pme_name = "PM_LWSYNC", .pme_code = 0x5094, .pme_short_desc = "threaded version, IC Misses where we got EA dir hit but no sector valids were on. ICBI took line out", .pme_long_desc = "threaded version, IC Misses where we got EA dir hit but no sector valids were on. ICBI took line out", }, [ POWER8_PME_PM_LWSYNC_HELD ] = { .pme_name = "PM_LWSYNC_HELD", .pme_code = 0x209a, .pme_short_desc = "LWSYNC held at dispatch", .pme_long_desc = "LWSYNC held at dispatch", }, [ POWER8_PME_PM_MEM_CO ] = { .pme_name = "PM_MEM_CO", .pme_code = 0x4c058, .pme_short_desc = "Memory castouts from this lpar", .pme_long_desc = "Memory castouts from this lpar.", }, [ POWER8_PME_PM_MEM_LOC_THRESH_IFU ] = { .pme_name = "PM_MEM_LOC_THRESH_IFU", .pme_code = 0x10058, .pme_short_desc = "Local Memory above threshold for IFU speculation control", .pme_long_desc = "Local Memory above threshold for IFU speculation control.", }, [ POWER8_PME_PM_MEM_LOC_THRESH_LSU_HIGH ] = { .pme_name = "PM_MEM_LOC_THRESH_LSU_HIGH", .pme_code = 0x40056, .pme_short_desc = "Local memory above threshold for LSU medium", .pme_long_desc = "Local memory above threshold for LSU medium.", }, [ POWER8_PME_PM_MEM_LOC_THRESH_LSU_MED ] = { .pme_name = "PM_MEM_LOC_THRESH_LSU_MED", .pme_code = 0x1c05e, .pme_short_desc = "Local memory above theshold for data prefetch", .pme_long_desc = "Local memory above theshold for data prefetch.", }, [ POWER8_PME_PM_MEM_PREF ] = { .pme_name = "PM_MEM_PREF", .pme_code = 0x2c058, .pme_short_desc = "Memory prefetch for this lpar. Includes L4", .pme_long_desc = "Memory prefetch for this lpar.", }, [ POWER8_PME_PM_MEM_READ ] = { .pme_name = "PM_MEM_READ", .pme_code = 0x10056, .pme_short_desc = "Reads from Memory from this lpar (includes data/inst/xlate/l1prefetch/inst prefetch). Includes L4", .pme_long_desc = "Reads from Memory from this lpar (includes data/inst/xlate/l1prefetch/inst prefetch).", }, [ POWER8_PME_PM_MEM_RWITM ] = { .pme_name = "PM_MEM_RWITM", .pme_code = 0x3c05e, .pme_short_desc = "Memory rwitm for this lpar", .pme_long_desc = "Memory rwitm for this lpar.", }, [ POWER8_PME_PM_MRK_BACK_BR_CMPL ] = { .pme_name = "PM_MRK_BACK_BR_CMPL", .pme_code = 0x3515e, .pme_short_desc = "Marked branch instruction completed with a target address less than current instruction address", .pme_long_desc = "Marked branch instruction completed with a target address less than current instruction address.", }, [ POWER8_PME_PM_MRK_BRU_FIN ] = { .pme_name = "PM_MRK_BRU_FIN", .pme_code = 0x2013a, .pme_short_desc = "bru marked instr finish", .pme_long_desc = "bru marked instr finish.", }, [ POWER8_PME_PM_MRK_BR_CMPL ] = { .pme_name = "PM_MRK_BR_CMPL", .pme_code = 0x1016e, .pme_short_desc = "Branch Instruction completed", .pme_long_desc = "Branch Instruction completed.", }, [ POWER8_PME_PM_MRK_BR_MPRED_CMPL ] = { .pme_name = "PM_MRK_BR_MPRED_CMPL", .pme_code = 0x301e4, .pme_short_desc = "Marked Branch Mispredicted", .pme_long_desc = "Marked Branch Mispredicted.", }, [ POWER8_PME_PM_MRK_BR_TAKEN_CMPL ] = { .pme_name = "PM_MRK_BR_TAKEN_CMPL", .pme_code = 0x101e2, .pme_short_desc = "Marked Branch Taken completed", .pme_long_desc = "Marked Branch Taken.", }, [ POWER8_PME_PM_MRK_CRU_FIN ] = { .pme_name = "PM_MRK_CRU_FIN", .pme_code = 0x3013a, .pme_short_desc = "IFU non-branch finished", .pme_long_desc = "IFU non-branch marked instruction finished.", }, [ POWER8_PME_PM_MRK_DATA_FROM_DL2L3_MOD ] = { .pme_name = "PM_MRK_DATA_FROM_DL2L3_MOD", .pme_code = 0x4d148, .pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load", .pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load.", }, [ POWER8_PME_PM_MRK_DATA_FROM_DL2L3_MOD_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_DL2L3_MOD_CYC", .pme_code = 0x2d128, .pme_short_desc = "Duration in cycles to reload with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load", .pme_long_desc = "Duration in cycles to reload with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load.", }, [ POWER8_PME_PM_MRK_DATA_FROM_DL2L3_SHR ] = { .pme_name = "PM_MRK_DATA_FROM_DL2L3_SHR", .pme_code = 0x3d148, .pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load", .pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load.", }, [ POWER8_PME_PM_MRK_DATA_FROM_DL2L3_SHR_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_DL2L3_SHR_CYC", .pme_code = 0x2c128, .pme_short_desc = "Duration in cycles to reload with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load", .pme_long_desc = "Duration in cycles to reload with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load.", }, [ POWER8_PME_PM_MRK_DATA_FROM_DL4 ] = { .pme_name = "PM_MRK_DATA_FROM_DL4", .pme_code = 0x3d14c, .pme_short_desc = "The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to a marked load", .pme_long_desc = "The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to a marked load.", }, [ POWER8_PME_PM_MRK_DATA_FROM_DL4_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_DL4_CYC", .pme_code = 0x2c12c, .pme_short_desc = "Duration in cycles to reload from another chip's L4 on a different Node or Group (Distant) due to a marked load", .pme_long_desc = "Duration in cycles to reload from another chip's L4 on a different Node or Group (Distant) due to a marked load.", }, [ POWER8_PME_PM_MRK_DATA_FROM_DMEM ] = { .pme_name = "PM_MRK_DATA_FROM_DMEM", .pme_code = 0x4d14c, .pme_short_desc = "The processor's data cache was reloaded from another chip's memory on the same Node or Group (Distant) due to a marked load", .pme_long_desc = "The processor's data cache was reloaded from another chip's memory on the same Node or Group (Distant) due to a marked load.", }, [ POWER8_PME_PM_MRK_DATA_FROM_DMEM_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_DMEM_CYC", .pme_code = 0x2d12c, .pme_short_desc = "Duration in cycles to reload from another chip's memory on the same Node or Group (Distant) due to a marked load", .pme_long_desc = "Duration in cycles to reload from another chip's memory on the same Node or Group (Distant) due to a marked load.", }, [ POWER8_PME_PM_MRK_DATA_FROM_L2 ] = { .pme_name = "PM_MRK_DATA_FROM_L2", .pme_code = 0x1d142, .pme_short_desc = "The processor's data cache was reloaded from local core's L2 due to a marked load", .pme_long_desc = "The processor's data cache was reloaded from local core's L2 due to a marked load.", }, [ POWER8_PME_PM_MRK_DATA_FROM_L21_MOD ] = { .pme_name = "PM_MRK_DATA_FROM_L21_MOD", .pme_code = 0x4d146, .pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another core's L2 on the same chip due to a marked load", .pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another core's L2 on the same chip due to a marked load.", }, [ POWER8_PME_PM_MRK_DATA_FROM_L21_MOD_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L21_MOD_CYC", .pme_code = 0x2d126, .pme_short_desc = "Duration in cycles to reload with Modified (M) data from another core's L2 on the same chip due to a marked load", .pme_long_desc = "Duration in cycles to reload with Modified (M) data from another core's L2 on the same chip due to a marked load.", }, [ POWER8_PME_PM_MRK_DATA_FROM_L21_SHR ] = { .pme_name = "PM_MRK_DATA_FROM_L21_SHR", .pme_code = 0x3d146, .pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to a marked load", .pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to a marked load.", }, [ POWER8_PME_PM_MRK_DATA_FROM_L21_SHR_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L21_SHR_CYC", .pme_code = 0x2c126, .pme_short_desc = "Duration in cycles to reload with Shared (S) data from another core's L2 on the same chip due to a marked load", .pme_long_desc = "Duration in cycles to reload with Shared (S) data from another core's L2 on the same chip due to a marked load.", }, [ POWER8_PME_PM_MRK_DATA_FROM_L2MISS ] = { .pme_name = "PM_MRK_DATA_FROM_L2MISS", .pme_code = 0x1d14e, .pme_short_desc = "Data cache reload L2 miss", .pme_long_desc = "Data cache reload L2 miss.", }, [ POWER8_PME_PM_MRK_DATA_FROM_L2MISS_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L2MISS_CYC", .pme_code = 0x4c12e, .pme_short_desc = "Duration in cycles to reload from a localtion other than the local core's L2 due to a marked load", .pme_long_desc = "Duration in cycles to reload from a localtion other than the local core's L2 due to a marked load.", }, [ POWER8_PME_PM_MRK_DATA_FROM_L2_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L2_CYC", .pme_code = 0x4c122, .pme_short_desc = "Duration in cycles to reload from local core's L2 due to a marked load", .pme_long_desc = "Duration in cycles to reload from local core's L2 due to a marked load.", }, [ POWER8_PME_PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST ] = { .pme_name = "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST", .pme_code = 0x3d140, .pme_short_desc = "The processor's data cache was reloaded from local core's L2 with load hit store conflict due to a marked load", .pme_long_desc = "The processor's data cache was reloaded from local core's L2 with load hit store conflict due to a marked load.", }, [ POWER8_PME_PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST_CYC", .pme_code = 0x2c120, .pme_short_desc = "Duration in cycles to reload from local core's L2 with load hit store conflict due to a marked load", .pme_long_desc = "Duration in cycles to reload from local core's L2 with load hit store conflict due to a marked load.", }, [ POWER8_PME_PM_MRK_DATA_FROM_L2_DISP_CONFLICT_OTHER ] = { .pme_name = "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_OTHER", .pme_code = 0x4d140, .pme_short_desc = "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to a marked load", .pme_long_desc = "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to a marked load.", }, [ POWER8_PME_PM_MRK_DATA_FROM_L2_DISP_CONFLICT_OTHER_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_OTHER_CYC", .pme_code = 0x2d120, .pme_short_desc = "Duration in cycles to reload from local core's L2 with dispatch conflict due to a marked load", .pme_long_desc = "Duration in cycles to reload from local core's L2 with dispatch conflict due to a marked load.", }, [ POWER8_PME_PM_MRK_DATA_FROM_L2_MEPF ] = { .pme_name = "PM_MRK_DATA_FROM_L2_MEPF", .pme_code = 0x2d140, .pme_short_desc = "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked load", .pme_long_desc = "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked load.", }, [ POWER8_PME_PM_MRK_DATA_FROM_L2_MEPF_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L2_MEPF_CYC", .pme_code = 0x4d120, .pme_short_desc = "Duration in cycles to reload from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked load", .pme_long_desc = "Duration in cycles to reload from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked load.", }, [ POWER8_PME_PM_MRK_DATA_FROM_L2_NO_CONFLICT ] = { .pme_name = "PM_MRK_DATA_FROM_L2_NO_CONFLICT", .pme_code = 0x1d140, .pme_short_desc = "The processor's data cache was reloaded from local core's L2 without conflict due to a marked load", .pme_long_desc = "The processor's data cache was reloaded from local core's L2 without conflict due to a marked load.", }, [ POWER8_PME_PM_MRK_DATA_FROM_L2_NO_CONFLICT_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L2_NO_CONFLICT_CYC", .pme_code = 0x4c120, .pme_short_desc = "Duration in cycles to reload from local core's L2 without conflict due to a marked load", .pme_long_desc = "Duration in cycles to reload from local core's L2 without conflict due to a marked load.", }, [ POWER8_PME_PM_MRK_DATA_FROM_L3 ] = { .pme_name = "PM_MRK_DATA_FROM_L3", .pme_code = 0x4d142, .pme_short_desc = "The processor's data cache was reloaded from local core's L3 due to a marked load", .pme_long_desc = "The processor's data cache was reloaded from local core's L3 due to a marked load.", }, [ POWER8_PME_PM_MRK_DATA_FROM_L31_ECO_MOD ] = { .pme_name = "PM_MRK_DATA_FROM_L31_ECO_MOD", .pme_code = 0x4d144, .pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to a marked load", .pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to a marked load.", }, [ POWER8_PME_PM_MRK_DATA_FROM_L31_ECO_MOD_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L31_ECO_MOD_CYC", .pme_code = 0x2d124, .pme_short_desc = "Duration in cycles to reload with Modified (M) data from another core's ECO L3 on the same chip due to a marked load", .pme_long_desc = "Duration in cycles to reload with Modified (M) data from another core's ECO L3 on the same chip due to a marked load.", }, [ POWER8_PME_PM_MRK_DATA_FROM_L31_ECO_SHR ] = { .pme_name = "PM_MRK_DATA_FROM_L31_ECO_SHR", .pme_code = 0x3d144, .pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to a marked load", .pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to a marked load.", }, [ POWER8_PME_PM_MRK_DATA_FROM_L31_ECO_SHR_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L31_ECO_SHR_CYC", .pme_code = 0x2c124, .pme_short_desc = "Duration in cycles to reload with Shared (S) data from another core's ECO L3 on the same chip due to a marked load", .pme_long_desc = "Duration in cycles to reload with Shared (S) data from another core's ECO L3 on the same chip due to a marked load.", }, [ POWER8_PME_PM_MRK_DATA_FROM_L31_MOD ] = { .pme_name = "PM_MRK_DATA_FROM_L31_MOD", .pme_code = 0x2d144, .pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another core's L3 on the same chip due to a marked load", .pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another core's L3 on the same chip due to a marked load.", }, [ POWER8_PME_PM_MRK_DATA_FROM_L31_MOD_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L31_MOD_CYC", .pme_code = 0x4d124, .pme_short_desc = "Duration in cycles to reload with Modified (M) data from another core's L3 on the same chip due to a marked load", .pme_long_desc = "Duration in cycles to reload with Modified (M) data from another core's L3 on the same chip due to a marked load.", }, [ POWER8_PME_PM_MRK_DATA_FROM_L31_SHR ] = { .pme_name = "PM_MRK_DATA_FROM_L31_SHR", .pme_code = 0x1d146, .pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another core's L3 on the same chip due to a marked load", .pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another core's L3 on the same chip due to a marked load.", }, [ POWER8_PME_PM_MRK_DATA_FROM_L31_SHR_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L31_SHR_CYC", .pme_code = 0x4c126, .pme_short_desc = "Duration in cycles to reload with Shared (S) data from another core's L3 on the same chip due to a marked load", .pme_long_desc = "Duration in cycles to reload with Shared (S) data from another core's L3 on the same chip due to a marked load.", }, [ POWER8_PME_PM_MRK_DATA_FROM_L3MISS ] = { .pme_name = "PM_MRK_DATA_FROM_L3MISS", .pme_code = 0x201e4, .pme_short_desc = "The processor's data cache was reloaded from a localtion other than the local core's L3 due to a marked load", .pme_long_desc = "The processor's data cache was reloaded from a localtion other than the local core's L3 due to a marked load.", }, [ POWER8_PME_PM_MRK_DATA_FROM_L3MISS_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L3MISS_CYC", .pme_code = 0x2d12e, .pme_short_desc = "Duration in cycles to reload from a localtion other than the local core's L3 due to a marked load", .pme_long_desc = "Duration in cycles to reload from a localtion other than the local core's L3 due to a marked load.", }, [ POWER8_PME_PM_MRK_DATA_FROM_L3_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L3_CYC", .pme_code = 0x2d122, .pme_short_desc = "Duration in cycles to reload from local core's L3 due to a marked load", .pme_long_desc = "Duration in cycles to reload from local core's L3 due to a marked load.", }, [ POWER8_PME_PM_MRK_DATA_FROM_L3_DISP_CONFLICT ] = { .pme_name = "PM_MRK_DATA_FROM_L3_DISP_CONFLICT", .pme_code = 0x3d142, .pme_short_desc = "The processor's data cache was reloaded from local core's L3 with dispatch conflict due to a marked load", .pme_long_desc = "The processor's data cache was reloaded from local core's L3 with dispatch conflict due to a marked load.", }, [ POWER8_PME_PM_MRK_DATA_FROM_L3_DISP_CONFLICT_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L3_DISP_CONFLICT_CYC", .pme_code = 0x2c122, .pme_short_desc = "Duration in cycles to reload from local core's L3 with dispatch conflict due to a marked load", .pme_long_desc = "Duration in cycles to reload from local core's L3 with dispatch conflict due to a marked load.", }, [ POWER8_PME_PM_MRK_DATA_FROM_L3_MEPF ] = { .pme_name = "PM_MRK_DATA_FROM_L3_MEPF", .pme_code = 0x2d142, .pme_short_desc = "The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked load", .pme_long_desc = "The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked load.", }, [ POWER8_PME_PM_MRK_DATA_FROM_L3_MEPF_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L3_MEPF_CYC", .pme_code = 0x4d122, .pme_short_desc = "Duration in cycles to reload from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked load", .pme_long_desc = "Duration in cycles to reload from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked load.", }, [ POWER8_PME_PM_MRK_DATA_FROM_L3_NO_CONFLICT ] = { .pme_name = "PM_MRK_DATA_FROM_L3_NO_CONFLICT", .pme_code = 0x1d144, .pme_short_desc = "The processor's data cache was reloaded from local core's L3 without conflict due to a marked load", .pme_long_desc = "The processor's data cache was reloaded from local core's L3 without conflict due to a marked load.", }, [ POWER8_PME_PM_MRK_DATA_FROM_L3_NO_CONFLICT_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L3_NO_CONFLICT_CYC", .pme_code = 0x4c124, .pme_short_desc = "Duration in cycles to reload from local core's L3 without conflict due to a marked load", .pme_long_desc = "Duration in cycles to reload from local core's L3 without conflict due to a marked load.", }, [ POWER8_PME_PM_MRK_DATA_FROM_LL4 ] = { .pme_name = "PM_MRK_DATA_FROM_LL4", .pme_code = 0x1d14c, .pme_short_desc = "The processor's data cache was reloaded from the local chip's L4 cache due to a marked load", .pme_long_desc = "The processor's data cache was reloaded from the local chip's L4 cache due to a marked load.", }, [ POWER8_PME_PM_MRK_DATA_FROM_LL4_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_LL4_CYC", .pme_code = 0x4c12c, .pme_short_desc = "Duration in cycles to reload from the local chip's L4 cache due to a marked load", .pme_long_desc = "Duration in cycles to reload from the local chip's L4 cache due to a marked load.", }, [ POWER8_PME_PM_MRK_DATA_FROM_LMEM ] = { .pme_name = "PM_MRK_DATA_FROM_LMEM", .pme_code = 0x2d148, .pme_short_desc = "The processor's data cache was reloaded from the local chip's Memory due to a marked load", .pme_long_desc = "The processor's data cache was reloaded from the local chip's Memory due to a marked load.", }, [ POWER8_PME_PM_MRK_DATA_FROM_LMEM_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_LMEM_CYC", .pme_code = 0x4d128, .pme_short_desc = "Duration in cycles to reload from the local chip's Memory due to a marked load", .pme_long_desc = "Duration in cycles to reload from the local chip's Memory due to a marked load.", }, [ POWER8_PME_PM_MRK_DATA_FROM_MEM ] = { .pme_name = "PM_MRK_DATA_FROM_MEM", .pme_code = 0x201e0, .pme_short_desc = "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a marked load", .pme_long_desc = "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a marked load.", }, [ POWER8_PME_PM_MRK_DATA_FROM_MEMORY ] = { .pme_name = "PM_MRK_DATA_FROM_MEMORY", .pme_code = 0x2d14c, .pme_short_desc = "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a marked load", .pme_long_desc = "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a marked load.", }, [ POWER8_PME_PM_MRK_DATA_FROM_MEMORY_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_MEMORY_CYC", .pme_code = 0x4d12c, .pme_short_desc = "Duration in cycles to reload from a memory location including L4 from local remote or distant due to a marked load", .pme_long_desc = "Duration in cycles to reload from a memory location including L4 from local remote or distant due to a marked load.", }, [ POWER8_PME_PM_MRK_DATA_FROM_OFF_CHIP_CACHE ] = { .pme_name = "PM_MRK_DATA_FROM_OFF_CHIP_CACHE", .pme_code = 0x4d14a, .pme_short_desc = "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked load", .pme_long_desc = "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked load.", }, [ POWER8_PME_PM_MRK_DATA_FROM_OFF_CHIP_CACHE_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_OFF_CHIP_CACHE_CYC", .pme_code = 0x2d12a, .pme_short_desc = "Duration in cycles to reload either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked load", .pme_long_desc = "Duration in cycles to reload either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked load.", }, [ POWER8_PME_PM_MRK_DATA_FROM_ON_CHIP_CACHE ] = { .pme_name = "PM_MRK_DATA_FROM_ON_CHIP_CACHE", .pme_code = 0x1d148, .pme_short_desc = "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to a marked load", .pme_long_desc = "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to a marked load.", }, [ POWER8_PME_PM_MRK_DATA_FROM_ON_CHIP_CACHE_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_ON_CHIP_CACHE_CYC", .pme_code = 0x4c128, .pme_short_desc = "Duration in cycles to reload either shared or modified data from another core's L2/L3 on the same chip due to a marked load", .pme_long_desc = "Duration in cycles to reload either shared or modified data from another core's L2/L3 on the same chip due to a marked load.", }, [ POWER8_PME_PM_MRK_DATA_FROM_RL2L3_MOD ] = { .pme_name = "PM_MRK_DATA_FROM_RL2L3_MOD", .pme_code = 0x2d146, .pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load", .pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load.", }, [ POWER8_PME_PM_MRK_DATA_FROM_RL2L3_MOD_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_RL2L3_MOD_CYC", .pme_code = 0x4d126, .pme_short_desc = "Duration in cycles to reload with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load", .pme_long_desc = "Duration in cycles to reload with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load.", }, [ POWER8_PME_PM_MRK_DATA_FROM_RL2L3_SHR ] = { .pme_name = "PM_MRK_DATA_FROM_RL2L3_SHR", .pme_code = 0x1d14a, .pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load", .pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load.", }, [ POWER8_PME_PM_MRK_DATA_FROM_RL2L3_SHR_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_RL2L3_SHR_CYC", .pme_code = 0x4c12a, .pme_short_desc = "Duration in cycles to reload with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load", .pme_long_desc = "Duration in cycles to reload with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load.", }, [ POWER8_PME_PM_MRK_DATA_FROM_RL4 ] = { .pme_name = "PM_MRK_DATA_FROM_RL4", .pme_code = 0x2d14a, .pme_short_desc = "The processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to a marked load", .pme_long_desc = "The processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to a marked load.", }, [ POWER8_PME_PM_MRK_DATA_FROM_RL4_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_RL4_CYC", .pme_code = 0x4d12a, .pme_short_desc = "Duration in cycles to reload from another chip's L4 on the same Node or Group ( Remote) due to a marked load", .pme_long_desc = "Duration in cycles to reload from another chip's L4 on the same Node or Group ( Remote) due to a marked load.", }, [ POWER8_PME_PM_MRK_DATA_FROM_RMEM ] = { .pme_name = "PM_MRK_DATA_FROM_RMEM", .pme_code = 0x3d14a, .pme_short_desc = "The processor's data cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to a marked load", .pme_long_desc = "The processor's data cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to a marked load.", }, [ POWER8_PME_PM_MRK_DATA_FROM_RMEM_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_RMEM_CYC", .pme_code = 0x2c12a, .pme_short_desc = "Duration in cycles to reload from another chip's memory on the same Node or Group ( Remote) due to a marked load", .pme_long_desc = "Duration in cycles to reload from another chip's memory on the same Node or Group ( Remote) due to a marked load.", }, [ POWER8_PME_PM_MRK_DCACHE_RELOAD_INTV ] = { .pme_name = "PM_MRK_DCACHE_RELOAD_INTV", .pme_code = 0x40118, .pme_short_desc = "Combined Intervention event", .pme_long_desc = "Combined Intervention event.", }, [ POWER8_PME_PM_MRK_DERAT_MISS ] = { .pme_name = "PM_MRK_DERAT_MISS", .pme_code = 0x301e6, .pme_short_desc = "Erat Miss (TLB Access) All page sizes", .pme_long_desc = "Erat Miss (TLB Access) All page sizes.", }, [ POWER8_PME_PM_MRK_DERAT_MISS_16G ] = { .pme_name = "PM_MRK_DERAT_MISS_16G", .pme_code = 0x4d154, .pme_short_desc = "Marked Data ERAT Miss (Data TLB Access) page size 16G", .pme_long_desc = "Marked Data ERAT Miss (Data TLB Access) page size 16G.", }, [ POWER8_PME_PM_MRK_DERAT_MISS_16M ] = { .pme_name = "PM_MRK_DERAT_MISS_16M", .pme_code = 0x3d154, .pme_short_desc = "Marked Data ERAT Miss (Data TLB Access) page size 16M", .pme_long_desc = "Marked Data ERAT Miss (Data TLB Access) page size 16M.", }, [ POWER8_PME_PM_MRK_DERAT_MISS_4K ] = { .pme_name = "PM_MRK_DERAT_MISS_4K", .pme_code = 0x1d156, .pme_short_desc = "Marked Data ERAT Miss (Data TLB Access) page size 4K", .pme_long_desc = "Marked Data ERAT Miss (Data TLB Access) page size 4K.", }, [ POWER8_PME_PM_MRK_DERAT_MISS_64K ] = { .pme_name = "PM_MRK_DERAT_MISS_64K", .pme_code = 0x2d154, .pme_short_desc = "Marked Data ERAT Miss (Data TLB Access) page size 64K", .pme_long_desc = "Marked Data ERAT Miss (Data TLB Access) page size 64K.", }, [ POWER8_PME_PM_MRK_DFU_FIN ] = { .pme_name = "PM_MRK_DFU_FIN", .pme_code = 0x20132, .pme_short_desc = "Decimal Unit marked Instruction Finish", .pme_long_desc = "Decimal Unit marked Instruction Finish.", }, [ POWER8_PME_PM_MRK_DPTEG_FROM_DL2L3_MOD ] = { .pme_name = "PM_MRK_DPTEG_FROM_DL2L3_MOD", .pme_code = 0x4f148, .pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request.", }, [ POWER8_PME_PM_MRK_DPTEG_FROM_DL2L3_SHR ] = { .pme_name = "PM_MRK_DPTEG_FROM_DL2L3_SHR", .pme_code = 0x3f148, .pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request.", }, [ POWER8_PME_PM_MRK_DPTEG_FROM_DL4 ] = { .pme_name = "PM_MRK_DPTEG_FROM_DL4", .pme_code = 0x3f14c, .pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a marked data side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a marked data side request.", }, [ POWER8_PME_PM_MRK_DPTEG_FROM_DMEM ] = { .pme_name = "PM_MRK_DPTEG_FROM_DMEM", .pme_code = 0x4f14c, .pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a marked data side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a marked data side request.", }, [ POWER8_PME_PM_MRK_DPTEG_FROM_L2 ] = { .pme_name = "PM_MRK_DPTEG_FROM_L2", .pme_code = 0x1f142, .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 due to a marked data side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 due to a marked data side request.", }, [ POWER8_PME_PM_MRK_DPTEG_FROM_L21_MOD ] = { .pme_name = "PM_MRK_DPTEG_FROM_L21_MOD", .pme_code = 0x4f146, .pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a marked data side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a marked data side request.", }, [ POWER8_PME_PM_MRK_DPTEG_FROM_L21_SHR ] = { .pme_name = "PM_MRK_DPTEG_FROM_L21_SHR", .pme_code = 0x3f146, .pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a marked data side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a marked data side request.", }, [ POWER8_PME_PM_MRK_DPTEG_FROM_L2MISS ] = { .pme_name = "PM_MRK_DPTEG_FROM_L2MISS", .pme_code = 0x1f14e, .pme_short_desc = "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L2 due to a marked data side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L2 due to a marked data side request.", }, [ POWER8_PME_PM_MRK_DPTEG_FROM_L2_DISP_CONFLICT_LDHITST ] = { .pme_name = "PM_MRK_DPTEG_FROM_L2_DISP_CONFLICT_LDHITST", .pme_code = 0x3f140, .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 with load hit store conflict due to a marked data side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 with load hit store conflict due to a marked data side request.", }, [ POWER8_PME_PM_MRK_DPTEG_FROM_L2_DISP_CONFLICT_OTHER ] = { .pme_name = "PM_MRK_DPTEG_FROM_L2_DISP_CONFLICT_OTHER", .pme_code = 0x4f140, .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 with dispatch conflict due to a marked data side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 with dispatch conflict due to a marked data side request.", }, [ POWER8_PME_PM_MRK_DPTEG_FROM_L2_MEPF ] = { .pme_name = "PM_MRK_DPTEG_FROM_L2_MEPF", .pme_code = 0x2f140, .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked data side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked data side request.", }, [ POWER8_PME_PM_MRK_DPTEG_FROM_L2_NO_CONFLICT ] = { .pme_name = "PM_MRK_DPTEG_FROM_L2_NO_CONFLICT", .pme_code = 0x1f140, .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a marked data side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a marked data side request.", }, [ POWER8_PME_PM_MRK_DPTEG_FROM_L3 ] = { .pme_name = "PM_MRK_DPTEG_FROM_L3", .pme_code = 0x4f142, .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 due to a marked data side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 due to a marked data side request.", }, [ POWER8_PME_PM_MRK_DPTEG_FROM_L31_ECO_MOD ] = { .pme_name = "PM_MRK_DPTEG_FROM_L31_ECO_MOD", .pme_code = 0x4f144, .pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a marked data side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a marked data side request.", }, [ POWER8_PME_PM_MRK_DPTEG_FROM_L31_ECO_SHR ] = { .pme_name = "PM_MRK_DPTEG_FROM_L31_ECO_SHR", .pme_code = 0x3f144, .pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a marked data side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a marked data side request.", }, [ POWER8_PME_PM_MRK_DPTEG_FROM_L31_MOD ] = { .pme_name = "PM_MRK_DPTEG_FROM_L31_MOD", .pme_code = 0x2f144, .pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a marked data side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a marked data side request.", }, [ POWER8_PME_PM_MRK_DPTEG_FROM_L31_SHR ] = { .pme_name = "PM_MRK_DPTEG_FROM_L31_SHR", .pme_code = 0x1f146, .pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a marked data side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a marked data side request.", }, [ POWER8_PME_PM_MRK_DPTEG_FROM_L3MISS ] = { .pme_name = "PM_MRK_DPTEG_FROM_L3MISS", .pme_code = 0x4f14e, .pme_short_desc = "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L3 due to a marked data side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L3 due to a marked data side request.", }, [ POWER8_PME_PM_MRK_DPTEG_FROM_L3_DISP_CONFLICT ] = { .pme_name = "PM_MRK_DPTEG_FROM_L3_DISP_CONFLICT", .pme_code = 0x3f142, .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a marked data side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a marked data side request.", }, [ POWER8_PME_PM_MRK_DPTEG_FROM_L3_MEPF ] = { .pme_name = "PM_MRK_DPTEG_FROM_L3_MEPF", .pme_code = 0x2f142, .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked data side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked data side request.", }, [ POWER8_PME_PM_MRK_DPTEG_FROM_L3_NO_CONFLICT ] = { .pme_name = "PM_MRK_DPTEG_FROM_L3_NO_CONFLICT", .pme_code = 0x1f144, .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a marked data side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a marked data side request.", }, [ POWER8_PME_PM_MRK_DPTEG_FROM_LL4 ] = { .pme_name = "PM_MRK_DPTEG_FROM_LL4", .pme_code = 0x1f14c, .pme_short_desc = "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a marked data side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a marked data side request.", }, [ POWER8_PME_PM_MRK_DPTEG_FROM_LMEM ] = { .pme_name = "PM_MRK_DPTEG_FROM_LMEM", .pme_code = 0x2f148, .pme_short_desc = "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a marked data side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a marked data side request.", }, [ POWER8_PME_PM_MRK_DPTEG_FROM_MEMORY ] = { .pme_name = "PM_MRK_DPTEG_FROM_MEMORY", .pme_code = 0x2f14c, .pme_short_desc = "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a marked data side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a marked data side request.", }, [ POWER8_PME_PM_MRK_DPTEG_FROM_OFF_CHIP_CACHE ] = { .pme_name = "PM_MRK_DPTEG_FROM_OFF_CHIP_CACHE", .pme_code = 0x4f14a, .pme_short_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked data side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked data side request.", }, [ POWER8_PME_PM_MRK_DPTEG_FROM_ON_CHIP_CACHE ] = { .pme_name = "PM_MRK_DPTEG_FROM_ON_CHIP_CACHE", .pme_code = 0x1f148, .pme_short_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a marked data side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a marked data side request.", }, [ POWER8_PME_PM_MRK_DPTEG_FROM_RL2L3_MOD ] = { .pme_name = "PM_MRK_DPTEG_FROM_RL2L3_MOD", .pme_code = 0x2f146, .pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked data side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked data side request.", }, [ POWER8_PME_PM_MRK_DPTEG_FROM_RL2L3_SHR ] = { .pme_name = "PM_MRK_DPTEG_FROM_RL2L3_SHR", .pme_code = 0x1f14a, .pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked data side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked data side request.", }, [ POWER8_PME_PM_MRK_DPTEG_FROM_RL4 ] = { .pme_name = "PM_MRK_DPTEG_FROM_RL4", .pme_code = 0x2f14a, .pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a marked data side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a marked data side request.", }, [ POWER8_PME_PM_MRK_DPTEG_FROM_RMEM ] = { .pme_name = "PM_MRK_DPTEG_FROM_RMEM", .pme_code = 0x3f14a, .pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a marked data side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a marked data side request.", }, [ POWER8_PME_PM_MRK_DTLB_MISS ] = { .pme_name = "PM_MRK_DTLB_MISS", .pme_code = 0x401e4, .pme_short_desc = "Marked dtlb miss", .pme_long_desc = "Marked dtlb miss.", }, [ POWER8_PME_PM_MRK_DTLB_MISS_16G ] = { .pme_name = "PM_MRK_DTLB_MISS_16G", .pme_code = 0x1d158, .pme_short_desc = "Marked Data TLB Miss page size 16G", .pme_long_desc = "Marked Data TLB Miss page size 16G.", }, [ POWER8_PME_PM_MRK_DTLB_MISS_16M ] = { .pme_name = "PM_MRK_DTLB_MISS_16M", .pme_code = 0x4d156, .pme_short_desc = "Marked Data TLB Miss page size 16M", .pme_long_desc = "Marked Data TLB Miss page size 16M.", }, [ POWER8_PME_PM_MRK_DTLB_MISS_4K ] = { .pme_name = "PM_MRK_DTLB_MISS_4K", .pme_code = 0x2d156, .pme_short_desc = "Marked Data TLB Miss page size 4k", .pme_long_desc = "Marked Data TLB Miss page size 4k.", }, [ POWER8_PME_PM_MRK_DTLB_MISS_64K ] = { .pme_name = "PM_MRK_DTLB_MISS_64K", .pme_code = 0x3d156, .pme_short_desc = "Marked Data TLB Miss page size 64K", .pme_long_desc = "Marked Data TLB Miss page size 64K.", }, [ POWER8_PME_PM_MRK_FAB_RSP_BKILL ] = { .pme_name = "PM_MRK_FAB_RSP_BKILL", .pme_code = 0x40154, .pme_short_desc = "Marked store had to do a bkill", .pme_long_desc = "Marked store had to do a bkill.", }, [ POWER8_PME_PM_MRK_FAB_RSP_BKILL_CYC ] = { .pme_name = "PM_MRK_FAB_RSP_BKILL_CYC", .pme_code = 0x2f150, .pme_short_desc = "cycles L2 RC took for a bkill", .pme_long_desc = "cycles L2 RC took for a bkill.", }, [ POWER8_PME_PM_MRK_FAB_RSP_CLAIM_RTY ] = { .pme_name = "PM_MRK_FAB_RSP_CLAIM_RTY", .pme_code = 0x3015e, .pme_short_desc = "Sampled store did a rwitm and got a rty", .pme_long_desc = "Sampled store did a rwitm and got a rty.", }, [ POWER8_PME_PM_MRK_FAB_RSP_DCLAIM ] = { .pme_name = "PM_MRK_FAB_RSP_DCLAIM", .pme_code = 0x30154, .pme_short_desc = "Marked store had to do a dclaim", .pme_long_desc = "Marked store had to do a dclaim.", }, [ POWER8_PME_PM_MRK_FAB_RSP_DCLAIM_CYC ] = { .pme_name = "PM_MRK_FAB_RSP_DCLAIM_CYC", .pme_code = 0x2f152, .pme_short_desc = "cycles L2 RC took for a dclaim", .pme_long_desc = "cycles L2 RC took for a dclaim.", }, [ POWER8_PME_PM_MRK_FAB_RSP_MATCH ] = { .pme_name = "PM_MRK_FAB_RSP_MATCH", .pme_code = 0x30156, .pme_short_desc = "ttype and cresp matched as specified in MMCR1", .pme_long_desc = "ttype and cresp matched as specified in MMCR1.", }, [ POWER8_PME_PM_MRK_FAB_RSP_MATCH_CYC ] = { .pme_name = "PM_MRK_FAB_RSP_MATCH_CYC", .pme_code = 0x4f152, .pme_short_desc = "cresp/ttype match cycles", .pme_long_desc = "cresp/ttype match cycles.", }, [ POWER8_PME_PM_MRK_FAB_RSP_RD_RTY ] = { .pme_name = "PM_MRK_FAB_RSP_RD_RTY", .pme_code = 0x4015e, .pme_short_desc = "Sampled L2 reads retry count", .pme_long_desc = "Sampled L2 reads retry count.", }, [ POWER8_PME_PM_MRK_FAB_RSP_RD_T_INTV ] = { .pme_name = "PM_MRK_FAB_RSP_RD_T_INTV", .pme_code = 0x1015e, .pme_short_desc = "Sampled Read got a T intervention", .pme_long_desc = "Sampled Read got a T intervention.", }, [ POWER8_PME_PM_MRK_FAB_RSP_RWITM_CYC ] = { .pme_name = "PM_MRK_FAB_RSP_RWITM_CYC", .pme_code = 0x4f150, .pme_short_desc = "cycles L2 RC took for a rwitm", .pme_long_desc = "cycles L2 RC took for a rwitm.", }, [ POWER8_PME_PM_MRK_FAB_RSP_RWITM_RTY ] = { .pme_name = "PM_MRK_FAB_RSP_RWITM_RTY", .pme_code = 0x2015e, .pme_short_desc = "Sampled store did a rwitm and got a rty", .pme_long_desc = "Sampled store did a rwitm and got a rty.", }, [ POWER8_PME_PM_MRK_FILT_MATCH ] = { .pme_name = "PM_MRK_FILT_MATCH", .pme_code = 0x2013c, .pme_short_desc = "Marked filter Match", .pme_long_desc = "Marked filter Match.", }, [ POWER8_PME_PM_MRK_FIN_STALL_CYC ] = { .pme_name = "PM_MRK_FIN_STALL_CYC", .pme_code = 0x1013c, .pme_short_desc = "Marked instruction Finish Stall cycles (marked finish after NTC) (use edge detect to count )", .pme_long_desc = "Marked instruction Finish Stall cycles (marked finish after NTC) (use edge detect to count #).", }, [ POWER8_PME_PM_MRK_FXU_FIN ] = { .pme_name = "PM_MRK_FXU_FIN", .pme_code = 0x20134, .pme_short_desc = "fxu marked instr finish", .pme_long_desc = "fxu marked instr finish.", }, [ POWER8_PME_PM_MRK_GRP_CMPL ] = { .pme_name = "PM_MRK_GRP_CMPL", .pme_code = 0x40130, .pme_short_desc = "marked instruction finished (completed)", .pme_long_desc = "marked instruction finished (completed).", }, [ POWER8_PME_PM_MRK_GRP_IC_MISS ] = { .pme_name = "PM_MRK_GRP_IC_MISS", .pme_code = 0x4013a, .pme_short_desc = "Marked Group experienced I cache miss", .pme_long_desc = "Marked Group experienced I cache miss.", }, [ POWER8_PME_PM_MRK_GRP_NTC ] = { .pme_name = "PM_MRK_GRP_NTC", .pme_code = 0x3013c, .pme_short_desc = "Marked group ntc cycles.", .pme_long_desc = "Marked group ntc cycles.", }, [ POWER8_PME_PM_MRK_INST_CMPL ] = { .pme_name = "PM_MRK_INST_CMPL", .pme_code = 0x401e0, .pme_short_desc = "marked instruction completed", .pme_long_desc = "marked instruction completed.", }, [ POWER8_PME_PM_MRK_INST_DECODED ] = { .pme_name = "PM_MRK_INST_DECODED", .pme_code = 0x20130, .pme_short_desc = "marked instruction decoded", .pme_long_desc = "marked instruction decoded. Name from ISU?", }, [ POWER8_PME_PM_MRK_INST_DISP ] = { .pme_name = "PM_MRK_INST_DISP", .pme_code = 0x101e0, .pme_short_desc = "The thread has dispatched a randomly sampled marked instruction", .pme_long_desc = "Marked Instruction dispatched.", }, [ POWER8_PME_PM_MRK_INST_FIN ] = { .pme_name = "PM_MRK_INST_FIN", .pme_code = 0x30130, .pme_short_desc = "marked instruction finished", .pme_long_desc = "marked instr finish any unit .", }, [ POWER8_PME_PM_MRK_INST_FROM_L3MISS ] = { .pme_name = "PM_MRK_INST_FROM_L3MISS", .pme_code = 0x401e6, .pme_short_desc = "Marked instruction was reloaded from a location beyond the local chiplet", .pme_long_desc = "n/a", }, [ POWER8_PME_PM_MRK_INST_ISSUED ] = { .pme_name = "PM_MRK_INST_ISSUED", .pme_code = 0x10132, .pme_short_desc = "Marked instruction issued", .pme_long_desc = "Marked instruction issued.", }, [ POWER8_PME_PM_MRK_INST_TIMEO ] = { .pme_name = "PM_MRK_INST_TIMEO", .pme_code = 0x40134, .pme_short_desc = "marked Instruction finish timeout (instruction lost)", .pme_long_desc = "marked Instruction finish timeout (instruction lost).", }, [ POWER8_PME_PM_MRK_L1_ICACHE_MISS ] = { .pme_name = "PM_MRK_L1_ICACHE_MISS", .pme_code = 0x101e4, .pme_short_desc = "sampled Instruction suffered an icache Miss", .pme_long_desc = "Marked L1 Icache Miss.", }, [ POWER8_PME_PM_MRK_L1_RELOAD_VALID ] = { .pme_name = "PM_MRK_L1_RELOAD_VALID", .pme_code = 0x101ea, .pme_short_desc = "Marked demand reload", .pme_long_desc = "Marked demand reload.", }, [ POWER8_PME_PM_MRK_L2_RC_DISP ] = { .pme_name = "PM_MRK_L2_RC_DISP", .pme_code = 0x20114, .pme_short_desc = "Marked Instruction RC dispatched in L2", .pme_long_desc = "Marked Instruction RC dispatched in L2.", }, [ POWER8_PME_PM_MRK_L2_RC_DONE ] = { .pme_name = "PM_MRK_L2_RC_DONE", .pme_code = 0x3012a, .pme_short_desc = "Marked RC done", .pme_long_desc = "Marked RC done.", }, [ POWER8_PME_PM_MRK_LARX_FIN ] = { .pme_name = "PM_MRK_LARX_FIN", .pme_code = 0x40116, .pme_short_desc = "Larx finished", .pme_long_desc = "Larx finished .", }, [ POWER8_PME_PM_MRK_LD_MISS_EXPOSED ] = { .pme_name = "PM_MRK_LD_MISS_EXPOSED", .pme_code = 0x1013f, .pme_short_desc = "Marked Load exposed Miss (exposed period ended)", .pme_long_desc = "Marked Load exposed Miss (use edge detect to count #)", }, [ POWER8_PME_PM_MRK_LD_MISS_EXPOSED_CYC ] = { .pme_name = "PM_MRK_LD_MISS_EXPOSED_CYC", .pme_code = 0x1013e, .pme_short_desc = "Marked Load exposed Miss cycles", .pme_long_desc = "Marked Load exposed Miss (use edge detect to count #).", }, [ POWER8_PME_PM_MRK_LD_MISS_L1 ] = { .pme_name = "PM_MRK_LD_MISS_L1", .pme_code = 0x201e2, .pme_short_desc = "Marked DL1 Demand Miss counted at exec time", .pme_long_desc = "Marked DL1 Demand Miss counted at exec time.", }, [ POWER8_PME_PM_MRK_LD_MISS_L1_CYC ] = { .pme_name = "PM_MRK_LD_MISS_L1_CYC", .pme_code = 0x4013e, .pme_short_desc = "Marked ld latency", .pme_long_desc = "Marked ld latency.", }, [ POWER8_PME_PM_MRK_LSU_FIN ] = { .pme_name = "PM_MRK_LSU_FIN", .pme_code = 0x40132, .pme_short_desc = "lsu marked instr finish", .pme_long_desc = "lsu marked instr finish.", }, [ POWER8_PME_PM_MRK_LSU_FLUSH ] = { .pme_name = "PM_MRK_LSU_FLUSH", .pme_code = 0xd180, .pme_short_desc = "Flush: (marked) : All Cases", .pme_long_desc = "Flush: (marked) : All Cases42", }, [ POWER8_PME_PM_MRK_LSU_FLUSH_LRQ ] = { .pme_name = "PM_MRK_LSU_FLUSH_LRQ", .pme_code = 0xd188, .pme_short_desc = "Flush: (marked) LRQ", .pme_long_desc = "Flush: (marked) LRQMarked LRQ flushes", }, [ POWER8_PME_PM_MRK_LSU_FLUSH_SRQ ] = { .pme_name = "PM_MRK_LSU_FLUSH_SRQ", .pme_code = 0xd18a, .pme_short_desc = "Flush: (marked) SRQ", .pme_long_desc = "Flush: (marked) SRQMarked SRQ lhs flushes", }, [ POWER8_PME_PM_MRK_LSU_FLUSH_ULD ] = { .pme_name = "PM_MRK_LSU_FLUSH_ULD", .pme_code = 0xd184, .pme_short_desc = "Flush: (marked) Unaligned Load", .pme_long_desc = "Flush: (marked) Unaligned LoadMarked unaligned load flushes", }, [ POWER8_PME_PM_MRK_LSU_FLUSH_UST ] = { .pme_name = "PM_MRK_LSU_FLUSH_UST", .pme_code = 0xd186, .pme_short_desc = "Flush: (marked) Unaligned Store", .pme_long_desc = "Flush: (marked) Unaligned StoreMarked unaligned store flushes", }, [ POWER8_PME_PM_MRK_LSU_REJECT ] = { .pme_name = "PM_MRK_LSU_REJECT", .pme_code = 0x40164, .pme_short_desc = "LSU marked reject (up to 2 per cycle)", .pme_long_desc = "LSU marked reject (up to 2 per cycle).", }, [ POWER8_PME_PM_MRK_LSU_REJECT_ERAT_MISS ] = { .pme_name = "PM_MRK_LSU_REJECT_ERAT_MISS", .pme_code = 0x30164, .pme_short_desc = "LSU marked reject due to ERAT (up to 2 per cycle)", .pme_long_desc = "LSU marked reject due to ERAT (up to 2 per cycle).", }, [ POWER8_PME_PM_MRK_NTF_FIN ] = { .pme_name = "PM_MRK_NTF_FIN", .pme_code = 0x20112, .pme_short_desc = "Marked next to finish instruction finished", .pme_long_desc = "Marked next to finish instruction finished.", }, [ POWER8_PME_PM_MRK_RUN_CYC ] = { .pme_name = "PM_MRK_RUN_CYC", .pme_code = 0x1d15e, .pme_short_desc = "Marked run cycles", .pme_long_desc = "Marked run cycles.", }, [ POWER8_PME_PM_MRK_SRC_PREF_TRACK_EFF ] = { .pme_name = "PM_MRK_SRC_PREF_TRACK_EFF", .pme_code = 0x1d15a, .pme_short_desc = "Marked src pref track was effective", .pme_long_desc = "Marked src pref track was effective.", }, [ POWER8_PME_PM_MRK_SRC_PREF_TRACK_INEFF ] = { .pme_name = "PM_MRK_SRC_PREF_TRACK_INEFF", .pme_code = 0x3d15a, .pme_short_desc = "Prefetch tracked was ineffective for marked src", .pme_long_desc = "Prefetch tracked was ineffective for marked src.", }, [ POWER8_PME_PM_MRK_SRC_PREF_TRACK_MOD ] = { .pme_name = "PM_MRK_SRC_PREF_TRACK_MOD", .pme_code = 0x4d15c, .pme_short_desc = "Prefetch tracked was moderate for marked src", .pme_long_desc = "Prefetch tracked was moderate for marked src.", }, [ POWER8_PME_PM_MRK_SRC_PREF_TRACK_MOD_L2 ] = { .pme_name = "PM_MRK_SRC_PREF_TRACK_MOD_L2", .pme_code = 0x1d15c, .pme_short_desc = "Marked src Prefetch Tracked was moderate (source L2)", .pme_long_desc = "Marked src Prefetch Tracked was moderate (source L2).", }, [ POWER8_PME_PM_MRK_SRC_PREF_TRACK_MOD_L3 ] = { .pme_name = "PM_MRK_SRC_PREF_TRACK_MOD_L3", .pme_code = 0x3d15c, .pme_short_desc = "Prefetch tracked was moderate (L3 hit) for marked src", .pme_long_desc = "Prefetch tracked was moderate (L3 hit) for marked src.", }, [ POWER8_PME_PM_MRK_STALL_CMPLU_CYC ] = { .pme_name = "PM_MRK_STALL_CMPLU_CYC", .pme_code = 0x3013e, .pme_short_desc = "Marked Group completion Stall", .pme_long_desc = "Marked Group Completion Stall cycles (use edge detect to count #).", }, [ POWER8_PME_PM_MRK_STCX_FAIL ] = { .pme_name = "PM_MRK_STCX_FAIL", .pme_code = 0x3e158, .pme_short_desc = "marked stcx failed", .pme_long_desc = "marked stcx failed.", }, [ POWER8_PME_PM_MRK_ST_CMPL ] = { .pme_name = "PM_MRK_ST_CMPL", .pme_code = 0x10134, .pme_short_desc = "marked store completed and sent to nest", .pme_long_desc = "Marked store completed.", }, [ POWER8_PME_PM_MRK_ST_CMPL_INT ] = { .pme_name = "PM_MRK_ST_CMPL_INT", .pme_code = 0x30134, .pme_short_desc = "marked store finished with intervention", .pme_long_desc = "marked store complete (data home) with intervention.", }, [ POWER8_PME_PM_MRK_ST_DRAIN_TO_L2DISP_CYC ] = { .pme_name = "PM_MRK_ST_DRAIN_TO_L2DISP_CYC", .pme_code = 0x3f150, .pme_short_desc = "cycles to drain st from core to L2", .pme_long_desc = "cycles to drain st from core to L2.", }, [ POWER8_PME_PM_MRK_ST_FWD ] = { .pme_name = "PM_MRK_ST_FWD", .pme_code = 0x3012c, .pme_short_desc = "Marked st forwards", .pme_long_desc = "Marked st forwards.", }, [ POWER8_PME_PM_MRK_ST_L2DISP_TO_CMPL_CYC ] = { .pme_name = "PM_MRK_ST_L2DISP_TO_CMPL_CYC", .pme_code = 0x1f150, .pme_short_desc = "cycles from L2 rc disp to l2 rc completion", .pme_long_desc = "cycles from L2 rc disp to l2 rc completion.", }, [ POWER8_PME_PM_MRK_ST_NEST ] = { .pme_name = "PM_MRK_ST_NEST", .pme_code = 0x20138, .pme_short_desc = "Marked store sent to nest", .pme_long_desc = "Marked store sent to nest.", }, [ POWER8_PME_PM_MRK_TGT_PREF_TRACK_EFF ] = { .pme_name = "PM_MRK_TGT_PREF_TRACK_EFF", .pme_code = 0x1c15a, .pme_short_desc = "Marked target pref track was effective", .pme_long_desc = "Marked target pref track was effective.", }, [ POWER8_PME_PM_MRK_TGT_PREF_TRACK_INEFF ] = { .pme_name = "PM_MRK_TGT_PREF_TRACK_INEFF", .pme_code = 0x3c15a, .pme_short_desc = "Prefetch tracked was ineffective for marked target", .pme_long_desc = "Prefetch tracked was ineffective for marked target.", }, [ POWER8_PME_PM_MRK_TGT_PREF_TRACK_MOD ] = { .pme_name = "PM_MRK_TGT_PREF_TRACK_MOD", .pme_code = 0x4c15c, .pme_short_desc = "Prefetch tracked was moderate for marked target", .pme_long_desc = "Prefetch tracked was moderate for marked target.", }, [ POWER8_PME_PM_MRK_TGT_PREF_TRACK_MOD_L2 ] = { .pme_name = "PM_MRK_TGT_PREF_TRACK_MOD_L2", .pme_code = 0x1c15c, .pme_short_desc = "Marked target Prefetch Tracked was moderate (source L2)", .pme_long_desc = "Marked target Prefetch Tracked was moderate (source L2).", }, [ POWER8_PME_PM_MRK_TGT_PREF_TRACK_MOD_L3 ] = { .pme_name = "PM_MRK_TGT_PREF_TRACK_MOD_L3", .pme_code = 0x3c15c, .pme_short_desc = "Prefetch tracked was moderate (L3 hit) for marked target", .pme_long_desc = "Prefetch tracked was moderate (L3 hit) for marked target.", }, [ POWER8_PME_PM_MRK_VSU_FIN ] = { .pme_name = "PM_MRK_VSU_FIN", .pme_code = 0x30132, .pme_short_desc = "VSU marked instr finish", .pme_long_desc = "vsu (fpu) marked instr finish.", }, [ POWER8_PME_PM_MULT_MRK ] = { .pme_name = "PM_MULT_MRK", .pme_code = 0x3d15e, .pme_short_desc = "mult marked instr", .pme_long_desc = "mult marked instr.", }, [ POWER8_PME_PM_NESTED_TEND ] = { .pme_name = "PM_NESTED_TEND", .pme_code = 0x20b0, .pme_short_desc = "Completion time nested tend", .pme_long_desc = "Completion time nested tend", }, [ POWER8_PME_PM_NEST_REF_CLK ] = { .pme_name = "PM_NEST_REF_CLK", .pme_code = 0x3006e, .pme_short_desc = "Multiply by 4 to obtain the number of PB cycles", .pme_long_desc = "Nest reference clocks.", }, [ POWER8_PME_PM_NON_FAV_TBEGIN ] = { .pme_name = "PM_NON_FAV_TBEGIN", .pme_code = 0x20b6, .pme_short_desc = "Dispatch time non favored tbegin", .pme_long_desc = "Dispatch time non favored tbegin", }, [ POWER8_PME_PM_NON_TM_RST_SC ] = { .pme_name = "PM_NON_TM_RST_SC", .pme_code = 0x328084, .pme_short_desc = "non tm snp rst tm sc", .pme_long_desc = "non tm snp rst tm sc", }, [ POWER8_PME_PM_NTCG_ALL_FIN ] = { .pme_name = "PM_NTCG_ALL_FIN", .pme_code = 0x2001a, .pme_short_desc = "Cycles after all instructions have finished to group completed", .pme_long_desc = "Ccycles after all instructions have finished to group completed.", }, [ POWER8_PME_PM_OUTER_TBEGIN ] = { .pme_name = "PM_OUTER_TBEGIN", .pme_code = 0x20ac, .pme_short_desc = "Completion time outer tbegin", .pme_long_desc = "Completion time outer tbegin", }, [ POWER8_PME_PM_OUTER_TEND ] = { .pme_name = "PM_OUTER_TEND", .pme_code = 0x20ae, .pme_short_desc = "Completion time outer tend", .pme_long_desc = "Completion time outer tend", }, [ POWER8_PME_PM_PMC1_OVERFLOW ] = { .pme_name = "PM_PMC1_OVERFLOW", .pme_code = 0x20010, .pme_short_desc = "Overflow from counter 1", .pme_long_desc = "Overflow from counter 1.", }, [ POWER8_PME_PM_PMC2_OVERFLOW ] = { .pme_name = "PM_PMC2_OVERFLOW", .pme_code = 0x30010, .pme_short_desc = "Overflow from counter 2", .pme_long_desc = "Overflow from counter 2.", }, [ POWER8_PME_PM_PMC2_REWIND ] = { .pme_name = "PM_PMC2_REWIND", .pme_code = 0x30020, .pme_short_desc = "PMC2 Rewind Event (did not match condition)", .pme_long_desc = "PMC2 Rewind Event (did not match condition).", }, [ POWER8_PME_PM_PMC2_SAVED ] = { .pme_name = "PM_PMC2_SAVED", .pme_code = 0x10022, .pme_short_desc = "PMC2 Rewind Value saved", .pme_long_desc = "PMC2 Rewind Value saved (matched condition).", }, [ POWER8_PME_PM_PMC3_OVERFLOW ] = { .pme_name = "PM_PMC3_OVERFLOW", .pme_code = 0x40010, .pme_short_desc = "Overflow from counter 3", .pme_long_desc = "Overflow from counter 3.", }, [ POWER8_PME_PM_PMC4_OVERFLOW ] = { .pme_name = "PM_PMC4_OVERFLOW", .pme_code = 0x10010, .pme_short_desc = "Overflow from counter 4", .pme_long_desc = "Overflow from counter 4.", }, [ POWER8_PME_PM_PMC4_REWIND ] = { .pme_name = "PM_PMC4_REWIND", .pme_code = 0x10020, .pme_short_desc = "PMC4 Rewind Event", .pme_long_desc = "PMC4 Rewind Event (did not match condition).", }, [ POWER8_PME_PM_PMC4_SAVED ] = { .pme_name = "PM_PMC4_SAVED", .pme_code = 0x30022, .pme_short_desc = "PMC4 Rewind Value saved (matched condition)", .pme_long_desc = "PMC4 Rewind Value saved (matched condition).", }, [ POWER8_PME_PM_PMC5_OVERFLOW ] = { .pme_name = "PM_PMC5_OVERFLOW", .pme_code = 0x10024, .pme_short_desc = "Overflow from counter 5", .pme_long_desc = "Overflow from counter 5.", }, [ POWER8_PME_PM_PMC6_OVERFLOW ] = { .pme_name = "PM_PMC6_OVERFLOW", .pme_code = 0x30024, .pme_short_desc = "Overflow from counter 6", .pme_long_desc = "Overflow from counter 6.", }, [ POWER8_PME_PM_PREF_TRACKED ] = { .pme_name = "PM_PREF_TRACKED", .pme_code = 0x2005a, .pme_short_desc = "Total number of Prefetch Operations that were tracked", .pme_long_desc = "Total number of Prefetch Operations that were tracked.", }, [ POWER8_PME_PM_PREF_TRACK_EFF ] = { .pme_name = "PM_PREF_TRACK_EFF", .pme_code = 0x1005a, .pme_short_desc = "Prefetch Tracked was effective", .pme_long_desc = "Prefetch Tracked was effective.", }, [ POWER8_PME_PM_PREF_TRACK_INEFF ] = { .pme_name = "PM_PREF_TRACK_INEFF", .pme_code = 0x3005a, .pme_short_desc = "Prefetch tracked was ineffective", .pme_long_desc = "Prefetch tracked was ineffective.", }, [ POWER8_PME_PM_PREF_TRACK_MOD ] = { .pme_name = "PM_PREF_TRACK_MOD", .pme_code = 0x4005a, .pme_short_desc = "Prefetch tracked was moderate", .pme_long_desc = "Prefetch tracked was moderate.", }, [ POWER8_PME_PM_PREF_TRACK_MOD_L2 ] = { .pme_name = "PM_PREF_TRACK_MOD_L2", .pme_code = 0x1005c, .pme_short_desc = "Prefetch Tracked was moderate (source L2)", .pme_long_desc = "Prefetch Tracked was moderate (source L2).", }, [ POWER8_PME_PM_PREF_TRACK_MOD_L3 ] = { .pme_name = "PM_PREF_TRACK_MOD_L3", .pme_code = 0x3005c, .pme_short_desc = "Prefetch tracked was moderate (L3)", .pme_long_desc = "Prefetch tracked was moderate (L3).", }, [ POWER8_PME_PM_PROBE_NOP_DISP ] = { .pme_name = "PM_PROBE_NOP_DISP", .pme_code = 0x40014, .pme_short_desc = "ProbeNops dispatched", .pme_long_desc = "ProbeNops dispatched.", }, [ POWER8_PME_PM_PTE_PREFETCH ] = { .pme_name = "PM_PTE_PREFETCH", .pme_code = 0xe084, .pme_short_desc = "PTE prefetches", .pme_long_desc = "PTE prefetches42", }, [ POWER8_PME_PM_PUMP_CPRED ] = { .pme_name = "PM_PUMP_CPRED", .pme_code = 0x10054, .pme_short_desc = "Pump prediction correct. Counts across all types of pumps for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)", .pme_long_desc = "Pump prediction correct. Counts across all types of pumpsfor all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate).", }, [ POWER8_PME_PM_PUMP_MPRED ] = { .pme_name = "PM_PUMP_MPRED", .pme_code = 0x40052, .pme_short_desc = "Pump misprediction. Counts across all types of pumps for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)", .pme_long_desc = "Pump Mis prediction Counts across all types of pumpsfor all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate).", }, [ POWER8_PME_PM_RC0_ALLOC ] = { .pme_name = "PM_RC0_ALLOC", .pme_code = 0x16081, .pme_short_desc = "RC mach 0 Busy. Used by PMU to sample ave RC livetime(mach0 used as sample point)", .pme_long_desc = "0.0", }, [ POWER8_PME_PM_RC0_BUSY ] = { .pme_name = "PM_RC0_BUSY", .pme_code = 0x16080, .pme_short_desc = "RC mach 0 Busy. Used by PMU to sample ave RC livetime(mach0 used as sample point)", .pme_long_desc = "RC mach 0 Busy. Used by PMU to sample ave RC livetime(mach0 used as sample point)", }, [ POWER8_PME_PM_RC_LIFETIME_EXC_1024 ] = { .pme_name = "PM_RC_LIFETIME_EXC_1024", .pme_code = 0xde200301eaull, .pme_short_desc = "Number of times the RC machine for a sampled instruction was active for more than 1024 cycles", .pme_long_desc = "Reload latency exceeded 1024 cyc", }, [ POWER8_PME_PM_RC_LIFETIME_EXC_2048 ] = { .pme_name = "PM_RC_LIFETIME_EXC_2048", .pme_code = 0xde200401ecull, .pme_short_desc = "Number of times the RC machine for a sampled instruction was active for more than 2048 cycles", .pme_long_desc = "Threshold counter exceeded a value of 2048", }, [ POWER8_PME_PM_RC_LIFETIME_EXC_256 ] = { .pme_name = "PM_RC_LIFETIME_EXC_256", .pme_code = 0xde200101e8ull, .pme_short_desc = "Number of times the RC machine for a sampled instruction was active for more than 256 cycles", .pme_long_desc = "Threshold counter exceed a count of 256", }, [ POWER8_PME_PM_RC_LIFETIME_EXC_32 ] = { .pme_name = "PM_RC_LIFETIME_EXC_32", .pme_code = 0xde200201e6ull, .pme_short_desc = "Number of times the RC machine for a sampled instruction was active for more than 32 cycles", .pme_long_desc = "Reload latency exceeded 32 cyc", }, [ POWER8_PME_PM_RC_USAGE ] = { .pme_name = "PM_RC_USAGE", .pme_code = 0x36088, .pme_short_desc = "Continuous 16 cycle(2to1) window where this signals rotates thru sampling each L2 RC machine busy. PMU uses this wave to then do 16 cyc count to sample total number of machs running", .pme_long_desc = "Continuous 16 cycle(2to1) window where this signals rotates thru sampling each L2 RC machine busy. PMU uses this wave to then do 16 cyc count to sample total number of machs running", }, [ POWER8_PME_PM_RD_CLEARING_SC ] = { .pme_name = "PM_RD_CLEARING_SC", .pme_code = 0x34808e, .pme_short_desc = "rd clearing sc", .pme_long_desc = "rd clearing sc", }, [ POWER8_PME_PM_RD_FORMING_SC ] = { .pme_name = "PM_RD_FORMING_SC", .pme_code = 0x34808c, .pme_short_desc = "rd forming sc", .pme_long_desc = "rd forming sc", }, [ POWER8_PME_PM_RD_HIT_PF ] = { .pme_name = "PM_RD_HIT_PF", .pme_code = 0x428086, .pme_short_desc = "rd machine hit l3 pf machine", .pme_long_desc = "rd machine hit l3 pf machine", }, [ POWER8_PME_PM_REAL_SRQ_FULL ] = { .pme_name = "PM_REAL_SRQ_FULL", .pme_code = 0x20004, .pme_short_desc = "Out of real srq entries", .pme_long_desc = "Out of real srq entries.", }, [ POWER8_PME_PM_RUN_CYC ] = { .pme_name = "PM_RUN_CYC", .pme_code = 0x600f4, .pme_short_desc = "Run_cycles", .pme_long_desc = "Run_cycles.", }, [ POWER8_PME_PM_RUN_CYC_SMT2_MODE ] = { .pme_name = "PM_RUN_CYC_SMT2_MODE", .pme_code = 0x3006c, .pme_short_desc = "Cycles run latch is set and core is in SMT2 mode", .pme_long_desc = "Cycles run latch is set and core is in SMT2 mode.", }, [ POWER8_PME_PM_RUN_CYC_SMT2_SHRD_MODE ] = { .pme_name = "PM_RUN_CYC_SMT2_SHRD_MODE", .pme_code = 0x2006a, .pme_short_desc = "cycles this threads run latch is set and the core is in SMT2 shared mode", .pme_long_desc = "Cycles run latch is set and core is in SMT2-shared mode.", }, [ POWER8_PME_PM_RUN_CYC_SMT2_SPLIT_MODE ] = { .pme_name = "PM_RUN_CYC_SMT2_SPLIT_MODE", .pme_code = 0x1006a, .pme_short_desc = "Cycles run latch is set and core is in SMT2-split mode", .pme_long_desc = "Cycles run latch is set and core is in SMT2-split mode.", }, [ POWER8_PME_PM_RUN_CYC_SMT4_MODE ] = { .pme_name = "PM_RUN_CYC_SMT4_MODE", .pme_code = 0x2006c, .pme_short_desc = "cycles this threads run latch is set and the core is in SMT4 mode", .pme_long_desc = "Cycles run latch is set and core is in SMT4 mode.", }, [ POWER8_PME_PM_RUN_CYC_SMT8_MODE ] = { .pme_name = "PM_RUN_CYC_SMT8_MODE", .pme_code = 0x4006c, .pme_short_desc = "Cycles run latch is set and core is in SMT8 mode", .pme_long_desc = "Cycles run latch is set and core is in SMT8 mode.", }, [ POWER8_PME_PM_RUN_CYC_ST_MODE ] = { .pme_name = "PM_RUN_CYC_ST_MODE", .pme_code = 0x1006c, .pme_short_desc = "Cycles run latch is set and core is in ST mode", .pme_long_desc = "Cycles run latch is set and core is in ST mode.", }, [ POWER8_PME_PM_RUN_INST_CMPL ] = { .pme_name = "PM_RUN_INST_CMPL", .pme_code = 0x500fa, .pme_short_desc = "Run_Instructions", .pme_long_desc = "Run_Instructions.", }, [ POWER8_PME_PM_RUN_PURR ] = { .pme_name = "PM_RUN_PURR", .pme_code = 0x400f4, .pme_short_desc = "Run_PURR", .pme_long_desc = "Run_PURR.", }, [ POWER8_PME_PM_RUN_SPURR ] = { .pme_name = "PM_RUN_SPURR", .pme_code = 0x10008, .pme_short_desc = "Run SPURR", .pme_long_desc = "Run SPURR.", }, [ POWER8_PME_PM_SEC_ERAT_HIT ] = { .pme_name = "PM_SEC_ERAT_HIT", .pme_code = 0xf082, .pme_short_desc = "secondary ERAT Hit", .pme_long_desc = "secondary ERAT Hit42", }, [ POWER8_PME_PM_SHL_CREATED ] = { .pme_name = "PM_SHL_CREATED", .pme_code = 0x508c, .pme_short_desc = "Store-Hit-Load Table Entry Created", .pme_long_desc = "Store-Hit-Load Table Entry Created", }, [ POWER8_PME_PM_SHL_ST_CONVERT ] = { .pme_name = "PM_SHL_ST_CONVERT", .pme_code = 0x508e, .pme_short_desc = "Store-Hit-Load Table Read Hit with entry Enabled", .pme_long_desc = "Store-Hit-Load Table Read Hit with entry Enabled", }, [ POWER8_PME_PM_SHL_ST_DISABLE ] = { .pme_name = "PM_SHL_ST_DISABLE", .pme_code = 0x5090, .pme_short_desc = "Store-Hit-Load Table Read Hit with entry Disabled (entry was disabled due to the entry shown to not prevent the flush)", .pme_long_desc = "Store-Hit-Load Table Read Hit with entry Disabled (entry was disabled due to the entry shown to not prevent the flush)", }, [ POWER8_PME_PM_SN0_ALLOC ] = { .pme_name = "PM_SN0_ALLOC", .pme_code = 0x26085, .pme_short_desc = "SN mach 0 Busy. Used by PMU to sample ave RC livetime(mach0 used as sample point)", .pme_long_desc = "0.0", }, [ POWER8_PME_PM_SN0_BUSY ] = { .pme_name = "PM_SN0_BUSY", .pme_code = 0x26084, .pme_short_desc = "SN mach 0 Busy. Used by PMU to sample ave RC livetime(mach0 used as sample point)", .pme_long_desc = "SN mach 0 Busy. Used by PMU to sample ave RC livetime(mach0 used as sample point)", }, [ POWER8_PME_PM_SNOOP_TLBIE ] = { .pme_name = "PM_SNOOP_TLBIE", .pme_code = 0xd0b2, .pme_short_desc = "TLBIE snoop", .pme_long_desc = "TLBIE snoopSnoop TLBIE", }, [ POWER8_PME_PM_SNP_TM_HIT_M ] = { .pme_name = "PM_SNP_TM_HIT_M", .pme_code = 0x338088, .pme_short_desc = "snp tm st hit m mu", .pme_long_desc = "snp tm st hit m mu", }, [ POWER8_PME_PM_SNP_TM_HIT_T ] = { .pme_name = "PM_SNP_TM_HIT_T", .pme_code = 0x33808a, .pme_short_desc = "snp tm_st_hit t tn te", .pme_long_desc = "snp tm_st_hit t tn te", }, [ POWER8_PME_PM_SN_USAGE ] = { .pme_name = "PM_SN_USAGE", .pme_code = 0x4608c, .pme_short_desc = "Continuous 16 cycle(2to1) window where this signals rotates thru sampling each L2 SN machine busy. PMU uses this wave to then do 16 cyc count to sample total number of machs running", .pme_long_desc = "Continuous 16 cycle(2to1) window where this signals rotates thru sampling each L2 SN machine busy. PMU uses this wave to then do 16 cyc count to sample total number of machs running", }, [ POWER8_PME_PM_STALL_END_GCT_EMPTY ] = { .pme_name = "PM_STALL_END_GCT_EMPTY", .pme_code = 0x10028, .pme_short_desc = "Count ended because GCT went empty", .pme_long_desc = "Count ended because GCT went empty.", }, [ POWER8_PME_PM_STCX_FAIL ] = { .pme_name = "PM_STCX_FAIL", .pme_code = 0x1e058, .pme_short_desc = "stcx failed", .pme_long_desc = "stcx failed .", }, [ POWER8_PME_PM_STCX_LSU ] = { .pme_name = "PM_STCX_LSU", .pme_code = 0xc090, .pme_short_desc = "STCX executed reported at sent to nest", .pme_long_desc = "STCX executed reported at sent to nest42", }, [ POWER8_PME_PM_ST_CAUSED_FAIL ] = { .pme_name = "PM_ST_CAUSED_FAIL", .pme_code = 0x717080, .pme_short_desc = "Non TM St caused any thread to fail", .pme_long_desc = "Non TM St caused any thread to fail", }, [ POWER8_PME_PM_ST_CMPL ] = { .pme_name = "PM_ST_CMPL", .pme_code = 0x20016, .pme_short_desc = "Store completion count", .pme_long_desc = "Store completion count.", }, [ POWER8_PME_PM_ST_FIN ] = { .pme_name = "PM_ST_FIN", .pme_code = 0x200f0, .pme_short_desc = "Store Instructions Finished", .pme_long_desc = "Store Instructions Finished (store sent to nest).", }, [ POWER8_PME_PM_ST_FWD ] = { .pme_name = "PM_ST_FWD", .pme_code = 0x20018, .pme_short_desc = "Store forwards that finished", .pme_long_desc = "Store forwards that finished.", }, [ POWER8_PME_PM_ST_MISS_L1 ] = { .pme_name = "PM_ST_MISS_L1", .pme_code = 0x300f0, .pme_short_desc = "Store Missed L1", .pme_long_desc = "Store Missed L1.", }, [ POWER8_PME_PM_SUSPENDED ] = { .pme_name = "PM_SUSPENDED", .pme_code = 0x0, .pme_short_desc = "Counter OFF", .pme_long_desc = "Counter OFF.", }, [ POWER8_PME_PM_SWAP_CANCEL ] = { .pme_name = "PM_SWAP_CANCEL", .pme_code = 0x3090, .pme_short_desc = "SWAP cancel , rtag not available", .pme_long_desc = "SWAP cancel , rtag not available", }, [ POWER8_PME_PM_SWAP_CANCEL_GPR ] = { .pme_name = "PM_SWAP_CANCEL_GPR", .pme_code = 0x3092, .pme_short_desc = "SWAP cancel , rtag not available for gpr", .pme_long_desc = "SWAP cancel , rtag not available for gpr", }, [ POWER8_PME_PM_SWAP_COMPLETE ] = { .pme_name = "PM_SWAP_COMPLETE", .pme_code = 0x308c, .pme_short_desc = "swap cast in completed", .pme_long_desc = "swap cast in completed", }, [ POWER8_PME_PM_SWAP_COMPLETE_GPR ] = { .pme_name = "PM_SWAP_COMPLETE_GPR", .pme_code = 0x308e, .pme_short_desc = "swap cast in completed fpr gpr", .pme_long_desc = "swap cast in completed fpr gpr", }, [ POWER8_PME_PM_SYNC_MRK_BR_LINK ] = { .pme_name = "PM_SYNC_MRK_BR_LINK", .pme_code = 0x15152, .pme_short_desc = "Marked Branch and link branch that can cause a synchronous interrupt", .pme_long_desc = "Marked Branch and link branch that can cause a synchronous interrupt.", }, [ POWER8_PME_PM_SYNC_MRK_BR_MPRED ] = { .pme_name = "PM_SYNC_MRK_BR_MPRED", .pme_code = 0x1515c, .pme_short_desc = "Marked Branch mispredict that can cause a synchronous interrupt", .pme_long_desc = "Marked Branch mispredict that can cause a synchronous interrupt.", }, [ POWER8_PME_PM_SYNC_MRK_FX_DIVIDE ] = { .pme_name = "PM_SYNC_MRK_FX_DIVIDE", .pme_code = 0x15156, .pme_short_desc = "Marked fixed point divide that can cause a synchronous interrupt", .pme_long_desc = "Marked fixed point divide that can cause a synchronous interrupt.", }, [ POWER8_PME_PM_SYNC_MRK_L2HIT ] = { .pme_name = "PM_SYNC_MRK_L2HIT", .pme_code = 0x15158, .pme_short_desc = "Marked L2 Hits that can throw a synchronous interrupt", .pme_long_desc = "Marked L2 Hits that can throw a synchronous interrupt.", }, [ POWER8_PME_PM_SYNC_MRK_L2MISS ] = { .pme_name = "PM_SYNC_MRK_L2MISS", .pme_code = 0x1515a, .pme_short_desc = "Marked L2 Miss that can throw a synchronous interrupt", .pme_long_desc = "Marked L2 Miss that can throw a synchronous interrupt.", }, [ POWER8_PME_PM_SYNC_MRK_L3MISS ] = { .pme_name = "PM_SYNC_MRK_L3MISS", .pme_code = 0x15154, .pme_short_desc = "Marked L3 misses that can throw a synchronous interrupt", .pme_long_desc = "Marked L3 misses that can throw a synchronous interrupt.", }, [ POWER8_PME_PM_SYNC_MRK_PROBE_NOP ] = { .pme_name = "PM_SYNC_MRK_PROBE_NOP", .pme_code = 0x15150, .pme_short_desc = "Marked probeNops which can cause synchronous interrupts", .pme_long_desc = "Marked probeNops which can cause synchronous interrupts.", }, [ POWER8_PME_PM_SYS_PUMP_CPRED ] = { .pme_name = "PM_SYS_PUMP_CPRED", .pme_code = 0x30050, .pme_short_desc = "Initial and Final Pump Scope was system pump for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)", .pme_long_desc = "Initial and Final Pump Scope and data sourced across this scope was system pump for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate).", }, [ POWER8_PME_PM_SYS_PUMP_MPRED ] = { .pme_name = "PM_SYS_PUMP_MPRED", .pme_code = 0x30052, .pme_short_desc = "Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)", .pme_long_desc = "Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope(Chip/Group) OR Final Pump Scope(system) got data from source that was at smaller scope(Chip/group) Final pump was system pump and initial pump was chip or group or", }, [ POWER8_PME_PM_SYS_PUMP_MPRED_RTY ] = { .pme_name = "PM_SYS_PUMP_MPRED_RTY", .pme_code = 0x40050, .pme_short_desc = "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)", .pme_long_desc = "Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope (Chip or Group) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate).", }, [ POWER8_PME_PM_TABLEWALK_CYC ] = { .pme_name = "PM_TABLEWALK_CYC", .pme_code = 0x10026, .pme_short_desc = "Cycles when a tablewalk (I or D) is active", .pme_long_desc = "Tablewalk Active.", }, [ POWER8_PME_PM_TABLEWALK_CYC_PREF ] = { .pme_name = "PM_TABLEWALK_CYC_PREF", .pme_code = 0xe086, .pme_short_desc = "tablewalk qualified for pte prefetches", .pme_long_desc = "tablewalk qualified for pte prefetches42", }, [ POWER8_PME_PM_TABORT_TRECLAIM ] = { .pme_name = "PM_TABORT_TRECLAIM", .pme_code = 0x20b2, .pme_short_desc = "Completion time tabortnoncd, tabortcd, treclaim", .pme_long_desc = "Completion time tabortnoncd, tabortcd, treclaim", }, [ POWER8_PME_PM_TB_BIT_TRANS ] = { .pme_name = "PM_TB_BIT_TRANS", .pme_code = 0x300f8, .pme_short_desc = "timebase event", .pme_long_desc = "timebase event.", }, [ POWER8_PME_PM_TEND_PEND_CYC ] = { .pme_name = "PM_TEND_PEND_CYC", .pme_code = 0xe0ba, .pme_short_desc = "TEND latency per thread", .pme_long_desc = "TEND latency per thread42", }, [ POWER8_PME_PM_THRD_ALL_RUN_CYC ] = { .pme_name = "PM_THRD_ALL_RUN_CYC", .pme_code = 0x2000c, .pme_short_desc = "All Threads in Run_cycles (was both threads in run_cycles)", .pme_long_desc = "All Threads in Run_cycles (was both threads in run_cycles).", }, [ POWER8_PME_PM_THRD_CONC_RUN_INST ] = { .pme_name = "PM_THRD_CONC_RUN_INST", .pme_code = 0x300f4, .pme_short_desc = "PPC Instructions Finished when both threads in run_cycles", .pme_long_desc = "Concurrent Run Instructions.", }, [ POWER8_PME_PM_THRD_GRP_CMPL_BOTH_CYC ] = { .pme_name = "PM_THRD_GRP_CMPL_BOTH_CYC", .pme_code = 0x10012, .pme_short_desc = "Cycles group completed on both completion slots by any thread", .pme_long_desc = "Two threads finished same cycle (gated by run latch).", }, [ POWER8_PME_PM_THRD_PRIO_0_1_CYC ] = { .pme_name = "PM_THRD_PRIO_0_1_CYC", .pme_code = 0x40bc, .pme_short_desc = "Cycles thread running at priority level 0 or 1", .pme_long_desc = "Cycles thread running at priority level 0 or 1", }, [ POWER8_PME_PM_THRD_PRIO_2_3_CYC ] = { .pme_name = "PM_THRD_PRIO_2_3_CYC", .pme_code = 0x40be, .pme_short_desc = "Cycles thread running at priority level 2 or 3", .pme_long_desc = "Cycles thread running at priority level 2 or 3", }, [ POWER8_PME_PM_THRD_PRIO_4_5_CYC ] = { .pme_name = "PM_THRD_PRIO_4_5_CYC", .pme_code = 0x5080, .pme_short_desc = "Cycles thread running at priority level 4 or 5", .pme_long_desc = "Cycles thread running at priority level 4 or 5", }, [ POWER8_PME_PM_THRD_PRIO_6_7_CYC ] = { .pme_name = "PM_THRD_PRIO_6_7_CYC", .pme_code = 0x5082, .pme_short_desc = "Cycles thread running at priority level 6 or 7", .pme_long_desc = "Cycles thread running at priority level 6 or 7", }, [ POWER8_PME_PM_THRD_REBAL_CYC ] = { .pme_name = "PM_THRD_REBAL_CYC", .pme_code = 0x3098, .pme_short_desc = "cycles rebalance was active", .pme_long_desc = "cycles rebalance was active", }, [ POWER8_PME_PM_THRESH_EXC_1024 ] = { .pme_name = "PM_THRESH_EXC_1024", .pme_code = 0x301ea, .pme_short_desc = "Threshold counter exceeded a value of 1024", .pme_long_desc = "Threshold counter exceeded a value of 1024.", }, [ POWER8_PME_PM_THRESH_EXC_128 ] = { .pme_name = "PM_THRESH_EXC_128", .pme_code = 0x401ea, .pme_short_desc = "Threshold counter exceeded a value of 128", .pme_long_desc = "Threshold counter exceeded a value of 128.", }, [ POWER8_PME_PM_THRESH_EXC_2048 ] = { .pme_name = "PM_THRESH_EXC_2048", .pme_code = 0x401ec, .pme_short_desc = "Threshold counter exceeded a value of 2048", .pme_long_desc = "Threshold counter exceeded a value of 2048.", }, [ POWER8_PME_PM_THRESH_EXC_256 ] = { .pme_name = "PM_THRESH_EXC_256", .pme_code = 0x101e8, .pme_short_desc = "Threshold counter exceed a count of 256", .pme_long_desc = "Threshold counter exceed a count of 256.", }, [ POWER8_PME_PM_THRESH_EXC_32 ] = { .pme_name = "PM_THRESH_EXC_32", .pme_code = 0x201e6, .pme_short_desc = "Threshold counter exceeded a value of 32", .pme_long_desc = "Threshold counter exceeded a value of 32.", }, [ POWER8_PME_PM_THRESH_EXC_4096 ] = { .pme_name = "PM_THRESH_EXC_4096", .pme_code = 0x101e6, .pme_short_desc = "Threshold counter exceed a count of 4096", .pme_long_desc = "Threshold counter exceed a count of 4096.", }, [ POWER8_PME_PM_THRESH_EXC_512 ] = { .pme_name = "PM_THRESH_EXC_512", .pme_code = 0x201e8, .pme_short_desc = "Threshold counter exceeded a value of 512", .pme_long_desc = "Threshold counter exceeded a value of 512.", }, [ POWER8_PME_PM_THRESH_EXC_64 ] = { .pme_name = "PM_THRESH_EXC_64", .pme_code = 0x301e8, .pme_short_desc = "IFU non-branch finished", .pme_long_desc = "Threshold counter exceeded a value of 64.", }, [ POWER8_PME_PM_THRESH_MET ] = { .pme_name = "PM_THRESH_MET", .pme_code = 0x101ec, .pme_short_desc = "threshold exceeded", .pme_long_desc = "threshold exceeded.", }, [ POWER8_PME_PM_THRESH_NOT_MET ] = { .pme_name = "PM_THRESH_NOT_MET", .pme_code = 0x4016e, .pme_short_desc = "Threshold counter did not meet threshold", .pme_long_desc = "Threshold counter did not meet threshold.", }, [ POWER8_PME_PM_TLBIE_FIN ] = { .pme_name = "PM_TLBIE_FIN", .pme_code = 0x30058, .pme_short_desc = "tlbie finished", .pme_long_desc = "tlbie finished.", }, [ POWER8_PME_PM_TLB_MISS ] = { .pme_name = "PM_TLB_MISS", .pme_code = 0x20066, .pme_short_desc = "TLB Miss (I + D)", .pme_long_desc = "TLB Miss (I + D).", }, [ POWER8_PME_PM_TM_BEGIN_ALL ] = { .pme_name = "PM_TM_BEGIN_ALL", .pme_code = 0x20b8, .pme_short_desc = "Tm any tbegin", .pme_long_desc = "Tm any tbegin", }, [ POWER8_PME_PM_TM_CAM_OVERFLOW ] = { .pme_name = "PM_TM_CAM_OVERFLOW", .pme_code = 0x318082, .pme_short_desc = "l3 tm cam overflow during L2 co of SC", .pme_long_desc = "l3 tm cam overflow during L2 co of SC", }, [ POWER8_PME_PM_TM_CAP_OVERFLOW ] = { .pme_name = "PM_TM_CAP_OVERFLOW", .pme_code = 0x74708c, .pme_short_desc = "TM Footprint Capactiy Overflow", .pme_long_desc = "TM Footprint Capactiy Overflow", }, [ POWER8_PME_PM_TM_END_ALL ] = { .pme_name = "PM_TM_END_ALL", .pme_code = 0x20ba, .pme_short_desc = "Tm any tend", .pme_long_desc = "Tm any tend", }, [ POWER8_PME_PM_TM_FAIL_CONF_NON_TM ] = { .pme_name = "PM_TM_FAIL_CONF_NON_TM", .pme_code = 0x3086, .pme_short_desc = "TEXAS fail reason @ completion", .pme_long_desc = "TEXAS fail reason @ completion", }, [ POWER8_PME_PM_TM_FAIL_CON_TM ] = { .pme_name = "PM_TM_FAIL_CON_TM", .pme_code = 0x3088, .pme_short_desc = "TEXAS fail reason @ completion", .pme_long_desc = "TEXAS fail reason @ completion", }, [ POWER8_PME_PM_TM_FAIL_DISALLOW ] = { .pme_name = "PM_TM_FAIL_DISALLOW", .pme_code = 0xe0b2, .pme_short_desc = "TM fail disallow", .pme_long_desc = "TM fail disallow42", }, [ POWER8_PME_PM_TM_FAIL_FOOTPRINT_OVERFLOW ] = { .pme_name = "PM_TM_FAIL_FOOTPRINT_OVERFLOW", .pme_code = 0x3084, .pme_short_desc = "TEXAS fail reason @ completion", .pme_long_desc = "TEXAS fail reason @ completion", }, [ POWER8_PME_PM_TM_FAIL_NON_TX_CONFLICT ] = { .pme_name = "PM_TM_FAIL_NON_TX_CONFLICT", .pme_code = 0xe0b8, .pme_short_desc = "Non transactional conflict from LSU whtver gets repoted to texas", .pme_long_desc = "Non transactional conflict from LSU whtver gets repoted to texas42", }, [ POWER8_PME_PM_TM_FAIL_SELF ] = { .pme_name = "PM_TM_FAIL_SELF", .pme_code = 0x308a, .pme_short_desc = "TEXAS fail reason @ completion", .pme_long_desc = "TEXAS fail reason @ completion", }, [ POWER8_PME_PM_TM_FAIL_TLBIE ] = { .pme_name = "PM_TM_FAIL_TLBIE", .pme_code = 0xe0b4, .pme_short_desc = "TLBIE hit bloom filter", .pme_long_desc = "TLBIE hit bloom filter42", }, [ POWER8_PME_PM_TM_FAIL_TX_CONFLICT ] = { .pme_name = "PM_TM_FAIL_TX_CONFLICT", .pme_code = 0xe0b6, .pme_short_desc = "Transactional conflict from LSU, whatever gets reported to texas", .pme_long_desc = "Transactional conflict from LSU, whatever gets reported to texas 42", }, [ POWER8_PME_PM_TM_FAV_CAUSED_FAIL ] = { .pme_name = "PM_TM_FAV_CAUSED_FAIL", .pme_code = 0x727086, .pme_short_desc = "TM Load (fav) caused another thread to fail", .pme_long_desc = "TM Load (fav) caused another thread to fail", }, [ POWER8_PME_PM_TM_LD_CAUSED_FAIL ] = { .pme_name = "PM_TM_LD_CAUSED_FAIL", .pme_code = 0x717082, .pme_short_desc = "Non TM Ld caused any thread to fail", .pme_long_desc = "Non TM Ld caused any thread to fail", }, [ POWER8_PME_PM_TM_LD_CONF ] = { .pme_name = "PM_TM_LD_CONF", .pme_code = 0x727084, .pme_short_desc = "TM Load (fav or non-fav) ran into conflict (failed)", .pme_long_desc = "TM Load (fav or non-fav) ran into conflict (failed)", }, [ POWER8_PME_PM_TM_RST_SC ] = { .pme_name = "PM_TM_RST_SC", .pme_code = 0x328086, .pme_short_desc = "tm snp rst tm sc", .pme_long_desc = "tm snp rst tm sc", }, [ POWER8_PME_PM_TM_SC_CO ] = { .pme_name = "PM_TM_SC_CO", .pme_code = 0x318080, .pme_short_desc = "l3 castout tm Sc line", .pme_long_desc = "l3 castout tm Sc line", }, [ POWER8_PME_PM_TM_ST_CAUSED_FAIL ] = { .pme_name = "PM_TM_ST_CAUSED_FAIL", .pme_code = 0x73708a, .pme_short_desc = "TM Store (fav or non-fav) caused another thread to fail", .pme_long_desc = "TM Store (fav or non-fav) caused another thread to fail", }, [ POWER8_PME_PM_TM_ST_CONF ] = { .pme_name = "PM_TM_ST_CONF", .pme_code = 0x737088, .pme_short_desc = "TM Store (fav or non-fav) ran into conflict (failed)", .pme_long_desc = "TM Store (fav or non-fav) ran into conflict (failed)", }, [ POWER8_PME_PM_TM_TBEGIN ] = { .pme_name = "PM_TM_TBEGIN", .pme_code = 0x20bc, .pme_short_desc = "Tm nested tbegin", .pme_long_desc = "Tm nested tbegin", }, [ POWER8_PME_PM_TM_TRANS_RUN_CYC ] = { .pme_name = "PM_TM_TRANS_RUN_CYC", .pme_code = 0x10060, .pme_short_desc = "run cycles in transactional state", .pme_long_desc = "run cycles in transactional state.", }, [ POWER8_PME_PM_TM_TRANS_RUN_INST ] = { .pme_name = "PM_TM_TRANS_RUN_INST", .pme_code = 0x30060, .pme_short_desc = "Instructions completed in transactional state", .pme_long_desc = "Instructions completed in transactional state.", }, [ POWER8_PME_PM_TM_TRESUME ] = { .pme_name = "PM_TM_TRESUME", .pme_code = 0x3080, .pme_short_desc = "Tm resume", .pme_long_desc = "Tm resume", }, [ POWER8_PME_PM_TM_TSUSPEND ] = { .pme_name = "PM_TM_TSUSPEND", .pme_code = 0x20be, .pme_short_desc = "Tm suspend", .pme_long_desc = "Tm suspend", }, [ POWER8_PME_PM_TM_TX_PASS_RUN_CYC ] = { .pme_name = "PM_TM_TX_PASS_RUN_CYC", .pme_code = 0x2e012, .pme_short_desc = "cycles spent in successful transactions", .pme_long_desc = "run cycles spent in successful transactions.", }, [ POWER8_PME_PM_TM_TX_PASS_RUN_INST ] = { .pme_name = "PM_TM_TX_PASS_RUN_INST", .pme_code = 0x4e014, .pme_short_desc = "run instructions spent in successful transactions.", .pme_long_desc = "run instructions spent in successful transactions.", }, [ POWER8_PME_PM_UP_PREF_L3 ] = { .pme_name = "PM_UP_PREF_L3", .pme_code = 0xe08c, .pme_short_desc = "Micropartition prefetch", .pme_long_desc = "Micropartition prefetch42", }, [ POWER8_PME_PM_UP_PREF_POINTER ] = { .pme_name = "PM_UP_PREF_POINTER", .pme_code = 0xe08e, .pme_short_desc = "Micrpartition pointer prefetches", .pme_long_desc = "Micrpartition pointer prefetches42", }, [ POWER8_PME_PM_VSU0_16FLOP ] = { .pme_name = "PM_VSU0_16FLOP", .pme_code = 0xa0a4, .pme_short_desc = "Sixteen flops operation (SP vector versions of fdiv,fsqrt)", .pme_long_desc = "Sixteen flops operation (SP vector versions of fdiv,fsqrt)", }, [ POWER8_PME_PM_VSU0_1FLOP ] = { .pme_name = "PM_VSU0_1FLOP", .pme_code = 0xa080, .pme_short_desc = "one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finished", .pme_long_desc = "one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finishedDecode into 1,2,4 FLOP according to instr IOP, multiplied by #vector elements according to route( eg x1, x2, x4) Only if instr sends finish to ISU", }, [ POWER8_PME_PM_VSU0_2FLOP ] = { .pme_name = "PM_VSU0_2FLOP", .pme_code = 0xa098, .pme_short_desc = "two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions)", .pme_long_desc = "two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions)", }, [ POWER8_PME_PM_VSU0_4FLOP ] = { .pme_name = "PM_VSU0_4FLOP", .pme_code = 0xa09c, .pme_short_desc = "four flops operation (scalar fdiv, fsqrt, DP vector version of fmadd, fnmadd, fmsub, fnmsub, SP vector versions of single flop instructions)", .pme_long_desc = "four flops operation (scalar fdiv, fsqrt, DP vector version of fmadd, fnmadd, fmsub, fnmsub, SP vector versions of single flop instructions)", }, [ POWER8_PME_PM_VSU0_8FLOP ] = { .pme_name = "PM_VSU0_8FLOP", .pme_code = 0xa0a0, .pme_short_desc = "eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub)", .pme_long_desc = "eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub)", }, [ POWER8_PME_PM_VSU0_COMPLEX_ISSUED ] = { .pme_name = "PM_VSU0_COMPLEX_ISSUED", .pme_code = 0xb0a4, .pme_short_desc = "Complex VMX instruction issued", .pme_long_desc = "Complex VMX instruction issued", }, [ POWER8_PME_PM_VSU0_CY_ISSUED ] = { .pme_name = "PM_VSU0_CY_ISSUED", .pme_code = 0xb0b4, .pme_short_desc = "Cryptographic instruction RFC02196 Issued", .pme_long_desc = "Cryptographic instruction RFC02196 Issued", }, [ POWER8_PME_PM_VSU0_DD_ISSUED ] = { .pme_name = "PM_VSU0_DD_ISSUED", .pme_code = 0xb0a8, .pme_short_desc = "64BIT Decimal Issued", .pme_long_desc = "64BIT Decimal Issued", }, [ POWER8_PME_PM_VSU0_DP_2FLOP ] = { .pme_name = "PM_VSU0_DP_2FLOP", .pme_code = 0xa08c, .pme_short_desc = "DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg", .pme_long_desc = "DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg", }, [ POWER8_PME_PM_VSU0_DP_FMA ] = { .pme_name = "PM_VSU0_DP_FMA", .pme_code = 0xa090, .pme_short_desc = "DP vector version of fmadd,fnmadd,fmsub,fnmsub", .pme_long_desc = "DP vector version of fmadd,fnmadd,fmsub,fnmsub", }, [ POWER8_PME_PM_VSU0_DP_FSQRT_FDIV ] = { .pme_name = "PM_VSU0_DP_FSQRT_FDIV", .pme_code = 0xa094, .pme_short_desc = "DP vector versions of fdiv,fsqrt", .pme_long_desc = "DP vector versions of fdiv,fsqrt", }, [ POWER8_PME_PM_VSU0_DQ_ISSUED ] = { .pme_name = "PM_VSU0_DQ_ISSUED", .pme_code = 0xb0ac, .pme_short_desc = "128BIT Decimal Issued", .pme_long_desc = "128BIT Decimal Issued", }, [ POWER8_PME_PM_VSU0_EX_ISSUED ] = { .pme_name = "PM_VSU0_EX_ISSUED", .pme_code = 0xb0b0, .pme_short_desc = "Direct move 32/64b VRFtoGPR RFC02206 Issued", .pme_long_desc = "Direct move 32/64b VRFtoGPR RFC02206 Issued", }, [ POWER8_PME_PM_VSU0_FIN ] = { .pme_name = "PM_VSU0_FIN", .pme_code = 0xa0bc, .pme_short_desc = "VSU0 Finished an instruction", .pme_long_desc = "VSU0 Finished an instruction", }, [ POWER8_PME_PM_VSU0_FMA ] = { .pme_name = "PM_VSU0_FMA", .pme_code = 0xa084, .pme_short_desc = "two flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only!", .pme_long_desc = "two flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only!", }, [ POWER8_PME_PM_VSU0_FPSCR ] = { .pme_name = "PM_VSU0_FPSCR", .pme_code = 0xb098, .pme_short_desc = "Move to/from FPSCR type instruction issued on Pipe 0", .pme_long_desc = "Move to/from FPSCR type instruction issued on Pipe 0", }, [ POWER8_PME_PM_VSU0_FSQRT_FDIV ] = { .pme_name = "PM_VSU0_FSQRT_FDIV", .pme_code = 0xa088, .pme_short_desc = "four flops operation (fdiv,fsqrt) Scalar Instructions only!", .pme_long_desc = "four flops operation (fdiv,fsqrt) Scalar Instructions only!", }, [ POWER8_PME_PM_VSU0_PERMUTE_ISSUED ] = { .pme_name = "PM_VSU0_PERMUTE_ISSUED", .pme_code = 0xb090, .pme_short_desc = "Permute VMX Instruction Issued", .pme_long_desc = "Permute VMX Instruction Issued", }, [ POWER8_PME_PM_VSU0_SCALAR_DP_ISSUED ] = { .pme_name = "PM_VSU0_SCALAR_DP_ISSUED", .pme_code = 0xb088, .pme_short_desc = "Double Precision scalar instruction issued on Pipe0", .pme_long_desc = "Double Precision scalar instruction issued on Pipe0", }, [ POWER8_PME_PM_VSU0_SIMPLE_ISSUED ] = { .pme_name = "PM_VSU0_SIMPLE_ISSUED", .pme_code = 0xb094, .pme_short_desc = "Simple VMX instruction issued", .pme_long_desc = "Simple VMX instruction issued", }, [ POWER8_PME_PM_VSU0_SINGLE ] = { .pme_name = "PM_VSU0_SINGLE", .pme_code = 0xa0a8, .pme_short_desc = "FPU single precision", .pme_long_desc = "FPU single precision", }, [ POWER8_PME_PM_VSU0_SQ ] = { .pme_name = "PM_VSU0_SQ", .pme_code = 0xb09c, .pme_short_desc = "Store Vector Issued", .pme_long_desc = "Store Vector Issued", }, [ POWER8_PME_PM_VSU0_STF ] = { .pme_name = "PM_VSU0_STF", .pme_code = 0xb08c, .pme_short_desc = "FPU store (SP or DP) issued on Pipe0", .pme_long_desc = "FPU store (SP or DP) issued on Pipe0", }, [ POWER8_PME_PM_VSU0_VECTOR_DP_ISSUED ] = { .pme_name = "PM_VSU0_VECTOR_DP_ISSUED", .pme_code = 0xb080, .pme_short_desc = "Double Precision vector instruction issued on Pipe0", .pme_long_desc = "Double Precision vector instruction issued on Pipe0", }, [ POWER8_PME_PM_VSU0_VECTOR_SP_ISSUED ] = { .pme_name = "PM_VSU0_VECTOR_SP_ISSUED", .pme_code = 0xb084, .pme_short_desc = "Single Precision vector instruction issued (executed)", .pme_long_desc = "Single Precision vector instruction issued (executed)", }, [ POWER8_PME_PM_VSU1_16FLOP ] = { .pme_name = "PM_VSU1_16FLOP", .pme_code = 0xa0a6, .pme_short_desc = "Sixteen flops operation (SP vector versions of fdiv,fsqrt)", .pme_long_desc = "Sixteen flops operation (SP vector versions of fdiv,fsqrt)", }, [ POWER8_PME_PM_VSU1_1FLOP ] = { .pme_name = "PM_VSU1_1FLOP", .pme_code = 0xa082, .pme_short_desc = "one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finished", .pme_long_desc = "one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finished", }, [ POWER8_PME_PM_VSU1_2FLOP ] = { .pme_name = "PM_VSU1_2FLOP", .pme_code = 0xa09a, .pme_short_desc = "two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions)", .pme_long_desc = "two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions)", }, [ POWER8_PME_PM_VSU1_4FLOP ] = { .pme_name = "PM_VSU1_4FLOP", .pme_code = 0xa09e, .pme_short_desc = "four flops operation (scalar fdiv, fsqrt, DP vector version of fmadd, fnmadd, fmsub, fnmsub, SP vector versions of single flop instructions)", .pme_long_desc = "four flops operation (scalar fdiv, fsqrt, DP vector version of fmadd, fnmadd, fmsub, fnmsub, SP vector versions of single flop instructions)", }, [ POWER8_PME_PM_VSU1_8FLOP ] = { .pme_name = "PM_VSU1_8FLOP", .pme_code = 0xa0a2, .pme_short_desc = "eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub)", .pme_long_desc = "eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub)", }, [ POWER8_PME_PM_VSU1_COMPLEX_ISSUED ] = { .pme_name = "PM_VSU1_COMPLEX_ISSUED", .pme_code = 0xb0a6, .pme_short_desc = "Complex VMX instruction issued", .pme_long_desc = "Complex VMX instruction issued", }, [ POWER8_PME_PM_VSU1_CY_ISSUED ] = { .pme_name = "PM_VSU1_CY_ISSUED", .pme_code = 0xb0b6, .pme_short_desc = "Cryptographic instruction RFC02196 Issued", .pme_long_desc = "Cryptographic instruction RFC02196 Issued", }, [ POWER8_PME_PM_VSU1_DD_ISSUED ] = { .pme_name = "PM_VSU1_DD_ISSUED", .pme_code = 0xb0aa, .pme_short_desc = "64BIT Decimal Issued", .pme_long_desc = "64BIT Decimal Issued", }, [ POWER8_PME_PM_VSU1_DP_2FLOP ] = { .pme_name = "PM_VSU1_DP_2FLOP", .pme_code = 0xa08e, .pme_short_desc = "DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg", .pme_long_desc = "DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg", }, [ POWER8_PME_PM_VSU1_DP_FMA ] = { .pme_name = "PM_VSU1_DP_FMA", .pme_code = 0xa092, .pme_short_desc = "DP vector version of fmadd,fnmadd,fmsub,fnmsub", .pme_long_desc = "DP vector version of fmadd,fnmadd,fmsub,fnmsub", }, [ POWER8_PME_PM_VSU1_DP_FSQRT_FDIV ] = { .pme_name = "PM_VSU1_DP_FSQRT_FDIV", .pme_code = 0xa096, .pme_short_desc = "DP vector versions of fdiv,fsqrt", .pme_long_desc = "DP vector versions of fdiv,fsqrt", }, [ POWER8_PME_PM_VSU1_DQ_ISSUED ] = { .pme_name = "PM_VSU1_DQ_ISSUED", .pme_code = 0xb0ae, .pme_short_desc = "128BIT Decimal Issued", .pme_long_desc = "128BIT Decimal Issued", }, [ POWER8_PME_PM_VSU1_EX_ISSUED ] = { .pme_name = "PM_VSU1_EX_ISSUED", .pme_code = 0xb0b2, .pme_short_desc = "Direct move 32/64b VRFtoGPR RFC02206 Issued", .pme_long_desc = "Direct move 32/64b VRFtoGPR RFC02206 Issued", }, [ POWER8_PME_PM_VSU1_FIN ] = { .pme_name = "PM_VSU1_FIN", .pme_code = 0xa0be, .pme_short_desc = "VSU1 Finished an instruction", .pme_long_desc = "VSU1 Finished an instruction", }, [ POWER8_PME_PM_VSU1_FMA ] = { .pme_name = "PM_VSU1_FMA", .pme_code = 0xa086, .pme_short_desc = "two flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only!", .pme_long_desc = "two flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only!", }, [ POWER8_PME_PM_VSU1_FPSCR ] = { .pme_name = "PM_VSU1_FPSCR", .pme_code = 0xb09a, .pme_short_desc = "Move to/from FPSCR type instruction issued on Pipe 0", .pme_long_desc = "Move to/from FPSCR type instruction issued on Pipe 0", }, [ POWER8_PME_PM_VSU1_FSQRT_FDIV ] = { .pme_name = "PM_VSU1_FSQRT_FDIV", .pme_code = 0xa08a, .pme_short_desc = "four flops operation (fdiv,fsqrt) Scalar Instructions only!", .pme_long_desc = "four flops operation (fdiv,fsqrt) Scalar Instructions only!", }, [ POWER8_PME_PM_VSU1_PERMUTE_ISSUED ] = { .pme_name = "PM_VSU1_PERMUTE_ISSUED", .pme_code = 0xb092, .pme_short_desc = "Permute VMX Instruction Issued", .pme_long_desc = "Permute VMX Instruction Issued", }, [ POWER8_PME_PM_VSU1_SCALAR_DP_ISSUED ] = { .pme_name = "PM_VSU1_SCALAR_DP_ISSUED", .pme_code = 0xb08a, .pme_short_desc = "Double Precision scalar instruction issued on Pipe1", .pme_long_desc = "Double Precision scalar instruction issued on Pipe1", }, [ POWER8_PME_PM_VSU1_SIMPLE_ISSUED ] = { .pme_name = "PM_VSU1_SIMPLE_ISSUED", .pme_code = 0xb096, .pme_short_desc = "Simple VMX instruction issued", .pme_long_desc = "Simple VMX instruction issued", }, [ POWER8_PME_PM_VSU1_SINGLE ] = { .pme_name = "PM_VSU1_SINGLE", .pme_code = 0xa0aa, .pme_short_desc = "FPU single precision", .pme_long_desc = "FPU single precision", }, [ POWER8_PME_PM_VSU1_SQ ] = { .pme_name = "PM_VSU1_SQ", .pme_code = 0xb09e, .pme_short_desc = "Store Vector Issued", .pme_long_desc = "Store Vector Issued", }, [ POWER8_PME_PM_VSU1_STF ] = { .pme_name = "PM_VSU1_STF", .pme_code = 0xb08e, .pme_short_desc = "FPU store (SP or DP) issued on Pipe1", .pme_long_desc = "FPU store (SP or DP) issued on Pipe1", }, [ POWER8_PME_PM_VSU1_VECTOR_DP_ISSUED ] = { .pme_name = "PM_VSU1_VECTOR_DP_ISSUED", .pme_code = 0xb082, .pme_short_desc = "Double Precision vector instruction issued on Pipe1", .pme_long_desc = "Double Precision vector instruction issued on Pipe1", }, [ POWER8_PME_PM_VSU1_VECTOR_SP_ISSUED ] = { .pme_name = "PM_VSU1_VECTOR_SP_ISSUED", .pme_code = 0xb086, .pme_short_desc = "Single Precision vector instruction issued (executed)", .pme_long_desc = "Single Precision vector instruction issued (executed)", }, }; #endif libpfm-4.9.0/lib/events/itanium2_events.h0000664000175000017500000027467013223402656020175 0ustar eranianeranian/* * Copyright (c) 2002-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. */ /* * This file is generated automatically * !! DO NOT CHANGE !! */ static pme_ita2_entry_t itanium2_pe []={ #define PME_ITA2_ALAT_CAPACITY_MISS_ALL 0 { "ALAT_CAPACITY_MISS_ALL", {0x30058}, 0xf0, 2, {0xf00007}, "ALAT Entry Replaced -- both integer and floating point instructions"}, #define PME_ITA2_ALAT_CAPACITY_MISS_FP 1 { "ALAT_CAPACITY_MISS_FP", {0x20058}, 0xf0, 2, {0xf00007}, "ALAT Entry Replaced -- only floating point instructions"}, #define PME_ITA2_ALAT_CAPACITY_MISS_INT 2 { "ALAT_CAPACITY_MISS_INT", {0x10058}, 0xf0, 2, {0xf00007}, "ALAT Entry Replaced -- only integer instructions"}, #define PME_ITA2_BACK_END_BUBBLE_ALL 3 { "BACK_END_BUBBLE_ALL", {0x0}, 0xf0, 1, {0xf00000}, "Full Pipe Bubbles in Main Pipe -- Front-end, RSE, EXE, FPU/L1D stall or a pipeline flush due to an exception/branch misprediction"}, #define PME_ITA2_BACK_END_BUBBLE_FE 4 { "BACK_END_BUBBLE_FE", {0x10000}, 0xf0, 1, {0xf00000}, "Full Pipe Bubbles in Main Pipe -- front-end"}, #define PME_ITA2_BACK_END_BUBBLE_L1D_FPU_RSE 5 { "BACK_END_BUBBLE_L1D_FPU_RSE", {0x20000}, 0xf0, 1, {0xf00000}, "Full Pipe Bubbles in Main Pipe -- L1D_FPU or RSE."}, #define PME_ITA2_BE_BR_MISPRED_DETAIL_ANY 6 { "BE_BR_MISPRED_DETAIL_ANY", {0x61}, 0xf0, 1, {0xf00003}, "BE Branch Misprediction Detail -- any back-end (be) mispredictions"}, #define PME_ITA2_BE_BR_MISPRED_DETAIL_PFS 7 { "BE_BR_MISPRED_DETAIL_PFS", {0x30061}, 0xf0, 1, {0xf00003}, "BE Branch Misprediction Detail -- only back-end pfs mispredictions for taken branches"}, #define PME_ITA2_BE_BR_MISPRED_DETAIL_ROT 8 { "BE_BR_MISPRED_DETAIL_ROT", {0x20061}, 0xf0, 1, {0xf00003}, "BE Branch Misprediction Detail -- only back-end rotate mispredictions"}, #define PME_ITA2_BE_BR_MISPRED_DETAIL_STG 9 { "BE_BR_MISPRED_DETAIL_STG", {0x10061}, 0xf0, 1, {0xf00003}, "BE Branch Misprediction Detail -- only back-end stage mispredictions"}, #define PME_ITA2_BE_EXE_BUBBLE_ALL 10 { "BE_EXE_BUBBLE_ALL", {0x2}, 0xf0, 1, {0xf00000}, "Full Pipe Bubbles in Main Pipe due to Execution Unit Stalls -- Back-end was stalled by exe"}, #define PME_ITA2_BE_EXE_BUBBLE_ARCR 11 { "BE_EXE_BUBBLE_ARCR", {0x40002}, 0xf0, 1, {0xf00000}, "Full Pipe Bubbles in Main Pipe due to Execution Unit Stalls -- Back-end was stalled by exe due to AR or CR dependency"}, #define PME_ITA2_BE_EXE_BUBBLE_ARCR_PR_CANCEL_BANK 12 { "BE_EXE_BUBBLE_ARCR_PR_CANCEL_BANK", {0x80002}, 0xf0, 1, {0xf00000}, "Full Pipe Bubbles in Main Pipe due to Execution Unit Stalls -- ARCR, PR, CANCEL or BANK_SWITCH"}, #define PME_ITA2_BE_EXE_BUBBLE_BANK_SWITCH 13 { "BE_EXE_BUBBLE_BANK_SWITCH", {0x70002}, 0xf0, 1, {0xf00000}, "Full Pipe Bubbles in Main Pipe due to Execution Unit Stalls -- Back-end was stalled by exe due to bank switching."}, #define PME_ITA2_BE_EXE_BUBBLE_CANCEL 14 { "BE_EXE_BUBBLE_CANCEL", {0x60002}, 0xf0, 1, {0xf00000}, "Full Pipe Bubbles in Main Pipe due to Execution Unit Stalls -- Back-end was stalled by exe due to a canceled load"}, #define PME_ITA2_BE_EXE_BUBBLE_FRALL 15 { "BE_EXE_BUBBLE_FRALL", {0x20002}, 0xf0, 1, {0xf00000}, "Full Pipe Bubbles in Main Pipe due to Execution Unit Stalls -- Back-end was stalled by exe due to FR/FR or FR/load dependency"}, #define PME_ITA2_BE_EXE_BUBBLE_GRALL 16 { "BE_EXE_BUBBLE_GRALL", {0x10002}, 0xf0, 1, {0xf00000}, "Full Pipe Bubbles in Main Pipe due to Execution Unit Stalls -- Back-end was stalled by exe due to GR/GR or GR/load dependency"}, #define PME_ITA2_BE_EXE_BUBBLE_GRGR 17 { "BE_EXE_BUBBLE_GRGR", {0x50002}, 0xf0, 1, {0xf00000}, "Full Pipe Bubbles in Main Pipe due to Execution Unit Stalls -- Back-end was stalled by exe due to GR/GR dependency"}, #define PME_ITA2_BE_EXE_BUBBLE_PR 18 { "BE_EXE_BUBBLE_PR", {0x30002}, 0xf0, 1, {0xf00000}, "Full Pipe Bubbles in Main Pipe due to Execution Unit Stalls -- Back-end was stalled by exe due to PR dependency"}, #define PME_ITA2_BE_FLUSH_BUBBLE_ALL 19 { "BE_FLUSH_BUBBLE_ALL", {0x4}, 0xf0, 1, {0xf00000}, "Full Pipe Bubbles in Main Pipe due to Flushes. -- Back-end was stalled due to either an exception/interruption or branch misprediction flush"}, #define PME_ITA2_BE_FLUSH_BUBBLE_BRU 20 { "BE_FLUSH_BUBBLE_BRU", {0x10004}, 0xf0, 1, {0xf00000}, "Full Pipe Bubbles in Main Pipe due to Flushes. -- Back-end was stalled due to a branch misprediction flush"}, #define PME_ITA2_BE_FLUSH_BUBBLE_XPN 21 { "BE_FLUSH_BUBBLE_XPN", {0x20004}, 0xf0, 1, {0xf00000}, "Full Pipe Bubbles in Main Pipe due to Flushes. -- Back-end was stalled due to an exception/interruption flush"}, #define PME_ITA2_BE_L1D_FPU_BUBBLE_ALL 22 { "BE_L1D_FPU_BUBBLE_ALL", {0xca}, 0xf0, 1, {0x5210000}, "Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D or FPU"}, #define PME_ITA2_BE_L1D_FPU_BUBBLE_FPU 23 { "BE_L1D_FPU_BUBBLE_FPU", {0x100ca}, 0xf0, 1, {0x5210000}, "Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by FPU."}, #define PME_ITA2_BE_L1D_FPU_BUBBLE_L1D 24 { "BE_L1D_FPU_BUBBLE_L1D", {0x200ca}, 0xf0, 1, {0x5210000}, "Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D. This includes all stalls caused by the L1 pipeline (created in the L1D stage of the L1 pipeline which corresponds to the DET stage of the main pipe)."}, #define PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_DCS 25 { "BE_L1D_FPU_BUBBLE_L1D_DCS", {0x800ca}, 0xf0, 1, {0x5210000}, "Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to DCS requiring a stall"}, #define PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_DCURECIR 26 { "BE_L1D_FPU_BUBBLE_L1D_DCURECIR", {0x400ca}, 0xf0, 1, {0x5210000}, "Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to DCU recirculating"}, #define PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_FILLCONF 27 { "BE_L1D_FPU_BUBBLE_L1D_FILLCONF", {0x700ca}, 0xf0, 1, {0x5210000}, "Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due a store in conflict with a returning fill."}, #define PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_FULLSTBUF 28 { "BE_L1D_FPU_BUBBLE_L1D_FULLSTBUF", {0x300ca}, 0xf0, 1, {0x5210000}, "Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to store buffer being full"}, #define PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_HPW 29 { "BE_L1D_FPU_BUBBLE_L1D_HPW", {0x500ca}, 0xf0, 1, {0x5210000}, "Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to Hardware Page Walker"}, #define PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_L2BPRESS 30 { "BE_L1D_FPU_BUBBLE_L1D_L2BPRESS", {0x900ca}, 0xf0, 1, {0x5210000}, "Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to L2 Back Pressure"}, #define PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_LDCHK 31 { "BE_L1D_FPU_BUBBLE_L1D_LDCHK", {0xc00ca}, 0xf0, 1, {0x5210000}, "Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to architectural ordering conflict"}, #define PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_LDCONF 32 { "BE_L1D_FPU_BUBBLE_L1D_LDCONF", {0xb00ca}, 0xf0, 1, {0x5210000}, "Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to architectural ordering conflict"}, #define PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_NAT 33 { "BE_L1D_FPU_BUBBLE_L1D_NAT", {0xd00ca}, 0xf0, 1, {0x5210000}, "Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to L1D data return needing recirculated NaT generation."}, #define PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_NATCONF 34 { "BE_L1D_FPU_BUBBLE_L1D_NATCONF", {0xf00ca}, 0xf0, 1, {0x5210000}, "Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to ld8.fill conflict with st8.spill not written to unat."}, #define PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_STBUFRECIR 35 { "BE_L1D_FPU_BUBBLE_L1D_STBUFRECIR", {0xe00ca}, 0xf0, 1, {0x5210000}, "Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to store buffer cancel needing recirculate."}, #define PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_TLB 36 { "BE_L1D_FPU_BUBBLE_L1D_TLB", {0xa00ca}, 0xf0, 1, {0x5210000}, "Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to L2DTLB to L1DTLB transfer"}, #define PME_ITA2_BE_LOST_BW_DUE_TO_FE_ALL 37 { "BE_LOST_BW_DUE_TO_FE_ALL", {0x72}, 0xf0, 2, {0xf00000}, "Invalid Bundles if BE Not Stalled for Other Reasons. -- count regardless of cause"}, #define PME_ITA2_BE_LOST_BW_DUE_TO_FE_BI 38 { "BE_LOST_BW_DUE_TO_FE_BI", {0x90072}, 0xf0, 2, {0xf00000}, "Invalid Bundles if BE Not Stalled for Other Reasons. -- only if caused by branch initialization stall"}, #define PME_ITA2_BE_LOST_BW_DUE_TO_FE_BRQ 39 { "BE_LOST_BW_DUE_TO_FE_BRQ", {0xa0072}, 0xf0, 2, {0xf00000}, "Invalid Bundles if BE Not Stalled for Other Reasons. -- only if caused by branch retirement queue stall"}, #define PME_ITA2_BE_LOST_BW_DUE_TO_FE_BR_ILOCK 40 { "BE_LOST_BW_DUE_TO_FE_BR_ILOCK", {0xc0072}, 0xf0, 2, {0xf00000}, "Invalid Bundles if BE Not Stalled for Other Reasons. -- only if caused by branch interlock stall"}, #define PME_ITA2_BE_LOST_BW_DUE_TO_FE_BUBBLE 41 { "BE_LOST_BW_DUE_TO_FE_BUBBLE", {0xd0072}, 0xf0, 2, {0xf00000}, "Invalid Bundles if BE Not Stalled for Other Reasons. -- only if caused by branch resteer bubble stall"}, #define PME_ITA2_BE_LOST_BW_DUE_TO_FE_FEFLUSH 42 { "BE_LOST_BW_DUE_TO_FE_FEFLUSH", {0x10072}, 0xf0, 2, {0xf00000}, "Invalid Bundles if BE Not Stalled for Other Reasons. -- only if caused by a front-end flush"}, #define PME_ITA2_BE_LOST_BW_DUE_TO_FE_FILL_RECIRC 43 { "BE_LOST_BW_DUE_TO_FE_FILL_RECIRC", {0x80072}, 0xf0, 2, {0xf00000}, "Invalid Bundles if BE Not Stalled for Other Reasons. -- only if caused by a recirculate for a cache line fill operation"}, #define PME_ITA2_BE_LOST_BW_DUE_TO_FE_IBFULL 44 { "BE_LOST_BW_DUE_TO_FE_IBFULL", {0x50072}, 0xf0, 2, {0xf00000}, "Invalid Bundles if BE Not Stalled for Other Reasons. -- (* meaningless for this event *)"}, #define PME_ITA2_BE_LOST_BW_DUE_TO_FE_IMISS 45 { "BE_LOST_BW_DUE_TO_FE_IMISS", {0x60072}, 0xf0, 2, {0xf00000}, "Invalid Bundles if BE Not Stalled for Other Reasons. -- only if caused by instruction cache miss stall"}, #define PME_ITA2_BE_LOST_BW_DUE_TO_FE_PLP 46 { "BE_LOST_BW_DUE_TO_FE_PLP", {0xb0072}, 0xf0, 2, {0xf00000}, "Invalid Bundles if BE Not Stalled for Other Reasons. -- only if caused by perfect loop prediction stall"}, #define PME_ITA2_BE_LOST_BW_DUE_TO_FE_TLBMISS 47 { "BE_LOST_BW_DUE_TO_FE_TLBMISS", {0x70072}, 0xf0, 2, {0xf00000}, "Invalid Bundles if BE Not Stalled for Other Reasons. -- only if caused by TLB stall"}, #define PME_ITA2_BE_LOST_BW_DUE_TO_FE_UNREACHED 48 { "BE_LOST_BW_DUE_TO_FE_UNREACHED", {0x40072}, 0xf0, 2, {0xf00000}, "Invalid Bundles if BE Not Stalled for Other Reasons. -- only if caused by unreachable bundle"}, #define PME_ITA2_BE_RSE_BUBBLE_ALL 49 { "BE_RSE_BUBBLE_ALL", {0x1}, 0xf0, 1, {0xf00000}, "Full Pipe Bubbles in Main Pipe due to RSE Stalls -- Back-end was stalled by RSE"}, #define PME_ITA2_BE_RSE_BUBBLE_AR_DEP 50 { "BE_RSE_BUBBLE_AR_DEP", {0x20001}, 0xf0, 1, {0xf00000}, "Full Pipe Bubbles in Main Pipe due to RSE Stalls -- Back-end was stalled by RSE due to AR dependencies"}, #define PME_ITA2_BE_RSE_BUBBLE_BANK_SWITCH 51 { "BE_RSE_BUBBLE_BANK_SWITCH", {0x10001}, 0xf0, 1, {0xf00000}, "Full Pipe Bubbles in Main Pipe due to RSE Stalls -- Back-end was stalled by RSE due to bank switching"}, #define PME_ITA2_BE_RSE_BUBBLE_LOADRS 52 { "BE_RSE_BUBBLE_LOADRS", {0x50001}, 0xf0, 1, {0xf00000}, "Full Pipe Bubbles in Main Pipe due to RSE Stalls -- Back-end was stalled by RSE due to loadrs calculations"}, #define PME_ITA2_BE_RSE_BUBBLE_OVERFLOW 53 { "BE_RSE_BUBBLE_OVERFLOW", {0x30001}, 0xf0, 1, {0xf00000}, "Full Pipe Bubbles in Main Pipe due to RSE Stalls -- Back-end was stalled by RSE due to need to spill"}, #define PME_ITA2_BE_RSE_BUBBLE_UNDERFLOW 54 { "BE_RSE_BUBBLE_UNDERFLOW", {0x40001}, 0xf0, 1, {0xf00000}, "Full Pipe Bubbles in Main Pipe due to RSE Stalls -- Back-end was stalled by RSE due to need to fill"}, #define PME_ITA2_BRANCH_EVENT 55 { "BRANCH_EVENT", {0x111}, 0xf0, 1, {0xf00003}, "Branch Event Captured"}, #define PME_ITA2_BR_MISPRED_DETAIL_ALL_ALL_PRED 56 { "BR_MISPRED_DETAIL_ALL_ALL_PRED", {0x5b}, 0xf0, 3, {0xf00003}, "FE Branch Mispredict Detail -- All branch types regardless of prediction result"}, #define PME_ITA2_BR_MISPRED_DETAIL_ALL_CORRECT_PRED 57 { "BR_MISPRED_DETAIL_ALL_CORRECT_PRED", {0x1005b}, 0xf0, 3, {0xf00003}, "FE Branch Mispredict Detail -- All branch types, correctly predicted branches (outcome and target)"}, #define PME_ITA2_BR_MISPRED_DETAIL_ALL_WRONG_PATH 58 { "BR_MISPRED_DETAIL_ALL_WRONG_PATH", {0x2005b}, 0xf0, 3, {0xf00003}, "FE Branch Mispredict Detail -- All branch types, mispredicted branches due to wrong branch direction"}, #define PME_ITA2_BR_MISPRED_DETAIL_ALL_WRONG_TARGET 59 { "BR_MISPRED_DETAIL_ALL_WRONG_TARGET", {0x3005b}, 0xf0, 3, {0xf00003}, "FE Branch Mispredict Detail -- All branch types, mispredicted branches due to wrong target for taken branches"}, #define PME_ITA2_BR_MISPRED_DETAIL_IPREL_ALL_PRED 60 { "BR_MISPRED_DETAIL_IPREL_ALL_PRED", {0x4005b}, 0xf0, 3, {0xf00003}, "FE Branch Mispredict Detail -- Only IP relative branches, regardless of prediction result"}, #define PME_ITA2_BR_MISPRED_DETAIL_IPREL_CORRECT_PRED 61 { "BR_MISPRED_DETAIL_IPREL_CORRECT_PRED", {0x5005b}, 0xf0, 3, {0xf00003}, "FE Branch Mispredict Detail -- Only IP relative branches, correctly predicted branches (outcome and target)"}, #define PME_ITA2_BR_MISPRED_DETAIL_IPREL_WRONG_PATH 62 { "BR_MISPRED_DETAIL_IPREL_WRONG_PATH", {0x6005b}, 0xf0, 3, {0xf00003}, "FE Branch Mispredict Detail -- Only IP relative branches, mispredicted branches due to wrong branch direction"}, #define PME_ITA2_BR_MISPRED_DETAIL_IPREL_WRONG_TARGET 63 { "BR_MISPRED_DETAIL_IPREL_WRONG_TARGET", {0x7005b}, 0xf0, 3, {0xf00003}, "FE Branch Mispredict Detail -- Only IP relative branches, mispredicted branches due to wrong target for taken branches"}, #define PME_ITA2_BR_MISPRED_DETAIL_NTRETIND_ALL_PRED 64 { "BR_MISPRED_DETAIL_NTRETIND_ALL_PRED", {0xc005b}, 0xf0, 3, {0xf00003}, "FE Branch Mispredict Detail -- Only non-return indirect branches, regardless of prediction result"}, #define PME_ITA2_BR_MISPRED_DETAIL_NTRETIND_CORRECT_PRED 65 { "BR_MISPRED_DETAIL_NTRETIND_CORRECT_PRED", {0xd005b}, 0xf0, 3, {0xf00003}, "FE Branch Mispredict Detail -- Only non-return indirect branches, correctly predicted branches (outcome and target)"}, #define PME_ITA2_BR_MISPRED_DETAIL_NTRETIND_WRONG_PATH 66 { "BR_MISPRED_DETAIL_NTRETIND_WRONG_PATH", {0xe005b}, 0xf0, 3, {0xf00003}, "FE Branch Mispredict Detail -- Only non-return indirect branches, mispredicted branches due to wrong branch direction"}, #define PME_ITA2_BR_MISPRED_DETAIL_NTRETIND_WRONG_TARGET 67 { "BR_MISPRED_DETAIL_NTRETIND_WRONG_TARGET", {0xf005b}, 0xf0, 3, {0xf00003}, "FE Branch Mispredict Detail -- Only non-return indirect branches, mispredicted branches due to wrong target for taken branches"}, #define PME_ITA2_BR_MISPRED_DETAIL_RETURN_ALL_PRED 68 { "BR_MISPRED_DETAIL_RETURN_ALL_PRED", {0x8005b}, 0xf0, 3, {0xf00003}, "FE Branch Mispredict Detail -- Only return type branches, regardless of prediction result"}, #define PME_ITA2_BR_MISPRED_DETAIL_RETURN_CORRECT_PRED 69 { "BR_MISPRED_DETAIL_RETURN_CORRECT_PRED", {0x9005b}, 0xf0, 3, {0xf00003}, "FE Branch Mispredict Detail -- Only return type branches, correctly predicted branches (outcome and target)"}, #define PME_ITA2_BR_MISPRED_DETAIL_RETURN_WRONG_PATH 70 { "BR_MISPRED_DETAIL_RETURN_WRONG_PATH", {0xa005b}, 0xf0, 3, {0xf00003}, "FE Branch Mispredict Detail -- Only return type branches, mispredicted branches due to wrong branch direction"}, #define PME_ITA2_BR_MISPRED_DETAIL_RETURN_WRONG_TARGET 71 { "BR_MISPRED_DETAIL_RETURN_WRONG_TARGET", {0xb005b}, 0xf0, 3, {0xf00003}, "FE Branch Mispredict Detail -- Only return type branches, mispredicted branches due to wrong target for taken branches"}, #define PME_ITA2_BR_MISPRED_DETAIL2_ALL_ALL_UNKNOWN_PRED 72 { "BR_MISPRED_DETAIL2_ALL_ALL_UNKNOWN_PRED", {0x68}, 0xf0, 2, {0xf00003}, "FE Branch Mispredict Detail (Unknown Path Component) -- All branch types, branches with unknown path prediction"}, #define PME_ITA2_BR_MISPRED_DETAIL2_ALL_UNKNOWN_PATH_CORRECT_PRED 73 { "BR_MISPRED_DETAIL2_ALL_UNKNOWN_PATH_CORRECT_PRED", {0x10068}, 0xf0, 2, {0xf00003}, "FE Branch Mispredict Detail (Unknown Path Component) -- All branch types, branches with unknown path prediction and correctly predicted branch (outcome & target)"}, #define PME_ITA2_BR_MISPRED_DETAIL2_ALL_UNKNOWN_PATH_WRONG_PATH 74 { "BR_MISPRED_DETAIL2_ALL_UNKNOWN_PATH_WRONG_PATH", {0x20068}, 0xf0, 2, {0xf00003}, "FE Branch Mispredict Detail (Unknown Path Component) -- All branch types, branches with unknown path prediction and wrong branch direction"}, #define PME_ITA2_BR_MISPRED_DETAIL2_IPREL_ALL_UNKNOWN_PRED 75 { "BR_MISPRED_DETAIL2_IPREL_ALL_UNKNOWN_PRED", {0x40068}, 0xf0, 2, {0xf00003}, "FE Branch Mispredict Detail (Unknown Path Component) -- Only IP relative branches, branches with unknown path prediction"}, #define PME_ITA2_BR_MISPRED_DETAIL2_IPREL_UNKNOWN_PATH_CORRECT_PRED 76 { "BR_MISPRED_DETAIL2_IPREL_UNKNOWN_PATH_CORRECT_PRED", {0x50068}, 0xf0, 2, {0xf00003}, "FE Branch Mispredict Detail (Unknown Path Component) -- Only IP relative branches, branches with unknown path prediction and correct predicted branch (outcome & target)"}, #define PME_ITA2_BR_MISPRED_DETAIL2_IPREL_UNKNOWN_PATH_WRONG_PATH 77 { "BR_MISPRED_DETAIL2_IPREL_UNKNOWN_PATH_WRONG_PATH", {0x60068}, 0xf0, 2, {0xf00003}, "FE Branch Mispredict Detail (Unknown Path Component) -- Only IP relative branches, branches with unknown path prediction and wrong branch direction"}, #define PME_ITA2_BR_MISPRED_DETAIL2_NRETIND_ALL_UNKNOWN_PRED 78 { "BR_MISPRED_DETAIL2_NRETIND_ALL_UNKNOWN_PRED", {0xc0068}, 0xf0, 2, {0xf00003}, "FE Branch Mispredict Detail (Unknown Path Component) -- Only non-return indirect branches, branches with unknown path prediction"}, #define PME_ITA2_BR_MISPRED_DETAIL2_NRETIND_UNKNOWN_PATH_CORRECT_PRED 79 { "BR_MISPRED_DETAIL2_NRETIND_UNKNOWN_PATH_CORRECT_PRED", {0xd0068}, 0xf0, 2, {0xf00003}, "FE Branch Mispredict Detail (Unknown Path Component) -- Only non-return indirect branches, branches with unknown path prediction and correct predicted branch (outcome & target)"}, #define PME_ITA2_BR_MISPRED_DETAIL2_NRETIND_UNKNOWN_PATH_WRONG_PATH 80 { "BR_MISPRED_DETAIL2_NRETIND_UNKNOWN_PATH_WRONG_PATH", {0xe0068}, 0xf0, 2, {0xf00003}, "FE Branch Mispredict Detail (Unknown Path Component) -- Only non-return indirect branches, branches with unknown path prediction and wrong branch direction"}, #define PME_ITA2_BR_MISPRED_DETAIL2_RETURN_ALL_UNKNOWN_PRED 81 { "BR_MISPRED_DETAIL2_RETURN_ALL_UNKNOWN_PRED", {0x80068}, 0xf0, 2, {0xf00003}, "FE Branch Mispredict Detail (Unknown Path Component) -- Only return type branches, branches with unknown path prediction"}, #define PME_ITA2_BR_MISPRED_DETAIL2_RETURN_UNKNOWN_PATH_CORRECT_PRED 82 { "BR_MISPRED_DETAIL2_RETURN_UNKNOWN_PATH_CORRECT_PRED", {0x90068}, 0xf0, 2, {0xf00003}, "FE Branch Mispredict Detail (Unknown Path Component) -- Only return type branches, branches with unknown path prediction and correct predicted branch (outcome & target)"}, #define PME_ITA2_BR_MISPRED_DETAIL2_RETURN_UNKNOWN_PATH_WRONG_PATH 83 { "BR_MISPRED_DETAIL2_RETURN_UNKNOWN_PATH_WRONG_PATH", {0xa0068}, 0xf0, 2, {0xf00003}, "FE Branch Mispredict Detail (Unknown Path Component) -- Only return type branches, branches with unknown path prediction and wrong branch direction"}, #define PME_ITA2_BR_PATH_PRED_ALL_MISPRED_NOTTAKEN 84 { "BR_PATH_PRED_ALL_MISPRED_NOTTAKEN", {0x54}, 0xf0, 3, {0xf00003}, "FE Branch Path Prediction Detail -- All branch types, incorrectly predicted path and not taken branch"}, #define PME_ITA2_BR_PATH_PRED_ALL_MISPRED_TAKEN 85 { "BR_PATH_PRED_ALL_MISPRED_TAKEN", {0x10054}, 0xf0, 3, {0xf00003}, "FE Branch Path Prediction Detail -- All branch types, incorrectly predicted path and taken branch"}, #define PME_ITA2_BR_PATH_PRED_ALL_OKPRED_NOTTAKEN 86 { "BR_PATH_PRED_ALL_OKPRED_NOTTAKEN", {0x20054}, 0xf0, 3, {0xf00003}, "FE Branch Path Prediction Detail -- All branch types, correctly predicted path and not taken branch"}, #define PME_ITA2_BR_PATH_PRED_ALL_OKPRED_TAKEN 87 { "BR_PATH_PRED_ALL_OKPRED_TAKEN", {0x30054}, 0xf0, 3, {0xf00003}, "FE Branch Path Prediction Detail -- All branch types, correctly predicted path and taken branch"}, #define PME_ITA2_BR_PATH_PRED_IPREL_MISPRED_NOTTAKEN 88 { "BR_PATH_PRED_IPREL_MISPRED_NOTTAKEN", {0x40054}, 0xf0, 3, {0xf00003}, "FE Branch Path Prediction Detail -- Only IP relative branches, incorrectly predicted path and not taken branch"}, #define PME_ITA2_BR_PATH_PRED_IPREL_MISPRED_TAKEN 89 { "BR_PATH_PRED_IPREL_MISPRED_TAKEN", {0x50054}, 0xf0, 3, {0xf00003}, "FE Branch Path Prediction Detail -- Only IP relative branches, incorrectly predicted path and taken branch"}, #define PME_ITA2_BR_PATH_PRED_IPREL_OKPRED_NOTTAKEN 90 { "BR_PATH_PRED_IPREL_OKPRED_NOTTAKEN", {0x60054}, 0xf0, 3, {0xf00003}, "FE Branch Path Prediction Detail -- Only IP relative branches, correctly predicted path and not taken branch"}, #define PME_ITA2_BR_PATH_PRED_IPREL_OKPRED_TAKEN 91 { "BR_PATH_PRED_IPREL_OKPRED_TAKEN", {0x70054}, 0xf0, 3, {0xf00003}, "FE Branch Path Prediction Detail -- Only IP relative branches, correctly predicted path and taken branch"}, #define PME_ITA2_BR_PATH_PRED_NRETIND_MISPRED_NOTTAKEN 92 { "BR_PATH_PRED_NRETIND_MISPRED_NOTTAKEN", {0xc0054}, 0xf0, 3, {0xf00003}, "FE Branch Path Prediction Detail -- Only non-return indirect branches, incorrectly predicted path and not taken branch"}, #define PME_ITA2_BR_PATH_PRED_NRETIND_MISPRED_TAKEN 93 { "BR_PATH_PRED_NRETIND_MISPRED_TAKEN", {0xd0054}, 0xf0, 3, {0xf00003}, "FE Branch Path Prediction Detail -- Only non-return indirect branches, incorrectly predicted path and taken branch"}, #define PME_ITA2_BR_PATH_PRED_NRETIND_OKPRED_NOTTAKEN 94 { "BR_PATH_PRED_NRETIND_OKPRED_NOTTAKEN", {0xe0054}, 0xf0, 3, {0xf00003}, "FE Branch Path Prediction Detail -- Only non-return indirect branches, correctly predicted path and not taken branch"}, #define PME_ITA2_BR_PATH_PRED_NRETIND_OKPRED_TAKEN 95 { "BR_PATH_PRED_NRETIND_OKPRED_TAKEN", {0xf0054}, 0xf0, 3, {0xf00003}, "FE Branch Path Prediction Detail -- Only non-return indirect branches, correctly predicted path and taken branch"}, #define PME_ITA2_BR_PATH_PRED_RETURN_MISPRED_NOTTAKEN 96 { "BR_PATH_PRED_RETURN_MISPRED_NOTTAKEN", {0x80054}, 0xf0, 3, {0xf00003}, "FE Branch Path Prediction Detail -- Only return type branches, incorrectly predicted path and not taken branch"}, #define PME_ITA2_BR_PATH_PRED_RETURN_MISPRED_TAKEN 97 { "BR_PATH_PRED_RETURN_MISPRED_TAKEN", {0x90054}, 0xf0, 3, {0xf00003}, "FE Branch Path Prediction Detail -- Only return type branches, incorrectly predicted path and taken branch"}, #define PME_ITA2_BR_PATH_PRED_RETURN_OKPRED_NOTTAKEN 98 { "BR_PATH_PRED_RETURN_OKPRED_NOTTAKEN", {0xa0054}, 0xf0, 3, {0xf00003}, "FE Branch Path Prediction Detail -- Only return type branches, correctly predicted path and not taken branch"}, #define PME_ITA2_BR_PATH_PRED_RETURN_OKPRED_TAKEN 99 { "BR_PATH_PRED_RETURN_OKPRED_TAKEN", {0xb0054}, 0xf0, 3, {0xf00003}, "FE Branch Path Prediction Detail -- Only return type branches, correctly predicted path and taken branch"}, #define PME_ITA2_BR_PATH_PRED2_ALL_UNKNOWNPRED_NOTTAKEN 100 { "BR_PATH_PRED2_ALL_UNKNOWNPRED_NOTTAKEN", {0x6a}, 0xf0, 2, {0xf00003}, "FE Branch Path Prediction Detail (Unknown pred component) -- All branch types, unknown predicted path and not taken branch (which impacts OKPRED_NOTTAKEN)"}, #define PME_ITA2_BR_PATH_PRED2_ALL_UNKNOWNPRED_TAKEN 101 { "BR_PATH_PRED2_ALL_UNKNOWNPRED_TAKEN", {0x1006a}, 0xf0, 2, {0xf00003}, "FE Branch Path Prediction Detail (Unknown pred component) -- All branch types, unknown predicted path and taken branch (which impacts MISPRED_TAKEN)"}, #define PME_ITA2_BR_PATH_PRED2_IPREL_UNKNOWNPRED_NOTTAKEN 102 { "BR_PATH_PRED2_IPREL_UNKNOWNPRED_NOTTAKEN", {0x4006a}, 0xf0, 2, {0xf00003}, "FE Branch Path Prediction Detail (Unknown pred component) -- Only IP relative branches, unknown predicted path and not taken branch (which impacts OKPRED_NOTTAKEN)"}, #define PME_ITA2_BR_PATH_PRED2_IPREL_UNKNOWNPRED_TAKEN 103 { "BR_PATH_PRED2_IPREL_UNKNOWNPRED_TAKEN", {0x5006a}, 0xf0, 2, {0xf00003}, "FE Branch Path Prediction Detail (Unknown pred component) -- Only IP relative branches, unknown predicted path and taken branch (which impacts MISPRED_TAKEN)"}, #define PME_ITA2_BR_PATH_PRED2_NRETIND_UNKNOWNPRED_NOTTAKEN 104 { "BR_PATH_PRED2_NRETIND_UNKNOWNPRED_NOTTAKEN", {0xc006a}, 0xf0, 2, {0xf00003}, "FE Branch Path Prediction Detail (Unknown pred component) -- Only non-return indirect branches, unknown predicted path and not taken branch (which impacts OKPRED_NOTTAKEN)"}, #define PME_ITA2_BR_PATH_PRED2_NRETIND_UNKNOWNPRED_TAKEN 105 { "BR_PATH_PRED2_NRETIND_UNKNOWNPRED_TAKEN", {0xd006a}, 0xf0, 2, {0xf00003}, "FE Branch Path Prediction Detail (Unknown pred component) -- Only non-return indirect branches, unknown predicted path and taken branch (which impacts MISPRED_TAKEN)"}, #define PME_ITA2_BR_PATH_PRED2_RETURN_UNKNOWNPRED_NOTTAKEN 106 { "BR_PATH_PRED2_RETURN_UNKNOWNPRED_NOTTAKEN", {0x8006a}, 0xf0, 2, {0xf00003}, "FE Branch Path Prediction Detail (Unknown pred component) -- Only return type branches, unknown predicted path and not taken branch (which impacts OKPRED_NOTTAKEN)"}, #define PME_ITA2_BR_PATH_PRED2_RETURN_UNKNOWNPRED_TAKEN 107 { "BR_PATH_PRED2_RETURN_UNKNOWNPRED_TAKEN", {0x9006a}, 0xf0, 2, {0xf00003}, "FE Branch Path Prediction Detail (Unknown pred component) -- Only return type branches, unknown predicted path and taken branch (which impacts MISPRED_TAKEN)"}, #define PME_ITA2_BUS_ALL_ANY 108 { "BUS_ALL_ANY", {0x30087}, 0xf0, 1, {0xf00000}, "Bus Transactions -- CPU or non-CPU (all transactions)."}, #define PME_ITA2_BUS_ALL_IO 109 { "BUS_ALL_IO", {0x10087}, 0xf0, 1, {0xf00000}, "Bus Transactions -- non-CPU priority agents"}, #define PME_ITA2_BUS_ALL_SELF 110 { "BUS_ALL_SELF", {0x20087}, 0xf0, 1, {0xf00000}, "Bus Transactions -- local processor"}, #define PME_ITA2_BUS_BACKSNP_REQ_THIS 111 { "BUS_BACKSNP_REQ_THIS", {0x1008e}, 0xf0, 1, {0xf00000}, "Bus Back Snoop Requests -- Counts the number of bus back snoop me requests"}, #define PME_ITA2_BUS_BRQ_LIVE_REQ_HI 112 { "BUS_BRQ_LIVE_REQ_HI", {0x9c}, 0xf0, 2, {0xf00000}, "BRQ Live Requests (upper 2 bits)"}, #define PME_ITA2_BUS_BRQ_LIVE_REQ_LO 113 { "BUS_BRQ_LIVE_REQ_LO", {0x9b}, 0xf0, 7, {0xf00000}, "BRQ Live Requests (lower 3 bits)"}, #define PME_ITA2_BUS_BRQ_REQ_INSERTED 114 { "BUS_BRQ_REQ_INSERTED", {0x9d}, 0xf0, 1, {0xf00000}, "BRQ Requests Inserted"}, #define PME_ITA2_BUS_DATA_CYCLE 115 { "BUS_DATA_CYCLE", {0x88}, 0xf0, 1, {0xf00000}, "Valid Data Cycle on the Bus"}, #define PME_ITA2_BUS_HITM 116 { "BUS_HITM", {0x84}, 0xf0, 1, {0xf00000}, "Bus Hit Modified Line Transactions"}, #define PME_ITA2_BUS_IO_ANY 117 { "BUS_IO_ANY", {0x30090}, 0xf0, 1, {0xf00000}, "IA-32 Compatible IO Bus Transactions -- CPU or non-CPU (all transactions)."}, #define PME_ITA2_BUS_IO_IO 118 { "BUS_IO_IO", {0x10090}, 0xf0, 1, {0xf00000}, "IA-32 Compatible IO Bus Transactions -- non-CPU priority agents"}, #define PME_ITA2_BUS_IO_SELF 119 { "BUS_IO_SELF", {0x20090}, 0xf0, 1, {0xf00000}, "IA-32 Compatible IO Bus Transactions -- local processor"}, #define PME_ITA2_BUS_IOQ_LIVE_REQ_HI 120 { "BUS_IOQ_LIVE_REQ_HI", {0x98}, 0xf0, 2, {0xf00000}, "Inorder Bus Queue Requests (upper 2 bits)"}, #define PME_ITA2_BUS_IOQ_LIVE_REQ_LO 121 { "BUS_IOQ_LIVE_REQ_LO", {0x97}, 0xf0, 3, {0xf00000}, "Inorder Bus Queue Requests (lower2 bitst)"}, #define PME_ITA2_BUS_LOCK_ANY 122 { "BUS_LOCK_ANY", {0x30093}, 0xf0, 1, {0xf00000}, "IA-32 Compatible Bus Lock Transactions -- CPU or non-CPU (all transactions)."}, #define PME_ITA2_BUS_LOCK_SELF 123 { "BUS_LOCK_SELF", {0x20093}, 0xf0, 1, {0xf00000}, "IA-32 Compatible Bus Lock Transactions -- local processor"}, #define PME_ITA2_BUS_MEMORY_ALL_ANY 124 { "BUS_MEMORY_ALL_ANY", {0xf008a}, 0xf0, 1, {0xf00000}, "Bus Memory Transactions -- All bus transactions from CPU or non-CPU (all transactions)."}, #define PME_ITA2_BUS_MEMORY_ALL_IO 125 { "BUS_MEMORY_ALL_IO", {0xd008a}, 0xf0, 1, {0xf00000}, "Bus Memory Transactions -- All bus transactions from non-CPU priority agents"}, #define PME_ITA2_BUS_MEMORY_ALL_SELF 126 { "BUS_MEMORY_ALL_SELF", {0xe008a}, 0xf0, 1, {0xf00000}, "Bus Memory Transactions -- All bus transactions from local processor"}, #define PME_ITA2_BUS_MEMORY_EQ_128BYTE_ANY 127 { "BUS_MEMORY_EQ_128BYTE_ANY", {0x7008a}, 0xf0, 1, {0xf00000}, "Bus Memory Transactions -- number of full cache line transactions (BRL, BRIL, BWL) from CPU or non-CPU (all transactions)."}, #define PME_ITA2_BUS_MEMORY_EQ_128BYTE_IO 128 { "BUS_MEMORY_EQ_128BYTE_IO", {0x5008a}, 0xf0, 1, {0xf00000}, "Bus Memory Transactions -- number of full cache line transactions (BRL, BRIL, BWL) from non-CPU priority agents"}, #define PME_ITA2_BUS_MEMORY_EQ_128BYTE_SELF 129 { "BUS_MEMORY_EQ_128BYTE_SELF", {0x6008a}, 0xf0, 1, {0xf00000}, "Bus Memory Transactions -- number of full cache line transactions (BRL, BRIL, BWL) from local processor"}, #define PME_ITA2_BUS_MEMORY_LT_128BYTE_ANY 130 { "BUS_MEMORY_LT_128BYTE_ANY", {0xb008a}, 0xf0, 1, {0xf00000}, "Bus Memory Transactions -- number of less than full cache line transactions (BRP, BWP) CPU or non-CPU (all transactions)."}, #define PME_ITA2_BUS_MEMORY_LT_128BYTE_IO 131 { "BUS_MEMORY_LT_128BYTE_IO", {0x9008a}, 0xf0, 1, {0xf00000}, "Bus Memory Transactions -- number of less than full cache line transactions (BRP, BWP) from non-CPU priority agents"}, #define PME_ITA2_BUS_MEMORY_LT_128BYTE_SELF 132 { "BUS_MEMORY_LT_128BYTE_SELF", {0xa008a}, 0xf0, 1, {0xf00000}, "Bus Memory Transactions -- number of less than full cache line transactions (BRP, BWP) local processor"}, #define PME_ITA2_BUS_MEM_READ_ALL_ANY 133 { "BUS_MEM_READ_ALL_ANY", {0xf008b}, 0xf0, 1, {0xf00000}, "Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- All memory read transactions from CPU or non-CPU (all transactions)."}, #define PME_ITA2_BUS_MEM_READ_ALL_IO 134 { "BUS_MEM_READ_ALL_IO", {0xd008b}, 0xf0, 1, {0xf00000}, "Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- All memory read transactions from non-CPU priority agents"}, #define PME_ITA2_BUS_MEM_READ_ALL_SELF 135 { "BUS_MEM_READ_ALL_SELF", {0xe008b}, 0xf0, 1, {0xf00000}, "Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- All memory read transactions from local processor"}, #define PME_ITA2_BUS_MEM_READ_BIL_ANY 136 { "BUS_MEM_READ_BIL_ANY", {0x3008b}, 0xf0, 1, {0xf00000}, "Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- Number of BIL 0-byte memory read invalidate transactions from CPU or non-CPU (all transactions)."}, #define PME_ITA2_BUS_MEM_READ_BIL_IO 137 { "BUS_MEM_READ_BIL_IO", {0x1008b}, 0xf0, 1, {0xf00000}, "Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- Number of BIL 0-byte memory read invalidate transactions from non-CPU priority agents"}, #define PME_ITA2_BUS_MEM_READ_BIL_SELF 138 { "BUS_MEM_READ_BIL_SELF", {0x2008b}, 0xf0, 1, {0xf00000}, "Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- Number of BIL 0-byte memory read invalidate transactions from local processor"}, #define PME_ITA2_BUS_MEM_READ_BRIL_ANY 139 { "BUS_MEM_READ_BRIL_ANY", {0xb008b}, 0xf0, 1, {0xf00000}, "Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- Number of full cache line memory read invalidate transactions from CPU or non-CPU (all transactions)."}, #define PME_ITA2_BUS_MEM_READ_BRIL_IO 140 { "BUS_MEM_READ_BRIL_IO", {0x9008b}, 0xf0, 1, {0xf00000}, "Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- Number of full cache line memory read invalidate transactions from non-CPU priority agents"}, #define PME_ITA2_BUS_MEM_READ_BRIL_SELF 141 { "BUS_MEM_READ_BRIL_SELF", {0xa008b}, 0xf0, 1, {0xf00000}, "Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- Number of full cache line memory read invalidate transactions from local processor"}, #define PME_ITA2_BUS_MEM_READ_BRL_ANY 142 { "BUS_MEM_READ_BRL_ANY", {0x7008b}, 0xf0, 1, {0xf00000}, "Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- Number of full cache line memory read transactions from CPU or non-CPU (all transactions)."}, #define PME_ITA2_BUS_MEM_READ_BRL_IO 143 { "BUS_MEM_READ_BRL_IO", {0x5008b}, 0xf0, 1, {0xf00000}, "Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- Number of full cache line memory read transactions from non-CPU priority agents"}, #define PME_ITA2_BUS_MEM_READ_BRL_SELF 144 { "BUS_MEM_READ_BRL_SELF", {0x6008b}, 0xf0, 1, {0xf00000}, "Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- Number of full cache line memory read transactions from local processor"}, #define PME_ITA2_BUS_MEM_READ_OUT_HI 145 { "BUS_MEM_READ_OUT_HI", {0x94}, 0xf0, 2, {0xf00000}, "Outstanding Memory Read Transactions (upper 2 bits)"}, #define PME_ITA2_BUS_MEM_READ_OUT_LO 146 { "BUS_MEM_READ_OUT_LO", {0x95}, 0xf0, 7, {0xf00000}, "Outstanding Memory Read Transactions (lower 3 bits)"}, #define PME_ITA2_BUS_OOQ_LIVE_REQ_HI 147 { "BUS_OOQ_LIVE_REQ_HI", {0x9a}, 0xf0, 2, {0xf00000}, "Out-of-order Bus Queue Requests (upper 2 bits)"}, #define PME_ITA2_BUS_OOQ_LIVE_REQ_LO 148 { "BUS_OOQ_LIVE_REQ_LO", {0x99}, 0xf0, 7, {0xf00000}, "Out-of-order Bus Queue Requests (lower 3 bits)"}, #define PME_ITA2_BUS_RD_DATA_ANY 149 { "BUS_RD_DATA_ANY", {0x3008c}, 0xf0, 1, {0xf00000}, "Bus Read Data Transactions -- CPU or non-CPU (all transactions)."}, #define PME_ITA2_BUS_RD_DATA_IO 150 { "BUS_RD_DATA_IO", {0x1008c}, 0xf0, 1, {0xf00000}, "Bus Read Data Transactions -- non-CPU priority agents"}, #define PME_ITA2_BUS_RD_DATA_SELF 151 { "BUS_RD_DATA_SELF", {0x2008c}, 0xf0, 1, {0xf00000}, "Bus Read Data Transactions -- local processor"}, #define PME_ITA2_BUS_RD_HIT 152 { "BUS_RD_HIT", {0x80}, 0xf0, 1, {0xf00000}, "Bus Read Hit Clean Non-local Cache Transactions"}, #define PME_ITA2_BUS_RD_HITM 153 { "BUS_RD_HITM", {0x81}, 0xf0, 1, {0xf00000}, "Bus Read Hit Modified Non-local Cache Transactions"}, #define PME_ITA2_BUS_RD_INVAL_ALL_HITM 154 { "BUS_RD_INVAL_ALL_HITM", {0x83}, 0xf0, 1, {0xf00000}, "Bus BRIL Burst Transaction Results in HITM"}, #define PME_ITA2_BUS_RD_INVAL_HITM 155 { "BUS_RD_INVAL_HITM", {0x82}, 0xf0, 1, {0xf00000}, "Bus BIL Transaction Results in HITM"}, #define PME_ITA2_BUS_RD_IO_ANY 156 { "BUS_RD_IO_ANY", {0x30091}, 0xf0, 1, {0xf00000}, "IA-32 Compatible IO Read Transactions -- CPU or non-CPU (all transactions)."}, #define PME_ITA2_BUS_RD_IO_IO 157 { "BUS_RD_IO_IO", {0x10091}, 0xf0, 1, {0xf00000}, "IA-32 Compatible IO Read Transactions -- non-CPU priority agents"}, #define PME_ITA2_BUS_RD_IO_SELF 158 { "BUS_RD_IO_SELF", {0x20091}, 0xf0, 1, {0xf00000}, "IA-32 Compatible IO Read Transactions -- local processor"}, #define PME_ITA2_BUS_RD_PRTL_ANY 159 { "BUS_RD_PRTL_ANY", {0x3008d}, 0xf0, 1, {0xf00000}, "Bus Read Partial Transactions -- CPU or non-CPU (all transactions)."}, #define PME_ITA2_BUS_RD_PRTL_IO 160 { "BUS_RD_PRTL_IO", {0x1008d}, 0xf0, 1, {0xf00000}, "Bus Read Partial Transactions -- non-CPU priority agents"}, #define PME_ITA2_BUS_RD_PRTL_SELF 161 { "BUS_RD_PRTL_SELF", {0x2008d}, 0xf0, 1, {0xf00000}, "Bus Read Partial Transactions -- local processor"}, #define PME_ITA2_BUS_SNOOPQ_REQ 162 { "BUS_SNOOPQ_REQ", {0x96}, 0xf0, 7, {0xf00000}, "Bus Snoop Queue Requests"}, #define PME_ITA2_BUS_SNOOPS_ANY 163 { "BUS_SNOOPS_ANY", {0x30086}, 0xf0, 1, {0xf00000}, "Bus Snoops Total -- CPU or non-CPU (all transactions)."}, #define PME_ITA2_BUS_SNOOPS_IO 164 { "BUS_SNOOPS_IO", {0x10086}, 0xf0, 1, {0xf00000}, "Bus Snoops Total -- non-CPU priority agents"}, #define PME_ITA2_BUS_SNOOPS_SELF 165 { "BUS_SNOOPS_SELF", {0x20086}, 0xf0, 1, {0xf00000}, "Bus Snoops Total -- local processor"}, #define PME_ITA2_BUS_SNOOPS_HITM_ANY 166 { "BUS_SNOOPS_HITM_ANY", {0x30085}, 0xf0, 1, {0xf00000}, "Bus Snoops HIT Modified Cache Line -- CPU or non-CPU (all transactions)."}, #define PME_ITA2_BUS_SNOOPS_HITM_SELF 167 { "BUS_SNOOPS_HITM_SELF", {0x20085}, 0xf0, 1, {0xf00000}, "Bus Snoops HIT Modified Cache Line -- local processor"}, #define PME_ITA2_BUS_SNOOP_STALL_CYCLES_ANY 168 { "BUS_SNOOP_STALL_CYCLES_ANY", {0x3008f}, 0xf0, 1, {0xf00000}, "Bus Snoop Stall Cycles (from any agent) -- CPU or non-CPU (all transactions)."}, #define PME_ITA2_BUS_SNOOP_STALL_CYCLES_SELF 169 { "BUS_SNOOP_STALL_CYCLES_SELF", {0x2008f}, 0xf0, 1, {0xf00000}, "Bus Snoop Stall Cycles (from any agent) -- local processor"}, #define PME_ITA2_BUS_WR_WB_ALL_ANY 170 { "BUS_WR_WB_ALL_ANY", {0xf0092}, 0xf0, 1, {0xf00000}, "Bus Write Back Transactions -- CPU or non-CPU (all transactions)."}, #define PME_ITA2_BUS_WR_WB_ALL_IO 171 { "BUS_WR_WB_ALL_IO", {0xd0092}, 0xf0, 1, {0xf00000}, "Bus Write Back Transactions -- non-CPU priority agents"}, #define PME_ITA2_BUS_WR_WB_ALL_SELF 172 { "BUS_WR_WB_ALL_SELF", {0xe0092}, 0xf0, 1, {0xf00000}, "Bus Write Back Transactions -- local processor"}, #define PME_ITA2_BUS_WR_WB_CCASTOUT_ANY 173 { "BUS_WR_WB_CCASTOUT_ANY", {0xb0092}, 0xf0, 1, {0xf00000}, "Bus Write Back Transactions -- CPU or non-CPU (all transactions)/Only 0-byte transactions with write back attribute (clean cast outs) will be counted"}, #define PME_ITA2_BUS_WR_WB_CCASTOUT_SELF 174 { "BUS_WR_WB_CCASTOUT_SELF", {0xa0092}, 0xf0, 1, {0xf00000}, "Bus Write Back Transactions -- local processor/Only 0-byte transactions with write back attribute (clean cast outs) will be counted"}, #define PME_ITA2_BUS_WR_WB_EQ_128BYTE_ANY 175 { "BUS_WR_WB_EQ_128BYTE_ANY", {0x70092}, 0xf0, 1, {0xf00000}, "Bus Write Back Transactions -- CPU or non-CPU (all transactions)./Only cache line transactions with write back or write coalesce attributes will be counted."}, #define PME_ITA2_BUS_WR_WB_EQ_128BYTE_IO 176 { "BUS_WR_WB_EQ_128BYTE_IO", {0x50092}, 0xf0, 1, {0xf00000}, "Bus Write Back Transactions -- non-CPU priority agents/Only cache line transactions with write back or write coalesce attributes will be counted."}, #define PME_ITA2_BUS_WR_WB_EQ_128BYTE_SELF 177 { "BUS_WR_WB_EQ_128BYTE_SELF", {0x60092}, 0xf0, 1, {0xf00000}, "Bus Write Back Transactions -- local processor/Only cache line transactions with write back or write coalesce attributes will be counted."}, #define PME_ITA2_CPU_CPL_CHANGES 178 { "CPU_CPL_CHANGES", {0x13}, 0xf0, 1, {0xf00000}, "Privilege Level Changes"}, #define PME_ITA2_CPU_CYCLES 179 { "CPU_CYCLES", {0x12}, 0xf0, 1, {0xf00000}, "CPU Cycles"}, #define PME_ITA2_DATA_DEBUG_REGISTER_FAULT 180 { "DATA_DEBUG_REGISTER_FAULT", {0x52}, 0xf0, 1, {0xf00000}, "Fault Due to Data Debug Reg. Match to Load/Store Instruction"}, #define PME_ITA2_DATA_DEBUG_REGISTER_MATCHES 181 { "DATA_DEBUG_REGISTER_MATCHES", {0xc6}, 0xf0, 1, {0xf00007}, "Data Debug Register Matches Data Address of Memory Reference."}, #define PME_ITA2_DATA_EAR_ALAT 182 { "DATA_EAR_ALAT", {0x6c8}, 0xf0, 1, {0xf00007}, "Data EAR ALAT"}, #define PME_ITA2_DATA_EAR_CACHE_LAT1024 183 { "DATA_EAR_CACHE_LAT1024", {0x805c8}, 0xf0, 1, {0xf00007}, "Data EAR Cache -- >= 1024 Cycles"}, #define PME_ITA2_DATA_EAR_CACHE_LAT128 184 { "DATA_EAR_CACHE_LAT128", {0x505c8}, 0xf0, 1, {0xf00007}, "Data EAR Cache -- >= 128 Cycles"}, #define PME_ITA2_DATA_EAR_CACHE_LAT16 185 { "DATA_EAR_CACHE_LAT16", {0x205c8}, 0xf0, 1, {0xf00007}, "Data EAR Cache -- >= 16 Cycles"}, #define PME_ITA2_DATA_EAR_CACHE_LAT2048 186 { "DATA_EAR_CACHE_LAT2048", {0x905c8}, 0xf0, 1, {0xf00007}, "Data EAR Cache -- >= 2048 Cycles"}, #define PME_ITA2_DATA_EAR_CACHE_LAT256 187 { "DATA_EAR_CACHE_LAT256", {0x605c8}, 0xf0, 1, {0xf00007}, "Data EAR Cache -- >= 256 Cycles"}, #define PME_ITA2_DATA_EAR_CACHE_LAT32 188 { "DATA_EAR_CACHE_LAT32", {0x305c8}, 0xf0, 1, {0xf00007}, "Data EAR Cache -- >= 32 Cycles"}, #define PME_ITA2_DATA_EAR_CACHE_LAT4 189 { "DATA_EAR_CACHE_LAT4", {0x5c8}, 0xf0, 1, {0xf00007}, "Data EAR Cache -- >= 4 Cycles"}, #define PME_ITA2_DATA_EAR_CACHE_LAT4096 190 { "DATA_EAR_CACHE_LAT4096", {0xa05c8}, 0xf0, 1, {0xf00007}, "Data EAR Cache -- >= 4096 Cycles"}, #define PME_ITA2_DATA_EAR_CACHE_LAT512 191 { "DATA_EAR_CACHE_LAT512", {0x705c8}, 0xf0, 1, {0xf00007}, "Data EAR Cache -- >= 512 Cycles"}, #define PME_ITA2_DATA_EAR_CACHE_LAT64 192 { "DATA_EAR_CACHE_LAT64", {0x405c8}, 0xf0, 1, {0xf00007}, "Data EAR Cache -- >= 64 Cycles"}, #define PME_ITA2_DATA_EAR_CACHE_LAT8 193 { "DATA_EAR_CACHE_LAT8", {0x105c8}, 0xf0, 1, {0xf00007}, "Data EAR Cache -- >= 8 Cycles"}, #define PME_ITA2_DATA_EAR_EVENTS 194 { "DATA_EAR_EVENTS", {0xc8}, 0xf0, 1, {0xf00007}, "L1 Data Cache EAR Events"}, #define PME_ITA2_DATA_EAR_TLB_ALL 195 { "DATA_EAR_TLB_ALL", {0xe04c8}, 0xf0, 1, {0xf00007}, "Data EAR TLB -- All L1 DTLB Misses"}, #define PME_ITA2_DATA_EAR_TLB_FAULT 196 { "DATA_EAR_TLB_FAULT", {0x804c8}, 0xf0, 1, {0xf00007}, "Data EAR TLB -- DTLB Misses which produce a software fault"}, #define PME_ITA2_DATA_EAR_TLB_L2DTLB 197 { "DATA_EAR_TLB_L2DTLB", {0x204c8}, 0xf0, 1, {0xf00007}, "Data EAR TLB -- L1 DTLB Misses which hit L2 DTLB"}, #define PME_ITA2_DATA_EAR_TLB_L2DTLB_OR_FAULT 198 { "DATA_EAR_TLB_L2DTLB_OR_FAULT", {0xa04c8}, 0xf0, 1, {0xf00007}, "Data EAR TLB -- L1 DTLB Misses which hit L2 DTLB or produce a software fault"}, #define PME_ITA2_DATA_EAR_TLB_L2DTLB_OR_VHPT 199 { "DATA_EAR_TLB_L2DTLB_OR_VHPT", {0x604c8}, 0xf0, 1, {0xf00007}, "Data EAR TLB -- L1 DTLB Misses which hit L2 DTLB or VHPT"}, #define PME_ITA2_DATA_EAR_TLB_VHPT 200 { "DATA_EAR_TLB_VHPT", {0x404c8}, 0xf0, 1, {0xf00007}, "Data EAR TLB -- L1 DTLB Misses which hit VHPT"}, #define PME_ITA2_DATA_EAR_TLB_VHPT_OR_FAULT 201 { "DATA_EAR_TLB_VHPT_OR_FAULT", {0xc04c8}, 0xf0, 1, {0xf00007}, "Data EAR TLB -- L1 DTLB Misses which hit VHPT or produce a software fault"}, #define PME_ITA2_DATA_REFERENCES_SET0 202 { "DATA_REFERENCES_SET0", {0xc3}, 0xf0, 4, {0x5010007}, "Data Memory References Issued to Memory Pipeline"}, #define PME_ITA2_DATA_REFERENCES_SET1 203 { "DATA_REFERENCES_SET1", {0xc5}, 0xf0, 4, {0x5110007}, "Data Memory References Issued to Memory Pipeline"}, #define PME_ITA2_DISP_STALLED 204 { "DISP_STALLED", {0x49}, 0xf0, 1, {0xf00000}, "Number of Cycles Dispersal Stalled"}, #define PME_ITA2_DTLB_INSERTS_HPW 205 { "DTLB_INSERTS_HPW", {0xc9}, 0xf0, 4, {0xf00007}, "Hardware Page Walker Installs to DTLB"}, #define PME_ITA2_DTLB_INSERTS_HPW_RETIRED 206 { "DTLB_INSERTS_HPW_RETIRED", {0x2c}, 0xf0, 4, {0xf00007}, "VHPT Entries Inserted into DTLB by the Hardware Page Walker"}, #define PME_ITA2_ENCBR_MISPRED_DETAIL_ALL_ALL_PRED 207 { "ENCBR_MISPRED_DETAIL_ALL_ALL_PRED", {0x63}, 0xf0, 3, {0xf00003}, "Number of Encoded Branches Retired -- All encoded branches regardless of prediction result"}, #define PME_ITA2_ENCBR_MISPRED_DETAIL_ALL_CORRECT_PRED 208 { "ENCBR_MISPRED_DETAIL_ALL_CORRECT_PRED", {0x10063}, 0xf0, 3, {0xf00003}, "Number of Encoded Branches Retired -- All encoded branches, correctly predicted branches (outcome and target)"}, #define PME_ITA2_ENCBR_MISPRED_DETAIL_ALL_WRONG_PATH 209 { "ENCBR_MISPRED_DETAIL_ALL_WRONG_PATH", {0x20063}, 0xf0, 3, {0xf00003}, "Number of Encoded Branches Retired -- All encoded branches, mispredicted branches due to wrong branch direction"}, #define PME_ITA2_ENCBR_MISPRED_DETAIL_ALL_WRONG_TARGET 210 { "ENCBR_MISPRED_DETAIL_ALL_WRONG_TARGET", {0x30063}, 0xf0, 3, {0xf00003}, "Number of Encoded Branches Retired -- All encoded branches, mispredicted branches due to wrong target for taken branches"}, #define PME_ITA2_ENCBR_MISPRED_DETAIL_ALL2_ALL_PRED 211 { "ENCBR_MISPRED_DETAIL_ALL2_ALL_PRED", {0xc0063}, 0xf0, 3, {0xf00003}, "Number of Encoded Branches Retired -- Only non-return indirect branches, regardless of prediction result"}, #define PME_ITA2_ENCBR_MISPRED_DETAIL_ALL2_CORRECT_PRED 212 { "ENCBR_MISPRED_DETAIL_ALL2_CORRECT_PRED", {0xd0063}, 0xf0, 3, {0xf00003}, "Number of Encoded Branches Retired -- Only non-return indirect branches, correctly predicted branches (outcome and target)"}, #define PME_ITA2_ENCBR_MISPRED_DETAIL_ALL2_WRONG_PATH 213 { "ENCBR_MISPRED_DETAIL_ALL2_WRONG_PATH", {0xe0063}, 0xf0, 3, {0xf00003}, "Number of Encoded Branches Retired -- Only non-return indirect branches, mispredicted branches due to wrong branch direction"}, #define PME_ITA2_ENCBR_MISPRED_DETAIL_ALL2_WRONG_TARGET 214 { "ENCBR_MISPRED_DETAIL_ALL2_WRONG_TARGET", {0xf0063}, 0xf0, 3, {0xf00003}, "Number of Encoded Branches Retired -- Only non-return indirect branches, mispredicted branches due to wrong target for taken branches"}, #define PME_ITA2_ENCBR_MISPRED_DETAIL_OVERSUB_ALL_PRED 215 { "ENCBR_MISPRED_DETAIL_OVERSUB_ALL_PRED", {0x80063}, 0xf0, 3, {0xf00003}, "Number of Encoded Branches Retired -- Only return type branches, regardless of prediction result"}, #define PME_ITA2_ENCBR_MISPRED_DETAIL_OVERSUB_CORRECT_PRED 216 { "ENCBR_MISPRED_DETAIL_OVERSUB_CORRECT_PRED", {0x90063}, 0xf0, 3, {0xf00003}, "Number of Encoded Branches Retired -- Only return type branches, correctly predicted branches (outcome and target)"}, #define PME_ITA2_ENCBR_MISPRED_DETAIL_OVERSUB_WRONG_PATH 217 { "ENCBR_MISPRED_DETAIL_OVERSUB_WRONG_PATH", {0xa0063}, 0xf0, 3, {0xf00003}, "Number of Encoded Branches Retired -- Only return type branches, mispredicted branches due to wrong branch direction"}, #define PME_ITA2_ENCBR_MISPRED_DETAIL_OVERSUB_WRONG_TARGET 218 { "ENCBR_MISPRED_DETAIL_OVERSUB_WRONG_TARGET", {0xb0063}, 0xf0, 3, {0xf00003}, "Number of Encoded Branches Retired -- Only return type branches, mispredicted branches due to wrong target for taken branches"}, #define PME_ITA2_EXTERN_DP_PINS_0_TO_3_ALL 219 { "EXTERN_DP_PINS_0_TO_3_ALL", {0xf009e}, 0xf0, 1, {0xf00000}, "DP Pins 0-3 Asserted -- include pin3 assertion"}, #define PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN0 220 { "EXTERN_DP_PINS_0_TO_3_PIN0", {0x1009e}, 0xf0, 1, {0xf00000}, "DP Pins 0-3 Asserted -- include pin0 assertion"}, #define PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN0_OR_PIN1 221 { "EXTERN_DP_PINS_0_TO_3_PIN0_OR_PIN1", {0x3009e}, 0xf0, 1, {0xf00000}, "DP Pins 0-3 Asserted -- include pin0 or pin1 assertion"}, #define PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN0_OR_PIN1_OR_PIN2 222 { "EXTERN_DP_PINS_0_TO_3_PIN0_OR_PIN1_OR_PIN2", {0x7009e}, 0xf0, 1, {0xf00000}, "DP Pins 0-3 Asserted -- include pin0 or pin1 or pin2 assertion"}, #define PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN0_OR_PIN1_OR_PIN3 223 { "EXTERN_DP_PINS_0_TO_3_PIN0_OR_PIN1_OR_PIN3", {0xb009e}, 0xf0, 1, {0xf00000}, "DP Pins 0-3 Asserted -- include pin0 or pin1 or pin3 assertion"}, #define PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN0_OR_PIN2 224 { "EXTERN_DP_PINS_0_TO_3_PIN0_OR_PIN2", {0x5009e}, 0xf0, 1, {0xf00000}, "DP Pins 0-3 Asserted -- include pin0 or pin2 assertion"}, #define PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN0_OR_PIN2_OR_PIN3 225 { "EXTERN_DP_PINS_0_TO_3_PIN0_OR_PIN2_OR_PIN3", {0xd009e}, 0xf0, 1, {0xf00000}, "DP Pins 0-3 Asserted -- include pin0 or pin2 or pin3 assertion"}, #define PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN0_OR_PIN3 226 { "EXTERN_DP_PINS_0_TO_3_PIN0_OR_PIN3", {0x9009e}, 0xf0, 1, {0xf00000}, "DP Pins 0-3 Asserted -- include pin0 or pin3 assertion"}, #define PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN1 227 { "EXTERN_DP_PINS_0_TO_3_PIN1", {0x2009e}, 0xf0, 1, {0xf00000}, "DP Pins 0-3 Asserted -- include pin1 assertion"}, #define PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN1_OR_PIN2 228 { "EXTERN_DP_PINS_0_TO_3_PIN1_OR_PIN2", {0x6009e}, 0xf0, 1, {0xf00000}, "DP Pins 0-3 Asserted -- include pin1 or pin2 assertion"}, #define PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN1_OR_PIN2_OR_PIN3 229 { "EXTERN_DP_PINS_0_TO_3_PIN1_OR_PIN2_OR_PIN3", {0xe009e}, 0xf0, 1, {0xf00000}, "DP Pins 0-3 Asserted -- include pin1 or pin2 or pin3 assertion"}, #define PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN1_OR_PIN3 230 { "EXTERN_DP_PINS_0_TO_3_PIN1_OR_PIN3", {0xa009e}, 0xf0, 1, {0xf00000}, "DP Pins 0-3 Asserted -- include pin1 or pin3 assertion"}, #define PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN2 231 { "EXTERN_DP_PINS_0_TO_3_PIN2", {0x4009e}, 0xf0, 1, {0xf00000}, "DP Pins 0-3 Asserted -- include pin2 assertion"}, #define PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN2_OR_PIN3 232 { "EXTERN_DP_PINS_0_TO_3_PIN2_OR_PIN3", {0xc009e}, 0xf0, 1, {0xf00000}, "DP Pins 0-3 Asserted -- include pin2 or pin3 assertion"}, #define PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN3 233 { "EXTERN_DP_PINS_0_TO_3_PIN3", {0x8009e}, 0xf0, 1, {0xf00000}, "DP Pins 0-3 Asserted -- include pin3 assertion"}, #define PME_ITA2_EXTERN_DP_PINS_4_TO_5_ALL 234 { "EXTERN_DP_PINS_4_TO_5_ALL", {0x3009f}, 0xf0, 1, {0xf00000}, "DP Pins 4-5 Asserted -- include pin5 assertion"}, #define PME_ITA2_EXTERN_DP_PINS_4_TO_5_PIN4 235 { "EXTERN_DP_PINS_4_TO_5_PIN4", {0x1009f}, 0xf0, 1, {0xf00000}, "DP Pins 4-5 Asserted -- include pin4 assertion"}, #define PME_ITA2_EXTERN_DP_PINS_4_TO_5_PIN5 236 { "EXTERN_DP_PINS_4_TO_5_PIN5", {0x2009f}, 0xf0, 1, {0xf00000}, "DP Pins 4-5 Asserted -- include pin5 assertion"}, #define PME_ITA2_FE_BUBBLE_ALL 237 { "FE_BUBBLE_ALL", {0x71}, 0xf0, 1, {0xf00000}, "Bubbles Seen by FE -- count regardless of cause"}, #define PME_ITA2_FE_BUBBLE_ALLBUT_FEFLUSH_BUBBLE 238 { "FE_BUBBLE_ALLBUT_FEFLUSH_BUBBLE", {0xb0071}, 0xf0, 1, {0xf00000}, "Bubbles Seen by FE -- ALL except FEFLUSH and BUBBLE"}, #define PME_ITA2_FE_BUBBLE_ALLBUT_IBFULL 239 { "FE_BUBBLE_ALLBUT_IBFULL", {0xc0071}, 0xf0, 1, {0xf00000}, "Bubbles Seen by FE -- ALL except IBFULl"}, #define PME_ITA2_FE_BUBBLE_BRANCH 240 { "FE_BUBBLE_BRANCH", {0x90071}, 0xf0, 1, {0xf00000}, "Bubbles Seen by FE -- only if caused by any of 4 branch recirculates"}, #define PME_ITA2_FE_BUBBLE_BUBBLE 241 { "FE_BUBBLE_BUBBLE", {0xd0071}, 0xf0, 1, {0xf00000}, "Bubbles Seen by FE -- only if caused by branch bubble stall"}, #define PME_ITA2_FE_BUBBLE_FEFLUSH 242 { "FE_BUBBLE_FEFLUSH", {0x10071}, 0xf0, 1, {0xf00000}, "Bubbles Seen by FE -- only if caused by a front-end flush"}, #define PME_ITA2_FE_BUBBLE_FILL_RECIRC 243 { "FE_BUBBLE_FILL_RECIRC", {0x80071}, 0xf0, 1, {0xf00000}, "Bubbles Seen by FE -- only if caused by a recirculate for a cache line fill operation"}, #define PME_ITA2_FE_BUBBLE_GROUP1 244 { "FE_BUBBLE_GROUP1", {0x30071}, 0xf0, 1, {0xf00000}, "Bubbles Seen by FE -- BUBBLE or BRANCH"}, #define PME_ITA2_FE_BUBBLE_GROUP2 245 { "FE_BUBBLE_GROUP2", {0x40071}, 0xf0, 1, {0xf00000}, "Bubbles Seen by FE -- IMISS or TLBMISS"}, #define PME_ITA2_FE_BUBBLE_GROUP3 246 { "FE_BUBBLE_GROUP3", {0xa0071}, 0xf0, 1, {0xf00000}, "Bubbles Seen by FE -- FILL_RECIRC or BRANCH"}, #define PME_ITA2_FE_BUBBLE_IBFULL 247 { "FE_BUBBLE_IBFULL", {0x50071}, 0xf0, 1, {0xf00000}, "Bubbles Seen by FE -- only if caused by instruction buffer full stall"}, #define PME_ITA2_FE_BUBBLE_IMISS 248 { "FE_BUBBLE_IMISS", {0x60071}, 0xf0, 1, {0xf00000}, "Bubbles Seen by FE -- only if caused by instruction cache miss stall"}, #define PME_ITA2_FE_BUBBLE_TLBMISS 249 { "FE_BUBBLE_TLBMISS", {0x70071}, 0xf0, 1, {0xf00000}, "Bubbles Seen by FE -- only if caused by TLB stall"}, #define PME_ITA2_FE_LOST_BW_ALL 250 { "FE_LOST_BW_ALL", {0x70}, 0xf0, 2, {0xf00000}, "Invalid Bundles at the Entrance to IB -- count regardless of cause"}, #define PME_ITA2_FE_LOST_BW_BI 251 { "FE_LOST_BW_BI", {0x90070}, 0xf0, 2, {0xf00000}, "Invalid Bundles at the Entrance to IB -- only if caused by branch initialization stall"}, #define PME_ITA2_FE_LOST_BW_BRQ 252 { "FE_LOST_BW_BRQ", {0xa0070}, 0xf0, 2, {0xf00000}, "Invalid Bundles at the Entrance to IB -- only if caused by branch retirement queue stall"}, #define PME_ITA2_FE_LOST_BW_BR_ILOCK 253 { "FE_LOST_BW_BR_ILOCK", {0xc0070}, 0xf0, 2, {0xf00000}, "Invalid Bundles at the Entrance to IB -- only if caused by branch interlock stall"}, #define PME_ITA2_FE_LOST_BW_BUBBLE 254 { "FE_LOST_BW_BUBBLE", {0xd0070}, 0xf0, 2, {0xf00000}, "Invalid Bundles at the Entrance to IB -- only if caused by branch resteer bubble stall"}, #define PME_ITA2_FE_LOST_BW_FEFLUSH 255 { "FE_LOST_BW_FEFLUSH", {0x10070}, 0xf0, 2, {0xf00000}, "Invalid Bundles at the Entrance to IB -- only if caused by a front-end flush"}, #define PME_ITA2_FE_LOST_BW_FILL_RECIRC 256 { "FE_LOST_BW_FILL_RECIRC", {0x80070}, 0xf0, 2, {0xf00000}, "Invalid Bundles at the Entrance to IB -- only if caused by a recirculate for a cache line fill operation"}, #define PME_ITA2_FE_LOST_BW_IBFULL 257 { "FE_LOST_BW_IBFULL", {0x50070}, 0xf0, 2, {0xf00000}, "Invalid Bundles at the Entrance to IB -- only if caused by instruction buffer full stall"}, #define PME_ITA2_FE_LOST_BW_IMISS 258 { "FE_LOST_BW_IMISS", {0x60070}, 0xf0, 2, {0xf00000}, "Invalid Bundles at the Entrance to IB -- only if caused by instruction cache miss stall"}, #define PME_ITA2_FE_LOST_BW_PLP 259 { "FE_LOST_BW_PLP", {0xb0070}, 0xf0, 2, {0xf00000}, "Invalid Bundles at the Entrance to IB -- only if caused by perfect loop prediction stall"}, #define PME_ITA2_FE_LOST_BW_TLBMISS 260 { "FE_LOST_BW_TLBMISS", {0x70070}, 0xf0, 2, {0xf00000}, "Invalid Bundles at the Entrance to IB -- only if caused by TLB stall"}, #define PME_ITA2_FE_LOST_BW_UNREACHED 261 { "FE_LOST_BW_UNREACHED", {0x40070}, 0xf0, 2, {0xf00000}, "Invalid Bundles at the Entrance to IB -- only if caused by unreachable bundle"}, #define PME_ITA2_FP_FAILED_FCHKF 262 { "FP_FAILED_FCHKF", {0x6}, 0xf0, 1, {0xf00001}, "Failed fchkf"}, #define PME_ITA2_FP_FALSE_SIRSTALL 263 { "FP_FALSE_SIRSTALL", {0x5}, 0xf0, 1, {0xf00001}, "SIR Stall Without a Trap"}, #define PME_ITA2_FP_FLUSH_TO_ZERO 264 { "FP_FLUSH_TO_ZERO", {0xb}, 0xf0, 2, {0xf00001}, "FP Result Flushed to Zero"}, #define PME_ITA2_FP_OPS_RETIRED 265 { "FP_OPS_RETIRED", {0x9}, 0xf0, 4, {0xf00001}, "Retired FP Operations"}, #define PME_ITA2_FP_TRUE_SIRSTALL 266 { "FP_TRUE_SIRSTALL", {0x3}, 0xf0, 1, {0xf00001}, "SIR stall asserted and leads to a trap"}, #define PME_ITA2_HPW_DATA_REFERENCES 267 { "HPW_DATA_REFERENCES", {0x2d}, 0xf0, 4, {0xf00007}, "Data Memory References to VHPT"}, #define PME_ITA2_IA32_INST_RETIRED 268 { "IA32_INST_RETIRED", {0x59}, 0xf0, 2, {0xf00000}, "IA-32 Instructions Retired"}, #define PME_ITA2_IA32_ISA_TRANSITIONS 269 { "IA32_ISA_TRANSITIONS", {0x7}, 0xf0, 1, {0xf00000}, "IA-64 to/from IA-32 ISA Transitions"}, #define PME_ITA2_IA64_INST_RETIRED 270 { "IA64_INST_RETIRED", {0x8}, 0xf0, 6, {0xf00003}, "Retired IA-64 Instructions, alias to IA64_INST_RETIRED_THIS"}, #define PME_ITA2_IA64_INST_RETIRED_THIS 271 { "IA64_INST_RETIRED_THIS", {0x8}, 0xf0, 6, {0xf00003}, "Retired IA-64 Instructions -- Retired IA-64 Instructions"}, #define PME_ITA2_IA64_TAGGED_INST_RETIRED_IBRP0_PMC8 272 { "IA64_TAGGED_INST_RETIRED_IBRP0_PMC8", {0x8}, 0xf0, 6, {0xf00003}, "Retired Tagged Instructions -- Instruction tagged by Instruction Breakpoint Pair 0 and opcode matcher PMC8. Code executed with PSR.is=1 is included."}, #define PME_ITA2_IA64_TAGGED_INST_RETIRED_IBRP1_PMC9 273 { "IA64_TAGGED_INST_RETIRED_IBRP1_PMC9", {0x10008}, 0xf0, 6, {0xf00003}, "Retired Tagged Instructions -- Instruction tagged by Instruction Breakpoint Pair 1 and opcode matcher PMC9. Code executed with PSR.is=1 is included."}, #define PME_ITA2_IA64_TAGGED_INST_RETIRED_IBRP2_PMC8 274 { "IA64_TAGGED_INST_RETIRED_IBRP2_PMC8", {0x20008}, 0xf0, 6, {0xf00003}, "Retired Tagged Instructions -- Instruction tagged by Instruction Breakpoint Pair 2 and opcode matcher PMC8. Code executed with PSR.is=1 is not included."}, #define PME_ITA2_IA64_TAGGED_INST_RETIRED_IBRP3_PMC9 275 { "IA64_TAGGED_INST_RETIRED_IBRP3_PMC9", {0x30008}, 0xf0, 6, {0xf00003}, "Retired Tagged Instructions -- Instruction tagged by Instruction Breakpoint Pair 3 and opcode matcher PMC9. Code executed with PSR.is=1 is not included."}, #define PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_ALL 276 { "IDEAL_BE_LOST_BW_DUE_TO_FE_ALL", {0x73}, 0xf0, 2, {0xf00000}, "Invalid Bundles at the Exit from IB -- count regardless of cause"}, #define PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_BI 277 { "IDEAL_BE_LOST_BW_DUE_TO_FE_BI", {0x90073}, 0xf0, 2, {0xf00000}, "Invalid Bundles at the Exit from IB -- only if caused by branch initialization stall"}, #define PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_BRQ 278 { "IDEAL_BE_LOST_BW_DUE_TO_FE_BRQ", {0xa0073}, 0xf0, 2, {0xf00000}, "Invalid Bundles at the Exit from IB -- only if caused by branch retirement queue stall"}, #define PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_BR_ILOCK 279 { "IDEAL_BE_LOST_BW_DUE_TO_FE_BR_ILOCK", {0xc0073}, 0xf0, 2, {0xf00000}, "Invalid Bundles at the Exit from IB -- only if caused by branch interlock stall"}, #define PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_BUBBLE 280 { "IDEAL_BE_LOST_BW_DUE_TO_FE_BUBBLE", {0xd0073}, 0xf0, 2, {0xf00000}, "Invalid Bundles at the Exit from IB -- only if caused by branch resteer bubble stall"}, #define PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_FEFLUSH 281 { "IDEAL_BE_LOST_BW_DUE_TO_FE_FEFLUSH", {0x10073}, 0xf0, 2, {0xf00000}, "Invalid Bundles at the Exit from IB -- only if caused by a front-end flush"}, #define PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_FILL_RECIRC 282 { "IDEAL_BE_LOST_BW_DUE_TO_FE_FILL_RECIRC", {0x80073}, 0xf0, 2, {0xf00000}, "Invalid Bundles at the Exit from IB -- only if caused by a recirculate for a cache line fill operation"}, #define PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_IBFULL 283 { "IDEAL_BE_LOST_BW_DUE_TO_FE_IBFULL", {0x50073}, 0xf0, 2, {0xf00000}, "Invalid Bundles at the Exit from IB -- (* meaningless for this event *)"}, #define PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_IMISS 284 { "IDEAL_BE_LOST_BW_DUE_TO_FE_IMISS", {0x60073}, 0xf0, 2, {0xf00000}, "Invalid Bundles at the Exit from IB -- only if caused by instruction cache miss stall"}, #define PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_PLP 285 { "IDEAL_BE_LOST_BW_DUE_TO_FE_PLP", {0xb0073}, 0xf0, 2, {0xf00000}, "Invalid Bundles at the Exit from IB -- only if caused by perfect loop prediction stall"}, #define PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_TLBMISS 286 { "IDEAL_BE_LOST_BW_DUE_TO_FE_TLBMISS", {0x70073}, 0xf0, 2, {0xf00000}, "Invalid Bundles at the Exit from IB -- only if caused by TLB stall"}, #define PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_UNREACHED 287 { "IDEAL_BE_LOST_BW_DUE_TO_FE_UNREACHED", {0x40073}, 0xf0, 2, {0xf00000}, "Invalid Bundles at the Exit from IB -- only if caused by unreachable bundle"}, #define PME_ITA2_INST_CHKA_LDC_ALAT_ALL 288 { "INST_CHKA_LDC_ALAT_ALL", {0x30056}, 0xf0, 2, {0xf00007}, "Retired chk.a and ld.c Instructions -- both integer and floating point instructions"}, #define PME_ITA2_INST_CHKA_LDC_ALAT_FP 289 { "INST_CHKA_LDC_ALAT_FP", {0x20056}, 0xf0, 2, {0xf00007}, "Retired chk.a and ld.c Instructions -- only floating point instructions"}, #define PME_ITA2_INST_CHKA_LDC_ALAT_INT 290 { "INST_CHKA_LDC_ALAT_INT", {0x10056}, 0xf0, 2, {0xf00007}, "Retired chk.a and ld.c Instructions -- only integer instructions"}, #define PME_ITA2_INST_DISPERSED 291 { "INST_DISPERSED", {0x4d}, 0xf0, 6, {0xf00001}, "Syllables Dispersed from REN to REG stage"}, #define PME_ITA2_INST_FAILED_CHKA_LDC_ALAT_ALL 292 { "INST_FAILED_CHKA_LDC_ALAT_ALL", {0x30057}, 0xf0, 1, {0xf00007}, "Failed chk.a and ld.c Instructions -- both integer and floating point instructions"}, #define PME_ITA2_INST_FAILED_CHKA_LDC_ALAT_FP 293 { "INST_FAILED_CHKA_LDC_ALAT_FP", {0x20057}, 0xf0, 1, {0xf00007}, "Failed chk.a and ld.c Instructions -- only floating point instructions"}, #define PME_ITA2_INST_FAILED_CHKA_LDC_ALAT_INT 294 { "INST_FAILED_CHKA_LDC_ALAT_INT", {0x10057}, 0xf0, 1, {0xf00007}, "Failed chk.a and ld.c Instructions -- only integer instructions"}, #define PME_ITA2_INST_FAILED_CHKS_RETIRED_ALL 295 { "INST_FAILED_CHKS_RETIRED_ALL", {0x30055}, 0xf0, 1, {0xf00000}, "Failed chk.s Instructions -- both integer and floating point instructions"}, #define PME_ITA2_INST_FAILED_CHKS_RETIRED_FP 296 { "INST_FAILED_CHKS_RETIRED_FP", {0x20055}, 0xf0, 1, {0xf00000}, "Failed chk.s Instructions -- only floating point instructions"}, #define PME_ITA2_INST_FAILED_CHKS_RETIRED_INT 297 { "INST_FAILED_CHKS_RETIRED_INT", {0x10055}, 0xf0, 1, {0xf00000}, "Failed chk.s Instructions -- only integer instructions"}, #define PME_ITA2_ISB_BUNPAIRS_IN 298 { "ISB_BUNPAIRS_IN", {0x46}, 0xf0, 1, {0xf00001}, "Bundle Pairs Written from L2 into FE"}, #define PME_ITA2_ITLB_MISSES_FETCH_ALL 299 { "ITLB_MISSES_FETCH_ALL", {0x30047}, 0xf0, 1, {0xf00001}, "ITLB Misses Demand Fetch -- All tlb misses will be counted. Note that this is not equal to sum of the L1ITLB and L2ITLB umasks because any access could be a miss in L1ITLB and L2ITLB."}, #define PME_ITA2_ITLB_MISSES_FETCH_L1ITLB 300 { "ITLB_MISSES_FETCH_L1ITLB", {0x10047}, 0xf0, 1, {0xf00001}, "ITLB Misses Demand Fetch -- All misses in L1ITLB will be counted. even if L1ITLB is not updated for an access (Uncacheable/nat page/not present page/faulting/some flushed), it will be counted here."}, #define PME_ITA2_ITLB_MISSES_FETCH_L2ITLB 301 { "ITLB_MISSES_FETCH_L2ITLB", {0x20047}, 0xf0, 1, {0xf00001}, "ITLB Misses Demand Fetch -- All misses in L1ITLB which also missed in L2ITLB will be counted."}, #define PME_ITA2_L1DTLB_TRANSFER 302 { "L1DTLB_TRANSFER", {0xc0}, 0xf0, 1, {0x5010007}, "L1DTLB Misses That Hit in the L2DTLB for Accesses Counted in L1D_READS"}, #define PME_ITA2_L1D_READS_SET0 303 { "L1D_READS_SET0", {0xc2}, 0xf0, 2, {0x5010007}, "L1 Data Cache Reads"}, #define PME_ITA2_L1D_READS_SET1 304 { "L1D_READS_SET1", {0xc4}, 0xf0, 2, {0x5110007}, "L1 Data Cache Reads"}, #define PME_ITA2_L1D_READ_MISSES_ALL 305 { "L1D_READ_MISSES_ALL", {0xc7}, 0xf0, 2, {0x5110007}, "L1 Data Cache Read Misses -- all L1D read misses will be counted."}, #define PME_ITA2_L1D_READ_MISSES_RSE_FILL 306 { "L1D_READ_MISSES_RSE_FILL", {0x100c7}, 0xf0, 2, {0x5110007}, "L1 Data Cache Read Misses -- only L1D read misses caused by RSE fills will be counted"}, #define PME_ITA2_L1ITLB_INSERTS_HPW 307 { "L1ITLB_INSERTS_HPW", {0x48}, 0xf0, 1, {0xf00001}, "L1ITLB Hardware Page Walker Inserts"}, #define PME_ITA2_L1I_EAR_CACHE_LAT0 308 { "L1I_EAR_CACHE_LAT0", {0x400343}, 0xf0, 1, {0xf00001}, "L1I EAR Cache -- > 0 Cycles (All L1 Misses)"}, #define PME_ITA2_L1I_EAR_CACHE_LAT1024 309 { "L1I_EAR_CACHE_LAT1024", {0xc00343}, 0xf0, 1, {0xf00001}, "L1I EAR Cache -- >= 1024 Cycles"}, #define PME_ITA2_L1I_EAR_CACHE_LAT128 310 { "L1I_EAR_CACHE_LAT128", {0xf00343}, 0xf0, 1, {0xf00001}, "L1I EAR Cache -- >= 128 Cycles"}, #define PME_ITA2_L1I_EAR_CACHE_LAT16 311 { "L1I_EAR_CACHE_LAT16", {0xfc0343}, 0xf0, 1, {0xf00001}, "L1I EAR Cache -- >= 16 Cycles"}, #define PME_ITA2_L1I_EAR_CACHE_LAT256 312 { "L1I_EAR_CACHE_LAT256", {0xe00343}, 0xf0, 1, {0xf00001}, "L1I EAR Cache -- >= 256 Cycles"}, #define PME_ITA2_L1I_EAR_CACHE_LAT32 313 { "L1I_EAR_CACHE_LAT32", {0xf80343}, 0xf0, 1, {0xf00001}, "L1I EAR Cache -- >= 32 Cycles"}, #define PME_ITA2_L1I_EAR_CACHE_LAT4 314 { "L1I_EAR_CACHE_LAT4", {0xff0343}, 0xf0, 1, {0xf00001}, "L1I EAR Cache -- >= 4 Cycles"}, #define PME_ITA2_L1I_EAR_CACHE_LAT4096 315 { "L1I_EAR_CACHE_LAT4096", {0x800343}, 0xf0, 1, {0xf00001}, "L1I EAR Cache -- >= 4096 Cycles"}, #define PME_ITA2_L1I_EAR_CACHE_LAT8 316 { "L1I_EAR_CACHE_LAT8", {0xfe0343}, 0xf0, 1, {0xf00001}, "L1I EAR Cache -- >= 8 Cycles"}, #define PME_ITA2_L1I_EAR_CACHE_RAB 317 { "L1I_EAR_CACHE_RAB", {0x343}, 0xf0, 1, {0xf00001}, "L1I EAR Cache -- RAB HIT"}, #define PME_ITA2_L1I_EAR_EVENTS 318 { "L1I_EAR_EVENTS", {0x43}, 0xf0, 1, {0xf00001}, "Instruction EAR Events"}, #define PME_ITA2_L1I_EAR_TLB_ALL 319 { "L1I_EAR_TLB_ALL", {0x70243}, 0xf0, 1, {0xf00001}, "L1I EAR TLB -- All L1 ITLB Misses"}, #define PME_ITA2_L1I_EAR_TLB_FAULT 320 { "L1I_EAR_TLB_FAULT", {0x40243}, 0xf0, 1, {0xf00001}, "L1I EAR TLB -- ITLB Misses which produced a fault"}, #define PME_ITA2_L1I_EAR_TLB_L2TLB 321 { "L1I_EAR_TLB_L2TLB", {0x10243}, 0xf0, 1, {0xf00001}, "L1I EAR TLB -- L1 ITLB Misses which hit L2 ITLB"}, #define PME_ITA2_L1I_EAR_TLB_L2TLB_OR_FAULT 322 { "L1I_EAR_TLB_L2TLB_OR_FAULT", {0x50243}, 0xf0, 1, {0xf00001}, "L1I EAR TLB -- L1 ITLB Misses which hit L2 ITLB or produce a software fault"}, #define PME_ITA2_L1I_EAR_TLB_L2TLB_OR_VHPT 323 { "L1I_EAR_TLB_L2TLB_OR_VHPT", {0x30243}, 0xf0, 1, {0xf00001}, "L1I EAR TLB -- L1 ITLB Misses which hit L2 ITLB or VHPT"}, #define PME_ITA2_L1I_EAR_TLB_VHPT 324 { "L1I_EAR_TLB_VHPT", {0x20243}, 0xf0, 1, {0xf00001}, "L1I EAR TLB -- L1 ITLB Misses which hit VHPT"}, #define PME_ITA2_L1I_EAR_TLB_VHPT_OR_FAULT 325 { "L1I_EAR_TLB_VHPT_OR_FAULT", {0x60243}, 0xf0, 1, {0xf00001}, "L1I EAR TLB -- L1 ITLB Misses which hit VHPT or produce a software fault"}, #define PME_ITA2_L1I_FETCH_ISB_HIT 326 { "L1I_FETCH_ISB_HIT", {0x66}, 0xf0, 1, {0xf00001}, "\"Just-In-Time\" Instruction Fetch Hitting in and Being Bypassed from ISB"}, #define PME_ITA2_L1I_FETCH_RAB_HIT 327 { "L1I_FETCH_RAB_HIT", {0x65}, 0xf0, 1, {0xf00001}, "Instruction Fetch Hitting in RAB"}, #define PME_ITA2_L1I_FILLS 328 { "L1I_FILLS", {0x41}, 0xf0, 1, {0xf00001}, "L1 Instruction Cache Fills"}, #define PME_ITA2_L1I_PREFETCHES 329 { "L1I_PREFETCHES", {0x44}, 0xf0, 1, {0xf00001}, "L1 Instruction Prefetch Requests"}, #define PME_ITA2_L1I_PREFETCH_STALL_ALL 330 { "L1I_PREFETCH_STALL_ALL", {0x30067}, 0xf0, 1, {0xf00000}, "Prefetch Pipeline Stalls -- Number of clocks prefetch pipeline is stalled"}, #define PME_ITA2_L1I_PREFETCH_STALL_FLOW 331 { "L1I_PREFETCH_STALL_FLOW", {0x20067}, 0xf0, 1, {0xf00000}, "Prefetch Pipeline Stalls -- Number of clocks flow is not asserted"}, #define PME_ITA2_L1I_PURGE 332 { "L1I_PURGE", {0x4b}, 0xf0, 1, {0xf00001}, "L1ITLB Purges Handled by L1I"}, #define PME_ITA2_L1I_PVAB_OVERFLOW 333 { "L1I_PVAB_OVERFLOW", {0x69}, 0xf0, 1, {0xf00000}, "PVAB Overflow"}, #define PME_ITA2_L1I_RAB_ALMOST_FULL 334 { "L1I_RAB_ALMOST_FULL", {0x64}, 0xf0, 1, {0xf00000}, "Is RAB Almost Full?"}, #define PME_ITA2_L1I_RAB_FULL 335 { "L1I_RAB_FULL", {0x60}, 0xf0, 1, {0xf00000}, "Is RAB Full?"}, #define PME_ITA2_L1I_READS 336 { "L1I_READS", {0x40}, 0xf0, 1, {0xf00001}, "L1 Instruction Cache Reads"}, #define PME_ITA2_L1I_SNOOP 337 { "L1I_SNOOP", {0x4a}, 0xf0, 1, {0xf00007}, "Snoop Requests Handled by L1I"}, #define PME_ITA2_L1I_STRM_PREFETCHES 338 { "L1I_STRM_PREFETCHES", {0x5f}, 0xf0, 1, {0xf00001}, "L1 Instruction Cache Line Prefetch Requests"}, #define PME_ITA2_L2DTLB_MISSES 339 { "L2DTLB_MISSES", {0xc1}, 0xf0, 4, {0x5010007}, "L2DTLB Misses"}, #define PME_ITA2_L2_BAD_LINES_SELECTED_ANY 340 { "L2_BAD_LINES_SELECTED_ANY", {0xb9}, 0xf0, 4, {0x4320007}, "Valid Line Replaced When Invalid Line Is Available -- Valid line replaced when invalid line is available"}, #define PME_ITA2_L2_BYPASS_L2_DATA1 341 { "L2_BYPASS_L2_DATA1", {0xb8}, 0xf0, 1, {0x4320007}, "Count L2 Bypasses -- Count only L2 data bypasses (L1D to L2A)"}, #define PME_ITA2_L2_BYPASS_L2_DATA2 342 { "L2_BYPASS_L2_DATA2", {0x100b8}, 0xf0, 1, {0x4320007}, "Count L2 Bypasses -- Count only L2 data bypasses (L1W to L2I)"}, #define PME_ITA2_L2_BYPASS_L2_INST1 343 { "L2_BYPASS_L2_INST1", {0x400b8}, 0xf0, 1, {0x4320007}, "Count L2 Bypasses -- Count only L2 instruction bypasses (L1D to L2A)"}, #define PME_ITA2_L2_BYPASS_L2_INST2 344 { "L2_BYPASS_L2_INST2", {0x500b8}, 0xf0, 1, {0x4320007}, "Count L2 Bypasses -- Count only L2 instruction bypasses (L1W to L2I)"}, #define PME_ITA2_L2_BYPASS_L3_DATA1 345 { "L2_BYPASS_L3_DATA1", {0x200b8}, 0xf0, 1, {0x4320007}, "Count L2 Bypasses -- Count only L3 data bypasses (L1D to L2A)"}, #define PME_ITA2_L2_BYPASS_L3_INST1 346 { "L2_BYPASS_L3_INST1", {0x600b8}, 0xf0, 1, {0x4320007}, "Count L2 Bypasses -- Count only L3 instruction bypasses (L1D to L2A)"}, #define PME_ITA2_L2_DATA_REFERENCES_L2_ALL 347 { "L2_DATA_REFERENCES_L2_ALL", {0x300b2}, 0xf0, 4, {0x4120007}, "Data Read/Write Access to L2 -- count both read and write operations (semaphores will count as 2)"}, #define PME_ITA2_L2_DATA_REFERENCES_L2_DATA_READS 348 { "L2_DATA_REFERENCES_L2_DATA_READS", {0x100b2}, 0xf0, 4, {0x4120007}, "Data Read/Write Access to L2 -- count only data read and semaphore operations."}, #define PME_ITA2_L2_DATA_REFERENCES_L2_DATA_WRITES 349 { "L2_DATA_REFERENCES_L2_DATA_WRITES", {0x200b2}, 0xf0, 4, {0x4120007}, "Data Read/Write Access to L2 -- count only data write and semaphore operations"}, #define PME_ITA2_L2_FILLB_FULL_THIS 350 { "L2_FILLB_FULL_THIS", {0xbf}, 0xf0, 1, {0x4520000}, "L2D Fill Buffer Is Full -- L2 Fill buffer is full"}, #define PME_ITA2_L2_FORCE_RECIRC_ANY 351 { "L2_FORCE_RECIRC_ANY", {0xb4}, 0x10, 4, {0x4220007}, "Forced Recirculates -- count forced recirculates regardless of cause. SMC_HIT, TRAN_PREF & SNP_OR_L3 will not be included here."}, #define PME_ITA2_L2_FORCE_RECIRC_FILL_HIT 352 { "L2_FORCE_RECIRC_FILL_HIT", {0x900b4}, 0x10, 4, {0x4220007}, "Forced Recirculates -- count only those caused by an L2 miss which hit in the fill buffer."}, #define PME_ITA2_L2_FORCE_RECIRC_FRC_RECIRC 353 { "L2_FORCE_RECIRC_FRC_RECIRC", {0xe00b4}, 0x10, 4, {0x4220007}, "Forced Recirculates -- caused by an L2 miss when a force recirculate already existed"}, #define PME_ITA2_L2_FORCE_RECIRC_IPF_MISS 354 { "L2_FORCE_RECIRC_IPF_MISS", {0xa00b4}, 0x10, 4, {0x4220007}, "Forced Recirculates -- caused by L2 miss when instruction prefetch buffer miss already existed"}, #define PME_ITA2_L2_FORCE_RECIRC_L1W 355 { "L2_FORCE_RECIRC_L1W", {0x200b4}, 0x10, 4, {0x4220007}, "Forced Recirculates -- count only those caused by forced limbo"}, #define PME_ITA2_L2_FORCE_RECIRC_OZQ_MISS 356 { "L2_FORCE_RECIRC_OZQ_MISS", {0xc00b4}, 0x10, 4, {0x4220007}, "Forced Recirculates -- caused by an L2 miss when an OZQ miss already existed"}, #define PME_ITA2_L2_FORCE_RECIRC_SAME_INDEX 357 { "L2_FORCE_RECIRC_SAME_INDEX", {0xd00b4}, 0x10, 4, {0x4220007}, "Forced Recirculates -- caused by an L2 miss when a miss to the same index already existed"}, #define PME_ITA2_L2_FORCE_RECIRC_SMC_HIT 358 { "L2_FORCE_RECIRC_SMC_HIT", {0x100b4}, 0x10, 4, {0x4220007}, "Forced Recirculates -- count only those caused by SMC hits due to an ifetch and load to same cache line or a pending WT store"}, #define PME_ITA2_L2_FORCE_RECIRC_SNP_OR_L3 359 { "L2_FORCE_RECIRC_SNP_OR_L3", {0x600b4}, 0x10, 4, {0x4220007}, "Forced Recirculates -- count only those caused by a snoop or L3 issue"}, #define PME_ITA2_L2_FORCE_RECIRC_TAG_NOTOK 360 { "L2_FORCE_RECIRC_TAG_NOTOK", {0x400b4}, 0x10, 4, {0x4220007}, "Forced Recirculates -- count only those caused by L2 hits caused by in flight snoops, stores with a sibling miss to the same index, sibling probe to the same line or pending sync.ia instructions."}, #define PME_ITA2_L2_FORCE_RECIRC_TRAN_PREF 361 { "L2_FORCE_RECIRC_TRAN_PREF", {0x500b4}, 0x10, 4, {0x4220007}, "Forced Recirculates -- count only those caused by transforms to prefetches"}, #define PME_ITA2_L2_FORCE_RECIRC_VIC_BUF_FULL 362 { "L2_FORCE_RECIRC_VIC_BUF_FULL", {0xb00b4}, 0x10, 4, {0x4220007}, "Forced Recirculates -- count only those caused by an L2 miss with victim buffer full"}, #define PME_ITA2_L2_FORCE_RECIRC_VIC_PEND 363 { "L2_FORCE_RECIRC_VIC_PEND", {0x800b4}, 0x10, 4, {0x4220007}, "Forced Recirculates -- count only those caused by an L2 miss with pending victim"}, #define PME_ITA2_L2_GOT_RECIRC_IFETCH_ANY 364 { "L2_GOT_RECIRC_IFETCH_ANY", {0x800ba}, 0xf0, 1, {0x4420007}, "Instruction Fetch Recirculates Received by L2D -- Instruction fetch recirculates received by L2"}, #define PME_ITA2_L2_GOT_RECIRC_OZQ_ACC 365 { "L2_GOT_RECIRC_OZQ_ACC", {0xb6}, 0xf0, 1, {0x4220007}, "Counts Number of OZQ Accesses Recirculated to L1D"}, #define PME_ITA2_L2_IFET_CANCELS_ANY 366 { "L2_IFET_CANCELS_ANY", {0xa1}, 0xf0, 1, {0x4020007}, "Instruction Fetch Cancels by the L2 -- total instruction fetch cancels by L2"}, #define PME_ITA2_L2_IFET_CANCELS_BYPASS 367 { "L2_IFET_CANCELS_BYPASS", {0x200a1}, 0xf0, 1, {0x4020007}, "Instruction Fetch Cancels by the L2 -- ifetch cancels due to bypassing"}, #define PME_ITA2_L2_IFET_CANCELS_CHG_PRIO 368 { "L2_IFET_CANCELS_CHG_PRIO", {0xc00a1}, 0xf0, 1, {0x4020007}, "Instruction Fetch Cancels by the L2 -- ifetch cancels due to change priority"}, #define PME_ITA2_L2_IFET_CANCELS_DATA_RD 369 { "L2_IFET_CANCELS_DATA_RD", {0x700a1}, 0xf0, 1, {0x4020007}, "Instruction Fetch Cancels by the L2 -- ifetch/prefetch cancels due to a data read"}, #define PME_ITA2_L2_IFET_CANCELS_DIDNT_RECIR 370 { "L2_IFET_CANCELS_DIDNT_RECIR", {0x400a1}, 0xf0, 1, {0x4020007}, "Instruction Fetch Cancels by the L2 -- ifetch cancels because it did not recirculate"}, #define PME_ITA2_L2_IFET_CANCELS_IFETCH_BYP 371 { "L2_IFET_CANCELS_IFETCH_BYP", {0xd00a1}, 0xf0, 1, {0x4020007}, "Instruction Fetch Cancels by the L2 -- due to ifetch bypass during last clock"}, #define PME_ITA2_L2_IFET_CANCELS_PREEMPT 372 { "L2_IFET_CANCELS_PREEMPT", {0x800a1}, 0xf0, 1, {0x4020007}, "Instruction Fetch Cancels by the L2 -- ifetch cancels due to preempts"}, #define PME_ITA2_L2_IFET_CANCELS_RECIR_OVER_SUB 373 { "L2_IFET_CANCELS_RECIR_OVER_SUB", {0x500a1}, 0xf0, 1, {0x4020007}, "Instruction Fetch Cancels by the L2 -- ifetch cancels because of recirculate oversubscription"}, #define PME_ITA2_L2_IFET_CANCELS_ST_FILL_WB 374 { "L2_IFET_CANCELS_ST_FILL_WB", {0x600a1}, 0xf0, 1, {0x4020007}, "Instruction Fetch Cancels by the L2 -- ifetch cancels due to a store or fill or write back"}, #define PME_ITA2_L2_INST_DEMAND_READS 375 { "L2_INST_DEMAND_READS", {0x42}, 0xf0, 1, {0xf00001}, "L2 Instruction Demand Fetch Requests"}, #define PME_ITA2_L2_INST_PREFETCHES 376 { "L2_INST_PREFETCHES", {0x45}, 0xf0, 1, {0xf00001}, "L2 Instruction Prefetch Requests"}, #define PME_ITA2_L2_ISSUED_RECIRC_IFETCH_ANY 377 { "L2_ISSUED_RECIRC_IFETCH_ANY", {0x800b9}, 0xf0, 1, {0x4420007}, "Instruction Fetch Recirculates Issued by L2 -- Instruction fetch recirculates issued by L2"}, #define PME_ITA2_L2_ISSUED_RECIRC_OZQ_ACC 378 { "L2_ISSUED_RECIRC_OZQ_ACC", {0xb5}, 0xf0, 1, {0x4220007}, "Count Number of Times a Recirculate Issue Was Attempted and Not Preempted"}, #define PME_ITA2_L2_L3ACCESS_CANCEL_ANY 379 { "L2_L3ACCESS_CANCEL_ANY", {0x900b0}, 0x10, 1, {0x4120007}, "Canceled L3 Accesses -- count cancels due to any reason. This umask will count more than the sum of all the other umasks. It will count things that weren't committed accesses when they reached L1w, but the L2 attempted to bypass them to the L3 anyway (speculatively). This will include accesses made repeatedly while the main pipeline is stalled and the L1d is attempting to recirculate an access down the L1d pipeline. Thus, an access could get counted many times before it really does get bypassed to the L3. It is a measure of how many times we asserted a request to the L3 but didn't confirm it."}, #define PME_ITA2_L2_L3ACCESS_CANCEL_DFETCH 380 { "L2_L3ACCESS_CANCEL_DFETCH", {0xa00b0}, 0x10, 1, {0x4120007}, "Canceled L3 Accesses -- data fetches"}, #define PME_ITA2_L2_L3ACCESS_CANCEL_EBL_REJECT 381 { "L2_L3ACCESS_CANCEL_EBL_REJECT", {0x800b0}, 0x10, 1, {0x4120007}, "Canceled L3 Accesses -- ebl rejects"}, #define PME_ITA2_L2_L3ACCESS_CANCEL_FILLD_FULL 382 { "L2_L3ACCESS_CANCEL_FILLD_FULL", {0x200b0}, 0x10, 1, {0x4120007}, "Canceled L3 Accesses -- filld being full"}, #define PME_ITA2_L2_L3ACCESS_CANCEL_IFETCH 383 { "L2_L3ACCESS_CANCEL_IFETCH", {0xb00b0}, 0xf0, 1, {0x4120007}, "Canceled L3 Accesses -- instruction fetches"}, #define PME_ITA2_L2_L3ACCESS_CANCEL_INV_L3_BYP 384 { "L2_L3ACCESS_CANCEL_INV_L3_BYP", {0x600b0}, 0x10, 1, {0x4120007}, "Canceled L3 Accesses -- invalid L3 bypasses"}, #define PME_ITA2_L2_L3ACCESS_CANCEL_SPEC_L3_BYP 385 { "L2_L3ACCESS_CANCEL_SPEC_L3_BYP", {0x100b0}, 0x10, 1, {0x4120007}, "Canceled L3 Accesses -- speculative L3 bypasses"}, #define PME_ITA2_L2_L3ACCESS_CANCEL_UC_BLOCKED 386 { "L2_L3ACCESS_CANCEL_UC_BLOCKED", {0x500b0}, 0x10, 1, {0x4120007}, "Canceled L3 Accesses -- Uncacheable blocked L3 Accesses"}, #define PME_ITA2_L2_MISSES 387 { "L2_MISSES", {0xcb}, 0xf0, 1, {0xf00007}, "L2 Misses"}, #define PME_ITA2_L2_OPS_ISSUED_FP_LOAD 388 { "L2_OPS_ISSUED_FP_LOAD", {0x900b8}, 0xf0, 4, {0x4420007}, "Different Operations Issued by L2D -- Count only valid floating point loads"}, #define PME_ITA2_L2_OPS_ISSUED_INT_LOAD 389 { "L2_OPS_ISSUED_INT_LOAD", {0x800b8}, 0xf0, 4, {0x4420007}, "Different Operations Issued by L2D -- Count only valid integer loads"}, #define PME_ITA2_L2_OPS_ISSUED_NST_NLD 390 { "L2_OPS_ISSUED_NST_NLD", {0xc00b8}, 0xf0, 4, {0x4420007}, "Different Operations Issued by L2D -- Count only valid non-load, no-store accesses"}, #define PME_ITA2_L2_OPS_ISSUED_RMW 391 { "L2_OPS_ISSUED_RMW", {0xa00b8}, 0xf0, 4, {0x4420007}, "Different Operations Issued by L2D -- Count only valid read_modify_write stores"}, #define PME_ITA2_L2_OPS_ISSUED_STORE 392 { "L2_OPS_ISSUED_STORE", {0xb00b8}, 0xf0, 4, {0x4420007}, "Different Operations Issued by L2D -- Count only valid non-read_modify_write stores"}, #define PME_ITA2_L2_OZDB_FULL_THIS 393 { "L2_OZDB_FULL_THIS", {0xbd}, 0xf0, 1, {0x4520000}, "L2 OZ Data Buffer Is Full -- L2 OZ Data Buffer is full"}, #define PME_ITA2_L2_OZQ_ACQUIRE 394 { "L2_OZQ_ACQUIRE", {0xa2}, 0xf0, 1, {0x4020000}, "Clocks With Acquire Ordering Attribute Existed in L2 OZQ"}, #define PME_ITA2_L2_OZQ_CANCELS0_ANY 395 { "L2_OZQ_CANCELS0_ANY", {0xa0}, 0xf0, 4, {0x4020007}, "L2 OZQ Cancels (Late or Any) -- counts the total OZ Queue cancels"}, #define PME_ITA2_L2_OZQ_CANCELS0_LATE_ACQUIRE 396 { "L2_OZQ_CANCELS0_LATE_ACQUIRE", {0x300a0}, 0xf0, 4, {0x4020007}, "L2 OZQ Cancels (Late or Any) -- counts the late cancels caused by acquires"}, #define PME_ITA2_L2_OZQ_CANCELS0_LATE_BYP_EFFRELEASE 397 { "L2_OZQ_CANCELS0_LATE_BYP_EFFRELEASE", {0x400a0}, 0xf0, 4, {0x4020007}, "L2 OZQ Cancels (Late or Any) -- counts the late cancels caused by L1D to L2A bypass effective releases"}, #define PME_ITA2_L2_OZQ_CANCELS0_LATE_RELEASE 398 { "L2_OZQ_CANCELS0_LATE_RELEASE", {0x200a0}, 0xf0, 4, {0x4020007}, "L2 OZQ Cancels (Late or Any) -- counts the late cancels caused by releases"}, #define PME_ITA2_L2_OZQ_CANCELS0_LATE_SPEC_BYP 399 { "L2_OZQ_CANCELS0_LATE_SPEC_BYP", {0x100a0}, 0xf0, 4, {0x4020007}, "L2 OZQ Cancels (Late or Any) -- counts the late cancels caused by speculative bypasses"}, #define PME_ITA2_L2_OZQ_CANCELS1_BANK_CONF 400 { "L2_OZQ_CANCELS1_BANK_CONF", {0x100ac}, 0xf0, 4, {0x4020007}, "L2 OZQ Cancels (Specific Reason Set 1) -- bank conflicts"}, #define PME_ITA2_L2_OZQ_CANCELS1_CANC_L2M_ST 401 { "L2_OZQ_CANCELS1_CANC_L2M_ST", {0x600ac}, 0xf0, 4, {0x4020007}, "L2 OZQ Cancels (Specific Reason Set 1) -- caused by a canceled store in L2M"}, #define PME_ITA2_L2_OZQ_CANCELS1_CCV 402 { "L2_OZQ_CANCELS1_CCV", {0x900ac}, 0xf0, 4, {0x4020007}, "L2 OZQ Cancels (Specific Reason Set 1) -- a ccv"}, #define PME_ITA2_L2_OZQ_CANCELS1_ECC 403 { "L2_OZQ_CANCELS1_ECC", {0xf00ac}, 0xf0, 4, {0x4020007}, "L2 OZQ Cancels (Specific Reason Set 1) -- ECC hardware detecting a problem"}, #define PME_ITA2_L2_OZQ_CANCELS1_HPW_IFETCH_CONF 404 { "L2_OZQ_CANCELS1_HPW_IFETCH_CONF", {0x500ac}, 0xf0, 4, {0x4020007}, "L2 OZQ Cancels (Specific Reason Set 1) -- a ifetch conflict (canceling HPW?)"}, #define PME_ITA2_L2_OZQ_CANCELS1_L1DF_L2M 405 { "L2_OZQ_CANCELS1_L1DF_L2M", {0xe00ac}, 0xf0, 4, {0x4020007}, "L2 OZQ Cancels (Specific Reason Set 1) -- L1D fill in L2M"}, #define PME_ITA2_L2_OZQ_CANCELS1_L1_FILL_CONF 406 { "L2_OZQ_CANCELS1_L1_FILL_CONF", {0x700ac}, 0xf0, 4, {0x4020007}, "L2 OZQ Cancels (Specific Reason Set 1) -- an L1 fill conflict"}, #define PME_ITA2_L2_OZQ_CANCELS1_L2A_ST_MAT 407 { "L2_OZQ_CANCELS1_L2A_ST_MAT", {0xd00ac}, 0xf0, 4, {0x4020007}, "L2 OZQ Cancels (Specific Reason Set 1) -- a store match in L2A"}, #define PME_ITA2_L2_OZQ_CANCELS1_L2D_ST_MAT 408 { "L2_OZQ_CANCELS1_L2D_ST_MAT", {0x200ac}, 0xf0, 4, {0x4020007}, "L2 OZQ Cancels (Specific Reason Set 1) -- a store match in L2D"}, #define PME_ITA2_L2_OZQ_CANCELS1_L2M_ST_MAT 409 { "L2_OZQ_CANCELS1_L2M_ST_MAT", {0xb00ac}, 0xf0, 4, {0x4020007}, "L2 OZQ Cancels (Specific Reason Set 1) -- a store match in L2M"}, #define PME_ITA2_L2_OZQ_CANCELS1_MFA 410 { "L2_OZQ_CANCELS1_MFA", {0xc00ac}, 0xf0, 4, {0x4020007}, "L2 OZQ Cancels (Specific Reason Set 1) -- a memory fence instruction"}, #define PME_ITA2_L2_OZQ_CANCELS1_REL 411 { "L2_OZQ_CANCELS1_REL", {0xac}, 0xf0, 4, {0x4020007}, "L2 OZQ Cancels (Specific Reason Set 1) -- caused by release"}, #define PME_ITA2_L2_OZQ_CANCELS1_SEM 412 { "L2_OZQ_CANCELS1_SEM", {0xa00ac}, 0xf0, 4, {0x4020007}, "L2 OZQ Cancels (Specific Reason Set 1) -- a semaphore"}, #define PME_ITA2_L2_OZQ_CANCELS1_ST_FILL_CONF 413 { "L2_OZQ_CANCELS1_ST_FILL_CONF", {0x800ac}, 0xf0, 4, {0x4020007}, "L2 OZQ Cancels (Specific Reason Set 1) -- a store fill conflict"}, #define PME_ITA2_L2_OZQ_CANCELS1_SYNC 414 { "L2_OZQ_CANCELS1_SYNC", {0x400ac}, 0xf0, 4, {0x4020007}, "L2 OZQ Cancels (Specific Reason Set 1) -- caused by sync.i"}, #define PME_ITA2_L2_OZQ_CANCELS2_ACQ 415 { "L2_OZQ_CANCELS2_ACQ", {0x400a8}, 0xf0, 4, {0x4020007}, "L2 OZQ Cancels (Specific Reason Set 2) -- caused by an acquire"}, #define PME_ITA2_L2_OZQ_CANCELS2_CANC_L2C_ST 416 { "L2_OZQ_CANCELS2_CANC_L2C_ST", {0x100a8}, 0xf0, 4, {0x4020007}, "L2 OZQ Cancels (Specific Reason Set 2) -- caused by a canceled store in L2C"}, #define PME_ITA2_L2_OZQ_CANCELS2_CANC_L2D_ST 417 { "L2_OZQ_CANCELS2_CANC_L2D_ST", {0xd00a8}, 0xf0, 4, {0x4020007}, "L2 OZQ Cancels (Specific Reason Set 2) -- caused by a canceled store in L2D"}, #define PME_ITA2_L2_OZQ_CANCELS2_DIDNT_RECIRC 418 { "L2_OZQ_CANCELS2_DIDNT_RECIRC", {0x900a8}, 0xf0, 4, {0x4020007}, "L2 OZQ Cancels (Specific Reason Set 2) -- caused because it did not recirculate"}, #define PME_ITA2_L2_OZQ_CANCELS2_D_IFET 419 { "L2_OZQ_CANCELS2_D_IFET", {0xf00a8}, 0xf0, 4, {0x4020007}, "L2 OZQ Cancels (Specific Reason Set 2) -- a demand ifetch"}, #define PME_ITA2_L2_OZQ_CANCELS2_L2C_ST_MAT 420 { "L2_OZQ_CANCELS2_L2C_ST_MAT", {0x200a8}, 0xf0, 4, {0x4020007}, "L2 OZQ Cancels (Specific Reason Set 2) -- a store match in L2C"}, #define PME_ITA2_L2_OZQ_CANCELS2_L2FILL_ST_CONF 421 { "L2_OZQ_CANCELS2_L2FILL_ST_CONF", {0x800a8}, 0xf0, 4, {0x4020007}, "L2 OZQ Cancels (Specific Reason Set 2) -- a L2fill and store conflict in L2C"}, #define PME_ITA2_L2_OZQ_CANCELS2_OVER_SUB 422 { "L2_OZQ_CANCELS2_OVER_SUB", {0xc00a8}, 0xf0, 4, {0x4020007}, "L2 OZQ Cancels (Specific Reason Set 2) -- oversubscription"}, #define PME_ITA2_L2_OZQ_CANCELS2_OZ_DATA_CONF 423 { "L2_OZQ_CANCELS2_OZ_DATA_CONF", {0x600a8}, 0xf0, 4, {0x4020007}, "L2 OZQ Cancels (Specific Reason Set 2) -- an OZ data conflict"}, #define PME_ITA2_L2_OZQ_CANCELS2_READ_WB_CONF 424 { "L2_OZQ_CANCELS2_READ_WB_CONF", {0x500a8}, 0xf0, 4, {0x4020007}, "L2 OZQ Cancels (Specific Reason Set 2) -- a write back conflict (canceling read?)"}, #define PME_ITA2_L2_OZQ_CANCELS2_RECIRC_OVER_SUB 425 { "L2_OZQ_CANCELS2_RECIRC_OVER_SUB", {0xa8}, 0xf0, 4, {0x4020007}, "L2 OZQ Cancels (Specific Reason Set 2) -- caused by a recirculate oversubscription"}, #define PME_ITA2_L2_OZQ_CANCELS2_SCRUB 426 { "L2_OZQ_CANCELS2_SCRUB", {0x300a8}, 0xf0, 4, {0x4020007}, "L2 OZQ Cancels (Specific Reason Set 2) -- 32/64 byte HPW/L2D fill which needs scrub"}, #define PME_ITA2_L2_OZQ_CANCELS2_WEIRD 427 { "L2_OZQ_CANCELS2_WEIRD", {0xa00a8}, 0xf0, 4, {0x4020007}, "L2 OZQ Cancels (Specific Reason Set 2) -- counts the cancels caused by attempted 5-cycle bypasses for non-aligned accesses and bypasses blocking recirculates for too long"}, #define PME_ITA2_L2_OZQ_FULL_THIS 428 { "L2_OZQ_FULL_THIS", {0xbc}, 0xf0, 1, {0x4520000}, "L2D OZQ Is Full -- L2D OZQ is full"}, #define PME_ITA2_L2_OZQ_RELEASE 429 { "L2_OZQ_RELEASE", {0xa3}, 0xf0, 1, {0x4020000}, "Clocks With Release Ordering Attribute Existed in L2 OZQ"}, #define PME_ITA2_L2_REFERENCES 430 { "L2_REFERENCES", {0xb1}, 0xf0, 4, {0x4120007}, "Requests Made To L2"}, #define PME_ITA2_L2_STORE_HIT_SHARED_ANY 431 { "L2_STORE_HIT_SHARED_ANY", {0xba}, 0xf0, 2, {0x4320007}, "Store Hit a Shared Line -- Store hit a shared line"}, #define PME_ITA2_L2_SYNTH_PROBE 432 { "L2_SYNTH_PROBE", {0xb7}, 0xf0, 1, {0x4220007}, "Synthesized Probe"}, #define PME_ITA2_L2_VICTIMB_FULL_THIS 433 { "L2_VICTIMB_FULL_THIS", {0xbe}, 0xf0, 1, {0x4520000}, "L2D Victim Buffer Is Full -- L2D victim buffer is full"}, #define PME_ITA2_L3_LINES_REPLACED 434 { "L3_LINES_REPLACED", {0xdf}, 0xf0, 1, {0xf00000}, "L3 Cache Lines Replaced"}, #define PME_ITA2_L3_MISSES 435 { "L3_MISSES", {0xdc}, 0xf0, 1, {0xf00007}, "L3 Misses"}, #define PME_ITA2_L3_READS_ALL_ALL 436 { "L3_READS_ALL_ALL", {0xf00dd}, 0xf0, 1, {0xf00007}, "L3 Reads -- L3 Read References"}, #define PME_ITA2_L3_READS_ALL_HIT 437 { "L3_READS_ALL_HIT", {0xd00dd}, 0xf0, 1, {0xf00007}, "L3 Reads -- L3 Read Hits"}, #define PME_ITA2_L3_READS_ALL_MISS 438 { "L3_READS_ALL_MISS", {0xe00dd}, 0xf0, 1, {0xf00007}, "L3 Reads -- L3 Read Misses"}, #define PME_ITA2_L3_READS_DATA_READ_ALL 439 { "L3_READS_DATA_READ_ALL", {0xb00dd}, 0xf0, 1, {0xf00007}, "L3 Reads -- L3 Load References (excludes reads for ownership used to satisfy stores)"}, #define PME_ITA2_L3_READS_DATA_READ_HIT 440 { "L3_READS_DATA_READ_HIT", {0x900dd}, 0xf0, 1, {0xf00007}, "L3 Reads -- L3 Load Hits (excludes reads for ownership used to satisfy stores)"}, #define PME_ITA2_L3_READS_DATA_READ_MISS 441 { "L3_READS_DATA_READ_MISS", {0xa00dd}, 0xf0, 1, {0xf00007}, "L3 Reads -- L3 Load Misses (excludes reads for ownership used to satisfy stores)"}, #define PME_ITA2_L3_READS_DINST_FETCH_ALL 442 { "L3_READS_DINST_FETCH_ALL", {0x300dd}, 0xf0, 1, {0xf00007}, "L3 Reads -- L3 Demand Instruction References"}, #define PME_ITA2_L3_READS_DINST_FETCH_HIT 443 { "L3_READS_DINST_FETCH_HIT", {0x100dd}, 0xf0, 1, {0xf00007}, "L3 Reads -- L3 Demand Instruction Fetch Hits"}, #define PME_ITA2_L3_READS_DINST_FETCH_MISS 444 { "L3_READS_DINST_FETCH_MISS", {0x200dd}, 0xf0, 1, {0xf00007}, "L3 Reads -- L3 Demand Instruction Fetch Misses"}, #define PME_ITA2_L3_READS_INST_FETCH_ALL 445 { "L3_READS_INST_FETCH_ALL", {0x700dd}, 0xf0, 1, {0xf00007}, "L3 Reads -- L3 Instruction Fetch and Prefetch References"}, #define PME_ITA2_L3_READS_INST_FETCH_HIT 446 { "L3_READS_INST_FETCH_HIT", {0x500dd}, 0xf0, 1, {0xf00007}, "L3 Reads -- L3 Instruction Fetch and Prefetch Hits"}, #define PME_ITA2_L3_READS_INST_FETCH_MISS 447 { "L3_READS_INST_FETCH_MISS", {0x600dd}, 0xf0, 1, {0xf00007}, "L3 Reads -- L3 Instruction Fetch and Prefetch Misses"}, #define PME_ITA2_L3_REFERENCES 448 { "L3_REFERENCES", {0xdb}, 0xf0, 1, {0xf00007}, "L3 References"}, #define PME_ITA2_L3_WRITES_ALL_ALL 449 { "L3_WRITES_ALL_ALL", {0xf00de}, 0xf0, 1, {0xf00007}, "L3 Writes -- L3 Write References"}, #define PME_ITA2_L3_WRITES_ALL_HIT 450 { "L3_WRITES_ALL_HIT", {0xd00de}, 0xf0, 1, {0xf00007}, "L3 Writes -- L3 Write Hits"}, #define PME_ITA2_L3_WRITES_ALL_MISS 451 { "L3_WRITES_ALL_MISS", {0xe00de}, 0xf0, 1, {0xf00007}, "L3 Writes -- L3 Write Misses"}, #define PME_ITA2_L3_WRITES_DATA_WRITE_ALL 452 { "L3_WRITES_DATA_WRITE_ALL", {0x700de}, 0xf0, 1, {0xf00007}, "L3 Writes -- L3 Store References (excludes L2 write backs, includes L3 read for ownership requests that satisfy stores)"}, #define PME_ITA2_L3_WRITES_DATA_WRITE_HIT 453 { "L3_WRITES_DATA_WRITE_HIT", {0x500de}, 0xf0, 1, {0xf00007}, "L3 Writes -- L3 Store Hits (excludes L2 write backs, includes L3 read for ownership requests that satisfy stores)"}, #define PME_ITA2_L3_WRITES_DATA_WRITE_MISS 454 { "L3_WRITES_DATA_WRITE_MISS", {0x600de}, 0xf0, 1, {0xf00007}, "L3 Writes -- L3 Store Misses (excludes L2 write backs, includes L3 read for ownership requests that satisfy stores)"}, #define PME_ITA2_L3_WRITES_L2_WB_ALL 455 { "L3_WRITES_L2_WB_ALL", {0xb00de}, 0xf0, 1, {0xf00007}, "L3 Writes -- L2 Write Back References"}, #define PME_ITA2_L3_WRITES_L2_WB_HIT 456 { "L3_WRITES_L2_WB_HIT", {0x900de}, 0xf0, 1, {0xf00007}, "L3 Writes -- L2 Write Back Hits"}, #define PME_ITA2_L3_WRITES_L2_WB_MISS 457 { "L3_WRITES_L2_WB_MISS", {0xa00de}, 0xf0, 1, {0xf00007}, "L3 Writes -- L2 Write Back Misses"}, #define PME_ITA2_LOADS_RETIRED 458 { "LOADS_RETIRED", {0xcd}, 0xf0, 4, {0x5310007}, "Retired Loads"}, #define PME_ITA2_MEM_READ_CURRENT_ANY 459 { "MEM_READ_CURRENT_ANY", {0x30089}, 0xf0, 1, {0xf00000}, "Current Mem Read Transactions On Bus -- CPU or non-CPU (all transactions)."}, #define PME_ITA2_MEM_READ_CURRENT_IO 460 { "MEM_READ_CURRENT_IO", {0x10089}, 0xf0, 1, {0xf00000}, "Current Mem Read Transactions On Bus -- non-CPU priority agents"}, #define PME_ITA2_MISALIGNED_LOADS_RETIRED 461 { "MISALIGNED_LOADS_RETIRED", {0xce}, 0xf0, 4, {0x5310007}, "Retired Misaligned Load Instructions"}, #define PME_ITA2_MISALIGNED_STORES_RETIRED 462 { "MISALIGNED_STORES_RETIRED", {0xd2}, 0xf0, 2, {0x5410007}, "Retired Misaligned Store Instructions"}, #define PME_ITA2_NOPS_RETIRED 463 { "NOPS_RETIRED", {0x50}, 0xf0, 6, {0xf00003}, "Retired NOP Instructions"}, #define PME_ITA2_PREDICATE_SQUASHED_RETIRED 464 { "PREDICATE_SQUASHED_RETIRED", {0x51}, 0xf0, 6, {0xf00003}, "Instructions Squashed Due to Predicate Off"}, #define PME_ITA2_RSE_CURRENT_REGS_2_TO_0 465 { "RSE_CURRENT_REGS_2_TO_0", {0x2b}, 0xf0, 7, {0xf00000}, "Current RSE Registers (Bits 2:0)"}, #define PME_ITA2_RSE_CURRENT_REGS_5_TO_3 466 { "RSE_CURRENT_REGS_5_TO_3", {0x2a}, 0xf0, 7, {0xf00000}, "Current RSE Registers (Bits 5:3)"}, #define PME_ITA2_RSE_CURRENT_REGS_6 467 { "RSE_CURRENT_REGS_6", {0x26}, 0xf0, 1, {0xf00000}, "Current RSE Registers (Bit 6)"}, #define PME_ITA2_RSE_DIRTY_REGS_2_TO_0 468 { "RSE_DIRTY_REGS_2_TO_0", {0x29}, 0xf0, 7, {0xf00000}, "Dirty RSE Registers (Bits 2:0)"}, #define PME_ITA2_RSE_DIRTY_REGS_5_TO_3 469 { "RSE_DIRTY_REGS_5_TO_3", {0x28}, 0xf0, 7, {0xf00000}, "Dirty RSE Registers (Bits 5:3)"}, #define PME_ITA2_RSE_DIRTY_REGS_6 470 { "RSE_DIRTY_REGS_6", {0x24}, 0xf0, 1, {0xf00000}, "Dirty RSE Registers (Bit 6)"}, #define PME_ITA2_RSE_EVENT_RETIRED 471 { "RSE_EVENT_RETIRED", {0x32}, 0xf0, 1, {0xf00000}, "Retired RSE operations"}, #define PME_ITA2_RSE_REFERENCES_RETIRED_ALL 472 { "RSE_REFERENCES_RETIRED_ALL", {0x30020}, 0xf0, 2, {0xf00007}, "RSE Accesses -- Both RSE loads and stores will be counted."}, #define PME_ITA2_RSE_REFERENCES_RETIRED_LOAD 473 { "RSE_REFERENCES_RETIRED_LOAD", {0x10020}, 0xf0, 2, {0xf00007}, "RSE Accesses -- Only RSE loads will be counted."}, #define PME_ITA2_RSE_REFERENCES_RETIRED_STORE 474 { "RSE_REFERENCES_RETIRED_STORE", {0x20020}, 0xf0, 2, {0xf00007}, "RSE Accesses -- Only RSE stores will be counted."}, #define PME_ITA2_SERIALIZATION_EVENTS 475 { "SERIALIZATION_EVENTS", {0x53}, 0xf0, 1, {0xf00000}, "Number of srlz.i Instructions"}, #define PME_ITA2_STORES_RETIRED 476 { "STORES_RETIRED", {0xd1}, 0xf0, 2, {0x5410007}, "Retired Stores"}, #define PME_ITA2_SYLL_NOT_DISPERSED_ALL 477 { "SYLL_NOT_DISPERSED_ALL", {0xf004e}, 0xf0, 5, {0xf00001}, "Syllables Not Dispersed -- Counts all syllables not dispersed. NOTE: Any combination of b0000-b1111 is valid."}, #define PME_ITA2_SYLL_NOT_DISPERSED_EXPL 478 { "SYLL_NOT_DISPERSED_EXPL", {0x1004e}, 0xf0, 5, {0xf00001}, "Syllables Not Dispersed -- Count syllables not dispersed due to explicit stop bits. These consist of programmer specified architected S-bit and templates 1 and 5. Dispersal takes a 6-syllable (3-syllable) hit for every template 1/5 in bundle 0(1). Dispersal takes a 3-syllable (0 syllable) hit for every S-bit in bundle 0(1)"}, #define PME_ITA2_SYLL_NOT_DISPERSED_EXPL_OR_FE 479 { "SYLL_NOT_DISPERSED_EXPL_OR_FE", {0x5004e}, 0xf0, 5, {0xf00001}, "Syllables Not Dispersed -- Count syllables not dispersed due to explicit stop bits or front-end not providing valid bundles or providing valid illegal templates."}, #define PME_ITA2_SYLL_NOT_DISPERSED_EXPL_OR_FE_OR_MLI 480 { "SYLL_NOT_DISPERSED_EXPL_OR_FE_OR_MLI", {0xd004e}, 0xf0, 5, {0xf00001}, "Syllables Not Dispersed -- Count syllables not dispersed due to explicit stop bits or due to front-end not providing valid bundles or providing valid illegal templates or due to MLI bundle and resteers to non-0 syllable."}, #define PME_ITA2_SYLL_NOT_DISPERSED_EXPL_OR_IMPL 481 { "SYLL_NOT_DISPERSED_EXPL_OR_IMPL", {0x3004e}, 0xf0, 5, {0xf00001}, "Syllables Not Dispersed -- Count syllables not dispersed due to explicit/implicit stop bits."}, #define PME_ITA2_SYLL_NOT_DISPERSED_EXPL_OR_IMPL_OR_FE 482 { "SYLL_NOT_DISPERSED_EXPL_OR_IMPL_OR_FE", {0x7004e}, 0xf0, 5, {0xf00001}, "Syllables Not Dispersed -- Count syllables not dispersed due to explicit or implicit stop bits or due to front-end not providing valid bundles or providing valid illegal template."}, #define PME_ITA2_SYLL_NOT_DISPERSED_EXPL_OR_IMPL_OR_MLI 483 { "SYLL_NOT_DISPERSED_EXPL_OR_IMPL_OR_MLI", {0xb004e}, 0xf0, 5, {0xf00001}, "Syllables Not Dispersed -- Count syllables not dispersed due to explicit or implicit stop bits or due to MLI bundle and resteers to non-0 syllable."}, #define PME_ITA2_SYLL_NOT_DISPERSED_EXPL_OR_MLI 484 { "SYLL_NOT_DISPERSED_EXPL_OR_MLI", {0x9004e}, 0xf0, 5, {0xf00001}, "Syllables Not Dispersed -- Count syllables not dispersed due to explicit stop bits or to MLI bundle and resteers to non-0 syllable."}, #define PME_ITA2_SYLL_NOT_DISPERSED_FE 485 { "SYLL_NOT_DISPERSED_FE", {0x4004e}, 0xf0, 5, {0xf00001}, "Syllables Not Dispersed -- Count syllables not dispersed due to front-end not providing valid bundles or providing valid illegal templates. Dispersal takes a 3-syllable hit for every invalid bundle or valid illegal template from front-end. Bundle 1 with front-end fault, is counted here (3-syllable hit).."}, #define PME_ITA2_SYLL_NOT_DISPERSED_FE_OR_MLI 486 { "SYLL_NOT_DISPERSED_FE_OR_MLI", {0xc004e}, 0xf0, 5, {0xf00001}, "Syllables Not Dispersed -- Count syllables not dispersed due to MLI bundle and resteers to non-0 syllable or due to front-end not providing valid bundles or providing valid illegal templates."}, #define PME_ITA2_SYLL_NOT_DISPERSED_IMPL 487 { "SYLL_NOT_DISPERSED_IMPL", {0x2004e}, 0xf0, 5, {0xf00001}, "Syllables Not Dispersed -- Count syllables not dispersed due to implicit stop bits. These consist of all of the non-architected stop bits (asymmetry, oversubscription, implicit). Dispersal takes a 6-syllable(3-syllable) hit for every implicit stop bits in bundle 0(1)."}, #define PME_ITA2_SYLL_NOT_DISPERSED_IMPL_OR_FE 488 { "SYLL_NOT_DISPERSED_IMPL_OR_FE", {0x6004e}, 0xf0, 5, {0xf00001}, "Syllables Not Dispersed -- Count syllables not dispersed due to implicit stop bits or to front-end not providing valid bundles or providing valid illegal templates."}, #define PME_ITA2_SYLL_NOT_DISPERSED_IMPL_OR_FE_OR_MLI 489 { "SYLL_NOT_DISPERSED_IMPL_OR_FE_OR_MLI", {0xe004e}, 0xf0, 5, {0xf00001}, "Syllables Not Dispersed -- Count syllables not dispersed due to implicit stop bits or due to front-end not providing valid bundles or providing valid illegal templates or due to MLI bundle and resteers to non-0 syllable."}, #define PME_ITA2_SYLL_NOT_DISPERSED_IMPL_OR_MLI 490 { "SYLL_NOT_DISPERSED_IMPL_OR_MLI", {0xa004e}, 0xf0, 5, {0xf00001}, "Syllables Not Dispersed -- Count syllables not dispersed due to implicit stop bits or to MLI bundle and resteers to non-0 syllable."}, #define PME_ITA2_SYLL_NOT_DISPERSED_MLI 491 { "SYLL_NOT_DISPERSED_MLI", {0x8004e}, 0xf0, 5, {0xf00001}, "Syllables Not Dispersed -- Count syllables not dispersed due to MLI bundle and resteers to non-0 syllable. Dispersal takes a 1 syllable hit for each MLI bundle . Dispersal could take 0-2 syllable hit depending on which syllable we resteer to. Bundle 1 with front-end fault which is split, is counted here (0-2 syllable hit)."}, #define PME_ITA2_SYLL_OVERCOUNT_ALL 492 { "SYLL_OVERCOUNT_ALL", {0x3004f}, 0xf0, 2, {0xf00001}, "Syllables Overcounted -- syllables overcounted in implicit & explicit bucket"}, #define PME_ITA2_SYLL_OVERCOUNT_EXPL 493 { "SYLL_OVERCOUNT_EXPL", {0x1004f}, 0xf0, 2, {0xf00001}, "Syllables Overcounted -- Only syllables overcounted in the explicit bucket"}, #define PME_ITA2_SYLL_OVERCOUNT_IMPL 494 { "SYLL_OVERCOUNT_IMPL", {0x2004f}, 0xf0, 2, {0xf00001}, "Syllables Overcounted -- Only syllables overcounted in the implicit bucket"}, #define PME_ITA2_UC_LOADS_RETIRED 495 { "UC_LOADS_RETIRED", {0xcf}, 0xf0, 4, {0x5310007}, "Retired Uncacheable Loads"}, #define PME_ITA2_UC_STORES_RETIRED 496 { "UC_STORES_RETIRED", {0xd0}, 0xf0, 2, {0x5410007}, "Retired Uncacheable Stores"}, }; #define PME_ITA2_EVENT_COUNT 497 libpfm-4.9.0/lib/events/intel_snbep_unc_cbo_events.h0000664000175000017500000005720513223402656022430 0ustar eranianeranian/* * Copyright (c) 2012 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * PMU: snbep_unc_cbo (Intel SandyBridge-EP C-Box uncore PMU) */ #define CBO_FILT_MESIF(a, b, c, d) \ { .uname = "STATE_"#a,\ .udesc = #b" cacheline state",\ .ufilters[0] = 1ULL << (18 + (c)),\ .grpid = d, \ } #define CBO_FILT_MESIFS(d) \ CBO_FILT_MESIF(I, Invalid, 0, d), \ CBO_FILT_MESIF(S, Shared, 1, d), \ CBO_FILT_MESIF(E, Exclusive, 2, d), \ CBO_FILT_MESIF(M, Modified, 3, d), \ CBO_FILT_MESIF(F, Forward, 4, d), \ { .uname = "STATE_MESIF",\ .udesc = "Any cache line state",\ .ufilters[0] = 0x1fULL << 18,\ .grpid = d, \ .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, \ } #define CBO_FILT_OPC(d) \ { .uname = "OPC_RFO",\ .udesc = "Demand data RFO (combine with any OPCODE umask)",\ .ufilters[0] = 0x180ULL << 23, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_CRD",\ .udesc = "Demand code read (combine with any OPCODE umask)",\ .ufilters[0] = 0x181ULL << 23, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_DRD",\ .udesc = "Demand data read (combine with any OPCODE umask)",\ .ufilters[0] = 0x182ULL << 23, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_PRD",\ .udesc = "Partial reads (UC) (combine with any OPCODE umask)",\ .ufilters[0] = 0x187ULL << 23, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_WCILF",\ .udesc = "Full Stream store (combine with any OPCODE umask)", \ .ufilters[0] = 0x18cULL << 23, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_WCIL",\ .udesc = "Partial Stream store (combine with any OPCODE umask)", \ .ufilters[0] = 0x18dULL << 23, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_PF_RFO",\ .udesc = "Prefetch RFO into LLC but do not pass to L2 (includes hints) (combine with any OPCODE umask)", \ .ufilters[0] = 0x190ULL << 23, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_PF_CODE",\ .udesc = "Prefetch code into LLC but do not pass to L2 (includes hints) (combine with any OPCODE umask)", \ .ufilters[0] = 0x191ULL << 23, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_PF_DATA",\ .udesc = "Prefetch data into LLC but do not pass to L2 (includes hints) (combine with any OPCODE umask)", \ .ufilters[0] = 0x192ULL << 23, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_PCIWILF",\ .udesc = "PCIe write (non-allocating) (combine with any OPCODE umask)", \ .ufilters[0] = 0x194ULL << 23, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_PCIPRD",\ .udesc = "PCIe UC read (combine with any OPCODE umask)", \ .ufilters[0] = 0x195ULL << 23, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_PCIITOM",\ .udesc = "PCIe write (allocating) (combine with any OPCODE umask)", \ .ufilters[0] = 0x19cULL << 23, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_PCIRDCUR",\ .udesc = "PCIe read current (combine with any OPCODE umask)", \ .ufilters[0] = 0x19eULL << 23, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_WBMTOI",\ .udesc = "Request writeback modified invalidate line (combine with any OPCODE umask)", \ .ufilters[0] = 0x1c4ULL << 23, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_WBMTOE",\ .udesc = "Request writeback modified set to exclusive (combine with any OPCODE umask)", \ .ufilters[0] = 0x1c5ULL << 23, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_ITOM",\ .udesc = "Request invalidate line (combine with any OPCODE umask)", \ .ufilters[0] = 0x1c8ULL << 23, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_PCINSRD",\ .udesc = "PCIe non-snoop read (combine with any OPCODE umask)", \ .ufilters[0] = 0x1e4ULL << 23, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_PCINSWR",\ .udesc = "PCIe non-snoop write (partial) (combine with any OPCODE umask)", \ .ufilters[0] = 0x1e5ULL << 23, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_PCINSWRF",\ .udesc = "PCIe non-snoop write (full) (combine with any OPCODE umask)", \ .ufilters[0] = 0x1e6ULL << 23, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ } static const intel_x86_umask_t snbep_unc_c_llc_lookup[]={ { .uname = "ANY", .udesc = "Any request", .grpid = 0, .uflags = INTEL_X86_NCOMBO, .ucode = 0x1f00, }, { .uname = "DATA_READ", .udesc = "Data read requests", .grpid = 0, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, .ucode = 0x300, }, { .uname = "WRITE", .udesc = "Write requests. Includes all write transactions (cached, uncached)", .grpid = 0, .uflags = INTEL_X86_NCOMBO, .ucode = 0x500, }, { .uname = "REMOTE_SNOOP", .udesc = "External snoop request", .grpid = 0, .uflags = INTEL_X86_NCOMBO, .ucode = 0x900, }, { .uname = "NID", .udesc = "Match a given RTID destination NID (must provide nf=X modifier)", .uflags = INTEL_X86_NCOMBO | INTEL_X86_GRP_DFL_NONE, .umodmsk_req = _SNBEP_UNC_ATTR_NF, .grpid = 1, .ucode = 0x4100, }, CBO_FILT_MESIFS(2), }; static const intel_x86_umask_t snbep_unc_c_llc_victims[]={ { .uname = "M_STATE", .udesc = "Lines in M state", .ucode = 0x100, }, { .uname = "E_STATE", .udesc = "Lines in E state", .ucode = 0x200, }, { .uname = "S_STATE", .udesc = "Lines in S state", .ucode = 0x400, }, { .uname = "MISS", .udesc = "TBD", .ucode = 0x800, }, { .uname = "NID", .udesc = "Victimized Lines matching the NID filter (must provide nf=X modifier)", .uflags = INTEL_X86_NCOMBO, .umodmsk_req = _SNBEP_UNC_ATTR_NF, .ucode = 0x4000, }, }; static const intel_x86_umask_t snbep_unc_c_misc[]={ { .uname = "RSPI_WAS_FSE", .udesc = "Silent snoop eviction", .ucode = 0x100, }, { .uname = "WC_ALIASING", .udesc = "Write combining aliasing", .ucode = 0x200, }, { .uname = "STARTED", .udesc = "TBD", .ucode = 0x400, }, { .uname = "RFO_HIT_S", .udesc = "RFO hits in S state", .ucode = 0x800, }, }; static const intel_x86_umask_t snbep_unc_c_ring_ad_used[]={ { .uname = "UP_EVEN", .udesc = "Up and Even ring polarity filter", .ucode = 0x100, }, { .uname = "UP_ODD", .udesc = "Up and odd ring polarity filter", .ucode = 0x200, }, { .uname = "DOWN_EVEN", .udesc = "Down and even ring polarity filter", .ucode = 0x400, }, { .uname = "DOWN_ODD", .udesc = "Down and odd ring polarity filter", .ucode = 0x800, }, }; static const intel_x86_umask_t snbep_unc_c_ring_bounces[]={ { .uname = "AK_CORE", .udesc = "Acknowledgment to core", .ucode = 0x200, }, { .uname = "BL_CORE", .udesc = "Data response to core", .ucode = 0x400, }, { .uname = "IV_CORE", .udesc = "Snoops of processor cache", .ucode = 0x800, }, }; static const intel_x86_umask_t snbep_unc_c_ring_iv_used[]={ { .uname = "ANY", .udesc = "Any filter", .ucode = 0xf00, .uflags = INTEL_X86_DFL, }, }; static const intel_x86_umask_t snbep_unc_c_rxr_ext_starved[]={ { .uname = "IRQ", .udesc = "Irq externally starved, therefore blocking the IPQ", .ucode = 0x100, }, { .uname = "IPQ", .udesc = "IPQ externally starved, therefore blocking the IRQ", .ucode = 0x200, }, { .uname = "ISMQ", .udesc = "ISMQ externally starved, therefore blocking both IRQ and IPQ", .ucode = 0x400, }, { .uname = "ISMQ_BIDS", .udesc = "Number of time the ISMQ bids", .ucode = 0x800, }, }; static const intel_x86_umask_t snbep_unc_c_rxr_inserts[]={ { .uname = "IPQ", .udesc = "IPQ", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "IRQ", .udesc = "IRQ", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "IRQ_REJECTED", .udesc = "IRQ rejected", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "VFIFO", .udesc = "Counts the number of allocated into the IRQ ordering FIFO", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t snbep_unc_c_rxr_ipq_retry[]={ { .uname = "ADDR_CONFLICT", .udesc = "Address conflict", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ANY", .udesc = "Any Reject", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "FULL", .udesc = "No Egress credits", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "QPI_CREDITS", .udesc = "No QPI credits", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t snbep_unc_c_rxr_irq_retry[]={ { .uname = "ADDR_CONFLICT", .udesc = "Address conflict", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ANY", .udesc = "Any reject", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "FULL", .udesc = "No Egress credits", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "QPI_CREDITS", .udesc = "No QPI credits", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "RTID", .udesc = "No RTIDs", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t snbep_unc_c_rxr_ismq_retry[]={ { .uname = "ANY", .udesc = "Any reject", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "FULL", .udesc = "No Egress credits", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "IIO_CREDITS", .udesc = "No IIO credits", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "QPI_CREDITS", .udesc = "NO QPI credits", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "RTID", .udesc = "No RTIDs", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t snbep_unc_c_tor_inserts[]={ { .uname = "EVICTION", .udesc = "Number of Evictions transactions inserted into TOR", .ucode = 0x400, .grpid = 0, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, }, { .uname = "MISS_ALL", .udesc = "Number of miss requests inserted into the TOR", .ucode = 0xa00, .grpid = 0, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, }, { .uname = "MISS_OPCODE", .udesc = "Number of miss transactions inserted into the TOR that match an opcode (must provide opc_* umask)", .ucode = 0x300, .grpid = 0, .uflags = INTEL_X86_NCOMBO, }, { .uname = "NID_ALL", .udesc = "Number of NID-matched transactions inserted into the TOR (must provide nf=X modifier)", .ucode = 0x4800, .grpid = 0, .umodmsk_req = _SNBEP_UNC_ATTR_NF, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, }, { .uname = "NID_EVICTION", .udesc = "Number of NID-matched eviction transactions inserted into the TOR (must provide nf=X modifier)", .ucode = 0x4400, .grpid = 0, .umodmsk_req = _SNBEP_UNC_ATTR_NF, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, }, { .uname = "NID_MISS_ALL", .udesc = "Number of NID-matched miss transactions that were inserted into the TOR (must provide nf=X modifier)", .ucode = 0x4a00, .grpid = 0, .umodmsk_req = _SNBEP_UNC_ATTR_NF, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, }, { .uname = "NID_MISS_OPCODE", .udesc = "Number of NID and opcode matched miss transactions inserted into the TOR (must provide opc_* umask and nf=X modifier)", .ucode = 0x4300, .grpid = 0, .umodmsk_req = _SNBEP_UNC_ATTR_NF, .uflags = INTEL_X86_NCOMBO, }, { .uname = "NID_OPCODE", .udesc = "Number of transactions inserted into the TOR that match a NID and opcode (must provide opc_* umask and nf=X modifier)", .ucode = 0x4100, .grpid = 0, .umodmsk_req = _SNBEP_UNC_ATTR_NF, .uflags = INTEL_X86_NCOMBO, }, { .uname = "NID_WB", .udesc = "Number of NID-matched write back transactions inserted into the TOR (must provide nf=X modifier)", .ucode = 0x5000, .grpid = 0, .umodmsk_req = _SNBEP_UNC_ATTR_NF, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, }, { .uname = "OPCODE", .udesc = "Number of transactions inserted into the TOR that match an opcode (must provide opc_* umask)", .ucode = 0x100, .grpid = 0, .uflags = INTEL_X86_NCOMBO, }, { .uname = "WB", .udesc = "Number of write transactions inserted into the TOR", .ucode = 0x1000, .grpid = 0, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, }, CBO_FILT_OPC(1) }; static const intel_x86_umask_t snbep_unc_c_tor_occupancy[]={ { .uname = "ALL", .udesc = "All valid TOR entries", .ucode = 0x800, .grpid = 0, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL | INTEL_X86_EXCL_GRP_GT, }, { .uname = "EVICTION", .udesc = "Number of outstanding eviction transactions in the TOR", .ucode = 0x400, .grpid = 0, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, }, { .uname = "MISS_ALL", .udesc = "Number of outstanding miss requests in the TOR", .ucode = 0xa00, .grpid = 0, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, }, { .uname = "MISS_OPCODE", .udesc = "Number of TOR entries that match a NID and an opcode (must provide opc_* umask)", .ucode = 0x300, .grpid = 0, .uflags = INTEL_X86_NCOMBO, }, { .uname = "NID_ALL", .udesc = "Number of NID-matched outstanding requests in the TOR (must provide nf=X modifier)", .ucode = 0x4800, .grpid = 0, .umodmsk_req = _SNBEP_UNC_ATTR_NF, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, }, { .uname = "NID_EVICTION", .udesc = "Number of NID-matched outstanding requests in the TOR (must provide a nf=X modifier)", .ucode = 0x4400, .grpid = 0, .umodmsk_req = _SNBEP_UNC_ATTR_NF, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, }, { .uname = "NID_MISS_ALL", .udesc = "Number of NID-matched outstanding miss requests in the TOR (must provide a nf=X modifier)", .ucode = 0x4a00, .grpid = 0, .umodmsk_req = _SNBEP_UNC_ATTR_NF, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, }, { .uname = "NID_MISS_OPCODE", .udesc = "Number of NID-matched outstanding miss requests in the TOR that an opcode (must provide nf=X modifier and opc_* umask)", .ucode = 0x4300, .grpid = 0, .umodmsk_req = _SNBEP_UNC_ATTR_NF, .uflags = INTEL_X86_NCOMBO, }, { .uname = "NID_OPCODE", .udesc = "Number of NID-matched TOR entries that an opcode (must provide nf=X modifier and opc_* umask)", .ucode = 0x4100, .grpid = 0, .umodmsk_req = _SNBEP_UNC_ATTR_NF, .uflags = INTEL_X86_NCOMBO, }, { .uname = "OPCODE", .udesc = "Number of TOR entries that match an opcode (must provide opc_* umask)", .ucode = 0x100, .grpid = 0, .uflags = INTEL_X86_NCOMBO, }, CBO_FILT_OPC(1) }; static const intel_x86_umask_t snbep_unc_c_txr_inserts[]={ { .uname = "AD_CACHE", .udesc = "Counts the number of ring transactions from Cachebo to AD ring", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "AK_CACHE", .udesc = "Counts the number of ring transactions from Cachebo to AK ring", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "BL_CACHE", .udesc = "Counts the number of ring transactions from Cachebo to BL ring", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "IV_CACHE", .udesc = "Counts the number of ring transactions from Cachebo to IV ring", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "AD_CORE", .udesc = "Counts the number of ring transactions from Corebo to AD ring", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "AK_CORE", .udesc = "Counts the number of ring transactions from Corebo to AK ring", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "BL_CORE", .udesc = "Counts the number of ring transactions from Corebo to BL ring", .ucode = 0x4000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_entry_t intel_snbep_unc_c_pe[]={ { .name = "UNC_C_CLOCKTICKS", .desc = "C-box Uncore clockticks", .modmsk = 0x0, .cntmsk = 0xf, .code = 0x00, .flags = INTEL_X86_FIXED, }, { .name = "UNC_C_COUNTER0_OCCUPANCY", .desc = "Counter 0 occupancy. Counts the occupancy related information by filtering CB0 occupancy count captured in counter 0.", .modmsk = SNBEP_UNC_CBO_ATTRS, .cntmsk = 0xe, .code = 0x1f, }, { .name = "UNC_C_ISMQ_DRD_MISS_OCC", .desc = "TBD", .modmsk = SNBEP_UNC_CBO_ATTRS, .cntmsk = 0x3, .code = 0x21, }, { .name = "UNC_C_LLC_LOOKUP", .desc = "Cache lookups. Counts number of times the LLC is accessed from L2 for code, data, prefetches (Must set filter mask bit 0 and select )", .modmsk = SNBEP_UNC_CBO_NID_ATTRS, .cntmsk = 0x3, .code = 0x34, .ngrp = 3, .flags = INTEL_X86_NO_AUTOENCODE, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_c_llc_lookup), .umasks = snbep_unc_c_llc_lookup, }, { .name = "UNC_C_LLC_VICTIMS", .desc = "Lines victimized", .modmsk = SNBEP_UNC_CBO_NID_ATTRS, .cntmsk = 0x3, .code = 0x37, .flags = INTEL_X86_NO_AUTOENCODE, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_c_llc_victims), .ngrp = 1, .umasks = snbep_unc_c_llc_victims, }, { .name = "UNC_C_MISC", .desc = "Miscellaneous C-Box events", .modmsk = SNBEP_UNC_CBO_ATTRS, .cntmsk = 0x3, .code = 0x39, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_c_misc), .ngrp = 1, .umasks = snbep_unc_c_misc, }, { .name = "UNC_C_RING_AD_USED", .desc = "Address ring in use. Counts number of cycles ring is being used at this ring stop", .modmsk = SNBEP_UNC_CBO_ATTRS, .cntmsk = 0xc, .code = 0x1b, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_c_ring_ad_used), .ngrp = 1, .umasks = snbep_unc_c_ring_ad_used, }, { .name = "UNC_C_RING_AK_USED", .desc = "Acknowledgment ring in use. Counts number of cycles ring is being used at this ring stop", .modmsk = SNBEP_UNC_CBO_ATTRS, .cntmsk = 0xc, .code = 0x1c, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_c_ring_ad_used), /* identical to RING_AD_USED */ .ngrp = 1, .umasks = snbep_unc_c_ring_ad_used, }, { .name = "UNC_C_RING_BL_USED", .desc = "Bus or Data ring in use. Counts number of cycles ring is being used at this ring stop", .modmsk = SNBEP_UNC_CBO_ATTRS, .cntmsk = 0xc, .code = 0x1d, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_c_ring_ad_used), /* identical to RING_AD_USED */ .ngrp = 1, .umasks = snbep_unc_c_ring_ad_used, }, { .name = "UNC_C_RING_BOUNCES", .desc = "Number of LLC responses that bounced in the ring", .modmsk = SNBEP_UNC_CBO_ATTRS, .cntmsk = 0x3, .code = 0x05, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_c_ring_bounces), .ngrp = 1, .umasks = snbep_unc_c_ring_bounces, }, { .name = "UNC_C_RING_IV_USED", .desc = "Invalidate ring in use. Counts number of cycles ring is being used at this ring stop", .modmsk = SNBEP_UNC_CBO_ATTRS, .cntmsk = 0xc, .code = 0x1e, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_c_ring_iv_used), .ngrp = 1, .umasks = snbep_unc_c_ring_iv_used, }, { .name = "UNC_C_RING_SRC_THRTL", .desc = "TDB", .modmsk = SNBEP_UNC_CBO_ATTRS, .cntmsk = 0x3, .code = 0x07, }, { .name = "UNC_C_RXR_EXT_STARVED", .desc = "Ingress arbiter blocking cycles", .modmsk = SNBEP_UNC_CBO_ATTRS, .cntmsk = 0x3, .code = 0x12, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_c_rxr_ext_starved), .ngrp = 1, .umasks = snbep_unc_c_rxr_ext_starved, }, { .name = "UNC_C_RXR_INSERTS", .desc = "Ingress Allocations", .code = 0x13, .cntmsk = 0x3, .ngrp = 1, .modmsk = SNBEP_UNC_CBO_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_c_rxr_inserts), .umasks = snbep_unc_c_rxr_inserts }, { .name = "UNC_C_RXR_IPQ_RETRY", .desc = "Probe Queue Retries", .code = 0x31, .cntmsk = 0x3, .ngrp = 1, .modmsk = SNBEP_UNC_CBO_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_c_rxr_ipq_retry), .umasks = snbep_unc_c_rxr_ipq_retry }, { .name = "UNC_C_RXR_IRQ_RETRY", .desc = "Ingress Request Queue Rejects", .code = 0x32, .cntmsk = 0x3, .ngrp = 1, .modmsk = SNBEP_UNC_CBO_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_c_rxr_irq_retry), .umasks = snbep_unc_c_rxr_irq_retry }, { .name = "UNC_C_RXR_ISMQ_RETRY", .desc = "ISMQ Retries", .code = 0x33, .cntmsk = 0x3, .ngrp = 1, .modmsk = SNBEP_UNC_CBO_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_c_rxr_ismq_retry), .umasks = snbep_unc_c_rxr_ismq_retry }, { .name = "UNC_C_RXR_OCCUPANCY", .desc = "Ingress Occupancy", .code = 0x11, .cntmsk = 0x1, .ngrp = 1, .modmsk = SNBEP_UNC_CBO_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_c_rxr_inserts), .umasks = snbep_unc_c_rxr_inserts, /* identical to snbep_unc_c_rxr_inserts */ }, { .name = "UNC_C_TOR_INSERTS", .desc = "TOR Inserts", .code = 0x35, .cntmsk = 0x3, .ngrp = 2, .modmsk = SNBEP_UNC_CBO_NID_ATTRS, .flags = INTEL_X86_NO_AUTOENCODE, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_c_tor_inserts), .umasks = snbep_unc_c_tor_inserts }, { .name = "UNC_C_TOR_OCCUPANCY", .desc = "TOR Occupancy", .code = 0x36, .cntmsk = 0x1, .ngrp = 2, .modmsk = SNBEP_UNC_CBO_NID_ATTRS, .flags = INTEL_X86_NO_AUTOENCODE, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_c_tor_occupancy), .umasks = snbep_unc_c_tor_occupancy }, { .name = "UNC_C_TXR_ADS_USED", .desc = "Egress events", .code = 0x04, .cntmsk = 0x3, .modmsk = SNBEP_UNC_CBO_ATTRS, }, { .name = "UNC_C_TXR_INSERTS", .desc = "Egress allocations", .code = 0x02, .cntmsk = 0x3, .ngrp = 1, .modmsk = SNBEP_UNC_CBO_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_c_txr_inserts), .umasks = snbep_unc_c_txr_inserts }, }; libpfm-4.9.0/lib/events/intel_ivbep_unc_irp_events.h0000664000175000017500000002017713223402656022453 0ustar eranianeranian/* * Copyright (c) 2014 Google Inc. All rights reserved * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * This file has been automatically generated. * * PMU: ivbep_unc_irp (Intel IvyBridge-EP IRP uncore) */ static const intel_x86_umask_t ivbep_unc_i_address_match[]={ { .uname = "STALL_COUNT", .udesc = "Number of time when it is not possible to merge two conflicting requests, a stall event occurs", .ucode = 0x100, }, { .uname = "MERGE_COUNT", .udesc = "Number of times when two requests to the same address from the same source are received back to back, it is possible to merge them", .ucode = 0x200, }, }; static const intel_x86_umask_t ivbep_unc_i_cache_ack_pending_occupancy[]={ { .uname = "ANY", .udesc = "Any source", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "SOURCE", .udesc = "Track all requests from any source port", .ucode = 0x200, }, }; static const intel_x86_umask_t ivbep_unc_i_tickles[]={ { .uname = "LOST_OWNERSHIP", .udesc = "Number of request that lost ownership as a result of a tickle", .ucode = 0x100, }, { .uname = "TOP_OF_QUEUE", .udesc = "Number of cases when a tickle was received but the request was at the head of the queue in the switch. In this case data is returned rather than releasing ownership", .ucode = 0x200, }, }; static const intel_x86_umask_t ivbep_unc_i_transactions[]={ { .uname = "READS", .udesc = "Number of read requests (not including read prefetches)", .ucode = 0x100, }, { .uname = "WRITES", .udesc = "Number of write requests. Each write should have a prefetch, so there is no need to explicitly track these requests", .ucode = 0x200, }, { .uname = "RD_PREFETCHES", .udesc = "Number of read prefetches", .ucode = 0x400, }, }; static const intel_x86_entry_t intel_ivbep_unc_i_pe[]={ { .name = "UNC_I_CLOCKTICKS", .desc = "Number of uclks in domain", .code = 0x0, .cntmsk = 0x3, .modmsk = SNBEP_UNC_IRP_ATTRS, }, { .name = "UNC_I_ADDRESS_MATCH", .desc = "Address match conflict count", .code = 0x17, .cntmsk = 0x3, .ngrp = 1, .modmsk = SNBEP_UNC_IRP_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_i_address_match), .umasks = ivbep_unc_i_address_match }, { .name = "UNC_I_CACHE_ACK_PENDING_OCCUPANCY", .desc = "Write ACK pending occupancy", .code = 0x14, .cntmsk = 0x3, .ngrp = 1, .modmsk = SNBEP_UNC_IRP_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_i_cache_ack_pending_occupancy), .umasks = ivbep_unc_i_cache_ack_pending_occupancy }, { .name = "UNC_I_CACHE_OWN_OCCUPANCY", .desc = "Outstanding write ownership occupancy", .code = 0x13, .cntmsk = 0x3, .ngrp = 1, .modmsk = SNBEP_UNC_IRP_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_i_cache_ack_pending_occupancy), .umasks = ivbep_unc_i_cache_ack_pending_occupancy /* shared */ }, { .name = "UNC_I_CACHE_READ_OCCUPANCY", .desc = "Outstanding read occupancy", .code = 0x10, .cntmsk = 0x3, .ngrp = 1, .modmsk = SNBEP_UNC_IRP_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_i_cache_ack_pending_occupancy), .umasks = ivbep_unc_i_cache_ack_pending_occupancy /* shared */ }, { .name = "UNC_I_CACHE_TOTAL_OCCUPANCY", .desc = "Total write cache occupancy", .code = 0x12, .cntmsk = 0x3, .ngrp = 1, .modmsk = SNBEP_UNC_IRP_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_i_cache_ack_pending_occupancy), .umasks = ivbep_unc_i_cache_ack_pending_occupancy /* shared */ }, { .name = "UNC_I_CACHE_WRITE_OCCUPANCY", .desc = "Outstanding write occupancy", .code = 0x11, .cntmsk = 0x3, .ngrp = 1, .modmsk = SNBEP_UNC_IRP_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_i_cache_ack_pending_occupancy), .umasks = ivbep_unc_i_cache_ack_pending_occupancy /* shared */ }, { .name = "UNC_I_RXR_AK_CYCLES_FULL", .desc = "TBD", .code = 0xb, .cntmsk = 0x3, .modmsk = SNBEP_UNC_IRP_ATTRS, }, { .name = "UNC_I_RXR_AK_INSERTS", .desc = "Egress cycles full", .code = 0xa, .cntmsk = 0x3, .modmsk = SNBEP_UNC_IRP_ATTRS, }, { .name = "UNC_I_RXR_AK_OCCUPANCY", .desc = "TBD", .code = 0x0c, .cntmsk = 0x3, .modmsk = SNBEP_UNC_IRP_ATTRS, }, { .name = "UNC_I_RXR_BL_DRS_CYCLES_FULL", .desc = "TBD", .code = 0x4, .cntmsk = 0x3, .modmsk = SNBEP_UNC_IRP_ATTRS, }, { .name = "UNC_I_RXR_BL_DRS_INSERTS", .desc = "BL Ingress occupancy DRS", .code = 0x1, .cntmsk = 0x3, .modmsk = SNBEP_UNC_IRP_ATTRS, }, { .name = "UNC_I_RXR_BL_DRS_OCCUPANCY", .desc = "TBD", .code = 0x7, .cntmsk = 0x3, .modmsk = SNBEP_UNC_IRP_ATTRS, }, { .name = "UNC_I_RXR_BL_NCB_CYCLES_FULL", .desc = "TBD", .code = 0x5, .cntmsk = 0x3, .modmsk = SNBEP_UNC_IRP_ATTRS, }, { .name = "UNC_I_RXR_BL_NCB_INSERTS", .desc = "BL Ingress occupancy NCB", .code = 0x2, .cntmsk = 0x3, .modmsk = SNBEP_UNC_IRP_ATTRS, }, { .name = "UNC_I_RXR_BL_NCB_OCCUPANCY", .desc = "TBD", .code = 0x8, .cntmsk = 0x3, .modmsk = SNBEP_UNC_IRP_ATTRS, }, { .name = "UNC_I_RXR_BL_NCS_CYCLES_FULL", .desc = "TBD", .code = 0x6, .cntmsk = 0x3, .modmsk = SNBEP_UNC_IRP_ATTRS, }, { .name = "UNC_I_RXR_BL_NCS_INSERTS", .desc = "BL Ingress Occupancy NCS", .code = 0x3, .cntmsk = 0x3, .modmsk = SNBEP_UNC_IRP_ATTRS, }, { .name = "UNC_I_RXR_BL_NCS_OCCUPANCY", .desc = "TBD", .code = 0x9, .cntmsk = 0x3, .modmsk = SNBEP_UNC_IRP_ATTRS, }, { .name = "UNC_I_TICKLES", .desc = "Tickle count", .code = 0x16, .cntmsk = 0x3, .ngrp = 1, .modmsk = SNBEP_UNC_IRP_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_i_tickles), .umasks = ivbep_unc_i_tickles }, { .name = "UNC_I_TRANSACTIONS", .desc = "Inbound transaction count", .code = 0x15, .cntmsk = 0x3, .ngrp = 1, .modmsk = SNBEP_UNC_IRP_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_i_transactions), .umasks = ivbep_unc_i_transactions }, { .name = "UNC_I_TXR_AD_STALL_CREDIT_CYCLES", .desc = "No AD Egress credit stalls", .code = 0x18, .cntmsk = 0x3, .modmsk = SNBEP_UNC_IRP_ATTRS, }, { .name = "UNC_I_TXR_BL_STALL_CREDIT_CYCLES", .desc = "No BL Egress credit stalls", .code = 0x19, .cntmsk = 0x3, .modmsk = SNBEP_UNC_IRP_ATTRS, }, { .name = "UNC_I_TXR_DATA_INSERTS_NCB", .desc = "Outbound read requests", .code = 0xe, .cntmsk = 0x3, .modmsk = SNBEP_UNC_IRP_ATTRS, }, { .name = "UNC_I_TXR_DATA_INSERTS_NCS", .desc = "Outbound read requests", .code = 0xf, .cntmsk = 0x3, .modmsk = SNBEP_UNC_IRP_ATTRS, }, { .name = "UNC_I_TXR_REQUEST_OCCUPANCY", .desc = "Outbound request queue occupancy", .code = 0xd, .cntmsk = 0x3, .modmsk = SNBEP_UNC_IRP_ATTRS, }, { .name = "UNC_I_WRITE_ORDERING_STALL_CYCLES", .desc = "Write ordering stalls", .code = 0x1a, .cntmsk = 0x3, .modmsk = SNBEP_UNC_IRP_ATTRS, }, }; libpfm-4.9.0/lib/events/power5+_events.h0000664000175000017500000053745113223402656017740 0ustar eranianeranian/****************************/ /* THIS IS OPEN SOURCE CODE */ /****************************/ #ifndef __POWER5p_EVENTS_H__ #define __POWER5p_EVENTS_H__ /* * File: power5+_events.h * CVS: * Author: Corey Ashford * cjashfor@us.ibm.com * Mods: * * * (C) Copyright IBM Corporation, 2009. All Rights Reserved. * Contributed by Corey Ashford * * Note: This code was automatically generated and should not be modified by * hand. * */ #define POWER5p_PME_PM_LSU_REJECT_RELOAD_CDF 0 #define POWER5p_PME_PM_FPU1_SINGLE 1 #define POWER5p_PME_PM_L3SB_REF 2 #define POWER5p_PME_PM_THRD_PRIO_DIFF_3or4_CYC 3 #define POWER5p_PME_PM_INST_FROM_L275_SHR 4 #define POWER5p_PME_PM_MRK_DATA_FROM_L375_MOD 5 #define POWER5p_PME_PM_DTLB_MISS_4K 6 #define POWER5p_PME_PM_CLB_FULL_CYC 7 #define POWER5p_PME_PM_MRK_ST_CMPL 8 #define POWER5p_PME_PM_LSU_FLUSH_LRQ_FULL 9 #define POWER5p_PME_PM_MRK_DATA_FROM_L275_SHR 10 #define POWER5p_PME_PM_1INST_CLB_CYC 11 #define POWER5p_PME_PM_MEM_SPEC_RD_CANCEL 12 #define POWER5p_PME_PM_MRK_DTLB_MISS_16M 13 #define POWER5p_PME_PM_FPU_FDIV 14 #define POWER5p_PME_PM_FPU_SINGLE 15 #define POWER5p_PME_PM_FPU0_FMA 16 #define POWER5p_PME_PM_SLB_MISS 17 #define POWER5p_PME_PM_LSU1_FLUSH_LRQ 18 #define POWER5p_PME_PM_L2SA_ST_HIT 19 #define POWER5p_PME_PM_DTLB_MISS 20 #define POWER5p_PME_PM_BR_PRED_TA 21 #define POWER5p_PME_PM_MRK_DATA_FROM_L375_MOD_CYC 22 #define POWER5p_PME_PM_CMPLU_STALL_FXU 23 #define POWER5p_PME_PM_EXT_INT 24 #define POWER5p_PME_PM_MRK_LSU1_FLUSH_LRQ 25 #define POWER5p_PME_PM_MRK_ST_GPS 26 #define POWER5p_PME_PM_LSU1_LDF 27 #define POWER5p_PME_PM_FAB_CMD_ISSUED 28 #define POWER5p_PME_PM_LSU0_SRQ_STFWD 29 #define POWER5p_PME_PM_CR_MAP_FULL_CYC 30 #define POWER5p_PME_PM_L2SA_RCST_DISP_FAIL_RC_FULL 31 #define POWER5p_PME_PM_MRK_LSU0_FLUSH_ULD 32 #define POWER5p_PME_PM_LSU_FLUSH_SRQ_FULL 33 #define POWER5p_PME_PM_MEM_RQ_DISP_Q16to19 34 #define POWER5p_PME_PM_FLUSH_IMBAL 35 #define POWER5p_PME_PM_THRD_PRIO_DIFF_minus3or4_CYC 36 #define POWER5p_PME_PM_DATA_FROM_L35_MOD 37 #define POWER5p_PME_PM_MEM_HI_PRIO_WR_CMPL 38 #define POWER5p_PME_PM_FPU1_FDIV 39 #define POWER5p_PME_PM_MEM_RQ_DISP 40 #define POWER5p_PME_PM_FPU0_FRSP_FCONV 41 #define POWER5p_PME_PM_LWSYNC_HELD 42 #define POWER5p_PME_PM_FXU_FIN 43 #define POWER5p_PME_PM_DSLB_MISS 44 #define POWER5p_PME_PM_DATA_FROM_L275_SHR 45 #define POWER5p_PME_PM_FXLS1_FULL_CYC 46 #define POWER5p_PME_PM_THRD_SEL_T0 47 #define POWER5p_PME_PM_PTEG_RELOAD_VALID 48 #define POWER5p_PME_PM_MRK_STCX_FAIL 49 #define POWER5p_PME_PM_LSU_LMQ_LHR_MERGE 50 #define POWER5p_PME_PM_2INST_CLB_CYC 51 #define POWER5p_PME_PM_FAB_PNtoVN_DIRECT 52 #define POWER5p_PME_PM_PTEG_FROM_L2MISS 53 #define POWER5p_PME_PM_CMPLU_STALL_LSU 54 #define POWER5p_PME_PM_MRK_DSLB_MISS 55 #define POWER5p_PME_PM_LSU_FLUSH_ULD 56 #define POWER5p_PME_PM_PTEG_FROM_LMEM 57 #define POWER5p_PME_PM_MRK_BRU_FIN 58 #define POWER5p_PME_PM_MEM_WQ_DISP_WRITE 59 #define POWER5p_PME_PM_MRK_DATA_FROM_L275_MOD_CYC 60 #define POWER5p_PME_PM_LSU1_NCLD 61 #define POWER5p_PME_PM_L2SA_RCLD_DISP_FAIL_OTHER 62 #define POWER5p_PME_PM_SNOOP_PW_RETRY_WQ_PWQ 63 #define POWER5p_PME_PM_FPU1_FULL_CYC 64 #define POWER5p_PME_PM_FPR_MAP_FULL_CYC 65 #define POWER5p_PME_PM_L3SA_ALL_BUSY 66 #define POWER5p_PME_PM_3INST_CLB_CYC 67 #define POWER5p_PME_PM_MEM_PWQ_DISP_Q2or3 68 #define POWER5p_PME_PM_L2SA_SHR_INV 69 #define POWER5p_PME_PM_THRESH_TIMEO 70 #define POWER5p_PME_PM_L2SA_RC_DISP_FAIL_CO_BUSY_ALL 71 #define POWER5p_PME_PM_THRD_SEL_OVER_GCT_IMBAL 72 #define POWER5p_PME_PM_FPU_FSQRT 73 #define POWER5p_PME_PM_PMC1_OVERFLOW 74 #define POWER5p_PME_PM_MRK_LSU0_FLUSH_LRQ 75 #define POWER5p_PME_PM_L3SC_SNOOP_RETRY 76 #define POWER5p_PME_PM_DATA_TABLEWALK_CYC 77 #define POWER5p_PME_PM_THRD_PRIO_6_CYC 78 #define POWER5p_PME_PM_FPU_FEST 79 #define POWER5p_PME_PM_FAB_M1toP1_SIDECAR_EMPTY 80 #define POWER5p_PME_PM_MRK_DATA_FROM_RMEM 81 #define POWER5p_PME_PM_MRK_DATA_FROM_L35_MOD_CYC 82 #define POWER5p_PME_PM_MEM_PWQ_DISP 83 #define POWER5p_PME_PM_FAB_P1toM1_SIDECAR_EMPTY 84 #define POWER5p_PME_PM_LD_MISS_L1_LSU0 85 #define POWER5p_PME_PM_SNOOP_PARTIAL_RTRY_QFULL 86 #define POWER5p_PME_PM_FPU1_STALL3 87 #define POWER5p_PME_PM_GCT_USAGE_80to99_CYC 88 #define POWER5p_PME_PM_WORK_HELD 89 #define POWER5p_PME_PM_INST_CMPL 90 #define POWER5p_PME_PM_LSU1_FLUSH_UST 91 #define POWER5p_PME_PM_FXU_IDLE 92 #define POWER5p_PME_PM_LSU0_FLUSH_ULD 93 #define POWER5p_PME_PM_LSU1_REJECT_LMQ_FULL 94 #define POWER5p_PME_PM_GRP_DISP_REJECT 95 #define POWER5p_PME_PM_PTEG_FROM_L25_SHR 96 #define POWER5p_PME_PM_L2SA_MOD_INV 97 #define POWER5p_PME_PM_FAB_CMD_RETRIED 98 #define POWER5p_PME_PM_L3SA_SHR_INV 99 #define POWER5p_PME_PM_L2SB_RC_DISP_FAIL_CO_BUSY_ALL 100 #define POWER5p_PME_PM_L2SA_RCST_DISP_FAIL_ADDR 101 #define POWER5p_PME_PM_L2SA_RCLD_DISP_FAIL_RC_FULL 102 #define POWER5p_PME_PM_PTEG_FROM_L375_MOD 103 #define POWER5p_PME_PM_MRK_LSU1_FLUSH_UST 104 #define POWER5p_PME_PM_BR_ISSUED 105 #define POWER5p_PME_PM_MRK_GRP_BR_REDIR 106 #define POWER5p_PME_PM_EE_OFF 107 #define POWER5p_PME_PM_IERAT_XLATE_WR_LP 108 #define POWER5p_PME_PM_DTLB_REF_64K 109 #define POWER5p_PME_PM_MEM_RQ_DISP_Q4to7 110 #define POWER5p_PME_PM_MEM_FAST_PATH_RD_DISP 111 #define POWER5p_PME_PM_INST_FROM_L3 112 #define POWER5p_PME_PM_ITLB_MISS 113 #define POWER5p_PME_PM_FXU1_BUSY_FXU0_IDLE 114 #define POWER5p_PME_PM_DTLB_REF_4K 115 #define POWER5p_PME_PM_FXLS_FULL_CYC 116 #define POWER5p_PME_PM_GRP_DISP_VALID 117 #define POWER5p_PME_PM_LSU_FLUSH_UST 118 #define POWER5p_PME_PM_FXU1_FIN 119 #define POWER5p_PME_PM_THRD_PRIO_4_CYC 120 #define POWER5p_PME_PM_MRK_DATA_FROM_L35_MOD 121 #define POWER5p_PME_PM_4INST_CLB_CYC 122 #define POWER5p_PME_PM_MRK_DTLB_REF_16M 123 #define POWER5p_PME_PM_INST_FROM_L375_MOD 124 #define POWER5p_PME_PM_GRP_CMPL 125 #define POWER5p_PME_PM_L2SC_RCST_DISP_FAIL_ADDR 126 #define POWER5p_PME_PM_FPU1_1FLOP 127 #define POWER5p_PME_PM_FPU_FRSP_FCONV 128 #define POWER5p_PME_PM_L3SC_REF 129 #define POWER5p_PME_PM_5INST_CLB_CYC 130 #define POWER5p_PME_PM_THRD_L2MISS_BOTH_CYC 131 #define POWER5p_PME_PM_MEM_PW_GATH 132 #define POWER5p_PME_PM_DTLB_REF_16G 133 #define POWER5p_PME_PM_FAB_DCLAIM_ISSUED 134 #define POWER5p_PME_PM_FAB_PNtoNN_SIDECAR 135 #define POWER5p_PME_PM_GRP_IC_MISS 136 #define POWER5p_PME_PM_INST_FROM_L35_SHR 137 #define POWER5p_PME_PM_LSU_LMQ_FULL_CYC 138 #define POWER5p_PME_PM_MRK_DATA_FROM_L2_CYC 139 #define POWER5p_PME_PM_LSU_SRQ_SYNC_CYC 140 #define POWER5p_PME_PM_LSU0_BUSY_REJECT 141 #define POWER5p_PME_PM_LSU_REJECT_ERAT_MISS 142 #define POWER5p_PME_PM_MRK_DATA_FROM_RMEM_CYC 143 #define POWER5p_PME_PM_DATA_FROM_L375_SHR 144 #define POWER5p_PME_PM_PTEG_FROM_L25_MOD 145 #define POWER5p_PME_PM_FPU0_FMOV_FEST 146 #define POWER5p_PME_PM_THRD_PRIO_7_CYC 147 #define POWER5p_PME_PM_LSU1_FLUSH_SRQ 148 #define POWER5p_PME_PM_LD_REF_L1_LSU0 149 #define POWER5p_PME_PM_L2SC_RCST_DISP 150 #define POWER5p_PME_PM_CMPLU_STALL_DIV 151 #define POWER5p_PME_PM_MEM_RQ_DISP_Q12to15 152 #define POWER5p_PME_PM_INST_FROM_L375_SHR 153 #define POWER5p_PME_PM_ST_REF_L1 154 #define POWER5p_PME_PM_L3SB_ALL_BUSY 155 #define POWER5p_PME_PM_FAB_P1toVNorNN_SIDECAR_EMPTY 156 #define POWER5p_PME_PM_MRK_DATA_FROM_L275_SHR_CYC 157 #define POWER5p_PME_PM_FAB_HOLDtoNN_EMPTY 158 #define POWER5p_PME_PM_DATA_FROM_LMEM 159 #define POWER5p_PME_PM_RUN_CYC 160 #define POWER5p_PME_PM_PTEG_FROM_RMEM 161 #define POWER5p_PME_PM_L2SC_RCLD_DISP 162 #define POWER5p_PME_PM_LSU_LRQ_S0_VALID 163 #define POWER5p_PME_PM_LSU0_LDF 164 #define POWER5p_PME_PM_PMC3_OVERFLOW 165 #define POWER5p_PME_PM_MRK_IMR_RELOAD 166 #define POWER5p_PME_PM_MRK_GRP_TIMEO 167 #define POWER5p_PME_PM_ST_MISS_L1 168 #define POWER5p_PME_PM_STOP_COMPLETION 169 #define POWER5p_PME_PM_LSU_BUSY_REJECT 170 #define POWER5p_PME_PM_ISLB_MISS 171 #define POWER5p_PME_PM_CYC 172 #define POWER5p_PME_PM_THRD_ONE_RUN_CYC 173 #define POWER5p_PME_PM_GRP_BR_REDIR_NONSPEC 174 #define POWER5p_PME_PM_LSU1_SRQ_STFWD 175 #define POWER5p_PME_PM_L3SC_MOD_INV 176 #define POWER5p_PME_PM_L2_PREF 177 #define POWER5p_PME_PM_GCT_NOSLOT_BR_MPRED 178 #define POWER5p_PME_PM_MRK_DATA_FROM_L25_MOD 179 #define POWER5p_PME_PM_L2SB_ST_REQ 180 #define POWER5p_PME_PM_L2SB_MOD_INV 181 #define POWER5p_PME_PM_MRK_L1_RELOAD_VALID 182 #define POWER5p_PME_PM_L3SB_HIT 183 #define POWER5p_PME_PM_L2SB_SHR_MOD 184 #define POWER5p_PME_PM_EE_OFF_EXT_INT 185 #define POWER5p_PME_PM_1PLUS_PPC_CMPL 186 #define POWER5p_PME_PM_L2SC_SHR_MOD 187 #define POWER5p_PME_PM_PMC6_OVERFLOW 188 #define POWER5p_PME_PM_IC_PREF_INSTALL 189 #define POWER5p_PME_PM_LSU_LRQ_FULL_CYC 190 #define POWER5p_PME_PM_TLB_MISS 191 #define POWER5p_PME_PM_GCT_FULL_CYC 192 #define POWER5p_PME_PM_FXU_BUSY 193 #define POWER5p_PME_PM_MRK_DATA_FROM_L3_CYC 194 #define POWER5p_PME_PM_LSU_REJECT_LMQ_FULL 195 #define POWER5p_PME_PM_LSU_SRQ_S0_ALLOC 196 #define POWER5p_PME_PM_GRP_MRK 197 #define POWER5p_PME_PM_INST_FROM_L25_SHR 198 #define POWER5p_PME_PM_DC_PREF_STREAM_ALLOC 199 #define POWER5p_PME_PM_FPU1_FIN 200 #define POWER5p_PME_PM_BR_MPRED_TA 201 #define POWER5p_PME_PM_MRK_DTLB_REF_64K 202 #define POWER5p_PME_PM_RUN_INST_CMPL 203 #define POWER5p_PME_PM_CRQ_FULL_CYC 204 #define POWER5p_PME_PM_L2SA_RCLD_DISP 205 #define POWER5p_PME_PM_SNOOP_WR_RETRY_QFULL 206 #define POWER5p_PME_PM_MRK_DTLB_REF_4K 207 #define POWER5p_PME_PM_LSU_SRQ_S0_VALID 208 #define POWER5p_PME_PM_LSU0_FLUSH_LRQ 209 #define POWER5p_PME_PM_INST_FROM_L275_MOD 210 #define POWER5p_PME_PM_GCT_EMPTY_CYC 211 #define POWER5p_PME_PM_LARX_LSU0 212 #define POWER5p_PME_PM_THRD_PRIO_DIFF_5or6_CYC 213 #define POWER5p_PME_PM_SNOOP_RETRY_1AHEAD 214 #define POWER5p_PME_PM_FPU1_FSQRT 215 #define POWER5p_PME_PM_MRK_LD_MISS_L1_LSU1 216 #define POWER5p_PME_PM_MRK_FPU_FIN 217 #define POWER5p_PME_PM_THRD_PRIO_5_CYC 218 #define POWER5p_PME_PM_MRK_DATA_FROM_LMEM 219 #define POWER5p_PME_PM_SNOOP_TLBIE 220 #define POWER5p_PME_PM_FPU1_FRSP_FCONV 221 #define POWER5p_PME_PM_DTLB_MISS_16G 222 #define POWER5p_PME_PM_L3SB_SNOOP_RETRY 223 #define POWER5p_PME_PM_FAB_VBYPASS_EMPTY 224 #define POWER5p_PME_PM_MRK_DATA_FROM_L275_MOD 225 #define POWER5p_PME_PM_L2SB_RCST_DISP 226 #define POWER5p_PME_PM_6INST_CLB_CYC 227 #define POWER5p_PME_PM_FLUSH 228 #define POWER5p_PME_PM_L2SC_MOD_INV 229 #define POWER5p_PME_PM_FPU_DENORM 230 #define POWER5p_PME_PM_L3SC_HIT 231 #define POWER5p_PME_PM_SNOOP_WR_RETRY_RQ 232 #define POWER5p_PME_PM_LSU1_REJECT_SRQ 233 #define POWER5p_PME_PM_L3SC_ALL_BUSY 234 #define POWER5p_PME_PM_IC_PREF_REQ 235 #define POWER5p_PME_PM_MRK_GRP_IC_MISS 236 #define POWER5p_PME_PM_GCT_NOSLOT_IC_MISS 237 #define POWER5p_PME_PM_MRK_DATA_FROM_L3 238 #define POWER5p_PME_PM_GCT_NOSLOT_SRQ_FULL 239 #define POWER5p_PME_PM_CMPLU_STALL_DCACHE_MISS 240 #define POWER5p_PME_PM_THRD_SEL_OVER_ISU_HOLD 241 #define POWER5p_PME_PM_LSU_FLUSH_LRQ 242 #define POWER5p_PME_PM_THRD_PRIO_2_CYC 243 #define POWER5p_PME_PM_L3SA_MOD_INV 244 #define POWER5p_PME_PM_LSU_FLUSH_SRQ 245 #define POWER5p_PME_PM_MRK_LSU_SRQ_INST_VALID 246 #define POWER5p_PME_PM_L3SA_REF 247 #define POWER5p_PME_PM_L2SC_RC_DISP_FAIL_CO_BUSY_ALL 248 #define POWER5p_PME_PM_FPU0_STALL3 249 #define POWER5p_PME_PM_TB_BIT_TRANS 250 #define POWER5p_PME_PM_GPR_MAP_FULL_CYC 251 #define POWER5p_PME_PM_MRK_LSU_FLUSH_LRQ 252 #define POWER5p_PME_PM_FPU0_STF 253 #define POWER5p_PME_PM_MRK_DTLB_MISS 254 #define POWER5p_PME_PM_FPU1_FMA 255 #define POWER5p_PME_PM_L2SA_MOD_TAG 256 #define POWER5p_PME_PM_LSU1_FLUSH_ULD 257 #define POWER5p_PME_PM_MRK_INST_FIN 258 #define POWER5p_PME_PM_MRK_LSU0_FLUSH_UST 259 #define POWER5p_PME_PM_FPU0_FULL_CYC 260 #define POWER5p_PME_PM_LSU_LRQ_S0_ALLOC 261 #define POWER5p_PME_PM_MRK_LSU1_FLUSH_ULD 262 #define POWER5p_PME_PM_MRK_DTLB_REF 263 #define POWER5p_PME_PM_BR_UNCOND 264 #define POWER5p_PME_PM_THRD_SEL_OVER_L2MISS 265 #define POWER5p_PME_PM_L2SB_SHR_INV 266 #define POWER5p_PME_PM_MEM_LO_PRIO_WR_CMPL 267 #define POWER5p_PME_PM_MRK_DTLB_MISS_64K 268 #define POWER5p_PME_PM_MRK_ST_MISS_L1 269 #define POWER5p_PME_PM_L3SC_MOD_TAG 270 #define POWER5p_PME_PM_GRP_DISP_SUCCESS 271 #define POWER5p_PME_PM_THRD_PRIO_DIFF_1or2_CYC 272 #define POWER5p_PME_PM_IC_DEMAND_L2_BHT_REDIRECT 273 #define POWER5p_PME_PM_LSU_DERAT_MISS 274 #define POWER5p_PME_PM_MEM_WQ_DISP_Q8to15 275 #define POWER5p_PME_PM_FPU0_SINGLE 276 #define POWER5p_PME_PM_THRD_PRIO_1_CYC 277 #define POWER5p_PME_PM_L2SC_RCST_DISP_FAIL_OTHER 278 #define POWER5p_PME_PM_SNOOP_RD_RETRY_RQ 279 #define POWER5p_PME_PM_FAB_HOLDtoVN_EMPTY 280 #define POWER5p_PME_PM_FPU1_FEST 281 #define POWER5p_PME_PM_SNOOP_DCLAIM_RETRY_QFULL 282 #define POWER5p_PME_PM_MRK_DATA_FROM_L25_SHR_CYC 283 #define POWER5p_PME_PM_MRK_ST_CMPL_INT 284 #define POWER5p_PME_PM_FLUSH_BR_MPRED 285 #define POWER5p_PME_PM_MRK_DTLB_MISS_16G 286 #define POWER5p_PME_PM_FPU_STF 287 #define POWER5p_PME_PM_L2SB_RCLD_DISP_FAIL_ADDR 288 #define POWER5p_PME_PM_CMPLU_STALL_FPU 289 #define POWER5p_PME_PM_THRD_PRIO_DIFF_minus1or2_CYC 290 #define POWER5p_PME_PM_GCT_NOSLOT_CYC 291 #define POWER5p_PME_PM_FXU0_BUSY_FXU1_IDLE 292 #define POWER5p_PME_PM_PTEG_FROM_L35_SHR 293 #define POWER5p_PME_PM_MRK_DTLB_REF_16G 294 #define POWER5p_PME_PM_MRK_LSU_FLUSH_UST 295 #define POWER5p_PME_PM_MRK_DATA_FROM_L25_SHR 296 #define POWER5p_PME_PM_L3SA_HIT 297 #define POWER5p_PME_PM_MRK_DATA_FROM_L35_SHR 298 #define POWER5p_PME_PM_L2SB_RCST_DISP_FAIL_ADDR 299 #define POWER5p_PME_PM_IERAT_XLATE_WR 300 #define POWER5p_PME_PM_L2SA_ST_REQ 301 #define POWER5p_PME_PM_INST_FROM_LMEM 302 #define POWER5p_PME_PM_THRD_SEL_T1 303 #define POWER5p_PME_PM_IC_DEMAND_L2_BR_REDIRECT 304 #define POWER5p_PME_PM_MRK_DATA_FROM_L35_SHR_CYC 305 #define POWER5p_PME_PM_FPU0_1FLOP 306 #define POWER5p_PME_PM_PTEG_FROM_L2 307 #define POWER5p_PME_PM_MEM_PW_CMPL 308 #define POWER5p_PME_PM_THRD_PRIO_DIFF_minus5or6_CYC 309 #define POWER5p_PME_PM_L2SB_RCLD_DISP_FAIL_OTHER 310 #define POWER5p_PME_PM_MRK_DTLB_MISS_4K 311 #define POWER5p_PME_PM_FPU0_FIN 312 #define POWER5p_PME_PM_L3SC_SHR_INV 313 #define POWER5p_PME_PM_GRP_BR_REDIR 314 #define POWER5p_PME_PM_L2SC_RCLD_DISP_FAIL_RC_FULL 315 #define POWER5p_PME_PM_MRK_LSU_FLUSH_SRQ 316 #define POWER5p_PME_PM_PTEG_FROM_L275_SHR 317 #define POWER5p_PME_PM_L2SB_RCLD_DISP_FAIL_RC_FULL 318 #define POWER5p_PME_PM_SNOOP_RD_RETRY_WQ 319 #define POWER5p_PME_PM_FAB_DCLAIM_RETRIED 320 #define POWER5p_PME_PM_LSU0_NCLD 321 #define POWER5p_PME_PM_LSU1_BUSY_REJECT 322 #define POWER5p_PME_PM_FXLS0_FULL_CYC 323 #define POWER5p_PME_PM_DTLB_REF_16M 324 #define POWER5p_PME_PM_FPU0_FEST 325 #define POWER5p_PME_PM_GCT_USAGE_60to79_CYC 326 #define POWER5p_PME_PM_DATA_FROM_L25_MOD 327 #define POWER5p_PME_PM_L2SC_RCLD_DISP_FAIL_ADDR 328 #define POWER5p_PME_PM_LSU0_REJECT_ERAT_MISS 329 #define POWER5p_PME_PM_DATA_FROM_L375_MOD 330 #define POWER5p_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC 331 #define POWER5p_PME_PM_DTLB_MISS_64K 332 #define POWER5p_PME_PM_LSU0_REJECT_RELOAD_CDF 333 #define POWER5p_PME_PM_0INST_FETCH 334 #define POWER5p_PME_PM_LSU1_REJECT_RELOAD_CDF 335 #define POWER5p_PME_PM_MEM_WQ_DISP_Q0to7 336 #define POWER5p_PME_PM_L1_PREF 337 #define POWER5p_PME_PM_MRK_DATA_FROM_LMEM_CYC 338 #define POWER5p_PME_PM_BRQ_FULL_CYC 339 #define POWER5p_PME_PM_GRP_IC_MISS_NONSPEC 340 #define POWER5p_PME_PM_PTEG_FROM_L275_MOD 341 #define POWER5p_PME_PM_MRK_LD_MISS_L1_LSU0 342 #define POWER5p_PME_PM_MRK_DATA_FROM_L375_SHR_CYC 343 #define POWER5p_PME_PM_DATA_FROM_L3 344 #define POWER5p_PME_PM_INST_FROM_L2 345 #define POWER5p_PME_PM_LSU_FLUSH 346 #define POWER5p_PME_PM_PMC2_OVERFLOW 347 #define POWER5p_PME_PM_FPU0_DENORM 348 #define POWER5p_PME_PM_FPU1_FMOV_FEST 349 #define POWER5p_PME_PM_INST_FETCH_CYC 350 #define POWER5p_PME_PM_INST_DISP 351 #define POWER5p_PME_PM_LSU_LDF 352 #define POWER5p_PME_PM_DATA_FROM_L25_SHR 353 #define POWER5p_PME_PM_L1_DCACHE_RELOAD_VALID 354 #define POWER5p_PME_PM_MEM_WQ_DISP_DCLAIM 355 #define POWER5p_PME_PM_MRK_GRP_ISSUED 356 #define POWER5p_PME_PM_FPU_FULL_CYC 357 #define POWER5p_PME_PM_INST_FROM_L35_MOD 358 #define POWER5p_PME_PM_FPU_FMA 359 #define POWER5p_PME_PM_THRD_PRIO_3_CYC 360 #define POWER5p_PME_PM_MRK_CRU_FIN 361 #define POWER5p_PME_PM_SNOOP_WR_RETRY_WQ 362 #define POWER5p_PME_PM_CMPLU_STALL_REJECT 363 #define POWER5p_PME_PM_MRK_FXU_FIN 364 #define POWER5p_PME_PM_LSU1_REJECT_ERAT_MISS 365 #define POWER5p_PME_PM_L2SB_RCST_DISP_FAIL_OTHER 366 #define POWER5p_PME_PM_L2SC_RC_DISP_FAIL_CO_BUSY 367 #define POWER5p_PME_PM_PMC4_OVERFLOW 368 #define POWER5p_PME_PM_L3SA_SNOOP_RETRY 369 #define POWER5p_PME_PM_PTEG_FROM_L35_MOD 370 #define POWER5p_PME_PM_INST_FROM_L25_MOD 371 #define POWER5p_PME_PM_THRD_SMT_HANG 372 #define POWER5p_PME_PM_CMPLU_STALL_ERAT_MISS 373 #define POWER5p_PME_PM_L3SA_MOD_TAG 374 #define POWER5p_PME_PM_INST_FROM_L2MISS 375 #define POWER5p_PME_PM_FLUSH_SYNC 376 #define POWER5p_PME_PM_MRK_GRP_DISP 377 #define POWER5p_PME_PM_MEM_RQ_DISP_Q8to11 378 #define POWER5p_PME_PM_L2SC_ST_HIT 379 #define POWER5p_PME_PM_L2SB_MOD_TAG 380 #define POWER5p_PME_PM_CLB_EMPTY_CYC 381 #define POWER5p_PME_PM_L2SB_ST_HIT 382 #define POWER5p_PME_PM_MEM_NONSPEC_RD_CANCEL 383 #define POWER5p_PME_PM_BR_PRED_CR_TA 384 #define POWER5p_PME_PM_MRK_LSU0_FLUSH_SRQ 385 #define POWER5p_PME_PM_MRK_LSU_FLUSH_ULD 386 #define POWER5p_PME_PM_INST_DISP_ATTEMPT 387 #define POWER5p_PME_PM_INST_FROM_RMEM 388 #define POWER5p_PME_PM_ST_REF_L1_LSU0 389 #define POWER5p_PME_PM_LSU0_DERAT_MISS 390 #define POWER5p_PME_PM_FPU_STALL3 391 #define POWER5p_PME_PM_L2SB_RCLD_DISP 392 #define POWER5p_PME_PM_BR_PRED_CR 393 #define POWER5p_PME_PM_MRK_DATA_FROM_L2 394 #define POWER5p_PME_PM_LSU0_FLUSH_SRQ 395 #define POWER5p_PME_PM_FAB_PNtoNN_DIRECT 396 #define POWER5p_PME_PM_IOPS_CMPL 397 #define POWER5p_PME_PM_L2SA_RCST_DISP 398 #define POWER5p_PME_PM_L2SA_RCST_DISP_FAIL_OTHER 399 #define POWER5p_PME_PM_L2SC_SHR_INV 400 #define POWER5p_PME_PM_SNOOP_RETRY_AB_COLLISION 401 #define POWER5p_PME_PM_FAB_PNtoVN_SIDECAR 402 #define POWER5p_PME_PM_LSU0_REJECT_LMQ_FULL 403 #define POWER5p_PME_PM_LSU_LMQ_S0_ALLOC 404 #define POWER5p_PME_PM_SNOOP_PW_RETRY_RQ 405 #define POWER5p_PME_PM_DTLB_REF 406 #define POWER5p_PME_PM_PTEG_FROM_L3 407 #define POWER5p_PME_PM_FAB_M1toVNorNN_SIDECAR_EMPTY 408 #define POWER5p_PME_PM_LSU_SRQ_EMPTY_CYC 409 #define POWER5p_PME_PM_FPU1_STF 410 #define POWER5p_PME_PM_LSU_LMQ_S0_VALID 411 #define POWER5p_PME_PM_GCT_USAGE_00to59_CYC 412 #define POWER5p_PME_PM_FPU_FMOV_FEST 413 #define POWER5p_PME_PM_DATA_FROM_L2MISS 414 #define POWER5p_PME_PM_XER_MAP_FULL_CYC 415 #define POWER5p_PME_PM_GRP_DISP_BLK_SB_CYC 416 #define POWER5p_PME_PM_FLUSH_SB 417 #define POWER5p_PME_PM_MRK_DATA_FROM_L375_SHR 418 #define POWER5p_PME_PM_MRK_GRP_CMPL 419 #define POWER5p_PME_PM_SUSPENDED 420 #define POWER5p_PME_PM_SNOOP_RD_RETRY_QFULL 421 #define POWER5p_PME_PM_GRP_IC_MISS_BR_REDIR_NONSPEC 422 #define POWER5p_PME_PM_DATA_FROM_L35_SHR 423 #define POWER5p_PME_PM_L3SB_MOD_INV 424 #define POWER5p_PME_PM_STCX_FAIL 425 #define POWER5p_PME_PM_LD_MISS_L1_LSU1 426 #define POWER5p_PME_PM_GRP_DISP 427 #define POWER5p_PME_PM_DC_PREF_DST 428 #define POWER5p_PME_PM_FPU1_DENORM 429 #define POWER5p_PME_PM_FPU0_FPSCR 430 #define POWER5p_PME_PM_DATA_FROM_L2 431 #define POWER5p_PME_PM_L2SA_RCLD_DISP_FAIL_ADDR 432 #define POWER5p_PME_PM_FPU_1FLOP 433 #define POWER5p_PME_PM_L2SC_RCLD_DISP_FAIL_OTHER 434 #define POWER5p_PME_PM_FPU0_FSQRT 435 #define POWER5p_PME_PM_L2SC_RCST_DISP_FAIL_RC_FULL 436 #define POWER5p_PME_PM_LD_REF_L1 437 #define POWER5p_PME_PM_INST_FROM_L1 438 #define POWER5p_PME_PM_TLBIE_HELD 439 #define POWER5p_PME_PM_DC_PREF_OUT_OF_STREAMS 440 #define POWER5p_PME_PM_MRK_DATA_FROM_L25_MOD_CYC 441 #define POWER5p_PME_PM_MRK_LSU1_FLUSH_SRQ 442 #define POWER5p_PME_PM_MEM_RQ_DISP_Q0to3 443 #define POWER5p_PME_PM_ST_REF_L1_LSU1 444 #define POWER5p_PME_PM_MRK_LD_MISS_L1 445 #define POWER5p_PME_PM_L1_WRITE_CYC 446 #define POWER5p_PME_PM_L2SC_ST_REQ 447 #define POWER5p_PME_PM_CMPLU_STALL_FDIV 448 #define POWER5p_PME_PM_THRD_SEL_OVER_CLB_EMPTY 449 #define POWER5p_PME_PM_BR_MPRED_CR 450 #define POWER5p_PME_PM_L3SB_MOD_TAG 451 #define POWER5p_PME_PM_MRK_DATA_FROM_L2MISS 452 #define POWER5p_PME_PM_LSU_REJECT_SRQ 453 #define POWER5p_PME_PM_LD_MISS_L1 454 #define POWER5p_PME_PM_INST_FROM_PREF 455 #define POWER5p_PME_PM_STCX_PASS 456 #define POWER5p_PME_PM_DC_INV_L2 457 #define POWER5p_PME_PM_LSU_SRQ_FULL_CYC 458 #define POWER5p_PME_PM_FPU_FIN 459 #define POWER5p_PME_PM_LSU_SRQ_STFWD 460 #define POWER5p_PME_PM_L2SA_SHR_MOD 461 #define POWER5p_PME_PM_0INST_CLB_CYC 462 #define POWER5p_PME_PM_FXU0_FIN 463 #define POWER5p_PME_PM_L2SB_RCST_DISP_FAIL_RC_FULL 464 #define POWER5p_PME_PM_THRD_GRP_CMPL_BOTH_CYC 465 #define POWER5p_PME_PM_PMC5_OVERFLOW 466 #define POWER5p_PME_PM_FPU0_FDIV 467 #define POWER5p_PME_PM_PTEG_FROM_L375_SHR 468 #define POWER5p_PME_PM_HV_CYC 469 #define POWER5p_PME_PM_L2SA_RC_DISP_FAIL_CO_BUSY 470 #define POWER5p_PME_PM_THRD_PRIO_DIFF_0_CYC 471 #define POWER5p_PME_PM_LR_CTR_MAP_FULL_CYC 472 #define POWER5p_PME_PM_L3SB_SHR_INV 473 #define POWER5p_PME_PM_DATA_FROM_RMEM 474 #define POWER5p_PME_PM_DATA_FROM_L275_MOD 475 #define POWER5p_PME_PM_LSU0_REJECT_SRQ 476 #define POWER5p_PME_PM_LSU1_DERAT_MISS 477 #define POWER5p_PME_PM_MRK_LSU_FIN 478 #define POWER5p_PME_PM_DTLB_MISS_16M 479 #define POWER5p_PME_PM_LSU0_FLUSH_UST 480 #define POWER5p_PME_PM_L2SB_RC_DISP_FAIL_CO_BUSY 481 #define POWER5p_PME_PM_L2SC_MOD_TAG 482 static const pme_power_entry_t power5p_pe[] = { [ POWER5p_PME_PM_LSU_REJECT_RELOAD_CDF ] = { .pme_name = "PM_LSU_REJECT_RELOAD_CDF", .pme_code = 0x2c4090, .pme_short_desc = "LSU reject due to reload CDF or tag update collision", .pme_long_desc = "Total cycles the Load Store Unit is busy rejecting instructions because of Critical Data Forward. When critical data arrives from the storage system it is formatted and immediately forwarded, bypassing the data cache, to the destination register using the result bus. Any instruction the requires the result bus in the same cycle is rejected. Tag update rejects are caused when an instruction requires access to the Dcache directory or ERAT in the same system when they are being updated. Combined Unit 0 + 1.", }, [ POWER5p_PME_PM_FPU1_SINGLE ] = { .pme_name = "PM_FPU1_SINGLE", .pme_code = 0x20e7, .pme_short_desc = "FPU1 executed single precision instruction", .pme_long_desc = "FPU1 has executed a single precision instruction.", }, [ POWER5p_PME_PM_L3SB_REF ] = { .pme_name = "PM_L3SB_REF", .pme_code = 0x701c4, .pme_short_desc = "L3 slice B references", .pme_long_desc = "Number of attempts made by this chip cores to find data in the L3. Reported per L3 slice", }, [ POWER5p_PME_PM_THRD_PRIO_DIFF_3or4_CYC ] = { .pme_name = "PM_THRD_PRIO_DIFF_3or4_CYC", .pme_code = 0x430e5, .pme_short_desc = "Cycles thread priority difference is 3 or 4", .pme_long_desc = "Cycles when this thread's priority is higher than the other thread's priority by 3 or 4.", }, [ POWER5p_PME_PM_INST_FROM_L275_SHR ] = { .pme_name = "PM_INST_FROM_L275_SHR", .pme_code = 0x322096, .pme_short_desc = "Instruction fetched from L2.75 shared", .pme_long_desc = "An instruction fetch group was fetched with shared (T) data from the L2 on a different module than this processor is located. Fetch groups can contain up to 8 instructions", }, [ POWER5p_PME_PM_MRK_DATA_FROM_L375_MOD ] = { .pme_name = "PM_MRK_DATA_FROM_L375_MOD", .pme_code = 0x1c70a7, .pme_short_desc = "Marked data loaded from L3.75 modified", .pme_long_desc = "The processor's Data Cache was reloaded with modified (M) data from the L3 of a chip on a different module than this processor is located due to a marked load.", }, [ POWER5p_PME_PM_DTLB_MISS_4K ] = { .pme_name = "PM_DTLB_MISS_4K", .pme_code = 0x1c208d, .pme_short_desc = "Data TLB miss for 4K page", .pme_long_desc = "Data TLB references to 4KB pages that missed the TLB. Page size is determined at TLB reload time.", }, [ POWER5p_PME_PM_CLB_FULL_CYC ] = { .pme_name = "PM_CLB_FULL_CYC", .pme_code = 0x220e5, .pme_short_desc = "Cycles CLB full", .pme_long_desc = "Cycles when both thread's CLB is full.", }, [ POWER5p_PME_PM_MRK_ST_CMPL ] = { .pme_name = "PM_MRK_ST_CMPL", .pme_code = 0x100003, .pme_short_desc = "Marked store instruction completed", .pme_long_desc = "A sampled store has completed (data home)", }, [ POWER5p_PME_PM_LSU_FLUSH_LRQ_FULL ] = { .pme_name = "PM_LSU_FLUSH_LRQ_FULL", .pme_code = 0x320e7, .pme_short_desc = "Flush caused by LRQ full", .pme_long_desc = "This thread was flushed at dispatch because its Load Request Queue was full. This allows the other thread to have more machine resources for it to make progress while this thread is stalled.", }, [ POWER5p_PME_PM_MRK_DATA_FROM_L275_SHR ] = { .pme_name = "PM_MRK_DATA_FROM_L275_SHR", .pme_code = 0x3c7097, .pme_short_desc = "Marked data loaded from L2.75 shared", .pme_long_desc = "The processor's Data Cache was reloaded with shared (T) data from the L2 on a different module than this processor is located due to a marked load.", }, [ POWER5p_PME_PM_1INST_CLB_CYC ] = { .pme_name = "PM_1INST_CLB_CYC", .pme_code = 0x400c1, .pme_short_desc = "Cycles 1 instruction in CLB", .pme_long_desc = "The cache line buffer (CLB) is a 6-deep, 4-wide instruction buffer. Fullness is reported on a cycle basis with each event representing the number of cycles the CLB had the corresponding number of entries occupied. These events give a real time history of the number of instruction buffers used, but not the number of PowerPC instructions within those buffers. Each thread has its own set of CLB; these events are thread specific.", }, [ POWER5p_PME_PM_MEM_SPEC_RD_CANCEL ] = { .pme_name = "PM_MEM_SPEC_RD_CANCEL", .pme_code = 0x721e6, .pme_short_desc = "Speculative memory read cancelled", .pme_long_desc = "Speculative memory read cancelled (i.e. cresp = sourced by L2/L3)", }, [ POWER5p_PME_PM_MRK_DTLB_MISS_16M ] = { .pme_name = "PM_MRK_DTLB_MISS_16M", .pme_code = 0x3c608d, .pme_short_desc = "Marked Data TLB misses for 16M page", .pme_long_desc = "Marked Data TLB misses for 16M page", }, [ POWER5p_PME_PM_FPU_FDIV ] = { .pme_name = "PM_FPU_FDIV", .pme_code = 0x100088, .pme_short_desc = "FPU executed FDIV instruction", .pme_long_desc = "The floating point unit has executed a divide instruction. This could be fdiv, fdivs, fdiv., fdivs.. Combined Unit 0 + Unit 1.", }, [ POWER5p_PME_PM_FPU_SINGLE ] = { .pme_name = "PM_FPU_SINGLE", .pme_code = 0x102090, .pme_short_desc = "FPU executed single precision instruction", .pme_long_desc = "FPU is executing single precision instruction. Combined Unit 0 + Unit 1.", }, [ POWER5p_PME_PM_FPU0_FMA ] = { .pme_name = "PM_FPU0_FMA", .pme_code = 0xc1, .pme_short_desc = "FPU0 executed multiply-add instruction", .pme_long_desc = "The floating point unit has executed a multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs.", }, [ POWER5p_PME_PM_SLB_MISS ] = { .pme_name = "PM_SLB_MISS", .pme_code = 0x280088, .pme_short_desc = "SLB misses", .pme_long_desc = "Total of all Segment Lookaside Buffer (SLB) misses, Instructions + Data.", }, [ POWER5p_PME_PM_LSU1_FLUSH_LRQ ] = { .pme_name = "PM_LSU1_FLUSH_LRQ", .pme_code = 0xc00c6, .pme_short_desc = "LSU1 LRQ flushes", .pme_long_desc = "A load was flushed by unit 1 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.", }, [ POWER5p_PME_PM_L2SA_ST_HIT ] = { .pme_name = "PM_L2SA_ST_HIT", .pme_code = 0x733e0, .pme_short_desc = "L2 slice A store hits", .pme_long_desc = "A store request made from the core hit in the L2 directory. This event is provided on each of the three L2 slices A, B, and C.", }, [ POWER5p_PME_PM_DTLB_MISS ] = { .pme_name = "PM_DTLB_MISS", .pme_code = 0x800c4, .pme_short_desc = "Data TLB misses", .pme_long_desc = "Data TLB misses, all page sizes.", }, [ POWER5p_PME_PM_BR_PRED_TA ] = { .pme_name = "PM_BR_PRED_TA", .pme_code = 0x230e3, .pme_short_desc = "A conditional branch was predicted, target prediction", .pme_long_desc = "The target address of a branch instruction was predicted.", }, [ POWER5p_PME_PM_MRK_DATA_FROM_L375_MOD_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L375_MOD_CYC", .pme_code = 0x4c70a7, .pme_short_desc = "Marked load latency from L3.75 modified", .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.", }, [ POWER5p_PME_PM_CMPLU_STALL_FXU ] = { .pme_name = "PM_CMPLU_STALL_FXU", .pme_code = 0x211099, .pme_short_desc = "Completion stall caused by FXU instruction", .pme_long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes was a fixed point instruction.", }, [ POWER5p_PME_PM_EXT_INT ] = { .pme_name = "PM_EXT_INT", .pme_code = 0x400003, .pme_short_desc = "External interrupts", .pme_long_desc = "An interrupt due to an external exception occurred", }, [ POWER5p_PME_PM_MRK_LSU1_FLUSH_LRQ ] = { .pme_name = "PM_MRK_LSU1_FLUSH_LRQ", .pme_code = 0x810c6, .pme_short_desc = "LSU1 marked LRQ flushes", .pme_long_desc = "A marked load was flushed by unit 1 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.", }, [ POWER5p_PME_PM_MRK_ST_GPS ] = { .pme_name = "PM_MRK_ST_GPS", .pme_code = 0x200003, .pme_short_desc = "Marked store sent to GPS", .pme_long_desc = "A sampled store has been sent to the memory subsystem", }, [ POWER5p_PME_PM_LSU1_LDF ] = { .pme_name = "PM_LSU1_LDF", .pme_code = 0xc50c4, .pme_short_desc = "LSU1 executed Floating Point load instruction", .pme_long_desc = "A floating point load was executed by LSU1", }, [ POWER5p_PME_PM_FAB_CMD_ISSUED ] = { .pme_name = "PM_FAB_CMD_ISSUED", .pme_code = 0x700c7, .pme_short_desc = "Fabric command issued", .pme_long_desc = "Incremented when a chip issues a command on its SnoopA address bus. Each of the two address busses (SnoopA and SnoopB) is capable of one transaction per fabric cycle (one fabric cycle = 2 cpu cycles in normal 2:1 mode), but each chip can only drive the SnoopA bus, and can only drive one transaction every two fabric cycles (i.e., every four cpu cycles). In MCM-based systems, two chips interleave their accesses to each of the two fabric busses (SnoopA, SnoopB) to reach a peak capability of one transaction per cpu clock cycle. The two chips that drive SnoopB are wired so that the chips refer to the bus as SnoopA but it is connected to the other two chips as SnoopB. Note that this event will only be recorded by the FBC on the chip that sourced the operation. The signal is delivered at FBC speed and the count must be scaled.", }, [ POWER5p_PME_PM_LSU0_SRQ_STFWD ] = { .pme_name = "PM_LSU0_SRQ_STFWD", .pme_code = 0xc60e1, .pme_short_desc = "LSU0 SRQ store forwarded", .pme_long_desc = "Data from a store instruction was forwarded to a load on unit 0. A load that misses L1 but becomes a store forward is treated as a load miss and it causes the DL1 load miss event to be counted. It does not go into the LMQ. If a load that hits L1 but becomes a store forward, then it's not treated as a load miss.", }, [ POWER5p_PME_PM_CR_MAP_FULL_CYC ] = { .pme_name = "PM_CR_MAP_FULL_CYC", .pme_code = 0x100c4, .pme_short_desc = "Cycles CR logical operation mapper full", .pme_long_desc = "The Conditional Register mapper cannot accept any more groups. This condition will prevent dispatch groups from being dispatched. This event only indicates that the mapper was full, not that dispatch was prevented.", }, [ POWER5p_PME_PM_L2SA_RCST_DISP_FAIL_RC_FULL ] = { .pme_name = "PM_L2SA_RCST_DISP_FAIL_RC_FULL", .pme_code = 0x722e0, .pme_short_desc = "L2 slice A RC store dispatch attempt failed due to all RC full", .pme_long_desc = "A Read/Claim dispatch for a store failed because all RC machines are busy.", }, [ POWER5p_PME_PM_MRK_LSU0_FLUSH_ULD ] = { .pme_name = "PM_MRK_LSU0_FLUSH_ULD", .pme_code = 0x810c1, .pme_short_desc = "LSU0 marked unaligned load flushes", .pme_long_desc = "A marked load was flushed from unit 0 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)", }, [ POWER5p_PME_PM_LSU_FLUSH_SRQ_FULL ] = { .pme_name = "PM_LSU_FLUSH_SRQ_FULL", .pme_code = 0x330e0, .pme_short_desc = "Flush caused by SRQ full", .pme_long_desc = "This thread was flushed at dispatch because its Store Request Queue was full. This allows the other thread to have more machine resources for it to make progress while this thread is stalled.", }, [ POWER5p_PME_PM_MEM_RQ_DISP_Q16to19 ] = { .pme_name = "PM_MEM_RQ_DISP_Q16to19", .pme_code = 0x727e6, .pme_short_desc = "Memory read queue dispatched to queues 16-19", .pme_long_desc = "A memory operation was dispatched to read queue 16,17,18 or 19. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", }, [ POWER5p_PME_PM_FLUSH_IMBAL ] = { .pme_name = "PM_FLUSH_IMBAL", .pme_code = 0x330e3, .pme_short_desc = "Flush caused by thread GCT imbalance", .pme_long_desc = "This thread has been flushed at dispatch because it is stalled and a GCT imbalance exists. GCT thresholds are set in the TSCR register. This allows the other thread to have more machine resources for it to make progress while this thread is stalled.", }, [ POWER5p_PME_PM_THRD_PRIO_DIFF_minus3or4_CYC ] = { .pme_name = "PM_THRD_PRIO_DIFF_minus3or4_CYC", .pme_code = 0x430e1, .pme_short_desc = "Cycles thread priority difference is -3 or -4", .pme_long_desc = "Cycles when this thread's priority is lower than the other thread's priority by 3 or 4.", }, [ POWER5p_PME_PM_DATA_FROM_L35_MOD ] = { .pme_name = "PM_DATA_FROM_L35_MOD", .pme_code = 0x2c309e, .pme_short_desc = "Data loaded from L3.5 modified", .pme_long_desc = "The processor's Data Cache was reloaded with modified (M) data from the L3 of a chip on the same module as this processor is located due to a demand load.", }, [ POWER5p_PME_PM_MEM_HI_PRIO_WR_CMPL ] = { .pme_name = "PM_MEM_HI_PRIO_WR_CMPL", .pme_code = 0x726e6, .pme_short_desc = "High priority write completed", .pme_long_desc = "A memory write, which was upgraded to high priority, completed. Writes can be upgraded to high priority to ensure that read traffic does not lock out writes. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", }, [ POWER5p_PME_PM_FPU1_FDIV ] = { .pme_name = "PM_FPU1_FDIV", .pme_code = 0xc4, .pme_short_desc = "FPU1 executed FDIV instruction", .pme_long_desc = "FPU1 has executed a divide instruction. This could be fdiv, fdivs, fdiv. fdivs.", }, [ POWER5p_PME_PM_MEM_RQ_DISP ] = { .pme_name = "PM_MEM_RQ_DISP", .pme_code = 0x701c6, .pme_short_desc = "Memory read queue dispatched", .pme_long_desc = "A memory read was dispatched. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", }, [ POWER5p_PME_PM_FPU0_FRSP_FCONV ] = { .pme_name = "PM_FPU0_FRSP_FCONV", .pme_code = 0x10c1, .pme_short_desc = "FPU0 executed FRSP or FCONV instructions", .pme_long_desc = "FPU0 has executed a frsp or convert kind of instruction. This could be frsp*, fcfid*, fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs.", }, [ POWER5p_PME_PM_LWSYNC_HELD ] = { .pme_name = "PM_LWSYNC_HELD", .pme_code = 0x130e0, .pme_short_desc = "LWSYNC held at dispatch", .pme_long_desc = "Cycles a LWSYNC instruction was held at dispatch. LWSYNC instructions are held at dispatch until all previous loads are done and all previous stores have issued. LWSYNC enters the Store Request Queue and is sent to the storage subsystem but does not wait for a response.", }, [ POWER5p_PME_PM_FXU_FIN ] = { .pme_name = "PM_FXU_FIN", .pme_code = 0x313088, .pme_short_desc = "FXU produced a result", .pme_long_desc = "The fixed point unit (Unit 0 + Unit 1) finished an instruction. Instructions that finish may not necessary complete.", }, [ POWER5p_PME_PM_DSLB_MISS ] = { .pme_name = "PM_DSLB_MISS", .pme_code = 0x800c5, .pme_short_desc = "Data SLB misses", .pme_long_desc = "A SLB miss for a data request occurred. SLB misses trap to the operating system to resolve.", }, [ POWER5p_PME_PM_DATA_FROM_L275_SHR ] = { .pme_name = "PM_DATA_FROM_L275_SHR", .pme_code = 0x3c3097, .pme_short_desc = "Data loaded from L2.75 shared", .pme_long_desc = "The processor's Data Cache was reloaded with shared (T) data from the L2 on a different module than this processor is located due to a demand load.", }, [ POWER5p_PME_PM_FXLS1_FULL_CYC ] = { .pme_name = "PM_FXLS1_FULL_CYC", .pme_code = 0x110c4, .pme_short_desc = "Cycles FXU1/LS1 queue full", .pme_long_desc = "The issue queue that feeds the Fixed Point unit 1 / Load Store Unit 1 is full. This condition will prevent dispatch groups from being dispatched. This event only indicates that the queue was full, not that dispatch was prevented.", }, [ POWER5p_PME_PM_THRD_SEL_T0 ] = { .pme_name = "PM_THRD_SEL_T0", .pme_code = 0x410c0, .pme_short_desc = "Decode selected thread 0", .pme_long_desc = "Thread selection picked thread 0 for decode.", }, [ POWER5p_PME_PM_PTEG_RELOAD_VALID ] = { .pme_name = "PM_PTEG_RELOAD_VALID", .pme_code = 0x830e4, .pme_short_desc = "PTEG reload valid", .pme_long_desc = "A Page Table Entry was loaded into the TLB.", }, [ POWER5p_PME_PM_MRK_STCX_FAIL ] = { .pme_name = "PM_MRK_STCX_FAIL", .pme_code = 0x820e6, .pme_short_desc = "Marked STCX failed", .pme_long_desc = "A marked stcx (stwcx or stdcx) failed", }, [ POWER5p_PME_PM_LSU_LMQ_LHR_MERGE ] = { .pme_name = "PM_LSU_LMQ_LHR_MERGE", .pme_code = 0xc70e5, .pme_short_desc = "LMQ LHR merges", .pme_long_desc = "A data cache miss occurred for the same real cache line address as an earlier request already in the Load Miss Queue and was merged into the LMQ entry.", }, [ POWER5p_PME_PM_2INST_CLB_CYC ] = { .pme_name = "PM_2INST_CLB_CYC", .pme_code = 0x400c2, .pme_short_desc = "Cycles 2 instructions in CLB", .pme_long_desc = "The cache line buffer (CLB) is a 6-deep, 4-wide instruction buffer. Fullness is reported on a cycle basis with each event representing the number of cycles the CLB had the corresponding number of entries occupied. These events give a real time history of the number of instruction buffers used, but not the number of PowerPC instructions within those buffers. Each thread has its own set of CLB; these events are thread specific.", }, [ POWER5p_PME_PM_FAB_PNtoVN_DIRECT ] = { .pme_name = "PM_FAB_PNtoVN_DIRECT", .pme_code = 0x723e7, .pme_short_desc = "PN to VN beat went straight to its destination", .pme_long_desc = "Fabric Data beats that the base chip takes the inbound PN data and passes it through to the outbound VN bus without going into a sidecar. The signal is delivered at FBC speed and the count must be scaled accordingly.", }, [ POWER5p_PME_PM_PTEG_FROM_L2MISS ] = { .pme_name = "PM_PTEG_FROM_L2MISS", .pme_code = 0x38309b, .pme_short_desc = "PTEG loaded from L2 miss", .pme_long_desc = "A Page Table Entry was loaded into the TLB but not from the local L2.", }, [ POWER5p_PME_PM_CMPLU_STALL_LSU ] = { .pme_name = "PM_CMPLU_STALL_LSU", .pme_code = 0x211098, .pme_short_desc = "Completion stall caused by LSU instruction", .pme_long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes was a load/store instruction.", }, [ POWER5p_PME_PM_MRK_DSLB_MISS ] = { .pme_name = "PM_MRK_DSLB_MISS", .pme_code = 0xc50c7, .pme_short_desc = "Marked Data SLB misses", .pme_long_desc = "A Data SLB miss was caused by a marked instruction.", }, [ POWER5p_PME_PM_LSU_FLUSH_ULD ] = { .pme_name = "PM_LSU_FLUSH_ULD", .pme_code = 0x1c0088, .pme_short_desc = "LRQ unaligned load flushes", .pme_long_desc = "A load was flushed because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1). Combined Unit 0 + 1.", }, [ POWER5p_PME_PM_PTEG_FROM_LMEM ] = { .pme_name = "PM_PTEG_FROM_LMEM", .pme_code = 0x283087, .pme_short_desc = "PTEG loaded from local memory", .pme_long_desc = "A Page Table Entry was loaded into the TLB from memory attached to the same module this proccessor is located on.", }, [ POWER5p_PME_PM_MRK_BRU_FIN ] = { .pme_name = "PM_MRK_BRU_FIN", .pme_code = 0x200005, .pme_short_desc = "Marked instruction BRU processing finished", .pme_long_desc = "The branch unit finished a marked instruction. Instructions that finish may not necessary complete.", }, [ POWER5p_PME_PM_MEM_WQ_DISP_WRITE ] = { .pme_name = "PM_MEM_WQ_DISP_WRITE", .pme_code = 0x703c6, .pme_short_desc = "Memory write queue dispatched due to write", .pme_long_desc = "A memory write was dispatched to a write queue. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", }, [ POWER5p_PME_PM_MRK_DATA_FROM_L275_MOD_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L275_MOD_CYC", .pme_code = 0x4c70a3, .pme_short_desc = "Marked load latency from L2.75 modified", .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.", }, [ POWER5p_PME_PM_LSU1_NCLD ] = { .pme_name = "PM_LSU1_NCLD", .pme_code = 0xc50c5, .pme_short_desc = "LSU1 non-cacheable loads", .pme_long_desc = "A non-cacheable load was executed by Unit 0.", }, [ POWER5p_PME_PM_L2SA_RCLD_DISP_FAIL_OTHER ] = { .pme_name = "PM_L2SA_RCLD_DISP_FAIL_OTHER", .pme_code = 0x731e0, .pme_short_desc = "L2 slice A RC load dispatch attempt failed due to other reasons", .pme_long_desc = "A Read/Claim dispatch for a load failed for some reason other than Full or Collision conditions.", }, [ POWER5p_PME_PM_SNOOP_PW_RETRY_WQ_PWQ ] = { .pme_name = "PM_SNOOP_PW_RETRY_WQ_PWQ", .pme_code = 0x717c6, .pme_short_desc = "Snoop partial-write retry due to collision with active write or partial-write queue", .pme_long_desc = "A snoop request for a partial write to memory was retried because it matched the cache line of an active write or partial write. When this happens the snoop request is retried and the active write is changed to high priority. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", }, [ POWER5p_PME_PM_FPU1_FULL_CYC ] = { .pme_name = "PM_FPU1_FULL_CYC", .pme_code = 0x100c7, .pme_short_desc = "Cycles FPU1 issue queue full", .pme_long_desc = "The issue queue for FPU1 cannot accept any more instructions. Dispatch to this issue queue is stopped", }, [ POWER5p_PME_PM_FPR_MAP_FULL_CYC ] = { .pme_name = "PM_FPR_MAP_FULL_CYC", .pme_code = 0x100c1, .pme_short_desc = "Cycles FPR mapper full", .pme_long_desc = "The floating point unit has executed an add, mult, sub, compare, fsel, fneg, fabs, fnabs, fres, or frsqrte kind of instruction. These are single FLOP operations.", }, [ POWER5p_PME_PM_L3SA_ALL_BUSY ] = { .pme_name = "PM_L3SA_ALL_BUSY", .pme_code = 0x721e3, .pme_short_desc = "L3 slice A active for every cycle all CI/CO machines busy", .pme_long_desc = "Cycles All Castin/Castout machines are busy.", }, [ POWER5p_PME_PM_3INST_CLB_CYC ] = { .pme_name = "PM_3INST_CLB_CYC", .pme_code = 0x400c3, .pme_short_desc = "Cycles 3 instructions in CLB", .pme_long_desc = "The cache line buffer (CLB) is a 6-deep, 4-wide instruction buffer. Fullness is reported on a cycle basis with each event representing the number of cycles the CLB had the corresponding number of entries occupied. These events give a real time history of the number of instruction buffers used, but not the number of PowerPC instructions within those buffers. Each thread has its own set of CLB; these events are thread specific.", }, [ POWER5p_PME_PM_MEM_PWQ_DISP_Q2or3 ] = { .pme_name = "PM_MEM_PWQ_DISP_Q2or3", .pme_code = 0x734e6, .pme_short_desc = "Memory partial-write queue dispatched to Write Queue 2 or 3", .pme_long_desc = "Memory partial-write queue dispatched to Write Queue 2 or 3. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", }, [ POWER5p_PME_PM_L2SA_SHR_INV ] = { .pme_name = "PM_L2SA_SHR_INV", .pme_code = 0x710c0, .pme_short_desc = "L2 slice A transition from shared to invalid", .pme_long_desc = "A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L, or Tagged) to the Invalid state. This transition was caused by any external snoop request. The event is provided on each of the three slices A, B, and C. NOTE: For this event to be useful the tablewalk duration event should also be counted.", }, [ POWER5p_PME_PM_THRESH_TIMEO ] = { .pme_name = "PM_THRESH_TIMEO", .pme_code = 0x30000b, .pme_short_desc = "Threshold timeout", .pme_long_desc = "The threshold timer expired", }, [ POWER5p_PME_PM_L2SA_RC_DISP_FAIL_CO_BUSY_ALL ] = { .pme_name = "PM_L2SA_RC_DISP_FAIL_CO_BUSY_ALL", .pme_code = 0x713c0, .pme_short_desc = "L2 slice A RC dispatch attempt failed due to all CO busy", .pme_long_desc = "A Read/Claim dispatch was rejected because all Castout machines were busy.", }, [ POWER5p_PME_PM_THRD_SEL_OVER_GCT_IMBAL ] = { .pme_name = "PM_THRD_SEL_OVER_GCT_IMBAL", .pme_code = 0x410c4, .pme_short_desc = "Thread selection overrides caused by GCT imbalance", .pme_long_desc = "Thread selection was overridden because of a GCT imbalance.", }, [ POWER5p_PME_PM_FPU_FSQRT ] = { .pme_name = "PM_FPU_FSQRT", .pme_code = 0x200090, .pme_short_desc = "FPU executed FSQRT instruction", .pme_long_desc = "The floating point unit has executed a square root instruction. This could be fsqrt* where XYZ* means XYZ, XYZs, XYZ., XYZs. Combined Unit 0 + Unit 1.", }, [ POWER5p_PME_PM_PMC1_OVERFLOW ] = { .pme_name = "PM_PMC1_OVERFLOW", .pme_code = 0x20000a, .pme_short_desc = "PMC1 Overflow", .pme_long_desc = "Overflows from PMC1 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.", }, [ POWER5p_PME_PM_MRK_LSU0_FLUSH_LRQ ] = { .pme_name = "PM_MRK_LSU0_FLUSH_LRQ", .pme_code = 0x810c2, .pme_short_desc = "LSU0 marked LRQ flushes", .pme_long_desc = "A marked load was flushed by unit 0 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.", }, [ POWER5p_PME_PM_L3SC_SNOOP_RETRY ] = { .pme_name = "PM_L3SC_SNOOP_RETRY", .pme_code = 0x731e5, .pme_short_desc = "L3 slice C snoop retries", .pme_long_desc = "Number of times an L3 retried a snoop because it got two in at the same time (one on snp_a, one on snp_b)", }, [ POWER5p_PME_PM_DATA_TABLEWALK_CYC ] = { .pme_name = "PM_DATA_TABLEWALK_CYC", .pme_code = 0x800c7, .pme_short_desc = "Cycles doing data tablewalks", .pme_long_desc = "Cycles a translation tablewalk is active. While a tablewalk is active any request attempting to access the TLB will be rejected and retried.", }, [ POWER5p_PME_PM_THRD_PRIO_6_CYC ] = { .pme_name = "PM_THRD_PRIO_6_CYC", .pme_code = 0x420e5, .pme_short_desc = "Cycles thread running at priority level 6", .pme_long_desc = "Cycles this thread was running at priority level 6.", }, [ POWER5p_PME_PM_FPU_FEST ] = { .pme_name = "PM_FPU_FEST", .pme_code = 0x1010a8, .pme_short_desc = "FPU executed FEST instruction", .pme_long_desc = "The floating point unit has executed an estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ. Combined Unit 0 + Unit 1.", }, [ POWER5p_PME_PM_FAB_M1toP1_SIDECAR_EMPTY ] = { .pme_name = "PM_FAB_M1toP1_SIDECAR_EMPTY", .pme_code = 0x702c7, .pme_short_desc = "M1 to P1 sidecar empty", .pme_long_desc = "Fabric cycles when the Minus-1 hip/hop sidecars (sidecars for chip to chip data transfer) are empty. The signal is delivered at FBC speed and the count must be scaled accordingly.", }, [ POWER5p_PME_PM_MRK_DATA_FROM_RMEM ] = { .pme_name = "PM_MRK_DATA_FROM_RMEM", .pme_code = 0x1c70a1, .pme_short_desc = "Marked data loaded from remote memory", .pme_long_desc = "The processor's Data Cache was reloaded due to a marked load from memory attached to a different module than this proccessor is located on.", }, [ POWER5p_PME_PM_MRK_DATA_FROM_L35_MOD_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L35_MOD_CYC", .pme_code = 0x4c70a6, .pme_short_desc = "Marked load latency from L3.5 modified", .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.", }, [ POWER5p_PME_PM_MEM_PWQ_DISP ] = { .pme_name = "PM_MEM_PWQ_DISP", .pme_code = 0x704c6, .pme_short_desc = "Memory partial-write queue dispatched", .pme_long_desc = "Number of Partial Writes dispatched. The MC provides resources to gather partial cacheline writes (Partial line DMA writes & CI-stores) to up to four different cachelines at a time. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", }, [ POWER5p_PME_PM_FAB_P1toM1_SIDECAR_EMPTY ] = { .pme_name = "PM_FAB_P1toM1_SIDECAR_EMPTY", .pme_code = 0x701c7, .pme_short_desc = "P1 to M1 sidecar empty", .pme_long_desc = "Fabric cycles when the Plus-1 hip/hop sidecars (sidecars for chip to chip data transfer) are empty. The signal is delivered at FBC speed and the count must be scaled accordingly.", }, [ POWER5p_PME_PM_LD_MISS_L1_LSU0 ] = { .pme_name = "PM_LD_MISS_L1_LSU0", .pme_code = 0xc10c2, .pme_short_desc = "LSU0 L1 D cache load misses", .pme_long_desc = "Load references that miss the Level 1 Data cache, by unit 0.", }, [ POWER5p_PME_PM_SNOOP_PARTIAL_RTRY_QFULL ] = { .pme_name = "PM_SNOOP_PARTIAL_RTRY_QFULL", .pme_code = 0x730e6, .pme_short_desc = "Snoop partial write retry due to partial-write queues full", .pme_long_desc = "A snoop request for a partial write to memory was retried because the write queues that handle partial writes were full. When this happens the active writes are changed to high priority. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", }, [ POWER5p_PME_PM_FPU1_STALL3 ] = { .pme_name = "PM_FPU1_STALL3", .pme_code = 0x20e5, .pme_short_desc = "FPU1 stalled in pipe3", .pme_long_desc = "FPU1 has generated a stall in pipe3 due to overflow, underflow, massive cancel, convert to integer (sometimes), or convert from integer (always).", }, [ POWER5p_PME_PM_GCT_USAGE_80to99_CYC ] = { .pme_name = "PM_GCT_USAGE_80to99_CYC", .pme_code = 0x30001f, .pme_short_desc = "Cycles GCT 80-99% full", .pme_long_desc = "Cycles when the Global Completion Table has between 80% and 99% of its slots used. The GCT has 20 entries shared between threads", }, [ POWER5p_PME_PM_WORK_HELD ] = { .pme_name = "PM_WORK_HELD", .pme_code = 0x40000c, .pme_short_desc = "Work held", .pme_long_desc = "RAS Unit has signaled completion to stop and there are groups waiting to complete", }, [ POWER5p_PME_PM_INST_CMPL ] = { .pme_name = "PM_INST_CMPL", .pme_code = 0x100009, .pme_short_desc = "Instructions completed", .pme_long_desc = "Number of PowerPC instructions that completed.", }, [ POWER5p_PME_PM_LSU1_FLUSH_UST ] = { .pme_name = "PM_LSU1_FLUSH_UST", .pme_code = 0xc00c5, .pme_short_desc = "LSU1 unaligned store flushes", .pme_long_desc = "A store was flushed from unit 1 because it was unaligned (crossed a 4K boundary)", }, [ POWER5p_PME_PM_FXU_IDLE ] = { .pme_name = "PM_FXU_IDLE", .pme_code = 0x100012, .pme_short_desc = "FXU idle", .pme_long_desc = "FXU0 and FXU1 are both idle.", }, [ POWER5p_PME_PM_LSU0_FLUSH_ULD ] = { .pme_name = "PM_LSU0_FLUSH_ULD", .pme_code = 0xc00c0, .pme_short_desc = "LSU0 unaligned load flushes", .pme_long_desc = "A load was flushed from unit 0 because it was unaligned (crossed a 64 byte boundary, or 32 byte if it missed the L1)", }, [ POWER5p_PME_PM_LSU1_REJECT_LMQ_FULL ] = { .pme_name = "PM_LSU1_REJECT_LMQ_FULL", .pme_code = 0xc40c5, .pme_short_desc = "LSU1 reject due to LMQ full or missed data coming", .pme_long_desc = "Total cycles the Load Store Unit 1 is busy rejecting instructions because the Load Miss Queue was full. The LMQ has eight entries. If all eight entries are full, subsequent load instructions are rejected.", }, [ POWER5p_PME_PM_GRP_DISP_REJECT ] = { .pme_name = "PM_GRP_DISP_REJECT", .pme_code = 0x120e4, .pme_short_desc = "Group dispatch rejected", .pme_long_desc = "A group that previously attempted dispatch was rejected.", }, [ POWER5p_PME_PM_PTEG_FROM_L25_SHR ] = { .pme_name = "PM_PTEG_FROM_L25_SHR", .pme_code = 0x183097, .pme_short_desc = "PTEG loaded from L2.5 shared", .pme_long_desc = "A Page Table Entry was loaded into the TLB with shared (T or SL) data from the L2 of a chip on the same module as this processor is located due to a demand load.", }, [ POWER5p_PME_PM_L2SA_MOD_INV ] = { .pme_name = "PM_L2SA_MOD_INV", .pme_code = 0x730e0, .pme_short_desc = "L2 slice A transition from modified to invalid", .pme_long_desc = "A cache line in the local L2 directory made a state transition from the Modified state to the Invalid state. This transition was caused by any RWITM snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A, B, and C.", }, [ POWER5p_PME_PM_FAB_CMD_RETRIED ] = { .pme_name = "PM_FAB_CMD_RETRIED", .pme_code = 0x710c7, .pme_short_desc = "Fabric command retried", .pme_long_desc = "Incremented when a command issued by a chip on its SnoopA address bus is retried for any reason. The overwhelming majority of retries are due to running out of memory controller queues but retries can also be caused by trying to reference addresses that are in a transient cache state -- e.g. a line is transient after issuing a DCLAIM instruction to a shared line but before the associated store completes. Each chip reports its own counts. The signal is delivered at FBC speed and the count must be scaled accordingly.", }, [ POWER5p_PME_PM_L3SA_SHR_INV ] = { .pme_name = "PM_L3SA_SHR_INV", .pme_code = 0x710c3, .pme_short_desc = "L3 slice A transition from shared to invalid", .pme_long_desc = "L3 snooper detects someone doing a store to a line that is Sx in this L3(i.e. invalidate hit SX and dispatched).", }, [ POWER5p_PME_PM_L2SB_RC_DISP_FAIL_CO_BUSY_ALL ] = { .pme_name = "PM_L2SB_RC_DISP_FAIL_CO_BUSY_ALL", .pme_code = 0x713c1, .pme_short_desc = "L2 slice B RC dispatch attempt failed due to all CO busy", .pme_long_desc = "A Read/Claim dispatch was rejected because all Castout machines were busy.", }, [ POWER5p_PME_PM_L2SA_RCST_DISP_FAIL_ADDR ] = { .pme_name = "PM_L2SA_RCST_DISP_FAIL_ADDR", .pme_code = 0x712c0, .pme_short_desc = "L2 slice A RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ", .pme_long_desc = "A Read/Claim dispatch for a store failed because of an address conflict. Two RC machines will never both work on the same line or line in the same congruence class at the same time.", }, [ POWER5p_PME_PM_L2SA_RCLD_DISP_FAIL_RC_FULL ] = { .pme_name = "PM_L2SA_RCLD_DISP_FAIL_RC_FULL", .pme_code = 0x721e0, .pme_short_desc = "L2 slice A RC load dispatch attempt failed due to all RC full", .pme_long_desc = "A Read/Claim dispatch for a load failed because all RC machines are busy.", }, [ POWER5p_PME_PM_PTEG_FROM_L375_MOD ] = { .pme_name = "PM_PTEG_FROM_L375_MOD", .pme_code = 0x1830a7, .pme_short_desc = "PTEG loaded from L3.75 modified", .pme_long_desc = "A Page Table Entry was loaded into the TLB with modified (M) data from the L3 of a chip on a different module than this processor is located, due to a demand load.", }, [ POWER5p_PME_PM_MRK_LSU1_FLUSH_UST ] = { .pme_name = "PM_MRK_LSU1_FLUSH_UST", .pme_code = 0x810c5, .pme_short_desc = "LSU1 marked unaligned store flushes", .pme_long_desc = "A marked store was flushed from unit 1 because it was unaligned (crossed a 4k boundary)", }, [ POWER5p_PME_PM_BR_ISSUED ] = { .pme_name = "PM_BR_ISSUED", .pme_code = 0x230e4, .pme_short_desc = "Branches issued", .pme_long_desc = "A branch instruction was issued to the branch unit. A branch that was incorrectly predicted may issue and execute multiple times.", }, [ POWER5p_PME_PM_MRK_GRP_BR_REDIR ] = { .pme_name = "PM_MRK_GRP_BR_REDIR", .pme_code = 0x212091, .pme_short_desc = "Group experienced marked branch redirect", .pme_long_desc = "A group containing a marked (sampled) instruction experienced a branch redirect.", }, [ POWER5p_PME_PM_EE_OFF ] = { .pme_name = "PM_EE_OFF", .pme_code = 0x130e3, .pme_short_desc = "Cycles MSR(EE) bit off", .pme_long_desc = "Cycles MSR(EE) bit was off indicating that interrupts due to external exceptions were masked.", }, [ POWER5p_PME_PM_IERAT_XLATE_WR_LP ] = { .pme_name = "PM_IERAT_XLATE_WR_LP", .pme_code = 0x210c6, .pme_short_desc = "Large page translation written to ierat", .pme_long_desc = "An entry was written into the IERAT as a result of an IERAT miss. This event can be used to count IERAT misses. An ERAT miss that are later ignored will not be counted unless the ERAT is written before the instruction stream is changed.", }, [ POWER5p_PME_PM_DTLB_REF_64K ] = { .pme_name = "PM_DTLB_REF_64K", .pme_code = 0x2c2086, .pme_short_desc = "Data TLB reference for 64K page", .pme_long_desc = "Data TLB references for 64KB pages. Includes hits + misses.", }, [ POWER5p_PME_PM_MEM_RQ_DISP_Q4to7 ] = { .pme_name = "PM_MEM_RQ_DISP_Q4to7", .pme_code = 0x712c6, .pme_short_desc = "Memory read queue dispatched to queues 4-7", .pme_long_desc = "A memory operation was dispatched to read queue 4,5,6 or 7. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", }, [ POWER5p_PME_PM_MEM_FAST_PATH_RD_DISP ] = { .pme_name = "PM_MEM_FAST_PATH_RD_DISP", .pme_code = 0x731e6, .pme_short_desc = "Fast path memory read dispatched", .pme_long_desc = "Fast path memory read dispatched", }, [ POWER5p_PME_PM_INST_FROM_L3 ] = { .pme_name = "PM_INST_FROM_L3", .pme_code = 0x12208d, .pme_short_desc = "Instruction fetched from L3", .pme_long_desc = "An instruction fetch group was fetched from the local L3. Fetch groups can contain up to 8 instructions", }, [ POWER5p_PME_PM_ITLB_MISS ] = { .pme_name = "PM_ITLB_MISS", .pme_code = 0x800c0, .pme_short_desc = "Instruction TLB misses", .pme_long_desc = "A TLB miss for an Instruction Fetch has occurred", }, [ POWER5p_PME_PM_FXU1_BUSY_FXU0_IDLE ] = { .pme_name = "PM_FXU1_BUSY_FXU0_IDLE", .pme_code = 0x400012, .pme_short_desc = "FXU1 busy FXU0 idle", .pme_long_desc = "FXU0 was idle while FXU1 was busy.", }, [ POWER5p_PME_PM_DTLB_REF_4K ] = { .pme_name = "PM_DTLB_REF_4K", .pme_code = 0x1c2086, .pme_short_desc = "Data TLB reference for 4K page", .pme_long_desc = "Data TLB references for 4KB pages. Includes hits + misses.", }, [ POWER5p_PME_PM_FXLS_FULL_CYC ] = { .pme_name = "PM_FXLS_FULL_CYC", .pme_code = 0x1110a8, .pme_short_desc = "Cycles FXLS queue is full", .pme_long_desc = "Cycles when the issue queues for one or both FXU/LSU units is full. Use with caution since this is the sum of cycles when Unit 0 was full plus Unit 1 full. It does not indicate when both units were full.", }, [ POWER5p_PME_PM_GRP_DISP_VALID ] = { .pme_name = "PM_GRP_DISP_VALID", .pme_code = 0x120e3, .pme_short_desc = "Group dispatch valid", .pme_long_desc = "A group is available for dispatch. This does not mean it was successfully dispatched.", }, [ POWER5p_PME_PM_LSU_FLUSH_UST ] = { .pme_name = "PM_LSU_FLUSH_UST", .pme_code = 0x2c0088, .pme_short_desc = "SRQ unaligned store flushes", .pme_long_desc = "A store was flushed because it was unaligned (crossed a 4K boundary). Combined Unit 0 + 1.", }, [ POWER5p_PME_PM_FXU1_FIN ] = { .pme_name = "PM_FXU1_FIN", .pme_code = 0x130e6, .pme_short_desc = "FXU1 produced a result", .pme_long_desc = "The Fixed Point unit 1 finished an instruction and produced a result. Instructions that finish may not necessary complete.", }, [ POWER5p_PME_PM_THRD_PRIO_4_CYC ] = { .pme_name = "PM_THRD_PRIO_4_CYC", .pme_code = 0x420e3, .pme_short_desc = "Cycles thread running at priority level 4", .pme_long_desc = "Cycles this thread was running at priority level 4.", }, [ POWER5p_PME_PM_MRK_DATA_FROM_L35_MOD ] = { .pme_name = "PM_MRK_DATA_FROM_L35_MOD", .pme_code = 0x2c709e, .pme_short_desc = "Marked data loaded from L3.5 modified", .pme_long_desc = "The processor's Data Cache was reloaded with modified (M) data from the L3 of a chip on the same module as this processor is located due to a marked load.", }, [ POWER5p_PME_PM_4INST_CLB_CYC ] = { .pme_name = "PM_4INST_CLB_CYC", .pme_code = 0x400c4, .pme_short_desc = "Cycles 4 instructions in CLB", .pme_long_desc = "The cache line buffer (CLB) is a 6-deep, 4-wide instruction buffer. Fullness is reported on a cycle basis with each event representing the number of cycles the CLB had the corresponding number of entries occupied. These events give a real time history of the number of instruction buffers used, but not the number of PowerPC instructions within those buffers. Each thread has its own set of CLB; these events are thread specific.", }, [ POWER5p_PME_PM_MRK_DTLB_REF_16M ] = { .pme_name = "PM_MRK_DTLB_REF_16M", .pme_code = 0x3c6086, .pme_short_desc = "Marked Data TLB reference for 16M page", .pme_long_desc = "Data TLB references by a marked instruction for 16MB pages.", }, [ POWER5p_PME_PM_INST_FROM_L375_MOD ] = { .pme_name = "PM_INST_FROM_L375_MOD", .pme_code = 0x42209d, .pme_short_desc = "Instruction fetched from L3.75 modified", .pme_long_desc = "An instruction fetch group was fetched with modified (M) data from the L3 of a chip on a different module than this processor is located. Fetch groups can contain up to 8 instructions", }, [ POWER5p_PME_PM_GRP_CMPL ] = { .pme_name = "PM_GRP_CMPL", .pme_code = 0x300013, .pme_short_desc = "Group completed", .pme_long_desc = "A group completed. Microcoded instructions that span multiple groups will generate this event once per group.", }, [ POWER5p_PME_PM_L2SC_RCST_DISP_FAIL_ADDR ] = { .pme_name = "PM_L2SC_RCST_DISP_FAIL_ADDR", .pme_code = 0x712c2, .pme_short_desc = "L2 slice C RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ", .pme_long_desc = "A Read/Claim dispatch for a store failed because of an address conflict. Two RC machines will never both work on the same line or line in the same congruence class at the same time.", }, [ POWER5p_PME_PM_FPU1_1FLOP ] = { .pme_name = "PM_FPU1_1FLOP", .pme_code = 0xc7, .pme_short_desc = "FPU1 executed add, mult, sub, cmp or sel instruction", .pme_long_desc = "The floating point unit has executed an add, mult, sub, compare, fsel, fneg, fabs, fnabs, fres, or frsqrte kind of instruction. These are single FLOP operations.", }, [ POWER5p_PME_PM_FPU_FRSP_FCONV ] = { .pme_name = "PM_FPU_FRSP_FCONV", .pme_code = 0x2010a8, .pme_short_desc = "FPU executed FRSP or FCONV instructions", .pme_long_desc = "The floating point unit has executed a frsp or convert kind of instruction. This could be frsp*, fcfid*, fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs. Combined Unit 0 + Unit 1.", }, [ POWER5p_PME_PM_L3SC_REF ] = { .pme_name = "PM_L3SC_REF", .pme_code = 0x701c5, .pme_short_desc = "L3 slice C references", .pme_long_desc = "Number of attempts made by this chip cores to find data in the L3. Reported per L3 slice.", }, [ POWER5p_PME_PM_5INST_CLB_CYC ] = { .pme_name = "PM_5INST_CLB_CYC", .pme_code = 0x400c5, .pme_short_desc = "Cycles 5 instructions in CLB", .pme_long_desc = "The cache line buffer (CLB) is a 6-deep, 4-wide instruction buffer. Fullness is reported on a cycle basis with each event representing the number of cycles the CLB had the corresponding number of entries occupied. These events give a real time history of the number of instruction buffers used, but not the number of PowerPC instructions within those buffers. Each thread has its own set of CLB; these events are thread specific.", }, [ POWER5p_PME_PM_THRD_L2MISS_BOTH_CYC ] = { .pme_name = "PM_THRD_L2MISS_BOTH_CYC", .pme_code = 0x410c7, .pme_short_desc = "Cycles both threads in L2 misses", .pme_long_desc = "Cycles that both threads have L2 miss pending. If only one thread has a L2 miss pending the other thread is given priority at decode. If both threads have L2 miss pending decode priority is determined by the number of GCT entries used.", }, [ POWER5p_PME_PM_MEM_PW_GATH ] = { .pme_name = "PM_MEM_PW_GATH", .pme_code = 0x714c6, .pme_short_desc = "Memory partial-write gathered", .pme_long_desc = "Two or more partial-writes have been merged into a single memory write. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", }, [ POWER5p_PME_PM_DTLB_REF_16G ] = { .pme_name = "PM_DTLB_REF_16G", .pme_code = 0x4c2086, .pme_short_desc = "Data TLB reference for 16G page", .pme_long_desc = "Data TLB references for 16GB pages. Includes hits + misses.", }, [ POWER5p_PME_PM_FAB_DCLAIM_ISSUED ] = { .pme_name = "PM_FAB_DCLAIM_ISSUED", .pme_code = 0x720e7, .pme_short_desc = "dclaim issued", .pme_long_desc = "A DCLAIM command was issued. Each chip reports its own counts. The signal is delivered at FBC speed and the count must be scaled accordingly.", }, [ POWER5p_PME_PM_FAB_PNtoNN_SIDECAR ] = { .pme_name = "PM_FAB_PNtoNN_SIDECAR", .pme_code = 0x713c7, .pme_short_desc = "PN to NN beat went to sidecar first", .pme_long_desc = "Fabric Data beats that the base chip takes the inbound PN data and forwards it on to the outbound NN data bus after going into a sidecar first. The signal is delivered at FBC speed and the count must be scaled.", }, [ POWER5p_PME_PM_GRP_IC_MISS ] = { .pme_name = "PM_GRP_IC_MISS", .pme_code = 0x120e7, .pme_short_desc = "Group experienced I cache miss", .pme_long_desc = "Number of groups, counted at dispatch, that have encountered an icache miss redirect. Every group constructed from a fetch group that missed the instruction cache will count.", }, [ POWER5p_PME_PM_INST_FROM_L35_SHR ] = { .pme_name = "PM_INST_FROM_L35_SHR", .pme_code = 0x12209d, .pme_short_desc = "Instruction fetched from L3.5 shared", .pme_long_desc = "An instruction fetch group was fetched with shared (S) data from the L3 of a chip on the same module as this processor is located. Fetch groups can contain up to 8 instructions", }, [ POWER5p_PME_PM_LSU_LMQ_FULL_CYC ] = { .pme_name = "PM_LSU_LMQ_FULL_CYC", .pme_code = 0xc30e7, .pme_short_desc = "Cycles LMQ full", .pme_long_desc = "The Load Miss Queue was full.", }, [ POWER5p_PME_PM_MRK_DATA_FROM_L2_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L2_CYC", .pme_code = 0x2c70a0, .pme_short_desc = "Marked load latency from L2", .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.", }, [ POWER5p_PME_PM_LSU_SRQ_SYNC_CYC ] = { .pme_name = "PM_LSU_SRQ_SYNC_CYC", .pme_code = 0x830e5, .pme_short_desc = "SRQ sync duration", .pme_long_desc = "Cycles that a sync instruction is active in the Store Request Queue.", }, [ POWER5p_PME_PM_LSU0_BUSY_REJECT ] = { .pme_name = "PM_LSU0_BUSY_REJECT", .pme_code = 0xc20e1, .pme_short_desc = "LSU0 busy due to reject", .pme_long_desc = "Total cycles the Load Store Unit 0 is busy rejecting instructions.", }, [ POWER5p_PME_PM_LSU_REJECT_ERAT_MISS ] = { .pme_name = "PM_LSU_REJECT_ERAT_MISS", .pme_code = 0x1c4090, .pme_short_desc = "LSU reject due to ERAT miss", .pme_long_desc = "Total cycles the Load Store Unit is busy rejecting instructions due to an ERAT miss. Combined unit 0 + 1. Requests that miss the Derat are rejected and retried until the request hits in the Erat.", }, [ POWER5p_PME_PM_MRK_DATA_FROM_RMEM_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_RMEM_CYC", .pme_code = 0x4c70a1, .pme_short_desc = "Marked load latency from remote memory", .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.", }, [ POWER5p_PME_PM_DATA_FROM_L375_SHR ] = { .pme_name = "PM_DATA_FROM_L375_SHR", .pme_code = 0x3c309e, .pme_short_desc = "Data loaded from L3.75 shared", .pme_long_desc = "The processor's Data Cache was reloaded with shared (S) data from the L3 of a chip on a different module than this processor is located due to a demand load.", }, [ POWER5p_PME_PM_PTEG_FROM_L25_MOD ] = { .pme_name = "PM_PTEG_FROM_L25_MOD", .pme_code = 0x283097, .pme_short_desc = "PTEG loaded from L2.5 modified", .pme_long_desc = "A Page Table Entry was loaded into the TLB with modified (M) data from the L2 of a chip on the same module as this processor is located due to a demand load.", }, [ POWER5p_PME_PM_FPU0_FMOV_FEST ] = { .pme_name = "PM_FPU0_FMOV_FEST", .pme_code = 0x10c0, .pme_short_desc = "FPU0 executed FMOV or FEST instructions", .pme_long_desc = "FPU0 has executed a move kind of instruction or one of the estimate instructions. This could be fmr*, fneg*, fabs*, fnabs* , fres* or frsqrte* where XYZ* means XYZ or XYZ.", }, [ POWER5p_PME_PM_THRD_PRIO_7_CYC ] = { .pme_name = "PM_THRD_PRIO_7_CYC", .pme_code = 0x420e6, .pme_short_desc = "Cycles thread running at priority level 7", .pme_long_desc = "Cycles this thread was running at priority level 7.", }, [ POWER5p_PME_PM_LSU1_FLUSH_SRQ ] = { .pme_name = "PM_LSU1_FLUSH_SRQ", .pme_code = 0xc00c7, .pme_short_desc = "LSU1 SRQ lhs flushes", .pme_long_desc = "A store was flushed because younger load hits and older store that is already in the SRQ or in the same group.", }, [ POWER5p_PME_PM_LD_REF_L1_LSU0 ] = { .pme_name = "PM_LD_REF_L1_LSU0", .pme_code = 0xc10c0, .pme_short_desc = "LSU0 L1 D cache load references", .pme_long_desc = "Load references to Level 1 Data Cache, by unit 0.", }, [ POWER5p_PME_PM_L2SC_RCST_DISP ] = { .pme_name = "PM_L2SC_RCST_DISP", .pme_code = 0x702c2, .pme_short_desc = "L2 slice C RC store dispatch attempt", .pme_long_desc = "A Read/Claim dispatch for a Store was attempted.", }, [ POWER5p_PME_PM_CMPLU_STALL_DIV ] = { .pme_name = "PM_CMPLU_STALL_DIV", .pme_code = 0x411099, .pme_short_desc = "Completion stall caused by DIV instruction", .pme_long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes was a fixed point divide instruction. This is a subset of PM_CMPLU_STALL_FXU.", }, [ POWER5p_PME_PM_MEM_RQ_DISP_Q12to15 ] = { .pme_name = "PM_MEM_RQ_DISP_Q12to15", .pme_code = 0x732e6, .pme_short_desc = "Memory read queue dispatched to queues 12-15", .pme_long_desc = "A memory operation was dispatched to read queue 12,13,14 or 15. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", }, [ POWER5p_PME_PM_INST_FROM_L375_SHR ] = { .pme_name = "PM_INST_FROM_L375_SHR", .pme_code = 0x32209d, .pme_short_desc = "Instruction fetched from L3.75 shared", .pme_long_desc = "An instruction fetch group was fetched with shared (S) data from the L3 of a chip on a different module than this processor is located. Fetch groups can contain up to 8 instructions", }, [ POWER5p_PME_PM_ST_REF_L1 ] = { .pme_name = "PM_ST_REF_L1", .pme_code = 0x2c10a8, .pme_short_desc = "L1 D cache store references", .pme_long_desc = "Store references to the Data Cache. Combined Unit 0 + 1.", }, [ POWER5p_PME_PM_L3SB_ALL_BUSY ] = { .pme_name = "PM_L3SB_ALL_BUSY", .pme_code = 0x721e4, .pme_short_desc = "L3 slice B active for every cycle all CI/CO machines busy", .pme_long_desc = "Cycles All Castin/Castout machines are busy.", }, [ POWER5p_PME_PM_FAB_P1toVNorNN_SIDECAR_EMPTY ] = { .pme_name = "PM_FAB_P1toVNorNN_SIDECAR_EMPTY", .pme_code = 0x711c7, .pme_short_desc = "P1 to VN/NN sidecar empty", .pme_long_desc = "Fabric cycles when the Plus-1 jump sidecar (sidecars for mcm to mcm data transfer) is empty. The signal is delivered at FBC speed and the count must be scaled accordingly.", }, [ POWER5p_PME_PM_MRK_DATA_FROM_L275_SHR_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L275_SHR_CYC", .pme_code = 0x2c70a3, .pme_short_desc = "Marked load latency from L2.75 shared", .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.", }, [ POWER5p_PME_PM_FAB_HOLDtoNN_EMPTY ] = { .pme_name = "PM_FAB_HOLDtoNN_EMPTY", .pme_code = 0x722e7, .pme_short_desc = "Hold buffer to NN empty", .pme_long_desc = "Fabric cyles when the Next Node out hold-buffers are emtpy. The signal is delivered at FBC speed and the count must be scaled accordingly.", }, [ POWER5p_PME_PM_DATA_FROM_LMEM ] = { .pme_name = "PM_DATA_FROM_LMEM", .pme_code = 0x2c3087, .pme_short_desc = "Data loaded from local memory", .pme_long_desc = "The processor's Data Cache was reloaded from memory attached to the same module this proccessor is located on.", }, [ POWER5p_PME_PM_RUN_CYC ] = { .pme_name = "PM_RUN_CYC", .pme_code = 0x100005, .pme_short_desc = "Run cycles", .pme_long_desc = "Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.", }, [ POWER5p_PME_PM_PTEG_FROM_RMEM ] = { .pme_name = "PM_PTEG_FROM_RMEM", .pme_code = 0x1830a1, .pme_short_desc = "PTEG loaded from remote memory", .pme_long_desc = "A Page Table Entry was loaded into the TLB from memory attached to a different module than this proccessor is located on.", }, [ POWER5p_PME_PM_L2SC_RCLD_DISP ] = { .pme_name = "PM_L2SC_RCLD_DISP", .pme_code = 0x701c2, .pme_short_desc = "L2 slice C RC load dispatch attempt", .pme_long_desc = "A Read/Claim dispatch for a Load was attempted", }, [ POWER5p_PME_PM_LSU_LRQ_S0_VALID ] = { .pme_name = "PM_LSU_LRQ_S0_VALID", .pme_code = 0xc60e6, .pme_short_desc = "LRQ slot 0 valid", .pme_long_desc = "This signal is asserted every cycle that the Load Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin. In SMT mode the LRQ is split between the two threads (16 entries each).", }, [ POWER5p_PME_PM_LSU0_LDF ] = { .pme_name = "PM_LSU0_LDF", .pme_code = 0xc50c0, .pme_short_desc = "LSU0 executed Floating Point load instruction", .pme_long_desc = "A floating point load was executed by LSU0", }, [ POWER5p_PME_PM_PMC3_OVERFLOW ] = { .pme_name = "PM_PMC3_OVERFLOW", .pme_code = 0x40000a, .pme_short_desc = "PMC3 Overflow", .pme_long_desc = "Overflows from PMC3 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.", }, [ POWER5p_PME_PM_MRK_IMR_RELOAD ] = { .pme_name = "PM_MRK_IMR_RELOAD", .pme_code = 0x820e2, .pme_short_desc = "Marked IMR reloaded", .pme_long_desc = "A DL1 reload occurred due to marked load", }, [ POWER5p_PME_PM_MRK_GRP_TIMEO ] = { .pme_name = "PM_MRK_GRP_TIMEO", .pme_code = 0x40000b, .pme_short_desc = "Marked group completion timeout", .pme_long_desc = "The sampling timeout expired indicating that the previously sampled instruction is no longer in the processor", }, [ POWER5p_PME_PM_ST_MISS_L1 ] = { .pme_name = "PM_ST_MISS_L1", .pme_code = 0xc10c3, .pme_short_desc = "L1 D cache store misses", .pme_long_desc = "A store missed the dcache. Combined Unit 0 + 1.", }, [ POWER5p_PME_PM_STOP_COMPLETION ] = { .pme_name = "PM_STOP_COMPLETION", .pme_code = 0x300018, .pme_short_desc = "Completion stopped", .pme_long_desc = "RAS Unit has signaled completion to stop", }, [ POWER5p_PME_PM_LSU_BUSY_REJECT ] = { .pme_name = "PM_LSU_BUSY_REJECT", .pme_code = 0x2c2088, .pme_short_desc = "LSU busy due to reject", .pme_long_desc = "Total cycles the Load Store Unit is busy rejecting instructions. Combined unit 0 + 1.", }, [ POWER5p_PME_PM_ISLB_MISS ] = { .pme_name = "PM_ISLB_MISS", .pme_code = 0x800c1, .pme_short_desc = "Instruction SLB misses", .pme_long_desc = "A SLB miss for an instruction fetch as occurred", }, [ POWER5p_PME_PM_CYC ] = { .pme_name = "PM_CYC", .pme_code = 0xf, .pme_short_desc = "Processor cycles", .pme_long_desc = "Processor cycles", }, [ POWER5p_PME_PM_THRD_ONE_RUN_CYC ] = { .pme_name = "PM_THRD_ONE_RUN_CYC", .pme_code = 0x10000b, .pme_short_desc = "One of the threads in run cycles", .pme_long_desc = "At least one thread has set its run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. This event does not respect FCWAIT.", }, [ POWER5p_PME_PM_GRP_BR_REDIR_NONSPEC ] = { .pme_name = "PM_GRP_BR_REDIR_NONSPEC", .pme_code = 0x112091, .pme_short_desc = "Group experienced non-speculative branch redirect", .pme_long_desc = "Number of groups, counted at completion, that have encountered a branch redirect.", }, [ POWER5p_PME_PM_LSU1_SRQ_STFWD ] = { .pme_name = "PM_LSU1_SRQ_STFWD", .pme_code = 0xc60e5, .pme_short_desc = "LSU1 SRQ store forwarded", .pme_long_desc = "Data from a store instruction was forwarded to a load on unit 1. A load that misses L1 but becomes a store forward is treated as a load miss and it causes the DL1 load miss event to be counted. It does not go into the LMQ. If a load that hits L1 but becomes a store forward, then it's not treated as a load miss.", }, [ POWER5p_PME_PM_L3SC_MOD_INV ] = { .pme_name = "PM_L3SC_MOD_INV", .pme_code = 0x730e5, .pme_short_desc = "L3 slice C transition from modified to invalid", .pme_long_desc = "L3 snooper detects someone doing a store to a line that is truly M in this L3 (i.e. L3 going M=>I) Mu|Me are not included since they are formed due to a previous read op Tx is not included since it is considered shared at this point.", }, [ POWER5p_PME_PM_L2_PREF ] = { .pme_name = "PM_L2_PREF", .pme_code = 0xc50c3, .pme_short_desc = "L2 cache prefetches", .pme_long_desc = "A request to prefetch data into L2 was made", }, [ POWER5p_PME_PM_GCT_NOSLOT_BR_MPRED ] = { .pme_name = "PM_GCT_NOSLOT_BR_MPRED", .pme_code = 0x41009c, .pme_short_desc = "No slot in GCT caused by branch mispredict", .pme_long_desc = "Cycles when the Global Completion Table has no slots from this thread because of a branch misprediction.", }, [ POWER5p_PME_PM_MRK_DATA_FROM_L25_MOD ] = { .pme_name = "PM_MRK_DATA_FROM_L25_MOD", .pme_code = 0x2c7097, .pme_short_desc = "Marked data loaded from L2.5 modified", .pme_long_desc = "The processor's Data Cache was reloaded with modified (M) data from the L2 of a chip on the same module as this processor is located due to a marked load.", }, [ POWER5p_PME_PM_L2SB_ST_REQ ] = { .pme_name = "PM_L2SB_ST_REQ", .pme_code = 0x723e1, .pme_short_desc = "L2 slice B store requests", .pme_long_desc = "A store request as seen at the L2 directory has been made from the core. Stores are counted after gathering in the L2 store queues. The event is provided on each of the three slices A, B, and C.", }, [ POWER5p_PME_PM_L2SB_MOD_INV ] = { .pme_name = "PM_L2SB_MOD_INV", .pme_code = 0x730e1, .pme_short_desc = "L2 slice B transition from modified to invalid", .pme_long_desc = "A cache line in the local L2 directory made a state transition from the Modified state to the Invalid state. This transition was caused by any RWITM snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A, B, and C.", }, [ POWER5p_PME_PM_MRK_L1_RELOAD_VALID ] = { .pme_name = "PM_MRK_L1_RELOAD_VALID", .pme_code = 0xc70e4, .pme_short_desc = "Marked L1 reload data source valid", .pme_long_desc = "The source information is valid and is for a marked load", }, [ POWER5p_PME_PM_L3SB_HIT ] = { .pme_name = "PM_L3SB_HIT", .pme_code = 0x711c4, .pme_short_desc = "L3 slice B hits", .pme_long_desc = "Number of attempts made by this chip cores that resulted in an L3 hit. Reported per L3 slice", }, [ POWER5p_PME_PM_L2SB_SHR_MOD ] = { .pme_name = "PM_L2SB_SHR_MOD", .pme_code = 0x700c1, .pme_short_desc = "L2 slice B transition from shared to modified", .pme_long_desc = "A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L , or Tagged) to the Modified state. This transition was caused by a store from either of the two local CPUs to a cache line in any of the Shared states. The event is provided on each of the three slices A, B, and C.", }, [ POWER5p_PME_PM_EE_OFF_EXT_INT ] = { .pme_name = "PM_EE_OFF_EXT_INT", .pme_code = 0x130e7, .pme_short_desc = "Cycles MSR(EE) bit off and external interrupt pending", .pme_long_desc = "Cycles when an interrupt due to an external exception is pending but external exceptions were masked.", }, [ POWER5p_PME_PM_1PLUS_PPC_CMPL ] = { .pme_name = "PM_1PLUS_PPC_CMPL", .pme_code = 0x100013, .pme_short_desc = "One or more PPC instruction completed", .pme_long_desc = "A group containing at least one PPC instruction completed. For microcoded instructions that span multiple groups, this will only occur once.", }, [ POWER5p_PME_PM_L2SC_SHR_MOD ] = { .pme_name = "PM_L2SC_SHR_MOD", .pme_code = 0x700c2, .pme_short_desc = "L2 slice C transition from shared to modified", .pme_long_desc = "A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L , or Tagged) to the Modified state. This transition was caused by a store from either of the two local CPUs to a cache line in any of the Shared states. The event is provided on each of the three slices A, B, and C.", }, [ POWER5p_PME_PM_PMC6_OVERFLOW ] = { .pme_name = "PM_PMC6_OVERFLOW", .pme_code = 0x30001a, .pme_short_desc = "PMC6 Overflow", .pme_long_desc = "Overflows from PMC6 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.", }, [ POWER5p_PME_PM_IC_PREF_INSTALL ] = { .pme_name = "PM_IC_PREF_INSTALL", .pme_code = 0x210c7, .pme_short_desc = "Instruction prefetched installed in prefetch buffer", .pme_long_desc = "A prefetch buffer entry (line) is allocated but the request is not a demand fetch.", }, [ POWER5p_PME_PM_LSU_LRQ_FULL_CYC ] = { .pme_name = "PM_LSU_LRQ_FULL_CYC", .pme_code = 0x110c2, .pme_short_desc = "Cycles LRQ full", .pme_long_desc = "Cycles when the LRQ is full.", }, [ POWER5p_PME_PM_TLB_MISS ] = { .pme_name = "PM_TLB_MISS", .pme_code = 0x180088, .pme_short_desc = "TLB misses", .pme_long_desc = "Total of Data TLB mises + Instruction TLB misses", }, [ POWER5p_PME_PM_GCT_FULL_CYC ] = { .pme_name = "PM_GCT_FULL_CYC", .pme_code = 0x100c0, .pme_short_desc = "Cycles GCT full", .pme_long_desc = "The Global Completion Table is completely full.", }, [ POWER5p_PME_PM_FXU_BUSY ] = { .pme_name = "PM_FXU_BUSY", .pme_code = 0x200012, .pme_short_desc = "FXU busy", .pme_long_desc = "Cycles when both FXU0 and FXU1 are busy.", }, [ POWER5p_PME_PM_MRK_DATA_FROM_L3_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L3_CYC", .pme_code = 0x2c70a4, .pme_short_desc = "Marked load latency from L3", .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.", }, [ POWER5p_PME_PM_LSU_REJECT_LMQ_FULL ] = { .pme_name = "PM_LSU_REJECT_LMQ_FULL", .pme_code = 0x2c4088, .pme_short_desc = "LSU reject due to LMQ full or missed data coming", .pme_long_desc = "Total cycles the Load Store Unit is busy rejecting instructions because the Load Miss Queue was full. The LMQ has eight entries. If all the eight entries are full, subsequent load instructions are rejected. Combined unit 0 + 1.", }, [ POWER5p_PME_PM_LSU_SRQ_S0_ALLOC ] = { .pme_name = "PM_LSU_SRQ_S0_ALLOC", .pme_code = 0xc20e7, .pme_short_desc = "SRQ slot 0 allocated", .pme_long_desc = "SRQ Slot zero was allocated", }, [ POWER5p_PME_PM_GRP_MRK ] = { .pme_name = "PM_GRP_MRK", .pme_code = 0x100014, .pme_short_desc = "Group marked in IDU", .pme_long_desc = "A group was sampled (marked). The group is called a marked group. One instruction within the group is tagged for detailed monitoring. The sampled instruction is called a marked instructions. Events associated with the marked instruction are annotated with the marked term.", }, [ POWER5p_PME_PM_INST_FROM_L25_SHR ] = { .pme_name = "PM_INST_FROM_L25_SHR", .pme_code = 0x122096, .pme_short_desc = "Instruction fetched from L2.5 shared", .pme_long_desc = "An instruction fetch group was fetched with shared (T or SL) data from the L2 of a chip on the same module as this processor is located. Fetch groups can contain up to 8 instructions.", }, [ POWER5p_PME_PM_DC_PREF_STREAM_ALLOC ] = { .pme_name = "PM_DC_PREF_STREAM_ALLOC", .pme_code = 0x830e7, .pme_short_desc = "D cache new prefetch stream allocated", .pme_long_desc = "A new Prefetch Stream was allocated.", }, [ POWER5p_PME_PM_FPU1_FIN ] = { .pme_name = "PM_FPU1_FIN", .pme_code = 0x10c7, .pme_short_desc = "FPU1 produced a result", .pme_long_desc = "FPU1 finished, produced a result. This only indicates finish, not completion. Floating Point Stores are included in this count but not Floating Point Loads., ,", }, [ POWER5p_PME_PM_BR_MPRED_TA ] = { .pme_name = "PM_BR_MPRED_TA", .pme_code = 0x230e6, .pme_short_desc = "Branch mispredictions due to target address", .pme_long_desc = "A branch instruction target was incorrectly predicted. This will result in a branch mispredict flush unless a flush is detected from an older instruction.", }, [ POWER5p_PME_PM_MRK_DTLB_REF_64K ] = { .pme_name = "PM_MRK_DTLB_REF_64K", .pme_code = 0x2c6086, .pme_short_desc = "Marked Data TLB reference for 64K page", .pme_long_desc = "Data TLB references by a marked instruction for 64KB pages.", }, [ POWER5p_PME_PM_RUN_INST_CMPL ] = { .pme_name = "PM_RUN_INST_CMPL", .pme_code = 0x500009, .pme_short_desc = "Run instructions completed", .pme_long_desc = "Number of run instructions completed.", }, [ POWER5p_PME_PM_CRQ_FULL_CYC ] = { .pme_name = "PM_CRQ_FULL_CYC", .pme_code = 0x110c1, .pme_short_desc = "Cycles CR issue queue full", .pme_long_desc = "The issue queue that feeds the Conditional Register unit is full. This condition will prevent dispatch groups from being dispatched. This event only indicates that the queue was full, not that dispatch was prevented.", }, [ POWER5p_PME_PM_L2SA_RCLD_DISP ] = { .pme_name = "PM_L2SA_RCLD_DISP", .pme_code = 0x701c0, .pme_short_desc = "L2 slice A RC load dispatch attempt", .pme_long_desc = "A Read/Claim dispatch for a Load was attempted", }, [ POWER5p_PME_PM_SNOOP_WR_RETRY_QFULL ] = { .pme_name = "PM_SNOOP_WR_RETRY_QFULL", .pme_code = 0x710c6, .pme_short_desc = "Snoop read retry due to read queue full", .pme_long_desc = "A snoop request for a write to memory was retried because the write queues were full. When this happens the snoop request is retried and the writes in the write reorder queue are changed to high priority. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", }, [ POWER5p_PME_PM_MRK_DTLB_REF_4K ] = { .pme_name = "PM_MRK_DTLB_REF_4K", .pme_code = 0x1c6086, .pme_short_desc = "Marked Data TLB reference for 4K page", .pme_long_desc = "Data TLB references by a marked instruction for 4KB pages.", }, [ POWER5p_PME_PM_LSU_SRQ_S0_VALID ] = { .pme_name = "PM_LSU_SRQ_S0_VALID", .pme_code = 0xc20e6, .pme_short_desc = "SRQ slot 0 valid", .pme_long_desc = "This signal is asserted every cycle that the Store Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin. In SMT mode the SRQ is split between the two threads (16 entries each).", }, [ POWER5p_PME_PM_LSU0_FLUSH_LRQ ] = { .pme_name = "PM_LSU0_FLUSH_LRQ", .pme_code = 0xc00c2, .pme_short_desc = "LSU0 LRQ flushes", .pme_long_desc = "A load was flushed by unit 0 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.", }, [ POWER5p_PME_PM_INST_FROM_L275_MOD ] = { .pme_name = "PM_INST_FROM_L275_MOD", .pme_code = 0x422096, .pme_short_desc = "Instruction fetched from L2.75 modified", .pme_long_desc = "An instruction fetch group was fetched with modified (M) data from the L2 on a different module than this processor is located. Fetch groups can contain up to 8 instructions", }, [ POWER5p_PME_PM_GCT_EMPTY_CYC ] = { .pme_name = "PM_GCT_EMPTY_CYC", .pme_code = 0x200004, .pme_short_desc = "Cycles GCT empty", .pme_long_desc = "The Global Completion Table is completely empty", }, [ POWER5p_PME_PM_LARX_LSU0 ] = { .pme_name = "PM_LARX_LSU0", .pme_code = 0x820e7, .pme_short_desc = "Larx executed on LSU0", .pme_long_desc = "A larx (lwarx or ldarx) was executed on side 0 (there is no corresponding unit 1 event since larx instructions can only execute on unit 0)", }, [ POWER5p_PME_PM_THRD_PRIO_DIFF_5or6_CYC ] = { .pme_name = "PM_THRD_PRIO_DIFF_5or6_CYC", .pme_code = 0x430e6, .pme_short_desc = "Cycles thread priority difference is 5 or 6", .pme_long_desc = "Cycles when this thread's priority is higher than the other thread's priority by 5 or 6.", }, [ POWER5p_PME_PM_SNOOP_RETRY_1AHEAD ] = { .pme_name = "PM_SNOOP_RETRY_1AHEAD", .pme_code = 0x725e6, .pme_short_desc = "Snoop retry due to one ahead collision", .pme_long_desc = "Snoop retry due to one ahead collision", }, [ POWER5p_PME_PM_FPU1_FSQRT ] = { .pme_name = "PM_FPU1_FSQRT", .pme_code = 0xc6, .pme_short_desc = "FPU1 executed FSQRT instruction", .pme_long_desc = "FPU1 has executed a square root instruction. This could be fsqrt* where XYZ* means XYZ, XYZs, XYZ., XYZs.", }, [ POWER5p_PME_PM_MRK_LD_MISS_L1_LSU1 ] = { .pme_name = "PM_MRK_LD_MISS_L1_LSU1", .pme_code = 0x820e4, .pme_short_desc = "LSU1 marked L1 D cache load misses", .pme_long_desc = "Load references that miss the Level 1 Data cache, by LSU1.", }, [ POWER5p_PME_PM_MRK_FPU_FIN ] = { .pme_name = "PM_MRK_FPU_FIN", .pme_code = 0x300014, .pme_short_desc = "Marked instruction FPU processing finished", .pme_long_desc = "One of the Floating Point Units finished a marked instruction. Instructions that finish may not necessary complete", }, [ POWER5p_PME_PM_THRD_PRIO_5_CYC ] = { .pme_name = "PM_THRD_PRIO_5_CYC", .pme_code = 0x420e4, .pme_short_desc = "Cycles thread running at priority level 5", .pme_long_desc = "Cycles this thread was running at priority level 5.", }, [ POWER5p_PME_PM_MRK_DATA_FROM_LMEM ] = { .pme_name = "PM_MRK_DATA_FROM_LMEM", .pme_code = 0x2c7087, .pme_short_desc = "Marked data loaded from local memory", .pme_long_desc = "The processor's Data Cache was reloaded due to a marked load from memory attached to the same module this proccessor is located on.", }, [ POWER5p_PME_PM_SNOOP_TLBIE ] = { .pme_name = "PM_SNOOP_TLBIE", .pme_code = 0x800c3, .pme_short_desc = "Snoop TLBIE", .pme_long_desc = "A tlbie was snooped from another processor.", }, [ POWER5p_PME_PM_FPU1_FRSP_FCONV ] = { .pme_name = "PM_FPU1_FRSP_FCONV", .pme_code = 0x10c5, .pme_short_desc = "FPU1 executed FRSP or FCONV instructions", .pme_long_desc = "FPU1 has executed a frsp or convert kind of instruction. This could be frsp*, fcfid*, fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs.", }, [ POWER5p_PME_PM_DTLB_MISS_16G ] = { .pme_name = "PM_DTLB_MISS_16G", .pme_code = 0x4c208d, .pme_short_desc = "Data TLB miss for 16G page", .pme_long_desc = "Data TLB references to 16GB pages that missed the TLB. Page size is determined at TLB reload time.", }, [ POWER5p_PME_PM_L3SB_SNOOP_RETRY ] = { .pme_name = "PM_L3SB_SNOOP_RETRY", .pme_code = 0x731e4, .pme_short_desc = "L3 slice B snoop retries", .pme_long_desc = "Number of times an L3 retried a snoop because it got two in at the same time (one on snp_a, one on snp_b)", }, [ POWER5p_PME_PM_FAB_VBYPASS_EMPTY ] = { .pme_name = "PM_FAB_VBYPASS_EMPTY", .pme_code = 0x731e7, .pme_short_desc = "Vertical bypass buffer empty", .pme_long_desc = "Fabric cycles when the Middle Bypass sidecar is empty. The signal is delivered at FBC speed and the count must be scaled accordingly.", }, [ POWER5p_PME_PM_MRK_DATA_FROM_L275_MOD ] = { .pme_name = "PM_MRK_DATA_FROM_L275_MOD", .pme_code = 0x1c70a3, .pme_short_desc = "Marked data loaded from L2.75 modified", .pme_long_desc = "The processor's Data Cache was reloaded with modified (M) data from the L2 on a different module than this processor is located due to a marked load.", }, [ POWER5p_PME_PM_L2SB_RCST_DISP ] = { .pme_name = "PM_L2SB_RCST_DISP", .pme_code = 0x702c1, .pme_short_desc = "L2 slice B RC store dispatch attempt", .pme_long_desc = "A Read/Claim dispatch for a Store was attempted.", }, [ POWER5p_PME_PM_6INST_CLB_CYC ] = { .pme_name = "PM_6INST_CLB_CYC", .pme_code = 0x400c6, .pme_short_desc = "Cycles 6 instructions in CLB", .pme_long_desc = "The cache line buffer (CLB) is a 6-deep, 4-wide instruction buffer. Fullness is reported on a cycle basis with each event representing the number of cycles the CLB had the corresponding number of entries occupied. These events give a real time history of the number of instruction buffers used, but not the number of PowerPC instructions within those buffers. Each thread has its own set of CLB; these events are thread specific.", }, [ POWER5p_PME_PM_FLUSH ] = { .pme_name = "PM_FLUSH", .pme_code = 0x110c7, .pme_short_desc = "Flushes", .pme_long_desc = "Flushes occurred including LSU and Branch flushes.", }, [ POWER5p_PME_PM_L2SC_MOD_INV ] = { .pme_name = "PM_L2SC_MOD_INV", .pme_code = 0x730e2, .pme_short_desc = "L2 slice C transition from modified to invalid", .pme_long_desc = "A cache line in the local L2 directory made a state transition from the Modified state to the Invalid state. This transition was caused by any RWITM snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A, B, and C.", }, [ POWER5p_PME_PM_FPU_DENORM ] = { .pme_name = "PM_FPU_DENORM", .pme_code = 0x102088, .pme_short_desc = "FPU received denormalized data", .pme_long_desc = "The floating point unit has encountered a denormalized operand. Combined Unit 0 + Unit 1.", }, [ POWER5p_PME_PM_L3SC_HIT ] = { .pme_name = "PM_L3SC_HIT", .pme_code = 0x711c5, .pme_short_desc = "L3 slice C hits", .pme_long_desc = "Number of attempts made by this chip cores that resulted in an L3 hit. Reported per L3 Slice", }, [ POWER5p_PME_PM_SNOOP_WR_RETRY_RQ ] = { .pme_name = "PM_SNOOP_WR_RETRY_RQ", .pme_code = 0x706c6, .pme_short_desc = "Snoop write/dclaim retry due to collision with active read queue", .pme_long_desc = "A snoop request for a write or dclaim to memory was retried because it matched the cacheline of an active read. This event is sent from the Memory Controller clock domain and must be scaled accordingly", }, [ POWER5p_PME_PM_LSU1_REJECT_SRQ ] = { .pme_name = "PM_LSU1_REJECT_SRQ", .pme_code = 0xc40c4, .pme_short_desc = "LSU1 SRQ lhs rejects", .pme_long_desc = "Total cycles the Load Store Unit 1 is busy rejecting instructions because of Load Hit Store conditions. Loads are rejected when data is needed from a previous store instruction but store forwarding is not possible because the data is not fully contained in the Store Data Queue or is not yet available in the Store Data Queue.", }, [ POWER5p_PME_PM_L3SC_ALL_BUSY ] = { .pme_name = "PM_L3SC_ALL_BUSY", .pme_code = 0x721e5, .pme_short_desc = "L3 slice C active for every cycle all CI/CO machines busy", .pme_long_desc = "Cycles All Castin/Castout machines are busy.", }, [ POWER5p_PME_PM_IC_PREF_REQ ] = { .pme_name = "PM_IC_PREF_REQ", .pme_code = 0x220e6, .pme_short_desc = "Instruction prefetch requests", .pme_long_desc = "An instruction prefetch request has been made.", }, [ POWER5p_PME_PM_MRK_GRP_IC_MISS ] = { .pme_name = "PM_MRK_GRP_IC_MISS", .pme_code = 0x412091, .pme_short_desc = "Group experienced marked I cache miss", .pme_long_desc = "A group containing a marked (sampled) instruction experienced an instruction cache miss.", }, [ POWER5p_PME_PM_GCT_NOSLOT_IC_MISS ] = { .pme_name = "PM_GCT_NOSLOT_IC_MISS", .pme_code = 0x21009c, .pme_short_desc = "No slot in GCT caused by I cache miss", .pme_long_desc = "Cycles when the Global Completion Table has no slots from this thread because of an Instruction Cache miss.", }, [ POWER5p_PME_PM_MRK_DATA_FROM_L3 ] = { .pme_name = "PM_MRK_DATA_FROM_L3", .pme_code = 0x1c708e, .pme_short_desc = "Marked data loaded from L3", .pme_long_desc = "The processor's Data Cache was reloaded from the local L3 due to a marked load.", }, [ POWER5p_PME_PM_GCT_NOSLOT_SRQ_FULL ] = { .pme_name = "PM_GCT_NOSLOT_SRQ_FULL", .pme_code = 0x310084, .pme_short_desc = "No slot in GCT caused by SRQ full", .pme_long_desc = "Cycles when the Global Completion Table has no slots from this thread because the Store Request Queue (SRQ) is full. This happens when the storage subsystem can not process the stores in the SRQ. Groups can not be dispatched until a SRQ entry is available.", }, [ POWER5p_PME_PM_CMPLU_STALL_DCACHE_MISS ] = { .pme_name = "PM_CMPLU_STALL_DCACHE_MISS", .pme_code = 0x21109a, .pme_short_desc = "Completion stall caused by D cache miss", .pme_long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes suffered a Data Cache Miss. Data Cache Miss has higher priority than any other Load/Store delay, so if an instruction encounters multiple delays only the Data Cache Miss will be reported and the entire delay period will be charged to Data Cache Miss. This is a subset of PM_CMPLU_STALL_LSU.", }, [ POWER5p_PME_PM_THRD_SEL_OVER_ISU_HOLD ] = { .pme_name = "PM_THRD_SEL_OVER_ISU_HOLD", .pme_code = 0x410c5, .pme_short_desc = "Thread selection overrides caused by ISU holds", .pme_long_desc = "Thread selection was overridden because of an ISU hold.", }, [ POWER5p_PME_PM_LSU_FLUSH_LRQ ] = { .pme_name = "PM_LSU_FLUSH_LRQ", .pme_code = 0x2c0090, .pme_short_desc = "LRQ flushes", .pme_long_desc = "A load was flushed because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte. Combined Units 0 and 1.", }, [ POWER5p_PME_PM_THRD_PRIO_2_CYC ] = { .pme_name = "PM_THRD_PRIO_2_CYC", .pme_code = 0x420e1, .pme_short_desc = "Cycles thread running at priority level 2", .pme_long_desc = "Cycles this thread was running at priority level 2.", }, [ POWER5p_PME_PM_L3SA_MOD_INV ] = { .pme_name = "PM_L3SA_MOD_INV", .pme_code = 0x730e3, .pme_short_desc = "L3 slice A transition from modified to invalid", .pme_long_desc = "L3 snooper detects someone doing a store to a line that is truly M in this L3 (i.e. L3 going M=>I) Mu|Me are not included since they are formed due to a prev read op. Tx is not included since it is considered shared at this point.", }, [ POWER5p_PME_PM_LSU_FLUSH_SRQ ] = { .pme_name = "PM_LSU_FLUSH_SRQ", .pme_code = 0x1c0090, .pme_short_desc = "SRQ flushes", .pme_long_desc = "A store was flushed because younger load hits and older store that is already in the SRQ or in the same group. Combined Unit 0 + 1.", }, [ POWER5p_PME_PM_MRK_LSU_SRQ_INST_VALID ] = { .pme_name = "PM_MRK_LSU_SRQ_INST_VALID", .pme_code = 0xc70e6, .pme_short_desc = "Marked instruction valid in SRQ", .pme_long_desc = "This signal is asserted every cycle when a marked request is resident in the Store Request Queue", }, [ POWER5p_PME_PM_L3SA_REF ] = { .pme_name = "PM_L3SA_REF", .pme_code = 0x701c3, .pme_short_desc = "L3 slice A references", .pme_long_desc = "Number of attempts made by this chip cores to find data in the L3. Reported per L3 slice", }, [ POWER5p_PME_PM_L2SC_RC_DISP_FAIL_CO_BUSY_ALL ] = { .pme_name = "PM_L2SC_RC_DISP_FAIL_CO_BUSY_ALL", .pme_code = 0x713c2, .pme_short_desc = "L2 slice C RC dispatch attempt failed due to all CO busy", .pme_long_desc = "A Read/Claim dispatch was rejected because all Castout machines were busy.", }, [ POWER5p_PME_PM_FPU0_STALL3 ] = { .pme_name = "PM_FPU0_STALL3", .pme_code = 0x20e1, .pme_short_desc = "FPU0 stalled in pipe3", .pme_long_desc = "FPU0 has generated a stall in pipe3 due to overflow, underflow, massive cancel, convert to integer (sometimes), or convert from integer (always).", }, [ POWER5p_PME_PM_TB_BIT_TRANS ] = { .pme_name = "PM_TB_BIT_TRANS", .pme_code = 0x100018, .pme_short_desc = "Time Base bit transition", .pme_long_desc = "When the selected time base bit (as specified in MMCR0[TBSEL])transitions from 0 to 1", }, [ POWER5p_PME_PM_GPR_MAP_FULL_CYC ] = { .pme_name = "PM_GPR_MAP_FULL_CYC", .pme_code = 0x130e5, .pme_short_desc = "Cycles GPR mapper full", .pme_long_desc = "The General Purpose Register mapper cannot accept any more groups. This condition will prevent dispatch groups from being dispatched. This event only indicates that the mapper was full, not that dispatch was prevented.", }, [ POWER5p_PME_PM_MRK_LSU_FLUSH_LRQ ] = { .pme_name = "PM_MRK_LSU_FLUSH_LRQ", .pme_code = 0x381088, .pme_short_desc = "Marked LRQ flushes", .pme_long_desc = "A marked load was flushed because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.", }, [ POWER5p_PME_PM_FPU0_STF ] = { .pme_name = "PM_FPU0_STF", .pme_code = 0x20e2, .pme_short_desc = "FPU0 executed store instruction", .pme_long_desc = "FPU0 has executed a Floating Point Store instruction.", }, [ POWER5p_PME_PM_MRK_DTLB_MISS ] = { .pme_name = "PM_MRK_DTLB_MISS", .pme_code = 0xc50c6, .pme_short_desc = "Marked Data TLB misses", .pme_long_desc = "Data TLB references by a marked instruction that missed the TLB (all page sizes).", }, [ POWER5p_PME_PM_FPU1_FMA ] = { .pme_name = "PM_FPU1_FMA", .pme_code = 0xc5, .pme_short_desc = "FPU1 executed multiply-add instruction", .pme_long_desc = "The floating point unit has executed a multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs.", }, [ POWER5p_PME_PM_L2SA_MOD_TAG ] = { .pme_name = "PM_L2SA_MOD_TAG", .pme_code = 0x720e0, .pme_short_desc = "L2 slice A transition from modified to tagged", .pme_long_desc = "A cache line in the local L2 directory made a state transition from the Modified state to the Tagged state. This transition was caused by a read snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A, B, and C.", }, [ POWER5p_PME_PM_LSU1_FLUSH_ULD ] = { .pme_name = "PM_LSU1_FLUSH_ULD", .pme_code = 0xc00c4, .pme_short_desc = "LSU1 unaligned load flushes", .pme_long_desc = "A load was flushed from unit 1 because it was unaligned (crossed a 64 byte boundary, or 32 byte if it missed the L1).", }, [ POWER5p_PME_PM_MRK_INST_FIN ] = { .pme_name = "PM_MRK_INST_FIN", .pme_code = 0x300005, .pme_short_desc = "Marked instruction finished", .pme_long_desc = "One of the execution units finished a marked instruction. Instructions that finish may not necessary complete", }, [ POWER5p_PME_PM_MRK_LSU0_FLUSH_UST ] = { .pme_name = "PM_MRK_LSU0_FLUSH_UST", .pme_code = 0x810c0, .pme_short_desc = "LSU0 marked unaligned store flushes", .pme_long_desc = "A marked store was flushed from unit 0 because it was unaligned", }, [ POWER5p_PME_PM_FPU0_FULL_CYC ] = { .pme_name = "PM_FPU0_FULL_CYC", .pme_code = 0x100c3, .pme_short_desc = "Cycles FPU0 issue queue full", .pme_long_desc = "The issue queue for FPU0 cannot accept any more instruction. Dispatch to this issue queue is stopped.", }, [ POWER5p_PME_PM_LSU_LRQ_S0_ALLOC ] = { .pme_name = "PM_LSU_LRQ_S0_ALLOC", .pme_code = 0xc60e7, .pme_short_desc = "LRQ slot 0 allocated", .pme_long_desc = "LRQ slot zero was allocated", }, [ POWER5p_PME_PM_MRK_LSU1_FLUSH_ULD ] = { .pme_name = "PM_MRK_LSU1_FLUSH_ULD", .pme_code = 0x810c4, .pme_short_desc = "LSU1 marked unaligned load flushes", .pme_long_desc = "A marked load was flushed from unit 1 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)", }, [ POWER5p_PME_PM_MRK_DTLB_REF ] = { .pme_name = "PM_MRK_DTLB_REF", .pme_code = 0xc60e4, .pme_short_desc = "Marked Data TLB reference", .pme_long_desc = "Total number of Data TLB references by a marked instruction for all page sizes. Page size is determined at TLB reload time.", }, [ POWER5p_PME_PM_BR_UNCOND ] = { .pme_name = "PM_BR_UNCOND", .pme_code = 0x123087, .pme_short_desc = "Unconditional branch", .pme_long_desc = "An unconditional branch was executed.", }, [ POWER5p_PME_PM_THRD_SEL_OVER_L2MISS ] = { .pme_name = "PM_THRD_SEL_OVER_L2MISS", .pme_code = 0x410c3, .pme_short_desc = "Thread selection overrides caused by L2 misses", .pme_long_desc = "Thread selection was overridden because one thread was had a L2 miss pending.", }, [ POWER5p_PME_PM_L2SB_SHR_INV ] = { .pme_name = "PM_L2SB_SHR_INV", .pme_code = 0x710c1, .pme_short_desc = "L2 slice B transition from shared to invalid", .pme_long_desc = "A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L, or Tagged) to the Invalid state. This transition was caused by any external snoop request. The event is provided on each of the three slices A, B, and C. NOTE: For this event to be useful the tablewalk duration event should also be counted.", }, [ POWER5p_PME_PM_MEM_LO_PRIO_WR_CMPL ] = { .pme_name = "PM_MEM_LO_PRIO_WR_CMPL", .pme_code = 0x736e6, .pme_short_desc = "Low priority write completed", .pme_long_desc = "A memory write, which was not upgraded to high priority, completed. This event is sent from the Memory Controller clock domain and must be scaled accordingly", }, [ POWER5p_PME_PM_MRK_DTLB_MISS_64K ] = { .pme_name = "PM_MRK_DTLB_MISS_64K", .pme_code = 0x2c608d, .pme_short_desc = "Marked Data TLB misses for 64K page", .pme_long_desc = "Data TLB references to 64KB pages by a marked instruction that missed the TLB. Page size is determined at TLB reload time.", }, [ POWER5p_PME_PM_MRK_ST_MISS_L1 ] = { .pme_name = "PM_MRK_ST_MISS_L1", .pme_code = 0x820e3, .pme_short_desc = "Marked L1 D cache store misses", .pme_long_desc = "A marked store missed the dcache", }, [ POWER5p_PME_PM_L3SC_MOD_TAG ] = { .pme_name = "PM_L3SC_MOD_TAG", .pme_code = 0x720e5, .pme_short_desc = "L3 slice C transition from modified to TAG", .pme_long_desc = "L3 snooper detects someone doing a read to a line that is truly M in this L3(i.e. L3 going M->T or M->I(go_Mu case); Mu|Me are not included since they are formed due to a prev read op). Tx is not included since it is considered shared at this point.", }, [ POWER5p_PME_PM_GRP_DISP_SUCCESS ] = { .pme_name = "PM_GRP_DISP_SUCCESS", .pme_code = 0x300002, .pme_short_desc = "Group dispatch success", .pme_long_desc = "Number of groups sucessfully dispatched (not rejected)", }, [ POWER5p_PME_PM_THRD_PRIO_DIFF_1or2_CYC ] = { .pme_name = "PM_THRD_PRIO_DIFF_1or2_CYC", .pme_code = 0x430e4, .pme_short_desc = "Cycles thread priority difference is 1 or 2", .pme_long_desc = "Cycles when this thread's priority is higher than the other thread's priority by 1 or 2.", }, [ POWER5p_PME_PM_IC_DEMAND_L2_BHT_REDIRECT ] = { .pme_name = "PM_IC_DEMAND_L2_BHT_REDIRECT", .pme_code = 0x230e0, .pme_short_desc = "L2 I cache demand request due to BHT redirect", .pme_long_desc = "A demand (not prefetch) miss to the instruction cache was sent to the L2 as a result of a branch prediction redirect (CR mispredict).", }, [ POWER5p_PME_PM_LSU_DERAT_MISS ] = { .pme_name = "PM_LSU_DERAT_MISS", .pme_code = 0x280090, .pme_short_desc = "DERAT misses", .pme_long_desc = "Total D-ERAT Misses. Requests that miss the Derat are rejected and retried until the request hits in the Erat. This may result in multiple erat misses for the same instruction. Combined Unit 0 + 1.", }, [ POWER5p_PME_PM_MEM_WQ_DISP_Q8to15 ] = { .pme_name = "PM_MEM_WQ_DISP_Q8to15", .pme_code = 0x733e6, .pme_short_desc = "Memory write queue dispatched to queues 8-15", .pme_long_desc = "A memory operation was dispatched to a write queue in the range between 8 and 15. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", }, [ POWER5p_PME_PM_FPU0_SINGLE ] = { .pme_name = "PM_FPU0_SINGLE", .pme_code = 0x20e3, .pme_short_desc = "FPU0 executed single precision instruction", .pme_long_desc = "FPU0 has executed a single precision instruction.", }, [ POWER5p_PME_PM_THRD_PRIO_1_CYC ] = { .pme_name = "PM_THRD_PRIO_1_CYC", .pme_code = 0x420e0, .pme_short_desc = "Cycles thread running at priority level 1", .pme_long_desc = "Cycles this thread was running at priority level 1. Priority level 1 is the lowest and indicates the thread is sleeping.", }, [ POWER5p_PME_PM_L2SC_RCST_DISP_FAIL_OTHER ] = { .pme_name = "PM_L2SC_RCST_DISP_FAIL_OTHER", .pme_code = 0x732e2, .pme_short_desc = "L2 slice C RC store dispatch attempt failed due to other reasons", .pme_long_desc = "A Read/Claim dispatch for a store failed for some reason other than Full or Collision conditions. Rejected dispatches do not count because they have not yet been attempted.", }, [ POWER5p_PME_PM_SNOOP_RD_RETRY_RQ ] = { .pme_name = "PM_SNOOP_RD_RETRY_RQ", .pme_code = 0x705c6, .pme_short_desc = "Snoop read retry due to collision with active read queue", .pme_long_desc = "A snoop request for a read from memory was retried because it matched the cache line of an active read. The snoop request is retried because the L2 may be able to source data via intervention for the 2nd read faster than the MC. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", }, [ POWER5p_PME_PM_FAB_HOLDtoVN_EMPTY ] = { .pme_name = "PM_FAB_HOLDtoVN_EMPTY", .pme_code = 0x721e7, .pme_short_desc = "Hold buffer to VN empty", .pme_long_desc = "Fabric cycles when the Vertical Node out hold-buffers are emtpy. The signal is delivered at FBC speed and the count must be scaled accordingly.", }, [ POWER5p_PME_PM_FPU1_FEST ] = { .pme_name = "PM_FPU1_FEST", .pme_code = 0x10c6, .pme_short_desc = "FPU1 executed FEST instruction", .pme_long_desc = "FPU1 has executed an estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ.", }, [ POWER5p_PME_PM_SNOOP_DCLAIM_RETRY_QFULL ] = { .pme_name = "PM_SNOOP_DCLAIM_RETRY_QFULL", .pme_code = 0x720e6, .pme_short_desc = "Snoop dclaim/flush retry due to write/dclaim queues full", .pme_long_desc = "The memory controller A memory write was dispatched to a write queue. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", }, [ POWER5p_PME_PM_MRK_DATA_FROM_L25_SHR_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L25_SHR_CYC", .pme_code = 0x2c70a2, .pme_short_desc = "Marked load latency from L2.5 shared", .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.", }, [ POWER5p_PME_PM_MRK_ST_CMPL_INT ] = { .pme_name = "PM_MRK_ST_CMPL_INT", .pme_code = 0x300003, .pme_short_desc = "Marked store completed with intervention", .pme_long_desc = "A marked store previously sent to the memory subsystem completed (data home) after requiring intervention", }, [ POWER5p_PME_PM_FLUSH_BR_MPRED ] = { .pme_name = "PM_FLUSH_BR_MPRED", .pme_code = 0x110c6, .pme_short_desc = "Flush caused by branch mispredict", .pme_long_desc = "A flush was caused by a branch mispredict.", }, [ POWER5p_PME_PM_MRK_DTLB_MISS_16G ] = { .pme_name = "PM_MRK_DTLB_MISS_16G", .pme_code = 0x4c608d, .pme_short_desc = "Marked Data TLB misses for 16G page", .pme_long_desc = "Data TLB references to 16GB pages by a marked instruction that missed the TLB. Page size is determined at TLB reload time.", }, [ POWER5p_PME_PM_FPU_STF ] = { .pme_name = "PM_FPU_STF", .pme_code = 0x202090, .pme_short_desc = "FPU executed store instruction", .pme_long_desc = "FPU has executed a store instruction. Combined Unit 0 + Unit 1.", }, [ POWER5p_PME_PM_L2SB_RCLD_DISP_FAIL_ADDR ] = { .pme_name = "PM_L2SB_RCLD_DISP_FAIL_ADDR", .pme_code = 0x711c1, .pme_short_desc = "L2 slice B RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ", .pme_long_desc = "A Read/Claim dispatch for a load failed because of an address conflict. Two RC machines will never both work on the same line or line in the same congruence class at the same time.", }, [ POWER5p_PME_PM_CMPLU_STALL_FPU ] = { .pme_name = "PM_CMPLU_STALL_FPU", .pme_code = 0x411098, .pme_short_desc = "Completion stall caused by FPU instruction", .pme_long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes was a floating point instruction.", }, [ POWER5p_PME_PM_THRD_PRIO_DIFF_minus1or2_CYC ] = { .pme_name = "PM_THRD_PRIO_DIFF_minus1or2_CYC", .pme_code = 0x430e2, .pme_short_desc = "Cycles thread priority difference is -1 or -2", .pme_long_desc = "Cycles when this thread's priority is lower than the other thread's priority by 1 or 2.", }, [ POWER5p_PME_PM_GCT_NOSLOT_CYC ] = { .pme_name = "PM_GCT_NOSLOT_CYC", .pme_code = 0x100004, .pme_short_desc = "Cycles no GCT slot allocated", .pme_long_desc = "Cycles when the Global Completion Table has no slots from this thread.", }, [ POWER5p_PME_PM_FXU0_BUSY_FXU1_IDLE ] = { .pme_name = "PM_FXU0_BUSY_FXU1_IDLE", .pme_code = 0x300012, .pme_short_desc = "FXU0 busy FXU1 idle", .pme_long_desc = "FXU0 is busy while FXU1 was idle", }, [ POWER5p_PME_PM_PTEG_FROM_L35_SHR ] = { .pme_name = "PM_PTEG_FROM_L35_SHR", .pme_code = 0x18309e, .pme_short_desc = "PTEG loaded from L3.5 shared", .pme_long_desc = "A Page Table Entry was loaded into the TLB with shared (S) data from the L3 of a chip on the same module as this processor is located, due to a demand load.", }, [ POWER5p_PME_PM_MRK_DTLB_REF_16G ] = { .pme_name = "PM_MRK_DTLB_REF_16G", .pme_code = 0x4c6086, .pme_short_desc = "Marked Data TLB reference for 16G page", .pme_long_desc = "Data TLB references by a marked instruction for 16GB pages.", }, [ POWER5p_PME_PM_MRK_LSU_FLUSH_UST ] = { .pme_name = "PM_MRK_LSU_FLUSH_UST", .pme_code = 0x2810a8, .pme_short_desc = "Marked unaligned store flushes", .pme_long_desc = "A marked store was flushed because it was unaligned", }, [ POWER5p_PME_PM_MRK_DATA_FROM_L25_SHR ] = { .pme_name = "PM_MRK_DATA_FROM_L25_SHR", .pme_code = 0x1c7097, .pme_short_desc = "Marked data loaded from L2.5 shared", .pme_long_desc = "The processor's Data Cache was reloaded with shared (T or SL) data from the L2 of a chip on the same module as this processor is located due to a marked load.", }, [ POWER5p_PME_PM_L3SA_HIT ] = { .pme_name = "PM_L3SA_HIT", .pme_code = 0x711c3, .pme_short_desc = "L3 slice A hits", .pme_long_desc = "Number of attempts made by this chip cores that resulted in an L3 hit. Reported per L3 slice", }, [ POWER5p_PME_PM_MRK_DATA_FROM_L35_SHR ] = { .pme_name = "PM_MRK_DATA_FROM_L35_SHR", .pme_code = 0x1c709e, .pme_short_desc = "Marked data loaded from L3.5 shared", .pme_long_desc = "The processor's Data Cache was reloaded with shared (S) data from the L3 of a chip on the same module as this processor is located due to a marked load.", }, [ POWER5p_PME_PM_L2SB_RCST_DISP_FAIL_ADDR ] = { .pme_name = "PM_L2SB_RCST_DISP_FAIL_ADDR", .pme_code = 0x712c1, .pme_short_desc = "L2 slice B RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ", .pme_long_desc = "A Read/Claim dispatch for a store failed because of an address conflict. Two RC machines will never both work on the same line or line in the same congruence class at the same time.", }, [ POWER5p_PME_PM_IERAT_XLATE_WR ] = { .pme_name = "PM_IERAT_XLATE_WR", .pme_code = 0x220e7, .pme_short_desc = "Translation written to ierat", .pme_long_desc = "An entry was written into the IERAT as a result of an IERAT miss. This event can be used to count IERAT misses. An ERAT miss that are later ignored will not be counted unless the ERAT is written before the instruction stream is changed.", }, [ POWER5p_PME_PM_L2SA_ST_REQ ] = { .pme_name = "PM_L2SA_ST_REQ", .pme_code = 0x723e0, .pme_short_desc = "L2 slice A store requests", .pme_long_desc = "A store request as seen at the L2 directory has been made from the core. Stores are counted after gathering in the L2 store queues. The event is provided on each of the three slices A, B, and C.", }, [ POWER5p_PME_PM_INST_FROM_LMEM ] = { .pme_name = "PM_INST_FROM_LMEM", .pme_code = 0x222086, .pme_short_desc = "Instruction fetched from local memory", .pme_long_desc = "An instruction fetch group was fetched from memory attached to the same module this proccessor is located on. Fetch groups can contain up to 8 instructions", }, [ POWER5p_PME_PM_THRD_SEL_T1 ] = { .pme_name = "PM_THRD_SEL_T1", .pme_code = 0x410c1, .pme_short_desc = "Decode selected thread 1", .pme_long_desc = "Thread selection picked thread 1 for decode.", }, [ POWER5p_PME_PM_IC_DEMAND_L2_BR_REDIRECT ] = { .pme_name = "PM_IC_DEMAND_L2_BR_REDIRECT", .pme_code = 0x230e1, .pme_short_desc = "L2 I cache demand request due to branch redirect", .pme_long_desc = "A demand (not prefetch) miss to the instruction cache was sent to the L2 as a result of a branch prediction redirect (either ALL mispredicted or Target).", }, [ POWER5p_PME_PM_MRK_DATA_FROM_L35_SHR_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L35_SHR_CYC", .pme_code = 0x2c70a6, .pme_short_desc = "Marked load latency from L3.5 shared", .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.", }, [ POWER5p_PME_PM_FPU0_1FLOP ] = { .pme_name = "PM_FPU0_1FLOP", .pme_code = 0xc3, .pme_short_desc = "FPU0 executed add, mult, sub, cmp or sel instruction", .pme_long_desc = "The floating point unit has executed an add, mult, sub, compare, fsel, fneg, fabs, fnabs, fres, or frsqrte kind of instruction. These are single FLOP operations.", }, [ POWER5p_PME_PM_PTEG_FROM_L2 ] = { .pme_name = "PM_PTEG_FROM_L2", .pme_code = 0x183087, .pme_short_desc = "PTEG loaded from L2", .pme_long_desc = "A Page Table Entry was loaded into the TLB from the local L2 due to a demand load", }, [ POWER5p_PME_PM_MEM_PW_CMPL ] = { .pme_name = "PM_MEM_PW_CMPL", .pme_code = 0x724e6, .pme_short_desc = "Memory partial-write completed", .pme_long_desc = "Number of Partial Writes completed. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", }, [ POWER5p_PME_PM_THRD_PRIO_DIFF_minus5or6_CYC ] = { .pme_name = "PM_THRD_PRIO_DIFF_minus5or6_CYC", .pme_code = 0x430e0, .pme_short_desc = "Cycles thread priority difference is -5 or -6", .pme_long_desc = "Cycles when this thread's priority is lower than the other thread's priority by 5 or 6.", }, [ POWER5p_PME_PM_L2SB_RCLD_DISP_FAIL_OTHER ] = { .pme_name = "PM_L2SB_RCLD_DISP_FAIL_OTHER", .pme_code = 0x731e1, .pme_short_desc = "L2 slice B RC load dispatch attempt failed due to other reasons", .pme_long_desc = "A Read/Claim dispatch for a load failed for some reason other than Full or Collision conditions.", }, [ POWER5p_PME_PM_MRK_DTLB_MISS_4K ] = { .pme_name = "PM_MRK_DTLB_MISS_4K", .pme_code = 0x1c608d, .pme_short_desc = "Marked Data TLB misses for 4K page", .pme_long_desc = "Data TLB references to 4KB pages by a marked instruction that missed the TLB. Page size is determined at TLB reload time.", }, [ POWER5p_PME_PM_FPU0_FIN ] = { .pme_name = "PM_FPU0_FIN", .pme_code = 0x10c3, .pme_short_desc = "FPU0 produced a result", .pme_long_desc = "FPU0 finished, produced a result. This only indicates finish, not completion. Floating Point Stores are included in this count but not Floating Point Loads.", }, [ POWER5p_PME_PM_L3SC_SHR_INV ] = { .pme_name = "PM_L3SC_SHR_INV", .pme_code = 0x710c5, .pme_short_desc = "L3 slice C transition from shared to invalid", .pme_long_desc = "L3 snooper detects someone doing a store to a line that is Sx in this L3(i.e. invalidate hit SX and dispatched).", }, [ POWER5p_PME_PM_GRP_BR_REDIR ] = { .pme_name = "PM_GRP_BR_REDIR", .pme_code = 0x120e6, .pme_short_desc = "Group experienced branch redirect", .pme_long_desc = "Number of groups, counted at dispatch, that have encountered a branch redirect. Every group constructed from a fetch group that has been redirected will count.", }, [ POWER5p_PME_PM_L2SC_RCLD_DISP_FAIL_RC_FULL ] = { .pme_name = "PM_L2SC_RCLD_DISP_FAIL_RC_FULL", .pme_code = 0x721e2, .pme_short_desc = "L2 slice C RC load dispatch attempt failed due to all RC full", .pme_long_desc = "A Read/Claim dispatch for a load failed because all RC machines are busy.", }, [ POWER5p_PME_PM_MRK_LSU_FLUSH_SRQ ] = { .pme_name = "PM_MRK_LSU_FLUSH_SRQ", .pme_code = 0x481088, .pme_short_desc = "Marked SRQ lhs flushes", .pme_long_desc = "A marked store was flushed because younger load hits and older store that is already in the SRQ or in the same group.", }, [ POWER5p_PME_PM_PTEG_FROM_L275_SHR ] = { .pme_name = "PM_PTEG_FROM_L275_SHR", .pme_code = 0x383097, .pme_short_desc = "PTEG loaded from L2.75 shared", .pme_long_desc = "A Page Table Entry was loaded into the TLB with shared (T) data from the L2 on a different module than this processor is located due to a demand load.", }, [ POWER5p_PME_PM_L2SB_RCLD_DISP_FAIL_RC_FULL ] = { .pme_name = "PM_L2SB_RCLD_DISP_FAIL_RC_FULL", .pme_code = 0x721e1, .pme_short_desc = "L2 slice B RC load dispatch attempt failed due to all RC full", .pme_long_desc = "A Read/Claim dispatch for a load failed because all RC machines are busy.", }, [ POWER5p_PME_PM_SNOOP_RD_RETRY_WQ ] = { .pme_name = "PM_SNOOP_RD_RETRY_WQ", .pme_code = 0x715c6, .pme_short_desc = "Snoop read retry due to collision with active write queue", .pme_long_desc = "A snoop request for a read from memory was retried because it matched the cache line of an active write. The snoop request is retried and the active write is changed to high priority. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", }, [ POWER5p_PME_PM_FAB_DCLAIM_RETRIED ] = { .pme_name = "PM_FAB_DCLAIM_RETRIED", .pme_code = 0x730e7, .pme_short_desc = "dclaim retried", .pme_long_desc = "A DCLAIM command was retried. Each chip reports its own counts. The signal is delivered at FBC speed and the count must be scaled accordingly.", }, [ POWER5p_PME_PM_LSU0_NCLD ] = { .pme_name = "PM_LSU0_NCLD", .pme_code = 0xc50c1, .pme_short_desc = "LSU0 non-cacheable loads", .pme_long_desc = "A non-cacheable load was executed by unit 0.", }, [ POWER5p_PME_PM_LSU1_BUSY_REJECT ] = { .pme_name = "PM_LSU1_BUSY_REJECT", .pme_code = 0xc20e5, .pme_short_desc = "LSU1 busy due to reject", .pme_long_desc = "Total cycles the Load Store Unit 1 is busy rejecting instructions.", }, [ POWER5p_PME_PM_FXLS0_FULL_CYC ] = { .pme_name = "PM_FXLS0_FULL_CYC", .pme_code = 0x110c0, .pme_short_desc = "Cycles FXU0/LS0 queue full", .pme_long_desc = "The issue queue that feeds the Fixed Point unit 0 / Load Store Unit 0 is full. This condition will prevent dispatch groups from being dispatched. This event only indicates that the queue was full, not that dispatch was prevented.", }, [ POWER5p_PME_PM_DTLB_REF_16M ] = { .pme_name = "PM_DTLB_REF_16M", .pme_code = 0x3c2086, .pme_short_desc = "Data TLB reference for 16M page", .pme_long_desc = "Data TLB references for 16MB pages. Includes hits + misses.", }, [ POWER5p_PME_PM_FPU0_FEST ] = { .pme_name = "PM_FPU0_FEST", .pme_code = 0x10c2, .pme_short_desc = "FPU0 executed FEST instruction", .pme_long_desc = "FPU0 has executed an estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ.", }, [ POWER5p_PME_PM_GCT_USAGE_60to79_CYC ] = { .pme_name = "PM_GCT_USAGE_60to79_CYC", .pme_code = 0x20001f, .pme_short_desc = "Cycles GCT 60-79% full", .pme_long_desc = "Cycles when the Global Completion Table has between 60% and 70% of its slots used. The GCT has 20 entries shared between threads.", }, [ POWER5p_PME_PM_DATA_FROM_L25_MOD ] = { .pme_name = "PM_DATA_FROM_L25_MOD", .pme_code = 0x2c3097, .pme_short_desc = "Data loaded from L2.5 modified", .pme_long_desc = "The processor's Data Cache was reloaded with modified (M) data from the L2 of a chip on the same module as this processor is located due to a demand load.", }, [ POWER5p_PME_PM_L2SC_RCLD_DISP_FAIL_ADDR ] = { .pme_name = "PM_L2SC_RCLD_DISP_FAIL_ADDR", .pme_code = 0x711c2, .pme_short_desc = "L2 slice C RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ", .pme_long_desc = "A Read/Claim dispatch for a load failed because of an address conflict. Two RC machines will never both work on the same line or line in the same congruence class at the same time.", }, [ POWER5p_PME_PM_LSU0_REJECT_ERAT_MISS ] = { .pme_name = "PM_LSU0_REJECT_ERAT_MISS", .pme_code = 0xc40c3, .pme_short_desc = "LSU0 reject due to ERAT miss", .pme_long_desc = "Total cycles the Load Store Unit 0 is busy rejecting instructions due to an ERAT miss. Requests that miss the Derat are rejected and retried until the request hits in the Erat.", }, [ POWER5p_PME_PM_DATA_FROM_L375_MOD ] = { .pme_name = "PM_DATA_FROM_L375_MOD", .pme_code = 0x1c30a7, .pme_short_desc = "Data loaded from L3.75 modified", .pme_long_desc = "The processor's Data Cache was reloaded with modified (M) data from the L3 of a chip on the same module as this processor is located due to a demand load.", }, [ POWER5p_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC ] = { .pme_name = "PM_LSU_LMQ_SRQ_EMPTY_CYC", .pme_code = 0x200015, .pme_short_desc = "Cycles LMQ and SRQ empty", .pme_long_desc = "Cycles when both the LMQ and SRQ are empty (LSU is idle)", }, [ POWER5p_PME_PM_DTLB_MISS_64K ] = { .pme_name = "PM_DTLB_MISS_64K", .pme_code = 0x2c208d, .pme_short_desc = "Data TLB miss for 64K page", .pme_long_desc = "Data TLB references to 64KB pages that missed the TLB. Page size is determined at TLB reload time.", }, [ POWER5p_PME_PM_LSU0_REJECT_RELOAD_CDF ] = { .pme_name = "PM_LSU0_REJECT_RELOAD_CDF", .pme_code = 0xc40c2, .pme_short_desc = "LSU0 reject due to reload CDF or tag update collision", .pme_long_desc = "Total cycles the Load Store Unit 0 is busy rejecting instructions because of Critical Data Forward. When critical data arrives from the storage system it is formatted and immediately forwarded, bypassing the data cache, to the destination register using the result bus. Any instruction the requires the result bus in the same cycle is rejected. Tag update rejects are caused when an instruction requires access to the Dcache directory or ERAT in the same system when they are being updated.", }, [ POWER5p_PME_PM_0INST_FETCH ] = { .pme_name = "PM_0INST_FETCH", .pme_code = 0x42208d, .pme_short_desc = "No instructions fetched", .pme_long_desc = "No instructions were fetched this cycles (due to IFU hold, redirect, or icache miss)", }, [ POWER5p_PME_PM_LSU1_REJECT_RELOAD_CDF ] = { .pme_name = "PM_LSU1_REJECT_RELOAD_CDF", .pme_code = 0xc40c6, .pme_short_desc = "LSU1 reject due to reload CDF or tag update collision", .pme_long_desc = "Total cycles the Load Store Unit 1 is busy rejecting instructions because of Critical Data Forward. When critical data arrives from the storage system it is formatted and immediately forwarded, bypassing the data cache, to the destination register using the result bus. Any instruction the requires the result bus in the same cycle is rejected. Tag update rejects are caused when an instruction requires access to the Dcache directory or ERAT in the same system when they are being updated.", }, [ POWER5p_PME_PM_MEM_WQ_DISP_Q0to7 ] = { .pme_name = "PM_MEM_WQ_DISP_Q0to7", .pme_code = 0x723e6, .pme_short_desc = "Memory write queue dispatched to queues 0-7", .pme_long_desc = "A memory operation was dispatched to a write queue in the range between 0 and 7. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", }, [ POWER5p_PME_PM_L1_PREF ] = { .pme_name = "PM_L1_PREF", .pme_code = 0xc70e7, .pme_short_desc = "L1 cache data prefetches", .pme_long_desc = "A request to prefetch data into the L1 was made", }, [ POWER5p_PME_PM_MRK_DATA_FROM_LMEM_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_LMEM_CYC", .pme_code = 0x4c70a0, .pme_short_desc = "Marked load latency from local memory", .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.", }, [ POWER5p_PME_PM_BRQ_FULL_CYC ] = { .pme_name = "PM_BRQ_FULL_CYC", .pme_code = 0x100c5, .pme_short_desc = "Cycles branch queue full", .pme_long_desc = "Cycles when the issue queue that feeds the branch unit is full. This condition will prevent dispatch groups from being dispatched. This event only indicates that the queue was full, not that dispatch was prevented.", }, [ POWER5p_PME_PM_GRP_IC_MISS_NONSPEC ] = { .pme_name = "PM_GRP_IC_MISS_NONSPEC", .pme_code = 0x112099, .pme_short_desc = "Group experienced non-speculative I cache miss", .pme_long_desc = "Number of groups, counted at completion, that have encountered an instruction cache miss.", }, [ POWER5p_PME_PM_PTEG_FROM_L275_MOD ] = { .pme_name = "PM_PTEG_FROM_L275_MOD", .pme_code = 0x1830a3, .pme_short_desc = "PTEG loaded from L2.75 modified", .pme_long_desc = "A Page Table Entry was loaded into the TLB with modified (M) data from the L2 on a different module than this processor is located due to a demand load.", }, [ POWER5p_PME_PM_MRK_LD_MISS_L1_LSU0 ] = { .pme_name = "PM_MRK_LD_MISS_L1_LSU0", .pme_code = 0x820e0, .pme_short_desc = "LSU0 marked L1 D cache load misses", .pme_long_desc = "Load references that miss the Level 1 Data cache, by LSU0.", }, [ POWER5p_PME_PM_MRK_DATA_FROM_L375_SHR_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L375_SHR_CYC", .pme_code = 0x2c70a7, .pme_short_desc = "Marked load latency from L3.75 shared", .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.", }, [ POWER5p_PME_PM_DATA_FROM_L3 ] = { .pme_name = "PM_DATA_FROM_L3", .pme_code = 0x1c308e, .pme_short_desc = "Data loaded from L3", .pme_long_desc = "The processor's Data Cache was reloaded from the local L3 due to a demand load.", }, [ POWER5p_PME_PM_INST_FROM_L2 ] = { .pme_name = "PM_INST_FROM_L2", .pme_code = 0x122086, .pme_short_desc = "Instruction fetched from L2", .pme_long_desc = "An instruction fetch group was fetched from L2. Fetch Groups can contain up to 8 instructions", }, [ POWER5p_PME_PM_LSU_FLUSH ] = { .pme_name = "PM_LSU_FLUSH", .pme_code = 0x110c5, .pme_short_desc = "Flush initiated by LSU", .pme_long_desc = "A flush was initiated by the Load Store Unit", }, [ POWER5p_PME_PM_PMC2_OVERFLOW ] = { .pme_name = "PM_PMC2_OVERFLOW", .pme_code = 0x30000a, .pme_short_desc = "PMC2 Overflow", .pme_long_desc = "Overflows from PMC2 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.", }, [ POWER5p_PME_PM_FPU0_DENORM ] = { .pme_name = "PM_FPU0_DENORM", .pme_code = 0x20e0, .pme_short_desc = "FPU0 received denormalized data", .pme_long_desc = "FPU0 has encountered a denormalized operand.", }, [ POWER5p_PME_PM_FPU1_FMOV_FEST ] = { .pme_name = "PM_FPU1_FMOV_FEST", .pme_code = 0x10c4, .pme_short_desc = "FPU1 executed FMOV or FEST instructions", .pme_long_desc = "FPU1 has executed a move kind of instruction or one of the estimate instructions. This could be fmr*, fneg*, fabs*, fnabs* , fres* or frsqrte* where XYZ* means XYZ or XYZ.", }, [ POWER5p_PME_PM_INST_FETCH_CYC ] = { .pme_name = "PM_INST_FETCH_CYC", .pme_code = 0x220e4, .pme_short_desc = "Cycles at least 1 instruction fetched", .pme_long_desc = "Cycles when at least one instruction was sent from the fetch unit to the decode unit.", }, [ POWER5p_PME_PM_INST_DISP ] = { .pme_name = "PM_INST_DISP", .pme_code = 0x300009, .pme_short_desc = "Instructions dispatched", .pme_long_desc = "Number of PowerPC instructions successfully dispatched.", }, [ POWER5p_PME_PM_LSU_LDF ] = { .pme_name = "PM_LSU_LDF", .pme_code = 0x1c50a8, .pme_short_desc = "LSU executed Floating Point load instruction", .pme_long_desc = "LSU executed Floating Point load instruction. Combined Unit 0 + 1.", }, [ POWER5p_PME_PM_DATA_FROM_L25_SHR ] = { .pme_name = "PM_DATA_FROM_L25_SHR", .pme_code = 0x1c3097, .pme_short_desc = "Data loaded from L2.5 shared", .pme_long_desc = "The processor's Data Cache was reloaded with shared (T or SL) data from the L2 of a chip on the same module as this processor is located due to a demand load.", }, [ POWER5p_PME_PM_L1_DCACHE_RELOAD_VALID ] = { .pme_name = "PM_L1_DCACHE_RELOAD_VALID", .pme_code = 0xc30e4, .pme_short_desc = "L1 reload data source valid", .pme_long_desc = "The data source information is valid,the data cache has been reloaded. Prior to POWER5+ this included data cache reloads due to prefetch activity. With POWER5+ this now only includes reloads due to demand loads.", }, [ POWER5p_PME_PM_MEM_WQ_DISP_DCLAIM ] = { .pme_name = "PM_MEM_WQ_DISP_DCLAIM", .pme_code = 0x713c6, .pme_short_desc = "Memory write queue dispatched due to dclaim/flush", .pme_long_desc = "A memory dclaim or flush operation was dispatched to a write queue. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", }, [ POWER5p_PME_PM_MRK_GRP_ISSUED ] = { .pme_name = "PM_MRK_GRP_ISSUED", .pme_code = 0x100015, .pme_short_desc = "Marked group issued", .pme_long_desc = "A sampled instruction was issued.", }, [ POWER5p_PME_PM_FPU_FULL_CYC ] = { .pme_name = "PM_FPU_FULL_CYC", .pme_code = 0x110090, .pme_short_desc = "Cycles FPU issue queue full", .pme_long_desc = "Cycles when one or both FPU issue queues are full. Combined Unit 0 + 1. Use with caution since this is the sum of cycles when Unit 0 was full plus Unit 1 full. It does not indicate when both units were full.", }, [ POWER5p_PME_PM_INST_FROM_L35_MOD ] = { .pme_name = "PM_INST_FROM_L35_MOD", .pme_code = 0x22209d, .pme_short_desc = "Instruction fetched from L3.5 modified", .pme_long_desc = "An instruction fetch group was fetched with modified (M) data from the L3 of a chip on the same module as this processor is located. Fetch groups can contain up to 8 instructions", }, [ POWER5p_PME_PM_FPU_FMA ] = { .pme_name = "PM_FPU_FMA", .pme_code = 0x200088, .pme_short_desc = "FPU executed multiply-add instruction", .pme_long_desc = "This signal is active for one cycle when FPU is executing multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs. Combined Unit 0 + Unit 1.", }, [ POWER5p_PME_PM_THRD_PRIO_3_CYC ] = { .pme_name = "PM_THRD_PRIO_3_CYC", .pme_code = 0x420e2, .pme_short_desc = "Cycles thread running at priority level 3", .pme_long_desc = "Cycles this thread was running at priority level 3.", }, [ POWER5p_PME_PM_MRK_CRU_FIN ] = { .pme_name = "PM_MRK_CRU_FIN", .pme_code = 0x400005, .pme_short_desc = "Marked instruction CRU processing finished", .pme_long_desc = "The Condition Register Unit finished a marked instruction. Instructions that finish may not necessary complete.", }, [ POWER5p_PME_PM_SNOOP_WR_RETRY_WQ ] = { .pme_name = "PM_SNOOP_WR_RETRY_WQ", .pme_code = 0x716c6, .pme_short_desc = "Snoop write/dclaim retry due to collision with active write queue", .pme_long_desc = "A snoop request for a write or dclaim to memory was retried because it matched the cache line of an active write. The snoop request is retried and the active write is changed to high priority. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", }, [ POWER5p_PME_PM_CMPLU_STALL_REJECT ] = { .pme_name = "PM_CMPLU_STALL_REJECT", .pme_code = 0x41109a, .pme_short_desc = "Completion stall caused by reject", .pme_long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes suffered a load/store reject. This is a subset of PM_CMPLU_STALL_LSU.", }, [ POWER5p_PME_PM_MRK_FXU_FIN ] = { .pme_name = "PM_MRK_FXU_FIN", .pme_code = 0x200014, .pme_short_desc = "Marked instruction FXU processing finished", .pme_long_desc = "One of the Fixed Point Units finished a marked instruction. Instructions that finish may not necessary complete.", }, [ POWER5p_PME_PM_LSU1_REJECT_ERAT_MISS ] = { .pme_name = "PM_LSU1_REJECT_ERAT_MISS", .pme_code = 0xc40c7, .pme_short_desc = "LSU1 reject due to ERAT miss", .pme_long_desc = "Total cycles the Load Store Unit 1 is busy rejecting instructions due to an ERAT miss. Requests that miss the Derat are rejected and retried until the request hits in the Erat.", }, [ POWER5p_PME_PM_L2SB_RCST_DISP_FAIL_OTHER ] = { .pme_name = "PM_L2SB_RCST_DISP_FAIL_OTHER", .pme_code = 0x732e1, .pme_short_desc = "L2 slice B RC store dispatch attempt failed due to other reasons", .pme_long_desc = "A Read/Claim dispatch for a store failed for some reason other than Full or Collision conditions. Rejected dispatches do not count because they have not yet been attempted.", }, [ POWER5p_PME_PM_L2SC_RC_DISP_FAIL_CO_BUSY ] = { .pme_name = "PM_L2SC_RC_DISP_FAIL_CO_BUSY", .pme_code = 0x703c2, .pme_short_desc = "L2 slice C RC dispatch attempt failed due to RC/CO pair chosen was miss and CO already busy", .pme_long_desc = "A Read/Claim Dispatch was rejected at dispatch because the Castout Machine was busy. In the case of an RC starting up on a miss and the victim is valid, the CO machine must be available for the RC to process the access. If the CO is still busy working on an old castout, then the RC must not-ack the access if it is a miss(re-issued by the CIU). If it is a miss and the CO is available to process the castout, the RC will accept the access. Once the RC has finished, it can restart and process new accesses that result in a hit (or miss that doesn't need a CO) even though the CO is still processing a castout from a previous access.", }, [ POWER5p_PME_PM_PMC4_OVERFLOW ] = { .pme_name = "PM_PMC4_OVERFLOW", .pme_code = 0x10000a, .pme_short_desc = "PMC4 Overflow", .pme_long_desc = "Overflows from PMC4 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.", }, [ POWER5p_PME_PM_L3SA_SNOOP_RETRY ] = { .pme_name = "PM_L3SA_SNOOP_RETRY", .pme_code = 0x731e3, .pme_short_desc = "L3 slice A snoop retries", .pme_long_desc = "Number of times an L3 retried a snoop because it got two in at the same time (one on snp_a, one on snp_b)", }, [ POWER5p_PME_PM_PTEG_FROM_L35_MOD ] = { .pme_name = "PM_PTEG_FROM_L35_MOD", .pme_code = 0x28309e, .pme_short_desc = "PTEG loaded from L3.5 modified", .pme_long_desc = "A Page Table Entry was loaded into the TLB with modified (M) data from the L3 of a chip on the same module as this processor is located, due to a demand load.", }, [ POWER5p_PME_PM_INST_FROM_L25_MOD ] = { .pme_name = "PM_INST_FROM_L25_MOD", .pme_code = 0x222096, .pme_short_desc = "Instruction fetched from L2.5 modified", .pme_long_desc = "An instruction fetch group was fetched with modified (M) data from the L2 of a chip on the same module as this processor is located. Fetch groups can contain up to 8 instructions.", }, [ POWER5p_PME_PM_THRD_SMT_HANG ] = { .pme_name = "PM_THRD_SMT_HANG", .pme_code = 0x330e7, .pme_short_desc = "SMT hang detected", .pme_long_desc = "A hung thread was detected", }, [ POWER5p_PME_PM_CMPLU_STALL_ERAT_MISS ] = { .pme_name = "PM_CMPLU_STALL_ERAT_MISS", .pme_code = 0x41109b, .pme_short_desc = "Completion stall caused by ERAT miss", .pme_long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes suffered an ERAT miss. This is a subset of PM_CMPLU_STALL_REJECT.", }, [ POWER5p_PME_PM_L3SA_MOD_TAG ] = { .pme_name = "PM_L3SA_MOD_TAG", .pme_code = 0x720e3, .pme_short_desc = "L3 slice A transition from modified to TAG", .pme_long_desc = "L3 snooper detects someone doing a read to a line that is truly M in this L3(i.e. L3 going M->T or M->I(go_Mu case) Mu|Me are not included since they are formed due to a prev read op). Tx is not included since it is considered shared at this point.", }, [ POWER5p_PME_PM_INST_FROM_L2MISS ] = { .pme_name = "PM_INST_FROM_L2MISS", .pme_code = 0x12209b, .pme_short_desc = "Instruction fetched missed L2", .pme_long_desc = "An instruction fetch group was fetched from beyond the local L2.", }, [ POWER5p_PME_PM_FLUSH_SYNC ] = { .pme_name = "PM_FLUSH_SYNC", .pme_code = 0x330e1, .pme_short_desc = "Flush caused by sync", .pme_long_desc = "This thread has been flushed at dispatch due to a sync, lwsync, ptesync, or tlbsync instruction. This allows the other thread to have more machine resources for it to make progress until the sync finishes.", }, [ POWER5p_PME_PM_MRK_GRP_DISP ] = { .pme_name = "PM_MRK_GRP_DISP", .pme_code = 0x100002, .pme_short_desc = "Marked group dispatched", .pme_long_desc = "A group containing a sampled instruction was dispatched", }, [ POWER5p_PME_PM_MEM_RQ_DISP_Q8to11 ] = { .pme_name = "PM_MEM_RQ_DISP_Q8to11", .pme_code = 0x722e6, .pme_short_desc = "Memory read queue dispatched to queues 8-11", .pme_long_desc = "A memory operation was dispatched to read queue 8,9,10 or 11. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", }, [ POWER5p_PME_PM_L2SC_ST_HIT ] = { .pme_name = "PM_L2SC_ST_HIT", .pme_code = 0x733e2, .pme_short_desc = "L2 slice C store hits", .pme_long_desc = "A store request made from the core hit in the L2 directory. The event is provided on each of the three slices A, B, and C.", }, [ POWER5p_PME_PM_L2SB_MOD_TAG ] = { .pme_name = "PM_L2SB_MOD_TAG", .pme_code = 0x720e1, .pme_short_desc = "L2 slice B transition from modified to tagged", .pme_long_desc = "A cache line in the local L2 directory made a state transition from the Modified state to the Tagged state. This transition was caused by a read snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A, B, and C.", }, [ POWER5p_PME_PM_CLB_EMPTY_CYC ] = { .pme_name = "PM_CLB_EMPTY_CYC", .pme_code = 0x410c6, .pme_short_desc = "Cycles CLB empty", .pme_long_desc = "Cycles when both thread's CLB is completely empty.", }, [ POWER5p_PME_PM_L2SB_ST_HIT ] = { .pme_name = "PM_L2SB_ST_HIT", .pme_code = 0x733e1, .pme_short_desc = "L2 slice B store hits", .pme_long_desc = "A store request made from the core hit in the L2 directory. This event is provided on each of the three L2 slices A, B and C.", }, [ POWER5p_PME_PM_MEM_NONSPEC_RD_CANCEL ] = { .pme_name = "PM_MEM_NONSPEC_RD_CANCEL", .pme_code = 0x711c6, .pme_short_desc = "Non speculative memory read cancelled", .pme_long_desc = "A non-speculative read was cancelled because the combined response indicated it was sourced from aother L2 or L3. This event is sent from the Memory Controller clock domain and must be scaled accordingly", }, [ POWER5p_PME_PM_BR_PRED_CR_TA ] = { .pme_name = "PM_BR_PRED_CR_TA", .pme_code = 0x423087, .pme_short_desc = "A conditional branch was predicted, CR and target prediction", .pme_long_desc = "Both the condition (taken or not taken) and the target address of a branch instruction was predicted.", }, [ POWER5p_PME_PM_MRK_LSU0_FLUSH_SRQ ] = { .pme_name = "PM_MRK_LSU0_FLUSH_SRQ", .pme_code = 0x810c3, .pme_short_desc = "LSU0 marked SRQ lhs flushes", .pme_long_desc = "A marked store was flushed because younger load hits and older store that is already in the SRQ or in the same group.", }, [ POWER5p_PME_PM_MRK_LSU_FLUSH_ULD ] = { .pme_name = "PM_MRK_LSU_FLUSH_ULD", .pme_code = 0x1810a8, .pme_short_desc = "Marked unaligned load flushes", .pme_long_desc = "A marked load was flushed because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)", }, [ POWER5p_PME_PM_INST_DISP_ATTEMPT ] = { .pme_name = "PM_INST_DISP_ATTEMPT", .pme_code = 0x120e1, .pme_short_desc = "Instructions dispatch attempted", .pme_long_desc = "Number of PowerPC Instructions dispatched (attempted, not filtered by success.", }, [ POWER5p_PME_PM_INST_FROM_RMEM ] = { .pme_name = "PM_INST_FROM_RMEM", .pme_code = 0x422086, .pme_short_desc = "Instruction fetched from remote memory", .pme_long_desc = "An instruction fetch group was fetched from memory attached to a different module than this proccessor is located on. Fetch groups can contain up to 8 instructions", }, [ POWER5p_PME_PM_ST_REF_L1_LSU0 ] = { .pme_name = "PM_ST_REF_L1_LSU0", .pme_code = 0xc10c1, .pme_short_desc = "LSU0 L1 D cache store references", .pme_long_desc = "Store references to the Data Cache by LSU0.", }, [ POWER5p_PME_PM_LSU0_DERAT_MISS ] = { .pme_name = "PM_LSU0_DERAT_MISS", .pme_code = 0x800c2, .pme_short_desc = "LSU0 DERAT misses", .pme_long_desc = "Total D-ERAT Misses by LSU0. Requests that miss the Derat are rejected and retried until the request hits in the Erat. This may result in multiple erat misses for the same instruction.", }, [ POWER5p_PME_PM_FPU_STALL3 ] = { .pme_name = "PM_FPU_STALL3", .pme_code = 0x202088, .pme_short_desc = "FPU stalled in pipe3", .pme_long_desc = "FPU has generated a stall in pipe3 due to overflow, underflow, massive cancel, convert to integer (sometimes), or convert from integer (always). This signal is active during the entire duration of the stall. Combined Unit 0 + Unit 1.", }, [ POWER5p_PME_PM_L2SB_RCLD_DISP ] = { .pme_name = "PM_L2SB_RCLD_DISP", .pme_code = 0x701c1, .pme_short_desc = "L2 slice B RC load dispatch attempt", .pme_long_desc = "A Read/Claim dispatch for a Load was attempted", }, [ POWER5p_PME_PM_BR_PRED_CR ] = { .pme_name = "PM_BR_PRED_CR", .pme_code = 0x230e2, .pme_short_desc = "A conditional branch was predicted, CR prediction", .pme_long_desc = "A conditional branch instruction was predicted as taken or not taken.", }, [ POWER5p_PME_PM_MRK_DATA_FROM_L2 ] = { .pme_name = "PM_MRK_DATA_FROM_L2", .pme_code = 0x1c7087, .pme_short_desc = "Marked data loaded from L2", .pme_long_desc = "The processor's Data Cache was reloaded from the local L2 due to a marked load.", }, [ POWER5p_PME_PM_LSU0_FLUSH_SRQ ] = { .pme_name = "PM_LSU0_FLUSH_SRQ", .pme_code = 0xc00c3, .pme_short_desc = "LSU0 SRQ lhs flushes", .pme_long_desc = "A store was flushed by unit 0 because younger load hits and older store that is already in the SRQ or in the same group.", }, [ POWER5p_PME_PM_FAB_PNtoNN_DIRECT ] = { .pme_name = "PM_FAB_PNtoNN_DIRECT", .pme_code = 0x703c7, .pme_short_desc = "PN to NN beat went straight to its destination", .pme_long_desc = "Fabric Data beats that the base chip takes the inbound PN data and passes it through to the outbound NN bus without going into a sidecar. The signal is delivered at FBC speed and the count must be scaled.", }, [ POWER5p_PME_PM_IOPS_CMPL ] = { .pme_name = "PM_IOPS_CMPL", .pme_code = 0x1, .pme_short_desc = "Internal operations completed", .pme_long_desc = "Number of internal operations that completed.", }, [ POWER5p_PME_PM_L2SA_RCST_DISP ] = { .pme_name = "PM_L2SA_RCST_DISP", .pme_code = 0x702c0, .pme_short_desc = "L2 slice A RC store dispatch attempt", .pme_long_desc = "A Read/Claim dispatch for a Store was attempted.", }, [ POWER5p_PME_PM_L2SA_RCST_DISP_FAIL_OTHER ] = { .pme_name = "PM_L2SA_RCST_DISP_FAIL_OTHER", .pme_code = 0x732e0, .pme_short_desc = "L2 slice A RC store dispatch attempt failed due to other reasons", .pme_long_desc = "A Read/Claim dispatch for a store failed for some reason other than Full or Collision conditions. Rejected dispatches do not count because they have not yet been attempted.", }, [ POWER5p_PME_PM_L2SC_SHR_INV ] = { .pme_name = "PM_L2SC_SHR_INV", .pme_code = 0x710c2, .pme_short_desc = "L2 slice C transition from shared to invalid", .pme_long_desc = "A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L, or Tagged) to the Invalid state. This transition was caused by any external snoop request. The event is provided on each of the three slices A, B, and C. NOTE: For this event to be useful the tablewalk duration event should also be counted.", }, [ POWER5p_PME_PM_SNOOP_RETRY_AB_COLLISION ] = { .pme_name = "PM_SNOOP_RETRY_AB_COLLISION", .pme_code = 0x735e6, .pme_short_desc = "Snoop retry due to a b collision", .pme_long_desc = "Snoop retry due to a b collision", }, [ POWER5p_PME_PM_FAB_PNtoVN_SIDECAR ] = { .pme_name = "PM_FAB_PNtoVN_SIDECAR", .pme_code = 0x733e7, .pme_short_desc = "PN to VN beat went to sidecar first", .pme_long_desc = "Fabric data beats that the base chip takes the inbound PN data and forwards it on to the outbound VN data bus after going into a sidecar first. The signal is delivered at FBC speed and the count must be scaled accordingly.", }, [ POWER5p_PME_PM_LSU0_REJECT_LMQ_FULL ] = { .pme_name = "PM_LSU0_REJECT_LMQ_FULL", .pme_code = 0xc40c1, .pme_short_desc = "LSU0 reject due to LMQ full or missed data coming", .pme_long_desc = "Total cycles the Load Store Unit 0 is busy rejecting instructions because the Load Miss Queue was full. The LMQ has eight entries. If all eight entries are full, subsequent load instructions are rejected.", }, [ POWER5p_PME_PM_LSU_LMQ_S0_ALLOC ] = { .pme_name = "PM_LSU_LMQ_S0_ALLOC", .pme_code = 0xc30e6, .pme_short_desc = "LMQ slot 0 allocated", .pme_long_desc = "The first entry in the LMQ was allocated.", }, [ POWER5p_PME_PM_SNOOP_PW_RETRY_RQ ] = { .pme_name = "PM_SNOOP_PW_RETRY_RQ", .pme_code = 0x707c6, .pme_short_desc = "Snoop partial-write retry due to collision with active read queue", .pme_long_desc = "A snoop request for a partial write to memory was retried because it matched the cache line of an active read. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", }, [ POWER5p_PME_PM_DTLB_REF ] = { .pme_name = "PM_DTLB_REF", .pme_code = 0xc20e4, .pme_short_desc = "Data TLB references", .pme_long_desc = "Total number of Data TLB references for all page sizes. Page size is determined at TLB reload time.", }, [ POWER5p_PME_PM_PTEG_FROM_L3 ] = { .pme_name = "PM_PTEG_FROM_L3", .pme_code = 0x18308e, .pme_short_desc = "PTEG loaded from L3", .pme_long_desc = "A Page Table Entry was loaded into the TLB from the local L3 due to a demand load.", }, [ POWER5p_PME_PM_FAB_M1toVNorNN_SIDECAR_EMPTY ] = { .pme_name = "PM_FAB_M1toVNorNN_SIDECAR_EMPTY", .pme_code = 0x712c7, .pme_short_desc = "M1 to VN/NN sidecar empty", .pme_long_desc = "Fabric cycles when the Minus-1 jump sidecar (sidecars for mcm to mcm data transfer) is empty. The signal is delivered at FBC speed and the count must be scaled accordingly.", }, [ POWER5p_PME_PM_LSU_SRQ_EMPTY_CYC ] = { .pme_name = "PM_LSU_SRQ_EMPTY_CYC", .pme_code = 0x400015, .pme_short_desc = "Cycles SRQ empty", .pme_long_desc = "Cycles the Store Request Queue is empty", }, [ POWER5p_PME_PM_FPU1_STF ] = { .pme_name = "PM_FPU1_STF", .pme_code = 0x20e6, .pme_short_desc = "FPU1 executed store instruction", .pme_long_desc = "FPU1 has executed a Floating Point Store instruction.", }, [ POWER5p_PME_PM_LSU_LMQ_S0_VALID ] = { .pme_name = "PM_LSU_LMQ_S0_VALID", .pme_code = 0xc30e5, .pme_short_desc = "LMQ slot 0 valid", .pme_long_desc = "This signal is asserted every cycle when the first entry in the LMQ is valid. The LMQ had eight entries that are allocated FIFO", }, [ POWER5p_PME_PM_GCT_USAGE_00to59_CYC ] = { .pme_name = "PM_GCT_USAGE_00to59_CYC", .pme_code = 0x10001f, .pme_short_desc = "Cycles GCT less than 60% full", .pme_long_desc = "Cycles when the Global Completion Table has fewer than 60% of its slots used. The GCT has 20 entries shared between threads.", }, [ POWER5p_PME_PM_FPU_FMOV_FEST ] = { .pme_name = "PM_FPU_FMOV_FEST", .pme_code = 0x301088, .pme_short_desc = "FPU executed FMOV or FEST instructions", .pme_long_desc = "The floating point unit has executed a move kind of instruction or one of the estimate instructions. This could be fmr*, fneg*, fabs*, fnabs* , fres* or frsqrte* where XYZ* means XYZ or XYZ.. Combined Unit 0 + Unit 1.", }, [ POWER5p_PME_PM_DATA_FROM_L2MISS ] = { .pme_name = "PM_DATA_FROM_L2MISS", .pme_code = 0x3c309b, .pme_short_desc = "Data loaded missed L2", .pme_long_desc = "The processor's Data Cache was reloaded but not from the local L2.", }, [ POWER5p_PME_PM_XER_MAP_FULL_CYC ] = { .pme_name = "PM_XER_MAP_FULL_CYC", .pme_code = 0x100c2, .pme_short_desc = "Cycles XER mapper full", .pme_long_desc = "The XER mapper cannot accept any more groups. This condition will prevent dispatch groups from being dispatched. This event only indicates that the mapper was full, not that dispatch was prevented.", }, [ POWER5p_PME_PM_GRP_DISP_BLK_SB_CYC ] = { .pme_name = "PM_GRP_DISP_BLK_SB_CYC", .pme_code = 0x130e1, .pme_short_desc = "Cycles group dispatch blocked by scoreboard", .pme_long_desc = "A scoreboard operation on a non-renamed resource has blocked dispatch.", }, [ POWER5p_PME_PM_FLUSH_SB ] = { .pme_name = "PM_FLUSH_SB", .pme_code = 0x330e2, .pme_short_desc = "Flush caused by scoreboard operation", .pme_long_desc = "This thread has been flushed at dispatch because its scoreboard bit is set indicating that a non-renamed resource is being updated. This allows the other thread to have more machine resources for it to make progress while this thread is stalled.", }, [ POWER5p_PME_PM_MRK_DATA_FROM_L375_SHR ] = { .pme_name = "PM_MRK_DATA_FROM_L375_SHR", .pme_code = 0x3c709e, .pme_short_desc = "Marked data loaded from L3.75 shared", .pme_long_desc = "The processor's Data Cache was reloaded with shared (S) data from the L3 of a chip on a different module than this processor is located due to a marked load.", }, [ POWER5p_PME_PM_MRK_GRP_CMPL ] = { .pme_name = "PM_MRK_GRP_CMPL", .pme_code = 0x400013, .pme_short_desc = "Marked group completed", .pme_long_desc = "A group containing a sampled instruction completed. Microcoded instructions that span multiple groups will generate this event once per group.", }, [ POWER5p_PME_PM_SUSPENDED ] = { .pme_name = "PM_SUSPENDED", .pme_code = 0x0, .pme_short_desc = "Suspended", .pme_long_desc = "The counter is suspended (does not count).", }, [ POWER5p_PME_PM_SNOOP_RD_RETRY_QFULL ] = { .pme_name = "PM_SNOOP_RD_RETRY_QFULL", .pme_code = 0x700c6, .pme_short_desc = "Snoop read retry due to read queue full", .pme_long_desc = "A snoop request for a read from memory was retried because the read queues were full. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", }, [ POWER5p_PME_PM_GRP_IC_MISS_BR_REDIR_NONSPEC ] = { .pme_name = "PM_GRP_IC_MISS_BR_REDIR_NONSPEC", .pme_code = 0x120e5, .pme_short_desc = "Group experienced non-speculative I cache miss or branch redirect", .pme_long_desc = "Group experienced non-speculative I cache miss or branch redirect", }, [ POWER5p_PME_PM_DATA_FROM_L35_SHR ] = { .pme_name = "PM_DATA_FROM_L35_SHR", .pme_code = 0x1c309e, .pme_short_desc = "Data loaded from L3.5 shared", .pme_long_desc = "The processor's Data Cache was reloaded with shared (S) data from the L3 of a chip on the same module as this processor is located due to a demand load.", }, [ POWER5p_PME_PM_L3SB_MOD_INV ] = { .pme_name = "PM_L3SB_MOD_INV", .pme_code = 0x730e4, .pme_short_desc = "L3 slice B transition from modified to invalid", .pme_long_desc = "L3 snooper detects someone doing a store to a line that is truly M in this L3 (i.e. L3 going M=>I). Mu|Me are not included since they are formed due to a prev read op. Tx is not included since it is considered shared at this point.", }, [ POWER5p_PME_PM_STCX_FAIL ] = { .pme_name = "PM_STCX_FAIL", .pme_code = 0x820e1, .pme_short_desc = "STCX failed", .pme_long_desc = "A stcx (stwcx or stdcx) failed", }, [ POWER5p_PME_PM_LD_MISS_L1_LSU1 ] = { .pme_name = "PM_LD_MISS_L1_LSU1", .pme_code = 0xc10c5, .pme_short_desc = "LSU1 L1 D cache load misses", .pme_long_desc = "Load references that miss the Level 1 Data cache, by unit 1.", }, [ POWER5p_PME_PM_GRP_DISP ] = { .pme_name = "PM_GRP_DISP", .pme_code = 0x200002, .pme_short_desc = "Group dispatches", .pme_long_desc = "A group was dispatched", }, [ POWER5p_PME_PM_DC_PREF_DST ] = { .pme_name = "PM_DC_PREF_DST", .pme_code = 0x830e6, .pme_short_desc = "DST (Data Stream Touch) stream start", .pme_long_desc = "A prefetch stream was started using the DST instruction.", }, [ POWER5p_PME_PM_FPU1_DENORM ] = { .pme_name = "PM_FPU1_DENORM", .pme_code = 0x20e4, .pme_short_desc = "FPU1 received denormalized data", .pme_long_desc = "FPU1 has encountered a denormalized operand.", }, [ POWER5p_PME_PM_FPU0_FPSCR ] = { .pme_name = "PM_FPU0_FPSCR", .pme_code = 0x30e0, .pme_short_desc = "FPU0 executed FPSCR instruction", .pme_long_desc = "FPU0 has executed FPSCR move related instruction. This could be mtfsfi*, mtfsb0*, mtfsb1*, mffs*, mtfsf*, mcrsf* where XYZ* means XYZ, XYZs, XYZ., XYZs.", }, [ POWER5p_PME_PM_DATA_FROM_L2 ] = { .pme_name = "PM_DATA_FROM_L2", .pme_code = 0x1c3087, .pme_short_desc = "Data loaded from L2", .pme_long_desc = "The processor's Data Cache was reloaded from the local L2 due to a demand load.", }, [ POWER5p_PME_PM_L2SA_RCLD_DISP_FAIL_ADDR ] = { .pme_name = "PM_L2SA_RCLD_DISP_FAIL_ADDR", .pme_code = 0x711c0, .pme_short_desc = "L2 slice A RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ", .pme_long_desc = "A Read/Claim dispatch for a load failed because of an address conflict. Two RC machines will never both work on the same line or line in the same congruence class at the same time.", }, [ POWER5p_PME_PM_FPU_1FLOP ] = { .pme_name = "PM_FPU_1FLOP", .pme_code = 0x100090, .pme_short_desc = "FPU executed one flop instruction", .pme_long_desc = "The floating point unit has executed an add, mult, sub, compare, fsel, fneg, fabs, fnabs, fres, or frsqrte kind of instruction. These are single FLOP operations.", }, [ POWER5p_PME_PM_L2SC_RCLD_DISP_FAIL_OTHER ] = { .pme_name = "PM_L2SC_RCLD_DISP_FAIL_OTHER", .pme_code = 0x731e2, .pme_short_desc = "L2 slice C RC load dispatch attempt failed due to other reasons", .pme_long_desc = "A Read/Claim dispatch for a load failed for some reason other than Full or Collision conditions.", }, [ POWER5p_PME_PM_FPU0_FSQRT ] = { .pme_name = "PM_FPU0_FSQRT", .pme_code = 0xc2, .pme_short_desc = "FPU0 executed FSQRT instruction", .pme_long_desc = "FPU0 has executed a square root instruction. This could be fsqrt* where XYZ* means XYZ, XYZs, XYZ., XYZs.", }, [ POWER5p_PME_PM_L2SC_RCST_DISP_FAIL_RC_FULL ] = { .pme_name = "PM_L2SC_RCST_DISP_FAIL_RC_FULL", .pme_code = 0x722e1, .pme_short_desc = "L2 slice C RC store dispatch attempt failed due to all RC full", .pme_long_desc = "A Read/Claim dispatch for a store failed because all RC machines are busy.", }, [ POWER5p_PME_PM_LD_REF_L1 ] = { .pme_name = "PM_LD_REF_L1", .pme_code = 0x1c10a8, .pme_short_desc = "L1 D cache load references", .pme_long_desc = "Load references to the Level 1 Data Cache. Combined unit 0 + 1.", }, [ POWER5p_PME_PM_INST_FROM_L1 ] = { .pme_name = "PM_INST_FROM_L1", .pme_code = 0x22208d, .pme_short_desc = "Instruction fetched from L1", .pme_long_desc = "An instruction fetch group was fetched from L1. Fetch Groups can contain up to 8 instructions", }, [ POWER5p_PME_PM_TLBIE_HELD ] = { .pme_name = "PM_TLBIE_HELD", .pme_code = 0x130e4, .pme_short_desc = "TLBIE held at dispatch", .pme_long_desc = "Cycles a TLBIE instruction was held at dispatch.", }, [ POWER5p_PME_PM_DC_PREF_OUT_OF_STREAMS ] = { .pme_name = "PM_DC_PREF_OUT_OF_STREAMS", .pme_code = 0xc50c2, .pme_short_desc = "D cache out of prefetch streams", .pme_long_desc = "A new prefetch stream was detected but no more stream entries were available.", }, [ POWER5p_PME_PM_MRK_DATA_FROM_L25_MOD_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L25_MOD_CYC", .pme_code = 0x4c70a2, .pme_short_desc = "Marked load latency from L2.5 modified", .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.", }, [ POWER5p_PME_PM_MRK_LSU1_FLUSH_SRQ ] = { .pme_name = "PM_MRK_LSU1_FLUSH_SRQ", .pme_code = 0x810c7, .pme_short_desc = "LSU1 marked SRQ lhs flushes", .pme_long_desc = "A marked store was flushed because younger load hits and older store that is already in the SRQ or in the same group.", }, [ POWER5p_PME_PM_MEM_RQ_DISP_Q0to3 ] = { .pme_name = "PM_MEM_RQ_DISP_Q0to3", .pme_code = 0x702c6, .pme_short_desc = "Memory read queue dispatched to queues 0-3", .pme_long_desc = "A memory operation was dispatched to read queue 0,1,2, or 3. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", }, [ POWER5p_PME_PM_ST_REF_L1_LSU1 ] = { .pme_name = "PM_ST_REF_L1_LSU1", .pme_code = 0xc10c4, .pme_short_desc = "LSU1 L1 D cache store references", .pme_long_desc = "Store references to the Data Cache by LSU1.", }, [ POWER5p_PME_PM_MRK_LD_MISS_L1 ] = { .pme_name = "PM_MRK_LD_MISS_L1", .pme_code = 0x182088, .pme_short_desc = "Marked L1 D cache load misses", .pme_long_desc = "Marked L1 D cache load misses", }, [ POWER5p_PME_PM_L1_WRITE_CYC ] = { .pme_name = "PM_L1_WRITE_CYC", .pme_code = 0x230e7, .pme_short_desc = "Cycles writing to instruction L1", .pme_long_desc = "Cycles that a cache line was written to the instruction cache.", }, [ POWER5p_PME_PM_L2SC_ST_REQ ] = { .pme_name = "PM_L2SC_ST_REQ", .pme_code = 0x723e2, .pme_short_desc = "L2 slice C store requests", .pme_long_desc = "A store request as seen at the L2 directory has been made from the core. Stores are counted after gathering in the L2 store queues. The event is provided on each of the three slices A, B, and C.", }, [ POWER5p_PME_PM_CMPLU_STALL_FDIV ] = { .pme_name = "PM_CMPLU_STALL_FDIV", .pme_code = 0x21109b, .pme_short_desc = "Completion stall caused by FDIV or FQRT instruction", .pme_long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes was a floating point divide or square root instruction. This is a subset of PM_CMPLU_STALL_FPU.", }, [ POWER5p_PME_PM_THRD_SEL_OVER_CLB_EMPTY ] = { .pme_name = "PM_THRD_SEL_OVER_CLB_EMPTY", .pme_code = 0x410c2, .pme_short_desc = "Thread selection overrides caused by CLB empty", .pme_long_desc = "Thread selection was overridden because one thread's CLB was empty.", }, [ POWER5p_PME_PM_BR_MPRED_CR ] = { .pme_name = "PM_BR_MPRED_CR", .pme_code = 0x230e5, .pme_short_desc = "Branch mispredictions due to CR bit setting", .pme_long_desc = "A conditional branch instruction was incorrectly predicted as taken or not taken. The branch execution unit detects a branch mispredict because the CR value is opposite of the predicted value. This will result in a branch redirect flush if not overfidden by a flush of an older instruction.", }, [ POWER5p_PME_PM_L3SB_MOD_TAG ] = { .pme_name = "PM_L3SB_MOD_TAG", .pme_code = 0x720e4, .pme_short_desc = "L3 slice B transition from modified to TAG", .pme_long_desc = "L3 snooper detects someone doing a read to a line that is truly M in this L3(i.e. L3 going M->T or M->I(go_Mu case); Mu|Me are not included since they are formed due to a prev read op). Tx is not included since it is considered shared at this point.", }, [ POWER5p_PME_PM_MRK_DATA_FROM_L2MISS ] = { .pme_name = "PM_MRK_DATA_FROM_L2MISS", .pme_code = 0x3c709b, .pme_short_desc = "Marked data loaded missed L2", .pme_long_desc = "DL1 was reloaded from beyond L2 due to a marked demand load.", }, [ POWER5p_PME_PM_LSU_REJECT_SRQ ] = { .pme_name = "PM_LSU_REJECT_SRQ", .pme_code = 0x1c4088, .pme_short_desc = "LSU SRQ lhs rejects", .pme_long_desc = "Total cycles the Load Store Unit is busy rejecting instructions because of Load Hit Store conditions. Loads are rejected when data is needed from a previous store instruction but store forwarding is not possible because the data is not fully contained in the Store Data Queue or is not yet available in the Store Data Queue. Combined Unit 0 + 1.", }, [ POWER5p_PME_PM_LD_MISS_L1 ] = { .pme_name = "PM_LD_MISS_L1", .pme_code = 0x3c1088, .pme_short_desc = "L1 D cache load misses", .pme_long_desc = "Load references that miss the Level 1 Data cache. Combined unit 0 + 1.", }, [ POWER5p_PME_PM_INST_FROM_PREF ] = { .pme_name = "PM_INST_FROM_PREF", .pme_code = 0x32208d, .pme_short_desc = "Instruction fetched from prefetch", .pme_long_desc = "An instruction fetch group was fetched from the prefetch buffer. Fetch groups can contain up to 8 instructions", }, [ POWER5p_PME_PM_STCX_PASS ] = { .pme_name = "PM_STCX_PASS", .pme_code = 0x820e5, .pme_short_desc = "Stcx passes", .pme_long_desc = "A stcx (stwcx or stdcx) instruction was successful", }, [ POWER5p_PME_PM_DC_INV_L2 ] = { .pme_name = "PM_DC_INV_L2", .pme_code = 0xc10c7, .pme_short_desc = "L1 D cache entries invalidated from L2", .pme_long_desc = "A dcache invalidated was received from the L2 because a line in L2 was castout.", }, [ POWER5p_PME_PM_LSU_SRQ_FULL_CYC ] = { .pme_name = "PM_LSU_SRQ_FULL_CYC", .pme_code = 0x110c3, .pme_short_desc = "Cycles SRQ full", .pme_long_desc = "Cycles the Store Request Queue is full.", }, [ POWER5p_PME_PM_FPU_FIN ] = { .pme_name = "PM_FPU_FIN", .pme_code = 0x401088, .pme_short_desc = "FPU produced a result", .pme_long_desc = "FPU finished, produced a result. This only indicates finish, not completion. Combined Unit 0 + Unit 1. Floating Point Stores are included in this count but not Floating Point Loads., , , XYZs", }, [ POWER5p_PME_PM_LSU_SRQ_STFWD ] = { .pme_name = "PM_LSU_SRQ_STFWD", .pme_code = 0x2c6088, .pme_short_desc = "SRQ store forwarded", .pme_long_desc = "Data from a store instruction was forwarded to a load. A load that misses L1 but becomes a store forward is treated as a load miss and it causes the DL1 load miss event to be counted. It does not go into the LMQ. If a load that hits L1 but becomes a store forward, then it's not treated as a load miss. Combined Unit 0 + 1.", }, [ POWER5p_PME_PM_L2SA_SHR_MOD ] = { .pme_name = "PM_L2SA_SHR_MOD", .pme_code = 0x700c0, .pme_short_desc = "L2 slice A transition from shared to modified", .pme_long_desc = "A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L , or Tagged) to the Modified state. This transition was caused by a store from either of the two local CPUs to a cache line in any of the Shared states. The event is provided on each of the three slices A, B, and C.", }, [ POWER5p_PME_PM_0INST_CLB_CYC ] = { .pme_name = "PM_0INST_CLB_CYC", .pme_code = 0x400c0, .pme_short_desc = "Cycles no instructions in CLB", .pme_long_desc = "The cache line buffer (CLB) is a 6-deep, 4-wide instruction buffer. Fullness is reported on a cycle basis with each event representing the number of cycles the CLB had the corresponding number of entries occupied. These events give a real time history of the number of instruction buffers used, but not the number of PowerPC instructions within those buffers. Each thread has its own set of CLB; these events are thread specific.", }, [ POWER5p_PME_PM_FXU0_FIN ] = { .pme_name = "PM_FXU0_FIN", .pme_code = 0x130e2, .pme_short_desc = "FXU0 produced a result", .pme_long_desc = "The Fixed Point unit 0 finished an instruction and produced a result. Instructions that finish may not necessary complete.", }, [ POWER5p_PME_PM_L2SB_RCST_DISP_FAIL_RC_FULL ] = { .pme_name = "PM_L2SB_RCST_DISP_FAIL_RC_FULL", .pme_code = 0x722e2, .pme_short_desc = "L2 slice B RC store dispatch attempt failed due to all RC full", .pme_long_desc = "A Read/Claim dispatch for a store failed because all RC machines are busy.", }, [ POWER5p_PME_PM_THRD_GRP_CMPL_BOTH_CYC ] = { .pme_name = "PM_THRD_GRP_CMPL_BOTH_CYC", .pme_code = 0x200013, .pme_short_desc = "Cycles group completed by both threads", .pme_long_desc = "Cycles that both threads completed.", }, [ POWER5p_PME_PM_PMC5_OVERFLOW ] = { .pme_name = "PM_PMC5_OVERFLOW", .pme_code = 0x10001a, .pme_short_desc = "PMC5 Overflow", .pme_long_desc = "Overflows from PMC5 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.", }, [ POWER5p_PME_PM_FPU0_FDIV ] = { .pme_name = "PM_FPU0_FDIV", .pme_code = 0xc0, .pme_short_desc = "FPU0 executed FDIV instruction", .pme_long_desc = "FPU0 has executed a divide instruction. This could be fdiv, fdivs, fdiv. fdivs.", }, [ POWER5p_PME_PM_PTEG_FROM_L375_SHR ] = { .pme_name = "PM_PTEG_FROM_L375_SHR", .pme_code = 0x38309e, .pme_short_desc = "PTEG loaded from L3.75 shared", .pme_long_desc = "A Page Table Entry was loaded into the TLB with shared (S) data from the L3 of a chip on a different module than this processor is located, due to a demand load.", }, [ POWER5p_PME_PM_HV_CYC ] = { .pme_name = "PM_HV_CYC", .pme_code = 0x20000b, .pme_short_desc = "Hypervisor Cycles", .pme_long_desc = "Cycles when the processor is executing in Hypervisor (MSR[HV] = 1 and MSR[PR]=0)", }, [ POWER5p_PME_PM_L2SA_RC_DISP_FAIL_CO_BUSY ] = { .pme_name = "PM_L2SA_RC_DISP_FAIL_CO_BUSY", .pme_code = 0x703c0, .pme_short_desc = "L2 slice A RC dispatch attempt failed due to RC/CO pair chosen was miss and CO already busy", .pme_long_desc = "A Read/Claim Dispatch was rejected at dispatch because the Castout Machine was busy. In the case of an RC starting up on a miss and the victim is valid, the CO machine must be available for the RC to process the access. If the CO is still busy working on an old castout, then the RC must not-ack the access if it is a miss(re-issued by the CIU). If it is a miss and the CO is available to process the castout, the RC will accept the access. Once the RC has finished, it can restart and process new accesses that result in a hit (or miss that doesn't need a CO) even though the CO is still processing a castout from a previous access.", }, [ POWER5p_PME_PM_THRD_PRIO_DIFF_0_CYC ] = { .pme_name = "PM_THRD_PRIO_DIFF_0_CYC", .pme_code = 0x430e3, .pme_short_desc = "Cycles no thread priority difference", .pme_long_desc = "Cycles when this thread's priority is equal to the other thread's priority.", }, [ POWER5p_PME_PM_LR_CTR_MAP_FULL_CYC ] = { .pme_name = "PM_LR_CTR_MAP_FULL_CYC", .pme_code = 0x100c6, .pme_short_desc = "Cycles LR/CTR mapper full", .pme_long_desc = "The LR/CTR mapper cannot accept any more groups. This condition will prevent dispatch groups from being dispatched. This event only indicates that the mapper was full, not that dispatch was prevented.", }, [ POWER5p_PME_PM_L3SB_SHR_INV ] = { .pme_name = "PM_L3SB_SHR_INV", .pme_code = 0x710c4, .pme_short_desc = "L3 slice B transition from shared to invalid", .pme_long_desc = "L3 snooper detects someone doing a store to a line that is Sx in this L3(i.e. invalidate hit SX and dispatched).", }, [ POWER5p_PME_PM_DATA_FROM_RMEM ] = { .pme_name = "PM_DATA_FROM_RMEM", .pme_code = 0x1c30a1, .pme_short_desc = "Data loaded from remote memory", .pme_long_desc = "The processor's Data Cache was reloaded from memory attached to a different module than this proccessor is located on.", }, [ POWER5p_PME_PM_DATA_FROM_L275_MOD ] = { .pme_name = "PM_DATA_FROM_L275_MOD", .pme_code = 0x1c30a3, .pme_short_desc = "Data loaded from L2.75 modified", .pme_long_desc = "The processor's Data Cache was reloaded with modified (M) data from the L2 on a different module than this processor is located due to a demand load.", }, [ POWER5p_PME_PM_LSU0_REJECT_SRQ ] = { .pme_name = "PM_LSU0_REJECT_SRQ", .pme_code = 0xc40c0, .pme_short_desc = "LSU0 SRQ lhs rejects", .pme_long_desc = "Total cycles the Load Store Unit 0 is busy rejecting instructions because of Load Hit Store conditions. Loads are rejected when data is needed from a previous store instruction but store forwarding is not possible because the data is not fully contained in the Store Data Queue or is not yet available in the Store Data Queue.", }, [ POWER5p_PME_PM_LSU1_DERAT_MISS ] = { .pme_name = "PM_LSU1_DERAT_MISS", .pme_code = 0x800c6, .pme_short_desc = "LSU1 DERAT misses", .pme_long_desc = "A data request (load or store) from LSU Unit 1 missed the ERAT and resulted in an ERAT reload. Multiple instructions may miss the ERAT entry for the same 4K page, but only one reload will occur.", }, [ POWER5p_PME_PM_MRK_LSU_FIN ] = { .pme_name = "PM_MRK_LSU_FIN", .pme_code = 0x400014, .pme_short_desc = "Marked instruction LSU processing finished", .pme_long_desc = "One of the Load/Store Units finished a marked instruction. Instructions that finish may not necessary complete", }, [ POWER5p_PME_PM_DTLB_MISS_16M ] = { .pme_name = "PM_DTLB_MISS_16M", .pme_code = 0x3c208d, .pme_short_desc = "Data TLB miss for 16M page", .pme_long_desc = "Data TLB references to 16MB pages that missed the TLB. Page size is determined at TLB reload time.", }, [ POWER5p_PME_PM_LSU0_FLUSH_UST ] = { .pme_name = "PM_LSU0_FLUSH_UST", .pme_code = 0xc00c1, .pme_short_desc = "LSU0 unaligned store flushes", .pme_long_desc = "A store was flushed from unit 0 because it was unaligned (crossed a 4K boundary).", }, [ POWER5p_PME_PM_L2SB_RC_DISP_FAIL_CO_BUSY ] = { .pme_name = "PM_L2SB_RC_DISP_FAIL_CO_BUSY", .pme_code = 0x703c1, .pme_short_desc = "L2 slice B RC dispatch attempt failed due to RC/CO pair chosen was miss and CO already busy", .pme_long_desc = "A Read/Claim Dispatch was rejected at dispatch because the Castout Machine was busy. In the case of an RC starting up on a miss and the victim is valid, the CO machine must be available for the RC to process the access. If the CO is still busy working on an old castout, then the RC must not-ack the access if it is a miss(re-issued by the CIU). If it is a miss and the CO is available to process the castout, the RC will accept the access. Once the RC has finished, it can restart and process new accesses that result in a hit (or miss that doesn't need a CO) even though the CO is still processing a castout from a previous access.", }, [ POWER5p_PME_PM_L2SC_MOD_TAG ] = { .pme_name = "PM_L2SC_MOD_TAG", .pme_code = 0x720e2, .pme_short_desc = "L2 slice C transition from modified to tagged", .pme_long_desc = "A cache line in the local L2 directory made a state transition from the Modified state to the Tagged state. This transition was caused by a read snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A, B, and C.", } }; #endif libpfm-4.9.0/lib/events/intel_x86_arch_events.h0000664000175000017500000000642213223402656021246 0ustar eranianeranian/* * Copyright (c) 2006-2007 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. */ /* * architected events for architectural perfmon v1 and v2 as defined by the IA-32 developer's manual * Vol 3B, table 18-6 (May 2007) */ static intel_x86_entry_t intel_x86_arch_pe[]={ {.name = "UNHALTED_CORE_CYCLES", .code = 0x003c, .cntmsk = 0x200000000ull, /* temporary */ .desc = "count core clock cycles whenever the clock signal on the specific core is running (not halted)" }, {.name = "INSTRUCTION_RETIRED", .code = 0x00c0, .cntmsk = 0x100000000ull, /* temporary */ .desc = "count the number of instructions at retirement. For instructions that consists of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction", }, {.name = "UNHALTED_REFERENCE_CYCLES", .code = 0x013c, .cntmsk = 0x400000000ull, /* temporary */ .desc = "count reference clock cycles while the clock signal on the specific core is running. The reference clock operates at a fixed frequency, irrespective of core frequency changes due to performance state transitions", }, {.name = "LLC_REFERENCES", .code = 0x4f2e, .desc = "count each request originating from the core to reference a cache line in the last level cache. The count may include speculation, but excludes cache line fills due to hardware prefetch", }, {.name = "LLC_MISSES", .code = 0x412e, .desc = "count each cache miss condition for references to the last level cache. The event count may include speculation, but excludes cache line fills due to hardware prefetch", }, {.name = "BRANCH_INSTRUCTIONS_RETIRED", .code = 0x00c4, .desc = "count branch instructions at retirement. Specifically, this event counts the retirement of the last micro-op of a branch instruction", }, {.name = "MISPREDICTED_BRANCH_RETIRED", .code = 0x00c5, .desc = "count mispredicted branch instructions at retirement. Specifically, this event counts at retirement of the last micro-op of a branch instruction in the architectural path of the execution and experienced misprediction in the branch prediction hardware", } }; libpfm-4.9.0/lib/events/s390x_cpumf_events.h0000664000175000017500000011604713223402656020516 0ustar eranianeranian#ifndef __S390X_CPUMF_EVENTS_H__ #define __S390X_CPUMF_EVENTS_H__ #define __stringify(x) #x #define STRINGIFY(x) __stringify(x) /* CPUMF counter sets */ #define CPUMF_CTRSET_NONE 0 #define CPUMF_CTRSET_BASIC 2 #define CPUMF_CTRSET_PROBLEM_STATE 4 #define CPUMF_CTRSET_CRYPTO 8 #define CPUMF_CTRSET_EXTENDED 1 #define CPUMF_CTRSET_MT_DIAG 32 static const pme_cpumf_ctr_t cpumcf_generic_counters[] = { { .ctrnum = 0, .ctrset = CPUMF_CTRSET_BASIC, .name = "CPU_CYCLES", .desc = "Cycle Count", }, { .ctrnum = 1, .ctrset = CPUMF_CTRSET_BASIC, .name = "INSTRUCTIONS", .desc = "Instruction Count", }, { .ctrnum = 2, .ctrset = CPUMF_CTRSET_BASIC, .name = "L1I_DIR_WRITES", .desc = "Level-1 I-Cache Directory Write Count", }, { .ctrnum = 3, .ctrset = CPUMF_CTRSET_BASIC, .name = "L1I_PENALTY_CYCLES", .desc = "Level-1 I-Cache Penalty Cycle Count", }, { .ctrnum = 4, .ctrset = CPUMF_CTRSET_BASIC, .name = "L1D_DIR_WRITES", .desc = "Level-1 D-Cache Directory Write Count", }, { .ctrnum = 5, .ctrset = CPUMF_CTRSET_BASIC, .name = "L1D_PENALTY_CYCLES", .desc = "Level-1 D-Cache Penalty Cycle Count", }, { .ctrnum = 32, .ctrset = CPUMF_CTRSET_PROBLEM_STATE, .name = "PROBLEM_STATE_CPU_CYCLES", .desc = "Problem-State Cycle Count", }, { .ctrnum = 33, .ctrset = CPUMF_CTRSET_PROBLEM_STATE, .name = "PROBLEM_STATE_INSTRUCTIONS", .desc = "Problem-State Instruction Count", }, { .ctrnum = 34, .ctrset = CPUMF_CTRSET_PROBLEM_STATE, .name = "PROBLEM_STATE_L1I_DIR_WRITES", .desc = "Problem-State Level-1 I-Cache Directory Write Count", }, { .ctrnum = 35, .ctrset = CPUMF_CTRSET_PROBLEM_STATE, .name = "PROBLEM_STATE_L1I_PENALTY_CYCLES", .desc = "Problem-State Level-1 I-Cache Penalty Cycle Count", }, { .ctrnum = 36, .ctrset = CPUMF_CTRSET_PROBLEM_STATE, .name = "PROBLEM_STATE_L1D_DIR_WRITES", .desc = "Problem-State Level-1 D-Cache Directory Write Count", }, { .ctrnum = 37, .ctrset = CPUMF_CTRSET_PROBLEM_STATE, .name = "PROBLEM_STATE_L1D_PENALTY_CYCLES", .desc = "Problem-State Level-1 D-Cache Penalty Cycle Count", }, { .ctrnum = 64, .ctrset = CPUMF_CTRSET_CRYPTO, .name = "PRNG_FUNCTIONS", .desc = "Total number of the PRNG functions issued by the" " CPU", }, { .ctrnum = 65, .ctrset = CPUMF_CTRSET_CRYPTO, .name = "PRNG_CYCLES", .desc = "Total number of CPU cycles when the DEA/AES" " coprocessor is busy performing PRNG functions" " issued by the CPU", }, { .ctrnum = 66, .ctrset = CPUMF_CTRSET_CRYPTO, .name = "PRNG_BLOCKED_FUNCTIONS", .desc = "Total number of the PRNG functions that are issued" " by the CPU and are blocked because the DEA/AES" " coprocessor is busy performing a function issued by" " another CPU", }, { .ctrnum = 67, .ctrset = CPUMF_CTRSET_CRYPTO, .name = "PRNG_BLOCKED_CYCLES", .desc = "Total number of CPU cycles blocked for the PRNG" " functions issued by the CPU because the DEA/AES" " coprocessor is busy performing a function issued by" " another CPU", }, { .ctrnum = 68, .ctrset = CPUMF_CTRSET_CRYPTO, .name = "SHA_FUNCTIONS", .desc = "Total number of SHA functions issued by the CPU", }, { .ctrnum = 69, .ctrset = CPUMF_CTRSET_CRYPTO, .name = "SHA_CYCLES", .desc = "Total number of CPU cycles when the SHA coprocessor" " is busy performing the SHA functions issued by the" " CPU", }, { .ctrnum = 70, .ctrset = CPUMF_CTRSET_CRYPTO, .name = "SHA_BLOCKED_FUNCTIONS", .desc = "Total number of the SHA functions that are issued" " by the CPU and are blocked because the SHA" " coprocessor is busy performing a function issued by" " another CPU", }, { .ctrnum = 71, .ctrset = CPUMF_CTRSET_CRYPTO, .name = "SHA_BLOCKED_CYCLES", .desc = "Total number of CPU cycles blocked for the SHA" " functions issued by the CPU because the SHA" " coprocessor is busy performing a function issued by" " another CPU", }, { .ctrnum = 72, .ctrset = CPUMF_CTRSET_CRYPTO, .name = "DEA_FUNCTIONS", .desc = "Total number of the DEA functions issued by the CPU", }, { .ctrnum = 73, .ctrset = CPUMF_CTRSET_CRYPTO, .name = "DEA_CYCLES", .desc = "Total number of CPU cycles when the DEA/AES" " coprocessor is busy performing the DEA functions" " issued by the CPU", }, { .ctrnum = 74, .ctrset = CPUMF_CTRSET_CRYPTO, .name = "DEA_BLOCKED_FUNCTIONS", .desc = "Total number of the DEA functions that are issued" " by the CPU and are blocked because the DEA/AES" " coprocessor is busy performing a function issued by" " another CPU", }, { .ctrnum = 75, .ctrset = CPUMF_CTRSET_CRYPTO, .name = "DEA_BLOCKED_CYCLES", .desc = "Total number of CPU cycles blocked for the DEA" " functions issued by the CPU because the DEA/AES" " coprocessor is busy performing a function issued by" " another CPU", }, { .ctrnum = 76, .ctrset = CPUMF_CTRSET_CRYPTO, .name = "AES_FUNCTIONS", .desc = "Total number of AES functions issued by the CPU", }, { .ctrnum = 77, .ctrset = CPUMF_CTRSET_CRYPTO, .name = "AES_CYCLES", .desc = "Total number of CPU cycles when the DEA/AES" " coprocessor is busy performing the AES functions" " issued by the CPU", }, { .ctrnum = 78, .ctrset = CPUMF_CTRSET_CRYPTO, .name = "AES_BLOCKED_FUNCTIONS", .desc = "Total number of AES functions that are issued by" " the CPU and are blocked because the DEA/AES" " coprocessor is busy performing a function issued by" " another CPU", }, { .ctrnum = 79, .ctrset = CPUMF_CTRSET_CRYPTO, .name = "AES_BLOCKED_CYCLES", .desc = "Total number of CPU cycles blocked for the AES" " functions issued by the CPU because the DEA/AES" " coprocessor is busy performing a function issued by" " another CPU", }, }; static const pme_cpumf_ctr_t cpumcf_z10_counters[] = { { .ctrnum = 128, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1I_L2_SOURCED_WRITES", .desc = "A directory write to the Level-1 I-Cache directory" " where the returned cache line was sourced from the" " Level-2 (L1.5) cache", }, { .ctrnum = 129, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1D_L2_SOURCED_WRITES", .desc = "A directory write to the Level-1 D-Cache directory" " where the installed cache line was sourced from the" " Level-2 (L1.5) cache", }, { .ctrnum = 130, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1I_L3_LOCAL_WRITES", .desc = "A directory write to the Level-1 I-Cache directory" " where the installed cache line was sourced from the" " Level-3 cache that is on the same book as the" " Instruction cache (Local L2 cache)", }, { .ctrnum = 131, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1D_L3_LOCAL_WRITES", .desc = "A directory write to the Level-1 D-Cache directory" " where the installtion cache line was source from" " the Level-3 cache that is on the same book as the" " Data cache (Local L2 cache)", }, { .ctrnum = 132, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1I_L3_REMOTE_WRITES", .desc = "A directory write to the Level-1 I-Cache directory" " where the installed cache line was sourced from a" " Level-3 cache that is not on the same book as the" " Instruction cache (Remote L2 cache)", }, { .ctrnum = 133, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1D_L3_REMOTE_WRITES", .desc = "A directory write to the Level-1 D-Cache directory" " where the installed cache line was sourced from a" " Level-3 cache that is not on the same book as the" " Data cache (Remote L2 cache)", }, { .ctrnum = 134, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1D_LMEM_SOURCED_WRITES", .desc = "A directory write to the Level-1 D-Cache directory" " where the installed cache line was sourced from" " memory that is attached to the same book as the" " Data cache (Local Memory)", }, { .ctrnum = 135, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1I_LMEM_SOURCED_WRITES", .desc = "A directory write to the Level-1 I-Cache where the" " installed cache line was sourced from memory that" " is attached to the s ame book as the Instruction" " cahe (local Memory)", }, { .ctrnum = 136, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1D_RO_EXCL_WRITES", .desc = "A directory write to the Level-1 D-Cache where the" " line was originally in a Read-Only state in the" " cache but has been updated to be in the Exclusive" " state that allows stores to the cache line", }, { .ctrnum = 137, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1I_CACHELINE_INVALIDATES", .desc = "A cache line in the Level-1 I-Cache has been" " invalidated by a store on the same CPU as the" " Level-1 I-Cache", }, { .ctrnum = 138, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "ITLB1_WRITES", .desc = "A translation entry has been written into the" " Level-1 Instruction Translation Lookaside Buffer", }, { .ctrnum = 139, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "DTLB1_WRITES", .desc = "A translation entry has been written to the Level-1" " Data Translation Lookaside Buffer", }, { .ctrnum = 140, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "TLB2_PTE_WRITES", .desc = "A translation entry has been written to the Level-2" " TLB Page Table Entry arrays", }, { .ctrnum = 141, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "TLB2_CRSTE_WRITES", .desc = "A translation entry has been written to the Level-2" " TLB Common Region Segment Table Entry arrays", }, { .ctrnum = 142, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "TLB2_CRSTE_HPAGE_WRITES", .desc = "A translation entry has been written to the Level-2" " TLB Common Region Segment Table Entry arrays for a" " one-megabyte large page translation", }, { .ctrnum = 145, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "ITLB1_MISSES", .desc = "Level-1 Instruction TLB miss in progress." " Incremented by one for every cycle an ITLB1 miss is" " in progress", }, { .ctrnum = 146, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "DTLB1_MISSES", .desc = "Level-1 Data TLB miss in progress. Incremented by" " one for every cycle an DTLB1 miss is in progress", }, { .ctrnum = 147, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L2C_STORES_SENT", .desc = "Incremented by one for every store sent to Level-2" " (L1.5) cache", }, }; static const pme_cpumf_ctr_t cpumcf_z196_counters[] = { { .ctrnum = 128, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1D_L2_SOURCED_WRITES", .desc = "A directory write to the Level-1 D-Cache directory" " where the returned cache line was sourced from the" " Level-2 cache", }, { .ctrnum = 129, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1I_L2_SOURCED_WRITES", .desc = "A directory write to the Level-1 I-Cache directory" " where the returned cache line was sourced from the" " Level-2 cache", }, { .ctrnum = 130, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "DTLB1_MISSES", .desc = "Level-1 Data TLB miss in progress. Incremented by" " one for every cycle a DTLB1 miss is in progress.", }, { .ctrnum = 131, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "ITLB1_MISSES", .desc = "Level-1 Instruction TLB miss in progress." " Incremented by one for every cycle a ITLB1 miss is" " in progress.", }, { .ctrnum = 133, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L2C_STORES_SENT", .desc = "Incremented by one for every store sent to Level-2" " cache", }, { .ctrnum = 134, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1D_OFFBOOK_L3_SOURCED_WRITES", .desc = "A directory write to the Level-1 D-Cache directory" " where the returned cache line was sourced from an" " Off Book Level-3 cache", }, { .ctrnum = 135, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1D_ONBOOK_L4_SOURCED_WRITES", .desc = "A directory write to the Level-1 D-Cache directory" " where the returned cache line was sourced from an" " On Book Level-4 cache", }, { .ctrnum = 136, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1I_ONBOOK_L4_SOURCED_WRITES", .desc = "A directory write to the Level-1 I-Cache directory" " where the returned cache line was sourced from an" " On Book Level-4 cache", }, { .ctrnum = 137, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1D_RO_EXCL_WRITES", .desc = "A directory write to the Level-1 D-Cache where the" " line was originally in a Read-Only state in the" " cache but has been updated to be in the Exclusive" " state that allows stores to the cache line", }, { .ctrnum = 138, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1D_OFFBOOK_L4_SOURCED_WRITES", .desc = "A directory write to the Level-1 D-Cache directory" " where the returned cache line was sourced from an" " Off Book Level-4 cache", }, { .ctrnum = 139, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1I_OFFBOOK_L4_SOURCED_WRITES", .desc = "A directory write to the Level-1 I-Cache directory" " where the returned cache line was sourced from an" " Off Book Level-4 cache", }, { .ctrnum = 140, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "DTLB1_HPAGE_WRITES", .desc = "A translation entry has been written to the Level-1" " Data Translation Lookaside Buffer for a one-" " megabyte page", }, { .ctrnum = 141, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1D_LMEM_SOURCED_WRITES", .desc = "A directory write to the Level-1 D-Cache where the" " installed cache line was sourced from memory that" " is attached to the same book as the Data cache" " (Local Memory)", }, { .ctrnum = 142, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1I_LMEM_SOURCED_WRITES", .desc = "A directory write to the Level-1 I-Cache where the" " installed cache line was sourced from memory that" " is attached to the same book as the Instruction" " cache (Local Memory)", }, { .ctrnum = 143, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1I_OFFBOOK_L3_SOURCED_WRITES", .desc = "A directory write to the Level-1 I-Cache directory" " where the returned cache line was sourced from an" " Off Book Level-3 cache", }, { .ctrnum = 144, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "DTLB1_WRITES", .desc = "A translation entry has been written to the Level-1" " Data Translation Lookaside Buffer", }, { .ctrnum = 145, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "ITLB1_WRITES", .desc = "A translation entry has been written to the Level-1" " Instruction Translation Lookaside Buffer", }, { .ctrnum = 146, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "TLB2_PTE_WRITES", .desc = "A translation entry has been written to the Level-2" " TLB Page Table Entry arrays", }, { .ctrnum = 147, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "TLB2_CRSTE_HPAGE_WRITES", .desc = "A translation entry has been written to the Level-2" " TLB Common Region Segment Table Entry arrays for a" " one-megabyte large page translation", }, { .ctrnum = 148, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "TLB2_CRSTE_WRITES", .desc = "A translation entry has been written to the Level-2" " TLB Common Region Segment Table Entry arrays", }, { .ctrnum = 150, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1D_ONCHIP_L3_SOURCED_WRITES", .desc = "A directory write to the Level-1 D-Cache directory" " where the returned cache line was sourced from an" " On Chip Level-3 cache", }, { .ctrnum = 152, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1D_OFFCHIP_L3_SOURCED_WRITES", .desc = "A directory write to the Level-1 D-Cache directory" " where the returned cache line was sourced from an" " Off Chip/On Book Level-3 cache", }, { .ctrnum = 153, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1I_ONCHIP_L3_SOURCED_WRITES", .desc = "A directory write to the Level-1 I-Cache directory" " where the returned cache line was sourced from an" " On Chip Level-3 cache", }, { .ctrnum = 155, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1I_OFFCHIP_L3_SOURCED_WRITES", .desc = "A directory write to the Level-1 I-Cache directory" " where the returned cache line was sourced from an" " Off Chip/On Book Level-3 cache", }, }; static const pme_cpumf_ctr_t cpumcf_zec12_counters[] = { { .ctrnum = 128, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "DTLB1_MISSES", .desc = "Level-1 Data TLB miss in progress. Incremented by" " one for every cycle a DTLB1 miss is in progress.", }, { .ctrnum = 129, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "ITLB1_MISSES", .desc = "Level-1 Instruction TLB miss in progress." " Incremented by one for every cycle a ITLB1 miss is" " in progress.", }, { .ctrnum = 130, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1D_L2I_SOURCED_WRITES", .desc = "A directory write to the Level-1 Data cache" " directory where the returned cache line was sourced" " from the Level-2 Instruction cache", }, { .ctrnum = 131, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1I_L2I_SOURCED_WRITES", .desc = "A directory write to the Level-1 Instruction cache" " directory where the returned cache line was sourced" " from the Level-2 Instruction cache", }, { .ctrnum = 132, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1D_L2D_SOURCED_WRITES", .desc = "A directory write to the Level-1 Data cache" " directory where the returned cache line was sourced" " from the Level-2 Data cache", }, { .ctrnum = 133, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "DTLB1_WRITES", .desc = "A translation entry has been written to the Level-1" " Data Translation Lookaside Buffer", }, { .ctrnum = 135, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1D_LMEM_SOURCED_WRITES", .desc = "A directory write to the Level-1 Data cache where" " the installed cache line was sourced from memory" " that is attached to the same book as the Data cache" " (Local Memory)", }, { .ctrnum = 137, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1I_LMEM_SOURCED_WRITES", .desc = "A directory write to the Level-1 Instruction cache" " where the installed cache line was sourced from" " memory that is attached to the same book as the" " Instruction cache (Local Memory)", }, { .ctrnum = 138, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1D_RO_EXCL_WRITES", .desc = "A directory write to the Level-1 D-Cache where the" " line was originally in a Read-Only state in the" " cache but has been updated to be in the Exclusive" " state that allows stores to the cache line", }, { .ctrnum = 139, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "DTLB1_HPAGE_WRITES", .desc = "A translation entry has been written to the Level-1" " Data Translation Lookaside Buffer for a one-" " megabyte page", }, { .ctrnum = 140, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "ITLB1_WRITES", .desc = "A translation entry has been written to the Level-1" " Instruction Translation Lookaside Buffer", }, { .ctrnum = 141, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "TLB2_PTE_WRITES", .desc = "A translation entry has been written to the Level-2" " TLB Page Table Entry arrays", }, { .ctrnum = 142, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "TLB2_CRSTE_HPAGE_WRITES", .desc = "A translation entry has been written to the Level-2" " TLB Common Region Segment Table Entry arrays for a" " one-megabyte large page translation", }, { .ctrnum = 143, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "TLB2_CRSTE_WRITES", .desc = "A translation entry has been written to the Level-2" " TLB Common Region Segment Table Entry arrays", }, { .ctrnum = 144, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1D_ONCHIP_L3_SOURCED_WRITES", .desc = "A directory write to the Level-1 Data cache" " directory where the returned cache line was sourced" " from an On Chip Level-3 cache without intervention", }, { .ctrnum = 145, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1D_OFFCHIP_L3_SOURCED_WRITES", .desc = "A directory write to the Level-1 Data cache" " directory where the returned cache line was sourced" " from an Off Chip/On Book Level-3 cache without" " intervention", }, { .ctrnum = 146, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1D_OFFBOOK_L3_SOURCED_WRITES", .desc = "A directory write to the Level-1 Data cache" " directory where the returned cache line was sourced" " from an Off Book Level-3 cache without intervention", }, { .ctrnum = 147, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1D_ONBOOK_L4_SOURCED_WRITES", .desc = "A directory write to the Level-1 Data cache" " directory where the returned cache line was sourced" " from an On Book Level-4 cache", }, { .ctrnum = 148, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1D_OFFBOOK_L4_SOURCED_WRITES", .desc = "A directory write to the Level-1 Data cache" " directory where the returned cache line was sourced" " from an Off Book Level-4 cache", }, { .ctrnum = 149, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "TX_NC_TEND", .desc = "A TEND instruction has completed in a" " nonconstrained transactional-execution mode", }, { .ctrnum = 150, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1D_ONCHIP_L3_SOURCED_WRITES_IV", .desc = "A directory write to the Level-1 Data cache" " directory where the returned cache line was sourced" " from a On Chip Level-3 cache with intervention", }, { .ctrnum = 151, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1D_OFFCHIP_L3_SOURCED_WRITES_IV", .desc = "A directory write to the Level-1 Data cache" " directory where the returned cache line was sourced" " from an Off Chip/On Book Level-3 cache with" " intervention", }, { .ctrnum = 152, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1D_OFFBOOK_L3_SOURCED_WRITES_IV", .desc = "A directory write to the Level-1 Data cache" " directory where the returned cache line was sourced" " from an Off Book Level-3 cache with intervention", }, { .ctrnum = 153, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1I_ONCHIP_L3_SOURCED_WRITES", .desc = "A directory write to the Level-1 Instruction cache" " directory where the returned cache line was sourced" " from an On Chip Level-3 cache without intervention", }, { .ctrnum = 154, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1I_OFFCHIP_L3_SOURCED_WRITES", .desc = "A directory write to the Level-1 Instruction cache" " directory where the returned cache line was sourced" " from an Off Chip/On Book Level-3 cache without" " intervention", }, { .ctrnum = 155, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1I_OFFBOOK_L3_SOURCED_WRITES", .desc = "A directory write to the Level-1 Instruction cache" " directory where the returned cache line was sourced" " from an Off Book Level-3 cache without intervention", }, { .ctrnum = 156, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1I_ONBOOK_L4_SOURCED_WRITES", .desc = "A directory write to the Level-1 Instruction cache" " directory where the returned cache line was sourced" " from an On Book Level-4 cache", }, { .ctrnum = 157, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1I_OFFBOOK_L4_SOURCED_WRITES", .desc = "A directory write to the Level-1 Instruction cache" " directory where the returned cache line was sourced" " from an Off Book Level-4 cache", }, { .ctrnum = 158, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "TX_C_TEND", .desc = "A TEND instruction has completed in a constrained" " transactional-execution mode", }, { .ctrnum = 159, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1I_ONCHIP_L3_SOURCED_WRITES_IV", .desc = "A directory write to the Level-1 Instruction cache" " directory where the returned cache line was sourced" " from an On Chip Level-3 cache with intervention", }, { .ctrnum = 160, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1I_OFFCHIP_L3_SOURCED_WRITES_IV", .desc = "A directory write to the Level-1 Instruction cache" " directory where the returned cache line was sourced" " from an Off Chip/On Book Level-3 cache with" " intervention", }, { .ctrnum = 161, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1I_OFFBOOK_L3_SOURCED_WRITES_IV", .desc = "A directory write to the Level-1 Instruction cache" " directory where the returned cache line was sourced" " from an Off Book Level-3 cache with intervention", }, { .ctrnum = 177, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "TX_NC_TABORT", .desc = "A transaction abort has occurred in a" " nonconstrained transactional-execution mode", }, { .ctrnum = 178, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "TX_C_TABORT_NO_SPECIAL", .desc = "A transaction abort has occurred in a constrained" " transactional-execution mode and the CPU is not" " using any special logic to allow the transaction to" " complete", }, { .ctrnum = 179, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "TX_C_TABORT_SPECIAL", .desc = "A transaction abort has occurred in a constrained" " transactional-execution mode and the CPU is using" " special logic to allow the transaction to complete", }, }; static const pme_cpumf_ctr_t cpumcf_z13_counters[] = { { .ctrnum = 128, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1D_WRITES_RO_EXCL", .desc = "Counter:128 Name:L1D_WRITES_RO_EXCL A directory" " write to the Level-1 Data cache where the line was" " originally in a Read-Only state in the cache but" " has been updated to be in the Exclusive state that" " allows stores to the cache line.", }, { .ctrnum = 129, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "DTLB1_WRITES", .desc = "A translation entry has been written to the Level-1" " Data Translation Lookaside Buffer", }, { .ctrnum = 130, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "DTLB1_MISSES", .desc = "Level-1 Data TLB miss in progress. Incremented by" " one for every cycle a DTLB1 miss is in progress.", }, { .ctrnum = 131, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "DTLB1_HPAGE_WRITES", .desc = "A translation entry has been written to the Level-1" " Data Translation Lookaside Buffer for a one-" " megabyte page", }, { .ctrnum = 132, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "DTLB1_GPAGE_WRITES", .desc = "Counter:132 Name:DTLB1_GPAGE_WRITES A translation" " entry has been written to the Level-1 Data" " Translation Lookaside Buffer for a two-gigabyte" " page.", }, { .ctrnum = 133, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1D_L2D_SOURCED_WRITES", .desc = "A directory write to the Level-1 Data cache" " directory where the returned cache line was sourced" " from the Level-2 Data cache", }, { .ctrnum = 134, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "ITLB1_WRITES", .desc = "A translation entry has been written to the Level-1" " Instruction Translation Lookaside Buffer", }, { .ctrnum = 135, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "ITLB1_MISSES", .desc = "Level-1 Instruction TLB miss in progress." " Incremented by one for every cycle an ITLB1 miss is" " in progress", }, { .ctrnum = 136, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1I_L2I_SOURCED_WRITES", .desc = "A directory write to the Level-1 Instruction cache" " directory where the returned cache line was sourced" " from the Level-2 Instruction cache", }, { .ctrnum = 137, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "TLB2_PTE_WRITES", .desc = "A translation entry has been written to the Level-2" " TLB Page Table Entry arrays", }, { .ctrnum = 138, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "TLB2_CRSTE_HPAGE_WRITES", .desc = "A translation entry has been written to the Level-2" " TLB Combined Region Segment Table Entry arrays for" " a one-megabyte large page translation", }, { .ctrnum = 139, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "TLB2_CRSTE_WRITES", .desc = "A translation entry has been written to the Level-2" " TLB Combined Region Segment Table Entry arrays", }, { .ctrnum = 140, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "TX_C_TEND", .desc = "A TEND instruction has completed in a constrained" " transactional-execution mode", }, { .ctrnum = 141, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "TX_NC_TEND", .desc = "A TEND instruction has completed in a non-" " constrained transactional-execution mode", }, { .ctrnum = 143, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1C_TLB1_MISSES", .desc = "Increments by one for any cycle where a Level-1" " cache or Level-1 TLB miss is in progress.", }, { .ctrnum = 144, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1D_ONCHIP_L3_SOURCED_WRITES", .desc = "A directory write to the Level-1 Data cache" " directory where the returned cache line was sourced" " from an On-Chip Level-3 cache without intervention", }, { .ctrnum = 145, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1D_ONCHIP_L3_SOURCED_WRITES_IV", .desc = "A directory write to the Level-1 Data cache" " directory where the returned cache line was sourced" " from an On-Chip Level-3 cache with intervention", }, { .ctrnum = 146, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1D_ONNODE_L4_SOURCED_WRITES", .desc = "A directory write to the Level-1 Data cache" " directory where the returned cache line was sourced" " from an On-Node Level-4 cache", }, { .ctrnum = 147, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1D_ONNODE_L3_SOURCED_WRITES_IV", .desc = "A directory write to the Level-1 Data cache" " directory where the returned cache line was sourced" " from an On-Node Level-3 cache with intervention", }, { .ctrnum = 148, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1D_ONNODE_L3_SOURCED_WRITES", .desc = "A directory write to the Level-1 Data cache" " directory where the returned cache line was sourced" " from an On-Node Level-3 cache without intervention", }, { .ctrnum = 149, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1D_ONDRAWER_L4_SOURCED_WRITES", .desc = "A directory write to the Level-1 Data cache" " directory where the returned cache line was sourced" " from an On-Drawer Level-4 cache", }, { .ctrnum = 150, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1D_ONDRAWER_L3_SOURCED_WRITES_IV", .desc = "A directory write to the Level-1 Data cache" " directory where the returned cache line was sourced" " from an On-Drawer Level-3 cache with intervention", }, { .ctrnum = 151, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1D_ONDRAWER_L3_SOURCED_WRITES", .desc = "A directory write to the Level-1 Data cache" " directory where the returned cache line was sourced" " from an On-Drawer Level-3 cache without" " intervention", }, { .ctrnum = 152, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1D_OFFDRAWER_SCOL_L4_SOURCED_WRITES", .desc = "A directory write to the Level-1 Data cache" " directory where the returned cache line was sourced" " from an Off-Drawer Same-Column Level-4 cache", }, { .ctrnum = 153, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV", .desc = "A directory write to the Level-1 Data cache" " directory where the returned cache line was sourced" " from an Off-Drawer Same-Column Level-3 cache with" " intervention", }, { .ctrnum = 154, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES", .desc = "A directory write to the Level-1 Data cache" " directory where the returned cache line was sourced" " from an Off-Drawer Same-Column Level-3 cache" " without intervention", }, { .ctrnum = 155, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1D_OFFDRAWER_FCOL_L4_SOURCED_WRITES", .desc = "A directory write to the Level-1 Data cache" " directory where the returned cache line was sourced" " from an Off-Drawer Far-Column Level-4 cache", }, { .ctrnum = 156, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV", .desc = "A directory write to the Level-1 Data cache" " directory where the returned cache line was sourced" " from an Off-Drawer Far-Column Level-3 cache with" " intervention", }, { .ctrnum = 157, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES", .desc = "A directory write to the Level-1 Data cache" " directory where the returned cache line was sourced" " from an Off-Drawer Far-Column Level-3 cache without" " intervention", }, { .ctrnum = 158, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1D_ONNODE_MEM_SOURCED_WRITES", .desc = "A directory write to the Level-1 Data cache" " directory where the returned cache line was sourced" " from On-Node memory", }, { .ctrnum = 159, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1D_ONDRAWER_MEM_SOURCED_WRITES", .desc = "A directory write to the Level-1 Data cache" " directory where the returned cache line was sourced" " from On-Drawer memory", }, { .ctrnum = 160, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1D_OFFDRAWER_MEM_SOURCED_WRITES", .desc = "A directory write to the Level-1 Data cache" " directory where the returned cache line was sourced" " from On-Drawer memory", }, { .ctrnum = 161, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1D_ONCHIP_MEM_SOURCED_WRITES", .desc = "A directory write to the Level-1 Data cache" " directory where the returned cache line was sourced" " from On-Chip memory", }, { .ctrnum = 162, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1I_ONCHIP_L3_SOURCED_WRITES", .desc = "A directory write to the Level-1 Instruction cache" " directory where the returned cache line was sourced" " from an On-Chip Level-3 cache without intervention", }, { .ctrnum = 163, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1I_ONCHIP_L3_SOURCED_WRITES_IV", .desc = "A directory write to the Level-1 Instruction cache" " directory where the returned cache line was sourced" " from an On Chip Level-3 cache with intervention", }, { .ctrnum = 164, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1I_ONNODE_L4_SOURCED_WRITES", .desc = "A directory write to the Level-1 Instruction cache" " directory where the returned cache line was sourced" " from an On-Node Level-4 cache", }, { .ctrnum = 165, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1I_ONNODE_L3_SOURCED_WRITES_IV", .desc = "A directory write to the Level-1 Instruction cache" " directory where the returned cache line was sourced" " from an On-Node Level-3 cache with intervention", }, { .ctrnum = 166, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1I_ONNODE_L3_SOURCED_WRITES", .desc = "A directory write to the Level-1 Instruction cache" " directory where the returned cache line was sourced" " from an On-Node Level-3 cache without intervention", }, { .ctrnum = 167, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1I_ONDRAWER_L4_SOURCED_WRITES", .desc = "A directory write to the Level-1 Instruction cache" " directory where the returned cache line was sourced" " from an On-Drawer Level-4 cache", }, { .ctrnum = 168, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1I_ONDRAWER_L3_SOURCED_WRITES_IV", .desc = "A directory write to the Level-1 Instruction cache" " directory where the returned cache line was sourced" " from an On-Drawer Level-3 cache with intervention", }, { .ctrnum = 169, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1I_ONDRAWER_L3_SOURCED_WRITES", .desc = "A directory write to the Level-1 Instruction cache" " directory where the returned cache line was sourced" " from an On-Drawer Level-3 cache without" " intervention", }, { .ctrnum = 170, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1I_OFFDRAWER_SCOL_L4_SOURCED_WRITES", .desc = "A directory write to the Level-1 Instruction cache" " directory where the returned cache line was sourced" " from an Off-Drawer Same-Column Level-4 cache", }, { .ctrnum = 171, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV", .desc = "A directory write to the Level-1 Instruction cache" " directory where the returned cache line was sourced" " from an Off-Drawer Same-Column Level-3 cache with" " intervention", }, { .ctrnum = 172, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES", .desc = "A directory write to the Level-1 Instruction cache" " directory where the returned cache line was sourced" " from an Off-Drawer Same-Column Level-3 cache" " without intervention", }, { .ctrnum = 173, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1I_OFFDRAWER_FCOL_L4_SOURCED_WRITES", .desc = "A directory write to the Level-1 Instruction cache" " directory where the returned cache line was sourced" " from an Off-Drawer Far-Column Level-4 cache", }, { .ctrnum = 174, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV", .desc = "A directory write to the Level-1 Instruction cache" " directory where the returned cache line was sourced" " from an Off-Drawer Far-Column Level-3 cache with" " intervention", }, { .ctrnum = 175, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES", .desc = "A directory write to the Level-1 Instruction cache" " directory where the returned cache line was sourced" " from an Off-Drawer Far-Column Level-3 cache without" " intervention", }, { .ctrnum = 176, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1I_ONNODE_MEM_SOURCED_WRITES", .desc = "A directory write to the Level-1 Instruction cache" " directory where the returned cache line was sourced" " from On-Node memory", }, { .ctrnum = 177, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1I_ONDRAWER_MEM_SOURCED_WRITES", .desc = "A directory write to the Level-1 Instruction cache" " directory where the returned cache line was sourced" " from On-Drawer memory", }, { .ctrnum = 178, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1I_OFFDRAWER_MEM_SOURCED_WRITES", .desc = "A directory write to the Level-1 Instruction cache" " directory where the returned cache line was sourced" " from On-Drawer memory", }, { .ctrnum = 179, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "L1I_ONCHIP_MEM_SOURCED_WRITES", .desc = "A directory write to the Level-1 Instruction cache" " directory where the returned cache line was sourced" " from On-Chip memory", }, { .ctrnum = 218, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "TX_NC_TABORT", .desc = "A transaction abort has occurred in a non-" " constrained transactional-execution mode", }, { .ctrnum = 219, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "TX_C_TABORT_NO_SPECIAL", .desc = "A transaction abort has occurred in a constrained" " transactional-execution mode and the CPU is not" " using any special logic to allow the transaction to" " complete", }, { .ctrnum = 220, .ctrset = CPUMF_CTRSET_EXTENDED, .name = "TX_C_TABORT_SPECIAL", .desc = "A transaction abort has occurred in a constrained" " transactional-execution mode and the CPU is using" " special logic to allow the transaction to complete", }, { .ctrnum = 448, .ctrset = CPUMF_CTRSET_MT_DIAG, .name = "MT_DIAG_CYCLES_ONE_THR_ACTIVE", .desc = "Cycle count with one thread active", }, { .ctrnum = 449, .ctrset = CPUMF_CTRSET_MT_DIAG, .name = "MT_DIAG_CYCLES_TWO_THR_ACTIVE", .desc = "Cycle count with two threads active", }, }; static const pme_cpumf_ctr_t cpumsf_counters[] = { { .ctrnum = 720896, .ctrset = CPUMF_CTRSET_NONE, .name = "SF_CYCLES_BASIC", .desc = "Sample CPU cycles using basic-sampling mode", }, { .ctrnum = 774144, .ctrset = CPUMF_CTRSET_NONE, .name = "SF_CYCLES_BASIC_DIAG", .desc = "Sample CPU cycle using diagnostic-sampling mode" " (not for ordinary use)", }, }; #endif /* __S390X_CPUMF_EVENTS_H__ */ libpfm-4.9.0/lib/events/sparc_ultra3_events.h0000664000175000017500000002456213223402656021040 0ustar eranianeranianstatic const sparc_entry_t ultra3_pe[] = { /* These two must always be first. */ { .name = "Cycle_cnt", .desc = "Accumulated cycles", .ctrl = PME_CTRL_S0 | PME_CTRL_S1, .code = 0x0, }, { .name = "Instr_cnt", .desc = "Number of instructions completed", .ctrl = PME_CTRL_S0 | PME_CTRL_S1, .code = 0x1, }, /* PIC0 events common to all UltraSPARC processors */ { .name = "Dispatch0_IC_miss", .desc = "I-buffer is empty from I-Cache miss", .ctrl = PME_CTRL_S0, .code = 0x2, }, { .name = "IC_ref", .desc = "I-cache references", .ctrl = PME_CTRL_S0, .code = 0x8, }, { .name = "DC_rd", .desc = "D-cache read references (including accesses that subsequently trap)", .ctrl = PME_CTRL_S0, .code = 0x9, }, { .name = "DC_wr", .desc = "D-cache store accesses (including cacheable stores that subsequently trap)", .ctrl = PME_CTRL_S0, .code = 0xa, }, { .name = "EC_ref", .desc = "E-cache references", .ctrl = PME_CTRL_S0, .code = 0xc, }, { .name = "EC_snoop_inv", .desc = "L2-cache invalidates generated from a snoop by a remote processor", .ctrl = PME_CTRL_S0, .code = 0xe, }, /* PIC1 events common to all UltraSPARC processors */ { .name = "Dispatch0_mispred", .desc = "I-buffer is empty from Branch misprediction", .ctrl = PME_CTRL_S1, .code = 0x2, }, { .name = "EC_wb", .desc = "Dirty sub-blocks that produce writebacks due to L2-cache miss events", .ctrl = PME_CTRL_S1, .code = 0xd, }, { .name = "EC_snoop_cb", .desc = "L2-cache copybacks generated from a snoop by a remote processor", .ctrl = PME_CTRL_S1, .code = 0xe, }, /* PIC0 events common to all UltraSPARC-III/III+/IIIi processors */ { .name = "Dispatch0_br_target", .desc = "I-buffer is empty due to a branch target address calculation", .ctrl = PME_CTRL_S0, .code = 0x3, }, { .name = "Dispatch0_2nd_br", .desc = "Stall cycles due to having two branch instructions line-up in one 4-instruction group causing the second branch in the group to be re-fetched, delaying it's entrance into the I-buffer", .ctrl = PME_CTRL_S0, .code = 0x4, }, { .name = "Rstall_storeQ", .desc = "R-stage stall for a store instruction which is the next instruction to be executed, but it stalled due to the store queue being full", .ctrl = PME_CTRL_S0, .code = 0x5, }, { .name = "Rstall_IU_use", .desc = "R-stage stall for an event that the next instruction to be executed depends on the result of a preceding integer instruction in the pipeline that is not yet available", .ctrl = PME_CTRL_S0, .code = 0x6, }, { .name = "EC_write_hit_RTO", .desc = "W-cache exclusive requests that hit L2-cache in S, O, or Os state and thus, do a read-to-own bus transaction", .ctrl = PME_CTRL_S0, .code = 0xd, }, { .name = "EC_rd_miss", .desc = "L2-cache miss events (including atomics) from D-cache events", .ctrl = PME_CTRL_S0, .code = 0xf, }, { .name = "PC_port0_rd", .desc = "P-cache cacheable FP loads to the first port (general purpose load path to D-cache and P-cache via MS pipeline)", .ctrl = PME_CTRL_S0, .code = 0x10, }, { .name = "SI_snoop", .desc = "Counts snoops from remote processor(s) including RTS, RTSR, RTO, RTOR, RS, RSR, RTSM, and WS", .ctrl = PME_CTRL_S0, .code = 0x11, }, { .name = "SI_ciq_flow", .desc = "Counts system clock cycles when the flow control (PauseOut) signal is asserted", .ctrl = PME_CTRL_S0, .code = 0x12, }, { .name = "SI_owned", .desc = "Counts events where owned_in is asserted on bus requests from the local processor", .ctrl = PME_CTRL_S0, .code = 0x13, }, { .name = "SW_count0", .desc = "Counts software-generated occurrences of 'sethi %hi(0xfc000), %g0' instruction", .ctrl = PME_CTRL_S0, .code = 0x14, }, { .name = "IU_Stat_Br_miss_taken", .desc = "Retired branches that were predicted to be taken, but in fact were not taken", .ctrl = PME_CTRL_S0, .code = 0x15, }, { .name = "IU_Stat_Br_Count_taken", .desc = "Retired taken branches", .ctrl = PME_CTRL_S0, .code = 0x16, }, { .name = "Dispatch0_rs_mispred", .desc = "I-buffer is empty due to a Return Address Stack misprediction", .ctrl = PME_CTRL_S0, .code = 0x4, }, { .name = "FA_pipe_completion", .desc = "Instructions that complete execution on the FPG ALU pipelines", .ctrl = PME_CTRL_S0, .code = 0x18, }, /* PIC1 events common to all UltraSPARC-III/III+/IIIi processors */ { .name = "IC_miss_cancelled", .desc = "I-cache misses cancelled due to mis-speculation, recycle, or other events", .ctrl = PME_CTRL_S1, .code = 0x3, }, { .name = "Re_FPU_bypass", .desc = "Stall due to recirculation when an FPU bypass condition that does not have a direct bypass path occurs", .ctrl = PME_CTRL_S1, .code = 0x5, }, { .name = "Re_DC_miss", .desc = "Stall due to loads that miss D-cache and get recirculated", .ctrl = PME_CTRL_S1, .code = 0x6, }, { .name = "Re_EC_miss", .desc = "Stall due to loads that miss L2-cache and get recirculated", .ctrl = PME_CTRL_S1, .code = 0x7, }, { .name = "IC_miss", .desc = "I-cache misses, including fetches from mis-speculated execution paths which are later cancelled", .ctrl = PME_CTRL_S1, .code = 0x8, }, { .name = "DC_rd_miss", .desc = "Recirculated loads that miss the D-cache", .ctrl = PME_CTRL_S1, .code = 0x9, }, { .name = "DC_wr_miss", .desc = "D-cache store accesses that miss D-cache", .ctrl = PME_CTRL_S1, .code = 0xa, }, { .name = "Rstall_FP_use", .desc = "R-stage stall for an event that the next instruction to be executed depends on the result of a preceding floating-point instruction in the pipeline that is not yet available", .ctrl = PME_CTRL_S1, .code = 0xb, }, { .name = "EC_misses", .desc = "E-cache misses", .ctrl = PME_CTRL_S1, .code = 0xc, }, { .name = "EC_ic_miss", .desc = "L2-cache read misses from I-cache requests", .ctrl = PME_CTRL_S1, .code = 0xf, }, { .name = "Re_PC_miss", .desc = "Stall due to recirculation when a prefetch cache miss occurs on a prefetch predicted second load", .ctrl = PME_CTRL_S1, .code = 0x10, }, { .name = "ITLB_miss", .desc = "I-TLB miss traps taken", .ctrl = PME_CTRL_S1, .code = 0x11, }, { .name = "DTLB_miss", .desc = "Memory reference instructions which trap due to D-TLB miss", .ctrl = PME_CTRL_S1, .code = 0x12, }, { .name = "WC_miss", .desc = "W-cache misses", .ctrl = PME_CTRL_S1, .code = 0x13, }, { .name = "WC_snoop_cb", .desc = "W-cache copybacks generated by a snoop from a remote processor", .ctrl = PME_CTRL_S1, .code = 0x14, }, { .name = "WC_scrubbed", .desc = "W-cache hits to clean lines", .ctrl = PME_CTRL_S1, .code = 0x15, }, { .name = "WC_wb_wo_read", .desc = "W-cache writebacks not requiring a read", .ctrl = PME_CTRL_S1, .code = 0x16, }, { .name = "PC_soft_hit", .desc = "FP loads that hit a P-cache line that was prefetched by a software-prefetch instruction", .ctrl = PME_CTRL_S1, .code = 0x18, }, { .name = "PC_snoop_inv", .desc = "P-cache invalidates that were generated by a snoop from a remote processor and stores by a local processor", .ctrl = PME_CTRL_S1, .code = 0x19, }, { .name = "PC_hard_hit", .desc = "FP loads that hit a P-cache line that was prefetched by a hardware prefetch", .ctrl = PME_CTRL_S1, .code = 0x1a, }, { .name = "PC_port1_rd", .desc = "P-cache cacheable FP loads to the second port (memory and out-of-pipeline instruction execution loads via the A0 and A1 pipelines)", .ctrl = PME_CTRL_S1, .code = 0x1b, }, { .name = "SW_count1", .desc = "Counts software-generated occurrences of 'sethi %hi(0xfc000), %g0' instruction", .ctrl = PME_CTRL_S1, .code = 0x1c, }, { .name = "IU_Stat_Br_miss_untaken", .desc = "Retired branches that were predicted to be untaken, but in fact were taken", .ctrl = PME_CTRL_S1, .code = 0x1d, }, { .name = "IU_Stat_Br_Count_untaken", .desc = "Retired untaken branches", .ctrl = PME_CTRL_S1, .code = 0x1e, }, { .name = "PC_MS_miss", .desc = "FP loads through the MS pipeline that miss P-cache", .ctrl = PME_CTRL_S1, .code = 0x1f, }, { .name = "Re_RAW_miss", .desc = "Stall due to recirculation when there is a load in the E-stage which has a non-bypassable read-after-write hazard with an earlier store instruction", .ctrl = PME_CTRL_S1, .code = 0x26, }, { .name = "FM_pipe_completion", .desc = "Instructions that complete execution on the FPG Multiply pipelines", .ctrl = PME_CTRL_S0, .code = 0x27, }, /* PIC0 memory controller events common to UltraSPARC-III/III+ processors */ { .name = "MC_reads_0", .desc = "Read requests completed to memory bank 0", .ctrl = PME_CTRL_S0, .code = 0x20, }, { .name = "MC_reads_1", .desc = "Read requests completed to memory bank 1", .ctrl = PME_CTRL_S0, .code = 0x21, }, { .name = "MC_reads_2", .desc = "Read requests completed to memory bank 2", .ctrl = PME_CTRL_S0, .code = 0x22, }, { .name = "MC_reads_3", .desc = "Read requests completed to memory bank 3", .ctrl = PME_CTRL_S0, .code = 0x23, }, { .name = "MC_stalls_0", .desc = "Clock cycles that requests were stalled in the MCU queues because bank 0 was busy with a previous request", .ctrl = PME_CTRL_S0, .code = 0x24, }, { .name = "MC_stalls_2", .desc = "Clock cycles that requests were stalled in the MCU queues because bank 2 was busy with a previous request", .ctrl = PME_CTRL_S0, .code = 0x25, }, /* PIC1 memory controller events common to all UltraSPARC-III/III+ processors */ { .name = "MC_writes_0", .desc = "Write requests completed to memory bank 0", .ctrl = PME_CTRL_S1, .code = 0x20, }, { .name = "MC_writes_1", .desc = "Write requests completed to memory bank 1", .ctrl = PME_CTRL_S1, .code = 0x21, }, { .name = "MC_writes_2", .desc = "Write requests completed to memory bank 2", .ctrl = PME_CTRL_S1, .code = 0x22, }, { .name = "MC_writes_3", .desc = "Write requests completed to memory bank 3", .ctrl = PME_CTRL_S1, .code = 0x23, }, { .name = "MC_stalls_1", .desc = "Clock cycles that requests were stalled in the MCU queues because bank 1 was busy with a previous request", .ctrl = PME_CTRL_S1, .code = 0x24, }, { .name = "MC_stalls_3", .desc = "Clock cycles that requests were stalled in the MCU queues because bank 3 was busy with a previous request", .ctrl = PME_CTRL_S1, .code = 0x25, }, }; #define PME_SPARC_ULTRA3_EVENT_COUNT (sizeof(ultra3_pe)/sizeof(sparc_entry_t)) libpfm-4.9.0/lib/events/perf_events.h0000664000175000017500000002542413223402656017370 0ustar eranianeranian/* * Copyright (c) 2009 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. */ #define CACHE_ST_ACCESS(n, d, e) \ {\ .name = #n"-STORES",\ .desc = d" store accesses",\ .id = PERF_COUNT_HW_CACHE_##e,\ .type = PERF_TYPE_HW_CACHE,\ .modmsk = PERF_ATTR_HW,\ .umask_ovfl_idx = -1,\ .equiv = "PERF_COUNT_HW_CACHE_"#e":WRITE:ACCESS"\ },\ {\ .name = #n"-STORE-MISSES",\ .desc = d" store misses",\ .id = PERF_COUNT_HW_CACHE_##e,\ .type = PERF_TYPE_HW_CACHE,\ .modmsk = PERF_ATTR_HW,\ .umask_ovfl_idx = -1,\ .equiv = "PERF_COUNT_HW_CACHE_"#e":WRITE:MISS"\ } #define CACHE_PF_ACCESS(n, d, e) \ {\ .name = #n"-PREFETCHES",\ .desc = d" prefetch accesses",\ .id = PERF_COUNT_HW_CACHE_##e,\ .type = PERF_TYPE_HW_CACHE,\ .modmsk = PERF_ATTR_HW,\ .umask_ovfl_idx = -1,\ .equiv = "PERF_COUNT_HW_CACHE_"#e":PREFETCH:ACCESS"\ },\ {\ .name = #n"-PREFETCH-MISSES",\ .desc = d" prefetch misses",\ .id = PERF_COUNT_HW_CACHE_##e,\ .type = PERF_TYPE_HW_CACHE,\ .modmsk = PERF_ATTR_HW,\ .umask_ovfl_idx = -1,\ .equiv = "PERF_COUNT_HW_CACHE_"#e":PREFETCH:MISS"\ } #define CACHE_LD_ACCESS(n, d, e) \ {\ .name = #n"-LOADS",\ .desc = d" load accesses",\ .id = PERF_COUNT_HW_CACHE_##e,\ .type = PERF_TYPE_HW_CACHE,\ .modmsk = PERF_ATTR_HW,\ .umask_ovfl_idx = -1,\ .equiv = "PERF_COUNT_HW_CACHE_"#e":READ:ACCESS"\ },\ {\ .name = #n"-LOAD-MISSES",\ .desc = d" load misses",\ .id = PERF_COUNT_HW_CACHE_##e,\ .type = PERF_TYPE_HW_CACHE,\ .modmsk = PERF_ATTR_HW,\ .umask_ovfl_idx = -1,\ .equiv = "PERF_COUNT_HW_CACHE_"#e":READ:MISS"\ } #define CACHE_ACCESS(n, d, e) \ CACHE_LD_ACCESS(n, d, e), \ CACHE_ST_ACCESS(n, d, e), \ CACHE_PF_ACCESS(n, d, e) #define ICACHE_ACCESS(n, d, e) \ CACHE_LD_ACCESS(n, d, e), \ CACHE_PF_ACCESS(n, d, e) static perf_event_t perf_static_events[]={ PCL_EVT_HW(CPU_CYCLES), PCL_EVT_AHW(CYCLES, CPU_CYCLES), PCL_EVT_AHW(CPU-CYCLES, CPU_CYCLES), PCL_EVT_HW(INSTRUCTIONS), PCL_EVT_AHW(INSTRUCTIONS, INSTRUCTIONS), PCL_EVT_HW(CACHE_REFERENCES), PCL_EVT_AHW(CACHE-REFERENCES, CACHE_REFERENCES), PCL_EVT_HW(CACHE_MISSES), PCL_EVT_AHW(CACHE-MISSES,CACHE_MISSES), PCL_EVT_HW(BRANCH_INSTRUCTIONS), PCL_EVT_AHW(BRANCH-INSTRUCTIONS, BRANCH_INSTRUCTIONS), PCL_EVT_AHW(BRANCHES, BRANCH_INSTRUCTIONS), PCL_EVT_HW(BRANCH_MISSES), PCL_EVT_AHW(BRANCH-MISSES, BRANCH_MISSES), PCL_EVT_HW(BUS_CYCLES), PCL_EVT_AHW(BUS-CYCLES, BUS_CYCLES), PCL_EVT_HW(STALLED_CYCLES_FRONTEND), PCL_EVT_AHW(STALLED-CYCLES-FRONTEND, STALLED_CYCLES_FRONTEND), PCL_EVT_AHW(IDLE-CYCLES-FRONTEND, STALLED_CYCLES_FRONTEND), PCL_EVT_HW(STALLED_CYCLES_BACKEND), PCL_EVT_AHW(STALLED-CYCLES-BACKEND, STALLED_CYCLES_BACKEND), PCL_EVT_AHW(IDLE-CYCLES-BACKEND, STALLED_CYCLES_BACKEND), PCL_EVT_HW(REF_CPU_CYCLES), PCL_EVT_AHW(REF-CYCLES,REF_CPU_CYCLES), PCL_EVT_SW(CPU_CLOCK), PCL_EVT_ASW(CPU-CLOCK, CPU_CLOCK), PCL_EVT_SW(TASK_CLOCK), PCL_EVT_ASW(TASK-CLOCK, TASK_CLOCK), PCL_EVT_SW(PAGE_FAULTS), PCL_EVT_ASW(PAGE-FAULTS, PAGE_FAULTS), PCL_EVT_ASW(FAULTS, PAGE_FAULTS), PCL_EVT_SW(CONTEXT_SWITCHES), PCL_EVT_ASW(CONTEXT-SWITCHES, CONTEXT_SWITCHES), PCL_EVT_ASW(CS, CONTEXT_SWITCHES), PCL_EVT_SW(CPU_MIGRATIONS), PCL_EVT_ASW(CPU-MIGRATIONS, CPU_MIGRATIONS), PCL_EVT_ASW(MIGRATIONS, CPU_MIGRATIONS), PCL_EVT_SW(PAGE_FAULTS_MIN), PCL_EVT_ASW(MINOR-FAULTS, PAGE_FAULTS_MIN), PCL_EVT_SW(PAGE_FAULTS_MAJ), PCL_EVT_ASW(MAJOR-FAULTS, PAGE_FAULTS_MAJ), { .name = "PERF_COUNT_HW_CACHE_L1D", .desc = "L1 data cache", .id = PERF_COUNT_HW_CACHE_L1D, .type = PERF_TYPE_HW_CACHE, .numasks = 5, .modmsk = PERF_ATTR_HW, .umask_ovfl_idx = -1, .ngrp = 2, .umasks = { { .uname = "READ", .udesc = "read access", .uid = PERF_COUNT_HW_CACHE_OP_READ << 8, .uflags= PERF_FL_DEFAULT, .grpid = 0, }, { .uname = "WRITE", .udesc = "write access", .uid = PERF_COUNT_HW_CACHE_OP_WRITE << 8, .grpid = 0, }, { .uname = "PREFETCH", .udesc = "prefetch access", .uid = PERF_COUNT_HW_CACHE_OP_PREFETCH << 8, .grpid = 0, }, { .uname = "ACCESS", .udesc = "hit access", .uid = PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16, .grpid = 1, }, { .uname = "MISS", .udesc = "miss access", .uid = PERF_COUNT_HW_CACHE_RESULT_MISS << 16, .uflags= PERF_FL_DEFAULT, .grpid = 1, } } }, CACHE_ACCESS(L1-DCACHE, "L1 cache", L1D), { .name = "PERF_COUNT_HW_CACHE_L1I", .desc = "L1 instruction cache", .id = PERF_COUNT_HW_CACHE_L1I, .type = PERF_TYPE_HW_CACHE, .numasks = 4, .modmsk = PERF_ATTR_HW, .umask_ovfl_idx = -1, .ngrp = 2, .umasks = { { .uname = "READ", .udesc = "read access", .uid = PERF_COUNT_HW_CACHE_OP_READ << 8, .uflags= PERF_FL_DEFAULT, .grpid = 0, }, { .uname = "PREFETCH", .udesc = "prefetch access", .uid = PERF_COUNT_HW_CACHE_OP_PREFETCH << 8, .grpid = 0, }, { .uname = "ACCESS", .udesc = "hit access", .uid = PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16, .grpid = 1, }, { .uname = "MISS", .udesc = "miss access", .uid = PERF_COUNT_HW_CACHE_RESULT_MISS << 16, .uflags= PERF_FL_DEFAULT, .grpid = 1, } } }, ICACHE_ACCESS(L1-ICACHE, "L1I cache", L1I), { .name = "PERF_COUNT_HW_CACHE_LL", .desc = "Last level cache", .id = PERF_COUNT_HW_CACHE_LL, .type = PERF_TYPE_HW_CACHE, .numasks = 5, .modmsk = PERF_ATTR_HW, .umask_ovfl_idx = -1, .ngrp = 2, .umasks = { { .uname = "READ", .udesc = "read access", .uid = PERF_COUNT_HW_CACHE_OP_READ << 8, .uflags= PERF_FL_DEFAULT, .grpid = 0, }, { .uname = "WRITE", .udesc = "write access", .uid = PERF_COUNT_HW_CACHE_OP_WRITE << 8, .grpid = 0, }, { .uname = "PREFETCH", .udesc = "prefetch access", .uid = PERF_COUNT_HW_CACHE_OP_PREFETCH << 8, .grpid = 0, }, { .uname = "ACCESS", .udesc = "hit access", .uid = PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16, .grpid = 1, }, { .uname = "MISS", .udesc = "miss access", .uid = PERF_COUNT_HW_CACHE_RESULT_MISS << 16, .uflags= PERF_FL_DEFAULT, .grpid = 1, } } }, CACHE_ACCESS(LLC, "Last level cache", LL), { .name = "PERF_COUNT_HW_CACHE_DTLB", .desc = "Data Translation Lookaside Buffer", .id = PERF_COUNT_HW_CACHE_DTLB, .type = PERF_TYPE_HW_CACHE, .numasks = 5, .modmsk = PERF_ATTR_HW, .umask_ovfl_idx = -1, .ngrp = 2, .umasks = { { .uname = "READ", .udesc = "read access", .uid = PERF_COUNT_HW_CACHE_OP_READ << 8, .uflags= PERF_FL_DEFAULT, .grpid = 0, }, { .uname = "WRITE", .udesc = "write access", .uid = PERF_COUNT_HW_CACHE_OP_WRITE << 8, .grpid = 0, }, { .uname = "PREFETCH", .udesc = "prefetch access", .uid = PERF_COUNT_HW_CACHE_OP_PREFETCH << 8, .grpid = 0, }, { .uname = "ACCESS", .udesc = "hit access", .uid = PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16, .grpid = 1, }, { .uname = "MISS", .udesc = "miss access", .uid = PERF_COUNT_HW_CACHE_RESULT_MISS << 16, .uflags= PERF_FL_DEFAULT, .grpid = 1, } } }, CACHE_ACCESS(DTLB, "Data TLB", DTLB), { .name = "PERF_COUNT_HW_CACHE_ITLB", .desc = "Instruction Translation Lookaside Buffer", .id = PERF_COUNT_HW_CACHE_ITLB, .type = PERF_TYPE_HW_CACHE, .numasks = 3, .modmsk = PERF_ATTR_HW, .umask_ovfl_idx = -1, .ngrp = 2, .umasks = { { .uname = "READ", .udesc = "read access", .uid = PERF_COUNT_HW_CACHE_OP_READ << 8, .uflags= PERF_FL_DEFAULT, .grpid = 0, }, { .uname = "ACCESS", .udesc = "hit access", .uid = PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16, .grpid = 1, }, { .uname = "MISS", .udesc = "miss access", .uid = PERF_COUNT_HW_CACHE_RESULT_MISS << 16, .uflags= PERF_FL_DEFAULT, .grpid = 1, } } }, CACHE_LD_ACCESS(ITLB, "Instruction TLB", ITLB), { .name = "PERF_COUNT_HW_CACHE_BPU", .desc = "Branch Prediction Unit", .id = PERF_COUNT_HW_CACHE_BPU, .type = PERF_TYPE_HW_CACHE, .numasks = 3, .modmsk = PERF_ATTR_HW, .umask_ovfl_idx = -1, .ngrp = 2, .umasks = { { .uname = "READ", .udesc = "read access", .uid = PERF_COUNT_HW_CACHE_OP_READ << 8, .uflags= PERF_FL_DEFAULT, .grpid = 0, }, { .uname = "ACCESS", .udesc = "hit access", .uid = PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16, .grpid = 1, }, { .uname = "MISS", .udesc = "miss access", .uid = PERF_COUNT_HW_CACHE_RESULT_MISS << 16, .uflags= PERF_FL_DEFAULT, .grpid = 1, } } }, CACHE_LD_ACCESS(BRANCH, "Branch ", BPU), { .name = "PERF_COUNT_HW_CACHE_NODE", .desc = "Node memory access", .id = PERF_COUNT_HW_CACHE_NODE, .type = PERF_TYPE_HW_CACHE, .numasks = 5, .modmsk = PERF_ATTR_HW, .umask_ovfl_idx = -1, .ngrp = 2, .umasks = { { .uname = "READ", .udesc = "read access", .uid = PERF_COUNT_HW_CACHE_OP_READ << 8, .uflags= PERF_FL_DEFAULT, .grpid = 0, }, { .uname = "WRITE", .udesc = "write access", .uid = PERF_COUNT_HW_CACHE_OP_WRITE << 8, .grpid = 0, }, { .uname = "PREFETCH", .udesc = "prefetch access", .uid = PERF_COUNT_HW_CACHE_OP_PREFETCH << 8, .grpid = 0, }, { .uname = "ACCESS", .udesc = "hit access", .uid = PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16, .grpid = 1, }, { .uname = "MISS", .udesc = "miss access", .uid = PERF_COUNT_HW_CACHE_RESULT_MISS << 16, .uflags= PERF_FL_DEFAULT, .grpid = 1, } }, }, CACHE_ACCESS(NODE, "Node ", NODE) }; #define PME_PERF_EVENT_COUNT (sizeof(perf_static_events)/sizeof(perf_event_t)) libpfm-4.9.0/lib/events/intel_bdx_unc_pcu_events.h0000664000175000017500000004011313223402656022110 0ustar eranianeranian/* * Copyright (c) 2017 Google Inc. All rights reserved * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * PMU: bdx_unc_pcu */ static intel_x86_umask_t bdx_unc_p_power_state_occupancy[]={ { .uname = "CORES_C0", .ucode = 0x4000, .udesc = "Number of cores in C-State -- C0 and C1", }, { .uname = "CORES_C3", .ucode = 0x8000, .udesc = "Number of cores in C-State -- C3", }, { .uname = "CORES_C6", .ucode = 0xc000, .udesc = "Number of cores in C-State -- C6 and C7", }, }; static intel_x86_entry_t intel_bdx_unc_p_pe[]={ { .name = "UNC_P_CLOCKTICKS", .code = 0x0, .desc = "The PCU runs off a fixed 1 GHz clock. This event counts the number of pclk cycles measured while the counter was enabled. The pclk, like the Memory Controllers dclk, counts at a constant rate making it a good measure of actual wall timee.", .modmsk = BDX_UNC_PCU_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_P_CORE0_TRANSITION_CYCLES", .code = 0x60, .desc = "Number of cycles spent performing core C state transitions. There is one event per core.", .modmsk = BDX_UNC_PCU_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_P_CORE10_TRANSITION_CYCLES", .code = 0x6a, .desc = "Number of cycles spent performing core C state transitions. There is one event per core.", .modmsk = BDX_UNC_PCU_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_P_CORE11_TRANSITION_CYCLES", .code = 0x6b, .desc = "Number of cycles spent performing core C state transitions. There is one event per core.", .modmsk = BDX_UNC_PCU_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_P_CORE12_TRANSITION_CYCLES", .code = 0x6c, .desc = "Number of cycles spent performing core C state transitions. There is one event per core.", .modmsk = BDX_UNC_PCU_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_P_CORE13_TRANSITION_CYCLES", .code = 0x6d, .desc = "Number of cycles spent performing core C state transitions. There is one event per core.", .modmsk = BDX_UNC_PCU_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_P_CORE14_TRANSITION_CYCLES", .code = 0x6e, .desc = "Number of cycles spent performing core C state transitions. There is one event per core.", .modmsk = BDX_UNC_PCU_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_P_CORE15_TRANSITION_CYCLES", .code = 0x6f, .desc = "Number of cycles spent performing core C state transitions. There is one event per core.", .modmsk = BDX_UNC_PCU_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_P_CORE16_TRANSITION_CYCLES", .code = 0x70, .desc = "Number of cycles spent performing core C state transitions. There is one event per core.", .modmsk = BDX_UNC_PCU_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_P_CORE17_TRANSITION_CYCLES", .code = 0x71, .desc = "Number of cycles spent performing core C state transitions. There is one event per core.", .modmsk = BDX_UNC_PCU_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_P_CORE1_TRANSITION_CYCLES", .code = 0x61, .desc = "Number of cycles spent performing core C state transitions. There is one event per core.", .modmsk = BDX_UNC_PCU_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_P_CORE2_TRANSITION_CYCLES", .code = 0x62, .desc = "Number of cycles spent performing core C state transitions. There is one event per core.", .modmsk = BDX_UNC_PCU_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_P_CORE3_TRANSITION_CYCLES", .code = 0x63, .desc = "Number of cycles spent performing core C state transitions. There is one event per core.", .modmsk = BDX_UNC_PCU_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_P_CORE4_TRANSITION_CYCLES", .code = 0x64, .desc = "Number of cycles spent performing core C state transitions. There is one event per core.", .modmsk = BDX_UNC_PCU_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_P_CORE5_TRANSITION_CYCLES", .code = 0x65, .desc = "Number of cycles spent performing core C state transitions. There is one event per core.", .modmsk = BDX_UNC_PCU_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_P_CORE6_TRANSITION_CYCLES", .code = 0x66, .desc = "Number of cycles spent performing core C state transitions. There is one event per core.", .modmsk = BDX_UNC_PCU_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_P_CORE7_TRANSITION_CYCLES", .code = 0x67, .desc = "Number of cycles spent performing core C state transitions. There is one event per core.", .modmsk = BDX_UNC_PCU_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_P_CORE8_TRANSITION_CYCLES", .code = 0x68, .desc = "Number of cycles spent performing core C state transitions. There is one event per core.", .modmsk = BDX_UNC_PCU_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_P_CORE9_TRANSITION_CYCLES", .code = 0x69, .desc = "Number of cycles spent performing core C state transitions. There is one event per core.", .modmsk = BDX_UNC_PCU_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_P_DEMOTIONS_CORE0", .code = 0x30, .desc = "Counts the number of times when a configurable cores had a C-state demotion", .modmsk = BDX_UNC_PCU_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_P_DEMOTIONS_CORE1", .code = 0x31, .desc = "Counts the number of times when a configurable cores had a C-state demotion", .modmsk = BDX_UNC_PCU_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_P_DEMOTIONS_CORE10", .code = 0x3a, .desc = "Counts the number of times when a configurable cores had a C-state demotion", .modmsk = BDX_UNC_PCU_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_P_DEMOTIONS_CORE11", .code = 0x3b, .desc = "Counts the number of times when a configurable cores had a C-state demotion", .modmsk = BDX_UNC_PCU_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_P_DEMOTIONS_CORE12", .code = 0x3c, .desc = "Counts the number of times when a configurable cores had a C-state demotion", .modmsk = BDX_UNC_PCU_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_P_DEMOTIONS_CORE13", .code = 0x3d, .desc = "Counts the number of times when a configurable cores had a C-state demotion", .modmsk = BDX_UNC_PCU_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_P_DEMOTIONS_CORE14", .code = 0x3e, .desc = "Counts the number of times when a configurable cores had a C-state demotion", .modmsk = BDX_UNC_PCU_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_P_DEMOTIONS_CORE15", .code = 0x3f, .desc = "Counts the number of times when a configurable cores had a C-state demotion", .modmsk = BDX_UNC_PCU_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_P_DEMOTIONS_CORE16", .code = 0x40, .desc = "Counts the number of times when a configurable cores had a C-state demotion", .modmsk = BDX_UNC_PCU_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_P_DEMOTIONS_CORE17", .code = 0x41, .desc = "Counts the number of times when a configurable cores had a C-state demotion", .modmsk = BDX_UNC_PCU_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_P_DEMOTIONS_CORE2", .code = 0x32, .desc = "Counts the number of times when a configurable cores had a C-state demotion", .modmsk = BDX_UNC_PCU_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_P_DEMOTIONS_CORE3", .code = 0x33, .desc = "Counts the number of times when a configurable cores had a C-state demotion", .modmsk = BDX_UNC_PCU_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_P_DEMOTIONS_CORE4", .code = 0x34, .desc = "Counts the number of times when a configurable cores had a C-state demotion", .modmsk = BDX_UNC_PCU_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_P_DEMOTIONS_CORE5", .code = 0x35, .desc = "Counts the number of times when a configurable cores had a C-state demotion", .modmsk = BDX_UNC_PCU_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_P_DEMOTIONS_CORE6", .code = 0x36, .desc = "Counts the number of times when a configurable cores had a C-state demotion", .modmsk = BDX_UNC_PCU_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_P_DEMOTIONS_CORE7", .code = 0x37, .desc = "Counts the number of times when a configurable cores had a C-state demotion", .modmsk = BDX_UNC_PCU_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_P_DEMOTIONS_CORE8", .code = 0x38, .desc = "Counts the number of times when a configurable cores had a C-state demotion", .modmsk = BDX_UNC_PCU_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_P_DEMOTIONS_CORE9", .code = 0x39, .desc = "Counts the number of times when a configurable cores had a C-state demotion", .modmsk = BDX_UNC_PCU_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES", .code = 0x4, .desc = "Counts the number of cycles when thermal conditions are the upper limit on frequency. This is related to the THERMAL_THROTTLE CYCLES_ABOVE_TEMP event, which always counts cycles when we are above the thermal temperature. This event (STRONGEST_UPPER_LIMIT) is sampled at the output of the algorithm that determines the actual frequency, while THERMAL_THROTTLE looks at the input.", .modmsk = BDX_UNC_PCU_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_P_FREQ_MAX_OS_CYCLES", .code = 0x6, .desc = "Counts the number of cycles when the OS is the upper limit on frequency.", .modmsk = BDX_UNC_PCU_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_P_FREQ_MAX_POWER_CYCLES", .code = 0x5, .desc = "Counts the number of cycles when power is the upper limit on frequency.", .modmsk = BDX_UNC_PCU_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_P_FREQ_MIN_IO_P_CYCLES", .code = 0x73, .desc = "Counts the number of cycles when IO P Limit is preventing us from dropping the frequency lower. This algorithm monitors the needs to the IO subsystem on both local and remote sockets and will maintain a frequency high enough to maintain good IO BW. This is necessary for when all the IA cores on a socket are idle but a user still would like to maintain high IO Bandwidth.", .modmsk = BDX_UNC_PCU_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_P_FREQ_TRANS_CYCLES", .code = 0x74, .desc = "Counts the number of cycles when the system is changing frequency. This can not be filtered by thread ID. One can also use it with the occupancy counter that monitors number of threads in C0 to estimate the performance impact that frequency transitions had on the system.", .modmsk = BDX_UNC_PCU_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES", .code = 0x2f, .desc = "Counts the number of cycles that the PCU has triggered memory phase shedding. This is a mode that can be run in the iMC physicals that saves power at the expense of additional latency.", .modmsk = BDX_UNC_PCU_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_P_POWER_STATE_OCCUPANCY", .code = 0x80, .desc = "This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.", .modmsk = BDX_UNC_PCU_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_p_power_state_occupancy, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_p_power_state_occupancy), }, { .name = "UNC_P_PROCHOT_EXTERNAL_CYCLES", .code = 0xa, .desc = "Counts the number of cycles that we are in external PROCHOT mode. This mode is triggered when a sensor off the die determines that something off-die (like DRAM) is too hot and must throttle to avoid damaging the chip.", .modmsk = BDX_UNC_PCU_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_P_PROCHOT_INTERNAL_CYCLES", .code = 0x9, .desc = "Counts the number of cycles that we are in Interal PROCHOT mode. This mode is triggered when a sensor on the die determines that we are too hot and must throttle to avoid damaging the chip.", .modmsk = BDX_UNC_PCU_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_P_TOTAL_TRANSITION_CYCLES", .code = 0x72, .desc = "Number of cycles spent performing core C state transitions across all cores.", .modmsk = BDX_UNC_PCU_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_P_UFS_BANDWIDTH_MAX_RANGE", .code = 0x7e, .desc = "TBD", .modmsk = BDX_UNC_PCU_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_P_UFS_TRANSITIONS_DOWN", .code = 0x7c, .desc = "Ring GV down due to low traffic", .modmsk = BDX_UNC_PCU_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_P_UFS_TRANSITIONS_IO_P_LIMIT", .code = 0x7d, .desc = "TBD", .modmsk = BDX_UNC_PCU_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_P_UFS_TRANSITIONS_NO_CHANGE", .code = 0x79, .desc = "Ring GV with same final and inital frequency", .modmsk = BDX_UNC_PCU_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_P_UFS_TRANSITIONS_UP_RING", .code = 0x7a, .desc = "Ring GV up due to high ring traffic", .modmsk = BDX_UNC_PCU_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_P_UFS_TRANSITIONS_UP_STALL", .code = 0x7b, .desc = "Ring GV up due to high core stalls", .modmsk = BDX_UNC_PCU_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_P_VR_HOT_CYCLES", .code = 0x42, .desc = "TBD", .modmsk = BDX_UNC_PCU_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_P_FREQ_BAND0_CYCLES", .desc = "Frequency Residency", .code = 0xb, .cntmsk = 0xf, .flags = INTEL_X86_NO_AUTOENCODE, .modmsk = BDX_UNC_PCU_BAND_ATTRS, .modmsk_req = _SNBEP_UNC_ATTR_FF, }, { .name = "UNC_P_FREQ_BAND1_CYCLES", .desc = "Frequency Residency", .code = 0xc, .cntmsk = 0xf, .flags = INTEL_X86_NO_AUTOENCODE, .modmsk = BDX_UNC_PCU_BAND_ATTRS, .modmsk_req = _SNBEP_UNC_ATTR_FF, }, { .name = "UNC_P_FREQ_BAND2_CYCLES", .desc = "Frequency Residency", .code = 0xd, .cntmsk = 0xf, .flags = INTEL_X86_NO_AUTOENCODE, .modmsk = BDX_UNC_PCU_BAND_ATTRS, .modmsk_req = _SNBEP_UNC_ATTR_FF, }, { .name = "UNC_P_FREQ_BAND3_CYCLES", .desc = "Frequency Residency", .code = 0xe, .cntmsk = 0xf, .flags = INTEL_X86_NO_AUTOENCODE, .modmsk = BDX_UNC_PCU_BAND_ATTRS, .modmsk_req = _SNBEP_UNC_ATTR_FF, }, { .name = "UNC_P_FIVR_PS_PS0_CYCLES", .desc = "Cycles spent in phase-shedding power state 0", .code = 0x75, .cntmsk = 0xf, .modmsk = BDX_UNC_PCU_ATTRS, }, { .name = "UNC_P_FIVR_PS_PS1_CYCLES", .desc = "Cycles spent in phase-shedding power state 1", .code = 0x76, .cntmsk = 0xf, .modmsk = BDX_UNC_PCU_ATTRS, }, { .name = "UNC_P_FIVR_PS_PS2_CYCLES", .desc = "Cycles spent in phase-shedding power state 2", .code = 0x77, .cntmsk = 0xf, .modmsk = BDX_UNC_PCU_ATTRS, }, { .name = "UNC_P_FIVR_PS_PS3_CYCLES", .desc = "Cycles spent in phase-shedding power state 3", .code = 0x78, .cntmsk = 0xf, .modmsk = BDX_UNC_PCU_ATTRS, }, }; libpfm-4.9.0/lib/events/intel_snbep_unc_ha_events.h0000664000175000017500000003372713223402656022260 0ustar eranianeranian/* * Copyright (c) 2012 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * This file has been automatically generated. * * PMU: snbep_unc_ha (Intel SandyBridge-EP HA uncore PMU) */ static const intel_x86_umask_t snbep_unc_h_conflict_cycles[]={ { .uname = "CONFLICT", .udesc = "Number of cycles that we are handling conflicts", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "NO_CONFLICT", .udesc = "Number of cycles that we are not handling conflicts", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t snbep_unc_h_directory_lookup[]={ { .uname = "NO_SNP", .udesc = "Snoop not needed", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "SNP", .udesc = "Snoop needed", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t snbep_unc_h_directory_update[]={ { .uname = "ANY", .udesc = "Counts any directory update", .ucode = 0x300, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "CLEAR", .udesc = "Directory clears", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "SET", .udesc = "Directory set", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t snbep_unc_h_igr_no_credit_cycles[]={ { .uname = "AD_QPI0", .udesc = "AD to QPI link 0", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "AD_QPI1", .udesc = "AD to QPI link 1", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "BL_QPI0", .udesc = "BL to QPI link 0", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "BL_QPI1", .udesc = "BL to QPI link 1", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t snbep_unc_h_imc_writes[]={ { .uname = "ALL", .udesc = "Counts all writes", .ucode = 0xf00, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "FULL", .udesc = "Counts full line non ISOCH", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "FULL_ISOCH", .udesc = "Counts ISOCH full line", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "PARTIAL", .udesc = "Counts partial non-ISOCH", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "PARTIAL_ISOCH", .udesc = "Counts ISOCH partial", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t snbep_unc_h_requests[]={ { .uname = "READS", .udesc = "Counts incoming read requests. Good proxy for LLC read misses, incl. RFOs", .ucode = 0x300, .uflags = INTEL_X86_NCOMBO, }, { .uname = "WRITES", .udesc = "Counts incoming writes", .ucode = 0xc00, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t snbep_unc_h_rpq_cycles_no_reg_credits[]={ { .uname = "CHN0", .udesc = "Channel 0", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "CHN1", .udesc = "Channel 1", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "CHN2", .udesc = "channel 2", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "CHN3", .udesc = "Chanell 3", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t snbep_unc_h_tad_requests_g0[]={ { .uname = "REGION0", .udesc = "Counts for TAD Region 0", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "REGION1", .udesc = "Counts for TAD Region 1", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "REGION2", .udesc = "Counts for TAD Region 2", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "REGION3", .udesc = "Counts for TAD Region 3", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "REGION4", .udesc = "Counts for TAD Region 4", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "REGION5", .udesc = "Counts for TAD Region 5", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "REGION6", .udesc = "Counts for TAD Region 6", .ucode = 0x4000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "REGION7", .udesc = "Counts for TAD Region 7", .ucode = 0x8000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t snbep_unc_h_tad_requests_g1[]={ { .uname = "REGION8", .udesc = "Counts for TAD Region 8", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "REGION9", .udesc = "Counts for TAD Region 9", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "REGION10", .udesc = "Counts for TAD Region 10", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "REGION11", .udesc = "Counts for TAD Region 11", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t snbep_unc_h_tracker_inserts[]={ { .uname = "ALL", .udesc = "Counts all requests", .ucode = 0x300, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t snbep_unc_h_txr_ad[]={ { .uname = "NDR", .udesc = "Counts non-data responses", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "SNP", .udesc = "Counts outbound snoops send on the ring", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t snbep_unc_h_txr_ad_cycles_full[]={ { .uname = "ALL", .udesc = "Counts cycles full from both schedulers", .ucode = 0x300, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "SCHED0", .udesc = "Counts cycles full from scheduler bank 0", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "SCHED1", .udesc = "Counts cycles full from scheduler bank 1", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t snbep_unc_h_txr_ak_cycles_full[]={ { .uname = "ALL", .udesc = "Counts cycles from both schedulers", .ucode = 0x300, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "SCHED0", .udesc = "Counts cycles from scheduler bank 0", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "SCHED1", .udesc = "Counts cycles from scheduler bank 1", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t snbep_unc_h_txr_bl[]={ { .uname = "DRS_CACHE", .udesc = "Counts data being sent to the cache", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "DRS_CORE", .udesc = "Counts data being sent directly to the requesting core", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "DRS_QPI", .udesc = "Counts data being sent to a remote socket over QPI", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, }; #if 0 static const intel_x86_umask_t snbep_unc_h_addr_opc_match[]={ { .uname = "FILT", .udesc = "Number of addr and opcode matches (opc via opc= or address via addr= modifiers)", .ucode = 0x300, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL | INTEL_X86_ADDR, }, }; #endif static const intel_x86_entry_t intel_snbep_unc_h_pe[]={ { .name = "UNC_H_CLOCKTICKS", .desc = "HA Uncore clockticks", .modmsk = SNBEP_UNC_HA_ATTRS, .cntmsk = 0xf, .code = 0x00, }, { .name = "UNC_H_CONFLICT_CYCLES", .desc = "Conflict Checks", .code = 0xb, .cntmsk = 0xf, .ngrp = 1, .modmsk = SNBEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_h_conflict_cycles), .umasks = snbep_unc_h_conflict_cycles, }, { .name = "UNC_H_DIRECT2CORE_COUNT", .desc = "Direct2Core Messages Sent", .code = 0x11, .cntmsk = 0xf, .modmsk = SNBEP_UNC_HA_ATTRS, }, { .name = "UNC_H_DIRECT2CORE_CYCLES_DISABLED", .desc = "Cycles when Direct2Core was Disabled", .code = 0x12, .cntmsk = 0xf, .modmsk = SNBEP_UNC_HA_ATTRS, }, { .name = "UNC_H_DIRECT2CORE_TXN_OVERRIDE", .desc = "Number of Reads that had Direct2Core Overridden", .code = 0x13, .cntmsk = 0xf, .modmsk = SNBEP_UNC_HA_ATTRS, }, { .name = "UNC_H_DIRECTORY_LOOKUP", .desc = "Directory Lookups", .code = 0xc, .cntmsk = 0xf, .ngrp = 1, .modmsk = SNBEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_h_directory_lookup), .umasks = snbep_unc_h_directory_lookup }, { .name = "UNC_H_DIRECTORY_UPDATE", .desc = "Directory Updates", .code = 0xd, .cntmsk = 0xf, .ngrp = 1, .modmsk = SNBEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_h_directory_update), .umasks = snbep_unc_h_directory_update }, { .name = "UNC_H_IGR_NO_CREDIT_CYCLES", .desc = "Cycles without QPI Ingress Credits", .code = 0x22, .cntmsk = 0xf, .ngrp = 1, .modmsk = SNBEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_h_igr_no_credit_cycles), .umasks = snbep_unc_h_igr_no_credit_cycles }, { .name = "UNC_H_IMC_RETRY", .desc = "Retry Events", .code = 0x1e, .cntmsk = 0xf, .modmsk = SNBEP_UNC_HA_ATTRS, }, { .name = "UNC_H_IMC_WRITES", .desc = "HA to iMC Full Line Writes Issued", .code = 0x1a, .cntmsk = 0xf, .ngrp = 1, .modmsk = SNBEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_h_imc_writes), .umasks = snbep_unc_h_imc_writes }, { .name = "UNC_H_REQUESTS", .desc = "Read and Write Requests", .code = 0x1, .cntmsk = 0xf, .ngrp = 1, .modmsk = SNBEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_h_requests), .umasks = snbep_unc_h_requests }, { .name = "UNC_H_RPQ_CYCLES_NO_REG_CREDITS", .desc = "iMC RPQ Credits Empty - Regular", .code = 0x15, .cntmsk = 0xf, .ngrp = 1, .modmsk = SNBEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_h_rpq_cycles_no_reg_credits), .umasks = snbep_unc_h_rpq_cycles_no_reg_credits }, { .name = "UNC_H_TAD_REQUESTS_G0", .desc = "HA Requests to a TAD Region - Group 0", .code = 0x1b, .cntmsk = 0xf, .ngrp = 1, .modmsk = SNBEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_h_tad_requests_g0), .umasks = snbep_unc_h_tad_requests_g0 }, { .name = "UNC_H_TAD_REQUESTS_G1", .desc = "HA Requests to a TAD Region - Group 1", .code = 0x1c, .cntmsk = 0xf, .ngrp = 1, .modmsk = SNBEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_h_tad_requests_g1), .umasks = snbep_unc_h_tad_requests_g1 }, { .name = "UNC_H_TRACKER_INSERTS", .desc = "Tracker Allocations", .code = 0x6, .cntmsk = 0xf, .ngrp = 1, .modmsk = SNBEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_h_tracker_inserts), .umasks = snbep_unc_h_tracker_inserts }, { .name = "UNC_H_TXR_AD", .desc = "Outbound NDR Ring Transactions", .code = 0xf, .cntmsk = 0xf, .ngrp = 1, .modmsk = SNBEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_h_txr_ad), .umasks = snbep_unc_h_txr_ad }, { .name = "UNC_H_TXR_AD_CYCLES_FULL", .desc = "AD Egress Full", .code = 0x2a, .cntmsk = 0xf, .ngrp = 1, .modmsk = SNBEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_h_txr_ad_cycles_full), .umasks = snbep_unc_h_txr_ad_cycles_full }, { .name = "UNC_H_TXR_AK_CYCLES_FULL", .desc = "AK Egress Full", .code = 0x32, .cntmsk = 0xf, .ngrp = 1, .modmsk = SNBEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_h_txr_ak_cycles_full), .umasks = snbep_unc_h_txr_ak_cycles_full }, { .name = "UNC_H_TXR_AK_NDR", .desc = "Outbound NDR Ring Transactions", .code = 0xe, .cntmsk = 0xf, .modmsk = SNBEP_UNC_HA_ATTRS, }, { .name = "UNC_H_TXR_BL", .desc = "Outbound DRS Ring Transactions to Cache", .code = 0x10, .cntmsk = 0xf, .ngrp = 1, .modmsk = SNBEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_h_txr_bl), .umasks = snbep_unc_h_txr_bl }, { .name = "UNC_H_TXR_BL_CYCLES_FULL", .desc = "BL Egress Full", .code = 0x36, .cntmsk = 0xf, .ngrp = 1, .modmsk = SNBEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_h_txr_ak_cycles_full), .umasks = snbep_unc_h_txr_ak_cycles_full, /* identical to snbep_unc_h_txr_ak_cycles_full */ }, { .name = "UNC_H_WPQ_CYCLES_NO_REG_CREDITS", .desc = "HA iMC CHN0 WPQ Credits Empty - Regular", .code = 0x18, .cntmsk = 0xf, .ngrp = 1, .modmsk = SNBEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_h_rpq_cycles_no_reg_credits), .umasks = snbep_unc_h_rpq_cycles_no_reg_credits , /* identical to snbep_unc_h_rpq_cycles_no_reg_credits */ }, #if 0 { .name = "UNC_H_ADDR_OPC_MATCH", .desc = "QPI address/opcode match", .code = 0x20, .cntmsk = 0xf, .ngrp = 1, .modmsk = SNBEP_UNC_HA_OPC_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_h_addr_opc_match), .umasks = snbep_unc_h_addr_opc_match, }, #endif }; libpfm-4.9.0/lib/events/power5_events.h0000664000175000017500000053001213223402656017647 0ustar eranianeranian/****************************/ /* THIS IS OPEN SOURCE CODE */ /****************************/ #ifndef __POWER5_EVENTS_H__ #define __POWER5_EVENTS_H__ /* * File: power5_events.h * CVS: * Author: Corey Ashford * cjashfor@us.ibm.com * Mods: * * * (C) Copyright IBM Corporation, 2009. All Rights Reserved. * Contributed by Corey Ashford * * Note: This code was automatically generated and should not be modified by * hand. * */ #define POWER5_PME_PM_LSU_REJECT_RELOAD_CDF 0 #define POWER5_PME_PM_FPU1_SINGLE 1 #define POWER5_PME_PM_L3SB_REF 2 #define POWER5_PME_PM_THRD_PRIO_DIFF_3or4_CYC 3 #define POWER5_PME_PM_INST_FROM_L275_SHR 4 #define POWER5_PME_PM_MRK_DATA_FROM_L375_MOD 5 #define POWER5_PME_PM_DTLB_MISS_4K 6 #define POWER5_PME_PM_CLB_FULL_CYC 7 #define POWER5_PME_PM_MRK_ST_CMPL 8 #define POWER5_PME_PM_LSU_FLUSH_LRQ_FULL 9 #define POWER5_PME_PM_MRK_DATA_FROM_L275_SHR 10 #define POWER5_PME_PM_1INST_CLB_CYC 11 #define POWER5_PME_PM_MEM_SPEC_RD_CANCEL 12 #define POWER5_PME_PM_MRK_DTLB_MISS_16M 13 #define POWER5_PME_PM_FPU_FDIV 14 #define POWER5_PME_PM_FPU_SINGLE 15 #define POWER5_PME_PM_FPU0_FMA 16 #define POWER5_PME_PM_SLB_MISS 17 #define POWER5_PME_PM_LSU1_FLUSH_LRQ 18 #define POWER5_PME_PM_L2SA_ST_HIT 19 #define POWER5_PME_PM_DTLB_MISS 20 #define POWER5_PME_PM_BR_PRED_TA 21 #define POWER5_PME_PM_MRK_DATA_FROM_L375_MOD_CYC 22 #define POWER5_PME_PM_CMPLU_STALL_FXU 23 #define POWER5_PME_PM_EXT_INT 24 #define POWER5_PME_PM_MRK_LSU1_FLUSH_LRQ 25 #define POWER5_PME_PM_LSU1_LDF 26 #define POWER5_PME_PM_MRK_ST_GPS 27 #define POWER5_PME_PM_FAB_CMD_ISSUED 28 #define POWER5_PME_PM_LSU0_SRQ_STFWD 29 #define POWER5_PME_PM_CR_MAP_FULL_CYC 30 #define POWER5_PME_PM_L2SA_RCST_DISP_FAIL_RC_FULL 31 #define POWER5_PME_PM_MRK_LSU0_FLUSH_ULD 32 #define POWER5_PME_PM_LSU_FLUSH_SRQ_FULL 33 #define POWER5_PME_PM_FLUSH_IMBAL 34 #define POWER5_PME_PM_MEM_RQ_DISP_Q16to19 35 #define POWER5_PME_PM_THRD_PRIO_DIFF_minus3or4_CYC 36 #define POWER5_PME_PM_DATA_FROM_L35_MOD 37 #define POWER5_PME_PM_MEM_HI_PRIO_WR_CMPL 38 #define POWER5_PME_PM_FPU1_FDIV 39 #define POWER5_PME_PM_FPU0_FRSP_FCONV 40 #define POWER5_PME_PM_MEM_RQ_DISP 41 #define POWER5_PME_PM_LWSYNC_HELD 42 #define POWER5_PME_PM_FXU_FIN 43 #define POWER5_PME_PM_DSLB_MISS 44 #define POWER5_PME_PM_FXLS1_FULL_CYC 45 #define POWER5_PME_PM_DATA_FROM_L275_SHR 46 #define POWER5_PME_PM_THRD_SEL_T0 47 #define POWER5_PME_PM_PTEG_RELOAD_VALID 48 #define POWER5_PME_PM_LSU_LMQ_LHR_MERGE 49 #define POWER5_PME_PM_MRK_STCX_FAIL 50 #define POWER5_PME_PM_2INST_CLB_CYC 51 #define POWER5_PME_PM_FAB_PNtoVN_DIRECT 52 #define POWER5_PME_PM_PTEG_FROM_L2MISS 53 #define POWER5_PME_PM_CMPLU_STALL_LSU 54 #define POWER5_PME_PM_MRK_DSLB_MISS 55 #define POWER5_PME_PM_LSU_FLUSH_ULD 56 #define POWER5_PME_PM_PTEG_FROM_LMEM 57 #define POWER5_PME_PM_MRK_BRU_FIN 58 #define POWER5_PME_PM_MEM_WQ_DISP_WRITE 59 #define POWER5_PME_PM_MRK_DATA_FROM_L275_MOD_CYC 60 #define POWER5_PME_PM_LSU1_NCLD 61 #define POWER5_PME_PM_L2SA_RCLD_DISP_FAIL_OTHER 62 #define POWER5_PME_PM_SNOOP_PW_RETRY_WQ_PWQ 63 #define POWER5_PME_PM_FPR_MAP_FULL_CYC 64 #define POWER5_PME_PM_FPU1_FULL_CYC 65 #define POWER5_PME_PM_L3SA_ALL_BUSY 66 #define POWER5_PME_PM_3INST_CLB_CYC 67 #define POWER5_PME_PM_MEM_PWQ_DISP_Q2or3 68 #define POWER5_PME_PM_L2SA_SHR_INV 69 #define POWER5_PME_PM_THRESH_TIMEO 70 #define POWER5_PME_PM_L2SA_RC_DISP_FAIL_CO_BUSY_ALL 71 #define POWER5_PME_PM_THRD_SEL_OVER_GCT_IMBAL 72 #define POWER5_PME_PM_FPU_FSQRT 73 #define POWER5_PME_PM_MRK_LSU0_FLUSH_LRQ 74 #define POWER5_PME_PM_PMC1_OVERFLOW 75 #define POWER5_PME_PM_L3SC_SNOOP_RETRY 76 #define POWER5_PME_PM_DATA_TABLEWALK_CYC 77 #define POWER5_PME_PM_THRD_PRIO_6_CYC 78 #define POWER5_PME_PM_FPU_FEST 79 #define POWER5_PME_PM_FAB_M1toP1_SIDECAR_EMPTY 80 #define POWER5_PME_PM_MRK_DATA_FROM_RMEM 81 #define POWER5_PME_PM_MRK_DATA_FROM_L35_MOD_CYC 82 #define POWER5_PME_PM_MEM_PWQ_DISP 83 #define POWER5_PME_PM_FAB_P1toM1_SIDECAR_EMPTY 84 #define POWER5_PME_PM_LD_MISS_L1_LSU0 85 #define POWER5_PME_PM_SNOOP_PARTIAL_RTRY_QFULL 86 #define POWER5_PME_PM_FPU1_STALL3 87 #define POWER5_PME_PM_GCT_USAGE_80to99_CYC 88 #define POWER5_PME_PM_WORK_HELD 89 #define POWER5_PME_PM_INST_CMPL 90 #define POWER5_PME_PM_LSU1_FLUSH_UST 91 #define POWER5_PME_PM_FXU_IDLE 92 #define POWER5_PME_PM_LSU0_FLUSH_ULD 93 #define POWER5_PME_PM_LSU1_REJECT_LMQ_FULL 94 #define POWER5_PME_PM_GRP_DISP_REJECT 95 #define POWER5_PME_PM_L2SA_MOD_INV 96 #define POWER5_PME_PM_PTEG_FROM_L25_SHR 97 #define POWER5_PME_PM_FAB_CMD_RETRIED 98 #define POWER5_PME_PM_L3SA_SHR_INV 99 #define POWER5_PME_PM_L2SB_RC_DISP_FAIL_CO_BUSY_ALL 100 #define POWER5_PME_PM_L2SA_RCST_DISP_FAIL_ADDR 101 #define POWER5_PME_PM_L2SA_RCLD_DISP_FAIL_RC_FULL 102 #define POWER5_PME_PM_PTEG_FROM_L375_MOD 103 #define POWER5_PME_PM_MRK_LSU1_FLUSH_UST 104 #define POWER5_PME_PM_BR_ISSUED 105 #define POWER5_PME_PM_MRK_GRP_BR_REDIR 106 #define POWER5_PME_PM_EE_OFF 107 #define POWER5_PME_PM_MEM_RQ_DISP_Q4to7 108 #define POWER5_PME_PM_MEM_FAST_PATH_RD_DISP 109 #define POWER5_PME_PM_INST_FROM_L3 110 #define POWER5_PME_PM_ITLB_MISS 111 #define POWER5_PME_PM_FXU1_BUSY_FXU0_IDLE 112 #define POWER5_PME_PM_FXLS_FULL_CYC 113 #define POWER5_PME_PM_DTLB_REF_4K 114 #define POWER5_PME_PM_GRP_DISP_VALID 115 #define POWER5_PME_PM_LSU_FLUSH_UST 116 #define POWER5_PME_PM_FXU1_FIN 117 #define POWER5_PME_PM_THRD_PRIO_4_CYC 118 #define POWER5_PME_PM_MRK_DATA_FROM_L35_MOD 119 #define POWER5_PME_PM_4INST_CLB_CYC 120 #define POWER5_PME_PM_MRK_DTLB_REF_16M 121 #define POWER5_PME_PM_INST_FROM_L375_MOD 122 #define POWER5_PME_PM_L2SC_RCST_DISP_FAIL_ADDR 123 #define POWER5_PME_PM_GRP_CMPL 124 #define POWER5_PME_PM_FPU1_1FLOP 125 #define POWER5_PME_PM_FPU_FRSP_FCONV 126 #define POWER5_PME_PM_5INST_CLB_CYC 127 #define POWER5_PME_PM_L3SC_REF 128 #define POWER5_PME_PM_THRD_L2MISS_BOTH_CYC 129 #define POWER5_PME_PM_MEM_PW_GATH 130 #define POWER5_PME_PM_FAB_PNtoNN_SIDECAR 131 #define POWER5_PME_PM_FAB_DCLAIM_ISSUED 132 #define POWER5_PME_PM_GRP_IC_MISS 133 #define POWER5_PME_PM_INST_FROM_L35_SHR 134 #define POWER5_PME_PM_LSU_LMQ_FULL_CYC 135 #define POWER5_PME_PM_MRK_DATA_FROM_L2_CYC 136 #define POWER5_PME_PM_LSU_SRQ_SYNC_CYC 137 #define POWER5_PME_PM_LSU0_BUSY_REJECT 138 #define POWER5_PME_PM_LSU_REJECT_ERAT_MISS 139 #define POWER5_PME_PM_MRK_DATA_FROM_RMEM_CYC 140 #define POWER5_PME_PM_DATA_FROM_L375_SHR 141 #define POWER5_PME_PM_FPU0_FMOV_FEST 142 #define POWER5_PME_PM_PTEG_FROM_L25_MOD 143 #define POWER5_PME_PM_LD_REF_L1_LSU0 144 #define POWER5_PME_PM_THRD_PRIO_7_CYC 145 #define POWER5_PME_PM_LSU1_FLUSH_SRQ 146 #define POWER5_PME_PM_L2SC_RCST_DISP 147 #define POWER5_PME_PM_CMPLU_STALL_DIV 148 #define POWER5_PME_PM_MEM_RQ_DISP_Q12to15 149 #define POWER5_PME_PM_INST_FROM_L375_SHR 150 #define POWER5_PME_PM_ST_REF_L1 151 #define POWER5_PME_PM_L3SB_ALL_BUSY 152 #define POWER5_PME_PM_FAB_P1toVNorNN_SIDECAR_EMPTY 153 #define POWER5_PME_PM_MRK_DATA_FROM_L275_SHR_CYC 154 #define POWER5_PME_PM_FAB_HOLDtoNN_EMPTY 155 #define POWER5_PME_PM_DATA_FROM_LMEM 156 #define POWER5_PME_PM_RUN_CYC 157 #define POWER5_PME_PM_PTEG_FROM_RMEM 158 #define POWER5_PME_PM_L2SC_RCLD_DISP 159 #define POWER5_PME_PM_LSU0_LDF 160 #define POWER5_PME_PM_LSU_LRQ_S0_VALID 161 #define POWER5_PME_PM_PMC3_OVERFLOW 162 #define POWER5_PME_PM_MRK_IMR_RELOAD 163 #define POWER5_PME_PM_MRK_GRP_TIMEO 164 #define POWER5_PME_PM_ST_MISS_L1 165 #define POWER5_PME_PM_STOP_COMPLETION 166 #define POWER5_PME_PM_LSU_BUSY_REJECT 167 #define POWER5_PME_PM_ISLB_MISS 168 #define POWER5_PME_PM_CYC 169 #define POWER5_PME_PM_THRD_ONE_RUN_CYC 170 #define POWER5_PME_PM_GRP_BR_REDIR_NONSPEC 171 #define POWER5_PME_PM_LSU1_SRQ_STFWD 172 #define POWER5_PME_PM_L3SC_MOD_INV 173 #define POWER5_PME_PM_L2_PREF 174 #define POWER5_PME_PM_GCT_NOSLOT_BR_MPRED 175 #define POWER5_PME_PM_MRK_DATA_FROM_L25_MOD 176 #define POWER5_PME_PM_L2SB_MOD_INV 177 #define POWER5_PME_PM_L2SB_ST_REQ 178 #define POWER5_PME_PM_MRK_L1_RELOAD_VALID 179 #define POWER5_PME_PM_L3SB_HIT 180 #define POWER5_PME_PM_L2SB_SHR_MOD 181 #define POWER5_PME_PM_EE_OFF_EXT_INT 182 #define POWER5_PME_PM_1PLUS_PPC_CMPL 183 #define POWER5_PME_PM_L2SC_SHR_MOD 184 #define POWER5_PME_PM_PMC6_OVERFLOW 185 #define POWER5_PME_PM_LSU_LRQ_FULL_CYC 186 #define POWER5_PME_PM_IC_PREF_INSTALL 187 #define POWER5_PME_PM_TLB_MISS 188 #define POWER5_PME_PM_GCT_FULL_CYC 189 #define POWER5_PME_PM_FXU_BUSY 190 #define POWER5_PME_PM_MRK_DATA_FROM_L3_CYC 191 #define POWER5_PME_PM_LSU_REJECT_LMQ_FULL 192 #define POWER5_PME_PM_LSU_SRQ_S0_ALLOC 193 #define POWER5_PME_PM_GRP_MRK 194 #define POWER5_PME_PM_INST_FROM_L25_SHR 195 #define POWER5_PME_PM_FPU1_FIN 196 #define POWER5_PME_PM_DC_PREF_STREAM_ALLOC 197 #define POWER5_PME_PM_BR_MPRED_TA 198 #define POWER5_PME_PM_CRQ_FULL_CYC 199 #define POWER5_PME_PM_L2SA_RCLD_DISP 200 #define POWER5_PME_PM_SNOOP_WR_RETRY_QFULL 201 #define POWER5_PME_PM_MRK_DTLB_REF_4K 202 #define POWER5_PME_PM_LSU_SRQ_S0_VALID 203 #define POWER5_PME_PM_LSU0_FLUSH_LRQ 204 #define POWER5_PME_PM_INST_FROM_L275_MOD 205 #define POWER5_PME_PM_GCT_EMPTY_CYC 206 #define POWER5_PME_PM_LARX_LSU0 207 #define POWER5_PME_PM_THRD_PRIO_DIFF_5or6_CYC 208 #define POWER5_PME_PM_SNOOP_RETRY_1AHEAD 209 #define POWER5_PME_PM_FPU1_FSQRT 210 #define POWER5_PME_PM_MRK_LD_MISS_L1_LSU1 211 #define POWER5_PME_PM_MRK_FPU_FIN 212 #define POWER5_PME_PM_THRD_PRIO_5_CYC 213 #define POWER5_PME_PM_MRK_DATA_FROM_LMEM 214 #define POWER5_PME_PM_FPU1_FRSP_FCONV 215 #define POWER5_PME_PM_SNOOP_TLBIE 216 #define POWER5_PME_PM_L3SB_SNOOP_RETRY 217 #define POWER5_PME_PM_FAB_VBYPASS_EMPTY 218 #define POWER5_PME_PM_MRK_DATA_FROM_L275_MOD 219 #define POWER5_PME_PM_6INST_CLB_CYC 220 #define POWER5_PME_PM_L2SB_RCST_DISP 221 #define POWER5_PME_PM_FLUSH 222 #define POWER5_PME_PM_L2SC_MOD_INV 223 #define POWER5_PME_PM_FPU_DENORM 224 #define POWER5_PME_PM_L3SC_HIT 225 #define POWER5_PME_PM_SNOOP_WR_RETRY_RQ 226 #define POWER5_PME_PM_LSU1_REJECT_SRQ 227 #define POWER5_PME_PM_IC_PREF_REQ 228 #define POWER5_PME_PM_L3SC_ALL_BUSY 229 #define POWER5_PME_PM_MRK_GRP_IC_MISS 230 #define POWER5_PME_PM_GCT_NOSLOT_IC_MISS 231 #define POWER5_PME_PM_MRK_DATA_FROM_L3 232 #define POWER5_PME_PM_GCT_NOSLOT_SRQ_FULL 233 #define POWER5_PME_PM_THRD_SEL_OVER_ISU_HOLD 234 #define POWER5_PME_PM_CMPLU_STALL_DCACHE_MISS 235 #define POWER5_PME_PM_L3SA_MOD_INV 236 #define POWER5_PME_PM_LSU_FLUSH_LRQ 237 #define POWER5_PME_PM_THRD_PRIO_2_CYC 238 #define POWER5_PME_PM_LSU_FLUSH_SRQ 239 #define POWER5_PME_PM_MRK_LSU_SRQ_INST_VALID 240 #define POWER5_PME_PM_L3SA_REF 241 #define POWER5_PME_PM_L2SC_RC_DISP_FAIL_CO_BUSY_ALL 242 #define POWER5_PME_PM_FPU0_STALL3 243 #define POWER5_PME_PM_GPR_MAP_FULL_CYC 244 #define POWER5_PME_PM_TB_BIT_TRANS 245 #define POWER5_PME_PM_MRK_LSU_FLUSH_LRQ 246 #define POWER5_PME_PM_FPU0_STF 247 #define POWER5_PME_PM_MRK_DTLB_MISS 248 #define POWER5_PME_PM_FPU1_FMA 249 #define POWER5_PME_PM_L2SA_MOD_TAG 250 #define POWER5_PME_PM_LSU1_FLUSH_ULD 251 #define POWER5_PME_PM_MRK_LSU0_FLUSH_UST 252 #define POWER5_PME_PM_MRK_INST_FIN 253 #define POWER5_PME_PM_FPU0_FULL_CYC 254 #define POWER5_PME_PM_LSU_LRQ_S0_ALLOC 255 #define POWER5_PME_PM_MRK_LSU1_FLUSH_ULD 256 #define POWER5_PME_PM_MRK_DTLB_REF 257 #define POWER5_PME_PM_BR_UNCOND 258 #define POWER5_PME_PM_THRD_SEL_OVER_L2MISS 259 #define POWER5_PME_PM_L2SB_SHR_INV 260 #define POWER5_PME_PM_MEM_LO_PRIO_WR_CMPL 261 #define POWER5_PME_PM_L3SC_MOD_TAG 262 #define POWER5_PME_PM_MRK_ST_MISS_L1 263 #define POWER5_PME_PM_GRP_DISP_SUCCESS 264 #define POWER5_PME_PM_THRD_PRIO_DIFF_1or2_CYC 265 #define POWER5_PME_PM_IC_DEMAND_L2_BHT_REDIRECT 266 #define POWER5_PME_PM_MEM_WQ_DISP_Q8to15 267 #define POWER5_PME_PM_FPU0_SINGLE 268 #define POWER5_PME_PM_LSU_DERAT_MISS 269 #define POWER5_PME_PM_THRD_PRIO_1_CYC 270 #define POWER5_PME_PM_L2SC_RCST_DISP_FAIL_OTHER 271 #define POWER5_PME_PM_FPU1_FEST 272 #define POWER5_PME_PM_FAB_HOLDtoVN_EMPTY 273 #define POWER5_PME_PM_SNOOP_RD_RETRY_RQ 274 #define POWER5_PME_PM_SNOOP_DCLAIM_RETRY_QFULL 275 #define POWER5_PME_PM_MRK_DATA_FROM_L25_SHR_CYC 276 #define POWER5_PME_PM_MRK_ST_CMPL_INT 277 #define POWER5_PME_PM_FLUSH_BR_MPRED 278 #define POWER5_PME_PM_L2SB_RCLD_DISP_FAIL_ADDR 279 #define POWER5_PME_PM_FPU_STF 280 #define POWER5_PME_PM_CMPLU_STALL_FPU 281 #define POWER5_PME_PM_THRD_PRIO_DIFF_minus1or2_CYC 282 #define POWER5_PME_PM_GCT_NOSLOT_CYC 283 #define POWER5_PME_PM_FXU0_BUSY_FXU1_IDLE 284 #define POWER5_PME_PM_PTEG_FROM_L35_SHR 285 #define POWER5_PME_PM_MRK_LSU_FLUSH_UST 286 #define POWER5_PME_PM_L3SA_HIT 287 #define POWER5_PME_PM_MRK_DATA_FROM_L25_SHR 288 #define POWER5_PME_PM_L2SB_RCST_DISP_FAIL_ADDR 289 #define POWER5_PME_PM_MRK_DATA_FROM_L35_SHR 290 #define POWER5_PME_PM_IERAT_XLATE_WR 291 #define POWER5_PME_PM_L2SA_ST_REQ 292 #define POWER5_PME_PM_THRD_SEL_T1 293 #define POWER5_PME_PM_IC_DEMAND_L2_BR_REDIRECT 294 #define POWER5_PME_PM_INST_FROM_LMEM 295 #define POWER5_PME_PM_FPU0_1FLOP 296 #define POWER5_PME_PM_MRK_DATA_FROM_L35_SHR_CYC 297 #define POWER5_PME_PM_PTEG_FROM_L2 298 #define POWER5_PME_PM_MEM_PW_CMPL 299 #define POWER5_PME_PM_THRD_PRIO_DIFF_minus5or6_CYC 300 #define POWER5_PME_PM_L2SB_RCLD_DISP_FAIL_OTHER 301 #define POWER5_PME_PM_FPU0_FIN 302 #define POWER5_PME_PM_MRK_DTLB_MISS_4K 303 #define POWER5_PME_PM_L3SC_SHR_INV 304 #define POWER5_PME_PM_GRP_BR_REDIR 305 #define POWER5_PME_PM_L2SC_RCLD_DISP_FAIL_RC_FULL 306 #define POWER5_PME_PM_MRK_LSU_FLUSH_SRQ 307 #define POWER5_PME_PM_PTEG_FROM_L275_SHR 308 #define POWER5_PME_PM_L2SB_RCLD_DISP_FAIL_RC_FULL 309 #define POWER5_PME_PM_SNOOP_RD_RETRY_WQ 310 #define POWER5_PME_PM_LSU0_NCLD 311 #define POWER5_PME_PM_FAB_DCLAIM_RETRIED 312 #define POWER5_PME_PM_LSU1_BUSY_REJECT 313 #define POWER5_PME_PM_FXLS0_FULL_CYC 314 #define POWER5_PME_PM_FPU0_FEST 315 #define POWER5_PME_PM_DTLB_REF_16M 316 #define POWER5_PME_PM_L2SC_RCLD_DISP_FAIL_ADDR 317 #define POWER5_PME_PM_LSU0_REJECT_ERAT_MISS 318 #define POWER5_PME_PM_DATA_FROM_L25_MOD 319 #define POWER5_PME_PM_GCT_USAGE_60to79_CYC 320 #define POWER5_PME_PM_DATA_FROM_L375_MOD 321 #define POWER5_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC 322 #define POWER5_PME_PM_LSU0_REJECT_RELOAD_CDF 323 #define POWER5_PME_PM_0INST_FETCH 324 #define POWER5_PME_PM_LSU1_REJECT_RELOAD_CDF 325 #define POWER5_PME_PM_L1_PREF 326 #define POWER5_PME_PM_MEM_WQ_DISP_Q0to7 327 #define POWER5_PME_PM_MRK_DATA_FROM_LMEM_CYC 328 #define POWER5_PME_PM_BRQ_FULL_CYC 329 #define POWER5_PME_PM_GRP_IC_MISS_NONSPEC 330 #define POWER5_PME_PM_PTEG_FROM_L275_MOD 331 #define POWER5_PME_PM_MRK_LD_MISS_L1_LSU0 332 #define POWER5_PME_PM_MRK_DATA_FROM_L375_SHR_CYC 333 #define POWER5_PME_PM_LSU_FLUSH 334 #define POWER5_PME_PM_DATA_FROM_L3 335 #define POWER5_PME_PM_INST_FROM_L2 336 #define POWER5_PME_PM_PMC2_OVERFLOW 337 #define POWER5_PME_PM_FPU0_DENORM 338 #define POWER5_PME_PM_FPU1_FMOV_FEST 339 #define POWER5_PME_PM_INST_FETCH_CYC 340 #define POWER5_PME_PM_LSU_LDF 341 #define POWER5_PME_PM_INST_DISP 342 #define POWER5_PME_PM_DATA_FROM_L25_SHR 343 #define POWER5_PME_PM_L1_DCACHE_RELOAD_VALID 344 #define POWER5_PME_PM_MEM_WQ_DISP_DCLAIM 345 #define POWER5_PME_PM_FPU_FULL_CYC 346 #define POWER5_PME_PM_MRK_GRP_ISSUED 347 #define POWER5_PME_PM_THRD_PRIO_3_CYC 348 #define POWER5_PME_PM_FPU_FMA 349 #define POWER5_PME_PM_INST_FROM_L35_MOD 350 #define POWER5_PME_PM_MRK_CRU_FIN 351 #define POWER5_PME_PM_SNOOP_WR_RETRY_WQ 352 #define POWER5_PME_PM_CMPLU_STALL_REJECT 353 #define POWER5_PME_PM_LSU1_REJECT_ERAT_MISS 354 #define POWER5_PME_PM_MRK_FXU_FIN 355 #define POWER5_PME_PM_L2SB_RCST_DISP_FAIL_OTHER 356 #define POWER5_PME_PM_L2SC_RC_DISP_FAIL_CO_BUSY 357 #define POWER5_PME_PM_PMC4_OVERFLOW 358 #define POWER5_PME_PM_L3SA_SNOOP_RETRY 359 #define POWER5_PME_PM_PTEG_FROM_L35_MOD 360 #define POWER5_PME_PM_INST_FROM_L25_MOD 361 #define POWER5_PME_PM_THRD_SMT_HANG 362 #define POWER5_PME_PM_CMPLU_STALL_ERAT_MISS 363 #define POWER5_PME_PM_L3SA_MOD_TAG 364 #define POWER5_PME_PM_FLUSH_SYNC 365 #define POWER5_PME_PM_INST_FROM_L2MISS 366 #define POWER5_PME_PM_L2SC_ST_HIT 367 #define POWER5_PME_PM_MEM_RQ_DISP_Q8to11 368 #define POWER5_PME_PM_MRK_GRP_DISP 369 #define POWER5_PME_PM_L2SB_MOD_TAG 370 #define POWER5_PME_PM_CLB_EMPTY_CYC 371 #define POWER5_PME_PM_L2SB_ST_HIT 372 #define POWER5_PME_PM_MEM_NONSPEC_RD_CANCEL 373 #define POWER5_PME_PM_BR_PRED_CR_TA 374 #define POWER5_PME_PM_MRK_LSU0_FLUSH_SRQ 375 #define POWER5_PME_PM_MRK_LSU_FLUSH_ULD 376 #define POWER5_PME_PM_INST_DISP_ATTEMPT 377 #define POWER5_PME_PM_INST_FROM_RMEM 378 #define POWER5_PME_PM_ST_REF_L1_LSU0 379 #define POWER5_PME_PM_LSU0_DERAT_MISS 380 #define POWER5_PME_PM_L2SB_RCLD_DISP 381 #define POWER5_PME_PM_FPU_STALL3 382 #define POWER5_PME_PM_BR_PRED_CR 383 #define POWER5_PME_PM_MRK_DATA_FROM_L2 384 #define POWER5_PME_PM_LSU0_FLUSH_SRQ 385 #define POWER5_PME_PM_FAB_PNtoNN_DIRECT 386 #define POWER5_PME_PM_IOPS_CMPL 387 #define POWER5_PME_PM_L2SC_SHR_INV 388 #define POWER5_PME_PM_L2SA_RCST_DISP_FAIL_OTHER 389 #define POWER5_PME_PM_L2SA_RCST_DISP 390 #define POWER5_PME_PM_SNOOP_RETRY_AB_COLLISION 391 #define POWER5_PME_PM_FAB_PNtoVN_SIDECAR 392 #define POWER5_PME_PM_LSU_LMQ_S0_ALLOC 393 #define POWER5_PME_PM_LSU0_REJECT_LMQ_FULL 394 #define POWER5_PME_PM_SNOOP_PW_RETRY_RQ 395 #define POWER5_PME_PM_DTLB_REF 396 #define POWER5_PME_PM_PTEG_FROM_L3 397 #define POWER5_PME_PM_FAB_M1toVNorNN_SIDECAR_EMPTY 398 #define POWER5_PME_PM_LSU_SRQ_EMPTY_CYC 399 #define POWER5_PME_PM_FPU1_STF 400 #define POWER5_PME_PM_LSU_LMQ_S0_VALID 401 #define POWER5_PME_PM_GCT_USAGE_00to59_CYC 402 #define POWER5_PME_PM_DATA_FROM_L2MISS 403 #define POWER5_PME_PM_GRP_DISP_BLK_SB_CYC 404 #define POWER5_PME_PM_FPU_FMOV_FEST 405 #define POWER5_PME_PM_XER_MAP_FULL_CYC 406 #define POWER5_PME_PM_FLUSH_SB 407 #define POWER5_PME_PM_MRK_DATA_FROM_L375_SHR 408 #define POWER5_PME_PM_MRK_GRP_CMPL 409 #define POWER5_PME_PM_SUSPENDED 410 #define POWER5_PME_PM_GRP_IC_MISS_BR_REDIR_NONSPEC 411 #define POWER5_PME_PM_SNOOP_RD_RETRY_QFULL 412 #define POWER5_PME_PM_L3SB_MOD_INV 413 #define POWER5_PME_PM_DATA_FROM_L35_SHR 414 #define POWER5_PME_PM_LD_MISS_L1_LSU1 415 #define POWER5_PME_PM_STCX_FAIL 416 #define POWER5_PME_PM_DC_PREF_DST 417 #define POWER5_PME_PM_GRP_DISP 418 #define POWER5_PME_PM_L2SA_RCLD_DISP_FAIL_ADDR 419 #define POWER5_PME_PM_FPU0_FPSCR 420 #define POWER5_PME_PM_DATA_FROM_L2 421 #define POWER5_PME_PM_FPU1_DENORM 422 #define POWER5_PME_PM_FPU_1FLOP 423 #define POWER5_PME_PM_L2SC_RCLD_DISP_FAIL_OTHER 424 #define POWER5_PME_PM_L2SC_RCST_DISP_FAIL_RC_FULL 425 #define POWER5_PME_PM_FPU0_FSQRT 426 #define POWER5_PME_PM_LD_REF_L1 427 #define POWER5_PME_PM_INST_FROM_L1 428 #define POWER5_PME_PM_TLBIE_HELD 429 #define POWER5_PME_PM_DC_PREF_OUT_OF_STREAMS 430 #define POWER5_PME_PM_MRK_DATA_FROM_L25_MOD_CYC 431 #define POWER5_PME_PM_MRK_LSU1_FLUSH_SRQ 432 #define POWER5_PME_PM_MEM_RQ_DISP_Q0to3 433 #define POWER5_PME_PM_ST_REF_L1_LSU1 434 #define POWER5_PME_PM_MRK_LD_MISS_L1 435 #define POWER5_PME_PM_L1_WRITE_CYC 436 #define POWER5_PME_PM_L2SC_ST_REQ 437 #define POWER5_PME_PM_CMPLU_STALL_FDIV 438 #define POWER5_PME_PM_THRD_SEL_OVER_CLB_EMPTY 439 #define POWER5_PME_PM_BR_MPRED_CR 440 #define POWER5_PME_PM_L3SB_MOD_TAG 441 #define POWER5_PME_PM_MRK_DATA_FROM_L2MISS 442 #define POWER5_PME_PM_LSU_REJECT_SRQ 443 #define POWER5_PME_PM_LD_MISS_L1 444 #define POWER5_PME_PM_INST_FROM_PREF 445 #define POWER5_PME_PM_DC_INV_L2 446 #define POWER5_PME_PM_STCX_PASS 447 #define POWER5_PME_PM_LSU_SRQ_FULL_CYC 448 #define POWER5_PME_PM_FPU_FIN 449 #define POWER5_PME_PM_L2SA_SHR_MOD 450 #define POWER5_PME_PM_LSU_SRQ_STFWD 451 #define POWER5_PME_PM_0INST_CLB_CYC 452 #define POWER5_PME_PM_FXU0_FIN 453 #define POWER5_PME_PM_L2SB_RCST_DISP_FAIL_RC_FULL 454 #define POWER5_PME_PM_THRD_GRP_CMPL_BOTH_CYC 455 #define POWER5_PME_PM_PMC5_OVERFLOW 456 #define POWER5_PME_PM_FPU0_FDIV 457 #define POWER5_PME_PM_PTEG_FROM_L375_SHR 458 #define POWER5_PME_PM_LD_REF_L1_LSU1 459 #define POWER5_PME_PM_L2SA_RC_DISP_FAIL_CO_BUSY 460 #define POWER5_PME_PM_HV_CYC 461 #define POWER5_PME_PM_THRD_PRIO_DIFF_0_CYC 462 #define POWER5_PME_PM_LR_CTR_MAP_FULL_CYC 463 #define POWER5_PME_PM_L3SB_SHR_INV 464 #define POWER5_PME_PM_DATA_FROM_RMEM 465 #define POWER5_PME_PM_DATA_FROM_L275_MOD 466 #define POWER5_PME_PM_LSU0_REJECT_SRQ 467 #define POWER5_PME_PM_LSU1_DERAT_MISS 468 #define POWER5_PME_PM_MRK_LSU_FIN 469 #define POWER5_PME_PM_DTLB_MISS_16M 470 #define POWER5_PME_PM_LSU0_FLUSH_UST 471 #define POWER5_PME_PM_L2SC_MOD_TAG 472 #define POWER5_PME_PM_L2SB_RC_DISP_FAIL_CO_BUSY 473 static const pme_power_entry_t power5_pe[] = { [ POWER5_PME_PM_LSU_REJECT_RELOAD_CDF ] = { .pme_name = "PM_LSU_REJECT_RELOAD_CDF", .pme_code = 0x2c6090, .pme_short_desc = "LSU reject due to reload CDF or tag update collision", .pme_long_desc = "Total cycles the Load Store Unit is busy rejecting instructions because of Critical Data Forward. When critical data arrives from the storage system it is formatted and immediately forwarded, bypassing the data cache, to the destination register using the result bus. Any instruction the requires the result bus in the same cycle is rejected. Tag update rejects are caused when an instruction requires access to the Dcache directory or ERAT in the same system when they are being updated. Combined Unit 0 + 1.", }, [ POWER5_PME_PM_FPU1_SINGLE ] = { .pme_name = "PM_FPU1_SINGLE", .pme_code = 0x20e7, .pme_short_desc = "FPU1 executed single precision instruction", .pme_long_desc = "FPU1 has executed a single precision instruction.", }, [ POWER5_PME_PM_L3SB_REF ] = { .pme_name = "PM_L3SB_REF", .pme_code = 0x701c4, .pme_short_desc = "L3 slice B references", .pme_long_desc = "Number of attempts made by this chip cores to find data in the L3. Reported per L3 slice ", }, [ POWER5_PME_PM_THRD_PRIO_DIFF_3or4_CYC ] = { .pme_name = "PM_THRD_PRIO_DIFF_3or4_CYC", .pme_code = 0x430e5, .pme_short_desc = "Cycles thread priority difference is 3 or 4", .pme_long_desc = "Cycles when this thread's priority is higher than the other thread's priority by 3 or 4.", }, [ POWER5_PME_PM_INST_FROM_L275_SHR ] = { .pme_name = "PM_INST_FROM_L275_SHR", .pme_code = 0x322096, .pme_short_desc = "Instruction fetched from L2.75 shared", .pme_long_desc = "An instruction fetch group was fetched with shared (T) data from the L2 on a different module than this processor is located. Fetch groups can contain up to 8 instructions", }, [ POWER5_PME_PM_MRK_DATA_FROM_L375_MOD ] = { .pme_name = "PM_MRK_DATA_FROM_L375_MOD", .pme_code = 0x1c70a7, .pme_short_desc = "Marked data loaded from L3.75 modified", .pme_long_desc = "The processor's Data Cache was reloaded with modified (M) data from the L3 of a chip on a different module than this processor is located due to a marked load.", }, [ POWER5_PME_PM_DTLB_MISS_4K ] = { .pme_name = "PM_DTLB_MISS_4K", .pme_code = 0xc40c0, .pme_short_desc = "Data TLB miss for 4K page", .pme_long_desc = "Data TLB references to 4KB pages that missed the TLB. Page size is determined at TLB reload time.", }, [ POWER5_PME_PM_CLB_FULL_CYC ] = { .pme_name = "PM_CLB_FULL_CYC", .pme_code = 0x220e5, .pme_short_desc = "Cycles CLB full", .pme_long_desc = "Cycles when both thread's CLB is full.", }, [ POWER5_PME_PM_MRK_ST_CMPL ] = { .pme_name = "PM_MRK_ST_CMPL", .pme_code = 0x100003, .pme_short_desc = "Marked store instruction completed", .pme_long_desc = "A sampled store has completed (data home)", }, [ POWER5_PME_PM_LSU_FLUSH_LRQ_FULL ] = { .pme_name = "PM_LSU_FLUSH_LRQ_FULL", .pme_code = 0x320e7, .pme_short_desc = "Flush caused by LRQ full", .pme_long_desc = "This thread was flushed at dispatch because its Load Request Queue was full. This allows the other thread to have more machine resources for it to make progress while this thread is stalled.", }, [ POWER5_PME_PM_MRK_DATA_FROM_L275_SHR ] = { .pme_name = "PM_MRK_DATA_FROM_L275_SHR", .pme_code = 0x3c7097, .pme_short_desc = "Marked data loaded from L2.75 shared", .pme_long_desc = "The processor's Data Cache was reloaded with shared (T) data from the L2 on a different module than this processor is located due to a marked load.", }, [ POWER5_PME_PM_1INST_CLB_CYC ] = { .pme_name = "PM_1INST_CLB_CYC", .pme_code = 0x400c1, .pme_short_desc = "Cycles 1 instruction in CLB", .pme_long_desc = "The cache line buffer (CLB) is a 6-deep, 4-wide instruction buffer. Fullness is reported on a cycle basis with each event representing the number of cycles the CLB had the corresponding number of entries occupied. These events give a real time history of the number of instruction buffers used, but not the number of PowerPC instructions within those buffers. Each thread has its own set of CLB; these events are thread specific.", }, [ POWER5_PME_PM_MEM_SPEC_RD_CANCEL ] = { .pme_name = "PM_MEM_SPEC_RD_CANCEL", .pme_code = 0x721e6, .pme_short_desc = "Speculative memory read cancelled", .pme_long_desc = "Speculative memory read cancelled (i.e. cresp = sourced by L2/L3)", }, [ POWER5_PME_PM_MRK_DTLB_MISS_16M ] = { .pme_name = "PM_MRK_DTLB_MISS_16M", .pme_code = 0xc40c5, .pme_short_desc = "Marked Data TLB misses for 16M page", .pme_long_desc = "Marked Data TLB misses for 16M page", }, [ POWER5_PME_PM_FPU_FDIV ] = { .pme_name = "PM_FPU_FDIV", .pme_code = 0x100088, .pme_short_desc = "FPU executed FDIV instruction", .pme_long_desc = "The floating point unit has executed a divide instruction. This could be fdiv, fdivs, fdiv., fdivs.. Combined Unit 0 + Unit 1.", }, [ POWER5_PME_PM_FPU_SINGLE ] = { .pme_name = "PM_FPU_SINGLE", .pme_code = 0x102090, .pme_short_desc = "FPU executed single precision instruction", .pme_long_desc = "FPU is executing single precision instruction. Combined Unit 0 + Unit 1.", }, [ POWER5_PME_PM_FPU0_FMA ] = { .pme_name = "PM_FPU0_FMA", .pme_code = 0xc1, .pme_short_desc = "FPU0 executed multiply-add instruction", .pme_long_desc = "The floating point unit has executed a multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs.", }, [ POWER5_PME_PM_SLB_MISS ] = { .pme_name = "PM_SLB_MISS", .pme_code = 0x280088, .pme_short_desc = "SLB misses", .pme_long_desc = "Total of all Segment Lookaside Buffer (SLB) misses, Instructions + Data.", }, [ POWER5_PME_PM_LSU1_FLUSH_LRQ ] = { .pme_name = "PM_LSU1_FLUSH_LRQ", .pme_code = 0xc00c6, .pme_short_desc = "LSU1 LRQ flushes", .pme_long_desc = "A load was flushed by unit 1 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.", }, [ POWER5_PME_PM_L2SA_ST_HIT ] = { .pme_name = "PM_L2SA_ST_HIT", .pme_code = 0x733e0, .pme_short_desc = "L2 slice A store hits", .pme_long_desc = "A store request made from the core hit in the L2 directory. This event is provided on each of the three L2 slices A, B, and C.", }, [ POWER5_PME_PM_DTLB_MISS ] = { .pme_name = "PM_DTLB_MISS", .pme_code = 0x800c4, .pme_short_desc = "Data TLB misses", .pme_long_desc = "Data TLB misses, all page sizes.", }, [ POWER5_PME_PM_BR_PRED_TA ] = { .pme_name = "PM_BR_PRED_TA", .pme_code = 0x230e3, .pme_short_desc = "A conditional branch was predicted, target prediction", .pme_long_desc = "The target address of a branch instruction was predicted.", }, [ POWER5_PME_PM_MRK_DATA_FROM_L375_MOD_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L375_MOD_CYC", .pme_code = 0x4c70a7, .pme_short_desc = "Marked load latency from L3.75 modified", .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.", }, [ POWER5_PME_PM_CMPLU_STALL_FXU ] = { .pme_name = "PM_CMPLU_STALL_FXU", .pme_code = 0x211099, .pme_short_desc = "Completion stall caused by FXU instruction", .pme_long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes was a fixed point instruction.", }, [ POWER5_PME_PM_EXT_INT ] = { .pme_name = "PM_EXT_INT", .pme_code = 0x400003, .pme_short_desc = "External interrupts", .pme_long_desc = "An interrupt due to an external exception occurred", }, [ POWER5_PME_PM_MRK_LSU1_FLUSH_LRQ ] = { .pme_name = "PM_MRK_LSU1_FLUSH_LRQ", .pme_code = 0x810c6, .pme_short_desc = "LSU1 marked LRQ flushes", .pme_long_desc = "A marked load was flushed by unit 1 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.", }, [ POWER5_PME_PM_LSU1_LDF ] = { .pme_name = "PM_LSU1_LDF", .pme_code = 0xc50c4, .pme_short_desc = "LSU1 executed Floating Point load instruction", .pme_long_desc = "A floating point load was executed by LSU1", }, [ POWER5_PME_PM_MRK_ST_GPS ] = { .pme_name = "PM_MRK_ST_GPS", .pme_code = 0x200003, .pme_short_desc = "Marked store sent to GPS", .pme_long_desc = "A sampled store has been sent to the memory subsystem", }, [ POWER5_PME_PM_FAB_CMD_ISSUED ] = { .pme_name = "PM_FAB_CMD_ISSUED", .pme_code = 0x700c7, .pme_short_desc = "Fabric command issued", .pme_long_desc = "Incremented when a chip issues a command on its SnoopA address bus. Each of the two address busses (SnoopA and SnoopB) is capable of one transaction per fabric cycle (one fabric cycle = 2 cpu cycles in normal 2:1 mode), but each chip can only drive the SnoopA bus, and can only drive one transaction every two fabric cycles (i.e., every four cpu cycles). In MCM-based systems, two chips interleave their accesses to each of the two fabric busses (SnoopA, SnoopB) to reach a peak capability of one transaction per cpu clock cycle. The two chips that drive SnoopB are wired so that the chips refer to the bus as SnoopA but it is connected to the other two chips as SnoopB. Note that this event will only be recorded by the FBC on the chip that sourced the operation. The signal is delivered at FBC speed and the count must be scaled.", }, [ POWER5_PME_PM_LSU0_SRQ_STFWD ] = { .pme_name = "PM_LSU0_SRQ_STFWD", .pme_code = 0xc20e0, .pme_short_desc = "LSU0 SRQ store forwarded", .pme_long_desc = "Data from a store instruction was forwarded to a load on unit 0. A load that misses L1 but becomes a store forward is treated as a load miss and it causes the DL1 load miss event to be counted. It does not go into the LMQ. If a load that hits L1 but becomes a store forward, then it's not treated as a load miss.", }, [ POWER5_PME_PM_CR_MAP_FULL_CYC ] = { .pme_name = "PM_CR_MAP_FULL_CYC", .pme_code = 0x100c4, .pme_short_desc = "Cycles CR logical operation mapper full", .pme_long_desc = "The Conditional Register mapper cannot accept any more groups. This condition will prevent dispatch groups from being dispatched. This event only indicates that the mapper was full, not that dispatch was prevented.", }, [ POWER5_PME_PM_L2SA_RCST_DISP_FAIL_RC_FULL ] = { .pme_name = "PM_L2SA_RCST_DISP_FAIL_RC_FULL", .pme_code = 0x722e0, .pme_short_desc = "L2 slice A RC store dispatch attempt failed due to all RC full", .pme_long_desc = "A Read/Claim dispatch for a store failed because all RC machines are busy.", }, [ POWER5_PME_PM_MRK_LSU0_FLUSH_ULD ] = { .pme_name = "PM_MRK_LSU0_FLUSH_ULD", .pme_code = 0x810c0, .pme_short_desc = "LSU0 marked unaligned load flushes", .pme_long_desc = "A marked load was flushed from unit 0 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)", }, [ POWER5_PME_PM_LSU_FLUSH_SRQ_FULL ] = { .pme_name = "PM_LSU_FLUSH_SRQ_FULL", .pme_code = 0x330e0, .pme_short_desc = "Flush caused by SRQ full", .pme_long_desc = "This thread was flushed at dispatch because its Store Request Queue was full. This allows the other thread to have more machine resources for it to make progress while this thread is stalled.", }, [ POWER5_PME_PM_FLUSH_IMBAL ] = { .pme_name = "PM_FLUSH_IMBAL", .pme_code = 0x330e3, .pme_short_desc = "Flush caused by thread GCT imbalance", .pme_long_desc = "This thread has been flushed at dispatch because it is stalled and a GCT imbalance exists. GCT thresholds are set in the TSCR register. This allows the other thread to have more machine resources for it to make progress while this thread is stalled.", }, [ POWER5_PME_PM_MEM_RQ_DISP_Q16to19 ] = { .pme_name = "PM_MEM_RQ_DISP_Q16to19", .pme_code = 0x727e6, .pme_short_desc = "Memory read queue dispatched to queues 16-19", .pme_long_desc = "A memory operation was dispatched to read queue 16,17,18 or 19. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", }, [ POWER5_PME_PM_THRD_PRIO_DIFF_minus3or4_CYC ] = { .pme_name = "PM_THRD_PRIO_DIFF_minus3or4_CYC", .pme_code = 0x430e1, .pme_short_desc = "Cycles thread priority difference is -3 or -4", .pme_long_desc = "Cycles when this thread's priority is lower than the other thread's priority by 3 or 4.", }, [ POWER5_PME_PM_DATA_FROM_L35_MOD ] = { .pme_name = "PM_DATA_FROM_L35_MOD", .pme_code = 0x2c309e, .pme_short_desc = "Data loaded from L3.5 modified", .pme_long_desc = "The processor's Data Cache was reloaded with modified (M) data from the L3 of a chip on the same module as this processor is located due to a demand load.", }, [ POWER5_PME_PM_MEM_HI_PRIO_WR_CMPL ] = { .pme_name = "PM_MEM_HI_PRIO_WR_CMPL", .pme_code = 0x726e6, .pme_short_desc = "High priority write completed", .pme_long_desc = "A memory write, which was upgraded to high priority, completed. Writes can be upgraded to high priority to ensure that read traffic does not lock out writes. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", }, [ POWER5_PME_PM_FPU1_FDIV ] = { .pme_name = "PM_FPU1_FDIV", .pme_code = 0xc4, .pme_short_desc = "FPU1 executed FDIV instruction", .pme_long_desc = "FPU1 has executed a divide instruction. This could be fdiv, fdivs, fdiv. fdivs.", }, [ POWER5_PME_PM_FPU0_FRSP_FCONV ] = { .pme_name = "PM_FPU0_FRSP_FCONV", .pme_code = 0x10c1, .pme_short_desc = "FPU0 executed FRSP or FCONV instructions", .pme_long_desc = "FPU0 has executed a frsp or convert kind of instruction. This could be frsp*, fcfid*, fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs.", }, [ POWER5_PME_PM_MEM_RQ_DISP ] = { .pme_name = "PM_MEM_RQ_DISP", .pme_code = 0x701c6, .pme_short_desc = "Memory read queue dispatched", .pme_long_desc = "A memory read was dispatched. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", }, [ POWER5_PME_PM_LWSYNC_HELD ] = { .pme_name = "PM_LWSYNC_HELD", .pme_code = 0x130e0, .pme_short_desc = "LWSYNC held at dispatch", .pme_long_desc = "Cycles a LWSYNC instruction was held at dispatch. LWSYNC instructions are held at dispatch until all previous loads are done and all previous stores have issued. LWSYNC enters the Store Request Queue and is sent to the storage subsystem but does not wait for a response.", }, [ POWER5_PME_PM_FXU_FIN ] = { .pme_name = "PM_FXU_FIN", .pme_code = 0x313088, .pme_short_desc = "FXU produced a result", .pme_long_desc = "The fixed point unit (Unit 0 + Unit 1) finished an instruction. Instructions that finish may not necessary complete.", }, [ POWER5_PME_PM_DSLB_MISS ] = { .pme_name = "PM_DSLB_MISS", .pme_code = 0x800c5, .pme_short_desc = "Data SLB misses", .pme_long_desc = "A SLB miss for a data request occurred. SLB misses trap to the operating system to resolve.", }, [ POWER5_PME_PM_FXLS1_FULL_CYC ] = { .pme_name = "PM_FXLS1_FULL_CYC", .pme_code = 0x110c4, .pme_short_desc = "Cycles FXU1/LS1 queue full", .pme_long_desc = "The issue queue that feeds the Fixed Point unit 1 / Load Store Unit 1 is full. This condition will prevent dispatch groups from being dispatched. This event only indicates that the queue was full, not that dispatch was prevented.", }, [ POWER5_PME_PM_DATA_FROM_L275_SHR ] = { .pme_name = "PM_DATA_FROM_L275_SHR", .pme_code = 0x3c3097, .pme_short_desc = "Data loaded from L2.75 shared", .pme_long_desc = "The processor's Data Cache was reloaded with shared (T) data from the L2 on a different module than this processor is located due to a demand load. ", }, [ POWER5_PME_PM_THRD_SEL_T0 ] = { .pme_name = "PM_THRD_SEL_T0", .pme_code = 0x410c0, .pme_short_desc = "Decode selected thread 0", .pme_long_desc = "Thread selection picked thread 0 for decode.", }, [ POWER5_PME_PM_PTEG_RELOAD_VALID ] = { .pme_name = "PM_PTEG_RELOAD_VALID", .pme_code = 0x830e4, .pme_short_desc = "PTEG reload valid", .pme_long_desc = "A Page Table Entry was loaded into the TLB.", }, [ POWER5_PME_PM_LSU_LMQ_LHR_MERGE ] = { .pme_name = "PM_LSU_LMQ_LHR_MERGE", .pme_code = 0xc70e5, .pme_short_desc = "LMQ LHR merges", .pme_long_desc = "A data cache miss occurred for the same real cache line address as an earlier request already in the Load Miss Queue and was merged into the LMQ entry.", }, [ POWER5_PME_PM_MRK_STCX_FAIL ] = { .pme_name = "PM_MRK_STCX_FAIL", .pme_code = 0x820e6, .pme_short_desc = "Marked STCX failed", .pme_long_desc = "A marked stcx (stwcx or stdcx) failed", }, [ POWER5_PME_PM_2INST_CLB_CYC ] = { .pme_name = "PM_2INST_CLB_CYC", .pme_code = 0x400c2, .pme_short_desc = "Cycles 2 instructions in CLB", .pme_long_desc = "The cache line buffer (CLB) is a 6-deep, 4-wide instruction buffer. Fullness is reported on a cycle basis with each event representing the number of cycles the CLB had the corresponding number of entries occupied. These events give a real time history of the number of instruction buffers used, but not the number of PowerPC instructions within those buffers. Each thread has its own set of CLB; these events are thread specific.", }, [ POWER5_PME_PM_FAB_PNtoVN_DIRECT ] = { .pme_name = "PM_FAB_PNtoVN_DIRECT", .pme_code = 0x723e7, .pme_short_desc = "PN to VN beat went straight to its destination", .pme_long_desc = "Fabric Data beats that the base chip takes the inbound PN data and passes it through to the outbound VN bus without going into a sidecar. The signal is delivered at FBC speed and the count must be scaled accordingly.", }, [ POWER5_PME_PM_PTEG_FROM_L2MISS ] = { .pme_name = "PM_PTEG_FROM_L2MISS", .pme_code = 0x38309b, .pme_short_desc = "PTEG loaded from L2 miss", .pme_long_desc = "A Page Table Entry was loaded into the TLB but not from the local L2.", }, [ POWER5_PME_PM_CMPLU_STALL_LSU ] = { .pme_name = "PM_CMPLU_STALL_LSU", .pme_code = 0x211098, .pme_short_desc = "Completion stall caused by LSU instruction", .pme_long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes was a load/store instruction.", }, [ POWER5_PME_PM_MRK_DSLB_MISS ] = { .pme_name = "PM_MRK_DSLB_MISS", .pme_code = 0xc50c7, .pme_short_desc = "Marked Data SLB misses", .pme_long_desc = "A Data SLB miss was caused by a marked instruction.", }, [ POWER5_PME_PM_LSU_FLUSH_ULD ] = { .pme_name = "PM_LSU_FLUSH_ULD", .pme_code = 0x1c0088, .pme_short_desc = "LRQ unaligned load flushes", .pme_long_desc = "A load was flushed because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1). Combined Unit 0 + 1.", }, [ POWER5_PME_PM_PTEG_FROM_LMEM ] = { .pme_name = "PM_PTEG_FROM_LMEM", .pme_code = 0x283087, .pme_short_desc = "PTEG loaded from local memory", .pme_long_desc = "A Page Table Entry was loaded into the TLB from memory attached to the same module this proccessor is located on.", }, [ POWER5_PME_PM_MRK_BRU_FIN ] = { .pme_name = "PM_MRK_BRU_FIN", .pme_code = 0x200005, .pme_short_desc = "Marked instruction BRU processing finished", .pme_long_desc = "The branch unit finished a marked instruction. Instructions that finish may not necessary complete.", }, [ POWER5_PME_PM_MEM_WQ_DISP_WRITE ] = { .pme_name = "PM_MEM_WQ_DISP_WRITE", .pme_code = 0x703c6, .pme_short_desc = "Memory write queue dispatched due to write", .pme_long_desc = "A memory write was dispatched to a write queue. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", }, [ POWER5_PME_PM_MRK_DATA_FROM_L275_MOD_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L275_MOD_CYC", .pme_code = 0x4c70a3, .pme_short_desc = "Marked load latency from L2.75 modified", .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.", }, [ POWER5_PME_PM_LSU1_NCLD ] = { .pme_name = "PM_LSU1_NCLD", .pme_code = 0xc50c5, .pme_short_desc = "LSU1 non-cacheable loads", .pme_long_desc = "A non-cacheable load was executed by Unit 0.", }, [ POWER5_PME_PM_L2SA_RCLD_DISP_FAIL_OTHER ] = { .pme_name = "PM_L2SA_RCLD_DISP_FAIL_OTHER", .pme_code = 0x731e0, .pme_short_desc = "L2 slice A RC load dispatch attempt failed due to other reasons", .pme_long_desc = "A Read/Claim dispatch for a load failed for some reason other than Full or Collision conditions.", }, [ POWER5_PME_PM_SNOOP_PW_RETRY_WQ_PWQ ] = { .pme_name = "PM_SNOOP_PW_RETRY_WQ_PWQ", .pme_code = 0x717c6, .pme_short_desc = "Snoop partial-write retry due to collision with active write or partial-write queue", .pme_long_desc = "A snoop request for a partial write to memory was retried because it matched the cache line of an active write or partial write. When this happens the snoop request is retried and the active write is changed to high priority. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", }, [ POWER5_PME_PM_FPR_MAP_FULL_CYC ] = { .pme_name = "PM_FPR_MAP_FULL_CYC", .pme_code = 0x100c1, .pme_short_desc = "Cycles FPR mapper full", .pme_long_desc = "The floating point unit has executed an add, mult, sub, compare, fsel, fneg, fabs, fnabs, fres, or frsqrte kind of instruction. These are single FLOP operations. ", }, [ POWER5_PME_PM_FPU1_FULL_CYC ] = { .pme_name = "PM_FPU1_FULL_CYC", .pme_code = 0x100c7, .pme_short_desc = "Cycles FPU1 issue queue full", .pme_long_desc = "The issue queue for FPU1 cannot accept any more instructions. Dispatch to this issue queue is stopped", }, [ POWER5_PME_PM_L3SA_ALL_BUSY ] = { .pme_name = "PM_L3SA_ALL_BUSY", .pme_code = 0x721e3, .pme_short_desc = "L3 slice A active for every cycle all CI/CO machines busy", .pme_long_desc = "Cycles All Castin/Castout machines are busy.", }, [ POWER5_PME_PM_3INST_CLB_CYC ] = { .pme_name = "PM_3INST_CLB_CYC", .pme_code = 0x400c3, .pme_short_desc = "Cycles 3 instructions in CLB", .pme_long_desc = "The cache line buffer (CLB) is a 6-deep, 4-wide instruction buffer. Fullness is reported on a cycle basis with each event representing the number of cycles the CLB had the corresponding number of entries occupied. These events give a real time history of the number of instruction buffers used, but not the number of PowerPC instructions within those buffers. Each thread has its own set of CLB; these events are thread specific.", }, [ POWER5_PME_PM_MEM_PWQ_DISP_Q2or3 ] = { .pme_name = "PM_MEM_PWQ_DISP_Q2or3", .pme_code = 0x734e6, .pme_short_desc = "Memory partial-write queue dispatched to Write Queue 2 or 3", .pme_long_desc = "Memory partial-write queue dispatched to Write Queue 2 or 3. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", }, [ POWER5_PME_PM_L2SA_SHR_INV ] = { .pme_name = "PM_L2SA_SHR_INV", .pme_code = 0x710c0, .pme_short_desc = "L2 slice A transition from shared to invalid", .pme_long_desc = "A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L, or Tagged) to the Invalid state. This transition was caused by any external snoop request. The event is provided on each of the three slices A, B, and C. NOTE: For this event to be useful the tablewalk duration event should also be counted.", }, [ POWER5_PME_PM_THRESH_TIMEO ] = { .pme_name = "PM_THRESH_TIMEO", .pme_code = 0x30000b, .pme_short_desc = "Threshold timeout", .pme_long_desc = "The threshold timer expired", }, [ POWER5_PME_PM_L2SA_RC_DISP_FAIL_CO_BUSY_ALL ] = { .pme_name = "PM_L2SA_RC_DISP_FAIL_CO_BUSY_ALL", .pme_code = 0x713c0, .pme_short_desc = "L2 slice A RC dispatch attempt failed due to all CO busy", .pme_long_desc = "A Read/Claim dispatch was rejected because all Castout machines were busy.", }, [ POWER5_PME_PM_THRD_SEL_OVER_GCT_IMBAL ] = { .pme_name = "PM_THRD_SEL_OVER_GCT_IMBAL", .pme_code = 0x410c4, .pme_short_desc = "Thread selection overrides caused by GCT imbalance", .pme_long_desc = "Thread selection was overridden because of a GCT imbalance.", }, [ POWER5_PME_PM_FPU_FSQRT ] = { .pme_name = "PM_FPU_FSQRT", .pme_code = 0x200090, .pme_short_desc = "FPU executed FSQRT instruction", .pme_long_desc = "The floating point unit has executed a square root instruction. This could be fsqrt* where XYZ* means XYZ, XYZs, XYZ., XYZs. Combined Unit 0 + Unit 1.", }, [ POWER5_PME_PM_MRK_LSU0_FLUSH_LRQ ] = { .pme_name = "PM_MRK_LSU0_FLUSH_LRQ", .pme_code = 0x810c2, .pme_short_desc = "LSU0 marked LRQ flushes", .pme_long_desc = "A marked load was flushed by unit 0 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.", }, [ POWER5_PME_PM_PMC1_OVERFLOW ] = { .pme_name = "PM_PMC1_OVERFLOW", .pme_code = 0x20000a, .pme_short_desc = "PMC1 Overflow", .pme_long_desc = "Overflows from PMC1 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.", }, [ POWER5_PME_PM_L3SC_SNOOP_RETRY ] = { .pme_name = "PM_L3SC_SNOOP_RETRY", .pme_code = 0x731e5, .pme_short_desc = "L3 slice C snoop retries", .pme_long_desc = "Number of times an L3 retried a snoop because it got two in at the same time (one on snp_a, one on snp_b)", }, [ POWER5_PME_PM_DATA_TABLEWALK_CYC ] = { .pme_name = "PM_DATA_TABLEWALK_CYC", .pme_code = 0x800c7, .pme_short_desc = "Cycles doing data tablewalks", .pme_long_desc = "Cycles a translation tablewalk is active. While a tablewalk is active any request attempting to access the TLB will be rejected and retried.", }, [ POWER5_PME_PM_THRD_PRIO_6_CYC ] = { .pme_name = "PM_THRD_PRIO_6_CYC", .pme_code = 0x420e5, .pme_short_desc = "Cycles thread running at priority level 6", .pme_long_desc = "Cycles this thread was running at priority level 6.", }, [ POWER5_PME_PM_FPU_FEST ] = { .pme_name = "PM_FPU_FEST", .pme_code = 0x401090, .pme_short_desc = "FPU executed FEST instruction", .pme_long_desc = "The floating point unit has executed an estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ. Combined Unit 0 + Unit 1.", }, [ POWER5_PME_PM_FAB_M1toP1_SIDECAR_EMPTY ] = { .pme_name = "PM_FAB_M1toP1_SIDECAR_EMPTY", .pme_code = 0x702c7, .pme_short_desc = "M1 to P1 sidecar empty", .pme_long_desc = "Fabric cycles when the Minus-1 hip/hop sidecars (sidecars for chip to chip data transfer) are empty. The signal is delivered at FBC speed and the count must be scaled accordingly.", }, [ POWER5_PME_PM_MRK_DATA_FROM_RMEM ] = { .pme_name = "PM_MRK_DATA_FROM_RMEM", .pme_code = 0x1c70a1, .pme_short_desc = "Marked data loaded from remote memory", .pme_long_desc = "The processor's Data Cache was reloaded due to a marked load from memory attached to a different module than this proccessor is located on.", }, [ POWER5_PME_PM_MRK_DATA_FROM_L35_MOD_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L35_MOD_CYC", .pme_code = 0x4c70a6, .pme_short_desc = "Marked load latency from L3.5 modified", .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.", }, [ POWER5_PME_PM_MEM_PWQ_DISP ] = { .pme_name = "PM_MEM_PWQ_DISP", .pme_code = 0x704c6, .pme_short_desc = "Memory partial-write queue dispatched", .pme_long_desc = "Number of Partial Writes dispatched. The MC provides resources to gather partial cacheline writes (Partial line DMA writes & CI-stores) to up to four different cachelines at a time. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", }, [ POWER5_PME_PM_FAB_P1toM1_SIDECAR_EMPTY ] = { .pme_name = "PM_FAB_P1toM1_SIDECAR_EMPTY", .pme_code = 0x701c7, .pme_short_desc = "P1 to M1 sidecar empty", .pme_long_desc = "Fabric cycles when the Plus-1 hip/hop sidecars (sidecars for chip to chip data transfer) are empty. The signal is delivered at FBC speed and the count must be scaled accordingly.", }, [ POWER5_PME_PM_LD_MISS_L1_LSU0 ] = { .pme_name = "PM_LD_MISS_L1_LSU0", .pme_code = 0xc10c2, .pme_short_desc = "LSU0 L1 D cache load misses", .pme_long_desc = "Load references that miss the Level 1 Data cache, by unit 0.", }, [ POWER5_PME_PM_SNOOP_PARTIAL_RTRY_QFULL ] = { .pme_name = "PM_SNOOP_PARTIAL_RTRY_QFULL", .pme_code = 0x730e6, .pme_short_desc = "Snoop partial write retry due to partial-write queues full", .pme_long_desc = "A snoop request for a partial write to memory was retried because the write queues that handle partial writes were full. When this happens the active writes are changed to high priority. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", }, [ POWER5_PME_PM_FPU1_STALL3 ] = { .pme_name = "PM_FPU1_STALL3", .pme_code = 0x20e5, .pme_short_desc = "FPU1 stalled in pipe3", .pme_long_desc = "FPU1 has generated a stall in pipe3 due to overflow, underflow, massive cancel, convert to integer (sometimes), or convert from integer (always).", }, [ POWER5_PME_PM_GCT_USAGE_80to99_CYC ] = { .pme_name = "PM_GCT_USAGE_80to99_CYC", .pme_code = 0x30001f, .pme_short_desc = "Cycles GCT 80-99% full", .pme_long_desc = "Cycles when the Global Completion Table has between 80% and 99% of its slots used. The GCT has 20 entries shared between threads", }, [ POWER5_PME_PM_WORK_HELD ] = { .pme_name = "PM_WORK_HELD", .pme_code = 0x40000c, .pme_short_desc = "Work held", .pme_long_desc = "RAS Unit has signaled completion to stop and there are groups waiting to complete", }, [ POWER5_PME_PM_INST_CMPL ] = { .pme_name = "PM_INST_CMPL", .pme_code = 0x100009, .pme_short_desc = "Instructions completed", .pme_long_desc = "Number of PowerPC instructions that completed. ", }, [ POWER5_PME_PM_LSU1_FLUSH_UST ] = { .pme_name = "PM_LSU1_FLUSH_UST", .pme_code = 0xc00c5, .pme_short_desc = "LSU1 unaligned store flushes", .pme_long_desc = "A store was flushed from unit 1 because it was unaligned (crossed a 4K boundary)", }, [ POWER5_PME_PM_FXU_IDLE ] = { .pme_name = "PM_FXU_IDLE", .pme_code = 0x100012, .pme_short_desc = "FXU idle", .pme_long_desc = "FXU0 and FXU1 are both idle.", }, [ POWER5_PME_PM_LSU0_FLUSH_ULD ] = { .pme_name = "PM_LSU0_FLUSH_ULD", .pme_code = 0xc00c0, .pme_short_desc = "LSU0 unaligned load flushes", .pme_long_desc = "A load was flushed from unit 0 because it was unaligned (crossed a 64 byte boundary, or 32 byte if it missed the L1)", }, [ POWER5_PME_PM_LSU1_REJECT_LMQ_FULL ] = { .pme_name = "PM_LSU1_REJECT_LMQ_FULL", .pme_code = 0xc60e5, .pme_short_desc = "LSU1 reject due to LMQ full or missed data coming", .pme_long_desc = "Total cycles the Load Store Unit 1 is busy rejecting instructions because the Load Miss Queue was full. The LMQ has eight entries. If all eight entries are full, subsequent load instructions are rejected.", }, [ POWER5_PME_PM_GRP_DISP_REJECT ] = { .pme_name = "PM_GRP_DISP_REJECT", .pme_code = 0x120e4, .pme_short_desc = "Group dispatch rejected", .pme_long_desc = "A group that previously attempted dispatch was rejected.", }, [ POWER5_PME_PM_L2SA_MOD_INV ] = { .pme_name = "PM_L2SA_MOD_INV", .pme_code = 0x730e0, .pme_short_desc = "L2 slice A transition from modified to invalid", .pme_long_desc = "A cache line in the local L2 directory made a state transition from the Modified state to the Invalid state. This transition was caused by any RWITM snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A, B, and C.", }, [ POWER5_PME_PM_PTEG_FROM_L25_SHR ] = { .pme_name = "PM_PTEG_FROM_L25_SHR", .pme_code = 0x183097, .pme_short_desc = "PTEG loaded from L2.5 shared", .pme_long_desc = "A Page Table Entry was loaded into the TLB with shared (T or SL) data from the L2 of a chip on the same module as this processor is located due to a demand load.", }, [ POWER5_PME_PM_FAB_CMD_RETRIED ] = { .pme_name = "PM_FAB_CMD_RETRIED", .pme_code = 0x710c7, .pme_short_desc = "Fabric command retried", .pme_long_desc = "Incremented when a command issued by a chip on its SnoopA address bus is retried for any reason. The overwhelming majority of retries are due to running out of memory controller queues but retries can also be caused by trying to reference addresses that are in a transient cache state -- e.g. a line is transient after issuing a DCLAIM instruction to a shared line but before the associated store completes. Each chip reports its own counts. The signal is delivered at FBC speed and the count must be scaled accordingly.", }, [ POWER5_PME_PM_L3SA_SHR_INV ] = { .pme_name = "PM_L3SA_SHR_INV", .pme_code = 0x710c3, .pme_short_desc = "L3 slice A transition from shared to invalid", .pme_long_desc = "L3 snooper detects someone doing a store to a line that is Sx in this L3(i.e. invalidate hit SX and dispatched).", }, [ POWER5_PME_PM_L2SB_RC_DISP_FAIL_CO_BUSY_ALL ] = { .pme_name = "PM_L2SB_RC_DISP_FAIL_CO_BUSY_ALL", .pme_code = 0x713c1, .pme_short_desc = "L2 slice B RC dispatch attempt failed due to all CO busy", .pme_long_desc = "A Read/Claim dispatch was rejected because all Castout machines were busy.", }, [ POWER5_PME_PM_L2SA_RCST_DISP_FAIL_ADDR ] = { .pme_name = "PM_L2SA_RCST_DISP_FAIL_ADDR", .pme_code = 0x712c0, .pme_short_desc = "L2 slice A RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ", .pme_long_desc = "A Read/Claim dispatch for a store failed because of an address conflict. Two RC machines will never both work on the same line or line in the same congruence class at the same time.", }, [ POWER5_PME_PM_L2SA_RCLD_DISP_FAIL_RC_FULL ] = { .pme_name = "PM_L2SA_RCLD_DISP_FAIL_RC_FULL", .pme_code = 0x721e0, .pme_short_desc = "L2 slice A RC load dispatch attempt failed due to all RC full", .pme_long_desc = "A Read/Claim dispatch for a load failed because all RC machines are busy.", }, [ POWER5_PME_PM_PTEG_FROM_L375_MOD ] = { .pme_name = "PM_PTEG_FROM_L375_MOD", .pme_code = 0x1830a7, .pme_short_desc = "PTEG loaded from L3.75 modified", .pme_long_desc = "A Page Table Entry was loaded into the TLB with modified (M) data from the L3 of a chip on a different module than this processor is located, due to a demand load.", }, [ POWER5_PME_PM_MRK_LSU1_FLUSH_UST ] = { .pme_name = "PM_MRK_LSU1_FLUSH_UST", .pme_code = 0x810c5, .pme_short_desc = "LSU1 marked unaligned store flushes", .pme_long_desc = "A marked store was flushed from unit 1 because it was unaligned (crossed a 4k boundary)", }, [ POWER5_PME_PM_BR_ISSUED ] = { .pme_name = "PM_BR_ISSUED", .pme_code = 0x230e4, .pme_short_desc = "Branches issued", .pme_long_desc = "A branch instruction was issued to the branch unit. A branch that was incorrectly predicted may issue and execute multiple times.", }, [ POWER5_PME_PM_MRK_GRP_BR_REDIR ] = { .pme_name = "PM_MRK_GRP_BR_REDIR", .pme_code = 0x212091, .pme_short_desc = "Group experienced marked branch redirect", .pme_long_desc = "A group containing a marked (sampled) instruction experienced a branch redirect.", }, [ POWER5_PME_PM_EE_OFF ] = { .pme_name = "PM_EE_OFF", .pme_code = 0x130e3, .pme_short_desc = "Cycles MSR(EE) bit off", .pme_long_desc = "Cycles MSR(EE) bit was off indicating that interrupts due to external exceptions were masked.", }, [ POWER5_PME_PM_MEM_RQ_DISP_Q4to7 ] = { .pme_name = "PM_MEM_RQ_DISP_Q4to7", .pme_code = 0x712c6, .pme_short_desc = "Memory read queue dispatched to queues 4-7", .pme_long_desc = "A memory operation was dispatched to read queue 4,5,6 or 7. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", }, [ POWER5_PME_PM_MEM_FAST_PATH_RD_DISP ] = { .pme_name = "PM_MEM_FAST_PATH_RD_DISP", .pme_code = 0x713e6, .pme_short_desc = "Fast path memory read dispatched", .pme_long_desc = "Fast path memory read dispatched", }, [ POWER5_PME_PM_INST_FROM_L3 ] = { .pme_name = "PM_INST_FROM_L3", .pme_code = 0x12208d, .pme_short_desc = "Instruction fetched from L3", .pme_long_desc = "An instruction fetch group was fetched from the local L3. Fetch groups can contain up to 8 instructions", }, [ POWER5_PME_PM_ITLB_MISS ] = { .pme_name = "PM_ITLB_MISS", .pme_code = 0x800c0, .pme_short_desc = "Instruction TLB misses", .pme_long_desc = "A TLB miss for an Instruction Fetch has occurred", }, [ POWER5_PME_PM_FXU1_BUSY_FXU0_IDLE ] = { .pme_name = "PM_FXU1_BUSY_FXU0_IDLE", .pme_code = 0x400012, .pme_short_desc = "FXU1 busy FXU0 idle", .pme_long_desc = "FXU0 was idle while FXU1 was busy.", }, [ POWER5_PME_PM_FXLS_FULL_CYC ] = { .pme_name = "PM_FXLS_FULL_CYC", .pme_code = 0x411090, .pme_short_desc = "Cycles FXLS queue is full", .pme_long_desc = "Cycles when the issue queues for one or both FXU/LSU units is full. Use with caution since this is the sum of cycles when Unit 0 was full plus Unit 1 full. It does not indicate when both units were full.", }, [ POWER5_PME_PM_DTLB_REF_4K ] = { .pme_name = "PM_DTLB_REF_4K", .pme_code = 0xc40c2, .pme_short_desc = "Data TLB reference for 4K page", .pme_long_desc = "Data TLB references for 4KB pages. Includes hits + misses.", }, [ POWER5_PME_PM_GRP_DISP_VALID ] = { .pme_name = "PM_GRP_DISP_VALID", .pme_code = 0x120e3, .pme_short_desc = "Group dispatch valid", .pme_long_desc = "A group is available for dispatch. This does not mean it was successfully dispatched.", }, [ POWER5_PME_PM_LSU_FLUSH_UST ] = { .pme_name = "PM_LSU_FLUSH_UST", .pme_code = 0x2c0088, .pme_short_desc = "SRQ unaligned store flushes", .pme_long_desc = "A store was flushed because it was unaligned (crossed a 4K boundary). Combined Unit 0 + 1.", }, [ POWER5_PME_PM_FXU1_FIN ] = { .pme_name = "PM_FXU1_FIN", .pme_code = 0x130e6, .pme_short_desc = "FXU1 produced a result", .pme_long_desc = "The Fixed Point unit 1 finished an instruction and produced a result. Instructions that finish may not necessary complete.", }, [ POWER5_PME_PM_THRD_PRIO_4_CYC ] = { .pme_name = "PM_THRD_PRIO_4_CYC", .pme_code = 0x420e3, .pme_short_desc = "Cycles thread running at priority level 4", .pme_long_desc = "Cycles this thread was running at priority level 4.", }, [ POWER5_PME_PM_MRK_DATA_FROM_L35_MOD ] = { .pme_name = "PM_MRK_DATA_FROM_L35_MOD", .pme_code = 0x2c709e, .pme_short_desc = "Marked data loaded from L3.5 modified", .pme_long_desc = "The processor's Data Cache was reloaded with modified (M) data from the L3 of a chip on the same module as this processor is located due to a marked load.", }, [ POWER5_PME_PM_4INST_CLB_CYC ] = { .pme_name = "PM_4INST_CLB_CYC", .pme_code = 0x400c4, .pme_short_desc = "Cycles 4 instructions in CLB", .pme_long_desc = "The cache line buffer (CLB) is a 6-deep, 4-wide instruction buffer. Fullness is reported on a cycle basis with each event representing the number of cycles the CLB had the corresponding number of entries occupied. These events give a real time history of the number of instruction buffers used, but not the number of PowerPC instructions within those buffers. Each thread has its own set of CLB; these events are thread specific.", }, [ POWER5_PME_PM_MRK_DTLB_REF_16M ] = { .pme_name = "PM_MRK_DTLB_REF_16M", .pme_code = 0xc40c7, .pme_short_desc = "Marked Data TLB reference for 16M page", .pme_long_desc = "Data TLB references by a marked instruction for 16MB pages.", }, [ POWER5_PME_PM_INST_FROM_L375_MOD ] = { .pme_name = "PM_INST_FROM_L375_MOD", .pme_code = 0x42209d, .pme_short_desc = "Instruction fetched from L3.75 modified", .pme_long_desc = "An instruction fetch group was fetched with modified (M) data from the L3 of a chip on a different module than this processor is located. Fetch groups can contain up to 8 instructions", }, [ POWER5_PME_PM_L2SC_RCST_DISP_FAIL_ADDR ] = { .pme_name = "PM_L2SC_RCST_DISP_FAIL_ADDR", .pme_code = 0x712c2, .pme_short_desc = "L2 slice C RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ", .pme_long_desc = "A Read/Claim dispatch for a store failed because of an address conflict. Two RC machines will never both work on the same line or line in the same congruence class at the same time.", }, [ POWER5_PME_PM_GRP_CMPL ] = { .pme_name = "PM_GRP_CMPL", .pme_code = 0x300013, .pme_short_desc = "Group completed", .pme_long_desc = "A group completed. Microcoded instructions that span multiple groups will generate this event once per group.", }, [ POWER5_PME_PM_FPU1_1FLOP ] = { .pme_name = "PM_FPU1_1FLOP", .pme_code = 0xc7, .pme_short_desc = "FPU1 executed add, mult, sub, cmp or sel instruction", .pme_long_desc = "The floating point unit has executed an add, mult, sub, compare, fsel, fneg, fabs, fnabs, fres, or frsqrte kind of instruction. These are single FLOP operations.", }, [ POWER5_PME_PM_FPU_FRSP_FCONV ] = { .pme_name = "PM_FPU_FRSP_FCONV", .pme_code = 0x301090, .pme_short_desc = "FPU executed FRSP or FCONV instructions", .pme_long_desc = "The floating point unit has executed a frsp or convert kind of instruction. This could be frsp*, fcfid*, fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs. Combined Unit 0 + Unit 1.", }, [ POWER5_PME_PM_5INST_CLB_CYC ] = { .pme_name = "PM_5INST_CLB_CYC", .pme_code = 0x400c5, .pme_short_desc = "Cycles 5 instructions in CLB", .pme_long_desc = "The cache line buffer (CLB) is a 6-deep, 4-wide instruction buffer. Fullness is reported on a cycle basis with each event representing the number of cycles the CLB had the corresponding number of entries occupied. These events give a real time history of the number of instruction buffers used, but not the number of PowerPC instructions within those buffers. Each thread has its own set of CLB; these events are thread specific.", }, [ POWER5_PME_PM_L3SC_REF ] = { .pme_name = "PM_L3SC_REF", .pme_code = 0x701c5, .pme_short_desc = "L3 slice C references", .pme_long_desc = "Number of attempts made by this chip cores to find data in the L3. Reported per L3 slice.", }, [ POWER5_PME_PM_THRD_L2MISS_BOTH_CYC ] = { .pme_name = "PM_THRD_L2MISS_BOTH_CYC", .pme_code = 0x410c7, .pme_short_desc = "Cycles both threads in L2 misses", .pme_long_desc = "Cycles that both threads have L2 miss pending. If only one thread has a L2 miss pending the other thread is given priority at decode. If both threads have L2 miss pending decode priority is determined by the number of GCT entries used.", }, [ POWER5_PME_PM_MEM_PW_GATH ] = { .pme_name = "PM_MEM_PW_GATH", .pme_code = 0x714c6, .pme_short_desc = "Memory partial-write gathered", .pme_long_desc = "Two or more partial-writes have been merged into a single memory write. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", }, [ POWER5_PME_PM_FAB_PNtoNN_SIDECAR ] = { .pme_name = "PM_FAB_PNtoNN_SIDECAR", .pme_code = 0x713c7, .pme_short_desc = "PN to NN beat went to sidecar first", .pme_long_desc = "Fabric Data beats that the base chip takes the inbound PN data and forwards it on to the outbound NN data bus after going into a sidecar first. The signal is delivered at FBC speed and the count must be scaled.", }, [ POWER5_PME_PM_FAB_DCLAIM_ISSUED ] = { .pme_name = "PM_FAB_DCLAIM_ISSUED", .pme_code = 0x720e7, .pme_short_desc = "dclaim issued", .pme_long_desc = "A DCLAIM command was issued. Each chip reports its own counts. The signal is delivered at FBC speed and the count must be scaled accordingly. ", }, [ POWER5_PME_PM_GRP_IC_MISS ] = { .pme_name = "PM_GRP_IC_MISS", .pme_code = 0x120e7, .pme_short_desc = "Group experienced I cache miss", .pme_long_desc = "Number of groups, counted at dispatch, that have encountered an icache miss redirect. Every group constructed from a fetch group that missed the instruction cache will count.", }, [ POWER5_PME_PM_INST_FROM_L35_SHR ] = { .pme_name = "PM_INST_FROM_L35_SHR", .pme_code = 0x12209d, .pme_short_desc = "Instruction fetched from L3.5 shared", .pme_long_desc = "An instruction fetch group was fetched with shared (S) data from the L3 of a chip on the same module as this processor is located. Fetch groups can contain up to 8 instructions", }, [ POWER5_PME_PM_LSU_LMQ_FULL_CYC ] = { .pme_name = "PM_LSU_LMQ_FULL_CYC", .pme_code = 0xc30e7, .pme_short_desc = "Cycles LMQ full", .pme_long_desc = "The Load Miss Queue was full.", }, [ POWER5_PME_PM_MRK_DATA_FROM_L2_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L2_CYC", .pme_code = 0x2c70a0, .pme_short_desc = "Marked load latency from L2", .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.", }, [ POWER5_PME_PM_LSU_SRQ_SYNC_CYC ] = { .pme_name = "PM_LSU_SRQ_SYNC_CYC", .pme_code = 0x830e5, .pme_short_desc = "SRQ sync duration", .pme_long_desc = "Cycles that a sync instruction is active in the Store Request Queue.", }, [ POWER5_PME_PM_LSU0_BUSY_REJECT ] = { .pme_name = "PM_LSU0_BUSY_REJECT", .pme_code = 0xc20e3, .pme_short_desc = "LSU0 busy due to reject", .pme_long_desc = "Total cycles the Load Store Unit 0 is busy rejecting instructions. ", }, [ POWER5_PME_PM_LSU_REJECT_ERAT_MISS ] = { .pme_name = "PM_LSU_REJECT_ERAT_MISS", .pme_code = 0x1c6090, .pme_short_desc = "LSU reject due to ERAT miss", .pme_long_desc = "Total cycles the Load Store Unit is busy rejecting instructions due to an ERAT miss. Combined unit 0 + 1. Requests that miss the Derat are rejected and retried until the request hits in the Erat.", }, [ POWER5_PME_PM_MRK_DATA_FROM_RMEM_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_RMEM_CYC", .pme_code = 0x4c70a1, .pme_short_desc = "Marked load latency from remote memory", .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.", }, [ POWER5_PME_PM_DATA_FROM_L375_SHR ] = { .pme_name = "PM_DATA_FROM_L375_SHR", .pme_code = 0x3c309e, .pme_short_desc = "Data loaded from L3.75 shared", .pme_long_desc = "The processor's Data Cache was reloaded with shared (S) data from the L3 of a chip on a different module than this processor is located due to a demand load.", }, [ POWER5_PME_PM_FPU0_FMOV_FEST ] = { .pme_name = "PM_FPU0_FMOV_FEST", .pme_code = 0x10c0, .pme_short_desc = "FPU0 executed FMOV or FEST instructions", .pme_long_desc = "FPU0 has executed a move kind of instruction or one of the estimate instructions. This could be fmr*, fneg*, fabs*, fnabs* , fres* or frsqrte* where XYZ* means XYZ or XYZ.", }, [ POWER5_PME_PM_PTEG_FROM_L25_MOD ] = { .pme_name = "PM_PTEG_FROM_L25_MOD", .pme_code = 0x283097, .pme_short_desc = "PTEG loaded from L2.5 modified", .pme_long_desc = "A Page Table Entry was loaded into the TLB with modified (M) data from the L2 of a chip on the same module as this processor is located due to a demand load.", }, [ POWER5_PME_PM_LD_REF_L1_LSU0 ] = { .pme_name = "PM_LD_REF_L1_LSU0", .pme_code = 0xc10c0, .pme_short_desc = "LSU0 L1 D cache load references", .pme_long_desc = "Load references to Level 1 Data Cache, by unit 0.", }, [ POWER5_PME_PM_THRD_PRIO_7_CYC ] = { .pme_name = "PM_THRD_PRIO_7_CYC", .pme_code = 0x420e6, .pme_short_desc = "Cycles thread running at priority level 7", .pme_long_desc = "Cycles this thread was running at priority level 7.", }, [ POWER5_PME_PM_LSU1_FLUSH_SRQ ] = { .pme_name = "PM_LSU1_FLUSH_SRQ", .pme_code = 0xc00c7, .pme_short_desc = "LSU1 SRQ lhs flushes", .pme_long_desc = "A store was flushed because younger load hits and older store that is already in the SRQ or in the same group. ", }, [ POWER5_PME_PM_L2SC_RCST_DISP ] = { .pme_name = "PM_L2SC_RCST_DISP", .pme_code = 0x702c2, .pme_short_desc = "L2 slice C RC store dispatch attempt", .pme_long_desc = "A Read/Claim dispatch for a Store was attempted.", }, [ POWER5_PME_PM_CMPLU_STALL_DIV ] = { .pme_name = "PM_CMPLU_STALL_DIV", .pme_code = 0x411099, .pme_short_desc = "Completion stall caused by DIV instruction", .pme_long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes was a fixed point divide instruction. This is a subset of PM_CMPLU_STALL_FXU.", }, [ POWER5_PME_PM_MEM_RQ_DISP_Q12to15 ] = { .pme_name = "PM_MEM_RQ_DISP_Q12to15", .pme_code = 0x732e6, .pme_short_desc = "Memory read queue dispatched to queues 12-15", .pme_long_desc = "A memory operation was dispatched to read queue 12,13,14 or 15. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", }, [ POWER5_PME_PM_INST_FROM_L375_SHR ] = { .pme_name = "PM_INST_FROM_L375_SHR", .pme_code = 0x32209d, .pme_short_desc = "Instruction fetched from L3.75 shared", .pme_long_desc = "An instruction fetch group was fetched with shared (S) data from the L3 of a chip on a different module than this processor is located. Fetch groups can contain up to 8 instructions", }, [ POWER5_PME_PM_ST_REF_L1 ] = { .pme_name = "PM_ST_REF_L1", .pme_code = 0x3c1090, .pme_short_desc = "L1 D cache store references", .pme_long_desc = "Store references to the Data Cache. Combined Unit 0 + 1.", }, [ POWER5_PME_PM_L3SB_ALL_BUSY ] = { .pme_name = "PM_L3SB_ALL_BUSY", .pme_code = 0x721e4, .pme_short_desc = "L3 slice B active for every cycle all CI/CO machines busy", .pme_long_desc = "Cycles All Castin/Castout machines are busy.", }, [ POWER5_PME_PM_FAB_P1toVNorNN_SIDECAR_EMPTY ] = { .pme_name = "PM_FAB_P1toVNorNN_SIDECAR_EMPTY", .pme_code = 0x711c7, .pme_short_desc = "P1 to VN/NN sidecar empty", .pme_long_desc = "Fabric cycles when the Plus-1 jump sidecar (sidecars for mcm to mcm data transfer) is empty. The signal is delivered at FBC speed and the count must be scaled accordingly.", }, [ POWER5_PME_PM_MRK_DATA_FROM_L275_SHR_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L275_SHR_CYC", .pme_code = 0x2c70a3, .pme_short_desc = "Marked load latency from L2.75 shared", .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.", }, [ POWER5_PME_PM_FAB_HOLDtoNN_EMPTY ] = { .pme_name = "PM_FAB_HOLDtoNN_EMPTY", .pme_code = 0x722e7, .pme_short_desc = "Hold buffer to NN empty", .pme_long_desc = "Fabric cyles when the Next Node out hold-buffers are emtpy. The signal is delivered at FBC speed and the count must be scaled accordingly.", }, [ POWER5_PME_PM_DATA_FROM_LMEM ] = { .pme_name = "PM_DATA_FROM_LMEM", .pme_code = 0x2c3087, .pme_short_desc = "Data loaded from local memory", .pme_long_desc = "The processor's Data Cache was reloaded from memory attached to the same module this proccessor is located on.", }, [ POWER5_PME_PM_RUN_CYC ] = { .pme_name = "PM_RUN_CYC", .pme_code = 0x100005, .pme_short_desc = "Run cycles", .pme_long_desc = "Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.", }, [ POWER5_PME_PM_PTEG_FROM_RMEM ] = { .pme_name = "PM_PTEG_FROM_RMEM", .pme_code = 0x1830a1, .pme_short_desc = "PTEG loaded from remote memory", .pme_long_desc = "A Page Table Entry was loaded into the TLB from memory attached to a different module than this proccessor is located on.", }, [ POWER5_PME_PM_L2SC_RCLD_DISP ] = { .pme_name = "PM_L2SC_RCLD_DISP", .pme_code = 0x701c2, .pme_short_desc = "L2 slice C RC load dispatch attempt", .pme_long_desc = "A Read/Claim dispatch for a Load was attempted", }, [ POWER5_PME_PM_LSU0_LDF ] = { .pme_name = "PM_LSU0_LDF", .pme_code = 0xc50c0, .pme_short_desc = "LSU0 executed Floating Point load instruction", .pme_long_desc = "A floating point load was executed by LSU0", }, [ POWER5_PME_PM_LSU_LRQ_S0_VALID ] = { .pme_name = "PM_LSU_LRQ_S0_VALID", .pme_code = 0xc20e2, .pme_short_desc = "LRQ slot 0 valid", .pme_long_desc = "This signal is asserted every cycle that the Load Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin. In SMT mode the LRQ is split between the two threads (16 entries each).", }, [ POWER5_PME_PM_PMC3_OVERFLOW ] = { .pme_name = "PM_PMC3_OVERFLOW", .pme_code = 0x40000a, .pme_short_desc = "PMC3 Overflow", .pme_long_desc = "Overflows from PMC3 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.", }, [ POWER5_PME_PM_MRK_IMR_RELOAD ] = { .pme_name = "PM_MRK_IMR_RELOAD", .pme_code = 0x820e2, .pme_short_desc = "Marked IMR reloaded", .pme_long_desc = "A DL1 reload occurred due to marked load", }, [ POWER5_PME_PM_MRK_GRP_TIMEO ] = { .pme_name = "PM_MRK_GRP_TIMEO", .pme_code = 0x40000b, .pme_short_desc = "Marked group completion timeout", .pme_long_desc = "The sampling timeout expired indicating that the previously sampled instruction is no longer in the processor", }, [ POWER5_PME_PM_ST_MISS_L1 ] = { .pme_name = "PM_ST_MISS_L1", .pme_code = 0xc10c3, .pme_short_desc = "L1 D cache store misses", .pme_long_desc = "A store missed the dcache. Combined Unit 0 + 1.", }, [ POWER5_PME_PM_STOP_COMPLETION ] = { .pme_name = "PM_STOP_COMPLETION", .pme_code = 0x300018, .pme_short_desc = "Completion stopped", .pme_long_desc = "RAS Unit has signaled completion to stop", }, [ POWER5_PME_PM_LSU_BUSY_REJECT ] = { .pme_name = "PM_LSU_BUSY_REJECT", .pme_code = 0x1c2090, .pme_short_desc = "LSU busy due to reject", .pme_long_desc = "Total cycles the Load Store Unit is busy rejecting instructions. Combined unit 0 + 1.", }, [ POWER5_PME_PM_ISLB_MISS ] = { .pme_name = "PM_ISLB_MISS", .pme_code = 0x800c1, .pme_short_desc = "Instruction SLB misses", .pme_long_desc = "A SLB miss for an instruction fetch as occurred", }, [ POWER5_PME_PM_CYC ] = { .pme_name = "PM_CYC", .pme_code = 0xf, .pme_short_desc = "Processor cycles", .pme_long_desc = "Processor cycles", }, [ POWER5_PME_PM_THRD_ONE_RUN_CYC ] = { .pme_name = "PM_THRD_ONE_RUN_CYC", .pme_code = 0x10000b, .pme_short_desc = "One of the threads in run cycles", .pme_long_desc = "At least one thread has set its run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. This event does not respect FCWAIT.", }, [ POWER5_PME_PM_GRP_BR_REDIR_NONSPEC ] = { .pme_name = "PM_GRP_BR_REDIR_NONSPEC", .pme_code = 0x112091, .pme_short_desc = "Group experienced non-speculative branch redirect", .pme_long_desc = "Number of groups, counted at completion, that have encountered a branch redirect.", }, [ POWER5_PME_PM_LSU1_SRQ_STFWD ] = { .pme_name = "PM_LSU1_SRQ_STFWD", .pme_code = 0xc20e4, .pme_short_desc = "LSU1 SRQ store forwarded", .pme_long_desc = "Data from a store instruction was forwarded to a load on unit 1. A load that misses L1 but becomes a store forward is treated as a load miss and it causes the DL1 load miss event to be counted. It does not go into the LMQ. If a load that hits L1 but becomes a store forward, then it's not treated as a load miss.", }, [ POWER5_PME_PM_L3SC_MOD_INV ] = { .pme_name = "PM_L3SC_MOD_INV", .pme_code = 0x730e5, .pme_short_desc = "L3 slice C transition from modified to invalid", .pme_long_desc = "L3 snooper detects someone doing a store to a line that is truly M in this L3 (i.e. L3 going M=>I) Mu|Me are not included since they are formed due to a previous read op Tx is not included since it is considered shared at this point.", }, [ POWER5_PME_PM_L2_PREF ] = { .pme_name = "PM_L2_PREF", .pme_code = 0xc50c3, .pme_short_desc = "L2 cache prefetches", .pme_long_desc = "A request to prefetch data into L2 was made", }, [ POWER5_PME_PM_GCT_NOSLOT_BR_MPRED ] = { .pme_name = "PM_GCT_NOSLOT_BR_MPRED", .pme_code = 0x41009c, .pme_short_desc = "No slot in GCT caused by branch mispredict", .pme_long_desc = "Cycles when the Global Completion Table has no slots from this thread because of a branch misprediction.", }, [ POWER5_PME_PM_MRK_DATA_FROM_L25_MOD ] = { .pme_name = "PM_MRK_DATA_FROM_L25_MOD", .pme_code = 0x2c7097, .pme_short_desc = "Marked data loaded from L2.5 modified", .pme_long_desc = "The processor's Data Cache was reloaded with modified (M) data from the L2 of a chip on the same module as this processor is located due to a marked load.", }, [ POWER5_PME_PM_L2SB_MOD_INV ] = { .pme_name = "PM_L2SB_MOD_INV", .pme_code = 0x730e1, .pme_short_desc = "L2 slice B transition from modified to invalid", .pme_long_desc = "A cache line in the local L2 directory made a state transition from the Modified state to the Invalid state. This transition was caused by any RWITM snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A, B, and C.", }, [ POWER5_PME_PM_L2SB_ST_REQ ] = { .pme_name = "PM_L2SB_ST_REQ", .pme_code = 0x723e1, .pme_short_desc = "L2 slice B store requests", .pme_long_desc = "A store request as seen at the L2 directory has been made from the core. Stores are counted after gathering in the L2 store queues. The event is provided on each of the three slices A, B, and C.", }, [ POWER5_PME_PM_MRK_L1_RELOAD_VALID ] = { .pme_name = "PM_MRK_L1_RELOAD_VALID", .pme_code = 0xc70e4, .pme_short_desc = "Marked L1 reload data source valid", .pme_long_desc = "The source information is valid and is for a marked load", }, [ POWER5_PME_PM_L3SB_HIT ] = { .pme_name = "PM_L3SB_HIT", .pme_code = 0x711c4, .pme_short_desc = "L3 slice B hits", .pme_long_desc = "Number of attempts made by this chip cores that resulted in an L3 hit. Reported per L3 slice", }, [ POWER5_PME_PM_L2SB_SHR_MOD ] = { .pme_name = "PM_L2SB_SHR_MOD", .pme_code = 0x700c1, .pme_short_desc = "L2 slice B transition from shared to modified", .pme_long_desc = "A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L , or Tagged) to the Modified state. This transition was caused by a store from either of the two local CPUs to a cache line in any of the Shared states. The event is provided on each of the three slices A, B, and C. ", }, [ POWER5_PME_PM_EE_OFF_EXT_INT ] = { .pme_name = "PM_EE_OFF_EXT_INT", .pme_code = 0x130e7, .pme_short_desc = "Cycles MSR(EE) bit off and external interrupt pending", .pme_long_desc = "Cycles when an interrupt due to an external exception is pending but external exceptions were masked.", }, [ POWER5_PME_PM_1PLUS_PPC_CMPL ] = { .pme_name = "PM_1PLUS_PPC_CMPL", .pme_code = 0x100013, .pme_short_desc = "One or more PPC instruction completed", .pme_long_desc = "A group containing at least one PPC instruction completed. For microcoded instructions that span multiple groups, this will only occur once.", }, [ POWER5_PME_PM_L2SC_SHR_MOD ] = { .pme_name = "PM_L2SC_SHR_MOD", .pme_code = 0x700c2, .pme_short_desc = "L2 slice C transition from shared to modified", .pme_long_desc = "A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L , or Tagged) to the Modified state. This transition was caused by a store from either of the two local CPUs to a cache line in any of the Shared states. The event is provided on each of the three slices A, B, and C. ", }, [ POWER5_PME_PM_PMC6_OVERFLOW ] = { .pme_name = "PM_PMC6_OVERFLOW", .pme_code = 0x30001a, .pme_short_desc = "PMC6 Overflow", .pme_long_desc = "Overflows from PMC6 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.", }, [ POWER5_PME_PM_LSU_LRQ_FULL_CYC ] = { .pme_name = "PM_LSU_LRQ_FULL_CYC", .pme_code = 0x110c2, .pme_short_desc = "Cycles LRQ full", .pme_long_desc = "Cycles when the LRQ is full.", }, [ POWER5_PME_PM_IC_PREF_INSTALL ] = { .pme_name = "PM_IC_PREF_INSTALL", .pme_code = 0x210c7, .pme_short_desc = "Instruction prefetched installed in prefetch buffer", .pme_long_desc = "A prefetch buffer entry (line) is allocated but the request is not a demand fetch.", }, [ POWER5_PME_PM_TLB_MISS ] = { .pme_name = "PM_TLB_MISS", .pme_code = 0x180088, .pme_short_desc = "TLB misses", .pme_long_desc = "Total of Data TLB mises + Instruction TLB misses", }, [ POWER5_PME_PM_GCT_FULL_CYC ] = { .pme_name = "PM_GCT_FULL_CYC", .pme_code = 0x100c0, .pme_short_desc = "Cycles GCT full", .pme_long_desc = "The Global Completion Table is completely full.", }, [ POWER5_PME_PM_FXU_BUSY ] = { .pme_name = "PM_FXU_BUSY", .pme_code = 0x200012, .pme_short_desc = "FXU busy", .pme_long_desc = "Cycles when both FXU0 and FXU1 are busy.", }, [ POWER5_PME_PM_MRK_DATA_FROM_L3_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L3_CYC", .pme_code = 0x2c70a4, .pme_short_desc = "Marked load latency from L3", .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.", }, [ POWER5_PME_PM_LSU_REJECT_LMQ_FULL ] = { .pme_name = "PM_LSU_REJECT_LMQ_FULL", .pme_code = 0x2c6088, .pme_short_desc = "LSU reject due to LMQ full or missed data coming", .pme_long_desc = "Total cycles the Load Store Unit is busy rejecting instructions because the Load Miss Queue was full. The LMQ has eight entries. If all the eight entries are full, subsequent load instructions are rejected. Combined unit 0 + 1.", }, [ POWER5_PME_PM_LSU_SRQ_S0_ALLOC ] = { .pme_name = "PM_LSU_SRQ_S0_ALLOC", .pme_code = 0xc20e5, .pme_short_desc = "SRQ slot 0 allocated", .pme_long_desc = "SRQ Slot zero was allocated", }, [ POWER5_PME_PM_GRP_MRK ] = { .pme_name = "PM_GRP_MRK", .pme_code = 0x100014, .pme_short_desc = "Group marked in IDU", .pme_long_desc = "A group was sampled (marked). The group is called a marked group. One instruction within the group is tagged for detailed monitoring. The sampled instruction is called a marked instructions. Events associated with the marked instruction are annotated with the marked term.", }, [ POWER5_PME_PM_INST_FROM_L25_SHR ] = { .pme_name = "PM_INST_FROM_L25_SHR", .pme_code = 0x122096, .pme_short_desc = "Instruction fetched from L2.5 shared", .pme_long_desc = "An instruction fetch group was fetched with shared (T or SL) data from the L2 of a chip on the same module as this processor is located. Fetch groups can contain up to 8 instructions.", }, [ POWER5_PME_PM_FPU1_FIN ] = { .pme_name = "PM_FPU1_FIN", .pme_code = 0x10c7, .pme_short_desc = "FPU1 produced a result", .pme_long_desc = "FPU1 finished, produced a result. This only indicates finish, not completion. Floating Point Stores are included in this count but not Floating Point Loads., , ", }, [ POWER5_PME_PM_DC_PREF_STREAM_ALLOC ] = { .pme_name = "PM_DC_PREF_STREAM_ALLOC", .pme_code = 0x830e7, .pme_short_desc = "D cache new prefetch stream allocated", .pme_long_desc = "A new Prefetch Stream was allocated.", }, [ POWER5_PME_PM_BR_MPRED_TA ] = { .pme_name = "PM_BR_MPRED_TA", .pme_code = 0x230e6, .pme_short_desc = "Branch mispredictions due to target address", .pme_long_desc = "A branch instruction target was incorrectly predicted. This will result in a branch mispredict flush unless a flush is detected from an older instruction.", }, [ POWER5_PME_PM_CRQ_FULL_CYC ] = { .pme_name = "PM_CRQ_FULL_CYC", .pme_code = 0x110c1, .pme_short_desc = "Cycles CR issue queue full", .pme_long_desc = "The issue queue that feeds the Conditional Register unit is full. This condition will prevent dispatch groups from being dispatched. This event only indicates that the queue was full, not that dispatch was prevented.", }, [ POWER5_PME_PM_L2SA_RCLD_DISP ] = { .pme_name = "PM_L2SA_RCLD_DISP", .pme_code = 0x701c0, .pme_short_desc = "L2 slice A RC load dispatch attempt", .pme_long_desc = "A Read/Claim dispatch for a Load was attempted", }, [ POWER5_PME_PM_SNOOP_WR_RETRY_QFULL ] = { .pme_name = "PM_SNOOP_WR_RETRY_QFULL", .pme_code = 0x710c6, .pme_short_desc = "Snoop read retry due to read queue full", .pme_long_desc = "A snoop request for a write to memory was retried because the write queues were full. When this happens the snoop request is retried and the writes in the write reorder queue are changed to high priority. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", }, [ POWER5_PME_PM_MRK_DTLB_REF_4K ] = { .pme_name = "PM_MRK_DTLB_REF_4K", .pme_code = 0xc40c3, .pme_short_desc = "Marked Data TLB reference for 4K page", .pme_long_desc = "Data TLB references by a marked instruction for 4KB pages.", }, [ POWER5_PME_PM_LSU_SRQ_S0_VALID ] = { .pme_name = "PM_LSU_SRQ_S0_VALID", .pme_code = 0xc20e1, .pme_short_desc = "SRQ slot 0 valid", .pme_long_desc = "This signal is asserted every cycle that the Store Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin. In SMT mode the SRQ is split between the two threads (16 entries each).", }, [ POWER5_PME_PM_LSU0_FLUSH_LRQ ] = { .pme_name = "PM_LSU0_FLUSH_LRQ", .pme_code = 0xc00c2, .pme_short_desc = "LSU0 LRQ flushes", .pme_long_desc = "A load was flushed by unit 0 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.", }, [ POWER5_PME_PM_INST_FROM_L275_MOD ] = { .pme_name = "PM_INST_FROM_L275_MOD", .pme_code = 0x422096, .pme_short_desc = "Instruction fetched from L2.75 modified", .pme_long_desc = "An instruction fetch group was fetched with modified (M) data from the L2 on a different module than this processor is located. Fetch groups can contain up to 8 instructions ", }, [ POWER5_PME_PM_GCT_EMPTY_CYC ] = { .pme_name = "PM_GCT_EMPTY_CYC", .pme_code = 0x200004, .pme_short_desc = "Cycles GCT empty", .pme_long_desc = "The Global Completion Table is completely empty", }, [ POWER5_PME_PM_LARX_LSU0 ] = { .pme_name = "PM_LARX_LSU0", .pme_code = 0x820e7, .pme_short_desc = "Larx executed on LSU0", .pme_long_desc = "A larx (lwarx or ldarx) was executed on side 0 (there is no corresponding unit 1 event since larx instructions can only execute on unit 0)", }, [ POWER5_PME_PM_THRD_PRIO_DIFF_5or6_CYC ] = { .pme_name = "PM_THRD_PRIO_DIFF_5or6_CYC", .pme_code = 0x430e6, .pme_short_desc = "Cycles thread priority difference is 5 or 6", .pme_long_desc = "Cycles when this thread's priority is higher than the other thread's priority by 5 or 6.", }, [ POWER5_PME_PM_SNOOP_RETRY_1AHEAD ] = { .pme_name = "PM_SNOOP_RETRY_1AHEAD", .pme_code = 0x725e6, .pme_short_desc = "Snoop retry due to one ahead collision", .pme_long_desc = "Snoop retry due to one ahead collision", }, [ POWER5_PME_PM_FPU1_FSQRT ] = { .pme_name = "PM_FPU1_FSQRT", .pme_code = 0xc6, .pme_short_desc = "FPU1 executed FSQRT instruction", .pme_long_desc = "FPU1 has executed a square root instruction. This could be fsqrt* where XYZ* means XYZ, XYZs, XYZ., XYZs.", }, [ POWER5_PME_PM_MRK_LD_MISS_L1_LSU1 ] = { .pme_name = "PM_MRK_LD_MISS_L1_LSU1", .pme_code = 0x820e4, .pme_short_desc = "LSU1 marked L1 D cache load misses", .pme_long_desc = "Load references that miss the Level 1 Data cache, by LSU1.", }, [ POWER5_PME_PM_MRK_FPU_FIN ] = { .pme_name = "PM_MRK_FPU_FIN", .pme_code = 0x300014, .pme_short_desc = "Marked instruction FPU processing finished", .pme_long_desc = "One of the Floating Point Units finished a marked instruction. Instructions that finish may not necessary complete", }, [ POWER5_PME_PM_THRD_PRIO_5_CYC ] = { .pme_name = "PM_THRD_PRIO_5_CYC", .pme_code = 0x420e4, .pme_short_desc = "Cycles thread running at priority level 5", .pme_long_desc = "Cycles this thread was running at priority level 5.", }, [ POWER5_PME_PM_MRK_DATA_FROM_LMEM ] = { .pme_name = "PM_MRK_DATA_FROM_LMEM", .pme_code = 0x2c7087, .pme_short_desc = "Marked data loaded from local memory", .pme_long_desc = "The processor's Data Cache was reloaded due to a marked load from memory attached to the same module this proccessor is located on.", }, [ POWER5_PME_PM_FPU1_FRSP_FCONV ] = { .pme_name = "PM_FPU1_FRSP_FCONV", .pme_code = 0x10c5, .pme_short_desc = "FPU1 executed FRSP or FCONV instructions", .pme_long_desc = "FPU1 has executed a frsp or convert kind of instruction. This could be frsp*, fcfid*, fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs.", }, [ POWER5_PME_PM_SNOOP_TLBIE ] = { .pme_name = "PM_SNOOP_TLBIE", .pme_code = 0x800c3, .pme_short_desc = "Snoop TLBIE", .pme_long_desc = "A tlbie was snooped from another processor.", }, [ POWER5_PME_PM_L3SB_SNOOP_RETRY ] = { .pme_name = "PM_L3SB_SNOOP_RETRY", .pme_code = 0x731e4, .pme_short_desc = "L3 slice B snoop retries", .pme_long_desc = "Number of times an L3 retried a snoop because it got two in at the same time (one on snp_a, one on snp_b)", }, [ POWER5_PME_PM_FAB_VBYPASS_EMPTY ] = { .pme_name = "PM_FAB_VBYPASS_EMPTY", .pme_code = 0x731e7, .pme_short_desc = "Vertical bypass buffer empty", .pme_long_desc = "Fabric cycles when the Middle Bypass sidecar is empty. The signal is delivered at FBC speed and the count must be scaled accordingly.", }, [ POWER5_PME_PM_MRK_DATA_FROM_L275_MOD ] = { .pme_name = "PM_MRK_DATA_FROM_L275_MOD", .pme_code = 0x1c70a3, .pme_short_desc = "Marked data loaded from L2.75 modified", .pme_long_desc = "The processor's Data Cache was reloaded with modified (M) data from the L2 on a different module than this processor is located due to a marked load.", }, [ POWER5_PME_PM_6INST_CLB_CYC ] = { .pme_name = "PM_6INST_CLB_CYC", .pme_code = 0x400c6, .pme_short_desc = "Cycles 6 instructions in CLB", .pme_long_desc = "The cache line buffer (CLB) is a 6-deep, 4-wide instruction buffer. Fullness is reported on a cycle basis with each event representing the number of cycles the CLB had the corresponding number of entries occupied. These events give a real time history of the number of instruction buffers used, but not the number of PowerPC instructions within those buffers. Each thread has its own set of CLB; these events are thread specific.", }, [ POWER5_PME_PM_L2SB_RCST_DISP ] = { .pme_name = "PM_L2SB_RCST_DISP", .pme_code = 0x702c1, .pme_short_desc = "L2 slice B RC store dispatch attempt", .pme_long_desc = "A Read/Claim dispatch for a Store was attempted.", }, [ POWER5_PME_PM_FLUSH ] = { .pme_name = "PM_FLUSH", .pme_code = 0x110c7, .pme_short_desc = "Flushes", .pme_long_desc = "Flushes occurred including LSU and Branch flushes.", }, [ POWER5_PME_PM_L2SC_MOD_INV ] = { .pme_name = "PM_L2SC_MOD_INV", .pme_code = 0x730e2, .pme_short_desc = "L2 slice C transition from modified to invalid", .pme_long_desc = "A cache line in the local L2 directory made a state transition from the Modified state to the Invalid state. This transition was caused by any RWITM snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A, B, and C.", }, [ POWER5_PME_PM_FPU_DENORM ] = { .pme_name = "PM_FPU_DENORM", .pme_code = 0x102088, .pme_short_desc = "FPU received denormalized data", .pme_long_desc = "The floating point unit has encountered a denormalized operand. Combined Unit 0 + Unit 1.", }, [ POWER5_PME_PM_L3SC_HIT ] = { .pme_name = "PM_L3SC_HIT", .pme_code = 0x711c5, .pme_short_desc = "L3 slice C hits", .pme_long_desc = "Number of attempts made by this chip cores that resulted in an L3 hit. Reported per L3 Slice", }, [ POWER5_PME_PM_SNOOP_WR_RETRY_RQ ] = { .pme_name = "PM_SNOOP_WR_RETRY_RQ", .pme_code = 0x706c6, .pme_short_desc = "Snoop write/dclaim retry due to collision with active read queue", .pme_long_desc = "A snoop request for a write or dclaim to memory was retried because it matched the cacheline of an active read. This event is sent from the Memory Controller clock domain and must be scaled accordingly", }, [ POWER5_PME_PM_LSU1_REJECT_SRQ ] = { .pme_name = "PM_LSU1_REJECT_SRQ", .pme_code = 0xc60e4, .pme_short_desc = "LSU1 SRQ lhs rejects", .pme_long_desc = "Total cycles the Load Store Unit 1 is busy rejecting instructions because of Load Hit Store conditions. Loads are rejected when data is needed from a previous store instruction but store forwarding is not possible because the data is not fully contained in the Store Data Queue or is not yet available in the Store Data Queue.", }, [ POWER5_PME_PM_IC_PREF_REQ ] = { .pme_name = "PM_IC_PREF_REQ", .pme_code = 0x220e6, .pme_short_desc = "Instruction prefetch requests", .pme_long_desc = "An instruction prefetch request has been made.", }, [ POWER5_PME_PM_L3SC_ALL_BUSY ] = { .pme_name = "PM_L3SC_ALL_BUSY", .pme_code = 0x721e5, .pme_short_desc = "L3 slice C active for every cycle all CI/CO machines busy", .pme_long_desc = "Cycles All Castin/Castout machines are busy.", }, [ POWER5_PME_PM_MRK_GRP_IC_MISS ] = { .pme_name = "PM_MRK_GRP_IC_MISS", .pme_code = 0x412091, .pme_short_desc = "Group experienced marked I cache miss", .pme_long_desc = "A group containing a marked (sampled) instruction experienced an instruction cache miss.", }, [ POWER5_PME_PM_GCT_NOSLOT_IC_MISS ] = { .pme_name = "PM_GCT_NOSLOT_IC_MISS", .pme_code = 0x21009c, .pme_short_desc = "No slot in GCT caused by I cache miss", .pme_long_desc = "Cycles when the Global Completion Table has no slots from this thread because of an Instruction Cache miss.", }, [ POWER5_PME_PM_MRK_DATA_FROM_L3 ] = { .pme_name = "PM_MRK_DATA_FROM_L3", .pme_code = 0x1c708e, .pme_short_desc = "Marked data loaded from L3", .pme_long_desc = "The processor's Data Cache was reloaded from the local L3 due to a marked load.", }, [ POWER5_PME_PM_GCT_NOSLOT_SRQ_FULL ] = { .pme_name = "PM_GCT_NOSLOT_SRQ_FULL", .pme_code = 0x310084, .pme_short_desc = "No slot in GCT caused by SRQ full", .pme_long_desc = "Cycles when the Global Completion Table has no slots from this thread because the Store Request Queue (SRQ) is full. This happens when the storage subsystem can not process the stores in the SRQ. Groups can not be dispatched until a SRQ entry is available.", }, [ POWER5_PME_PM_THRD_SEL_OVER_ISU_HOLD ] = { .pme_name = "PM_THRD_SEL_OVER_ISU_HOLD", .pme_code = 0x410c5, .pme_short_desc = "Thread selection overrides caused by ISU holds", .pme_long_desc = "Thread selection was overridden because of an ISU hold.", }, [ POWER5_PME_PM_CMPLU_STALL_DCACHE_MISS ] = { .pme_name = "PM_CMPLU_STALL_DCACHE_MISS", .pme_code = 0x21109a, .pme_short_desc = "Completion stall caused by D cache miss", .pme_long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes suffered a Data Cache Miss. Data Cache Miss has higher priority than any other Load/Store delay, so if an instruction encounters multiple delays only the Data Cache Miss will be reported and the entire delay period will be charged to Data Cache Miss. This is a subset of PM_CMPLU_STALL_LSU.", }, [ POWER5_PME_PM_L3SA_MOD_INV ] = { .pme_name = "PM_L3SA_MOD_INV", .pme_code = 0x730e3, .pme_short_desc = "L3 slice A transition from modified to invalid", .pme_long_desc = "L3 snooper detects someone doing a store to a line that is truly M in this L3 (i.e. L3 going M=>I) Mu|Me are not included since they are formed due to a prev read op. Tx is not included since it is considered shared at this point.", }, [ POWER5_PME_PM_LSU_FLUSH_LRQ ] = { .pme_name = "PM_LSU_FLUSH_LRQ", .pme_code = 0x2c0090, .pme_short_desc = "LRQ flushes", .pme_long_desc = "A load was flushed because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte. Combined Units 0 and 1.", }, [ POWER5_PME_PM_THRD_PRIO_2_CYC ] = { .pme_name = "PM_THRD_PRIO_2_CYC", .pme_code = 0x420e1, .pme_short_desc = "Cycles thread running at priority level 2", .pme_long_desc = "Cycles this thread was running at priority level 2.", }, [ POWER5_PME_PM_LSU_FLUSH_SRQ ] = { .pme_name = "PM_LSU_FLUSH_SRQ", .pme_code = 0x1c0090, .pme_short_desc = "SRQ flushes", .pme_long_desc = "A store was flushed because younger load hits and older store that is already in the SRQ or in the same group. Combined Unit 0 + 1.", }, [ POWER5_PME_PM_MRK_LSU_SRQ_INST_VALID ] = { .pme_name = "PM_MRK_LSU_SRQ_INST_VALID", .pme_code = 0xc70e6, .pme_short_desc = "Marked instruction valid in SRQ", .pme_long_desc = "This signal is asserted every cycle when a marked request is resident in the Store Request Queue", }, [ POWER5_PME_PM_L3SA_REF ] = { .pme_name = "PM_L3SA_REF", .pme_code = 0x701c3, .pme_short_desc = "L3 slice A references", .pme_long_desc = "Number of attempts made by this chip cores to find data in the L3. Reported per L3 slice ", }, [ POWER5_PME_PM_L2SC_RC_DISP_FAIL_CO_BUSY_ALL ] = { .pme_name = "PM_L2SC_RC_DISP_FAIL_CO_BUSY_ALL", .pme_code = 0x713c2, .pme_short_desc = "L2 slice C RC dispatch attempt failed due to all CO busy", .pme_long_desc = "A Read/Claim dispatch was rejected because all Castout machines were busy.", }, [ POWER5_PME_PM_FPU0_STALL3 ] = { .pme_name = "PM_FPU0_STALL3", .pme_code = 0x20e1, .pme_short_desc = "FPU0 stalled in pipe3", .pme_long_desc = "FPU0 has generated a stall in pipe3 due to overflow, underflow, massive cancel, convert to integer (sometimes), or convert from integer (always).", }, [ POWER5_PME_PM_GPR_MAP_FULL_CYC ] = { .pme_name = "PM_GPR_MAP_FULL_CYC", .pme_code = 0x130e5, .pme_short_desc = "Cycles GPR mapper full", .pme_long_desc = "The General Purpose Register mapper cannot accept any more groups. This condition will prevent dispatch groups from being dispatched. This event only indicates that the mapper was full, not that dispatch was prevented.", }, [ POWER5_PME_PM_TB_BIT_TRANS ] = { .pme_name = "PM_TB_BIT_TRANS", .pme_code = 0x100018, .pme_short_desc = "Time Base bit transition", .pme_long_desc = "When the selected time base bit (as specified in MMCR0[TBSEL])transitions from 0 to 1 ", }, [ POWER5_PME_PM_MRK_LSU_FLUSH_LRQ ] = { .pme_name = "PM_MRK_LSU_FLUSH_LRQ", .pme_code = 0x381088, .pme_short_desc = "Marked LRQ flushes", .pme_long_desc = "A marked load was flushed because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.", }, [ POWER5_PME_PM_FPU0_STF ] = { .pme_name = "PM_FPU0_STF", .pme_code = 0x20e2, .pme_short_desc = "FPU0 executed store instruction", .pme_long_desc = "FPU0 has executed a Floating Point Store instruction.", }, [ POWER5_PME_PM_MRK_DTLB_MISS ] = { .pme_name = "PM_MRK_DTLB_MISS", .pme_code = 0xc50c6, .pme_short_desc = "Marked Data TLB misses", .pme_long_desc = "Data TLB references by a marked instruction that missed the TLB (all page sizes).", }, [ POWER5_PME_PM_FPU1_FMA ] = { .pme_name = "PM_FPU1_FMA", .pme_code = 0xc5, .pme_short_desc = "FPU1 executed multiply-add instruction", .pme_long_desc = "The floating point unit has executed a multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs.", }, [ POWER5_PME_PM_L2SA_MOD_TAG ] = { .pme_name = "PM_L2SA_MOD_TAG", .pme_code = 0x720e0, .pme_short_desc = "L2 slice A transition from modified to tagged", .pme_long_desc = "A cache line in the local L2 directory made a state transition from the Modified state to the Tagged state. This transition was caused by a read snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A, B, and C.", }, [ POWER5_PME_PM_LSU1_FLUSH_ULD ] = { .pme_name = "PM_LSU1_FLUSH_ULD", .pme_code = 0xc00c4, .pme_short_desc = "LSU1 unaligned load flushes", .pme_long_desc = "A load was flushed from unit 1 because it was unaligned (crossed a 64 byte boundary, or 32 byte if it missed the L1).", }, [ POWER5_PME_PM_MRK_LSU0_FLUSH_UST ] = { .pme_name = "PM_MRK_LSU0_FLUSH_UST", .pme_code = 0x810c1, .pme_short_desc = "LSU0 marked unaligned store flushes", .pme_long_desc = "A marked store was flushed from unit 0 because it was unaligned", }, [ POWER5_PME_PM_MRK_INST_FIN ] = { .pme_name = "PM_MRK_INST_FIN", .pme_code = 0x300005, .pme_short_desc = "Marked instruction finished", .pme_long_desc = "One of the execution units finished a marked instruction. Instructions that finish may not necessary complete", }, [ POWER5_PME_PM_FPU0_FULL_CYC ] = { .pme_name = "PM_FPU0_FULL_CYC", .pme_code = 0x100c3, .pme_short_desc = "Cycles FPU0 issue queue full", .pme_long_desc = "The issue queue for FPU0 cannot accept any more instruction. Dispatch to this issue queue is stopped.", }, [ POWER5_PME_PM_LSU_LRQ_S0_ALLOC ] = { .pme_name = "PM_LSU_LRQ_S0_ALLOC", .pme_code = 0xc20e6, .pme_short_desc = "LRQ slot 0 allocated", .pme_long_desc = "LRQ slot zero was allocated", }, [ POWER5_PME_PM_MRK_LSU1_FLUSH_ULD ] = { .pme_name = "PM_MRK_LSU1_FLUSH_ULD", .pme_code = 0x810c4, .pme_short_desc = "LSU1 marked unaligned load flushes", .pme_long_desc = "A marked load was flushed from unit 1 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)", }, [ POWER5_PME_PM_MRK_DTLB_REF ] = { .pme_name = "PM_MRK_DTLB_REF", .pme_code = 0x1c4090, .pme_short_desc = "Marked Data TLB reference", .pme_long_desc = "Total number of Data TLB references by a marked instruction for all page sizes. Page size is determined at TLB reload time.", }, [ POWER5_PME_PM_BR_UNCOND ] = { .pme_name = "PM_BR_UNCOND", .pme_code = 0x123087, .pme_short_desc = "Unconditional branch", .pme_long_desc = "An unconditional branch was executed.", }, [ POWER5_PME_PM_THRD_SEL_OVER_L2MISS ] = { .pme_name = "PM_THRD_SEL_OVER_L2MISS", .pme_code = 0x410c3, .pme_short_desc = "Thread selection overrides caused by L2 misses", .pme_long_desc = "Thread selection was overridden because one thread was had a L2 miss pending.", }, [ POWER5_PME_PM_L2SB_SHR_INV ] = { .pme_name = "PM_L2SB_SHR_INV", .pme_code = 0x710c1, .pme_short_desc = "L2 slice B transition from shared to invalid", .pme_long_desc = "A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L, or Tagged) to the Invalid state. This transition was caused by any external snoop request. The event is provided on each of the three slices A, B, and C. NOTE: For this event to be useful the tablewalk duration event should also be counted.", }, [ POWER5_PME_PM_MEM_LO_PRIO_WR_CMPL ] = { .pme_name = "PM_MEM_LO_PRIO_WR_CMPL", .pme_code = 0x736e6, .pme_short_desc = "Low priority write completed", .pme_long_desc = "A memory write, which was not upgraded to high priority, completed. This event is sent from the Memory Controller clock domain and must be scaled accordingly", }, [ POWER5_PME_PM_L3SC_MOD_TAG ] = { .pme_name = "PM_L3SC_MOD_TAG", .pme_code = 0x720e5, .pme_short_desc = "L3 slice C transition from modified to TAG", .pme_long_desc = "L3 snooper detects someone doing a read to a line that is truly M in this L3(i.e. L3 going M->T or M->I(go_Mu case); Mu|Me are not included since they are formed due to a prev read op). Tx is not included since it is considered shared at this point.", }, [ POWER5_PME_PM_MRK_ST_MISS_L1 ] = { .pme_name = "PM_MRK_ST_MISS_L1", .pme_code = 0x820e3, .pme_short_desc = "Marked L1 D cache store misses", .pme_long_desc = "A marked store missed the dcache", }, [ POWER5_PME_PM_GRP_DISP_SUCCESS ] = { .pme_name = "PM_GRP_DISP_SUCCESS", .pme_code = 0x300002, .pme_short_desc = "Group dispatch success", .pme_long_desc = "Number of groups sucessfully dispatched (not rejected)", }, [ POWER5_PME_PM_THRD_PRIO_DIFF_1or2_CYC ] = { .pme_name = "PM_THRD_PRIO_DIFF_1or2_CYC", .pme_code = 0x430e4, .pme_short_desc = "Cycles thread priority difference is 1 or 2", .pme_long_desc = "Cycles when this thread's priority is higher than the other thread's priority by 1 or 2.", }, [ POWER5_PME_PM_IC_DEMAND_L2_BHT_REDIRECT ] = { .pme_name = "PM_IC_DEMAND_L2_BHT_REDIRECT", .pme_code = 0x230e0, .pme_short_desc = "L2 I cache demand request due to BHT redirect", .pme_long_desc = "A demand (not prefetch) miss to the instruction cache was sent to the L2 as a result of a branch prediction redirect (CR mispredict).", }, [ POWER5_PME_PM_MEM_WQ_DISP_Q8to15 ] = { .pme_name = "PM_MEM_WQ_DISP_Q8to15", .pme_code = 0x733e6, .pme_short_desc = "Memory write queue dispatched to queues 8-15", .pme_long_desc = "A memory operation was dispatched to a write queue in the range between 8 and 15. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", }, [ POWER5_PME_PM_FPU0_SINGLE ] = { .pme_name = "PM_FPU0_SINGLE", .pme_code = 0x20e3, .pme_short_desc = "FPU0 executed single precision instruction", .pme_long_desc = "FPU0 has executed a single precision instruction.", }, [ POWER5_PME_PM_LSU_DERAT_MISS ] = { .pme_name = "PM_LSU_DERAT_MISS", .pme_code = 0x280090, .pme_short_desc = "DERAT misses", .pme_long_desc = "Total D-ERAT Misses. Requests that miss the Derat are rejected and retried until the request hits in the Erat. This may result in multiple erat misses for the same instruction. Combined Unit 0 + 1.", }, [ POWER5_PME_PM_THRD_PRIO_1_CYC ] = { .pme_name = "PM_THRD_PRIO_1_CYC", .pme_code = 0x420e0, .pme_short_desc = "Cycles thread running at priority level 1", .pme_long_desc = "Cycles this thread was running at priority level 1. Priority level 1 is the lowest and indicates the thread is sleeping.", }, [ POWER5_PME_PM_L2SC_RCST_DISP_FAIL_OTHER ] = { .pme_name = "PM_L2SC_RCST_DISP_FAIL_OTHER", .pme_code = 0x732e2, .pme_short_desc = "L2 slice C RC store dispatch attempt failed due to other reasons", .pme_long_desc = "A Read/Claim dispatch for a store failed for some reason other than Full or Collision conditions. Rejected dispatches do not count because they have not yet been attempted.", }, [ POWER5_PME_PM_FPU1_FEST ] = { .pme_name = "PM_FPU1_FEST", .pme_code = 0x10c6, .pme_short_desc = "FPU1 executed FEST instruction", .pme_long_desc = "FPU1 has executed an estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ.", }, [ POWER5_PME_PM_FAB_HOLDtoVN_EMPTY ] = { .pme_name = "PM_FAB_HOLDtoVN_EMPTY", .pme_code = 0x721e7, .pme_short_desc = "Hold buffer to VN empty", .pme_long_desc = "Fabric cycles when the Vertical Node out hold-buffers are emtpy. The signal is delivered at FBC speed and the count must be scaled accordingly.", }, [ POWER5_PME_PM_SNOOP_RD_RETRY_RQ ] = { .pme_name = "PM_SNOOP_RD_RETRY_RQ", .pme_code = 0x705c6, .pme_short_desc = "Snoop read retry due to collision with active read queue", .pme_long_desc = "A snoop request for a read from memory was retried because it matched the cache line of an active read. The snoop request is retried because the L2 may be able to source data via intervention for the 2nd read faster than the MC. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", }, [ POWER5_PME_PM_SNOOP_DCLAIM_RETRY_QFULL ] = { .pme_name = "PM_SNOOP_DCLAIM_RETRY_QFULL", .pme_code = 0x720e6, .pme_short_desc = "Snoop dclaim/flush retry due to write/dclaim queues full", .pme_long_desc = "The memory controller A memory write was dispatched to a write queue. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", }, [ POWER5_PME_PM_MRK_DATA_FROM_L25_SHR_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L25_SHR_CYC", .pme_code = 0x2c70a2, .pme_short_desc = "Marked load latency from L2.5 shared", .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.", }, [ POWER5_PME_PM_MRK_ST_CMPL_INT ] = { .pme_name = "PM_MRK_ST_CMPL_INT", .pme_code = 0x300003, .pme_short_desc = "Marked store completed with intervention", .pme_long_desc = "A marked store previously sent to the memory subsystem completed (data home) after requiring intervention", }, [ POWER5_PME_PM_FLUSH_BR_MPRED ] = { .pme_name = "PM_FLUSH_BR_MPRED", .pme_code = 0x110c6, .pme_short_desc = "Flush caused by branch mispredict", .pme_long_desc = "A flush was caused by a branch mispredict.", }, [ POWER5_PME_PM_L2SB_RCLD_DISP_FAIL_ADDR ] = { .pme_name = "PM_L2SB_RCLD_DISP_FAIL_ADDR", .pme_code = 0x711c1, .pme_short_desc = "L2 slice B RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ", .pme_long_desc = "A Read/Claim dispatch for a load failed because of an address conflict. Two RC machines will never both work on the same line or line in the same congruence class at the same time.", }, [ POWER5_PME_PM_FPU_STF ] = { .pme_name = "PM_FPU_STF", .pme_code = 0x202090, .pme_short_desc = "FPU executed store instruction", .pme_long_desc = "FPU has executed a store instruction. Combined Unit 0 + Unit 1.", }, [ POWER5_PME_PM_CMPLU_STALL_FPU ] = { .pme_name = "PM_CMPLU_STALL_FPU", .pme_code = 0x411098, .pme_short_desc = "Completion stall caused by FPU instruction", .pme_long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes was a floating point instruction.", }, [ POWER5_PME_PM_THRD_PRIO_DIFF_minus1or2_CYC ] = { .pme_name = "PM_THRD_PRIO_DIFF_minus1or2_CYC", .pme_code = 0x430e2, .pme_short_desc = "Cycles thread priority difference is -1 or -2", .pme_long_desc = "Cycles when this thread's priority is lower than the other thread's priority by 1 or 2.", }, [ POWER5_PME_PM_GCT_NOSLOT_CYC ] = { .pme_name = "PM_GCT_NOSLOT_CYC", .pme_code = 0x100004, .pme_short_desc = "Cycles no GCT slot allocated", .pme_long_desc = "Cycles when the Global Completion Table has no slots from this thread.", }, [ POWER5_PME_PM_FXU0_BUSY_FXU1_IDLE ] = { .pme_name = "PM_FXU0_BUSY_FXU1_IDLE", .pme_code = 0x300012, .pme_short_desc = "FXU0 busy FXU1 idle", .pme_long_desc = "FXU0 is busy while FXU1 was idle", }, [ POWER5_PME_PM_PTEG_FROM_L35_SHR ] = { .pme_name = "PM_PTEG_FROM_L35_SHR", .pme_code = 0x18309e, .pme_short_desc = "PTEG loaded from L3.5 shared", .pme_long_desc = "A Page Table Entry was loaded into the TLB with shared (S) data from the L3 of a chip on the same module as this processor is located, due to a demand load.", }, [ POWER5_PME_PM_MRK_LSU_FLUSH_UST ] = { .pme_name = "PM_MRK_LSU_FLUSH_UST", .pme_code = 0x381090, .pme_short_desc = "Marked unaligned store flushes", .pme_long_desc = "A marked store was flushed because it was unaligned", }, [ POWER5_PME_PM_L3SA_HIT ] = { .pme_name = "PM_L3SA_HIT", .pme_code = 0x711c3, .pme_short_desc = "L3 slice A hits", .pme_long_desc = "Number of attempts made by this chip cores that resulted in an L3 hit. Reported per L3 slice", }, [ POWER5_PME_PM_MRK_DATA_FROM_L25_SHR ] = { .pme_name = "PM_MRK_DATA_FROM_L25_SHR", .pme_code = 0x1c7097, .pme_short_desc = "Marked data loaded from L2.5 shared", .pme_long_desc = "The processor's Data Cache was reloaded with shared (T or SL) data from the L2 of a chip on the same module as this processor is located due to a marked load.", }, [ POWER5_PME_PM_L2SB_RCST_DISP_FAIL_ADDR ] = { .pme_name = "PM_L2SB_RCST_DISP_FAIL_ADDR", .pme_code = 0x712c1, .pme_short_desc = "L2 slice B RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ", .pme_long_desc = "A Read/Claim dispatch for a store failed because of an address conflict. Two RC machines will never both work on the same line or line in the same congruence class at the same time.", }, [ POWER5_PME_PM_MRK_DATA_FROM_L35_SHR ] = { .pme_name = "PM_MRK_DATA_FROM_L35_SHR", .pme_code = 0x1c709e, .pme_short_desc = "Marked data loaded from L3.5 shared", .pme_long_desc = "The processor's Data Cache was reloaded with shared (S) data from the L3 of a chip on the same module as this processor is located due to a marked load.", }, [ POWER5_PME_PM_IERAT_XLATE_WR ] = { .pme_name = "PM_IERAT_XLATE_WR", .pme_code = 0x220e7, .pme_short_desc = "Translation written to ierat", .pme_long_desc = "An entry was written into the IERAT as a result of an IERAT miss. This event can be used to count IERAT misses. An ERAT miss that are later ignored will not be counted unless the ERAT is written before the instruction stream is changed.", }, [ POWER5_PME_PM_L2SA_ST_REQ ] = { .pme_name = "PM_L2SA_ST_REQ", .pme_code = 0x723e0, .pme_short_desc = "L2 slice A store requests", .pme_long_desc = "A store request as seen at the L2 directory has been made from the core. Stores are counted after gathering in the L2 store queues. The event is provided on each of the three slices A, B, and C.", }, [ POWER5_PME_PM_THRD_SEL_T1 ] = { .pme_name = "PM_THRD_SEL_T1", .pme_code = 0x410c1, .pme_short_desc = "Decode selected thread 1", .pme_long_desc = "Thread selection picked thread 1 for decode.", }, [ POWER5_PME_PM_IC_DEMAND_L2_BR_REDIRECT ] = { .pme_name = "PM_IC_DEMAND_L2_BR_REDIRECT", .pme_code = 0x230e1, .pme_short_desc = "L2 I cache demand request due to branch redirect", .pme_long_desc = "A demand (not prefetch) miss to the instruction cache was sent to the L2 as a result of a branch prediction redirect (either ALL mispredicted or Target).", }, [ POWER5_PME_PM_INST_FROM_LMEM ] = { .pme_name = "PM_INST_FROM_LMEM", .pme_code = 0x222086, .pme_short_desc = "Instruction fetched from local memory", .pme_long_desc = "An instruction fetch group was fetched from memory attached to the same module this proccessor is located on. Fetch groups can contain up to 8 instructions", }, [ POWER5_PME_PM_FPU0_1FLOP ] = { .pme_name = "PM_FPU0_1FLOP", .pme_code = 0xc3, .pme_short_desc = "FPU0 executed add, mult, sub, cmp or sel instruction", .pme_long_desc = "The floating point unit has executed an add, mult, sub, compare, fsel, fneg, fabs, fnabs, fres, or frsqrte kind of instruction. These are single FLOP operations.", }, [ POWER5_PME_PM_MRK_DATA_FROM_L35_SHR_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L35_SHR_CYC", .pme_code = 0x2c70a6, .pme_short_desc = "Marked load latency from L3.5 shared", .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.", }, [ POWER5_PME_PM_PTEG_FROM_L2 ] = { .pme_name = "PM_PTEG_FROM_L2", .pme_code = 0x183087, .pme_short_desc = "PTEG loaded from L2", .pme_long_desc = "A Page Table Entry was loaded into the TLB from the local L2 due to a demand load", }, [ POWER5_PME_PM_MEM_PW_CMPL ] = { .pme_name = "PM_MEM_PW_CMPL", .pme_code = 0x724e6, .pme_short_desc = "Memory partial-write completed", .pme_long_desc = "Number of Partial Writes completed. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", }, [ POWER5_PME_PM_THRD_PRIO_DIFF_minus5or6_CYC ] = { .pme_name = "PM_THRD_PRIO_DIFF_minus5or6_CYC", .pme_code = 0x430e0, .pme_short_desc = "Cycles thread priority difference is -5 or -6", .pme_long_desc = "Cycles when this thread's priority is lower than the other thread's priority by 5 or 6.", }, [ POWER5_PME_PM_L2SB_RCLD_DISP_FAIL_OTHER ] = { .pme_name = "PM_L2SB_RCLD_DISP_FAIL_OTHER", .pme_code = 0x731e1, .pme_short_desc = "L2 slice B RC load dispatch attempt failed due to other reasons", .pme_long_desc = "A Read/Claim dispatch for a load failed for some reason other than Full or Collision conditions.", }, [ POWER5_PME_PM_FPU0_FIN ] = { .pme_name = "PM_FPU0_FIN", .pme_code = 0x10c3, .pme_short_desc = "FPU0 produced a result", .pme_long_desc = "FPU0 finished, produced a result. This only indicates finish, not completion. Floating Point Stores are included in this count but not Floating Point Loads.", }, [ POWER5_PME_PM_MRK_DTLB_MISS_4K ] = { .pme_name = "PM_MRK_DTLB_MISS_4K", .pme_code = 0xc40c1, .pme_short_desc = "Marked Data TLB misses for 4K page", .pme_long_desc = "Data TLB references to 4KB pages by a marked instruction that missed the TLB. Page size is determined at TLB reload time.", }, [ POWER5_PME_PM_L3SC_SHR_INV ] = { .pme_name = "PM_L3SC_SHR_INV", .pme_code = 0x710c5, .pme_short_desc = "L3 slice C transition from shared to invalid", .pme_long_desc = "L3 snooper detects someone doing a store to a line that is Sx in this L3(i.e. invalidate hit SX and dispatched).", }, [ POWER5_PME_PM_GRP_BR_REDIR ] = { .pme_name = "PM_GRP_BR_REDIR", .pme_code = 0x120e6, .pme_short_desc = "Group experienced branch redirect", .pme_long_desc = "Number of groups, counted at dispatch, that have encountered a branch redirect. Every group constructed from a fetch group that has been redirected will count.", }, [ POWER5_PME_PM_L2SC_RCLD_DISP_FAIL_RC_FULL ] = { .pme_name = "PM_L2SC_RCLD_DISP_FAIL_RC_FULL", .pme_code = 0x721e2, .pme_short_desc = "L2 slice C RC load dispatch attempt failed due to all RC full", .pme_long_desc = "A Read/Claim dispatch for a load failed because all RC machines are busy.", }, [ POWER5_PME_PM_MRK_LSU_FLUSH_SRQ ] = { .pme_name = "PM_MRK_LSU_FLUSH_SRQ", .pme_code = 0x481088, .pme_short_desc = "Marked SRQ lhs flushes", .pme_long_desc = "A marked store was flushed because younger load hits and older store that is already in the SRQ or in the same group.", }, [ POWER5_PME_PM_PTEG_FROM_L275_SHR ] = { .pme_name = "PM_PTEG_FROM_L275_SHR", .pme_code = 0x383097, .pme_short_desc = "PTEG loaded from L2.75 shared", .pme_long_desc = "A Page Table Entry was loaded into the TLB with shared (T) data from the L2 on a different module than this processor is located due to a demand load.", }, [ POWER5_PME_PM_L2SB_RCLD_DISP_FAIL_RC_FULL ] = { .pme_name = "PM_L2SB_RCLD_DISP_FAIL_RC_FULL", .pme_code = 0x721e1, .pme_short_desc = "L2 slice B RC load dispatch attempt failed due to all RC full", .pme_long_desc = "A Read/Claim dispatch for a load failed because all RC machines are busy.", }, [ POWER5_PME_PM_SNOOP_RD_RETRY_WQ ] = { .pme_name = "PM_SNOOP_RD_RETRY_WQ", .pme_code = 0x715c6, .pme_short_desc = "Snoop read retry due to collision with active write queue", .pme_long_desc = "A snoop request for a read from memory was retried because it matched the cache line of an active write. The snoop request is retried and the active write is changed to high priority. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", }, [ POWER5_PME_PM_LSU0_NCLD ] = { .pme_name = "PM_LSU0_NCLD", .pme_code = 0xc50c1, .pme_short_desc = "LSU0 non-cacheable loads", .pme_long_desc = "A non-cacheable load was executed by unit 0.", }, [ POWER5_PME_PM_FAB_DCLAIM_RETRIED ] = { .pme_name = "PM_FAB_DCLAIM_RETRIED", .pme_code = 0x730e7, .pme_short_desc = "dclaim retried", .pme_long_desc = "A DCLAIM command was retried. Each chip reports its own counts. The signal is delivered at FBC speed and the count must be scaled accordingly.", }, [ POWER5_PME_PM_LSU1_BUSY_REJECT ] = { .pme_name = "PM_LSU1_BUSY_REJECT", .pme_code = 0xc20e7, .pme_short_desc = "LSU1 busy due to reject", .pme_long_desc = "Total cycles the Load Store Unit 1 is busy rejecting instructions.", }, [ POWER5_PME_PM_FXLS0_FULL_CYC ] = { .pme_name = "PM_FXLS0_FULL_CYC", .pme_code = 0x110c0, .pme_short_desc = "Cycles FXU0/LS0 queue full", .pme_long_desc = "The issue queue that feeds the Fixed Point unit 0 / Load Store Unit 0 is full. This condition will prevent dispatch groups from being dispatched. This event only indicates that the queue was full, not that dispatch was prevented.", }, [ POWER5_PME_PM_FPU0_FEST ] = { .pme_name = "PM_FPU0_FEST", .pme_code = 0x10c2, .pme_short_desc = "FPU0 executed FEST instruction", .pme_long_desc = "FPU0 has executed an estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ. ", }, [ POWER5_PME_PM_DTLB_REF_16M ] = { .pme_name = "PM_DTLB_REF_16M", .pme_code = 0xc40c6, .pme_short_desc = "Data TLB reference for 16M page", .pme_long_desc = "Data TLB references for 16MB pages. Includes hits + misses.", }, [ POWER5_PME_PM_L2SC_RCLD_DISP_FAIL_ADDR ] = { .pme_name = "PM_L2SC_RCLD_DISP_FAIL_ADDR", .pme_code = 0x711c2, .pme_short_desc = "L2 slice C RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ", .pme_long_desc = "A Read/Claim dispatch for a load failed because of an address conflict. Two RC machines will never both work on the same line or line in the same congruence class at the same time.", }, [ POWER5_PME_PM_LSU0_REJECT_ERAT_MISS ] = { .pme_name = "PM_LSU0_REJECT_ERAT_MISS", .pme_code = 0xc60e3, .pme_short_desc = "LSU0 reject due to ERAT miss", .pme_long_desc = "Total cycles the Load Store Unit 0 is busy rejecting instructions due to an ERAT miss. Requests that miss the Derat are rejected and retried until the request hits in the Erat.", }, [ POWER5_PME_PM_DATA_FROM_L25_MOD ] = { .pme_name = "PM_DATA_FROM_L25_MOD", .pme_code = 0x2c3097, .pme_short_desc = "Data loaded from L2.5 modified", .pme_long_desc = "The processor's Data Cache was reloaded with modified (M) data from the L2 of a chip on the same module as this processor is located due to a demand load.", }, [ POWER5_PME_PM_GCT_USAGE_60to79_CYC ] = { .pme_name = "PM_GCT_USAGE_60to79_CYC", .pme_code = 0x20001f, .pme_short_desc = "Cycles GCT 60-79% full", .pme_long_desc = "Cycles when the Global Completion Table has between 60% and 70% of its slots used. The GCT has 20 entries shared between threads.", }, [ POWER5_PME_PM_DATA_FROM_L375_MOD ] = { .pme_name = "PM_DATA_FROM_L375_MOD", .pme_code = 0x1c30a7, .pme_short_desc = "Data loaded from L3.75 modified", .pme_long_desc = "The processor's Data Cache was reloaded with modified (M) data from the L3 of a chip on the same module as this processor is located due to a demand load.", }, [ POWER5_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC ] = { .pme_name = "PM_LSU_LMQ_SRQ_EMPTY_CYC", .pme_code = 0x200015, .pme_short_desc = "Cycles LMQ and SRQ empty", .pme_long_desc = "Cycles when both the LMQ and SRQ are empty (LSU is idle)", }, [ POWER5_PME_PM_LSU0_REJECT_RELOAD_CDF ] = { .pme_name = "PM_LSU0_REJECT_RELOAD_CDF", .pme_code = 0xc60e2, .pme_short_desc = "LSU0 reject due to reload CDF or tag update collision", .pme_long_desc = "Total cycles the Load Store Unit 0 is busy rejecting instructions because of Critical Data Forward. When critical data arrives from the storage system it is formatted and immediately forwarded, bypassing the data cache, to the destination register using the result bus. Any instruction the requires the result bus in the same cycle is rejected. Tag update rejects are caused when an instruction requires access to the Dcache directory or ERAT in the same system when they are being updated.", }, [ POWER5_PME_PM_0INST_FETCH ] = { .pme_name = "PM_0INST_FETCH", .pme_code = 0x42208d, .pme_short_desc = "No instructions fetched", .pme_long_desc = "No instructions were fetched this cycles (due to IFU hold, redirect, or icache miss)", }, [ POWER5_PME_PM_LSU1_REJECT_RELOAD_CDF ] = { .pme_name = "PM_LSU1_REJECT_RELOAD_CDF", .pme_code = 0xc60e6, .pme_short_desc = "LSU1 reject due to reload CDF or tag update collision", .pme_long_desc = "Total cycles the Load Store Unit 1 is busy rejecting instructions because of Critical Data Forward. When critical data arrives from the storage system it is formatted and immediately forwarded, bypassing the data cache, to the destination register using the result bus. Any instruction the requires the result bus in the same cycle is rejected. Tag update rejects are caused when an instruction requires access to the Dcache directory or ERAT in the same system when they are being updated.", }, [ POWER5_PME_PM_L1_PREF ] = { .pme_name = "PM_L1_PREF", .pme_code = 0xc70e7, .pme_short_desc = "L1 cache data prefetches", .pme_long_desc = "A request to prefetch data into the L1 was made", }, [ POWER5_PME_PM_MEM_WQ_DISP_Q0to7 ] = { .pme_name = "PM_MEM_WQ_DISP_Q0to7", .pme_code = 0x723e6, .pme_short_desc = "Memory write queue dispatched to queues 0-7", .pme_long_desc = "A memory operation was dispatched to a write queue in the range between 0 and 7. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", }, [ POWER5_PME_PM_MRK_DATA_FROM_LMEM_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_LMEM_CYC", .pme_code = 0x4c70a0, .pme_short_desc = "Marked load latency from local memory", .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.", }, [ POWER5_PME_PM_BRQ_FULL_CYC ] = { .pme_name = "PM_BRQ_FULL_CYC", .pme_code = 0x100c5, .pme_short_desc = "Cycles branch queue full", .pme_long_desc = "Cycles when the issue queue that feeds the branch unit is full. This condition will prevent dispatch groups from being dispatched. This event only indicates that the queue was full, not that dispatch was prevented.", }, [ POWER5_PME_PM_GRP_IC_MISS_NONSPEC ] = { .pme_name = "PM_GRP_IC_MISS_NONSPEC", .pme_code = 0x112099, .pme_short_desc = "Group experienced non-speculative I cache miss", .pme_long_desc = "Number of groups, counted at completion, that have encountered an instruction cache miss.", }, [ POWER5_PME_PM_PTEG_FROM_L275_MOD ] = { .pme_name = "PM_PTEG_FROM_L275_MOD", .pme_code = 0x1830a3, .pme_short_desc = "PTEG loaded from L2.75 modified", .pme_long_desc = "A Page Table Entry was loaded into the TLB with modified (M) data from the L2 on a different module than this processor is located due to a demand load. ", }, [ POWER5_PME_PM_MRK_LD_MISS_L1_LSU0 ] = { .pme_name = "PM_MRK_LD_MISS_L1_LSU0", .pme_code = 0x820e0, .pme_short_desc = "LSU0 marked L1 D cache load misses", .pme_long_desc = "Load references that miss the Level 1 Data cache, by LSU0.", }, [ POWER5_PME_PM_MRK_DATA_FROM_L375_SHR_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L375_SHR_CYC", .pme_code = 0x2c70a7, .pme_short_desc = "Marked load latency from L3.75 shared", .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.", }, [ POWER5_PME_PM_LSU_FLUSH ] = { .pme_name = "PM_LSU_FLUSH", .pme_code = 0x110c5, .pme_short_desc = "Flush initiated by LSU", .pme_long_desc = "A flush was initiated by the Load Store Unit", }, [ POWER5_PME_PM_DATA_FROM_L3 ] = { .pme_name = "PM_DATA_FROM_L3", .pme_code = 0x1c308e, .pme_short_desc = "Data loaded from L3", .pme_long_desc = "The processor's Data Cache was reloaded from the local L3 due to a demand load.", }, [ POWER5_PME_PM_INST_FROM_L2 ] = { .pme_name = "PM_INST_FROM_L2", .pme_code = 0x122086, .pme_short_desc = "Instruction fetched from L2", .pme_long_desc = "An instruction fetch group was fetched from L2. Fetch Groups can contain up to 8 instructions", }, [ POWER5_PME_PM_PMC2_OVERFLOW ] = { .pme_name = "PM_PMC2_OVERFLOW", .pme_code = 0x30000a, .pme_short_desc = "PMC2 Overflow", .pme_long_desc = "Overflows from PMC2 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.", }, [ POWER5_PME_PM_FPU0_DENORM ] = { .pme_name = "PM_FPU0_DENORM", .pme_code = 0x20e0, .pme_short_desc = "FPU0 received denormalized data", .pme_long_desc = "FPU0 has encountered a denormalized operand. ", }, [ POWER5_PME_PM_FPU1_FMOV_FEST ] = { .pme_name = "PM_FPU1_FMOV_FEST", .pme_code = 0x10c4, .pme_short_desc = "FPU1 executed FMOV or FEST instructions", .pme_long_desc = "FPU1 has executed a move kind of instruction or one of the estimate instructions. This could be fmr*, fneg*, fabs*, fnabs* , fres* or frsqrte* where XYZ* means XYZ or XYZ.", }, [ POWER5_PME_PM_INST_FETCH_CYC ] = { .pme_name = "PM_INST_FETCH_CYC", .pme_code = 0x220e4, .pme_short_desc = "Cycles at least 1 instruction fetched", .pme_long_desc = "Cycles when at least one instruction was sent from the fetch unit to the decode unit.", }, [ POWER5_PME_PM_LSU_LDF ] = { .pme_name = "PM_LSU_LDF", .pme_code = 0x4c5090, .pme_short_desc = "LSU executed Floating Point load instruction", .pme_long_desc = "LSU executed Floating Point load instruction. Combined Unit 0 + 1.", }, [ POWER5_PME_PM_INST_DISP ] = { .pme_name = "PM_INST_DISP", .pme_code = 0x300009, .pme_short_desc = "Instructions dispatched", .pme_long_desc = "Number of PowerPC instructions successfully dispatched.", }, [ POWER5_PME_PM_DATA_FROM_L25_SHR ] = { .pme_name = "PM_DATA_FROM_L25_SHR", .pme_code = 0x1c3097, .pme_short_desc = "Data loaded from L2.5 shared", .pme_long_desc = "The processor's Data Cache was reloaded with shared (T or SL) data from the L2 of a chip on the same module as this processor is located due to a demand load.", }, [ POWER5_PME_PM_L1_DCACHE_RELOAD_VALID ] = { .pme_name = "PM_L1_DCACHE_RELOAD_VALID", .pme_code = 0xc30e4, .pme_short_desc = "L1 reload data source valid", .pme_long_desc = "The data source information is valid,the data cache has been reloaded. Prior to POWER5+ this included data cache reloads due to prefetch activity. With POWER5+ this now only includes reloads due to demand loads.", }, [ POWER5_PME_PM_MEM_WQ_DISP_DCLAIM ] = { .pme_name = "PM_MEM_WQ_DISP_DCLAIM", .pme_code = 0x713c6, .pme_short_desc = "Memory write queue dispatched due to dclaim/flush", .pme_long_desc = "A memory dclaim or flush operation was dispatched to a write queue. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", }, [ POWER5_PME_PM_FPU_FULL_CYC ] = { .pme_name = "PM_FPU_FULL_CYC", .pme_code = 0x110090, .pme_short_desc = "Cycles FPU issue queue full", .pme_long_desc = "Cycles when one or both FPU issue queues are full. Combined Unit 0 + 1. Use with caution since this is the sum of cycles when Unit 0 was full plus Unit 1 full. It does not indicate when both units were full.", }, [ POWER5_PME_PM_MRK_GRP_ISSUED ] = { .pme_name = "PM_MRK_GRP_ISSUED", .pme_code = 0x100015, .pme_short_desc = "Marked group issued", .pme_long_desc = "A sampled instruction was issued.", }, [ POWER5_PME_PM_THRD_PRIO_3_CYC ] = { .pme_name = "PM_THRD_PRIO_3_CYC", .pme_code = 0x420e2, .pme_short_desc = "Cycles thread running at priority level 3", .pme_long_desc = "Cycles this thread was running at priority level 3.", }, [ POWER5_PME_PM_FPU_FMA ] = { .pme_name = "PM_FPU_FMA", .pme_code = 0x200088, .pme_short_desc = "FPU executed multiply-add instruction", .pme_long_desc = "This signal is active for one cycle when FPU is executing multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs. Combined Unit 0 + Unit 1.", }, [ POWER5_PME_PM_INST_FROM_L35_MOD ] = { .pme_name = "PM_INST_FROM_L35_MOD", .pme_code = 0x22209d, .pme_short_desc = "Instruction fetched from L3.5 modified", .pme_long_desc = "An instruction fetch group was fetched with modified (M) data from the L3 of a chip on the same module as this processor is located. Fetch groups can contain up to 8 instructions", }, [ POWER5_PME_PM_MRK_CRU_FIN ] = { .pme_name = "PM_MRK_CRU_FIN", .pme_code = 0x400005, .pme_short_desc = "Marked instruction CRU processing finished", .pme_long_desc = "The Condition Register Unit finished a marked instruction. Instructions that finish may not necessary complete.", }, [ POWER5_PME_PM_SNOOP_WR_RETRY_WQ ] = { .pme_name = "PM_SNOOP_WR_RETRY_WQ", .pme_code = 0x716c6, .pme_short_desc = "Snoop write/dclaim retry due to collision with active write queue", .pme_long_desc = "A snoop request for a write or dclaim to memory was retried because it matched the cache line of an active write. The snoop request is retried and the active write is changed to high priority. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", }, [ POWER5_PME_PM_CMPLU_STALL_REJECT ] = { .pme_name = "PM_CMPLU_STALL_REJECT", .pme_code = 0x41109a, .pme_short_desc = "Completion stall caused by reject", .pme_long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes suffered a load/store reject. This is a subset of PM_CMPLU_STALL_LSU.", }, [ POWER5_PME_PM_LSU1_REJECT_ERAT_MISS ] = { .pme_name = "PM_LSU1_REJECT_ERAT_MISS", .pme_code = 0xc60e7, .pme_short_desc = "LSU1 reject due to ERAT miss", .pme_long_desc = "Total cycles the Load Store Unit 1 is busy rejecting instructions due to an ERAT miss. Requests that miss the Derat are rejected and retried until the request hits in the Erat.", }, [ POWER5_PME_PM_MRK_FXU_FIN ] = { .pme_name = "PM_MRK_FXU_FIN", .pme_code = 0x200014, .pme_short_desc = "Marked instruction FXU processing finished", .pme_long_desc = "One of the Fixed Point Units finished a marked instruction. Instructions that finish may not necessary complete.", }, [ POWER5_PME_PM_L2SB_RCST_DISP_FAIL_OTHER ] = { .pme_name = "PM_L2SB_RCST_DISP_FAIL_OTHER", .pme_code = 0x732e1, .pme_short_desc = "L2 slice B RC store dispatch attempt failed due to other reasons", .pme_long_desc = "A Read/Claim dispatch for a store failed for some reason other than Full or Collision conditions. Rejected dispatches do not count because they have not yet been attempted.", }, [ POWER5_PME_PM_L2SC_RC_DISP_FAIL_CO_BUSY ] = { .pme_name = "PM_L2SC_RC_DISP_FAIL_CO_BUSY", .pme_code = 0x703c2, .pme_short_desc = "L2 slice C RC dispatch attempt failed due to RC/CO pair chosen was miss and CO already busy", .pme_long_desc = "A Read/Claim Dispatch was rejected at dispatch because the Castout Machine was busy. In the case of an RC starting up on a miss and the victim is valid, the CO machine must be available for the RC to process the access. If the CO is still busy working on an old castout, then the RC must not-ack the access if it is a miss(re-issued by the CIU). If it is a miss and the CO is available to process the castout, the RC will accept the access. Once the RC has finished, it can restart and process new accesses that result in a hit (or miss that doesn't need a CO) even though the CO is still processing a castout from a previous access.", }, [ POWER5_PME_PM_PMC4_OVERFLOW ] = { .pme_name = "PM_PMC4_OVERFLOW", .pme_code = 0x10000a, .pme_short_desc = "PMC4 Overflow", .pme_long_desc = "Overflows from PMC4 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.", }, [ POWER5_PME_PM_L3SA_SNOOP_RETRY ] = { .pme_name = "PM_L3SA_SNOOP_RETRY", .pme_code = 0x731e3, .pme_short_desc = "L3 slice A snoop retries", .pme_long_desc = "Number of times an L3 retried a snoop because it got two in at the same time (one on snp_a, one on snp_b)", }, [ POWER5_PME_PM_PTEG_FROM_L35_MOD ] = { .pme_name = "PM_PTEG_FROM_L35_MOD", .pme_code = 0x28309e, .pme_short_desc = "PTEG loaded from L3.5 modified", .pme_long_desc = "A Page Table Entry was loaded into the TLB with modified (M) data from the L3 of a chip on the same module as this processor is located, due to a demand load.", }, [ POWER5_PME_PM_INST_FROM_L25_MOD ] = { .pme_name = "PM_INST_FROM_L25_MOD", .pme_code = 0x222096, .pme_short_desc = "Instruction fetched from L2.5 modified", .pme_long_desc = "An instruction fetch group was fetched with modified (M) data from the L2 of a chip on the same module as this processor is located. Fetch groups can contain up to 8 instructions.", }, [ POWER5_PME_PM_THRD_SMT_HANG ] = { .pme_name = "PM_THRD_SMT_HANG", .pme_code = 0x330e7, .pme_short_desc = "SMT hang detected", .pme_long_desc = "A hung thread was detected", }, [ POWER5_PME_PM_CMPLU_STALL_ERAT_MISS ] = { .pme_name = "PM_CMPLU_STALL_ERAT_MISS", .pme_code = 0x41109b, .pme_short_desc = "Completion stall caused by ERAT miss", .pme_long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes suffered an ERAT miss. This is a subset of PM_CMPLU_STALL_REJECT.", }, [ POWER5_PME_PM_L3SA_MOD_TAG ] = { .pme_name = "PM_L3SA_MOD_TAG", .pme_code = 0x720e3, .pme_short_desc = "L3 slice A transition from modified to TAG", .pme_long_desc = "L3 snooper detects someone doing a read to a line that is truly M in this L3(i.e. L3 going M->T or M->I(go_Mu case) Mu|Me are not included since they are formed due to a prev read op). Tx is not included since it is considered shared at this point.", }, [ POWER5_PME_PM_FLUSH_SYNC ] = { .pme_name = "PM_FLUSH_SYNC", .pme_code = 0x330e1, .pme_short_desc = "Flush caused by sync", .pme_long_desc = "This thread has been flushed at dispatch due to a sync, lwsync, ptesync, or tlbsync instruction. This allows the other thread to have more machine resources for it to make progress until the sync finishes.", }, [ POWER5_PME_PM_INST_FROM_L2MISS ] = { .pme_name = "PM_INST_FROM_L2MISS", .pme_code = 0x12209b, .pme_short_desc = "Instruction fetched missed L2", .pme_long_desc = "An instruction fetch group was fetched from beyond the local L2.", }, [ POWER5_PME_PM_L2SC_ST_HIT ] = { .pme_name = "PM_L2SC_ST_HIT", .pme_code = 0x733e2, .pme_short_desc = "L2 slice C store hits", .pme_long_desc = "A store request made from the core hit in the L2 directory. The event is provided on each of the three slices A, B, and C.", }, [ POWER5_PME_PM_MEM_RQ_DISP_Q8to11 ] = { .pme_name = "PM_MEM_RQ_DISP_Q8to11", .pme_code = 0x722e6, .pme_short_desc = "Memory read queue dispatched to queues 8-11", .pme_long_desc = "A memory operation was dispatched to read queue 8,9,10 or 11. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", }, [ POWER5_PME_PM_MRK_GRP_DISP ] = { .pme_name = "PM_MRK_GRP_DISP", .pme_code = 0x100002, .pme_short_desc = "Marked group dispatched", .pme_long_desc = "A group containing a sampled instruction was dispatched", }, [ POWER5_PME_PM_L2SB_MOD_TAG ] = { .pme_name = "PM_L2SB_MOD_TAG", .pme_code = 0x720e1, .pme_short_desc = "L2 slice B transition from modified to tagged", .pme_long_desc = "A cache line in the local L2 directory made a state transition from the Modified state to the Tagged state. This transition was caused by a read snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A, B, and C.", }, [ POWER5_PME_PM_CLB_EMPTY_CYC ] = { .pme_name = "PM_CLB_EMPTY_CYC", .pme_code = 0x410c6, .pme_short_desc = "Cycles CLB empty", .pme_long_desc = "Cycles when both thread's CLB is completely empty.", }, [ POWER5_PME_PM_L2SB_ST_HIT ] = { .pme_name = "PM_L2SB_ST_HIT", .pme_code = 0x733e1, .pme_short_desc = "L2 slice B store hits", .pme_long_desc = "A store request made from the core hit in the L2 directory. This event is provided on each of the three L2 slices A, B and C.", }, [ POWER5_PME_PM_MEM_NONSPEC_RD_CANCEL ] = { .pme_name = "PM_MEM_NONSPEC_RD_CANCEL", .pme_code = 0x711c6, .pme_short_desc = "Non speculative memory read cancelled", .pme_long_desc = "A non-speculative read was cancelled because the combined response indicated it was sourced from aother L2 or L3. This event is sent from the Memory Controller clock domain and must be scaled accordingly", }, [ POWER5_PME_PM_BR_PRED_CR_TA ] = { .pme_name = "PM_BR_PRED_CR_TA", .pme_code = 0x423087, .pme_short_desc = "A conditional branch was predicted, CR and target prediction", .pme_long_desc = "Both the condition (taken or not taken) and the target address of a branch instruction was predicted.", }, [ POWER5_PME_PM_MRK_LSU0_FLUSH_SRQ ] = { .pme_name = "PM_MRK_LSU0_FLUSH_SRQ", .pme_code = 0x810c3, .pme_short_desc = "LSU0 marked SRQ lhs flushes", .pme_long_desc = "A marked store was flushed because younger load hits and older store that is already in the SRQ or in the same group.", }, [ POWER5_PME_PM_MRK_LSU_FLUSH_ULD ] = { .pme_name = "PM_MRK_LSU_FLUSH_ULD", .pme_code = 0x481090, .pme_short_desc = "Marked unaligned load flushes", .pme_long_desc = "A marked load was flushed because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)", }, [ POWER5_PME_PM_INST_DISP_ATTEMPT ] = { .pme_name = "PM_INST_DISP_ATTEMPT", .pme_code = 0x120e1, .pme_short_desc = "Instructions dispatch attempted", .pme_long_desc = "Number of PowerPC Instructions dispatched (attempted, not filtered by success.", }, [ POWER5_PME_PM_INST_FROM_RMEM ] = { .pme_name = "PM_INST_FROM_RMEM", .pme_code = 0x422086, .pme_short_desc = "Instruction fetched from remote memory", .pme_long_desc = "An instruction fetch group was fetched from memory attached to a different module than this proccessor is located on. Fetch groups can contain up to 8 instructions", }, [ POWER5_PME_PM_ST_REF_L1_LSU0 ] = { .pme_name = "PM_ST_REF_L1_LSU0", .pme_code = 0xc10c1, .pme_short_desc = "LSU0 L1 D cache store references", .pme_long_desc = "Store references to the Data Cache by LSU0.", }, [ POWER5_PME_PM_LSU0_DERAT_MISS ] = { .pme_name = "PM_LSU0_DERAT_MISS", .pme_code = 0x800c2, .pme_short_desc = "LSU0 DERAT misses", .pme_long_desc = "Total D-ERAT Misses by LSU0. Requests that miss the Derat are rejected and retried until the request hits in the Erat. This may result in multiple erat misses for the same instruction.", }, [ POWER5_PME_PM_L2SB_RCLD_DISP ] = { .pme_name = "PM_L2SB_RCLD_DISP", .pme_code = 0x701c1, .pme_short_desc = "L2 slice B RC load dispatch attempt", .pme_long_desc = "A Read/Claim dispatch for a Load was attempted", }, [ POWER5_PME_PM_FPU_STALL3 ] = { .pme_name = "PM_FPU_STALL3", .pme_code = 0x202088, .pme_short_desc = "FPU stalled in pipe3", .pme_long_desc = "FPU has generated a stall in pipe3 due to overflow, underflow, massive cancel, convert to integer (sometimes), or convert from integer (always). This signal is active during the entire duration of the stall. Combined Unit 0 + Unit 1.", }, [ POWER5_PME_PM_BR_PRED_CR ] = { .pme_name = "PM_BR_PRED_CR", .pme_code = 0x230e2, .pme_short_desc = "A conditional branch was predicted, CR prediction", .pme_long_desc = "A conditional branch instruction was predicted as taken or not taken.", }, [ POWER5_PME_PM_MRK_DATA_FROM_L2 ] = { .pme_name = "PM_MRK_DATA_FROM_L2", .pme_code = 0x1c7087, .pme_short_desc = "Marked data loaded from L2", .pme_long_desc = "The processor's Data Cache was reloaded from the local L2 due to a marked load.", }, [ POWER5_PME_PM_LSU0_FLUSH_SRQ ] = { .pme_name = "PM_LSU0_FLUSH_SRQ", .pme_code = 0xc00c3, .pme_short_desc = "LSU0 SRQ lhs flushes", .pme_long_desc = "A store was flushed by unit 0 because younger load hits and older store that is already in the SRQ or in the same group.", }, [ POWER5_PME_PM_FAB_PNtoNN_DIRECT ] = { .pme_name = "PM_FAB_PNtoNN_DIRECT", .pme_code = 0x703c7, .pme_short_desc = "PN to NN beat went straight to its destination", .pme_long_desc = "Fabric Data beats that the base chip takes the inbound PN data and passes it through to the outbound NN bus without going into a sidecar. The signal is delivered at FBC speed and the count must be scaled.", }, [ POWER5_PME_PM_IOPS_CMPL ] = { .pme_name = "PM_IOPS_CMPL", .pme_code = 0x1, .pme_short_desc = "Internal operations completed", .pme_long_desc = "Number of internal operations that completed.", }, [ POWER5_PME_PM_L2SC_SHR_INV ] = { .pme_name = "PM_L2SC_SHR_INV", .pme_code = 0x710c2, .pme_short_desc = "L2 slice C transition from shared to invalid", .pme_long_desc = "A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L, or Tagged) to the Invalid state. This transition was caused by any external snoop request. The event is provided on each of the three slices A, B, and C. NOTE: For this event to be useful the tablewalk duration event should also be counted.", }, [ POWER5_PME_PM_L2SA_RCST_DISP_FAIL_OTHER ] = { .pme_name = "PM_L2SA_RCST_DISP_FAIL_OTHER", .pme_code = 0x732e0, .pme_short_desc = "L2 slice A RC store dispatch attempt failed due to other reasons", .pme_long_desc = "A Read/Claim dispatch for a store failed for some reason other than Full or Collision conditions. Rejected dispatches do not count because they have not yet been attempted.", }, [ POWER5_PME_PM_L2SA_RCST_DISP ] = { .pme_name = "PM_L2SA_RCST_DISP", .pme_code = 0x702c0, .pme_short_desc = "L2 slice A RC store dispatch attempt", .pme_long_desc = "A Read/Claim dispatch for a Store was attempted.", }, [ POWER5_PME_PM_SNOOP_RETRY_AB_COLLISION ] = { .pme_name = "PM_SNOOP_RETRY_AB_COLLISION", .pme_code = 0x735e6, .pme_short_desc = "Snoop retry due to a b collision", .pme_long_desc = "Snoop retry due to a b collision", }, [ POWER5_PME_PM_FAB_PNtoVN_SIDECAR ] = { .pme_name = "PM_FAB_PNtoVN_SIDECAR", .pme_code = 0x733e7, .pme_short_desc = "PN to VN beat went to sidecar first", .pme_long_desc = "Fabric data beats that the base chip takes the inbound PN data and forwards it on to the outbound VN data bus after going into a sidecar first. The signal is delivered at FBC speed and the count must be scaled accordingly.", }, [ POWER5_PME_PM_LSU_LMQ_S0_ALLOC ] = { .pme_name = "PM_LSU_LMQ_S0_ALLOC", .pme_code = 0xc30e6, .pme_short_desc = "LMQ slot 0 allocated", .pme_long_desc = "The first entry in the LMQ was allocated.", }, [ POWER5_PME_PM_LSU0_REJECT_LMQ_FULL ] = { .pme_name = "PM_LSU0_REJECT_LMQ_FULL", .pme_code = 0xc60e1, .pme_short_desc = "LSU0 reject due to LMQ full or missed data coming", .pme_long_desc = "Total cycles the Load Store Unit 0 is busy rejecting instructions because the Load Miss Queue was full. The LMQ has eight entries. If all eight entries are full, subsequent load instructions are rejected.", }, [ POWER5_PME_PM_SNOOP_PW_RETRY_RQ ] = { .pme_name = "PM_SNOOP_PW_RETRY_RQ", .pme_code = 0x707c6, .pme_short_desc = "Snoop partial-write retry due to collision with active read queue", .pme_long_desc = "A snoop request for a partial write to memory was retried because it matched the cache line of an active read. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", }, [ POWER5_PME_PM_DTLB_REF ] = { .pme_name = "PM_DTLB_REF", .pme_code = 0x2c4090, .pme_short_desc = "Data TLB references", .pme_long_desc = "Total number of Data TLB references for all page sizes. Page size is determined at TLB reload time.", }, [ POWER5_PME_PM_PTEG_FROM_L3 ] = { .pme_name = "PM_PTEG_FROM_L3", .pme_code = 0x18308e, .pme_short_desc = "PTEG loaded from L3", .pme_long_desc = "A Page Table Entry was loaded into the TLB from the local L3 due to a demand load.", }, [ POWER5_PME_PM_FAB_M1toVNorNN_SIDECAR_EMPTY ] = { .pme_name = "PM_FAB_M1toVNorNN_SIDECAR_EMPTY", .pme_code = 0x712c7, .pme_short_desc = "M1 to VN/NN sidecar empty", .pme_long_desc = "Fabric cycles when the Minus-1 jump sidecar (sidecars for mcm to mcm data transfer) is empty. The signal is delivered at FBC speed and the count must be scaled accordingly.", }, [ POWER5_PME_PM_LSU_SRQ_EMPTY_CYC ] = { .pme_name = "PM_LSU_SRQ_EMPTY_CYC", .pme_code = 0x400015, .pme_short_desc = "Cycles SRQ empty", .pme_long_desc = "Cycles the Store Request Queue is empty", }, [ POWER5_PME_PM_FPU1_STF ] = { .pme_name = "PM_FPU1_STF", .pme_code = 0x20e6, .pme_short_desc = "FPU1 executed store instruction", .pme_long_desc = "FPU1 has executed a Floating Point Store instruction.", }, [ POWER5_PME_PM_LSU_LMQ_S0_VALID ] = { .pme_name = "PM_LSU_LMQ_S0_VALID", .pme_code = 0xc30e5, .pme_short_desc = "LMQ slot 0 valid", .pme_long_desc = "This signal is asserted every cycle when the first entry in the LMQ is valid. The LMQ had eight entries that are allocated FIFO", }, [ POWER5_PME_PM_GCT_USAGE_00to59_CYC ] = { .pme_name = "PM_GCT_USAGE_00to59_CYC", .pme_code = 0x10001f, .pme_short_desc = "Cycles GCT less than 60% full", .pme_long_desc = "Cycles when the Global Completion Table has fewer than 60% of its slots used. The GCT has 20 entries shared between threads.", }, [ POWER5_PME_PM_DATA_FROM_L2MISS ] = { .pme_name = "PM_DATA_FROM_L2MISS", .pme_code = 0x3c309b, .pme_short_desc = "Data loaded missed L2", .pme_long_desc = "The processor's Data Cache was reloaded but not from the local L2.", }, [ POWER5_PME_PM_GRP_DISP_BLK_SB_CYC ] = { .pme_name = "PM_GRP_DISP_BLK_SB_CYC", .pme_code = 0x130e1, .pme_short_desc = "Cycles group dispatch blocked by scoreboard", .pme_long_desc = "A scoreboard operation on a non-renamed resource has blocked dispatch.", }, [ POWER5_PME_PM_FPU_FMOV_FEST ] = { .pme_name = "PM_FPU_FMOV_FEST", .pme_code = 0x301088, .pme_short_desc = "FPU executed FMOV or FEST instructions", .pme_long_desc = "The floating point unit has executed a move kind of instruction or one of the estimate instructions. This could be fmr*, fneg*, fabs*, fnabs* , fres* or frsqrte* where XYZ* means XYZ or XYZ.. Combined Unit 0 + Unit 1.", }, [ POWER5_PME_PM_XER_MAP_FULL_CYC ] = { .pme_name = "PM_XER_MAP_FULL_CYC", .pme_code = 0x100c2, .pme_short_desc = "Cycles XER mapper full", .pme_long_desc = "The XER mapper cannot accept any more groups. This condition will prevent dispatch groups from being dispatched. This event only indicates that the mapper was full, not that dispatch was prevented.", }, [ POWER5_PME_PM_FLUSH_SB ] = { .pme_name = "PM_FLUSH_SB", .pme_code = 0x330e2, .pme_short_desc = "Flush caused by scoreboard operation", .pme_long_desc = "This thread has been flushed at dispatch because its scoreboard bit is set indicating that a non-renamed resource is being updated. This allows the other thread to have more machine resources for it to make progress while this thread is stalled.", }, [ POWER5_PME_PM_MRK_DATA_FROM_L375_SHR ] = { .pme_name = "PM_MRK_DATA_FROM_L375_SHR", .pme_code = 0x3c709e, .pme_short_desc = "Marked data loaded from L3.75 shared", .pme_long_desc = "The processor's Data Cache was reloaded with shared (S) data from the L3 of a chip on a different module than this processor is located due to a marked load.", }, [ POWER5_PME_PM_MRK_GRP_CMPL ] = { .pme_name = "PM_MRK_GRP_CMPL", .pme_code = 0x400013, .pme_short_desc = "Marked group completed", .pme_long_desc = "A group containing a sampled instruction completed. Microcoded instructions that span multiple groups will generate this event once per group.", }, [ POWER5_PME_PM_SUSPENDED ] = { .pme_name = "PM_SUSPENDED", .pme_code = 0x0, .pme_short_desc = "Suspended", .pme_long_desc = "The counter is suspended (does not count).", }, [ POWER5_PME_PM_GRP_IC_MISS_BR_REDIR_NONSPEC ] = { .pme_name = "PM_GRP_IC_MISS_BR_REDIR_NONSPEC", .pme_code = 0x120e5, .pme_short_desc = "Group experienced non-speculative I cache miss or branch redirect", .pme_long_desc = "Group experienced non-speculative I cache miss or branch redirect", }, [ POWER5_PME_PM_SNOOP_RD_RETRY_QFULL ] = { .pme_name = "PM_SNOOP_RD_RETRY_QFULL", .pme_code = 0x700c6, .pme_short_desc = "Snoop read retry due to read queue full", .pme_long_desc = "A snoop request for a read from memory was retried because the read queues were full. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", }, [ POWER5_PME_PM_L3SB_MOD_INV ] = { .pme_name = "PM_L3SB_MOD_INV", .pme_code = 0x730e4, .pme_short_desc = "L3 slice B transition from modified to invalid", .pme_long_desc = "L3 snooper detects someone doing a store to a line that is truly M in this L3 (i.e. L3 going M=>I). Mu|Me are not included since they are formed due to a prev read op. Tx is not included since it is considered shared at this point.", }, [ POWER5_PME_PM_DATA_FROM_L35_SHR ] = { .pme_name = "PM_DATA_FROM_L35_SHR", .pme_code = 0x1c309e, .pme_short_desc = "Data loaded from L3.5 shared", .pme_long_desc = "The processor's Data Cache was reloaded with shared (S) data from the L3 of a chip on the same module as this processor is located due to a demand load.", }, [ POWER5_PME_PM_LD_MISS_L1_LSU1 ] = { .pme_name = "PM_LD_MISS_L1_LSU1", .pme_code = 0xc10c6, .pme_short_desc = "LSU1 L1 D cache load misses", .pme_long_desc = "Load references that miss the Level 1 Data cache, by unit 1.", }, [ POWER5_PME_PM_STCX_FAIL ] = { .pme_name = "PM_STCX_FAIL", .pme_code = 0x820e1, .pme_short_desc = "STCX failed", .pme_long_desc = "A stcx (stwcx or stdcx) failed", }, [ POWER5_PME_PM_DC_PREF_DST ] = { .pme_name = "PM_DC_PREF_DST", .pme_code = 0x830e6, .pme_short_desc = "DST (Data Stream Touch) stream start", .pme_long_desc = "A prefetch stream was started using the DST instruction.", }, [ POWER5_PME_PM_GRP_DISP ] = { .pme_name = "PM_GRP_DISP", .pme_code = 0x200002, .pme_short_desc = "Group dispatches", .pme_long_desc = "A group was dispatched", }, [ POWER5_PME_PM_L2SA_RCLD_DISP_FAIL_ADDR ] = { .pme_name = "PM_L2SA_RCLD_DISP_FAIL_ADDR", .pme_code = 0x711c0, .pme_short_desc = "L2 slice A RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ", .pme_long_desc = "A Read/Claim dispatch for a load failed because of an address conflict. Two RC machines will never both work on the same line or line in the same congruence class at the same time.", }, [ POWER5_PME_PM_FPU0_FPSCR ] = { .pme_name = "PM_FPU0_FPSCR", .pme_code = 0x30e0, .pme_short_desc = "FPU0 executed FPSCR instruction", .pme_long_desc = "FPU0 has executed FPSCR move related instruction. This could be mtfsfi*, mtfsb0*, mtfsb1*, mffs*, mtfsf*, mcrsf* where XYZ* means XYZ, XYZs, XYZ., XYZs.", }, [ POWER5_PME_PM_DATA_FROM_L2 ] = { .pme_name = "PM_DATA_FROM_L2", .pme_code = 0x1c3087, .pme_short_desc = "Data loaded from L2", .pme_long_desc = "The processor's Data Cache was reloaded from the local L2 due to a demand load.", }, [ POWER5_PME_PM_FPU1_DENORM ] = { .pme_name = "PM_FPU1_DENORM", .pme_code = 0x20e4, .pme_short_desc = "FPU1 received denormalized data", .pme_long_desc = "FPU1 has encountered a denormalized operand.", }, [ POWER5_PME_PM_FPU_1FLOP ] = { .pme_name = "PM_FPU_1FLOP", .pme_code = 0x100090, .pme_short_desc = "FPU executed one flop instruction", .pme_long_desc = "The floating point unit has executed an add, mult, sub, compare, fsel, fneg, fabs, fnabs, fres, or frsqrte kind of instruction. These are single FLOP operations.", }, [ POWER5_PME_PM_L2SC_RCLD_DISP_FAIL_OTHER ] = { .pme_name = "PM_L2SC_RCLD_DISP_FAIL_OTHER", .pme_code = 0x731e2, .pme_short_desc = "L2 slice C RC load dispatch attempt failed due to other reasons", .pme_long_desc = "A Read/Claim dispatch for a load failed for some reason other than Full or Collision conditions.", }, [ POWER5_PME_PM_L2SC_RCST_DISP_FAIL_RC_FULL ] = { .pme_name = "PM_L2SC_RCST_DISP_FAIL_RC_FULL", .pme_code = 0x722e2, .pme_short_desc = "L2 slice C RC store dispatch attempt failed due to all RC full", .pme_long_desc = "A Read/Claim dispatch for a store failed because all RC machines are busy.", }, [ POWER5_PME_PM_FPU0_FSQRT ] = { .pme_name = "PM_FPU0_FSQRT", .pme_code = 0xc2, .pme_short_desc = "FPU0 executed FSQRT instruction", .pme_long_desc = "FPU0 has executed a square root instruction. This could be fsqrt* where XYZ* means XYZ, XYZs, XYZ., XYZs.", }, [ POWER5_PME_PM_LD_REF_L1 ] = { .pme_name = "PM_LD_REF_L1", .pme_code = 0x4c1090, .pme_short_desc = "L1 D cache load references", .pme_long_desc = "Load references to the Level 1 Data Cache. Combined unit 0 + 1.", }, [ POWER5_PME_PM_INST_FROM_L1 ] = { .pme_name = "PM_INST_FROM_L1", .pme_code = 0x22208d, .pme_short_desc = "Instruction fetched from L1", .pme_long_desc = "An instruction fetch group was fetched from L1. Fetch Groups can contain up to 8 instructions", }, [ POWER5_PME_PM_TLBIE_HELD ] = { .pme_name = "PM_TLBIE_HELD", .pme_code = 0x130e4, .pme_short_desc = "TLBIE held at dispatch", .pme_long_desc = "Cycles a TLBIE instruction was held at dispatch.", }, [ POWER5_PME_PM_DC_PREF_OUT_OF_STREAMS ] = { .pme_name = "PM_DC_PREF_OUT_OF_STREAMS", .pme_code = 0xc50c2, .pme_short_desc = "D cache out of prefetch streams", .pme_long_desc = "A new prefetch stream was detected but no more stream entries were available.", }, [ POWER5_PME_PM_MRK_DATA_FROM_L25_MOD_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L25_MOD_CYC", .pme_code = 0x4c70a2, .pme_short_desc = "Marked load latency from L2.5 modified", .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.", }, [ POWER5_PME_PM_MRK_LSU1_FLUSH_SRQ ] = { .pme_name = "PM_MRK_LSU1_FLUSH_SRQ", .pme_code = 0x810c7, .pme_short_desc = "LSU1 marked SRQ lhs flushes", .pme_long_desc = "A marked store was flushed because younger load hits and older store that is already in the SRQ or in the same group.", }, [ POWER5_PME_PM_MEM_RQ_DISP_Q0to3 ] = { .pme_name = "PM_MEM_RQ_DISP_Q0to3", .pme_code = 0x702c6, .pme_short_desc = "Memory read queue dispatched to queues 0-3", .pme_long_desc = "A memory operation was dispatched to read queue 0,1,2, or 3. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", }, [ POWER5_PME_PM_ST_REF_L1_LSU1 ] = { .pme_name = "PM_ST_REF_L1_LSU1", .pme_code = 0xc10c5, .pme_short_desc = "LSU1 L1 D cache store references", .pme_long_desc = "Store references to the Data Cache by LSU1.", }, [ POWER5_PME_PM_MRK_LD_MISS_L1 ] = { .pme_name = "PM_MRK_LD_MISS_L1", .pme_code = 0x182088, .pme_short_desc = "Marked L1 D cache load misses", .pme_long_desc = "Marked L1 D cache load misses", }, [ POWER5_PME_PM_L1_WRITE_CYC ] = { .pme_name = "PM_L1_WRITE_CYC", .pme_code = 0x230e7, .pme_short_desc = "Cycles writing to instruction L1", .pme_long_desc = "Cycles that a cache line was written to the instruction cache.", }, [ POWER5_PME_PM_L2SC_ST_REQ ] = { .pme_name = "PM_L2SC_ST_REQ", .pme_code = 0x723e2, .pme_short_desc = "L2 slice C store requests", .pme_long_desc = "A store request as seen at the L2 directory has been made from the core. Stores are counted after gathering in the L2 store queues. The event is provided on each of the three slices A, B, and C.", }, [ POWER5_PME_PM_CMPLU_STALL_FDIV ] = { .pme_name = "PM_CMPLU_STALL_FDIV", .pme_code = 0x21109b, .pme_short_desc = "Completion stall caused by FDIV or FQRT instruction", .pme_long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes was a floating point divide or square root instruction. This is a subset of PM_CMPLU_STALL_FPU.", }, [ POWER5_PME_PM_THRD_SEL_OVER_CLB_EMPTY ] = { .pme_name = "PM_THRD_SEL_OVER_CLB_EMPTY", .pme_code = 0x410c2, .pme_short_desc = "Thread selection overrides caused by CLB empty", .pme_long_desc = "Thread selection was overridden because one thread's CLB was empty.", }, [ POWER5_PME_PM_BR_MPRED_CR ] = { .pme_name = "PM_BR_MPRED_CR", .pme_code = 0x230e5, .pme_short_desc = "Branch mispredictions due to CR bit setting", .pme_long_desc = "A conditional branch instruction was incorrectly predicted as taken or not taken. The branch execution unit detects a branch mispredict because the CR value is opposite of the predicted value. This will result in a branch redirect flush if not overfidden by a flush of an older instruction.", }, [ POWER5_PME_PM_L3SB_MOD_TAG ] = { .pme_name = "PM_L3SB_MOD_TAG", .pme_code = 0x720e4, .pme_short_desc = "L3 slice B transition from modified to TAG", .pme_long_desc = "L3 snooper detects someone doing a read to a line that is truly M in this L3(i.e. L3 going M->T or M->I(go_Mu case); Mu|Me are not included since they are formed due to a prev read op). Tx is not included since it is considered shared at this point.", }, [ POWER5_PME_PM_MRK_DATA_FROM_L2MISS ] = { .pme_name = "PM_MRK_DATA_FROM_L2MISS", .pme_code = 0x3c709b, .pme_short_desc = "Marked data loaded missed L2", .pme_long_desc = "DL1 was reloaded from beyond L2 due to a marked demand load.", }, [ POWER5_PME_PM_LSU_REJECT_SRQ ] = { .pme_name = "PM_LSU_REJECT_SRQ", .pme_code = 0x1c6088, .pme_short_desc = "LSU SRQ lhs rejects", .pme_long_desc = "Total cycles the Load Store Unit is busy rejecting instructions because of Load Hit Store conditions. Loads are rejected when data is needed from a previous store instruction but store forwarding is not possible because the data is not fully contained in the Store Data Queue or is not yet available in the Store Data Queue. Combined Unit 0 + 1.", }, [ POWER5_PME_PM_LD_MISS_L1 ] = { .pme_name = "PM_LD_MISS_L1", .pme_code = 0x3c1088, .pme_short_desc = "L1 D cache load misses", .pme_long_desc = "Load references that miss the Level 1 Data cache. Combined unit 0 + 1.", }, [ POWER5_PME_PM_INST_FROM_PREF ] = { .pme_name = "PM_INST_FROM_PREF", .pme_code = 0x32208d, .pme_short_desc = "Instruction fetched from prefetch", .pme_long_desc = "An instruction fetch group was fetched from the prefetch buffer. Fetch groups can contain up to 8 instructions", }, [ POWER5_PME_PM_DC_INV_L2 ] = { .pme_name = "PM_DC_INV_L2", .pme_code = 0xc10c7, .pme_short_desc = "L1 D cache entries invalidated from L2", .pme_long_desc = "A dcache invalidated was received from the L2 because a line in L2 was castout.", }, [ POWER5_PME_PM_STCX_PASS ] = { .pme_name = "PM_STCX_PASS", .pme_code = 0x820e5, .pme_short_desc = "Stcx passes", .pme_long_desc = "A stcx (stwcx or stdcx) instruction was successful", }, [ POWER5_PME_PM_LSU_SRQ_FULL_CYC ] = { .pme_name = "PM_LSU_SRQ_FULL_CYC", .pme_code = 0x110c3, .pme_short_desc = "Cycles SRQ full", .pme_long_desc = "Cycles the Store Request Queue is full.", }, [ POWER5_PME_PM_FPU_FIN ] = { .pme_name = "PM_FPU_FIN", .pme_code = 0x401088, .pme_short_desc = "FPU produced a result", .pme_long_desc = "FPU finished, produced a result. This only indicates finish, not completion. Combined Unit 0 + Unit 1. Floating Point Stores are included in this count but not Floating Point Loads., , , XYZs", }, [ POWER5_PME_PM_L2SA_SHR_MOD ] = { .pme_name = "PM_L2SA_SHR_MOD", .pme_code = 0x700c0, .pme_short_desc = "L2 slice A transition from shared to modified", .pme_long_desc = "A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L , or Tagged) to the Modified state. This transition was caused by a store from either of the two local CPUs to a cache line in any of the Shared states. The event is provided on each of the three slices A, B, and C. ", }, [ POWER5_PME_PM_LSU_SRQ_STFWD ] = { .pme_name = "PM_LSU_SRQ_STFWD", .pme_code = 0x1c2088, .pme_short_desc = "SRQ store forwarded", .pme_long_desc = "Data from a store instruction was forwarded to a load. A load that misses L1 but becomes a store forward is treated as a load miss and it causes the DL1 load miss event to be counted. It does not go into the LMQ. If a load that hits L1 but becomes a store forward, then it's not treated as a load miss. Combined Unit 0 + 1.", }, [ POWER5_PME_PM_0INST_CLB_CYC ] = { .pme_name = "PM_0INST_CLB_CYC", .pme_code = 0x400c0, .pme_short_desc = "Cycles no instructions in CLB", .pme_long_desc = "The cache line buffer (CLB) is a 6-deep, 4-wide instruction buffer. Fullness is reported on a cycle basis with each event representing the number of cycles the CLB had the corresponding number of entries occupied. These events give a real time history of the number of instruction buffers used, but not the number of PowerPC instructions within those buffers. Each thread has its own set of CLB; these events are thread specific.", }, [ POWER5_PME_PM_FXU0_FIN ] = { .pme_name = "PM_FXU0_FIN", .pme_code = 0x130e2, .pme_short_desc = "FXU0 produced a result", .pme_long_desc = "The Fixed Point unit 0 finished an instruction and produced a result. Instructions that finish may not necessary complete.", }, [ POWER5_PME_PM_L2SB_RCST_DISP_FAIL_RC_FULL ] = { .pme_name = "PM_L2SB_RCST_DISP_FAIL_RC_FULL", .pme_code = 0x722e1, .pme_short_desc = "L2 slice B RC store dispatch attempt failed due to all RC full", .pme_long_desc = "A Read/Claim dispatch for a store failed because all RC machines are busy.", }, [ POWER5_PME_PM_THRD_GRP_CMPL_BOTH_CYC ] = { .pme_name = "PM_THRD_GRP_CMPL_BOTH_CYC", .pme_code = 0x200013, .pme_short_desc = "Cycles group completed by both threads", .pme_long_desc = "Cycles that both threads completed.", }, [ POWER5_PME_PM_PMC5_OVERFLOW ] = { .pme_name = "PM_PMC5_OVERFLOW", .pme_code = 0x10001a, .pme_short_desc = "PMC5 Overflow", .pme_long_desc = "Overflows from PMC5 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.", }, [ POWER5_PME_PM_FPU0_FDIV ] = { .pme_name = "PM_FPU0_FDIV", .pme_code = 0xc0, .pme_short_desc = "FPU0 executed FDIV instruction", .pme_long_desc = "FPU0 has executed a divide instruction. This could be fdiv, fdivs, fdiv. fdivs.", }, [ POWER5_PME_PM_PTEG_FROM_L375_SHR ] = { .pme_name = "PM_PTEG_FROM_L375_SHR", .pme_code = 0x38309e, .pme_short_desc = "PTEG loaded from L3.75 shared", .pme_long_desc = "A Page Table Entry was loaded into the TLB with shared (S) data from the L3 of a chip on a different module than this processor is located, due to a demand load.", }, [ POWER5_PME_PM_LD_REF_L1_LSU1 ] = { .pme_name = "PM_LD_REF_L1_LSU1", .pme_code = 0xc10c4, .pme_short_desc = "LSU1 L1 D cache load references", .pme_long_desc = "Load references to Level 1 Data Cache, by unit 1.", }, [ POWER5_PME_PM_L2SA_RC_DISP_FAIL_CO_BUSY ] = { .pme_name = "PM_L2SA_RC_DISP_FAIL_CO_BUSY", .pme_code = 0x703c0, .pme_short_desc = "L2 slice A RC dispatch attempt failed due to RC/CO pair chosen was miss and CO already busy", .pme_long_desc = "A Read/Claim Dispatch was rejected at dispatch because the Castout Machine was busy. In the case of an RC starting up on a miss and the victim is valid, the CO machine must be available for the RC to process the access. If the CO is still busy working on an old castout, then the RC must not-ack the access if it is a miss(re-issued by the CIU). If it is a miss and the CO is available to process the castout, the RC will accept the access. Once the RC has finished, it can restart and process new accesses that result in a hit (or miss that doesn't need a CO) even though the CO is still processing a castout from a previous access.", }, [ POWER5_PME_PM_HV_CYC ] = { .pme_name = "PM_HV_CYC", .pme_code = 0x20000b, .pme_short_desc = "Hypervisor Cycles", .pme_long_desc = "Cycles when the processor is executing in Hypervisor (MSR[HV] = 1 and MSR[PR]=0)", }, [ POWER5_PME_PM_THRD_PRIO_DIFF_0_CYC ] = { .pme_name = "PM_THRD_PRIO_DIFF_0_CYC", .pme_code = 0x430e3, .pme_short_desc = "Cycles no thread priority difference", .pme_long_desc = "Cycles when this thread's priority is equal to the other thread's priority.", }, [ POWER5_PME_PM_LR_CTR_MAP_FULL_CYC ] = { .pme_name = "PM_LR_CTR_MAP_FULL_CYC", .pme_code = 0x100c6, .pme_short_desc = "Cycles LR/CTR mapper full", .pme_long_desc = "The LR/CTR mapper cannot accept any more groups. This condition will prevent dispatch groups from being dispatched. This event only indicates that the mapper was full, not that dispatch was prevented.", }, [ POWER5_PME_PM_L3SB_SHR_INV ] = { .pme_name = "PM_L3SB_SHR_INV", .pme_code = 0x710c4, .pme_short_desc = "L3 slice B transition from shared to invalid", .pme_long_desc = "L3 snooper detects someone doing a store to a line that is Sx in this L3(i.e. invalidate hit SX and dispatched).", }, [ POWER5_PME_PM_DATA_FROM_RMEM ] = { .pme_name = "PM_DATA_FROM_RMEM", .pme_code = 0x1c30a1, .pme_short_desc = "Data loaded from remote memory", .pme_long_desc = "The processor's Data Cache was reloaded from memory attached to a different module than this proccessor is located on.", }, [ POWER5_PME_PM_DATA_FROM_L275_MOD ] = { .pme_name = "PM_DATA_FROM_L275_MOD", .pme_code = 0x1c30a3, .pme_short_desc = "Data loaded from L2.75 modified", .pme_long_desc = "The processor's Data Cache was reloaded with modified (M) data from the L2 on a different module than this processor is located due to a demand load. ", }, [ POWER5_PME_PM_LSU0_REJECT_SRQ ] = { .pme_name = "PM_LSU0_REJECT_SRQ", .pme_code = 0xc60e0, .pme_short_desc = "LSU0 SRQ lhs rejects", .pme_long_desc = "Total cycles the Load Store Unit 0 is busy rejecting instructions because of Load Hit Store conditions. Loads are rejected when data is needed from a previous store instruction but store forwarding is not possible because the data is not fully contained in the Store Data Queue or is not yet available in the Store Data Queue.", }, [ POWER5_PME_PM_LSU1_DERAT_MISS ] = { .pme_name = "PM_LSU1_DERAT_MISS", .pme_code = 0x800c6, .pme_short_desc = "LSU1 DERAT misses", .pme_long_desc = "A data request (load or store) from LSU Unit 1 missed the ERAT and resulted in an ERAT reload. Multiple instructions may miss the ERAT entry for the same 4K page, but only one reload will occur.", }, [ POWER5_PME_PM_MRK_LSU_FIN ] = { .pme_name = "PM_MRK_LSU_FIN", .pme_code = 0x400014, .pme_short_desc = "Marked instruction LSU processing finished", .pme_long_desc = "One of the Load/Store Units finished a marked instruction. Instructions that finish may not necessary complete", }, [ POWER5_PME_PM_DTLB_MISS_16M ] = { .pme_name = "PM_DTLB_MISS_16M", .pme_code = 0xc40c4, .pme_short_desc = "Data TLB miss for 16M page", .pme_long_desc = "Data TLB references to 16MB pages that missed the TLB. Page size is determined at TLB reload time.", }, [ POWER5_PME_PM_LSU0_FLUSH_UST ] = { .pme_name = "PM_LSU0_FLUSH_UST", .pme_code = 0xc00c1, .pme_short_desc = "LSU0 unaligned store flushes", .pme_long_desc = "A store was flushed from unit 0 because it was unaligned (crossed a 4K boundary).", }, [ POWER5_PME_PM_L2SC_MOD_TAG ] = { .pme_name = "PM_L2SC_MOD_TAG", .pme_code = 0x720e2, .pme_short_desc = "L2 slice C transition from modified to tagged", .pme_long_desc = "A cache line in the local L2 directory made a state transition from the Modified state to the Tagged state. This transition was caused by a read snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A, B, and C.", }, [ POWER5_PME_PM_L2SB_RC_DISP_FAIL_CO_BUSY ] = { .pme_name = "PM_L2SB_RC_DISP_FAIL_CO_BUSY", .pme_code = 0x703c1, .pme_short_desc = "L2 slice B RC dispatch attempt failed due to RC/CO pair chosen was miss and CO already busy", .pme_long_desc = "A Read/Claim Dispatch was rejected at dispatch because the Castout Machine was busy. In the case of an RC starting up on a miss and the victim is valid, the CO machine must be available for the RC to process the access. If the CO is still busy working on an old castout, then the RC must not-ack the access if it is a miss(re-issued by the CIU). If it is a miss and the CO is available to process the castout, the RC will accept the access. Once the RC has finished, it can restart and process new accesses that result in a hit (or miss that doesn't need a CO) even though the CO is still processing a castout from a previous access.", } }; #endif libpfm-4.9.0/lib/events/intel_snbep_unc_pcu_events.h0000664000175000017500000002230613223402656022446 0ustar eranianeranian/* * Copyright (c) 2012 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * PMU: snbep_unc_pcu (Intel SandyBridge-EP PCU uncore) */ static const intel_x86_umask_t snbep_unc_p_power_state_occupancy[]={ { .uname = "CORES_C0", .udesc = "Counts number of cores in C0", .ucode = 0x4000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "CORES_C3", .udesc = "Counts number of cores in C3", .ucode = 0x8000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "CORES_C6", .udesc = "Counts number of cores in C6", .ucode = 0xc000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t snbep_unc_p_occupancy_counters[]={ { .uname = "C0", .udesc = "Counts number of cores in C0", .ucode = 0x0100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "C3", .udesc = "Counts number of cores in C3", .ucode = 0x0200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "C6", .udesc = "Counts number of cores in C6", .ucode = 0x0300, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_entry_t intel_snbep_unc_p_pe[]={ { .name = "UNC_P_CLOCKTICKS", .desc = "PCU Uncore clockticks", .modmsk = SNBEP_UNC_PCU_ATTRS, .cntmsk = 0xf, .code = 0x00, }, { .name = "UNC_P_CORE0_TRANSITION_CYCLES", .desc = "Core C State Transition Cycles", .code = 0x3 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = SNBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_CORE1_TRANSITION_CYCLES", .desc = "Core C State Transition Cycles", .code = 0x4 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = SNBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_CORE2_TRANSITION_CYCLES", .desc = "Core C State Transition Cycles", .code = 0x5 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = SNBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_CORE3_TRANSITION_CYCLES", .desc = "Core C State Transition Cycles", .code = 0x6 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = SNBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_CORE4_TRANSITION_CYCLES", .desc = "Core C State Transition Cycles", .code = 0x7 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = SNBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_CORE5_TRANSITION_CYCLES", .desc = "Core C State Transition Cycles", .code = 0x8 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = SNBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_CORE6_TRANSITION_CYCLES", .desc = "Core C State Transition Cycles", .code = 0x9 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = SNBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_CORE7_TRANSITION_CYCLES", .desc = "Core C State Transition Cycles", .code = 0xa | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = SNBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_DEMOTIONS_CORE0", .desc = "Core C State Demotions", .code = 0x1e, .cntmsk = 0xf, .modmsk = SNBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_DEMOTIONS_CORE1", .desc = "Core C State Demotions", .code = 0x1f, .cntmsk = 0xf, .modmsk = SNBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_DEMOTIONS_CORE2", .desc = "Core C State Demotions", .code = 0x20, .cntmsk = 0xf, .modmsk = SNBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_DEMOTIONS_CORE3", .desc = "Core C State Demotions", .code = 0x21, .cntmsk = 0xf, .modmsk = SNBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_DEMOTIONS_CORE4", .desc = "Core C State Demotions", .code = 0x22, .cntmsk = 0xf, .modmsk = SNBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_DEMOTIONS_CORE5", .desc = "Core C State Demotions", .code = 0x23, .cntmsk = 0xf, .modmsk = SNBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_DEMOTIONS_CORE6", .desc = "Core C State Demotions", .code = 0x24, .cntmsk = 0xf, .modmsk = SNBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_DEMOTIONS_CORE7", .desc = "Core C State Demotions", .code = 0x25, .cntmsk = 0xf, .modmsk = SNBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_FREQ_BAND0_CYCLES", .desc = "Frequency Residency", .code = 0xb, .cntmsk = 0xf, .flags = INTEL_X86_NO_AUTOENCODE, .modmsk = SNBEP_UNC_PCU_BAND_ATTRS, .modmsk_req = _SNBEP_UNC_ATTR_FF, }, { .name = "UNC_P_FREQ_BAND1_CYCLES", .desc = "Frequency Residency", .code = 0xc, .cntmsk = 0xf, .flags = INTEL_X86_NO_AUTOENCODE, .modmsk = SNBEP_UNC_PCU_BAND_ATTRS, .modmsk_req = _SNBEP_UNC_ATTR_FF, }, { .name = "UNC_P_FREQ_BAND2_CYCLES", .desc = "Frequency Residency", .code = 0xd, .cntmsk = 0xf, .flags = INTEL_X86_NO_AUTOENCODE, .modmsk = SNBEP_UNC_PCU_BAND_ATTRS, .modmsk_req = _SNBEP_UNC_ATTR_FF, }, { .name = "UNC_P_FREQ_BAND3_CYCLES", .desc = "Frequency Residency", .code = 0xe, .cntmsk = 0xf, .flags = INTEL_X86_NO_AUTOENCODE, .modmsk = SNBEP_UNC_PCU_BAND_ATTRS, .modmsk_req = _SNBEP_UNC_ATTR_FF, }, { .name = "UNC_P_FREQ_MAX_CURRENT_CYCLES", .desc = "Current Strongest Upper Limit Cycles", .code = 0x7, .cntmsk = 0xf, .modmsk = SNBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES", .desc = "Thermal Strongest Upper Limit Cycles", .code = 0x4, .cntmsk = 0xf, .modmsk = SNBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_FREQ_MAX_OS_CYCLES", .desc = "OS Strongest Upper Limit Cycles", .code = 0x6, .cntmsk = 0xf, .modmsk = SNBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_FREQ_MAX_POWER_CYCLES", .desc = "Power Strongest Upper Limit Cycles", .code = 0x5, .cntmsk = 0xf, .modmsk = SNBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_FREQ_MIN_IO_P_CYCLES", .desc = "IO P Limit Strongest Lower Limit Cycles", .code = 0x1 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .ngrp = 1, .modmsk = SNBEP_UNC_PCU_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_p_occupancy_counters), .umasks = snbep_unc_p_occupancy_counters }, { .name = "UNC_P_FREQ_MIN_PERF_P_CYCLES", .desc = "Perf P Limit Strongest Lower Limit Cycles", .code = 0x2 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .ngrp = 1, .modmsk = SNBEP_UNC_PCU_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_p_occupancy_counters), .umasks = snbep_unc_p_occupancy_counters }, { .name = "UNC_P_FREQ_TRANS_CYCLES", .desc = "Cycles spent changing Frequency", .code = 0x0 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .ngrp = 1, .modmsk = SNBEP_UNC_PCU_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_p_occupancy_counters), .umasks = snbep_unc_p_occupancy_counters }, { .name = "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES", .desc = "Memory Phase Shedding Cycles", .code = 0x2f, .cntmsk = 0xf, .modmsk = SNBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_POWER_STATE_OCCUPANCY", .desc = "Number of cores in C0", .code = 0x80, .cntmsk = 0xf, .ngrp = 1, .modmsk = SNBEP_UNC_PCU_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_p_power_state_occupancy), .umasks = snbep_unc_p_power_state_occupancy }, { .name = "UNC_P_PROCHOT_EXTERNAL_CYCLES", .desc = "External Prochot", .code = 0xa, .cntmsk = 0xf, .modmsk = SNBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_PROCHOT_INTERNAL_CYCLES", .desc = "Internal Prochot", .code = 0x9, .cntmsk = 0xf, .modmsk = SNBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_TOTAL_TRANSITION_CYCLES", .desc = "Total Core C State Transition Cycles", .code = 0xb | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = SNBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_VOLT_TRANS_CYCLES_CHANGE", .desc = "Cycles Changing Voltage", .code = 0x3, .cntmsk = 0xf, .modmsk = SNBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_VOLT_TRANS_CYCLES_DECREASE", .desc = "Cycles Decreasing Voltage", .code = 0x2, .cntmsk = 0xf, .modmsk = SNBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_VOLT_TRANS_CYCLES_INCREASE", .desc = "Cycles Increasing Voltage", .code = 0x1, .cntmsk = 0xf, .modmsk = SNBEP_UNC_PCU_ATTRS, }, { .name = "UNC_P_VR_HOT_CYCLES", .desc = "VR Hot", .code = 0x32, .cntmsk = 0xf, .modmsk = SNBEP_UNC_PCU_ATTRS, }, }; libpfm-4.9.0/lib/events/mips_74k_events.h0000664000175000017500000004712713223402656020075 0ustar eranianeranian/* * Copyright (c) 2011 Samara Technology Group, Inc * Contributed by Philip Mucci * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * Based on: * MIPS32 74KTM Processor Core Family Software Users' Manual * Document Number: MD00519 Revision 01.05 March 30, 2011 */ static const mips_entry_t mips_74k_pe []={ { .name = "CYCLES", /* BOTH */ .code = 0x0, .desc = "Cycles", }, { .name = "INSTRUCTIONS", /* BOTH */ .code = 0x1, .desc = "Instructions graduated", }, { .name = "PREDICTED_JR_31", .code = 0x2, .desc = "jr $31 (return) instructions whose target is predicted", }, { .name = "JR_31_MISPREDICTIONS", .code = 0x82, .desc = "jr $31 (return) predicted but guessed wrong", }, { .name = "REDIRECT_STALLS", .code = 0x3, .desc = "Cycles where no instruction is fetched because it has no next address candidate. This includes stalls due to register indirect jumps such as jr, stalls following a wait or eret and stalls dues to exceptions from instruction fetch", }, { .name = "JR_31_NO_PREDICTIONS", .code = 0x83, .desc = "jr $31 (return) instructions fetched and not predicted using RPS", }, { .name = "ITLB_ACCESSES", .code = 0x4, .desc = "ITLB accesses", }, { .name = "ITLB_MISSES", .code = 0x84, .desc = "ITLB misses, which result in a JTLB access", }, { .name = "JTLB_INSN_MISSES", .code = 0x85, .desc = "JTLB instruction access misses (will lead to an exception)", }, { .name = "ICACHE_ACCESSES", .code = 0x6, .desc = "Instruction cache accesses. 74K cores have a 128-bit connection to the I-cache and fetch 4 instructions every access. This counts every such access, including accesses for instructions which are eventually discarded. For example, following a branch which is incorrectly predicted, the 74K core will continue to fetch instructions, which will eventually get thrown away", }, { .name = "ICACHE_MISSES", .code = 0x86, .desc = "I-cache misses. Includes misses resulting from fetch-ahead and speculation", }, { .name = "ICACHE_MISS_STALLS", .code = 0x7, .desc = "Cycles where no instruction is fetched because we missed in the I-cache", }, { .name = "UNCACHED_IFETCH_STALLS", .code = 0x8, .desc = "Cycles where no instruction is fetched because we're waiting for an I-fetch from uncached memory", }, { .name = "PDTRACE_BACK_STALLS", .code = 0x88, .desc = "PDTrace back stalls", }, { .name = "IFU_REPLAYS", .code = 0x9, .desc = "Number of times the instruction fetch pipeline is flushed and replayed because the IFU buffers are full and unable to accept any instructions", }, { .name = "KILLED_FETCH_SLOTS", .code = 0x89, .desc = "Valid fetch slots killed due to taken branches/jumps or stalling instructions", }, { .name = "DDQ0_FULL_DR_STALLS", .code = 0xd, .desc = "Cycles where no instructions are brought into the IDU because the ALU instruction candidate pool is full", }, { .name = "DDQ1_FULL_DR_STALLS", .code = 0x8d, .desc = "Cycles where no instructions are brought into the IDU because the AGEN instruction candidate pool is full", }, { .name = "ALCB_FULL_DR_STALLS", .code = 0xe, .desc = "Cycles where no instructions can be added to the issue pool, because we have run out of ALU completion buffers (CBs)", }, { .name = "AGCB_FULL_DR_STALLS", .code = 0x8e, .desc = "Cycles where no instructions can be added to the issue pool, because we have run out of AGEN completion buffers (CBs)", }, { .name = "CLDQ_FULL_DR_STALLS", .code = 0xf, .desc = "Cycles where no instructions can be added to the issue pool, because we've used all the FIFO entries in the CLDQ which keep track of data coming back from the FPU", }, { .name = "IODQ_FULL_DR_STALLS", .code = 0x8f, .desc = "Cycles where no instructions can be added to the issue pool, because we've filled the in order FIFO used for coprocessor 1 instructions (IOIQ)", }, { .name = "ALU_EMPTY_CYCLES", .code = 0x10, .desc = "Cycles with no ALU-pipe issue; no instructions available", }, { .name = "AGEN_EMPTY_CYCLES", .code = 0x90, .desc = "Cycles with no AGEN-pipe issue; no instructions available", }, { .name = "ALU_OPERANDS_NOT_READY_CYCLES", .code = 0x11, .desc = "Cycles with no ALU-pipe issue; we have instructions, but operands not ready", }, { .name = "AGEN_OPERANDS_NOT_READY_CYCLES", .code = 0x91, .desc = "Cycles with no AGEN-pipe issue; we have instructions, but operands not ready", }, { .name = "ALU_NO_ISSUE_CYCLES", .code = 0x12, .desc = "Cycles with no ALU-pipe issue; we have instructions, but some resource is unavailable. This includes, operands are not ready (same as event 17), div in progress inhibits MDU instructions, CorExtend resource limitation", }, { .name = "AGEN_NO_ISSUE_CYCLES", .code = 0x92, .desc = "Cycles with no AGEN-pipe issue; we have instructions, but some resource is unavailable. This includes, operands are not ready (same as event 17), Non-issued stores blocking ready to issue loads, issued cacheops blocking ready to issue loads", }, { .name = "ALU_BUBBLE_CYCLES", .code = 0x13, .desc = "ALU-pipe bubble issued. The resulting empty pipe stage guarantees that some resource will be unused for a cycle, sometime soon. Used, for example, to guarantee an opportunity to write mfc1 data into a CB", }, { .name = "AGEN_BUBBLE_CYCLES", .code = 0x93, .desc = "AGEN-pipe bubble issued. The resulting empty pipe stage guarantees that some resource will be unused for a cycle, sometime soon. Used, for example, to allow access to the data cache for refill or eviction", }, { .name = "SINGLE_ISSUE_CYCLES", .code = 0x14, .desc = "Cycles when one instruction is issued", }, { .name = "DUAL_ISSUE_CYCLES", .code = 0x94, .desc = "Cycles when two instructions are issued (one ALU, one AGEN)", }, { .name = "OOO_ALU_ISSUE_CYCLES", .code = 0x15, .desc = "Cycles when instructions are issued out of order into the ALU pipe. i.e. instruction issued is not the oldest in the pool", }, { .name = "OOO_AGEN_ISSUE_CYCLES", .code = 0x95, .desc = "Cycles when instructions are issued out of order into the AGEN pipe. i.e. instruction issued is not the oldest in the pool", }, { .name = "JALR_JALR_HB_INSNS", .code = 0x16, .desc = "Graduated JAR/JALR.HB", }, { .name = "DCACHE_LINE_REFILL_REQUESTS", .code = 0x96, .desc = "D-Cache line refill (not LD/ST misses)", }, { .name = "DCACHE_LOAD_ACCESSES", .code = 0x17, .desc = "Cacheable loads - Counts all accesses to the D-cache caused by load instructions. This count includes instructions that do not graduate", }, { .name = "DCACHE_ACCESSES", .code = 0x97, .desc = "All D-cache accesses (loads, stores, prefetch, cacheop etc). This count includes instructions that do not graduate", }, { .name = "DCACHE_WRITEBACKS", .code = 0x18, .desc = "D-Cache writebacks", }, { .name = "DCACHE_MISSES", .code = 0x98, .desc = "D-cache misses. This count is per instruction at graduation and includes load, store, prefetch, synci and address based cacheops", }, { .name = "JTLB_DATA_ACCESSES", .code = 0x19, .desc = "JTLB d-side (data side as opposed to instruction side) accesses", }, { .name = "JTLB_DATA_MISSES", .code = 0x99, .desc = "JTLB translation fails on d-side (data side as opposed to instruction side) accesses. This count includes instructions that do not graduate", }, { .name = "LOAD_STORE_REPLAYS", .code = 0x1a, .desc = "Load/store instruction redirects, which happen when the load/store follows too closely on a possibly matching cacheop", }, { .name = "DCACHE_VTAG_MISMATCH", .code = 0x9a, .desc = "The 74K core's D-cache has an auxiliary virtual tag, used to pick the right line early. When (occasionally) the physical tag match and virtual tag match do not line up, it is treated as a cache miss - in processing the miss the virtual tag is corrected for future accesses. This event counts those bogus misses", }, { .name = "L2_CACHE_WRITEBACKS", .code = 0x1c, .desc = "L2 cache writebacks", }, { .name = "L2_CACHE_ACCESSES", .code = 0x9c, .desc = "L2 cache accesses", }, { .name = "L2_CACHE_MISSES", .code = 0x1d, .desc = "L2 cache misses", }, { .name = "L2_CACHE_MISS_CYCLES", .code = 0x9d, .desc = "L2 cache miss cycles", }, { .name = "FSB_FULL_STALLS", .code = 0x1e, .desc = "Cycles Fill Store Buffer(FSB) are full and cause a pipe stall", }, { .name = "FSB_OVER_50_FULL", .code = 0x9e, .desc = "Cycles Fill Store Buffer(FSB) > 1/2 full", }, { .name = "LDQ_FULL_STALLS", .code = 0x1f, .desc = "Cycles Load Data Queue (LDQ) are full and cause a pipe stall", }, { .name = "LDQ_OVER_50_FULL", .code = 0x9f, .desc = "Cycles Load Data Queue(LDQ) > 1/2 full", }, { .name = "WBB_FULL_STALLS", .code = 0x20, .desc = "Cycles Writeback Buffer(WBB) are full and cause a pipe stall", }, { .name = "WBB_OVER_50_FULL", .code = 0xa0, .desc = "Cycles Writeback Buffer(WBB) > 1/2 full", }, { .name = "LOAD_MISS_CONSUMER_REPLAYS", .code = 0x23, .desc = "Replays following optimistic issue of instruction dependent on load which missed. Counted only when the dependent instruction graduates", }, { .name = "FPU_LOAD_INSNS", .code = 0xa3, .desc = "Floating Point Load instructions graduated", }, { .name = "JR_NON_31_INSNS", .code = 0x24, .desc = "jr (not $31) instructions graduated", }, { .name = "MISPREDICTED_JR_31_INSNS", .code = 0xa4, .desc = "jr $31 mispredicted at graduation", }, { .name = "INT_BRANCH_INSNS", .code = 0x25, .desc = "Integer branch instructions graduated", }, { .name = "FPU_BRANCH_INSNS", .code = 0xa5, .desc = "Floating point branch instructions graduated", }, { .name = "BRANCH_LIKELY_INSNS", .code = 0x26, .desc = "Branch-likely instructions graduated", }, { .name = "MISPREDICTED_BRANCH_LIKELY_INSNS", .code = 0xa6, .desc = "Mispredicted branch-likely instructions graduated", }, { .name = "COND_BRANCH_INSNS", .code = 0x27, .desc = "Conditional branches graduated", }, { .name = "MISPREDICTED_BRANCH_INSNS", .code = 0xa7, .desc = "Mispredicted conditional branches graduated", }, { .name = "INTEGER_INSNS", .code = 0x28, .desc = "Integer instructions graduated (includes nop, ssnop, ehb as well as all arithmetic, logical, shift and extract type operations)", }, { .name = "FPU_INSNS", .code = 0xa8, .desc = "Floating point instructions graduated (but not counting floating point load/store)", }, { .name = "LOAD_INSNS", .code = 0x29, .desc = "Loads graduated (includes floating point)", }, { .name = "STORE_INSNS", .code = 0xa9, .desc = "Stores graduated (includes floating point). Of sc instructions, only successful ones are counted", }, { .name = "J_JAL_INSNS", .code = 0x2a, .desc = "j/jal graduated", }, { .name = "MIPS16_INSNS", .code = 0xaa, .desc = "MIPS16e instructions graduated", }, { .name = "NOP_INSNS", .code = 0x2b, .desc = "no-ops graduated - included (sll, nop, ssnop, ehb)", }, { .name = "NT_MUL_DIV_INSNS", .code = 0xab, .desc = "integer multiply/divides graduated", }, { .name = "DSP_INSNS", .code = 0x2c, .desc = "DSP instructions graduated", }, { .name = "ALU_DSP_SATURATION_INSNS", .code = 0xac, .desc = "ALU-DSP instructions graduated, result was saturated", }, { .name = "DSP_BRANCH_INSNS", .code = 0x2d, .desc = "DSP branch instructions graduated", }, { .name = "MDU_DSP_SATURATION_INSNS", .code = 0xad, .desc = "MDU-DSP instructions graduated, result was saturated", }, { .name = "UNCACHED_LOAD_INSNS", .code = 0x2e, .desc = "Uncached loads graduated", }, { .name = "UNCACHED_STORE_INSNS", .code = 0xae, .desc = "Uncached stores graduated", }, { .name = "EJTAG_INSN_TRIGGERS", .code = 0x31, .desc = "EJTAG instruction triggers", }, { .name = "EJTAG_DATA_TRIGGERS", .code = 0xb1, .desc = "EJTAG data triggers", }, { .name = "CP1_BRANCH_MISPREDICTIONS", .code = 0x32, .desc = "CP1 branches mispredicted", }, { .name = "SC_INSNS", .code = 0x33, .desc = "sc instructions graduated", }, { .name = "FAILED_SC_INSNS", .code = 0xb3, .desc = "sc instructions failed", }, { .name = "PREFETCH_INSNS", .code = 0x34, .desc = "prefetch instructions graduated at the top of LSGB", }, { .name = "CACHE_HIT_PREFETCH_INSNS", .code = 0xb4, .desc = "prefetch instructions which did nothing, because they hit in the cache", }, { .name = "NO_INSN_CYCLES", .code = 0x35, .desc = "Cycles where no instructions graduated", }, { .name = "LOAD_MISS_INSNS", .code = 0xb5, .desc = "Load misses graduated. Includes floating point loads", }, { .name = "ONE_INSN_CYCLES", .code = 0x36, .desc = "Cycles where one instruction graduated", }, { .name = "TWO_INSNS_CYCLES", .code = 0xb6, .desc = "Cycles where two instructions graduated", }, { .name = "GFIFO_BLOCKED_CYCLES", .code = 0x37, .desc = "GFifo blocked cycles", }, { .name = "FPU_STORE_INSNS", .code = 0xb7, .desc = "Floating point stores graduated", }, { .name = "GFIFO_BLOCKED_TLB_CACHE", .code = 0x38, .desc = "GFifo blocked due to TLB or Cacheop", }, { .name = "NO_INSTRUCTIONS_FROM_REPLAY_CYCLES", .code = 0xb8, .desc = "Number of cycles no instructions graduated from the time the pipe was flushed because of a replay until the first new instruction graduates. This is an indicator of the graduation bandwidth loss due to replay. Often times this replay is a result of event 25 and therefor an indicator of bandwidth lost due to cache misses", }, { .name = "MISPREDICTION_BRANCH_NODELAY_CYCLES", .code = 0x39, /* even counters event 57 (raw 57) */ .desc = "Slot 0 misprediction branch instruction graduation cycles without the delay slot" }, { .name = "MISPREDICTION_BRANCH_DELAY_WAIT_CYCLES", .code = 0xb9, /* even counters event 57 (raw 57) */ .desc = "Cycles waiting for delay slot to graduate on a mispredicted branch", }, { .name = "EXCEPTIONS_TAKEN", .code = 0x3a, .desc = "Exceptions taken", }, { .name = "GRADUATION_REPLAYS", .code = 0xba, .desc = "Replays initiated from graduation", }, { .name = "COREEXTEND_EVENTS", .code = 0x3b, .desc = "Implementation specific CorExtend event. The integrator of this core may connect the core pin UDI_perfcnt_event to an event to be counted. This is intended for use with the CorExtend interface", }, { .name = "DSPRAM_EVENTS", .code = 0xbe, .desc = "Implementation-specific DSPRAM event. The integrator of this core may connect the core pin SP_prf_c13_e62_xx to the event to be counted", }, { .name = "L2_CACHE_SINGLE_BIT_ERRORS", .code = 0x3f, .desc = "L2 single-bit errors which were detected", }, { .name = "SYSTEM_EVENT_0", .code = 0x40, .desc = "SI_Event[0] - Implementation-specific system event. The integrator of this core may connect the core pin SI_PCEvent[0] to an event to be counted", }, { .name = "SYSTEM_EVENT_1", .code = 0xc0, .desc = "SI_Event[1] - Implementation-specific system event. The integrator of this core may connect the core pin SI_PCEvent[1] to an event to be counted", }, { .name = "SYSTEM_EVENT_2", .code = 0x41, .desc = "SI_Event[2] - Implementation-specific system event. The integrator of this core may connect the core pin SI_PCEvent[2] to an event to be counted", }, { .name = "SYSTEM_EVENT_3", .code = 0xc1, .desc = "SI_Event[3] - Implementation-specific system event. The integrator of this core may connect the core pin SI_PCEvent[3] to an event to be counted", }, { .name = "SYSTEM_EVENT_4", .code = 0x42, .desc = "SI_Event[4] - Implementation-specific system event. The integrator of this core may connect the core pin SI_PCEvent[4] to an event to be counted", }, { .name = "SYSTEM_EVENT_5", .code = 0xc2, .desc = "SI_Event[5] - Implementation-specific system event. The integrator of this core may connect the core pin SI_PCEvent[5] to an event to be counted", }, { .name = "SYSTEM_EVENT_6", .code = 0x43, .desc = "SI_Event[6] - Implementation-specific system event. The integrator of this core may connect the core pin SI_PCEvent[6] to an event to be counted", }, { .name = "SYSTEM_EVENT_7", .code = 0xc3, .desc = "SI_Event[7] - Implementation-specific system event. The integrator of this core may connect the core pin SI_PCEvent[7] to an event to be counted", }, { .name = "OCP_ALL_REQUESTS", .code = 0x44, .desc = "All OCP requests accepted", }, { .name = "OCP_ALL_CACHEABLE_REQUESTS", .code = 0xc4, .desc = "All OCP cacheable requests accepted", }, { .name = "OCP_READ_REQUESTS", .code = 0x45, .desc = "OCP read requests accepted", }, { .name = "OCP_READ_CACHEABLE_REQUESTS", .code = 0xc5, .desc = "OCP cacheable read requests accepted", }, { .name = "OCP_WRITE_REQUESTS", .code = 0x46, .desc = "OCP write requests accepted", }, { .name = "OCP_WRITE_CACHEABLE REQUESTS", .code = 0xc6, .desc = "OCP cacheable write requests accepted", }, { .name = "OCP_WRITE_DATA_SENT", .code = 0xc7, .desc = "OCP write data sent", }, { .name = "OCP_READ_DATA_RECEIVED", .code = 0xc8, .desc = "OCP read data received", }, { .name = "FSB_LESS_25_FULL", .code = 0x4a, .desc = "Cycles fill store buffer (FSB) < 1/4 full", }, { .name = "FSB_25_50_FULL", .code = 0xca, .desc = "Cycles fill store buffer (FSB) 1/4 to 1/2 full", }, { .name = "LDQ_LESS_25_FULL", .code = 0x4b, .desc = "Cycles load data queue (LDQ) < 1/4 full", }, { .name = "LDQ_25_50_FULL", .code = 0xcb, .desc = "Cycles load data queue (LDQ) 1/4 to 1/2 full", }, { .name = "WBB_LESS_25_FULL", .code = 0x4c, .desc = "Cycles writeback buffer (WBB) < 1/4 full", }, { .name = "WBB_25_50_FULL", .code = 0xcc, .desc = "Cycles writeback buffer (WBB) 1/4 to 1/2 full", }, }; libpfm-4.9.0/lib/events/intel_coreduo_events.h0000664000175000017500000010631313223402656021264 0ustar eranianeranian/* * Copyright (c) 2011 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * This file has been automatically generated. * * PMU: coreduo (Intel Core Duo/Core Solo) */ static const intel_x86_umask_t coreduo_sse_prefetch[]={ { .uname = "NTA", .udesc = "Streaming SIMD Extensions (SSE) Prefetch NTA instructions executed", .ucode = 0x0, }, { .uname = "T1", .udesc = "SSE software prefetch instruction PREFE0xTCT1 retired", .ucode = 0x100, }, { .uname = "T2", .udesc = "SSE software prefetch instruction PREFE0xTCT2 retired", .ucode = 0x200, }, }; static const intel_x86_umask_t coreduo_l2_ads[]={ { .uname = "SELF", .udesc = "This core", .ucode = 0x4000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "BOTH_CORES", .udesc = "Both cores", .ucode = 0xc000, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t coreduo_l2_lines_in[]={ { .uname = "SELF", .udesc = "This core", .ucode = 0x4000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, .grpid = 0, }, { .uname = "BOTH_CORES", .udesc = "Both cores", .ucode = 0xc000, .uflags= INTEL_X86_NCOMBO, .grpid = 0, }, { .uname = "ANY", .udesc = "All inclusive", .ucode = 0x3000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, .grpid = 1, }, { .uname = "PREFETCH", .udesc = "Hardware prefetch only", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO, .grpid = 1, }, }; static const intel_x86_umask_t coreduo_l2_ifetch[]={ { .uname = "MESI", .udesc = "Any cacheline access", .ucode = 0xf00, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, .grpid = 0, }, { .uname = "I_STATE", .udesc = "Invalid cacheline", .ucode = 0x100, .grpid = 0, }, { .uname = "S_STATE", .udesc = "Shared cacheline", .ucode = 0x200, .grpid = 0, }, { .uname = "E_STATE", .udesc = "Exclusive cacheline", .ucode = 0x400, .grpid = 0, }, { .uname = "M_STATE", .udesc = "Modified cacheline", .ucode = 0x800, .grpid = 0, }, { .uname = "SELF", .udesc = "This core", .ucode = 0x4000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, .grpid = 1, }, { .uname = "BOTH_CORES", .udesc = "Both cores", .ucode = 0xc000, .uflags= INTEL_X86_NCOMBO, .grpid = 1, }, }; static const intel_x86_umask_t coreduo_l2_rqsts[]={ { .uname = "MESI", .udesc = "Any cacheline access", .ucode = 0xf00, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, .grpid = 0, }, { .uname = "I_STATE", .udesc = "Invalid cacheline", .ucode = 0x100, .grpid = 0, }, { .uname = "S_STATE", .udesc = "Shared cacheline", .ucode = 0x200, .grpid = 0, }, { .uname = "E_STATE", .udesc = "Exclusive cacheline", .ucode = 0x400, .grpid = 0, }, { .uname = "M_STATE", .udesc = "Modified cacheline", .ucode = 0x800, .grpid = 0, }, { .uname = "SELF", .udesc = "This core", .ucode = 0x4000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, .grpid = 1, }, { .uname = "BOTH_CORES", .udesc = "Both cores", .ucode = 0xc000, .uflags= INTEL_X86_NCOMBO, .grpid = 1, }, { .uname = "ANY", .udesc = "All inclusive", .ucode = 0x3000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, .grpid = 2, }, { .uname = "PREFETCH", .udesc = "Hardware prefetch only", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO, .grpid = 2, }, }; static const intel_x86_umask_t coreduo_thermal_trip[]={ { .uname = "CYCLES", .udesc = "Duration in a thermal trip based on the current core clock", .ucode = 0xc000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "TRIPS", .udesc = "Number of thermal trips", .ucode = 0xc000 | INTEL_X86_MOD_EDGE, .modhw = _INTEL_X86_ATTR_E, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t coreduo_cpu_clk_unhalted[]={ { .uname = "CORE_P", .udesc = "Unhalted core cycles", .ucode = 0x0, }, { .uname = "NONHLT_REF_CYCLES", .udesc = "Non-halted bus cycles", .ucode = 0x100, }, { .uname = "SERIAL_EXECUTION_CYCLES", .udesc = "Non-halted bus cycles of this core executing code while the other core is halted", .ucode = 0x200, }, }; static const intel_x86_umask_t coreduo_dcache_cache_ld[]={ { .uname = "MESI", .udesc = "Any cacheline access", .ucode = 0xf00, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "I_STATE", .udesc = "Invalid cacheline", .ucode = 0x100, }, { .uname = "S_STATE", .udesc = "Shared cacheline", .ucode = 0x200, }, { .uname = "E_STATE", .udesc = "Exclusive cacheline", .ucode = 0x400, }, { .uname = "M_STATE", .udesc = "Modified cacheline", .ucode = 0x800, }, }; static const intel_x86_umask_t coreduo_sse_pre_miss[]={ { .uname = "NTA_MISS", .udesc = "PREFETCHNTA missed all caches", .ucode = 0x0, .uflags= INTEL_X86_NCOMBO, }, { .uname = "T1_MISS", .udesc = "PREFETCHT1 missed all caches", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "T2_MISS", .udesc = "PREFETCHT2 missed all caches", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "STORES_MISS", .udesc = "SSE streaming store instruction missed all caches", .ucode = 0x300, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t coreduo_bus_drdy_clocks[]={ { .uname = "THIS_AGENT", .udesc = "This agent", .ucode = 0x0, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "ALL_AGENTS", .udesc = "Any agent on the bus", .ucode = 0x2000, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t coreduo_simd_int_instructions[]={ { .uname = "MUL", .udesc = "Number of SIMD Integer packed multiply instructions executed", .ucode = 0x100, }, { .uname = "SHIFT", .udesc = "Number of SIMD Integer packed shift instructions executed", .ucode = 0x200, }, { .uname = "PACK", .udesc = "Number of SIMD Integer pack operations instruction executed", .ucode = 0x400, }, { .uname = "UNPACK", .udesc = "Number of SIMD Integer unpack instructions executed", .ucode = 0x800, }, { .uname = "LOGICAL", .udesc = "Number of SIMD Integer packed logical instructions executed", .ucode = 0x1000, }, { .uname = "ARITHMETIC", .udesc = "Number of SIMD Integer packed arithmetic instructions executed", .ucode = 0x2000, }, }; static const intel_x86_umask_t coreduo_mmx_fp_trans[]={ { .uname = "TO_FP", .udesc = "Number of transitions from MMX to X87", .ucode = 0x0, }, { .uname = "TO_MMX", .udesc = "Number of transitions from X87 to MMX", .ucode = 0x100, }, }; static const intel_x86_umask_t coreduo_sse_instructions_retired[]={ { .uname = "SINGLE", .udesc = "Number of SSE/SSE2 single precision instructions retired (packed and scalar)", .ucode = 0x0, .uflags= INTEL_X86_NCOMBO, }, { .uname = "SCALAR_SINGLE", .udesc = "Number of SSE/SSE2 scalar single precision instructions retired", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PACKED_DOUBLE", .udesc = "Number of SSE/SSE2 packed double precision instructions retired", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DOUBLE", .udesc = "Number of SSE/SSE2 scalar double precision instructions retired", .ucode = 0x300, .uflags= INTEL_X86_NCOMBO, }, { .uname = "INT_128", .udesc = "Number of SSE2 128 bit integer instructions retired", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t coreduo_sse_comp_instructions_retired[]={ { .uname = "PACKED_SINGLE", .udesc = "Number of SSE/SSE2 packed single precision compute instructions retired (does not include AND, OR, XOR)", .ucode = 0x0, }, { .uname = "SCALAR_SINGLE", .udesc = "Number of SSE/SSE2 scalar single precision compute instructions retired (does not include AND, OR, XOR)", .ucode = 0x100, }, { .uname = "PACKED_DOUBLE", .udesc = "Number of SSE/SSE2 packed double precision compute instructions retired (does not include AND, OR, XOR)", .ucode = 0x200, }, { .uname = "SCALAR_DOUBLE", .udesc = "Number of SSE/SSE2 scalar double precision compute instructions retired (does not include AND, OR, XOR)", .ucode = 0x300, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t coreduo_fused_uops[]={ { .uname = "ALL", .udesc = "All fused uops retired", .ucode = 0x0, }, { .uname = "LOADS", .udesc = "Fused load uops retired", .ucode = 0x100, }, { .uname = "STORES", .udesc = "Fused load uops retired", .ucode = 0x200, }, }; static const intel_x86_umask_t coreduo_est_trans[]={ { .uname = "ANY", .udesc = "Any Intel Enhanced SpeedStep(R) Technology transitions", .ucode = 0x0, }, { .uname = "FREQ", .udesc = "Intel Enhanced SpeedStep Technology frequency transitions", .ucode = 0x1000, }, }; static const intel_x86_entry_t intel_coreduo_pe[]={ { .name = "UNHALTED_CORE_CYCLES", .desc = "Unhalted core cycles", .modmsk = INTEL_X86_ATTRS, .equiv = "CPU_CLK_UNHALTED:CORE_P", .cntmsk = 0x3, .code = 0x3c, }, { .name = "UNHALTED_REFERENCE_CYCLES", .desc = "Unhalted reference cycles. Measures bus cycles", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x13c, .flags = INTEL_X86_FIXED, }, { .name = "INSTRUCTION_RETIRED", .desc = "Instructions retired", .modmsk = INTEL_X86_ATTRS, .equiv = "INSTR_RET", .cntmsk = 0x3, .code = 0xc0, }, { .name = "INSTRUCTIONS_RETIRED", .desc = "This is an alias for INSTRUCTION_RETIRED", .modmsk = INTEL_X86_ATTRS, .equiv = "INSTRUCTION_RETIRED", .cntmsk = 0x3, .code = 0xc0, }, { .name = "LLC_REFERENCES", .desc = "Last level of cache references", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x4f2e, }, { .name = "LAST_LEVEL_CACHE_REFERENCES", .desc = "This is an alias for LLC_REFERENCES", .modmsk = INTEL_X86_ATTRS, .equiv = "LLC_REFERENCES", .cntmsk = 0x3, .code = 0x4f2e, }, { .name = "LLC_MISSES", .desc = "Last level of cache misses", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x412e, }, { .name = "LAST_LEVEL_CACHE_MISSES", .desc = "This is an alias for LLC_MISSES", .modmsk = INTEL_X86_ATTRS, .equiv = "LLC_MISSES", .cntmsk = 0x3, .code = 0x412e, }, { .name = "BRANCH_INSTRUCTIONS_RETIRED", .desc = "Branch instructions retired", .modmsk = INTEL_X86_ATTRS, .equiv = "BR_INSTR_RET", .cntmsk = 0x3, .code = 0xc4, }, { .name = "MISPREDICTED_BRANCH_RETIRED", .desc = "Mispredicted branch instruction retired", .modmsk = INTEL_X86_ATTRS, .equiv = "BR_MISPRED_RET", .cntmsk = 0x3, .code = 0xc5, }, { .name = "LD_BLOCKS", .desc = "Load operations delayed due to store buffer blocks. The preceding store may be blocked due to unknown address, unknown data, or conflict due to partial overlap between the load and store.", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x3, }, { .name = "SD_DRAINS", .desc = "Cycles while draining store buffers", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x4, }, { .name = "MISALIGN_MEM_REF", .desc = "Misaligned data memory references (MOB splits of loads and stores).", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x5, }, { .name = "SEG_REG_LOADS", .desc = "Segment register loads", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x6, }, { .name = "SSE_PREFETCH", .desc = "Streaming SIMD Extensions (SSE) Prefetch instructions executed", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x7, .numasks = LIBPFM_ARRAY_SIZE(coreduo_sse_prefetch), .ngrp = 1, .umasks = coreduo_sse_prefetch, }, { .name = "SSE_NTSTORES_RET", .desc = "SSE streaming store instruction retired", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x307, }, { .name = "FP_COMPS_OP_EXE", .desc = "FP computational Instruction executed. FADD, FSUB, FCOM, FMULs, MUL, IMUL, FDIVs, DIV, IDIV, FPREMs, FSQRT are included; but exclude FADD or FMUL used in the middle of a transcendental instruction.", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x10, }, { .name = "FP_ASSIST", .desc = "FP exceptions experienced microcode assists", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x2, .code = 0x11, }, { .name = "MUL", .desc = "Multiply operations (a speculative count, including FP and integer multiplies).", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x2, .code = 0x12, }, { .name = "DIV", .desc = "Divide operations (a speculative count, including FP and integer multiplies). ", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x2, .code = 0x13, }, { .name = "CYCLES_DIV_BUSY", .desc = "Cycles the divider is busy ", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x1, .code = 0x14, }, { .name = "L2_ADS", .desc = "L2 Address strobes ", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x21, .numasks = LIBPFM_ARRAY_SIZE(coreduo_l2_ads), .ngrp = 1, .umasks = coreduo_l2_ads, }, { .name = "DBUS_BUSY", .desc = "Core cycle during which data bus was busy (increments by 4)", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x22, .numasks = LIBPFM_ARRAY_SIZE(coreduo_l2_ads), .ngrp = 1, .umasks = coreduo_l2_ads, /* identical to actual umasks list for this event */ }, { .name = "DBUS_BUSY_RD", .desc = "Cycles data bus is busy transferring data to a core (increments by 4) ", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x23, .numasks = LIBPFM_ARRAY_SIZE(coreduo_l2_ads), .ngrp = 1, .umasks = coreduo_l2_ads, /* identical to actual umasks list for this event */ }, { .name = "L2_LINES_IN", .desc = "L2 cache lines allocated", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x24, .numasks = LIBPFM_ARRAY_SIZE(coreduo_l2_lines_in), .ngrp = 2, .umasks = coreduo_l2_lines_in, }, { .name = "L2_M_LINES_IN", .desc = "L2 Modified-state cache lines allocated", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x25, .numasks = LIBPFM_ARRAY_SIZE(coreduo_l2_ads), .ngrp = 1, .umasks = coreduo_l2_ads, /* identical to actual umasks list for this event */ }, { .name = "L2_LINES_OUT", .desc = "L2 cache lines evicted ", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x26, .numasks = LIBPFM_ARRAY_SIZE(coreduo_l2_lines_in), .ngrp = 2, .umasks = coreduo_l2_lines_in, /* identical to actual umasks list for this event */ }, { .name = "L2_M_LINES_OUT", .desc = "L2 Modified-state cache lines evicted ", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x27, .numasks = LIBPFM_ARRAY_SIZE(coreduo_l2_lines_in), .ngrp = 2, .umasks = coreduo_l2_lines_in, /* identical to actual umasks list for this event */ }, { .name = "L2_IFETCH", .desc = "L2 instruction fetches from instruction fetch unit (includes speculative fetches) ", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x28, .numasks = LIBPFM_ARRAY_SIZE(coreduo_l2_ifetch), .ngrp = 2, .umasks = coreduo_l2_ifetch, }, { .name = "L2_LD", .desc = "L2 cache reads (includes speculation) ", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x29, .numasks = LIBPFM_ARRAY_SIZE(coreduo_l2_ifetch), .ngrp = 2, .umasks = coreduo_l2_ifetch, /* identical to actual umasks list for this event */ }, { .name = "L2_ST", .desc = "L2 cache writes (includes speculation)", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x2a, .numasks = LIBPFM_ARRAY_SIZE(coreduo_l2_ifetch), .ngrp = 2, .umasks = coreduo_l2_ifetch, /* identical to actual umasks list for this event */ }, { .name = "L2_RQSTS", .desc = "L2 cache reference requests ", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x2e, .numasks = LIBPFM_ARRAY_SIZE(coreduo_l2_rqsts), .ngrp = 3, .umasks = coreduo_l2_rqsts, }, { .name = "L2_REJECT_CYCLES", .desc = "Cycles L2 is busy and rejecting new requests.", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x30, .numasks = LIBPFM_ARRAY_SIZE(coreduo_l2_rqsts), .ngrp = 3, .umasks = coreduo_l2_rqsts, /* identical to actual umasks list for this event */ }, { .name = "L2_NO_REQUEST_CYCLES", .desc = "Cycles there is no request to access L2.", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x32, .numasks = LIBPFM_ARRAY_SIZE(coreduo_l2_rqsts), .ngrp = 3, .umasks = coreduo_l2_rqsts, /* identical to actual umasks list for this event */ }, { .name = "EST_TRANS", .desc = "Intel Enhanced SpeedStep(R) Technology transitions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x3a, .numasks= LIBPFM_ARRAY_SIZE(coreduo_est_trans), .ngrp = 1, .umasks = coreduo_est_trans, }, { .name = "THERMAL_TRIP", .desc = "Duration in a thermal trip based on the current core clock ", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x3b, .numasks = LIBPFM_ARRAY_SIZE(coreduo_thermal_trip), .ngrp = 1, .umasks = coreduo_thermal_trip, }, { .name = "CPU_CLK_UNHALTED", .desc = "Core cycles when core is not halted", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x3c, .numasks = LIBPFM_ARRAY_SIZE(coreduo_cpu_clk_unhalted), .ngrp = 1, .umasks = coreduo_cpu_clk_unhalted, }, { .name = "DCACHE_CACHE_LD", .desc = "L1 cacheable data read operations", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x40, .numasks = LIBPFM_ARRAY_SIZE(coreduo_dcache_cache_ld), .ngrp = 1, .umasks = coreduo_dcache_cache_ld, }, { .name = "DCACHE_CACHE_ST", .desc = "L1 cacheable data write operations", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x41, .numasks = LIBPFM_ARRAY_SIZE(coreduo_dcache_cache_ld), .ngrp = 1, .umasks = coreduo_dcache_cache_ld, /* identical to actual umasks list for this event */ }, { .name = "DCACHE_CACHE_LOCK", .desc = "L1 cacheable lock read operations to invalid state", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x42, .numasks = LIBPFM_ARRAY_SIZE(coreduo_dcache_cache_ld), .ngrp = 1, .umasks = coreduo_dcache_cache_ld, /* identical to actual umasks list for this event */ }, { .name = "DATA_MEM_REF", .desc = "L1 data read and writes of cacheable and non-cacheable types", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x143, }, { .name = "DATA_MEM_CACHE_REF", .desc = "L1 data cacheable read and write operations.", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x244, }, { .name = "DCACHE_REPL", .desc = "L1 data cache line replacements", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xf45, }, { .name = "DCACHE_M_REPL", .desc = "L1 data M-state cache line allocated", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x46, }, { .name = "DCACHE_M_EVICT", .desc = "L1 data M-state cache line evicted", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x47, }, { .name = "DCACHE_PEND_MISS", .desc = "Weighted cycles of L1 miss outstanding", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x48, }, { .name = "DTLB_MISS", .desc = "Data references that missed TLB", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x49, }, { .name = "SSE_PRE_MISS", .desc = "Streaming SIMD Extensions (SSE) instructions missing all cache levels", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x4b, .numasks = LIBPFM_ARRAY_SIZE(coreduo_sse_pre_miss), .ngrp = 1, .umasks = coreduo_sse_pre_miss, }, { .name = "L1_PREF_REQ", .desc = "L1 prefetch requests due to DCU cache misses", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x4f, }, { .name = "BUS_REQ_OUTSTANDING", .desc = "Weighted cycles of cacheable bus data read requests. This event counts full-line read request from DCU or HW prefetcher, but not RFO, write, instruction fetches, or others.", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x60, .numasks = LIBPFM_ARRAY_SIZE(coreduo_l2_lines_in), .ngrp = 2, .umasks = coreduo_l2_lines_in, /* identical to actual umasks list for this event */ }, { .name = "BUS_BNR_CLOCKS", .desc = "External bus cycles while BNR asserted", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x61, }, { .name = "BUS_DRDY_CLOCKS", .desc = "External bus cycles while DRDY asserted", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x62, .numasks = LIBPFM_ARRAY_SIZE(coreduo_bus_drdy_clocks), .ngrp = 1, .umasks = coreduo_bus_drdy_clocks, }, { .name = "BUS_LOCKS_CLOCKS", .desc = "External bus cycles while bus lock signal asserted", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x63, .numasks = LIBPFM_ARRAY_SIZE(coreduo_l2_ads), .ngrp = 1, .umasks = coreduo_l2_ads, /* identical to actual umasks list for this event */ }, { .name = "BUS_DATA_RCV", .desc = "External bus cycles while bus lock signal asserted", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x4064, }, { .name = "BUS_TRANS_BRD", .desc = "Burst read bus transactions (data or code)", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x65, .numasks = LIBPFM_ARRAY_SIZE(coreduo_l2_ads), .ngrp = 1, .umasks = coreduo_l2_ads, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRANS_RFO", .desc = "Completed read for ownership ", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x66, .numasks = LIBPFM_ARRAY_SIZE(coreduo_l2_lines_in), .ngrp = 2, .umasks = coreduo_l2_lines_in, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRANS_IFETCH", .desc = "Completed instruction fetch transactions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x68, .numasks = LIBPFM_ARRAY_SIZE(coreduo_l2_lines_in), .ngrp = 2, .umasks = coreduo_l2_lines_in, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRANS_INVAL", .desc = "Completed invalidate transactions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x69, .numasks = LIBPFM_ARRAY_SIZE(coreduo_l2_lines_in), .ngrp = 2, .umasks = coreduo_l2_lines_in, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRANS_PWR", .desc = "Completed partial write transactions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x6a, .numasks = LIBPFM_ARRAY_SIZE(coreduo_l2_lines_in), .ngrp = 2, .umasks = coreduo_l2_lines_in, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRANS_P", .desc = "Completed partial transactions (include partial read + partial write + line write)", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x6b, .numasks = LIBPFM_ARRAY_SIZE(coreduo_l2_lines_in), .ngrp = 2, .umasks = coreduo_l2_lines_in, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRANS_IO", .desc = "Completed I/O transactions (read and write)", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x6c, .numasks = LIBPFM_ARRAY_SIZE(coreduo_l2_lines_in), .ngrp = 2, .umasks = coreduo_l2_lines_in, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRANS_DEF", .desc = "Completed defer transactions ", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x206d, .numasks = LIBPFM_ARRAY_SIZE(coreduo_l2_ads), .ngrp = 1, .umasks = coreduo_l2_ads, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRANS_WB", .desc = "Completed writeback transactions from DCU (does not include L2 writebacks)", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xc067, .numasks = LIBPFM_ARRAY_SIZE(coreduo_bus_drdy_clocks), .ngrp = 1, .umasks = coreduo_bus_drdy_clocks, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRANS_BURST", .desc = "Completed burst transactions (full line transactions include reads, write, RFO, and writebacks) ", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xc06e, .numasks = LIBPFM_ARRAY_SIZE(coreduo_bus_drdy_clocks), .ngrp = 1, .umasks = coreduo_bus_drdy_clocks, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRANS_MEM", .desc = "Completed memory transactions. This includes Bus_Trans_Burst + Bus_Trans_P + Bus_Trans_Inval.", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xc06f, .numasks = LIBPFM_ARRAY_SIZE(coreduo_bus_drdy_clocks), .ngrp = 1, .umasks = coreduo_bus_drdy_clocks, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRANS_ANY", .desc = "Any completed bus transactions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xc070, .numasks = LIBPFM_ARRAY_SIZE(coreduo_bus_drdy_clocks), .ngrp = 1, .umasks = coreduo_bus_drdy_clocks, /* identical to actual umasks list for this event */ }, { .name = "BUS_SNOOPS", .desc = "External bus cycles while bus lock signal asserted", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x77, .numasks = LIBPFM_ARRAY_SIZE(coreduo_l2_ifetch), .ngrp = 2, .umasks = coreduo_l2_ifetch, /* identical to actual umasks list for this event */ }, { .name = "DCU_SNOOP_TO_SHARE", .desc = "DCU snoops to share-state L1 cache line due to L1 misses ", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x178, .numasks = LIBPFM_ARRAY_SIZE(coreduo_l2_ads), .ngrp = 1, .umasks = coreduo_l2_ads, /* identical to actual umasks list for this event */ }, { .name = "BUS_NOT_IN_USE", .desc = "Number of cycles there is no transaction from the core", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x7d, .numasks = LIBPFM_ARRAY_SIZE(coreduo_l2_ads), .ngrp = 1, .umasks = coreduo_l2_ads, /* identical to actual umasks list for this event */ }, { .name = "BUS_SNOOP_STALL", .desc = "Number of bus cycles while bus snoop is stalled", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x7e, }, { .name = "ICACHE_READS", .desc = "Number of instruction fetches from ICache, streaming buffers (both cacheable and uncacheable fetches)", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x80, }, { .name = "ICACHE_MISSES", .desc = "Number of instruction fetch misses from ICache, streaming buffers.", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x81, }, { .name = "ITLB_MISSES", .desc = "Number of iITLB misses", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x85, }, { .name = "IFU_MEM_STALL", .desc = "Cycles IFU is stalled while waiting for data from memory", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x86, }, { .name = "ILD_STALL", .desc = "Number of instruction length decoder stalls (Counts number of LCP stalls)", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x87, }, { .name = "BR_INST_EXEC", .desc = "Branch instruction executed (includes speculation).", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x88, }, { .name = "BR_MISSP_EXEC", .desc = "Branch instructions executed and mispredicted at execution (includes branches that do not have prediction or mispredicted)", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x89, }, { .name = "BR_BAC_MISSP_EXEC", .desc = "Branch instructions executed that were mispredicted at front end", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x8a, }, { .name = "BR_CND_EXEC", .desc = "Conditional branch instructions executed", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x8b, }, { .name = "BR_CND_MISSP_EXEC", .desc = "Conditional branch instructions executed that were mispredicted", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x8c, }, { .name = "BR_IND_EXEC", .desc = "Indirect branch instructions executed", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x8d, }, { .name = "BR_IND_MISSP_EXEC", .desc = "Indirect branch instructions executed that were mispredicted", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x8e, }, { .name = "BR_RET_EXEC", .desc = "Return branch instructions executed", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x8f, }, { .name = "BR_RET_MISSP_EXEC", .desc = "Return branch instructions executed that were mispredicted", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x90, }, { .name = "BR_RET_BAC_MISSP_EXEC", .desc = "Return branch instructions executed that were mispredicted at the front end", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x91, }, { .name = "BR_CALL_EXEC", .desc = "Return call instructions executed", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x92, }, { .name = "BR_CALL_MISSP_EXEC", .desc = "Return call instructions executed that were mispredicted", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x93, }, { .name = "BR_IND_CALL_EXEC", .desc = "Indirect call branch instructions executed", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x94, }, { .name = "RESOURCE_STALL", .desc = "Cycles while there is a resource related stall (renaming, buffer entries) as seen by allocator", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xa2, }, { .name = "MMX_INSTR_EXEC", .desc = "Number of MMX instructions executed (does not include MOVQ and MOVD stores)", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xb0, }, { .name = "SIMD_INT_SAT_EXEC", .desc = "Number of SIMD Integer saturating instructions executed", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xb1, }, { .name = "SIMD_INT_INSTRUCTIONS", .desc = "Number of SIMD Integer instructions executed", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xb3, .numasks = LIBPFM_ARRAY_SIZE(coreduo_simd_int_instructions), .ngrp = 1, .umasks = coreduo_simd_int_instructions, }, { .name = "INSTR_RET", .desc = "Number of instruction retired (Macro fused instruction count as 2)", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xc0, }, { .name = "FP_COMP_INSTR_RET", .desc = "Number of FP compute instructions retired (X87 instruction or instruction that contain X87 operations)", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x1, .code = 0xc1, }, { .name = "UOPS_RET", .desc = "Number of micro-ops retired (include fused uops)", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xc2, }, { .name = "SMC_DETECTED", .desc = "Number of times self-modifying code condition detected", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xc3, }, { .name = "BR_INSTR_RET", .desc = "Number of branch instructions retired", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xc4, }, { .name = "BR_MISPRED_RET", .desc = "Number of mispredicted branch instructions retired", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xc5, }, { .name = "CYCLES_INT_MASKED", .desc = "Cycles while interrupt is disabled", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xc6, }, { .name = "CYCLES_INT_PEDNING_MASKED", .desc = "Cycles while interrupt is disabled and interrupts are pending", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xc7, }, { .name = "HW_INT_RX", .desc = "Number of hardware interrupts received", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xc8, }, { .name = "BR_TAKEN_RET", .desc = "Number of taken branch instruction retired", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xc9, }, { .name = "BR_MISPRED_TAKEN_RET", .desc = "Number of taken and mispredicted branch instructions retired", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xca, }, { .name = "MMX_FP_TRANS", .desc = "Transitions from MMX (TM) Instructions to Floating Point Instructions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xcc, .numasks = LIBPFM_ARRAY_SIZE(coreduo_mmx_fp_trans), .ngrp = 1, .umasks = coreduo_mmx_fp_trans, }, { .name = "MMX_ASSIST", .desc = "Number of EMMS executed", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xcd, }, { .name = "MMX_INSTR_RET", .desc = "Number of MMX instruction retired", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xce, }, { .name = "INSTR_DECODED", .desc = "Number of instruction decoded", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xd0, }, { .name = "ESP_UOPS", .desc = "Number of ESP folding instruction decoded", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xd7, }, { .name = "SSE_INSTRUCTIONS_RETIRED", .desc = "Number of SSE/SSE2 instructions retired (packed and scalar)", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xd8, .numasks = LIBPFM_ARRAY_SIZE(coreduo_sse_instructions_retired), .ngrp = 1, .umasks = coreduo_sse_instructions_retired, }, { .name = "SSE_COMP_INSTRUCTIONS_RETIRED", .desc = "Number of computational SSE/SSE2 instructions retired (does not include AND, OR, XOR)", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xd9, .numasks = LIBPFM_ARRAY_SIZE(coreduo_sse_comp_instructions_retired), .ngrp = 1, .umasks = coreduo_sse_comp_instructions_retired, }, { .name = "FUSED_UOPS", .desc = "Fused uops retired", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xda, .numasks = LIBPFM_ARRAY_SIZE(coreduo_fused_uops), .ngrp = 1, .umasks = coreduo_fused_uops, }, { .name = "UNFUSION", .desc = "Number of unfusion events in the ROB (due to exception)", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xdb, }, { .name = "BR_INSTR_DECODED", .desc = "Branch instructions decoded", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xe0, }, { .name = "BTB_MISSES", .desc = "Number of branches the BTB did not produce a prediction", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xe2, }, { .name = "BR_BOGUS", .desc = "Number of bogus branches", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xe4, }, { .name = "BACLEARS", .desc = "Number of BAClears asserted", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xe6, }, { .name = "PREF_RQSTS_UP", .desc = "Number of hardware prefetch requests issued in forward streams", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xf0, }, { .name = "PREF_RQSTS_DN", .desc = "Number of hardware prefetch requests issued in backward streams", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xf8, }, }; libpfm-4.9.0/lib/events/intel_bdx_unc_ha_events.h0000664000175000017500000012256013223402656021720 0ustar eranianeranian/* * Copyright (c) 2017 Google Inc. All rights reserved * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * PMU: bdx_unc_ha */ static intel_x86_umask_t bdx_unc_h_bypass_imc[]={ { .uname = "NOT_TAKEN", .ucode = 0x200, .udesc = "HA to iMC Bypass -- Not Taken", }, { .uname = "TAKEN", .ucode = 0x100, .udesc = "HA to iMC Bypass -- Taken", }, }; static intel_x86_umask_t bdx_unc_h_directory_lookup[]={ { .uname = "NO_SNP", .ucode = 0x200, .udesc = "Directory Lookups -- Snoop Not Needed", }, { .uname = "SNP", .ucode = 0x100, .udesc = "Directory Lookups -- Snoop Needed", }, }; static intel_x86_umask_t bdx_unc_h_directory_update[]={ { .uname = "ANY", .ucode = 0x300, .udesc = "Directory Updates -- Any Directory Update", .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "CLEAR", .ucode = 0x200, .udesc = "Directory Updates -- Directory Clear", }, { .uname = "SET", .ucode = 0x100, .udesc = "Directory Updates -- Directory Set", }, }; static intel_x86_umask_t bdx_unc_h_hitme_hit[]={ { .uname = "ACKCNFLTWBI", .ucode = 0x400, .udesc = "Counts Number of Hits in HitMe Cache -- op is AckCnfltWbI", }, { .uname = "ALL", .ucode = 0xff00, .udesc = "Counts Number of Hits in HitMe Cache -- All Requests", .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "ALLOCS", .ucode = 0x7000, .udesc = "Counts Number of Hits in HitMe Cache -- Allocations", .uflags = INTEL_X86_NCOMBO, }, { .uname = "EVICTS", .ucode = 0x4200, .udesc = "Counts Number of Hits in HitMe Cache -- Allocations", .uflags = INTEL_X86_NCOMBO, }, { .uname = "HOM", .ucode = 0xf00, .udesc = "Counts Number of Hits in HitMe Cache -- HOM Requests", .uflags = INTEL_X86_NCOMBO, }, { .uname = "INVALS", .ucode = 0x2600, .udesc = "Counts Number of Hits in HitMe Cache -- Invalidations", .uflags = INTEL_X86_NCOMBO, }, { .uname = "READ_OR_INVITOE", .ucode = 0x100, .udesc = "Counts Number of Hits in HitMe Cache -- op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE", }, { .uname = "RSP", .ucode = 0x8000, .udesc = "Counts Number of Hits in HitMe Cache -- op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI", }, { .uname = "RSPFWDI_LOCAL", .ucode = 0x2000, .udesc = "Counts Number of Hits in HitMe Cache -- op is RspIFwd or RspIFwdWb for a local request", }, { .uname = "RSPFWDI_REMOTE", .ucode = 0x1000, .udesc = "Counts Number of Hits in HitMe Cache -- op is RspIFwd or RspIFwdWb for a remote request", }, { .uname = "RSPFWDS", .ucode = 0x4000, .udesc = "Counts Number of Hits in HitMe Cache -- op is RsSFwd or RspSFwdWb", }, { .uname = "WBMTOE_OR_S", .ucode = 0x800, .udesc = "Counts Number of Hits in HitMe Cache -- op is WbMtoE or WbMtoS", }, { .uname = "WBMTOI", .ucode = 0x200, .udesc = "Counts Number of Hits in HitMe Cache -- op is WbMtoI", }, }; static intel_x86_umask_t bdx_unc_h_hitme_hit_pv_bits_set[]={ { .uname = "ACKCNFLTWBI", .ucode = 0x400, .udesc = "Accumulates Number of PV bits set on HitMe Cache Hits -- op is AckCnfltWbI", }, { .uname = "ALL", .ucode = 0xff00, .udesc = "Accumulates Number of PV bits set on HitMe Cache Hits -- All Requests", .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "HOM", .ucode = 0xf00, .udesc = "Accumulates Number of PV bits set on HitMe Cache Hits -- HOM Requests", }, { .uname = "READ_OR_INVITOE", .ucode = 0x100, .udesc = "Accumulates Number of PV bits set on HitMe Cache Hits -- op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE", }, { .uname = "RSP", .ucode = 0x8000, .udesc = "Accumulates Number of PV bits set on HitMe Cache Hits -- op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI", }, { .uname = "RSPFWDI_LOCAL", .ucode = 0x2000, .udesc = "Accumulates Number of PV bits set on HitMe Cache Hits -- op is RspIFwd or RspIFwdWb for a local request", }, { .uname = "RSPFWDI_REMOTE", .ucode = 0x1000, .udesc = "Accumulates Number of PV bits set on HitMe Cache Hits -- op is RspIFwd or RspIFwdWb for a remote request", }, { .uname = "RSPFWDS", .ucode = 0x4000, .udesc = "Accumulates Number of PV bits set on HitMe Cache Hits -- op is RsSFwd or RspSFwdWb", }, { .uname = "WBMTOE_OR_S", .ucode = 0x800, .udesc = "Accumulates Number of PV bits set on HitMe Cache Hits -- op is WbMtoE or WbMtoS", }, { .uname = "WBMTOI", .ucode = 0x200, .udesc = "Accumulates Number of PV bits set on HitMe Cache Hits -- op is WbMtoI", }, }; static intel_x86_umask_t bdx_unc_h_hitme_lookup[]={ { .uname = "ACKCNFLTWBI", .ucode = 0x400, .udesc = "Counts Number of times HitMe Cache is accessed -- op is AckCnfltWbI", }, { .uname = "ALL", .ucode = 0xff00, .udesc = "Counts Number of times HitMe Cache is accessed -- All Requests", .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "ALLOCS", .ucode = 0x7000, .udesc = "Counts Number of times HitMe Cache is accessed -- Allocations", }, { .uname = "HOM", .ucode = 0xf00, .udesc = "Counts Number of times HitMe Cache is accessed -- HOM Requests", .uflags = INTEL_X86_NCOMBO, }, { .uname = "INVALS", .ucode = 0x2600, .udesc = "Counts Number of times HitMe Cache is accessed -- Invalidations", .uflags = INTEL_X86_NCOMBO, }, { .uname = "READ_OR_INVITOE", .ucode = 0x100, .udesc = "Counts Number of times HitMe Cache is accessed -- op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE", }, { .uname = "RSP", .ucode = 0x8000, .udesc = "Counts Number of times HitMe Cache is accessed -- op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI", }, { .uname = "RSPFWDI_LOCAL", .ucode = 0x2000, .udesc = "Counts Number of times HitMe Cache is accessed -- op is RspIFwd or RspIFwdWb for a local request", }, { .uname = "RSPFWDI_REMOTE", .ucode = 0x1000, .udesc = "Counts Number of times HitMe Cache is accessed -- op is RspIFwd or RspIFwdWb for a remote request", }, { .uname = "RSPFWDS", .ucode = 0x4000, .udesc = "Counts Number of times HitMe Cache is accessed -- op is RsSFwd or RspSFwdWb", }, { .uname = "WBMTOE_OR_S", .ucode = 0x800, .udesc = "Counts Number of times HitMe Cache is accessed -- op is WbMtoE or WbMtoS", }, { .uname = "WBMTOI", .ucode = 0x200, .udesc = "Counts Number of times HitMe Cache is accessed -- op is WbMtoI", }, }; static intel_x86_umask_t bdx_unc_h_igr_no_credit_cycles[]={ { .uname = "AD_QPI0", .ucode = 0x100, .udesc = "Cycles without QPI Ingress Credits -- AD to QPI Link 0", }, { .uname = "AD_QPI1", .ucode = 0x200, .udesc = "Cycles without QPI Ingress Credits -- AD to QPI Link 1", }, { .uname = "AD_QPI2", .ucode = 0x1000, .udesc = "Cycles without QPI Ingress Credits -- BL to QPI Link 0", }, { .uname = "BL_QPI0", .ucode = 0x400, .udesc = "Cycles without QPI Ingress Credits -- BL to QPI Link 0", }, { .uname = "BL_QPI1", .ucode = 0x800, .udesc = "Cycles without QPI Ingress Credits -- BL to QPI Link 1", }, { .uname = "BL_QPI2", .ucode = 0x2000, .udesc = "Cycles without QPI Ingress Credits -- BL to QPI Link 1", }, }; static intel_x86_umask_t bdx_unc_h_imc_reads[]={ { .uname = "NORMAL", .ucode = 0x100, .udesc = "HA to iMC Normal Priority Reads Issued -- Normal Priority", .uflags = INTEL_X86_DFL, }, }; static intel_x86_umask_t bdx_unc_h_imc_writes[]={ { .uname = "ALL", .ucode = 0xf00, .udesc = "HA to iMC Full Line Writes Issued -- All Writes", .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "FULL", .ucode = 0x100, .udesc = "HA to iMC Full Line Writes Issued -- Full Line Non-ISOCH", }, { .uname = "FULL_ISOCH", .ucode = 0x400, .udesc = "HA to iMC Full Line Writes Issued -- ISOCH Full Line", }, { .uname = "PARTIAL", .ucode = 0x200, .udesc = "HA to iMC Full Line Writes Issued -- Partial Non-ISOCH", }, { .uname = "PARTIAL_ISOCH", .ucode = 0x800, .udesc = "HA to iMC Full Line Writes Issued -- ISOCH Partial", }, }; static intel_x86_umask_t bdx_unc_h_osb[]={ { .uname = "CANCELLED", .ucode = 0x1000, .udesc = "OSB Snoop Broadcast -- Cancelled", }, { .uname = "INVITOE_LOCAL", .ucode = 0x400, .udesc = "OSB Snoop Broadcast -- Local InvItoE", }, { .uname = "READS_LOCAL", .ucode = 0x200, .udesc = "OSB Snoop Broadcast -- Local Reads", }, { .uname = "READS_LOCAL_USEFUL", .ucode = 0x2000, .udesc = "OSB Snoop Broadcast -- Reads Local - Useful", }, { .uname = "REMOTE", .ucode = 0x800, .udesc = "OSB Snoop Broadcast -- Remote", }, { .uname = "REMOTE_USEFUL", .ucode = 0x4000, .udesc = "OSB Snoop Broadcast -- Remote - Useful", }, }; static intel_x86_umask_t bdx_unc_h_osb_edr[]={ { .uname = "ALL", .ucode = 0x100, .udesc = "OSB Early Data Return -- All", .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "READS_LOCAL_I", .ucode = 0x200, .udesc = "OSB Early Data Return -- Reads to Local I", }, { .uname = "READS_LOCAL_S", .ucode = 0x800, .udesc = "OSB Early Data Return -- Reads to Local S", }, { .uname = "READS_REMOTE_I", .ucode = 0x400, .udesc = "OSB Early Data Return -- Reads to Remote I", }, { .uname = "READS_REMOTE_S", .ucode = 0x1000, .udesc = "OSB Early Data Return -- Reads to Remote S", }, }; static intel_x86_umask_t bdx_unc_h_requests[]={ { .uname = "INVITOE_LOCAL", .ucode = 0x1000, .udesc = "Read and Write Requests -- Local InvItoEs", }, { .uname = "INVITOE_REMOTE", .ucode = 0x2000, .udesc = "Read and Write Requests -- Remote InvItoEs", }, { .uname = "READS", .ucode = 0x300, .udesc = "Read and Write Requests -- Reads", .uflags = INTEL_X86_NCOMBO, }, { .uname = "READS_LOCAL", .ucode = 0x100, .udesc = "Read and Write Requests -- Local Reads", }, { .uname = "READS_REMOTE", .ucode = 0x200, .udesc = "Read and Write Requests -- Remote Reads", }, { .uname = "WRITES", .ucode = 0xc00, .udesc = "Read and Write Requests -- Writes", .uflags = INTEL_X86_NCOMBO, }, { .uname = "WRITES_LOCAL", .ucode = 0x400, .udesc = "Read and Write Requests -- Local Writes", }, { .uname = "WRITES_REMOTE", .ucode = 0x800, .udesc = "Read and Write Requests -- Remote Writes", }, }; static intel_x86_umask_t bdx_unc_h_ring_ad_used[]={ { .uname = "CCW", .ucode = 0xc00, .udesc = "Counterclockwise", .uflags = INTEL_X86_NCOMBO, }, { .uname = "CCW_EVEN", .ucode = 0x400, .udesc = "Counterclockwise and Even", }, { .uname = "CCW_ODD", .ucode = 0x800, .udesc = "Counterclockwise and Odd", }, { .uname = "CW", .ucode = 0x300, .udesc = "Clockwise", .uflags = INTEL_X86_NCOMBO, }, { .uname = "CW_EVEN", .ucode = 0x100, .udesc = "Clockwise and Even", }, { .uname = "CW_ODD", .ucode = 0x200, .udesc = "Clockwise and Odd", }, }; static intel_x86_umask_t bdx_unc_h_rpq_cycles_no_reg_credits[]={ { .uname = "CHN0", .ucode = 0x100, .udesc = "iMC RPQ Credits Empty - Regular -- Channel 0", .uflags = INTEL_X86_NCOMBO, }, { .uname = "CHN1", .ucode = 0x200, .udesc = "iMC RPQ Credits Empty - Regular -- Channel 1", .uflags = INTEL_X86_NCOMBO, }, { .uname = "CHN2", .ucode = 0x400, .udesc = "iMC RPQ Credits Empty - Regular -- Channel 2", .uflags = INTEL_X86_NCOMBO, }, { .uname = "CHN3", .ucode = 0x800, .udesc = "iMC RPQ Credits Empty - Regular -- Channel 3", .uflags = INTEL_X86_NCOMBO, }, }; static intel_x86_umask_t bdx_unc_h_sbo0_credits_acquired[]={ { .uname = "AD", .ucode = 0x100, .udesc = "For AD Ring", }, { .uname = "BL", .ucode = 0x200, .udesc = "For BL Ring", }, }; static intel_x86_umask_t bdx_unc_h_snoops_rsp_after_data[]={ { .uname = "LOCAL", .ucode = 0x100, .udesc = "Data beat the Snoop Responses -- Local Requests", .uflags = INTEL_X86_NCOMBO, }, { .uname = "REMOTE", .ucode = 0x200, .udesc = "Data beat the Snoop Responses -- Remote Requests", .uflags = INTEL_X86_NCOMBO, }, }; static intel_x86_umask_t bdx_unc_h_snoop_cycles_ne[]={ { .uname = "ALL", .ucode = 0x300, .udesc = "Cycles with Snoops Outstanding -- All Requests", .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "LOCAL", .ucode = 0x100, .udesc = "Cycles with Snoops Outstanding -- Local Requests", }, { .uname = "REMOTE", .ucode = 0x200, .udesc = "Cycles with Snoops Outstanding -- Remote Requests", }, }; static intel_x86_umask_t bdx_unc_h_snoop_occupancy[]={ { .uname = "LOCAL", .ucode = 0x100, .udesc = "Tracker Snoops Outstanding Accumulator -- Local Requests", .uflags = INTEL_X86_NCOMBO, }, { .uname = "REMOTE", .ucode = 0x200, .udesc = "Tracker Snoops Outstanding Accumulator -- Remote Requests", .uflags = INTEL_X86_NCOMBO, }, }; static intel_x86_umask_t bdx_unc_h_snoop_resp[]={ { .uname = "RSPCNFLCT", .ucode = 0x4000, .udesc = "Snoop Responses Received -- RSPCNFLCT*", }, { .uname = "RSPI", .ucode = 0x100, .udesc = "Snoop Responses Received -- RspI", }, { .uname = "RSPIFWD", .ucode = 0x400, .udesc = "Snoop Responses Received -- RspIFwd", }, { .uname = "RSPS", .ucode = 0x200, .udesc = "Snoop Responses Received -- RspS", }, { .uname = "RSPSFWD", .ucode = 0x800, .udesc = "Snoop Responses Received -- RspSFwd", }, { .uname = "RSP_FWD_WB", .ucode = 0x2000, .udesc = "Snoop Responses Received -- Rsp*Fwd*WB", }, { .uname = "RSP_WB", .ucode = 0x1000, .udesc = "Snoop Responses Received -- Rsp*WB", }, }; static intel_x86_umask_t bdx_unc_h_snp_resp_recv_local[]={ { .uname = "OTHER", .ucode = 0x8000, .udesc = "Snoop Responses Received Local -- Other", }, { .uname = "RSPCNFLCT", .ucode = 0x4000, .udesc = "Snoop Responses Received Local -- RspCnflct", }, { .uname = "RSPI", .ucode = 0x100, .udesc = "Snoop Responses Received Local -- RspI", }, { .uname = "RSPIFWD", .ucode = 0x400, .udesc = "Snoop Responses Received Local -- RspIFwd", }, { .uname = "RSPS", .ucode = 0x200, .udesc = "Snoop Responses Received Local -- RspS", }, { .uname = "RSPSFWD", .ucode = 0x800, .udesc = "Snoop Responses Received Local -- RspSFwd", }, { .uname = "RSPxFWDxWB", .ucode = 0x2000, .udesc = "Snoop Responses Received Local -- Rsp*FWD*WB", }, { .uname = "RSPxWB", .ucode = 0x1000, .udesc = "Snoop Responses Received Local -- Rsp*WB", }, }; static intel_x86_umask_t bdx_unc_h_stall_no_sbo_credit[]={ { .uname = "SBO0_AD", .ucode = 0x100, .udesc = "Stall on No Sbo Credits -- For SBo0, AD Ring", }, { .uname = "SBO0_BL", .ucode = 0x400, .udesc = "Stall on No Sbo Credits -- For SBo0, BL Ring", }, { .uname = "SBO1_AD", .ucode = 0x200, .udesc = "Stall on No Sbo Credits -- For SBo1, AD Ring", }, { .uname = "SBO1_BL", .ucode = 0x800, .udesc = "Stall on No Sbo Credits -- For SBo1, BL Ring", }, }; static intel_x86_umask_t bdx_unc_h_tad_requests_g0[]={ { .uname = "REGION0", .ucode = 0x100, .udesc = "HA Requests to a TAD Region - Group 0 -- TAD Region 0", .uflags = INTEL_X86_NCOMBO, }, { .uname = "REGION1", .ucode = 0x200, .udesc = "HA Requests to a TAD Region - Group 0 -- TAD Region 1", .uflags = INTEL_X86_NCOMBO, }, { .uname = "REGION2", .ucode = 0x400, .udesc = "HA Requests to a TAD Region - Group 0 -- TAD Region 2", .uflags = INTEL_X86_NCOMBO, }, { .uname = "REGION3", .ucode = 0x800, .udesc = "HA Requests to a TAD Region - Group 0 -- TAD Region 3", .uflags = INTEL_X86_NCOMBO, }, { .uname = "REGION4", .ucode = 0x1000, .udesc = "HA Requests to a TAD Region - Group 0 -- TAD Region 4", .uflags = INTEL_X86_NCOMBO, }, { .uname = "REGION5", .ucode = 0x2000, .udesc = "HA Requests to a TAD Region - Group 0 -- TAD Region 5", .uflags = INTEL_X86_NCOMBO, }, { .uname = "REGION6", .ucode = 0x4000, .udesc = "HA Requests to a TAD Region - Group 0 -- TAD Region 6", .uflags = INTEL_X86_NCOMBO, }, { .uname = "REGION7", .ucode = 0x8000, .udesc = "HA Requests to a TAD Region - Group 0 -- TAD Region 7", .uflags = INTEL_X86_NCOMBO, }, }; static intel_x86_umask_t bdx_unc_h_tad_requests_g1[]={ { .uname = "REGION10", .ucode = 0x400, .udesc = "HA Requests to a TAD Region - Group 1 -- TAD Region 10", .uflags = INTEL_X86_NCOMBO, }, { .uname = "REGION11", .ucode = 0x800, .udesc = "HA Requests to a TAD Region - Group 1 -- TAD Region 11", .uflags = INTEL_X86_NCOMBO, }, { .uname = "REGION8", .ucode = 0x100, .udesc = "HA Requests to a TAD Region - Group 1 -- TAD Region 8", .uflags = INTEL_X86_NCOMBO, }, { .uname = "REGION9", .ucode = 0x200, .udesc = "HA Requests to a TAD Region - Group 1 -- TAD Region 9", .uflags = INTEL_X86_NCOMBO, }, }; static intel_x86_umask_t bdx_unc_h_tracker_cycles_full[]={ { .uname = "ALL", .ucode = 0x200, .udesc = "Tracker Cycles Full -- Cycles Completely Used", .uflags = INTEL_X86_DFL, }, { .uname = "GP", .ucode = 0x100, .udesc = "Tracker Cycles Full -- Cycles GP Completely Used", }, }; static intel_x86_umask_t bdx_unc_h_tracker_cycles_ne[]={ { .uname = "ALL", .ucode = 0x300, .udesc = "Tracker Cycles Not Empty -- All Requests", .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "LOCAL", .ucode = 0x100, .udesc = "Tracker Cycles Not Empty -- Local Requests", }, { .uname = "REMOTE", .ucode = 0x200, .udesc = "Tracker Cycles Not Empty -- Remote Requests", }, }; static intel_x86_umask_t bdx_unc_h_tracker_occupancy[]={ { .uname = "INVITOE_LOCAL", .ucode = 0x4000, .udesc = "Tracker Occupancy Accumultor -- Local InvItoE Requests", }, { .uname = "INVITOE_REMOTE", .ucode = 0x8000, .udesc = "Tracker Occupancy Accumultor -- Remote InvItoE Requests", }, { .uname = "READS_LOCAL", .ucode = 0x400, .udesc = "Tracker Occupancy Accumultor -- Local Read Requests", }, { .uname = "READS_REMOTE", .ucode = 0x800, .udesc = "Tracker Occupancy Accumultor -- Remote Read Requests", }, { .uname = "WRITES_LOCAL", .ucode = 0x1000, .udesc = "Tracker Occupancy Accumultor -- Local Write Requests", }, { .uname = "WRITES_REMOTE", .ucode = 0x2000, .udesc = "Tracker Occupancy Accumultor -- Remote Write Requests", }, }; static intel_x86_umask_t bdx_unc_h_tracker_pending_occupancy[]={ { .uname = "LOCAL", .ucode = 0x100, .udesc = "Data Pending Occupancy Accumultor -- Local Requests", .uflags = INTEL_X86_NCOMBO, }, { .uname = "REMOTE", .ucode = 0x200, .udesc = "Data Pending Occupancy Accumultor -- Remote Requests", .uflags = INTEL_X86_NCOMBO, }, }; static intel_x86_umask_t bdx_unc_h_txr_ad_cycles_full[]={ { .uname = "ALL", .ucode = 0x300, .udesc = "All", .uflags = INTEL_X86_DFL, }, { .uname = "SCHED0", .ucode = 0x100, .udesc = "Scheduler 0", }, { .uname = "SCHED1", .ucode = 0x200, .udesc = "Scheduler 1", }, }; static intel_x86_umask_t bdx_unc_h_txr_bl[]={ { .uname = "DRS_CACHE", .ucode = 0x100, .udesc = "Outbound DRS Ring Transactions to Cache -- Data to Cache", }, { .uname = "DRS_CORE", .ucode = 0x200, .udesc = "Outbound DRS Ring Transactions to Cache -- Data to Core", }, { .uname = "DRS_QPI", .ucode = 0x400, .udesc = "Outbound DRS Ring Transactions to Cache -- Data to QPI", }, }; static intel_x86_umask_t bdx_unc_h_txr_starved[]={ { .uname = "AK", .ucode = 0x100, .udesc = "Injection Starvation -- For AK Ring", }, { .uname = "BL", .ucode = 0x200, .udesc = "Injection Starvation -- For BL Ring", }, }; static intel_x86_umask_t bdx_unc_h_wpq_cycles_no_reg_credits[]={ { .uname = "CHN0", .ucode = 0x100, .udesc = "HA iMC CHN0 WPQ Credits Empty - Regular -- Channel 0", .uflags = INTEL_X86_NCOMBO, }, { .uname = "CHN1", .ucode = 0x200, .udesc = "HA iMC CHN0 WPQ Credits Empty - Regular -- Channel 1", .uflags = INTEL_X86_NCOMBO, }, { .uname = "CHN2", .ucode = 0x400, .udesc = "HA iMC CHN0 WPQ Credits Empty - Regular -- Channel 2", .uflags = INTEL_X86_NCOMBO, }, { .uname = "CHN3", .ucode = 0x800, .udesc = "HA iMC CHN0 WPQ Credits Empty - Regular -- Channel 3", .uflags = INTEL_X86_NCOMBO, }, }; static intel_x86_entry_t intel_bdx_unc_h_pe[]={ /* ADDR_OPC_MATCH not supported (linux kernel has no support for HA OPC yet*/ { .name = "UNC_H_BT_CYCLES_NE", .code = 0x42, .desc = "Cycles the Backup Tracker (BT) is not empty. The BT is the actual HOM tracker in IVT.", .modmsk = BDX_UNC_HA_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_H_BT_OCCUPANCY", .code = 0x43, .desc = "Accumulates the occupancy of te HA BT pool in every cycle. This can be used with the 'not empty' stat to calculate the average queue occupancy or the 'allocations' stat to calculate average queue latency. HA BTs are allocated as son as a request enters the HA and are released after the snoop response and data return and the response is returned to the ring", .modmsk = BDX_UNC_HA_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_H_BYPASS_IMC", .code = 0x14, .desc = "Counts the number of times when the HA was able to bypass was attempted. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filted by when the bypass was taken and when it was not.", .modmsk = BDX_UNC_HA_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_h_bypass_imc, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_h_bypass_imc), }, { .name = "UNC_H_CONFLICT_CYCLES", .code = 0xb, .desc = "TBD", .modmsk = BDX_UNC_HA_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_H_CLOCKTICKS", .code = 0x0, .desc = "Counts the number of uclks in the HA. This will be slightly different than the count in the Ubox because of enable/freeze delays. The HA is on the other side of the die from the fixed Ubox uclk counter, so the drift could be somewhat larger than in units that are closer like the QPI Agent.", .modmsk = BDX_UNC_HA_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_H_DIRECT2CORE_COUNT", .code = 0x11, .desc = "Number of Direct2Core messages sent", .modmsk = BDX_UNC_HA_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_H_DIRECT2CORE_CYCLES_DISABLED", .code = 0x12, .desc = "Number of cycles in which Direct2Core was disabled", .modmsk = BDX_UNC_HA_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_H_DIRECT2CORE_TXN_OVERRIDE", .code = 0x13, .desc = "Number of Reads where Direct2Core overridden", .modmsk = BDX_UNC_HA_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_H_DIRECTORY_LAT_OPT", .code = 0x41, .desc = "Directory Latency Optimization Data Return Path Taken. When directory mode is enabled and the directory retuned for a read is Dir=I, then data can be returned using a faster path if certain conditions are met (credits, free pipeline, etc).", .modmsk = BDX_UNC_HA_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_H_DIRECTORY_LOOKUP", .code = 0xc, .desc = "Counts the number of transactions that looked up the directory. Can be filtered by requests that had to snoop and those that did not have to.", .modmsk = BDX_UNC_HA_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_h_directory_lookup, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_h_directory_lookup), }, { .name = "UNC_H_DIRECTORY_UPDATE", .code = 0xd, .desc = "Counts the number of directory updates that were required. These result in writes to the memory controller. This can be filtered by directory sets and directory clears.", .modmsk = BDX_UNC_HA_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_h_directory_update, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_h_directory_update), }, { .name = "UNC_H_HITME_HIT", .code = 0x71, .desc = "", .modmsk = BDX_UNC_HA_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_h_hitme_hit, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_h_hitme_hit), }, { .name = "UNC_H_HITME_HIT_PV_BITS_SET", .code = 0x72, .desc = "", .modmsk = BDX_UNC_HA_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_h_hitme_hit_pv_bits_set, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_h_hitme_hit_pv_bits_set), }, { .name = "UNC_H_HITME_LOOKUP", .code = 0x70, .desc = "", .modmsk = BDX_UNC_HA_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_h_hitme_lookup, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_h_hitme_lookup), }, { .name = "UNC_H_IGR_NO_CREDIT_CYCLES", .code = 0x22, .desc = "Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent. This can be filtered by the different credit pools and the different links.", .modmsk = BDX_UNC_HA_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_h_igr_no_credit_cycles, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_h_igr_no_credit_cycles), }, { .name = "UNC_H_IMC_READS", .code = 0x17, .desc = "Count of the number of reads issued to any of the memory controller channels. This can be filtered by the priority of the reads.", .modmsk = BDX_UNC_HA_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_h_imc_reads, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_h_imc_reads), }, { .name = "UNC_H_IMC_RETRY", .code = 0x1e, .desc = "", .modmsk = BDX_UNC_HA_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_H_IMC_WRITES", .code = 0x1a, .desc = "Counts the total number of full line writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH.", .modmsk = BDX_UNC_HA_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_h_imc_writes, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_h_imc_writes), }, { .name = "UNC_H_OSB", .code = 0x53, .desc = "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.", .modmsk = BDX_UNC_HA_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_h_osb, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_h_osb), }, { .name = "UNC_H_OSB_EDR", .code = 0x54, .desc = "Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return", .modmsk = BDX_UNC_HA_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_h_osb_edr, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_h_osb_edr), }, { .name = "UNC_H_REQUESTS", .code = 0x1, .desc = "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).", .modmsk = BDX_UNC_HA_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_h_requests, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_h_requests), }, { .name = "UNC_H_RING_AD_USED", .code = 0x3e, .desc = "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", .modmsk = BDX_UNC_HA_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_h_ring_ad_used, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_h_ring_ad_used), }, { .name = "UNC_H_RING_AK_USED", .code = 0x3f, .desc = "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", .modmsk = BDX_UNC_HA_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_h_ring_ad_used, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_h_ring_ad_used), }, { .name = "UNC_H_RING_BL_USED", .code = 0x40, .desc = "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", .modmsk = BDX_UNC_HA_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_h_ring_ad_used, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_h_ring_ad_used), }, { .name = "UNC_H_RPQ_CYCLES_NO_REG_CREDITS", .code = 0x15, .desc = "Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMCs RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given iven time.", .modmsk = BDX_UNC_HA_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_h_rpq_cycles_no_reg_credits, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_h_rpq_cycles_no_reg_credits), }, { .name = "UNC_H_SBO0_CREDITS_ACQUIRED", .code = 0x68, .desc = "Number of Sbo 0 credits acquired in a given cycle, per ring.", .modmsk = BDX_UNC_HA_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_h_sbo0_credits_acquired, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_h_sbo0_credits_acquired), }, { .name = "UNC_H_SBO0_CREDIT_OCCUPANCY", .code = 0x6a, .desc = "Number of Sbo 0 credits in use in a given cycle, per ring.", .modmsk = BDX_UNC_HA_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_h_sbo0_credits_acquired, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_h_sbo0_credits_acquired), }, { .name = "UNC_H_SBO1_CREDITS_ACQUIRED", .code = 0x69, .desc = "Number of Sbo 1 credits acquired in a given cycle, per ring.", .modmsk = BDX_UNC_HA_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_h_sbo0_credits_acquired, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_h_sbo0_credits_acquired), }, { .name = "UNC_H_SBO1_CREDIT_OCCUPANCY", .code = 0x6b, .desc = "Number of Sbo 1 credits in use in a given cycle, per ring.", .modmsk = BDX_UNC_HA_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_h_sbo0_credits_acquired, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_h_sbo0_credits_acquired), }, { .name = "UNC_H_SNOOPS_RSP_AFTER_DATA", .code = 0xa, .desc = "Counts the number of reads when the snoop was on the critical path to the data return.", .modmsk = BDX_UNC_HA_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_h_snoops_rsp_after_data, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_h_snoops_rsp_after_data), }, { .name = "UNC_H_SNOOP_CYCLES_NE", .code = 0x8, .desc = "Counts cycles when one or more snoops are outstanding.", .modmsk = BDX_UNC_HA_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_h_snoop_cycles_ne, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_h_snoop_cycles_ne), }, { .name = "UNC_H_SNOOP_OCCUPANCY", .code = 0x9, .desc = "Accumulates the occupancy of either the local HA tracker pool that have snoops pending in every cycle. This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency. HA trackers are allocated as soon as a request enters the HA if an HT (HomeTracker) entry is available and this occupancy is decremented when all the snoop responses have retureturned.", .modmsk = BDX_UNC_HA_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_h_snoop_occupancy, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_h_snoop_occupancy), }, { .name = "UNC_H_SNOOP_RESP", .code = 0x21, .desc = "Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.", .modmsk = BDX_UNC_HA_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_h_snoop_resp, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_h_snoop_resp), }, { .name = "UNC_H_SNP_RESP_RECV_LOCAL", .code = 0x60, .desc = "Number of snoop responses received for a Local request", .modmsk = BDX_UNC_HA_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_h_snp_resp_recv_local, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_h_snp_resp_recv_local), }, { .name = "UNC_H_STALL_NO_SBO_CREDIT", .code = 0x6c, .desc = "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.", .modmsk = BDX_UNC_HA_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_h_stall_no_sbo_credit, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_h_stall_no_sbo_credit), }, { .name = "UNC_H_TAD_REQUESTS_G0", .code = 0x1b, .desc = "Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save powewer.", .modmsk = BDX_UNC_HA_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_h_tad_requests_g0, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_h_tad_requests_g0), }, { .name = "UNC_H_TAD_REQUESTS_G1", .code = 0x1c, .desc = "Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 8 to 10. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save powewer.", .modmsk = BDX_UNC_HA_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_h_tad_requests_g1, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_h_tad_requests_g1), }, { .name = "UNC_H_TRACKER_CYCLES_FULL", .code = 0x2, .desc = "Counts the number of cycles when the local HA tracker pool is completely used. This can be used with edge detect to identify the number of situations when the pool became fully utilized. This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure. In other words, the system could be starved for RTIDs but not fill up the HA trackers. HA trackers are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.", .modmsk = BDX_UNC_HA_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_h_tracker_cycles_full, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_h_tracker_cycles_full), }, { .name = "UNC_H_TRACKER_CYCLES_NE", .code = 0x3, .desc = "Counts the number of cycles when the local HA tracker pool is not empty. This can be used with edge detect to identify the number of situations when the pool became empty. This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure. In other words, this buffer could be completely empty, but there may still be credits in use by the CBos. This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occpancy. HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.", .modmsk = BDX_UNC_HA_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_h_tracker_cycles_ne, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_h_tracker_cycles_ne), }, { .name = "UNC_H_TRACKER_OCCUPANCY", .code = 0x4, .desc = "Accumulates the occupancy of the local HA tracker pool in every cycle. This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency. HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the rhe ring.", .modmsk = BDX_UNC_HA_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_h_tracker_occupancy, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_h_tracker_occupancy), }, { .name = "UNC_H_TRACKER_PENDING_OCCUPANCY", .code = 0x5, .desc = "Accumulates the number of transactions that have data from the memory controller until they get scheduled to the Egress. This can be used to calculate the queuing latency for two things. (1) If the system is waiting for snoops, this will increase. (2) If the system cant schedule to the Egress because of either (a) Egress Credits or (b) QPI BL IGR credits for remote requestss.", .modmsk = BDX_UNC_HA_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_h_tracker_pending_occupancy, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_h_tracker_pending_occupancy), }, { .name = "UNC_H_TXR_AD_CYCLES_FULL", .code = 0x2a, .desc = "AD Egress Full", .modmsk = BDX_UNC_HA_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_h_txr_ad_cycles_full, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_h_txr_ad_cycles_full), }, { .name = "UNC_H_TXR_AK_CYCLES_FULL", .code = 0x32, .desc = "AK Egress Full", .modmsk = BDX_UNC_HA_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_h_txr_ad_cycles_full, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_h_txr_ad_cycles_full), /* shared */ }, { .name = "UNC_H_TXR_BL", .code = 0x10, .desc = "Counts the number of DRS messages sent out on the BL ring. This can be filtered by the destination.", .modmsk = BDX_UNC_HA_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_h_txr_bl, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_h_txr_bl), }, { .name = "UNC_H_TXR_BL_CYCLES_FULL", .code = 0x36, .desc = "BL Egress Full", .modmsk = BDX_UNC_HA_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_h_txr_ad_cycles_full, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_h_txr_ad_cycles_full), /* shared */ }, { .name = "UNC_H_TXR_STARVED", .code = 0x6d, .desc = "Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.", .modmsk = BDX_UNC_HA_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_h_txr_starved, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_h_txr_starved), }, { .name = "UNC_H_WPQ_CYCLES_NO_REG_CREDITS", .code = 0x18, .desc = "Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMCs WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given iven time.", .modmsk = BDX_UNC_HA_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_h_wpq_cycles_no_reg_credits, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_h_wpq_cycles_no_reg_credits), }, }; libpfm-4.9.0/lib/events/intel_wsm_events.h0000664000175000017500000023333213223402656020434 0ustar eranianeranian/* * Copyright (c) 2011 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * This file has been automatically generated. * * PMU: wsm (Intel Westmere (single-socket)) */ static const intel_x86_umask_t wsm_uops_decoded[]={ { .uname = "ESP_FOLDING", .udesc = "Stack pointer instructions decoded", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ESP_SYNC", .udesc = "Stack pointer sync operations", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "MS", .udesc = "Counts the number of uops decoded by the Microcode Sequencer (MS). The MS delivers uops when the instruction is more than 4 uops long or a microcode assist is occurring.", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "MS_CYCLES_ACTIVE", .udesc = "Uops decoded by Microcode Sequencer", .uequiv = "MS:c=1", .ucode = 0x200 | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, }, { .uname = "STALL_CYCLES", .udesc = "Cycles no Uops are decoded", .ucode = 0x100 | INTEL_X86_MOD_INV | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t wsm_bpu_clears[]={ { .uname = "EARLY", .udesc = "Early Branch Prediction Unit clears", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "LATE", .udesc = "Late Branch Prediction Unit clears", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t wsm_uops_retired[]={ { .uname = "ANY", .udesc = "Uops retired (Precise Event)", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS | INTEL_X86_DFL, }, { .uname = "MACRO_FUSED", .udesc = "Macro-fused Uops retired (Precise Event)", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "RETIRE_SLOTS", .udesc = "Retirement slots used (Precise Event)", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "STALL_CYCLES", .udesc = "Cycles Uops are not retiring (Precise Event)", .uequiv = "ANY:c=1:i=1", .ucode = 0x100 | INTEL_X86_MOD_INV | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, .modhw = _INTEL_X86_ATTR_I | _INTEL_X86_ATTR_C, }, { .uname = "TOTAL_CYCLES", .udesc = "Total cycles using precise uop retired event (Precise Event)", .uequiv = "ANY:c=16:i=1", .ucode = 0x100 | INTEL_X86_MOD_INV | (0x10 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, .modhw = _INTEL_X86_ATTR_I | _INTEL_X86_ATTR_C, }, { .uname = "ACTIVE_CYCLES", .udesc = "Alias for TOTAL_CYCLES (Precise Event)", .uequiv = "ANY:c=1", .ucode = 0x100 | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, .modhw = _INTEL_X86_ATTR_C, }, }; static const intel_x86_umask_t wsm_br_misp_retired[]={ { .uname = "ALL_BRANCHES", .udesc = "Mispredicted retired branch instructions (Precise Event)", .ucode = 0x0, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "NEAR_CALL", .udesc = "Mispredicted near retired calls (Precise Event)", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "CONDITIONAL", .udesc = "Mispredicted conditional branches retired (Precise Event)", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, }; static const intel_x86_umask_t wsm_ept[]={ { .uname = "WALK_CYCLES", .udesc = "Extended Page Table walk cycles", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t wsm_uops_executed[]={ { .uname = "PORT0", .udesc = "Uops executed on port 0 (integer arithmetic, SIMD and FP add uops)", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PORT1", .udesc = "Uops executed on port 1 (integer arithmetic, SIMD, integer shift, FP multiply, FP divide uops)", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PORT2_CORE", .udesc = "Uops executed on port 2 on any thread (load uops) (core count only)", .ucode = 0x400 | INTEL_X86_MOD_ANY, .modhw = _INTEL_X86_ATTR_T, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PORT3_CORE", .udesc = "Uops executed on port 3 on any thread (store uops) (core count only)", .ucode = 0x800 | INTEL_X86_MOD_ANY, .modhw = _INTEL_X86_ATTR_T, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PORT4_CORE", .udesc = "Uops executed on port 4 on any thread (handle store values for stores on port 3) (core count only)", .ucode = 0x1000 | INTEL_X86_MOD_ANY, .modhw = _INTEL_X86_ATTR_T, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PORT5", .udesc = "Uops executed on port 5", .ucode = 0x2000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PORT015", .udesc = "Uops issued on ports 0, 1 or 5", .ucode = 0x4000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PORT234_CORE", .udesc = "Uops issued on ports 2, 3 or 4 on any thread (core count only)", .ucode = 0x8000 | INTEL_X86_MOD_ANY, .modhw = _INTEL_X86_ATTR_T, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PORT015_STALL_CYCLES", .udesc = "Cycles no Uops issued on ports 0, 1 or 5", .uequiv = "PORT015:c=1:i=1", .ucode = 0x4000 | INTEL_X86_MOD_INV | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, }, { .uname = "CORE_ACTIVE_CYCLES_NO_PORT5", .udesc = "Cycles in which uops are executed only on port0-4 on any thread (core count only)", .ucode = 0x1f00 | INTEL_X86_MOD_ANY | (0x1 << INTEL_X86_CMASK_BIT), .modhw = _INTEL_X86_ATTR_C | _INTEL_X86_ATTR_T, .uflags= INTEL_X86_NCOMBO, }, { .uname = "CORE_ACTIVE_CYCLES", .udesc = "Cycles in which uops are executed on any port any thread (core count only)", .ucode = 0x3f00 | INTEL_X86_MOD_ANY | (0x1 << INTEL_X86_CMASK_BIT), .modhw = _INTEL_X86_ATTR_C | _INTEL_X86_ATTR_T, .uflags= INTEL_X86_NCOMBO, }, { .uname = "CORE_STALL_CYCLES", .udesc = "Cycles in which no uops are executed on any port any thread (core count only)", .ucode = 0x3f00 | INTEL_X86_MOD_ANY | INTEL_X86_MOD_INV | (0x1 << INTEL_X86_CMASK_BIT), .modhw = _INTEL_X86_ATTR_C | _INTEL_X86_ATTR_T | _INTEL_X86_ATTR_I, .uflags= INTEL_X86_NCOMBO, }, { .uname = "CORE_STALL_CYCLES_NO_PORT5", .udesc = "Cycles in which no uops are executed on any port0-4 on any thread (core count only)", .ucode = 0x1f00 | INTEL_X86_MOD_ANY | INTEL_X86_MOD_INV | (0x1 << INTEL_X86_CMASK_BIT), .modhw = _INTEL_X86_ATTR_C | _INTEL_X86_ATTR_T | _INTEL_X86_ATTR_I, .uflags= INTEL_X86_NCOMBO, }, { .uname = "CORE_STALL_COUNT", .udesc = "Number of transitions from stalled to uops to execute on any port any thread (core count only)", .uequiv = "CORE_STALL_CYCLES:e:t:i:c=1", .ucode = 0x3f00 | INTEL_X86_MOD_EDGE | INTEL_X86_MOD_ANY | INTEL_X86_MOD_INV | (0x1 << INTEL_X86_CMASK_BIT), .modhw = _INTEL_X86_ATTR_E | _INTEL_X86_ATTR_T | _INTEL_X86_ATTR_I | _INTEL_X86_ATTR_C, .uflags = INTEL_X86_NCOMBO, }, { .uname = "CORE_STALL_COUNT_NO_PORT5", .udesc = "Number of transitions from stalled to uops to execute on ports 0-4 on any thread (core count only)", .uequiv = "CORE_STALL_CYCLES_NO_PORT5:e:t:i:c=1", .ucode = 0x1f00 | INTEL_X86_MOD_EDGE | INTEL_X86_MOD_ANY | INTEL_X86_MOD_INV | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t wsm_inst_retired[]={ { .uname = "ANY_P", .udesc = "Instructions Retired (Precise Event)", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "ANY", .udesc = "Instructions Retired (Precise Event)", .ucode = 0x100, .uequiv = "ANY_P", .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS | INTEL_X86_DFL, }, { .uname = "X87", .udesc = "Retired floating-point operations (Precise Event)", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "MMX", .udesc = "Retired MMX instructions (Precise Event)", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "TOTAL_CYCLES", .udesc = "Total cycles (Precise Event)", .uequiv = "ANY_P:c=16:i=1", .ucode = 0x100 | INTEL_X86_MOD_INV | (0x10 << INTEL_X86_CMASK_BIT), /* inv=1, cmask=16 */ .modhw = _INTEL_X86_ATTR_I | _INTEL_X86_ATTR_C, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, }; static const intel_x86_umask_t wsm_ild_stall[]={ { .uname = "ANY", .udesc = "Any Instruction Length Decoder stall cycles", .uequiv = "IQ_FULL:LCP:MRU:REGEN", .ucode = 0xf00, .uflags= INTEL_X86_DFL, }, { .uname = "IQ_FULL", .udesc = "Instruction Queue full stall cycles", .ucode = 0x400, }, { .uname = "LCP", .udesc = "Length Change Prefix stall cycles", .ucode = 0x100, }, { .uname = "MRU", .udesc = "Stall cycles due to BPU MRU bypass", .ucode = 0x200, }, { .uname = "REGEN", .udesc = "Regen stall cycles", .ucode = 0x800, }, }; static const intel_x86_umask_t wsm_dtlb_load_misses[]={ { .uname = "ANY", .udesc = "DTLB load misses", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "PDE_MISS", .udesc = "DTLB load miss caused by low part of address", .ucode = 0x2000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "STLB_HIT", .udesc = "DTLB second level hit", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "WALK_COMPLETED", .udesc = "DTLB load miss page walks complete", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "WALK_CYCLES", .udesc = "DTLB load miss page walk cycles", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "LARGE_WALK_COMPLETED", .udesc = "DTLB load miss large page walk cycles", .ucode = 0x8000, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t wsm_l2_lines_in[]={ { .uname = "ANY", .udesc = "L2 lines allocated", .ucode = 0x700, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "E_STATE", .udesc = "L2 lines allocated in the E state", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "S_STATE", .udesc = "L2 lines allocated in the S state", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t wsm_ssex_uops_retired[]={ { .uname = "PACKED_DOUBLE", .udesc = "SIMD Packed-Double Uops retired (Precise Event)", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "PACKED_SINGLE", .udesc = "SIMD Packed-Single Uops retired (Precise Event)", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "SCALAR_DOUBLE", .udesc = "SIMD Scalar-Double Uops retired (Precise Event)", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "SCALAR_SINGLE", .udesc = "SIMD Scalar-Single Uops retired (Precise Event)", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "VECTOR_INTEGER", .udesc = "SIMD Vector Integer Uops retired (Precise Event)", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, }; static const intel_x86_umask_t wsm_store_blocks[]={ { .uname = "AT_RET", .udesc = "Loads delayed with at-Retirement block code", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "L1D_BLOCK", .udesc = "Cacheable loads delayed with L1D block code", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t wsm_fp_mmx_trans[]={ { .uname = "ANY", .udesc = "All Floating Point to and from MMX transitions", .ucode = 0x300, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "TO_FP", .udesc = "Transitions from MMX to Floating Point instructions", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "TO_MMX", .udesc = "Transitions from Floating Point to MMX instructions", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t wsm_cache_lock_cycles[]={ { .uname = "L1D", .udesc = "Cycles L1D locked", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "L1D_L2", .udesc = "Cycles L1D and L2 locked", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t wsm_l3_lat_cache[]={ { .uname = "MISS", .udesc = "Last level cache miss", .ucode = 0x4100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "REFERENCE", .udesc = "Last level cache reference", .ucode = 0x4f00, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t wsm_simd_int_64[]={ { .uname = "PACK", .udesc = "SIMD integer 64 bit pack operations", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PACKED_ARITH", .udesc = "SIMD integer 64 bit arithmetic operations", .ucode = 0x2000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PACKED_LOGICAL", .udesc = "SIMD integer 64 bit logical operations", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PACKED_MPY", .udesc = "SIMD integer 64 bit packed multiply operations", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PACKED_SHIFT", .udesc = "SIMD integer 64 bit shift operations", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "SHUFFLE_MOVE", .udesc = "SIMD integer 64 bit shuffle/move operations", .ucode = 0x4000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "UNPACK", .udesc = "SIMD integer 64 bit unpack operations", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t wsm_br_misp_exec[]={ { .uname = "ANY", .udesc = "Mispredicted branches executed", .ucode = 0x7f00, .uflags= INTEL_X86_NCOMBO, }, { .uname = "COND", .udesc = "Mispredicted conditional branches executed", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DIRECT", .udesc = "Mispredicted unconditional branches executed", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DIRECT_NEAR_CALL", .udesc = "Mispredicted non call branches executed", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "INDIRECT_NEAR_CALL", .udesc = "Mispredicted indirect call branches executed", .ucode = 0x2000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "INDIRECT_NON_CALL", .udesc = "Mispredicted indirect non call branches executed", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "NEAR_CALLS", .udesc = "Mispredicted call branches executed", .ucode = 0x3000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "NON_CALLS", .udesc = "Mispredicted non call branches executed", .ucode = 0x700, .uflags= INTEL_X86_NCOMBO, }, { .uname = "RETURN_NEAR", .udesc = "Mispredicted return branches executed", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "TAKEN", .udesc = "Mispredicted taken branches executed", .ucode = 0x4000, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t wsm_baclear[]={ { .uname = "BAD_TARGET", .udesc = "BACLEAR asserted with bad target address", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "CLEAR", .udesc = "BACLEAR asserted, regardless of cause", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t wsm_dtlb_misses[]={ { .uname = "ANY", .udesc = "DTLB misses", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "LARGE_WALK_COMPLETED", .udesc = "DTLB miss large page walks", .ucode = 0x8000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "STLB_HIT", .udesc = "DTLB first level misses but second level hit", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "WALK_COMPLETED", .udesc = "DTLB miss page walks", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "WALK_CYCLES", .udesc = "DTLB miss page walk cycles", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PDE_MISS", .udesc = "DTLB miss caused by low part of address", .ucode = 0x2000, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t wsm_mem_inst_retired[]={ { .uname = "LATENCY_ABOVE_THRESHOLD", .udesc = "Memory instructions retired above programmed clocks, minimum threshold value is 3, (Precise Event and ldlat required)", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS | INTEL_X86_LDLAT, }, { .uname = "LOADS", .udesc = "Instructions retired which contains a load (Precise Event)", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "STORES", .udesc = "Instructions retired which contains a store (Precise Event)", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, }; static const intel_x86_umask_t wsm_uops_issued[]={ { .uname = "ANY", .udesc = "Uops issued", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "STALL_CYCLES", .udesc = "Cycles stalled no issued uops", .uequiv = "ANY:c=1:i=1", .ucode = 0x100 | INTEL_X86_MOD_INV | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, }, { .uname = "FUSED", .udesc = "Fused Uops issued", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "CYCLES_ALL_THREADS", .udesc = "Cycles uops issued on either threads (core count)", .uequiv = "ANY:c=1:t=1", .ucode = 0x100 | INTEL_X86_MOD_ANY | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, }, { .uname = "CORE_STALL_CYCLES", .udesc = "Cycles no uops issued on any threads (core count)", .uequiv = "ANY:c=1:i=1:t=1", .ucode = 0x100 | INTEL_X86_MOD_ANY | INTEL_X86_MOD_INV | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t wsm_l2_rqsts[]={ { .uname = "IFETCH_HIT", .udesc = "L2 instruction fetch hits", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "IFETCH_MISS", .udesc = "L2 instruction fetch misses", .ucode = 0x2000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "IFETCHES", .udesc = "L2 instruction fetches", .ucode = 0x3000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "LD_HIT", .udesc = "L2 load hits", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "LD_MISS", .udesc = "L2 load misses", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "LOADS", .udesc = "L2 requests", .ucode = 0x300, .uflags= INTEL_X86_NCOMBO, }, { .uname = "MISS", .udesc = "All L2 misses", .ucode = 0xaa00, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PREFETCH_HIT", .udesc = "L2 prefetch hits", .ucode = 0x4000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PREFETCH_MISS", .udesc = "L2 prefetch misses", .ucode = 0x8000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PREFETCHES", .udesc = "All L2 prefetches", .ucode = 0xc000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "REFERENCES", .udesc = "All L2 requests", .ucode = 0xff00, .uflags= INTEL_X86_NCOMBO, }, { .uname = "RFO_HIT", .udesc = "L2 RFO hits", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "RFO_MISS", .udesc = "L2 RFO misses", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "RFOS", .udesc = "L2 RFO requests", .ucode = 0xc00, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t wsm_load_dispatch[]={ { .uname = "ANY", .udesc = "All loads dispatched", .ucode = 0x700, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "RS", .udesc = "Number of loads dispatched from the Reservation Station (RS) that bypass the Memory Order Buffer", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "RS_DELAYED", .udesc = "Number of delayed RS dispatches at the stage latch", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "MOB", .udesc = "Number of loads dispatched from Reservation Station (RS)", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t wsm_snoopq_requests[]={ { .uname = "CODE", .udesc = "Snoop code requests", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DATA", .udesc = "Snoop data requests", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "INVALIDATE", .udesc = "Snoop invalidate requests", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t wsm_offcore_requests[]={ { .uname = "ANY", .udesc = "All offcore requests", .ucode = 0x8000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "ANY_READ", .udesc = "Offcore read requests", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ANY_RFO", .udesc = "Offcore RFO requests", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DEMAND_READ_CODE", .udesc = "Offcore demand code read requests", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DEMAND_READ_DATA", .udesc = "Offcore demand data read requests", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DEMAND_RFO", .udesc = "Offcore demand RFO requests", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "L1D_WRITEBACK", .udesc = "Offcore L1 data cache writebacks", .ucode = 0x4000, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t wsm_load_block[]={ { .uname = "OVERLAP_STORE", .udesc = "Loads that partially overlap an earlier store", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t wsm_misalign_memory[]={ { .uname = "STORE", .udesc = "Store referenced with misaligned address", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t wsm_machine_clears[]={ { .uname = "MEM_ORDER", .udesc = "Execution pipeline restart due to Memory ordering conflicts ", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "CYCLES", .udesc = "Cycles machine clear is asserted", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "SMC", .udesc = "Self-modifying code detected", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t wsm_fp_comp_ops_exe[]={ { .uname = "MMX", .udesc = "MMX Uops", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "SSE_DOUBLE_PRECISION", .udesc = "SSE FP double precision Uops", .ucode = 0x8000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "SSE_FP", .udesc = "SSE and SSE2 FP Uops", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "SSE_FP_PACKED", .udesc = "SSE FP packed Uops", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "SSE_FP_SCALAR", .udesc = "SSE FP scalar Uops", .ucode = 0x2000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "SSE_SINGLE_PRECISION", .udesc = "SSE FP single precision Uops", .ucode = 0x4000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "SSE2_INTEGER", .udesc = "SSE2 integer Uops", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "X87", .udesc = "Computational floating-point operations executed", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t wsm_br_inst_retired[]={ { .uname = "ALL_BRANCHES", .udesc = "Retired branch instructions (Precise Event)", .ucode = 0x0, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS | INTEL_X86_DFL, }, { .uname = "CONDITIONAL", .udesc = "Retired conditional branch instructions (Precise Event)", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "NEAR_CALL", .udesc = "Retired near call instructions (Precise Event)", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, }; static const intel_x86_umask_t wsm_large_itlb[]={ { .uname = "HIT", .udesc = "Large ITLB hit", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t wsm_lsd[]={ { .uname = "UOPS", .udesc = "Counts the number of micro-ops delivered by LSD", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ACTIVE", .udesc = "Cycles is which at least one micro-op delivered by LSD", .uequiv = "UOPS:c=1", .ucode = 0x100 | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, }, { .uname = "INACTIVE", .udesc = "Cycles is which no micro-op is delivered by LSD", .uequiv = "UOPS:c=1:i=1", .ucode = 0x100 | INTEL_X86_MOD_INV | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t wsm_l2_lines_out[]={ { .uname = "ANY", .udesc = "L2 lines evicted", .ucode = 0xf00, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "DEMAND_CLEAN", .udesc = "L2 lines evicted by a demand request", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DEMAND_DIRTY", .udesc = "L2 modified lines evicted by a demand request", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PREFETCH_CLEAN", .udesc = "L2 lines evicted by a prefetch request", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PREFETCH_DIRTY", .udesc = "L2 modified lines evicted by a prefetch request", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t wsm_itlb_misses[]={ { .uname = "ANY", .udesc = "ITLB miss", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "WALK_COMPLETED", .udesc = "ITLB miss page walks", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "WALK_CYCLES", .udesc = "ITLB miss page walk cycles", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "LARGE_WALK_COMPLETED", .udesc = "Number of completed large page walks due to misses in the STLB", .ucode = 0x8000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "STLB_HIT", .udesc = "ITLB misses hitting second level TLB", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t wsm_l1d_prefetch[]={ { .uname = "MISS", .udesc = "L1D hardware prefetch misses", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "REQUESTS", .udesc = "L1D hardware prefetch requests", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "TRIGGERS", .udesc = "L1D hardware prefetch requests triggered", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t wsm_sq_misc[]={ { .uname = "LRU_HINTS", .udesc = "Super Queue LRU hints sent to LLC", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "SPLIT_LOCK", .udesc = "Super Queue lock splits across a cache line", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t wsm_fp_assist[]={ { .uname = "ALL", .udesc = "All X87 Floating point assists (Precise Event)", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS | INTEL_X86_DFL, }, { .uname = "INPUT", .udesc = "X87 Floating point assists for invalid input value (Precise Event)", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "OUTPUT", .udesc = "X87 Floating point assists for invalid output value (Precise Event)", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, }; static const intel_x86_umask_t wsm_simd_int_128[]={ { .uname = "PACK", .udesc = "128 bit SIMD integer pack operations", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PACKED_ARITH", .udesc = "128 bit SIMD integer arithmetic operations", .ucode = 0x2000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PACKED_LOGICAL", .udesc = "128 bit SIMD integer logical operations", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PACKED_MPY", .udesc = "128 bit SIMD integer multiply operations", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PACKED_SHIFT", .udesc = "128 bit SIMD integer shift operations", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "SHUFFLE_MOVE", .udesc = "128 bit SIMD integer shuffle/move operations", .ucode = 0x4000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "UNPACK", .udesc = "128 bit SIMD integer unpack operations", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t wsm_offcore_requests_outstanding[]={ { .uname = "ANY_READ", .udesc = "Outstanding offcore reads", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DEMAND_READ_CODE", .udesc = "Outstanding offcore demand code reads", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DEMAND_READ_DATA", .udesc = "Outstanding offcore demand data reads", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DEMAND_RFO", .udesc = "Outstanding offcore demand RFOs", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ANY_READ_NOT_EMPTY", .udesc = "Number of cycles with offcore reads busy", .uequiv = "ANY_READ:c=1", .ucode = 0x800 | (0x1 << INTEL_X86_CMASK_BIT), /* cmask=1 */ .modhw = _INTEL_X86_ATTR_C, .uflags = INTEL_X86_NCOMBO, }, { .uname = "READ_DATA_NOT_EMPTY", .udesc = "Number of cycles with offcore demand data reads busy", .uequiv = "DEMAND_READ_DATA:c=1", .ucode = 0x800 | (0x1 << INTEL_X86_CMASK_BIT), /* cmask=1 */ .modhw = _INTEL_X86_ATTR_C, .uflags = INTEL_X86_NCOMBO, }, { .uname = "READ_CODE_NOT_EMPTY", .udesc = "Number of cycles with offcore code reads busy", .uequiv = "DEMAND_READ_CODE:c=1", .ucode = 0x200 | (0x1 << INTEL_X86_CMASK_BIT), /* cmask=1 */ .modhw = _INTEL_X86_ATTR_C, .uflags = INTEL_X86_NCOMBO, }, { .uname = "RFO_NOT_EMPTY", .udesc = "Number of cycles with offcore rfo busy", .uequiv = "DEMAND_RFO:c=1", .ucode = 0x200 | (0x1 << INTEL_X86_CMASK_BIT), /* cmask=1 */ .modhw = _INTEL_X86_ATTR_C, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t wsm_mem_store_retired[]={ { .uname = "DTLB_MISS", .udesc = "Retired stores that miss the DTLB (Precise Event)", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS | INTEL_X86_DFL, }, }; static const intel_x86_umask_t wsm_inst_decoded[]={ { .uname = "DEC0", .udesc = "Instructions that must be decoded by decoder 0", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t wsm_macro_insts[]={ { .uname = "DECODED", .udesc = "Instructions decoded", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t wsm_arith[]={ { .uname = "CYCLES_DIV_BUSY", .udesc = "Counts the number of cycles the divider is busy executing divide or square root operations. The divide can be integer, X87 or Streaming SIMD Extensions (SSE). The square root operation can be either X87 or SSE. Count may be incorrect when HT is on", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DIV", .udesc = "Counts the number of divide or square root operations. The divide can be integer, X87 or Streaming SIMD Extensions (SSE). The square root operation can be either X87 or SSE. Count may be incorrect when HT is on", .uequiv = "CYCLES_DIV_BUSY:c=1:i=1:e=1", .ucode = 0x100 | INTEL_X86_MOD_EDGE | INTEL_X86_MOD_INV | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, }, { .uname = "MUL", .udesc = "Counts the number of multiply operations executed. This includes integer as well as floating point multiply operations but excludes DPPS mul and MPSAD. Count may be incorrect when HT is on", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t wsm_l2_transactions[]={ { .uname = "ANY", .udesc = "All L2 transactions", .ucode = 0x8000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "FILL", .udesc = "L2 fill transactions", .ucode = 0x2000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "IFETCH", .udesc = "L2 instruction fetch transactions", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "L1D_WB", .udesc = "L1D writeback to L2 transactions", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "LOAD", .udesc = "L2 Load transactions", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PREFETCH", .udesc = "L2 prefetch transactions", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "RFO", .udesc = "L2 RFO transactions", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "WB", .udesc = "L2 writeback to LLC transactions", .ucode = 0x4000, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t wsm_sb_drain[]={ { .uname = "ANY", .udesc = "All Store buffer stall cycles", .ucode = 0x700, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t wsm_mem_uncore_retired[]={ { .uname = "LOCAL_HITM", .udesc = "Load instructions retired that HIT modified data in sibling core (Precise Event)", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, .umodel = PFM_PMU_INTEL_WSM_DP, }, { .uname = "LOCAL_DRAM_AND_REMOTE_CACHE_HIT", .udesc = "Load instructions retired local dram and remote cache HIT data sources (Precise Event)", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, .umodel = PFM_PMU_INTEL_WSM_DP, }, { .uname = "REMOTE_DRAM", .udesc = "Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, .umodel = PFM_PMU_INTEL_WSM_DP, }, { .uname = "UNCACHEABLE", .udesc = "Load instructions retired IO (Precise Event)", .ucode = 0x8000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "REMOTE_HITM", .udesc = "Retired loads that hit remote socket in modified state (Precise Event)", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, .umodel = PFM_PMU_INTEL_WSM_DP, }, { .uname = "OTHER_LLC_MISS", .udesc = "Load instructions retired other LLC miss (Precise Event)", .ucode = 0x2000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, .umodel = PFM_PMU_INTEL_WSM_DP, }, { .uname = "UNKNOWN_SOURCE", .udesc = "Load instructions retired unknown LLC miss (Precise Event)", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, .umodel = PFM_PMU_INTEL_WSM_DP, }, { .uname = "LOCAL_DRAM", .udesc = "Retired loads with a data source of local DRAM or locally homed remote cache HITM (Precise Event)", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, .umodel = PFM_PMU_INTEL_WSM, }, { .uname = "OTHER_CORE_L2_HITM", .udesc = "Retired loads instruction that hit modified data in sibling core (Precise Event)", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, .umodel = PFM_PMU_INTEL_WSM, }, { .uname = "REMOTE_CACHE_LOCAL_HOME_HIT", .udesc = "Retired loads instruction that hit remote cache hit data source (Precise Event)", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, .umodel = PFM_PMU_INTEL_WSM, }, { .uname = "REMOTE_DRAM", .udesc = "Retired loads instruction remote DRAM and remote home-remote cache HITM (Precise Event)", .ucode = 0x2000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, .umodel = PFM_PMU_INTEL_WSM, }, }; static const intel_x86_umask_t wsm_l2_data_rqsts[]={ { .uname = "ANY", .udesc = "All L2 data requests", .ucode = 0xff00, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "DEMAND_E_STATE", .udesc = "L2 data demand loads in E state", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DEMAND_I_STATE", .udesc = "L2 data demand loads in I state (misses)", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DEMAND_M_STATE", .udesc = "L2 data demand loads in M state", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DEMAND_MESI", .udesc = "L2 data demand requests", .ucode = 0xf00, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DEMAND_S_STATE", .udesc = "L2 data demand loads in S state", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PREFETCH_E_STATE", .udesc = "L2 data prefetches in E state", .ucode = 0x4000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PREFETCH_I_STATE", .udesc = "L2 data prefetches in the I state (misses)", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PREFETCH_M_STATE", .udesc = "L2 data prefetches in M state", .ucode = 0x8000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PREFETCH_MESI", .udesc = "All L2 data prefetches", .ucode = 0xf000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PREFETCH_S_STATE", .udesc = "L2 data prefetches in the S state", .ucode = 0x2000, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t wsm_br_inst_exec[]={ { .uname = "ANY", .udesc = "Branch instructions executed", .ucode = 0x7f00, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "COND", .udesc = "Conditional branch instructions executed", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DIRECT", .udesc = "Unconditional branches executed", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DIRECT_NEAR_CALL", .udesc = "Unconditional call branches executed", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "INDIRECT_NEAR_CALL", .udesc = "Indirect call branches executed", .ucode = 0x2000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "INDIRECT_NON_CALL", .udesc = "Indirect non call branches executed", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "NEAR_CALLS", .udesc = "Call branches executed", .ucode = 0x3000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "NON_CALLS", .udesc = "All non call branches executed", .ucode = 0x700, .uflags= INTEL_X86_NCOMBO, }, { .uname = "RETURN_NEAR", .udesc = "Indirect return branches executed", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "TAKEN", .udesc = "Taken branches executed", .ucode = 0x4000, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t wsm_snoopq_requests_outstanding[]={ { .uname = "CODE", .udesc = "Outstanding snoop code requests", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "CODE_NOT_EMPTY", .udesc = "Cycles snoop code requests queue not empty", .uequiv = "CODE:c=1", .ucode = 0x400 | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, }, { .uname = "DATA", .udesc = "Outstanding snoop data requests", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DATA_NOT_EMPTY", .udesc = "Cycles snoop data requests queue not empty", .uequiv = "DATA:c=1", .ucode = 0x100 | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, }, { .uname = "INVALIDATE", .udesc = "Outstanding snoop invalidate requests", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "INVALIDATE_NOT_EMPTY", .udesc = "Cycles snoop invalidate requests queue not empty", .uequiv = "INVALIDATE:c=1", .ucode = 0x200 | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t wsm_mem_load_retired[]={ { .uname = "DTLB_MISS", .udesc = "Retired loads that miss the DTLB (Precise Event)", .ucode = 0x8000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "HIT_LFB", .udesc = "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)", .ucode = 0x4000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "L1D_HIT", .udesc = "Retired loads that hit the L1 data cache (Precise Event)", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "L2_HIT", .udesc = "Retired loads that hit the L2 cache (Precise Event)", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "L3_MISS", .udesc = "Retired loads that miss the LLC cache (Precise Event)", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "LLC_MISS", .udesc = "This is an alias for L3_MISS", .uequiv = "L3_MISS", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "L3_UNSHARED_HIT", .udesc = "Retired loads that hit valid versions in the LLC cache (Precise Event)", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "LLC_UNSHARED_HIT", .udesc = "This is an alias for L3_UNSHARED_HIT", .uequiv = "L3_UNSHARED_HIT", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "OTHER_CORE_L2_HIT_HITM", .udesc = "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, }; static const intel_x86_umask_t wsm_l1i[]={ { .uname = "CYCLES_STALLED", .udesc = "L1I instruction fetch stall cycles", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "HITS", .udesc = "L1I instruction fetch hits", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "MISSES", .udesc = "L1I instruction fetch misses", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "READS", .udesc = "L1I Instruction fetches", .ucode = 0x300, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t wsm_l2_write[]={ { .uname = "LOCK_E_STATE", .udesc = "L2 demand lock RFOs in E state", .ucode = 0x4000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "LOCK_HIT", .udesc = "All demand L2 lock RFOs that hit the cache", .ucode = 0xe000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "LOCK_I_STATE", .udesc = "L2 demand lock RFOs in I state (misses)", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "LOCK_M_STATE", .udesc = "L2 demand lock RFOs in M state", .ucode = 0x8000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "LOCK_MESI", .udesc = "All demand L2 lock RFOs", .ucode = 0xf000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "LOCK_S_STATE", .udesc = "L2 demand lock RFOs in S state", .ucode = 0x2000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "RFO_HIT", .udesc = "All L2 demand store RFOs that hit the cache", .ucode = 0xe00, .uflags= INTEL_X86_NCOMBO, }, { .uname = "RFO_I_STATE", .udesc = "L2 demand store RFOs in I state (misses)", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "RFO_M_STATE", .udesc = "L2 demand store RFOs in M state", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "RFO_MESI", .udesc = "All L2 demand store RFOs", .ucode = 0xf00, .uflags= INTEL_X86_NCOMBO, }, { .uname = "RFO_S_STATE", .udesc = "L2 demand store RFOs in S state", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t wsm_snoop_response[]={ { .uname = "HIT", .udesc = "Thread responded HIT to snoop", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "HITE", .udesc = "Thread responded HITE to snoop", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "HITM", .udesc = "Thread responded HITM to snoop", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t wsm_l1d[]={ { .uname = "M_EVICT", .udesc = "L1D cache lines replaced in M state ", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "M_REPL", .udesc = "L1D cache lines allocated in the M state", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "M_SNOOP_EVICT", .udesc = "L1D snoop eviction of cache lines in M state", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "REPL", .udesc = "L1 data cache lines allocated", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t wsm_resource_stalls[]={ { .uname = "ANY", .udesc = "Resource related stall cycles", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "FPCW", .udesc = "FPU control word write stall cycles", .ucode = 0x2000, }, { .uname = "LOAD", .udesc = "Load buffer stall cycles", .ucode = 0x200, }, { .uname = "MXCSR", .udesc = "MXCSR rename stall cycles", .ucode = 0x4000, }, { .uname = "OTHER", .udesc = "Other Resource related stall cycles", .ucode = 0x8000, }, { .uname = "ROB_FULL", .udesc = "ROB full stall cycles", .ucode = 0x1000, }, { .uname = "RS_FULL", .udesc = "Reservation Station full stall cycles", .ucode = 0x400, }, { .uname = "STORE", .udesc = "Store buffer stall cycles", .ucode = 0x800, }, }; static const intel_x86_umask_t wsm_rat_stalls[]={ { .uname = "ANY", .udesc = "All RAT stall cycles", .uequiv = "FLAGS:REGISTERS:ROB_READ_PORT:SCOREBOARD", .ucode = 0xf00, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "FLAGS", .udesc = "Flag stall cycles", .ucode = 0x100, }, { .uname = "REGISTERS", .udesc = "Partial register stall cycles", .ucode = 0x200, }, { .uname = "ROB_READ_PORT", .udesc = "ROB read port stalls cycles", .ucode = 0x400, }, { .uname = "SCOREBOARD", .udesc = "Scoreboard stall cycles", .ucode = 0x800, }, }; static const intel_x86_umask_t wsm_cpu_clk_unhalted[]={ { .uname = "THREAD_P", .udesc = "Cycles when thread is not halted (programmable counter)", .ucode = 0x0, .uflags= INTEL_X86_NCOMBO, }, { .uname = "REF_P", .udesc = "Reference base clock (133 Mhz) cycles when thread is not halted", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "TOTAL_CYCLES", .udesc = "Total number of elapsed cycles. Does not work when C-state enabled", .uequiv = "THREAD_P:c=2:i=1", .ucode = 0x0 | INTEL_X86_MOD_INV | (0x2 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t wsm_l1d_wb_l2[]={ { .uname = "E_STATE", .udesc = "L1 writebacks to L2 in E state", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "I_STATE", .udesc = "L1 writebacks to L2 in I state (misses)", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "M_STATE", .udesc = "L1 writebacks to L2 in M state", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "MESI", .udesc = "All L1 writebacks to L2", .ucode = 0xf00, .uflags= INTEL_X86_NCOMBO, }, { .uname = "S_STATE", .udesc = "L1 writebacks to L2 in S state", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t wsm_offcore_response_0[]={ { .uname = "DMND_DATA_RD", .udesc = "Request: counts the number of demand and DCU prefetch data reads of full and partial cachelines as well as demand data page table entry cacheline reads. Does not count L2 data read prefetches or instruction fetches", .ucode = 0x100, .grpid = 0, }, { .uname = "DMND_RFO", .udesc = "Request: counts the number of demand and DCU prefetch reads for ownership (RFO) requests generated by a write to data cacheline. Does not count L2 RFO", .ucode = 0x200, .grpid = 0, }, { .uname = "DMND_IFETCH", .udesc = "Request: counts the number of demand and DCU prefetch instruction cacheline reads. Does not count L2 code read prefetches", .ucode = 0x400, .grpid = 0, }, { .uname = "WB", .udesc = "Request: counts the number of writeback (modified to exclusive) transactions", .ucode = 0x800, .grpid = 0, }, { .uname = "PF_DATA_RD", .udesc = "Request: counts the number of data cacheline reads generated by L2 prefetchers", .ucode = 0x1000, .grpid = 0, }, { .uname = "PF_RFO", .udesc = "Request: counts the number of RFO requests generated by L2 prefetchers", .ucode = 0x2000, .grpid = 0, }, { .uname = "PF_IFETCH", .udesc = "Request: counts the number of code reads generated by L2 prefetchers", .ucode = 0x4000, .grpid = 0, }, { .uname = "OTHER", .udesc = "Request: counts one of the following transaction types, including L3 invalidate, I/O, full or partial writes, WC or non-temporal stores, CLFLUSH, Fences, lock, unlock, split lock", .ucode = 0x8000, .grpid = 0, }, { .uname = "ANY_IFETCH", .udesc = "Request: combination of PF_IFETCH | DMND_IFETCH", .uequiv = "PF_IFETCH:DMND_IFETCH", .ucode = 0x4400, .grpid = 0, }, { .uname = "ANY_REQUEST", .udesc = "Request: combination of all requests umasks", .uequiv = "DMND_DATA_RD:DMND_RFO:DMND_IFETCH:WB:PF_DATA_RD:PF_RFO:PF_IFETCH:OTHER", .ucode = 0xff00, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, .grpid = 0, }, { .uname = "ANY_DATA", .udesc = "Request: any data read/write request", .uequiv = "DMND_DATA_RD:PF_DATA_RD:DMND_RFO:PF_RFO", .ucode = 0x3300, .grpid = 0, }, { .uname = "ANY_DATA_RD", .udesc = "Request: any data read in request", .uequiv = "DMND_DATA_RD:PF_DATA_RD", .ucode = 0x1100, .grpid = 0, }, { .uname = "ANY_RFO", .udesc = "Request: combination of DMND_RFO | PF_RFO", .uequiv = "DMND_RFO:PF_RFO", .ucode = 0x2200, .grpid = 0, }, { .uname = "UNCORE_HIT", .udesc = "Response: counts L3 Hit: local or remote home requests that hit L3 cache in the uncore with no coherency actions required (snooping)", .ucode = 0x10000, .grpid = 1, }, { .uname = "OTHER_CORE_HIT_SNP", .udesc = "Response: counts L3 Hit: local or remote home requests that hit L3 cache in the uncore and was serviced by another core with a cross core snoop where no modified copies were found (clean)", .ucode = 0x20000, .grpid = 1, }, { .uname = "OTHER_CORE_HITM", .udesc = "Response: counts L3 Hit: local or remote home requests that hit L3 cache in the uncore and was serviced by another core with a cross core snoop where modified copies were found (HITM)", .ucode = 0x40000, .grpid = 1, }, { .uname = "REMOTE_CACHE_HITM", .udesc = "Response: counts L3 Hit: local or remote home requests that hit a remote L3 cacheline in modified (HITM) state", .ucode = 0x80000, .grpid = 1, }, { .uname = "REMOTE_CACHE_FWD", .udesc = "Response: counts L3 Miss: local homed requests that missed the L3 cache and was serviced by forwarded data following a cross package snoop where no modified copies found. (Remote home requests are not counted)", .ucode = 0x100000, .grpid = 1, .umodel = PFM_PMU_INTEL_WSM, }, { .uname = "LOCAL_DRAM_AND_REMOTE_CACHE_HIT", .udesc = "Response: counts L3 Miss: local home requests that missed the L3 cache and were serviced by local DRAM or a remote cache", .ucode = 0x100000, .grpid = 1, .umodel = PFM_PMU_INTEL_WSM_DP, }, { .uname = "REMOTE_DRAM", .udesc = "Response: counts L3 Miss: remote home requests that missed the L3 cache and were serviced by remote DRAM", .ucode = 0x200000, .grpid = 1, .umodel = PFM_PMU_INTEL_WSM_DP, }, { .uname = "LOCAL_DRAM", .udesc = "Response: counts L3 Miss: local home requests that missed the L3 cache and were serviced by local DRAM", .ucode = 0x200000, .grpid = 1, .umodel = PFM_PMU_INTEL_WSM, }, { .uname = "REMOTE_DRAM", .udesc = "Response: counts L3 Miss: remote home requests that missed the L3 cache and were serviced by remote DRAM", .ucode = 0x400000, .grpid = 1, .umodel = PFM_PMU_INTEL_WSM, }, { .uname = "OTHER_LLC_MISS", .udesc = "Response: counts L3 Miss: remote home requests that missed the L3 cache", .ucode = 0x400000, .grpid = 1, .umodel = PFM_PMU_INTEL_WSM_DP, }, { .uname = "NON_DRAM", .udesc = "Response: Non-DRAM requests that were serviced by IOH", .ucode = 0x800000, .grpid = 1, }, { .uname = "ANY_CACHE_DRAM", .udesc = "Response: requests serviced by any source but IOH", .uequiv = "UNCORE_HIT:OTHER_CORE_HIT_SNP:OTHER_CORE_HITM:REMOTE_CACHE_FWD:REMOTE_CACHE_HITM:REMOTE_DRAM:LOCAL_DRAM", .ucode = 0x7f0000, .grpid = 1, .umodel = PFM_PMU_INTEL_WSM, }, { .uname = "ANY_CACHE_DRAM", .udesc = "Response: requests serviced by any source but IOH", .uequiv = "UNCORE_HIT:OTHER_CORE_HIT_SNP:OTHER_CORE_HITM:REMOTE_CACHE_HITM:OTHER_LLC_MISS:REMOTE_DRAM:LOCAL_DRAM_AND_REMOTE_CACHE_HIT", .ucode = 0x7f0000, .grpid = 1, .umodel = PFM_PMU_INTEL_WSM_DP, }, { .uname = "ANY_DRAM", .udesc = "Response: requests serviced by local or remote DRAM", .uequiv = "REMOTE_DRAM:LOCAL_DRAM", .ucode = 0x600000, .umodel = PFM_PMU_INTEL_WSM, .grpid = 1, }, { .uname = "ANY_LLC_MISS", .udesc = "Response: requests that missed in L3", .uequiv = "REMOTE_CACHE_HITM:REMOTE_CACHE_FWD:REMOTE_DRAM:LOCAL_DRAM:NON_DRAM", .ucode = 0xf80000, .grpid = 1, .umodel = PFM_PMU_INTEL_WSM, }, { .uname = "ANY_LLC_MISS", .udesc = "Response: requests that missed in L3", .uequiv = "REMOTE_CACHE_HITM:REMOTE_DRAM:OTHER_LLC_MISS:LOCAL_DRAM_AND_REMOTE_CACHE_HIT:NON_DRAM", .ucode = 0xf80000, .grpid = 1, .umodel = PFM_PMU_INTEL_WSM_DP, }, { .uname = "LOCAL_CACHE_DRAM", .udesc = "Response: requests hit local core or uncore caches or local DRAM", .uequiv = "UNCORE_HIT:OTHER_CORE_HIT_SNP:OTHER_CORE_HITM:LOCAL_DRAM", .ucode = 0x270000, .umodel = PFM_PMU_INTEL_WSM, .grpid = 1, }, { .uname = "REMOTE_CACHE_DRAM", .udesc = "Response: requests that miss L3 and hit remote caches or DRAM", .uequiv = "REMOTE_CACHE_HITM:REMOTE_CACHE_FWD:REMOTE_DRAM", .ucode = 0x580000, .grpid = 1, .umodel = PFM_PMU_INTEL_WSM, }, { .uname = "LOCAL_CACHE", .udesc = "Response: any local (core and socket) caches", .uequiv = "UNCORE_HIT:OTHER_CORE_HIT_SNP:OTHER_CORE_HITM", .ucode = 0x70000, .grpid = 1, }, { .uname = "ANY_RESPONSE", .udesc = "Response: combination of all response umasks", .uequiv = "UNCORE_HIT:OTHER_CORE_HIT_SNP:OTHER_CORE_HITM:REMOTE_CACHE_HITM:REMOTE_CACHE_FWD:REMOTE_DRAM:LOCAL_DRAM:NON_DRAM", .ucode = 0xff0000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, .grpid = 1, .umodel = PFM_PMU_INTEL_WSM, }, { .uname = "ANY_RESPONSE", .udesc = "Response: combination of all response umasks", .uequiv = "UNCORE_HIT:OTHER_CORE_HIT_SNP:OTHER_CORE_HITM:REMOTE_CACHE_HITM:REMOTE_DRAM:OTHER_LLC_MISS:LOCAL_DRAM_AND_REMOTE_CACHE_HIT:NON_DRAM", .ucode = 0xff0000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, .grpid = 1, .umodel = PFM_PMU_INTEL_WSM_DP, }, }; static const intel_x86_entry_t intel_wsm_pe[]={ { .name = "UNHALTED_CORE_CYCLES", .desc = "Count core clock cycles whenever the clock signal on the specific core is running (not halted).", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x20000000full, .code = 0x3c, }, { .name = "INSTRUCTION_RETIRED", .desc = "Count the number of instructions at retirement.", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x10000000full, .code = 0xc0, }, { .name = "INSTRUCTIONS_RETIRED", .desc = "This is an alias for INSTRUCTION_RETIRED", .modmsk = INTEL_V3_ATTRS, .equiv = "INSTRUCTION_RETIRED", .cntmsk = 0x10000000full, .code = 0xc0, }, { .name = "UNHALTED_REFERENCE_CYCLES", .desc = "Unhalted reference cycles", .modmsk = INTEL_FIXED3_ATTRS, .cntmsk = 0x400000000ull, .code = 0x0300, /* pseudo encoding */ .flags = INTEL_X86_FIXED, }, { .name = "LLC_REFERENCES", .desc = "Count each request originating from the core to reference a cache line in the last level cache. The count may include speculation, but excludes cache line fills due to hardware prefetch (Alias for L3_LAT_CACHE:REFERENCE).", .modmsk = INTEL_V3_ATTRS, .equiv = "L3_LAT_CACHE:REFERENCE", .cntmsk = 0xf, .code = 0x4f2e, }, { .name = "LAST_LEVEL_CACHE_REFERENCES", .desc = "This is an alias for L3_LAT_CACHE:REFERENCE", .modmsk = INTEL_V3_ATTRS, .equiv = "L3_LAT_CACHE:REFERENCE", .cntmsk = 0xf, .code = 0x4f2e, }, { .name = "LLC_MISSES", .desc = "Count each cache miss condition for references to the last level cache. The event count may include speculation, but excludes cache line fills due to hardware prefetch (Alias for L3_LAT_CACHE:MISS)", .modmsk = INTEL_V3_ATTRS, .equiv = "L3_LAT_CACHE:MISS", .cntmsk = 0xf, .code = 0x412e, }, { .name = "LAST_LEVEL_CACHE_MISSES", .desc = "This is an alias for L3_LAT_CACHE:MISS", .modmsk = INTEL_V3_ATTRS, .equiv = "L3_LAT_CACHE:MISS", .cntmsk = 0xf, .code = 0x412e, }, { .name = "BRANCH_INSTRUCTIONS_RETIRED", .desc = "Count branch instructions at retirement. Specifically, this event counts the retirement of the last micro-op of a branch instruction.", .modmsk = INTEL_V3_ATTRS, .equiv = "BR_INST_RETIRED:ALL_BRANCHES", .cntmsk = 0xf, .code = 0x4c4, }, { .name = "UOPS_DECODED", .desc = "Micro-ops decoded", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0xd1, .numasks = LIBPFM_ARRAY_SIZE(wsm_uops_decoded), .ngrp = 1, .umasks = wsm_uops_decoded, }, { .name = "L1D_CACHE_LOCK_FB_HIT", .desc = "L1D cacheable load lock speculated or retired accepted into the fill buffer", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x152, }, { .name = "BPU_CLEARS", .desc = "Branch Prediction Unit clears", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0xe8, .numasks = LIBPFM_ARRAY_SIZE(wsm_bpu_clears), .ngrp = 1, .umasks = wsm_bpu_clears, }, { .name = "UOPS_RETIRED", .desc = "Cycles Uops are being retired (Precise Event)", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0xc2, .flags= INTEL_X86_PEBS, .numasks = LIBPFM_ARRAY_SIZE(wsm_uops_retired), .ngrp = 1, .umasks = wsm_uops_retired, }, { .name = "BR_MISP_RETIRED", .desc = "Mispredicted retired branches (Precise Event)", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0xc5, .flags= INTEL_X86_PEBS, .numasks = LIBPFM_ARRAY_SIZE(wsm_br_misp_retired), .ngrp = 1, .umasks = wsm_br_misp_retired, }, { .name = "EPT", .desc = "Extended Page Table", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x4f, .numasks = LIBPFM_ARRAY_SIZE(wsm_ept), .ngrp = 1, .umasks = wsm_ept, }, { .name = "UOPS_EXECUTED", .desc = "Micro-ops executed", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0xb1, .numasks = LIBPFM_ARRAY_SIZE(wsm_uops_executed), .ngrp = 1, .umasks = wsm_uops_executed, }, { .name = "IO_TRANSACTIONS", .desc = "I/O transactions", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x16c, }, { .name = "ES_REG_RENAMES", .desc = "ES segment renames", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x1d5, }, { .name = "INST_RETIRED", .desc = "Instructions retired (Precise Event)", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0xc0, .flags= INTEL_X86_PEBS, .numasks = LIBPFM_ARRAY_SIZE(wsm_inst_retired), .ngrp = 1, .umasks = wsm_inst_retired, }, { .name = "ILD_STALL", .desc = "Instruction Length Decoder stalls", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x87, .numasks = LIBPFM_ARRAY_SIZE(wsm_ild_stall), .ngrp = 1, .umasks = wsm_ild_stall, }, { .name = "DTLB_LOAD_MISSES", .desc = "DTLB load misses", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x8, .numasks = LIBPFM_ARRAY_SIZE(wsm_dtlb_load_misses), .ngrp = 1, .umasks = wsm_dtlb_load_misses, }, { .name = "L2_LINES_IN", .desc = "L2 lines allocated", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0xf1, .numasks = LIBPFM_ARRAY_SIZE(wsm_l2_lines_in), .ngrp = 1, .umasks = wsm_l2_lines_in, }, { .name = "SSEX_UOPS_RETIRED", .desc = "SIMD micro-ops retired (Precise Event)", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0xc7, .flags= INTEL_X86_PEBS, .numasks = LIBPFM_ARRAY_SIZE(wsm_ssex_uops_retired), .ngrp = 1, .umasks = wsm_ssex_uops_retired, }, { .name = "STORE_BLOCKS", .desc = "Load delayed by block code", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x6, .numasks = LIBPFM_ARRAY_SIZE(wsm_store_blocks), .ngrp = 1, .umasks = wsm_store_blocks, }, { .name = "FP_MMX_TRANS", .desc = "Floating Point to and from MMX transitions", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0xcc, .numasks = LIBPFM_ARRAY_SIZE(wsm_fp_mmx_trans), .ngrp = 1, .umasks = wsm_fp_mmx_trans, }, { .name = "CACHE_LOCK_CYCLES", .desc = "Cache locked", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x63, .numasks = LIBPFM_ARRAY_SIZE(wsm_cache_lock_cycles), .ngrp = 1, .umasks = wsm_cache_lock_cycles, }, { .name = "OFFCORE_REQUESTS_SQ_FULL", .desc = "Offcore requests blocked due to Super Queue full", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x1b2, }, { .name = "LONGEST_LAT_CACHE", .desc = "Last level cache accesses", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x2e, .numasks = LIBPFM_ARRAY_SIZE(wsm_l3_lat_cache), .ngrp = 1, .umasks = wsm_l3_lat_cache, }, { .name = "L3_LAT_CACHE", .desc = "Last level cache accesses", .equiv = "LONGEST_LAT_CACHE", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x2e, .numasks = LIBPFM_ARRAY_SIZE(wsm_l3_lat_cache), .ngrp = 1, .umasks = wsm_l3_lat_cache, }, { .name = "SIMD_INT_64", .desc = "SIMD 64-bit integer operations", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0xfd, .numasks = LIBPFM_ARRAY_SIZE(wsm_simd_int_64), .ngrp = 1, .umasks = wsm_simd_int_64, }, { .name = "BR_INST_DECODED", .desc = "Branch instructions decoded", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x1e0, }, { .name = "BR_MISP_EXEC", .desc = "Mispredicted branches executed", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x89, .numasks = LIBPFM_ARRAY_SIZE(wsm_br_misp_exec), .ngrp = 1, .umasks = wsm_br_misp_exec, }, { .name = "SQ_FULL_STALL_CYCLES", .desc = "Super Queue full stall cycles", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x1f6, }, { .name = "BACLEAR", .desc = "Branch address calculator clears", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0xe6, .numasks = LIBPFM_ARRAY_SIZE(wsm_baclear), .ngrp = 1, .umasks = wsm_baclear, }, { .name = "DTLB_MISSES", .desc = "Data TLB misses", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x49, .numasks = LIBPFM_ARRAY_SIZE(wsm_dtlb_misses), .ngrp = 1, .umasks = wsm_dtlb_misses, }, { .name = "MEM_INST_RETIRED", .desc = "Memory instructions retired (Precise Event)", .modmsk = INTEL_V3_ATTRS | _INTEL_X86_ATTR_LDLAT, .cntmsk = 0xf, .code = 0xb, .flags= INTEL_X86_PEBS, .numasks = LIBPFM_ARRAY_SIZE(wsm_mem_inst_retired), .ngrp = 1, .umasks = wsm_mem_inst_retired, }, { .name = "UOPS_ISSUED", .desc = "Uops issued", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0xe, .numasks = LIBPFM_ARRAY_SIZE(wsm_uops_issued), .ngrp = 1, .umasks = wsm_uops_issued, }, { .name = "L2_RQSTS", .desc = "L2 requests", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x24, .numasks = LIBPFM_ARRAY_SIZE(wsm_l2_rqsts), .ngrp = 1, .umasks = wsm_l2_rqsts, }, { .name = "TWO_UOP_INSTS_DECODED", .desc = "Two Uop instructions decoded", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x119, }, { .name = "LOAD_DISPATCH", .desc = "Loads dispatched", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x13, .numasks = LIBPFM_ARRAY_SIZE(wsm_load_dispatch), .ngrp = 1, .umasks = wsm_load_dispatch, }, { .name = "BACLEAR_FORCE_IQ", .desc = "BACLEAR forced by Instruction queue", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x1a7, }, { .name = "SNOOPQ_REQUESTS", .desc = "Snoopq requests", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0xb4, .numasks = LIBPFM_ARRAY_SIZE(wsm_snoopq_requests), .ngrp = 1, .umasks = wsm_snoopq_requests, }, { .name = "OFFCORE_REQUESTS", .desc = "Offcore requests", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0xb0, .numasks = LIBPFM_ARRAY_SIZE(wsm_offcore_requests), .ngrp = 1, .umasks = wsm_offcore_requests, }, { .name = "LOAD_BLOCK", .desc = "Loads blocked", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x3, .numasks = LIBPFM_ARRAY_SIZE(wsm_load_block), .ngrp = 1, .umasks = wsm_load_block, }, { .name = "MISALIGN_MEMORY", .desc = "Misaligned accesses", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x5, .numasks = LIBPFM_ARRAY_SIZE(wsm_misalign_memory), .ngrp = 1, .umasks = wsm_misalign_memory, }, { .name = "INST_QUEUE_WRITE_CYCLES", .desc = "Cycles instructions are written to the instruction queue", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x11e, }, { .name = "LSD_OVERFLOW", .desc = "Number of loops that cannot stream from the instruction queue.", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x120, }, { .name = "MACHINE_CLEARS", .desc = "Machine clear asserted", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0xc3, .numasks = LIBPFM_ARRAY_SIZE(wsm_machine_clears), .ngrp = 1, .umasks = wsm_machine_clears, }, { .name = "FP_COMP_OPS_EXE", .desc = "SSE/MMX micro-ops", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x10, .numasks = LIBPFM_ARRAY_SIZE(wsm_fp_comp_ops_exe), .ngrp = 1, .umasks = wsm_fp_comp_ops_exe, }, { .name = "ITLB_FLUSH", .desc = "ITLB flushes", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x1ae, }, { .name = "BR_INST_RETIRED", .desc = "Retired branch instructions (Precise Event)", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0xc4, .flags= INTEL_X86_PEBS, .numasks = LIBPFM_ARRAY_SIZE(wsm_br_inst_retired), .ngrp = 1, .umasks = wsm_br_inst_retired, }, { .name = "L1D_CACHE_PREFETCH_LOCK_FB_HIT", .desc = "L1D prefetch load lock accepted in fill buffer", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x152, }, { .name = "LARGE_ITLB", .desc = "Large ITLB accesses", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x82, .numasks = LIBPFM_ARRAY_SIZE(wsm_large_itlb), .ngrp = 1, .umasks = wsm_large_itlb, }, { .name = "LSD", .desc = "Loop stream detector", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0xa8, .numasks = LIBPFM_ARRAY_SIZE(wsm_lsd), .ngrp = 1, .umasks = wsm_lsd, }, { .name = "L2_LINES_OUT", .desc = "L2 lines evicted", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0xf2, .numasks = LIBPFM_ARRAY_SIZE(wsm_l2_lines_out), .ngrp = 1, .umasks = wsm_l2_lines_out, }, { .name = "ITLB_MISSES", .desc = "ITLB miss", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x85, .numasks = LIBPFM_ARRAY_SIZE(wsm_itlb_misses), .ngrp = 1, .umasks = wsm_itlb_misses, }, { .name = "L1D_PREFETCH", .desc = "L1D hardware prefetch", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x4e, .numasks = LIBPFM_ARRAY_SIZE(wsm_l1d_prefetch), .ngrp = 1, .umasks = wsm_l1d_prefetch, }, { .name = "SQ_MISC", .desc = "Super Queue miscellaneous", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0xf4, .numasks = LIBPFM_ARRAY_SIZE(wsm_sq_misc), .ngrp = 1, .umasks = wsm_sq_misc, }, { .name = "SEG_RENAME_STALLS", .desc = "Segment rename stall cycles", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x1d4, }, { .name = "FP_ASSIST", .desc = "X87 Floating point assists (Precise Event)", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0xf7, .flags= INTEL_X86_PEBS, .numasks = LIBPFM_ARRAY_SIZE(wsm_fp_assist), .ngrp = 1, .umasks = wsm_fp_assist, }, { .name = "SIMD_INT_128", .desc = "128 bit SIMD operations", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x12, .numasks = LIBPFM_ARRAY_SIZE(wsm_simd_int_128), .ngrp = 1, .umasks = wsm_simd_int_128, }, { .name = "OFFCORE_REQUESTS_OUTSTANDING", .desc = "Outstanding offcore requests", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x1, .code = 0x60, .numasks = LIBPFM_ARRAY_SIZE(wsm_offcore_requests_outstanding), .ngrp = 1, .umasks = wsm_offcore_requests_outstanding, }, { .name = "MEM_STORE_RETIRED", .desc = "Retired stores", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0xc, .flags= INTEL_X86_PEBS, .numasks = LIBPFM_ARRAY_SIZE(wsm_mem_store_retired), .ngrp = 1, .umasks = wsm_mem_store_retired, }, { .name = "INST_DECODED", .desc = "Instructions decoded", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x18, .numasks = LIBPFM_ARRAY_SIZE(wsm_inst_decoded), .ngrp = 1, .umasks = wsm_inst_decoded, }, { .name = "MACRO_INSTS_FUSIONS_DECODED", .desc = "Count the number of instructions decoded that are macros-fused but not necessarily executed or retired", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x1a6, }, { .name = "MACRO_INSTS", .desc = "Macro-instructions", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0xd0, .numasks = LIBPFM_ARRAY_SIZE(wsm_macro_insts), .ngrp = 1, .umasks = wsm_macro_insts, }, { .name = "PARTIAL_ADDRESS_ALIAS", .desc = "False dependencies due to partial address aliasing", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x107, }, { .name = "ARITH", .desc = "Counts arithmetic multiply and divide operations", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x14, .numasks = LIBPFM_ARRAY_SIZE(wsm_arith), .ngrp = 1, .umasks = wsm_arith, }, { .name = "L2_TRANSACTIONS", .desc = "L2 transactions", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0xf0, .numasks = LIBPFM_ARRAY_SIZE(wsm_l2_transactions), .ngrp = 1, .umasks = wsm_l2_transactions, }, { .name = "INST_QUEUE_WRITES", .desc = "Instructions written to instruction queue.", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x117, }, { .name = "SB_DRAIN", .desc = "Store buffer", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x4, .numasks = LIBPFM_ARRAY_SIZE(wsm_sb_drain), .ngrp = 1, .umasks = wsm_sb_drain, }, { .name = "LOAD_HIT_PRE", .desc = "Load operations conflicting with software prefetches", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x14c, }, { .name = "MEM_UNCORE_RETIRED", .desc = "Load instructions retired (Precise Event)", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0xf, .flags= INTEL_X86_PEBS, .numasks = LIBPFM_ARRAY_SIZE(wsm_mem_uncore_retired), .ngrp = 1, .umasks = wsm_mem_uncore_retired, }, { .name = "L2_DATA_RQSTS", .desc = "All L2 data requests", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x26, .numasks = LIBPFM_ARRAY_SIZE(wsm_l2_data_rqsts), .ngrp = 1, .umasks = wsm_l2_data_rqsts, }, { .name = "BR_INST_EXEC", .desc = "Branch instructions executed", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x88, .numasks = LIBPFM_ARRAY_SIZE(wsm_br_inst_exec), .ngrp = 1, .umasks = wsm_br_inst_exec, }, { .name = "ITLB_MISS_RETIRED", .desc = "Retired instructions that missed the ITLB (Precise Event)", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x20c8, .flags= INTEL_X86_PEBS, }, { .name = "BPU_MISSED_CALL_RET", .desc = "Branch prediction unit missed call or return", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x1e5, }, { .name = "SNOOPQ_REQUESTS_OUTSTANDING", .desc = "Outstanding snoop requests", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x1, .code = 0xb3, .numasks = LIBPFM_ARRAY_SIZE(wsm_snoopq_requests_outstanding), .ngrp = 1, .umasks = wsm_snoopq_requests_outstanding, }, { .name = "MEM_LOAD_RETIRED", .desc = "Memory loads retired (Precise Event)", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0xcb, .flags= INTEL_X86_PEBS, .numasks = LIBPFM_ARRAY_SIZE(wsm_mem_load_retired), .ngrp = 1, .umasks = wsm_mem_load_retired, }, { .name = "L1I", .desc = "L1I instruction fetch", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x80, .numasks = LIBPFM_ARRAY_SIZE(wsm_l1i), .ngrp = 1, .umasks = wsm_l1i, }, { .name = "L2_WRITE", .desc = "L2 demand lock/store RFO", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x27, .numasks = LIBPFM_ARRAY_SIZE(wsm_l2_write), .ngrp = 1, .umasks = wsm_l2_write, }, { .name = "SNOOP_RESPONSE", .desc = "Snoop", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0xb8, .numasks = LIBPFM_ARRAY_SIZE(wsm_snoop_response), .ngrp = 1, .umasks = wsm_snoop_response, }, { .name = "L1D", .desc = "L1D cache", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x51, .numasks = LIBPFM_ARRAY_SIZE(wsm_l1d), .ngrp = 1, .umasks = wsm_l1d, }, { .name = "RESOURCE_STALLS", .desc = "Resource related stall cycles", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0xa2, .numasks = LIBPFM_ARRAY_SIZE(wsm_resource_stalls), .ngrp = 1, .umasks = wsm_resource_stalls, }, { .name = "RAT_STALLS", .desc = "All RAT stall cycles", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0xd2, .numasks = LIBPFM_ARRAY_SIZE(wsm_rat_stalls), .ngrp = 1, .umasks = wsm_rat_stalls, }, { .name = "CPU_CLK_UNHALTED", .desc = "Cycles when processor is not in halted state", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x3c, .numasks = LIBPFM_ARRAY_SIZE(wsm_cpu_clk_unhalted), .ngrp = 1, .umasks = wsm_cpu_clk_unhalted, }, { .name = "L1D_WB_L2", .desc = "L1D writebacks to L2", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x28, .numasks = LIBPFM_ARRAY_SIZE(wsm_l1d_wb_l2), .ngrp = 1, .umasks = wsm_l1d_wb_l2, }, { .name = "MISPREDICTED_BRANCH_RETIRED", .desc = "Count mispredicted branch instructions at retirement. Specifically, this event counts at retirement of the last micro-op of a branch instruction in the architectural path of the execution and experienced misprediction in the branch prediction hardware", .modmsk = INTEL_V3_ATTRS, .equiv = "BR_MISP_RETIRED:ALL_BRANCHES", .cntmsk = 0xf, .code = 0xc5, }, { .name = "THREAD_ACTIVE", .desc = "Cycles thread is active", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x1ec, }, { .name = "UOP_UNFUSION", .desc = "Counts unfusion events due to floating point exception to a fused uop", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x1db, }, { .name = "OFFCORE_RESPONSE_0", .desc = "Offcore response 0 (must provide at least one request and one response umasks)", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x1b7, .flags= INTEL_X86_NHM_OFFCORE, .numasks = LIBPFM_ARRAY_SIZE(wsm_offcore_response_0), .ngrp = 2, .umasks = wsm_offcore_response_0, }, { .name = "OFFCORE_RESPONSE_1", .desc = "Offcore response 1 (must provide at least one request and one response umasks)", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x1bb, .flags= INTEL_X86_NHM_OFFCORE, .numasks = LIBPFM_ARRAY_SIZE(wsm_offcore_response_0), .ngrp = 2, .umasks = wsm_offcore_response_0, /* identical to actual umasks list for this event */ }, }; libpfm-4.9.0/lib/events/intel_snbep_unc_imc_events.h0000664000175000017500000002370313223402656022431 0ustar eranianeranian/* * Copyright (c) 2012 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * PMU: snbep_unc_imc (Intel SandyBridge-EP IMC uncore PMU) */ static const intel_x86_umask_t snbep_unc_m_cas_count[]={ { .uname = "ALL", .udesc = "Counts total number of DRAM CAS commands issued on this channel", .ucode = 0xf00, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "RD", .udesc = "Counts all DRAM reads on this channel, incl. underfills", .ucode = 0x300, .uflags = INTEL_X86_NCOMBO, }, { .uname = "RD_REG", .udesc = "Counts number of DRAM read CAS commands issued on this channel, incl. regular read CAS and those with implicit precharge", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "RD_UNDERFILL", .udesc = "Counts number of underfill reads issued by the memory controller", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "WR", .udesc = "Counts number of DRAM write CAS commands on this channel", .ucode = 0xc00, .uflags = INTEL_X86_NCOMBO, }, { .uname = "WR_RMM", .udesc = "Counts Number of opportunistic DRAM write CAS commands issued on this channel", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "WR_WMM", .udesc = "Counts number of DRAM write CAS commands issued on this channel while in Write-Major mode", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t snbep_unc_m_dram_refresh[]={ { .uname = "HIGH", .udesc = "TBD", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "PANIC", .udesc = "TBD", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t snbep_unc_m_major_modes[]={ { .uname = "ISOCH", .udesc = "Counts cycles in ISOCH Major mode", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "PARTIAL", .udesc = "Counts cycles in Partial Major mode", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "READ", .udesc = "Counts cycles in Read Major mode", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "WRITE", .udesc = "Counts cycles in Write Major mode", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t snbep_unc_m_power_cke_cycles[]={ { .uname = "RANK0", .udesc = "Count cycles for rank 0", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "RANK1", .udesc = "Count cycles for rank 1", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "RANK2", .udesc = "Count cycles for rank 2", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "RANK3", .udesc = "Count cycles for rank 3", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "RANK4", .udesc = "Count cycles for rank 4", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "RANK5", .udesc = "Count cycles for rank 5", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "RANK6", .udesc = "Count cycles for rank 6", .ucode = 0x4000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "RANK7", .udesc = "Count cycles for rank 7", .ucode = 0x8000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t snbep_unc_m_preemption[]={ { .uname = "RD_PREEMPT_RD", .udesc = "Counts read over read preemptions", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "RD_PREEMPT_WR", .udesc = "Counts read over write preemptions", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t snbep_unc_m_pre_count[]={ { .uname = "PAGE_CLOSE", .udesc = "Counts number of DRAM precharge commands sent on this channel as a result of the page close counter expiring", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "PAGE_MISS", .udesc = "Counts number of DRAM precharge commands sent on this channel as a result of page misses", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_entry_t intel_snbep_unc_m_pe[]={ { .name = "UNC_M_CLOCKTICKS", .desc = "IMC Uncore clockticks", .modmsk = 0x0, .cntmsk = 0x100000000ull, .code = 0xff, /* perf pseudo encoding for fixed counter */ .flags = INTEL_X86_FIXED, }, { .name = "UNC_M_ACT_COUNT", .desc = "DRAM Activate Count", .code = 0x1, .cntmsk = 0xf, .modmsk = SNBEP_UNC_IMC_ATTRS, }, { .name = "UNC_M_CAS_COUNT", .desc = "DRAM RD_CAS and WR_CAS Commands.", .code = 0x4, .cntmsk = 0xf, .ngrp = 1, .modmsk = SNBEP_UNC_IMC_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_m_cas_count), .umasks = snbep_unc_m_cas_count }, { .name = "UNC_M_DRAM_PRE_ALL", .desc = "DRAM Precharge All Commands", .code = 0x6, .cntmsk = 0xf, .modmsk = SNBEP_UNC_IMC_ATTRS, }, { .name = "UNC_M_DRAM_REFRESH", .desc = "Number of DRAM Refreshes Issued", .code = 0x5, .cntmsk = 0xf, .ngrp = 1, .modmsk = SNBEP_UNC_IMC_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_m_dram_refresh), .umasks = snbep_unc_m_dram_refresh }, { .name = "UNC_M_ECC_CORRECTABLE_ERRORS", .desc = "ECC Correctable Errors", .code = 0x9, .cntmsk = 0xf, .modmsk = SNBEP_UNC_IMC_ATTRS, }, { .name = "UNC_M_MAJOR_MODES", .desc = "Cycles in a Major Mode", .code = 0x7, .cntmsk = 0xf, .ngrp = 1, .modmsk = SNBEP_UNC_IMC_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_m_major_modes), .umasks = snbep_unc_m_major_modes }, { .name = "UNC_M_POWER_CHANNEL_DLLOFF", .desc = "Channel DLLOFF Cycles", .code = 0x84, .cntmsk = 0xf, .modmsk = SNBEP_UNC_IMC_ATTRS, }, { .name = "UNC_M_POWER_CHANNEL_PPD", .desc = "Channel PPD Cycles", .code = 0x85, .cntmsk = 0xf, .modmsk = SNBEP_UNC_IMC_ATTRS, }, { .name = "UNC_M_POWER_CKE_CYCLES", .desc = "CKE_ON_CYCLES by Rank", .code = 0x83, .cntmsk = 0xf, .ngrp = 1, .modmsk = SNBEP_UNC_IMC_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_m_power_cke_cycles), .umasks = snbep_unc_m_power_cke_cycles }, { .name = "UNC_M_POWER_CRITICAL_THROTTLE_CYCLES", .desc = "Critical Throttle Cycles", .code = 0x86, .cntmsk = 0xf, .modmsk = SNBEP_UNC_IMC_ATTRS, }, { .name = "UNC_M_POWER_SELF_REFRESH", .desc = "Clock-Enabled Self-Refresh", .code = 0x43, .cntmsk = 0xf, .modmsk = SNBEP_UNC_IMC_ATTRS, }, { .name = "UNC_M_POWER_THROTTLE_CYCLES", .desc = "Throttle Cycles for Rank 0", .code = 0x41, .cntmsk = 0xf, .ngrp = 1, .modmsk = SNBEP_UNC_IMC_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_m_power_cke_cycles), .umasks = snbep_unc_m_power_cke_cycles /* identical to snbep_unc_m_power_cke_cycles */ }, { .name = "UNC_M_PREEMPTION", .desc = "Read Preemption Count", .code = 0x8, .cntmsk = 0xf, .ngrp = 1, .modmsk = SNBEP_UNC_IMC_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_m_preemption), .umasks = snbep_unc_m_preemption }, { .name = "UNC_M_PRE_COUNT", .desc = "DRAM Precharge commands.", .code = 0x2, .cntmsk = 0xf, .ngrp = 1, .modmsk = SNBEP_UNC_IMC_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_m_pre_count), .umasks = snbep_unc_m_pre_count }, { .name = "UNC_M_RPQ_CYCLES_FULL", .desc = "Read Pending Queue Full Cycles", .code = 0x12, .cntmsk = 0xf, .modmsk = SNBEP_UNC_IMC_ATTRS, }, { .name = "UNC_M_RPQ_CYCLES_NE", .desc = "Read Pending Queue Not Empty", .code = 0x11, .cntmsk = 0xf, .modmsk = SNBEP_UNC_IMC_ATTRS, }, { .name = "UNC_M_RPQ_INSERTS", .desc = "Read Pending Queue Allocations", .code = 0x10, .cntmsk = 0xf, .modmsk = SNBEP_UNC_IMC_ATTRS, }, { .name = "UNC_M_RPQ_OCCUPANCY", .desc = "Read Pending Queue Occupancy", .code = 0x80, .cntmsk = 0xf, .modmsk = SNBEP_UNC_IMC_ATTRS, }, { .name = "UNC_M_WPQ_CYCLES_FULL", .desc = "Write Pending Queue Full Cycles", .code = 0x22, .cntmsk = 0xf, .modmsk = SNBEP_UNC_IMC_ATTRS, }, { .name = "UNC_M_WPQ_CYCLES_NE", .desc = "Write Pending Queue Not Empty", .code = 0x21, .cntmsk = 0xf, .modmsk = SNBEP_UNC_IMC_ATTRS, }, { .name = "UNC_M_WPQ_INSERTS", .desc = "Write Pending Queue Allocations", .code = 0x20, .cntmsk = 0xf, .modmsk = SNBEP_UNC_IMC_ATTRS, }, { .name = "UNC_M_WPQ_OCCUPANCY", .desc = "Write Pending Queue Occupancy", .code = 0x81, .cntmsk = 0xf, .modmsk = SNBEP_UNC_IMC_ATTRS, }, { .name = "UNC_M_WPQ_READ_HIT", .desc = "Write Pending Queue CAM Match", .code = 0x23, .cntmsk = 0xf, .modmsk = SNBEP_UNC_IMC_ATTRS, }, { .name = "UNC_M_WPQ_WRITE_HIT", .desc = "Write Pending Queue CAM Match", .code = 0x24, .cntmsk = 0xf, .modmsk = SNBEP_UNC_IMC_ATTRS, }, }; libpfm-4.9.0/lib/events/arm_cortex_a7_events.h0000664000175000017500000001376013223402656021166 0ustar eranianeranian/* * Copyright (c) 2014 by Vince Weaver * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * Cortex A7 MPCore * based on Table 11-5 from the "Cortex-A7 MPCore Technical Reference Manual" */ static const arm_entry_t arm_cortex_a7_pe[]={ {.name = "SW_INCR", .modmsk = ARMV7_A7_ATTRS, .code = 0x00, .desc = "Incremented on writes to the Software Increment Register" }, {.name = "L1I_CACHE_REFILL", .modmsk = ARMV7_A7_ATTRS, .code = 0x01, .desc = "Level 1 instruction cache refill" }, {.name = "L1I_TLB_REFILL", .modmsk = ARMV7_A7_ATTRS, .code = 0x02, .desc = "Level 1 instruction TLB refill" }, {.name = "L1D_CACHE_REFILL", .modmsk = ARMV7_A7_ATTRS, .code = 0x03, .desc = "Level 1 data cache refill" }, {.name = "L1D_CACHE_ACCESS", .modmsk = ARMV7_A7_ATTRS, .code = 0x04, .desc = "Level 1 data cache access" }, {.name = "L1D_TLB_REFILL", .modmsk = ARMV7_A7_ATTRS, .code = 0x05, .desc = "Level 1 data TLB refill" }, {.name = "DATA_READS", .modmsk = ARMV7_A7_ATTRS, .code = 0x06, .desc = "Data reads architecturally executed" }, {.name = "DATA_WRITES", .modmsk = ARMV7_A7_ATTRS, .code = 0x07, .desc = "Data writes architecturally executed" }, {.name = "INST_RETIRED", .modmsk = ARMV7_A7_ATTRS, .code = 0x08, .desc = "Instruction architecturally executed" }, {.name = "EXCEPTION_TAKEN", .modmsk = ARMV7_A7_ATTRS, .code = 0x09, .desc = "Exception taken" }, {.name = "EXCEPTION_RETURN", .modmsk = ARMV7_A7_ATTRS, .code = 0x0a, .desc = "Instruction architecturally executed" }, {.name = "CID_WRITE_RETIRED", .modmsk = ARMV7_A7_ATTRS, .code = 0x0b, .desc = "Change to ContextID retired" }, {.name = "SW_CHANGE_PC", .modmsk = ARMV7_A7_ATTRS, .code = 0x0c, .desc = "Software change of PC" }, {.name = "IMMEDIATE_BRANCHES", .modmsk = ARMV7_A7_ATTRS, .code = 0x0d, .desc = "Immediate branch architecturally executed" }, {.name = "PROCEDURE_RETURNS", .modmsk = ARMV7_A7_ATTRS, .code = 0x0e, .desc = "Procedure returns architecturally executed" }, {.name = "UNALIGNED_LOAD_STORE", .modmsk = ARMV7_A7_ATTRS, .code = 0x0f, .desc = "Unaligned load-store" }, {.name = "BRANCH_MISPRED", .modmsk = ARMV7_A7_ATTRS, .code = 0x10, .desc = "Branches mispredicted/not predicted" }, {.name = "CPU_CYCLES", .modmsk = ARMV7_A7_ATTRS, .code = 0x11, .desc = "Cycles" }, {.name = "BRANCH_PRED", .modmsk = ARMV7_A7_ATTRS, .code = 0x12, .desc = "Predictable branch speculatively executed" }, {.name = "DATA_MEM_ACCESS", .modmsk = ARMV7_A7_ATTRS, .code = 0x13, .desc = "Data memory access" }, {.name = "L1I_CACHE_ACCESS", .modmsk = ARMV7_A7_ATTRS, .code = 0x14, .desc = "Level 1 instruction cache access" }, {.name = "L1D_CACHE_EVICTION", .modmsk = ARMV7_A7_ATTRS, .code = 0x15, .desc = "Level 1 data cache eviction" }, {.name = "L2D_CACHE_ACCESS", .modmsk = ARMV7_A7_ATTRS, .code = 0x16, .desc = "Level 2 data cache access" }, {.name = "L2D_CACHE_REFILL", .modmsk = ARMV7_A7_ATTRS, .code = 0x17, .desc = "Level 2 data cache refill" }, {.name = "L2D_CACHE_WB", .modmsk = ARMV7_A7_ATTRS, .code = 0x18, .desc = "Level 2 data cache WriteBack" }, {.name = "BUS_ACCESS", .modmsk = ARMV7_A7_ATTRS, .code = 0x19, .desc = "Bus accesses" }, {.name = "BUS_CYCLES", .modmsk = ARMV7_A7_ATTRS, .code = 0x1d, .desc = "Bus cycle" }, {.name = "BUS_READ_ACCESS", .modmsk = ARMV7_A7_ATTRS, .code = 0x60, .desc = "Bus read access" }, {.name = "BUS_WRITE_ACCESS", .modmsk = ARMV7_A7_ATTRS, .code = 0x61, .desc = "Bus write access" }, {.name = "IRQ_EXCEPTION_TAKEN", .modmsk = ARMV7_A7_ATTRS, .code = 0x86, .desc = "IRQ Exception Taken" }, {.name = "FIQ_EXCEPTION_TAKEN", .modmsk = ARMV7_A7_ATTRS, .code = 0x87, .desc = "FIQ Exception Taken" }, {.name = "EXTERNAL_MEMORY_REQUEST", .modmsk = ARMV7_A7_ATTRS, .code = 0xc0, .desc = "External memory request" }, {.name = "NONCACHE_EXTERNAL_MEMORY_REQUEST", .modmsk = ARMV7_A7_ATTRS, .code = 0xc1, .desc = "Non-cacheable xternal memory request" }, {.name = "PREFETCH_LINEFILL", .modmsk = ARMV7_A7_ATTRS, .code = 0xc2, .desc = "Linefill due to prefetch" }, {.name = "PREFETCH_LINEFILL_DROPPED", .modmsk = ARMV7_A7_ATTRS, .code = 0xc3, .desc = "Prefetch linefill dropped" }, {.name = "ENTERING_READ_ALLOC", .modmsk = ARMV7_A7_ATTRS, .code = 0xc4, .desc = "Entering read allocate mode" }, {.name = "READ_ALLOC", .modmsk = ARMV7_A7_ATTRS, .code = 0xc5, .desc = "Read allocate mode" }, /* 0xc6 is Reserved */ {.name = "ETM_EXT_OUT_0", .modmsk = ARMV7_A7_ATTRS, .code = 0xc7, .desc = "ETM Ext Out[0]" }, {.name = "ETM_EXT_OUT_1", .modmsk = ARMV7_A7_ATTRS, .code = 0xc8, .desc = "ETM Ext Out[1]" }, {.name = "DATA_WRITE_STALL", .modmsk = ARMV7_A7_ATTRS, .code = 0xc9, .desc = "Data write operation that stalls pipeline due to full store buffer" }, {.name = "DATA_SNOOPED", .modmsk = ARMV7_A7_ATTRS, .code = 0xca, .desc = "Data snooped from other processor" }, }; libpfm-4.9.0/lib/events/intel_knl_unc_cha_events.h0000664000175000017500000011272513223402656022074 0ustar eranianeranian/* * Copyright (c) 2016 Intel Corp. All rights reserved * Contributed by Peinan Zhang * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * PMU: knl_unc_cha (Intel Knights Landing CHA uncore PMU) */ static const intel_x86_umask_t knl_unc_cha_llc_lookup[]={ { .uname = "DATA_READ", .udesc = "Data read requests", .ucode = 0x0300, .uflags = INTEL_X86_NCOMBO, }, { .uname = "WRITE", .udesc = "Write requests. Includes all write transactions (cached, uncached)", .ucode = 0x0500, .uflags = INTEL_X86_NCOMBO, }, { .uname = "REMOTE_SNOOP", .udesc = "External snoop request", .ucode = 0x0900, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ANY", .udesc = "Any request", .ucode = 0x1100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t knl_unc_cha_llc_victims[]={ { .uname = "M_STATE", .udesc = "Lines in M state", .ucode = 0x0100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "E_STATE", .udesc = "Lines in E state", .ucode = 0x0200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "S_STATE", .udesc = "Lines in S state", .ucode = 0x0400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "F_STATE", .udesc = "Lines in F state", .ucode = 0x0800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "LOCAL", .udesc = "Victimized Lines matching the NID filter.", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "REMOTE", .udesc = "Victimized Lines does not matching the NID.", .ucode = 0x8000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t knl_unc_cha_ingress_int_starved[]={ { .uname = "IRQ", .udesc = "Internal starved with IRQ.", .ucode = 0x0100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "IPQ", .udesc = "Internal starved with IPQ.", .ucode = 0x0400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ISMQ", .udesc = "Internal starved with ISMQ.", .ucode = 0x0800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "PRQ", .udesc = "Internal starved with PRQ.", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t knl_unc_cha_ingress_ext[]={ { .uname = "IRQ", .udesc = "IRQ", .ucode = 0x0100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "IRQ_REJ", .udesc = "IRQ rejected", .ucode = 0x0200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "IPQ", .udesc = "IPQ", .ucode = 0x0400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "PRQ", .udesc = "PRQ", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "PRQ_REJ", .udesc = "PRQ rejected", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t knl_unc_cha_ingress_entry_reject_q0[]={ { .uname = "AD_REQ_VN0", .udesc = "AD Request", .ucode = 0x0100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "AD_RSP_VN0", .udesc = "AD Response", .ucode = 0x0200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "BL_RSP_VN0", .udesc = "BL Response", .ucode = 0x0400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "BL_WB_VN0", .udesc = "BL WB", .ucode = 0x0800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "BL_NCB_VN0", .udesc = "BL NCB", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "BL_NCS_VN0", .udesc = "BL NCS", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "AK_NON_UPI", .udesc = "AK non upi", .ucode = 0x4000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "IV_NON_UPI", .udesc = "IV non upi", .ucode = 0x8000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t knl_unc_cha_ingress_entry_reject_q1[]={ { .uname = "ANY_REJECT", .udesc = "Any reject from request queue0", .ucode = 0x0100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "SF_VICTIM", .udesc = "SF victim", .ucode = 0x0800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "SF_WAY", .udesc = "SF way", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ALLOW_SNP", .udesc = "allow snoop", .ucode = 0x4000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "PA_MATCH", .udesc = "PA match", .ucode = 0x8000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t knl_unc_cha_tor_subevent[]={ { .uname = "IRQ", .udesc = " -IRQ.", .ucode = 0x3100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "EVICT", .udesc = " -SF/LLC Evictions.", .ucode = 0x3200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "PRQ", .udesc = " -PRQ.", .ucode = 0x3400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "IPQ", .udesc = " -IPQ.", .ucode = 0x3800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "HIT", .udesc = " -Hit (Not a Miss).", .ucode = 0x1f00, .uflags = INTEL_X86_NCOMBO, }, { .uname = "MISS", .udesc = " -Miss.", .ucode = 0x2f00, .uflags = INTEL_X86_NCOMBO, }, { .uname = "IRQ_HIT", .udesc = " -IRQ HIT.", .ucode = 0x1100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "IRQ_MISS", .udesc = " -IRQ MISS.", .ucode = 0x2100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "PRQ_HIT", .udesc = " -PRQ HIT.", .ucode = 0x1400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "PRQ_MISS", .udesc = " -PRQ MISS.", .ucode = 0x2400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "IPQ_HIT", .udesc = " -IPQ HIT", .ucode = 0x1800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "IPQ_MISS", .udesc = " -IPQ MISS", .ucode = 0x2800, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t knl_unc_cha_misc[]={ { .uname = "RSPI_WAS_FSE", .udesc = "Silent Snoop Eviction", .ucode = 0x0100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "WC_ALIASING", .udesc = "Write Combining Aliasing.", .ucode = 0x0200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "RFO_HIT_S", .udesc = "Counts the number of times that an RFO hits in S state.", .ucode = 0x0800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "CV0_PREF_VIC", .udesc = "CV0 Prefetch Victim.", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "CV0_PREF_MISS", .udesc = "CV0 Prefetch Miss.", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t knl_unc_cha_tgr_ext[]={ { .uname = "TGR0", .udesc = "for Transgress 0", .ucode = 0x0100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "TGR1", .udesc = "for Transgress 1", .ucode = 0x0200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "TGR2", .udesc = "for Transgress 2", .ucode = 0x0400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "TGR3", .udesc = "for Transgress 3", .ucode = 0x0800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "TGR4", .udesc = "for Transgress 4", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "TGR5", .udesc = "for Transgress 5", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "TGR6", .udesc = "for Transgress 6", .ucode = 0x4000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "TGR7", .udesc = "for Transgress 7", .ucode = 0x8000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t knl_unc_cha_tgr_ext1[]={ { .uname = "TGR8", .udesc = "for Transgress 8", .ucode = 0x0100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ANY_OF_TGR0_THRU_TGR7", .udesc = "for Transgress 0-7", .ucode = 0x0200, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t knl_unc_cha_ring_type_agent[]={ { .uname = "AD_AG0", .udesc = "AD - Agent 0", .ucode = 0x0100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "AK_AG0", .udesc = "AK - Agent 0", .ucode = 0x0200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "BL_AG0", .udesc = "BL - Agent 0", .ucode = 0x0400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "IV_AG0", .udesc = "IV - Agent 0", .ucode = 0x0800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "AD_AG1", .udesc = "AD - Agent 1", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "AK_AG1", .udesc = "AK - Agent 1", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "BL_AG1", .udesc = "BL - Agent 1", .ucode = 0x4000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t knl_unc_cha_ring_type[]={ { .uname = "AD", .udesc = " - AD ring", .ucode = 0x0100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "AK", .udesc = " - AK ring", .ucode = 0x0200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "BL", .udesc = " - BL ring", .ucode = 0x0400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "IV", .udesc = " - IV ring", .ucode = 0x0800, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t knl_unc_cha_dire_ext[]={ { .uname = "VERT", .udesc = " - vertical", .ucode = 0x0000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "HORZ", .udesc = " - horizontal", .ucode = 0x0100, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t knl_unc_cha_ring_use_vert[]={ { .uname = "UP_EVEN", .udesc = "UP_EVEN", .ucode = 0x0100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "UP_ODD", .udesc = "UP_ODD", .ucode = 0x0200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "DN_EVEN", .udesc = "DN_EVEN", .ucode = 0x0200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "DN_ODD", .udesc = "DN_ODD", .ucode = 0x0400, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t knl_unc_cha_ring_use_hori[]={ { .uname = "LEFT_EVEN", .udesc = "LEFT_EVEN", .ucode = 0x0100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "LEFT_ODD", .udesc = "LEFT_ODD", .ucode = 0x0200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "RIGHT_EVEN", .udesc = "RIGHT_EVEN", .ucode = 0x0400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "RIGHT_ODD", .udesc = "RIGHT_ODD", .ucode = 0x0800, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t knl_unc_cha_ring_use_updn[]={ { .uname = "UP", .udesc = "up", .ucode = 0x0100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "DN", .udesc = "down", .ucode = 0x0400, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t knl_unc_cha_ring_use_lfrt[]={ { .uname = "LEFT", .udesc = "left", .ucode = 0x0100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "RIGHT", .udesc = "right", .ucode = 0x0400, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t knl_unc_cha_iv_snp[]={ { .uname = "IV_SNP_GO_UP", .udesc = "IV_SNP_GO_UP", .ucode = 0x0100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "IV_SNP_GO_DN", .udesc = "IV_SNP_GO_DN", .ucode = 0x0400, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t knl_unc_cha_cms_ext[]={ { .uname = "AD_BNC", .udesc = "AD_BNC", .ucode = 0x0100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "AK_BNC", .udesc = "AK_BNC", .ucode = 0x0200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "BL_BNC", .udesc = "BL_BNC", .ucode = 0x0400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "IV_BNC", .udesc = "IV_BNC", .ucode = 0x0800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "AD_CRD", .udesc = "AD_CRD", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "BL_CRD", .udesc = "AD_CRD", .ucode = 0x4000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t knl_unc_cha_cms_crd_starved[]={ { .uname = "AD_BNC", .udesc = "AD_BNC", .ucode = 0x0100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "AK_BNC", .udesc = "AK_BNC", .ucode = 0x0200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "BL_BNC", .udesc = "BL_BNC", .ucode = 0x0400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "IV_BNC", .udesc = "IV_BNC", .ucode = 0x0800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "AD_CRD", .udesc = "AD_CRD", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "BL_CRD", .udesc = "AD_CRD", .ucode = 0x4000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "IVF", .udesc = "IVF", .ucode = 0x8000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t knl_unc_cha_cms_busy_starved[]={ { .uname = "AD_BNC", .udesc = "AD_BNC", .ucode = 0x0100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "BL_BNC", .udesc = "BL_BNC", .ucode = 0x0400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "AD_CRD", .udesc = "AD_CRD", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "BL_CRD", .udesc = "AD_CRD", .ucode = 0x4000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_entry_t intel_knl_unc_cha_pe[]={ { .name = "UNC_H_U_CLOCKTICKS", .desc = "Uncore clockticks", .modmsk = 0x0, .cntmsk = 0xf, .code = 0x00, .flags = INTEL_X86_FIXED, }, { .name = "UNC_H_INGRESS_OCCUPANCY", .desc = "Ingress Occupancy. Ingress Occupancy. Counts number of entries in the specified Ingress queue in each cycle", .cntmsk = 0xf, .code = 0x11, .ngrp = 1, .flags = INTEL_X86_NO_AUTOENCODE, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_ingress_ext), .umasks = knl_unc_cha_ingress_ext, }, { .name = "UNC_H_INGRESS_INSERTS", .desc = "Ingress Allocations. Counts number of allocations per cycle into the specified Ingress queue", .cntmsk = 0xf, .code = 0x13, .ngrp = 1, .flags = INTEL_X86_NO_AUTOENCODE, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_ingress_ext), .umasks = knl_unc_cha_ingress_ext, }, { .name = "UNC_H_INGRESS_INT_STARVED", .desc = "Cycles Internal Starvation", .cntmsk = 0xf, .code = 0x14, .ngrp = 1, .flags = INTEL_X86_NO_AUTOENCODE, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_ingress_int_starved), .umasks = knl_unc_cha_ingress_int_starved, }, { .name = "UNC_H_INGRESS_RETRY_IRQ0_REJECT", .desc = "Ingress Request Queue Rejects", .cntmsk = 0xf, .code = 0x18, .ngrp = 1, .flags = INTEL_X86_NO_AUTOENCODE, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_ingress_entry_reject_q0), .umasks = knl_unc_cha_ingress_entry_reject_q0, }, { .name = "UNC_H_INGRESS_RETRY_IRQ01_REJECT", .desc = "Ingress Request Queue Rejects", .cntmsk = 0xf, .code = 0x19, .ngrp = 1, .flags = INTEL_X86_NO_AUTOENCODE, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_ingress_entry_reject_q1), .umasks = knl_unc_cha_ingress_entry_reject_q1, }, { .name = "UNC_H_INGRESS_RETRY_PRQ0_REJECT", .desc = "Ingress Request Queue Rejects", .cntmsk = 0xf, .code = 0x20, .ngrp = 1, .flags = INTEL_X86_NO_AUTOENCODE, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_ingress_entry_reject_q0), .umasks = knl_unc_cha_ingress_entry_reject_q0, }, { .name = "UNC_H_INGRESS_RETRY_PRQ1_REJECT", .desc = "Ingress Request Queue Rejects", .cntmsk = 0xf, .code = 0x21, .ngrp = 1, .flags = INTEL_X86_NO_AUTOENCODE, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_ingress_entry_reject_q1), .umasks = knl_unc_cha_ingress_entry_reject_q1, }, { .name = "UNC_H_INGRESS_RETRY_IPQ0_REJECT", .desc = "Ingress Request Queue Rejects", .cntmsk = 0xf, .code = 0x22, .ngrp = 1, .flags = INTEL_X86_NO_AUTOENCODE, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_ingress_entry_reject_q0), .umasks = knl_unc_cha_ingress_entry_reject_q0, }, { .name = "UNC_H_INGRESS_RETRY_IPQ1_REJECT", .desc = "Ingress Request Queue Rejects", .cntmsk = 0xf, .code = 0x23, .ngrp = 1, .flags = INTEL_X86_NO_AUTOENCODE, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_ingress_entry_reject_q1), .umasks = knl_unc_cha_ingress_entry_reject_q1, }, { .name = "UNC_H_INGRESS_RETRY_ISMQ0_REJECT", .desc = "ISMQ Rejects", .cntmsk = 0xf, .code = 0x24, .ngrp = 1, .flags = INTEL_X86_NO_AUTOENCODE, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_ingress_entry_reject_q0), .umasks = knl_unc_cha_ingress_entry_reject_q0, }, { .name = "UNC_H_INGRESS_RETRY_REQ_Q0_RETRY", .desc = "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", .cntmsk = 0xf, .code = 0x2a, .ngrp = 1, .flags = INTEL_X86_NO_AUTOENCODE, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_ingress_entry_reject_q0), .umasks = knl_unc_cha_ingress_entry_reject_q0, }, { .name = "UNC_H_INGRESS_RETRY_REQ_Q1_RETRY", .desc = "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", .cntmsk = 0xf, .code = 0x2b, .ngrp = 1, .flags = INTEL_X86_NO_AUTOENCODE, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_ingress_entry_reject_q1), .umasks = knl_unc_cha_ingress_entry_reject_q1, }, { .name = "UNC_H_INGRESS_RETRY_ISMQ0_RETRY", .desc = "ISMQ retries", .cntmsk = 0xf, .code = 0x2c, .ngrp = 1, .flags = INTEL_X86_NO_AUTOENCODE, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_ingress_entry_reject_q0), .umasks = knl_unc_cha_ingress_entry_reject_q0, }, { .name = "UNC_H_INGRESS_RETRY_OTHER0_RETRY", .desc = "Other Queue Retries", .cntmsk = 0xf, .code = 0x2e, .ngrp = 1, .flags = INTEL_X86_NO_AUTOENCODE, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_ingress_entry_reject_q0), .umasks = knl_unc_cha_ingress_entry_reject_q0, }, { .name = "UNC_H_INGRESS_RETRY_OTHER1_RETRY", .desc = "Other Queue Retries", .cntmsk = 0xf, .code = 0x2f, .ngrp = 1, .flags = INTEL_X86_NO_AUTOENCODE, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_ingress_entry_reject_q1), .umasks = knl_unc_cha_ingress_entry_reject_q1, }, { .name = "UNC_H_SF_LOOKUP", .desc = "Cache Lookups. Counts the number of times the LLC was accessed.", .cntmsk = 0xf, .code = 0x34, .ngrp = 1, .flags = INTEL_X86_NO_AUTOENCODE, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_llc_lookup), .umasks = knl_unc_cha_llc_lookup, }, { .name = "UNC_H_CACHE_LINES_VICTIMIZED", .desc = "Cache Lookups. Counts the number of times the LLC was accessed.", .cntmsk = 0xf, .code = 0x37, .ngrp = 1, .flags = INTEL_X86_NO_AUTOENCODE, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_llc_victims), .umasks = knl_unc_cha_llc_victims, }, { .name = "UNC_H_TOR_INSERTS", .desc = "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", .modmsk = KNL_UNC_CHA_TOR_ATTRS, .cntmsk = 0xf, .code = 0x35, .ngrp = 1, .flags = INTEL_X86_NO_AUTOENCODE, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_tor_subevent), .umasks = knl_unc_cha_tor_subevent }, { .name = "UNC_H_TOR_OCCUPANCY", .desc = "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent", .modmsk = KNL_UNC_CHA_TOR_ATTRS, .cntmsk = 0xf, .code = 0x36, .ngrp = 1, .flags = INTEL_X86_NO_AUTOENCODE, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_tor_subevent), .umasks = knl_unc_cha_tor_subevent }, { .name = "UNC_H_MISC", .desc = "Miscellaneous events in the Cha", .cntmsk = 0xf, .code = 0x39, .ngrp = 1, .flags = INTEL_X86_NO_AUTOENCODE, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_misc), .umasks = knl_unc_cha_misc, }, { .name = "UNC_H_AG0_AD_CRD_ACQUIRED", .desc = "CMS Agent0 AD Credits Acquired.", .cntmsk = 0xf, .code = 0x80, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_tgr_ext), .umasks = knl_unc_cha_tgr_ext, }, { .name = "UNC_H_AG0_AD_CRD_ACQUIRED_EXT", .desc = "CMS Agent0 AD Credits Acquired.", .cntmsk = 0xf, .code = 0x81, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_tgr_ext1), .umasks = knl_unc_cha_tgr_ext1, }, { .name = "UNC_H_AG0_AD_CRD_OCCUPANCY", .desc = "CMS Agent0 AD Credits Occupancy.", .cntmsk = 0xf, .code = 0x82, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_tgr_ext), .umasks = knl_unc_cha_tgr_ext, }, { .name = "UNC_H_AG0_AD_CRD_OCCUPANCY_EXT", .desc = "CMS Agent0 AD Credits Acquired For Transgress.", .cntmsk = 0xf, .code = 0x83, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_tgr_ext1), .umasks = knl_unc_cha_tgr_ext1, }, { .name = "UNC_H_AG1_AD_CRD_ACQUIRED", .desc = "CMS Agent1 AD Credits Acquired .", .cntmsk = 0xf, .code = 0x84, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_tgr_ext), .umasks = knl_unc_cha_tgr_ext, }, { .name = "UNC_H_AG1_AD_CRD_ACQUIRED_EXT", .desc = "CMS Agent1 AD Credits Acquired .", .cntmsk = 0xf, .code = 0x85, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_tgr_ext1), .umasks = knl_unc_cha_tgr_ext1, }, { .name = "UNC_H_AG1_AD_CRD_OCCUPANCY", .desc = "CMS Agent1 AD Credits Occupancy.", .cntmsk = 0xf, .code = 0x86, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_tgr_ext), .umasks = knl_unc_cha_tgr_ext, }, { .name = "UNC_H_AG1_AD_CRD_OCCUPANCY_EXT", .desc = "CMS Agent1 AD Credits Occupancy.", .cntmsk = 0xf, .code = 0x87, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_tgr_ext1), .umasks = knl_unc_cha_tgr_ext1, }, { .name = "UNC_H_AG0_BL_CRD_ACQUIRED", .desc = "CMS Agent0 BL Credits Acquired.", .cntmsk = 0xf, .code = 0x88, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_tgr_ext), .umasks = knl_unc_cha_tgr_ext, }, { .name = "UNC_H_AG0_BL_CRD_ACQUIRED_EXT", .desc = "CMS Agent0 BL Credits Acquired.", .cntmsk = 0xf, .code = 0x89, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_tgr_ext1), .umasks = knl_unc_cha_tgr_ext1, }, { .name = "UNC_H_AG0_BL_CRD_OCCUPANCY", .desc = "CMS Agent0 BL Credits Occupancy.", .cntmsk = 0xf, .code = 0x8a, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_tgr_ext), .umasks = knl_unc_cha_tgr_ext, }, { .name = "UNC_H_AG0_BL_CRD_OCCUPANCY_EXT", .desc = "CMS Agent0 BL Credits Occupancy.", .cntmsk = 0xf, .code = 0x8b, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_tgr_ext1), .umasks = knl_unc_cha_tgr_ext1, }, { .name = "UNC_H_AG1_BL_CRD_ACQUIRED", .desc = "CMS Agent1 BL Credits Acquired.", .cntmsk = 0xf, .code = 0x8c, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_tgr_ext), .umasks = knl_unc_cha_tgr_ext, }, { .name = "UNC_H_AG1_BL_CRD_ACQUIRED_EXT", .desc = "CMS Agent1 BL Credits Acquired.", .cntmsk = 0xf, .code = 0x8d, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_tgr_ext1), .umasks = knl_unc_cha_tgr_ext1, }, { .name = "UNC_H_AG1_BL_CRD_OCCUPANCY", .desc = "CMS Agent1 BL Credits Occupancy.", .cntmsk = 0xf, .code = 0x8e, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_tgr_ext), .umasks = knl_unc_cha_tgr_ext, }, { .name = "UNC_H_AG1_BL_CRD_OCCUPANCY_EXT", .desc = "CMS Agent1 BL Credits Occupancy.", .cntmsk = 0xf, .code = 0x8f, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_tgr_ext1), .umasks = knl_unc_cha_tgr_ext1, }, { .name = "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD", .desc = "Stall on No AD Transgress Credits.", .cntmsk = 0xf, .code = 0xD0, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_tgr_ext), .umasks = knl_unc_cha_tgr_ext, }, { .name = "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD_EXT", .desc = "Stall on No AD Transgress Credits.", .cntmsk = 0xf, .code = 0xD1, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_tgr_ext1), .umasks = knl_unc_cha_tgr_ext1, }, { .name = "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD", .desc = "Stall on No AD Transgress Credits.", .cntmsk = 0xf, .code = 0xD2, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_tgr_ext), .umasks = knl_unc_cha_tgr_ext, }, { .name = "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD_EXT", .desc = "Stall on No AD Transgress Credits.", .cntmsk = 0xf, .code = 0xD3, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_tgr_ext1), .umasks = knl_unc_cha_tgr_ext1, }, { .name = "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL", .desc = "Stall on No AD Transgress Credits.", .cntmsk = 0xf, .code = 0xD4, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_tgr_ext), .umasks = knl_unc_cha_tgr_ext, }, { .name = "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL_EXT", .desc = "Stall on No AD Transgress Credits.", .cntmsk = 0xf, .code = 0xD5, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_tgr_ext1), .umasks = knl_unc_cha_tgr_ext1, }, { .name = "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL", .desc = "Stall on No AD Transgress Credits.", .cntmsk = 0xf, .code = 0xD6, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_tgr_ext), .umasks = knl_unc_cha_tgr_ext, }, { .name = "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL_EXT", .desc = "Stall on No AD Transgress Credits.", .cntmsk = 0xf, .code = 0xD7, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_tgr_ext1), .umasks = knl_unc_cha_tgr_ext1, }, { .name = "UNC_H_EGRESS_VERT_OCCUPANCY", .desc = "CMS Vert Egress Occupancy.", .cntmsk = 0xf, .code = 0x90, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_ring_type_agent), .umasks = knl_unc_cha_ring_type_agent, }, { .name = "UNC_H_EGRESS_VERT_INSERTS", .desc = "CMS Vert Egress Allocations.", .cntmsk = 0xf, .code = 0x91, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_ring_type_agent), .umasks = knl_unc_cha_ring_type_agent, }, { .name = "UNC_H_EGRESS_VERT_CYCLES_FULL", .desc = "Cycles CMS Vertical Egress Queue Is Full.", .cntmsk = 0xf, .code = 0x92, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_ring_type_agent), .umasks = knl_unc_cha_ring_type_agent, }, { .name = "UNC_H_EGRESS_VERT_CYCLES_NE", .desc = "Cycles CMS Vertical Egress Queue Is Not Empty.", .cntmsk = 0xf, .code = 0x93, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_ring_type_agent), .umasks = knl_unc_cha_ring_type_agent, }, { .name = "UNC_H_EGRESS_VERT_NACK", .desc = "CMS Vertical Egress NACKs.", .cntmsk = 0xf, .code = 0x98, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_ring_type_agent), .umasks = knl_unc_cha_ring_type_agent, }, { .name = "UNC_H_EGRESS_VERT_STARVED", .desc = "CMS Vertical Egress Injection Starvation.", .cntmsk = 0xf, .code = 0x9a, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_ring_type_agent), .umasks = knl_unc_cha_ring_type_agent, }, { .name = "UNC_H_EGRESS_VERT_ADS_USED", .desc = "CMS Vertical ADS Used.", .cntmsk = 0xf, .code = 0x9c, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_ring_type_agent), .umasks = knl_unc_cha_ring_type_agent, }, { .name = "UNC_H_EGRESS_VERT_BYPASS", .desc = "CMS Vertical Egress Bypass.", .cntmsk = 0xf, .code = 0x9e, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_ring_type_agent), .umasks = knl_unc_cha_ring_type_agent, }, { .name = "UNC_H_EGRESS_HORZ_OCCUPANCY", .desc = "CMS Horizontal Egress Occupancy.", .cntmsk = 0xf, .code = 0x94, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_ring_type), .umasks = knl_unc_cha_ring_type, }, { .name = "UNC_H_EGRESS_HORZ_INSERTS", .desc = "CMS Horizontal Egress Inserts.", .cntmsk = 0xf, .code = 0x95, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_ring_type), .umasks = knl_unc_cha_ring_type, }, { .name = "UNC_H_EGRESS_HORZ_CYCLES_FULL", .desc = "Cycles CMS Horizontal Egress Queue is Full.", .cntmsk = 0xf, .code = 0x96, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_ring_type), .umasks = knl_unc_cha_ring_type, }, { .name = "UNC_H_EGRESS_HORZ_CYCLES_NE", .desc = "Cycles CMS Horizontal Egress Queue is Not Empty.", .cntmsk = 0xf, .code = 0x97, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_ring_type), .umasks = knl_unc_cha_ring_type, }, { .name = "UNC_H_EGRESS_HORZ_NACK", .desc = "CMS Horizontal Egress NACKs.", .cntmsk = 0xf, .code = 0x99, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_ring_type), .umasks = knl_unc_cha_ring_type, }, { .name = "UNC_H_EGRESS_HORZ_STARVED", .desc = "CMS Horizontal Egress Injection Starvation.", .cntmsk = 0xf, .code = 0x9b, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_ring_type), .umasks = knl_unc_cha_ring_type, }, { .name = "UNC_H_EGRESS_HORZ_ADS_USED", .desc = "CMS Horizontal ADS Used.", .cntmsk = 0xf, .code = 0x9d, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_ring_type), .umasks = knl_unc_cha_ring_type, }, { .name = "UNC_H_EGRESS_HORZ_BYPASS", .desc = "CMS Horizontal Egress Bypass.", .cntmsk = 0xf, .code = 0x9f, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_ring_type), .umasks = knl_unc_cha_ring_type, }, { .name = "UNC_H_RING_BOUNCES_VERT", .desc = "Number of incoming messages from the Vertical ring that were bounced, by ring type.", .cntmsk = 0xf, .code = 0xa0, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_ring_type), .umasks = knl_unc_cha_ring_type, }, { .name = "UNC_H_RING_BOUNCES_HORZ", .desc = "Number of incoming messages from the Horizontal ring that were bounced, by ring type.", .cntmsk = 0xf, .code = 0xa1, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_ring_type), .umasks = knl_unc_cha_ring_type, }, { .name = "UNC_H_RING_SINK_STARVED_VERT", .desc = "Vertical ring sink starvation count.", .cntmsk = 0xf, .code = 0xa2, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_ring_type), .umasks = knl_unc_cha_ring_type, }, { .name = "UNC_H_RING_SINK_STARVED_HORZ", .desc = "Horizontal ring sink starvation count.", .cntmsk = 0xf, .code = 0xa3, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_ring_type), .umasks = knl_unc_cha_ring_type, }, { .name = "UNC_H_RING_SRC_THRT", .desc = "Counts cycles in throttle mode.", .cntmsk = 0xf, .code = 0xa4, }, { .name = "UNC_H_FAST_ASSERTED", .desc = "Counts cycles source throttling is adderted", .cntmsk = 0xf, .code = 0xa5, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_dire_ext), .umasks = knl_unc_cha_dire_ext, }, { .name = "UNC_H_VERT_RING_AD_IN_USE", .desc = "Counts the number of cycles that the Vertical AD ring is being used at this ring stop.", .cntmsk = 0xf, .code = 0xa6, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_ring_use_vert), .umasks = knl_unc_cha_ring_use_vert, }, { .name = "UNC_H_HORZ_RING_AD_IN_USE", .desc = "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.", .cntmsk = 0xf, .code = 0xa7, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_ring_use_hori), .umasks = knl_unc_cha_ring_use_hori, }, { .name = "UNC_H_VERT_RING_AK_IN_USE", .desc = "Counts the number of cycles that the Vertical AK ring is being used at this ring stop.", .cntmsk = 0xf, .code = 0xa8, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_ring_use_vert), .umasks = knl_unc_cha_ring_use_vert, }, { .name = "UNC_H_HORZ_RING_AK_IN_USE", .desc = "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.", .cntmsk = 0xf, .code = 0xa9, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_ring_use_hori), .umasks = knl_unc_cha_ring_use_hori, }, { .name = "UNC_H_VERT_RING_BL_IN_USE", .desc = "Counts the number of cycles that the Vertical BL ring is being used at this ring stop.", .cntmsk = 0xf, .code = 0xaa, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_ring_use_vert), .umasks = knl_unc_cha_ring_use_vert, }, { .name = "UNC_H_HORZ_RING_BL_IN_USE", .desc = "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.", .cntmsk = 0xf, .code = 0xab, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_ring_use_hori), .umasks = knl_unc_cha_ring_use_hori, }, { .name = "UNC_H_VERT_RING_IV_IN_USE", .desc = "Counts the number of cycles that the Vertical IV ring is being used at this ring stop.", .cntmsk = 0xf, .code = 0xac, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_ring_use_updn), .umasks = knl_unc_cha_ring_use_updn, }, { .name = "UNC_H_HORZ_RING_IV_IN_USE", .desc = "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop.", .cntmsk = 0xf, .code = 0xad, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_ring_use_lfrt), .umasks = knl_unc_cha_ring_use_lfrt, }, { .name = "UNC_H_EGRESS_ORDERING", .desc = "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements.", .cntmsk = 0xf, .code = 0xae, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_iv_snp), .umasks = knl_unc_cha_iv_snp, }, { .name = "UNC_H_TG_INGRESS_OCCUPANCY", .desc = "Transgress Ingress Occupancy. Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh.", .cntmsk = 0xf, .code = 0xb0, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_cms_ext), .umasks = knl_unc_cha_cms_ext, }, { .name = "UNC_H_TG_INGRESS_INSERTS", .desc = "Transgress Ingress Allocations. Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh.", .cntmsk = 0xf, .code = 0xb1, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_cms_ext), .umasks = knl_unc_cha_cms_ext, }, { .name = "UNC_H_TG_INGRESS_BYPASS", .desc = "Transgress Ingress Bypass. Number of packets bypassing the CMS Ingress.", .cntmsk = 0xf, .code = 0xb2, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_cms_ext), .umasks = knl_unc_cha_cms_ext, }, { .name = "UNC_H_TG_INGRESS_CRD_STARVED", .desc = "Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", .cntmsk = 0xf, .code = 0xb3, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_cms_crd_starved), .umasks = knl_unc_cha_cms_crd_starved, }, { .name = "UNC_H_TG_INGRESS_BUSY_STARVED", .desc = "Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority.", .cntmsk = 0xf, .code = 0xb4, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_cha_cms_busy_starved), .umasks = knl_unc_cha_cms_busy_starved, }, }; libpfm-4.9.0/lib/events/intel_snbep_unc_qpi_events.h0000664000175000017500000003154413223402656022454 0ustar eranianeranian/* * Copyright (c) 2012 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * This file has been automatically generated. * * PMU: snbep_unc_qpi (Intel SandyBridge-EP QPI uncore) */ static const intel_x86_umask_t snbep_unc_q_direct2core[]={ { .uname = "FAILURE_CREDITS", .udesc = "Number of spawn failures due to lack of Egress credits", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "FAILURE_CREDITS_RBT", .udesc = "Number of spawn failures due to lack of Egress credit and route-back table (RBT) bit was not set", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "FAILURE_RBT", .udesc = "Number of spawn failures because route-back table (RBT) specified that the transaction should not trigger a direct2core transaction", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "SUCCESS", .udesc = "Number of spawn successes", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t snbep_unc_q_rxl_credits_consumed_vn0[]={ { .uname = "DRS", .udesc = "Number of times VN0 consumed for DRS message class", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "HOM", .udesc = "Number of times VN0 consumed for HOM message class", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "NCB", .udesc = "Number of times VN0 consumed for NCB message class", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "NCS", .udesc = "Number of times VN0 consumed for NCS message class", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "NDR", .udesc = "Number of times VN0 consumed for NDR message class", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "SNP", .udesc = "Number of times VN0 consumed for SNP message class", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t snbep_unc_q_rxl_flits_g0[]={ { .uname = "DATA", .udesc = "Number of data flits over QPI", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "IDLE", .udesc = "Number of flits over QPI that do not hold protocol payload", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "NON_DATA", .udesc = "Number of non-NULL non-data flits over QPI", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t snbep_unc_q_rxl_flits_g1[]={ { .uname = "DRS", .udesc = "Number of flits over QPI on the Data Response (DRS) channel", .ucode = 0x1800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "DRS_DATA", .udesc = "Number of data flits over QPI on the Data Response (DRS) channel", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "DRS_NONDATA", .udesc = "Number of protocol flits over QPI on the Data Response (DRS) channel", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "HOM", .udesc = "Number of flits over QPI on the home channel", .ucode = 0x600, .uflags = INTEL_X86_NCOMBO, }, { .uname = "HOM_NONREQ", .udesc = "Number of non-request flits over QPI on the home channel", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "HOM_REQ", .udesc = "Number of data requests over QPI on the home channel", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "SNP", .udesc = "Number of snoop requests flits over QPI", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t snbep_unc_q_rxl_flits_g2[]={ { .uname = "NCB", .udesc = "Number of non-coherent bypass flits", .ucode = 0xc00, .uflags = INTEL_X86_NCOMBO, }, { .uname = "NCB_DATA", .udesc = "Number of non-coherent data flits", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "NCB_NONDATA", .udesc = "Number of bypass non-data flits", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "NCS", .udesc = "Number of non-coherent standard (NCS) flits", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "NDR_AD", .udesc = "Number of flits received over Non-data response (NDR) channel", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "NDR_AK", .udesc = "Number of flits received on the Non-data response (NDR) channel)", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_entry_t intel_snbep_unc_q_pe[]={ { .name = "UNC_Q_CLOCKTICKS", .desc = "Number of qfclks", .code = 0x14, .cntmsk = 0xf, .modmsk = SNBEP_UNC_QPI_ATTRS, }, { .name = "UNC_Q_CTO_COUNT", .desc = "Count of CTO Events", .code = 0x38, .cntmsk = 0xf, .modmsk = SNBEP_UNC_QPI_ATTRS, }, { .name = "UNC_Q_DIRECT2CORE", .desc = "Direct 2 Core Spawning", .code = 0x13, .cntmsk = 0xf, .ngrp = 1, .modmsk = SNBEP_UNC_QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_q_direct2core), .umasks = snbep_unc_q_direct2core }, { .name = "UNC_Q_L1_POWER_CYCLES", .desc = "Cycles in L1", .code = 0x12, .cntmsk = 0xf, .modmsk = SNBEP_UNC_QPI_ATTRS, }, { .name = "UNC_Q_RXL0P_POWER_CYCLES", .desc = "Cycles in L0p", .code = 0x10, .cntmsk = 0xf, .modmsk = SNBEP_UNC_QPI_ATTRS, }, { .name = "UNC_Q_RXL0_POWER_CYCLES", .desc = "Cycles in L0", .code = 0xf, .cntmsk = 0xf, .modmsk = SNBEP_UNC_QPI_ATTRS, }, { .name = "UNC_Q_RXL_BYPASSED", .desc = "Rx Flit Buffer Bypassed", .code = 0x9, .cntmsk = 0xf, .modmsk = SNBEP_UNC_QPI_ATTRS, }, { .name = "UNC_Q_RXL_CREDITS_CONSUMED_VN0", .desc = "VN0 Credit Consumed", .code = 0x1e | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .ngrp = 1, .modmsk = SNBEP_UNC_QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_q_rxl_credits_consumed_vn0), .umasks = snbep_unc_q_rxl_credits_consumed_vn0 }, { .name = "UNC_Q_RXL_CREDITS_CONSUMED_VNA", .desc = "VNA Credit Consumed", .code = 0x1d | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = SNBEP_UNC_QPI_ATTRS, }, { .name = "UNC_Q_RXL_CYCLES_NE", .desc = "RxQ Cycles Not Empty", .code = 0xa, .cntmsk = 0xf, .modmsk = SNBEP_UNC_QPI_ATTRS, }, { .name = "UNC_Q_RXL_FLITS_G0", .desc = "Flits Received - Group 0", .code = 0x1, .cntmsk = 0xf, .ngrp = 1, .modmsk = SNBEP_UNC_QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_q_rxl_flits_g0), .umasks = snbep_unc_q_rxl_flits_g0 }, { .name = "UNC_Q_RXL_FLITS_G1", .desc = "Flits Received - Group 1", .code = 0x2 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .ngrp = 1, .modmsk = SNBEP_UNC_QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_q_rxl_flits_g1), .umasks = snbep_unc_q_rxl_flits_g1 }, { .name = "UNC_Q_RXL_FLITS_G2", .desc = "Flits Received - Group 2", .code = 0x3 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .ngrp = 1, .modmsk = SNBEP_UNC_QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_q_rxl_flits_g2), .umasks = snbep_unc_q_rxl_flits_g2 }, { .name = "UNC_Q_RXL_INSERTS", .desc = "Rx Flit Buffer Allocations", .code = 0x8, .cntmsk = 0xf, .modmsk = SNBEP_UNC_QPI_ATTRS, }, { .name = "UNC_Q_RXL_INSERTS_DRS", .desc = "Rx Flit Buffer Allocations - DRS", .code = 0x9 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = SNBEP_UNC_QPI_ATTRS, }, { .name = "UNC_Q_RXL_INSERTS_HOM", .desc = "Rx Flit Buffer Allocations - HOM", .code = 0xc | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = SNBEP_UNC_QPI_ATTRS, }, { .name = "UNC_Q_RXL_INSERTS_NCB", .desc = "Rx Flit Buffer Allocations - NCB", .code = 0xa | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = SNBEP_UNC_QPI_ATTRS, }, { .name = "UNC_Q_RXL_INSERTS_NCS", .desc = "Rx Flit Buffer Allocations - NCS", .code = 0xb | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = SNBEP_UNC_QPI_ATTRS, }, { .name = "UNC_Q_RXL_INSERTS_NDR", .desc = "Rx Flit Buffer Allocations - NDR", .code = 0xe | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = SNBEP_UNC_QPI_ATTRS, }, { .name = "UNC_Q_RXL_INSERTS_SNP", .desc = "Rx Flit Buffer Allocations - SNP", .code = 0xd | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = SNBEP_UNC_QPI_ATTRS, }, { .name = "UNC_Q_RXL_OCCUPANCY", .desc = "RxQ Occupancy - All Packets", .code = 0xb, .cntmsk = 0xf, .modmsk = SNBEP_UNC_QPI_ATTRS, }, { .name = "UNC_Q_RXL_OCCUPANCY_DRS", .desc = "RxQ Occupancy - DRS", .code = 0x15 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = SNBEP_UNC_QPI_ATTRS, }, { .name = "UNC_Q_RXL_OCCUPANCY_HOM", .desc = "RxQ Occupancy - HOM", .code = 0x18 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = SNBEP_UNC_QPI_ATTRS, }, { .name = "UNC_Q_RXL_OCCUPANCY_NCB", .desc = "RxQ Occupancy - NCB", .code = 0x16 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = SNBEP_UNC_QPI_ATTRS, }, { .name = "UNC_Q_RXL_OCCUPANCY_NCS", .desc = "RxQ Occupancy - NCS", .code = 0x17 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = SNBEP_UNC_QPI_ATTRS, }, { .name = "UNC_Q_RXL_OCCUPANCY_NDR", .desc = "RxQ Occupancy - NDR", .code = 0x1a | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = SNBEP_UNC_QPI_ATTRS, }, { .name = "UNC_Q_RXL_OCCUPANCY_SNP", .desc = "RxQ Occupancy - SNP", .code = 0x19 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = SNBEP_UNC_QPI_ATTRS, }, { .name = "UNC_Q_TXL0P_POWER_CYCLES", .desc = "Cycles in L0p", .code = 0xd, .cntmsk = 0xf, .modmsk = SNBEP_UNC_QPI_ATTRS, }, { .name = "UNC_Q_TXL0_POWER_CYCLES", .desc = "Cycles in L0", .code = 0xc, .cntmsk = 0xf, .modmsk = SNBEP_UNC_QPI_ATTRS, }, { .name = "UNC_Q_TXL_BYPASSED", .desc = "Tx Flit Buffer Bypassed", .code = 0x5, .cntmsk = 0xf, .modmsk = SNBEP_UNC_QPI_ATTRS, }, { .name = "UNC_Q_TXL_CYCLES_NE", .desc = "Tx Flit Buffer Cycles not Empty", .code = 0x6, .cntmsk = 0xf, .modmsk = SNBEP_UNC_QPI_ATTRS, }, { .name = "UNC_Q_TXL_FLITS_G0", .desc = "Flits Transferred - Group 0", .code = 0x0, .cntmsk = 0xf, .ngrp = 1, .modmsk = SNBEP_UNC_QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_q_rxl_flits_g0), .umasks = snbep_unc_q_rxl_flits_g0 /* shared with rxl_flits_g0 */ }, { .name = "UNC_Q_TXL_FLITS_G1", .desc = "Flits Transferred - Group 1", .code = 0x0 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .ngrp = 1, .modmsk = SNBEP_UNC_QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_q_rxl_flits_g1), .umasks = snbep_unc_q_rxl_flits_g1 /* shared with rxl_flits_g1 */ }, { .name = "UNC_Q_TXL_FLITS_G2", .desc = "Flits Transferred - Group 2", .code = 0x1 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .ngrp = 1, .modmsk = SNBEP_UNC_QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_q_rxl_flits_g2), .umasks = snbep_unc_q_rxl_flits_g2 /* shared with rxl_flits_g2 */ }, { .name = "UNC_Q_TXL_INSERTS", .desc = "Tx Flit Buffer Allocations", .code = 0x4, .cntmsk = 0xf, .modmsk = SNBEP_UNC_QPI_ATTRS, }, { .name = "UNC_Q_TXL_OCCUPANCY", .desc = "Tx Flit Buffer Occupancy", .code = 0x7, .cntmsk = 0xf, .modmsk = SNBEP_UNC_QPI_ATTRS, }, { .name = "UNC_Q_VNA_CREDIT_RETURNS", .desc = "VNA Credits Returned", .code = 0x1c | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = SNBEP_UNC_QPI_ATTRS, }, { .name = "UNC_Q_VNA_CREDIT_RETURN_OCCUPANCY", .desc = "VNA Credits Pending Return - Occupancy", .code = 0x1b | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = SNBEP_UNC_QPI_ATTRS, }, }; libpfm-4.9.0/lib/events/intel_wsm_unc_events.h0000664000175000017500000011444113223402656021300 0ustar eranianeranian/* * Copyright (c) 2011 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * This file has been automatically generated. * * PMU: wsm_unc (Intel Westmere uncore) */ static const intel_x86_umask_t wsm_unc_unc_dram_open[]={ { .uname = "CH0", .udesc = "DRAM Channel 0 open commands issued for read or write", .ucode = 0x100, }, { .uname = "CH1", .udesc = "DRAM Channel 1 open commands issued for read or write", .ucode = 0x200, }, { .uname = "CH2", .udesc = "DRAM Channel 2 open commands issued for read or write", .ucode = 0x400, }, }; static const intel_x86_umask_t wsm_unc_unc_gc_occupancy[]={ { .uname = "READ_TRACKER", .udesc = "In the read tracker", .ucode = 0x100, .uflags= INTEL_X86_DFL, }, }; static const intel_x86_umask_t wsm_unc_unc_dram_page_close[]={ { .uname = "CH0", .udesc = "DRAM Channel 0 page close", .ucode = 0x100, }, { .uname = "CH1", .udesc = "DRAM Channel 1 page close", .ucode = 0x200, }, { .uname = "CH2", .udesc = "DRAM Channel 2 page close", .ucode = 0x400, }, }; static const intel_x86_umask_t wsm_unc_unc_dram_page_miss[]={ { .uname = "CH0", .udesc = "DRAM Channel 0 page miss", .ucode = 0x100, }, { .uname = "CH1", .udesc = "DRAM Channel 1 page miss", .ucode = 0x200, }, { .uname = "CH2", .udesc = "DRAM Channel 2 page miss", .ucode = 0x400, }, }; static const intel_x86_umask_t wsm_unc_unc_dram_pre_all[]={ { .uname = "CH0", .udesc = "DRAM Channel 0 precharge all commands", .ucode = 0x100, }, { .uname = "CH1", .udesc = "DRAM Channel 1 precharge all commands", .ucode = 0x200, }, { .uname = "CH2", .udesc = "DRAM Channel 2 precharge all commands", .ucode = 0x400, }, }; static const intel_x86_umask_t wsm_unc_unc_dram_read_cas[]={ { .uname = "CH0", .udesc = "DRAM Channel 0 read CAS commands", .ucode = 0x100, }, { .uname = "AUTOPRE_CH0", .udesc = "DRAM Channel 0 read CAS auto page close commands", .ucode = 0x200, }, { .uname = "CH1", .udesc = "DRAM Channel 1 read CAS commands", .ucode = 0x400, }, { .uname = "AUTOPRE_CH1", .udesc = "DRAM Channel 1 read CAS auto page close commands", .ucode = 0x800, }, { .uname = "CH2", .udesc = "DRAM Channel 2 read CAS commands", .ucode = 0x1000, }, { .uname = "AUTOPRE_CH2", .udesc = "DRAM Channel 2 read CAS auto page close commands", .ucode = 0x2000, }, }; static const intel_x86_umask_t wsm_unc_unc_dram_refresh[]={ { .uname = "CH0", .udesc = "DRAM Channel 0 refresh commands", .ucode = 0x100, }, { .uname = "CH1", .udesc = "DRAM Channel 1 refresh commands", .ucode = 0x200, }, { .uname = "CH2", .udesc = "DRAM Channel 2 refresh commands", .ucode = 0x400, }, }; static const intel_x86_umask_t wsm_unc_unc_dram_write_cas[]={ { .uname = "CH0", .udesc = "DRAM Channel 0 write CAS commands", .ucode = 0x100, }, { .uname = "AUTOPRE_CH0", .udesc = "DRAM Channel 0 write CAS auto page close commands", .ucode = 0x200, }, { .uname = "CH1", .udesc = "DRAM Channel 1 write CAS commands", .ucode = 0x400, }, { .uname = "AUTOPRE_CH1", .udesc = "DRAM Channel 1 write CAS auto page close commands", .ucode = 0x800, }, { .uname = "CH2", .udesc = "DRAM Channel 2 write CAS commands", .ucode = 0x1000, }, { .uname = "AUTOPRE_CH2", .udesc = "DRAM Channel 2 write CAS auto page close commands", .ucode = 0x2000, }, }; static const intel_x86_umask_t wsm_unc_unc_gq_alloc[]={ { .uname = "READ_TRACKER", .udesc = "GQ read tracker requests", .ucode = 0x100, }, { .uname = "RT_LLC_MISS", .udesc = "GQ read tracker LLC misses", .ucode = 0x200, }, { .uname = "RT_TO_LLC_RESP", .udesc = "GQ read tracker LLC requests", .ucode = 0x400, }, { .uname = "RT_TO_RTID_ACQUIRED", .udesc = "GQ read tracker LLC miss to RTID acquired", .ucode = 0x800, }, { .uname = "WT_TO_RTID_ACQUIRED", .udesc = "GQ write tracker LLC miss to RTID acquired", .ucode = 0x1000, }, { .uname = "WRITE_TRACKER", .udesc = "GQ write tracker LLC misses", .ucode = 0x2000, }, { .uname = "PEER_PROBE_TRACKER", .udesc = "GQ peer probe tracker requests", .ucode = 0x4000, }, }; static const intel_x86_umask_t wsm_unc_unc_gq_cycles_full[]={ { .uname = "READ_TRACKER", .udesc = "Cycles GQ read tracker is full.", .ucode = 0x100, }, { .uname = "WRITE_TRACKER", .udesc = "Cycles GQ write tracker is full.", .ucode = 0x200, }, { .uname = "PEER_PROBE_TRACKER", .udesc = "Cycles GQ peer probe tracker is full.", .ucode = 0x400, }, }; static const intel_x86_umask_t wsm_unc_unc_gq_cycles_not_empty[]={ { .uname = "READ_TRACKER", .udesc = "Cycles GQ read tracker is busy", .ucode = 0x100, }, { .uname = "WRITE_TRACKER", .udesc = "Cycles GQ write tracker is busy", .ucode = 0x200, }, { .uname = "PEER_PROBE_TRACKER", .udesc = "Cycles GQ peer probe tracker is busy", .ucode = 0x400, }, }; static const intel_x86_umask_t wsm_unc_unc_gq_data_from[]={ { .uname = "QPI", .udesc = "Cycles GQ data is imported from Quickpath interface", .ucode = 0x100, }, { .uname = "QMC", .udesc = "Cycles GQ data is imported from Quickpath memory interface", .ucode = 0x200, }, { .uname = "LLC", .udesc = "Cycles GQ data is imported from LLC", .ucode = 0x400, }, { .uname = "CORES_02", .udesc = "Cycles GQ data is imported from Cores 0 and 2", .ucode = 0x800, }, { .uname = "CORES_13", .udesc = "Cycles GQ data is imported from Cores 1 and 3", .ucode = 0x1000, }, }; static const intel_x86_umask_t wsm_unc_unc_gq_data_to[]={ { .uname = "QPI_QMC", .udesc = "Cycles GQ data sent to the QPI or QMC", .ucode = 0x100, }, { .uname = "LLC", .udesc = "Cycles GQ data sent to LLC", .ucode = 0x200, }, { .uname = "CORES", .udesc = "Cycles GQ data sent to cores", .ucode = 0x400, }, }; static const intel_x86_umask_t wsm_unc_unc_llc_hits[]={ { .uname = "READ", .udesc = "Number of LLC read hits", .ucode = 0x100, }, { .uname = "WRITE", .udesc = "Number of LLC write hits", .ucode = 0x200, }, { .uname = "PROBE", .udesc = "Number of LLC peer probe hits", .ucode = 0x400, }, { .uname = "ANY", .udesc = "Number of LLC hits", .ucode = 0x300, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t wsm_unc_unc_llc_lines_in[]={ { .uname = "M_STATE", .udesc = "LLC lines allocated in M state", .ucode = 0x100, }, { .uname = "E_STATE", .udesc = "LLC lines allocated in E state", .ucode = 0x200, }, { .uname = "S_STATE", .udesc = "LLC lines allocated in S state", .ucode = 0x400, }, { .uname = "F_STATE", .udesc = "LLC lines allocated in F state", .ucode = 0x800, }, { .uname = "ANY", .udesc = "LLC lines allocated", .ucode = 0xf00, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t wsm_unc_unc_llc_lines_out[]={ { .uname = "M_STATE", .udesc = "LLC lines victimized in M state", .ucode = 0x100, }, { .uname = "E_STATE", .udesc = "LLC lines victimized in E state", .ucode = 0x200, }, { .uname = "S_STATE", .udesc = "LLC lines victimized in S state", .ucode = 0x400, }, { .uname = "I_STATE", .udesc = "LLC lines victimized in I state", .ucode = 0x800, }, { .uname = "F_STATE", .udesc = "LLC lines victimized in F state", .ucode = 0x1000, }, { .uname = "ANY", .udesc = "LLC lines victimized", .ucode = 0x1f00, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t wsm_unc_unc_llc_miss[]={ { .uname = "READ", .udesc = "Number of LLC read misses", .ucode = 0x100, }, { .uname = "WRITE", .udesc = "Number of LLC write misses", .ucode = 0x200, }, { .uname = "PROBE", .udesc = "Number of LLC peer probe misses", .ucode = 0x400, }, { .uname = "ANY", .udesc = "Number of LLC misses", .ucode = 0x300, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t wsm_unc_unc_qhl_address_conflicts[]={ { .uname = "2WAY", .udesc = "QHL 2 way address conflicts", .ucode = 0x200, }, { .uname = "3WAY", .udesc = "QHL 3 way address conflicts", .ucode = 0x400, }, }; static const intel_x86_umask_t wsm_unc_unc_qhl_conflict_cycles[]={ { .uname = "IOH", .udesc = "QHL IOH Tracker conflict cycles", .ucode = 0x100, }, { .uname = "REMOTE", .udesc = "QHL Remote Tracker conflict cycles", .ucode = 0x200, }, { .uname = "LOCAL", .udesc = "QHL Local Tracker conflict cycles", .ucode = 0x400, }, }; static const intel_x86_umask_t wsm_unc_unc_qhl_cycles_full[]={ { .uname = "REMOTE", .udesc = "Cycles QHL Remote Tracker is full", .ucode = 0x200, }, { .uname = "LOCAL", .udesc = "Cycles QHL Local Tracker is full", .ucode = 0x400, }, { .uname = "IOH", .udesc = "Cycles QHL IOH Tracker is full", .ucode = 0x100, }, }; static const intel_x86_umask_t wsm_unc_unc_qhl_cycles_not_empty[]={ { .uname = "IOH", .udesc = "Cycles QHL IOH is busy", .ucode = 0x100, }, { .uname = "REMOTE", .udesc = "Cycles QHL Remote Tracker is busy", .ucode = 0x200, }, { .uname = "LOCAL", .udesc = "Cycles QHL Local Tracker is busy", .ucode = 0x400, }, }; static const intel_x86_umask_t wsm_unc_unc_qhl_frc_ack_cnflts[]={ { .uname = "LOCAL", .udesc = "QHL FrcAckCnflts sent to local home", .ucode = 0x400, .uflags= INTEL_X86_DFL, }, }; static const intel_x86_umask_t wsm_unc_unc_qhl_sleeps[]={ { .uname = "IOH_ORDER", .udesc = "Due to IOH ordering (write after read) conflicts", .ucode = 0x100, }, { .uname = "REMOTE_ORDER", .udesc = "Due to remote socket ordering (write after read) conflicts", .ucode = 0x200, }, { .uname = "LOCAL_ORDER", .udesc = "Due to local socket ordering (write after read) conflicts", .ucode = 0x400, }, { .uname = "IOH_CONFLICT", .udesc = "Due to IOH address conflicts", .ucode = 0x800, }, { .uname = "REMOTE_CONFLICT", .udesc = "Due to remote socket address conflicts", .ucode = 0x1000, }, { .uname = "LOCAL_CONFLICT", .udesc = "Due to local socket address conflicts", .ucode = 0x2000, }, }; static const intel_x86_umask_t wsm_unc_unc_qhl_occupancy[]={ { .uname = "IOH", .udesc = "Cycles QHL IOH Tracker Allocate to Deallocate Read Occupancy", .ucode = 0x100, }, { .uname = "REMOTE", .udesc = "Cycles QHL Remote Tracker Allocate to Deallocate Read Occupancy", .ucode = 0x200, }, { .uname = "LOCAL", .udesc = "Cycles QHL Local Tracker Allocate to Deallocate Read Occupancy", .ucode = 0x400, }, }; static const intel_x86_umask_t wsm_unc_unc_qhl_requests[]={ { .uname = "LOCAL_READS", .udesc = "Quickpath Home Logic local read requests", .ucode = 0x1000, }, { .uname = "LOCAL_WRITES", .udesc = "Quickpath Home Logic local write requests", .ucode = 0x2000, }, { .uname = "REMOTE_READS", .udesc = "Quickpath Home Logic remote read requests", .ucode = 0x400, }, { .uname = "IOH_READS", .udesc = "Quickpath Home Logic IOH read requests", .ucode = 0x100, }, { .uname = "IOH_WRITES", .udesc = "Quickpath Home Logic IOH write requests", .ucode = 0x200, }, { .uname = "REMOTE_WRITES", .udesc = "Quickpath Home Logic remote write requests", .ucode = 0x800, }, }; static const intel_x86_umask_t wsm_unc_unc_qmc_busy[]={ { .uname = "READ_CH0", .udesc = "Cycles QMC channel 0 busy with a read request", .ucode = 0x100, }, { .uname = "READ_CH1", .udesc = "Cycles QMC channel 1 busy with a read request", .ucode = 0x200, }, { .uname = "READ_CH2", .udesc = "Cycles QMC channel 2 busy with a read request", .ucode = 0x400, }, { .uname = "WRITE_CH0", .udesc = "Cycles QMC channel 0 busy with a write request", .ucode = 0x800, }, { .uname = "WRITE_CH1", .udesc = "Cycles QMC channel 1 busy with a write request", .ucode = 0x1000, }, { .uname = "WRITE_CH2", .udesc = "Cycles QMC channel 2 busy with a write request", .ucode = 0x2000, }, }; static const intel_x86_umask_t wsm_unc_unc_qmc_cancel[]={ { .uname = "CH0", .udesc = "QMC channel 0 cancels", .ucode = 0x100, }, { .uname = "CH1", .udesc = "QMC channel 1 cancels", .ucode = 0x200, }, { .uname = "CH2", .udesc = "QMC channel 2 cancels", .ucode = 0x400, }, { .uname = "ANY", .udesc = "QMC cancels", .ucode = 0x700, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t wsm_unc_unc_qmc_critical_priority_reads[]={ { .uname = "CH0", .udesc = "QMC channel 0 critical priority read requests", .ucode = 0x100, }, { .uname = "CH1", .udesc = "QMC channel 1 critical priority read requests", .ucode = 0x200, }, { .uname = "CH2", .udesc = "QMC channel 2 critical priority read requests", .ucode = 0x400, }, { .uname = "ANY", .udesc = "QMC critical priority read requests", .ucode = 0x700, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t wsm_unc_unc_qmc_high_priority_reads[]={ { .uname = "CH0", .udesc = "QMC channel 0 high priority read requests", .ucode = 0x100, }, { .uname = "CH1", .udesc = "QMC channel 1 high priority read requests", .ucode = 0x200, }, { .uname = "CH2", .udesc = "QMC channel 2 high priority read requests", .ucode = 0x400, }, { .uname = "ANY", .udesc = "QMC high priority read requests", .ucode = 0x700, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t wsm_unc_unc_qmc_isoc_full[]={ { .uname = "READ_CH0", .udesc = "Cycles DRAM channel 0 full with isochronous read requests", .ucode = 0x100, }, { .uname = "READ_CH1", .udesc = "Cycles DRAM channel 1 full with isochronous read requests", .ucode = 0x200, }, { .uname = "READ_CH2", .udesc = "Cycles DRAM channel 2 full with isochronous read requests", .ucode = 0x400, }, { .uname = "WRITE_CH0", .udesc = "Cycles DRAM channel 0 full with isochronous write requests", .ucode = 0x800, }, { .uname = "WRITE_CH1", .udesc = "Cycles DRAM channel 1 full with isochronous write requests", .ucode = 0x1000, }, { .uname = "WRITE_CH2", .udesc = "Cycles DRAM channel 2 full with isochronous write requests", .ucode = 0x2000, }, }; static const intel_x86_umask_t wsm_unc_unc_imc_isoc_occupancy[]={ { .uname = "CH0", .udesc = "IMC channel 0 isochronous read request occupancy", .ucode = 0x100, }, { .uname = "CH1", .udesc = "IMC channel 1 isochronous read request occupancy", .ucode = 0x200, }, { .uname = "CH2", .udesc = "IMC channel 2 isochronous read request occupancy", .ucode = 0x400, }, { .uname = "ANY", .udesc = "IMC isochronous read request occupancy", .ucode = 0x700, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t wsm_unc_unc_qmc_normal_reads[]={ { .uname = "CH0", .udesc = "QMC channel 0 normal read requests", .ucode = 0x100, }, { .uname = "CH1", .udesc = "QMC channel 1 normal read requests", .ucode = 0x200, }, { .uname = "CH2", .udesc = "QMC channel 2 normal read requests", .ucode = 0x400, }, { .uname = "ANY", .udesc = "QMC normal read requests", .ucode = 0x700, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t wsm_unc_unc_qmc_occupancy[]={ { .uname = "CH0", .udesc = "IMC channel 0 normal read request occupancy", .ucode = 0x100, }, { .uname = "CH1", .udesc = "IMC channel 1 normal read request occupancy", .ucode = 0x200, }, { .uname = "CH2", .udesc = "IMC channel 2 normal read request occupancy", .ucode = 0x400, }, }; static const intel_x86_umask_t wsm_unc_unc_qmc_priority_updates[]={ { .uname = "CH0", .udesc = "QMC channel 0 priority updates", .ucode = 0x100, }, { .uname = "CH1", .udesc = "QMC channel 1 priority updates", .ucode = 0x200, }, { .uname = "CH2", .udesc = "QMC channel 2 priority updates", .ucode = 0x400, }, { .uname = "ANY", .udesc = "QMC priority updates", .ucode = 0x700, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t wsm_unc_unc_imc_retry[]={ { .uname = "CH0", .udesc = "Channel 0", .ucode = 0x100, }, { .uname = "CH1", .udesc = "Channel 1", .ucode = 0x200, }, { .uname = "CH2", .udesc = "Channel 2", .ucode = 0x400, }, { .uname = "ANY", .udesc = "Any channel", .ucode = 0x700, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t wsm_unc_unc_qmc_writes[]={ { .uname = "FULL_CH0", .udesc = "QMC channel 0 full cache line writes", .ucode = 0x100, .grpid = 0, }, { .uname = "FULL_CH1", .udesc = "QMC channel 1 full cache line writes", .ucode = 0x200, .grpid = 0, }, { .uname = "FULL_CH2", .udesc = "QMC channel 2 full cache line writes", .ucode = 0x400, .grpid = 0, }, { .uname = "FULL_ANY", .udesc = "QMC full cache line writes", .ucode = 0x700, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, .grpid = 0, }, { .uname = "PARTIAL_CH0", .udesc = "QMC channel 0 partial cache line writes", .ucode = 0x800, .grpid = 1, }, { .uname = "PARTIAL_CH1", .udesc = "QMC channel 1 partial cache line writes", .ucode = 0x1000, .grpid = 1, }, { .uname = "PARTIAL_CH2", .udesc = "QMC channel 2 partial cache line writes", .ucode = 0x2000, .grpid = 1, }, { .uname = "PARTIAL_ANY", .udesc = "QMC partial cache line writes", .ucode = 0x3800, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, .grpid = 1, }, }; static const intel_x86_umask_t wsm_unc_unc_qpi_rx_no_ppt_credit[]={ { .uname = "STALLS_LINK_0", .udesc = "Link 0 snoop stalls due to no PPT entry", .ucode = 0x100, }, { .uname = "STALLS_LINK_1", .udesc = "Link 1 snoop stalls due to no PPT entry", .ucode = 0x200, }, }; static const intel_x86_umask_t wsm_unc_unc_qpi_tx_header[]={ { .uname = "BUSY_LINK_0", .udesc = "Cycles link 0 outbound header busy", .ucode = 0x200, }, { .uname = "BUSY_LINK_1", .udesc = "Cycles link 1 outbound header busy", .ucode = 0x800, }, }; static const intel_x86_umask_t wsm_unc_unc_qpi_tx_stalled_multi_flit[]={ { .uname = "DRS_LINK_0", .udesc = "Cycles QPI outbound link 0 DRS stalled", .ucode = 0x100, }, { .uname = "NCB_LINK_0", .udesc = "Cycles QPI outbound link 0 NCB stalled", .ucode = 0x200, }, { .uname = "NCS_LINK_0", .udesc = "Cycles QPI outbound link 0 NCS stalled", .ucode = 0x400, }, { .uname = "DRS_LINK_1", .udesc = "Cycles QPI outbound link 1 DRS stalled", .ucode = 0x800, }, { .uname = "NCB_LINK_1", .udesc = "Cycles QPI outbound link 1 NCB stalled", .ucode = 0x1000, }, { .uname = "NCS_LINK_1", .udesc = "Cycles QPI outbound link 1 NCS stalled", .ucode = 0x2000, }, { .uname = "LINK_0", .udesc = "Cycles QPI outbound link 0 multi flit stalled", .ucode = 0x700, .uflags= INTEL_X86_NCOMBO, }, { .uname = "LINK_1", .udesc = "Cycles QPI outbound link 1 multi flit stalled", .ucode = 0x3800, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t wsm_unc_unc_qpi_tx_stalled_single_flit[]={ { .uname = "HOME_LINK_0", .udesc = "Cycles QPI outbound link 0 HOME stalled", .ucode = 0x100, }, { .uname = "SNOOP_LINK_0", .udesc = "Cycles QPI outbound link 0 SNOOP stalled", .ucode = 0x200, }, { .uname = "NDR_LINK_0", .udesc = "Cycles QPI outbound link 0 NDR stalled", .ucode = 0x400, }, { .uname = "HOME_LINK_1", .udesc = "Cycles QPI outbound link 1 HOME stalled", .ucode = 0x800, }, { .uname = "SNOOP_LINK_1", .udesc = "Cycles QPI outbound link 1 SNOOP stalled", .ucode = 0x1000, }, { .uname = "NDR_LINK_1", .udesc = "Cycles QPI outbound link 1 NDR stalled", .ucode = 0x2000, }, { .uname = "LINK_0", .udesc = "Cycles QPI outbound link 0 single flit stalled", .ucode = 0x700, .uflags= INTEL_X86_NCOMBO, }, { .uname = "LINK_1", .udesc = "Cycles QPI outbound link 1 single flit stalled", .ucode = 0x3800, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t wsm_unc_unc_snp_resp_to_local_home[]={ { .uname = "I_STATE", .udesc = "Local home snoop response - LLC does not have cache line", .ucode = 0x100, }, { .uname = "S_STATE", .udesc = "Local home snoop response - LLC has cache line in S state", .ucode = 0x200, }, { .uname = "FWD_S_STATE", .udesc = "Local home snoop response - LLC forwarding cache line in S state.", .ucode = 0x400, }, { .uname = "FWD_I_STATE", .udesc = "Local home snoop response - LLC has forwarded a modified cache line", .ucode = 0x800, }, { .uname = "CONFLICT", .udesc = "Local home conflict snoop response", .ucode = 0x1000, }, { .uname = "WB", .udesc = "Local home snoop response - LLC has cache line in the M state", .ucode = 0x2000, }, }; static const intel_x86_umask_t wsm_unc_unc_snp_resp_to_remote_home[]={ { .uname = "I_STATE", .udesc = "Remote home snoop response - LLC does not have cache line", .ucode = 0x100, }, { .uname = "S_STATE", .udesc = "Remote home snoop response - LLC has cache line in S state", .ucode = 0x200, }, { .uname = "FWD_S_STATE", .udesc = "Remote home snoop response - LLC forwarding cache line in S state.", .ucode = 0x400, }, { .uname = "FWD_I_STATE", .udesc = "Remote home snoop response - LLC has forwarded a modified cache line", .ucode = 0x800, }, { .uname = "CONFLICT", .udesc = "Remote home conflict snoop response", .ucode = 0x1000, }, { .uname = "WB", .udesc = "Remote home snoop response - LLC has cache line in the M state", .ucode = 0x2000, }, { .uname = "HITM", .udesc = "Remote home snoop response - LLC HITM", .ucode = 0x2400, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t wsm_unc_unc_thermal_throttling_temp[]={ { .uname = "CORE_0", .udesc = "Core 0", .ucode = 0x100, }, { .uname = "CORE_1", .udesc = "Core 1", .ucode = 0x200, }, { .uname = "CORE_2", .udesc = "Core 2", .ucode = 0x400, }, { .uname = "CORE_3", .udesc = "Core 3", .ucode = 0x800, }, }; static const intel_x86_entry_t intel_wsm_unc_pe[]={ { .name = "UNC_CLK_UNHALTED", .desc = "Uncore clockticks.", .modmsk =0x0, .cntmsk = 0x100000, .code = 0xff, .flags = INTEL_X86_FIXED, }, { .name = "UNC_DRAM_OPEN", .desc = "DRAM open commands issued for read or write", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x60, .numasks = LIBPFM_ARRAY_SIZE(wsm_unc_unc_dram_open), .ngrp = 1, .umasks = wsm_unc_unc_dram_open, }, { .name = "UNC_GC_OCCUPANCY", .desc = "Number of queue entries", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x2, .numasks = LIBPFM_ARRAY_SIZE(wsm_unc_unc_gc_occupancy), .ngrp = 1, .umasks = wsm_unc_unc_gc_occupancy, }, { .name = "UNC_DRAM_PAGE_CLOSE", .desc = "DRAM page close due to idle timer expiration", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x61, .numasks = LIBPFM_ARRAY_SIZE(wsm_unc_unc_dram_page_close), .ngrp = 1, .umasks = wsm_unc_unc_dram_page_close, }, { .name = "UNC_DRAM_PAGE_MISS", .desc = "DRAM Channel 0 page miss", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x62, .numasks = LIBPFM_ARRAY_SIZE(wsm_unc_unc_dram_page_miss), .ngrp = 1, .umasks = wsm_unc_unc_dram_page_miss, }, { .name = "UNC_DRAM_PRE_ALL", .desc = "DRAM Channel 0 precharge all commands", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x66, .numasks = LIBPFM_ARRAY_SIZE(wsm_unc_unc_dram_pre_all), .ngrp = 1, .umasks = wsm_unc_unc_dram_pre_all, }, { .name = "UNC_DRAM_THERMAL_THROTTLED", .desc = "Uncore cycles DRAM was throttled due to its temperature being above thermal throttling threshold", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x67, }, { .name = "UNC_DRAM_READ_CAS", .desc = "DRAM Channel 0 read CAS commands", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x63, .numasks = LIBPFM_ARRAY_SIZE(wsm_unc_unc_dram_read_cas), .ngrp = 1, .umasks = wsm_unc_unc_dram_read_cas, }, { .name = "UNC_DRAM_REFRESH", .desc = "DRAM Channel 0 refresh commands", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x65, .numasks = LIBPFM_ARRAY_SIZE(wsm_unc_unc_dram_refresh), .ngrp = 1, .umasks = wsm_unc_unc_dram_refresh, }, { .name = "UNC_DRAM_WRITE_CAS", .desc = "DRAM Channel 0 write CAS commands", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x64, .numasks = LIBPFM_ARRAY_SIZE(wsm_unc_unc_dram_write_cas), .ngrp = 1, .umasks = wsm_unc_unc_dram_write_cas, }, { .name = "UNC_GQ_ALLOC", .desc = "GQ read tracker requests", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x3, .numasks = LIBPFM_ARRAY_SIZE(wsm_unc_unc_gq_alloc), .ngrp = 1, .umasks = wsm_unc_unc_gq_alloc, }, { .name = "UNC_GQ_CYCLES_FULL", .desc = "Cycles GQ read tracker is full.", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x0, .numasks = LIBPFM_ARRAY_SIZE(wsm_unc_unc_gq_cycles_full), .ngrp = 1, .umasks = wsm_unc_unc_gq_cycles_full, }, { .name = "UNC_GQ_CYCLES_NOT_EMPTY", .desc = "Cycles GQ read tracker is busy", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x1, .numasks = LIBPFM_ARRAY_SIZE(wsm_unc_unc_gq_cycles_not_empty), .ngrp = 1, .umasks = wsm_unc_unc_gq_cycles_not_empty, }, { .name = "UNC_GQ_DATA_FROM", .desc = "Cycles GQ data is imported", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x4, .numasks = LIBPFM_ARRAY_SIZE(wsm_unc_unc_gq_data_from), .ngrp = 1, .umasks = wsm_unc_unc_gq_data_from, }, { .name = "UNC_GQ_DATA_TO", .desc = "Cycles GQ data is exported", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x5, .numasks = LIBPFM_ARRAY_SIZE(wsm_unc_unc_gq_data_to), .ngrp = 1, .umasks = wsm_unc_unc_gq_data_to, }, { .name = "UNC_LLC_HITS", .desc = "Number of LLC read hits", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x8, .numasks = LIBPFM_ARRAY_SIZE(wsm_unc_unc_llc_hits), .ngrp = 1, .umasks = wsm_unc_unc_llc_hits, }, { .name = "UNC_LLC_LINES_IN", .desc = "LLC lines allocated in M state", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0xa, .numasks = LIBPFM_ARRAY_SIZE(wsm_unc_unc_llc_lines_in), .ngrp = 1, .umasks = wsm_unc_unc_llc_lines_in, }, { .name = "UNC_LLC_LINES_OUT", .desc = "LLC lines victimized in M state", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0xb, .numasks = LIBPFM_ARRAY_SIZE(wsm_unc_unc_llc_lines_out), .ngrp = 1, .umasks = wsm_unc_unc_llc_lines_out, }, { .name = "UNC_LLC_MISS", .desc = "Number of LLC read misses", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x9, .numasks = LIBPFM_ARRAY_SIZE(wsm_unc_unc_llc_miss), .ngrp = 1, .umasks = wsm_unc_unc_llc_miss, }, { .name = "UNC_QHL_ADDRESS_CONFLICTS", .desc = "QHL 2 way address conflicts", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x24, .numasks = LIBPFM_ARRAY_SIZE(wsm_unc_unc_qhl_address_conflicts), .ngrp = 1, .umasks = wsm_unc_unc_qhl_address_conflicts, }, { .name = "UNC_QHL_CONFLICT_CYCLES", .desc = "QHL IOH Tracker conflict cycles", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x25, .numasks = LIBPFM_ARRAY_SIZE(wsm_unc_unc_qhl_conflict_cycles), .ngrp = 1, .umasks = wsm_unc_unc_qhl_conflict_cycles, }, { .name = "UNC_QHL_CYCLES_FULL", .desc = "Cycles QHL Remote Tracker is full", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x21, .numasks = LIBPFM_ARRAY_SIZE(wsm_unc_unc_qhl_cycles_full), .ngrp = 1, .umasks = wsm_unc_unc_qhl_cycles_full, }, { .name = "UNC_QHL_CYCLES_NOT_EMPTY", .desc = "Cycles QHL Tracker is not empty", .modmsk =0x0, .cntmsk = 0x1fe00000, .code = 0x22, .numasks = LIBPFM_ARRAY_SIZE(wsm_unc_unc_qhl_cycles_not_empty), .ngrp = 1, .umasks = wsm_unc_unc_qhl_cycles_not_empty, }, { .name = "UNC_QHL_FRC_ACK_CNFLTS", .desc = "QHL FrcAckCnflts sent to local home", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x33, .numasks = LIBPFM_ARRAY_SIZE(wsm_unc_unc_qhl_frc_ack_cnflts), .ngrp = 1, .umasks = wsm_unc_unc_qhl_frc_ack_cnflts, }, { .name = "UNC_QHL_SLEEPS", .desc = "Number of occurrences a request was put to sleep", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x34, .numasks = LIBPFM_ARRAY_SIZE(wsm_unc_unc_qhl_sleeps), .ngrp = 1, .umasks = wsm_unc_unc_qhl_sleeps, }, { .name = "UNC_QHL_OCCUPANCY", .desc = "Cycles QHL Tracker Allocate to Deallocate Read Occupancy", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x23, .numasks = LIBPFM_ARRAY_SIZE(wsm_unc_unc_qhl_occupancy), .ngrp = 1, .umasks = wsm_unc_unc_qhl_occupancy, }, { .name = "UNC_QHL_REQUESTS", .desc = "Quickpath Home Logic local read requests", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x20, .numasks = LIBPFM_ARRAY_SIZE(wsm_unc_unc_qhl_requests), .ngrp = 1, .umasks = wsm_unc_unc_qhl_requests, }, { .name = "UNC_QHL_TO_QMC_BYPASS", .desc = "Number of requests to QMC that bypass QHL", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x26, }, { .name = "UNC_QMC_BUSY", .desc = "Cycles QMC busy with a read request", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x29, .numasks = LIBPFM_ARRAY_SIZE(wsm_unc_unc_qmc_busy), .ngrp = 1, .umasks = wsm_unc_unc_qmc_busy, }, { .name = "UNC_QMC_CANCEL", .desc = "QMC cancels", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x30, .numasks = LIBPFM_ARRAY_SIZE(wsm_unc_unc_qmc_cancel), .ngrp = 1, .umasks = wsm_unc_unc_qmc_cancel, }, { .name = "UNC_QMC_CRITICAL_PRIORITY_READS", .desc = "QMC critical priority read requests", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x2e, .numasks = LIBPFM_ARRAY_SIZE(wsm_unc_unc_qmc_critical_priority_reads), .ngrp = 1, .umasks = wsm_unc_unc_qmc_critical_priority_reads, }, { .name = "UNC_QMC_HIGH_PRIORITY_READS", .desc = "QMC high priority read requests", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x2d, .numasks = LIBPFM_ARRAY_SIZE(wsm_unc_unc_qmc_high_priority_reads), .ngrp = 1, .umasks = wsm_unc_unc_qmc_high_priority_reads, }, { .name = "UNC_QMC_ISOC_FULL", .desc = "Cycles DRAM full with isochronous (ISOC) read requests", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x28, .numasks = LIBPFM_ARRAY_SIZE(wsm_unc_unc_qmc_isoc_full), .ngrp = 1, .umasks = wsm_unc_unc_qmc_isoc_full, }, { .name = "UNC_IMC_ISOC_OCCUPANCY", .desc = "IMC isochronous (ISOC) Read Occupancy", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x2b, .numasks = LIBPFM_ARRAY_SIZE(wsm_unc_unc_imc_isoc_occupancy), .ngrp = 1, .umasks = wsm_unc_unc_imc_isoc_occupancy, }, { .name = "UNC_QMC_NORMAL_READS", .desc = "QMC normal read requests", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x2c, .numasks = LIBPFM_ARRAY_SIZE(wsm_unc_unc_qmc_normal_reads), .ngrp = 1, .umasks = wsm_unc_unc_qmc_normal_reads, }, { .name = "UNC_QMC_OCCUPANCY", .desc = "QMC Occupancy", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x2a, .numasks = LIBPFM_ARRAY_SIZE(wsm_unc_unc_qmc_occupancy), .ngrp = 1, .umasks = wsm_unc_unc_qmc_occupancy, }, { .name = "UNC_QMC_PRIORITY_UPDATES", .desc = "QMC priority updates", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x31, .numasks = LIBPFM_ARRAY_SIZE(wsm_unc_unc_qmc_priority_updates), .ngrp = 1, .umasks = wsm_unc_unc_qmc_priority_updates, }, { .name = "UNC_IMC_RETRY", .desc = "Number of IMC DRAM channel retries (retries occur in RAS mode only)", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x32, .numasks = LIBPFM_ARRAY_SIZE(wsm_unc_unc_imc_retry), .ngrp = 1, .umasks = wsm_unc_unc_imc_retry, }, { .name = "UNC_QMC_WRITES", .desc = "QMC cache line writes", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x2f, .flags= INTEL_X86_GRP_EXCL, .numasks = LIBPFM_ARRAY_SIZE(wsm_unc_unc_qmc_writes), .ngrp = 2, .umasks = wsm_unc_unc_qmc_writes, }, { .name = "UNC_QPI_RX_NO_PPT_CREDIT", .desc = "Link 0 snoop stalls due to no PPT entry", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x43, .numasks = LIBPFM_ARRAY_SIZE(wsm_unc_unc_qpi_rx_no_ppt_credit), .ngrp = 1, .umasks = wsm_unc_unc_qpi_rx_no_ppt_credit, }, { .name = "UNC_QPI_TX_HEADER", .desc = "Cycles link 0 outbound header busy", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x42, .numasks = LIBPFM_ARRAY_SIZE(wsm_unc_unc_qpi_tx_header), .ngrp = 1, .umasks = wsm_unc_unc_qpi_tx_header, }, { .name = "UNC_QPI_TX_STALLED_MULTI_FLIT", .desc = "Cycles QPI outbound stalls", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x41, .numasks = LIBPFM_ARRAY_SIZE(wsm_unc_unc_qpi_tx_stalled_multi_flit), .ngrp = 1, .umasks = wsm_unc_unc_qpi_tx_stalled_multi_flit, }, { .name = "UNC_QPI_TX_STALLED_SINGLE_FLIT", .desc = "Cycles QPI outbound link stalls", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x40, .numasks = LIBPFM_ARRAY_SIZE(wsm_unc_unc_qpi_tx_stalled_single_flit), .ngrp = 1, .umasks = wsm_unc_unc_qpi_tx_stalled_single_flit, }, { .name = "UNC_SNP_RESP_TO_LOCAL_HOME", .desc = "Local home snoop response", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x6, .numasks = LIBPFM_ARRAY_SIZE(wsm_unc_unc_snp_resp_to_local_home), .ngrp = 1, .umasks = wsm_unc_unc_snp_resp_to_local_home, }, { .name = "UNC_SNP_RESP_TO_REMOTE_HOME", .desc = "Remote home snoop response", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x7, .numasks = LIBPFM_ARRAY_SIZE(wsm_unc_unc_snp_resp_to_remote_home), .ngrp = 1, .umasks = wsm_unc_unc_snp_resp_to_remote_home, }, { .name = "UNC_THERMAL_THROTTLING_TEMP", .desc = "Uncore cycles that the PCU records core temperature above threshold", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x80, .numasks = LIBPFM_ARRAY_SIZE(wsm_unc_unc_thermal_throttling_temp), .ngrp = 1, .umasks = wsm_unc_unc_thermal_throttling_temp, }, { .name = "UNC_THERMAL_THROTTLED_TEMP", .desc = "Uncore cycles that the PCU records that core is in power throttled state due to temperature being above threshold", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x81, .numasks = LIBPFM_ARRAY_SIZE(wsm_unc_unc_thermal_throttling_temp), .ngrp = 1, .umasks = wsm_unc_unc_thermal_throttling_temp, /* identical to actual umasks list for this event */ }, { .name = "UNC_PROCHOT_ASSERTION", .desc = "Number of system assertions of PROCHOT indicating the entire processor has exceeded the thermal limit", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x82, }, { .name = "UNC_THERMAL_THROTTLING_PROCHOT", .desc = "Uncore cycles that the PCU records that core is in power throttled state due PROCHOT assertions", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x83, .numasks = LIBPFM_ARRAY_SIZE(wsm_unc_unc_thermal_throttling_temp), .ngrp = 1, .umasks = wsm_unc_unc_thermal_throttling_temp, /* identical to actual umasks list for this event */ }, { .name = "UNC_TURBO_MODE", .desc = "Uncore cycles that a core is operating in turbo mode", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x84, .numasks = LIBPFM_ARRAY_SIZE(wsm_unc_unc_thermal_throttling_temp), .ngrp = 1, .umasks = wsm_unc_unc_thermal_throttling_temp, /* identical to actual umasks list for this event */ }, { .name = "UNC_CYCLES_UNHALTED_L3_FLL_ENABLE", .desc = "Uncore cycles where at least one core is unhalted and all L3 ways are enabled", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x85, }, { .name = "UNC_CYCLES_UNHALTED_L3_FLL_DISABLE", .desc = "Uncore cycles where at least one core is unhalted and all L3 ways are disabled", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x86, }, }; libpfm-4.9.0/lib/events/itanium_events.h0000664000175000017500000006674113223402656020111 0ustar eranianeranian/* * Copyright (c) 2001-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux/ia64. */ /* * This file is generated automatically * !! DO NOT CHANGE !! */ /* * Events table for the Itanium PMU family */ static pme_ita_entry_t itanium_pe []={ #define PME_ITA_ALAT_INST_CHKA_LDC_ALL 0 { "ALAT_INST_CHKA_LDC_ALL", {0x30036} , 0xf0, 2, {0xffff0003}, NULL}, #define PME_ITA_ALAT_INST_CHKA_LDC_FP 1 { "ALAT_INST_CHKA_LDC_FP", {0x10036} , 0xf0, 2, {0xffff0003}, NULL}, #define PME_ITA_ALAT_INST_CHKA_LDC_INT 2 { "ALAT_INST_CHKA_LDC_INT", {0x20036} , 0xf0, 2, {0xffff0003}, NULL}, #define PME_ITA_ALAT_INST_FAILED_CHKA_LDC_ALL 3 { "ALAT_INST_FAILED_CHKA_LDC_ALL", {0x30037} , 0xf0, 2, {0xffff0003}, NULL}, #define PME_ITA_ALAT_INST_FAILED_CHKA_LDC_FP 4 { "ALAT_INST_FAILED_CHKA_LDC_FP", {0x10037} , 0xf0, 2, {0xffff0003}, NULL}, #define PME_ITA_ALAT_INST_FAILED_CHKA_LDC_INT 5 { "ALAT_INST_FAILED_CHKA_LDC_INT", {0x20037} , 0xf0, 2, {0xffff0003}, NULL}, #define PME_ITA_ALAT_REPLACEMENT_ALL 6 { "ALAT_REPLACEMENT_ALL", {0x30038} , 0xf0, 2, {0xffff0007}, NULL}, #define PME_ITA_ALAT_REPLACEMENT_FP 7 { "ALAT_REPLACEMENT_FP", {0x10038} , 0xf0, 2, {0xffff0007}, NULL}, #define PME_ITA_ALAT_REPLACEMENT_INT 8 { "ALAT_REPLACEMENT_INT", {0x20038} , 0xf0, 2, {0xffff0007}, NULL}, #define PME_ITA_ALL_STOPS_DISPERSED 9 { "ALL_STOPS_DISPERSED", {0x2f} , 0xf0, 1, {0xffff0001}, NULL}, #define PME_ITA_BRANCH_EVENT 10 { "BRANCH_EVENT", {0x811} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_MULTIWAY_ALL_PATHS_ALL_PREDICTIONS 11 { "BRANCH_MULTIWAY_ALL_PATHS_ALL_PREDICTIONS", {0xe} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_MULTIWAY_ALL_PATHS_CORRECT_PREDICTIONS 12 { "BRANCH_MULTIWAY_ALL_PATHS_CORRECT_PREDICTIONS", {0x1000e} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_MULTIWAY_ALL_PATHS_WRONG_PATH 13 { "BRANCH_MULTIWAY_ALL_PATHS_WRONG_PATH", {0x2000e} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_MULTIWAY_ALL_PATHS_WRONG_TARGET 14 { "BRANCH_MULTIWAY_ALL_PATHS_WRONG_TARGET", {0x3000e} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_MULTIWAY_NOT_TAKEN_ALL_PREDICTIONS 15 { "BRANCH_MULTIWAY_NOT_TAKEN_ALL_PREDICTIONS", {0x8000e} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_MULTIWAY_NOT_TAKEN_CORRECT_PREDICTIONS 16 { "BRANCH_MULTIWAY_NOT_TAKEN_CORRECT_PREDICTIONS", {0x9000e} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_MULTIWAY_NOT_TAKEN_WRONG_PATH 17 { "BRANCH_MULTIWAY_NOT_TAKEN_WRONG_PATH", {0xa000e} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_MULTIWAY_NOT_TAKEN_WRONG_TARGET 18 { "BRANCH_MULTIWAY_NOT_TAKEN_WRONG_TARGET", {0xb000e} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_MULTIWAY_TAKEN_ALL_PREDICTIONS 19 { "BRANCH_MULTIWAY_TAKEN_ALL_PREDICTIONS", {0xc000e} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_MULTIWAY_TAKEN_CORRECT_PREDICTIONS 20 { "BRANCH_MULTIWAY_TAKEN_CORRECT_PREDICTIONS", {0xd000e} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_MULTIWAY_TAKEN_WRONG_PATH 21 { "BRANCH_MULTIWAY_TAKEN_WRONG_PATH", {0xe000e} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_MULTIWAY_TAKEN_WRONG_TARGET 22 { "BRANCH_MULTIWAY_TAKEN_WRONG_TARGET", {0xf000e} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_NOT_TAKEN 23 { "BRANCH_NOT_TAKEN", {0x8000d} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_PATH_1ST_STAGE_NT_OUTCOMES_CORRECTLY_PREDICTED 24 { "BRANCH_PATH_1ST_STAGE_NT_OUTCOMES_CORRECTLY_PREDICTED", {0x6000f} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_PATH_1ST_STAGE_NT_OUTCOMES_INCORRECTLY_PREDICTED 25 { "BRANCH_PATH_1ST_STAGE_NT_OUTCOMES_INCORRECTLY_PREDICTED", {0x4000f} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_PATH_1ST_STAGE_TK_OUTCOMES_CORRECTLY_PREDICTED 26 { "BRANCH_PATH_1ST_STAGE_TK_OUTCOMES_CORRECTLY_PREDICTED", {0x7000f} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_PATH_1ST_STAGE_TK_OUTCOMES_INCORRECTLY_PREDICTED 27 { "BRANCH_PATH_1ST_STAGE_TK_OUTCOMES_INCORRECTLY_PREDICTED", {0x5000f} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_PATH_2ND_STAGE_NT_OUTCOMES_CORRECTLY_PREDICTED 28 { "BRANCH_PATH_2ND_STAGE_NT_OUTCOMES_CORRECTLY_PREDICTED", {0xa000f} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_PATH_2ND_STAGE_NT_OUTCOMES_INCORRECTLY_PREDICTED 29 { "BRANCH_PATH_2ND_STAGE_NT_OUTCOMES_INCORRECTLY_PREDICTED", {0x8000f} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_PATH_2ND_STAGE_TK_OUTCOMES_CORRECTLY_PREDICTED 30 { "BRANCH_PATH_2ND_STAGE_TK_OUTCOMES_CORRECTLY_PREDICTED", {0xb000f} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_PATH_2ND_STAGE_TK_OUTCOMES_INCORRECTLY_PREDICTED 31 { "BRANCH_PATH_2ND_STAGE_TK_OUTCOMES_INCORRECTLY_PREDICTED", {0x9000f} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_PATH_3RD_STAGE_NT_OUTCOMES_CORRECTLY_PREDICTED 32 { "BRANCH_PATH_3RD_STAGE_NT_OUTCOMES_CORRECTLY_PREDICTED", {0xe000f} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_PATH_3RD_STAGE_NT_OUTCOMES_INCORRECTLY_PREDICTED 33 { "BRANCH_PATH_3RD_STAGE_NT_OUTCOMES_INCORRECTLY_PREDICTED", {0xc000f} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_PATH_3RD_STAGE_TK_OUTCOMES_CORRECTLY_PREDICTED 34 { "BRANCH_PATH_3RD_STAGE_TK_OUTCOMES_CORRECTLY_PREDICTED", {0xf000f} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_PATH_3RD_STAGE_TK_OUTCOMES_INCORRECTLY_PREDICTED 35 { "BRANCH_PATH_3RD_STAGE_TK_OUTCOMES_INCORRECTLY_PREDICTED", {0xd000f} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_PATH_ALL_NT_OUTCOMES_CORRECTLY_PREDICTED 36 { "BRANCH_PATH_ALL_NT_OUTCOMES_CORRECTLY_PREDICTED", {0x2000f} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_PATH_ALL_NT_OUTCOMES_INCORRECTLY_PREDICTED 37 { "BRANCH_PATH_ALL_NT_OUTCOMES_INCORRECTLY_PREDICTED", {0xf} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_PATH_ALL_TK_OUTCOMES_CORRECTLY_PREDICTED 38 { "BRANCH_PATH_ALL_TK_OUTCOMES_CORRECTLY_PREDICTED", {0x3000f} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_PATH_ALL_TK_OUTCOMES_INCORRECTLY_PREDICTED 39 { "BRANCH_PATH_ALL_TK_OUTCOMES_INCORRECTLY_PREDICTED", {0x1000f} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_PREDICTOR_1ST_STAGE_ALL_PREDICTIONS 40 { "BRANCH_PREDICTOR_1ST_STAGE_ALL_PREDICTIONS", {0x40010} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_PREDICTOR_1ST_STAGE_CORRECT_PREDICTIONS 41 { "BRANCH_PREDICTOR_1ST_STAGE_CORRECT_PREDICTIONS", {0x50010} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_PREDICTOR_1ST_STAGE_WRONG_PATH 42 { "BRANCH_PREDICTOR_1ST_STAGE_WRONG_PATH", {0x60010} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_PREDICTOR_1ST_STAGE_WRONG_TARGET 43 { "BRANCH_PREDICTOR_1ST_STAGE_WRONG_TARGET", {0x70010} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_PREDICTOR_2ND_STAGE_ALL_PREDICTIONS 44 { "BRANCH_PREDICTOR_2ND_STAGE_ALL_PREDICTIONS", {0x80010} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_PREDICTOR_2ND_STAGE_CORRECT_PREDICTIONS 45 { "BRANCH_PREDICTOR_2ND_STAGE_CORRECT_PREDICTIONS", {0x90010} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_PREDICTOR_2ND_STAGE_WRONG_PATH 46 { "BRANCH_PREDICTOR_2ND_STAGE_WRONG_PATH", {0xa0010} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_PREDICTOR_2ND_STAGE_WRONG_TARGET 47 { "BRANCH_PREDICTOR_2ND_STAGE_WRONG_TARGET", {0xb0010} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_PREDICTOR_3RD_STAGE_ALL_PREDICTIONS 48 { "BRANCH_PREDICTOR_3RD_STAGE_ALL_PREDICTIONS", {0xc0010} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_PREDICTOR_3RD_STAGE_CORRECT_PREDICTIONS 49 { "BRANCH_PREDICTOR_3RD_STAGE_CORRECT_PREDICTIONS", {0xd0010} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_PREDICTOR_3RD_STAGE_WRONG_PATH 50 { "BRANCH_PREDICTOR_3RD_STAGE_WRONG_PATH", {0xe0010} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_PREDICTOR_3RD_STAGE_WRONG_TARGET 51 { "BRANCH_PREDICTOR_3RD_STAGE_WRONG_TARGET", {0xf0010} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_PREDICTOR_ALL_ALL_PREDICTIONS 52 { "BRANCH_PREDICTOR_ALL_ALL_PREDICTIONS", {0x10} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_PREDICTOR_ALL_CORRECT_PREDICTIONS 53 { "BRANCH_PREDICTOR_ALL_CORRECT_PREDICTIONS", {0x10010} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_PREDICTOR_ALL_WRONG_PATH 54 { "BRANCH_PREDICTOR_ALL_WRONG_PATH", {0x20010} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_PREDICTOR_ALL_WRONG_TARGET 55 { "BRANCH_PREDICTOR_ALL_WRONG_TARGET", {0x30010} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_TAKEN_SLOT_0 56 { "BRANCH_TAKEN_SLOT_0", {0x1000d} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_TAKEN_SLOT_1 57 { "BRANCH_TAKEN_SLOT_1", {0x2000d} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_TAKEN_SLOT_2 58 { "BRANCH_TAKEN_SLOT_2", {0x4000d} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BUS_ALL_ANY 59 { "BUS_ALL_ANY", {0x10047} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_ALL_IO 60 { "BUS_ALL_IO", {0x40047} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_ALL_SELF 61 { "BUS_ALL_SELF", {0x20047} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_BRQ_LIVE_REQ_HI 62 { "BUS_BRQ_LIVE_REQ_HI", {0x5c} , 0xf0, 2, {0xffff0000}, NULL}, #define PME_ITA_BUS_BRQ_LIVE_REQ_LO 63 { "BUS_BRQ_LIVE_REQ_LO", {0x5b} , 0xf0, 2, {0xffff0000}, NULL}, #define PME_ITA_BUS_BRQ_REQ_INSERTED 64 { "BUS_BRQ_REQ_INSERTED", {0x5d} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_BURST_ANY 65 { "BUS_BURST_ANY", {0x10049} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_BURST_IO 66 { "BUS_BURST_IO", {0x40049} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_BURST_SELF 67 { "BUS_BURST_SELF", {0x20049} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_HITM 68 { "BUS_HITM", {0x44} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_IO_ANY 69 { "BUS_IO_ANY", {0x10050} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_IOQ_LIVE_REQ_HI 70 { "BUS_IOQ_LIVE_REQ_HI", {0x58} , 0xf0, 3, {0xffff0000}, NULL}, #define PME_ITA_BUS_IOQ_LIVE_REQ_LO 71 { "BUS_IOQ_LIVE_REQ_LO", {0x57} , 0xf0, 3, {0xffff0000}, NULL}, #define PME_ITA_BUS_IO_SELF 72 { "BUS_IO_SELF", {0x20050} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_LOCK_ANY 73 { "BUS_LOCK_ANY", {0x10053} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_LOCK_CYCLES_ANY 74 { "BUS_LOCK_CYCLES_ANY", {0x10054} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_LOCK_CYCLES_SELF 75 { "BUS_LOCK_CYCLES_SELF", {0x20054} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_LOCK_SELF 76 { "BUS_LOCK_SELF", {0x20053} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_MEMORY_ANY 77 { "BUS_MEMORY_ANY", {0x1004a} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_MEMORY_IO 78 { "BUS_MEMORY_IO", {0x4004a} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_MEMORY_SELF 79 { "BUS_MEMORY_SELF", {0x2004a} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_PARTIAL_ANY 80 { "BUS_PARTIAL_ANY", {0x10048} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_PARTIAL_IO 81 { "BUS_PARTIAL_IO", {0x40048} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_PARTIAL_SELF 82 { "BUS_PARTIAL_SELF", {0x20048} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_RD_ALL_ANY 83 { "BUS_RD_ALL_ANY", {0x1004b} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_RD_ALL_IO 84 { "BUS_RD_ALL_IO", {0x4004b} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_RD_ALL_SELF 85 { "BUS_RD_ALL_SELF", {0x2004b} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_RD_DATA_ANY 86 { "BUS_RD_DATA_ANY", {0x1004c} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_RD_DATA_IO 87 { "BUS_RD_DATA_IO", {0x4004c} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_RD_DATA_SELF 88 { "BUS_RD_DATA_SELF", {0x2004c} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_RD_HIT 89 { "BUS_RD_HIT", {0x40} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_RD_HITM 90 { "BUS_RD_HITM", {0x41} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_RD_INVAL_ANY 91 { "BUS_RD_INVAL_ANY", {0x1004e} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_RD_INVAL_BST_ANY 92 { "BUS_RD_INVAL_BST_ANY", {0x1004f} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_RD_INVAL_BST_HITM 93 { "BUS_RD_INVAL_BST_HITM", {0x43} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_RD_INVAL_BST_IO 94 { "BUS_RD_INVAL_BST_IO", {0x4004f} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_RD_INVAL_BST_SELF 95 { "BUS_RD_INVAL_BST_SELF", {0x2004f} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_RD_INVAL_HITM 96 { "BUS_RD_INVAL_HITM", {0x42} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_RD_INVAL_IO 97 { "BUS_RD_INVAL_IO", {0x4004e} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_RD_INVAL_SELF 98 { "BUS_RD_INVAL_SELF", {0x2004e} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_RD_IO_ANY 99 { "BUS_RD_IO_ANY", {0x10051} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_RD_IO_SELF 100 { "BUS_RD_IO_SELF", {0x20051} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_RD_PRTL_ANY 101 { "BUS_RD_PRTL_ANY", {0x1004d} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_RD_PRTL_IO 102 { "BUS_RD_PRTL_IO", {0x4004d} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_RD_PRTL_SELF 103 { "BUS_RD_PRTL_SELF", {0x2004d} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_SNOOPQ_REQ 104 { "BUS_SNOOPQ_REQ", {0x56} , 0x30, 3, {0xffff0000}, NULL}, #define PME_ITA_BUS_SNOOPS_ANY 105 { "BUS_SNOOPS_ANY", {0x10046} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_SNOOPS_HITM_ANY 106 { "BUS_SNOOPS_HITM_ANY", {0x10045} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_SNOOP_STALL_CYCLES_ANY 107 { "BUS_SNOOP_STALL_CYCLES_ANY", {0x10055} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_SNOOP_STALL_CYCLES_SELF 108 { "BUS_SNOOP_STALL_CYCLES_SELF", {0x20055} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_WR_WB_ANY 109 { "BUS_WR_WB_ANY", {0x10052} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_WR_WB_IO 110 { "BUS_WR_WB_IO", {0x40052} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_WR_WB_SELF 111 { "BUS_WR_WB_SELF", {0x20052} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_CPU_CPL_CHANGES 112 { "CPU_CPL_CHANGES", {0x34} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_CPU_CYCLES 113 { "CPU_CYCLES", {0x12} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_DATA_ACCESS_CYCLE 114 { "DATA_ACCESS_CYCLE", {0x3} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_DATA_EAR_CACHE_LAT1024 115 { "DATA_EAR_CACHE_LAT1024", {0x90367} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_DATA_EAR_CACHE_LAT128 116 { "DATA_EAR_CACHE_LAT128", {0x50367} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_DATA_EAR_CACHE_LAT16 117 { "DATA_EAR_CACHE_LAT16", {0x20367} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_DATA_EAR_CACHE_LAT2048 118 { "DATA_EAR_CACHE_LAT2048", {0xa0367} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_DATA_EAR_CACHE_LAT256 119 { "DATA_EAR_CACHE_LAT256", {0x60367} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_DATA_EAR_CACHE_LAT32 120 { "DATA_EAR_CACHE_LAT32", {0x30367} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_DATA_EAR_CACHE_LAT4 121 { "DATA_EAR_CACHE_LAT4", {0x367} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_DATA_EAR_CACHE_LAT512 122 { "DATA_EAR_CACHE_LAT512", {0x80367} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_DATA_EAR_CACHE_LAT64 123 { "DATA_EAR_CACHE_LAT64", {0x40367} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_DATA_EAR_CACHE_LAT8 124 { "DATA_EAR_CACHE_LAT8", {0x10367} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_DATA_EAR_CACHE_LAT_NONE 125 { "DATA_EAR_CACHE_LAT_NONE", {0xf0367} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_DATA_EAR_EVENTS 126 { "DATA_EAR_EVENTS", {0x67} , 0xf0, 1, {0xffff0007}, NULL}, #define PME_ITA_DATA_EAR_TLB_L2 127 { "DATA_EAR_TLB_L2", {0x20767} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_DATA_EAR_TLB_SW 128 { "DATA_EAR_TLB_SW", {0x80767} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_DATA_EAR_TLB_VHPT 129 { "DATA_EAR_TLB_VHPT", {0x40767} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_DATA_REFERENCES_RETIRED 130 { "DATA_REFERENCES_RETIRED", {0x63} , 0xf0, 2, {0xffff0007}, NULL}, #define PME_ITA_DEPENDENCY_ALL_CYCLE 131 { "DEPENDENCY_ALL_CYCLE", {0x6} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_DEPENDENCY_SCOREBOARD_CYCLE 132 { "DEPENDENCY_SCOREBOARD_CYCLE", {0x2} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_DTC_MISSES 133 { "DTC_MISSES", {0x60} , 0xf0, 1, {0xffff0007}, NULL}, #define PME_ITA_DTLB_INSERTS_HPW 134 { "DTLB_INSERTS_HPW", {0x62} , 0xf0, 1, {0xffff0007}, NULL}, #define PME_ITA_DTLB_MISSES 135 { "DTLB_MISSES", {0x61} , 0xf0, 1, {0xffff0007}, NULL}, #define PME_ITA_EXPL_STOPBITS 136 { "EXPL_STOPBITS", {0x2e} , 0xf0, 1, {0xffff0001}, NULL}, #define PME_ITA_FP_FLUSH_TO_ZERO 137 { "FP_FLUSH_TO_ZERO", {0xb} , 0xf0, 2, {0xffff0003}, NULL}, #define PME_ITA_FP_OPS_RETIRED_HI 138 { "FP_OPS_RETIRED_HI", {0xa} , 0xf0, 3, {0xffff0003}, NULL}, #define PME_ITA_FP_OPS_RETIRED_LO 139 { "FP_OPS_RETIRED_LO", {0x9} , 0xf0, 3, {0xffff0003}, NULL}, #define PME_ITA_FP_SIR_FLUSH 140 { "FP_SIR_FLUSH", {0xc} , 0xf0, 2, {0xffff0003}, NULL}, #define PME_ITA_IA32_INST_RETIRED 141 { "IA32_INST_RETIRED", {0x15} , 0xf0, 2, {0xffff0000}, NULL}, #define PME_ITA_IA64_INST_RETIRED 142 { "IA64_INST_RETIRED", {0x8} , 0x30, 6, {0xffff0003}, NULL}, #define PME_ITA_IA64_TAGGED_INST_RETIRED_PMC8 143 { "IA64_TAGGED_INST_RETIRED_PMC8", {0x30008} , 0x30, 6, {0xffff0003}, NULL}, #define PME_ITA_IA64_TAGGED_INST_RETIRED_PMC9 144 { "IA64_TAGGED_INST_RETIRED_PMC9", {0x20008} , 0x30, 6, {0xffff0003}, NULL}, #define PME_ITA_INST_ACCESS_CYCLE 145 { "INST_ACCESS_CYCLE", {0x1} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_INST_DISPERSED 146 { "INST_DISPERSED", {0x2d} , 0x30, 6, {0xffff0001}, NULL}, #define PME_ITA_INST_FAILED_CHKS_RETIRED_ALL 147 { "INST_FAILED_CHKS_RETIRED_ALL", {0x30035} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_INST_FAILED_CHKS_RETIRED_FP 148 { "INST_FAILED_CHKS_RETIRED_FP", {0x20035} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_INST_FAILED_CHKS_RETIRED_INT 149 { "INST_FAILED_CHKS_RETIRED_INT", {0x10035} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_INSTRUCTION_EAR_CACHE_LAT1024 150 { "INSTRUCTION_EAR_CACHE_LAT1024", {0x80123} , 0xf0, 1, {0xffff0001}, NULL}, #define PME_ITA_INSTRUCTION_EAR_CACHE_LAT128 151 { "INSTRUCTION_EAR_CACHE_LAT128", {0x50123} , 0xf0, 1, {0xffff0001}, NULL}, #define PME_ITA_INSTRUCTION_EAR_CACHE_LAT16 152 { "INSTRUCTION_EAR_CACHE_LAT16", {0x20123} , 0xf0, 1, {0xffff0001}, NULL}, #define PME_ITA_INSTRUCTION_EAR_CACHE_LAT2048 153 { "INSTRUCTION_EAR_CACHE_LAT2048", {0x90123} , 0xf0, 1, {0xffff0001}, NULL}, #define PME_ITA_INSTRUCTION_EAR_CACHE_LAT256 154 { "INSTRUCTION_EAR_CACHE_LAT256", {0x60123} , 0xf0, 1, {0xffff0001}, NULL}, #define PME_ITA_INSTRUCTION_EAR_CACHE_LAT32 155 { "INSTRUCTION_EAR_CACHE_LAT32", {0x30123} , 0xf0, 1, {0xffff0001}, NULL}, #define PME_ITA_INSTRUCTION_EAR_CACHE_LAT4096 156 { "INSTRUCTION_EAR_CACHE_LAT4096", {0xa0123} , 0xf0, 1, {0xffff0001}, NULL}, #define PME_ITA_INSTRUCTION_EAR_CACHE_LAT4 157 { "INSTRUCTION_EAR_CACHE_LAT4", {0x123} , 0xf0, 1, {0xffff0001}, NULL}, #define PME_ITA_INSTRUCTION_EAR_CACHE_LAT512 158 { "INSTRUCTION_EAR_CACHE_LAT512", {0x70123} , 0xf0, 1, {0xffff0001}, NULL}, #define PME_ITA_INSTRUCTION_EAR_CACHE_LAT64 159 { "INSTRUCTION_EAR_CACHE_LAT64", {0x40123} , 0xf0, 1, {0xffff0001}, NULL}, #define PME_ITA_INSTRUCTION_EAR_CACHE_LAT8 160 { "INSTRUCTION_EAR_CACHE_LAT8", {0x10123} , 0xf0, 1, {0xffff0001}, NULL}, #define PME_ITA_INSTRUCTION_EAR_CACHE_LAT_NONE 161 { "INSTRUCTION_EAR_CACHE_LAT_NONE", {0xf0123} , 0xf0, 1, {0xffff0001}, NULL}, #define PME_ITA_INSTRUCTION_EAR_EVENTS 162 { "INSTRUCTION_EAR_EVENTS", {0x23} , 0xf0, 1, {0xffff0001}, NULL}, #define PME_ITA_INSTRUCTION_EAR_TLB_SW 163 { "INSTRUCTION_EAR_TLB_SW", {0x80523} , 0xf0, 1, {0xffff0001}, NULL}, #define PME_ITA_INSTRUCTION_EAR_TLB_VHPT 164 { "INSTRUCTION_EAR_TLB_VHPT", {0x40523} , 0xf0, 1, {0xffff0001}, NULL}, #define PME_ITA_ISA_TRANSITIONS 165 { "ISA_TRANSITIONS", {0x14} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_ISB_LINES_IN 166 { "ISB_LINES_IN", {0x26} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_ITLB_INSERTS_HPW 167 { "ITLB_INSERTS_HPW", {0x28} , 0xf0, 1, {0xffff0001}, NULL}, #define PME_ITA_ITLB_MISSES_FETCH 168 { "ITLB_MISSES_FETCH", {0x27} , 0xf0, 1, {0xffff0001}, NULL}, #define PME_ITA_L1D_READ_FORCED_MISSES_RETIRED 169 { "L1D_READ_FORCED_MISSES_RETIRED", {0x6b} , 0xf0, 2, {0xffff0007}, NULL}, #define PME_ITA_L1D_READ_MISSES_RETIRED 170 { "L1D_READ_MISSES_RETIRED", {0x66} , 0xf0, 2, {0xffff0007}, NULL}, #define PME_ITA_L1D_READS_RETIRED 171 { "L1D_READS_RETIRED", {0x64} , 0xf0, 2, {0xffff0007}, NULL}, #define PME_ITA_L1I_DEMAND_READS 172 { "L1I_DEMAND_READS", {0x20} , 0xf0, 1, {0xffff0001}, NULL}, #define PME_ITA_L1I_FILLS 173 { "L1I_FILLS", {0x21} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_L1I_PREFETCH_READS 174 { "L1I_PREFETCH_READS", {0x24} , 0xf0, 1, {0xffff0001}, NULL}, #define PME_ITA_L1_OUTSTANDING_REQ_HI 175 { "L1_OUTSTANDING_REQ_HI", {0x79} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_L1_OUTSTANDING_REQ_LO 176 { "L1_OUTSTANDING_REQ_LO", {0x78} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_L2_DATA_REFERENCES_ALL 177 { "L2_DATA_REFERENCES_ALL", {0x30069} , 0xf0, 2, {0xffff0007}, NULL}, #define PME_ITA_L2_DATA_REFERENCES_READS 178 { "L2_DATA_REFERENCES_READS", {0x10069} , 0xf0, 2, {0xffff0007}, NULL}, #define PME_ITA_L2_DATA_REFERENCES_WRITES 179 { "L2_DATA_REFERENCES_WRITES", {0x20069} , 0xf0, 2, {0xffff0007}, NULL}, #define PME_ITA_L2_FLUSH_DETAILS_ADDR_CONFLICT 180 { "L2_FLUSH_DETAILS_ADDR_CONFLICT", {0x20077} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_L2_FLUSH_DETAILS_ALL 181 { "L2_FLUSH_DETAILS_ALL", {0xf0077} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_L2_FLUSH_DETAILS_BUS_REJECT 182 { "L2_FLUSH_DETAILS_BUS_REJECT", {0x40077} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_L2_FLUSH_DETAILS_FULL_FLUSH 183 { "L2_FLUSH_DETAILS_FULL_FLUSH", {0x80077} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_L2_FLUSH_DETAILS_ST_BUFFER 184 { "L2_FLUSH_DETAILS_ST_BUFFER", {0x10077} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_L2_FLUSHES 185 { "L2_FLUSHES", {0x76} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_L2_INST_DEMAND_READS 186 { "L2_INST_DEMAND_READS", {0x22} , 0xf0, 1, {0xffff0001}, NULL}, #define PME_ITA_L2_INST_PREFETCH_READS 187 { "L2_INST_PREFETCH_READS", {0x25} , 0xf0, 1, {0xffff0001}, NULL}, #define PME_ITA_L2_MISSES 188 { "L2_MISSES", {0x6a} , 0xf0, 2, {0xffff0007}, NULL}, #define PME_ITA_L2_REFERENCES 189 { "L2_REFERENCES", {0x68} , 0xf0, 3, {0xffff0007}, NULL}, #define PME_ITA_L3_LINES_REPLACED 190 { "L3_LINES_REPLACED", {0x7f} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_L3_MISSES 191 { "L3_MISSES", {0x7c} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_L3_READS_ALL_READS_ALL 192 { "L3_READS_ALL_READS_ALL", {0xf007d} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_L3_READS_ALL_READS_HIT 193 { "L3_READS_ALL_READS_HIT", {0xd007d} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_L3_READS_ALL_READS_MISS 194 { "L3_READS_ALL_READS_MISS", {0xe007d} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_L3_READS_DATA_READS_ALL 195 { "L3_READS_DATA_READS_ALL", {0xb007d} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_L3_READS_DATA_READS_HIT 196 { "L3_READS_DATA_READS_HIT", {0x9007d} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_L3_READS_DATA_READS_MISS 197 { "L3_READS_DATA_READS_MISS", {0xa007d} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_L3_READS_INST_READS_ALL 198 { "L3_READS_INST_READS_ALL", {0x7007d} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_L3_READS_INST_READS_HIT 199 { "L3_READS_INST_READS_HIT", {0x5007d} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_L3_READS_INST_READS_MISS 200 { "L3_READS_INST_READS_MISS", {0x6007d} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_L3_REFERENCES 201 { "L3_REFERENCES", {0x7b} , 0xf0, 1, {0xffff0007}, NULL}, #define PME_ITA_L3_WRITES_ALL_WRITES_ALL 202 { "L3_WRITES_ALL_WRITES_ALL", {0xf007e} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_L3_WRITES_ALL_WRITES_HIT 203 { "L3_WRITES_ALL_WRITES_HIT", {0xd007e} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_L3_WRITES_ALL_WRITES_MISS 204 { "L3_WRITES_ALL_WRITES_MISS", {0xe007e} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_L3_WRITES_DATA_WRITES_ALL 205 { "L3_WRITES_DATA_WRITES_ALL", {0x7007e} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_L3_WRITES_DATA_WRITES_HIT 206 { "L3_WRITES_DATA_WRITES_HIT", {0x5007e} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_L3_WRITES_DATA_WRITES_MISS 207 { "L3_WRITES_DATA_WRITES_MISS", {0x6007e} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_L3_WRITES_L2_WRITEBACK_ALL 208 { "L3_WRITES_L2_WRITEBACK_ALL", {0xb007e} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_L3_WRITES_L2_WRITEBACK_HIT 209 { "L3_WRITES_L2_WRITEBACK_HIT", {0x9007e} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_L3_WRITES_L2_WRITEBACK_MISS 210 { "L3_WRITES_L2_WRITEBACK_MISS", {0xa007e} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_LOADS_RETIRED 211 { "LOADS_RETIRED", {0x6c} , 0xf0, 2, {0xffff0007}, NULL}, #define PME_ITA_MEMORY_CYCLE 212 { "MEMORY_CYCLE", {0x7} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_MISALIGNED_LOADS_RETIRED 213 { "MISALIGNED_LOADS_RETIRED", {0x70} , 0xf0, 2, {0xffff0007}, NULL}, #define PME_ITA_MISALIGNED_STORES_RETIRED 214 { "MISALIGNED_STORES_RETIRED", {0x71} , 0xf0, 2, {0xffff0007}, NULL}, #define PME_ITA_NOPS_RETIRED 215 { "NOPS_RETIRED", {0x30} , 0x30, 6, {0xffff0003}, NULL}, #define PME_ITA_PIPELINE_ALL_FLUSH_CYCLE 216 { "PIPELINE_ALL_FLUSH_CYCLE", {0x4} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_PIPELINE_BACKEND_FLUSH_CYCLE 217 { "PIPELINE_BACKEND_FLUSH_CYCLE", {0x0} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_PIPELINE_FLUSH_ALL 218 { "PIPELINE_FLUSH_ALL", {0xf0033} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_PIPELINE_FLUSH_DTC_FLUSH 219 { "PIPELINE_FLUSH_DTC_FLUSH", {0x40033} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_PIPELINE_FLUSH_IEU_FLUSH 220 { "PIPELINE_FLUSH_IEU_FLUSH", {0x80033} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_PIPELINE_FLUSH_L1D_WAYMP_FLUSH 221 { "PIPELINE_FLUSH_L1D_WAYMP_FLUSH", {0x20033} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_PIPELINE_FLUSH_OTHER_FLUSH 222 { "PIPELINE_FLUSH_OTHER_FLUSH", {0x10033} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_PREDICATE_SQUASHED_RETIRED 223 { "PREDICATE_SQUASHED_RETIRED", {0x31} , 0x30, 6, {0xffff0003}, NULL}, #define PME_ITA_RSE_LOADS_RETIRED 224 { "RSE_LOADS_RETIRED", {0x72} , 0xf0, 2, {0xffff0007}, NULL}, #define PME_ITA_RSE_REFERENCES_RETIRED 225 { "RSE_REFERENCES_RETIRED", {0x65} , 0xf0, 2, {0xffff0007}, NULL}, #define PME_ITA_STORES_RETIRED 226 { "STORES_RETIRED", {0x6d} , 0xf0, 2, {0xffff0007}, NULL}, #define PME_ITA_UC_LOADS_RETIRED 227 { "UC_LOADS_RETIRED", {0x6e} , 0xf0, 2, {0xffff0007}, NULL}, #define PME_ITA_UC_STORES_RETIRED 228 { "UC_STORES_RETIRED", {0x6f} , 0xf0, 2, {0xffff0007}, NULL}, #define PME_ITA_UNSTALLED_BACKEND_CYCLE 229 { "UNSTALLED_BACKEND_CYCLE", {0x5} , 0xf0, 1, {0xffff0000}, NULL}}; #define PME_ITA_EVENT_COUNT 230 libpfm-4.9.0/lib/events/power4_events.h0000664000175000017500000024170613223402656017657 0ustar eranianeranian/****************************/ /* THIS IS OPEN SOURCE CODE */ /****************************/ #ifndef __POWER4_EVENTS_H__ #define __POWER4_EVENTS_H__ /* * File: power4_events.h * CVS: * Author: Corey Ashford * cjashfor@us.ibm.com * Mods: * * * (C) Copyright IBM Corporation, 2009. All Rights Reserved. * Contributed by Corey Ashford * * Note: This code was automatically generated and should not be modified by * hand. * */ #define POWER4_PME_PM_MRK_LSU_SRQ_INST_VALID 0 #define POWER4_PME_PM_FPU1_SINGLE 1 #define POWER4_PME_PM_DC_PREF_OUT_STREAMS 2 #define POWER4_PME_PM_FPU0_STALL3 3 #define POWER4_PME_PM_TB_BIT_TRANS 4 #define POWER4_PME_PM_GPR_MAP_FULL_CYC 5 #define POWER4_PME_PM_MRK_ST_CMPL 6 #define POWER4_PME_PM_MRK_LSU_FLUSH_LRQ 7 #define POWER4_PME_PM_FPU0_STF 8 #define POWER4_PME_PM_FPU1_FMA 9 #define POWER4_PME_PM_L2SA_MOD_TAG 10 #define POWER4_PME_PM_MRK_DATA_FROM_L275_SHR 11 #define POWER4_PME_PM_1INST_CLB_CYC 12 #define POWER4_PME_PM_LSU1_FLUSH_ULD 13 #define POWER4_PME_PM_MRK_INST_FIN 14 #define POWER4_PME_PM_MRK_LSU0_FLUSH_UST 15 #define POWER4_PME_PM_FPU_FDIV 16 #define POWER4_PME_PM_LSU_LRQ_S0_ALLOC 17 #define POWER4_PME_PM_FPU0_FULL_CYC 18 #define POWER4_PME_PM_FPU_SINGLE 19 #define POWER4_PME_PM_FPU0_FMA 20 #define POWER4_PME_PM_MRK_LSU1_FLUSH_ULD 21 #define POWER4_PME_PM_LSU1_FLUSH_LRQ 22 #define POWER4_PME_PM_L2SA_ST_HIT 23 #define POWER4_PME_PM_L2SB_SHR_INV 24 #define POWER4_PME_PM_DTLB_MISS 25 #define POWER4_PME_PM_MRK_ST_MISS_L1 26 #define POWER4_PME_PM_EXT_INT 27 #define POWER4_PME_PM_MRK_LSU1_FLUSH_LRQ 28 #define POWER4_PME_PM_MRK_ST_GPS 29 #define POWER4_PME_PM_GRP_DISP_SUCCESS 30 #define POWER4_PME_PM_LSU1_LDF 31 #define POWER4_PME_PM_FAB_CMD_ISSUED 32 #define POWER4_PME_PM_LSU0_SRQ_STFWD 33 #define POWER4_PME_PM_CR_MAP_FULL_CYC 34 #define POWER4_PME_PM_MRK_LSU0_FLUSH_ULD 35 #define POWER4_PME_PM_LSU_DERAT_MISS 36 #define POWER4_PME_PM_FPU0_SINGLE 37 #define POWER4_PME_PM_FPU1_FDIV 38 #define POWER4_PME_PM_FPU1_FEST 39 #define POWER4_PME_PM_FPU0_FRSP_FCONV 40 #define POWER4_PME_PM_MRK_ST_CMPL_INT 41 #define POWER4_PME_PM_FXU_FIN 42 #define POWER4_PME_PM_FPU_STF 43 #define POWER4_PME_PM_DSLB_MISS 44 #define POWER4_PME_PM_DATA_FROM_L275_SHR 45 #define POWER4_PME_PM_FXLS1_FULL_CYC 46 #define POWER4_PME_PM_L3B0_DIR_MIS 47 #define POWER4_PME_PM_2INST_CLB_CYC 48 #define POWER4_PME_PM_MRK_STCX_FAIL 49 #define POWER4_PME_PM_LSU_LMQ_LHR_MERGE 50 #define POWER4_PME_PM_FXU0_BUSY_FXU1_IDLE 51 #define POWER4_PME_PM_L3B1_DIR_REF 52 #define POWER4_PME_PM_MRK_LSU_FLUSH_UST 53 #define POWER4_PME_PM_MRK_DATA_FROM_L25_SHR 54 #define POWER4_PME_PM_LSU_FLUSH_ULD 55 #define POWER4_PME_PM_MRK_BRU_FIN 56 #define POWER4_PME_PM_IERAT_XLATE_WR 57 #define POWER4_PME_PM_LSU0_BUSY 58 #define POWER4_PME_PM_L2SA_ST_REQ 59 #define POWER4_PME_PM_DATA_FROM_MEM 60 #define POWER4_PME_PM_FPR_MAP_FULL_CYC 61 #define POWER4_PME_PM_FPU1_FULL_CYC 62 #define POWER4_PME_PM_FPU0_FIN 63 #define POWER4_PME_PM_3INST_CLB_CYC 64 #define POWER4_PME_PM_DATA_FROM_L35 65 #define POWER4_PME_PM_L2SA_SHR_INV 66 #define POWER4_PME_PM_MRK_LSU_FLUSH_SRQ 67 #define POWER4_PME_PM_THRESH_TIMEO 68 #define POWER4_PME_PM_FPU_FSQRT 69 #define POWER4_PME_PM_MRK_LSU0_FLUSH_LRQ 70 #define POWER4_PME_PM_FXLS0_FULL_CYC 71 #define POWER4_PME_PM_DATA_TABLEWALK_CYC 72 #define POWER4_PME_PM_FPU0_ALL 73 #define POWER4_PME_PM_FPU0_FEST 74 #define POWER4_PME_PM_DATA_FROM_L25_MOD 75 #define POWER4_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC 76 #define POWER4_PME_PM_FPU_FEST 77 #define POWER4_PME_PM_0INST_FETCH 78 #define POWER4_PME_PM_LARX_LSU1 79 #define POWER4_PME_PM_LD_MISS_L1_LSU0 80 #define POWER4_PME_PM_L1_PREF 81 #define POWER4_PME_PM_FPU1_STALL3 82 #define POWER4_PME_PM_BRQ_FULL_CYC 83 #define POWER4_PME_PM_LARX 84 #define POWER4_PME_PM_MRK_DATA_FROM_L35 85 #define POWER4_PME_PM_WORK_HELD 86 #define POWER4_PME_PM_MRK_LD_MISS_L1_LSU0 87 #define POWER4_PME_PM_FXU_IDLE 88 #define POWER4_PME_PM_INST_CMPL 89 #define POWER4_PME_PM_LSU1_FLUSH_UST 90 #define POWER4_PME_PM_LSU0_FLUSH_ULD 91 #define POWER4_PME_PM_INST_FROM_L2 92 #define POWER4_PME_PM_DATA_FROM_L3 93 #define POWER4_PME_PM_FPU0_DENORM 94 #define POWER4_PME_PM_FPU1_FMOV_FEST 95 #define POWER4_PME_PM_GRP_DISP_REJECT 96 #define POWER4_PME_PM_INST_FETCH_CYC 97 #define POWER4_PME_PM_LSU_LDF 98 #define POWER4_PME_PM_INST_DISP 99 #define POWER4_PME_PM_L2SA_MOD_INV 100 #define POWER4_PME_PM_DATA_FROM_L25_SHR 101 #define POWER4_PME_PM_FAB_CMD_RETRIED 102 #define POWER4_PME_PM_L1_DCACHE_RELOAD_VALID 103 #define POWER4_PME_PM_MRK_GRP_ISSUED 104 #define POWER4_PME_PM_FPU_FULL_CYC 105 #define POWER4_PME_PM_FPU_FMA 106 #define POWER4_PME_PM_MRK_CRU_FIN 107 #define POWER4_PME_PM_MRK_LSU1_FLUSH_UST 108 #define POWER4_PME_PM_MRK_FXU_FIN 109 #define POWER4_PME_PM_BR_ISSUED 110 #define POWER4_PME_PM_EE_OFF 111 #define POWER4_PME_PM_INST_FROM_L3 112 #define POWER4_PME_PM_ITLB_MISS 113 #define POWER4_PME_PM_FXLS_FULL_CYC 114 #define POWER4_PME_PM_FXU1_BUSY_FXU0_IDLE 115 #define POWER4_PME_PM_GRP_DISP_VALID 116 #define POWER4_PME_PM_L2SC_ST_HIT 117 #define POWER4_PME_PM_MRK_GRP_DISP 118 #define POWER4_PME_PM_L2SB_MOD_TAG 119 #define POWER4_PME_PM_INST_FROM_L25_L275 120 #define POWER4_PME_PM_LSU_FLUSH_UST 121 #define POWER4_PME_PM_L2SB_ST_HIT 122 #define POWER4_PME_PM_FXU1_FIN 123 #define POWER4_PME_PM_L3B1_DIR_MIS 124 #define POWER4_PME_PM_4INST_CLB_CYC 125 #define POWER4_PME_PM_GRP_CMPL 126 #define POWER4_PME_PM_DC_PREF_L2_CLONE_L3 127 #define POWER4_PME_PM_FPU_FRSP_FCONV 128 #define POWER4_PME_PM_5INST_CLB_CYC 129 #define POWER4_PME_PM_MRK_LSU0_FLUSH_SRQ 130 #define POWER4_PME_PM_MRK_LSU_FLUSH_ULD 131 #define POWER4_PME_PM_8INST_CLB_CYC 132 #define POWER4_PME_PM_LSU_LMQ_FULL_CYC 133 #define POWER4_PME_PM_ST_REF_L1_LSU0 134 #define POWER4_PME_PM_LSU0_DERAT_MISS 135 #define POWER4_PME_PM_LSU_SRQ_SYNC_CYC 136 #define POWER4_PME_PM_FPU_STALL3 137 #define POWER4_PME_PM_MRK_DATA_FROM_L2 138 #define POWER4_PME_PM_FPU0_FMOV_FEST 139 #define POWER4_PME_PM_LSU0_FLUSH_SRQ 140 #define POWER4_PME_PM_LD_REF_L1_LSU0 141 #define POWER4_PME_PM_L2SC_SHR_INV 142 #define POWER4_PME_PM_LSU1_FLUSH_SRQ 143 #define POWER4_PME_PM_LSU_LMQ_S0_ALLOC 144 #define POWER4_PME_PM_ST_REF_L1 145 #define POWER4_PME_PM_LSU_SRQ_EMPTY_CYC 146 #define POWER4_PME_PM_FPU1_STF 147 #define POWER4_PME_PM_L3B0_DIR_REF 148 #define POWER4_PME_PM_RUN_CYC 149 #define POWER4_PME_PM_LSU_LMQ_S0_VALID 150 #define POWER4_PME_PM_LSU_LRQ_S0_VALID 151 #define POWER4_PME_PM_LSU0_LDF 152 #define POWER4_PME_PM_MRK_IMR_RELOAD 153 #define POWER4_PME_PM_7INST_CLB_CYC 154 #define POWER4_PME_PM_MRK_GRP_TIMEO 155 #define POWER4_PME_PM_FPU_FMOV_FEST 156 #define POWER4_PME_PM_GRP_DISP_BLK_SB_CYC 157 #define POWER4_PME_PM_XER_MAP_FULL_CYC 158 #define POWER4_PME_PM_ST_MISS_L1 159 #define POWER4_PME_PM_STOP_COMPLETION 160 #define POWER4_PME_PM_MRK_GRP_CMPL 161 #define POWER4_PME_PM_ISLB_MISS 162 #define POWER4_PME_PM_CYC 163 #define POWER4_PME_PM_LD_MISS_L1_LSU1 164 #define POWER4_PME_PM_STCX_FAIL 165 #define POWER4_PME_PM_LSU1_SRQ_STFWD 166 #define POWER4_PME_PM_GRP_DISP 167 #define POWER4_PME_PM_DATA_FROM_L2 168 #define POWER4_PME_PM_L2_PREF 169 #define POWER4_PME_PM_FPU0_FPSCR 170 #define POWER4_PME_PM_FPU1_DENORM 171 #define POWER4_PME_PM_MRK_DATA_FROM_L25_MOD 172 #define POWER4_PME_PM_L2SB_ST_REQ 173 #define POWER4_PME_PM_L2SB_MOD_INV 174 #define POWER4_PME_PM_FPU0_FSQRT 175 #define POWER4_PME_PM_LD_REF_L1 176 #define POWER4_PME_PM_MRK_L1_RELOAD_VALID 177 #define POWER4_PME_PM_L2SB_SHR_MOD 178 #define POWER4_PME_PM_INST_FROM_L1 179 #define POWER4_PME_PM_1PLUS_PPC_CMPL 180 #define POWER4_PME_PM_EE_OFF_EXT_INT 181 #define POWER4_PME_PM_L2SC_SHR_MOD 182 #define POWER4_PME_PM_LSU_LRQ_FULL_CYC 183 #define POWER4_PME_PM_IC_PREF_INSTALL 184 #define POWER4_PME_PM_MRK_LSU1_FLUSH_SRQ 185 #define POWER4_PME_PM_GCT_FULL_CYC 186 #define POWER4_PME_PM_INST_FROM_MEM 187 #define POWER4_PME_PM_FXU_BUSY 188 #define POWER4_PME_PM_ST_REF_L1_LSU1 189 #define POWER4_PME_PM_MRK_LD_MISS_L1 190 #define POWER4_PME_PM_MRK_LSU1_INST_FIN 191 #define POWER4_PME_PM_L1_WRITE_CYC 192 #define POWER4_PME_PM_BIQ_IDU_FULL_CYC 193 #define POWER4_PME_PM_MRK_LSU0_INST_FIN 194 #define POWER4_PME_PM_L2SC_ST_REQ 195 #define POWER4_PME_PM_LSU1_BUSY 196 #define POWER4_PME_PM_FPU_ALL 197 #define POWER4_PME_PM_LSU_SRQ_S0_ALLOC 198 #define POWER4_PME_PM_GRP_MRK 199 #define POWER4_PME_PM_FPU1_FIN 200 #define POWER4_PME_PM_DC_PREF_STREAM_ALLOC 201 #define POWER4_PME_PM_BR_MPRED_CR 202 #define POWER4_PME_PM_BR_MPRED_TA 203 #define POWER4_PME_PM_CRQ_FULL_CYC 204 #define POWER4_PME_PM_INST_FROM_PREF 205 #define POWER4_PME_PM_LD_MISS_L1 206 #define POWER4_PME_PM_STCX_PASS 207 #define POWER4_PME_PM_DC_INV_L2 208 #define POWER4_PME_PM_LSU_SRQ_FULL_CYC 209 #define POWER4_PME_PM_LSU0_FLUSH_LRQ 210 #define POWER4_PME_PM_LSU_SRQ_S0_VALID 211 #define POWER4_PME_PM_LARX_LSU0 212 #define POWER4_PME_PM_GCT_EMPTY_CYC 213 #define POWER4_PME_PM_FPU1_ALL 214 #define POWER4_PME_PM_FPU1_FSQRT 215 #define POWER4_PME_PM_FPU_FIN 216 #define POWER4_PME_PM_L2SA_SHR_MOD 217 #define POWER4_PME_PM_MRK_LD_MISS_L1_LSU1 218 #define POWER4_PME_PM_LSU_SRQ_STFWD 219 #define POWER4_PME_PM_FXU0_FIN 220 #define POWER4_PME_PM_MRK_FPU_FIN 221 #define POWER4_PME_PM_LSU_BUSY 222 #define POWER4_PME_PM_INST_FROM_L35 223 #define POWER4_PME_PM_FPU1_FRSP_FCONV 224 #define POWER4_PME_PM_SNOOP_TLBIE 225 #define POWER4_PME_PM_FPU0_FDIV 226 #define POWER4_PME_PM_LD_REF_L1_LSU1 227 #define POWER4_PME_PM_MRK_DATA_FROM_L275_MOD 228 #define POWER4_PME_PM_HV_CYC 229 #define POWER4_PME_PM_6INST_CLB_CYC 230 #define POWER4_PME_PM_LR_CTR_MAP_FULL_CYC 231 #define POWER4_PME_PM_L2SC_MOD_INV 232 #define POWER4_PME_PM_FPU_DENORM 233 #define POWER4_PME_PM_DATA_FROM_L275_MOD 234 #define POWER4_PME_PM_LSU1_DERAT_MISS 235 #define POWER4_PME_PM_IC_PREF_REQ 236 #define POWER4_PME_PM_MRK_LSU_FIN 237 #define POWER4_PME_PM_MRK_DATA_FROM_L3 238 #define POWER4_PME_PM_MRK_DATA_FROM_MEM 239 #define POWER4_PME_PM_LSU0_FLUSH_UST 240 #define POWER4_PME_PM_LSU_FLUSH_LRQ 241 #define POWER4_PME_PM_LSU_FLUSH_SRQ 242 #define POWER4_PME_PM_L2SC_MOD_TAG 243 static const pme_power_entry_t power4_pe[] = { [ POWER4_PME_PM_MRK_LSU_SRQ_INST_VALID ] = { .pme_name = "PM_MRK_LSU_SRQ_INST_VALID", .pme_code = 0x933, .pme_short_desc = "Marked instruction valid in SRQ", .pme_long_desc = "This signal is asserted every cycle when a marked request is resident in the Store Request Queue", }, [ POWER4_PME_PM_FPU1_SINGLE ] = { .pme_name = "PM_FPU1_SINGLE", .pme_code = 0x127, .pme_short_desc = "FPU1 executed single precision instruction", .pme_long_desc = "This signal is active for one cycle when fp1 is executing single precision instruction.", }, [ POWER4_PME_PM_DC_PREF_OUT_STREAMS ] = { .pme_name = "PM_DC_PREF_OUT_STREAMS", .pme_code = 0xc36, .pme_short_desc = "Out of prefetch streams", .pme_long_desc = "A new prefetch stream was detected, but no more stream entries were available", }, [ POWER4_PME_PM_FPU0_STALL3 ] = { .pme_name = "PM_FPU0_STALL3", .pme_code = 0x121, .pme_short_desc = "FPU0 stalled in pipe3", .pme_long_desc = "This signal indicates that fp0 has generated a stall in pipe3 due to overflow, underflow, massive cancel, convert to integer (sometimes), or convert from integer (always). This signal is active during the entire duration of the stall. ", }, [ POWER4_PME_PM_TB_BIT_TRANS ] = { .pme_name = "PM_TB_BIT_TRANS", .pme_code = 0x8005, .pme_short_desc = "Time Base bit transition", .pme_long_desc = "When the selected time base bit (as specified in MMCR0[TBSEL])transitions from 0 to 1 ", }, [ POWER4_PME_PM_GPR_MAP_FULL_CYC ] = { .pme_name = "PM_GPR_MAP_FULL_CYC", .pme_code = 0x235, .pme_short_desc = "Cycles GPR mapper full", .pme_long_desc = "The ISU sends a signal indicating that the gpr mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.", }, [ POWER4_PME_PM_MRK_ST_CMPL ] = { .pme_name = "PM_MRK_ST_CMPL", .pme_code = 0x1003, .pme_short_desc = "Marked store instruction completed", .pme_long_desc = "A sampled store has completed (data home)", }, [ POWER4_PME_PM_MRK_LSU_FLUSH_LRQ ] = { .pme_name = "PM_MRK_LSU_FLUSH_LRQ", .pme_code = 0x3910, .pme_short_desc = "Marked LRQ flushes", .pme_long_desc = "A marked load was flushed because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.", }, [ POWER4_PME_PM_FPU0_STF ] = { .pme_name = "PM_FPU0_STF", .pme_code = 0x122, .pme_short_desc = "FPU0 executed store instruction", .pme_long_desc = "This signal is active for one cycle when fp0 is executing a store instruction.", }, [ POWER4_PME_PM_FPU1_FMA ] = { .pme_name = "PM_FPU1_FMA", .pme_code = 0x105, .pme_short_desc = "FPU1 executed multiply-add instruction", .pme_long_desc = "This signal is active for one cycle when fp1 is executing multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs.", }, [ POWER4_PME_PM_L2SA_MOD_TAG ] = { .pme_name = "PM_L2SA_MOD_TAG", .pme_code = 0xf06, .pme_short_desc = "L2 slice A transition from modified to tagged", .pme_long_desc = "A cache line in the local L2 directory made a state transition from the Modified state to the Tagged state. This transition was caused by a read snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A,B,and C.", }, [ POWER4_PME_PM_MRK_DATA_FROM_L275_SHR ] = { .pme_name = "PM_MRK_DATA_FROM_L275_SHR", .pme_code = 0x6c76, .pme_short_desc = "Marked data loaded from L2.75 shared", .pme_long_desc = "DL1 was reloaded with shared (T) data from the L2 of another MCM due to a marked demand load", }, [ POWER4_PME_PM_1INST_CLB_CYC ] = { .pme_name = "PM_1INST_CLB_CYC", .pme_code = 0x450, .pme_short_desc = "Cycles 1 instruction in CLB", .pme_long_desc = "The cache line buffer (CLB) is an 8-deep, 4-wide instruction buffer. Fullness is indicated in the 8 valid bits associated with each of the 4-wide slots with full(0) correspanding to the number of cycles there are 8 instructions in the queue and full (7) corresponding to the number of cycles there is 1 instruction in the queue. This signal gives a real time history of the number of instruction quads valid in the instruction queue.", }, [ POWER4_PME_PM_LSU1_FLUSH_ULD ] = { .pme_name = "PM_LSU1_FLUSH_ULD", .pme_code = 0xc04, .pme_short_desc = "LSU1 unaligned load flushes", .pme_long_desc = "A load was flushed from unit 1 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)", }, [ POWER4_PME_PM_MRK_INST_FIN ] = { .pme_name = "PM_MRK_INST_FIN", .pme_code = 0x7005, .pme_short_desc = "Marked instruction finished", .pme_long_desc = "One of the execution units finished a marked instruction. Instructions that finish may not necessary complete", }, [ POWER4_PME_PM_MRK_LSU0_FLUSH_UST ] = { .pme_name = "PM_MRK_LSU0_FLUSH_UST", .pme_code = 0x911, .pme_short_desc = "LSU0 marked unaligned store flushes", .pme_long_desc = "A marked store was flushed from unit 0 because it was unaligned", }, [ POWER4_PME_PM_FPU_FDIV ] = { .pme_name = "PM_FPU_FDIV", .pme_code = 0x1100, .pme_short_desc = "FPU executed FDIV instruction", .pme_long_desc = "This signal is active for one cycle at the end of the microcode executed when FPU is executing a divide instruction. This could be fdiv, fdivs, fdiv. fdivs. Combined Unit 0 + Unit 1", }, [ POWER4_PME_PM_LSU_LRQ_S0_ALLOC ] = { .pme_name = "PM_LSU_LRQ_S0_ALLOC", .pme_code = 0xc26, .pme_short_desc = "LRQ slot 0 allocated", .pme_long_desc = "LRQ slot zero was allocated", }, [ POWER4_PME_PM_FPU0_FULL_CYC ] = { .pme_name = "PM_FPU0_FULL_CYC", .pme_code = 0x203, .pme_short_desc = "Cycles FPU0 issue queue full", .pme_long_desc = "The issue queue for FPU unit 0 cannot accept any more instructions. Issue is stopped", }, [ POWER4_PME_PM_FPU_SINGLE ] = { .pme_name = "PM_FPU_SINGLE", .pme_code = 0x5120, .pme_short_desc = "FPU executed single precision instruction", .pme_long_desc = "FPU is executing single precision instruction. Combined Unit 0 + Unit 1", }, [ POWER4_PME_PM_FPU0_FMA ] = { .pme_name = "PM_FPU0_FMA", .pme_code = 0x101, .pme_short_desc = "FPU0 executed multiply-add instruction", .pme_long_desc = "This signal is active for one cycle when fp0 is executing multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs.", }, [ POWER4_PME_PM_MRK_LSU1_FLUSH_ULD ] = { .pme_name = "PM_MRK_LSU1_FLUSH_ULD", .pme_code = 0x914, .pme_short_desc = "LSU1 marked unaligned load flushes", .pme_long_desc = "A marked load was flushed from unit 1 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)", }, [ POWER4_PME_PM_LSU1_FLUSH_LRQ ] = { .pme_name = "PM_LSU1_FLUSH_LRQ", .pme_code = 0xc06, .pme_short_desc = "LSU1 LRQ flushes", .pme_long_desc = "A load was flushed by unit 1 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.", }, [ POWER4_PME_PM_L2SA_ST_HIT ] = { .pme_name = "PM_L2SA_ST_HIT", .pme_code = 0xf11, .pme_short_desc = "L2 slice A store hits", .pme_long_desc = "A store request made from the core hit in the L2 directory. This event is provided on each of the three L2 slices A,B, and C.", }, [ POWER4_PME_PM_L2SB_SHR_INV ] = { .pme_name = "PM_L2SB_SHR_INV", .pme_code = 0xf21, .pme_short_desc = "L2 slice B transition from shared to invalid", .pme_long_desc = "A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L, or Tagged) to the Invalid state. This transition was caused by any external snoop request. The event is provided on each of the three slices A,B,and C. NOTE: For this event to be useful the tablewalk duration event should also be counted.", }, [ POWER4_PME_PM_DTLB_MISS ] = { .pme_name = "PM_DTLB_MISS", .pme_code = 0x904, .pme_short_desc = "Data TLB misses", .pme_long_desc = "A TLB miss for a data request occurred. Requests that miss the TLB may be retried until the instruction is in the next to complete group (unless HID4 is set to allow speculative tablewalks). This may result in multiple TLB misses for the same instruction.", }, [ POWER4_PME_PM_MRK_ST_MISS_L1 ] = { .pme_name = "PM_MRK_ST_MISS_L1", .pme_code = 0x923, .pme_short_desc = "Marked L1 D cache store misses", .pme_long_desc = "A marked store missed the dcache", }, [ POWER4_PME_PM_EXT_INT ] = { .pme_name = "PM_EXT_INT", .pme_code = 0x8002, .pme_short_desc = "External interrupts", .pme_long_desc = "An external interrupt occurred", }, [ POWER4_PME_PM_MRK_LSU1_FLUSH_LRQ ] = { .pme_name = "PM_MRK_LSU1_FLUSH_LRQ", .pme_code = 0x916, .pme_short_desc = "LSU1 marked LRQ flushes", .pme_long_desc = "A marked load was flushed by unit 1 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.", }, [ POWER4_PME_PM_MRK_ST_GPS ] = { .pme_name = "PM_MRK_ST_GPS", .pme_code = 0x6003, .pme_short_desc = "Marked store sent to GPS", .pme_long_desc = "A sampled store has been sent to the memory subsystem", }, [ POWER4_PME_PM_GRP_DISP_SUCCESS ] = { .pme_name = "PM_GRP_DISP_SUCCESS", .pme_code = 0x5001, .pme_short_desc = "Group dispatch success", .pme_long_desc = "Number of groups sucessfully dispatched (not rejected)", }, [ POWER4_PME_PM_LSU1_LDF ] = { .pme_name = "PM_LSU1_LDF", .pme_code = 0x934, .pme_short_desc = "LSU1 executed Floating Point load instruction", .pme_long_desc = "A floating point load was executed from LSU unit 1", }, [ POWER4_PME_PM_FAB_CMD_ISSUED ] = { .pme_name = "PM_FAB_CMD_ISSUED", .pme_code = 0xf16, .pme_short_desc = "Fabric command issued", .pme_long_desc = "A bus command was issued on the MCM to MCM fabric from the local (this chip's) Fabric Bus Controller. This event is scaled to the fabric frequency and must be adjusted for a true count. i.e. if the fabric is running 2:1, divide the count by 2.", }, [ POWER4_PME_PM_LSU0_SRQ_STFWD ] = { .pme_name = "PM_LSU0_SRQ_STFWD", .pme_code = 0xc20, .pme_short_desc = "LSU0 SRQ store forwarded", .pme_long_desc = "Data from a store instruction was forwarded to a load on unit 0", }, [ POWER4_PME_PM_CR_MAP_FULL_CYC ] = { .pme_name = "PM_CR_MAP_FULL_CYC", .pme_code = 0x204, .pme_short_desc = "Cycles CR logical operation mapper full", .pme_long_desc = "The ISU sends a signal indicating that the cr mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.", }, [ POWER4_PME_PM_MRK_LSU0_FLUSH_ULD ] = { .pme_name = "PM_MRK_LSU0_FLUSH_ULD", .pme_code = 0x910, .pme_short_desc = "LSU0 marked unaligned load flushes", .pme_long_desc = "A marked load was flushed from unit 0 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)", }, [ POWER4_PME_PM_LSU_DERAT_MISS ] = { .pme_name = "PM_LSU_DERAT_MISS", .pme_code = 0x6900, .pme_short_desc = "DERAT misses", .pme_long_desc = "Total D-ERAT Misses (Unit 0 + Unit 1). Requests that miss the Derat are rejected and retried until the request hits in the Erat. This may result in multiple erat misses for the same instruction.", }, [ POWER4_PME_PM_FPU0_SINGLE ] = { .pme_name = "PM_FPU0_SINGLE", .pme_code = 0x123, .pme_short_desc = "FPU0 executed single precision instruction", .pme_long_desc = "This signal is active for one cycle when fp0 is executing single precision instruction.", }, [ POWER4_PME_PM_FPU1_FDIV ] = { .pme_name = "PM_FPU1_FDIV", .pme_code = 0x104, .pme_short_desc = "FPU1 executed FDIV instruction", .pme_long_desc = "This signal is active for one cycle at the end of the microcode executed when fp1 is executing a divide instruction. This could be fdiv, fdivs, fdiv. fdivs.", }, [ POWER4_PME_PM_FPU1_FEST ] = { .pme_name = "PM_FPU1_FEST", .pme_code = 0x116, .pme_short_desc = "FPU1 executed FEST instruction", .pme_long_desc = "This signal is active for one cycle when fp1 is executing one of the estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ. ", }, [ POWER4_PME_PM_FPU0_FRSP_FCONV ] = { .pme_name = "PM_FPU0_FRSP_FCONV", .pme_code = 0x111, .pme_short_desc = "FPU0 executed FRSP or FCONV instructions", .pme_long_desc = "fThis signal is active for one cycle when fp0 is executing frsp or convert kind of instruction. This could be frsp*, fcfid*, fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs.", }, [ POWER4_PME_PM_MRK_ST_CMPL_INT ] = { .pme_name = "PM_MRK_ST_CMPL_INT", .pme_code = 0x3003, .pme_short_desc = "Marked store completed with intervention", .pme_long_desc = "A marked store previously sent to the memory subsystem completed (data home) after requiring intervention", }, [ POWER4_PME_PM_FXU_FIN ] = { .pme_name = "PM_FXU_FIN", .pme_code = 0x3230, .pme_short_desc = "FXU produced a result", .pme_long_desc = "The fixed point unit (Unit 0 + Unit 1) finished a marked instruction. Instructions that finish may not necessary complete.", }, [ POWER4_PME_PM_FPU_STF ] = { .pme_name = "PM_FPU_STF", .pme_code = 0x6120, .pme_short_desc = "FPU executed store instruction", .pme_long_desc = "FPU is executing a store instruction. Combined Unit 0 + Unit 1", }, [ POWER4_PME_PM_DSLB_MISS ] = { .pme_name = "PM_DSLB_MISS", .pme_code = 0x905, .pme_short_desc = "Data SLB misses", .pme_long_desc = "A SLB miss for a data request occurred. SLB misses trap to the operating system to resolve", }, [ POWER4_PME_PM_DATA_FROM_L275_SHR ] = { .pme_name = "PM_DATA_FROM_L275_SHR", .pme_code = 0x6c66, .pme_short_desc = "Data loaded from L2.75 shared", .pme_long_desc = "DL1 was reloaded with shared (T) data from the L2 of another MCM due to a demand load", }, [ POWER4_PME_PM_FXLS1_FULL_CYC ] = { .pme_name = "PM_FXLS1_FULL_CYC", .pme_code = 0x214, .pme_short_desc = "Cycles FXU1/LS1 queue full", .pme_long_desc = "The issue queue for FXU/LSU unit 1 cannot accept any more instructions. Issue is stopped", }, [ POWER4_PME_PM_L3B0_DIR_MIS ] = { .pme_name = "PM_L3B0_DIR_MIS", .pme_code = 0xf01, .pme_short_desc = "L3 bank 0 directory misses", .pme_long_desc = "A reference was made to the local L3 directory by a local CPU and it missed in the L3. Only requests from on-MCM CPUs are counted. This event is scaled to the L3 speed and the count must be scaled. i.e. if the L3 is running 3:1, divide the count by 3", }, [ POWER4_PME_PM_2INST_CLB_CYC ] = { .pme_name = "PM_2INST_CLB_CYC", .pme_code = 0x451, .pme_short_desc = "Cycles 2 instructions in CLB", .pme_long_desc = "The cache line buffer (CLB) is an 8-deep, 4-wide instruction buffer. Fullness is indicated in the 8 valid bits associated with each of the 4-wide slots with full(0) correspanding to the number of cycles there are 8 instructions in the queue and full (7) corresponding to the number of cycles there is 1 instruction in the queue. This signal gives a real time history of the number of instruction quads valid in the instruction queue.", }, [ POWER4_PME_PM_MRK_STCX_FAIL ] = { .pme_name = "PM_MRK_STCX_FAIL", .pme_code = 0x925, .pme_short_desc = "Marked STCX failed", .pme_long_desc = "A marked stcx (stwcx or stdcx) failed", }, [ POWER4_PME_PM_LSU_LMQ_LHR_MERGE ] = { .pme_name = "PM_LSU_LMQ_LHR_MERGE", .pme_code = 0x926, .pme_short_desc = "LMQ LHR merges", .pme_long_desc = "A dcache miss occurred for the same real cache line address as an earlier request already in the Load Miss Queue and was merged into the LMQ entry.", }, [ POWER4_PME_PM_FXU0_BUSY_FXU1_IDLE ] = { .pme_name = "PM_FXU0_BUSY_FXU1_IDLE", .pme_code = 0x7002, .pme_short_desc = "FXU0 busy FXU1 idle", .pme_long_desc = "FXU0 is busy while FXU1 was idle", }, [ POWER4_PME_PM_L3B1_DIR_REF ] = { .pme_name = "PM_L3B1_DIR_REF", .pme_code = 0xf02, .pme_short_desc = "L3 bank 1 directory references", .pme_long_desc = "A reference was made to the local L3 directory by a local CPU. Only requests from on-MCM CPUs are counted. This event is scaled to the L3 speed and the count must be scaled. i.e. if the L3 is running 3:1, divide the count by 3", }, [ POWER4_PME_PM_MRK_LSU_FLUSH_UST ] = { .pme_name = "PM_MRK_LSU_FLUSH_UST", .pme_code = 0x7910, .pme_short_desc = "Marked unaligned store flushes", .pme_long_desc = "A marked store was flushed because it was unaligned", }, [ POWER4_PME_PM_MRK_DATA_FROM_L25_SHR ] = { .pme_name = "PM_MRK_DATA_FROM_L25_SHR", .pme_code = 0x5c76, .pme_short_desc = "Marked data loaded from L2.5 shared", .pme_long_desc = "DL1 was reloaded with shared (T or SL) data from the L2 of a chip on this MCM due to a marked demand load", }, [ POWER4_PME_PM_LSU_FLUSH_ULD ] = { .pme_name = "PM_LSU_FLUSH_ULD", .pme_code = 0x1c00, .pme_short_desc = "LRQ unaligned load flushes", .pme_long_desc = "A load was flushed because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)", }, [ POWER4_PME_PM_MRK_BRU_FIN ] = { .pme_name = "PM_MRK_BRU_FIN", .pme_code = 0x2005, .pme_short_desc = "Marked instruction BRU processing finished", .pme_long_desc = "The branch unit finished a marked instruction. Instructions that finish may not necessary complete", }, [ POWER4_PME_PM_IERAT_XLATE_WR ] = { .pme_name = "PM_IERAT_XLATE_WR", .pme_code = 0x327, .pme_short_desc = "Translation written to ierat", .pme_long_desc = "This signal will be asserted each time the I-ERAT is written. This indicates that an ERAT miss has been serviced. ERAT misses will initiate a sequence resulting in the ERAT being written. ERAT misses that are later ignored will not be counted unless the ERAT is written before the instruction stream is changed, This should be a fairly accurate count of ERAT missed (best available).", }, [ POWER4_PME_PM_LSU0_BUSY ] = { .pme_name = "PM_LSU0_BUSY", .pme_code = 0xc33, .pme_short_desc = "LSU0 busy", .pme_long_desc = "LSU unit 0 is busy rejecting instructions", }, [ POWER4_PME_PM_L2SA_ST_REQ ] = { .pme_name = "PM_L2SA_ST_REQ", .pme_code = 0xf10, .pme_short_desc = "L2 slice A store requests", .pme_long_desc = "A store request as seen at the L2 directory has been made from the core. Stores are counted after gathering in the L2 store queues. The event is provided on each of the three slices A,B,and C.", }, [ POWER4_PME_PM_DATA_FROM_MEM ] = { .pme_name = "PM_DATA_FROM_MEM", .pme_code = 0x2c66, .pme_short_desc = "Data loaded from memory", .pme_long_desc = "DL1 was reloaded from memory due to a demand load", }, [ POWER4_PME_PM_FPR_MAP_FULL_CYC ] = { .pme_name = "PM_FPR_MAP_FULL_CYC", .pme_code = 0x201, .pme_short_desc = "Cycles FPR mapper full", .pme_long_desc = "The ISU sends a signal indicating that the FPR mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.", }, [ POWER4_PME_PM_FPU1_FULL_CYC ] = { .pme_name = "PM_FPU1_FULL_CYC", .pme_code = 0x207, .pme_short_desc = "Cycles FPU1 issue queue full", .pme_long_desc = "The issue queue for FPU unit 1 cannot accept any more instructions. Issue is stopped", }, [ POWER4_PME_PM_FPU0_FIN ] = { .pme_name = "PM_FPU0_FIN", .pme_code = 0x113, .pme_short_desc = "FPU0 produced a result", .pme_long_desc = "fp0 finished, produced a result This only indicates finish, not completion. ", }, [ POWER4_PME_PM_3INST_CLB_CYC ] = { .pme_name = "PM_3INST_CLB_CYC", .pme_code = 0x452, .pme_short_desc = "Cycles 3 instructions in CLB", .pme_long_desc = "The cache line buffer (CLB) is an 8-deep, 4-wide instruction buffer. Fullness is indicated in the 8 valid bits associated with each of the 4-wide slots with full(0) correspanding to the number of cycles there are 8 instructions in the queue and full (7) corresponding to the number of cycles there is 1 instruction in the queue. This signal gives a real time history of the number of instruction quads valid in the instruction queue.", }, [ POWER4_PME_PM_DATA_FROM_L35 ] = { .pme_name = "PM_DATA_FROM_L35", .pme_code = 0x3c66, .pme_short_desc = "Data loaded from L3.5", .pme_long_desc = "DL1 was reloaded from the L3 of another MCM due to a demand load", }, [ POWER4_PME_PM_L2SA_SHR_INV ] = { .pme_name = "PM_L2SA_SHR_INV", .pme_code = 0xf05, .pme_short_desc = "L2 slice A transition from shared to invalid", .pme_long_desc = "A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L, or Tagged) to the Invalid state. This transition was caused by any external snoop request. The event is provided on each of the three slices A,B,and C. NOTE: For this event to be useful the tablewalk duration event should also be counted.", }, [ POWER4_PME_PM_MRK_LSU_FLUSH_SRQ ] = { .pme_name = "PM_MRK_LSU_FLUSH_SRQ", .pme_code = 0x4910, .pme_short_desc = "Marked SRQ flushes", .pme_long_desc = "A marked store was flushed because younger load hits and older store that is already in the SRQ or in the same group.", }, [ POWER4_PME_PM_THRESH_TIMEO ] = { .pme_name = "PM_THRESH_TIMEO", .pme_code = 0x2003, .pme_short_desc = "Threshold timeout", .pme_long_desc = "The threshold timer expired", }, [ POWER4_PME_PM_FPU_FSQRT ] = { .pme_name = "PM_FPU_FSQRT", .pme_code = 0x6100, .pme_short_desc = "FPU executed FSQRT instruction", .pme_long_desc = "This signal is active for one cycle at the end of the microcode executed when FPU is executing a square root instruction. This could be fsqrt* where XYZ* means XYZ, XYZs, XYZ., XYZs. Combined Unit 0 + Unit 1", }, [ POWER4_PME_PM_MRK_LSU0_FLUSH_LRQ ] = { .pme_name = "PM_MRK_LSU0_FLUSH_LRQ", .pme_code = 0x912, .pme_short_desc = "LSU0 marked LRQ flushes", .pme_long_desc = "A marked load was flushed by unit 0 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.", }, [ POWER4_PME_PM_FXLS0_FULL_CYC ] = { .pme_name = "PM_FXLS0_FULL_CYC", .pme_code = 0x210, .pme_short_desc = "Cycles FXU0/LS0 queue full", .pme_long_desc = "The issue queue for FXU/LSU unit 0 cannot accept any more instructions. Issue is stopped", }, [ POWER4_PME_PM_DATA_TABLEWALK_CYC ] = { .pme_name = "PM_DATA_TABLEWALK_CYC", .pme_code = 0x936, .pme_short_desc = "Cycles doing data tablewalks", .pme_long_desc = "This signal is asserted every cycle when a tablewalk is active. While a tablewalk is active any request attempting to access the TLB will be rejected and retried.", }, [ POWER4_PME_PM_FPU0_ALL ] = { .pme_name = "PM_FPU0_ALL", .pme_code = 0x103, .pme_short_desc = "FPU0 executed add, mult, sub, cmp or sel instruction", .pme_long_desc = "This signal is active for one cycle when fp0 is executing an add, mult, sub, compare, or fsel kind of instruction. This could be fadd*, fmul*, fsub*, fcmp**, fsel where XYZ* means XYZ, XYZs, XYZ., XYZs. and XYZ** means XYZu, XYZo", }, [ POWER4_PME_PM_FPU0_FEST ] = { .pme_name = "PM_FPU0_FEST", .pme_code = 0x112, .pme_short_desc = "FPU0 executed FEST instruction", .pme_long_desc = "This signal is active for one cycle when fp0 is executing one of the estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ. ", }, [ POWER4_PME_PM_DATA_FROM_L25_MOD ] = { .pme_name = "PM_DATA_FROM_L25_MOD", .pme_code = 0x8c66, .pme_short_desc = "Data loaded from L2.5 modified", .pme_long_desc = "DL1 was reloaded with modified (M) data from the L2 of a chip on this MCM due to a demand load", }, [ POWER4_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC ] = { .pme_name = "PM_LSU_LMQ_SRQ_EMPTY_CYC", .pme_code = 0x2002, .pme_short_desc = "Cycles LMQ and SRQ empty", .pme_long_desc = "Cycles when both the LMQ and SRQ are empty (LSU is idle)", }, [ POWER4_PME_PM_FPU_FEST ] = { .pme_name = "PM_FPU_FEST", .pme_code = 0x3110, .pme_short_desc = "FPU executed FEST instruction", .pme_long_desc = "This signal is active for one cycle when executing one of the estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ. Combined Unit 0 + Unit 1.", }, [ POWER4_PME_PM_0INST_FETCH ] = { .pme_name = "PM_0INST_FETCH", .pme_code = 0x8327, .pme_short_desc = "No instructions fetched", .pme_long_desc = "No instructions were fetched this cycles (due to IFU hold, redirect, or icache miss)", }, [ POWER4_PME_PM_LARX_LSU1 ] = { .pme_name = "PM_LARX_LSU1", .pme_code = 0xc77, .pme_short_desc = "Larx executed on LSU1", .pme_long_desc = "Invalid event, larx instructions are never executed on unit 1", }, [ POWER4_PME_PM_LD_MISS_L1_LSU0 ] = { .pme_name = "PM_LD_MISS_L1_LSU0", .pme_code = 0xc12, .pme_short_desc = "LSU0 L1 D cache load misses", .pme_long_desc = "A load, executing on unit 0, missed the dcache", }, [ POWER4_PME_PM_L1_PREF ] = { .pme_name = "PM_L1_PREF", .pme_code = 0xc35, .pme_short_desc = "L1 cache data prefetches", .pme_long_desc = "A request to prefetch data into the L1 was made", }, [ POWER4_PME_PM_FPU1_STALL3 ] = { .pme_name = "PM_FPU1_STALL3", .pme_code = 0x125, .pme_short_desc = "FPU1 stalled in pipe3", .pme_long_desc = "This signal indicates that fp1 has generated a stall in pipe3 due to overflow, underflow, massive cancel, convert to integer (sometimes), or convert from integer (always). This signal is active during the entire duration of the stall. ", }, [ POWER4_PME_PM_BRQ_FULL_CYC ] = { .pme_name = "PM_BRQ_FULL_CYC", .pme_code = 0x205, .pme_short_desc = "Cycles branch queue full", .pme_long_desc = "The ISU sends a signal indicating that the issue queue that feeds the ifu br unit cannot accept any more group (queue is full of groups).", }, [ POWER4_PME_PM_LARX ] = { .pme_name = "PM_LARX", .pme_code = 0x4c70, .pme_short_desc = "Larx executed", .pme_long_desc = "A Larx (lwarx or ldarx) was executed. This is the combined count from LSU0 + LSU1, but these instructions only execute on LSU0", }, [ POWER4_PME_PM_MRK_DATA_FROM_L35 ] = { .pme_name = "PM_MRK_DATA_FROM_L35", .pme_code = 0x3c76, .pme_short_desc = "Marked data loaded from L3.5", .pme_long_desc = "DL1 was reloaded from the L3 of another MCM due to a marked demand load", }, [ POWER4_PME_PM_WORK_HELD ] = { .pme_name = "PM_WORK_HELD", .pme_code = 0x2001, .pme_short_desc = "Work held", .pme_long_desc = "RAS Unit has signaled completion to stop and there are groups waiting to complete", }, [ POWER4_PME_PM_MRK_LD_MISS_L1_LSU0 ] = { .pme_name = "PM_MRK_LD_MISS_L1_LSU0", .pme_code = 0x920, .pme_short_desc = "LSU0 L1 D cache load misses", .pme_long_desc = "A marked load, executing on unit 0, missed the dcache", }, [ POWER4_PME_PM_FXU_IDLE ] = { .pme_name = "PM_FXU_IDLE", .pme_code = 0x5002, .pme_short_desc = "FXU idle", .pme_long_desc = "FXU0 and FXU1 are both idle", }, [ POWER4_PME_PM_INST_CMPL ] = { .pme_name = "PM_INST_CMPL", .pme_code = 0x8001, .pme_short_desc = "Instructions completed", .pme_long_desc = "Number of Eligible Instructions that completed. ", }, [ POWER4_PME_PM_LSU1_FLUSH_UST ] = { .pme_name = "PM_LSU1_FLUSH_UST", .pme_code = 0xc05, .pme_short_desc = "LSU1 unaligned store flushes", .pme_long_desc = "A store was flushed from unit 1 because it was unaligned (crossed a 4k boundary)", }, [ POWER4_PME_PM_LSU0_FLUSH_ULD ] = { .pme_name = "PM_LSU0_FLUSH_ULD", .pme_code = 0xc00, .pme_short_desc = "LSU0 unaligned load flushes", .pme_long_desc = "A load was flushed from unit 0 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)", }, [ POWER4_PME_PM_INST_FROM_L2 ] = { .pme_name = "PM_INST_FROM_L2", .pme_code = 0x3327, .pme_short_desc = "Instructions fetched from L2", .pme_long_desc = "An instruction fetch group was fetched from L2. Fetch Groups can contain up to 8 instructions", }, [ POWER4_PME_PM_DATA_FROM_L3 ] = { .pme_name = "PM_DATA_FROM_L3", .pme_code = 0x1c66, .pme_short_desc = "Data loaded from L3", .pme_long_desc = "DL1 was reloaded from the local L3 due to a demand load", }, [ POWER4_PME_PM_FPU0_DENORM ] = { .pme_name = "PM_FPU0_DENORM", .pme_code = 0x120, .pme_short_desc = "FPU0 received denormalized data", .pme_long_desc = "This signal is active for one cycle when one of the operands is denormalized.", }, [ POWER4_PME_PM_FPU1_FMOV_FEST ] = { .pme_name = "PM_FPU1_FMOV_FEST", .pme_code = 0x114, .pme_short_desc = "FPU1 executing FMOV or FEST instructions", .pme_long_desc = "This signal is active for one cycle when fp1 is executing a move kind of instruction or one of the estimate instructions.. This could be fmr*, fneg*, fabs*, fnabs* , fres* or frsqrte* where XYZ* means XYZ or XYZ", }, [ POWER4_PME_PM_GRP_DISP_REJECT ] = { .pme_name = "PM_GRP_DISP_REJECT", .pme_code = 0x8003, .pme_short_desc = "Group dispatch rejected", .pme_long_desc = "A group that previously attempted dispatch was rejected.", }, [ POWER4_PME_PM_INST_FETCH_CYC ] = { .pme_name = "PM_INST_FETCH_CYC", .pme_code = 0x323, .pme_short_desc = "Cycles at least 1 instruction fetched", .pme_long_desc = "Asserted each cycle when the IFU sends at least one instruction to the IDU. ", }, [ POWER4_PME_PM_LSU_LDF ] = { .pme_name = "PM_LSU_LDF", .pme_code = 0x8930, .pme_short_desc = "LSU executed Floating Point load instruction", .pme_long_desc = "LSU executed Floating Point load instruction", }, [ POWER4_PME_PM_INST_DISP ] = { .pme_name = "PM_INST_DISP", .pme_code = 0x221, .pme_short_desc = "Instructions dispatched", .pme_long_desc = "The ISU sends the number of instructions dispatched.", }, [ POWER4_PME_PM_L2SA_MOD_INV ] = { .pme_name = "PM_L2SA_MOD_INV", .pme_code = 0xf07, .pme_short_desc = "L2 slice A transition from modified to invalid", .pme_long_desc = "A cache line in the local L2 directory made a state transition from the Modified state to the Invalid state. This transition was caused by any RWITM snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A,B,and C.", }, [ POWER4_PME_PM_DATA_FROM_L25_SHR ] = { .pme_name = "PM_DATA_FROM_L25_SHR", .pme_code = 0x5c66, .pme_short_desc = "Data loaded from L2.5 shared", .pme_long_desc = "DL1 was reloaded with shared (T or SL) data from the L2 of a chip on this MCM due to a demand load", }, [ POWER4_PME_PM_FAB_CMD_RETRIED ] = { .pme_name = "PM_FAB_CMD_RETRIED", .pme_code = 0xf17, .pme_short_desc = "Fabric command retried", .pme_long_desc = "A bus command on the MCM to MCM fabric was retried. This event is the total count of all retried fabric commands for the local MCM (all four chips report the same value). This event is scaled to the fabric frequency and must be adjusted for a true count. i.e. if the fabric is running 2:1, divide the count by 2.", }, [ POWER4_PME_PM_L1_DCACHE_RELOAD_VALID ] = { .pme_name = "PM_L1_DCACHE_RELOAD_VALID", .pme_code = 0xc64, .pme_short_desc = "L1 reload data source valid", .pme_long_desc = "The data source information is valid", }, [ POWER4_PME_PM_MRK_GRP_ISSUED ] = { .pme_name = "PM_MRK_GRP_ISSUED", .pme_code = 0x6005, .pme_short_desc = "Marked group issued", .pme_long_desc = "A sampled instruction was issued", }, [ POWER4_PME_PM_FPU_FULL_CYC ] = { .pme_name = "PM_FPU_FULL_CYC", .pme_code = 0x5200, .pme_short_desc = "Cycles FPU issue queue full", .pme_long_desc = "Cycles when one or both FPU issue queues are full", }, [ POWER4_PME_PM_FPU_FMA ] = { .pme_name = "PM_FPU_FMA", .pme_code = 0x2100, .pme_short_desc = "FPU executed multiply-add instruction", .pme_long_desc = "This signal is active for one cycle when FPU is executing multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs. Combined Unit 0 + Unit 1", }, [ POWER4_PME_PM_MRK_CRU_FIN ] = { .pme_name = "PM_MRK_CRU_FIN", .pme_code = 0x4005, .pme_short_desc = "Marked instruction CRU processing finished", .pme_long_desc = "The Condition Register Unit finished a marked instruction. Instructions that finish may not necessary complete", }, [ POWER4_PME_PM_MRK_LSU1_FLUSH_UST ] = { .pme_name = "PM_MRK_LSU1_FLUSH_UST", .pme_code = 0x915, .pme_short_desc = "LSU1 marked unaligned store flushes", .pme_long_desc = "A marked store was flushed from unit 1 because it was unaligned (crossed a 4k boundary)", }, [ POWER4_PME_PM_MRK_FXU_FIN ] = { .pme_name = "PM_MRK_FXU_FIN", .pme_code = 0x6004, .pme_short_desc = "Marked instruction FXU processing finished", .pme_long_desc = "One of the Fixed Point Units finished a marked instruction. Instructions that finish may not necessary complete", }, [ POWER4_PME_PM_BR_ISSUED ] = { .pme_name = "PM_BR_ISSUED", .pme_code = 0x330, .pme_short_desc = "Branches issued", .pme_long_desc = "This signal will be asserted each time the ISU issues a branch instruction. This signal will be asserted each time the ISU selects a branch instruction to issue.", }, [ POWER4_PME_PM_EE_OFF ] = { .pme_name = "PM_EE_OFF", .pme_code = 0x233, .pme_short_desc = "Cycles MSR(EE) bit off", .pme_long_desc = "The number of Cycles MSR(EE) bit was off.", }, [ POWER4_PME_PM_INST_FROM_L3 ] = { .pme_name = "PM_INST_FROM_L3", .pme_code = 0x5327, .pme_short_desc = "Instruction fetched from L3", .pme_long_desc = "An instruction fetch group was fetched from L3. Fetch Groups can contain up to 8 instructions", }, [ POWER4_PME_PM_ITLB_MISS ] = { .pme_name = "PM_ITLB_MISS", .pme_code = 0x900, .pme_short_desc = "Instruction TLB misses", .pme_long_desc = "A TLB miss for an Instruction Fetch has occurred", }, [ POWER4_PME_PM_FXLS_FULL_CYC ] = { .pme_name = "PM_FXLS_FULL_CYC", .pme_code = 0x8210, .pme_short_desc = "Cycles FXLS queue is full", .pme_long_desc = "Cycles when one or both FXU/LSU issue queue are full", }, [ POWER4_PME_PM_FXU1_BUSY_FXU0_IDLE ] = { .pme_name = "PM_FXU1_BUSY_FXU0_IDLE", .pme_code = 0x4002, .pme_short_desc = "FXU1 busy FXU0 idle", .pme_long_desc = "FXU0 was idle while FXU1 was busy", }, [ POWER4_PME_PM_GRP_DISP_VALID ] = { .pme_name = "PM_GRP_DISP_VALID", .pme_code = 0x223, .pme_short_desc = "Group dispatch valid", .pme_long_desc = "Dispatch has been attempted for a valid group. Some groups may be rejected. The total number of successful dispatches is the number of dispatch valid minus dispatch reject.", }, [ POWER4_PME_PM_L2SC_ST_HIT ] = { .pme_name = "PM_L2SC_ST_HIT", .pme_code = 0xf15, .pme_short_desc = "L2 slice C store hits", .pme_long_desc = "A store request made from the core hit in the L2 directory. This event is provided on each of the three L2 slices A,B, and C.", }, [ POWER4_PME_PM_MRK_GRP_DISP ] = { .pme_name = "PM_MRK_GRP_DISP", .pme_code = 0x1002, .pme_short_desc = "Marked group dispatched", .pme_long_desc = "A group containing a sampled instruction was dispatched", }, [ POWER4_PME_PM_L2SB_MOD_TAG ] = { .pme_name = "PM_L2SB_MOD_TAG", .pme_code = 0xf22, .pme_short_desc = "L2 slice B transition from modified to tagged", .pme_long_desc = "A cache line in the local L2 directory made a state transition from the Modified state to the Tagged state. This transition was caused by a read snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A,B,and C.", }, [ POWER4_PME_PM_INST_FROM_L25_L275 ] = { .pme_name = "PM_INST_FROM_L25_L275", .pme_code = 0x2327, .pme_short_desc = "Instruction fetched from L2.5/L2.75", .pme_long_desc = "An instruction fetch group was fetched from the L2 of another chip. Fetch Groups can contain up to 8 instructions", }, [ POWER4_PME_PM_LSU_FLUSH_UST ] = { .pme_name = "PM_LSU_FLUSH_UST", .pme_code = 0x2c00, .pme_short_desc = "SRQ unaligned store flushes", .pme_long_desc = "A store was flushed because it was unaligned", }, [ POWER4_PME_PM_L2SB_ST_HIT ] = { .pme_name = "PM_L2SB_ST_HIT", .pme_code = 0xf13, .pme_short_desc = "L2 slice B store hits", .pme_long_desc = "A store request made from the core hit in the L2 directory. This event is provided on each of the three L2 slices A,B, and C.", }, [ POWER4_PME_PM_FXU1_FIN ] = { .pme_name = "PM_FXU1_FIN", .pme_code = 0x236, .pme_short_desc = "FXU1 produced a result", .pme_long_desc = "The Fixed Point unit 1 finished an instruction and produced a result", }, [ POWER4_PME_PM_L3B1_DIR_MIS ] = { .pme_name = "PM_L3B1_DIR_MIS", .pme_code = 0xf03, .pme_short_desc = "L3 bank 1 directory misses", .pme_long_desc = "A reference was made to the local L3 directory by a local CPU and it missed in the L3. Only requests from on-MCM CPUs are counted. This event is scaled to the L3 speed and the count must be scaled. i.e. if the L3 is running 3:1, divide the count by 3", }, [ POWER4_PME_PM_4INST_CLB_CYC ] = { .pme_name = "PM_4INST_CLB_CYC", .pme_code = 0x453, .pme_short_desc = "Cycles 4 instructions in CLB", .pme_long_desc = "The cache line buffer (CLB) is an 8-deep, 4-wide instruction buffer. Fullness is indicated in the 8 valid bits associated with each of the 4-wide slots with full(0) correspanding to the number of cycles there are 8 instructions in the queue and full (7) corresponding to the number of cycles there is 1 instruction in the queue. This signal gives a real time history of the number of instruction quads valid in the instruction queue.", }, [ POWER4_PME_PM_GRP_CMPL ] = { .pme_name = "PM_GRP_CMPL", .pme_code = 0x7003, .pme_short_desc = "Group completed", .pme_long_desc = "A group completed. Microcoded instructions that span multiple groups will generate this event once per group.", }, [ POWER4_PME_PM_DC_PREF_L2_CLONE_L3 ] = { .pme_name = "PM_DC_PREF_L2_CLONE_L3", .pme_code = 0xc27, .pme_short_desc = "L2 prefetch cloned with L3", .pme_long_desc = "A prefetch request was made to the L2 with a cloned request sent to the L3", }, [ POWER4_PME_PM_FPU_FRSP_FCONV ] = { .pme_name = "PM_FPU_FRSP_FCONV", .pme_code = 0x7110, .pme_short_desc = "FPU executed FRSP or FCONV instructions", .pme_long_desc = "This signal is active for one cycle when executing frsp or convert kind of instruction. This could be frsp*, fcfid*, fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs. Combined Unit 0 + Unit 1", }, [ POWER4_PME_PM_5INST_CLB_CYC ] = { .pme_name = "PM_5INST_CLB_CYC", .pme_code = 0x454, .pme_short_desc = "Cycles 5 instructions in CLB", .pme_long_desc = "The cache line buffer (CLB) is an 8-deep, 4-wide instruction buffer. Fullness is indicated in the 8 valid bits associated with each of the 4-wide slots with full(0) correspanding to the number of cycles there are 8 instructions in the queue and full (7) corresponding to the number of cycles there is 1 instruction in the queue. This signal gives a real time history of the number of instruction quads valid in the instruction queue.", }, [ POWER4_PME_PM_MRK_LSU0_FLUSH_SRQ ] = { .pme_name = "PM_MRK_LSU0_FLUSH_SRQ", .pme_code = 0x913, .pme_short_desc = "LSU0 marked SRQ flushes", .pme_long_desc = "A marked store was flushed because younger load hits and older store that is already in the SRQ or in the same group.", }, [ POWER4_PME_PM_MRK_LSU_FLUSH_ULD ] = { .pme_name = "PM_MRK_LSU_FLUSH_ULD", .pme_code = 0x8910, .pme_short_desc = "Marked unaligned load flushes", .pme_long_desc = "A marked load was flushed because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)", }, [ POWER4_PME_PM_8INST_CLB_CYC ] = { .pme_name = "PM_8INST_CLB_CYC", .pme_code = 0x457, .pme_short_desc = "Cycles 8 instructions in CLB", .pme_long_desc = "The cache line buffer (CLB) is an 8-deep, 4-wide instruction buffer. Fullness is indicated in the 8 valid bits associated with each of the 4-wide slots with full(0) correspanding to the number of cycles there are 8 instructions in the queue and full (7) corresponding to the number of cycles there is 1 instruction in the queue. This signal gives a real time history of the number of instruction quads valid in the instruction queue.", }, [ POWER4_PME_PM_LSU_LMQ_FULL_CYC ] = { .pme_name = "PM_LSU_LMQ_FULL_CYC", .pme_code = 0x927, .pme_short_desc = "Cycles LMQ full", .pme_long_desc = "The LMQ was full", }, [ POWER4_PME_PM_ST_REF_L1_LSU0 ] = { .pme_name = "PM_ST_REF_L1_LSU0", .pme_code = 0xc11, .pme_short_desc = "LSU0 L1 D cache store references", .pme_long_desc = "A store executed on unit 0", }, [ POWER4_PME_PM_LSU0_DERAT_MISS ] = { .pme_name = "PM_LSU0_DERAT_MISS", .pme_code = 0x902, .pme_short_desc = "LSU0 DERAT misses", .pme_long_desc = "A data request (load or store) from LSU Unit 0 missed the ERAT and resulted in an ERAT reload. Multiple instructions may miss the ERAT entry for the same 4K page, but only one reload will occur.", }, [ POWER4_PME_PM_LSU_SRQ_SYNC_CYC ] = { .pme_name = "PM_LSU_SRQ_SYNC_CYC", .pme_code = 0x932, .pme_short_desc = "SRQ sync duration", .pme_long_desc = "This signal is asserted every cycle when a sync is in the SRQ.", }, [ POWER4_PME_PM_FPU_STALL3 ] = { .pme_name = "PM_FPU_STALL3", .pme_code = 0x2120, .pme_short_desc = "FPU stalled in pipe3", .pme_long_desc = "FPU has generated a stall in pipe3 due to overflow, underflow, massive cancel, convert to integer (sometimes), or convert from integer (always). This signal is active during the entire duration of the stall. Combined Unit 0 + Unit 1", }, [ POWER4_PME_PM_MRK_DATA_FROM_L2 ] = { .pme_name = "PM_MRK_DATA_FROM_L2", .pme_code = 0x4c76, .pme_short_desc = "Marked data loaded from L2", .pme_long_desc = "DL1 was reloaded from the local L2 due to a marked demand load", }, [ POWER4_PME_PM_FPU0_FMOV_FEST ] = { .pme_name = "PM_FPU0_FMOV_FEST", .pme_code = 0x110, .pme_short_desc = "FPU0 executed FMOV or FEST instructions", .pme_long_desc = "This signal is active for one cycle when fp0 is executing a move kind of instruction or one of the estimate instructions.. This could be fmr*, fneg*, fabs*, fnabs* , fres* or frsqrte* where XYZ* means XYZ or XYZ", }, [ POWER4_PME_PM_LSU0_FLUSH_SRQ ] = { .pme_name = "PM_LSU0_FLUSH_SRQ", .pme_code = 0xc03, .pme_short_desc = "LSU0 SRQ flushes", .pme_long_desc = "A store was flushed because younger load hits and older store that is already in the SRQ or in the same group.", }, [ POWER4_PME_PM_LD_REF_L1_LSU0 ] = { .pme_name = "PM_LD_REF_L1_LSU0", .pme_code = 0xc10, .pme_short_desc = "LSU0 L1 D cache load references", .pme_long_desc = "A load executed on unit 0", }, [ POWER4_PME_PM_L2SC_SHR_INV ] = { .pme_name = "PM_L2SC_SHR_INV", .pme_code = 0xf25, .pme_short_desc = "L2 slice C transition from shared to invalid", .pme_long_desc = "A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L, or Tagged) to the Invalid state. This transition was caused by any external snoop request. The event is provided on each of the three slices A,B,and C. NOTE: For this event to be useful the tablewalk duration event should also be counted.", }, [ POWER4_PME_PM_LSU1_FLUSH_SRQ ] = { .pme_name = "PM_LSU1_FLUSH_SRQ", .pme_code = 0xc07, .pme_short_desc = "LSU1 SRQ flushes", .pme_long_desc = "A store was flushed because younger load hits and older store that is already in the SRQ or in the same group. ", }, [ POWER4_PME_PM_LSU_LMQ_S0_ALLOC ] = { .pme_name = "PM_LSU_LMQ_S0_ALLOC", .pme_code = 0x935, .pme_short_desc = "LMQ slot 0 allocated", .pme_long_desc = "The first entry in the LMQ was allocated.", }, [ POWER4_PME_PM_ST_REF_L1 ] = { .pme_name = "PM_ST_REF_L1", .pme_code = 0x7c10, .pme_short_desc = "L1 D cache store references", .pme_long_desc = "Total DL1 Store references", }, [ POWER4_PME_PM_LSU_SRQ_EMPTY_CYC ] = { .pme_name = "PM_LSU_SRQ_EMPTY_CYC", .pme_code = 0x4003, .pme_short_desc = "Cycles SRQ empty", .pme_long_desc = "The Store Request Queue is empty", }, [ POWER4_PME_PM_FPU1_STF ] = { .pme_name = "PM_FPU1_STF", .pme_code = 0x126, .pme_short_desc = "FPU1 executed store instruction", .pme_long_desc = "This signal is active for one cycle when fp1 is executing a store instruction.", }, [ POWER4_PME_PM_L3B0_DIR_REF ] = { .pme_name = "PM_L3B0_DIR_REF", .pme_code = 0xf00, .pme_short_desc = "L3 bank 0 directory references", .pme_long_desc = "A reference was made to the local L3 directory by a local CPU. Only requests from on-MCM CPUs are counted. This event is scaled to the L3 speed and the count must be scaled. i.e. if the L3 is running 3:1, divide the count by 3", }, [ POWER4_PME_PM_RUN_CYC ] = { .pme_name = "PM_RUN_CYC", .pme_code = 0x1005, .pme_short_desc = "Run cycles", .pme_long_desc = "Processor Cycles gated by the run latch", }, [ POWER4_PME_PM_LSU_LMQ_S0_VALID ] = { .pme_name = "PM_LSU_LMQ_S0_VALID", .pme_code = 0x931, .pme_short_desc = "LMQ slot 0 valid", .pme_long_desc = "This signal is asserted every cycle when the first entry in the LMQ is valid. The LMQ had eight entries that are allocated FIFO", }, [ POWER4_PME_PM_LSU_LRQ_S0_VALID ] = { .pme_name = "PM_LSU_LRQ_S0_VALID", .pme_code = 0xc22, .pme_short_desc = "LRQ slot 0 valid", .pme_long_desc = "This signal is asserted every cycle that the Load Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin.", }, [ POWER4_PME_PM_LSU0_LDF ] = { .pme_name = "PM_LSU0_LDF", .pme_code = 0x930, .pme_short_desc = "LSU0 executed Floating Point load instruction", .pme_long_desc = "A floating point load was executed from LSU unit 0", }, [ POWER4_PME_PM_MRK_IMR_RELOAD ] = { .pme_name = "PM_MRK_IMR_RELOAD", .pme_code = 0x922, .pme_short_desc = "Marked IMR reloaded", .pme_long_desc = "A DL1 reload occurred due to marked load", }, [ POWER4_PME_PM_7INST_CLB_CYC ] = { .pme_name = "PM_7INST_CLB_CYC", .pme_code = 0x456, .pme_short_desc = "Cycles 7 instructions in CLB", .pme_long_desc = "The cache line buffer (CLB) is an 8-deep, 4-wide instruction buffer. Fullness is indicated in the 8 valid bits associated with each of the 4-wide slots with full(0) correspanding to the number of cycles there are 8 instructions in the queue and full (7) corresponding to the number of cycles there is 1 instruction in the queue. This signal gives a real time history of the number of instruction quads valid in the instruction queue.", }, [ POWER4_PME_PM_MRK_GRP_TIMEO ] = { .pme_name = "PM_MRK_GRP_TIMEO", .pme_code = 0x5005, .pme_short_desc = "Marked group completion timeout", .pme_long_desc = "The sampling timeout expired indicating that the previously sampled instruction is no longer in the processor", }, [ POWER4_PME_PM_FPU_FMOV_FEST ] = { .pme_name = "PM_FPU_FMOV_FEST", .pme_code = 0x8110, .pme_short_desc = "FPU executing FMOV or FEST instructions", .pme_long_desc = "This signal is active for one cycle when executing a move kind of instruction or one of the estimate instructions.. This could be fmr*, fneg*, fabs*, fnabs* , fres* or frsqrte* where XYZ* means XYZ or XYZ . Combined Unit 0 + Unit 1", }, [ POWER4_PME_PM_GRP_DISP_BLK_SB_CYC ] = { .pme_name = "PM_GRP_DISP_BLK_SB_CYC", .pme_code = 0x231, .pme_short_desc = "Cycles group dispatch blocked by scoreboard", .pme_long_desc = "The ISU sends a signal indicating that dispatch is blocked by scoreboard.", }, [ POWER4_PME_PM_XER_MAP_FULL_CYC ] = { .pme_name = "PM_XER_MAP_FULL_CYC", .pme_code = 0x202, .pme_short_desc = "Cycles XER mapper full", .pme_long_desc = "The ISU sends a signal indicating that the xer mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.", }, [ POWER4_PME_PM_ST_MISS_L1 ] = { .pme_name = "PM_ST_MISS_L1", .pme_code = 0xc23, .pme_short_desc = "L1 D cache store misses", .pme_long_desc = "A store missed the dcache", }, [ POWER4_PME_PM_STOP_COMPLETION ] = { .pme_name = "PM_STOP_COMPLETION", .pme_code = 0x3001, .pme_short_desc = "Completion stopped", .pme_long_desc = "RAS Unit has signaled completion to stop", }, [ POWER4_PME_PM_MRK_GRP_CMPL ] = { .pme_name = "PM_MRK_GRP_CMPL", .pme_code = 0x4004, .pme_short_desc = "Marked group completed", .pme_long_desc = "A group containing a sampled instruction completed. Microcoded instructions that span multiple groups will generate this event once per group.", }, [ POWER4_PME_PM_ISLB_MISS ] = { .pme_name = "PM_ISLB_MISS", .pme_code = 0x901, .pme_short_desc = "Instruction SLB misses", .pme_long_desc = "A SLB miss for an instruction fetch as occurred", }, [ POWER4_PME_PM_CYC ] = { .pme_name = "PM_CYC", .pme_code = 0x7, .pme_short_desc = "Processor cycles", .pme_long_desc = "Processor cycles", }, [ POWER4_PME_PM_LD_MISS_L1_LSU1 ] = { .pme_name = "PM_LD_MISS_L1_LSU1", .pme_code = 0xc16, .pme_short_desc = "LSU1 L1 D cache load misses", .pme_long_desc = "A load, executing on unit 1, missed the dcache", }, [ POWER4_PME_PM_STCX_FAIL ] = { .pme_name = "PM_STCX_FAIL", .pme_code = 0x921, .pme_short_desc = "STCX failed", .pme_long_desc = "A stcx (stwcx or stdcx) failed", }, [ POWER4_PME_PM_LSU1_SRQ_STFWD ] = { .pme_name = "PM_LSU1_SRQ_STFWD", .pme_code = 0xc24, .pme_short_desc = "LSU1 SRQ store forwarded", .pme_long_desc = "Data from a store instruction was forwarded to a load on unit 1", }, [ POWER4_PME_PM_GRP_DISP ] = { .pme_name = "PM_GRP_DISP", .pme_code = 0x2004, .pme_short_desc = "Group dispatches", .pme_long_desc = "A group was dispatched", }, [ POWER4_PME_PM_DATA_FROM_L2 ] = { .pme_name = "PM_DATA_FROM_L2", .pme_code = 0x4c66, .pme_short_desc = "Data loaded from L2", .pme_long_desc = "DL1 was reloaded from the local L2 due to a demand load", }, [ POWER4_PME_PM_L2_PREF ] = { .pme_name = "PM_L2_PREF", .pme_code = 0xc34, .pme_short_desc = "L2 cache prefetches", .pme_long_desc = "A request to prefetch data into L2 was made", }, [ POWER4_PME_PM_FPU0_FPSCR ] = { .pme_name = "PM_FPU0_FPSCR", .pme_code = 0x130, .pme_short_desc = "FPU0 executed FPSCR instruction", .pme_long_desc = "This signal is active for one cycle when fp0 is executing fpscr move related instruction. This could be mtfsfi*, mtfsb0*, mtfsb1*. mffs*, mtfsf*, mcrsf* where XYZ* means XYZ, XYZs, XYZ., XYZs", }, [ POWER4_PME_PM_FPU1_DENORM ] = { .pme_name = "PM_FPU1_DENORM", .pme_code = 0x124, .pme_short_desc = "FPU1 received denormalized data", .pme_long_desc = "This signal is active for one cycle when one of the operands is denormalized.", }, [ POWER4_PME_PM_MRK_DATA_FROM_L25_MOD ] = { .pme_name = "PM_MRK_DATA_FROM_L25_MOD", .pme_code = 0x8c76, .pme_short_desc = "Marked data loaded from L2.5 modified", .pme_long_desc = "DL1 was reloaded with modified (M) data from the L2 of a chip on this MCM due to a marked demand load", }, [ POWER4_PME_PM_L2SB_ST_REQ ] = { .pme_name = "PM_L2SB_ST_REQ", .pme_code = 0xf12, .pme_short_desc = "L2 slice B store requests", .pme_long_desc = "A store request as seen at the L2 directory has been made from the core. Stores are counted after gathering in the L2 store queues. The event is provided on each of the three slices A,B,and C.", }, [ POWER4_PME_PM_L2SB_MOD_INV ] = { .pme_name = "PM_L2SB_MOD_INV", .pme_code = 0xf23, .pme_short_desc = "L2 slice B transition from modified to invalid", .pme_long_desc = "A cache line in the local L2 directory made a state transition from the Modified state to the Invalid state. This transition was caused by any RWITM snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A,B,and C.", }, [ POWER4_PME_PM_FPU0_FSQRT ] = { .pme_name = "PM_FPU0_FSQRT", .pme_code = 0x102, .pme_short_desc = "FPU0 executed FSQRT instruction", .pme_long_desc = "This signal is active for one cycle at the end of the microcode executed when fp0 is executing a square root instruction. This could be fsqrt* where XYZ* means XYZ, XYZs, XYZ., XYZs.", }, [ POWER4_PME_PM_LD_REF_L1 ] = { .pme_name = "PM_LD_REF_L1", .pme_code = 0x8c10, .pme_short_desc = "L1 D cache load references", .pme_long_desc = "Total DL1 Load references", }, [ POWER4_PME_PM_MRK_L1_RELOAD_VALID ] = { .pme_name = "PM_MRK_L1_RELOAD_VALID", .pme_code = 0xc74, .pme_short_desc = "Marked L1 reload data source valid", .pme_long_desc = "The source information is valid and is for a marked load", }, [ POWER4_PME_PM_L2SB_SHR_MOD ] = { .pme_name = "PM_L2SB_SHR_MOD", .pme_code = 0xf20, .pme_short_desc = "L2 slice B transition from shared to modified", .pme_long_desc = "A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L , or Tagged) to the Modified state. This transition was caused by a store from either of the two local CPUs to a cache line in any of the Shared states. The event is provided on each of the three slices A,B,and C. ", }, [ POWER4_PME_PM_INST_FROM_L1 ] = { .pme_name = "PM_INST_FROM_L1", .pme_code = 0x6327, .pme_short_desc = "Instruction fetched from L1", .pme_long_desc = "An instruction fetch group was fetched from L1. Fetch Groups can contain up to 8 instructions", }, [ POWER4_PME_PM_1PLUS_PPC_CMPL ] = { .pme_name = "PM_1PLUS_PPC_CMPL", .pme_code = 0x5003, .pme_short_desc = "One or more PPC instruction completed", .pme_long_desc = "A group containing at least one PPC instruction completed. For microcoded instructions that span multiple groups, this will only occur once.", }, [ POWER4_PME_PM_EE_OFF_EXT_INT ] = { .pme_name = "PM_EE_OFF_EXT_INT", .pme_code = 0x237, .pme_short_desc = "Cycles MSR(EE) bit off and external interrupt pending", .pme_long_desc = "Cycles MSR(EE) bit off and external interrupt pending", }, [ POWER4_PME_PM_L2SC_SHR_MOD ] = { .pme_name = "PM_L2SC_SHR_MOD", .pme_code = 0xf24, .pme_short_desc = "L2 slice C transition from shared to modified", .pme_long_desc = "A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L , or Tagged) to the Modified state. This transition was caused by a store from either of the two local CPUs to a cache line in any of the Shared states. The event is provided on each of the three slices A,B,and C. ", }, [ POWER4_PME_PM_LSU_LRQ_FULL_CYC ] = { .pme_name = "PM_LSU_LRQ_FULL_CYC", .pme_code = 0x212, .pme_short_desc = "Cycles LRQ full", .pme_long_desc = "The isu sends this signal when the lrq is full.", }, [ POWER4_PME_PM_IC_PREF_INSTALL ] = { .pme_name = "PM_IC_PREF_INSTALL", .pme_code = 0x325, .pme_short_desc = "Instruction prefetched installed in prefetch buffer", .pme_long_desc = "This signal is asserted when a prefetch buffer entry (line) is allocated but the request is not a demand fetch.", }, [ POWER4_PME_PM_MRK_LSU1_FLUSH_SRQ ] = { .pme_name = "PM_MRK_LSU1_FLUSH_SRQ", .pme_code = 0x917, .pme_short_desc = "LSU1 marked SRQ flushes", .pme_long_desc = "A marked store was flushed because younger load hits and older store that is already in the SRQ or in the same group.", }, [ POWER4_PME_PM_GCT_FULL_CYC ] = { .pme_name = "PM_GCT_FULL_CYC", .pme_code = 0x200, .pme_short_desc = "Cycles GCT full", .pme_long_desc = "The ISU sends a signal indicating the gct is full. ", }, [ POWER4_PME_PM_INST_FROM_MEM ] = { .pme_name = "PM_INST_FROM_MEM", .pme_code = 0x1327, .pme_short_desc = "Instruction fetched from memory", .pme_long_desc = "An instruction fetch group was fetched from memory. Fetch Groups can contain up to 8 instructions", }, [ POWER4_PME_PM_FXU_BUSY ] = { .pme_name = "PM_FXU_BUSY", .pme_code = 0x6002, .pme_short_desc = "FXU busy", .pme_long_desc = "FXU0 and FXU1 are both busy", }, [ POWER4_PME_PM_ST_REF_L1_LSU1 ] = { .pme_name = "PM_ST_REF_L1_LSU1", .pme_code = 0xc15, .pme_short_desc = "LSU1 L1 D cache store references", .pme_long_desc = "A store executed on unit 1", }, [ POWER4_PME_PM_MRK_LD_MISS_L1 ] = { .pme_name = "PM_MRK_LD_MISS_L1", .pme_code = 0x1920, .pme_short_desc = "Marked L1 D cache load misses", .pme_long_desc = "Marked L1 D cache load misses", }, [ POWER4_PME_PM_MRK_LSU1_INST_FIN ] = { .pme_name = "PM_MRK_LSU1_INST_FIN", .pme_code = 0xc32, .pme_short_desc = "LSU1 finished a marked instruction", .pme_long_desc = "LSU unit 1 finished a marked instruction", }, [ POWER4_PME_PM_L1_WRITE_CYC ] = { .pme_name = "PM_L1_WRITE_CYC", .pme_code = 0x333, .pme_short_desc = "Cycles writing to instruction L1", .pme_long_desc = "This signal is asserted each cycle a cache write is active.", }, [ POWER4_PME_PM_BIQ_IDU_FULL_CYC ] = { .pme_name = "PM_BIQ_IDU_FULL_CYC", .pme_code = 0x324, .pme_short_desc = "Cycles BIQ or IDU full", .pme_long_desc = "This signal will be asserted each time either the IDU is full or the BIQ is full.", }, [ POWER4_PME_PM_MRK_LSU0_INST_FIN ] = { .pme_name = "PM_MRK_LSU0_INST_FIN", .pme_code = 0xc31, .pme_short_desc = "LSU0 finished a marked instruction", .pme_long_desc = "LSU unit 0 finished a marked instruction", }, [ POWER4_PME_PM_L2SC_ST_REQ ] = { .pme_name = "PM_L2SC_ST_REQ", .pme_code = 0xf14, .pme_short_desc = "L2 slice C store requests", .pme_long_desc = "A store request as seen at the L2 directory has been made from the core. Stores are counted after gathering in the L2 store queues. The event is provided on each of the three slices A,B,and C.", }, [ POWER4_PME_PM_LSU1_BUSY ] = { .pme_name = "PM_LSU1_BUSY", .pme_code = 0xc37, .pme_short_desc = "LSU1 busy", .pme_long_desc = "LSU unit 1 is busy rejecting instructions ", }, [ POWER4_PME_PM_FPU_ALL ] = { .pme_name = "PM_FPU_ALL", .pme_code = 0x5100, .pme_short_desc = "FPU executed add, mult, sub, cmp or sel instruction", .pme_long_desc = "This signal is active for one cycle when FPU is executing an add, mult, sub, compare, or fsel kind of instruction. This could be fadd*, fmul*, fsub*, fcmp**, fsel where XYZ* means XYZ, XYZs, XYZ., XYZs. and XYZ** means XYZu, XYZo. Combined Unit 0 + Unit 1", }, [ POWER4_PME_PM_LSU_SRQ_S0_ALLOC ] = { .pme_name = "PM_LSU_SRQ_S0_ALLOC", .pme_code = 0xc25, .pme_short_desc = "SRQ slot 0 allocated", .pme_long_desc = "SRQ Slot zero was allocated", }, [ POWER4_PME_PM_GRP_MRK ] = { .pme_name = "PM_GRP_MRK", .pme_code = 0x5004, .pme_short_desc = "Group marked in IDU", .pme_long_desc = "A group was sampled (marked)", }, [ POWER4_PME_PM_FPU1_FIN ] = { .pme_name = "PM_FPU1_FIN", .pme_code = 0x117, .pme_short_desc = "FPU1 produced a result", .pme_long_desc = "fp1 finished, produced a result. This only indicates finish, not completion. ", }, [ POWER4_PME_PM_DC_PREF_STREAM_ALLOC ] = { .pme_name = "PM_DC_PREF_STREAM_ALLOC", .pme_code = 0x907, .pme_short_desc = "D cache new prefetch stream allocated", .pme_long_desc = "A new Prefetch Stream was allocated", }, [ POWER4_PME_PM_BR_MPRED_CR ] = { .pme_name = "PM_BR_MPRED_CR", .pme_code = 0x331, .pme_short_desc = "Branch mispredictions due CR bit setting", .pme_long_desc = "This signal is asserted when the branch execution unit detects a branch mispredict because the CR value is opposite of the predicted value. This signal is asserted after a branch issue event and will result in a branch redirect flush if not overridden by a flush of an older instruction.", }, [ POWER4_PME_PM_BR_MPRED_TA ] = { .pme_name = "PM_BR_MPRED_TA", .pme_code = 0x332, .pme_short_desc = "Branch mispredictions due to target address", .pme_long_desc = "branch miss predict due to a target address prediction. This signal will be asserted each time the branch execution unit detects an incorrect target address prediction. This signal will be asserted after a valid branch execution unit issue and will cause a branch mispredict flush unless a flush is detected from an older instruction.", }, [ POWER4_PME_PM_CRQ_FULL_CYC ] = { .pme_name = "PM_CRQ_FULL_CYC", .pme_code = 0x211, .pme_short_desc = "Cycles CR issue queue full", .pme_long_desc = "The ISU sends a signal indicating that the issue queue that feeds the ifu cr unit cannot accept any more group (queue is full of groups).", }, [ POWER4_PME_PM_INST_FROM_PREF ] = { .pme_name = "PM_INST_FROM_PREF", .pme_code = 0x7327, .pme_short_desc = "Instructions fetched from prefetch", .pme_long_desc = "An instruction fetch group was fetched from the prefetch buffer. Fetch Groups can contain up to 8 instructions", }, [ POWER4_PME_PM_LD_MISS_L1 ] = { .pme_name = "PM_LD_MISS_L1", .pme_code = 0x3c10, .pme_short_desc = "L1 D cache load misses", .pme_long_desc = "Total DL1 Load references that miss the DL1", }, [ POWER4_PME_PM_STCX_PASS ] = { .pme_name = "PM_STCX_PASS", .pme_code = 0xc75, .pme_short_desc = "Stcx passes", .pme_long_desc = "A stcx (stwcx or stdcx) instruction was successful", }, [ POWER4_PME_PM_DC_INV_L2 ] = { .pme_name = "PM_DC_INV_L2", .pme_code = 0xc17, .pme_short_desc = "L1 D cache entries invalidated from L2", .pme_long_desc = "A dcache invalidated was received from the L2 because a line in L2 was castout.", }, [ POWER4_PME_PM_LSU_SRQ_FULL_CYC ] = { .pme_name = "PM_LSU_SRQ_FULL_CYC", .pme_code = 0x213, .pme_short_desc = "Cycles SRQ full", .pme_long_desc = "The isu sends this signal when the srq is full.", }, [ POWER4_PME_PM_LSU0_FLUSH_LRQ ] = { .pme_name = "PM_LSU0_FLUSH_LRQ", .pme_code = 0xc02, .pme_short_desc = "LSU0 LRQ flushes", .pme_long_desc = "A load was flushed by unit 1 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.", }, [ POWER4_PME_PM_LSU_SRQ_S0_VALID ] = { .pme_name = "PM_LSU_SRQ_S0_VALID", .pme_code = 0xc21, .pme_short_desc = "SRQ slot 0 valid", .pme_long_desc = "This signal is asserted every cycle that the Store Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin.", }, [ POWER4_PME_PM_LARX_LSU0 ] = { .pme_name = "PM_LARX_LSU0", .pme_code = 0xc73, .pme_short_desc = "Larx executed on LSU0", .pme_long_desc = "A larx (lwarx or ldarx) was executed on side 0 (there is no coresponding unit 1 event since larx instructions can only execute on unit 0)", }, [ POWER4_PME_PM_GCT_EMPTY_CYC ] = { .pme_name = "PM_GCT_EMPTY_CYC", .pme_code = 0x1004, .pme_short_desc = "Cycles GCT empty", .pme_long_desc = "The Global Completion Table is completely empty", }, [ POWER4_PME_PM_FPU1_ALL ] = { .pme_name = "PM_FPU1_ALL", .pme_code = 0x107, .pme_short_desc = "FPU1 executed add, mult, sub, cmp or sel instruction", .pme_long_desc = "This signal is active for one cycle when fp1 is executing an add, mult, sub, compare, or fsel kind of instruction. This could be fadd*, fmul*, fsub*, fcmp**, fsel where XYZ* means XYZ, XYZs, XYZ., XYZs. and XYZ** means XYZu, XYZo", }, [ POWER4_PME_PM_FPU1_FSQRT ] = { .pme_name = "PM_FPU1_FSQRT", .pme_code = 0x106, .pme_short_desc = "FPU1 executed FSQRT instruction", .pme_long_desc = "This signal is active for one cycle at the end of the microcode executed when fp1 is executing a square root instruction. This could be fsqrt* where XYZ* means XYZ, XYZs, XYZ., XYZs.", }, [ POWER4_PME_PM_FPU_FIN ] = { .pme_name = "PM_FPU_FIN", .pme_code = 0x4110, .pme_short_desc = "FPU produced a result", .pme_long_desc = "FPU finished, produced a result This only indicates finish, not completion. Combined Unit 0 + Unit 1", }, [ POWER4_PME_PM_L2SA_SHR_MOD ] = { .pme_name = "PM_L2SA_SHR_MOD", .pme_code = 0xf04, .pme_short_desc = "L2 slice A transition from shared to modified", .pme_long_desc = "A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L , or Tagged) to the Modified state. This transition was caused by a store from either of the two local CPUs to a cache line in any of the Shared states. The event is provided on each of the three slices A,B,and C. ", }, [ POWER4_PME_PM_MRK_LD_MISS_L1_LSU1 ] = { .pme_name = "PM_MRK_LD_MISS_L1_LSU1", .pme_code = 0x924, .pme_short_desc = "LSU1 L1 D cache load misses", .pme_long_desc = "A marked load, executing on unit 1, missed the dcache", }, [ POWER4_PME_PM_LSU_SRQ_STFWD ] = { .pme_name = "PM_LSU_SRQ_STFWD", .pme_code = 0x1c20, .pme_short_desc = "SRQ store forwarded", .pme_long_desc = "Data from a store instruction was forwarded to a load", }, [ POWER4_PME_PM_FXU0_FIN ] = { .pme_name = "PM_FXU0_FIN", .pme_code = 0x232, .pme_short_desc = "FXU0 produced a result", .pme_long_desc = "The Fixed Point unit 0 finished an instruction and produced a result", }, [ POWER4_PME_PM_MRK_FPU_FIN ] = { .pme_name = "PM_MRK_FPU_FIN", .pme_code = 0x7004, .pme_short_desc = "Marked instruction FPU processing finished", .pme_long_desc = "One of the Floating Point Units finished a marked instruction. Instructions that finish may not necessary complete", }, [ POWER4_PME_PM_LSU_BUSY ] = { .pme_name = "PM_LSU_BUSY", .pme_code = 0x4c30, .pme_short_desc = "LSU busy", .pme_long_desc = "LSU (unit 0 + unit 1) is busy rejecting instructions ", }, [ POWER4_PME_PM_INST_FROM_L35 ] = { .pme_name = "PM_INST_FROM_L35", .pme_code = 0x4327, .pme_short_desc = "Instructions fetched from L3.5", .pme_long_desc = "An instruction fetch group was fetched from the L3 of another module. Fetch Groups can contain up to 8 instructions", }, [ POWER4_PME_PM_FPU1_FRSP_FCONV ] = { .pme_name = "PM_FPU1_FRSP_FCONV", .pme_code = 0x115, .pme_short_desc = "FPU1 executed FRSP or FCONV instructions", .pme_long_desc = "fThis signal is active for one cycle when fp1 is executing frsp or convert kind of instruction. This could be frsp*, fcfid*, fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs.", }, [ POWER4_PME_PM_SNOOP_TLBIE ] = { .pme_name = "PM_SNOOP_TLBIE", .pme_code = 0x903, .pme_short_desc = "Snoop TLBIE", .pme_long_desc = "A TLB miss for a data request occurred. Requests that miss the TLB may be retried until the instruction is in the next to complete group (unless HID4 is set to allow speculative tablewalks). This may result in multiple TLB misses for the same instruction.", }, [ POWER4_PME_PM_FPU0_FDIV ] = { .pme_name = "PM_FPU0_FDIV", .pme_code = 0x100, .pme_short_desc = "FPU0 executed FDIV instruction", .pme_long_desc = "This signal is active for one cycle at the end of the microcode executed when fp0 is executing a divide instruction. This could be fdiv, fdivs, fdiv. fdivs.", }, [ POWER4_PME_PM_LD_REF_L1_LSU1 ] = { .pme_name = "PM_LD_REF_L1_LSU1", .pme_code = 0xc14, .pme_short_desc = "LSU1 L1 D cache load references", .pme_long_desc = "A load executed on unit 1", }, [ POWER4_PME_PM_MRK_DATA_FROM_L275_MOD ] = { .pme_name = "PM_MRK_DATA_FROM_L275_MOD", .pme_code = 0x7c76, .pme_short_desc = "Marked data loaded from L2.75 modified", .pme_long_desc = "DL1 was reloaded with modified (M) data from the L2 of another MCM due to a marked demand load. ", }, [ POWER4_PME_PM_HV_CYC ] = { .pme_name = "PM_HV_CYC", .pme_code = 0x3004, .pme_short_desc = "Hypervisor Cycles", .pme_long_desc = "Cycles when the processor is executing in Hypervisor (MSR[HV] = 0 and MSR[PR]=0)", }, [ POWER4_PME_PM_6INST_CLB_CYC ] = { .pme_name = "PM_6INST_CLB_CYC", .pme_code = 0x455, .pme_short_desc = "Cycles 6 instructions in CLB", .pme_long_desc = "The cache line buffer (CLB) is an 8-deep, 4-wide instruction buffer. Fullness is indicated in the 8 valid bits associated with each of the 4-wide slots with full(0) correspanding to the number of cycles there are 8 instructions in the queue and full (7) corresponding to the number of cycles there is 1 instruction in the queue. This signal gives a real time history of the number of instruction quads valid in the instruction queue.", }, [ POWER4_PME_PM_LR_CTR_MAP_FULL_CYC ] = { .pme_name = "PM_LR_CTR_MAP_FULL_CYC", .pme_code = 0x206, .pme_short_desc = "Cycles LR/CTR mapper full", .pme_long_desc = "The ISU sends a signal indicating that the lr/ctr mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.", }, [ POWER4_PME_PM_L2SC_MOD_INV ] = { .pme_name = "PM_L2SC_MOD_INV", .pme_code = 0xf27, .pme_short_desc = "L2 slice C transition from modified to invalid", .pme_long_desc = "A cache line in the local L2 directory made a state transition from the Modified state to the Invalid state. This transition was caused by any RWITM snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A,B,and C.", }, [ POWER4_PME_PM_FPU_DENORM ] = { .pme_name = "PM_FPU_DENORM", .pme_code = 0x1120, .pme_short_desc = "FPU received denormalized data", .pme_long_desc = "This signal is active for one cycle when one of the operands is denormalized. Combined Unit 0 + Unit 1", }, [ POWER4_PME_PM_DATA_FROM_L275_MOD ] = { .pme_name = "PM_DATA_FROM_L275_MOD", .pme_code = 0x7c66, .pme_short_desc = "Data loaded from L2.75 modified", .pme_long_desc = "DL1 was reloaded with modified (M) data from the L2 of another MCM due to a demand load. ", }, [ POWER4_PME_PM_LSU1_DERAT_MISS ] = { .pme_name = "PM_LSU1_DERAT_MISS", .pme_code = 0x906, .pme_short_desc = "LSU1 DERAT misses", .pme_long_desc = "A data request (load or store) from LSU Unit 1 missed the ERAT and resulted in an ERAT reload. Multiple instructions may miss the ERAT entry for the same 4K page, but only one reload will occur.", }, [ POWER4_PME_PM_IC_PREF_REQ ] = { .pme_name = "PM_IC_PREF_REQ", .pme_code = 0x326, .pme_short_desc = "Instruction prefetch requests", .pme_long_desc = "Asserted when a non-canceled prefetch is made to the cache interface unit (CIU).", }, [ POWER4_PME_PM_MRK_LSU_FIN ] = { .pme_name = "PM_MRK_LSU_FIN", .pme_code = 0x8004, .pme_short_desc = "Marked instruction LSU processing finished", .pme_long_desc = "One of the Load/Store Units finished a marked instruction. Instructions that finish may not necessary complete", }, [ POWER4_PME_PM_MRK_DATA_FROM_L3 ] = { .pme_name = "PM_MRK_DATA_FROM_L3", .pme_code = 0x1c76, .pme_short_desc = "Marked data loaded from L3", .pme_long_desc = "DL1 was reloaded from the local L3 due to a marked demand load", }, [ POWER4_PME_PM_MRK_DATA_FROM_MEM ] = { .pme_name = "PM_MRK_DATA_FROM_MEM", .pme_code = 0x2c76, .pme_short_desc = "Marked data loaded from memory", .pme_long_desc = "DL1 was reloaded from memory due to a marked demand load", }, [ POWER4_PME_PM_LSU0_FLUSH_UST ] = { .pme_name = "PM_LSU0_FLUSH_UST", .pme_code = 0xc01, .pme_short_desc = "LSU0 unaligned store flushes", .pme_long_desc = "A store was flushed from unit 0 because it was unaligned (crossed a 4k boundary)", }, [ POWER4_PME_PM_LSU_FLUSH_LRQ ] = { .pme_name = "PM_LSU_FLUSH_LRQ", .pme_code = 0x6c00, .pme_short_desc = "LRQ flushes", .pme_long_desc = "A load was flushed because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.", }, [ POWER4_PME_PM_LSU_FLUSH_SRQ ] = { .pme_name = "PM_LSU_FLUSH_SRQ", .pme_code = 0x5c00, .pme_short_desc = "SRQ flushes", .pme_long_desc = "A store was flushed because younger load hits and older store that is already in the SRQ or in the same group.", }, [ POWER4_PME_PM_L2SC_MOD_TAG ] = { .pme_name = "PM_L2SC_MOD_TAG", .pme_code = 0xf26, .pme_short_desc = "L2 slice C transition from modified to tagged", .pme_long_desc = "A cache line in the local L2 directory made a state transition from the Modified state to the Tagged state. This transition was caused by a read snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A,B,and C.", } }; #endif libpfm-4.9.0/lib/events/intel_bdx_unc_imc_events.h0000664000175000017500000006340213223402656022077 0ustar eranianeranian/* * Copyright (c) 2017 Google Inc. All rights reserved * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * PMU: bdx_unc_imc */ static intel_x86_umask_t bdx_unc_m_act_count[]={ { .uname = "BYP", .ucode = 0x800, .udesc = "DRAM Activate Count -- Activate due to Write", }, { .uname = "RD", .ucode = 0x100, .udesc = "DRAM Activate Count -- Activate due to Read", }, { .uname = "WR", .ucode = 0x200, .udesc = "DRAM Activate Count -- Activate due to Write", }, }; static intel_x86_umask_t bdx_unc_m_byp_cmds[]={ { .uname = "ACT", .ucode = 0x100, .udesc = "ACT command issued by 2 cycle bypass", }, { .uname = "CAS", .ucode = 0x200, .udesc = "CAS command issued by 2 cycle bypass", }, { .uname = "PRE", .ucode = 0x400, .udesc = "PRE command issued by 2 cycle bypass", }, }; static intel_x86_umask_t bdx_unc_m_cas_count[]={ { .uname = "ALL", .ucode = 0xf00, .udesc = "DRAM RD_CAS and WR_CAS Commands. All DRAM WR_CAS (w/ and w/out auto-pre)", .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "RD", .ucode = 0x300, .udesc = "DRAM RD_CAS and WR_CAS Commands. All DRAM Reads (RD_CAS + Underfills)", .uflags = INTEL_X86_NCOMBO, }, { .uname = "RD_REG", .ucode = 0x100, .udesc = "DRAM RD_CAS and WR_CAS Commands. All DRAM RD_CAS (w/ and w/out auto-pre)", }, { .uname = "RD_RMM", .ucode = 0x2000, .udesc = "DRAM RD_CAS and WR_CAS Commands. Read CAS issued in RMM", }, { .uname = "RD_UNDERFILL", .ucode = 0x200, .udesc = "DRAM RD_CAS and WR_CAS Commands. Underfill Read Issued", }, { .uname = "RD_WMM", .ucode = 0x1000, .udesc = "DRAM RD_CAS and WR_CAS Commands. Read CAS issued in WMM", }, { .uname = "WR", .ucode = 0xc00, .udesc = "DRAM RD_CAS and WR_CAS Commands. All DRAM WR_CAS (both Modes)", .uflags = INTEL_X86_NCOMBO, }, { .uname = "WR_RMM", .ucode = 0x800, .udesc = "DRAM RD_CAS and WR_CAS Commands. DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mode", }, { .uname = "WR_WMM", .ucode = 0x400, .udesc = "DRAM RD_CAS and WR_CAS Commands. DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode", }, }; static intel_x86_umask_t bdx_unc_m_dram_refresh[]={ { .uname = "HIGH", .ucode = 0x400, .udesc = "Number of DRAM Refreshes Issued", }, { .uname = "PANIC", .ucode = 0x200, .udesc = "Number of DRAM Refreshes Issued", }, }; static intel_x86_umask_t bdx_unc_m_major_modes[]={ { .uname = "ISOCH", .ucode = 0x800, .udesc = "Cycles in a Major Mode -- Isoch Major Mode", }, { .uname = "PARTIAL", .ucode = 0x400, .udesc = "Cycles in a Major Mode -- Partial Major Mode", }, { .uname = "READ", .ucode = 0x100, .udesc = "Cycles in a Major Mode -- Read Major Mode", }, { .uname = "WRITE", .ucode = 0x200, .udesc = "Cycles in a Major Mode -- Write Major Mode", }, }; static intel_x86_umask_t bdx_unc_m_power_cke_cycles[]={ { .uname = "RANK0", .ucode = 0x100, .udesc = "CKE_ON_CYCLES by Rank -- DIMM ID", .uflags = INTEL_X86_NCOMBO, }, { .uname = "RANK1", .ucode = 0x200, .udesc = "CKE_ON_CYCLES by Rank -- DIMM ID", .uflags = INTEL_X86_NCOMBO, }, { .uname = "RANK2", .ucode = 0x400, .udesc = "CKE_ON_CYCLES by Rank -- DIMM ID", .uflags = INTEL_X86_NCOMBO, }, { .uname = "RANK3", .ucode = 0x800, .udesc = "CKE_ON_CYCLES by Rank -- DIMM ID", .uflags = INTEL_X86_NCOMBO, }, { .uname = "RANK4", .ucode = 0x1000, .udesc = "CKE_ON_CYCLES by Rank -- DIMM ID", .uflags = INTEL_X86_NCOMBO, }, { .uname = "RANK5", .ucode = 0x2000, .udesc = "CKE_ON_CYCLES by Rank -- DIMM ID", .uflags = INTEL_X86_NCOMBO, }, { .uname = "RANK6", .ucode = 0x4000, .udesc = "CKE_ON_CYCLES by Rank -- DIMM ID", .uflags = INTEL_X86_NCOMBO, }, { .uname = "RANK7", .ucode = 0x8000, .udesc = "CKE_ON_CYCLES by Rank -- DIMM ID", .uflags = INTEL_X86_NCOMBO, }, }; static intel_x86_umask_t bdx_unc_m_power_throttle_cycles[]={ { .uname = "RANK0", .ucode = 0x100, .udesc = "Throttle Cycles for Rank 0 -- DIMM ID", }, { .uname = "RANK1", .ucode = 0x200, .udesc = "Throttle Cycles for Rank 0 -- DIMM ID", }, { .uname = "RANK2", .ucode = 0x400, .udesc = "Throttle Cycles for Rank 0 -- DIMM ID", }, { .uname = "RANK3", .ucode = 0x800, .udesc = "Throttle Cycles for Rank 0 -- DIMM ID", }, { .uname = "RANK4", .ucode = 0x1000, .udesc = "Throttle Cycles for Rank 0 -- DIMM ID", }, { .uname = "RANK5", .ucode = 0x2000, .udesc = "Throttle Cycles for Rank 0 -- DIMM ID", }, { .uname = "RANK6", .ucode = 0x4000, .udesc = "Throttle Cycles for Rank 0 -- DIMM ID", }, { .uname = "RANK7", .ucode = 0x8000, .udesc = "Throttle Cycles for Rank 0 -- DIMM ID", }, }; static intel_x86_umask_t bdx_unc_m_preemption[]={ { .uname = "RD_PREEMPT_RD", .ucode = 0x100, .udesc = "Read Preemption Count -- Read over Read Preemption", }, { .uname = "RD_PREEMPT_WR", .ucode = 0x200, .udesc = "Read Preemption Count -- Read over Write Preemption", }, }; static intel_x86_umask_t bdx_unc_m_pre_count[]={ { .uname = "BYP", .ucode = 0x1000, .udesc = "DRAM Precharge commands. -- Precharge due to bypass", }, { .uname = "PAGE_CLOSE", .ucode = 0x200, .udesc = "DRAM Precharge commands. -- Precharge due to timer expiration", }, { .uname = "PAGE_MISS", .ucode = 0x100, .udesc = "DRAM Precharge commands. -- Precharges due to page miss", }, { .uname = "RD", .ucode = 0x400, .udesc = "DRAM Precharge commands. -- Precharge due to read", }, { .uname = "WR", .ucode = 0x800, .udesc = "DRAM Precharge commands. -- Precharge due to write", }, }; static intel_x86_umask_t bdx_unc_m_rd_cas_prio[]={ { .uname = "HIGH", .ucode = 0x400, .udesc = "Read CAS issued with HIGH priority", }, { .uname = "LOW", .ucode = 0x100, .udesc = "Read CAS issued with LOW priority", }, { .uname = "MED", .ucode = 0x200, .udesc = "Read CAS issued with MEDIUM priority", }, { .uname = "PANIC", .ucode = 0x800, .udesc = "Read CAS issued with PANIC NON ISOCH priority (starved)", }, }; static intel_x86_umask_t bdx_unc_m_rd_cas_rank0[]={ { .uname = "ALLBANKS", .ucode = 0x1000, .udesc = "Access to Rank 0 -- All Banks", .uflags = INTEL_X86_NCOMBO, }, { .uname = "BANK0", .ucode = 0x0, .udesc = "Access to Rank 0 -- Bank 0", .uflags = INTEL_X86_NCOMBO, }, { .uname = "BANK1", .ucode = 0x100, .udesc = "Access to Rank 0 -- Bank 1", .uflags = INTEL_X86_NCOMBO, }, { .uname = "BANK10", .ucode = 0xa00, .udesc = "Access to Rank 0 -- Bank 10", .uflags = INTEL_X86_NCOMBO, }, { .uname = "BANK11", .ucode = 0xb00, .udesc = "Access to Rank 0 -- Bank 11", .uflags = INTEL_X86_NCOMBO, }, { .uname = "BANK12", .ucode = 0xc00, .udesc = "Access to Rank 0 -- Bank 12", .uflags = INTEL_X86_NCOMBO, }, { .uname = "BANK13", .ucode = 0xd00, .udesc = "Access to Rank 0 -- Bank 13", .uflags = INTEL_X86_NCOMBO, }, { .uname = "BANK14", .ucode = 0xe00, .udesc = "Access to Rank 0 -- Bank 14", .uflags = INTEL_X86_NCOMBO, }, { .uname = "BANK15", .ucode = 0xf00, .udesc = "Access to Rank 0 -- Bank 15", .uflags = INTEL_X86_NCOMBO, }, { .uname = "BANK2", .ucode = 0x200, .udesc = "Access to Rank 0 -- Bank 2", .uflags = INTEL_X86_NCOMBO, }, { .uname = "BANK3", .ucode = 0x300, .udesc = "Access to Rank 0 -- Bank 3", .uflags = INTEL_X86_NCOMBO, }, { .uname = "BANK4", .ucode = 0x400, .udesc = "Access to Rank 0 -- Bank 4", .uflags = INTEL_X86_NCOMBO, }, { .uname = "BANK5", .ucode = 0x500, .udesc = "Access to Rank 0 -- Bank 5", .uflags = INTEL_X86_NCOMBO, }, { .uname = "BANK6", .ucode = 0x600, .udesc = "Access to Rank 0 -- Bank 6", .uflags = INTEL_X86_NCOMBO, }, { .uname = "BANK7", .ucode = 0x700, .udesc = "Access to Rank 0 -- Bank 7", .uflags = INTEL_X86_NCOMBO, }, { .uname = "BANK8", .ucode = 0x800, .udesc = "Access to Rank 0 -- Bank 8", .uflags = INTEL_X86_NCOMBO, }, { .uname = "BANK9", .ucode = 0x900, .udesc = "Access to Rank 0 -- Bank 9", .uflags = INTEL_X86_NCOMBO, }, { .uname = "BANKG0", .ucode = 0x1100, .udesc = "Access to Rank 0 -- Bank Group 0 (Banks 0-3)", .uflags = INTEL_X86_NCOMBO, }, { .uname = "BANKG1", .ucode = 0x1200, .udesc = "Access to Rank 0 -- Bank Group 1 (Banks 4-7)", .uflags = INTEL_X86_NCOMBO, }, { .uname = "BANKG2", .ucode = 0x1300, .udesc = "Access to Rank 0 -- Bank Group 2 (Banks 8-11)", .uflags = INTEL_X86_NCOMBO, }, { .uname = "BANKG3", .ucode = 0x1400, .udesc = "Access to Rank 0 -- Bank Group 3 (Banks 12-15)", .uflags = INTEL_X86_NCOMBO, }, }; static intel_x86_umask_t bdx_unc_m_rd_cas_rank2[]={ { .uname = "BANK0", .ucode = 0x0, .udesc = "RD_CAS Access to Rank 2 -- Bank 0", .uflags = INTEL_X86_DFL, }, }; static intel_x86_umask_t bdx_unc_m_vmse_wr_push[]={ { .uname = "RMM", .ucode = 0x200, .udesc = "VMSE WR PUSH issued -- VMSE write PUSH issued in RMM", }, { .uname = "WMM", .ucode = 0x100, .udesc = "VMSE WR PUSH issued -- VMSE write PUSH issued in WMM", }, }; static intel_x86_umask_t bdx_unc_m_wmm_to_rmm[]={ { .uname = "LOW_THRESH", .ucode = 0x100, .udesc = "Transition from WMM to RMM because of low threshold -- Transition from WMM to RMM because of starve counter", }, { .uname = "STARVE", .ucode = 0x200, .udesc = "Transition from WMM to RMM because of low threshold -- ", }, { .uname = "VMSE_RETRY", .ucode = 0x400, .udesc = "Transition from WMM to RMM because of low threshold -- ", }, }; static intel_x86_entry_t intel_bdx_unc_m_pe[]={ { .name = "UNC_M_CLOCKTICKS", .desc = "IMC Uncore clockticks (fixed counter)", .modmsk = 0x0, .cntmsk = 0x100000000ull, .code = 0xff, /* perf pseudo encoding for fixed counter */ .flags = INTEL_X86_FIXED, }, { .name = "UNC_M_ACT_COUNT", .code = 0x1, .desc = "Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.", .modmsk = BDX_UNC_IMC_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_m_act_count, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_m_act_count), }, { .name = "UNC_M_BYP_CMDS", .code = 0xa1, .desc = "TBD", .modmsk = BDX_UNC_IMC_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_m_byp_cmds, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_m_byp_cmds), }, { .name = "UNC_M_CAS_COUNT", .code = 0x4, .desc = "DRAM RD_CAS and WR_CAS Commands", .modmsk = BDX_UNC_IMC_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_m_cas_count, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_m_cas_count), }, { .name = "UNC_M_DCLOCKTICKS", .code = 0x0, .desc = "TBD", .modmsk = BDX_UNC_IMC_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_M_DRAM_PRE_ALL", .code = 0x6, .desc = "Counts the number of times that the precharge all command was sent.", .modmsk = BDX_UNC_IMC_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_M_DRAM_REFRESH", .code = 0x5, .desc = "Counts the number of refreshes issued.", .modmsk = BDX_UNC_IMC_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_m_dram_refresh, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_m_dram_refresh), }, { .name = "UNC_M_ECC_CORRECTABLE_ERRORS", .code = 0x9, .desc = "Counts the number of ECC errors detected and corrected by the iMC on this channel. This counter is only useful with ECC DRAM devices. This count will increment one time for each correction regardless of the number of bits corrected. The iMC can correct up to 4 bit errors in independent channel mode and 8 bit erros in lockstep mode.", .modmsk = BDX_UNC_IMC_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_M_MAJOR_MODES", .code = 0x7, .desc = "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.", .modmsk = BDX_UNC_IMC_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_m_major_modes, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_m_major_modes), }, { .name = "UNC_M_POWER_CHANNEL_DLLOFF", .code = 0x84, .desc = "Number of cycles when all the ranks in the channel are in CKE Slow (DLLOFF) mode.", .modmsk = BDX_UNC_IMC_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_M_POWER_CHANNEL_PPD", .code = 0x85, .desc = "Number of cycles when all the ranks in the channel are in PPD mode. If IBT=off is enabled, then this can be used to count those cycles. If it is not enabled, then this can count the number of cycles when that could have been taken advantage of.", .modmsk = BDX_UNC_IMC_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_M_POWER_CKE_CYCLES", .code = 0x83, .desc = "Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).", .modmsk = BDX_UNC_IMC_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_m_power_cke_cycles, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_m_power_cke_cycles), }, { .name = "UNC_M_POWER_CRITICAL_THROTTLE_CYCLES", .code = 0x86, .desc = "Counts the number of cycles when the iMC is in critical thermal throttling. When this happens, all traffic is blocked. This should be rare unless something bad is going on in the platform. There is no filtering by rank for this event.", .modmsk = BDX_UNC_IMC_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_M_POWER_PCU_THROTTLING", .code = 0x42, .desc = "TBD", .modmsk = BDX_UNC_IMC_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_M_POWER_SELF_REFRESH", .code = 0x43, .desc = "Counts the number of cycles when the iMC is in self-refresh and the iMC still has a clock. This happens in some package C-states. For example, the PCU may ask the iMC to enter self-refresh even though some of the cores are still processing. One use of this is for Monroe technology. Self-refresh is required during package C3 and C6, but there is no clock in the iMC at this time, so it is not possible to count these cases.", .modmsk = BDX_UNC_IMC_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_M_POWER_THROTTLE_CYCLES", .code = 0x41, .desc = "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.", .modmsk = BDX_UNC_IMC_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_m_power_throttle_cycles, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_m_power_throttle_cycles), }, { .name = "UNC_M_PREEMPTION", .code = 0x8, .desc = "Counts the number of times a read in the iMC preempts another read or write. Generally reads to an open page are issued ahead of requests to closed pages. This improves the page hit rate of the system. However, high priority requests can cause pages of active requests to be closed in order to get them out. This will reduce the latency of the high-priority request at the expense of lower bandwidth and increased overall average latency.", .modmsk = BDX_UNC_IMC_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_m_preemption, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_m_preemption), }, { .name = "UNC_M_PRE_COUNT", .code = 0x2, .desc = "Counts the number of DRAM Precharge commands sent on this channel.", .modmsk = BDX_UNC_IMC_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_m_pre_count, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_m_pre_count), }, { .name = "UNC_M_RD_CAS_PRIO", .code = 0xa0, .desc = "TBD", .modmsk = BDX_UNC_IMC_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_m_rd_cas_prio, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_m_rd_cas_prio), }, { .name = "UNC_M_RD_CAS_RANK0", .code = 0xb0, .desc = "TBD", .modmsk = BDX_UNC_IMC_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_m_rd_cas_rank0, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_m_rd_cas_rank0), }, { .name = "UNC_M_RD_CAS_RANK1", .code = 0xb1, .desc = "TBD", .modmsk = BDX_UNC_IMC_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_m_rd_cas_rank0, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_m_rd_cas_rank0), /* shared */ }, { .name = "UNC_M_RD_CAS_RANK2", .code = 0xb2, .desc = "TBD", .modmsk = BDX_UNC_IMC_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_m_rd_cas_rank2, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_m_rd_cas_rank2), }, { .name = "UNC_M_RD_CAS_RANK4", .code = 0xb4, .desc = "TBD", .modmsk = BDX_UNC_IMC_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_m_rd_cas_rank0, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_m_rd_cas_rank0), /* shared */ }, { .name = "UNC_M_RD_CAS_RANK5", .code = 0xb5, .desc = "TBD", .modmsk = BDX_UNC_IMC_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_m_rd_cas_rank0, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_m_rd_cas_rank0), /* shared */ }, { .name = "UNC_M_RD_CAS_RANK6", .code = 0xb6, .desc = "TBD", .modmsk = BDX_UNC_IMC_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_m_rd_cas_rank0, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_m_rd_cas_rank0), /* shared */ }, { .name = "UNC_M_RD_CAS_RANK7", .code = 0xb7, .desc = "TBD", .modmsk = BDX_UNC_IMC_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_m_rd_cas_rank0, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_m_rd_cas_rank0), /* shared */ }, { .name = "UNC_M_RPQ_CYCLES_NE", .code = 0x11, .desc = "Counts the number of cycles that the Read Pending Queue is not empty. This can then be used to calculate the average occupancy (in conjunction with the Read Pending Queue Occupancy count). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This filter is to be used in conjunction with the occupancy filter so that one can correctly track the average occupancies for schedulable entries and scheduled requests.", .modmsk = BDX_UNC_IMC_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_M_RPQ_INSERTS", .code = 0x10, .desc = "Counts the number of allocations into the Read Pending Queue. This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This includes both ISOCH and non-ISOCH requests.", .modmsk = BDX_UNC_IMC_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_M_VMSE_MXB_WR_OCCUPANCY", .code = 0x91, .desc = "TBD", .modmsk = BDX_UNC_IMC_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_M_VMSE_WR_PUSH", .code = 0x90, .desc = "TBD", .modmsk = BDX_UNC_IMC_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_m_vmse_wr_push, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_m_vmse_wr_push), }, { .name = "UNC_M_WMM_TO_RMM", .code = 0xc0, .desc = "TBD", .modmsk = BDX_UNC_IMC_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_m_wmm_to_rmm, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_m_wmm_to_rmm), }, { .name = "UNC_M_WPQ_CYCLES_FULL", .code = 0x22, .desc = "Counts the number of cycles when the Write Pending Queue is full. When the WPQ is full, the HA will not be able to issue any additional read requests into the iMC. This count should be similar count in the HA which tracks the number of cycles that the HA has no WPQ credits, just somewhat smaller to account for the credit return overhead.", .modmsk = BDX_UNC_IMC_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_M_WPQ_CYCLES_NE", .code = 0x21, .desc = "Counts the number of cycles that the Write Pending Queue is not empty. This can then be used to calculate the average queue occupancy (in conjunction with the WPQ Occupancy Accumulation count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencieies.", .modmsk = BDX_UNC_IMC_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_M_WPQ_READ_HIT", .code = 0x23, .desc = "Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.", .modmsk = BDX_UNC_IMC_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_M_WPQ_WRITE_HIT", .code = 0x24, .desc = "Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.", .modmsk = BDX_UNC_IMC_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_M_WRONG_MM", .code = 0xc1, .desc = "TBD", .modmsk = BDX_UNC_IMC_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_M_WR_CAS_RANK0", .code = 0xb8, .desc = "TBD", .modmsk = BDX_UNC_IMC_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_m_rd_cas_rank0, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_m_rd_cas_rank0), }, { .name = "UNC_M_WR_CAS_RANK1", .code = 0xb9, .desc = "TBD", .modmsk = BDX_UNC_IMC_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_m_rd_cas_rank0, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_m_rd_cas_rank0), /* shared */ }, { .name = "UNC_M_WR_CAS_RANK4", .code = 0xbc, .desc = "TBD", .modmsk = BDX_UNC_IMC_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_m_rd_cas_rank0, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_m_rd_cas_rank0), /* shared */ }, { .name = "UNC_M_WR_CAS_RANK5", .code = 0xbd, .desc = "TBD", .modmsk = BDX_UNC_IMC_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_m_rd_cas_rank0, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_m_rd_cas_rank0), /* shared */ }, { .name = "UNC_M_WR_CAS_RANK6", .code = 0xbe, .desc = "TBD", .modmsk = BDX_UNC_IMC_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_m_rd_cas_rank0, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_m_rd_cas_rank0), /* shared */ }, { .name = "UNC_M_WR_CAS_RANK7", .code = 0xbf, .desc = "TBD", .modmsk = BDX_UNC_IMC_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_m_rd_cas_rank0, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_m_rd_cas_rank0), /* shared */ }, }; libpfm-4.9.0/lib/events/sparc_ultra3i_events.h0000664000175000017500000002412713223402656021206 0ustar eranianeranianstatic const sparc_entry_t ultra3i_pe[] = { /* These two must always be first. */ { .name = "Cycle_cnt", .desc = "Accumulated cycles", .ctrl = PME_CTRL_S0 | PME_CTRL_S1, .code = 0x0, }, { .name = "Instr_cnt", .desc = "Number of instructions completed", .ctrl = PME_CTRL_S0 | PME_CTRL_S1, .code = 0x1, }, /* PIC0 events common to all UltraSPARC processors */ { .name = "Dispatch0_IC_miss", .desc = "I-buffer is empty from I-Cache miss", .ctrl = PME_CTRL_S0, .code = 0x2, }, { .name = "IC_ref", .desc = "I-cache references", .ctrl = PME_CTRL_S0, .code = 0x8, }, { .name = "DC_rd", .desc = "D-cache read references (including accesses that subsequently trap)", .ctrl = PME_CTRL_S0, .code = 0x9, }, { .name = "DC_wr", .desc = "D-cache store accesses (including cacheable stores that subsequently trap)", .ctrl = PME_CTRL_S0, .code = 0xa, }, { .name = "EC_ref", .desc = "E-cache references", .ctrl = PME_CTRL_S0, .code = 0xc, }, { .name = "EC_snoop_inv", .desc = "L2-cache invalidates generated from a snoop by a remote processor", .ctrl = PME_CTRL_S0, .code = 0xe, }, /* PIC1 events common to all UltraSPARC processors */ { .name = "Dispatch0_mispred", .desc = "I-buffer is empty from Branch misprediction", .ctrl = PME_CTRL_S1, .code = 0x2, }, { .name = "EC_wb", .desc = "Dirty sub-blocks that produce writebacks due to L2-cache miss events", .ctrl = PME_CTRL_S1, .code = 0xd, }, { .name = "EC_snoop_cb", .desc = "L2-cache copybacks generated from a snoop by a remote processor", .ctrl = PME_CTRL_S1, .code = 0xe, }, /* PIC0 events common to all UltraSPARC-III/III+/IIIi processors */ { .name = "Dispatch0_br_target", .desc = "I-buffer is empty due to a branch target address calculation", .ctrl = PME_CTRL_S0, .code = 0x3, }, { .name = "Dispatch0_2nd_br", .desc = "Stall cycles due to having two branch instructions line-up in one 4-instruction group causing the second branch in the group to be re-fetched, delaying it's entrance into the I-buffer", .ctrl = PME_CTRL_S0, .code = 0x4, }, { .name = "Rstall_storeQ", .desc = "R-stage stall for a store instruction which is the next instruction to be executed, but it stalled due to the store queue being full", .ctrl = PME_CTRL_S0, .code = 0x5, }, { .name = "Rstall_IU_use", .desc = "R-stage stall for an event that the next instruction to be executed depends on the result of a preceding integer instruction in the pipeline that is not yet available", .ctrl = PME_CTRL_S0, .code = 0x6, }, { .name = "EC_write_hit_RTO", .desc = "W-cache exclusive requests that hit L2-cache in S, O, or Os state and thus, do a read-to-own bus transaction", .ctrl = PME_CTRL_S0, .code = 0xd, }, { .name = "EC_rd_miss", .desc = "L2-cache miss events (including atomics) from D-cache events", .ctrl = PME_CTRL_S0, .code = 0xf, }, { .name = "PC_port0_rd", .desc = "P-cache cacheable FP loads to the first port (general purpose load path to D-cache and P-cache via MS pipeline)", .ctrl = PME_CTRL_S0, .code = 0x10, }, { .name = "SI_snoop", .desc = "Counts snoops from remote processor(s) including RTS, RTSR, RTO, RTOR, RS, RSR, RTSM, and WS", .ctrl = PME_CTRL_S0, .code = 0x11, }, { .name = "SI_ciq_flow", .desc = "Counts system clock cycles when the flow control (PauseOut) signal is asserted", .ctrl = PME_CTRL_S0, .code = 0x12, }, { .name = "SI_owned", .desc = "Counts events where owned_in is asserted on bus requests from the local processor", .ctrl = PME_CTRL_S0, .code = 0x13, }, { .name = "SW_count0", .desc = "Counts software-generated occurrences of 'sethi %hi(0xfc000), %g0' instruction", .ctrl = PME_CTRL_S0, .code = 0x14, }, { .name = "IU_Stat_Br_miss_taken", .desc = "Retired branches that were predicted to be taken, but in fact were not taken", .ctrl = PME_CTRL_S0, .code = 0x15, }, { .name = "IU_Stat_Br_Count_taken", .desc = "Retired taken branches", .ctrl = PME_CTRL_S0, .code = 0x16, }, { .name = "Dispatch0_rs_mispred", .desc = "I-buffer is empty due to a Return Address Stack misprediction", .ctrl = PME_CTRL_S0, .code = 0x4, }, { .name = "FA_pipe_completion", .desc = "Instructions that complete execution on the FPG ALU pipelines", .ctrl = PME_CTRL_S0, .code = 0x18, }, /* PIC1 events common to all UltraSPARC-III/III+/IIIi processors */ { .name = "IC_miss_cancelled", .desc = "I-cache misses cancelled due to mis-speculation, recycle, or other events", .ctrl = PME_CTRL_S1, .code = 0x3, }, { .name = "Re_FPU_bypass", .desc = "Stall due to recirculation when an FPU bypass condition that does not have a direct bypass path occurs", .ctrl = PME_CTRL_S1, .code = 0x5, }, { .name = "Re_DC_miss", .desc = "Stall due to loads that miss D-cache and get recirculated", .ctrl = PME_CTRL_S1, .code = 0x6, }, { .name = "Re_EC_miss", .desc = "Stall due to loads that miss L2-cache and get recirculated", .ctrl = PME_CTRL_S1, .code = 0x7, }, { .name = "IC_miss", .desc = "I-cache misses, including fetches from mis-speculated execution paths which are later cancelled", .ctrl = PME_CTRL_S1, .code = 0x8, }, { .name = "DC_rd_miss", .desc = "Recirculated loads that miss the D-cache", .ctrl = PME_CTRL_S1, .code = 0x9, }, { .name = "DC_wr_miss", .desc = "D-cache store accesses that miss D-cache", .ctrl = PME_CTRL_S1, .code = 0xa, }, { .name = "Rstall_FP_use", .desc = "R-stage stall for an event that the next instruction to be executed depends on the result of a preceding floating-point instruction in the pipeline that is not yet available", .ctrl = PME_CTRL_S1, .code = 0xb, }, { .name = "EC_misses", .desc = "E-cache misses", .ctrl = PME_CTRL_S1, .code = 0xc, }, { .name = "EC_ic_miss", .desc = "L2-cache read misses from I-cache requests", .ctrl = PME_CTRL_S1, .code = 0xf, }, { .name = "Re_PC_miss", .desc = "Stall due to recirculation when a prefetch cache miss occurs on a prefetch predicted second load", .ctrl = PME_CTRL_S1, .code = 0x10, }, { .name = "ITLB_miss", .desc = "I-TLB miss traps taken", .ctrl = PME_CTRL_S1, .code = 0x11, }, { .name = "DTLB_miss", .desc = "Memory reference instructions which trap due to D-TLB miss", .ctrl = PME_CTRL_S1, .code = 0x12, }, { .name = "WC_miss", .desc = "W-cache misses", .ctrl = PME_CTRL_S1, .code = 0x13, }, { .name = "WC_snoop_cb", .desc = "W-cache copybacks generated by a snoop from a remote processor", .ctrl = PME_CTRL_S1, .code = 0x14, }, { .name = "WC_scrubbed", .desc = "W-cache hits to clean lines", .ctrl = PME_CTRL_S1, .code = 0x15, }, { .name = "WC_wb_wo_read", .desc = "W-cache writebacks not requiring a read", .ctrl = PME_CTRL_S1, .code = 0x16, }, { .name = "PC_soft_hit", .desc = "FP loads that hit a P-cache line that was prefetched by a software-prefetch instruction", .ctrl = PME_CTRL_S1, .code = 0x18, }, { .name = "PC_snoop_inv", .desc = "P-cache invalidates that were generated by a snoop from a remote processor and stores by a local processor", .ctrl = PME_CTRL_S1, .code = 0x19, }, { .name = "PC_hard_hit", .desc = "FP loads that hit a P-cache line that was prefetched by a hardware prefetch", .ctrl = PME_CTRL_S1, .code = 0x1a, }, { .name = "PC_port1_rd", .desc = "P-cache cacheable FP loads to the second port (memory and out-of-pipeline instruction execution loads via the A0 and A1 pipelines)", .ctrl = PME_CTRL_S1, .code = 0x1b, }, { .name = "SW_count1", .desc = "Counts software-generated occurrences of 'sethi %hi(0xfc000), %g0' instruction", .ctrl = PME_CTRL_S1, .code = 0x1c, }, { .name = "IU_Stat_Br_miss_untaken", .desc = "Retired branches that were predicted to be untaken, but in fact were taken", .ctrl = PME_CTRL_S1, .code = 0x1d, }, { .name = "IU_Stat_Br_Count_untaken", .desc = "Retired untaken branches", .ctrl = PME_CTRL_S1, .code = 0x1e, }, { .name = "PC_MS_miss", .desc = "FP loads through the MS pipeline that miss P-cache", .ctrl = PME_CTRL_S1, .code = 0x1f, }, { .name = "Re_RAW_miss", .desc = "Stall due to recirculation when there is a load in the E-stage which has a non-bypassable read-after-write hazard with an earlier store instruction", .ctrl = PME_CTRL_S1, .code = 0x26, }, { .name = "FM_pipe_completion", .desc = "Instructions that complete execution on the FPG Multiply pipelines", .ctrl = PME_CTRL_S0, .code = 0x27, }, /* PIC0 memory controller events specific to UltraSPARC-IIIi processors */ { .name = "MC_read_dispatched", .desc = "DDR 64-byte reads dispatched by the MIU", .ctrl = PME_CTRL_S0, .code = 0x20, }, { .name = "MC_write_dispatched", .desc = "DDR 64-byte writes dispatched by the MIU", .ctrl = PME_CTRL_S0, .code = 0x21, }, { .name = "MC_read_returned_to_JBU", .desc = "64-byte reads that return data to JBU", .ctrl = PME_CTRL_S0, .code = 0x22, }, { .name = "MC_msl_busy_stall", .desc = "Stall cycles due to msl_busy", .ctrl = PME_CTRL_S0, .code = 0x23, }, { .name = "MC_mdb_overflow_stall", .desc = "Stall cycles due to potential memory data buffer overflow", .ctrl = PME_CTRL_S0, .code = 0x24, }, { .name = "MC_miu_spec_request", .desc = "Speculative requests accepted by MIU", .ctrl = PME_CTRL_S0, .code = 0x25, }, /* PIC1 memory controller events specific to UltraSPARC-IIIi processors */ { .name = "MC_reads", .desc = "64-byte reads by the MSL", .ctrl = PME_CTRL_S1, .code = 0x20, }, { .name = "MC_writes", .desc = "64-byte writes by the MSL", .ctrl = PME_CTRL_S1, .code = 0x21, }, { .name = "MC_page_close_stall", .desc = "DDR page conflicts", .ctrl = PME_CTRL_S1, .code = 0x22, }, /* PIC1 events specific to UltraSPARC-III+/IIIi */ { .name = "Re_DC_missovhd", .desc = "Used to measure D-cache stall counts separately for L2-cache hits and misses. This counter is used with the recirculation and cache access events to separately calculate the D-cache loads that hit and miss the L2-cache", .ctrl = PME_CTRL_S1, .code = 0x4, }, }; #define PME_SPARC_ULTRA3I_EVENT_COUNT (sizeof(ultra3i_pe)/sizeof(sparc_entry_t)) libpfm-4.9.0/lib/events/intel_knl_unc_m2pcie_events.h0000664000175000017500000001017613223402656022515 0ustar eranianeranian/* * Copyright (c) 2016 Intel Corp. All rights reserved * Contributed by Peinan Zhang * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * PMU: knl_unc_m2pcie (Intel Knights Landing M2PCIe uncore) */ static const intel_x86_umask_t knl_unc_m2p_ingress_cycles_ne[]={ { .uname = "CBO_IDI", .udesc = "CBO_IDI", .ucode = 0x0100, }, { .uname = "CBO_NCB", .udesc = "CBO_NCB", .ucode = 0x0200, }, { .uname = "CBO_NCS", .udesc = "CBO_NCS", .ucode = 0x0400, }, { .uname = "ALL", .udesc = "All", .ucode = 0x0800, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t knl_unc_m2p_egress_cycles[]={ { .uname = "AD_0", .udesc = "AD_0", .ucode = 0x0100, }, { .uname = "AK_0", .udesc = "AK_0", .ucode = 0x0200, }, { .uname = "BL_0", .udesc = "BL_0", .ucode = 0x0400, }, { .uname = "AD_1", .udesc = "AD_1", .ucode = 0x0800, }, { .uname = "AK_1", .udesc = "AK_1", .ucode = 0x1000, }, { .uname = "BL_1", .udesc = "BL_1", .ucode = 0x2000, }, }; static const intel_x86_umask_t knl_unc_m2p_egress_inserts[]={ { .uname = "AD_0", .udesc = "AD_0", .ucode = 0x0100, }, { .uname = "AK_0", .udesc = "AK_0", .ucode = 0x0200, }, { .uname = "BL_0", .udesc = "BL_0", .ucode = 0x0400, }, { .uname = "AK_CRD_0", .udesc = "AK_CRD_0", .ucode = 0x0800, }, { .uname = "AD_1", .udesc = "AD_1", .ucode = 0x1000, }, { .uname = "AK_1", .udesc = "AK_1", .ucode = 0x2000, }, { .uname = "BL_1", .udesc = "BL_1", .ucode = 0x4000, }, { .uname = "AK_CRD_1", .udesc = "AK_CRD_1", .ucode = 0x8000, }, }; static const intel_x86_entry_t intel_knl_unc_m2pcie_pe[]={ { .name = "UNC_M2P_INGRESS_CYCLES_NE", .desc = "Ingress Queue Cycles Not Empty. Counts the number of cycles when the M2PCIe Ingress is not empty", .code = 0x10, .cntmsk = 0xf, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_m2p_ingress_cycles_ne), .umasks = knl_unc_m2p_ingress_cycles_ne }, { .name = "UNC_M2P_EGRESS_CYCLES_NE", .desc = "Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty", .code = 0x23, .cntmsk = 0x3, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_m2p_egress_cycles), .umasks = knl_unc_m2p_egress_cycles }, { .name = "UNC_M2P_EGRESS_INSERTS", .desc = "Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue", .code = 0x24, .cntmsk = 0xf, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_m2p_egress_inserts), .umasks = knl_unc_m2p_egress_inserts }, { .name = "UNC_M2P_EGRESS_CYCLES_FULL", .desc = "Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full", .code = 0x25, .cntmsk = 0xf, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_m2p_egress_cycles), .umasks = knl_unc_m2p_egress_cycles }, }; libpfm-4.9.0/lib/events/amd64_events_fam15h_nb.h0000664000175000017500000011560213223402656021165 0ustar eranianeranian/* * Copyright (c) 2013 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * This file has been automatically generated. * * PMU: amd64_fam15h_nb_nb (AMD64 Fam15h Interlagos NorthBridge) * * Based on libpfm patch by Robert Richter : * Family 15h Microarchitecture performance monitor events * * History: * * Nov 30 2013 -- Stephane Eranian , eranian@gmail.com: * Split core and Northbridge events as PMU is distinct * * Apr 29 2011 -- Robert Richter, robert.richter@amd.com: * Source: BKDG for AMD Family 15h Models 00h-0Fh Processors, * 42301, Rev 1.15, April 18, 2011 * * Dec 09 2010 -- Robert Richter, robert.richter@amd.com: * Source: BIOS and Kernel Developer's Guide for the AMD Family 15h * Processors, Rev 0.90, May 18, 2010 */ #define CORE_SELECT(b) \ { .uname = "CORE_0",\ .udesc = "Measure on Core0",\ .ucode = 0 << 4,\ .grpid = b,\ .uflags= AMD64_FL_NCOMBO,\ },\ { .uname = "CORE_1",\ .udesc = "Measure on Core1",\ .ucode = 1 << 4,\ .grpid = b,\ .uflags= AMD64_FL_NCOMBO,\ },\ { .uname = "CORE_2",\ .udesc = "Measure on Core2",\ .ucode = 2 << 4,\ .grpid = b,\ .uflags= AMD64_FL_NCOMBO,\ },\ { .uname = "CORE_3",\ .udesc = "Measure on Core3",\ .ucode = 3 << 4,\ .grpid = b,\ .uflags= AMD64_FL_NCOMBO,\ },\ { .uname = "CORE_4",\ .udesc = "Measure on Core4",\ .ucode = 4 << 4,\ .grpid = b,\ .uflags= AMD64_FL_NCOMBO,\ },\ { .uname = "CORE_5",\ .udesc = "Measure on Core5",\ .ucode = 5 << 4,\ .grpid = b,\ .uflags= AMD64_FL_NCOMBO,\ },\ { .uname = "CORE_6",\ .udesc = "Measure on Core6",\ .ucode = 6 << 4,\ .grpid = b,\ .uflags= AMD64_FL_NCOMBO,\ },\ { .uname = "CORE_7",\ .udesc = "Measure on Core7",\ .ucode = 7 << 4,\ .grpid = b,\ .uflags= AMD64_FL_NCOMBO,\ },\ { .uname = "ANY_CORE",\ .udesc = "Measure on any core",\ .ucode = 0xf << 4,\ .grpid = b,\ .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,\ } static const amd64_umask_t amd64_fam15h_nb_dram_accesses[]={ { .uname = "DCT0_PAGE_HIT", .udesc = "DCT0 Page hit", .ucode = 0x1, }, { .uname = "DCT0_PAGE_MISS", .udesc = "DCT0 Page Miss", .ucode = 0x2, }, { .uname = "DCT0_PAGE_CONFLICT", .udesc = "DCT0 Page Conflict", .ucode = 0x4, }, { .uname = "DCT1_PAGE_HIT", .udesc = "DCT1 Page hit", .ucode = 0x8, }, { .uname = "DCT1_PAGE_MISS", .udesc = "DCT1 Page Miss", .ucode = 0x10, }, { .uname = "DCT1_PAGE_CONFLICT", .udesc = "DCT1 Page Conflict", .ucode = 0x20, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam15h_nb_dram_controller_page_table_overflows[]={ { .uname = "DCT0_PAGE_TABLE_OVERFLOW", .udesc = "DCT0 Page Table Overflow", .ucode = 0x1, }, { .uname = "DCT1_PAGE_TABLE_OVERFLOW", .udesc = "DCT1 Page Table Overflow", .ucode = 0x2, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3, .uflags = AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam15h_nb_memory_controller_dram_command_slots_missed[]={ { .uname = "DCT0_COMMAND_SLOTS_MISSED", .udesc = "DCT0 Command Slots Missed (in MemClks)", .ucode = 0x1, }, { .uname = "DCT1_COMMAND_SLOTS_MISSED", .udesc = "DCT1 Command Slots Missed (in MemClks)", .ucode = 0x2, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3, .uflags = AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam15h_nb_memory_controller_turnarounds[]={ { .uname = "DCT0_DIMM_TURNAROUND", .udesc = "DCT0 DIMM (chip select) turnaround", .ucode = 0x1, }, { .uname = "DCT0_READ_WRITE_TURNAROUND", .udesc = "DCT0 Read to write turnaround", .ucode = 0x2, }, { .uname = "DCT0_WRITE_READ_TURNAROUND", .udesc = "DCT0 Write to read turnaround", .ucode = 0x4, }, { .uname = "DCT1_DIMM_TURNAROUND", .udesc = "DCT1 DIMM (chip select) turnaround", .ucode = 0x8, }, { .uname = "DCT1_READ_WRITE_TURNAROUND", .udesc = "DCT1 Read to write turnaround", .ucode = 0x10, }, { .uname = "DCT1_WRITE_READ_TURNAROUND", .udesc = "DCT1 Write to read turnaround", .ucode = 0x20, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3f, .uflags = AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam15h_nb_memory_controller_bypass_counter_saturation[]={ { .uname = "MEMORY_CONTROLLER_HIGH_PRIORITY_BYPASS", .udesc = "Memory controller high priority bypass", .ucode = 0x1, }, { .uname = "MEMORY_CONTROLLER_MEDIUM_PRIORITY_BYPASS", .udesc = "Memory controller medium priority bypass", .ucode = 0x2, }, { .uname = "DCT0_DCQ_BYPASS", .udesc = "DCT0 DCQ bypass", .ucode = 0x4, }, { .uname = "DCT1_DCQ_BYPASS", .udesc = "DCT1 DCQ bypass", .ucode = 0x8, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xf, .uflags = AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam15h_nb_thermal_status[]={ { .uname = "NUM_HTC_TRIP_POINT_CROSSED", .udesc = "Number of times the HTC trip point is crossed", .ucode = 0x4, }, { .uname = "NUM_CLOCKS_HTC_PSTATE_INACTIVE", .udesc = "Number of clocks HTC P-state is inactive", .ucode = 0x20, }, { .uname = "NUM_CLOCKS_HTC_PSTATE_ACTIVE", .udesc = "Number of clocks HTC P-state is active", .ucode = 0x40, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x64, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam15h_nb_cpu_io_requests_to_memory_io[]={ { .uname = "REMOTE_IO_TO_LOCAL_IO", .udesc = "Remote IO to Local IO", .ucode = 0x61, .uflags= AMD64_FL_NCOMBO, }, { .uname = "REMOTE_CPU_TO_LOCAL_IO", .udesc = "Remote CPU to Local IO", .ucode = 0x64, .uflags= AMD64_FL_NCOMBO, }, { .uname = "LOCAL_IO_TO_REMOTE_IO", .udesc = "Local IO to Remote IO", .ucode = 0x91, .uflags= AMD64_FL_NCOMBO, }, { .uname = "LOCAL_IO_TO_REMOTE_MEM", .udesc = "Local IO to Remote Mem", .ucode = 0x92, .uflags= AMD64_FL_NCOMBO, }, { .uname = "LOCAL_CPU_TO_REMOTE_IO", .udesc = "Local CPU to Remote IO", .ucode = 0x94, .uflags= AMD64_FL_NCOMBO, }, { .uname = "LOCAL_CPU_TO_REMOTE_MEM", .udesc = "Local CPU to Remote Mem", .ucode = 0x98, .uflags= AMD64_FL_NCOMBO, }, { .uname = "LOCAL_IO_TO_LOCAL_IO", .udesc = "Local IO to Local IO", .ucode = 0xa1, .uflags= AMD64_FL_NCOMBO, }, { .uname = "LOCAL_IO_TO_LOCAL_MEM", .udesc = "Local IO to Local Mem", .ucode = 0xa2, .uflags= AMD64_FL_NCOMBO, }, { .uname = "LOCAL_CPU_TO_LOCAL_IO", .udesc = "Local CPU to Local IO", .ucode = 0xa4, .uflags= AMD64_FL_NCOMBO, }, { .uname = "LOCAL_CPU_TO_LOCAL_MEM", .udesc = "Local CPU to Local Mem", .ucode = 0xa8, .uflags= AMD64_FL_NCOMBO, }, }; static const amd64_umask_t amd64_fam15h_nb_cache_block_commands[]={ { .uname = "VICTIM_BLOCK", .udesc = "Victim Block (Writeback)", .ucode = 0x1, }, { .uname = "READ_BLOCK", .udesc = "Read Block (Dcache load miss refill)", .ucode = 0x4, }, { .uname = "READ_BLOCK_SHARED", .udesc = "Read Block Shared (Icache refill)", .ucode = 0x8, }, { .uname = "READ_BLOCK_MODIFIED", .udesc = "Read Block Modified (Dcache store miss refill)", .ucode = 0x10, }, { .uname = "CHANGE_TO_DIRTY", .udesc = "Change-to-Dirty (first store to clean block already in cache)", .ucode = 0x20, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3d, .uflags = AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam15h_nb_sized_commands[]={ { .uname = "NON-POSTED_SZWR_BYTE", .udesc = "Non-Posted SzWr Byte (1-32 bytes). Typical Usage: Legacy or mapped IO, typically 1-4 bytes.", .ucode = 0x1, }, { .uname = "NON-POSTED_SZWR_DW", .udesc = "Non-Posted SzWr DW (1-16 dwords). Typical Usage: Legacy or mapped IO, typically 1", .ucode = 0x2, }, { .uname = "POSTED_SZWR_BYTE", .udesc = "Posted SzWr Byte (1-32 bytes). Typical Usage: Subcache-line DMA writes, size varies; also", .ucode = 0x4, }, { .uname = "POSTED_SZWR_DW", .udesc = "Posted SzWr DW (1-16 dwords). Typical Usage: Block-oriented DMA writes, often cache-line", .ucode = 0x8, }, { .uname = "SZRD_BYTE", .udesc = "SzRd Byte (4 bytes). Typical Usage: Legacy or mapped IO.", .ucode = 0x10, }, { .uname = "SZRD_DW", .udesc = "SzRd DW (1-16 dwords). Typical Usage: Block-oriented DMA reads, typically cache-line size.", .ucode = 0x20, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam15h_nb_probe_responses_and_upstream_requests[]={ { .uname = "PROBE_MISS", .udesc = "Probe miss", .ucode = 0x1, }, { .uname = "PROBE_HIT_CLEAN", .udesc = "Probe hit clean", .ucode = 0x2, }, { .uname = "PROBE_HIT_DIRTY_WITHOUT_MEMORY_CANCEL", .udesc = "Probe hit dirty without memory cancel (probed by Sized Write or Change2Dirty)", .ucode = 0x4, }, { .uname = "PROBE_HIT_DIRTY_WITH_MEMORY_CANCEL", .udesc = "Probe hit dirty with memory cancel (probed by DMA read or cache refill request)", .ucode = 0x8, }, { .uname = "UPSTREAM_DISPLAY_REFRESH_ISOC_READS", .udesc = "Upstream display refresh/ISOC reads", .ucode = 0x10, }, { .uname = "UPSTREAM_NON-DISPLAY_REFRESH_READS", .udesc = "Upstream non-display refresh reads", .ucode = 0x20, }, { .uname = "UPSTREAM_ISOC_WRITES", .udesc = "Upstream ISOC writes", .ucode = 0x40, }, { .uname = "UPSTREAM_NON-ISOC_WRITES", .udesc = "Upstream non-ISOC writes", .ucode = 0x80, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xff, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam15h_nb_gart_events[]={ { .uname = "GART_APERTURE_HIT_ON_ACCESS_FROM_CPU", .udesc = "GART aperture hit on access from CPU", .ucode = 0x1, }, { .uname = "GART_APERTURE_HIT_ON_ACCESS_FROM_IO", .udesc = "GART aperture hit on access from IO", .ucode = 0x2, }, { .uname = "GART_MISS", .udesc = "GART miss", .ucode = 0x4, }, { .uname = "GART_REQUEST_HIT_TABLE_WALK_IN_PROGRESS", .udesc = "GART Request hit table walk in progress", .ucode = 0x8, }, { .uname = "GART_MULTIPLE_TABLE_WALK_IN_PROGRESS", .udesc = "GART multiple table walk in progress", .ucode = 0x80, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x8f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam15h_nb_link_transmit_bandwidth[]={ { .uname = "COMMAND_DW_SENT", .udesc = "Command DW sent", .ucode = 0x1, .grpid = 0, }, { .uname = "DATA_DW_SENT", .udesc = "Data DW sent", .ucode = 0x2, .grpid = 0, }, { .uname = "BUFFER_RELEASE_DW_SENT", .udesc = "Buffer release DW sent", .ucode = 0x4, .grpid = 0, }, { .uname = "NOP_DW_SENT", .udesc = "NOP DW sent (idle)", .ucode = 0x8, .grpid = 0, }, { .uname = "ADDRESS_DW_SENT", .udesc = "Address (including extensions) DW sent", .ucode = 0x10, .grpid = 0, }, { .uname = "PER_PACKET_CRC_SENT", .udesc = "Per packet CRC sent", .ucode = 0x20, .grpid = 0, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, .grpid = 0, }, { .uname = "SUBLINK_1", .udesc = "When links are unganged, enable this umask to select sublink 1", .ucode = 0x80, .grpid = 1, .uflags= AMD64_FL_NCOMBO, }, { .uname = "SUBLINK_0", .udesc = "When links are unganged, enable this umask to select sublink 0 (default when links ganged)", .ucode = 0x00, .grpid = 1, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam15h_nb_cpu_to_dram_requests_to_target_node[]={ { .uname = "LOCAL_TO_NODE_0", .udesc = "From Local node to Node 0", .ucode = 0x1, }, { .uname = "LOCAL_TO_NODE_1", .udesc = "From Local node to Node 1", .ucode = 0x2, }, { .uname = "LOCAL_TO_NODE_2", .udesc = "From Local node to Node 2", .ucode = 0x4, }, { .uname = "LOCAL_TO_NODE_3", .udesc = "From Local node to Node 3", .ucode = 0x8, }, { .uname = "LOCAL_TO_NODE_4", .udesc = "From Local node to Node 4", .ucode = 0x10, }, { .uname = "LOCAL_TO_NODE_5", .udesc = "From Local node to Node 5", .ucode = 0x20, }, { .uname = "LOCAL_TO_NODE_6", .udesc = "From Local node to Node 6", .ucode = 0x40, }, { .uname = "LOCAL_TO_NODE_7", .udesc = "From Local node to Node 7", .ucode = 0x80, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xff, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam15h_nb_io_to_dram_requests_to_target_node[]={ { .uname = "LOCAL_TO_NODE_0", .udesc = "From Local node to Node 0", .ucode = 0x1, }, { .uname = "LOCAL_TO_NODE_1", .udesc = "From Local node to Node 1", .ucode = 0x2, }, { .uname = "LOCAL_TO_NODE_2", .udesc = "From Local node to Node 2", .ucode = 0x4, }, { .uname = "LOCAL_TO_NODE_3", .udesc = "From Local node to Node 3", .ucode = 0x8, }, { .uname = "LOCAL_TO_NODE_4", .udesc = "From Local node to Node 4", .ucode = 0x10, }, { .uname = "LOCAL_TO_NODE_5", .udesc = "From Local node to Node 5", .ucode = 0x20, }, { .uname = "LOCAL_TO_NODE_6", .udesc = "From Local node to Node 6", .ucode = 0x40, }, { .uname = "LOCAL_TO_NODE_7", .udesc = "From Local node to Node 7", .ucode = 0x80, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xff, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam15h_nb_cpu_read_command_requests_to_target_node_0_3[]={ { .uname = "READ_BLOCK_LOCAL_TO_NODE_0", .udesc = "Read block From Local node to Node 0", .ucode = 0x11, .uflags= AMD64_FL_NCOMBO, }, { .uname = "READ_BLOCK_SHARED_LOCAL_TO_NODE_0", .udesc = "Read block shared From Local node to Node 0", .ucode = 0x12, .uflags= AMD64_FL_NCOMBO, }, { .uname = "READ_BLOCK_MODIFIED_LOCAL_TO_NODE_0", .udesc = "Read block modified From Local node to Node 0", .ucode = 0x14, .uflags= AMD64_FL_NCOMBO, }, { .uname = "CHANGE_TO_DIRTY_LOCAL_TO_NODE_0", .udesc = "Change-to-Dirty From Local node to Node 0", .ucode = 0x18, .uflags= AMD64_FL_NCOMBO, }, { .uname = "READ_BLOCK_LOCAL_TO_NODE_1", .udesc = "Read block From Local node to Node 1", .ucode = 0x21, .uflags= AMD64_FL_NCOMBO, }, { .uname = "READ_BLOCK_SHARED_LOCAL_TO_NODE_1", .udesc = "Read block shared From Local node to Node 1", .ucode = 0x22, .uflags= AMD64_FL_NCOMBO, }, { .uname = "READ_BLOCK_MODIFIED_LOCAL_TO_NODE_1", .udesc = "Read block modified From Local node to Node 1", .ucode = 0x24, .uflags= AMD64_FL_NCOMBO, }, { .uname = "CHANGE_TO_DIRTY_LOCAL_TO_NODE_1", .udesc = "Change-to-Dirty From Local node to Node 1", .ucode = 0x28, .uflags= AMD64_FL_NCOMBO, }, { .uname = "READ_BLOCK_LOCAL_TO_NODE_2", .udesc = "Read block From Local node to Node 2", .ucode = 0x41, .uflags= AMD64_FL_NCOMBO, }, { .uname = "READ_BLOCK_SHARED_LOCAL_TO_NODE_2", .udesc = "Read block shared From Local node to Node 2", .ucode = 0x42, .uflags= AMD64_FL_NCOMBO, }, { .uname = "READ_BLOCK_MODIFIED_LOCAL_TO_NODE_2", .udesc = "Read block modified From Local node to Node 2", .ucode = 0x44, .uflags= AMD64_FL_NCOMBO, }, { .uname = "CHANGE_TO_DIRTY_LOCAL_TO_NODE_2", .udesc = "Change-to-Dirty From Local node to Node 2", .ucode = 0x48, .uflags= AMD64_FL_NCOMBO, }, { .uname = "READ_BLOCK_LOCAL_TO_NODE_3", .udesc = "Read block From Local node to Node 3", .ucode = 0x81, .uflags= AMD64_FL_NCOMBO, }, { .uname = "READ_BLOCK_SHARED_LOCAL_TO_NODE_3", .udesc = "Read block shared From Local node to Node 3", .ucode = 0x82, .uflags= AMD64_FL_NCOMBO, }, { .uname = "READ_BLOCK_MODIFIED_LOCAL_TO_NODE_3", .udesc = "Read block modified From Local node to Node 3", .ucode = 0x84, .uflags= AMD64_FL_NCOMBO, }, { .uname = "CHANGE_TO_DIRTY_LOCAL_TO_NODE_3", .udesc = "Change-to-Dirty From Local node to Node 3", .ucode = 0x88, .uflags= AMD64_FL_NCOMBO, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xff, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam15h_nb_cpu_read_command_requests_to_target_node_4_7[]={ { .uname = "READ_BLOCK_LOCAL_TO_NODE_4", .udesc = "Read block From Local node to Node 4", .ucode = 0x11, .uflags= AMD64_FL_NCOMBO, }, { .uname = "READ_BLOCK_SHARED_LOCAL_TO_NODE_4", .udesc = "Read block shared From Local node to Node 4", .ucode = 0x12, .uflags= AMD64_FL_NCOMBO, }, { .uname = "READ_BLOCK_MODIFIED_LOCAL_TO_NODE_4", .udesc = "Read block modified From Local node to Node 4", .ucode = 0x14, .uflags= AMD64_FL_NCOMBO, }, { .uname = "CHANGE_TO_DIRTY_LOCAL_TO_NODE_4", .udesc = "Change-to-Dirty From Local node to Node 4", .ucode = 0x18, .uflags= AMD64_FL_NCOMBO, }, { .uname = "READ_BLOCK_LOCAL_TO_NODE_5", .udesc = "Read block From Local node to Node 5", .ucode = 0x21, .uflags= AMD64_FL_NCOMBO, }, { .uname = "READ_BLOCK_SHARED_LOCAL_TO_NODE_5", .udesc = "Read block shared From Local node to Node 5", .ucode = 0x22, .uflags= AMD64_FL_NCOMBO, }, { .uname = "READ_BLOCK_MODIFIED_LOCAL_TO_NODE_5", .udesc = "Read block modified From Local node to Node 5", .ucode = 0x24, .uflags= AMD64_FL_NCOMBO, }, { .uname = "CHANGE_TO_DIRTY_LOCAL_TO_NODE_5", .udesc = "Change-to-Dirty From Local node to Node 5", .ucode = 0x28, .uflags= AMD64_FL_NCOMBO, }, { .uname = "READ_BLOCK_LOCAL_TO_NODE_6", .udesc = "Read block From Local node to Node 6", .ucode = 0x41, .uflags= AMD64_FL_NCOMBO, }, { .uname = "READ_BLOCK_SHARED_LOCAL_TO_NODE_6", .udesc = "Read block shared From Local node to Node 6", .ucode = 0x42, .uflags= AMD64_FL_NCOMBO, }, { .uname = "READ_BLOCK_MODIFIED_LOCAL_TO_NODE_6", .udesc = "Read block modified From Local node to Node 6", .ucode = 0x44, .uflags= AMD64_FL_NCOMBO, }, { .uname = "CHANGE_TO_DIRTY_LOCAL_TO_NODE_6", .udesc = "Change-to-Dirty From Local node to Node 6", .ucode = 0x48, .uflags= AMD64_FL_NCOMBO, }, { .uname = "READ_BLOCK_LOCAL_TO_NODE_7", .udesc = "Read block From Local node to Node 7", .ucode = 0x81, .uflags= AMD64_FL_NCOMBO, }, { .uname = "READ_BLOCK_SHARED_LOCAL_TO_NODE_7", .udesc = "Read block shared From Local node to Node 7", .ucode = 0x82, .uflags= AMD64_FL_NCOMBO, }, { .uname = "READ_BLOCK_MODIFIED_LOCAL_TO_NODE_7", .udesc = "Read block modified From Local node to Node 7", .ucode = 0x84, .uflags= AMD64_FL_NCOMBO, }, { .uname = "CHANGE_TO_DIRTY_LOCAL_TO_NODE_7", .udesc = "Change-to-Dirty From Local node to Node 7", .ucode = 0x88, .uflags= AMD64_FL_NCOMBO, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xff, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam15h_nb_cpu_command_requests_to_target_node[]={ { .uname = "READ_SIZED_LOCAL_TO_NODE_0", .udesc = "Read Sized From Local node to Node 0", .ucode = 0x11, .uflags= AMD64_FL_NCOMBO, }, { .uname = "WRITE_SIZED_LOCAL_TO_NODE_0", .udesc = "Write Sized From Local node to Node 0", .ucode = 0x12, .uflags= AMD64_FL_NCOMBO, }, { .uname = "VICTIM_BLOCK_LOCAL_TO_NODE_0", .udesc = "Victim Block From Local node to Node 0", .ucode = 0x14, .uflags= AMD64_FL_NCOMBO, }, { .uname = "READ_SIZED_LOCAL_TO_NODE_1", .udesc = "Read Sized From Local node to Node 1", .ucode = 0x21, .uflags= AMD64_FL_NCOMBO, }, { .uname = "WRITE_SIZED_LOCAL_TO_NODE_1", .udesc = "Write Sized From Local node to Node 1", .ucode = 0x22, .uflags= AMD64_FL_NCOMBO, }, { .uname = "VICTIM_BLOCK_LOCAL_TO_NODE_1", .udesc = "Victim Block From Local node to Node 1", .ucode = 0x24, .uflags= AMD64_FL_NCOMBO, }, { .uname = "READ_SIZED_LOCAL_TO_NODE_2", .udesc = "Read Sized From Local node to Node 2", .ucode = 0x41, .uflags= AMD64_FL_NCOMBO, }, { .uname = "WRITE_SIZED_LOCAL_TO_NODE_2", .udesc = "Write Sized From Local node to Node 2", .ucode = 0x42, .uflags= AMD64_FL_NCOMBO, }, { .uname = "VICTIM_BLOCK_LOCAL_TO_NODE_2", .udesc = "Victim Block From Local node to Node 2", .ucode = 0x44, .uflags= AMD64_FL_NCOMBO, }, { .uname = "READ_SIZED_LOCAL_TO_NODE_3", .udesc = "Read Sized From Local node to Node 3", .ucode = 0x81, .uflags= AMD64_FL_NCOMBO, }, { .uname = "WRITE_SIZED_LOCAL_TO_NODE_3", .udesc = "Write Sized From Local node to Node 3", .ucode = 0x82, .uflags= AMD64_FL_NCOMBO, }, { .uname = "VICTIM_BLOCK_LOCAL_TO_NODE_3", .udesc = "Victim Block From Local node to Node 3", .ucode = 0x84, .uflags= AMD64_FL_NCOMBO, }, { .uname = "READ_SIZED_LOCAL_TO_NODE_4", .udesc = "Read Sized From Local node to Node 4", .ucode = 0x19, .uflags= AMD64_FL_NCOMBO, }, { .uname = "WRITE_SIZED_LOCAL_TO_NODE_4", .udesc = "Write Sized From Local node to Node 4", .ucode = 0x1a, .uflags= AMD64_FL_NCOMBO, }, { .uname = "VICTIM_BLOCK_LOCAL_TO_NODE_4", .udesc = "Victim Block From Local node to Node 4", .ucode = 0x1c, .uflags= AMD64_FL_NCOMBO, }, { .uname = "READ_SIZED_LOCAL_TO_NODE_5", .udesc = "Read Sized From Local node to Node 5", .ucode = 0x29, .uflags= AMD64_FL_NCOMBO, }, { .uname = "WRITE_SIZED_LOCAL_TO_NODE_5", .udesc = "Write Sized From Local node to Node 5", .ucode = 0x2a, .uflags= AMD64_FL_NCOMBO, }, { .uname = "VICTIM_BLOCK_LOCAL_TO_NODE_5", .udesc = "Victim Block From Local node to Node 5", .ucode = 0x2c, .uflags= AMD64_FL_NCOMBO, }, { .uname = "READ_SIZED_LOCAL_TO_NODE_6", .udesc = "Read Sized From Local node to Node 6", .ucode = 0x49, .uflags= AMD64_FL_NCOMBO, }, { .uname = "WRITE_SIZED_LOCAL_TO_NODE_6", .udesc = "Write Sized From Local node to Node 6", .ucode = 0x4a, .uflags= AMD64_FL_NCOMBO, }, { .uname = "VICTIM_BLOCK_LOCAL_TO_NODE_6", .udesc = "Victim Block From Local node to Node 6", .ucode = 0x4c, .uflags= AMD64_FL_NCOMBO, }, { .uname = "READ_SIZED_LOCAL_TO_NODE_7", .udesc = "Read Sized From Local node to Node 7", .ucode = 0x89, .uflags= AMD64_FL_NCOMBO, }, { .uname = "WRITE_SIZED_LOCAL_TO_NODE_7", .udesc = "Write Sized From Local node to Node 7", .ucode = 0x8a, .uflags= AMD64_FL_NCOMBO, }, { .uname = "VICTIM_BLOCK_LOCAL_TO_NODE_7", .udesc = "Victim Block From Local node to Node 7", .ucode = 0x8c, .uflags= AMD64_FL_NCOMBO, }, { .uname = "ALL_LOCAL_TO_NODE_0_3", .udesc = "All From Local node to Node 0-3", .ucode = 0xf7, .uflags= AMD64_FL_NCOMBO, }, { .uname = "ALL_LOCAL_TO_NODE_4_7", .udesc = "All From Local node to Node 4-7", .ucode = 0xff, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam15h_nb_request_cache_status_0[]={ { .uname = "PROBE_HIT_S", .udesc = "Probe Hit S", .ucode = 0x1, }, { .uname = "PROBE_HIT_E", .udesc = "Probe Hit E", .ucode = 0x2, }, { .uname = "PROBE_HIT_MUW_OR_O", .udesc = "Probe Hit MuW or O", .ucode = 0x4, }, { .uname = "PROBE_HIT_M", .udesc = "Probe Hit M", .ucode = 0x8, }, { .uname = "PROBE_MISS", .udesc = "Probe Miss", .ucode = 0x10, }, { .uname = "DIRECTED_PROBE", .udesc = "Directed Probe", .ucode = 0x20, }, { .uname = "TRACK_CACHE_STAT_FOR_RDBLK", .udesc = "Track Cache Stat for RdBlk", .ucode = 0x40, }, { .uname = "TRACK_CACHE_STAT_FOR_RDBLKS", .udesc = "Track Cache Stat for RdBlkS", .ucode = 0x80, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xff, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam15h_nb_request_cache_status_1[]={ { .uname = "PROBE_HIT_S", .udesc = "Probe Hit S", .ucode = 0x1, }, { .uname = "PROBE_HIT_E", .udesc = "Probe Hit E", .ucode = 0x2, }, { .uname = "PROBE_HIT_MUW_OR_O", .udesc = "Probe Hit MuW or O", .ucode = 0x4, }, { .uname = "PROBE_HIT_M", .udesc = "Probe Hit M", .ucode = 0x8, }, { .uname = "PROBE_MISS", .udesc = "Probe Miss", .ucode = 0x10, }, { .uname = "DIRECTED_PROBE", .udesc = "Directed Probe", .ucode = 0x20, }, { .uname = "TRACK_CACHE_STAT_FOR_CHGTODIRTY", .udesc = "Track Cache Stat for ChgToDirty", .ucode = 0x40, }, { .uname = "TRACK_CACHE_STAT_FOR_RDBLKM", .udesc = "Track Cache Stat for RdBlkM", .ucode = 0x80, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xff, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam15h_nb_memory_controller_requests[]={ { .uname = "WRITE_REQUESTS_TO_DCT", .udesc = "Write requests sent to the DCT", .ucode = 0x1, }, { .uname = "READ_REQUESTS_TO_DCT", .udesc = "Read requests (including prefetch requests) sent to the DCT", .ucode = 0x2, }, { .uname = "PREFETCH_REQUESTS_TO_DCT", .udesc = "Prefetch requests sent to the DCT", .ucode = 0x4, }, { .uname = "32_BYTES_SIZED_WRITES", .udesc = "32 Bytes Sized Writes", .ucode = 0x8, }, { .uname = "64_BYTES_SIZED_WRITES", .udesc = "64 Bytes Sized Writes", .ucode = 0x10, }, { .uname = "32_BYTES_SIZED_READS", .udesc = "32 Bytes Sized Reads", .ucode = 0x20, }, { .uname = "64_BYTE_SIZED_READS", .udesc = "64 Byte Sized Reads", .ucode = 0x40, }, { .uname = "READ_REQUESTS_TO_DCT_WHILE_WRITES_PENDING", .udesc = "Read requests sent to the DCT while writes requests are pending in the DCT", .ucode = 0x80, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xff, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam15h_nb_read_request_to_l3_cache[]={ { .uname = "READ_BLOCK_EXCLUSIVE", .udesc = "Read Block Exclusive (Data cache read)", .ucode = 0x1, .grpid = 0, }, { .uname = "READ_BLOCK_SHARED", .udesc = "Read Block Shared (Instruction cache read)", .ucode = 0x2, .grpid = 0, }, { .uname = "READ_BLOCK_MODIFY", .udesc = "Read Block Modify", .ucode = 0x4, .grpid = 0, }, { .uname = "PREFETCH", .udesc = "Count prefetches only", .ucode = 0x8, .grpid = 0, }, { .uname = "READ_BLOCK_ANY", .udesc = "Count any read request", .ucode = 0x7, .grpid = 0, .uflags= AMD64_FL_DFL | AMD64_FL_NCOMBO, }, CORE_SELECT(1), }; static const amd64_umask_t amd64_fam15h_nb_l3_fills_caused_by_l2_evictions[]={ { .uname = "SHARED", .udesc = "Shared", .ucode = 0x1, .grpid = 0, }, { .uname = "EXCLUSIVE", .udesc = "Exclusive", .ucode = 0x2, .grpid = 0, }, { .uname = "OWNED", .udesc = "Owned", .ucode = 0x4, .grpid = 0, }, { .uname = "MODIFIED", .udesc = "Modified", .ucode = 0x8, .grpid = 0, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xff, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, .grpid = 0, }, CORE_SELECT(1), }; static const amd64_umask_t amd64_fam15h_nb_l3_evictions[]={ { .uname = "SHARED", .udesc = "Shared", .ucode = 0x1, }, { .uname = "EXCLUSIVE", .udesc = "Exclusive", .ucode = 0x2, }, { .uname = "OWNED", .udesc = "Owned", .ucode = 0x4, }, { .uname = "MODIFIED", .udesc = "Modified", .ucode = 0x8, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xf, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam15h_nb_l3_latency[]={ { .uname = "L3_REQUEST_CYCLE", .udesc = "L3 Request cycle count.", .ucode = 0x1, }, { .uname = "L3_REQUEST", .udesc = "L3 request count.", .ucode = 0x2, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_entry_t amd64_fam15h_nb_pe[]={ { .name = "DRAM_ACCESSES", .desc = "DRAM Accesses", .code = 0xe0, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_nb_dram_accesses), .ngrp = 1, .umasks = amd64_fam15h_nb_dram_accesses, }, { .name = "DRAM_CONTROLLER_PAGE_TABLE_OVERFLOWS", .desc = "DRAM Controller Page Table Overflows", .code = 0xe1, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_nb_dram_controller_page_table_overflows), .ngrp = 1, .umasks = amd64_fam15h_nb_dram_controller_page_table_overflows, }, { .name = "MEMORY_CONTROLLER_DRAM_COMMAND_SLOTS_MISSED", .desc = "Memory Controller DRAM Command Slots Missed", .code = 0xe2, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_nb_memory_controller_dram_command_slots_missed), .ngrp = 1, .umasks = amd64_fam15h_nb_memory_controller_dram_command_slots_missed, }, { .name = "MEMORY_CONTROLLER_TURNAROUNDS", .desc = "Memory Controller Turnarounds", .code = 0xe3, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_nb_memory_controller_turnarounds), .ngrp = 1, .umasks = amd64_fam15h_nb_memory_controller_turnarounds, }, { .name = "MEMORY_CONTROLLER_BYPASS_COUNTER_SATURATION", .desc = "Memory Controller Bypass Counter Saturation", .code = 0xe4, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_nb_memory_controller_bypass_counter_saturation), .ngrp = 1, .umasks = amd64_fam15h_nb_memory_controller_bypass_counter_saturation, }, { .name = "THERMAL_STATUS", .desc = "Thermal Status", .code = 0xe8, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_nb_thermal_status), .ngrp = 1, .umasks = amd64_fam15h_nb_thermal_status, }, { .name = "CPU_IO_REQUESTS_TO_MEMORY_IO", .desc = "CPU/IO Requests to Memory/IO", .code = 0xe9, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_nb_cpu_io_requests_to_memory_io), .ngrp = 1, .umasks = amd64_fam15h_nb_cpu_io_requests_to_memory_io, }, { .name = "CACHE_BLOCK_COMMANDS", .desc = "Cache Block Commands", .code = 0xea, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_nb_cache_block_commands), .ngrp = 1, .umasks = amd64_fam15h_nb_cache_block_commands, }, { .name = "SIZED_COMMANDS", .desc = "Sized Commands", .code = 0xeb, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_nb_sized_commands), .ngrp = 1, .umasks = amd64_fam15h_nb_sized_commands, }, { .name = "PROBE_RESPONSES_AND_UPSTREAM_REQUESTS", .desc = "Probe Responses and Upstream Requests", .code = 0xec, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_nb_probe_responses_and_upstream_requests), .ngrp = 1, .umasks = amd64_fam15h_nb_probe_responses_and_upstream_requests, }, { .name = "GART_EVENTS", .desc = "GART Events", .code = 0xee, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_nb_gart_events), .ngrp = 1, .umasks = amd64_fam15h_nb_gart_events, }, { .name = "LINK_TRANSMIT_BANDWIDTH_LINK_0", .desc = "Link Transmit Bandwidth Link 0", .code = 0xf6, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_nb_link_transmit_bandwidth), .ngrp = 2, .umasks = amd64_fam15h_nb_link_transmit_bandwidth, }, { .name = "LINK_TRANSMIT_BANDWIDTH_LINK_1", .desc = "Link Transmit Bandwidth Link 1", .code = 0xf7, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_nb_link_transmit_bandwidth), .ngrp = 2, .umasks = amd64_fam15h_nb_link_transmit_bandwidth, }, { .name = "LINK_TRANSMIT_BANDWIDTH_LINK_2", .desc = "Link Transmit Bandwidth Link 2", .code = 0xf8, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_nb_link_transmit_bandwidth), .ngrp = 2, .umasks = amd64_fam15h_nb_link_transmit_bandwidth, }, { .name = "LINK_TRANSMIT_BANDWIDTH_LINK_3", .desc = "Link Transmit Bandwidth Link 3", .code = 0x1f9, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_nb_link_transmit_bandwidth), .ngrp = 2, .umasks = amd64_fam15h_nb_link_transmit_bandwidth, }, { .name = "CPU_TO_DRAM_REQUESTS_TO_TARGET_NODE", .desc = "CPU to DRAM Requests to Target Node", .code = 0x1e0, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_nb_cpu_to_dram_requests_to_target_node), .ngrp = 1, .umasks = amd64_fam15h_nb_cpu_to_dram_requests_to_target_node, }, { .name = "IO_TO_DRAM_REQUESTS_TO_TARGET_NODE", .desc = "IO to DRAM Requests to Target Node", .code = 0x1e1, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_nb_io_to_dram_requests_to_target_node), .ngrp = 1, .umasks = amd64_fam15h_nb_io_to_dram_requests_to_target_node, }, { .name = "CPU_READ_COMMAND_LATENCY_TO_TARGET_NODE_0_3", .desc = "CPU Read Command Latency to Target Node 0-3", .code = 0x1e2, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_nb_cpu_read_command_requests_to_target_node_0_3), .ngrp = 1, .umasks = amd64_fam15h_nb_cpu_read_command_requests_to_target_node_0_3, }, { .name = "CPU_READ_COMMAND_REQUESTS_TO_TARGET_NODE_0_3", .desc = "CPU Read Command Requests to Target Node 0-3", .code = 0x1e3, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_nb_cpu_read_command_requests_to_target_node_0_3), .ngrp = 1, .umasks = amd64_fam15h_nb_cpu_read_command_requests_to_target_node_0_3, }, { .name = "CPU_READ_COMMAND_LATENCY_TO_TARGET_NODE_4_7", .desc = "CPU Read Command Latency to Target Node 4-7", .code = 0x1e4, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_nb_cpu_read_command_requests_to_target_node_4_7), .ngrp = 1, .umasks = amd64_fam15h_nb_cpu_read_command_requests_to_target_node_4_7, }, { .name = "CPU_READ_COMMAND_REQUESTS_TO_TARGET_NODE_4_7", .desc = "CPU Read Command Requests to Target Node 4-7", .code = 0x1e5, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_nb_cpu_read_command_requests_to_target_node_4_7), .ngrp = 1, .umasks = amd64_fam15h_nb_cpu_read_command_requests_to_target_node_4_7, }, { .name = "CPU_COMMAND_LATENCY_TO_TARGET_NODE", .desc = "CPU Command Latency to Target Node", .code = 0x1e6, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_nb_cpu_command_requests_to_target_node), .ngrp = 1, .umasks = amd64_fam15h_nb_cpu_command_requests_to_target_node, }, { .name = "CPU_REQUESTS_TO_TARGET_NODE", .desc = "CPU Requests to Target Node", .code = 0x1e7, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_nb_cpu_command_requests_to_target_node), .ngrp = 1, .umasks = amd64_fam15h_nb_cpu_command_requests_to_target_node, }, { .name = "REQUEST_CACHE_STATUS_0", .desc = "Request Cache Status 0", .code = 0x1ea, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_nb_request_cache_status_0), .ngrp = 1, .umasks = amd64_fam15h_nb_request_cache_status_0, }, { .name = "REQUEST_CACHE_STATUS_1", .desc = "Request Cache Status 1", .code = 0x1eb, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_nb_request_cache_status_1), .ngrp = 1, .umasks = amd64_fam15h_nb_request_cache_status_1, }, { .name = "MEMORY_CONTROLLER_REQUESTS", .desc = "Memory Controller Requests", .code = 0x1f0, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_nb_memory_controller_requests), .ngrp = 1, .umasks = amd64_fam15h_nb_memory_controller_requests, }, { .name = "READ_REQUEST_TO_L3_CACHE", .desc = "Read Request to L3 Cache", .code = 0x4e0, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_nb_read_request_to_l3_cache), .ngrp = 2, .umasks = amd64_fam15h_nb_read_request_to_l3_cache, }, { .name = "L3_CACHE_MISSES", .desc = "L3 Cache Misses", .code = 0x4e1, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_nb_read_request_to_l3_cache), .ngrp = 2, .umasks = amd64_fam15h_nb_read_request_to_l3_cache, }, { .name = "L3_FILLS_CAUSED_BY_L2_EVICTIONS", .desc = "L3 Fills caused by L2 Evictions", .code = 0x4e2, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_nb_l3_fills_caused_by_l2_evictions), .ngrp = 2, .umasks = amd64_fam15h_nb_l3_fills_caused_by_l2_evictions, }, { .name = "L3_EVICTIONS", .desc = "L3 Evictions", .code = 0x4e3, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_nb_l3_evictions), .ngrp = 1, .umasks = amd64_fam15h_nb_l3_evictions, }, { .name = "NON_CANCELED_L3_READ_REQUESTS", .desc = "Non-canceled L3 Read Requests", .code = 0x4ed, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_nb_read_request_to_l3_cache), .ngrp = 2, .umasks = amd64_fam15h_nb_read_request_to_l3_cache, }, { .name = "L3_LATENCY", .desc = "L3 Latency", .code = 0x4ef, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_nb_l3_latency), .ngrp = 1, .umasks = amd64_fam15h_nb_l3_latency, }, }; libpfm-4.9.0/lib/events/intel_hswep_unc_r3qpi_events.h0000664000175000017500000003562413223402656022743 0ustar eranianeranian/* * Copyright (c) 2014 Google Inc. All rights reserved * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * PMU: hswep_unc_r3qpi (Intel Haswell-EP R3QPI uncore) */ static const intel_x86_umask_t hswep_unc_r3_ring_ad_used[]={ { .uname = "CCW_EVEN", .udesc = "Counter-Clockwise and even ring polarity", .ucode = 0x400, }, { .uname = "CCW_ODD", .udesc = "Counter-Clockwise and odd ring polarity", .ucode = 0x800, }, { .uname = "CW_EVEN", .udesc = "Clockwise and even ring polarity", .ucode = 0x100, }, { .uname = "CW_ODD", .udesc = "Clockwise and odd ring polarity", .ucode = 0x200, }, { .uname = "CW", .udesc = "Clockwise with any polarity on either virtual rings", .ucode = 0x300, }, { .uname = "CCW", .udesc = "Counter-clockwise with any polarity on either virtual rings", .ucode = 0xc00, }, }; static const intel_x86_umask_t hswep_unc_r3_ring_iv_used[]={ { .uname = "CW", .udesc = "Clockwise with any polarity on either virtual rings", .ucode = 0x300, }, { .uname = "ANY", .udesc = "Counter-clockwise with any polarity on either virtual rings", .ucode = 0xf00, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t hswep_unc_r3_rxr_cycles_ne[]={ { .uname = "HOM", .udesc = "HOM Ingress queue", .ucode = 0x100, }, { .uname = "SNP", .udesc = "SNP Ingress queue", .ucode = 0x200, }, { .uname = "NDR", .udesc = "NDR Ingress queue", .ucode = 0x400, }, }; static const intel_x86_umask_t hswep_unc_r3_rxr_inserts[]={ { .uname = "DRS", .udesc = "DRS Ingress queue", .ucode = 0x800, }, { .uname = "HOM", .udesc = "HOM Ingress queue", .ucode = 0x100, }, { .uname = "NCB", .udesc = "NCB Ingress queue", .ucode = 0x1000, }, { .uname = "NCS", .udesc = "NCS Ingress queue", .ucode = 0x2000, }, { .uname = "NDR", .udesc = "NDR Ingress queue", .ucode = 0x400, }, { .uname = "SNP", .udesc = "SNP Ingress queue", .ucode = 0x200, }, }; static const intel_x86_umask_t hswep_unc_r3_vn0_credits_used[]={ { .uname = "HOM", .udesc = "Filter HOM message class", .ucode = 0x100, }, { .uname = "SNP", .udesc = "Filter SNP message class", .ucode = 0x200, }, { .uname = "NDR", .udesc = "Filter NDR message class", .ucode = 0x400, }, { .uname = "DRS", .udesc = "Filter DRS message class", .ucode = 0x800, }, { .uname = "NCB", .udesc = "Filter NCB message class", .ucode = 0x1000, }, { .uname = "NCS", .udesc = "Filter NCS message class", .ucode = 0x2000, }, }; static const intel_x86_umask_t hswep_unc_r3_c_lo_ad_credits_empty[]={ { .uname = "CBO0", .udesc = "CBox 0", .ucode = 0x100, }, { .uname = "CBO1", .udesc = "CBox 1", .ucode = 0x200, }, { .uname = "CBO2", .udesc = "CBox 2", .ucode = 0x400, }, { .uname = "CBO3", .udesc = "CBox 3", .ucode = 0x800, }, { .uname = "CBO4", .udesc = "CBox 4", .ucode = 0x1000, }, { .uname = "CBO5", .udesc = "CBox 5", .ucode = 0x2000, }, { .uname = "CBO6", .udesc = "CBox 6", .ucode = 0x4000, }, { .uname = "CBO7", .udesc = "CBox 7", .ucode = 0x8000, } }; static const intel_x86_umask_t hswep_unc_r3_c_hi_ad_credits_empty[]={ { .uname = "CBO8", .udesc = "CBox 8", .ucode = 0x100, }, { .uname = "CBO9", .udesc = "CBox 9", .ucode = 0x200, }, { .uname = "CBO10", .udesc = "CBox 10", .ucode = 0x400, }, { .uname = "CBO11", .udesc = "CBox 11", .ucode = 0x800, }, { .uname = "CBO12", .udesc = "CBox 12", .ucode = 0x1000, }, { .uname = "CBO13", .udesc = "CBox 13", .ucode = 0x2000, }, { .uname = "CBO14_16", .udesc = "CBox 14 and CBox 16", .ucode = 0x4000, }, { .uname = "CBO15_17", .udesc = "CBox 15 and CBox 17", .ucode = 0x8000, } }; static const intel_x86_umask_t hswep_unc_r3_ha_r2_bl_credits_empty[]={ { .uname = "HA0", .udesc = "HA0", .ucode = 0x100, }, { .uname = "HA1", .udesc = "HA1", .ucode = 0x200, }, { .uname = "R2_NCB", .udesc = "R2 NCB messages", .ucode = 0x400, }, { .uname = "R2_NCS", .udesc = "R2 NCS messages", .ucode = 0x800, } }; static const intel_x86_umask_t hswep_unc_r3_qpi0_ad_credits_empty[]={ { .uname = "VNA", .udesc = "VNA", .ucode = 0x100, }, { .uname = "VN0_HOM", .udesc = "VN0 HOM messages", .ucode = 0x200, }, { .uname = "VN0_SNP", .udesc = "VN0 SNP messages", .ucode = 0x400, }, { .uname = "VN0_NDR", .udesc = "VN0 NDR messages", .ucode = 0x800, }, { .uname = "VN1_HOM", .udesc = "VN1 HOM messages", .ucode = 0x1000, }, { .uname = "VN1_SNP", .udesc = "VN1 SNP messages", .ucode = 0x2000, }, { .uname = "VN1_NDR", .udesc = "VN1 NDR messages", .ucode = 0x4000, }, }; static const intel_x86_umask_t hswep_unc_r3_sbo0_credits_acquired[]={ { .uname = "AD", .udesc = "For AD ring", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "BL", .udesc = "For BL ring", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t hswep_unc_r3_txr_nack[]={ { .uname = "AD", .udesc = "AD clockwise Egress queue", .ucode = 0x100, }, { .uname = "AK", .udesc = "AD counter-clockwise Egress queue", .ucode = 0x200, }, { .uname = "BL", .udesc = "BL clockwise Egress queue", .ucode = 0x400, }, }; static const intel_x86_umask_t hswep_unc_r3_vna_credits_acquired[]={ { .uname = "AD", .udesc = "For AD ring", .ucode = 0x100, }, { .uname = "BL", .udesc = "For BL ring", .ucode = 0x400, }, }; static const intel_x86_umask_t hswep_unc_r3_stall_no_sbo_credit[]={ { .uname = "SBO0_AD", .udesc = "For SBO0, AD ring", .ucode = 0x100, }, { .uname = "SBO1_AD", .udesc = "For SBO1, AD ring", .ucode = 0x100, }, { .uname = "SBO0_BL", .udesc = "For SBO0, BL ring", .ucode = 0x100, }, { .uname = "SBO1_BL", .udesc = "For SBO1, BL ring", .ucode = 0x100, }, }; static const intel_x86_umask_t hswep_unc_r3_ring_sink_starved[]={ { .uname = "AK", .udesc = "For AJ ring", .ucode = 0x200, .uflags = INTEL_X86_DFL, }, }; static const intel_x86_entry_t intel_hswep_unc_r3_pe[]={ { .name = "UNC_R3_CLOCKTICKS", .desc = "Number of uclks in domain", .code = 0x1, .cntmsk = 0x7, .modmsk = HSWEP_UNC_R3QPI_ATTRS, }, { .name = "UNC_R3_RING_AD_USED", .desc = "R3 AD Ring in Use", .code = 0x7, .cntmsk = 0x7, .ngrp = 1, .modmsk = HSWEP_UNC_R3QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_r3_ring_ad_used), .umasks = hswep_unc_r3_ring_ad_used }, { .name = "UNC_R3_RING_AK_USED", .desc = "R3 AK Ring in Use", .code = 0x8, .cntmsk = 0x7, .ngrp = 1, .modmsk = HSWEP_UNC_R3QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_r3_ring_ad_used), .umasks = hswep_unc_r3_ring_ad_used /* shared */ }, { .name = "UNC_R3_RING_BL_USED", .desc = "R3 BL Ring in Use", .code = 0x9, .cntmsk = 0x7, .ngrp = 1, .modmsk = HSWEP_UNC_R3QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_r3_ring_ad_used), .umasks = hswep_unc_r3_ring_ad_used /* shared */ }, { .name = "UNC_R3_RING_IV_USED", .desc = "R3 IV Ring in Use", .code = 0xa, .cntmsk = 0x7, .ngrp = 1, .modmsk = HSWEP_UNC_R3QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_r3_ring_iv_used), .umasks = hswep_unc_r3_ring_iv_used }, { .name = "UNC_R3_RING_SINK_STARVED", .desc = "R3 Ring stop starved", .code = 0xe, .cntmsk = 0x7, .ngrp = 1, .modmsk = HSWEP_UNC_R3QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_r3_ring_sink_starved), .umasks = hswep_unc_r3_ring_sink_starved }, { .name = "UNC_R3_RXR_CYCLES_NE", .desc = "Ingress Cycles Not Empty", .code = 0x10, .cntmsk = 0x3, .ngrp = 1, .modmsk = HSWEP_UNC_R3QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_r3_rxr_cycles_ne), .umasks = hswep_unc_r3_rxr_cycles_ne }, { .name = "UNC_R3_RXR_CYCLES_NE_VN1", .desc = "VN1 Ingress Cycles Not Empty", .code = 0x14, .cntmsk = 0x3, .ngrp = 1, .modmsk = HSWEP_UNC_R3QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_r3_rxr_inserts), .umasks = hswep_unc_r3_rxr_inserts }, { .name = "UNC_R3_RXR_INSERTS", .desc = "Ingress Allocations", .code = 0x11, .cntmsk = 0x3, .ngrp = 1, .modmsk = HSWEP_UNC_R3QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_r3_rxr_inserts), .umasks = hswep_unc_r3_rxr_inserts }, { .name = "UNC_R3_RXR_INSERTS_VN1", .desc = "VN1 Ingress Allocations", .code = 0x15, .cntmsk = 0x3, .ngrp = 1, .modmsk = HSWEP_UNC_R3QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_r3_rxr_inserts), .umasks = hswep_unc_r3_rxr_inserts }, { .name = "UNC_R3_RXR_OCCUPANCY_VN1", .desc = "VN1 Ingress Occupancy Accumulator", .code = 0x13, .cntmsk = 0x1, .ngrp = 1, .modmsk = HSWEP_UNC_R3QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_r3_rxr_inserts), .umasks = hswep_unc_r3_rxr_inserts/* shared */ }, { .name = "UNC_R3_VN0_CREDITS_REJECT", .desc = "VN0 Credit Acquisition Failed", .code = 0x37, .cntmsk = 0x3, .ngrp = 1, .modmsk = HSWEP_UNC_R3QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_r3_vn0_credits_used), .umasks = hswep_unc_r3_vn0_credits_used }, { .name = "UNC_R3_VN0_CREDITS_USED", .desc = "VN0 Credit Used", .code = 0x36, .cntmsk = 0x3, .ngrp = 1, .modmsk = HSWEP_UNC_R3QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_r3_vn0_credits_used), .umasks = hswep_unc_r3_vn0_credits_used }, { .name = "UNC_R3_VNA_CREDITS_ACQUIRED", .desc = "VNA credit Acquisitions", .code = 0x33, .cntmsk = 0x3, .ngrp = 1, .modmsk = HSWEP_UNC_R3QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_r3_vna_credits_acquired), .umasks = hswep_unc_r3_vna_credits_acquired }, { .name = "UNC_R3_VNA_CREDITS_REJECT", .desc = "VNA Credit Reject", .code = 0x34, .cntmsk = 0x3, .ngrp = 1, .modmsk = HSWEP_UNC_R3QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_r3_vn0_credits_used), .umasks = hswep_unc_r3_vn0_credits_used /* shared */ }, { .name = "UNC_R3_STALL_NO_SBO_CREDIT", .desc = "Stall no SBO credit", .code = 0x2c, .cntmsk = 0x3, .ngrp = 1, .modmsk = HSWEP_UNC_R3QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_r3_stall_no_sbo_credit), .umasks = hswep_unc_r3_stall_no_sbo_credit, }, { .name = "UNC_R3_C_LO_AD_CREDITS_EMPTY", .desc = "Cbox AD credits empty", .code = 0x22, .cntmsk = 0x3, .ngrp = 1, .modmsk = HSWEP_UNC_R3QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_r3_c_lo_ad_credits_empty), .umasks = hswep_unc_r3_c_lo_ad_credits_empty }, { .name = "UNC_R3_C_HI_AD_CREDITS_EMPTY", .desc = "Cbox AD credits empty", .code = 0x1f, .cntmsk = 0x3, .ngrp = 1, .modmsk = HSWEP_UNC_R3QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_r3_c_hi_ad_credits_empty), .umasks = hswep_unc_r3_c_hi_ad_credits_empty }, { .name = "UNC_R3_QPI0_AD_CREDITS_EMPTY", .desc = "QPI0 AD credits empty", .code = 0x20, .cntmsk = 0x3, .ngrp = 1, .modmsk = HSWEP_UNC_R3QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_r3_qpi0_ad_credits_empty), .umasks = hswep_unc_r3_qpi0_ad_credits_empty }, { .name = "UNC_R3_QPI0_BL_CREDITS_EMPTY", .desc = "QPI0 BL credits empty", .code = 0x21, .cntmsk = 0x3, .ngrp = 1, .modmsk = HSWEP_UNC_R3QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_r3_qpi0_ad_credits_empty), .umasks = hswep_unc_r3_qpi0_ad_credits_empty }, { .name = "UNC_R3_QPI1_BL_CREDITS_EMPTY", .desc = "QPI0 BL credits empty", .code = 0x2f, .cntmsk = 0x3, .ngrp = 1, .modmsk = HSWEP_UNC_R3QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_r3_qpi0_ad_credits_empty), .umasks = hswep_unc_r3_qpi0_ad_credits_empty }, { .name = "UNC_R3_HA_R2_BL_CREDITS_EMPTY", .desc = "HA/R2 AD credits empty", .code = 0x2d, .cntmsk = 0x3, .ngrp = 1, .modmsk = HSWEP_UNC_R3QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_r3_ha_r2_bl_credits_empty), .umasks = hswep_unc_r3_ha_r2_bl_credits_empty }, { .name = "UNC_R3_SBO0_CREDITS_ACQUIRED", .desc = "SBO0 credits acquired", .code = 0x28, .cntmsk = 0x3, .ngrp = 1, .modmsk = HSWEP_UNC_R3QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_r3_sbo0_credits_acquired), .umasks = hswep_unc_r3_sbo0_credits_acquired, }, { .name = "UNC_R3_SBO1_CREDITS_ACQUIRED", .desc = "SBO1 credits acquired", .code = 0x29, .cntmsk = 0x3, .ngrp = 1, .modmsk = HSWEP_UNC_R3QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_r3_sbo0_credits_acquired), .umasks = hswep_unc_r3_sbo0_credits_acquired, }, { .name = "UNC_R3_TXR_NACK", .desc = "Egress NACK", .code = 0x26, .cntmsk = 0x3, .ngrp = 1, .modmsk = HSWEP_UNC_R3QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_r3_txr_nack), .umasks = hswep_unc_r3_txr_nack }, { .name = "UNC_R3_VN1_CREDITS_REJECT", .desc = "VN1 Credit Acquisition Failed", .code = 0x39, .cntmsk = 0x3, .ngrp = 1, .modmsk = HSWEP_UNC_R3QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_r3_vn0_credits_used), /* shared */ .umasks = hswep_unc_r3_vn0_credits_used }, { .name = "UNC_R3_VN1_CREDITS_USED", .desc = "VN0 Credit Used", .code = 0x38, .cntmsk = 0x3, .ngrp = 1, .modmsk = HSWEP_UNC_R3QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_r3_vn0_credits_used), /* shared */ .umasks = hswep_unc_r3_vn0_credits_used }, }; libpfm-4.9.0/lib/events/arm_cortex_a9_events.h0000664000175000017500000002035513223402656021166 0ustar eranianeranian/* * Copyright (c) 2010 University of Tennessee * Contributed by Vince Weaver * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. */ /* * the various event names are the same as those given in the * file linux-2.6/arch/arm/kernel/perf_event.c */ /* * Cortex A9 r2p2 Event Table * based on Table 11-7 from the "Cortex A9 Technical Reference Manual" */ static const arm_entry_t arm_cortex_a9_pe []={ /* * ARMv7 events */ {.name = "PMNC_SW_INCR", .code = 0x00, .desc = "Incremented by writes to the Software Increment Register" }, {.name = "IFETCH_MISS", .code = 0x01, .desc = "Instruction fetches that cause lowest-level cache miss" }, {.name = "ITLB_MISS", .code = 0x02, .desc = "Instruction fetches that cause lowest-level TLB miss" }, {.name = "DCACHE_REFILL", .code = 0x03, .desc = "Data read or writes that cause lowest-level cache miss" }, {.name = "DCACHE_ACCESS", .code = 0x04, .desc = "Data read or writes that cause lowest-level cache access" }, {.name = "DTLB_REFILL", .code = 0x05, .desc = "Data read or writes that cause lowest-level TLB refill" }, {.name = "DREAD", .code = 0x06, .desc = "Data read architecturally executed" }, {.name = "DWRITE", .code = 0x07, .desc = "Data write architecturally executed" }, {.name = "EXC_TAKEN", .code = 0x09, .desc = "Counts each exception taken" }, {.name = "EXC_EXECUTED", .code = 0x0a, .desc = "Exception returns architecturally executed" }, {.name = "CID_WRITE", .code = 0x0b, .desc = "Instruction writes to Context ID Register, architecturally executed" }, {.name = "PC_WRITE", .code = 0x0c, .desc = "Software change of PC. Equivalent to branches" }, {.name = "PC_IMM_BRANCH", .code = 0x0d, .desc = "Immediate branches architecturally executed" }, {.name = "UNALIGNED_ACCESS", .code = 0x0f, .desc = "Unaligned accesses architecturally executed" }, {.name = "PC_BRANCH_MIS_PRED", .code = 0x10, .desc = "Branches mispredicted or not predicted" }, {.name = "CLOCK_CYCLES", .code = 0x11, .desc = "Clock cycles" }, {.name = "PC_BRANCH_MIS_USED", .code = 0x12, .desc = "Branches that could have been predicted" }, /* * Cortex A9 specific events */ {.name = "JAVA_HW_BYTECODE_EXEC", .code = 0x40, .desc = "Java bytecodes decoded, including speculative (approximate)" }, {.name = "JAVA_SW_BYTECODE_EXEC", .code = 0x41, .desc = "Software Java bytecodes decoded, including speculative (approximate)" }, {.name = "JAZELLE_BRANCH_EXEC", .code = 0x42, .desc = "Jazelle backward branches executed. Includes branches that are flushed because of previous load/store which abort late (approximate)" }, {.name = "COHERENT_LINE_MISS", .code = 0x50, .desc = "Coherent linefill misses which also miss on other processors" }, {.name = "COHERENT_LINE_HIT", .code = 0x51, .desc = "Coherent linefill requests that hit on another processor" }, {.name = "ICACHE_DEP_STALL_CYCLES", .code = 0x60, .desc = "Cycles processor is stalled waiting for instruction cache and the instruction cache is performing at least one linefill (approximate)" }, {.name = "DCACHE_DEP_STALL_CYCLES", .code = 0x61, .desc = "Cycles processor is stalled waiting for data cache" }, {.name = "TLB_MISS_DEP_STALL_CYCLES", .code = 0x62, .desc = "Cycles processor is stalled waiting for completion of TLB walk (approximate)" }, {.name = "STREX_EXECUTED_PASSED", .code = 0x63, .desc = "Number of STREX instructions executed and passed" }, {.name = "STREX_EXECUTED_FAILED", .code = 0x64, .desc = "Number of STREX instructions executed and failed" }, {.name = "DATA_EVICTION", .code = 0x65, .desc = "Data eviction requests due to linefill in data cache" }, {.name = "ISSUE_STAGE_NO_INST", .code = 0x66, .desc = "Cycles the issue stage does not dispatch any instructions" }, {.name = "ISSUE_STAGE_EMPTY", .code = 0x67, .desc = "Cycles where issue stage is empty" }, {.name = "INST_OUT_OF_RENAME_STAGE", .code = 0x68, .desc = "Number of instructions going through register renaming stage (approximate)" }, {.name = "PREDICTABLE_FUNCT_RETURNS", .code = 0x6e, .desc = "Number of predictable function returns whose condition codes do not fail (approximate)" }, {.name = "MAIN_UNIT_EXECUTED_INST", .code = 0x70, .desc = "Instructions executed in the main execution, multiply, ALU pipelines (approximate)" }, {.name = "SECOND_UNIT_EXECUTED_INST", .code = 0x71, .desc = "Instructions executed in the second execution pipeline" }, {.name = "LD_ST_UNIT_EXECUTED_INST", .code = 0x72, .desc = "Instructions executed in the Load/Store unit" }, {.name = "FP_EXECUTED_INST", .code = 0x73, .desc = "Floating point instructions going through register renaming stage" }, {.name = "NEON_EXECUTED_INST", .code = 0x74, .desc = "NEON instructions going through register renaming stage (approximate)" }, {.name = "PLD_FULL_DEP_STALL_CYCLES", .code = 0x80, .desc = "Cycles processor is stalled because PLD slots are full (approximate)" }, {.name = "DATA_WR_DEP_STALL_CYCLES", .code = 0x81, .desc = "Cycles processor is stalled due to writes to external memory (approximate)" }, {.name = "ITLB_MISS_DEP_STALL_CYCLES", .code = 0x82, .desc = "Cycles stalled due to main instruction TLB miss (approximate)" }, {.name = "DTLB_MISS_DEP_STALL_CYCLES", .code = 0x83, .desc = "Cycles stalled due to main data TLB miss (approximate)" }, {.name = "MICRO_ITLB_MISS_DEP_STALL_CYCLES", .code = 0x84, .desc = "Cycles stalled due to micro instruction TLB miss (approximate)" }, {.name = "MICRO_DTLB_MISS_DEP_STALL_CYCLES", .code = 0x85, .desc = "Cycles stalled due to micro data TLB miss (approximate)" }, {.name = "DMB_DEP_STALL_CYCLES", .code = 0x86, .desc = "Cycles stalled due to DMB memory barrier (approximate)" }, {.name = "INTGR_CLK_ENABLED_CYCLES", .code = 0x8a, .desc = "Cycles during which integer core clock is enabled (approximate)" }, {.name = "DATA_ENGINE_CLK_EN_CYCLES", .code = 0x8b, .desc = "Cycles during which Data Engine clock is enabled (approximate)" }, {.name = "ISB_INST", .code = 0x90, .desc = "Number of ISB instructions architecturally executed" }, {.name = "DSB_INST", .code = 0x91, .desc = "Number of DSB instructions architecturally executed" }, {.name = "DMB_INST", .code = 0x92, .desc = "Number of DMB instructions architecturally executed (approximate)" }, {.name = "EXT_INTERRUPTS", .code = 0x93, .desc = "Number of External interrupts (approximate)" }, {.name = "PLE_CACHE_LINE_RQST_COMPLETED", .code = 0xa0, .desc = "PLE cache line requests completed" }, {.name = "PLE_CACHE_LINE_RQST_SKIPPED", .code = 0xa1, .desc = "PLE cache line requests skipped" }, {.name = "PLE_FIFO_FLUSH", .code = 0xa2, .desc = "PLE FIFO flushes" }, {.name = "PLE_RQST_COMPLETED", .code = 0xa3, .desc = "PLE requests completed" }, {.name = "PLE_FIFO_OVERFLOW", .code = 0xa4, .desc = "PLE FIFO overflows" }, {.name = "PLE_RQST_PROG", .code = 0xa5, .desc = "PLE requests programmed" }, {.name = "CPU_CYCLES", .code = 0xff, .desc = "CPU cycles" }, }; #define ARM_CORTEX_A9_EVENT_COUNT (sizeof(arm_cortex_a9_pe)/sizeof(arm_entry_t)) libpfm-4.9.0/lib/events/amd64_events_fam14h.h0000664000175000017500000012457313223402656020514 0ustar eranianeranian/* * Copyright (c) 2011 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * This file has been automatically generated. * * PMU: amd64_fam14h (AMD64 Fam14h) */ static const amd64_umask_t amd64_fam14h_dispatched_fpu[]={ { .uname = "PIPE0", .udesc = "Pipe 0 (fadd, imul, mmx) ops", .ucode = 0x1, }, { .uname = "PIPE1", .udesc = "Pipe 1 (fmul, store, mmx) ops", .ucode = 0x2, }, { .uname = "ANY", .udesc = "Pipe 1 and Pipe 0 ops", .ucode = 0x3, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam14h_retired_sse_operations[]={ { .uname = "SINGLE_ADD_SUB_OPS", .udesc = "Single precision add/subtract ops", .ucode = 0x1, }, { .uname = "SINGLE_MUL_OPS", .udesc = "Single precision multiply ops", .ucode = 0x2, }, { .uname = "SINGLE_DIV_OPS", .udesc = "Single precision divide/square root ops", .ucode = 0x4, }, { .uname = "DOUBLE_ADD_SUB_OPS", .udesc = "Double precision add/subtract ops", .ucode = 0x8, }, { .uname = "DOUBLE_MUL_OPS", .udesc = "Double precision multiply ops", .ucode = 0x10, }, { .uname = "DOUBLE_DIV_OPS", .udesc = "Double precision divide/square root ops", .ucode = 0x20, }, { .uname = "OP_TYPE", .udesc = "Op type: 0=uops. 1=FLOPS", .ucode = 0x40, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x7f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam14h_retired_move_ops[]={ { .uname = "ALL_OTHER_MERGING_MOVE_UOPS", .udesc = "All other merging move uops", .ucode = 0x4, }, { .uname = "ALL_OTHER_MOVE_UOPS", .udesc = "All other move uops", .ucode = 0x8, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xc, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam14h_retired_serializing_ops[]={ { .uname = "SSE_BOTTOM_EXECUTING_UOPS", .udesc = "SSE bottom-executing uops retired", .ucode = 0x1, }, { .uname = "SSE_BOTTOM_SERIALIZING_UOPS", .udesc = "SSE bottom-serializing uops retired", .ucode = 0x2, }, { .uname = "X87_BOTTOM_EXECUTING_UOPS", .udesc = "X87 bottom-executing uops retired", .ucode = 0x4, }, { .uname = "X87_BOTTOM_SERIALIZING_UOPS", .udesc = "X87 bottom-serializing uops retired", .ucode = 0x8, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xf, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam14h_retired_x87_fpu_ops[]={ { .uname = "ADD_SUB_OPS", .udesc = "Add/subtract ops", .ucode = 0x1, }, { .uname = "MULT_OPS", .udesc = "Multiply ops", .ucode = 0x2, }, { .uname = "DIV_FSQRT_OPS", .udesc = "Divide and fqsrt ops", .ucode = 0x4, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x7, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam14h_segment_register_loads[]={ { .uname = "ES", .udesc = "ES", .ucode = 0x1, }, { .uname = "CS", .udesc = "CS", .ucode = 0x2, }, { .uname = "SS", .udesc = "SS", .ucode = 0x4, }, { .uname = "DS", .udesc = "DS", .ucode = 0x8, }, { .uname = "FS", .udesc = "FS", .ucode = 0x10, }, { .uname = "GS", .udesc = "GS", .ucode = 0x20, }, { .uname = "HS", .udesc = "HS", .ucode = 0x40, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x7f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam14h_locked_ops[]={ { .uname = "EXECUTED", .udesc = "Number of locked instructions executed", .ucode = 0x1, }, { .uname = "BUS_LOCK", .udesc = "Number of cycles to acquire bus lock", .ucode = 0x2, }, { .uname = "UNLOCK_LINE", .udesc = "Number of cycles to unlock line (not including cache miss)", .ucode = 0x4, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x7, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam14h_cancelled_store_to_load_forward_operations[]={ { .uname = "ADDRESS_MISMATCHES", .udesc = "Address mismatches (starting byte not the same).", .ucode = 0x1, }, { .uname = "STORE_IS_SMALLER_THAN_LOAD", .udesc = "Store is smaller than load.", .ucode = 0x2, }, { .uname = "MISALIGNED", .udesc = "Misaligned.", .ucode = 0x4, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x7, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam14h_data_cache_refills[]={ { .uname = "UNCACHEABLE", .udesc = "From non-cacheable data", .ucode = 0x1, }, { .uname = "SHARED", .udesc = "From shared lines", .ucode = 0x2, }, { .uname = "EXCLUSIVE", .udesc = "From exclusive lines", .ucode = 0x4, }, { .uname = "OWNED", .udesc = "From owned lines", .ucode = 0x8, }, { .uname = "MODIFIED", .udesc = "From modified lines", .ucode = 0x10, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x1f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam14h_data_cache_refills_from_nb[]={ { .uname = "UNCACHEABLE", .udesc = "Uncacheable data", .ucode = 0x1, }, { .uname = "SHARED", .udesc = "Shared", .ucode = 0x2, }, { .uname = "EXCLUSIVE", .udesc = "Exclusive", .ucode = 0x4, }, { .uname = "OWNED", .udesc = "Owned", .ucode = 0x8, }, { .uname = "MODIFIED", .udesc = "Modified", .ucode = 0x10, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x1f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam14h_data_cache_lines_evicted[]={ { .uname = "PROBE", .udesc = "Eviction from probe", .ucode = 0x1, }, { .uname = "SHARED", .udesc = "Shared eviction", .ucode = 0x2, }, { .uname = "EXCLUSIVE", .udesc = "Exclusive eviction", .ucode = 0x4, }, { .uname = "OWNED", .udesc = "Owned eviction", .ucode = 0x8, }, { .uname = "MODIFIED", .udesc = "Modified eviction", .ucode = 0x10, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x1f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam14h_dtlb_miss[]={ { .uname = "STORES_L1TLB_MISS", .udesc = "Stores that miss L1TLB", .ucode = 0x1, }, { .uname = "LOADS_L1TLB_MISS", .udesc = "Loads that miss L1TLB", .ucode = 0x2, }, { .uname = "STORES_L2TLB_MISS", .udesc = "Stores that miss L2TLB", .ucode = 0x4, }, { .uname = "LOADS_L2TLB_MISS", .udesc = "Loads that miss L2TLB", .ucode = 0x8, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xf, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam14h_prefetch_instructions_dispatched[]={ { .uname = "LOAD", .udesc = "Load (Prefetch, PrefetchT0/T1/T2)", .ucode = 0x1, }, { .uname = "STORE", .udesc = "Store (PrefetchW)", .ucode = 0x2, }, { .uname = "NTA", .udesc = "NTA (PrefetchNTA)", .ucode = 0x4, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x7, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam14h_l1_dtlb_hit[]={ { .uname = "L1_4K_TLB_HIT", .udesc = "L1 4K TLB hit", .ucode = 0x1, }, { .uname = "L1_2M_TLB_HIT", .udesc = "L1 2M TLB hit", .ucode = 0x2, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam14h_dcache_sw_prefetches[]={ { .uname = "HIT", .udesc = "SW prefetch hit in the data cache", .ucode = 0x1, }, { .uname = "PENDING_FILL", .udesc = "SW prefetch hit a pending fill", .ucode = 0x2, }, { .uname = "NO_MAB", .udesc = "SW prefetch does not get a MAB", .ucode = 0x4, }, { .uname = "L2_HIT", .udesc = "SW prefetch hits L2", .ucode = 0x8, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xf, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam14h_memory_requests[]={ { .uname = "NON_CACHEABLE", .udesc = "Requests to non-cacheable (UC) memory", .ucode = 0x1, }, { .uname = "WRITE_COMBINING", .udesc = "Requests to write-combining (WC) memory or WC buffer flushes to WB memory", .ucode = 0x2, }, { .uname = "STREAMING_STORE", .udesc = "Streaming store (SS) requests", .ucode = 0x80, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x83, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam14h_mab_requests[]={ { .uname = "DC_BUFFER_0", .udesc = "Data cache buffer 0", .ucode = 0x0, .uflags= AMD64_FL_NCOMBO, }, { .uname = "DC_BUFFER_1", .udesc = "Data cache buffer 1", .ucode = 0x1, .uflags= AMD64_FL_NCOMBO, }, { .uname = "DC_BUFFER_2", .udesc = "Data cache buffer 2", .ucode = 0x2, .uflags= AMD64_FL_NCOMBO, }, { .uname = "DC_BUFFER_3", .udesc = "Data cache buffer 3", .ucode = 0x3, .uflags= AMD64_FL_NCOMBO, }, { .uname = "DC_BUFFER_4", .udesc = "Data cache buffer 4", .ucode = 0x4, .uflags= AMD64_FL_NCOMBO, }, { .uname = "DC_BUFFER_5", .udesc = "Data cache buffer 5", .ucode = 0x5, .uflags= AMD64_FL_NCOMBO, }, { .uname = "DC_BUFFER_6", .udesc = "Data cache buffer 6", .ucode = 0x6, .uflags= AMD64_FL_NCOMBO, }, { .uname = "DC_BUFFER_7", .udesc = "Data cache buffer 7", .ucode = 0x7, .uflags= AMD64_FL_NCOMBO, }, { .uname = "IC_BUFFER_0", .udesc = "Instruction cache Buffer 1", .ucode = 0x8, .uflags= AMD64_FL_NCOMBO, }, { .uname = "IC_BUFFER_1", .udesc = "Instructions cache buffer 1", .ucode = 0x9, .uflags= AMD64_FL_NCOMBO, }, { .uname = "ANY_IC_BUFFER", .udesc = "Any instruction cache buffer", .ucode = 0xa, .uflags= AMD64_FL_NCOMBO, }, { .uname = "ANY_DC_BUFFER", .udesc = "Any data cache buffer", .ucode = 0xb, .uflags= AMD64_FL_NCOMBO, }, }; static const amd64_umask_t amd64_fam14h_system_read_responses[]={ { .uname = "EXCLUSIVE", .udesc = "Exclusive", .ucode = 0x1, }, { .uname = "MODIFIED", .udesc = "Modified", .ucode = 0x2, }, { .uname = "SHARED", .udesc = "Shared", .ucode = 0x4, }, { .uname = "OWNED", .udesc = "Owned", .ucode = 0x8, }, { .uname = "DATA_ERROR", .udesc = "Data Error", .ucode = 0x10, }, { .uname = "DIRTY_SUCCESS", .udesc = "Change-to-dirty success", .ucode = 0x20, }, { .uname = "UNCACHEABLE", .udesc = "Uncacheable", .ucode = 0x40, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x7f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam14h_requests_to_l2[]={ { .uname = "INSTRUCTIONS", .udesc = "IC fill", .ucode = 0x1, }, { .uname = "DATA", .udesc = "DC fill", .ucode = 0x2, }, { .uname = "SNOOP", .udesc = "Tag snoop request", .ucode = 0x8, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xb, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam14h_l2_cache_miss[]={ { .uname = "INSTRUCTIONS", .udesc = "IC fill", .ucode = 0x1, }, { .uname = "DATA", .udesc = "DC fill (includes possible replays, whereas EventSelect 041h does not)", .ucode = 0x2, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam14h_l2_fill_writeback[]={ { .uname = "L2_FILLS", .udesc = "L2 fills (victims from L1 caches, TLB page table walks and data prefetches)", .ucode = 0x1, }, { .uname = "L2_WRITEBACKS", .udesc = "L2 Writebacks to system.", .ucode = 0x2, }, { .uname = "IC_ATTR_WRITES_L2_ACCESS", .udesc = "Ic attribute writes which access the L2", .ucode = 0x4, }, { .uname = "IC_ATTR_WRITES_L2_WRITES", .udesc = "Ic attribute writes which store into the L2", .ucode = 0x8, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xf, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam14h_l1_itlb_miss_and_l2_itlb_miss[]={ { .uname = "4K_PAGE_FETCHES", .udesc = "Instruction fetches to a 4K page.", .ucode = 0x1, }, { .uname = "2M_PAGE_FETCHES", .udesc = "Instruction fetches to a 2M page.", .ucode = 0x2, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam14h_instruction_cache_lines_invalidated[]={ { .uname = "INVALIDATING_LS_PROBE", .udesc = "IC invalidate due to an LS probe", .ucode = 0x1, }, { .uname = "INVALIDATING_BU_PROBE", .udesc = "IC invalidate due to a BU probe", .ucode = 0x2, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam14h_retired_floating_point_instructions[]={ { .uname = "X87", .udesc = "X87 or MMX instructions", .ucode = 0x1, }, { .uname = "SSE", .udesc = "SSE (SSE, SSE2, SSE3, MNI) instructions", .ucode = 0x2, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam14h_fpu_exceptions[]={ { .uname = "X87_RECLASS_MICROFAULTS", .udesc = "X87 reclass microfaults", .ucode = 0x1, }, { .uname = "SSE_RETYPE_MICROFAULTS", .udesc = "SSE retype microfaults", .ucode = 0x2, }, { .uname = "SSE_RECLASS_MICROFAULTS", .udesc = "SSE reclass microfaults", .ucode = 0x4, }, { .uname = "SSE_AND_X87_MICROTRAPS", .udesc = "SSE and x87 microtraps", .ucode = 0x8, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xf, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam14h_dram_accesses_page[]={ { .uname = "HIT", .udesc = "DCT0 Page hit", .ucode = 0x1, }, { .uname = "MISS", .udesc = "DCT0 Page Miss", .ucode = 0x2, }, { .uname = "CONFLICT", .udesc = "DCT0 Page Conflict", .ucode = 0x4, }, { .uname = "WRITE_REQUEST", .udesc = "Write request", .ucode = 0x40, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x47, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam14h_memory_controller_page_table[]={ { .uname = "DCT0_PAGE_TABLE_OVERFLOW", .udesc = "DCT0 Page Table Overflow", .ucode = 0x1, }, { .uname = "DCT0_PAGE_TABLE_STALE_HIT", .udesc = "DCT0 number of stale table entry hits (hit on a page closed too soon)", .ucode = 0x2, }, { .uname = "DCT0_PAGE_TABLE_IDLE_INC", .udesc = "DCT0 page table idle cycle limit incremented", .ucode = 0x4, }, { .uname = "DCT0_PAGE_TABLE_IDLE_DEC", .udesc = "DCT0 page table idle cycle limit decremented", .ucode = 0x8, }, { .uname = "DCT0_PAGE_TABLE_CLOSED", .udesc = "DCT0 page table is closed due to row inactivity", .ucode = 0x10, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x1f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam14h_memory_controller_slot_misses[]={ { .uname = "DCT0_RBD", .udesc = "DCT0 RBD", .ucode = 0x10, }, { .uname = "DCT0_PREFETCH", .udesc = "DCT0 prefetch", .ucode = 0x40, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x50, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam14h_memory_controller_rbd_queue_events[]={ { .uname = "DCQ_BYPASS_MAX", .udesc = "DCQ_BYPASS_MAX counter reached", .ucode = 0x4, }, { .uname = "BANK_CLOSED", .udesc = "Bank is closed due to bank conflict with an outstanding request in the RBD queue", .ucode = 0x8, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xc, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam14h_thermal_status[]={ { .uname = "MEMHOT_L", .udesc = "MEMHOT_L assertions", .ucode = 0x1, }, { .uname = "HTC_TRANSITION", .udesc = "Number of times HTC transitions from inactive to active", .ucode = 0x4, }, { .uname = "CLOCKS_HTC_P_STATE_INACTIVE", .udesc = "Number of clocks HTC P-state is inactive.", .ucode = 0x20, }, { .uname = "CLOCKS_HTC_P_STATE_ACTIVE", .udesc = "Number of clocks HTC P-state is active", .ucode = 0x40, }, { .uname = "PROCHOT_L", .udesc = "PROCHOT_L asserted by an external source and the assertion causes a P-state change", .ucode = 0x80, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xc5, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam14h_cpu_io_requests_to_memory_io[]={ { .uname = "I_O_TO_I_O", .udesc = "IO to IO", .ucode = 0x1, }, { .uname = "I_O_TO_MEM", .udesc = "IO to Mem", .ucode = 0x2, }, { .uname = "CPU_TO_I_O", .udesc = "CPU to IO", .ucode = 0x4, }, { .uname = "CPU_TO_MEM", .udesc = "CPU to Mem", .ucode = 0x8, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xf, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam14h_cache_block[]={ { .uname = "VICTIM_WRITEBACK", .udesc = "Victim Block (Writeback)", .ucode = 0x1, }, { .uname = "DCACHE_LOAD_MISS", .udesc = "Read Block (Dcache load miss refill)", .ucode = 0x4, }, { .uname = "SHARED_ICACHE_REFILL", .udesc = "Read Block Shared (Icache refill)", .ucode = 0x8, }, { .uname = "READ_BLOCK_MODIFIED", .udesc = "Read Block Modified (Dcache store miss refill)", .ucode = 0x10, }, { .uname = "CHANGE_TO_DIRTY", .udesc = "Change-to-Dirty (first store to clean block already in cache)", .ucode = 0x20, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3d, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam14h_sized_commands[]={ { .uname = "NON_POSTED_WRITE_BYTE", .udesc = "Non-Posted SzWr Byte (1-32 bytes) Legacy or mapped IO, typically 1-4 bytes", .ucode = 0x1, }, { .uname = "NON_POSTED_WRITE_DWORD", .udesc = "Non-Posted SzWr DW (1-16 dwords) Legacy or mapped IO, typically 1 DWORD", .ucode = 0x2, }, { .uname = "POSTED_WRITE_BYTE", .udesc = "Posted SzWr Byte (1-32 bytes) Subcache-line DMA writes, size varies; also flushes of partially-filled Write Combining buffer", .ucode = 0x4, }, { .uname = "POSTED_WRITE_DWORD", .udesc = "Posted SzWr DW (1-16 dwords) Block-oriented DMA writes, often cache-line sized; also processor Write Combining buffer flushes", .ucode = 0x8, }, { .uname = "READ_BYTE_4_BYTES", .udesc = "SzRd Byte (4 bytes) Legacy or mapped IO", .ucode = 0x10, }, { .uname = "READ_DWORD_1_16_DWORDS", .udesc = "SzRd DW (1-16 dwords) Block-oriented DMA reads, typically cache-line size", .ucode = 0x20, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam14h_probe[]={ { .uname = "MISS", .udesc = "Probe miss", .ucode = 0x1, }, { .uname = "HIT_CLEAN", .udesc = "Probe hit clean", .ucode = 0x2, }, { .uname = "HIT_DIRTY_NO_MEMORY_CANCEL", .udesc = "Probe hit dirty without memory cancel (probed by Sized Write or Change2Dirty)", .ucode = 0x4, }, { .uname = "HIT_DIRTY_WITH_MEMORY_CANCEL", .udesc = "Probe hit dirty with memory cancel (probed by DMA read or cache refill request)", .ucode = 0x8, }, { .uname = "UPSTREAM_HIGH_PRIO_READS", .udesc = "Upstream high priority reads", .ucode = 0x10, }, { .uname = "UPSTREAM_LOW_PRIO_READS", .udesc = "Upstream low priority reads", .ucode = 0x20, }, { .uname = "UPSTREAM_LOW_PRIO_WRITES", .udesc = "Upstream non-ISOC writes", .ucode = 0x80, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xbf, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam14h_dev_events[]={ { .uname = "HIT", .udesc = "DEV hit", .ucode = 0x10, }, { .uname = "MISS", .udesc = "DEV miss", .ucode = 0x20, }, { .uname = "ERROR", .udesc = "DEV error", .ucode = 0x40, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x70, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam14h_memory_controller_requests[]={ { .uname = "32_BYTES_WRITES", .udesc = "32 Bytes Sized Writes", .ucode = 0x8, }, { .uname = "64_BYTES_WRITES", .udesc = "64 Bytes Sized Writes", .ucode = 0x10, }, { .uname = "32_BYTES_READS", .udesc = "32 Bytes Sized Reads", .ucode = 0x20, }, { .uname = "64_BYTES_READS", .udesc = "64 Byte Sized Reads", .ucode = 0x40, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x78, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam14h_sideband_signals_special_signals[]={ { .uname = "STOPGRANT", .udesc = "Stopgrant", .ucode = 0x2, }, { .uname = "SHUTDOWN", .udesc = "Shutdown", .ucode = 0x4, }, { .uname = "WBINVD", .udesc = "Wbinvd", .ucode = 0x8, }, { .uname = "INVD", .udesc = "Invd", .ucode = 0x10, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x1c, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam14h_interrupt_events[]={ { .uname = "FIXED_AND_LPA", .udesc = "Fixed and LPA", .ucode = 0x1, }, { .uname = "LPA", .udesc = "LPA", .ucode = 0x2, }, { .uname = "SMI", .udesc = "SMI", .ucode = 0x4, }, { .uname = "NMI", .udesc = "NMI", .ucode = 0x8, }, { .uname = "INIT", .udesc = "INIT", .ucode = 0x10, }, { .uname = "STARTUP", .udesc = "STARTUP", .ucode = 0x20, }, { .uname = "INT", .udesc = "INT", .ucode = 0x40, }, { .uname = "EOI", .udesc = "EOI", .ucode = 0x80, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xff, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam14h_pdc_miss[]={ { .uname = "HOST_PDE_LEVEL", .udesc = "Host PDE level", .ucode = 0x1, }, { .uname = "HOST_PDPE_LEVEL", .udesc = "Host PDPE level", .ucode = 0x2, }, { .uname = "HOST_PML4E_LEVEL", .udesc = "Host PML4E level", .ucode = 0x4, }, { .uname = "GUEST_PDE_LEVEL", .udesc = "Guest PDE level", .ucode = 0x10, }, { .uname = "GUEST_PDPE_LEVEL", .udesc = "Guest PDPE level", .ucode = 0x20, }, { .uname = "GUEST_PML4E_LEVEL", .udesc = "Guest PML4E level", .ucode = 0x40, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x67, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_entry_t amd64_fam14h_pe[]={ { .name = "DISPATCHED_FPU", .desc = "Number of uops dispatched to FPU execution pipelines", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x0, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_dispatched_fpu), .ngrp = 1, .umasks = amd64_fam14h_dispatched_fpu, }, { .name = "CYCLES_NO_FPU_OPS_RETIRED", .desc = "Cycles in which the FPU is Empty", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x1, }, { .name = "DISPATCHED_FPU_OPS_FAST_FLAG", .desc = "Dispatched Fast Flag FPU Operations", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x2, }, { .name = "RETIRED_SSE_OPERATIONS", .desc = "Retired SSE Operations", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x3, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_retired_sse_operations), .ngrp = 1, .umasks = amd64_fam14h_retired_sse_operations, }, { .name = "RETIRED_MOVE_OPS", .desc = "Retired Move Ops", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x4, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_retired_move_ops), .ngrp = 1, .umasks = amd64_fam14h_retired_move_ops, }, { .name = "RETIRED_SERIALIZING_OPS", .desc = "Retired Serializing Ops", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x5, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_retired_serializing_ops), .ngrp = 1, .umasks = amd64_fam14h_retired_serializing_ops, }, { .name = "RETIRED_X87_FPU_OPS", .desc = "Number of x87 floating points ops that have retired", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x11, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_retired_x87_fpu_ops), .ngrp = 1, .umasks = amd64_fam14h_retired_x87_fpu_ops, }, { .name = "SEGMENT_REGISTER_LOADS", .desc = "Segment Register Loads", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x20, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_segment_register_loads), .ngrp = 1, .umasks = amd64_fam14h_segment_register_loads, }, { .name = "PIPELINE_RESTART_DUE_TO_SELF_MODIFYING_CODE", .desc = "Pipeline Restart Due to Self-Modifying Code", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x21, }, { .name = "PIPELINE_RESTART_DUE_TO_PROBE_HIT", .desc = "Pipeline Restart Due to Probe Hit", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x22, }, { .name = "RSQ_FULL", .desc = "Number of cycles that the RSQ holds retired stores. This buffer holds the stores waiting to retired as well as requests that missed the data cache and waiting on a refill", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x23, }, { .name = "LOCKED_OPS", .desc = "Locked Operations", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x24, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_locked_ops), .ngrp = 1, .umasks = amd64_fam14h_locked_ops, }, { .name = "RETIRED_CLFLUSH_INSTRUCTIONS", .desc = "Retired CLFLUSH Instructions", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x26, }, { .name = "RETIRED_CPUID_INSTRUCTIONS", .desc = "Retired CPUID Instructions", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x27, }, { .name = "CANCELLED_STORE_TO_LOAD_FORWARD_OPERATIONS", .desc = "Cancelled Store to Load Forward Operations", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x2a, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_cancelled_store_to_load_forward_operations), .ngrp = 1, .umasks = amd64_fam14h_cancelled_store_to_load_forward_operations, }, { .name = "DATA_CACHE_ACCESSES", .desc = "Data Cache Accesses", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x40, }, { .name = "DATA_CACHE_MISSES", .desc = "Data Cache Misses", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x41, }, { .name = "DATA_CACHE_REFILLS", .desc = "Data Cache Refills from L2 or Northbridge", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x42, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_data_cache_refills), .ngrp = 1, .umasks = amd64_fam14h_data_cache_refills, }, { .name = "DATA_CACHE_REFILLS_FROM_NB", .desc = "Data Cache Refills from the Northbridge", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x43, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_data_cache_refills_from_nb), .ngrp = 1, .umasks = amd64_fam14h_data_cache_refills_from_nb, }, { .name = "DATA_CACHE_LINES_EVICTED", .desc = "Data Cache Lines Evicted", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x44, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_data_cache_lines_evicted), .ngrp = 1, .umasks = amd64_fam14h_data_cache_lines_evicted, }, { .name = "L1_DTLB_MISS_AND_L2_DTLB_HIT", .desc = "Number of data cache accesses that miss in the L1 DTLB and hit the L2 DTLB. This is a speculative event", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x45, }, { .name = "DTLB_MISS", .desc = "L1 DTLB and L2 DTLB Miss", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x46, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_dtlb_miss), .ngrp = 1, .umasks = amd64_fam14h_dtlb_miss, }, { .name = "MISALIGNED_ACCESSES", .desc = "Misaligned Accesses", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x47, }, { .name = "PREFETCH_INSTRUCTIONS_DISPATCHED", .desc = "Prefetch Instructions Dispatched", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x4b, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_prefetch_instructions_dispatched), .ngrp = 1, .umasks = amd64_fam14h_prefetch_instructions_dispatched, }, { .name = "DCACHE_MISSES_BY_LOCKED_INSTRUCTIONS", .desc = "DCACHE Misses by Locked Instructions", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x4c, }, { .name = "L1_DTLB_HIT", .desc = "L1 DTLB Hit", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x4d, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_l1_dtlb_hit), .ngrp = 1, .umasks = amd64_fam14h_l1_dtlb_hit, }, { .name = "DCACHE_SW_PREFETCHES", .desc = "Number of software prefetches that do not cause an actual data cache refill", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x52, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_dcache_sw_prefetches), .ngrp = 1, .umasks = amd64_fam14h_dcache_sw_prefetches, }, { .name = "GLOBAL_TLB_FLUSHES", .desc = "Global TLB Flushes", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x54, }, { .name = "MEMORY_REQUESTS", .desc = "Memory Requests by Type", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x65, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_memory_requests), .ngrp = 1, .umasks = amd64_fam14h_memory_requests, }, { .name = "MAB_REQUESTS", .desc = "Number of L1 I-cache and D-cache misses per buffer. Average latency by combining with MAB_WAIT_CYCLES.", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x68, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_mab_requests), .ngrp = 1, .umasks = amd64_fam14h_mab_requests, }, { .name = "MAB_WAIT_CYCLES", .desc = "Latency of L1 I-cache and D-cache misses per buffer. Average latency by combining with MAB_REQUESTS.", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x69, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_mab_requests), .ngrp = 1, .umasks = amd64_fam14h_mab_requests, /* identical to actual umasks list for this event */ }, { .name = "SYSTEM_READ_RESPONSES", .desc = "Northbridge Read Responses by Coherency State", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x6c, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_system_read_responses), .ngrp = 1, .umasks = amd64_fam14h_system_read_responses, }, { .name = "CPU_CLK_UNHALTED", .desc = "CPU Clocks not Halted", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x76, }, { .name = "REQUESTS_TO_L2", .desc = "Requests to L2 Cache", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x7d, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_requests_to_l2), .ngrp = 1, .umasks = amd64_fam14h_requests_to_l2, }, { .name = "L2_CACHE_MISS", .desc = "L2 Cache Misses", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x7e, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_l2_cache_miss), .ngrp = 1, .umasks = amd64_fam14h_l2_cache_miss, }, { .name = "L2_FILL_WRITEBACK", .desc = "L2 Fill/Writeback", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x7f, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_l2_fill_writeback), .ngrp = 1, .umasks = amd64_fam14h_l2_fill_writeback, }, { .name = "INSTRUCTION_CACHE_FETCHES", .desc = "Instruction Cache Fetches", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x80, }, { .name = "INSTRUCTION_CACHE_MISSES", .desc = "Instruction Cache Misses", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x81, }, { .name = "INSTRUCTION_CACHE_REFILLS_FROM_L2", .desc = "Instruction Cache Refills from L2", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x82, }, { .name = "INSTRUCTION_CACHE_REFILLS_FROM_SYSTEM", .desc = "Instruction Cache Refills from System", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x83, }, { .name = "L1_ITLB_MISS_AND_L2_ITLB_MISS", .desc = "L1 ITLB Miss and L2 ITLB Miss", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x85, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_l1_itlb_miss_and_l2_itlb_miss), .ngrp = 1, .umasks = amd64_fam14h_l1_itlb_miss_and_l2_itlb_miss, }, { .name = "INSTRUCTION_FETCH_STALL", .desc = "Instruction Fetch Stall", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x87, }, { .name = "RETURN_STACK_HITS", .desc = "Return Stack Hits", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x88, }, { .name = "RETURN_STACK_OVERFLOWS", .desc = "Return Stack Overflows", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x89, }, { .name = "INSTRUCTION_CACHE_VICTIMS", .desc = "Instruction Cache Victims", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x8b, }, { .name = "INSTRUCTION_CACHE_LINES_INVALIDATED", .desc = "Instruction Cache Lines Invalidated", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x8c, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_instruction_cache_lines_invalidated), .ngrp = 1, .umasks = amd64_fam14h_instruction_cache_lines_invalidated, }, { .name = "ITLB_RELOADS", .desc = "ITLB Reloads", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x99, }, { .name = "ITLB_RELOADS_ABORTED", .desc = "ITLB Reloads Aborted", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x9a, }, { .name = "RETIRED_INSTRUCTIONS", .desc = "Retired Instructions", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xc0, }, { .name = "RETIRED_UOPS", .desc = "Retired uops", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xc1, }, { .name = "RETIRED_BRANCH_INSTRUCTIONS", .desc = "Retired Branch Instructions", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xc2, }, { .name = "RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS", .desc = "Retired Mispredicted Branch Instructions", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xc3, }, { .name = "RETIRED_TAKEN_BRANCH_INSTRUCTIONS", .desc = "Retired Taken Branch Instructions", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xc4, }, { .name = "RETIRED_TAKEN_BRANCH_INSTRUCTIONS_MISPREDICTED", .desc = "Retired Taken Branch Instructions Mispredicted", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xc5, }, { .name = "RETIRED_FAR_CONTROL_TRANSFERS", .desc = "Retired Far Control Transfers", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xc6, }, { .name = "RETIRED_BRANCH_RESYNCS", .desc = "Retired Branch Resyncs", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xc7, }, { .name = "RETIRED_NEAR_RETURNS", .desc = "Retired Near Returns", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xc8, }, { .name = "RETIRED_NEAR_RETURNS_MISPREDICTED", .desc = "Retired Near Returns Mispredicted", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xc9, }, { .name = "RETIRED_INDIRECT_BRANCHES_MISPREDICTED", .desc = "Retired Indirect Branches Mispredicted", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xca, }, { .name = "RETIRED_FLOATING_POINT_INSTRUCTIONS", .desc = "Retired SSE/MMX/FP Instructions", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xcb, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_retired_floating_point_instructions), .ngrp = 1, .umasks = amd64_fam14h_retired_floating_point_instructions, }, { .name = "INTERRUPTS_MASKED_CYCLES", .desc = "Interrupts-Masked Cycles", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xcd, }, { .name = "INTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDING", .desc = "Interrupts-Masked Cycles with Interrupt Pending", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xce, }, { .name = "INTERRUPTS_TAKEN", .desc = "Interrupts Taken", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xcf, }, { .name = "FPU_EXCEPTIONS", .desc = "FPU Exceptions", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xdb, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_fpu_exceptions), .ngrp = 1, .umasks = amd64_fam14h_fpu_exceptions, }, { .name = "DR0_BREAKPOINT_MATCHES", .desc = "DR0 Breakpoint Matches", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xdc, }, { .name = "DR1_BREAKPOINT_MATCHES", .desc = "DR1 Breakpoint Matches", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xdd, }, { .name = "DR2_BREAKPOINT_MATCHES", .desc = "DR2 Breakpoint Matches", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xde, }, { .name = "DR3_BREAKPOINT_MATCHES", .desc = "DR3 Breakpoint Matches", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xdf, }, { .name = "DRAM_ACCESSES_PAGE", .desc = "DRAM Accesses", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xe0, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_dram_accesses_page), .ngrp = 1, .umasks = amd64_fam14h_dram_accesses_page, }, { .name = "MEMORY_CONTROLLER_PAGE_TABLE", .desc = "Number of page table events in the local DRAM controller", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xe1, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_memory_controller_page_table), .ngrp = 1, .umasks = amd64_fam14h_memory_controller_page_table, }, { .name = "MEMORY_CONTROLLER_SLOT_MISSES", .desc = "Memory Controller DRAM Command Slots Missed", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xe2, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_memory_controller_slot_misses), .ngrp = 1, .umasks = amd64_fam14h_memory_controller_slot_misses, }, { .name = "MEMORY_CONTROLLER_RBD_QUEUE_EVENTS", .desc = "Memory Controller Bypass Counter Saturation", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xe4, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_memory_controller_rbd_queue_events), .ngrp = 1, .umasks = amd64_fam14h_memory_controller_rbd_queue_events, }, { .name = "THERMAL_STATUS", .desc = "Thermal Status", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xe8, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_thermal_status), .ngrp = 1, .umasks = amd64_fam14h_thermal_status, }, { .name = "CPU_IO_REQUESTS_TO_MEMORY_IO", .desc = "CPU/IO Requests to Memory/IO", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xe9, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_cpu_io_requests_to_memory_io), .ngrp = 1, .umasks = amd64_fam14h_cpu_io_requests_to_memory_io, }, { .name = "CACHE_BLOCK", .desc = "Cache Block Commands", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xea, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_cache_block), .ngrp = 1, .umasks = amd64_fam14h_cache_block, }, { .name = "SIZED_COMMANDS", .desc = "Sized Commands", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xeb, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_sized_commands), .ngrp = 1, .umasks = amd64_fam14h_sized_commands, }, { .name = "PROBE", .desc = "Probe Responses and Upstream Requests", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xec, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_probe), .ngrp = 1, .umasks = amd64_fam14h_probe, }, { .name = "DEV_EVENTS", .desc = "DEV Events", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xee, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_dev_events), .ngrp = 1, .umasks = amd64_fam14h_dev_events, }, { .name = "MEMORY_CONTROLLER_REQUESTS", .desc = "Memory Controller Requests", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x1f0, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_memory_controller_requests), .ngrp = 1, .umasks = amd64_fam14h_memory_controller_requests, }, { .name = "SIDEBAND_SIGNALS_SPECIAL_SIGNALS", .desc = "Sideband signals and special cycles", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x1e9, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_sideband_signals_special_signals), .ngrp = 1, .umasks = amd64_fam14h_sideband_signals_special_signals, }, { .name = "INTERRUPT_EVENTS", .desc = "Interrupt events", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x1ea, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_interrupt_events), .ngrp = 1, .umasks = amd64_fam14h_interrupt_events, }, { .name = "PDC_MISS", .desc = "PDC miss", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x162, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_pdc_miss), .ngrp = 1, .umasks = amd64_fam14h_pdc_miss, }, }; libpfm-4.9.0/lib/events/intel_snbep_unc_r3qpi_events.h0000664000175000017500000002232713223402656022720 0ustar eranianeranian/* * Copyright (c) 2012 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * This file has been automatically generated. * * PMU: snbep_unc_r3qpi (Intel SandyBridge-EP R3QPI uncore) */ static const intel_x86_umask_t snbep_unc_r3_iio_credits_acquired[]={ { .uname = "DRS", .udesc = "DRS", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "NCB", .udesc = "NCB", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "NCS", .udesc = "NCS", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t snbep_unc_r3_ring_ad_used[]={ { .uname = "CCW_EVEN", .udesc = "Counter-Clockwise and even ring polarity", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "CCW_ODD", .udesc = "Counter-Clockwise and odd ring polarity", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "CW_EVEN", .udesc = "Clockwise and even ring polarity", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "CW_ODD", .udesc = "Clockwise and odd ring polarity", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t snbep_unc_r3_ring_iv_used[]={ { .uname = "ANY", .udesc = "Any polarity", .ucode = 0xf00, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t snbep_unc_r3_rxr_bypassed[]={ { .uname = "AD", .udesc = "Ingress Bypassed", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t snbep_unc_r3_rxr_cycles_ne[]={ { .uname = "DRS", .udesc = "DRS Ingress queue", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "HOM", .udesc = "HOM Ingress queue", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "NCB", .udesc = "NCB Ingress queue", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "NCS", .udesc = "NCS Ingress queue", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "NDR", .udesc = "NDR Ingress queue", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "SNP", .udesc = "SNP Ingress queue", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t snbep_unc_r3_vn0_credits_reject[]={ { .uname = "DRS", .udesc = "Filter DRS message class", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "HOM", .udesc = "Filter HOM message class", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "NCB", .udesc = "Filter NCB message class", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "NCS", .udesc = "Filter NCS message class", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "NDR", .udesc = "Filter NDR message class", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "SNP", .udesc = "Filter SNP message class", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_entry_t intel_snbep_unc_r3_pe[]={ { .name = "UNC_R3_CLOCKTICKS", .desc = "Number of uclks in domain", .code = 0x1, .cntmsk = 0x7, .modmsk = SNBEP_UNC_R3QPI_ATTRS, }, { .name = "UNC_R3_IIO_CREDITS_ACQUIRED", .desc = "to IIO BL Credit Acquired", .code = 0x20, .cntmsk = 0x3, .ngrp = 1, .modmsk = SNBEP_UNC_R3QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_r3_iio_credits_acquired), .umasks = snbep_unc_r3_iio_credits_acquired }, { .name = "UNC_R3_IIO_CREDITS_REJECT", .desc = "to IIO BL Credit Rejected", .code = 0x21, .cntmsk = 0x3, .ngrp = 1, .modmsk = SNBEP_UNC_R3QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_r3_iio_credits_acquired), .umasks = snbep_unc_r3_iio_credits_acquired /* shared */ }, { .name = "UNC_R3_IIO_CREDITS_USED", .desc = "to IIO BL Credit In Use", .code = 0x22, .cntmsk = 0x3, .ngrp = 1, .modmsk = SNBEP_UNC_R3QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_r3_iio_credits_acquired), .umasks = snbep_unc_r3_iio_credits_acquired /* shared */ }, { .name = "UNC_R3_RING_AD_USED", .desc = "R3 AD Ring in Use", .code = 0x7, .cntmsk = 0x7, .ngrp = 1, .modmsk = SNBEP_UNC_R3QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_r3_ring_ad_used), .umasks = snbep_unc_r3_ring_ad_used }, { .name = "UNC_R3_RING_AK_USED", .desc = "R3 AK Ring in Use", .code = 0x8, .cntmsk = 0x7, .ngrp = 1, .modmsk = SNBEP_UNC_R3QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_r3_ring_ad_used), .umasks = snbep_unc_r3_ring_ad_used /* shared */ }, { .name = "UNC_R3_RING_BL_USED", .desc = "R3 BL Ring in Use", .code = 0x9, .cntmsk = 0x7, .ngrp = 1, .modmsk = SNBEP_UNC_R3QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_r3_ring_ad_used), .umasks = snbep_unc_r3_ring_ad_used /* shared */ }, { .name = "UNC_R3_RING_IV_USED", .desc = "R3 IV Ring in Use", .code = 0xa, .cntmsk = 0x7, .ngrp = 1, .modmsk = SNBEP_UNC_R3QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_r3_ring_iv_used), .umasks = snbep_unc_r3_ring_iv_used }, { .name = "UNC_R3_RXR_BYPASSED", .desc = "Ingress Bypassed", .code = 0x12, .cntmsk = 0x3, .ngrp = 1, .modmsk = SNBEP_UNC_R3QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_r3_rxr_bypassed), .umasks = snbep_unc_r3_rxr_bypassed }, { .name = "UNC_R3_RXR_CYCLES_NE", .desc = "Ingress Cycles Not Empty", .code = 0x10, .cntmsk = 0x3, .ngrp = 1, .modmsk = SNBEP_UNC_R3QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_r3_rxr_cycles_ne), .umasks = snbep_unc_r3_rxr_cycles_ne }, { .name = "UNC_R3_RXR_INSERTS", .desc = "Ingress Allocations", .code = 0x11, .cntmsk = 0x3, .ngrp = 1, .modmsk = SNBEP_UNC_R3QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_r3_rxr_cycles_ne), .umasks = snbep_unc_r3_rxr_cycles_ne /* shared */ }, { .name = "UNC_R3_RXR_OCCUPANCY", .desc = "Ingress Occupancy Accumulator", .code = 0x13, .cntmsk = 0x1, .ngrp = 1, .modmsk = SNBEP_UNC_R3QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_r3_rxr_cycles_ne), .umasks = snbep_unc_r3_rxr_cycles_ne /* shared */ }, { .name = "UNC_R3_TXR_CYCLES_FULL", .desc = "Egress cycles full", .code = 0x25, .cntmsk = 0x3, .modmsk = SNBEP_UNC_R3QPI_ATTRS, }, { .name = "UNC_R3_TXR_INSERTS", .desc = "Egress allocations", .code = 0x24, .cntmsk = 0x3, .modmsk = SNBEP_UNC_R3QPI_ATTRS, }, { .name = "UNC_R3_TXR_NACK", .desc = "Egress Nack", .code = 0x26, .cntmsk = 0x3, .modmsk = SNBEP_UNC_R3QPI_ATTRS, }, { .name = "UNC_R3_VN0_CREDITS_REJECT", .desc = "VN0 Credit Acquisition Failed on DRS", .code = 0x37, .cntmsk = 0x3, .ngrp = 1, .modmsk = SNBEP_UNC_R3QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_r3_vn0_credits_reject), .umasks = snbep_unc_r3_vn0_credits_reject }, { .name = "UNC_R3_VN0_CREDITS_USED", .desc = "VN0 Credit Used", .code = 0x36, .cntmsk = 0x3, .ngrp = 1, .modmsk = SNBEP_UNC_R3QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_r3_vn0_credits_reject), .umasks = snbep_unc_r3_vn0_credits_reject /* shared */ }, { .name = "UNC_R3_VNA_CREDITS_ACQUIRED", .desc = "VNA credit Acquisitions", .code = 0x33, .cntmsk = 0x3, .modmsk = SNBEP_UNC_R3QPI_ATTRS, }, { .name = "UNC_R3_VNA_CREDITS_REJECT", .desc = "VNA Credit Reject", .code = 0x34, .cntmsk = 0x3, .ngrp = 1, .modmsk = SNBEP_UNC_R3QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_r3_vn0_credits_reject), .umasks = snbep_unc_r3_vn0_credits_reject /* shared */ }, { .name = "UNC_R3_VNA_CREDIT_CYCLES_OUT", .desc = "Cycles with no VNA credits available", .code = 0x31, .cntmsk = 0x3, .modmsk = SNBEP_UNC_R3QPI_ATTRS, }, { .name = "UNC_R3_VNA_CREDIT_CYCLES_USED", .desc = "Cycles with 1 or more VNA credits in use", .code = 0x32, .cntmsk = 0x3, .modmsk = SNBEP_UNC_R3QPI_ATTRS, }, }; libpfm-4.9.0/lib/events/torrent_events.h0000664000175000017500000011443313223402656020130 0ustar eranianeranian/* Power Torrent PMU event codes */ #ifndef __POWER_TORRENT_EVENTS_H__ #define __POWER_TORRENT_EVENTS_H__ /* PRELIMINARY EVENT ENCODING * 0x0000_0000 - 0x00FF_FFFF = PowerPC core events * 0x0100_0000 - 0x01FF_FFFF = Torrent events * 0x0200_0000 - 0xFFFF_FFFF = reserved * For Torrent events: * Reserve encodings 0x0..0x00FF_FFFF for core PowerPC events. * For Torrent events * 0x00F0_0000 = Torrent PMU id * 0x000F_0000 = PMU unit number (e.g. 0 for MCD0, 1 for MCD1) * 0x0000_FF00 = virtual counter number (unused on MCD) * 0x0000_00FF = PMC mux value (unused on Util, MMU, CAU) * (Note that some of these fields are wider than necessary) * * The upper bits 0xFFFF_FFFF_0000_0000 are reserved for attribute * fields. */ #define PMU_SPACE_MASK 0xFF000000 #define POWERPC_CORE_SPACE 0x00000000 #define TORRENT_SPACE 0x01000000 #define IS_CORE_EVENT(x) ((x & PMU_SPACE_MASK) == POWERPC_CORE_SPACE) #define IS_TORRENT_EVENT(x) ((x & PMU_SPACE_MASK) == TORRENT_SPACE) #define TORRENT_PMU_SHIFT 20 #define TORRENT_PMU_MASK (0xF << TORRENT_PMU_SHIFT) #define TORRENT_PMU_GET(x) ((x & TORRENT_PMU_MASK) >> TORRENT_PMU_SHIFT) #define TORRENT_UNIT_SHIFT 16 #define TORRENT_UNIT_MASK (0xF << TORRENT_UNIT_SHIFT) #define TORRENT_UNIT_GET(x) ((x & TORRENT_UNIT_MASK) >> TORRENT_UNIT_SHIFT) #define TORRENT_VIRT_CTR_SHIFT 8 #define TORRENT_VIRT_CTR_MASK (0xFF << TORRENT_VIRT_CTR_SHIFT) #define TORRENT_VIRT_CTR_GET(x) ((x & TORRENT_VIRT_CTR_MASK) >> TORRENT_VIRT_CTR_SHIFT) #define TORRENT_MUX_SHIFT 0 #define TORRENT_MUX_MASK 0xFF #define TORRENT_MUX_GET(x) ((x & TORRENT_MUX_MASK) >> TORRENT_MUX_SHIFT) #define TORRENT_PBUS_WXYZ_ID 0x0 #define TORRENT_PBUS_LL_ID 0x1 #define TORRENT_PBUS_MCD_ID 0x2 #define TORRENT_PBUS_UTIL_ID 0x3 #define TORRENT_MMU_ID 0x4 #define TORRENT_CAU_ID 0x5 #define TORRENT_LAST_ID (TORRENT_CAU_ID) #define TORRENT_NUM_PMU_TYPES (TORRENT_LAST_ID + 1) /* TORRENT_DEVEL_NUM_PMU_TYPES is so that we don't try to call functions in * PMUs which are not currently supported. When all Torrent PMUs are * supported, we NEED to remove this definition and replace the usages of it * with TORRENT_NUM_PMU_TYPES. */ #define TORRENT_DEVEL_NUM_PMU_TYPES (TORRENT_PBUS_WXYZ_ID + 1) #define TORRENT_PMU(pmu) (TORRENT_SPACE | \ TORRENT_##pmu##_ID << TORRENT_PMU_SHIFT) #define TORRENT_PBUS_WXYZ TORRENT_PMU(PBUS_WXYZ) #define TORRENT_PBUS_LL TORRENT_PMU(PBUS_LL) #define TORRENT_PBUS_MCD TORRENT_PMU(PBUS_MCD) #define TORRENT_PBUS_UTIL TORRENT_PMU(PBUS_UTIL) #define TORRENT_MMU TORRENT_PMU(MMU) #define TORRENT_CAU TORRENT_PMU(CAU) #define COUNTER_W (0 << TORRENT_VIRT_CTR_SHIFT) #define COUNTER_X (1 << TORRENT_VIRT_CTR_SHIFT) #define COUNTER_Y (2 << TORRENT_VIRT_CTR_SHIFT) #define COUNTER_Z (3 << TORRENT_VIRT_CTR_SHIFT) #define COUNTER_LL0 (0 << TORRENT_VIRT_CTR_SHIFT) #define COUNTER_LL1 (1 << TORRENT_VIRT_CTR_SHIFT) #define COUNTER_LL2 (2 << TORRENT_VIRT_CTR_SHIFT) #define COUNTER_LL3 (3 << TORRENT_VIRT_CTR_SHIFT) #define COUNTER_LL4 (4 << TORRENT_VIRT_CTR_SHIFT) #define COUNTER_LL5 (5 << TORRENT_VIRT_CTR_SHIFT) #define COUNTER_LL6 (6 << TORRENT_VIRT_CTR_SHIFT) /* Attributes */ #define TORRENT_ATTR_MCD_TYPE_SHIFT 32 #define TORRENT_ATTR_MCD_TYPE_MASK (0x3ULL << TORRENT_ATTR_MCD_TYPE_SHIFT) #define TORRENT_ATTR_UTIL_SEL_SHIFT 32 #define TORRENT_ATTR_UTIL_SEL_MASK (0x3ULL << TORRENT_ATTR_UTIL_SEL_SHIFT) #define TORRENT_ATTR_UTIL_CMP_SHIFT 34 #define TORRENT_ATTR_UTIL_CMP_MASK (0x1FULL << TORRENT_ATTR_UTIL_CMP_SHIFT) static const pme_torrent_entry_t torrent_pe[] = { { .pme_name = "PM_PBUS_W_DISABLED", .pme_code = TORRENT_PBUS_WXYZ | COUNTER_W | 0x0, .pme_desc = "The W Link event counter is disabled" }, { .pme_name = "PM_PBUS_W_IN_IDLE", .pme_code = TORRENT_PBUS_WXYZ | COUNTER_W | 0x1, .pme_desc = "Bus cycles that the W Link \"in\" channel is idle" }, { .pme_name = "PM_PBUS_W_IN_CMDRSP", .pme_code = TORRENT_PBUS_WXYZ | COUNTER_W | 0x2, .pme_desc = "Number of commands, partial responses, and combined responses received on the W Link \"in\" channel (Note: multiple events can occur in one cycle)" }, { .pme_name = "PM_PBUS_W_IN_DATA", .pme_code = TORRENT_PBUS_WXYZ | COUNTER_W | 0x3, .pme_desc = "Bus cycles that the W Link \"in\" channel is receiving data or a data header" }, { .pme_name = "PM_PBUS_W_OUT_IDLE", .pme_code = TORRENT_PBUS_WXYZ | COUNTER_W | 0x5, .pme_desc = "Bus cycles that the W Link \"out\" channel is idle" }, { .pme_name = "PM_PBUS_W_OUT_CMDRSP", .pme_code = TORRENT_PBUS_WXYZ | COUNTER_W | 0x6, .pme_desc = "Number of commands, partial responses, and combined responses sent on the W Link \"out\" channel (Note: multiple events can occur in one cycle)" }, { .pme_name = "PM_PBUS_W_OUT_DATA", .pme_code = TORRENT_PBUS_WXYZ | COUNTER_W | 0x7, .pme_desc = "Bus cycles that the W Link \"out\" channel is sending data or a data header" }, { .pme_name = "PM_PBUS_X_DISABLED", .pme_code = TORRENT_PBUS_WXYZ | COUNTER_X | 0x0, .pme_desc = "The X Link event counter is disabled" }, { .pme_name = "PM_PBUS_X_IN_IDLE", .pme_code = TORRENT_PBUS_WXYZ | COUNTER_X | 0x1, .pme_desc = "Bus cycles that the X Link \"in\" channel is idle" }, { .pme_name = "PM_PBUS_X_IN_CMDRSP", .pme_code = TORRENT_PBUS_WXYZ | COUNTER_X | 0x2, .pme_desc = "Number of commands, partial responses, and combined responses received on the X Link \"in\" channel (Note: multiple events can occur in one cycle)" }, { .pme_name = "PM_PBUS_X_IN_DATA", .pme_code = TORRENT_PBUS_WXYZ | COUNTER_X | 0x3, .pme_desc = "Bus cycles that the X Link \"in\" channel is receiving data or a data header" }, { .pme_name = "PM_PBUS_X_OUT_IDLE", .pme_code = TORRENT_PBUS_WXYZ | COUNTER_X | 0x5, .pme_desc = "Bus cycles that the X Link \"out\" channel is idle" }, { .pme_name = "PM_PBUS_X_OUT_CMDRSP", .pme_code = TORRENT_PBUS_WXYZ | COUNTER_X | 0x6, .pme_desc = "Number of commands, partial responses, and combined responses sent on the X Link \"out\" channel (Note: multiple events can occur in one cycle)" }, { .pme_name = "PM_PBUS_X_OUT_DATA", .pme_code = TORRENT_PBUS_WXYZ | COUNTER_X | 0x7, .pme_desc = "Bus cycles that the X Link \"out\" channel is sending data or a data header" }, { .pme_name = "PM_PBUS_Y_DISABLED", .pme_code = TORRENT_PBUS_WXYZ | COUNTER_Y | 0x0, .pme_desc = "The Y Link event counter is disabled" }, { .pme_name = "PM_PBUS_Y_IN_IDLE", .pme_code = TORRENT_PBUS_WXYZ | COUNTER_Y | 0x1, .pme_desc = "Bus cycles that the Y Link \"in\" channel is idle" }, { .pme_name = "PM_PBUS_Y_IN_CMDRSP", .pme_code = TORRENT_PBUS_WXYZ | COUNTER_Y | 0x2, .pme_desc = "Number of commands, partial responses, and combined responses received on the Y Link \"in\" channel (Note: multiple events can occur in one cycle)" }, { .pme_name = "PM_PBUS_Y_IN_DATA", .pme_code = TORRENT_PBUS_WXYZ | COUNTER_Y | 0x3, .pme_desc = "Bus cycles that the Y Link \"in\" channel is receiving data or a data header" }, { .pme_name = "PM_PBUS_Y_OUT_IDLE", .pme_code = TORRENT_PBUS_WXYZ | COUNTER_Y | 0x5, .pme_desc = "Bus cycles that the Y Link \"out\" channel is idle", }, { .pme_name = "PM_PBUS_Y_OUT_CMDRSP", .pme_code = TORRENT_PBUS_WXYZ | COUNTER_Y | 0x6, .pme_desc = "Number of commands, partial responses, and combined responses sent on the Y Link \"out\" channel (Note: multiple events can occur in one cycle)" }, { .pme_name = "PM_PBUS_Y_OUT_DATA", .pme_code = TORRENT_PBUS_WXYZ | COUNTER_Y | 0x7, .pme_desc = "Bus cycles that the W Link \"out\" channel is sending data or a data header" }, { .pme_name = "PM_PBUS_Z_DISABLED", .pme_code = TORRENT_PBUS_WXYZ | COUNTER_Z | 0x0, .pme_desc = "The Z Link event counter is disabled" }, { .pme_name = "PM_PBUS_Z_IN_IDLE", .pme_code = TORRENT_PBUS_WXYZ | COUNTER_Z | 0x1, .pme_desc = "Bus cycles that the Z Link \"in\" channel is idle" }, { .pme_name = "PM_PBUS_Z_IN_CMDRSP", .pme_code = TORRENT_PBUS_WXYZ | COUNTER_Z | 0x2, .pme_desc = "Number of commands, partial responses, and combined responses received on the Z Link \"in\" channel (Note: multiple events can occur in one cycle)" }, { .pme_name = "PM_PBUS_Z_IN_DATA", .pme_code = TORRENT_PBUS_WXYZ | COUNTER_Z | 0x3, .pme_desc = "Bus cycles that the Z Link \"in\" channel is receiving data or a data header" }, { .pme_name = "PM_PBUS_Z_OUT_IDLE", .pme_code = TORRENT_PBUS_WXYZ | COUNTER_Z | 0x5, .pme_desc = "Bus cycles that the Z Link \"out\" channel is idle" }, { .pme_name = "PM_PBUS_Z_OUT_CMDRSP", .pme_code = TORRENT_PBUS_WXYZ | COUNTER_Z | 0x6, .pme_desc = "Number of commands, partial responses, and combined responses sent on the Z Link \"out\" channel (Note: multiple events can occur in one cycle)" }, { .pme_name = "PM_PBUS_Z_OUT_DATA", .pme_code = TORRENT_PBUS_WXYZ | COUNTER_Z | 0x7, .pme_desc = "Bus cycles that the Z Link \"out\" channel is sending data or a data header" }, { .pme_name = "PM_PBUS_LL0_DISABLED", .pme_code = TORRENT_PBUS_LL | COUNTER_LL0 | 0x0, .pme_desc = "The Local Link 0 event counter is disabled" }, { .pme_name = "PM_PBUS_LL0_IN_IDLE", .pme_code = TORRENT_PBUS_LL | COUNTER_LL0 | 0x1, .pme_desc = "Bus cycles that the Local Link 0 \"in\" channel is idle" }, { .pme_name = "PM_PBUS_LL0_IN_CMDRSP", .pme_code = TORRENT_PBUS_LL | COUNTER_LL0 | 0x2, .pme_desc = "Number of commands, partial responses, and combined responses received on the Local Link 0 \"in\" channel (Note: multiple events can occur in one cycle)" }, { .pme_name = "PM_PBUS_LL0_IN_DATA", .pme_code = TORRENT_PBUS_LL | COUNTER_LL0 | 0x3, .pme_desc = "Bus cycles that the Local Link 0 \"in\" channel is receiving data or a data header" }, { .pme_name = "PM_PBUS_LL0_OUT_IDLE", .pme_code = TORRENT_PBUS_LL | COUNTER_LL0 | 0x5, .pme_desc = "Bus cycles that the Local Link 0 \"out\" channel is idle" }, { .pme_name = "PM_PBUS_LL0_OUT_CMDRSP", .pme_code = TORRENT_PBUS_LL | COUNTER_LL0 | 0x6, .pme_desc = "Number of commands, partial responses, and combined responses sent on the Local Link 0 \"out\" channel (Note: multiple events can occur in one cycle)" }, { .pme_name = "PM_PBUS_LL0_OUT_DATA", .pme_code = TORRENT_PBUS_LL | COUNTER_LL0 | 0x7, .pme_desc = "Bus cycles that the Local Link 0 \"out\" channel is sending data or a data header" }, { .pme_name = "PM_PBUS_LL0_IN_ISR", .pme_code = TORRENT_PBUS_LL | COUNTER_LL0 | 0x9, .pme_desc = "Bus cycles that the Local Link 0 \"in\" channel is receiving ISR data or an ISR data header" }, { .pme_name = "PM_PBUS_LL0_OUT_ISR", .pme_code = TORRENT_PBUS_LL | COUNTER_LL0 | 0xd, .pme_desc = "Bus cycles that the Local Link 0 \"out\" channel is sending ISR data or an ISR data header" }, { .pme_name = "PM_PBUS_LL1_DISABLED", .pme_code = TORRENT_PBUS_LL | COUNTER_LL1 | 0x0, .pme_desc = "The Local Link 1 event counter is disabled" }, { .pme_name = "PM_PBUS_LL1_IN_IDLE", .pme_code = TORRENT_PBUS_LL | COUNTER_LL1 | 0x1, .pme_desc = "Bus cycles that the Local Link 1 \"in\" channel is idle" }, { .pme_name = "PM_PBUS_LL1_IN_CMDRSP", .pme_code = TORRENT_PBUS_LL | COUNTER_LL1 | 0x2, .pme_desc = "Number of commands, partial responses, and combined responses received on the Local Link 1 \"in\" channel (Note: multiple events can occur in one cycle)" }, { .pme_name = "PM_PBUS_LL1_IN_DATA", .pme_code = TORRENT_PBUS_LL | COUNTER_LL1 | 0x3, .pme_desc = "Bus cycles that the Local Link 1 \"in\" channel is receiving data or a data header" }, { .pme_name = "PM_PBUS_LL1_OUT_IDLE", .pme_code = TORRENT_PBUS_LL | COUNTER_LL1 | 0x5, .pme_desc = "Bus cycles that the Local Link 1 \"out\" channel is idle" }, { .pme_name = "PM_PBUS_LL1_OUT_CMDRSP", .pme_code = TORRENT_PBUS_LL | COUNTER_LL1 | 0x6, .pme_desc = "Number of commands, partial responses, and combined responses sent on the Local Link 1 \"out\" channel (Note: multiple events can occur in one cycle)" }, { .pme_name = "PM_PBUS_LL1_OUT_DATA", .pme_code = TORRENT_PBUS_LL | COUNTER_LL1 | 0x7, .pme_desc = "Bus cycles that the Local Link 1 \"out\" channel is sending data or a data header" }, { .pme_name = "PM_PBUS_LL1_IN_ISR", .pme_code = TORRENT_PBUS_LL | COUNTER_LL1 | 0x9, .pme_desc = "Bus cycles that the Local Link 1 \"in\" channel is receiving ISR data or an ISR data header" }, { .pme_name = "PM_PBUS_LL1_OUT_ISR", .pme_code = TORRENT_PBUS_LL | COUNTER_LL1 | 0xd, .pme_desc = "Bus cycles that the Local Link 1 \"out\" channel is sending ISR data or an ISR data header" }, { .pme_name = "PM_PBUS_LL2_DISABLED", .pme_code = TORRENT_PBUS_LL | COUNTER_LL2 | 0x0, .pme_desc = "The Local Link 2 event counter is disabled" }, { .pme_name = "PM_PBUS_LL2_IN_IDLE", .pme_code = TORRENT_PBUS_LL | COUNTER_LL2 | 0x1, .pme_desc = "Bus cycles that the Local Link 2 \"in\" channel is idle" }, { .pme_name = "PM_PBUS_LL2_IN_CMDRSP", .pme_code = TORRENT_PBUS_LL | COUNTER_LL2 | 0x2, .pme_desc = "Number of commands, partial responses, and combined responses received on the Local Link 2 \"in\" channel (Note: multiple events can occur in one cycle)" }, { .pme_name = "PM_PBUS_LL2_IN_DATA", .pme_code = TORRENT_PBUS_LL | COUNTER_LL2 | 0x3, .pme_desc = "Bus cycles that the Local Link 2 \"in\" channel is receiving data or a data header" }, { .pme_name = "PM_PBUS_LL2_OUT_IDLE", .pme_code = TORRENT_PBUS_LL | COUNTER_LL2 | 0x5, .pme_desc = "Bus cycles that the Local Link 2 \"out\" channel is idle" }, { .pme_name = "PM_PBUS_LL2_OUT_CMDRSP", .pme_code = TORRENT_PBUS_LL | COUNTER_LL2 | 0x6, .pme_desc = "Number of commands, partial responses, and combined responses sent on the Local Link 2 \"out\" channel (Note: multiple events can occur in one cycle)" }, { .pme_name = "PM_PBUS_LL2_OUT_DATA", .pme_code = TORRENT_PBUS_LL | COUNTER_LL2 | 0x7, .pme_desc = "Bus cycles that the Local Link 2 \"out\" channel is sending data or a data header" }, { .pme_name = "PM_PBUS_LL2_IN_ISR", .pme_code = TORRENT_PBUS_LL | COUNTER_LL2 | 0x9, .pme_desc = "Bus cycles that the Local Link 2 \"in\" channel is receiving ISR data or an ISR data header" }, { .pme_name = "PM_PBUS_LL2_OUT_ISR", .pme_code = TORRENT_PBUS_LL | COUNTER_LL2 | 0xd, .pme_desc = "Bus cycles that the Local Link 2 \"out\" channel is sending ISR data or an ISR data header" }, { .pme_name = "PM_PBUS_LL3_DISABLED", .pme_code = TORRENT_PBUS_LL | COUNTER_LL3 | 0x0, .pme_desc = "The Local Link 3 event counter is disabled" }, { .pme_name = "PM_PBUS_LL3_IN_IDLE", .pme_code = TORRENT_PBUS_LL | COUNTER_LL3 | 0x1, .pme_desc = "Bus cycles that the Local Link 3 \"in\" channel is idle" }, { .pme_name = "PM_PBUS_LL3_IN_CMDRSP", .pme_code = TORRENT_PBUS_LL | COUNTER_LL3 | 0x2, .pme_desc = "Number of commands, partial responses, and combined responses received on the Local Link 3 \"in\" channel (Note: multiple events can occur in one cycle)" }, { .pme_name = "PM_PBUS_LL3_IN_DATA", .pme_code = TORRENT_PBUS_LL | COUNTER_LL3 | 0x3, .pme_desc = "Bus cycles that the Local Link 3 \"in\" channel is receiving data or a data header" }, { .pme_name = "PM_PBUS_LL3_OUT_IDLE", .pme_code = TORRENT_PBUS_LL | COUNTER_LL3 | 0x5, .pme_desc = "Bus cycles that the Local Link 3 \"out\" channel is idle" }, { .pme_name = "PM_PBUS_LL3_OUT_CMDRSP", .pme_code = TORRENT_PBUS_LL | COUNTER_LL3 | 0x6, .pme_desc = "Number of commands, partial responses, and combined responses sent on the Local Link 3 \"out\" channel (Note: multiple events can occur in one cycle)" }, { .pme_name = "PM_PBUS_LL3_OUT_DATA", .pme_code = TORRENT_PBUS_LL | COUNTER_LL3 | 0x7, .pme_desc = "Bus cycles that the Local Link 3 \"out\" channel is sending data or a data header" }, { .pme_name = "PM_PBUS_LL3_IN_ISR", .pme_code = TORRENT_PBUS_LL | COUNTER_LL3 | 0x9, .pme_desc = "Bus cycles that the Local Link 3 \"in\" channel is receiving ISR data or an ISR data header" }, { .pme_name = "PM_PBUS_LL3_OUT_ISR", .pme_code = TORRENT_PBUS_LL | COUNTER_LL3 | 0xd, .pme_desc = "Bus cycles that the Local Link 3 \"out\" channel is sending ISR data or an ISR data header" }, { .pme_name = "PM_PBUS_LL4_DISABLED", .pme_code = TORRENT_PBUS_LL | COUNTER_LL4 | 0x0, .pme_desc = "The Local Link 4 event counter is disabled" }, { .pme_name = "PM_PBUS_LL4_IN_IDLE", .pme_code = TORRENT_PBUS_LL | COUNTER_LL4 | 0x1, .pme_desc = "Bus cycles that the Local Link 4 \"in\" channel is idle" }, { .pme_name = "PM_PBUS_LL4_IN_CMDRSP", .pme_code = TORRENT_PBUS_LL | COUNTER_LL4 | 0x2, .pme_desc = "Number of commands, partial responses, and combined responses received on the Local Link 4 \"in\" channel (Note: multiple events can occur in one cycle)" }, { .pme_name = "PM_PBUS_LL4_IN_DATA", .pme_code = TORRENT_PBUS_LL | COUNTER_LL4 | 0x3, .pme_desc = "Bus cycles that the Local Link 4 \"in\" channel is receiving data or a data header" }, { .pme_name = "PM_PBUS_LL4_OUT_IDLE", .pme_code = TORRENT_PBUS_LL | COUNTER_LL4 | 0x5, .pme_desc = "Bus cycles that the Local Link 4 \"out\" channel is idle" }, { .pme_name = "PM_PBUS_LL4_OUT_CMDRSP", .pme_code = TORRENT_PBUS_LL | COUNTER_LL4 | 0x6, .pme_desc = "Number of commands, partial responses, and combined responses sent on the Local Link 4 \"out\" channel (Note: multiple events can occur in one cycle)" }, { .pme_name = "PM_PBUS_LL4_OUT_DATA", .pme_code = TORRENT_PBUS_LL | COUNTER_LL4 | 0x7, .pme_desc = "Bus cycles that the Local Link 4 \"out\" channel is sending data or a data header" }, { .pme_name = "PM_PBUS_LL4_IN_ISR", .pme_code = TORRENT_PBUS_LL | COUNTER_LL4 | 0x9, .pme_desc = "Bus cycles that the Local Link 4 \"in\" channel is receiving ISR data or an ISR data header" }, { .pme_name = "PM_PBUS_LL4_OUT_ISR", .pme_code = TORRENT_PBUS_LL | COUNTER_LL4 | 0xd, .pme_desc = "Bus cycles that the Local Link 4 \"out\" channel is sending ISR data or an ISR data header" }, { .pme_name = "PM_PBUS_LL5_DISABLED", .pme_code = TORRENT_PBUS_LL | COUNTER_LL5 | 0x0, .pme_desc = "The Local Link 5 event counter is disabled" }, { .pme_name = "PM_PBUS_LL5_IN_IDLE", .pme_code = TORRENT_PBUS_LL | COUNTER_LL5 | 0x1, .pme_desc = "Bus cycles that the Local Link 5 \"in\" channel is idle" }, { .pme_name = "PM_PBUS_LL5_IN_CMDRSP", .pme_code = TORRENT_PBUS_LL | COUNTER_LL5 | 0x2, .pme_desc = "Number of commands, partial responses, and combined responses received on the Local Link 5 \"in\" channel (Note: multiple events can occur in one cycle)" }, { .pme_name = "PM_PBUS_LL5_IN_DATA", .pme_code = TORRENT_PBUS_LL | COUNTER_LL5 | 0x3, .pme_desc = "Bus cycles that the Local Link 5 \"in\" channel is receiving data or a data header" }, { .pme_name = "PM_PBUS_LL5_OUT_IDLE", .pme_code = TORRENT_PBUS_LL | COUNTER_LL5 | 0x5, .pme_desc = "Bus cycles that the Local Link 5 \"out\" channel is idle" }, { .pme_name = "PM_PBUS_LL5_OUT_CMDRSP", .pme_code = TORRENT_PBUS_LL | COUNTER_LL5 | 0x6, .pme_desc = "Number of commands, partial responses, and combined responses sent on the Local Link 5 \"out\" channel (Note: multiple events can occur in one cycle)" }, { .pme_name = "PM_PBUS_LL5_OUT_DATA", .pme_code = TORRENT_PBUS_LL | COUNTER_LL5 | 0x7, .pme_desc = "Bus cycles that the Local Link 5 \"out\" channel is sending data or a data header" }, { .pme_name = "PM_PBUS_LL5_IN_ISR", .pme_code = TORRENT_PBUS_LL | COUNTER_LL5 | 0x9, .pme_desc = "Bus cycles that the Local Link 5 \"in\" channel is receiving ISR data or an ISR data header" }, { .pme_name = "PM_PBUS_LL5_OUT_ISR", .pme_code = TORRENT_PBUS_LL | COUNTER_LL5 | 0xd, .pme_desc = "Bus cycles that the Local Link 5 \"out\" channel is sending ISR data or an ISR data header" }, { .pme_name = "PM_PBUS_LL6_DISABLED", .pme_code = TORRENT_PBUS_LL | COUNTER_LL6 | 0x0, .pme_desc = "The Local Link 6 event counter is disabled" }, { .pme_name = "PM_PBUS_LL6_IN_IDLE", .pme_code = TORRENT_PBUS_LL | COUNTER_LL6 | 0x1, .pme_desc = "Bus cycles that the Local Link 6 \"in\" channel is idle" }, { .pme_name = "PM_PBUS_LL6_IN_CMDRSP", .pme_code = TORRENT_PBUS_LL | COUNTER_LL6 | 0x2, .pme_desc = "Number of commands, partial responses, and combined responses received on the Local Link 6 \"in\" channel (Note: multiple events can occur in one cycle)" }, { .pme_name = "PM_PBUS_LL6_IN_DATA", .pme_code = TORRENT_PBUS_LL | COUNTER_LL6 | 0x3, .pme_desc = "Bus cycles that the Local Link 6 \"in\" channel is receiving data or a data header" }, { .pme_name = "PM_PBUS_LL6_OUT_IDLE", .pme_code = TORRENT_PBUS_LL | COUNTER_LL6 | 0x5, .pme_desc = "Bus cycles that the Local Link 6 \"out\" channel is idle" }, { .pme_name = "PM_PBUS_LL6_OUT_CMDRSP", .pme_code = TORRENT_PBUS_LL | COUNTER_LL6 | 0x6, .pme_desc = "Number of commands, partial responses, and combined responses sent on the Local Link 6 \"out\" channel (Note: multiple events can occur in one cycle)" }, { .pme_name = "PM_PBUS_LL6_OUT_DATA", .pme_code = TORRENT_PBUS_LL | COUNTER_LL6 | 0x7, .pme_desc = "Bus cycles that the Local Link 6 \"out\" channel is sending data or a data header" }, { .pme_name = "PM_PBUS_LL6_IN_ISR", .pme_code = TORRENT_PBUS_LL | COUNTER_LL6 | 0x9, .pme_desc = "Bus cycles that the Local Link 6 \"in\" channel is receiving ISR data or an ISR data header" }, { .pme_name = "PM_PBUS_LL6_OUT_ISR", .pme_code = TORRENT_PBUS_LL | COUNTER_LL6 | 0xd, .pme_desc = "Bus cycles that the Local Link 6 \"out\" channel is sending ISR data or an ISR data header" }, { .pme_name = "PM_PBUS_MCD0_PROBE_ISSUED", .pme_code = TORRENT_PBUS_MCD | 0 << TORRENT_UNIT_SHIFT | 0x00, .pme_desc = "cl_probe command issued", .pme_modmsk = _TORRENT_ATTR_MCD }, { .pme_name = "PM_PBUS_MCD0_PROBE_CRESP_GOOD", .pme_code = TORRENT_PBUS_MCD | 0 << TORRENT_UNIT_SHIFT | 0x01, .pme_desc = "cResp for a cl_probe was addr_ack_done", .pme_modmsk = _TORRENT_ATTR_MCD }, { .pme_name = "PM_PBUS_MCD0_PROBE_CRESP_RETRY", .pme_code = TORRENT_PBUS_MCD | 0 << TORRENT_UNIT_SHIFT | 0x02, .pme_desc = "cResp for a cl_probe was rty_sp or addr_error or unexpected cResp", .pme_modmsk = _TORRENT_ATTR_MCD }, { .pme_name = "PM_PBUS_MCD0_FLUSH1_ISSUED", .pme_code = TORRENT_PBUS_MCD | 0 << TORRENT_UNIT_SHIFT | 0x03, .pme_desc = "dcbfk command issued", .pme_modmsk = _TORRENT_ATTR_MCD }, { .pme_name = "PM_PBUS_MCD0_FLUSH0_ISSUED", .pme_code = TORRENT_PBUS_MCD | 0 << TORRENT_UNIT_SHIFT | 0x04, .pme_desc = "dcbf command issued", .pme_modmsk = _TORRENT_ATTR_MCD }, { .pme_name = "PM_PBUS_MCD0_BKILL_ISSUED", .pme_code = TORRENT_PBUS_MCD | 0 << TORRENT_UNIT_SHIFT | 0x05, .pme_desc = "bkill command issued", .pme_modmsk = _TORRENT_ATTR_MCD }, { .pme_name = "PM_PBUS_MCD0_FLUSH1_GOOD_COMP", .pme_code = TORRENT_PBUS_MCD | 0 << TORRENT_UNIT_SHIFT | 0x06, .pme_desc = "cResp for a dcbfk was addr_ack_done and no collision", .pme_modmsk = _TORRENT_ATTR_MCD }, { .pme_name = "PM_PBUS_MCD0_FLUSH1_COLLISION", .pme_code = TORRENT_PBUS_MCD | 0 << TORRENT_UNIT_SHIFT | 0x07, .pme_desc = "dcbfk had a collision", .pme_modmsk = _TORRENT_ATTR_MCD }, { .pme_name = "PM_PBUS_MCD0_FLUSH1_BAD_CRESP", .pme_code = TORRENT_PBUS_MCD | 0 << TORRENT_UNIT_SHIFT | 0x08, .pme_desc = "cResp for a dcbfk was rty_sp or fl_addr_ack_bk_sp", .pme_modmsk = _TORRENT_ATTR_MCD }, { .pme_name = "PM_PBUS_MCD0_FLUSH0_CRESP_RETRY", .pme_code = TORRENT_PBUS_MCD | 0 << TORRENT_UNIT_SHIFT | 0x09, .pme_desc = "cResp for a dcbf was rty_sp", .pme_modmsk = _TORRENT_ATTR_MCD }, { .pme_name = "PM_PBUS_MCD0_BKILL_CRESP_RETRY", .pme_code = TORRENT_PBUS_MCD | 0 << TORRENT_UNIT_SHIFT | 0x0A, .pme_desc = "cResp for a bkill was rty_sp or fl_addr_ack_bk_sp", .pme_modmsk = _TORRENT_ATTR_MCD }, { .pme_name = "PM_PBUS_MCD0_RCMD_HIT", .pme_code = TORRENT_PBUS_MCD | 0 << TORRENT_UNIT_SHIFT | 0x0B, .pme_desc = "a reflected command got a hit", .pme_modmsk = _TORRENT_ATTR_MCD }, { .pme_name = "PM_PBUS_MCD0_RCMD_MISS", .pme_code = TORRENT_PBUS_MCD | 0 << TORRENT_UNIT_SHIFT | 0x0C, .pme_desc = "a reflected command got a miss", .pme_modmsk = _TORRENT_ATTR_MCD }, { .pme_name = "PM_PBUS_MCD0_RCMD_HIT_MD", .pme_code = TORRENT_PBUS_MCD | 0 << TORRENT_UNIT_SHIFT | 0x0D, .pme_desc = "a reflected command got a hit in the main directory", .pme_modmsk = _TORRENT_ATTR_MCD }, { .pme_name = "PM_PBUS_MCD0_RCMD_HIT_NE", .pme_code = TORRENT_PBUS_MCD | 0 << TORRENT_UNIT_SHIFT | 0x0E, .pme_desc = "a reflected command got a hit in the new entry buffer", .pme_modmsk = _TORRENT_ATTR_MCD }, { .pme_name = "PM_PBUS_MCD0_RCMD_HIT_CO", .pme_code = TORRENT_PBUS_MCD | 0 << TORRENT_UNIT_SHIFT | 0x0F, .pme_desc = "a reflected command got a hit in the castout buffer", .pme_modmsk = _TORRENT_ATTR_MCD }, { .pme_name = "PM_PBUS_MCD0_RCMD_MISS_CREATE", .pme_code = TORRENT_PBUS_MCD | 0 << TORRENT_UNIT_SHIFT | 0x10, .pme_desc = "a reflected command with a miss should create an entry", .pme_modmsk = _TORRENT_ATTR_MCD }, { .pme_name = "PM_PBUS_MCD0_RCMD_MISS_CREATED", .pme_code = TORRENT_PBUS_MCD | 0 << TORRENT_UNIT_SHIFT | 0x11, .pme_desc = "a new entry was created", .pme_modmsk = _TORRENT_ATTR_MCD }, { .pme_name = "PM_PBUS_MCD0_RTY_DINC", .pme_code = TORRENT_PBUS_MCD | 0 << TORRENT_UNIT_SHIFT | 0x12, .pme_desc = "MCD responded rty_dinc", .pme_modmsk = _TORRENT_ATTR_MCD }, { .pme_name = "PM_PBUS_MCD0_RTY_FULL", .pme_code = TORRENT_PBUS_MCD | 0 << TORRENT_UNIT_SHIFT | 0x13, .pme_desc = "MCD responded rty_lpc", .pme_modmsk = _TORRENT_ATTR_MCD }, { .pme_name = "PM_PBUS_MCD0_BK_RTY", .pme_code = TORRENT_PBUS_MCD | 0 << TORRENT_UNIT_SHIFT | 0x14, .pme_desc = "MCD responded with a master retry (rty_other or rty_lost_claim)", .pme_modmsk = _TORRENT_ATTR_MCD }, { .pme_name = "PM_PBUS_MCD0_NE_FULL", .pme_code = TORRENT_PBUS_MCD | 0 << TORRENT_UNIT_SHIFT | 0x15, .pme_desc = "The new entry buffer is full", .pme_modmsk = _TORRENT_ATTR_MCD }, { .pme_name = "PM_PBUS_MCD0_DEMAND_CASTOUT", .pme_code = TORRENT_PBUS_MCD | 0 << TORRENT_UNIT_SHIFT | 0x16, .pme_desc = "A demand castout was done", .pme_modmsk = _TORRENT_ATTR_MCD }, { .pme_name = "PM_PBUS_MCD0_OTHER_CASTOUT", .pme_code = TORRENT_PBUS_MCD | 0 << TORRENT_UNIT_SHIFT | 0x17, .pme_desc = "A non-demand castout was done", .pme_modmsk = _TORRENT_ATTR_MCD }, { .pme_name = "PM_PBUS_MCD0_CASTOUT", .pme_code = TORRENT_PBUS_MCD | 0 << TORRENT_UNIT_SHIFT | 0x18, .pme_desc = "A castout was done", .pme_modmsk = _TORRENT_ATTR_MCD }, { .pme_name = "PM_PBUS_MCD0_CO_MOVE", .pme_code = TORRENT_PBUS_MCD | 0 << TORRENT_UNIT_SHIFT | 0x19, .pme_desc = "A castout entry was moved to the main directory", .pme_modmsk = _TORRENT_ATTR_MCD }, { .pme_name = "PM_PBUS_MCD0_NE_MOVE", .pme_code = TORRENT_PBUS_MCD | 0 << TORRENT_UNIT_SHIFT | 0x1A, .pme_desc = "A new entry movement was processed", .pme_modmsk = _TORRENT_ATTR_MCD }, { .pme_name = "PM_PBUS_MCD0_PAGE_CREATE", .pme_code = TORRENT_PBUS_MCD | 0 << TORRENT_UNIT_SHIFT | 0x1B, .pme_desc = "A new entry movement created a page (got a miss)", .pme_modmsk = _TORRENT_ATTR_MCD }, { .pme_name = "PM_PBUS_MCD0_NE_MOVE_MERGE", .pme_code = TORRENT_PBUS_MCD | 0 << TORRENT_UNIT_SHIFT | 0x1C, .pme_desc = "A new entry movement merged with an existing page (got a hit)", .pme_modmsk = _TORRENT_ATTR_MCD }, { .pme_name = "PM_PBUS_MCD0_NE_MOVE_ABORT_FLUSH", .pme_code = TORRENT_PBUS_MCD | 0 << TORRENT_UNIT_SHIFT | 0x1D, .pme_desc = "A new entry movement was aborted due to flush in progress", .pme_modmsk = _TORRENT_ATTR_MCD }, { .pme_name = "PM_PBUS_MCD0_NE_MOVE_ABORT_COQ", .pme_code = TORRENT_PBUS_MCD | 0 << TORRENT_UNIT_SHIFT | 0x1E, .pme_desc = "A new entry movement was aborted due to castout buffer full", .pme_modmsk = _TORRENT_ATTR_MCD }, { .pme_name = "PM_PBUS_MCD0_EM_HOLDOFF", .pme_code = TORRENT_PBUS_MCD | 0 << TORRENT_UNIT_SHIFT | 0x1F, .pme_desc = "An entry movement was held off", .pme_modmsk = _TORRENT_ATTR_MCD }, { .pme_name = "PM_PBUS_MCD0_EMQ_NOT_MT", .pme_code = TORRENT_PBUS_MCD | 0 << TORRENT_UNIT_SHIFT | 0x21, .pme_desc = "The entry movement queue is not empty", .pme_modmsk = _TORRENT_ATTR_MCD }, { .pme_name = "PM_PBUS_MCD1_PROBE_ISSUED", .pme_code = TORRENT_PBUS_MCD | 1 << TORRENT_UNIT_SHIFT | 0x00, .pme_desc = "cl_probe command issued", .pme_modmsk = _TORRENT_ATTR_MCD }, { .pme_name = "PM_PBUS_MCD1_PROBE_CRESP_GOOD", .pme_code = TORRENT_PBUS_MCD | 1 << TORRENT_UNIT_SHIFT | 0x01, .pme_desc = "cResp for a cl_probe was addr_ack_done", .pme_modmsk = _TORRENT_ATTR_MCD }, { .pme_name = "PM_PBUS_MCD1_PROBE_CRESP_RETRY", .pme_code = TORRENT_PBUS_MCD | 1 << TORRENT_UNIT_SHIFT | 0x02, .pme_desc = "cResp for a cl_probe was rty_sp or addr_error or unexpected cResp", .pme_modmsk = _TORRENT_ATTR_MCD }, { .pme_name = "PM_PBUS_MCD1_FLUSH1_ISSUED", .pme_code = TORRENT_PBUS_MCD | 1 << TORRENT_UNIT_SHIFT | 0x03, .pme_desc = "dcbfk command issued", .pme_modmsk = _TORRENT_ATTR_MCD }, { .pme_name = "PM_PBUS_MCD1_FLUSH0_ISSUED", .pme_code = TORRENT_PBUS_MCD | 1 << TORRENT_UNIT_SHIFT | 0x04, .pme_desc = "dcbf command issued", .pme_modmsk = _TORRENT_ATTR_MCD }, { .pme_name = "PM_PBUS_MCD1_BKILL_ISSUED", .pme_code = TORRENT_PBUS_MCD | 1 << TORRENT_UNIT_SHIFT | 0x05, .pme_desc = "bkill command issued", .pme_modmsk = _TORRENT_ATTR_MCD }, { .pme_name = "PM_PBUS_MCD1_FLUSH1_GOOD_COMP", .pme_code = TORRENT_PBUS_MCD | 1 << TORRENT_UNIT_SHIFT | 0x06, .pme_desc = "cResp for a dcbfk was addr_ack_done and no collision", .pme_modmsk = _TORRENT_ATTR_MCD }, { .pme_name = "PM_PBUS_MCD1_FLUSH1_COLLISION", .pme_code = TORRENT_PBUS_MCD | 1 << TORRENT_UNIT_SHIFT | 0x07, .pme_desc = "dcbfk had a collision", .pme_modmsk = _TORRENT_ATTR_MCD }, { .pme_name = "PM_PBUS_MCD1_FLUSH1_BAD_CRESP", .pme_code = TORRENT_PBUS_MCD | 1 << TORRENT_UNIT_SHIFT | 0x08, .pme_desc = "cResp for a dcbfk was rty_sp or fl_addr_ack_bk_sp", .pme_modmsk = _TORRENT_ATTR_MCD }, { .pme_name = "PM_PBUS_MCD1_FLUSH0_CRESP_RETRY", .pme_code = TORRENT_PBUS_MCD | 1 << TORRENT_UNIT_SHIFT | 0x09, .pme_desc = "cResp for a dcbf was rty_sp", .pme_modmsk = _TORRENT_ATTR_MCD }, { .pme_name = "PM_PBUS_MCD1_BKILL_CRESP_RETRY", .pme_code = TORRENT_PBUS_MCD | 1 << TORRENT_UNIT_SHIFT | 0x0A, .pme_desc = "cResp for a bkill was rty_sp or fl_addr_ack_bk_sp", .pme_modmsk = _TORRENT_ATTR_MCD }, { .pme_name = "PM_PBUS_MCD1_RCMD_HIT", .pme_code = TORRENT_PBUS_MCD | 1 << TORRENT_UNIT_SHIFT | 0x0B, .pme_desc = "a reflected command got a hit", .pme_modmsk = _TORRENT_ATTR_MCD }, { .pme_name = "PM_PBUS_MCD1_RCMD_MISS", .pme_code = TORRENT_PBUS_MCD | 1 << TORRENT_UNIT_SHIFT | 0x0C, .pme_desc = "a reflected command got a miss", .pme_modmsk = _TORRENT_ATTR_MCD }, { .pme_name = "PM_PBUS_MCD1_RCMD_HIT_MD", .pme_code = TORRENT_PBUS_MCD | 1 << TORRENT_UNIT_SHIFT | 0x0D, .pme_desc = "a reflected command got a hit in the main directory", .pme_modmsk = _TORRENT_ATTR_MCD }, { .pme_name = "PM_PBUS_MCD1_RCMD_HIT_NE", .pme_code = TORRENT_PBUS_MCD | 1 << TORRENT_UNIT_SHIFT | 0x0E, .pme_desc = "a reflected command got a hit in the new entry buffer", .pme_modmsk = _TORRENT_ATTR_MCD }, { .pme_name = "PM_PBUS_MCD1_RCMD_HIT_CO", .pme_code = TORRENT_PBUS_MCD | 1 << TORRENT_UNIT_SHIFT | 0x0F, .pme_desc = "a reflected command got a hit in the castout buffer", .pme_modmsk = _TORRENT_ATTR_MCD }, { .pme_name = "PM_PBUS_MCD1_RCMD_MISS_CREATE", .pme_code = TORRENT_PBUS_MCD | 1 << TORRENT_UNIT_SHIFT | 0x10, .pme_desc = "a reflected command with a miss should create an entry", .pme_modmsk = _TORRENT_ATTR_MCD }, { .pme_name = "PM_PBUS_MCD1_RCMD_MISS_CREATED", .pme_code = TORRENT_PBUS_MCD | 1 << TORRENT_UNIT_SHIFT | 0x11, .pme_desc = "a new entry was created", .pme_modmsk = _TORRENT_ATTR_MCD }, { .pme_name = "PM_PBUS_MCD1_RTY_DINC", .pme_code = TORRENT_PBUS_MCD | 1 << TORRENT_UNIT_SHIFT | 0x12, .pme_desc = "MCD responded rty_dinc", .pme_modmsk = _TORRENT_ATTR_MCD }, { .pme_name = "PM_PBUS_MCD1_RTY_FULL", .pme_code = TORRENT_PBUS_MCD | 1 << TORRENT_UNIT_SHIFT | 0x13, .pme_desc = "MCD responded rty_lpc", .pme_modmsk = _TORRENT_ATTR_MCD }, { .pme_name = "PM_PBUS_MCD1_BK_RTY", .pme_code = TORRENT_PBUS_MCD | 1 << TORRENT_UNIT_SHIFT | 0x14, .pme_desc = "MCD responded with a master retry (rty_other or rty_lost_claim)", .pme_modmsk = _TORRENT_ATTR_MCD }, { .pme_name = "PM_PBUS_MCD1_NE_FULL", .pme_code = TORRENT_PBUS_MCD | 1 << TORRENT_UNIT_SHIFT | 0x15, .pme_desc = "The new entry buffer is full", .pme_modmsk = _TORRENT_ATTR_MCD }, { .pme_name = "PM_PBUS_MCD1_DEMAND_CASTOUT", .pme_code = TORRENT_PBUS_MCD | 1 << TORRENT_UNIT_SHIFT | 0x16, .pme_desc = "A demand castout was done", .pme_modmsk = _TORRENT_ATTR_MCD }, { .pme_name = "PM_PBUS_MCD1_OTHER_CASTOUT", .pme_code = TORRENT_PBUS_MCD | 1 << TORRENT_UNIT_SHIFT | 0x17, .pme_desc = "A non-demand castout was done", .pme_modmsk = _TORRENT_ATTR_MCD }, { .pme_name = "PM_PBUS_MCD1_CASTOUT", .pme_code = TORRENT_PBUS_MCD | 1 << TORRENT_UNIT_SHIFT | 0x18, .pme_desc = "A castout was done", .pme_modmsk = _TORRENT_ATTR_MCD }, { .pme_name = "PM_PBUS_MCD1_CO_MOVE", .pme_code = TORRENT_PBUS_MCD | 1 << TORRENT_UNIT_SHIFT | 0x19, .pme_desc = "A castout entry was moved to the main directory", .pme_modmsk = _TORRENT_ATTR_MCD }, { .pme_name = "PM_PBUS_MCD1_NE_MOVE", .pme_code = TORRENT_PBUS_MCD | 1 << TORRENT_UNIT_SHIFT | 0x1A, .pme_desc = "A new entry movement was processed", .pme_modmsk = _TORRENT_ATTR_MCD }, { .pme_name = "PM_PBUS_MCD1_PAGE_CREATE", .pme_code = TORRENT_PBUS_MCD | 1 << TORRENT_UNIT_SHIFT | 0x1B, .pme_desc = "A new entry movement created a page (got a miss)", .pme_modmsk = _TORRENT_ATTR_MCD }, { .pme_name = "PM_PBUS_MCD1_NE_MOVE_MERGE", .pme_code = TORRENT_PBUS_MCD | 1 << TORRENT_UNIT_SHIFT | 0x1C, .pme_desc = "A new entry movement merged with an existing page (got a hit)", .pme_modmsk = _TORRENT_ATTR_MCD }, { .pme_name = "PM_PBUS_MCD1_NE_MOVE_ABORT_FLUSH", .pme_code = TORRENT_PBUS_MCD | 1 << TORRENT_UNIT_SHIFT | 0x1D, .pme_desc = "A new entry movement was aborted due to flush in progress", .pme_modmsk = _TORRENT_ATTR_MCD }, { .pme_name = "PM_PBUS_MCD1_NE_MOVE_ABORT_COQ", .pme_code = TORRENT_PBUS_MCD | 1 << TORRENT_UNIT_SHIFT | 0x1E, .pme_desc = "A new entry movement was aborted due to castout buffer full", .pme_modmsk = _TORRENT_ATTR_MCD }, { .pme_name = "PM_PBUS_MCD1_EM_HOLDOFF", .pme_code = TORRENT_PBUS_MCD | 1 << TORRENT_UNIT_SHIFT | 0x1F, .pme_desc = "An entry movement was held off", .pme_modmsk = _TORRENT_ATTR_MCD }, { .pme_name = "PM_PBUS_MCD1_EMQ_NOT_MT", .pme_code = TORRENT_PBUS_MCD | 1 << TORRENT_UNIT_SHIFT | 0x21, .pme_desc = "The entry movement queue is not empty", .pme_modmsk = _TORRENT_ATTR_MCD }, { .pme_name = "PM_PBUS_UTIL_PB_APM_NM_HI_CNT", .pme_code = TORRENT_PBUS_UTIL | 0x0 << TORRENT_VIRT_CTR_SHIFT | 0x0, .pme_desc = "Node Master High Threshold Counter", .pme_modmsk = _TORRENT_ATTR_UTIL_HI }, { .pme_name = "PM_PBUS_UTIL_PB_APM_NM_LO_CNT", .pme_code = TORRENT_PBUS_UTIL | 0x1 << TORRENT_VIRT_CTR_SHIFT | 0x0, .pme_desc = "Node Master Low Threshold Counter", .pme_modmsk = _TORRENT_ATTR_UTIL_LO }, { .pme_name = "PM_PBUS_UTIL_PB_APM_LM_HI_CNT", .pme_code = TORRENT_PBUS_UTIL | 0x2 << TORRENT_VIRT_CTR_SHIFT | 0x0, .pme_desc = "Local Master High Threshold Counter", .pme_modmsk = _TORRENT_ATTR_UTIL_HI }, { .pme_name = "PM_PBUS_UTIL_PB_APM_LM_LO_CNT", .pme_code = TORRENT_PBUS_UTIL | 0x3 << TORRENT_VIRT_CTR_SHIFT | 0x0, .pme_desc = "Local Master Low Threshold Counter", .pme_modmsk = _TORRENT_ATTR_UTIL_LO }, { .pme_name = "PM_PBUS_UTIL_NODE_MASTER_PUMPS", .pme_code = TORRENT_PBUS_UTIL | 0x0 << TORRENT_VIRT_CTR_SHIFT | 0x1, .pme_desc = "Node Master Pumps" }, { .pme_name = "PM_PBUS_UTIL_LOCAL_MASTER_PUMPS", .pme_code = TORRENT_PBUS_UTIL | 0x1 << TORRENT_VIRT_CTR_SHIFT | 0x1, .pme_desc = "Local Master Pumps" }, { .pme_name = "PM_PBUS_UTIL_RETRY_NODE_MASTER_PUMPS", .pme_code = TORRENT_PBUS_UTIL | 0x2 << TORRENT_VIRT_CTR_SHIFT | 0x1, .pme_desc = "Retry Node Master Pumps" }, { .pme_name = "PM_PBUS_UTIL_RETRY_LOCAL_MASTER_PUMPS", .pme_code = TORRENT_PBUS_UTIL | 0x3 << TORRENT_VIRT_CTR_SHIFT | 0x1, .pme_desc = "Retry Local Master Pumps" }, { .pme_name = "PM_PBUS_UTIL_PB_APM_RCMD_CNT", .pme_code = TORRENT_PBUS_UTIL | 0x4 << TORRENT_VIRT_CTR_SHIFT, .pme_desc = "rCmd Activity Counter" }, { .pme_name = "PM_PBUS_UTIL_PB_APM_INTDATA_CNT", .pme_code = TORRENT_PBUS_UTIL | 0x5 << TORRENT_VIRT_CTR_SHIFT, .pme_desc = "Internal Data Counter" }, { .pme_name = "PM_PBUS_UTIL_PB_APM_EXTDATSND_W_CNT", .pme_code = TORRENT_PBUS_UTIL | 0x6 << TORRENT_VIRT_CTR_SHIFT, .pme_desc = "External Data Send Activity Counter for WXYZ links" }, { .pme_name = "PM_PBUS_UTIL_PB_APM_EXTDATRCV_W_CNT", .pme_code = TORRENT_PBUS_UTIL | 0x7 << TORRENT_VIRT_CTR_SHIFT, .pme_desc = "External Data Receive Activity Counter for WXYZ links" }, { .pme_name = "PM_PBUS_UTIL_PB_APM_EXTDATSND_LL_CNT", .pme_code = TORRENT_PBUS_UTIL | 0x8 << TORRENT_VIRT_CTR_SHIFT, .pme_desc = "External Data Send Activity Counter for LL links" }, { .pme_name = "PM_PBUS_UTIL_PB_APM_EXTDATRCV_LL_CNT", .pme_code = TORRENT_PBUS_UTIL | 0x9 << TORRENT_VIRT_CTR_SHIFT, .pme_desc = "External Data Receive Activity Counter for LL links" }, { .pme_name = "PM_PBUS_UTIL_PB_APM_EXTDAT_W_LL_CNT", .pme_code = TORRENT_PBUS_UTIL | 0xA << TORRENT_VIRT_CTR_SHIFT, .pme_desc = "External Data Activity Counter from WXYZ to LL links" }, { .pme_name = "PM_PBUS_UTIL_PB_APM_EXTDAT_LL_W_CNT", .pme_code = TORRENT_PBUS_UTIL | 0xB << TORRENT_VIRT_CTR_SHIFT, .pme_desc = "External Data Activity Counter from LL to WXYZ links" }, { .pme_name = "PM_MMU_G_MMCHIT", .pme_code = TORRENT_MMU | (0 << TORRENT_VIRT_CTR_SHIFT), .pme_desc = "Memory Management Cache Hit Counter Register" }, { .pme_name = "PM_MMU_G_MMCMIS", .pme_code = TORRENT_MMU | (1 << TORRENT_VIRT_CTR_SHIFT), .pme_desc = "Memory Management Cache Miss Counter Register" }, { .pme_name = "PM_MMU_G_MMATHIT", .pme_code = TORRENT_MMU | (2 << TORRENT_VIRT_CTR_SHIFT), .pme_desc = "Memory Management AT Cache Hit Counter Register" }, { .pme_name = "PM_MMU_G_MMATMIS", .pme_code = TORRENT_MMU | (3 << TORRENT_VIRT_CTR_SHIFT), .pme_desc = "Memory Management AT Cache Miss Counter Register" }, { .pme_name = "PM_CAU_CYCLES_WAITING_ON_A_CREDIT", .pme_code = TORRENT_CAU | 0, .pme_desc = "Count of cycles spent waiting on a credit. Increments whenever any index has a packet to send, but nothing (from any index) can be sent." }, }; #define PME_TORRENT_EVENT_COUNT (sizeof(torrent_pe) / sizeof(pme_torrent_entry_t)) #endif libpfm-4.9.0/lib/events/intel_hswep_unc_cbo_events.h0000664000175000017500000010556413223402656022451 0ustar eranianeranian/* * Copyright (c) 2014 Google Inc. All rights reserved * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * PMU: hswep_unc_cbo (Intel Haswell-EP C-Box uncore PMU) */ #define CBO_FILT_MESIF(a, b, c, d) \ { .uname = "STATE_"#a,\ .udesc = #b" cacheline state",\ .ufilters[0] = 1ULL << (17 + (c)),\ .grpid = d, \ } #define CBO_FILT_MESIFS(d) \ CBO_FILT_MESIF(I, Invalid, 0, d), \ CBO_FILT_MESIF(S, Shared, 1, d), \ CBO_FILT_MESIF(E, Exclusive, 2, d), \ CBO_FILT_MESIF(M, Modified, 3, d), \ CBO_FILT_MESIF(F, Forward, 4, d), \ CBO_FILT_MESIF(D, Debug, 5, d), \ { .uname = "STATE_MP",\ .udesc = "Cacheline is modified but never written, was forwarded in modified state",\ .ufilters[0] = 0x1ULL << (17+6),\ .grpid = d, \ .uflags = INTEL_X86_NCOMBO, \ }, \ { .uname = "STATE_MESIFD",\ .udesc = "Any cache line state",\ .ufilters[0] = 0x7fULL << 17,\ .grpid = d, \ .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, \ } #define CBO_FILT_OPC(d) \ { .uname = "OPC_RFO",\ .udesc = "Demand data RFO (combine with any OPCODE umask)",\ .ufilters[1] = 0x180ULL << 20, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_CRD",\ .udesc = "Demand code read (combine with any OPCODE umask)",\ .ufilters[1] = 0x181ULL << 20, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_DRD",\ .udesc = "Demand data read (combine with any OPCODE umask)",\ .ufilters[1] = 0x182ULL << 20, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_PRD",\ .udesc = "Partial reads (UC) (combine with any OPCODE umask)",\ .ufilters[1] = 0x187ULL << 20, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_WCILF",\ .udesc = "Full Stream store (combine with any OPCODE umask)", \ .ufilters[1] = 0x18cULL << 20, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_WCIL",\ .udesc = "Partial Stream store (combine with any OPCODE umask)", \ .ufilters[1] = 0x18dULL << 20, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_WIL",\ .udesc = "Write Invalidate Line (Partial) (combine with any OPCODE umask)", \ .ufilters[1] = 0x18fULL << 20, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_PF_RFO",\ .udesc = "Prefetch RFO into LLC but do not pass to L2 (includes hints) (combine with any OPCODE umask)", \ .ufilters[1] = 0x190ULL << 20, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_PF_CODE",\ .udesc = "Prefetch code into LLC but do not pass to L2 (includes hints) (combine with any OPCODE umask)", \ .ufilters[1] = 0x191ULL << 20, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_PF_DATA",\ .udesc = "Prefetch data into LLC but do not pass to L2 (includes hints) (combine with any OPCODE umask)", \ .ufilters[1] = 0x192ULL << 20, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_PCIWIL",\ .udesc = "PCIe write (partial, non-allocating) - partial line MMIO write transactions from IIO (P2P). Not used for coherent transacions. Uncacheable. (combine with any OPCODE umask)", \ .ufilters[1] = 0x193ULL << 20, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_PCIWIF",\ .udesc = "PCIe write (full, non-allocating) - full line MMIO write transactions from IIO (P2P). Not used for coherent transacions. Uncacheable. (combine with any OPCODE umask)", \ .ufilters[1] = 0x194ULL << 20, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_PCIITOM",\ .udesc = "PCIe write (allocating) (combine with any OPCODE umask)", \ .ufilters[1] = 0x19cULL << 20, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_PCIRDCUR",\ .udesc = "PCIe read current (combine with any OPCODE umask)", \ .ufilters[1] = 0x19eULL << 20, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_WBMTOI",\ .udesc = "Request writeback modified invalidate line (combine with any OPCODE umask)", \ .ufilters[1] = 0x1c4ULL << 20, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_WBMTOE",\ .udesc = "Request writeback modified set to exclusive (combine with any OPCODE umask)", \ .ufilters[1] = 0x1c5ULL << 20, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_ITOM",\ .udesc = "Request invalidate line. Request exclusive ownership of the line (combine with any OPCODE umask)", \ .ufilters[1] = 0x1c8ULL << 20, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_PCINSRD",\ .udesc = "PCIe non-snoop read (combine with any OPCODE umask)", \ .ufilters[1] = 0x1e4ULL << 20, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_PCINSWR",\ .udesc = "PCIe non-snoop write (partial) (combine with any OPCODE umask)", \ .ufilters[1] = 0x1e5ULL << 20, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_PCINSWRF",\ .udesc = "PCIe non-snoop write (full) (combine with any OPCODE umask)", \ .ufilters[1] = 0x1e6ULL << 20, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ } static const intel_x86_umask_t hswep_unc_c_llc_lookup[]={ { .uname = "DATA_READ", .udesc = "Data read requests", .grpid = 0, .ucode = 0x300, .uflags = INTEL_X86_NCOMBO, }, { .uname = "WRITE", .udesc = "Write requests. Includes all write transactions (cached, uncached)", .grpid = 0, .ucode = 0x500, .uflags = INTEL_X86_NCOMBO, }, { .uname = "REMOTE_SNOOP", .udesc = "External snoop request", .grpid = 0, .ucode = 0x900, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ANY", .udesc = "Any request", .grpid = 0, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, .ucode = 0x1100, }, { .uname = "NID", .udesc = "Match a given RTID destination NID (must provide nf=X modifier)", .umodmsk_req = _SNBEP_UNC_ATTR_NF1, .grpid = 1, .ucode = 0x4100, .uflags = INTEL_X86_GRP_DFL_NONE }, CBO_FILT_MESIFS(2), }; static const intel_x86_umask_t hswep_unc_c_llc_victims[]={ { .uname = "STATE_M", .udesc = "Lines in M state", .ucode = 0x100, .grpid = 0, }, { .uname = "STATE_E", .udesc = "Lines in E state", .ucode = 0x200, .grpid = 0, }, { .uname = "STATE_S", .udesc = "Lines in S state", .ucode = 0x400, .grpid = 0, }, { .uname = "STATE_F", .udesc = "Lines in F state", .ucode = 0x800, .grpid = 0, }, { .uname = "MISS", .udesc = "TBD", .ucode = 0x1000, .grpid = 0, }, { .uname = "NID", .udesc = "Victimized Lines matching the NID filter (must provide nf=X modifier)", .ucode = 0x4000, .uflags = INTEL_X86_GRP_DFL_NONE, .umodmsk_req = _SNBEP_UNC_ATTR_NF1, .grpid = 1, }, }; static const intel_x86_umask_t hswep_unc_c_ring_ad_used[]={ { .uname = "UP_EVEN", .udesc = "Up and Even ring polarity filter", .ucode = 0x100, }, { .uname = "UP_ODD", .udesc = "Up and odd ring polarity filter", .ucode = 0x200, }, { .uname = "DOWN_EVEN", .udesc = "Down and even ring polarity filter", .ucode = 0x400, }, { .uname = "DOWN_ODD", .udesc = "Down and odd ring polarity filter", .ucode = 0x800, }, { .uname = "UP", .udesc = "Up ring polarity filter", .ucode = 0x3300, }, { .uname = "DOWN", .udesc = "Down ring polarity filter", .ucode = 0xcc00, }, { .uname = "ALL", .udesc = "up or down ring polarity filter", .ucode = 0xcc00, }, }; static const intel_x86_umask_t hswep_unc_c_ring_bounces[]={ { .uname = "AD_IRQ", .udesc = "TBD", .ucode = 0x200, }, { .uname = "AK", .udesc = "Acknowledgments to core", .ucode = 0x400, }, { .uname = "BL", .udesc = "Data responses to core", .ucode = 0x800, }, { .uname = "IV", .udesc = "Snoops of processor cache", .ucode = 0x1000, }, }; static const intel_x86_umask_t hswep_unc_c_ring_iv_used[]={ { .uname = "ANY", .udesc = "Any filter", .ucode = 0x0f00, .uflags = INTEL_X86_DFL, }, { .uname = "UP", .udesc = "Filter on any up polarity", .ucode = 0x0300, }, { .uname = "DN", .udesc = "Filter on any up polarity", .ucode = 0x0c00, }, { .uname = "DOWN", .udesc = "Filter on any down polarity", .ucode = 0xcc00, }, }; static const intel_x86_umask_t hswep_unc_c_rxr_ext_starved[]={ { .uname = "IRQ", .udesc = "Irq externally starved, therefore blocking the IPQ", .ucode = 0x100, }, { .uname = "IPQ", .udesc = "IPQ externally starved, therefore blocking the IRQ", .ucode = 0x200, }, { .uname = "PRQ", .udesc = "IRQ is blocking the ingress queue and causing starvation", .ucode = 0x400, }, { .uname = "ISMQ_BIDS", .udesc = "Number of time the ISMQ bids", .ucode = 0x800, }, }; static const intel_x86_umask_t hswep_unc_c_rxr_inserts[]={ { .uname = "IRQ", .udesc = "IRQ", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "IRQ_REJECTED", .udesc = "IRQ rejected", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "IPQ", .udesc = "IPQ", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "PRQ", .udesc = "PRQ", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "PRQ_REJECTED", .udesc = "PRQ rejected", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t hswep_unc_c_rxr_ipq_retry[]={ { .uname = "ADDR_CONFLICT", .udesc = "Address conflict", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ANY", .udesc = "Any Reject", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "FULL", .udesc = "No Egress credits", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "QPI_CREDITS", .udesc = "No QPI credits", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t hswep_unc_c_rxr_ipq_retry2[]={ { .uname = "AD_SBO", .udesc = "Count number of time that a request from the IPQ was retried because it lacked credits to send an AD packet to SBO", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "TARGET", .udesc = "Count number of times that a request from the IPQ was retried filtered by the target NodeId", .ucode = 0x100, .umodmsk_req = _SNBEP_UNC_ATTR_NF1, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t hswep_unc_c_rxr_irq_retry[]={ { .uname = "ADDR_CONFLICT", .udesc = "Address conflict", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ANY", .udesc = "Any reject", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "FULL", .udesc = "No Egress credits", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "QPI_CREDITS", .udesc = "No QPI credits", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "RTID", .udesc = "No RTIDs", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "IIO_CREDITS", .udesc = "No IIO Credits", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t hswep_unc_c_rxr_irq_retry2[]={ { .uname = "AD_SBO", .udesc = "Count number of time that a request from the IRQ was retried because it lacked credits to send an AD packet to SBO", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "BL_SBO", .udesc = "Count number of time that a request from the IRQ was retried because it lacked credits to send an BL packet to SBO", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "TARGET", .udesc = "Count number of times that a request from the IRQ was retried filtered by the target NodeId", .ucode = 0x100, .umodmsk_req = _SNBEP_UNC_ATTR_NF1, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t hswep_unc_c_rxr_ismq_retry[]={ { .uname = "ANY", .udesc = "Any reject", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "FULL", .udesc = "No Egress credits", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "IIO_CREDITS", .udesc = "No IIO credits", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "QPI_CREDITS", .udesc = "NO QPI credits", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "RTID", .udesc = "No RTIDs", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "WB_CREDITS", .udesc = "No WB credits", .ucode = 0x8000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t hswep_unc_c_rxr_ismq_retry2[]={ { .uname = "AD_SBO", .udesc = "Count number of time that a request from the ISMQ was retried because it lacked credits to send an AD packet to SBO", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "BL_SBO", .udesc = "Count number of time that a request from the ISMQ was retried because it lacked credits to send an BL packet to SBO", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "TARGET", .udesc = "Count number of times that a request from the ISMQ was retried filtered by the target NodeId", .ucode = 0x100, .umodmsk_req = _SNBEP_UNC_ATTR_NF1, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t hswep_unc_c_tor_inserts[]={ { .uname = "OPCODE", .udesc = "Number of transactions inserted into the TOR that match an opcode (must provide opc_* umask)", .ucode = 0x100, .grpid = 0, .uflags = INTEL_X86_NCOMBO, }, { .uname = "MISS_OPCODE", .udesc = "Number of miss transactions inserted into the TOR that match an opcode (must provide opc_* umask)", .ucode = 0x300, .grpid = 0, .uflags = INTEL_X86_NCOMBO, }, { .uname = "EVICTION", .udesc = "Number of Evictions transactions inserted into TOR", .ucode = 0x400, .grpid = 0, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, }, { .uname = "ALL", .udesc = "Number of transactions inserted in TOR", .ucode = 0x800, .grpid = 0, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL | INTEL_X86_EXCL_GRP_GT, }, { .uname = "WB", .udesc = "Number of write transactions inserted into the TOR", .ucode = 0x1000, .grpid = 0, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, }, { .uname = "LOCAL_OPCODE", .udesc = "Number of opcode-matched transactions inserted into the TOR that are satisfied by locally homed memory", .ucode = 0x2100, .grpid = 0, .uflags = INTEL_X86_NCOMBO, }, { .uname = "MISS_LOCAL_OPCODE", .udesc = "Number of miss opcode-matched transactions inserted into the TOR that are satisfied by locally homed memory", .ucode = 0x2300, .grpid = 0, .uflags = INTEL_X86_NCOMBO, }, { .uname = "LOCAL", .udesc = "Number of transactions inserted into the TOR that are satisfied by locally homed memory", .ucode = 0x2800, .grpid = 0, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, }, { .uname = "MISS_LOCAL", .udesc = "Number of miss transactions inserted into the TOR that are satisfied by locally homed memory", .ucode = 0x2a00, .grpid = 0, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, }, { .uname = "NID_OPCODE", .udesc = "Number of transactions inserted into the TOR that match a NID and opcode (must provide opc_* umask and nf=X modifier)", .ucode = 0x4100, .grpid = 0, .umodmsk_req = _SNBEP_UNC_ATTR_NF1, .uflags = INTEL_X86_NCOMBO, }, { .uname = "NID_MISS_OPCODE", .udesc = "Number of NID and opcode matched miss transactions inserted into the TOR (must provide opc_* umask and nf=X modifier)", .ucode = 0x4300, .grpid = 0, .umodmsk_req = _SNBEP_UNC_ATTR_NF1, .uflags = INTEL_X86_NCOMBO, }, { .uname = "NID_EVICTION", .udesc = "Number of NID-matched eviction transactions inserted into the TOR (must provide nf=X modifier)", .ucode = 0x4400, .grpid = 0, .umodmsk_req = _SNBEP_UNC_ATTR_NF1, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, }, { .uname = "NID_ALL", .udesc = "Number of NID-matched transactions inserted into the TOR (must provide nf=X modifier)", .ucode = 0x4800, .grpid = 0, .umodmsk_req = _SNBEP_UNC_ATTR_NF1, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, }, { .uname = "NID_MISS_ALL", .udesc = "Number of NID-matched miss transactions that were inserted into the TOR (must provide nf=X modifier)", .ucode = 0x4a00, .grpid = 0, .umodmsk_req = _SNBEP_UNC_ATTR_NF1, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, }, { .uname = "NID_WB", .udesc = "Number of NID-matched write back transactions inserted into the TOR (must provide nf=X modifier)", .ucode = 0x5000, .grpid = 0, .umodmsk_req = _SNBEP_UNC_ATTR_NF1, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, }, { .uname = "REMOTE_OPCODE", .udesc = "Number of opcode-matched transactions inserted into the TOR that are satisfied by remote caches or memory", .ucode = 0x8100, .grpid = 0, .uflags = INTEL_X86_NCOMBO, }, { .uname = "MISS_REMOTE_OPCODE", .udesc = "Number of miss opcode-matched transactions inserted into the TOR that are satisfied by remote caches or memory", .ucode = 0x8300, .grpid = 0, .uflags = INTEL_X86_NCOMBO, }, { .uname = "REMOTE", .udesc = "Number of transactions inserted into the TOR that are satisfied by remote caches or memory", .ucode = 0x8800, .grpid = 0, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, }, { .uname = "MISS_REMOTE", .udesc = "Number of miss transactions inserted into the TOR that are satisfied by remote caches or memory", .ucode = 0x8a00, .grpid = 0, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, }, CBO_FILT_OPC(1) }; static const intel_x86_umask_t hswep_unc_c_tor_occupancy[]={ { .uname = "OPCODE", .udesc = "Number of TOR entries that match an opcode (must provide opc_* umask)", .ucode = 0x100, .grpid = 0, .uflags = INTEL_X86_NCOMBO, }, { .uname = "MISS_OPCODE", .udesc = "Number of TOR entries that match a NID and an opcode (must provide opc_* umask)", .ucode = 0x300, .grpid = 0, .uflags = INTEL_X86_NCOMBO, }, { .uname = "EVICTION", .udesc = "Number of outstanding eviction transactions in the TOR", .ucode = 0x400, .grpid = 0, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, }, { .uname = "ALL", .udesc = "All valid TOR entries", .ucode = 0x800, .grpid = 0, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL | INTEL_X86_EXCL_GRP_GT, }, { .uname = "MISS_ALL", .udesc = "Number of outstanding miss requests in the TOR", .ucode = 0xa00, .grpid = 0, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, }, { .uname = "WB", .udesc = "Number of write transactions in the TOR. Does not include RFO, but actual operations that contain data being sent from the core", .ucode = 0x1000, .grpid = 0, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, }, { .uname = "LOCAL_OPCODE", .udesc = "Number of opcode-matched transactions in the TOR that are satisfied by locally homed memory", .ucode = 0x2100, .grpid = 0, .uflags = INTEL_X86_NCOMBO, }, { .uname = "MISS_LOCAL_OPCODE", .udesc = "Number of miss opcode-matched transactions in the TOR that are satisfied by locally homed memory", .ucode = 0x2300, .grpid = 0, .uflags = INTEL_X86_NCOMBO, }, { .uname = "LOCAL", .udesc = "Number of transactions in the TOR that are satisfied by locally homed memory", .ucode = 0x2800, .grpid = 0, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, }, { .uname = "MISS_LOCAL", .udesc = "Number of miss transactions in the TOR that are satisfied by locally homed memory", .ucode = 0x2a00, .grpid = 0, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, }, { .uname = "NID_OPCODE", .udesc = "Number of NID-matched TOR entries that an opcode (must provide nf=X modifier and opc_* umask)", .ucode = 0x4100, .grpid = 0, .umodmsk_req = _SNBEP_UNC_ATTR_NF1, .uflags = INTEL_X86_NCOMBO, }, { .uname = "NID_MISS_OPCODE", .udesc = "Number of NID-matched outstanding miss requests in the TOR that an opcode (must provide nf=X modifier and opc_* umask)", .ucode = 0x4300, .grpid = 0, .umodmsk_req = _SNBEP_UNC_ATTR_NF1, .uflags = INTEL_X86_NCOMBO, }, { .uname = "NID_EVICTION", .udesc = "Number of NID-matched outstanding requests in the TOR (must provide a nf=X modifier)", .ucode = 0x4400, .grpid = 0, .umodmsk_req = _SNBEP_UNC_ATTR_NF1, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, }, { .uname = "NID_ALL", .udesc = "Number of NID-matched outstanding requests in the TOR (must provide nf=X modifier)", .ucode = 0x4800, .grpid = 0, .umodmsk_req = _SNBEP_UNC_ATTR_NF1, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, }, { .uname = "NID_MISS_ALL", .udesc = "Number of NID-matched outstanding miss requests in the TOR (must provide a nf=X modifier)", .ucode = 0x4a00, .grpid = 0, .umodmsk_req = _SNBEP_UNC_ATTR_NF1, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, }, { .uname = "NID_WB", .udesc = "Number of NID-matched write transactions in the TOR (must provide a nf=X modifier)", .ucode = 0x5000, .grpid = 0, .umodmsk_req = _SNBEP_UNC_ATTR_NF1, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, }, { .uname = "REMOTE_OPCODE", .udesc = "Number of opcode-matched transactions in the TOR that are satisfied by remote caches or memory", .ucode = 0x8100, .grpid = 0, .uflags = INTEL_X86_NCOMBO, }, { .uname = "MISS_REMOTE_OPCODE", .udesc = "Number of miss opcode-matched transactions in the TOR that are satisfied by remote caches or memory", .ucode = 0x8300, .grpid = 0, .uflags = INTEL_X86_NCOMBO, }, { .uname = "REMOTE", .udesc = "Number of transactions in the TOR that are satisfied by remote caches or memory", .ucode = 0x8800, .grpid = 0, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, }, { .uname = "MISS_REMOTE", .udesc = "Number of miss transactions inserted into the TOR that are satisfied by remote caches or memory", .ucode = 0x8a00, .grpid = 0, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, }, CBO_FILT_OPC(1) }; static const intel_x86_umask_t hswep_unc_c_txr_inserts[]={ { .uname = "AD_CACHE", .udesc = "Counts the number of ring transactions from Cachebo to AD ring", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "AK_CACHE", .udesc = "Counts the number of ring transactions from Cachebo to AK ring", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "BL_CACHE", .udesc = "Counts the number of ring transactions from Cachebo to BL ring", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "IV_CACHE", .udesc = "Counts the number of ring transactions from Cachebo ton IV ring", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "AD_CORE", .udesc = "Counts the number of ring transactions from Corebo to AD ring", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "AK_CORE", .udesc = "Counts the number of ring transactions from Corebo to AK ring", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "BL_CORE", .udesc = "Counts the number of ring transactions from Corebo to BL ring", .ucode = 0x4000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t hswep_unc_c_txr_ads_used[]={ { .uname = "AD", .udesc = "onto AD ring", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "AK", .udesc = "Onto AK ring", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "BL", .udesc = "Onto BL ring", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, } }; static const intel_x86_umask_t hswep_unc_c_misc[]={ { .uname = "RSPI_WAS_FSE", .udesc = "Counts the number of times when a SNoop hit in FSE states and triggered a silent eviction. This is useful because this information is lost in the PRE encodings", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "WC_ALIASING", .udesc = "Counts the number of times a USWC write (WCIL(F)) transaction hits in the LLC in M state, triggering a WBMTOI followed by the USWC write. This occurs when there is WC aliasing", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "STARTED", .udesc = "TBD", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "RFO_HIT_S", .udesc = "Counts the number of times that an RFO hits in S state. This is useful for determining if it might be good for a workload to use RSPIWB instead of RSPSWB", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "CVZERO_PREFETCH_VICTIM", .udesc = "Counts the number of clean victims with raw CV=0 (core valid)", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "CVZERO_PREFETCH_MISS", .udesc = "Counts the number of Demand Data Read requests hitting non-modified state lines with raw CV=0 (core valid)", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t hswep_unc_c_sbo_credits_acquired[]={ { .uname = "AD", .udesc = "for AD ring", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "BL", .udesc = "for BL ring", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, } }; static const intel_x86_entry_t intel_hswep_unc_c_pe[]={ { .name = "UNC_C_CLOCKTICKS", .desc = "C-box Uncore clockticks", .modmsk = 0x0, .cntmsk = 0xf, .code = 0x00, .flags = INTEL_X86_FIXED, }, { .name = "UNC_C_COUNTER0_OCCUPANCY", .desc = "Counter 0 occupancy. Counts the occupancy related information by filtering CB0 occupancy count captured in counter 0.", .modmsk = HSWEP_UNC_CBO_ATTRS, .cntmsk = 0xe, .code = 0x1f, }, { .name = "UNC_C_LLC_LOOKUP", .desc = "Cache lookups", .modmsk = HSWEP_UNC_CBO_NID_ATTRS, .cntmsk = 0xf, .code = 0x34, .ngrp = 3, .flags = INTEL_X86_NO_AUTOENCODE, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_c_llc_lookup), .umasks = hswep_unc_c_llc_lookup, }, { .name = "UNC_C_LLC_VICTIMS", .desc = "Lines victimized", .modmsk = HSWEP_UNC_CBO_NID_ATTRS, .cntmsk = 0xf, .code = 0x37, .flags = INTEL_X86_NO_AUTOENCODE, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_c_llc_victims), .ngrp = 2, .umasks = hswep_unc_c_llc_victims, }, { .name = "UNC_C_MISC", .desc = "Miscellaneous C-Box events", .modmsk = HSWEP_UNC_CBO_ATTRS, .cntmsk = 0xf, .code = 0x39, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_c_misc), .ngrp = 1, .umasks = hswep_unc_c_misc, }, { .name = "UNC_C_RING_AD_USED", .desc = "Address ring in use. Counts number of cycles ring is being used at this ring stop", .modmsk = HSWEP_UNC_CBO_ATTRS, .cntmsk = 0xf, .code = 0x1b, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_c_ring_ad_used), .ngrp = 1, .umasks = hswep_unc_c_ring_ad_used, }, { .name = "UNC_C_RING_AK_USED", .desc = "Acknowledgement ring in use. Counts number of cycles ring is being used at this ring stop", .modmsk = HSWEP_UNC_CBO_ATTRS, .cntmsk = 0xf, .code = 0x1c, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_c_ring_ad_used), /* identical to RING_AD_USED */ .ngrp = 1, .umasks = hswep_unc_c_ring_ad_used, }, { .name = "UNC_C_RING_BL_USED", .desc = "Bus or Data ring in use. Counts number of cycles ring is being used at this ring stop", .modmsk = HSWEP_UNC_CBO_ATTRS, .cntmsk = 0xf, .code = 0x1d, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_c_ring_ad_used), /* identical to RING_AD_USED */ .ngrp = 1, .umasks = hswep_unc_c_ring_ad_used, }, { .name = "UNC_C_RING_BOUNCES", .desc = "Number of LLC responses that bounced in the ring", .modmsk = HSWEP_UNC_CBO_ATTRS, .cntmsk = 0xf, .code = 0x05, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_c_ring_bounces), .ngrp = 1, .umasks = hswep_unc_c_ring_bounces, }, { .name = "UNC_C_FAST_ASSERTED", .desc = "Number of cycles in which the local distress or incoming distress signals are asserted (FaST). Incoming distress includes both up and down", .modmsk = HSWEP_UNC_CBO_ATTRS, .cntmsk = 0x3, .code = 0x09, }, { .name = "UNC_C_BOUNCE_CONTROL", .desc = "Bounce control", .modmsk = HSWEP_UNC_CBO_ATTRS, .cntmsk = 0xf, .code = 0x0a, }, { .name = "UNC_C_RING_IV_USED", .desc = "Invalidate ring in use. Counts number of cycles ring is being used at this ring stop", .modmsk = HSWEP_UNC_CBO_ATTRS, .cntmsk = 0xf, .code = 0x1e, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_c_ring_iv_used), .ngrp = 1, .umasks = hswep_unc_c_ring_iv_used, }, { .name = "UNC_C_RING_SRC_THRTL", .desc = "TDB", .modmsk = HSWEP_UNC_CBO_ATTRS, .cntmsk = 0xf, .code = 0x07, }, { .name = "UNC_C_RXR_EXT_STARVED", .desc = "Ingress arbiter blocking cycles", .modmsk = HSWEP_UNC_CBO_ATTRS, .cntmsk = 0xf, .code = 0x12, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_c_rxr_ext_starved), .ngrp = 1, .umasks = hswep_unc_c_rxr_ext_starved, }, { .name = "UNC_C_RXR_INSERTS", .desc = "Ingress Allocations", .code = 0x13, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_CBO_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_c_rxr_inserts), .umasks = hswep_unc_c_rxr_inserts }, { .name = "UNC_C_RXR_IPQ_RETRY", .desc = "Probe Queue Retries", .code = 0x31, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_CBO_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_c_rxr_ipq_retry), .umasks = hswep_unc_c_rxr_ipq_retry }, { .name = "UNC_C_RXR_IPQ_RETRY2", .desc = "Probe Queue Retries", .code = 0x28, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_CBO_NID_ATTRS, .flags = INTEL_X86_NO_AUTOENCODE, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_c_rxr_ipq_retry2), .umasks = hswep_unc_c_rxr_ipq_retry2 }, { .name = "UNC_C_RXR_IRQ_RETRY", .desc = "Ingress Request Queue Rejects", .code = 0x32, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_CBO_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_c_rxr_irq_retry), .umasks = hswep_unc_c_rxr_irq_retry }, { .name = "UNC_C_RXR_IRQ_RETRY2", .desc = "Ingress Request Queue Rejects", .code = 0x29, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_CBO_NID_ATTRS, .flags = INTEL_X86_NO_AUTOENCODE, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_c_rxr_irq_retry2), .umasks = hswep_unc_c_rxr_irq_retry2 }, { .name = "UNC_C_RXR_ISMQ_RETRY", .desc = "ISMQ Retries", .code = 0x33, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_CBO_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_c_rxr_ismq_retry), .umasks = hswep_unc_c_rxr_ismq_retry }, { .name = "UNC_C_RXR_ISMQ_RETRY2", .desc = "ISMQ Retries", .code = 0x2a, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_CBO_NID_ATTRS, .flags = INTEL_X86_NO_AUTOENCODE, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_c_rxr_ismq_retry2), .umasks = hswep_unc_c_rxr_ismq_retry2 }, { .name = "UNC_C_RXR_OCCUPANCY", .desc = "Ingress Occupancy", .code = 0x11, .cntmsk = 0x1, .ngrp = 1, .modmsk = HSWEP_UNC_CBO_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_c_rxr_inserts), .umasks = hswep_unc_c_rxr_inserts, /* identical to hswep_unc_c_rxr_inserts */ }, { .name = "UNC_C_TOR_INSERTS", .desc = "TOR Inserts", .code = 0x35, .cntmsk = 0xf, .ngrp = 2, .modmsk = HSWEP_UNC_CBO_NID_ATTRS | _SNBEP_UNC_ATTR_ISOC | _SNBEP_UNC_ATTR_NC, .flags = INTEL_X86_NO_AUTOENCODE, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_c_tor_inserts), .umasks = hswep_unc_c_tor_inserts }, { .name = "UNC_C_TOR_OCCUPANCY", .desc = "TOR Occupancy", .code = 0x36, .cntmsk = 0x1, .ngrp = 2, .modmsk = HSWEP_UNC_CBO_NID_ATTRS | _SNBEP_UNC_ATTR_ISOC | _SNBEP_UNC_ATTR_NC, .flags = INTEL_X86_NO_AUTOENCODE, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_c_tor_occupancy), .umasks = hswep_unc_c_tor_occupancy }, { .name = "UNC_C_TXR_ADS_USED", .desc = "Egress events", .code = 0x04, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_CBO_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_c_txr_ads_used), .umasks = hswep_unc_c_txr_ads_used }, { .name = "UNC_C_TXR_INSERTS", .desc = "Egress allocations", .code = 0x02, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_CBO_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_c_txr_inserts), .umasks = hswep_unc_c_txr_inserts }, { .name = "UNC_C_SBO_CREDITS_ACQUIRED", .desc = "SBO credits acquired", .code = 0x3d, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_CBO_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_c_sbo_credits_acquired), .umasks = hswep_unc_c_sbo_credits_acquired }, { .name = "UNC_C_SBO_CREDITS_OCCUPANCY", .desc = "SBO credits occupancy", .code = 0x3e, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_CBO_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_c_sbo_credits_acquired), /* shared */ .umasks = hswep_unc_c_sbo_credits_acquired }, }; libpfm-4.9.0/lib/events/intel_hswep_unc_sbo_events.h0000664000175000017500000001732213223402656022463 0ustar eranianeranian/* * Copyright (c) 2014 Google Inc. All rights reserved * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * PMU: hswep_unc_sbo (Intel Haswell-EP S-Box uncore PMU) */ static const intel_x86_umask_t hswep_unc_s_ring_ad_used[]={ { .uname = "UP_EVEN", .udesc = "Up and Even ring polarity filter", .ucode = 0x100, }, { .uname = "UP_ODD", .udesc = "Up and odd ring polarity filter", .ucode = 0x200, }, { .uname = "DOWN_EVEN", .udesc = "Down and even ring polarity filter", .ucode = 0x400, }, { .uname = "DOWN_ODD", .udesc = "Down and odd ring polarity filter", .ucode = 0x800, }, { .uname = "UP", .udesc = "Up ring polarity filter", .ucode = 0x3300, }, { .uname = "DOWN", .udesc = "Down ring polarity filter", .ucode = 0xcc00, }, }; static const intel_x86_umask_t hswep_unc_s_ring_bounces[]={ { .uname = "AD_CACHE", .udesc = "AD_CACHE", .ucode = 0x100, }, { .uname = "AK_CORE", .udesc = "Acknowledgments to core", .ucode = 0x200, }, { .uname = "BL_CORE", .udesc = "Data responses to core", .ucode = 0x400, }, { .uname = "IV_CORE", .udesc = "Snoops of processor cache", .ucode = 0x800, }, }; static const intel_x86_umask_t hswep_unc_s_ring_iv_used[]={ { .uname = "ANY", .udesc = "Any filter", .ucode = 0x0f00, .uflags = INTEL_X86_DFL, }, { .uname = "UP", .udesc = "Filter on any up polarity", .ucode = 0x0300, }, { .uname = "DOWN", .udesc = "Filter on any down polarity", .ucode = 0xcc00, }, }; static const intel_x86_umask_t hswep_unc_s_rxr_bypass[]={ { .uname = "AD_CRD", .udesc = "AD credis", .ucode = 0x0100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "AD_BNC", .udesc = "AD bounces", .ucode = 0x0200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "BL_CRD", .udesc = "BL credits", .ucode = 0x0400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "BL_BNC", .udesc = "BL bounces", .ucode = 0x0800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "AK", .udesc = "AK", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "IV", .udesc = "IV", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t hswep_unc_s_txr_ads_used[]={ { .uname = "AD", .udesc = "onto AD ring", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "AK", .udesc = "Onto AK ring", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "BL", .udesc = "Onto BL ring", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, } }; static const intel_x86_entry_t intel_hswep_unc_s_pe[]={ { .name = "UNC_S_CLOCKTICKS", .desc = "S-box Uncore clockticks", .modmsk = HSWEP_UNC_SBO_ATTRS, .cntmsk = 0xf, .code = 0x00, }, { .name = "UNC_S_RING_AD_USED", .desc = "Address ring in use. Counts number of cycles ring is being used at this ring stop", .modmsk = HSWEP_UNC_SBO_ATTRS, .cntmsk = 0xf, .code = 0x1b, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_s_ring_ad_used), .ngrp = 1, .umasks = hswep_unc_s_ring_ad_used, }, { .name = "UNC_S_RING_AK_USED", .desc = "Acknowledgement ring in use. Counts number of cycles ring is being used at this ring stop", .modmsk = HSWEP_UNC_SBO_ATTRS, .cntmsk = 0xf, .code = 0x1c, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_s_ring_ad_used), /* identical to RING_AD_USED */ .ngrp = 1, .umasks = hswep_unc_s_ring_ad_used, }, { .name = "UNC_S_RING_BL_USED", .desc = "Bus or Data ring in use. Counts number of cycles ring is being used at this ring stop", .modmsk = HSWEP_UNC_SBO_ATTRS, .cntmsk = 0xf, .code = 0x1d, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_s_ring_ad_used), /* identical to RING_AD_USED */ .ngrp = 1, .umasks = hswep_unc_s_ring_ad_used, }, { .name = "UNC_S_RING_IV_USED", .desc = "Invalidate ring in use. Counts number of cycles ring is being used at this ring stop", .modmsk = HSWEP_UNC_SBO_ATTRS, .cntmsk = 0xf, .code = 0x1e, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_s_ring_iv_used), .ngrp = 1, .umasks = hswep_unc_s_ring_iv_used, }, { .name = "UNC_S_RING_BOUNCES", .desc = "Number of LLC responses that bounced in the ring", .modmsk = HSWEP_UNC_SBO_ATTRS, .cntmsk = 0xf, .code = 0x05, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_s_ring_bounces), .ngrp = 1, .umasks = hswep_unc_s_ring_bounces, }, { .name = "UNC_S_FAST_ASSERTED", .desc = "Number of cycles in which the local distress or incoming distress signals are asserted (FaST). Incoming distress includes both up and down", .modmsk = HSWEP_UNC_SBO_ATTRS, .cntmsk = 0xf, .code = 0x09, }, { .name = "UNC_C_BOUNCE_CONTROL", .desc = "Bounce control", .modmsk = HSWEP_UNC_SBO_ATTRS, .cntmsk = 0xf, .code = 0x0a, }, { .name = "UNC_S_RXR_OCCUPANCY", .desc = "Ingress Occupancy", .code = 0x11, .cntmsk = 0x1, .ngrp = 1, .modmsk = HSWEP_UNC_SBO_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_s_rxr_bypass), /* shared with rxr_bypass */ .umasks = hswep_unc_s_rxr_bypass, }, { .name = "UNC_S_RXR_BYPASS", .desc = "Ingress Allocations", .code = 0x12, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_SBO_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_s_rxr_bypass), .umasks = hswep_unc_s_rxr_bypass }, { .name = "UNC_S_RXR_INSERTS", .desc = "Ingress Allocations", .code = 0x13, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_SBO_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_s_rxr_bypass), /* shared with rxr_bypass */ .umasks = hswep_unc_s_rxr_bypass }, { .name = "UNC_S_TXR_ADS_USED", .desc = "Egress events", .code = 0x04, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_SBO_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_s_txr_ads_used), .umasks = hswep_unc_s_txr_ads_used }, { .name = "UNC_S_TXR_INSERTS", .desc = "Egress allocations", .code = 0x02, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_SBO_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_s_rxr_bypass), /* shared with rxr_bypass */ .umasks = hswep_unc_s_rxr_bypass }, { .name = "UNC_S_TXR_OCCUPANCY", .desc = "Egress allocations", .code = 0x01, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_SBO_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_s_rxr_bypass), /* shared with rxr_bypass */ .umasks = hswep_unc_s_rxr_bypass }, }; libpfm-4.9.0/lib/events/intel_snbep_unc_r2pcie_events.h0000664000175000017500000001301213223402656023035 0ustar eranianeranian/* * Copyright (c) 2012 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * This file has been automatically generated. * * PMU: snbep_unc_r2pcie (Intel SandyBridge-EP R2PCIe uncore) */ static const intel_x86_umask_t snbep_unc_r2_ring_ad_used[]={ { .uname = "CCW_EVEN", .udesc = "Counter-clockwise and even ring polarity", .ucode = 0x400, }, { .uname = "CCW_ODD", .udesc = "Counter-clockwise and odd ring polarity", .ucode = 0x800, }, { .uname = "CW_EVEN", .udesc = "Clockwise and even ring polarity", .ucode = 0x100, }, { .uname = "CW_ODD", .udesc = "Clockwise and odd ring polarity", .ucode = 0x200, }, { .uname = "CW_ANY", .udesc = "Clockwise with any polarity", .ucode = 0x300, }, { .uname = "CCW_ANY", .udesc = "Counter-clockwise with any polarity", .ucode = 0xc00, }, { .uname = "ANY", .udesc = "any direction and any polarity", .ucode = 0xf00, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t snbep_unc_r2_ring_iv_used[]={ { .uname = "ANY", .udesc = "R2 IV Ring in Use", .ucode = 0xf00, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t snbep_unc_r2_rxr_cycles_ne[]={ { .uname = "DRS", .udesc = "DRS Ingress queue", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "NCB", .udesc = "NCB Ingress queue", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "NCS", .udesc = "NCS Ingress queue", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t snbep_unc_r2_txr_cycles_full[]={ { .uname = "AD", .udesc = "AD Egress queue", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "AK", .udesc = "AK Egress queue", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "BL", .udesc = "BL Egress queue", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_entry_t intel_snbep_unc_r2_pe[]={ { .name = "UNC_R2_CLOCKTICKS", .desc = "Number of uclks in domain", .code = 0x1, .cntmsk = 0xf, .modmsk = SNBEP_UNC_R2PCIE_ATTRS, }, { .name = "UNC_R2_RING_AD_USED", .desc = "R2 AD Ring in Use", .code = 0x7, .cntmsk = 0xf, .ngrp = 1, .modmsk = SNBEP_UNC_R2PCIE_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_r2_ring_ad_used), .umasks = snbep_unc_r2_ring_ad_used }, { .name = "UNC_R2_RING_AK_USED", .desc = "R2 AK Ring in Use", .code = 0x8, .cntmsk = 0xf, .ngrp = 1, .modmsk = SNBEP_UNC_R2PCIE_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_r2_ring_ad_used), .umasks = snbep_unc_r2_ring_ad_used /* shared */ }, { .name = "UNC_R2_RING_BL_USED", .desc = "R2 BL Ring in Use", .code = 0x9, .cntmsk = 0xf, .ngrp = 1, .modmsk = SNBEP_UNC_R2PCIE_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_r2_ring_ad_used), .umasks = snbep_unc_r2_ring_ad_used /* shared */ }, { .name = "UNC_R2_RING_IV_USED", .desc = "R2 IV Ring in Use", .code = 0xa, .cntmsk = 0xf, .ngrp = 1, .modmsk = SNBEP_UNC_R2PCIE_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_r2_ring_iv_used), .umasks = snbep_unc_r2_ring_iv_used }, { .name = "UNC_R2_RXR_AK_BOUNCES", .desc = "AK Ingress Bounced", .code = 0x12, .cntmsk = 0x1, .modmsk = SNBEP_UNC_R2PCIE_ATTRS, }, { .name = "UNC_R2_RXR_CYCLES_NE", .desc = "Ingress Cycles Not Empty", .code = 0x10, .cntmsk = 0x3, .ngrp = 1, .modmsk = SNBEP_UNC_R2PCIE_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_r2_rxr_cycles_ne), .umasks = snbep_unc_r2_rxr_cycles_ne }, { .name = "UNC_R2_TXR_CYCLES_FULL", .desc = "Egress Cycles Full", .code = 0x25, .cntmsk = 0x1, .ngrp = 1, .modmsk = SNBEP_UNC_R2PCIE_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_r2_txr_cycles_full), .umasks = snbep_unc_r2_txr_cycles_full }, { .name = "UNC_R2_TXR_CYCLES_NE", .desc = "Egress Cycles Not Empty", .code = 0x23, .cntmsk = 0x1, .ngrp = 1, .modmsk = SNBEP_UNC_R2PCIE_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_r2_txr_cycles_full), .umasks = snbep_unc_r2_txr_cycles_full /* shared */ }, { .name = "UNC_R2_TXR_INSERTS", .desc = "Egress allocations", .code = 0x24, .cntmsk = 0x1, .modmsk = SNBEP_UNC_R2PCIE_ATTRS, }, }; libpfm-4.9.0/lib/events/intel_snbep_unc_ubo_events.h0000664000175000017500000000451613223402656022447 0ustar eranianeranian/* * Copyright (c) 2012 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * PMU: snbep_unc_ubo (Intel SandyBridge-EP U-Box uncore PMU) */ static const intel_x86_umask_t snbep_unc_u_event_msg[]={ { .uname = "DOORBELL_RCVD", .udesc = "TBD", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "INT_PRIO", .udesc = "TBD", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "IPI_RCVD", .udesc = "TBD", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "MSI_RCVD", .udesc = "TBD", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "VLW_RCVD", .udesc = "TBD", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_entry_t intel_snbep_unc_u_pe[]={ { .name = "UNC_U_EVENT_MSG", .desc = "VLW Received", .code = 0x42, .cntmsk = 0x3, .ngrp = 1, .modmsk = SNBEP_UNC_UBO_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_u_event_msg), .umasks = snbep_unc_u_event_msg }, { .name = "UNC_U_LOCK_CYCLES", .desc = "IDI Lock/SplitLock Cycles", .code = 0x44, .cntmsk = 0x3, .modmsk = SNBEP_UNC_UBO_ATTRS, }, }; libpfm-4.9.0/lib/events/intel_core_events.h0000664000175000017500000014744013223402656020562 0ustar eranianeranian/* * Copyright (c) 2011 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * This file has been automatically generated. * * PMU: core (Intel Core) */ static const intel_x86_umask_t core_rs_uops_dispatched_cycles[]={ { .uname = "PORT_0", .udesc = "On port 0", .ucode = 0x100, }, { .uname = "PORT_1", .udesc = "On port 1", .ucode = 0x200, }, { .uname = "PORT_2", .udesc = "On port 2", .ucode = 0x400, }, { .uname = "PORT_3", .udesc = "On port 3", .ucode = 0x800, }, { .uname = "PORT_4", .udesc = "On port 4", .ucode = 0x1000, }, { .uname = "PORT_5", .udesc = "On port 5", .ucode = 0x2000, }, { .uname = "ANY", .udesc = "On any port", .uequiv = "PORT_0:PORT_1:PORT_2:PORT_3:PORT_4:PORT_5", .ucode = 0x3f00, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t core_load_block[]={ { .uname = "STA", .udesc = "Loads blocked by a preceding store with unknown address", .ucode = 0x200, }, { .uname = "STD", .udesc = "Loads blocked by a preceding store with unknown data", .ucode = 0x400, }, { .uname = "OVERLAP_STORE", .udesc = "Loads that partially overlap an earlier store, or 4K equived with a previous store", .ucode = 0x800, }, { .uname = "UNTIL_RETIRE", .udesc = "Loads blocked until retirement", .ucode = 0x1000, }, { .uname = "L1D", .udesc = "Loads blocked by the L1 data cache", .ucode = 0x2000, }, }; static const intel_x86_umask_t core_store_block[]={ { .uname = "ORDER", .udesc = "Cycles while store is waiting for a preceding store to be globally observed", .ucode = 0x200, }, { .uname = "SNOOP", .udesc = "A store is blocked due to a conflict with an external or internal snoop", .ucode = 0x800, }, }; static const intel_x86_umask_t core_sse_pre_exec[]={ { .uname = "NTA", .udesc = "Streaming SIMD Extensions (SSE) Prefetch NTA instructions executed", .ucode = 0x0, .uflags= INTEL_X86_NCOMBO, }, { .uname = "L1", .udesc = "Streaming SIMD Extensions (SSE) PrefetchT0 instructions executed", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "L2", .udesc = "Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions executed", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "STORES", .udesc = "Streaming SIMD Extensions (SSE) Weakly-ordered store instructions executed", .ucode = 0x300, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t core_dtlb_misses[]={ { .uname = "ANY", .udesc = "Any memory access that missed the DTLB", .ucode = 0x100, .uflags= INTEL_X86_DFL, }, { .uname = "MISS_LD", .udesc = "DTLB misses due to load operations", .ucode = 0x200, }, { .uname = "L0_MISS_LD", .udesc = "L0 DTLB misses due to load operations", .ucode = 0x400, }, { .uname = "MISS_ST", .udesc = "DTLB misses due to store operations", .ucode = 0x800, }, }; static const intel_x86_umask_t core_memory_disambiguation[]={ { .uname = "RESET", .udesc = "Memory disambiguation reset cycles", .ucode = 0x100, }, { .uname = "SUCCESS", .udesc = "Number of loads that were successfully disambiguated", .ucode = 0x200, }, }; static const intel_x86_umask_t core_page_walks[]={ { .uname = "COUNT", .udesc = "Number of page-walks executed", .ucode = 0x100, }, { .uname = "CYCLES", .udesc = "Duration of page-walks in core cycles", .ucode = 0x200, }, }; static const intel_x86_umask_t core_delayed_bypass[]={ { .uname = "FP", .udesc = "Delayed bypass to FP operation", .ucode = 0x0, }, { .uname = "SIMD", .udesc = "Delayed bypass to SIMD operation", .ucode = 0x100, }, { .uname = "LOAD", .udesc = "Delayed bypass to load operation", .ucode = 0x200, }, }; static const intel_x86_umask_t core_l2_ads[]={ { .uname = "SELF", .udesc = "This core", .ucode = 0x4000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "BOTH_CORES", .udesc = "Both cores", .ucode = 0xc000, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t core_l2_lines_in[]={ { .uname = "SELF", .udesc = "This core", .ucode = 0x4000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, .grpid = 0, }, { .uname = "BOTH_CORES", .udesc = "Both cores", .ucode = 0xc000, .uflags= INTEL_X86_NCOMBO, .grpid = 0, }, { .uname = "ANY", .udesc = "All inclusive", .ucode = 0x3000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, .grpid = 1, }, { .uname = "PREFETCH", .udesc = "Hardware prefetch only", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO, .grpid = 1, }, { .uname = "EXCL_PREFETCH", .udesc = "Exclude hardware prefetch", .ucode = 0x0, .uflags= INTEL_X86_NCOMBO, .grpid = 1, }, }; static const intel_x86_umask_t core_l2_ifetch[]={ { .uname = "SELF", .udesc = "This core", .ucode = 0x4000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, .grpid = 0, }, { .uname = "BOTH_CORES", .udesc = "Both cores", .ucode = 0xc000, .uflags= INTEL_X86_NCOMBO, .grpid = 0, }, { .uname = "MESI", .udesc = "Any cacheline access", .uequiv = "M_STATE:E_STATE:S_STATE:I_STATE", .ucode = 0xf00, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, .grpid = 1, }, { .uname = "I_STATE", .udesc = "Invalid cacheline", .ucode = 0x100, .grpid = 1, }, { .uname = "S_STATE", .udesc = "Shared cacheline", .ucode = 0x200, .grpid = 1, }, { .uname = "E_STATE", .udesc = "Exclusive cacheline", .ucode = 0x400, .grpid = 1, }, { .uname = "M_STATE", .udesc = "Modified cacheline", .ucode = 0x800, .grpid = 1, }, }; static const intel_x86_umask_t core_l2_ld[]={ { .uname = "SELF", .udesc = "This core", .ucode = 0x4000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, .grpid = 0, }, { .uname = "BOTH_CORES", .udesc = "Both cores", .ucode = 0xc000, .uflags= INTEL_X86_NCOMBO, .grpid = 0, }, { .uname = "ANY", .udesc = "All inclusive", .ucode = 0x3000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, .grpid = 1, }, { .uname = "PREFETCH", .udesc = "Hardware prefetch only", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO, .grpid = 1, }, { .uname = "EXCL_PREFETCH", .udesc = "Exclude hardware prefetch", .ucode = 0x0, .uflags= INTEL_X86_NCOMBO, .grpid = 1, }, { .uname = "MESI", .udesc = "Any cacheline access", .uequiv = "M_STATE:E_STATE:S_STATE:I_STATE", .ucode = 0xf00, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, .grpid = 2, }, { .uname = "I_STATE", .udesc = "Invalid cacheline", .ucode = 0x100, .grpid = 2, }, { .uname = "S_STATE", .udesc = "Shared cacheline", .ucode = 0x200, .grpid = 2, }, { .uname = "E_STATE", .udesc = "Exclusive cacheline", .ucode = 0x400, .grpid = 2, }, { .uname = "M_STATE", .udesc = "Modified cacheline", .ucode = 0x800, .grpid = 2, }, }; static const intel_x86_umask_t core_cpu_clk_unhalted[]={ { .uname = "CORE_P", .udesc = "Core cycles when core is not halted", .ucode = 0x0, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "BUS", .udesc = "Bus cycles when core is not halted. This event can give a measurement of the elapsed time. This events has a constant ratio with CPU_CLK_UNHALTED:REF event, which is the maximum bus to processor frequency ratio", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "NO_OTHER", .udesc = "Bus cycles when core is active and the other is halted", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t core_l1d_cache_ld[]={ { .uname = "MESI", .udesc = "Any cacheline access", .uequiv = "M_STATE:E_STATE:S_STATE:I_STATE", .ucode = 0xf00, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "I_STATE", .udesc = "Invalid cacheline", .ucode = 0x100, }, { .uname = "S_STATE", .udesc = "Shared cacheline", .ucode = 0x200, }, { .uname = "E_STATE", .udesc = "Exclusive cacheline", .ucode = 0x400, }, { .uname = "M_STATE", .udesc = "Modified cacheline", .ucode = 0x800, }, }; static const intel_x86_umask_t core_l1d_split[]={ { .uname = "LOADS", .udesc = "Cache line split loads from the L1 data cache", .ucode = 0x100, }, { .uname = "STORES", .udesc = "Cache line split stores to the L1 data cache", .ucode = 0x200, }, }; static const intel_x86_umask_t core_sse_pre_miss[]={ { .uname = "NTA", .udesc = "Streaming SIMD Extensions (SSE) Prefetch NTA instructions missing all cache levels", .ucode = 0x0, }, { .uname = "L1", .udesc = "Streaming SIMD Extensions (SSE) PrefetchT0 instructions missing all cache levels", .ucode = 0x100, }, { .uname = "L2", .udesc = "Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions missing all cache levels", .ucode = 0x200, }, }; static const intel_x86_umask_t core_l1d_prefetch[]={ { .uname = "REQUESTS", .udesc = "L1 data cache prefetch requests", .ucode = 0x1000, .uflags= INTEL_X86_DFL, }, }; static const intel_x86_umask_t core_bus_request_outstanding[]={ { .uname = "SELF", .udesc = "This core", .ucode = 0x4000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, .grpid = 0, }, { .uname = "BOTH_CORES", .udesc = "Both cores", .ucode = 0xc000, .uflags= INTEL_X86_NCOMBO, .grpid = 0, }, { .uname = "THIS_AGENT", .udesc = "This agent", .ucode = 0x0, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, .grpid = 1, }, { .uname = "ALL_AGENTS", .udesc = "Any agent on the bus", .ucode = 0x2000, .uflags= INTEL_X86_NCOMBO, .grpid = 1, }, }; static const intel_x86_umask_t core_bus_bnr_drv[]={ { .uname = "THIS_AGENT", .udesc = "This agent", .ucode = 0x0, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "ALL_AGENTS", .udesc = "Any agent on the bus", .ucode = 0x2000, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t core_ext_snoop[]={ { .uname = "ANY", .udesc = "Any external snoop response", .ucode = 0xb00, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, .grpid = 0, }, { .uname = "CLEAN", .udesc = "External snoop CLEAN response", .ucode = 0x100, .grpid = 0, }, { .uname = "HIT", .udesc = "External snoop HIT response", .ucode = 0x200, .grpid = 0, }, { .uname = "HITM", .udesc = "External snoop HITM response", .ucode = 0x800, .grpid = 0, }, { .uname = "THIS_AGENT", .udesc = "This agent", .ucode = 0x0, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, .grpid = 1, }, { .uname = "ALL_AGENTS", .udesc = "Any agent on the bus", .ucode = 0x2000, .uflags= INTEL_X86_NCOMBO, .grpid = 1, }, }; static const intel_x86_umask_t core_cmp_snoop[]={ { .uname = "ANY", .udesc = "L1 data cache is snooped by other core", .ucode = 0x300, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, .grpid = 0, }, { .uname = "SHARE", .udesc = "L1 data cache is snooped for sharing by other core", .ucode = 0x100, .grpid = 0, }, { .uname = "INVALIDATE", .udesc = "L1 data cache is snooped for Invalidation by other core", .ucode = 0x200, .grpid = 0, }, { .uname = "SELF", .udesc = "This core", .ucode = 0x4000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, .grpid = 1, }, { .uname = "BOTH_CORES", .udesc = "Both cores", .ucode = 0xc000, .uflags= INTEL_X86_NCOMBO, .grpid = 1, }, }; static const intel_x86_umask_t core_itlb[]={ { .uname = "SMALL_MISS", .udesc = "ITLB small page misses", .ucode = 0x200, }, { .uname = "LARGE_MISS", .udesc = "ITLB large page misses", .ucode = 0x1000, }, { .uname = "FLUSH", .udesc = "ITLB flushes", .ucode = 0x4000, }, { .uname = "MISSES", .udesc = "ITLB misses", .ucode = 0x1200, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t core_inst_queue[]={ { .uname = "FULL", .udesc = "Cycles during which the instruction queue is full", .ucode = 0x200, .uflags= INTEL_X86_DFL, }, }; static const intel_x86_umask_t core_macro_insts[]={ { .uname = "DECODED", .udesc = "Instructions decoded", .ucode = 0x100, }, { .uname = "CISC_DECODED", .udesc = "CISC instructions decoded", .ucode = 0x800, }, }; static const intel_x86_umask_t core_esp[]={ { .uname = "SYNCH", .udesc = "ESP register content synchronization", .ucode = 0x100, }, { .uname = "ADDITIONS", .udesc = "ESP register automatic additions", .ucode = 0x200, }, }; static const intel_x86_umask_t core_simd_uop_type_exec[]={ { .uname = "MUL", .udesc = "SIMD packed multiply micro-ops executed", .ucode = 0x100, }, { .uname = "SHIFT", .udesc = "SIMD packed shift micro-ops executed", .ucode = 0x200, }, { .uname = "PACK", .udesc = "SIMD pack micro-ops executed", .ucode = 0x400, }, { .uname = "UNPACK", .udesc = "SIMD unpack micro-ops executed", .ucode = 0x800, }, { .uname = "LOGICAL", .udesc = "SIMD packed logical micro-ops executed", .ucode = 0x1000, }, { .uname = "ARITHMETIC", .udesc = "SIMD packed arithmetic micro-ops executed", .ucode = 0x2000, }, }; static const intel_x86_umask_t core_inst_retired[]={ { .uname = "ANY_P", .udesc = "Instructions retired (Precise Event)", .ucode = 0x0, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS | INTEL_X86_DFL, }, { .uname = "LOADS", .udesc = "Instructions retired, which contain a load", .ucode = 0x100, }, { .uname = "STORES", .udesc = "Instructions retired, which contain a store", .ucode = 0x200, }, { .uname = "OTHER", .udesc = "Instructions retired, with no load or store operation", .ucode = 0x400, }, }; static const intel_x86_umask_t core_x87_ops_retired[]={ { .uname = "FXCH", .udesc = "FXCH instructions retired", .ucode = 0x100, }, { .uname = "ANY", .udesc = "Retired floating-point computational operations (Precise Event)", .ucode = 0xfe00, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS | INTEL_X86_DFL, }, }; static const intel_x86_umask_t core_uops_retired[]={ { .uname = "LD_IND_BR", .udesc = "Fused load+op or load+indirect branch retired", .ucode = 0x100, }, { .uname = "STD_STA", .udesc = "Fused store address + data retired", .ucode = 0x200, }, { .uname = "MACRO_FUSION", .udesc = "Retired instruction pairs fused into one micro-op", .ucode = 0x400, }, { .uname = "NON_FUSED", .udesc = "Non-fused micro-ops retired", .ucode = 0x800, }, { .uname = "FUSED", .udesc = "Fused micro-ops retired", .ucode = 0x700, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ANY", .udesc = "Micro-ops retired", .ucode = 0xf00, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t core_machine_nukes[]={ { .uname = "SMC", .udesc = "Self-Modifying Code detected", .ucode = 0x100, }, { .uname = "MEM_ORDER", .udesc = "Execution pipeline restart due to memory ordering conflict or memory disambiguation misprediction", .ucode = 0x400, }, }; static const intel_x86_umask_t core_br_inst_retired[]={ { .uname = "ANY", .udesc = "Retired branch instructions", .ucode = 0x0, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "PRED_NOT_TAKEN", .udesc = "Retired branch instructions that were predicted not-taken", .ucode = 0x100, }, { .uname = "MISPRED_NOT_TAKEN", .udesc = "Retired branch instructions that were mispredicted not-taken", .ucode = 0x200, }, { .uname = "PRED_TAKEN", .udesc = "Retired branch instructions that were predicted taken", .ucode = 0x400, }, { .uname = "MISPRED_TAKEN", .udesc = "Retired branch instructions that were mispredicted taken", .ucode = 0x800, }, { .uname = "TAKEN", .udesc = "Retired taken branch instructions", .ucode = 0xc00, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t core_simd_inst_retired[]={ { .uname = "PACKED_SINGLE", .udesc = "Retired Streaming SIMD Extensions (SSE) packed-single instructions", .ucode = 0x100, }, { .uname = "SCALAR_SINGLE", .udesc = "Retired Streaming SIMD Extensions (SSE) scalar-single instructions", .ucode = 0x200, }, { .uname = "PACKED_DOUBLE", .udesc = "Retired Streaming SIMD Extensions 2 (SSE2) packed-double instructions", .ucode = 0x400, }, { .uname = "SCALAR_DOUBLE", .udesc = "Retired Streaming SIMD Extensions 2 (SSE2) scalar-double instructions", .ucode = 0x800, }, { .uname = "VECTOR", .udesc = "Retired Streaming SIMD Extensions 2 (SSE2) vector integer instructions", .ucode = 0x1000, }, { .uname = "ANY", .udesc = "Retired Streaming SIMD instructions (Precise Event)", .ucode = 0x1f00, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS | INTEL_X86_DFL, }, }; static const intel_x86_umask_t core_simd_comp_inst_retired[]={ { .uname = "PACKED_SINGLE", .udesc = "Retired computational Streaming SIMD Extensions (SSE) packed-single instructions", .ucode = 0x100, }, { .uname = "SCALAR_SINGLE", .udesc = "Retired computational Streaming SIMD Extensions (SSE) scalar-single instructions", .ucode = 0x200, }, { .uname = "PACKED_DOUBLE", .udesc = "Retired computational Streaming SIMD Extensions 2 (SSE2) packed-double instructions", .ucode = 0x400, }, { .uname = "SCALAR_DOUBLE", .udesc = "Retired computational Streaming SIMD Extensions 2 (SSE2) scalar-double instructions", .ucode = 0x800, }, }; static const intel_x86_umask_t core_mem_load_retired[]={ { .uname = "L1D_MISS", .udesc = "Retired loads that miss the L1 data cache (Precise Event)", .ucode = 0x100, .uflags= INTEL_X86_PEBS, }, { .uname = "L1D_LINE_MISS", .udesc = "L1 data cache line missed by retired loads (Precise Event)", .ucode = 0x200, .uflags= INTEL_X86_PEBS, }, { .uname = "L2_MISS", .udesc = "Retired loads that miss the L2 cache (Precise Event)", .ucode = 0x400, .uflags= INTEL_X86_PEBS, }, { .uname = "L2_LINE_MISS", .udesc = "L2 cache line missed by retired loads (Precise Event)", .ucode = 0x800, .uflags= INTEL_X86_PEBS, }, { .uname = "DTLB_MISS", .udesc = "Retired loads that miss the DTLB (Precise Event)", .ucode = 0x1000, .uflags= INTEL_X86_PEBS, }, }; static const intel_x86_umask_t core_fp_mmx_trans[]={ { .uname = "TO_FP", .udesc = "Transitions from MMX (TM) Instructions to Floating Point Instructions", .ucode = 0x200, }, { .uname = "TO_MMX", .udesc = "Transitions from Floating Point to MMX (TM) Instructions", .ucode = 0x100, }, }; static const intel_x86_umask_t core_rat_stalls[]={ { .uname = "ROB_READ_PORT", .udesc = "ROB read port stalls cycles", .ucode = 0x100, }, { .uname = "PARTIAL_CYCLES", .udesc = "Partial register stall cycles", .ucode = 0x200, }, { .uname = "FLAGS", .udesc = "Flag stall cycles", .ucode = 0x400, }, { .uname = "FPSW", .udesc = "FPU status word stall", .ucode = 0x800, }, { .uname = "ANY", .udesc = "All RAT stall cycles", .ucode = 0xf00, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t core_seg_rename_stalls[]={ { .uname = "ES", .udesc = "Segment rename stalls - ES ", .ucode = 0x100, }, { .uname = "DS", .udesc = "Segment rename stalls - DS", .ucode = 0x200, }, { .uname = "FS", .udesc = "Segment rename stalls - FS", .ucode = 0x400, }, { .uname = "GS", .udesc = "Segment rename stalls - GS", .ucode = 0x800, }, { .uname = "ANY", .udesc = "Any (ES/DS/FS/GS) segment rename stall", .ucode = 0xf00, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t core_seg_reg_renames[]={ { .uname = "ES", .udesc = "Segment renames - ES", .ucode = 0x100, }, { .uname = "DS", .udesc = "Segment renames - DS", .ucode = 0x200, }, { .uname = "FS", .udesc = "Segment renames - FS", .ucode = 0x400, }, { .uname = "GS", .udesc = "Segment renames - GS", .ucode = 0x800, }, { .uname = "ANY", .udesc = "Any (ES/DS/FS/GS) segment rename", .ucode = 0xf00, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t core_resource_stalls[]={ { .uname = "ROB_FULL", .udesc = "Cycles during which the ROB is full", .ucode = 0x100, }, { .uname = "RS_FULL", .udesc = "Cycles during which the RS is full", .ucode = 0x200, }, { .uname = "LD_ST", .udesc = "Cycles during which the pipeline has exceeded load or store limit or waiting to commit all stores", .ucode = 0x400, }, { .uname = "FPCW", .udesc = "Cycles stalled due to FPU control word write", .ucode = 0x800, }, { .uname = "BR_MISS_CLEAR", .udesc = "Cycles stalled due to branch misprediction", .ucode = 0x1000, }, { .uname = "ANY", .udesc = "Resource related stalls", .ucode = 0x1f00, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_entry_t intel_core_pe[]={ { .name = "UNHALTED_CORE_CYCLES", .desc = "Count core clock cycles whenever the clock signal on the specific core is running (not halted)", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x200000003ull, .code = 0x3c, }, { .name = "INSTRUCTION_RETIRED", .desc = "Count the number of instructions at retirement", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x100000003ull, .code = 0xc0, }, { .name = "INSTRUCTIONS_RETIRED", .desc = "This is an alias from INSTRUCTION_RETIRED", .modmsk = INTEL_X86_ATTRS, .equiv = "INSTRUCTION_RETIRED", .cntmsk = 0x100000003ull, .code = 0xc0, }, { .name = "UNHALTED_REFERENCE_CYCLES", .desc = "Unhalted reference cycles", .modmsk = INTEL_FIXED2_ATTRS, .cntmsk = 0x400000000ull, .code = 0x0300, /* pseudo encoding */ .flags = INTEL_X86_FIXED, }, { .name = "LLC_REFERENCES", .desc = "Count each request originating equiv the core to reference a cache line in the last level cache. The count may include speculation, but excludes cache line fills due to hardware prefetch. Alias to L2_RQSTS:SELF_DEMAND_MESI", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x4f2e, }, { .name = "LAST_LEVEL_CACHE_REFERENCES", .desc = "This is an alias for LLC_REFERENCES", .modmsk = INTEL_X86_ATTRS, .equiv = "LLC_REFERENCES", .cntmsk = 0x3, .code = 0x4f2e, }, { .name = "LLC_MISSES", .desc = "Count each cache miss condition for references to the last level cache. The event count may include speculation, but excludes cache line fills due to hardware prefetch. Alias to event L2_RQSTS:SELF_DEMAND_I_STATE", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x412e, }, { .name = "LAST_LEVEL_CACHE_MISSES", .desc = "This is an alias for LLC_MISSES", .modmsk = INTEL_X86_ATTRS, .equiv = "LLC_MISSES", .cntmsk = 0x3, .code = 0x412e, }, { .name = "BRANCH_INSTRUCTIONS_RETIRED", .desc = "Count branch instructions at retirement. Specifically, this event counts the retirement of the last micro-op of a branch instruction.", .modmsk = INTEL_X86_ATTRS, .equiv = "BR_INST_RETIRED:ANY", .cntmsk = 0x3, .code = 0xc4, }, { .name = "MISPREDICTED_BRANCH_RETIRED", .desc = "Count mispredicted branch instructions at retirement. Specifically, this event counts at retirement of the last micro-op of a branch instruction in the architectural path of the execution and experienced misprediction in the branch prediction hardware.", .modmsk = INTEL_X86_ATTRS, .equiv = "BR_INST_RETIRED_MISPRED", .cntmsk = 0x3, .code = 0xc5, .flags= INTEL_X86_PEBS, }, { .name = "RS_UOPS_DISPATCHED_CYCLES", .desc = "Cycles micro-ops dispatched for execution", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x1, .code = 0xa1, .numasks = LIBPFM_ARRAY_SIZE(core_rs_uops_dispatched_cycles), .ngrp = 1, .umasks = core_rs_uops_dispatched_cycles, }, { .name = "RS_UOPS_DISPATCHED", .desc = "Number of micro-ops dispatched for execution", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xa0, }, { .name = "RS_UOPS_DISPATCHED_NONE", .desc = "Number of of cycles in which no micro-ops is dispatched for execution", .modmsk =0x0, .equiv = "RS_UOPS_DISPATCHED:i=1:c=1", .cntmsk = 0x3, .code = 0xa0 | INTEL_X86_MOD_INV | (0x1 << INTEL_X86_CMASK_BIT), }, { .name = "LOAD_BLOCK", .desc = "Loads blocked", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x3, .numasks = LIBPFM_ARRAY_SIZE(core_load_block), .ngrp = 1, .umasks = core_load_block, }, { .name = "SB_DRAIN_CYCLES", .desc = "Cycles while stores are blocked due to store buffer drain", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x104, }, { .name = "STORE_BLOCK", .desc = "Cycles while store is waiting", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x4, .numasks = LIBPFM_ARRAY_SIZE(core_store_block), .ngrp = 1, .umasks = core_store_block, }, { .name = "SEGMENT_REG_LOADS", .desc = "Number of segment register loads", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x6, }, { .name = "SSE_PRE_EXEC", .desc = "Streaming SIMD Extensions (SSE) Prefetch instructions executed", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x7, .numasks = LIBPFM_ARRAY_SIZE(core_sse_pre_exec), .ngrp = 1, .umasks = core_sse_pre_exec, }, { .name = "DTLB_MISSES", .desc = "Memory accesses that missed the DTLB", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x8, .numasks = LIBPFM_ARRAY_SIZE(core_dtlb_misses), .ngrp = 1, .umasks = core_dtlb_misses, }, { .name = "MEMORY_DISAMBIGUATION", .desc = "Memory disambiguation", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x9, .numasks = LIBPFM_ARRAY_SIZE(core_memory_disambiguation), .ngrp = 1, .umasks = core_memory_disambiguation, }, { .name = "PAGE_WALKS", .desc = "Number of page-walks executed", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xc, .numasks = LIBPFM_ARRAY_SIZE(core_page_walks), .ngrp = 1, .umasks = core_page_walks, }, { .name = "FP_COMP_OPS_EXE", .desc = "Floating point computational micro-ops executed", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x1, .code = 0x10, }, { .name = "FP_ASSIST", .desc = "Floating point assists", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x2, .code = 0x11, }, { .name = "MUL", .desc = "Multiply operations executed", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x2, .code = 0x12, }, { .name = "DIV", .desc = "Divide operations executed", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x2, .code = 0x13, }, { .name = "CYCLES_DIV_BUSY", .desc = "Cycles the divider is busy", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x1, .code = 0x14, }, { .name = "IDLE_DURING_DIV", .desc = "Cycles the divider is busy and all other execution units are idle", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x1, .code = 0x18, }, { .name = "DELAYED_BYPASS", .desc = "Delayed bypass", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x2, .code = 0x19, .numasks = LIBPFM_ARRAY_SIZE(core_delayed_bypass), .ngrp = 1, .umasks = core_delayed_bypass, }, { .name = "L2_ADS", .desc = "Cycles L2 address bus is in use", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x21, .numasks = LIBPFM_ARRAY_SIZE(core_l2_ads), .ngrp = 1, .umasks = core_l2_ads, }, { .name = "L2_DBUS_BUSY_RD", .desc = "Cycles the L2 transfers data to the core", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x23, .numasks = LIBPFM_ARRAY_SIZE(core_l2_ads), .ngrp = 1, .umasks = core_l2_ads, /* identical to actual umasks list for this event */ }, { .name = "L2_LINES_IN", .desc = "L2 cache misses", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x24, .numasks = LIBPFM_ARRAY_SIZE(core_l2_lines_in), .ngrp = 2, .umasks = core_l2_lines_in, }, { .name = "L2_M_LINES_IN", .desc = "L2 cache line modifications", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x25, .numasks = LIBPFM_ARRAY_SIZE(core_l2_ads), .ngrp = 1, .umasks = core_l2_ads, /* identical to actual umasks list for this event */ }, { .name = "L2_LINES_OUT", .desc = "L2 cache lines evicted", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x26, .numasks = LIBPFM_ARRAY_SIZE(core_l2_lines_in), .ngrp = 2, .umasks = core_l2_lines_in, /* identical to actual umasks list for this event */ }, { .name = "L2_M_LINES_OUT", .desc = "Modified lines evicted from the L2 cache", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x27, .numasks = LIBPFM_ARRAY_SIZE(core_l2_lines_in), .ngrp = 2, .umasks = core_l2_lines_in, /* identical to actual umasks list for this event */ }, { .name = "L2_IFETCH", .desc = "L2 cacheable instruction fetch requests", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x28, .numasks = LIBPFM_ARRAY_SIZE(core_l2_ifetch), .ngrp = 2, .umasks = core_l2_ifetch, }, { .name = "L2_LD", .desc = "L2 cache reads", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x29, .numasks = LIBPFM_ARRAY_SIZE(core_l2_ld), .ngrp = 3, .umasks = core_l2_ld, }, { .name = "L2_ST", .desc = "L2 store requests", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x2a, .numasks = LIBPFM_ARRAY_SIZE(core_l2_ifetch), .ngrp = 2, .umasks = core_l2_ifetch, /* identical to actual umasks list for this event */ }, { .name = "L2_LOCK", .desc = "L2 locked accesses", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x2b, .numasks = LIBPFM_ARRAY_SIZE(core_l2_ifetch), .ngrp = 2, .umasks = core_l2_ifetch, /* identical to actual umasks list for this event */ }, { .name = "L2_RQSTS", .desc = "L2 cache requests", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x2e, .numasks = LIBPFM_ARRAY_SIZE(core_l2_ld), .ngrp = 3, .umasks = core_l2_ld, /* identical to actual umasks list for this event */ }, { .name = "L2_REJECT_BUSQ", .desc = "Rejected L2 cache requests", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x30, .numasks = LIBPFM_ARRAY_SIZE(core_l2_ld), .ngrp = 3, .umasks = core_l2_ld, /* identical to actual umasks list for this event */ }, { .name = "L2_NO_REQ", .desc = "Cycles no L2 cache requests are pending", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x32, .numasks = LIBPFM_ARRAY_SIZE(core_l2_ads), .ngrp = 1, .umasks = core_l2_ads, /* identical to actual umasks list for this event */ }, { .name = "EIST_TRANS", .desc = "Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x3a, }, { .name = "THERMAL_TRIP", .desc = "Number of thermal trips", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xc03b, }, { .name = "CPU_CLK_UNHALTED", .desc = "Core cycles when core is not halted", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x3c, .numasks = LIBPFM_ARRAY_SIZE(core_cpu_clk_unhalted), .ngrp = 1, .umasks = core_cpu_clk_unhalted, }, { .name = "L1D_CACHE_LD", .desc = "L1 cacheable data reads", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x40, .numasks = LIBPFM_ARRAY_SIZE(core_l1d_cache_ld), .ngrp = 1, .umasks = core_l1d_cache_ld, }, { .name = "L1D_CACHE_ST", .desc = "L1 cacheable data writes", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x41, .numasks = LIBPFM_ARRAY_SIZE(core_l1d_cache_ld), .ngrp = 1, .umasks = core_l1d_cache_ld, /* identical to actual umasks list for this event */ }, { .name = "L1D_CACHE_LOCK", .desc = "L1 data cacheable locked reads", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x42, .numasks = LIBPFM_ARRAY_SIZE(core_l1d_cache_ld), .ngrp = 1, .umasks = core_l1d_cache_ld, /* identical to actual umasks list for this event */ }, { .name = "L1D_ALL_REF", .desc = "All references to the L1 data cache", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x143, }, { .name = "L1D_ALL_CACHE_REF", .desc = "L1 Data cacheable reads and writes", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x243, }, { .name = "L1D_REPL", .desc = "Cache lines allocated in the L1 data cache", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xf45, }, { .name = "L1D_M_REPL", .desc = "Modified cache lines allocated in the L1 data cache", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x46, }, { .name = "L1D_M_EVICT", .desc = "Modified cache lines evicted from the L1 data cache", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x47, }, { .name = "L1D_PEND_MISS", .desc = "Total number of outstanding L1 data cache misses at any cycle", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x48, }, { .name = "L1D_SPLIT", .desc = "Cache line split from L1 data cache", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x49, .numasks = LIBPFM_ARRAY_SIZE(core_l1d_split), .ngrp = 1, .umasks = core_l1d_split, }, { .name = "SSE_PRE_MISS", .desc = "Streaming SIMD Extensions (SSE) instructions missing all cache levels", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x4b, .numasks = LIBPFM_ARRAY_SIZE(core_sse_pre_miss), .ngrp = 1, .umasks = core_sse_pre_miss, }, { .name = "LOAD_HIT_PRE", .desc = "Load operations conflicting with a software prefetch to the same address", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x4c, }, { .name = "L1D_PREFETCH", .desc = "L1 data cache prefetch", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x4e, .numasks = LIBPFM_ARRAY_SIZE(core_l1d_prefetch), .ngrp = 1, .umasks = core_l1d_prefetch, }, { .name = "BUS_REQUEST_OUTSTANDING", .desc = "Number of pending full cache line read transactions on the bus occurring in each cycle", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x60, .numasks = LIBPFM_ARRAY_SIZE(core_bus_request_outstanding), .ngrp = 2, .umasks = core_bus_request_outstanding, }, { .name = "BUS_BNR_DRV", .desc = "Number of Bus Not Ready signals asserted", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x61, .numasks = LIBPFM_ARRAY_SIZE(core_bus_bnr_drv), .ngrp = 1, .umasks = core_bus_bnr_drv, }, { .name = "BUS_DRDY_CLOCKS", .desc = "Bus cycles when data is sent on the bus", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x62, .numasks = LIBPFM_ARRAY_SIZE(core_bus_bnr_drv), .ngrp = 1, .umasks = core_bus_bnr_drv, /* identical to actual umasks list for this event */ }, { .name = "BUS_LOCK_CLOCKS", .desc = "Bus cycles when a LOCK signal is asserted", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x63, .numasks = LIBPFM_ARRAY_SIZE(core_bus_request_outstanding), .ngrp = 2, .umasks = core_bus_request_outstanding, /* identical to actual umasks list for this event */ }, { .name = "BUS_DATA_RCV", .desc = "Bus cycles while processor receives data", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x64, .numasks = LIBPFM_ARRAY_SIZE(core_l2_ads), .ngrp = 1, .umasks = core_l2_ads, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRANS_BRD", .desc = "Burst read bus transactions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x65, .numasks = LIBPFM_ARRAY_SIZE(core_bus_request_outstanding), .ngrp = 2, .umasks = core_bus_request_outstanding, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRANS_RFO", .desc = "RFO bus transactions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x66, .numasks = LIBPFM_ARRAY_SIZE(core_bus_request_outstanding), .ngrp = 2, .umasks = core_bus_request_outstanding, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRANS_WB", .desc = "Explicit writeback bus transactions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x67, .numasks = LIBPFM_ARRAY_SIZE(core_bus_request_outstanding), .ngrp = 2, .umasks = core_bus_request_outstanding, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRANS_IFETCH", .desc = "Instruction-fetch bus transactions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x68, .numasks = LIBPFM_ARRAY_SIZE(core_bus_request_outstanding), .ngrp = 2, .umasks = core_bus_request_outstanding, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRANS_INVAL", .desc = "Invalidate bus transactions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x69, .numasks = LIBPFM_ARRAY_SIZE(core_bus_request_outstanding), .ngrp = 2, .umasks = core_bus_request_outstanding, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRANS_PWR", .desc = "Partial write bus transaction", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x6a, .numasks = LIBPFM_ARRAY_SIZE(core_bus_request_outstanding), .ngrp = 2, .umasks = core_bus_request_outstanding, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRANS_P", .desc = "Partial bus transactions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x6b, .numasks = LIBPFM_ARRAY_SIZE(core_bus_request_outstanding), .ngrp = 2, .umasks = core_bus_request_outstanding, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRANS_IO", .desc = "IO bus transactions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x6c, .numasks = LIBPFM_ARRAY_SIZE(core_bus_request_outstanding), .ngrp = 2, .umasks = core_bus_request_outstanding, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRANS_DEF", .desc = "Deferred bus transactions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x6d, .numasks = LIBPFM_ARRAY_SIZE(core_bus_request_outstanding), .ngrp = 2, .umasks = core_bus_request_outstanding, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRANS_BURST", .desc = "Burst (full cache-line) bus transactions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x6e, .numasks = LIBPFM_ARRAY_SIZE(core_bus_request_outstanding), .ngrp = 2, .umasks = core_bus_request_outstanding, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRANS_MEM", .desc = "Memory bus transactions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x6f, .numasks = LIBPFM_ARRAY_SIZE(core_bus_request_outstanding), .ngrp = 2, .umasks = core_bus_request_outstanding, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRANS_ANY", .desc = "All bus transactions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x70, .numasks = LIBPFM_ARRAY_SIZE(core_bus_request_outstanding), .ngrp = 2, .umasks = core_bus_request_outstanding, /* identical to actual umasks list for this event */ }, { .name = "EXT_SNOOP", .desc = "External snoops responses", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x77, .numasks = LIBPFM_ARRAY_SIZE(core_ext_snoop), .ngrp = 2, .umasks = core_ext_snoop, }, { .name = "CMP_SNOOP", .desc = "L1 data cache is snooped by other core", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x78, .numasks = LIBPFM_ARRAY_SIZE(core_cmp_snoop), .ngrp = 2, .umasks = core_cmp_snoop, }, { .name = "BUS_HIT_DRV", .desc = "HIT signal asserted", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x7a, .numasks = LIBPFM_ARRAY_SIZE(core_bus_bnr_drv), .ngrp = 1, .umasks = core_bus_bnr_drv, /* identical to actual umasks list for this event */ }, { .name = "BUS_HITM_DRV", .desc = "HITM signal asserted", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x7b, .numasks = LIBPFM_ARRAY_SIZE(core_bus_bnr_drv), .ngrp = 1, .umasks = core_bus_bnr_drv, /* identical to actual umasks list for this event */ }, { .name = "BUSQ_EMPTY", .desc = "Bus queue is empty", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x7d, .numasks = LIBPFM_ARRAY_SIZE(core_bus_bnr_drv), .ngrp = 1, .umasks = core_bus_bnr_drv, /* identical to actual umasks list for this event */ }, { .name = "SNOOP_STALL_DRV", .desc = "Bus stalled for snoops", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x7e, .numasks = LIBPFM_ARRAY_SIZE(core_bus_request_outstanding), .ngrp = 2, .umasks = core_bus_request_outstanding, /* identical to actual umasks list for this event */ }, { .name = "BUS_IO_WAIT", .desc = "IO requests waiting in the bus queue", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x7f, .numasks = LIBPFM_ARRAY_SIZE(core_l2_ads), .ngrp = 1, .umasks = core_l2_ads, /* identical to actual umasks list for this event */ }, { .name = "L1I_READS", .desc = "Instruction fetches", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x80, }, { .name = "L1I_MISSES", .desc = "Instruction Fetch Unit misses", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x81, }, { .name = "ITLB", .desc = "ITLB small page misses", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x82, .numasks = LIBPFM_ARRAY_SIZE(core_itlb), .ngrp = 1, .umasks = core_itlb, }, { .name = "INST_QUEUE", .desc = "Cycles during which the instruction queue is full", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x83, .numasks = LIBPFM_ARRAY_SIZE(core_inst_queue), .ngrp = 1, .umasks = core_inst_queue, }, { .name = "CYCLES_L1I_MEM_STALLED", .desc = "Cycles during which instruction fetches are stalled", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x86, }, { .name = "ILD_STALL", .desc = "Instruction Length Decoder stall cycles due to a length changing prefix", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x87, }, { .name = "BR_INST_EXEC", .desc = "Branch instructions executed", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x88, }, { .name = "BR_MISSP_EXEC", .desc = "Mispredicted branch instructions executed", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x89, }, { .name = "BR_BAC_MISSP_EXEC", .desc = "Branch instructions mispredicted at decoding", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x8a, }, { .name = "BR_CND_EXEC", .desc = "Conditional branch instructions executed", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x8b, }, { .name = "BR_CND_MISSP_EXEC", .desc = "Mispredicted conditional branch instructions executed", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x8c, }, { .name = "BR_IND_EXEC", .desc = "Indirect branch instructions executed", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x8d, }, { .name = "BR_IND_MISSP_EXEC", .desc = "Mispredicted indirect branch instructions executed", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x8e, }, { .name = "BR_RET_EXEC", .desc = "RET instructions executed", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x8f, }, { .name = "BR_RET_MISSP_EXEC", .desc = "Mispredicted RET instructions executed", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x90, }, { .name = "BR_RET_BAC_MISSP_EXEC", .desc = "RET instructions executed mispredicted at decoding", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x91, }, { .name = "BR_CALL_EXEC", .desc = "CALL instructions executed", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x92, }, { .name = "BR_CALL_MISSP_EXEC", .desc = "Mispredicted CALL instructions executed", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x93, }, { .name = "BR_IND_CALL_EXEC", .desc = "Indirect CALL instructions executed", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x94, }, { .name = "BR_TKN_BUBBLE_1", .desc = "Branch predicted taken with bubble I", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x97, }, { .name = "BR_TKN_BUBBLE_2", .desc = "Branch predicted taken with bubble II", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x98, }, { .name = "MACRO_INSTS", .desc = "Instructions decoded", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xaa, .numasks = LIBPFM_ARRAY_SIZE(core_macro_insts), .ngrp = 1, .umasks = core_macro_insts, }, { .name = "ESP", .desc = "ESP register content synchronization", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xab, .numasks = LIBPFM_ARRAY_SIZE(core_esp), .ngrp = 1, .umasks = core_esp, }, { .name = "SIMD_UOPS_EXEC", .desc = "SIMD micro-ops executed (excluding stores)", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xb0, }, { .name = "SIMD_SAT_UOP_EXEC", .desc = "SIMD saturated arithmetic micro-ops executed", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xb1, }, { .name = "SIMD_UOP_TYPE_EXEC", .desc = "SIMD packed multiply micro-ops executed", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xb3, .numasks = LIBPFM_ARRAY_SIZE(core_simd_uop_type_exec), .ngrp = 1, .umasks = core_simd_uop_type_exec, }, { .name = "INST_RETIRED", .desc = "Instructions retired", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xc0, .flags= INTEL_X86_PEBS, .numasks = LIBPFM_ARRAY_SIZE(core_inst_retired), .ngrp = 1, .umasks = core_inst_retired, }, { .name = "X87_OPS_RETIRED", .desc = "FXCH instructions retired", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xc1, .flags= INTEL_X86_PEBS, .numasks = LIBPFM_ARRAY_SIZE(core_x87_ops_retired), .ngrp = 1, .umasks = core_x87_ops_retired, }, { .name = "UOPS_RETIRED", .desc = "Fused load+op or load+indirect branch retired", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xc2, .numasks = LIBPFM_ARRAY_SIZE(core_uops_retired), .ngrp = 1, .umasks = core_uops_retired, }, { .name = "MACHINE_NUKES", .desc = "Self-Modifying Code detected", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xc3, .numasks = LIBPFM_ARRAY_SIZE(core_machine_nukes), .ngrp = 1, .umasks = core_machine_nukes, }, { .name = "BR_INST_RETIRED", .desc = "Retired branch instructions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xc4, .numasks = LIBPFM_ARRAY_SIZE(core_br_inst_retired), .ngrp = 1, .umasks = core_br_inst_retired, }, { .name = "BR_INST_RETIRED_MISPRED", .desc = "Retired mispredicted branch instructions (Precise_Event)", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xc5, .flags= INTEL_X86_PEBS, }, { .name = "CYCLES_INT_MASKED", .desc = "Cycles during which interrupts are disabled", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x1c6, }, { .name = "CYCLES_INT_PENDING_AND_MASKED", .desc = "Cycles during which interrupts are pending and disabled", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x2c6, }, { .name = "SIMD_INST_RETIRED", .desc = "Retired Streaming SIMD Extensions (SSE) packed-single instructions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xc7, .flags= INTEL_X86_PEBS, .numasks = LIBPFM_ARRAY_SIZE(core_simd_inst_retired), .ngrp = 1, .umasks = core_simd_inst_retired, }, { .name = "HW_INT_RCV", .desc = "Hardware interrupts received", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xc8, }, { .name = "ITLB_MISS_RETIRED", .desc = "Retired instructions that missed the ITLB", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xc9, }, { .name = "SIMD_COMP_INST_RETIRED", .desc = "Retired computational Streaming SIMD Extensions (SSE) packed-single instructions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xca, .numasks = LIBPFM_ARRAY_SIZE(core_simd_comp_inst_retired), .ngrp = 1, .umasks = core_simd_comp_inst_retired, }, { .name = "MEM_LOAD_RETIRED", .desc = "Retired loads that miss the L1 data cache", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x1, .code = 0xcb, .flags= INTEL_X86_PEBS, .numasks = LIBPFM_ARRAY_SIZE(core_mem_load_retired), .ngrp = 1, .umasks = core_mem_load_retired, }, { .name = "FP_MMX_TRANS", .desc = "Transitions from MMX (TM) Instructions to Floating Point Instructions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xcc, .numasks = LIBPFM_ARRAY_SIZE(core_fp_mmx_trans), .ngrp = 1, .umasks = core_fp_mmx_trans, }, { .name = "SIMD_ASSIST", .desc = "SIMD assists invoked", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xcd, }, { .name = "SIMD_INSTR_RETIRED", .desc = "SIMD Instructions retired", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xce, }, { .name = "SIMD_SAT_INSTR_RETIRED", .desc = "Saturated arithmetic instructions retired", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xcf, }, { .name = "RAT_STALLS", .desc = "ROB read port stalls cycles", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xd2, .numasks = LIBPFM_ARRAY_SIZE(core_rat_stalls), .ngrp = 1, .umasks = core_rat_stalls, }, { .name = "SEG_RENAME_STALLS", .desc = "Segment rename stalls - ES ", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xd4, .numasks = LIBPFM_ARRAY_SIZE(core_seg_rename_stalls), .ngrp = 1, .umasks = core_seg_rename_stalls, }, { .name = "SEG_REG_RENAMES", .desc = "Segment renames - ES", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xd5, .numasks = LIBPFM_ARRAY_SIZE(core_seg_reg_renames), .ngrp = 1, .umasks = core_seg_reg_renames, }, { .name = "RESOURCE_STALLS", .desc = "Cycles during which the ROB is full", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xdc, .numasks = LIBPFM_ARRAY_SIZE(core_resource_stalls), .ngrp = 1, .umasks = core_resource_stalls, }, { .name = "BR_INST_DECODED", .desc = "Branch instructions decoded", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xe0, }, { .name = "BOGUS_BR", .desc = "Bogus branches", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xe4, }, { .name = "BACLEARS", .desc = "BACLEARS asserted", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xe6, }, { .name = "PREF_RQSTS_UP", .desc = "Upward prefetches issued from the DPL", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xf0, }, { .name = "PREF_RQSTS_DN", .desc = "Downward prefetches issued from the DPL", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xf8, }, }; libpfm-4.9.0/lib/events/sparc_niagara2_events.h0000664000175000017500000001473613223402656021314 0ustar eranianeranianstatic const sparc_entry_t niagara2_pe[] = { /* PIC0 Niagara-2 events */ { .name = "All_strands_idle", .desc = "Cycles when no strand can be picked for the physical core on which the monitoring strand resides.", .ctrl = PME_CTRL_S0 | PME_CTRL_S1, .code = 0x0, }, { .name = "Instr_cnt", .desc = "Number of instructions completed", .ctrl = PME_CTRL_S0 | PME_CTRL_S1, .code = 0x2, .umasks = { { .uname = "branches", .udesc = "Completed branches", .ubit = 0, }, { .uname = "taken_branches", .udesc = "Taken branches, which are always mispredicted", .ubit = 1, }, { .uname = "FGU_arith", .udesc = "All FADD, FSUB, FCMP, convert, FMUL, FDIV, FNEG, FABS, FSQRT, FMOV, FPADD, FPSUB, FPACK, FEXPAND, FPMERGE, FMUL8, FMULD8, FALIGNDATA, BSHUFFLE, FZERO, FONE, FSRC, FNOT1, FNOT2, FOR, FNOR, FAND, FNAND, FXOR, FXNOR, FORNOT1, FORNOT2, FANDNOT1, FANDNOT2, PDIST, SIAM", .ubit = 2, }, { .uname = "Loads", .udesc = "Load instructions", .ubit = 3, }, { .uname = "Stores", .udesc = "Stores instructions", .ubit = 3, }, { .uname = "SW_count", .udesc = "Software count 'sethi %hi(fc00), %g0' instructions", .ubit = 5, }, { .uname = "other", .udesc = "Instructions not covered by other mask bits", .ubit = 6, }, { .uname = "atomics", .udesc = "Atomics are LDSTUB/A, CASA/XA, SWAP/A", .ubit = 7, }, }, .numasks = 8, }, { .name = "cache", .desc = "Cache events", .ctrl = PME_CTRL_S0 | PME_CTRL_S1, .code = 0x3, .umasks = { { .uname = "IC_miss", .udesc = "I-cache misses. This counts only primary instruction cache misses, and does not count duplicate instruction cache misses.4 Also, only 'true' misses are counted. If a thread encounters an I$ miss, but the thread is redirected (due to a branch misprediction or trap, for example) before the line returns from L2 and is loaded into the I$, then the miss is not counted.", .ubit = 0, }, { .uname = "DC_miss", .udesc = "D-cache misses. This counts both primary and duplicate data cache misses.", .ubit = 1, }, { .uname = "L2IC_miss", .udesc = "L2 cache instruction misses", .ubit = 4, }, { .uname = "L2LD_miss", .udesc = "L2 cache load misses. Block loads are treated as one L2 miss event. In reality, each individual load can hit or miss in the L2 since the block load is not atomic.", .ubit = 5, }, }, .numasks = 4, }, { .name = "TLB", .desc = "TLB events", .ctrl = PME_CTRL_S0 | PME_CTRL_S1, .code = 0x4, .umasks = { { .uname = "ITLB_L2ref", .udesc = "ITLB references to L2. For each ITLB miss with hardware tablewalk enabled, count each access the ITLB hardware tablewalk makes to L2.", .ubit = 2, }, { .uname = "DTLB_L2ref", .udesc = "DTLB references to L2. For each DTLB miss with hardware tablewalk enabled, count each access the DTLB hardware tablewalk makes to L2.", .ubit = 3, }, { .uname = "ITLB_L2miss", .udesc = "For each ITLB miss with hardware tablewalk enabled, count each access the ITLB hardware tablewalk makes to L2 which misses in L2. Note: Depending upon the hardware table walk configuration, each ITLB miss may issue from 1 to 4 requests to L2 to search TSBs.", .ubit = 4, }, { .uname = "DTLB_L2miss", .udesc = "For each DTLB miss with hardware tablewalk enabled, count each access the DTLB hardware tablewalk makes to L2 which misses in L2. Note: Depending upon the hardware table walk configuration, each DTLB miss may issue from 1 to 4 requests to L2 to search TSBs.", .ubit = 5, }, }, .numasks = 4, }, { .name = "mem", .desc = "Memory operations", .ctrl = PME_CTRL_S0 | PME_CTRL_S1, .code = 0x5, .umasks = { { .uname = "stream_load", .udesc = "Stream Unit load operations to L2", .ubit = 0, }, { .uname = "stream_store", .udesc = "Stream Unit store operations to L2", .ubit = 1, }, { .uname = "cpu_load", .udesc = "CPU loads to L2", .ubit = 2, }, { .uname = "cpu_ifetch", .udesc = "CPU instruction fetches to L2", .ubit = 3, }, { .uname = "cpu_store", .udesc = "CPU stores to L2", .ubit = 6, }, { .uname = "mmu_load", .udesc = "MMU loads to L2", .ubit = 7, }, }, .numasks = 6, }, { .name = "spu_ops", .desc = "Stream Unit operations. User, supervisor, and hypervisor counting must all be enabled to properly count these events.", .ctrl = PME_CTRL_S0 | PME_CTRL_S1, .code = 0x6, .umasks = { { .uname = "DES", .udesc = "Increment for each CWQ or ASI operation that uses DES/3DES unit", .ubit = 0, }, { .uname = "AES", .udesc = "Increment for each CWQ or ASI operation that uses AES unit", .ubit = 1, }, { .uname = "RC4", .udesc = "Increment for each CWQ or ASI operation that uses RC4 unit", .ubit = 2, }, { .uname = "HASH", .udesc = "Increment for each CWQ or ASI operation that uses MD5/SHA-1/SHA-256 unit", .ubit = 3, }, { .uname = "MA", .udesc = "Increment for each CWQ or ASI modular arithmetic operation", .ubit = 4, }, { .uname = "CSUM", .udesc = "Increment for each iSCSI CRC or TCP/IP checksum operation", .ubit = 5, }, }, .numasks = 6, }, { .name = "spu_busy", .desc = "Stream Unit busy cycles. User, supervisor, and hypervisor counting must all be enabled to properly count these events.", .ctrl = PME_CTRL_S0 | PME_CTRL_S1, .code = 0x07, .umasks = { { .uname = "DES", .udesc = "Cycles the DES/3DES unit is busy", .ubit = 0, }, { .uname = "AES", .udesc = "Cycles the AES unit is busy", .ubit = 1, }, { .uname = "RC4", .udesc = "Cycles the RC4 unit is busy", .ubit = 2, }, { .uname = "HASH", .udesc = "Cycles the MD5/SHA-1/SHA-256 unit is busy", .ubit = 3, }, { .uname = "MA", .udesc = "Cycles the modular arithmetic unit is busy", .ubit = 4, }, { .uname = "CSUM", .udesc = "Cycles the CRC/MPA/checksum unit is busy", .ubit = 5, }, }, .numasks = 6, }, { .name = "tlb_miss", .desc = "TLB misses", .ctrl = PME_CTRL_S0 | PME_CTRL_S1, .code = 0xb, .umasks = { { .uname = "ITLB", .udesc = "I-TLB misses", .ubit = 2, }, { .uname = "DTLB", .udesc = "D-TLB misses", .ubit = 3, }, }, .numasks = 2, }, }; #define PME_SPARC_NIAGARA2_EVENT_COUNT (sizeof(niagara2_pe)/sizeof(sparc_entry_t)) libpfm-4.9.0/lib/events/ppc970_events.h0000664000175000017500000020032313223402656017447 0ustar eranianeranian/****************************/ /* THIS IS OPEN SOURCE CODE */ /****************************/ #ifndef __PPC970_EVENTS_H__ #define __PPC970_EVENTS_H__ /* * File: ppc970_events.h * CVS: * Author: Corey Ashford * cjashfor@us.ibm.com * Mods: * * * (C) Copyright IBM Corporation, 2009. All Rights Reserved. * Contributed by Corey Ashford * * Note: This code was automatically generated and should not be modified by * hand. * */ #define PPC970_PME_PM_LSU_REJECT_RELOAD_CDF 0 #define PPC970_PME_PM_MRK_LSU_SRQ_INST_VALID 1 #define PPC970_PME_PM_FPU1_SINGLE 2 #define PPC970_PME_PM_FPU0_STALL3 3 #define PPC970_PME_PM_TB_BIT_TRANS 4 #define PPC970_PME_PM_GPR_MAP_FULL_CYC 5 #define PPC970_PME_PM_MRK_ST_CMPL 6 #define PPC970_PME_PM_FPU0_STF 7 #define PPC970_PME_PM_FPU1_FMA 8 #define PPC970_PME_PM_LSU1_FLUSH_ULD 9 #define PPC970_PME_PM_MRK_INST_FIN 10 #define PPC970_PME_PM_MRK_LSU0_FLUSH_UST 11 #define PPC970_PME_PM_LSU_LRQ_S0_ALLOC 12 #define PPC970_PME_PM_FPU_FDIV 13 #define PPC970_PME_PM_FPU0_FULL_CYC 14 #define PPC970_PME_PM_FPU_SINGLE 15 #define PPC970_PME_PM_FPU0_FMA 16 #define PPC970_PME_PM_MRK_LSU1_FLUSH_ULD 17 #define PPC970_PME_PM_LSU1_FLUSH_LRQ 18 #define PPC970_PME_PM_DTLB_MISS 19 #define PPC970_PME_PM_MRK_ST_MISS_L1 20 #define PPC970_PME_PM_EXT_INT 21 #define PPC970_PME_PM_MRK_LSU1_FLUSH_LRQ 22 #define PPC970_PME_PM_MRK_ST_GPS 23 #define PPC970_PME_PM_GRP_DISP_SUCCESS 24 #define PPC970_PME_PM_LSU1_LDF 25 #define PPC970_PME_PM_LSU0_SRQ_STFWD 26 #define PPC970_PME_PM_CR_MAP_FULL_CYC 27 #define PPC970_PME_PM_MRK_LSU0_FLUSH_ULD 28 #define PPC970_PME_PM_LSU_DERAT_MISS 29 #define PPC970_PME_PM_FPU0_SINGLE 30 #define PPC970_PME_PM_FPU1_FDIV 31 #define PPC970_PME_PM_FPU1_FEST 32 #define PPC970_PME_PM_FPU0_FRSP_FCONV 33 #define PPC970_PME_PM_GCT_EMPTY_SRQ_FULL 34 #define PPC970_PME_PM_MRK_ST_CMPL_INT 35 #define PPC970_PME_PM_FLUSH_BR_MPRED 36 #define PPC970_PME_PM_FXU_FIN 37 #define PPC970_PME_PM_FPU_STF 38 #define PPC970_PME_PM_DSLB_MISS 39 #define PPC970_PME_PM_FXLS1_FULL_CYC 40 #define PPC970_PME_PM_LSU_LMQ_LHR_MERGE 41 #define PPC970_PME_PM_MRK_STCX_FAIL 42 #define PPC970_PME_PM_FXU0_BUSY_FXU1_IDLE 43 #define PPC970_PME_PM_MRK_DATA_FROM_L25_SHR 44 #define PPC970_PME_PM_LSU_FLUSH_ULD 45 #define PPC970_PME_PM_MRK_BRU_FIN 46 #define PPC970_PME_PM_IERAT_XLATE_WR 47 #define PPC970_PME_PM_DATA_FROM_MEM 48 #define PPC970_PME_PM_FPR_MAP_FULL_CYC 49 #define PPC970_PME_PM_FPU1_FULL_CYC 50 #define PPC970_PME_PM_FPU0_FIN 51 #define PPC970_PME_PM_GRP_BR_REDIR 52 #define PPC970_PME_PM_THRESH_TIMEO 53 #define PPC970_PME_PM_FPU_FSQRT 54 #define PPC970_PME_PM_MRK_LSU0_FLUSH_LRQ 55 #define PPC970_PME_PM_PMC1_OVERFLOW 56 #define PPC970_PME_PM_FXLS0_FULL_CYC 57 #define PPC970_PME_PM_FPU0_ALL 58 #define PPC970_PME_PM_DATA_TABLEWALK_CYC 59 #define PPC970_PME_PM_FPU0_FEST 60 #define PPC970_PME_PM_DATA_FROM_L25_MOD 61 #define PPC970_PME_PM_LSU0_REJECT_ERAT_MISS 62 #define PPC970_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC 63 #define PPC970_PME_PM_LSU0_REJECT_RELOAD_CDF 64 #define PPC970_PME_PM_FPU_FEST 65 #define PPC970_PME_PM_0INST_FETCH 66 #define PPC970_PME_PM_LD_MISS_L1_LSU0 67 #define PPC970_PME_PM_LSU1_REJECT_RELOAD_CDF 68 #define PPC970_PME_PM_L1_PREF 69 #define PPC970_PME_PM_FPU1_STALL3 70 #define PPC970_PME_PM_BRQ_FULL_CYC 71 #define PPC970_PME_PM_PMC8_OVERFLOW 72 #define PPC970_PME_PM_PMC7_OVERFLOW 73 #define PPC970_PME_PM_WORK_HELD 74 #define PPC970_PME_PM_MRK_LD_MISS_L1_LSU0 75 #define PPC970_PME_PM_FXU_IDLE 76 #define PPC970_PME_PM_INST_CMPL 77 #define PPC970_PME_PM_LSU1_FLUSH_UST 78 #define PPC970_PME_PM_LSU0_FLUSH_ULD 79 #define PPC970_PME_PM_LSU_FLUSH 80 #define PPC970_PME_PM_INST_FROM_L2 81 #define PPC970_PME_PM_LSU1_REJECT_LMQ_FULL 82 #define PPC970_PME_PM_PMC2_OVERFLOW 83 #define PPC970_PME_PM_FPU0_DENORM 84 #define PPC970_PME_PM_FPU1_FMOV_FEST 85 #define PPC970_PME_PM_GRP_DISP_REJECT 86 #define PPC970_PME_PM_LSU_LDF 87 #define PPC970_PME_PM_INST_DISP 88 #define PPC970_PME_PM_DATA_FROM_L25_SHR 89 #define PPC970_PME_PM_L1_DCACHE_RELOAD_VALID 90 #define PPC970_PME_PM_MRK_GRP_ISSUED 91 #define PPC970_PME_PM_FPU_FMA 92 #define PPC970_PME_PM_MRK_CRU_FIN 93 #define PPC970_PME_PM_MRK_LSU1_FLUSH_UST 94 #define PPC970_PME_PM_MRK_FXU_FIN 95 #define PPC970_PME_PM_LSU1_REJECT_ERAT_MISS 96 #define PPC970_PME_PM_BR_ISSUED 97 #define PPC970_PME_PM_PMC4_OVERFLOW 98 #define PPC970_PME_PM_EE_OFF 99 #define PPC970_PME_PM_INST_FROM_L25_MOD 100 #define PPC970_PME_PM_ITLB_MISS 101 #define PPC970_PME_PM_FXU1_BUSY_FXU0_IDLE 102 #define PPC970_PME_PM_GRP_DISP_VALID 103 #define PPC970_PME_PM_MRK_GRP_DISP 104 #define PPC970_PME_PM_LSU_FLUSH_UST 105 #define PPC970_PME_PM_FXU1_FIN 106 #define PPC970_PME_PM_GRP_CMPL 107 #define PPC970_PME_PM_FPU_FRSP_FCONV 108 #define PPC970_PME_PM_MRK_LSU0_FLUSH_SRQ 109 #define PPC970_PME_PM_LSU_LMQ_FULL_CYC 110 #define PPC970_PME_PM_ST_REF_L1_LSU0 111 #define PPC970_PME_PM_LSU0_DERAT_MISS 112 #define PPC970_PME_PM_LSU_SRQ_SYNC_CYC 113 #define PPC970_PME_PM_FPU_STALL3 114 #define PPC970_PME_PM_LSU_REJECT_ERAT_MISS 115 #define PPC970_PME_PM_MRK_DATA_FROM_L2 116 #define PPC970_PME_PM_LSU0_FLUSH_SRQ 117 #define PPC970_PME_PM_FPU0_FMOV_FEST 118 #define PPC970_PME_PM_LD_REF_L1_LSU0 119 #define PPC970_PME_PM_LSU1_FLUSH_SRQ 120 #define PPC970_PME_PM_GRP_BR_MPRED 121 #define PPC970_PME_PM_LSU_LMQ_S0_ALLOC 122 #define PPC970_PME_PM_LSU0_REJECT_LMQ_FULL 123 #define PPC970_PME_PM_ST_REF_L1 124 #define PPC970_PME_PM_MRK_VMX_FIN 125 #define PPC970_PME_PM_LSU_SRQ_EMPTY_CYC 126 #define PPC970_PME_PM_FPU1_STF 127 #define PPC970_PME_PM_RUN_CYC 128 #define PPC970_PME_PM_LSU_LMQ_S0_VALID 129 #define PPC970_PME_PM_LSU0_LDF 130 #define PPC970_PME_PM_LSU_LRQ_S0_VALID 131 #define PPC970_PME_PM_PMC3_OVERFLOW 132 #define PPC970_PME_PM_MRK_IMR_RELOAD 133 #define PPC970_PME_PM_MRK_GRP_TIMEO 134 #define PPC970_PME_PM_FPU_FMOV_FEST 135 #define PPC970_PME_PM_GRP_DISP_BLK_SB_CYC 136 #define PPC970_PME_PM_XER_MAP_FULL_CYC 137 #define PPC970_PME_PM_ST_MISS_L1 138 #define PPC970_PME_PM_STOP_COMPLETION 139 #define PPC970_PME_PM_MRK_GRP_CMPL 140 #define PPC970_PME_PM_ISLB_MISS 141 #define PPC970_PME_PM_SUSPENDED 142 #define PPC970_PME_PM_CYC 143 #define PPC970_PME_PM_LD_MISS_L1_LSU1 144 #define PPC970_PME_PM_STCX_FAIL 145 #define PPC970_PME_PM_LSU1_SRQ_STFWD 146 #define PPC970_PME_PM_GRP_DISP 147 #define PPC970_PME_PM_L2_PREF 148 #define PPC970_PME_PM_FPU1_DENORM 149 #define PPC970_PME_PM_DATA_FROM_L2 150 #define PPC970_PME_PM_FPU0_FPSCR 151 #define PPC970_PME_PM_MRK_DATA_FROM_L25_MOD 152 #define PPC970_PME_PM_FPU0_FSQRT 153 #define PPC970_PME_PM_LD_REF_L1 154 #define PPC970_PME_PM_MRK_L1_RELOAD_VALID 155 #define PPC970_PME_PM_1PLUS_PPC_CMPL 156 #define PPC970_PME_PM_INST_FROM_L1 157 #define PPC970_PME_PM_EE_OFF_EXT_INT 158 #define PPC970_PME_PM_PMC6_OVERFLOW 159 #define PPC970_PME_PM_LSU_LRQ_FULL_CYC 160 #define PPC970_PME_PM_IC_PREF_INSTALL 161 #define PPC970_PME_PM_DC_PREF_OUT_OF_STREAMS 162 #define PPC970_PME_PM_MRK_LSU1_FLUSH_SRQ 163 #define PPC970_PME_PM_GCT_FULL_CYC 164 #define PPC970_PME_PM_INST_FROM_MEM 165 #define PPC970_PME_PM_FLUSH_LSU_BR_MPRED 166 #define PPC970_PME_PM_FXU_BUSY 167 #define PPC970_PME_PM_ST_REF_L1_LSU1 168 #define PPC970_PME_PM_MRK_LD_MISS_L1 169 #define PPC970_PME_PM_L1_WRITE_CYC 170 #define PPC970_PME_PM_LSU_REJECT_LMQ_FULL 171 #define PPC970_PME_PM_FPU_ALL 172 #define PPC970_PME_PM_LSU_SRQ_S0_ALLOC 173 #define PPC970_PME_PM_INST_FROM_L25_SHR 174 #define PPC970_PME_PM_GRP_MRK 175 #define PPC970_PME_PM_BR_MPRED_CR 176 #define PPC970_PME_PM_DC_PREF_STREAM_ALLOC 177 #define PPC970_PME_PM_FPU1_FIN 178 #define PPC970_PME_PM_LSU_REJECT_SRQ 179 #define PPC970_PME_PM_BR_MPRED_TA 180 #define PPC970_PME_PM_CRQ_FULL_CYC 181 #define PPC970_PME_PM_LD_MISS_L1 182 #define PPC970_PME_PM_INST_FROM_PREF 183 #define PPC970_PME_PM_STCX_PASS 184 #define PPC970_PME_PM_DC_INV_L2 185 #define PPC970_PME_PM_LSU_SRQ_FULL_CYC 186 #define PPC970_PME_PM_LSU0_FLUSH_LRQ 187 #define PPC970_PME_PM_LSU_SRQ_S0_VALID 188 #define PPC970_PME_PM_LARX_LSU0 189 #define PPC970_PME_PM_GCT_EMPTY_CYC 190 #define PPC970_PME_PM_FPU1_ALL 191 #define PPC970_PME_PM_FPU1_FSQRT 192 #define PPC970_PME_PM_FPU_FIN 193 #define PPC970_PME_PM_LSU_SRQ_STFWD 194 #define PPC970_PME_PM_MRK_LD_MISS_L1_LSU1 195 #define PPC970_PME_PM_FXU0_FIN 196 #define PPC970_PME_PM_MRK_FPU_FIN 197 #define PPC970_PME_PM_PMC5_OVERFLOW 198 #define PPC970_PME_PM_SNOOP_TLBIE 199 #define PPC970_PME_PM_FPU1_FRSP_FCONV 200 #define PPC970_PME_PM_FPU0_FDIV 201 #define PPC970_PME_PM_LD_REF_L1_LSU1 202 #define PPC970_PME_PM_HV_CYC 203 #define PPC970_PME_PM_LR_CTR_MAP_FULL_CYC 204 #define PPC970_PME_PM_FPU_DENORM 205 #define PPC970_PME_PM_LSU0_REJECT_SRQ 206 #define PPC970_PME_PM_LSU1_REJECT_SRQ 207 #define PPC970_PME_PM_LSU1_DERAT_MISS 208 #define PPC970_PME_PM_IC_PREF_REQ 209 #define PPC970_PME_PM_MRK_LSU_FIN 210 #define PPC970_PME_PM_MRK_DATA_FROM_MEM 211 #define PPC970_PME_PM_LSU0_FLUSH_UST 212 #define PPC970_PME_PM_LSU_FLUSH_LRQ 213 #define PPC970_PME_PM_LSU_FLUSH_SRQ 214 static const pme_power_entry_t ppc970_pe[] = { [ PPC970_PME_PM_LSU_REJECT_RELOAD_CDF ] = { .pme_name = "PM_LSU_REJECT_RELOAD_CDF", .pme_code = 0x6920, .pme_short_desc = "LSU reject due to reload CDF or tag update collision", .pme_long_desc = "LSU reject due to reload CDF or tag update collision", }, [ PPC970_PME_PM_MRK_LSU_SRQ_INST_VALID ] = { .pme_name = "PM_MRK_LSU_SRQ_INST_VALID", .pme_code = 0x936, .pme_short_desc = "Marked instruction valid in SRQ", .pme_long_desc = "This signal is asserted every cycle when a marked request is resident in the Store Request Queue", }, [ PPC970_PME_PM_FPU1_SINGLE ] = { .pme_name = "PM_FPU1_SINGLE", .pme_code = 0x127, .pme_short_desc = "FPU1 executed single precision instruction", .pme_long_desc = "This signal is active for one cycle when fp1 is executing single precision instruction.", }, [ PPC970_PME_PM_FPU0_STALL3 ] = { .pme_name = "PM_FPU0_STALL3", .pme_code = 0x121, .pme_short_desc = "FPU0 stalled in pipe3", .pme_long_desc = "This signal indicates that fp0 has generated a stall in pipe3 due to overflow, underflow, massive cancel, convert to integer (sometimes), or convert from integer (always). This signal is active during the entire duration of the stall. ", }, [ PPC970_PME_PM_TB_BIT_TRANS ] = { .pme_name = "PM_TB_BIT_TRANS", .pme_code = 0x8005, .pme_short_desc = "Time Base bit transition", .pme_long_desc = "When the selected time base bit (as specified in MMCR0[TBSEL])transitions from 0 to 1 ", }, [ PPC970_PME_PM_GPR_MAP_FULL_CYC ] = { .pme_name = "PM_GPR_MAP_FULL_CYC", .pme_code = 0x335, .pme_short_desc = "Cycles GPR mapper full", .pme_long_desc = "The ISU sends a signal indicating that the gpr mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.", }, [ PPC970_PME_PM_MRK_ST_CMPL ] = { .pme_name = "PM_MRK_ST_CMPL", .pme_code = 0x1003, .pme_short_desc = "Marked store instruction completed", .pme_long_desc = "A sampled store has completed (data home)", }, [ PPC970_PME_PM_FPU0_STF ] = { .pme_name = "PM_FPU0_STF", .pme_code = 0x122, .pme_short_desc = "FPU0 executed store instruction", .pme_long_desc = "This signal is active for one cycle when fp0 is executing a store instruction.", }, [ PPC970_PME_PM_FPU1_FMA ] = { .pme_name = "PM_FPU1_FMA", .pme_code = 0x105, .pme_short_desc = "FPU1 executed multiply-add instruction", .pme_long_desc = "This signal is active for one cycle when fp1 is executing multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs.", }, [ PPC970_PME_PM_LSU1_FLUSH_ULD ] = { .pme_name = "PM_LSU1_FLUSH_ULD", .pme_code = 0x804, .pme_short_desc = "LSU1 unaligned load flushes", .pme_long_desc = "A load was flushed from unit 1 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)", }, [ PPC970_PME_PM_MRK_INST_FIN ] = { .pme_name = "PM_MRK_INST_FIN", .pme_code = 0x7005, .pme_short_desc = "Marked instruction finished", .pme_long_desc = "One of the execution units finished a marked instruction. Instructions that finish may not necessary complete", }, [ PPC970_PME_PM_MRK_LSU0_FLUSH_UST ] = { .pme_name = "PM_MRK_LSU0_FLUSH_UST", .pme_code = 0x711, .pme_short_desc = "LSU0 marked unaligned store flushes", .pme_long_desc = "A marked store was flushed from unit 0 because it was unaligned", }, [ PPC970_PME_PM_LSU_LRQ_S0_ALLOC ] = { .pme_name = "PM_LSU_LRQ_S0_ALLOC", .pme_code = 0x826, .pme_short_desc = "LRQ slot 0 allocated", .pme_long_desc = "LRQ slot zero was allocated", }, [ PPC970_PME_PM_FPU_FDIV ] = { .pme_name = "PM_FPU_FDIV", .pme_code = 0x1100, .pme_short_desc = "FPU executed FDIV instruction", .pme_long_desc = "This signal is active for one cycle at the end of the microcode executed when FPU is executing a divide instruction. This could be fdiv, fdivs, fdiv. fdivs. Combined Unit 0 + Unit 1", }, [ PPC970_PME_PM_FPU0_FULL_CYC ] = { .pme_name = "PM_FPU0_FULL_CYC", .pme_code = 0x303, .pme_short_desc = "Cycles FPU0 issue queue full", .pme_long_desc = "The issue queue for FPU unit 0 cannot accept any more instructions. Issue is stopped", }, [ PPC970_PME_PM_FPU_SINGLE ] = { .pme_name = "PM_FPU_SINGLE", .pme_code = 0x5120, .pme_short_desc = "FPU executed single precision instruction", .pme_long_desc = "FPU is executing single precision instruction. Combined Unit 0 + Unit 1", }, [ PPC970_PME_PM_FPU0_FMA ] = { .pme_name = "PM_FPU0_FMA", .pme_code = 0x101, .pme_short_desc = "FPU0 executed multiply-add instruction", .pme_long_desc = "This signal is active for one cycle when fp0 is executing multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs.", }, [ PPC970_PME_PM_MRK_LSU1_FLUSH_ULD ] = { .pme_name = "PM_MRK_LSU1_FLUSH_ULD", .pme_code = 0x714, .pme_short_desc = "LSU1 marked unaligned load flushes", .pme_long_desc = "A marked load was flushed from unit 1 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)", }, [ PPC970_PME_PM_LSU1_FLUSH_LRQ ] = { .pme_name = "PM_LSU1_FLUSH_LRQ", .pme_code = 0x806, .pme_short_desc = "LSU1 LRQ flushes", .pme_long_desc = "A load was flushed by unit 1 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.", }, [ PPC970_PME_PM_DTLB_MISS ] = { .pme_name = "PM_DTLB_MISS", .pme_code = 0x704, .pme_short_desc = "Data TLB misses", .pme_long_desc = "A TLB miss for a data request occurred. Requests that miss the TLB may be retried until the instruction is in the next to complete group (unless HID4 is set to allow speculative tablewalks). This may result in multiple TLB misses for the same instruction.", }, [ PPC970_PME_PM_MRK_ST_MISS_L1 ] = { .pme_name = "PM_MRK_ST_MISS_L1", .pme_code = 0x723, .pme_short_desc = "Marked L1 D cache store misses", .pme_long_desc = "A marked store missed the dcache", }, [ PPC970_PME_PM_EXT_INT ] = { .pme_name = "PM_EXT_INT", .pme_code = 0x8002, .pme_short_desc = "External interrupts", .pme_long_desc = "An external interrupt occurred", }, [ PPC970_PME_PM_MRK_LSU1_FLUSH_LRQ ] = { .pme_name = "PM_MRK_LSU1_FLUSH_LRQ", .pme_code = 0x716, .pme_short_desc = "LSU1 marked LRQ flushes", .pme_long_desc = "A marked load was flushed by unit 1 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.", }, [ PPC970_PME_PM_MRK_ST_GPS ] = { .pme_name = "PM_MRK_ST_GPS", .pme_code = 0x6003, .pme_short_desc = "Marked store sent to GPS", .pme_long_desc = "A sampled store has been sent to the memory subsystem", }, [ PPC970_PME_PM_GRP_DISP_SUCCESS ] = { .pme_name = "PM_GRP_DISP_SUCCESS", .pme_code = 0x5001, .pme_short_desc = "Group dispatch success", .pme_long_desc = "Number of groups sucessfully dispatched (not rejected)", }, [ PPC970_PME_PM_LSU1_LDF ] = { .pme_name = "PM_LSU1_LDF", .pme_code = 0x734, .pme_short_desc = "LSU1 executed Floating Point load instruction", .pme_long_desc = "A floating point load was executed from LSU unit 1", }, [ PPC970_PME_PM_LSU0_SRQ_STFWD ] = { .pme_name = "PM_LSU0_SRQ_STFWD", .pme_code = 0x820, .pme_short_desc = "LSU0 SRQ store forwarded", .pme_long_desc = "Data from a store instruction was forwarded to a load on unit 0", }, [ PPC970_PME_PM_CR_MAP_FULL_CYC ] = { .pme_name = "PM_CR_MAP_FULL_CYC", .pme_code = 0x304, .pme_short_desc = "Cycles CR logical operation mapper full", .pme_long_desc = "The ISU sends a signal indicating that the cr mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.", }, [ PPC970_PME_PM_MRK_LSU0_FLUSH_ULD ] = { .pme_name = "PM_MRK_LSU0_FLUSH_ULD", .pme_code = 0x710, .pme_short_desc = "LSU0 marked unaligned load flushes", .pme_long_desc = "A marked load was flushed from unit 0 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)", }, [ PPC970_PME_PM_LSU_DERAT_MISS ] = { .pme_name = "PM_LSU_DERAT_MISS", .pme_code = 0x6700, .pme_short_desc = "DERAT misses", .pme_long_desc = "Total D-ERAT Misses (Unit 0 + Unit 1). Requests that miss the Derat are rejected and retried until the request hits in the Erat. This may result in multiple erat misses for the same instruction.", }, [ PPC970_PME_PM_FPU0_SINGLE ] = { .pme_name = "PM_FPU0_SINGLE", .pme_code = 0x123, .pme_short_desc = "FPU0 executed single precision instruction", .pme_long_desc = "This signal is active for one cycle when fp0 is executing single precision instruction.", }, [ PPC970_PME_PM_FPU1_FDIV ] = { .pme_name = "PM_FPU1_FDIV", .pme_code = 0x104, .pme_short_desc = "FPU1 executed FDIV instruction", .pme_long_desc = "This signal is active for one cycle at the end of the microcode executed when fp1 is executing a divide instruction. This could be fdiv, fdivs, fdiv. fdivs.", }, [ PPC970_PME_PM_FPU1_FEST ] = { .pme_name = "PM_FPU1_FEST", .pme_code = 0x116, .pme_short_desc = "FPU1 executed FEST instruction", .pme_long_desc = "This signal is active for one cycle when fp1 is executing one of the estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ. ", }, [ PPC970_PME_PM_FPU0_FRSP_FCONV ] = { .pme_name = "PM_FPU0_FRSP_FCONV", .pme_code = 0x111, .pme_short_desc = "FPU0 executed FRSP or FCONV instructions", .pme_long_desc = "This signal is active for one cycle when fp0 is executing frsp or convert kind of instruction. This could be frsp*, fcfid*, fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs.", }, [ PPC970_PME_PM_GCT_EMPTY_SRQ_FULL ] = { .pme_name = "PM_GCT_EMPTY_SRQ_FULL", .pme_code = 0x200b, .pme_short_desc = "GCT empty caused by SRQ full", .pme_long_desc = "GCT empty caused by SRQ full", }, [ PPC970_PME_PM_MRK_ST_CMPL_INT ] = { .pme_name = "PM_MRK_ST_CMPL_INT", .pme_code = 0x3003, .pme_short_desc = "Marked store completed with intervention", .pme_long_desc = "A marked store previously sent to the memory subsystem completed (data home) after requiring intervention", }, [ PPC970_PME_PM_FLUSH_BR_MPRED ] = { .pme_name = "PM_FLUSH_BR_MPRED", .pme_code = 0x316, .pme_short_desc = "Flush caused by branch mispredict", .pme_long_desc = "Flush caused by branch mispredict", }, [ PPC970_PME_PM_FXU_FIN ] = { .pme_name = "PM_FXU_FIN", .pme_code = 0x3330, .pme_short_desc = "FXU produced a result", .pme_long_desc = "The fixed point unit (Unit 0 + Unit 1) finished a marked instruction. Instructions that finish may not necessary complete.", }, [ PPC970_PME_PM_FPU_STF ] = { .pme_name = "PM_FPU_STF", .pme_code = 0x6120, .pme_short_desc = "FPU executed store instruction", .pme_long_desc = "FPU is executing a store instruction. Combined Unit 0 + Unit 1", }, [ PPC970_PME_PM_DSLB_MISS ] = { .pme_name = "PM_DSLB_MISS", .pme_code = 0x705, .pme_short_desc = "Data SLB misses", .pme_long_desc = "A SLB miss for a data request occurred. SLB misses trap to the operating system to resolve", }, [ PPC970_PME_PM_FXLS1_FULL_CYC ] = { .pme_name = "PM_FXLS1_FULL_CYC", .pme_code = 0x314, .pme_short_desc = "Cycles FXU1/LS1 queue full", .pme_long_desc = "The issue queue for FXU/LSU unit 0 cannot accept any more instructions. Issue is stopped", }, [ PPC970_PME_PM_LSU_LMQ_LHR_MERGE ] = { .pme_name = "PM_LSU_LMQ_LHR_MERGE", .pme_code = 0x935, .pme_short_desc = "LMQ LHR merges", .pme_long_desc = "A dcache miss occurred for the same real cache line address as an earlier request already in the Load Miss Queue and was merged into the LMQ entry.", }, [ PPC970_PME_PM_MRK_STCX_FAIL ] = { .pme_name = "PM_MRK_STCX_FAIL", .pme_code = 0x726, .pme_short_desc = "Marked STCX failed", .pme_long_desc = "A marked stcx (stwcx or stdcx) failed", }, [ PPC970_PME_PM_FXU0_BUSY_FXU1_IDLE ] = { .pme_name = "PM_FXU0_BUSY_FXU1_IDLE", .pme_code = 0x7002, .pme_short_desc = "FXU0 busy FXU1 idle", .pme_long_desc = "FXU0 is busy while FXU1 was idle", }, [ PPC970_PME_PM_MRK_DATA_FROM_L25_SHR ] = { .pme_name = "PM_MRK_DATA_FROM_L25_SHR", .pme_code = 0x193d, .pme_short_desc = "Marked data loaded from L2.5 shared", .pme_long_desc = "DL1 was reloaded with shared (T or SL) data from the L2 of a chip on this MCM due to a marked demand load", }, [ PPC970_PME_PM_LSU_FLUSH_ULD ] = { .pme_name = "PM_LSU_FLUSH_ULD", .pme_code = 0x1800, .pme_short_desc = "LRQ unaligned load flushes", .pme_long_desc = "A load was flushed because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)", }, [ PPC970_PME_PM_MRK_BRU_FIN ] = { .pme_name = "PM_MRK_BRU_FIN", .pme_code = 0x2005, .pme_short_desc = "Marked instruction BRU processing finished", .pme_long_desc = "The branch unit finished a marked instruction. Instructions that finish may not necessary complete", }, [ PPC970_PME_PM_IERAT_XLATE_WR ] = { .pme_name = "PM_IERAT_XLATE_WR", .pme_code = 0x430, .pme_short_desc = "Translation written to ierat", .pme_long_desc = "This signal will be asserted each time the I-ERAT is written. This indicates that an ERAT miss has been serviced. ERAT misses will initiate a sequence resulting in the ERAT being written. ERAT misses that are later ignored will not be counted unless the ERAT is written before the instruction stream is changed, This should be a fairly accurate count of ERAT missed (best available).", }, [ PPC970_PME_PM_DATA_FROM_MEM ] = { .pme_name = "PM_DATA_FROM_MEM", .pme_code = 0x3837, .pme_short_desc = "Data loaded from memory", .pme_long_desc = "Data loaded from memory", }, [ PPC970_PME_PM_FPR_MAP_FULL_CYC ] = { .pme_name = "PM_FPR_MAP_FULL_CYC", .pme_code = 0x301, .pme_short_desc = "Cycles FPR mapper full", .pme_long_desc = "The ISU sends a signal indicating that the FPR mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.", }, [ PPC970_PME_PM_FPU1_FULL_CYC ] = { .pme_name = "PM_FPU1_FULL_CYC", .pme_code = 0x307, .pme_short_desc = "Cycles FPU1 issue queue full", .pme_long_desc = "The issue queue for FPU unit 1 cannot accept any more instructions. Issue is stopped", }, [ PPC970_PME_PM_FPU0_FIN ] = { .pme_name = "PM_FPU0_FIN", .pme_code = 0x113, .pme_short_desc = "FPU0 produced a result", .pme_long_desc = "fp0 finished, produced a result This only indicates finish, not completion. ", }, [ PPC970_PME_PM_GRP_BR_REDIR ] = { .pme_name = "PM_GRP_BR_REDIR", .pme_code = 0x326, .pme_short_desc = "Group experienced branch redirect", .pme_long_desc = "Group experienced branch redirect", }, [ PPC970_PME_PM_THRESH_TIMEO ] = { .pme_name = "PM_THRESH_TIMEO", .pme_code = 0x2003, .pme_short_desc = "Threshold timeout", .pme_long_desc = "The threshold timer expired", }, [ PPC970_PME_PM_FPU_FSQRT ] = { .pme_name = "PM_FPU_FSQRT", .pme_code = 0x6100, .pme_short_desc = "FPU executed FSQRT instruction", .pme_long_desc = "This signal is active for one cycle at the end of the microcode executed when FPU is executing a square root instruction. This could be fsqrt* where XYZ* means XYZ, XYZs, XYZ., XYZs. Combined Unit 0 + Unit 1", }, [ PPC970_PME_PM_MRK_LSU0_FLUSH_LRQ ] = { .pme_name = "PM_MRK_LSU0_FLUSH_LRQ", .pme_code = 0x712, .pme_short_desc = "LSU0 marked LRQ flushes", .pme_long_desc = "A marked load was flushed by unit 0 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.", }, [ PPC970_PME_PM_PMC1_OVERFLOW ] = { .pme_name = "PM_PMC1_OVERFLOW", .pme_code = 0x200a, .pme_short_desc = "PMC1 Overflow", .pme_long_desc = "PMC1 Overflow", }, [ PPC970_PME_PM_FXLS0_FULL_CYC ] = { .pme_name = "PM_FXLS0_FULL_CYC", .pme_code = 0x310, .pme_short_desc = "Cycles FXU0/LS0 queue full", .pme_long_desc = "The issue queue for FXU/LSU unit 0 cannot accept any more instructions. Issue is stopped", }, [ PPC970_PME_PM_FPU0_ALL ] = { .pme_name = "PM_FPU0_ALL", .pme_code = 0x103, .pme_short_desc = "FPU0 executed add, mult, sub, cmp or sel instruction", .pme_long_desc = "This signal is active for one cycle when fp0 is executing an add, mult, sub, compare, or fsel kind of instruction. This could be fadd*, fmul*, fsub*, fcmp**, fsel where XYZ* means XYZ, XYZs, XYZ., XYZs. and XYZ** means XYZu, XYZo", }, [ PPC970_PME_PM_DATA_TABLEWALK_CYC ] = { .pme_name = "PM_DATA_TABLEWALK_CYC", .pme_code = 0x707, .pme_short_desc = "Cycles doing data tablewalks", .pme_long_desc = "This signal is asserted every cycle when a tablewalk is active. While a tablewalk is active any request attempting to access the TLB will be rejected and retried.", }, [ PPC970_PME_PM_FPU0_FEST ] = { .pme_name = "PM_FPU0_FEST", .pme_code = 0x112, .pme_short_desc = "FPU0 executed FEST instruction", .pme_long_desc = "This signal is active for one cycle when fp0 is executing one of the estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ. ", }, [ PPC970_PME_PM_DATA_FROM_L25_MOD ] = { .pme_name = "PM_DATA_FROM_L25_MOD", .pme_code = 0x383d, .pme_short_desc = "Data loaded from L2.5 modified", .pme_long_desc = "DL1 was reloaded with modified (M) data from the L2 of a chip on this MCM due to a demand load", }, [ PPC970_PME_PM_LSU0_REJECT_ERAT_MISS ] = { .pme_name = "PM_LSU0_REJECT_ERAT_MISS", .pme_code = 0x923, .pme_short_desc = "LSU0 reject due to ERAT miss", .pme_long_desc = "LSU0 reject due to ERAT miss", }, [ PPC970_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC ] = { .pme_name = "PM_LSU_LMQ_SRQ_EMPTY_CYC", .pme_code = 0x2002, .pme_short_desc = "Cycles LMQ and SRQ empty", .pme_long_desc = "Cycles when both the LMQ and SRQ are empty (LSU is idle)", }, [ PPC970_PME_PM_LSU0_REJECT_RELOAD_CDF ] = { .pme_name = "PM_LSU0_REJECT_RELOAD_CDF", .pme_code = 0x922, .pme_short_desc = "LSU0 reject due to reload CDF or tag update collision", .pme_long_desc = "LSU0 reject due to reload CDF or tag update collision", }, [ PPC970_PME_PM_FPU_FEST ] = { .pme_name = "PM_FPU_FEST", .pme_code = 0x3110, .pme_short_desc = "FPU executed FEST instruction", .pme_long_desc = "This signal is active for one cycle when executing one of the estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ. Combined Unit 0 + Unit 1.", }, [ PPC970_PME_PM_0INST_FETCH ] = { .pme_name = "PM_0INST_FETCH", .pme_code = 0x442d, .pme_short_desc = "No instructions fetched", .pme_long_desc = "No instructions were fetched this cycles (due to IFU hold, redirect, or icache miss)", }, [ PPC970_PME_PM_LD_MISS_L1_LSU0 ] = { .pme_name = "PM_LD_MISS_L1_LSU0", .pme_code = 0x812, .pme_short_desc = "LSU0 L1 D cache load misses", .pme_long_desc = "A load, executing on unit 0, missed the dcache", }, [ PPC970_PME_PM_LSU1_REJECT_RELOAD_CDF ] = { .pme_name = "PM_LSU1_REJECT_RELOAD_CDF", .pme_code = 0x926, .pme_short_desc = "LSU1 reject due to reload CDF or tag update collision", .pme_long_desc = "LSU1 reject due to reload CDF or tag update collision", }, [ PPC970_PME_PM_L1_PREF ] = { .pme_name = "PM_L1_PREF", .pme_code = 0x731, .pme_short_desc = "L1 cache data prefetches", .pme_long_desc = "A request to prefetch data into the L1 was made", }, [ PPC970_PME_PM_FPU1_STALL3 ] = { .pme_name = "PM_FPU1_STALL3", .pme_code = 0x125, .pme_short_desc = "FPU1 stalled in pipe3", .pme_long_desc = "This signal indicates that fp1 has generated a stall in pipe3 due to overflow, underflow, massive cancel, convert to integer (sometimes), or convert from integer (always). This signal is active during the entire duration of the stall. ", }, [ PPC970_PME_PM_BRQ_FULL_CYC ] = { .pme_name = "PM_BRQ_FULL_CYC", .pme_code = 0x305, .pme_short_desc = "Cycles branch queue full", .pme_long_desc = "The ISU sends a signal indicating that the issue queue that feeds the ifu br unit cannot accept any more group (queue is full of groups).", }, [ PPC970_PME_PM_PMC8_OVERFLOW ] = { .pme_name = "PM_PMC8_OVERFLOW", .pme_code = 0x100a, .pme_short_desc = "PMC8 Overflow", .pme_long_desc = "PMC8 Overflow", }, [ PPC970_PME_PM_PMC7_OVERFLOW ] = { .pme_name = "PM_PMC7_OVERFLOW", .pme_code = 0x800a, .pme_short_desc = "PMC7 Overflow", .pme_long_desc = "PMC7 Overflow", }, [ PPC970_PME_PM_WORK_HELD ] = { .pme_name = "PM_WORK_HELD", .pme_code = 0x2001, .pme_short_desc = "Work held", .pme_long_desc = "RAS Unit has signaled completion to stop and there are groups waiting to complete", }, [ PPC970_PME_PM_MRK_LD_MISS_L1_LSU0 ] = { .pme_name = "PM_MRK_LD_MISS_L1_LSU0", .pme_code = 0x720, .pme_short_desc = "LSU0 L1 D cache load misses", .pme_long_desc = "A marked load, executing on unit 0, missed the dcache", }, [ PPC970_PME_PM_FXU_IDLE ] = { .pme_name = "PM_FXU_IDLE", .pme_code = 0x5002, .pme_short_desc = "FXU idle", .pme_long_desc = "FXU0 and FXU1 are both idle", }, [ PPC970_PME_PM_INST_CMPL ] = { .pme_name = "PM_INST_CMPL", .pme_code = 0x1, .pme_short_desc = "Instructions completed", .pme_long_desc = "Number of Eligible Instructions that completed. ", }, [ PPC970_PME_PM_LSU1_FLUSH_UST ] = { .pme_name = "PM_LSU1_FLUSH_UST", .pme_code = 0x805, .pme_short_desc = "LSU1 unaligned store flushes", .pme_long_desc = "A store was flushed from unit 1 because it was unaligned (crossed a 4k boundary)", }, [ PPC970_PME_PM_LSU0_FLUSH_ULD ] = { .pme_name = "PM_LSU0_FLUSH_ULD", .pme_code = 0x800, .pme_short_desc = "LSU0 unaligned load flushes", .pme_long_desc = "A load was flushed from unit 0 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)", }, [ PPC970_PME_PM_LSU_FLUSH ] = { .pme_name = "PM_LSU_FLUSH", .pme_code = 0x315, .pme_short_desc = "Flush initiated by LSU", .pme_long_desc = "Flush initiated by LSU", }, [ PPC970_PME_PM_INST_FROM_L2 ] = { .pme_name = "PM_INST_FROM_L2", .pme_code = 0x1426, .pme_short_desc = "Instructions fetched from L2", .pme_long_desc = "An instruction fetch group was fetched from L2. Fetch Groups can contain up to 8 instructions", }, [ PPC970_PME_PM_LSU1_REJECT_LMQ_FULL ] = { .pme_name = "PM_LSU1_REJECT_LMQ_FULL", .pme_code = 0x925, .pme_short_desc = "LSU1 reject due to LMQ full or missed data coming", .pme_long_desc = "LSU1 reject due to LMQ full or missed data coming", }, [ PPC970_PME_PM_PMC2_OVERFLOW ] = { .pme_name = "PM_PMC2_OVERFLOW", .pme_code = 0x300a, .pme_short_desc = "PMC2 Overflow", .pme_long_desc = "PMC2 Overflow", }, [ PPC970_PME_PM_FPU0_DENORM ] = { .pme_name = "PM_FPU0_DENORM", .pme_code = 0x120, .pme_short_desc = "FPU0 received denormalized data", .pme_long_desc = "This signal is active for one cycle when one of the operands is denormalized.", }, [ PPC970_PME_PM_FPU1_FMOV_FEST ] = { .pme_name = "PM_FPU1_FMOV_FEST", .pme_code = 0x114, .pme_short_desc = "FPU1 executing FMOV or FEST instructions", .pme_long_desc = "This signal is active for one cycle when fp1 is executing a move kind of instruction or one of the estimate instructions.. This could be fmr*, fneg*, fabs*, fnabs* , fres* or frsqrte* where XYZ* means XYZ or XYZ", }, [ PPC970_PME_PM_GRP_DISP_REJECT ] = { .pme_name = "PM_GRP_DISP_REJECT", .pme_code = 0x324, .pme_short_desc = "Group dispatch rejected", .pme_long_desc = "A group that previously attempted dispatch was rejected.", }, [ PPC970_PME_PM_LSU_LDF ] = { .pme_name = "PM_LSU_LDF", .pme_code = 0x8730, .pme_short_desc = "LSU executed Floating Point load instruction", .pme_long_desc = "LSU executed Floating Point load instruction", }, [ PPC970_PME_PM_INST_DISP ] = { .pme_name = "PM_INST_DISP", .pme_code = 0x320, .pme_short_desc = "Instructions dispatched", .pme_long_desc = "The ISU sends the number of instructions dispatched.", }, [ PPC970_PME_PM_DATA_FROM_L25_SHR ] = { .pme_name = "PM_DATA_FROM_L25_SHR", .pme_code = 0x183d, .pme_short_desc = "Data loaded from L2.5 shared", .pme_long_desc = "DL1 was reloaded with shared (T or SL) data from the L2 of a chip on this MCM due to a demand load", }, [ PPC970_PME_PM_L1_DCACHE_RELOAD_VALID ] = { .pme_name = "PM_L1_DCACHE_RELOAD_VALID", .pme_code = 0x834, .pme_short_desc = "L1 reload data source valid", .pme_long_desc = "The data source information is valid", }, [ PPC970_PME_PM_MRK_GRP_ISSUED ] = { .pme_name = "PM_MRK_GRP_ISSUED", .pme_code = 0x6005, .pme_short_desc = "Marked group issued", .pme_long_desc = "A sampled instruction was issued", }, [ PPC970_PME_PM_FPU_FMA ] = { .pme_name = "PM_FPU_FMA", .pme_code = 0x2100, .pme_short_desc = "FPU executed multiply-add instruction", .pme_long_desc = "This signal is active for one cycle when FPU is executing multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs. Combined Unit 0 + Unit 1", }, [ PPC970_PME_PM_MRK_CRU_FIN ] = { .pme_name = "PM_MRK_CRU_FIN", .pme_code = 0x4005, .pme_short_desc = "Marked instruction CRU processing finished", .pme_long_desc = "The Condition Register Unit finished a marked instruction. Instructions that finish may not necessary complete", }, [ PPC970_PME_PM_MRK_LSU1_FLUSH_UST ] = { .pme_name = "PM_MRK_LSU1_FLUSH_UST", .pme_code = 0x715, .pme_short_desc = "LSU1 marked unaligned store flushes", .pme_long_desc = "A marked store was flushed from unit 1 because it was unaligned (crossed a 4k boundary)", }, [ PPC970_PME_PM_MRK_FXU_FIN ] = { .pme_name = "PM_MRK_FXU_FIN", .pme_code = 0x6004, .pme_short_desc = "Marked instruction FXU processing finished", .pme_long_desc = "Marked instruction FXU processing finished", }, [ PPC970_PME_PM_LSU1_REJECT_ERAT_MISS ] = { .pme_name = "PM_LSU1_REJECT_ERAT_MISS", .pme_code = 0x927, .pme_short_desc = "LSU1 reject due to ERAT miss", .pme_long_desc = "LSU1 reject due to ERAT miss", }, [ PPC970_PME_PM_BR_ISSUED ] = { .pme_name = "PM_BR_ISSUED", .pme_code = 0x431, .pme_short_desc = "Branches issued", .pme_long_desc = "This signal will be asserted each time the ISU issues a branch instruction. This signal will be asserted each time the ISU selects a branch instruction to issue.", }, [ PPC970_PME_PM_PMC4_OVERFLOW ] = { .pme_name = "PM_PMC4_OVERFLOW", .pme_code = 0x500a, .pme_short_desc = "PMC4 Overflow", .pme_long_desc = "PMC4 Overflow", }, [ PPC970_PME_PM_EE_OFF ] = { .pme_name = "PM_EE_OFF", .pme_code = 0x333, .pme_short_desc = "Cycles MSR(EE) bit off", .pme_long_desc = "The number of Cycles MSR(EE) bit was off.", }, [ PPC970_PME_PM_INST_FROM_L25_MOD ] = { .pme_name = "PM_INST_FROM_L25_MOD", .pme_code = 0x6426, .pme_short_desc = "Instruction fetched from L2.5 modified", .pme_long_desc = "Instruction fetched from L2.5 modified", }, [ PPC970_PME_PM_ITLB_MISS ] = { .pme_name = "PM_ITLB_MISS", .pme_code = 0x700, .pme_short_desc = "Instruction TLB misses", .pme_long_desc = "A TLB miss for an Instruction Fetch has occurred", }, [ PPC970_PME_PM_FXU1_BUSY_FXU0_IDLE ] = { .pme_name = "PM_FXU1_BUSY_FXU0_IDLE", .pme_code = 0x4002, .pme_short_desc = "FXU1 busy FXU0 idle", .pme_long_desc = "FXU0 was idle while FXU1 was busy", }, [ PPC970_PME_PM_GRP_DISP_VALID ] = { .pme_name = "PM_GRP_DISP_VALID", .pme_code = 0x323, .pme_short_desc = "Group dispatch valid", .pme_long_desc = "Dispatch has been attempted for a valid group. Some groups may be rejected. The total number of successful dispatches is the number of dispatch valid minus dispatch reject.", }, [ PPC970_PME_PM_MRK_GRP_DISP ] = { .pme_name = "PM_MRK_GRP_DISP", .pme_code = 0x1002, .pme_short_desc = "Marked group dispatched", .pme_long_desc = "A group containing a sampled instruction was dispatched", }, [ PPC970_PME_PM_LSU_FLUSH_UST ] = { .pme_name = "PM_LSU_FLUSH_UST", .pme_code = 0x2800, .pme_short_desc = "SRQ unaligned store flushes", .pme_long_desc = "A store was flushed because it was unaligned", }, [ PPC970_PME_PM_FXU1_FIN ] = { .pme_name = "PM_FXU1_FIN", .pme_code = 0x336, .pme_short_desc = "FXU1 produced a result", .pme_long_desc = "The Fixed Point unit 1 finished an instruction and produced a result", }, [ PPC970_PME_PM_GRP_CMPL ] = { .pme_name = "PM_GRP_CMPL", .pme_code = 0x7003, .pme_short_desc = "Group completed", .pme_long_desc = "A group completed. Microcoded instructions that span multiple groups will generate this event once per group.", }, [ PPC970_PME_PM_FPU_FRSP_FCONV ] = { .pme_name = "PM_FPU_FRSP_FCONV", .pme_code = 0x7110, .pme_short_desc = "FPU executed FRSP or FCONV instructions", .pme_long_desc = "This signal is active for one cycle when executing frsp or convert kind of instruction. This could be frsp*, fcfid*, fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs. Combined Unit 0 + Unit 1", }, [ PPC970_PME_PM_MRK_LSU0_FLUSH_SRQ ] = { .pme_name = "PM_MRK_LSU0_FLUSH_SRQ", .pme_code = 0x713, .pme_short_desc = "LSU0 marked SRQ flushes", .pme_long_desc = "A marked store was flushed because younger load hits and older store that is already in the SRQ or in the same group.", }, [ PPC970_PME_PM_LSU_LMQ_FULL_CYC ] = { .pme_name = "PM_LSU_LMQ_FULL_CYC", .pme_code = 0x837, .pme_short_desc = "Cycles LMQ full", .pme_long_desc = "The LMQ was full", }, [ PPC970_PME_PM_ST_REF_L1_LSU0 ] = { .pme_name = "PM_ST_REF_L1_LSU0", .pme_code = 0x811, .pme_short_desc = "LSU0 L1 D cache store references", .pme_long_desc = "A store executed on unit 0", }, [ PPC970_PME_PM_LSU0_DERAT_MISS ] = { .pme_name = "PM_LSU0_DERAT_MISS", .pme_code = 0x702, .pme_short_desc = "LSU0 DERAT misses", .pme_long_desc = "A data request (load or store) from LSU Unit 0 missed the ERAT and resulted in an ERAT reload. Multiple instructions may miss the ERAT entry for the same 4K page, but only one reload will occur.", }, [ PPC970_PME_PM_LSU_SRQ_SYNC_CYC ] = { .pme_name = "PM_LSU_SRQ_SYNC_CYC", .pme_code = 0x735, .pme_short_desc = "SRQ sync duration", .pme_long_desc = "This signal is asserted every cycle when a sync is in the SRQ.", }, [ PPC970_PME_PM_FPU_STALL3 ] = { .pme_name = "PM_FPU_STALL3", .pme_code = 0x2120, .pme_short_desc = "FPU stalled in pipe3", .pme_long_desc = "FPU has generated a stall in pipe3 due to overflow, underflow, massive cancel, convert to integer (sometimes), or convert from integer (always). This signal is active during the entire duration of the stall. Combined Unit 0 + Unit 1", }, [ PPC970_PME_PM_LSU_REJECT_ERAT_MISS ] = { .pme_name = "PM_LSU_REJECT_ERAT_MISS", .pme_code = 0x5920, .pme_short_desc = "LSU reject due to ERAT miss", .pme_long_desc = "LSU reject due to ERAT miss", }, [ PPC970_PME_PM_MRK_DATA_FROM_L2 ] = { .pme_name = "PM_MRK_DATA_FROM_L2", .pme_code = 0x1937, .pme_short_desc = "Marked data loaded from L2", .pme_long_desc = "DL1 was reloaded from the local L2 due to a marked demand load", }, [ PPC970_PME_PM_LSU0_FLUSH_SRQ ] = { .pme_name = "PM_LSU0_FLUSH_SRQ", .pme_code = 0x803, .pme_short_desc = "LSU0 SRQ flushes", .pme_long_desc = "A store was flushed because younger load hits and older store that is already in the SRQ or in the same group.", }, [ PPC970_PME_PM_FPU0_FMOV_FEST ] = { .pme_name = "PM_FPU0_FMOV_FEST", .pme_code = 0x110, .pme_short_desc = "FPU0 executed FMOV or FEST instructions", .pme_long_desc = "This signal is active for one cycle when fp0 is executing a move kind of instruction or one of the estimate instructions.. This could be fmr*, fneg*, fabs*, fnabs* , fres* or frsqrte* where XYZ* means XYZ or XYZ", }, [ PPC970_PME_PM_LD_REF_L1_LSU0 ] = { .pme_name = "PM_LD_REF_L1_LSU0", .pme_code = 0x810, .pme_short_desc = "LSU0 L1 D cache load references", .pme_long_desc = "A load executed on unit 0", }, [ PPC970_PME_PM_LSU1_FLUSH_SRQ ] = { .pme_name = "PM_LSU1_FLUSH_SRQ", .pme_code = 0x807, .pme_short_desc = "LSU1 SRQ flushes", .pme_long_desc = "A store was flushed because younger load hits and older store that is already in the SRQ or in the same group. ", }, [ PPC970_PME_PM_GRP_BR_MPRED ] = { .pme_name = "PM_GRP_BR_MPRED", .pme_code = 0x327, .pme_short_desc = "Group experienced a branch mispredict", .pme_long_desc = "Group experienced a branch mispredict", }, [ PPC970_PME_PM_LSU_LMQ_S0_ALLOC ] = { .pme_name = "PM_LSU_LMQ_S0_ALLOC", .pme_code = 0x836, .pme_short_desc = "LMQ slot 0 allocated", .pme_long_desc = "The first entry in the LMQ was allocated.", }, [ PPC970_PME_PM_LSU0_REJECT_LMQ_FULL ] = { .pme_name = "PM_LSU0_REJECT_LMQ_FULL", .pme_code = 0x921, .pme_short_desc = "LSU0 reject due to LMQ full or missed data coming", .pme_long_desc = "LSU0 reject due to LMQ full or missed data coming", }, [ PPC970_PME_PM_ST_REF_L1 ] = { .pme_name = "PM_ST_REF_L1", .pme_code = 0x7810, .pme_short_desc = "L1 D cache store references", .pme_long_desc = "Total DL1 Store references", }, [ PPC970_PME_PM_MRK_VMX_FIN ] = { .pme_name = "PM_MRK_VMX_FIN", .pme_code = 0x3005, .pme_short_desc = "Marked instruction VMX processing finished", .pme_long_desc = "Marked instruction VMX processing finished", }, [ PPC970_PME_PM_LSU_SRQ_EMPTY_CYC ] = { .pme_name = "PM_LSU_SRQ_EMPTY_CYC", .pme_code = 0x4003, .pme_short_desc = "Cycles SRQ empty", .pme_long_desc = "The Store Request Queue is empty", }, [ PPC970_PME_PM_FPU1_STF ] = { .pme_name = "PM_FPU1_STF", .pme_code = 0x126, .pme_short_desc = "FPU1 executed store instruction", .pme_long_desc = "This signal is active for one cycle when fp1 is executing a store instruction.", }, [ PPC970_PME_PM_RUN_CYC ] = { .pme_name = "PM_RUN_CYC", .pme_code = 0x1005, .pme_short_desc = "Run cycles", .pme_long_desc = "Processor Cycles gated by the run latch", }, [ PPC970_PME_PM_LSU_LMQ_S0_VALID ] = { .pme_name = "PM_LSU_LMQ_S0_VALID", .pme_code = 0x835, .pme_short_desc = "LMQ slot 0 valid", .pme_long_desc = "This signal is asserted every cycle when the first entry in the LMQ is valid. The LMQ had eight entries that are allocated FIFO", }, [ PPC970_PME_PM_LSU0_LDF ] = { .pme_name = "PM_LSU0_LDF", .pme_code = 0x730, .pme_short_desc = "LSU0 executed Floating Point load instruction", .pme_long_desc = "A floating point load was executed from LSU unit 0", }, [ PPC970_PME_PM_LSU_LRQ_S0_VALID ] = { .pme_name = "PM_LSU_LRQ_S0_VALID", .pme_code = 0x822, .pme_short_desc = "LRQ slot 0 valid", .pme_long_desc = "This signal is asserted every cycle that the Load Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin.", }, [ PPC970_PME_PM_PMC3_OVERFLOW ] = { .pme_name = "PM_PMC3_OVERFLOW", .pme_code = 0x400a, .pme_short_desc = "PMC3 Overflow", .pme_long_desc = "PMC3 Overflow", }, [ PPC970_PME_PM_MRK_IMR_RELOAD ] = { .pme_name = "PM_MRK_IMR_RELOAD", .pme_code = 0x722, .pme_short_desc = "Marked IMR reloaded", .pme_long_desc = "A DL1 reload occurred due to marked load", }, [ PPC970_PME_PM_MRK_GRP_TIMEO ] = { .pme_name = "PM_MRK_GRP_TIMEO", .pme_code = 0x5005, .pme_short_desc = "Marked group completion timeout", .pme_long_desc = "The sampling timeout expired indicating that the previously sampled instruction is no longer in the processor", }, [ PPC970_PME_PM_FPU_FMOV_FEST ] = { .pme_name = "PM_FPU_FMOV_FEST", .pme_code = 0x8110, .pme_short_desc = "FPU executing FMOV or FEST instructions", .pme_long_desc = "This signal is active for one cycle when executing a move kind of instruction or one of the estimate instructions.. This could be fmr*, fneg*, fabs*, fnabs* , fres* or frsqrte* where XYZ* means XYZ or XYZ . Combined Unit 0 + Unit 1", }, [ PPC970_PME_PM_GRP_DISP_BLK_SB_CYC ] = { .pme_name = "PM_GRP_DISP_BLK_SB_CYC", .pme_code = 0x331, .pme_short_desc = "Cycles group dispatch blocked by scoreboard", .pme_long_desc = "The ISU sends a signal indicating that dispatch is blocked by scoreboard.", }, [ PPC970_PME_PM_XER_MAP_FULL_CYC ] = { .pme_name = "PM_XER_MAP_FULL_CYC", .pme_code = 0x302, .pme_short_desc = "Cycles XER mapper full", .pme_long_desc = "The ISU sends a signal indicating that the xer mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.", }, [ PPC970_PME_PM_ST_MISS_L1 ] = { .pme_name = "PM_ST_MISS_L1", .pme_code = 0x813, .pme_short_desc = "L1 D cache store misses", .pme_long_desc = "A store missed the dcache", }, [ PPC970_PME_PM_STOP_COMPLETION ] = { .pme_name = "PM_STOP_COMPLETION", .pme_code = 0x3001, .pme_short_desc = "Completion stopped", .pme_long_desc = "RAS Unit has signaled completion to stop", }, [ PPC970_PME_PM_MRK_GRP_CMPL ] = { .pme_name = "PM_MRK_GRP_CMPL", .pme_code = 0x4004, .pme_short_desc = "Marked group completed", .pme_long_desc = "A group containing a sampled instruction completed. Microcoded instructions that span multiple groups will generate this event once per group.", }, [ PPC970_PME_PM_ISLB_MISS ] = { .pme_name = "PM_ISLB_MISS", .pme_code = 0x701, .pme_short_desc = "Instruction SLB misses", .pme_long_desc = "A SLB miss for an instruction fetch as occurred", }, [ PPC970_PME_PM_SUSPENDED ] = { .pme_name = "PM_SUSPENDED", .pme_code = 0x0, .pme_short_desc = "Suspended", .pme_long_desc = "Suspended", }, [ PPC970_PME_PM_CYC ] = { .pme_name = "PM_CYC", .pme_code = 0x7, .pme_short_desc = "Processor cycles", .pme_long_desc = "Processor cycles", }, [ PPC970_PME_PM_LD_MISS_L1_LSU1 ] = { .pme_name = "PM_LD_MISS_L1_LSU1", .pme_code = 0x816, .pme_short_desc = "LSU1 L1 D cache load misses", .pme_long_desc = "A load, executing on unit 1, missed the dcache", }, [ PPC970_PME_PM_STCX_FAIL ] = { .pme_name = "PM_STCX_FAIL", .pme_code = 0x721, .pme_short_desc = "STCX failed", .pme_long_desc = "A stcx (stwcx or stdcx) failed", }, [ PPC970_PME_PM_LSU1_SRQ_STFWD ] = { .pme_name = "PM_LSU1_SRQ_STFWD", .pme_code = 0x824, .pme_short_desc = "LSU1 SRQ store forwarded", .pme_long_desc = "Data from a store instruction was forwarded to a load on unit 1", }, [ PPC970_PME_PM_GRP_DISP ] = { .pme_name = "PM_GRP_DISP", .pme_code = 0x2004, .pme_short_desc = "Group dispatches", .pme_long_desc = "A group was dispatched", }, [ PPC970_PME_PM_L2_PREF ] = { .pme_name = "PM_L2_PREF", .pme_code = 0x733, .pme_short_desc = "L2 cache prefetches", .pme_long_desc = "A request to prefetch data into L2 was made", }, [ PPC970_PME_PM_FPU1_DENORM ] = { .pme_name = "PM_FPU1_DENORM", .pme_code = 0x124, .pme_short_desc = "FPU1 received denormalized data", .pme_long_desc = "This signal is active for one cycle when one of the operands is denormalized.", }, [ PPC970_PME_PM_DATA_FROM_L2 ] = { .pme_name = "PM_DATA_FROM_L2", .pme_code = 0x1837, .pme_short_desc = "Data loaded from L2", .pme_long_desc = "DL1 was reloaded from the local L2 due to a demand load", }, [ PPC970_PME_PM_FPU0_FPSCR ] = { .pme_name = "PM_FPU0_FPSCR", .pme_code = 0x130, .pme_short_desc = "FPU0 executed FPSCR instruction", .pme_long_desc = "This signal is active for one cycle when fp0 is executing fpscr move related instruction. This could be mtfsfi*, mtfsb0*, mtfsb1*. mffs*, mtfsf*, mcrsf* where XYZ* means XYZ, XYZs, XYZ., XYZs", }, [ PPC970_PME_PM_MRK_DATA_FROM_L25_MOD ] = { .pme_name = "PM_MRK_DATA_FROM_L25_MOD", .pme_code = 0x393d, .pme_short_desc = "Marked data loaded from L2.5 modified", .pme_long_desc = "DL1 was reloaded with modified (M) data from the L2 of a chip on this MCM due to a marked demand load", }, [ PPC970_PME_PM_FPU0_FSQRT ] = { .pme_name = "PM_FPU0_FSQRT", .pme_code = 0x102, .pme_short_desc = "FPU0 executed FSQRT instruction", .pme_long_desc = "This signal is active for one cycle at the end of the microcode executed when fp0 is executing a square root instruction. This could be fsqrt* where XYZ* means XYZ, XYZs, XYZ., XYZs.", }, [ PPC970_PME_PM_LD_REF_L1 ] = { .pme_name = "PM_LD_REF_L1", .pme_code = 0x8810, .pme_short_desc = "L1 D cache load references", .pme_long_desc = "Total DL1 Load references", }, [ PPC970_PME_PM_MRK_L1_RELOAD_VALID ] = { .pme_name = "PM_MRK_L1_RELOAD_VALID", .pme_code = 0x934, .pme_short_desc = "Marked L1 reload data source valid", .pme_long_desc = "The source information is valid and is for a marked load", }, [ PPC970_PME_PM_1PLUS_PPC_CMPL ] = { .pme_name = "PM_1PLUS_PPC_CMPL", .pme_code = 0x5003, .pme_short_desc = "One or more PPC instruction completed", .pme_long_desc = "A group containing at least one PPC instruction completed. For microcoded instructions that span multiple groups, this will only occur once.", }, [ PPC970_PME_PM_INST_FROM_L1 ] = { .pme_name = "PM_INST_FROM_L1", .pme_code = 0x142d, .pme_short_desc = "Instruction fetched from L1", .pme_long_desc = "An instruction fetch group was fetched from L1. Fetch Groups can contain up to 8 instructions", }, [ PPC970_PME_PM_EE_OFF_EXT_INT ] = { .pme_name = "PM_EE_OFF_EXT_INT", .pme_code = 0x337, .pme_short_desc = "Cycles MSR(EE) bit off and external interrupt pending", .pme_long_desc = "Cycles MSR(EE) bit off and external interrupt pending", }, [ PPC970_PME_PM_PMC6_OVERFLOW ] = { .pme_name = "PM_PMC6_OVERFLOW", .pme_code = 0x700a, .pme_short_desc = "PMC6 Overflow", .pme_long_desc = "PMC6 Overflow", }, [ PPC970_PME_PM_LSU_LRQ_FULL_CYC ] = { .pme_name = "PM_LSU_LRQ_FULL_CYC", .pme_code = 0x312, .pme_short_desc = "Cycles LRQ full", .pme_long_desc = "The ISU sends this signal when the LRQ is full.", }, [ PPC970_PME_PM_IC_PREF_INSTALL ] = { .pme_name = "PM_IC_PREF_INSTALL", .pme_code = 0x427, .pme_short_desc = "Instruction prefetched installed in prefetch", .pme_long_desc = "New line coming into the prefetch buffer", }, [ PPC970_PME_PM_DC_PREF_OUT_OF_STREAMS ] = { .pme_name = "PM_DC_PREF_OUT_OF_STREAMS", .pme_code = 0x732, .pme_short_desc = "D cache out of streams", .pme_long_desc = "out of streams", }, [ PPC970_PME_PM_MRK_LSU1_FLUSH_SRQ ] = { .pme_name = "PM_MRK_LSU1_FLUSH_SRQ", .pme_code = 0x717, .pme_short_desc = "LSU1 marked SRQ flushes", .pme_long_desc = "A marked store was flushed because younger load hits and older store that is already in the SRQ or in the same group.", }, [ PPC970_PME_PM_GCT_FULL_CYC ] = { .pme_name = "PM_GCT_FULL_CYC", .pme_code = 0x300, .pme_short_desc = "Cycles GCT full", .pme_long_desc = "The ISU sends a signal indicating the gct is full. ", }, [ PPC970_PME_PM_INST_FROM_MEM ] = { .pme_name = "PM_INST_FROM_MEM", .pme_code = 0x2426, .pme_short_desc = "Instruction fetched from memory", .pme_long_desc = "Instruction fetched from memory", }, [ PPC970_PME_PM_FLUSH_LSU_BR_MPRED ] = { .pme_name = "PM_FLUSH_LSU_BR_MPRED", .pme_code = 0x317, .pme_short_desc = "Flush caused by LSU or branch mispredict", .pme_long_desc = "Flush caused by LSU or branch mispredict", }, [ PPC970_PME_PM_FXU_BUSY ] = { .pme_name = "PM_FXU_BUSY", .pme_code = 0x6002, .pme_short_desc = "FXU busy", .pme_long_desc = "FXU0 and FXU1 are both busy", }, [ PPC970_PME_PM_ST_REF_L1_LSU1 ] = { .pme_name = "PM_ST_REF_L1_LSU1", .pme_code = 0x815, .pme_short_desc = "LSU1 L1 D cache store references", .pme_long_desc = "A store executed on unit 1", }, [ PPC970_PME_PM_MRK_LD_MISS_L1 ] = { .pme_name = "PM_MRK_LD_MISS_L1", .pme_code = 0x1720, .pme_short_desc = "Marked L1 D cache load misses", .pme_long_desc = "Marked L1 D cache load misses", }, [ PPC970_PME_PM_L1_WRITE_CYC ] = { .pme_name = "PM_L1_WRITE_CYC", .pme_code = 0x434, .pme_short_desc = "Cycles writing to instruction L1", .pme_long_desc = "This signal is asserted each cycle a cache write is active.", }, [ PPC970_PME_PM_LSU_REJECT_LMQ_FULL ] = { .pme_name = "PM_LSU_REJECT_LMQ_FULL", .pme_code = 0x2920, .pme_short_desc = "LSU reject due to LMQ full or missed data coming", .pme_long_desc = "LSU reject due to LMQ full or missed data coming", }, [ PPC970_PME_PM_FPU_ALL ] = { .pme_name = "PM_FPU_ALL", .pme_code = 0x5100, .pme_short_desc = "FPU executed add, mult, sub, cmp or sel instruction", .pme_long_desc = "This signal is active for one cycle when FPU is executing an add, mult, sub, compare, or fsel kind of instruction. This could be fadd*, fmul*, fsub*, fcmp**, fsel where XYZ* means XYZ, XYZs, XYZ., XYZs. and XYZ** means XYZu, XYZo. Combined Unit 0 + Unit 1", }, [ PPC970_PME_PM_LSU_SRQ_S0_ALLOC ] = { .pme_name = "PM_LSU_SRQ_S0_ALLOC", .pme_code = 0x825, .pme_short_desc = "SRQ slot 0 allocated", .pme_long_desc = "SRQ Slot zero was allocated", }, [ PPC970_PME_PM_INST_FROM_L25_SHR ] = { .pme_name = "PM_INST_FROM_L25_SHR", .pme_code = 0x5426, .pme_short_desc = "Instruction fetched from L2.5 shared", .pme_long_desc = "Instruction fetched from L2.5 shared", }, [ PPC970_PME_PM_GRP_MRK ] = { .pme_name = "PM_GRP_MRK", .pme_code = 0x5004, .pme_short_desc = "Group marked in IDU", .pme_long_desc = "A group was sampled (marked)", }, [ PPC970_PME_PM_BR_MPRED_CR ] = { .pme_name = "PM_BR_MPRED_CR", .pme_code = 0x432, .pme_short_desc = "Branch mispredictions due to CR bit setting", .pme_long_desc = "This signal is asserted when the branch execution unit detects a branch mispredict because the CR value is opposite of the predicted value. This signal is asserted after a branch issue event and will result in a branch redirect flush if not overridden by a flush of an older instruction.", }, [ PPC970_PME_PM_DC_PREF_STREAM_ALLOC ] = { .pme_name = "PM_DC_PREF_STREAM_ALLOC", .pme_code = 0x737, .pme_short_desc = "D cache new prefetch stream allocated", .pme_long_desc = "A new Prefetch Stream was allocated", }, [ PPC970_PME_PM_FPU1_FIN ] = { .pme_name = "PM_FPU1_FIN", .pme_code = 0x117, .pme_short_desc = "FPU1 produced a result", .pme_long_desc = "fp1 finished, produced a result. This only indicates finish, not completion. ", }, [ PPC970_PME_PM_LSU_REJECT_SRQ ] = { .pme_name = "PM_LSU_REJECT_SRQ", .pme_code = 0x1920, .pme_short_desc = "LSU SRQ rejects", .pme_long_desc = "LSU SRQ rejects", }, [ PPC970_PME_PM_BR_MPRED_TA ] = { .pme_name = "PM_BR_MPRED_TA", .pme_code = 0x433, .pme_short_desc = "Branch mispredictions due to target address", .pme_long_desc = "branch miss predict due to a target address prediction. This signal will be asserted each time the branch execution unit detects an incorrect target address prediction. This signal will be asserted after a valid branch execution unit issue and will cause a branch mispredict flush unless a flush is detected from an older instruction.", }, [ PPC970_PME_PM_CRQ_FULL_CYC ] = { .pme_name = "PM_CRQ_FULL_CYC", .pme_code = 0x311, .pme_short_desc = "Cycles CR issue queue full", .pme_long_desc = "The ISU sends a signal indicating that the issue queue that feeds the ifu cr unit cannot accept any more group (queue is full of groups).", }, [ PPC970_PME_PM_LD_MISS_L1 ] = { .pme_name = "PM_LD_MISS_L1", .pme_code = 0x3810, .pme_short_desc = "L1 D cache load misses", .pme_long_desc = "Total DL1 Load references that miss the DL1", }, [ PPC970_PME_PM_INST_FROM_PREF ] = { .pme_name = "PM_INST_FROM_PREF", .pme_code = 0x342d, .pme_short_desc = "Instructions fetched from prefetch", .pme_long_desc = "An instruction fetch group was fetched from the prefetch buffer. Fetch Groups can contain up to 8 instructions", }, [ PPC970_PME_PM_STCX_PASS ] = { .pme_name = "PM_STCX_PASS", .pme_code = 0x725, .pme_short_desc = "Stcx passes", .pme_long_desc = "A stcx (stwcx or stdcx) instruction was successful", }, [ PPC970_PME_PM_DC_INV_L2 ] = { .pme_name = "PM_DC_INV_L2", .pme_code = 0x817, .pme_short_desc = "L1 D cache entries invalidated from L2", .pme_long_desc = "A dcache invalidated was received from the L2 because a line in L2 was castout.", }, [ PPC970_PME_PM_LSU_SRQ_FULL_CYC ] = { .pme_name = "PM_LSU_SRQ_FULL_CYC", .pme_code = 0x313, .pme_short_desc = "Cycles SRQ full", .pme_long_desc = "The ISU sends this signal when the srq is full.", }, [ PPC970_PME_PM_LSU0_FLUSH_LRQ ] = { .pme_name = "PM_LSU0_FLUSH_LRQ", .pme_code = 0x802, .pme_short_desc = "LSU0 LRQ flushes", .pme_long_desc = "A load was flushed by unit 1 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.", }, [ PPC970_PME_PM_LSU_SRQ_S0_VALID ] = { .pme_name = "PM_LSU_SRQ_S0_VALID", .pme_code = 0x821, .pme_short_desc = "SRQ slot 0 valid", .pme_long_desc = "This signal is asserted every cycle that the Store Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin.", }, [ PPC970_PME_PM_LARX_LSU0 ] = { .pme_name = "PM_LARX_LSU0", .pme_code = 0x727, .pme_short_desc = "Larx executed on LSU0", .pme_long_desc = "A larx (lwarx or ldarx) was executed on side 0 (there is no coresponding unit 1 event since larx instructions can only execute on unit 0)", }, [ PPC970_PME_PM_GCT_EMPTY_CYC ] = { .pme_name = "PM_GCT_EMPTY_CYC", .pme_code = 0x1004, .pme_short_desc = "Cycles GCT empty", .pme_long_desc = "The Global Completion Table is completely empty", }, [ PPC970_PME_PM_FPU1_ALL ] = { .pme_name = "PM_FPU1_ALL", .pme_code = 0x107, .pme_short_desc = "FPU1 executed add, mult, sub, cmp or sel instruction", .pme_long_desc = "This signal is active for one cycle when fp1 is executing an add, mult, sub, compare, or fsel kind of instruction. This could be fadd*, fmul*, fsub*, fcmp**, fsel where XYZ* means XYZ, XYZs, XYZ., XYZs. and XYZ** means XYZu, XYZo", }, [ PPC970_PME_PM_FPU1_FSQRT ] = { .pme_name = "PM_FPU1_FSQRT", .pme_code = 0x106, .pme_short_desc = "FPU1 executed FSQRT instruction", .pme_long_desc = "This signal is active for one cycle at the end of the microcode executed when fp1 is executing a square root instruction. This could be fsqrt* where XYZ* means XYZ, XYZs, XYZ., XYZs.", }, [ PPC970_PME_PM_FPU_FIN ] = { .pme_name = "PM_FPU_FIN", .pme_code = 0x4110, .pme_short_desc = "FPU produced a result", .pme_long_desc = "FPU finished, produced a result This only indicates finish, not completion. Combined Unit 0 + Unit 1", }, [ PPC970_PME_PM_LSU_SRQ_STFWD ] = { .pme_name = "PM_LSU_SRQ_STFWD", .pme_code = 0x1820, .pme_short_desc = "SRQ store forwarded", .pme_long_desc = "Data from a store instruction was forwarded to a load", }, [ PPC970_PME_PM_MRK_LD_MISS_L1_LSU1 ] = { .pme_name = "PM_MRK_LD_MISS_L1_LSU1", .pme_code = 0x724, .pme_short_desc = "LSU1 L1 D cache load misses", .pme_long_desc = "A marked load, executing on unit 1, missed the dcache", }, [ PPC970_PME_PM_FXU0_FIN ] = { .pme_name = "PM_FXU0_FIN", .pme_code = 0x332, .pme_short_desc = "FXU0 produced a result", .pme_long_desc = "The Fixed Point unit 0 finished an instruction and produced a result", }, [ PPC970_PME_PM_MRK_FPU_FIN ] = { .pme_name = "PM_MRK_FPU_FIN", .pme_code = 0x7004, .pme_short_desc = "Marked instruction FPU processing finished", .pme_long_desc = "One of the Floating Point Units finished a marked instruction. Instructions that finish may not necessary complete", }, [ PPC970_PME_PM_PMC5_OVERFLOW ] = { .pme_name = "PM_PMC5_OVERFLOW", .pme_code = 0x600a, .pme_short_desc = "PMC5 Overflow", .pme_long_desc = "PMC5 Overflow", }, [ PPC970_PME_PM_SNOOP_TLBIE ] = { .pme_name = "PM_SNOOP_TLBIE", .pme_code = 0x703, .pme_short_desc = "Snoop TLBIE", .pme_long_desc = "A TLB miss for a data request occurred. Requests that miss the TLB may be retried until the instruction is in the next to complete group (unless HID4 is set to allow speculative tablewalks). This may result in multiple TLB misses for the same instruction.", }, [ PPC970_PME_PM_FPU1_FRSP_FCONV ] = { .pme_name = "PM_FPU1_FRSP_FCONV", .pme_code = 0x115, .pme_short_desc = "FPU1 executed FRSP or FCONV instructions", .pme_long_desc = "This signal is active for one cycle when fp1 is executing frsp or convert kind of instruction. This could be frsp*, fcfid*, fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs.", }, [ PPC970_PME_PM_FPU0_FDIV ] = { .pme_name = "PM_FPU0_FDIV", .pme_code = 0x100, .pme_short_desc = "FPU0 executed FDIV instruction", .pme_long_desc = "This signal is active for one cycle at the end of the microcode executed when fp0 is executing a divide instruction. This could be fdiv, fdivs, fdiv. fdivs.", }, [ PPC970_PME_PM_LD_REF_L1_LSU1 ] = { .pme_name = "PM_LD_REF_L1_LSU1", .pme_code = 0x814, .pme_short_desc = "LSU1 L1 D cache load references", .pme_long_desc = "A load executed on unit 1", }, [ PPC970_PME_PM_HV_CYC ] = { .pme_name = "PM_HV_CYC", .pme_code = 0x3004, .pme_short_desc = "Hypervisor Cycles", .pme_long_desc = "Cycles when the processor is executing in Hypervisor (MSR[HV] = 1 and MSR[PR]=0)", }, [ PPC970_PME_PM_LR_CTR_MAP_FULL_CYC ] = { .pme_name = "PM_LR_CTR_MAP_FULL_CYC", .pme_code = 0x306, .pme_short_desc = "Cycles LR/CTR mapper full", .pme_long_desc = "The ISU sends a signal indicating that the lr/ctr mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.", }, [ PPC970_PME_PM_FPU_DENORM ] = { .pme_name = "PM_FPU_DENORM", .pme_code = 0x1120, .pme_short_desc = "FPU received denormalized data", .pme_long_desc = "This signal is active for one cycle when one of the operands is denormalized. Combined Unit 0 + Unit 1", }, [ PPC970_PME_PM_LSU0_REJECT_SRQ ] = { .pme_name = "PM_LSU0_REJECT_SRQ", .pme_code = 0x920, .pme_short_desc = "LSU0 SRQ rejects", .pme_long_desc = "LSU0 SRQ rejects", }, [ PPC970_PME_PM_LSU1_REJECT_SRQ ] = { .pme_name = "PM_LSU1_REJECT_SRQ", .pme_code = 0x924, .pme_short_desc = "LSU1 SRQ rejects", .pme_long_desc = "LSU1 SRQ rejects", }, [ PPC970_PME_PM_LSU1_DERAT_MISS ] = { .pme_name = "PM_LSU1_DERAT_MISS", .pme_code = 0x706, .pme_short_desc = "LSU1 DERAT misses", .pme_long_desc = "A data request (load or store) from LSU Unit 1 missed the ERAT and resulted in an ERAT reload. Multiple instructions may miss the ERAT entry for the same 4K page, but only one reload will occur.", }, [ PPC970_PME_PM_IC_PREF_REQ ] = { .pme_name = "PM_IC_PREF_REQ", .pme_code = 0x426, .pme_short_desc = "Instruction prefetch requests", .pme_long_desc = "Asserted when a non-canceled prefetch is made to the cache interface unit (CIU).", }, [ PPC970_PME_PM_MRK_LSU_FIN ] = { .pme_name = "PM_MRK_LSU_FIN", .pme_code = 0x8004, .pme_short_desc = "Marked instruction LSU processing finished", .pme_long_desc = "One of the Load/Store Units finished a marked instruction. Instructions that finish may not necessary complete", }, [ PPC970_PME_PM_MRK_DATA_FROM_MEM ] = { .pme_name = "PM_MRK_DATA_FROM_MEM", .pme_code = 0x3937, .pme_short_desc = "Marked data loaded from memory", .pme_long_desc = "Marked data loaded from memory", }, [ PPC970_PME_PM_LSU0_FLUSH_UST ] = { .pme_name = "PM_LSU0_FLUSH_UST", .pme_code = 0x801, .pme_short_desc = "LSU0 unaligned store flushes", .pme_long_desc = "A store was flushed from unit 0 because it was unaligned (crossed a 4k boundary)", }, [ PPC970_PME_PM_LSU_FLUSH_LRQ ] = { .pme_name = "PM_LSU_FLUSH_LRQ", .pme_code = 0x6800, .pme_short_desc = "LRQ flushes", .pme_long_desc = "A load was flushed because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.", }, [ PPC970_PME_PM_LSU_FLUSH_SRQ ] = { .pme_name = "PM_LSU_FLUSH_SRQ", .pme_code = 0x5800, .pme_short_desc = "SRQ flushes", .pme_long_desc = "A store was flushed because younger load hits and older store that is already in the SRQ or in the same group.", } }; #endif libpfm-4.9.0/lib/events/intel_nhm_unc_events.h0000664000175000017500000010477713223402656021267 0ustar eranianeranian/* * Copyright (c) 2011 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * This file has been automatically generated. * * PMU: nhm_unc (Intel Nehalem uncore) */ static const intel_x86_umask_t nhm_unc_unc_dram_open[]={ { .uname = "CH0", .udesc = "DRAM Channel 0 open commands issued for read or write", .ucode = 0x100, }, { .uname = "CH1", .udesc = "DRAM Channel 1 open commands issued for read or write", .ucode = 0x200, }, { .uname = "CH2", .udesc = "DRAM Channel 2 open commands issued for read or write", .ucode = 0x400, }, }; static const intel_x86_umask_t nhm_unc_unc_dram_page_close[]={ { .uname = "CH0", .udesc = "DRAM Channel 0 page close", .ucode = 0x100, }, { .uname = "CH1", .udesc = "DRAM Channel 1 page close", .ucode = 0x200, }, { .uname = "CH2", .udesc = "DRAM Channel 2 page close", .ucode = 0x400, }, }; static const intel_x86_umask_t nhm_unc_unc_dram_page_miss[]={ { .uname = "CH0", .udesc = "DRAM Channel 0 page miss", .ucode = 0x100, }, { .uname = "CH1", .udesc = "DRAM Channel 1 page miss", .ucode = 0x200, }, { .uname = "CH2", .udesc = "DRAM Channel 2 page miss", .ucode = 0x400, }, }; static const intel_x86_umask_t nhm_unc_unc_dram_pre_all[]={ { .uname = "CH0", .udesc = "DRAM Channel 0 precharge all commands", .ucode = 0x100, }, { .uname = "CH1", .udesc = "DRAM Channel 1 precharge all commands", .ucode = 0x200, }, { .uname = "CH2", .udesc = "DRAM Channel 2 precharge all commands", .ucode = 0x400, }, }; static const intel_x86_umask_t nhm_unc_unc_dram_read_cas[]={ { .uname = "CH0", .udesc = "DRAM Channel 0 read CAS commands", .ucode = 0x100, }, { .uname = "AUTOPRE_CH0", .udesc = "DRAM Channel 0 read CAS auto page close commands", .ucode = 0x200, }, { .uname = "CH1", .udesc = "DRAM Channel 1 read CAS commands", .ucode = 0x400, }, { .uname = "AUTOPRE_CH1", .udesc = "DRAM Channel 1 read CAS auto page close commands", .ucode = 0x800, }, { .uname = "CH2", .udesc = "DRAM Channel 2 read CAS commands", .ucode = 0x1000, }, { .uname = "AUTOPRE_CH2", .udesc = "DRAM Channel 2 read CAS auto page close commands", .ucode = 0x2000, }, }; static const intel_x86_umask_t nhm_unc_unc_dram_refresh[]={ { .uname = "CH0", .udesc = "DRAM Channel 0 refresh commands", .ucode = 0x100, }, { .uname = "CH1", .udesc = "DRAM Channel 1 refresh commands", .ucode = 0x200, }, { .uname = "CH2", .udesc = "DRAM Channel 2 refresh commands", .ucode = 0x400, }, }; static const intel_x86_umask_t nhm_unc_unc_dram_write_cas[]={ { .uname = "CH0", .udesc = "DRAM Channel 0 write CAS commands", .ucode = 0x100, }, { .uname = "AUTOPRE_CH0", .udesc = "DRAM Channel 0 write CAS auto page close commands", .ucode = 0x200, }, { .uname = "CH1", .udesc = "DRAM Channel 1 write CAS commands", .ucode = 0x400, }, { .uname = "AUTOPRE_CH1", .udesc = "DRAM Channel 1 write CAS auto page close commands", .ucode = 0x800, }, { .uname = "CH2", .udesc = "DRAM Channel 2 write CAS commands", .ucode = 0x1000, }, { .uname = "AUTOPRE_CH2", .udesc = "DRAM Channel 2 write CAS auto page close commands", .ucode = 0x2000, }, }; static const intel_x86_umask_t nhm_unc_unc_gq_alloc[]={ { .uname = "READ_TRACKER", .udesc = "GQ read tracker requests", .ucode = 0x100, }, { .uname = "RT_LLC_MISS", .udesc = "GQ read tracker LLC misses", .ucode = 0x200, }, { .uname = "RT_TO_LLC_RESP", .udesc = "GQ read tracker LLC requests", .ucode = 0x400, }, { .uname = "RT_TO_RTID_ACQUIRED", .udesc = "GQ read tracker LLC miss to RTID acquired", .ucode = 0x800, }, { .uname = "WT_TO_RTID_ACQUIRED", .udesc = "GQ write tracker LLC miss to RTID acquired", .ucode = 0x1000, }, { .uname = "WRITE_TRACKER", .udesc = "GQ write tracker LLC misses", .ucode = 0x2000, }, { .uname = "PEER_PROBE_TRACKER", .udesc = "GQ peer probe tracker requests", .ucode = 0x4000, }, }; static const intel_x86_umask_t nhm_unc_unc_gq_cycles_full[]={ { .uname = "READ_TRACKER", .udesc = "Cycles GQ read tracker is full.", .ucode = 0x100, }, { .uname = "WRITE_TRACKER", .udesc = "Cycles GQ write tracker is full.", .ucode = 0x200, }, { .uname = "PEER_PROBE_TRACKER", .udesc = "Cycles GQ peer probe tracker is full.", .ucode = 0x400, }, }; static const intel_x86_umask_t nhm_unc_unc_gq_cycles_not_empty[]={ { .uname = "READ_TRACKER", .udesc = "Cycles GQ read tracker is busy", .ucode = 0x100, }, { .uname = "WRITE_TRACKER", .udesc = "Cycles GQ write tracker is busy", .ucode = 0x200, }, { .uname = "PEER_PROBE_TRACKER", .udesc = "Cycles GQ peer probe tracker is busy", .ucode = 0x400, }, }; static const intel_x86_umask_t nhm_unc_unc_gq_data_from[]={ { .uname = "QPI", .udesc = "Cycles GQ data is imported from Quickpath interface", .ucode = 0x100, }, { .uname = "QMC", .udesc = "Cycles GQ data is imported from Quickpath memory interface", .ucode = 0x200, }, { .uname = "LLC", .udesc = "Cycles GQ data is imported from LLC", .ucode = 0x400, }, { .uname = "CORES_02", .udesc = "Cycles GQ data is imported from Cores 0 and 2", .ucode = 0x800, }, { .uname = "CORES_13", .udesc = "Cycles GQ data is imported from Cores 1 and 3", .ucode = 0x1000, }, }; static const intel_x86_umask_t nhm_unc_unc_gq_data_to[]={ { .uname = "QPI_QMC", .udesc = "Cycles GQ data sent to the QPI or QMC", .ucode = 0x100, }, { .uname = "LLC", .udesc = "Cycles GQ data sent to LLC", .ucode = 0x200, }, { .uname = "CORES", .udesc = "Cycles GQ data sent to cores", .ucode = 0x400, }, }; static const intel_x86_umask_t nhm_unc_unc_llc_hits[]={ { .uname = "READ", .udesc = "Number of LLC read hits", .ucode = 0x100, }, { .uname = "WRITE", .udesc = "Number of LLC write hits", .ucode = 0x200, }, { .uname = "PROBE", .udesc = "Number of LLC peer probe hits", .ucode = 0x400, }, { .uname = "ANY", .udesc = "Number of LLC hits", .ucode = 0x300, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t nhm_unc_unc_llc_lines_in[]={ { .uname = "M_STATE", .udesc = "LLC lines allocated in M state", .ucode = 0x100, }, { .uname = "E_STATE", .udesc = "LLC lines allocated in E state", .ucode = 0x200, }, { .uname = "S_STATE", .udesc = "LLC lines allocated in S state", .ucode = 0x400, }, { .uname = "F_STATE", .udesc = "LLC lines allocated in F state", .ucode = 0x800, }, { .uname = "ANY", .udesc = "LLC lines allocated", .ucode = 0xf00, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t nhm_unc_unc_llc_lines_out[]={ { .uname = "M_STATE", .udesc = "LLC lines victimized in M state", .ucode = 0x100, }, { .uname = "E_STATE", .udesc = "LLC lines victimized in E state", .ucode = 0x200, }, { .uname = "S_STATE", .udesc = "LLC lines victimized in S state", .ucode = 0x400, }, { .uname = "I_STATE", .udesc = "LLC lines victimized in I state", .ucode = 0x800, }, { .uname = "F_STATE", .udesc = "LLC lines victimized in F state", .ucode = 0x1000, }, { .uname = "ANY", .udesc = "LLC lines victimized", .ucode = 0x1f00, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t nhm_unc_unc_llc_miss[]={ { .uname = "READ", .udesc = "Number of LLC read misses", .ucode = 0x100, }, { .uname = "WRITE", .udesc = "Number of LLC write misses", .ucode = 0x200, }, { .uname = "PROBE", .udesc = "Number of LLC peer probe misses", .ucode = 0x400, }, { .uname = "ANY", .udesc = "Number of LLC misses", .ucode = 0x300, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t nhm_unc_unc_qhl_address_conflicts[]={ { .uname = "2WAY", .udesc = "QHL 2 way address conflicts", .ucode = 0x200, }, { .uname = "3WAY", .udesc = "QHL 3 way address conflicts", .ucode = 0x400, }, }; static const intel_x86_umask_t nhm_unc_unc_qhl_conflict_cycles[]={ { .uname = "IOH", .udesc = "QHL IOH Tracker conflict cycles", .ucode = 0x100, }, { .uname = "REMOTE", .udesc = "QHL Remote Tracker conflict cycles", .ucode = 0x200, }, { .uname = "LOCAL", .udesc = "QHL Local Tracker conflict cycles", .ucode = 0x400, }, }; static const intel_x86_umask_t nhm_unc_unc_qhl_cycles_full[]={ { .uname = "REMOTE", .udesc = "Cycles QHL Remote Tracker is full", .ucode = 0x200, }, { .uname = "LOCAL", .udesc = "Cycles QHL Local Tracker is full", .ucode = 0x400, }, { .uname = "IOH", .udesc = "Cycles QHL IOH Tracker is full", .ucode = 0x100, }, }; static const intel_x86_umask_t nhm_unc_unc_qhl_cycles_not_empty[]={ { .uname = "IOH", .udesc = "Cycles QHL IOH is busy", .ucode = 0x100, }, { .uname = "REMOTE", .udesc = "Cycles QHL Remote Tracker is busy", .ucode = 0x200, }, { .uname = "LOCAL", .udesc = "Cycles QHL Local Tracker is busy", .ucode = 0x400, }, }; static const intel_x86_umask_t nhm_unc_unc_qhl_frc_ack_cnflts[]={ { .uname = "LOCAL", .udesc = "QHL FrcAckCnflts sent to local home", .ucode = 0x400, .uflags= INTEL_X86_DFL, }, }; static const intel_x86_umask_t nhm_unc_unc_qhl_occupancy[]={ { .uname = "IOH", .udesc = "Cycles QHL IOH Tracker Allocate to Deallocate Read Occupancy", .ucode = 0x100, }, { .uname = "REMOTE", .udesc = "Cycles QHL Remote Tracker Allocate to Deallocate Read Occupancy", .ucode = 0x200, }, { .uname = "LOCAL", .udesc = "Cycles QHL Local Tracker Allocate to Deallocate Read Occupancy", .ucode = 0x400, }, }; static const intel_x86_umask_t nhm_unc_unc_qhl_requests[]={ { .uname = "LOCAL_READS", .udesc = "Quickpath Home Logic local read requests", .ucode = 0x1000, }, { .uname = "LOCAL_WRITES", .udesc = "Quickpath Home Logic local write requests", .ucode = 0x2000, }, { .uname = "REMOTE_READS", .udesc = "Quickpath Home Logic remote read requests", .ucode = 0x400, }, { .uname = "IOH_READS", .udesc = "Quickpath Home Logic IOH read requests", .ucode = 0x100, }, { .uname = "IOH_WRITES", .udesc = "Quickpath Home Logic IOH write requests", .ucode = 0x200, }, { .uname = "REMOTE_WRITES", .udesc = "Quickpath Home Logic remote write requests", .ucode = 0x800, }, }; static const intel_x86_umask_t nhm_unc_unc_qmc_busy[]={ { .uname = "READ_CH0", .udesc = "Cycles QMC channel 0 busy with a read request", .ucode = 0x100, }, { .uname = "READ_CH1", .udesc = "Cycles QMC channel 1 busy with a read request", .ucode = 0x200, }, { .uname = "READ_CH2", .udesc = "Cycles QMC channel 2 busy with a read request", .ucode = 0x400, }, { .uname = "WRITE_CH0", .udesc = "Cycles QMC channel 0 busy with a write request", .ucode = 0x800, }, { .uname = "WRITE_CH1", .udesc = "Cycles QMC channel 1 busy with a write request", .ucode = 0x1000, }, { .uname = "WRITE_CH2", .udesc = "Cycles QMC channel 2 busy with a write request", .ucode = 0x2000, }, }; static const intel_x86_umask_t nhm_unc_unc_qmc_cancel[]={ { .uname = "CH0", .udesc = "QMC channel 0 cancels", .ucode = 0x100, }, { .uname = "CH1", .udesc = "QMC channel 1 cancels", .ucode = 0x200, }, { .uname = "CH2", .udesc = "QMC channel 2 cancels", .ucode = 0x400, }, { .uname = "ANY", .udesc = "QMC cancels", .ucode = 0x700, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t nhm_unc_unc_qmc_critical_priority_reads[]={ { .uname = "CH0", .udesc = "QMC channel 0 critical priority read requests", .ucode = 0x100, }, { .uname = "CH1", .udesc = "QMC channel 1 critical priority read requests", .ucode = 0x200, }, { .uname = "CH2", .udesc = "QMC channel 2 critical priority read requests", .ucode = 0x400, }, { .uname = "ANY", .udesc = "QMC critical priority read requests", .ucode = 0x700, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t nhm_unc_unc_qmc_high_priority_reads[]={ { .uname = "CH0", .udesc = "QMC channel 0 high priority read requests", .ucode = 0x100, }, { .uname = "CH1", .udesc = "QMC channel 1 high priority read requests", .ucode = 0x200, }, { .uname = "CH2", .udesc = "QMC channel 2 high priority read requests", .ucode = 0x400, }, { .uname = "ANY", .udesc = "QMC high priority read requests", .ucode = 0x700, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t nhm_unc_unc_qmc_isoc_full[]={ { .uname = "READ_CH0", .udesc = "Cycles DRAM channel 0 full with isochronous read requests", .ucode = 0x100, }, { .uname = "READ_CH1", .udesc = "Cycles DRAM channel 1 full with isochronous read requests", .ucode = 0x200, }, { .uname = "READ_CH2", .udesc = "Cycles DRAM channel 2 full with isochronous read requests", .ucode = 0x400, }, { .uname = "WRITE_CH0", .udesc = "Cycles DRAM channel 0 full with isochronous write requests", .ucode = 0x800, }, { .uname = "WRITE_CH1", .udesc = "Cycles DRAM channel 1 full with isochronous write requests", .ucode = 0x1000, }, { .uname = "WRITE_CH2", .udesc = "Cycles DRAM channel 2 full with isochronous write requests", .ucode = 0x2000, }, }; static const intel_x86_umask_t nhm_unc_unc_imc_isoc_occupancy[]={ { .uname = "CH0", .udesc = "IMC channel 0 isochronous read request occupancy", .ucode = 0x100, }, { .uname = "CH1", .udesc = "IMC channel 1 isochronous read request occupancy", .ucode = 0x200, }, { .uname = "CH2", .udesc = "IMC channel 2 isochronous read request occupancy", .ucode = 0x400, }, { .uname = "ANY", .udesc = "IMC isochronous read request occupancy", .ucode = 0x700, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t nhm_unc_unc_qmc_normal_full[]={ { .uname = "READ_CH0", .udesc = "Cycles DRAM channel 0 full with normal read requests", .ucode = 0x100, }, { .uname = "READ_CH1", .udesc = "Cycles DRAM channel 1 full with normal read requests", .ucode = 0x200, }, { .uname = "READ_CH2", .udesc = "Cycles DRAM channel 2 full with normal read requests", .ucode = 0x400, }, { .uname = "WRITE_CH0", .udesc = "Cycles DRAM channel 0 full with normal write requests", .ucode = 0x800, }, { .uname = "WRITE_CH1", .udesc = "Cycles DRAM channel 1 full with normal write requests", .ucode = 0x1000, }, { .uname = "WRITE_CH2", .udesc = "Cycles DRAM channel 2 full with normal write requests", .ucode = 0x2000, }, }; static const intel_x86_umask_t nhm_unc_unc_qmc_normal_reads[]={ { .uname = "CH0", .udesc = "QMC channel 0 normal read requests", .ucode = 0x100, }, { .uname = "CH1", .udesc = "QMC channel 1 normal read requests", .ucode = 0x200, }, { .uname = "CH2", .udesc = "QMC channel 2 normal read requests", .ucode = 0x400, }, { .uname = "ANY", .udesc = "QMC normal read requests", .ucode = 0x700, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t nhm_unc_unc_qmc_occupancy[]={ { .uname = "CH0", .udesc = "IMC channel 0 normal read request occupancy", .ucode = 0x100, }, { .uname = "CH1", .udesc = "IMC channel 1 normal read request occupancy", .ucode = 0x200, }, { .uname = "CH2", .udesc = "IMC channel 2 normal read request occupancy", .ucode = 0x400, }, }; static const intel_x86_umask_t nhm_unc_unc_qmc_priority_updates[]={ { .uname = "CH0", .udesc = "QMC channel 0 priority updates", .ucode = 0x100, }, { .uname = "CH1", .udesc = "QMC channel 1 priority updates", .ucode = 0x200, }, { .uname = "CH2", .udesc = "QMC channel 2 priority updates", .ucode = 0x400, }, { .uname = "ANY", .udesc = "QMC priority updates", .ucode = 0x700, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t nhm_unc_unc_qmc_writes[]={ { .uname = "FULL_CH0", .udesc = "QMC channel 0 full cache line writes", .ucode = 0x100, .grpid = 0, }, { .uname = "FULL_CH1", .udesc = "QMC channel 1 full cache line writes", .ucode = 0x200, .grpid = 0, }, { .uname = "FULL_CH2", .udesc = "QMC channel 2 full cache line writes", .ucode = 0x400, .grpid = 0, }, { .uname = "FULL_ANY", .udesc = "QMC full cache line writes", .ucode = 0x700, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, .grpid = 0, }, { .uname = "PARTIAL_CH0", .udesc = "QMC channel 0 partial cache line writes", .ucode = 0x800, .grpid = 1, }, { .uname = "PARTIAL_CH1", .udesc = "QMC channel 1 partial cache line writes", .ucode = 0x1000, .grpid = 1, }, { .uname = "PARTIAL_CH2", .udesc = "QMC channel 2 partial cache line writes", .ucode = 0x2000, .grpid = 1, }, { .uname = "PARTIAL_ANY", .udesc = "QMC partial cache line writes", .ucode = 0x3800, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, .grpid = 1, }, }; static const intel_x86_umask_t nhm_unc_unc_qpi_rx_no_ppt_credit[]={ { .uname = "STALLS_LINK_0", .udesc = "Link 0 snoop stalls due to no PPT entry", .ucode = 0x100, }, { .uname = "STALLS_LINK_1", .udesc = "Link 1 snoop stalls due to no PPT entry", .ucode = 0x200, }, }; static const intel_x86_umask_t nhm_unc_unc_qpi_tx_header[]={ { .uname = "BUSY_LINK_0", .udesc = "Cycles link 0 outbound header busy", .ucode = 0x200, }, { .uname = "BUSY_LINK_1", .udesc = "Cycles link 1 outbound header busy", .ucode = 0x800, }, }; static const intel_x86_umask_t nhm_unc_unc_qpi_tx_stalled_multi_flit[]={ { .uname = "DRS_LINK_0", .udesc = "Cycles QPI outbound link 0 DRS stalled", .ucode = 0x100, }, { .uname = "NCB_LINK_0", .udesc = "Cycles QPI outbound link 0 NCB stalled", .ucode = 0x200, }, { .uname = "NCS_LINK_0", .udesc = "Cycles QPI outbound link 0 NCS stalled", .ucode = 0x400, }, { .uname = "DRS_LINK_1", .udesc = "Cycles QPI outbound link 1 DRS stalled", .ucode = 0x800, }, { .uname = "NCB_LINK_1", .udesc = "Cycles QPI outbound link 1 NCB stalled", .ucode = 0x1000, }, { .uname = "NCS_LINK_1", .udesc = "Cycles QPI outbound link 1 NCS stalled", .ucode = 0x2000, }, { .uname = "LINK_0", .udesc = "Cycles QPI outbound link 0 multi flit stalled", .ucode = 0x700, .uflags= INTEL_X86_NCOMBO, }, { .uname = "LINK_1", .udesc = "Cycles QPI outbound link 1 multi flit stalled", .ucode = 0x3800, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t nhm_unc_unc_qpi_tx_stalled_single_flit[]={ { .uname = "HOME_LINK_0", .udesc = "Cycles QPI outbound link 0 HOME stalled", .ucode = 0x100, }, { .uname = "SNOOP_LINK_0", .udesc = "Cycles QPI outbound link 0 SNOOP stalled", .ucode = 0x200, }, { .uname = "NDR_LINK_0", .udesc = "Cycles QPI outbound link 0 NDR stalled", .ucode = 0x400, }, { .uname = "HOME_LINK_1", .udesc = "Cycles QPI outbound link 1 HOME stalled", .ucode = 0x800, }, { .uname = "SNOOP_LINK_1", .udesc = "Cycles QPI outbound link 1 SNOOP stalled", .ucode = 0x1000, }, { .uname = "NDR_LINK_1", .udesc = "Cycles QPI outbound link 1 NDR stalled", .ucode = 0x2000, }, { .uname = "LINK_0", .udesc = "Cycles QPI outbound link 0 single flit stalled", .ucode = 0x700, .uflags= INTEL_X86_NCOMBO, }, { .uname = "LINK_1", .udesc = "Cycles QPI outbound link 1 single flit stalled", .ucode = 0x3800, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t nhm_unc_unc_snp_resp_to_local_home[]={ { .uname = "I_STATE", .udesc = "Local home snoop response - LLC does not have cache line", .ucode = 0x100, }, { .uname = "S_STATE", .udesc = "Local home snoop response - LLC has cache line in S state", .ucode = 0x200, }, { .uname = "FWD_S_STATE", .udesc = "Local home snoop response - LLC forwarding cache line in S state.", .ucode = 0x400, }, { .uname = "FWD_I_STATE", .udesc = "Local home snoop response - LLC has forwarded a modified cache line", .ucode = 0x800, }, { .uname = "CONFLICT", .udesc = "Local home conflict snoop response", .ucode = 0x1000, }, { .uname = "WB", .udesc = "Local home snoop response - LLC has cache line in the M state", .ucode = 0x2000, }, }; static const intel_x86_umask_t nhm_unc_unc_snp_resp_to_remote_home[]={ { .uname = "I_STATE", .udesc = "Remote home snoop response - LLC does not have cache line", .ucode = 0x100, }, { .uname = "S_STATE", .udesc = "Remote home snoop response - LLC has cache line in S state", .ucode = 0x200, }, { .uname = "FWD_S_STATE", .udesc = "Remote home snoop response - LLC forwarding cache line in S state.", .ucode = 0x400, }, { .uname = "FWD_I_STATE", .udesc = "Remote home snoop response - LLC has forwarded a modified cache line", .ucode = 0x800, }, { .uname = "CONFLICT", .udesc = "Remote home conflict snoop response", .ucode = 0x1000, }, { .uname = "WB", .udesc = "Remote home snoop response - LLC has cache line in the M state", .ucode = 0x2000, }, { .uname = "HITM", .udesc = "Remote home snoop response - LLC HITM", .ucode = 0x2400, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_entry_t intel_nhm_unc_pe[]={ { .name = "UNC_CLK_UNHALTED", .desc = "Uncore clockticks.", .modmsk =0x0, .cntmsk = 0x100000, .code = 0xff, .flags = INTEL_X86_FIXED, }, { .name = "UNC_DRAM_OPEN", .desc = "DRAM open commands issued for read or write", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x60, .numasks = LIBPFM_ARRAY_SIZE(nhm_unc_unc_dram_open), .ngrp = 1, .umasks = nhm_unc_unc_dram_open, }, { .name = "UNC_DRAM_PAGE_CLOSE", .desc = "DRAM page close due to idle timer expiration", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x61, .numasks = LIBPFM_ARRAY_SIZE(nhm_unc_unc_dram_page_close), .ngrp = 1, .umasks = nhm_unc_unc_dram_page_close, }, { .name = "UNC_DRAM_PAGE_MISS", .desc = "DRAM Channel 0 page miss", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x62, .numasks = LIBPFM_ARRAY_SIZE(nhm_unc_unc_dram_page_miss), .ngrp = 1, .umasks = nhm_unc_unc_dram_page_miss, }, { .name = "UNC_DRAM_PRE_ALL", .desc = "DRAM Channel 0 precharge all commands", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x66, .numasks = LIBPFM_ARRAY_SIZE(nhm_unc_unc_dram_pre_all), .ngrp = 1, .umasks = nhm_unc_unc_dram_pre_all, }, { .name = "UNC_DRAM_READ_CAS", .desc = "DRAM Channel 0 read CAS commands", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x63, .numasks = LIBPFM_ARRAY_SIZE(nhm_unc_unc_dram_read_cas), .ngrp = 1, .umasks = nhm_unc_unc_dram_read_cas, }, { .name = "UNC_DRAM_REFRESH", .desc = "DRAM Channel 0 refresh commands", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x65, .numasks = LIBPFM_ARRAY_SIZE(nhm_unc_unc_dram_refresh), .ngrp = 1, .umasks = nhm_unc_unc_dram_refresh, }, { .name = "UNC_DRAM_WRITE_CAS", .desc = "DRAM Channel 0 write CAS commands", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x64, .numasks = LIBPFM_ARRAY_SIZE(nhm_unc_unc_dram_write_cas), .ngrp = 1, .umasks = nhm_unc_unc_dram_write_cas, }, { .name = "UNC_GQ_ALLOC", .desc = "GQ read tracker requests", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x3, .numasks = LIBPFM_ARRAY_SIZE(nhm_unc_unc_gq_alloc), .ngrp = 1, .umasks = nhm_unc_unc_gq_alloc, }, { .name = "UNC_GQ_CYCLES_FULL", .desc = "Cycles GQ read tracker is full.", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x0, .numasks = LIBPFM_ARRAY_SIZE(nhm_unc_unc_gq_cycles_full), .ngrp = 1, .umasks = nhm_unc_unc_gq_cycles_full, }, { .name = "UNC_GQ_CYCLES_NOT_EMPTY", .desc = "Cycles GQ read tracker is busy", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x1, .numasks = LIBPFM_ARRAY_SIZE(nhm_unc_unc_gq_cycles_not_empty), .ngrp = 1, .umasks = nhm_unc_unc_gq_cycles_not_empty, }, { .name = "UNC_GQ_DATA_FROM", .desc = "Cycles GQ data is imported", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x4, .numasks = LIBPFM_ARRAY_SIZE(nhm_unc_unc_gq_data_from), .ngrp = 1, .umasks = nhm_unc_unc_gq_data_from, }, { .name = "UNC_GQ_DATA_TO", .desc = "Cycles GQ data is exported", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x5, .numasks = LIBPFM_ARRAY_SIZE(nhm_unc_unc_gq_data_to), .ngrp = 1, .umasks = nhm_unc_unc_gq_data_to, }, { .name = "UNC_LLC_HITS", .desc = "Number of LLC read hits", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x8, .numasks = LIBPFM_ARRAY_SIZE(nhm_unc_unc_llc_hits), .ngrp = 1, .umasks = nhm_unc_unc_llc_hits, }, { .name = "UNC_LLC_LINES_IN", .desc = "LLC lines allocated in M state", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0xa, .numasks = LIBPFM_ARRAY_SIZE(nhm_unc_unc_llc_lines_in), .ngrp = 1, .umasks = nhm_unc_unc_llc_lines_in, }, { .name = "UNC_LLC_LINES_OUT", .desc = "LLC lines victimized in M state", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0xb, .numasks = LIBPFM_ARRAY_SIZE(nhm_unc_unc_llc_lines_out), .ngrp = 1, .umasks = nhm_unc_unc_llc_lines_out, }, { .name = "UNC_LLC_MISS", .desc = "Number of LLC read misses", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x9, .numasks = LIBPFM_ARRAY_SIZE(nhm_unc_unc_llc_miss), .ngrp = 1, .umasks = nhm_unc_unc_llc_miss, }, { .name = "UNC_QHL_ADDRESS_CONFLICTS", .desc = "QHL 2 way address conflicts", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x24, .numasks = LIBPFM_ARRAY_SIZE(nhm_unc_unc_qhl_address_conflicts), .ngrp = 1, .umasks = nhm_unc_unc_qhl_address_conflicts, }, { .name = "UNC_QHL_CONFLICT_CYCLES", .desc = "QHL IOH Tracker conflict cycles", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x25, .numasks = LIBPFM_ARRAY_SIZE(nhm_unc_unc_qhl_conflict_cycles), .ngrp = 1, .umasks = nhm_unc_unc_qhl_conflict_cycles, }, { .name = "UNC_QHL_CYCLES_FULL", .desc = "Cycles QHL Remote Tracker is full", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x21, .numasks = LIBPFM_ARRAY_SIZE(nhm_unc_unc_qhl_cycles_full), .ngrp = 1, .umasks = nhm_unc_unc_qhl_cycles_full, }, { .name = "UNC_QHL_CYCLES_NOT_EMPTY", .desc = "Cycles QHL Tracker is not empty", .modmsk =0x0, .cntmsk = 0x1fe00000, .code = 0x22, .numasks = LIBPFM_ARRAY_SIZE(nhm_unc_unc_qhl_cycles_not_empty), .ngrp = 1, .umasks = nhm_unc_unc_qhl_cycles_not_empty, }, { .name = "UNC_QHL_FRC_ACK_CNFLTS", .desc = "QHL FrcAckCnflts sent to local home", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x33, .numasks = LIBPFM_ARRAY_SIZE(nhm_unc_unc_qhl_frc_ack_cnflts), .ngrp = 1, .umasks = nhm_unc_unc_qhl_frc_ack_cnflts, }, { .name = "UNC_QHL_OCCUPANCY", .desc = "Cycles QHL Tracker Allocate to Deallocate Read Occupancy", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x23, .numasks = LIBPFM_ARRAY_SIZE(nhm_unc_unc_qhl_occupancy), .ngrp = 1, .umasks = nhm_unc_unc_qhl_occupancy, }, { .name = "UNC_QHL_REQUESTS", .desc = "Quickpath Home Logic local read requests", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x20, .numasks = LIBPFM_ARRAY_SIZE(nhm_unc_unc_qhl_requests), .ngrp = 1, .umasks = nhm_unc_unc_qhl_requests, }, { .name = "UNC_QHL_TO_QMC_BYPASS", .desc = "Number of requests to QMC that bypass QHL", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x26, }, { .name = "UNC_QMC_BUSY", .desc = "Cycles QMC busy with a read request", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x29, .numasks = LIBPFM_ARRAY_SIZE(nhm_unc_unc_qmc_busy), .ngrp = 1, .umasks = nhm_unc_unc_qmc_busy, }, { .name = "UNC_QMC_CANCEL", .desc = "QMC cancels", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x30, .numasks = LIBPFM_ARRAY_SIZE(nhm_unc_unc_qmc_cancel), .ngrp = 1, .umasks = nhm_unc_unc_qmc_cancel, }, { .name = "UNC_QMC_CRITICAL_PRIORITY_READS", .desc = "QMC critical priority read requests", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x2e, .numasks = LIBPFM_ARRAY_SIZE(nhm_unc_unc_qmc_critical_priority_reads), .ngrp = 1, .umasks = nhm_unc_unc_qmc_critical_priority_reads, }, { .name = "UNC_QMC_HIGH_PRIORITY_READS", .desc = "QMC high priority read requests", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x2d, .numasks = LIBPFM_ARRAY_SIZE(nhm_unc_unc_qmc_high_priority_reads), .ngrp = 1, .umasks = nhm_unc_unc_qmc_high_priority_reads, }, { .name = "UNC_QMC_ISOC_FULL", .desc = "Cycles DRAM full with isochronous (ISOC) read requests", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x28, .numasks = LIBPFM_ARRAY_SIZE(nhm_unc_unc_qmc_isoc_full), .ngrp = 1, .umasks = nhm_unc_unc_qmc_isoc_full, }, { .name = "UNC_IMC_ISOC_OCCUPANCY", .desc = "IMC isochronous (ISOC) Read Occupancy", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x2b, .numasks = LIBPFM_ARRAY_SIZE(nhm_unc_unc_imc_isoc_occupancy), .ngrp = 1, .umasks = nhm_unc_unc_imc_isoc_occupancy, }, { .name = "UNC_QMC_NORMAL_FULL", .desc = "Cycles DRAM full with normal read requests", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x27, .numasks = LIBPFM_ARRAY_SIZE(nhm_unc_unc_qmc_normal_full), .ngrp = 1, .umasks = nhm_unc_unc_qmc_normal_full, }, { .name = "UNC_QMC_NORMAL_READS", .desc = "QMC normal read requests", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x2c, .numasks = LIBPFM_ARRAY_SIZE(nhm_unc_unc_qmc_normal_reads), .ngrp = 1, .umasks = nhm_unc_unc_qmc_normal_reads, }, { .name = "UNC_QMC_OCCUPANCY", .desc = "QMC Occupancy", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x2a, .numasks = LIBPFM_ARRAY_SIZE(nhm_unc_unc_qmc_occupancy), .ngrp = 1, .umasks = nhm_unc_unc_qmc_occupancy, }, { .name = "UNC_QMC_PRIORITY_UPDATES", .desc = "QMC priority updates", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x31, .numasks = LIBPFM_ARRAY_SIZE(nhm_unc_unc_qmc_priority_updates), .ngrp = 1, .umasks = nhm_unc_unc_qmc_priority_updates, }, { .name = "UNC_QMC_WRITES", .desc = "QMC cache line writes", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x2f, .flags= INTEL_X86_GRP_EXCL, .numasks = LIBPFM_ARRAY_SIZE(nhm_unc_unc_qmc_writes), .ngrp = 2, .umasks = nhm_unc_unc_qmc_writes, }, { .name = "UNC_QPI_RX_NO_PPT_CREDIT", .desc = "Link 0 snoop stalls due to no PPT entry", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x43, .numasks = LIBPFM_ARRAY_SIZE(nhm_unc_unc_qpi_rx_no_ppt_credit), .ngrp = 1, .umasks = nhm_unc_unc_qpi_rx_no_ppt_credit, }, { .name = "UNC_QPI_TX_HEADER", .desc = "Cycles link 0 outbound header busy", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x42, .numasks = LIBPFM_ARRAY_SIZE(nhm_unc_unc_qpi_tx_header), .ngrp = 1, .umasks = nhm_unc_unc_qpi_tx_header, }, { .name = "UNC_QPI_TX_STALLED_MULTI_FLIT", .desc = "Cycles QPI outbound stalls", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x41, .numasks = LIBPFM_ARRAY_SIZE(nhm_unc_unc_qpi_tx_stalled_multi_flit), .ngrp = 1, .umasks = nhm_unc_unc_qpi_tx_stalled_multi_flit, }, { .name = "UNC_QPI_TX_STALLED_SINGLE_FLIT", .desc = "Cycles QPI outbound link stalls", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x40, .numasks = LIBPFM_ARRAY_SIZE(nhm_unc_unc_qpi_tx_stalled_single_flit), .ngrp = 1, .umasks = nhm_unc_unc_qpi_tx_stalled_single_flit, }, { .name = "UNC_SNP_RESP_TO_LOCAL_HOME", .desc = "Local home snoop response", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x6, .numasks = LIBPFM_ARRAY_SIZE(nhm_unc_unc_snp_resp_to_local_home), .ngrp = 1, .umasks = nhm_unc_unc_snp_resp_to_local_home, }, { .name = "UNC_SNP_RESP_TO_REMOTE_HOME", .desc = "Remote home snoop response", .modmsk = NHM_UNC_ATTRS, .cntmsk = 0x1fe00000, .code = 0x7, .numasks = LIBPFM_ARRAY_SIZE(nhm_unc_unc_snp_resp_to_remote_home), .ngrp = 1, .umasks = nhm_unc_unc_snp_resp_to_remote_home, }, }; libpfm-4.9.0/lib/events/intel_hswep_unc_irp_events.h0000664000175000017500000002233213223402656022467 0ustar eranianeranian/* * Copyright (c) 2014 Google Inc. All rights reserved * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * PMU: hswep_unc_irp (Intel Haswell-EP IRP uncore) */ static const intel_x86_umask_t hswep_unc_i_cache_ack_pending_occupancy[]={ { .uname = "ANY", .udesc = "Any source", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "SOURCE", .udesc = "Track all requests from any source port", .ucode = 0x200, }, }; static const intel_x86_umask_t hswep_unc_i_coherent_ops[]={ { .uname = "PCIRDCUR", .udesc = "PCI read current", .ucode = 0x100, }, { .uname = "CRD", .udesc = "CRD", .ucode = 0x200, }, { .uname = "DRD", .udesc = "DRD", .ucode = 0x400, }, { .uname = "RFO", .udesc = "RFO", .ucode = 0x800, }, { .uname = "PCITOM", .udesc = "DRITOM", .ucode = 0x1000, }, { .uname = "PCIDCAHINT", .udesc = "PCIDCAHINT", .ucode = 0x2000, }, { .uname = "WBMTOI", .udesc = "WBMTOI", .ucode = 0x4000, }, { .uname = "CFLUSH", .udesc = "CFLUSH", .ucode = 0x8000, }, }; static const intel_x86_umask_t hswep_unc_i_misc0[]={ { .uname = "FAST_REQ", .udesc = "Fastpath requests", .ucode = 0x100, }, { .uname = "FAST_REJ", .udesc = "Fastpath rejects", .ucode = 0x200, }, { .uname = "2ND_RD_INSERT", .udesc = "Cache insert of read transaction as secondary", .ucode = 0x400, }, { .uname = "2ND_WR_INSERT", .udesc = "Cache insert of write transaction as secondary", .ucode = 0x800, }, { .uname = "2ND_ATOMIC_INSERT", .udesc = "Cache insert of atomic transaction as secondary", .ucode = 0x1000, }, { .uname = "FAST_XFER", .udesc = "Fastpath trasnfers from primary to secondary", .ucode = 0x2000, }, { .uname = "PF_ACK_HINT", .udesc = "Prefetch ack hints from primary to secondary", .ucode = 0x4000, }, { .uname = "PF_TIMEOUT", .udesc = "Prefetch timeout", .ucode = 0x8000, }, }; static const intel_x86_umask_t hswep_unc_i_misc1[]={ { .uname = "SLOW_I", .udesc = "Slow transfer of I-state cacheline", .ucode = 0x100, }, { .uname = "SLOW_S", .udesc = "Slow transfer of S-state cacheline", .ucode = 0x200, }, { .uname = "SLOW_E", .udesc = "Slow transfer of e-state cacheline", .ucode = 0x400, }, { .uname = "SLOW_M", .udesc = "Slow transfer of M-state cacheline", .ucode = 0x800, }, { .uname = "LOST_FWD", .udesc = "LOST forwards", .ucode = 0x1000, }, { .uname = "SEC_RCVD_INVLD", .udesc = "Received Invalid", .ucode = 0x2000, }, { .uname = "SEC_RCVD_VLD", .udesc = "Received Valid", .ucode = 0x4000, }, { .uname = "DATA_THROTTLE", .udesc = "Data throttled", .ucode = 0x8000, }, }; static const intel_x86_umask_t hswep_unc_i_snoop_resp[]={ { .uname = "MISS", .udesc = "Miss", .ucode = 0x100, }, { .uname = "HIT_I", .udesc = "Hit in Invalid state", .ucode = 0x200, }, { .uname = "HIT_ES", .udesc = "Hit in Exclusive or Shared state", .ucode = 0x400, }, { .uname = "HIT_M", .udesc = "Hit in Modified state", .ucode = 0x800, }, { .uname = "SNPCODE", .udesc = "Snoop Code", .ucode = 0x1000, }, { .uname = "SNPDATA", .udesc = "Snoop Data", .ucode = 0x2000, }, { .uname = "SNPINV", .udesc = "Snoop Invalid", .ucode = 0x4000, }, }; static const intel_x86_umask_t hswep_unc_i_transactions[]={ { .uname = "READS", .udesc = "Reads (not including prefetches)", .ucode = 0x100, }, { .uname = "WRITES", .udesc = "Writes", .ucode = 0x200, }, { .uname = "RD_PREF", .udesc = "Read prefetches", .ucode = 0x400, }, { .uname = "WR_PREF", .udesc = "Write prefetches", .ucode = 0x800, }, { .uname = "ATOMIC", .udesc = "Atomic transactions", .ucode = 0x1000, }, { .uname = "OTHER", .udesc = "Other kinds of transactions", .ucode = 0x2000, }, { .uname = "ORDERINGQ", .udesc = "Track request coming from port designated in IRP OrderingQ filter", .ucode = 0x4000, }, }; static const intel_x86_entry_t intel_hswep_unc_i_pe[]={ { .name = "UNC_I_CLOCKTICKS", .desc = "Number of uclks in domain", .code = 0x0, .cntmsk = 0x3, .modmsk = HSWEP_UNC_IRP_ATTRS, }, { .name = "UNC_I_SNOOP_RESP", .desc = "Snoop responses", .code = 0x17, .cntmsk = 0x3, .ngrp = 1, .modmsk = HSWEP_UNC_IRP_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_i_snoop_resp), .umasks = hswep_unc_i_snoop_resp, }, { .name = "UNC_I_MISC0", .desc = "Miscellaneous events", .code = 0x14, .cntmsk = 0x3, .ngrp = 1, .modmsk = HSWEP_UNC_IRP_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_i_misc0), .umasks = hswep_unc_i_misc0, }, { .name = "UNC_I_COHERENT_OPS", .desc = "Coherent operations", .code = 0x13, .cntmsk = 0x3, .ngrp = 1, .modmsk = HSWEP_UNC_IRP_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_i_coherent_ops), .umasks = hswep_unc_i_coherent_ops, }, { .name = "UNC_I_CACHE_TOTAL_OCCUPANCY", .desc = "Total write cache occupancy", .code = 0x12, .cntmsk = 0x3, .ngrp = 1, .modmsk = HSWEP_UNC_IRP_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_i_cache_ack_pending_occupancy), .umasks = hswep_unc_i_cache_ack_pending_occupancy /* shared */ }, { .name = "UNC_I_RXR_AK_INSERTS", .desc = "Egress cycles full", .code = 0xa, .cntmsk = 0x3, .modmsk = HSWEP_UNC_IRP_ATTRS, }, { .name = "UNC_I_RXR_BL_DRS_CYCLES_FULL", .desc = "TBD", .code = 0x4, .cntmsk = 0x3, .modmsk = HSWEP_UNC_IRP_ATTRS, }, { .name = "UNC_I_RXR_BL_DRS_INSERTS", .desc = "BL Ingress occupancy DRS", .code = 0x1, .cntmsk = 0x3, .modmsk = HSWEP_UNC_IRP_ATTRS, }, { .name = "UNC_I_RXR_BL_DRS_OCCUPANCY", .desc = "TBD", .code = 0x7, .cntmsk = 0x3, .modmsk = HSWEP_UNC_IRP_ATTRS, }, { .name = "UNC_I_RXR_BL_NCB_CYCLES_FULL", .desc = "TBD", .code = 0x5, .cntmsk = 0x3, .modmsk = HSWEP_UNC_IRP_ATTRS, }, { .name = "UNC_I_RXR_BL_NCB_INSERTS", .desc = "BL Ingress occupancy NCB", .code = 0x2, .cntmsk = 0x3, .modmsk = HSWEP_UNC_IRP_ATTRS, }, { .name = "UNC_I_RXR_BL_NCB_OCCUPANCY", .desc = "TBD", .code = 0x8, .cntmsk = 0x3, .modmsk = HSWEP_UNC_IRP_ATTRS, }, { .name = "UNC_I_RXR_BL_NCS_CYCLES_FULL", .desc = "TBD", .code = 0x6, .cntmsk = 0x3, .modmsk = HSWEP_UNC_IRP_ATTRS, }, { .name = "UNC_I_RXR_BL_NCS_INSERTS", .desc = "BL Ingress Occupancy NCS", .code = 0x3, .cntmsk = 0x3, .modmsk = HSWEP_UNC_IRP_ATTRS, }, { .name = "UNC_I_RXR_BL_NCS_OCCUPANCY", .desc = "TBD", .code = 0x9, .cntmsk = 0x3, .modmsk = HSWEP_UNC_IRP_ATTRS, }, { .name = "UNC_I_TRANSACTIONS", .desc = "Inbound transactions", .code = 0x16, .cntmsk = 0x3, .ngrp = 1, .modmsk = HSWEP_UNC_IRP_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_i_transactions), .umasks = hswep_unc_i_transactions, }, { .name = "UNC_I_MISC1", .desc = "Misc events", .code = 0x15, .cntmsk = 0x3, .ngrp = 1, .modmsk = HSWEP_UNC_IRP_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_i_misc1), .umasks = hswep_unc_i_misc1, }, { .name = "UNC_I_TXR_AD_STALL_CREDIT_CYCLES", .desc = "No AD Egress credit stalls", .code = 0x18, .cntmsk = 0x3, .modmsk = HSWEP_UNC_IRP_ATTRS, }, { .name = "UNC_I_TXR_BL_STALL_CREDIT_CYCLES", .desc = "No BL Egress credit stalls", .code = 0x19, .cntmsk = 0x3, .modmsk = HSWEP_UNC_IRP_ATTRS, }, { .name = "UNC_I_TXR_DATA_INSERTS_NCB", .desc = "Outbound read requests", .code = 0xe, .cntmsk = 0x3, .modmsk = HSWEP_UNC_IRP_ATTRS, }, { .name = "UNC_I_TXR_DATA_INSERTS_NCS", .desc = "Outbound read requests", .code = 0xf, .cntmsk = 0x3, .modmsk = HSWEP_UNC_IRP_ATTRS, }, { .name = "UNC_I_TXR_REQUEST_OCCUPANCY", .desc = "Outbound request queue occupancy", .code = 0xd, .cntmsk = 0x3, .modmsk = HSWEP_UNC_IRP_ATTRS, }, }; libpfm-4.9.0/lib/events/intel_p6_events.h0000664000175000017500000006106013223402656020150 0ustar eranianeranian/* * Copyright (c) 2011 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * This file has been automatically generated. * * PMU: p6 (Intel P6 Processor Family) */ static const intel_x86_umask_t p6_l2_ifetch[]={ { .uname = "I", .udesc = "Invalid state", .ucode = 0x100, }, { .uname = "S", .udesc = "Shared state", .ucode = 0x200, }, { .uname = "E", .udesc = "Exclusive state", .ucode = 0x400, }, { .uname = "M", .udesc = "Modified state", .ucode = 0x800, }, }; static const intel_x86_umask_t p6_bus_drdy_clocks[]={ { .uname = "SELF", .udesc = "Clocks when processor is driving bus", .ucode = 0x0, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "ANY", .udesc = "Clocks when any agent is driving bus", .ucode = 0x2000, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t p6_mmx_instr_type_exec[]={ { .uname = "MUL", .udesc = "MMX packed multiply instructions executed", .ucode = 0x100, }, { .uname = "SHIFT", .udesc = "MMX packed shift instructions executed", .ucode = 0x200, }, { .uname = "PACK", .udesc = "MMX pack operation instructions executed", .ucode = 0x400, }, { .uname = "UNPACK", .udesc = "MMX unpack operation instructions executed", .ucode = 0x800, }, { .uname = "LOGICAL", .udesc = "MMX packed logical instructions executed", .ucode = 0x1000, }, { .uname = "ARITH", .udesc = "MMX packed arithmetic instructions executed", .ucode = 0x2000, }, }; static const intel_x86_umask_t p6_fp_mmx_trans[]={ { .uname = "TO_FP", .udesc = "From MMX instructions to floating-point instructions", .ucode = 0x0, .uflags= INTEL_X86_NCOMBO, }, { .uname = "TO_MMX", .udesc = "From floating-point instructions to MMX instructions", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t p6_seg_rename_stalls[]={ { .uname = "ES", .udesc = "Segment register ES", .ucode = 0x100, }, { .uname = "DS", .udesc = "Segment register DS", .ucode = 0x200, }, { .uname = "FS", .udesc = "Segment register FS", .ucode = 0x400, }, { .uname = "GS", .udesc = "Segment register GS", .ucode = 0x800, }, }; static const intel_x86_umask_t p6_emon_kni_pref_dispatched[]={ { .uname = "NTA", .udesc = "Prefetch NTA", .ucode = 0x0, .uflags= INTEL_X86_NCOMBO, }, { .uname = "T1", .udesc = "Prefetch T1", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "T2", .udesc = "Prefetch T2", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "WEAK", .udesc = "Weakly ordered stores", .ucode = 0x300, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t p6_emon_kni_inst_retired[]={ { .uname = "PACKED_SCALAR", .udesc = "Packed and scalar instructions", .ucode = 0x0, .uflags= INTEL_X86_NCOMBO, }, { .uname = "SCALAR", .udesc = "Scalar only", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_entry_t intel_p6_pe[]={ { .name = "CPU_CLK_UNHALTED", .desc = "Number cycles during which the processor is not halted", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x79, }, { .name = "INST_RETIRED", .desc = "Number of instructions retired", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xc0, }, { .name = "DATA_MEM_REFS", .desc = "All loads from any memory type. All stores to any memory typeEach part of a split is counted separately. The internal logic counts not only memory loads and stores but also internal retries. 80-bit floating point accesses are double counted, since they are decomposed into a 16-bit exponent load and a 64-bit mantissa load. Memory accesses are only counted when they are actually performed (such as a load that gets squashed because a previous cache miss is outstanding to the same address, and which finally gets performed, is only counted once). Does not include I/O accesses or other non-memory accesses", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x43, }, { .name = "DCU_LINES_IN", .desc = "Total lines allocated in the DCU", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x45, }, { .name = "DCU_M_LINES_IN", .desc = "Number of M state lines allocated in the DCU", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x46, }, { .name = "DCU_M_LINES_OUT", .desc = "Number of M state lines evicted from the DCU. This includes evictions via snoop HITM, intervention or replacement", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x47, }, { .name = "DCU_MISS_OUTSTANDING", .desc = "Weighted number of cycle while a DCU miss is outstanding, incremented by the number of cache misses at any particular time. Cacheable read requests only are considered. Uncacheable requests are excluded Read-for-ownerships are counted, as well as line fills, invalidates, and stores", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x48, }, { .name = "IFU_IFETCH", .desc = "Number of instruction fetches, both cacheable and noncacheable including UC fetches", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x80, }, { .name = "IFU_IFETCH_MISS", .desc = "Number of instruction fetch misses. All instructions fetches that do not hit the IFU (i.e., that produce memory requests). Includes UC accesses", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x81, }, { .name = "ITLB_MISS", .desc = "Number of ITLB misses", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x85, }, { .name = "IFU_MEM_STALL", .desc = "Number of cycles instruction fetch is stalled for any reason. Includes IFU cache misses, ITLB misses, ITLB faults, and other minor stalls", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x86, }, { .name = "ILD_STALL", .desc = "Number of cycles that the instruction length decoder is stalled", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x87, }, { .name = "L2_IFETCH", .desc = "Number of L2 instruction fetches. This event indicates that a normal instruction fetch was received by the L2. The count includes only L2 cacheable instruction fetches: it does not include UC instruction fetches It does not include ITLB miss accesses", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x28, .numasks = LIBPFM_ARRAY_SIZE(p6_l2_ifetch), .ngrp = 1, .umasks = p6_l2_ifetch, }, { .name = "L2_ST", .desc = "Number of L2 data stores. This event indicates that a normal, unlocked, store memory access was received by the L2. Specifically, it indicates that the DCU sent a read-for ownership request to the L2. It also includes Invalid to Modified requests sent by the DCU to the L2. It includes only L2 cacheable memory accesses; it does not include I/O accesses, other non-memory accesses, or memory accesses such as UC/WT memory accesses. It does include L2 cacheable TLB miss memory accesses", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x2a, .numasks = LIBPFM_ARRAY_SIZE(p6_l2_ifetch), .ngrp = 1, .umasks = p6_l2_ifetch, /* identical to actual umasks list for this event */ }, { .name = "L2_M_LINES_INM", .desc = "Number of modified lines allocated in the L2", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x25, }, { .name = "L2_RQSTS", .desc = "Total number of L2 requests", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x2e, .numasks = LIBPFM_ARRAY_SIZE(p6_l2_ifetch), .ngrp = 1, .umasks = p6_l2_ifetch, /* identical to actual umasks list for this event */ }, { .name = "L2_ADS", .desc = "Number of L2 address strobes", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x21, }, { .name = "L2_DBUS_BUSY", .desc = "Number of cycles during which the L2 cache data bus was busy", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x22, }, { .name = "L2_DBUS_BUSY_RD", .desc = "Number of cycles during which the data bus was busy transferring read data from L2 to the processor", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x23, }, { .name = "BUS_DRDY_CLOCKS", .desc = "Number of clocks during which DRDY# is asserted. Utilization of the external system data bus during data transfers", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x62, .numasks = LIBPFM_ARRAY_SIZE(p6_bus_drdy_clocks), .ngrp = 1, .umasks = p6_bus_drdy_clocks, }, { .name = "BUS_LOCK_CLOCKS", .desc = "Number of clocks during which LOCK# is asserted on the external system bus", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x63, .numasks = LIBPFM_ARRAY_SIZE(p6_bus_drdy_clocks), .ngrp = 1, .umasks = p6_bus_drdy_clocks, /* identical to actual umasks list for this event */ }, { .name = "BUS_REQ_OUTSTANDING", .desc = "Number of bus requests outstanding. This counter is incremented by the number of cacheable read bus requests outstanding in any given cycle", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x60, }, { .name = "BUS_TRANS_BRD", .desc = "Number of burst read transactions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x65, .numasks = LIBPFM_ARRAY_SIZE(p6_bus_drdy_clocks), .ngrp = 1, .umasks = p6_bus_drdy_clocks, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRANS_RFO", .desc = "Number of completed read for ownership transactions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x66, .numasks = LIBPFM_ARRAY_SIZE(p6_bus_drdy_clocks), .ngrp = 1, .umasks = p6_bus_drdy_clocks, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRANS_WB", .desc = "Number of completed write back transactions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x67, .numasks = LIBPFM_ARRAY_SIZE(p6_bus_drdy_clocks), .ngrp = 1, .umasks = p6_bus_drdy_clocks, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRAN_IFETCH", .desc = "Number of completed instruction fetch transactions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x68, .numasks = LIBPFM_ARRAY_SIZE(p6_bus_drdy_clocks), .ngrp = 1, .umasks = p6_bus_drdy_clocks, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRAN_INVAL", .desc = "Number of completed invalidate transactions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x69, .numasks = LIBPFM_ARRAY_SIZE(p6_bus_drdy_clocks), .ngrp = 1, .umasks = p6_bus_drdy_clocks, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRAN_PWR", .desc = "Number of completed partial write transactions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x6a, .numasks = LIBPFM_ARRAY_SIZE(p6_bus_drdy_clocks), .ngrp = 1, .umasks = p6_bus_drdy_clocks, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRANS_P", .desc = "Number of completed partial transactions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x6b, .numasks = LIBPFM_ARRAY_SIZE(p6_bus_drdy_clocks), .ngrp = 1, .umasks = p6_bus_drdy_clocks, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRANS_IO", .desc = "Number of completed I/O transactions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x6c, .numasks = LIBPFM_ARRAY_SIZE(p6_bus_drdy_clocks), .ngrp = 1, .umasks = p6_bus_drdy_clocks, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRAN_DEF", .desc = "Number of completed deferred transactions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x6d, .numasks = LIBPFM_ARRAY_SIZE(p6_bus_drdy_clocks), .ngrp = 1, .umasks = p6_bus_drdy_clocks, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRAN_BURST", .desc = "Number of completed burst transactions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x6e, .numasks = LIBPFM_ARRAY_SIZE(p6_bus_drdy_clocks), .ngrp = 1, .umasks = p6_bus_drdy_clocks, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRAN_ANY", .desc = "Number of all completed bus transactions. Address bus utilization can be calculated knowing the minimum address bus occupancy. Includes special cycles, etc.", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x70, .numasks = LIBPFM_ARRAY_SIZE(p6_bus_drdy_clocks), .ngrp = 1, .umasks = p6_bus_drdy_clocks, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRAN_MEM", .desc = "Number of completed memory transactions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x6f, .numasks = LIBPFM_ARRAY_SIZE(p6_bus_drdy_clocks), .ngrp = 1, .umasks = p6_bus_drdy_clocks, /* identical to actual umasks list for this event */ }, { .name = "BUS_DATA_RECV", .desc = "Number of bus clock cycles during which this processor is receiving data", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x64, }, { .name = "BUS_BNR_DRV", .desc = "Number of bus clock cycles during which this processor is driving the BNR# pin", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x61, }, { .name = "BUS_HIT_DRV", .desc = "Number of bus clock cycles during which this processor is driving the HIT# pin", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x7a, }, { .name = "BUS_HITM_DRV", .desc = "Number of bus clock cycles during which this processor is driving the HITM# pin", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x7b, }, { .name = "BUS_SNOOP_STALL", .desc = "Number of clock cycles during which the bus is snoop stalled", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x7e, }, { .name = "FLOPS", .desc = "Number of computational floating-point operations retired. Excludes floating-point computational operations that cause traps or assists. Includes internal sub-operations for complex floating-point instructions like transcendentals. Excludes floating point loads and stores", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x1, .code = 0xc1, }, { .name = "FP_COMP_OPS_EXE", .desc = "Number of computational floating-point operations executed. The number of FADD, FSUB, FCOM, FMULs, integer MULs and IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This number does not include the number of cycles, but the number of operations. This event does not distinguish an FADD used in the middle of a transcendental flow from a separate FADD instruction", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x1, .code = 0x10, }, { .name = "FP_ASSIST", .desc = "Number of floating-point exception cases handled by microcode.", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x2, .code = 0x11, }, { .name = "MUL", .desc = "Number of multiplies.This count includes integer as well as FP multiplies and is speculative", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x2, .code = 0x12, }, { .name = "DIV", .desc = "Number of divides.This count includes integer as well as FP divides and is speculative", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x2, .code = 0x13, }, { .name = "CYCLES_DIV_BUSY", .desc = "Number of cycles during which the divider is busy, and cannot accept new divides. This includes integer and FP divides, FPREM, FPSQRT, etc. and is speculative", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x1, .code = 0x14, }, { .name = "LD_BLOCKS", .desc = "Number of load operations delayed due to store buffer blocks. Includes counts caused by preceding stores whose addresses are unknown, preceding stores whose addresses are known but whose data is unknown, and preceding stores that conflicts with the load but which incompletely overlap the load", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x3, }, { .name = "SB_DRAINS", .desc = "Number of store buffer drain cycles. Incremented every cycle the store buffer is draining. Draining is caused by serializing operations like CPUID, synchronizing operations like XCHG, interrupt acknowledgment, as well as other conditions (such as cache flushing).", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x4, }, { .name = "MISALIGN_MEM_REF", .desc = "Number of misaligned data memory references. Incremented by 1 every cycle during which, either the processor's load or store pipeline dispatches a misaligned micro-op Counting is performed if it is the first or second half or if it is blocked, squashed, or missed. In this context, misaligned means crossing a 64-bit boundary", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x5, }, { .name = "UOPS_RETIRED", .desc = "Number of micro-ops retired", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xc2, }, { .name = "INST_DECODED", .desc = "Number of instructions decoded", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xd0, }, { .name = "HW_INT_RX", .desc = "Number of hardware interrupts received", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xc8, }, { .name = "CYCLES_INT_MASKED", .desc = "Number of processor cycles for which interrupts are disabled", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xc6, }, { .name = "CYCLES_INT_PENDING_AND_MASKED", .desc = "Number of processor cycles for which interrupts are disabled and interrupts are pending.", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xc7, }, { .name = "BR_INST_RETIRED", .desc = "Number of branch instructions retired", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xc4, }, { .name = "BR_MISS_PRED_RETIRED", .desc = "Number of mispredicted branches retired", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xc5, }, { .name = "BR_TAKEN_RETIRED", .desc = "Number of taken branches retired", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xc9, }, { .name = "BR_MISS_PRED_TAKEN_RET", .desc = "Number of taken mispredicted branches retired", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xca, }, { .name = "BR_INST_DECODED", .desc = "Number of branch instructions decoded", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xe0, }, { .name = "BTB_MISSES", .desc = "Number of branches for which the BTB did not produce a prediction", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xe2, }, { .name = "BR_BOGUS", .desc = "Number of bogus branches", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xe4, }, { .name = "BACLEARS", .desc = "Number of times BACLEAR is asserted. This is the number of times that a static branch prediction was made, in which the branch decoder decided to make a branch prediction because the BTB did not", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xe6, }, { .name = "RESOURCE_STALLS", .desc = "Incremented by 1 during every cycle for which there is a resource related stall. Includes register renaming buffer entries, memory buffer entries. Does not include stalls due to bus queue full, too many cache misses, etc. In addition to resource related stalls, this event counts some other events. Includes stalls arising during branch misprediction recovery, such as if retirement of the mispredicted branch is delayed and stalls arising while store buffer is draining from synchronizing operations", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xa2, }, { .name = "PARTIAL_RAT_STALLS", .desc = "Number of cycles or events for partial stalls. This includes flag partial stalls", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xd2, }, { .name = "SEGMENT_REG_LOADS", .desc = "Number of segment register loads.", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x6, }, { .name = "MMX_SAT_INSTR_EXEC", .desc = "Number of MMX saturating instructions executed", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xb1, }, { .name = "MMX_UOPS_EXEC", .desc = "Number of MMX micro-ops executed", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xb2, }, { .name = "MMX_INSTR_TYPE_EXEC", .desc = "Number of MMX instructions executed by type", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xb3, .numasks = LIBPFM_ARRAY_SIZE(p6_mmx_instr_type_exec), .ngrp = 1, .umasks = p6_mmx_instr_type_exec, }, { .name = "FP_MMX_TRANS", .desc = "Number of MMX transitions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xcc, .numasks = LIBPFM_ARRAY_SIZE(p6_fp_mmx_trans), .ngrp = 1, .umasks = p6_fp_mmx_trans, }, { .name = "MMX_ASSIST", .desc = "Number of MMX micro-ops executed", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xcd, }, { .name = "SEG_RENAME_STALLS", .desc = "Number of Segment Register Renaming Stalls", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xd4, .numasks = LIBPFM_ARRAY_SIZE(p6_seg_rename_stalls), .ngrp = 1, .umasks = p6_seg_rename_stalls, }, { .name = "SEG_REG_RENAMES", .desc = "Number of Segment Register Renames", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xd5, .numasks = LIBPFM_ARRAY_SIZE(p6_seg_rename_stalls), .ngrp = 1, .umasks = p6_seg_rename_stalls, /* identical to actual umasks list for this event */ }, { .name = "RET_SEG_RENAMES", .desc = "Number of segment register rename events retired", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xd6, }, { .name = "EMON_KNI_PREF_DISPATCHED", .desc = "Number of Streaming SIMD extensions prefetch/weakly-ordered instructions dispatched (speculative prefetches are included in counting). Pentium III and later", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x7, .numasks = LIBPFM_ARRAY_SIZE(p6_emon_kni_pref_dispatched), .ngrp = 1, .umasks = p6_emon_kni_pref_dispatched, }, { .name = "EMON_KNI_PREF_MISS", .desc = "Number of prefetch/weakly-ordered instructions that miss all caches. Pentium III and later", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x4b, .numasks = LIBPFM_ARRAY_SIZE(p6_emon_kni_pref_dispatched), .ngrp = 1, .umasks = p6_emon_kni_pref_dispatched, /* identical to actual umasks list for this event */ }, { .name = "L2_LD", .desc = "Number of L2 data loads. This event indicates that a normal, unlocked, load memory access was received by the L2. It includes only L2 cacheable memory accesses; it does not include I/O accesses, other non-memory accesses, or memory accesses such as UC/WT memory accesses. It does include L2 cacheable TLB miss memory accesses", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x29, .numasks = LIBPFM_ARRAY_SIZE(p6_l2_ifetch), .ngrp = 1, .umasks = p6_l2_ifetch, /* identical to actual umasks list for this event */ }, { .name = "L2_LINES_IN", .desc = "Number of lines allocated in the L2", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x24, }, { .name = "L2_LINES_OUT", .desc = "Number of lines removed from the L2 for any reason", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x26, }, { .name = "L2_M_LINES_OUTM", .desc = "Number of modified lines removed from the L2 for any reason", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x27, }, { .name = "EMON_KNI_INST_RETIRED", .desc = "Number of SSE instructions retired. Pentium III and later", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xd8, .numasks = LIBPFM_ARRAY_SIZE(p6_emon_kni_inst_retired), .ngrp = 1, .umasks = p6_emon_kni_inst_retired, }, { .name = "EMON_KNI_COMP_INST_RET", .desc = "Number of SSE computation instructions retired. Pentium III and later", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xd9, .numasks = LIBPFM_ARRAY_SIZE(p6_emon_kni_inst_retired), .ngrp = 1, .umasks = p6_emon_kni_inst_retired, /* identical to actual umasks list for this event */ }, }; libpfm-4.9.0/lib/events/intel_knl_events.h0000664000175000017500000012337413223402656020416 0ustar eranianeranian/* * Copyright (c) 2016 Intel Corp. All rights reserved * Contributed by Peinan Zhang * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * PMU: knl (Intel Knights Landing) */ static const intel_x86_umask_t knl_icache[]={ { .uname = "HIT", .udesc = "Counts all instruction fetches that hit the instruction cache.", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "MISSES", .udesc = "Counts all instruction fetches that miss the instruction cache or produce memory requests. An instruction fetch miss is counted only once and not once for every cycle it is outstanding.", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ACCESSES", .udesc = "Counts all instruction fetches, including uncacheable fetches.", .ucode = 0x300, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t knl_uops_retired[]={ { .uname = "ALL", .udesc = "Counts the number of micro-ops retired.", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "MS", .udesc = "Counts the number of micro-ops retired that are from the complex flows issued by the micro-sequencer (MS).", .ucode = 0x0100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "SCALAR_SIMD", .udesc = "Counts the number of scalar SSE, AVX, AVX2, AVX-512 micro-ops retired. More specifically, it counts scalar SSE, AVX, AVX2, AVX-512 micro-ops except for loads (memory-to-register mov-type micro ops), division, sqrt.", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "PACKED_SIMD", .udesc = "Counts the number of vector SSE, AVX, AVX2, AVX-512 micro-ops retired. More specifically, it counts packed SSE, AVX, AVX2, AVX-512 micro-ops (both floating point and integer) except for loads (memory-to-register mov-type micro-ops), packed byte and word multiplies.", .ucode = 0x4000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t knl_inst_retired[]={ { .uname = "ANY_P", .udesc = "Instructions retired using generic counter (precise event)", .ucode = 0x0, .uflags = INTEL_X86_PEBS | INTEL_X86_DFL, }, { .uname = "ANY", .udesc = "Instructions retired using generic counter (precise event)", .uequiv = "ANY_P", .ucode = 0x0, .uflags = INTEL_X86_PEBS, }, }; static const intel_x86_umask_t knl_l2_requests_reject[]={ { .uname = "ALL", .udesc = "Counts the number of MEC requests from the L2Q that reference a cache line excluding SW prefetches filling only to L2 cache and L1 evictions (automatically exlcudes L2HWP, UC, WC) that were rejected - Multiple repeated rejects should be counted multiple times.", .ucode = 0x000, .uflags = INTEL_X86_DFL, }, }; static const intel_x86_umask_t knl_core_reject[]={ { .uname = "ALL", .udesc = "Counts the number of MEC requests that were not accepted into the L2Q because of any L2 queue reject condition. There is no concept of at-ret here. It might include requests due to instructions in the speculative path", .ucode = 0x000, .uflags = INTEL_X86_DFL, }, }; static const intel_x86_umask_t knl_machine_clears[]={ { .uname = "SMC", .udesc = "Counts the number of times that the machine clears due to program modifying data within 1K of a recently fetched code page.", .ucode = 0x0100, .uflags = INTEL_X86_DFL, }, { .uname = "MEMORY_ORDERING", .udesc = "Counts the number of times the machine clears due to memory ordering hazards", .ucode = 0x0200, }, { .uname = "FP_ASSIST", .udesc = "Counts the number of floating operations retired that required microcode assists", .ucode = 0x0400, }, { .uname = "ALL", .udesc = "Counts all nukes", .ucode = 0x0800, }, { .uname = "ANY", .udesc = "Counts all nukes", .uequiv = "ALL", .ucode = 0x0800, }, }; static const intel_x86_umask_t knl_br_inst_retired[]={ { .uname = "ANY", .udesc = "Counts the number of branch instructions retired (Precise Event)", .ucode = 0x0, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL | INTEL_X86_PEBS, }, { .uname = "ALL_BRANCHES", .udesc = "Counts the number of branch instructions retired", .uequiv = "ANY", .ucode = 0x0, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "JCC", .udesc = "Counts the number of branch instructions retired that were conditional jumps.", .ucode = 0x7e00, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "TAKEN_JCC", .udesc = "Counts the number of branch instructions retired that were conditional jumps and predicted taken.", .ucode = 0xfe00, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "CALL", .udesc = "Counts the number of near CALL branch instructions retired.", .ucode = 0xf900, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "REL_CALL", .udesc = "Counts the number of near relative CALL branch instructions retired.", .ucode = 0xfd00, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "IND_CALL", .udesc = "Counts the number of near indirect CALL branch instructions retired. (Precise Event)", .ucode = 0xfb00, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "RETURN", .udesc = "Counts the number of near RET branch instructions retired. (Precise Event)", .ucode = 0xf700, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "NON_RETURN_IND", .udesc = "Counts the number of branch instructions retired that were near indirect CALL or near indirect JMP. (Precise Event)", .ucode = 0xeb00, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "FAR_BRANCH", .udesc = "Counts the number of far branch instructions retired. (Precise Event)", .uequiv = "FAR", .ucode = 0xbf00, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "FAR", .udesc = "Counts the number of far branch instructions retired. (Precise Event)", .ucode = 0xbf00, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, }; static const intel_x86_umask_t knl_fetch_stall[]={ { .uname = "ICACHE_FILL_PENDING_CYCLES", .udesc = "Counts the number of core cycles the fetch stalls because of an icache miss. This is a cumulative count of core cycles the fetch stalled for all icache misses", .ucode = 0x0400, .uflags = INTEL_X86_DFL | INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t knl_baclears[]={ { .uname = "ALL", .udesc = "Counts the number of times the front end resteers for any branch as a result of another branch handling mechanism in the front end.", .ucode = 0x100, .uflags = INTEL_X86_DFL | INTEL_X86_NCOMBO, }, { .uname = "ANY", .udesc = "Counts the number of times the front end resteers for any branch as a result of another branch handling mechanism in the front end.", .uequiv = "ALL", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "RETURN", .udesc = "Counts the number of times the front end resteers for RET branches as a result of another branch handling mechanism in the front end.", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "COND", .udesc = "Counts the number of times the front end resteers for conditional branches as a result of another branch handling mechanism in the front end.", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t knl_cpu_clk_unhalted[]={ { .uname = "THREAD_P", .udesc = "thread cycles when core is not halted", .ucode = 0x0, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "BUS", .udesc = "Bus cycles when core is not halted. This event can give a measurement of the elapsed time. This events has a constant ratio with CPU_CLK_UNHALTED:REF event, which is the maximum bus to processor frequency ratio", .uequiv = "REF_P", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "REF_P", .udesc = "Number of reference cycles that the cpu is not in a halted state. The core enters the halted state when it is running the HLT instruction. In mobile systems, the core frequency may change from time to time. This event is not affected by core frequency changes but counts as if the core is running a the same maximum frequency all the time", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t knl_mem_uops_retired[]={ { .uname = "L1_MISS_LOADS", .udesc = "Counts the number of load micro-ops retired that miss in L1 D cache.", .ucode = 0x100, }, { .uname = "LD_DCU_MISS", .udesc = "Counts the number of load micro-ops retired that miss in L1 D cache.", .uequiv = "L1_MISS_LOADS", .ucode = 0x100, }, { .uname = "L2_HIT_LOADS", .udesc = "Counts the number of load micro-ops retired that hit in the L2.", .ucode = 0x200, .uflags = INTEL_X86_PEBS, }, { .uname = "L2_MISS_LOADS", .udesc = "Counts the number of load micro-ops retired that miss in the L2.", .ucode = 0x400, .uflags = INTEL_X86_PEBS, }, { .uname = "LD_L2_MISS", .udesc = "Counts the number of load micro-ops retired that miss in the L2.", .uequiv = "L2_MISS_LOADS", .ucode = 0x400, .uflags = INTEL_X86_PEBS, }, { .uname = "DTLB_MISS_LOADS", .udesc = "Counts the number of load micro-ops retired that cause a DTLB miss.", .ucode = 0x800, .uflags = INTEL_X86_PEBS, }, { .uname = "UTLB_MISS_LOADS", .udesc = "Counts the number of load micro-ops retired that caused micro TLB miss.", .ucode = 0x1000, }, { .uname = "LD_UTLB_MISS", .udesc = "Counts the number of load micro-ops retired that caused micro TLB miss.", .uequiv = "UTLB_MISS_LOADS", .ucode = 0x1000, }, { .uname = "HITM", .udesc = "Counts the loads retired that get the data from the other core in the same tile in M state.", .ucode = 0x2000, .uflags = INTEL_X86_PEBS, }, { .uname = "ALL_LOADS", .udesc = "Counts all the load micro-ops retired.", .ucode = 0x4000, .uflags = INTEL_X86_DFL, }, { .uname = "ANY_LD", .udesc = "Counts all the load micro-ops retired.", .uequiv = "ALL_LOADS", .ucode = 0x4000, }, { .uname = "ALL_STORES", .udesc = "Counts all the store micro-ops retired.", .ucode = 0x8000, }, { .uname = "ANY_ST", .udesc = "Counts all the store micro-ops retired.", .uequiv = "ALL_STORES", .ucode = 0x8000, }, }; static const intel_x86_umask_t knl_page_walks[]={ { .uname = "D_SIDE_CYCLES", .udesc = "Counts the total D-side page walks that are completed or started. The page walks started in the speculative path will also be counted.", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "D_SIDE_WALKS", .udesc = "Counts the total number of core cycles for all the D-side page walks. The cycles for page walks started in speculative path will also be included.", .ucode = 0x100 | INTEL_X86_MOD_EDGE | (1ULL << INTEL_X86_CMASK_BIT), .modhw = _INTEL_X86_ATTR_E | _INTEL_X86_ATTR_C, .uflags = INTEL_X86_NCOMBO, }, { .uname = "I_SIDE_CYCLES", .udesc = "Counts the total I-side page walks that are completed.", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "I_SIDE_WALKS", .udesc = "Counts the total number of core cycles for all the I-side page walks. The cycles for page walks started in speculative path will also be included.", .ucode = 0x200 | INTEL_X86_MOD_EDGE | (1ULL << INTEL_X86_CMASK_BIT), .modhw = _INTEL_X86_ATTR_E | _INTEL_X86_ATTR_C, .uflags = INTEL_X86_NCOMBO, }, { .uname = "CYCLES", .udesc = "Counts the total page walks completed (I-side and D-side)", .ucode = 0x300, .modhw = _INTEL_X86_ATTR_E | _INTEL_X86_ATTR_C, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "WALKS", .udesc = "Counts the total number of core cycles for all the page walks. The cycles for page walks started in speculative path will also be included.", .ucode = 0x300 | INTEL_X86_MOD_EDGE | (1ULL << INTEL_X86_CMASK_BIT), .modhw = _INTEL_X86_ATTR_E | _INTEL_X86_ATTR_C, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t knl_l2_rqsts[]={ { .uname = "MISS", .udesc = "Counts the number of L2 cache misses", .ucode = 0x4100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "REFERENCE", .udesc = "Counts the total number of L2 cache references.", .ucode = 0x4f00, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t knl_recycleq[]={ { .uname = "LD_BLOCK_ST_FORWARD", .udesc = "Counts the number of occurrences a retired load gets blocked because its address partially overlaps with a store (Precise Event).", .ucode = 0x0100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "LD_BLOCK_STD_NOTREADY", .udesc = "Counts the number of occurrences a retired load gets blocked because its address overlaps with a store whose data is not ready.", .ucode = 0x0200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ST_SPLITS", .udesc = "Counts the number of occurrences a retired store that is a cache line split. Each split should be counted only once.", .ucode = 0x0400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "LD_SPLITS", .udesc = "Counts the number of occurrences a retired load that is a cache line split. Each split should be counted only once (Precise Event).", .ucode = 0x0800, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "LOCK", .udesc = "Counts all the retired locked loads. It does not include stores because we would double count if we count stores.", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "STA_FULL", .udesc = "Counts the store micro-ops retired that were pushed in the rehad queue because the store address buffer is full.", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ANY_LD", .udesc = "Counts any retired load that was pushed into the recycle queue for any reason.", .ucode = 0x4000, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "ANY_ST", .udesc = "Counts any retired store that was pushed into the recycle queue for any reason.", .ucode = 0x8000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t knl_offcore_response_0[]={ { .uname = "DMND_DATA_RD", .udesc = "Counts demand cacheable data and L1 prefetch data reads", .ucode = 1ULL << (0 + 8), .grpid = 0, }, { .uname = "DMND_RFO", .udesc = "Counts Demand cacheable data writes", .ucode = 1ULL << (1 + 8), .grpid = 0, }, { .uname = "DMND_CODE_RD", .udesc = "Counts demand code reads and prefetch code reads", .ucode = 1ULL << (2 + 8), .grpid = 0, }, { .uname = "PF_L2_RFO", .udesc = "Counts L2 data RFO prefetches (includes PREFETCHW instruction)", .ucode = 1ULL << (5 + 8), .grpid = 0, }, { .uname = "PF_L2_CODE_RD", .udesc = "Request: number of code reads generated by L2 prefetchers", .ucode = 1ULL << (6 + 8), .grpid = 0, }, { .uname = "PARTIAL_READS", .udesc = "Counts Partial reads (UC or WC and is valid only for Outstanding response type).", .ucode = 1ULL << (7 + 8), .grpid = 0, }, { .uname = "PARTIAL_WRITES", .udesc = "Counts Partial writes (UC or WT or WP and should be programmed on PMC1)", .ucode = 1ULL << (8 + 8), .grpid = 0, }, { .uname = "UC_CODE_READS", .udesc = "Counts UC code reads (valid only for Outstanding response type)", .ucode = 1ULL << (9 + 8), .grpid = 0, }, { .uname = "BUS_LOCKS", .udesc = "Counts Bus locks and split lock requests", .ucode = 1ULL << (10 + 8), .grpid = 0, }, { .uname = "FULL_STREAMING_STORES", .udesc = "Counts Full streaming stores (WC and should be programmed on PMC1)", .ucode = 1ULL << (11 + 8), .grpid = 0, }, { .uname = "PF_SOFTWARE", .udesc = "Counts Software prefetches", .ucode = 1ULL << (12 + 8), .grpid = 0, }, { .uname = "PF_L1_DATA_RD", .udesc = "Counts L1 data HW prefetches", .ucode = 1ULL << (13 + 8), .grpid = 0, }, { .uname = "PARTIAL_STREAMING_STORES", .udesc = "Counts Partial streaming stores (WC and should be programmed on PMC1)", .ucode = 1ULL << (14 + 8), .grpid = 0, }, { .uname = "STREAMING_STORES", .udesc = "Counts all streaming stores (WC and should be programmed on PMC1)", .ucode = (1ULL << 14 | 1ULL << 11) << 8, .uequiv = "PARTIAL_STREAMING_STORES:FULL_STREAMING_STORES", .grpid = 0, }, { .uname = "ANY_REQUEST", .udesc = "Counts any request", .ucode = 1ULL << (15 + 8), .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, .grpid = 0, }, { .uname = "ANY_DATA_RD", .udesc = "Counts Demand cacheable data and L1 prefetch data read requests", .ucode = (1ULL << 0 | 1ULL << 7 | 1ULL << 12 | 1ULL << 13) << 8, .uequiv = "DMND_DATA_RD:PARTIAL_READS:PF_SOFTWARE:PF_L1_DATA_RD", .grpid = 0, }, { .uname = "ANY_RFO", .udesc = "Counts Demand cacheable data write requests", .ucode = (1ULL << 1 | 1ULL << 5) << 8, .grpid = 0, }, { .uname = "ANY_CODE_RD", .udesc = "Counts Demand code reads and prefetch code read requests", .ucode = (1ULL << 2 | 1ULL << 6) << 8, .uequiv = "DMND_CODE_RD:PF_L2_CODE_RD", .grpid = 0, }, { .uname = "ANY_READ", .udesc = "Counts any Read request", .ucode = (1ULL << 0 | 1ULL << 1 | 1ULL << 2 | 1ULL << 5 | 1ULL << 6 | 1ULL << 7 | 1ULL << 9 | 1ULL << 12 | 1ULL << 13 ) << 8, .uequiv = "DMND_DATA_RD:DMND_RFO:DMND_CODE_RD:PF_L2_RFO:PF_L2_CODE_RD:PARTIAL_READS:UC_CODE_READS:PF_SOFTWARE:PF_L1_DATA_RD", .grpid = 0, }, { .uname = "ANY_PF_L2", .udesc = "Counts any Prefetch requests", .ucode = (1ULL << 5 | 1ULL << 6) << 8, .uequiv = "PF_L2_RFO:PF_L2_CODE_RD", .grpid = 0, }, { .uname = "ANY_RESPONSE", .udesc = "Accounts for any response", .ucode = (1ULL << 16) << 8, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL | INTEL_X86_EXCL_GRP_GT, .grpid = 1, }, { .uname = "DDR_NEAR", .udesc = "Accounts for data responses from DRAM Local.", .ucode = (1ULL << 31 | 1ULL << 23 ) << 8, .grpid = 1, }, { .uname = "DDR_FAR", .udesc = "Accounts for data responses from DRAM Far.", .ucode = (1ULL << 31 | 1ULL << 24 ) << 8, .grpid = 1, }, { .uname = "MCDRAM_NEAR", .udesc = "Accounts for data responses from MCDRAM Local.", .ucode = (1ULL << 31 | 1ULL << 21 ) << 8, .grpid = 1, }, { .uname = "MCDRAM_FAR", .udesc = "Accounts for data responses from MCDRAM Far or Other tile L2 hit far.", .ucode = (1ULL << 32 | 1ULL << 22 ) << 8, .grpid = 1, }, { .uname = "L2_HIT_NEAR_TILE_E_F", .udesc = "Accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.", .ucode = (1ULL << 35 | 1ULL << 19 ) << 8, .grpid = 1, }, { .uname = "L2_HIT_NEAR_TILE_M", .udesc = "Accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.", .ucode = (1ULL << 36 | 1ULL << 19 ) << 8, .grpid = 1, }, { .uname = "L2_HIT_FAR_TILE_E_F", .udesc = "Accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.", .ucode = (1ULL << 35 | 1ULL << 22 ) << 8, .grpid = 1, }, { .uname = "L2_HIT_FAR_TILE_M", .udesc = "Accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.", .ucode = (1ULL << 36 | 1ULL << 22 ) << 8, .grpid = 1, }, { .uname = "NON_DRAM", .udesc = "accounts for responses from any NON_DRAM system address. This includes MMIO transactions", .ucode = (1ULL << 37 | 1ULL << 17 ) << 8, .grpid = 1, }, { .uname = "MCDRAM", .udesc = "accounts for responses from MCDRAM (local and far)", .ucode = (1ULL << 32 | 1ULL << 31 | 1ULL << 22 | 1ULL << 21 ) << 8, .grpid = 1, }, { .uname = "DDR", .udesc = "accounts for responses from DDR (local and far)", .ucode = (1ULL << 32 | 1ULL << 31 | 1ULL << 24 | 1ULL << 23 ) << 8, .grpid = 1, }, { .uname = "L2_HIT_NEAR_TILE", .udesc = " accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", .ucode = (1ULL << 36 | 1ULL << 35 | 1ULL << 20 | 1ULL << 19 ) << 8, .grpid = 1, }, { .uname = "L2_HIT_FAR_TILE", .udesc = "accounts for responses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", .ucode = (1ULL << 36 | 1ULL << 35 | 1ULL << 22 ) << 8, .grpid = 1, }, { .uname = "OUTSTANDING", .udesc = "outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.", .ucode = (1ULL << 38) << 8, .uflags = INTEL_X86_GRP_DFL_NONE | INTEL_X86_EXCL_GRP_BUT_0, /* can only be combined with request type bits (grpid = 0) */ .grpid = 2, }, }; static const intel_x86_umask_t knl_offcore_response_1[]={ { .uname = "DMND_DATA_RD", .udesc = "Counts demand cacheable data and L1 prefetch data reads", .ucode = 1ULL << (0 + 8), .grpid = 0, }, { .uname = "DMND_RFO", .udesc = "Counts Demand cacheable data writes", .ucode = 1ULL << (1 + 8), .grpid = 0, }, { .uname = "DMND_CODE_RD", .udesc = "Counts demand code reads and prefetch code reads", .ucode = 1ULL << (2 + 8), .grpid = 0, }, { .uname = "PF_L2_RFO", .udesc = "Counts L2 data RFO prefetches (includes PREFETCHW instruction)", .ucode = 1ULL << (5 + 8), .grpid = 0, }, { .uname = "PF_L2_CODE_RD", .udesc = "Request: number of code reads generated by L2 prefetchers", .ucode = 1ULL << (6 + 8), .grpid = 0, }, { .uname = "PARTIAL_READS", .udesc = "Counts Partial reads (UC or WC and is valid only for Outstanding response type).", .ucode = 1ULL << (7 + 8), .grpid = 0, }, { .uname = "PARTIAL_WRITES", .udesc = "Counts Partial writes (UC or WT or WP and should be programmed on PMC1)", .ucode = 1ULL << (8 + 8), .grpid = 0, }, { .uname = "UC_CODE_READS", .udesc = "Counts UC code reads (valid only for Outstanding response type)", .ucode = 1ULL << (9 + 8), .grpid = 0, }, { .uname = "BUS_LOCKS", .udesc = "Counts Bus locks and split lock requests", .ucode = 1ULL << (10 + 8), .grpid = 0, }, { .uname = "FULL_STREAMING_STORES", .udesc = "Counts Full streaming stores (WC and should be programmed on PMC1)", .ucode = 1ULL << (11 + 8), .grpid = 0, }, { .uname = "PF_SOFTWARE", .udesc = "Counts Software prefetches", .ucode = 1ULL << (12 + 8), .grpid = 0, }, { .uname = "PF_L1_DATA_RD", .udesc = "Counts L1 data HW prefetches", .ucode = 1ULL << (13 + 8), .grpid = 0, }, { .uname = "PARTIAL_STREAMING_STORES", .udesc = "Counts Partial streaming stores (WC and should be programmed on PMC1)", .ucode = 1ULL << (14 + 8), .grpid = 0, }, { .uname = "STREAMING_STORES", .udesc = "Counts all streaming stores (WC and should be programmed on PMC1)", .ucode = (1ULL << 14 | 1ULL << 11) << 8, .uequiv = "PARTIAL_STREAMING_STORES:FULL_STREAMING_STORES", .grpid = 0, }, { .uname = "ANY_REQUEST", .udesc = "Counts any request", .ucode = 1ULL << (15 + 8), .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, .grpid = 0, }, { .uname = "ANY_DATA_RD", .udesc = "Counts Demand cacheable data and L1 prefetch data read requests", .ucode = (1ULL << 0 | 1ULL << 7 | 1ULL << 12 | 1ULL << 13) << 8, .uequiv = "DMND_DATA_RD:PARTIAL_READS:PF_SOFTWARE:PF_L1_DATA_RD", .grpid = 0, }, { .uname = "ANY_RFO", .udesc = "Counts Demand cacheable data write requests", .ucode = (1ULL << 1 | 1ULL << 5) << 8, .grpid = 0, }, { .uname = "ANY_CODE_RD", .udesc = "Counts Demand code reads and prefetch code read requests", .ucode = (1ULL << 2 | 1ULL << 6) << 8, .uequiv = "DMND_CODE_RD:PF_L2_CODE_RD", .grpid = 0, }, { .uname = "ANY_READ", .udesc = "Counts any Read request", .ucode = (1ULL << 0 | 1ULL << 1 | 1ULL << 2 | 1ULL << 5 | 1ULL << 6 | 1ULL << 7 | 1ULL << 9 | 1ULL << 12 | 1ULL << 13 ) << 8, .uequiv = "DMND_DATA_RD:DMND_RFO:DMND_CODE_RD:PF_L2_RFO:PF_L2_CODE_RD:PARTIAL_READS:UC_CODE_READS:PF_SOFTWARE:PF_L1_DATA_RD", .grpid = 0, }, { .uname = "ANY_PF_L2", .udesc = "Counts any Prefetch requests", .ucode = (1ULL << 5 | 1ULL << 6) << 8, .uequiv = "PF_L2_RFO:PF_L2_CODE_RD", .grpid = 0, }, { .uname = "ANY_RESPONSE", .udesc = "Accounts for any response", .ucode = (1ULL << 16) << 8, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL | INTEL_X86_EXCL_GRP_GT, .grpid = 1, }, { .uname = "DDR_NEAR", .udesc = "Accounts for data responses from DRAM Local.", .ucode = (1ULL << 31 | 1ULL << 23 ) << 8, .grpid = 1, }, { .uname = "DDR_FAR", .udesc = "Accounts for data responses from DRAM Far.", .ucode = (1ULL << 31 | 1ULL << 24 ) << 8, .grpid = 1, }, { .uname = "MCDRAM_NEAR", .udesc = "Accounts for data responses from MCDRAM Local.", .ucode = (1ULL << 31 | 1ULL << 21 ) << 8, .grpid = 1, }, { .uname = "MCDRAM_FAR", .udesc = "Accounts for data responses from MCDRAM Far or Other tile L2 hit far.", .ucode = (1ULL << 32 | 1ULL << 22 ) << 8, .grpid = 1, }, { .uname = "L2_HIT_NEAR_TILE_E_F", .udesc = "Accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.", .ucode = (1ULL << 35 | 1ULL << 19 ) << 8, .grpid = 1, }, { .uname = "L2_HIT_NEAR_TILE_M", .udesc = "Accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.", .ucode = (1ULL << 36 | 1ULL << 19 ) << 8, .grpid = 1, }, { .uname = "L2_HIT_FAR_TILE_E_F", .udesc = "Accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.", .ucode = (1ULL << 35 | 1ULL << 22 ) << 8, .grpid = 1, }, { .uname = "L2_HIT_FAR_TILE_M", .udesc = "Accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.", .ucode = (1ULL << 36 | 1ULL << 22 ) << 8, .grpid = 1, }, { .uname = "NON_DRAM", .udesc = "accounts for responses from any NON_DRAM system address. This includes MMIO transactions", .ucode = (1ULL << 37 | 1ULL << 17 ) << 8, .grpid = 1, }, { .uname = "MCDRAM", .udesc = "accounts for responses from MCDRAM (local and far)", .ucode = (1ULL << 32 | 1ULL << 31 | 1ULL << 22 | 1ULL << 21 ) << 8, .grpid = 1, }, { .uname = "DDR", .udesc = "accounts for responses from DDR (local and far)", .ucode = (1ULL << 32 | 1ULL << 31 | 1ULL << 24 | 1ULL << 23 ) << 8, .grpid = 1, }, { .uname = "L2_HIT_NEAR_TILE", .udesc = " accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", .ucode = (1ULL << 36 | 1ULL << 35 | 1ULL << 20 | 1ULL << 19 ) << 8, .grpid = 1, }, { .uname = "L2_HIT_FAR_TILE", .udesc = "accounts for responses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", .ucode = (1ULL << 36 | 1ULL << 35 | 1ULL << 22 ) << 8, .grpid = 1, }, }; static const intel_x86_umask_t knl_br_misp_retired[]={ { .uname = "ALL_BRANCHES", .udesc = "All mispredicted branches (Precise Event)", .uequiv = "ANY", .ucode = 0x0000, /* architectural encoding */ .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "ANY", .udesc = "All mispredicted branches (Precise Event)", .ucode = 0x0000, /* architectural encoding */ .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS | INTEL_X86_DFL, }, { .uname = "JCC", .udesc = "Number of mispredicted conditional branch instructions retired (Precise Event)", .ucode = 0x7e00, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "NON_RETURN_IND", .udesc = "Number of mispredicted non-return branch instructions retired (Precise Event)", .ucode = 0xeb00, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "RETURN", .udesc = "Number of mispredicted return branch instructions retired (Precise Event)", .ucode = 0xf700, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "IND_CALL", .udesc = "Number of mispredicted indirect call branch instructions retired (Precise Event)", .ucode = 0xfb00, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "TAKEN_JCC", .udesc = "Number of mispredicted taken conditional branch instructions retired (Precise Event)", .ucode = 0xfe00, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "CALL", .udesc = "Counts the number of mispredicted near CALL branch instructions retired.", .ucode = 0xf900, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "REL_CALL", .udesc = "Counts the number of mispredicted near relative CALL branch instructions retired.", .ucode = 0xfd00, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "FAR_BRANCH", .udesc = "Counts the number of mispredicted far branch instructions retired.", .ucode = 0xbf00, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, }; static const intel_x86_umask_t knl_no_alloc_cycles[]={ { .uname = "ROB_FULL", .udesc = "Counts the number of core cycles when no micro-ops are allocated and the ROB is full", .ucode = 0x0100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "MISPREDICTS", .udesc = "Counts the number of core cycles when no micro-ops are allocated and the alloc pipe is stalled waiting for a mispredicted branch to retire.", .ucode = 0x0400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "RAT_STALL", .udesc = "Counts the number of core cycles when no micro-ops are allocated and a RATstall (caused by reservation station full) is asserted.", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "NOT_DELIVERED", .udesc = "Counts the number of core cycles when no micro-ops are allocated, the IQ is empty, and no other condition is blocking allocation.", .ucode = 0x9000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ALL", .udesc = "Counts the total number of core cycles when no micro-ops are allocated for any reason.", .ucode = 0x7f00, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "ANY", .udesc = "Counts the total number of core cycles when no micro-ops are allocated for any reason.", .uequiv = "ALL", .ucode = 0x7f00, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t knl_rs_full_stall[]={ { .uname = "MEC", .udesc = "Counts the number of core cycles when allocation pipeline is stalled and is waiting for a free MEC reservation station entry.", .ucode = 0x0100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ANY", .udesc = "Counts the total number of core cycles the Alloc pipeline is stalled when any one of the reservation stations is full.", .ucode = 0x1f00, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t knl_cycles_div_busy[]={ { .uname = "ALL", .udesc = "Counts the number of core cycles when divider is busy. Does not imply a stall waiting for the divider.", .ucode = 0x0100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t knl_ms_decoded[]={ { .uname = "ENTRY", .udesc = "Counts the number of times the MSROM starts a flow of uops.", .ucode = 0x0100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t knl_decode_restriction[]={ { .uname = "PREDECODE_WRONG", .udesc = "Number of times the prediction (from the predecode cache) for instruction length is incorrect", .ucode = 0x0100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_entry_t intel_knl_pe[]={ { .name = "UNHALTED_CORE_CYCLES", .desc = "Unhalted core cycles", .modmsk = INTEL_V3_ATTRS, /* any thread only supported in fixed counter */ .cntmsk = 0x200000003ull, .code = 0x3c, }, { .name = "UNHALTED_REFERENCE_CYCLES", .desc = "Unhalted reference cycle", .modmsk = INTEL_FIXED3_ATTRS, .cntmsk = 0x400000000ull, .code = 0x0300, /* pseudo encoding */ .flags = INTEL_X86_FIXED, }, { .name = "INSTRUCTION_RETIRED", .desc = "Instructions retired (any thread modifier supported in fixed counter)", .modmsk = INTEL_V3_ATTRS, /* any thread only supported in fixed counter */ .cntmsk = 0x100000003ull, .code = 0xc0, }, { .name = "INSTRUCTIONS_RETIRED", .desc = "This is an alias for INSTRUCTION_RETIRED (any thread modifier supported in fixed counter)", .modmsk = INTEL_V3_ATTRS, /* any thread only supported in fixed counter */ .equiv = "INSTRUCTION_RETIRED", .cntmsk = 0x10003, .code = 0xc0, }, { .name = "LLC_REFERENCES", .desc = "Last level of cache references", .modmsk = INTEL_V2_ATTRS, .cntmsk = 0x3, .code = 0x4f2e, }, { .name = "LAST_LEVEL_CACHE_REFERENCES", .desc = "This is an alias for LLC_REFERENCES", .modmsk = INTEL_V2_ATTRS, .equiv = "LLC_REFERENCES", .cntmsk = 0x3, .code = 0x4f2e, }, { .name = "LLC_MISSES", .desc = "Last level of cache misses", .modmsk = INTEL_V2_ATTRS, .cntmsk = 0x3, .code = 0x412e, }, { .name = "LAST_LEVEL_CACHE_MISSES", .desc = "This is an alias for LLC_MISSES", .modmsk = INTEL_V2_ATTRS, .equiv = "LLC_MISSES", .cntmsk = 0x3, .code = 0x412e, }, { .name = "BRANCH_INSTRUCTIONS_RETIRED", .desc = "Branch instructions retired", .modmsk = INTEL_V2_ATTRS, .equiv = "BR_INST_RETIRED:ANY", .cntmsk = 0x3, .code = 0xc4, }, { .name = "MISPREDICTED_BRANCH_RETIRED", .desc = "Mispredicted branch instruction retired", .equiv = "BR_MISP_RETIRED:ANY", .modmsk = INTEL_V2_ATTRS, .cntmsk = 0x3, .code = 0xc5, .flags = INTEL_X86_PEBS, }, /* begin model specific events */ { .name = "ICACHE", .desc = "Instruction fetches", .modmsk = INTEL_V2_ATTRS, .cntmsk = 0x3, .code = 0x80, .numasks = LIBPFM_ARRAY_SIZE(knl_icache), .ngrp = 1, .umasks = knl_icache, }, { .name = "UOPS_RETIRED", .desc = "Micro-ops retired", .modmsk = INTEL_V2_ATTRS, .cntmsk = 0x3, .code = 0xc2, .numasks = LIBPFM_ARRAY_SIZE(knl_uops_retired), .ngrp = 1, .umasks = knl_uops_retired, }, { .name = "INST_RETIRED", .desc = "Instructions retired", .modmsk = INTEL_V2_ATTRS, .cntmsk = 0x3, .code = 0xc0, .flags = INTEL_X86_PEBS, .numasks = LIBPFM_ARRAY_SIZE(knl_inst_retired), .ngrp = 1, .umasks = knl_inst_retired, }, { .name = "CYCLES_DIV_BUSY", .desc = "Counts the number of core cycles when divider is busy.", .modmsk = INTEL_V2_ATTRS, .cntmsk = 0x3, .code = 0xcd, .numasks = LIBPFM_ARRAY_SIZE(knl_cycles_div_busy), .ngrp = 1, .umasks = knl_cycles_div_busy, }, { .name = "RS_FULL_STALL", .desc = "Counts the number of core cycles when allocation pipeline is stalled.", .modmsk = INTEL_V2_ATTRS, .cntmsk = 0x3, .code = 0xcb, .numasks = LIBPFM_ARRAY_SIZE(knl_rs_full_stall), .ngrp = 1, .umasks = knl_rs_full_stall, }, { .name = "L2_REQUESTS", .desc = "L2 cache requests", .modmsk = INTEL_V2_ATTRS, .cntmsk = 0x3, .code = 0x2e, .numasks = LIBPFM_ARRAY_SIZE(knl_l2_rqsts), .ngrp = 1, .umasks = knl_l2_rqsts, }, { .name = "MACHINE_CLEARS", .desc = "Counts the number of times that the machine clears.", .modmsk = INTEL_V2_ATTRS, .cntmsk = 0x3, .code = 0xc3, .numasks = LIBPFM_ARRAY_SIZE(knl_machine_clears), .ngrp = 1, .umasks = knl_machine_clears, }, { .name = "BR_INST_RETIRED", .desc = "Retired branch instructions", .modmsk = INTEL_V2_ATTRS, .cntmsk = 0x3, .code = 0xc4, .numasks = LIBPFM_ARRAY_SIZE(knl_br_inst_retired), .flags = INTEL_X86_PEBS, .ngrp = 1, .umasks = knl_br_inst_retired, }, { .name = "BR_MISP_RETIRED", .desc = "Counts the number of mispredicted branch instructions retired.", .modmsk = INTEL_V2_ATTRS, .cntmsk = 0x3, .code = 0xc5, .flags = INTEL_X86_PEBS, .numasks = LIBPFM_ARRAY_SIZE(knl_br_misp_retired), .ngrp = 1, .umasks = knl_br_misp_retired, }, { .name = "MS_DECODED", .desc = "Number of times the MSROM starts a flow of uops.", .modmsk = INTEL_V2_ATTRS, .cntmsk = 0x3, .code = 0xe7, .numasks = LIBPFM_ARRAY_SIZE(knl_ms_decoded), .ngrp = 1, .umasks = knl_ms_decoded, }, { .name = "FETCH_STALL", .desc = "Counts the number of core cycles the fetch stalls.", .modmsk = INTEL_V2_ATTRS, .cntmsk = 0x3, .code = 0x86, .numasks = LIBPFM_ARRAY_SIZE(knl_fetch_stall), .ngrp = 1, .umasks = knl_fetch_stall, }, { .name = "BACLEARS", .desc = "Branch address calculator", .modmsk = INTEL_V2_ATTRS, .cntmsk = 0x3, .code = 0xe6, .numasks = LIBPFM_ARRAY_SIZE(knl_baclears), .ngrp = 1, .umasks = knl_baclears, }, { .name = "NO_ALLOC_CYCLES", .desc = "Front-end allocation", .modmsk = INTEL_V2_ATTRS, .cntmsk = 0x3, .code = 0xca, .numasks = LIBPFM_ARRAY_SIZE(knl_no_alloc_cycles), .ngrp = 1, .umasks = knl_no_alloc_cycles, }, { .name = "CPU_CLK_UNHALTED", .desc = "Core cycles when core is not halted", .modmsk = INTEL_V2_ATTRS, .cntmsk = 0x3, .code = 0x3c, .numasks = LIBPFM_ARRAY_SIZE(knl_cpu_clk_unhalted), .ngrp = 1, .umasks = knl_cpu_clk_unhalted, }, { .name = "MEM_UOPS_RETIRED", .desc = "Counts the number of load micro-ops retired.", .modmsk = INTEL_V2_ATTRS, .cntmsk = 0x3, .code = 0x4, .flags = INTEL_X86_PEBS, .numasks = LIBPFM_ARRAY_SIZE(knl_mem_uops_retired), .ngrp = 1, .umasks = knl_mem_uops_retired, }, { .name = "PAGE_WALKS", .desc = "Number of page-walks executed", .modmsk = INTEL_V2_ATTRS, .cntmsk = 0x3, .code = 0x5, .numasks = LIBPFM_ARRAY_SIZE(knl_page_walks), .ngrp = 1, .umasks = knl_page_walks, }, { .name = "L2_REQUESTS_REJECT", .desc = "Counts the number of MEC requests from the L2Q that reference a cache line were rejected.", .modmsk = INTEL_V2_ATTRS, .cntmsk = 0x3, .code = 0x30, .numasks = LIBPFM_ARRAY_SIZE(knl_l2_requests_reject), .ngrp = 1, .umasks = knl_l2_requests_reject, }, { .name = "CORE_REJECT_L2Q", .desc = "Number of requests not accepted into the L2Q because of any L2 queue reject condition.", .modmsk = INTEL_V2_ATTRS, .cntmsk = 0x3, .code = 0x31, .numasks = LIBPFM_ARRAY_SIZE(knl_core_reject), .ngrp = 1, .umasks = knl_core_reject, }, { .name = "RECYCLEQ", .desc = "Counts the number of occurrences a retired load gets blocked.", .modmsk = INTEL_V2_ATTRS, .cntmsk = 0x3, .code = 0x03, .flags = INTEL_X86_PEBS, .numasks = LIBPFM_ARRAY_SIZE(knl_recycleq), .ngrp = 1, .umasks = knl_recycleq, }, { .name = "OFFCORE_RESPONSE_0", .desc = "Offcore response event (must provide at least one request type and either any_response or any combination of supplier + snoop)", .modmsk = INTEL_V2_ATTRS, .cntmsk = 0xf, .code = 0x01b7, .flags = INTEL_X86_NHM_OFFCORE, .numasks = LIBPFM_ARRAY_SIZE(knl_offcore_response_0), .ngrp = 3, .umasks = knl_offcore_response_0, }, { .name = "OFFCORE_RESPONSE_1", .desc = "Offcore response event (must provide at least one request type and either any_response or any combination of supplier + snoop)", .modmsk = INTEL_V2_ATTRS, .cntmsk = 0xf, .code = 0x02b7, .flags = INTEL_X86_NHM_OFFCORE, .numasks = LIBPFM_ARRAY_SIZE(knl_offcore_response_1), .ngrp = 2, .umasks = knl_offcore_response_1, }, }; libpfm-4.9.0/lib/events/arm_1176_events.h0000664000175000017500000000741113223402656017665 0ustar eranianeranian/* * Copyright (c) 2013 by Vince Weaver * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. */ /* * the various event names are the same as those given in the * file linux-2.6/arch/arm/kernel/perf_event_v6.c */ /* * ARM1176 Event Table */ static const arm_entry_t arm_1176_pe []={ {.name = "ICACHE_MISS", .code = 0x00, .desc = "Instruction cache miss (includes speculative accesses)" }, {.name = "IBUF_STALL", .code = 0x01, .desc = "Stall because instruction buffer cannot deliver an instruction" }, {.name = "DDEP_STALL", .code = 0x02, .desc = "Stall because of data dependency" }, {.name = "ITLB_MISS", .code = 0x03, .desc = "Instruction MicroTLB miss" }, {.name = "DTLB_MISS", .code = 0x04, .desc = "Data MicroTLB miss" }, {.name = "BR_EXEC", .code = 0x05, .desc = "Branch instruction executed" }, {.name = "BR_MISPREDICT", .code = 0x06, .desc = "Branch mispredicted" }, {.name = "INSTR_EXEC", .code = 0x07, .desc = "Instruction executed" }, {.name = "DCACHE_HIT", .code = 0x09, .desc = "Data cache hit" }, {.name = "DCACHE_ACCESS", .code = 0x0a, .desc = "Data cache access" }, {.name = "DCACHE_MISS", .code = 0x0b, .desc = "Data cache miss" }, {.name = "DCACHE_WBACK", .code = 0x0c, .desc = "Data cache writeback" }, {.name = "SW_PC_CHANGE", .code = 0x0d, .desc = "Software changed the PC." }, {.name = "MAIN_TLB_MISS", .code = 0x0f, .desc = "Main TLB miss" }, {.name = "EXPL_D_ACCESS", .code = 0x10, .desc = "Explicit external data cache access " }, {.name = "LSU_FULL_STALL", .code = 0x11, .desc = "Stall because of a full Load Store Unit request queue." }, {.name = "WBUF_DRAINED", .code = 0x12, .desc = "Write buffer drained due to data synchronization barrier or strongly ordered operation" }, {.name = "ETMEXTOUT_0", .code = 0x20, .desc = "ETMEXTOUT[0] was asserted" }, {.name = "ETMEXTOUT_1", .code = 0x21, .desc = "ETMEXTOUT[1] was asserted" }, {.name = "ETMEXTOUT", .code = 0x22, .desc = "Increment once for each of ETMEXTOUT[0] or ETMEXTOUT[1]" }, {.name = "PROC_CALL_EXEC", .code = 0x23, .desc = "Procedure call instruction executed" }, {.name = "PROC_RET_EXEC", .code = 0x24, .desc = "Procedure return instruction executed" }, {.name = "PROC_RET_EXEC_PRED", .code = 0x25, .desc = "Procedure return instruction executed and address predicted" }, {.name = "PROC_RET_EXEC_PRED_INCORRECT", .code = 0x26, .desc = "Procedure return instruction executed and address predicted incorrectly" }, {.name = "CPU_CYCLES", .code = 0xff, .desc = "CPU cycles" }, }; #define ARM_1176_EVENT_COUNT (sizeof(arm_1176_pe)/sizeof(arm_entry_t)) libpfm-4.9.0/lib/events/power7_events.h0000664000175000017500000050771113223402656017663 0ustar eranianeranian/****************************/ /* THIS IS OPEN SOURCE CODE */ /****************************/ #ifndef __POWER7_EVENTS_H__ #define __POWER7_EVENTS_H__ /* * File: power7_events.h * CVS: * Author: Corey Ashford * cjashfor@us.ibm.com * Mods: * * * (C) Copyright IBM Corporation, 2009. All Rights Reserved. * Contributed by Corey Ashford * * Note: This code was automatically generated and should not be modified by * hand. * * Documentation on the PMU events can be found at: * http://www.power.org/documentation/comprehensive-pmu-event-reference-power7 */ #define POWER7_PME_PM_IC_DEMAND_L2_BR_ALL 0 #define POWER7_PME_PM_GCT_UTIL_7_TO_10_SLOTS 1 #define POWER7_PME_PM_PMC2_SAVED 2 #define POWER7_PME_PM_CMPLU_STALL_DFU 3 #define POWER7_PME_PM_VSU0_16FLOP 4 #define POWER7_PME_PM_MRK_LSU_DERAT_MISS 5 #define POWER7_PME_PM_MRK_ST_CMPL 6 #define POWER7_PME_PM_NEST_PAIR3_ADD 7 #define POWER7_PME_PM_L2_ST_DISP 8 #define POWER7_PME_PM_L2_CASTOUT_MOD 9 #define POWER7_PME_PM_ISEG 10 #define POWER7_PME_PM_MRK_INST_TIMEO 11 #define POWER7_PME_PM_L2_RCST_DISP_FAIL_ADDR 12 #define POWER7_PME_PM_LSU1_DC_PREF_STREAM_CONFIRM 13 #define POWER7_PME_PM_IERAT_WR_64K 14 #define POWER7_PME_PM_MRK_DTLB_MISS_16M 15 #define POWER7_PME_PM_IERAT_MISS 16 #define POWER7_PME_PM_MRK_PTEG_FROM_LMEM 17 #define POWER7_PME_PM_FLOP 18 #define POWER7_PME_PM_THRD_PRIO_4_5_CYC 19 #define POWER7_PME_PM_BR_PRED_TA 20 #define POWER7_PME_PM_CMPLU_STALL_FXU 21 #define POWER7_PME_PM_EXT_INT 22 #define POWER7_PME_PM_VSU_FSQRT_FDIV 23 #define POWER7_PME_PM_MRK_LD_MISS_EXPOSED_CYC 24 #define POWER7_PME_PM_LSU1_LDF 25 #define POWER7_PME_PM_IC_WRITE_ALL 26 #define POWER7_PME_PM_LSU0_SRQ_STFWD 27 #define POWER7_PME_PM_PTEG_FROM_RL2L3_MOD 28 #define POWER7_PME_PM_MRK_DATA_FROM_L31_SHR 29 #define POWER7_PME_PM_DATA_FROM_L21_MOD 30 #define POWER7_PME_PM_VSU1_SCAL_DOUBLE_ISSUED 31 #define POWER7_PME_PM_VSU0_8FLOP 32 #define POWER7_PME_PM_POWER_EVENT1 33 #define POWER7_PME_PM_DISP_CLB_HELD_BAL 34 #define POWER7_PME_PM_VSU1_2FLOP 35 #define POWER7_PME_PM_LWSYNC_HELD 36 #define POWER7_PME_PM_PTEG_FROM_DL2L3_SHR 37 #define POWER7_PME_PM_INST_FROM_L21_MOD 38 #define POWER7_PME_PM_IERAT_XLATE_WR_16MPLUS 39 #define POWER7_PME_PM_IC_REQ_ALL 40 #define POWER7_PME_PM_DSLB_MISS 41 #define POWER7_PME_PM_L3_MISS 42 #define POWER7_PME_PM_LSU0_L1_PREF 43 #define POWER7_PME_PM_VSU_SCALAR_SINGLE_ISSUED 44 #define POWER7_PME_PM_LSU1_DC_PREF_STREAM_CONFIRM_STRIDE 45 #define POWER7_PME_PM_L2_INST 46 #define POWER7_PME_PM_VSU0_FRSP 47 #define POWER7_PME_PM_FLUSH_DISP 48 #define POWER7_PME_PM_PTEG_FROM_L2MISS 49 #define POWER7_PME_PM_VSU1_DQ_ISSUED 50 #define POWER7_PME_PM_CMPLU_STALL_LSU 51 #define POWER7_PME_PM_MRK_DATA_FROM_DMEM 52 #define POWER7_PME_PM_LSU_FLUSH_ULD 53 #define POWER7_PME_PM_PTEG_FROM_LMEM 54 #define POWER7_PME_PM_MRK_DERAT_MISS_16M 55 #define POWER7_PME_PM_THRD_ALL_RUN_CYC 56 #define POWER7_PME_PM_MEM0_PREFETCH_DISP 57 #define POWER7_PME_PM_MRK_STALL_CMPLU_CYC_COUNT 58 #define POWER7_PME_PM_DATA_FROM_DL2L3_MOD 59 #define POWER7_PME_PM_VSU_FRSP 60 #define POWER7_PME_PM_MRK_DATA_FROM_L21_MOD 61 #define POWER7_PME_PM_PMC1_OVERFLOW 62 #define POWER7_PME_PM_VSU0_SINGLE 63 #define POWER7_PME_PM_MRK_PTEG_FROM_L3MISS 64 #define POWER7_PME_PM_MRK_PTEG_FROM_L31_SHR 65 #define POWER7_PME_PM_VSU0_VECTOR_SP_ISSUED 66 #define POWER7_PME_PM_VSU1_FEST 67 #define POWER7_PME_PM_MRK_INST_DISP 68 #define POWER7_PME_PM_VSU0_COMPLEX_ISSUED 69 #define POWER7_PME_PM_LSU1_FLUSH_UST 70 #define POWER7_PME_PM_INST_CMPL 71 #define POWER7_PME_PM_FXU_IDLE 72 #define POWER7_PME_PM_LSU0_FLUSH_ULD 73 #define POWER7_PME_PM_MRK_DATA_FROM_DL2L3_MOD 74 #define POWER7_PME_PM_LSU_LMQ_SRQ_EMPTY_ALL_CYC 75 #define POWER7_PME_PM_LSU1_REJECT_LMQ_FULL 76 #define POWER7_PME_PM_INST_PTEG_FROM_L21_MOD 77 #define POWER7_PME_PM_INST_FROM_RL2L3_MOD 78 #define POWER7_PME_PM_SHL_CREATED 79 #define POWER7_PME_PM_L2_ST_HIT 80 #define POWER7_PME_PM_DATA_FROM_DMEM 81 #define POWER7_PME_PM_L3_LD_MISS 82 #define POWER7_PME_PM_FXU1_BUSY_FXU0_IDLE 83 #define POWER7_PME_PM_DISP_CLB_HELD_RES 84 #define POWER7_PME_PM_L2_SN_SX_I_DONE 85 #define POWER7_PME_PM_GRP_CMPL 86 #define POWER7_PME_PM_STCX_CMPL 87 #define POWER7_PME_PM_VSU0_2FLOP 88 #define POWER7_PME_PM_L3_PREF_MISS 89 #define POWER7_PME_PM_LSU_SRQ_SYNC_CYC 90 #define POWER7_PME_PM_LSU_REJECT_ERAT_MISS 91 #define POWER7_PME_PM_L1_ICACHE_MISS 92 #define POWER7_PME_PM_LSU1_FLUSH_SRQ 93 #define POWER7_PME_PM_LD_REF_L1_LSU0 94 #define POWER7_PME_PM_VSU0_FEST 95 #define POWER7_PME_PM_VSU_VECTOR_SINGLE_ISSUED 96 #define POWER7_PME_PM_FREQ_UP 97 #define POWER7_PME_PM_DATA_FROM_LMEM 98 #define POWER7_PME_PM_LSU1_LDX 99 #define POWER7_PME_PM_PMC3_OVERFLOW 100 #define POWER7_PME_PM_MRK_BR_MPRED 101 #define POWER7_PME_PM_SHL_MATCH 102 #define POWER7_PME_PM_MRK_BR_TAKEN 103 #define POWER7_PME_PM_CMPLU_STALL_BRU 104 #define POWER7_PME_PM_ISLB_MISS 105 #define POWER7_PME_PM_CYC 106 #define POWER7_PME_PM_DISP_HELD_THERMAL 107 #define POWER7_PME_PM_INST_PTEG_FROM_RL2L3_SHR 108 #define POWER7_PME_PM_LSU1_SRQ_STFWD 109 #define POWER7_PME_PM_GCT_NOSLOT_BR_MPRED 110 #define POWER7_PME_PM_1PLUS_PPC_CMPL 111 #define POWER7_PME_PM_PTEG_FROM_DMEM 112 #define POWER7_PME_PM_VSU_2FLOP 113 #define POWER7_PME_PM_GCT_FULL_CYC 114 #define POWER7_PME_PM_MRK_DATA_FROM_L3_CYC 115 #define POWER7_PME_PM_LSU_SRQ_S0_ALLOC 116 #define POWER7_PME_PM_MRK_DERAT_MISS_4K 117 #define POWER7_PME_PM_BR_MPRED_TA 118 #define POWER7_PME_PM_INST_PTEG_FROM_L2MISS 119 #define POWER7_PME_PM_DPU_HELD_POWER 120 #define POWER7_PME_PM_RUN_INST_CMPL 121 #define POWER7_PME_PM_MRK_VSU_FIN 122 #define POWER7_PME_PM_LSU_SRQ_S0_VALID 123 #define POWER7_PME_PM_GCT_EMPTY_CYC 124 #define POWER7_PME_PM_IOPS_DISP 125 #define POWER7_PME_PM_RUN_SPURR 126 #define POWER7_PME_PM_PTEG_FROM_L21_MOD 127 #define POWER7_PME_PM_VSU0_1FLOP 128 #define POWER7_PME_PM_SNOOP_TLBIE 129 #define POWER7_PME_PM_DATA_FROM_L3MISS 130 #define POWER7_PME_PM_VSU_SINGLE 131 #define POWER7_PME_PM_DTLB_MISS_16G 132 #define POWER7_PME_PM_CMPLU_STALL_VECTOR 133 #define POWER7_PME_PM_FLUSH 134 #define POWER7_PME_PM_L2_LD_HIT 135 #define POWER7_PME_PM_NEST_PAIR2_AND 136 #define POWER7_PME_PM_VSU1_1FLOP 137 #define POWER7_PME_PM_IC_PREF_REQ 138 #define POWER7_PME_PM_L3_LD_HIT 139 #define POWER7_PME_PM_GCT_NOSLOT_IC_MISS 140 #define POWER7_PME_PM_DISP_HELD 141 #define POWER7_PME_PM_L2_LD 142 #define POWER7_PME_PM_LSU_FLUSH_SRQ 143 #define POWER7_PME_PM_BC_PLUS_8_CONV 144 #define POWER7_PME_PM_MRK_DATA_FROM_L31_MOD_CYC 145 #define POWER7_PME_PM_CMPLU_STALL_VECTOR_LONG 146 #define POWER7_PME_PM_L2_RCST_BUSY_RC_FULL 147 #define POWER7_PME_PM_TB_BIT_TRANS 148 #define POWER7_PME_PM_THERMAL_MAX 149 #define POWER7_PME_PM_LSU1_FLUSH_ULD 150 #define POWER7_PME_PM_LSU1_REJECT_LHS 151 #define POWER7_PME_PM_LSU_LRQ_S0_ALLOC 152 #define POWER7_PME_PM_L3_CO_L31 153 #define POWER7_PME_PM_POWER_EVENT4 154 #define POWER7_PME_PM_DATA_FROM_L31_SHR 155 #define POWER7_PME_PM_BR_UNCOND 156 #define POWER7_PME_PM_LSU1_DC_PREF_STREAM_ALLOC 157 #define POWER7_PME_PM_PMC4_REWIND 158 #define POWER7_PME_PM_L2_RCLD_DISP 159 #define POWER7_PME_PM_THRD_PRIO_2_3_CYC 160 #define POWER7_PME_PM_MRK_PTEG_FROM_L2MISS 161 #define POWER7_PME_PM_IC_DEMAND_L2_BHT_REDIRECT 162 #define POWER7_PME_PM_LSU_DERAT_MISS 163 #define POWER7_PME_PM_IC_PREF_CANCEL_L2 164 #define POWER7_PME_PM_MRK_FIN_STALL_CYC_COUNT 165 #define POWER7_PME_PM_BR_PRED_CCACHE 166 #define POWER7_PME_PM_GCT_UTIL_1_TO_2_SLOTS 167 #define POWER7_PME_PM_MRK_ST_CMPL_INT 168 #define POWER7_PME_PM_LSU_TWO_TABLEWALK_CYC 169 #define POWER7_PME_PM_MRK_DATA_FROM_L3MISS 170 #define POWER7_PME_PM_GCT_NOSLOT_CYC 171 #define POWER7_PME_PM_LSU_SET_MPRED 172 #define POWER7_PME_PM_FLUSH_DISP_TLBIE 173 #define POWER7_PME_PM_VSU1_FCONV 174 #define POWER7_PME_PM_DERAT_MISS_16G 175 #define POWER7_PME_PM_INST_FROM_LMEM 176 #define POWER7_PME_PM_IC_DEMAND_L2_BR_REDIRECT 177 #define POWER7_PME_PM_CMPLU_STALL_SCALAR_LONG 178 #define POWER7_PME_PM_INST_PTEG_FROM_L2 179 #define POWER7_PME_PM_PTEG_FROM_L2 180 #define POWER7_PME_PM_MRK_DATA_FROM_L21_SHR_CYC 181 #define POWER7_PME_PM_MRK_DTLB_MISS_4K 182 #define POWER7_PME_PM_VSU0_FPSCR 183 #define POWER7_PME_PM_VSU1_VECT_DOUBLE_ISSUED 184 #define POWER7_PME_PM_MRK_PTEG_FROM_RL2L3_MOD 185 #define POWER7_PME_PM_MEM0_RQ_DISP 186 #define POWER7_PME_PM_L2_LD_MISS 187 #define POWER7_PME_PM_VMX_RESULT_SAT_1 188 #define POWER7_PME_PM_L1_PREF 189 #define POWER7_PME_PM_MRK_DATA_FROM_LMEM_CYC 190 #define POWER7_PME_PM_GRP_IC_MISS_NONSPEC 191 #define POWER7_PME_PM_PB_NODE_PUMP 192 #define POWER7_PME_PM_SHL_MERGED 193 #define POWER7_PME_PM_NEST_PAIR1_ADD 194 #define POWER7_PME_PM_DATA_FROM_L3 195 #define POWER7_PME_PM_LSU_FLUSH 196 #define POWER7_PME_PM_LSU_SRQ_SYNC_COUNT 197 #define POWER7_PME_PM_PMC2_OVERFLOW 198 #define POWER7_PME_PM_LSU_LDF 199 #define POWER7_PME_PM_POWER_EVENT3 200 #define POWER7_PME_PM_DISP_WT 201 #define POWER7_PME_PM_CMPLU_STALL_REJECT 202 #define POWER7_PME_PM_IC_BANK_CONFLICT 203 #define POWER7_PME_PM_BR_MPRED_CR_TA 204 #define POWER7_PME_PM_L2_INST_MISS 205 #define POWER7_PME_PM_CMPLU_STALL_ERAT_MISS 206 #define POWER7_PME_PM_NEST_PAIR2_ADD 207 #define POWER7_PME_PM_MRK_LSU_FLUSH 208 #define POWER7_PME_PM_L2_LDST 209 #define POWER7_PME_PM_INST_FROM_L31_SHR 210 #define POWER7_PME_PM_VSU0_FIN 211 #define POWER7_PME_PM_LARX_LSU 212 #define POWER7_PME_PM_INST_FROM_RMEM 213 #define POWER7_PME_PM_DISP_CLB_HELD_TLBIE 214 #define POWER7_PME_PM_MRK_DATA_FROM_DMEM_CYC 215 #define POWER7_PME_PM_BR_PRED_CR 216 #define POWER7_PME_PM_LSU_REJECT 217 #define POWER7_PME_PM_GCT_UTIL_3_TO_6_SLOTS 218 #define POWER7_PME_PM_CMPLU_STALL_END_GCT_NOSLOT 219 #define POWER7_PME_PM_LSU0_REJECT_LMQ_FULL 220 #define POWER7_PME_PM_VSU_FEST 221 #define POWER7_PME_PM_NEST_PAIR0_AND 222 #define POWER7_PME_PM_PTEG_FROM_L3 223 #define POWER7_PME_PM_POWER_EVENT2 224 #define POWER7_PME_PM_IC_PREF_CANCEL_PAGE 225 #define POWER7_PME_PM_VSU0_FSQRT_FDIV 226 #define POWER7_PME_PM_MRK_GRP_CMPL 227 #define POWER7_PME_PM_VSU0_SCAL_DOUBLE_ISSUED 228 #define POWER7_PME_PM_GRP_DISP 229 #define POWER7_PME_PM_LSU0_LDX 230 #define POWER7_PME_PM_DATA_FROM_L2 231 #define POWER7_PME_PM_MRK_DATA_FROM_RL2L3_MOD 232 #define POWER7_PME_PM_LD_REF_L1 233 #define POWER7_PME_PM_VSU0_VECT_DOUBLE_ISSUED 234 #define POWER7_PME_PM_VSU1_2FLOP_DOUBLE 235 #define POWER7_PME_PM_THRD_PRIO_6_7_CYC 236 #define POWER7_PME_PM_BC_PLUS_8_RSLV_TAKEN 237 #define POWER7_PME_PM_BR_MPRED_CR 238 #define POWER7_PME_PM_L3_CO_MEM 239 #define POWER7_PME_PM_LD_MISS_L1 240 #define POWER7_PME_PM_DATA_FROM_RL2L3_MOD 241 #define POWER7_PME_PM_LSU_SRQ_FULL_CYC 242 #define POWER7_PME_PM_TABLEWALK_CYC 243 #define POWER7_PME_PM_MRK_PTEG_FROM_RMEM 244 #define POWER7_PME_PM_LSU_SRQ_STFWD 245 #define POWER7_PME_PM_INST_PTEG_FROM_RMEM 246 #define POWER7_PME_PM_FXU0_FIN 247 #define POWER7_PME_PM_LSU1_L1_SW_PREF 248 #define POWER7_PME_PM_PTEG_FROM_L31_MOD 249 #define POWER7_PME_PM_PMC5_OVERFLOW 250 #define POWER7_PME_PM_LD_REF_L1_LSU1 251 #define POWER7_PME_PM_INST_PTEG_FROM_L21_SHR 252 #define POWER7_PME_PM_CMPLU_STALL_THRD 253 #define POWER7_PME_PM_DATA_FROM_RMEM 254 #define POWER7_PME_PM_VSU0_SCAL_SINGLE_ISSUED 255 #define POWER7_PME_PM_BR_MPRED_LSTACK 256 #define POWER7_PME_PM_MRK_DATA_FROM_RL2L3_MOD_CYC 257 #define POWER7_PME_PM_LSU0_FLUSH_UST 258 #define POWER7_PME_PM_LSU_NCST 259 #define POWER7_PME_PM_BR_TAKEN 260 #define POWER7_PME_PM_INST_PTEG_FROM_LMEM 261 #define POWER7_PME_PM_GCT_NOSLOT_BR_MPRED_IC_MISS 262 #define POWER7_PME_PM_DTLB_MISS_4K 263 #define POWER7_PME_PM_PMC4_SAVED 264 #define POWER7_PME_PM_VSU1_PERMUTE_ISSUED 265 #define POWER7_PME_PM_SLB_MISS 266 #define POWER7_PME_PM_LSU1_FLUSH_LRQ 267 #define POWER7_PME_PM_DTLB_MISS 268 #define POWER7_PME_PM_VSU1_FRSP 269 #define POWER7_PME_PM_VSU_VECTOR_DOUBLE_ISSUED 270 #define POWER7_PME_PM_L2_CASTOUT_SHR 271 #define POWER7_PME_PM_DATA_FROM_DL2L3_SHR 272 #define POWER7_PME_PM_VSU1_STF 273 #define POWER7_PME_PM_ST_FIN 274 #define POWER7_PME_PM_PTEG_FROM_L21_SHR 275 #define POWER7_PME_PM_L2_LOC_GUESS_WRONG 276 #define POWER7_PME_PM_MRK_STCX_FAIL 277 #define POWER7_PME_PM_LSU0_REJECT_LHS 278 #define POWER7_PME_PM_IC_PREF_CANCEL_HIT 279 #define POWER7_PME_PM_L3_PREF_BUSY 280 #define POWER7_PME_PM_MRK_BRU_FIN 281 #define POWER7_PME_PM_LSU1_NCLD 282 #define POWER7_PME_PM_INST_PTEG_FROM_L31_MOD 283 #define POWER7_PME_PM_LSU_NCLD 284 #define POWER7_PME_PM_LSU_LDX 285 #define POWER7_PME_PM_L2_LOC_GUESS_CORRECT 286 #define POWER7_PME_PM_THRESH_TIMEO 287 #define POWER7_PME_PM_L3_PREF_ST 288 #define POWER7_PME_PM_DISP_CLB_HELD_SYNC 289 #define POWER7_PME_PM_VSU_SIMPLE_ISSUED 290 #define POWER7_PME_PM_VSU1_SINGLE 291 #define POWER7_PME_PM_DATA_TABLEWALK_CYC 292 #define POWER7_PME_PM_L2_RC_ST_DONE 293 #define POWER7_PME_PM_MRK_PTEG_FROM_L21_MOD 294 #define POWER7_PME_PM_LARX_LSU1 295 #define POWER7_PME_PM_MRK_DATA_FROM_RMEM 296 #define POWER7_PME_PM_DISP_CLB_HELD 297 #define POWER7_PME_PM_DERAT_MISS_4K 298 #define POWER7_PME_PM_L2_RCLD_DISP_FAIL_ADDR 299 #define POWER7_PME_PM_SEG_EXCEPTION 300 #define POWER7_PME_PM_FLUSH_DISP_SB 301 #define POWER7_PME_PM_L2_DC_INV 302 #define POWER7_PME_PM_PTEG_FROM_DL2L3_MOD 303 #define POWER7_PME_PM_DSEG 304 #define POWER7_PME_PM_BR_PRED_LSTACK 305 #define POWER7_PME_PM_VSU0_STF 306 #define POWER7_PME_PM_LSU_FX_FIN 307 #define POWER7_PME_PM_DERAT_MISS_16M 308 #define POWER7_PME_PM_MRK_PTEG_FROM_DL2L3_MOD 309 #define POWER7_PME_PM_GCT_UTIL_11_PLUS_SLOTS 310 #define POWER7_PME_PM_INST_FROM_L3 311 #define POWER7_PME_PM_MRK_IFU_FIN 312 #define POWER7_PME_PM_ITLB_MISS 313 #define POWER7_PME_PM_VSU_STF 314 #define POWER7_PME_PM_LSU_FLUSH_UST 315 #define POWER7_PME_PM_L2_LDST_MISS 316 #define POWER7_PME_PM_FXU1_FIN 317 #define POWER7_PME_PM_SHL_DEALLOCATED 318 #define POWER7_PME_PM_L2_SN_M_WR_DONE 319 #define POWER7_PME_PM_LSU_REJECT_SET_MPRED 320 #define POWER7_PME_PM_L3_PREF_LD 321 #define POWER7_PME_PM_L2_SN_M_RD_DONE 322 #define POWER7_PME_PM_MRK_DERAT_MISS_16G 323 #define POWER7_PME_PM_VSU_FCONV 324 #define POWER7_PME_PM_ANY_THRD_RUN_CYC 325 #define POWER7_PME_PM_LSU_LMQ_FULL_CYC 326 #define POWER7_PME_PM_MRK_LSU_REJECT_LHS 327 #define POWER7_PME_PM_MRK_LD_MISS_L1_CYC 328 #define POWER7_PME_PM_MRK_DATA_FROM_L2_CYC 329 #define POWER7_PME_PM_INST_IMC_MATCH_DISP 330 #define POWER7_PME_PM_MRK_DATA_FROM_RMEM_CYC 331 #define POWER7_PME_PM_VSU0_SIMPLE_ISSUED 332 #define POWER7_PME_PM_CMPLU_STALL_DIV 333 #define POWER7_PME_PM_MRK_PTEG_FROM_RL2L3_SHR 334 #define POWER7_PME_PM_VSU_FMA_DOUBLE 335 #define POWER7_PME_PM_VSU_4FLOP 336 #define POWER7_PME_PM_VSU1_FIN 337 #define POWER7_PME_PM_NEST_PAIR1_AND 338 #define POWER7_PME_PM_INST_PTEG_FROM_RL2L3_MOD 339 #define POWER7_PME_PM_RUN_CYC 340 #define POWER7_PME_PM_PTEG_FROM_RMEM 341 #define POWER7_PME_PM_LSU_LRQ_S0_VALID 342 #define POWER7_PME_PM_LSU0_LDF 343 #define POWER7_PME_PM_FLUSH_COMPLETION 344 #define POWER7_PME_PM_ST_MISS_L1 345 #define POWER7_PME_PM_L2_NODE_PUMP 346 #define POWER7_PME_PM_INST_FROM_DL2L3_SHR 347 #define POWER7_PME_PM_MRK_STALL_CMPLU_CYC 348 #define POWER7_PME_PM_VSU1_DENORM 349 #define POWER7_PME_PM_MRK_DATA_FROM_L31_SHR_CYC 350 #define POWER7_PME_PM_NEST_PAIR0_ADD 351 #define POWER7_PME_PM_INST_FROM_L3MISS 352 #define POWER7_PME_PM_EE_OFF_EXT_INT 353 #define POWER7_PME_PM_INST_PTEG_FROM_DMEM 354 #define POWER7_PME_PM_INST_FROM_DL2L3_MOD 355 #define POWER7_PME_PM_PMC6_OVERFLOW 356 #define POWER7_PME_PM_VSU_2FLOP_DOUBLE 357 #define POWER7_PME_PM_TLB_MISS 358 #define POWER7_PME_PM_FXU_BUSY 359 #define POWER7_PME_PM_L2_RCLD_DISP_FAIL_OTHER 360 #define POWER7_PME_PM_LSU_REJECT_LMQ_FULL 361 #define POWER7_PME_PM_IC_RELOAD_SHR 362 #define POWER7_PME_PM_GRP_MRK 363 #define POWER7_PME_PM_MRK_ST_NEST 364 #define POWER7_PME_PM_VSU1_FSQRT_FDIV 365 #define POWER7_PME_PM_LSU0_FLUSH_LRQ 366 #define POWER7_PME_PM_LARX_LSU0 367 #define POWER7_PME_PM_IBUF_FULL_CYC 368 #define POWER7_PME_PM_MRK_DATA_FROM_DL2L3_SHR_CYC 369 #define POWER7_PME_PM_LSU_DC_PREF_STREAM_ALLOC 370 #define POWER7_PME_PM_GRP_MRK_CYC 371 #define POWER7_PME_PM_MRK_DATA_FROM_RL2L3_SHR_CYC 372 #define POWER7_PME_PM_L2_GLOB_GUESS_CORRECT 373 #define POWER7_PME_PM_LSU_REJECT_LHS 374 #define POWER7_PME_PM_MRK_DATA_FROM_LMEM 375 #define POWER7_PME_PM_INST_PTEG_FROM_L3 376 #define POWER7_PME_PM_FREQ_DOWN 377 #define POWER7_PME_PM_PB_RETRY_NODE_PUMP 378 #define POWER7_PME_PM_INST_FROM_RL2L3_SHR 379 #define POWER7_PME_PM_MRK_INST_ISSUED 380 #define POWER7_PME_PM_PTEG_FROM_L3MISS 381 #define POWER7_PME_PM_RUN_PURR 382 #define POWER7_PME_PM_MRK_GRP_IC_MISS 383 #define POWER7_PME_PM_MRK_DATA_FROM_L3 384 #define POWER7_PME_PM_CMPLU_STALL_DCACHE_MISS 385 #define POWER7_PME_PM_PTEG_FROM_RL2L3_SHR 386 #define POWER7_PME_PM_LSU_FLUSH_LRQ 387 #define POWER7_PME_PM_MRK_DERAT_MISS_64K 388 #define POWER7_PME_PM_INST_PTEG_FROM_DL2L3_MOD 389 #define POWER7_PME_PM_L2_ST_MISS 390 #define POWER7_PME_PM_MRK_PTEG_FROM_L21_SHR 391 #define POWER7_PME_PM_LWSYNC 392 #define POWER7_PME_PM_LSU0_DC_PREF_STREAM_CONFIRM_STRIDE 393 #define POWER7_PME_PM_MRK_LSU_FLUSH_LRQ 394 #define POWER7_PME_PM_INST_IMC_MATCH_CMPL 395 #define POWER7_PME_PM_NEST_PAIR3_AND 396 #define POWER7_PME_PM_PB_RETRY_SYS_PUMP 397 #define POWER7_PME_PM_MRK_INST_FIN 398 #define POWER7_PME_PM_MRK_PTEG_FROM_DL2L3_SHR 399 #define POWER7_PME_PM_INST_FROM_L31_MOD 400 #define POWER7_PME_PM_MRK_DTLB_MISS_64K 401 #define POWER7_PME_PM_LSU_FIN 402 #define POWER7_PME_PM_MRK_LSU_REJECT 403 #define POWER7_PME_PM_L2_CO_FAIL_BUSY 404 #define POWER7_PME_PM_MEM0_WQ_DISP 405 #define POWER7_PME_PM_DATA_FROM_L31_MOD 406 #define POWER7_PME_PM_THERMAL_WARN 407 #define POWER7_PME_PM_VSU0_4FLOP 408 #define POWER7_PME_PM_BR_MPRED_CCACHE 409 #define POWER7_PME_PM_CMPLU_STALL_IFU 410 #define POWER7_PME_PM_L1_DEMAND_WRITE 411 #define POWER7_PME_PM_FLUSH_BR_MPRED 412 #define POWER7_PME_PM_MRK_DTLB_MISS_16G 413 #define POWER7_PME_PM_MRK_PTEG_FROM_DMEM 414 #define POWER7_PME_PM_L2_RCST_DISP 415 #define POWER7_PME_PM_CMPLU_STALL 416 #define POWER7_PME_PM_LSU_PARTIAL_CDF 417 #define POWER7_PME_PM_DISP_CLB_HELD_SB 418 #define POWER7_PME_PM_VSU0_FMA_DOUBLE 419 #define POWER7_PME_PM_FXU0_BUSY_FXU1_IDLE 420 #define POWER7_PME_PM_IC_DEMAND_CYC 421 #define POWER7_PME_PM_MRK_DATA_FROM_L21_SHR 422 #define POWER7_PME_PM_MRK_LSU_FLUSH_UST 423 #define POWER7_PME_PM_INST_PTEG_FROM_L3MISS 424 #define POWER7_PME_PM_VSU_DENORM 425 #define POWER7_PME_PM_MRK_LSU_PARTIAL_CDF 426 #define POWER7_PME_PM_INST_FROM_L21_SHR 427 #define POWER7_PME_PM_IC_PREF_WRITE 428 #define POWER7_PME_PM_BR_PRED 429 #define POWER7_PME_PM_INST_FROM_DMEM 430 #define POWER7_PME_PM_IC_PREF_CANCEL_ALL 431 #define POWER7_PME_PM_LSU_DC_PREF_STREAM_CONFIRM 432 #define POWER7_PME_PM_MRK_LSU_FLUSH_SRQ 433 #define POWER7_PME_PM_MRK_FIN_STALL_CYC 434 #define POWER7_PME_PM_L2_RCST_DISP_FAIL_OTHER 435 #define POWER7_PME_PM_VSU1_DD_ISSUED 436 #define POWER7_PME_PM_PTEG_FROM_L31_SHR 437 #define POWER7_PME_PM_DATA_FROM_L21_SHR 438 #define POWER7_PME_PM_LSU0_NCLD 439 #define POWER7_PME_PM_VSU1_4FLOP 440 #define POWER7_PME_PM_VSU1_8FLOP 441 #define POWER7_PME_PM_VSU_8FLOP 442 #define POWER7_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC 443 #define POWER7_PME_PM_DTLB_MISS_64K 444 #define POWER7_PME_PM_THRD_CONC_RUN_INST 445 #define POWER7_PME_PM_MRK_PTEG_FROM_L2 446 #define POWER7_PME_PM_PB_SYS_PUMP 447 #define POWER7_PME_PM_VSU_FIN 448 #define POWER7_PME_PM_MRK_DATA_FROM_L31_MOD 449 #define POWER7_PME_PM_THRD_PRIO_0_1_CYC 450 #define POWER7_PME_PM_DERAT_MISS_64K 451 #define POWER7_PME_PM_PMC2_REWIND 452 #define POWER7_PME_PM_INST_FROM_L2 453 #define POWER7_PME_PM_GRP_BR_MPRED_NONSPEC 454 #define POWER7_PME_PM_INST_DISP 455 #define POWER7_PME_PM_MEM0_RD_CANCEL_TOTAL 456 #define POWER7_PME_PM_LSU0_DC_PREF_STREAM_CONFIRM 457 #define POWER7_PME_PM_L1_DCACHE_RELOAD_VALID 458 #define POWER7_PME_PM_VSU_SCALAR_DOUBLE_ISSUED 459 #define POWER7_PME_PM_L3_PREF_HIT 460 #define POWER7_PME_PM_MRK_PTEG_FROM_L31_MOD 461 #define POWER7_PME_PM_CMPLU_STALL_STORE 462 #define POWER7_PME_PM_MRK_FXU_FIN 463 #define POWER7_PME_PM_PMC4_OVERFLOW 464 #define POWER7_PME_PM_MRK_PTEG_FROM_L3 465 #define POWER7_PME_PM_LSU0_LMQ_LHR_MERGE 466 #define POWER7_PME_PM_BTAC_HIT 467 #define POWER7_PME_PM_L3_RD_BUSY 468 #define POWER7_PME_PM_LSU0_L1_SW_PREF 469 #define POWER7_PME_PM_INST_FROM_L2MISS 470 #define POWER7_PME_PM_LSU0_DC_PREF_STREAM_ALLOC 471 #define POWER7_PME_PM_L2_ST 472 #define POWER7_PME_PM_VSU0_DENORM 473 #define POWER7_PME_PM_MRK_DATA_FROM_DL2L3_SHR 474 #define POWER7_PME_PM_BR_PRED_CR_TA 475 #define POWER7_PME_PM_VSU0_FCONV 476 #define POWER7_PME_PM_MRK_LSU_FLUSH_ULD 477 #define POWER7_PME_PM_BTAC_MISS 478 #define POWER7_PME_PM_MRK_LD_MISS_EXPOSED_CYC_COUNT 479 #define POWER7_PME_PM_MRK_DATA_FROM_L2 480 #define POWER7_PME_PM_LSU_DCACHE_RELOAD_VALID 481 #define POWER7_PME_PM_VSU_FMA 482 #define POWER7_PME_PM_LSU0_FLUSH_SRQ 483 #define POWER7_PME_PM_LSU1_L1_PREF 484 #define POWER7_PME_PM_IOPS_CMPL 485 #define POWER7_PME_PM_L2_SYS_PUMP 486 #define POWER7_PME_PM_L2_RCLD_BUSY_RC_FULL 487 #define POWER7_PME_PM_LSU_LMQ_S0_ALLOC 488 #define POWER7_PME_PM_FLUSH_DISP_SYNC 489 #define POWER7_PME_PM_MRK_DATA_FROM_DL2L3_MOD_CYC 490 #define POWER7_PME_PM_L2_IC_INV 491 #define POWER7_PME_PM_MRK_DATA_FROM_L21_MOD_CYC 492 #define POWER7_PME_PM_L3_PREF_LDST 493 #define POWER7_PME_PM_LSU_SRQ_EMPTY_CYC 494 #define POWER7_PME_PM_LSU_LMQ_S0_VALID 495 #define POWER7_PME_PM_FLUSH_PARTIAL 496 #define POWER7_PME_PM_VSU1_FMA_DOUBLE 497 #define POWER7_PME_PM_1PLUS_PPC_DISP 498 #define POWER7_PME_PM_DATA_FROM_L2MISS 499 #define POWER7_PME_PM_SUSPENDED 500 #define POWER7_PME_PM_VSU0_FMA 501 #define POWER7_PME_PM_CMPLU_STALL_SCALAR 502 #define POWER7_PME_PM_STCX_FAIL 503 #define POWER7_PME_PM_VSU0_FSQRT_FDIV_DOUBLE 504 #define POWER7_PME_PM_DC_PREF_DST 505 #define POWER7_PME_PM_VSU1_SCAL_SINGLE_ISSUED 506 #define POWER7_PME_PM_L3_HIT 507 #define POWER7_PME_PM_L2_GLOB_GUESS_WRONG 508 #define POWER7_PME_PM_MRK_DFU_FIN 509 #define POWER7_PME_PM_INST_FROM_L1 510 #define POWER7_PME_PM_BRU_FIN 511 #define POWER7_PME_PM_IC_DEMAND_REQ 512 #define POWER7_PME_PM_VSU1_FSQRT_FDIV_DOUBLE 513 #define POWER7_PME_PM_VSU1_FMA 514 #define POWER7_PME_PM_MRK_LD_MISS_L1 515 #define POWER7_PME_PM_VSU0_2FLOP_DOUBLE 516 #define POWER7_PME_PM_LSU_DC_PREF_STRIDED_STREAM_CONFIRM 517 #define POWER7_PME_PM_INST_PTEG_FROM_L31_SHR 518 #define POWER7_PME_PM_MRK_LSU_REJECT_ERAT_MISS 519 #define POWER7_PME_PM_MRK_DATA_FROM_L2MISS 520 #define POWER7_PME_PM_DATA_FROM_RL2L3_SHR 521 #define POWER7_PME_PM_INST_FROM_PREF 522 #define POWER7_PME_PM_VSU1_SQ 523 #define POWER7_PME_PM_L2_LD_DISP 524 #define POWER7_PME_PM_L2_DISP_ALL 525 #define POWER7_PME_PM_THRD_GRP_CMPL_BOTH_CYC 526 #define POWER7_PME_PM_VSU_FSQRT_FDIV_DOUBLE 527 #define POWER7_PME_PM_BR_MPRED 528 #define POWER7_PME_PM_INST_PTEG_FROM_DL2L3_SHR 529 #define POWER7_PME_PM_VSU_1FLOP 530 #define POWER7_PME_PM_HV_CYC 531 #define POWER7_PME_PM_MRK_LSU_FIN 532 #define POWER7_PME_PM_MRK_DATA_FROM_RL2L3_SHR 533 #define POWER7_PME_PM_DTLB_MISS_16M 534 #define POWER7_PME_PM_LSU1_LMQ_LHR_MERGE 535 #define POWER7_PME_PM_IFU_FIN 536 #define POWER7_PME_PM_1THRD_CON_RUN_INSTR 537 #define POWER7_PME_PM_CMPLU_STALL_COUNT 538 #define POWER7_PME_PM_MEM0_PB_RD_CL 539 #define POWER7_PME_PM_THRD_1_RUN_CYC 540 #define POWER7_PME_PM_THRD_2_CONC_RUN_INSTR 541 #define POWER7_PME_PM_THRD_2_RUN_CYC 542 #define POWER7_PME_PM_THRD_3_CONC_RUN_INST 543 #define POWER7_PME_PM_THRD_3_RUN_CYC 544 #define POWER7_PME_PM_THRD_4_CONC_RUN_INST 545 #define POWER7_PME_PM_THRD_4_RUN_CYC 546 static const pme_power_entry_t power7_pe[] = { [ POWER7_PME_PM_IC_DEMAND_L2_BR_ALL ] = { .pme_name = "PM_IC_DEMAND_L2_BR_ALL", .pme_code = 0x4898, .pme_short_desc = " L2 I cache demand request due to BHT or redirect", .pme_long_desc = " L2 I cache demand request due to BHT or redirect", }, [ POWER7_PME_PM_GCT_UTIL_7_TO_10_SLOTS ] = { .pme_name = "PM_GCT_UTIL_7_TO_10_SLOTS", .pme_code = 0x20a0, .pme_short_desc = "GCT Utilization 7-10 entries", .pme_long_desc = "GCT Utilization 7-10 entries", }, [ POWER7_PME_PM_PMC2_SAVED ] = { .pme_name = "PM_PMC2_SAVED", .pme_code = 0x10022, .pme_short_desc = "PMC2 Rewind Value saved", .pme_long_desc = "PMC2 was counting speculatively. The speculative condition was met and the counter value was committed by copying it to the backup register.", }, [ POWER7_PME_PM_CMPLU_STALL_DFU ] = { .pme_name = "PM_CMPLU_STALL_DFU", .pme_code = 0x2003c, .pme_short_desc = "Completion stall caused by Decimal Floating Point Unit", .pme_long_desc = "Completion stall caused by Decimal Floating Point Unit", }, [ POWER7_PME_PM_VSU0_16FLOP ] = { .pme_name = "PM_VSU0_16FLOP", .pme_code = 0xa0a4, .pme_short_desc = "Sixteen flops operation (SP vector versions of fdiv,fsqrt) ", .pme_long_desc = "Sixteen flops operation (SP vector versions of fdiv,fsqrt) ", }, [ POWER7_PME_PM_MRK_LSU_DERAT_MISS ] = { .pme_name = "PM_MRK_LSU_DERAT_MISS", .pme_code = 0x3d05a, .pme_short_desc = "Marked DERAT Miss", .pme_long_desc = "Marked DERAT Miss", }, [ POWER7_PME_PM_MRK_ST_CMPL ] = { .pme_name = "PM_MRK_ST_CMPL", .pme_code = 0x10034, .pme_short_desc = "marked store finished (was complete)", .pme_long_desc = "A sampled store has completed (data home)", }, [ POWER7_PME_PM_NEST_PAIR3_ADD ] = { .pme_name = "PM_NEST_PAIR3_ADD", .pme_code = 0x40881, .pme_short_desc = " Nest events (MC0/MC1/PB/GX), Pair3 ADD", .pme_long_desc = " Nest events (MC0/MC1/PB/GX), Pair3 ADD", }, [ POWER7_PME_PM_L2_ST_DISP ] = { .pme_name = "PM_L2_ST_DISP", .pme_code = 0x46180, .pme_short_desc = "All successful store dispatches", .pme_long_desc = "All successful store dispatches", }, [ POWER7_PME_PM_L2_CASTOUT_MOD ] = { .pme_name = "PM_L2_CASTOUT_MOD", .pme_code = 0x16180, .pme_short_desc = "L2 Castouts - Modified (M, Mu, Me)", .pme_long_desc = "An L2 line in the Modified state was castout. Total for all slices.", }, [ POWER7_PME_PM_ISEG ] = { .pme_name = "PM_ISEG", .pme_code = 0x20a4, .pme_short_desc = "ISEG Exception", .pme_long_desc = "ISEG Exception", }, [ POWER7_PME_PM_MRK_INST_TIMEO ] = { .pme_name = "PM_MRK_INST_TIMEO", .pme_code = 0x40034, .pme_short_desc = "marked Instruction finish timeout ", .pme_long_desc = "The number of instructions finished since the last progress indicator from a marked instruction exceeded the threshold. The marked instruction was flushed.", }, [ POWER7_PME_PM_L2_RCST_DISP_FAIL_ADDR ] = { .pme_name = "PM_L2_RCST_DISP_FAIL_ADDR", .pme_code = 0x36282, .pme_short_desc = " L2 RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ", .pme_long_desc = " L2 RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ", }, [ POWER7_PME_PM_LSU1_DC_PREF_STREAM_CONFIRM ] = { .pme_name = "PM_LSU1_DC_PREF_STREAM_CONFIRM", .pme_code = 0xd0b6, .pme_short_desc = "LS1 'Dcache prefetch stream confirmed", .pme_long_desc = "LS1 'Dcache prefetch stream confirmed", }, [ POWER7_PME_PM_IERAT_WR_64K ] = { .pme_name = "PM_IERAT_WR_64K", .pme_code = 0x40be, .pme_short_desc = "large page 64k ", .pme_long_desc = "large page 64k ", }, [ POWER7_PME_PM_MRK_DTLB_MISS_16M ] = { .pme_name = "PM_MRK_DTLB_MISS_16M", .pme_code = 0x4d05e, .pme_short_desc = "Marked Data TLB misses for 16M page", .pme_long_desc = "Data TLB references to 16M pages by a marked instruction that missed the TLB. Page size is determined at TLB reload time.", }, [ POWER7_PME_PM_IERAT_MISS ] = { .pme_name = "PM_IERAT_MISS", .pme_code = 0x100f6, .pme_short_desc = "IERAT Miss (Not implemented as DI on POWER6)", .pme_long_desc = "A translation request missed the Instruction Effective to Real Address Translation (ERAT) table", }, [ POWER7_PME_PM_MRK_PTEG_FROM_LMEM ] = { .pme_name = "PM_MRK_PTEG_FROM_LMEM", .pme_code = 0x4d052, .pme_short_desc = "Marked PTEG loaded from local memory", .pme_long_desc = "A Page Table Entry was loaded into the ERAT from memory attached to the same module this proccessor is located on due to a marked load or store.", }, [ POWER7_PME_PM_FLOP ] = { .pme_name = "PM_FLOP", .pme_code = 0x100f4, .pme_short_desc = "Floating Point Operation Finished", .pme_long_desc = "A floating point operation has completed", }, [ POWER7_PME_PM_THRD_PRIO_4_5_CYC ] = { .pme_name = "PM_THRD_PRIO_4_5_CYC", .pme_code = 0x40b4, .pme_short_desc = " Cycles thread running at priority level 4 or 5", .pme_long_desc = " Cycles thread running at priority level 4 or 5", }, [ POWER7_PME_PM_BR_PRED_TA ] = { .pme_name = "PM_BR_PRED_TA", .pme_code = 0x40aa, .pme_short_desc = "Branch predict - target address", .pme_long_desc = "The target address of a branch instruction was predicted.", }, [ POWER7_PME_PM_CMPLU_STALL_FXU ] = { .pme_name = "PM_CMPLU_STALL_FXU", .pme_code = 0x20014, .pme_short_desc = "Completion stall caused by FXU instruction", .pme_long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes was a fixed point instruction.", }, [ POWER7_PME_PM_EXT_INT ] = { .pme_name = "PM_EXT_INT", .pme_code = 0x200f8, .pme_short_desc = "external interrupt", .pme_long_desc = "An interrupt due to an external exception occurred", }, [ POWER7_PME_PM_VSU_FSQRT_FDIV ] = { .pme_name = "PM_VSU_FSQRT_FDIV", .pme_code = 0xa888, .pme_short_desc = "four flops operation (fdiv,fsqrt) Scalar Instructions only!", .pme_long_desc = "DP vector versions of fdiv,fsqrt ", }, [ POWER7_PME_PM_MRK_LD_MISS_EXPOSED_CYC ] = { .pme_name = "PM_MRK_LD_MISS_EXPOSED_CYC", .pme_code = 0x1003e, .pme_short_desc = "Marked Load exposed Miss ", .pme_long_desc = "Marked Load exposed Miss ", }, [ POWER7_PME_PM_LSU1_LDF ] = { .pme_name = "PM_LSU1_LDF", .pme_code = 0xc086, .pme_short_desc = "LS1 Scalar Loads ", .pme_long_desc = "A floating point load was executed by LSU1", }, [ POWER7_PME_PM_IC_WRITE_ALL ] = { .pme_name = "PM_IC_WRITE_ALL", .pme_code = 0x488c, .pme_short_desc = "Icache sectors written, prefetch + demand", .pme_long_desc = "Icache sectors written, prefetch + demand", }, [ POWER7_PME_PM_LSU0_SRQ_STFWD ] = { .pme_name = "PM_LSU0_SRQ_STFWD", .pme_code = 0xc0a0, .pme_short_desc = "LS0 SRQ forwarded data to a load", .pme_long_desc = "Data from a store instruction was forwarded to a load on unit 0. A load that misses L1 but becomes a store forward is treated as a load miss and it causes the DL1 load miss event to be counted. It does not go into the LMQ. If a load that hits L1 but becomes a store forward, then it's not treated as a load miss.", }, [ POWER7_PME_PM_PTEG_FROM_RL2L3_MOD ] = { .pme_name = "PM_PTEG_FROM_RL2L3_MOD", .pme_code = 0x1c052, .pme_short_desc = "PTEG loaded from remote L2 or L3 modified", .pme_long_desc = "A Page Table Entry was loaded into the ERAT with modified (M) data from an L2 or L3 on a remote module due to a demand load or store.", }, [ POWER7_PME_PM_MRK_DATA_FROM_L31_SHR ] = { .pme_name = "PM_MRK_DATA_FROM_L31_SHR", .pme_code = 0x1d04e, .pme_short_desc = "Marked data loaded from another L3 on same chip shared", .pme_long_desc = "Marked data loaded from another L3 on same chip shared", }, [ POWER7_PME_PM_DATA_FROM_L21_MOD ] = { .pme_name = "PM_DATA_FROM_L21_MOD", .pme_code = 0x3c046, .pme_short_desc = "Data loaded from another L2 on same chip modified", .pme_long_desc = "Data loaded from another L2 on same chip modified", }, [ POWER7_PME_PM_VSU1_SCAL_DOUBLE_ISSUED ] = { .pme_name = "PM_VSU1_SCAL_DOUBLE_ISSUED", .pme_code = 0xb08a, .pme_short_desc = "Double Precision scalar instruction issued on Pipe1", .pme_long_desc = "Double Precision scalar instruction issued on Pipe1", }, [ POWER7_PME_PM_VSU0_8FLOP ] = { .pme_name = "PM_VSU0_8FLOP", .pme_code = 0xa0a0, .pme_short_desc = "eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) ", .pme_long_desc = "eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) ", }, [ POWER7_PME_PM_POWER_EVENT1 ] = { .pme_name = "PM_POWER_EVENT1", .pme_code = 0x1006e, .pme_short_desc = "Power Management Event 1", .pme_long_desc = "Power Management Event 1", }, [ POWER7_PME_PM_DISP_CLB_HELD_BAL ] = { .pme_name = "PM_DISP_CLB_HELD_BAL", .pme_code = 0x2092, .pme_short_desc = "Dispatch/CLB Hold: Balance", .pme_long_desc = "Dispatch/CLB Hold: Balance", }, [ POWER7_PME_PM_VSU1_2FLOP ] = { .pme_name = "PM_VSU1_2FLOP", .pme_code = 0xa09a, .pme_short_desc = "two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions)", .pme_long_desc = "two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions)", }, [ POWER7_PME_PM_LWSYNC_HELD ] = { .pme_name = "PM_LWSYNC_HELD", .pme_code = 0x209a, .pme_short_desc = "LWSYNC held at dispatch", .pme_long_desc = "Cycles a LWSYNC instruction was held at dispatch. LWSYNC instructions are held at dispatch until all previous loads are done and all previous stores have issued. LWSYNC enters the Store Request Queue and is sent to the storage subsystem but does not wait for a response.", }, [ POWER7_PME_PM_PTEG_FROM_DL2L3_SHR ] = { .pme_name = "PM_PTEG_FROM_DL2L3_SHR", .pme_code = 0x3c054, .pme_short_desc = "PTEG loaded from remote L2 or L3 shared", .pme_long_desc = "A Page Table Entry was loaded into the ERAT with shared (T or SL) data from an L2 or L3 on a remote module due to a demand load or store.", }, [ POWER7_PME_PM_INST_FROM_L21_MOD ] = { .pme_name = "PM_INST_FROM_L21_MOD", .pme_code = 0x34046, .pme_short_desc = "Instruction fetched from another L2 on same chip modified", .pme_long_desc = "Instruction fetched from another L2 on same chip modified", }, [ POWER7_PME_PM_IERAT_XLATE_WR_16MPLUS ] = { .pme_name = "PM_IERAT_XLATE_WR_16MPLUS", .pme_code = 0x40bc, .pme_short_desc = "large page 16M+", .pme_long_desc = "large page 16M+", }, [ POWER7_PME_PM_IC_REQ_ALL ] = { .pme_name = "PM_IC_REQ_ALL", .pme_code = 0x4888, .pme_short_desc = "Icache requests, prefetch + demand", .pme_long_desc = "Icache requests, prefetch + demand", }, [ POWER7_PME_PM_DSLB_MISS ] = { .pme_name = "PM_DSLB_MISS", .pme_code = 0xd090, .pme_short_desc = "Data SLB Miss - Total of all segment sizes", .pme_long_desc = "A SLB miss for a data request occurred. SLB misses trap to the operating system to resolve.", }, [ POWER7_PME_PM_L3_MISS ] = { .pme_name = "PM_L3_MISS", .pme_code = 0x1f082, .pme_short_desc = "L3 Misses ", .pme_long_desc = "L3 Misses ", }, [ POWER7_PME_PM_LSU0_L1_PREF ] = { .pme_name = "PM_LSU0_L1_PREF", .pme_code = 0xd0b8, .pme_short_desc = " LS0 L1 cache data prefetches", .pme_long_desc = " LS0 L1 cache data prefetches", }, [ POWER7_PME_PM_VSU_SCALAR_SINGLE_ISSUED ] = { .pme_name = "PM_VSU_SCALAR_SINGLE_ISSUED", .pme_code = 0xb884, .pme_short_desc = "Single Precision scalar instruction issued on Pipe0", .pme_long_desc = "Single Precision scalar instruction issued on Pipe0", }, [ POWER7_PME_PM_LSU1_DC_PREF_STREAM_CONFIRM_STRIDE ] = { .pme_name = "PM_LSU1_DC_PREF_STREAM_CONFIRM_STRIDE", .pme_code = 0xd0be, .pme_short_desc = "LS1 Dcache Strided prefetch stream confirmed", .pme_long_desc = "LS1 Dcache Strided prefetch stream confirmed", }, [ POWER7_PME_PM_L2_INST ] = { .pme_name = "PM_L2_INST", .pme_code = 0x36080, .pme_short_desc = "Instruction Load Count", .pme_long_desc = "Instruction Load Count", }, [ POWER7_PME_PM_VSU0_FRSP ] = { .pme_name = "PM_VSU0_FRSP", .pme_code = 0xa0b4, .pme_short_desc = "Round to single precision instruction executed", .pme_long_desc = "Round to single precision instruction executed", }, [ POWER7_PME_PM_FLUSH_DISP ] = { .pme_name = "PM_FLUSH_DISP", .pme_code = 0x2082, .pme_short_desc = "Dispatch flush", .pme_long_desc = "Dispatch flush", }, [ POWER7_PME_PM_PTEG_FROM_L2MISS ] = { .pme_name = "PM_PTEG_FROM_L2MISS", .pme_code = 0x4c058, .pme_short_desc = "PTEG loaded from L2 miss", .pme_long_desc = "A Page Table Entry was loaded into the TLB but not from the local L2.", }, [ POWER7_PME_PM_VSU1_DQ_ISSUED ] = { .pme_name = "PM_VSU1_DQ_ISSUED", .pme_code = 0xb09a, .pme_short_desc = "128BIT Decimal Issued on Pipe1", .pme_long_desc = "128BIT Decimal Issued on Pipe1", }, [ POWER7_PME_PM_CMPLU_STALL_LSU ] = { .pme_name = "PM_CMPLU_STALL_LSU", .pme_code = 0x20012, .pme_short_desc = "Completion stall caused by LSU instruction", .pme_long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes was a load/store instruction.", }, [ POWER7_PME_PM_MRK_DATA_FROM_DMEM ] = { .pme_name = "PM_MRK_DATA_FROM_DMEM", .pme_code = 0x1d04a, .pme_short_desc = "Marked data loaded from distant memory", .pme_long_desc = "The processor's Data Cache was reloaded with data from memory attached to a distant module due to a marked load.", }, [ POWER7_PME_PM_LSU_FLUSH_ULD ] = { .pme_name = "PM_LSU_FLUSH_ULD", .pme_code = 0xc8b0, .pme_short_desc = "Flush: Unaligned Load", .pme_long_desc = "A load was flushed because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1). Combined Unit 0 + 1.", }, [ POWER7_PME_PM_PTEG_FROM_LMEM ] = { .pme_name = "PM_PTEG_FROM_LMEM", .pme_code = 0x4c052, .pme_short_desc = "PTEG loaded from local memory", .pme_long_desc = "A Page Table Entry was loaded into the TLB from memory attached to the same module this proccessor is located on.", }, [ POWER7_PME_PM_MRK_DERAT_MISS_16M ] = { .pme_name = "PM_MRK_DERAT_MISS_16M", .pme_code = 0x3d05c, .pme_short_desc = "Marked DERAT misses for 16M page", .pme_long_desc = "A marked data request (load or store) missed the ERAT for 16M page and resulted in an ERAT reload.", }, [ POWER7_PME_PM_THRD_ALL_RUN_CYC ] = { .pme_name = "PM_THRD_ALL_RUN_CYC", .pme_code = 0x2000c, .pme_short_desc = "All Threads in run_cycles", .pme_long_desc = "Cycles when all threads had their run latches set. Operating systems use the run latch to indicate when they are doing useful work.", }, [ POWER7_PME_PM_MEM0_PREFETCH_DISP ] = { .pme_name = "PM_MEM0_PREFETCH_DISP", .pme_code = 0x20083, .pme_short_desc = " Nest events (MC0/MC1/PB/GX), Pair1 Bit1", .pme_long_desc = " Nest events (MC0/MC1/PB/GX), Pair1 Bit1", }, [ POWER7_PME_PM_MRK_STALL_CMPLU_CYC_COUNT ] = { .pme_name = "PM_MRK_STALL_CMPLU_CYC_COUNT", .pme_code = 0x3003f, .pme_short_desc = "Marked Group Completion Stall cycles (use edge detect to count #)", .pme_long_desc = "Marked Group Completion Stall cycles (use edge detect to count #)", }, [ POWER7_PME_PM_DATA_FROM_DL2L3_MOD ] = { .pme_name = "PM_DATA_FROM_DL2L3_MOD", .pme_code = 0x3c04c, .pme_short_desc = "Data loaded from distant L2 or L3 modified", .pme_long_desc = "The processor's Data Cache was reloaded with modified (M) data from an L2 or L3 on a distant module due to a demand load", }, [ POWER7_PME_PM_VSU_FRSP ] = { .pme_name = "PM_VSU_FRSP", .pme_code = 0xa8b4, .pme_short_desc = "Round to single precision instruction executed", .pme_long_desc = "Round to single precision instruction executed", }, [ POWER7_PME_PM_MRK_DATA_FROM_L21_MOD ] = { .pme_name = "PM_MRK_DATA_FROM_L21_MOD", .pme_code = 0x3d046, .pme_short_desc = "Marked data loaded from another L2 on same chip modified", .pme_long_desc = "Marked data loaded from another L2 on same chip modified", }, [ POWER7_PME_PM_PMC1_OVERFLOW ] = { .pme_name = "PM_PMC1_OVERFLOW", .pme_code = 0x20010, .pme_short_desc = "Overflow from counter 1", .pme_long_desc = "Overflows from PMC1 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.", }, [ POWER7_PME_PM_VSU0_SINGLE ] = { .pme_name = "PM_VSU0_SINGLE", .pme_code = 0xa0a8, .pme_short_desc = "FPU single precision", .pme_long_desc = "VSU0 executed single precision instruction", }, [ POWER7_PME_PM_MRK_PTEG_FROM_L3MISS ] = { .pme_name = "PM_MRK_PTEG_FROM_L3MISS", .pme_code = 0x2d058, .pme_short_desc = "Marked PTEG loaded from L3 miss", .pme_long_desc = "A Page Table Entry was loaded into the ERAT from beyond the L3 due to a marked load or store", }, [ POWER7_PME_PM_MRK_PTEG_FROM_L31_SHR ] = { .pme_name = "PM_MRK_PTEG_FROM_L31_SHR", .pme_code = 0x2d056, .pme_short_desc = "Marked PTEG loaded from another L3 on same chip shared", .pme_long_desc = "Marked PTEG loaded from another L3 on same chip shared", }, [ POWER7_PME_PM_VSU0_VECTOR_SP_ISSUED ] = { .pme_name = "PM_VSU0_VECTOR_SP_ISSUED", .pme_code = 0xb090, .pme_short_desc = "Single Precision vector instruction issued (executed)", .pme_long_desc = "Single Precision vector instruction issued (executed)", }, [ POWER7_PME_PM_VSU1_FEST ] = { .pme_name = "PM_VSU1_FEST", .pme_code = 0xa0ba, .pme_short_desc = "Estimate instruction executed", .pme_long_desc = "Estimate instruction executed", }, [ POWER7_PME_PM_MRK_INST_DISP ] = { .pme_name = "PM_MRK_INST_DISP", .pme_code = 0x20030, .pme_short_desc = "marked instruction dispatch", .pme_long_desc = "A marked instruction was dispatched", }, [ POWER7_PME_PM_VSU0_COMPLEX_ISSUED ] = { .pme_name = "PM_VSU0_COMPLEX_ISSUED", .pme_code = 0xb096, .pme_short_desc = "Complex VMX instruction issued", .pme_long_desc = "Complex VMX instruction issued", }, [ POWER7_PME_PM_LSU1_FLUSH_UST ] = { .pme_name = "PM_LSU1_FLUSH_UST", .pme_code = 0xc0b6, .pme_short_desc = "LS1 Flush: Unaligned Store", .pme_long_desc = "A store was flushed from unit 1 because it was unaligned (crossed a 4K boundary)", }, [ POWER7_PME_PM_INST_CMPL ] = { .pme_name = "PM_INST_CMPL", .pme_code = 0x2, .pme_short_desc = "# PPC Instructions Finished", .pme_long_desc = "Number of PowerPC Instructions that completed.", }, [ POWER7_PME_PM_FXU_IDLE ] = { .pme_name = "PM_FXU_IDLE", .pme_code = 0x1000e, .pme_short_desc = "fxu0 idle and fxu1 idle", .pme_long_desc = "FXU0 and FXU1 are both idle.", }, [ POWER7_PME_PM_LSU0_FLUSH_ULD ] = { .pme_name = "PM_LSU0_FLUSH_ULD", .pme_code = 0xc0b0, .pme_short_desc = "LS0 Flush: Unaligned Load", .pme_long_desc = "A load was flushed from unit 0 because it was unaligned (crossed a 64 byte boundary, or 32 byte if it missed the L1)", }, [ POWER7_PME_PM_MRK_DATA_FROM_DL2L3_MOD ] = { .pme_name = "PM_MRK_DATA_FROM_DL2L3_MOD", .pme_code = 0x3d04c, .pme_short_desc = "Marked data loaded from distant L2 or L3 modified", .pme_long_desc = "The processor's Data Cache was reloaded with modified (M) data from an L2 or L3 on a distant module due to a marked load.", }, [ POWER7_PME_PM_LSU_LMQ_SRQ_EMPTY_ALL_CYC ] = { .pme_name = "PM_LSU_LMQ_SRQ_EMPTY_ALL_CYC", .pme_code = 0x3001c, .pme_short_desc = "ALL threads lsu empty (lmq and srq empty)", .pme_long_desc = "ALL threads lsu empty (lmq and srq empty)", }, [ POWER7_PME_PM_LSU1_REJECT_LMQ_FULL ] = { .pme_name = "PM_LSU1_REJECT_LMQ_FULL", .pme_code = 0xc0a6, .pme_short_desc = "LS1 Reject: LMQ Full (LHR)", .pme_long_desc = "Total cycles the Load Store Unit 1 is busy rejecting instructions because the Load Miss Queue was full. The LMQ has eight entries. If all eight entries are full, subsequent load instructions are rejected.", }, [ POWER7_PME_PM_INST_PTEG_FROM_L21_MOD ] = { .pme_name = "PM_INST_PTEG_FROM_L21_MOD", .pme_code = 0x3e056, .pme_short_desc = "Instruction PTEG loaded from another L2 on same chip modified", .pme_long_desc = "Instruction PTEG loaded from another L2 on same chip modified", }, [ POWER7_PME_PM_INST_FROM_RL2L3_MOD ] = { .pme_name = "PM_INST_FROM_RL2L3_MOD", .pme_code = 0x14042, .pme_short_desc = "Instruction fetched from remote L2 or L3 modified", .pme_long_desc = "An instruction fetch group was fetched with modified (M) data from an L2 or L3 on a remote module. Fetch groups can contain up to 8 instructions", }, [ POWER7_PME_PM_SHL_CREATED ] = { .pme_name = "PM_SHL_CREATED", .pme_code = 0x5082, .pme_short_desc = "SHL table entry Created", .pme_long_desc = "SHL table entry Created", }, [ POWER7_PME_PM_L2_ST_HIT ] = { .pme_name = "PM_L2_ST_HIT", .pme_code = 0x46182, .pme_short_desc = "All successful store dispatches that were L2Hits", .pme_long_desc = "A store request hit in the L2 directory. This event includes all requests to this L2 from all sources. Total for all slices.", }, [ POWER7_PME_PM_DATA_FROM_DMEM ] = { .pme_name = "PM_DATA_FROM_DMEM", .pme_code = 0x1c04a, .pme_short_desc = "Data loaded from distant memory", .pme_long_desc = "The processor's Data Cache was reloaded with data from memory attached to a distant module due to a demand load", }, [ POWER7_PME_PM_L3_LD_MISS ] = { .pme_name = "PM_L3_LD_MISS", .pme_code = 0x2f082, .pme_short_desc = "L3 demand LD Miss", .pme_long_desc = "L3 demand LD Miss", }, [ POWER7_PME_PM_FXU1_BUSY_FXU0_IDLE ] = { .pme_name = "PM_FXU1_BUSY_FXU0_IDLE", .pme_code = 0x4000e, .pme_short_desc = "fxu0 idle and fxu1 busy. ", .pme_long_desc = "FXU0 was idle while FXU1 was busy", }, [ POWER7_PME_PM_DISP_CLB_HELD_RES ] = { .pme_name = "PM_DISP_CLB_HELD_RES", .pme_code = 0x2094, .pme_short_desc = "Dispatch/CLB Hold: Resource", .pme_long_desc = "Dispatch/CLB Hold: Resource", }, [ POWER7_PME_PM_L2_SN_SX_I_DONE ] = { .pme_name = "PM_L2_SN_SX_I_DONE", .pme_code = 0x36382, .pme_short_desc = "SNP dispatched and went from Sx or Tx to Ix", .pme_long_desc = "SNP dispatched and went from Sx or Tx to Ix", }, [ POWER7_PME_PM_GRP_CMPL ] = { .pme_name = "PM_GRP_CMPL", .pme_code = 0x30004, .pme_short_desc = "group completed", .pme_long_desc = "A group completed. Microcoded instructions that span multiple groups will generate this event once per group.", }, [ POWER7_PME_PM_STCX_CMPL ] = { .pme_name = "PM_STCX_CMPL", .pme_code = 0xc098, .pme_short_desc = "STCX executed", .pme_long_desc = "Conditional stores with reservation completed", }, [ POWER7_PME_PM_VSU0_2FLOP ] = { .pme_name = "PM_VSU0_2FLOP", .pme_code = 0xa098, .pme_short_desc = "two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions)", .pme_long_desc = "two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions)", }, [ POWER7_PME_PM_L3_PREF_MISS ] = { .pme_name = "PM_L3_PREF_MISS", .pme_code = 0x3f082, .pme_short_desc = "L3 Prefetch Directory Miss", .pme_long_desc = "L3 Prefetch Directory Miss", }, [ POWER7_PME_PM_LSU_SRQ_SYNC_CYC ] = { .pme_name = "PM_LSU_SRQ_SYNC_CYC", .pme_code = 0xd096, .pme_short_desc = "A sync is in the SRQ", .pme_long_desc = "Cycles that a sync instruction is active in the Store Request Queue.", }, [ POWER7_PME_PM_LSU_REJECT_ERAT_MISS ] = { .pme_name = "PM_LSU_REJECT_ERAT_MISS", .pme_code = 0x20064, .pme_short_desc = "LSU Reject due to ERAT (up to 2 per cycles)", .pme_long_desc = "Total cycles the Load Store Unit is busy rejecting instructions due to an ERAT miss. Combined unit 0 + 1. Requests that miss the Derat are rejected and retried until the request hits in the Erat.", }, [ POWER7_PME_PM_L1_ICACHE_MISS ] = { .pme_name = "PM_L1_ICACHE_MISS", .pme_code = 0x200fc, .pme_short_desc = "Demand iCache Miss", .pme_long_desc = "An instruction fetch request missed the L1 cache.", }, [ POWER7_PME_PM_LSU1_FLUSH_SRQ ] = { .pme_name = "PM_LSU1_FLUSH_SRQ", .pme_code = 0xc0be, .pme_short_desc = "LS1 Flush: SRQ", .pme_long_desc = "Load Hit Store flush. A younger load was flushed from unit 1 because it hits (overlaps) an older store that is already in the SRQ or in the same group. If the real addresses match but the effective addresses do not, an alias condition exists that prevents store forwarding. If the load and store are in the same group the load must be flushed to separate the two instructions. ", }, [ POWER7_PME_PM_LD_REF_L1_LSU0 ] = { .pme_name = "PM_LD_REF_L1_LSU0", .pme_code = 0xc080, .pme_short_desc = "LS0 L1 D cache load references counted at finish", .pme_long_desc = "Load references to Level 1 Data Cache, by unit 0.", }, [ POWER7_PME_PM_VSU0_FEST ] = { .pme_name = "PM_VSU0_FEST", .pme_code = 0xa0b8, .pme_short_desc = "Estimate instruction executed", .pme_long_desc = "Estimate instruction executed", }, [ POWER7_PME_PM_VSU_VECTOR_SINGLE_ISSUED ] = { .pme_name = "PM_VSU_VECTOR_SINGLE_ISSUED", .pme_code = 0xb890, .pme_short_desc = "Single Precision vector instruction issued (executed)", .pme_long_desc = "Single Precision vector instruction issued (executed)", }, [ POWER7_PME_PM_FREQ_UP ] = { .pme_name = "PM_FREQ_UP", .pme_code = 0x4000c, .pme_short_desc = "Power Management: Above Threshold A", .pme_long_desc = "Processor frequency was sped up due to power management", }, [ POWER7_PME_PM_DATA_FROM_LMEM ] = { .pme_name = "PM_DATA_FROM_LMEM", .pme_code = 0x3c04a, .pme_short_desc = "Data loaded from local memory", .pme_long_desc = "The processor's Data Cache was reloaded from memory attached to the same module this proccessor is located on.", }, [ POWER7_PME_PM_LSU1_LDX ] = { .pme_name = "PM_LSU1_LDX", .pme_code = 0xc08a, .pme_short_desc = "LS1 Vector Loads", .pme_long_desc = "LS1 Vector Loads", }, [ POWER7_PME_PM_PMC3_OVERFLOW ] = { .pme_name = "PM_PMC3_OVERFLOW", .pme_code = 0x40010, .pme_short_desc = "Overflow from counter 3", .pme_long_desc = "Overflows from PMC3 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.", }, [ POWER7_PME_PM_MRK_BR_MPRED ] = { .pme_name = "PM_MRK_BR_MPRED", .pme_code = 0x30036, .pme_short_desc = "Marked Branch Mispredicted", .pme_long_desc = "A marked branch was mispredicted", }, [ POWER7_PME_PM_SHL_MATCH ] = { .pme_name = "PM_SHL_MATCH", .pme_code = 0x5086, .pme_short_desc = "SHL Table Match", .pme_long_desc = "SHL Table Match", }, [ POWER7_PME_PM_MRK_BR_TAKEN ] = { .pme_name = "PM_MRK_BR_TAKEN", .pme_code = 0x10036, .pme_short_desc = "Marked Branch Taken", .pme_long_desc = "A marked branch was taken", }, [ POWER7_PME_PM_CMPLU_STALL_BRU ] = { .pme_name = "PM_CMPLU_STALL_BRU", .pme_code = 0x4004e, .pme_short_desc = "Completion stall due to BRU", .pme_long_desc = "Completion stall due to BRU", }, [ POWER7_PME_PM_ISLB_MISS ] = { .pme_name = "PM_ISLB_MISS", .pme_code = 0xd092, .pme_short_desc = "Instruction SLB Miss - Tota of all segment sizes", .pme_long_desc = "A SLB miss for an instruction fetch as occurred", }, [ POWER7_PME_PM_CYC ] = { .pme_name = "PM_CYC", .pme_code = 0x1e, .pme_short_desc = "Cycles", .pme_long_desc = "Processor Cycles", }, [ POWER7_PME_PM_DISP_HELD_THERMAL ] = { .pme_name = "PM_DISP_HELD_THERMAL", .pme_code = 0x30006, .pme_short_desc = "Dispatch Held due to Thermal", .pme_long_desc = "Dispatch Held due to Thermal", }, [ POWER7_PME_PM_INST_PTEG_FROM_RL2L3_SHR ] = { .pme_name = "PM_INST_PTEG_FROM_RL2L3_SHR", .pme_code = 0x2e054, .pme_short_desc = "Instruction PTEG loaded from remote L2 or L3 shared", .pme_long_desc = "Instruction PTEG loaded from remote L2 or L3 shared", }, [ POWER7_PME_PM_LSU1_SRQ_STFWD ] = { .pme_name = "PM_LSU1_SRQ_STFWD", .pme_code = 0xc0a2, .pme_short_desc = "LS1 SRQ forwarded data to a load", .pme_long_desc = "Data from a store instruction was forwarded to a load on unit 1. A load that misses L1 but becomes a store forward is treated as a load miss and it causes the DL1 load miss event to be counted. It does not go into the LMQ. If a load that hits L1 but becomes a store forward, then it's not treated as a load miss.", }, [ POWER7_PME_PM_GCT_NOSLOT_BR_MPRED ] = { .pme_name = "PM_GCT_NOSLOT_BR_MPRED", .pme_code = 0x4001a, .pme_short_desc = "GCT empty by branch mispredict", .pme_long_desc = "Cycles when the Global Completion Table has no slots from this thread because of a branch misprediction.", }, [ POWER7_PME_PM_1PLUS_PPC_CMPL ] = { .pme_name = "PM_1PLUS_PPC_CMPL", .pme_code = 0x100f2, .pme_short_desc = "1 or more ppc insts finished", .pme_long_desc = "A group containing at least one PPC instruction completed. For microcoded instructions that span multiple groups, this will only occur once.", }, [ POWER7_PME_PM_PTEG_FROM_DMEM ] = { .pme_name = "PM_PTEG_FROM_DMEM", .pme_code = 0x2c052, .pme_short_desc = "PTEG loaded from distant memory", .pme_long_desc = "A Page Table Entry was loaded into the ERAT with data from memory attached to a distant module due to a demand load or store.", }, [ POWER7_PME_PM_VSU_2FLOP ] = { .pme_name = "PM_VSU_2FLOP", .pme_code = 0xa898, .pme_short_desc = "two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions)", .pme_long_desc = "two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions)", }, [ POWER7_PME_PM_GCT_FULL_CYC ] = { .pme_name = "PM_GCT_FULL_CYC", .pme_code = 0x4086, .pme_short_desc = "Cycles No room in EAT", .pme_long_desc = "The Global Completion Table is completely full.", }, [ POWER7_PME_PM_MRK_DATA_FROM_L3_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L3_CYC", .pme_code = 0x40020, .pme_short_desc = "Marked ld latency Data source 0001 (L3)", .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.", }, [ POWER7_PME_PM_LSU_SRQ_S0_ALLOC ] = { .pme_name = "PM_LSU_SRQ_S0_ALLOC", .pme_code = 0xd09d, .pme_short_desc = "Slot 0 of SRQ valid", .pme_long_desc = "Slot 0 of SRQ valid", }, [ POWER7_PME_PM_MRK_DERAT_MISS_4K ] = { .pme_name = "PM_MRK_DERAT_MISS_4K", .pme_code = 0x1d05c, .pme_short_desc = "Marked DERAT misses for 4K page", .pme_long_desc = "A marked data request (load or store) missed the ERAT for 4K page and resulted in an ERAT reload.", }, [ POWER7_PME_PM_BR_MPRED_TA ] = { .pme_name = "PM_BR_MPRED_TA", .pme_code = 0x40ae, .pme_short_desc = "Branch mispredict - target address", .pme_long_desc = "A branch instruction target was incorrectly predicted. This will result in a branch mispredict flush unless a flush is detected from an older instruction.", }, [ POWER7_PME_PM_INST_PTEG_FROM_L2MISS ] = { .pme_name = "PM_INST_PTEG_FROM_L2MISS", .pme_code = 0x4e058, .pme_short_desc = "Instruction PTEG loaded from L2 miss", .pme_long_desc = "Instruction PTEG loaded from L2 miss", }, [ POWER7_PME_PM_DPU_HELD_POWER ] = { .pme_name = "PM_DPU_HELD_POWER", .pme_code = 0x20006, .pme_short_desc = "Dispatch Held due to Power Management", .pme_long_desc = "Cycles that Instruction Dispatch was held due to power management. More than one hold condition can exist at the same time", }, [ POWER7_PME_PM_RUN_INST_CMPL ] = { .pme_name = "PM_RUN_INST_CMPL", .pme_code = 0x400fa, .pme_short_desc = "Run_Instructions", .pme_long_desc = "Number of run instructions completed. ", }, [ POWER7_PME_PM_MRK_VSU_FIN ] = { .pme_name = "PM_MRK_VSU_FIN", .pme_code = 0x30032, .pme_short_desc = "vsu (fpu) marked instr finish", .pme_long_desc = "vsu (fpu) marked instr finish", }, [ POWER7_PME_PM_LSU_SRQ_S0_VALID ] = { .pme_name = "PM_LSU_SRQ_S0_VALID", .pme_code = 0xd09c, .pme_short_desc = "Slot 0 of SRQ valid", .pme_long_desc = "This signal is asserted every cycle that the Store Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin. In SMT mode the SRQ is split between the two threads (16 entries each).", }, [ POWER7_PME_PM_GCT_EMPTY_CYC ] = { .pme_name = "PM_GCT_EMPTY_CYC", .pme_code = 0x20008, .pme_short_desc = "GCT empty, all threads", .pme_long_desc = "Cycles when the Global Completion Table was completely empty. No thread had an entry allocated.", }, [ POWER7_PME_PM_IOPS_DISP ] = { .pme_name = "PM_IOPS_DISP", .pme_code = 0x30014, .pme_short_desc = "IOPS dispatched", .pme_long_desc = "IOPS dispatched", }, [ POWER7_PME_PM_RUN_SPURR ] = { .pme_name = "PM_RUN_SPURR", .pme_code = 0x10008, .pme_short_desc = "Run SPURR", .pme_long_desc = "Run SPURR", }, [ POWER7_PME_PM_PTEG_FROM_L21_MOD ] = { .pme_name = "PM_PTEG_FROM_L21_MOD", .pme_code = 0x3c056, .pme_short_desc = "PTEG loaded from another L2 on same chip modified", .pme_long_desc = "PTEG loaded from another L2 on same chip modified", }, [ POWER7_PME_PM_VSU0_1FLOP ] = { .pme_name = "PM_VSU0_1FLOP", .pme_code = 0xa080, .pme_short_desc = "one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg, xsadd, xsmul, xssub, xscmp, xssel, xsabs, xsnabs, xsre, xssqrte, xsneg) operation finished", .pme_long_desc = "one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg, xsadd, xsmul, xssub, xscmp, xssel, xsabs, xsnabs, xsre, xssqrte, xsneg) operation finished", }, [ POWER7_PME_PM_SNOOP_TLBIE ] = { .pme_name = "PM_SNOOP_TLBIE", .pme_code = 0xd0b2, .pme_short_desc = "TLBIE snoop", .pme_long_desc = "A tlbie was snooped from another processor.", }, [ POWER7_PME_PM_DATA_FROM_L3MISS ] = { .pme_name = "PM_DATA_FROM_L3MISS", .pme_code = 0x2c048, .pme_short_desc = "Demand LD - L3 Miss (not L2 hit and not L3 hit)", .pme_long_desc = "The processor's Data Cache was reloaded from beyond L3 due to a demand load", }, [ POWER7_PME_PM_VSU_SINGLE ] = { .pme_name = "PM_VSU_SINGLE", .pme_code = 0xa8a8, .pme_short_desc = "Vector or Scalar single precision", .pme_long_desc = "Vector or Scalar single precision", }, [ POWER7_PME_PM_DTLB_MISS_16G ] = { .pme_name = "PM_DTLB_MISS_16G", .pme_code = 0x1c05e, .pme_short_desc = "Data TLB miss for 16G page", .pme_long_desc = "Data TLB references to 16GB pages that missed the TLB. Page size is determined at TLB reload time.", }, [ POWER7_PME_PM_CMPLU_STALL_VECTOR ] = { .pme_name = "PM_CMPLU_STALL_VECTOR", .pme_code = 0x2001c, .pme_short_desc = "Completion stall caused by Vector instruction", .pme_long_desc = "Completion stall caused by Vector instruction", }, [ POWER7_PME_PM_FLUSH ] = { .pme_name = "PM_FLUSH", .pme_code = 0x400f8, .pme_short_desc = "Flush (any type)", .pme_long_desc = "Flushes occurred including LSU and Branch flushes.", }, [ POWER7_PME_PM_L2_LD_HIT ] = { .pme_name = "PM_L2_LD_HIT", .pme_code = 0x36182, .pme_short_desc = "All successful load dispatches that were L2 hits", .pme_long_desc = "A load request (data or instruction) hit in the L2 directory. Includes speculative, prefetched, and demand requests. This event includes all requests to this L2 from all sources. Total for all slices", }, [ POWER7_PME_PM_NEST_PAIR2_AND ] = { .pme_name = "PM_NEST_PAIR2_AND", .pme_code = 0x30883, .pme_short_desc = " Nest events (MC0/MC1/PB/GX), Pair2 AND", .pme_long_desc = " Nest events (MC0/MC1/PB/GX), Pair2 AND", }, [ POWER7_PME_PM_VSU1_1FLOP ] = { .pme_name = "PM_VSU1_1FLOP", .pme_code = 0xa082, .pme_short_desc = "one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg, xsadd, xsmul, xssub, xscmp, xssel, xsabs, xsnabs, xsre, xssqrte, xsneg) operation finished", .pme_long_desc = "one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg, xsadd, xsmul, xssub, xscmp, xssel, xsabs, xsnabs, xsre, xssqrte, xsneg) operation finished", }, [ POWER7_PME_PM_IC_PREF_REQ ] = { .pme_name = "PM_IC_PREF_REQ", .pme_code = 0x408a, .pme_short_desc = "Instruction prefetch requests", .pme_long_desc = "An instruction prefetch request has been made.", }, [ POWER7_PME_PM_L3_LD_HIT ] = { .pme_name = "PM_L3_LD_HIT", .pme_code = 0x2f080, .pme_short_desc = "L3 demand LD Hits", .pme_long_desc = "L3 demand LD Hits", }, [ POWER7_PME_PM_GCT_NOSLOT_IC_MISS ] = { .pme_name = "PM_GCT_NOSLOT_IC_MISS", .pme_code = 0x2001a, .pme_short_desc = "GCT empty by I cache miss", .pme_long_desc = "Cycles when the Global Completion Table has no slots from this thread because of an Instruction Cache miss.", }, [ POWER7_PME_PM_DISP_HELD ] = { .pme_name = "PM_DISP_HELD", .pme_code = 0x10006, .pme_short_desc = "Dispatch Held", .pme_long_desc = "Dispatch Held", }, [ POWER7_PME_PM_L2_LD ] = { .pme_name = "PM_L2_LD", .pme_code = 0x16080, .pme_short_desc = "Data Load Count", .pme_long_desc = "Data Load Count", }, [ POWER7_PME_PM_LSU_FLUSH_SRQ ] = { .pme_name = "PM_LSU_FLUSH_SRQ", .pme_code = 0xc8bc, .pme_short_desc = "Flush: SRQ", .pme_long_desc = "Load Hit Store flush. A younger load was flushed because it hits (overlaps) an older store that is already in the SRQ or in the same group. If the real addresses match but the effective addresses do not, an alias condition exists that prevents store forwarding. If the load and store are in the same group the load must be flushed to separate the two instructions. Combined Unit 0 + 1.", }, [ POWER7_PME_PM_BC_PLUS_8_CONV ] = { .pme_name = "PM_BC_PLUS_8_CONV", .pme_code = 0x40b8, .pme_short_desc = "BC+8 Converted", .pme_long_desc = "BC+8 Converted", }, [ POWER7_PME_PM_MRK_DATA_FROM_L31_MOD_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L31_MOD_CYC", .pme_code = 0x40026, .pme_short_desc = "Marked ld latency Data source 0111 (L3.1 M same chip)", .pme_long_desc = "Marked ld latency Data source 0111 (L3.1 M same chip)", }, [ POWER7_PME_PM_CMPLU_STALL_VECTOR_LONG ] = { .pme_name = "PM_CMPLU_STALL_VECTOR_LONG", .pme_code = 0x4004a, .pme_short_desc = "completion stall due to long latency vector instruction", .pme_long_desc = "completion stall due to long latency vector instruction", }, [ POWER7_PME_PM_L2_RCST_BUSY_RC_FULL ] = { .pme_name = "PM_L2_RCST_BUSY_RC_FULL", .pme_code = 0x26282, .pme_short_desc = " L2 activated Busy to the core for stores due to all RC full", .pme_long_desc = " L2 activated Busy to the core for stores due to all RC full", }, [ POWER7_PME_PM_TB_BIT_TRANS ] = { .pme_name = "PM_TB_BIT_TRANS", .pme_code = 0x300f8, .pme_short_desc = "Time Base bit transition", .pme_long_desc = "When the selected time base bit (as specified in MMCR0[TBSEL])transitions from 0 to 1 ", }, [ POWER7_PME_PM_THERMAL_MAX ] = { .pme_name = "PM_THERMAL_MAX", .pme_code = 0x40006, .pme_short_desc = "Processor In Thermal MAX", .pme_long_desc = "The processor experienced a thermal overload condition. This bit is sticky, it remains set until cleared by software.", }, [ POWER7_PME_PM_LSU1_FLUSH_ULD ] = { .pme_name = "PM_LSU1_FLUSH_ULD", .pme_code = 0xc0b2, .pme_short_desc = "LS 1 Flush: Unaligned Load", .pme_long_desc = "A load was flushed from unit 1 because it was unaligned (crossed a 64 byte boundary, or 32 byte if it missed the L1).", }, [ POWER7_PME_PM_LSU1_REJECT_LHS ] = { .pme_name = "PM_LSU1_REJECT_LHS", .pme_code = 0xc0ae, .pme_short_desc = "LS1 Reject: Load Hit Store", .pme_long_desc = "Load Store Unit 1 rejected a load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully.", }, [ POWER7_PME_PM_LSU_LRQ_S0_ALLOC ] = { .pme_name = "PM_LSU_LRQ_S0_ALLOC", .pme_code = 0xd09f, .pme_short_desc = "Slot 0 of LRQ valid", .pme_long_desc = "Slot 0 of LRQ valid", }, [ POWER7_PME_PM_L3_CO_L31 ] = { .pme_name = "PM_L3_CO_L31", .pme_code = 0x4f080, .pme_short_desc = "L3 Castouts to Memory", .pme_long_desc = "L3 Castouts to Memory", }, [ POWER7_PME_PM_POWER_EVENT4 ] = { .pme_name = "PM_POWER_EVENT4", .pme_code = 0x4006e, .pme_short_desc = "Power Management Event 4", .pme_long_desc = "Power Management Event 4", }, [ POWER7_PME_PM_DATA_FROM_L31_SHR ] = { .pme_name = "PM_DATA_FROM_L31_SHR", .pme_code = 0x1c04e, .pme_short_desc = "Data loaded from another L3 on same chip shared", .pme_long_desc = "Data loaded from another L3 on same chip shared", }, [ POWER7_PME_PM_BR_UNCOND ] = { .pme_name = "PM_BR_UNCOND", .pme_code = 0x409e, .pme_short_desc = "Unconditional Branch", .pme_long_desc = "An unconditional branch was executed.", }, [ POWER7_PME_PM_LSU1_DC_PREF_STREAM_ALLOC ] = { .pme_name = "PM_LSU1_DC_PREF_STREAM_ALLOC", .pme_code = 0xd0aa, .pme_short_desc = "LS 1 D cache new prefetch stream allocated", .pme_long_desc = "LS 1 D cache new prefetch stream allocated", }, [ POWER7_PME_PM_PMC4_REWIND ] = { .pme_name = "PM_PMC4_REWIND", .pme_code = 0x10020, .pme_short_desc = "PMC4 Rewind Event", .pme_long_desc = "PMC4 was counting speculatively. The speculative condition was not met and the counter was restored to its previous value.", }, [ POWER7_PME_PM_L2_RCLD_DISP ] = { .pme_name = "PM_L2_RCLD_DISP", .pme_code = 0x16280, .pme_short_desc = " L2 RC load dispatch attempt", .pme_long_desc = " L2 RC load dispatch attempt", }, [ POWER7_PME_PM_THRD_PRIO_2_3_CYC ] = { .pme_name = "PM_THRD_PRIO_2_3_CYC", .pme_code = 0x40b2, .pme_short_desc = " Cycles thread running at priority level 2 or 3", .pme_long_desc = " Cycles thread running at priority level 2 or 3", }, [ POWER7_PME_PM_MRK_PTEG_FROM_L2MISS ] = { .pme_name = "PM_MRK_PTEG_FROM_L2MISS", .pme_code = 0x4d058, .pme_short_desc = "Marked PTEG loaded from L2 miss", .pme_long_desc = "A Page Table Entry was loaded into the ERAT but not from the local L2 due to a marked load or store.", }, [ POWER7_PME_PM_IC_DEMAND_L2_BHT_REDIRECT ] = { .pme_name = "PM_IC_DEMAND_L2_BHT_REDIRECT", .pme_code = 0x4098, .pme_short_desc = " L2 I cache demand request due to BHT redirect", .pme_long_desc = "A demand (not prefetch) miss to the instruction cache was sent to the L2 as a result of a branch prediction redirect (CR mispredict).", }, [ POWER7_PME_PM_LSU_DERAT_MISS ] = { .pme_name = "PM_LSU_DERAT_MISS", .pme_code = 0x200f6, .pme_short_desc = "DERAT Reloaded due to a DERAT miss", .pme_long_desc = "Total D-ERAT Misses. Requests that miss the Derat are rejected and retried until the request hits in the Erat. This may result in multiple erat misses for the same instruction. Combined Unit 0 + 1.", }, [ POWER7_PME_PM_IC_PREF_CANCEL_L2 ] = { .pme_name = "PM_IC_PREF_CANCEL_L2", .pme_code = 0x4094, .pme_short_desc = "L2 Squashed request", .pme_long_desc = "L2 Squashed request", }, [ POWER7_PME_PM_MRK_FIN_STALL_CYC_COUNT ] = { .pme_name = "PM_MRK_FIN_STALL_CYC_COUNT", .pme_code = 0x1003d, .pme_short_desc = "Marked instruction Finish Stall cycles (marked finish after NTC) (use edge detect to count #)", .pme_long_desc = "Marked instruction Finish Stall cycles (marked finish after NTC) (use edge detect to count #)", }, [ POWER7_PME_PM_BR_PRED_CCACHE ] = { .pme_name = "PM_BR_PRED_CCACHE", .pme_code = 0x40a0, .pme_short_desc = "Count Cache Predictions", .pme_long_desc = "The count value of a Branch and Count instruction was predicted", }, [ POWER7_PME_PM_GCT_UTIL_1_TO_2_SLOTS ] = { .pme_name = "PM_GCT_UTIL_1_TO_2_SLOTS", .pme_code = 0x209c, .pme_short_desc = "GCT Utilization 1-2 entries", .pme_long_desc = "GCT Utilization 1-2 entries", }, [ POWER7_PME_PM_MRK_ST_CMPL_INT ] = { .pme_name = "PM_MRK_ST_CMPL_INT", .pme_code = 0x30034, .pme_short_desc = "marked store complete (data home) with intervention", .pme_long_desc = "A marked store previously sent to the memory subsystem completed (data home) after requiring intervention", }, [ POWER7_PME_PM_LSU_TWO_TABLEWALK_CYC ] = { .pme_name = "PM_LSU_TWO_TABLEWALK_CYC", .pme_code = 0xd0a6, .pme_short_desc = "Cycles when two tablewalks pending on this thread", .pme_long_desc = "Cycles when two tablewalks pending on this thread", }, [ POWER7_PME_PM_MRK_DATA_FROM_L3MISS ] = { .pme_name = "PM_MRK_DATA_FROM_L3MISS", .pme_code = 0x2d048, .pme_short_desc = "Marked data loaded from L3 miss", .pme_long_desc = "DL1 was reloaded from beyond L3 due to a marked load.", }, [ POWER7_PME_PM_GCT_NOSLOT_CYC ] = { .pme_name = "PM_GCT_NOSLOT_CYC", .pme_code = 0x100f8, .pme_short_desc = "No itags assigned ", .pme_long_desc = "Cycles when the Global Completion Table has no slots from this thread.", }, [ POWER7_PME_PM_LSU_SET_MPRED ] = { .pme_name = "PM_LSU_SET_MPRED", .pme_code = 0xc0a8, .pme_short_desc = "Line already in cache at reload time", .pme_long_desc = "Line already in cache at reload time", }, [ POWER7_PME_PM_FLUSH_DISP_TLBIE ] = { .pme_name = "PM_FLUSH_DISP_TLBIE", .pme_code = 0x208a, .pme_short_desc = "Dispatch Flush: TLBIE", .pme_long_desc = "Dispatch Flush: TLBIE", }, [ POWER7_PME_PM_VSU1_FCONV ] = { .pme_name = "PM_VSU1_FCONV", .pme_code = 0xa0b2, .pme_short_desc = "Convert instruction executed", .pme_long_desc = "Convert instruction executed", }, [ POWER7_PME_PM_DERAT_MISS_16G ] = { .pme_name = "PM_DERAT_MISS_16G", .pme_code = 0x4c05c, .pme_short_desc = "DERAT misses for 16G page", .pme_long_desc = "A data request (load or store) missed the ERAT for 16G page and resulted in an ERAT reload.", }, [ POWER7_PME_PM_INST_FROM_LMEM ] = { .pme_name = "PM_INST_FROM_LMEM", .pme_code = 0x3404a, .pme_short_desc = "Instruction fetched from local memory", .pme_long_desc = "An instruction fetch group was fetched from memory attached to the same module this proccessor is located on. Fetch groups can contain up to 8 instructions", }, [ POWER7_PME_PM_IC_DEMAND_L2_BR_REDIRECT ] = { .pme_name = "PM_IC_DEMAND_L2_BR_REDIRECT", .pme_code = 0x409a, .pme_short_desc = " L2 I cache demand request due to branch redirect", .pme_long_desc = "A demand (not prefetch) miss to the instruction cache was sent to the L2 as a result of a branch prediction redirect (either ALL mispredicted or Target).", }, [ POWER7_PME_PM_CMPLU_STALL_SCALAR_LONG ] = { .pme_name = "PM_CMPLU_STALL_SCALAR_LONG", .pme_code = 0x20018, .pme_short_desc = "Completion stall caused by long latency scalar instruction", .pme_long_desc = "Completion stall caused by long latency scalar instruction", }, [ POWER7_PME_PM_INST_PTEG_FROM_L2 ] = { .pme_name = "PM_INST_PTEG_FROM_L2", .pme_code = 0x1e050, .pme_short_desc = "Instruction PTEG loaded from L2", .pme_long_desc = "Instruction PTEG loaded from L2", }, [ POWER7_PME_PM_PTEG_FROM_L2 ] = { .pme_name = "PM_PTEG_FROM_L2", .pme_code = 0x1c050, .pme_short_desc = "PTEG loaded from L2", .pme_long_desc = "A Page Table Entry was loaded into the ERAT from the local L2 due to a demand load or store.", }, [ POWER7_PME_PM_MRK_DATA_FROM_L21_SHR_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L21_SHR_CYC", .pme_code = 0x20024, .pme_short_desc = "Marked ld latency Data source 0100 (L2.1 S)", .pme_long_desc = "Marked load latency Data source 0100 (L2.1 S)", }, [ POWER7_PME_PM_MRK_DTLB_MISS_4K ] = { .pme_name = "PM_MRK_DTLB_MISS_4K", .pme_code = 0x2d05a, .pme_short_desc = "Marked Data TLB misses for 4K page", .pme_long_desc = "Data TLB references to 4KB pages by a marked instruction that missed the TLB. Page size is determined at TLB reload time.", }, [ POWER7_PME_PM_VSU0_FPSCR ] = { .pme_name = "PM_VSU0_FPSCR", .pme_code = 0xb09c, .pme_short_desc = "Move to/from FPSCR type instruction issued on Pipe 0", .pme_long_desc = "Move to/from FPSCR type instruction issued on Pipe 0", }, [ POWER7_PME_PM_VSU1_VECT_DOUBLE_ISSUED ] = { .pme_name = "PM_VSU1_VECT_DOUBLE_ISSUED", .pme_code = 0xb082, .pme_short_desc = "Double Precision vector instruction issued on Pipe1", .pme_long_desc = "Double Precision vector instruction issued on Pipe1", }, [ POWER7_PME_PM_MRK_PTEG_FROM_RL2L3_MOD ] = { .pme_name = "PM_MRK_PTEG_FROM_RL2L3_MOD", .pme_code = 0x1d052, .pme_short_desc = "Marked PTEG loaded from remote L2 or L3 modified", .pme_long_desc = "A Page Table Entry was loaded into the ERAT with shared (T or SL) data from an L2 or L3 on a remote module due to a marked load or store.", }, [ POWER7_PME_PM_MEM0_RQ_DISP ] = { .pme_name = "PM_MEM0_RQ_DISP", .pme_code = 0x10083, .pme_short_desc = " Nest events (MC0/MC1/PB/GX), Pair0 Bit1", .pme_long_desc = " Nest events (MC0/MC1/PB/GX), Pair0 Bit1", }, [ POWER7_PME_PM_L2_LD_MISS ] = { .pme_name = "PM_L2_LD_MISS", .pme_code = 0x26080, .pme_short_desc = "Data Load Miss", .pme_long_desc = "Data Load Miss", }, [ POWER7_PME_PM_VMX_RESULT_SAT_1 ] = { .pme_name = "PM_VMX_RESULT_SAT_1", .pme_code = 0xb0a0, .pme_short_desc = "Valid result with sat=1", .pme_long_desc = "Valid result with sat=1", }, [ POWER7_PME_PM_L1_PREF ] = { .pme_name = "PM_L1_PREF", .pme_code = 0xd8b8, .pme_short_desc = "L1 Prefetches", .pme_long_desc = "A request to prefetch data into the L1 was made", }, [ POWER7_PME_PM_MRK_DATA_FROM_LMEM_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_LMEM_CYC", .pme_code = 0x2002c, .pme_short_desc = "Marked ld latency Data Source 1100 (Local Memory)", .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.", }, [ POWER7_PME_PM_GRP_IC_MISS_NONSPEC ] = { .pme_name = "PM_GRP_IC_MISS_NONSPEC", .pme_code = 0x1000c, .pme_short_desc = "Group experienced non-speculative I cache miss", .pme_long_desc = "Number of groups, counted at completion, that have encountered an instruction cache miss.", }, [ POWER7_PME_PM_PB_NODE_PUMP ] = { .pme_name = "PM_PB_NODE_PUMP", .pme_code = 0x10081, .pme_short_desc = " Nest events (MC0/MC1/PB/GX), Pair0 Bit0", .pme_long_desc = " Nest events (MC0/MC1/PB/GX), Pair0 Bit0", }, [ POWER7_PME_PM_SHL_MERGED ] = { .pme_name = "PM_SHL_MERGED", .pme_code = 0x5084, .pme_short_desc = "SHL table entry merged with existing", .pme_long_desc = "SHL table entry merged with existing", }, [ POWER7_PME_PM_NEST_PAIR1_ADD ] = { .pme_name = "PM_NEST_PAIR1_ADD", .pme_code = 0x20881, .pme_short_desc = " Nest events (MC0/MC1/PB/GX), Pair1 ADD", .pme_long_desc = " Nest events (MC0/MC1/PB/GX), Pair1 ADD", }, [ POWER7_PME_PM_DATA_FROM_L3 ] = { .pme_name = "PM_DATA_FROM_L3", .pme_code = 0x1c048, .pme_short_desc = "Data loaded from L3", .pme_long_desc = "The processor's Data Cache was reloaded from the local L3 due to a demand load.", }, [ POWER7_PME_PM_LSU_FLUSH ] = { .pme_name = "PM_LSU_FLUSH", .pme_code = 0x208e, .pme_short_desc = "Flush initiated by LSU", .pme_long_desc = "A flush was initiated by the Load Store Unit.", }, [ POWER7_PME_PM_LSU_SRQ_SYNC_COUNT ] = { .pme_name = "PM_LSU_SRQ_SYNC_COUNT", .pme_code = 0xd097, .pme_short_desc = "SRQ sync count (edge of PM_LSU_SRQ_SYNC_CYC)", .pme_long_desc = "SRQ sync count (edge of PM_LSU_SRQ_SYNC_CYC)", }, [ POWER7_PME_PM_PMC2_OVERFLOW ] = { .pme_name = "PM_PMC2_OVERFLOW", .pme_code = 0x30010, .pme_short_desc = "Overflow from counter 2", .pme_long_desc = "Overflows from PMC2 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.", }, [ POWER7_PME_PM_LSU_LDF ] = { .pme_name = "PM_LSU_LDF", .pme_code = 0xc884, .pme_short_desc = "All Scalar Loads", .pme_long_desc = "LSU executed Floating Point load instruction. Combined Unit 0 + 1.", }, [ POWER7_PME_PM_POWER_EVENT3 ] = { .pme_name = "PM_POWER_EVENT3", .pme_code = 0x3006e, .pme_short_desc = "Power Management Event 3", .pme_long_desc = "Power Management Event 3", }, [ POWER7_PME_PM_DISP_WT ] = { .pme_name = "PM_DISP_WT", .pme_code = 0x30008, .pme_short_desc = "Dispatched Starved (not held, nothing to dispatch)", .pme_long_desc = "Dispatched Starved (not held, nothing to dispatch)", }, [ POWER7_PME_PM_CMPLU_STALL_REJECT ] = { .pme_name = "PM_CMPLU_STALL_REJECT", .pme_code = 0x40016, .pme_short_desc = "Completion stall caused by reject", .pme_long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes suffered a load/store reject. This is a subset of PM_CMPLU_STALL_LSU.", }, [ POWER7_PME_PM_IC_BANK_CONFLICT ] = { .pme_name = "PM_IC_BANK_CONFLICT", .pme_code = 0x4082, .pme_short_desc = "Read blocked due to interleave conflict. ", .pme_long_desc = "Read blocked due to interleave conflict. ", }, [ POWER7_PME_PM_BR_MPRED_CR_TA ] = { .pme_name = "PM_BR_MPRED_CR_TA", .pme_code = 0x48ae, .pme_short_desc = "Branch mispredict - taken/not taken and target", .pme_long_desc = "Branch mispredict - taken/not taken and target", }, [ POWER7_PME_PM_L2_INST_MISS ] = { .pme_name = "PM_L2_INST_MISS", .pme_code = 0x36082, .pme_short_desc = "Instruction Load Misses", .pme_long_desc = "Instruction Load Misses", }, [ POWER7_PME_PM_CMPLU_STALL_ERAT_MISS ] = { .pme_name = "PM_CMPLU_STALL_ERAT_MISS", .pme_code = 0x40018, .pme_short_desc = "Completion stall caused by ERAT miss", .pme_long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes suffered an ERAT miss. This is a subset of PM_CMPLU_STALL_REJECT.", }, [ POWER7_PME_PM_NEST_PAIR2_ADD ] = { .pme_name = "PM_NEST_PAIR2_ADD", .pme_code = 0x30881, .pme_short_desc = " Nest events (MC0/MC1/PB/GX), Pair2 ADD", .pme_long_desc = " Nest events (MC0/MC1/PB/GX), Pair2 ADD", }, [ POWER7_PME_PM_MRK_LSU_FLUSH ] = { .pme_name = "PM_MRK_LSU_FLUSH", .pme_code = 0xd08c, .pme_short_desc = "Flush: (marked) : All Cases", .pme_long_desc = "Marked flush initiated by LSU", }, [ POWER7_PME_PM_L2_LDST ] = { .pme_name = "PM_L2_LDST", .pme_code = 0x16880, .pme_short_desc = "Data Load+Store Count", .pme_long_desc = "Data Load+Store Count", }, [ POWER7_PME_PM_INST_FROM_L31_SHR ] = { .pme_name = "PM_INST_FROM_L31_SHR", .pme_code = 0x1404e, .pme_short_desc = "Instruction fetched from another L3 on same chip shared", .pme_long_desc = "Instruction fetched from another L3 on same chip shared", }, [ POWER7_PME_PM_VSU0_FIN ] = { .pme_name = "PM_VSU0_FIN", .pme_code = 0xa0bc, .pme_short_desc = "VSU0 Finished an instruction", .pme_long_desc = "VSU0 Finished an instruction", }, [ POWER7_PME_PM_LARX_LSU ] = { .pme_name = "PM_LARX_LSU", .pme_code = 0xc894, .pme_short_desc = "Larx Finished", .pme_long_desc = "Larx Finished", }, [ POWER7_PME_PM_INST_FROM_RMEM ] = { .pme_name = "PM_INST_FROM_RMEM", .pme_code = 0x34042, .pme_short_desc = "Instruction fetched from remote memory", .pme_long_desc = "An instruction fetch group was fetched from memory attached to a different module than this proccessor is located on. Fetch groups can contain up to 8 instructions", }, [ POWER7_PME_PM_DISP_CLB_HELD_TLBIE ] = { .pme_name = "PM_DISP_CLB_HELD_TLBIE", .pme_code = 0x2096, .pme_short_desc = "Dispatch Hold: Due to TLBIE", .pme_long_desc = "Dispatch Hold: Due to TLBIE", }, [ POWER7_PME_PM_MRK_DATA_FROM_DMEM_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_DMEM_CYC", .pme_code = 0x2002e, .pme_short_desc = "Marked ld latency Data Source 1110 (Distant Memory)", .pme_long_desc = "Marked ld latency Data Source 1110 (Distant Memory)", }, [ POWER7_PME_PM_BR_PRED_CR ] = { .pme_name = "PM_BR_PRED_CR", .pme_code = 0x40a8, .pme_short_desc = "Branch predict - taken/not taken", .pme_long_desc = "A conditional branch instruction was predicted as taken or not taken.", }, [ POWER7_PME_PM_LSU_REJECT ] = { .pme_name = "PM_LSU_REJECT", .pme_code = 0x10064, .pme_short_desc = "LSU Reject (up to 2 per cycle)", .pme_long_desc = "The Load Store Unit rejected an instruction. Combined Unit 0 + 1", }, [ POWER7_PME_PM_GCT_UTIL_3_TO_6_SLOTS ] = { .pme_name = "PM_GCT_UTIL_3_TO_6_SLOTS", .pme_code = 0x209e, .pme_short_desc = "GCT Utilization 3-6 entries", .pme_long_desc = "GCT Utilization 3-6 entries", }, [ POWER7_PME_PM_CMPLU_STALL_END_GCT_NOSLOT ] = { .pme_name = "PM_CMPLU_STALL_END_GCT_NOSLOT", .pme_code = 0x10028, .pme_short_desc = "Count ended because GCT went empty", .pme_long_desc = "Count ended because GCT went empty", }, [ POWER7_PME_PM_LSU0_REJECT_LMQ_FULL ] = { .pme_name = "PM_LSU0_REJECT_LMQ_FULL", .pme_code = 0xc0a4, .pme_short_desc = "LS0 Reject: LMQ Full (LHR)", .pme_long_desc = "Total cycles the Load Store Unit 0 is busy rejecting instructions because the Load Miss Queue was full. The LMQ has eight entries. If all eight entries are full, subsequent load instructions are rejected.", }, [ POWER7_PME_PM_VSU_FEST ] = { .pme_name = "PM_VSU_FEST", .pme_code = 0xa8b8, .pme_short_desc = "Estimate instruction executed", .pme_long_desc = "Estimate instruction executed", }, [ POWER7_PME_PM_NEST_PAIR0_AND ] = { .pme_name = "PM_NEST_PAIR0_AND", .pme_code = 0x10883, .pme_short_desc = " Nest events (MC0/MC1/PB/GX), Pair0 AND", .pme_long_desc = " Nest events (MC0/MC1/PB/GX), Pair0 AND", }, [ POWER7_PME_PM_PTEG_FROM_L3 ] = { .pme_name = "PM_PTEG_FROM_L3", .pme_code = 0x2c050, .pme_short_desc = "PTEG loaded from L3", .pme_long_desc = "A Page Table Entry was loaded into the TLB from the local L3 due to a demand load.", }, [ POWER7_PME_PM_POWER_EVENT2 ] = { .pme_name = "PM_POWER_EVENT2", .pme_code = 0x2006e, .pme_short_desc = "Power Management Event 2", .pme_long_desc = "Power Management Event 2", }, [ POWER7_PME_PM_IC_PREF_CANCEL_PAGE ] = { .pme_name = "PM_IC_PREF_CANCEL_PAGE", .pme_code = 0x4090, .pme_short_desc = "Prefetch Canceled due to page boundary", .pme_long_desc = "Prefetch Canceled due to page boundary", }, [ POWER7_PME_PM_VSU0_FSQRT_FDIV ] = { .pme_name = "PM_VSU0_FSQRT_FDIV", .pme_code = 0xa088, .pme_short_desc = "four flops operation (fdiv,fsqrt,xsdiv,xssqrt) Scalar Instructions only!", .pme_long_desc = "four flops operation (fdiv,fsqrt,xsdiv,xssqrt) Scalar Instructions only!", }, [ POWER7_PME_PM_MRK_GRP_CMPL ] = { .pme_name = "PM_MRK_GRP_CMPL", .pme_code = 0x40030, .pme_short_desc = "Marked group complete", .pme_long_desc = "A group containing a sampled instruction completed. Microcoded instructions that span multiple groups will generate this event once per group.", }, [ POWER7_PME_PM_VSU0_SCAL_DOUBLE_ISSUED ] = { .pme_name = "PM_VSU0_SCAL_DOUBLE_ISSUED", .pme_code = 0xb088, .pme_short_desc = "Double Precision scalar instruction issued on Pipe0", .pme_long_desc = "Double Precision scalar instruction issued on Pipe0", }, [ POWER7_PME_PM_GRP_DISP ] = { .pme_name = "PM_GRP_DISP", .pme_code = 0x3000a, .pme_short_desc = "dispatch_success (Group Dispatched)", .pme_long_desc = "A group was dispatched", }, [ POWER7_PME_PM_LSU0_LDX ] = { .pme_name = "PM_LSU0_LDX", .pme_code = 0xc088, .pme_short_desc = "LS0 Vector Loads", .pme_long_desc = "LS0 Vector Loads", }, [ POWER7_PME_PM_DATA_FROM_L2 ] = { .pme_name = "PM_DATA_FROM_L2", .pme_code = 0x1c040, .pme_short_desc = "Data loaded from L2", .pme_long_desc = "The processor's Data Cache was reloaded from the local L2 due to a demand load.", }, [ POWER7_PME_PM_MRK_DATA_FROM_RL2L3_MOD ] = { .pme_name = "PM_MRK_DATA_FROM_RL2L3_MOD", .pme_code = 0x1d042, .pme_short_desc = "Marked data loaded from remote L2 or L3 modified", .pme_long_desc = "The processor's Data Cache was reloaded with modified (M) data from an L2 or L3 on a remote module due to a marked load.", }, [ POWER7_PME_PM_LD_REF_L1 ] = { .pme_name = "PM_LD_REF_L1", .pme_code = 0xc880, .pme_short_desc = " L1 D cache load references counted at finish", .pme_long_desc = " L1 D cache load references counted at finish", }, [ POWER7_PME_PM_VSU0_VECT_DOUBLE_ISSUED ] = { .pme_name = "PM_VSU0_VECT_DOUBLE_ISSUED", .pme_code = 0xb080, .pme_short_desc = "Double Precision vector instruction issued on Pipe0", .pme_long_desc = "Double Precision vector instruction issued on Pipe0", }, [ POWER7_PME_PM_VSU1_2FLOP_DOUBLE ] = { .pme_name = "PM_VSU1_2FLOP_DOUBLE", .pme_code = 0xa08e, .pme_short_desc = "two flop DP vector operation (xvadddp, xvmuldp, xvsubdp, xvcmpdp, xvseldp, xvabsdp, xvnabsdp, xvredp ,xvsqrtedp, vxnegdp) ", .pme_long_desc = "two flop DP vector operation (xvadddp, xvmuldp, xvsubdp, xvcmpdp, xvseldp, xvabsdp, xvnabsdp, xvredp ,xvsqrtedp, vxnegdp) ", }, [ POWER7_PME_PM_THRD_PRIO_6_7_CYC ] = { .pme_name = "PM_THRD_PRIO_6_7_CYC", .pme_code = 0x40b6, .pme_short_desc = " Cycles thread running at priority level 6 or 7", .pme_long_desc = " Cycles thread running at priority level 6 or 7", }, [ POWER7_PME_PM_BC_PLUS_8_RSLV_TAKEN ] = { .pme_name = "PM_BC_PLUS_8_RSLV_TAKEN", .pme_code = 0x40ba, .pme_short_desc = "BC+8 Resolve outcome was Taken, resulting in the conditional instruction being canceled", .pme_long_desc = "BC+8 Resolve outcome was Taken, resulting in the conditional instruction being canceled", }, [ POWER7_PME_PM_BR_MPRED_CR ] = { .pme_name = "PM_BR_MPRED_CR", .pme_code = 0x40ac, .pme_short_desc = "Branch mispredict - taken/not taken", .pme_long_desc = "A conditional branch instruction was incorrectly predicted as taken or not taken. The branch execution unit detects a branch mispredict because the CR value is opposite of the predicted value. This will result in a branch redirect flush if not overfidden by a flush of an older instruction.", }, [ POWER7_PME_PM_L3_CO_MEM ] = { .pme_name = "PM_L3_CO_MEM", .pme_code = 0x4f082, .pme_short_desc = "L3 Castouts to L3.1", .pme_long_desc = "L3 Castouts to L3.1", }, [ POWER7_PME_PM_LD_MISS_L1 ] = { .pme_name = "PM_LD_MISS_L1", .pme_code = 0x400f0, .pme_short_desc = "Load Missed L1", .pme_long_desc = "Load references that miss the Level 1 Data cache. Combined unit 0 + 1.", }, [ POWER7_PME_PM_DATA_FROM_RL2L3_MOD ] = { .pme_name = "PM_DATA_FROM_RL2L3_MOD", .pme_code = 0x1c042, .pme_short_desc = "Data loaded from remote L2 or L3 modified", .pme_long_desc = "The processor's Data Cache was reloaded with modified (M) data from an L2 or L3 on a remote module due to a demand load", }, [ POWER7_PME_PM_LSU_SRQ_FULL_CYC ] = { .pme_name = "PM_LSU_SRQ_FULL_CYC", .pme_code = 0x1001a, .pme_short_desc = "Storage Queue is full and is blocking dispatch", .pme_long_desc = "Cycles the Store Request Queue is full.", }, [ POWER7_PME_PM_TABLEWALK_CYC ] = { .pme_name = "PM_TABLEWALK_CYC", .pme_code = 0x10026, .pme_short_desc = "Cycles when a tablewalk (I or D) is active", .pme_long_desc = "Cycles doing instruction or data tablewalks", }, [ POWER7_PME_PM_MRK_PTEG_FROM_RMEM ] = { .pme_name = "PM_MRK_PTEG_FROM_RMEM", .pme_code = 0x3d052, .pme_short_desc = "Marked PTEG loaded from remote memory", .pme_long_desc = "A Page Table Entry was loaded into the ERAT. POWER6 does not have a TLB", }, [ POWER7_PME_PM_LSU_SRQ_STFWD ] = { .pme_name = "PM_LSU_SRQ_STFWD", .pme_code = 0xc8a0, .pme_short_desc = "Load got data from a store", .pme_long_desc = "Data from a store instruction was forwarded to a load. A load that misses L1 but becomes a store forward is treated as a load miss and it causes the DL1 load miss event to be counted. It does not go into the LMQ. If a load that hits L1 but becomes a store forward, then it's not treated as a load miss. Combined Unit 0 + 1.", }, [ POWER7_PME_PM_INST_PTEG_FROM_RMEM ] = { .pme_name = "PM_INST_PTEG_FROM_RMEM", .pme_code = 0x3e052, .pme_short_desc = "Instruction PTEG loaded from remote memory", .pme_long_desc = "Instruction PTEG loaded from remote memory", }, [ POWER7_PME_PM_FXU0_FIN ] = { .pme_name = "PM_FXU0_FIN", .pme_code = 0x10004, .pme_short_desc = "FXU0 Finished", .pme_long_desc = "The Fixed Point unit 0 finished an instruction and produced a result. Instructions that finish may not necessary complete.", }, [ POWER7_PME_PM_LSU1_L1_SW_PREF ] = { .pme_name = "PM_LSU1_L1_SW_PREF", .pme_code = 0xc09e, .pme_short_desc = "LSU1 Software L1 Prefetches, including SW Transient Prefetches", .pme_long_desc = "LSU1 Software L1 Prefetches, including SW Transient Prefetches", }, [ POWER7_PME_PM_PTEG_FROM_L31_MOD ] = { .pme_name = "PM_PTEG_FROM_L31_MOD", .pme_code = 0x1c054, .pme_short_desc = "PTEG loaded from another L3 on same chip modified", .pme_long_desc = "PTEG loaded from another L3 on same chip modified", }, [ POWER7_PME_PM_PMC5_OVERFLOW ] = { .pme_name = "PM_PMC5_OVERFLOW", .pme_code = 0x10024, .pme_short_desc = "Overflow from counter 5", .pme_long_desc = "Overflows from PMC5 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.", }, [ POWER7_PME_PM_LD_REF_L1_LSU1 ] = { .pme_name = "PM_LD_REF_L1_LSU1", .pme_code = 0xc082, .pme_short_desc = "LS1 L1 D cache load references counted at finish", .pme_long_desc = "Load references to Level 1 Data Cache, by unit 1.", }, [ POWER7_PME_PM_INST_PTEG_FROM_L21_SHR ] = { .pme_name = "PM_INST_PTEG_FROM_L21_SHR", .pme_code = 0x4e056, .pme_short_desc = "Instruction PTEG loaded from another L2 on same chip shared", .pme_long_desc = "Instruction PTEG loaded from another L2 on same chip shared", }, [ POWER7_PME_PM_CMPLU_STALL_THRD ] = { .pme_name = "PM_CMPLU_STALL_THRD", .pme_code = 0x1001c, .pme_short_desc = "Completion Stalled due to thread conflict. Group ready to complete but it was another thread's turn", .pme_long_desc = "Completion Stalled due to thread conflict. Group ready to complete but it was another thread's turn", }, [ POWER7_PME_PM_DATA_FROM_RMEM ] = { .pme_name = "PM_DATA_FROM_RMEM", .pme_code = 0x3c042, .pme_short_desc = "Data loaded from remote memory", .pme_long_desc = "The processor's Data Cache was reloaded from memory attached to a different module than this proccessor is located on.", }, [ POWER7_PME_PM_VSU0_SCAL_SINGLE_ISSUED ] = { .pme_name = "PM_VSU0_SCAL_SINGLE_ISSUED", .pme_code = 0xb084, .pme_short_desc = "Single Precision scalar instruction issued on Pipe0", .pme_long_desc = "Single Precision scalar instruction issued on Pipe0", }, [ POWER7_PME_PM_BR_MPRED_LSTACK ] = { .pme_name = "PM_BR_MPRED_LSTACK", .pme_code = 0x40a6, .pme_short_desc = "Branch Mispredict due to Link Stack", .pme_long_desc = "Branch Mispredict due to Link Stack", }, [ POWER7_PME_PM_MRK_DATA_FROM_RL2L3_MOD_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_RL2L3_MOD_CYC", .pme_code = 0x40028, .pme_short_desc = "Marked ld latency Data source 1001 (L2.5/L3.5 M same 4 chip node)", .pme_long_desc = "Marked ld latency Data source 1001 (L2.5/L3.5 M same 4 chip node)", }, [ POWER7_PME_PM_LSU0_FLUSH_UST ] = { .pme_name = "PM_LSU0_FLUSH_UST", .pme_code = 0xc0b4, .pme_short_desc = "LS0 Flush: Unaligned Store", .pme_long_desc = "A store was flushed from unit 0 because it was unaligned (crossed a 4K boundary).", }, [ POWER7_PME_PM_LSU_NCST ] = { .pme_name = "PM_LSU_NCST", .pme_code = 0xc090, .pme_short_desc = "Non-cachable Stores sent to nest", .pme_long_desc = "Non-cachable Stores sent to nest", }, [ POWER7_PME_PM_BR_TAKEN ] = { .pme_name = "PM_BR_TAKEN", .pme_code = 0x20004, .pme_short_desc = "Branch Taken", .pme_long_desc = "A branch instruction was taken. This could have been a conditional branch or an unconditional branch", }, [ POWER7_PME_PM_INST_PTEG_FROM_LMEM ] = { .pme_name = "PM_INST_PTEG_FROM_LMEM", .pme_code = 0x4e052, .pme_short_desc = "Instruction PTEG loaded from local memory", .pme_long_desc = "Instruction PTEG loaded from local memory", }, [ POWER7_PME_PM_GCT_NOSLOT_BR_MPRED_IC_MISS ] = { .pme_name = "PM_GCT_NOSLOT_BR_MPRED_IC_MISS", .pme_code = 0x4001c, .pme_short_desc = "GCT empty by branch mispredict + IC miss", .pme_long_desc = "No slot in GCT caused by branch mispredict or I cache miss", }, [ POWER7_PME_PM_DTLB_MISS_4K ] = { .pme_name = "PM_DTLB_MISS_4K", .pme_code = 0x2c05a, .pme_short_desc = "Data TLB miss for 4K page", .pme_long_desc = "Data TLB references to 4KB pages that missed the TLB. Page size is determined at TLB reload time.", }, [ POWER7_PME_PM_PMC4_SAVED ] = { .pme_name = "PM_PMC4_SAVED", .pme_code = 0x30022, .pme_short_desc = "PMC4 Rewind Value saved (matched condition)", .pme_long_desc = "PMC4 was counting speculatively. The speculative condition was met and the counter value was committed by copying it to the backup register.", }, [ POWER7_PME_PM_VSU1_PERMUTE_ISSUED ] = { .pme_name = "PM_VSU1_PERMUTE_ISSUED", .pme_code = 0xb092, .pme_short_desc = "Permute VMX Instruction Issued", .pme_long_desc = "Permute VMX Instruction Issued", }, [ POWER7_PME_PM_SLB_MISS ] = { .pme_name = "PM_SLB_MISS", .pme_code = 0xd890, .pme_short_desc = "Data + Instruction SLB Miss - Total of all segment sizes", .pme_long_desc = "Total of all Segment Lookaside Buffer (SLB) misses, Instructions + Data.", }, [ POWER7_PME_PM_LSU1_FLUSH_LRQ ] = { .pme_name = "PM_LSU1_FLUSH_LRQ", .pme_code = 0xc0ba, .pme_short_desc = "LS1 Flush: LRQ", .pme_long_desc = "Load Hit Load or Store Hit Load flush. A younger load was flushed from unit 1 because it executed before an older store and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.", }, [ POWER7_PME_PM_DTLB_MISS ] = { .pme_name = "PM_DTLB_MISS", .pme_code = 0x300fc, .pme_short_desc = "TLB reload valid", .pme_long_desc = "Data TLB misses, all page sizes.", }, [ POWER7_PME_PM_VSU1_FRSP ] = { .pme_name = "PM_VSU1_FRSP", .pme_code = 0xa0b6, .pme_short_desc = "Round to single precision instruction executed", .pme_long_desc = "Round to single precision instruction executed", }, [ POWER7_PME_PM_VSU_VECTOR_DOUBLE_ISSUED ] = { .pme_name = "PM_VSU_VECTOR_DOUBLE_ISSUED", .pme_code = 0xb880, .pme_short_desc = "Double Precision vector instruction issued on Pipe0", .pme_long_desc = "Double Precision vector instruction issued on Pipe0", }, [ POWER7_PME_PM_L2_CASTOUT_SHR ] = { .pme_name = "PM_L2_CASTOUT_SHR", .pme_code = 0x16182, .pme_short_desc = "L2 Castouts - Shared (T, Te, Si, S)", .pme_long_desc = "An L2 line in the Shared state was castout. Total for all slices.", }, [ POWER7_PME_PM_DATA_FROM_DL2L3_SHR ] = { .pme_name = "PM_DATA_FROM_DL2L3_SHR", .pme_code = 0x3c044, .pme_short_desc = "Data loaded from distant L2 or L3 shared", .pme_long_desc = "The processor's Data Cache was reloaded with shared (T or SL) data from an L2 or L3 on a distant module due to a demand load", }, [ POWER7_PME_PM_VSU1_STF ] = { .pme_name = "PM_VSU1_STF", .pme_code = 0xb08e, .pme_short_desc = "FPU store (SP or DP) issued on Pipe1", .pme_long_desc = "FPU store (SP or DP) issued on Pipe1", }, [ POWER7_PME_PM_ST_FIN ] = { .pme_name = "PM_ST_FIN", .pme_code = 0x200f0, .pme_short_desc = "Store Instructions Finished", .pme_long_desc = "Store requests sent to the nest.", }, [ POWER7_PME_PM_PTEG_FROM_L21_SHR ] = { .pme_name = "PM_PTEG_FROM_L21_SHR", .pme_code = 0x4c056, .pme_short_desc = "PTEG loaded from another L2 on same chip shared", .pme_long_desc = "PTEG loaded from another L2 on same chip shared", }, [ POWER7_PME_PM_L2_LOC_GUESS_WRONG ] = { .pme_name = "PM_L2_LOC_GUESS_WRONG", .pme_code = 0x26480, .pme_short_desc = "L2 guess loc and guess was not correct (ie data remote)", .pme_long_desc = "L2 guess loc and guess was not correct (ie data remote)", }, [ POWER7_PME_PM_MRK_STCX_FAIL ] = { .pme_name = "PM_MRK_STCX_FAIL", .pme_code = 0xd08e, .pme_short_desc = "Marked STCX failed", .pme_long_desc = "A marked stcx (stwcx or stdcx) failed", }, [ POWER7_PME_PM_LSU0_REJECT_LHS ] = { .pme_name = "PM_LSU0_REJECT_LHS", .pme_code = 0xc0ac, .pme_short_desc = "LS0 Reject: Load Hit Store", .pme_long_desc = "Load Store Unit 0 rejected a load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully.", }, [ POWER7_PME_PM_IC_PREF_CANCEL_HIT ] = { .pme_name = "PM_IC_PREF_CANCEL_HIT", .pme_code = 0x4092, .pme_short_desc = "Prefetch Canceled due to icache hit", .pme_long_desc = "Prefetch Canceled due to icache hit", }, [ POWER7_PME_PM_L3_PREF_BUSY ] = { .pme_name = "PM_L3_PREF_BUSY", .pme_code = 0x4f080, .pme_short_desc = "Prefetch machines >= threshold (8,16,20,24)", .pme_long_desc = "Prefetch machines >= threshold (8,16,20,24)", }, [ POWER7_PME_PM_MRK_BRU_FIN ] = { .pme_name = "PM_MRK_BRU_FIN", .pme_code = 0x2003a, .pme_short_desc = "bru marked instr finish", .pme_long_desc = "The branch unit finished a marked instruction. Instructions that finish may not necessary complete.", }, [ POWER7_PME_PM_LSU1_NCLD ] = { .pme_name = "PM_LSU1_NCLD", .pme_code = 0xc08e, .pme_short_desc = "LS1 Non-cachable Loads counted at finish", .pme_long_desc = "A non-cacheable load was executed by Unit 0.", }, [ POWER7_PME_PM_INST_PTEG_FROM_L31_MOD ] = { .pme_name = "PM_INST_PTEG_FROM_L31_MOD", .pme_code = 0x1e054, .pme_short_desc = "Instruction PTEG loaded from another L3 on same chip modified", .pme_long_desc = "Instruction PTEG loaded from another L3 on same chip modified", }, [ POWER7_PME_PM_LSU_NCLD ] = { .pme_name = "PM_LSU_NCLD", .pme_code = 0xc88c, .pme_short_desc = "Non-cachable Loads counted at finish", .pme_long_desc = "A non-cacheable load was executed. Combined Unit 0 + 1.", }, [ POWER7_PME_PM_LSU_LDX ] = { .pme_name = "PM_LSU_LDX", .pme_code = 0xc888, .pme_short_desc = "All Vector loads (vsx vector + vmx vector)", .pme_long_desc = "All Vector loads (vsx vector + vmx vector)", }, [ POWER7_PME_PM_L2_LOC_GUESS_CORRECT ] = { .pme_name = "PM_L2_LOC_GUESS_CORRECT", .pme_code = 0x16480, .pme_short_desc = "L2 guess loc and guess was correct (ie data local)", .pme_long_desc = "L2 guess loc and guess was correct (ie data local)", }, [ POWER7_PME_PM_THRESH_TIMEO ] = { .pme_name = "PM_THRESH_TIMEO", .pme_code = 0x10038, .pme_short_desc = "Threshold timeout event", .pme_long_desc = "The threshold timer expired", }, [ POWER7_PME_PM_L3_PREF_ST ] = { .pme_name = "PM_L3_PREF_ST", .pme_code = 0xd0ae, .pme_short_desc = "L3 cache ST prefetches", .pme_long_desc = "L3 cache ST prefetches", }, [ POWER7_PME_PM_DISP_CLB_HELD_SYNC ] = { .pme_name = "PM_DISP_CLB_HELD_SYNC", .pme_code = 0x2098, .pme_short_desc = "Dispatch/CLB Hold: Sync type instruction", .pme_long_desc = "Dispatch/CLB Hold: Sync type instruction", }, [ POWER7_PME_PM_VSU_SIMPLE_ISSUED ] = { .pme_name = "PM_VSU_SIMPLE_ISSUED", .pme_code = 0xb894, .pme_short_desc = "Simple VMX instruction issued", .pme_long_desc = "Simple VMX instruction issued", }, [ POWER7_PME_PM_VSU1_SINGLE ] = { .pme_name = "PM_VSU1_SINGLE", .pme_code = 0xa0aa, .pme_short_desc = "FPU single precision", .pme_long_desc = "VSU1 executed single precision instruction", }, [ POWER7_PME_PM_DATA_TABLEWALK_CYC ] = { .pme_name = "PM_DATA_TABLEWALK_CYC", .pme_code = 0x3001a, .pme_short_desc = "Data Tablewalk Active", .pme_long_desc = "Cycles a translation tablewalk is active. While a tablewalk is active any request attempting to access the TLB will be rejected and retried.", }, [ POWER7_PME_PM_L2_RC_ST_DONE ] = { .pme_name = "PM_L2_RC_ST_DONE", .pme_code = 0x36380, .pme_short_desc = "RC did st to line that was Tx or Sx", .pme_long_desc = "RC did st to line that was Tx or Sx", }, [ POWER7_PME_PM_MRK_PTEG_FROM_L21_MOD ] = { .pme_name = "PM_MRK_PTEG_FROM_L21_MOD", .pme_code = 0x3d056, .pme_short_desc = "Marked PTEG loaded from another L2 on same chip modified", .pme_long_desc = "Marked PTEG loaded from another L2 on same chip modified", }, [ POWER7_PME_PM_LARX_LSU1 ] = { .pme_name = "PM_LARX_LSU1", .pme_code = 0xc096, .pme_short_desc = "ls1 Larx Finished", .pme_long_desc = "A larx (lwarx or ldarx) was executed on side 1 ", }, [ POWER7_PME_PM_MRK_DATA_FROM_RMEM ] = { .pme_name = "PM_MRK_DATA_FROM_RMEM", .pme_code = 0x3d042, .pme_short_desc = "Marked data loaded from remote memory", .pme_long_desc = "The processor's Data Cache was reloaded due to a marked load from memory attached to a different module than this proccessor is located on.", }, [ POWER7_PME_PM_DISP_CLB_HELD ] = { .pme_name = "PM_DISP_CLB_HELD", .pme_code = 0x2090, .pme_short_desc = "CLB Hold: Any Reason", .pme_long_desc = "CLB Hold: Any Reason", }, [ POWER7_PME_PM_DERAT_MISS_4K ] = { .pme_name = "PM_DERAT_MISS_4K", .pme_code = 0x1c05c, .pme_short_desc = "DERAT misses for 4K page", .pme_long_desc = "A data request (load or store) missed the ERAT for 4K page and resulted in an ERAT reload.", }, [ POWER7_PME_PM_L2_RCLD_DISP_FAIL_ADDR ] = { .pme_name = "PM_L2_RCLD_DISP_FAIL_ADDR", .pme_code = 0x16282, .pme_short_desc = " L2 RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ", .pme_long_desc = " L2 RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ", }, [ POWER7_PME_PM_SEG_EXCEPTION ] = { .pme_name = "PM_SEG_EXCEPTION", .pme_code = 0x28a4, .pme_short_desc = "ISEG + DSEG Exception", .pme_long_desc = "ISEG + DSEG Exception", }, [ POWER7_PME_PM_FLUSH_DISP_SB ] = { .pme_name = "PM_FLUSH_DISP_SB", .pme_code = 0x208c, .pme_short_desc = "Dispatch Flush: Scoreboard", .pme_long_desc = "Dispatch Flush: Scoreboard", }, [ POWER7_PME_PM_L2_DC_INV ] = { .pme_name = "PM_L2_DC_INV", .pme_code = 0x26182, .pme_short_desc = "Dcache invalidates from L2 ", .pme_long_desc = "The L2 invalidated a line in processor's data cache. This is caused by the L2 line being cast out or invalidated. Total for all slices", }, [ POWER7_PME_PM_PTEG_FROM_DL2L3_MOD ] = { .pme_name = "PM_PTEG_FROM_DL2L3_MOD", .pme_code = 0x4c054, .pme_short_desc = "PTEG loaded from distant L2 or L3 modified", .pme_long_desc = "A Page Table Entry was loaded into the ERAT with modified (M) data from an L2 or L3 on a distant module due to a demand load or store.", }, [ POWER7_PME_PM_DSEG ] = { .pme_name = "PM_DSEG", .pme_code = 0x20a6, .pme_short_desc = "DSEG Exception", .pme_long_desc = "DSEG Exception", }, [ POWER7_PME_PM_BR_PRED_LSTACK ] = { .pme_name = "PM_BR_PRED_LSTACK", .pme_code = 0x40a2, .pme_short_desc = "Link Stack Predictions", .pme_long_desc = "The target address of a Branch to Link instruction was predicted by the link stack.", }, [ POWER7_PME_PM_VSU0_STF ] = { .pme_name = "PM_VSU0_STF", .pme_code = 0xb08c, .pme_short_desc = "FPU store (SP or DP) issued on Pipe0", .pme_long_desc = "FPU store (SP or DP) issued on Pipe0", }, [ POWER7_PME_PM_LSU_FX_FIN ] = { .pme_name = "PM_LSU_FX_FIN", .pme_code = 0x10066, .pme_short_desc = "LSU Finished a FX operation (up to 2 per cycle)", .pme_long_desc = "LSU Finished a FX operation (up to 2 per cycle)", }, [ POWER7_PME_PM_DERAT_MISS_16M ] = { .pme_name = "PM_DERAT_MISS_16M", .pme_code = 0x3c05c, .pme_short_desc = "DERAT misses for 16M page", .pme_long_desc = "A data request (load or store) missed the ERAT for 16M page and resulted in an ERAT reload.", }, [ POWER7_PME_PM_MRK_PTEG_FROM_DL2L3_MOD ] = { .pme_name = "PM_MRK_PTEG_FROM_DL2L3_MOD", .pme_code = 0x4d054, .pme_short_desc = "Marked PTEG loaded from distant L2 or L3 modified", .pme_long_desc = "A Page Table Entry was loaded into the ERAT with modified (M) data from an L2 or L3 on a distant module due to a marked load or store.", }, [ POWER7_PME_PM_GCT_UTIL_11_PLUS_SLOTS ] = { .pme_name = "PM_GCT_UTIL_11_PLUS_SLOTS", .pme_code = 0x20a2, .pme_short_desc = "GCT Utilization 11+ entries", .pme_long_desc = "GCT Utilization 11+ entries", }, [ POWER7_PME_PM_INST_FROM_L3 ] = { .pme_name = "PM_INST_FROM_L3", .pme_code = 0x14048, .pme_short_desc = "Instruction fetched from L3", .pme_long_desc = "An instruction fetch group was fetched from L3. Fetch Groups can contain up to 8 instructions", }, [ POWER7_PME_PM_MRK_IFU_FIN ] = { .pme_name = "PM_MRK_IFU_FIN", .pme_code = 0x3003a, .pme_short_desc = "IFU non-branch marked instruction finished", .pme_long_desc = "The Instruction Fetch Unit finished a marked instruction.", }, [ POWER7_PME_PM_ITLB_MISS ] = { .pme_name = "PM_ITLB_MISS", .pme_code = 0x400fc, .pme_short_desc = "ITLB Reloaded (always zero on POWER6)", .pme_long_desc = "A TLB miss for an Instruction Fetch has occurred", }, [ POWER7_PME_PM_VSU_STF ] = { .pme_name = "PM_VSU_STF", .pme_code = 0xb88c, .pme_short_desc = "FPU store (SP or DP) issued on Pipe0", .pme_long_desc = "FPU store (SP or DP) issued on Pipe0", }, [ POWER7_PME_PM_LSU_FLUSH_UST ] = { .pme_name = "PM_LSU_FLUSH_UST", .pme_code = 0xc8b4, .pme_short_desc = "Flush: Unaligned Store", .pme_long_desc = "A store was flushed because it was unaligned (crossed a 4K boundary). Combined Unit 0 + 1.", }, [ POWER7_PME_PM_L2_LDST_MISS ] = { .pme_name = "PM_L2_LDST_MISS", .pme_code = 0x26880, .pme_short_desc = "Data Load+Store Miss", .pme_long_desc = "Data Load+Store Miss", }, [ POWER7_PME_PM_FXU1_FIN ] = { .pme_name = "PM_FXU1_FIN", .pme_code = 0x40004, .pme_short_desc = "FXU1 Finished", .pme_long_desc = "The Fixed Point unit 1 finished an instruction and produced a result. Instructions that finish may not necessary complete.", }, [ POWER7_PME_PM_SHL_DEALLOCATED ] = { .pme_name = "PM_SHL_DEALLOCATED", .pme_code = 0x5080, .pme_short_desc = "SHL Table entry deallocated", .pme_long_desc = "SHL Table entry deallocated", }, [ POWER7_PME_PM_L2_SN_M_WR_DONE ] = { .pme_name = "PM_L2_SN_M_WR_DONE", .pme_code = 0x46382, .pme_short_desc = "SNP dispatched for a write and was M", .pme_long_desc = "SNP dispatched for a write and was M", }, [ POWER7_PME_PM_LSU_REJECT_SET_MPRED ] = { .pme_name = "PM_LSU_REJECT_SET_MPRED", .pme_code = 0xc8a8, .pme_short_desc = "Reject: Set Predict Wrong", .pme_long_desc = "The Load Store Unit rejected an instruction because the cache set was improperly predicted. This is a fast reject and will be immediately redispatched. Combined Unit 0 + 1", }, [ POWER7_PME_PM_L3_PREF_LD ] = { .pme_name = "PM_L3_PREF_LD", .pme_code = 0xd0ac, .pme_short_desc = "L3 cache LD prefetches", .pme_long_desc = "L3 cache LD prefetches", }, [ POWER7_PME_PM_L2_SN_M_RD_DONE ] = { .pme_name = "PM_L2_SN_M_RD_DONE", .pme_code = 0x46380, .pme_short_desc = "SNP dispatched for a read and was M", .pme_long_desc = "SNP dispatched for a read and was M", }, [ POWER7_PME_PM_MRK_DERAT_MISS_16G ] = { .pme_name = "PM_MRK_DERAT_MISS_16G", .pme_code = 0x4d05c, .pme_short_desc = "Marked DERAT misses for 16G page", .pme_long_desc = "A marked data request (load or store) missed the ERAT for 16G page and resulted in an ERAT reload.", }, [ POWER7_PME_PM_VSU_FCONV ] = { .pme_name = "PM_VSU_FCONV", .pme_code = 0xa8b0, .pme_short_desc = "Convert instruction executed", .pme_long_desc = "Convert instruction executed", }, [ POWER7_PME_PM_ANY_THRD_RUN_CYC ] = { .pme_name = "PM_ANY_THRD_RUN_CYC", .pme_code = 0x100fa, .pme_short_desc = "One of threads in run_cycles ", .pme_long_desc = "One of threads in run_cycles ", }, [ POWER7_PME_PM_LSU_LMQ_FULL_CYC ] = { .pme_name = "PM_LSU_LMQ_FULL_CYC", .pme_code = 0xd0a4, .pme_short_desc = "LMQ full", .pme_long_desc = "The Load Miss Queue was full.", }, [ POWER7_PME_PM_MRK_LSU_REJECT_LHS ] = { .pme_name = "PM_MRK_LSU_REJECT_LHS", .pme_code = 0xd082, .pme_short_desc = " Reject(marked): Load Hit Store", .pme_long_desc = "The Load Store Unit rejected a marked load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully", }, [ POWER7_PME_PM_MRK_LD_MISS_L1_CYC ] = { .pme_name = "PM_MRK_LD_MISS_L1_CYC", .pme_code = 0x4003e, .pme_short_desc = "L1 data load miss cycles", .pme_long_desc = "L1 data load miss cycles", }, [ POWER7_PME_PM_MRK_DATA_FROM_L2_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L2_CYC", .pme_code = 0x20020, .pme_short_desc = "Marked ld latency Data source 0000 (L2 hit)", .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.", }, [ POWER7_PME_PM_INST_IMC_MATCH_DISP ] = { .pme_name = "PM_INST_IMC_MATCH_DISP", .pme_code = 0x30016, .pme_short_desc = "IMC Matches dispatched", .pme_long_desc = "IMC Matches dispatched", }, [ POWER7_PME_PM_MRK_DATA_FROM_RMEM_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_RMEM_CYC", .pme_code = 0x4002c, .pme_short_desc = "Marked ld latency Data source 1101 (Memory same 4 chip node)", .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.", }, [ POWER7_PME_PM_VSU0_SIMPLE_ISSUED ] = { .pme_name = "PM_VSU0_SIMPLE_ISSUED", .pme_code = 0xb094, .pme_short_desc = "Simple VMX instruction issued", .pme_long_desc = "Simple VMX instruction issued", }, [ POWER7_PME_PM_CMPLU_STALL_DIV ] = { .pme_name = "PM_CMPLU_STALL_DIV", .pme_code = 0x40014, .pme_short_desc = "Completion stall caused by DIV instruction", .pme_long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes was a fixed point divide instruction. This is a subset of PM_CMPLU_STALL_FXU.", }, [ POWER7_PME_PM_MRK_PTEG_FROM_RL2L3_SHR ] = { .pme_name = "PM_MRK_PTEG_FROM_RL2L3_SHR", .pme_code = 0x2d054, .pme_short_desc = "Marked PTEG loaded from remote L2 or L3 shared", .pme_long_desc = "A Page Table Entry was loaded into the ERAT from memory attached to a different module than this proccessor is located on due to a marked load or store.", }, [ POWER7_PME_PM_VSU_FMA_DOUBLE ] = { .pme_name = "PM_VSU_FMA_DOUBLE", .pme_code = 0xa890, .pme_short_desc = "DP vector version of fmadd,fnmadd,fmsub,fnmsub", .pme_long_desc = "DP vector version of fmadd,fnmadd,fmsub,fnmsub", }, [ POWER7_PME_PM_VSU_4FLOP ] = { .pme_name = "PM_VSU_4FLOP", .pme_code = 0xa89c, .pme_short_desc = "four flops operation (scalar fdiv, fsqrt; DP vector version of fmadd, fnmadd, fmsub, fnmsub; SP vector versions of single flop instructions)", .pme_long_desc = "four flops operation (scalar fdiv, fsqrt; DP vector version of fmadd, fnmadd, fmsub, fnmsub; SP vector versions of single flop instructions)", }, [ POWER7_PME_PM_VSU1_FIN ] = { .pme_name = "PM_VSU1_FIN", .pme_code = 0xa0be, .pme_short_desc = "VSU1 Finished an instruction", .pme_long_desc = "VSU1 Finished an instruction", }, [ POWER7_PME_PM_NEST_PAIR1_AND ] = { .pme_name = "PM_NEST_PAIR1_AND", .pme_code = 0x20883, .pme_short_desc = " Nest events (MC0/MC1/PB/GX), Pair1 AND", .pme_long_desc = " Nest events (MC0/MC1/PB/GX), Pair1 AND", }, [ POWER7_PME_PM_INST_PTEG_FROM_RL2L3_MOD ] = { .pme_name = "PM_INST_PTEG_FROM_RL2L3_MOD", .pme_code = 0x1e052, .pme_short_desc = "Instruction PTEG loaded from remote L2 or L3 modified", .pme_long_desc = "Instruction PTEG loaded from remote L2 or L3 modified", }, [ POWER7_PME_PM_RUN_CYC ] = { .pme_name = "PM_RUN_CYC", .pme_code = 0x200f4, .pme_short_desc = "Run_cycles", .pme_long_desc = "Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.", }, [ POWER7_PME_PM_PTEG_FROM_RMEM ] = { .pme_name = "PM_PTEG_FROM_RMEM", .pme_code = 0x3c052, .pme_short_desc = "PTEG loaded from remote memory", .pme_long_desc = "A Page Table Entry was loaded into the TLB from memory attached to a different module than this proccessor is located on.", }, [ POWER7_PME_PM_LSU_LRQ_S0_VALID ] = { .pme_name = "PM_LSU_LRQ_S0_VALID", .pme_code = 0xd09e, .pme_short_desc = "Slot 0 of LRQ valid", .pme_long_desc = "This signal is asserted every cycle that the Load Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin. In SMT mode the LRQ is split between the two threads (16 entries each).", }, [ POWER7_PME_PM_LSU0_LDF ] = { .pme_name = "PM_LSU0_LDF", .pme_code = 0xc084, .pme_short_desc = "LS0 Scalar Loads", .pme_long_desc = "A floating point load was executed by LSU0", }, [ POWER7_PME_PM_FLUSH_COMPLETION ] = { .pme_name = "PM_FLUSH_COMPLETION", .pme_code = 0x30012, .pme_short_desc = "Completion Flush", .pme_long_desc = "Completion Flush", }, [ POWER7_PME_PM_ST_MISS_L1 ] = { .pme_name = "PM_ST_MISS_L1", .pme_code = 0x300f0, .pme_short_desc = "L1 D cache store misses", .pme_long_desc = "A store missed the dcache. Combined Unit 0 + 1.", }, [ POWER7_PME_PM_L2_NODE_PUMP ] = { .pme_name = "PM_L2_NODE_PUMP", .pme_code = 0x36480, .pme_short_desc = "RC req that was a local (aka node) pump attempt", .pme_long_desc = "RC req that was a local (aka node) pump attempt", }, [ POWER7_PME_PM_INST_FROM_DL2L3_SHR ] = { .pme_name = "PM_INST_FROM_DL2L3_SHR", .pme_code = 0x34044, .pme_short_desc = "Instruction fetched from distant L2 or L3 shared", .pme_long_desc = "An instruction fetch group was fetched with shared (S) data from the L2 or L3 on a distant module. Fetch groups can contain up to 8 instructions", }, [ POWER7_PME_PM_MRK_STALL_CMPLU_CYC ] = { .pme_name = "PM_MRK_STALL_CMPLU_CYC", .pme_code = 0x3003e, .pme_short_desc = "Marked Group Completion Stall cycles ", .pme_long_desc = "Marked Group Completion Stall cycles ", }, [ POWER7_PME_PM_VSU1_DENORM ] = { .pme_name = "PM_VSU1_DENORM", .pme_code = 0xa0ae, .pme_short_desc = "FPU denorm operand", .pme_long_desc = "VSU1 received denormalized data", }, [ POWER7_PME_PM_MRK_DATA_FROM_L31_SHR_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L31_SHR_CYC", .pme_code = 0x20026, .pme_short_desc = "Marked ld latency Data source 0110 (L3.1 S) ", .pme_long_desc = "Marked load latency Data source 0110 (L3.1 S) ", }, [ POWER7_PME_PM_NEST_PAIR0_ADD ] = { .pme_name = "PM_NEST_PAIR0_ADD", .pme_code = 0x10881, .pme_short_desc = " Nest events (MC0/MC1/PB/GX), Pair0 ADD", .pme_long_desc = " Nest events (MC0/MC1/PB/GX), Pair0 ADD", }, [ POWER7_PME_PM_INST_FROM_L3MISS ] = { .pme_name = "PM_INST_FROM_L3MISS", .pme_code = 0x24048, .pme_short_desc = "Instruction fetched missed L3", .pme_long_desc = "An instruction fetch group was fetched from beyond L3. Fetch groups can contain up to 8 instructions.", }, [ POWER7_PME_PM_EE_OFF_EXT_INT ] = { .pme_name = "PM_EE_OFF_EXT_INT", .pme_code = 0x2080, .pme_short_desc = "ee off and external interrupt", .pme_long_desc = "Cycles when an interrupt due to an external exception is pending but external exceptions were masked.", }, [ POWER7_PME_PM_INST_PTEG_FROM_DMEM ] = { .pme_name = "PM_INST_PTEG_FROM_DMEM", .pme_code = 0x2e052, .pme_short_desc = "Instruction PTEG loaded from distant memory", .pme_long_desc = "Instruction PTEG loaded from distant memory", }, [ POWER7_PME_PM_INST_FROM_DL2L3_MOD ] = { .pme_name = "PM_INST_FROM_DL2L3_MOD", .pme_code = 0x3404c, .pme_short_desc = "Instruction fetched from distant L2 or L3 modified", .pme_long_desc = "An instruction fetch group was fetched with modified (M) data from an L2 or L3 on a distant module. Fetch groups can contain up to 8 instructions", }, [ POWER7_PME_PM_PMC6_OVERFLOW ] = { .pme_name = "PM_PMC6_OVERFLOW", .pme_code = 0x30024, .pme_short_desc = "Overflow from counter 6", .pme_long_desc = "Overflows from PMC6 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.", }, [ POWER7_PME_PM_VSU_2FLOP_DOUBLE ] = { .pme_name = "PM_VSU_2FLOP_DOUBLE", .pme_code = 0xa88c, .pme_short_desc = "DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg", .pme_long_desc = "DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg", }, [ POWER7_PME_PM_TLB_MISS ] = { .pme_name = "PM_TLB_MISS", .pme_code = 0x20066, .pme_short_desc = "TLB Miss (I + D)", .pme_long_desc = "Total of Data TLB mises + Instruction TLB misses", }, [ POWER7_PME_PM_FXU_BUSY ] = { .pme_name = "PM_FXU_BUSY", .pme_code = 0x2000e, .pme_short_desc = "fxu0 busy and fxu1 busy.", .pme_long_desc = "Cycles when both FXU0 and FXU1 are busy.", }, [ POWER7_PME_PM_L2_RCLD_DISP_FAIL_OTHER ] = { .pme_name = "PM_L2_RCLD_DISP_FAIL_OTHER", .pme_code = 0x26280, .pme_short_desc = " L2 RC load dispatch attempt failed due to other reasons", .pme_long_desc = " L2 RC load dispatch attempt failed due to other reasons", }, [ POWER7_PME_PM_LSU_REJECT_LMQ_FULL ] = { .pme_name = "PM_LSU_REJECT_LMQ_FULL", .pme_code = 0xc8a4, .pme_short_desc = "Reject: LMQ Full (LHR)", .pme_long_desc = "Total cycles the Load Store Unit is busy rejecting instructions because the Load Miss Queue was full. The LMQ has eight entries. If all the eight entries are full, subsequent load instructions are rejected. Combined unit 0 + 1.", }, [ POWER7_PME_PM_IC_RELOAD_SHR ] = { .pme_name = "PM_IC_RELOAD_SHR", .pme_code = 0x4096, .pme_short_desc = "Reloading line to be shared between the threads", .pme_long_desc = "An Instruction Cache request was made by this thread and the cache line was already in the cache for the other thread. The line is marked valid for all threads.", }, [ POWER7_PME_PM_GRP_MRK ] = { .pme_name = "PM_GRP_MRK", .pme_code = 0x10031, .pme_short_desc = "IDU Marked Instruction", .pme_long_desc = "A group was sampled (marked). The group is called a marked group. One instruction within the group is tagged for detailed monitoring. The sampled instruction is called a marked instructions. Events associated with the marked instruction are annotated with the marked term.", }, [ POWER7_PME_PM_MRK_ST_NEST ] = { .pme_name = "PM_MRK_ST_NEST", .pme_code = 0x20034, .pme_short_desc = "marked store sent to Nest", .pme_long_desc = "A sampled store has been sent to the memory subsystem", }, [ POWER7_PME_PM_VSU1_FSQRT_FDIV ] = { .pme_name = "PM_VSU1_FSQRT_FDIV", .pme_code = 0xa08a, .pme_short_desc = "four flops operation (fdiv,fsqrt,xsdiv,xssqrt) Scalar Instructions only!", .pme_long_desc = "four flops operation (fdiv,fsqrt,xsdiv,xssqrt) Scalar Instructions only!", }, [ POWER7_PME_PM_LSU0_FLUSH_LRQ ] = { .pme_name = "PM_LSU0_FLUSH_LRQ", .pme_code = 0xc0b8, .pme_short_desc = "LS0 Flush: LRQ", .pme_long_desc = "Load Hit Load or Store Hit Load flush. A younger load was flushed from unit 0 because it executed before an older store and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.", }, [ POWER7_PME_PM_LARX_LSU0 ] = { .pme_name = "PM_LARX_LSU0", .pme_code = 0xc094, .pme_short_desc = "ls0 Larx Finished", .pme_long_desc = "A larx (lwarx or ldarx) was executed on side 0 ", }, [ POWER7_PME_PM_IBUF_FULL_CYC ] = { .pme_name = "PM_IBUF_FULL_CYC", .pme_code = 0x4084, .pme_short_desc = "Cycles No room in ibuff", .pme_long_desc = "Cycles with the Instruction Buffer was full. The Instruction Buffer is a circular queue of 64 instructions per thread, organized as 16 groups of 4 instructions.", }, [ POWER7_PME_PM_MRK_DATA_FROM_DL2L3_SHR_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_DL2L3_SHR_CYC", .pme_code = 0x2002a, .pme_short_desc = "Marked ld latency Data Source 1010 (Distant L2.75/L3.75 S)", .pme_long_desc = "Marked ld latency Data Source 1010 (Distant L2.75/L3.75 S)", }, [ POWER7_PME_PM_LSU_DC_PREF_STREAM_ALLOC ] = { .pme_name = "PM_LSU_DC_PREF_STREAM_ALLOC", .pme_code = 0xd8a8, .pme_short_desc = "D cache new prefetch stream allocated", .pme_long_desc = "D cache new prefetch stream allocated", }, [ POWER7_PME_PM_GRP_MRK_CYC ] = { .pme_name = "PM_GRP_MRK_CYC", .pme_code = 0x10030, .pme_short_desc = "cycles IDU marked instruction before dispatch", .pme_long_desc = "cycles IDU marked instruction before dispatch", }, [ POWER7_PME_PM_MRK_DATA_FROM_RL2L3_SHR_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_RL2L3_SHR_CYC", .pme_code = 0x20028, .pme_short_desc = "Marked ld latency Data Source 1000 (Remote L2.5/L3.5 S)", .pme_long_desc = "Marked load latency Data Source 1000 (Remote L2.5/L3.5 S)", }, [ POWER7_PME_PM_L2_GLOB_GUESS_CORRECT ] = { .pme_name = "PM_L2_GLOB_GUESS_CORRECT", .pme_code = 0x16482, .pme_short_desc = "L2 guess glb and guess was correct (ie data remote)", .pme_long_desc = "L2 guess glb and guess was correct (ie data remote)", }, [ POWER7_PME_PM_LSU_REJECT_LHS ] = { .pme_name = "PM_LSU_REJECT_LHS", .pme_code = 0xc8ac, .pme_short_desc = "Reject: Load Hit Store", .pme_long_desc = "The Load Store Unit rejected a load load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully. Combined Unit 0 + 1", }, [ POWER7_PME_PM_MRK_DATA_FROM_LMEM ] = { .pme_name = "PM_MRK_DATA_FROM_LMEM", .pme_code = 0x3d04a, .pme_short_desc = "Marked data loaded from local memory", .pme_long_desc = "The processor's Data Cache was reloaded due to a marked load from memory attached to the same module this proccessor is located on.", }, [ POWER7_PME_PM_INST_PTEG_FROM_L3 ] = { .pme_name = "PM_INST_PTEG_FROM_L3", .pme_code = 0x2e050, .pme_short_desc = "Instruction PTEG loaded from L3", .pme_long_desc = "Instruction PTEG loaded from L3", }, [ POWER7_PME_PM_FREQ_DOWN ] = { .pme_name = "PM_FREQ_DOWN", .pme_code = 0x3000c, .pme_short_desc = "Frequency is being slewed down due to Power Management", .pme_long_desc = "Processor frequency was slowed down due to power management", }, [ POWER7_PME_PM_PB_RETRY_NODE_PUMP ] = { .pme_name = "PM_PB_RETRY_NODE_PUMP", .pme_code = 0x30081, .pme_short_desc = " Nest events (MC0/MC1/PB/GX), Pair2 Bit0", .pme_long_desc = " Nest events (MC0/MC1/PB/GX), Pair2 Bit0", }, [ POWER7_PME_PM_INST_FROM_RL2L3_SHR ] = { .pme_name = "PM_INST_FROM_RL2L3_SHR", .pme_code = 0x1404c, .pme_short_desc = "Instruction fetched from remote L2 or L3 shared", .pme_long_desc = "An instruction fetch group was fetched with shared (S) data from the L2 or L3 on a remote module. Fetch groups can contain up to 8 instructions", }, [ POWER7_PME_PM_MRK_INST_ISSUED ] = { .pme_name = "PM_MRK_INST_ISSUED", .pme_code = 0x10032, .pme_short_desc = "Marked instruction issued", .pme_long_desc = "A marked instruction was issued to an execution unit.", }, [ POWER7_PME_PM_PTEG_FROM_L3MISS ] = { .pme_name = "PM_PTEG_FROM_L3MISS", .pme_code = 0x2c058, .pme_short_desc = "PTEG loaded from L3 miss", .pme_long_desc = " Page Table Entry was loaded into the ERAT from beyond the L3 due to a demand load or store.", }, [ POWER7_PME_PM_RUN_PURR ] = { .pme_name = "PM_RUN_PURR", .pme_code = 0x400f4, .pme_short_desc = "Run_PURR", .pme_long_desc = "The Processor Utilization of Resources Register was incremented while the run latch was set. The PURR registers will be incremented roughly in the ratio in which the instructions are dispatched from the two threads. ", }, [ POWER7_PME_PM_MRK_GRP_IC_MISS ] = { .pme_name = "PM_MRK_GRP_IC_MISS", .pme_code = 0x40038, .pme_short_desc = "Marked group experienced I cache miss", .pme_long_desc = "A group containing a marked (sampled) instruction experienced an instruction cache miss.", }, [ POWER7_PME_PM_MRK_DATA_FROM_L3 ] = { .pme_name = "PM_MRK_DATA_FROM_L3", .pme_code = 0x1d048, .pme_short_desc = "Marked data loaded from L3", .pme_long_desc = "The processor's Data Cache was reloaded from the local L3 due to a marked load.", }, [ POWER7_PME_PM_CMPLU_STALL_DCACHE_MISS ] = { .pme_name = "PM_CMPLU_STALL_DCACHE_MISS", .pme_code = 0x20016, .pme_short_desc = "Completion stall caused by D cache miss", .pme_long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes suffered a Data Cache Miss. Data Cache Miss has higher priority than any other Load/Store delay, so if an instruction encounters multiple delays only the Data Cache Miss will be reported and the entire delay period will be charged to Data Cache Miss. This is a subset of PM_CMPLU_STALL_LSU.", }, [ POWER7_PME_PM_PTEG_FROM_RL2L3_SHR ] = { .pme_name = "PM_PTEG_FROM_RL2L3_SHR", .pme_code = 0x2c054, .pme_short_desc = "PTEG loaded from remote L2 or L3 shared", .pme_long_desc = "A Page Table Entry was loaded into the ERAT with shared (T or SL) data from an L2 or L3 on a remote module due to a demand load or store.", }, [ POWER7_PME_PM_LSU_FLUSH_LRQ ] = { .pme_name = "PM_LSU_FLUSH_LRQ", .pme_code = 0xc8b8, .pme_short_desc = "Flush: LRQ", .pme_long_desc = "Load Hit Load or Store Hit Load flush. A younger load was flushed because it executed before an older store and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte. Combined Unit 0 + 1.", }, [ POWER7_PME_PM_MRK_DERAT_MISS_64K ] = { .pme_name = "PM_MRK_DERAT_MISS_64K", .pme_code = 0x2d05c, .pme_short_desc = "Marked DERAT misses for 64K page", .pme_long_desc = "A marked data request (load or store) missed the ERAT for 64K page and resulted in an ERAT reload.", }, [ POWER7_PME_PM_INST_PTEG_FROM_DL2L3_MOD ] = { .pme_name = "PM_INST_PTEG_FROM_DL2L3_MOD", .pme_code = 0x4e054, .pme_short_desc = "Instruction PTEG loaded from distant L2 or L3 modified", .pme_long_desc = "Instruction PTEG loaded from distant L2 or L3 modified", }, [ POWER7_PME_PM_L2_ST_MISS ] = { .pme_name = "PM_L2_ST_MISS", .pme_code = 0x26082, .pme_short_desc = "Data Store Miss", .pme_long_desc = "Data Store Miss", }, [ POWER7_PME_PM_LWSYNC ] = { .pme_name = "PM_LWSYNC", .pme_code = 0xd094, .pme_short_desc = "lwsync count (easier to use than IMC)", .pme_long_desc = "lwsync count (easier to use than IMC)", }, [ POWER7_PME_PM_LSU0_DC_PREF_STREAM_CONFIRM_STRIDE ] = { .pme_name = "PM_LSU0_DC_PREF_STREAM_CONFIRM_STRIDE", .pme_code = 0xd0bc, .pme_short_desc = "LS0 Dcache Strided prefetch stream confirmed", .pme_long_desc = "LS0 Dcache Strided prefetch stream confirmed", }, [ POWER7_PME_PM_MRK_PTEG_FROM_L21_SHR ] = { .pme_name = "PM_MRK_PTEG_FROM_L21_SHR", .pme_code = 0x4d056, .pme_short_desc = "Marked PTEG loaded from another L2 on same chip shared", .pme_long_desc = "Marked PTEG loaded from another L2 on same chip shared", }, [ POWER7_PME_PM_MRK_LSU_FLUSH_LRQ ] = { .pme_name = "PM_MRK_LSU_FLUSH_LRQ", .pme_code = 0xd088, .pme_short_desc = "Flush: (marked) LRQ", .pme_long_desc = "Load Hit Load or Store Hit Load flush. A marked load was flushed because it executed before an older store and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.", }, [ POWER7_PME_PM_INST_IMC_MATCH_CMPL ] = { .pme_name = "PM_INST_IMC_MATCH_CMPL", .pme_code = 0x100f0, .pme_short_desc = "IMC Match Count", .pme_long_desc = "Number of instructions resulting from the marked instructions expansion that completed.", }, [ POWER7_PME_PM_NEST_PAIR3_AND ] = { .pme_name = "PM_NEST_PAIR3_AND", .pme_code = 0x40883, .pme_short_desc = " Nest events (MC0/MC1/PB/GX), Pair3 AND", .pme_long_desc = " Nest events (MC0/MC1/PB/GX), Pair3 AND", }, [ POWER7_PME_PM_PB_RETRY_SYS_PUMP ] = { .pme_name = "PM_PB_RETRY_SYS_PUMP", .pme_code = 0x40081, .pme_short_desc = " Nest events (MC0/MC1/PB/GX), Pair3 Bit0", .pme_long_desc = " Nest events (MC0/MC1/PB/GX), Pair3 Bit0", }, [ POWER7_PME_PM_MRK_INST_FIN ] = { .pme_name = "PM_MRK_INST_FIN", .pme_code = 0x30030, .pme_short_desc = "marked instr finish any unit ", .pme_long_desc = "One of the execution units finished a marked instruction. Instructions that finish may not necessary complete", }, [ POWER7_PME_PM_MRK_PTEG_FROM_DL2L3_SHR ] = { .pme_name = "PM_MRK_PTEG_FROM_DL2L3_SHR", .pme_code = 0x3d054, .pme_short_desc = "Marked PTEG loaded from remote L2 or L3 shared", .pme_long_desc = "A Page Table Entry was loaded into the ERAT from memory attached to a different module than this proccessor is located on due to a marked load or store.", }, [ POWER7_PME_PM_INST_FROM_L31_MOD ] = { .pme_name = "PM_INST_FROM_L31_MOD", .pme_code = 0x14044, .pme_short_desc = "Instruction fetched from another L3 on same chip modified", .pme_long_desc = "Instruction fetched from another L3 on same chip modified", }, [ POWER7_PME_PM_MRK_DTLB_MISS_64K ] = { .pme_name = "PM_MRK_DTLB_MISS_64K", .pme_code = 0x3d05e, .pme_short_desc = "Marked Data TLB misses for 64K page", .pme_long_desc = "Data TLB references to 64KB pages by a marked instruction that missed the TLB. Page size is determined at TLB reload time.", }, [ POWER7_PME_PM_LSU_FIN ] = { .pme_name = "PM_LSU_FIN", .pme_code = 0x30066, .pme_short_desc = "LSU Finished an instruction (up to 2 per cycle)", .pme_long_desc = "LSU Finished an instruction (up to 2 per cycle)", }, [ POWER7_PME_PM_MRK_LSU_REJECT ] = { .pme_name = "PM_MRK_LSU_REJECT", .pme_code = 0x40064, .pme_short_desc = "LSU marked reject (up to 2 per cycle)", .pme_long_desc = "LSU marked reject (up to 2 per cycle)", }, [ POWER7_PME_PM_L2_CO_FAIL_BUSY ] = { .pme_name = "PM_L2_CO_FAIL_BUSY", .pme_code = 0x16382, .pme_short_desc = " L2 RC Cast Out dispatch attempt failed due to all CO machines busy", .pme_long_desc = " L2 RC Cast Out dispatch attempt failed due to all CO machines busy", }, [ POWER7_PME_PM_MEM0_WQ_DISP ] = { .pme_name = "PM_MEM0_WQ_DISP", .pme_code = 0x40083, .pme_short_desc = " Nest events (MC0/MC1/PB/GX), Pair3 Bit1", .pme_long_desc = " Nest events (MC0/MC1/PB/GX), Pair3 Bit1", }, [ POWER7_PME_PM_DATA_FROM_L31_MOD ] = { .pme_name = "PM_DATA_FROM_L31_MOD", .pme_code = 0x1c044, .pme_short_desc = "Data loaded from another L3 on same chip modified", .pme_long_desc = "Data loaded from another L3 on same chip modified", }, [ POWER7_PME_PM_THERMAL_WARN ] = { .pme_name = "PM_THERMAL_WARN", .pme_code = 0x10016, .pme_short_desc = "Processor in Thermal Warning", .pme_long_desc = "Processor in Thermal Warning", }, [ POWER7_PME_PM_VSU0_4FLOP ] = { .pme_name = "PM_VSU0_4FLOP", .pme_code = 0xa09c, .pme_short_desc = "four flops operation (scalar fdiv, fsqrt; DP vector version of fmadd, fnmadd, fmsub, fnmsub; SP vector versions of single flop instructions)", .pme_long_desc = "four flops operation (scalar fdiv, fsqrt; DP vector version of fmadd, fnmadd, fmsub, fnmsub; SP vector versions of single flop instructions)", }, [ POWER7_PME_PM_BR_MPRED_CCACHE ] = { .pme_name = "PM_BR_MPRED_CCACHE", .pme_code = 0x40a4, .pme_short_desc = "Branch Mispredict due to Count Cache prediction", .pme_long_desc = "A branch instruction target was incorrectly predicted by the ccount cache. This will result in a branch redirect flush if not overfidden by a flush of an older instruction.", }, [ POWER7_PME_PM_CMPLU_STALL_IFU ] = { .pme_name = "PM_CMPLU_STALL_IFU", .pme_code = 0x4004c, .pme_short_desc = "Completion stall due to IFU ", .pme_long_desc = "Completion stall due to IFU ", }, [ POWER7_PME_PM_L1_DEMAND_WRITE ] = { .pme_name = "PM_L1_DEMAND_WRITE", .pme_code = 0x408c, .pme_short_desc = "Instruction Demand sectors wriittent into IL1", .pme_long_desc = "Instruction Demand sectors wriittent into IL1", }, [ POWER7_PME_PM_FLUSH_BR_MPRED ] = { .pme_name = "PM_FLUSH_BR_MPRED", .pme_code = 0x2084, .pme_short_desc = "Flush caused by branch mispredict", .pme_long_desc = "A flush was caused by a branch mispredict.", }, [ POWER7_PME_PM_MRK_DTLB_MISS_16G ] = { .pme_name = "PM_MRK_DTLB_MISS_16G", .pme_code = 0x1d05e, .pme_short_desc = "Marked Data TLB misses for 16G page", .pme_long_desc = "Data TLB references to 16GB pages by a marked instruction that missed the TLB. Page size is determined at TLB reload time.", }, [ POWER7_PME_PM_MRK_PTEG_FROM_DMEM ] = { .pme_name = "PM_MRK_PTEG_FROM_DMEM", .pme_code = 0x2d052, .pme_short_desc = "Marked PTEG loaded from distant memory", .pme_long_desc = "A Page Table Entry was loaded into the ERAT from memory attached to a different module than this proccessor is located on due to a marked load or store.", }, [ POWER7_PME_PM_L2_RCST_DISP ] = { .pme_name = "PM_L2_RCST_DISP", .pme_code = 0x36280, .pme_short_desc = " L2 RC store dispatch attempt", .pme_long_desc = " L2 RC store dispatch attempt", }, [ POWER7_PME_PM_CMPLU_STALL ] = { .pme_name = "PM_CMPLU_STALL", .pme_code = 0x4000a, .pme_short_desc = "No groups completed, GCT not empty", .pme_long_desc = "No groups completed, GCT not empty", }, [ POWER7_PME_PM_LSU_PARTIAL_CDF ] = { .pme_name = "PM_LSU_PARTIAL_CDF", .pme_code = 0xc0aa, .pme_short_desc = "A partial cacheline was returned from the L3", .pme_long_desc = "A partial cacheline was returned from the L3", }, [ POWER7_PME_PM_DISP_CLB_HELD_SB ] = { .pme_name = "PM_DISP_CLB_HELD_SB", .pme_code = 0x20a8, .pme_short_desc = "Dispatch/CLB Hold: Scoreboard", .pme_long_desc = "Dispatch/CLB Hold: Scoreboard", }, [ POWER7_PME_PM_VSU0_FMA_DOUBLE ] = { .pme_name = "PM_VSU0_FMA_DOUBLE", .pme_code = 0xa090, .pme_short_desc = "four flop DP vector operations (xvmadddp, xvnmadddp, xvmsubdp, xvmsubdp)", .pme_long_desc = "four flop DP vector operations (xvmadddp, xvnmadddp, xvmsubdp, xvmsubdp)", }, [ POWER7_PME_PM_FXU0_BUSY_FXU1_IDLE ] = { .pme_name = "PM_FXU0_BUSY_FXU1_IDLE", .pme_code = 0x3000e, .pme_short_desc = "fxu0 busy and fxu1 idle", .pme_long_desc = "FXU0 is busy while FXU1 was idle", }, [ POWER7_PME_PM_IC_DEMAND_CYC ] = { .pme_name = "PM_IC_DEMAND_CYC", .pme_code = 0x10018, .pme_short_desc = "Cycles when a demand ifetch was pending", .pme_long_desc = "Cycles when a demand ifetch was pending", }, [ POWER7_PME_PM_MRK_DATA_FROM_L21_SHR ] = { .pme_name = "PM_MRK_DATA_FROM_L21_SHR", .pme_code = 0x3d04e, .pme_short_desc = "Marked data loaded from another L2 on same chip shared", .pme_long_desc = "Marked data loaded from another L2 on same chip shared", }, [ POWER7_PME_PM_MRK_LSU_FLUSH_UST ] = { .pme_name = "PM_MRK_LSU_FLUSH_UST", .pme_code = 0xd086, .pme_short_desc = "Flush: (marked) Unaligned Store", .pme_long_desc = "A marked store was flushed because it was unaligned", }, [ POWER7_PME_PM_INST_PTEG_FROM_L3MISS ] = { .pme_name = "PM_INST_PTEG_FROM_L3MISS", .pme_code = 0x2e058, .pme_short_desc = "Instruction PTEG loaded from L3 miss", .pme_long_desc = "Instruction PTEG loaded from L3 miss", }, [ POWER7_PME_PM_VSU_DENORM ] = { .pme_name = "PM_VSU_DENORM", .pme_code = 0xa8ac, .pme_short_desc = "Vector or Scalar denorm operand", .pme_long_desc = "Vector or Scalar denorm operand", }, [ POWER7_PME_PM_MRK_LSU_PARTIAL_CDF ] = { .pme_name = "PM_MRK_LSU_PARTIAL_CDF", .pme_code = 0xd080, .pme_short_desc = "A partial cacheline was returned from the L3 for a marked load", .pme_long_desc = "A partial cacheline was returned from the L3 for a marked load", }, [ POWER7_PME_PM_INST_FROM_L21_SHR ] = { .pme_name = "PM_INST_FROM_L21_SHR", .pme_code = 0x3404e, .pme_short_desc = "Instruction fetched from another L2 on same chip shared", .pme_long_desc = "Instruction fetched from another L2 on same chip shared", }, [ POWER7_PME_PM_IC_PREF_WRITE ] = { .pme_name = "PM_IC_PREF_WRITE", .pme_code = 0x408e, .pme_short_desc = "Instruction prefetch written into IL1", .pme_long_desc = "Number of Instruction Cache entries written because of prefetch. Prefetch entries are marked least recently used and are candidates for eviction if they are not needed to satify a demand fetch.", }, [ POWER7_PME_PM_BR_PRED ] = { .pme_name = "PM_BR_PRED", .pme_code = 0x409c, .pme_short_desc = "Branch Predictions made", .pme_long_desc = "A branch prediction was made. This could have been a target prediction, a condition prediction, or both", }, [ POWER7_PME_PM_INST_FROM_DMEM ] = { .pme_name = "PM_INST_FROM_DMEM", .pme_code = 0x1404a, .pme_short_desc = "Instruction fetched from distant memory", .pme_long_desc = "An instruction fetch group was fetched from memory attached to a distant module. Fetch groups can contain up to 8 instructions", }, [ POWER7_PME_PM_IC_PREF_CANCEL_ALL ] = { .pme_name = "PM_IC_PREF_CANCEL_ALL", .pme_code = 0x4890, .pme_short_desc = "Prefetch Canceled due to page boundary or icache hit", .pme_long_desc = "Prefetch Canceled due to page boundary or icache hit", }, [ POWER7_PME_PM_LSU_DC_PREF_STREAM_CONFIRM ] = { .pme_name = "PM_LSU_DC_PREF_STREAM_CONFIRM", .pme_code = 0xd8b4, .pme_short_desc = "Dcache new prefetch stream confirmed", .pme_long_desc = "Dcache new prefetch stream confirmed", }, [ POWER7_PME_PM_MRK_LSU_FLUSH_SRQ ] = { .pme_name = "PM_MRK_LSU_FLUSH_SRQ", .pme_code = 0xd08a, .pme_short_desc = "Flush: (marked) SRQ", .pme_long_desc = "Load Hit Store flush. A marked load was flushed because it hits (overlaps) an older store that is already in the SRQ or in the same group. If the real addresses match but the effective addresses do not, an alias condition exists that prevents store forwarding. If the load and store are in the same group the load must be flushed to separate the two instructions. ", }, [ POWER7_PME_PM_MRK_FIN_STALL_CYC ] = { .pme_name = "PM_MRK_FIN_STALL_CYC", .pme_code = 0x1003c, .pme_short_desc = "Marked instruction Finish Stall cycles (marked finish after NTC) ", .pme_long_desc = "Marked instruction Finish Stall cycles (marked finish after NTC) ", }, [ POWER7_PME_PM_L2_RCST_DISP_FAIL_OTHER ] = { .pme_name = "PM_L2_RCST_DISP_FAIL_OTHER", .pme_code = 0x46280, .pme_short_desc = " L2 RC store dispatch attempt failed due to other reasons", .pme_long_desc = " L2 RC store dispatch attempt failed due to other reasons", }, [ POWER7_PME_PM_VSU1_DD_ISSUED ] = { .pme_name = "PM_VSU1_DD_ISSUED", .pme_code = 0xb098, .pme_short_desc = "64BIT Decimal Issued on Pipe1", .pme_long_desc = "64BIT Decimal Issued on Pipe1", }, [ POWER7_PME_PM_PTEG_FROM_L31_SHR ] = { .pme_name = "PM_PTEG_FROM_L31_SHR", .pme_code = 0x2c056, .pme_short_desc = "PTEG loaded from another L3 on same chip shared", .pme_long_desc = "PTEG loaded from another L3 on same chip shared", }, [ POWER7_PME_PM_DATA_FROM_L21_SHR ] = { .pme_name = "PM_DATA_FROM_L21_SHR", .pme_code = 0x3c04e, .pme_short_desc = "Data loaded from another L2 on same chip shared", .pme_long_desc = "Data loaded from another L2 on same chip shared", }, [ POWER7_PME_PM_LSU0_NCLD ] = { .pme_name = "PM_LSU0_NCLD", .pme_code = 0xc08c, .pme_short_desc = "LS0 Non-cachable Loads counted at finish", .pme_long_desc = "A non-cacheable load was executed by unit 0.", }, [ POWER7_PME_PM_VSU1_4FLOP ] = { .pme_name = "PM_VSU1_4FLOP", .pme_code = 0xa09e, .pme_short_desc = "four flops operation (scalar fdiv, fsqrt; DP vector version of fmadd, fnmadd, fmsub, fnmsub; SP vector versions of single flop instructions)", .pme_long_desc = "four flops operation (scalar fdiv, fsqrt; DP vector version of fmadd, fnmadd, fmsub, fnmsub; SP vector versions of single flop instructions)", }, [ POWER7_PME_PM_VSU1_8FLOP ] = { .pme_name = "PM_VSU1_8FLOP", .pme_code = 0xa0a2, .pme_short_desc = "eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) ", .pme_long_desc = "eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) ", }, [ POWER7_PME_PM_VSU_8FLOP ] = { .pme_name = "PM_VSU_8FLOP", .pme_code = 0xa8a0, .pme_short_desc = "eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) ", .pme_long_desc = "eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) ", }, [ POWER7_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC ] = { .pme_name = "PM_LSU_LMQ_SRQ_EMPTY_CYC", .pme_code = 0x2003e, .pme_short_desc = "LSU empty (lmq and srq empty)", .pme_long_desc = "Cycles when both the LMQ and SRQ are empty (LSU is idle)", }, [ POWER7_PME_PM_DTLB_MISS_64K ] = { .pme_name = "PM_DTLB_MISS_64K", .pme_code = 0x3c05e, .pme_short_desc = "Data TLB miss for 64K page", .pme_long_desc = "Data TLB references to 64KB pages that missed the TLB. Page size is determined at TLB reload time.", }, [ POWER7_PME_PM_THRD_CONC_RUN_INST ] = { .pme_name = "PM_THRD_CONC_RUN_INST", .pme_code = 0x300f4, .pme_short_desc = "Concurrent Run Instructions", .pme_long_desc = "Instructions completed by this thread when both threads had their run latches set.", }, [ POWER7_PME_PM_MRK_PTEG_FROM_L2 ] = { .pme_name = "PM_MRK_PTEG_FROM_L2", .pme_code = 0x1d050, .pme_short_desc = "Marked PTEG loaded from L2", .pme_long_desc = "A Page Table Entry was loaded into the ERAT from the local L2 due to a marked load or store.", }, [ POWER7_PME_PM_PB_SYS_PUMP ] = { .pme_name = "PM_PB_SYS_PUMP", .pme_code = 0x20081, .pme_short_desc = " Nest events (MC0/MC1/PB/GX), Pair1 Bit0", .pme_long_desc = " Nest events (MC0/MC1/PB/GX), Pair1 Bit0", }, [ POWER7_PME_PM_VSU_FIN ] = { .pme_name = "PM_VSU_FIN", .pme_code = 0xa8bc, .pme_short_desc = "VSU0 Finished an instruction", .pme_long_desc = "VSU0 Finished an instruction", }, [ POWER7_PME_PM_MRK_DATA_FROM_L31_MOD ] = { .pme_name = "PM_MRK_DATA_FROM_L31_MOD", .pme_code = 0x1d044, .pme_short_desc = "Marked data loaded from another L3 on same chip modified", .pme_long_desc = "Marked data loaded from another L3 on same chip modified", }, [ POWER7_PME_PM_THRD_PRIO_0_1_CYC ] = { .pme_name = "PM_THRD_PRIO_0_1_CYC", .pme_code = 0x40b0, .pme_short_desc = " Cycles thread running at priority level 0 or 1", .pme_long_desc = " Cycles thread running at priority level 0 or 1", }, [ POWER7_PME_PM_DERAT_MISS_64K ] = { .pme_name = "PM_DERAT_MISS_64K", .pme_code = 0x2c05c, .pme_short_desc = "DERAT misses for 64K page", .pme_long_desc = "A data request (load or store) missed the ERAT for 64K page and resulted in an ERAT reload.", }, [ POWER7_PME_PM_PMC2_REWIND ] = { .pme_name = "PM_PMC2_REWIND", .pme_code = 0x30020, .pme_short_desc = "PMC2 Rewind Event (did not match condition)", .pme_long_desc = "PMC2 was counting speculatively. The speculative condition was not met and the counter was restored to its previous value.", }, [ POWER7_PME_PM_INST_FROM_L2 ] = { .pme_name = "PM_INST_FROM_L2", .pme_code = 0x14040, .pme_short_desc = "Instruction fetched from L2", .pme_long_desc = "An instruction fetch group was fetched from L2. Fetch Groups can contain up to 8 instructions", }, [ POWER7_PME_PM_GRP_BR_MPRED_NONSPEC ] = { .pme_name = "PM_GRP_BR_MPRED_NONSPEC", .pme_code = 0x1000a, .pme_short_desc = "Group experienced non-speculative branch redirect", .pme_long_desc = "Group experienced non-speculative branch redirect", }, [ POWER7_PME_PM_INST_DISP ] = { .pme_name = "PM_INST_DISP", .pme_code = 0x200f2, .pme_short_desc = "# PPC Dispatched", .pme_long_desc = "Number of PowerPC instructions successfully dispatched.", }, [ POWER7_PME_PM_MEM0_RD_CANCEL_TOTAL ] = { .pme_name = "PM_MEM0_RD_CANCEL_TOTAL", .pme_code = 0x30083, .pme_short_desc = " Nest events (MC0/MC1/PB/GX), Pair2 Bit1", .pme_long_desc = " Nest events (MC0/MC1/PB/GX), Pair2 Bit1", }, [ POWER7_PME_PM_LSU0_DC_PREF_STREAM_CONFIRM ] = { .pme_name = "PM_LSU0_DC_PREF_STREAM_CONFIRM", .pme_code = 0xd0b4, .pme_short_desc = "LS0 Dcache prefetch stream confirmed", .pme_long_desc = "LS0 Dcache prefetch stream confirmed", }, [ POWER7_PME_PM_L1_DCACHE_RELOAD_VALID ] = { .pme_name = "PM_L1_DCACHE_RELOAD_VALID", .pme_code = 0x300f6, .pme_short_desc = "L1 reload data source valid", .pme_long_desc = "The data source information is valid,the data cache has been reloaded. Prior to POWER5+ this included data cache reloads due to prefetch activity. With POWER5+ this now only includes reloads due to demand loads.", }, [ POWER7_PME_PM_VSU_SCALAR_DOUBLE_ISSUED ] = { .pme_name = "PM_VSU_SCALAR_DOUBLE_ISSUED", .pme_code = 0xb888, .pme_short_desc = "Double Precision scalar instruction issued on Pipe0", .pme_long_desc = "Double Precision scalar instruction issued on Pipe0", }, [ POWER7_PME_PM_L3_PREF_HIT ] = { .pme_name = "PM_L3_PREF_HIT", .pme_code = 0x3f080, .pme_short_desc = "L3 Prefetch Directory Hit", .pme_long_desc = "L3 Prefetch Directory Hit", }, [ POWER7_PME_PM_MRK_PTEG_FROM_L31_MOD ] = { .pme_name = "PM_MRK_PTEG_FROM_L31_MOD", .pme_code = 0x1d054, .pme_short_desc = "Marked PTEG loaded from another L3 on same chip modified", .pme_long_desc = "Marked PTEG loaded from another L3 on same chip modified", }, [ POWER7_PME_PM_CMPLU_STALL_STORE ] = { .pme_name = "PM_CMPLU_STALL_STORE", .pme_code = 0x2004a, .pme_short_desc = "Completion stall due to store instruction", .pme_long_desc = "Completion stall due to store instruction", }, [ POWER7_PME_PM_MRK_FXU_FIN ] = { .pme_name = "PM_MRK_FXU_FIN", .pme_code = 0x20038, .pme_short_desc = "fxu marked instr finish", .pme_long_desc = "One of the Fixed Point Units finished a marked instruction. Instructions that finish may not necessary complete.", }, [ POWER7_PME_PM_PMC4_OVERFLOW ] = { .pme_name = "PM_PMC4_OVERFLOW", .pme_code = 0x10010, .pme_short_desc = "Overflow from counter 4", .pme_long_desc = "Overflows from PMC4 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.", }, [ POWER7_PME_PM_MRK_PTEG_FROM_L3 ] = { .pme_name = "PM_MRK_PTEG_FROM_L3", .pme_code = 0x2d050, .pme_short_desc = "Marked PTEG loaded from L3", .pme_long_desc = "A Page Table Entry was loaded into the ERAT from the local L3 due to a marked load or store.", }, [ POWER7_PME_PM_LSU0_LMQ_LHR_MERGE ] = { .pme_name = "PM_LSU0_LMQ_LHR_MERGE", .pme_code = 0xd098, .pme_short_desc = "LS0 Load Merged with another cacheline request", .pme_long_desc = "LS0 Load Merged with another cacheline request", }, [ POWER7_PME_PM_BTAC_HIT ] = { .pme_name = "PM_BTAC_HIT", .pme_code = 0x508a, .pme_short_desc = "BTAC Correct Prediction", .pme_long_desc = "BTAC Correct Prediction", }, [ POWER7_PME_PM_L3_RD_BUSY ] = { .pme_name = "PM_L3_RD_BUSY", .pme_code = 0x4f082, .pme_short_desc = "Rd machines busy >= threshold (2,4,6,8)", .pme_long_desc = "Rd machines busy >= threshold (2,4,6,8)", }, [ POWER7_PME_PM_LSU0_L1_SW_PREF ] = { .pme_name = "PM_LSU0_L1_SW_PREF", .pme_code = 0xc09c, .pme_short_desc = "LSU0 Software L1 Prefetches, including SW Transient Prefetches", .pme_long_desc = "LSU0 Software L1 Prefetches, including SW Transient Prefetches", }, [ POWER7_PME_PM_INST_FROM_L2MISS ] = { .pme_name = "PM_INST_FROM_L2MISS", .pme_code = 0x44048, .pme_short_desc = "Instruction fetched missed L2", .pme_long_desc = "An instruction fetch group was fetched from beyond the local L2.", }, [ POWER7_PME_PM_LSU0_DC_PREF_STREAM_ALLOC ] = { .pme_name = "PM_LSU0_DC_PREF_STREAM_ALLOC", .pme_code = 0xd0a8, .pme_short_desc = "LS0 D cache new prefetch stream allocated", .pme_long_desc = "LS0 D cache new prefetch stream allocated", }, [ POWER7_PME_PM_L2_ST ] = { .pme_name = "PM_L2_ST", .pme_code = 0x16082, .pme_short_desc = "Data Store Count", .pme_long_desc = "Data Store Count", }, [ POWER7_PME_PM_VSU0_DENORM ] = { .pme_name = "PM_VSU0_DENORM", .pme_code = 0xa0ac, .pme_short_desc = "FPU denorm operand", .pme_long_desc = "VSU0 received denormalized data", }, [ POWER7_PME_PM_MRK_DATA_FROM_DL2L3_SHR ] = { .pme_name = "PM_MRK_DATA_FROM_DL2L3_SHR", .pme_code = 0x3d044, .pme_short_desc = "Marked data loaded from distant L2 or L3 shared", .pme_long_desc = "The processor's Data Cache was reloaded with shared (T or SL) data from an L2 or L3 on a distant module due to a marked load.", }, [ POWER7_PME_PM_BR_PRED_CR_TA ] = { .pme_name = "PM_BR_PRED_CR_TA", .pme_code = 0x48aa, .pme_short_desc = "Branch predict - taken/not taken and target", .pme_long_desc = "Both the condition (taken or not taken) and the target address of a branch instruction was predicted.", }, [ POWER7_PME_PM_VSU0_FCONV ] = { .pme_name = "PM_VSU0_FCONV", .pme_code = 0xa0b0, .pme_short_desc = "Convert instruction executed", .pme_long_desc = "Convert instruction executed", }, [ POWER7_PME_PM_MRK_LSU_FLUSH_ULD ] = { .pme_name = "PM_MRK_LSU_FLUSH_ULD", .pme_code = 0xd084, .pme_short_desc = "Flush: (marked) Unaligned Load", .pme_long_desc = "A marked load was flushed because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)", }, [ POWER7_PME_PM_BTAC_MISS ] = { .pme_name = "PM_BTAC_MISS", .pme_code = 0x5088, .pme_short_desc = "BTAC Mispredicted", .pme_long_desc = "BTAC Mispredicted", }, [ POWER7_PME_PM_MRK_LD_MISS_EXPOSED_CYC_COUNT ] = { .pme_name = "PM_MRK_LD_MISS_EXPOSED_CYC_COUNT", .pme_code = 0x1003f, .pme_short_desc = "Marked Load exposed Miss (use edge detect to count #)", .pme_long_desc = "Marked Load exposed Miss (use edge detect to count #)", }, [ POWER7_PME_PM_MRK_DATA_FROM_L2 ] = { .pme_name = "PM_MRK_DATA_FROM_L2", .pme_code = 0x1d040, .pme_short_desc = "Marked data loaded from L2", .pme_long_desc = "The processor's Data Cache was reloaded from the local L2 due to a marked load.", }, [ POWER7_PME_PM_LSU_DCACHE_RELOAD_VALID ] = { .pme_name = "PM_LSU_DCACHE_RELOAD_VALID", .pme_code = 0xd0a2, .pme_short_desc = "count per sector of lines reloaded in L1 (demand + prefetch) ", .pme_long_desc = "count per sector of lines reloaded in L1 (demand + prefetch) ", }, [ POWER7_PME_PM_VSU_FMA ] = { .pme_name = "PM_VSU_FMA", .pme_code = 0xa884, .pme_short_desc = "two flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only!", .pme_long_desc = "two flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only!", }, [ POWER7_PME_PM_LSU0_FLUSH_SRQ ] = { .pme_name = "PM_LSU0_FLUSH_SRQ", .pme_code = 0xc0bc, .pme_short_desc = "LS0 Flush: SRQ", .pme_long_desc = "Load Hit Store flush. A younger load was flushed from unit 0 because it hits (overlaps) an older store that is already in the SRQ or in the same group. If the real addresses match but the effective addresses do not, an alias condition exists that prevents store forwarding. If the load and store are in the same group the load must be flushed to separate the two instructions. ", }, [ POWER7_PME_PM_LSU1_L1_PREF ] = { .pme_name = "PM_LSU1_L1_PREF", .pme_code = 0xd0ba, .pme_short_desc = " LS1 L1 cache data prefetches", .pme_long_desc = " LS1 L1 cache data prefetches", }, [ POWER7_PME_PM_IOPS_CMPL ] = { .pme_name = "PM_IOPS_CMPL", .pme_code = 0x10014, .pme_short_desc = "Internal Operations completed", .pme_long_desc = "Number of internal operations that completed.", }, [ POWER7_PME_PM_L2_SYS_PUMP ] = { .pme_name = "PM_L2_SYS_PUMP", .pme_code = 0x36482, .pme_short_desc = "RC req that was a global (aka system) pump attempt", .pme_long_desc = "RC req that was a global (aka system) pump attempt", }, [ POWER7_PME_PM_L2_RCLD_BUSY_RC_FULL ] = { .pme_name = "PM_L2_RCLD_BUSY_RC_FULL", .pme_code = 0x46282, .pme_short_desc = " L2 activated Busy to the core for loads due to all RC full", .pme_long_desc = " L2 activated Busy to the core for loads due to all RC full", }, [ POWER7_PME_PM_LSU_LMQ_S0_ALLOC ] = { .pme_name = "PM_LSU_LMQ_S0_ALLOC", .pme_code = 0xd0a1, .pme_short_desc = "Slot 0 of LMQ valid", .pme_long_desc = "Slot 0 of LMQ valid", }, [ POWER7_PME_PM_FLUSH_DISP_SYNC ] = { .pme_name = "PM_FLUSH_DISP_SYNC", .pme_code = 0x2088, .pme_short_desc = "Dispatch Flush: Sync", .pme_long_desc = "Dispatch Flush: Sync", }, [ POWER7_PME_PM_MRK_DATA_FROM_DL2L3_MOD_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_DL2L3_MOD_CYC", .pme_code = 0x4002a, .pme_short_desc = "Marked ld latency Data source 1011 (L2.75/L3.75 M different 4 chip node)", .pme_long_desc = "Marked ld latency Data source 1011 (L2.75/L3.75 M different 4 chip node)", }, [ POWER7_PME_PM_L2_IC_INV ] = { .pme_name = "PM_L2_IC_INV", .pme_code = 0x26180, .pme_short_desc = "Icache Invalidates from L2 ", .pme_long_desc = "Icache Invalidates from L2 ", }, [ POWER7_PME_PM_MRK_DATA_FROM_L21_MOD_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L21_MOD_CYC", .pme_code = 0x40024, .pme_short_desc = "Marked ld latency Data source 0101 (L2.1 M same chip)", .pme_long_desc = "Marked ld latency Data source 0101 (L2.1 M same chip)", }, [ POWER7_PME_PM_L3_PREF_LDST ] = { .pme_name = "PM_L3_PREF_LDST", .pme_code = 0xd8ac, .pme_short_desc = "L3 cache prefetches LD + ST", .pme_long_desc = "L3 cache prefetches LD + ST", }, [ POWER7_PME_PM_LSU_SRQ_EMPTY_CYC ] = { .pme_name = "PM_LSU_SRQ_EMPTY_CYC", .pme_code = 0x40008, .pme_short_desc = "ALL threads srq empty", .pme_long_desc = "The Store Request Queue is empty", }, [ POWER7_PME_PM_LSU_LMQ_S0_VALID ] = { .pme_name = "PM_LSU_LMQ_S0_VALID", .pme_code = 0xd0a0, .pme_short_desc = "Slot 0 of LMQ valid", .pme_long_desc = "This signal is asserted every cycle that the Load Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin. In SMT mode the LRQ is split between the two threads (16 entries each).", }, [ POWER7_PME_PM_FLUSH_PARTIAL ] = { .pme_name = "PM_FLUSH_PARTIAL", .pme_code = 0x2086, .pme_short_desc = "Partial flush", .pme_long_desc = "Partial flush", }, [ POWER7_PME_PM_VSU1_FMA_DOUBLE ] = { .pme_name = "PM_VSU1_FMA_DOUBLE", .pme_code = 0xa092, .pme_short_desc = "four flop DP vector operations (xvmadddp, xvnmadddp, xvmsubdp, xvmsubdp)", .pme_long_desc = "four flop DP vector operations (xvmadddp, xvnmadddp, xvmsubdp, xvmsubdp)", }, [ POWER7_PME_PM_1PLUS_PPC_DISP ] = { .pme_name = "PM_1PLUS_PPC_DISP", .pme_code = 0x400f2, .pme_short_desc = "Cycles at least one Instr Dispatched", .pme_long_desc = "A group containing at least one PPC instruction was dispatched. For microcoded instructions that span multiple groups, this will only occur once.", }, [ POWER7_PME_PM_DATA_FROM_L2MISS ] = { .pme_name = "PM_DATA_FROM_L2MISS", .pme_code = 0x200fe, .pme_short_desc = "Demand LD - L2 Miss (not L2 hit)", .pme_long_desc = "The processor's Data Cache was reloaded but not from the local L2.", }, [ POWER7_PME_PM_SUSPENDED ] = { .pme_name = "PM_SUSPENDED", .pme_code = 0x0, .pme_short_desc = "Counter OFF", .pme_long_desc = "The counter is suspended (does not count)", }, [ POWER7_PME_PM_VSU0_FMA ] = { .pme_name = "PM_VSU0_FMA", .pme_code = 0xa084, .pme_short_desc = "two flops operation (fmadd, fnmadd, fmsub, fnmsub, xsmadd, xsnmadd, xsmsub, xsnmsub) Scalar instructions only!", .pme_long_desc = "two flops operation (fmadd, fnmadd, fmsub, fnmsub, xsmadd, xsnmadd, xsmsub, xsnmsub) Scalar instructions only!", }, [ POWER7_PME_PM_CMPLU_STALL_SCALAR ] = { .pme_name = "PM_CMPLU_STALL_SCALAR", .pme_code = 0x40012, .pme_short_desc = "Completion stall caused by FPU instruction", .pme_long_desc = "Completion stall caused by FPU instruction", }, [ POWER7_PME_PM_STCX_FAIL ] = { .pme_name = "PM_STCX_FAIL", .pme_code = 0xc09a, .pme_short_desc = "STCX failed", .pme_long_desc = "A stcx (stwcx or stdcx) failed", }, [ POWER7_PME_PM_VSU0_FSQRT_FDIV_DOUBLE ] = { .pme_name = "PM_VSU0_FSQRT_FDIV_DOUBLE", .pme_code = 0xa094, .pme_short_desc = "eight flop DP vector operations (xvfdivdp, xvsqrtdp ", .pme_long_desc = "eight flop DP vector operations (xvfdivdp, xvsqrtdp ", }, [ POWER7_PME_PM_DC_PREF_DST ] = { .pme_name = "PM_DC_PREF_DST", .pme_code = 0xd0b0, .pme_short_desc = "Data Stream Touch", .pme_long_desc = "A prefetch stream was started using the DST instruction.", }, [ POWER7_PME_PM_VSU1_SCAL_SINGLE_ISSUED ] = { .pme_name = "PM_VSU1_SCAL_SINGLE_ISSUED", .pme_code = 0xb086, .pme_short_desc = "Single Precision scalar instruction issued on Pipe1", .pme_long_desc = "Single Precision scalar instruction issued on Pipe1", }, [ POWER7_PME_PM_L3_HIT ] = { .pme_name = "PM_L3_HIT", .pme_code = 0x1f080, .pme_short_desc = "L3 Hits", .pme_long_desc = "L3 Hits", }, [ POWER7_PME_PM_L2_GLOB_GUESS_WRONG ] = { .pme_name = "PM_L2_GLOB_GUESS_WRONG", .pme_code = 0x26482, .pme_short_desc = "L2 guess glb and guess was not correct (ie data local)", .pme_long_desc = "L2 guess glb and guess was not correct (ie data local)", }, [ POWER7_PME_PM_MRK_DFU_FIN ] = { .pme_name = "PM_MRK_DFU_FIN", .pme_code = 0x20032, .pme_short_desc = "Decimal Unit marked Instruction Finish", .pme_long_desc = "The Decimal Floating Point Unit finished a marked instruction.", }, [ POWER7_PME_PM_INST_FROM_L1 ] = { .pme_name = "PM_INST_FROM_L1", .pme_code = 0x4080, .pme_short_desc = "Instruction fetches from L1", .pme_long_desc = "An instruction fetch group was fetched from L1. Fetch Groups can contain up to 8 instructions", }, [ POWER7_PME_PM_BRU_FIN ] = { .pme_name = "PM_BRU_FIN", .pme_code = 0x10068, .pme_short_desc = "Branch Instruction Finished ", .pme_long_desc = "The Branch execution unit finished an instruction", }, [ POWER7_PME_PM_IC_DEMAND_REQ ] = { .pme_name = "PM_IC_DEMAND_REQ", .pme_code = 0x4088, .pme_short_desc = "Demand Instruction fetch request", .pme_long_desc = "Demand Instruction fetch request", }, [ POWER7_PME_PM_VSU1_FSQRT_FDIV_DOUBLE ] = { .pme_name = "PM_VSU1_FSQRT_FDIV_DOUBLE", .pme_code = 0xa096, .pme_short_desc = "eight flop DP vector operations (xvfdivdp, xvsqrtdp ", .pme_long_desc = "eight flop DP vector operations (xvfdivdp, xvsqrtdp ", }, [ POWER7_PME_PM_VSU1_FMA ] = { .pme_name = "PM_VSU1_FMA", .pme_code = 0xa086, .pme_short_desc = "two flops operation (fmadd, fnmadd, fmsub, fnmsub, xsmadd, xsnmadd, xsmsub, xsnmsub) Scalar instructions only!", .pme_long_desc = "two flops operation (fmadd, fnmadd, fmsub, fnmsub, xsmadd, xsnmadd, xsmsub, xsnmsub) Scalar instructions only!", }, [ POWER7_PME_PM_MRK_LD_MISS_L1 ] = { .pme_name = "PM_MRK_LD_MISS_L1", .pme_code = 0x20036, .pme_short_desc = "Marked DL1 Demand Miss", .pme_long_desc = "Marked L1 D cache load misses", }, [ POWER7_PME_PM_VSU0_2FLOP_DOUBLE ] = { .pme_name = "PM_VSU0_2FLOP_DOUBLE", .pme_code = 0xa08c, .pme_short_desc = "two flop DP vector operation (xvadddp, xvmuldp, xvsubdp, xvcmpdp, xvseldp, xvabsdp, xvnabsdp, xvredp ,xvsqrtedp, vxnegdp) ", .pme_long_desc = "two flop DP vector operation (xvadddp, xvmuldp, xvsubdp, xvcmpdp, xvseldp, xvabsdp, xvnabsdp, xvredp ,xvsqrtedp, vxnegdp) ", }, [ POWER7_PME_PM_LSU_DC_PREF_STRIDED_STREAM_CONFIRM ] = { .pme_name = "PM_LSU_DC_PREF_STRIDED_STREAM_CONFIRM", .pme_code = 0xd8bc, .pme_short_desc = "Dcache Strided prefetch stream confirmed (software + hardware)", .pme_long_desc = "Dcache Strided prefetch stream confirmed (software + hardware)", }, [ POWER7_PME_PM_INST_PTEG_FROM_L31_SHR ] = { .pme_name = "PM_INST_PTEG_FROM_L31_SHR", .pme_code = 0x2e056, .pme_short_desc = "Instruction PTEG loaded from another L3 on same chip shared", .pme_long_desc = "Instruction PTEG loaded from another L3 on same chip shared", }, [ POWER7_PME_PM_MRK_LSU_REJECT_ERAT_MISS ] = { .pme_name = "PM_MRK_LSU_REJECT_ERAT_MISS", .pme_code = 0x30064, .pme_short_desc = "LSU marked reject due to ERAT (up to 2 per cycle)", .pme_long_desc = "LSU marked reject due to ERAT (up to 2 per cycle)", }, [ POWER7_PME_PM_MRK_DATA_FROM_L2MISS ] = { .pme_name = "PM_MRK_DATA_FROM_L2MISS", .pme_code = 0x4d048, .pme_short_desc = "Marked data loaded missed L2", .pme_long_desc = "DL1 was reloaded from beyond L2 due to a marked demand load.", }, [ POWER7_PME_PM_DATA_FROM_RL2L3_SHR ] = { .pme_name = "PM_DATA_FROM_RL2L3_SHR", .pme_code = 0x1c04c, .pme_short_desc = "Data loaded from remote L2 or L3 shared", .pme_long_desc = "The processor's Data Cache was reloaded with shared (T or SL) data from an L2 or L3 on a remote module due to a demand load", }, [ POWER7_PME_PM_INST_FROM_PREF ] = { .pme_name = "PM_INST_FROM_PREF", .pme_code = 0x14046, .pme_short_desc = "Instruction fetched from prefetch", .pme_long_desc = "An instruction fetch group was fetched from the prefetch buffer. Fetch groups can contain up to 8 instructions", }, [ POWER7_PME_PM_VSU1_SQ ] = { .pme_name = "PM_VSU1_SQ", .pme_code = 0xb09e, .pme_short_desc = "Store Vector Issued on Pipe1", .pme_long_desc = "Store Vector Issued on Pipe1", }, [ POWER7_PME_PM_L2_LD_DISP ] = { .pme_name = "PM_L2_LD_DISP", .pme_code = 0x36180, .pme_short_desc = "All successful load dispatches", .pme_long_desc = "All successful load dispatches", }, [ POWER7_PME_PM_L2_DISP_ALL ] = { .pme_name = "PM_L2_DISP_ALL", .pme_code = 0x46080, .pme_short_desc = "All successful LD/ST dispatches for this thread(i+d)", .pme_long_desc = "All successful LD/ST dispatches for this thread(i+d)", }, [ POWER7_PME_PM_THRD_GRP_CMPL_BOTH_CYC ] = { .pme_name = "PM_THRD_GRP_CMPL_BOTH_CYC", .pme_code = 0x10012, .pme_short_desc = "Cycles group completed by both threads", .pme_long_desc = "Cycles that both threads completed.", }, [ POWER7_PME_PM_VSU_FSQRT_FDIV_DOUBLE ] = { .pme_name = "PM_VSU_FSQRT_FDIV_DOUBLE", .pme_code = 0xa894, .pme_short_desc = "DP vector versions of fdiv,fsqrt ", .pme_long_desc = "DP vector versions of fdiv,fsqrt ", }, [ POWER7_PME_PM_BR_MPRED ] = { .pme_name = "PM_BR_MPRED", .pme_code = 0x400f6, .pme_short_desc = "Number of Branch Mispredicts", .pme_long_desc = "A branch instruction was incorrectly predicted. This could have been a target prediction, a condition prediction, or both", }, [ POWER7_PME_PM_INST_PTEG_FROM_DL2L3_SHR ] = { .pme_name = "PM_INST_PTEG_FROM_DL2L3_SHR", .pme_code = 0x3e054, .pme_short_desc = "Instruction PTEG loaded from remote L2 or L3 shared", .pme_long_desc = "Instruction PTEG loaded from remote L2 or L3 shared", }, [ POWER7_PME_PM_VSU_1FLOP ] = { .pme_name = "PM_VSU_1FLOP", .pme_code = 0xa880, .pme_short_desc = "one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finished", .pme_long_desc = "one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finished", }, [ POWER7_PME_PM_HV_CYC ] = { .pme_name = "PM_HV_CYC", .pme_code = 0x2000a, .pme_short_desc = "cycles in hypervisor mode ", .pme_long_desc = "Cycles when the processor is executing in Hypervisor (MSR[HV] = 1 and MSR[PR]=0)", }, [ POWER7_PME_PM_MRK_DATA_FROM_RL2L3_SHR ] = { .pme_name = "PM_MRK_DATA_FROM_RL2L3_SHR", .pme_code = 0x1d04c, .pme_short_desc = "Marked data loaded from remote L2 or L3 shared", .pme_long_desc = "The processor's Data Cache was reloaded with shared (T or SL) data from an L2 or L3 on a remote module due to a marked load", }, [ POWER7_PME_PM_DTLB_MISS_16M ] = { .pme_name = "PM_DTLB_MISS_16M", .pme_code = 0x4c05e, .pme_short_desc = "Data TLB miss for 16M page", .pme_long_desc = "Data TLB references to 16MB pages that missed the TLB. Page size is determined at TLB reload time.", }, [ POWER7_PME_PM_MRK_LSU_FIN ] = { .pme_name = "PM_MRK_LSU_FIN", .pme_code = 0x40032, .pme_short_desc = "Marked LSU instruction finished", .pme_long_desc = "One of the Load/Store Units finished a marked instruction. Instructions that finish may not necessary complete", }, [ POWER7_PME_PM_LSU1_LMQ_LHR_MERGE ] = { .pme_name = "PM_LSU1_LMQ_LHR_MERGE", .pme_code = 0xd09a, .pme_short_desc = "LS1 Load Merge with another cacheline request", .pme_long_desc = "LS1 Load Merge with another cacheline request", }, [ POWER7_PME_PM_IFU_FIN ] = { .pme_name = "PM_IFU_FIN", .pme_code = 0x40066, .pme_short_desc = "IFU Finished a (non-branch) instruction", .pme_long_desc = "The Instruction Fetch Unit finished an instruction", }, [ POWER7_PME_PM_1THRD_CON_RUN_INSTR ] = { .pme_name = "PM_1THRD_CON_RUN_INSTR", .pme_code = 0x30062, .pme_short_desc = "1 thread Concurrent Run Instructions", .pme_long_desc = "1 thread Concurrent Run Instructions", }, [ POWER7_PME_PM_CMPLU_STALL_COUNT ] = { .pme_name = "PM_CMPLU_STALL_COUNT", .pme_code = 0x4000B, .pme_short_desc = "Marked LSU instruction finished", .pme_long_desc = "One of the Load/Store Units finished a marked instruction. Instructions that finish may not necessary complete", }, [ POWER7_PME_PM_MEM0_PB_RD_CL ] = { .pme_name = "PM_MEM0_PB_RD_CL", .pme_code = 0x30083, .pme_short_desc = "Nest events (MC0/MC1/PB/GX), Pair2 Bit1", .pme_long_desc = "Nest events (MC0/MC1/PB/GX), Pair2 Bit1", }, [ POWER7_PME_PM_THRD_1_RUN_CYC ] = { .pme_name = "PM_THRD_1_RUN_CYC", .pme_code = 0x10060, .pme_short_desc = "1 thread in Run Cycles", .pme_long_desc = "At least one thread has set its run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. This event does not respect FCWAIT.", }, [ POWER7_PME_PM_THRD_2_CONC_RUN_INSTR ] = { .pme_name = "PM_THRD_2_CONC_RUN_INSTR", .pme_code = 0x40062, .pme_short_desc = "2 thread Concurrent Run Instructions", .pme_long_desc = "2 thread Concurrent Run Instructions", }, [ POWER7_PME_PM_THRD_2_RUN_CYC ] = { .pme_name = "PM_THRD_2_RUN_CYC", .pme_code = 0x20060, .pme_short_desc = "2 thread in Run Cycles", .pme_long_desc = "2 thread in Run Cycles", }, [ POWER7_PME_PM_THRD_3_CONC_RUN_INST ] = { .pme_name = "PM_THRD_3_CONC_RUN_INST", .pme_code = 0x10062, .pme_short_desc = "3 thread in Run Cycles", .pme_long_desc = "3 thread in Run Cycles", }, [ POWER7_PME_PM_THRD_3_RUN_CYC ] = { .pme_name = "PM_THRD_3_RUN_CYC", .pme_code = 0x30060, .pme_short_desc = "3 thread in Run Cycles", .pme_long_desc = "3 thread in Run Cycles", }, [ POWER7_PME_PM_THRD_4_CONC_RUN_INST ] = { .pme_name = "PM_THRD_4_CONC_RUN_INST", .pme_code = 0x20062, .pme_short_desc = "4 thread in Run Cycles", .pme_long_desc = "4 thread in Run Cycles", }, [ POWER7_PME_PM_THRD_4_RUN_CYC ] = { .pme_name = "PM_THRD_4_RUN_CYC", .pme_code = 0x40060, .pme_short_desc = "4 thread in Run Cycles", .pme_long_desc = "4 thread in Run Cycles", }, }; #endif libpfm-4.9.0/lib/events/amd64_events_fam17h.h0000664000175000017500000007527613223402656020524 0ustar eranianeranian/* * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * PMU: amd64_fam17h (AMD64 Fam17h)) */ static const amd64_umask_t amd64_fam17h_l1_itlb_miss_l2_itlb_miss[]={ { .uname = "IF1G", .udesc = "TBD", .ucode = 0x4, }, { .uname = "IF2M", .udesc = "TBD", .ucode = 0x2, }, { .uname = "IF4K", .udesc = "TBD", .ucode = 0x1, }, }; static const amd64_umask_t amd64_fam17h_retired_mmx_fp_instructions[]={ { .uname = "SSE_INSTR", .udesc = "TBD", .ucode = 0x4, }, { .uname = "MMX_INSTR", .udesc = "TBD", .ucode = 0x2, }, { .uname = "X87_INSTR", .udesc = "TBD", .ucode = 0x1, }, }; static const amd64_umask_t amd64_fam17h_tagged_ibs_ops[]={ { .uname = "IBS_COUNT_ROLLOVER", .udesc = "Number of times a uop could not be tagged by IBS because of a previous tagged uop that has not retired.", .ucode = 0x4, }, { .uname = "IBS_TAGGED_OPS_RET", .udesc = "Number of uops tagged by IBS that retired.", .ucode = 0x2, }, { .uname = "IBS_TAGGED_OPS", .udesc = "Number of uops tagged by IBS.", .ucode = 0x1, }, }; static const amd64_umask_t amd64_fam17h_number_of_move_elimination_and_scalar_op_optimization[]={ { .uname = "OPTIMIZED", .udesc = "Number of scalar ops optimized.", .ucode = 0x8, }, { .uname = "OPT_POTENTIAL", .udesc = "Number of ops that are candidates for optimization (have z-bit either set or pass.", .ucode = 0x4, }, { .uname = "SSE_MOV_OPS_ELIM", .udesc = "Number of SSE move ops eliminated.", .ucode = 0x2, }, { .uname = "SSE_MOV_OPS", .udesc = "Number of SSE move ops.", .ucode = 0x1, }, }; static const amd64_umask_t amd64_fam17h_retired_sse_avx_operations[]={ { .uname = "DP_MULT_ADD_FLOPS", .udesc = "Double precision multiply-add flops.", .ucode = 0x80, }, { .uname = "DP_DIV_FLOPS", .udesc = "Double precision divide/square root flops.", .ucode = 0x40, }, { .uname = "DP_MULT_FLOPS", .udesc = "Double precision multiply flops.", .ucode = 0x20, }, { .uname = "DP_ADD_SUB_FLOPS", .udesc = "Double precision add/subtract flops.", .ucode = 0x10, }, { .uname = "SP_MULT_ADD_FLOPS", .udesc = "Single precision multiply-add flops.", .ucode = 0x8, }, { .uname = "SP_DIV_FLOPS", .udesc = "Single precision divide/square root flops.", .ucode = 0x4, }, { .uname = "SP_MULT_FLOPS", .udesc = "Single precision multiply flops.", .ucode = 0x2, }, { .uname = "SP_ADD_SUB_FLOPS", .udesc = "Single precision add/subtract flops.", .ucode = 0x1, }, }; static const amd64_umask_t amd64_fam17h_retired_serializing_ops[]={ { .uname = "X87_CTRL_RET", .udesc = "X87 control word mispredict traps due to mispredction in RC or PC, or changes in mask bits.", .ucode = 0x8, }, { .uname = "X87_BOT_RET", .udesc = "X87 bottom-executing uops retired.", .ucode = 0x4, }, { .uname = "SSE_CTRL_RET", .udesc = "SSE control word mispreduct traps due to mispredctions in RC, FTZ or DAZ or changes in mask bits.", .ucode = 0x2, }, { .uname = "SSE_BOT_RET", .udesc = "SSE bottom-executing uops retired.", .ucode = 0x1, }, }; static const amd64_umask_t amd64_fam17h_retired_x87_floating_point_operations[]={ { .uname = "DIV_SQR_R_OPS", .udesc = "Divide and square root ops", .ucode = 0x4, }, { .uname = "MUL_OPS", .udesc = "Multiple ops", .ucode = 0x2, }, { .uname = "ADD_SUB_OPS", .udesc = "Add/subtract ops", .ucode = 0x1, }, }; static const amd64_umask_t amd64_fam17h_fpu_pipe_assignment[]={ { .uname = "DUAL3", .udesc = "Total number of multi-pipe uops assigned to pipe3", .ucode = 0x80, }, { .uname = "DUAL2", .udesc = "Total number of multi-pipe uops assigned to pipe2", .ucode = 0x40, }, { .uname = "DUAL1", .udesc = "Total number of multi-pipe uops assigned to pipe1", .ucode = 0x20, }, { .uname = "DUAL0", .udesc = "Total number of multi-pipe uops assigned to pipe0", .ucode = 0x10, }, { .uname = "TOTAL3", .udesc = "Total number of uops assigned to pipe3", .ucode = 0x8, }, { .uname = "TOTAL2", .udesc = "Total number of uops assigned to pipe2", .ucode = 0x4, }, { .uname = "TOTAL1", .udesc = "Total number of uops assigned to pipe1", .ucode = 0x2, }, { .uname = "TOTAL0", .udesc = "Total number of uops assigned to pipe0", .ucode = 0x1, }, }; static const amd64_umask_t amd64_fam17h_instruction_cache_lines_invalidated[]={ { .uname = "L2_INVALIDATING_PROBE", .udesc = "IC line invalidated due to L2 invalidating probe (external or LS).", .ucode = 0x2, }, { .uname = "FILL_INVALIDATED", .udesc = "IC line invalidated due to overwriting fill response.", .ucode = 0x1, }, }; static const amd64_umask_t amd64_fam17h_instruction_pipe_stall[]={ { .uname = "IC_STALL_ANY", .udesc = "IC pipe was stalled during this clock cycle for any reason (nothing valud in pipe ICM1).", .ucode = 0x4, }, { .uname = "IC_STALL_DQ_EMPTY", .udesc = "IC pipe was stalled during this clock cycle (including IC to OC fetches) due to DQ empty.", .ucode = 0x2, }, { .uname = "IC_STALL_BACK_PRESSURE", .udesc = "IC pipe was stalled during this clock cycle (ncluding IC to OC fetches) due to back pressure.", .ucode = 0x1, }, }; static const amd64_umask_t amd64_fam17h_core_to_l2_cacheable_request_access_status[]={ { .uname = "LS_RD_BLK_C_S", .udesc = "Load/Store ReadBlock C/S hit", .ucode = 0x80, }, { .uname = "LS_RD_BLK_L_HIT_X", .udesc = "Load/Store Readblock L hit eXclusive.", .ucode = 0x40, }, { .uname = "LS_RD_BLK_L_HIT_S", .udesc = "Load/Store ReadBlock L hit Shared.", .ucode = 0x20, }, { .uname = "LS_RD_BLK_X", .udesc = "Load/Store ReadblockX/ChangeToX hit eXclusive.", .ucode = 0x10, }, { .uname = "LS_RD_BLK_C", .udesc = "Load/Store ReadBlock C S L X Change To X Miss.", .ucode = 0x8, }, { .uname = "IC_FILL_HIT_X", .udesc = "Icache fill hit eXclusive.", .ucode = 0x4, }, { .uname = "IC_FILL_HIT_S", .udesc = "Icache fill hit Shared.", .ucode = 0x2, }, { .uname = "IC_FILL_MISS", .udesc = "Icache fill miss.", .ucode = 0x1, }, }; static const amd64_umask_t amd64_fam17h_cycles_with_fill_pending_from_l2[]={ { .uname = "L2_FILL_BUSY", .udesc = "TBD", .ucode = 0x1, .uflags = AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam17h_l2_latency[]={ { .uname = "L2_CYCLES_WAITING_ON_FILLS", .udesc = "TBD", .ucode = 0x1, .uflags = AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam17h_requests_to_l2_group1[]={ { .uname = "RD_BLK_L", .udesc = "TBD", .ucode = 0x80, }, { .uname = "RD_BLK_X", .udesc = "TBD", .ucode = 0x40, }, { .uname = "LS_RD_BLK_C_S", .udesc = "TBD", .ucode = 0x20, }, { .uname = "CACHEABLE_IC_READ", .udesc = "TBD", .ucode = 0x10, }, { .uname = "CHANGE_TO_X", .udesc = "TBD", .ucode = 0x8, }, { .uname = "PREFETCH_L2", .udesc = "TBD", .ucode = 0x4, }, { .uname = "L2_HW_PF", .udesc = "TBD", .ucode = 0x2, }, { .uname = "OTHER_REQUESTS", .udesc = "TBD", .ucode = 0x1, }, }; static const amd64_umask_t amd64_fam17h_requests_to_l2_group2[]={ { .uname = "GROUP1", .udesc = "TBD", .ucode = 0x80, }, { .uname = "LS_RD_SIZED", .udesc = "TBD", .ucode = 0x40, }, { .uname = "LS_RD_SIZED_N_C", .udesc = "TBD", .ucode = 0x20, }, { .uname = "IC_RD_SIZED", .udesc = "TBD", .ucode = 0x10, }, { .uname = "IC_RD_SIZED_N_C", .udesc = "TBD", .ucode = 0x8, }, { .uname = "SMC_INVAL", .udesc = "TBD", .ucode = 0x4, }, { .uname = "BUS_LOCKS_ORIGINATOR", .udesc = "TBD", .ucode = 0x2, }, { .uname = "BUS_LOCKS_RESPONSES", .udesc = "TBD", .ucode = 0x1, }, }; static const amd64_umask_t amd64_fam17h_ls_to_l2_wbc_requests[]={ { .uname = "WCB_WRITE", .udesc = "TBD", .ucode = 0x40, }, { .uname = "WCB_CLOSE", .udesc = "TBD", .ucode = 0x20, }, { .uname = "CACHE_LINE_FLUSH", .udesc = "TBD", .ucode = 0x10, }, { .uname = "I_LINE_FLUSH", .udesc = "TBD", .ucode = 0x8, }, { .uname = "ZERO_BYTE_STORE", .udesc = "TBD", .ucode = 0x4, }, { .uname = "LOCAL_IC_CLR", .udesc = "TBD", .ucode = 0x2, }, { .uname = "C_L_ZERO", .udesc = "TBD", .ucode = 0x1, }, }; static const amd64_umask_t amd64_fam17h_ls_dispatch[]={ { .uname = "LD_ST_DISPATCH", .udesc = "Load/Store uops dispatched.", .ucode = 0x4, }, { .uname = "STORE_DISPATCH", .udesc = "Store uops dispatched.", .ucode = 0x2, }, { .uname = "LD_DISPATCH", .udesc = "Load uops dispatched.", .ucode = 0x1, }, }; static const amd64_umask_t amd64_fam17h_ineffective_software_prefetch[]={ { .uname = "MAB_MCH_CNT", .udesc = "TBD", .ucode = 0x2, }, { .uname = "DATA_PIPE_SW_PF_DC_HIT", .udesc = "TBD", .ucode = 0x1, }, }; static const amd64_umask_t amd64_fam17h_l1_dtlb_miss[]={ { .uname = "TLB_RELOAD_1G_L2_MISS", .udesc = "TBD", .ucode = 0x80, }, { .uname = "TLB_RELOAD_2M_L2_MISS", .udesc = "TBD", .ucode = 0x40, }, { .uname = "TLB_RELOAD_32K_L2_MISS", .udesc = "TBD", .ucode = 0x20, }, { .uname = "TLB_RELOAD_4K_L2_MISS", .udesc = "TBD", .ucode = 0x10, }, { .uname = "TLB_RELOAD_1G_L2_HIT", .udesc = "TBD", .ucode = 0x8, }, { .uname = "TLB_RELOAD_2M_L2_HIT", .udesc = "TBD", .ucode = 0x4, }, { .uname = "TLB_RELOAD_32K_L2_HIT", .udesc = "TBD", .ucode = 0x2, }, { .uname = "TLB_RELOAD_4K_L2_HIT", .udesc = "TBD", .ucode = 0x1, }, }; static const amd64_umask_t amd64_fam17h_locks[]={ { .uname = "SPEC_LOCK_MAP_COMMIT", .udesc = "TBD", .ucode = 0x8, }, { .uname = "SPEC_LOCK", .udesc = "TBD", .ucode = 0x4, }, { .uname = "NON_SPEC_LOCK", .udesc = "TBD", .ucode = 0x2, }, { .uname = "BUS_LOCK", .udesc = "TBD", .ucode = 0x1, }, }; static const amd64_umask_t amd64_fam17h_mab_allocation_by_pipe[]={ { .uname = "TLB_PIPE_EARLY", .udesc = "TBD", .ucode = 0x10, }, { .uname = "HW_PF", .udesc = "hw_pf", .ucode = 0x8, }, { .uname = "TLB_PIPE_LATE", .udesc = "TBD", .ucode = 0x4, }, { .uname = "ST_PIPE", .udesc = "TBD", .ucode = 0x2, }, { .uname = "DATA_PIPE", .udesc = "TBD", .ucode = 0x1, }, }; static const amd64_umask_t amd64_fam17h_prefetch_instructions_dispatched[]={ { .uname = "PREFETCH_NTA", .udesc = "Non-temporal prefetches.", .ucode = 0x4, }, { .uname = "STORE_PREFETCH_W", .udesc = "TBD", .ucode = 0x2, }, { .uname = "LOAD_PREFETCH_W", .udesc = "TBD", .ucode = 0x1, }, }; static const amd64_umask_t amd64_fam17h_tablewalker_allocation[]={ { .uname = "ALLOC_ISIDE1", .udesc = "TBD", .ucode = 0x8, }, { .uname = "ALLOC_ISIDE0", .udesc = "TBD", .ucode = 0x4, }, { .uname = "ALLOC_DSIDE1", .udesc = "TBD", .ucode = 0x2, }, { .uname = "ALLOC_DSIDE0", .udesc = "TBD", .ucode = 0x1, }, }; static const amd64_umask_t amd64_fam17h_oc_mode_switch[]={ { .uname = "OC_IC_MODE_SWITCH", .udesc = "TBD", .ucode = 0x2, }, { .uname = "IC_OC_MODE_SWITCH", .udesc = "TBD", .ucode = 0x1, }, }; static const amd64_umask_t amd64_fam17h_dynamic_tokens_dispatch_stall_cycles_0[]={ { .uname = "RETIRE_TOKEN_STALL", .udesc = "Retire tokens unavailable", .ucode = 0x40, }, { .uname = "AGSQ_TOKEN_STALL", .udesc = "AGSQ tokens unavailable", .ucode = 0x20, }, { .uname = "ALU_TOKEN_STALL", .udesc = "ALU tokens unavailable", .ucode = 0x10, }, { .uname = "ALSQ3_0_TOKEN_STALL", .udesc = "TBD", .ucode = 0x8, }, { .uname = "ALSQ3_TOKEN_STALL", .udesc = "ALSQ3 tokens unavailable", .ucode = 0x4, }, { .uname = "ALSQ2_TOKEN_STALL", .udesc = "ALSQ2 tokens unavailable", .ucode = 0x2, }, { .uname = "ALSQ1_TOKEN_STALL", .udesc = "ALSQ1 tokens unavailable", .ucode = 0x1, }, }; static const amd64_entry_t amd64_fam17h_pe[]={ { .name = "L1_ITLB_MISS_L2_ITLB_HIT", .desc = "The number of instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB.", .modmsk = AMD64_FAM17H_ATTRS, .code = 0x84, .flags = 0, .ngrp = 0, }, { .name = "L1_ITLB_MISS_L2_ITLB_MISS", .desc = "The number of instruction fetches that miss in both the L1 and L2 TLBs.", .modmsk = AMD64_FAM17H_ATTRS, .code = 0x85, .flags = 0, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam17h_l1_itlb_miss_l2_itlb_miss), .umasks = amd64_fam17h_l1_itlb_miss_l2_itlb_miss, }, { .name = "PIPELINE_RESTART_DUE_TO_INSTRUCTION_STREAM_PROBE", .desc = "The number of pipeline restarts caused by invalidating probes that hit on the instruction stream currently being executed. This would happen if the active instruction stream was being modified by another processor in an MP system - typically a highly unlikely event.", .modmsk = AMD64_FAM17H_ATTRS, .code = 0x86, .flags = 0, .ngrp = 0, }, { .name = "ITLB_RELOADS", .desc = "The number of ITLB reload requests.", .modmsk = AMD64_FAM17H_ATTRS, .code = 0x99, .flags = 0, .ngrp = 0, }, { .name = "DIV_CYCLES_BUSY_COUNT", .desc = "TBD", .modmsk = AMD64_FAM17H_ATTRS, .code = 0xd3, .flags = 0, .ngrp = 0, }, { .name = "DIV_OP_COUNT", .desc = "TBD", .modmsk = AMD64_FAM17H_ATTRS, .code = 0xd4, .flags = 0, .ngrp = 0, }, { .name = "RETIRED_BRANCH_INSTRUCTIONS", .desc = "The number of branch instructions retired. This includes all types of architectural control flow changes, including exceptions and interrupts.", .modmsk = AMD64_FAM17H_ATTRS, .code = 0xc2, .flags = 0, .ngrp = 0, }, { .name = "RETIRED_FAR_CONTROL_TRANSFERS", .desc = "The number of far control transfers retired including far call/jump/return, IRET, SYSCALL and SYSRET, plus exceptions and interrupts. Far control transfers are not subject to branch prediction.", .modmsk = AMD64_FAM17H_ATTRS, .code = 0xc6, .flags = 0, .ngrp = 0, }, { .name = "RETIRED_INDIRECT_BRANCH_INSTRUCTIONS_MISPREDICTED", .desc = "TBD", .modmsk = AMD64_FAM17H_ATTRS, .code = 0xca, .flags = 0, .ngrp = 0, }, { .name = "RETIRED_BRANCH_INSTRUCTIONS_MISPREDICTED", .desc = "The number of branch instructions retired, of any type, that were not correctly predicted. This includes those for which prediction is not attempted (far control transfers, exceptions and interrupts).", .modmsk = AMD64_FAM17H_ATTRS, .code = 0xc3, .flags = 0, .ngrp = 0, }, { .name = "RETIRED_BRANCH_RESYNCS", .desc = "The number of resync branches. These reflect pipeline restarts due to certain microcode assists and events such as writes to the active instruction stream, among other things. Each occurrence reflects a restart penalty similar to a branch mispredict. This is relatively rare.", .modmsk = AMD64_FAM17H_ATTRS, .code = 0xc7, .flags = 0, .ngrp = 0, }, { .name = "RETIRED_TAKEN_BRANCH_INSTRUCTIONS", .desc = "The number of taken branches that were retired. This includes all types of architectural control flow changes, including exceptions and interrupts.", .modmsk = AMD64_FAM17H_ATTRS, .code = 0xc4, .flags = 0, .ngrp = 0, }, { .name = "RETIRED_TAKEN_BRANCH_INSTRUCTIONS_MISPREDICTED", .desc = "The number of retired taken branch instructions that were mispredicted.", .modmsk = AMD64_FAM17H_ATTRS, .code = 0xc5, .flags = 0, .ngrp = 0, }, { .name = "RETIRED_CONDITIONAL_BRANCH_INSTRUCTIONS", .desc = "TBD", .modmsk = AMD64_FAM17H_ATTRS, .code = 0xd1, .flags = 0, .ngrp = 0, }, { .name = "RETIRED_CONDITIONAL_BRANCH_INSTRUCTIONS_MISPREDICTED", .desc = "TBD", .modmsk = AMD64_FAM17H_ATTRS, .code = 0xd2, .flags = 0, .ngrp = 0, }, { .name = "RETIRED_UOPS", .desc = "The number of uops retired. This includes all processor activity (instructions, exceptions, interrupts, microcode assists, etc.). The number of events logged per cycle can vary from 0 to 4.", .modmsk = AMD64_FAM17H_ATTRS, .code = 0xc1, .flags = 0, .ngrp = 0, }, { .name = "RETIRED_FUSED_BRANCH_INSTRUCTIONS", .desc = "The number of fused retired branch instructions retired per cycle. The number of events logged per cycle can vary from 0 to 3.", .modmsk = AMD64_FAM17H_ATTRS, .code = 0x1d0, .flags = 0, .ngrp = 0, }, { .name = "RETIRED_INSTRUCTIONS", .desc = "Instructions Retired.", .modmsk = AMD64_FAM17H_ATTRS, .code = 0xc0, .flags = 0, .ngrp = 0, }, { .name = "RETIRED_MMX_FP_INSTRUCTIONS", .desc = "The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS.", .modmsk = AMD64_FAM17H_ATTRS, .code = 0xcb, .flags = 0, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam17h_retired_mmx_fp_instructions), .umasks = amd64_fam17h_retired_mmx_fp_instructions, }, { .name = "RETIRED_NEAR_RETURNS", .desc = "The number of near return instructions (RET or RETI) retired.", .modmsk = AMD64_FAM17H_ATTRS, .code = 0xc8, .flags = 0, .ngrp = 0, }, { .name = "RETIRED_NEAR_RETURNS_MISPREDICTED", .desc = "The number of near returns retired that were not correctly predicted by the return address predictor. Each such mispredict incurs the same penalty as a mispredicted conditional branch instruction.", .modmsk = AMD64_FAM17H_ATTRS, .code = 0xc9, .flags = 0, .ngrp = 0, }, { .name = "TAGGED_IBS_OPS", .desc = "TBD", .modmsk = AMD64_FAM17H_ATTRS, .code = 0x1cf, .flags = 0, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam17h_tagged_ibs_ops), .umasks = amd64_fam17h_tagged_ibs_ops, }, { .name = "NUMBER_OF_MOVE_ELIMINATION_AND_SCALAR_OP_OPTIMIZATION", .desc = "This is a dispatch based speculative event. It is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes.", .modmsk = AMD64_FAM17H_ATTRS, .code = 0x4, .flags = 0, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam17h_number_of_move_elimination_and_scalar_op_optimization), .umasks = amd64_fam17h_number_of_move_elimination_and_scalar_op_optimization, }, { .name = "RETIRED_SSE_AVX_OPERATIONS", .desc = "This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15.", .modmsk = AMD64_FAM17H_ATTRS, .code = 0x3, .flags = 0, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam17h_retired_sse_avx_operations), .umasks = amd64_fam17h_retired_sse_avx_operations, }, { .name = "RETIRED_SERIALIZING_OPS", .desc = "The number of serializing Ops retired.", .modmsk = AMD64_FAM17H_ATTRS, .code = 0x5, .flags = 0, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam17h_retired_serializing_ops), .umasks = amd64_fam17h_retired_serializing_ops, }, { .name = "RETIRED_X87_FLOATING_POINT_OPERATIONS", .desc = "The number of x87 floating-point Ops that have retired. The number of events logged per cycle can vary from 0 to 8.", .modmsk = AMD64_FAM17H_ATTRS, .code = 0x2, .flags = 0, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam17h_retired_x87_floating_point_operations), .umasks = amd64_fam17h_retired_x87_floating_point_operations, }, { .name = "FP_SCHEDULER_EMPTY", .desc = "This is a speculative event. The number of cycles in which the FPU scheduler is empty. Note that some Ops like FP loads bypass the scheduler. Invert this to count cycles in which at least one FPU operation is present in the FPU.", .modmsk = AMD64_FAM17H_ATTRS, .code = 0x1, .flags = 0, .ngrp = 0, }, { .name = "FPU_PIPE_ASSIGNMENT", .desc = "The number of operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one-cycle dispatch event. This event is a speculative event. (See Core::X86::Pmc::Core::ExRetMmxFpInstr). Since this event includes non-numeric operations it is not suitable for measuring MFLOPS.", .modmsk = AMD64_FAM17H_ATTRS, .code = 0x0, .flags = 0, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam17h_fpu_pipe_assignment), .umasks = amd64_fam17h_fpu_pipe_assignment, }, { .name = "INSTRUCTION_CACHE_REFILLS_FROM_L2", .desc = "The number of 64-byte instruction cachelines that was fulfilled by the L2 cache.", .modmsk = AMD64_FAM17H_ATTRS, .code = 0x82, .flags = 0, .ngrp = 0, }, { .name = "INSTRUCTION_CACHE_REFILLS_FROM_SYSTEM", .desc = "The number of 64-byte instruction cachelines fulfilled from system memory or another cache.", .modmsk = AMD64_FAM17H_ATTRS, .code = 0x83, .flags = 0, .ngrp = 0, }, { .name = "INSTRUCTION_CACHE_LINES_INVALIDATED", .desc = "The number of instruction cachelines invalidated. A non-SMC event is CMC (cross modifying code), either from the other thread of the core or another core.", .modmsk = AMD64_FAM17H_ATTRS, .code = 0x8c, .flags = 0, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam17h_instruction_cache_lines_invalidated), .umasks = amd64_fam17h_instruction_cache_lines_invalidated, }, { .name = "INSTRUCTION_PIPE_STALL", .desc = "TBD", .modmsk = AMD64_FAM17H_ATTRS, .code = 0x87, .flags = 0, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam17h_instruction_pipe_stall), .umasks = amd64_fam17h_instruction_pipe_stall, }, { .name = "32_BYTE_INSTRUCTION_CACHE_FETCH", .desc = "The number of 32B fetch windows transferred from IC pipe to DE instruction decoder (includes non-cacheable and cacheable fill responses).", .modmsk = AMD64_FAM17H_ATTRS, .code = 0x80, .flags = 0, .ngrp = 0, }, { .name = "32_BYTE_INSTRUCTION_CACHE_MISSES", .desc = "The number of 32B fetch windows tried to read the L1 IC and missed in the full tag.", .modmsk = AMD64_FAM17H_ATTRS, .code = 0x81, .flags = 0, .ngrp = 0, }, { .name = "CORE_TO_L2_CACHEABLE_REQUEST_ACCESS_STATUS", .desc = "This event does not count accesses to the L2 cache by the L2 prefetcher, but it does count accesses by the L1 prefetcher.", .modmsk = AMD64_FAM17H_ATTRS, .code = 0x64, .flags = 0, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam17h_core_to_l2_cacheable_request_access_status), .umasks = amd64_fam17h_core_to_l2_cacheable_request_access_status, }, { .name = "CYCLES_WITH_FILL_PENDING_FROM_L2", .desc = "Total cycles spent with one or more fill requests in flight from L2.", .modmsk = AMD64_FAM17H_ATTRS, .code = 0x6d, .flags = 0, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam17h_cycles_with_fill_pending_from_l2), .umasks = amd64_fam17h_cycles_with_fill_pending_from_l2, }, { .name = "L2_LATENCY", .desc = "Total cycles spent waiting for L2 fills to complete from L3 or memory, divided by four. This may be used to calculate average latency by multiplying this count by four and then dividing by the total number of L2 fills (umask L2RequestG1). Event counts are for both threads. To calculate average latency, the number of fills from both threads must be used.", .modmsk = AMD64_FAM17H_ATTRS, .code = 0x62, .flags = 0, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam17h_l2_latency), .umasks = amd64_fam17h_l2_latency, }, { .name = "REQUESTS_TO_L2_GROUP1", .desc = "TBD", .modmsk = AMD64_FAM17H_ATTRS, .code = 0x60, .flags = 0, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam17h_requests_to_l2_group1), .umasks = amd64_fam17h_requests_to_l2_group1, }, { .name = "REQUESTS_TO_L2_GROUP2", .desc = "Multi-events in that LS and IF requests can be received simultaneous.", .modmsk = AMD64_FAM17H_ATTRS, .code = 0x61, .flags = 0, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam17h_requests_to_l2_group2), .umasks = amd64_fam17h_requests_to_l2_group2, }, { .name = "LS_TO_L2_WBC_REQUESTS", .desc = "TBD", .modmsk = AMD64_FAM17H_ATTRS, .code = 0x63, .flags = 0, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam17h_ls_to_l2_wbc_requests), .umasks = amd64_fam17h_ls_to_l2_wbc_requests, }, { .name = "DATA_CACHE_ACCESSES", .desc = "The number of accesses to the data cache for load and store references. This may include certain microcode scratchpad accesses, although these are generally rare. Each increment represents an eight-byte access, although the instruction may only be accessing a portion of that. This event is a speculative event.", .modmsk = AMD64_FAM17H_ATTRS, .code = 0x40, .flags = 0, .ngrp = 0, }, { .name = "LS_DISPATCH", .desc = "Counts the number of operations dispatched to the LS unit. Unit Masks ADDed.", .modmsk = AMD64_FAM17H_ATTRS, .code = 0x29, .flags = 0, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam17h_ls_dispatch), .umasks = amd64_fam17h_ls_dispatch, }, { .name = "INEFFECTIVE_SOFTWARE_PREFETCH", .desc = "The number of software prefetches that did not fetch data outside of the processor core.", .modmsk = AMD64_FAM17H_ATTRS, .code = 0x52, .flags = 0, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam17h_ineffective_software_prefetch), .umasks = amd64_fam17h_ineffective_software_prefetch, }, { .name = "L1_DTLB_MISS", .desc = "L1 Data TLB misses.", .modmsk = AMD64_FAM17H_ATTRS, .code = 0x45, .flags = 0, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam17h_l1_dtlb_miss), .umasks = amd64_fam17h_l1_dtlb_miss, }, { .name = "LOCKS", .desc = "Lock operations. Unit masks ORed", .modmsk = AMD64_FAM17H_ATTRS, .code = 0x25, .flags = 0, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam17h_locks), .umasks = amd64_fam17h_locks, }, { .name = "MAB_ALLOCATION_BY_PIPE", .desc = "TBD", .modmsk = AMD64_FAM17H_ATTRS, .code = 0x41, .flags = 0, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam17h_mab_allocation_by_pipe), .umasks = amd64_fam17h_mab_allocation_by_pipe, }, { .name = "MISALIGNED_LOADS", .desc = "TBD", .modmsk = AMD64_FAM17H_ATTRS, .code = 0x47, .flags = 0, .ngrp = 0, }, { .name = "CYCLES_NOT_IN_HALT", .desc = "TBD", .modmsk = AMD64_FAM17H_ATTRS, .code = 0x76, .flags = 0, .ngrp = 0, }, { .name = "PREFETCH_INSTRUCTIONS_DISPATCHED", .desc = "Software Prefetch Instructions Dispatched.", .modmsk = AMD64_FAM17H_ATTRS, .code = 0x4b, .flags = 0, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam17h_prefetch_instructions_dispatched), .umasks = amd64_fam17h_prefetch_instructions_dispatched, }, { .name = "STORE_TO_LOAD_FORWARD", .desc = "Number of STore Lad Forward hits.", .modmsk = AMD64_FAM17H_ATTRS, .code = 0x35, .flags = 0, .ngrp = 0, }, { .name = "TABLEWALKER_ALLOCATION", .desc = "TBD", .modmsk = AMD64_FAM17H_ATTRS, .code = 0x46, .flags = 0, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam17h_tablewalker_allocation), .umasks = amd64_fam17h_tablewalker_allocation, }, { .name = "MERGE", .desc = "See .", .modmsk = AMD64_FAM17H_ATTRS, .code = 0xfff, .flags = 0, .ngrp = 0, }, { .name = "L1_BTB_CORRECTION", .desc = "TBD", .modmsk = AMD64_FAM17H_ATTRS, .code = 0x8a, .flags = 0, .ngrp = 0, }, { .name = "L2_BTB_CORRECTION", .desc = "TBD", .modmsk = AMD64_FAM17H_ATTRS, .code = 0x8b, .flags = 0, .ngrp = 0, }, { .name = "OC_MODE_SWITCH", .desc = "TBD", .modmsk = AMD64_FAM17H_ATTRS, .code = 0x28a, .flags = 0, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam17h_oc_mode_switch), .umasks = amd64_fam17h_oc_mode_switch, }, { .name = "DYNAMIC_TOKENS_DISPATCH_STALLS_CYCLES_0", .desc = "Cycles where a dispatch group is valid but does not get dispatched due to a token stall.", .modmsk = AMD64_FAM17H_ATTRS, .code = 0xaf, .flags = 0, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam17h_dynamic_tokens_dispatch_stall_cycles_0), .umasks = amd64_fam17h_dynamic_tokens_dispatch_stall_cycles_0, }, }; libpfm-4.9.0/lib/events/amd64_events_fam15h.h0000664000175000017500000011124313223402656020503 0ustar eranianeranian/* * Copyright (c) 2011 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * This file has been automatically generated. * * PMU: amd64_fam15h (AMD64 Fam15h Interlagos) * * Based on libpfm patch by Robert Richter : * Family 15h Microarchitecture performance monitor events * * History: * * Apr 29 2011 -- Robert Richter, robert.richter@amd.com: * Source: BKDG for AMD Family 15h Models 00h-0Fh Processors, * 42301, Rev 1.15, April 18, 2011 * * Dec 09 2010 -- Robert Richter, robert.richter@amd.com: * Source: BIOS and Kernel Developer's Guide for the AMD Family 15h * Processors, Rev 0.90, May 18, 2010 */ #define CORE_SELECT(b) \ { .uname = "CORE_0",\ .udesc = "Measure on Core0",\ .ucode = 0 << 4,\ .grpid = b,\ .uflags= AMD64_FL_NCOMBO,\ },\ { .uname = "CORE_1",\ .udesc = "Measure on Core1",\ .ucode = 1 << 4,\ .grpid = b,\ .uflags= AMD64_FL_NCOMBO,\ },\ { .uname = "CORE_2",\ .udesc = "Measure on Core2",\ .ucode = 2 << 4,\ .grpid = b,\ .uflags= AMD64_FL_NCOMBO,\ },\ { .uname = "CORE_3",\ .udesc = "Measure on Core3",\ .ucode = 3 << 4,\ .grpid = b,\ .uflags= AMD64_FL_NCOMBO,\ },\ { .uname = "CORE_4",\ .udesc = "Measure on Core4",\ .ucode = 4 << 4,\ .grpid = b,\ .uflags= AMD64_FL_NCOMBO,\ },\ { .uname = "CORE_5",\ .udesc = "Measure on Core5",\ .ucode = 5 << 4,\ .grpid = b,\ .uflags= AMD64_FL_NCOMBO,\ },\ { .uname = "CORE_6",\ .udesc = "Measure on Core6",\ .ucode = 6 << 4,\ .grpid = b,\ .uflags= AMD64_FL_NCOMBO,\ },\ { .uname = "CORE_7",\ .udesc = "Measure on Core7",\ .ucode = 7 << 4,\ .grpid = b,\ .uflags= AMD64_FL_NCOMBO,\ },\ { .uname = "ANY_CORE",\ .udesc = "Measure on any core",\ .ucode = 0xf << 4,\ .grpid = b,\ .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,\ } static const amd64_umask_t amd64_fam15h_dispatched_fpu_ops[]={ { .uname = "OPS_PIPE0", .udesc = "Total number uops assigned to Pipe 0", .ucode = 0x1, }, { .uname = "OPS_PIPE1", .udesc = "Total number uops assigned to Pipe 1", .ucode = 0x2, }, { .uname = "OPS_PIPE2", .udesc = "Total number uops assigned to Pipe 2", .ucode = 0x4, }, { .uname = "OPS_PIPE3", .udesc = "Total number uops assigned to Pipe 3", .ucode = 0x8, }, { .uname = "OPS_DUAL_PIPE0", .udesc = "Total number dual-pipe uops assigned to Pipe 0", .ucode = 0x10, }, { .uname = "OPS_DUAL_PIPE1", .udesc = "Total number dual-pipe uops assigned to Pipe 1", .ucode = 0x20, }, { .uname = "OPS_DUAL_PIPE2", .udesc = "Total number dual-pipe uops assigned to Pipe 2", .ucode = 0x40, }, { .uname = "OPS_DUAL_PIPE3", .udesc = "Total number dual-pipe uops assigned to Pipe 3", .ucode = 0x80, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xff, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam15h_retired_sse_ops[]={ { .uname = "SINGLE_ADD_SUB_OPS", .udesc = "Single-precision add/subtract FLOPS", .ucode = 0x1, }, { .uname = "SINGLE_MUL_OPS", .udesc = "Single-precision multiply FLOPS", .ucode = 0x2, }, { .uname = "SINGLE_DIV_OPS", .udesc = "Single-precision divide/square root FLOPS", .ucode = 0x4, }, { .uname = "SINGLE_MUL_ADD_OPS", .udesc = "Single precision multiply-add FLOPS. Multiply-add counts as 2 FLOPS", .ucode = 0x8, }, { .uname = "DOUBLE_ADD_SUB_OPS", .udesc = "Double precision add/subtract FLOPS", .ucode = 0x10, }, { .uname = "DOUBLE_MUL_OPS", .udesc = "Double precision multiply FLOPS", .ucode = 0x20, }, { .uname = "DOUBLE_DIV_OPS", .udesc = "Double precision divide/square root FLOPS", .ucode = 0x40, }, { .uname = "DOUBLE_MUL_ADD_OPS", .udesc = "Double precision multiply-add FLOPS. Multiply-add counts as 2 FLOPS", .ucode = 0x80, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xff, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam15h_move_scalar_optimization[]={ { .uname = "SSE_MOVE_OPS", .udesc = "Number of SSE Move Ops", .ucode = 0x1, }, { .uname = "SSE_MOVE_OPS_ELIM", .udesc = "Number of SSE Move Ops eliminated", .ucode = 0x2, }, { .uname = "OPT_CAND", .udesc = "Number of Ops that are candidates for optimization (Z-bit set or pass)", .ucode = 0x4, }, { .uname = "SCALAR_OPS_OPTIMIZED", .udesc = "Number of Scalar ops optimized", .ucode = 0x8, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xf, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam15h_retired_serializing_ops[]={ { .uname = "SSE_RETIRED", .udesc = "SSE bottom-executing uops retired", .ucode = 0x1, }, { .uname = "SSE_MISPREDICTED", .udesc = "SSE control word mispredict traps due to mispredictions", .ucode = 0x2, }, { .uname = "X87_RETIRED", .udesc = "X87 bottom-executing uops retired", .ucode = 0x4, }, { .uname = "X87_MISPREDICTED", .udesc = "X87 control word mispredict traps due to mispredictions", .ucode = 0x8, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xf, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam15h_segment_register_loads[]={ { .uname = "ES", .udesc = "ES", .ucode = 0x1, }, { .uname = "CS", .udesc = "CS", .ucode = 0x2, }, { .uname = "SS", .udesc = "SS", .ucode = 0x4, }, { .uname = "DS", .udesc = "DS", .ucode = 0x8, }, { .uname = "FS", .udesc = "FS", .ucode = 0x10, }, { .uname = "GS", .udesc = "GS", .ucode = 0x20, }, { .uname = "HS", .udesc = "HS", .ucode = 0x40, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x7f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam15h_load_q_store_q_full[]={ { .uname = "LOAD_QUEUE", .udesc = "The number of cycles that the load buffer is full", .ucode = 0x1, }, { .uname = "STORE_QUEUE", .udesc = "The number of cycles that the store buffer is full", .ucode = 0x2, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam15h_locked_ops[]={ { .uname = "EXECUTED", .udesc = "Number of locked instructions executed", .ucode = 0x1, }, { .uname = "CYCLES_NON_SPECULATIVE_PHASE", .udesc = "Number of cycles spent in non-speculative phase, excluding cache miss penalty", .ucode = 0x4, }, { .uname = "CYCLES_WAITING", .udesc = "Number of cycles spent in non-speculative phase, including the cache miss penalty", .ucode = 0x8, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xd, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam15h_cancelled_store_to_load[]={ { .uname = "SIZE_ADDRESS_MISMATCHES", .udesc = "Store is smaller than load or different starting byte but partial overlap", .ucode = 0x1, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x1, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam15h_data_cache_misses[]={ { .uname = "DC_MISS_STREAMING_STORE", .udesc = "First data cache miss or streaming store to a 64B cache line", .ucode = 0x1, }, { .uname = "STREAMING_STORE", .udesc = "First streaming store to a 64B cache line", .ucode = 0x2, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam15h_data_cache_refills_from_l2_or_northbridge[]={ { .uname = "GOOD", .udesc = "Fill with good data. (Final valid status is valid)", .ucode = 0x1, }, { .uname = "INVALID", .udesc = "Early valid status turned out to be invalid", .ucode = 0x2, }, { .uname = "POISON", .udesc = "Fill with poison data", .ucode = 0x4, }, { .uname = "READ_ERROR", .udesc = "Fill with read data error", .ucode = 0x8, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xf, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam15h_unified_tlb_hit[]={ { .uname = "4K_DATA", .udesc = "4 KB unified TLB hit for data", .ucode = 0x1, }, { .uname = "2M_DATA", .udesc = "2 MB unified TLB hit for data", .ucode = 0x2, }, { .uname = "1G_DATA", .udesc = "1 GB unified TLB hit for data", .ucode = 0x4, }, { .uname = "4K_INST", .udesc = "4 KB unified TLB hit for instruction", .ucode = 0x10, }, { .uname = "2M_INST", .udesc = "2 MB unified TLB hit for instruction", .ucode = 0x20, }, { .uname = "1G_INST", .udesc = "1 GB unified TLB hit for instruction", .ucode = 0x40, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x77, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam15h_unified_tlb_miss[]={ { .uname = "4K_DATA", .udesc = "4 KB unified TLB miss for data", .ucode = 0x1, }, { .uname = "2M_DATA", .udesc = "2 MB unified TLB miss for data", .ucode = 0x2, }, { .uname = "1GB_DATA", .udesc = "1 GB unified TLB miss for data", .ucode = 0x4, }, { .uname = "4K_INST", .udesc = "4 KB unified TLB miss for instruction", .ucode = 0x10, }, { .uname = "2M_INST", .udesc = "2 MB unified TLB miss for instruction", .ucode = 0x20, }, { .uname = "1G_INST", .udesc = "1 GB unified TLB miss for instruction", .ucode = 0x40, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x77, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam15h_prefetch_instructions_dispatched[]={ { .uname = "LOAD", .udesc = "Load (Prefetch, PrefetchT0/T1/T2)", .ucode = 0x1, }, { .uname = "STORE", .udesc = "Store (PrefetchW)", .ucode = 0x2, }, { .uname = "NTA", .udesc = "NTA (PrefetchNTA)", .ucode = 0x4, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x7, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam15h_ineffective_sw_prefetches[]={ { .uname = "SW_PREFETCH_HIT_IN_L1", .udesc = "Software prefetch hit in the L1", .ucode = 0x1, }, { .uname = "SW_PREFETCH_HIT_IN_L2", .udesc = "Software prefetch hit in the L2", .ucode = 0x8, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x9, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam15h_memory_requests[]={ { .uname = "NON_CACHEABLE", .udesc = "Requests to non-cacheable (UC) memory", .ucode = 0x1, }, { .uname = "WRITE_COMBINING", .udesc = "Requests to non-cacheable (WC, but not WC+/SS) memory", .ucode = 0x2, }, { .uname = "STREAMING_STORE", .udesc = "Requests to non-cacheable (WC+/SS, but not WC) memory", .ucode = 0x80, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x83, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam15h_data_prefetcher[]={ { .uname = "ATTEMPTED", .udesc = "Prefetch attempts", .ucode = 0x2, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x2, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam15h_mab_reqs[]={ { .uname = "BUFFER_BIT_0", .udesc = "Buffer entry index bit 0", .ucode = 0x1, }, { .uname = "BUFFER_BIT_1", .udesc = "Buffer entry index bit 1", .ucode = 0x2, }, { .uname = "BUFFER_BIT_2", .udesc = "Buffer entry index bit 2", .ucode = 0x4, }, { .uname = "BUFFER_BIT_3", .udesc = "Buffer entry index bit 3", .ucode = 0x8, }, { .uname = "BUFFER_BIT_4", .udesc = "Buffer entry index bit 4", .ucode = 0x10, }, { .uname = "BUFFER_BIT_5", .udesc = "Buffer entry index bit 5", .ucode = 0x20, }, { .uname = "BUFFER_BIT_6", .udesc = "Buffer entry index bit 6", .ucode = 0x40, }, { .uname = "BUFFER_BIT_7", .udesc = "Buffer entry index bit 7", .ucode = 0x80, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xff, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam15h_system_read_responses[]={ { .uname = "EXCLUSIVE", .udesc = "Exclusive", .ucode = 0x1, }, { .uname = "MODIFIED", .udesc = "Modified (D18F0x68[ATMModeEn]==0), Modified written (D18F0x68[ATMModeEn]==1)", .ucode = 0x2, }, { .uname = "SHARED", .udesc = "Shared", .ucode = 0x4, }, { .uname = "OWNED", .udesc = "Owned", .ucode = 0x8, }, { .uname = "DATA_ERROR", .udesc = "Data Error", .ucode = 0x10, }, { .uname = "MODIFIED_UNWRITTEN", .udesc = "Modified unwritten", .ucode = 0x20, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam15h_octword_write_transfers[]={ { .uname = "OCTWORD_WRITE_TRANSFER", .udesc = "OW write transfer", .ucode = 0x1, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x1, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam15h_requests_to_l2[]={ { .uname = "INSTRUCTIONS", .udesc = "IC fill", .ucode = 0x1, }, { .uname = "DATA", .udesc = "DC fill", .ucode = 0x2, }, { .uname = "TLB_WALK", .udesc = "TLB fill (page table walks)", .ucode = 0x4, }, { .uname = "SNOOP", .udesc = "NB probe request", .ucode = 0x8, }, { .uname = "CANCELLED", .udesc = "Canceled request", .ucode = 0x10, }, { .uname = "PREFETCHER", .udesc = "L2 cache prefetcher request", .ucode = 0x40, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x5f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam15h_l2_cache_miss[]={ { .uname = "INSTRUCTIONS", .udesc = "IC fill", .ucode = 0x1, }, { .uname = "DATA", .udesc = "DC fill (includes possible replays, whereas PMCx041 does not)", .ucode = 0x2, }, { .uname = "TLB_WALK", .udesc = "TLB page table walk", .ucode = 0x4, }, { .uname = "PREFETCHER", .udesc = "L2 Cache Prefetcher request", .ucode = 0x10, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x17, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam15h_l2_cache_fill_writeback[]={ { .uname = "L2_FILLS", .udesc = "L2 fills from system", .ucode = 0x1, }, { .uname = "L2_WRITEBACKS", .udesc = "L2 Writebacks to system (Clean and Dirty)", .ucode = 0x2, }, { .uname = "L2_WRITEBACKS_CLEAN", .udesc = "L2 Clean Writebacks to system", .ucode = 0x4, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x7, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam15h_page_splintering[]={ { .uname = "GUEST_LARGER", .udesc = "Guest page size is larger than host page size when nested paging is enabled", .ucode = 0x1, }, { .uname = "MTRR_MISMATCH", .udesc = "Splintering due to MTRRs, IORRs, APIC, TOMs or other special address region", .ucode = 0x2, }, { .uname = "HOST_LARGER", .udesc = "Host page size is larger than the guest page size", .ucode = 0x4, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x7, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam15h_l1_itlb_miss_and_l2_itlb_miss[]={ { .uname = "4K_PAGE_FETCHES", .udesc = "Instruction fetches to a 4 KB page", .ucode = 0x1, }, { .uname = "2M_PAGE_FETCHES", .udesc = "Instruction fetches to a 2 MB page", .ucode = 0x2, }, { .uname = "1G_PAGE_FETCHES", .udesc = "Instruction fetches to a 1 GB page", .ucode = 0x4, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x7, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam15h_instruction_cache_invalidated[]={ { .uname = "NON_SMC_PROBE_MISS", .udesc = "Non-SMC invalidating probe that missed on in-flight instructions", .ucode = 0x1, }, { .uname = "NON_SMC_PROBE_HIT", .udesc = "Non-SMC invalidating probe that hit on in-flight instructions", .ucode = 0x2, }, { .uname = "SMC_PROBE_MISS", .udesc = "SMC invalidating probe that missed on in-flight instructions", .ucode = 0x4, }, { .uname = "SMC_PROBE_HIT", .udesc = "SMC invalidating probe that hit on in-flight instructions", .ucode = 0x8, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xf, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam15h_retired_mmx_fp_instructions[]={ { .uname = "X87", .udesc = "X87 instructions", .ucode = 0x1, }, { .uname = "MMX", .udesc = "MMX(tm) instructions", .ucode = 0x2, }, { .uname = "SSE", .udesc = "SSE instructions (SSE,SSE2,SSE3,SSSE3,SSE4A,SSE4.1,SSE4.2,AVX,XOP,FMA4)", .ucode = 0x4, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x7, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam15h_fpu_exceptions[]={ { .uname = "TOTAL_FAULTS", .udesc = "Total microfaults", .ucode = 0x1, }, { .uname = "TOTAL_TRAPS", .udesc = "Total microtraps", .ucode = 0x2, }, { .uname = "INT2EXT_FAULTS", .udesc = "Int2Ext faults", .ucode = 0x4, }, { .uname = "EXT2INT_FAULTS", .udesc = "Ext2Int faults", .ucode = 0x8, }, { .uname = "BYPASS_FAULTS", .udesc = "Bypass faults", .ucode = 0x10, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x1f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam15h_ibs_ops_tagged[]={ { .uname = "TAGGED", .udesc = "Number of ops tagged by IBS", .ucode = 0x1, }, { .uname = "RETIRED", .udesc = "Number of ops tagged by IBS that retired", .ucode = 0x2, }, { .uname = "IGNORED", .udesc = "Number of times an op could not be tagged by IBS because of a previous tagged op that has not retired", .ucode = 0x4, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x7, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam15h_ls_dispatch[]={ { .uname = "LOADS", .udesc = "Loads", .ucode = 0x1, }, { .uname = "STORES", .udesc = "Stores", .ucode = 0x2, }, { .uname = "LOAD_OP_STORES", .udesc = "Load-op-Stores", .ucode = 0x4, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x7, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam15h_l2_prefetcher_trigger_events[]={ { .uname = "LOAD_L1_MISS_SEEN_BY_PREFETCHER", .udesc = "Load L1 miss seen by prefetcher", .ucode = 0x1, }, { .uname = "STORE_L1_MISS_SEEN_BY_PREFETCHER", .udesc = "Store L1 miss seen by prefetcher", .ucode = 0x2, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_entry_t amd64_fam15h_pe[]={ { .name = "DISPATCHED_FPU_OPS", .desc = "FPU Pipe Assignment", .modmsk = AMD64_FAM15H_ATTRS, .code = 0x0, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_dispatched_fpu_ops), .ngrp = 1, .umasks = amd64_fam15h_dispatched_fpu_ops, }, { .name = "CYCLES_FPU_EMPTY", .desc = "FP Scheduler Empty", .modmsk = AMD64_FAM15H_ATTRS, .code = 0x1, }, { .name = "RETIRED_SSE_OPS", .desc = "Retired SSE/BNI Ops", .modmsk = AMD64_FAM15H_ATTRS, .code = 0x3, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_retired_sse_ops), .ngrp = 1, .umasks = amd64_fam15h_retired_sse_ops, }, { .name = "MOVE_SCALAR_OPTIMIZATION", .desc = "Number of Move Elimination and Scalar Op Optimization", .modmsk = AMD64_FAM15H_ATTRS, .code = 0x4, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_move_scalar_optimization), .ngrp = 1, .umasks = amd64_fam15h_move_scalar_optimization, }, { .name = "RETIRED_SERIALIZING_OPS", .desc = "Retired Serializing Ops", .modmsk = AMD64_FAM15H_ATTRS, .code = 0x5, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_retired_serializing_ops), .ngrp = 1, .umasks = amd64_fam15h_retired_serializing_ops, }, { .name = "BOTTOM_EXECUTE_OP", .desc = "Number of Cycles that a Bottom-Execute uop is in the FP Scheduler", .modmsk = AMD64_FAM15H_ATTRS, .code = 0x6, }, { .name = "SEGMENT_REGISTER_LOADS", .desc = "Segment Register Loads", .modmsk = AMD64_FAM15H_ATTRS, .code = 0x20, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_segment_register_loads), .ngrp = 1, .umasks = amd64_fam15h_segment_register_loads, }, { .name = "PIPELINE_RESTART_DUE_TO_SELF_MODIFYING_CODE", .desc = "Pipeline Restart Due to Self-Modifying Code", .modmsk = AMD64_FAM15H_ATTRS, .code = 0x21, }, { .name = "PIPELINE_RESTART_DUE_TO_PROBE_HIT", .desc = "Pipeline Restart Due to Probe Hit", .modmsk = AMD64_FAM15H_ATTRS, .code = 0x22, }, { .name = "LOAD_Q_STORE_Q_FULL", .desc = "Load Queue/Store Queue Full", .modmsk = AMD64_FAM15H_ATTRS, .code = 0x23, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_load_q_store_q_full), .ngrp = 1, .umasks = amd64_fam15h_load_q_store_q_full, }, { .name = "LOCKED_OPS", .desc = "Locked Operations", .modmsk = AMD64_FAM15H_ATTRS, .code = 0x24, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_locked_ops), .ngrp = 1, .umasks = amd64_fam15h_locked_ops, }, { .name = "RETIRED_CLFLUSH_INSTRUCTIONS", .desc = "Retired CLFLUSH Instructions", .modmsk = AMD64_FAM15H_ATTRS, .code = 0x26, }, { .name = "RETIRED_CPUID_INSTRUCTIONS", .desc = "Retired CPUID Instructions", .modmsk = AMD64_FAM15H_ATTRS, .code = 0x27, }, { .name = "CANCELLED_STORE_TO_LOAD", .desc = "Canceled Store to Load Forward Operations", .modmsk = AMD64_FAM15H_ATTRS, .code = 0x2a, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_cancelled_store_to_load), .ngrp = 1, .umasks = amd64_fam15h_cancelled_store_to_load, }, { .name = "SMIS_RECEIVED", .desc = "SMIs Received", .modmsk = AMD64_FAM15H_ATTRS, .code = 0x2b, }, { .name = "DATA_CACHE_ACCESSES", .desc = "Data Cache Accesses", .modmsk = AMD64_FAM15H_ATTRS, .code = 0x40, }, { .name = "DATA_CACHE_MISSES", .desc = "Data Cache Misses", .modmsk = AMD64_FAM15H_ATTRS, .code = 0x41, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_data_cache_misses), .ngrp = 1, .umasks = amd64_fam15h_data_cache_misses, }, { .name = "DATA_CACHE_REFILLS_FROM_L2_OR_NORTHBRIDGE", .desc = "Data Cache Refills from L2 or System", .modmsk = AMD64_FAM15H_ATTRS, .code = 0x42, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_data_cache_refills_from_l2_or_northbridge), .ngrp = 1, .umasks = amd64_fam15h_data_cache_refills_from_l2_or_northbridge, }, { .name = "DATA_CACHE_REFILLS_FROM_NORTHBRIDGE", .desc = "Data Cache Refills from System", .modmsk = AMD64_FAM15H_ATTRS, .code = 0x43, }, { .name = "UNIFIED_TLB_HIT", .desc = "Unified TLB Hit", .modmsk = AMD64_FAM15H_ATTRS, .code = 0x45, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_unified_tlb_hit), .ngrp = 1, .umasks = amd64_fam15h_unified_tlb_hit, }, { .name = "UNIFIED_TLB_MISS", .desc = "Unified TLB Miss", .modmsk = AMD64_FAM15H_ATTRS, .code = 0x46, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_unified_tlb_miss), .ngrp = 1, .umasks = amd64_fam15h_unified_tlb_miss, }, { .name = "MISALIGNED_ACCESSES", .desc = "Misaligned Accesses", .modmsk = AMD64_FAM15H_ATTRS, .code = 0x47, }, { .name = "PREFETCH_INSTRUCTIONS_DISPATCHED", .desc = "Prefetch Instructions Dispatched", .modmsk = AMD64_FAM15H_ATTRS, .code = 0x4b, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_prefetch_instructions_dispatched), .ngrp = 1, .umasks = amd64_fam15h_prefetch_instructions_dispatched, }, { .name = "INEFFECTIVE_SW_PREFETCHES", .desc = "Ineffective Software Prefetches", .modmsk = AMD64_FAM15H_ATTRS, .code = 0x52, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_ineffective_sw_prefetches), .ngrp = 1, .umasks = amd64_fam15h_ineffective_sw_prefetches, }, { .name = "MEMORY_REQUESTS", .desc = "Memory Requests by Type", .modmsk = AMD64_FAM15H_ATTRS, .code = 0x65, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_memory_requests), .ngrp = 1, .umasks = amd64_fam15h_memory_requests, }, { .name = "DATA_PREFETCHER", .desc = "Data Prefetcher", .modmsk = AMD64_FAM15H_ATTRS, .code = 0x67, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_data_prefetcher), .ngrp = 1, .umasks = amd64_fam15h_data_prefetcher, }, { .name = "MAB_REQS", .desc = "MAB Requests", .modmsk = AMD64_FAM15H_ATTRS, .code = 0x68, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_mab_reqs), .ngrp = 1, .umasks = amd64_fam15h_mab_reqs, }, { .name = "MAB_WAIT", .desc = "MAB Wait Cycles", .modmsk = AMD64_FAM15H_ATTRS, .code = 0x69, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_mab_reqs), .ngrp = 1, .umasks = amd64_fam15h_mab_reqs, /* identical to actual umasks list for this event */ }, { .name = "SYSTEM_READ_RESPONSES", .desc = "Response From System on Cache Refills", .modmsk = AMD64_FAM15H_ATTRS, .code = 0x6c, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_system_read_responses), .ngrp = 1, .umasks = amd64_fam15h_system_read_responses, }, { .name = "OCTWORD_WRITE_TRANSFERS", .desc = "Octwords Written to System", .modmsk = AMD64_FAM15H_ATTRS, .code = 0x6d, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_octword_write_transfers), .ngrp = 1, .umasks = amd64_fam15h_octword_write_transfers, }, { .name = "CPU_CLK_UNHALTED", .desc = "CPU Clocks not Halted", .modmsk = AMD64_FAM15H_ATTRS, .code = 0x76, }, { .name = "REQUESTS_TO_L2", .desc = "Requests to L2 Cache", .modmsk = AMD64_FAM15H_ATTRS, .code = 0x7d, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_requests_to_l2), .ngrp = 1, .umasks = amd64_fam15h_requests_to_l2, }, { .name = "L2_CACHE_MISS", .desc = "L2 Cache Misses", .modmsk = AMD64_FAM15H_ATTRS, .code = 0x7e, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_l2_cache_miss), .ngrp = 1, .umasks = amd64_fam15h_l2_cache_miss, }, { .name = "L2_CACHE_FILL_WRITEBACK", .desc = "L2 Fill/Writeback", .modmsk = AMD64_FAM15H_ATTRS, .code = 0x7f, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_l2_cache_fill_writeback), .ngrp = 1, .umasks = amd64_fam15h_l2_cache_fill_writeback, }, { .name = "PAGE_SPLINTERING", .desc = "Page Splintering", .modmsk = AMD64_FAM15H_ATTRS, .code = 0x165, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_page_splintering), .ngrp = 1, .umasks = amd64_fam15h_page_splintering, }, { .name = "INSTRUCTION_CACHE_FETCHES", .desc = "Instruction Cache Fetches", .modmsk = AMD64_FAM15H_ATTRS, .code = 0x80, }, { .name = "INSTRUCTION_CACHE_MISSES", .desc = "Instruction Cache Misses", .modmsk = AMD64_FAM15H_ATTRS, .code = 0x81, }, { .name = "INSTRUCTION_CACHE_REFILLS_FROM_L2", .desc = "Instruction Cache Refills from L2", .modmsk = AMD64_FAM15H_ATTRS, .code = 0x82, }, { .name = "INSTRUCTION_CACHE_REFILLS_FROM_SYSTEM", .desc = "Instruction Cache Refills from System", .modmsk = AMD64_FAM15H_ATTRS, .code = 0x83, }, { .name = "L1_ITLB_MISS_AND_L2_ITLB_HIT", .desc = "L1 ITLB Miss, L2 ITLB Hit", .modmsk = AMD64_FAM15H_ATTRS, .code = 0x84, }, { .name = "L1_ITLB_MISS_AND_L2_ITLB_MISS", .desc = "L1 ITLB Miss, L2 ITLB Miss", .modmsk = AMD64_FAM15H_ATTRS, .code = 0x85, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_l1_itlb_miss_and_l2_itlb_miss), .ngrp = 1, .umasks = amd64_fam15h_l1_itlb_miss_and_l2_itlb_miss, }, { .name = "PIPELINE_RESTART_DUE_TO_INSTRUCTION_STREAM_PROBE", .desc = "Pipeline Restart Due to Instruction Stream Probe", .modmsk = AMD64_FAM15H_ATTRS, .code = 0x86, }, { .name = "INSTRUCTION_FETCH_STALL", .desc = "Instruction Fetch Stall", .modmsk = AMD64_FAM15H_ATTRS, .code = 0x87, }, { .name = "RETURN_STACK_HITS", .desc = "Return Stack Hits", .modmsk = AMD64_FAM15H_ATTRS, .code = 0x88, }, { .name = "RETURN_STACK_OVERFLOWS", .desc = "Return Stack Overflows", .modmsk = AMD64_FAM15H_ATTRS, .code = 0x89, }, { .name = "INSTRUCTION_CACHE_VICTIMS", .desc = "Instruction Cache Victims", .modmsk = AMD64_FAM15H_ATTRS, .code = 0x8b, }, { .name = "INSTRUCTION_CACHE_INVALIDATED", .desc = "Instruction Cache Lines Invalidated", .modmsk = AMD64_FAM15H_ATTRS, .code = 0x8c, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_instruction_cache_invalidated), .ngrp = 1, .umasks = amd64_fam15h_instruction_cache_invalidated, }, { .name = "ITLB_RELOADS", .desc = "ITLB Reloads", .modmsk = AMD64_FAM15H_ATTRS, .code = 0x99, }, { .name = "ITLB_RELOADS_ABORTED", .desc = "ITLB Reloads Aborted", .modmsk = AMD64_FAM15H_ATTRS, .code = 0x9a, }, { .name = "RETIRED_INSTRUCTIONS", .desc = "Retired Instructions", .modmsk = AMD64_FAM15H_ATTRS, .code = 0xc0, }, { .name = "RETIRED_UOPS", .desc = "Retired uops", .modmsk = AMD64_FAM15H_ATTRS, .code = 0xc1, }, { .name = "RETIRED_BRANCH_INSTRUCTIONS", .desc = "Retired Branch Instructions", .modmsk = AMD64_FAM15H_ATTRS, .code = 0xc2, }, { .name = "RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS", .desc = "Retired Mispredicted Branch Instructions", .modmsk = AMD64_FAM15H_ATTRS, .code = 0xc3, }, { .name = "RETIRED_TAKEN_BRANCH_INSTRUCTIONS", .desc = "Retired Taken Branch Instructions", .modmsk = AMD64_FAM15H_ATTRS, .code = 0xc4, }, { .name = "RETIRED_TAKEN_BRANCH_INSTRUCTIONS_MISPREDICTED", .desc = "Retired Taken Branch Instructions Mispredicted", .modmsk = AMD64_FAM15H_ATTRS, .code = 0xc5, }, { .name = "RETIRED_FAR_CONTROL_TRANSFERS", .desc = "Retired Far Control Transfers", .modmsk = AMD64_FAM15H_ATTRS, .code = 0xc6, }, { .name = "RETIRED_BRANCH_RESYNCS", .desc = "Retired Branch Resyncs", .modmsk = AMD64_FAM15H_ATTRS, .code = 0xc7, }, { .name = "RETIRED_NEAR_RETURNS", .desc = "Retired Near Returns", .modmsk = AMD64_FAM15H_ATTRS, .code = 0xc8, }, { .name = "RETIRED_NEAR_RETURNS_MISPREDICTED", .desc = "Retired Near Returns Mispredicted", .modmsk = AMD64_FAM15H_ATTRS, .code = 0xc9, }, { .name = "RETIRED_INDIRECT_BRANCHES_MISPREDICTED", .desc = "Retired Indirect Branches Mispredicted", .modmsk = AMD64_FAM15H_ATTRS, .code = 0xca, }, { .name = "RETIRED_MMX_FP_INSTRUCTIONS", .desc = "Retired MMX/FP Instructions", .modmsk = AMD64_FAM15H_ATTRS, .code = 0xcb, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_retired_mmx_fp_instructions), .ngrp = 1, .umasks = amd64_fam15h_retired_mmx_fp_instructions, }, { .name = "INTERRUPTS_MASKED_CYCLES", .desc = "Interrupts-Masked Cycles", .modmsk = AMD64_FAM15H_ATTRS, .code = 0xcd, }, { .name = "INTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDING", .desc = "Interrupts-Masked Cycles with Interrupt Pending", .modmsk = AMD64_FAM15H_ATTRS, .code = 0xce, }, { .name = "INTERRUPTS_TAKEN", .desc = "Interrupts Taken", .modmsk = AMD64_FAM15H_ATTRS, .code = 0xcf, }, { .name = "DECODER_EMPTY", .desc = "Decoder Empty", .modmsk = AMD64_FAM15H_ATTRS, .code = 0xd0, }, { .name = "DISPATCH_STALLS", .desc = "Dispatch Stalls", .modmsk = AMD64_FAM15H_ATTRS, .code = 0xd1, }, { .name = "DISPATCH_STALL_FOR_SERIALIZATION", .desc = "Microsequencer Stall due to Serialization", .modmsk = AMD64_FAM15H_ATTRS, .code = 0xd3, }, { .name = "DISPATCH_STALL_FOR_RETIRE_QUEUE_FULL", .desc = "Dispatch Stall for Instruction Retire Q Full", .modmsk = AMD64_FAM15H_ATTRS, .code = 0xd5, }, { .name = "DISPATCH_STALL_FOR_INT_SCHED_QUEUE_FULL", .desc = "Dispatch Stall for Integer Scheduler Queue Full", .modmsk = AMD64_FAM15H_ATTRS, .code = 0xd6, }, { .name = "DISPATCH_STALL_FOR_FPU_FULL", .desc = "Dispatch Stall for FP Scheduler Queue Full", .modmsk = AMD64_FAM15H_ATTRS, .code = 0xd7, }, { .name = "DISPATCH_STALL_FOR_LDQ_FULL", .desc = "Dispatch Stall for LDQ Full", .modmsk = AMD64_FAM15H_ATTRS, .code = 0xd8, }, { .name = "MICROSEQ_STALL_WAITING_FOR_ALL_QUIET", .desc = "Microsequencer Stall Waiting for All Quiet", .modmsk = AMD64_FAM15H_ATTRS, .code = 0xd9, }, { .name = "FPU_EXCEPTIONS", .desc = "FPU Exceptions", .modmsk = AMD64_FAM15H_ATTRS, .code = 0xdb, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_fpu_exceptions), .ngrp = 1, .umasks = amd64_fam15h_fpu_exceptions, }, { .name = "DR0_BREAKPOINTS", .desc = "DR0 Breakpoint Match", .modmsk = AMD64_FAM15H_ATTRS, .code = 0xdc, }, { .name = "DR1_BREAKPOINTS", .desc = "DR1 Breakpoint Match", .modmsk = AMD64_FAM15H_ATTRS, .code = 0xdd, }, { .name = "DR2_BREAKPOINTS", .desc = "DR2 Breakpoint Match", .modmsk = AMD64_FAM15H_ATTRS, .code = 0xde, }, { .name = "DR3_BREAKPOINTS", .desc = "DR3 Breakpoint Match", .modmsk = AMD64_FAM15H_ATTRS, .code = 0xdf, }, { .name = "IBS_OPS_TAGGED", .desc = "Tagged IBS Ops", .modmsk = AMD64_FAM15H_ATTRS, .code = 0x1cf, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_ibs_ops_tagged), .ngrp = 1, .umasks = amd64_fam15h_ibs_ops_tagged, }, { .name = "LS_DISPATCH", .desc = "LS Dispatch", .modmsk = AMD64_FAM15H_ATTRS, .code = 0x29, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_ls_dispatch), .ngrp = 1, .umasks = amd64_fam15h_ls_dispatch, }, { .name = "EXECUTED_CLFLUSH_INSTRUCTIONS", .desc = "Executed CLFLUSH Instructions", .modmsk = AMD64_FAM15H_ATTRS, .code = 0x30, }, { .name = "L2_PREFETCHER_TRIGGER_EVENTS", .desc = "L2 Prefetcher Trigger Events", .modmsk = AMD64_FAM15H_ATTRS, .code = 0x16c, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_l2_prefetcher_trigger_events), .ngrp = 1, .umasks = amd64_fam15h_l2_prefetcher_trigger_events, }, { .name = "DISPATCH_STALL_FOR_STQ_FULL", .desc = "Dispatch Stall for STQ Full", .modmsk = AMD64_FAM15H_ATTRS, .code = 0x1d8, }, }; libpfm-4.9.0/lib/events/arm_cortex_a57_events.h0000664000175000017500000002645113223402656021254 0ustar eranianeranian/* * Copyright (c) 2014 Google Inc. All rights reserved * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * Cortex A57 r1p1 * based on Table 11-24 from the "Cortex A57 Technical Reference Manual" */ static const arm_entry_t arm_cortex_a57_pe[]={ {.name = "SW_INCR", .modmsk = ARMV8_ATTRS, .code = 0x00, .desc = "Instruction architecturally executed (condition check pass) Software increment" }, {.name = "L1I_CACHE_REFILL", .modmsk = ARMV8_ATTRS, .code = 0x01, .desc = "Level 1 instruction cache refill" }, {.name = "L1I_TLB_REFILL", .modmsk = ARMV8_ATTRS, .code = 0x02, .desc = "Level 1 instruction TLB refill" }, {.name = "L1D_CACHE_REFILL", .modmsk = ARMV8_ATTRS, .code = 0x03, .desc = "Level 1 data cache refill" }, {.name = "L1D_CACHE_ACCESS", .modmsk = ARMV8_ATTRS, .code = 0x04, .desc = "Level 1 data cache access" }, {.name = "L1D_TLB_REFILL", .modmsk = ARMV8_ATTRS, .code = 0x05, .desc = "Level 1 data TLB refill" }, {.name = "INST_RETIRED", .modmsk = ARMV8_ATTRS, .code = 0x08, .desc = "Instruction architecturally executed" }, {.name = "EXCEPTION_TAKEN", .modmsk = ARMV8_ATTRS, .code = 0x09, .desc = "Exception taken" }, {.name = "EXCEPTION_RETURN", .modmsk = ARMV8_ATTRS, .code = 0x0a, .desc = "Instruction architecturally executed (condition check pass) Exception return" }, {.name = "CID_WRITE_RETIRED", .modmsk = ARMV8_ATTRS, .code = 0x0b, .desc = "Instruction architecturally executed (condition check pass) Write to CONTEXTIDR" }, {.name = "BRANCH_MISPRED", .modmsk = ARMV8_ATTRS, .code = 0x10, .desc = "Mispredicted or not predicted branch speculatively executed" }, {.name = "CPU_CYCLES", .modmsk = ARMV8_ATTRS, .code = 0x11, .desc = "Cycles" }, {.name = "BRANCH_PRED", .modmsk = ARMV8_ATTRS, .code = 0x12, .desc = "Predictable branch speculatively executed" }, {.name = "DATA_MEM_ACCESS", .modmsk = ARMV8_ATTRS, .code = 0x13, .desc = "Data memory access" }, {.name = "L1I_CACHE_ACCESS", .modmsk = ARMV8_ATTRS, .code = 0x14, .desc = "Level 1 instruction cache access" }, {.name = "L1D_CACHE_WB", .modmsk = ARMV8_ATTRS, .code = 0x15, .desc = "Level 1 data cache WriteBack" }, {.name = "L2D_CACHE_ACCESS", .modmsk = ARMV8_ATTRS, .code = 0x16, .desc = "Level 2 data cache access" }, {.name = "L2D_CACHE_REFILL", .modmsk = ARMV8_ATTRS, .code = 0x17, .desc = "Level 2 data cache refill" }, {.name = "L2D_CACHE_WB", .modmsk = ARMV8_ATTRS, .code = 0x18, .desc = "Level 2 data cache WriteBack" }, {.name = "BUS_ACCESS", .modmsk = ARMV8_ATTRS, .code = 0x19, .desc = "Bus access" }, {.name = "LOCAL_MEMORY_ERROR", .modmsk = ARMV8_ATTRS, .code = 0x1a, .desc = "Local memory error" }, {.name = "INST_SPEC_EXEC", .modmsk = ARMV8_ATTRS, .code = 0x1b, .desc = "Instruction speculatively executed" }, {.name = "TTBR_WRITE_RETIRED", .modmsk = ARMV8_ATTRS, .code = 0x1c, .desc = "Instruction architecturally executed (condition check pass) Write to translation table base" }, {.name = "BUS_CYCLES", .modmsk = ARMV8_ATTRS, .code = 0x1d, .desc = "Bus cycle" }, {.name = "L1D_READ_ACCESS", .modmsk = ARMV8_ATTRS, .code = 0x40, .desc = "Level 1 data cache read access" }, {.name = "L1D_WRITE_ACCESS", .modmsk = ARMV8_ATTRS, .code = 0x41, .desc = "Level 1 data cache write access" }, {.name = "L1D_READ_REFILL", .modmsk = ARMV8_ATTRS, .code = 0x42, .desc = "Level 1 data cache read refill" }, {.name = "L1D_WRITE_REFILL", .modmsk = ARMV8_ATTRS, .code = 0x43, .desc = "Level 1 data cache write refill" }, {.name = "L1D_WB_VICTIM", .modmsk = ARMV8_ATTRS, .code = 0x46, .desc = "Level 1 data cache writeback victim" }, {.name = "L1D_WB_CLEAN_COHERENCY", .modmsk = ARMV8_ATTRS, .code = 0x47, .desc = "Level 1 data cache writeback cleaning and coherency" }, {.name = "L1D_INVALIDATE", .modmsk = ARMV8_ATTRS, .code = 0x48, .desc = "Level 1 data cache invalidate" }, {.name = "L1D_TLB_READ_REFILL", .modmsk = ARMV8_ATTRS, .code = 0x4c, .desc = "Level 1 data TLB read refill" }, {.name = "L1D_TLB_WRITE_REFILL", .modmsk = ARMV8_ATTRS, .code = 0x4d, .desc = "Level 1 data TLB write refill" }, {.name = "L2D_READ_ACCESS", .modmsk = ARMV8_ATTRS, .code = 0x50, .desc = "Level 2 data cache read access" }, {.name = "L2D_WRITE_ACCESS", .modmsk = ARMV8_ATTRS, .code = 0x51, .desc = "Level 2 data cache write access" }, {.name = "L2D_READ_REFILL", .modmsk = ARMV8_ATTRS, .code = 0x52, .desc = "Level 2 data cache read refill" }, {.name = "L2D_WRITE_REFILL", .modmsk = ARMV8_ATTRS, .code = 0x53, .desc = "Level 2 data cache write refill" }, {.name = "L2D_WB_VICTIM", .modmsk = ARMV8_ATTRS, .code = 0x56, .desc = "Level 2 data cache writeback victim" }, {.name = "L2D_WB_CLEAN_COHERENCY", .modmsk = ARMV8_ATTRS, .code = 0x57, .desc = "Level 2 data cache writeback cleaning and coherency" }, {.name = "L2D_INVALIDATE", .modmsk = ARMV8_ATTRS, .code = 0x58, .desc = "Level 2 data cache invalidate" }, {.name = "BUS_READ_ACCESS", .modmsk = ARMV8_ATTRS, .code = 0x60, .desc = "Bus read access" }, {.name = "BUS_WRITE_ACCESS", .modmsk = ARMV8_ATTRS, .code = 0x61, .desc = "Bus write access" }, {.name = "BUS_NORMAL_ACCESS", .modmsk = ARMV8_ATTRS, .code = 0x62, .desc = "Bus normal access" }, {.name = "BUS_NOT_NORMAL_ACCESS", .modmsk = ARMV8_ATTRS, .code = 0x63, .desc = "Bus not normal access" }, {.name = "BUS_NORMAL_ACCESS_2", .modmsk = ARMV8_ATTRS, .code = 0x64, .desc = "Bus normal access" }, {.name = "BUS_PERIPH_ACCESS", .modmsk = ARMV8_ATTRS, .code = 0x65, .desc = "Bus peripheral access" }, {.name = "DATA_MEM_READ_ACCESS", .modmsk = ARMV8_ATTRS, .code = 0x66, .desc = "Data memory read access" }, {.name = "DATA_MEM_WRITE_ACCESS", .modmsk = ARMV8_ATTRS, .code = 0x67, .desc = "Data memory write access" }, {.name = "UNALIGNED_READ_ACCESS", .modmsk = ARMV8_ATTRS, .code = 0x68, .desc = "Unaligned read access" }, {.name = "UNALIGNED_WRITE_ACCESS", .modmsk = ARMV8_ATTRS, .code = 0x69, .desc = "Unaligned read access" }, {.name = "UNALIGNED_ACCESS", .modmsk = ARMV8_ATTRS, .code = 0x6a, .desc = "Unaligned access" }, {.name = "INST_SPEC_EXEC_LDREX", .modmsk = ARMV8_ATTRS, .code = 0x6c, .desc = "LDREX exclusive instruction speculatively executed" }, {.name = "INST_SPEC_EXEC_STREX_PASS", .modmsk = ARMV8_ATTRS, .code = 0x6d, .desc = "STREX pass exclusive instruction speculatively executed" }, {.name = "INST_SPEC_EXEC_STREX_FAIL", .modmsk = ARMV8_ATTRS, .code = 0x6e, .desc = "STREX fail exclusive instruction speculatively executed" }, {.name = "INST_SPEC_EXEC_LOAD", .modmsk = ARMV8_ATTRS, .code = 0x70, .desc = "Load instruction speculatively executed" }, {.name = "INST_SPEC_EXEC_STORE", .modmsk = ARMV8_ATTRS, .code = 0x71, .desc = "Store instruction speculatively executed" }, {.name = "INST_SPEC_EXEC_LOAD_STORE", .modmsk = ARMV8_ATTRS, .code = 0x72, .desc = "Load or store instruction speculatively executed" }, {.name = "INST_SPEC_EXEC_INTEGER_INST", .modmsk = ARMV8_ATTRS, .code = 0x73, .desc = "Integer data processing instruction speculatively executed" }, {.name = "INST_SPEC_EXEC_SIMD", .modmsk = ARMV8_ATTRS, .code = 0x74, .desc = "Advanced SIMD instruction speculatively executed" }, {.name = "INST_SPEC_EXEC_VFP", .modmsk = ARMV8_ATTRS, .code = 0x75, .desc = "VFP instruction speculatively executed" }, {.name = "INST_SPEC_EXEC_SOFT_PC", .modmsk = ARMV8_ATTRS, .code = 0x76, .desc = "Software of the PC instruction speculatively executed" }, {.name = "BRANCH_SPEC_EXEC_IMM_BRANCH", .modmsk = ARMV8_ATTRS, .code = 0x78, .desc = "Immediate branch speculatively executed" }, {.name = "BRANCH_SPEC_EXEC_RET", .modmsk = ARMV8_ATTRS, .code = 0x79, .desc = "Return branch speculatively executed" }, {.name = "BRANCH_SPEC_EXEC_IND", .modmsk = ARMV8_ATTRS, .code = 0x7a, .desc = "Indirect branch speculatively executed" }, {.name = "BARRIER_SPEC_EXEC_ISB", .modmsk = ARMV8_ATTRS, .code = 0x7c, .desc = "ISB barrier speculatively executed" }, {.name = "BARRIER_SPEC_EXEC_DSB", .modmsk = ARMV8_ATTRS, .code = 0x7d, .desc = "DSB barrier speculatively executed" }, {.name = "BARRIER_SPEC_EXEC_DMB", .modmsk = ARMV8_ATTRS, .code = 0x7e, .desc = "DMB barrier speculatively executed" }, {.name = "EXCEPTION_UNDEF", .modmsk = ARMV8_ATTRS, .code = 0x81, .desc = "Exception taken, other synchronous" }, {.name = "EXCEPTION_SVC", .modmsk = ARMV8_ATTRS, .code = 0x82, .desc = "Exception taken, supervisor call" }, {.name = "EXCEPTION_PABORT", .modmsk = ARMV8_ATTRS, .code = 0x83, .desc = "Exception taken, instruction abort" }, {.name = "EXCEPTION_DABORT", .modmsk = ARMV8_ATTRS, .code = 0x84, .desc = "Exception taken, data abort or SError" }, {.name = "EXCEPTION_IRQ", .modmsk = ARMV8_ATTRS, .code = 0x86, .desc = "Exception taken, irq" }, {.name = "EXCEPTION_FIQ", .modmsk = ARMV8_ATTRS, .code = 0x87, .desc = "Exception taken, irq" }, {.name = "EXCEPTION_SMC", .modmsk = ARMV8_ATTRS, .code = 0x88, .desc = "Exception taken, secure monitor call" }, {.name = "EXCEPTION_HVC", .modmsk = ARMV8_ATTRS, .code = 0x8a, .desc = "Exception taken, hypervisor call" }, {.name = "EXCEPTION_TRAP_PABORT", .modmsk = ARMV8_ATTRS, .code = 0x8b, .desc = "Exception taken, instruction abort not taken locally" }, {.name = "EXCEPTION_TRAP_DABORT", .modmsk = ARMV8_ATTRS, .code = 0x8c, .desc = "Exception taken, data abort or SError not taken locally" }, {.name = "EXCEPTION_TRAP_OTHER", .modmsk = ARMV8_ATTRS, .code = 0x8d, .desc = "Exception taken, other traps not taken locally" }, {.name = "EXCEPTION_TRAP_IRQ", .modmsk = ARMV8_ATTRS, .code = 0x8e, .desc = "Exception taken, irq not taken locally" }, {.name = "EXCEPTION_TRAP_FIQ", .modmsk = ARMV8_ATTRS, .code = 0x8f, .desc = "Exception taken, fiq not taken locally" }, {.name = "RC_LD_SPEC", .modmsk = ARMV8_ATTRS, .code = 0x90, .desc = "Release consistency instruction speculatively executed (load-acquire)", }, {.name = "RC_ST_SPEC", .modmsk = ARMV8_ATTRS, .code = 0x91, .desc = "Release consistency instruction speculatively executed (store-release)", }, /* END Cortex A47 specific events */ }; libpfm-4.9.0/lib/events/intel_pii_events.h0000664000175000017500000005530313223402656020407 0ustar eranianeranian/* * Copyright (c) 2011 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * This file has been automatically generated. * * PMU: pii (Intel Pentium II) */ static const intel_x86_umask_t pii_l2_ifetch[]={ { .uname = "I", .udesc = "Invalid state", .ucode = 0x100, }, { .uname = "S", .udesc = "Shared state", .ucode = 0x200, }, { .uname = "E", .udesc = "Exclusive state", .ucode = 0x400, }, { .uname = "M", .udesc = "Modified state", .ucode = 0x800, }, }; static const intel_x86_umask_t pii_bus_drdy_clocks[]={ { .uname = "SELF", .udesc = "Clocks when processor is driving bus", .ucode = 0x0, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "ANY", .udesc = "Clocks when any agent is driving bus", .ucode = 0x2000, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t pii_mmx_instr_type_exec[]={ { .uname = "MUL", .udesc = "MMX packed multiply instructions executed", .ucode = 0x100, }, { .uname = "SHIFT", .udesc = "MMX packed shift instructions executed", .ucode = 0x200, }, { .uname = "PACK", .udesc = "MMX pack operation instructions executed", .ucode = 0x400, }, { .uname = "UNPACK", .udesc = "MMX unpack operation instructions executed", .ucode = 0x800, }, { .uname = "LOGICAL", .udesc = "MMX packed logical instructions executed", .ucode = 0x1000, }, { .uname = "ARITH", .udesc = "MMX packed arithmetic instructions executed", .ucode = 0x2000, }, }; static const intel_x86_umask_t pii_fp_mmx_trans[]={ { .uname = "TO_FP", .udesc = "From MMX instructions to floating-point instructions", .ucode = 0x0, .uflags= INTEL_X86_NCOMBO, }, { .uname = "TO_MMX", .udesc = "From floating-point instructions to MMX instructions", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t pii_seg_rename_stalls[]={ { .uname = "ES", .udesc = "Segment register ES", .ucode = 0x100, }, { .uname = "DS", .udesc = "Segment register DS", .ucode = 0x200, }, { .uname = "FS", .udesc = "Segment register FS", .ucode = 0x400, }, { .uname = "GS", .udesc = "Segment register GS", .ucode = 0x800, }, }; static const intel_x86_entry_t intel_pii_pe[]={ { .name = "CPU_CLK_UNHALTED", .desc = "Number cycles during which the processor is not halted", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x79, }, { .name = "INST_RETIRED", .desc = "Number of instructions retired", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xc0, }, { .name = "DATA_MEM_REFS", .desc = "All loads from any memory type. All stores to any memory typeEach part of a split is counted separately. The internal logic counts not only memory loads and stores but also internal retries. 80-bit floating point accesses are double counted, since they are decomposed into a 16-bit exponent load and a 64-bit mantissa load. Memory accesses are only counted when they are actually performed (such as a load that gets squashed because a previous cache miss is outstanding to the same address, and which finally gets performed, is only counted once). Does not include I/O accesses or other non-memory accesses", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x43, }, { .name = "DCU_LINES_IN", .desc = "Total lines allocated in the DCU", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x45, }, { .name = "DCU_M_LINES_IN", .desc = "Number of M state lines allocated in the DCU", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x46, }, { .name = "DCU_M_LINES_OUT", .desc = "Number of M state lines evicted from the DCU. This includes evictions via snoop HITM, intervention or replacement", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x47, }, { .name = "DCU_MISS_OUTSTANDING", .desc = "Weighted number of cycle while a DCU miss is outstanding, incremented by the number of cache misses at any particular time. Cacheable read requests only are considered. Uncacheable requests are excluded Read-for-ownerships are counted, as well as line fills, invalidates, and stores", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x48, }, { .name = "IFU_IFETCH", .desc = "Number of instruction fetches, both cacheable and noncacheable including UC fetches", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x80, }, { .name = "IFU_IFETCH_MISS", .desc = "Number of instruction fetch misses. All instructions fetches that do not hit the IFU (i.e., that produce memory requests). Includes UC accesses", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x81, }, { .name = "ITLB_MISS", .desc = "Number of ITLB misses", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x85, }, { .name = "IFU_MEM_STALL", .desc = "Number of cycles instruction fetch is stalled for any reason. Includes IFU cache misses, ITLB misses, ITLB faults, and other minor stalls", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x86, }, { .name = "ILD_STALL", .desc = "Number of cycles that the instruction length decoder is stalled", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x87, }, { .name = "L2_IFETCH", .desc = "Number of L2 instruction fetches. This event indicates that a normal instruction fetch was received by the L2. The count includes only L2 cacheable instruction fetches: it does not include UC instruction fetches It does not include ITLB miss accesses", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x28, .numasks = LIBPFM_ARRAY_SIZE(pii_l2_ifetch), .ngrp = 1, .umasks = pii_l2_ifetch, }, { .name = "L2_ST", .desc = "Number of L2 data stores. This event indicates that a normal, unlocked, store memory access was received by the L2. Specifically, it indicates that the DCU sent a read-for ownership request to the L2. It also includes Invalid to Modified requests sent by the DCU to the L2. It includes only L2 cacheable memory accesses; it does not include I/O accesses, other non-memory accesses, or memory accesses such as UC/WT memory accesses. It does include L2 cacheable TLB miss memory accesses", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x2a, .numasks = LIBPFM_ARRAY_SIZE(pii_l2_ifetch), .ngrp = 1, .umasks = pii_l2_ifetch, /* identical to actual umasks list for this event */ }, { .name = "L2_M_LINES_INM", .desc = "Number of modified lines allocated in the L2", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x25, }, { .name = "L2_RQSTS", .desc = "Total number of L2 requests", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x2e, .numasks = LIBPFM_ARRAY_SIZE(pii_l2_ifetch), .ngrp = 1, .umasks = pii_l2_ifetch, /* identical to actual umasks list for this event */ }, { .name = "L2_ADS", .desc = "Number of L2 address strobes", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x21, }, { .name = "L2_DBUS_BUSY", .desc = "Number of cycles during which the L2 cache data bus was busy", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x22, }, { .name = "L2_DBUS_BUSY_RD", .desc = "Number of cycles during which the data bus was busy transferring read data from L2 to the processor", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x23, }, { .name = "BUS_DRDY_CLOCKS", .desc = "Number of clocks during which DRDY# is asserted. Utilization of the external system data bus during data transfers", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x62, .numasks = LIBPFM_ARRAY_SIZE(pii_bus_drdy_clocks), .ngrp = 1, .umasks = pii_bus_drdy_clocks, }, { .name = "BUS_LOCK_CLOCKS", .desc = "Number of clocks during which LOCK# is asserted on the external system bus", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x63, .numasks = LIBPFM_ARRAY_SIZE(pii_bus_drdy_clocks), .ngrp = 1, .umasks = pii_bus_drdy_clocks, /* identical to actual umasks list for this event */ }, { .name = "BUS_REQ_OUTSTANDING", .desc = "Number of bus requests outstanding. This counter is incremented by the number of cacheable read bus requests outstanding in any given cycle", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x60, }, { .name = "BUS_TRANS_BRD", .desc = "Number of burst read transactions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x65, .numasks = LIBPFM_ARRAY_SIZE(pii_bus_drdy_clocks), .ngrp = 1, .umasks = pii_bus_drdy_clocks, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRANS_RFO", .desc = "Number of completed read for ownership transactions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x66, .numasks = LIBPFM_ARRAY_SIZE(pii_bus_drdy_clocks), .ngrp = 1, .umasks = pii_bus_drdy_clocks, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRANS_WB", .desc = "Number of completed write back transactions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x67, .numasks = LIBPFM_ARRAY_SIZE(pii_bus_drdy_clocks), .ngrp = 1, .umasks = pii_bus_drdy_clocks, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRAN_IFETCH", .desc = "Number of completed instruction fetch transactions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x68, .numasks = LIBPFM_ARRAY_SIZE(pii_bus_drdy_clocks), .ngrp = 1, .umasks = pii_bus_drdy_clocks, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRAN_INVAL", .desc = "Number of completed invalidate transactions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x69, .numasks = LIBPFM_ARRAY_SIZE(pii_bus_drdy_clocks), .ngrp = 1, .umasks = pii_bus_drdy_clocks, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRAN_PWR", .desc = "Number of completed partial write transactions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x6a, .numasks = LIBPFM_ARRAY_SIZE(pii_bus_drdy_clocks), .ngrp = 1, .umasks = pii_bus_drdy_clocks, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRANS_P", .desc = "Number of completed partial transactions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x6b, .numasks = LIBPFM_ARRAY_SIZE(pii_bus_drdy_clocks), .ngrp = 1, .umasks = pii_bus_drdy_clocks, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRANS_IO", .desc = "Number of completed I/O transactions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x6c, .numasks = LIBPFM_ARRAY_SIZE(pii_bus_drdy_clocks), .ngrp = 1, .umasks = pii_bus_drdy_clocks, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRAN_DEF", .desc = "Number of completed deferred transactions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x6d, .numasks = LIBPFM_ARRAY_SIZE(pii_bus_drdy_clocks), .ngrp = 1, .umasks = pii_bus_drdy_clocks, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRAN_BURST", .desc = "Number of completed burst transactions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x6e, .numasks = LIBPFM_ARRAY_SIZE(pii_bus_drdy_clocks), .ngrp = 1, .umasks = pii_bus_drdy_clocks, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRAN_ANY", .desc = "Number of all completed bus transactions. Address bus utilization can be calculated knowing the minimum address bus occupancy. Includes special cycles, etc.", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x70, .numasks = LIBPFM_ARRAY_SIZE(pii_bus_drdy_clocks), .ngrp = 1, .umasks = pii_bus_drdy_clocks, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRAN_MEM", .desc = "Number of completed memory transactions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x6f, .numasks = LIBPFM_ARRAY_SIZE(pii_bus_drdy_clocks), .ngrp = 1, .umasks = pii_bus_drdy_clocks, /* identical to actual umasks list for this event */ }, { .name = "BUS_DATA_RECV", .desc = "Number of bus clock cycles during which this processor is receiving data", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x64, }, { .name = "BUS_BNR_DRV", .desc = "Number of bus clock cycles during which this processor is driving the BNR# pin", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x61, }, { .name = "BUS_HIT_DRV", .desc = "Number of bus clock cycles during which this processor is driving the HIT# pin", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x7a, }, { .name = "BUS_HITM_DRV", .desc = "Number of bus clock cycles during which this processor is driving the HITM# pin", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x7b, }, { .name = "BUS_SNOOP_STALL", .desc = "Number of clock cycles during which the bus is snoop stalled", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x7e, }, { .name = "FLOPS", .desc = "Number of computational floating-point operations retired. Excludes floating-point computational operations that cause traps or assists. Includes internal sub-operations for complex floating-point instructions like transcendentals. Excludes floating point loads and stores", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x1, .code = 0xc1, }, { .name = "FP_COMP_OPS_EXE", .desc = "Number of computational floating-point operations executed. The number of FADD, FSUB, FCOM, FMULs, integer MULs and IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This number does not include the number of cycles, but the number of operations. This event does not distinguish an FADD used in the middle of a transcendental flow from a separate FADD instruction", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x1, .code = 0x10, }, { .name = "FP_ASSIST", .desc = "Number of floating-point exception cases handled by microcode.", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x2, .code = 0x11, }, { .name = "MUL", .desc = "Number of multiplies.This count includes integer as well as FP multiplies and is speculative", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x2, .code = 0x12, }, { .name = "DIV", .desc = "Number of divides.This count includes integer as well as FP divides and is speculative", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x2, .code = 0x13, }, { .name = "CYCLES_DIV_BUSY", .desc = "Number of cycles during which the divider is busy, and cannot accept new divides. This includes integer and FP divides, FPREM, FPSQRT, etc. and is speculative", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x1, .code = 0x14, }, { .name = "LD_BLOCKS", .desc = "Number of load operations delayed due to store buffer blocks. Includes counts caused by preceding stores whose addresses are unknown, preceding stores whose addresses are known but whose data is unknown, and preceding stores that conflicts with the load but which incompletely overlap the load", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x3, }, { .name = "SB_DRAINS", .desc = "Number of store buffer drain cycles. Incremented every cycle the store buffer is draining. Draining is caused by serializing operations like CPUID, synchronizing operations like XCHG, interrupt acknowledgment, as well as other conditions (such as cache flushing).", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x4, }, { .name = "MISALIGN_MEM_REF", .desc = "Number of misaligned data memory references. Incremented by 1 every cycle during which, either the processor's load or store pipeline dispatches a misaligned micro-op Counting is performed if it is the first or second half or if it is blocked, squashed, or missed. In this context, misaligned means crossing a 64-bit boundary", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x5, }, { .name = "UOPS_RETIRED", .desc = "Number of micro-ops retired", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xc2, }, { .name = "INST_DECODED", .desc = "Number of instructions decoded", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xd0, }, { .name = "HW_INT_RX", .desc = "Number of hardware interrupts received", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xc8, }, { .name = "CYCLES_INT_MASKED", .desc = "Number of processor cycles for which interrupts are disabled", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xc6, }, { .name = "CYCLES_INT_PENDING_AND_MASKED", .desc = "Number of processor cycles for which interrupts are disabled and interrupts are pending.", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xc7, }, { .name = "BR_INST_RETIRED", .desc = "Number of branch instructions retired", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xc4, }, { .name = "BR_MISS_PRED_RETIRED", .desc = "Number of mispredicted branches retired", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xc5, }, { .name = "BR_TAKEN_RETIRED", .desc = "Number of taken branches retired", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xc9, }, { .name = "BR_MISS_PRED_TAKEN_RET", .desc = "Number of taken mispredicted branches retired", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xca, }, { .name = "BR_INST_DECODED", .desc = "Number of branch instructions decoded", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xe0, }, { .name = "BTB_MISSES", .desc = "Number of branches for which the BTB did not produce a prediction", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xe2, }, { .name = "BR_BOGUS", .desc = "Number of bogus branches", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xe4, }, { .name = "BACLEARS", .desc = "Number of times BACLEAR is asserted. This is the number of times that a static branch prediction was made, in which the branch decoder decided to make a branch prediction because the BTB did not", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xe6, }, { .name = "RESOURCE_STALLS", .desc = "Incremented by 1 during every cycle for which there is a resource related stall. Includes register renaming buffer entries, memory buffer entries. Does not include stalls due to bus queue full, too many cache misses, etc. In addition to resource related stalls, this event counts some other events. Includes stalls arising during branch misprediction recovery, such as if retirement of the mispredicted branch is delayed and stalls arising while store buffer is draining from synchronizing operations", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xa2, }, { .name = "PARTIAL_RAT_STALLS", .desc = "Number of cycles or events for partial stalls. This includes flag partial stalls", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xd2, }, { .name = "SEGMENT_REG_LOADS", .desc = "Number of segment register loads.", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x6, }, { .name = "MMX_INSTR_EXEC", .desc = "Number of MMX instructions executed", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xb0, }, { .name = "MMX_INSTR_RET", .desc = "Number of MMX instructions retired", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xce, }, { .name = "MMX_SAT_INSTR_EXEC", .desc = "Number of MMX saturating instructions executed", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xb1, }, { .name = "MMX_UOPS_EXEC", .desc = "Number of MMX micro-ops executed", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xb2, }, { .name = "MMX_INSTR_TYPE_EXEC", .desc = "Number of MMX instructions executed by type", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xb3, .numasks = LIBPFM_ARRAY_SIZE(pii_mmx_instr_type_exec), .ngrp = 1, .umasks = pii_mmx_instr_type_exec, }, { .name = "FP_MMX_TRANS", .desc = "Number of MMX transitions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xcc, .numasks = LIBPFM_ARRAY_SIZE(pii_fp_mmx_trans), .ngrp = 1, .umasks = pii_fp_mmx_trans, }, { .name = "MMX_ASSIST", .desc = "Number of MMX micro-ops executed", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xcd, }, { .name = "SEG_RENAME_STALLS", .desc = "Number of Segment Register Renaming Stalls", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xd4, .numasks = LIBPFM_ARRAY_SIZE(pii_seg_rename_stalls), .ngrp = 1, .umasks = pii_seg_rename_stalls, }, { .name = "SEG_REG_RENAMES", .desc = "Number of Segment Register Renames", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xd5, .numasks = LIBPFM_ARRAY_SIZE(pii_seg_rename_stalls), .ngrp = 1, .umasks = pii_seg_rename_stalls, /* identical to actual umasks list for this event */ }, { .name = "RET_SEG_RENAMES", .desc = "Number of segment register rename events retired", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xd6, }, { .name = "L2_LD", .desc = "Number of L2 data loads. This event indicates that a normal, unlocked, load memory access was received by the L2. It includes only L2 cacheable memory accesses; it does not include I/O accesses, other non-memory accesses, or memory accesses such as UC/WT memory accesses. It does include L2 cacheable TLB miss memory accesses", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x29, .numasks = LIBPFM_ARRAY_SIZE(pii_l2_ifetch), .ngrp = 1, .umasks = pii_l2_ifetch, /* identical to actual umasks list for this event */ }, { .name = "L2_LINES_IN", .desc = "Number of lines allocated in the L2", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x24, }, { .name = "L2_LINES_OUT", .desc = "Number of lines removed from the L2 for any reason", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x26, }, { .name = "L2_M_LINES_OUTM", .desc = "Number of modified lines removed from the L2 for any reason", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x27, }, }; libpfm-4.9.0/lib/events/sparc_niagara1_events.h0000664000175000017500000000206113223402656021277 0ustar eranianeranianstatic const sparc_entry_t niagara1_pe[] = { /* PIC1 Niagara-1 events */ { .name = "Instr_cnt", .desc = "Number of instructions completed", .ctrl = PME_CTRL_S1, .code = 0x0, }, /* PIC0 Niagara-1 events */ { .name = "SB_full", .desc = "Store-buffer full", .ctrl = PME_CTRL_S0, .code = 0x0, }, { .name = "FP_instr_cnt", .desc = "FPU instructions", .ctrl = PME_CTRL_S0, .code = 0x1, }, { .name = "IC_miss", .desc = "I-cache miss", .ctrl = PME_CTRL_S0, .code = 0x2, }, { .name = "DC_miss", .desc = "D-cache miss", .ctrl = PME_CTRL_S0, .code = 0x3, }, { .name = "ITLB_miss", .desc = "I-TLB miss", .ctrl = PME_CTRL_S0, .code = 0x4, }, { .name = "DTLB_miss", .desc = "D-TLB miss", .ctrl = PME_CTRL_S0, .code = 0x5, }, { .name = "L2_imiss", .desc = "E-cache instruction fetch miss", .ctrl = PME_CTRL_S0, .code = 0x6, }, { .name = "L2_dmiss_ld", .desc = "E-cache data load miss", .ctrl = PME_CTRL_S0, .code = 0x7, }, }; #define PME_SPARC_NIAGARA1_EVENT_COUNT (sizeof(niagara1_pe)/sizeof(sparc_entry_t)) libpfm-4.9.0/lib/events/intel_hsw_events.h0000664000175000017500000027705313223402656020437 0ustar eranianeranian/* * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * PMU: hsw (Intel Haswell) */ static const intel_x86_umask_t hsw_baclears[]={ { .uname = "ANY", .udesc = "Counts the number of times the front end is re-steered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end", .ucode = 0x1f00, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t hsw_br_inst_exec[]={ { .uname = "NONTAKEN_CONDITIONAL", .udesc = "All macro conditional nontaken branch instructions", .ucode = 0x4100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "NONTAKEN_COND", .udesc = "All macro conditional nontaken branch instructions", .ucode = 0x4100, .uequiv = "NONTAKEN_CONDITIONAL", .uflags = INTEL_X86_NCOMBO, }, { .uname = "TAKEN_CONDITIONAL", .udesc = "Taken speculative and retired macro-conditional branches", .ucode = 0x8100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "TAKEN_COND", .udesc = "Taken speculative and retired macro-conditional branches", .ucode = 0x8100, .uequiv = "TAKEN_CONDITIONAL", .uflags = INTEL_X86_NCOMBO, }, { .uname = "TAKEN_DIRECT_JUMP", .udesc = "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects", .ucode = 0x8200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "TAKEN_INDIRECT_JUMP_NON_CALL_RET", .udesc = "Taken speculative and retired indirect branches excluding calls and returns", .ucode = 0x8400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "TAKEN_INDIRECT_NEAR_RETURN", .udesc = "Taken speculative and retired indirect branches with return mnemonic", .ucode = 0x8800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "TAKEN_DIRECT_NEAR_CALL", .udesc = "Taken speculative and retired direct near calls", .ucode = 0x9000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ALL_CONDITIONAL", .udesc = "Speculative and retired macro-conditional branches", .ucode = 0xc100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ALL_COND", .udesc = "Speculative and retired macro-conditional branches", .ucode = 0xc100, .uequiv = "ALL_CONDITIONAL", .uflags = INTEL_X86_NCOMBO, }, { .uname = "ANY_COND", .udesc = "Speculative and retired macro-conditional branches", .ucode = 0xc100, .uequiv = "ALL_CONDITIONAL", .uflags = INTEL_X86_NCOMBO, }, { .uname = "ALL_DIRECT_JMP", .udesc = "Speculative and retired macro-unconditional branches excluding calls and indirects", .ucode = 0xc200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ALL_INDIRECT_JUMP_NON_CALL_RET", .udesc = "Speculative and retired indirect branches excluding calls and returns", .ucode = 0xc400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ALL_INDIRECT_NEAR_RETURN", .udesc = "Speculative and retired indirect return branches", .ucode = 0xc800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ALL_DIRECT_NEAR_CALL", .udesc = "Speculative and retired direct near calls", .ucode = 0xd000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "TAKEN_INDIRECT_NEAR_CALL", .udesc = "All indirect calls, including both register and memory indirect", .ucode = 0xa000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ALL_BRANCHES", .udesc = "All branch instructions executed", .ucode = 0xff00, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t hsw_br_inst_retired[]={ { .uname = "CONDITIONAL", .udesc = "Counts all taken and not taken macro conditional branch instructions", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "COND", .udesc = "Counts all taken and not taken macro conditional branch instructions", .ucode = 0x100, .uequiv = "CONDITIONAL", .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "NEAR_CALL", .udesc = "Counts all macro direct and indirect near calls", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "ALL_BRANCHES", .udesc = "Counts all taken and not taken macro branches including far branches (architectural event)", .ucode = 0x0, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL | INTEL_X86_PEBS, }, { .uname = "NEAR_RETURN", .udesc = "Counts the number of near ret instructions retired", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "NOT_TAKEN", .udesc = "Counts all not taken macro branch instructions retired", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "NEAR_TAKEN", .udesc = "Counts the number of near branch taken instructions retired", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "FAR_BRANCH", .udesc = "Counts the number of far branch instructions retired", .ucode = 0x4000, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, }; static const intel_x86_umask_t hsw_br_misp_exec[]={ { .uname = "NONTAKEN_CONDITIONAL", .udesc = "Not taken speculative and retired mispredicted macro conditional branches", .ucode = 0x4100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "NONTAKEN_COND", .udesc = "Not taken speculative and retired mispredicted macro conditional branches", .ucode = 0x4100, .uequiv = "NONTAKEN_CONDITIONAL", .uflags = INTEL_X86_NCOMBO, }, { .uname = "TAKEN_CONDITIONAL", .udesc = "Taken speculative and retired mispredicted macro conditional branches", .ucode = 0x8100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "TAKEN_COND", .udesc = "Taken speculative and retired mispredicted macro conditional branches", .ucode = 0x8100, .uequiv = "TAKEN_CONDITIONAL", .uflags = INTEL_X86_NCOMBO, }, { .uname = "TAKEN_INDIRECT_JUMP_NON_CALL_RET", .udesc = "Taken speculative and retired mispredicted indirect branches excluding calls and returns", .ucode = 0x8400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "TAKEN_RETURN_NEAR", .udesc = "Taken speculative and retired mispredicted indirect branches with return mnemonic", .ucode = 0x8800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ALL_CONDITIONAL", .udesc = "Speculative and retired mispredicted macro conditional branches", .ucode = 0xc100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ANY_COND", .udesc = "Speculative and retired mispredicted macro conditional branches", .ucode = 0xc100, .uequiv = "ALL_CONDITIONAL", .uflags = INTEL_X86_NCOMBO, }, { .uname = "ALL_INDIRECT_JUMP_NON_CALL_RET", .udesc = "All mispredicted indirect branches that are not calls nor returns", .ucode = 0xc400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ALL_BRANCHES", .udesc = "Speculative and retired mispredicted macro conditional branches", .ucode = 0xff00, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "TAKEN_INDIRECT_NEAR_CALL", .udesc = "Taken speculative and retired mispredicted indirect calls", .ucode = 0xa000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t hsw_br_misp_retired[]={ { .uname = "CONDITIONAL", .udesc = "All mispredicted macro conditional branch instructions", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "COND", .udesc = "All mispredicted macro conditional branch instructions", .ucode = 0x100, .uequiv = "CONDITIONAL", .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "ALL_BRANCHES", .udesc = "All mispredicted macro branches (architectural event)", .ucode = 0x0, /* architectural encoding */ .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS | INTEL_X86_DFL, }, { .uname = "NEAR_TAKEN", .udesc = "number of near branch instructions retired that were mispredicted and taken", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, }; static const intel_x86_umask_t hsw_cpl_cycles[]={ { .uname = "RING0", .udesc = "Unhalted core cycles when the thread is in ring 0", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "RING123", .udesc = "Unhalted core cycles when thread is in rings 1, 2, or 3", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "RING0_TRANS", .udesc = "Number of intervals between processor halts while thread is in ring 0", .ucode = 0x100 | INTEL_X86_MOD_EDGE | (1 << INTEL_X86_CMASK_BIT), /* edge=1 cnt=1 */ .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_E | _INTEL_X86_ATTR_C, }, }; static const intel_x86_umask_t hsw_cpu_clk_thread_unhalted[]={ { .uname = "REF_XCLK", .udesc = "Count Xclk pulses (100Mhz) when the core is unhalted", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "REF_XCLK_ANY", .udesc = "Count Xclk pulses 100Mhz) when the at least one thread on the physical core is unhalted", .ucode = 0x100 | INTEL_X86_MOD_ANY, /* any=1 */ .uequiv = "REF_XCLK:t", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_T, }, { .uname = "REF_P", .udesc = "Cycles when the core is unhalted (count at 100 Mhz)", .ucode = 0x100, .uequiv = "REF_XCLK", .uflags = INTEL_X86_NCOMBO, }, { .uname = "THREAD_P", .udesc = "Cycles when thread is not halted", .ucode = 0x000, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "ONE_THREAD_ACTIVE", .udesc = "Counts Xclk (100Mhz) pulses when this thread is unhalted and the other thread is halted", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t hsw_cycle_activity[]={ { .uname = "CYCLES_L2_PENDING", .udesc = "Cycles with pending L2 miss loads (must use with HT off only)", .ucode = 0x0100 | (0x1 << INTEL_X86_CMASK_BIT), .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, .ucntmsk= 0xf, }, { .uname = "CYCLES_LDM_PENDING", .udesc = "Cycles with pending memory loads", .ucode = 0x0200 | (0x2 << INTEL_X86_CMASK_BIT), .modhw = _INTEL_X86_ATTR_C, .uflags = INTEL_X86_NCOMBO, }, { .uname = "CYCLES_L1D_PENDING", .udesc = "Cycles with pending L1D load cache misses", .ucode = 0x0800 | (0x8 << INTEL_X86_CMASK_BIT), .ucntmsk= 0x4, .modhw = _INTEL_X86_ATTR_C, .uflags = INTEL_X86_NCOMBO, }, { .uname = "STALLS_L1D_PENDING", .udesc = "Executions stalls due to pending L1D load cache misses", .ucode = 0x0c00 | (0xc << INTEL_X86_CMASK_BIT), .ucntmsk= 0x4, .modhw = _INTEL_X86_ATTR_C, .uflags = INTEL_X86_NCOMBO, }, { .uname = "STALLS_L2_PENDING", .udesc = "Execution stalls due to L2 pending loads (must use with HT off only)", .ucode = 0x0500 | (0x5 << INTEL_X86_CMASK_BIT), .ucntmsk= 0xf, .modhw = _INTEL_X86_ATTR_C, .uflags = INTEL_X86_NCOMBO, }, { .uname = "STALLS_LDM_PENDING", .udesc = "Execution stalls due to memory subsystem", .ucode = 0x0600 | (0x6 << INTEL_X86_CMASK_BIT), .ucntmsk= 0xf, .modhw = _INTEL_X86_ATTR_C, .uflags = INTEL_X86_NCOMBO, }, { .uname = "CYCLES_NO_EXECUTE", .udesc = "Cycles during which no instructions were executed in the execution stage of the pipeline", .ucode = 0x0400 | (0x4 << INTEL_X86_CMASK_BIT), .ucntmsk= 0xf, .modhw = _INTEL_X86_ATTR_C, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t hsw_dtlb_load_misses[]={ { .uname = "MISS_CAUSES_A_WALK", .udesc = "Misses in all DTLB levels that cause page walks", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "WALK_COMPLETED_4K", .udesc = "Misses in all TLB levels causes a page walk that completes (4K)", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "WALK_COMPLETED_2M_4M", .udesc = "Misses in all TLB levels causes a page walk that completes (2M/4M)", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "WALK_COMPLETED", .udesc = "Misses in all TLB levels causes a page walk of any page size that completes", .ucode = 0xe00, .uflags = INTEL_X86_NCOMBO, }, { .uname = "WALK_DURATION", .udesc = "Cycles when PMH is busy with page walks", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "STLB_HIT_4K", .udesc = "Misses that miss the DTLB and hit the STLB (4K)", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "STLB_HIT_2M", .udesc = "Misses that miss the DTLB and hit the STLB (2M)", .ucode = 0x4000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "STLB_HIT", .udesc = "Number of cache load STLB hits. No page walk", .ucode = 0x6000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "PDE_CACHE_MISS", .udesc = "DTLB misses with low part of linear-to-physical address translation missed", .ucode = 0x8000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t hsw_itlb_misses[]={ { .uname = "MISS_CAUSES_A_WALK", .udesc = "Misses in all DTLB levels that cause page walks", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "WALK_COMPLETED_4K", .udesc = "Misses in all TLB levels causes a page walk that completes (4K)", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "WALK_COMPLETED_2M_4M", .udesc = "Misses in all TLB levels causes a page walk that completes (2M/4M)", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "WALK_COMPLETED", .udesc = "Misses in all TLB levels causes a page walk of any page size that completes", .ucode = 0xe00, .uflags = INTEL_X86_NCOMBO, }, { .uname = "WALK_DURATION", .udesc = "Cycles when PMH is busy with page walks", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "STLB_HIT_4K", .udesc = "Misses that miss the DTLB and hit the STLB (4K)", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "STLB_HIT_2M", .udesc = "Misses that miss the DTLB and hit the STLB (2M)", .ucode = 0x4000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "STLB_HIT", .udesc = "Number of cache load STLB hits. No page walk", .ucode = 0x6000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t hsw_fp_assist[]={ { .uname = "X87_OUTPUT", .udesc = "Number of X87 FP assists due to output values", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "X87_INPUT", .udesc = "Number of X87 FP assists due to input values", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "SIMD_OUTPUT", .udesc = "Number of SIMD FP assists due to output values", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "SIMD_INPUT", .udesc = "Number of SIMD FP assists due to input values", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ANY", .udesc = "Cycles with any input/output SEE or FP assists", .ucode = 0x1e00 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */ .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "ALL", .udesc = "Cycles with any input and output SSE or FP assist", .ucode = 0x1e00 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */ .uequiv = "ANY", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, }; static const intel_x86_umask_t hsw_icache[]={ { .uname = "MISSES", .udesc = "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "HIT", .udesc = "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. Includes cacheable and uncacheable accesses and uncacheable fetches", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "IFETCH_STALL", .udesc = "Number of cycles where a code-fetch stalled due to L1 instruction cache miss or an iTLB miss", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t hsw_idq[]={ { .uname = "EMPTY", .udesc = "Cycles the Instruction Decode Queue (IDQ) is empty", .ucode = 0x200, .ucntmsk= 0xf, .uflags = INTEL_X86_NCOMBO, }, { .uname = "MITE_UOPS", .udesc = "Number of uops delivered to Instruction Decode Queue (IDQ) from MITE path", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "DSB_UOPS", .udesc = "Number of uops delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "MS_DSB_UOPS", .udesc = "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "MS_MITE_UOPS", .udesc = "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "MS_UOPS", .udesc = "Number of Uops were delivered into Instruction Decode Queue (IDQ) from MS, initiated by Decode Stream Buffer (DSB) or MITE", .ucode = 0x3000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "MS_UOPS_CYCLES", .udesc = "Number of cycles that Uops were delivered into Instruction Decode Queue (IDQ) when MS_Busy, initiated by Decode Stream Buffer (DSB) or MITE", .ucode = 0x3000 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */ .uequiv = "MS_UOPS:c=1", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "MS_SWITCHES", .udesc = "Number of cycles that Uops were delivered into Instruction Decode Queue (IDQ) when MS_Busy, initiated by Decode Stream Buffer (DSB) or MITE", .ucode = 0x3000 | INTEL_X86_MOD_EDGE | (1 << INTEL_X86_CMASK_BIT), /* edge=1 cnt=1 */ .uequiv = "MS_UOPS:c=1:e", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_E | _INTEL_X86_ATTR_C, }, { .uname = "MITE_UOPS_CYCLES", .udesc = "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path", .ucode = 0x400 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */ .uequiv = "MITE_UOPS:c=1", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "DSB_UOPS_CYCLES", .udesc = "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", .ucode = 0x800 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */ .uequiv = "DSB_UOPS:c=1", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "MS_DSB_UOPS_CYCLES", .udesc = "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", .ucode = 0x1000 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */ .uequiv = "MS_DSB_UOPS:c=1", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "MS_DSB_OCCUR", .udesc = "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is busy", .ucode = 0x1000 | INTEL_X86_MOD_EDGE | (1 << INTEL_X86_CMASK_BIT), /* edge=1 cnt=1 */ .uequiv = "MS_DSB_UOPS:c=1:e=1", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_E | _INTEL_X86_ATTR_C, }, { .uname = "ALL_DSB_CYCLES_4_UOPS", .udesc = "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", .ucode = 0x1800 | (4 << INTEL_X86_CMASK_BIT), /* cnt=4 */ .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "ALL_DSB_CYCLES_ANY_UOPS", .udesc = "Cycles Decode Stream Buffer (DSB) is delivering any Uop", .ucode = 0x1800 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */ .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "ALL_MITE_CYCLES_4_UOPS", .udesc = "Cycles MITE is delivering 4 Uops", .ucode = 0x2400 | (4 << INTEL_X86_CMASK_BIT), /* cnt=4 */ .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "ALL_MITE_CYCLES_ANY_UOPS", .udesc = "Cycles MITE is delivering any Uop", .ucode = 0x2400 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */ .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "ALL_MITE_UOPS", .udesc = "Number of uops delivered to Instruction Decode Queue (IDQ) from any path", .ucode = 0x3c00, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t hsw_idq_uops_not_delivered[]={ { .uname = "CORE", .udesc = "Count number of non-delivered uops to Resource Allocation Table (RAT)", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "CYCLES_0_UOPS_DELIV_CORE", .udesc = "Cycles per thread when 4 or more uops are not delivered to the Resource Allocation Table (RAT) when backend is not stalled", .ucode = 0x100 | (4 << INTEL_X86_CMASK_BIT), /* cnt=4 */ .uflags = INTEL_X86_NCOMBO, .uequiv = "CORE:c=4", .modhw = _INTEL_X86_ATTR_C, }, { .uname = "CYCLES_LE_1_UOP_DELIV_CORE", .udesc = "Cycles per thread when 3 or more uops are not delivered to the Resource Allocation Table (RAT) when backend is not stalled", .ucode = 0x100 | (3 << INTEL_X86_CMASK_BIT), /* cnt=3 */ .uequiv = "CORE:c=3", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "CYCLES_LE_2_UOP_DELIV_CORE", .udesc = "Cycles with less than 2 uops delivered by the front end", .ucode = 0x100 | (2 << INTEL_X86_CMASK_BIT), /* cnt=2 */ .uequiv = "CORE:c=2", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "CYCLES_LE_3_UOP_DELIV_CORE", .udesc = "Cycles with less than 3 uops delivered by the front end", .ucode = 0x100 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */ .uequiv = "CORE:c=1", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "CYCLES_FE_WAS_OK", .udesc = "Cycles Front-End (FE) delivered 4 uops or Resource Allocation Table (RAT) was stalling FE", .ucode = 0x100 | INTEL_X86_MOD_INV | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 inv=1 */ .uequiv = "CORE:c=1:i", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C | _INTEL_X86_ATTR_I, } }; static const intel_x86_umask_t hsw_inst_retired[]={ { .uname = "ANY_P", .udesc = "Number of instructions retired. General Counter - architectural event", .ucode = 0x000, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "ALL", .udesc = "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution (Precise Event)", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "TOTAL_CYCLES", .udesc = "Number of cycles using always true condition", .ucode = 0x100 | INTEL_X86_MOD_INV | (10 << INTEL_X86_CMASK_BIT), /* inv=1 cnt=10 */ .uequiv = "ALL:i=1:c=10", .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, .modhw = _INTEL_X86_ATTR_I | _INTEL_X86_ATTR_C, }, { .uname = "PREC_DIST", .udesc = "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution", .ucode = 0x100, .uequiv = "ALL", .ucntmsk= 0x2, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "X87", .udesc = "X87 FP operations retired with no exceptions. Also counts flows that have several X87 or flows that use X87 uops in the exception handling", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, }; static const intel_x86_umask_t hsw_int_misc[]={ { .uname = "RECOVERY_CYCLES", .udesc = "Cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...)", .ucode = 0x300 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */ .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "RECOVERY_CYCLES_ANY", .udesc = "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke)", .ucode = 0x300 | (1 << INTEL_X86_CMASK_BIT) | INTEL_X86_MOD_ANY, /* cnt=1 any=1 */ .uequiv = "RECOVERY_CYCLES:t", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C | _INTEL_X86_ATTR_T, }, { .uname = "RECOVERY_STALLS_COUNT", .udesc = "Number of occurrences waiting for Machine Clears", .ucode = 0x300 | INTEL_X86_MOD_EDGE | (1 << INTEL_X86_CMASK_BIT), /* edge=1 cnt=1 */ .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_E | _INTEL_X86_ATTR_C, }, }; static const intel_x86_umask_t hsw_itlb[]={ { .uname = "ITLB_FLUSH", .udesc = "Flushing of the Instruction TLB (ITLB) pages independent of page size", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t hsw_l1d[]={ { .uname = "REPLACEMENT", .udesc = "L1D Data line replacements", .ucode = 0x100, .uflags = INTEL_X86_DFL, }, }; static const intel_x86_umask_t hsw_l1d_pend_miss[]={ { .uname = "PENDING", .udesc = "Cycles with L1D load misses outstanding", .ucode = 0x100, .ucntmsk = 0x4, .uflags = INTEL_X86_DFL, }, { .uname = "PENDING_CYCLES", .udesc = "Cycles with L1D load misses outstanding", .ucode = 0x100 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */ .uequiv = "PENDING:c=1", .ucntmsk = 0x4, .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "OCCURRENCES", .udesc = "Number L1D miss outstanding", .ucode = 0x100 | INTEL_X86_MOD_EDGE | (1 << INTEL_X86_CMASK_BIT), /* edge=1 cnt=1 */ .uequiv = "PENDING:c=1:e=1", .ucntmsk = 0x4, .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_E | _INTEL_X86_ATTR_C, }, { .uname = "EDGE", .udesc = "Number L1D miss outstanding", .ucode = 0x100 | INTEL_X86_MOD_EDGE | (1 << INTEL_X86_CMASK_BIT), /* edge=1 cnt=1 */ .uequiv = "PENDING:c=1:e=1", .ucntmsk = 0x4, .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_E | _INTEL_X86_ATTR_C, }, { .uname = "REQUEST_FB_FULL", .udesc = "Number of times a demand request was blocked due to Fill Buffer (FB) unavailability", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "FB_FULL", .udesc = "Number of cycles a demand request was blocked due to Fill Buffer (FB) unavailability", .ucode = 0x200 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */ .uequiv = "REQUEST_FB_FULL:c=1", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, }; static const intel_x86_umask_t hsw_l2_demand_rqsts[]={ { .uname = "WB_HIT", .udesc = "WB requests that hit L2 cache", .ucode = 0x5000, .uflags = INTEL_X86_DFL, }, }; static const intel_x86_umask_t hsw_l2_lines_in[]={ { .uname = "I", .udesc = "L2 cache lines in I state filling L2", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "S", .udesc = "L2 cache lines in S state filling L2", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "E", .udesc = "L2 cache lines in E state filling L2", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ALL", .udesc = "L2 cache lines filling L2", .ucode = 0x700, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "ANY", .udesc = "L2 cache lines filling L2", .uequiv = "ALL", .ucode = 0x700, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t hsw_l2_lines_out[]={ { .uname = "DEMAND_CLEAN", .udesc = "Number of clean L2 cachelines evicted by demand", .ucode = 0x500, .uflags = INTEL_X86_NCOMBO, }, { .uname = "DEMAND_DIRTY", .udesc = "Number of dirty L2 cachelines evicted by demand", .ucode = 0x600, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t hsw_l2_rqsts[]={ { .uname = "DEMAND_DATA_RD_MISS", .udesc = "Demand Data Read requests that miss L2 cache", .ucode = 0x2100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "DEMAND_DATA_RD_HIT", .udesc = "Demand Data Read requests that hit L2 cache", .ucode = 0x4100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "DEMAND_RFO_MISS", .udesc = "RFO requests that miss L2 cache", .ucode = 0x2200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "RFO_MISS", .udesc = "RFO requests that miss L2 cache", .ucode = 0x2200, .uequiv = "DEMAND_RFO_MISS", .uflags = INTEL_X86_NCOMBO, }, { .uname = "DEMAND_RFO_HIT", .udesc = "RFO requests that hit L2 cache", .ucode = 0x4200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "RFO_HIT", .udesc = "RFO requests that hit L2 cache", .ucode = 0x4200, .uequiv = "DEMAND_RFO_HIT", .uflags = INTEL_X86_NCOMBO, }, { .uname = "CODE_RD_MISS", .udesc = "L2 cache misses when fetching instructions", .ucode = 0x2400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ALL_DEMAND_MISS", .udesc = "All demand requests that miss the L2 cache", .ucode = 0x2700, .uflags = INTEL_X86_NCOMBO, }, { .uname = "CODE_RD_HIT", .udesc = "L2 cache hits when fetching instructions, code reads", .ucode = 0x4400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "L2_PF_MISS", .udesc = "Requests from the L2 hardware prefetchers that miss L2 cache", .ucode = 0x3800, .uequiv = "PF_MISS", .uflags = INTEL_X86_NCOMBO, }, { .uname = "PF_MISS", .udesc = "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that miss L2 cache", .ucode = 0x3800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "MISS", .udesc = "All requests that miss the L2 cache", .ucode = 0x3f00, .uflags = INTEL_X86_NCOMBO, }, { .uname = "L2_PF_HIT", .udesc = "Requests from the L2 hardware prefetchers that hit L2 cache", .ucode = 0xd800, .uequiv = "PF_HIT", .uflags = INTEL_X86_NCOMBO, }, { .uname = "PF_HIT", .udesc = "Requests from the L2 hardware prefetchers that hit L2 cache", .ucode = 0xd800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ALL_DEMAND_DATA_RD", .udesc = "Any data read request to L2 cache", .ucode = 0xe100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ALL_RFO", .udesc = "Any data RFO request to L2 cache", .ucode = 0xe200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ALL_CODE_RD", .udesc = "Any code read request to L2 cache", .ucode = 0xe400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ALL_DEMAND_REFERENCES", .udesc = "All demand requests to L2 cache ", .ucode = 0xe700, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ALL_PF", .udesc = "Any L2 HW prefetch request to L2 cache", .ucode = 0xf800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "REFERENCES", .udesc = "All requests to L2 cache", .ucode = 0xff00, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t hsw_l2_trans[]={ { .uname = "DEMAND_DATA_RD", .udesc = "Demand Data Read requests that access L2 cache", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "RFO", .udesc = "RFO requests that access L2 cache", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "CODE_RD", .udesc = "L2 cache accesses when fetching instructions", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ALL_PF", .udesc = "L2 or L3 HW prefetches that access L2 cache, including rejects", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "L1D_WB", .udesc = "L1D writebacks that access L2 cache", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "L2_FILL", .udesc = "L2 fill requests that access L2 cache", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "L2_WB", .udesc = "L2 writebacks that access L2 cache", .ucode = 0x4000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ALL_REQUESTS", .udesc = "Transactions accessing L2 pipe", .ucode = 0x8000, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t hsw_ld_blocks[]={ { .uname = "STORE_FORWARD", .udesc = "Counts the number of loads blocked by overlapping with store buffer entries that cannot be forwarded", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "NO_SR", .udesc = "number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t hsw_ld_blocks_partial[]={ { .uname = "ADDRESS_ALIAS", .udesc = "False dependencies in MOB due to partial compare on address", .ucode = 0x100, .uflags = INTEL_X86_DFL, }, }; static const intel_x86_umask_t hsw_load_hit_pre[]={ { .uname = "SW_PF", .udesc = "Non software-prefetch load dispatches that hit FB allocated for software prefetch", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "HW_PF", .udesc = "Non software-prefetch load dispatches that hit FB allocated for hardware prefetch", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t hsw_lock_cycles[]={ { .uname = "SPLIT_LOCK_UC_LOCK_DURATION", .udesc = "Cycles in which the L1D and L2 are locked, due to a UC lock or split lock", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "CACHE_LOCK_DURATION", .udesc = "cycles that the L1D is locked", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t hsw_longest_lat_cache[]={ { .uname = "MISS", .udesc = "Core-originated cacheable demand requests missed LLC - architectural event", .ucode = 0x4100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "REFERENCE", .udesc = "Core-originated cacheable demand requests that refer to LLC - architectural event", .ucode = 0x4f00, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t hsw_machine_clears[]={ { .uname = "CYCLES", .udesc = "Cycles there was a Nuke. Account for both thread-specific and All Thread Nukes", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "MEMORY_ORDERING", .udesc = "Number of Memory Ordering Machine Clears detected", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "SMC", .udesc = "Number of Self-modifying code (SMC) Machine Clears detected", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "MASKMOV", .udesc = "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "COUNT", .udesc = "Number of machine clears (nukes) of any type", .ucode = 0x100 | INTEL_X86_MOD_EDGE | (1 << INTEL_X86_CMASK_BIT), /* edge=1 cnt=1 */ .uequiv = "CYCLES:c=1:e", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_E | _INTEL_X86_ATTR_C, }, }; static const intel_x86_umask_t hsw_mem_load_uops_l3_hit_retired[]={ { .uname = "XSNP_MISS", .udesc = "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "XSNP_HIT", .udesc = "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "XSNP_HITM", .udesc = "Load had HitM Response from a core on same socket (shared L3). (Non PEBS", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "XSNP_NONE", .udesc = "Retired load uops which data sources were hits in L3 without snoops required", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, }; static const intel_x86_umask_t hsw_mem_load_uops_l3_miss_retired[]={ { .uname = "LOCAL_DRAM", .udesc = "Retired load uops missing L3 cache but hitting local memory", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS | INTEL_X86_DFL, }, { .uname = "REMOTE_DRAM", .udesc = "Number of retired load uops that missed L3 but were service by remote RAM, snoop not needed, snoop miss, snoop hit data not forwarded (Precise Event)", .ucode = 0x400, .umodel = PFM_PMU_INTEL_HSW_EP, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "REMOTE_HITM", .udesc = "Number of retired load uops whose data sources was remote HITM (Precise Event)", .ucode = 0x1000, .umodel = PFM_PMU_INTEL_HSW_EP, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "REMOTE_FWD", .udesc = "Load uops that miss in the L3 whose data source was forwarded from a remote cache (Precise Event)", .ucode = 0x2000, .umodel = PFM_PMU_INTEL_HSW_EP, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, }; static const intel_x86_umask_t hsw_mem_load_uops_retired[]={ { .uname = "L1_HIT", .udesc = "Retired load uops with L1 cache hits as data source", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "L2_HIT", .udesc = "Retired load uops with L2 cache hits as data source", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "L3_HIT", .udesc = "Retired load uops with L3 cache hits as data source", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "L1_MISS", .udesc = "Retired load uops which missed the L1D", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "L2_MISS", .udesc = "Retired load uops which missed the L2. Unknown data source excluded", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "L3_MISS", .udesc = "Retired load uops which missed the L3", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "HIT_LFB", .udesc = "Retired load uops which missed L1 but hit line fill buffer (LFB)", .ucode = 0x4000, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, }; static const intel_x86_umask_t hsw_mem_trans_retired[]={ { .uname = "LOAD_LATENCY", .udesc = "Memory load instructions retired above programmed clocks, minimum threshold value is 3 (Precise Event and ldlat required)", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS | INTEL_X86_LDLAT | INTEL_X86_DFL, }, { .uname = "LATENCY_ABOVE_THRESHOLD", .udesc = "Memory load instructions retired above programmed clocks, minimum threshold value is 3 (Precise Event and ldlat required)", .ucode = 0x100, .uequiv = "LOAD_LATENCY", .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS | INTEL_X86_LDLAT | INTEL_X86_NO_AUTOENCODE, }, }; static const intel_x86_umask_t hsw_mem_uops_retired[]={ { .uname = "STLB_MISS_LOADS", .udesc = "Load uops with true STLB miss retired to architected path", .ucode = 0x1100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "STLB_MISS_STORES", .udesc = "Store uops with true STLB miss retired to architected path", .ucode = 0x1200, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "LOCK_LOADS", .udesc = "Load uops with locked access retired", .ucode = 0x2100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "SPLIT_LOADS", .udesc = "Line-splitted load uops retired", .ucode = 0x4100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "SPLIT_STORES", .udesc = "Line-splitted store uops retired", .ucode = 0x4200, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "ALL_LOADS", .udesc = "All load uops retired", .ucode = 0x8100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "ALL_STORES", .udesc = "All store uops retired", .ucode = 0x8200, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, }; static const intel_x86_umask_t hsw_misalign_mem_ref[]={ { .uname = "LOADS", .udesc = "Speculative cache-line split load uops dispatched to the L1D", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "STORES", .udesc = "Speculative cache-line split store-address uops dispatched to L1D", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t hsw_move_elimination[]={ { .uname = "INT_ELIMINATED", .udesc = "Number of integer Move Elimination candidate uops that were eliminated", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "SIMD_ELIMINATED", .udesc = "Number of SIMD Move Elimination candidate uops that were eliminated", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "INT_NOT_ELIMINATED", .udesc = "Number of integer Move Elimination candidate uops that were not eliminated", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "SIMD_NOT_ELIMINATED", .udesc = "Number of SIMD Move Elimination candidate uops that were not eliminated", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t hsw_offcore_requests[]={ { .uname = "DEMAND_DATA_RD", .udesc = "Demand data read requests sent to uncore (use with HT off only)", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DEMAND_CODE_RD", .udesc = "Demand code read requests sent to uncore (use with HT off only)", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "DEMAND_RFO", .udesc = "Demand RFOs requests sent to uncore (use with HT off only)", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ALL_DATA_RD", .udesc = "Data read requests sent to uncore (use with HT off only)", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t hsw_other_assists[]={ { .uname = "AVX_TO_SSE", .udesc = "Number of transitions from AVX-256 to legacy SSE when penalty applicable", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "SSE_TO_AVX", .udesc = "Number of transitions from legacy SSE to AVX-256 when penalty applicable", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ANY_WB_ASSIST", .udesc = "Number of times any microcode assist is invoked by HW upon uop writeback", .ucode = 0x4000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t hsw_resource_stalls[]={ { .uname = "ANY", .udesc = "Cycles Allocation is stalled due to Resource Related reason", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "ALL", .udesc = "Cycles Allocation is stalled due to Resource Related reason", .ucode = 0x100, .uequiv = "ANY", .uflags = INTEL_X86_NCOMBO, }, { .uname = "RS", .udesc = "Stall cycles caused by absence of eligible entries in Reservation Station (RS)", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "SB", .udesc = "Cycles Allocator is stalled due to Store Buffer full (not including draining from synch)", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ROB", .udesc = "ROB full stall cycles", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t hsw_rob_misc_events[]={ { .uname = "LBR_INSERTS", .udesc = "Count each time an new Last Branch Record (LBR) is inserted", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t hsw_rs_events[]={ { .uname = "EMPTY_CYCLES", .udesc = "Cycles the Reservation Station (RS) is empty for this thread", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "EMPTY_END", .udesc = "Counts number of time the Reservation Station (RS) goes from empty to non-empty", .ucode = 0x100 | INTEL_X86_MOD_INV | INTEL_X86_MOD_EDGE | (1 << INTEL_X86_CMASK_BIT), /* inv=1 edge=1 cnt=1 */ .uequiv = "EMPTY_CYCLES:c=1:e:i", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_E | _INTEL_X86_ATTR_I | _INTEL_X86_ATTR_C, }, }; static const intel_x86_umask_t hsw_tlb_flush[]={ { .uname = "DTLB_THREAD", .udesc = "Count number of DTLB flushes of thread-specific entries", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "STLB_ANY", .udesc = "Count number of any STLB flushes", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t hsw_uops_executed[]={ { .uname = "CORE", .udesc = "Number of uops executed from any thread", .ucode = 0x200, .uflags = INTEL_X86_DFL, }, { .uname = "STALL_CYCLES", .udesc = "Number of cycles with no uops executed", .ucode = 0x100 | INTEL_X86_MOD_INV | (1 << INTEL_X86_CMASK_BIT), /* inv=1 cnt=1 */ .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_I | _INTEL_X86_ATTR_C, }, { .uname = "CYCLES_GE_1_UOP_EXEC", .udesc = "Cycles where at least 1 uop was executed per thread", .ucode = 0x100 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */ .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "CYCLES_GE_2_UOPS_EXEC", .udesc = "Cycles where at least 2 uops were executed per thread", .ucode = 0x100 | (2 << INTEL_X86_CMASK_BIT), /* cnt=2 */ .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "CYCLES_GE_3_UOPS_EXEC", .udesc = "Cycles where at least 3 uops were executed per thread", .ucode = 0x100 | (3 << INTEL_X86_CMASK_BIT), /* cnt=3 */ .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "CYCLES_GE_4_UOPS_EXEC", .udesc = "Cycles where at least 4 uops were executed per thread", .ucode = 0x100 | (4 << INTEL_X86_CMASK_BIT), /* cnt=4 */ .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "CORE_CYCLES_GE_1", .udesc = "Cycles where at least 1 uop was executed from any thread", .ucode = 0x200 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */ .uequiv = "CORE:c=1", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "CORE_CYCLES_GE_2", .udesc = "Cycles where at least 2 uops were executed from any thread", .ucode = 0x200 | (2 << INTEL_X86_CMASK_BIT), /* cnt=2 */ .uequiv = "CORE:c=2", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "CORE_CYCLES_GE_3", .udesc = "Cycles where at least 3 uops were executed from any thread", .ucode = 0x200 | (3 << INTEL_X86_CMASK_BIT), /* cnt=3 */ .uequiv = "CORE:c=3", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "CORE_CYCLES_GE_4", .udesc = "Cycles where at least 4 uops were executed from any thread", .ucode = 0x200 | (4 << INTEL_X86_CMASK_BIT), /* cnt=4 */ .uequiv = "CORE:c=4", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "CORE_CYCLES_NONE", .udesc = "Cycles where no uop is executed on any thread", .ucode = 0x200 | INTEL_X86_MOD_INV, /* inv=1 */ .uequiv = "CORE:i", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_I, }, }; static const intel_x86_umask_t hsw_uops_executed_port[]={ { .uname = "PORT_0", .udesc = "Cycles which a Uop is executed on port 0", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "PORT_1", .udesc = "Cycles which a Uop is executed on port 1", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "PORT_2", .udesc = "Cycles which a Uop is executed on port 2", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "PORT_3", .udesc = "Cycles which a Uop is executed on port 3", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "PORT_4", .udesc = "Cycles which a Uop is executed on port 4", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "PORT_5", .udesc = "Cycles which a Uop is executed on port 5", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "PORT_6", .udesc = "Cycles which a Uop is executed on port 6", .ucode = 0x4000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "PORT_7", .udesc = "Cycles which a Uop is executed on port 7", .ucode = 0x8000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "PORT_0_CORE", .udesc = "tbd", .ucode = 0x100 | INTEL_X86_MOD_ANY, /* any=1 */ .uequiv = "PORT_0:t=1", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_T, }, { .uname = "PORT_1_CORE", .udesc = "tbd", .ucode = 0x200 | INTEL_X86_MOD_ANY, /* any=1 */ .uequiv = "PORT_1:t=1", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_T, }, { .uname = "PORT_2_CORE", .udesc = "tbd", .ucode = 0x400 | INTEL_X86_MOD_ANY, /* any=1 */ .uequiv = "PORT_2:t=1", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_T, }, { .uname = "PORT_3_CORE", .udesc = "tbd", .ucode = 0x800 | INTEL_X86_MOD_ANY, /* any=1 */ .uequiv = "PORT_3:t=1", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_T, }, { .uname = "PORT_4_CORE", .udesc = "tbd", .ucode = 0x1000 | INTEL_X86_MOD_ANY, /* any=1 */ .uequiv = "PORT_4:t=1", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_T, }, { .uname = "PORT_5_CORE", .udesc = "tbd", .ucode = 0x2000 | INTEL_X86_MOD_ANY, /* any=1 */ .uequiv = "PORT_5:t=1", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_T, }, { .uname = "PORT_6_CORE", .udesc = "tbd", .ucode = 0x4000 | INTEL_X86_MOD_ANY, /* any=1 */ .uequiv = "PORT_6:t=1", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_T, }, { .uname = "PORT_7_CORE", .udesc = "tbd", .ucode = 0x8000 | INTEL_X86_MOD_ANY, /* any=1 */ .uequiv = "PORT_7:t=1", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_T, }, }; static const intel_x86_umask_t hsw_uops_issued[]={ { .uname = "ANY", .udesc = "Number of Uops issued by the Resource Allocation Table (RAT) to the Reservation Station (RS)", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "ALL", .udesc = "Number of Uops issued by the Resource Allocation Table (RAT) to the Reservation Station (RS)", .ucode = 0x100, .uequiv = "ANY", .uflags = INTEL_X86_NCOMBO, }, { .uname = "FLAGS_MERGE", .udesc = "Number of flags-merge uops being allocated. Such uops adds delay", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "SLOW_LEA", .udesc = "Number of slow LEA or similar uops allocated. Such uop has 3 sources regardless if result of LEA instruction or not", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "SINGLE_MUL", .udesc = "Number of Multiply packed/scalar single precision uops allocated", .ucode = 0x4000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "STALL_CYCLES", .udesc = "Counts the number of cycles no uops issued by this thread", .ucode = 0x100 | INTEL_X86_MOD_INV | (1 << INTEL_X86_CMASK_BIT), /* inv=1 cnt=1 */ .uequiv = "ANY:c=1:i=1", .uflags = INTEL_X86_NCOMBO, .ucntmsk = 0xf, .modhw = _INTEL_X86_ATTR_I | _INTEL_X86_ATTR_C, }, { .uname = "CORE_STALL_CYCLES", .udesc = "Counts the number of cycles no uops issued on this core", .ucode = 0x100 | INTEL_X86_MOD_ANY | INTEL_X86_MOD_INV | (1 << INTEL_X86_CMASK_BIT), /* any=1 inv=1 cnt=1 */ .uequiv = "ANY:c=1:i=1:t=1", .ucntmsk = 0xf, .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_T | _INTEL_X86_ATTR_I | _INTEL_X86_ATTR_C, }, }; static const intel_x86_umask_t hsw_uops_retired[]={ { .uname = "ALL", .udesc = "All uops that actually retired", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS | INTEL_X86_DFL, }, { .uname = "ANY", .udesc = "All uops that actually retired", .ucode = 0x100, .uequiv = "ALL", .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "RETIRE_SLOTS", .udesc = "number of retirement slots used non PEBS", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "STALL_CYCLES", .udesc = "Cycles no executable uops retired (Precise Event)", .ucode = 0x100 | INTEL_X86_MOD_INV | (1 << INTEL_X86_CMASK_BIT), /* inv=1 cnt=1 */ .uequiv = "ALL:i=1:c=1", .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, .modhw = _INTEL_X86_ATTR_I | _INTEL_X86_ATTR_C, }, { .uname = "TOTAL_CYCLES", .udesc = "Number of cycles using always true condition applied to PEBS uops retired event", .ucode = 0x100 | INTEL_X86_MOD_INV | (10 << INTEL_X86_CMASK_BIT), /* inv=1 cnt=10 */ .uequiv = "ALL:i=1:c=10", .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, .modhw = _INTEL_X86_ATTR_I | _INTEL_X86_ATTR_C, }, { .uname = "CORE_STALL_CYCLES", .udesc = "Cycles no executable uops retired on core (Precise Event)", .ucode = 0x100 | INTEL_X86_MOD_INV | (1 << INTEL_X86_CMASK_BIT), /* inv=1 cnt=1 */ .uequiv = "ALL:i=1:c=1:t=1", .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, .modhw = _INTEL_X86_ATTR_I | _INTEL_X86_ATTR_C, }, { .uname = "STALL_OCCURRENCES", .udesc = "Number of transitions from stalled to unstalled execution (Precise Event)", .ucode = 0x100 | INTEL_X86_MOD_INV | INTEL_X86_MOD_EDGE| (1 << INTEL_X86_CMASK_BIT), /* inv=1 edge=1 cnt=1 */ .uequiv = "ALL:c=1:i=1:e=1", .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, .modhw = _INTEL_X86_ATTR_I | _INTEL_X86_ATTR_C | _INTEL_X86_ATTR_E, }, }; static const intel_x86_umask_t hsw_offcore_response[]={ { .uname = "DMND_DATA_RD", .udesc = "Request: number of demand and DCU prefetch data reads of full and partial cachelines as well as demand data page table entry cacheline reads. Does not count L2 data read prefetches or instruction fetches", .ucode = 1ULL << (0 + 8), .grpid = 0, }, { .uname = "DMND_RFO", .udesc = "Request: number of demand and DCU prefetch reads for ownership (RFO) requests generated by a write to data cacheline. Does not count L2 RFO prefetches", .ucode = 1ULL << (1 + 8), .grpid = 0, }, { .uname = "DMND_CODE_RD", .udesc = "Request: number of demand and DCU prefetch instruction cacheline reads. Does not count L2 code read prefetches", .ucode = 1ULL << (2 + 8), .grpid = 0, }, { .uname = "DMND_IFETCH", .udesc = "Request: number of demand and DCU prefetch instruction cacheline reads. Does not count L2 code read prefetches", .ucode = 1ULL << (2 + 8), .uequiv = "DMND_CODE_RD", .grpid = 0, }, { .uname = "WB", .udesc = "Request: number of writebacks (modified to exclusive) transactions", .ucode = 1ULL << (3 + 8), .grpid = 0, }, { .uname = "PF_DATA_RD", .udesc = "Request: number of data cacheline reads generated by L2 prefetchers", .ucode = 1ULL << (4 + 8), .grpid = 0, }, { .uname = "PF_RFO", .udesc = "Request: number of RFO requests generated by L2 prefetchers", .ucode = 1ULL << (5 + 8), .grpid = 0, }, { .uname = "PF_CODE_RD", .udesc = "Request: number of code reads generated by L2 prefetchers", .ucode = 1ULL << (6 + 8), .grpid = 0, }, { .uname = "PF_IFETCH", .udesc = "Request: number of code reads generated by L2 prefetchers", .ucode = 1ULL << (6 + 8), .grpid = 0, .uequiv= "PF_CODE_RD", }, { .uname = "PF_L3_DATA_RD", .udesc = "Request: number of L2 prefetcher requests to L3 for loads", .ucode = 1ULL << (7 + 8), .grpid = 0, }, { .uname = "PF_L3_RFO", .udesc = "Request: number of RFO requests generated by L2 prefetcher", .ucode = 1ULL << (8 + 8), .grpid = 0, }, { .uname = "PF_L3_CODE_RD", .udesc = "Request: number of L2 prefetcher requests to L3 for instruction fetches", .ucode = 1ULL << (9 + 8), .grpid = 0, }, { .uname = "PF_L3_IFETCH", .udesc = "Request: number of L2 prefetcher requests to L3 for instruction fetches", .ucode = 1ULL << (9 + 8), .grpid = 0, .uequiv= "PF_L3_CODE_RD", }, { .uname = "SPLIT_LOCK_UC_LOCK", .udesc = "Request: number of bus lock and split lock requests", .ucode = 1ULL << (10 + 8), .grpid = 0, }, { .uname = "BUS_LOCKS", .udesc = "Request: number of bus lock and split lock requests", .ucode = 1ULL << (10 + 8), .grpid = 0, .uequiv= "SPLIT_LOCK_UC_LOCK", }, { .uname = "STRM_ST", .udesc = "Request: number of streaming store requests", .ucode = 1ULL << (11 + 8), .grpid = 0, }, { .uname = "OTHER", .udesc = "Request: counts one of the following transaction types, including L3 invalidate, I/O, full or partial writes, WC or non-temporal stores, CLFLUSH, Fences, lock, unlock, split lock", .ucode = 1ULL << (15+8), .grpid = 0, }, { .uname = "ANY_CODE_RD", .udesc = "Request: combination of PF_CODE_RD | DMND_CODE_RD | PF_L3_CODE_RD", .uequiv = "PF_CODE_RD:DMND_CODE_RD:PF_L3_CODE_RD", .ucode = 0x24400, .grpid = 0, }, { .uname = "ANY_IFETCH", .udesc = "Request: combination of PF_CODE_RD | PF_L3_CODE_RD", .ucode = 0x24000, .grpid = 0, }, { .uname = "ANY_REQUEST", .udesc = "Request: combination of all request umasks", .uequiv = "DMND_DATA_RD:DMND_RFO:DMND_CODE_RD:WB:PF_DATA_RD:PF_RFO:PF_CODE_RD:PF_L3_DATA_RD:PF_L3_RFO:PF_L3_CODE_RD:SPLIT_LOCK_UC_LOCK:STRM_ST:OTHER", .ucode = 0x8fff00, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, .grpid = 0, }, { .uname = "ANY_DATA", .udesc = "Request: combination of DMND_DATA | PF_DATA_RD | PF_L3_DATA_RD", .uequiv = "DMND_DATA_RD:PF_DATA_RD:PF_L3_DATA_RD", .ucode = 0x9100, .grpid = 0, }, { .uname = "ANY_RFO", .udesc = "Request: combination of DMND_RFO | PF_RFO | PF_L3_RFO", .uequiv = "DMND_RFO:PF_RFO:PF_L3_RFO", .ucode = 0x12200, .grpid = 0, }, { .uname = "ANY_RESPONSE", .udesc = "Response: count any response type", .ucode = 1ULL << (16+8), .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL | INTEL_X86_EXCL_GRP_GT, .grpid = 1, }, { .uname = "NO_SUPP", .udesc = "Supplier: counts number of times supplier information is not available", .ucode = 1ULL << (17+8), .grpid = 1, }, { .uname = "L3_HITM", .udesc = "Supplier: counts L3 hits in M-state (initial lookup)", .ucode = 1ULL << (18+8), .grpid = 1, }, { .uname = "L3_HITE", .udesc = "Supplier: counts L3 hits in E-state", .ucode = 1ULL << (19+8), .grpid = 1, }, { .uname = "L3_HITS", .udesc = "Supplier: counts L3 hits in S-state", .ucode = 1ULL << (20+8), .grpid = 1, }, { .uname = "L3_HITF", .udesc = "Supplier: counts L3 hits in F-state", .ucode = 1ULL << (21+8), .umodel = PFM_PMU_INTEL_HSW_EP, .grpid = 1, }, { .uname = "L3_HIT", .udesc = "Supplier: counts L3 hits in any state (M, E, S)", .ucode = 0x7ULL << (18+8), .uequiv = "L3_HITM:L3_HITE:L3_HITS", .umodel = PFM_PMU_INTEL_HSW, .grpid = 1, }, { .uname = "L3_HIT", .udesc = "Supplier: counts L3 hits in any state (M, E, S, F)", .ucode = 0xfULL << (18+8), .uequiv = "L3_HITM:L3_HITE:L3_HITS:L3_HITF", .umodel = PFM_PMU_INTEL_HSW_EP, .grpid = 1, }, { .uname = "L3_MISS_LOCAL", .udesc = "Supplier: counts L3 misses to local DRAM", .ucode = 1ULL << (22+8), .grpid = 1, }, { .uname = "L3_MISS_REMOTE_HOP0", .udesc = "Supplier: counts L3 misses to remote DRAM with 0 hop", .ucode = 0x1ULL << (27+8), .umodel = PFM_PMU_INTEL_HSW_EP, .grpid = 1, }, { .uname = "L3_MISS_REMOTE_HOP1", .udesc = "Supplier: counts L3 misses to remote DRAM with 1 hop", .ucode = 0x1ULL << (28+8), .umodel = PFM_PMU_INTEL_HSW_EP, .grpid = 1, }, { .uname = "L3_MISS_REMOTE_HOP2P", .udesc = "Supplier: counts L3 misses to remote DRAM with 2P hops", .ucode = 0x1ULL << (29+8), .umodel = PFM_PMU_INTEL_HSW_EP, .grpid = 1, }, { .uname = "L3_MISS", .udesc = "Supplier: counts L3 misses to local DRAM", .ucode = 0x1ULL << (22+8), .uequiv = "L3_MISS_LOCAL", .grpid = 1, .umodel = PFM_PMU_INTEL_HSW, }, { .uname = "L3_MISS", .udesc = "Supplier: counts L3 misses to local or remote DRAM", .ucode = 0x7ULL << (27+8) | 0x1ULL << (22+8), .uequiv = "L3_MISS_LOCAL:L3_MISS_REMOTE_HOP0:L3_MISS_REMOTE_HOP1:L3_MISS_REMOTE_HOP2P", .umodel = PFM_PMU_INTEL_HSW_EP, .grpid = 1, }, { .uname = "L3_MISS_REMOTE", .udesc = "Supplier: counts L3 misses to remote node", .ucode = 0x7ULL << (27+8), .uequiv = "L3_MISS_REMOTE_HOP0:L3_MISS_REMOTE_HOP1:L3_MISS_REMOTE_HOP2P", .umodel = PFM_PMU_INTEL_HSW_EP, .grpid = 1, }, { .uname = "L3_MISS_REMOTE_DRAM", .udesc = "Supplier: counts L3 misses to remote node", .ucode = 0x7ULL << (27+8), .uequiv = "L3_MISS_REMOTE", .umodel = PFM_PMU_INTEL_HSW_EP, .grpid = 1, }, { .uname = "SPL_HIT", .udesc = "Supplier: counts L3 supplier hit", .ucode = 0x1ULL << (30+8), .grpid = 1, }, { .uname = "SNP_NONE", .udesc = "Snoop: counts number of times no snoop-related information is available", .ucode = 1ULL << (31+8), .grpid = 2, }, { .uname = "SNP_NOT_NEEDED", .udesc = "Snoop: counts the number of times no snoop was needed to satisfy the request", .ucode = 1ULL << (32+8), .grpid = 2, }, { .uname = "SNP_MISS", .udesc = "Snoop: counts number of times a snoop was needed and it missed all snooped caches", .ucode = 1ULL << (33+8), .grpid = 2, }, { .uname = "SNP_NO_FWD", .udesc = "Snoop: counts number of times a snoop was needed and it hit in at leas one snooped cache", .ucode = 1ULL << (34+8), .grpid = 2, }, { .uname = "SNP_FWD", .udesc = "Snoop: counts number of times a snoop was needed and data was forwarded from a remote socket", .ucode = 1ULL << (35+8), .grpid = 2, }, { .uname = "SNP_HITM", .udesc = "Snoop: counts number of times a snoop was needed and it hitM-ed in local or remote cache", .ucode = 1ULL << (36+8), .grpid = 2, }, { .uname = "SNP_NON_DRAM", .udesc = "Snoop: counts number of times target was a non-DRAM system address. This includes MMIO transactions", .ucode = 1ULL << (37+8), .grpid = 2, }, { .uname = "SNP_ANY", .udesc = "Snoop: any snoop reason", .ucode = 0x7fULL << (31+8), .uequiv = "SNP_NONE:SNP_NOT_NEEDED:SNP_MISS:SNP_NO_FWD:SNP_FWD:SNP_HITM:SNP_NON_DRAM", .uflags= INTEL_X86_DFL, .grpid = 2, }, }; static const intel_x86_umask_t hsw_hle_retired[]={ { .uname = "START", .udesc = "Number of times an HLE execution started", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "COMMIT", .udesc = "Number of times an HLE execution successfully committed", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ABORTED", .udesc = "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one) (Precise Event)", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "ABORTED_MISC1", .udesc = "Number of times an HLE execution aborted due to various memory events", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ABORTED_MISC2", .udesc = "Number of times an HLE execution aborted due to uncommon conditions", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ABORTED_MISC3", .udesc = "Number of times an HLE execution aborted due to HLE-unfriendly instructions", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ABORTED_MISC4", .udesc = "Number of times an HLE execution aborted due to incompatible memory type", .ucode = 0x4000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ABORTED_MISC5", .udesc = "Number of times an HLE execution aborted due to none of the other 4 reasons (e.g., interrupt)", .ucode = 0x8000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t hsw_rtm_retired[]={ { .uname = "START", .udesc = "Number of times an RTM execution started", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "COMMIT", .udesc = "Number of times an RTM execution successfully committed", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ABORTED", .udesc = "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one) (Precise Event)", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "ABORTED_MISC1", .udesc = "Number of times an RTM execution aborted due to various memory events", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ABORTED_MISC2", .udesc = "Number of times an RTM execution aborted due to uncommon conditions", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ABORTED_MISC3", .udesc = "Number of times an RTM execution aborted due to RTM-unfriendly instructions", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ABORTED_MISC4", .udesc = "Number of times an RTM execution aborted due to incompatible memory type", .ucode = 0x4000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ABORTED_MISC5", .udesc = "Number of times an RTM execution aborted due to none of the other 4 reasons (e.g., interrupt)", .ucode = 0x8000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t hsw_tx_mem[]={ { .uname = "ABORT_CONFLICT", .udesc = "Number of times a transactional abort was signaled due to data conflict on a transactionally accessed address", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ABORT_CAPACITY_WRITE", .udesc = "Number of times a transactional abort was signaled due to data capacity limitation for transactional writes", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ABORT_HLE_STORE_TO_ELIDED_LOCK", .udesc = "Number of times a HLE transactional execution aborted due to a non xrelease prefixed instruction writing to an elided lock in the elision buffer", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", .udesc = "Number of times a HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ABORT_HLE_ELISION_BUFFER_MISMATCH", .udesc = "Number of times a HLE transaction execution aborted due to xrelease lock not satisfying the address and value requirements in the elision buffer", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", .udesc = "Number of times a HLE transaction execution aborted due to an unsupported read alignment from the elision buffer", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ABORT_HLE_ELISION_BUFFER_FULL", .udesc = "Number of times a HLE clock could not be elided due to ElisionBufferAvailable being zero", .ucode = 0x4000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t hsw_tx_exec[]={ { .uname = "MISC1", .udesc = "Number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "MISC2", .udesc = "Number of times a class of instructions that may cause a transactional abort was executed inside a transactional region", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "MISC3", .udesc = "Number of times an instruction execution caused the supported nest count to be exceeded", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "MISC4", .udesc = "Number of times an instruction with HLE xbegin prefix was executed inside a RTM transactional region", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "MISC5", .udesc = "Number of times an instruction with HLE xacquire prefix was executed inside a RTM transactional region", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t hsw_offcore_requests_outstanding[]={ { .uname = "ALL_DATA_RD_CYCLES", .udesc = "Cycles with cacheable data read transactions in the superQ (use with HT off only)", .uequiv = "ALL_DATA_RD:c=1", .ucode = 0x800 | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, }, { .uname = "DEMAND_CODE_RD_CYCLES", .udesc = "Cycles with demand code reads transactions in the superQ (use with HT off only)", .uequiv = "DEMAND_CODE_RD:c=1", .ucode = 0x200 | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, }, { .uname = "DEMAND_DATA_RD_CYCLES", .udesc = "Cycles with demand data read transactions in the superQ (use with HT off only)", .uequiv = "DEMAND_DATA_RD:c=1", .ucode = 0x100 | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, }, { .uname = "ALL_DATA_RD", .udesc = "Cacheable data read transactions in the superQ every cycle (use with HT off only)", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DEMAND_CODE_RD", .udesc = "Code read transactions in the superQ every cycle (use with HT off only)", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DEMAND_DATA_RD", .udesc = "Demand data read transactions in the superQ every cycle (use with HT off only)", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DEMAND_DATA_RD_GE_6", .udesc = "Cycles with at lesat 6 offcore outstanding demand data read requests in the uncore queue", .uequiv = "DEMAND_DATA_RD:c=6", .ucode = 0x100 | (6 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "DEMAND_RFO", .udesc = "Outstanding RFO (store) transactions in the superQ every cycle (use with HT off only)", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DEMAND_RFO_CYCLES", .udesc = "Cycles with outstanding RFO (store) transactions in the superQ (use with HT off only)", .uequiv = "DEMAND_RFO:c=1", .ucode = 0x400 | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t hsw_ild_stall[]={ { .uname = "LCP", .udesc = "Stall caused by changing prefix length of the instruction", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "IQ_FULL", .udesc = "Stall cycles due to IQ full", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t hsw_page_walker_loads[]={ { .uname = "DTLB_L1", .udesc = "Number of DTLB page walker loads that hit in the L1D and line fill buffer", .ucode = 0x1100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ITLB_L1", .udesc = "Number of ITLB page walker loads that hit in the L1I and line fill buffer", .ucode = 0x2100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DTLB_L2", .udesc = "Number of DTLB page walker loads that hit in the L2", .ucode = 0x1200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ITLB_L2", .udesc = "Number of ITLB page walker loads that hit in the L2", .ucode = 0x2200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DTLB_L3", .udesc = "Number of DTLB page walker loads that hit in the L3", .ucode = 0x1400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ITLB_L3", .udesc = "Number of ITLB page walker loads that hit in the L3", .ucode = 0x2400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "EPT_DTLB_L1", .udesc = "Number of extended page table walks from the DTLB that hit in the L1D and line fill buffer", .ucode = 0x4100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "EPT_ITLB_L1", .udesc = "Number of extended page table walks from the ITLB that hit in the L1D and line fill buffer", .ucode = 0x8100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "EPT_DTLB_L2", .udesc = "Number of extended page table walks from the DTLB that hit in the L2", .ucode = 0x4200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "EPT_ITLB_L2", .udesc = "Number of extended page table walks from the ITLB that hit in the L2", .ucode = 0x8200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "EPT_DTLB_L3", .udesc = "Number of extended page table walks from the DTLB that hit in the L3", .ucode = 0x4400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "EPT_ITLB_L3", .udesc = "Number of extended page table walks from the ITLB that hit in the L3", .ucode = 0x8400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DTLB_MEMORY", .udesc = "Number of DTLB page walker loads that hit memory", .ucode = 0x1800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ITLB_MEMORY", .udesc = "Number of ITLB page walker loads that hit memory", .ucode = 0x2800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "EPT_DTLB_MEMORY", .udesc = "Number of extended page table walks from the DTLB that hit memory", .ucode = 0x4800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "EPT_ITLB_MEMORY", .udesc = "Number of extended page table walks from the ITLB that hit memory", .ucode = 0x8800, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t hsw_lsd[]={ { .uname = "UOPS", .udesc = "Number of uops delivered by the Loop Stream Detector (LSD)", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "ACTIVE", .udesc = "Cycles with uops delivered by the LSD but which did not come from decoder", .ucode = 0x100 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */ .uequiv = "UOPS:c=1", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "CYCLES_4_UOPS", .udesc = "Cycles with 4 uops delivered by the LSD but which did not come from decoder", .ucode = 0x100 | (4 << INTEL_X86_CMASK_BIT), /* cnt=4 */ .uequiv = "UOPS:c=4", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, }; static const intel_x86_umask_t hsw_dsb2mite_switches[]={ { .uname = "PENALTY_CYCLES", .udesc = "Number of DSB to MITE switch true penalty cycles", .ucode = 0x0200, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t hsw_ept[]={ { .uname = "WALK_CYCLES", .udesc = "Cycles for an extended page table walk", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t hsw_arith[]={ { .uname = "DIVIDER_UOPS", .udesc = "Number of uops executed by divider", .ucode = 0x0200, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t hsw_offcore_requests_buffer[]={ { .uname = "SQ_FULL", .udesc = "Number of cycles the offcore requests buffer is full", .ucode = 0x0100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t hsw_avx[]={ { .uname = "ALL", .udesc = "Approximate counts of AVX and AVX2 256-bit instructions, including non-arithmetic instructions, loads, and stores. May count non-AVX instructions using 256-bit operations", .ucode = 0x0700, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t hsw_sq_misc[]={ { .uname = "SPLIT_LOCK", .udesc = "Number of split locks in the super queue (SQ)", .ucode = 0x1000, .uflags = INTEL_X86_DFL, }, }; static const intel_x86_entry_t intel_hsw_pe[]={ { .name = "UNHALTED_CORE_CYCLES", .desc = "Count core clock cycles whenever the clock signal on the specific core is running (not halted)", .modmsk = INTEL_V4_ATTRS, .cntmsk = 0x20000000full, .code = 0x3c, }, { .name = "UNHALTED_REFERENCE_CYCLES", .desc = "Unhalted reference cycles", .modmsk = INTEL_FIXED3_ATTRS, .cntmsk = 0x400000000ull, .code = 0x0300, /* pseudo encoding */ .flags = INTEL_X86_FIXED, }, { .name = "INSTRUCTION_RETIRED", .desc = "Number of instructions at retirement", .modmsk = INTEL_V4_ATTRS, .cntmsk = 0x10000000full, .code = 0xc0, }, { .name = "INSTRUCTIONS_RETIRED", .desc = "This is an alias for INSTRUCTION_RETIRED", .modmsk = INTEL_V4_ATTRS, .equiv = "INSTRUCTION_RETIRED", .cntmsk = 0x10000000full, .code = 0xc0, }, { .name = "BRANCH_INSTRUCTIONS_RETIRED", .desc = "Count branch instructions at retirement. Specifically, this event counts the retirement of the last micro-op of a branch instruction", .modmsk = INTEL_V4_ATTRS, .equiv = "BR_INST_RETIRED:ALL_BRANCHES", .cntmsk = 0xff, .code = 0xc4, }, { .name = "MISPREDICTED_BRANCH_RETIRED", .desc = "Count mispredicted branch instructions at retirement. Specifically, this event counts at retirement of the last micro-op of a branch instruction in the architectural path of the execution and experienced misprediction in the branch prediction hardware", .modmsk = INTEL_V4_ATTRS, .equiv = "BR_MISP_RETIRED:ALL_BRANCHES", .cntmsk = 0xff, .code = 0xc5, }, { .name = "BACLEARS", .desc = "Branch re-steered", .code = 0xe6, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hsw_baclears), .umasks = hsw_baclears }, { .name = "BR_INST_EXEC", .desc = "Branch instructions executed", .code = 0x88, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hsw_br_inst_exec), .umasks = hsw_br_inst_exec }, { .name = "BR_INST_RETIRED", .desc = "Branch instructions retired (Precise Event)", .code = 0xc4, .cntmsk = 0xff, .ngrp = 1, .flags = INTEL_X86_PEBS, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hsw_br_inst_retired), .umasks = hsw_br_inst_retired }, { .name = "BR_MISP_EXEC", .desc = "Mispredicted branches executed", .code = 0x89, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hsw_br_misp_exec), .umasks = hsw_br_misp_exec }, { .name = "BR_MISP_RETIRED", .desc = "Mispredicted retired branches (Precise Event)", .code = 0xc5, .cntmsk = 0xff, .ngrp = 1, .flags = INTEL_X86_PEBS, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hsw_br_misp_retired), .umasks = hsw_br_misp_retired }, { .name = "CPL_CYCLES", .desc = "Unhalted core cycles at a specific ring level", .code = 0x5c, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hsw_cpl_cycles), .umasks = hsw_cpl_cycles }, { .name = "CPU_CLK_THREAD_UNHALTED", .desc = "Count core clock cycles whenever the clock signal on the specific core is running (not halted)", .code = 0x3c, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hsw_cpu_clk_thread_unhalted), .umasks = hsw_cpu_clk_thread_unhalted }, { .name = "CPU_CLK_UNHALTED", .desc = "Count core clock cycles whenever the clock signal on the specific core is running (not halted)", .code = 0x3c, .cntmsk = 0xff, .modmsk = INTEL_V4_ATTRS, .equiv = "CPU_CLK_THREAD_UNHALTED", }, { .name = "CYCLE_ACTIVITY", .desc = "Stalled cycles", .code = 0xa3, .cntmsk = 0xf, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hsw_cycle_activity), .umasks = hsw_cycle_activity }, { .name = "DTLB_LOAD_MISSES", .desc = "Data TLB load misses", .code = 0x8, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hsw_dtlb_load_misses), .umasks = hsw_dtlb_load_misses }, { .name = "DTLB_STORE_MISSES", .desc = "Data TLB store misses", .code = 0x49, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hsw_dtlb_load_misses), .umasks = hsw_dtlb_load_misses /* shared */ }, { .name = "FP_ASSIST", .desc = "X87 floating-point assists", .code = 0xca, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hsw_fp_assist), .umasks = hsw_fp_assist }, { .name = "HLE_RETIRED", .desc = "HLE execution (Precise Event)", .code = 0xc8, .cntmsk = 0xff, .ngrp = 1, .flags = INTEL_X86_PEBS, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hsw_hle_retired), .umasks = hsw_hle_retired }, { .name = "ICACHE", .desc = "Instruction Cache", .code = 0x80, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hsw_icache), .umasks = hsw_icache }, { .name = "IDQ", .desc = "IDQ operations", .code = 0x79, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hsw_idq), .umasks = hsw_idq }, { .name = "IDQ_UOPS_NOT_DELIVERED", .desc = "Uops not delivered", .code = 0x9c, .cntmsk = 0xf, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hsw_idq_uops_not_delivered), .umasks = hsw_idq_uops_not_delivered }, { .name = "INST_RETIRED", .desc = "Number of instructions retired (Precise Event)", .code = 0xc0, .cntmsk = 0xff, .ngrp = 1, .flags = INTEL_X86_PEBS, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hsw_inst_retired), .umasks = hsw_inst_retired }, { .name = "INT_MISC", .desc = "Miscellaneous interruptions", .code = 0xd, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hsw_int_misc), .umasks = hsw_int_misc }, { .name = "ITLB", .desc = "Instruction TLB", .code = 0xae, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hsw_itlb), .umasks = hsw_itlb }, { .name = "ITLB_MISSES", .desc = "Instruction TLB misses", .code = 0x85, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hsw_itlb_misses), .umasks = hsw_itlb_misses }, { .name = "L1D", .desc = "L1D cache", .code = 0x51, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hsw_l1d), .umasks = hsw_l1d }, { .name = "L1D_PEND_MISS", .desc = "L1D pending misses", .code = 0x48, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hsw_l1d_pend_miss), .umasks = hsw_l1d_pend_miss }, { .name = "L2_DEMAND_RQSTS", .desc = "Demand Data Read requests to L2", .code = 0x27, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hsw_l2_demand_rqsts), .umasks = hsw_l2_demand_rqsts }, { .name = "L2_LINES_IN", .desc = "L2 lines allocated", .code = 0xf1, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hsw_l2_lines_in), .umasks = hsw_l2_lines_in }, { .name = "L2_LINES_OUT", .desc = "L2 lines evicted", .code = 0xf2, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hsw_l2_lines_out), .umasks = hsw_l2_lines_out }, { .name = "L2_RQSTS", .desc = "L2 requests", .code = 0x24, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hsw_l2_rqsts), .umasks = hsw_l2_rqsts }, { .name = "L2_TRANS", .desc = "L2 transactions", .code = 0xf0, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hsw_l2_trans), .umasks = hsw_l2_trans }, { .name = "LD_BLOCKS", .desc = "Blocking loads", .code = 0x3, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hsw_ld_blocks), .umasks = hsw_ld_blocks }, { .name = "LD_BLOCKS_PARTIAL", .desc = "Partial load blocks", .code = 0x7, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hsw_ld_blocks_partial), .umasks = hsw_ld_blocks_partial }, { .name = "LOAD_HIT_PRE", .desc = "Load dispatches", .code = 0x4c, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hsw_load_hit_pre), .umasks = hsw_load_hit_pre }, { .name = "LOCK_CYCLES", .desc = "Locked cycles in L1D and L2", .code = 0x63, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hsw_lock_cycles), .umasks = hsw_lock_cycles }, { .name = "LONGEST_LAT_CACHE", .desc = "L3 cache", .code = 0x2e, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hsw_longest_lat_cache), .umasks = hsw_longest_lat_cache }, { .name = "MACHINE_CLEARS", .desc = "Machine clear asserted", .code = 0xc3, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hsw_machine_clears), .umasks = hsw_machine_clears }, { .name = "MEM_LOAD_UOPS_L3_HIT_RETIRED", .desc = "L3 hit load uops retired (Precise Event)", .code = 0xd2, .cntmsk = 0xf, .ngrp = 1, .flags = INTEL_X86_PEBS, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hsw_mem_load_uops_l3_hit_retired), .umasks = hsw_mem_load_uops_l3_hit_retired }, { .name = "MEM_LOAD_UOPS_LLC_HIT_RETIRED", .desc = "L3 hit load uops retired (Precise Event)", .equiv = "MEM_LOAD_UOPS_L3_HIT_RETIRED", .code = 0xd2, .cntmsk = 0xf, .ngrp = 1, .flags = INTEL_X86_PEBS, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hsw_mem_load_uops_l3_hit_retired), .umasks = hsw_mem_load_uops_l3_hit_retired }, { .name = "MEM_LOAD_UOPS_L3_MISS_RETIRED", .desc = "Load uops retired that missed the L3 (Precise Event)", .code = 0xd3, .cntmsk = 0xf, .ngrp = 1, .flags = INTEL_X86_PEBS, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hsw_mem_load_uops_l3_miss_retired), .umasks = hsw_mem_load_uops_l3_miss_retired }, { .name = "MEM_LOAD_UOPS_LLC_MISS_RETIRED", .desc = "Load uops retired that missed the L3 (Precise Event)", .equiv = "MEM_LOAD_UOPS_L3_MISS_RETIRED", .code = 0xd3, .cntmsk = 0xf, .ngrp = 1, .flags = INTEL_X86_PEBS, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hsw_mem_load_uops_l3_miss_retired), .umasks = hsw_mem_load_uops_l3_miss_retired }, { .name = "MEM_LOAD_UOPS_RETIRED", .desc = "Retired load uops (Precise Event)", .code = 0xd1, .cntmsk = 0xf, .ngrp = 1, .flags = INTEL_X86_PEBS, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hsw_mem_load_uops_retired), .umasks = hsw_mem_load_uops_retired }, { .name = "MEM_TRANS_RETIRED", .desc = "Memory transactions retired (Precise Event)", .code = 0xcd, .cntmsk = 0x8, .ngrp = 1, .flags = INTEL_X86_PEBS, .modmsk = INTEL_V4_ATTRS | _INTEL_X86_ATTR_LDLAT, .numasks = LIBPFM_ARRAY_SIZE(hsw_mem_trans_retired), .umasks = hsw_mem_trans_retired }, { .name = "MEM_UOPS_RETIRED", .desc = "Memory uops retired (Precise Event)", .code = 0xd0, .cntmsk = 0xf, .ngrp = 1, .flags = INTEL_X86_PEBS, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hsw_mem_uops_retired), .umasks = hsw_mem_uops_retired }, { .name = "MISALIGN_MEM_REF", .desc = "Misaligned memory references", .code = 0x5, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hsw_misalign_mem_ref), .umasks = hsw_misalign_mem_ref }, { .name = "MOVE_ELIMINATION", .desc = "Move Elimination", .code = 0x58, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hsw_move_elimination), .umasks = hsw_move_elimination }, { .name = "OFFCORE_REQUESTS", .desc = "Demand Data Read requests sent to uncore", .code = 0xb0, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hsw_offcore_requests), .umasks = hsw_offcore_requests }, { .name = "OTHER_ASSISTS", .desc = "Software assist", .code = 0xc1, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hsw_other_assists), .umasks = hsw_other_assists }, { .name = "RESOURCE_STALLS", .desc = "Cycles Allocation is stalled due to Resource Related reason", .code = 0xa2, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hsw_resource_stalls), .umasks = hsw_resource_stalls }, { .name = "ROB_MISC_EVENTS", .desc = "ROB miscellaneous events", .code = 0xcc, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hsw_rob_misc_events), .umasks = hsw_rob_misc_events }, { .name = "RS_EVENTS", .desc = "Reservation Station", .code = 0x5e, .cntmsk = 0xf, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hsw_rs_events), .umasks = hsw_rs_events }, { .name = "RTM_RETIRED", .desc = "Restricted Transaction Memory execution (Precise Event)", .code = 0xc9, .cntmsk = 0xf, .ngrp = 1, .flags = INTEL_X86_PEBS, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hsw_rtm_retired), .umasks = hsw_rtm_retired }, { .name = "TLB_FLUSH", .desc = "TLB flushes", .code = 0xbd, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hsw_tlb_flush), .umasks = hsw_tlb_flush }, { .name = "UOPS_EXECUTED", .desc = "Uops executed", .code = 0xb1, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hsw_uops_executed), .umasks = hsw_uops_executed }, { .name = "LSD", .desc = "Loop stream detector", .code = 0xa8, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hsw_lsd), .umasks = hsw_lsd, }, { .name = "UOPS_EXECUTED_PORT", .desc = "Uops dispatched to specific ports", .code = 0xa1, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hsw_uops_executed_port), .umasks = hsw_uops_executed_port }, { .name = "UOPS_DISPATCHED_PORT", .desc = "Uops dispatched to specific ports", .code = 0xa1, .cntmsk = 0xff, .ngrp = 1, .equiv = "UOPS_EXECUTED_PORT", .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hsw_uops_executed_port), .umasks = hsw_uops_executed_port }, { .name = "UOPS_ISSUED", .desc = "Uops issued", .code = 0xe, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hsw_uops_issued), .umasks = hsw_uops_issued }, { .name = "UOPS_RETIRED", .desc = "Uops retired (Precise Event)", .code = 0xc2, .cntmsk = 0xff, .ngrp = 1, .flags = INTEL_X86_PEBS, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hsw_uops_retired), .umasks = hsw_uops_retired }, { .name = "TX_MEM", .desc = "Transactional memory aborts", .code = 0x54, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hsw_tx_mem), .umasks = hsw_tx_mem, }, { .name = "TX_EXEC", .desc = "Transactional execution", .code = 0x5d, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hsw_tx_exec), .umasks = hsw_tx_exec }, { .name = "OFFCORE_REQUESTS_OUTSTANDING", .desc = "Outstanding offcore requests", .modmsk = INTEL_V4_ATTRS, .cntmsk = 0xff, .code = 0x60, .numasks = LIBPFM_ARRAY_SIZE(hsw_offcore_requests_outstanding), .ngrp = 1, .umasks = hsw_offcore_requests_outstanding, }, { .name = "ILD_STALL", .desc = "Instruction Length Decoder stalls", .modmsk = INTEL_V4_ATTRS, .cntmsk = 0xff, .code = 0x87, .numasks = LIBPFM_ARRAY_SIZE(hsw_ild_stall), .ngrp = 1, .umasks = hsw_ild_stall, }, { .name = "PAGE_WALKER_LOADS", .desc = "Page walker loads", .modmsk = INTEL_V4_ATTRS, .cntmsk = 0xf, .code = 0xbc, .numasks = LIBPFM_ARRAY_SIZE(hsw_page_walker_loads), .ngrp = 1, .umasks = hsw_page_walker_loads, }, { .name = "DSB2MITE_SWITCHES", .desc = "Number of DSB to MITE switches", .modmsk = INTEL_V4_ATTRS, .cntmsk = 0xff, .code = 0xab, .numasks = LIBPFM_ARRAY_SIZE(hsw_dsb2mite_switches), .ngrp = 1, .umasks = hsw_dsb2mite_switches, }, { .name = "EPT", .desc = "Extended page table", .modmsk = INTEL_V4_ATTRS, .cntmsk = 0xff, .code = 0x4f, .numasks = LIBPFM_ARRAY_SIZE(hsw_ept), .ngrp = 1, .umasks = hsw_ept, }, { .name = "ARITH", .desc = "Counts arithmetic multiply operations", .modmsk = INTEL_V4_ATTRS, .cntmsk = 0xff, .code = 0x14, .numasks = LIBPFM_ARRAY_SIZE(hsw_arith), .ngrp = 1, .umasks = hsw_arith, }, { .name = "AVX", .desc = "Counts AVX instructions", .modmsk = INTEL_V4_ATTRS, .cntmsk = 0xff, .code = 0xc6, .numasks = LIBPFM_ARRAY_SIZE(hsw_avx), .ngrp = 1, .umasks = hsw_avx, }, { .name = "SQ_MISC", .desc = "SuperQueue miscellaneous", .modmsk = INTEL_V4_ATTRS, .cntmsk = 0xf, .code = 0xf4, .numasks = LIBPFM_ARRAY_SIZE(hsw_sq_misc), .ngrp = 1, .umasks = hsw_sq_misc, }, { .name = "OFFCORE_REQUESTS_BUFFER", .desc = "Offcore reqest buffer", .modmsk = INTEL_V4_ATTRS, .cntmsk = 0xff, .code = 0xb2, .numasks = LIBPFM_ARRAY_SIZE(hsw_offcore_requests_buffer), .ngrp = 1, .umasks = hsw_offcore_requests_buffer, }, { .name = "OFFCORE_RESPONSE_0", .desc = "Offcore response event (must provide at least one request type and either any_response or any combination of supplier + snoop)", .modmsk = INTEL_V4_ATTRS, .cntmsk = 0xf, .code = 0x1b7, .flags= INTEL_X86_NHM_OFFCORE, .numasks = LIBPFM_ARRAY_SIZE(hsw_offcore_response), .ngrp = 3, .umasks = hsw_offcore_response, }, { .name = "OFFCORE_RESPONSE_1", .desc = "Offcore response event (must provide at least one request type and either any_response or any combination of supplier + snoop)", .modmsk = INTEL_V4_ATTRS, .cntmsk = 0xf, .code = 0x1bb, .flags= INTEL_X86_NHM_OFFCORE, .numasks = LIBPFM_ARRAY_SIZE(hsw_offcore_response), .ngrp = 3, .umasks = hsw_offcore_response, /* identical to actual umasks list for this event */ }, }; libpfm-4.9.0/lib/events/intel_bdw_events.h0000664000175000017500000030617013223402656020403 0ustar eranianeranian/* * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * PMU: bdw (Intel Broadwell) */ static const intel_x86_umask_t bdw_baclears[]={ { .uname = "ANY", .udesc = "Number of front-end re-steers due to BPU misprediction", .ucode = 0x1f00, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t bdw_br_inst_exec[]={ { .uname = "NONTAKEN_CONDITIONAL", .udesc = "All macro conditional nontaken branch instructions", .ucode = 0x4100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "NONTAKEN_COND", .udesc = "All macro conditional nontaken branch instructions", .ucode = 0x4100, .uequiv = "NONTAKEN_CONDITIONAL", .uflags = INTEL_X86_NCOMBO, }, { .uname = "TAKEN_CONDITIONAL", .udesc = "Taken speculative and retired macro-conditional branches", .ucode = 0x8100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "TAKEN_COND", .udesc = "Taken speculative and retired macro-conditional branches", .ucode = 0x8100, .uequiv = "TAKEN_CONDITIONAL", .uflags = INTEL_X86_NCOMBO, }, { .uname = "TAKEN_DIRECT_JUMP", .udesc = "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects", .ucode = 0x8200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "TAKEN_INDIRECT_JUMP_NON_CALL_RET", .udesc = "Taken speculative and retired indirect branches excluding calls and returns", .ucode = 0x8400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "TAKEN_INDIRECT_NEAR_RETURN", .udesc = "Taken speculative and retired indirect branches with return mnemonic", .ucode = 0x8800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "TAKEN_DIRECT_NEAR_CALL", .udesc = "Taken speculative and retired direct near calls", .ucode = 0x9000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ALL_CONDITIONAL", .udesc = "Speculative and retired macro-conditional branches", .ucode = 0xc100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ALL_COND", .udesc = "Speculative and retired macro-conditional branches", .ucode = 0xc100, .uequiv = "ALL_CONDITIONAL", .uflags = INTEL_X86_NCOMBO, }, { .uname = "ANY_COND", .udesc = "Speculative and retired macro-conditional branches", .ucode = 0xc100, .uequiv = "ALL_CONDITIONAL", .uflags = INTEL_X86_NCOMBO, }, { .uname = "ALL_DIRECT_JMP", .udesc = "Speculative and retired macro-unconditional branches excluding calls and indirects", .ucode = 0xc200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ALL_INDIRECT_JUMP_NON_CALL_RET", .udesc = "Speculative and retired indirect branches excluding calls and returns", .ucode = 0xc400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ALL_INDIRECT_NEAR_RETURN", .udesc = "Speculative and retired indirect return branches", .ucode = 0xc800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ALL_DIRECT_NEAR_CALL", .udesc = "Speculative and retired direct near calls", .ucode = 0xd000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "TAKEN_INDIRECT_NEAR_CALL", .udesc = "All indirect calls, including both register and memory indirect", .ucode = 0xa000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ALL_BRANCHES", .udesc = "All branch instructions executed", .ucode = 0xff00, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t bdw_br_inst_retired[]={ { .uname = "CONDITIONAL", .udesc = "Counts all taken and not taken macro conditional branch instructions", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "COND", .udesc = "Counts all taken and not taken macro conditional branch instructions", .ucode = 0x100, .uequiv = "CONDITIONAL", .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "NEAR_CALL", .udesc = "Counts all macro direct and indirect near calls", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "ALL_BRANCHES", .udesc = "Counts all taken and not taken macro branches including far branches (architectural event)", .ucode = 0x0, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL | INTEL_X86_PEBS, }, { .uname = "NEAR_RETURN", .udesc = "Counts the number of near ret instructions retired", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "NOT_TAKEN", .udesc = "Counts all not taken macro branch instructions retired", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "NEAR_TAKEN", .udesc = "Counts the number of near branch taken instructions retired", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "FAR_BRANCH", .udesc = "Counts the number of far branch instructions retired", .ucode = 0x4000, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, }; static const intel_x86_umask_t bdw_br_misp_exec[]={ { .uname = "NONTAKEN_CONDITIONAL", .udesc = "Not taken speculative and retired mispredicted macro conditional branches", .ucode = 0x4100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "NONTAKEN_COND", .udesc = "Not taken speculative and retired mispredicted macro conditional branches", .ucode = 0x4100, .uequiv = "NONTAKEN_CONDITIONAL", .uflags = INTEL_X86_NCOMBO, }, { .uname = "TAKEN_CONDITIONAL", .udesc = "Taken speculative and retired mispredicted macro conditional branches", .ucode = 0x8100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "TAKEN_COND", .udesc = "Taken speculative and retired mispredicted macro conditional branches", .ucode = 0x8100, .uequiv = "TAKEN_CONDITIONAL", .uflags = INTEL_X86_NCOMBO, }, { .uname = "TAKEN_INDIRECT_JUMP_NON_CALL_RET", .udesc = "Taken speculative and retired mispredicted indirect branches excluding calls and returns", .ucode = 0x8400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ALL_CONDITIONAL", .udesc = "Speculative and retired mispredicted macro conditional branches", .ucode = 0xc100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ANY_COND", .udesc = "Speculative and retired mispredicted macro conditional branches", .ucode = 0xc100, .uequiv = "ALL_CONDITIONAL", .uflags = INTEL_X86_NCOMBO, }, { .uname = "ALL_INDIRECT_JUMP_NON_CALL_RET", .udesc = "All mispredicted indirect branches that are not calls nor returns", .ucode = 0xc400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ALL_BRANCHES", .udesc = "Speculative and retired mispredicted macro conditional branches", .ucode = 0xff00, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "TAKEN_INDIRECT_NEAR_CALL", .udesc = "Taken speculative and retired mispredicted indirect calls", .ucode = 0xa000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "TAKEN_RETURN_NEAR", .udesc = "Taken speculative and retired mispredicted direct returns", .ucode = 0x8800, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t bdw_br_misp_retired[]={ { .uname = "CONDITIONAL", .udesc = "All mispredicted macro conditional branch instructions", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "COND", .udesc = "All mispredicted macro conditional branch instructions", .ucode = 0x100, .uequiv = "CONDITIONAL", .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "ALL_BRANCHES", .udesc = "All mispredicted macro branches (architectural event)", .ucode = 0x0, /* architectural encoding */ .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS | INTEL_X86_DFL, }, { .uname = "NEAR_TAKEN", .udesc = "Number of near branch instructions retired that were mispredicted and taken", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "RET", .udesc = "Number of mispredicted ret instructions retired", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, }; static const intel_x86_umask_t bdw_cpl_cycles[]={ { .uname = "RING0", .udesc = "Unhalted core cycles when the thread is in ring 0", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "RING123", .udesc = "Unhalted core cycles when thread is in rings 1, 2, or 3", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "RING0_TRANS", .udesc = "Number of intervals between processor halts while thread is in ring 0", .ucode = 0x100 | INTEL_X86_MOD_EDGE | (1 << INTEL_X86_CMASK_BIT), /* edge=1 cnt=1 */ .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_E | _INTEL_X86_ATTR_C, }, }; static const intel_x86_umask_t bdw_cpu_clk_thread_unhalted[]={ { .uname = "REF_XCLK", .udesc = "Count Xclk pulses (100Mhz) when the core is unhalted", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "REF_XCLK_ANY", .udesc = "Count Xclk pulses (100Mhz) when the at least one thread on the physical core is unhalted", .ucode = 0x100 | INTEL_X86_MOD_ANY, /* any=1 */ .uequiv = "REF_XCLK:t", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_T, }, { .uname = "REF_P", .udesc = "Cycles when the core is unhalted (count at 100 Mhz)", .ucode = 0x100, .uequiv = "REF_XCLK", .uflags= INTEL_X86_NCOMBO, }, { .uname = "THREAD_P", .udesc = "Cycles when thread is not halted", .ucode = 0x000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "ONE_THREAD_ACTIVE", .udesc = "Counts Xclk (100Mhz) pulses when this thread is unhalted and the other thread is halted", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t bdw_cycle_activity[]={ { .uname = "CYCLES_L2_PENDING", .udesc = "Cycles with pending L2 miss loads (must use with HT off only)", .ucode = 0x0100 | (0x1 << INTEL_X86_CMASK_BIT), .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, .ucntmsk= 0xf, }, { .uname = "CYCLES_LDM_PENDING", .udesc = "Cycles with pending memory loads", .ucode = 0x0200 | (0x2 << INTEL_X86_CMASK_BIT), .modhw = _INTEL_X86_ATTR_C, .uequiv = "CYCLES_MEM_ANY", .uflags = INTEL_X86_NCOMBO, }, { .uname = "CYCLES_MEM_ANY", .udesc = "Cycles with pending memory loads", .ucode = 0x0200 | (0x2 << INTEL_X86_CMASK_BIT), .modhw = _INTEL_X86_ATTR_C, .uflags = INTEL_X86_NCOMBO, }, { .uname = "CYCLES_L1D_PENDING", .udesc = "Cycles with pending L1D load cache misses", .ucode = 0x0800 | (0x8 << INTEL_X86_CMASK_BIT), .modhw = _INTEL_X86_ATTR_C, .ucntmsk= 0x4, .uflags = INTEL_X86_NCOMBO, }, { .uname = "STALLS_LDM_PENDING", .udesc = "Executions stalls when there is at least one pending demand load request", .ucode = 0x0600 | (0x6 << INTEL_X86_CMASK_BIT), .modhw = _INTEL_X86_ATTR_C, .ucntmsk= 0x4, .uflags = INTEL_X86_NCOMBO, }, { .uname = "STALLS_L1D_PENDING", .udesc = "Executions stalls while there is at least one L1D demand load outstanding", .ucode = 0x0c00 | (0xc << INTEL_X86_CMASK_BIT), .modhw = _INTEL_X86_ATTR_C, .ucntmsk= 0x4, .uflags = INTEL_X86_NCOMBO, }, { .uname = "STALLS_L2_PENDING", .udesc = "Execution stalls while there is at least one L2 demand load pending outstanding", .ucode = 0x0500 | (0x5 << INTEL_X86_CMASK_BIT), .modhw = _INTEL_X86_ATTR_C, .ucntmsk= 0xf, .uflags = INTEL_X86_NCOMBO, }, { .uname = "STALLS_TOTAL", .udesc = "Cycles during which no instructions were executed in the execution stage of the pipeline", .ucode = 0x0400 | (0x4 << INTEL_X86_CMASK_BIT), .modhw = _INTEL_X86_ATTR_C, .ucntmsk= 0xf, .uflags = INTEL_X86_NCOMBO, }, { .uname = "CYCLES_NO_EXECUTE", .udesc = "Cycles during which no instructions were executed in the execution stage of the pipeline", .ucode = 0x0400 | (0x4 << INTEL_X86_CMASK_BIT), .modhw = _INTEL_X86_ATTR_C, .uequiv = "STALLS_TOTAL", .ucntmsk= 0xf, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t bdw_dtlb_load_misses[]={ { .uname = "MISS_CAUSES_A_WALK", .udesc = "Misses in all DTLB levels that cause page walks", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "WALK_COMPLETED_4K", .udesc = "Misses in all TLB levels causes a page walk that completes (4K)", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "WALK_COMPLETED_2M_4M", .udesc = "Misses in all TLB levels causes a page walk of 2MB/4MB page sizes that completes", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "WALK_COMPLETED_1G", .udesc = "Misses in all TLB levels causes a page walk of 1GB page sizes that completes", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "WALK_COMPLETED", .udesc = "Misses in all TLB levels causes a page walk of any page size that completes", .ucode = 0xe00, .uflags = INTEL_X86_NCOMBO, }, { .uname = "WALK_DURATION", .udesc = "Cycles when PMH is busy with page walks", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "STLB_HIT_4K", .udesc = "Misses that miss the DTLB and hit the STLB (4KB)", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "STLB_HIT_2M", .udesc = "Misses that miss the DTLB and hit the STLB (2MB)", .ucode = 0x4000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "STLB_HIT", .udesc = "Number of cache load STLB hits. No page walk", .ucode = 0x6000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t bdw_itlb_misses[]={ { .uname = "MISS_CAUSES_A_WALK", .udesc = "Misses in all DTLB levels that cause page walks", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "WALK_COMPLETED_4K", .udesc = "Misses in all TLB levels causes a page walk that completes (4KB)", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "WALK_COMPLETED_2M_4M", .udesc = "Misses in all TLB levels causes a page walk that completes (2MB/4MB)", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "WALK_COMPLETED_1G", .udesc = "Misses in all TLB levels causes a page walk that completes (1GB)", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "WALK_COMPLETED", .udesc = "Misses in all TLB levels causes a page walk of any page size that completes", .ucode = 0xe00, .uflags = INTEL_X86_NCOMBO, }, { .uname = "WALK_DURATION", .udesc = "Cycles when PMH is busy with page walks", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "STLB_HIT_4K", .udesc = "Misses that miss the DTLB and hit the STLB (4KB)", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "STLB_HIT_2M", .udesc = "Misses that miss the DTLB and hit the STLB (2MB)", .ucode = 0x4000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "STLB_HIT", .udesc = "Number of cache load STLB hits. No page walk", .ucode = 0x6000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t bdw_fp_assist[]={ { .uname = "X87_OUTPUT", .udesc = "Number of X87 FP assists due to output values", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "X87_INPUT", .udesc = "Number of X87 FP assists due to input values", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "SIMD_OUTPUT", .udesc = "Number of SIMD FP assists due to output values", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "SIMD_INPUT", .udesc = "Number of SIMD FP assists due to input values", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ANY", .udesc = "Cycles with any input/output SEE or FP assists", .ucode = 0x1e00 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */ .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "ALL", .udesc = "Cycles with any input and output SSE or FP assist", .ucode = 0x1e00 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */ .uequiv = "ANY", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, }; static const intel_x86_umask_t bdw_icache[]={ { .uname = "MISSES", .udesc = "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "IFDATA_STALL", .udesc = "Number of cycles where a code fetch is stalled due to L1 miss", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "HIT", .udesc = "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. Includes cacheable and uncacheable accesses and uncacheable fetches", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t bdw_idq[]={ { .uname = "EMPTY", .udesc = "Cycles the Instruction Decode Queue (IDQ) is empty", .ucode = 0x200, .ucntmsk= 0xf, .uflags = INTEL_X86_NCOMBO, }, { .uname = "MITE_UOPS", .udesc = "Number of uops delivered to Instruction Decode Queue (IDQ) from MITE path", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "DSB_UOPS", .udesc = "Number of uops delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "MS_DSB_UOPS", .udesc = "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "MS_MITE_UOPS", .udesc = "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "MS_UOPS", .udesc = "Number of Uops were delivered into Instruction Decode Queue (IDQ) from MS, initiated by Decode Stream Buffer (DSB) or MITE", .ucode = 0x3000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "MS_UOPS_CYCLES", .udesc = "Number of cycles that Uops were delivered into Instruction Decode Queue (IDQ) when MS_Busy, initiated by Decode Stream Buffer (DSB) or MITE", .ucode = 0x3000 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */ .uequiv = "MS_UOPS:c=1", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "MS_SWITCHES", .udesc = "Number of cycles that Uops were delivered into Instruction Decode Queue (IDQ) when MS_Busy, initiated by Decode Stream Buffer (DSB) or MITE", .ucode = 0x3000 | INTEL_X86_MOD_EDGE | (1 << INTEL_X86_CMASK_BIT), /* edge=1 cnt=1 */ .uequiv = "MS_UOPS:c=1:e", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_E | _INTEL_X86_ATTR_C, }, { .uname = "MITE_UOPS_CYCLES", .udesc = "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path", .ucode = 0x400 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */ .uequiv = "MITE_UOPS:c=1", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "DSB_UOPS_CYCLES", .udesc = "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", .ucode = 0x800 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */ .uequiv = "DSB_UOPS:c=1", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "MS_DSB_UOPS_CYCLES", .udesc = "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", .ucode = 0x1000 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */ .uequiv = "MS_DSB_UOPS:c=1", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "MS_DSB_OCCUR", .udesc = "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is busy", .ucode = 0x1000 | INTEL_X86_MOD_EDGE | (1 << INTEL_X86_CMASK_BIT), /* edge=1 cnt=1 */ .uequiv = "MS_DSB_UOPS:c=1:e=1", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_E | _INTEL_X86_ATTR_C, }, { .uname = "ALL_DSB_CYCLES_4_UOPS", .udesc = "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", .ucode = 0x1800 | (4 << INTEL_X86_CMASK_BIT), /* cnt=4 */ .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "ALL_DSB_CYCLES_ANY_UOPS", .udesc = "Cycles Decode Stream Buffer (DSB) is delivering any Uop", .ucode = 0x1800 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */ .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "ALL_MITE_CYCLES_4_UOPS", .udesc = "Cycles MITE is delivering 4 Uops", .ucode = 0x2400 | (4 << INTEL_X86_CMASK_BIT), /* cnt=4 */ .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "ALL_MITE_CYCLES_ANY_UOPS", .udesc = "Cycles MITE is delivering any Uop", .ucode = 0x2400 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */ .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "ALL_MITE_UOPS", .udesc = "Number of uops delivered to Instruction Decode Queue (IDQ) from any path", .ucode = 0x3c00, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t bdw_idq_uops_not_delivered[]={ { .uname = "CORE", .udesc = "Count number of non-delivered uops to Resource Allocation Table (RAT)", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "CYCLES_0_UOPS_DELIV_CORE", .udesc = "Cycles per thread when 4 or more uops are not delivered to the Resource Allocation Table (RAT) when backend is not stalled", .ucode = 0x100 | (4 << INTEL_X86_CMASK_BIT), /* cnt=4 */ .uflags = INTEL_X86_NCOMBO, .uequiv = "CORE:c=4", .modhw = _INTEL_X86_ATTR_C, }, { .uname = "CYCLES_LE_1_UOP_DELIV_CORE", .udesc = "Cycles per thread when 3 or more uops are not delivered to the Resource Allocation Table (RAT) when backend is not stalled", .ucode = 0x100 | (3 << INTEL_X86_CMASK_BIT), /* cnt=3 */ .uequiv = "CORE:c=3", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "CYCLES_LE_2_UOP_DELIV_CORE", .udesc = "Cycles with less than 2 uops delivered by the front end", .ucode = 0x100 | (2 << INTEL_X86_CMASK_BIT), /* cnt=2 */ .uequiv = "CORE:c=2", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "CYCLES_LE_3_UOP_DELIV_CORE", .udesc = "Cycles with less than 3 uops delivered by the front end", .ucode = 0x100 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */ .uequiv = "CORE:c=1", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "CYCLES_FE_WAS_OK", .udesc = "Cycles Front-End (FE) delivered 4 uops or Resource Allocation Table (RAT) was stalling FE", .ucode = 0x100 | INTEL_X86_MOD_INV | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 inv=1 */ .uequiv = "CORE:c=1:i", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C | _INTEL_X86_ATTR_I, }, }; static const intel_x86_umask_t bdw_inst_retired[]={ { .uname = "ANY_P", .udesc = "Number of instructions retired. General Counter - architectural event", .ucode = 0x000, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "ALL", .udesc = "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution (Precise Event)", .ucode = 0x100, .uequiv = "PREC_DIST", .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "TOTAL_CYCLES", .udesc = "Number of cycles using always true condition", .ucode = 0x100 | INTEL_X86_MOD_INV | (10 << INTEL_X86_CMASK_BIT), /* inv=1 cnt=10 */ .uequiv = "PREC_DIST:i=1:c=10", .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, .modhw = _INTEL_X86_ATTR_I | _INTEL_X86_ATTR_C, }, { .uname = "PREC_DIST", .udesc = "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution (Precise event)", .ucode = 0x100, .ucntmsk= 0x2, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "X87", .udesc = "Number of FPU operations retired (instructions with no exceptions)", .ucode = 0x200, .ucntmsk= 0x2, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t bdw_int_misc[]={ { .uname = "RECOVERY_CYCLES", .udesc = "Cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...)", .ucode = 0x300 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */ .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "RECOVERY_CYCLES_ANY", .udesc = "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke)", .ucode = 0x300 | (1 << INTEL_X86_CMASK_BIT) | INTEL_X86_MOD_ANY, /* cnt=1 any=1 */ .uequiv = "RECOVERY_CYCLES:t", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C | _INTEL_X86_ATTR_T, }, { .uname = "RECOVERY_STALLS_COUNT", .udesc = "Number of occurrences waiting for Machine Clears", .ucode = 0x300 | INTEL_X86_MOD_EDGE | (1 << INTEL_X86_CMASK_BIT), /* edge=1 cnt=1 */ .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_E | _INTEL_X86_ATTR_C, }, { .uname = "RAT_STALL_CYCLES", .udesc = "Cycles when the Resource Allocation Table (RAT) external stall event is sent to the Instruction Decode Queue (IDQ) for the thread. Also includes cycles when the allocator is serving another thread", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t bdw_itlb[]={ { .uname = "ITLB_FLUSH", .udesc = "Flushing of the Instruction TLB (ITLB) pages independent of page size", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t bdw_l1d[]={ { .uname = "REPLACEMENT", .udesc = "L1D Data line replacements", .ucode = 0x100, .uflags = INTEL_X86_DFL, }, }; static const intel_x86_umask_t bdw_sq_misc[]={ { .uname = "SPLIT_LOCK", .udesc = "Number of split locks in the super queue (SQ)", .ucode = 0x1000, .uflags = INTEL_X86_DFL, }, }; static const intel_x86_umask_t bdw_l1d_pend_miss[]={ { .uname = "PENDING", .udesc = "Cycles with L1D load misses outstanding", .ucode = 0x100, .ucntmsk = 0x4, .uflags = INTEL_X86_DFL, }, { .uname = "PENDING_CYCLES", .udesc = "Cycles with L1D load misses outstanding", .ucode = 0x100 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */ .uequiv = "PENDING:c=1", .ucntmsk = 0x4, .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "PENDING_CYCLES_ANY", .udesc = "Cycles with L1D load misses outstanding from any thread", .ucode = 0x100 | (1 << INTEL_X86_CMASK_BIT) | INTEL_X86_MOD_ANY, /* cnt=1 any=1 */ .uequiv = "PENDING:c=1:t", .ucntmsk = 0x4, .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C | _INTEL_X86_ATTR_T, }, { .uname = "OCCURRENCES", .udesc = "Number L1D miss outstanding", .ucode = 0x100 | INTEL_X86_MOD_EDGE | (1 << INTEL_X86_CMASK_BIT), /* edge=1 cnt=1 */ .uequiv = "PENDING:c=1:e=1", .ucntmsk = 0x4, .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_E | _INTEL_X86_ATTR_C, }, { .uname = "EDGE", .udesc = "Number L1D miss outstanding", .ucode = 0x100 | INTEL_X86_MOD_EDGE | (1 << INTEL_X86_CMASK_BIT), /* edge=1 cnt=1 */ .uequiv = "PENDING:c=1:e=1", .ucntmsk = 0x4, .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_E | _INTEL_X86_ATTR_C, }, { .uname = "FB_FULL", .udesc = "Number of cycles a demand request was blocked due to Fill Buffer (FB) unavailability", .ucode = 0x200 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */ .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, }; static const intel_x86_umask_t bdw_l2_demand_rqsts[]={ { .uname = "WB_HIT", .udesc = "WB requests that hit L2 cache", .ucode = 0x5000, .uflags = INTEL_X86_DFL, }, }; static const intel_x86_umask_t bdw_l2_lines_in[]={ { .uname = "I", .udesc = "L2 cache lines in I state filling L2", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "S", .udesc = "L2 cache lines in S state filling L2", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "E", .udesc = "L2 cache lines in E state filling L2", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ALL", .udesc = "L2 cache lines filling L2", .ucode = 0x700, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "ANY", .udesc = "L2 cache lines filling L2", .uequiv = "ALL", .ucode = 0x700, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t bdw_l2_lines_out[]={ { .uname = "DEMAND_CLEAN", .udesc = "Number of clean L2 cachelines evicted by demand", .ucode = 0x500, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t bdw_l2_rqsts[]={ { .uname = "DEMAND_DATA_RD_MISS", .udesc = "Demand Data Read requests that miss L2 cache", .ucode = 0x2100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "DEMAND_DATA_RD_HIT", .udesc = "Demand Data Read requests that hit L2 cache", .ucode = 0x4100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "DEMAND_RFO_MISS", .udesc = "RFO requests that miss L2 cache", .ucode = 0x2200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "RFO_MISS", .udesc = "RFO requests that miss L2 cache", .ucode = 0x2200, .uequiv = "DEMAND_RFO_MISS", .uflags = INTEL_X86_NCOMBO, }, { .uname = "DEMAND_RFO_HIT", .udesc = "RFO requests that hit L2 cache", .ucode = 0x4200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "RFO_HIT", .udesc = "RFO requests that hit L2 cache", .ucode = 0x4200, .uequiv = "DEMAND_RFO_HIT", .uflags = INTEL_X86_NCOMBO, }, { .uname = "CODE_RD_MISS", .udesc = "L2 cache misses when fetching instructions", .ucode = 0x2400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ALL_DEMAND_MISS", .udesc = "All demand requests that miss the L2 cache", .ucode = 0x2700, .uflags = INTEL_X86_NCOMBO, }, { .uname = "CODE_RD_HIT", .udesc = "L2 cache hits when fetching instructions, code reads", .ucode = 0x4400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "L2_PF_MISS", .udesc = "Requests from the L2 hardware prefetchers that miss L2 cache", .ucode = 0x3800, .uequiv = "PF_MISS", .uflags = INTEL_X86_NCOMBO, }, { .uname = "PF_MISS", .udesc = "Requests from the L2 hardware prefetchers that miss L2 cache", .ucode = 0x3800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "MISS", .udesc = "All requests that miss the L2 cache", .ucode = 0x3f00, .uflags = INTEL_X86_NCOMBO, }, { .uname = "L2_PF_HIT", .udesc = "Requests from the L2 hardware prefetchers that hit L2 cache", .ucode = 0xd800, .uequiv = "PF_HIT", .uflags = INTEL_X86_NCOMBO, }, { .uname = "PF_HIT", .udesc = "Requests from the L2 hardware prefetchers that hit L2 cache", .ucode = 0xd800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ALL_DEMAND_DATA_RD", .udesc = "Any data read request to L2 cache", .ucode = 0xe100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ALL_RFO", .udesc = "Any data RFO request to L2 cache", .ucode = 0xe200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ALL_CODE_RD", .udesc = "Any code read request to L2 cache", .ucode = 0xe400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ALL_DEMAND_REFERENCES", .udesc = "All demand requests to L2 cache ", .ucode = 0xe700, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ALL_PF", .udesc = "Any L2 HW prefetch request to L2 cache", .ucode = 0xf800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "REFERENCES", .udesc = "All requests to L2 cache", .ucode = 0xff00, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t bdw_l2_trans[]={ { .uname = "DEMAND_DATA_RD", .udesc = "Demand Data Read requests that access L2 cache", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "RFO", .udesc = "RFO requests that access L2 cache", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "CODE_RD", .udesc = "L2 cache accesses when fetching instructions", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ALL_PF", .udesc = "L2 or L3 HW prefetches that access L2 cache, including rejects", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "L1D_WB", .udesc = "L1D writebacks that access L2 cache", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "L2_FILL", .udesc = "L2 fill requests that access L2 cache", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "L2_WB", .udesc = "L2 writebacks that access L2 cache", .ucode = 0x4000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ALL_REQUESTS", .udesc = "Transactions accessing L2 pipe", .ucode = 0x8000, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t bdw_ld_blocks[]={ { .uname = "STORE_FORWARD", .udesc = "Counts the number of loads blocked by overlapping with store buffer entries that cannot be forwarded", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "NO_SR", .udesc = "number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t bdw_ld_blocks_partial[]={ { .uname = "ADDRESS_ALIAS", .udesc = "False dependencies in MOB due to partial compare on address", .ucode = 0x100, .uflags = INTEL_X86_DFL, }, }; static const intel_x86_umask_t bdw_load_hit_pre[]={ { .uname = "HW_PF", .udesc = "Non software-prefetch load dispatches that hit FB allocated for hardware prefetch", .ucode = 0x200, }, { .uname = "SW_PF", .udesc = "Non software-prefetch load dispatches that hit FB allocated for software prefetch", .ucode = 0x100, }, }; static const intel_x86_umask_t bdw_lock_cycles[]={ { .uname = "SPLIT_LOCK_UC_LOCK_DURATION", .udesc = "Cycles in which the L1D and L2 are locked, due to a UC lock or split lock", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "CACHE_LOCK_DURATION", .udesc = "cycles that the L1D is locked", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t bdw_longest_lat_cache[]={ { .uname = "MISS", .udesc = "Core-originated cacheable demand requests missed LLC - architectural event", .ucode = 0x4100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "REFERENCE", .udesc = "Core-originated cacheable demand requests that refer to LLC - architectural event", .ucode = 0x4f00, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t bdw_machine_clears[]={ { .uname = "CYCLES", .udesc = "Cycles there was a Nuke. Account for both thread-specific and All Thread Nukes", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "MEMORY_ORDERING", .udesc = "Number of Memory Ordering Machine Clears detected", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "SMC", .udesc = "Number of Self-modifying code (SMC) Machine Clears detected", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "MASKMOV", .udesc = "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "COUNT", .udesc = "Number of machine clears (nukes) of any type", .ucode = 0x100 | INTEL_X86_MOD_EDGE | (1 << INTEL_X86_CMASK_BIT), /* edge=1 cnt=1 */ .uequiv = "CYCLES:c=1:e", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_E | _INTEL_X86_ATTR_C, }, }; static const intel_x86_umask_t bdw_mem_load_uops_l3_hit_retired[]={ { .uname = "XSNP_MISS", .udesc = "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "XSNP_HIT", .udesc = "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "XSNP_HITM", .udesc = "Load had HitM Response from a core on same socket (shared L3). (Non PEBS", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "XSNP_NONE", .udesc = "Retired load uops which data sources were hits in L3 without snoops required", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, }; static const intel_x86_umask_t bdw_mem_load_uops_l3_miss_retired[]={ { .uname = "LOCAL_DRAM", .udesc = "Retired load uops missing L3 cache but hitting local memory (Precise Event)", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS , }, { .uname = "REMOTE_DRAM", .udesc = "Number of retired load uops that missed L3 but were service by remote RAM, snoop not needed, snoop miss, snoop hit data not forwarded (Precise Event)", .ucode = 0x400, .umodel = PFM_PMU_INTEL_BDW_EP, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "REMOTE_HITM", .udesc = "Number of retired load uops whose data sources was remote HITM (Precise Event)", .ucode = 0x1000, .umodel = PFM_PMU_INTEL_BDW_EP, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "REMOTE_FWD", .udesc = "Load uops that miss in the L3 whose data source was forwarded from a remote cache (Precise Event)", .ucode = 0x2000, .umodel = PFM_PMU_INTEL_BDW_EP, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, }; static const intel_x86_umask_t bdw_mem_load_uops_retired[]={ { .uname = "L1_HIT", .udesc = "Retired load uops with L1 cache hits as data source", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "L2_HIT", .udesc = "Retired load uops with L2 cache hits as data source", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "L3_HIT", .udesc = "Retired load uops with L3 cache hits as data source", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "L1_MISS", .udesc = "Retired load uops which missed the L1D", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "L2_MISS", .udesc = "Retired load uops which missed the L2. Unknown data source excluded", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "L3_MISS", .udesc = "Retired load uops which missed the L3", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "HIT_LFB", .udesc = "Retired load uops which missed L1 but hit line fill buffer (LFB)", .ucode = 0x4000, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, }; static const intel_x86_umask_t bdw_mem_trans_retired[]={ { .uname = "LOAD_LATENCY", .udesc = "Memory load instructions retired above programmed clocks, minimum threshold value is 3 (Precise Event and ldlat required)", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS | INTEL_X86_LDLAT | INTEL_X86_DFL, }, { .uname = "LATENCY_ABOVE_THRESHOLD", .udesc = "Memory load instructions retired above programmed clocks, minimum threshold value is 3 (Precise Event and ldlat required)", .ucode = 0x100, .uequiv = "LOAD_LATENCY", .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS | INTEL_X86_LDLAT | INTEL_X86_NO_AUTOENCODE, }, }; static const intel_x86_umask_t bdw_mem_uops_retired[]={ { .uname = "STLB_MISS_LOADS", .udesc = "Load uops with true STLB miss retired to architected path", .ucode = 0x1100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "STLB_MISS_STORES", .udesc = "Store uops with true STLB miss retired to architected path", .ucode = 0x1200, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "LOCK_LOADS", .udesc = "Load uops with locked access retired", .ucode = 0x2100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "SPLIT_LOADS", .udesc = "Line-splitted load uops retired", .ucode = 0x4100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "SPLIT_STORES", .udesc = "Line-splitted store uops retired", .ucode = 0x4200, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "ALL_LOADS", .udesc = "All load uops retired", .ucode = 0x8100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "ALL_STORES", .udesc = "All store uops retired", .ucode = 0x8200, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, }; static const intel_x86_umask_t bdw_misalign_mem_ref[]={ { .uname = "LOADS", .udesc = "Speculative cache-line split load uops dispatched to the L1D", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "STORES", .udesc = "Speculative cache-line split store-address uops dispatched to L1D", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t bdw_move_elimination[]={ { .uname = "INT_ELIMINATED", .udesc = "Number of integer Move Elimination candidate uops that were eliminated", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "SIMD_ELIMINATED", .udesc = "Number of SIMD Move Elimination candidate uops that were eliminated", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "INT_NOT_ELIMINATED", .udesc = "Number of integer Move Elimination candidate uops that were not eliminated", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "SIMD_NOT_ELIMINATED", .udesc = "Number of SIMD Move Elimination candidate uops that were not eliminated", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t bdw_offcore_requests[]={ { .uname = "DEMAND_DATA_RD", .udesc = "Demand data read requests sent to uncore (use with HT off only)", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DEMAND_CODE_RD", .udesc = "Demand code read requests sent to uncore (use with HT off only)", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "DEMAND_RFO", .udesc = "Demand RFOs requests sent to uncore (use with HT off only)", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ALL_DATA_RD", .udesc = "Data read requests sent to uncore (use with HT off only)", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t bdw_other_assists[]={ { .uname = "AVX_TO_SSE", .udesc = "Number of transitions from AVX-256 to legacy SSE when penalty applicable", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "SSE_TO_AVX", .udesc = "Number of transitions from legacy SSE to AVX-256 when penalty applicable", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ANY_WB_ASSIST", .udesc = "Number of times any microcode assist is invoked by HW upon uop writeback", .ucode = 0x4000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t bdw_resource_stalls[]={ { .uname = "ANY", .udesc = "Cycles Allocation is stalled due to Resource Related reason", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "ALL", .udesc = "Cycles Allocation is stalled due to Resource Related reason", .ucode = 0x100, .uequiv = "ANY", .uflags = INTEL_X86_NCOMBO, }, { .uname = "RS", .udesc = "Stall cycles caused by absence of eligible entries in Reservation Station (RS)", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "SB", .udesc = "Cycles Allocator is stalled due to Store Buffer full (not including draining from synch)", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ROB", .udesc = "ROB full stall cycles", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t bdw_rob_misc_events[]={ { .uname = "LBR_INSERTS", .udesc = "Count each time an new Last Branch Record (LBR) is inserted", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t bdw_rs_events[]={ { .uname = "EMPTY_CYCLES", .udesc = "Cycles the Reservation Station (RS) is empty for this thread", .ucode = 0x100, .uflags = INTEL_X86_DFL, }, { .uname = "EMPTY_END", .udesc = "Number of times the reservation station (RS) was empty", .ucode = 0x100 | INTEL_X86_MOD_INV | (1 << INTEL_X86_CMASK_BIT) | INTEL_X86_MOD_EDGE, /* inv=1, cmask=1,edge=1 */ .modhw = _INTEL_X86_ATTR_I | _INTEL_X86_ATTR_C | _INTEL_X86_ATTR_E, }, }; static const intel_x86_umask_t bdw_tlb_flush[]={ { .uname = "DTLB_THREAD", .udesc = "Count number of DTLB flushes of thread-specific entries", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "STLB_ANY", .udesc = "Count number of any STLB flushes", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t bdw_uops_executed[]={ { .uname = "CORE", .udesc = "Number of uops executed from any thread", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "THREAD", .udesc = "Number of uops executed per thread each cycle", .ucode = 0x100, .uflags = INTEL_X86_DFL | INTEL_X86_NCOMBO, }, { .uname = "STALL_CYCLES", .udesc = "Number of cycles with no uops executed", .ucode = 0x100 | INTEL_X86_MOD_INV | (1 << INTEL_X86_CMASK_BIT), /* inv=1 cnt=1 */ .uequiv = "THREAD:c=1:i", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_I | _INTEL_X86_ATTR_C, }, { .uname = "CYCLES_GE_1_UOP_EXEC", .udesc = "Cycles where at least 1 uop was executed per thread", .ucode = 0x100 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */ .uequiv = "THREAD:c=1", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "CYCLES_GE_2_UOPS_EXEC", .udesc = "Cycles where at least 2 uops were executed per thread", .ucode = 0x100 | (2 << INTEL_X86_CMASK_BIT), /* cnt=2 */ .uequiv = "THREAD:c=2", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "CYCLES_GE_3_UOPS_EXEC", .udesc = "Cycles where at least 3 uops were executed per thread", .ucode = 0x100 | (3 << INTEL_X86_CMASK_BIT), /* cnt=3 */ .uequiv = "THREAD:c=3", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "CYCLES_GE_4_UOPS_EXEC", .udesc = "Cycles where at least 4 uops were executed per thread", .ucode = 0x100 | (4 << INTEL_X86_CMASK_BIT), /* cnt=4 */ .uequiv = "THREAD:c=4", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "CORE_CYCLES_GE_1", .udesc = "Cycles where at least 1 uop was executed from any thread", .ucode = 0x200 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */ .uequiv = "CORE:c=1", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "CORE_CYCLES_GE_2", .udesc = "Cycles where at least 2 uops were executed from any thread", .ucode = 0x200 | (2 << INTEL_X86_CMASK_BIT), /* cnt=2 */ .uequiv = "CORE:c=2", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "CORE_CYCLES_GE_3", .udesc = "Cycles where at least 3 uops were executed from any thread", .ucode = 0x200 | (3 << INTEL_X86_CMASK_BIT), /* cnt=3 */ .uequiv = "CORE:c=3", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "CORE_CYCLES_GE_4", .udesc = "Cycles where at least 4 uops were executed from any thread", .ucode = 0x200 | (4 << INTEL_X86_CMASK_BIT), /* cnt=4 */ .uequiv = "CORE:c=4", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "CORE_CYCLES_NONE", .udesc = "Cycles where no uop is executed on any thread", .ucode = 0x200 | INTEL_X86_MOD_INV, /* inv=1 */ .uequiv = "CORE:i", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_I, }, }; static const intel_x86_umask_t bdw_uops_executed_port[]={ { .uname = "PORT_0", .udesc = "Cycles which a Uop is executed on port 0", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "PORT_1", .udesc = "Cycles which a Uop is executed on port 1", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "PORT_2", .udesc = "Cycles which a Uop is executed on port 2", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "PORT_3", .udesc = "Cycles which a Uop is executed on port 3", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "PORT_4", .udesc = "Cycles which a Uop is executed on port 4", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "PORT_5", .udesc = "Cycles which a Uop is executed on port 5", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "PORT_6", .udesc = "Cycles which a Uop is executed on port 6", .ucode = 0x4000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "PORT_7", .udesc = "Cycles which a Uop is executed on port 7", .ucode = 0x8000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "PORT_0_CORE", .udesc = "tbd", .ucode = 0x100 | INTEL_X86_MOD_ANY, /* any=1 */ .uequiv = "PORT_0:t=1", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_T, }, { .uname = "PORT_1_CORE", .udesc = "tbd", .ucode = 0x200 | INTEL_X86_MOD_ANY, /* any=1 */ .uequiv = "PORT_1:t=1", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_T, }, { .uname = "PORT_2_CORE", .udesc = "tbd", .ucode = 0x400 | INTEL_X86_MOD_ANY, /* any=1 */ .uequiv = "PORT_2:t=1", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_T, }, { .uname = "PORT_3_CORE", .udesc = "tbd", .ucode = 0x800 | INTEL_X86_MOD_ANY, /* any=1 */ .uequiv = "PORT_3:t=1", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_T, }, { .uname = "PORT_4_CORE", .udesc = "tbd", .ucode = 0x1000 | INTEL_X86_MOD_ANY, /* any=1 */ .uequiv = "PORT_4:t=1", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_T, }, { .uname = "PORT_5_CORE", .udesc = "tbd", .ucode = 0x2000 | INTEL_X86_MOD_ANY, /* any=1 */ .uequiv = "PORT_5:t=1", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_T, }, { .uname = "PORT_6_CORE", .udesc = "tbd", .ucode = 0x4000 | INTEL_X86_MOD_ANY, /* any=1 */ .uequiv = "PORT_6:t=1", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_T, }, { .uname = "PORT_7_CORE", .udesc = "tbd", .ucode = 0x8000 | INTEL_X86_MOD_ANY, /* any=1 */ .uequiv = "PORT_7:t=1", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_T, }, }; static const intel_x86_umask_t bdw_uops_issued[]={ { .uname = "ANY", .udesc = "Number of Uops issued by the Resource Allocation Table (RAT) to the Reservation Station (RS)", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "ALL", .udesc = "Number of Uops issued by the Resource Allocation Table (RAT) to the Reservation Station (RS)", .ucode = 0x100, .uequiv = "ANY", .uflags = INTEL_X86_NCOMBO, }, { .uname = "FLAGS_MERGE", .udesc = "Number of flags-merge uops being allocated. Such uops adds delay", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "SLOW_LEA", .udesc = "Number of slow LEA or similar uops allocated. Such uop has 3 sources regardless if result of LEA instruction or not", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "SINGLE_MUL", .udesc = "Number of Multiply packed/scalar single precision uops allocated", .ucode = 0x4000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "STALL_CYCLES", .udesc = "Counts the number of cycles no uops issued by this thread", .ucode = 0x100 | INTEL_X86_MOD_INV | (1 << INTEL_X86_CMASK_BIT), /* inv=1 cnt=1 */ .uequiv = "ANY:c=1:i=1", .uflags = INTEL_X86_NCOMBO, .ucntmsk = 0xf, .modhw = _INTEL_X86_ATTR_I | _INTEL_X86_ATTR_C, }, { .uname = "CORE_STALL_CYCLES", .udesc = "Counts the number of cycles no uops issued on this core", .ucode = 0x100 | INTEL_X86_MOD_ANY | INTEL_X86_MOD_INV | (1 << INTEL_X86_CMASK_BIT), /* any=1 inv=1 cnt=1 */ .uequiv = "ANY:c=1:i=1:t=1", .ucntmsk = 0xf, .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_T | _INTEL_X86_ATTR_I | _INTEL_X86_ATTR_C, }, }; static const intel_x86_umask_t bdw_uops_retired[]={ { .uname = "ALL", .udesc = "All uops that actually retired", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS | INTEL_X86_DFL, }, { .uname = "ANY", .udesc = "All uops that actually retired", .ucode = 0x100, .uequiv = "ALL", .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "RETIRE_SLOTS", .udesc = "number of retirement slots used non PEBS", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "STALL_CYCLES", .udesc = "Cycles no executable uops retired (Precise Event)", .ucode = 0x100 | INTEL_X86_MOD_INV | (1 << INTEL_X86_CMASK_BIT), /* inv=1 cnt=1 */ .uequiv = "ALL:i=1:c=1", .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, .modhw = _INTEL_X86_ATTR_I | _INTEL_X86_ATTR_C, }, { .uname = "TOTAL_CYCLES", .udesc = "Number of cycles using always true condition applied to PEBS uops retired event", .ucode = 0x100 | INTEL_X86_MOD_INV | (10 << INTEL_X86_CMASK_BIT), /* inv=1 cnt=10 */ .uequiv = "ALL:i=1:c=10", .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, .modhw = _INTEL_X86_ATTR_I | _INTEL_X86_ATTR_C, }, { .uname = "CORE_STALL_CYCLES", .udesc = "Cycles no executable uops retired on core (Precise Event)", .ucode = 0x100 | INTEL_X86_MOD_INV | (1 << INTEL_X86_CMASK_BIT), /* inv=1 cnt=1 */ .uequiv = "ALL:i=1:c=1:t=1", .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, .modhw = _INTEL_X86_ATTR_I | _INTEL_X86_ATTR_C, }, { .uname = "STALL_OCCURRENCES", .udesc = "Number of transitions from stalled to unstalled execution (Precise Event)", .ucode = 0x100 | INTEL_X86_MOD_INV | INTEL_X86_MOD_EDGE| (1 << INTEL_X86_CMASK_BIT), /* inv=1 edge=1 cnt=1 */ .uequiv = "ALL:c=1:i=1:e=1", .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, .modhw = _INTEL_X86_ATTR_I | _INTEL_X86_ATTR_C | _INTEL_X86_ATTR_E, }, }; static const intel_x86_umask_t bdw_offcore_response[]={ { .uname = "DMND_DATA_RD", .udesc = "Request: number of demand and DCU prefetch data reads of full and partial cachelines as well as demand data page table entry cacheline reads. Does not count L2 data read prefetches or instruction fetches", .ucode = 1ULL << (0 + 8), .grpid = 0, }, { .uname = "DMND_RFO", .udesc = "Request: number of demand and DCU prefetch reads for ownership (RFO) requests generated by a write to data cacheline. Does not count L2 RFO prefetches", .ucode = 1ULL << (1 + 8), .grpid = 0, }, { .uname = "DMND_IFETCH", .udesc = "Request: number of demand and DCU prefetch instruction cacheline reads. Does not count L2 code read prefetches", .ucode = 1ULL << (2 + 8), .grpid = 0, }, { .uname = "WB", .udesc = "Request: number of writebacks (modified to exclusive) transactions", .ucode = 1ULL << (3 + 8), .grpid = 0, }, { .uname = "PF_DATA_RD", .udesc = "Request: number of data cacheline reads generated by L2 prefetchers", .ucode = 1ULL << (4 + 8), .grpid = 0, }, { .uname = "PF_RFO", .udesc = "Request: number of RFO requests generated by L2 prefetchers", .ucode = 1ULL << (5 + 8), .grpid = 0, }, { .uname = "PF_IFETCH", .udesc = "Request: number of code reads generated by L2 prefetchers", .ucode = 1ULL << (6 + 8), .grpid = 0, }, { .uname = "PF_LLC_DATA_RD", .udesc = "Request: number of L3 prefetcher requests to L2 for loads", .ucode = 1ULL << (7 + 8), .grpid = 0, }, { .uname = "PF_LLC_RFO", .udesc = "Request: number of RFO requests generated by L2 prefetcher", .ucode = 1ULL << (8 + 8), .grpid = 0, }, { .uname = "PF_LLC_IFETCH", .udesc = "Request: number of L2 prefetcher requests to L3 for instruction fetches", .ucode = 1ULL << (9 + 8), .grpid = 0, }, { .uname = "BUS_LOCKS", .udesc = "Request: number bus lock and split lock requests", .ucode = 1ULL << (10 + 8), .grpid = 0, }, { .uname = "STRM_ST", .udesc = "Request: number of streaming store requests", .ucode = 1ULL << (11 + 8), .grpid = 0, }, { .uname = "OTHER", .udesc = "Request: counts one of the following transaction types, including L3 invalidate, I/O, full or partial writes, WC or non-temporal stores, CLFLUSH, Fences, lock, unlock, split lock", .ucode = 1ULL << (15+8), .grpid = 0, }, { .uname = "ANY_IFETCH", .udesc = "Request: combination of PF_IFETCH | DMND_IFETCH | PF_LLC_IFETCH", .uequiv = "PF_IFETCH:DMND_IFETCH:PF_LLC_IFETCH", .ucode = 0x24100, .grpid = 0, }, { .uname = "ANY_REQUEST", .udesc = "Request: combination of all request umasks", .uequiv = "DMND_DATA_RD:DMND_RFO:DMND_IFETCH:WB:PF_DATA_RD:PF_RFO:PF_IFETCH:PF_LLC_DATA_RD:PF_LLC_RFO:PF_LLC_IFETCH:BUS_LOCKS:STRM_ST:OTHER", .ucode = 0x8fff00, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, .grpid = 0, }, { .uname = "ANY_DATA", .udesc = "Request: combination of DMND_DATA | PF_DATA_RD | PF_LLC_DATA_RD", .uequiv = "DMND_DATA_RD:PF_DATA_RD:PF_LLC_DATA_RD", .ucode = 0x9100, .grpid = 0, }, { .uname = "ANY_RFO", .udesc = "Request: combination of DMND_RFO | PF_RFO | PF_LLC_RFO", .uequiv = "DMND_RFO:PF_RFO:PF_LLC_RFO", .ucode = 0x10300, .grpid = 0, }, { .uname = "ANY_RESPONSE", .udesc = "Response: count any response type", .ucode = 1ULL << (16+8), .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL | INTEL_X86_EXCL_GRP_GT, .grpid = 1, }, { .uname = "NO_SUPP", .udesc = "Supplier: counts number of times supplier information is not available", .ucode = 1ULL << (17+8), .grpid = 1, }, { .uname = "L3_HITM", .udesc = "Supplier: counts L3 hits in M-state (initial lookup)", .ucode = 1ULL << (18+8), .grpid = 1, }, { .uname = "LLC_HITM", .udesc = "Supplier: counts L3 hits in M-state (initial lookup)", .ucode = 1ULL << (18+8), .uequiv = "L3_HITM", .grpid = 1, }, { .uname = "L3_HITE", .udesc = "Supplier: counts L3 hits in E-state", .ucode = 1ULL << (19+8), .grpid = 1, }, { .uname = "LLC_HITE", .udesc = "Supplier: counts L3 hits in E-state", .ucode = 1ULL << (19+8), .uequiv = "L3_HITE", .grpid = 1, }, { .uname = "L3_HITS", .udesc = "Supplier: counts L3 hits in S-state", .ucode = 1ULL << (20+8), .grpid = 1, }, { .uname = "LLC_HITS", .udesc = "Supplier: counts L3 hits in S-state", .ucode = 1ULL << (20+8), .uequiv = "L3_HITS", .grpid = 1, }, { .uname = "L3_HITF", .udesc = "Supplier: counts L3 hits in F-state", .ucode = 1ULL << (21+8), .grpid = 1, }, { .uname = "LLC_HITF", .udesc = "Supplier: counts L3 hits in F-state", .ucode = 1ULL << (20+8), .uequiv = "L3_HITF", .grpid = 1, }, { .uname = "L3_HITMESF", .udesc = "Supplier: counts L3 hits in any state (M, E, S, F)", .ucode = 0xfULL << (18+8), .uequiv = "L3_HITM:L3_HITE:L3_HITS:L3_HITF", .grpid = 1, }, { .uname = "LLC_HITMESF", .udesc = "Supplier: counts L3 hits in any state (M, E, S, F)", .ucode = 0xfULL << (18+8), .uequiv = "L3_HITMESF", .grpid = 1, }, { .uname = "L3_HIT", .udesc = "Alias for L3_HITMESF", .ucode = 0xfULL << (18+8), .uequiv = "L3_HITM:L3_HITE:L3_HITS:L3_HITF", .grpid = 1, }, { .uname = "LLC_HIT", .udesc = "Alias for LLC_HITMESF", .ucode = 0xfULL << (18+8), .uequiv = "L3_HITM:L3_HITE:L3_HITS:L3_HITF", .grpid = 1, }, { .uname = "L3_MISS_LOCAL", .udesc = "Supplier: counts L3 misses to local DRAM", .ucode = 1ULL << (26+8), .grpid = 1, }, { .uname = "LLC_MISS_LOCAL", .udesc = "Supplier: counts L3 misses to local DRAM", .ucode = 1ULL << (26+8), .uequiv = "L3_MISS_LOCAL", .grpid = 1, }, { .uname = "LLC_MISS_LOCAL_DRAM", .udesc = "Supplier: counts L3 misses to local DRAM", .ucode = 1ULL << (26+8), .uequiv = "L3_MISS_LOCAL", .grpid = 1, }, { .uname = "L3_MISS", .udesc = "Supplier: counts L3 misses to local DRAM", .ucode = 1ULL << (26+8), .uequiv = "L3_MISS_LOCAL", .grpid = 1, .umodel = PFM_PMU_INTEL_BDW, }, { .uname = "L3_MISS", .udesc = "Supplier: counts L3 misses to local or remote DRAM", .ucode = 0xfULL << (26+8), .uequiv = "L3_MISS_LOCAL:L3_MISS_REMOTE_HOP0:L3_MISS_REMOTE_HOP1:L3_MISS_REMOTE_HOP2P", .umodel = PFM_PMU_INTEL_BDW_EP, .grpid = 1, }, { .uname = "L3_MISS_REMOTE_HOP0", .udesc = "Supplier: counts L3 misses to remote DRAM with 0 hop", .ucode = 0x1ULL << (27+8), .umodel = PFM_PMU_INTEL_BDW_EP, .grpid = 1, }, { .uname = "L3_MISS_REMOTE_HOP0_DRAM", .udesc = "Supplier: counts L3 misses to remote DRAM with 0 hop", .ucode = 0x1ULL << (27+8), .uequiv = "L3_MISS_REMOTE_HOP0", .umodel = PFM_PMU_INTEL_BDW_EP, .grpid = 1, }, { .uname = "L3_MISS_REMOTE_HOP1", .udesc = "Supplier: counts L3 misses to remote DRAM with 1 hop", .ucode = 0x1ULL << (28+8), .umodel = PFM_PMU_INTEL_BDW_EP, .grpid = 1, }, { .uname = "L3_MISS_REMOTE_HOP1_DRAM", .udesc = "Supplier: counts L3 misses to remote DRAM with 1 hop", .ucode = 0x1ULL << (28+8), .uequiv = "L3_MISS_REMOTE_HOP1", .umodel = PFM_PMU_INTEL_BDW_EP, .grpid = 1, }, { .uname = "L3_MISS_REMOTE_HOP2P", .udesc = "Supplier: counts L3 misses to remote DRAM with 2P hops", .ucode = 0x1ULL << (29+8), .umodel = PFM_PMU_INTEL_BDW_EP, .grpid = 1, }, { .uname = "L3_MISS_REMOTE_HOP2P_DRAM", .udesc = "Supplier: counts L3 misses to remote DRAM with 2P hops", .ucode = 0x1ULL << (29+8), .uequiv = "L3_MISS_REMOTE_HOP2P", .umodel = PFM_PMU_INTEL_BDW_EP, .grpid = 1, }, { .uname = "L3_MISS_REMOTE", .udesc = "Supplier: counts L3 misses to remote node", .uequiv = "L3_MISS_REMOTE_HOP0:L3_MISS_REMOTE_HOP1:L3_MISS_REMOTE_HOP2P", .ucode = 0x7ULL << (27+8), .umodel = PFM_PMU_INTEL_BDW_EP, .grpid = 1, }, { .uname = "L3_MISS_REMOTE_DRAM", .udesc = "Supplier: counts L3 misses to remote node", .ucode = 0x7ULL << (27+8), .uequiv = "L3_MISS_REMOTE", .umodel = PFM_PMU_INTEL_BDW_EP, .grpid = 1, }, { .uname = "SPL_HIT", .udesc = "Supplier: counts L3 supplier hit", .ucode = 0x1ULL << (30+8), .grpid = 1, }, { .uname = "SNP_NONE", .udesc = "Snoop: counts number of times no snoop-related information is available", .ucode = 1ULL << (31+8), .grpid = 2, }, { .uname = "SNP_NOT_NEEDED", .udesc = "Snoop: counts the number of times no snoop was needed to satisfy the request", .ucode = 1ULL << (32+8), .grpid = 2, }, { .uname = "SNP_MISS", .udesc = "Snoop: counts number of times a snoop was needed and it missed all snooped caches", .ucode = 1ULL << (33+8), .grpid = 2, }, { .uname = "SNP_NO_FWD", .udesc = "Snoop: counts number of times a snoop was needed and it hit in at leas one snooped cache", .ucode = 1ULL << (34+8), .grpid = 2, }, { .uname = "SNP_FWD", .udesc = "Snoop: counts number of times a snoop was needed and data was forwarded from a remote socket", .ucode = 1ULL << (35+8), .grpid = 2, }, { .uname = "HITM", .udesc = "Snoop: counts number of times a snoop was needed and it hitM-ed in local or remote cache", .ucode = 1ULL << (36+8), .uequiv = "SNP_HITM", .grpid = 2, }, { .uname = "SNP_HITM", .udesc = "Snoop: counts number of times a snoop was needed and it hitM-ed in local or remote cache", .ucode = 1ULL << (36+8), .grpid = 2, }, { .uname = "NON_DRAM", .udesc = "Snoop: counts number of times target was a non-DRAM system address. This includes MMIO transactions", .ucode = 1ULL << (37+8), .grpid = 2, }, { .uname = "SNP_ANY", .udesc = "Snoop: any snoop reason", .ucode = 0x7fULL << (31+8), .uequiv = "SNP_NONE:SNP_NOT_NEEDED:SNP_MISS:SNP_NO_FWD:SNP_FWD:HITM:NON_DRAM", .uflags = INTEL_X86_DFL, .grpid = 2, }, }; static const intel_x86_umask_t bdw_hle_retired[]={ { .uname = "START", .udesc = "Number of times an HLE execution started", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "COMMIT", .udesc = "Number of times an HLE execution successfully committed", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ABORTED", .udesc = "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one) (Precise Event)", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "ABORTED_MISC1", .udesc = "Number of times an HLE execution aborted due to various memory events", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ABORTED_MISC2", .udesc = "Number of times an HLE execution aborted due to uncommon conditions", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ABORTED_MISC3", .udesc = "Number of times an HLE execution aborted due to HLE-unfriendly instructions", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ABORTED_MISC4", .udesc = "Number of times an HLE execution aborted due to incompatible memory type", .ucode = 0x4000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ABORTED_MISC5", .udesc = "Number of times an HLE execution aborted due to none of the other 4 reasons (e.g., interrupt)", .ucode = 0x8000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t bdw_rtm_retired[]={ { .uname = "START", .udesc = "Number of times an RTM execution started", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "COMMIT", .udesc = "Number of times an RTM execution successfully committed", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ABORTED", .udesc = "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one) (Precise Event)", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "ABORTED_MISC1", .udesc = "Number of times an RTM execution aborted due to various memory events", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ABORTED_MISC2", .udesc = "Number of times an RTM execution aborted due to uncommon conditions", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ABORTED_MISC3", .udesc = "Number of times an RTM execution aborted due to RTM-unfriendly instructions", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ABORTED_MISC4", .udesc = "Number of times an RTM execution aborted due to incompatible memory type", .ucode = 0x4000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ABORTED_MISC5", .udesc = "Number of times an RTM execution aborted due to none of the other 4 reasons (e.g., interrupt)", .ucode = 0x8000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t bdw_tx_mem[]={ { .uname = "ABORT_CONFLICT", .udesc = "Number of times a transactional abort was signaled due to data conflict on a transactionally accessed address", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ABORT_CAPACITY", .udesc = "Number of times a transactional abort was signaled due to data capacity limitation", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ABORT_HLE_STORE_TO_ELIDED_LOCK", .udesc = "Number of times a HLE transactional execution aborted due to a non xrelease prefixed instruction writing to an elided lock in the elision buffer", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", .udesc = "Number of times a HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ABORT_HLE_ELISION_BUFFER_MISMATCH", .udesc = "Number of times a HLE transaction execution aborted due to xrelease lock not satisfying the address and value requirements in the elision buffer", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", .udesc = "Number of times a HLE transaction execution aborted due to an unsupported read alignment from the elision buffer", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ABORT_HLE_ELISION_BUFFER_FULL", .udesc = "Number of times a HLE clock could not be elided due to ElisionBufferAvailable being zero", .ucode = 0x4000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t bdw_tx_exec[]={ { .uname = "MISC1", .udesc = "Number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "MISC2", .udesc = "Number of times a class of instructions that may cause a transactional abort was executed inside a transactional region", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "MISC3", .udesc = "Number of times an instruction execution caused the supported nest count to be exceeded", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "MISC4", .udesc = "Number of times an instruction a xbegin instruction was executed inside HLE transactional region", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "MISC5", .udesc = "Number of times an instruction with HLE xacquire prefix was executed inside a RTM transactional region", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t bdw_offcore_requests_outstanding[]={ { .uname = "ALL_DATA_RD_CYCLES", .udesc = "Cycles with cacheable data read transactions in the superQ (use with HT off only)", .uequiv = "ALL_DATA_RD:c=1", .ucode = 0x800 | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, }, { .uname = "DEMAND_CODE_RD_CYCLES", .udesc = "Cycles with demand code reads transactions in the superQ (use with HT off only)", .uequiv = "DEMAND_CODE_RD:c=1", .ucode = 0x200 | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, }, { .uname = "DEMAND_DATA_RD_CYCLES", .udesc = "Cycles with demand data read transactions in the superQ (use with HT off only)", .uequiv = "DEMAND_DATA_RD:c=1", .ucode = 0x100 | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, }, { .uname = "ALL_DATA_RD", .udesc = "Cacheable data read transactions in the superQ every cycle (use with HT off only)", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DEMAND_CODE_RD", .udesc = "Code read transactions in the superQ every cycle (use with HT off only)", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DEMAND_DATA_RD", .udesc = "Demand data read transactions in the superQ every cycle (use with HT off only)", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DEMAND_DATA_RD_GE_6", .udesc = "Cycles with at lesat 6 offcore outstanding demand data read requests in the uncore queue", .uequiv = "DEMAND_DATA_RD:c=6", .ucode = 0x100 | (6 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "DEMAND_RFO", .udesc = "Outstanding RFO (store) transactions in the superQ every cycle (use with HT off only)", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DEMAND_RFO_CYCLES", .udesc = "Cycles with outstanding RFO (store) transactions in the superQ (use with HT off only)", .uequiv = "DEMAND_RFO:c=1", .ucode = 0x400 | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t bdw_ild_stall[]={ { .uname = "LCP", .udesc = "Stall caused by changing prefix length of the instruction", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t bdw_page_walker_loads[]={ { .uname = "DTLB_L1", .udesc = "Number of DTLB page walker loads that hit in the L1D and line fill buffer", .ucode = 0x1100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ITLB_L1", .udesc = "Number of ITLB page walker loads that hit in the L1I and line fill buffer", .ucode = 0x2100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DTLB_L2", .udesc = "Number of DTLB page walker loads that hit in the L2", .ucode = 0x1200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ITLB_L2", .udesc = "Number of ITLB page walker loads that hit in the L2", .ucode = 0x2200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DTLB_L3", .udesc = "Number of DTLB page walker loads that hit in the L3", .ucode = 0x1400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ITLB_L3", .udesc = "Number of ITLB page walker loads that hit in the L3", .ucode = 0x2400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DTLB_MEMORY", .udesc = "Number of DTLB page walker loads that hit memory", .ucode = 0x1800, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t bdw_lsd[]={ { .uname = "UOPS", .udesc = "Number of uops delivered by the Loop Stream Detector (LSD)", .ucode = 0x100, .uflags= INTEL_X86_DFL, }, { .uname = "ACTIVE", .udesc = "Cycles with uops delivered by the LSD but which did not come from decoder", .ucode = 0x100 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */ .uequiv = "UOPS:c=1", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "CYCLES_4_UOPS", .udesc = "Cycles with 4 uops delivered by the LSD but which did not come from decoder", .ucode = 0x100 | (4 << INTEL_X86_CMASK_BIT), /* cnt=4 */ .uequiv = "UOPS:c=4", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, }; static const intel_x86_umask_t bdw_dsb2mite_switches[]={ { .uname = "PENALTY_CYCLES", .udesc = "Number of DSB to MITE switch true penalty cycles", .ucode = 0x0200, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t bdw_ept[]={ { .uname = "WALK_CYCLES", .udesc = "Cycles for an extended page table walk", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t bdw_arith[]={ { .uname = "FPU_DIV_ACTIVE", .udesc = "Cycles when divider is busy execuing divide operations", .ucode = 0x0100, .uflags= INTEL_X86_DFL, }, }; static const intel_x86_umask_t bdw_fp_arith[]={ { .uname = "SCALAR_DOUBLE", .udesc = "Number of scalar double precision floating-point arithmetic instructions (multiply by 1 to get flops)", .ucode = 0x0100, }, { .uname = "SCALAR_SINGLE", .udesc = "Number of scalar single precision floating-point arithmetic instructions (multiply by 1 to get flops)", .ucode = 0x0200, }, { .uname = "SCALAR", .udesc = "Number of SSE/AVX computational scalar floating-point instructions retired. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element", .ucode = 0x0300, .uequiv = "SCALAR_DOUBLE:SCALAR_SINGLE", }, { .uname = "128B_PACKED_DOUBLE", .udesc = "Number of scalar 128-bit packed double precision floating-point arithmetic instructions (multiply by 2 to get flops)", .ucode = 0x0400, }, { .uname = "128B_PACKED_SINGLE", .udesc = "Number of scalar 128-bit packed single precision floating-point arithmetic instructions (multiply by 4 to get flops)", .ucode = 0x0800, }, { .uname = "256B_PACKED_DOUBLE", .udesc = "Number of scalar 256-bit packed double precision floating-point arithmetic instructions (multiply by 4 to get flops)", .ucode = 0x1000, }, { .uname = "256B_PACKED_SINGLE", .udesc = "Number of scalar 256-bit packed single precision floating-point arithmetic instructions (multiply by 8 to get flops)", .ucode = 0x2000, }, { .uname = "PACKED", .udesc = "Number of SSE/AVX computational packed floating-point instructions retired. Applies to SSE* and AVX*, packed, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element", .ucode = 0x3c00, .uequiv = "128B_PACKED_DOUBLE:128B_PACKED_SINGLE:256B_PACKED_SINGLE:256B_PACKED_DOUBLE", }, { .uname = "SINGLE", .udesc = "Number of SSE/AVX computational single precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element", .ucode = 0x2a00, .uequiv = "256B_PACKED_SINGLE:128B_PACKED_SINGLE:SCALAR_SINGLE", }, { .uname = "DOUBLE", .udesc = "Number of SSE/AVX computational double precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element", .ucode = 0x1500, .uequiv = "SCALAR_DOUBLE:128B_PACKED_DOUBLE:256B_PACKED_DOUBLE", }, }; static const intel_x86_umask_t bdw_offcore_requests_buffer[]={ { .uname = "SQ_FULL", .udesc = "Number of cycles the offcore requests buffer is full", .ucode = 0x0100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t bdw_uops_dispatches_cancelled[]={ { .uname = "SIMD_PRF", .udesc = "Number of uops cancelled after they were dispatched from the scheduler to the execution units when the total number of physical register read ports exceeds the read bandwidth of the register file. This umask applies to instructions: DPPS, DPPS, VPCMPESTRI, PCMPESTRI, VPCMPESTRM, PCMPESTRM, VFMADD*, VFMADDSUB*, VFMSUB*, VMSUBADD*, VFNMADD*, VFNMSUB*", .ucode = 0x0300, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_entry_t intel_bdw_pe[]={ { .name = "UNHALTED_CORE_CYCLES", .desc = "Count core clock cycles whenever the clock signal on the specific core is running (not halted)", .modmsk = INTEL_V4_ATTRS, .cntmsk = 0x20000000full, .code = 0x3c, }, { .name = "UNHALTED_REFERENCE_CYCLES", .desc = "Unhalted reference cycles", .modmsk = INTEL_FIXED3_ATTRS, .cntmsk = 0x400000000ull, .code = 0x0300, /* pseudo encoding */ .flags = INTEL_X86_FIXED, }, { .name = "INSTRUCTION_RETIRED", .desc = "Number of instructions at retirement", .modmsk = INTEL_V4_ATTRS, .cntmsk = 0x10000000full, .code = 0xc0, }, { .name = "INSTRUCTIONS_RETIRED", .desc = "This is an alias for INSTRUCTION_RETIRED", .modmsk = INTEL_V4_ATTRS, .equiv = "INSTRUCTION_RETIRED", .cntmsk = 0x10000000full, .code = 0xc0, }, { .name = "BRANCH_INSTRUCTIONS_RETIRED", .desc = "Count branch instructions at retirement. Specifically, this event counts the retirement of the last micro-op of a branch instruction", .modmsk = INTEL_V4_ATTRS, .equiv = "BR_INST_RETIRED:ALL_BRANCHES", .cntmsk = 0xff, .code = 0xc4, }, { .name = "MISPREDICTED_BRANCH_RETIRED", .desc = "Count mispredicted branch instructions at retirement. Specifically, this event counts at retirement of the last micro-op of a branch instruction in the architectural path of the execution and experienced misprediction in the branch prediction hardware", .modmsk = INTEL_V4_ATTRS, .equiv = "BR_MISP_RETIRED:ALL_BRANCHES", .cntmsk = 0xff, .code = 0xc5, }, { .name = "BACLEARS", .desc = "Branch re-steered", .code = 0xe6, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(bdw_baclears), .umasks = bdw_baclears }, { .name = "BR_INST_EXEC", .desc = "Branch instructions executed", .code = 0x88, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(bdw_br_inst_exec), .umasks = bdw_br_inst_exec }, { .name = "BR_INST_RETIRED", .desc = "Branch instructions retired (Precise Event)", .code = 0xc4, .cntmsk = 0xff, .ngrp = 1, .flags = INTEL_X86_PEBS, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(bdw_br_inst_retired), .umasks = bdw_br_inst_retired }, { .name = "BR_MISP_EXEC", .desc = "Mispredicted branches executed", .code = 0x89, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(bdw_br_misp_exec), .umasks = bdw_br_misp_exec }, { .name = "BR_MISP_RETIRED", .desc = "Mispredicted retired branches (Precise Event)", .code = 0xc5, .cntmsk = 0xff, .ngrp = 1, .flags = INTEL_X86_PEBS, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(bdw_br_misp_retired), .umasks = bdw_br_misp_retired }, { .name = "CPL_CYCLES", .desc = "Unhalted core cycles at a specific ring level", .code = 0x5c, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(bdw_cpl_cycles), .umasks = bdw_cpl_cycles }, { .name = "CPU_CLK_THREAD_UNHALTED", .desc = "Count core clock cycles whenever the clock signal on the specific core is running (not halted)", .code = 0x3c, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(bdw_cpu_clk_thread_unhalted), .umasks = bdw_cpu_clk_thread_unhalted }, { .name = "CPU_CLK_UNHALTED", .desc = "Count core clock cycles whenever the clock signal on the specific core is running (not halted)", .code = 0x3c, .cntmsk = 0xff, .modmsk = INTEL_V4_ATTRS, .equiv = "CPU_CLK_THREAD_UNHALTED", }, { .name = "CYCLE_ACTIVITY", .desc = "Stalled cycles", .code = 0xa3, .cntmsk = 0xf, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(bdw_cycle_activity), .umasks = bdw_cycle_activity }, { .name = "DTLB_LOAD_MISSES", .desc = "Data TLB load misses", .code = 0x8, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(bdw_dtlb_load_misses), .umasks = bdw_dtlb_load_misses }, { .name = "DTLB_STORE_MISSES", .desc = "Data TLB store misses", .code = 0x49, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(bdw_dtlb_load_misses), .umasks = bdw_dtlb_load_misses /* shared */ }, { .name = "FP_ASSIST", .desc = "X87 floating-point assists", .code = 0xca, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(bdw_fp_assist), .umasks = bdw_fp_assist }, { .name = "HLE_RETIRED", .desc = "HLE execution (Precise Event)", .code = 0xc8, .cntmsk = 0xff, .ngrp = 1, .flags = INTEL_X86_PEBS, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(bdw_hle_retired), .umasks = bdw_hle_retired }, { .name = "ICACHE", .desc = "Instruction Cache", .code = 0x80, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(bdw_icache), .umasks = bdw_icache }, { .name = "IDQ", .desc = "IDQ operations", .code = 0x79, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(bdw_idq), .umasks = bdw_idq }, { .name = "IDQ_UOPS_NOT_DELIVERED", .desc = "Uops not delivered", .code = 0x9c, .cntmsk = 0xf, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(bdw_idq_uops_not_delivered), .umasks = bdw_idq_uops_not_delivered }, { .name = "INST_RETIRED", .desc = "Number of instructions retired (Precise Event)", .code = 0xc0, .cntmsk = 0xff, .ngrp = 1, .flags = INTEL_X86_PEBS, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(bdw_inst_retired), .umasks = bdw_inst_retired }, { .name = "INT_MISC", .desc = "Miscellaneous interruptions", .code = 0xd, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(bdw_int_misc), .umasks = bdw_int_misc }, { .name = "ITLB", .desc = "Instruction TLB", .code = 0xae, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(bdw_itlb), .umasks = bdw_itlb }, { .name = "ITLB_MISSES", .desc = "Instruction TLB misses", .code = 0x85, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(bdw_itlb_misses), .umasks = bdw_itlb_misses }, { .name = "L1D", .desc = "L1D cache", .code = 0x51, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(bdw_l1d), .umasks = bdw_l1d }, { .name = "L1D_PEND_MISS", .desc = "L1D pending misses", .code = 0x48, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(bdw_l1d_pend_miss), .umasks = bdw_l1d_pend_miss }, { .name = "L2_DEMAND_RQSTS", .desc = "Demand Data Read requests to L2", .code = 0x27, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(bdw_l2_demand_rqsts), .umasks = bdw_l2_demand_rqsts }, { .name = "L2_LINES_IN", .desc = "L2 lines allocated", .code = 0xf1, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(bdw_l2_lines_in), .umasks = bdw_l2_lines_in }, { .name = "L2_LINES_OUT", .desc = "L2 lines evicted", .code = 0xf2, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(bdw_l2_lines_out), .umasks = bdw_l2_lines_out }, { .name = "L2_RQSTS", .desc = "L2 requests", .code = 0x24, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(bdw_l2_rqsts), .umasks = bdw_l2_rqsts }, { .name = "L2_TRANS", .desc = "L2 transactions", .code = 0xf0, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(bdw_l2_trans), .umasks = bdw_l2_trans }, { .name = "LD_BLOCKS", .desc = "Blocking loads", .code = 0x3, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(bdw_ld_blocks), .umasks = bdw_ld_blocks }, { .name = "LD_BLOCKS_PARTIAL", .desc = "Partial load blocks", .code = 0x7, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(bdw_ld_blocks_partial), .umasks = bdw_ld_blocks_partial }, { .name = "LOAD_HIT_PRE", .desc = "Load dispatches", .code = 0x4c, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(bdw_load_hit_pre), .umasks = bdw_load_hit_pre }, { .name = "LOCK_CYCLES", .desc = "Locked cycles in L1D and L2", .code = 0x63, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(bdw_lock_cycles), .umasks = bdw_lock_cycles }, { .name = "LONGEST_LAT_CACHE", .desc = "L3 cache", .code = 0x2e, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(bdw_longest_lat_cache), .umasks = bdw_longest_lat_cache }, { .name = "MACHINE_CLEARS", .desc = "Machine clear asserted", .code = 0xc3, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(bdw_machine_clears), .umasks = bdw_machine_clears }, { .name = "MEM_LOAD_UOPS_L3_HIT_RETIRED", .desc = "L3 hit load uops retired (Precise Event)", .code = 0xd2, .cntmsk = 0xf, .ngrp = 1, .flags = INTEL_X86_PEBS, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(bdw_mem_load_uops_l3_hit_retired), .umasks = bdw_mem_load_uops_l3_hit_retired }, { .name = "MEM_LOAD_UOPS_LLC_HIT_RETIRED", .desc = "L3 hit load uops retired (Precise Event)", .equiv = "MEM_LOAD_UOPS_L3_HIT_RETIRED", .code = 0xd2, .cntmsk = 0xf, .ngrp = 1, .flags = INTEL_X86_PEBS, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(bdw_mem_load_uops_l3_hit_retired), .umasks = bdw_mem_load_uops_l3_hit_retired }, { .name = "MEM_LOAD_UOPS_L3_MISS_RETIRED", .desc = "Load uops retired that missed the L3 (Precise Event)", .code = 0xd3, .cntmsk = 0xf, .ngrp = 1, .flags = INTEL_X86_PEBS, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(bdw_mem_load_uops_l3_miss_retired), .umasks = bdw_mem_load_uops_l3_miss_retired }, { .name = "MEM_LOAD_UOPS_LLC_MISS_RETIRED", .desc = "Load uops retired that missed the L3 (Precise Event)", .equiv = "MEM_LOAD_UOPS_L3_MISS_RETIRED", .code = 0xd3, .cntmsk = 0xf, .ngrp = 1, .flags = INTEL_X86_PEBS, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(bdw_mem_load_uops_l3_miss_retired), .umasks = bdw_mem_load_uops_l3_miss_retired }, { .name = "MEM_LOAD_UOPS_RETIRED", .desc = "Retired load uops (Precise Event)", .code = 0xd1, .cntmsk = 0xf, .ngrp = 1, .flags = INTEL_X86_PEBS, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(bdw_mem_load_uops_retired), .umasks = bdw_mem_load_uops_retired }, { .name = "MEM_TRANS_RETIRED", .desc = "Memory transactions retired (Precise Event)", .code = 0xcd, .cntmsk = 0x8, .ngrp = 1, .flags = INTEL_X86_PEBS, .modmsk = INTEL_V4_ATTRS | _INTEL_X86_ATTR_LDLAT, .numasks = LIBPFM_ARRAY_SIZE(bdw_mem_trans_retired), .umasks = bdw_mem_trans_retired }, { .name = "MEM_UOPS_RETIRED", .desc = "Memory uops retired (Precise Event)", .code = 0xd0, .cntmsk = 0xf, .ngrp = 1, .flags = INTEL_X86_PEBS, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(bdw_mem_uops_retired), .umasks = bdw_mem_uops_retired }, { .name = "MISALIGN_MEM_REF", .desc = "Misaligned memory references", .code = 0x5, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(bdw_misalign_mem_ref), .umasks = bdw_misalign_mem_ref }, { .name = "MOVE_ELIMINATION", .desc = "Move Elimination", .code = 0x58, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(bdw_move_elimination), .umasks = bdw_move_elimination }, { .name = "OFFCORE_REQUESTS", .desc = "Demand Data Read requests sent to uncore", .code = 0xb0, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(bdw_offcore_requests), .umasks = bdw_offcore_requests }, { .name = "OTHER_ASSISTS", .desc = "Software assist", .code = 0xc1, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(bdw_other_assists), .umasks = bdw_other_assists }, { .name = "RESOURCE_STALLS", .desc = "Cycles Allocation is stalled due to Resource Related reason", .code = 0xa2, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(bdw_resource_stalls), .umasks = bdw_resource_stalls }, { .name = "ROB_MISC_EVENTS", .desc = "ROB miscellaneous events", .code = 0xcc, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(bdw_rob_misc_events), .umasks = bdw_rob_misc_events }, { .name = "RS_EVENTS", .desc = "Reservation Station", .code = 0x5e, .cntmsk = 0xf, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(bdw_rs_events), .umasks = bdw_rs_events }, { .name = "RTM_RETIRED", .desc = "Restricted Transaction Memory execution (Precise Event)", .code = 0xc9, .cntmsk = 0xf, .ngrp = 1, .flags = INTEL_X86_PEBS, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(bdw_rtm_retired), .umasks = bdw_rtm_retired }, { .name = "TLB_FLUSH", .desc = "TLB flushes", .code = 0xbd, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(bdw_tlb_flush), .umasks = bdw_tlb_flush }, { .name = "UOPS_EXECUTED", .desc = "Uops executed", .code = 0xb1, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(bdw_uops_executed), .umasks = bdw_uops_executed }, { .name = "LSD", .desc = "Loop stream detector", .code = 0xa8, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(bdw_lsd), .umasks = bdw_lsd, }, { .name = "UOPS_EXECUTED_PORT", .desc = "Uops dispatch to specific ports", .code = 0xa1, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(bdw_uops_executed_port), .umasks = bdw_uops_executed_port }, { .name = "UOPS_ISSUED", .desc = "Uops issued", .code = 0xe, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(bdw_uops_issued), .umasks = bdw_uops_issued }, { .name = "ARITH", .desc = "Arithmetic uop", .code = 0x14, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(bdw_arith), .umasks = bdw_arith }, { .name = "UOPS_RETIRED", .desc = "Uops retired (Precise Event)", .code = 0xc2, .cntmsk = 0xff, .ngrp = 1, .flags = INTEL_X86_PEBS, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(bdw_uops_retired), .umasks = bdw_uops_retired }, { .name = "TX_MEM", .desc = "Transactional memory aborts", .code = 0x54, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(bdw_tx_mem), .umasks = bdw_tx_mem, }, { .name = "TX_EXEC", .desc = "Transactional execution", .code = 0x5d, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(bdw_tx_exec), .umasks = bdw_tx_exec }, { .name = "OFFCORE_REQUESTS_OUTSTANDING", .desc = "Outstanding offcore requests", .modmsk = INTEL_V4_ATTRS, .cntmsk = 0xff, .code = 0x60, .numasks = LIBPFM_ARRAY_SIZE(bdw_offcore_requests_outstanding), .ngrp = 1, .umasks = bdw_offcore_requests_outstanding, }, { .name = "ILD_STALL", .desc = "Instruction Length Decoder stalls", .modmsk = INTEL_V4_ATTRS, .cntmsk = 0xff, .code = 0x87, .numasks = LIBPFM_ARRAY_SIZE(bdw_ild_stall), .ngrp = 1, .umasks = bdw_ild_stall, }, { .name = "PAGE_WALKER_LOADS", .desc = "Page walker loads", .modmsk = INTEL_V4_ATTRS, .cntmsk = 0xf, .code = 0xbc, .numasks = LIBPFM_ARRAY_SIZE(bdw_page_walker_loads), .ngrp = 1, .umasks = bdw_page_walker_loads, }, { .name = "DSB2MITE_SWITCHES", .desc = "Number of DSB to MITE switches", .modmsk = INTEL_V4_ATTRS, .cntmsk = 0xff, .code = 0xab, .numasks = LIBPFM_ARRAY_SIZE(bdw_dsb2mite_switches), .ngrp = 1, .umasks = bdw_dsb2mite_switches, }, { .name = "EPT", .desc = "Extended page table", .modmsk = INTEL_V4_ATTRS, .cntmsk = 0xff, .code = 0x4f, .numasks = LIBPFM_ARRAY_SIZE(bdw_ept), .ngrp = 1, .umasks = bdw_ept, }, { .name = "FP_ARITH", .desc = "Floating-point", .modmsk = INTEL_V4_ATTRS, .cntmsk = 0xf, .code = 0xc7, .numasks = LIBPFM_ARRAY_SIZE(bdw_fp_arith), .ngrp = 1, .umasks = bdw_fp_arith, }, { .name = "OFFCORE_REQUESTS_BUFFER", .desc = "Offcore reqest buffer", .modmsk = INTEL_V4_ATTRS, .cntmsk = 0xff, .code = 0xb2, .numasks = LIBPFM_ARRAY_SIZE(bdw_offcore_requests_buffer), .ngrp = 1, .umasks = bdw_offcore_requests_buffer, }, { .name = "UOPS_DISPATCHES_CANCELLED", .desc = "Micro-ops cancelled", .modmsk = INTEL_V4_ATTRS, .cntmsk = 0xf, .code = 0xa0, .numasks = LIBPFM_ARRAY_SIZE(bdw_uops_dispatches_cancelled), .ngrp = 1, .umasks = bdw_uops_dispatches_cancelled, }, { .name = "SQ_MISC", .desc = "SuperQueue miscellaneous", .modmsk = INTEL_V4_ATTRS, .cntmsk = 0xf, .code = 0xf4, .numasks = LIBPFM_ARRAY_SIZE(bdw_sq_misc), .ngrp = 1, .umasks = bdw_sq_misc, }, { .name = "OFFCORE_RESPONSE_0", .desc = "Offcore response event (must provide at least one request type and either any_response or any combination of supplier + snoop)", .modmsk = INTEL_V4_ATTRS, .cntmsk = 0xf, .code = 0x1b7, .flags= INTEL_X86_NHM_OFFCORE, .numasks = LIBPFM_ARRAY_SIZE(bdw_offcore_response), .ngrp = 3, .umasks = bdw_offcore_response, }, { .name = "OFFCORE_RESPONSE_1", .desc = "Offcore response event (must provide at least one request type and either any_response or any combination of supplier + snoop)", .modmsk = INTEL_V4_ATTRS, .cntmsk = 0xf, .code = 0x1bb, .flags= INTEL_X86_NHM_OFFCORE, .numasks = LIBPFM_ARRAY_SIZE(bdw_offcore_response), .ngrp = 3, .umasks = bdw_offcore_response, /* identical to actual umasks list for this event */ }, }; libpfm-4.9.0/lib/events/intel_ivbep_unc_ubo_events.h0000664000175000017500000000612113223402656022437 0ustar eranianeranian/* * Copyright (c) 2014 Google Inc. All rights reserved * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * PMU: ivbep_unc_ubo (Intel IvyBridge-EP U-Box uncore PMU) */ static const intel_x86_umask_t ivbep_unc_u_event_msg[]={ { .uname = "DOORBELL_RCVD", .udesc = "TBD", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "INT_PRIO", .udesc = "TBD", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "IPI_RCVD", .udesc = "TBD", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "MSI_RCVD", .udesc = "TBD", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "VLW_RCVD", .udesc = "TBD", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t ivbep_unc_u_phold_cycles[]={ { .uname = "ASSERT_TO_ACK", .udesc = "Number of cycles asserted to ACK", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ACK_TO_DEASSERT", .udesc = "Number of cycles ACK to deassert", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_entry_t intel_ivbep_unc_u_pe[]={ { .name = "UNC_U_EVENT_MSG", .desc = "VLW Received", .code = 0x42, .cntmsk = 0x3, .ngrp = 1, .modmsk = IVBEP_UNC_UBO_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_u_event_msg), .umasks = ivbep_unc_u_event_msg }, { .name = "UNC_U_LOCK_CYCLES", .desc = "IDI Lock/SplitLock Cycles", .code = 0x44, .cntmsk = 0x3, .modmsk = IVBEP_UNC_UBO_ATTRS, }, { .name = "UNC_U_PHOLD_CYCLES", .desc = "Cycles PHOLD asserts to Ack", .code = 0x45, .cntmsk = 0x3, .ngrp = 1, .modmsk = IVBEP_UNC_UBO_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_u_phold_cycles), .umasks = ivbep_unc_u_phold_cycles }, { .name = "UNC_U_RACU_REQUESTS", .desc = "RACU requests", .code = 0x46, .cntmsk = 0x3, .modmsk = IVBEP_UNC_UBO_ATTRS, }, }; libpfm-4.9.0/lib/events/intel_ivbep_unc_r2pcie_events.h0000664000175000017500000001715413223402656023046 0ustar eranianeranian/* * Copyright (c) 2014 Google Inc. All rights reserved * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * This file has been automatically generated. * * PMU: ivbep_unc_r2pcie (Intel IvyBridge-EP R2PCIe uncore) */ static const intel_x86_umask_t ivbep_unc_r2_ring_ad_used[]={ { .uname = "CCW_VR0_EVEN", .udesc = "Counter-clockwise and even ring polarity on virtual ring 0", .ucode = 0x400, }, { .uname = "CCW_VR0_ODD", .udesc = "Counter-clockwise and odd ring polarity on virtual ring 0", .ucode = 0x800, }, { .uname = "CW_VR0_EVEN", .udesc = "Clockwise and even ring polarity on virtual ring 0", .ucode = 0x100, }, { .uname = "CW_VR0_ODD", .udesc = "Clockwise and odd ring polarity on virtual ring 0", .ucode = 0x200, }, { .uname = "CCW_VR1_EVEN", .udesc = "Counter-clockwise and even ring polarity on virtual ring 1", .ucode = 0x400, }, { .uname = "CCW_VR1_ODD", .udesc = "Counter-clockwise and odd ring polarity on virtual ring 1", .ucode = 0x800, }, { .uname = "CW_VR1_EVEN", .udesc = "Clockwise and even ring polarity on virtual ring 1", .ucode = 0x100, }, { .uname = "CW_VR1_ODD", .udesc = "Clockwise and odd ring polarity on virtual ring 1", .ucode = 0x200, }, { .uname = "CW", .udesc = "Clockwise with any polarity on either virtual rings", .ucode = 0x3300, .uflags = INTEL_X86_NCOMBO, }, { .uname = "CCW", .udesc = "Counter-clockwise with any polarity on either virtual rings", .ucode = 0xcc00, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t ivbep_unc_r2_rxr_ak_bounces[]={ { .uname = "CW", .udesc = "Clockwise", .ucode = 0x100, }, { .uname = "CCW", .udesc = "Counter-clockwise", .ucode = 0x200, }, }; static const intel_x86_umask_t ivbep_unc_r2_rxr_occupancy[]={ { .uname = "DRS", .udesc = "DRS Ingress queue", .ucode = 0x800, .uflags = INTEL_X86_DFL, }, }; static const intel_x86_umask_t ivbep_unc_r2_ring_iv_used[]={ { .uname = "CW", .udesc = "Clockwise with any polarity on either virtual rings", .ucode = 0x3300, .uflags = INTEL_X86_NCOMBO, }, { .uname = "CCW", .udesc = "Counter-clockwise with any polarity on either virtual rings", .ucode = 0xcc00, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ANY", .udesc = "any direction and any polarity on any virtual ring", .ucode = 0xff00, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t ivbep_unc_r2_rxr_cycles_ne[]={ { .uname = "NCB", .udesc = "NCB Ingress queue", .ucode = 0x1000, }, { .uname = "NCS", .udesc = "NCS Ingress queue", .ucode = 0x2000, }, }; static const intel_x86_umask_t ivbep_unc_r2_txr_cycles_full[]={ { .uname = "AD", .udesc = "AD Egress queue", .ucode = 0x100, }, { .uname = "AK", .udesc = "AK Egress queue", .ucode = 0x200, }, { .uname = "BL", .udesc = "BL Egress queue", .ucode = 0x400, }, }; static const intel_x86_entry_t intel_ivbep_unc_r2_pe[]={ { .name = "UNC_R2_CLOCKTICKS", .desc = "Number of uclks in domain", .code = 0x1, .cntmsk = 0xf, .modmsk = IVBEP_UNC_R2PCIE_ATTRS, }, { .name = "UNC_R2_RING_AD_USED", .desc = "R2 AD Ring in Use", .code = 0x7, .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_R2PCIE_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r2_ring_ad_used), .umasks = ivbep_unc_r2_ring_ad_used }, { .name = "UNC_R2_RING_AK_USED", .desc = "R2 AK Ring in Use", .code = 0x8, .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_R2PCIE_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r2_ring_ad_used), .umasks = ivbep_unc_r2_ring_ad_used /* shared */ }, { .name = "UNC_R2_RING_BL_USED", .desc = "R2 BL Ring in Use", .code = 0x9, .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_R2PCIE_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r2_ring_ad_used), .umasks = ivbep_unc_r2_ring_ad_used /* shared */ }, { .name = "UNC_R2_RING_IV_USED", .desc = "R2 IV Ring in Use", .code = 0xa, .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_R2PCIE_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r2_ring_iv_used), .umasks = ivbep_unc_r2_ring_iv_used }, { .name = "UNC_R2_RXR_AK_BOUNCES", .desc = "AK Ingress Bounced", .code = 0x12, .cntmsk = 0x1, .modmsk = IVBEP_UNC_R2PCIE_ATTRS, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r2_rxr_ak_bounces), .umasks = ivbep_unc_r2_rxr_ak_bounces }, { .name = "UNC_R2_RXR_OCCUPANCY", .desc = "Ingress occupancy accumulator", .code = 0x13, .cntmsk = 0x1, .modmsk = IVBEP_UNC_R2PCIE_ATTRS, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r2_rxr_occupancy), .umasks = ivbep_unc_r2_rxr_occupancy }, { .name = "UNC_R2_RXR_CYCLES_NE", .desc = "Ingress Cycles Not Empty", .code = 0x10, .cntmsk = 0x3, .ngrp = 1, .modmsk = IVBEP_UNC_R2PCIE_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r2_rxr_cycles_ne), .umasks = ivbep_unc_r2_rxr_cycles_ne }, { .name = "UNC_R2_RXR_INSERTS", .desc = "Ingress inserts", .code = 0x11, .cntmsk = 0x3, .ngrp = 1, .modmsk = IVBEP_UNC_R2PCIE_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r2_rxr_cycles_ne), .umasks = ivbep_unc_r2_rxr_cycles_ne, /* shared */ }, { .name = "UNC_R2_TXR_CYCLES_FULL", .desc = "Egress Cycles Full", .code = 0x25, .cntmsk = 0x1, .ngrp = 1, .modmsk = IVBEP_UNC_R2PCIE_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r2_txr_cycles_full), .umasks = ivbep_unc_r2_txr_cycles_full }, { .name = "UNC_R2_TXR_CYCLES_NE", .desc = "Egress Cycles Not Empty", .code = 0x23, .cntmsk = 0x1, .ngrp = 1, .modmsk = IVBEP_UNC_R2PCIE_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r2_txr_cycles_full), .umasks = ivbep_unc_r2_txr_cycles_full /* shared */ }, { .name = "UNC_R2_TXR_NACK_CCW", .desc = "Egress counter-clockwise BACK", .code = 0x28, .cntmsk = 0x1, .ngrp = 1, .modmsk = IVBEP_UNC_R2PCIE_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r2_txr_cycles_full), .umasks = ivbep_unc_r2_txr_cycles_full /* shared */ }, { .name = "UNC_R2_TXR_NACK_CW", .desc = "Egress clockwise BACK", .code = 0x26, .cntmsk = 0x1, .ngrp = 1, .modmsk = IVBEP_UNC_R2PCIE_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r2_txr_cycles_full), .umasks = ivbep_unc_r2_txr_cycles_full /* shared */ }, }; libpfm-4.9.0/lib/events/intel_ivbep_unc_qpi_events.h0000664000175000017500000005502313223402656022450 0ustar eranianeranian/* * Copyright (c) 2014 Google Inc. All rights reserved * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * This file has been automatically generated. * * PMU: ivbep_unc_qpi (Intel IvyBridge-EP QPI uncore) */ static const intel_x86_umask_t ivbep_unc_q_direct2core[]={ { .uname = "FAILURE_CREDITS", .udesc = "Number of spawn failures due to lack of Egress credits", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "FAILURE_CREDITS_RBT", .udesc = "Number of spawn failures due to lack of Egress credit and route-back table (RBT) bit was not set", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "FAILURE_RBT_HIT", .udesc = "Number of spawn failures because route-back table (RBT) specified that the transaction should not trigger a direct2core transaction", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "SUCCESS_RBT_HIT", .udesc = "Number of spawn successes", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "FAILURE_MISS", .udesc = "Number of spawn failures due to RBT tag not matching although the valid bit was set and there was enough Egress credits", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "FAILURE_CREDITS_MISS", .udesc = "Number of spawn failures due to RBT tag not matching and they were not enough Egress credits. The valid bit was set", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "FAILURE_RBT_MISS", .udesc = "Number of spawn failures due to RBT tag not matching, the valid bit was not set but there were enough Egress credits", .ucode = 0x4000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "FAILURE_CREDITS_RBT_MISS", .udesc = "Number of spawn failures due to RBT tag not matching, the valid bit was not set and there were not enough Egress credits", .ucode = 0x8000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t ivbep_unc_q_rxl_credits_consumed_vn0[]={ { .uname = "DRS", .udesc = "Number of times VN0 consumed for DRS message class", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "HOM", .udesc = "Number of times VN0 consumed for HOM message class", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "NCB", .udesc = "Number of times VN0 consumed for NCB message class", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "NCS", .udesc = "Number of times VN0 consumed for NCS message class", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "NDR", .udesc = "Number of times VN0 consumed for NDR message class", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "SNP", .udesc = "Number of times VN0 consumed for SNP message class", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t ivbep_unc_q_rxl_credits_consumed_vn1[]={ { .uname = "DRS", .udesc = "Number of times VN1 consumed for DRS message class", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "HOM", .udesc = "Number of times VN1 consumed for HOM message class", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "NCB", .udesc = "Number of times VN1 consumed for NCB message class", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "NCS", .udesc = "Number of times VN1 consumed for NCS message class", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "NDR", .udesc = "Number of times VN1 consumed for NDR message class", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "SNP", .udesc = "Number of times VN1 consumed for SNP message class", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t ivbep_unc_q_rxl_flits_g0[]={ { .uname = "DATA", .udesc = "Number of data flits over QPI", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "IDLE", .udesc = "Number of flits over QPI that do not hold protocol payload", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "NON_DATA", .udesc = "Number of non-NULL non-data flits over QPI", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t ivbep_unc_q_txl_flits_g0[]={ { .uname = "DATA", .udesc = "Number of data flits over QPI", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "NON_DATA", .udesc = "Number of non-NULL non-data flits over QPI", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t ivbep_unc_q_rxl_flits_g1[]={ { .uname = "DRS", .udesc = "Number of flits over QPI on the Data Response (DRS) channel", .ucode = 0x1800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "DRS_DATA", .udesc = "Number of data flits over QPI on the Data Response (DRS) channel", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "DRS_NONDATA", .udesc = "Number of protocol flits over QPI on the Data Response (DRS) channel", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "HOM", .udesc = "Number of flits over QPI on the home channel", .ucode = 0x600, .uflags = INTEL_X86_NCOMBO, }, { .uname = "HOM_NONREQ", .udesc = "Number of non-request flits over QPI on the home channel", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "HOM_REQ", .udesc = "Number of data requests over QPI on the home channel", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "SNP", .udesc = "Number of snoop requests flits over QPI", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t ivbep_unc_q_rxl_flits_g2[]={ { .uname = "NCB", .udesc = "Number of non-coherent bypass flits", .ucode = 0xc00, .uflags = INTEL_X86_NCOMBO, }, { .uname = "NCB_DATA", .udesc = "Number of non-coherent data flits", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "NCB_NONDATA", .udesc = "Number of bypass non-data flits", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "NCS", .udesc = "Number of non-coherent standard (NCS) flits", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "NDR_AD", .udesc = "Number of flits received over Non-data response (NDR) channel", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "NDR_AK", .udesc = "Number of flits received on the Non-data response (NDR) channel)", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t ivbep_unc_q_txr_ad_hom_credit_acquired[]={ { .uname = "VN0", .udesc = "for VN0", .ucode = 0x100, }, { .uname = "VN1", .udesc = "for VN1", .ucode = 0x200, }, }; static const intel_x86_umask_t ivbep_unc_q_txr_bl_drs_credit_acquired[]={ { .uname = "VN0", .udesc = "for VN0", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "VN1", .udesc = "for VN1", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "VN_SHR", .udesc = "for shared VN", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_entry_t intel_ivbep_unc_q_pe[]={ { .name = "UNC_Q_CLOCKTICKS", .desc = "Number of qfclks", .code = 0x14, .cntmsk = 0xf, .modmsk = IVBEP_UNC_QPI_ATTRS, }, { .name = "UNC_Q_CTO_COUNT", .desc = "Count of CTO Events", .code = 0x38 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = IVBEP_UNC_QPI_ATTRS, }, { .name = "UNC_Q_DIRECT2CORE", .desc = "Direct 2 Core Spawning", .code = 0x13, .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_direct2core), .umasks = ivbep_unc_q_direct2core }, { .name = "UNC_Q_L1_POWER_CYCLES", .desc = "Cycles in L1", .code = 0x12, .cntmsk = 0xf, .modmsk = IVBEP_UNC_QPI_ATTRS, }, { .name = "UNC_Q_RXL0P_POWER_CYCLES", .desc = "Cycles in L0p", .code = 0x10, .cntmsk = 0xf, .modmsk = IVBEP_UNC_QPI_ATTRS, }, { .name = "UNC_Q_RXL0_POWER_CYCLES", .desc = "Cycles in L0", .code = 0xf, .cntmsk = 0xf, .modmsk = IVBEP_UNC_QPI_ATTRS, }, { .name = "UNC_Q_RXL_BYPASSED", .desc = "Rx Flit Buffer Bypassed", .code = 0x9, .cntmsk = 0xf, .modmsk = IVBEP_UNC_QPI_ATTRS, }, { .name = "UNC_Q_RXL_CREDITS_CONSUMED_VN0", .desc = "VN0 Credit Consumed", .code = 0x1e | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_rxl_credits_consumed_vn0), .umasks = ivbep_unc_q_rxl_credits_consumed_vn0 }, { .name = "UNC_Q_RXL_CREDITS_CONSUMED_VN1", .desc = "VN1 Credit Consumed", .code = 0x39 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_rxl_credits_consumed_vn1), .umasks = ivbep_unc_q_rxl_credits_consumed_vn1 }, { .name = "UNC_Q_RXL_CREDITS_CONSUMED_VNA", .desc = "VNA Credit Consumed", .code = 0x1d | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = IVBEP_UNC_QPI_ATTRS, }, { .name = "UNC_Q_RXL_CYCLES_NE", .desc = "RxQ Cycles Not Empty", .code = 0xa, .cntmsk = 0xf, .modmsk = IVBEP_UNC_QPI_ATTRS, }, { .name = "UNC_Q_RXL_FLITS_G0", .desc = "Flits Received - Group 0", .code = 0x1, .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_rxl_flits_g0), .umasks = ivbep_unc_q_rxl_flits_g0 }, { .name = "UNC_Q_RXL_FLITS_G1", .desc = "Flits Received - Group 1", .code = 0x2 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_rxl_flits_g1), .umasks = ivbep_unc_q_rxl_flits_g1 }, { .name = "UNC_Q_RXL_FLITS_G2", .desc = "Flits Received - Group 2", .code = 0x3 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_rxl_flits_g2), .umasks = ivbep_unc_q_rxl_flits_g2 }, { .name = "UNC_Q_RXL_INSERTS", .desc = "Rx Flit Buffer Allocations", .code = 0x8, .cntmsk = 0xf, .modmsk = IVBEP_UNC_QPI_ATTRS, }, { .name = "UNC_Q_RXL_INSERTS_DRS", .desc = "Rx Flit Buffer Allocations - DRS", .code = 0x9 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = IVBEP_UNC_QPI_ATTRS, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_txr_ad_hom_credit_acquired), .umasks = ivbep_unc_q_txr_ad_hom_credit_acquired, }, { .name = "UNC_Q_RXL_INSERTS_HOM", .desc = "Rx Flit Buffer Allocations - HOM", .code = 0xc | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = IVBEP_UNC_QPI_ATTRS, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_txr_ad_hom_credit_acquired), .umasks = ivbep_unc_q_txr_ad_hom_credit_acquired, }, { .name = "UNC_Q_RXL_INSERTS_NCB", .desc = "Rx Flit Buffer Allocations - NCB", .code = 0xa | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = IVBEP_UNC_QPI_ATTRS, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_txr_ad_hom_credit_acquired), .umasks = ivbep_unc_q_txr_ad_hom_credit_acquired, }, { .name = "UNC_Q_RXL_INSERTS_NCS", .desc = "Rx Flit Buffer Allocations - NCS", .code = 0xb | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = IVBEP_UNC_QPI_ATTRS, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_txr_ad_hom_credit_acquired), .umasks = ivbep_unc_q_txr_ad_hom_credit_acquired, }, { .name = "UNC_Q_RXL_INSERTS_NDR", .desc = "Rx Flit Buffer Allocations - NDR", .code = 0xe | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = IVBEP_UNC_QPI_ATTRS, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_txr_ad_hom_credit_acquired), .umasks = ivbep_unc_q_txr_ad_hom_credit_acquired, }, { .name = "UNC_Q_RXL_INSERTS_SNP", .desc = "Rx Flit Buffer Allocations - SNP", .code = 0xd | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = IVBEP_UNC_QPI_ATTRS, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_txr_ad_hom_credit_acquired), .umasks = ivbep_unc_q_txr_ad_hom_credit_acquired, }, { .name = "UNC_Q_RXL_OCCUPANCY", .desc = "RxQ Occupancy - All Packets", .code = 0xb, .cntmsk = 0xf, .modmsk = IVBEP_UNC_QPI_ATTRS, }, { .name = "UNC_Q_RXL_OCCUPANCY_DRS", .desc = "RxQ Occupancy - DRS", .code = 0x15 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = IVBEP_UNC_QPI_ATTRS, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_txr_ad_hom_credit_acquired), .umasks = ivbep_unc_q_txr_ad_hom_credit_acquired, }, { .name = "UNC_Q_RXL_OCCUPANCY_HOM", .desc = "RxQ Occupancy - HOM", .code = 0x18 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = IVBEP_UNC_QPI_ATTRS, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_txr_ad_hom_credit_acquired), .umasks = ivbep_unc_q_txr_ad_hom_credit_acquired, }, { .name = "UNC_Q_RXL_OCCUPANCY_NCB", .desc = "RxQ Occupancy - NCB", .code = 0x16 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = IVBEP_UNC_QPI_ATTRS, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_txr_ad_hom_credit_acquired), .umasks = ivbep_unc_q_txr_ad_hom_credit_acquired, }, { .name = "UNC_Q_RXL_OCCUPANCY_NCS", .desc = "RxQ Occupancy - NCS", .code = 0x17 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = IVBEP_UNC_QPI_ATTRS, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_txr_ad_hom_credit_acquired), .umasks = ivbep_unc_q_txr_ad_hom_credit_acquired, }, { .name = "UNC_Q_RXL_OCCUPANCY_NDR", .desc = "RxQ Occupancy - NDR", .code = 0x1a | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = IVBEP_UNC_QPI_ATTRS, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_txr_ad_hom_credit_acquired), .umasks = ivbep_unc_q_txr_ad_hom_credit_acquired, }, { .name = "UNC_Q_RXL_OCCUPANCY_SNP", .desc = "RxQ Occupancy - SNP", .code = 0x19 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = IVBEP_UNC_QPI_ATTRS, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_txr_ad_hom_credit_acquired), .umasks = ivbep_unc_q_txr_ad_hom_credit_acquired, }, { .name = "UNC_Q_TXL0P_POWER_CYCLES", .desc = "Cycles in L0p", .code = 0xd, .cntmsk = 0xf, .modmsk = IVBEP_UNC_QPI_ATTRS, }, { .name = "UNC_Q_TXL0_POWER_CYCLES", .desc = "Cycles in L0", .code = 0xc, .cntmsk = 0xf, .modmsk = IVBEP_UNC_QPI_ATTRS, }, { .name = "UNC_Q_TXL_BYPASSED", .desc = "Tx Flit Buffer Bypassed", .code = 0x5, .cntmsk = 0xf, .modmsk = IVBEP_UNC_QPI_ATTRS, }, { .name = "UNC_Q_TXL_CYCLES_NE", .desc = "Tx Flit Buffer Cycles not Empty", .code = 0x6, .cntmsk = 0xf, .modmsk = IVBEP_UNC_QPI_ATTRS, }, { .name = "UNC_Q_TXL_FLITS_G0", .desc = "Flits Transferred - Group 0", .code = 0x0, .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_txl_flits_g0), .umasks = ivbep_unc_q_txl_flits_g0 }, { .name = "UNC_Q_TXL_FLITS_G1", .desc = "Flits Transferred - Group 1", .code = 0x0 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_rxl_flits_g1), .umasks = ivbep_unc_q_rxl_flits_g1 /* shared with rxl_flits_g1 */ }, { .name = "UNC_Q_TXL_FLITS_G2", .desc = "Flits Transferred - Group 2", .code = 0x1 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_rxl_flits_g2), .umasks = ivbep_unc_q_rxl_flits_g2 /* shared with rxl_flits_g2 */ }, { .name = "UNC_Q_TXL_INSERTS", .desc = "Tx Flit Buffer Allocations", .code = 0x4, .cntmsk = 0xf, .modmsk = IVBEP_UNC_QPI_ATTRS, }, { .name = "UNC_Q_TXL_OCCUPANCY", .desc = "Tx Flit Buffer Occupancy", .code = 0x7, .cntmsk = 0xf, .modmsk = IVBEP_UNC_QPI_ATTRS, }, { .name = "UNC_Q_VNA_CREDIT_RETURNS", .desc = "VNA Credits Returned", .code = 0x1c | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = IVBEP_UNC_QPI_ATTRS, }, { .name = "UNC_Q_VNA_CREDIT_RETURN_OCCUPANCY", .desc = "VNA Credits Pending Return - Occupancy", .code = 0x1b | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = IVBEP_UNC_QPI_ATTRS, }, { .name = "UNC_Q_TXR_AD_HOM_CREDIT_ACQUIRED", .desc = "R3QPI Egress credit occupancy AD HOM", .code = 0x26 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_txr_ad_hom_credit_acquired), .umasks = ivbep_unc_q_txr_ad_hom_credit_acquired, }, { .name = "UNC_Q_TXR_AD_HOM_CREDIT_OCCUPANCY", .desc = "R3QPI Egress credit occupancy AD HOM", .code = 0x22 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_txr_ad_hom_credit_acquired), /* shared */ .umasks = ivbep_unc_q_txr_ad_hom_credit_acquired, }, { .name = "UNC_Q_TXR_AD_NDR_CREDIT_ACQUIRED", .desc = "R3QPI Egress credit occupancy AD NDR", .code = 0x28 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_txr_ad_hom_credit_acquired), .umasks = ivbep_unc_q_txr_ad_hom_credit_acquired, }, { .name = "UNC_Q_TXR_AD_NDR_CREDIT_OCCUPANCY", .desc = "R3QPI Egress credit occupancy AD NDR", .code = 0x24 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_txr_ad_hom_credit_acquired), /* shared */ .umasks = ivbep_unc_q_txr_ad_hom_credit_acquired, }, { .name = "UNC_Q_TXR_AD_SNP_CREDIT_ACQUIRED", .desc = "R3QPI Egress credit occupancy AD SNP", .code = 0x27 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_txr_ad_hom_credit_acquired), .umasks = ivbep_unc_q_txr_ad_hom_credit_acquired, }, { .name = "UNC_Q_TXR_AD_SNP_CREDIT_OCCUPANCY", .desc = "R3QPI Egress credit occupancy AD SNP", .code = 0x23 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_txr_ad_hom_credit_acquired), /* shared */ .umasks = ivbep_unc_q_txr_ad_hom_credit_acquired, }, { .name = "UNC_Q_TXR_AK_NDR_CREDIT_ACQUIRED", .desc = "R3QPI Egress credit occupancy AK NDR", .code = 0x29 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_txr_ad_hom_credit_acquired), .umasks = ivbep_unc_q_txr_ad_hom_credit_acquired, }, { .name = "UNC_Q_TXR_AK_NDR_CREDIT_OCCUPANCY", .desc = "R3QPI Egress credit occupancy AD NDR", .code = 0x25 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_txr_ad_hom_credit_acquired), /* shared */ .umasks = ivbep_unc_q_txr_ad_hom_credit_acquired, }, { .name = "UNC_Q_TXR_BL_DRS_CREDIT_ACQUIRED", .desc = "R3QPI Egress credit occupancy BL DRS", .code = 0x2a | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_txr_bl_drs_credit_acquired), .umasks = ivbep_unc_q_txr_bl_drs_credit_acquired, }, { .name = "UNC_Q_TXR_BL_DRS_CREDIT_OCCUPANCY", .desc = "R3QPI Egress credit occupancy BL DRS", .code = 0x1f | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_txr_bl_drs_credit_acquired), /* shared */ .umasks = ivbep_unc_q_txr_bl_drs_credit_acquired, }, { .name = "UNC_Q_TXR_BL_NCB_CREDIT_ACQUIRED", .desc = "R3QPI Egress credit occupancy BL NCB", .code = 0x2b | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_txr_ad_hom_credit_acquired), .umasks = ivbep_unc_q_txr_ad_hom_credit_acquired, }, { .name = "UNC_Q_TXR_BL_NCB_CREDIT_OCCUPANCY", .desc = "R3QPI Egress credit occupancy BL NCB", .code = 0x20 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_txr_ad_hom_credit_acquired), /* shared */ .umasks = ivbep_unc_q_txr_ad_hom_credit_acquired, }, { .name = "UNC_Q_TXR_BL_NCS_CREDIT_ACQUIRED", .desc = "R3QPI Egress credit occupancy BL NCS", .code = 0x2c | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_txr_ad_hom_credit_acquired), .umasks = ivbep_unc_q_txr_ad_hom_credit_acquired, }, { .name = "UNC_Q_TXR_BL_NCS_CREDIT_OCCUPANCY", .desc = "R3QPI Egress credit occupancy BL NCS", .code = 0x21 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_txr_ad_hom_credit_acquired), /* shared */ .umasks = ivbep_unc_q_txr_ad_hom_credit_acquired, }, }; libpfm-4.9.0/lib/events/arm_xgene_events.h0000664000175000017500000003261513223402656020401 0ustar eranianeranian/* * Copyright (c) 2014 Red Hat Inc. All rights reserved * Contributed by William Cohen * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * Applied Micro X-Gene * based on https://github.com/AppliedMicro/ENGLinuxLatest/blob/apm_linux_v3.17-rc4/Documentation/arm64/xgene_pmu.txt */ static const arm_entry_t arm_xgene_pe[]={ {.name = "SW_INCR", .modmsk = ARMV8_ATTRS, .code = 0x00, .desc = "Instruction architecturally executed (condition check pass) software increment" }, {.name = "L1I_CACHE_REFILL", .modmsk = ARMV8_ATTRS, .code = 0x01, .desc = "Level 1 instruction cache refill" }, {.name = "L1I_TLB_REFILL", .modmsk = ARMV8_ATTRS, .code = 0x02, .desc = "Level 1 instruction TLB refill" }, {.name = "L1D_CACHE_REFILL", .modmsk = ARMV8_ATTRS, .code = 0x03, .desc = "Level 1 data cache refill" }, {.name = "L1D_CACHE_ACCESS", .modmsk = ARMV8_ATTRS, .code = 0x04, .desc = "Level 1 data cache access" }, {.name = "L1D_TLB_REFILL", .modmsk = ARMV8_ATTRS, .code = 0x05, .desc = "Level 1 data TLB refill" }, {.name = "INST_RETIRED", .modmsk = ARMV8_ATTRS, .code = 0x08, .desc = "Instruction architecturally executed" }, {.name = "EXCEPTION_TAKEN", .modmsk = ARMV8_ATTRS, .code = 0x09, .desc = "Exception taken" }, {.name = "EXCEPTION_RETURN", .modmsk = ARMV8_ATTRS, .code = 0x0a, .desc = "Instruction architecturally executed (condition check pass) - Exception return" }, {.name = "CID_WRITE_RETIRED", .modmsk = ARMV8_ATTRS, .code = 0x0b, .desc = "Instruction architecturally executed (condition check pass) - Write to CONTEXTIDR", }, {.name = "BRANCH_MISPRED", .modmsk = ARMV8_ATTRS, .code = 0x10, .desc = "Mispredicted or not predicted branch speculatively executed" }, {.name = "CPU_CYCLES", .modmsk = ARMV8_ATTRS, .code = 0x11, .desc = "Cycles" }, {.name = "BRANCH_PRED", .modmsk = ARMV8_ATTRS, .code = 0x12, .desc = "Predictable branch speculatively executed" }, {.name = "DATA_MEM_ACCESS", .modmsk = ARMV8_ATTRS, .code = 0x13, .desc = "Data memory access" }, {.name = "L1I_CACHE_ACCESS", .modmsk = ARMV8_ATTRS, .code = 0x14, .desc = "Level 1 instruction cache access" }, {.name = "L2D_CACHE_ACCESS", .modmsk = ARMV8_ATTRS, .code = 0x16, .desc = "Level 2 data cache access" }, {.name = "L2D_CACHE_REFILL", .modmsk = ARMV8_ATTRS, .code = 0x17, .desc = "Level 2 data cache refill" }, {.name = "L2D_CACHE_WB", .modmsk = ARMV8_ATTRS, .code = 0x18, .desc = "Level 2 data cache WriteBack" }, {.name = "BUS_ACCESS", .modmsk = ARMV8_ATTRS, .code = 0x19, .desc = "Bus access" }, {.name = "LOCAL_MEMORY_ERROR", .modmsk = ARMV8_ATTRS, .code = 0x1a, .desc = "Local memory error" }, {.name = "INST_SPEC_EXEC", .modmsk = ARMV8_ATTRS, .code = 0x1b, .desc = "Instruction speculatively executed" }, {.name = "TTBR_WRITE_RETIRED", .modmsk = ARMV8_ATTRS, .code = 0x1c, .desc = "Instruction architecturally executed (condition check pass) Write to translation table base" }, {.name = "L1D_READ_ACCESS", .modmsk = ARMV8_ATTRS, .code = 0x40, .desc = "Level 1 data cache read access" }, {.name = "L1D_WRITE_ACCESS", .modmsk = ARMV8_ATTRS, .code = 0x41, .desc = "Level 1 data cache write access" }, {.name = "L1D_READ_REFILL", .modmsk = ARMV8_ATTRS, .code = 0x42, .desc = "Level 1 data cache read refill" }, {.name = "L1D_INVALIDATE", .modmsk = ARMV8_ATTRS, .code = 0x48, .desc = "Level 1 data cache invalidate" }, {.name = "L1D_TLB_READ_REFILL", .modmsk = ARMV8_ATTRS, .code = 0x4c, .desc = "Level 1 data TLB read refill" }, {.name = "L1D_TLB_WRITE_REFILL", .modmsk = ARMV8_ATTRS, .code = 0x4d, .desc = "Level 1 data TLB write refill" }, {.name = "L2D_READ_ACCESS", .modmsk = ARMV8_ATTRS, .code = 0x50, .desc = "Level 2 data cache read access" }, {.name = "L2D_WRITE_ACCESS", .modmsk = ARMV8_ATTRS, .code = 0x51, .desc = "Level 2 data cache write access" }, {.name = "L2D_READ_REFILL", .modmsk = ARMV8_ATTRS, .code = 0x52, .desc = "Level 2 data cache read refill" }, {.name = "L2D_WRITE_REFILL", .modmsk = ARMV8_ATTRS, .code = 0x53, .desc = "Level 2 data cache write refill" }, {.name = "L2D_WB_VICTIM", .modmsk = ARMV8_ATTRS, .code = 0x56, .desc = "Level 2 data cache writeback victim" }, {.name = "L2D_WB_CLEAN_COHERENCY", .modmsk = ARMV8_ATTRS, .code = 0x57, .desc = "Level 2 data cache writeback cleaning and coherency" }, {.name = "L2D_INVALIDATE", .modmsk = ARMV8_ATTRS, .code = 0x58, .desc = "Level 2 data cache invalidate" }, {.name = "BUS_READ_ACCESS", .modmsk = ARMV8_ATTRS, .code = 0x60, .desc = "Bus read access" }, {.name = "BUS_WRITE_ACCESS", .modmsk = ARMV8_ATTRS, .code = 0x61, .desc = "Bus write access" }, {.name = "BUS_NORMAL_ACCESS", .modmsk = ARMV8_ATTRS, .code = 0x62, .desc = "Bus normal access" }, {.name = "BUS_NOT_NORMAL_ACCESS", .modmsk = ARMV8_ATTRS, .code = 0x63, .desc = "Bus not normal access" }, {.name = "BUS_NORMAL_ACCESS_2", .modmsk = ARMV8_ATTRS, .code = 0x64, .desc = "Bus normal access" }, {.name = "BUS_PERIPH_ACCESS", .modmsk = ARMV8_ATTRS, .code = 0x65, .desc = "Bus peripheral access" }, {.name = "DATA_MEM_READ_ACCESS", .modmsk = ARMV8_ATTRS, .code = 0x66, .desc = "Data memory read access" }, {.name = "DATA_MEM_WRITE_ACCESS", .modmsk = ARMV8_ATTRS, .code = 0x67, .desc = "Data memory write access" }, {.name = "UNALIGNED_READ_ACCESS", .modmsk = ARMV8_ATTRS, .code = 0x68, .desc = "Unaligned read access" }, {.name = "UNALIGNED_WRITE_ACCESS", .modmsk = ARMV8_ATTRS, .code = 0x69, .desc = "Unaligned read access" }, {.name = "UNALIGNED_ACCESS", .modmsk = ARMV8_ATTRS, .code = 0x6a, .desc = "Unaligned access" }, {.name = "INST_SPEC_EXEC_LDREX", .modmsk = ARMV8_ATTRS, .code = 0x6c, .desc = "Exclusive operation speculatively executed - Load exclusive" }, {.name = "INST_SPEC_EXEC_STREX_PASS", .modmsk = ARMV8_ATTRS, .code = 0x6d, .desc = "Exclusive operation speculative executed - Store exclusive pass" }, {.name = "INST_SPEC_EXEC_STREX_FAIL", .modmsk = ARMV8_ATTRS, .code = 0x6e, .desc = "Exclusive operation speculative executed - Store exclusive fail" }, {.name = "INST_SPEC_EXEC_STREX", .modmsk = ARMV8_ATTRS, .code = 0x6f, .desc = "Exclusive operation speculatively executed - Store exclusive" }, {.name = "INST_SPEC_EXEC_LOAD", .modmsk = ARMV8_ATTRS, .code = 0x70, .desc = "Load instruction speculatively executed" }, {.name = "INST_SPEC_EXEC_STORE", .modmsk = ARMV8_ATTRS, .code = 0x71, .desc = "Store instruction speculatively executed" }, {.name = "INST_SPEC_EXEC_LOAD_STORE", .modmsk = ARMV8_ATTRS, .code = 0x72, .desc = "Load or store instruction speculatively executed" }, {.name = "INST_SPEC_EXEC_INTEGER_INST", .modmsk = ARMV8_ATTRS, .code = 0x73, .desc = "Integer data processing instruction speculatively executed" }, {.name = "INST_SPEC_EXEC_SIMD", .modmsk = ARMV8_ATTRS, .code = 0x74, .desc = "Advanced SIMD instruction speculatively executed" }, {.name = "INST_SPEC_EXEC_VFP", .modmsk = ARMV8_ATTRS, .code = 0x75, .desc = "VFP instruction speculatively executed" }, {.name = "INST_SPEC_EXEC_SOFT_PC", .modmsk = ARMV8_ATTRS, .code = 0x76, .desc = "Software change of the PC instruction speculatively executed" }, {.name = "BRANCH_SPEC_EXEC_IMM_BRANCH", .modmsk = ARMV8_ATTRS, .code = 0x78, .desc = "Immediate branch speculatively executed" }, {.name = "BRANCH_SPEC_EXEC_RET", .modmsk = ARMV8_ATTRS, .code = 0x79, .desc = "Return branch speculatively executed" }, {.name = "BRANCH_SPEC_EXEC_IND", .modmsk = ARMV8_ATTRS, .code = 0x7a, .desc = "Indirect branch speculatively executed" }, {.name = "BARRIER_SPEC_EXEC_ISB", .modmsk = ARMV8_ATTRS, .code = 0x7c, .desc = "ISB barrier speculatively executed" }, {.name = "BARRIER_SPEC_EXEC_DSB", .modmsk = ARMV8_ATTRS, .code = 0x7d, .desc = "DSB barrier speculatively executed" }, {.name = "BARRIER_SPEC_EXEC_DMB", .modmsk = ARMV8_ATTRS, .code = 0x7e, .desc = "DMB barrier speculatively executed" }, {.name = "EXCEPTION_UNDEF", .modmsk = ARMV8_ATTRS, .code = 0x81, .desc = "Exception taken, other synchronous" }, {.name = "EXCEPTION_SVC", .modmsk = ARMV8_ATTRS, .code = 0x82, .desc = "Exception taken, supervisor call" }, {.name = "EXCEPTION_PABORT", .modmsk = ARMV8_ATTRS, .code = 0x83, .desc = "Exception taken, instruction abort" }, {.name = "EXCEPTION_DABORT", .modmsk = ARMV8_ATTRS, .code = 0x84, .desc = "Exception taken, data abort or SError" }, {.name = "EXCEPTION_IRQ", .modmsk = ARMV8_ATTRS, .code = 0x86, .desc = "Exception taken, irq" }, {.name = "EXCEPTION_FIQ", .modmsk = ARMV8_ATTRS, .code = 0x87, .desc = "Exception taken, fiq" }, {.name = "EXCEPTION_HVC", .modmsk = ARMV8_ATTRS, .code = 0x8a, .desc = "Exception taken, hypervisor call" }, {.name = "EXCEPTION_TRAP_PABORT", .modmsk = ARMV8_ATTRS, .code = 0x8b, .desc = "Exception taken, instruction abort not taken locally" }, {.name = "EXCEPTION_TRAP_DABORT", .modmsk = ARMV8_ATTRS, .code = 0x8c, .desc = "Exception taken, data abort or SError not taken locally" }, {.name = "EXCEPTION_TRAP_OTHER", .modmsk = ARMV8_ATTRS, .code = 0x8d, .desc = "Exception taken, other traps not taken locally" }, {.name = "EXCEPTION_TRAP_IRQ", .modmsk = ARMV8_ATTRS, .code = 0x8e, .desc = "Exception taken, irq not taken locally" }, {.name = "EXCEPTION_TRAP_FIQ", .modmsk = ARMV8_ATTRS, .code = 0x8f, .desc = "Exception taken, fiq not taken locally" }, {.name = "RC_LD_SPEC", .modmsk = ARMV8_ATTRS, .code = 0x90, .desc = "Release consistency instruction speculatively executed (load-acquire)", }, {.name = "RC_ST_SPEC", .modmsk = ARMV8_ATTRS, .code = 0x91, .desc = "Release consistency instruction speculatively executed (store-release)", }, {.name = "INST_SPEC_EXEC_NOP", .modmsk = ARMV8_ATTRS, .code = 0x100, .desc = "Operation speculatively executed - NOP", }, {.name = "FSU_CLOCK_OFF", .modmsk = ARMV8_ATTRS, .code = 0x101, .desc = "FSU clocking gated off cycle", }, {.name = "BTB_MISPREDICT", .modmsk = ARMV8_ATTRS, .code = 0x102, .desc = "BTB misprediction", }, {.name = "ITB_MISS", .modmsk = ARMV8_ATTRS, .code = 0x103, .desc = "ITB miss", }, {.name = "DTB_MISS", .modmsk = ARMV8_ATTRS, .code = 0x104, .desc = "DTB miss", }, {.name = "L1D_CACHE_LATE_MISS", .modmsk = ARMV8_ATTRS, .code = 0x105, .desc = "L1 data cache late miss", }, {.name = "L1D_CACHE_PREFETCH", .modmsk = ARMV8_ATTRS, .code = 0x106, .desc = "L1 data cache prefetch request", }, {.name = "L2_CACHE_PREFETCH", .modmsk = ARMV8_ATTRS, .code = 0x107, .desc = "L2 data prefetch request", }, {.name = "STALLED_CYCLES_FRONTEND", .modmsk = ARMV8_ATTRS, .code = 0x108, .desc = "Decode starved for instruction cycle", }, {.name = "STALLED_CYCLES_BACKEND", .modmsk = ARMV8_ATTRS, .code = 0x109, .desc = "Op dispatch stalled cycle", }, {.name = "IXA_NO_ISSUE", .modmsk = ARMV8_ATTRS, .code = 0x10A, .desc = "IXA Op non-issue", }, {.name = "IXB_NO_ISSUE", .modmsk = ARMV8_ATTRS, .code = 0x10B, .desc = "IXB Op non-issue", }, {.name = "BX_NO_ISSUE", .modmsk = ARMV8_ATTRS, .code = 0x10C, .desc = "BX Op non-issue", }, {.name = "LX_NO_ISSUE", .modmsk = ARMV8_ATTRS, .code = 0x10D, .desc = "LX Op non-issue", }, {.name = "SX_NO_ISSUE", .modmsk = ARMV8_ATTRS, .code = 0x10E, .desc = "SX Op non-issue", }, {.name = "FX_NO_ISSUE", .modmsk = ARMV8_ATTRS, .code = 0x10F, .desc = "FX Op non-issue", }, {.name = "WAIT_CYCLES", .modmsk = ARMV8_ATTRS, .code = 0x110, .desc = "Wait state cycle", }, {.name = "L1_STAGE2_TLB_REFILL", .modmsk = ARMV8_ATTRS, .code = 0x111, .desc = "L1 stage-2 TLB refill", }, {.name = "PAGE_WALK_L0_STAGE1_HIT", .modmsk = ARMV8_ATTRS, .code = 0x112, .desc = "Page Walk Cache level-0 stage-1 hit", }, {.name = "PAGE_WALK_L1_STAGE1_HIT", .modmsk = ARMV8_ATTRS, .code = 0x113, .desc = "Page Walk Cache level-1 stage-1 hit", }, {.name = "PAGE_WALK_L2_STAGE1_HIT", .modmsk = ARMV8_ATTRS, .code = 0x114, .desc = "Page Walk Cache level-2 stage-1 hit", }, {.name = "PAGE_WALK_L1_STAGE2_HIT", .modmsk = ARMV8_ATTRS, .code = 0x115, .desc = "Page Walk Cache level-1 stage-2 hit", }, {.name = "PAGE_WALK_L2_STAGE2_HIT", .modmsk = ARMV8_ATTRS, .code = 0x116, .desc = "Page Walk Cache level-2 stage-2 hit", }, /* END Applied Micro X-Gene specific events */ }; libpfm-4.9.0/lib/events/intel_glm_events.h0000664000175000017500000012635113223402656020407 0ustar eranianeranian/* * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * FILE AUTOMATICALLY GENERATED from download.01.org/perfmon/GLM/Goldmont_core_V6.json * PMU: glm (Intel Goldmont) */ static const intel_x86_umask_t glm_icache[]={ { .uname = "HIT", .udesc = "References per ICache line that are available in the ICache (hit). This event counts differently than Intel processors based on Silvermont microarchitecture", .ucode = 0x0100, .uflags = INTEL_X86_NCOMBO, .grpid = 0, .ucntmsk = 0xfull, }, { .uname = "MISSES", .udesc = "References per ICache line that are not available in the ICache (miss). This event counts differently than Intel processors based on Silvermont microarchitecture", .ucode = 0x0200, .uflags = INTEL_X86_NCOMBO, .grpid = 0, .ucntmsk = 0xfull, }, { .uname = "ACCESSES", .udesc = "References per ICache line. This event counts differently than Intel processors based on Silvermont microarchitecture", .ucode = 0x0300, .uflags = INTEL_X86_NCOMBO, .grpid = 0, .ucntmsk = 0xfull, }, }; static const intel_x86_umask_t glm_l2_reject_xq[]={ { .uname = "ALL", .udesc = "Requests rejected by the XQ", .ucode = 0x0000, .uflags = INTEL_X86_DFL, .grpid = 0, .ucntmsk = 0xfull, }, }; static const intel_x86_umask_t glm_hw_interrupts[]={ { .uname = "RECEIVED", .udesc = "Hardware interrupts received", .ucode = 0x0100, .uflags = INTEL_X86_NCOMBO, .grpid = 0, .ucntmsk = 0xfull, }, { .uname = "PENDING_AND_MASKED", .udesc = "Cycles pending interrupts are masked", .ucode = 0x0400, .uflags = INTEL_X86_NCOMBO, .grpid = 0, .ucntmsk = 0xfull, }, }; static const intel_x86_umask_t glm_br_misp_retired[]={ { .uname = "ALL_BRANCHES", .udesc = "Retired mispredicted branch instructions (Precise Event)", .ucode = 0x0000, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS | INTEL_X86_DFL, .grpid = 0, .ucntmsk = 0xfull, }, { .uname = "JCC", .udesc = "Retired mispredicted conditional branch instructions (Precise Event)", .ucode = 0x7e00, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, .grpid = 0, .ucntmsk = 0xfull, }, { .uname = "TAKEN_JCC", .udesc = "Retired mispredicted conditional branch instructions that were taken (Precise Event)", .ucode = 0xfe00, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, .grpid = 0, .ucntmsk = 0xfull, }, { .uname = "IND_CALL", .udesc = "Retired mispredicted near indirect call instructions (Precise Event)", .ucode = 0xfb00, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, .grpid = 0, .ucntmsk = 0xfull, }, { .uname = "RETURN", .udesc = "Retired mispredicted near return instructions (Precise Event)", .ucode = 0xf700, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, .grpid = 0, .ucntmsk = 0xfull, }, { .uname = "NON_RETURN_IND", .udesc = "Retired mispredicted instructions of near indirect Jmp or near indirect call (Precise Event)", .ucode = 0xeb00, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, .grpid = 0, .ucntmsk = 0xfull, }, }; static const intel_x86_umask_t glm_decode_restriction[]={ { .uname = "PREDECODE_WRONG", .udesc = "Decode restrictions due to predicting wrong instruction length", .ucode = 0x0100, .uflags = INTEL_X86_DFL, .grpid = 0, .ucntmsk = 0xfull, }, }; static const intel_x86_umask_t glm_misalign_mem_ref[]={ { .uname = "LOAD_PAGE_SPLIT", .udesc = "Load uops that split a page (Precise Event)", .ucode = 0x0200, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, .grpid = 0, .ucntmsk = 0xfull, }, { .uname = "STORE_PAGE_SPLIT", .udesc = "Store uops that split a page (Precise Event)", .ucode = 0x0400, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, .grpid = 0, .ucntmsk = 0xfull, }, }; static const intel_x86_umask_t glm_inst_retired[]={ { .uname = "ANY_P", .udesc = "Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The event continues counting during hardware interrupts, traps, and inside interrupt handlers. This is an architectural performance event. This event uses a (_P)rogrammable general purpose performance counter. *This event is Precise Event capable: The EventingRIP field in the PEBS record is precise to the address of the instruction which caused the event. Note: Because PEBS records can be collected only on IA32_PMC0, only one event can use the PEBS facility at a time.", .ucode = 0x0000, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS | INTEL_X86_DFL, .grpid = 0, .ucntmsk = 0xfull, }, }; static const intel_x86_umask_t glm_issue_slots_not_consumed[]={ { .uname = "RESOURCE_FULL", .udesc = "Unfilled issue slots per cycle because of a full resource in the backend", .ucode = 0x0100, .uflags = INTEL_X86_NCOMBO, .grpid = 0, .ucntmsk = 0xfull, }, { .uname = "RECOVERY", .udesc = "Unfilled issue slots per cycle to recover", .ucode = 0x0200, .uflags = INTEL_X86_NCOMBO, .grpid = 0, .ucntmsk = 0xfull, }, { .uname = "ANY", .udesc = "Unfilled issue slots per cycle", .ucode = 0x0000, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, .grpid = 0, .ucntmsk = 0xfull, }, }; static const intel_x86_umask_t glm_itlb[]={ { .uname = "MISS", .udesc = "ITLB misses", .ucode = 0x0400, .uflags = INTEL_X86_DFL, .grpid = 0, .ucntmsk = 0xfull, }, }; static const intel_x86_umask_t glm_longest_lat_cache[]={ { .uname = "REFERENCE", .udesc = "L2 cache requests", .ucode = 0x4f00, .uflags = INTEL_X86_NCOMBO, .grpid = 0, .ucntmsk = 0xfull, }, { .uname = "MISS", .udesc = "L2 cache request misses", .ucode = 0x4100, .uflags = INTEL_X86_NCOMBO, .grpid = 0, .ucntmsk = 0xfull, }, }; static const intel_x86_umask_t glm_mem_load_uops_retired[]={ { .uname = "L1_HIT", .udesc = "Load uops retired that hit L1 data cache (Precise Event)", .ucode = 0x0100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, .grpid = 0, .ucntmsk = 0xfull, }, { .uname = "L1_MISS", .udesc = "Load uops retired that missed L1 data cache (Precise Event)", .ucode = 0x0800, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, .grpid = 0, .ucntmsk = 0xfull, }, { .uname = "L2_HIT", .udesc = "Load uops retired that hit L2 (Precise Event)", .ucode = 0x0200, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, .grpid = 0, .ucntmsk = 0xfull, }, { .uname = "L2_MISS", .udesc = "Load uops retired that missed L2 (Precise Event)", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, .grpid = 0, .ucntmsk = 0xfull, }, { .uname = "HITM", .udesc = "Memory uop retired where cross core or cross module HITM occurred (Precise Event)", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, .grpid = 0, .ucntmsk = 0xfull, }, { .uname = "WCB_HIT", .udesc = "Loads retired that hit WCB (Precise Event)", .ucode = 0x4000, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, .grpid = 0, .ucntmsk = 0xfull, }, { .uname = "DRAM_HIT", .udesc = "Loads retired that came from DRAM (Precise Event)", .ucode = 0x8000, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, .grpid = 0, .ucntmsk = 0xfull, }, }; static const intel_x86_umask_t glm_ld_blocks[]={ { .uname = "ALL_BLOCK", .udesc = "Loads blocked (Precise Event)", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, .grpid = 0, .ucntmsk = 0xfull, }, { .uname = "UTLB_MISS", .udesc = "Loads blocked because address in not in the UTLB (Precise Event)", .ucode = 0x0800, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, .grpid = 0, .ucntmsk = 0xfull, }, { .uname = "STORE_FORWARD", .udesc = "Loads blocked due to store forward restriction (Precise Event)", .ucode = 0x0200, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, .grpid = 0, .ucntmsk = 0xfull, }, { .uname = "DATA_UNKNOWN", .udesc = "Loads blocked due to store data not ready (Precise Event)", .ucode = 0x0100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, .grpid = 0, .ucntmsk = 0xfull, }, { .uname = "4K_ALIAS", .udesc = "Loads blocked because address has 4k partial address false dependence (Precise Event)", .ucode = 0x0400, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, .grpid = 0, .ucntmsk = 0xfull, }, }; static const intel_x86_umask_t glm_dl1[]={ { .uname = "DIRTY_EVICTION", .udesc = "L1 Cache evictions for dirty data", .ucode = 0x0100, .uflags = INTEL_X86_DFL, .grpid = 0, .ucntmsk = 0xfull, }, }; static const intel_x86_umask_t glm_cycles_div_busy[]={ { .uname = "ALL", .udesc = "Cycles a divider is busy", .ucode = 0x0000, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, .grpid = 0, .ucntmsk = 0xfull, }, { .uname = "IDIV", .udesc = "Cycles the integer divide unit is busy", .ucode = 0x0100, .uflags = INTEL_X86_NCOMBO, .grpid = 0, .ucntmsk = 0xfull, }, { .uname = "FPDIV", .udesc = "Cycles the FP divide unit is busy", .ucode = 0x0200, .uflags = INTEL_X86_NCOMBO, .grpid = 0, .ucntmsk = 0xfull, }, }; static const intel_x86_umask_t glm_ms_decoded[]={ { .uname = "MS_ENTRY", .udesc = "MS decode starts", .ucode = 0x0100, .uflags = INTEL_X86_DFL, .grpid = 0, .ucntmsk = 0xfull, }, }; static const intel_x86_umask_t glm_uops_retired[]={ { .uname = "ANY", .udesc = "Uops retired (Precise Event)", .ucode = 0x0000, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS | INTEL_X86_DFL, .grpid = 0, .ucntmsk = 0xfull, }, { .uname = "MS", .udesc = "MS uops retired (Precise Event)", .ucode = 0x0100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, .grpid = 0, .ucntmsk = 0xfull, }, }; static const intel_x86_umask_t glm_offcore_response_0[]={ { .uname = "DMND_DATA_RD", .udesc = "Request: number of demand and DCU prefetch data reads of full and partial cachelines as well as demand data page table entry cacheline reads. Does not count L2 data read prefetches or instruction fetches", .ucode = 1ULL << (0 + 8), .grpid = 0, .ucntmsk = 0xffull, }, { .uname = "DMND_RFO", .udesc = "Request: number of demand and DCU prefetch reads for ownership (RFO) requests generated by a write to data cacheline. Does not count L2 RFO prefetches", .ucode = 1ULL << (1 + 8), .grpid = 0, .ucntmsk = 0xffull, }, { .uname = "DMND_CODE_RD", .udesc = "Request: number of demand and DCU prefetch instruction cacheline reads. Does not count L2 code read prefetches", .ucode = 1ULL << (2 + 8), .grpid = 0, .ucntmsk = 0xffull, }, { .uname = "WB", .udesc = "Request: number of writebacks (modified to exclusive) transactions", .ucode = 1ULL << (3 + 8), .grpid = 0, .ucntmsk = 0xffull, }, { .uname = "PF_DATA_RD", .udesc = "Request: number of data cacheline reads generated by L2 prefetcher", .ucode = 1ULL << (4 + 8), .grpid = 0, .ucntmsk = 0xffull, }, { .uname = "PF_RFO", .udesc = "Request: number of RFO requests generated by L2 prefetcher", .ucode = 1ULL << (5 + 8), .grpid = 0, .ucntmsk = 0xffull, }, { .uname = "PARTIAL_READS", .udesc = "Request: number of partil reads", .ucode = 1ULL << (7 + 8), .grpid = 0, .ucntmsk = 0xffull, }, { .uname = "PARTIAL_WRITES", .udesc = "Request: number of partial writes", .ucode = 1ULL << (8 + 8), .grpid = 0, .ucntmsk = 0xffull, }, { .uname = "UC_CODE_READS", .udesc = "Request: number of uncached code reads", .ucode = 1ULL << (9 + 8), .grpid = 0, .ucntmsk = 0xffull, }, { .uname = "BUS_LOCKS", .udesc = "Request: number of bus lock and split lock requests", .ucode = 1ULL << (10 + 8), .grpid = 0, .ucntmsk = 0xffull, }, { .uname = "FULL_STRM_ST", .udesc = "Request: number of streaming store requests for full cacheline", .ucode = 1ULL << (11 + 8), .grpid = 0, .ucntmsk = 0xffull, }, { .uname = "SW_PF", .udesc = "Request: number of cacheline requests due to software prefetch", .ucode = 1ULL << (12 + 8), .grpid = 0, .ucntmsk = 0xffull, }, { .uname = "PF_L1_DATA_RD", .udesc = "Request: number of data cacheline reads generated by L1 data prefetcher", .ucode = 1ULL << (13 + 8), .grpid = 0, .ucntmsk = 0xffull, }, { .uname = "PARTIAL_STRM_ST", .udesc = "Request: number of streaming store requests for partial cacheline", .ucode = 1ULL << (14 + 8), .grpid = 0, .ucntmsk = 0xffull, }, { .uname = "STRM_ST", .udesc = "Request: number of streaming store requests for partial or full cacheline", .ucode = (1ULL << (14 + 8)) | (1ULL << (11+8)), .uequiv = "FULL_STRM_ST:PARTIAL_STRM_ST", .grpid = 0, .ucntmsk = 0xffull, }, { .uname = "ANY_REQUEST", .udesc = "Request: combination of all request umasks", .ucode = 1ULL << (15 + 8), .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, .grpid = 0, .ucntmsk = 0xffull, }, { .uname = "ANY_PF_DATA_RD", .udesc = "Request: number of prefetch data reads", .ucode = (1ULL << (4+8)) | (1ULL << (12+8)) | (1ULL << (13+8)), .grpid = 0, .ucntmsk = 0xffull, .uequiv = "PF_DATA_RD:SW_PF:PF_L1_DATA_RD", }, { .uname = "ANY_RFO", .udesc = "Request: number of RFO", .ucode = (1ULL << (1+8)) | (1ULL << (5+8)), .grpid = 0, .ucntmsk = 0xffull, .uequiv = "DMND_RFO:PF_RFO", }, { .uname = "ANY_RESPONSE", .udesc = "Response: any response type", .ucode = 1ULL << (16 + 8), .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL | INTEL_X86_EXCL_GRP_GT, .grpid = 1, .ucntmsk = 0xffull, }, { .uname = "L2_HIT", .udesc = "Supplier: counts L2 hits", .ucode = 1ULL << (18 + 8), .grpid = 1, .ucntmsk = 0xffull, }, { .uname = "L2_MISS_SNP_MISS_OR_NO_SNOOP_NEEDED", .udesc = "Snoop: counts number true misses to this processor module for which a snoop request missed the other processor module or no snoop was needed", .ucode = 1ULL << (33 + 8), .grpid = 2, .ucntmsk = 0xffull, }, { .uname = "L2_MISS_HIT_OTHER_CORE_NO_FWD", .udesc = "Snoop: counts number of times a snoop request hits the other processor module but no data forwarding is needed", .ucode = 1ULL << (34 + 8), .grpid = 2, .ucntmsk = 0xffull, }, { .uname = "L2_MISS_HITM_OTHER_CORE", .udesc = "Snoop: counts number of times a snoop request hits in the other processor module or other core's L1 where a modified copy (M-state) is found", .ucode = 1ULL << (36 + 8), .grpid = 2, .ucntmsk = 0xffull, }, { .uname = "L2_MISS_SNP_NON_DRAM", .udesc = "Snoop: counts number of times target was a non-DRAM system address. This includes MMIO transactions", .ucode = 1ULL << (37 + 8), .grpid = 2, .ucntmsk = 0xffull, }, { .uname = "L2_MISS_SNP_ANY", .udesc = "Snoop: any snoop reason", .ucode = 0x1bULL << (33 + 8), .uflags = INTEL_X86_DFL, .uequiv = "L2_MISS_SNP_MISS_OR_NO_SNOOP_NEEDED:L2_MISS_HIT_OTHER_CORE_NO_FWD:L2_MISS_HITM_OTHER_CORE:L2_MISS_SNP_NON_DRAM", .grpid = 2, .ucntmsk = 0xffull, }, { .uname = "OUTSTANDING", .udesc = "Outstanding request: counts weighted cycles of outstanding offcore requests of the request type specified in the bits 15:0 of offcore_response from the time the XQ receives the request and any response received. Bits 37:16 must be set to 0. This is only available for offcore_response_0", .ucode = 1ULL << (38 + 8), .uflags = INTEL_X86_GRP_DFL_NONE | INTEL_X86_EXCL_GRP_BUT_0, /* can only be combined with request type bits (grpid = 0) */ .grpid = 3, .ucntmsk = 0xffull, }, }; static const intel_x86_umask_t glm_offcore_response_1[]={ { .uname = "DMND_DATA_RD", .udesc = "Request: number of demand and DCU prefetch data reads of full and partial cachelines as well as demand data page table entry cacheline reads. Does not count L2 data read prefetches or instruction fetches", .ucode = 1ULL << (0 + 8), .grpid = 0, .ucntmsk = 0xffull, }, { .uname = "DMND_RFO", .udesc = "Request: number of demand and DCU prefetch reads for ownership (RFO) requests generated by a write to data cacheline. Does not count L2 RFO prefetches", .ucode = 1ULL << (1 + 8), .grpid = 0, .ucntmsk = 0xffull, }, { .uname = "DMND_CODE_RD", .udesc = "Request: number of demand and DCU prefetch instruction cacheline reads. Does not count L2 code read prefetches", .ucode = 1ULL << (2 + 8), .grpid = 0, .ucntmsk = 0xffull, }, { .uname = "WB", .udesc = "Request: number of writebacks (modified to exclusive) transactions", .ucode = 1ULL << (3 + 8), .grpid = 0, .ucntmsk = 0xffull, }, { .uname = "PF_DATA_RD", .udesc = "Request: number of data cacheline reads generated by L2 prefetcher", .ucode = 1ULL << (4 + 8), .grpid = 0, .ucntmsk = 0xffull, }, { .uname = "PF_RFO", .udesc = "Request: number of RFO requests generated by L2 prefetcher", .ucode = 1ULL << (5 + 8), .grpid = 0, .ucntmsk = 0xffull, }, { .uname = "PARTIAL_READS", .udesc = "Request: number of partil reads", .ucode = 1ULL << (7 + 8), .grpid = 0, .ucntmsk = 0xffull, }, { .uname = "PARTIAL_WRITES", .udesc = "Request: number of partial writes", .ucode = 1ULL << (8 + 8), .grpid = 0, .ucntmsk = 0xffull, }, { .uname = "UC_CODE_READS", .udesc = "Request: number of uncached code reads", .ucode = 1ULL << (9 + 8), .grpid = 0, .ucntmsk = 0xffull, }, { .uname = "BUS_LOCKS", .udesc = "Request: number of bus lock and split lock requests", .ucode = 1ULL << (10 + 8), .grpid = 0, .ucntmsk = 0xffull, }, { .uname = "FULL_STRM_ST", .udesc = "Request: number of streaming store requests for full cacheline", .ucode = 1ULL << (11 + 8), .grpid = 0, .ucntmsk = 0xffull, }, { .uname = "SW_PF", .udesc = "Request: number of cacheline requests due to software prefetch", .ucode = 1ULL << (12 + 8), .grpid = 0, .ucntmsk = 0xffull, }, { .uname = "PF_L1_DATA_RD", .udesc = "Request: number of data cacheline reads generated by L1 data prefetcher", .ucode = 1ULL << (13 + 8), .grpid = 0, .ucntmsk = 0xffull, }, { .uname = "PARTIAL_STRM_ST", .udesc = "Request: number of streaming store requests for partial cacheline", .ucode = 1ULL << (14 + 8), .grpid = 0, .ucntmsk = 0xffull, }, { .uname = "STRM_ST", .udesc = "Request: number of streaming store requests for partial or full cacheline", .ucode = (1ULL << (14 + 8)) | (1ULL << (11+8)), .uequiv = "FULL_STRM_ST:PARTIAL_STRM_ST", .grpid = 0, .ucntmsk = 0xffull, }, { .uname = "ANY_REQUEST", .udesc = "Request: combination of all request umasks", .ucode = 1ULL << (15 + 8), .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, .grpid = 0, .ucntmsk = 0xffull, }, { .uname = "ANY_PF_DATA_RD", .udesc = "Request: number of prefetch data reads", .ucode = (1ULL << (4+8)) | (1ULL << (12+8)) | (1ULL << (13+8)), .grpid = 0, .ucntmsk = 0xffull, .uequiv = "PF_DATA_RD:SW_PF:PF_L1_DATA_RD", }, { .uname = "ANY_RFO", .udesc = "Request: number of RFO", .ucode = (1ULL << (1+8)) | (1ULL << (5+8)), .grpid = 0, .ucntmsk = 0xffull, .uequiv = "DMND_RFO:PF_RFO", }, { .uname = "ANY_RESPONSE", .udesc = "Response: any response type", .ucode = 1ULL << (16 + 8), .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL | INTEL_X86_EXCL_GRP_GT, .grpid = 1, .ucntmsk = 0xffull, }, { .uname = "L2_HIT", .udesc = "Supplier: counts L2 hits", .ucode = 1ULL << (18 + 8), .grpid = 1, .ucntmsk = 0xffull, }, { .uname = "L2_MISS_SNP_MISS_OR_NO_SNOOP_NEEDED", .udesc = "Snoop: counts number true misses to this processor module for which a snoop request missed the other processor module or no snoop was needed", .ucode = 1ULL << (33 + 8), .grpid = 2, .ucntmsk = 0xffull, }, { .uname = "L2_MISS_HIT_OTHER_CORE_NO_FWD", .udesc = "Snoop: counts number of times a snoop request hits the other processor module but no data forwarding is needed", .ucode = 1ULL << (34 + 8), .grpid = 2, .ucntmsk = 0xffull, }, { .uname = "L2_MISS_HITM_OTHER_CORE", .udesc = "Snoop: counts number of times a snoop request hits in the other processor module or other core's L1 where a modified copy (M-state) is found", .ucode = 1ULL << (36 + 8), .grpid = 2, .ucntmsk = 0xffull, }, { .uname = "L2_MISS_SNP_NON_DRAM", .udesc = "Snoop: counts number of times target was a non-DRAM system address. This includes MMIO transactions", .ucode = 1ULL << (37 + 8), .grpid = 2, .ucntmsk = 0xffull, }, { .uname = "L2_MISS_SNP_ANY", .udesc = "Snoop: any snoop reason", .ucode = 0xfULL << (33 + 8), .uflags = INTEL_X86_DFL, .grpid = 2, .ucntmsk = 0xffull, .uequiv = "L2_MISS_SNP_MISS_OR_NO_SNOOP_NEEDED:L2_MISS_HIT_OTHER_CORE_NO_FWD:L2_MISS_HITM_OTHER_CORE:L2_MISS_SNP_NON_DRAM", }, }; static const intel_x86_umask_t glm_machine_clears[]={ { .uname = "SMC", .udesc = "Self-Modifying Code detected", .ucode = 0x0100, .uflags = INTEL_X86_NCOMBO, .grpid = 0, .ucntmsk = 0xfull, }, { .uname = "MEMORY_ORDERING", .udesc = "Machine cleas due to memory ordering issue", .ucode = 0x0200, .uflags = INTEL_X86_NCOMBO, .grpid = 0, .ucntmsk = 0xfull, }, { .uname = "FP_ASSIST", .udesc = "Machine clears due to FP assists", .ucode = 0x0400, .uflags = INTEL_X86_NCOMBO, .grpid = 0, .ucntmsk = 0xfull, }, { .uname = "DISAMBIGUATION", .udesc = "Machine clears due to memory disambiguation", .ucode = 0x0800, .uflags = INTEL_X86_NCOMBO, .grpid = 0, .ucntmsk = 0xfull, }, { .uname = "ALL", .udesc = "All machine clears", .ucode = 0x0000, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, .grpid = 0, .ucntmsk = 0xfull, }, }; static const intel_x86_umask_t glm_br_inst_retired[]={ { .uname = "ALL_BRANCHES", .udesc = "Retired branch instructions (Precise Event)", .ucode = 0x0000, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS | INTEL_X86_DFL, .grpid = 0, .ucntmsk = 0xfull, }, { .uname = "ALL_TAKEN_BRANCHES", .udesc = "Retired branch instructions (Precise Event)", .ucode = 0x8000, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, .grpid = 0, .ucntmsk = 0xfull, }, { .uname = "JCC", .udesc = "Retired conditional branch instructions (Precise Event)", .ucode = 0x7e00, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, .grpid = 0, .ucntmsk = 0xfull, }, { .uname = "TAKEN_JCC", .udesc = "Retired conditional branch instructions that were taken (Precise Event)", .ucode = 0xfe00, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, .grpid = 0, .ucntmsk = 0xfull, }, { .uname = "CALL", .udesc = "Retired near call instructions (Precise Event)", .ucode = 0xf900, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, .grpid = 0, .ucntmsk = 0xfull, }, { .uname = "REL_CALL", .udesc = "Retired near relative call instructions (Precise Event)", .ucode = 0xfd00, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, .grpid = 0, .ucntmsk = 0xfull, }, { .uname = "IND_CALL", .udesc = "Retired near indirect call instructions (Precise Event)", .ucode = 0xfb00, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, .grpid = 0, .ucntmsk = 0xfull, }, { .uname = "RETURN", .udesc = "Retired near return instructions (Precise Event)", .ucode = 0xf700, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, .grpid = 0, .ucntmsk = 0xfull, }, { .uname = "NON_RETURN_IND", .udesc = "Retired instructions of near indirect Jmp or call (Precise Event)", .ucode = 0xeb00, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, .grpid = 0, .ucntmsk = 0xfull, }, { .uname = "FAR_BRANCH", .udesc = "Retired far branch instructions (Precise Event)", .ucode = 0xbf00, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, .grpid = 0, .ucntmsk = 0xfull, }, }; static const intel_x86_umask_t glm_fetch_stall[]={ { .uname = "ICACHE_FILL_PENDING_CYCLES", .udesc = "Cycles where code-fetch is stalled and an ICache miss is outstanding. This is not the same as an ICache Miss", .ucode = 0x0200, .uflags = INTEL_X86_DFL, .grpid = 0, .ucntmsk = 0xfull, }, }; static const intel_x86_umask_t glm_uops_not_delivered[]={ { .uname = "ANY", .udesc = "Uops requested but not-delivered to the back-end per cycle", .ucode = 0x0000, .uflags = INTEL_X86_DFL, .grpid = 0, .ucntmsk = 0xfull, }, }; static const intel_x86_umask_t glm_mem_uops_retired[]={ { .uname = "ALL_LOADS", .udesc = "Load uops retired (Precise Event)", .ucode = 0x8100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, .grpid = 0, .ucntmsk = 0xfull, }, { .uname = "ALL_STORES", .udesc = "Store uops retired (Precise Event)", .ucode = 0x8200, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, .grpid = 0, .ucntmsk = 0xfull, }, { .uname = "ALL", .udesc = "Memory uops retired (Precise Event)", .ucode = 0x8300, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, .grpid = 0, .ucntmsk = 0xfull, }, { .uname = "DTLB_MISS_LOADS", .udesc = "Load uops retired that missed the DTLB (Precise Event)", .ucode = 0x1100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, .grpid = 0, .ucntmsk = 0xfull, }, { .uname = "DTLB_MISS_STORES", .udesc = "Store uops retired that missed the DTLB (Precise Event)", .ucode = 0x1200, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, .grpid = 0, .ucntmsk = 0xfull, }, { .uname = "DTLB_MISS", .udesc = "Memory uops retired that missed the DTLB (Precise Event)", .ucode = 0x1300, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, .grpid = 0, .ucntmsk = 0xfull, }, { .uname = "LOCK_LOADS", .udesc = "Locked load uops retired (Precise Event)", .ucode = 0x2100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, .grpid = 0, .ucntmsk = 0xfull, }, { .uname = "SPLIT_LOADS", .udesc = "Load uops retired that split a cache-line (Precise Event)", .ucode = 0x4100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, .grpid = 0, .ucntmsk = 0xfull, }, { .uname = "SPLIT_STORES", .udesc = "Stores uops retired that split a cache-line (Precise Event)", .ucode = 0x4200, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, .grpid = 0, .ucntmsk = 0xfull, }, { .uname = "SPLIT", .udesc = "Memory uops retired that split a cache-line (Precise Event)", .ucode = 0x4300, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, .grpid = 0, .ucntmsk = 0xfull, }, }; static const intel_x86_umask_t glm_uops_issued[]={ { .uname = "ANY", .udesc = "Uops issued to the back end per cycle", .ucode = 0x0000, .uflags = INTEL_X86_DFL, .grpid = 0, .ucntmsk = 0xfull, }, }; static const intel_x86_umask_t glm_core_reject_l2q[]={ { .uname = "ALL", .udesc = "Requests rejected by the L2Q ", .ucode = 0x0000, .uflags = INTEL_X86_DFL, .grpid = 0, .ucntmsk = 0xfull, }, }; static const intel_x86_umask_t glm_page_walks[]={ { .uname = "D_SIDE_CYCLES", .udesc = "Duration of D-side page-walks in cycles", .ucode = 0x0100, .uflags = INTEL_X86_NCOMBO, .grpid = 0, .ucntmsk = 0xfull, }, { .uname = "I_SIDE_CYCLES", .udesc = "Duration of I-side pagewalks in cycles", .ucode = 0x0200, .uflags = INTEL_X86_NCOMBO, .grpid = 0, .ucntmsk = 0xfull, }, { .uname = "CYCLES", .udesc = "Duration of page-walks in cycles", .ucode = 0x0300, .uflags = INTEL_X86_NCOMBO, .grpid = 0, .ucntmsk = 0xfull, }, }; static const intel_x86_umask_t glm_baclears[]={ { .uname = "ALL", .udesc = "BACLEARs asserted for any branch type", .ucode = 0x0100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, .grpid = 0, .ucntmsk = 0xfull, }, { .uname = "RETURN", .udesc = "BACLEARs asserted for return branch", .ucode = 0x0800, .uflags = INTEL_X86_NCOMBO, .grpid = 0, .ucntmsk = 0xfull, }, { .uname = "COND", .udesc = "BACLEARs asserted for conditional branch", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, .grpid = 0, .ucntmsk = 0xfull, }, }; static const intel_x86_umask_t glm_cpu_clk_unhalted[]={ { .uname = "CORE", .udesc = "Core cycles when core is not halted (Fixed event)", .ucode = 0x0200, .uflags = INTEL_X86_NCOMBO, .grpid = 0, .ucntmsk = 0x200000000ull, }, { .uname = "REF_TSC", .udesc = "Reference cycles when core is not halted (Fixed event)", .ucode = 0x0300, .uflags = INTEL_X86_NCOMBO, .grpid = 0, .ucntmsk = 0x400000000ull, }, { .uname = "CORE_P", .udesc = "Core cycles when core is not halted", .ucode = 0x0000, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, .grpid = 0, .ucntmsk = 0xfull, }, { .uname = "REF", .udesc = "Reference cycles when core is not halted", .ucode = 0x0100, .uflags = INTEL_X86_NCOMBO, .grpid = 0, .ucntmsk = 0xfull, }, }; static const intel_x86_entry_t intel_glm_pe[]={ { .name = "ICACHE", .desc = "References per ICache line that are available in the ICache (hit). This event counts differently than Intel processors based on Silvermont microarchitecture", .code = 0x80, .modmsk = INTEL_V2_ATTRS, .cntmsk = 0xfull, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(glm_icache), .umasks = glm_icache, }, { .name = "L2_REJECT_XQ", .desc = "Requests rejected by the XQ", .code = 0x30, .modmsk = INTEL_V2_ATTRS, .cntmsk = 0xfull, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(glm_l2_reject_xq), .umasks = glm_l2_reject_xq, }, { .name = "HW_INTERRUPTS", .desc = "Hardware interrupts received", .code = 0xcb, .modmsk = INTEL_V2_ATTRS, .cntmsk = 0xfull, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(glm_hw_interrupts), .umasks = glm_hw_interrupts, }, { .name = "BR_MISP_RETIRED", .desc = "Retired mispredicted branch instructions (Precise Event)", .code = 0xc5, .modmsk = INTEL_V2_ATTRS, .cntmsk = 0xfull, .flags = INTEL_X86_PEBS, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(glm_br_misp_retired), .umasks = glm_br_misp_retired, }, { .name = "DECODE_RESTRICTION", .desc = "Decode restrictions due to predicting wrong instruction length", .code = 0xe9, .modmsk = INTEL_V2_ATTRS, .cntmsk = 0xfull, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(glm_decode_restriction), .umasks = glm_decode_restriction, }, { .name = "MISALIGN_MEM_REF", .desc = "Load uops that split a page (Precise Event)", .code = 0x13, .modmsk = INTEL_V2_ATTRS, .cntmsk = 0xfull, .flags = INTEL_X86_PEBS, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(glm_misalign_mem_ref), .umasks = glm_misalign_mem_ref, }, { .name = "INST_RETIRED", .desc = "Instructions retired (Precise Event)", .code = 0xc0, .modmsk = INTEL_V2_ATTRS, .cntmsk = 0x10000000full, .flags = INTEL_X86_PEBS, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(glm_inst_retired), .umasks = glm_inst_retired, }, { .name = "INSTRUCTION_RETIRED", .desc = "Number of instructions retired", .code = 0xc0, .modmsk = INTEL_V2_ATTRS, .cntmsk = 0x100000ffull, .ngrp = 0, }, { .name = "ISSUE_SLOTS_NOT_CONSUMED", .desc = "Unfilled issue slots per cycle because of a full resource in the backend", .code = 0xca, .modmsk = INTEL_V2_ATTRS, .cntmsk = 0xfull, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(glm_issue_slots_not_consumed), .umasks = glm_issue_slots_not_consumed, }, { .name = "ITLB", .desc = "ITLB misses", .code = 0x81, .modmsk = INTEL_V2_ATTRS, .cntmsk = 0xfull, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(glm_itlb), .umasks = glm_itlb, }, { .name = "LONGEST_LAT_CACHE", .desc = "L2 cache requests", .code = 0x2e, .modmsk = INTEL_V2_ATTRS, .cntmsk = 0xfull, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(glm_longest_lat_cache), .umasks = glm_longest_lat_cache, }, { .name = "MEM_LOAD_UOPS_RETIRED", .desc = "Load uops retired that hit L1 data cache (Precise Event)", .code = 0xd1, .modmsk = INTEL_V2_ATTRS, .cntmsk = 0xfull, .flags = INTEL_X86_PEBS, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(glm_mem_load_uops_retired), .umasks = glm_mem_load_uops_retired, }, { .name = "LD_BLOCKS", .desc = "Loads blocked (Precise Event)", .code = 0x03, .modmsk = INTEL_V2_ATTRS, .cntmsk = 0xfull, .flags = INTEL_X86_PEBS, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(glm_ld_blocks), .umasks = glm_ld_blocks, }, { .name = "DL1", .desc = "L1 Cache evictions for dirty data", .code = 0x51, .modmsk = INTEL_V2_ATTRS, .cntmsk = 0xfull, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(glm_dl1), .umasks = glm_dl1, }, { .name = "CYCLES_DIV_BUSY", .desc = "Cycles a divider is busy", .code = 0xcd, .modmsk = INTEL_V2_ATTRS, .cntmsk = 0xfull, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(glm_cycles_div_busy), .umasks = glm_cycles_div_busy, }, { .name = "MS_DECODED", .desc = "MS decode starts", .code = 0xe7, .modmsk = INTEL_V2_ATTRS, .cntmsk = 0xfull, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(glm_ms_decoded), .umasks = glm_ms_decoded, }, { .name = "UOPS_RETIRED", .desc = "Uops retired (Precise Event)", .code = 0xc2, .modmsk = INTEL_V2_ATTRS, .cntmsk = 0xfull, .flags = INTEL_X86_PEBS, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(glm_uops_retired), .umasks = glm_uops_retired, }, { .name = "OFFCORE_RESPONSE_1", .desc = "Offcore response event (must provide at least one request type and either any_response or any combination of supplier + snoop)", .code = 0x2b7, .modmsk = INTEL_V2_ATTRS, .cntmsk = 0xffull, .flags = INTEL_X86_NHM_OFFCORE, .ngrp = 3, .numasks = LIBPFM_ARRAY_SIZE(glm_offcore_response_1), .umasks = glm_offcore_response_1, }, { .name = "MACHINE_CLEARS", .desc = "Self-Modifying Code detected", .code = 0xc3, .modmsk = INTEL_V2_ATTRS, .cntmsk = 0xfull, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(glm_machine_clears), .umasks = glm_machine_clears, }, { .name = "BR_INST_RETIRED", .desc = "Retired branch instructions (Precise Event)", .code = 0xc4, .modmsk = INTEL_V2_ATTRS, .cntmsk = 0xfull, .flags = INTEL_X86_PEBS, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(glm_br_inst_retired), .umasks = glm_br_inst_retired, }, { .name = "FETCH_STALL", .desc = "Cycles where code-fetch is stalled and an ICache miss is outstanding. This is not the same as an ICache Miss", .code = 0x86, .modmsk = INTEL_V2_ATTRS, .cntmsk = 0xfull, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(glm_fetch_stall), .umasks = glm_fetch_stall, }, { .name = "UOPS_NOT_DELIVERED", .desc = "Uops requested but not-delivered to the back-end per cycle", .code = 0x9c, .modmsk = INTEL_V2_ATTRS, .cntmsk = 0xfull, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(glm_uops_not_delivered), .umasks = glm_uops_not_delivered, }, { .name = "MISPREDICTED_BRANCH_RETIRED", .desc = "Number of mispredicted branch instructions retired", .code = 0xc5, .modmsk = INTEL_V2_ATTRS, .cntmsk = 0xffull, .equiv = "BR_MISP_RETIRED:ALL_BRANCHES", .ngrp = 0, }, { .name = "INSTRUCTIONS_RETIRED", .desc = "Number of instructions retired", .code = 0xc0, .modmsk = INTEL_V2_ATTRS, .cntmsk = 0x100000ffull, .equiv = "INSTRUCTION_RETIRED", .ngrp = 0, }, { .name = "MEM_UOPS_RETIRED", .desc = "Load uops retired (Precise Event)", .code = 0xd0, .modmsk = INTEL_V2_ATTRS, .cntmsk = 0xfull, .flags = INTEL_X86_PEBS, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(glm_mem_uops_retired), .umasks = glm_mem_uops_retired, }, { .name = "UOPS_ISSUED", .desc = "Uops issued to the back end per cycle", .code = 0x0e, .modmsk = INTEL_V2_ATTRS, .cntmsk = 0xfull, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(glm_uops_issued), .umasks = glm_uops_issued, }, { .name = "OFFCORE_RESPONSE_0", .desc = "Offcore response event (must provide at least one request type and either any_response or any combination of supplier + snoop)", .code = 0x1b7, .modmsk = INTEL_V2_ATTRS, .cntmsk = 0xffull, .flags = INTEL_X86_NHM_OFFCORE, .ngrp = 4, .numasks = LIBPFM_ARRAY_SIZE(glm_offcore_response_0), .umasks = glm_offcore_response_0, }, { .name = "UNHALTED_REFERENCE_CYCLES", .desc = "Unhalted reference cycles. Ticks at constant reference frequency", .code = 0x0300, .modmsk = INTEL_FIXED2_ATTRS, .cntmsk = 0x40000000ull, .flags = INTEL_X86_FIXED, .ngrp = 0, }, { .name = "BRANCH_INSTRUCTIONS_RETIRED", .desc = "Number of branch instructions retired", .code = 0xc4, .modmsk = INTEL_V2_ATTRS, .cntmsk = 0xffull, .equiv = "BR_INST_RETIRED:ALL_BRANCHES", .ngrp = 0, }, { .name = "CORE_REJECT_L2Q", .desc = "Requests rejected by the L2Q ", .code = 0x31, .modmsk = INTEL_V2_ATTRS, .cntmsk = 0xfull, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(glm_core_reject_l2q), .umasks = glm_core_reject_l2q, }, { .name = "PAGE_WALKS", .desc = "Duration of D-side page-walks in cycles", .code = 0x05, .modmsk = INTEL_V2_ATTRS, .cntmsk = 0xfull, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(glm_page_walks), .umasks = glm_page_walks, }, { .name = "BACLEARS", .desc = "BACLEARs asserted for any branch type", .code = 0xe6, .modmsk = INTEL_V2_ATTRS, .cntmsk = 0xfull, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(glm_baclears), .umasks = glm_baclears, }, { .name = "CPU_CLK_UNHALTED", .desc = "Core cycles when core is not halted (Fixed event)", .code = 0x00, .modmsk = INTEL_V2_ATTRS, .cntmsk = 0x60000000full, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(glm_cpu_clk_unhalted), .umasks = glm_cpu_clk_unhalted, }, { .name = "UNHALTED_CORE_CYCLES", .desc = "Core clock cycles whenever the clock signal on the specific core is running (not halted)", .code = 0x3c, .modmsk = INTEL_V2_ATTRS, .cntmsk = 0x20000000ull, .ngrp = 0, }, }; libpfm-4.9.0/lib/events/intel_ivbep_unc_cbo_events.h0000664000175000017500000007363013223402656022426 0ustar eranianeranian/* * Copyright (c) 2014 Google Inc. All rights reserved * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * PMU: ivbep_unc_cbo (Intel IvyBridge-EP C-Box uncore PMU) */ #define CBO_FILT_MESIF(a, b, c, d) \ { .uname = "STATE_"#a,\ .udesc = #b" cacheline state",\ .ufilters[0] = 1ULL << (17 + (c)),\ .grpid = d, \ } #define CBO_FILT_MESIFS(d) \ CBO_FILT_MESIF(I, Invalid, 0, d), \ CBO_FILT_MESIF(S, Shared, 1, d), \ CBO_FILT_MESIF(E, Exclusive, 2, d), \ CBO_FILT_MESIF(M, Modified, 3, d), \ CBO_FILT_MESIF(F, Forward, 4, d), \ { .uname = "STATE_MESIF",\ .udesc = "Any cache line state",\ .ufilters[0] = 0x3fULL << 17,\ .grpid = d, \ .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, \ } #define CBO_FILT_OPC(d) \ { .uname = "OPC_RFO",\ .udesc = "Demand data RFO (combine with any OPCODE umask)",\ .ufilters[1] = 0x180ULL << 20, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_CRD",\ .udesc = "Demand code read (combine with any OPCODE umask)",\ .ufilters[1] = 0x181ULL << 20, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_DRD",\ .udesc = "Demand data read (combine with any OPCODE umask)",\ .ufilters[1] = 0x182ULL << 20, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_PRD",\ .udesc = "Partial reads (UC) (combine with any OPCODE umask)",\ .ufilters[1] = 0x187ULL << 20, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_WCILF",\ .udesc = "Full Stream store (combine with any OPCODE umask)", \ .ufilters[1] = 0x18cULL << 20, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_WCIL",\ .udesc = "Partial Stream store (combine with any OPCODE umask)", \ .ufilters[1] = 0x18dULL << 20, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_PF_RFO",\ .udesc = "Prefetch RFO into LLC but do not pass to L2 (includes hints) (combine with any OPCODE umask)", \ .ufilters[1] = 0x190ULL << 20, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_PF_CODE",\ .udesc = "Prefetch code into LLC but do not pass to L2 (includes hints) (combine with any OPCODE umask)", \ .ufilters[1] = 0x191ULL << 20, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_PF_DATA",\ .udesc = "Prefetch data into LLC but do not pass to L2 (includes hints) (combine with any OPCODE umask)", \ .ufilters[1] = 0x192ULL << 20, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_PCIWILF",\ .udesc = "PCIe write (non-allocating) (combine with any OPCODE umask)", \ .ufilters[1] = 0x194ULL << 20, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_PCIPRD",\ .udesc = "PCIe UC read (combine with any OPCODE umask)", \ .ufilters[1] = 0x195ULL << 20, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_PCIITOM",\ .udesc = "PCIe write (allocating) (combine with any OPCODE umask)", \ .ufilters[1] = 0x19cULL << 20, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_PCIRDCUR",\ .udesc = "PCIe read current (combine with any OPCODE umask)", \ .ufilters[1] = 0x19eULL << 20, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_WBMTOI",\ .udesc = "Request writeback modified invalidate line (combine with any OPCODE umask)", \ .ufilters[1] = 0x1c4ULL << 20, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_WBMTOE",\ .udesc = "Request writeback modified set to exclusive (combine with any OPCODE umask)", \ .ufilters[1] = 0x1c5ULL << 20, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_ITOM",\ .udesc = "Request invalidate line (combine with any OPCODE umask)", \ .ufilters[1] = 0x1c8ULL << 20, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_PCINSRD",\ .udesc = "PCIe non-snoop read (combine with any OPCODE umask)", \ .ufilters[1] = 0x1e4ULL << 20, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_PCINSWR",\ .udesc = "PCIe non-snoop write (partial) (combine with any OPCODE umask)", \ .ufilters[1] = 0x1e5ULL << 20, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ }, \ { .uname = "OPC_PCINSWRF",\ .udesc = "PCIe non-snoop write (full) (combine with any OPCODE umask)", \ .ufilters[1] = 0x1e6ULL << 20, \ .uflags = INTEL_X86_NCOMBO, \ .grpid = d, \ } static const intel_x86_umask_t ivbep_unc_c_llc_lookup[]={ { .uname = "DATA_READ", .udesc = "Data read requests", .grpid = 0, .ucode = 0x300, .uflags = INTEL_X86_NCOMBO, }, { .uname = "WRITE", .udesc = "Write requests. Includes all write transactions (cached, uncached)", .grpid = 0, .ucode = 0x500, .uflags = INTEL_X86_NCOMBO, }, { .uname = "REMOTE_SNOOP", .udesc = "External snoop request", .grpid = 0, .ucode = 0x900, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ANY", .udesc = "Any request", .grpid = 0, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, .ucode = 0x1100, }, { .uname = "NID", .udesc = "Match a given RTID destination NID (must provide nf=X modifier)", .umodmsk_req = _SNBEP_UNC_ATTR_NF1, .grpid = 1, .ucode = 0x4100, .uflags = INTEL_X86_GRP_DFL_NONE }, CBO_FILT_MESIFS(2), }; static const intel_x86_umask_t ivbep_unc_c_llc_victims[]={ { .uname = "STATE_M", .udesc = "Lines in M state", .ucode = 0x100, .grpid = 0, }, { .uname = "STATE_E", .udesc = "Lines in E state", .ucode = 0x200, .grpid = 0, }, { .uname = "STATE_S", .udesc = "Lines in S state", .ucode = 0x400, .grpid = 0, }, { .uname = "MISS", .udesc = "TBD", .ucode = 0x800, .grpid = 0, }, { .uname = "NID", .udesc = "Victimized Lines matching the NID filter (must provide nf=X modifier)", .ucode = 0x4000, .uflags = INTEL_X86_GRP_DFL_NONE, .umodmsk_req = _SNBEP_UNC_ATTR_NF1, .grpid = 1, }, }; static const intel_x86_umask_t ivbep_unc_c_ring_ad_used[]={ { .uname = "UP_VR0_EVEN", .udesc = "Up and Even ring polarity filter on virtual ring 0", .ucode = 0x100, }, { .uname = "UP_VR0_ODD", .udesc = "Up and odd ring polarity filter on virtual ring 0", .ucode = 0x200, }, { .uname = "DOWN_VR0_EVEN", .udesc = "Down and even ring polarity filter on virtual ring 0", .ucode = 0x400, }, { .uname = "DOWN_VR0_ODD", .udesc = "Down and odd ring polarity filter on virtual ring 0", .ucode = 0x800, }, { .uname = "UP_VR1_EVEN", .udesc = "Up and Even ring polarity filter on virtual ring 1", .ucode = 0x1000, }, { .uname = "UP_VR1_ODD", .udesc = "Up and odd ring polarity filter on virtual ring 1", .ucode = 0x2000, }, { .uname = "DOWN_VR1_EVEN", .udesc = "Down and even ring polarity filter on virtual ring 1", .ucode = 0x4000, }, { .uname = "DOWN_VR1_ODD", .udesc = "Down and odd ring polarity filter on virtual ring 1", .ucode = 0x8000, }, { .uname = "UP", .udesc = "Up on any virtual ring", .ucode = 0x3300, }, { .uname = "DOWN", .udesc = "Down any virtual ring", .ucode = 0xcc00, }, }; static const intel_x86_umask_t ivbep_unc_c_ring_bounces[]={ { .uname = "AD_IRQ", .udesc = "TBD", .ucode = 0x200, }, { .uname = "AK", .udesc = "Acknowledgments to core", .ucode = 0x400, }, { .uname = "BL", .udesc = "Data responses to core", .ucode = 0x800, }, { .uname = "IV", .udesc = "Snoops of processor cache", .ucode = 0x1000, }, }; static const intel_x86_umask_t ivbep_unc_c_ring_iv_used[]={ { .uname = "ANY", .udesc = "Any filter", .ucode = 0xf00, .uflags = INTEL_X86_DFL, }, { .uname = "UP", .udesc = "Filter on any up polarity", .ucode = 0x3300, }, { .uname = "DOWN", .udesc = "Filter on any down polarity", .ucode = 0xcc00, }, }; static const intel_x86_umask_t ivbep_unc_c_rxr_ext_starved[]={ { .uname = "IRQ", .udesc = "Irq externally starved, therefore blocking the IPQ", .ucode = 0x100, }, { .uname = "IPQ", .udesc = "IPQ externally starved, therefore blocking the IRQ", .ucode = 0x200, }, { .uname = "PRQ", .udesc = "IRQ is blocking the ingress queue and causing starvation", .ucode = 0x400, }, { .uname = "ISMQ_BIDS", .udesc = "Number of time the ISMQ bids", .ucode = 0x800, }, }; static const intel_x86_umask_t ivbep_unc_c_rxr_inserts[]={ { .uname = "IPQ", .udesc = "IPQ", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "IRQ", .udesc = "IRQ", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "IRQ_REJECTED", .udesc = "IRQ rejected", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "VFIFO", .udesc = "Counts the number of allocated into the IRQ ordering FIFO", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t ivbep_unc_c_rxr_ipq_retry[]={ { .uname = "ADDR_CONFLICT", .udesc = "Address conflict", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ANY", .udesc = "Any Reject", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "FULL", .udesc = "No Egress credits", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "QPI_CREDITS", .udesc = "No QPI credits", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t ivbep_unc_c_rxr_irq_retry[]={ { .uname = "ADDR_CONFLICT", .udesc = "Address conflict", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ANY", .udesc = "Any reject", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "FULL", .udesc = "No Egress credits", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "QPI_CREDITS", .udesc = "No QPI credits", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "RTID", .udesc = "No RTIDs", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "IIO_CREDITS", .udesc = "No IIO Credits", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t ivbep_unc_c_rxr_ismq_retry[]={ { .uname = "ANY", .udesc = "Any reject", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "FULL", .udesc = "No Egress credits", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "IIO_CREDITS", .udesc = "No IIO credits", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "QPI_CREDITS", .udesc = "NO QPI credits", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "RTID", .udesc = "No RTIDs", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "WB_CREDITS", .udesc = "No WB credits", .ucode = 0x8000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t ivbep_unc_c_tor_inserts[]={ { .uname = "OPCODE", .udesc = "Number of transactions inserted into the TOR that match an opcode (must provide opc_* umask)", .ucode = 0x100, .grpid = 0, .uflags = INTEL_X86_NCOMBO, }, { .uname = "MISS_OPCODE", .udesc = "Number of miss transactions inserted into the TOR that match an opcode (must provide opc_* umask)", .ucode = 0x300, .grpid = 0, .uflags = INTEL_X86_NCOMBO, }, { .uname = "EVICTION", .udesc = "Number of Evictions transactions inserted into TOR", .ucode = 0x400, .grpid = 0, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, }, { .uname = "ALL", .udesc = "Number of transactions inserted in TOR", .ucode = 0x800, .grpid = 0, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL | INTEL_X86_EXCL_GRP_GT, }, { .uname = "WB", .udesc = "Number of write transactions inserted into the TOR", .ucode = 0x1000, .grpid = 0, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, }, { .uname = "LOCAL_OPCODE", .udesc = "Number of opcode-matched transactions inserted into the TOR that are satisfied by locally homed memory", .ucode = 0x2100, .grpid = 0, .uflags = INTEL_X86_NCOMBO, }, { .uname = "MISS_LOCAL_OPCODE", .udesc = "Number of miss opcode-matched transactions inserted into the TOR that are satisfied by locally homed memory", .ucode = 0x2300, .grpid = 0, .uflags = INTEL_X86_NCOMBO, }, { .uname = "LOCAL", .udesc = "Number of transactions inserted into the TOR that are satisfied by locally homed memory", .ucode = 0x2800, .grpid = 0, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, }, { .uname = "MISS_LOCAL", .udesc = "Number of miss transactions inserted into the TOR that are satisfied by locally homed memory", .ucode = 0x2a00, .grpid = 0, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, }, { .uname = "NID_OPCODE", .udesc = "Number of transactions inserted into the TOR that match a NID and opcode (must provide opc_* umask and nf=X modifier)", .ucode = 0x4100, .grpid = 0, .umodmsk_req = _SNBEP_UNC_ATTR_NF1, .uflags = INTEL_X86_NCOMBO, }, { .uname = "NID_MISS_OPCODE", .udesc = "Number of NID and opcode matched miss transactions inserted into the TOR (must provide opc_* umask and nf=X modifier)", .ucode = 0x4300, .grpid = 0, .umodmsk_req = _SNBEP_UNC_ATTR_NF1, .uflags = INTEL_X86_NCOMBO, }, { .uname = "NID_EVICTION", .udesc = "Number of NID-matched eviction transactions inserted into the TOR (must provide nf=X modifier)", .ucode = 0x4400, .grpid = 0, .umodmsk_req = _SNBEP_UNC_ATTR_NF1, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, }, { .uname = "NID_ALL", .udesc = "Number of NID-matched transactions inserted into the TOR (must provide nf=X modifier)", .ucode = 0x4800, .grpid = 0, .umodmsk_req = _SNBEP_UNC_ATTR_NF1, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, }, { .uname = "NID_MISS_ALL", .udesc = "Number of NID-matched miss transactions that were inserted into the TOR (must provide nf=X modifier)", .ucode = 0x4a00, .grpid = 0, .umodmsk_req = _SNBEP_UNC_ATTR_NF1, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, }, { .uname = "NID_WB", .udesc = "Number of NID-matched write back transactions inserted into the TOR (must provide nf=X modifier)", .ucode = 0x5000, .grpid = 0, .umodmsk_req = _SNBEP_UNC_ATTR_NF1, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, }, { .uname = "REMOTE_OPCODE", .udesc = "Number of opcode-matched transactions inserted into the TOR that are satisfied by remote caches or memory", .ucode = 0x8100, .grpid = 0, .uflags = INTEL_X86_NCOMBO, }, { .uname = "MISS_REMOTE_OPCODE", .udesc = "Number of miss opcode-matched transactions inserted into the TOR that are satisfied by remote caches or memory", .ucode = 0x8300, .grpid = 0, .uflags = INTEL_X86_NCOMBO, }, { .uname = "REMOTE", .udesc = "Number of transactions inserted into the TOR that are satisfied by remote caches or memory", .ucode = 0x8800, .grpid = 0, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, }, { .uname = "MISS_REMOTE", .udesc = "Number of miss transactions inserted into the TOR that are satisfied by remote caches or memory", .ucode = 0x8a00, .grpid = 0, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, }, CBO_FILT_OPC(1) }; static const intel_x86_umask_t ivbep_unc_c_tor_occupancy[]={ { .uname = "OPCODE", .udesc = "Number of TOR entries that match an opcode (must provide opc_* umask)", .ucode = 0x100, .grpid = 0, .uflags = INTEL_X86_NCOMBO, }, { .uname = "MISS_OPCODE", .udesc = "Number of TOR entries that match a NID and an opcode (must provide opc_* umask)", .ucode = 0x300, .grpid = 0, .uflags = INTEL_X86_NCOMBO, }, { .uname = "EVICTION", .udesc = "Number of outstanding eviction transactions in the TOR", .ucode = 0x400, .grpid = 0, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, }, { .uname = "ALL", .udesc = "All valid TOR entries", .ucode = 0x800, .grpid = 0, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL | INTEL_X86_EXCL_GRP_GT, }, { .uname = "MISS_ALL", .udesc = "Number of outstanding miss requests in the TOR", .ucode = 0xa00, .grpid = 0, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, }, { .uname = "WB", .udesc = "Number of write transactions in the TOR. Does not include RFO, but actual operations that contain data being sent from the core", .ucode = 0x1000, .grpid = 0, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, }, { .uname = "LOCAL_OPCODE", .udesc = "Number of opcode-matched transactions in the TOR that are satisfied by locally homed memory", .ucode = 0x2100, .grpid = 0, .uflags = INTEL_X86_NCOMBO, }, { .uname = "MISS_LOCAL_OPCODE", .udesc = "Number of miss opcode-matched transactions in the TOR that are satisfied by locally homed memory", .ucode = 0x2300, .grpid = 0, .uflags = INTEL_X86_NCOMBO, }, { .uname = "LOCAL", .udesc = "Number of transactions in the TOR that are satisfied by locally homed memory", .ucode = 0x2800, .grpid = 0, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, }, { .uname = "MISS_LOCAL", .udesc = "Number of miss transactions in the TOR that are satisfied by locally homed memory", .ucode = 0x2a00, .grpid = 0, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, }, { .uname = "NID_OPCODE", .udesc = "Number of NID-matched TOR entries that an opcode (must provide nf=X modifier and opc_* umask)", .ucode = 0x4100, .grpid = 0, .umodmsk_req = _SNBEP_UNC_ATTR_NF1, .uflags = INTEL_X86_NCOMBO, }, { .uname = "NID_MISS_OPCODE", .udesc = "Number of NID-matched outstanding miss requests in the TOR that an opcode (must provide nf=X modifier and opc_* umask)", .ucode = 0x4300, .grpid = 0, .umodmsk_req = _SNBEP_UNC_ATTR_NF1, .uflags = INTEL_X86_NCOMBO, }, { .uname = "NID_EVICTION", .udesc = "Number of NID-matched outstanding requests in the TOR (must provide a nf=X modifier)", .ucode = 0x4400, .grpid = 0, .umodmsk_req = _SNBEP_UNC_ATTR_NF1, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, }, { .uname = "NID_ALL", .udesc = "Number of NID-matched outstanding requests in the TOR (must provide nf=X modifier)", .ucode = 0x4800, .grpid = 0, .umodmsk_req = _SNBEP_UNC_ATTR_NF1, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, }, { .uname = "NID_MISS_ALL", .udesc = "Number of NID-matched outstanding miss requests in the TOR (must provide a nf=X modifier)", .ucode = 0x4a00, .grpid = 0, .umodmsk_req = _SNBEP_UNC_ATTR_NF1, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, }, { .uname = "NID_WB", .udesc = "Number of NID-matched write transactions in the TOR (must provide a nf=X modifier)", .ucode = 0x5000, .grpid = 0, .umodmsk_req = _SNBEP_UNC_ATTR_NF1, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, }, { .uname = "REMOTE_OPCODE", .udesc = "Number of opcode-matched transactions in the TOR that are satisfied by remote caches or memory", .ucode = 0x8100, .grpid = 0, .uflags = INTEL_X86_NCOMBO, }, { .uname = "MISS_REMOTE_OPCODE", .udesc = "Number of miss opcode-matched transactions in the TOR that are satisfied by remote caches or memory", .ucode = 0x8300, .grpid = 0, .uflags = INTEL_X86_NCOMBO, }, { .uname = "REMOTE", .udesc = "Number of transactions in the TOR that are satisfied by remote caches or memory", .ucode = 0x8800, .grpid = 0, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, }, { .uname = "MISS_REMOTE", .udesc = "Number of miss transactions inserted into the TOR that are satisfied by remote caches or memory", .ucode = 0x8a00, .grpid = 0, .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, }, CBO_FILT_OPC(1) }; static const intel_x86_umask_t ivbep_unc_c_txr_inserts[]={ { .uname = "AD_CACHE", .udesc = "Counts the number of ring transactions from Cachebo to AD ring", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "AK_CACHE", .udesc = "Counts the number of ring transactions from Cachebo to AK ring", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "BL_CACHE", .udesc = "Counts the number of ring transactions from Cachebo to BL ring", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "IV_CACHE", .udesc = "Counts the number of ring transactions from Cachebo ton IV ring", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "AD_CORE", .udesc = "Counts the number of ring transactions from Corebo to AD ring", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "AK_CORE", .udesc = "Counts the number of ring transactions from Corebo to AK ring", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "BL_CORE", .udesc = "Counts the number of ring transactions from Corebo to BL ring", .ucode = 0x4000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t ivbep_unc_c_txr_ads_used[]={ { .uname = "AD", .udesc = "onto AD ring", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "AK", .udesc = "Onto AK ring", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "BL", .udesc = "Onto BL ring", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, } }; static const intel_x86_umask_t ivbep_unc_c_misc[]={ { .uname = "RSPI_WAS_FSE", .udesc = "Counts the number of times when a SNoop hit in FSE states and triggered a silent eviction. This is useful because this information is lost in the PRE encodings", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "WC_ALIASING", .udesc = "Counts the number of times a USWC write (WCIL(F)) transaction hits in the LLC in M state, triggering a WBMTOI followed by the USWC write. This occurs when there is WC aliasing", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "STARTED", .udesc = "TBD", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "RFO_HIT_S", .udesc = "Counts the number of times that an RFO hits in S state. This is useful for determining if it might be good for a workload to use RSPIWB instead of RSPSWB", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_entry_t intel_ivbep_unc_c_pe[]={ { .name = "UNC_C_CLOCKTICKS", .desc = "C-box Uncore clockticks", .modmsk = 0x0, .cntmsk = 0xf, .code = 0x00, .flags = INTEL_X86_FIXED, }, { .name = "UNC_C_COUNTER0_OCCUPANCY", .desc = "Counter 0 occupancy. Counts the occupancy related information by filtering CB0 occupancy count captured in counter 0.", .modmsk = IVBEP_UNC_CBO_ATTRS, .cntmsk = 0xe, .code = 0x1f, }, { .name = "UNC_C_LLC_LOOKUP", .desc = "Cache lookups", .modmsk = IVBEP_UNC_CBO_NID_ATTRS, .cntmsk = 0x3, .code = 0x34, .ngrp = 3, .flags = INTEL_X86_NO_AUTOENCODE, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_c_llc_lookup), .umasks = ivbep_unc_c_llc_lookup, }, { .name = "UNC_C_LLC_VICTIMS", .desc = "Lines victimized", .modmsk = IVBEP_UNC_CBO_NID_ATTRS, .cntmsk = 0x3, .code = 0x37, .flags = INTEL_X86_NO_AUTOENCODE, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_c_llc_victims), .ngrp = 2, .umasks = ivbep_unc_c_llc_victims, }, { .name = "UNC_C_MISC", .desc = "Miscellaneous C-Box events", .modmsk = IVBEP_UNC_CBO_ATTRS, .cntmsk = 0x3, .code = 0x39, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_c_misc), .ngrp = 1, .umasks = ivbep_unc_c_misc, }, { .name = "UNC_C_RING_AD_USED", .desc = "Address ring in use. Counts number of cycles ring is being used at this ring stop", .modmsk = IVBEP_UNC_CBO_ATTRS, .cntmsk = 0xc, .code = 0x1b, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_c_ring_ad_used), .ngrp = 1, .umasks = ivbep_unc_c_ring_ad_used, }, { .name = "UNC_C_RING_AK_USED", .desc = "Acknowledgement ring in use. Counts number of cycles ring is being used at this ring stop", .modmsk = IVBEP_UNC_CBO_ATTRS, .cntmsk = 0xc, .code = 0x1c, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_c_ring_ad_used), /* identical to RING_AD_USED */ .ngrp = 1, .umasks = ivbep_unc_c_ring_ad_used, }, { .name = "UNC_C_RING_BL_USED", .desc = "Bus or Data ring in use. Counts number of cycles ring is being used at this ring stop", .modmsk = IVBEP_UNC_CBO_ATTRS, .cntmsk = 0xc, .code = 0x1d, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_c_ring_ad_used), /* identical to RING_AD_USED */ .ngrp = 1, .umasks = ivbep_unc_c_ring_ad_used, }, { .name = "UNC_C_RING_BOUNCES", .desc = "Number of LLC responses that bounced in the ring", .modmsk = IVBEP_UNC_CBO_ATTRS, .cntmsk = 0x3, .code = 0x05, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_c_ring_bounces), .ngrp = 1, .umasks = ivbep_unc_c_ring_bounces, }, { .name = "UNC_C_RING_IV_USED", .desc = "Invalidate ring in use. Counts number of cycles ring is being used at this ring stop", .modmsk = IVBEP_UNC_CBO_ATTRS, .cntmsk = 0xc, .code = 0x1e, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_c_ring_iv_used), .ngrp = 1, .umasks = ivbep_unc_c_ring_iv_used, }, { .name = "UNC_C_RING_SRC_THRTL", .desc = "TDB", .modmsk = IVBEP_UNC_CBO_ATTRS, .cntmsk = 0x3, .code = 0x07, }, { .name = "UNC_C_RXR_EXT_STARVED", .desc = "Ingress arbiter blocking cycles", .modmsk = IVBEP_UNC_CBO_ATTRS, .cntmsk = 0x3, .code = 0x12, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_c_rxr_ext_starved), .ngrp = 1, .umasks = ivbep_unc_c_rxr_ext_starved, }, { .name = "UNC_C_RXR_INSERTS", .desc = "Ingress Allocations", .code = 0x13, .cntmsk = 0x3, .ngrp = 1, .modmsk = IVBEP_UNC_CBO_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_c_rxr_inserts), .umasks = ivbep_unc_c_rxr_inserts }, { .name = "UNC_C_RXR_IPQ_RETRY", .desc = "Probe Queue Retries", .code = 0x31, .cntmsk = 0x3, .ngrp = 1, .modmsk = IVBEP_UNC_CBO_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_c_rxr_ipq_retry), .umasks = ivbep_unc_c_rxr_ipq_retry }, { .name = "UNC_C_RXR_IRQ_RETRY", .desc = "Ingress Request Queue Rejects", .code = 0x32, .cntmsk = 0x3, .ngrp = 1, .modmsk = IVBEP_UNC_CBO_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_c_rxr_irq_retry), .umasks = ivbep_unc_c_rxr_irq_retry }, { .name = "UNC_C_RXR_ISMQ_RETRY", .desc = "ISMQ Retries", .code = 0x33, .cntmsk = 0x3, .ngrp = 1, .modmsk = IVBEP_UNC_CBO_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_c_rxr_ismq_retry), .umasks = ivbep_unc_c_rxr_ismq_retry }, { .name = "UNC_C_RXR_OCCUPANCY", .desc = "Ingress Occupancy", .code = 0x11, .cntmsk = 0x1, .ngrp = 1, .modmsk = IVBEP_UNC_CBO_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_c_rxr_inserts), .umasks = ivbep_unc_c_rxr_inserts, /* identical to ivbep_unc_c_rxr_inserts */ }, { .name = "UNC_C_TOR_INSERTS", .desc = "TOR Inserts", .code = 0x35, .cntmsk = 0x3, .ngrp = 2, .modmsk = IVBEP_UNC_CBO_NID_ATTRS | _SNBEP_UNC_ATTR_ISOC | _SNBEP_UNC_ATTR_NC, .flags = INTEL_X86_NO_AUTOENCODE, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_c_tor_inserts), .umasks = ivbep_unc_c_tor_inserts }, { .name = "UNC_C_TOR_OCCUPANCY", .desc = "TOR Occupancy", .code = 0x36, .cntmsk = 0x1, .ngrp = 2, .modmsk = IVBEP_UNC_CBO_NID_ATTRS | _SNBEP_UNC_ATTR_ISOC | _SNBEP_UNC_ATTR_NC, .flags = INTEL_X86_NO_AUTOENCODE, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_c_tor_occupancy), .umasks = ivbep_unc_c_tor_occupancy }, { .name = "UNC_C_TXR_ADS_USED", .desc = "Egress events", .code = 0x04, .cntmsk = 0x3, .ngrp = 1, .modmsk = IVBEP_UNC_CBO_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_c_txr_ads_used), .umasks = ivbep_unc_c_txr_ads_used }, { .name = "UNC_C_TXR_INSERTS", .desc = "Egress allocations", .code = 0x02, .cntmsk = 0x3, .ngrp = 1, .modmsk = IVBEP_UNC_CBO_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_c_txr_inserts), .umasks = ivbep_unc_c_txr_inserts }, }; libpfm-4.9.0/lib/events/power6_events.h0000664000175000017500000044150113223402656017654 0ustar eranianeranian/****************************/ /* THIS IS OPEN SOURCE CODE */ /****************************/ #ifndef __POWER6_EVENTS_H__ #define __POWER6_EVENTS_H__ /* * File: power6_events.h * CVS: * Author: Corey Ashford * cjashfor@us.ibm.com * Mods: * * * (C) Copyright IBM Corporation, 2009. All Rights Reserved. * Contributed by Corey Ashford * * Note: This code was automatically generated and should not be modified by * hand. * */ #define POWER6_PME_PM_LSU_REJECT_STQ_FULL 0 #define POWER6_PME_PM_DPU_HELD_FXU_MULTI 1 #define POWER6_PME_PM_VMX1_STALL 2 #define POWER6_PME_PM_PMC2_SAVED 3 #define POWER6_PME_PM_L2SB_IC_INV 4 #define POWER6_PME_PM_IERAT_MISS_64K 5 #define POWER6_PME_PM_THRD_PRIO_DIFF_3or4_CYC 6 #define POWER6_PME_PM_LD_REF_L1_BOTH 7 #define POWER6_PME_PM_FPU1_FCONV 8 #define POWER6_PME_PM_IBUF_FULL_COUNT 9 #define POWER6_PME_PM_MRK_LSU_DERAT_MISS 10 #define POWER6_PME_PM_MRK_ST_CMPL 11 #define POWER6_PME_PM_L2_CASTOUT_MOD 12 #define POWER6_PME_PM_FPU1_ST_FOLDED 13 #define POWER6_PME_PM_MRK_INST_TIMEO 14 #define POWER6_PME_PM_DPU_WT 15 #define POWER6_PME_PM_DPU_HELD_RESTART 16 #define POWER6_PME_PM_IERAT_MISS 17 #define POWER6_PME_PM_FPU_SINGLE 18 #define POWER6_PME_PM_MRK_PTEG_FROM_LMEM 19 #define POWER6_PME_PM_HV_COUNT 20 #define POWER6_PME_PM_L2SA_ST_HIT 21 #define POWER6_PME_PM_L2_LD_MISS_INST 22 #define POWER6_PME_PM_EXT_INT 23 #define POWER6_PME_PM_LSU1_LDF 24 #define POWER6_PME_PM_FAB_CMD_ISSUED 25 #define POWER6_PME_PM_PTEG_FROM_L21 26 #define POWER6_PME_PM_L2SA_MISS 27 #define POWER6_PME_PM_PTEG_FROM_RL2L3_MOD 28 #define POWER6_PME_PM_DPU_WT_COUNT 29 #define POWER6_PME_PM_MRK_PTEG_FROM_L25_MOD 30 #define POWER6_PME_PM_LD_HIT_L2 31 #define POWER6_PME_PM_PTEG_FROM_DL2L3_SHR 32 #define POWER6_PME_PM_MEM_DP_RQ_GLOB_LOC 33 #define POWER6_PME_PM_L3SA_MISS 34 #define POWER6_PME_PM_NO_ITAG_COUNT 35 #define POWER6_PME_PM_DSLB_MISS 36 #define POWER6_PME_PM_LSU_FLUSH_ALIGN 37 #define POWER6_PME_PM_DPU_HELD_FPU_CR 38 #define POWER6_PME_PM_PTEG_FROM_L2MISS 39 #define POWER6_PME_PM_MRK_DATA_FROM_DMEM 40 #define POWER6_PME_PM_PTEG_FROM_LMEM 41 #define POWER6_PME_PM_MRK_DERAT_REF_64K 42 #define POWER6_PME_PM_L2SA_LD_REQ_INST 43 #define POWER6_PME_PM_MRK_DERAT_MISS_16M 44 #define POWER6_PME_PM_DATA_FROM_DL2L3_MOD 45 #define POWER6_PME_PM_FPU0_FXMULT 46 #define POWER6_PME_PM_L3SB_MISS 47 #define POWER6_PME_PM_STCX_CANCEL 48 #define POWER6_PME_PM_L2SA_LD_MISS_DATA 49 #define POWER6_PME_PM_IC_INV_L2 50 #define POWER6_PME_PM_DPU_HELD 51 #define POWER6_PME_PM_PMC1_OVERFLOW 52 #define POWER6_PME_PM_THRD_PRIO_6_CYC 53 #define POWER6_PME_PM_MRK_PTEG_FROM_L3MISS 54 #define POWER6_PME_PM_MRK_LSU0_REJECT_UST 55 #define POWER6_PME_PM_MRK_INST_DISP 56 #define POWER6_PME_PM_LARX 57 #define POWER6_PME_PM_INST_CMPL 58 #define POWER6_PME_PM_FXU_IDLE 59 #define POWER6_PME_PM_MRK_DATA_FROM_DL2L3_MOD 60 #define POWER6_PME_PM_L2_LD_REQ_DATA 61 #define POWER6_PME_PM_LSU_DERAT_MISS_CYC 62 #define POWER6_PME_PM_DPU_HELD_POWER_COUNT 63 #define POWER6_PME_PM_INST_FROM_RL2L3_MOD 64 #define POWER6_PME_PM_DATA_FROM_DMEM_CYC 65 #define POWER6_PME_PM_DATA_FROM_DMEM 66 #define POWER6_PME_PM_LSU_REJECT_PARTIAL_SECTOR 67 #define POWER6_PME_PM_LSU_REJECT_DERAT_MPRED 68 #define POWER6_PME_PM_LSU1_REJECT_ULD 69 #define POWER6_PME_PM_DATA_FROM_L3_CYC 70 #define POWER6_PME_PM_FXU1_BUSY_FXU0_IDLE 71 #define POWER6_PME_PM_INST_FROM_MEM_DP 72 #define POWER6_PME_PM_LSU_FLUSH_DSI 73 #define POWER6_PME_PM_MRK_DERAT_REF_16G 74 #define POWER6_PME_PM_LSU_LDF_BOTH 75 #define POWER6_PME_PM_FPU1_1FLOP 76 #define POWER6_PME_PM_DATA_FROM_RMEM_CYC 77 #define POWER6_PME_PM_INST_PTEG_SECONDARY 78 #define POWER6_PME_PM_L1_ICACHE_MISS 79 #define POWER6_PME_PM_INST_DISP_LLA 80 #define POWER6_PME_PM_THRD_BOTH_RUN_CYC 81 #define POWER6_PME_PM_LSU_ST_CHAINED 82 #define POWER6_PME_PM_FPU1_FXDIV 83 #define POWER6_PME_PM_FREQ_UP 84 #define POWER6_PME_PM_FAB_RETRY_SYS_PUMP 85 #define POWER6_PME_PM_DATA_FROM_LMEM 86 #define POWER6_PME_PM_PMC3_OVERFLOW 87 #define POWER6_PME_PM_LSU0_REJECT_SET_MPRED 88 #define POWER6_PME_PM_LSU0_REJECT_DERAT_MPRED 89 #define POWER6_PME_PM_LSU1_REJECT_STQ_FULL 90 #define POWER6_PME_PM_MRK_BR_MPRED 91 #define POWER6_PME_PM_L2SA_ST_MISS 92 #define POWER6_PME_PM_LSU0_REJECT_EXTERN 93 #define POWER6_PME_PM_MRK_BR_TAKEN 94 #define POWER6_PME_PM_ISLB_MISS 95 #define POWER6_PME_PM_CYC 96 #define POWER6_PME_PM_FPU_FXDIV 97 #define POWER6_PME_PM_DPU_HELD_LLA_END 98 #define POWER6_PME_PM_MEM0_DP_CL_WR_LOC 99 #define POWER6_PME_PM_MRK_LSU_REJECT_ULD 100 #define POWER6_PME_PM_1PLUS_PPC_CMPL 101 #define POWER6_PME_PM_PTEG_FROM_DMEM 102 #define POWER6_PME_PM_DPU_WT_BR_MPRED_COUNT 103 #define POWER6_PME_PM_GCT_FULL_CYC 104 #define POWER6_PME_PM_INST_FROM_L25_SHR 105 #define POWER6_PME_PM_MRK_DERAT_MISS_4K 106 #define POWER6_PME_PM_DC_PREF_STREAM_ALLOC 107 #define POWER6_PME_PM_FPU1_FIN 108 #define POWER6_PME_PM_BR_MPRED_TA 109 #define POWER6_PME_PM_DPU_HELD_POWER 110 #define POWER6_PME_PM_RUN_INST_CMPL 111 #define POWER6_PME_PM_GCT_EMPTY_CYC 112 #define POWER6_PME_PM_LLA_COUNT 113 #define POWER6_PME_PM_LSU0_REJECT_NO_SCRATCH 114 #define POWER6_PME_PM_DPU_WT_IC_MISS 115 #define POWER6_PME_PM_DATA_FROM_L3MISS 116 #define POWER6_PME_PM_FPU_FPSCR 117 #define POWER6_PME_PM_VMX1_INST_ISSUED 118 #define POWER6_PME_PM_FLUSH 119 #define POWER6_PME_PM_ST_HIT_L2 120 #define POWER6_PME_PM_SYNC_CYC 121 #define POWER6_PME_PM_FAB_SYS_PUMP 122 #define POWER6_PME_PM_IC_PREF_REQ 123 #define POWER6_PME_PM_MEM0_DP_RQ_GLOB_LOC 124 #define POWER6_PME_PM_FPU_ISSUE_0 125 #define POWER6_PME_PM_THRD_PRIO_2_CYC 126 #define POWER6_PME_PM_VMX_SIMPLE_ISSUED 127 #define POWER6_PME_PM_MRK_FPU1_FIN 128 #define POWER6_PME_PM_DPU_HELD_CW 129 #define POWER6_PME_PM_L3SA_REF 130 #define POWER6_PME_PM_STCX 131 #define POWER6_PME_PM_L2SB_MISS 132 #define POWER6_PME_PM_LSU0_REJECT 133 #define POWER6_PME_PM_TB_BIT_TRANS 134 #define POWER6_PME_PM_THERMAL_MAX 135 #define POWER6_PME_PM_FPU0_STF 136 #define POWER6_PME_PM_FPU1_FMA 137 #define POWER6_PME_PM_LSU1_REJECT_LHS 138 #define POWER6_PME_PM_DPU_HELD_INT 139 #define POWER6_PME_PM_THRD_LLA_BOTH_CYC 140 #define POWER6_PME_PM_DPU_HELD_THERMAL_COUNT 141 #define POWER6_PME_PM_PMC4_REWIND 142 #define POWER6_PME_PM_DERAT_REF_16M 143 #define POWER6_PME_PM_FPU0_FCONV 144 #define POWER6_PME_PM_L2SA_LD_REQ_DATA 145 #define POWER6_PME_PM_DATA_FROM_MEM_DP 146 #define POWER6_PME_PM_MRK_VMX_FLOAT_ISSUED 147 #define POWER6_PME_PM_MRK_PTEG_FROM_L2MISS 148 #define POWER6_PME_PM_THRD_PRIO_DIFF_1or2_CYC 149 #define POWER6_PME_PM_VMX0_STALL 150 #define POWER6_PME_PM_IC_DEMAND_L2_BHT_REDIRECT 151 #define POWER6_PME_PM_LSU_DERAT_MISS 152 #define POWER6_PME_PM_FPU0_SINGLE 153 #define POWER6_PME_PM_FPU_ISSUE_STEERING 154 #define POWER6_PME_PM_THRD_PRIO_1_CYC 155 #define POWER6_PME_PM_VMX_COMPLEX_ISSUED 156 #define POWER6_PME_PM_FPU_ISSUE_ST_FOLDED 157 #define POWER6_PME_PM_DFU_FIN 158 #define POWER6_PME_PM_BR_PRED_CCACHE 159 #define POWER6_PME_PM_MRK_ST_CMPL_INT 160 #define POWER6_PME_PM_FAB_MMIO 161 #define POWER6_PME_PM_MRK_VMX_SIMPLE_ISSUED 162 #define POWER6_PME_PM_FPU_STF 163 #define POWER6_PME_PM_MEM1_DP_CL_WR_GLOB 164 #define POWER6_PME_PM_MRK_DATA_FROM_L3MISS 165 #define POWER6_PME_PM_GCT_NOSLOT_CYC 166 #define POWER6_PME_PM_L2_ST_REQ_DATA 167 #define POWER6_PME_PM_INST_TABLEWALK_COUNT 168 #define POWER6_PME_PM_PTEG_FROM_L35_SHR 169 #define POWER6_PME_PM_DPU_HELD_ISYNC 170 #define POWER6_PME_PM_MRK_DATA_FROM_L25_SHR 171 #define POWER6_PME_PM_L3SA_HIT 172 #define POWER6_PME_PM_DERAT_MISS_16G 173 #define POWER6_PME_PM_DATA_PTEG_2ND_HALF 174 #define POWER6_PME_PM_L2SA_ST_REQ 175 #define POWER6_PME_PM_INST_FROM_LMEM 176 #define POWER6_PME_PM_IC_DEMAND_L2_BR_REDIRECT 177 #define POWER6_PME_PM_PTEG_FROM_L2 178 #define POWER6_PME_PM_DATA_PTEG_1ST_HALF 179 #define POWER6_PME_PM_BR_MPRED_COUNT 180 #define POWER6_PME_PM_IERAT_MISS_4K 181 #define POWER6_PME_PM_THRD_BOTH_RUN_COUNT 182 #define POWER6_PME_PM_LSU_REJECT_ULD 183 #define POWER6_PME_PM_DATA_FROM_DL2L3_MOD_CYC 184 #define POWER6_PME_PM_MRK_PTEG_FROM_RL2L3_MOD 185 #define POWER6_PME_PM_FPU0_FLOP 186 #define POWER6_PME_PM_FPU0_FEST 187 #define POWER6_PME_PM_MRK_LSU0_REJECT_LHS 188 #define POWER6_PME_PM_VMX_RESULT_SAT_1 189 #define POWER6_PME_PM_NO_ITAG_CYC 190 #define POWER6_PME_PM_LSU1_REJECT_NO_SCRATCH 191 #define POWER6_PME_PM_0INST_FETCH 192 #define POWER6_PME_PM_DPU_WT_BR_MPRED 193 #define POWER6_PME_PM_L1_PREF 194 #define POWER6_PME_PM_VMX_FLOAT_MULTICYCLE 195 #define POWER6_PME_PM_DATA_FROM_L25_SHR_CYC 196 #define POWER6_PME_PM_DATA_FROM_L3 197 #define POWER6_PME_PM_PMC2_OVERFLOW 198 #define POWER6_PME_PM_VMX0_LD_WRBACK 199 #define POWER6_PME_PM_FPU0_DENORM 200 #define POWER6_PME_PM_INST_FETCH_CYC 201 #define POWER6_PME_PM_LSU_LDF 202 #define POWER6_PME_PM_LSU_REJECT_L2_CORR 203 #define POWER6_PME_PM_DERAT_REF_64K 204 #define POWER6_PME_PM_THRD_PRIO_3_CYC 205 #define POWER6_PME_PM_FPU_FMA 206 #define POWER6_PME_PM_INST_FROM_L35_MOD 207 #define POWER6_PME_PM_DFU_CONV 208 #define POWER6_PME_PM_INST_FROM_L25_MOD 209 #define POWER6_PME_PM_PTEG_FROM_L35_MOD 210 #define POWER6_PME_PM_MRK_VMX_ST_ISSUED 211 #define POWER6_PME_PM_VMX_FLOAT_ISSUED 212 #define POWER6_PME_PM_LSU0_REJECT_L2_CORR 213 #define POWER6_PME_PM_THRD_L2MISS 214 #define POWER6_PME_PM_FPU_FCONV 215 #define POWER6_PME_PM_FPU_FXMULT 216 #define POWER6_PME_PM_FPU1_FRSP 217 #define POWER6_PME_PM_MRK_DERAT_REF_16M 218 #define POWER6_PME_PM_L2SB_CASTOUT_SHR 219 #define POWER6_PME_PM_THRD_ONE_RUN_COUNT 220 #define POWER6_PME_PM_INST_FROM_RMEM 221 #define POWER6_PME_PM_LSU_BOTH_BUS 222 #define POWER6_PME_PM_FPU1_FSQRT_FDIV 223 #define POWER6_PME_PM_L2_LD_REQ_INST 224 #define POWER6_PME_PM_MRK_PTEG_FROM_L35_SHR 225 #define POWER6_PME_PM_BR_PRED_CR 226 #define POWER6_PME_PM_MRK_LSU0_REJECT_ULD 227 #define POWER6_PME_PM_LSU_REJECT 228 #define POWER6_PME_PM_LSU_REJECT_LHS_BOTH 229 #define POWER6_PME_PM_GXO_ADDR_CYC_BUSY 230 #define POWER6_PME_PM_LSU_SRQ_EMPTY_COUNT 231 #define POWER6_PME_PM_PTEG_FROM_L3 232 #define POWER6_PME_PM_VMX0_LD_ISSUED 233 #define POWER6_PME_PM_FXU_PIPELINED_MULT_DIV 234 #define POWER6_PME_PM_FPU1_STF 235 #define POWER6_PME_PM_DFU_ADD 236 #define POWER6_PME_PM_MEM_DP_CL_WR_GLOB 237 #define POWER6_PME_PM_MRK_LSU1_REJECT_ULD 238 #define POWER6_PME_PM_ITLB_REF 239 #define POWER6_PME_PM_LSU0_REJECT_L2MISS 240 #define POWER6_PME_PM_DATA_FROM_L35_SHR 241 #define POWER6_PME_PM_MRK_DATA_FROM_RL2L3_MOD 242 #define POWER6_PME_PM_FPU0_FPSCR 243 #define POWER6_PME_PM_DATA_FROM_L2 244 #define POWER6_PME_PM_DPU_HELD_XER 245 #define POWER6_PME_PM_FAB_NODE_PUMP 246 #define POWER6_PME_PM_VMX_RESULT_SAT_0_1 247 #define POWER6_PME_PM_LD_REF_L1 248 #define POWER6_PME_PM_TLB_REF 249 #define POWER6_PME_PM_DC_PREF_OUT_OF_STREAMS 250 #define POWER6_PME_PM_FLUSH_FPU 251 #define POWER6_PME_PM_MEM1_DP_CL_WR_LOC 252 #define POWER6_PME_PM_L2SB_LD_HIT 253 #define POWER6_PME_PM_FAB_DCLAIM 254 #define POWER6_PME_PM_MEM_DP_CL_WR_LOC 255 #define POWER6_PME_PM_BR_MPRED_CR 256 #define POWER6_PME_PM_LSU_REJECT_EXTERN 257 #define POWER6_PME_PM_DATA_FROM_RL2L3_MOD 258 #define POWER6_PME_PM_DPU_HELD_RU_WQ 259 #define POWER6_PME_PM_LD_MISS_L1 260 #define POWER6_PME_PM_DC_INV_L2 261 #define POWER6_PME_PM_MRK_PTEG_FROM_RMEM 262 #define POWER6_PME_PM_FPU_FIN 263 #define POWER6_PME_PM_FXU0_FIN 264 #define POWER6_PME_PM_DPU_HELD_FPQ 265 #define POWER6_PME_PM_GX_DMA_READ 266 #define POWER6_PME_PM_LSU1_REJECT_PARTIAL_SECTOR 267 #define POWER6_PME_PM_0INST_FETCH_COUNT 268 #define POWER6_PME_PM_PMC5_OVERFLOW 269 #define POWER6_PME_PM_L2SB_LD_REQ 270 #define POWER6_PME_PM_THRD_PRIO_DIFF_0_CYC 271 #define POWER6_PME_PM_DATA_FROM_RMEM 272 #define POWER6_PME_PM_LSU_LMQ_SRQ_EMPTY_BOTH_CYC 273 #define POWER6_PME_PM_ST_REF_L1_BOTH 274 #define POWER6_PME_PM_VMX_PERMUTE_ISSUED 275 #define POWER6_PME_PM_BR_TAKEN 276 #define POWER6_PME_PM_FAB_DMA 277 #define POWER6_PME_PM_GCT_EMPTY_COUNT 278 #define POWER6_PME_PM_FPU1_SINGLE 279 #define POWER6_PME_PM_L2SA_CASTOUT_SHR 280 #define POWER6_PME_PM_L3SB_REF 281 #define POWER6_PME_PM_FPU0_FRSP 282 #define POWER6_PME_PM_PMC4_SAVED 283 #define POWER6_PME_PM_L2SA_DC_INV 284 #define POWER6_PME_PM_GXI_ADDR_CYC_BUSY 285 #define POWER6_PME_PM_FPU0_FMA 286 #define POWER6_PME_PM_SLB_MISS 287 #define POWER6_PME_PM_MRK_ST_GPS 288 #define POWER6_PME_PM_DERAT_REF_4K 289 #define POWER6_PME_PM_L2_CASTOUT_SHR 290 #define POWER6_PME_PM_DPU_HELD_STCX_CR 291 #define POWER6_PME_PM_FPU0_ST_FOLDED 292 #define POWER6_PME_PM_MRK_DATA_FROM_L21 293 #define POWER6_PME_PM_THRD_PRIO_DIFF_minus3or4_CYC 294 #define POWER6_PME_PM_DATA_FROM_L35_MOD 295 #define POWER6_PME_PM_DATA_FROM_DL2L3_SHR 296 #define POWER6_PME_PM_GXI_DATA_CYC_BUSY 297 #define POWER6_PME_PM_LSU_REJECT_STEAL 298 #define POWER6_PME_PM_ST_FIN 299 #define POWER6_PME_PM_DPU_HELD_CR_LOGICAL 300 #define POWER6_PME_PM_THRD_SEL_T0 301 #define POWER6_PME_PM_PTEG_RELOAD_VALID 302 #define POWER6_PME_PM_L2_PREF_ST 303 #define POWER6_PME_PM_MRK_STCX_FAIL 304 #define POWER6_PME_PM_LSU0_REJECT_LHS 305 #define POWER6_PME_PM_DFU_EXP_EQ 306 #define POWER6_PME_PM_DPU_HELD_FP_FX_MULT 307 #define POWER6_PME_PM_L2_LD_MISS_DATA 308 #define POWER6_PME_PM_DATA_FROM_L35_MOD_CYC 309 #define POWER6_PME_PM_FLUSH_FXU 310 #define POWER6_PME_PM_FPU_ISSUE_1 311 #define POWER6_PME_PM_DATA_FROM_LMEM_CYC 312 #define POWER6_PME_PM_DPU_HELD_LSU_SOPS 313 #define POWER6_PME_PM_INST_PTEG_2ND_HALF 314 #define POWER6_PME_PM_THRESH_TIMEO 315 #define POWER6_PME_PM_LSU_REJECT_UST_BOTH 316 #define POWER6_PME_PM_LSU_REJECT_FAST 317 #define POWER6_PME_PM_DPU_HELD_THRD_PRIO 318 #define POWER6_PME_PM_L2_PREF_LD 319 #define POWER6_PME_PM_FPU_FEST 320 #define POWER6_PME_PM_MRK_DATA_FROM_RMEM 321 #define POWER6_PME_PM_LD_MISS_L1_CYC 322 #define POWER6_PME_PM_DERAT_MISS_4K 323 #define POWER6_PME_PM_DPU_HELD_COMPLETION 324 #define POWER6_PME_PM_FPU_ISSUE_STALL_ST 325 #define POWER6_PME_PM_L2SB_DC_INV 326 #define POWER6_PME_PM_PTEG_FROM_L25_SHR 327 #define POWER6_PME_PM_PTEG_FROM_DL2L3_MOD 328 #define POWER6_PME_PM_FAB_CMD_RETRIED 329 #define POWER6_PME_PM_BR_PRED_LSTACK 330 #define POWER6_PME_PM_GXO_DATA_CYC_BUSY 331 #define POWER6_PME_PM_DFU_SUBNORM 332 #define POWER6_PME_PM_FPU_ISSUE_OOO 333 #define POWER6_PME_PM_LSU_REJECT_ULD_BOTH 334 #define POWER6_PME_PM_L2SB_ST_MISS 335 #define POWER6_PME_PM_DATA_FROM_L25_MOD_CYC 336 #define POWER6_PME_PM_INST_PTEG_1ST_HALF 337 #define POWER6_PME_PM_DERAT_MISS_16M 338 #define POWER6_PME_PM_GX_DMA_WRITE 339 #define POWER6_PME_PM_MRK_PTEG_FROM_DL2L3_MOD 340 #define POWER6_PME_PM_MEM1_DP_RQ_GLOB_LOC 341 #define POWER6_PME_PM_L2SB_LD_REQ_DATA 342 #define POWER6_PME_PM_L2SA_LD_MISS_INST 343 #define POWER6_PME_PM_MRK_LSU0_REJECT_L2MISS 344 #define POWER6_PME_PM_MRK_IFU_FIN 345 #define POWER6_PME_PM_INST_FROM_L3 346 #define POWER6_PME_PM_FXU1_FIN 347 #define POWER6_PME_PM_THRD_PRIO_4_CYC 348 #define POWER6_PME_PM_MRK_DATA_FROM_L35_MOD 349 #define POWER6_PME_PM_LSU_REJECT_SET_MPRED 350 #define POWER6_PME_PM_MRK_DERAT_MISS_16G 351 #define POWER6_PME_PM_FPU0_FXDIV 352 #define POWER6_PME_PM_MRK_LSU1_REJECT_UST 353 #define POWER6_PME_PM_FPU_ISSUE_DIV_SQRT_OVERLAP 354 #define POWER6_PME_PM_INST_FROM_L35_SHR 355 #define POWER6_PME_PM_MRK_LSU_REJECT_LHS 356 #define POWER6_PME_PM_LSU_LMQ_FULL_CYC 357 #define POWER6_PME_PM_SYNC_COUNT 358 #define POWER6_PME_PM_MEM0_DP_RQ_LOC_GLOB 359 #define POWER6_PME_PM_L2SA_CASTOUT_MOD 360 #define POWER6_PME_PM_LSU_LMQ_SRQ_EMPTY_BOTH_COUNT 361 #define POWER6_PME_PM_PTEG_FROM_MEM_DP 362 #define POWER6_PME_PM_LSU_REJECT_SLOW 363 #define POWER6_PME_PM_PTEG_FROM_L25_MOD 364 #define POWER6_PME_PM_THRD_PRIO_7_CYC 365 #define POWER6_PME_PM_MRK_PTEG_FROM_RL2L3_SHR 366 #define POWER6_PME_PM_ST_REQ_L2 367 #define POWER6_PME_PM_ST_REF_L1 368 #define POWER6_PME_PM_FPU_ISSUE_STALL_THRD 369 #define POWER6_PME_PM_RUN_COUNT 370 #define POWER6_PME_PM_RUN_CYC 371 #define POWER6_PME_PM_PTEG_FROM_RMEM 372 #define POWER6_PME_PM_LSU0_LDF 373 #define POWER6_PME_PM_ST_MISS_L1 374 #define POWER6_PME_PM_INST_FROM_DL2L3_SHR 375 #define POWER6_PME_PM_L2SA_IC_INV 376 #define POWER6_PME_PM_THRD_ONE_RUN_CYC 377 #define POWER6_PME_PM_L2SB_LD_REQ_INST 378 #define POWER6_PME_PM_MRK_DATA_FROM_L25_MOD 379 #define POWER6_PME_PM_DPU_HELD_XTHRD 380 #define POWER6_PME_PM_L2SB_ST_REQ 381 #define POWER6_PME_PM_INST_FROM_L21 382 #define POWER6_PME_PM_INST_FROM_L3MISS 383 #define POWER6_PME_PM_L3SB_HIT 384 #define POWER6_PME_PM_EE_OFF_EXT_INT 385 #define POWER6_PME_PM_INST_FROM_DL2L3_MOD 386 #define POWER6_PME_PM_PMC6_OVERFLOW 387 #define POWER6_PME_PM_FPU_FLOP 388 #define POWER6_PME_PM_FXU_BUSY 389 #define POWER6_PME_PM_FPU1_FLOP 390 #define POWER6_PME_PM_IC_RELOAD_SHR 391 #define POWER6_PME_PM_INST_TABLEWALK_CYC 392 #define POWER6_PME_PM_DATA_FROM_RL2L3_MOD_CYC 393 #define POWER6_PME_PM_THRD_PRIO_DIFF_5or6_CYC 394 #define POWER6_PME_PM_IBUF_FULL_CYC 395 #define POWER6_PME_PM_L2SA_LD_REQ 396 #define POWER6_PME_PM_VMX1_LD_WRBACK 397 #define POWER6_PME_PM_MRK_FPU_FIN 398 #define POWER6_PME_PM_THRD_PRIO_5_CYC 399 #define POWER6_PME_PM_DFU_BACK2BACK 400 #define POWER6_PME_PM_MRK_DATA_FROM_LMEM 401 #define POWER6_PME_PM_LSU_REJECT_LHS 402 #define POWER6_PME_PM_DPU_HELD_SPR 403 #define POWER6_PME_PM_FREQ_DOWN 404 #define POWER6_PME_PM_DFU_ENC_BCD_DPD 405 #define POWER6_PME_PM_DPU_HELD_GPR 406 #define POWER6_PME_PM_LSU0_NCST 407 #define POWER6_PME_PM_MRK_INST_ISSUED 408 #define POWER6_PME_PM_INST_FROM_RL2L3_SHR 409 #define POWER6_PME_PM_FPU_DENORM 410 #define POWER6_PME_PM_PTEG_FROM_L3MISS 411 #define POWER6_PME_PM_RUN_PURR 412 #define POWER6_PME_PM_MRK_VMX0_LD_WRBACK 413 #define POWER6_PME_PM_L2_MISS 414 #define POWER6_PME_PM_MRK_DATA_FROM_L3 415 #define POWER6_PME_PM_MRK_LSU1_REJECT_LHS 416 #define POWER6_PME_PM_L2SB_LD_MISS_INST 417 #define POWER6_PME_PM_PTEG_FROM_RL2L3_SHR 418 #define POWER6_PME_PM_MRK_DERAT_MISS_64K 419 #define POWER6_PME_PM_LWSYNC 420 #define POWER6_PME_PM_FPU1_FXMULT 421 #define POWER6_PME_PM_MEM0_DP_CL_WR_GLOB 422 #define POWER6_PME_PM_LSU0_REJECT_PARTIAL_SECTOR 423 #define POWER6_PME_PM_INST_IMC_MATCH_CMPL 424 #define POWER6_PME_PM_DPU_HELD_THERMAL 425 #define POWER6_PME_PM_FPU_FRSP 426 #define POWER6_PME_PM_MRK_INST_FIN 427 #define POWER6_PME_PM_MRK_PTEG_FROM_DL2L3_SHR 428 #define POWER6_PME_PM_MRK_DTLB_REF 429 #define POWER6_PME_PM_MRK_PTEG_FROM_L25_SHR 430 #define POWER6_PME_PM_DPU_HELD_LSU 431 #define POWER6_PME_PM_FPU_FSQRT_FDIV 432 #define POWER6_PME_PM_LSU_LMQ_SRQ_EMPTY_COUNT 433 #define POWER6_PME_PM_DATA_PTEG_SECONDARY 434 #define POWER6_PME_PM_FPU1_FEST 435 #define POWER6_PME_PM_L2SA_LD_HIT 436 #define POWER6_PME_PM_DATA_FROM_MEM_DP_CYC 437 #define POWER6_PME_PM_BR_MPRED_CCACHE 438 #define POWER6_PME_PM_DPU_HELD_COUNT 439 #define POWER6_PME_PM_LSU1_REJECT_SET_MPRED 440 #define POWER6_PME_PM_FPU_ISSUE_2 441 #define POWER6_PME_PM_LSU1_REJECT_L2_CORR 442 #define POWER6_PME_PM_MRK_PTEG_FROM_DMEM 443 #define POWER6_PME_PM_MEM1_DP_RQ_LOC_GLOB 444 #define POWER6_PME_PM_THRD_PRIO_DIFF_minus1or2_CYC 445 #define POWER6_PME_PM_THRD_PRIO_0_CYC 446 #define POWER6_PME_PM_FXU0_BUSY_FXU1_IDLE 447 #define POWER6_PME_PM_LSU1_REJECT_DERAT_MPRED 448 #define POWER6_PME_PM_MRK_VMX1_LD_WRBACK 449 #define POWER6_PME_PM_DATA_FROM_RL2L3_SHR_CYC 450 #define POWER6_PME_PM_IERAT_MISS_16M 451 #define POWER6_PME_PM_MRK_DATA_FROM_MEM_DP 452 #define POWER6_PME_PM_LARX_L1HIT 453 #define POWER6_PME_PM_L2_ST_MISS_DATA 454 #define POWER6_PME_PM_FPU_ST_FOLDED 455 #define POWER6_PME_PM_MRK_DATA_FROM_L35_SHR 456 #define POWER6_PME_PM_DPU_HELD_MULT_GPR 457 #define POWER6_PME_PM_FPU0_1FLOP 458 #define POWER6_PME_PM_IERAT_MISS_16G 459 #define POWER6_PME_PM_IC_PREF_WRITE 460 #define POWER6_PME_PM_THRD_PRIO_DIFF_minus5or6_CYC 461 #define POWER6_PME_PM_FPU0_FIN 462 #define POWER6_PME_PM_DATA_FROM_L2_CYC 463 #define POWER6_PME_PM_DERAT_REF_16G 464 #define POWER6_PME_PM_BR_PRED 465 #define POWER6_PME_PM_VMX1_LD_ISSUED 466 #define POWER6_PME_PM_L2SB_CASTOUT_MOD 467 #define POWER6_PME_PM_INST_FROM_DMEM 468 #define POWER6_PME_PM_DATA_FROM_L35_SHR_CYC 469 #define POWER6_PME_PM_LSU0_NCLD 470 #define POWER6_PME_PM_FAB_RETRY_NODE_PUMP 471 #define POWER6_PME_PM_VMX0_INST_ISSUED 472 #define POWER6_PME_PM_DATA_FROM_L25_MOD 473 #define POWER6_PME_PM_DPU_HELD_ITLB_ISLB 474 #define POWER6_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC 475 #define POWER6_PME_PM_THRD_CONC_RUN_INST 476 #define POWER6_PME_PM_MRK_PTEG_FROM_L2 477 #define POWER6_PME_PM_PURR 478 #define POWER6_PME_PM_DERAT_MISS_64K 479 #define POWER6_PME_PM_PMC2_REWIND 480 #define POWER6_PME_PM_INST_FROM_L2 481 #define POWER6_PME_PM_INST_DISP 482 #define POWER6_PME_PM_DATA_FROM_L25_SHR 483 #define POWER6_PME_PM_L1_DCACHE_RELOAD_VALID 484 #define POWER6_PME_PM_LSU1_REJECT_UST 485 #define POWER6_PME_PM_FAB_ADDR_COLLISION 486 #define POWER6_PME_PM_MRK_FXU_FIN 487 #define POWER6_PME_PM_LSU0_REJECT_UST 488 #define POWER6_PME_PM_PMC4_OVERFLOW 489 #define POWER6_PME_PM_MRK_PTEG_FROM_L3 490 #define POWER6_PME_PM_INST_FROM_L2MISS 491 #define POWER6_PME_PM_L2SB_ST_HIT 492 #define POWER6_PME_PM_DPU_WT_IC_MISS_COUNT 493 #define POWER6_PME_PM_MRK_DATA_FROM_DL2L3_SHR 494 #define POWER6_PME_PM_MRK_PTEG_FROM_L35_MOD 495 #define POWER6_PME_PM_FPU1_FPSCR 496 #define POWER6_PME_PM_LSU_REJECT_UST 497 #define POWER6_PME_PM_LSU0_DERAT_MISS 498 #define POWER6_PME_PM_MRK_PTEG_FROM_MEM_DP 499 #define POWER6_PME_PM_MRK_DATA_FROM_L2 500 #define POWER6_PME_PM_FPU0_FSQRT_FDIV 501 #define POWER6_PME_PM_DPU_HELD_FXU_SOPS 502 #define POWER6_PME_PM_MRK_FPU0_FIN 503 #define POWER6_PME_PM_L2SB_LD_MISS_DATA 504 #define POWER6_PME_PM_LSU_SRQ_EMPTY_CYC 505 #define POWER6_PME_PM_1PLUS_PPC_DISP 506 #define POWER6_PME_PM_VMX_ST_ISSUED 507 #define POWER6_PME_PM_DATA_FROM_L2MISS 508 #define POWER6_PME_PM_LSU0_REJECT_ULD 509 #define POWER6_PME_PM_SUSPENDED 510 #define POWER6_PME_PM_DFU_ADD_SHIFTED_BOTH 511 #define POWER6_PME_PM_LSU_REJECT_NO_SCRATCH 512 #define POWER6_PME_PM_STCX_FAIL 513 #define POWER6_PME_PM_FPU1_DENORM 514 #define POWER6_PME_PM_GCT_NOSLOT_COUNT 515 #define POWER6_PME_PM_DATA_FROM_DL2L3_SHR_CYC 516 #define POWER6_PME_PM_DATA_FROM_L21 517 #define POWER6_PME_PM_FPU_1FLOP 518 #define POWER6_PME_PM_LSU1_REJECT 519 #define POWER6_PME_PM_IC_REQ 520 #define POWER6_PME_PM_MRK_DFU_FIN 521 #define POWER6_PME_PM_NOT_LLA_CYC 522 #define POWER6_PME_PM_INST_FROM_L1 523 #define POWER6_PME_PM_MRK_VMX_COMPLEX_ISSUED 524 #define POWER6_PME_PM_BRU_FIN 525 #define POWER6_PME_PM_LSU1_REJECT_EXTERN 526 #define POWER6_PME_PM_DATA_FROM_L21_CYC 527 #define POWER6_PME_PM_GXI_CYC_BUSY 528 #define POWER6_PME_PM_MRK_LD_MISS_L1 529 #define POWER6_PME_PM_L1_WRITE_CYC 530 #define POWER6_PME_PM_LLA_CYC 531 #define POWER6_PME_PM_MRK_DATA_FROM_L2MISS 532 #define POWER6_PME_PM_GCT_FULL_COUNT 533 #define POWER6_PME_PM_MEM_DP_RQ_LOC_GLOB 534 #define POWER6_PME_PM_DATA_FROM_RL2L3_SHR 535 #define POWER6_PME_PM_MRK_LSU_REJECT_UST 536 #define POWER6_PME_PM_MRK_VMX_PERMUTE_ISSUED 537 #define POWER6_PME_PM_MRK_PTEG_FROM_L21 538 #define POWER6_PME_PM_THRD_GRP_CMPL_BOTH_CYC 539 #define POWER6_PME_PM_BR_MPRED 540 #define POWER6_PME_PM_LD_REQ_L2 541 #define POWER6_PME_PM_FLUSH_ASYNC 542 #define POWER6_PME_PM_HV_CYC 543 #define POWER6_PME_PM_LSU1_DERAT_MISS 544 #define POWER6_PME_PM_DPU_HELD_SMT 545 #define POWER6_PME_PM_MRK_LSU_FIN 546 #define POWER6_PME_PM_MRK_DATA_FROM_RL2L3_SHR 547 #define POWER6_PME_PM_LSU0_REJECT_STQ_FULL 548 #define POWER6_PME_PM_MRK_DERAT_REF_4K 549 #define POWER6_PME_PM_FPU_ISSUE_STALL_FPR 550 #define POWER6_PME_PM_IFU_FIN 551 #define POWER6_PME_PM_GXO_CYC_BUSY 552 static const pme_power_entry_t power6_pe[] = { [ POWER6_PME_PM_LSU_REJECT_STQ_FULL ] = { .pme_name = "PM_LSU_REJECT_STQ_FULL", .pme_code = 0x1a0030, .pme_short_desc = "LSU reject due to store queue full", .pme_long_desc = "LSU reject due to store queue full", }, [ POWER6_PME_PM_DPU_HELD_FXU_MULTI ] = { .pme_name = "PM_DPU_HELD_FXU_MULTI", .pme_code = 0x210a6, .pme_short_desc = "DISP unit held due to FXU multicycle", .pme_long_desc = "DISP unit held due to FXU multicycle", }, [ POWER6_PME_PM_VMX1_STALL ] = { .pme_name = "PM_VMX1_STALL", .pme_code = 0xb008c, .pme_short_desc = "VMX1 stall", .pme_long_desc = "VMX1 stall", }, [ POWER6_PME_PM_PMC2_SAVED ] = { .pme_name = "PM_PMC2_SAVED", .pme_code = 0x100022, .pme_short_desc = "PMC2 rewind value saved", .pme_long_desc = "PMC2 rewind value saved", }, [ POWER6_PME_PM_L2SB_IC_INV ] = { .pme_name = "PM_L2SB_IC_INV", .pme_code = 0x5068c, .pme_short_desc = "L2 slice B I cache invalidate", .pme_long_desc = "L2 slice B I cache invalidate", }, [ POWER6_PME_PM_IERAT_MISS_64K ] = { .pme_name = "PM_IERAT_MISS_64K", .pme_code = 0x392076, .pme_short_desc = "IERAT misses for 64K page", .pme_long_desc = "IERAT misses for 64K page", }, [ POWER6_PME_PM_THRD_PRIO_DIFF_3or4_CYC ] = { .pme_name = "PM_THRD_PRIO_DIFF_3or4_CYC", .pme_code = 0x323040, .pme_short_desc = "Cycles thread priority difference is 3 or 4", .pme_long_desc = "Cycles thread priority difference is 3 or 4", }, [ POWER6_PME_PM_LD_REF_L1_BOTH ] = { .pme_name = "PM_LD_REF_L1_BOTH", .pme_code = 0x180036, .pme_short_desc = "Both units L1 D cache load reference", .pme_long_desc = "Both units L1 D cache load reference", }, [ POWER6_PME_PM_FPU1_FCONV ] = { .pme_name = "PM_FPU1_FCONV", .pme_code = 0xd10a8, .pme_short_desc = "FPU1 executed FCONV instruction", .pme_long_desc = "FPU1 executed FCONV instruction", }, [ POWER6_PME_PM_IBUF_FULL_COUNT ] = { .pme_name = "PM_IBUF_FULL_COUNT", .pme_code = 0x40085, .pme_short_desc = "Periods instruction buffer full", .pme_long_desc = "Periods instruction buffer full", }, [ POWER6_PME_PM_MRK_LSU_DERAT_MISS ] = { .pme_name = "PM_MRK_LSU_DERAT_MISS", .pme_code = 0x400012, .pme_short_desc = "Marked DERAT miss", .pme_long_desc = "Marked DERAT miss", }, [ POWER6_PME_PM_MRK_ST_CMPL ] = { .pme_name = "PM_MRK_ST_CMPL", .pme_code = 0x100006, .pme_short_desc = "Marked store instruction completed", .pme_long_desc = "A sampled store has completed (data home)", }, [ POWER6_PME_PM_L2_CASTOUT_MOD ] = { .pme_name = "PM_L2_CASTOUT_MOD", .pme_code = 0x150630, .pme_short_desc = "L2 castouts - Modified (M, Mu, Me)", .pme_long_desc = "L2 castouts - Modified (M, Mu, Me)", }, [ POWER6_PME_PM_FPU1_ST_FOLDED ] = { .pme_name = "PM_FPU1_ST_FOLDED", .pme_code = 0xd10ac, .pme_short_desc = "FPU1 folded store", .pme_long_desc = "FPU1 folded store", }, [ POWER6_PME_PM_MRK_INST_TIMEO ] = { .pme_name = "PM_MRK_INST_TIMEO", .pme_code = 0x40003e, .pme_short_desc = "Marked Instruction finish timeout ", .pme_long_desc = "Marked Instruction finish timeout ", }, [ POWER6_PME_PM_DPU_WT ] = { .pme_name = "PM_DPU_WT", .pme_code = 0x300004, .pme_short_desc = "Cycles DISP unit is stalled waiting for instructions", .pme_long_desc = "Cycles DISP unit is stalled waiting for instructions", }, [ POWER6_PME_PM_DPU_HELD_RESTART ] = { .pme_name = "PM_DPU_HELD_RESTART", .pme_code = 0x30086, .pme_short_desc = "DISP unit held after restart coming", .pme_long_desc = "DISP unit held after restart coming", }, [ POWER6_PME_PM_IERAT_MISS ] = { .pme_name = "PM_IERAT_MISS", .pme_code = 0x420ce, .pme_short_desc = "IERAT miss count", .pme_long_desc = "IERAT miss count", }, [ POWER6_PME_PM_FPU_SINGLE ] = { .pme_name = "PM_FPU_SINGLE", .pme_code = 0x4c1030, .pme_short_desc = "FPU executed single precision instruction", .pme_long_desc = "FPU is executing single precision instruction. Combined Unit 0 + Unit 1", }, [ POWER6_PME_PM_MRK_PTEG_FROM_LMEM ] = { .pme_name = "PM_MRK_PTEG_FROM_LMEM", .pme_code = 0x412042, .pme_short_desc = "Marked PTEG loaded from local memory", .pme_long_desc = "Marked PTEG loaded from local memory", }, [ POWER6_PME_PM_HV_COUNT ] = { .pme_name = "PM_HV_COUNT", .pme_code = 0x200017, .pme_short_desc = "Hypervisor Periods", .pme_long_desc = "Periods when the processor is executing in Hypervisor (MSR[HV] = 1 and MSR[PR]=0)", }, [ POWER6_PME_PM_L2SA_ST_HIT ] = { .pme_name = "PM_L2SA_ST_HIT", .pme_code = 0x50786, .pme_short_desc = "L2 slice A store hits", .pme_long_desc = "A store request made from the core hit in the L2 directory. This event is provided on each of the three L2 slices A,B, and C.", }, [ POWER6_PME_PM_L2_LD_MISS_INST ] = { .pme_name = "PM_L2_LD_MISS_INST", .pme_code = 0x250530, .pme_short_desc = "L2 instruction load misses", .pme_long_desc = "L2 instruction load misses", }, [ POWER6_PME_PM_EXT_INT ] = { .pme_name = "PM_EXT_INT", .pme_code = 0x2000f8, .pme_short_desc = "External interrupts", .pme_long_desc = "An external interrupt occurred", }, [ POWER6_PME_PM_LSU1_LDF ] = { .pme_name = "PM_LSU1_LDF", .pme_code = 0x8008c, .pme_short_desc = "LSU1 executed Floating Point load instruction", .pme_long_desc = "A floating point load was executed from LSU unit 1", }, [ POWER6_PME_PM_FAB_CMD_ISSUED ] = { .pme_name = "PM_FAB_CMD_ISSUED", .pme_code = 0x150130, .pme_short_desc = "Fabric command issued", .pme_long_desc = "Fabric command issued", }, [ POWER6_PME_PM_PTEG_FROM_L21 ] = { .pme_name = "PM_PTEG_FROM_L21", .pme_code = 0x213048, .pme_short_desc = "PTEG loaded from private L2 other core", .pme_long_desc = "PTEG loaded from private L2 other core", }, [ POWER6_PME_PM_L2SA_MISS ] = { .pme_name = "PM_L2SA_MISS", .pme_code = 0x50584, .pme_short_desc = "L2 slice A misses", .pme_long_desc = "L2 slice A misses", }, [ POWER6_PME_PM_PTEG_FROM_RL2L3_MOD ] = { .pme_name = "PM_PTEG_FROM_RL2L3_MOD", .pme_code = 0x11304c, .pme_short_desc = "PTEG loaded from remote L2 or L3 modified", .pme_long_desc = "PTEG loaded from remote L2 or L3 modified", }, [ POWER6_PME_PM_DPU_WT_COUNT ] = { .pme_name = "PM_DPU_WT_COUNT", .pme_code = 0x300005, .pme_short_desc = "Periods DISP unit is stalled waiting for instructions", .pme_long_desc = "Periods DISP unit is stalled waiting for instructions", }, [ POWER6_PME_PM_MRK_PTEG_FROM_L25_MOD ] = { .pme_name = "PM_MRK_PTEG_FROM_L25_MOD", .pme_code = 0x312046, .pme_short_desc = "Marked PTEG loaded from L2.5 modified", .pme_long_desc = "Marked PTEG loaded from L2.5 modified", }, [ POWER6_PME_PM_LD_HIT_L2 ] = { .pme_name = "PM_LD_HIT_L2", .pme_code = 0x250730, .pme_short_desc = "L2 D cache load hits", .pme_long_desc = "L2 D cache load hits", }, [ POWER6_PME_PM_PTEG_FROM_DL2L3_SHR ] = { .pme_name = "PM_PTEG_FROM_DL2L3_SHR", .pme_code = 0x31304c, .pme_short_desc = "PTEG loaded from distant L2 or L3 shared", .pme_long_desc = "PTEG loaded from distant L2 or L3 shared", }, [ POWER6_PME_PM_MEM_DP_RQ_GLOB_LOC ] = { .pme_name = "PM_MEM_DP_RQ_GLOB_LOC", .pme_code = 0x150230, .pme_short_desc = "Memory read queue marking cache line double pump state from global to local", .pme_long_desc = "Memory read queue marking cache line double pump state from global to local", }, [ POWER6_PME_PM_L3SA_MISS ] = { .pme_name = "PM_L3SA_MISS", .pme_code = 0x50084, .pme_short_desc = "L3 slice A misses", .pme_long_desc = "L3 slice A misses", }, [ POWER6_PME_PM_NO_ITAG_COUNT ] = { .pme_name = "PM_NO_ITAG_COUNT", .pme_code = 0x40089, .pme_short_desc = "Periods no ITAG available", .pme_long_desc = "Periods no ITAG available", }, [ POWER6_PME_PM_DSLB_MISS ] = { .pme_name = "PM_DSLB_MISS", .pme_code = 0x830e8, .pme_short_desc = "Data SLB misses", .pme_long_desc = "A SLB miss for a data request occurred. SLB misses trap to the operating system to resolve", }, [ POWER6_PME_PM_LSU_FLUSH_ALIGN ] = { .pme_name = "PM_LSU_FLUSH_ALIGN", .pme_code = 0x220cc, .pme_short_desc = "Flush caused by alignement exception", .pme_long_desc = "Flush caused by alignement exception", }, [ POWER6_PME_PM_DPU_HELD_FPU_CR ] = { .pme_name = "PM_DPU_HELD_FPU_CR", .pme_code = 0x210a0, .pme_short_desc = "DISP unit held due to FPU updating CR", .pme_long_desc = "DISP unit held due to FPU updating CR", }, [ POWER6_PME_PM_PTEG_FROM_L2MISS ] = { .pme_name = "PM_PTEG_FROM_L2MISS", .pme_code = 0x113028, .pme_short_desc = "PTEG loaded from L2 miss", .pme_long_desc = "PTEG loaded from L2 miss", }, [ POWER6_PME_PM_MRK_DATA_FROM_DMEM ] = { .pme_name = "PM_MRK_DATA_FROM_DMEM", .pme_code = 0x20304a, .pme_short_desc = "Marked data loaded from distant memory", .pme_long_desc = "Marked data loaded from distant memory", }, [ POWER6_PME_PM_PTEG_FROM_LMEM ] = { .pme_name = "PM_PTEG_FROM_LMEM", .pme_code = 0x41304a, .pme_short_desc = "PTEG loaded from local memory", .pme_long_desc = "PTEG loaded from local memory", }, [ POWER6_PME_PM_MRK_DERAT_REF_64K ] = { .pme_name = "PM_MRK_DERAT_REF_64K", .pme_code = 0x182044, .pme_short_desc = "Marked DERAT reference for 64K page", .pme_long_desc = "Marked DERAT reference for 64K page", }, [ POWER6_PME_PM_L2SA_LD_REQ_INST ] = { .pme_name = "PM_L2SA_LD_REQ_INST", .pme_code = 0x50580, .pme_short_desc = "L2 slice A instruction load requests", .pme_long_desc = "L2 slice A instruction load requests", }, [ POWER6_PME_PM_MRK_DERAT_MISS_16M ] = { .pme_name = "PM_MRK_DERAT_MISS_16M", .pme_code = 0x392044, .pme_short_desc = "Marked DERAT misses for 16M page", .pme_long_desc = "A marked data request (load or store) missed the ERAT for 16M page and resulted in an ERAT reload.", }, [ POWER6_PME_PM_DATA_FROM_DL2L3_MOD ] = { .pme_name = "PM_DATA_FROM_DL2L3_MOD", .pme_code = 0x40005c, .pme_short_desc = "Data loaded from distant L2 or L3 modified", .pme_long_desc = "Data loaded from distant L2 or L3 modified", }, [ POWER6_PME_PM_FPU0_FXMULT ] = { .pme_name = "PM_FPU0_FXMULT", .pme_code = 0xd0086, .pme_short_desc = "FPU0 executed fixed point multiplication", .pme_long_desc = "FPU0 executed fixed point multiplication", }, [ POWER6_PME_PM_L3SB_MISS ] = { .pme_name = "PM_L3SB_MISS", .pme_code = 0x5008c, .pme_short_desc = "L3 slice B misses", .pme_long_desc = "L3 slice B misses", }, [ POWER6_PME_PM_STCX_CANCEL ] = { .pme_name = "PM_STCX_CANCEL", .pme_code = 0x830ec, .pme_short_desc = "stcx cancel by core", .pme_long_desc = "stcx cancel by core", }, [ POWER6_PME_PM_L2SA_LD_MISS_DATA ] = { .pme_name = "PM_L2SA_LD_MISS_DATA", .pme_code = 0x50482, .pme_short_desc = "L2 slice A data load misses", .pme_long_desc = "L2 slice A data load misses", }, [ POWER6_PME_PM_IC_INV_L2 ] = { .pme_name = "PM_IC_INV_L2", .pme_code = 0x250632, .pme_short_desc = "L1 I cache entries invalidated from L2", .pme_long_desc = "L1 I cache entries invalidated from L2", }, [ POWER6_PME_PM_DPU_HELD ] = { .pme_name = "PM_DPU_HELD", .pme_code = 0x200004, .pme_short_desc = "DISP unit held", .pme_long_desc = "DISP unit held", }, [ POWER6_PME_PM_PMC1_OVERFLOW ] = { .pme_name = "PM_PMC1_OVERFLOW", .pme_code = 0x200014, .pme_short_desc = "PMC1 Overflow", .pme_long_desc = "PMC1 Overflow", }, [ POWER6_PME_PM_THRD_PRIO_6_CYC ] = { .pme_name = "PM_THRD_PRIO_6_CYC", .pme_code = 0x222046, .pme_short_desc = "Cycles thread running at priority level 6", .pme_long_desc = "Cycles thread running at priority level 6", }, [ POWER6_PME_PM_MRK_PTEG_FROM_L3MISS ] = { .pme_name = "PM_MRK_PTEG_FROM_L3MISS", .pme_code = 0x312054, .pme_short_desc = "Marked PTEG loaded from L3 miss", .pme_long_desc = "Marked PTEG loaded from L3 miss", }, [ POWER6_PME_PM_MRK_LSU0_REJECT_UST ] = { .pme_name = "PM_MRK_LSU0_REJECT_UST", .pme_code = 0x930e2, .pme_short_desc = "LSU0 marked unaligned store reject", .pme_long_desc = "LSU0 marked unaligned store reject", }, [ POWER6_PME_PM_MRK_INST_DISP ] = { .pme_name = "PM_MRK_INST_DISP", .pme_code = 0x10001a, .pme_short_desc = "Marked instruction dispatched", .pme_long_desc = "Marked instruction dispatched", }, [ POWER6_PME_PM_LARX ] = { .pme_name = "PM_LARX", .pme_code = 0x830ea, .pme_short_desc = "Larx executed", .pme_long_desc = "Larx executed", }, [ POWER6_PME_PM_INST_CMPL ] = { .pme_name = "PM_INST_CMPL", .pme_code = 0x2, .pme_short_desc = "Instructions completed", .pme_long_desc = "Number of PPC instructions completed. ", }, [ POWER6_PME_PM_FXU_IDLE ] = { .pme_name = "PM_FXU_IDLE", .pme_code = 0x100050, .pme_short_desc = "FXU idle", .pme_long_desc = "FXU0 and FXU1 are both idle", }, [ POWER6_PME_PM_MRK_DATA_FROM_DL2L3_MOD ] = { .pme_name = "PM_MRK_DATA_FROM_DL2L3_MOD", .pme_code = 0x40304c, .pme_short_desc = "Marked data loaded from distant L2 or L3 modified", .pme_long_desc = "Marked data loaded from distant L2 or L3 modified", }, [ POWER6_PME_PM_L2_LD_REQ_DATA ] = { .pme_name = "PM_L2_LD_REQ_DATA", .pme_code = 0x150430, .pme_short_desc = "L2 data load requests", .pme_long_desc = "L2 data load requests", }, [ POWER6_PME_PM_LSU_DERAT_MISS_CYC ] = { .pme_name = "PM_LSU_DERAT_MISS_CYC", .pme_code = 0x1000fc, .pme_short_desc = "DERAT miss latency", .pme_long_desc = "DERAT miss latency", }, [ POWER6_PME_PM_DPU_HELD_POWER_COUNT ] = { .pme_name = "PM_DPU_HELD_POWER_COUNT", .pme_code = 0x20003d, .pme_short_desc = "Periods DISP unit held due to Power Management", .pme_long_desc = "Periods DISP unit held due to Power Management", }, [ POWER6_PME_PM_INST_FROM_RL2L3_MOD ] = { .pme_name = "PM_INST_FROM_RL2L3_MOD", .pme_code = 0x142044, .pme_short_desc = "Instruction fetched from remote L2 or L3 modified", .pme_long_desc = "Instruction fetched from remote L2 or L3 modified", }, [ POWER6_PME_PM_DATA_FROM_DMEM_CYC ] = { .pme_name = "PM_DATA_FROM_DMEM_CYC", .pme_code = 0x20002e, .pme_short_desc = "Load latency from distant memory", .pme_long_desc = "Load latency from distant memory", }, [ POWER6_PME_PM_DATA_FROM_DMEM ] = { .pme_name = "PM_DATA_FROM_DMEM", .pme_code = 0x20005e, .pme_short_desc = "Data loaded from distant memory", .pme_long_desc = "Data loaded from distant memory", }, [ POWER6_PME_PM_LSU_REJECT_PARTIAL_SECTOR ] = { .pme_name = "PM_LSU_REJECT_PARTIAL_SECTOR", .pme_code = 0x1a0032, .pme_short_desc = "LSU reject due to partial sector valid", .pme_long_desc = "LSU reject due to partial sector valid", }, [ POWER6_PME_PM_LSU_REJECT_DERAT_MPRED ] = { .pme_name = "PM_LSU_REJECT_DERAT_MPRED", .pme_code = 0x2a0030, .pme_short_desc = "LSU reject due to mispredicted DERAT", .pme_long_desc = "LSU reject due to mispredicted DERAT", }, [ POWER6_PME_PM_LSU1_REJECT_ULD ] = { .pme_name = "PM_LSU1_REJECT_ULD", .pme_code = 0x90088, .pme_short_desc = "LSU1 unaligned load reject", .pme_long_desc = "LSU1 unaligned load reject", }, [ POWER6_PME_PM_DATA_FROM_L3_CYC ] = { .pme_name = "PM_DATA_FROM_L3_CYC", .pme_code = 0x200022, .pme_short_desc = "Load latency from L3", .pme_long_desc = "Load latency from L3", }, [ POWER6_PME_PM_FXU1_BUSY_FXU0_IDLE ] = { .pme_name = "PM_FXU1_BUSY_FXU0_IDLE", .pme_code = 0x400050, .pme_short_desc = "FXU1 busy FXU0 idle", .pme_long_desc = "FXU0 was idle while FXU1 was busy", }, [ POWER6_PME_PM_INST_FROM_MEM_DP ] = { .pme_name = "PM_INST_FROM_MEM_DP", .pme_code = 0x142042, .pme_short_desc = "Instruction fetched from double pump memory", .pme_long_desc = "Instruction fetched from double pump memory", }, [ POWER6_PME_PM_LSU_FLUSH_DSI ] = { .pme_name = "PM_LSU_FLUSH_DSI", .pme_code = 0x220ce, .pme_short_desc = "Flush caused by DSI", .pme_long_desc = "Flush caused by DSI", }, [ POWER6_PME_PM_MRK_DERAT_REF_16G ] = { .pme_name = "PM_MRK_DERAT_REF_16G", .pme_code = 0x482044, .pme_short_desc = "Marked DERAT reference for 16G page", .pme_long_desc = "Marked DERAT reference for 16G page", }, [ POWER6_PME_PM_LSU_LDF_BOTH ] = { .pme_name = "PM_LSU_LDF_BOTH", .pme_code = 0x180038, .pme_short_desc = "Both LSU units executed Floating Point load instruction", .pme_long_desc = "Both LSU units executed Floating Point load instruction", }, [ POWER6_PME_PM_FPU1_1FLOP ] = { .pme_name = "PM_FPU1_1FLOP", .pme_code = 0xc0088, .pme_short_desc = "FPU1 executed add, mult, sub, cmp or sel instruction", .pme_long_desc = "This signal is active for one cycle when fp1 is executing an add, mult, sub, compare, or fsel kind of instruction. This could be fadd*, fmul*, fsub*, fcmp**, fsel where XYZ* means XYZ, XYZs, XYZ., XYZs. and XYZ** means XYZu, XYZo", }, [ POWER6_PME_PM_DATA_FROM_RMEM_CYC ] = { .pme_name = "PM_DATA_FROM_RMEM_CYC", .pme_code = 0x40002c, .pme_short_desc = "Load latency from remote memory", .pme_long_desc = "Load latency from remote memory", }, [ POWER6_PME_PM_INST_PTEG_SECONDARY ] = { .pme_name = "PM_INST_PTEG_SECONDARY", .pme_code = 0x910ac, .pme_short_desc = "Instruction table walk matched in secondary PTEG", .pme_long_desc = "Instruction table walk matched in secondary PTEG", }, [ POWER6_PME_PM_L1_ICACHE_MISS ] = { .pme_name = "PM_L1_ICACHE_MISS", .pme_code = 0x100056, .pme_short_desc = "L1 I cache miss count", .pme_long_desc = "L1 I cache miss count", }, [ POWER6_PME_PM_INST_DISP_LLA ] = { .pme_name = "PM_INST_DISP_LLA", .pme_code = 0x310a2, .pme_short_desc = "Instruction dispatched under load look ahead", .pme_long_desc = "Instruction dispatched under load look ahead", }, [ POWER6_PME_PM_THRD_BOTH_RUN_CYC ] = { .pme_name = "PM_THRD_BOTH_RUN_CYC", .pme_code = 0x400004, .pme_short_desc = "Both threads in run cycles", .pme_long_desc = "Both threads in run cycles", }, [ POWER6_PME_PM_LSU_ST_CHAINED ] = { .pme_name = "PM_LSU_ST_CHAINED", .pme_code = 0x820ce, .pme_short_desc = "number of chained stores", .pme_long_desc = "number of chained stores", }, [ POWER6_PME_PM_FPU1_FXDIV ] = { .pme_name = "PM_FPU1_FXDIV", .pme_code = 0xc10a8, .pme_short_desc = "FPU1 executed fixed point division", .pme_long_desc = "FPU1 executed fixed point division", }, [ POWER6_PME_PM_FREQ_UP ] = { .pme_name = "PM_FREQ_UP", .pme_code = 0x40003c, .pme_short_desc = "Frequency is being slewed up due to Power Management", .pme_long_desc = "Frequency is being slewed up due to Power Management", }, [ POWER6_PME_PM_FAB_RETRY_SYS_PUMP ] = { .pme_name = "PM_FAB_RETRY_SYS_PUMP", .pme_code = 0x50182, .pme_short_desc = "Retry of a system pump, locally mastered ", .pme_long_desc = "Retry of a system pump, locally mastered ", }, [ POWER6_PME_PM_DATA_FROM_LMEM ] = { .pme_name = "PM_DATA_FROM_LMEM", .pme_code = 0x40005e, .pme_short_desc = "Data loaded from local memory", .pme_long_desc = "Data loaded from local memory", }, [ POWER6_PME_PM_PMC3_OVERFLOW ] = { .pme_name = "PM_PMC3_OVERFLOW", .pme_code = 0x400014, .pme_short_desc = "PMC3 Overflow", .pme_long_desc = "PMC3 Overflow", }, [ POWER6_PME_PM_LSU0_REJECT_SET_MPRED ] = { .pme_name = "PM_LSU0_REJECT_SET_MPRED", .pme_code = 0xa0084, .pme_short_desc = "LSU0 reject due to mispredicted set", .pme_long_desc = "LSU0 reject due to mispredicted set", }, [ POWER6_PME_PM_LSU0_REJECT_DERAT_MPRED ] = { .pme_name = "PM_LSU0_REJECT_DERAT_MPRED", .pme_code = 0xa0082, .pme_short_desc = "LSU0 reject due to mispredicted DERAT", .pme_long_desc = "LSU0 reject due to mispredicted DERAT", }, [ POWER6_PME_PM_LSU1_REJECT_STQ_FULL ] = { .pme_name = "PM_LSU1_REJECT_STQ_FULL", .pme_code = 0xa0088, .pme_short_desc = "LSU1 reject due to store queue full", .pme_long_desc = "LSU1 reject due to store queue full", }, [ POWER6_PME_PM_MRK_BR_MPRED ] = { .pme_name = "PM_MRK_BR_MPRED", .pme_code = 0x300052, .pme_short_desc = "Marked branch mispredicted", .pme_long_desc = "Marked branch mispredicted", }, [ POWER6_PME_PM_L2SA_ST_MISS ] = { .pme_name = "PM_L2SA_ST_MISS", .pme_code = 0x50486, .pme_short_desc = "L2 slice A store misses", .pme_long_desc = "L2 slice A store misses", }, [ POWER6_PME_PM_LSU0_REJECT_EXTERN ] = { .pme_name = "PM_LSU0_REJECT_EXTERN", .pme_code = 0xa10a4, .pme_short_desc = "LSU0 external reject request ", .pme_long_desc = "LSU0 external reject request ", }, [ POWER6_PME_PM_MRK_BR_TAKEN ] = { .pme_name = "PM_MRK_BR_TAKEN", .pme_code = 0x100052, .pme_short_desc = "Marked branch taken", .pme_long_desc = "Marked branch taken", }, [ POWER6_PME_PM_ISLB_MISS ] = { .pme_name = "PM_ISLB_MISS", .pme_code = 0x830e0, .pme_short_desc = "Instruction SLB misses", .pme_long_desc = "A SLB miss for an instruction fetch as occurred", }, [ POWER6_PME_PM_CYC ] = { .pme_name = "PM_CYC", .pme_code = 0x1e, .pme_short_desc = "Processor cycles", .pme_long_desc = "Processor cycles", }, [ POWER6_PME_PM_FPU_FXDIV ] = { .pme_name = "PM_FPU_FXDIV", .pme_code = 0x1c1034, .pme_short_desc = "FPU executed fixed point division", .pme_long_desc = "FPU executed fixed point division", }, [ POWER6_PME_PM_DPU_HELD_LLA_END ] = { .pme_name = "PM_DPU_HELD_LLA_END", .pme_code = 0x30084, .pme_short_desc = "DISP unit held due to load look ahead ended", .pme_long_desc = "DISP unit held due to load look ahead ended", }, [ POWER6_PME_PM_MEM0_DP_CL_WR_LOC ] = { .pme_name = "PM_MEM0_DP_CL_WR_LOC", .pme_code = 0x50286, .pme_short_desc = "cacheline write setting dp to local side 0", .pme_long_desc = "cacheline write setting dp to local side 0", }, [ POWER6_PME_PM_MRK_LSU_REJECT_ULD ] = { .pme_name = "PM_MRK_LSU_REJECT_ULD", .pme_code = 0x193034, .pme_short_desc = "Marked unaligned load reject", .pme_long_desc = "Marked unaligned load reject", }, [ POWER6_PME_PM_1PLUS_PPC_CMPL ] = { .pme_name = "PM_1PLUS_PPC_CMPL", .pme_code = 0x100004, .pme_short_desc = "One or more PPC instruction completed", .pme_long_desc = "A group containing at least one PPC instruction completed. For microcoded instructions that span multiple groups, this will only occur once.", }, [ POWER6_PME_PM_PTEG_FROM_DMEM ] = { .pme_name = "PM_PTEG_FROM_DMEM", .pme_code = 0x21304a, .pme_short_desc = "PTEG loaded from distant memory", .pme_long_desc = "PTEG loaded from distant memory", }, [ POWER6_PME_PM_DPU_WT_BR_MPRED_COUNT ] = { .pme_name = "PM_DPU_WT_BR_MPRED_COUNT", .pme_code = 0x40000d, .pme_short_desc = "Periods DISP unit is stalled due to branch misprediction", .pme_long_desc = "Periods DISP unit is stalled due to branch misprediction", }, [ POWER6_PME_PM_GCT_FULL_CYC ] = { .pme_name = "PM_GCT_FULL_CYC", .pme_code = 0x40086, .pme_short_desc = "Cycles GCT full", .pme_long_desc = "The ISU sends a signal indicating the gct is full. ", }, [ POWER6_PME_PM_INST_FROM_L25_SHR ] = { .pme_name = "PM_INST_FROM_L25_SHR", .pme_code = 0x442046, .pme_short_desc = "Instruction fetched from L2.5 shared", .pme_long_desc = "Instruction fetched from L2.5 shared", }, [ POWER6_PME_PM_MRK_DERAT_MISS_4K ] = { .pme_name = "PM_MRK_DERAT_MISS_4K", .pme_code = 0x292044, .pme_short_desc = "Marked DERAT misses for 4K page", .pme_long_desc = "A marked data request (load or store) missed the ERAT for 4K page and resulted in an ERAT reload.", }, [ POWER6_PME_PM_DC_PREF_STREAM_ALLOC ] = { .pme_name = "PM_DC_PREF_STREAM_ALLOC", .pme_code = 0x810a2, .pme_short_desc = "D cache new prefetch stream allocated", .pme_long_desc = "A new Prefetch Stream was allocated", }, [ POWER6_PME_PM_FPU1_FIN ] = { .pme_name = "PM_FPU1_FIN", .pme_code = 0xd0088, .pme_short_desc = "FPU1 produced a result", .pme_long_desc = "fp1 finished, produced a result. This only indicates finish, not completion. ", }, [ POWER6_PME_PM_BR_MPRED_TA ] = { .pme_name = "PM_BR_MPRED_TA", .pme_code = 0x410ac, .pme_short_desc = "Branch mispredictions due to target address", .pme_long_desc = "branch miss predict due to a target address prediction. This signal will be asserted each time the branch execution unit detects an incorrect target address prediction. This signal will be asserted after a valid branch execution unit issue and will cause a branch mispredict flush unless a flush is detected from an older instruction.", }, [ POWER6_PME_PM_DPU_HELD_POWER ] = { .pme_name = "PM_DPU_HELD_POWER", .pme_code = 0x20003c, .pme_short_desc = "DISP unit held due to Power Management", .pme_long_desc = "DISP unit held due to Power Management", }, [ POWER6_PME_PM_RUN_INST_CMPL ] = { .pme_name = "PM_RUN_INST_CMPL", .pme_code = 0x500009, .pme_short_desc = "Run instructions completed", .pme_long_desc = "Number of run instructions completed. ", }, [ POWER6_PME_PM_GCT_EMPTY_CYC ] = { .pme_name = "PM_GCT_EMPTY_CYC", .pme_code = 0x1000f8, .pme_short_desc = "Cycles GCT empty", .pme_long_desc = "The Global Completion Table is completely empty", }, [ POWER6_PME_PM_LLA_COUNT ] = { .pme_name = "PM_LLA_COUNT", .pme_code = 0xc01f, .pme_short_desc = "Transitions into Load Look Ahead mode", .pme_long_desc = "Transitions into Load Look Ahead mode", }, [ POWER6_PME_PM_LSU0_REJECT_NO_SCRATCH ] = { .pme_name = "PM_LSU0_REJECT_NO_SCRATCH", .pme_code = 0xa10a2, .pme_short_desc = "LSU0 reject due to scratch register not available", .pme_long_desc = "LSU0 reject due to scratch register not available", }, [ POWER6_PME_PM_DPU_WT_IC_MISS ] = { .pme_name = "PM_DPU_WT_IC_MISS", .pme_code = 0x20000c, .pme_short_desc = "Cycles DISP unit is stalled due to I cache miss", .pme_long_desc = "Cycles DISP unit is stalled due to I cache miss", }, [ POWER6_PME_PM_DATA_FROM_L3MISS ] = { .pme_name = "PM_DATA_FROM_L3MISS", .pme_code = 0x3000fe, .pme_short_desc = "Data loaded from private L3 miss", .pme_long_desc = "Data loaded from private L3 miss", }, [ POWER6_PME_PM_FPU_FPSCR ] = { .pme_name = "PM_FPU_FPSCR", .pme_code = 0x2d0032, .pme_short_desc = "FPU executed FPSCR instruction", .pme_long_desc = "FPU executed FPSCR instruction", }, [ POWER6_PME_PM_VMX1_INST_ISSUED ] = { .pme_name = "PM_VMX1_INST_ISSUED", .pme_code = 0x60088, .pme_short_desc = "VMX1 instruction issued", .pme_long_desc = "VMX1 instruction issued", }, [ POWER6_PME_PM_FLUSH ] = { .pme_name = "PM_FLUSH", .pme_code = 0x100010, .pme_short_desc = "Flushes", .pme_long_desc = "Flushes", }, [ POWER6_PME_PM_ST_HIT_L2 ] = { .pme_name = "PM_ST_HIT_L2", .pme_code = 0x150732, .pme_short_desc = "L2 D cache store hits", .pme_long_desc = "L2 D cache store hits", }, [ POWER6_PME_PM_SYNC_CYC ] = { .pme_name = "PM_SYNC_CYC", .pme_code = 0x920cc, .pme_short_desc = "Sync duration", .pme_long_desc = "Sync duration", }, [ POWER6_PME_PM_FAB_SYS_PUMP ] = { .pme_name = "PM_FAB_SYS_PUMP", .pme_code = 0x50180, .pme_short_desc = "System pump operation, locally mastered", .pme_long_desc = "System pump operation, locally mastered", }, [ POWER6_PME_PM_IC_PREF_REQ ] = { .pme_name = "PM_IC_PREF_REQ", .pme_code = 0x4008c, .pme_short_desc = "Instruction prefetch requests", .pme_long_desc = "Asserted when a non-canceled prefetch is made to the cache interface unit (CIU).", }, [ POWER6_PME_PM_MEM0_DP_RQ_GLOB_LOC ] = { .pme_name = "PM_MEM0_DP_RQ_GLOB_LOC", .pme_code = 0x50280, .pme_short_desc = "Memory read queue marking cache line double pump state from global to local side 0", .pme_long_desc = "Memory read queue marking cache line double pump state from global to local side 0", }, [ POWER6_PME_PM_FPU_ISSUE_0 ] = { .pme_name = "PM_FPU_ISSUE_0", .pme_code = 0x320c6, .pme_short_desc = "FPU issue 0 per cycle", .pme_long_desc = "FPU issue 0 per cycle", }, [ POWER6_PME_PM_THRD_PRIO_2_CYC ] = { .pme_name = "PM_THRD_PRIO_2_CYC", .pme_code = 0x322040, .pme_short_desc = "Cycles thread running at priority level 2", .pme_long_desc = "Cycles thread running at priority level 2", }, [ POWER6_PME_PM_VMX_SIMPLE_ISSUED ] = { .pme_name = "PM_VMX_SIMPLE_ISSUED", .pme_code = 0x70082, .pme_short_desc = "VMX instruction issued to simple", .pme_long_desc = "VMX instruction issued to simple", }, [ POWER6_PME_PM_MRK_FPU1_FIN ] = { .pme_name = "PM_MRK_FPU1_FIN", .pme_code = 0xd008a, .pme_short_desc = "Marked instruction FPU1 processing finished", .pme_long_desc = "Marked instruction FPU1 processing finished", }, [ POWER6_PME_PM_DPU_HELD_CW ] = { .pme_name = "PM_DPU_HELD_CW", .pme_code = 0x20084, .pme_short_desc = "DISP unit held due to cache writes ", .pme_long_desc = "DISP unit held due to cache writes ", }, [ POWER6_PME_PM_L3SA_REF ] = { .pme_name = "PM_L3SA_REF", .pme_code = 0x50080, .pme_short_desc = "L3 slice A references", .pme_long_desc = "L3 slice A references", }, [ POWER6_PME_PM_STCX ] = { .pme_name = "PM_STCX", .pme_code = 0x830e6, .pme_short_desc = "STCX executed", .pme_long_desc = "STCX executed", }, [ POWER6_PME_PM_L2SB_MISS ] = { .pme_name = "PM_L2SB_MISS", .pme_code = 0x5058c, .pme_short_desc = "L2 slice B misses", .pme_long_desc = "L2 slice B misses", }, [ POWER6_PME_PM_LSU0_REJECT ] = { .pme_name = "PM_LSU0_REJECT", .pme_code = 0xa10a6, .pme_short_desc = "LSU0 reject", .pme_long_desc = "LSU0 reject", }, [ POWER6_PME_PM_TB_BIT_TRANS ] = { .pme_name = "PM_TB_BIT_TRANS", .pme_code = 0x100026, .pme_short_desc = "Time Base bit transition", .pme_long_desc = "When the selected time base bit (as specified in MMCR0[TBSEL])transitions from 0 to 1 ", }, [ POWER6_PME_PM_THERMAL_MAX ] = { .pme_name = "PM_THERMAL_MAX", .pme_code = 0x30002a, .pme_short_desc = "Processor in thermal MAX", .pme_long_desc = "Processor in thermal MAX", }, [ POWER6_PME_PM_FPU0_STF ] = { .pme_name = "PM_FPU0_STF", .pme_code = 0xc10a4, .pme_short_desc = "FPU0 executed store instruction", .pme_long_desc = "This signal is active for one cycle when fp0 is executing a store instruction.", }, [ POWER6_PME_PM_FPU1_FMA ] = { .pme_name = "PM_FPU1_FMA", .pme_code = 0xc008a, .pme_short_desc = "FPU1 executed multiply-add instruction", .pme_long_desc = "This signal is active for one cycle when fp1 is executing multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs.", }, [ POWER6_PME_PM_LSU1_REJECT_LHS ] = { .pme_name = "PM_LSU1_REJECT_LHS", .pme_code = 0x9008e, .pme_short_desc = "LSU1 load hit store reject", .pme_long_desc = "LSU1 load hit store reject", }, [ POWER6_PME_PM_DPU_HELD_INT ] = { .pme_name = "PM_DPU_HELD_INT", .pme_code = 0x310a8, .pme_short_desc = "DISP unit held due to exception", .pme_long_desc = "DISP unit held due to exception", }, [ POWER6_PME_PM_THRD_LLA_BOTH_CYC ] = { .pme_name = "PM_THRD_LLA_BOTH_CYC", .pme_code = 0x400008, .pme_short_desc = "Both threads in Load Look Ahead", .pme_long_desc = "Both threads in Load Look Ahead", }, [ POWER6_PME_PM_DPU_HELD_THERMAL_COUNT ] = { .pme_name = "PM_DPU_HELD_THERMAL_COUNT", .pme_code = 0x10002b, .pme_short_desc = "Periods DISP unit held due to thermal condition", .pme_long_desc = "Periods DISP unit held due to thermal condition", }, [ POWER6_PME_PM_PMC4_REWIND ] = { .pme_name = "PM_PMC4_REWIND", .pme_code = 0x100020, .pme_short_desc = "PMC4 rewind event", .pme_long_desc = "PMC4 rewind event", }, [ POWER6_PME_PM_DERAT_REF_16M ] = { .pme_name = "PM_DERAT_REF_16M", .pme_code = 0x382070, .pme_short_desc = "DERAT reference for 16M page", .pme_long_desc = "DERAT reference for 16M page", }, [ POWER6_PME_PM_FPU0_FCONV ] = { .pme_name = "PM_FPU0_FCONV", .pme_code = 0xd10a0, .pme_short_desc = "FPU0 executed FCONV instruction", .pme_long_desc = "FPU0 executed FCONV instruction", }, [ POWER6_PME_PM_L2SA_LD_REQ_DATA ] = { .pme_name = "PM_L2SA_LD_REQ_DATA", .pme_code = 0x50480, .pme_short_desc = "L2 slice A data load requests", .pme_long_desc = "L2 slice A data load requests", }, [ POWER6_PME_PM_DATA_FROM_MEM_DP ] = { .pme_name = "PM_DATA_FROM_MEM_DP", .pme_code = 0x10005e, .pme_short_desc = "Data loaded from double pump memory", .pme_long_desc = "Data loaded from double pump memory", }, [ POWER6_PME_PM_MRK_VMX_FLOAT_ISSUED ] = { .pme_name = "PM_MRK_VMX_FLOAT_ISSUED", .pme_code = 0x70088, .pme_short_desc = "Marked VMX instruction issued to float", .pme_long_desc = "Marked VMX instruction issued to float", }, [ POWER6_PME_PM_MRK_PTEG_FROM_L2MISS ] = { .pme_name = "PM_MRK_PTEG_FROM_L2MISS", .pme_code = 0x412054, .pme_short_desc = "Marked PTEG loaded from L2 miss", .pme_long_desc = "Marked PTEG loaded from L2 miss", }, [ POWER6_PME_PM_THRD_PRIO_DIFF_1or2_CYC ] = { .pme_name = "PM_THRD_PRIO_DIFF_1or2_CYC", .pme_code = 0x223040, .pme_short_desc = "Cycles thread priority difference is 1 or 2", .pme_long_desc = "Cycles thread priority difference is 1 or 2", }, [ POWER6_PME_PM_VMX0_STALL ] = { .pme_name = "PM_VMX0_STALL", .pme_code = 0xb0084, .pme_short_desc = "VMX0 stall", .pme_long_desc = "VMX0 stall", }, [ POWER6_PME_PM_IC_DEMAND_L2_BHT_REDIRECT ] = { .pme_name = "PM_IC_DEMAND_L2_BHT_REDIRECT", .pme_code = 0x420ca, .pme_short_desc = "L2 I cache demand request due to BHT redirect", .pme_long_desc = "L2 I cache demand request due to BHT redirect", }, [ POWER6_PME_PM_LSU_DERAT_MISS ] = { .pme_name = "PM_LSU_DERAT_MISS", .pme_code = 0x20000e, .pme_short_desc = "DERAT misses", .pme_long_desc = "Total DERAT Misses (Unit 0 + Unit 1). Requests that miss the Derat are rejected and retried until the request hits in the Erat. This may result in multiple erat misses for the same instruction.", }, [ POWER6_PME_PM_FPU0_SINGLE ] = { .pme_name = "PM_FPU0_SINGLE", .pme_code = 0xc10a6, .pme_short_desc = "FPU0 executed single precision instruction", .pme_long_desc = "This signal is active for one cycle when fp0 is executing single precision instruction.", }, [ POWER6_PME_PM_FPU_ISSUE_STEERING ] = { .pme_name = "PM_FPU_ISSUE_STEERING", .pme_code = 0x320c4, .pme_short_desc = "FPU issue steering", .pme_long_desc = "FPU issue steering", }, [ POWER6_PME_PM_THRD_PRIO_1_CYC ] = { .pme_name = "PM_THRD_PRIO_1_CYC", .pme_code = 0x222040, .pme_short_desc = "Cycles thread running at priority level 1", .pme_long_desc = "Cycles thread running at priority level 1", }, [ POWER6_PME_PM_VMX_COMPLEX_ISSUED ] = { .pme_name = "PM_VMX_COMPLEX_ISSUED", .pme_code = 0x70084, .pme_short_desc = "VMX instruction issued to complex", .pme_long_desc = "VMX instruction issued to complex", }, [ POWER6_PME_PM_FPU_ISSUE_ST_FOLDED ] = { .pme_name = "PM_FPU_ISSUE_ST_FOLDED", .pme_code = 0x320c2, .pme_short_desc = "FPU issue a folded store", .pme_long_desc = "FPU issue a folded store", }, [ POWER6_PME_PM_DFU_FIN ] = { .pme_name = "PM_DFU_FIN", .pme_code = 0xe0080, .pme_short_desc = "DFU instruction finish", .pme_long_desc = "DFU instruction finish", }, [ POWER6_PME_PM_BR_PRED_CCACHE ] = { .pme_name = "PM_BR_PRED_CCACHE", .pme_code = 0x410a4, .pme_short_desc = "Branch count cache prediction", .pme_long_desc = "Branch count cache prediction", }, [ POWER6_PME_PM_MRK_ST_CMPL_INT ] = { .pme_name = "PM_MRK_ST_CMPL_INT", .pme_code = 0x300006, .pme_short_desc = "Marked store completed with intervention", .pme_long_desc = "A marked store previously sent to the memory subsystem completed (data home) after requiring intervention", }, [ POWER6_PME_PM_FAB_MMIO ] = { .pme_name = "PM_FAB_MMIO", .pme_code = 0x50186, .pme_short_desc = "MMIO operation, locally mastered", .pme_long_desc = "MMIO operation, locally mastered", }, [ POWER6_PME_PM_MRK_VMX_SIMPLE_ISSUED ] = { .pme_name = "PM_MRK_VMX_SIMPLE_ISSUED", .pme_code = 0x7008a, .pme_short_desc = "Marked VMX instruction issued to simple", .pme_long_desc = "Marked VMX instruction issued to simple", }, [ POWER6_PME_PM_FPU_STF ] = { .pme_name = "PM_FPU_STF", .pme_code = 0x3c1030, .pme_short_desc = "FPU executed store instruction", .pme_long_desc = "FPU is executing a store instruction. Combined Unit 0 + Unit 1", }, [ POWER6_PME_PM_MEM1_DP_CL_WR_GLOB ] = { .pme_name = "PM_MEM1_DP_CL_WR_GLOB", .pme_code = 0x5028c, .pme_short_desc = "cacheline write setting dp to global side 1", .pme_long_desc = "cacheline write setting dp to global side 1", }, [ POWER6_PME_PM_MRK_DATA_FROM_L3MISS ] = { .pme_name = "PM_MRK_DATA_FROM_L3MISS", .pme_code = 0x303028, .pme_short_desc = "Marked data loaded from L3 miss", .pme_long_desc = "Marked data loaded from L3 miss", }, [ POWER6_PME_PM_GCT_NOSLOT_CYC ] = { .pme_name = "PM_GCT_NOSLOT_CYC", .pme_code = 0x100008, .pme_short_desc = "Cycles no GCT slot allocated", .pme_long_desc = "Cycles this thread does not have any slots allocated in the GCT.", }, [ POWER6_PME_PM_L2_ST_REQ_DATA ] = { .pme_name = "PM_L2_ST_REQ_DATA", .pme_code = 0x250432, .pme_short_desc = "L2 data store requests", .pme_long_desc = "L2 data store requests", }, [ POWER6_PME_PM_INST_TABLEWALK_COUNT ] = { .pme_name = "PM_INST_TABLEWALK_COUNT", .pme_code = 0x920cb, .pme_short_desc = "Periods doing instruction tablewalks", .pme_long_desc = "Periods doing instruction tablewalks", }, [ POWER6_PME_PM_PTEG_FROM_L35_SHR ] = { .pme_name = "PM_PTEG_FROM_L35_SHR", .pme_code = 0x21304e, .pme_short_desc = "PTEG loaded from L3.5 shared", .pme_long_desc = "PTEG loaded from L3.5 shared", }, [ POWER6_PME_PM_DPU_HELD_ISYNC ] = { .pme_name = "PM_DPU_HELD_ISYNC", .pme_code = 0x2008a, .pme_short_desc = "DISP unit held due to ISYNC ", .pme_long_desc = "DISP unit held due to ISYNC ", }, [ POWER6_PME_PM_MRK_DATA_FROM_L25_SHR ] = { .pme_name = "PM_MRK_DATA_FROM_L25_SHR", .pme_code = 0x40304e, .pme_short_desc = "Marked data loaded from L2.5 shared", .pme_long_desc = "DL1 was reloaded with shared (T or SL) data from the L2 of a chip on this MCM due to a marked demand load", }, [ POWER6_PME_PM_L3SA_HIT ] = { .pme_name = "PM_L3SA_HIT", .pme_code = 0x50082, .pme_short_desc = "L3 slice A hits", .pme_long_desc = "L3 slice A hits", }, [ POWER6_PME_PM_DERAT_MISS_16G ] = { .pme_name = "PM_DERAT_MISS_16G", .pme_code = 0x492070, .pme_short_desc = "DERAT misses for 16G page", .pme_long_desc = "A data request (load or store) missed the ERAT for 16G page and resulted in an ERAT reload.", }, [ POWER6_PME_PM_DATA_PTEG_2ND_HALF ] = { .pme_name = "PM_DATA_PTEG_2ND_HALF", .pme_code = 0x910a2, .pme_short_desc = "Data table walk matched in second half pri­mary PTEG", .pme_long_desc = "Data table walk matched in second half pri­mary PTEG", }, [ POWER6_PME_PM_L2SA_ST_REQ ] = { .pme_name = "PM_L2SA_ST_REQ", .pme_code = 0x50484, .pme_short_desc = "L2 slice A store requests", .pme_long_desc = "A store request as seen at the L2 directory has been made from the core. Stores are counted after gathering in the L2 store queues. The event is provided on each of the three slices A,B,and C.", }, [ POWER6_PME_PM_INST_FROM_LMEM ] = { .pme_name = "PM_INST_FROM_LMEM", .pme_code = 0x442042, .pme_short_desc = "Instruction fetched from local memory", .pme_long_desc = "Instruction fetched from local memory", }, [ POWER6_PME_PM_IC_DEMAND_L2_BR_REDIRECT ] = { .pme_name = "PM_IC_DEMAND_L2_BR_REDIRECT", .pme_code = 0x420cc, .pme_short_desc = "L2 I cache demand request due to branch redirect", .pme_long_desc = "L2 I cache demand request due to branch redirect", }, [ POWER6_PME_PM_PTEG_FROM_L2 ] = { .pme_name = "PM_PTEG_FROM_L2", .pme_code = 0x113048, .pme_short_desc = "PTEG loaded from L2", .pme_long_desc = "PTEG loaded from L2", }, [ POWER6_PME_PM_DATA_PTEG_1ST_HALF ] = { .pme_name = "PM_DATA_PTEG_1ST_HALF", .pme_code = 0x910a0, .pme_short_desc = "Data table walk matched in first half primary PTEG", .pme_long_desc = "Data table walk matched in first half primary PTEG", }, [ POWER6_PME_PM_BR_MPRED_COUNT ] = { .pme_name = "PM_BR_MPRED_COUNT", .pme_code = 0x410aa, .pme_short_desc = "Branch misprediction due to count prediction", .pme_long_desc = "Branch misprediction due to count prediction", }, [ POWER6_PME_PM_IERAT_MISS_4K ] = { .pme_name = "PM_IERAT_MISS_4K", .pme_code = 0x492076, .pme_short_desc = "IERAT misses for 4K page", .pme_long_desc = "IERAT misses for 4K page", }, [ POWER6_PME_PM_THRD_BOTH_RUN_COUNT ] = { .pme_name = "PM_THRD_BOTH_RUN_COUNT", .pme_code = 0x400005, .pme_short_desc = "Periods both threads in run cycles", .pme_long_desc = "Periods both threads in run cycles", }, [ POWER6_PME_PM_LSU_REJECT_ULD ] = { .pme_name = "PM_LSU_REJECT_ULD", .pme_code = 0x190030, .pme_short_desc = "Unaligned load reject", .pme_long_desc = "Unaligned load reject", }, [ POWER6_PME_PM_DATA_FROM_DL2L3_MOD_CYC ] = { .pme_name = "PM_DATA_FROM_DL2L3_MOD_CYC", .pme_code = 0x40002a, .pme_short_desc = "Load latency from distant L2 or L3 modified", .pme_long_desc = "Load latency from distant L2 or L3 modified", }, [ POWER6_PME_PM_MRK_PTEG_FROM_RL2L3_MOD ] = { .pme_name = "PM_MRK_PTEG_FROM_RL2L3_MOD", .pme_code = 0x112044, .pme_short_desc = "Marked PTEG loaded from remote L2 or L3 modified", .pme_long_desc = "Marked PTEG loaded from remote L2 or L3 modified", }, [ POWER6_PME_PM_FPU0_FLOP ] = { .pme_name = "PM_FPU0_FLOP", .pme_code = 0xc0086, .pme_short_desc = "FPU0 executed 1FLOP, FMA, FSQRT or FDIV instruction", .pme_long_desc = "FPU0 executed 1FLOP, FMA, FSQRT or FDIV instruction", }, [ POWER6_PME_PM_FPU0_FEST ] = { .pme_name = "PM_FPU0_FEST", .pme_code = 0xd10a6, .pme_short_desc = "FPU0 executed FEST instruction", .pme_long_desc = "This signal is active for one cycle when fp0 is executing one of the estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ. ", }, [ POWER6_PME_PM_MRK_LSU0_REJECT_LHS ] = { .pme_name = "PM_MRK_LSU0_REJECT_LHS", .pme_code = 0x930e6, .pme_short_desc = "LSU0 marked load hit store reject", .pme_long_desc = "LSU0 marked load hit store reject", }, [ POWER6_PME_PM_VMX_RESULT_SAT_1 ] = { .pme_name = "PM_VMX_RESULT_SAT_1", .pme_code = 0xb0086, .pme_short_desc = "VMX valid result with sat=1", .pme_long_desc = "VMX valid result with sat=1", }, [ POWER6_PME_PM_NO_ITAG_CYC ] = { .pme_name = "PM_NO_ITAG_CYC", .pme_code = 0x40088, .pme_short_desc = "Cyles no ITAG available", .pme_long_desc = "Cyles no ITAG available", }, [ POWER6_PME_PM_LSU1_REJECT_NO_SCRATCH ] = { .pme_name = "PM_LSU1_REJECT_NO_SCRATCH", .pme_code = 0xa10aa, .pme_short_desc = "LSU1 reject due to scratch register not available", .pme_long_desc = "LSU1 reject due to scratch register not available", }, [ POWER6_PME_PM_0INST_FETCH ] = { .pme_name = "PM_0INST_FETCH", .pme_code = 0x40080, .pme_short_desc = "No instructions fetched", .pme_long_desc = "No instructions were fetched this cycles (due to IFU hold, redirect, or icache miss)", }, [ POWER6_PME_PM_DPU_WT_BR_MPRED ] = { .pme_name = "PM_DPU_WT_BR_MPRED", .pme_code = 0x40000c, .pme_short_desc = "Cycles DISP unit is stalled due to branch misprediction", .pme_long_desc = "Cycles DISP unit is stalled due to branch misprediction", }, [ POWER6_PME_PM_L1_PREF ] = { .pme_name = "PM_L1_PREF", .pme_code = 0x810a4, .pme_short_desc = "L1 cache data prefetches", .pme_long_desc = "A request to prefetch data into the L1 was made", }, [ POWER6_PME_PM_VMX_FLOAT_MULTICYCLE ] = { .pme_name = "PM_VMX_FLOAT_MULTICYCLE", .pme_code = 0xb0082, .pme_short_desc = "VMX multi-cycle floating point instruction issued", .pme_long_desc = "VMX multi-cycle floating point instruction issued", }, [ POWER6_PME_PM_DATA_FROM_L25_SHR_CYC ] = { .pme_name = "PM_DATA_FROM_L25_SHR_CYC", .pme_code = 0x200024, .pme_short_desc = "Load latency from L2.5 shared", .pme_long_desc = "Load latency from L2.5 shared", }, [ POWER6_PME_PM_DATA_FROM_L3 ] = { .pme_name = "PM_DATA_FROM_L3", .pme_code = 0x300058, .pme_short_desc = "Data loaded from L3", .pme_long_desc = "DL1 was reloaded from the local L3 due to a demand load", }, [ POWER6_PME_PM_PMC2_OVERFLOW ] = { .pme_name = "PM_PMC2_OVERFLOW", .pme_code = 0x300014, .pme_short_desc = "PMC2 Overflow", .pme_long_desc = "PMC2 Overflow", }, [ POWER6_PME_PM_VMX0_LD_WRBACK ] = { .pme_name = "PM_VMX0_LD_WRBACK", .pme_code = 0x60084, .pme_short_desc = "VMX0 load writeback valid", .pme_long_desc = "VMX0 load writeback valid", }, [ POWER6_PME_PM_FPU0_DENORM ] = { .pme_name = "PM_FPU0_DENORM", .pme_code = 0xc10a2, .pme_short_desc = "FPU0 received denormalized data", .pme_long_desc = "This signal is active for one cycle when one of the operands is denormalized.", }, [ POWER6_PME_PM_INST_FETCH_CYC ] = { .pme_name = "PM_INST_FETCH_CYC", .pme_code = 0x420c8, .pme_short_desc = "Cycles at least 1 instruction fetched", .pme_long_desc = "Asserted each cycle when the IFU sends at least one instruction to the IDU. ", }, [ POWER6_PME_PM_LSU_LDF ] = { .pme_name = "PM_LSU_LDF", .pme_code = 0x280032, .pme_short_desc = "LSU executed Floating Point load instruction", .pme_long_desc = "LSU executed Floating Point load instruction", }, [ POWER6_PME_PM_LSU_REJECT_L2_CORR ] = { .pme_name = "PM_LSU_REJECT_L2_CORR", .pme_code = 0x1a1034, .pme_short_desc = "LSU reject due to L2 correctable error", .pme_long_desc = "LSU reject due to L2 correctable error", }, [ POWER6_PME_PM_DERAT_REF_64K ] = { .pme_name = "PM_DERAT_REF_64K", .pme_code = 0x282070, .pme_short_desc = "DERAT reference for 64K page", .pme_long_desc = "DERAT reference for 64K page", }, [ POWER6_PME_PM_THRD_PRIO_3_CYC ] = { .pme_name = "PM_THRD_PRIO_3_CYC", .pme_code = 0x422040, .pme_short_desc = "Cycles thread running at priority level 3", .pme_long_desc = "Cycles thread running at priority level 3", }, [ POWER6_PME_PM_FPU_FMA ] = { .pme_name = "PM_FPU_FMA", .pme_code = 0x2c0030, .pme_short_desc = "FPU executed multiply-add instruction", .pme_long_desc = "This signal is active for one cycle when FPU is executing multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs. Combined Unit 0 + Unit 1", }, [ POWER6_PME_PM_INST_FROM_L35_MOD ] = { .pme_name = "PM_INST_FROM_L35_MOD", .pme_code = 0x142046, .pme_short_desc = "Instruction fetched from L3.5 modified", .pme_long_desc = "Instruction fetched from L3.5 modified", }, [ POWER6_PME_PM_DFU_CONV ] = { .pme_name = "PM_DFU_CONV", .pme_code = 0xe008e, .pme_short_desc = "DFU convert from fixed op", .pme_long_desc = "DFU convert from fixed op", }, [ POWER6_PME_PM_INST_FROM_L25_MOD ] = { .pme_name = "PM_INST_FROM_L25_MOD", .pme_code = 0x342046, .pme_short_desc = "Instruction fetched from L2.5 modified", .pme_long_desc = "Instruction fetched from L2.5 modified", }, [ POWER6_PME_PM_PTEG_FROM_L35_MOD ] = { .pme_name = "PM_PTEG_FROM_L35_MOD", .pme_code = 0x11304e, .pme_short_desc = "PTEG loaded from L3.5 modified", .pme_long_desc = "PTEG loaded from L3.5 modified", }, [ POWER6_PME_PM_MRK_VMX_ST_ISSUED ] = { .pme_name = "PM_MRK_VMX_ST_ISSUED", .pme_code = 0xb0088, .pme_short_desc = "Marked VMX store issued", .pme_long_desc = "Marked VMX store issued", }, [ POWER6_PME_PM_VMX_FLOAT_ISSUED ] = { .pme_name = "PM_VMX_FLOAT_ISSUED", .pme_code = 0x70080, .pme_short_desc = "VMX instruction issued to float", .pme_long_desc = "VMX instruction issued to float", }, [ POWER6_PME_PM_LSU0_REJECT_L2_CORR ] = { .pme_name = "PM_LSU0_REJECT_L2_CORR", .pme_code = 0xa10a0, .pme_short_desc = "LSU0 reject due to L2 correctable error", .pme_long_desc = "LSU0 reject due to L2 correctable error", }, [ POWER6_PME_PM_THRD_L2MISS ] = { .pme_name = "PM_THRD_L2MISS", .pme_code = 0x310a0, .pme_short_desc = "Thread in L2 miss", .pme_long_desc = "Thread in L2 miss", }, [ POWER6_PME_PM_FPU_FCONV ] = { .pme_name = "PM_FPU_FCONV", .pme_code = 0x1d1034, .pme_short_desc = "FPU executed FCONV instruction", .pme_long_desc = "FPU executed FCONV instruction", }, [ POWER6_PME_PM_FPU_FXMULT ] = { .pme_name = "PM_FPU_FXMULT", .pme_code = 0x1d0032, .pme_short_desc = "FPU executed fixed point multiplication", .pme_long_desc = "FPU executed fixed point multiplication", }, [ POWER6_PME_PM_FPU1_FRSP ] = { .pme_name = "PM_FPU1_FRSP", .pme_code = 0xd10aa, .pme_short_desc = "FPU1 executed FRSP instruction", .pme_long_desc = "FPU1 executed FRSP instruction", }, [ POWER6_PME_PM_MRK_DERAT_REF_16M ] = { .pme_name = "PM_MRK_DERAT_REF_16M", .pme_code = 0x382044, .pme_short_desc = "Marked DERAT reference for 16M page", .pme_long_desc = "Marked DERAT reference for 16M page", }, [ POWER6_PME_PM_L2SB_CASTOUT_SHR ] = { .pme_name = "PM_L2SB_CASTOUT_SHR", .pme_code = 0x5068a, .pme_short_desc = "L2 slice B castouts - Shared", .pme_long_desc = "L2 slice B castouts - Shared", }, [ POWER6_PME_PM_THRD_ONE_RUN_COUNT ] = { .pme_name = "PM_THRD_ONE_RUN_COUNT", .pme_code = 0x1000fb, .pme_short_desc = "Periods one of the threads in run cycles", .pme_long_desc = "Periods one of the threads in run cycles", }, [ POWER6_PME_PM_INST_FROM_RMEM ] = { .pme_name = "PM_INST_FROM_RMEM", .pme_code = 0x342042, .pme_short_desc = "Instruction fetched from remote memory", .pme_long_desc = "Instruction fetched from remote memory", }, [ POWER6_PME_PM_LSU_BOTH_BUS ] = { .pme_name = "PM_LSU_BOTH_BUS", .pme_code = 0x810aa, .pme_short_desc = "Both data return buses busy simultaneously", .pme_long_desc = "Both data return buses busy simultaneously", }, [ POWER6_PME_PM_FPU1_FSQRT_FDIV ] = { .pme_name = "PM_FPU1_FSQRT_FDIV", .pme_code = 0xc008c, .pme_short_desc = "FPU1 executed FSQRT or FDIV instruction", .pme_long_desc = "FPU1 executed FSQRT or FDIV instruction", }, [ POWER6_PME_PM_L2_LD_REQ_INST ] = { .pme_name = "PM_L2_LD_REQ_INST", .pme_code = 0x150530, .pme_short_desc = "L2 instruction load requests", .pme_long_desc = "L2 instruction load requests", }, [ POWER6_PME_PM_MRK_PTEG_FROM_L35_SHR ] = { .pme_name = "PM_MRK_PTEG_FROM_L35_SHR", .pme_code = 0x212046, .pme_short_desc = "Marked PTEG loaded from L3.5 shared", .pme_long_desc = "Marked PTEG loaded from L3.5 shared", }, [ POWER6_PME_PM_BR_PRED_CR ] = { .pme_name = "PM_BR_PRED_CR", .pme_code = 0x410a2, .pme_short_desc = "A conditional branch was predicted, CR prediction", .pme_long_desc = "A conditional branch was predicted, CR prediction", }, [ POWER6_PME_PM_MRK_LSU0_REJECT_ULD ] = { .pme_name = "PM_MRK_LSU0_REJECT_ULD", .pme_code = 0x930e0, .pme_short_desc = "LSU0 marked unaligned load reject", .pme_long_desc = "LSU0 marked unaligned load reject", }, [ POWER6_PME_PM_LSU_REJECT ] = { .pme_name = "PM_LSU_REJECT", .pme_code = 0x4a1030, .pme_short_desc = "LSU reject", .pme_long_desc = "LSU reject", }, [ POWER6_PME_PM_LSU_REJECT_LHS_BOTH ] = { .pme_name = "PM_LSU_REJECT_LHS_BOTH", .pme_code = 0x290038, .pme_short_desc = "Load hit store reject both units", .pme_long_desc = "Load hit store reject both units", }, [ POWER6_PME_PM_GXO_ADDR_CYC_BUSY ] = { .pme_name = "PM_GXO_ADDR_CYC_BUSY", .pme_code = 0x50382, .pme_short_desc = "Outbound GX address utilization (# of cycles address out is valid)", .pme_long_desc = "Outbound GX address utilization (# of cycles address out is valid)", }, [ POWER6_PME_PM_LSU_SRQ_EMPTY_COUNT ] = { .pme_name = "PM_LSU_SRQ_EMPTY_COUNT", .pme_code = 0x40001d, .pme_short_desc = "Periods SRQ empty", .pme_long_desc = "The Store Request Queue is empty", }, [ POWER6_PME_PM_PTEG_FROM_L3 ] = { .pme_name = "PM_PTEG_FROM_L3", .pme_code = 0x313048, .pme_short_desc = "PTEG loaded from L3", .pme_long_desc = "PTEG loaded from L3", }, [ POWER6_PME_PM_VMX0_LD_ISSUED ] = { .pme_name = "PM_VMX0_LD_ISSUED", .pme_code = 0x60082, .pme_short_desc = "VMX0 load issued", .pme_long_desc = "VMX0 load issued", }, [ POWER6_PME_PM_FXU_PIPELINED_MULT_DIV ] = { .pme_name = "PM_FXU_PIPELINED_MULT_DIV", .pme_code = 0x210ae, .pme_short_desc = "Fix point multiply/divide pipelined", .pme_long_desc = "Fix point multiply/divide pipelined", }, [ POWER6_PME_PM_FPU1_STF ] = { .pme_name = "PM_FPU1_STF", .pme_code = 0xc10ac, .pme_short_desc = "FPU1 executed store instruction", .pme_long_desc = "This signal is active for one cycle when fp1 is executing a store instruction.", }, [ POWER6_PME_PM_DFU_ADD ] = { .pme_name = "PM_DFU_ADD", .pme_code = 0xe008c, .pme_short_desc = "DFU add type instruction", .pme_long_desc = "DFU add type instruction", }, [ POWER6_PME_PM_MEM_DP_CL_WR_GLOB ] = { .pme_name = "PM_MEM_DP_CL_WR_GLOB", .pme_code = 0x250232, .pme_short_desc = "cache line write setting double pump state to global", .pme_long_desc = "cache line write setting double pump state to global", }, [ POWER6_PME_PM_MRK_LSU1_REJECT_ULD ] = { .pme_name = "PM_MRK_LSU1_REJECT_ULD", .pme_code = 0x930e8, .pme_short_desc = "LSU1 marked unaligned load reject", .pme_long_desc = "LSU1 marked unaligned load reject", }, [ POWER6_PME_PM_ITLB_REF ] = { .pme_name = "PM_ITLB_REF", .pme_code = 0x920c2, .pme_short_desc = "Instruction TLB reference", .pme_long_desc = "Instruction TLB reference", }, [ POWER6_PME_PM_LSU0_REJECT_L2MISS ] = { .pme_name = "PM_LSU0_REJECT_L2MISS", .pme_code = 0x90084, .pme_short_desc = "LSU0 L2 miss reject", .pme_long_desc = "LSU0 L2 miss reject", }, [ POWER6_PME_PM_DATA_FROM_L35_SHR ] = { .pme_name = "PM_DATA_FROM_L35_SHR", .pme_code = 0x20005a, .pme_short_desc = "Data loaded from L3.5 shared", .pme_long_desc = "Data loaded from L3.5 shared", }, [ POWER6_PME_PM_MRK_DATA_FROM_RL2L3_MOD ] = { .pme_name = "PM_MRK_DATA_FROM_RL2L3_MOD", .pme_code = 0x10304c, .pme_short_desc = "Marked data loaded from remote L2 or L3 modified", .pme_long_desc = "Marked data loaded from remote L2 or L3 modified", }, [ POWER6_PME_PM_FPU0_FPSCR ] = { .pme_name = "PM_FPU0_FPSCR", .pme_code = 0xd0084, .pme_short_desc = "FPU0 executed FPSCR instruction", .pme_long_desc = "This signal is active for one cycle when fp0 is executing fpscr move related instruction. This could be mtfsfi*, mtfsb0*, mtfsb1*. mffs*, mtfsf*, mcrsf* where XYZ* means XYZ, XYZs, XYZ., XYZs", }, [ POWER6_PME_PM_DATA_FROM_L2 ] = { .pme_name = "PM_DATA_FROM_L2", .pme_code = 0x100058, .pme_short_desc = "Data loaded from L2", .pme_long_desc = "DL1 was reloaded from the local L2 due to a demand load", }, [ POWER6_PME_PM_DPU_HELD_XER ] = { .pme_name = "PM_DPU_HELD_XER", .pme_code = 0x20088, .pme_short_desc = "DISP unit held due to XER dependency", .pme_long_desc = "DISP unit held due to XER dependency", }, [ POWER6_PME_PM_FAB_NODE_PUMP ] = { .pme_name = "PM_FAB_NODE_PUMP", .pme_code = 0x50188, .pme_short_desc = "Node pump operation, locally mastered", .pme_long_desc = "Node pump operation, locally mastered", }, [ POWER6_PME_PM_VMX_RESULT_SAT_0_1 ] = { .pme_name = "PM_VMX_RESULT_SAT_0_1", .pme_code = 0xb008e, .pme_short_desc = "VMX valid result with sat bit is set (0->1)", .pme_long_desc = "VMX valid result with sat bit is set (0->1)", }, [ POWER6_PME_PM_LD_REF_L1 ] = { .pme_name = "PM_LD_REF_L1", .pme_code = 0x80082, .pme_short_desc = "L1 D cache load references", .pme_long_desc = "Total DL1 Load references", }, [ POWER6_PME_PM_TLB_REF ] = { .pme_name = "PM_TLB_REF", .pme_code = 0x920c8, .pme_short_desc = "TLB reference", .pme_long_desc = "TLB reference", }, [ POWER6_PME_PM_DC_PREF_OUT_OF_STREAMS ] = { .pme_name = "PM_DC_PREF_OUT_OF_STREAMS", .pme_code = 0x810a0, .pme_short_desc = "D cache out of streams", .pme_long_desc = "out of streams", }, [ POWER6_PME_PM_FLUSH_FPU ] = { .pme_name = "PM_FLUSH_FPU", .pme_code = 0x230ec, .pme_short_desc = "Flush caused by FPU exception", .pme_long_desc = "Flush caused by FPU exception", }, [ POWER6_PME_PM_MEM1_DP_CL_WR_LOC ] = { .pme_name = "PM_MEM1_DP_CL_WR_LOC", .pme_code = 0x5028e, .pme_short_desc = "cacheline write setting dp to local side 1", .pme_long_desc = "cacheline write setting dp to local side 1", }, [ POWER6_PME_PM_L2SB_LD_HIT ] = { .pme_name = "PM_L2SB_LD_HIT", .pme_code = 0x5078a, .pme_short_desc = "L2 slice B load hits", .pme_long_desc = "L2 slice B load hits", }, [ POWER6_PME_PM_FAB_DCLAIM ] = { .pme_name = "PM_FAB_DCLAIM", .pme_code = 0x50184, .pme_short_desc = "Dclaim operation, locally mastered", .pme_long_desc = "Dclaim operation, locally mastered", }, [ POWER6_PME_PM_MEM_DP_CL_WR_LOC ] = { .pme_name = "PM_MEM_DP_CL_WR_LOC", .pme_code = 0x150232, .pme_short_desc = "cache line write setting double pump state to local", .pme_long_desc = "cache line write setting double pump state to local", }, [ POWER6_PME_PM_BR_MPRED_CR ] = { .pme_name = "PM_BR_MPRED_CR", .pme_code = 0x410a8, .pme_short_desc = "Branch mispredictions due to CR bit setting", .pme_long_desc = "This signal is asserted when the branch execution unit detects a branch mispredict because the CR value is opposite of the predicted value. This signal is asserted after a branch issue event and will result in a branch redirect flush if not overridden by a flush of an older instruction.", }, [ POWER6_PME_PM_LSU_REJECT_EXTERN ] = { .pme_name = "PM_LSU_REJECT_EXTERN", .pme_code = 0x3a1030, .pme_short_desc = "LSU external reject request ", .pme_long_desc = "LSU external reject request ", }, [ POWER6_PME_PM_DATA_FROM_RL2L3_MOD ] = { .pme_name = "PM_DATA_FROM_RL2L3_MOD", .pme_code = 0x10005c, .pme_short_desc = "Data loaded from remote L2 or L3 modified", .pme_long_desc = "Data loaded from remote L2 or L3 modified", }, [ POWER6_PME_PM_DPU_HELD_RU_WQ ] = { .pme_name = "PM_DPU_HELD_RU_WQ", .pme_code = 0x2008e, .pme_short_desc = "DISP unit held due to RU FXU write queue full", .pme_long_desc = "DISP unit held due to RU FXU write queue full", }, [ POWER6_PME_PM_LD_MISS_L1 ] = { .pme_name = "PM_LD_MISS_L1", .pme_code = 0x80080, .pme_short_desc = "L1 D cache load misses", .pme_long_desc = "Total DL1 Load references that miss the DL1", }, [ POWER6_PME_PM_DC_INV_L2 ] = { .pme_name = "PM_DC_INV_L2", .pme_code = 0x150632, .pme_short_desc = "L1 D cache entries invalidated from L2", .pme_long_desc = "A dcache invalidated was received from the L2 because a line in L2 was castout.", }, [ POWER6_PME_PM_MRK_PTEG_FROM_RMEM ] = { .pme_name = "PM_MRK_PTEG_FROM_RMEM", .pme_code = 0x312042, .pme_short_desc = "Marked PTEG loaded from remote memory", .pme_long_desc = "Marked PTEG loaded from remote memory", }, [ POWER6_PME_PM_FPU_FIN ] = { .pme_name = "PM_FPU_FIN", .pme_code = 0x1d0030, .pme_short_desc = "FPU produced a result", .pme_long_desc = "FPU finished, produced a result This only indicates finish, not completion. Combined Unit 0 + Unit 1", }, [ POWER6_PME_PM_FXU0_FIN ] = { .pme_name = "PM_FXU0_FIN", .pme_code = 0x300016, .pme_short_desc = "FXU0 produced a result", .pme_long_desc = "The Fixed Point unit 0 finished an instruction and produced a result", }, [ POWER6_PME_PM_DPU_HELD_FPQ ] = { .pme_name = "PM_DPU_HELD_FPQ", .pme_code = 0x20086, .pme_short_desc = "DISP unit held due to FPU issue queue full", .pme_long_desc = "DISP unit held due to FPU issue queue full", }, [ POWER6_PME_PM_GX_DMA_READ ] = { .pme_name = "PM_GX_DMA_READ", .pme_code = 0x5038c, .pme_short_desc = "DMA Read Request", .pme_long_desc = "DMA Read Request", }, [ POWER6_PME_PM_LSU1_REJECT_PARTIAL_SECTOR ] = { .pme_name = "PM_LSU1_REJECT_PARTIAL_SECTOR", .pme_code = 0xa008e, .pme_short_desc = "LSU1 reject due to partial sector valid", .pme_long_desc = "LSU1 reject due to partial sector valid", }, [ POWER6_PME_PM_0INST_FETCH_COUNT ] = { .pme_name = "PM_0INST_FETCH_COUNT", .pme_code = 0x40081, .pme_short_desc = "Periods with no instructions fetched", .pme_long_desc = "No instructions were fetched this periods (due to IFU hold, redirect, or icache miss)", }, [ POWER6_PME_PM_PMC5_OVERFLOW ] = { .pme_name = "PM_PMC5_OVERFLOW", .pme_code = 0x100024, .pme_short_desc = "PMC5 Overflow", .pme_long_desc = "PMC5 Overflow", }, [ POWER6_PME_PM_L2SB_LD_REQ ] = { .pme_name = "PM_L2SB_LD_REQ", .pme_code = 0x50788, .pme_short_desc = "L2 slice B load requests ", .pme_long_desc = "L2 slice B load requests ", }, [ POWER6_PME_PM_THRD_PRIO_DIFF_0_CYC ] = { .pme_name = "PM_THRD_PRIO_DIFF_0_CYC", .pme_code = 0x123040, .pme_short_desc = "Cycles no thread priority difference", .pme_long_desc = "Cycles no thread priority difference", }, [ POWER6_PME_PM_DATA_FROM_RMEM ] = { .pme_name = "PM_DATA_FROM_RMEM", .pme_code = 0x30005e, .pme_short_desc = "Data loaded from remote memory", .pme_long_desc = "Data loaded from remote memory", }, [ POWER6_PME_PM_LSU_LMQ_SRQ_EMPTY_BOTH_CYC ] = { .pme_name = "PM_LSU_LMQ_SRQ_EMPTY_BOTH_CYC", .pme_code = 0x30001c, .pme_short_desc = "Cycles both threads LMQ and SRQ empty", .pme_long_desc = "Cycles both threads LMQ and SRQ empty", }, [ POWER6_PME_PM_ST_REF_L1_BOTH ] = { .pme_name = "PM_ST_REF_L1_BOTH", .pme_code = 0x280038, .pme_short_desc = "Both units L1 D cache store reference", .pme_long_desc = "Both units L1 D cache store reference", }, [ POWER6_PME_PM_VMX_PERMUTE_ISSUED ] = { .pme_name = "PM_VMX_PERMUTE_ISSUED", .pme_code = 0x70086, .pme_short_desc = "VMX instruction issued to permute", .pme_long_desc = "VMX instruction issued to permute", }, [ POWER6_PME_PM_BR_TAKEN ] = { .pme_name = "PM_BR_TAKEN", .pme_code = 0x200052, .pme_short_desc = "Branches taken", .pme_long_desc = "Branches taken", }, [ POWER6_PME_PM_FAB_DMA ] = { .pme_name = "PM_FAB_DMA", .pme_code = 0x5018c, .pme_short_desc = "DMA operation, locally mastered", .pme_long_desc = "DMA operation, locally mastered", }, [ POWER6_PME_PM_GCT_EMPTY_COUNT ] = { .pme_name = "PM_GCT_EMPTY_COUNT", .pme_code = 0x200009, .pme_short_desc = "Periods GCT empty", .pme_long_desc = "The Global Completion Table is completely empty.", }, [ POWER6_PME_PM_FPU1_SINGLE ] = { .pme_name = "PM_FPU1_SINGLE", .pme_code = 0xc10ae, .pme_short_desc = "FPU1 executed single precision instruction", .pme_long_desc = "This signal is active for one cycle when fp1 is executing single precision instruction.", }, [ POWER6_PME_PM_L2SA_CASTOUT_SHR ] = { .pme_name = "PM_L2SA_CASTOUT_SHR", .pme_code = 0x50682, .pme_short_desc = "L2 slice A castouts - Shared", .pme_long_desc = "L2 slice A castouts - Shared", }, [ POWER6_PME_PM_L3SB_REF ] = { .pme_name = "PM_L3SB_REF", .pme_code = 0x50088, .pme_short_desc = "L3 slice B references", .pme_long_desc = "L3 slice B references", }, [ POWER6_PME_PM_FPU0_FRSP ] = { .pme_name = "PM_FPU0_FRSP", .pme_code = 0xd10a2, .pme_short_desc = "FPU0 executed FRSP instruction", .pme_long_desc = "FPU0 executed FRSP instruction", }, [ POWER6_PME_PM_PMC4_SAVED ] = { .pme_name = "PM_PMC4_SAVED", .pme_code = 0x300022, .pme_short_desc = "PMC4 rewind value saved", .pme_long_desc = "PMC4 rewind value saved", }, [ POWER6_PME_PM_L2SA_DC_INV ] = { .pme_name = "PM_L2SA_DC_INV", .pme_code = 0x50686, .pme_short_desc = "L2 slice A D cache invalidate", .pme_long_desc = "L2 slice A D cache invalidate", }, [ POWER6_PME_PM_GXI_ADDR_CYC_BUSY ] = { .pme_name = "PM_GXI_ADDR_CYC_BUSY", .pme_code = 0x50388, .pme_short_desc = "Inbound GX address utilization (# of cycle address is in valid)", .pme_long_desc = "Inbound GX address utilization (# of cycle address is in valid)", }, [ POWER6_PME_PM_FPU0_FMA ] = { .pme_name = "PM_FPU0_FMA", .pme_code = 0xc0082, .pme_short_desc = "FPU0 executed multiply-add instruction", .pme_long_desc = "This signal is active for one cycle when fp0 is executing multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs.", }, [ POWER6_PME_PM_SLB_MISS ] = { .pme_name = "PM_SLB_MISS", .pme_code = 0x183034, .pme_short_desc = "SLB misses", .pme_long_desc = "SLB misses", }, [ POWER6_PME_PM_MRK_ST_GPS ] = { .pme_name = "PM_MRK_ST_GPS", .pme_code = 0x200006, .pme_short_desc = "Marked store sent to GPS", .pme_long_desc = "A sampled store has been sent to the memory subsystem", }, [ POWER6_PME_PM_DERAT_REF_4K ] = { .pme_name = "PM_DERAT_REF_4K", .pme_code = 0x182070, .pme_short_desc = "DERAT reference for 4K page", .pme_long_desc = "DERAT reference for 4K page", }, [ POWER6_PME_PM_L2_CASTOUT_SHR ] = { .pme_name = "PM_L2_CASTOUT_SHR", .pme_code = 0x250630, .pme_short_desc = "L2 castouts - Shared (T, Te, Si, S)", .pme_long_desc = "L2 castouts - Shared (T, Te, Si, S)", }, [ POWER6_PME_PM_DPU_HELD_STCX_CR ] = { .pme_name = "PM_DPU_HELD_STCX_CR", .pme_code = 0x2008c, .pme_short_desc = "DISP unit held due to STCX updating CR ", .pme_long_desc = "DISP unit held due to STCX updating CR ", }, [ POWER6_PME_PM_FPU0_ST_FOLDED ] = { .pme_name = "PM_FPU0_ST_FOLDED", .pme_code = 0xd10a4, .pme_short_desc = "FPU0 folded store", .pme_long_desc = "FPU0 folded store", }, [ POWER6_PME_PM_MRK_DATA_FROM_L21 ] = { .pme_name = "PM_MRK_DATA_FROM_L21", .pme_code = 0x203048, .pme_short_desc = "Marked data loaded from private L2 other core", .pme_long_desc = "Marked data loaded from private L2 other core", }, [ POWER6_PME_PM_THRD_PRIO_DIFF_minus3or4_CYC ] = { .pme_name = "PM_THRD_PRIO_DIFF_minus3or4_CYC", .pme_code = 0x323046, .pme_short_desc = "Cycles thread priority difference is -3 or -4", .pme_long_desc = "Cycles thread priority difference is -3 or -4", }, [ POWER6_PME_PM_DATA_FROM_L35_MOD ] = { .pme_name = "PM_DATA_FROM_L35_MOD", .pme_code = 0x10005a, .pme_short_desc = "Data loaded from L3.5 modified", .pme_long_desc = "Data loaded from L3.5 modified", }, [ POWER6_PME_PM_DATA_FROM_DL2L3_SHR ] = { .pme_name = "PM_DATA_FROM_DL2L3_SHR", .pme_code = 0x30005c, .pme_short_desc = "Data loaded from distant L2 or L3 shared", .pme_long_desc = "Data loaded from distant L2 or L3 shared", }, [ POWER6_PME_PM_GXI_DATA_CYC_BUSY ] = { .pme_name = "PM_GXI_DATA_CYC_BUSY", .pme_code = 0x5038a, .pme_short_desc = "Inbound GX Data utilization (# of cycle data in is valid)", .pme_long_desc = "Inbound GX Data utilization (# of cycle data in is valid)", }, [ POWER6_PME_PM_LSU_REJECT_STEAL ] = { .pme_name = "PM_LSU_REJECT_STEAL", .pme_code = 0x9008c, .pme_short_desc = "LSU reject due to steal", .pme_long_desc = "LSU reject due to steal", }, [ POWER6_PME_PM_ST_FIN ] = { .pme_name = "PM_ST_FIN", .pme_code = 0x100054, .pme_short_desc = "Store instructions finished", .pme_long_desc = "Store instructions finished", }, [ POWER6_PME_PM_DPU_HELD_CR_LOGICAL ] = { .pme_name = "PM_DPU_HELD_CR_LOGICAL", .pme_code = 0x3008e, .pme_short_desc = "DISP unit held due to CR, LR or CTR updated by CR logical, MTCRF, MTLR or MTCTR", .pme_long_desc = "DISP unit held due to CR, LR or CTR updated by CR logical, MTCRF, MTLR or MTCTR", }, [ POWER6_PME_PM_THRD_SEL_T0 ] = { .pme_name = "PM_THRD_SEL_T0", .pme_code = 0x310a6, .pme_short_desc = "Decode selected thread 0", .pme_long_desc = "Decode selected thread 0", }, [ POWER6_PME_PM_PTEG_RELOAD_VALID ] = { .pme_name = "PM_PTEG_RELOAD_VALID", .pme_code = 0x130e8, .pme_short_desc = "TLB reload valid", .pme_long_desc = "TLB reload valid", }, [ POWER6_PME_PM_L2_PREF_ST ] = { .pme_name = "PM_L2_PREF_ST", .pme_code = 0x810a8, .pme_short_desc = "L2 cache prefetches", .pme_long_desc = "L2 cache prefetches", }, [ POWER6_PME_PM_MRK_STCX_FAIL ] = { .pme_name = "PM_MRK_STCX_FAIL", .pme_code = 0x830e4, .pme_short_desc = "Marked STCX failed", .pme_long_desc = "A marked stcx (stwcx or stdcx) failed", }, [ POWER6_PME_PM_LSU0_REJECT_LHS ] = { .pme_name = "PM_LSU0_REJECT_LHS", .pme_code = 0x90086, .pme_short_desc = "LSU0 load hit store reject", .pme_long_desc = "LSU0 load hit store reject", }, [ POWER6_PME_PM_DFU_EXP_EQ ] = { .pme_name = "PM_DFU_EXP_EQ", .pme_code = 0xe0084, .pme_short_desc = "DFU operand exponents are equal for add type", .pme_long_desc = "DFU operand exponents are equal for add type", }, [ POWER6_PME_PM_DPU_HELD_FP_FX_MULT ] = { .pme_name = "PM_DPU_HELD_FP_FX_MULT", .pme_code = 0x210a8, .pme_short_desc = "DISP unit held due to non fixed multiple/divide after fixed multiply/divide", .pme_long_desc = "DISP unit held due to non fixed multiple/divide after fixed multiply/divide", }, [ POWER6_PME_PM_L2_LD_MISS_DATA ] = { .pme_name = "PM_L2_LD_MISS_DATA", .pme_code = 0x250430, .pme_short_desc = "L2 data load misses", .pme_long_desc = "L2 data load misses", }, [ POWER6_PME_PM_DATA_FROM_L35_MOD_CYC ] = { .pme_name = "PM_DATA_FROM_L35_MOD_CYC", .pme_code = 0x400026, .pme_short_desc = "Load latency from L3.5 modified", .pme_long_desc = "Load latency from L3.5 modified", }, [ POWER6_PME_PM_FLUSH_FXU ] = { .pme_name = "PM_FLUSH_FXU", .pme_code = 0x230ea, .pme_short_desc = "Flush caused by FXU exception", .pme_long_desc = "Flush caused by FXU exception", }, [ POWER6_PME_PM_FPU_ISSUE_1 ] = { .pme_name = "PM_FPU_ISSUE_1", .pme_code = 0x320c8, .pme_short_desc = "FPU issue 1 per cycle", .pme_long_desc = "FPU issue 1 per cycle", }, [ POWER6_PME_PM_DATA_FROM_LMEM_CYC ] = { .pme_name = "PM_DATA_FROM_LMEM_CYC", .pme_code = 0x20002c, .pme_short_desc = "Load latency from local memory", .pme_long_desc = "Load latency from local memory", }, [ POWER6_PME_PM_DPU_HELD_LSU_SOPS ] = { .pme_name = "PM_DPU_HELD_LSU_SOPS", .pme_code = 0x30080, .pme_short_desc = "DISP unit held due to LSU slow ops (sync, tlbie, stcx)", .pme_long_desc = "DISP unit held due to LSU slow ops (sync, tlbie, stcx)", }, [ POWER6_PME_PM_INST_PTEG_2ND_HALF ] = { .pme_name = "PM_INST_PTEG_2ND_HALF", .pme_code = 0x910aa, .pme_short_desc = "Instruction table walk matched in second half primary PTEG", .pme_long_desc = "Instruction table walk matched in second half primary PTEG", }, [ POWER6_PME_PM_THRESH_TIMEO ] = { .pme_name = "PM_THRESH_TIMEO", .pme_code = 0x300018, .pme_short_desc = "Threshold timeout", .pme_long_desc = "The threshold timer expired", }, [ POWER6_PME_PM_LSU_REJECT_UST_BOTH ] = { .pme_name = "PM_LSU_REJECT_UST_BOTH", .pme_code = 0x190036, .pme_short_desc = "Unaligned store reject both units", .pme_long_desc = "Unaligned store reject both units", }, [ POWER6_PME_PM_LSU_REJECT_FAST ] = { .pme_name = "PM_LSU_REJECT_FAST", .pme_code = 0x30003e, .pme_short_desc = "LSU fast reject", .pme_long_desc = "LSU fast reject", }, [ POWER6_PME_PM_DPU_HELD_THRD_PRIO ] = { .pme_name = "PM_DPU_HELD_THRD_PRIO", .pme_code = 0x3008a, .pme_short_desc = "DISP unit held due to lower priority thread", .pme_long_desc = "DISP unit held due to lower priority thread", }, [ POWER6_PME_PM_L2_PREF_LD ] = { .pme_name = "PM_L2_PREF_LD", .pme_code = 0x810a6, .pme_short_desc = "L2 cache prefetches", .pme_long_desc = "L2 cache prefetches", }, [ POWER6_PME_PM_FPU_FEST ] = { .pme_name = "PM_FPU_FEST", .pme_code = 0x4d1030, .pme_short_desc = "FPU executed FEST instruction", .pme_long_desc = "This signal is active for one cycle when executing one of the estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ. Combined Unit 0 + Unit 1.", }, [ POWER6_PME_PM_MRK_DATA_FROM_RMEM ] = { .pme_name = "PM_MRK_DATA_FROM_RMEM", .pme_code = 0x30304a, .pme_short_desc = "Marked data loaded from remote memory", .pme_long_desc = "Marked data loaded from remote memory", }, [ POWER6_PME_PM_LD_MISS_L1_CYC ] = { .pme_name = "PM_LD_MISS_L1_CYC", .pme_code = 0x10000c, .pme_short_desc = "L1 data load miss cycles", .pme_long_desc = "L1 data load miss cycles", }, [ POWER6_PME_PM_DERAT_MISS_4K ] = { .pme_name = "PM_DERAT_MISS_4K", .pme_code = 0x192070, .pme_short_desc = "DERAT misses for 4K page", .pme_long_desc = "A data request (load or store) missed the ERAT for 4K page and resulted in an ERAT reload.", }, [ POWER6_PME_PM_DPU_HELD_COMPLETION ] = { .pme_name = "PM_DPU_HELD_COMPLETION", .pme_code = 0x210ac, .pme_short_desc = "DISP unit held due to completion holding dispatch ", .pme_long_desc = "DISP unit held due to completion holding dispatch ", }, [ POWER6_PME_PM_FPU_ISSUE_STALL_ST ] = { .pme_name = "PM_FPU_ISSUE_STALL_ST", .pme_code = 0x320ce, .pme_short_desc = "FPU issue stalled due to store", .pme_long_desc = "FPU issue stalled due to store", }, [ POWER6_PME_PM_L2SB_DC_INV ] = { .pme_name = "PM_L2SB_DC_INV", .pme_code = 0x5068e, .pme_short_desc = "L2 slice B D cache invalidate", .pme_long_desc = "L2 slice B D cache invalidate", }, [ POWER6_PME_PM_PTEG_FROM_L25_SHR ] = { .pme_name = "PM_PTEG_FROM_L25_SHR", .pme_code = 0x41304e, .pme_short_desc = "PTEG loaded from L2.5 shared", .pme_long_desc = "PTEG loaded from L2.5 shared", }, [ POWER6_PME_PM_PTEG_FROM_DL2L3_MOD ] = { .pme_name = "PM_PTEG_FROM_DL2L3_MOD", .pme_code = 0x41304c, .pme_short_desc = "PTEG loaded from distant L2 or L3 modified", .pme_long_desc = "PTEG loaded from distant L2 or L3 modified", }, [ POWER6_PME_PM_FAB_CMD_RETRIED ] = { .pme_name = "PM_FAB_CMD_RETRIED", .pme_code = 0x250130, .pme_short_desc = "Fabric command retried", .pme_long_desc = "Fabric command retried", }, [ POWER6_PME_PM_BR_PRED_LSTACK ] = { .pme_name = "PM_BR_PRED_LSTACK", .pme_code = 0x410a6, .pme_short_desc = "A conditional branch was predicted, link stack", .pme_long_desc = "A conditional branch was predicted, link stack", }, [ POWER6_PME_PM_GXO_DATA_CYC_BUSY ] = { .pme_name = "PM_GXO_DATA_CYC_BUSY", .pme_code = 0x50384, .pme_short_desc = "Outbound GX Data utilization (# of cycles data out is valid)", .pme_long_desc = "Outbound GX Data utilization (# of cycles data out is valid)", }, [ POWER6_PME_PM_DFU_SUBNORM ] = { .pme_name = "PM_DFU_SUBNORM", .pme_code = 0xe0086, .pme_short_desc = "DFU result is a subnormal", .pme_long_desc = "DFU result is a subnormal", }, [ POWER6_PME_PM_FPU_ISSUE_OOO ] = { .pme_name = "PM_FPU_ISSUE_OOO", .pme_code = 0x320c0, .pme_short_desc = "FPU issue out-of-order", .pme_long_desc = "FPU issue out-of-order", }, [ POWER6_PME_PM_LSU_REJECT_ULD_BOTH ] = { .pme_name = "PM_LSU_REJECT_ULD_BOTH", .pme_code = 0x290036, .pme_short_desc = "Unaligned load reject both units", .pme_long_desc = "Unaligned load reject both units", }, [ POWER6_PME_PM_L2SB_ST_MISS ] = { .pme_name = "PM_L2SB_ST_MISS", .pme_code = 0x5048e, .pme_short_desc = "L2 slice B store misses", .pme_long_desc = "L2 slice B store misses", }, [ POWER6_PME_PM_DATA_FROM_L25_MOD_CYC ] = { .pme_name = "PM_DATA_FROM_L25_MOD_CYC", .pme_code = 0x400024, .pme_short_desc = "Load latency from L2.5 modified", .pme_long_desc = "Load latency from L2.5 modified", }, [ POWER6_PME_PM_INST_PTEG_1ST_HALF ] = { .pme_name = "PM_INST_PTEG_1ST_HALF", .pme_code = 0x910a8, .pme_short_desc = "Instruction table walk matched in first half primary PTEG", .pme_long_desc = "Instruction table walk matched in first half primary PTEG", }, [ POWER6_PME_PM_DERAT_MISS_16M ] = { .pme_name = "PM_DERAT_MISS_16M", .pme_code = 0x392070, .pme_short_desc = "DERAT misses for 16M page", .pme_long_desc = "A data request (load or store) missed the ERAT for 16M page and resulted in an ERAT reload.", }, [ POWER6_PME_PM_GX_DMA_WRITE ] = { .pme_name = "PM_GX_DMA_WRITE", .pme_code = 0x5038e, .pme_short_desc = "All DMA Write Requests (including dma wrt lgcy)", .pme_long_desc = "All DMA Write Requests (including dma wrt lgcy)", }, [ POWER6_PME_PM_MRK_PTEG_FROM_DL2L3_MOD ] = { .pme_name = "PM_MRK_PTEG_FROM_DL2L3_MOD", .pme_code = 0x412044, .pme_short_desc = "Marked PTEG loaded from distant L2 or L3 modified", .pme_long_desc = "Marked PTEG loaded from distant L2 or L3 modified", }, [ POWER6_PME_PM_MEM1_DP_RQ_GLOB_LOC ] = { .pme_name = "PM_MEM1_DP_RQ_GLOB_LOC", .pme_code = 0x50288, .pme_short_desc = "Memory read queue marking cache line double pump state from global to local side 1", .pme_long_desc = "Memory read queue marking cache line double pump state from global to local side 1", }, [ POWER6_PME_PM_L2SB_LD_REQ_DATA ] = { .pme_name = "PM_L2SB_LD_REQ_DATA", .pme_code = 0x50488, .pme_short_desc = "L2 slice B data load requests", .pme_long_desc = "L2 slice B data load requests", }, [ POWER6_PME_PM_L2SA_LD_MISS_INST ] = { .pme_name = "PM_L2SA_LD_MISS_INST", .pme_code = 0x50582, .pme_short_desc = "L2 slice A instruction load misses", .pme_long_desc = "L2 slice A instruction load misses", }, [ POWER6_PME_PM_MRK_LSU0_REJECT_L2MISS ] = { .pme_name = "PM_MRK_LSU0_REJECT_L2MISS", .pme_code = 0x930e4, .pme_short_desc = "LSU0 marked L2 miss reject", .pme_long_desc = "LSU0 marked L2 miss reject", }, [ POWER6_PME_PM_MRK_IFU_FIN ] = { .pme_name = "PM_MRK_IFU_FIN", .pme_code = 0x20000a, .pme_short_desc = "Marked instruction IFU processing finished", .pme_long_desc = "Marked instruction IFU processing finished", }, [ POWER6_PME_PM_INST_FROM_L3 ] = { .pme_name = "PM_INST_FROM_L3", .pme_code = 0x342040, .pme_short_desc = "Instruction fetched from L3", .pme_long_desc = "An instruction fetch group was fetched from L3. Fetch Groups can contain up to 8 instructions", }, [ POWER6_PME_PM_FXU1_FIN ] = { .pme_name = "PM_FXU1_FIN", .pme_code = 0x400016, .pme_short_desc = "FXU1 produced a result", .pme_long_desc = "The Fixed Point unit 1 finished an instruction and produced a result", }, [ POWER6_PME_PM_THRD_PRIO_4_CYC ] = { .pme_name = "PM_THRD_PRIO_4_CYC", .pme_code = 0x422046, .pme_short_desc = "Cycles thread running at priority level 4", .pme_long_desc = "Cycles thread running at priority level 4", }, [ POWER6_PME_PM_MRK_DATA_FROM_L35_MOD ] = { .pme_name = "PM_MRK_DATA_FROM_L35_MOD", .pme_code = 0x10304e, .pme_short_desc = "Marked data loaded from L3.5 modified", .pme_long_desc = "Marked data loaded from L3.5 modified", }, [ POWER6_PME_PM_LSU_REJECT_SET_MPRED ] = { .pme_name = "PM_LSU_REJECT_SET_MPRED", .pme_code = 0x2a0032, .pme_short_desc = "LSU reject due to mispredicted set", .pme_long_desc = "LSU reject due to mispredicted set", }, [ POWER6_PME_PM_MRK_DERAT_MISS_16G ] = { .pme_name = "PM_MRK_DERAT_MISS_16G", .pme_code = 0x492044, .pme_short_desc = "Marked DERAT misses for 16G page", .pme_long_desc = "A marked data request (load or store) missed the ERAT for 16G page and resulted in an ERAT reload.", }, [ POWER6_PME_PM_FPU0_FXDIV ] = { .pme_name = "PM_FPU0_FXDIV", .pme_code = 0xc10a0, .pme_short_desc = "FPU0 executed fixed point division", .pme_long_desc = "FPU0 executed fixed point division", }, [ POWER6_PME_PM_MRK_LSU1_REJECT_UST ] = { .pme_name = "PM_MRK_LSU1_REJECT_UST", .pme_code = 0x930ea, .pme_short_desc = "LSU1 marked unaligned store reject", .pme_long_desc = "LSU1 marked unaligned store reject", }, [ POWER6_PME_PM_FPU_ISSUE_DIV_SQRT_OVERLAP ] = { .pme_name = "PM_FPU_ISSUE_DIV_SQRT_OVERLAP", .pme_code = 0x320cc, .pme_short_desc = "FPU divide/sqrt overlapped with other divide/sqrt", .pme_long_desc = "FPU divide/sqrt overlapped with other divide/sqrt", }, [ POWER6_PME_PM_INST_FROM_L35_SHR ] = { .pme_name = "PM_INST_FROM_L35_SHR", .pme_code = 0x242046, .pme_short_desc = "Instruction fetched from L3.5 shared", .pme_long_desc = "Instruction fetched from L3.5 shared", }, [ POWER6_PME_PM_MRK_LSU_REJECT_LHS ] = { .pme_name = "PM_MRK_LSU_REJECT_LHS", .pme_code = 0x493030, .pme_short_desc = "Marked load hit store reject", .pme_long_desc = "Marked load hit store reject", }, [ POWER6_PME_PM_LSU_LMQ_FULL_CYC ] = { .pme_name = "PM_LSU_LMQ_FULL_CYC", .pme_code = 0x810ac, .pme_short_desc = "Cycles LMQ full", .pme_long_desc = "The LMQ was full", }, [ POWER6_PME_PM_SYNC_COUNT ] = { .pme_name = "PM_SYNC_COUNT", .pme_code = 0x920cd, .pme_short_desc = "SYNC instructions completed", .pme_long_desc = "SYNC instructions completed", }, [ POWER6_PME_PM_MEM0_DP_RQ_LOC_GLOB ] = { .pme_name = "PM_MEM0_DP_RQ_LOC_GLOB", .pme_code = 0x50282, .pme_short_desc = "Memory read queue marking cache line double pump state from local to global side 0", .pme_long_desc = "Memory read queue marking cache line double pump state from local to global side 0", }, [ POWER6_PME_PM_L2SA_CASTOUT_MOD ] = { .pme_name = "PM_L2SA_CASTOUT_MOD", .pme_code = 0x50680, .pme_short_desc = "L2 slice A castouts - Modified", .pme_long_desc = "L2 slice A castouts - Modified", }, [ POWER6_PME_PM_LSU_LMQ_SRQ_EMPTY_BOTH_COUNT ] = { .pme_name = "PM_LSU_LMQ_SRQ_EMPTY_BOTH_COUNT", .pme_code = 0x30001d, .pme_short_desc = "Periods both threads LMQ and SRQ empty", .pme_long_desc = "Periods both threads LMQ and SRQ empty", }, [ POWER6_PME_PM_PTEG_FROM_MEM_DP ] = { .pme_name = "PM_PTEG_FROM_MEM_DP", .pme_code = 0x11304a, .pme_short_desc = "PTEG loaded from double pump memory", .pme_long_desc = "PTEG loaded from double pump memory", }, [ POWER6_PME_PM_LSU_REJECT_SLOW ] = { .pme_name = "PM_LSU_REJECT_SLOW", .pme_code = 0x20003e, .pme_short_desc = "LSU slow reject", .pme_long_desc = "LSU slow reject", }, [ POWER6_PME_PM_PTEG_FROM_L25_MOD ] = { .pme_name = "PM_PTEG_FROM_L25_MOD", .pme_code = 0x31304e, .pme_short_desc = "PTEG loaded from L2.5 modified", .pme_long_desc = "PTEG loaded from L2.5 modified", }, [ POWER6_PME_PM_THRD_PRIO_7_CYC ] = { .pme_name = "PM_THRD_PRIO_7_CYC", .pme_code = 0x122046, .pme_short_desc = "Cycles thread running at priority level 7", .pme_long_desc = "Cycles thread running at priority level 7", }, [ POWER6_PME_PM_MRK_PTEG_FROM_RL2L3_SHR ] = { .pme_name = "PM_MRK_PTEG_FROM_RL2L3_SHR", .pme_code = 0x212044, .pme_short_desc = "Marked PTEG loaded from remote L2 or L3 shared", .pme_long_desc = "Marked PTEG loaded from remote L2 or L3 shared", }, [ POWER6_PME_PM_ST_REQ_L2 ] = { .pme_name = "PM_ST_REQ_L2", .pme_code = 0x250732, .pme_short_desc = "L2 store requests", .pme_long_desc = "L2 store requests", }, [ POWER6_PME_PM_ST_REF_L1 ] = { .pme_name = "PM_ST_REF_L1", .pme_code = 0x80086, .pme_short_desc = "L1 D cache store references", .pme_long_desc = "Total DL1 Store references", }, [ POWER6_PME_PM_FPU_ISSUE_STALL_THRD ] = { .pme_name = "PM_FPU_ISSUE_STALL_THRD", .pme_code = 0x330e0, .pme_short_desc = "FPU issue stalled due to thread resource conflict", .pme_long_desc = "FPU issue stalled due to thread resource conflict", }, [ POWER6_PME_PM_RUN_COUNT ] = { .pme_name = "PM_RUN_COUNT", .pme_code = 0x10000b, .pme_short_desc = "Run Periods", .pme_long_desc = "Processor Periods gated by the run latch", }, [ POWER6_PME_PM_RUN_CYC ] = { .pme_name = "PM_RUN_CYC", .pme_code = 0x10000a, .pme_short_desc = "Run cycles", .pme_long_desc = "Processor Cycles gated by the run latch", }, [ POWER6_PME_PM_PTEG_FROM_RMEM ] = { .pme_name = "PM_PTEG_FROM_RMEM", .pme_code = 0x31304a, .pme_short_desc = "PTEG loaded from remote memory", .pme_long_desc = "PTEG loaded from remote memory", }, [ POWER6_PME_PM_LSU0_LDF ] = { .pme_name = "PM_LSU0_LDF", .pme_code = 0x80084, .pme_short_desc = "LSU0 executed Floating Point load instruction", .pme_long_desc = "A floating point load was executed from LSU unit 0", }, [ POWER6_PME_PM_ST_MISS_L1 ] = { .pme_name = "PM_ST_MISS_L1", .pme_code = 0x80088, .pme_short_desc = "L1 D cache store misses", .pme_long_desc = "A store missed the dcache", }, [ POWER6_PME_PM_INST_FROM_DL2L3_SHR ] = { .pme_name = "PM_INST_FROM_DL2L3_SHR", .pme_code = 0x342044, .pme_short_desc = "Instruction fetched from distant L2 or L3 shared", .pme_long_desc = "Instruction fetched from distant L2 or L3 shared", }, [ POWER6_PME_PM_L2SA_IC_INV ] = { .pme_name = "PM_L2SA_IC_INV", .pme_code = 0x50684, .pme_short_desc = "L2 slice A I cache invalidate", .pme_long_desc = "L2 slice A I cache invalidate", }, [ POWER6_PME_PM_THRD_ONE_RUN_CYC ] = { .pme_name = "PM_THRD_ONE_RUN_CYC", .pme_code = 0x100016, .pme_short_desc = "One of the threads in run cycles", .pme_long_desc = "One of the threads in run cycles", }, [ POWER6_PME_PM_L2SB_LD_REQ_INST ] = { .pme_name = "PM_L2SB_LD_REQ_INST", .pme_code = 0x50588, .pme_short_desc = "L2 slice B instruction load requests", .pme_long_desc = "L2 slice B instruction load requests", }, [ POWER6_PME_PM_MRK_DATA_FROM_L25_MOD ] = { .pme_name = "PM_MRK_DATA_FROM_L25_MOD", .pme_code = 0x30304e, .pme_short_desc = "Marked data loaded from L2.5 modified", .pme_long_desc = "DL1 was reloaded with modified (M) data from the L2 of a chip on this MCM due to a marked demand load", }, [ POWER6_PME_PM_DPU_HELD_XTHRD ] = { .pme_name = "PM_DPU_HELD_XTHRD", .pme_code = 0x30082, .pme_short_desc = "DISP unit held due to cross thread resource conflicts", .pme_long_desc = "DISP unit held due to cross thread resource conflicts", }, [ POWER6_PME_PM_L2SB_ST_REQ ] = { .pme_name = "PM_L2SB_ST_REQ", .pme_code = 0x5048c, .pme_short_desc = "L2 slice B store requests", .pme_long_desc = "A store request as seen at the L2 directory has been made from the core. Stores are counted after gathering in the L2 store queues. The event is provided on each of the three slices A,B,and C.", }, [ POWER6_PME_PM_INST_FROM_L21 ] = { .pme_name = "PM_INST_FROM_L21", .pme_code = 0x242040, .pme_short_desc = "Instruction fetched from private L2 other core", .pme_long_desc = "Instruction fetched from private L2 other core", }, [ POWER6_PME_PM_INST_FROM_L3MISS ] = { .pme_name = "PM_INST_FROM_L3MISS", .pme_code = 0x342054, .pme_short_desc = "Instruction fetched missed L3", .pme_long_desc = "Instruction fetched missed L3", }, [ POWER6_PME_PM_L3SB_HIT ] = { .pme_name = "PM_L3SB_HIT", .pme_code = 0x5008a, .pme_short_desc = "L3 slice B hits", .pme_long_desc = "L3 slice B hits", }, [ POWER6_PME_PM_EE_OFF_EXT_INT ] = { .pme_name = "PM_EE_OFF_EXT_INT", .pme_code = 0x230ee, .pme_short_desc = "Cycles MSR(EE) bit off and external interrupt pending", .pme_long_desc = "Cycles MSR(EE) bit off and external interrupt pending", }, [ POWER6_PME_PM_INST_FROM_DL2L3_MOD ] = { .pme_name = "PM_INST_FROM_DL2L3_MOD", .pme_code = 0x442044, .pme_short_desc = "Instruction fetched from distant L2 or L3 modified", .pme_long_desc = "Instruction fetched from distant L2 or L3 modified", }, [ POWER6_PME_PM_PMC6_OVERFLOW ] = { .pme_name = "PM_PMC6_OVERFLOW", .pme_code = 0x300024, .pme_short_desc = "PMC6 Overflow", .pme_long_desc = "PMC6 Overflow", }, [ POWER6_PME_PM_FPU_FLOP ] = { .pme_name = "PM_FPU_FLOP", .pme_code = 0x1c0032, .pme_short_desc = "FPU executed 1FLOP, FMA, FSQRT or FDIV instruction", .pme_long_desc = "FPU executed 1FLOP, FMA, FSQRT or FDIV instruction", }, [ POWER6_PME_PM_FXU_BUSY ] = { .pme_name = "PM_FXU_BUSY", .pme_code = 0x200050, .pme_short_desc = "FXU busy", .pme_long_desc = "FXU0 and FXU1 are both busy", }, [ POWER6_PME_PM_FPU1_FLOP ] = { .pme_name = "PM_FPU1_FLOP", .pme_code = 0xc008e, .pme_short_desc = "FPU1 executed 1FLOP, FMA, FSQRT or FDIV instruction", .pme_long_desc = "FPU1 executed 1FLOP, FMA, FSQRT or FDIV instruction", }, [ POWER6_PME_PM_IC_RELOAD_SHR ] = { .pme_name = "PM_IC_RELOAD_SHR", .pme_code = 0x4008e, .pme_short_desc = "I cache line reloading to be shared by threads", .pme_long_desc = "I cache line reloading to be shared by threads", }, [ POWER6_PME_PM_INST_TABLEWALK_CYC ] = { .pme_name = "PM_INST_TABLEWALK_CYC", .pme_code = 0x920ca, .pme_short_desc = "Cycles doing instruction tablewalks", .pme_long_desc = "Cycles doing instruction tablewalks", }, [ POWER6_PME_PM_DATA_FROM_RL2L3_MOD_CYC ] = { .pme_name = "PM_DATA_FROM_RL2L3_MOD_CYC", .pme_code = 0x400028, .pme_short_desc = "Load latency from remote L2 or L3 modified", .pme_long_desc = "Load latency from remote L2 or L3 modified", }, [ POWER6_PME_PM_THRD_PRIO_DIFF_5or6_CYC ] = { .pme_name = "PM_THRD_PRIO_DIFF_5or6_CYC", .pme_code = 0x423040, .pme_short_desc = "Cycles thread priority difference is 5 or 6", .pme_long_desc = "Cycles thread priority difference is 5 or 6", }, [ POWER6_PME_PM_IBUF_FULL_CYC ] = { .pme_name = "PM_IBUF_FULL_CYC", .pme_code = 0x40084, .pme_short_desc = "Cycles instruction buffer full", .pme_long_desc = "Cycles instruction buffer full", }, [ POWER6_PME_PM_L2SA_LD_REQ ] = { .pme_name = "PM_L2SA_LD_REQ", .pme_code = 0x50780, .pme_short_desc = "L2 slice A load requests ", .pme_long_desc = "L2 slice A load requests ", }, [ POWER6_PME_PM_VMX1_LD_WRBACK ] = { .pme_name = "PM_VMX1_LD_WRBACK", .pme_code = 0x6008c, .pme_short_desc = "VMX1 load writeback valid", .pme_long_desc = "VMX1 load writeback valid", }, [ POWER6_PME_PM_MRK_FPU_FIN ] = { .pme_name = "PM_MRK_FPU_FIN", .pme_code = 0x2d0030, .pme_short_desc = "Marked instruction FPU processing finished", .pme_long_desc = "One of the Floating Point Units finished a marked instruction. Instructions that finish may not necessary complete", }, [ POWER6_PME_PM_THRD_PRIO_5_CYC ] = { .pme_name = "PM_THRD_PRIO_5_CYC", .pme_code = 0x322046, .pme_short_desc = "Cycles thread running at priority level 5", .pme_long_desc = "Cycles thread running at priority level 5", }, [ POWER6_PME_PM_DFU_BACK2BACK ] = { .pme_name = "PM_DFU_BACK2BACK", .pme_code = 0xe0082, .pme_short_desc = "DFU back to back operations executed", .pme_long_desc = "DFU back to back operations executed", }, [ POWER6_PME_PM_MRK_DATA_FROM_LMEM ] = { .pme_name = "PM_MRK_DATA_FROM_LMEM", .pme_code = 0x40304a, .pme_short_desc = "Marked data loaded from local memory", .pme_long_desc = "Marked data loaded from local memory", }, [ POWER6_PME_PM_LSU_REJECT_LHS ] = { .pme_name = "PM_LSU_REJECT_LHS", .pme_code = 0x190032, .pme_short_desc = "Load hit store reject", .pme_long_desc = "Load hit store reject", }, [ POWER6_PME_PM_DPU_HELD_SPR ] = { .pme_name = "PM_DPU_HELD_SPR", .pme_code = 0x3008c, .pme_short_desc = "DISP unit held due to MTSPR/MFSPR", .pme_long_desc = "DISP unit held due to MTSPR/MFSPR", }, [ POWER6_PME_PM_FREQ_DOWN ] = { .pme_name = "PM_FREQ_DOWN", .pme_code = 0x30003c, .pme_short_desc = "Frequency is being slewed down due to Power Management", .pme_long_desc = "Frequency is being slewed down due to Power Management", }, [ POWER6_PME_PM_DFU_ENC_BCD_DPD ] = { .pme_name = "PM_DFU_ENC_BCD_DPD", .pme_code = 0xe008a, .pme_short_desc = "DFU Encode BCD to DPD", .pme_long_desc = "DFU Encode BCD to DPD", }, [ POWER6_PME_PM_DPU_HELD_GPR ] = { .pme_name = "PM_DPU_HELD_GPR", .pme_code = 0x20080, .pme_short_desc = "DISP unit held due to GPR dependencies", .pme_long_desc = "DISP unit held due to GPR dependencies", }, [ POWER6_PME_PM_LSU0_NCST ] = { .pme_name = "PM_LSU0_NCST", .pme_code = 0x820cc, .pme_short_desc = "LSU0 non-cachable stores", .pme_long_desc = "LSU0 non-cachable stores", }, [ POWER6_PME_PM_MRK_INST_ISSUED ] = { .pme_name = "PM_MRK_INST_ISSUED", .pme_code = 0x10001c, .pme_short_desc = "Marked instruction issued", .pme_long_desc = "Marked instruction issued", }, [ POWER6_PME_PM_INST_FROM_RL2L3_SHR ] = { .pme_name = "PM_INST_FROM_RL2L3_SHR", .pme_code = 0x242044, .pme_short_desc = "Instruction fetched from remote L2 or L3 shared", .pme_long_desc = "Instruction fetched from remote L2 or L3 shared", }, [ POWER6_PME_PM_FPU_DENORM ] = { .pme_name = "PM_FPU_DENORM", .pme_code = 0x2c1034, .pme_short_desc = "FPU received denormalized data", .pme_long_desc = "This signal is active for one cycle when one of the operands is denormalized. Combined Unit 0 + Unit 1", }, [ POWER6_PME_PM_PTEG_FROM_L3MISS ] = { .pme_name = "PM_PTEG_FROM_L3MISS", .pme_code = 0x313028, .pme_short_desc = "PTEG loaded from L3 miss", .pme_long_desc = "PTEG loaded from L3 miss", }, [ POWER6_PME_PM_RUN_PURR ] = { .pme_name = "PM_RUN_PURR", .pme_code = 0x4000f4, .pme_short_desc = "Run PURR Event", .pme_long_desc = "Run PURR Event", }, [ POWER6_PME_PM_MRK_VMX0_LD_WRBACK ] = { .pme_name = "PM_MRK_VMX0_LD_WRBACK", .pme_code = 0x60086, .pme_short_desc = "Marked VMX0 load writeback valid", .pme_long_desc = "Marked VMX0 load writeback valid", }, [ POWER6_PME_PM_L2_MISS ] = { .pme_name = "PM_L2_MISS", .pme_code = 0x250532, .pme_short_desc = "L2 cache misses", .pme_long_desc = "L2 cache misses", }, [ POWER6_PME_PM_MRK_DATA_FROM_L3 ] = { .pme_name = "PM_MRK_DATA_FROM_L3", .pme_code = 0x303048, .pme_short_desc = "Marked data loaded from L3", .pme_long_desc = "DL1 was reloaded from the local L3 due to a marked demand load", }, [ POWER6_PME_PM_MRK_LSU1_REJECT_LHS ] = { .pme_name = "PM_MRK_LSU1_REJECT_LHS", .pme_code = 0x930ee, .pme_short_desc = "LSU1 marked load hit store reject", .pme_long_desc = "LSU1 marked load hit store reject", }, [ POWER6_PME_PM_L2SB_LD_MISS_INST ] = { .pme_name = "PM_L2SB_LD_MISS_INST", .pme_code = 0x5058a, .pme_short_desc = "L2 slice B instruction load misses", .pme_long_desc = "L2 slice B instruction load misses", }, [ POWER6_PME_PM_PTEG_FROM_RL2L3_SHR ] = { .pme_name = "PM_PTEG_FROM_RL2L3_SHR", .pme_code = 0x21304c, .pme_short_desc = "PTEG loaded from remote L2 or L3 shared", .pme_long_desc = "PTEG loaded from remote L2 or L3 shared", }, [ POWER6_PME_PM_MRK_DERAT_MISS_64K ] = { .pme_name = "PM_MRK_DERAT_MISS_64K", .pme_code = 0x192044, .pme_short_desc = "Marked DERAT misses for 64K page", .pme_long_desc = "A marked data request (load or store) missed the ERAT for 64K page and resulted in an ERAT reload.", }, [ POWER6_PME_PM_LWSYNC ] = { .pme_name = "PM_LWSYNC", .pme_code = 0x810ae, .pme_short_desc = "Isync instruction completed", .pme_long_desc = "Isync instruction completed", }, [ POWER6_PME_PM_FPU1_FXMULT ] = { .pme_name = "PM_FPU1_FXMULT", .pme_code = 0xd008e, .pme_short_desc = "FPU1 executed fixed point multiplication", .pme_long_desc = "FPU1 executed fixed point multiplication", }, [ POWER6_PME_PM_MEM0_DP_CL_WR_GLOB ] = { .pme_name = "PM_MEM0_DP_CL_WR_GLOB", .pme_code = 0x50284, .pme_short_desc = "cacheline write setting dp to global side 0", .pme_long_desc = "cacheline write setting dp to global side 0", }, [ POWER6_PME_PM_LSU0_REJECT_PARTIAL_SECTOR ] = { .pme_name = "PM_LSU0_REJECT_PARTIAL_SECTOR", .pme_code = 0xa0086, .pme_short_desc = "LSU0 reject due to partial sector valid", .pme_long_desc = "LSU0 reject due to partial sector valid", }, [ POWER6_PME_PM_INST_IMC_MATCH_CMPL ] = { .pme_name = "PM_INST_IMC_MATCH_CMPL", .pme_code = 0x1000f0, .pme_short_desc = "IMC matched instructions completed", .pme_long_desc = "Number of instructions resulting from the marked instructions expansion that completed.", }, [ POWER6_PME_PM_DPU_HELD_THERMAL ] = { .pme_name = "PM_DPU_HELD_THERMAL", .pme_code = 0x10002a, .pme_short_desc = "DISP unit held due to thermal condition", .pme_long_desc = "DISP unit held due to thermal condition", }, [ POWER6_PME_PM_FPU_FRSP ] = { .pme_name = "PM_FPU_FRSP", .pme_code = 0x2d1034, .pme_short_desc = "FPU executed FRSP instruction", .pme_long_desc = "FPU executed FRSP instruction", }, [ POWER6_PME_PM_MRK_INST_FIN ] = { .pme_name = "PM_MRK_INST_FIN", .pme_code = 0x30000a, .pme_short_desc = "Marked instruction finished", .pme_long_desc = "One of the execution units finished a marked instruction. Instructions that finish may not necessary complete", }, [ POWER6_PME_PM_MRK_PTEG_FROM_DL2L3_SHR ] = { .pme_name = "PM_MRK_PTEG_FROM_DL2L3_SHR", .pme_code = 0x312044, .pme_short_desc = "Marked PTEG loaded from distant L2 or L3 shared", .pme_long_desc = "Marked PTEG loaded from distant L2 or L3 shared", }, [ POWER6_PME_PM_MRK_DTLB_REF ] = { .pme_name = "PM_MRK_DTLB_REF", .pme_code = 0x920c0, .pme_short_desc = "Marked Data TLB reference", .pme_long_desc = "Marked Data TLB reference", }, [ POWER6_PME_PM_MRK_PTEG_FROM_L25_SHR ] = { .pme_name = "PM_MRK_PTEG_FROM_L25_SHR", .pme_code = 0x412046, .pme_short_desc = "Marked PTEG loaded from L2.5 shared", .pme_long_desc = "Marked PTEG loaded from L2.5 shared", }, [ POWER6_PME_PM_DPU_HELD_LSU ] = { .pme_name = "PM_DPU_HELD_LSU", .pme_code = 0x210a2, .pme_short_desc = "DISP unit held due to LSU move or invalidate SLB and SR", .pme_long_desc = "DISP unit held due to LSU move or invalidate SLB and SR", }, [ POWER6_PME_PM_FPU_FSQRT_FDIV ] = { .pme_name = "PM_FPU_FSQRT_FDIV", .pme_code = 0x2c0032, .pme_short_desc = "FPU executed FSQRT or FDIV instruction", .pme_long_desc = "FPU executed FSQRT or FDIV instruction", }, [ POWER6_PME_PM_LSU_LMQ_SRQ_EMPTY_COUNT ] = { .pme_name = "PM_LSU_LMQ_SRQ_EMPTY_COUNT", .pme_code = 0x20001d, .pme_short_desc = "Periods LMQ and SRQ empty", .pme_long_desc = "Periods when both the LMQ and SRQ are empty (LSU is idle)", }, [ POWER6_PME_PM_DATA_PTEG_SECONDARY ] = { .pme_name = "PM_DATA_PTEG_SECONDARY", .pme_code = 0x910a4, .pme_short_desc = "Data table walk matched in secondary PTEG", .pme_long_desc = "Data table walk matched in secondary PTEG", }, [ POWER6_PME_PM_FPU1_FEST ] = { .pme_name = "PM_FPU1_FEST", .pme_code = 0xd10ae, .pme_short_desc = "FPU1 executed FEST instruction", .pme_long_desc = "This signal is active for one cycle when fp1 is executing one of the estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ. ", }, [ POWER6_PME_PM_L2SA_LD_HIT ] = { .pme_name = "PM_L2SA_LD_HIT", .pme_code = 0x50782, .pme_short_desc = "L2 slice A load hits", .pme_long_desc = "L2 slice A load hits", }, [ POWER6_PME_PM_DATA_FROM_MEM_DP_CYC ] = { .pme_name = "PM_DATA_FROM_MEM_DP_CYC", .pme_code = 0x40002e, .pme_short_desc = "Load latency from double pump memory", .pme_long_desc = "Load latency from double pump memory", }, [ POWER6_PME_PM_BR_MPRED_CCACHE ] = { .pme_name = "PM_BR_MPRED_CCACHE", .pme_code = 0x410ae, .pme_short_desc = "Branch misprediction due to count cache prediction", .pme_long_desc = "Branch misprediction due to count cache prediction", }, [ POWER6_PME_PM_DPU_HELD_COUNT ] = { .pme_name = "PM_DPU_HELD_COUNT", .pme_code = 0x200005, .pme_short_desc = "Periods DISP unit held", .pme_long_desc = "Dispatch unit held", }, [ POWER6_PME_PM_LSU1_REJECT_SET_MPRED ] = { .pme_name = "PM_LSU1_REJECT_SET_MPRED", .pme_code = 0xa008c, .pme_short_desc = "LSU1 reject due to mispredicted set", .pme_long_desc = "LSU1 reject due to mispredicted set", }, [ POWER6_PME_PM_FPU_ISSUE_2 ] = { .pme_name = "PM_FPU_ISSUE_2", .pme_code = 0x320ca, .pme_short_desc = "FPU issue 2 per cycle", .pme_long_desc = "FPU issue 2 per cycle", }, [ POWER6_PME_PM_LSU1_REJECT_L2_CORR ] = { .pme_name = "PM_LSU1_REJECT_L2_CORR", .pme_code = 0xa10a8, .pme_short_desc = "LSU1 reject due to L2 correctable error", .pme_long_desc = "LSU1 reject due to L2 correctable error", }, [ POWER6_PME_PM_MRK_PTEG_FROM_DMEM ] = { .pme_name = "PM_MRK_PTEG_FROM_DMEM", .pme_code = 0x212042, .pme_short_desc = "Marked PTEG loaded from distant memory", .pme_long_desc = "Marked PTEG loaded from distant memory", }, [ POWER6_PME_PM_MEM1_DP_RQ_LOC_GLOB ] = { .pme_name = "PM_MEM1_DP_RQ_LOC_GLOB", .pme_code = 0x5028a, .pme_short_desc = "Memory read queue marking cache line double pump state from local to global side 1", .pme_long_desc = "Memory read queue marking cache line double pump state from local to global side 1", }, [ POWER6_PME_PM_THRD_PRIO_DIFF_minus1or2_CYC ] = { .pme_name = "PM_THRD_PRIO_DIFF_minus1or2_CYC", .pme_code = 0x223046, .pme_short_desc = "Cycles thread priority difference is -1 or -2", .pme_long_desc = "Cycles thread priority difference is -1 or -2", }, [ POWER6_PME_PM_THRD_PRIO_0_CYC ] = { .pme_name = "PM_THRD_PRIO_0_CYC", .pme_code = 0x122040, .pme_short_desc = "Cycles thread running at priority level 0", .pme_long_desc = "Cycles thread running at priority level 0", }, [ POWER6_PME_PM_FXU0_BUSY_FXU1_IDLE ] = { .pme_name = "PM_FXU0_BUSY_FXU1_IDLE", .pme_code = 0x300050, .pme_short_desc = "FXU0 busy FXU1 idle", .pme_long_desc = "FXU0 is busy while FXU1 was idle", }, [ POWER6_PME_PM_LSU1_REJECT_DERAT_MPRED ] = { .pme_name = "PM_LSU1_REJECT_DERAT_MPRED", .pme_code = 0xa008a, .pme_short_desc = "LSU1 reject due to mispredicted DERAT", .pme_long_desc = "LSU1 reject due to mispredicted DERAT", }, [ POWER6_PME_PM_MRK_VMX1_LD_WRBACK ] = { .pme_name = "PM_MRK_VMX1_LD_WRBACK", .pme_code = 0x6008e, .pme_short_desc = "Marked VMX1 load writeback valid", .pme_long_desc = "Marked VMX1 load writeback valid", }, [ POWER6_PME_PM_DATA_FROM_RL2L3_SHR_CYC ] = { .pme_name = "PM_DATA_FROM_RL2L3_SHR_CYC", .pme_code = 0x200028, .pme_short_desc = "Load latency from remote L2 or L3 shared", .pme_long_desc = "Load latency from remote L2 or L3 shared", }, [ POWER6_PME_PM_IERAT_MISS_16M ] = { .pme_name = "PM_IERAT_MISS_16M", .pme_code = 0x292076, .pme_short_desc = "IERAT misses for 16M page", .pme_long_desc = "IERAT misses for 16M page", }, [ POWER6_PME_PM_MRK_DATA_FROM_MEM_DP ] = { .pme_name = "PM_MRK_DATA_FROM_MEM_DP", .pme_code = 0x10304a, .pme_short_desc = "Marked data loaded from double pump memory", .pme_long_desc = "Marked data loaded from double pump memory", }, [ POWER6_PME_PM_LARX_L1HIT ] = { .pme_name = "PM_LARX_L1HIT", .pme_code = 0x830e2, .pme_short_desc = "larx hits in L1", .pme_long_desc = "larx hits in L1", }, [ POWER6_PME_PM_L2_ST_MISS_DATA ] = { .pme_name = "PM_L2_ST_MISS_DATA", .pme_code = 0x150432, .pme_short_desc = "L2 data store misses", .pme_long_desc = "L2 data store misses", }, [ POWER6_PME_PM_FPU_ST_FOLDED ] = { .pme_name = "PM_FPU_ST_FOLDED", .pme_code = 0x3d1030, .pme_short_desc = "FPU folded store", .pme_long_desc = "FPU folded store", }, [ POWER6_PME_PM_MRK_DATA_FROM_L35_SHR ] = { .pme_name = "PM_MRK_DATA_FROM_L35_SHR", .pme_code = 0x20304e, .pme_short_desc = "Marked data loaded from L3.5 shared", .pme_long_desc = "Marked data loaded from L3.5 shared", }, [ POWER6_PME_PM_DPU_HELD_MULT_GPR ] = { .pme_name = "PM_DPU_HELD_MULT_GPR", .pme_code = 0x210aa, .pme_short_desc = "DISP unit held due to multiple/divide multiply/divide GPR dependencies", .pme_long_desc = "DISP unit held due to multiple/divide multiply/divide GPR dependencies", }, [ POWER6_PME_PM_FPU0_1FLOP ] = { .pme_name = "PM_FPU0_1FLOP", .pme_code = 0xc0080, .pme_short_desc = "FPU0 executed add, mult, sub, cmp or sel instruction", .pme_long_desc = "This signal is active for one cycle when fp0 is executing an add, mult, sub, compare, or fsel kind of instruction. This could be fadd*, fmul*, fsub*, fcmp**, fsel where XYZ* means XYZ, XYZs, XYZ., XYZs. and XYZ** means XYZu, XYZo", }, [ POWER6_PME_PM_IERAT_MISS_16G ] = { .pme_name = "PM_IERAT_MISS_16G", .pme_code = 0x192076, .pme_short_desc = "IERAT misses for 16G page", .pme_long_desc = "IERAT misses for 16G page", }, [ POWER6_PME_PM_IC_PREF_WRITE ] = { .pme_name = "PM_IC_PREF_WRITE", .pme_code = 0x430e0, .pme_short_desc = "Instruction prefetch written into I cache", .pme_long_desc = "Instruction prefetch written into I cache", }, [ POWER6_PME_PM_THRD_PRIO_DIFF_minus5or6_CYC ] = { .pme_name = "PM_THRD_PRIO_DIFF_minus5or6_CYC", .pme_code = 0x423046, .pme_short_desc = "Cycles thread priority difference is -5 or -6", .pme_long_desc = "Cycles thread priority difference is -5 or -6", }, [ POWER6_PME_PM_FPU0_FIN ] = { .pme_name = "PM_FPU0_FIN", .pme_code = 0xd0080, .pme_short_desc = "FPU0 produced a result", .pme_long_desc = "fp0 finished, produced a result This only indicates finish, not completion. ", }, [ POWER6_PME_PM_DATA_FROM_L2_CYC ] = { .pme_name = "PM_DATA_FROM_L2_CYC", .pme_code = 0x200020, .pme_short_desc = "Load latency from L2", .pme_long_desc = "Load latency from L2", }, [ POWER6_PME_PM_DERAT_REF_16G ] = { .pme_name = "PM_DERAT_REF_16G", .pme_code = 0x482070, .pme_short_desc = "DERAT reference for 16G page", .pme_long_desc = "DERAT reference for 16G page", }, [ POWER6_PME_PM_BR_PRED ] = { .pme_name = "PM_BR_PRED", .pme_code = 0x410a0, .pme_short_desc = "A conditional branch was predicted", .pme_long_desc = "A conditional branch was predicted", }, [ POWER6_PME_PM_VMX1_LD_ISSUED ] = { .pme_name = "PM_VMX1_LD_ISSUED", .pme_code = 0x6008a, .pme_short_desc = "VMX1 load issued", .pme_long_desc = "VMX1 load issued", }, [ POWER6_PME_PM_L2SB_CASTOUT_MOD ] = { .pme_name = "PM_L2SB_CASTOUT_MOD", .pme_code = 0x50688, .pme_short_desc = "L2 slice B castouts - Modified", .pme_long_desc = "L2 slice B castouts - Modified", }, [ POWER6_PME_PM_INST_FROM_DMEM ] = { .pme_name = "PM_INST_FROM_DMEM", .pme_code = 0x242042, .pme_short_desc = "Instruction fetched from distant memory", .pme_long_desc = "Instruction fetched from distant memory", }, [ POWER6_PME_PM_DATA_FROM_L35_SHR_CYC ] = { .pme_name = "PM_DATA_FROM_L35_SHR_CYC", .pme_code = 0x200026, .pme_short_desc = "Load latency from L3.5 shared", .pme_long_desc = "Load latency from L3.5 shared", }, [ POWER6_PME_PM_LSU0_NCLD ] = { .pme_name = "PM_LSU0_NCLD", .pme_code = 0x820ca, .pme_short_desc = "LSU0 non-cacheable loads", .pme_long_desc = "LSU0 non-cacheable loads", }, [ POWER6_PME_PM_FAB_RETRY_NODE_PUMP ] = { .pme_name = "PM_FAB_RETRY_NODE_PUMP", .pme_code = 0x5018a, .pme_short_desc = "Retry of a node pump, locally mastered", .pme_long_desc = "Retry of a node pump, locally mastered", }, [ POWER6_PME_PM_VMX0_INST_ISSUED ] = { .pme_name = "PM_VMX0_INST_ISSUED", .pme_code = 0x60080, .pme_short_desc = "VMX0 instruction issued", .pme_long_desc = "VMX0 instruction issued", }, [ POWER6_PME_PM_DATA_FROM_L25_MOD ] = { .pme_name = "PM_DATA_FROM_L25_MOD", .pme_code = 0x30005a, .pme_short_desc = "Data loaded from L2.5 modified", .pme_long_desc = "DL1 was reloaded with modified (M) data from the L2 of a chip on this MCM due to a demand load", }, [ POWER6_PME_PM_DPU_HELD_ITLB_ISLB ] = { .pme_name = "PM_DPU_HELD_ITLB_ISLB", .pme_code = 0x210a4, .pme_short_desc = "DISP unit held due to SLB or TLB invalidates ", .pme_long_desc = "DISP unit held due to SLB or TLB invalidates ", }, [ POWER6_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC ] = { .pme_name = "PM_LSU_LMQ_SRQ_EMPTY_CYC", .pme_code = 0x20001c, .pme_short_desc = "Cycles LMQ and SRQ empty", .pme_long_desc = "Cycles when both the LMQ and SRQ are empty (LSU is idle)", }, [ POWER6_PME_PM_THRD_CONC_RUN_INST ] = { .pme_name = "PM_THRD_CONC_RUN_INST", .pme_code = 0x300026, .pme_short_desc = "Concurrent run instructions", .pme_long_desc = "Concurrent run instructions", }, [ POWER6_PME_PM_MRK_PTEG_FROM_L2 ] = { .pme_name = "PM_MRK_PTEG_FROM_L2", .pme_code = 0x112040, .pme_short_desc = "Marked PTEG loaded from L2.5 modified", .pme_long_desc = "Marked PTEG loaded from L2.5 modified", }, [ POWER6_PME_PM_PURR ] = { .pme_name = "PM_PURR", .pme_code = 0x10000e, .pme_short_desc = "PURR Event", .pme_long_desc = "PURR Event", }, [ POWER6_PME_PM_DERAT_MISS_64K ] = { .pme_name = "PM_DERAT_MISS_64K", .pme_code = 0x292070, .pme_short_desc = "DERAT misses for 64K page", .pme_long_desc = "A data request (load or store) missed the ERAT for 64K page and resulted in an ERAT reload.", }, [ POWER6_PME_PM_PMC2_REWIND ] = { .pme_name = "PM_PMC2_REWIND", .pme_code = 0x300020, .pme_short_desc = "PMC2 rewind event", .pme_long_desc = "PMC2 rewind event", }, [ POWER6_PME_PM_INST_FROM_L2 ] = { .pme_name = "PM_INST_FROM_L2", .pme_code = 0x142040, .pme_short_desc = "Instructions fetched from L2", .pme_long_desc = "An instruction fetch group was fetched from L2. Fetch Groups can contain up to 8 instructions", }, [ POWER6_PME_PM_INST_DISP ] = { .pme_name = "PM_INST_DISP", .pme_code = 0x200012, .pme_short_desc = "Instructions dispatched", .pme_long_desc = "The ISU sends the number of instructions dispatched.", }, [ POWER6_PME_PM_DATA_FROM_L25_SHR ] = { .pme_name = "PM_DATA_FROM_L25_SHR", .pme_code = 0x40005a, .pme_short_desc = "Data loaded from L2.5 shared", .pme_long_desc = "DL1 was reloaded with shared (T or SL) data from the L2 of a chip on this MCM due to a demand load", }, [ POWER6_PME_PM_L1_DCACHE_RELOAD_VALID ] = { .pme_name = "PM_L1_DCACHE_RELOAD_VALID", .pme_code = 0x3000f6, .pme_short_desc = "L1 reload data source valid", .pme_long_desc = "The data source information is valid", }, [ POWER6_PME_PM_LSU1_REJECT_UST ] = { .pme_name = "PM_LSU1_REJECT_UST", .pme_code = 0x9008a, .pme_short_desc = "LSU1 unaligned store reject", .pme_long_desc = "LSU1 unaligned store reject", }, [ POWER6_PME_PM_FAB_ADDR_COLLISION ] = { .pme_name = "PM_FAB_ADDR_COLLISION", .pme_code = 0x5018e, .pme_short_desc = "local node launch collision with off-node address ", .pme_long_desc = "local node launch collision with off-node address ", }, [ POWER6_PME_PM_MRK_FXU_FIN ] = { .pme_name = "PM_MRK_FXU_FIN", .pme_code = 0x20001a, .pme_short_desc = "Marked instruction FXU processing finished", .pme_long_desc = "The fixed point units (Unit 0 + Unit 1) finished a marked instruction. Instructions that finish may not necessary complete.", }, [ POWER6_PME_PM_LSU0_REJECT_UST ] = { .pme_name = "PM_LSU0_REJECT_UST", .pme_code = 0x90082, .pme_short_desc = "LSU0 unaligned store reject", .pme_long_desc = "LSU0 unaligned store reject", }, [ POWER6_PME_PM_PMC4_OVERFLOW ] = { .pme_name = "PM_PMC4_OVERFLOW", .pme_code = 0x100014, .pme_short_desc = "PMC4 Overflow", .pme_long_desc = "PMC4 Overflow", }, [ POWER6_PME_PM_MRK_PTEG_FROM_L3 ] = { .pme_name = "PM_MRK_PTEG_FROM_L3", .pme_code = 0x312040, .pme_short_desc = "Marked PTEG loaded from L3", .pme_long_desc = "Marked PTEG loaded from L3", }, [ POWER6_PME_PM_INST_FROM_L2MISS ] = { .pme_name = "PM_INST_FROM_L2MISS", .pme_code = 0x442054, .pme_short_desc = "Instructions fetched missed L2", .pme_long_desc = "An instruction fetch group was fetched from beyond L2.", }, [ POWER6_PME_PM_L2SB_ST_HIT ] = { .pme_name = "PM_L2SB_ST_HIT", .pme_code = 0x5078e, .pme_short_desc = "L2 slice B store hits", .pme_long_desc = "A store request made from the core hit in the L2 directory. This event is provided on each of the three L2 slices A,B, and C.", }, [ POWER6_PME_PM_DPU_WT_IC_MISS_COUNT ] = { .pme_name = "PM_DPU_WT_IC_MISS_COUNT", .pme_code = 0x20000d, .pme_short_desc = "Periods DISP unit is stalled due to I cache miss", .pme_long_desc = "Periods DISP unit is stalled due to I cache miss", }, [ POWER6_PME_PM_MRK_DATA_FROM_DL2L3_SHR ] = { .pme_name = "PM_MRK_DATA_FROM_DL2L3_SHR", .pme_code = 0x30304c, .pme_short_desc = "Marked data loaded from distant L2 or L3 shared", .pme_long_desc = "Marked data loaded from distant L2 or L3 shared", }, [ POWER6_PME_PM_MRK_PTEG_FROM_L35_MOD ] = { .pme_name = "PM_MRK_PTEG_FROM_L35_MOD", .pme_code = 0x112046, .pme_short_desc = "Marked PTEG loaded from L3.5 modified", .pme_long_desc = "Marked PTEG loaded from L3.5 modified", }, [ POWER6_PME_PM_FPU1_FPSCR ] = { .pme_name = "PM_FPU1_FPSCR", .pme_code = 0xd008c, .pme_short_desc = "FPU1 executed FPSCR instruction", .pme_long_desc = "FPU1 executed FPSCR instruction", }, [ POWER6_PME_PM_LSU_REJECT_UST ] = { .pme_name = "PM_LSU_REJECT_UST", .pme_code = 0x290030, .pme_short_desc = "Unaligned store reject", .pme_long_desc = "Unaligned store reject", }, [ POWER6_PME_PM_LSU0_DERAT_MISS ] = { .pme_name = "PM_LSU0_DERAT_MISS", .pme_code = 0x910a6, .pme_short_desc = "LSU0 DERAT misses", .pme_long_desc = "A data request (load or store) from LSU Unit 0 missed the ERAT and resulted in an ERAT reload. Multiple instructions may miss the ERAT entry for the same 4K page, but only one reload will occur.", }, [ POWER6_PME_PM_MRK_PTEG_FROM_MEM_DP ] = { .pme_name = "PM_MRK_PTEG_FROM_MEM_DP", .pme_code = 0x112042, .pme_short_desc = "Marked PTEG loaded from double pump memory", .pme_long_desc = "Marked PTEG loaded from double pump memory", }, [ POWER6_PME_PM_MRK_DATA_FROM_L2 ] = { .pme_name = "PM_MRK_DATA_FROM_L2", .pme_code = 0x103048, .pme_short_desc = "Marked data loaded from L2", .pme_long_desc = "DL1 was reloaded from the local L2 due to a marked demand load", }, [ POWER6_PME_PM_FPU0_FSQRT_FDIV ] = { .pme_name = "PM_FPU0_FSQRT_FDIV", .pme_code = 0xc0084, .pme_short_desc = "FPU0 executed FSQRT or FDIV instruction", .pme_long_desc = "FPU0 executed FSQRT or FDIV instruction", }, [ POWER6_PME_PM_DPU_HELD_FXU_SOPS ] = { .pme_name = "PM_DPU_HELD_FXU_SOPS", .pme_code = 0x30088, .pme_short_desc = "DISP unit held due to FXU slow ops (mtmsr, scv, rfscv)", .pme_long_desc = "DISP unit held due to FXU slow ops (mtmsr, scv, rfscv)", }, [ POWER6_PME_PM_MRK_FPU0_FIN ] = { .pme_name = "PM_MRK_FPU0_FIN", .pme_code = 0xd0082, .pme_short_desc = "Marked instruction FPU0 processing finished", .pme_long_desc = "Marked instruction FPU0 processing finished", }, [ POWER6_PME_PM_L2SB_LD_MISS_DATA ] = { .pme_name = "PM_L2SB_LD_MISS_DATA", .pme_code = 0x5048a, .pme_short_desc = "L2 slice B data load misses", .pme_long_desc = "L2 slice B data load misses", }, [ POWER6_PME_PM_LSU_SRQ_EMPTY_CYC ] = { .pme_name = "PM_LSU_SRQ_EMPTY_CYC", .pme_code = 0x40001c, .pme_short_desc = "Cycles SRQ empty", .pme_long_desc = "The Store Request Queue is empty", }, [ POWER6_PME_PM_1PLUS_PPC_DISP ] = { .pme_name = "PM_1PLUS_PPC_DISP", .pme_code = 0x100012, .pme_short_desc = "Cycles at least one instruction dispatched", .pme_long_desc = "Cycles at least one instruction dispatched", }, [ POWER6_PME_PM_VMX_ST_ISSUED ] = { .pme_name = "PM_VMX_ST_ISSUED", .pme_code = 0xb0080, .pme_short_desc = "VMX store issued", .pme_long_desc = "VMX store issued", }, [ POWER6_PME_PM_DATA_FROM_L2MISS ] = { .pme_name = "PM_DATA_FROM_L2MISS", .pme_code = 0x2000fe, .pme_short_desc = "Data loaded missed L2", .pme_long_desc = "DL1 was reloaded from beyond L2.", }, [ POWER6_PME_PM_LSU0_REJECT_ULD ] = { .pme_name = "PM_LSU0_REJECT_ULD", .pme_code = 0x90080, .pme_short_desc = "LSU0 unaligned load reject", .pme_long_desc = "LSU0 unaligned load reject", }, [ POWER6_PME_PM_SUSPENDED ] = { .pme_name = "PM_SUSPENDED", .pme_code = 0x0, .pme_short_desc = "Suspended", .pme_long_desc = "Suspended", }, [ POWER6_PME_PM_DFU_ADD_SHIFTED_BOTH ] = { .pme_name = "PM_DFU_ADD_SHIFTED_BOTH", .pme_code = 0xe0088, .pme_short_desc = "DFU add type with both operands shifted", .pme_long_desc = "DFU add type with both operands shifted", }, [ POWER6_PME_PM_LSU_REJECT_NO_SCRATCH ] = { .pme_name = "PM_LSU_REJECT_NO_SCRATCH", .pme_code = 0x2a1034, .pme_short_desc = "LSU reject due to scratch register not available", .pme_long_desc = "LSU reject due to scratch register not available", }, [ POWER6_PME_PM_STCX_FAIL ] = { .pme_name = "PM_STCX_FAIL", .pme_code = 0x830ee, .pme_short_desc = "STCX failed", .pme_long_desc = "A stcx (stwcx or stdcx) failed", }, [ POWER6_PME_PM_FPU1_DENORM ] = { .pme_name = "PM_FPU1_DENORM", .pme_code = 0xc10aa, .pme_short_desc = "FPU1 received denormalized data", .pme_long_desc = "This signal is active for one cycle when one of the operands is denormalized.", }, [ POWER6_PME_PM_GCT_NOSLOT_COUNT ] = { .pme_name = "PM_GCT_NOSLOT_COUNT", .pme_code = 0x100009, .pme_short_desc = "Periods no GCT slot allocated", .pme_long_desc = "Periods this thread does not have any slots allocated in the GCT.", }, [ POWER6_PME_PM_DATA_FROM_DL2L3_SHR_CYC ] = { .pme_name = "PM_DATA_FROM_DL2L3_SHR_CYC", .pme_code = 0x20002a, .pme_short_desc = "Load latency from distant L2 or L3 shared", .pme_long_desc = "Load latency from distant L2 or L3 shared", }, [ POWER6_PME_PM_DATA_FROM_L21 ] = { .pme_name = "PM_DATA_FROM_L21", .pme_code = 0x200058, .pme_short_desc = "Data loaded from private L2 other core", .pme_long_desc = "Data loaded from private L2 other core", }, [ POWER6_PME_PM_FPU_1FLOP ] = { .pme_name = "PM_FPU_1FLOP", .pme_code = 0x1c0030, .pme_short_desc = "FPU executed one flop instruction ", .pme_long_desc = "This event counts the number of one flop instructions. These could be fadd*, fmul*, fsub*, fneg+, fabs+, fnabs+, fres+, frsqrte+, fcmp**, or fsel where XYZ* means XYZ, XYZs, XYZ., XYZs., XYZ+ means XYZ, XYZ., and XYZ** means XYZu, XYZo.", }, [ POWER6_PME_PM_LSU1_REJECT ] = { .pme_name = "PM_LSU1_REJECT", .pme_code = 0xa10ae, .pme_short_desc = "LSU1 reject", .pme_long_desc = "LSU1 reject", }, [ POWER6_PME_PM_IC_REQ ] = { .pme_name = "PM_IC_REQ", .pme_code = 0x4008a, .pme_short_desc = "I cache demand of prefetch request", .pme_long_desc = "I cache demand of prefetch request", }, [ POWER6_PME_PM_MRK_DFU_FIN ] = { .pme_name = "PM_MRK_DFU_FIN", .pme_code = 0x300008, .pme_short_desc = "DFU marked instruction finish", .pme_long_desc = "DFU marked instruction finish", }, [ POWER6_PME_PM_NOT_LLA_CYC ] = { .pme_name = "PM_NOT_LLA_CYC", .pme_code = 0x401e, .pme_short_desc = "Load Look Ahead not Active", .pme_long_desc = "Load Look Ahead not Active", }, [ POWER6_PME_PM_INST_FROM_L1 ] = { .pme_name = "PM_INST_FROM_L1", .pme_code = 0x40082, .pme_short_desc = "Instruction fetched from L1", .pme_long_desc = "An instruction fetch group was fetched from L1. Fetch Groups can contain up to 8 instructions", }, [ POWER6_PME_PM_MRK_VMX_COMPLEX_ISSUED ] = { .pme_name = "PM_MRK_VMX_COMPLEX_ISSUED", .pme_code = 0x7008c, .pme_short_desc = "Marked VMX instruction issued to complex", .pme_long_desc = "Marked VMX instruction issued to complex", }, [ POWER6_PME_PM_BRU_FIN ] = { .pme_name = "PM_BRU_FIN", .pme_code = 0x430e6, .pme_short_desc = "BRU produced a result", .pme_long_desc = "BRU produced a result", }, [ POWER6_PME_PM_LSU1_REJECT_EXTERN ] = { .pme_name = "PM_LSU1_REJECT_EXTERN", .pme_code = 0xa10ac, .pme_short_desc = "LSU1 external reject request ", .pme_long_desc = "LSU1 external reject request ", }, [ POWER6_PME_PM_DATA_FROM_L21_CYC ] = { .pme_name = "PM_DATA_FROM_L21_CYC", .pme_code = 0x400020, .pme_short_desc = "Load latency from private L2 other core", .pme_long_desc = "Load latency from private L2 other core", }, [ POWER6_PME_PM_GXI_CYC_BUSY ] = { .pme_name = "PM_GXI_CYC_BUSY", .pme_code = 0x50386, .pme_short_desc = "Inbound GX bus utilizations (# of cycles in use)", .pme_long_desc = "Inbound GX bus utilizations (# of cycles in use)", }, [ POWER6_PME_PM_MRK_LD_MISS_L1 ] = { .pme_name = "PM_MRK_LD_MISS_L1", .pme_code = 0x200056, .pme_short_desc = "Marked L1 D cache load misses", .pme_long_desc = "Marked L1 D cache load misses", }, [ POWER6_PME_PM_L1_WRITE_CYC ] = { .pme_name = "PM_L1_WRITE_CYC", .pme_code = 0x430e2, .pme_short_desc = "Cycles writing to instruction L1", .pme_long_desc = "This signal is asserted each cycle a cache write is active.", }, [ POWER6_PME_PM_LLA_CYC ] = { .pme_name = "PM_LLA_CYC", .pme_code = 0xc01e, .pme_short_desc = "Load Look Ahead Active", .pme_long_desc = "Load Look Ahead Active", }, [ POWER6_PME_PM_MRK_DATA_FROM_L2MISS ] = { .pme_name = "PM_MRK_DATA_FROM_L2MISS", .pme_code = 0x103028, .pme_short_desc = "Marked data loaded missed L2", .pme_long_desc = "DL1 was reloaded from beyond L2 due to a marked demand load.", }, [ POWER6_PME_PM_GCT_FULL_COUNT ] = { .pme_name = "PM_GCT_FULL_COUNT", .pme_code = 0x40087, .pme_short_desc = "Periods GCT full", .pme_long_desc = "The ISU sends a signal indicating the gct is full.", }, [ POWER6_PME_PM_MEM_DP_RQ_LOC_GLOB ] = { .pme_name = "PM_MEM_DP_RQ_LOC_GLOB", .pme_code = 0x250230, .pme_short_desc = "Memory read queue marking cache line double pump state from local to global", .pme_long_desc = "Memory read queue marking cache line double pump state from local to global", }, [ POWER6_PME_PM_DATA_FROM_RL2L3_SHR ] = { .pme_name = "PM_DATA_FROM_RL2L3_SHR", .pme_code = 0x20005c, .pme_short_desc = "Data loaded from remote L2 or L3 shared", .pme_long_desc = "Data loaded from remote L2 or L3 shared", }, [ POWER6_PME_PM_MRK_LSU_REJECT_UST ] = { .pme_name = "PM_MRK_LSU_REJECT_UST", .pme_code = 0x293034, .pme_short_desc = "Marked unaligned store reject", .pme_long_desc = "Marked unaligned store reject", }, [ POWER6_PME_PM_MRK_VMX_PERMUTE_ISSUED ] = { .pme_name = "PM_MRK_VMX_PERMUTE_ISSUED", .pme_code = 0x7008e, .pme_short_desc = "Marked VMX instruction issued to permute", .pme_long_desc = "Marked VMX instruction issued to permute", }, [ POWER6_PME_PM_MRK_PTEG_FROM_L21 ] = { .pme_name = "PM_MRK_PTEG_FROM_L21", .pme_code = 0x212040, .pme_short_desc = "Marked PTEG loaded from private L2 other core", .pme_long_desc = "Marked PTEG loaded from private L2 other core", }, [ POWER6_PME_PM_THRD_GRP_CMPL_BOTH_CYC ] = { .pme_name = "PM_THRD_GRP_CMPL_BOTH_CYC", .pme_code = 0x200018, .pme_short_desc = "Cycles group completed by both threads", .pme_long_desc = "Cycles group completed by both threads", }, [ POWER6_PME_PM_BR_MPRED ] = { .pme_name = "PM_BR_MPRED", .pme_code = 0x400052, .pme_short_desc = "Branches incorrectly predicted", .pme_long_desc = "Branches incorrectly predicted", }, [ POWER6_PME_PM_LD_REQ_L2 ] = { .pme_name = "PM_LD_REQ_L2", .pme_code = 0x150730, .pme_short_desc = "L2 load requests ", .pme_long_desc = "L2 load requests ", }, [ POWER6_PME_PM_FLUSH_ASYNC ] = { .pme_name = "PM_FLUSH_ASYNC", .pme_code = 0x220ca, .pme_short_desc = "Flush caused by asynchronous exception", .pme_long_desc = "Flush caused by asynchronous exception", }, [ POWER6_PME_PM_HV_CYC ] = { .pme_name = "PM_HV_CYC", .pme_code = 0x200016, .pme_short_desc = "Hypervisor Cycles", .pme_long_desc = "Cycles when the processor is executing in Hypervisor (MSR[HV] = 1 and MSR[PR]=0)", }, [ POWER6_PME_PM_LSU1_DERAT_MISS ] = { .pme_name = "PM_LSU1_DERAT_MISS", .pme_code = 0x910ae, .pme_short_desc = "LSU1 DERAT misses", .pme_long_desc = "A data request (load or store) from LSU Unit 1 missed the ERAT and resulted in an ERAT reload. Multiple instructions may miss the ERAT entry for the same 4K page, but only one reload will occur.", }, [ POWER6_PME_PM_DPU_HELD_SMT ] = { .pme_name = "PM_DPU_HELD_SMT", .pme_code = 0x20082, .pme_short_desc = "DISP unit held due to SMT conflicts ", .pme_long_desc = "DISP unit held due to SMT conflicts ", }, [ POWER6_PME_PM_MRK_LSU_FIN ] = { .pme_name = "PM_MRK_LSU_FIN", .pme_code = 0x40001a, .pme_short_desc = "Marked instruction LSU processing finished", .pme_long_desc = "One of the Load/Store Units finished a marked instruction. Instructions that finish may not necessary complete", }, [ POWER6_PME_PM_MRK_DATA_FROM_RL2L3_SHR ] = { .pme_name = "PM_MRK_DATA_FROM_RL2L3_SHR", .pme_code = 0x20304c, .pme_short_desc = "Marked data loaded from remote L2 or L3 shared", .pme_long_desc = "Marked data loaded from remote L2 or L3 shared", }, [ POWER6_PME_PM_LSU0_REJECT_STQ_FULL ] = { .pme_name = "PM_LSU0_REJECT_STQ_FULL", .pme_code = 0xa0080, .pme_short_desc = "LSU0 reject due to store queue full", .pme_long_desc = "LSU0 reject due to store queue full", }, [ POWER6_PME_PM_MRK_DERAT_REF_4K ] = { .pme_name = "PM_MRK_DERAT_REF_4K", .pme_code = 0x282044, .pme_short_desc = "Marked DERAT reference for 4K page", .pme_long_desc = "Marked DERAT reference for 4K page", }, [ POWER6_PME_PM_FPU_ISSUE_STALL_FPR ] = { .pme_name = "PM_FPU_ISSUE_STALL_FPR", .pme_code = 0x330e2, .pme_short_desc = "FPU issue stalled due to FPR dependencies", .pme_long_desc = "FPU issue stalled due to FPR dependencies", }, [ POWER6_PME_PM_IFU_FIN ] = { .pme_name = "PM_IFU_FIN", .pme_code = 0x430e4, .pme_short_desc = "IFU finished an instruction", .pme_long_desc = "IFU finished an instruction", }, [ POWER6_PME_PM_GXO_CYC_BUSY ] = { .pme_name = "PM_GXO_CYC_BUSY", .pme_code = 0x50380, .pme_short_desc = "Outbound GX bus utilizations (# of cycles in use)", .pme_long_desc = "Outbound GX bus utilizations (# of cycles in use)", } }; #endif libpfm-4.9.0/lib/events/intel_bdx_unc_sbo_events.h0000664000175000017500000003173313223402656022114 0ustar eranianeranian/* * Copyright (c) 2017 Google Inc. All rights reserved * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * PMU: bdx_unc_sbo */ static intel_x86_umask_t bdx_unc_s_ring_ad_used[]={ { .uname = "DOWN_EVEN", .ucode = 0x400, .udesc = "Down and Event", }, { .uname = "DOWN_ODD", .ucode = 0x800, .udesc = "Down and Odd", }, { .uname = "UP_EVEN", .ucode = 0x100, .udesc = "Up and Even", }, { .uname = "UP_ODD", .ucode = 0x200, .udesc = "Up and Odd", }, { .uname = "UP", .ucode = 0x300, .udesc = "Up", .uflags= INTEL_X86_NCOMBO, }, { .uname = "DOWN", .ucode = 0xcc00, .udesc = "Down", .uflags= INTEL_X86_NCOMBO, }, }; static intel_x86_umask_t bdx_unc_s_ring_bounces[]={ { .uname = "AD_CACHE", .ucode = 0x100, .udesc = "Number of LLC responses that bounced on the Ring. -- ", }, { .uname = "AK_CORE", .ucode = 0x200, .udesc = "Number of LLC responses that bounced on the Ring. -- Acknowledgements to core", }, { .uname = "BL_CORE", .ucode = 0x400, .udesc = "Number of LLC responses that bounced on the Ring. -- Data Responses to core", }, { .uname = "IV_CORE", .ucode = 0x800, .udesc = "Number of LLC responses that bounced on the Ring. -- Snoops of processors cachee.", }, }; static intel_x86_umask_t bdx_unc_s_ring_iv_used[]={ { .uname = "DN", .ucode = 0xc00, .udesc = "BL Ring in Use -- Any", .uflags= INTEL_X86_NCOMBO, }, { .uname = "UP", .ucode = 0x300, .udesc = "BL Ring in Use -- Any", .uflags= INTEL_X86_NCOMBO, }, }; static intel_x86_umask_t bdx_unc_s_rxr_bypass[]={ { .uname = "AD_BNC", .ucode = 0x200, .udesc = "Bypass -- AD - Bounces", .uflags= INTEL_X86_NCOMBO, }, { .uname = "AD_CRD", .ucode = 0x100, .udesc = "Bypass -- AD - Credits", .uflags= INTEL_X86_NCOMBO, }, { .uname = "AK", .ucode = 0x1000, .udesc = "Bypass -- AK", .uflags= INTEL_X86_NCOMBO, }, { .uname = "BL_BNC", .ucode = 0x800, .udesc = "Bypass -- BL - Bounces", .uflags= INTEL_X86_NCOMBO, }, { .uname = "BL_CRD", .ucode = 0x400, .udesc = "Bypass -- BL - Credits", .uflags= INTEL_X86_NCOMBO, }, { .uname = "IV", .ucode = 0x2000, .udesc = "Bypass -- IV", .uflags= INTEL_X86_NCOMBO, }, }; static intel_x86_umask_t bdx_unc_s_rxr_inserts[]={ { .uname = "AD_BNC", .ucode = 0x200, .udesc = "Ingress Allocations -- AD - Bounces", }, { .uname = "AD_CRD", .ucode = 0x100, .udesc = "Ingress Allocations -- AD - Credits", }, { .uname = "AK", .ucode = 0x1000, .udesc = "Ingress Allocations -- AK", }, { .uname = "BL_BNC", .ucode = 0x800, .udesc = "Ingress Allocations -- BL - Bounces", }, { .uname = "BL_CRD", .ucode = 0x400, .udesc = "Ingress Allocations -- BL - Credits", }, { .uname = "IV", .ucode = 0x2000, .udesc = "Ingress Allocations -- IV", }, }; static intel_x86_umask_t bdx_unc_s_rxr_occupancy[]={ { .uname = "AD_BNC", .ucode = 0x200, .udesc = "Ingress Occupancy -- AD - Bounces", .uflags= INTEL_X86_NCOMBO, }, { .uname = "AD_CRD", .ucode = 0x100, .udesc = "Ingress Occupancy -- AD - Credits", .uflags= INTEL_X86_NCOMBO, }, { .uname = "AK", .ucode = 0x1000, .udesc = "Ingress Occupancy -- AK", .uflags= INTEL_X86_NCOMBO, }, { .uname = "BL_BNC", .ucode = 0x800, .udesc = "Ingress Occupancy -- BL - Bounces", .uflags= INTEL_X86_NCOMBO, }, { .uname = "BL_CRD", .ucode = 0x400, .udesc = "Ingress Occupancy -- BL - Credits", .uflags= INTEL_X86_NCOMBO, }, { .uname = "IV", .ucode = 0x2000, .udesc = "Ingress Occupancy -- IV", .uflags= INTEL_X86_NCOMBO, }, }; static intel_x86_umask_t bdx_unc_s_txr_ads_used[]={ { .uname = "AD", .ucode = 0x100, .udesc = "TBD", }, { .uname = "AK", .ucode = 0x200, .udesc = "TBD", }, { .uname = "BL", .ucode = 0x400, .udesc = "TBD", }, }; static intel_x86_umask_t bdx_unc_s_txr_inserts[]={ { .uname = "AD_BNC", .ucode = 0x200, .udesc = "Egress Allocations -- AD - Bounces", }, { .uname = "AD_CRD", .ucode = 0x100, .udesc = "Egress Allocations -- AD - Credits", }, { .uname = "AK", .ucode = 0x1000, .udesc = "Egress Allocations -- AK", }, { .uname = "BL_BNC", .ucode = 0x800, .udesc = "Egress Allocations -- BL - Bounces", }, { .uname = "BL_CRD", .ucode = 0x400, .udesc = "Egress Allocations -- BL - Credits", }, { .uname = "IV", .ucode = 0x2000, .udesc = "Egress Allocations -- IV", }, }; static intel_x86_umask_t bdx_unc_s_txr_occupancy[]={ { .uname = "AD_BNC", .ucode = 0x200, .udesc = "Egress Occupancy -- AD - Bounces", }, { .uname = "AD_CRD", .ucode = 0x100, .udesc = "Egress Occupancy -- AD - Credits", }, { .uname = "AK", .ucode = 0x1000, .udesc = "Egress Occupancy -- AK", }, { .uname = "BL_BNC", .ucode = 0x800, .udesc = "Egress Occupancy -- BL - Bounces", }, { .uname = "BL_CRD", .ucode = 0x400, .udesc = "Egress Occupancy -- BL - Credits", }, { .uname = "IV", .ucode = 0x2000, .udesc = "Egress Occupancy -- IV", }, }; static intel_x86_umask_t bdx_unc_s_txr_ordering[]={ { .uname = "IVSNOOPGO_UP", .ucode = 0x100, .udesc = "TBD", }, { .uname = "IVSNOOP_DN", .ucode = 0x200, .udesc = "TBD", }, { .uname = "AK_U2C_UP_EVEN", .ucode = 0x400, .udesc = "TBD", }, { .uname = "AK_U2C_UP_ODD", .ucode = 0x800, .udesc = "TBD", }, { .uname = "AK_U2C_DN_EVEN", .ucode = 0x1000, .udesc = "TBD", }, { .uname = "AK_U2C_DN_ODD", .ucode = 0x2000, .udesc = "TBD", }, }; static intel_x86_entry_t intel_bdx_unc_s_pe[]={ { .name = "UNC_S_BOUNCE_CONTROL", .code = 0xa, .desc = "TBD", .modmsk = BDX_UNC_SBO_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_S_CLOCKTICKS", .code = 0x0, .desc = "TBD", .modmsk = BDX_UNC_SBO_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_S_FAST_ASSERTED", .code = 0x9, .desc = "Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across.", .modmsk = BDX_UNC_SBO_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_S_RING_AD_USED", .code = 0x1b, .desc = "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the rhe ring.", .modmsk = BDX_UNC_SBO_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_s_ring_ad_used, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_s_ring_ad_used), }, { .name = "UNC_S_RING_AK_USED", .code = 0x1c, .desc = "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the rhe ring.", .modmsk = BDX_UNC_SBO_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_s_ring_ad_used, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_s_ring_ad_used), }, { .name = "UNC_S_RING_BL_USED", .code = 0x1d, .desc = "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the rhe ring.", .modmsk = BDX_UNC_SBO_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_s_ring_ad_used, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_s_ring_ad_used), }, { .name = "UNC_S_RING_BOUNCES", .code = 0x5, .desc = "TBD", .modmsk = BDX_UNC_SBO_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_s_ring_bounces, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_s_ring_bounces), }, { .name = "UNC_S_RING_IV_USED", .code = 0x1e, .desc = "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. There is only 1 IV ring in BDX. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ DN_ODD.", .modmsk = BDX_UNC_SBO_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_s_ring_iv_used, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_s_ring_iv_used), }, { .name = "UNC_S_RXR_BYPASS", .code = 0x12, .desc = "Bypass the Sbo Ingress.", .modmsk = BDX_UNC_SBO_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_s_rxr_bypass, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_s_rxr_bypass), }, { .name = "UNC_S_RXR_INSERTS", .code = 0x13, .desc = "Number of allocations into the Sbo Ingress The Ingress is used to queue up requests received from the ring.", .modmsk = BDX_UNC_SBO_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_s_rxr_inserts, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_s_rxr_inserts), }, { .name = "UNC_S_RXR_OCCUPANCY", .code = 0x11, .desc = "Occupancy event for the Ingress buffers in the Sbo. The Ingress is used to queue up requests received from the ring.", .modmsk = BDX_UNC_SBO_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_s_rxr_occupancy, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_s_rxr_occupancy), }, { .name = "UNC_S_TXR_ADS_USED", .code = 0x4, .desc = "", .modmsk = BDX_UNC_SBO_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_s_txr_ads_used, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_s_txr_ads_used), }, { .name = "UNC_S_TXR_INSERTS", .code = 0x2, .desc = "Number of allocations into the Sbo Egress. The Egress is used to queue up requests destined for the ring.", .modmsk = BDX_UNC_SBO_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_s_txr_inserts, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_s_txr_inserts), }, { .name = "UNC_S_TXR_OCCUPANCY", .code = 0x1, .desc = "Occupancy event for the Egress buffers in the Sbo. The egress is used to queue up requests destined for the ring.", .modmsk = BDX_UNC_SBO_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_s_txr_occupancy, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_s_txr_occupancy), }, { .name = "UNC_S_TXR_ORDERING", .code = 0x7, .desc = "TB", .modmsk = BDX_UNC_SBO_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_s_txr_ordering, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_s_txr_ordering), }, }; libpfm-4.9.0/lib/events/intel_skl_events.h0000664000175000017500000030170413223402656020416 0ustar eranianeranian/* * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * PMU: skl (Intel SkyLake) */ static const intel_x86_umask_t skl_baclears[]={ { .uname = "ANY", .udesc = "Number of front-end re-steers due to BPU misprediction", .ucode = 0x0100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t skl_br_inst_retired[]={ { .uname = "CONDITIONAL", .udesc = "Counts all taken and not taken macro conditional branch instructions", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "COND", .udesc = "Counts all taken and not taken macro conditional branch instructions", .ucode = 0x100, .uequiv = "CONDITIONAL", .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "NEAR_CALL", .udesc = "Counts all macro direct and indirect near calls", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "ALL_BRANCHES", .udesc = "Counts all taken and not taken macro branches including far branches (architectural event)", .ucode = 0x0, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL | INTEL_X86_PEBS, }, { .uname = "NEAR_RETURN", .udesc = "Counts the number of near ret instructions retired", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "NOT_TAKEN", .udesc = "Counts all not taken macro branch instructions retired", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "NEAR_TAKEN", .udesc = "Counts the number of near branch taken instructions retired", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "FAR_BRANCH", .udesc = "Counts the number of far branch instructions retired", .ucode = 0x4000, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, }; static const intel_x86_umask_t skl_br_misp_retired[]={ { .uname = "CONDITIONAL", .udesc = "All mispredicted macro conditional branch instructions", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "COND", .udesc = "All mispredicted macro conditional branch instructions", .ucode = 0x100, .uequiv = "CONDITIONAL", .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "ALL_BRANCHES", .udesc = "All mispredicted macro branches (architectural event)", .ucode = 0x0, /* architectural encoding */ .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS | INTEL_X86_DFL, }, { .uname = "NEAR_TAKEN", .udesc = "Number of near branch instructions retired that were mispredicted and taken", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "NEAR_CALL", .udesc = "Counts both taken and not taken retired mispredicted direct and indirect near calls, including both register and memory indirect.", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, }; static const intel_x86_umask_t skl_cpu_clk_thread_unhalted[]={ { .uname = "REF_XCLK", .udesc = "Count Xclk pulses (100Mhz) when the core is unhalted", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "REF_XCLK_ANY", .udesc = "Count Xclk pulses (100Mhz) when the at least one thread on the physical core is unhalted", .ucode = 0x100 | INTEL_X86_MOD_ANY, /* any=1 */ .uequiv = "REF_XCLK:t", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_T, }, { .uname = "REF_P", .udesc = "Cycles when the core is unhalted (count at 100 Mhz)", .ucode = 0x100, .uequiv = "REF_XCLK", .uflags= INTEL_X86_NCOMBO, }, { .uname = "THREAD_P", .udesc = "Cycles when thread is not halted", .ucode = 0x000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "ONE_THREAD_ACTIVE", .udesc = "Counts Xclk (100Mhz) pulses when this thread is unhalted and the other thread is halted", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "RING0_TRANS", .udesc = "Counts when the current privilege level transitions from ring 1, 2 or 3 to ring 0 (kernel)", .ucode = 0x000 | INTEL_X86_MOD_EDGE | (1 << INTEL_X86_CMASK_BIT), /* edge=1 cnt=1 */ .uequiv = "THREAD_P:e:c=1", .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t skl_cycle_activity[]={ { .uname = "CYCLES_L2_MISS", .udesc = "Cycles with pending L2 miss demand loads outstanding", .ucode = 0x0100 | (0x1 << INTEL_X86_CMASK_BIT), .modhw = _INTEL_X86_ATTR_C, .uflags = INTEL_X86_NCOMBO, }, { .uname = "CYCLES_L2_PENDING", .udesc = "Cycles with pending L2 miss demand loads outstanding", .ucode = 0x0100 | (0x1 << INTEL_X86_CMASK_BIT), .modhw = _INTEL_X86_ATTR_C, .uflags = INTEL_X86_NCOMBO, .uequiv = "CYCLES_L2_MISS", }, { .uname = "CYCLES_L3_MISS", .udesc = "Cycles with L3 cache miss demand loads outstanding", .ucode = 0x0200 | (0x2 << INTEL_X86_CMASK_BIT), .modhw = _INTEL_X86_ATTR_C, .uflags = INTEL_X86_NCOMBO, }, { .uname = "CYCLES_LDM_PENDING", .udesc = "Cycles with L3 cache miss demand loads outstanding", .ucode = 0x0200 | (0x2 << INTEL_X86_CMASK_BIT), .uequiv = "CYCLES_L3_MISS", .modhw = _INTEL_X86_ATTR_C, .uflags = INTEL_X86_NCOMBO, }, { .uname = "CYCLES_L1D_MISS", .udesc = "Cycles with pending L1D load cache misses", .ucode = 0x0800 | (0x8 << INTEL_X86_CMASK_BIT), .modhw = _INTEL_X86_ATTR_C, .uflags = INTEL_X86_NCOMBO, }, { .uname = "CYCLES_L1D_PENDING", .udesc = "Cycles with pending L1D load cache misses", .ucode = 0x0800 | (0x8 << INTEL_X86_CMASK_BIT), .uequiv = "CYCLES_L1D_MISS", .modhw = _INTEL_X86_ATTR_C, .uflags = INTEL_X86_NCOMBO, }, { .uname = "CYCLES_MEM_ANY", .udesc = "Cycles when memory subsystem has at least one outstanding load", .ucode = 0x1000 | (0x10 << INTEL_X86_CMASK_BIT), .modhw = _INTEL_X86_ATTR_C, .uflags = INTEL_X86_NCOMBO, }, { .uname = "STALLS_L1D_MISS", .udesc = "Execution stalls while at least one L1D demand load cache miss is outstanding", .ucode = 0x0c00 | (0xc << INTEL_X86_CMASK_BIT), .modhw = _INTEL_X86_ATTR_C, .ucntmsk= 0x4, .uflags = INTEL_X86_NCOMBO, }, { .uname = "STALLS_L2_MISS", .udesc = "Execution stalls while at least one L2 demand load is outstanding", .ucode = 0x0500 | (0x5 << INTEL_X86_CMASK_BIT), .modhw = _INTEL_X86_ATTR_C, .ucntmsk= 0xf, .uflags = INTEL_X86_NCOMBO, }, { .uname = "STALLS_L3_MISS", .udesc = "Execution stalls while at least one L3 demand load is outstanding", .ucode = 0x0600 | (0x6 << INTEL_X86_CMASK_BIT), .modhw = _INTEL_X86_ATTR_C, .uflags = INTEL_X86_NCOMBO, }, { .uname = "STALLS_MEM_ANY", .udesc = "Execution stalls while at least one demand load is outstanding in the memory subsystem", .ucode = 0x1400 | (20 << INTEL_X86_CMASK_BIT), /* cnt=20 */ .modhw = _INTEL_X86_ATTR_C, .uflags = INTEL_X86_NCOMBO, }, { .uname = "STALLS_TOTAL", .udesc = "Total execution stalls in cycles", .ucode = 0x0400 | (0x4 << INTEL_X86_CMASK_BIT), .modhw = _INTEL_X86_ATTR_C, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t skl_dtlb_load_misses[]={ { .uname = "MISS_CAUSES_A_WALK", .udesc = "Misses in all DTLB levels that cause page walks", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "WALK_COMPLETED", .udesc = "Number of misses in all TLB levels causing a page walk of any page size that completes", .ucode = 0xe00, .uflags = INTEL_X86_NCOMBO, }, { .uname = "WALK_COMPLETED_4K", .udesc = "Number of misses in all TLB levels causing a page walk of 4KB page size that completes", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "WALK_COMPLETED_2M_4M", .udesc = "Number of misses in all TLB levels causing a page walk of 2MB/4MB page size that completes", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "WALK_COMPLETED_1G", .udesc = "Number of misses in all TLB levels causing a page walk of 1GB page size that completes", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "WALK_ACTIVE", .udesc = "Cycles with at least one hardware walker active for a load", .ucode = 0x1000 | (0x1 << INTEL_X86_CMASK_BIT), .uflags = INTEL_X86_NCOMBO, }, { .uname = "WALK_DURATION", .udesc = "Cycles when hardware page walker is busy with page walks", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "WALK_PENDING", .udesc = "Cycles when hardware page walker is busy with page walks", .ucode = 0x1000, .uequiv = "WALK_DURATION", .uflags = INTEL_X86_NCOMBO, }, { .uname = "STLB_HIT", .udesc = "Number of cache load STLB hits. No page walk", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t skl_itlb_misses[]={ { .uname = "MISS_CAUSES_A_WALK", .udesc = "Misses in all DTLB levels that cause page walks", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "WALK_COMPLETED", .udesc = "Number of misses in all TLB levels causing a page walk of any page size that completes", .ucode = 0xe00, .uflags = INTEL_X86_NCOMBO, }, { .uname = "WALK_COMPLETED_4K", .udesc = "Number of misses in all TLB levels causing a page walk of 4KB page size that completes", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "WALK_COMPLETED_2M_4M", .udesc = "Number of misses in all TLB levels causing a page walk of 2MB/4MB page size that completes", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "WALK_COMPLETED_1G", .udesc = "Number of misses in all TLB levels causing a page walk of 1GB page size that completes", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "WALK_DURATION", .udesc = "Cycles when PMH is busy with page walks", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "WALK_PENDING", .udesc = "Cycles when PMH is busy with page walks", .ucode = 0x1000, .uequiv = "WALK_DURATION", .uflags = INTEL_X86_NCOMBO, }, { .uname = "STLB_HIT", .udesc = "Number of cache load STLB hits. No page walk", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t skl_fp_assist[]={ { .uname = "ANY", .udesc = "Cycles with any input/output SEE or FP assists", .ucode = 0x1e00 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */ .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, .modhw = _INTEL_X86_ATTR_C, }, }; static const intel_x86_umask_t skl_icache_16b[]={ { .uname = "IFDATA_STALL", .udesc = "Cycles where a code fetch is stalled due to L1 instruction cache miss", .ucode = 0x400, .uflags = INTEL_X86_DFL, }, }; static const intel_x86_umask_t skl_icache_64b[]={ { .uname = "IFTAG_HIT", .udesc = "Number of instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "IFTAG_MISS", .udesc = "Number of instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "IFTAG_STALL", .udesc = "Cycles where a code fetch is stalled due to L1 instruction cache tag miss", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t skl_idq[]={ { .uname = "MITE_UOPS", .udesc = "Number of uops delivered to Instruction Decode Queue (IDQ) from MITE path", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "DSB_UOPS", .udesc = "Number of uops delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "MS_DSB_UOPS", .udesc = "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "MS_MITE_UOPS", .udesc = "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "MS_UOPS", .udesc = "Number of Uops were delivered into Instruction Decode Queue (IDQ) from MS, initiated by Decode Stream Buffer (DSB) or MITE", .ucode = 0x3000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "MS_UOPS_CYCLES", .udesc = "Number of cycles that Uops were delivered into Instruction Decode Queue (IDQ) when MS_Busy, initiated by Decode Stream Buffer (DSB) or MITE", .ucode = 0x3000 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */ .uequiv = "MS_UOPS:c=1", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "MS_SWITCHES", .udesc = "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer", .ucode = 0x3000 | INTEL_X86_MOD_EDGE | (1 << INTEL_X86_CMASK_BIT), /* edge=1 cnt=1 */ .uequiv = "MS_UOPS:c=1:e", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_E | _INTEL_X86_ATTR_C, }, { .uname = "MITE_UOPS_CYCLES", .udesc = "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path", .ucode = 0x400 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */ .uequiv = "MITE_UOPS:c=1", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "DSB_UOPS_CYCLES", .udesc = "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", .ucode = 0x800 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */ .uequiv = "DSB_UOPS:c=1", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "MS_DSB_UOPS_CYCLES", .udesc = "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", .ucode = 0x1000 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */ .uequiv = "MS_DSB_UOPS:c=1", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "MS_DSB_OCCUR", .udesc = "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is busy", .ucode = 0x1000 | INTEL_X86_MOD_EDGE | (1 << INTEL_X86_CMASK_BIT), /* edge=1 cnt=1 */ .uequiv = "MS_DSB_UOPS:c=1:e=1", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_E | _INTEL_X86_ATTR_C, }, { .uname = "ALL_DSB_CYCLES_4_UOPS", .udesc = "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", .ucode = 0x1800 | (4 << INTEL_X86_CMASK_BIT), /* cnt=4 */ .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "ALL_DSB_CYCLES_ANY_UOPS", .udesc = "Cycles Decode Stream Buffer (DSB) is delivering any Uop", .ucode = 0x1800 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */ .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "ALL_MITE_CYCLES_4_UOPS", .udesc = "Cycles MITE is delivering 4 Uops", .ucode = 0x2400 | (4 << INTEL_X86_CMASK_BIT), /* cnt=4 */ .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "ALL_MITE_CYCLES_ANY_UOPS", .udesc = "Cycles MITE is delivering any Uop", .ucode = 0x2400 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */ .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "ALL_MITE_UOPS", .udesc = "Number of uops delivered to Instruction Decode Queue (IDQ) from any path", .ucode = 0x3c00, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t skl_idq_uops_not_delivered[]={ { .uname = "CORE", .udesc = "Count number of non-delivered uops to Resource Allocation Table (RAT)", .ucode = 0x100, .uflags = INTEL_X86_DFL, }, { .uname = "CYCLES_0_UOPS_DELIV_CORE", .udesc = "Number of uops not delivered to Resource Allocation Table (RAT) per thread when backend is not stalled", .ucode = 0x100 | (4 << INTEL_X86_CMASK_BIT), .modhw = _INTEL_X86_ATTR_C, .uflags = INTEL_X86_NCOMBO, }, { .uname = "CYCLES_FE_WAS_OK", .udesc = "Count cycles front-end (FE) delivered 4 uops or Resource Allocation Table (RAT) was stalling front-end", .ucode = 0x100 | INTEL_X86_MOD_INV | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 inv=1 */ .uequiv = "CORE:c=1:i", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C | _INTEL_X86_ATTR_I, }, { .uname = "CYCLES_LE_1_UOPS_DELIV_CORE", .udesc = "Count cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend is not stalled", .ucode = 0x100 | (3 << INTEL_X86_CMASK_BIT), .modhw = _INTEL_X86_ATTR_C, .uflags = INTEL_X86_NCOMBO, }, { .uname = "CYCLES_LE_2_UOPS_DELIV_CORE", .udesc = "Count cycles with less than 2 uops delivered by the front-end", .ucode = 0x100 | (2 << INTEL_X86_CMASK_BIT), .modhw = _INTEL_X86_ATTR_C, .uflags = INTEL_X86_NCOMBO, }, { .uname = "CYCLES_LE_3_UOPS_DELIV_CORE", .udesc = "Count cycles with less then 3 uops delivered by the front-end", .ucode = 0x100 | (1 << INTEL_X86_CMASK_BIT), .modhw = _INTEL_X86_ATTR_C, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t skl_inst_retired[]={ { .uname = "ANY_P", .udesc = "Number of instructions retired. General Counter - architectural event", .ucode = 0x000, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "ALL", .udesc = "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution (Precise Event)", .ucode = 0x100, .uequiv = "PREC_DIST", .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "TOTAL_CYCLES", .udesc = "Number of cycles using always true condition", .ucode = 0x100 | INTEL_X86_MOD_INV | (10 << INTEL_X86_CMASK_BIT), /* inv=1 cnt=10 */ .uequiv = "PREC_DIST:i=1:c=10", .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, .modhw = _INTEL_X86_ATTR_I | _INTEL_X86_ATTR_C, }, { .uname = "PREC_DIST", .udesc = "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution (Precise event)", .ucode = 0x100, .ucntmsk= 0x2, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, }; static const intel_x86_umask_t skl_int_misc[]={ { .uname = "RECOVERY_CYCLES", .udesc = "Cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...)", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "RECOVERY_CYCLES_ANY", .udesc = "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke)", .ucode = 0x100 | INTEL_X86_MOD_ANY, /* any=1 */ .uequiv = "RECOVERY_CYCLES:t", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_T, }, { .uname = "RECOVERY_STALLS_COUNT", .udesc = "Number of occurrences waiting for Machine Clears", .ucode = 0x100 | INTEL_X86_MOD_EDGE | (1 << INTEL_X86_CMASK_BIT), /* edge=1 cnt=1 */ .uequiv = "RECOVERY_CYCLES:e:c=1", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_E, }, { .uname = "CLEAR_RESTEER_CYCLES", .udesc = "Number of cycles the issue-stage is waiting for front-end to fetch from resteered path following branch misprediction or machine clear events", .ucode = 0x8000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t skl_itlb[]={ { .uname = "ITLB_FLUSH", .udesc = "Flushing of the Instruction TLB (ITLB) pages independent of page size", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t skl_l1d[]={ { .uname = "REPLACEMENT", .udesc = "L1D Data line replacements", .ucode = 0x100, .uflags = INTEL_X86_DFL, }, }; static const intel_x86_umask_t skl_sq_misc[]={ { .uname = "SPLIT_LOCK", .udesc = "Number of split locks in the super queue (SQ)", .ucode = 0x1000, .uflags = INTEL_X86_DFL, }, }; static const intel_x86_umask_t skl_l1d_pend_miss[]={ { .uname = "PENDING", .udesc = "Cycles with L1D load misses outstanding", .ucode = 0x100, .ucntmsk = 0x4, .uflags = INTEL_X86_DFL, }, { .uname = "FB_FULL", .udesc = "Number of times a request needed a fill buffer (FB) entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands load, store or SW prefetch", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "PENDING_CYCLES", .udesc = "Cycles with L1D load misses outstanding", .ucode = 0x100 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */ .uequiv = "PENDING:c=1", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "PENDING_CYCLES_ANY", .udesc = "Cycles with L1D load misses outstanding from any thread", .ucode = 0x100 | (1 << INTEL_X86_CMASK_BIT) | INTEL_X86_MOD_ANY, /* cnt=1 any=1 */ .uequiv = "PENDING:c=1:t", .ucntmsk = 0x4, .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C | _INTEL_X86_ATTR_T, }, { .uname = "OCCURRENCES", .udesc = "Number L1D miss outstanding", .ucode = 0x100 | INTEL_X86_MOD_EDGE | (1 << INTEL_X86_CMASK_BIT), /* edge=1 cnt=1 */ .uequiv = "PENDING:c=1:e=1", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_E | _INTEL_X86_ATTR_C, }, { .uname = "EDGE", .udesc = "Number L1D miss outstanding", .ucode = 0x100 | INTEL_X86_MOD_EDGE | (1 << INTEL_X86_CMASK_BIT), /* edge=1 cnt=1 */ .uequiv = "PENDING:c=1:e=1", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_E | _INTEL_X86_ATTR_C, }, }; static const intel_x86_umask_t skl_l2_lines_in[]={ { .uname = "ALL", .udesc = "L2 cache lines filling L2", .ucode = 0x1f00, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "ANY", .udesc = "L2 cache lines filling L2", .uequiv = "ALL", .ucode = 0x1f00, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t skl_l2_lines_out[]={ { .uname = "NON_SILENT", .udesc = "Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines can be either in modified state or clean state. Modified lines may either be written back to L3 or directly written to memory and not allocated in L3. Clean lines may either be allocated in L3 or dropped ", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "USELESS_HWPREF", .udesc = "Counts the number of lines that have been hardware prefetched but not used and now evicted by L2 cache", .ucode = 0x400, .uequiv = "USELESS_HWPF", .uflags = INTEL_X86_NCOMBO, }, { .uname = "USELESS_HWPF", .udesc = "Counts the number of lines that have been hardware prefetched but not used and now evicted by L2 cache", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "SILENT", .udesc = "Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared state. This is a per-core event.", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t skl_l2_rqsts[]={ { .uname = "DEMAND_DATA_RD_MISS", .udesc = "Demand Data Read requests that miss L2 cache", .ucode = 0x2100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "DEMAND_DATA_RD_HIT", .udesc = "Demand Data Read requests that hit L2 cache", .ucode = 0x4100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "DEMAND_RFO_MISS", .udesc = "RFO requests that miss L2 cache", .ucode = 0x2200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "RFO_MISS", .udesc = "RFO requests that miss L2 cache", .ucode = 0x2200, .uequiv = "DEMAND_RFO_MISS", .uflags = INTEL_X86_NCOMBO, }, { .uname = "DEMAND_RFO_HIT", .udesc = "RFO requests that hit L2 cache", .ucode = 0x4200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "RFO_HIT", .udesc = "RFO requests that hit L2 cache", .ucode = 0x4200, .uequiv = "DEMAND_RFO_HIT", .uflags = INTEL_X86_NCOMBO, }, { .uname = "CODE_RD_MISS", .udesc = "L2 cache misses when fetching instructions", .ucode = 0x2400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ALL_DEMAND_MISS", .udesc = "All demand requests that miss the L2 cache", .ucode = 0x2700, .uflags = INTEL_X86_NCOMBO, }, { .uname = "CODE_RD_HIT", .udesc = "L2 cache hits when fetching instructions, code reads", .ucode = 0x4400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "MISS", .udesc = "All requests that miss the L2 cache", .ucode = 0x3f00, .uflags = INTEL_X86_NCOMBO, }, { .uname = "PF_MISS", .udesc = "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that miss L2 cache", .ucode = 0x3800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "PF_HIT", .udesc = "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cache", .ucode = 0xd800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ALL_DEMAND_DATA_RD", .udesc = "Any data read request to L2 cache", .ucode = 0xe100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ALL_RFO", .udesc = "Any data RFO request to L2 cache", .ucode = 0xe200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ALL_CODE_RD", .udesc = "Any code read request to L2 cache", .ucode = 0xe400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ALL_DEMAND_REFERENCES", .udesc = "All demand requests to L2 cache ", .ucode = 0xe700, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ALL_PF", .udesc = "Any L2 HW prefetch request to L2 cache", .ucode = 0xf800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "REFERENCES", .udesc = "All requests to L2 cache", .ucode = 0xff00, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t skl_l2_trans[]={ { .uname = "L2_WB", .udesc = "L2 writebacks that access L2 cache", .ucode = 0x4000, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t skl_ld_blocks[]={ { .uname = "STORE_FORWARD", .udesc = "Counts the number of loads blocked by overlapping with store buffer entries that cannot be forwarded", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "NO_SR", .udesc = "number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t skl_ld_blocks_partial[]={ { .uname = "ADDRESS_ALIAS", .udesc = "False dependencies in MOB due to partial compare on address", .ucode = 0x100, .uflags = INTEL_X86_DFL, }, }; static const intel_x86_umask_t skl_load_hit_pre[]={ { .uname = "SW_PF", .udesc = "Demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch", .ucode = 0x100, .uflags = INTEL_X86_DFL, }, }; static const intel_x86_umask_t skl_lock_cycles[]={ { .uname = "CACHE_LOCK_DURATION", .udesc = "cycles that the L1D is locked", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t skl_longest_lat_cache[]={ { .uname = "MISS", .udesc = "Core-originated cacheable demand requests missed LLC - architectural event", .ucode = 0x4100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "REFERENCE", .udesc = "Core-originated cacheable demand requests that refer to LLC - architectural event", .ucode = 0x4f00, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t skl_machine_clears[]={ { .uname = "COUNT", .udesc = "Number of machine clears (Nukes) of any type", .ucode = 0x100| (1 << INTEL_X86_CMASK_BIT) | (1 << INTEL_X86_EDGE_BIT), .modhw = _INTEL_X86_ATTR_E | _INTEL_X86_ATTR_C, .uflags = INTEL_X86_NCOMBO, }, { .uname = "MEMORY_ORDERING", .udesc = "Number of Memory Ordering Machine Clears detected", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "SMC", .udesc = "Number of Self-modifying code (SMC) Machine Clears detected", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t skl_mem_load_l3_hit_retired[]={ { .uname = "XSNP_MISS", .udesc = "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "XSNP_HIT", .udesc = "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "XSNP_HITM", .udesc = "Load had HitM Response from a core on same socket (shared L3). (Non PEBS", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "XSNP_NONE", .udesc = "Retired load uops which data sources were hits in L3 without snoops required", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, }; static const intel_x86_umask_t skl_mem_load_l3_miss_retired[]={ { .uname = "LOCAL_DRAM", .udesc = "Retired load instructions which data sources missed L3 but serviced from local dram", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "REMOTE_DRAM", .udesc = "Retired load instructions which data sources missed L3 but serviced from remote dram", .ucode = 0x200, .umodel = PFM_PMU_INTEL_SKX, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "REMOTE_HITM", .udesc = "Retired load instructions whose data sources was remote HITM", .ucode = 0x400, .umodel = PFM_PMU_INTEL_SKX, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "REMOTE_FWD", .udesc = "Retired load instructions whose data sources was remote HITM", .ucode = 0x800, .umodel = PFM_PMU_INTEL_SKX, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, }; static const intel_x86_umask_t skl_mem_load_retired[]={ { .uname = "L1_HIT", .udesc = "Retired load uops with L1 cache hits as data source", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "L2_HIT", .udesc = "Retired load uops with L2 cache hits as data source", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "L3_HIT", .udesc = "Retired load uops with L3 cache hits as data source", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "L1_MISS", .udesc = "Retired load uops which missed the L1D", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "L2_MISS", .udesc = "Retired load uops which missed the L2. Unknown data source excluded", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "L3_MISS", .udesc = "Retired load uops which missed the L3", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "HIT_LFB", .udesc = "Retired load uops which missed L1 but hit line fill buffer (LFB)", .ucode = 0x4000, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "FB_HIT", .udesc = "Retired load uops which missed L1 but hit line fill buffer (LFB)", .ucode = 0x4000, .uequiv = "HIT_LFB", .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, }; static const intel_x86_umask_t skl_mem_trans_retired[]={ { .uname = "LOAD_LATENCY", .udesc = "Memory load instructions retired above programmed clocks, minimum threshold value is 3 (Precise Event and ldlat required)", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS | INTEL_X86_LDLAT | INTEL_X86_DFL, }, { .uname = "LATENCY_ABOVE_THRESHOLD", .udesc = "Memory load instructions retired above programmed clocks, minimum threshold value is 3 (Precise Event and ldlat required)", .ucode = 0x100, .uequiv = "LOAD_LATENCY", .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS | INTEL_X86_LDLAT | INTEL_X86_NO_AUTOENCODE, }, }; static const intel_x86_umask_t skl_mem_inst_retired[]={ { .uname = "STLB_MISS_LOADS", .udesc = "Load uops with true STLB miss retired to architected path", .ucode = 0x1100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "STLB_MISS_STORES", .udesc = "Store uops with true STLB miss retired to architected path", .ucode = 0x1200, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "LOCK_LOADS", .udesc = "Load uops with locked access retired", .ucode = 0x2100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "SPLIT_LOADS", .udesc = "Line-splitted load uops retired", .ucode = 0x4100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "SPLIT_STORES", .udesc = "Line-splitted store uops retired", .ucode = 0x4200, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "ALL_LOADS", .udesc = "All load uops retired", .ucode = 0x8100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "ALL_STORES", .udesc = "All store uops retired", .ucode = 0x8200, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, }; static const intel_x86_umask_t skl_misalign_mem_ref[]={ { .uname = "LOADS", .udesc = "Speculative cache-line split load uops dispatched to the L1D", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "STORES", .udesc = "Speculative cache-line split store-address uops dispatched to L1D", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t skl_move_elimination[]={ { .uname = "INT_ELIMINATED", .udesc = "Number of integer Move Elimination candidate uops that were eliminated", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "SIMD_ELIMINATED", .udesc = "Number of SIMD Move Elimination candidate uops that were eliminated", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "INT_NOT_ELIMINATED", .udesc = "Number of integer Move Elimination candidate uops that were not eliminated", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "SIMD_NOT_ELIMINATED", .udesc = "Number of SIMD Move Elimination candidate uops that were not eliminated", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t skl_offcore_requests[]={ { .uname = "DEMAND_DATA_RD", .udesc = "Demand data read requests sent to uncore (use with HT off only)", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DEMAND_CODE_RD", .udesc = "Demand code read requests sent to uncore (use with HT off only)", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "DEMAND_RFO", .udesc = "Demand RFOs requests sent to uncore (use with HT off only)", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ALL_DATA_RD", .udesc = "Data read requests sent to uncore (use with HT off only)", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ALL_REQUESTS", .udesc = "Number of memory transactions that reached the superqueue (SQ)", .ucode = 0x8000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "L3_MISS_DEMAND_DATA_RD", .udesc = "Number of demand data read requests which missed the L3 cache", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t skl_other_assists[]={ { .uname = "ANY", .udesc = "Number of times a microcode assist is invoked by HW other than FP-assist. Examples include AD (page Access Dirty) and AVX* related assists", .ucode = 0x3f00, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t skl_resource_stalls[]={ { .uname = "ANY", .udesc = "Cycles Allocation is stalled due to Resource Related reason", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "ALL", .udesc = "Cycles Allocation is stalled due to Resource Related reason", .ucode = 0x100, .uequiv = "ANY", .uflags = INTEL_X86_NCOMBO, }, { .uname = "RS", .udesc = "Stall cycles caused by absence of eligible entries in Reservation Station (RS)", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "SB", .udesc = "Cycles Allocator is stalled due to Store Buffer full (not including draining from synch)", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ROB", .udesc = "ROB full stall cycles", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t skl_rob_misc_events[]={ { .uname = "LBR_INSERTS", .udesc = "Count each time an new Last Branch Record (LBR) is inserted", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t skl_rs_events[]={ { .uname = "EMPTY_CYCLES", .udesc = "Cycles the Reservation Station (RS) is empty for this thread", .ucode = 0x100, .uflags = INTEL_X86_DFL, }, { .uname = "EMPTY_END", .udesc = "Number of times the reservation station (RS) was empty", .ucode = 0x100 | INTEL_X86_MOD_INV | (1 << INTEL_X86_CMASK_BIT) | INTEL_X86_MOD_EDGE, /* inv=1, cmask=1,edge=1 */ .modhw = _INTEL_X86_ATTR_I | _INTEL_X86_ATTR_C | _INTEL_X86_ATTR_E, }, }; static const intel_x86_umask_t skl_tlb_flush[]={ { .uname = "DTLB_THREAD", .udesc = "Count number of DTLB flushes of thread-specific entries", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "STLB_ANY", .udesc = "Count number of any STLB flushes", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t skl_uops_executed[]={ { .uname = "THREAD", .udesc = "Number of uops executed per thread in each cycle", .ucode = 0x100, .uflags = INTEL_X86_DFL, }, { .uname = "THREAD_CYCLES_GE_1", .udesc = "Number of cycles with at least 1 uop is executed per thread", .ucode = 0x100 | (0x1 << INTEL_X86_CMASK_BIT), .modhw = _INTEL_X86_ATTR_C, .uflags = INTEL_X86_NCOMBO, }, { .uname = "THREAD_CYCLES_GE_2", .udesc = "Number of cycles with at least 2 uops are executed per thread", .ucode = 0x100 | (0x2 << INTEL_X86_CMASK_BIT), .modhw = _INTEL_X86_ATTR_C, .uflags = INTEL_X86_NCOMBO }, { .uname = "THREAD_CYCLES_GE_3", .udesc = "Number of cycles with at least 3 uops are executed per thread", .ucode = 0x100 | (0x3 << INTEL_X86_CMASK_BIT), .modhw = _INTEL_X86_ATTR_C, .uflags = INTEL_X86_NCOMBO, }, { .uname = "THREAD_CYCLES_GE_4", .udesc = "Number of cycles with at least 4 uops are executed per thread", .ucode = 0x100 | (0x4 << INTEL_X86_CMASK_BIT), .modhw = _INTEL_X86_ATTR_C, .uflags = INTEL_X86_NCOMBO, }, { .uname = "CORE", .udesc = "Number of uops executed from any thread in each cycle", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "CORE_CYCLES_GE_1", .udesc = "Number of cycles with at least 1 uop is executed for any thread", .ucode = 0x200 | (0x1 << INTEL_X86_CMASK_BIT), .modhw = _INTEL_X86_ATTR_C, .uflags = INTEL_X86_NCOMBO }, { .uname = "CORE_CYCLES_GE_2", .udesc = "Number of cycles with at least 2 uops are executed for any thread", .ucode = 0x200 | (0x2 << INTEL_X86_CMASK_BIT), .modhw = _INTEL_X86_ATTR_C, .uflags = INTEL_X86_NCOMBO }, { .uname = "CORE_CYCLES_GE_3", .udesc = "Number of cycles with at least 3 uops are executed for any thread", .ucode = 0x200 | (0x3 << INTEL_X86_CMASK_BIT), .modhw = _INTEL_X86_ATTR_C, .uflags = INTEL_X86_NCOMBO, }, { .uname = "CORE_CYCLES_GE_4", .udesc = "Number of cycles with at least 4 uops are executed for any thread", .ucode = 0x200 | (0x4 << INTEL_X86_CMASK_BIT), .modhw = _INTEL_X86_ATTR_C, .uflags = INTEL_X86_NCOMBO, }, { .uname = "STALL_CYCLES", .udesc = "Number of cycles with no uops executed by thread", .ucode = 0x100 | INTEL_X86_MOD_INV | (1 << INTEL_X86_CMASK_BIT), /* inv=1 cnt=1 */ .uequiv = "THREAD:c=1:i", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_I | _INTEL_X86_ATTR_C, }, { .uname = "CORE_CYCLES_NONE", .udesc = "Number of cycles with no uops executed from any thread", .ucode = 0x200 | INTEL_X86_MOD_INV | (1 << INTEL_X86_CMASK_BIT), /* inv=1 cnt=1 */ .uequiv = "CORE:c=1:i", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_I | _INTEL_X86_ATTR_C, }, { .uname = "X87", .udesc = "Number of x87 uops executed per thread", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO }, }; static const intel_x86_umask_t skl_uops_dispatched_port[]={ { .uname = "PORT_0", .udesc = "Cycles which a Uop is executed on port 0", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "PORT_1", .udesc = "Cycles which a Uop is executed on port 1", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "PORT_2", .udesc = "Cycles which a Uop is executed on port 2", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "PORT_3", .udesc = "Cycles which a Uop is executed on port 3", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "PORT_4", .udesc = "Cycles which a Uop is executed on port 4", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "PORT_5", .udesc = "Cycles which a Uop is executed on port 5", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "PORT_6", .udesc = "Cycles which a Uop is executed on port 6", .ucode = 0x4000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "PORT_7", .udesc = "Cycles which a Uop is executed on port 7", .ucode = 0x8000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "PORT_0_CORE", .udesc = "tbd", .ucode = 0x100 | INTEL_X86_MOD_ANY, /* any=1 */ .uequiv = "PORT_0:t=1", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_T, }, { .uname = "PORT_1_CORE", .udesc = "tbd", .ucode = 0x200 | INTEL_X86_MOD_ANY, /* any=1 */ .uequiv = "PORT_1:t=1", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_T, }, { .uname = "PORT_2_CORE", .udesc = "tbd", .ucode = 0x400 | INTEL_X86_MOD_ANY, /* any=1 */ .uequiv = "PORT_2:t=1", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_T, }, { .uname = "PORT_3_CORE", .udesc = "tbd", .ucode = 0x800 | INTEL_X86_MOD_ANY, /* any=1 */ .uequiv = "PORT_3:t=1", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_T, }, { .uname = "PORT_4_CORE", .udesc = "tbd", .ucode = 0x1000 | INTEL_X86_MOD_ANY, /* any=1 */ .uequiv = "PORT_4:t=1", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_T, }, { .uname = "PORT_5_CORE", .udesc = "tbd", .ucode = 0x2000 | INTEL_X86_MOD_ANY, /* any=1 */ .uequiv = "PORT_5:t=1", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_T, }, { .uname = "PORT_6_CORE", .udesc = "tbd", .ucode = 0x4000 | INTEL_X86_MOD_ANY, /* any=1 */ .uequiv = "PORT_6:t=1", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_T, }, { .uname = "PORT_7_CORE", .udesc = "tbd", .ucode = 0x8000 | INTEL_X86_MOD_ANY, /* any=1 */ .uequiv = "PORT_7:t=1", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_T, }, }; static const intel_x86_umask_t skl_uops_issued[]={ { .uname = "ANY", .udesc = "Number of Uops issued by the Resource Allocation Table (RAT) to the Reservation Station (RS)", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "ALL", .udesc = "Number of Uops issued by the Resource Allocation Table (RAT) to the Reservation Station (RS)", .ucode = 0x100, .uequiv = "ANY", .uflags = INTEL_X86_NCOMBO, }, { .uname = "VECTOR_WIDTH_MISMATCH", .udesc = "Number of blend uops issued by the Resource Allocation table (RAT) to the Reservation Station (RS) in order to preserve upper bits of vector registers", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "FLAGS_MERGE", .udesc = "Number of flags-merge uops being allocated. Such uops adds delay", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "SLOW_LEA", .udesc = "Number of slow LEA or similar uops allocated. Such uop has 3 sources regardless if result of LEA instruction or not", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "SINGLE_MUL", .udesc = "Number of Multiply packed/scalar single precision uops allocated", .ucode = 0x4000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "STALL_CYCLES", .udesc = "Counts the number of cycles no uops issued by this thread", .ucode = 0x100 | INTEL_X86_MOD_INV | (1 << INTEL_X86_CMASK_BIT), /* inv=1 cnt=1 */ .uequiv = "ANY:c=1:i=1", .uflags = INTEL_X86_NCOMBO, .ucntmsk = 0xf, .modhw = _INTEL_X86_ATTR_I | _INTEL_X86_ATTR_C, }, { .uname = "CORE_STALL_CYCLES", .udesc = "Counts the number of cycles no uops issued on this core", .ucode = 0x100 | INTEL_X86_MOD_ANY | INTEL_X86_MOD_INV | (1 << INTEL_X86_CMASK_BIT), /* any=1 inv=1 cnt=1 */ .uequiv = "ANY:c=1:i=1:t=1", .ucntmsk = 0xf, .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_T | _INTEL_X86_ATTR_I | _INTEL_X86_ATTR_C, }, }; static const intel_x86_umask_t skl_uops_retired[]={ { .uname = "ALL", .udesc = "All uops that actually retired", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS | INTEL_X86_DFL, }, { .uname = "ANY", .udesc = "All uops that actually retired", .ucode = 0x100, .uequiv = "ALL", .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "RETIRE_SLOTS", .udesc = "number of retirement slots used non PEBS", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "STALL_CYCLES", .udesc = "Cycles no executable uops retired (Precise Event)", .ucode = 0x100 | INTEL_X86_MOD_INV | (1 << INTEL_X86_CMASK_BIT), /* inv=1 cnt=1 */ .uequiv = "ALL:c=1:i", .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, .modhw = _INTEL_X86_ATTR_I | _INTEL_X86_ATTR_C, }, { .uname = "TOTAL_CYCLES", .udesc = "Number of cycles using always true condition applied to PEBS uops retired event", .ucode = 0x100 | INTEL_X86_MOD_INV | (10 << INTEL_X86_CMASK_BIT), /* inv=1 cnt=10 */ .uequiv = "ALL:c=10:i", .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, .modhw = _INTEL_X86_ATTR_I | _INTEL_X86_ATTR_C, }, { .uname = "CORE_STALL_CYCLES", .udesc = "Cycles no executable uops retired on core (Precise Event)", .ucode = 0x100 | INTEL_X86_MOD_INV | (1 << INTEL_X86_CMASK_BIT), /* inv=1 cnt=1 */ .uequiv = "ALL:c=1:i:t=1", .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, .modhw = _INTEL_X86_ATTR_I | _INTEL_X86_ATTR_C, }, { .uname = "STALL_OCCURRENCES", .udesc = "Number of transitions from stalled to unstalled execution (Precise Event)", .ucode = 0x100 | INTEL_X86_MOD_INV | INTEL_X86_MOD_EDGE| (1 << INTEL_X86_CMASK_BIT), /* inv=1 edge=1 cnt=1 */ .uequiv = "ALL:c=1:i=1:e=1", .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, .modhw = _INTEL_X86_ATTR_I | _INTEL_X86_ATTR_C | _INTEL_X86_ATTR_E, }, }; static const intel_x86_umask_t skl_offcore_response[]={ { .uname = "DMND_DATA_RD", .udesc = "Request: number of demand and DCU prefetch data reads of full and partial cachelines as well as demand data page table entry cacheline reads. Does not count L2 data read prefetches or instruction fetches", .ucode = 1ULL << (0 + 8), .grpid = 0, }, { .uname = "DMND_RFO", .udesc = "Request: number of demand and DCU prefetch reads for ownership (RFO) requests generated by a write to data cacheline. Does not count L2 RFO prefetches", .ucode = 1ULL << (1 + 8), .grpid = 0, }, { .uname = "DMND_CODE_RD", .udesc = "Request: number of demand and DCU prefetch instruction cacheline reads. Does not count L2 code read prefetches", .ucode = 1ULL << (2 + 8), .grpid = 0, }, { .uname = "PF_L2_DATA_RD", .udesc = "Request: number of data prefetch requests to L2", .ucode = 1ULL << (4 + 8), .umodel = PFM_PMU_INTEL_SKX, .grpid = 0, }, { .uname = "PF_L2_RFO", .udesc = "Request: number of RFO prefetch requests to L2", .ucode = 1ULL << (5 + 8), .umodel = PFM_PMU_INTEL_SKX, .grpid = 0, }, { .uname = "PF_L3_DATA_RD", .udesc = "Request: number of data prefetch requests for loads that end up in L3", .ucode = 1ULL << (7 + 8), .umodel = PFM_PMU_INTEL_SKX, .grpid = 0, }, { .uname = "PF_L3_RFO", .udesc = "Request: number of RFO prefetch requests that end up in L3", .ucode = 1ULL << (8 + 8), .umodel = PFM_PMU_INTEL_SKX, .grpid = 0, }, { .uname = "PF_L1D_AND_SW", .udesc = "Request: number of L1 data cache hardware prefetch requests and software prefetch requests", .ucode = 1ULL << (10 + 8), .umodel = PFM_PMU_INTEL_SKX, .grpid = 0, }, { .uname = "OTHER", .udesc = "Request: counts one of the following transaction types, including L3 invalidate, I/O, full or partial writes, WC or non-temporal stores, CLFLUSH, Fences, lock, unlock, split lock", .ucode = 1ULL << (15+8), .grpid = 0, }, { .uname = "ANY_REQUEST", .udesc = "Request: combination of all request umasks", .uequiv = "DMND_DATA_RD:DMND_RFO:DMND_CODE_RD:OTHER", .ucode = 0x1800700, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, .umodel = PFM_PMU_INTEL_SKL, .grpid = 0, }, { .uname = "ANY_REQUEST", .udesc = "Request: combination of all request umasks", .uequiv = "DMND_DATA_RD:DMND_RFO:DMND_CODE_RD:PF_L2_DATA_RD:PF_L2_RFO:PF_L3_DATA_RD:PF_L3_RFO:PF_L1D_AND_SW:OTHER", .ucode = 0x85b700, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, .umodel = PFM_PMU_INTEL_SKX, .grpid = 0, }, { .uname = "ANY_DATA_RD", .udesc = "Request: combination of DMND_DATA_RD | PF_L2_DATA_RD | PF_L3_DATA_RD | PF_L1D_AND_SW", .uequiv = "DMND_DATA_RD:PF_L2_DATA_RD:PF_L3_DATA_RD:PF_L1D_AND_SW", .ucode = 0x1049100, .umodel = PFM_PMU_INTEL_SKX, .grpid = 0, }, { .uname = "ANY_DATA", .udesc = "Request: combination of ANY_DATA_RD | PF_L2_RFO | PF_L3_RFO | DMND_RFO", .uequiv = "ANY_DATA_RD:DMND_RFO:PF_L2_RFO:PF_L3_RFO", .ucode = 0x105b300, .umodel = PFM_PMU_INTEL_SKX, .grpid = 0, }, { .uname = "ANY_DATA_PF", .udesc = "Request: combination of PF_L2_DATA_RD | PF_L3_DATA_RD | PF_L1D_AND_SW", .uequiv = "PF_L2_DATA_RD:PF_L3_DATA_RD:PF_L1D_AND_SW", .ucode = 0x1049000, .umodel = PFM_PMU_INTEL_SKX, .grpid = 0, }, { .uname = "ANY_RFO", .udesc = "Request: combination of DMND_RFO | PF_L2_RFO | PF_L3_RFO", .uequiv = "DMND_RFO:PF_L2_RFO:PF_L3_RFO", .ucode = 0x1012200, .umodel = PFM_PMU_INTEL_SKX, .grpid = 0, }, { .uname = "ANY_RESPONSE", .udesc = "Response: count any response type", .ucode = 1ULL << (16+8), .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL | INTEL_X86_EXCL_GRP_GT, .grpid = 1, }, { .uname = "SUPPLIER_NONE", .udesc = "Supplier: counts number of times supplier information is not available", .ucode = 1ULL << (17+8), .grpid = 1, }, { .uname = "NO_SUPP", .udesc = "Supplier: counts number of times supplier information is not available", .ucode = 1ULL << (17+8), .uequiv = "SUPPLIER_NONE", .grpid = 1, }, { .uname = "L3_HITM", .udesc = "Supplier: counts L3 hits in M-state (initial lookup)", .ucode = 1ULL << (18+8), .grpid = 1, }, { .uname = "L3_HITE", .udesc = "Supplier: counts L3 hits in E-state", .ucode = 1ULL << (19+8), .grpid = 1, }, { .uname = "L3_HITS", .udesc = "Supplier: counts L3 hits in S-state", .ucode = 1ULL << (20+8), .grpid = 1, }, { .uname = "L3_HITF", .udesc = "Supplier: counts L3 hits in F-state", .ucode = 1ULL << (21+8), .umodel = PFM_PMU_INTEL_SKX, .grpid = 1, }, { .uname = "L3_HITMES", .udesc = "Supplier: counts L3 hits in any state (M, E, S)", .ucode = 0x3ULL << (18+8), .uequiv = "L3_HITM:L3_HITE:L3_HITS", .umodel = PFM_PMU_INTEL_SKL, .grpid = 1, }, { .uname = "L3_HIT", .udesc = "Alias for L3_HITMES", .ucode = 0x3ULL << (18+8), .uequiv = "L3_HITMES", .umodel = PFM_PMU_INTEL_SKL, .grpid = 1, }, { .uname = "L3_HITMESF", .udesc = "Supplier: counts L3 hits in any state (M, E, S, F)", .ucode = 0xfULL << (18+8), .uequiv = "L3_HITM:L3_HITE:L3_HITS:L3_HITF", .umodel = PFM_PMU_INTEL_SKX, .grpid = 1, }, { .uname = "L3_HIT", .udesc = "Alias for L3_HITMES", .ucode = 0x3ULL << (18+8), .uequiv = "L3_HITMESF", .umodel = PFM_PMU_INTEL_SKX, .grpid = 1, }, { .uname = "L4_HIT_LOCAL_L4", .udesc = "Supplier: L4 local hit", .ucode = 0x1ULL << (22+8), .umodel = PFM_PMU_INTEL_SKL, .grpid = 1, }, { .uname = "L3_MISS_LOCAL", .udesc = "Supplier: counts L3 misses to local DRAM", .ucode = 1ULL << (26+8), .grpid = 1, }, { .uname = "L3_MISS_MISS_REMOTE_HOP1_DRAM", .udesc = "Supplier: counts L3 misses to remote DRAM with 1 hop", .ucode = 1ULL << (28+8), .grpid = 1, }, { .uname = "L3_MISS", .udesc = "Supplier: counts L3 misses", .ucode = 0x1ULL << (26+8), .uequiv = "L3_MISS_LOCAL", .umodel = PFM_PMU_INTEL_SKL, .grpid = 1, }, { .uname = "L3_MISS", .udesc = "Supplier: counts L3 misses (local or remote)", .ucode = 0xfULL << (26+8), .uequiv = "L3_MISS_LOCAL", .umodel = PFM_PMU_INTEL_SKX, .grpid = 1, }, { .uname = "SPL_HIT", .udesc = "Snoop: counts L3 supplier hit", .ucode = 0x1ULL << (30+8), .umodel = PFM_PMU_INTEL_SKL, .grpid = 1, }, { .uname = "SNP_NONE", .udesc = "Snoop: counts number of times no snoop-related information is available", .ucode = 1ULL << (31+8), .grpid = 2, }, { .uname = "SNP_NOT_NEEDED", .udesc = "Snoop: counts the number of times no snoop was needed to satisfy the request", .ucode = 1ULL << (32+8), .grpid = 2, }, { .uname = "SNP_MISS", .udesc = "Snoop: counts number of times a snoop was needed and it missed all snooped caches", .ucode = 1ULL << (33+8), .grpid = 2, }, { .uname = "SNP_HIT_NO_FWD", .udesc = "Snoop: counts number of times a snoop was needed and it hit in at leas one snooped cache", .ucode = 1ULL << (34+8), .grpid = 2, }, { .uname = "SNP_HIT_WITH_FWD", .udesc = "Snoop: counts number of times a snoop was needed and data was forwarded from a remote socket", .ucode = 1ULL << (35+8), .grpid = 2, }, { .uname = "SNP_HITM", .udesc = "Snoop: counts number of times a snoop was needed and it hitM-ed in local or remote cache", .ucode = 1ULL << (36+8), .grpid = 2, }, { .uname = "SNP_NON_DRAM", .udesc = "Snoop: counts number of times target was a non-DRAM system address. This includes MMIO transactions", .ucode = 1ULL << (37+8), .grpid = 2, }, { .uname = "SNP_ANY", .udesc = "Snoop: any snoop reason", .ucode = 0x7fULL << (31+8), .uequiv = "SNP_NONE:SNP_NOT_NEEDED:SNP_MISS:SNP_HIT_NO_FWD:SNP_HIT_WITH_FWD:SNP_HITM:SNP_NON_DRAM", .uflags= INTEL_X86_DFL, .grpid = 2, }, }; static const intel_x86_umask_t skl_hle_retired[]={ { .uname = "START", .udesc = "Number of times an HLE execution started", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "COMMIT", .udesc = "Number of times an HLE execution successfully committed", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ABORTED", .udesc = "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one) (Precise Event)", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "ABORTED_MEM", .udesc = "Number of times an HLE execution aborted due to various memory events", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ABORTED_TMR", .udesc = "Number of times an HLE execution aborted due to hardware timer expiration", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ABORTED_UNFRIENDLY", .udesc = "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain events such as AD-assists", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ABORTED_MEMTYPE", .udesc = "Number of times an HLE execution aborted due to incompatible memory type", .ucode = 0x4000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ABORTED_EVENTS", .udesc = "Number of times an HLE execution aborted due to none of the other 4 reasons (e.g., interrupt)", .ucode = 0x8000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t skl_rtm_retired[]={ { .uname = "START", .udesc = "Number of times an RTM execution started", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "COMMIT", .udesc = "Number of times an RTM execution successfully committed", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ABORTED", .udesc = "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one) (Precise Event)", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "ABORTED_MEM", .udesc = "Number of times an RTM execution aborted due to various memory events", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ABORTED_TMR", .udesc = "Number of times an RTM execution aborted due to uncommon conditions", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ABORTED_UNFRIENDLY", .udesc = "Number of times an RTM execution aborted due to RTM-unfriendly instructions", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ABORTED_MEMTYPE", .udesc = "Number of times an RTM execution aborted due to incompatible memory type", .ucode = 0x4000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ABORTED_EVENTS", .udesc = "Number of times an RTM execution aborted due to none of the other 4 reasons (e.g., interrupt)", .ucode = 0x8000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t skl_tx_mem[]={ { .uname = "ABORT_CONFLICT", .udesc = "Number of times a transactional abort was signaled due to data conflict on a transactionally accessed address", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ABORT_CAPACITY", .udesc = "Number of times a transactional abort was signaled due to data capacity limitation", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ABORT_HLE_STORE_TO_ELIDED_LOCK", .udesc = "Number of times a HLE transactional execution aborted due to a non xrelease prefixed instruction writing to an elided lock in the elision buffer", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", .udesc = "Number of times a HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ABORT_HLE_ELISION_BUFFER_MISMATCH", .udesc = "Number of times a HLE transaction execution aborted due to xrelease lock not satisfying the address and value requirements in the elision buffer", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", .udesc = "Number of times a HLE transaction execution aborted due to an unsupported read alignment from the elision buffer", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ABORT_HLE_ELISION_BUFFER_FULL", .udesc = "Number of times a HLE clock could not be elided due to ElisionBufferAvailable being zero", .ucode = 0x4000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t skl_tx_exec[]={ { .uname = "MISC1", .udesc = "Number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "MISC2", .udesc = "Number of times a class of instructions that may cause a transactional abort was executed inside a transactional region", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "MISC3", .udesc = "Number of times an instruction execution caused the supported nest count to be exceeded", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "MISC4", .udesc = "Number of times an instruction a xbegin instruction was executed inside HLE transactional region", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "MISC5", .udesc = "Number of times an instruction with HLE xacquire prefix was executed inside a RTM transactional region", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t skl_offcore_requests_outstanding[]={ { .uname = "ALL_DATA_RD_CYCLES", .udesc = "Cycles with cacheable data read transactions in the superQ (use with HT off only)", .uequiv = "ALL_DATA_RD:c=1", .ucode = 0x800 | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, }, { .uname = "DEMAND_CODE_RD_CYCLES", .udesc = "Cycles with demand code reads transactions in the superQ (use with HT off only)", .uequiv = "DEMAND_CODE_RD:c=1", .ucode = 0x200 | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, }, { .uname = "CYCLES_WITH_DEMAND_CODE_RD", .udesc = "Cycles with demand code reads transactions in the superQ (use with HT off only)", .uequiv = "DEMAND_CODE_RD:c=1", .ucode = 0x200 | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, }, { .uname = "DEMAND_DATA_RD_CYCLES", .udesc = "Cycles with demand data read transactions in the superQ (use with HT off only)", .uequiv = "DEMAND_DATA_RD:c=1", .ucode = 0x100 | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, }, { .uname = "CYCLES_WITH_DEMAND_DATA_RD", .udesc = "Cycles with demand data read transactions in the superQ (use with HT off only)", .uequiv = "DEMAND_DATA_RD:c=1", .ucode = 0x100 | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, }, { .uname = "ALL_DATA_RD", .udesc = "Cacheable data read transactions in the superQ every cycle (use with HT off only)", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DEMAND_CODE_RD", .udesc = "Code read transactions in the superQ every cycle (use with HT off only)", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DEMAND_DATA_RD", .udesc = "Demand data read transactions in the superQ every cycle (use with HT off only)", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DEMAND_DATA_RD_GE_6", .udesc = "Cycles with at lesat 6 offcore outstanding demand data read requests in the uncore queue", .uequiv = "DEMAND_DATA_RD:c=6", .ucode = 0x100 | (6 << INTEL_X86_CMASK_BIT), /* cnt=1 */ .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "DEMAND_RFO", .udesc = "Outstanding RFO (store) transactions in the superQ every cycle (use with HT off only)", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DEMAND_RFO_CYCLES", .udesc = "Cycles with outstanding RFO (store) transactions in the superQ (use with HT off only)", .uequiv = "DEMAND_RFO:c=1", .ucode = 0x400 | (0x1 << INTEL_X86_CMASK_BIT), /* cnt=1 */ .uflags= INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "CYCLES_WITH_DEMAND_RFO", .udesc = "Cycles with outstanding RFO (store) transactions in the superQ (use with HT off only)", .uequiv = "DEMAND_RFO:c=1", .ucode = 0x400 | (0x1 << INTEL_X86_CMASK_BIT), /* cnt=1 */ .uflags= INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "L3_MISS_DEMAND_DATA_RD", .udesc = "Number of offcore outstanding demand data read requests missing the L3 cache every cycle", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "L3_MISS_DEMAND_DATA_RD_GE_6", .udesc = "Number of cycles in which at least 6 demand data read requests missing the L3", .ucode = 0x1000 | (0x6 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "CYCLES_WITH_L3_MISS_DEMAND_DATA_RD", .udesc = "Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ", .ucode = 0x1000 | (0x1 << INTEL_X86_CMASK_BIT), /* cnt=1 */ .uflags= INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, }; static const intel_x86_umask_t skl_ild_stall[]={ { .uname = "LCP", .udesc = "Stall caused by changing prefix length of the instruction", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t skl_lsd[]={ { .uname = "UOPS", .udesc = "Number of uops delivered by the Loop Stream Detector (LSD)", .ucode = 0x100, .uflags= INTEL_X86_DFL | INTEL_X86_NCOMBO, }, { .uname = "CYCLES_4_UOPS", .udesc = "Number of cycles the LSD delivered 4 uops which did not come from the decoder", .ucode = 0x100| (0x4 << INTEL_X86_CMASK_BIT), .modhw = _INTEL_X86_ATTR_C, .uflags= INTEL_X86_NCOMBO, }, { .uname = "CYCLES_ACTIVE", .udesc = "Number of cycles the LSD delivered uops which did not come from the decoder", .ucode = 0x100| (0x1 << INTEL_X86_CMASK_BIT), .modhw = _INTEL_X86_ATTR_C, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t skl_dsb2mite_switches[]={ { .uname = "PENALTY_CYCLES", .udesc = "Number of DSB to MITE switch true penalty cycles", .ucode = 0x0200, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t skl_ept[]={ { .uname = "WALK_DURATION", .udesc = "Cycles for an extended page table walk of any type", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "WALK_PENDING", .udesc = "Cycles for an extended page table walk of any type", .ucode = 0x1000, .uequiv = "WALK_DURATION", .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t skl_arith[]={ { .uname = "DIVIDER_ACTIVE", .udesc = "Cycles when divider is busy executing divide or square root operations on integers or floating-points", .ucode = 0x100 | (1 << INTEL_X86_CMASK_BIT), .uflags = INTEL_X86_DFL | INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "FPU_DIV_ACTIVE", .udesc = "Cycles when divider is busy executing divide or square root operations on integers or floating-points", .ucode = 0x100 | (1 << INTEL_X86_CMASK_BIT), .uequiv = "DIVIDER_ACTIVE", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, }; static const intel_x86_umask_t skl_fp_arith[]={ { .uname = "SCALAR_DOUBLE", .udesc = "Number of scalar double precision floating-point arithmetic instructions (multiply by 1 to get flops)", .ucode = 0x0100, }, { .uname = "SCALAR_SINGLE", .udesc = "Number of scalar single precision floating-point arithmetic instructions (multiply by 1 to get flops)", .ucode = 0x0200, }, { .uname = "128B_PACKED_DOUBLE", .udesc = "Number of scalar 128-bit packed double precision floating-point arithmetic instructions (multiply by 2 to get flops)", .ucode = 0x0400, }, { .uname = "128B_PACKED_SINGLE", .udesc = "Number of scalar 128-bit packed single precision floating-point arithmetic instructions (multiply by 4 to get flops)", .ucode = 0x0800, }, { .uname = "256B_PACKED_DOUBLE", .udesc = "Number of scalar 256-bit packed double precision floating-point arithmetic instructions (multiply by 4 to get flops)", .ucode = 0x1000, }, { .uname = "256B_PACKED_SINGLE", .udesc = "Number of scalar 256-bit packed single precision floating-point arithmetic instructions (multiply by 8 to get flops)", .ucode = 0x2000, }, { .uname = "512B_PACKED_DOUBLE", .udesc = "Number of scalar 512-bit packed double precision floating-point arithmetic instructions (multiply by 8 to get flops)", .ucode = 0x4000, }, { .uname = "512B_PACKED_SINGLE", .udesc = "Number of scalar 512-bit packed single precision floating-point arithmetic instructions (multiply by 16 to get flops)", .ucode = 0x8000, }, }; static const intel_x86_umask_t skl_exe_activity[]={ { .uname = "1_PORTS_UTIL", .udesc = "Cycles with 1 uop executing across all ports and Reservation Station is not empty", .ucode = 0x0200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "2_PORTS_UTIL", .udesc = "Cycles with 2 uops executing across all ports and Reservation Station is not empty", .ucode = 0x0400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "3_PORTS_UTIL", .udesc = "Cycles with 3 uops executing across all ports and Reservation Station is not empty", .ucode = 0x0800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "4_PORTS_UTIL", .udesc = "Cycles with 4 uops executing across all ports and Reservation Station is not empty", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "BOUND_ON_STORES", .udesc = "Cycles where the store buffer is full and no outstanding load", .ucode = 0x4000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "EXE_BOUND_0_PORTS", .udesc = "Cycles where no uop is executed and the Reservation Station was not empty", .ucode = 0x0100, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t skl_frontend_retired[]={ { .uname = "DSB_MISS", .udesc = "Retired instructions experiencing decode stream buffer (DSB) miss", .ucode = 0x11 << 8, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "ITLB_MISS", .udesc = "Retired instructions experiencing ITLB true miss", .ucode = 0x14 << 8, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "L1I_MISS", .udesc = "Retired instructions experiencing L1I cache true miss", .ucode = 0x12 << 8, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "L2_MISS", .udesc = "Retired instructions experiencing instruction L2 cache true miss", .ucode = 0x13 << 8, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "STLB_MISS", .udesc = "Retired instructions experiencing STLB (2nd level TLB) true miss", .ucode = 0x15 << 8, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "IDQ_4_BUBBLES", .udesc = "Retired instructions after an interval where the front-end did not deliver any uops (4 bubbles) for a period determined by the fe_thres modifier and which was not interrupted by a back-end stall", .ucode = (4 << 20 | 0x6) << 8, .uflags= INTEL_X86_NCOMBO | INTEL_X86_FETHR | INTEL_X86_PEBS, }, { .uname = "IDQ_3_BUBBLES", .udesc = "Counts instructions retired after an interval where the front-end did not deliver more than 1 uop (3 bubbles) for a period determined by the fe_thres modifier and which was not interrupted by a back-end stall", .ucode = (3 << 20 | 0x6) << 8, .uflags= INTEL_X86_NCOMBO | INTEL_X86_FETHR | INTEL_X86_PEBS, }, { .uname = "IDQ_2_BUBBLES", .udesc = "Counts instructions retired after an interval where the front-end did not deliver more than 2 uops (2 bubbles) for a period determined by the fe_thres modifier and which was not interrupted by a back-end stall", .ucode = (2 << 20 | 0x6) << 8, .uflags= INTEL_X86_NCOMBO | INTEL_X86_FETHR | INTEL_X86_PEBS, }, { .uname = "IDQ_1_BUBBLE", .udesc = "Counts instructions retired after an interval where the front-end did not deliver more than 3 uops (1 bubble) for a period determined by the fe_thres modifier and which was not interrupted by a back-end stall", .ucode = (1 << 20 | 0x6) << 8, .uflags= INTEL_X86_NCOMBO | INTEL_X86_FETHR | INTEL_X86_PEBS, }, }; static const intel_x86_umask_t skl_hw_interrupts[]={ { .uname = "RECEIVED", .udesc = "Number of hardware interrupts received by the processor", .ucode = 0x100, .uflags= INTEL_X86_DFL, }, }; static const intel_x86_umask_t skl_offcore_requests_buffer[]={ { .uname = "SQ_FULL", .udesc = "Number of requests for which the offcore buffer (SQ) is full", .ucode = 0x100, .uflags= INTEL_X86_DFL, }, }; static const intel_x86_umask_t skl_mem_load_misc_retired[]={ { .uname = "UC", .udesc = "Number of uncached load retired", .ucode = 0x400, .uflags= INTEL_X86_PEBS | INTEL_X86_DFL, }, }; static const intel_x86_umask_t skl_idi_misc[]={ { .uname = "WB_UPGRADE", .udesc = "Counts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortly", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "WB_DOWNGRADE", .udesc = "Counts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortly", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t skl_core_power[]={ { .uname = "LVL0_TURBO_LICENSE", .udesc = "Number of core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.", .ucode = 0x700, .umodel = PFM_PMU_INTEL_SKX, .uflags= INTEL_X86_NCOMBO, }, { .uname = "LVL1_TURBO_LICENSE", .udesc = "Number of core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule.", .ucode = 0x1800, .umodel = PFM_PMU_INTEL_SKX, .uflags= INTEL_X86_NCOMBO, }, { .uname = "LVL2_TURBO_LICENSE", .udesc = "Number of core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.", .ucode = 0x2000, .umodel = PFM_PMU_INTEL_SKX, .uflags= INTEL_X86_NCOMBO, }, { .uname = "THROTTLE", .udesc = "Number of core cycles where the core was throttled due to a pending power level request.", .ucode = 0x4000, .umodel = PFM_PMU_INTEL_SKX, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t skl_sw_prefetch[]={ { .uname = "NTA", .udesc = "Number of prefetch.nta instructions executed", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "T0", .udesc = "Number of prefetch.t0 instructions executed", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "T1_T2", .udesc = "Number prefetch.t1 or prefetch.t2 instructions executed", .ucode = 0x4000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PREFETCHW", .udesc = "Number prefetch.w instructions executed", .ucode = 0x8000, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_entry_t intel_skl_pe[]={ { .name = "UNHALTED_CORE_CYCLES", .desc = "Count core clock cycles whenever the clock signal on the specific core is running (not halted)", .modmsk = INTEL_V4_ATTRS, .cntmsk = 0x20000000full, .code = 0x3c, }, { .name = "UNHALTED_REFERENCE_CYCLES", .desc = "Unhalted reference cycles", .modmsk = INTEL_FIXED3_ATTRS, .cntmsk = 0x400000000ull, .code = 0x0300, /* pseudo encoding */ .flags = INTEL_X86_FIXED, }, { .name = "INSTRUCTION_RETIRED", .desc = "Number of instructions at retirement", .modmsk = INTEL_V4_ATTRS, .cntmsk = 0x10000000full, .code = 0xc0, }, { .name = "INSTRUCTIONS_RETIRED", .desc = "This is an alias for INSTRUCTION_RETIRED", .modmsk = INTEL_V4_ATTRS, .equiv = "INSTRUCTION_RETIRED", .cntmsk = 0x10000000full, .code = 0xc0, }, { .name = "BRANCH_INSTRUCTIONS_RETIRED", .desc = "Count branch instructions at retirement. Specifically, this event counts the retirement of the last micro-op of a branch instruction", .modmsk = INTEL_V4_ATTRS, .equiv = "BR_INST_RETIRED:ALL_BRANCHES", .cntmsk = 0xff, .code = 0xc4, }, { .name = "MISPREDICTED_BRANCH_RETIRED", .desc = "Count mispredicted branch instructions at retirement. Specifically, this event counts at retirement of the last micro-op of a branch instruction in the architectural path of the execution and experienced misprediction in the branch prediction hardware", .modmsk = INTEL_V4_ATTRS, .equiv = "BR_MISP_RETIRED:ALL_BRANCHES", .cntmsk = 0xff, .code = 0xc5, }, { .name = "BACLEARS", .desc = "Branch re-steered", .code = 0xe6, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(skl_baclears), .umasks = skl_baclears }, { .name = "BR_INST_RETIRED", .desc = "Branch instructions retired (Precise Event)", .code = 0xc4, .cntmsk = 0xff, .ngrp = 1, .flags = INTEL_X86_PEBS, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(skl_br_inst_retired), .umasks = skl_br_inst_retired }, { .name = "BR_MISP_RETIRED", .desc = "Mispredicted retired branches (Precise Event)", .code = 0xc5, .cntmsk = 0xff, .ngrp = 1, .flags = INTEL_X86_PEBS, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(skl_br_misp_retired), .umasks = skl_br_misp_retired }, { .name = "CPU_CLK_THREAD_UNHALTED", .desc = "Count core clock cycles whenever the clock signal on the specific core is running (not halted)", .code = 0x3c, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(skl_cpu_clk_thread_unhalted), .umasks = skl_cpu_clk_thread_unhalted }, { .name = "CPU_CLK_UNHALTED", .desc = "Count core clock cycles whenever the clock signal on the specific core is running (not halted)", .code = 0x3c, .cntmsk = 0xff, .modmsk = INTEL_V4_ATTRS, .equiv = "CPU_CLK_THREAD_UNHALTED", }, { .name = "CYCLE_ACTIVITY", .desc = "Stalled cycles", .code = 0xa3, .cntmsk = 0xf, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(skl_cycle_activity), .umasks = skl_cycle_activity }, { .name = "DTLB_LOAD_MISSES", .desc = "Data TLB load misses", .code = 0x8, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(skl_dtlb_load_misses), .umasks = skl_dtlb_load_misses }, { .name = "DTLB_STORE_MISSES", .desc = "Data TLB store misses", .code = 0x49, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(skl_dtlb_load_misses), .umasks = skl_dtlb_load_misses /* shared */ }, { .name = "FP_ASSIST", .desc = "X87 floating-point assists", .code = 0xca, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(skl_fp_assist), .umasks = skl_fp_assist }, { .name = "HLE_RETIRED", .desc = "HLE execution (Precise Event)", .code = 0xc8, .cntmsk = 0xff, .ngrp = 1, .flags = INTEL_X86_PEBS, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(skl_hle_retired), .umasks = skl_hle_retired }, { .name = "ICACHE_16B", .desc = "Instruction Cache", .code = 0x80, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(skl_icache_16b), .umasks = skl_icache_16b }, { .name = "ICACHE_64B", .desc = "Instruction Cache", .code = 0x83, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(skl_icache_64b), .umasks = skl_icache_64b }, { .name = "IDQ", .desc = "IDQ operations", .code = 0x79, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(skl_idq), .umasks = skl_idq }, { .name = "IDQ_UOPS_NOT_DELIVERED", .desc = "Uops not delivered", .code = 0x9c, .cntmsk = 0xf, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(skl_idq_uops_not_delivered), .umasks = skl_idq_uops_not_delivered }, { .name = "INST_RETIRED", .desc = "Number of instructions retired (Precise Event)", .code = 0xc0, .cntmsk = 0xff, .ngrp = 1, .flags = INTEL_X86_PEBS, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(skl_inst_retired), .umasks = skl_inst_retired }, { .name = "INT_MISC", .desc = "Miscellaneous interruptions", .code = 0xd, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(skl_int_misc), .umasks = skl_int_misc }, { .name = "ITLB", .desc = "Instruction TLB", .code = 0xae, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(skl_itlb), .umasks = skl_itlb }, { .name = "ITLB_MISSES", .desc = "Instruction TLB misses", .code = 0x85, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(skl_itlb_misses), .umasks = skl_itlb_misses }, { .name = "L1D", .desc = "L1D cache", .code = 0x51, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(skl_l1d), .umasks = skl_l1d }, { .name = "L1D_PEND_MISS", .desc = "L1D pending misses", .code = 0x48, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(skl_l1d_pend_miss), .umasks = skl_l1d_pend_miss }, { .name = "L2_LINES_IN", .desc = "L2 lines allocated", .code = 0xf1, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(skl_l2_lines_in), .umasks = skl_l2_lines_in }, { .name = "L2_LINES_OUT", .desc = "L2 lines evicted", .code = 0xf2, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(skl_l2_lines_out), .umasks = skl_l2_lines_out }, { .name = "L2_RQSTS", .desc = "L2 requests", .code = 0x24, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(skl_l2_rqsts), .umasks = skl_l2_rqsts }, { .name = "L2_TRANS", .desc = "L2 transactions", .code = 0xf0, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(skl_l2_trans), .umasks = skl_l2_trans }, { .name = "LD_BLOCKS", .desc = "Blocking loads", .code = 0x3, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(skl_ld_blocks), .umasks = skl_ld_blocks }, { .name = "LD_BLOCKS_PARTIAL", .desc = "Partial load blocks", .code = 0x7, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(skl_ld_blocks_partial), .umasks = skl_ld_blocks_partial }, { .name = "LOAD_HIT_PRE", .desc = "Load dispatches", .code = 0x4c, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(skl_load_hit_pre), .umasks = skl_load_hit_pre }, { .name = "LOCK_CYCLES", .desc = "Locked cycles in L1D and L2", .code = 0x63, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(skl_lock_cycles), .umasks = skl_lock_cycles }, { .name = "LONGEST_LAT_CACHE", .desc = "L3 cache", .code = 0x2e, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(skl_longest_lat_cache), .umasks = skl_longest_lat_cache }, { .name = "MACHINE_CLEARS", .desc = "Machine clear asserted", .code = 0xc3, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(skl_machine_clears), .umasks = skl_machine_clears }, { .name = "MEM_LOAD_L3_HIT_RETIRED", .desc = "L3 hit load uops retired (Precise Event)", .code = 0xd2, .cntmsk = 0xf, .ngrp = 1, .flags = INTEL_X86_PEBS, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(skl_mem_load_l3_hit_retired), .umasks = skl_mem_load_l3_hit_retired }, { .name = "MEM_LOAD_UOPS_L3_HIT_RETIRED", .desc = "L3 hit load uops retired (Precise Event)", .equiv = "MEM_LOAD_L3_HIT_RETIRED", .code = 0xd2, .cntmsk = 0xf, .ngrp = 1, .flags = INTEL_X86_PEBS, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(skl_mem_load_l3_hit_retired), .umasks = skl_mem_load_l3_hit_retired }, { .name = "MEM_LOAD_UOPS_L3_MISS_RETIRED", .desc = "L3 miss load uops retired (Precise Event)", .code = 0xd3, .cntmsk = 0xf, .ngrp = 1, .flags = INTEL_X86_PEBS, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(skl_mem_load_l3_miss_retired), .umasks = skl_mem_load_l3_miss_retired }, { .name = "MEM_LOAD_UOPS_LLC_HIT_RETIRED", .desc = "L3 hit load uops retired (Precise Event)", .equiv = "MEM_LOAD_L3_HIT_RETIRED", .code = 0xd2, .cntmsk = 0xf, .ngrp = 1, .flags = INTEL_X86_PEBS, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(skl_mem_load_l3_hit_retired), .umasks = skl_mem_load_l3_hit_retired }, { .name = "MEM_LOAD_RETIRED", .desc = "Retired load uops (Precise Event)", .code = 0xd1, .cntmsk = 0xf, .ngrp = 1, .flags = INTEL_X86_PEBS, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(skl_mem_load_retired), .umasks = skl_mem_load_retired }, { .name = "MEM_LOAD_UOPS_RETIRED", .desc = "Retired load uops (Precise Event)", .code = 0xd1, .equiv = "MEM_LOAD_RETIRED", .cntmsk = 0xf, .ngrp = 1, .flags = INTEL_X86_PEBS, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(skl_mem_load_retired), .umasks = skl_mem_load_retired }, { .name = "MEM_TRANS_RETIRED", .desc = "Memory transactions retired (Precise Event)", .code = 0xcd, .cntmsk = 0x8, .ngrp = 1, .flags = INTEL_X86_PEBS, .modmsk = INTEL_V4_ATTRS | _INTEL_X86_ATTR_LDLAT, .numasks = LIBPFM_ARRAY_SIZE(skl_mem_trans_retired), .umasks = skl_mem_trans_retired }, { .name = "MEM_INST_RETIRED", .desc = "Memory instructions retired (Precise Event)", .code = 0xd0, .cntmsk = 0xf, .ngrp = 1, .flags = INTEL_X86_PEBS, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(skl_mem_inst_retired), .umasks = skl_mem_inst_retired }, { .name = "MEM_UOPS_RETIRED", .desc = "Memory instructions retired (Precise Event)", .code = 0xd0, .cntmsk = 0xf, .equiv = "MEM_INST_RETIRED", .ngrp = 1, .flags = INTEL_X86_PEBS, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(skl_mem_inst_retired), .umasks = skl_mem_inst_retired }, { .name = "MISALIGN_MEM_REF", .desc = "Misaligned memory references", .code = 0x5, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(skl_misalign_mem_ref), .umasks = skl_misalign_mem_ref }, { .name = "MOVE_ELIMINATION", .desc = "Move Elimination", .code = 0x58, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(skl_move_elimination), .umasks = skl_move_elimination }, { .name = "OFFCORE_REQUESTS", .desc = "Demand Data Read requests sent to uncore", .code = 0xb0, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(skl_offcore_requests), .umasks = skl_offcore_requests }, { .name = "OTHER_ASSISTS", .desc = "Software assist", .code = 0xc1, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(skl_other_assists), .umasks = skl_other_assists }, { .name = "RESOURCE_STALLS", .desc = "Cycles Allocation is stalled due to Resource Related reason", .code = 0xa2, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(skl_resource_stalls), .umasks = skl_resource_stalls }, { .name = "ROB_MISC_EVENTS", .desc = "ROB miscellaneous events", .code = 0xcc, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(skl_rob_misc_events), .umasks = skl_rob_misc_events }, { .name = "RS_EVENTS", .desc = "Reservation Station", .code = 0x5e, .cntmsk = 0xf, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(skl_rs_events), .umasks = skl_rs_events }, { .name = "RTM_RETIRED", .desc = "Restricted Transaction Memory execution (Precise Event)", .code = 0xc9, .cntmsk = 0xf, .ngrp = 1, .flags = INTEL_X86_PEBS, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(skl_rtm_retired), .umasks = skl_rtm_retired }, { .name = "TLB_FLUSH", .desc = "TLB flushes", .code = 0xbd, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(skl_tlb_flush), .umasks = skl_tlb_flush }, { .name = "UOPS_EXECUTED", .desc = "Uops executed", .code = 0xb1, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(skl_uops_executed), .umasks = skl_uops_executed }, { .name = "LSD", .desc = "Loop stream detector", .code = 0xa8, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(skl_lsd), .umasks = skl_lsd, }, { .name = "UOPS_DISPATCHED_PORT", .desc = "Uops dispatched to specific ports", .code = 0xa1, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(skl_uops_dispatched_port), .umasks = skl_uops_dispatched_port, }, { .name = "UOPS_DISPATCHED", .desc = "Uops dispatched to specific ports", .equiv = "UOPS_DISPATCHED_PORT", .code = 0xa1, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(skl_uops_dispatched_port), .umasks = skl_uops_dispatched_port, }, { .name = "UOPS_ISSUED", .desc = "Uops issued", .code = 0xe, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(skl_uops_issued), .umasks = skl_uops_issued }, { .name = "ARITH", .desc = "Arithmetic uop", .code = 0x14, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(skl_arith), .umasks = skl_arith }, { .name = "UOPS_RETIRED", .desc = "Uops retired (Precise Event)", .code = 0xc2, .cntmsk = 0xff, .ngrp = 1, .flags = INTEL_X86_PEBS, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(skl_uops_retired), .umasks = skl_uops_retired }, { .name = "TX_MEM", .desc = "Transactional memory aborts", .code = 0x54, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(skl_tx_mem), .umasks = skl_tx_mem, }, { .name = "TX_EXEC", .desc = "Transactional execution", .code = 0x5d, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(skl_tx_exec), .umasks = skl_tx_exec }, { .name = "OFFCORE_REQUESTS_OUTSTANDING", .desc = "Outstanding offcore requests", .modmsk = INTEL_V4_ATTRS, .cntmsk = 0xff, .code = 0x60, .numasks = LIBPFM_ARRAY_SIZE(skl_offcore_requests_outstanding), .ngrp = 1, .umasks = skl_offcore_requests_outstanding, }, { .name = "ILD_STALL", .desc = "Instruction Length Decoder stalls", .modmsk = INTEL_V4_ATTRS, .cntmsk = 0xff, .code = 0x87, .numasks = LIBPFM_ARRAY_SIZE(skl_ild_stall), .ngrp = 1, .umasks = skl_ild_stall, }, { .name = "DSB2MITE_SWITCHES", .desc = "Number of DSB to MITE switches", .modmsk = INTEL_V4_ATTRS, .cntmsk = 0xff, .code = 0xab, .numasks = LIBPFM_ARRAY_SIZE(skl_dsb2mite_switches), .ngrp = 1, .umasks = skl_dsb2mite_switches, }, { .name = "EPT", .desc = "Extended page table", .modmsk = INTEL_V4_ATTRS, .cntmsk = 0xff, .code = 0x4f, .numasks = LIBPFM_ARRAY_SIZE(skl_ept), .ngrp = 1, .umasks = skl_ept, }, { .name = "FP_ARITH", .desc = "Floating-point", .modmsk = INTEL_V4_ATTRS, .cntmsk = 0xf, .code = 0xc7, .numasks = LIBPFM_ARRAY_SIZE(skl_fp_arith), .ngrp = 1, .umasks = skl_fp_arith, }, { .name = "EXE_ACTIVITY", .desc = "Execution activity", .modmsk = INTEL_V4_ATTRS, .cntmsk = 0xf, .code = 0xa6, .numasks = LIBPFM_ARRAY_SIZE(skl_exe_activity), .ngrp = 1, .umasks = skl_exe_activity, }, { .name = "FRONTEND_RETIRED", .desc = "Precise Front-End activity", .modmsk = INTEL_SKL_FE_ATTRS, .cntmsk = 0xf, .code = 0x1c6, .flags = INTEL_X86_FRONTEND | INTEL_X86_PEBS, .numasks = LIBPFM_ARRAY_SIZE(skl_frontend_retired), .ngrp = 1, .umasks = skl_frontend_retired, }, { .name = "HW_INTERRUPTS", .desc = "Number of hardware interrupts received by the processor", .modmsk = INTEL_V4_ATTRS, .cntmsk = 0xff, .code = 0xcb, .numasks = LIBPFM_ARRAY_SIZE(skl_hw_interrupts), .ngrp = 1, .umasks = skl_hw_interrupts, }, { .name = "SQ_MISC", .desc = "SuperQueue miscellaneous", .modmsk = INTEL_V4_ATTRS, .cntmsk = 0xf, .code = 0xf4, .numasks = LIBPFM_ARRAY_SIZE(skl_sq_misc), .ngrp = 1, .umasks = skl_sq_misc, }, { .name = "MEM_LOAD_MISC_RETIRED", .desc = "Load retired miscellaneous", .modmsk = INTEL_V4_ATTRS, .flags = INTEL_X86_PEBS, .cntmsk = 0xf, .code = 0xd4, .numasks = LIBPFM_ARRAY_SIZE(skl_mem_load_misc_retired), .ngrp = 1, .umasks = skl_mem_load_misc_retired, }, { .name = "IDI_MISC", .desc = "Miscellaneous", .modmsk = INTEL_V4_ATTRS, .cntmsk = 0xf, .code = 0xfe, .numasks = LIBPFM_ARRAY_SIZE(skl_idi_misc), .model = PFM_PMU_INTEL_SKX, .ngrp = 1, .umasks = skl_idi_misc, }, { .name = "CORE_POWER", .desc = "Power power cycles", .modmsk = INTEL_V4_ATTRS, .cntmsk = 0xf, .code = 0x28, .numasks = LIBPFM_ARRAY_SIZE(skl_core_power), .model = PFM_PMU_INTEL_SKX, .ngrp = 1, .umasks = skl_core_power, }, { .name = "SW_PREFETCH", .desc = "Software prefetches", .modmsk = INTEL_V4_ATTRS, .equiv = "SW_PREFETCH_ACCESS", .cntmsk = 0xf, .code = 0x32, .numasks = LIBPFM_ARRAY_SIZE(skl_sw_prefetch), .ngrp = 1, .umasks = skl_sw_prefetch, }, { .name = "SW_PREFETCH_ACCESS", .desc = "Software prefetches", .modmsk = INTEL_V4_ATTRS, .cntmsk = 0xf, .code = 0x32, .numasks = LIBPFM_ARRAY_SIZE(skl_sw_prefetch), .ngrp = 1, .umasks = skl_sw_prefetch, }, { .name = "OFFCORE_REQUESTS_BUFFER", .desc = "Offcore requests buffer", .modmsk = INTEL_V4_ATTRS, .cntmsk = 0xff, .code = 0xb2, .numasks = LIBPFM_ARRAY_SIZE(skl_offcore_requests_buffer), .ngrp = 1, .umasks = skl_offcore_requests_buffer, }, { .name = "OFFCORE_RESPONSE_0", .desc = "Offcore response event (must provide at least one request type and either any_response or any combination of supplier + snoop)", .modmsk = INTEL_V4_ATTRS, .cntmsk = 0xf, .code = 0x1b7, .flags= INTEL_X86_NHM_OFFCORE, .numasks = LIBPFM_ARRAY_SIZE(skl_offcore_response), .ngrp = 3, .umasks = skl_offcore_response, }, { .name = "OFFCORE_RESPONSE_1", .desc = "Offcore response event (must provide at least one request type and either any_response or any combination of supplier + snoop)", .modmsk = INTEL_V4_ATTRS, .cntmsk = 0xf, .code = 0x1bb, .flags= INTEL_X86_NHM_OFFCORE, .numasks = LIBPFM_ARRAY_SIZE(skl_offcore_response), .ngrp = 3, .umasks = skl_offcore_response, /* identical to actual umasks list for this event */ }, }; libpfm-4.9.0/lib/events/sparc_ultra3plus_events.h0000664000175000017500000003001313223402656021730 0ustar eranianeranianstatic const sparc_entry_t ultra3plus_pe[] = { /* These two must always be first. */ { .name = "Cycle_cnt", .desc = "Accumulated cycles", .ctrl = PME_CTRL_S0 | PME_CTRL_S1, .code = 0x0, }, { .name = "Instr_cnt", .desc = "Number of instructions completed", .ctrl = PME_CTRL_S0 | PME_CTRL_S1, .code = 0x1, }, /* PIC0 events common to all UltraSPARC processors */ { .name = "Dispatch0_IC_miss", .desc = "I-buffer is empty from I-Cache miss", .ctrl = PME_CTRL_S0, .code = 0x2, }, { .name = "IC_ref", .desc = "I-cache references", .ctrl = PME_CTRL_S0, .code = 0x8, }, { .name = "DC_rd", .desc = "D-cache read references (including accesses that subsequently trap)", .ctrl = PME_CTRL_S0, .code = 0x9, }, { .name = "DC_wr", .desc = "D-cache store accesses (including cacheable stores that subsequently trap)", .ctrl = PME_CTRL_S0, .code = 0xa, }, { .name = "EC_ref", .desc = "E-cache references", .ctrl = PME_CTRL_S0, .code = 0xc, }, { .name = "EC_snoop_inv", .desc = "L2-cache invalidates generated from a snoop by a remote processor", .ctrl = PME_CTRL_S0, .code = 0xe, }, /* PIC1 events common to all UltraSPARC processors */ { .name = "Dispatch0_mispred", .desc = "I-buffer is empty from Branch misprediction", .ctrl = PME_CTRL_S1, .code = 0x2, }, { .name = "EC_wb", .desc = "Dirty sub-blocks that produce writebacks due to L2-cache miss events", .ctrl = PME_CTRL_S1, .code = 0xd, }, { .name = "EC_snoop_cb", .desc = "L2-cache copybacks generated from a snoop by a remote processor", .ctrl = PME_CTRL_S1, .code = 0xe, }, /* PIC0 events common to all UltraSPARC-III/III+/IIIi processors */ { .name = "Dispatch0_br_target", .desc = "I-buffer is empty due to a branch target address calculation", .ctrl = PME_CTRL_S0, .code = 0x3, }, { .name = "Dispatch0_2nd_br", .desc = "Stall cycles due to having two branch instructions line-up in one 4-instruction group causing the second branch in the group to be re-fetched, delaying it's entrance into the I-buffer", .ctrl = PME_CTRL_S0, .code = 0x4, }, { .name = "Rstall_storeQ", .desc = "R-stage stall for a store instruction which is the next instruction to be executed, but it stalled due to the store queue being full", .ctrl = PME_CTRL_S0, .code = 0x5, }, { .name = "Rstall_IU_use", .desc = "R-stage stall for an event that the next instruction to be executed depends on the result of a preceding integer instruction in the pipeline that is not yet available", .ctrl = PME_CTRL_S0, .code = 0x6, }, { .name = "EC_write_hit_RTO", .desc = "W-cache exclusive requests that hit L2-cache in S, O, or Os state and thus, do a read-to-own bus transaction", .ctrl = PME_CTRL_S0, .code = 0xd, }, { .name = "EC_rd_miss", .desc = "L2-cache miss events (including atomics) from D-cache events", .ctrl = PME_CTRL_S0, .code = 0xf, }, { .name = "PC_port0_rd", .desc = "P-cache cacheable FP loads to the first port (general purpose load path to D-cache and P-cache via MS pipeline)", .ctrl = PME_CTRL_S0, .code = 0x10, }, { .name = "SI_snoop", .desc = "Counts snoops from remote processor(s) including RTS, RTSR, RTO, RTOR, RS, RSR, RTSM, and WS", .ctrl = PME_CTRL_S0, .code = 0x11, }, { .name = "SI_ciq_flow", .desc = "Counts system clock cycles when the flow control (PauseOut) signal is asserted", .ctrl = PME_CTRL_S0, .code = 0x12, }, { .name = "SI_owned", .desc = "Counts events where owned_in is asserted on bus requests from the local processor", .ctrl = PME_CTRL_S0, .code = 0x13, }, { .name = "SW_count0", .desc = "Counts software-generated occurrences of 'sethi %hi(0xfc000), %g0' instruction", .ctrl = PME_CTRL_S0, .code = 0x14, }, { .name = "IU_Stat_Br_miss_taken", .desc = "Retired branches that were predicted to be taken, but in fact were not taken", .ctrl = PME_CTRL_S0, .code = 0x15, }, { .name = "IU_Stat_Br_Count_taken", .desc = "Retired taken branches", .ctrl = PME_CTRL_S0, .code = 0x16, }, { .name = "Dispatch0_rs_mispred", .desc = "I-buffer is empty due to a Return Address Stack misprediction", .ctrl = PME_CTRL_S0, .code = 0x4, }, { .name = "FA_pipe_completion", .desc = "Instructions that complete execution on the FPG ALU pipelines", .ctrl = PME_CTRL_S0, .code = 0x18, }, /* PIC1 events common to all UltraSPARC-III/III+/IIIi processors */ { .name = "IC_miss_cancelled", .desc = "I-cache misses cancelled due to mis-speculation, recycle, or other events", .ctrl = PME_CTRL_S1, .code = 0x3, }, { .name = "Re_FPU_bypass", .desc = "Stall due to recirculation when an FPU bypass condition that does not have a direct bypass path occurs", .ctrl = PME_CTRL_S1, .code = 0x5, }, { .name = "Re_DC_miss", .desc = "Stall due to loads that miss D-cache and get recirculated", .ctrl = PME_CTRL_S1, .code = 0x6, }, { .name = "Re_EC_miss", .desc = "Stall due to loads that miss L2-cache and get recirculated", .ctrl = PME_CTRL_S1, .code = 0x7, }, { .name = "IC_miss", .desc = "I-cache misses, including fetches from mis-speculated execution paths which are later cancelled", .ctrl = PME_CTRL_S1, .code = 0x8, }, { .name = "DC_rd_miss", .desc = "Recirculated loads that miss the D-cache", .ctrl = PME_CTRL_S1, .code = 0x9, }, { .name = "DC_wr_miss", .desc = "D-cache store accesses that miss D-cache", .ctrl = PME_CTRL_S1, .code = 0xa, }, { .name = "Rstall_FP_use", .desc = "R-stage stall for an event that the next instruction to be executed depends on the result of a preceding floating-point instruction in the pipeline that is not yet available", .ctrl = PME_CTRL_S1, .code = 0xb, }, { .name = "EC_misses", .desc = "E-cache misses", .ctrl = PME_CTRL_S1, .code = 0xc, }, { .name = "EC_ic_miss", .desc = "L2-cache read misses from I-cache requests", .ctrl = PME_CTRL_S1, .code = 0xf, }, { .name = "Re_PC_miss", .desc = "Stall due to recirculation when a prefetch cache miss occurs on a prefetch predicted second load", .ctrl = PME_CTRL_S1, .code = 0x10, }, { .name = "ITLB_miss", .desc = "I-TLB miss traps taken", .ctrl = PME_CTRL_S1, .code = 0x11, }, { .name = "DTLB_miss", .desc = "Memory reference instructions which trap due to D-TLB miss", .ctrl = PME_CTRL_S1, .code = 0x12, }, { .name = "WC_miss", .desc = "W-cache misses", .ctrl = PME_CTRL_S1, .code = 0x13, }, { .name = "WC_snoop_cb", .desc = "W-cache copybacks generated by a snoop from a remote processor", .ctrl = PME_CTRL_S1, .code = 0x14, }, { .name = "WC_scrubbed", .desc = "W-cache hits to clean lines", .ctrl = PME_CTRL_S1, .code = 0x15, }, { .name = "WC_wb_wo_read", .desc = "W-cache writebacks not requiring a read", .ctrl = PME_CTRL_S1, .code = 0x16, }, { .name = "PC_soft_hit", .desc = "FP loads that hit a P-cache line that was prefetched by a software-prefetch instruction", .ctrl = PME_CTRL_S1, .code = 0x18, }, { .name = "PC_snoop_inv", .desc = "P-cache invalidates that were generated by a snoop from a remote processor and stores by a local processor", .ctrl = PME_CTRL_S1, .code = 0x19, }, { .name = "PC_hard_hit", .desc = "FP loads that hit a P-cache line that was prefetched by a hardware prefetch", .ctrl = PME_CTRL_S1, .code = 0x1a, }, { .name = "PC_port1_rd", .desc = "P-cache cacheable FP loads to the second port (memory and out-of-pipeline instruction execution loads via the A0 and A1 pipelines)", .ctrl = PME_CTRL_S1, .code = 0x1b, }, { .name = "SW_count1", .desc = "Counts software-generated occurrences of 'sethi %hi(0xfc000), %g0' instruction", .ctrl = PME_CTRL_S1, .code = 0x1c, }, { .name = "IU_Stat_Br_miss_untaken", .desc = "Retired branches that were predicted to be untaken, but in fact were taken", .ctrl = PME_CTRL_S1, .code = 0x1d, }, { .name = "IU_Stat_Br_Count_untaken", .desc = "Retired untaken branches", .ctrl = PME_CTRL_S1, .code = 0x1e, }, { .name = "PC_MS_miss", .desc = "FP loads through the MS pipeline that miss P-cache", .ctrl = PME_CTRL_S1, .code = 0x1f, }, { .name = "Re_RAW_miss", .desc = "Stall due to recirculation when there is a load in the E-stage which has a non-bypassable read-after-write hazard with an earlier store instruction", .ctrl = PME_CTRL_S1, .code = 0x26, }, { .name = "FM_pipe_completion", .desc = "Instructions that complete execution on the FPG Multiply pipelines", .ctrl = PME_CTRL_S0, .code = 0x27, }, /* PIC0 memory controller events common to UltraSPARC-III/III+ processors */ { .name = "MC_reads_0", .desc = "Read requests completed to memory bank 0", .ctrl = PME_CTRL_S0, .code = 0x20, }, { .name = "MC_reads_1", .desc = "Read requests completed to memory bank 1", .ctrl = PME_CTRL_S0, .code = 0x21, }, { .name = "MC_reads_2", .desc = "Read requests completed to memory bank 2", .ctrl = PME_CTRL_S0, .code = 0x22, }, { .name = "MC_reads_3", .desc = "Read requests completed to memory bank 3", .ctrl = PME_CTRL_S0, .code = 0x23, }, { .name = "MC_stalls_0", .desc = "Clock cycles that requests were stalled in the MCU queues because bank 0 was busy with a previous request", .ctrl = PME_CTRL_S0, .code = 0x24, }, { .name = "MC_stalls_2", .desc = "Clock cycles that requests were stalled in the MCU queues because bank 2 was busy with a previous request", .ctrl = PME_CTRL_S0, .code = 0x25, }, /* PIC1 memory controller events common to all UltraSPARC-III/III+ processors */ { .name = "MC_writes_0", .desc = "Write requests completed to memory bank 0", .ctrl = PME_CTRL_S1, .code = 0x20, }, { .name = "MC_writes_1", .desc = "Write requests completed to memory bank 1", .ctrl = PME_CTRL_S1, .code = 0x21, }, { .name = "MC_writes_2", .desc = "Write requests completed to memory bank 2", .ctrl = PME_CTRL_S1, .code = 0x22, }, { .name = "MC_writes_3", .desc = "Write requests completed to memory bank 3", .ctrl = PME_CTRL_S1, .code = 0x23, }, { .name = "MC_stalls_1", .desc = "Clock cycles that requests were stalled in the MCU queues because bank 1 was busy with a previous request", .ctrl = PME_CTRL_S1, .code = 0x24, }, { .name = "MC_stalls_3", .desc = "Clock cycles that requests were stalled in the MCU queues because bank 3 was busy with a previous request", .ctrl = PME_CTRL_S1, .code = 0x25, }, /* PIC0 events specific to UltraSPARC-III+ processors */ { .name = "EC_wb_remote", .desc = "Counts the retry event when any victimization for which the processor generates an R_WB transaction to non_LPA address region", .ctrl = PME_CTRL_S0, .code = 0x19, }, { .name = "EC_miss_local", .desc = "Counts any transaction to an LPA for which the processor issues an RTS/RTO/RS transaction", .ctrl = PME_CTRL_S0, .code = 0x1a, }, { .name = "EC_miss_mtag_remote", .desc = "Counts any transaction to an LPA in which the processor is required to generate a retry transaction", .ctrl = PME_CTRL_S0, .code = 0x1b, }, /* PIC1 events specific to UltraSPARC-III+/IIIi processors */ { .name = "Re_DC_missovhd", .desc = "Used to measure D-cache stall counts separately for L2-cache hits and misses. This counter is used with the recirculation and cache access events to separately calculate the D-cache loads that hit and miss the L2-cache", .ctrl = PME_CTRL_S1, .code = 0x4, }, /* PIC1 events specific to UltraSPARC-III+ processors */ { .name = "EC_miss_mtag_remote", .desc = "Counts any transaction to an LPA in which the processor is required to generate a retry transaction", .ctrl = PME_CTRL_S1, .code = 0x28, }, { .name = "EC_miss_remote", .desc = "Counts the events triggered whenever the processor generates a remote (R_*) transaction and the address is to a non-LPA portion (remote) of the physical address space, or an R_WS transaction due to block-store/block-store-commit to any address space (LPA or non-LPA), or an R-RTO due to store/swap request on Os state to LPA space", .ctrl = PME_CTRL_S1, .code = 0x29, }, }; #define PME_SPARC_ULTRA3PLUS_EVENT_COUNT (sizeof(ultra3plus_pe)/sizeof(sparc_entry_t)) libpfm-4.9.0/lib/events/intel_netburst_events.h0000664000175000017500000011321713223402656021473 0ustar eranianeranian/* * Copyright (c) 2006 IBM Corp. * Contributed by Kevin Corry * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * * This header contains arrays to describe the Event-Selection-Control * Registers (ESCRs), Counter-Configuration-Control Registers (CCCRs), * and countable events on Pentium4/Xeon/EM64T systems. * * For more details, see: * - IA-32 Intel Architecture Software Developer's Manual, * Volume 3B: System Programming Guide, Part 2 * (available at: http://www.intel.com/design/Pentium4/manuals/253669.htm) * - Chapter 18.10: Performance Monitoring Overview * - Chapter 18.13: Performance Monitoring - Pentium4 and Xeon Processors * - Chapter 18.14: Performance Monitoring and Hyper-Threading Technology * - Appendix A.1: Pentium4 and Xeon Processor Performance-Monitoring Events * * This header also contains an array to describe how the Perfmon PMCs map to * the ESCRs and CCCRs. */ #ifndef _NETBURST_EVENTS_H_ #define _NETBURST_EVENTS_H_ /** * netburst_events * * Array of events that can be counted on Pentium4. **/ static const netburst_entry_t netburst_events[] = { /* 0 */ {.name = "TC_deliver_mode", .desc = "The duration (in clock cycles) of the operating modes of " "the trace cache and decode engine in the processor package", .event_select = 0x1, .escr_select = 0x1, .allowed_escrs = { 9, 32 }, .perf_code = P4_EVENT_TC_DELIVER_MODE, .event_masks = { {.name = "DD", .desc = "Both logical CPUs in deliver mode", .bit = 0, }, {.name = "DB", .desc = "Logical CPU 0 in deliver mode and " "logical CPU 1 in build mode", .bit = 1, }, {.name = "DI", .desc = "Logical CPU 0 in deliver mode and logical CPU 1 " "either halted, under machine clear condition, or " "transitioning to a long microcode flow", .bit = 2, }, {.name = "BD", .desc = "Logical CPU 0 in build mode and " "logical CPU 1 is in deliver mode", .bit = 3, }, {.name = "BB", .desc = "Both logical CPUs in build mode", .bit = 4, }, {.name = "BI", .desc = "Logical CPU 0 in build mode and logical CPU 1 " "either halted, under machine clear condition, or " "transitioning to a long microcode flow", .bit = 5, }, {.name = "ID", .desc = "Logical CPU 0 either halted, under machine clear " "condition, or transitioning to a long microcode " "flow, and logical CPU 1 in deliver mode", .bit = 6, }, {.name = "IB", .desc = "Logical CPU 0 either halted, under machine clear " "condition, or transitioning to a long microcode " "flow, and logical CPU 1 in build mode", .bit = 7, }, }, }, /* 1 */ {.name = "BPU_fetch_request", .desc = "Instruction fetch requests by the Branch Prediction Unit", .event_select = 0x3, .escr_select = 0x0, .allowed_escrs = { 0, 23 }, .perf_code = P4_EVENT_BPU_FETCH_REQUEST, .event_masks = { {.name = "TCMISS", .desc = "Trace cache lookup miss", .bit = 0, .flags = NETBURST_FL_DFL, }, }, }, /* 2 */ {.name = "ITLB_reference", .desc = "Translations using the Instruction " "Translation Look-Aside Buffer", .event_select = 0x18, .escr_select = 0x3, .allowed_escrs = { 3, 26 }, .perf_code = P4_EVENT_ITLB_REFERENCE, .event_masks = { {.name = "HIT", .desc = "ITLB hit", .bit = 0, }, {.name = "MISS", .desc = "ITLB miss", .bit = 1, }, {.name = "HIT_UC", .desc = "Uncacheable ITLB hit", .bit = 2, }, }, }, /* 3 */ {.name = "memory_cancel", .desc = "Canceling of various types of requests in the " "Data cache Address Control unit (DAC)", .event_select = 0x2, .escr_select = 0x5, .allowed_escrs = { 15, 38 }, .perf_code = P4_EVENT_MEMORY_CANCEL, .event_masks = { {.name = "ST_RB_FULL", .desc = "Replayed because no store request " "buffer is available", .bit = 2, }, {.name = "64K_CONF", .desc = "Conflicts due to 64K aliasing", .bit = 3, }, }, }, /* 4 */ {.name = "memory_complete", .desc = "Completions of a load split, store split, " "uncacheable (UC) split, or UC load", .event_select = 0x8, .escr_select = 0x2, .allowed_escrs = { 13, 36 }, .perf_code = P4_EVENT_MEMORY_COMPLETE, .event_masks = { {.name = "LSC", .desc = "Load split completed, excluding UC/WC loads", .bit = 0, }, {.name = "SSC", .desc = "Any split stores completed", .bit = 1, }, }, }, /* 5 */ {.name = "load_port_replay", .desc = "Replayed events at the load port", .event_select = 0x4, .escr_select = 0x2, .allowed_escrs = { 13, 36 }, .perf_code = P4_EVENT_LOAD_PORT_REPLAY, .event_masks = { {.name = "SPLIT_LD", .desc = "Split load", .bit = 1, .flags = NETBURST_FL_DFL, }, }, }, /* 6 */ {.name = "store_port_replay", .desc = "Replayed events at the store port", .event_select = 0x5, .escr_select = 0x2, .allowed_escrs = { 13, 36 }, .perf_code = P4_EVENT_STORE_PORT_REPLAY, .event_masks = { {.name = "SPLIT_ST", .desc = "Split store", .bit = 1, .flags = NETBURST_FL_DFL, }, }, }, /* 7 */ {.name = "MOB_load_replay", .desc = "Count of times the memory order buffer (MOB) " "caused a load operation to be replayed", .event_select = 0x3, .escr_select = 0x2, .allowed_escrs = { 2, 25 }, .perf_code = P4_EVENT_MOB_LOAD_REPLAY, .event_masks = { {.name = "NO_STA", .desc = "Replayed because of unknown store address", .bit = 1, }, {.name = "NO_STD", .desc = "Replayed because of unknown store data", .bit = 3, }, {.name = "PARTIAL_DATA", .desc = "Replayed because of partially overlapped data " "access between the load and store operations", .bit = 4, }, {.name = "UNALGN_ADDR", .desc = "Replayed because the lower 4 bits of the " "linear address do not match between the " "load and store operations", .bit = 5, }, }, }, /* 8 */ {.name = "page_walk_type", .desc = "Page walks that the page miss handler (PMH) performs", .event_select = 0x1, .escr_select = 0x4, .allowed_escrs = { 4, 27 }, .perf_code = P4_EVENT_PAGE_WALK_TYPE, .event_masks = { {.name = "DTMISS", .desc = "Page walk for a data TLB miss (load or store)", .bit = 0, }, {.name = "ITMISS", .desc = "Page walk for an instruction TLB miss", .bit = 1, }, }, }, /* 9 */ {.name = "BSQ_cache_reference", .desc = "Cache references (2nd or 3rd level caches) as seen by the " "bus unit. Read types include both load and RFO, and write " "types include writebacks and evictions", .event_select = 0xC, .escr_select = 0x7, .allowed_escrs = { 7, 30 }, .perf_code = P4_EVENT_BSQ_CACHE_REFERENCE, .event_masks = { {.name = "RD_2ndL_HITS", .desc = "Read 2nd level cache hit Shared", .bit = 0, }, {.name = "RD_2ndL_HITE", .desc = "Read 2nd level cache hit Exclusive", .bit = 1, }, {.name = "RD_2ndL_HITM", .desc = "Read 2nd level cache hit Modified", .bit = 2, }, {.name = "RD_3rdL_HITS", .desc = "Read 3rd level cache hit Shared", .bit = 3, }, {.name = "RD_3rdL_HITE", .desc = "Read 3rd level cache hit Exclusive", .bit = 4, }, {.name = "RD_3rdL_HITM", .desc = "Read 3rd level cache hit Modified", .bit = 5, }, {.name = "RD_2ndL_MISS", .desc = "Read 2nd level cache miss", .bit = 8, }, {.name = "RD_3rdL_MISS", .desc = "Read 3rd level cache miss", .bit = 9, }, {.name = "WR_2ndL_MISS", .desc = "A writeback lookup from DAC misses the 2nd " "level cache (unlikely to happen)", .bit = 10, }, }, }, /* 10 */ {.name = "IOQ_allocation", .desc = "Count of various types of transactions on the bus. A count " "is generated each time a transaction is allocated into the " "IOQ that matches the specified mask bits. An allocated entry " "can be a sector (64 bytes) or a chunk of 8 bytes. Requests " "are counted once per retry. All 'TYPE_BIT*' event-masks " "together are treated as a single 5-bit value", .event_select = 0x3, .escr_select = 0x6, .allowed_escrs = { 6, 29 }, .perf_code = P4_EVENT_IOQ_ALLOCATION, .event_masks = { {.name = "TYPE_BIT0", .desc = "Bus request type (bit 0)", .bit = 0, }, {.name = "TYPE_BIT1", .desc = "Bus request type (bit 1)", .bit = 1, }, {.name = "TYPE_BIT2", .desc = "Bus request type (bit 2)", .bit = 2, }, {.name = "TYPE_BIT3", .desc = "Bus request type (bit 3)", .bit = 3, }, {.name = "TYPE_BIT4", .desc = "Bus request type (bit 4)", .bit = 4, }, {.name = "ALL_READ", .desc = "Count read entries", .bit = 5, }, {.name = "ALL_WRITE", .desc = "Count write entries", .bit = 6, }, {.name = "MEM_UC", .desc = "Count UC memory access entries", .bit = 7, }, {.name = "MEM_WC", .desc = "Count WC memory access entries", .bit = 8, }, {.name = "MEM_WT", .desc = "Count write-through (WT) memory access entries", .bit = 9, }, {.name = "MEM_WP", .desc = "Count write-protected (WP) memory access entries", .bit = 10, }, {.name = "MEM_WB", .desc = "Count WB memory access entries", .bit = 11, }, {.name = "OWN", .desc = "Count all store requests driven by processor, as " "opposed to other processor or DMA", .bit = 13, }, {.name = "OTHER", .desc = "Count all requests driven by other " "processors or DMA", .bit = 14, }, {.name = "PREFETCH", .desc = "Include HW and SW prefetch requests in the count", .bit = 15, }, }, }, /* 11 */ {.name = "IOQ_active_entries", .desc = "Number of entries (clipped at 15) in the IOQ that are " "active. An allocated entry can be a sector (64 bytes) " "or a chunk of 8 bytes. This event must be programmed in " "conjunction with IOQ_allocation. All 'TYPE_BIT*' event-masks " "together are treated as a single 5-bit value", .event_select = 0x1A, .escr_select = 0x6, .allowed_escrs = { 29, -1 }, .perf_code = P4_EVENT_IOQ_ACTIVE_ENTRIES, .event_masks = { {.name = "TYPE_BIT0", .desc = "Bus request type (bit 0)", .bit = 0, }, {.name = "TYPE_BIT1", .desc = "Bus request type (bit 1)", .bit = 1, }, {.name = "TYPE_BIT2", .desc = "Bus request type (bit 2)", .bit = 2, }, {.name = "TYPE_BIT3", .desc = "Bus request type (bit 3)", .bit = 3, }, {.name = "TYPE_BIT4", .desc = "Bus request type (bit 4)", .bit = 4, }, {.name = "ALL_READ", .desc = "Count read entries", .bit = 5, }, {.name = "ALL_WRITE", .desc = "Count write entries", .bit = 6, }, {.name = "MEM_UC", .desc = "Count UC memory access entries", .bit = 7, }, {.name = "MEM_WC", .desc = "Count WC memory access entries", .bit = 8, }, {.name = "MEM_WT", .desc = "Count write-through (WT) memory access entries", .bit = 9, }, {.name = "MEM_WP", .desc = "Count write-protected (WP) memory access entries", .bit = 10, }, {.name = "MEM_WB", .desc = "Count WB memory access entries", .bit = 11, }, {.name = "OWN", .desc = "Count all store requests driven by processor, as " "opposed to other processor or DMA", .bit = 13, }, {.name = "OTHER", .desc = "Count all requests driven by other " "processors or DMA", .bit = 14, }, {.name = "PREFETCH", .desc = "Include HW and SW prefetch requests in the count", .bit = 15, }, }, }, /* 12 */ {.name = "FSB_data_activity", .desc = "Count of DRDY or DBSY events that " "occur on the front side bus", .event_select = 0x17, .escr_select = 0x6, .allowed_escrs = { 6, 29 }, .perf_code = P4_EVENT_FSB_DATA_ACTIVITY, .event_masks = { {.name = "DRDY_DRV", .desc = "Count when this processor drives data onto the bus. " "Includes writes and implicit writebacks", .bit = 0, }, {.name = "DRDY_OWN", .desc = "Count when this processor reads data from the bus. " "Includes loads and some PIC transactions. Count " "DRDY events that we drive. Count DRDY events sampled " "that we own", .bit = 1, }, {.name = "DRDY_OTHER", .desc = "Count when data is on the bus but not being sampled " "by the processor. It may or may not be driven by " "this processor", .bit = 2, }, {.name = "DBSY_DRV", .desc = "Count when this processor reserves the bus for use " "in the next bus cycle in order to drive data", .bit = 3, }, {.name = "DBSY_OWN", .desc = "Count when some agent reserves the bus for use in " "the next bus cycle to drive data that this processor " "will sample", .bit = 4, }, {.name = "DBSY_OTHER", .desc = "Count when some agent reserves the bus for use in " "the next bus cycle to drive data that this processor " "will NOT sample. It may or may not be being driven " "by this processor", .bit = 5, }, }, }, /* 13 */ {.name = "BSQ_allocation", .desc = "Allocations in the Bus Sequence Unit (BSQ). The event mask " "bits consist of four sub-groups: request type, request " "length, memory type, and a sub-group consisting mostly of " "independent bits (5 through 10). Must specify a mask for " "each sub-group", .event_select = 0x5, .escr_select = 0x7, .allowed_escrs = { 7, -1 }, .perf_code = P4_EVENT_BSQ_ALLOCATION, .event_masks = { {.name = "REQ_TYPE0", .desc = "Along with REQ_TYPE1, request type encodings are: " "0 - Read (excludes read invalidate), 1 - Read " "invalidate, 2 - Write (other than writebacks), 3 - " "Writeback (evicted from cache)", .bit = 0, }, {.name = "REQ_TYPE1", .desc = "Along with REQ_TYPE0, request type encodings are: " "0 - Read (excludes read invalidate), 1 - Read " "invalidate, 2 - Write (other than writebacks), 3 - " "Writeback (evicted from cache)", .bit = 1, }, {.name = "REQ_LEN0", .desc = "Along with REQ_LEN1, request length encodings are: " "0 - zero chunks, 1 - one chunk, 3 - eight chunks", .bit = 2, }, {.name = "REQ_LEN1", .desc = "Along with REQ_LEN0, request length encodings are: " "0 - zero chunks, 1 - one chunk, 3 - eight chunks", .bit = 3, }, {.name = "REQ_IO_TYPE", .desc = "Request type is input or output", .bit = 5, }, {.name = "REQ_LOCK_TYPE", .desc = "Request type is bus lock", .bit = 6, }, {.name = "REQ_CACHE_TYPE", .desc = "Request type is cacheable", .bit = 7, }, {.name = "REQ_SPLIT_TYPE", .desc = "Request type is a bus 8-byte chunk split across " "an 8-byte boundary", .bit = 8, }, {.name = "REQ_DEM_TYPE", .desc = "0: Request type is HW.SW prefetch. " "1: Request type is a demand", .bit = 9, }, {.name = "REQ_ORD_TYPE", .desc = "Request is an ordered type", .bit = 10, }, {.name = "MEM_TYPE0", .desc = "Along with MEM_TYPE1 and MEM_TYPE2, " "memory type encodings are: 0 - UC, " "1 - USWC, 4- WT, 5 - WP, 6 - WB", .bit = 11, }, {.name = "MEM_TYPE1", .desc = "Along with MEM_TYPE0 and MEM_TYPE2, " "memory type encodings are: 0 - UC, " "1 - USWC, 4- WT, 5 - WP, 6 - WB", .bit = 12, }, {.name = "MEM_TYPE2", .desc = "Along with MEM_TYPE0 and MEM_TYPE1, " "memory type encodings are: 0 - UC, " "1 - USWC, 4- WT, 5 - WP, 6 - WB", .bit = 13, }, }, }, /* 14 */ {.name = "BSQ_active_entries", .desc = "Number of BSQ entries (clipped at 15) currently active " "(valid) which meet the subevent mask criteria during " "allocation in the BSQ. Active request entries are allocated " "on the BSQ until de-allocated. De-allocation of an entry " "does not necessarily imply the request is filled. This " "event must be programmed in conjunction with BSQ_allocation", .event_select = 0x6, .escr_select = 0x7, .allowed_escrs = { 30, -1 }, .perf_code = P4_EVENT_BSQ_ACTIVE_ENTRIES, .event_masks = { {.name = "REQ_TYPE0", .desc = "Along with REQ_TYPE1, request type encodings are: " "0 - Read (excludes read invalidate), 1 - Read " "invalidate, 2 - Write (other than writebacks), 3 - " "Writeback (evicted from cache)", .bit = 0, }, {.name = "REQ_TYPE1", .desc = "Along with REQ_TYPE0, request type encodings are: " "0 - Read (excludes read invalidate), 1 - Read " "invalidate, 2 - Write (other than writebacks), 3 - " "Writeback (evicted from cache)", .bit = 1, }, {.name = "REQ_LEN0", .desc = "Along with REQ_LEN1, request length encodings are: " "0 - zero chunks, 1 - one chunk, 3 - eight chunks", .bit = 2, }, {.name = "REQ_LEN1", .desc = "Along with REQ_LEN0, request length encodings are: " "0 - zero chunks, 1 - one chunk, 3 - eight chunks", .bit = 3, }, {.name = "REQ_IO_TYPE", .desc = "Request type is input or output", .bit = 5, }, {.name = "REQ_LOCK_TYPE", .desc = "Request type is bus lock", .bit = 6, }, {.name = "REQ_CACHE_TYPE", .desc = "Request type is cacheable", .bit = 7, }, {.name = "REQ_SPLIT_TYPE", .desc = "Request type is a bus 8-byte chunk split across " "an 8-byte boundary", .bit = 8, }, {.name = "REQ_DEM_TYPE", .desc = "0: Request type is HW.SW prefetch. " "1: Request type is a demand", .bit = 9, }, {.name = "REQ_ORD_TYPE", .desc = "Request is an ordered type", .bit = 10, }, {.name = "MEM_TYPE0", .desc = "Along with MEM_TYPE1 and MEM_TYPE2, " "memory type encodings are: 0 - UC, " "1 - USWC, 4- WT, 5 - WP, 6 - WB", .bit = 11, }, {.name = "MEM_TYPE1", .desc = "Along with MEM_TYPE0 and MEM_TYPE2, " "memory type encodings are: 0 - UC, " "1 - USWC, 4- WT, 5 - WP, 6 - WB", .bit = 12, }, {.name = "MEM_TYPE2", .desc = "Along with MEM_TYPE0 and MEM_TYPE1, " "memory type encodings are: 0 - UC, " "1 - USWC, 4- WT, 5 - WP, 6 - WB", .bit = 13, }, }, }, /* 15 */ {.name = "SSE_input_assist", .desc = "Number of times an assist is requested to handle problems " "with input operands for SSE/SSE2/SSE3 operations; most " "notably denormal source operands when the DAZ bit isn't set", .event_select = 0x34, .escr_select = 0x1, .allowed_escrs = { 12, 35 }, .perf_code = P4_EVENT_SSE_INPUT_ASSIST, .event_masks = { {.name = "ALL", .desc = "Count assists for SSE/SSE2/SSE3 uops", .bit = 15, .flags = NETBURST_FL_DFL, }, }, }, /* 16 */ {.name = "packed_SP_uop", .desc = "Number of packed single-precision uops", .event_select = 0x8, .escr_select = 0x1, .perf_code = P4_EVENT_PACKED_SP_UOP, .allowed_escrs = { 12, 35 }, .event_masks = { {.name = "ALL", .desc = "Count all uops operating on packed " "single-precisions operands", .bit = 15, .flags = NETBURST_FL_DFL, }, {.name = "TAG0", .desc = "Tag this event with tag bit 0 " "for retirement counting with execution_event", .bit = 16, }, {.name = "TAG1", .desc = "Tag this event with tag bit 1 " "for retirement counting with execution_event", .bit = 17, }, {.name = "TAG2", .desc = "Tag this event with tag bit 2 " "for retirement counting with execution_event", .bit = 18, }, {.name = "TAG3", .desc = "Tag this event with tag bit 3 " "for retirement counting with execution_event", .bit = 19, }, }, }, /* 17 */ {.name = "packed_DP_uop", .desc = "Number of packed double-precision uops", .event_select = 0xC, .escr_select = 0x1, .allowed_escrs = { 12, 35 }, .perf_code = P4_EVENT_PACKED_DP_UOP, .event_masks = { {.name = "ALL", .desc = "Count all uops operating on packed " "double-precisions operands", .bit = 15, .flags = NETBURST_FL_DFL, }, {.name = "TAG0", .desc = "Tag this event with tag bit 0 " "for retirement counting with execution_event", .bit = 16, }, {.name = "TAG1", .desc = "Tag this event with tag bit 1 " "for retirement counting with execution_event", .bit = 17, }, {.name = "TAG2", .desc = "Tag this event with tag bit 2 " "for retirement counting with execution_event", .bit = 18, }, {.name = "TAG3", .desc = "Tag this event with tag bit 3 " "for retirement counting with execution_event", .bit = 19, }, }, }, /* 18 */ {.name = "scalar_SP_uop", .desc = "Number of scalar single-precision uops", .event_select = 0xA, .escr_select = 0x1, .allowed_escrs = { 12, 35 }, .perf_code = P4_EVENT_SCALAR_SP_UOP, .event_masks = { {.name = "ALL", .desc = "Count all uops operating on scalar " "single-precisions operands", .bit = 15, .flags = NETBURST_FL_DFL, }, {.name = "TAG0", .desc = "Tag this event with tag bit 0 " "for retirement counting with execution_event", .bit = 16, }, {.name = "TAG1", .desc = "Tag this event with tag bit 1 " "for retirement counting with execution_event", .bit = 17, }, {.name = "TAG2", .desc = "Tag this event with tag bit 2 " "for retirement counting with execution_event", .bit = 18, }, {.name = "TAG3", .desc = "Tag this event with tag bit 3 " "for retirement counting with execution_event", .bit = 19, }, }, }, /* 19 */ {.name = "scalar_DP_uop", .desc = "Number of scalar double-precision uops", .event_select = 0xE, .escr_select = 0x1, .allowed_escrs = { 12, 35 }, .perf_code = P4_EVENT_SCALAR_DP_UOP, .event_masks = { {.name = "ALL", .desc = "Count all uops operating on scalar " "double-precisions operands", .bit = 15, .flags = NETBURST_FL_DFL, }, {.name = "TAG0", .desc = "Tag this event with tag bit 0 " "for retirement counting with execution_event", .bit = 16, }, {.name = "TAG1", .desc = "Tag this event with tag bit 1 " "for retirement counting with execution_event", .bit = 17, }, {.name = "TAG2", .desc = "Tag this event with tag bit 2 " "for retirement counting with execution_event", .bit = 18, }, {.name = "TAG3", .desc = "Tag this event with tag bit 3 " "for retirement counting with execution_event", .bit = 19, }, }, }, /* 20 */ {.name = "64bit_MMX_uop", .desc = "Number of MMX instructions which " "operate on 64-bit SIMD operands", .event_select = 0x2, .escr_select = 0x1, .allowed_escrs = { 12, 35 }, .perf_code = P4_EVENT_64BIT_MMX_UOP, .event_masks = { {.name = "ALL", .desc = "Count all uops operating on 64-bit SIMD integer " "operands in memory or MMX registers", .bit = 15, .flags = NETBURST_FL_DFL, }, {.name = "TAG0", .desc = "Tag this event with tag bit 0 " "for retirement counting with execution_event", .bit = 16, }, {.name = "TAG1", .desc = "Tag this event with tag bit 1 " "for retirement counting with execution_event", .bit = 17, }, {.name = "TAG2", .desc = "Tag this event with tag bit 2 " "for retirement counting with execution_event", .bit = 18, }, {.name = "TAG3", .desc = "Tag this event with tag bit 3 " "for retirement counting with execution_event", .bit = 19, }, }, }, /* 21 */ {.name = "128bit_MMX_uop", .desc = "Number of MMX instructions which " "operate on 128-bit SIMD operands", .event_select = 0x1A, .escr_select = 0x1, .allowed_escrs = { 12, 35 }, .perf_code = P4_EVENT_128BIT_MMX_UOP, .event_masks = { {.name = "ALL", .desc = "Count all uops operating on 128-bit SIMD integer " "operands in memory or MMX registers", .bit = 15, .flags = NETBURST_FL_DFL, }, {.name = "TAG0", .desc = "Tag this event with tag bit 0 " "for retirement counting with execution_event", .bit = 16, }, {.name = "TAG1", .desc = "Tag this event with tag bit 1 " "for retirement counting with execution_event", .bit = 17, }, {.name = "TAG2", .desc = "Tag this event with tag bit 2 " "for retirement counting with execution_event", .bit = 18, }, {.name = "TAG3", .desc = "Tag this event with tag bit 3 " "for retirement counting with execution_event", .bit = 19, }, }, }, /* 22 */ {.name = "x87_FP_uop", .desc = "Number of x87 floating-point uops", .event_select = 0x4, .escr_select = 0x1, .allowed_escrs = { 12, 35 }, .perf_code = P4_EVENT_X87_FP_UOP, .event_masks = { {.name = "ALL", .desc = "Count all x87 FP uops", .bit = 15, .flags = NETBURST_FL_DFL, }, {.name = "TAG0", .desc = "Tag this event with tag bit 0 " "for retirement counting with execution_event", .bit = 16, }, {.name = "TAG1", .desc = "Tag this event with tag bit 1 " "for retirement counting with execution_event", .bit = 17, }, {.name = "TAG2", .desc = "Tag this event with tag bit 2 " "for retirement counting with execution_event", .bit = 18, }, {.name = "TAG3", .desc = "Tag this event with tag bit 3 " "for retirement counting with execution_event", .bit = 19, }, }, }, /* 23 */ {.name = "TC_misc", .desc = "Miscellaneous events detected by the TC. The counter will " "count twice for each occurrence", .event_select = 0x6, .escr_select = 0x1, .allowed_escrs = { 9, 32 }, .perf_code = P4_EVENT_TC_MISC, .event_masks = { {.name = "FLUSH", .desc = "Number of flushes", .bit = 4, .flags = NETBURST_FL_DFL, }, }, }, /* 24 */ {.name = "global_power_events", .desc = "Counts the time during which a processor is not stopped", .event_select = 0x13, .escr_select = 0x6, .allowed_escrs = { 6, 29 }, .perf_code = P4_EVENT_GLOBAL_POWER_EVENTS, .event_masks = { {.name = "RUNNING", .desc = "The processor is active (includes the " "handling of HLT STPCLK and throttling", .bit = 0, .flags = NETBURST_FL_DFL, }, }, }, /* 25 */ {.name = "tc_ms_xfer", .desc = "Number of times that uop delivery changed from TC to MS ROM", .event_select = 0x5, .escr_select = 0x0, .allowed_escrs = { 8, 31 }, .perf_code = P4_EVENT_TC_MS_XFER, .event_masks = { {.name = "CISC", .desc = "A TC to MS transfer occurred", .bit = 0, .flags = NETBURST_FL_DFL, }, }, }, /* 26 */ {.name = "uop_queue_writes", .desc = "Number of valid uops written to the uop queue", .event_select = 0x9, .escr_select = 0x0, .allowed_escrs = { 8, 31 }, .perf_code = P4_EVENT_UOP_QUEUE_WRITES, .event_masks = { {.name = "FROM_TC_BUILD", .desc = "The uops being written are from TC build mode", .bit = 0, }, {.name = "FROM_TC_DELIVER", .desc = "The uops being written are from TC deliver mode", .bit = 1, }, {.name = "FROM_ROM", .desc = "The uops being written are from microcode ROM", .bit = 2, }, }, }, /* 27 */ {.name = "retired_mispred_branch_type", .desc = "Number of retiring mispredicted branches by type", .event_select = 0x5, .escr_select = 0x2, .allowed_escrs = { 10, 33 }, .perf_code = P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, .event_masks = { {.name = "CONDITIONAL", .desc = "Conditional jumps", .bit = 1, }, {.name = "CALL", .desc = "Indirect call branches", .bit = 2, }, {.name = "RETURN", .desc = "Return branches", .bit = 3, }, {.name = "INDIRECT", .desc = "Returns, indirect calls, or indirect jumps", .bit = 4, }, }, }, /* 28 */ {.name = "retired_branch_type", .desc = "Number of retiring branches by type", .event_select = 0x4, .escr_select = 0x2, .allowed_escrs = { 10, 33 }, .perf_code = P4_EVENT_RETIRED_BRANCH_TYPE, .event_masks = { {.name = "CONDITIONAL", .desc = "Conditional jumps", .bit = 1, }, {.name = "CALL", .desc = "Indirect call branches", .bit = 2, }, {.name = "RETURN", .desc = "Return branches", .bit = 3, }, {.name = "INDIRECT", .desc = "Returns, indirect calls, or indirect jumps", .bit = 4, }, }, }, /* 29 */ {.name = "resource_stall", .desc = "Occurrences of latency or stalls in the Allocator", .event_select = 0x1, .escr_select = 0x1, .allowed_escrs = { 17, 40 }, .perf_code = P4_EVENT_RESOURCE_STALL, .event_masks = { {.name = "SBFULL", .desc = "A stall due to lack of store buffers", .bit = 5, .flags = NETBURST_FL_DFL, }, }, }, /* 30 */ {.name = "WC_Buffer", .desc = "Number of Write Combining Buffer operations", .event_select = 0x5, .escr_select = 0x5, .allowed_escrs = { 15, 38 }, .perf_code = P4_EVENT_WC_BUFFER, .event_masks = { {.name = "WCB_EVICTS", .desc = "WC Buffer evictions of all causes", .bit = 0, }, {.name = "WCB_FULL_EVICT", .desc = "WC Buffer eviction; no WC buffer is available", .bit = 1, }, }, }, /* 31 */ {.name = "b2b_cycles", .desc = "Number of back-to-back bus cycles", .event_select = 0x16, .escr_select = 0x3, .allowed_escrs = { 6, 29 }, .perf_code = P4_EVENT_B2B_CYCLES, .event_masks = { {.name = "BIT1", .desc = "bit 1", .bit = 1, }, {.name = "BIT2", .desc = "bit 2", .bit = 2, }, {.name = "BIT3", .desc = "bit 3", .bit = 3, }, {.name = "BIT4", .desc = "bit 4", .bit = 4, }, {.name = "BIT5", .desc = "bit 5", .bit = 4, }, {.name = "BIT6", .desc = "bit 6", .bit = 4, }, }, }, /* 32 */ {.name = "bnr", .desc = "Number of bus-not-ready conditions", .event_select = 0x8, .escr_select = 0x3, .allowed_escrs = { 6, 29 }, .perf_code = P4_EVENT_BNR, .event_masks = { {.name = "BIT0", .desc = "bit 0", .bit = 0, }, {.name = "BIT1", .desc = "bit 1", .bit = 1, }, {.name = "BIT2", .desc = "bit 2", .bit = 2, }, }, }, /* 33 */ {.name = "snoop", .desc = "Number of snoop hit modified bus traffic", .event_select = 0x6, .escr_select = 0x3, .allowed_escrs = { 6, 29 }, .perf_code = P4_EVENT_SNOOP, .event_masks = { {.name = "BIT2", .desc = "bit 2", .bit = 2, }, {.name = "BIT6", .desc = "bit 6", .bit = 6, }, {.name = "BIT7", .desc = "bit 7", .bit = 7, }, }, }, /* 34 */ {.name = "response", .desc = "Count of different types of responses", .event_select = 0x4, .escr_select = 0x3, .allowed_escrs = { 6, 29 }, .perf_code = P4_EVENT_RESPONSE, .event_masks = { {.name = "BIT1", .desc = "bit 1", .bit = 1, }, {.name = "BIT2", .desc = "bit 2", .bit = 2, }, {.name = "BIT8", .desc = "bit 8", .bit = 8, }, {.name = "BIT9", .desc = "bit 9", .bit = 9, }, }, }, /* 35 */ {.name = "front_end_event", .desc = "Number of retirements of tagged uops which are specified " "through the front-end tagging mechanism", .event_select = 0x8, .escr_select = 0x5, .allowed_escrs = { 21, 43 }, .perf_code = P4_EVENT_FRONT_END_EVENT, .event_masks = { {.name = "NBOGUS", .desc = "The marked uops are not bogus", .bit = 0, }, {.name = "BOGUS", .desc = "The marked uops are bogus", .bit = 1, }, }, }, /* 36 */ {.name = "execution_event", .desc = "Number of retirements of tagged uops which are specified " "through the execution tagging mechanism. The event-mask " "allows from one to four types of uops to be tagged", .event_select = 0xC, .escr_select = 0x5, .allowed_escrs = { 21, 43 }, .perf_code = P4_EVENT_EXECUTION_EVENT, .event_masks = { {.name = "NBOGUS0", .desc = "The marked uops are not bogus", .bit = 0, }, {.name = "NBOGUS1", .desc = "The marked uops are not bogus", .bit = 1, }, {.name = "NBOGUS2", .desc = "The marked uops are not bogus", .bit = 2, }, {.name = "NBOGUS3", .desc = "The marked uops are not bogus", .bit = 3, }, {.name = "BOGUS0", .desc = "The marked uops are bogus", .bit = 4, }, {.name = "BOGUS1", .desc = "The marked uops are bogus", .bit = 5, }, {.name = "BOGUS2", .desc = "The marked uops are bogus", .bit = 6, }, {.name = "BOGUS3", .desc = "The marked uops are bogus", .bit = 7, }, }, }, /* 37 */ {.name = "replay_event", .desc = "Number of retirements of tagged uops which are specified " "through the replay tagging mechanism", .event_select = 0x9, .escr_select = 0x5, .allowed_escrs = { 21, 43 }, .perf_code = P4_EVENT_REPLAY_EVENT, .event_masks = { {.name = "NBOGUS", .desc = "The marked uops are not bogus", .bit = 0, }, {.name = "BOGUS", .desc = "The marked uops are bogus", .bit = 1, }, {.name = "L1_LD_MISS", .desc = "Virtual mask for L1 cache load miss replays", .bit = 2, }, {.name = "L2_LD_MISS", .desc = "Virtual mask for L2 cache load miss replays", .bit = 3, }, {.name = "DTLB_LD_MISS", .desc = "Virtual mask for DTLB load miss replays", .bit = 4, }, {.name = "DTLB_ST_MISS", .desc = "Virtual mask for DTLB store miss replays", .bit = 5, }, {.name = "DTLB_ALL_MISS", .desc = "Virtual mask for all DTLB miss replays", .bit = 6, }, {.name = "BR_MSP", .desc = "Virtual mask for tagged mispredicted branch replays", .bit = 7, }, {.name = "MOB_LD_REPLAY", .desc = "Virtual mask for MOB load replays", .bit = 8, }, {.name = "SP_LD_RET", .desc = "Virtual mask for split load replays. Use with load_port_replay event", .bit = 9, }, {.name = "SP_ST_RET", .desc = "Virtual mask for split store replays. Use with store_port_replay event", .bit = 10, }, }, }, /* 38 */ {.name = "instr_retired", .desc = "Number of instructions retired during a clock cycle", .event_select = 0x2, .escr_select = 0x4, .allowed_escrs = { 20, 42 }, .perf_code = P4_EVENT_INSTR_RETIRED, .event_masks = { {.name = "NBOGUSNTAG", .desc = "Non-bogus instructions that are not tagged", .bit = 0, }, {.name = "NBOGUSTAG", .desc = "Non-bogus instructions that are tagged", .bit = 1, }, {.name = "BOGUSNTAG", .desc = "Bogus instructions that are not tagged", .bit = 2, }, {.name = "BOGUSTAG", .desc = "Bogus instructions that are tagged", .bit = 3, }, }, }, /* 39 */ {.name = "uops_retired", .desc = "Number of uops retired during a clock cycle", .event_select = 0x1, .escr_select = 0x4, .allowed_escrs = { 20, 42 }, .perf_code = P4_EVENT_UOPS_RETIRED, .event_masks = { {.name = "NBOGUS", .desc = "The marked uops are not bogus", .bit = 0, }, {.name = "BOGUS", .desc = "The marked uops are bogus", .bit = 1, }, }, }, /* 40 */ {.name = "uops_type", .desc = "This event is used in conjunction with with the front-end " "mechanism to tag load and store uops", .event_select = 0x2, .escr_select = 0x2, .allowed_escrs = { 18, 41 }, .perf_code = P4_EVENT_UOP_TYPE, .event_masks = { {.name = "TAGLOADS", .desc = "The uop is a load operation", .bit = 1, }, {.name = "TAGSTORES", .desc = "The uop is a store operation", .bit = 2, }, }, }, /* 41 */ {.name = "branch_retired", .desc = "Number of retirements of a branch", .event_select = 0x6, .escr_select = 0x5, .allowed_escrs = { 21, 43 }, .perf_code = P4_EVENT_BRANCH_RETIRED, .event_masks = { {.name = "MMNP", .desc = "Branch not-taken predicted", .bit = 0, }, {.name = "MMNM", .desc = "Branch not-taken mispredicted", .bit = 1, }, {.name = "MMTP", .desc = "Branch taken predicted", .bit = 2, }, {.name = "MMTM", .desc = "Branch taken mispredicted", .bit = 3, }, }, }, /* 42 */ {.name = "mispred_branch_retired", .desc = "Number of retirements of mispredicted " "IA-32 branch instructions", .event_select = 0x3, .escr_select = 0x4, .allowed_escrs = { 20, 42 }, .perf_code = P4_EVENT_MISPRED_BRANCH_RETIRED, .event_masks = { {.name = "BOGUS", .desc = "The retired instruction is not bogus", .bit = 0, .flags = NETBURST_FL_DFL, }, }, }, /* 43 */ {.name = "x87_assist", .desc = "Number of retirements of x87 instructions that required " "special handling", .event_select = 0x3, .escr_select = 0x5, .allowed_escrs = { 21, 43 }, .perf_code = P4_EVENT_X87_ASSIST, .event_masks = { {.name = "FPSU", .desc = "Handle FP stack underflow", .bit = 0, }, {.name = "FPSO", .desc = "Handle FP stack overflow", .bit = 1, }, {.name = "POAO", .desc = "Handle x87 output overflow", .bit = 2, }, {.name = "POAU", .desc = "Handle x87 output underflow", .bit = 3, }, {.name = "PREA", .desc = "Handle x87 input assist", .bit = 4, }, }, }, /* 44 */ {.name = "machine_clear", .desc = "Number of occurrences when the entire " "pipeline of the machine is cleared", .event_select = 0x2, .escr_select = 0x5, .allowed_escrs = { 21, 43 }, .perf_code = P4_EVENT_MACHINE_CLEAR, .event_masks = { {.name = "CLEAR", .desc = "Counts for a portion of the many cycles while the " "machine is cleared for any cause. Use edge-" "triggering for this bit only to get a count of " "occurrences versus a duration", .bit = 0, }, {.name = "MOCLEAR", .desc = "Increments each time the machine is cleared due to " "memory ordering issues", .bit = 2, }, {.name = "SMCLEAR", .desc = "Increments each time the machine is cleared due to " "self-modifying code issues", .bit = 6, }, }, }, /* 45 */ {.name = "instr_completed", .desc = "Instructions that have completed and " "retired during a clock cycle (models 3, 4, 6 only)", .event_select = 0x7, .escr_select = 0x4, .allowed_escrs = { 21, 42 }, .perf_code = P4_EVENT_INSTR_COMPLETED, .event_masks = { {.name = "NBOGUS", .desc = "Non-bogus instructions", .bit = 0, }, {.name = "BOGUS", .desc = "Bogus instructions", .bit = 1, }, }, }, }; #define PME_REPLAY_EVENT 37 #define NETBURST_EVENT_COUNT (sizeof(netburst_events)/sizeof(netburst_entry_t)) #endif libpfm-4.9.0/lib/events/powerpc_events.h0000664000175000017500000000225513223402656020110 0ustar eranianeranian/* * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * * powerpc_events.h */ #ifndef _POWERPC_EVENTS_H_ #define _POWERPC_EVENTS_H_ #define PME_INSTR_COMPLETED 1 #endif libpfm-4.9.0/lib/events/amd64_events_fam12h.h0000664000175000017500000014173713223402656020513 0ustar eranianeranian/* * Copyright (c) 2011 University of Tennessee * Contributed by Vince Weaver * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * PMU: amd64_fam12h (AMD64 Fam12h) */ static const amd64_umask_t amd64_fam12h_dispatched_fpu[]={ { .uname = "OPS_ADD", .udesc = "Add pipe ops excluding load ops and SSE move ops", .ucode = 0x1, }, { .uname = "OPS_MULTIPLY", .udesc = "Multiply pipe ops excluding load ops and SSE move ops", .ucode = 0x2, }, { .uname = "OPS_STORE", .udesc = "Store pipe ops excluding load ops and SSE move ops", .ucode = 0x4, }, { .uname = "OPS_ADD_PIPE_LOAD_OPS", .udesc = "Add pipe load ops and SSE move ops", .ucode = 0x8, }, { .uname = "OPS_MULTIPLY_PIPE_LOAD_OPS", .udesc = "Multiply pipe load ops and SSE move ops", .ucode = 0x10, }, { .uname = "OPS_STORE_PIPE_LOAD_OPS", .udesc = "Store pipe load ops and SSE move ops", .ucode = 0x20, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam12h_retired_sse_operations[]={ { .uname = "SINGLE_ADD_SUB_OPS", .udesc = "Single precision add/subtract ops", .ucode = 0x1, }, { .uname = "SINGLE_MUL_OPS", .udesc = "Single precision multiply ops", .ucode = 0x2, }, { .uname = "SINGLE_DIV_OPS", .udesc = "Single precision divide/square root ops", .ucode = 0x4, }, { .uname = "DOUBLE_ADD_SUB_OPS", .udesc = "Double precision add/subtract ops", .ucode = 0x8, }, { .uname = "DOUBLE_MUL_OPS", .udesc = "Double precision multiply ops", .ucode = 0x10, }, { .uname = "DOUBLE_DIV_OPS", .udesc = "Double precision divide/square root ops", .ucode = 0x20, }, { .uname = "OP_TYPE", .udesc = "Op type: 0=uops. 1=FLOPS", .ucode = 0x40, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x7f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam12h_retired_move_ops[]={ { .uname = "LOW_QW_MOVE_UOPS", .udesc = "Merging low quadword move uops", .ucode = 0x1, }, { .uname = "HIGH_QW_MOVE_UOPS", .udesc = "Merging high quadword move uops", .ucode = 0x2, }, { .uname = "ALL_OTHER_MERGING_MOVE_UOPS", .udesc = "All other merging move uops", .ucode = 0x4, }, { .uname = "ALL_OTHER_MOVE_UOPS", .udesc = "All other move uops", .ucode = 0x8, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xf, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam12h_retired_serializing_ops[]={ { .uname = "SSE_BOTTOM_EXECUTING_UOPS", .udesc = "SSE bottom-executing uops retired", .ucode = 0x1, }, { .uname = "SSE_BOTTOM_SERIALIZING_UOPS", .udesc = "SSE bottom-serializing uops retired", .ucode = 0x2, }, { .uname = "X87_BOTTOM_EXECUTING_UOPS", .udesc = "X87 bottom-executing uops retired", .ucode = 0x4, }, { .uname = "X87_BOTTOM_SERIALIZING_UOPS", .udesc = "X87 bottom-serializing uops retired", .ucode = 0x8, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xf, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam12h_fp_scheduler_cycles[]={ { .uname = "BOTTOM_EXECUTE_CYCLES", .udesc = "Number of cycles a bottom-execute uop is in the FP scheduler", .ucode = 0x1, }, { .uname = "BOTTOM_SERIALIZING_CYCLES", .udesc = "Number of cycles a bottom-serializing uop is in the FP scheduler", .ucode = 0x2, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam12h_segment_register_loads[]={ { .uname = "ES", .udesc = "ES", .ucode = 0x1, }, { .uname = "CS", .udesc = "CS", .ucode = 0x2, }, { .uname = "SS", .udesc = "SS", .ucode = 0x4, }, { .uname = "DS", .udesc = "DS", .ucode = 0x8, }, { .uname = "FS", .udesc = "FS", .ucode = 0x10, }, { .uname = "GS", .udesc = "GS", .ucode = 0x20, }, { .uname = "HS", .udesc = "HS", .ucode = 0x40, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x7f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam12h_locked_ops[]={ { .uname = "EXECUTED", .udesc = "The number of locked instructions executed", .ucode = 0x1, }, { .uname = "CYCLES_SPECULATIVE_PHASE", .udesc = "The number of cycles spent in speculative phase", .ucode = 0x2, }, { .uname = "CYCLES_NON_SPECULATIVE_PHASE", .udesc = "The number of cycles spent in non-speculative phase (including cache miss penalty)", .ucode = 0x4, }, { .uname = "CYCLES_WAITING", .udesc = "The number of cycles waiting for a cache hit (cache miss penalty).", .ucode = 0x8, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xf, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam12h_cancelled_store_to_load_forward_operations[]={ { .uname = "ADDRESS_MISMATCHES", .udesc = "Address mismatches (starting byte not the same).", .ucode = 0x1, }, { .uname = "STORE_IS_SMALLER_THAN_LOAD", .udesc = "Store is smaller than load.", .ucode = 0x2, }, { .uname = "MISALIGNED", .udesc = "Misaligned.", .ucode = 0x4, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x7, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam12h_data_cache_refills[]={ { .uname = "SYSTEM", .udesc = "Refill from the Northbridge", .ucode = 0x1, }, { .uname = "L2_SHARED", .udesc = "Shared-state line from L2", .ucode = 0x2, }, { .uname = "L2_EXCLUSIVE", .udesc = "Exclusive-state line from L2", .ucode = 0x4, }, { .uname = "L2_OWNED", .udesc = "Owned-state line from L2", .ucode = 0x8, }, { .uname = "L2_MODIFIED", .udesc = "Modified-state line from L2", .ucode = 0x10, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x1f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam12h_data_cache_refills_from_northbridge[]={ { .uname = "INVALID", .udesc = "Invalid", .ucode = 0x1, }, { .uname = "SHARED", .udesc = "Shared", .ucode = 0x2, }, { .uname = "EXCLUSIVE", .udesc = "Exclusive", .ucode = 0x4, }, { .uname = "OWNED", .udesc = "Owned", .ucode = 0x8, }, { .uname = "MODIFIED", .udesc = "Modified", .ucode = 0x10, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x1f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam12h_data_cache_lines_evicted[]={ { .uname = "INVALID", .udesc = "Invalid", .ucode = 0x1, }, { .uname = "SHARED", .udesc = "Shared", .ucode = 0x2, }, { .uname = "EXCLUSIVE", .udesc = "Exclusive", .ucode = 0x4, }, { .uname = "OWNED", .udesc = "Owned", .ucode = 0x8, }, { .uname = "MODIFIED", .udesc = "Modified", .ucode = 0x10, }, { .uname = "BY_PREFETCHNTA", .udesc = "Cache line evicted was brought into the cache with by a PrefetchNTA instruction.", .ucode = 0x20, }, { .uname = "NOT_BY_PREFETCHNTA", .udesc = "Cache line evicted was not brought into the cache with by a PrefetchNTA instruction.", .ucode = 0x40, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x7f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam12h_l1_dtlb_miss_and_l2_dtlb_hit[]={ { .uname = "L2_4K_TLB_HIT", .udesc = "L2 4K TLB hit", .ucode = 0x1, }, { .uname = "L2_2M_TLB_HIT", .udesc = "L2 2M TLB hit", .ucode = 0x2, }, { .uname = "L2_1G_TLB_HIT", .udesc = "L2 1G TLB hit", .ucode = 0x4, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x7, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam12h_l1_dtlb_and_l2_dtlb_miss[]={ { .uname = "4K_TLB_RELOAD", .udesc = "4K TLB reload", .ucode = 0x1, }, { .uname = "2M_TLB_RELOAD", .udesc = "2M TLB reload", .ucode = 0x2, }, { .uname = "1G_TLB_RELOAD", .udesc = "1G TLB reload", .ucode = 0x4, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x7, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam12h_prefetch_instructions_dispatched[]={ { .uname = "LOAD", .udesc = "Load (Prefetch, PrefetchT0/T1/T2)", .ucode = 0x1, }, { .uname = "STORE", .udesc = "Store (PrefetchW)", .ucode = 0x2, }, { .uname = "NTA", .udesc = "NTA (PrefetchNTA)", .ucode = 0x4, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x7, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam12h_dcache_misses_by_locked_instructions[]={ { .uname = "DATA_CACHE_MISSES_BY_LOCKED_INSTRUCTIONS", .udesc = "Data cache misses by locked instructions", .ucode = 0x2, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x2, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam12h_l1_dtlb_hit[]={ { .uname = "L1_4K_TLB_HIT", .udesc = "L1 4K TLB hit", .ucode = 0x1, }, { .uname = "L1_2M_TLB_HIT", .udesc = "L1 2M TLB hit", .ucode = 0x2, }, { .uname = "L1_1G_TLB_HIT", .udesc = "L1 1G TLB hit", .ucode = 0x4, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x7, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam12h_ineffective_sw_prefetches[]={ { .uname = "SW_PREFETCH_HIT_IN_L1", .udesc = "Software prefetch hit in the L1.", .ucode = 0x1, }, { .uname = "SW_PREFETCH_HIT_IN_L2", .udesc = "Software prefetch hit in L2.", .ucode = 0x8, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x9, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam12h_memory_requests[]={ { .uname = "NON_CACHEABLE", .udesc = "Requests to non-cacheable (UC) memory", .ucode = 0x1, }, { .uname = "WRITE_COMBINING", .udesc = "Requests to write-combining (WC) memory or WC buffer flushes to WB memory", .ucode = 0x2, }, { .uname = "CACHE_DISABLED", .udesc = "Requests to cache-disabled (CD) memory", .ucode = 0x4, }, { .uname = "STREAMING_STORE", .udesc = "Streaming store (SS) requests", .ucode = 0x80, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x87, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam12h_data_prefetches[]={ { .uname = "CANCELLED", .udesc = "Cancelled prefetches", .ucode = 0x1, }, { .uname = "ATTEMPTED", .udesc = "Prefetch attempts", .ucode = 0x2, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam12h_northbridge_read_responses[]={ { .uname = "EXCLUSIVE", .udesc = "Exclusive", .ucode = 0x1, }, { .uname = "MODIFIED", .udesc = "Modified", .ucode = 0x2, }, { .uname = "SHARED", .udesc = "Shared", .ucode = 0x4, }, { .uname = "OWNED", .udesc = "Owned", .ucode = 0x8, }, { .uname = "DATA_ERROR", .udesc = "Data Error", .ucode = 0x10, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x1f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam12h_octwords_written_to_system[]={ { .uname = "OCTWORD_WRITE_TRANSFER", .udesc = "Octword write transfer", .ucode = 0x1, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x1, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam12h_requests_to_l2[]={ { .uname = "INSTRUCTIONS", .udesc = "IC fill", .ucode = 0x1, }, { .uname = "DATA", .udesc = "DC fill", .ucode = 0x2, }, { .uname = "TLB_WALK", .udesc = "TLB fill (page table walks)", .ucode = 0x4, }, { .uname = "SNOOP", .udesc = "Tag snoop request", .ucode = 0x8, }, { .uname = "CANCELLED", .udesc = "Cancelled request", .ucode = 0x10, }, { .uname = "HW_PREFETCH_FROM_DC", .udesc = "Hardware prefetch from DC", .ucode = 0x20, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam12h_l2_cache_miss[]={ { .uname = "INSTRUCTIONS", .udesc = "IC fill", .ucode = 0x1, }, { .uname = "DATA", .udesc = "DC fill (includes possible replays, whereas EventSelect 041h does not)", .ucode = 0x2, }, { .uname = "TLB_WALK", .udesc = "TLB page table walk", .ucode = 0x4, }, { .uname = "HW_PREFETCH_FROM_DC", .udesc = "Hardware prefetch from DC", .ucode = 0x8, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xf, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam12h_l2_fill_writeback[]={ { .uname = "L2_FILLS", .udesc = "L2 fills (victims from L1 caches, TLB page table walks and data prefetches)", .ucode = 0x1, }, { .uname = "L2_WRITEBACKS", .udesc = "L2 Writebacks to system.", .ucode = 0x2, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam12h_l1_itlb_miss_and_l2_itlb_miss[]={ { .uname = "4K_PAGE_FETCHES", .udesc = "Instruction fetches to a 4K page.", .ucode = 0x1, }, { .uname = "2M_PAGE_FETCHES", .udesc = "Instruction fetches to a 2M page.", .ucode = 0x2, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam12h_instruction_cache_lines_invalidated[]={ { .uname = "INVALIDATING_PROBE_NO_IN_FLIGHT", .udesc = "Invalidating probe that did not hit any in-flight instructions.", .ucode = 0x1, }, { .uname = "INVALIDATING_PROBE_ONE_OR_MORE_IN_FLIGHT", .udesc = "Invalidating probe that hit one or more in-flight instructions.", .ucode = 0x2, }, { .uname = "SMC_NO_INFLIGHT", .udesc = "SMC that did not hit any in-flight instructions.", .ucode = 0x4, }, { .uname = "SMC_INFLIGHT", .udesc = "SMC that hit one or more in-flight instructions.", .ucode = 0x8, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xf, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam12h_retired_mmx_and_fp_instructions[]={ { .uname = "X87", .udesc = "X87 instructions", .ucode = 0x1, }, { .uname = "MMX_AND_3DNOW", .udesc = "MMX and 3DNow! instructions", .ucode = 0x2, }, { .uname = "SSE_AND_SSE2", .udesc = "SSE and SSE2 instructions", .ucode = 0x4, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x7, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam12h_interrupt_events[]={ { .uname = "FIXED_AND_LPA", .udesc = "Fixed and LPA", .ucode = 0x1, }, { .uname = "LPA", .udesc = "LPA", .ucode = 0x2, }, { .uname = "SMI", .udesc = "SMI", .ucode = 0x4, }, { .uname = "NMI", .udesc = "NMI", .ucode = 0x8, }, { .uname = "INIT", .udesc = "INIT", .ucode = 0x10, }, { .uname = "STARTUP", .udesc = "STARTUP", .ucode = 0x20, }, { .uname = "INT", .udesc = "INT", .ucode = 0x40, }, { .uname = "EOI", .udesc = "EOI", .ucode = 0x80, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xff, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam12h_sideband_signals[]={ { .uname = "STOPGRANT", .udesc = "STOPGRANT", .ucode = 0x2, }, { .uname = "SHUTDOWN", .udesc = "SHUTDOWN", .ucode = 0x4, }, { .uname = "WBINVD", .udesc = "WBINVD", .ucode = 0x8, }, { .uname = "INVD", .udesc = "INVD", .ucode = 0x10, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x1e, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam12h_fpu_exceptions[]={ { .uname = "X87_RECLASS_MICROFAULTS", .udesc = "X87 reclass microfaults", .ucode = 0x1, }, { .uname = "SSE_RETYPE_MICROFAULTS", .udesc = "SSE retype microfaults", .ucode = 0x2, }, { .uname = "SSE_RECLASS_MICROFAULTS", .udesc = "SSE reclass microfaults", .ucode = 0x4, }, { .uname = "SSE_AND_X87_MICROTRAPS", .udesc = "SSE and x87 microtraps", .ucode = 0x8, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xf, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam12h_dram_accesses_page[]={ { .uname = "DCT0_HIT", .udesc = "DCT0 Page hit", .ucode = 0x1, }, { .uname = "DCT0_MISS", .udesc = "DCT0 Page Miss", .ucode = 0x2, }, { .uname = "DCT0_CONFLICT", .udesc = "DCT0 Page Conflict", .ucode = 0x4, }, { .uname = "DCT1_PAGE_HIT", .udesc = "DCT1 Page hit", .ucode = 0x8, }, { .uname = "DCT1_PAGE_MISS", .udesc = "DCT1 Page Miss", .ucode = 0x10, }, { .uname = "DCT1_PAGE_CONFLICT", .udesc = "DCT1 Page Conflict", .ucode = 0x20, }, { .uname = "WRITE_REQUEST", .udesc = "Write request.", .ucode = 0x40, }, { .uname = "READ_REQUEST", .udesc = "Read request.", .ucode = 0x80, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xff, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam12h_memory_controller_page_table_events[]={ { .uname = "PAGE_TABLE_OVERFLOW", .udesc = "Page Table Overflow", .ucode = 0x1, }, { .uname = "STALE_TABLE_ENTRY_HITS", .udesc = "Number of stale table entry hits. (hit on a page closed too soon).", .ucode = 0x2, }, { .uname = "PAGE_TABLE_IDLE_CYCLE_LIMIT_INCREMENTED", .udesc = "Page table idle cycle limit incremented.", .ucode = 0x4, }, { .uname = "PAGE_TABLE_IDLE_CYCLE_LIMIT_DECREMENTED", .udesc = "Page table idle cycle limit decremented.", .ucode = 0x8, }, { .uname = "PAGE_TABLE_CLOSED_INACTIVITY", .udesc = "Page table is closed due to row inactivity.", .ucode = 0x10, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x1f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam12h_memory_controller_slot_misses[]={ { .uname = "DCT0_RBD", .udesc = "DCT0 RBD.", .ucode = 0x10, }, { .uname = "DCT1_RBD", .udesc = "DCT1 RBD.", .ucode = 0x20, }, { .uname = "DCT0_PREFETCH", .udesc = "DCT0 Prefetch.", .ucode = 0x40, }, { .uname = "DCT1_PREFETCH", .udesc = "DCT1 Prefetch.", .ucode = 0x80, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xf0, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam12h_memory_controller_turnarounds[]={ { .uname = "DCT0_READ_TO_WRITE", .udesc = "DCT0 read-to-write turnaround.", .ucode = 0x1, }, { .uname = "DCT0_WRITE_TO_READ", .udesc = "DCT0 write-to-read turnaround", .ucode = 0x2, }, { .uname = "DCT1_READ_TO_WRITE", .udesc = "DCT1 read-to-write turnaround.", .ucode = 0x8, }, { .uname = "DCT1_WRITE_TO_READ", .udesc = "DCT1 write-to-read turnaround", .ucode = 0x10, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x1b, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam12h_memory_rbd_queue[]={ { .uname = "COUNTER_REACHED", .udesc = "D18F2x[1,0]94[DcqBypassMax] counter reached.", .ucode = 0x4, }, { .uname = "BANK_CLOSED", .udesc = "Bank is closed due to bank conflict with an outstanding request in the RBD queue.", .ucode = 0x8, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xc, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam12h_thermal_status[]={ { .uname = "MEMHOT_L_ASSERTIONS", .udesc = "MEMHOT_L assertions.", .ucode = 0x1, }, { .uname = "HTC_TRANSITIONS", .udesc = "Number of times the HTC transitions from inactive to active.", .ucode = 0x4, }, { .uname = "CLOCKS_HTC_P_STATE_INACTIVE", .udesc = "Number of clocks HTC P-state is inactive.", .ucode = 0x20, }, { .uname = "CLOCKS_HTC_P_STATE_ACTIVE", .udesc = "Number of clocks HTC P-state is active", .ucode = 0x40, }, { .uname = "PROCHOT_L_ASSERTIONS", .udesc = "PROCHOT_L asserted by an external source and the assertion causes a P-state change.", .ucode = 0x80, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xe5, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam12h_cpu_io_requests_to_memory_io[]={ { .uname = "I_O_TO_I_O", .udesc = "IO to IO", .ucode = 0x1, }, { .uname = "I_O_TO_MEM", .udesc = "IO to Mem", .ucode = 0x2, }, { .uname = "CPU_TO_I_O", .udesc = "CPU to IO", .ucode = 0x4, }, { .uname = "CPU_TO_MEM", .udesc = "CPU to Mem", .ucode = 0x8, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x0f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam12h_cache_block[]={ { .uname = "VICTIM_WRITEBACK", .udesc = "Victim Block (Writeback)", .ucode = 0x1, }, { .uname = "DCACHE_LOAD_MISS", .udesc = "Read Block (Dcache load miss refill)", .ucode = 0x4, }, { .uname = "SHARED_ICACHE_REFILL", .udesc = "Read Block Shared (Icache refill)", .ucode = 0x8, }, { .uname = "READ_BLOCK_MODIFIED", .udesc = "Read Block Modified (Dcache store miss refill)", .ucode = 0x10, }, { .uname = "READ_TO_DIRTY", .udesc = "Change-to-Dirty (first store to clean block already in cache)", .ucode = 0x20, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3d, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam12h_sized_commands[]={ { .uname = "NON_POSTED_WRITE_BYTE", .udesc = "Non-Posted SzWr Byte (1-32 bytes) Legacy or mapped IO, typically 1-4 bytes", .ucode = 0x1, }, { .uname = "NON_POSTED_WRITE_DWORD", .udesc = "Non-Posted SzWr DW (1-16 dwords) Legacy or mapped IO, typically 1 DWORD", .ucode = 0x2, }, { .uname = "POSTED_WRITE_BYTE", .udesc = "Posted SzWr Byte (1-32 bytes) Subcache-line DMA writes, size varies; also flushes of partially-filled Write Combining buffer", .ucode = 0x4, }, { .uname = "POSTED_WRITE_DWORD", .udesc = "Posted SzWr DW (1-16 dwords) Block-oriented DMA writes, often cache-line sized; also processor Write Combining buffer flushes", .ucode = 0x8, }, { .uname = "READ_BYTE_4_BYTES", .udesc = "SzRd Byte (4 bytes) Legacy or mapped IO", .ucode = 0x10, }, { .uname = "READ_DWORD_1_16_DWORDS", .udesc = "SzRd DW (1-16 dwords) Block-oriented DMA reads, typically cache-line size", .ucode = 0x20, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam12h_probe[]={ { .uname = "MISS", .udesc = "Probe miss", .ucode = 0x1, }, { .uname = "HIT_CLEAN", .udesc = "Probe hit clean", .ucode = 0x2, }, { .uname = "HIT_DIRTY_NO_MEMORY_CANCEL", .udesc = "Probe hit dirty without memory cancel (probed by Sized Write or Change2Dirty)", .ucode = 0x4, }, { .uname = "HIT_DIRTY_WITH_MEMORY_CANCEL", .udesc = "Probe hit dirty with memory cancel (probed by DMA read or cache refill request)", .ucode = 0x8, }, { .uname = "UPSTREAM_HIGH_PRIORITY_READS", .udesc = "Upstream high priority reads.", .ucode = 0x10, }, { .uname = "UPSTREAM_LOW_PRIORITY_READS", .udesc = "Upstream low priority reads.", .ucode = 0x20, }, { .uname = "UPSTREAM_LOW_PRIORITY_WRITES", .udesc = "Upstream low priority writes.", .ucode = 0x80, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xbf, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam12h_dev[]={ { .uname = "DEV_HIT", .udesc = "DEV hit", .ucode = 0x10, }, { .uname = "DEV_MISS", .udesc = "DEV miss", .ucode = 0x20, }, { .uname = "DEV_ERROR", .udesc = "DEV error", .ucode = 0x40, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x70, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam12h_memory_controller_requests[]={ { .uname = "32_BYTES_WRITES", .udesc = "32 Bytes Sized Writes", .ucode = 0x8, }, { .uname = "64_BYTES_WRITES", .udesc = "64 Bytes Sized Writes", .ucode = 0x10, }, { .uname = "32_BYTES_READS", .udesc = "32 Bytes Sized Reads", .ucode = 0x20, }, { .uname = "64_BYTES_READS", .udesc = "64 Byte Sized Reads", .ucode = 0x40, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x78, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam12h_page_size_mismatches[]={ { .uname = "GUEST_LARGER", .udesc = "Guest page size is larger than the host page size.", .ucode = 0x1, }, { .uname = "MTRR_MISMATCH", .udesc = "MTRR mismatch.", .ucode = 0x2, }, { .uname = "HOST_LARGER", .udesc = "Host page size is larger than the guest page size.", .ucode = 0x4, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x7, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam12h_retired_x87_ops[]={ { .uname = "ADD_SUB_OPS", .udesc = "Add/subtract ops", .ucode = 0x1, }, { .uname = "MUL_OPS", .udesc = "Multiply ops", .ucode = 0x2, }, { .uname = "DIV_OPS", .udesc = "Divide ops", .ucode = 0x4, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x7, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_entry_t amd64_fam12h_pe[]={ { .name = "DISPATCHED_FPU", .desc = "Dispatched FPU Operations", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x0, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_dispatched_fpu), .ngrp = 1, .umasks = amd64_fam12h_dispatched_fpu, }, { .name = "CYCLES_NO_FPU_OPS_RETIRED", .desc = "Cycles in which the FPU is Empty", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x1, }, { .name = "DISPATCHED_FPU_OPS_FAST_FLAG", .desc = "Dispatched Fast Flag FPU Operations", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x2, }, { .name = "RETIRED_SSE_OPERATIONS", .desc = "Retired SSE Operations", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x3, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_retired_sse_operations), .ngrp = 1, .umasks = amd64_fam12h_retired_sse_operations, }, { .name = "RETIRED_MOVE_OPS", .desc = "Retired Move Ops", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x4, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_retired_move_ops), .ngrp = 1, .umasks = amd64_fam12h_retired_move_ops, }, { .name = "RETIRED_SERIALIZING_OPS", .desc = "Retired Serializing Ops", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x5, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_retired_serializing_ops), .ngrp = 1, .umasks = amd64_fam12h_retired_serializing_ops, }, { .name = "FP_SCHEDULER_CYCLES", .desc = "Number of Cycles that a Serializing uop is in the FP Scheduler", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x6, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_fp_scheduler_cycles), .ngrp = 1, .umasks = amd64_fam12h_fp_scheduler_cycles, }, { .name = "SEGMENT_REGISTER_LOADS", .desc = "Segment Register Loads", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x20, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_segment_register_loads), .ngrp = 1, .umasks = amd64_fam12h_segment_register_loads, }, { .name = "PIPELINE_RESTART_DUE_TO_SELF_MODIFYING_CODE", .desc = "Pipeline Restart Due to Self-Modifying Code", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x21, }, { .name = "PIPELINE_RESTART_DUE_TO_PROBE_HIT", .desc = "Pipeline Restart Due to Probe Hit", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x22, }, { .name = "LS_BUFFER_2_FULL_CYCLES", .desc = "LS Buffer 2 Full", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x23, }, { .name = "LOCKED_OPS", .desc = "Locked Operations", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x24, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_locked_ops), .ngrp = 1, .umasks = amd64_fam12h_locked_ops, }, { .name = "RETIRED_CLFLUSH_INSTRUCTIONS", .desc = "Retired CLFLUSH Instructions", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x26, }, { .name = "RETIRED_CPUID_INSTRUCTIONS", .desc = "Retired CPUID Instructions", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x27, }, { .name = "CANCELLED_STORE_TO_LOAD_FORWARD_OPERATIONS", .desc = "Cancelled Store to Load Forward Operations", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x2a, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_cancelled_store_to_load_forward_operations), .ngrp = 1, .umasks = amd64_fam12h_cancelled_store_to_load_forward_operations, }, { .name = "SMIS_RECEIVED", .desc = "SMIs Received", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x2b, }, { .name = "DATA_CACHE_ACCESSES", .desc = "Data Cache Accesses", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x40, }, { .name = "DATA_CACHE_MISSES", .desc = "Data Cache Misses", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x41, }, { .name = "DATA_CACHE_REFILLS", .desc = "Data Cache Refills from L2 or Northbridge", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x42, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_data_cache_refills), .ngrp = 1, .umasks = amd64_fam12h_data_cache_refills, }, { .name = "DATA_CACHE_REFILLS_FROM_SYSTEM", .desc = "Data Cache Refills from the Northbridge", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x43, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_data_cache_refills_from_northbridge), .ngrp = 1, .umasks = amd64_fam12h_data_cache_refills_from_northbridge, }, { .name = "DATA_CACHE_LINES_EVICTED", .desc = "Data Cache Lines Evicted", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x44, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_data_cache_lines_evicted), .ngrp = 1, .umasks = amd64_fam12h_data_cache_lines_evicted, }, { .name = "L1_DTLB_MISS_AND_L2_DTLB_HIT", .desc = "L1 DTLB Miss and L2 DTLB Hit", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x45, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_l1_dtlb_miss_and_l2_dtlb_hit), .ngrp = 1, .umasks = amd64_fam12h_l1_dtlb_miss_and_l2_dtlb_hit, }, { .name = "L1_DTLB_AND_L2_DTLB_MISS", .desc = "L1 DTLB and L2 DTLB Miss", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x46, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_l1_dtlb_and_l2_dtlb_miss), .ngrp = 1, .umasks = amd64_fam12h_l1_dtlb_and_l2_dtlb_miss, }, { .name = "MISALIGNED_ACCESSES", .desc = "Misaligned Accesses", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x47, }, { .name = "MICROARCHITECTURAL_LATE_CANCEL_OF_AN_ACCESS", .desc = "Microarchitectural Late Cancel of an Access", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x48, }, { .name = "MICROARCHITECTURAL_EARLY_CANCEL_OF_AN_ACCESS", .desc = "Microarchitectural Early Cancel of an Access", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x49, }, { .name = "PREFETCH_INSTRUCTIONS_DISPATCHED", .desc = "Prefetch Instructions Dispatched", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x4b, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_prefetch_instructions_dispatched), .ngrp = 1, .umasks = amd64_fam12h_prefetch_instructions_dispatched, }, { .name = "DCACHE_MISSES_BY_LOCKED_INSTRUCTIONS", .desc = "DCACHE Misses by Locked Instructions", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x4c, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_dcache_misses_by_locked_instructions), .ngrp = 1, .umasks = amd64_fam12h_dcache_misses_by_locked_instructions, }, { .name = "L1_DTLB_HIT", .desc = "L1 DTLB Hit", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x4d, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_l1_dtlb_hit), .ngrp = 1, .umasks = amd64_fam12h_l1_dtlb_hit, }, { .name = "INEFFECTIVE_SW_PREFETCHES", .desc = "Ineffective Software Prefetches", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x52, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_ineffective_sw_prefetches), .ngrp = 1, .umasks = amd64_fam12h_ineffective_sw_prefetches, }, { .name = "GLOBAL_TLB_FLUSHES", .desc = "Global TLB Flushes", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x54, }, { .name = "MEMORY_REQUESTS", .desc = "Memory Requests by Type", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x65, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_memory_requests), .ngrp = 1, .umasks = amd64_fam12h_memory_requests, }, { .name = "DATA_PREFETCHES", .desc = "Data Prefetcher", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x67, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_data_prefetches), .ngrp = 1, .umasks = amd64_fam12h_data_prefetches, }, { .name = "NORTHBRIDGE_READ_RESPONSES", .desc = "Northbridge Read Responses by Coherency State", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x6c, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_northbridge_read_responses), .ngrp = 1, .umasks = amd64_fam12h_northbridge_read_responses, }, { .name = "OCTWORDS_WRITTEN_TO_SYSTEM", .desc = "Octwords Written to System", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x6d, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_octwords_written_to_system), .ngrp = 1, .umasks = amd64_fam12h_octwords_written_to_system, }, { .name = "CPU_CLK_UNHALTED", .desc = "CPU Clocks not Halted", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x76, }, { .name = "REQUESTS_TO_L2", .desc = "Requests to L2 Cache", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x7d, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_requests_to_l2), .ngrp = 1, .umasks = amd64_fam12h_requests_to_l2, }, { .name = "L2_CACHE_MISS", .desc = "L2 Cache Misses", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x7e, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_l2_cache_miss), .ngrp = 1, .umasks = amd64_fam12h_l2_cache_miss, }, { .name = "L2_FILL_WRITEBACK", .desc = "L2 Fill/Writeback", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x7f, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_l2_fill_writeback), .ngrp = 1, .umasks = amd64_fam12h_l2_fill_writeback, }, { .name = "PAGE_SIZE_MISMATCHES", .desc = "Page Size Mismatches", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x165, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_page_size_mismatches), .ngrp = 1, .umasks = amd64_fam12h_page_size_mismatches, }, { .name = "INSTRUCTION_CACHE_FETCHES", .desc = "Instruction Cache Fetches", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x80, }, { .name = "INSTRUCTION_CACHE_MISSES", .desc = "Instruction Cache Misses", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x81, }, { .name = "INSTRUCTION_CACHE_REFILLS_FROM_L2", .desc = "Instruction Cache Refills from L2", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x82, }, { .name = "INSTRUCTION_CACHE_REFILLS_FROM_SYSTEM", .desc = "Instruction Cache Refills from System", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x83, }, { .name = "L1_ITLB_MISS_AND_L2_ITLB_HIT", .desc = "L1 ITLB Miss and L2 ITLB Hit", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x84, }, { .name = "L1_ITLB_MISS_AND_L2_ITLB_MISS", .desc = "L1 ITLB Miss and L2 ITLB Miss", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x85, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_l1_itlb_miss_and_l2_itlb_miss), .ngrp = 1, .umasks = amd64_fam12h_l1_itlb_miss_and_l2_itlb_miss, }, { .name = "PIPELINE_RESTART_DUE_TO_INSTRUCTION_STREAM_PROBE", .desc = "Pipeline Restart Due to Instruction Stream Probe", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x86, }, { .name = "INSTRUCTION_FETCH_STALL", .desc = "Instruction Fetch Stall", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x87, }, { .name = "RETURN_STACK_HITS", .desc = "Return Stack Hits", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x88, }, { .name = "RETURN_STACK_OVERFLOWS", .desc = "Return Stack Overflows", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x89, }, { .name = "INSTRUCTION_CACHE_VICTIMS", .desc = "Instruction Cache Victims", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x8b, }, { .name = "INSTRUCTION_CACHE_LINES_INVALIDATED", .desc = "Instruction Cache Lines Invalidated", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x8c, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_instruction_cache_lines_invalidated), .ngrp = 1, .umasks = amd64_fam12h_instruction_cache_lines_invalidated, }, { .name = "ITLB_RELOADS", .desc = "ITLB Reloads", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x99, }, { .name = "ITLB_RELOADS_ABORTED", .desc = "ITLB Reloads Aborted", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x9a, }, { .name = "RETIRED_INSTRUCTIONS", .desc = "Retired Instructions", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xc0, }, { .name = "RETIRED_UOPS", .desc = "Retired uops", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xc1, }, { .name = "RETIRED_BRANCH_INSTRUCTIONS", .desc = "Retired Branch Instructions", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xc2, }, { .name = "RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS", .desc = "Retired Mispredicted Branch Instructions", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xc3, }, { .name = "RETIRED_TAKEN_BRANCH_INSTRUCTIONS", .desc = "Retired Taken Branch Instructions", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xc4, }, { .name = "RETIRED_TAKEN_BRANCH_INSTRUCTIONS_MISPREDICTED", .desc = "Retired Taken Branch Instructions Mispredicted", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xc5, }, { .name = "RETIRED_FAR_CONTROL_TRANSFERS", .desc = "Retired Far Control Transfers", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xc6, }, { .name = "RETIRED_BRANCH_RESYNCS", .desc = "Retired Branch Resyncs", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xc7, }, { .name = "RETIRED_NEAR_RETURNS", .desc = "Retired Near Returns", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xc8, }, { .name = "RETIRED_NEAR_RETURNS_MISPREDICTED", .desc = "Retired Near Returns Mispredicted", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xc9, }, { .name = "RETIRED_INDIRECT_BRANCHES_MISPREDICTED", .desc = "Retired Indirect Branches Mispredicted", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xca, }, { .name = "RETIRED_MMX_AND_FP_INSTRUCTIONS", .desc = "Retired MMX/FP Instructions", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xcb, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_retired_mmx_and_fp_instructions), .ngrp = 1, .umasks = amd64_fam12h_retired_mmx_and_fp_instructions, }, { .name = "INTERRUPTS_MASKED_CYCLES", .desc = "Interrupts-Masked Cycles", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xcd, }, { .name = "INTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDING", .desc = "Interrupts-Masked Cycles with Interrupt Pending", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xce, }, { .name = "INTERRUPTS_TAKEN", .desc = "Interrupts Taken", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xcf, }, { .name = "DECODER_EMPTY", .desc = "Decoder Empty", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xd0, }, { .name = "DISPATCH_STALLS", .desc = "Dispatch Stalls", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xd1, }, { .name = "DISPATCH_STALL_FOR_BRANCH_ABORT", .desc = "Dispatch Stall for Branch Abort to Retire", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xd2, }, { .name = "DISPATCH_STALL_FOR_SERIALIZATION", .desc = "Dispatch Stall for Serialization", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xd3, }, { .name = "DISPATCH_STALL_FOR_SEGMENT_LOAD", .desc = "Dispatch Stall for Segment Load", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xd4, }, { .name = "DISPATCH_STALL_FOR_REORDER_BUFFER_FULL", .desc = "Dispatch Stall for Reorder Buffer Full", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xd5, }, { .name = "DISPATCH_STALL_FOR_RESERVATION_STATION_FULL", .desc = "Dispatch Stall for Reservation Station Full", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xd6, }, { .name = "DISPATCH_STALL_FOR_FPU_FULL", .desc = "Dispatch Stall for FPU Full", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xd7, }, { .name = "DISPATCH_STALL_FOR_LS_FULL", .desc = "Dispatch Stall for LS Full", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xd8, }, { .name = "DISPATCH_STALL_WAITING_FOR_ALL_QUIET", .desc = "Dispatch Stall Waiting for All Quiet", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xd9, }, { .name = "DISPATCH_STALL_FOR_FAR_TRANSFER_OR_RSYNC", .desc = "Dispatch Stall for Far Transfer or Resync to Retire", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xda, }, { .name = "FPU_EXCEPTIONS", .desc = "FPU Exceptions", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xdb, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_fpu_exceptions), .ngrp = 1, .umasks = amd64_fam12h_fpu_exceptions, }, { .name = "DR0_BREAKPOINT_MATCHES", .desc = "DR0 Breakpoint Matches", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xdc, }, { .name = "DR1_BREAKPOINT_MATCHES", .desc = "DR1 Breakpoint Matches", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xdd, }, { .name = "DR2_BREAKPOINT_MATCHES", .desc = "DR2 Breakpoint Matches", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xde, }, { .name = "DR3_BREAKPOINT_MATCHES", .desc = "DR3 Breakpoint Matches", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xdf, }, { .name = "RETIRED_X87_OPS", .desc = "Retired x87 Floating Point Operations", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x1c0, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_retired_x87_ops), .ngrp = 1, .umasks = amd64_fam12h_retired_x87_ops, }, { .name = "LFENCE_INST_RETIRED", .desc = "LFENCE Instructions Retired", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x1d3, }, { .name = "SFENCE_INST_RETIRED", .desc = "SFENCE Instructions Retired", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x1d4, }, { .name = "MFENCE_INST_RETIRED", .desc = "MFENCE Instructions Retired", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x1d5, }, { .name = "DRAM_ACCESSES_PAGE", .desc = "DRAM Accesses", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xe0, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_dram_accesses_page), .ngrp = 1, .umasks = amd64_fam12h_dram_accesses_page, }, { .name = "MEMORY_CONTROLLER_0_PAGE", .desc = "DRAM Controller 0 Page Table Events", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xe1, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_memory_controller_page_table_events), .ngrp = 1, .umasks = amd64_fam12h_memory_controller_page_table_events, }, { .name = "MEMORY_CONTROLLER_SLOT_MISSES", .desc = "Memory Controller DRAM Command Slots Missed", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xe2, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_memory_controller_slot_misses), .ngrp = 1, .umasks = amd64_fam12h_memory_controller_slot_misses, }, { .name = "MEMORY_CONTROLLER_TURNAROUNDS", .desc = "Memory Controller Turnarounds", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xe3, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_memory_controller_turnarounds), .ngrp = 1, .umasks = amd64_fam12h_memory_controller_turnarounds, }, { .name = "MEMORY_CONTROLLER_RBD_QUEUE", .desc = "Memory Controller RBD Queue Events", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xe4, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_memory_rbd_queue), .ngrp = 1, .umasks = amd64_fam12h_memory_rbd_queue, }, { .name = "MEMORY_CONTROLLER_1_PAGE", .desc = "DRAM Controller 1 Page Table Events", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xe5, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_memory_controller_page_table_events), .ngrp = 1, .umasks = amd64_fam12h_memory_controller_page_table_events, }, { .name = "THERMAL_STATUS", .desc = "Thermal Status", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xe8, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_thermal_status), .ngrp = 1, .umasks = amd64_fam12h_thermal_status, }, { .name = "CPU_IO_REQUESTS_TO_MEMORY_IO", .desc = "CPU/IO Requests to Memory/IO", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xe9, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_cpu_io_requests_to_memory_io), .ngrp = 1, .umasks = amd64_fam12h_cpu_io_requests_to_memory_io, }, { .name = "CACHE_BLOCK", .desc = "Cache Block Commands", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xea, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_cache_block), .ngrp = 1, .umasks = amd64_fam12h_cache_block, }, { .name = "SIZED_COMMANDS", .desc = "Sized Commands", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xeb, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_sized_commands), .ngrp = 1, .umasks = amd64_fam12h_sized_commands, }, { .name = "PROBE", .desc = "Probe Responses and Upstream Requests", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xec, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_probe), .ngrp = 1, .umasks = amd64_fam12h_probe, }, { .name = "DEV", .desc = "DEV Events", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xee, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_dev), .ngrp = 1, .umasks = amd64_fam12h_dev, }, { .name = "MEMORY_CONTROLLER_REQUESTS", .desc = "Memory Controller Requests", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x1f0, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_memory_controller_requests), .ngrp = 1, .umasks = amd64_fam12h_memory_controller_requests, }, { .name = "SIDEBAND_SIGNALS", .desc = "Sideband Signals and Special Cycles", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x1e9, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_sideband_signals), .ngrp = 1, .umasks = amd64_fam12h_sideband_signals, }, { .name = "INTERRUPT_EVENTS", .desc = "Interrupt Events", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x1ea, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_interrupt_events), .ngrp = 1, .umasks = amd64_fam12h_interrupt_events, }, }; libpfm-4.9.0/lib/events/intel_atom_events.h0000664000175000017500000011174213223402656020566 0ustar eranianeranian/* * Copyright (c) 2011 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * This file has been automatically generated. * * PMU: atom (Intel Atom) */ static const intel_x86_umask_t atom_l2_reject_busq[]={ { .uname = "MESI", .udesc = "Any cacheline access", .ucode = 0xf00, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, .grpid = 0, }, { .uname = "I_STATE", .udesc = "Invalid cacheline", .ucode = 0x100, .grpid = 0, }, { .uname = "S_STATE", .udesc = "Shared cacheline", .ucode = 0x200, .grpid = 0, }, { .uname = "E_STATE", .udesc = "Exclusive cacheline", .ucode = 0x400, .grpid = 0, }, { .uname = "M_STATE", .udesc = "Modified cacheline", .ucode = 0x800, .grpid = 0, }, { .uname = "SELF", .udesc = "This core", .ucode = 0x4000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, .grpid = 1, }, { .uname = "BOTH_CORES", .udesc = "Both cores", .ucode = 0xc000, .grpid = 1, }, { .uname = "ANY", .udesc = "All inclusive", .ucode = 0x3000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, .grpid = 2, }, { .uname = "PREFETCH", .udesc = "Hardware prefetch only", .ucode = 0x1000, .grpid = 2, }, }; static const intel_x86_umask_t atom_icache[]={ { .uname = "ACCESSES", .udesc = "Instruction fetches, including uncacheacble fetches", .ucode = 0x300, .uflags= INTEL_X86_NCOMBO, }, { .uname = "MISSES", .udesc = "Count all instructions fetches that miss the icache or produce memory requests. This includes uncacheache fetches. Any instruction fetch miss is counted only once and not once for every cycle it is outstanding", .ucode = 0x200, }, }; static const intel_x86_umask_t atom_l2_lock[]={ { .uname = "MESI", .udesc = "Any cacheline access", .ucode = 0xf00, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, .grpid = 0, }, { .uname = "I_STATE", .udesc = "Invalid cacheline", .ucode = 0x100, .grpid = 0, }, { .uname = "S_STATE", .udesc = "Shared cacheline", .ucode = 0x200, .grpid = 0, }, { .uname = "E_STATE", .udesc = "Exclusive cacheline", .ucode = 0x400, .grpid = 0, }, { .uname = "M_STATE", .udesc = "Modified cacheline", .ucode = 0x800, .grpid = 0, }, { .uname = "SELF", .udesc = "This core", .ucode = 0x4000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, .grpid = 1, }, { .uname = "BOTH_CORES", .udesc = "Both cores", .ucode = 0xc000, .grpid = 1, }, }; static const intel_x86_umask_t atom_uops_retired[]={ { .uname = "ANY", .udesc = "Micro-ops retired", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "STALLED_CYCLES", .udesc = "Cycles no micro-ops retired", .ucode = 0x1000 | INTEL_X86_MOD_INV | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, }, { .uname = "STALLS", .udesc = "Periods no micro-ops retired", .ucode = 0x1000 | INTEL_X86_MOD_EDGE | INTEL_X86_MOD_INV | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t atom_l2_m_lines_out[]={ { .uname = "SELF", .udesc = "This core", .ucode = 0x4000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, .grpid = 0, }, { .uname = "BOTH_CORES", .udesc = "Both cores", .ucode = 0xc000, .grpid = 0, }, { .uname = "ANY", .udesc = "All inclusive", .ucode = 0x3000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, .grpid = 1, }, { .uname = "PREFETCH", .udesc = "Hardware prefetch only", .ucode = 0x1000, .grpid = 1, }, }; static const intel_x86_umask_t atom_simd_comp_inst_retired[]={ { .uname = "PACKED_SINGLE", .udesc = "Retired computational Streaming SIMD Extensions (SSE) packed-single instructions", .ucode = 0x100, }, { .uname = "SCALAR_SINGLE", .udesc = "Retired computational Streaming SIMD Extensions (SSE) scalar-single instructions", .ucode = 0x200, }, { .uname = "PACKED_DOUBLE", .udesc = "Retired computational Streaming SIMD Extensions 2 (SSE2) packed-double instructions", .ucode = 0x400, }, { .uname = "SCALAR_DOUBLE", .udesc = "Retired computational Streaming SIMD Extensions 2 (SSE2) scalar-double instructions", .ucode = 0x800, }, }; static const intel_x86_umask_t atom_simd_sat_uop_exec[]={ { .uname = "S", .udesc = "SIMD saturated arithmetic micro-ops executed", .ucode = 0x0, .uflags= INTEL_X86_NCOMBO, }, { .uname = "AR", .udesc = "SIMD saturated arithmetic micro-ops retired", .ucode = 0x8000, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t atom_inst_retired[]={ { .uname = "ANY_P", .udesc = "Instructions retired using generic counter (precise event)", .ucode = 0x0, .uflags= INTEL_X86_PEBS | INTEL_X86_DFL, }, }; static const intel_x86_umask_t atom_l1d_cache[]={ { .uname = "LD", .udesc = "L1 Cacheable Data Reads", .ucode = 0x2100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ST", .udesc = "L1 Cacheable Data Writes", .ucode = 0x2200, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t atom_mul[]={ { .uname = "S", .udesc = "Multiply operations executed", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "AR", .udesc = "Multiply operations retired", .ucode = 0x8100, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t atom_div[]={ { .uname = "S", .udesc = "Divide operations executed", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "AR", .udesc = "Divide operations retired", .ucode = 0x8100, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t atom_bus_trans_p[]={ { .uname = "THIS_AGENT", .udesc = "This agent", .ucode = 0x0, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, .grpid = 0, }, { .uname = "ALL_AGENTS", .udesc = "Any agent on the bus", .ucode = 0x2000, .uflags= INTEL_X86_NCOMBO, .grpid = 0, }, { .uname = "SELF", .udesc = "This core", .ucode = 0x4000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, .grpid = 1, }, { .uname = "BOTH_CORES", .udesc = "Both cores", .ucode = 0xc000, .grpid = 1, }, }; static const intel_x86_umask_t atom_bus_io_wait[]={ { .uname = "SELF", .udesc = "This core", .ucode = 0x4000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "BOTH_CORES", .udesc = "Both cores", .ucode = 0xc000, }, }; static const intel_x86_umask_t atom_bus_hitm_drv[]={ { .uname = "THIS_AGENT", .udesc = "This agent", .ucode = 0x0, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "ALL_AGENTS", .udesc = "Any agent on the bus", .ucode = 0x2000, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t atom_itlb[]={ { .uname = "FLUSH", .udesc = "ITLB flushes", .ucode = 0x400, }, { .uname = "MISSES", .udesc = "ITLB misses", .ucode = 0x200, }, }; static const intel_x86_umask_t atom_simd_uop_type_exec[]={ { .uname = "MUL_S", .udesc = "SIMD packed multiply micro-ops executed", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "MUL_AR", .udesc = "SIMD packed multiply micro-ops retired", .ucode = 0x8100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "SHIFT_S", .udesc = "SIMD packed shift micro-ops executed", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "SHIFT_AR", .udesc = "SIMD packed shift micro-ops retired", .ucode = 0x8200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PACK_S", .udesc = "SIMD packed micro-ops executed", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PACK_AR", .udesc = "SIMD packed micro-ops retired", .ucode = 0x8400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "UNPACK_S", .udesc = "SIMD unpacked micro-ops executed", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "UNPACK_AR", .udesc = "SIMD unpacked micro-ops retired", .ucode = 0x8800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "LOGICAL_S", .udesc = "SIMD packed logical micro-ops executed", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "LOGICAL_AR", .udesc = "SIMD packed logical micro-ops retired", .ucode = 0x9000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ARITHMETIC_S", .udesc = "SIMD packed arithmetic micro-ops executed", .ucode = 0x2000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ARITHMETIC_AR", .udesc = "SIMD packed arithmetic micro-ops retired", .ucode = 0xa000, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t atom_simd_inst_retired[]={ { .uname = "PACKED_SINGLE", .udesc = "Retired Streaming SIMD Extensions (SSE) packed-single instructions", .ucode = 0x100, }, { .uname = "SCALAR_SINGLE", .udesc = "Retired Streaming SIMD Extensions (SSE) scalar-single instructions", .ucode = 0x200, }, { .uname = "PACKED_DOUBLE", .udesc = "Retired Streaming SIMD Extensions 2 (SSE2) packed-double instructions", .ucode = 0x400, }, { .uname = "SCALAR_DOUBLE", .udesc = "Retired Streaming SIMD Extensions 2 (SSE2) scalar-double instructions", .ucode = 0x800, }, { .uname = "VECTOR", .udesc = "Retired Streaming SIMD Extensions 2 (SSE2) vector instructions", .ucode = 0x1000, }, { .uname = "ANY", .udesc = "Retired Streaming SIMD instructions", .ucode = 0x1f00, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t atom_prefetch[]={ { .uname = "PREFETCHT0", .udesc = "Streaming SIMD Extensions (SSE) PrefetchT0 instructions executed", .ucode = 0x100, }, { .uname = "SW_L2", .udesc = "Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions executed", .ucode = 0x600, }, { .uname = "PREFETCHNTA", .udesc = "Streaming SIMD Extensions (SSE) Prefetch NTA instructions executed", .ucode = 0x800, }, }; static const intel_x86_umask_t atom_l2_rqsts[]={ { .uname = "SELF", .udesc = "This core", .ucode = 0x4000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, .grpid = 0, }, { .uname = "BOTH_CORES", .udesc = "Both cores", .ucode = 0xc000, .grpid = 0, }, { .uname = "ANY", .udesc = "All inclusive", .ucode = 0x3000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, .grpid = 1, }, { .uname = "PREFETCH", .udesc = "Hardware prefetch only", .ucode = 0x1000, .grpid = 1, }, { .uname = "MESI", .udesc = "Any cacheline access", .ucode = 0xf00, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, .grpid = 2, }, { .uname = "I_STATE", .udesc = "Invalid cacheline", .ucode = 0x100, .grpid = 2, }, { .uname = "S_STATE", .udesc = "Shared cacheline", .ucode = 0x200, .grpid = 2, }, { .uname = "E_STATE", .udesc = "Exclusive cacheline", .ucode = 0x400, .grpid = 2, }, { .uname = "M_STATE", .udesc = "Modified cacheline", .ucode = 0x800, .grpid = 2, }, }; static const intel_x86_umask_t atom_simd_uops_exec[]={ { .uname = "S", .udesc = "Number of SIMD saturated arithmetic micro-ops executed", .ucode = 0x0, .uflags= INTEL_X86_NCOMBO, }, { .uname = "AR", .udesc = "Number of SIMD saturated arithmetic micro-ops retired", .ucode = 0x8000, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t atom_machine_clears[]={ { .uname = "SMC", .udesc = "Self-Modifying Code detected", .ucode = 0x100, .uflags= INTEL_X86_DFL, }, }; static const intel_x86_umask_t atom_br_inst_retired[]={ { .uname = "ANY", .udesc = "Retired branch instructions", .ucode = 0x0, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "PRED_NOT_TAKEN", .udesc = "Retired branch instructions that were predicted not-taken", .ucode = 0x100, }, { .uname = "MISPRED_NOT_TAKEN", .udesc = "Retired branch instructions that were mispredicted not-taken", .ucode = 0x200, }, { .uname = "PRED_TAKEN", .udesc = "Retired branch instructions that were predicted taken", .ucode = 0x400, }, { .uname = "MISPRED_TAKEN", .udesc = "Retired branch instructions that were mispredicted taken", .ucode = 0x800, }, { .uname = "MISPRED", .udesc = "Retired mispredicted branch instructions", .ucode = 0xa00, .uflags= INTEL_X86_NCOMBO, }, { .uname = "TAKEN", .udesc = "Retired taken branch instructions", .ucode = 0xc00, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ANY1", .udesc = "Retired branch instructions", .ucode = 0xf00, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t atom_macro_insts[]={ { .uname = "NON_CISC_DECODED", .udesc = "Non-CISC macro instructions decoded ", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ALL_DECODED", .udesc = "All Instructions decoded", .ucode = 0x300, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t atom_segment_reg_loads[]={ { .uname = "ANY", .udesc = "Number of segment register loads", .ucode = 0x8000, .uflags= INTEL_X86_DFL, }, }; static const intel_x86_umask_t atom_baclears[]={ { .uname = "ANY", .udesc = "BACLEARS asserted", .ucode = 0x100, .uflags= INTEL_X86_DFL, }, }; static const intel_x86_umask_t atom_cycles_int_masked[]={ { .uname = "CYCLES_INT_MASKED", .udesc = "Cycles during which interrupts are disabled", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "CYCLES_INT_PENDING_AND_MASKED", .udesc = "Cycles during which interrupts are pending and disabled", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t atom_fp_assist[]={ { .uname = "S", .udesc = "Floating point assists for executed instructions", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "AR", .udesc = "Floating point assists for retired instructions", .ucode = 0x8100, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t atom_data_tlb_misses[]={ { .uname = "DTLB_MISS", .udesc = "Memory accesses that missed the DTLB", .ucode = 0x700, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DTLB_MISS_LD", .udesc = "DTLB misses due to load operations", .ucode = 0x500, }, { .uname = "L0_DTLB_MISS_LD", .udesc = "L0 (micro-TLB) misses due to load operations", .ucode = 0x900, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DTLB_MISS_ST", .udesc = "DTLB misses due to store operations", .ucode = 0x600, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t atom_store_forwards[]={ { .uname = "GOOD", .udesc = "Good store forwards", .ucode = 0x8100, .uflags= INTEL_X86_DFL, }, }; static const intel_x86_umask_t atom_cpu_clk_unhalted[]={ { .uname = "CORE_P", .udesc = "Core cycles when core is not halted", .ucode = 0x0, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "BUS", .udesc = "Bus cycles when core is not halted. This event can give a measurement of the elapsed time. This events has a constant ratio with CPU_CLK_UNHALTED:REF event, which is the maximum bus to processor frequency ratio", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "NO_OTHER", .udesc = "Bus cycles when core is active and other is halted", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t atom_mem_load_retired[]={ { .uname = "L2_HIT", .udesc = "Retired loads that hit the L2 cache (precise event)", .ucode = 0x100, .uflags= INTEL_X86_PEBS, }, { .uname = "L2_MISS", .udesc = "Retired loads that miss the L2 cache (precise event)", .ucode = 0x200, .uflags= INTEL_X86_PEBS, }, { .uname = "DTLB_MISS", .udesc = "Retired loads that miss the DTLB (precise event)", .ucode = 0x400, .uflags= INTEL_X86_PEBS, }, }; static const intel_x86_umask_t atom_x87_comp_ops_exe[]={ { .uname = "ANY_S", .udesc = "Floating point computational micro-ops executed", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ANY_AR", .udesc = "Floating point computational micro-ops retired", .ucode = 0x8100, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t atom_page_walks[]={ { .uname = "WALKS", .udesc = "Number of page-walks executed", .uequiv = "CYCLES", .ucode = 0x300 | INTEL_X86_MOD_EDGE, .modhw = _INTEL_X86_ATTR_E, .uflags= INTEL_X86_NCOMBO, }, { .uname = "CYCLES", .udesc = "Duration of page-walks in core cycles", .ucode = 0x300, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_entry_t intel_atom_pe[]={ { .name = "UNHALTED_CORE_CYCLES", .desc = "Unhalted core cycles", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x200000003ull, .code = 0x3c, }, { .name = "UNHALTED_REFERENCE_CYCLES", .desc = "Unhalted reference cycle", .modmsk = INTEL_FIXED3_ATTRS, .cntmsk = 0x400000000ull, .code = 0x0300, /* pseudo encoding */ .flags = INTEL_X86_FIXED, }, { .name = "INSTRUCTION_RETIRED", .desc = "Instructions retired", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x100000003ull, .code = 0xc0, }, { .name = "INSTRUCTIONS_RETIRED", .desc = "This is an alias for INSTRUCTION_RETIRED", .modmsk = INTEL_V3_ATTRS, .equiv = "INSTRUCTION_RETIRED", .cntmsk = 0x10003, .code = 0xc0, }, { .name = "LLC_REFERENCES", .desc = "Last level of cache references", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x4f2e, }, { .name = "LAST_LEVEL_CACHE_REFERENCES", .desc = "This is an alias for LLC_REFERENCES", .modmsk = INTEL_V3_ATTRS, .equiv = "LLC_REFERENCES", .cntmsk = 0x3, .code = 0x4f2e, }, { .name = "LLC_MISSES", .desc = "Last level of cache misses", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x412e, }, { .name = "LAST_LEVEL_CACHE_MISSES", .desc = "This is an alias for LLC_MISSES", .modmsk = INTEL_V3_ATTRS, .equiv = "LLC_MISSES", .cntmsk = 0x3, .code = 0x412e, }, { .name = "BRANCH_INSTRUCTIONS_RETIRED", .desc = "Branch instructions retired", .modmsk = INTEL_V3_ATTRS, .equiv = "BR_INST_RETIRED:ANY", .cntmsk = 0x3, .code = 0xc4, }, { .name = "MISPREDICTED_BRANCH_RETIRED", .desc = "Mispredicted branch instruction retired", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0xc5, .flags= INTEL_X86_PEBS, }, { .name = "SIMD_INSTR_RETIRED", .desc = "SIMD Instructions retired", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0xce, }, { .name = "L2_REJECT_BUSQ", .desc = "Rejected L2 cache requests", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x30, .numasks = LIBPFM_ARRAY_SIZE(atom_l2_reject_busq), .ngrp = 3, .umasks = atom_l2_reject_busq, }, { .name = "SIMD_SAT_INSTR_RETIRED", .desc = "Saturated arithmetic instructions retired", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0xcf, }, { .name = "ICACHE", .desc = "Instruction fetches", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x80, .numasks = LIBPFM_ARRAY_SIZE(atom_icache), .ngrp = 1, .umasks = atom_icache, }, { .name = "L2_LOCK", .desc = "L2 locked accesses", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x2b, .numasks = LIBPFM_ARRAY_SIZE(atom_l2_lock), .ngrp = 2, .umasks = atom_l2_lock, }, { .name = "UOPS_RETIRED", .desc = "Micro-ops retired", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0xc2, .numasks = LIBPFM_ARRAY_SIZE(atom_uops_retired), .ngrp = 1, .umasks = atom_uops_retired, }, { .name = "L2_M_LINES_OUT", .desc = "Modified lines evicted from the L2 cache", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x27, .numasks = LIBPFM_ARRAY_SIZE(atom_l2_m_lines_out), .ngrp = 2, .umasks = atom_l2_m_lines_out, }, { .name = "SIMD_COMP_INST_RETIRED", .desc = "Retired computational Streaming SIMD Extensions (SSE) instructions", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0xca, .numasks = LIBPFM_ARRAY_SIZE(atom_simd_comp_inst_retired), .ngrp = 1, .umasks = atom_simd_comp_inst_retired, }, { .name = "SNOOP_STALL_DRV", .desc = "Bus stalled for snoops", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x7e, .numasks = LIBPFM_ARRAY_SIZE(atom_l2_m_lines_out), .ngrp = 2, .umasks = atom_l2_m_lines_out, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRANS_BURST", .desc = "Burst (full cache-line) bus transactions", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x6e, .numasks = LIBPFM_ARRAY_SIZE(atom_l2_m_lines_out), .ngrp = 2, .umasks = atom_l2_m_lines_out, /* identical to actual umasks list for this event */ }, { .name = "SIMD_SAT_UOP_EXEC", .desc = "SIMD saturated arithmetic micro-ops executed", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0xb1, .numasks = LIBPFM_ARRAY_SIZE(atom_simd_sat_uop_exec), .ngrp = 1, .umasks = atom_simd_sat_uop_exec, }, { .name = "BUS_TRANS_IO", .desc = "IO bus transactions", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x6c, .numasks = LIBPFM_ARRAY_SIZE(atom_l2_m_lines_out), .ngrp = 2, .umasks = atom_l2_m_lines_out, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRANS_RFO", .desc = "RFO bus transactions", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x66, .numasks = LIBPFM_ARRAY_SIZE(atom_l2_m_lines_out), .ngrp = 2, .umasks = atom_l2_m_lines_out, /* identical to actual umasks list for this event */ }, { .name = "SIMD_ASSIST", .desc = "SIMD assists invoked", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0xcd, }, { .name = "INST_RETIRED", .desc = "Instructions retired", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0xc0, .flags= INTEL_X86_PEBS, .numasks = LIBPFM_ARRAY_SIZE(atom_inst_retired), .ngrp = 1, .umasks = atom_inst_retired, }, { .name = "L1D_CACHE", .desc = "L1 Cacheable Data Reads", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x40, .numasks = LIBPFM_ARRAY_SIZE(atom_l1d_cache), .ngrp = 1, .umasks = atom_l1d_cache, }, { .name = "MUL", .desc = "Multiply operations executed", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x12, .numasks = LIBPFM_ARRAY_SIZE(atom_mul), .ngrp = 1, .umasks = atom_mul, }, { .name = "DIV", .desc = "Divide operations executed", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x13, .numasks = LIBPFM_ARRAY_SIZE(atom_div), .ngrp = 1, .umasks = atom_div, }, { .name = "BUS_TRANS_P", .desc = "Partial bus transactions", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x6b, .numasks = LIBPFM_ARRAY_SIZE(atom_bus_trans_p), .ngrp = 2, .umasks = atom_bus_trans_p, }, { .name = "BUS_IO_WAIT", .desc = "IO requests waiting in the bus queue", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x7f, .numasks = LIBPFM_ARRAY_SIZE(atom_bus_io_wait), .ngrp = 1, .umasks = atom_bus_io_wait, }, { .name = "L2_M_LINES_IN", .desc = "L2 cache line modifications", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x25, .numasks = LIBPFM_ARRAY_SIZE(atom_bus_io_wait), .ngrp = 1, .umasks = atom_bus_io_wait, /* identical to actual umasks list for this event */ }, { .name = "L2_LINES_IN", .desc = "L2 cache misses", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x24, .numasks = LIBPFM_ARRAY_SIZE(atom_l2_m_lines_out), .ngrp = 2, .umasks = atom_l2_m_lines_out, /* identical to actual umasks list for this event */ }, { .name = "BUSQ_EMPTY", .desc = "Bus queue is empty", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x7d, .numasks = LIBPFM_ARRAY_SIZE(atom_bus_io_wait), .ngrp = 1, .umasks = atom_bus_io_wait, /* identical to actual umasks list for this event */ }, { .name = "L2_IFETCH", .desc = "L2 cacheable instruction fetch requests", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x28, .numasks = LIBPFM_ARRAY_SIZE(atom_l2_lock), .ngrp = 2, .umasks = atom_l2_lock, /* identical to actual umasks list for this event */ }, { .name = "BUS_HITM_DRV", .desc = "HITM signal asserted", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x7b, .numasks = LIBPFM_ARRAY_SIZE(atom_bus_hitm_drv), .ngrp = 1, .umasks = atom_bus_hitm_drv, }, { .name = "ITLB", .desc = "ITLB hits", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x82, .numasks = LIBPFM_ARRAY_SIZE(atom_itlb), .ngrp = 1, .umasks = atom_itlb, }, { .name = "BUS_TRANS_MEM", .desc = "Memory bus transactions", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x6f, .numasks = LIBPFM_ARRAY_SIZE(atom_l2_m_lines_out), .ngrp = 2, .umasks = atom_l2_m_lines_out, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRANS_PWR", .desc = "Partial write bus transaction", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x6a, .numasks = LIBPFM_ARRAY_SIZE(atom_l2_m_lines_out), .ngrp = 2, .umasks = atom_l2_m_lines_out, /* identical to actual umasks list for this event */ }, { .name = "BR_INST_DECODED", .desc = "Branch instructions decoded", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x1e0, }, { .name = "BUS_TRANS_INVAL", .desc = "Invalidate bus transactions", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x69, .numasks = LIBPFM_ARRAY_SIZE(atom_l2_m_lines_out), .ngrp = 2, .umasks = atom_l2_m_lines_out, /* identical to actual umasks list for this event */ }, { .name = "SIMD_UOP_TYPE_EXEC", .desc = "SIMD micro-ops executed", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0xb3, .numasks = LIBPFM_ARRAY_SIZE(atom_simd_uop_type_exec), .ngrp = 1, .umasks = atom_simd_uop_type_exec, }, { .name = "SIMD_INST_RETIRED", .desc = "Retired Streaming SIMD Extensions (SSE) instructions", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0xc7, .numasks = LIBPFM_ARRAY_SIZE(atom_simd_inst_retired), .ngrp = 1, .umasks = atom_simd_inst_retired, }, { .name = "CYCLES_DIV_BUSY", .desc = "Cycles the divider is busy", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x14, }, { .name = "PREFETCH", .desc = "Streaming SIMD Extensions (SSE) PrefetchT0 instructions executed", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x7, .numasks = LIBPFM_ARRAY_SIZE(atom_prefetch), .ngrp = 1, .umasks = atom_prefetch, }, { .name = "L2_RQSTS", .desc = "L2 cache requests", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x2e, .numasks = LIBPFM_ARRAY_SIZE(atom_l2_rqsts), .ngrp = 3, .umasks = atom_l2_rqsts, }, { .name = "SIMD_UOPS_EXEC", .desc = "SIMD micro-ops executed (excluding stores)", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0xb0, .numasks = LIBPFM_ARRAY_SIZE(atom_simd_uops_exec), .ngrp = 1, .umasks = atom_simd_uops_exec, }, { .name = "HW_INT_RCV", .desc = "Hardware interrupts received (warning overcounts by 2x)", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x1c8, }, { .name = "BUS_TRANS_BRD", .desc = "Burst read bus transactions", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x65, .numasks = LIBPFM_ARRAY_SIZE(atom_bus_trans_p), .ngrp = 2, .umasks = atom_bus_trans_p, /* identical to actual umasks list for this event */ }, { .name = "BOGUS_BR", .desc = "Bogus branches", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0xe4, }, { .name = "BUS_DATA_RCV", .desc = "Bus cycles while processor receives data", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x64, .numasks = LIBPFM_ARRAY_SIZE(atom_bus_io_wait), .ngrp = 1, .umasks = atom_bus_io_wait, /* identical to actual umasks list for this event */ }, { .name = "MACHINE_CLEARS", .desc = "Self-Modifying Code detected", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0xc3, .numasks = LIBPFM_ARRAY_SIZE(atom_machine_clears), .ngrp = 1, .umasks = atom_machine_clears, }, { .name = "BR_INST_RETIRED", .desc = "Retired branch instructions", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0xc4, .numasks = LIBPFM_ARRAY_SIZE(atom_br_inst_retired), .ngrp = 1, .umasks = atom_br_inst_retired, }, { .name = "L2_ADS", .desc = "Cycles L2 address bus is in use", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x21, .numasks = LIBPFM_ARRAY_SIZE(atom_bus_io_wait), .ngrp = 1, .umasks = atom_bus_io_wait, /* identical to actual umasks list for this event */ }, { .name = "EIST_TRANS", .desc = "Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x3a, }, { .name = "BUS_TRANS_WB", .desc = "Explicit writeback bus transactions", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x67, .numasks = LIBPFM_ARRAY_SIZE(atom_l2_m_lines_out), .ngrp = 2, .umasks = atom_l2_m_lines_out, /* identical to actual umasks list for this event */ }, { .name = "MACRO_INSTS", .desc = "Macro-instructions decoded", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0xaa, .numasks = LIBPFM_ARRAY_SIZE(atom_macro_insts), .ngrp = 1, .umasks = atom_macro_insts, }, { .name = "L2_LINES_OUT", .desc = "L2 cache lines evicted. ", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x26, .numasks = LIBPFM_ARRAY_SIZE(atom_l2_m_lines_out), .ngrp = 2, .umasks = atom_l2_m_lines_out, /* identical to actual umasks list for this event */ }, { .name = "L2_LD", .desc = "L2 cache reads", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x29, .numasks = LIBPFM_ARRAY_SIZE(atom_l2_rqsts), .ngrp = 3, .umasks = atom_l2_rqsts, /* identical to actual umasks list for this event */ }, { .name = "SEGMENT_REG_LOADS", .desc = "Number of segment register loads", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x6, .numasks = LIBPFM_ARRAY_SIZE(atom_segment_reg_loads), .ngrp = 1, .umasks = atom_segment_reg_loads, }, { .name = "L2_NO_REQ", .desc = "Cycles no L2 cache requests are pending", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x32, .numasks = LIBPFM_ARRAY_SIZE(atom_bus_io_wait), .ngrp = 1, .umasks = atom_bus_io_wait, /* identical to actual umasks list for this event */ }, { .name = "THERMAL_TRIP", .desc = "Number of thermal trips", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0xc03b, }, { .name = "EXT_SNOOP", .desc = "External snoops", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x77, .numasks = LIBPFM_ARRAY_SIZE(atom_l2_lock), .ngrp = 2, .umasks = atom_l2_lock, /* identical to actual umasks list for this event */ }, { .name = "BACLEARS", .desc = "Branch address calculator", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0xe6, .numasks = LIBPFM_ARRAY_SIZE(atom_baclears), .ngrp = 1, .umasks = atom_baclears, }, { .name = "CYCLES_INT_MASKED", .desc = "Cycles during which interrupts are disabled", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0xc6, .numasks = LIBPFM_ARRAY_SIZE(atom_cycles_int_masked), .ngrp = 1, .umasks = atom_cycles_int_masked, }, { .name = "FP_ASSIST", .desc = "Floating point assists", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x11, .numasks = LIBPFM_ARRAY_SIZE(atom_fp_assist), .ngrp = 1, .umasks = atom_fp_assist, }, { .name = "L2_ST", .desc = "L2 store requests", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x2a, .numasks = LIBPFM_ARRAY_SIZE(atom_l2_lock), .ngrp = 2, .umasks = atom_l2_lock, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRANS_DEF", .desc = "Deferred bus transactions", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x6d, .numasks = LIBPFM_ARRAY_SIZE(atom_l2_m_lines_out), .ngrp = 2, .umasks = atom_l2_m_lines_out, /* identical to actual umasks list for this event */ }, { .name = "DATA_TLB_MISSES", .desc = "Memory accesses that missed the DTLB", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x8, .numasks = LIBPFM_ARRAY_SIZE(atom_data_tlb_misses), .ngrp = 1, .umasks = atom_data_tlb_misses, }, { .name = "BUS_BNR_DRV", .desc = "Number of Bus Not Ready signals asserted", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x61, .numasks = LIBPFM_ARRAY_SIZE(atom_bus_hitm_drv), .ngrp = 1, .umasks = atom_bus_hitm_drv, /* identical to actual umasks list for this event */ }, { .name = "STORE_FORWARDS", .desc = "All store forwards", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x2, .numasks = LIBPFM_ARRAY_SIZE(atom_store_forwards), .ngrp = 1, .umasks = atom_store_forwards, }, { .name = "CPU_CLK_UNHALTED", .desc = "Core cycles when core is not halted", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x3c, .numasks = LIBPFM_ARRAY_SIZE(atom_cpu_clk_unhalted), .ngrp = 1, .umasks = atom_cpu_clk_unhalted, }, { .name = "BUS_TRANS_ANY", .desc = "All bus transactions", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x70, .numasks = LIBPFM_ARRAY_SIZE(atom_l2_m_lines_out), .ngrp = 2, .umasks = atom_l2_m_lines_out, /* identical to actual umasks list for this event */ }, { .name = "MEM_LOAD_RETIRED", .desc = "Retired loads", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0xcb, .flags= INTEL_X86_PEBS, .numasks = LIBPFM_ARRAY_SIZE(atom_mem_load_retired), .ngrp = 1, .umasks = atom_mem_load_retired, }, { .name = "X87_COMP_OPS_EXE", .desc = "Floating point computational micro-ops executed", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x10, .numasks = LIBPFM_ARRAY_SIZE(atom_x87_comp_ops_exe), .ngrp = 1, .umasks = atom_x87_comp_ops_exe, }, { .name = "PAGE_WALKS", .desc = "Number of page-walks executed", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0xc, .numasks = LIBPFM_ARRAY_SIZE(atom_page_walks), .ngrp = 1, .umasks = atom_page_walks, }, { .name = "BUS_LOCK_CLOCKS", .desc = "Bus cycles when a LOCK signal is asserted", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x63, .numasks = LIBPFM_ARRAY_SIZE(atom_bus_trans_p), .ngrp = 2, .umasks = atom_bus_trans_p, /* identical to actual umasks list for this event */ }, { .name = "BUS_REQUEST_OUTSTANDING", .desc = "Outstanding cacheable data read bus requests duration", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x60, .numasks = LIBPFM_ARRAY_SIZE(atom_bus_trans_p), .ngrp = 2, .umasks = atom_bus_trans_p, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRANS_IFETCH", .desc = "Instruction-fetch bus transactions", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x68, .numasks = LIBPFM_ARRAY_SIZE(atom_bus_trans_p), .ngrp = 2, .umasks = atom_bus_trans_p, /* identical to actual umasks list for this event */ }, { .name = "BUS_HIT_DRV", .desc = "HIT signal asserted", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x7a, .numasks = LIBPFM_ARRAY_SIZE(atom_bus_hitm_drv), .ngrp = 1, .umasks = atom_bus_hitm_drv, /* identical to actual umasks list for this event */ }, { .name = "BUS_DRDY_CLOCKS", .desc = "Bus cycles when data is sent on the bus", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x62, .numasks = LIBPFM_ARRAY_SIZE(atom_bus_hitm_drv), .ngrp = 1, .umasks = atom_bus_hitm_drv, /* identical to actual umasks list for this event */ }, { .name = "L2_DBUS_BUSY", .desc = "Cycles the L2 cache data bus is busy", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x22, .numasks = LIBPFM_ARRAY_SIZE(atom_bus_io_wait), .ngrp = 1, .umasks = atom_bus_io_wait, /* identical to actual umasks list for this event */ }, }; libpfm-4.9.0/lib/events/intel_nhm_events.h0000664000175000017500000021677113223402656020420 0ustar eranianeranian/* * Copyright (c) 2011 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * This file has been automatically generated. * * PMU: nhm (Intel Nehalem) */ static const intel_x86_umask_t nhm_arith[]={ { .uname = "CYCLES_DIV_BUSY", .udesc = "Counts the number of cycles the divider is busy executing divide or square root operations. The divide can be integer, X87 or Streaming SIMD Extensions (SSE). The square root operation can be either X87 or SSE.", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DIV", .udesc = "Counts the number of divide or square root operations. The divide can be integer, X87 or Streaming SIMD Extensions (SSE). The square root operation can be either X87 or SSE.", .uequiv = "CYCLES_DIV_BUSY:c=1:i=1:e=1", .ucode = 0x100 | INTEL_X86_MOD_EDGE | INTEL_X86_MOD_INV | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, }, { .uname = "MUL", .udesc = "Counts the number of multiply operations executed. This includes integer as well as floating point multiply operations but excludes DPPS mul and MPSAD.", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t nhm_baclear[]={ { .uname = "BAD_TARGET", .udesc = "BACLEAR asserted with bad target address", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "CLEAR", .udesc = "BACLEAR asserted, regardless of cause", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t nhm_bpu_clears[]={ { .uname = "EARLY", .udesc = "Early Branch Prediction Unit clears", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "LATE", .udesc = "Late Branch Prediction Unit clears", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ANY", .udesc = "Count any Branch Prediction Unit clears", .ucode = 0x300, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t nhm_br_inst_exec[]={ { .uname = "ANY", .udesc = "Branch instructions executed", .ucode = 0x7f00, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "COND", .udesc = "Conditional branch instructions executed", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DIRECT", .udesc = "Unconditional branches executed", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DIRECT_NEAR_CALL", .udesc = "Unconditional call branches executed", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "INDIRECT_NEAR_CALL", .udesc = "Indirect call branches executed", .ucode = 0x2000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "INDIRECT_NON_CALL", .udesc = "Indirect non call branches executed", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "NEAR_CALLS", .udesc = "Call branches executed", .ucode = 0x3000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "NON_CALLS", .udesc = "All non call branches executed", .ucode = 0x700, .uflags= INTEL_X86_NCOMBO, }, { .uname = "RETURN_NEAR", .udesc = "Indirect return branches executed", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "TAKEN", .udesc = "Taken branches executed", .ucode = 0x4000, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t nhm_br_inst_retired[]={ { .uname = "ALL_BRANCHES", .udesc = "Retired branch instructions (Precise Event)", .ucode = 0x0, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS | INTEL_X86_DFL, }, { .uname = "CONDITIONAL", .udesc = "Retired conditional branch instructions (Precise Event)", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "NEAR_CALL", .udesc = "Retired near call instructions (Precise Event)", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, }; static const intel_x86_umask_t nhm_br_misp_exec[]={ { .uname = "ANY", .udesc = "Mispredicted branches executed", .ucode = 0x7f00, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "COND", .udesc = "Mispredicted conditional branches executed", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DIRECT", .udesc = "Mispredicted unconditional branches executed", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DIRECT_NEAR_CALL", .udesc = "Mispredicted non call branches executed", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "INDIRECT_NEAR_CALL", .udesc = "Mispredicted indirect call branches executed", .ucode = 0x2000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "INDIRECT_NON_CALL", .udesc = "Mispredicted indirect non call branches executed", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "NEAR_CALLS", .udesc = "Mispredicted call branches executed", .ucode = 0x3000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "NON_CALLS", .udesc = "Mispredicted non call branches executed", .ucode = 0x700, .uflags= INTEL_X86_NCOMBO, }, { .uname = "RETURN_NEAR", .udesc = "Mispredicted return branches executed", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "TAKEN", .udesc = "Mispredicted taken branches executed", .ucode = 0x4000, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t nhm_br_misp_retired[]={ { .uname = "NEAR_CALL", .udesc = "Counts mispredicted direct and indirect near unconditional retired calls", .ucode = 0x200, .uflags= INTEL_X86_PEBS | INTEL_X86_DFL, }, }; static const intel_x86_umask_t nhm_cache_lock_cycles[]={ { .uname = "L1D", .udesc = "Cycles L1D locked", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "L1D_L2", .udesc = "Cycles L1D and L2 locked", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t nhm_cpu_clk_unhalted[]={ { .uname = "THREAD_P", .udesc = "Cycles when thread is not halted (programmable counter)", .ucode = 0x0, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "REF_P", .udesc = "Reference base clock (133 Mhz) cycles when thread is not halted", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "TOTAL_CYCLES", .udesc = "Total number of elapsed cycles. Does not work when C-state enabled", .uequiv = "THREAD_P:c=2:i=1", .ucode = 0x0 | INTEL_X86_MOD_INV | (0x2 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t nhm_dtlb_load_misses[]={ { .uname = "ANY", .udesc = "DTLB load misses", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "PDE_MISS", .udesc = "DTLB load miss caused by low part of address", .ucode = 0x2000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "WALK_COMPLETED", .udesc = "DTLB load miss page walks complete", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "STLB_HIT", .udesc = "DTLB second level hit", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PDP_MISS", .udesc = "Number of DTLB cache load misses where the high part of the linear to physical address translation was missed", .ucode = 0x4000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "LARGE_WALK_COMPLETED", .udesc = "Counts number of completed large page walks due to load miss in the STLB", .ucode = 0x8000, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t nhm_dtlb_misses[]={ { .uname = "ANY", .udesc = "DTLB misses", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "STLB_HIT", .udesc = "DTLB first level misses but second level hit", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "WALK_COMPLETED", .udesc = "DTLB miss page walks", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PDE_MISS", .udesc = "Number of DTLB cache misses where the low part of the linear to physical address translation was missed", .ucode = 0x2000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PDP_MISS", .udesc = "Number of DTLB misses where the high part of the linear to physical address translation was missed", .ucode = 0x4000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "LARGE_WALK_COMPLETED", .udesc = "Counts number of completed large page walks due to misses in the STLB", .ucode = 0x8000, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t nhm_ept[]={ { .uname = "EPDE_MISS", .udesc = "Extended Page Directory Entry miss", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "EPDPE_MISS", .udesc = "Extended Page Directory Pointer miss", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "EPDPE_HIT", .udesc = "Extended Page Directory Pointer hit", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t nhm_fp_assist[]={ { .uname = "ALL", .udesc = "Floating point assists (Precise Event)", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS | INTEL_X86_DFL, }, { .uname = "INPUT", .udesc = "Floating point assists for invalid input value (Precise Event)", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "OUTPUT", .udesc = "Floating point assists for invalid output value (Precise Event)", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, }; static const intel_x86_umask_t nhm_fp_comp_ops_exe[]={ { .uname = "MMX", .udesc = "MMX Uops", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "SSE_DOUBLE_PRECISION", .udesc = "SSE* FP double precision Uops", .ucode = 0x8000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "SSE_FP", .udesc = "SSE and SSE2 FP Uops", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "SSE_FP_PACKED", .udesc = "SSE FP packed Uops", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "SSE_FP_SCALAR", .udesc = "SSE FP scalar Uops", .ucode = 0x2000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "SSE_SINGLE_PRECISION", .udesc = "SSE* FP single precision Uops", .ucode = 0x4000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "SSE2_INTEGER", .udesc = "SSE2 integer Uops", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "X87", .udesc = "Computational floating-point operations executed", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t nhm_fp_mmx_trans[]={ { .uname = "ANY", .udesc = "All Floating Point to and from MMX transitions", .ucode = 0x300, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "TO_FP", .udesc = "Transitions from MMX to Floating Point instructions", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "TO_MMX", .udesc = "Transitions from Floating Point to MMX instructions", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t nhm_ifu_ivc[]={ { .uname = "FULL", .udesc = "Instruction Fetche unit victim cache full", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "L1I_EVICTION", .udesc = "L1 Instruction cache evictions", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t nhm_ild_stall[]={ { .uname = "ANY", .udesc = "Any Instruction Length Decoder stall cycles", .uequiv = "IQ_FULL:LCP:MRU:REGEN", .ucode = 0xf00, .uflags= INTEL_X86_DFL, }, { .uname = "IQ_FULL", .udesc = "Instruction Queue full stall cycles", .ucode = 0x400, }, { .uname = "LCP", .udesc = "Length Change Prefix stall cycles", .ucode = 0x100, }, { .uname = "MRU", .udesc = "Stall cycles due to BPU MRU bypass", .ucode = 0x200, }, { .uname = "REGEN", .udesc = "Regen stall cycles", .ucode = 0x800, }, }; static const intel_x86_umask_t nhm_inst_decoded[]={ { .uname = "DEC0", .udesc = "Instructions that must be decoded by decoder 0", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t nhm_inst_retired[]={ { .uname = "ANY_P", .udesc = "Instructions Retired (Precise Event)", .ucode = 0x0, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS | INTEL_X86_DFL, }, { .uname = "X87", .udesc = "Retired floating-point operations (Precise Event)", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, }; static const intel_x86_umask_t nhm_l1d[]={ { .uname = "M_EVICT", .udesc = "L1D cache lines replaced in M state", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "M_REPL", .udesc = "L1D cache lines allocated in the M state", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "M_SNOOP_EVICT", .udesc = "L1D snoop eviction of cache lines in M state", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "REPL", .udesc = "L1 data cache lines allocated", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t nhm_l1d_all_ref[]={ { .uname = "ANY", .udesc = "All references to the L1 data cache", .ucode = 0x100, .uflags= INTEL_X86_DFL, }, { .uname = "CACHEABLE", .udesc = "L1 data cacheable reads and writes", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t nhm_l1d_cache_ld[]={ { .uname = "E_STATE", .udesc = "L1 data cache read in E state", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "I_STATE", .udesc = "L1 data cache read in I state (misses)", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "M_STATE", .udesc = "L1 data cache read in M state", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "MESI", .udesc = "L1 data cache reads", .ucode = 0xf00, .uflags= INTEL_X86_DFL, }, { .uname = "S_STATE", .udesc = "L1 data cache read in S state", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t nhm_l1d_cache_lock[]={ { .uname = "E_STATE", .udesc = "L1 data cache load locks in E state", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "HIT", .udesc = "L1 data cache load lock hits", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "M_STATE", .udesc = "L1 data cache load locks in M state", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "S_STATE", .udesc = "L1 data cache load locks in S state", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t nhm_l1d_cache_st[]={ { .uname = "E_STATE", .udesc = "L1 data cache stores in E state", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "I_STATE", .udesc = "L1 data cache store in the I state", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "M_STATE", .udesc = "L1 data cache stores in M state", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "S_STATE", .udesc = "L1 data cache stores in S state", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "MESI", .udesc = "L1 data cache store in all states", .ucode = 0xf00, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t nhm_l1d_prefetch[]={ { .uname = "MISS", .udesc = "L1D hardware prefetch misses", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "REQUESTS", .udesc = "L1D hardware prefetch requests", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "TRIGGERS", .udesc = "L1D hardware prefetch requests triggered", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t nhm_l1d_wb_l2[]={ { .uname = "E_STATE", .udesc = "L1 writebacks to L2 in E state", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "I_STATE", .udesc = "L1 writebacks to L2 in I state (misses)", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "M_STATE", .udesc = "L1 writebacks to L2 in M state", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "S_STATE", .udesc = "L1 writebacks to L2 in S state", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "MESI", .udesc = "All L1 writebacks to L2", .ucode = 0xf00, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t nhm_l1i[]={ { .uname = "CYCLES_STALLED", .udesc = "L1I instruction fetch stall cycles", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "HITS", .udesc = "L1I instruction fetch hits", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "MISSES", .udesc = "L1I instruction fetch misses", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "READS", .udesc = "L1I Instruction fetches", .ucode = 0x300, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t nhm_l2_data_rqsts[]={ { .uname = "ANY", .udesc = "All L2 data requests", .ucode = 0xff00, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "DEMAND_E_STATE", .udesc = "L2 data demand loads in E state", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DEMAND_I_STATE", .udesc = "L2 data demand loads in I state (misses)", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DEMAND_M_STATE", .udesc = "L2 data demand loads in M state", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DEMAND_MESI", .udesc = "L2 data demand requests", .ucode = 0xf00, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DEMAND_S_STATE", .udesc = "L2 data demand loads in S state", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PREFETCH_E_STATE", .udesc = "L2 data prefetches in E state", .ucode = 0x4000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PREFETCH_I_STATE", .udesc = "L2 data prefetches in the I state (misses)", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PREFETCH_M_STATE", .udesc = "L2 data prefetches in M state", .ucode = 0x8000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PREFETCH_MESI", .udesc = "All L2 data prefetches", .ucode = 0xf000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PREFETCH_S_STATE", .udesc = "L2 data prefetches in the S state", .ucode = 0x2000, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t nhm_l2_hw_prefetch[]={ { .uname = "HIT", .udesc = "Count L2 HW prefetcher detector hits", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ALLOC", .udesc = "Count L2 HW prefetcher allocations", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DATA_TRIGGER", .udesc = "Count L2 HW data prefetcher triggered", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "CODE_TRIGGER", .udesc = "Count L2 HW code prefetcher triggered", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DCA_TRIGGER", .udesc = "Count L2 HW DCA prefetcher triggered", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "KICK_START", .udesc = "Count L2 HW prefetcher kick started", .ucode = 0x2000, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t nhm_l2_lines_in[]={ { .uname = "ANY", .udesc = "L2 lines allocated", .ucode = 0x700, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "E_STATE", .udesc = "L2 lines allocated in the E state", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "S_STATE", .udesc = "L2 lines allocated in the S state", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t nhm_l2_lines_out[]={ { .uname = "ANY", .udesc = "L2 lines evicted", .ucode = 0xf00, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "DEMAND_CLEAN", .udesc = "L2 lines evicted by a demand request", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DEMAND_DIRTY", .udesc = "L2 modified lines evicted by a demand request", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PREFETCH_CLEAN", .udesc = "L2 lines evicted by a prefetch request", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PREFETCH_DIRTY", .udesc = "L2 modified lines evicted by a prefetch request", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t nhm_l2_rqsts[]={ { .uname = "MISS", .udesc = "All L2 misses", .ucode = 0xaa00, .uflags= INTEL_X86_NCOMBO, }, { .uname = "REFERENCES", .udesc = "All L2 requests", .ucode = 0xff00, .uflags= INTEL_X86_NCOMBO, }, { .uname = "IFETCH_HIT", .udesc = "L2 instruction fetch hits", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "IFETCH_MISS", .udesc = "L2 instruction fetch misses", .ucode = 0x2000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "IFETCHES", .udesc = "L2 instruction fetches", .ucode = 0x3000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "LD_HIT", .udesc = "L2 load hits", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "LD_MISS", .udesc = "L2 load misses", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "LOADS", .udesc = "L2 requests", .ucode = 0x300, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PREFETCH_HIT", .udesc = "L2 prefetch hits", .ucode = 0x4000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PREFETCH_MISS", .udesc = "L2 prefetch misses", .ucode = 0x8000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PREFETCHES", .udesc = "All L2 prefetches", .ucode = 0xc000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "RFO_HIT", .udesc = "L2 RFO hits", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "RFO_MISS", .udesc = "L2 RFO misses", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "RFOS", .udesc = "L2 RFO requests", .ucode = 0xc00, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t nhm_l2_transactions[]={ { .uname = "ANY", .udesc = "All L2 transactions", .ucode = 0x8000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "FILL", .udesc = "L2 fill transactions", .ucode = 0x2000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "IFETCH", .udesc = "L2 instruction fetch transactions", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "L1D_WB", .udesc = "L1D writeback to L2 transactions", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "LOAD", .udesc = "L2 Load transactions", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PREFETCH", .udesc = "L2 prefetch transactions", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "RFO", .udesc = "L2 RFO transactions", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "WB", .udesc = "L2 writeback to LLC transactions", .ucode = 0x4000, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t nhm_l2_write[]={ { .uname = "LOCK_E_STATE", .udesc = "L2 demand lock RFOs in E state", .ucode = 0x4000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "LOCK_I_STATE", .udesc = "L2 demand lock RFOs in I state (misses)", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "LOCK_S_STATE", .udesc = "L2 demand lock RFOs in S state", .ucode = 0x2000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "LOCK_HIT", .udesc = "All demand L2 lock RFOs that hit the cache", .ucode = 0xe000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "LOCK_M_STATE", .udesc = "L2 demand lock RFOs in M state", .ucode = 0x8000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "LOCK_MESI", .udesc = "All demand L2 lock RFOs", .ucode = 0xf000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "RFO_HIT", .udesc = "All L2 demand store RFOs that hit the cache", .ucode = 0xe00, .uflags= INTEL_X86_NCOMBO, }, { .uname = "RFO_I_STATE", .udesc = "L2 demand store RFOs in I state (misses)", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "RFO_E_STATE", .udesc = "L2 demand store RFOs in the E state (exclusive)", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "RFO_M_STATE", .udesc = "L2 demand store RFOs in M state", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "RFO_MESI", .udesc = "All L2 demand store RFOs", .ucode = 0xf00, .uflags= INTEL_X86_NCOMBO, }, { .uname = "RFO_S_STATE", .udesc = "L2 demand store RFOs in S state", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t nhm_large_itlb[]={ { .uname = "HIT", .udesc = "Large ITLB hit", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t nhm_load_dispatch[]={ { .uname = "ANY", .udesc = "All loads dispatched", .ucode = 0x700, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "MOB", .udesc = "Loads dispatched from the MOB", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "RS", .udesc = "Loads dispatched that bypass the MOB", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "RS_DELAYED", .udesc = "Loads dispatched from stage 305", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t nhm_longest_lat_cache[]={ { .uname = "REFERENCE", .udesc = "Longest latency cache reference", .ucode = 0x4f00, .uflags= INTEL_X86_NCOMBO, }, { .uname = "MISS", .udesc = "Longest latency cache miss", .ucode = 0x4100, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t nhm_lsd[]={ { .uname = "ACTIVE", .udesc = "Cycles when uops were delivered by the LSD", .ucode = 0x100 | (0x1 << INTEL_X86_CMASK_BIT), .modhw = _INTEL_X86_ATTR_C, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "INACTIVE", .udesc = "Cycles no uops were delivered by the LSD", .uequiv = "ACTIVE:i=1", .ucode = 0x100 | INTEL_X86_MOD_INV | (0x1 << INTEL_X86_CMASK_BIT), }, }; static const intel_x86_umask_t nhm_machine_clears[]={ { .uname = "SMC", .udesc = "Self-Modifying Code detected", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "CYCLES", .udesc = "Cycles machine clear asserted", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "MEM_ORDER", .udesc = "Execution pipeline restart due to Memory ordering conflicts", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "FUSION_ASSIST", .udesc = "Counts the number of macro-fusion assists", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t nhm_macro_insts[]={ { .uname = "DECODED", .udesc = "Instructions decoded", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "FUSIONS_DECODED", .udesc = "Macro-fused instructions decoded", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t nhm_memory_disambiguation[]={ { .uname = "RESET", .udesc = "Counts memory disambiguation reset cycles", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "WATCHDOG", .udesc = "Counts the number of times the memory disambiguation watchdog kicked in", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "WATCH_CYCLES", .udesc = "Counts the cycles that the memory disambiguation watchdog is active", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t nhm_mem_inst_retired[]={ { .uname = "LATENCY_ABOVE_THRESHOLD", .udesc = "Memory instructions retired above programmed clocks, minimum threshold value is 3, (Precise Event and ldlat required)", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS | INTEL_X86_LDLAT, }, { .uname = "LOADS", .udesc = "Instructions retired which contains a load (Precise Event)", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "STORES", .udesc = "Instructions retired which contains a store (Precise Event)", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, }; static const intel_x86_umask_t nhm_mem_load_retired[]={ { .uname = "DTLB_MISS", .udesc = "Retired loads that miss the DTLB (Precise Event)", .ucode = 0x8000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "HIT_LFB", .udesc = "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)", .ucode = 0x4000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "L1D_HIT", .udesc = "Retired loads that hit the L1 data cache (Precise Event)", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "L2_HIT", .udesc = "Retired loads that hit the L2 cache (Precise Event)", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "L3_MISS", .udesc = "Retired loads that miss the L3 cache (Precise Event)", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "LLC_MISS", .udesc = "This is an alias for L3_MISS", .uequiv = "L3_MISS", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "L3_UNSHARED_HIT", .udesc = "Retired loads that hit valid versions in the L3 cache (Precise Event)", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "LLC_UNSHARED_HIT", .udesc = "This is an alias for L3_UNSHARED_HIT", .uequiv = "L3_UNSHARED_HIT", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "OTHER_CORE_L2_HIT_HITM", .udesc = "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, }; static const intel_x86_umask_t nhm_mem_store_retired[]={ { .uname = "DTLB_MISS", .udesc = "Retired stores that miss the DTLB (Precise Event)", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS | INTEL_X86_DFL, }, }; static const intel_x86_umask_t nhm_mem_uncore_retired[]={ { .uname = "OTHER_CORE_L2_HITM", .udesc = "Load instructions retired that HIT modified data in sibling core (Precise Event)", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "REMOTE_CACHE_LOCAL_HOME_HIT", .udesc = "Load instructions retired remote cache HIT data source (Precise Event)", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "REMOTE_DRAM", .udesc = "Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "LOCAL_DRAM", .udesc = "Load instructions retired with a data source of local DRAM or locally homed remote hitm (Precise Event)", .ucode = 0x2000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "L3_DATA_MISS_UNKNOWN", .udesc = "Load instructions retired where the memory reference missed L3 and data source is unknown (Model 46 only, Precise Event)", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, .umodel = PFM_PMU_INTEL_NHM_EX, }, { .uname = "UNCACHEABLE", .udesc = "Load instructions retired where the memory reference missed L1, L2, L3 caches and to perform I/O (Model 46 only, Precise Event)", .ucode = 0x8000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, .umodel = PFM_PMU_INTEL_NHM_EX, }, }; static const intel_x86_umask_t nhm_offcore_requests[]={ { .uname = "ANY", .udesc = "All offcore requests", .ucode = 0x8000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "ANY_READ", .udesc = "Offcore read requests", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ANY_RFO", .udesc = "Offcore RFO requests", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DEMAND_READ_CODE", .udesc = "Counts number of offcore demand code read requests. Does not count L2 prefetch requests.", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DEMAND_READ_DATA", .udesc = "Offcore demand data read requests", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DEMAND_RFO", .udesc = "Offcore demand RFO requests", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "L1D_WRITEBACK", .udesc = "Offcore L1 data cache writebacks", .ucode = 0x4000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "UNCACHED_MEM", .udesc = "Counts number of offcore uncached memory requests", .ucode = 0x2000, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t nhm_pic_accesses[]={ { .uname = "TPR_READS", .udesc = "Counts number of TPR reads", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "TPR_WRITES", .udesc = "Counts number of TPR writes", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t nhm_rat_stalls[]={ { .uname = "FLAGS", .udesc = "Flag stall cycles", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "REGISTERS", .udesc = "Partial register stall cycles", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ROB_READ_PORT", .udesc = "ROB read port stalls cycles", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "SCOREBOARD", .udesc = "Scoreboard stall cycles", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ANY", .udesc = "All RAT stall cycles", .ucode = 0xf00, .uflags= INTEL_X86_DFL, }, }; static const intel_x86_umask_t nhm_resource_stalls[]={ { .uname = "FPCW", .udesc = "FPU control word write stall cycles", .ucode = 0x2000, }, { .uname = "LOAD", .udesc = "Load buffer stall cycles", .ucode = 0x200, }, { .uname = "MXCSR", .udesc = "MXCSR rename stall cycles", .ucode = 0x4000, }, { .uname = "RS_FULL", .udesc = "Reservation Station full stall cycles", .ucode = 0x400, }, { .uname = "STORE", .udesc = "Store buffer stall cycles", .ucode = 0x800, }, { .uname = "OTHER", .udesc = "Other Resource related stall cycles", .ucode = 0x8000, }, { .uname = "ROB_FULL", .udesc = "ROB full stall cycles", .ucode = 0x1000, }, { .uname = "ANY", .udesc = "Resource related stall cycles", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t nhm_simd_int_128[]={ { .uname = "PACK", .udesc = "128 bit SIMD integer pack operations", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PACKED_ARITH", .udesc = "128 bit SIMD integer arithmetic operations", .ucode = 0x2000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PACKED_LOGICAL", .udesc = "128 bit SIMD integer logical operations", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PACKED_MPY", .udesc = "128 bit SIMD integer multiply operations", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PACKED_SHIFT", .udesc = "128 bit SIMD integer shift operations", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "SHUFFLE_MOVE", .udesc = "128 bit SIMD integer shuffle/move operations", .ucode = 0x4000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "UNPACK", .udesc = "128 bit SIMD integer unpack operations", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t nhm_simd_int_64[]={ { .uname = "PACK", .udesc = "SIMD integer 64 bit pack operations", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PACKED_ARITH", .udesc = "SIMD integer 64 bit arithmetic operations", .ucode = 0x2000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PACKED_LOGICAL", .udesc = "SIMD integer 64 bit logical operations", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PACKED_MPY", .udesc = "SIMD integer 64 bit packed multiply operations", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PACKED_SHIFT", .udesc = "SIMD integer 64 bit shift operations", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "SHUFFLE_MOVE", .udesc = "SIMD integer 64 bit shuffle/move operations", .ucode = 0x4000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "UNPACK", .udesc = "SIMD integer 64 bit unpack operations", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t nhm_snoop_response[]={ { .uname = "HIT", .udesc = "Thread responded HIT to snoop", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "HITE", .udesc = "Thread responded HITE to snoop", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "HITM", .udesc = "Thread responded HITM to snoop", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t nhm_sq_misc[]={ { .uname = "PROMOTION", .udesc = "Counts the number of L2 secondary misses that hit the Super Queue", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PROMOTION_POST_GO", .udesc = "Counts the number of L2 secondary misses during the Super Queue filling L2", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "LRU_HINTS", .udesc = "Counts number of Super Queue LRU hints sent to L3", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "FILL_DROPPED", .udesc = "Counts the number of SQ L2 fills dropped due to L2 busy", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "SPLIT_LOCK", .udesc = "Super Queue lock splits across a cache line", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t nhm_sse_mem_exec[]={ { .uname = "NTA", .udesc = "Streaming SIMD L1D NTA prefetch miss", .ucode = 0x100, .uflags= INTEL_X86_DFL, }, }; static const intel_x86_umask_t nhm_ssex_uops_retired[]={ { .uname = "PACKED_DOUBLE", .udesc = "SIMD Packed-Double Uops retired (Precise Event)", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "PACKED_SINGLE", .udesc = "SIMD Packed-Single Uops retired (Precise Event)", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "SCALAR_DOUBLE", .udesc = "SIMD Scalar-Double Uops retired (Precise Event)", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "SCALAR_SINGLE", .udesc = "SIMD Scalar-Single Uops retired (Precise Event)", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "VECTOR_INTEGER", .udesc = "SIMD Vector Integer Uops retired (Precise Event)", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, }; static const intel_x86_umask_t nhm_store_blocks[]={ { .uname = "AT_RET", .udesc = "Loads delayed with at-Retirement block code", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "L1D_BLOCK", .udesc = "Cacheable loads delayed with L1D block code", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "NOT_STA", .udesc = "Loads delayed due to a store blocked for unknown data", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "STA", .udesc = "Loads delayed due to a store blocked for an unknown address", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t nhm_uops_decoded[]={ { .uname = "ESP_FOLDING", .udesc = "Stack pointer instructions decoded", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ESP_SYNC", .udesc = "Stack pointer sync operations", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "MS", .udesc = "Uops decoded by Microcode Sequencer", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "MS_CYCLES_ACTIVE", .udesc = "Cycles in which at least one uop is decoded by Microcode Sequencer", .uequiv = "MS:c=1", .ucode = 0x200 | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t nhm_uops_executed[]={ { .uname = "PORT0", .udesc = "Uops executed on port 0", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PORT1", .udesc = "Uops executed on port 1", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PORT2_CORE", .udesc = "Uops executed on port 2 on any thread (core count only)", .ucode = 0x400 | INTEL_X86_MOD_ANY, .modhw = _INTEL_X86_ATTR_T, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PORT3_CORE", .udesc = "Uops executed on port 3 on any thread (core count only)", .ucode = 0x800 | INTEL_X86_MOD_ANY, .modhw = _INTEL_X86_ATTR_T, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PORT4_CORE", .udesc = "Uops executed on port 4 on any thread (core count only)", .ucode = 0x1000 | INTEL_X86_MOD_ANY, .modhw = _INTEL_X86_ATTR_T, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PORT5", .udesc = "Uops executed on port 5", .ucode = 0x2000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PORT015", .udesc = "Uops issued on ports 0, 1 or 5", .ucode = 0x4000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PORT234_CORE", .udesc = "Uops issued on ports 2, 3 or 4 on any thread (core count only)", .ucode = 0x8000 | INTEL_X86_MOD_ANY, .modhw = _INTEL_X86_ATTR_T, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PORT015_STALL_CYCLES", .udesc = "Cycles no Uops issued on ports 0, 1 or 5", .uequiv = "PORT015:c=1:i=1", .ucode = 0x4000 | INTEL_X86_MOD_INV | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t nhm_uops_issued[]={ { .uname = "ANY", .udesc = "Uops issued", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "STALLED_CYCLES", .udesc = "Cycles stalled no issued uops", .uequiv = "ANY:c=1:i=1", .ucode = 0x100 | INTEL_X86_MOD_INV | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, }, { .uname = "FUSED", .udesc = "Fused Uops issued", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t nhm_uops_retired[]={ { .uname = "ANY", .udesc = "Uops retired (Precise Event)", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS | INTEL_X86_DFL, }, { .uname = "RETIRE_SLOTS", .udesc = "Retirement slots used (Precise Event)", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "ACTIVE_CYCLES", .udesc = "Cycles Uops are being retired (Precise Event)", .uequiv = "ANY:c=1", .ucode = 0x100 | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "STALL_CYCLES", .udesc = "Cycles No Uops retired (Precise Event)", .uequiv = "ANY:c=1:i=1", .ucode = 0x100 | INTEL_X86_MOD_INV | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "MACRO_FUSED", .udesc = "Macro-fused Uops retired (Precise Event)", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, }; static const intel_x86_umask_t nhm_offcore_response_0[]={ { .uname = "DMND_DATA_RD", .udesc = "Request: counts the number of demand and DCU prefetch data reads of full and partial cachelines as well as demand data page table entry cacheline reads. Does not count L2 data read prefetches or instruction fetches", .ucode = 0x100, .grpid = 0, }, { .uname = "DMND_RFO", .udesc = "Request: counts the number of demand and DCU prefetch reads for ownership (RFO) requests generated by a write to data cacheline. Does not count L2 RFO", .ucode = 0x200, .grpid = 0, }, { .uname = "DMND_IFETCH", .udesc = "Request: counts the number of demand and DCU prefetch instruction cacheline reads. Does not count L2 code read prefetches", .ucode = 0x400, .grpid = 0, }, { .uname = "WB", .udesc = "Request: counts the number of writeback (modified to exclusive) transactions", .ucode = 0x800, .grpid = 0, }, { .uname = "PF_DATA_RD", .udesc = "Request: counts the number of data cacheline reads generated by L2 prefetchers", .ucode = 0x1000, .grpid = 0, }, { .uname = "PF_RFO", .udesc = "Request: counts the number of RFO requests generated by L2 prefetchers", .ucode = 0x2000, .grpid = 0, }, { .uname = "PF_IFETCH", .udesc = "Request: counts the number of code reads generated by L2 prefetchers", .ucode = 0x4000, .grpid = 0, }, { .uname = "OTHER", .udesc = "Request: counts one of the following transaction types, including L3 invalidate, I/O, full or partial writes, WC or non-temporal stores, CLFLUSH, Fences, lock, unlock, split lock", .ucode = 0x8000, .grpid = 0, }, { .uname = "ANY_IFETCH", .udesc = "Request: combination of PF_IFETCH | DMND_IFETCH", .uequiv = "PF_IFETCH:DMND_IFETCH", .ucode = 0x4400, .grpid = 0, }, { .uname = "ANY_REQUEST", .udesc = "Request: combination of all requests umasks", .uequiv = "DMND_DATA_RD:DMND_RFO:DMND_IFETCH:WB:PF_DATA_RD:PF_RFO:PF_IFETCH:OTHER", .ucode = 0xff00, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, .grpid = 0, }, { .uname = "ANY_DATA", .udesc = "Request: any data read/write request", .uequiv = "DMND_DATA_RD:PF_DATA_RD:DMND_RFO:PF_RFO", .ucode = 0x3300, .grpid = 0, }, { .uname = "ANY_DATA_RD", .udesc = "Request: any data read in request", .uequiv = "DMND_DATA_RD:PF_DATA_RD", .ucode = 0x1100, .grpid = 0, }, { .uname = "ANY_RFO", .udesc = "Request: combination of DMND_RFO | PF_RFO", .uequiv = "DMND_RFO:PF_RFO", .ucode = 0x2200, .grpid = 0, }, { .uname = "UNCORE_HIT", .udesc = "Response: counts L3 Hit: local or remote home requests that hit L3 cache in the uncore with no coherency actions required (snooping)", .ucode = 0x10000, .grpid = 1, }, { .uname = "OTHER_CORE_HIT_SNP", .udesc = "Response: counts L3 Hit: local or remote home requests that hit L3 cache in the uncore and was serviced by another core with a cross core snoop where no modified copies were found (clean)", .ucode = 0x20000, .grpid = 1, }, { .uname = "OTHER_CORE_HITM", .udesc = "Response: counts L3 Hit: local or remote home requests that hit L3 cache in the uncore and was serviced by another core with a cross core snoop where modified copies were found (HITM)", .ucode = 0x40000, .grpid = 1, }, { .uname = "REMOTE_CACHE_HITM", .udesc = "Response: counts L3 Hit: local or remote home requests that hit a remote L3 cacheline in modified (HITM) state", .ucode = 0x80000, .grpid = 1, }, { .uname = "REMOTE_CACHE_FWD", .udesc = "Response: counts L3 Miss: local homed requests that missed the L3 cache and was serviced by forwarded data following a cross package snoop where no modified copies found. (Remote home requests are not counted)", .ucode = 0x100000, .grpid = 1, }, { .uname = "REMOTE_DRAM", .udesc = "Response: counts L3 Miss: remote home requests that missed the L3 cache and were serviced by remote DRAM", .ucode = 0x200000, .grpid = 1, }, { .uname = "LOCAL_DRAM", .udesc = "Response: counts L3 Miss: local home requests that missed the L3 cache and were serviced by local DRAM", .ucode = 0x400000, .grpid = 1, }, { .uname = "NON_DRAM", .udesc = "Response: Non-DRAM requests that were serviced by IOH", .ucode = 0x800000, .grpid = 1, }, { .uname = "ANY_CACHE_DRAM", .udesc = "Response: requests serviced by any source but IOH", .uequiv = "UNCORE_HIT:OTHER_CORE_HIT_SNP:OTHER_CORE_HITM:REMOTE_CACHE_FWD:REMOTE_CACHE_HITM:REMOTE_DRAM:LOCAL_DRAM", .ucode = 0x7f0000, .grpid = 1, }, { .uname = "ANY_DRAM", .udesc = "Response: requests serviced by local or remote DRAM", .uequiv = "REMOTE_DRAM:LOCAL_DRAM", .ucode = 0x600000, .grpid = 1, }, { .uname = "ANY_LLC_MISS", .udesc = "Response: requests that missed in L3", .uequiv = "REMOTE_CACHE_HITM:REMOTE_CACHE_FWD:REMOTE_DRAM:LOCAL_DRAM:NON_DRAM", .ucode = 0xf80000, .grpid = 1, }, { .uname = "LOCAL_CACHE_DRAM", .udesc = "Response: requests hit local core or uncore caches or local DRAM", .uequiv = "UNCORE_HIT:OTHER_CORE_HIT_SNP:OTHER_CORE_HITM:LOCAL_DRAM", .ucode = 0x470000, .grpid = 1, }, { .uname = "REMOTE_CACHE_DRAM", .udesc = "Response: requests that miss L3 and hit remote caches or DRAM", .uequiv = "REMOTE_CACHE_HITM:REMOTE_CACHE_FWD:REMOTE_DRAM", .ucode = 0x380000, .grpid = 1, }, { .uname = "ANY_RESPONSE", .udesc = "Response: combination of all response umasks", .uequiv = "UNCORE_HIT:OTHER_CORE_HIT_SNP:OTHER_CORE_HITM:REMOTE_CACHE_FWD:REMOTE_CACHE_HITM:REMOTE_DRAM:LOCAL_DRAM:NON_DRAM", .ucode = 0xff0000, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, .grpid = 1, }, }; static const intel_x86_entry_t intel_nhm_pe[]={ { .name = "UNHALTED_CORE_CYCLES", .desc = "Count core clock cycles whenever the clock signal on the specific core is running (not halted)", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x20000000full, .code = 0x3c, }, { .name = "INSTRUCTION_RETIRED", .desc = "Count the number of instructions at retirement", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x10000000full, .code = 0xc0, }, { .name = "INSTRUCTIONS_RETIRED", .desc = "This is an alias for INSTRUCTION_RETIRED", .modmsk = INTEL_V3_ATTRS, .equiv = "INSTRUCTION_RETIRED", .cntmsk = 0x10000000full, .code = 0xc0, }, { .name = "UNHALTED_REFERENCE_CYCLES", .desc = "Unhalted reference cycles", .modmsk = INTEL_FIXED3_ATTRS, .cntmsk = 0x400000000ull, .code = 0x0300, /* pseudo encoding */ .flags = INTEL_X86_FIXED, }, { .name = "LLC_REFERENCES", .desc = "Count each request originating equiv the core to reference a cache line in the last level cache. The count may include speculation, but excludes cache line fills due to hardware prefetch. Alias to L2_RQSTS:SELF_DEMAND_MESI", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x4f2e, }, { .name = "LAST_LEVEL_CACHE_REFERENCES", .desc = "This is an alias for LLC_REFERENCES", .modmsk = INTEL_V3_ATTRS, .equiv = "LLC_REFERENCES", .cntmsk = 0xf, .code = 0x4f2e, }, { .name = "LLC_MISSES", .desc = "Count each cache miss condition for references to the last level cache. The event count may include speculation, but excludes cache line fills due to hardware prefetch. Alias to event L2_RQSTS:SELF_DEMAND_I_STATE", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x412e, }, { .name = "LAST_LEVEL_CACHE_MISSES", .desc = "This is an equiv for LLC_MISSES", .modmsk = INTEL_V3_ATTRS, .equiv = "LLC_MISSES", .cntmsk = 0xf, .code = 0x412e, }, { .name = "BRANCH_INSTRUCTIONS_RETIRED", .desc = "Count branch instructions at retirement. Specifically, this event counts the retirement of the last micro-op of a branch instruction.", .modmsk = INTEL_V3_ATTRS, .equiv = "BR_INST_RETIRED:ALL_BRANCHES", .cntmsk = 0xf, .code = 0xc4, }, { .name = "ARITH", .desc = "Counts arithmetic multiply and divide operations", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x14, .numasks = LIBPFM_ARRAY_SIZE(nhm_arith), .ngrp = 1, .umasks = nhm_arith, }, { .name = "BACLEAR", .desc = "Branch address calculator", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0xe6, .numasks = LIBPFM_ARRAY_SIZE(nhm_baclear), .ngrp = 1, .umasks = nhm_baclear, }, { .name = "BACLEAR_FORCE_IQ", .desc = "Instruction queue forced BACLEAR", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x1a7, }, { .name = "BOGUS_BR", .desc = "Counts the number of bogus branches.", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x1e4, }, { .name = "BPU_CLEARS", .desc = "Branch prediction Unit clears", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0xe8, .numasks = LIBPFM_ARRAY_SIZE(nhm_bpu_clears), .ngrp = 1, .umasks = nhm_bpu_clears, }, { .name = "BPU_MISSED_CALL_RET", .desc = "Branch prediction unit missed call or return", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x1e5, }, { .name = "BR_INST_DECODED", .desc = "Branch instructions decoded", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x1e0, }, { .name = "BR_INST_EXEC", .desc = "Branch instructions executed", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x88, .numasks = LIBPFM_ARRAY_SIZE(nhm_br_inst_exec), .ngrp = 1, .umasks = nhm_br_inst_exec, }, { .name = "BR_INST_RETIRED", .desc = "Retired branch instructions", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0xc4, .flags= INTEL_X86_PEBS, .numasks = LIBPFM_ARRAY_SIZE(nhm_br_inst_retired), .ngrp = 1, .umasks = nhm_br_inst_retired, }, { .name = "BR_MISP_EXEC", .desc = "Mispredicted branches executed", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x89, .numasks = LIBPFM_ARRAY_SIZE(nhm_br_misp_exec), .ngrp = 1, .umasks = nhm_br_misp_exec, }, { .name = "BR_MISP_RETIRED", .desc = "Count Mispredicted Branch Activity", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0xc5, .flags= INTEL_X86_PEBS, .numasks = LIBPFM_ARRAY_SIZE(nhm_br_misp_retired), .ngrp = 1, .umasks = nhm_br_misp_retired, }, { .name = "CACHE_LOCK_CYCLES", .desc = "Cache lock cycles", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x63, .numasks = LIBPFM_ARRAY_SIZE(nhm_cache_lock_cycles), .ngrp = 1, .umasks = nhm_cache_lock_cycles, }, { .name = "CPU_CLK_UNHALTED", .desc = "Cycles when processor is not in halted state", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x3c, .numasks = LIBPFM_ARRAY_SIZE(nhm_cpu_clk_unhalted), .ngrp = 1, .umasks = nhm_cpu_clk_unhalted, }, { .name = "DTLB_LOAD_MISSES", .desc = "Data TLB load misses", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x8, .numasks = LIBPFM_ARRAY_SIZE(nhm_dtlb_load_misses), .ngrp = 1, .umasks = nhm_dtlb_load_misses, }, { .name = "DTLB_MISSES", .desc = "Data TLB misses", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x49, .numasks = LIBPFM_ARRAY_SIZE(nhm_dtlb_misses), .ngrp = 1, .umasks = nhm_dtlb_misses, }, { .name = "EPT", .desc = "Extended Page Directory", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x4f, .numasks = LIBPFM_ARRAY_SIZE(nhm_ept), .ngrp = 1, .umasks = nhm_ept, }, { .name = "ES_REG_RENAMES", .desc = "ES segment renames", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x1d5, }, { .name = "FP_ASSIST", .desc = "Floating point assists", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0xf7, .flags= INTEL_X86_PEBS, .numasks = LIBPFM_ARRAY_SIZE(nhm_fp_assist), .ngrp = 1, .umasks = nhm_fp_assist, }, { .name = "FP_COMP_OPS_EXE", .desc = "Floating point computational micro-ops", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x10, .numasks = LIBPFM_ARRAY_SIZE(nhm_fp_comp_ops_exe), .ngrp = 1, .umasks = nhm_fp_comp_ops_exe, }, { .name = "FP_MMX_TRANS", .desc = "Floating Point to and from MMX transitions", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0xcc, .numasks = LIBPFM_ARRAY_SIZE(nhm_fp_mmx_trans), .ngrp = 1, .umasks = nhm_fp_mmx_trans, }, { .name = "IFU_IVC", .desc = "Instruction Fetch unit victim cache", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x81, .numasks = LIBPFM_ARRAY_SIZE(nhm_ifu_ivc), .ngrp = 1, .umasks = nhm_ifu_ivc, }, { .name = "ILD_STALL", .desc = "Instruction Length Decoder stalls", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x87, .numasks = LIBPFM_ARRAY_SIZE(nhm_ild_stall), .ngrp = 1, .umasks = nhm_ild_stall, }, { .name = "INST_DECODED", .desc = "Instructions decoded", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x18, .numasks = LIBPFM_ARRAY_SIZE(nhm_inst_decoded), .ngrp = 1, .umasks = nhm_inst_decoded, }, { .name = "INST_QUEUE_WRITES", .desc = "Instructions written to instruction queue.", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x117, }, { .name = "INST_QUEUE_WRITE_CYCLES", .desc = "Cycles instructions are written to the instruction queue", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x11e, }, { .name = "INST_RETIRED", .desc = "Instructions retired", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0xc0, .flags= INTEL_X86_PEBS, .numasks = LIBPFM_ARRAY_SIZE(nhm_inst_retired), .ngrp = 1, .umasks = nhm_inst_retired, }, { .name = "IO_TRANSACTIONS", .desc = "I/O transactions", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x16c, }, { .name = "ITLB_FLUSH", .desc = "Counts the number of ITLB flushes", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x1ae, }, { .name = "ITLB_MISSES", .desc = "Instruction TLB misses", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x85, .numasks = LIBPFM_ARRAY_SIZE(nhm_dtlb_misses), .ngrp = 1, .umasks = nhm_dtlb_misses, /* identical to actual umasks list for this event */ }, { .name = "ITLB_MISS_RETIRED", .desc = "Retired instructions that missed the ITLB (Precise Event)", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x20c8, .flags= INTEL_X86_PEBS, }, { .name = "L1D", .desc = "L1D cache", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x51, .numasks = LIBPFM_ARRAY_SIZE(nhm_l1d), .ngrp = 1, .umasks = nhm_l1d, }, { .name = "L1D_ALL_REF", .desc = "L1D references", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x43, .numasks = LIBPFM_ARRAY_SIZE(nhm_l1d_all_ref), .ngrp = 1, .umasks = nhm_l1d_all_ref, }, { .name = "L1D_CACHE_LD", .desc = "L1D cacheable loads. WARNING: event may overcount loads", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x40, .numasks = LIBPFM_ARRAY_SIZE(nhm_l1d_cache_ld), .ngrp = 1, .umasks = nhm_l1d_cache_ld, }, { .name = "L1D_CACHE_LOCK", .desc = "L1 data cache load lock", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x42, .numasks = LIBPFM_ARRAY_SIZE(nhm_l1d_cache_lock), .ngrp = 1, .umasks = nhm_l1d_cache_lock, }, { .name = "L1D_CACHE_LOCK_FB_HIT", .desc = "L1D load lock accepted in fill buffer", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x153, }, { .name = "L1D_CACHE_PREFETCH_LOCK_FB_HIT", .desc = "L1D prefetch load lock accepted in fill buffer", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x152, }, { .name = "L1D_CACHE_ST", .desc = "L1 data cache stores", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x41, .numasks = LIBPFM_ARRAY_SIZE(nhm_l1d_cache_st), .ngrp = 1, .umasks = nhm_l1d_cache_st, }, { .name = "L1D_PREFETCH", .desc = "L1D hardware prefetch", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x4e, .numasks = LIBPFM_ARRAY_SIZE(nhm_l1d_prefetch), .ngrp = 1, .umasks = nhm_l1d_prefetch, }, { .name = "L1D_WB_L2", .desc = "L1 writebacks to L2", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x28, .numasks = LIBPFM_ARRAY_SIZE(nhm_l1d_wb_l2), .ngrp = 1, .umasks = nhm_l1d_wb_l2, }, { .name = "L1I", .desc = "L1I instruction fetches", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x80, .numasks = LIBPFM_ARRAY_SIZE(nhm_l1i), .ngrp = 1, .umasks = nhm_l1i, }, { .name = "L1I_OPPORTUNISTIC_HITS", .desc = "Opportunistic hits in streaming", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x183, }, { .name = "L2_DATA_RQSTS", .desc = "L2 data requests", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x26, .numasks = LIBPFM_ARRAY_SIZE(nhm_l2_data_rqsts), .ngrp = 1, .umasks = nhm_l2_data_rqsts, }, { .name = "L2_HW_PREFETCH", .desc = "L2 HW prefetches", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0xf3, .numasks = LIBPFM_ARRAY_SIZE(nhm_l2_hw_prefetch), .ngrp = 1, .umasks = nhm_l2_hw_prefetch, }, { .name = "L2_LINES_IN", .desc = "L2 lines allocated", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0xf1, .numasks = LIBPFM_ARRAY_SIZE(nhm_l2_lines_in), .ngrp = 1, .umasks = nhm_l2_lines_in, }, { .name = "L2_LINES_OUT", .desc = "L2 lines evicted", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0xf2, .numasks = LIBPFM_ARRAY_SIZE(nhm_l2_lines_out), .ngrp = 1, .umasks = nhm_l2_lines_out, }, { .name = "L2_RQSTS", .desc = "L2 requests", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x24, .numasks = LIBPFM_ARRAY_SIZE(nhm_l2_rqsts), .ngrp = 1, .umasks = nhm_l2_rqsts, }, { .name = "L2_TRANSACTIONS", .desc = "L2 transactions", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0xf0, .numasks = LIBPFM_ARRAY_SIZE(nhm_l2_transactions), .ngrp = 1, .umasks = nhm_l2_transactions, }, { .name = "L2_WRITE", .desc = "L2 demand lock/store RFO", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x27, .numasks = LIBPFM_ARRAY_SIZE(nhm_l2_write), .ngrp = 1, .umasks = nhm_l2_write, }, { .name = "LARGE_ITLB", .desc = "Large instruction TLB", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x82, .numasks = LIBPFM_ARRAY_SIZE(nhm_large_itlb), .ngrp = 1, .umasks = nhm_large_itlb, }, { .name = "LOAD_DISPATCH", .desc = "Loads dispatched", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x13, .numasks = LIBPFM_ARRAY_SIZE(nhm_load_dispatch), .ngrp = 1, .umasks = nhm_load_dispatch, }, { .name = "LOAD_HIT_PRE", .desc = "Load operations conflicting with software prefetches", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x3, .code = 0x14c, }, { .name = "LONGEST_LAT_CACHE", .desc = "Longest latency cache reference", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x2e, .numasks = LIBPFM_ARRAY_SIZE(nhm_longest_lat_cache), .ngrp = 1, .umasks = nhm_longest_lat_cache, }, { .name = "LSD", .desc = "Loop stream detector", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0xa8, .numasks = LIBPFM_ARRAY_SIZE(nhm_lsd), .ngrp = 1, .umasks = nhm_lsd, }, { .name = "MACHINE_CLEARS", .desc = "Machine Clear", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0xc3, .numasks = LIBPFM_ARRAY_SIZE(nhm_machine_clears), .ngrp = 1, .umasks = nhm_machine_clears, }, { .name = "MACRO_INSTS", .desc = "Macro-fused instructions", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0xd0, .numasks = LIBPFM_ARRAY_SIZE(nhm_macro_insts), .ngrp = 1, .umasks = nhm_macro_insts, }, { .name = "MEMORY_DISAMBIGUATION", .desc = "Memory Disambiguation Activity", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x9, .numasks = LIBPFM_ARRAY_SIZE(nhm_memory_disambiguation), .ngrp = 1, .umasks = nhm_memory_disambiguation, }, { .name = "MEM_INST_RETIRED", .desc = "Memory instructions retired", .modmsk = INTEL_V3_ATTRS | _INTEL_X86_ATTR_LDLAT, .cntmsk = 0xf, .code = 0xb, .flags= INTEL_X86_PEBS, .numasks = LIBPFM_ARRAY_SIZE(nhm_mem_inst_retired), .ngrp = 1, .umasks = nhm_mem_inst_retired, }, { .name = "MEM_LOAD_RETIRED", .desc = "Retired loads", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0xcb, .flags= INTEL_X86_PEBS, .numasks = LIBPFM_ARRAY_SIZE(nhm_mem_load_retired), .ngrp = 1, .umasks = nhm_mem_load_retired, }, { .name = "MEM_STORE_RETIRED", .desc = "Retired stores", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0xc, .flags= INTEL_X86_PEBS, .numasks = LIBPFM_ARRAY_SIZE(nhm_mem_store_retired), .ngrp = 1, .umasks = nhm_mem_store_retired, }, { .name = "MEM_UNCORE_RETIRED", .desc = "Load instructions retired which hit offcore", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0xf, .flags= INTEL_X86_PEBS, .numasks = LIBPFM_ARRAY_SIZE(nhm_mem_uncore_retired), .ngrp = 1, .umasks = nhm_mem_uncore_retired, }, { .name = "OFFCORE_REQUESTS", .desc = "Offcore memory requests", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0xb0, .numasks = LIBPFM_ARRAY_SIZE(nhm_offcore_requests), .ngrp = 1, .umasks = nhm_offcore_requests, }, { .name = "OFFCORE_REQUESTS_SQ_FULL", .desc = "Counts cycles the Offcore Request buffer or Super Queue is full.", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x1b2, }, { .name = "PARTIAL_ADDRESS_ALIAS", .desc = "False dependencies due to partial address forming", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x107, }, { .name = "PIC_ACCESSES", .desc = "Programmable interrupt controller", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0xba, .numasks = LIBPFM_ARRAY_SIZE(nhm_pic_accesses), .ngrp = 1, .umasks = nhm_pic_accesses, }, { .name = "RAT_STALLS", .desc = "Register allocation table stalls", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0xd2, .numasks = LIBPFM_ARRAY_SIZE(nhm_rat_stalls), .ngrp = 1, .umasks = nhm_rat_stalls, }, { .name = "RESOURCE_STALLS", .desc = "Processor stalls", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0xa2, .numasks = LIBPFM_ARRAY_SIZE(nhm_resource_stalls), .ngrp = 1, .umasks = nhm_resource_stalls, }, { .name = "SEG_RENAME_STALLS", .desc = "Segment rename stall cycles", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x1d4, }, { .name = "SEGMENT_REG_LOADS", .desc = "Counts number of segment register loads", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x1f8, }, { .name = "SIMD_INT_128", .desc = "128 bit SIMD integer operations", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x12, .numasks = LIBPFM_ARRAY_SIZE(nhm_simd_int_128), .ngrp = 1, .umasks = nhm_simd_int_128, }, { .name = "SIMD_INT_64", .desc = "64 bit SIMD integer operations", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0xfd, .numasks = LIBPFM_ARRAY_SIZE(nhm_simd_int_64), .ngrp = 1, .umasks = nhm_simd_int_64, }, { .name = "SNOOP_RESPONSE", .desc = "Snoop", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0xb8, .numasks = LIBPFM_ARRAY_SIZE(nhm_snoop_response), .ngrp = 1, .umasks = nhm_snoop_response, }, { .name = "SQ_FULL_STALL_CYCLES", .desc = "Counts cycles the Offcore Request buffer or Super Queue is full and request(s) are outstanding.", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x1f6, }, { .name = "SQ_MISC", .desc = "Super Queue Activity Related to L2 Cache Access", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0xf4, .numasks = LIBPFM_ARRAY_SIZE(nhm_sq_misc), .ngrp = 1, .umasks = nhm_sq_misc, }, { .name = "SSE_MEM_EXEC", .desc = "Streaming SIMD executed", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x4b, .numasks = LIBPFM_ARRAY_SIZE(nhm_sse_mem_exec), .ngrp = 1, .umasks = nhm_sse_mem_exec, }, { .name = "SSEX_UOPS_RETIRED", .desc = "SIMD micro-ops retired", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0xc7, .flags= INTEL_X86_PEBS, .numasks = LIBPFM_ARRAY_SIZE(nhm_ssex_uops_retired), .ngrp = 1, .umasks = nhm_ssex_uops_retired, }, { .name = "STORE_BLOCKS", .desc = "Delayed loads", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x6, .numasks = LIBPFM_ARRAY_SIZE(nhm_store_blocks), .ngrp = 1, .umasks = nhm_store_blocks, }, { .name = "TWO_UOP_INSTS_DECODED", .desc = "Two micro-ops instructions decoded", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x119, }, { .name = "UOPS_DECODED_DEC0", .desc = "Micro-ops decoded by decoder 0", .modmsk =0x0, .cntmsk = 0xf, .code = 0x13d, }, { .name = "UOPS_DECODED", .desc = "Micro-ops decoded", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0xd1, .numasks = LIBPFM_ARRAY_SIZE(nhm_uops_decoded), .ngrp = 1, .umasks = nhm_uops_decoded, }, { .name = "UOPS_EXECUTED", .desc = "Micro-ops executed", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0xb1, .numasks = LIBPFM_ARRAY_SIZE(nhm_uops_executed), .ngrp = 1, .umasks = nhm_uops_executed, }, { .name = "UOPS_ISSUED", .desc = "Micro-ops issued", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0xe, .numasks = LIBPFM_ARRAY_SIZE(nhm_uops_issued), .ngrp = 1, .umasks = nhm_uops_issued, }, { .name = "UOPS_RETIRED", .desc = "Micro-ops retired", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0xc2, .flags= INTEL_X86_PEBS, .numasks = LIBPFM_ARRAY_SIZE(nhm_uops_retired), .ngrp = 1, .umasks = nhm_uops_retired, }, { .name = "UOP_UNFUSION", .desc = "Micro-ops unfusions due to FP exceptions", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x1db, }, { .name = "OFFCORE_RESPONSE_0", .desc = "Offcore response 0 (must provide at least one request and one response umasks)", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x1b7, .flags= INTEL_X86_NHM_OFFCORE, .numasks = LIBPFM_ARRAY_SIZE(nhm_offcore_response_0), .ngrp = 2, .umasks = nhm_offcore_response_0, }, }; libpfm-4.9.0/lib/events/intel_bdx_unc_irp_events.h0000664000175000017500000003220013223402656022111 0ustar eranianeranian/* * Copyright (c) 2017 Google Inc. All rights reserved * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * PMU: bdx_unc_irp */ static intel_x86_umask_t bdx_unc_i_cache_total_occupancy[]={ { .uname = "ANY", .ucode = 0x100, .udesc = "Total Write Cache Occupancy -- Any Source", .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "SOURCE", .ucode = 0x200, .udesc = "Total Write Cache Occupancy -- Select Source", .uflags = INTEL_X86_NCOMBO, }, }; static intel_x86_umask_t bdx_unc_i_coherent_ops[]={ { .uname = "CLFLUSH", .ucode = 0x8000, .udesc = "Coherent Ops -- CLFlush", .uflags = INTEL_X86_NCOMBO, }, { .uname = "CRD", .ucode = 0x200, .udesc = "Coherent Ops -- CRd", .uflags = INTEL_X86_NCOMBO, }, { .uname = "DRD", .ucode = 0x400, .udesc = "Coherent Ops -- DRd", .uflags = INTEL_X86_NCOMBO, }, { .uname = "PCIDCAHINT", .ucode = 0x2000, .udesc = "Coherent Ops -- PCIDCAHin5t", .uflags = INTEL_X86_NCOMBO, }, { .uname = "PCIRDCUR", .ucode = 0x100, .udesc = "Coherent Ops -- PCIRdCur", .uflags = INTEL_X86_NCOMBO, }, { .uname = "PCITOM", .ucode = 0x1000, .udesc = "Coherent Ops -- PCIItoM", .uflags = INTEL_X86_NCOMBO, }, { .uname = "RFO", .ucode = 0x800, .udesc = "Coherent Ops -- RFO", .uflags = INTEL_X86_NCOMBO, }, { .uname = "WBMTOI", .ucode = 0x4000, .udesc = "Coherent Ops -- WbMtoI", .uflags = INTEL_X86_NCOMBO, }, }; static intel_x86_umask_t bdx_unc_i_misc0[]={ { .uname = "2ND_ATOMIC_INSERT", .ucode = 0x1000, .udesc = "Misc Events - Set 0 -- Cache Inserts of Atomic Transactions as Secondary", .uflags = INTEL_X86_NCOMBO, }, { .uname = "2ND_RD_INSERT", .ucode = 0x400, .udesc = "Misc Events - Set 0 -- Cache Inserts of Read Transactions as Secondary", .uflags = INTEL_X86_NCOMBO, }, { .uname = "2ND_WR_INSERT", .ucode = 0x800, .udesc = "Misc Events - Set 0 -- Cache Inserts of Write Transactions as Secondary", .uflags = INTEL_X86_NCOMBO, }, { .uname = "FAST_REJ", .ucode = 0x200, .udesc = "Misc Events - Set 0 -- Fastpath Rejects", .uflags = INTEL_X86_NCOMBO, }, { .uname = "FAST_REQ", .ucode = 0x100, .udesc = "Misc Events - Set 0 -- Fastpath Requests", .uflags = INTEL_X86_NCOMBO, }, { .uname = "FAST_XFER", .ucode = 0x2000, .udesc = "Misc Events - Set 0 -- Fastpath Transfers From Primary to Secondary", .uflags = INTEL_X86_NCOMBO, }, { .uname = "PF_ACK_HINT", .ucode = 0x4000, .udesc = "Misc Events - Set 0 -- Prefetch Ack Hints From Primary to Secondary", .uflags = INTEL_X86_NCOMBO, }, { .uname = "PF_TIMEOUT", .ucode = 0x8000, .udesc = "Misc Events - Set 0 -- Prefetch TimeOut", .uflags = INTEL_X86_NCOMBO, }, }; static intel_x86_umask_t bdx_unc_i_misc1[]={ { .uname = "DATA_THROTTLE", .ucode = 0x8000, .udesc = "Misc Events - Set 1 -- Data Throttled", .uflags = INTEL_X86_NCOMBO, }, { .uname = "LOST_FWD", .ucode = 0x1000, .udesc = "Misc Events - Set 1 -- ", .uflags = INTEL_X86_NCOMBO, }, { .uname = "SEC_RCVD_INVLD", .ucode = 0x2000, .udesc = "Misc Events - Set 1 -- Received Invalid", .uflags = INTEL_X86_NCOMBO, }, { .uname = "SEC_RCVD_VLD", .ucode = 0x4000, .udesc = "Misc Events - Set 1 -- Received Valid", .uflags = INTEL_X86_NCOMBO, }, { .uname = "SLOW_I", .ucode = 0x100, .udesc = "Misc Events - Set 1 -- Slow Transfer of I Line", .uflags = INTEL_X86_NCOMBO, }, { .uname = "SLOW_S", .ucode = 0x200, .udesc = "Misc Events - Set 1 -- Slow Transfer of S Line", .uflags = INTEL_X86_NCOMBO, }, { .uname = "SLOW_E", .ucode = 0x400, .udesc = "Misc Events - Set 1 -- Slow Transfer of E Line", .uflags = INTEL_X86_NCOMBO, }, { .uname = "SLOW_M", .ucode = 0x800, .udesc = "Misc Events - Set 1 -- Slow Transfer of M Line", .uflags = INTEL_X86_NCOMBO, }, }; static intel_x86_umask_t bdx_unc_i_snoop_resp[]={ { .uname = "HIT_ES", .ucode = 0x400, .udesc = "Snoop Responses -- Hit E or S", }, { .uname = "HIT_I", .ucode = 0x200, .udesc = "Snoop Responses -- Hit I", }, { .uname = "HIT_M", .ucode = 0x800, .udesc = "Snoop Responses -- Hit M", }, { .uname = "MISS", .ucode = 0x100, .udesc = "Snoop Responses -- Miss", }, { .uname = "SNPCODE", .ucode = 0x1000, .udesc = "Snoop Responses -- SnpCode", }, { .uname = "SNPDATA", .ucode = 0x2000, .udesc = "Snoop Responses -- SnpData", }, { .uname = "SNPINV", .ucode = 0x4000, .udesc = "Snoop Responses -- SnpInv", }, }; static intel_x86_umask_t bdx_unc_i_transactions[]={ { .uname = "ATOMIC", .ucode = 0x1000, .udesc = "Inbound Transaction Count -- Atomic", }, { .uname = "ORDERINGQ", .ucode = 0x4000, .udesc = "Inbound Transaction Count -- Select Source via IRP orderingQ register", }, { .uname = "OTHER", .ucode = 0x2000, .udesc = "Inbound Transaction Count -- Other", }, { .uname = "RD_PREF", .ucode = 0x400, .udesc = "Inbound Transaction Count -- Read Prefetches", }, { .uname = "READS", .ucode = 0x100, .udesc = "Inbound Transaction Count -- Reads", }, { .uname = "WRITES", .ucode = 0x200, .udesc = "Inbound Transaction Count -- Writes", }, { .uname = "WR_PREF", .ucode = 0x800, .udesc = "Inbound Transaction Count -- Write Prefetches", }, }; static intel_x86_entry_t intel_bdx_unc_i_pe[]={ { .name = "UNC_I_CACHE_TOTAL_OCCUPANCY", .code = 0x12, .desc = "Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.", .modmsk = BDX_UNC_IRP_ATTRS, .cntmsk = 0x3, .ngrp = 1, .umasks = bdx_unc_i_cache_total_occupancy, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_i_cache_total_occupancy), }, { .name = "UNC_I_CLOCKTICKS", .code = 0x0, .desc = "Number of clocks in the IRP.", .modmsk = BDX_UNC_IRP_ATTRS, .cntmsk = 0x3, }, { .name = "UNC_I_COHERENT_OPS", .code = 0x13, .desc = "Counts the number of coherency related operations servied by the IRP", .modmsk = BDX_UNC_IRP_ATTRS, .cntmsk = 0x3, .ngrp = 1, .umasks = bdx_unc_i_coherent_ops, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_i_coherent_ops), }, { .name = "UNC_I_MISC0", .code = 0x14, .desc = "", .modmsk = BDX_UNC_IRP_ATTRS, .cntmsk = 0x3, .ngrp = 1, .umasks = bdx_unc_i_misc0, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_i_misc0), }, { .name = "UNC_I_MISC1", .code = 0x15, .desc = "", .modmsk = BDX_UNC_IRP_ATTRS, .cntmsk = 0x3, .ngrp = 1, .umasks = bdx_unc_i_misc1, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_i_misc1), }, { .name = "UNC_I_RXR_AK_INSERTS", .code = 0xa, .desc = "Counts the number of allocations into the AK Ingress. This queue is where the IRP receives responses from R2PCIe (the ring).", .modmsk = BDX_UNC_IRP_ATTRS, .cntmsk = 0x3, }, { .name = "UNC_I_RXR_BL_DRS_CYCLES_FULL", .code = 0x4, .desc = "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", .modmsk = BDX_UNC_IRP_ATTRS, .cntmsk = 0x3, }, { .name = "UNC_I_RXR_BL_DRS_INSERTS", .code = 0x1, .desc = "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", .modmsk = BDX_UNC_IRP_ATTRS, .cntmsk = 0x3, }, { .name = "UNC_I_RXR_BL_DRS_OCCUPANCY", .code = 0x7, .desc = "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", .modmsk = BDX_UNC_IRP_ATTRS, .cntmsk = 0x3, }, { .name = "UNC_I_RXR_BL_NCB_CYCLES_FULL", .code = 0x5, .desc = "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", .modmsk = BDX_UNC_IRP_ATTRS, .cntmsk = 0x3, }, { .name = "UNC_I_RXR_BL_NCB_INSERTS", .code = 0x2, .desc = "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", .modmsk = BDX_UNC_IRP_ATTRS, .cntmsk = 0x3, }, { .name = "UNC_I_RXR_BL_NCB_OCCUPANCY", .code = 0x8, .desc = "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", .modmsk = BDX_UNC_IRP_ATTRS, .cntmsk = 0x3, }, { .name = "UNC_I_RXR_BL_NCS_CYCLES_FULL", .code = 0x6, .desc = "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", .modmsk = BDX_UNC_IRP_ATTRS, .cntmsk = 0x3, }, { .name = "UNC_I_RXR_BL_NCS_INSERTS", .code = 0x3, .desc = "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", .modmsk = BDX_UNC_IRP_ATTRS, .cntmsk = 0x3, }, { .name = "UNC_I_RXR_BL_NCS_OCCUPANCY", .code = 0x9, .desc = "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", .modmsk = BDX_UNC_IRP_ATTRS, .cntmsk = 0x3, }, { .name = "UNC_I_SNOOP_RESP", .code = 0x17, .desc = "", .modmsk = BDX_UNC_IRP_ATTRS, .cntmsk = 0x3, .ngrp = 1, .umasks = bdx_unc_i_snoop_resp, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_i_snoop_resp), }, { .name = "UNC_I_TRANSACTIONS", .code = 0x16, .desc = "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portItID.", .modmsk = BDX_UNC_IRP_ATTRS, .cntmsk = 0x3, .ngrp = 1, .umasks = bdx_unc_i_transactions, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_i_transactions), }, { .name = "UNC_I_TXR_AD_STALL_CREDIT_CYCLES", .code = 0x18, .desc = "Counts the number times when it is not possible to issue a request to the R2PCIe because there are no AD Egress Credits available.", .modmsk = BDX_UNC_IRP_ATTRS, .cntmsk = 0x3, }, { .name = "UNC_I_TXR_BL_STALL_CREDIT_CYCLES", .code = 0x19, .desc = "Counts the number times when it is not possible to issue data to the R2PCIe because there are no BL Egress Credits available.", .modmsk = BDX_UNC_IRP_ATTRS, .cntmsk = 0x3, }, { .name = "UNC_I_TXR_DATA_INSERTS_NCB", .code = 0xe, .desc = "Counts the number of requests issued to the switch (towards the devices).", .modmsk = BDX_UNC_IRP_ATTRS, .cntmsk = 0x3, }, { .name = "UNC_I_TXR_DATA_INSERTS_NCS", .code = 0xf, .desc = "Counts the number of requests issued to the switch (towards the devices).", .modmsk = BDX_UNC_IRP_ATTRS, .cntmsk = 0x3, }, { .name = "UNC_I_TXR_REQUEST_OCCUPANCY", .code = 0xd, .desc = "Accumultes the number of outstanding outbound requests from the IRP to the switch (towards the devices). This can be used in conjuection with the allocations event in order to calculate average latency of outbound requests.", .modmsk = BDX_UNC_IRP_ATTRS, .cntmsk = 0x3, }, }; libpfm-4.9.0/lib/events/powerpc_nest_events.h0000664000175000017500000000442113223402656021136 0ustar eranianeranian#ifndef __POWERPC_NEST_EVENTS_H__ #define __POWERPC_NEST_EVENTS_H__ #define POWERPC_PME_NEST_MCS_00 0 #define POWERPC_PME_NEST_MCS_01 1 #define POWERPC_PME_NEST_MCS_02 2 #define POWERPC_PME_NEST_MCS_03 3 static const pme_power_entry_t powerpc_nest_read_pe[] = { [ POWERPC_PME_NEST_MCS_00 ] = { .pme_name = "MCS_00", .pme_code = 0x118, .pme_short_desc = "Total Read Bandwidth seen on both MCS of MC0", .pme_long_desc = "Total Read Bandwidth seen on both MCS of MC0", }, [ POWERPC_PME_NEST_MCS_01 ] = { .pme_name = "MCS_01", .pme_code = 0x120, .pme_short_desc = "Total Read Bandwidth seen on both MCS of MC1", .pme_long_desc = "Total Read Bandwidth seen on both MCS of MC1", }, [ POWERPC_PME_NEST_MCS_02 ] = { .pme_name = "MCS_02", .pme_code = 0x128, .pme_short_desc = "Total Read Bandwidth seen on both MCS of MC2", .pme_long_desc = "Total Read Bandwidth seen on both MCS of MC2", }, [ POWERPC_PME_NEST_MCS_03 ] = { .pme_name = "MCS_03", .pme_code = 0x130, .pme_short_desc = "Total Read Bandwidth seen on both MCS of MC3", .pme_long_desc = "Total Read Bandwidth seen on both MCS of MC3", }, }; static const pme_power_entry_t powerpc_nest_write_pe[] = { [ POWERPC_PME_NEST_MCS_00 ] = { .pme_name = "MCS_00", .pme_code = 0x198, .pme_short_desc = "Total Write Bandwidth seen on both MCS of MC0", .pme_long_desc = "Total Write Bandwidth seen on both MCS of MC0", }, [ POWERPC_PME_NEST_MCS_01 ] = { .pme_name = "MCS_01", .pme_code = 0x1a0, .pme_short_desc = "Total Write Bandwidth seen on both MCS of MC1", .pme_long_desc = "Total Write Bandwidth seen on both MCS of MC1", }, [ POWERPC_PME_NEST_MCS_02 ] = { .pme_name = "MCS_02", .pme_code = 0x1a8, .pme_short_desc = "Total Write Bandwidth seen on both MCS of MC2", .pme_long_desc = "Total Write Bandwidth seen on both MCS of MC2", }, [ POWERPC_PME_NEST_MCS_03 ] = { .pme_name = "MCS_03", .pme_code = 0x1b0, .pme_short_desc = "Total Write Bandwidth seen on both MCS of MC3", .pme_long_desc = "Total Write Bandwidth seen on both MCS of MC3", }, }; #endif libpfm-4.9.0/lib/events/intel_snb_events.h0000664000175000017500000026006613223402656020414 0ustar eranianeranian/* * Copyright (c) 2011 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * This file has been automatically generated. * * PMU: snb (Intel Sandy Bridge) */ static const intel_x86_umask_t snb_agu_bypass_cancel[]={ { .uname = "COUNT", .udesc = "This event counts executed load operations", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t snb_arith[]={ { .uname = "FPU_DIV_ACTIVE", .udesc = "Cycles that the divider is active, includes integer and floating point", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "FPU_DIV", .udesc = "Number of cycles the divider is activated, includes integer and floating point", .uequiv = "FPU_DIV_ACTIVE:c=1:e=1", .ucode = 0x100 | INTEL_X86_MOD_EDGE | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t snb_br_inst_exec[]={ { .uname = "NONTAKEN_COND", .udesc = "All macro conditional non-taken branch instructions", .ucode = 0x4100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "TAKEN_COND", .udesc = "All macro conditional taken branch instructions", .ucode = 0x8100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "TAKEN_DIRECT_JUMP", .udesc = "All macro unconditional taken branch instructions, excluding calls and indirects", .ucode = 0x8200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "TAKEN_INDIRECT_JUMP_NON_CALL_RET", .udesc = "All taken indirect branches that are not calls nor returns", .ucode = 0x8400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "TAKEN_RETURN_NEAR", .udesc = "All taken indirect branches that have a return mnemonic", .ucode = 0x8800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "TAKEN_DIRECT_NEAR_CALL", .udesc = "All taken non-indirect calls", .ucode = 0x9000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "TAKEN_INDIRECT_NEAR_CALL", .udesc = "All taken indirect calls, including both register and memory indirect", .ucode = 0xa000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ALL_BRANCHES", .udesc = "All near executed branches instructions (not necessarily retired)", .ucode = 0xff00, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "ALL_CONDITIONAL", .udesc = "All macro conditional branch instructions", .ucode = 0xc100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ANY_COND", .udesc = "All macro conditional branch instructions", .ucode = 0xc100, .uequiv = "ALL_CONDITIONAL", .uflags= INTEL_X86_NCOMBO, }, { .uname = "ANY_INDIRECT_JUMP_NON_CALL_RET", .udesc = "All indirect branches that are not calls nor returns", .ucode = 0xc400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ANY_DIRECT_NEAR_CALL", .udesc = "All non-indirect calls", .ucode = 0xd000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ALL_DIRECT_JMP", .udesc = "Speculative and retired macro-unconditional branches excluding calls and indirects", .ucode = 0xc200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ALL_INDIRECT_NEAR_RETURN", .udesc = "Speculative and retired indirect return branches", .ucode = 0xc800, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t snb_br_inst_retired[]={ { .uname = "ALL_BRANCHES", .udesc = "All taken and not taken macro branches including far branches (Precise Event)", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS | INTEL_X86_DFL, }, { .uname = "CONDITIONAL", .udesc = "All taken and not taken macro conditional branch instructions (Precise Event)", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "FAR_BRANCH", .udesc = "Number of far branch instructions retired (Precise Event)", .ucode = 0x4000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "NEAR_CALL", .udesc = "All macro direct and indirect near calls, does not count far calls (Precise Event)", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "NEAR_RETURN", .udesc = "Number of near ret instructions retired (Precise Event)", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "NEAR_TAKEN", .udesc = "Number of near branch taken instructions retired (Precise Event)", .ucode = 0x2000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "NOT_TAKEN", .udesc = "All not taken macro branch instructions retired (Precise Event)", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, }; static const intel_x86_umask_t snb_br_misp_exec[]={ { .uname = "NONTAKEN_COND", .udesc = "All non-taken mispredicted macro conditional branch instructions", .ucode = 0x4100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "TAKEN_COND", .udesc = "All taken mispredicted macro conditional branch instructions", .ucode = 0x8100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "TAKEN_INDIRECT_JUMP_NON_CALL_RET", .udesc = "All taken mispredicted indirect branches that are not calls nor returns", .ucode = 0x8400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "TAKEN_RETURN_NEAR", .udesc = "All taken mispredicted indirect branches that have a return mnemonic", .ucode = 0x8800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "TAKEN_DIRECT_NEAR_CALL", .udesc = "All taken mispredicted non-indirect calls", .ucode = 0x9000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "TAKEN_INDIRECT_NEAR_CALL", .udesc = "All taken mispredicted indirect calls, including both register and memory indirect", .ucode = 0xa000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ANY_COND", .udesc = "All mispredicted macro conditional branch instructions", .ucode = 0xc100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ANY_DIRECT_NEAR_CALL", .udesc = "All mispredicted non-indirect calls", .ucode = 0xd000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ANY_INDIRECT_JUMP_NON_CALL_RET", .udesc = "All mispredicted indirect branches that are not calls nor returns", .ucode = 0xc400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ALL_BRANCHES", .udesc = "All mispredicted branch instructions", .ucode = 0xff00, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t snb_br_misp_retired[]={ { .uname = "ALL_BRANCHES", .udesc = "All mispredicted macro branches (Precise Event)", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS | INTEL_X86_DFL, }, { .uname = "CONDITIONAL", .udesc = "All mispredicted macro conditional branch instructions (Precise Event)", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "NEAR_CALL", .udesc = "All macro direct and indirect near calls (Precise Event)", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "NOT_TAKEN", .udesc = "Number of branch instructions retired that were mispredicted and not-taken (Precise Event)", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "TAKEN", .udesc = "Number of branch instructions retired that were mispredicted and taken (Precise Event)", .ucode = 0x2000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, }; static const intel_x86_umask_t snb_lock_cycles[]={ { .uname = "SPLIT_LOCK_UC_LOCK_DURATION", .udesc = "Cycles in which the L1D and L2 are locked, due to a UC lock or split lock", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "CACHE_LOCK_DURATION", .udesc = "Cycles in which the L1D is locked", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t snb_cpl_cycles[]={ { .uname = "RING0", .udesc = "Unhalted core cycles the thread was in ring 0", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "RING0_TRANS", .udesc = "Transitions from rings 1, 2, or 3 to ring 0", .uequiv = "RING0:c=1:e=1", .ucode = 0x100 | INTEL_X86_MOD_EDGE | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, }, { .uname = "RING123", .udesc = "Unhalted core cycles the thread was in rings 1, 2, or 3", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t snb_cpu_clk_unhalted[]={ { .uname = "REF_P", .udesc = "Cycles when the core is unhalted (count at 100 Mhz)", .ucode = 0x100, .uequiv = "REF_XCLK", .uflags= INTEL_X86_NCOMBO, }, { .uname = "REF_XCLK", .udesc = "Count Xclk pulses (100Mhz) when the core is unhalted", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "REF_XCLK_ANY", .udesc = "Count Xclk pulses (100Mhz) when the at least one thread on the physical core is unhalted", .ucode = 0x100 | INTEL_X86_MOD_ANY, /* any=1 */ .uequiv = "REF_XCLK:t", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_T, }, { .uname = "THREAD_P", .udesc = "Cycles when thread is not halted", .ucode = 0x0, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "ONE_THREAD_ACTIVE", .udesc = "Counts Xclk (100Mhz) pulses when this thread is unhalted and the other thread is halted", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t snb_dsb2mite_switches[]={ { .uname = "COUNT", .udesc = "Number of DSB to MITE switches", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "PENALTY_CYCLES", .udesc = "Cycles SB to MITE switches caused delay", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t snb_dsb_fill[]={ { .uname = "ALL_CANCEL", .udesc = "Number of times a valid DSB fill has been cancelled for any reason", .ucode = 0xa00, .uflags= INTEL_X86_NCOMBO, }, { .uname = "EXCEED_DSB_LINES", .udesc = "DSB Fill encountered > 3 DSB lines", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "OTHER_CANCEL", .udesc = "Number of times a valid DSB fill has been cancelled not because of exceeding way limit", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t snb_dtlb_load_misses[]={ { .uname = "MISS_CAUSES_A_WALK", .udesc = "Demand load miss in all TLB levels which causes an page walk of any page size", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "CAUSES_A_WALK", .udesc = "Demand load miss in all TLB levels which causes an page walk of any page size", .ucode = 0x100, .uequiv = "MISS_CAUSES_A_WALK", .uflags= INTEL_X86_NCOMBO, }, { .uname = "STLB_HIT", .udesc = "Number of DTLB lookups for loads which missed first level DTLB but hit second level DTLB (STLB); No page walk.", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "WALK_COMPLETED", .udesc = "Demand load miss in all TLB levels which causes a page walk that completes for any page size", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "WALK_DURATION", .udesc = "Cycles PMH is busy with a walk", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t snb_dtlb_store_misses[]={ { .uname = "MISS_CAUSES_A_WALK", .udesc = "Miss in all TLB levels that causes a page walk of any page size (4K/2M/4M/1G)", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "CAUSES_A_WALK", .udesc = "Miss in all TLB levels that causes a page walk of any page size (4K/2M/4M/1G)", .ucode = 0x100, .uequiv = "MISS_CAUSES_A_WALK", .uflags= INTEL_X86_NCOMBO, }, { .uname = "STLB_HIT", .udesc = "First level miss but second level hit; no page walk. Only relevant if multiple levels", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "WALK_COMPLETED", .udesc = "Miss in all TLB levels that causes a page walk that completes of any page size (4K/2M/4M/1G)", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "WALK_DURATION", .udesc = "Cycles PMH is busy with this walk", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t snb_fp_assist[]={ { .uname = "ANY", .udesc = "Cycles with any input/output SSE or FP assists", .ucode = 0x1e00 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */ .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "SIMD_INPUT", .udesc = "Number of SIMD FP assists due to input values", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "SIMD_OUTPUT", .udesc = "Number of SIMD FP assists due to output values", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "X87_INPUT", .udesc = "Number of X87 assists due to input value", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "X87_OUTPUT", .udesc = "Number of X87 assists due to output value", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ALL", .udesc = "Cycles with any input and output SSE or FP assist", .ucode = 0x1e00 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */ .uequiv = "ANY", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, }; static const intel_x86_umask_t snb_fp_comp_ops_exe[]={ { .uname = "X87", .udesc = "Number of X87 uops executed", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "SSE_FP_PACKED_DOUBLE", .udesc = "Number of SSE double precision FP packed uops executed", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "SSE_FP_SCALAR_SINGLE", .udesc = "Number of SSE single precision FP scalar uops executed", .ucode = 0x2000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "SSE_PACKED_SINGLE", .udesc = "Number of SSE single precision FP packed uops executed", .ucode = 0x4000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "SSE_SCALAR_DOUBLE", .udesc = "Number of SSE double precision FP scalar uops executed", .ucode = 0x8000, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t snb_hw_pre_req[]={ { .uname = "L1D_MISS", .udesc = "Hardware prefetch requests that misses the L1D cache. A request is counted each time it accesses the cache and misses it, including if a block is applicable or if it hits the full buffer, for example. This accounts for both L1 streamer and IP-based Hw prefetchers", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t snb_icache[]={ { .uname = "MISSES", .udesc = "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes UC accesses", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "HIT", .udesc = "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. Includes cacheable and uncacheable accesses and uncacheable fetches", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t snb_idq[]={ { .uname = "EMPTY", .udesc = "Cycles IDQ is empty", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "MITE_UOPS", .udesc = "Number of uops delivered to IDQ from MITE path", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DSB_UOPS", .udesc = "Number of uops delivered to IDQ from DSB path", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "MS_DSB_UOPS", .udesc = "Number of uops delivered to IDQ when MS busy by DSB", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "MS_MITE_UOPS", .udesc = "Number of uops delivered to IDQ when MS busy by MITE", .ucode = 0x2000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "MS_UOPS", .udesc = "Number of uops were delivered to IDQ from MS by either DSB or MITE", .ucode = 0x3000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "MITE_UOPS_CYCLES", .udesc = "Cycles where uops are delivered to IDQ from MITE (MITE active)", .uequiv = "MITE_UOPS:c=1", .ucode = 0x400 | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, }, { .uname = "MS_SWITCHES", .udesc = "Number of cycles that Uops were delivered into Instruction Decode Queue (IDQ) when MS_Busy, initiated by Decode Stream Buffer (DSB) or MITE", .ucode = 0x3000 | INTEL_X86_MOD_EDGE | (1 << INTEL_X86_CMASK_BIT), /* edge=1 cnt=1 */ .uequiv = "MS_UOPS:c=1:e", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_E | _INTEL_X86_ATTR_C, }, { .uname = "DSB_UOPS_CYCLES", .udesc = "Cycles where uops are delivered to IDQ from DSB (DSB active)", .ucode = 0x800 | (0x1 << INTEL_X86_CMASK_BIT), .modhw = _INTEL_X86_ATTR_C, .uflags= INTEL_X86_NCOMBO, }, { .uname = "MS_DSB_UOPS_CYCLES", .udesc = "Cycles where uops delivered to IDQ when MS busy by DSB", .uequiv = "MS_DSB_UOPS:c=1", .ucode = 0x1000 | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, }, { .uname = "MS_MITE_UOPS_CYCLES", .udesc = "Cycles where uops delivered to IDQ when MS busy by MITE", .uequiv = "MS_MITE_UOPS:c=1", .ucode = 0x2000 | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, }, { .uname = "MS_UOPS_CYCLES", .udesc = "Cycles where uops delivered to IDQ from MS by either BSD or MITE", .uequiv = "MS_UOPS:c=1", .ucode = 0x3000 | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, }, { .uname = "ALL_DSB_UOPS", .udesc = "Number of uops deliver from either DSB paths", .ucode = 0x1800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ALL_DSB_CYCLES", .udesc = "Cycles MITE/MS deliver anything", .ucode = 0x1800 | (0x1 << INTEL_X86_CMASK_BIT), .modhw = _INTEL_X86_ATTR_C, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ALL_DSB_CYCLES_4_UOPS", .udesc = "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", .ucode = 0x1800 | (4 << INTEL_X86_CMASK_BIT), /* cnt=4 */ .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "ALL_MITE_UOPS", .udesc = "Number of uops delivered from either MITE paths", .ucode = 0x2400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ALL_MITE_CYCLES", .udesc = "Cycles DSB/MS deliver anything", .ucode = 0x2400 | (0x1 << INTEL_X86_CMASK_BIT), .modhw = _INTEL_X86_ATTR_C, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ALL_MITE_CYCLES_4_UOPS", .udesc = "Cycles MITE is delivering 4 Uops", .ucode = 0x2400 | (4 << INTEL_X86_CMASK_BIT), /* cnt=4 */ .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "ANY_UOPS", .udesc = "Number of uops delivered to IDQ from any path", .ucode = 0x3c00, .uflags= INTEL_X86_NCOMBO, }, { .uname = "MS_DSB_UOPS_OCCUR", .udesc = "Occurrences of DSB MS going active", .uequiv = "MS_DSB_UOPS:c=1:e=1", .ucode = 0x1000 | INTEL_X86_MOD_EDGE | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t snb_idq_uops_not_delivered[]={ { .uname = "CORE", .udesc = "Number of non-delivered uops to RAT (use cmask to qualify further)", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "CYCLES_0_UOPS_DELIV_CORE", .udesc = "Cycles per thread when 4 or more uops are not delivered to the Resource Allocation Table (RAT) when backend is not stalled", .ucode = 0x100 | (4 << INTEL_X86_CMASK_BIT), /* cnt=4 */ .uflags = INTEL_X86_NCOMBO, .uequiv = "CORE:c=4", .modhw = _INTEL_X86_ATTR_C, }, { .uname = "CYCLES_GE_1_UOP_DELIV_CORE", .udesc = "Cycles per thread when 1 or more uops are delivered to the Resource Allocation Table (RAT) by the front end", .ucode = 0x100 | (4 << INTEL_X86_CMASK_BIT) | INTEL_X86_MOD_INV, /* cnt=4 inv=1 */ .uequiv = "CORE:c=4:i", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C | _INTEL_X86_ATTR_I, }, { .uname = "CYCLES_LE_1_UOP_DELIV_CORE", .udesc = "Cycles per thread when 3 or more uops are not delivered to the Resource Allocation Table (RAT) when backend is not stalled", .ucode = 0x100 | (3 << INTEL_X86_CMASK_BIT), /* cnt=3 */ .uequiv = "CORE:c=3", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "CYCLES_LE_2_UOP_DELIV_CORE", .udesc = "Cycles with less than 2 uops delivered by the front end", .ucode = 0x100 | (2 << INTEL_X86_CMASK_BIT), /* cnt=2 */ .uequiv = "CORE:c=2", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "CYCLES_LE_3_UOP_DELIV_CORE", .udesc = "Cycles with less than 3 uops delivered by the front end", .ucode = 0x100 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */ .uequiv = "CORE:c=1", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "CYCLES_FE_WAS_OK", .udesc = "Cycles Front-End (FE) delivered 4 uops or Resource Allocation Table (RAT) was stalling FE", .ucode = 0x100 | INTEL_X86_MOD_INV | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 inv=1 */ .uequiv = "CORE:c=1:i", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C | _INTEL_X86_ATTR_I, }, }; static const intel_x86_umask_t snb_ild_stall[]={ { .uname = "LCP", .udesc = "Stall caused by changing prefix length of the instruction", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "IQ_FULL", .udesc = "Stall cycles due to IQ full", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t snb_insts_written_to_iq[]={ { .uname = "INSTS", .udesc = "Number of instructions written to IQ every cycle", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t snb_inst_retired[]={ { .uname = "ANY_P", .udesc = "Number of instructions retired", .ucode = 0x0, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "PREC_DIST", .udesc = "Precise instruction retired event to reduce effect of PEBS shadow IP distribution (Precise Event)", .ucntmsk = 0x2, .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, }; static const intel_x86_umask_t snb_int_misc[]={ { .uname = "RAT_STALL_CYCLES", .udesc = "Cycles RAT external stall is sent to IDQ for this thread", .ucode = 0x4000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "RECOVERY_CYCLES", .udesc = "Cycles waiting to be recovered after Machine Clears due to all other cases except JEClear", .ucode = 0x300 | (0x1 << INTEL_X86_CMASK_BIT), .modhw = _INTEL_X86_ATTR_C, .uflags= INTEL_X86_NCOMBO, }, { .uname = "RECOVERY_STALLS_COUNT", .udesc = "Number of times need to wait after Machine Clears due to all other cases except JEClear", .ucode = 0x300 | INTEL_X86_MOD_EDGE | (0x1 << INTEL_X86_CMASK_BIT), .modhw = _INTEL_X86_ATTR_E | _INTEL_X86_ATTR_C, .uflags= INTEL_X86_NCOMBO, }, { .uname = "RECOVERY_CYCLES_ANY", .udesc = "Cycles during which the allocator was stalled due to recovery from earlier clear event for any thread (e.g. misprediction or memory nuke)", .ucode = 0x300 | (0x1 << INTEL_X86_CMASK_BIT) | INTEL_X86_MOD_ANY, /* cnt=1 any=1 */ .modhw = _INTEL_X86_ATTR_C | _INTEL_X86_ATTR_T, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t snb_itlb[]={ { .uname = "ITLB_FLUSH", .udesc = "Number of ITLB flushes, includes 4k/2M/4M pages", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "FLUSH", .udesc = "Number of ITLB flushes, includes 4k/2M/4M pages", .ucode = 0x100, .uequiv = "ITLB_FLUSH", .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t snb_l1d[]={ { .uname = "ALLOCATED_IN_M", .udesc = "Number of allocations of L1D cache lines in modified (M) state", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ALL_M_REPLACEMENT", .udesc = "Number of cache lines in M-state evicted of L1D due to snoop HITM or dirty line replacement", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "M_EVICT", .udesc = "Number of modified lines evicted from L1D due to replacement", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "REPLACEMENT", .udesc = "Number of cache lines brought into the L1D cache", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t snb_l1d_blocks[]={ { .uname = "BANK_CONFLICT", .udesc = "Number of dispatched loads cancelled due to L1D bank conflicts with other load ports", .ucode = 0x500, .uflags= INTEL_X86_NCOMBO, }, { .uname = "BANK_CONFLICT_CYCLES", .udesc = "Cycles when dispatched loads are cancelled due to L1D bank conflicts with other load ports", .ucode = 0x500 | (0x1 << INTEL_X86_CMASK_BIT), /* cnt=1 */ .uequiv = "BANK_CONFLICT:c=1", .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, .modhw = _INTEL_X86_ATTR_C, }, }; static const intel_x86_umask_t snb_l1d_pend_miss[]={ { .uname = "OCCURRENCES", .udesc = "Occurrences of L1D_PEND_MISS going active", .uequiv = "PENDING:e=1:c=1", .ucode = 0x100 | INTEL_X86_MOD_EDGE | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C | _INTEL_X86_ATTR_E, }, { .uname = "EDGE", .udesc = "Occurrences of L1D_PEND_MISS going active", .uequiv = "OCCURRENCES", .ucode = 0x100 | INTEL_X86_MOD_EDGE | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C | _INTEL_X86_ATTR_E, }, { .uname = "PENDING", .udesc = "Number of L1D load misses outstanding every cycle", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PENDING_CYCLES", .udesc = "Cycles with L1D load misses outstanding", .uequiv = "PENDING:c=1", .ucode = 0x100 | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "PENDING_CYCLES_ANY", .udesc = "Cycles with L1D load misses outstanding from any thread", .uequiv = "PENDING:c=1:t", .ucode = 0x100 | (0x1 << INTEL_X86_CMASK_BIT) | INTEL_X86_MOD_ANY, .uflags= INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C | _INTEL_X86_ATTR_T, }, { .uname = "FB_FULL", .udesc = "Number of cycles a demand request was blocked due to Fill Buffer (FB) unavailability", .ucode = 0x200 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */ .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, }; static const intel_x86_umask_t snb_l2_l1d_wb_rqsts[]={ { .uname = "ALL", .udesc = "Non rejected writebacks from L1D to L2 cache lines in E state", .ucode = 0xf00, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "HIT_E", .udesc = "Non rejected writebacks from L1D to L2 cache lines in E state", .ucode = 0x400, }, { .uname = "HIT_M", .udesc = "Non rejected writebacks from L1D to L2 cache lines in M state", .ucode = 0x800, }, { .uname = "HIT_S", .udesc = "Non rejected writebacks from L1D to L2 cache lines in S state", .ucode = 0x200, }, { .uname = "MISS", .udesc = "Number of modified lines evicted from L1 and missing L2 (non-rejected WB from DCU)", .ucode = 0x100, }, }; static const intel_x86_umask_t snb_l2_lines_in[]={ { .uname = "ANY", .udesc = "L2 cache lines filling (counting does not cover rejects)", .ucode = 0x700, .uflags= INTEL_X86_NCOMBO, }, { .uname = "E", .udesc = "L2 cache lines in E state (counting does not cover rejects)", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "I", .udesc = "L2 cache lines in I state (counting does not cover rejects)", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "S", .udesc = "L2 cache lines in S state (counting does not cover rejects)", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t snb_l2_lines_out[]={ { .uname = "DEMAND_CLEAN", .udesc = "L2 clean line evicted by a demand", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DEMAND_DIRTY", .udesc = "L2 dirty line evicted by a demand", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PREFETCH_CLEAN", .udesc = "L2 clean line evicted by a prefetch", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PREFETCH_DIRTY", .udesc = "L2 dirty line evicted by an MLC Prefetch", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DIRTY_ANY", .udesc = "Any L2 dirty line evicted (does not cover rejects)", .ucode = 0xa00, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t snb_l2_rqsts[]={ { .uname = "ALL_CODE_RD", .udesc = "Any ifetch request to L2 cache", .ucode = 0x3000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "CODE_RD_HIT", .udesc = "L2 cache hits when fetching instructions", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "CODE_RD_MISS", .udesc = "L2 cache misses when fetching instructions", .ucode = 0x2000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ALL_DEMAND_DATA_RD", .udesc = "Demand data read requests to L2 cache", .ucode = 0x300, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ALL_DEMAND_RD_HIT", .udesc = "Demand data read requests that hit L2", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ALL_PF", .udesc = "Any L2 HW prefetch request to L2 cache", .ucode = 0xc000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PF_HIT", .udesc = "Requests from the L2 hardware prefetchers that hit L2 cache", .ucode = 0x4000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PF_MISS", .udesc = "Requests from the L2 hardware prefetchers that miss L2 cache", .ucode = 0x8000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "RFO_ANY", .udesc = "Any RFO requests to L2 cache", .ucode = 0xc00, .uflags= INTEL_X86_NCOMBO, }, { .uname = "RFO_HITS", .udesc = "RFO requests that hit L2 cache", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "RFO_MISS", .udesc = "RFO requests that miss L2 cache", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t snb_l2_store_lock_rqsts[]={ { .uname = "HIT_E", .udesc = "RFOs that hit cache lines in E state", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "MISS", .udesc = "RFOs that miss cache (I state)", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "HIT_M", .udesc = "RFOs that hit cache lines in M state", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ALL", .udesc = "RFOs that access cache lines in any state", .ucode = 0xf00, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t snb_l2_trans[]={ { .uname = "ALL", .udesc = "Transactions accessing MLC pipe", .ucode = 0x8000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "CODE_RD", .udesc = "L2 cache accesses when fetching instructions", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "L1D_WB", .udesc = "L1D writebacks that access L2 cache", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "LOAD", .udesc = "Demand Data Read* requests that access L2 cache", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "L2_FILL", .udesc = "L2 fill requests that access L2 cache", .ucode = 0x2000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "L2_WB", .udesc = "L2 writebacks that access L2 cache", .ucode = 0x4000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ALL_PREFETCH", .udesc = "L2 or L3 HW prefetches that access L2 cache (including rejects)", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "RFO", .udesc = "RFO requests that access L2 cache", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t snb_ld_blocks[]={ { .uname = "DATA_UNKNOWN", .udesc = "Blocked loads due to store buffer blocks with unknown data", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "STORE_FORWARD", .udesc = "Loads blocked by overlapping with store buffer that cannot be forwarded", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "NO_SR", .udesc = "Number of split loads blocked due to resource not available", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ALL_BLOCK", .udesc = "Number of cases where any load is blocked but has not DCU miss", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t snb_ld_blocks_partial[]={ { .uname = "ADDRESS_ALIAS", .udesc = "False dependencies in MOB due to partial compare on address", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ALL_STA_BLOCK", .udesc = "Number of times that load operations are temporarily blocked because of older stores, with addresses that are not yet known. A load operation may incur more than one block of this type", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t snb_load_hit_pre[]={ { .uname = "HW_PF", .udesc = "Non sw-prefetch load dispatches that hit the fill buffer allocated for HW prefetch", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "SW_PF", .udesc = "Non sw-prefetch load dispatches that hit the fill buffer allocated for SW prefetch", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t snb_l3_lat_cache[]={ { .uname = "MISS", .udesc = "Core-originated cacheable demand requests missed L3", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "REFERENCE", .udesc = "Core-originated cacheable demand requests that refer to L3", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t snb_machine_clears[]={ { .uname = "MASKMOV", .udesc = "The number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0", .ucode = 0x2000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "MEMORY_ORDERING", .udesc = "Number of Memory Ordering Machine Clears detected", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "SMC", .udesc = "Self-Modifying Code detected", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "COUNT", .udesc = "Number of machine clears (nukes) of any type", .ucode = 0x100 | INTEL_X86_MOD_EDGE | (1 << INTEL_X86_CMASK_BIT), /* edge=1 cnt=1 */ .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_E | _INTEL_X86_ATTR_C, }, }; static const intel_x86_umask_t snb_mem_load_uops_llc_hit_retired[]={ { .uname = "XSNP_HIT", .udesc = "Load LLC Hit and a cross-core Snoop hits in on-pkg core cache (Precise Event)", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "XSNP_HITM", .udesc = "Load had HitM Response from a core on same socket (shared LLC) (Precise Event)", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "XSNP_MISS", .udesc = "Load LLC Hit and a cross-core Snoop missed in on-pkg core cache (Precise Event)", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "XSNP_NONE", .udesc = "Load hit in last-level (L3) cache with no snoop needed (Precise Event)", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, }; static const intel_x86_umask_t snb_mem_load_uops_misc_retired[]={ { .uname = "LLC_MISS", .udesc = "Counts load driven L3 misses and some non simd split loads (Precise Event)", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS | INTEL_X86_DFL, }, }; static const intel_x86_umask_t snb_mem_load_uops_retired[]={ { .uname = "HIT_LFB", .udesc = "A load missed L1D but hit the Fill Buffer (Precise Event)", .ucode = 0x4000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "L1_HIT", .udesc = "Load hit in nearest-level (L1D) cache (Precise Event)", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "L2_HIT", .udesc = "Load hit in mid-level (L2) cache (Precise Event)", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "L3_HIT", .udesc = "Load hit in last-level (L3) cache with no snoop needed (Precise Event)", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "L3_MISS", .udesc = "Retired load uops which data sources were data missed LLC (excluding unknown data source)", .ucode = 0x2000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, .umodel = PFM_PMU_INTEL_SNB_EP, }, }; static const intel_x86_umask_t snb_mem_trans_retired[]={ { .uname = "LATENCY_ABOVE_THRESHOLD", .udesc = "Memory load instructions retired above programmed clocks, minimum threshold value is 3 (Precise Event and ldlat required)", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS | INTEL_X86_LDLAT, }, { .uname = "PRECISE_STORE", .udesc = "Capture where stores occur, must use with PEBS (Precise Event required)", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, }; static const intel_x86_umask_t snb_mem_uops_retired[]={ { .uname = "ALL_LOADS", .udesc = "Any retired loads (Precise Event)", .ucode = 0x8100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "ANY_LOADS", .udesc = "Any retired loads (Precise Event)", .ucode = 0x8100, .uequiv = "ALL_LOADS", .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "ALL_STORES", .udesc = "Any retired stores (Precise Event)", .ucode = 0x8200, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "ANY_STORES", .udesc = "Any retired stores (Precise Event)", .ucode = 0x8200, .uequiv = "ALL_STORES", .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "LOCK_LOADS", .udesc = "Locked retired loads (Precise Event)", .ucode = 0x2100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "LOCK_STORES", .udesc = "Locked retired stores (Precise Event)", .ucode = 0x2200, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "SPLIT_LOADS", .udesc = "Retired loads causing cacheline splits (Precise Event)", .ucode = 0x4100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "SPLIT_STORES", .udesc = "Retired stores causing cacheline splits (Precise Event)", .ucode = 0x4200, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "STLB_MISS_LOADS", .udesc = "STLB misses dues to retired loads (Precise Event)", .ucode = 0x1100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "STLB_MISS_STORES", .udesc = "STLB misses dues to retired stores (Precise Event)", .ucode = 0x1200, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, }; static const intel_x86_umask_t snb_misalign_mem_ref[]={ { .uname = "LOADS", .udesc = "Speculative cache-line split load uops dispatched to the L1D", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "STORES", .udesc = "Speculative cache-line split Store-address uops dispatched to L1D", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t snb_offcore_requests[]={ { .uname = "ALL_DATA_RD", .udesc = "Demand and prefetch read requests sent to uncore", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ALL_DATA_READ", .udesc = "Demand and prefetch read requests sent to uncore", .uequiv = "ALL_DATA_RD", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DEMAND_CODE_RD", .udesc = "Offcore code read requests, including cacheable and un-cacheables", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DEMAND_DATA_RD", .udesc = "Demand Data Read requests sent to uncore", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DEMAND_RFO", .udesc = "Offcore Demand RFOs, includes regular RFO, Locks, ItoM", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t snb_offcore_requests_buffer[]={ { .uname = "SQ_FULL", .udesc = "Offcore requests buffer cannot take more entries for this thread core", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t snb_offcore_requests_outstanding[]={ { .uname = "ALL_DATA_RD_CYCLES", .udesc = "Cycles with cacheable data read transactions in the superQ", .uequiv = "ALL_DATA_RD:c=1", .ucode = 0x800 | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, }, { .uname = "DEMAND_CODE_RD_CYCLES", .udesc = "Cycles with demand code reads transactions in the superQ", .uequiv = "DEMAND_CODE_RD:c=1", .ucode = 0x200 | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, }, { .uname = "DEMAND_DATA_RD_CYCLES", .udesc = "Cycles with demand data read transactions in the superQ", .uequiv = "DEMAND_DATA_RD:c=1", .ucode = 0x100 | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, }, { .uname = "ALL_DATA_RD", .udesc = "Cacheable data read transactions in the superQ every cycle", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DEMAND_CODE_RD", .udesc = "Code read transactions in the superQ every cycle", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DEMAND_DATA_RD", .udesc = "Demand data read transactions in the superQ every cycle", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DEMAND_DATA_RD_GE_6", .udesc = "Cycles with at lesat 6 offcore outstanding demand data read requests in the uncore queue", .uequiv = "DEMAND_DATA_RD:c=6", .ucode = 0x100 | (6 << INTEL_X86_CMASK_BIT), .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "DEMAND_RFO", .udesc = "Outstanding RFO (store) transactions in the superQ every cycle", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "DEMAND_RFO_CYCLES", .udesc = "Cycles with outstanding RFO (store) transactions in the superQ", .uequiv = "DEMAND_RFO:c=1", .ucode = 0x400 | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t snb_other_assists[]={ { .uname = "ITLB_MISS_RETIRED", .udesc = "Number of instructions that experienced an ITLB miss", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "AVX_TO_SSE", .udesc = "Number of transitions from AVX-256 to legacy SSE when penalty applicable", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "SSE_TO_AVX", .udesc = "Number of transitions from legacy SSE to AVX-256 when penalty applicable", .ucode = 0x2000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "AVX_STORE", .udesc = "Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t snb_partial_rat_stalls[]={ { .uname = "FLAGS_MERGE_UOP", .udesc = "Number of flags-merge uops in flight in each cycle", .ucode = 0x2000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "CYCLES_FLAGS_MERGE_UOP", .udesc = "Cycles in which flags-merge uops in flight", .uequiv = "FLAGS_MERGE_UOP:c=1", .ucode = 0x2000 | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, }, { .uname = "MUL_SINGLE_UOP", .udesc = "Number of Multiply packed/scalar single precision uops allocated", .ucode = 0x8000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "SLOW_LEA_WINDOW", .udesc = "Number of cycles with at least one slow LEA uop allocated", .ucode = 0x4000, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t snb_resource_stalls[]={ { .uname = "ANY", .udesc = "Cycles stalled due to Resource Related reason", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "LB", .udesc = "Cycles stalled due to lack of load buffers", .ucode = 0x200, }, { .uname = "RS", .udesc = "Cycles stalled due to no eligible RS entry available", .ucode = 0x400, }, { .uname = "SB", .udesc = "Cycles stalled due to no store buffers available (not including draining from sync)", .ucode = 0x800, }, { .uname = "ROB", .udesc = "Cycles stalled due to re-order buffer full", .ucode = 0x1000, }, { .uname = "FCSW", .udesc = "Cycles stalled due to writing the FPU control word", .ucode = 0x2000, }, { .uname = "MXCSR", .udesc = "Cycles stalled due to the MXCSR register ranme occurring too close to a previous MXCSR rename", .ucode = 0x4000, }, { .uname = "MEM_RS", .udesc = "Cycles stalled due to LB, SB or RS being completely in use", .ucode = 0xe00, .uequiv = "LB:SB:RS", }, { .uname = "LD_SB", .udesc = "Resource stalls due to load or store buffers all being in use", .ucode = 0xa00, }, { .uname = "OOO_SRC", .udesc = "Resource stalls due to Rob being full, FCSW, MXCSR and OTHER", .ucode = 0xf000, }, }; static const intel_x86_umask_t snb_resource_stalls2[]={ { .uname = "ALL_FL_EMPTY", .udesc = "Cycles stalled due to free list empty", .ucode = 0xc00, }, { .uname = "ALL_PRF_CONTROL", .udesc = "Cycles stalls due to control structures full for physical registers", .ucode = 0xf00, }, { .uname = "ANY_PRF_CONTROL", .udesc = "Cycles stalls due to control structures full for physical registers", .ucode = 0xf00, .uequiv = "ALL_PRF_CONTROL", }, { .uname = "BOB_FULL", .udesc = "Cycles Allocator is stalled due Branch Order Buffer", .ucode = 0x4000, }, { .uname = "OOO_RSRC", .udesc = "Cycles stalled due to out of order resources full", .ucode = 0x4f00, }, }; static const intel_x86_umask_t snb_rob_misc_events[]={ { .uname = "LBR_INSERTS", .udesc = "Count each time an new LBR record is saved by HW", .ucode = 0x2000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t snb_rs_events[]={ { .uname = "EMPTY_CYCLES", .udesc = "Cycles the RS is empty for this thread", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "EMPTY_END", .udesc = "Counts number of time the Reservation Station (RS) goes from empty to non-empty", .ucode = 0x100 | INTEL_X86_MOD_INV | INTEL_X86_MOD_EDGE | (1 << INTEL_X86_CMASK_BIT), /* inv=1 edge=1 cnt=1 */ .uequiv = "EMPTY_CYCLES:c=1:e:i", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_E | _INTEL_X86_ATTR_I | _INTEL_X86_ATTR_C, }, }; static const intel_x86_umask_t snb_simd_fp_256[]={ { .uname = "PACKED_SINGLE", .udesc = "Counts 256-bit packed single-precision", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PACKED_DOUBLE", .udesc = "Counts 256-bit packed double-precision", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t snb_sq_misc[]={ { .uname = "SPLIT_LOCK", .udesc = "Split locks in SQ", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t snb_tlb_flush[]={ { .uname = "DTLB_THREAD", .udesc = "Number of DTLB flushes of thread-specific entries", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "STLB_ANY", .udesc = "Number of STLB flushes", .ucode = 0x2000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t snb_uops_dispatched_port[]={ { .uname = "PORT_0", .udesc = "Cycles which a Uop is dispatched on port 0", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PORT_1", .udesc = "Cycles which a Uop is dispatched on port 1", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PORT_2_LD", .udesc = "Cycles in which a load uop is dispatched on port 2", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PORT_2_STA", .udesc = "Cycles in which a store uop is dispatched on port 2", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PORT_2", .udesc = "Cycles in which a uop is dispatched on port 2", .ucode = 0xc00, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PORT_3", .udesc = "Cycles in which a uop is dispatched on port 3", .ucode = 0x3000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PORT_4", .udesc = "Cycles which a uop is dispatched on port 4", .ucode = 0x4000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PORT_5", .udesc = "Cycles which a Uop is dispatched on port 5", .ucode = 0x8000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "PORT_0_CORE", .udesc = "Cycles in which a uop is dispatched on port 0 for any thread", .ucode = 0x100 | INTEL_X86_MOD_ANY, /* any=1 */ .uequiv = "PORT_0:t", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_T, }, { .uname = "PORT_1_CORE", .udesc = "Cycles in which a uop is dispatched on port 1 for any thread", .ucode = 0x200 | INTEL_X86_MOD_ANY, /* any=1 */ .uequiv = "PORT_1:t", .uflags= INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_T, }, { .uname = "PORT_2_CORE", .udesc = "Cycles in which a uop is dispatched on port 2 for any thread", .ucode = 0xc00 | INTEL_X86_MOD_ANY, /* any=1 */ .uequiv = "PORT_2:t", .uflags= INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_T, }, { .uname = "PORT_3_CORE", .udesc = "Cycles in which a uop is dispatched on port 3 for any thread", .ucode = 0x3000 | INTEL_X86_MOD_ANY, /* any=1 */ .uequiv = "PORT_3:t", .uflags= INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_T, }, { .uname = "PORT_4_CORE", .udesc = "Cycles in which a uop is dispatched on port 4 for any thread", .ucode = 0x4000 | INTEL_X86_MOD_ANY, /* any=1 */ .uequiv = "PORT_4:t", .uflags= INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_T, }, { .uname = "PORT_5_CORE", .udesc = "Cycles in which a uop is dispatched on port 5 for any thread", .ucode = 0x8000 | INTEL_X86_MOD_ANY, /* any=1 */ .uequiv = "PORT_5:t", .uflags= INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_T, }, }; static const intel_x86_umask_t snb_uops_issued[]={ { .uname = "ANY", .udesc = "Number of uops issued by the RAT to the Reservation Station (RS)", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "CORE_STALL_CYCLES", .udesc = "Cycles no uops issued on this core (by any thread)", .uequiv = "ANY:c=1:i=1:t=1", .ucode = 0x100 | INTEL_X86_MOD_ANY | INTEL_X86_MOD_INV | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_I | _INTEL_X86_ATTR_C | _INTEL_X86_ATTR_T, }, { .uname = "STALL_CYCLES", .udesc = "Cycles no uops issued by this thread", .uequiv = "ANY:c=1:i=1", .ucode = 0x100 | INTEL_X86_MOD_INV | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_I | _INTEL_X86_ATTR_C, }, }; static const intel_x86_umask_t snb_uops_retired[]={ { .uname = "ALL", .udesc = "All uops that actually retired (Precise Event)", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS | INTEL_X86_DFL, }, { .uname = "ANY", .udesc = "All uops that actually retired (Precise Event)", .ucode = 0x100, .uequiv= "ALL", .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "RETIRE_SLOTS", .udesc = "Number of retirement slots used (Precise Event)", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "STALL_CYCLES", .udesc = "Cycles no executable uop retired (Precise Event)", .uequiv = "ALL:c=1:i", .ucode = 0x100 | INTEL_X86_MOD_INV | (0x1 << INTEL_X86_CMASK_BIT), .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, .modhw = _INTEL_X86_ATTR_I | _INTEL_X86_ATTR_C, }, { .uname = "TOTAL_CYCLES", .udesc = "Total cycles using precise uop retired event (Precise Event)", .uequiv = "ALL:c=10:i", .ucode = 0x100 | INTEL_X86_MOD_INV | (10 << INTEL_X86_CMASK_BIT), .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, .modhw = _INTEL_X86_ATTR_I | _INTEL_X86_ATTR_C, }, }; static const intel_x86_umask_t snb_offcore_response[]={ { .uname = "DMND_DATA_RD", .udesc = "Request: number of demand and DCU prefetch data reads of full and partial cachelines as well as demand data page table entry cacheline reads. Does not count L2 data read prefetches or instruction fetches", .ucode = 1ULL << (0 + 8), .grpid = 0, }, { .uname = "DMND_RFO", .udesc = "Request: number of demand and DCU prefetch reads for ownership (RFO) requests generated by a write to data cacheline. Does not count L2 RFO prefetches", .ucode = 1ULL << (1 + 8), .grpid = 0, }, { .uname = "DMND_IFETCH", .udesc = "Request: number of demand and DCU prefetch instruction cacheline reads. Does not count L2 code read prefetches", .ucode = 1ULL << (2 + 8), .grpid = 0, }, { .uname = "WB", .udesc = "Request: number of writebacks (modified to exclusive) transactions", .ucode = 1ULL << (3 + 8), .grpid = 0, }, { .uname = "PF_DATA_RD", .udesc = "Request: number of data cacheline reads generated by L2 prefetchers", .ucode = 1ULL << (4 + 8), .grpid = 0, }, { .uname = "PF_RFO", .udesc = "Request: number of RFO requests generated by L2 prefetchers", .ucode = 1ULL << (5 + 8), .grpid = 0, }, { .uname = "PF_IFETCH", .udesc = "Request: number of code reads generated by L2 prefetchers", .ucode = 1ULL << (6 + 8), .grpid = 0, }, { .uname = "PF_LLC_DATA_RD", .udesc = "Request: number of L3 prefetcher requests to L2 for loads", .ucode = 1ULL << (7 + 8), .grpid = 0, }, { .uname = "PF_LLC_RFO", .udesc = "Request: number of RFO requests generated by L2 prefetcher", .ucode = 1ULL << (8 + 8), .grpid = 0, }, { .uname = "PF_LLC_IFETCH", .udesc = "Request: number of L2 prefetcher requests to L3 for instruction fetches", .ucode = 1ULL << (9 + 8), .grpid = 0, }, { .uname = "BUS_LOCKS", .udesc = "Request: number bus lock and split lock requests", .ucode = 1ULL << (10 + 8), .grpid = 0, }, { .uname = "STRM_ST", .udesc = "Request: number of streaming store requests", .ucode = 1ULL << (11 + 8), .grpid = 0, }, { .uname = "OTHER", .udesc = "Request: counts one of the following transaction types, including L3 invalidate, I/O, full or partial writes, WC or non-temporal stores, CLFLUSH, Fences, lock, unlock, split lock", .ucode = 1ULL << (15+8), .grpid = 0, }, { .uname = "ANY_IFETCH", .udesc = "Request: combination of PF_IFETCH | DMND_IFETCH | PF_LLC_IFETCH", .uequiv = "PF_IFETCH:DMND_IFETCH:PF_LLC_IFETCH", .ucode = 0x24400, .grpid = 0, }, { .uname = "ANY_REQUEST", .udesc = "Request: combination of all request umasks", .uequiv = "DMND_DATA_RD:DMND_RFO:DMND_IFETCH:WB:PF_DATA_RD:PF_RFO:PF_IFETCH:PF_LLC_DATA_RD:PF_LLC_RFO:PF_LLC_IFETCH:BUS_LOCKS:STRM_ST:OTHER", .ucode = 0x8fff00, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, .grpid = 0, }, { .uname = "ANY_DATA", .udesc = "Request: combination of DMND_DATA | PF_DATA_RD | PF_LLC_DATA_RD", .uequiv = "DMND_DATA_RD:PF_DATA_RD:PF_LLC_DATA_RD", .ucode = 0x9100, .grpid = 0, }, { .uname = "ANY_RFO", .udesc = "Request: combination of DMND_RFO | PF_RFO | PF_LLC_RFO", .uequiv = "DMND_RFO:PF_RFO:PF_LLC_RFO", .ucode = 0x12200, .grpid = 0, }, { .uname = "ANY_RESPONSE", .udesc = "Response: count any response type", .ucode = 1ULL << (16+8), .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL | INTEL_X86_EXCL_GRP_GT, .grpid = 1, }, { .uname = "NO_SUPP", .udesc = "Supplier: counts number of times supplier information is not available", .ucode = 1ULL << (17+8), .grpid = 1, }, { .uname = "LLC_HITM", .udesc = "Supplier: counts L3 hits in M-state (initial lookup)", .ucode = 1ULL << (18+8), .grpid = 1, }, { .uname = "LLC_HITE", .udesc = "Supplier: counts L3 hits in E-state", .ucode = 1ULL << (19+8), .grpid = 1, }, { .uname = "LLC_HITS", .udesc = "Supplier: counts L3 hits in S-state", .ucode = 1ULL << (20+8), .grpid = 1, }, { .uname = "LLC_HITF", .udesc = "Supplier: counts L3 hits in F-state", .ucode = 1ULL << (21+8), .grpid = 1, }, { .uname = "LLC_MISS_LOCAL_DRAM", .udesc = "Supplier: counts L3 misses to local DRAM", .ucode = 1ULL << (22+8), .grpid = 1, }, { .uname = "LLC_MISS_LOCAL", .udesc = "Supplier: counts L3 misses to local DRAM", .ucode = 1ULL << (22+8), .uequiv = "LLC_MISS_LOCAL_DRAM", .grpid = 1, }, { .uname = "L3_MISS", .udesc = "Supplier: counts L3 misses to local DRAM", .ucode = 0x1ULL << (22+8), .grpid = 1, .uequiv = "LLC_MISS_LOCAL", .umodel = PFM_PMU_INTEL_SNB, }, { .uname = "LLC_MISS_REMOTE", .udesc = "Supplier: counts L3 misses to remote DRAM", .ucode = 0xffULL << (23+8), .uequiv = "LLC_MISS_REMOTE_DRAM", .grpid = 1, .umodel = PFM_PMU_INTEL_SNB_EP, }, { .uname = "LLC_MISS_REMOTE_DRAM", .udesc = "Supplier: counts L3 misses to remote DRAM", .ucode = 0xffULL << (23+8), .grpid = 1, .umodel = PFM_PMU_INTEL_SNB_EP, }, { .uname = "L3_MISS", .udesc = "Supplier: counts L3 misses to local or remote DRAM", .ucode = 0x3ULL << (22+8), .uequiv = "LLC_MISS_LOCAL:LLC_MISS_REMOTE", .umodel = PFM_PMU_INTEL_SNB_EP, .grpid = 1, }, { .uname = "LLC_HITMESF", .udesc = "Supplier: counts L3 hits in any state (M, E, S, F)", .ucode = 0xfULL << (18+8), .uequiv = "LLC_HITM:LLC_HITE:LLC_HITS:LLC_HITF", .grpid = 1, }, { .uname = "SNP_NONE", .udesc = "Snoop: counts number of times no snoop-related information is available", .ucode = 1ULL << (31+8), .grpid = 2, }, { .uname = "SNP_NOT_NEEDED", .udesc = "Snoop: counts the number of times no snoop was needed to satisfy the request", .ucode = 1ULL << (32+8), .grpid = 2, }, { .uname = "NO_SNP_NEEDED", .udesc = "Snoop: counts the number of times no snoop was needed to satisfy the request", .ucode = 1ULL << (32+8), .uequiv = "SNP_NOT_NEEDED", .grpid = 2, }, { .uname = "SNP_MISS", .udesc = "Snoop: counts number of times a snoop was needed and it missed all snooped caches", .ucode = 1ULL << (33+8), .grpid = 2, }, { .uname = "SNP_NO_FWD", .udesc = "Snoop: counts number of times a snoop was needed and it hit in at leas one snooped cache", .ucode = 1ULL << (34+8), .grpid = 2, }, { .uname = "SNP_FWD", .udesc = "Snoop: counts number of times a snoop was needed and data was forwarded from a remote socket", .ucode = 1ULL << (35+8), .grpid = 2, }, { .uname = "HITM", .udesc = "Snoop: counts number of times a snoop was needed and it hitM-ed in local or remote cache", .ucode = 1ULL << (36+8), .grpid = 2, }, { .uname = "NON_DRAM", .udesc = "Snoop: counts number of times target was a non-DRAM system address. This includes MMIO transactions", .ucode = 1ULL << (37+8), .grpid = 2, }, { .uname = "SNP_ANY", .udesc = "Snoop: any snoop reason", .ucode = 0x7fULL << (31+8), .uequiv = "SNP_NONE:SNP_NOT_NEEDED:SNP_MISS:SNP_NO_FWD:SNP_FWD:HITM:NON_DRAM", .uflags= INTEL_X86_DFL, .grpid = 2, }, }; static const intel_x86_umask_t snb_baclears[]={ { .uname = "ANY", .udesc = "Counts the number of times the front end is re-steered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end", .ucode = 0x1f00, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t snb_cycle_activity[]={ { .uname = "CYCLES_L2_PENDING", .udesc = "Cycles with pending L2 miss loads", .ucode = 0x0100 | (0x1 << INTEL_X86_CMASK_BIT), .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, .ucntmsk= 0xf, }, { .uname = "CYCLES_L1D_PENDING", .udesc = "Cycles with pending L1D load cache misses", .ucode = 0x0200 | (0x2 << INTEL_X86_CMASK_BIT), .ucntmsk= 0x4, .modhw = _INTEL_X86_ATTR_C, .uflags = INTEL_X86_NCOMBO, }, { .uname = "CYCLES_NO_DISPATCH", .udesc = "Cycles of dispatch stalls", .ucode = 0x0400 | (0x4 << INTEL_X86_CMASK_BIT), .ucntmsk= 0xf, .modhw = _INTEL_X86_ATTR_C, .uflags = INTEL_X86_NCOMBO, }, { .uname = "STALLS_L2_PENDING", .udesc = "Execution stalls due to L2 pending loads", .ucode = 0x0500 | (0x5 << INTEL_X86_CMASK_BIT), .ucntmsk= 0xf, .modhw = _INTEL_X86_ATTR_C, .uflags = INTEL_X86_NCOMBO, }, { .uname = "STALLS_L1D_PENDING", .udesc = "Execution stalls due to L1D pending loads", .ucode = 0x0600 | (0x6 << INTEL_X86_CMASK_BIT), .ucntmsk= 0x4, .modhw = _INTEL_X86_ATTR_C, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t snb_ept[]={ { .uname = "WALK_CYCLES", .udesc = "Cycles for an extended page table walk", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t snb_lsd[]={ { .uname = "UOPS", .udesc = "Number of uops delivered by the Loop Stream Detector (LSD)", .ucode = 0x100, .uflags= INTEL_X86_DFL, }, { .uname = "ACTIVE", .udesc = "Cycles with uops delivered by the LSD but which did not come from decoder", .ucode = 0x100 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */ .uequiv = "UOPS:c=1", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "CYCLES_4_UOPS", .udesc = "Cycles with 4 uops delivered by the LSD but which did not come from decoder", .ucode = 0x100 | (4 << INTEL_X86_CMASK_BIT), /* cnt=4 */ .uequiv = "UOPS:c=4", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, }; static const intel_x86_umask_t snb_page_walks[]={ { .uname = "LLC_MISS", .udesc = "Number of page walks with a LLC miss", .ucode = 0x100, .uflags= INTEL_X86_DFL, }, }; static const intel_x86_umask_t snb_uops_executed[]={ { .uname = "CORE", .udesc = "Counts total number of uops executed from any thread per cycle", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "THREAD", .udesc = "Counts total number of uops executed per thread each cycle", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "STALL_CYCLES", .udesc = "Number of cycles with no uops executed", .ucode = 0x100 | INTEL_X86_MOD_INV | (1 << INTEL_X86_CMASK_BIT), /* inv=1 cnt=1 */ .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_I | _INTEL_X86_ATTR_C, }, { .uname = "CYCLES_GE_1_UOP_EXEC", .udesc = "Cycles where at least 1 uop was executed per thread", .ucode = 0x100 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */ .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "CYCLES_GE_2_UOPS_EXEC", .udesc = "Cycles where at least 2 uops were executed per thread", .ucode = 0x100 | (2 << INTEL_X86_CMASK_BIT), /* cnt=2 */ .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "CYCLES_GE_3_UOPS_EXEC", .udesc = "Cycles where at least 3 uops were executed per thread", .ucode = 0x100 | (3 << INTEL_X86_CMASK_BIT), /* cnt=3 */ .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "CYCLES_GE_4_UOPS_EXEC", .udesc = "Cycles where at least 4 uops were executed per thread", .ucode = 0x100 | (4 << INTEL_X86_CMASK_BIT), /* cnt=4 */ .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "CORE_CYCLES_GE_1", .udesc = "Cycles where at least 1 uop was executed from any thread", .ucode = 0x200 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */ .uequiv = "CORE:c=1", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "CORE_CYCLES_GE_2", .udesc = "Cycles where at least 2 uops were executed from any thread", .ucode = 0x200 | (2 << INTEL_X86_CMASK_BIT), /* cnt=2 */ .uequiv = "CORE:c=2", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "CORE_CYCLES_GE_3", .udesc = "Cycles where at least 3 uops were executed from any thread", .ucode = 0x200 | (3 << INTEL_X86_CMASK_BIT), /* cnt=3 */ .uequiv = "CORE:c=3", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "CORE_CYCLES_GE_4", .udesc = "Cycles where at least 4 uops were executed from any thread", .ucode = 0x200 | (4 << INTEL_X86_CMASK_BIT), /* cnt=4 */ .uequiv = "CORE:c=4", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_C, }, { .uname = "CORE_CYCLES_NONE", .udesc = "Cycles where no uop is executed on any thread", .ucode = 0x200 | INTEL_X86_MOD_INV, /* inv=1 */ .uequiv = "CORE:i", .uflags = INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_I, }, }; static const intel_x86_umask_t snb_mem_load_uops_llc_miss_retired[]={ { .uname = "LOCAL_DRAM", .udesc = "Load uops that miss in the L3 and hit local DRAM", .ucode = 0x100, .umodel = PFM_PMU_INTEL_SNB_EP, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "REMOTE_DRAM", .udesc = "Load uops that miss in the L3 and hit remote DRAM", .ucode = 0x400, .umodel = PFM_PMU_INTEL_SNB_EP, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, }; static const intel_x86_entry_t intel_snb_pe[]={ { .name = "AGU_BYPASS_CANCEL", .desc = "Number of executed load operations with all the following traits: 1. addressing of the format [base + offset], 2. the offset is between 1 and 2047, 3. the address specified in the base register is in one page and the address [base+offset] is in another page", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xb6, .numasks = LIBPFM_ARRAY_SIZE(snb_agu_bypass_cancel), .ngrp = 1, .umasks = snb_agu_bypass_cancel, }, { .name = "ARITH", .desc = "Counts arithmetic multiply operations", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0x14, .numasks = LIBPFM_ARRAY_SIZE(snb_arith), .ngrp = 1, .umasks = snb_arith, }, { .name = "BACLEARS", .desc = "Branch re-steered", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xe6, .numasks = LIBPFM_ARRAY_SIZE(snb_baclears), .ngrp = 1, .umasks = snb_baclears, }, { .name = "BR_INST_EXEC", .desc = "Branch instructions executed", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0x88, .numasks = LIBPFM_ARRAY_SIZE(snb_br_inst_exec), .ngrp = 1, .umasks = snb_br_inst_exec, }, { .name = "BR_INST_RETIRED", .desc = "Retired branch instructions", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xc4, .flags= INTEL_X86_PEBS, .numasks = LIBPFM_ARRAY_SIZE(snb_br_inst_retired), .ngrp = 1, .umasks = snb_br_inst_retired, }, { .name = "BR_MISP_EXEC", .desc = "Mispredicted branches executed", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0x89, .numasks = LIBPFM_ARRAY_SIZE(snb_br_misp_exec), .ngrp = 1, .umasks = snb_br_misp_exec, }, { .name = "BR_MISP_RETIRED", .desc = "Mispredicted retired branches", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xc5, .flags= INTEL_X86_PEBS, .numasks = LIBPFM_ARRAY_SIZE(snb_br_misp_retired), .ngrp = 1, .umasks = snb_br_misp_retired, }, { .name = "BRANCH_INSTRUCTIONS_RETIRED", .desc = "Count branch instructions at retirement. Specifically, this event counts the retirement of the last micro-op of a branch instruction", .modmsk = INTEL_V3_ATTRS, .equiv = "BR_INST_RETIRED:ALL_BRANCHES", .cntmsk = 0xff, .code = 0xc4, }, { .name = "MISPREDICTED_BRANCH_RETIRED", .desc = "Count mispredicted branch instructions at retirement. Specifically, this event counts at retirement of the last micro-op of a branch instruction in the architectural path of the execution and experienced misprediction in the branch prediction hardware", .modmsk = INTEL_V3_ATTRS, .equiv = "BR_MISP_RETIRED:ALL_BRANCHES", .cntmsk = 0xff, .code = 0xc5, }, { .name = "LOCK_CYCLES", .desc = "Locked cycles in L1D and L2", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0x63, .numasks = LIBPFM_ARRAY_SIZE(snb_lock_cycles), .ngrp = 1, .umasks = snb_lock_cycles, }, { .name = "CPL_CYCLES", .desc = "Unhalted core cycles at a specific ring level", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0x5c, .numasks = LIBPFM_ARRAY_SIZE(snb_cpl_cycles), .ngrp = 1, .umasks = snb_cpl_cycles, }, { .name = "CPU_CLK_UNHALTED", .desc = "Cycles when processor is not in halted state", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0x3c, .numasks = LIBPFM_ARRAY_SIZE(snb_cpu_clk_unhalted), .ngrp = 1, .umasks = snb_cpu_clk_unhalted, }, { .name = "DSB2MITE_SWITCHES", .desc = "Number of DSB to MITE switches", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xab, .numasks = LIBPFM_ARRAY_SIZE(snb_dsb2mite_switches), .ngrp = 1, .umasks = snb_dsb2mite_switches, }, { .name = "DSB_FILL", .desc = "DSB fills", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xac, .numasks = LIBPFM_ARRAY_SIZE(snb_dsb_fill), .ngrp = 1, .umasks = snb_dsb_fill, }, { .name = "DTLB_LOAD_MISSES", .desc = "Data TLB load misses", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0x8, .numasks = LIBPFM_ARRAY_SIZE(snb_dtlb_load_misses), .ngrp = 1, .umasks = snb_dtlb_load_misses, }, { .name = "DTLB_STORE_MISSES", .desc = "Data TLB store misses", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0x49, .numasks = LIBPFM_ARRAY_SIZE(snb_dtlb_store_misses), .ngrp = 1, .umasks = snb_dtlb_store_misses, }, { .name = "FP_ASSIST", .desc = "X87 Floating point assists", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xca, .numasks = LIBPFM_ARRAY_SIZE(snb_fp_assist), .ngrp = 1, .umasks = snb_fp_assist, }, { .name = "FP_COMP_OPS_EXE", .desc = "Counts number of floating point events", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0x10, .numasks = LIBPFM_ARRAY_SIZE(snb_fp_comp_ops_exe), .ngrp = 1, .umasks = snb_fp_comp_ops_exe, }, { .name = "HW_PRE_REQ", .desc = "Hardware prefetch requests", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0x4e, .numasks = LIBPFM_ARRAY_SIZE(snb_hw_pre_req), .ngrp = 1, .umasks = snb_hw_pre_req, }, { .name = "ICACHE", .desc = "Instruction Cache accesses", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0x80, .numasks = LIBPFM_ARRAY_SIZE(snb_icache), .ngrp = 1, .umasks = snb_icache, }, { .name = "IDQ", .desc = "IDQ operations", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0x79, .numasks = LIBPFM_ARRAY_SIZE(snb_idq), .ngrp = 1, .umasks = snb_idq, }, { .name = "IDQ_UOPS_NOT_DELIVERED", .desc = "Uops not delivered", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0x9c, .numasks = LIBPFM_ARRAY_SIZE(snb_idq_uops_not_delivered), .ngrp = 1, .umasks = snb_idq_uops_not_delivered, }, { .name = "ILD_STALL", .desc = "Instruction Length Decoder stalls", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0x87, .numasks = LIBPFM_ARRAY_SIZE(snb_ild_stall), .ngrp = 1, .umasks = snb_ild_stall, }, { .name = "INSTS_WRITTEN_TO_IQ", .desc = "Instructions written to IQ", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0x17, .numasks = LIBPFM_ARRAY_SIZE(snb_insts_written_to_iq), .ngrp = 1, .umasks = snb_insts_written_to_iq, }, { .name = "INST_RETIRED", .desc = "Instructions retired", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xc0, .flags= INTEL_X86_PEBS, .numasks = LIBPFM_ARRAY_SIZE(snb_inst_retired), .ngrp = 1, .umasks = snb_inst_retired, }, { .name = "INSTRUCTION_RETIRED", .desc = "Number of instructions at retirement", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x10000000full, .code = 0xc0, }, { .name = "INSTRUCTIONS_RETIRED", .desc = "This is an alias for INSTRUCTION_RETIRED", .modmsk = INTEL_V3_ATTRS, .equiv = "INSTRUCTION_RETIRED", .cntmsk = 0x10000000full, .code = 0xc0, }, { .name = "INT_MISC", .desc = "Miscellaneous internals", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xd, .numasks = LIBPFM_ARRAY_SIZE(snb_int_misc), .ngrp = 1, .umasks = snb_int_misc, }, { .name = "ITLB", .desc = "Instruction TLB", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xae, .numasks = LIBPFM_ARRAY_SIZE(snb_itlb), .ngrp = 1, .umasks = snb_itlb, }, { .name = "ITLB_MISSES", .desc = "Instruction TLB misses", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0x85, .numasks = LIBPFM_ARRAY_SIZE(snb_dtlb_store_misses), .ngrp = 1, .umasks = snb_dtlb_store_misses, /* identical to actual umasks list for this event */ }, { .name = "L1D", .desc = "L1D cache", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0x51, .numasks = LIBPFM_ARRAY_SIZE(snb_l1d), .ngrp = 1, .umasks = snb_l1d, }, { .name = "L1D_BLOCKS", .desc = "L1D is blocking", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xbf, .numasks = LIBPFM_ARRAY_SIZE(snb_l1d_blocks), .ngrp = 1, .umasks = snb_l1d_blocks, }, { .name = "L1D_PEND_MISS", .desc = "L1D pending misses", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x4, .code = 0x48, .numasks = LIBPFM_ARRAY_SIZE(snb_l1d_pend_miss), .ngrp = 1, .umasks = snb_l1d_pend_miss, }, { .name = "L2_L1D_WB_RQSTS", .desc = "Writeback requests from L1D to L2", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0x28, .numasks = LIBPFM_ARRAY_SIZE(snb_l2_l1d_wb_rqsts), .ngrp = 1, .umasks = snb_l2_l1d_wb_rqsts, }, { .name = "L2_LINES_IN", .desc = "L2 lines allocated", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xf1, .numasks = LIBPFM_ARRAY_SIZE(snb_l2_lines_in), .ngrp = 1, .umasks = snb_l2_lines_in, }, { .name = "L2_LINES_OUT", .desc = "L2 lines evicted", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xf2, .numasks = LIBPFM_ARRAY_SIZE(snb_l2_lines_out), .ngrp = 1, .umasks = snb_l2_lines_out, }, { .name = "L2_RQSTS", .desc = "L2 requests", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0x24, .numasks = LIBPFM_ARRAY_SIZE(snb_l2_rqsts), .ngrp = 1, .umasks = snb_l2_rqsts, }, { .name = "L2_STORE_LOCK_RQSTS", .desc = "L2 store lock requests", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0x27, .numasks = LIBPFM_ARRAY_SIZE(snb_l2_store_lock_rqsts), .ngrp = 1, .umasks = snb_l2_store_lock_rqsts, }, { .name = "L2_TRANS", .desc = "L2 transactions", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xf0, .numasks = LIBPFM_ARRAY_SIZE(snb_l2_trans), .ngrp = 1, .umasks = snb_l2_trans, }, { .name = "LAST_LEVEL_CACHE_MISSES", .desc = "This is an alias for L3_LAT_CACHE:MISS", .modmsk = INTEL_V3_ATTRS, .equiv = "L3_LAT_CACHE:MISS", .cntmsk = 0xff, .code = 0x412e, }, { .name = "LLC_MISSES", .desc = "Alias for LAST_LEVEL_CACHE_MISSES", .modmsk = INTEL_V3_ATTRS, .equiv = "LAST_LEVEL_CACHE_MISSES", .cntmsk = 0xff, .code = 0x412e, }, { .name = "LAST_LEVEL_CACHE_REFERENCES", .desc = "This is an alias for L3_LAT_CACHE:REFERENCE", .modmsk = INTEL_V3_ATTRS, .equiv = "L3_LAT_CACHE:REFERENCE", .cntmsk = 0xff, .code = 0x4f2e, }, { .name = "LLC_REFERENCES", .desc = "Alias for LAST_LEVEL_CACHE_REFERENCES", .modmsk = INTEL_V3_ATTRS, .equiv = "LAST_LEVEL_CACHE_REFERENCES", .cntmsk = 0xff, .code = 0x4f2e, }, { .name = "LD_BLOCKS", .desc = "Blocking loads", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0x3, .numasks = LIBPFM_ARRAY_SIZE(snb_ld_blocks), .ngrp = 1, .umasks = snb_ld_blocks, }, { .name = "LD_BLOCKS_PARTIAL", .desc = "Partial load blocks", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0x7, .numasks = LIBPFM_ARRAY_SIZE(snb_ld_blocks_partial), .ngrp = 1, .umasks = snb_ld_blocks_partial, }, { .name = "LOAD_HIT_PRE", .desc = "Load dispatches that hit fill buffer", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0x4c, .numasks = LIBPFM_ARRAY_SIZE(snb_load_hit_pre), .ngrp = 1, .umasks = snb_load_hit_pre, }, { .name = "L3_LAT_CACHE", .desc = "Core-originated cacheable demand requests to L3", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0x2e, .numasks = LIBPFM_ARRAY_SIZE(snb_l3_lat_cache), .ngrp = 1, .umasks = snb_l3_lat_cache, }, { .name = "MACHINE_CLEARS", .desc = "Machine clear asserted", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xc3, .numasks = LIBPFM_ARRAY_SIZE(snb_machine_clears), .ngrp = 1, .umasks = snb_machine_clears, }, { .name = "MEM_LOAD_UOPS_LLC_HIT_RETIRED", .desc = "L3 hit loads uops retired", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xd2, .flags= INTEL_X86_PEBS, .numasks = LIBPFM_ARRAY_SIZE(snb_mem_load_uops_llc_hit_retired), .ngrp = 1, .umasks = snb_mem_load_uops_llc_hit_retired, }, { .name = "MEM_LOAD_LLC_HIT_RETIRED", .desc = "L3 hit loads uops retired (deprecated use MEM_LOAD_UOPS_LLC_HIT_RETIRED)", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xd2, .equiv = "MEM_LOAD_UOPS_LLC_HIT_RETIRED", .flags= INTEL_X86_PEBS, .numasks = LIBPFM_ARRAY_SIZE(snb_mem_load_uops_llc_hit_retired), .ngrp = 1, .umasks = snb_mem_load_uops_llc_hit_retired, }, { .name = "MEM_LOAD_UOPS_MISC_RETIRED", .desc = "Loads and some non simd split loads uops retired", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xd4, .flags= INTEL_X86_PEBS, .numasks = LIBPFM_ARRAY_SIZE(snb_mem_load_uops_misc_retired), .ngrp = 1, .umasks = snb_mem_load_uops_misc_retired, }, { .name = "MEM_LOAD_MISC_RETIRED", .desc = "Loads and some non simd split loads uops retired (deprecated use MEM_LOAD_UOPS_MISC_RETIRED)", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xd4, .equiv = "MEM_LOAD_UOPS_MISC_RETIRED", .flags= INTEL_X86_PEBS, .numasks = LIBPFM_ARRAY_SIZE(snb_mem_load_uops_misc_retired), .ngrp = 1, .umasks = snb_mem_load_uops_misc_retired, }, { .name = "MEM_LOAD_UOPS_RETIRED", .desc = "Memory loads uops retired", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xd1, .flags= INTEL_X86_PEBS, .numasks = LIBPFM_ARRAY_SIZE(snb_mem_load_uops_retired), .ngrp = 1, .umasks = snb_mem_load_uops_retired, }, { .name = "MEM_LOAD_RETIRED", .desc = "Memory loads uops retired (deprecated use MEM_LOAD_UOPS_RETIRED)", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xd1, .equiv = "MEM_LOAD_UOPS_RETIRED", .flags= INTEL_X86_PEBS, .numasks = LIBPFM_ARRAY_SIZE(snb_mem_load_uops_retired), .ngrp = 1, .umasks = snb_mem_load_uops_retired, }, { .name = "MEM_TRANS_RETIRED", .desc = "Memory transactions retired", .modmsk = INTEL_V3_ATTRS | _INTEL_X86_ATTR_LDLAT, .cntmsk = 0x8, .code = 0xcd, .flags= INTEL_X86_PEBS, .numasks = LIBPFM_ARRAY_SIZE(snb_mem_trans_retired), .ngrp = 1, .umasks = snb_mem_trans_retired, }, { .name = "MEM_UOPS_RETIRED", .desc = "Memory uops retired", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xd0, .flags= INTEL_X86_PEBS, .numasks = LIBPFM_ARRAY_SIZE(snb_mem_uops_retired), .ngrp = 1, .umasks = snb_mem_uops_retired, }, { .name = "MEM_UOP_RETIRED", .desc = "Memory uops retired (deprecated use MEM_UOPS_RETIRED)", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xd0, .equiv = "MEM_UOPS_RETIRED", .flags= INTEL_X86_PEBS, .numasks = LIBPFM_ARRAY_SIZE(snb_mem_uops_retired), .ngrp = 1, .umasks = snb_mem_uops_retired, }, { .name = "MISALIGN_MEM_REF", .desc = "Misaligned memory references", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0x5, .numasks = LIBPFM_ARRAY_SIZE(snb_misalign_mem_ref), .ngrp = 1, .umasks = snb_misalign_mem_ref, }, { .name = "OFFCORE_REQUESTS", .desc = "Offcore requests", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xb0, .numasks = LIBPFM_ARRAY_SIZE(snb_offcore_requests), .ngrp = 1, .umasks = snb_offcore_requests, }, { .name = "OFFCORE_REQUESTS_BUFFER", .desc = "Offcore requests buffer", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xb2, .numasks = LIBPFM_ARRAY_SIZE(snb_offcore_requests_buffer), .ngrp = 1, .umasks = snb_offcore_requests_buffer, }, { .name = "OFFCORE_REQUESTS_OUTSTANDING", .desc = "Outstanding offcore requests", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0x60, .numasks = LIBPFM_ARRAY_SIZE(snb_offcore_requests_outstanding), .ngrp = 1, .umasks = snb_offcore_requests_outstanding, }, { .name = "OTHER_ASSISTS", .desc = "Count hardware assists", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xc1, .numasks = LIBPFM_ARRAY_SIZE(snb_other_assists), .ngrp = 1, .umasks = snb_other_assists, }, { .name = "PARTIAL_RAT_STALLS", .desc = "Partial Register Allocation Table stalls", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0x59, .numasks = LIBPFM_ARRAY_SIZE(snb_partial_rat_stalls), .ngrp = 1, .umasks = snb_partial_rat_stalls, }, { .name = "RESOURCE_STALLS", .desc = "Resource related stall cycles", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xa2, .numasks = LIBPFM_ARRAY_SIZE(snb_resource_stalls), .ngrp = 1, .umasks = snb_resource_stalls, }, { .name = "RESOURCE_STALLS2", .desc = "Resource related stall cycles", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0x5b, .numasks = LIBPFM_ARRAY_SIZE(snb_resource_stalls2), .ngrp = 1, .umasks = snb_resource_stalls2, }, { .name = "ROB_MISC_EVENTS", .desc = "Reorder buffer events", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xcc, .numasks = LIBPFM_ARRAY_SIZE(snb_rob_misc_events), .ngrp = 1, .umasks = snb_rob_misc_events, }, { .name = "RS_EVENTS", .desc = "Reservation station events", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0x5e, .numasks = LIBPFM_ARRAY_SIZE(snb_rs_events), .ngrp = 1, .umasks = snb_rs_events, }, { .name = "SIMD_FP_256", .desc = "Counts 256-bit packed floating point instructions", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0x11, .numasks = LIBPFM_ARRAY_SIZE(snb_simd_fp_256), .ngrp = 1, .umasks = snb_simd_fp_256, }, { .name = "SQ_MISC", .desc = "SuperQ events", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xf4, .numasks = LIBPFM_ARRAY_SIZE(snb_sq_misc), .ngrp = 1, .umasks = snb_sq_misc, }, { .name = "TLB_FLUSH", .desc = "TLB flushes", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xbd, .numasks = LIBPFM_ARRAY_SIZE(snb_tlb_flush), .ngrp = 1, .umasks = snb_tlb_flush, }, { .name = "UNHALTED_CORE_CYCLES", .desc = "Count core clock cycles whenever the clock signal on the specific core is running (not halted)", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0x20000000full, .code = 0x3c, }, { .name = "UNHALTED_REFERENCE_CYCLES", .desc = "Unhalted reference cycles", .modmsk = INTEL_FIXED3_ATTRS, .cntmsk = 0x400000000ull, .code = 0x0300, /* pseudo encoding */ .flags = INTEL_X86_FIXED, }, { .name = "UOPS_EXECUTED", .desc = "Uops executed", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xb1, .numasks = LIBPFM_ARRAY_SIZE(snb_uops_executed), .ngrp = 1, .umasks = snb_uops_executed, }, { .name = "UOPS_DISPATCHED_PORT", .desc = "Uops dispatch to specific ports", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xa1, .numasks = LIBPFM_ARRAY_SIZE(snb_uops_dispatched_port), .ngrp = 1, .umasks = snb_uops_dispatched_port, }, { .name = "UOPS_ISSUED", .desc = "Uops issued", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xe, .numasks = LIBPFM_ARRAY_SIZE(snb_uops_issued), .ngrp = 1, .umasks = snb_uops_issued, }, { .name = "UOPS_RETIRED", .desc = "Uops retired", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xc2, .flags= INTEL_X86_PEBS, .numasks = LIBPFM_ARRAY_SIZE(snb_uops_retired), .ngrp = 1, .umasks = snb_uops_retired, }, { .name = "CYCLE_ACTIVITY", .desc = "Stalled cycles", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xa3, .numasks = LIBPFM_ARRAY_SIZE(snb_cycle_activity), .ngrp = 1, .umasks = snb_cycle_activity, }, { .name = "EPT", .desc = "Extended page table", .modmsk = INTEL_V4_ATTRS, .cntmsk = 0xff, .code = 0x4f, .numasks = LIBPFM_ARRAY_SIZE(snb_ept), .ngrp = 1, .umasks = snb_ept, }, { .name = "LSD", .desc = "Loop stream detector", .code = 0xa8, .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(snb_lsd), .umasks = snb_lsd, }, { .name = "PAGE_WALKS", .desc = "page walker", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xbe, .numasks = LIBPFM_ARRAY_SIZE(snb_page_walks), .ngrp = 1, .umasks = snb_page_walks, }, { .name = "MEM_LOAD_UOPS_LLC_MISS_RETIRED", .desc = "Load uops retired which miss the L3 cache", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xd3, .flags= INTEL_X86_PEBS, .numasks = LIBPFM_ARRAY_SIZE(snb_mem_load_uops_llc_miss_retired), .ngrp = 1, .umasks = snb_mem_load_uops_llc_miss_retired, }, { .name = "OFFCORE_RESPONSE_0", .desc = "Offcore response event (must provide at least one request type and either any_response or any combination of supplier + snoop)", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x1b7, .flags= INTEL_X86_NHM_OFFCORE, .numasks = LIBPFM_ARRAY_SIZE(snb_offcore_response), .ngrp = 3, .umasks = snb_offcore_response, }, { .name = "OFFCORE_RESPONSE_1", .desc = "Offcore response event (must provide at least one request type and either any_response or any combination of supplier + snoop)", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xf, .code = 0x1bb, .flags= INTEL_X86_NHM_OFFCORE, .numasks = LIBPFM_ARRAY_SIZE(snb_offcore_response), .ngrp = 3, .umasks = snb_offcore_response, /* identical to actual umasks list for this event */ }, }; libpfm-4.9.0/lib/events/power9_events.h0000664000175000017500000125441413223402656017665 0ustar eranianeranian/* * File: power9_events.h * CVS: * Author: Will Schmidt * will_schmidt@vnet.ibm.com * Author: Carl Love * cel@us.ibm.com * * Mods: * Initial content generated by Will Schmidt. (Jan 31, 2017). * Refresh/update generated Jun 06, 2017 by Will Schmidt. * missing _ALT events added, Nov 16, 2017 by Will Schmidt. * * Contributed by * (C) Copyright IBM Corporation, 2017. All Rights Reserved. * * Note: This code was automatically generated and should not be modified by * hand. * * Documentation on the PMU events will be published at: * ... */ #ifndef __POWER9_EVENTS_H__ #define __POWER9_EVENTS_H__ #define POWER9_PME_PM_1FLOP_CMPL 0 #define POWER9_PME_PM_1PLUS_PPC_CMPL 1 #define POWER9_PME_PM_1PLUS_PPC_DISP 2 #define POWER9_PME_PM_2FLOP_CMPL 3 #define POWER9_PME_PM_4FLOP_CMPL 4 #define POWER9_PME_PM_8FLOP_CMPL 5 #define POWER9_PME_PM_ANY_THRD_RUN_CYC 6 #define POWER9_PME_PM_BACK_BR_CMPL 7 #define POWER9_PME_PM_BANK_CONFLICT 8 #define POWER9_PME_PM_BFU_BUSY 9 #define POWER9_PME_PM_BR_2PATH 10 #define POWER9_PME_PM_BR_CMPL 11 #define POWER9_PME_PM_BR_CORECT_PRED_TAKEN_CMPL 12 #define POWER9_PME_PM_BR_MPRED_CCACHE 13 #define POWER9_PME_PM_BR_MPRED_CMPL 14 #define POWER9_PME_PM_BR_MPRED_LSTACK 15 #define POWER9_PME_PM_BR_MPRED_PCACHE 16 #define POWER9_PME_PM_BR_MPRED_TAKEN_CR 17 #define POWER9_PME_PM_BR_MPRED_TAKEN_TA 18 #define POWER9_PME_PM_BR_PRED_CCACHE 19 #define POWER9_PME_PM_BR_PRED_LSTACK 20 #define POWER9_PME_PM_BR_PRED_PCACHE 21 #define POWER9_PME_PM_BR_PRED_TAKEN_CR 22 #define POWER9_PME_PM_BR_PRED_TA 23 #define POWER9_PME_PM_BR_PRED 24 #define POWER9_PME_PM_BR_TAKEN_CMPL 25 #define POWER9_PME_PM_BRU_FIN 26 #define POWER9_PME_PM_BR_UNCOND 27 #define POWER9_PME_PM_BTAC_BAD_RESULT 28 #define POWER9_PME_PM_BTAC_GOOD_RESULT 29 #define POWER9_PME_PM_CHIP_PUMP_CPRED 30 #define POWER9_PME_PM_CLB_HELD 31 #define POWER9_PME_PM_CMPLU_STALL_ANY_SYNC 32 #define POWER9_PME_PM_CMPLU_STALL_BRU 33 #define POWER9_PME_PM_CMPLU_STALL_CRYPTO 34 #define POWER9_PME_PM_CMPLU_STALL_DCACHE_MISS 35 #define POWER9_PME_PM_CMPLU_STALL_DFLONG 36 #define POWER9_PME_PM_CMPLU_STALL_DFU 37 #define POWER9_PME_PM_CMPLU_STALL_DMISS_L21_L31 38 #define POWER9_PME_PM_CMPLU_STALL_DMISS_L2L3_CONFLICT 39 #define POWER9_PME_PM_CMPLU_STALL_DMISS_L2L3 40 #define POWER9_PME_PM_CMPLU_STALL_DMISS_L3MISS 41 #define POWER9_PME_PM_CMPLU_STALL_DMISS_LMEM 42 #define POWER9_PME_PM_CMPLU_STALL_DMISS_REMOTE 43 #define POWER9_PME_PM_CMPLU_STALL_DPLONG 44 #define POWER9_PME_PM_CMPLU_STALL_DP 45 #define POWER9_PME_PM_CMPLU_STALL_EIEIO 46 #define POWER9_PME_PM_CMPLU_STALL_EMQ_FULL 47 #define POWER9_PME_PM_CMPLU_STALL_ERAT_MISS 48 #define POWER9_PME_PM_CMPLU_STALL_EXCEPTION 49 #define POWER9_PME_PM_CMPLU_STALL_EXEC_UNIT 50 #define POWER9_PME_PM_CMPLU_STALL_FLUSH_ANY_THREAD 51 #define POWER9_PME_PM_CMPLU_STALL_FXLONG 52 #define POWER9_PME_PM_CMPLU_STALL_FXU 53 #define POWER9_PME_PM_CMPLU_STALL_HWSYNC 54 #define POWER9_PME_PM_CMPLU_STALL_LARX 55 #define POWER9_PME_PM_CMPLU_STALL_LHS 56 #define POWER9_PME_PM_CMPLU_STALL_LMQ_FULL 57 #define POWER9_PME_PM_CMPLU_STALL_LOAD_FINISH 58 #define POWER9_PME_PM_CMPLU_STALL_LRQ_FULL 59 #define POWER9_PME_PM_CMPLU_STALL_LRQ_OTHER 60 #define POWER9_PME_PM_CMPLU_STALL_LSAQ_ARB 61 #define POWER9_PME_PM_CMPLU_STALL_LSU_FIN 62 #define POWER9_PME_PM_CMPLU_STALL_LSU_FLUSH_NEXT 63 #define POWER9_PME_PM_CMPLU_STALL_LSU_MFSPR 64 #define POWER9_PME_PM_CMPLU_STALL_LSU 65 #define POWER9_PME_PM_CMPLU_STALL_LWSYNC 66 #define POWER9_PME_PM_CMPLU_STALL_MTFPSCR 67 #define POWER9_PME_PM_CMPLU_STALL_NESTED_TBEGIN 68 #define POWER9_PME_PM_CMPLU_STALL_NESTED_TEND 69 #define POWER9_PME_PM_CMPLU_STALL_NTC_DISP_FIN 70 #define POWER9_PME_PM_CMPLU_STALL_NTC_FLUSH 71 #define POWER9_PME_PM_CMPLU_STALL_OTHER_CMPL 72 #define POWER9_PME_PM_CMPLU_STALL_PASTE 73 #define POWER9_PME_PM_CMPLU_STALL_PM 74 #define POWER9_PME_PM_CMPLU_STALL_SLB 75 #define POWER9_PME_PM_CMPLU_STALL_SPEC_FINISH 76 #define POWER9_PME_PM_CMPLU_STALL_SRQ_FULL 77 #define POWER9_PME_PM_CMPLU_STALL_STCX 78 #define POWER9_PME_PM_CMPLU_STALL_ST_FWD 79 #define POWER9_PME_PM_CMPLU_STALL_STORE_DATA 80 #define POWER9_PME_PM_CMPLU_STALL_STORE_FIN_ARB 81 #define POWER9_PME_PM_CMPLU_STALL_STORE_FINISH 82 #define POWER9_PME_PM_CMPLU_STALL_STORE_PIPE_ARB 83 #define POWER9_PME_PM_CMPLU_STALL_SYNC_PMU_INT 84 #define POWER9_PME_PM_CMPLU_STALL_TEND 85 #define POWER9_PME_PM_CMPLU_STALL_THRD 86 #define POWER9_PME_PM_CMPLU_STALL_TLBIE 87 #define POWER9_PME_PM_CMPLU_STALL 88 #define POWER9_PME_PM_CMPLU_STALL_VDPLONG 89 #define POWER9_PME_PM_CMPLU_STALL_VDP 90 #define POWER9_PME_PM_CMPLU_STALL_VFXLONG 91 #define POWER9_PME_PM_CMPLU_STALL_VFXU 92 #define POWER9_PME_PM_CO0_BUSY 93 #define POWER9_PME_PM_CO0_BUSY_ALT 94 #define POWER9_PME_PM_CO_DISP_FAIL 95 #define POWER9_PME_PM_CO_TM_SC_FOOTPRINT 96 #define POWER9_PME_PM_CO_USAGE 97 #define POWER9_PME_PM_CYC 98 #define POWER9_PME_PM_DARQ0_0_3_ENTRIES 99 #define POWER9_PME_PM_DARQ0_10_12_ENTRIES 100 #define POWER9_PME_PM_DARQ0_4_6_ENTRIES 101 #define POWER9_PME_PM_DARQ0_7_9_ENTRIES 102 #define POWER9_PME_PM_DARQ1_0_3_ENTRIES 103 #define POWER9_PME_PM_DARQ1_10_12_ENTRIES 104 #define POWER9_PME_PM_DARQ1_4_6_ENTRIES 105 #define POWER9_PME_PM_DARQ1_7_9_ENTRIES 106 #define POWER9_PME_PM_DARQ_STORE_REJECT 107 #define POWER9_PME_PM_DARQ_STORE_XMIT 108 #define POWER9_PME_PM_DATA_CHIP_PUMP_CPRED 109 #define POWER9_PME_PM_DATA_FROM_DL2L3_MOD 110 #define POWER9_PME_PM_DATA_FROM_DL2L3_SHR 111 #define POWER9_PME_PM_DATA_FROM_DL4 112 #define POWER9_PME_PM_DATA_FROM_DMEM 113 #define POWER9_PME_PM_DATA_FROM_L21_MOD 114 #define POWER9_PME_PM_DATA_FROM_L21_SHR 115 #define POWER9_PME_PM_DATA_FROM_L2_DISP_CONFLICT_LDHITST 116 #define POWER9_PME_PM_DATA_FROM_L2_DISP_CONFLICT_OTHER 117 #define POWER9_PME_PM_DATA_FROM_L2_MEPF 118 #define POWER9_PME_PM_DATA_FROM_L2MISS_MOD 119 #define POWER9_PME_PM_DATA_FROM_L2MISS 120 #define POWER9_PME_PM_DATA_FROM_L2_NO_CONFLICT 121 #define POWER9_PME_PM_DATA_FROM_L2 122 #define POWER9_PME_PM_DATA_FROM_L31_ECO_MOD 123 #define POWER9_PME_PM_DATA_FROM_L31_ECO_SHR 124 #define POWER9_PME_PM_DATA_FROM_L31_MOD 125 #define POWER9_PME_PM_DATA_FROM_L31_SHR 126 #define POWER9_PME_PM_DATA_FROM_L3_DISP_CONFLICT 127 #define POWER9_PME_PM_DATA_FROM_L3_MEPF 128 #define POWER9_PME_PM_DATA_FROM_L3MISS_MOD 129 #define POWER9_PME_PM_DATA_FROM_L3MISS 130 #define POWER9_PME_PM_DATA_FROM_L3_NO_CONFLICT 131 #define POWER9_PME_PM_DATA_FROM_L3 132 #define POWER9_PME_PM_DATA_FROM_LL4 133 #define POWER9_PME_PM_DATA_FROM_LMEM 134 #define POWER9_PME_PM_DATA_FROM_MEMORY 135 #define POWER9_PME_PM_DATA_FROM_OFF_CHIP_CACHE 136 #define POWER9_PME_PM_DATA_FROM_ON_CHIP_CACHE 137 #define POWER9_PME_PM_DATA_FROM_RL2L3_MOD 138 #define POWER9_PME_PM_DATA_FROM_RL2L3_SHR 139 #define POWER9_PME_PM_DATA_FROM_RL4 140 #define POWER9_PME_PM_DATA_FROM_RMEM 141 #define POWER9_PME_PM_DATA_GRP_PUMP_CPRED 142 #define POWER9_PME_PM_DATA_GRP_PUMP_MPRED_RTY 143 #define POWER9_PME_PM_DATA_GRP_PUMP_MPRED 144 #define POWER9_PME_PM_DATA_PUMP_CPRED 145 #define POWER9_PME_PM_DATA_PUMP_MPRED 146 #define POWER9_PME_PM_DATA_STORE 147 #define POWER9_PME_PM_DATA_SYS_PUMP_CPRED 148 #define POWER9_PME_PM_DATA_SYS_PUMP_MPRED_RTY 149 #define POWER9_PME_PM_DATA_SYS_PUMP_MPRED 150 #define POWER9_PME_PM_DATA_TABLEWALK_CYC 151 #define POWER9_PME_PM_DC_DEALLOC_NO_CONF 152 #define POWER9_PME_PM_DC_PREF_CONF 153 #define POWER9_PME_PM_DC_PREF_CONS_ALLOC 154 #define POWER9_PME_PM_DC_PREF_FUZZY_CONF 155 #define POWER9_PME_PM_DC_PREF_HW_ALLOC 156 #define POWER9_PME_PM_DC_PREF_STRIDED_CONF 157 #define POWER9_PME_PM_DC_PREF_SW_ALLOC 158 #define POWER9_PME_PM_DC_PREF_XCONS_ALLOC 159 #define POWER9_PME_PM_DECODE_FUSION_CONST_GEN 160 #define POWER9_PME_PM_DECODE_FUSION_EXT_ADD 161 #define POWER9_PME_PM_DECODE_FUSION_LD_ST_DISP 162 #define POWER9_PME_PM_DECODE_FUSION_OP_PRESERV 163 #define POWER9_PME_PM_DECODE_HOLD_ICT_FULL 164 #define POWER9_PME_PM_DECODE_LANES_NOT_AVAIL 165 #define POWER9_PME_PM_DERAT_MISS_16G 166 #define POWER9_PME_PM_DERAT_MISS_16M 167 #define POWER9_PME_PM_DERAT_MISS_1G 168 #define POWER9_PME_PM_DERAT_MISS_2M 169 #define POWER9_PME_PM_DERAT_MISS_4K 170 #define POWER9_PME_PM_DERAT_MISS_64K 171 #define POWER9_PME_PM_DFU_BUSY 172 #define POWER9_PME_PM_DISP_CLB_HELD_BAL 173 #define POWER9_PME_PM_DISP_CLB_HELD_SB 174 #define POWER9_PME_PM_DISP_CLB_HELD_TLBIE 175 #define POWER9_PME_PM_DISP_HELD_HB_FULL 176 #define POWER9_PME_PM_DISP_HELD_ISSQ_FULL 177 #define POWER9_PME_PM_DISP_HELD_SYNC_HOLD 178 #define POWER9_PME_PM_DISP_HELD_TBEGIN 179 #define POWER9_PME_PM_DISP_HELD 180 #define POWER9_PME_PM_DISP_STARVED 181 #define POWER9_PME_PM_DP_QP_FLOP_CMPL 182 #define POWER9_PME_PM_DPTEG_FROM_DL2L3_MOD 183 #define POWER9_PME_PM_DPTEG_FROM_DL2L3_SHR 184 #define POWER9_PME_PM_DPTEG_FROM_DL4 185 #define POWER9_PME_PM_DPTEG_FROM_DMEM 186 #define POWER9_PME_PM_DPTEG_FROM_L21_MOD 187 #define POWER9_PME_PM_DPTEG_FROM_L21_SHR 188 #define POWER9_PME_PM_DPTEG_FROM_L2_MEPF 189 #define POWER9_PME_PM_DPTEG_FROM_L2MISS 190 #define POWER9_PME_PM_DPTEG_FROM_L2_NO_CONFLICT 191 #define POWER9_PME_PM_DPTEG_FROM_L2 192 #define POWER9_PME_PM_DPTEG_FROM_L31_ECO_MOD 193 #define POWER9_PME_PM_DPTEG_FROM_L31_ECO_SHR 194 #define POWER9_PME_PM_DPTEG_FROM_L31_MOD 195 #define POWER9_PME_PM_DPTEG_FROM_L31_SHR 196 #define POWER9_PME_PM_DPTEG_FROM_L3_DISP_CONFLICT 197 #define POWER9_PME_PM_DPTEG_FROM_L3_MEPF 198 #define POWER9_PME_PM_DPTEG_FROM_L3MISS 199 #define POWER9_PME_PM_DPTEG_FROM_L3_NO_CONFLICT 200 #define POWER9_PME_PM_DPTEG_FROM_L3 201 #define POWER9_PME_PM_DPTEG_FROM_LL4 202 #define POWER9_PME_PM_DPTEG_FROM_LMEM 203 #define POWER9_PME_PM_DPTEG_FROM_MEMORY 204 #define POWER9_PME_PM_DPTEG_FROM_OFF_CHIP_CACHE 205 #define POWER9_PME_PM_DPTEG_FROM_ON_CHIP_CACHE 206 #define POWER9_PME_PM_DPTEG_FROM_RL2L3_MOD 207 #define POWER9_PME_PM_DPTEG_FROM_RL2L3_SHR 208 #define POWER9_PME_PM_DPTEG_FROM_RL4 209 #define POWER9_PME_PM_DPTEG_FROM_RMEM 210 #define POWER9_PME_PM_DSIDE_L2MEMACC 211 #define POWER9_PME_PM_DSIDE_MRU_TOUCH 212 #define POWER9_PME_PM_DSIDE_OTHER_64B_L2MEMACC 213 #define POWER9_PME_PM_DSLB_MISS 214 #define POWER9_PME_PM_DSLB_MISS_ALT 215 #define POWER9_PME_PM_DTLB_MISS_16G 216 #define POWER9_PME_PM_DTLB_MISS_16M 217 #define POWER9_PME_PM_DTLB_MISS_1G 218 #define POWER9_PME_PM_DTLB_MISS_2M 219 #define POWER9_PME_PM_DTLB_MISS_4K 220 #define POWER9_PME_PM_DTLB_MISS_64K 221 #define POWER9_PME_PM_DTLB_MISS 222 #define POWER9_PME_PM_SPACEHOLDER_0000040062 223 #define POWER9_PME_PM_SPACEHOLDER_0000040064 224 #define POWER9_PME_PM_EAT_FORCE_MISPRED 225 #define POWER9_PME_PM_EAT_FULL_CYC 226 #define POWER9_PME_PM_EE_OFF_EXT_INT 227 #define POWER9_PME_PM_EXT_INT 228 #define POWER9_PME_PM_FLOP_CMPL 229 #define POWER9_PME_PM_FLUSH_COMPLETION 230 #define POWER9_PME_PM_FLUSH_DISP_SB 231 #define POWER9_PME_PM_FLUSH_DISP_TLBIE 232 #define POWER9_PME_PM_FLUSH_DISP 233 #define POWER9_PME_PM_FLUSH_HB_RESTORE_CYC 234 #define POWER9_PME_PM_FLUSH_LSU 235 #define POWER9_PME_PM_FLUSH_MPRED 236 #define POWER9_PME_PM_FLUSH 237 #define POWER9_PME_PM_FMA_CMPL 238 #define POWER9_PME_PM_FORCED_NOP 239 #define POWER9_PME_PM_FREQ_DOWN 240 #define POWER9_PME_PM_FREQ_UP 241 #define POWER9_PME_PM_FXU_1PLUS_BUSY 242 #define POWER9_PME_PM_FXU_BUSY 243 #define POWER9_PME_PM_FXU_FIN 244 #define POWER9_PME_PM_FXU_IDLE 245 #define POWER9_PME_PM_GRP_PUMP_CPRED 246 #define POWER9_PME_PM_GRP_PUMP_MPRED_RTY 247 #define POWER9_PME_PM_GRP_PUMP_MPRED 248 #define POWER9_PME_PM_HV_CYC 249 #define POWER9_PME_PM_HWSYNC 250 #define POWER9_PME_PM_IBUF_FULL_CYC 251 #define POWER9_PME_PM_IC_DEMAND_CYC 252 #define POWER9_PME_PM_IC_DEMAND_L2_BHT_REDIRECT 253 #define POWER9_PME_PM_IC_DEMAND_L2_BR_REDIRECT 254 #define POWER9_PME_PM_IC_DEMAND_REQ 255 #define POWER9_PME_PM_IC_INVALIDATE 256 #define POWER9_PME_PM_IC_MISS_CMPL 257 #define POWER9_PME_PM_IC_MISS_ICBI 258 #define POWER9_PME_PM_IC_PREF_CANCEL_HIT 259 #define POWER9_PME_PM_IC_PREF_CANCEL_L2 260 #define POWER9_PME_PM_IC_PREF_CANCEL_PAGE 261 #define POWER9_PME_PM_IC_PREF_REQ 262 #define POWER9_PME_PM_IC_PREF_WRITE 263 #define POWER9_PME_PM_IC_RELOAD_PRIVATE 264 #define POWER9_PME_PM_ICT_EMPTY_CYC 265 #define POWER9_PME_PM_ICT_NOSLOT_BR_MPRED_ICMISS 266 #define POWER9_PME_PM_ICT_NOSLOT_BR_MPRED 267 #define POWER9_PME_PM_ICT_NOSLOT_CYC 268 #define POWER9_PME_PM_ICT_NOSLOT_DISP_HELD_HB_FULL 269 #define POWER9_PME_PM_ICT_NOSLOT_DISP_HELD_ISSQ 270 #define POWER9_PME_PM_ICT_NOSLOT_DISP_HELD_SYNC 271 #define POWER9_PME_PM_ICT_NOSLOT_DISP_HELD_TBEGIN 272 #define POWER9_PME_PM_ICT_NOSLOT_DISP_HELD 273 #define POWER9_PME_PM_ICT_NOSLOT_IC_L3MISS 274 #define POWER9_PME_PM_ICT_NOSLOT_IC_L3 275 #define POWER9_PME_PM_ICT_NOSLOT_IC_MISS 276 #define POWER9_PME_PM_IERAT_RELOAD_16M 277 #define POWER9_PME_PM_IERAT_RELOAD_4K 278 #define POWER9_PME_PM_IERAT_RELOAD_64K 279 #define POWER9_PME_PM_IERAT_RELOAD 280 #define POWER9_PME_PM_IFETCH_THROTTLE 281 #define POWER9_PME_PM_INST_CHIP_PUMP_CPRED 282 #define POWER9_PME_PM_INST_CMPL 283 #define POWER9_PME_PM_INST_DISP 284 #define POWER9_PME_PM_INST_FROM_DL2L3_MOD 285 #define POWER9_PME_PM_INST_FROM_DL2L3_SHR 286 #define POWER9_PME_PM_INST_FROM_DL4 287 #define POWER9_PME_PM_INST_FROM_DMEM 288 #define POWER9_PME_PM_INST_FROM_L1 289 #define POWER9_PME_PM_INST_FROM_L21_MOD 290 #define POWER9_PME_PM_INST_FROM_L21_SHR 291 #define POWER9_PME_PM_INST_FROM_L2_DISP_CONFLICT_LDHITST 292 #define POWER9_PME_PM_INST_FROM_L2_DISP_CONFLICT_OTHER 293 #define POWER9_PME_PM_INST_FROM_L2_MEPF 294 #define POWER9_PME_PM_INST_FROM_L2MISS 295 #define POWER9_PME_PM_INST_FROM_L2_NO_CONFLICT 296 #define POWER9_PME_PM_INST_FROM_L2 297 #define POWER9_PME_PM_INST_FROM_L31_ECO_MOD 298 #define POWER9_PME_PM_INST_FROM_L31_ECO_SHR 299 #define POWER9_PME_PM_INST_FROM_L31_MOD 300 #define POWER9_PME_PM_INST_FROM_L31_SHR 301 #define POWER9_PME_PM_INST_FROM_L3_DISP_CONFLICT 302 #define POWER9_PME_PM_INST_FROM_L3_MEPF 303 #define POWER9_PME_PM_INST_FROM_L3MISS_MOD 304 #define POWER9_PME_PM_INST_FROM_L3MISS 305 #define POWER9_PME_PM_INST_FROM_L3_NO_CONFLICT 306 #define POWER9_PME_PM_INST_FROM_L3 307 #define POWER9_PME_PM_INST_FROM_LL4 308 #define POWER9_PME_PM_INST_FROM_LMEM 309 #define POWER9_PME_PM_INST_FROM_MEMORY 310 #define POWER9_PME_PM_INST_FROM_OFF_CHIP_CACHE 311 #define POWER9_PME_PM_INST_FROM_ON_CHIP_CACHE 312 #define POWER9_PME_PM_INST_FROM_RL2L3_MOD 313 #define POWER9_PME_PM_INST_FROM_RL2L3_SHR 314 #define POWER9_PME_PM_INST_FROM_RL4 315 #define POWER9_PME_PM_INST_FROM_RMEM 316 #define POWER9_PME_PM_INST_GRP_PUMP_CPRED 317 #define POWER9_PME_PM_INST_GRP_PUMP_MPRED_RTY 318 #define POWER9_PME_PM_INST_GRP_PUMP_MPRED 319 #define POWER9_PME_PM_INST_IMC_MATCH_CMPL 320 #define POWER9_PME_PM_INST_PUMP_CPRED 321 #define POWER9_PME_PM_INST_PUMP_MPRED 322 #define POWER9_PME_PM_INST_SYS_PUMP_CPRED 323 #define POWER9_PME_PM_INST_SYS_PUMP_MPRED_RTY 324 #define POWER9_PME_PM_INST_SYS_PUMP_MPRED 325 #define POWER9_PME_PM_IOPS_CMPL 326 #define POWER9_PME_PM_IPTEG_FROM_DL2L3_MOD 327 #define POWER9_PME_PM_IPTEG_FROM_DL2L3_SHR 328 #define POWER9_PME_PM_IPTEG_FROM_DL4 329 #define POWER9_PME_PM_IPTEG_FROM_DMEM 330 #define POWER9_PME_PM_IPTEG_FROM_L21_MOD 331 #define POWER9_PME_PM_IPTEG_FROM_L21_SHR 332 #define POWER9_PME_PM_IPTEG_FROM_L2_MEPF 333 #define POWER9_PME_PM_IPTEG_FROM_L2MISS 334 #define POWER9_PME_PM_IPTEG_FROM_L2_NO_CONFLICT 335 #define POWER9_PME_PM_IPTEG_FROM_L2 336 #define POWER9_PME_PM_IPTEG_FROM_L31_ECO_MOD 337 #define POWER9_PME_PM_IPTEG_FROM_L31_ECO_SHR 338 #define POWER9_PME_PM_IPTEG_FROM_L31_MOD 339 #define POWER9_PME_PM_IPTEG_FROM_L31_SHR 340 #define POWER9_PME_PM_IPTEG_FROM_L3_DISP_CONFLICT 341 #define POWER9_PME_PM_IPTEG_FROM_L3_MEPF 342 #define POWER9_PME_PM_IPTEG_FROM_L3MISS 343 #define POWER9_PME_PM_IPTEG_FROM_L3_NO_CONFLICT 344 #define POWER9_PME_PM_IPTEG_FROM_L3 345 #define POWER9_PME_PM_IPTEG_FROM_LL4 346 #define POWER9_PME_PM_IPTEG_FROM_LMEM 347 #define POWER9_PME_PM_IPTEG_FROM_MEMORY 348 #define POWER9_PME_PM_IPTEG_FROM_OFF_CHIP_CACHE 349 #define POWER9_PME_PM_IPTEG_FROM_ON_CHIP_CACHE 350 #define POWER9_PME_PM_IPTEG_FROM_RL2L3_MOD 351 #define POWER9_PME_PM_IPTEG_FROM_RL2L3_SHR 352 #define POWER9_PME_PM_IPTEG_FROM_RL4 353 #define POWER9_PME_PM_IPTEG_FROM_RMEM 354 #define POWER9_PME_PM_ISIDE_DISP_FAIL_ADDR 355 #define POWER9_PME_PM_ISIDE_DISP_FAIL_OTHER 356 #define POWER9_PME_PM_ISIDE_DISP 357 #define POWER9_PME_PM_ISIDE_L2MEMACC 358 #define POWER9_PME_PM_ISIDE_MRU_TOUCH 359 #define POWER9_PME_PM_ISLB_MISS 360 #define POWER9_PME_PM_ISLB_MISS_ALT 361 #define POWER9_PME_PM_ISQ_0_8_ENTRIES 362 #define POWER9_PME_PM_ISQ_36_44_ENTRIES 363 #define POWER9_PME_PM_ISU0_ISS_HOLD_ALL 364 #define POWER9_PME_PM_ISU1_ISS_HOLD_ALL 365 #define POWER9_PME_PM_ISU2_ISS_HOLD_ALL 366 #define POWER9_PME_PM_ISU3_ISS_HOLD_ALL 367 #define POWER9_PME_PM_ISYNC 368 #define POWER9_PME_PM_ITLB_MISS 369 #define POWER9_PME_PM_L1_DCACHE_RELOADED_ALL 370 #define POWER9_PME_PM_L1_DCACHE_RELOAD_VALID 371 #define POWER9_PME_PM_L1_DEMAND_WRITE 372 #define POWER9_PME_PM_L1_ICACHE_MISS 373 #define POWER9_PME_PM_L1_ICACHE_RELOADED_ALL 374 #define POWER9_PME_PM_L1_ICACHE_RELOADED_PREF 375 #define POWER9_PME_PM_L1PF_L2MEMACC 376 #define POWER9_PME_PM_L1_PREF 377 #define POWER9_PME_PM_L1_SW_PREF 378 #define POWER9_PME_PM_L2_CASTOUT_MOD 379 #define POWER9_PME_PM_L2_CASTOUT_SHR 380 #define POWER9_PME_PM_L2_CHIP_PUMP 381 #define POWER9_PME_PM_L2_DC_INV 382 #define POWER9_PME_PM_L2_DISP_ALL_L2MISS 383 #define POWER9_PME_PM_L2_GROUP_PUMP 384 #define POWER9_PME_PM_L2_GRP_GUESS_CORRECT 385 #define POWER9_PME_PM_L2_GRP_GUESS_WRONG 386 #define POWER9_PME_PM_L2_IC_INV 387 #define POWER9_PME_PM_L2_INST_MISS 388 #define POWER9_PME_PM_L2_INST_MISS_ALT 389 #define POWER9_PME_PM_L2_INST 390 #define POWER9_PME_PM_L2_INST_ALT 391 #define POWER9_PME_PM_L2_LD_DISP 392 #define POWER9_PME_PM_L2_LD_DISP_ALT 393 #define POWER9_PME_PM_L2_LD_HIT 394 #define POWER9_PME_PM_L2_LD_HIT_ALT 395 #define POWER9_PME_PM_L2_LD_MISS_128B 396 #define POWER9_PME_PM_L2_LD_MISS_64B 397 #define POWER9_PME_PM_L2_LD_MISS 398 #define POWER9_PME_PM_L2_LD 399 #define POWER9_PME_PM_L2_LOC_GUESS_CORRECT 400 #define POWER9_PME_PM_L2_LOC_GUESS_WRONG 401 #define POWER9_PME_PM_L2_RCLD_DISP_FAIL_ADDR 402 #define POWER9_PME_PM_L2_RCLD_DISP_FAIL_OTHER 403 #define POWER9_PME_PM_L2_RCLD_DISP 404 #define POWER9_PME_PM_L2_RCST_DISP_FAIL_ADDR 405 #define POWER9_PME_PM_L2_RCST_DISP_FAIL_OTHER 406 #define POWER9_PME_PM_L2_RCST_DISP 407 #define POWER9_PME_PM_L2_RC_ST_DONE 408 #define POWER9_PME_PM_L2_RTY_LD 409 #define POWER9_PME_PM_L2_RTY_LD_ALT 410 #define POWER9_PME_PM_L2_RTY_ST 411 #define POWER9_PME_PM_L2_RTY_ST_ALT 412 #define POWER9_PME_PM_L2_SN_M_RD_DONE 413 #define POWER9_PME_PM_L2_SN_M_WR_DONE 414 #define POWER9_PME_PM_L2_SN_M_WR_DONE_ALT 415 #define POWER9_PME_PM_L2_SN_SX_I_DONE 416 #define POWER9_PME_PM_L2_ST_DISP 417 #define POWER9_PME_PM_L2_ST_DISP_ALT 418 #define POWER9_PME_PM_L2_ST_HIT 419 #define POWER9_PME_PM_L2_ST_HIT_ALT 420 #define POWER9_PME_PM_L2_ST_MISS_128B 421 #define POWER9_PME_PM_L2_ST_MISS_64B 422 #define POWER9_PME_PM_L2_ST_MISS 423 #define POWER9_PME_PM_L2_ST 424 #define POWER9_PME_PM_L2_SYS_GUESS_CORRECT 425 #define POWER9_PME_PM_L2_SYS_GUESS_WRONG 426 #define POWER9_PME_PM_L2_SYS_PUMP 427 #define POWER9_PME_PM_L3_CI_HIT 428 #define POWER9_PME_PM_L3_CI_MISS 429 #define POWER9_PME_PM_L3_CINJ 430 #define POWER9_PME_PM_L3_CI_USAGE 431 #define POWER9_PME_PM_L3_CO0_BUSY 432 #define POWER9_PME_PM_L3_CO0_BUSY_ALT 433 #define POWER9_PME_PM_L3_CO_L31 434 #define POWER9_PME_PM_L3_CO_LCO 435 #define POWER9_PME_PM_L3_CO_MEM 436 #define POWER9_PME_PM_L3_CO_MEPF 437 #define POWER9_PME_PM_L3_CO_MEPF_ALT 438 #define POWER9_PME_PM_L3_CO 439 #define POWER9_PME_PM_L3_GRP_GUESS_CORRECT 440 #define POWER9_PME_PM_L3_GRP_GUESS_WRONG_HIGH 441 #define POWER9_PME_PM_L3_GRP_GUESS_WRONG_LOW 442 #define POWER9_PME_PM_L3_HIT 443 #define POWER9_PME_PM_L3_L2_CO_HIT 444 #define POWER9_PME_PM_L3_L2_CO_MISS 445 #define POWER9_PME_PM_L3_LAT_CI_HIT 446 #define POWER9_PME_PM_L3_LAT_CI_MISS 447 #define POWER9_PME_PM_L3_LD_HIT 448 #define POWER9_PME_PM_L3_LD_MISS 449 #define POWER9_PME_PM_L3_LD_PREF 450 #define POWER9_PME_PM_L3_LOC_GUESS_CORRECT 451 #define POWER9_PME_PM_L3_LOC_GUESS_WRONG 452 #define POWER9_PME_PM_L3_MISS 453 #define POWER9_PME_PM_L3_P0_CO_L31 454 #define POWER9_PME_PM_L3_P0_CO_MEM 455 #define POWER9_PME_PM_L3_P0_CO_RTY 456 #define POWER9_PME_PM_L3_P0_CO_RTY_ALT 457 #define POWER9_PME_PM_L3_P0_GRP_PUMP 458 #define POWER9_PME_PM_L3_P0_LCO_DATA 459 #define POWER9_PME_PM_L3_P0_LCO_NO_DATA 460 #define POWER9_PME_PM_L3_P0_LCO_RTY 461 #define POWER9_PME_PM_L3_P0_NODE_PUMP 462 #define POWER9_PME_PM_L3_P0_PF_RTY 463 #define POWER9_PME_PM_L3_P0_PF_RTY_ALT 464 #define POWER9_PME_PM_L3_P0_SYS_PUMP 465 #define POWER9_PME_PM_L3_P1_CO_L31 466 #define POWER9_PME_PM_L3_P1_CO_MEM 467 #define POWER9_PME_PM_L3_P1_CO_RTY 468 #define POWER9_PME_PM_L3_P1_CO_RTY_ALT 469 #define POWER9_PME_PM_L3_P1_GRP_PUMP 470 #define POWER9_PME_PM_L3_P1_LCO_DATA 471 #define POWER9_PME_PM_L3_P1_LCO_NO_DATA 472 #define POWER9_PME_PM_L3_P1_LCO_RTY 473 #define POWER9_PME_PM_L3_P1_NODE_PUMP 474 #define POWER9_PME_PM_L3_P1_PF_RTY 475 #define POWER9_PME_PM_L3_P1_PF_RTY_ALT 476 #define POWER9_PME_PM_L3_P1_SYS_PUMP 477 #define POWER9_PME_PM_L3_P2_LCO_RTY 478 #define POWER9_PME_PM_L3_P3_LCO_RTY 479 #define POWER9_PME_PM_L3_PF0_BUSY 480 #define POWER9_PME_PM_L3_PF0_BUSY_ALT 481 #define POWER9_PME_PM_L3_PF_HIT_L3 482 #define POWER9_PME_PM_L3_PF_MISS_L3 483 #define POWER9_PME_PM_L3_PF_OFF_CHIP_CACHE 484 #define POWER9_PME_PM_L3_PF_OFF_CHIP_MEM 485 #define POWER9_PME_PM_L3_PF_ON_CHIP_CACHE 486 #define POWER9_PME_PM_L3_PF_ON_CHIP_MEM 487 #define POWER9_PME_PM_L3_PF_USAGE 488 #define POWER9_PME_PM_L3_RD0_BUSY 489 #define POWER9_PME_PM_L3_RD0_BUSY_ALT 490 #define POWER9_PME_PM_L3_RD_USAGE 491 #define POWER9_PME_PM_L3_SN0_BUSY 492 #define POWER9_PME_PM_L3_SN0_BUSY_ALT 493 #define POWER9_PME_PM_L3_SN_USAGE 494 #define POWER9_PME_PM_L3_SW_PREF 495 #define POWER9_PME_PM_L3_SYS_GUESS_CORRECT 496 #define POWER9_PME_PM_L3_SYS_GUESS_WRONG 497 #define POWER9_PME_PM_L3_TRANS_PF 498 #define POWER9_PME_PM_L3_WI0_BUSY 499 #define POWER9_PME_PM_L3_WI0_BUSY_ALT 500 #define POWER9_PME_PM_L3_WI_USAGE 501 #define POWER9_PME_PM_LARX_FIN 502 #define POWER9_PME_PM_LD_CMPL 503 #define POWER9_PME_PM_LD_L3MISS_PEND_CYC 504 #define POWER9_PME_PM_LD_MISS_L1_FIN 505 #define POWER9_PME_PM_LD_MISS_L1 506 #define POWER9_PME_PM_LD_REF_L1 507 #define POWER9_PME_PM_LINK_STACK_CORRECT 508 #define POWER9_PME_PM_LINK_STACK_INVALID_PTR 509 #define POWER9_PME_PM_LINK_STACK_WRONG_ADD_PRED 510 #define POWER9_PME_PM_LMQ_EMPTY_CYC 511 #define POWER9_PME_PM_LMQ_MERGE 512 #define POWER9_PME_PM_LRQ_REJECT 513 #define POWER9_PME_PM_LS0_DC_COLLISIONS 514 #define POWER9_PME_PM_LS0_ERAT_MISS_PREF 515 #define POWER9_PME_PM_LS0_LAUNCH_HELD_PREF 516 #define POWER9_PME_PM_LS0_PTE_TABLEWALK_CYC 517 #define POWER9_PME_PM_LS0_TM_DISALLOW 518 #define POWER9_PME_PM_LS0_UNALIGNED_LD 519 #define POWER9_PME_PM_LS0_UNALIGNED_ST 520 #define POWER9_PME_PM_LS1_DC_COLLISIONS 521 #define POWER9_PME_PM_LS1_ERAT_MISS_PREF 522 #define POWER9_PME_PM_LS1_LAUNCH_HELD_PREF 523 #define POWER9_PME_PM_LS1_PTE_TABLEWALK_CYC 524 #define POWER9_PME_PM_LS1_TM_DISALLOW 525 #define POWER9_PME_PM_LS1_UNALIGNED_LD 526 #define POWER9_PME_PM_LS1_UNALIGNED_ST 527 #define POWER9_PME_PM_LS2_DC_COLLISIONS 528 #define POWER9_PME_PM_LS2_ERAT_MISS_PREF 529 #define POWER9_PME_PM_LS2_TM_DISALLOW 530 #define POWER9_PME_PM_LS2_UNALIGNED_LD 531 #define POWER9_PME_PM_LS2_UNALIGNED_ST 532 #define POWER9_PME_PM_LS3_DC_COLLISIONS 533 #define POWER9_PME_PM_LS3_ERAT_MISS_PREF 534 #define POWER9_PME_PM_LS3_TM_DISALLOW 535 #define POWER9_PME_PM_LS3_UNALIGNED_LD 536 #define POWER9_PME_PM_LS3_UNALIGNED_ST 537 #define POWER9_PME_PM_LSU0_1_LRQF_FULL_CYC 538 #define POWER9_PME_PM_LSU0_ERAT_HIT 539 #define POWER9_PME_PM_LSU0_FALSE_LHS 540 #define POWER9_PME_PM_LSU0_L1_CAM_CANCEL 541 #define POWER9_PME_PM_LSU0_LDMX_FIN 542 #define POWER9_PME_PM_LSU0_LMQ_S0_VALID 543 #define POWER9_PME_PM_LSU0_LRQ_S0_VALID_CYC 544 #define POWER9_PME_PM_LSU0_SET_MPRED 545 #define POWER9_PME_PM_LSU0_SRQ_S0_VALID_CYC 546 #define POWER9_PME_PM_LSU0_STORE_REJECT 547 #define POWER9_PME_PM_LSU0_TM_L1_HIT 548 #define POWER9_PME_PM_LSU0_TM_L1_MISS 549 #define POWER9_PME_PM_LSU1_ERAT_HIT 550 #define POWER9_PME_PM_LSU1_FALSE_LHS 551 #define POWER9_PME_PM_LSU1_L1_CAM_CANCEL 552 #define POWER9_PME_PM_LSU1_LDMX_FIN 553 #define POWER9_PME_PM_LSU1_SET_MPRED 554 #define POWER9_PME_PM_LSU1_STORE_REJECT 555 #define POWER9_PME_PM_LSU1_TM_L1_HIT 556 #define POWER9_PME_PM_LSU1_TM_L1_MISS 557 #define POWER9_PME_PM_LSU2_3_LRQF_FULL_CYC 558 #define POWER9_PME_PM_LSU2_ERAT_HIT 559 #define POWER9_PME_PM_LSU2_FALSE_LHS 560 #define POWER9_PME_PM_LSU2_L1_CAM_CANCEL 561 #define POWER9_PME_PM_LSU2_LDMX_FIN 562 #define POWER9_PME_PM_LSU2_SET_MPRED 563 #define POWER9_PME_PM_LSU2_STORE_REJECT 564 #define POWER9_PME_PM_LSU2_TM_L1_HIT 565 #define POWER9_PME_PM_LSU2_TM_L1_MISS 566 #define POWER9_PME_PM_LSU3_ERAT_HIT 567 #define POWER9_PME_PM_LSU3_FALSE_LHS 568 #define POWER9_PME_PM_LSU3_L1_CAM_CANCEL 569 #define POWER9_PME_PM_LSU3_LDMX_FIN 570 #define POWER9_PME_PM_LSU3_SET_MPRED 571 #define POWER9_PME_PM_LSU3_STORE_REJECT 572 #define POWER9_PME_PM_LSU3_TM_L1_HIT 573 #define POWER9_PME_PM_LSU3_TM_L1_MISS 574 #define POWER9_PME_PM_LSU_DERAT_MISS 575 #define POWER9_PME_PM_LSU_FIN 576 #define POWER9_PME_PM_LSU_FLUSH_ATOMIC 577 #define POWER9_PME_PM_LSU_FLUSH_CI 578 #define POWER9_PME_PM_LSU_FLUSH_EMSH 579 #define POWER9_PME_PM_LSU_FLUSH_LARX_STCX 580 #define POWER9_PME_PM_LSU_FLUSH_LHL_SHL 581 #define POWER9_PME_PM_LSU_FLUSH_LHS 582 #define POWER9_PME_PM_LSU_FLUSH_NEXT 583 #define POWER9_PME_PM_LSU_FLUSH_OTHER 584 #define POWER9_PME_PM_LSU_FLUSH_RELAUNCH_MISS 585 #define POWER9_PME_PM_LSU_FLUSH_SAO 586 #define POWER9_PME_PM_LSU_FLUSH_UE 587 #define POWER9_PME_PM_LSU_FLUSH_WRK_ARND 588 #define POWER9_PME_PM_LSU_LMQ_FULL_CYC 589 #define POWER9_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC 590 #define POWER9_PME_PM_LSU_NCST 591 #define POWER9_PME_PM_LSU_REJECT_ERAT_MISS 592 #define POWER9_PME_PM_LSU_REJECT_LHS 593 #define POWER9_PME_PM_LSU_REJECT_LMQ_FULL 594 #define POWER9_PME_PM_LSU_SRQ_FULL_CYC 595 #define POWER9_PME_PM_LSU_STCX_FAIL 596 #define POWER9_PME_PM_LSU_STCX 597 #define POWER9_PME_PM_LWSYNC 598 #define POWER9_PME_PM_MATH_FLOP_CMPL 599 #define POWER9_PME_PM_MEM_CO 600 #define POWER9_PME_PM_MEM_LOC_THRESH_IFU 601 #define POWER9_PME_PM_MEM_LOC_THRESH_LSU_HIGH 602 #define POWER9_PME_PM_MEM_LOC_THRESH_LSU_MED 603 #define POWER9_PME_PM_MEM_PREF 604 #define POWER9_PME_PM_MEM_READ 605 #define POWER9_PME_PM_MEM_RWITM 606 #define POWER9_PME_PM_MRK_BACK_BR_CMPL 607 #define POWER9_PME_PM_MRK_BR_2PATH 608 #define POWER9_PME_PM_MRK_BR_CMPL 609 #define POWER9_PME_PM_MRK_BR_MPRED_CMPL 610 #define POWER9_PME_PM_MRK_BR_TAKEN_CMPL 611 #define POWER9_PME_PM_MRK_BRU_FIN 612 #define POWER9_PME_PM_MRK_DATA_FROM_DL2L3_MOD_CYC 613 #define POWER9_PME_PM_MRK_DATA_FROM_DL2L3_MOD 614 #define POWER9_PME_PM_MRK_DATA_FROM_DL2L3_SHR_CYC 615 #define POWER9_PME_PM_MRK_DATA_FROM_DL2L3_SHR 616 #define POWER9_PME_PM_MRK_DATA_FROM_DL4_CYC 617 #define POWER9_PME_PM_MRK_DATA_FROM_DL4 618 #define POWER9_PME_PM_MRK_DATA_FROM_DMEM_CYC 619 #define POWER9_PME_PM_MRK_DATA_FROM_DMEM 620 #define POWER9_PME_PM_MRK_DATA_FROM_L21_MOD_CYC 621 #define POWER9_PME_PM_MRK_DATA_FROM_L21_MOD 622 #define POWER9_PME_PM_MRK_DATA_FROM_L21_SHR_CYC 623 #define POWER9_PME_PM_MRK_DATA_FROM_L21_SHR 624 #define POWER9_PME_PM_MRK_DATA_FROM_L2_CYC 625 #define POWER9_PME_PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST_CYC 626 #define POWER9_PME_PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST 627 #define POWER9_PME_PM_MRK_DATA_FROM_L2_DISP_CONFLICT_OTHER_CYC 628 #define POWER9_PME_PM_MRK_DATA_FROM_L2_DISP_CONFLICT_OTHER 629 #define POWER9_PME_PM_MRK_DATA_FROM_L2_MEPF_CYC 630 #define POWER9_PME_PM_MRK_DATA_FROM_L2_MEPF 631 #define POWER9_PME_PM_MRK_DATA_FROM_L2MISS_CYC 632 #define POWER9_PME_PM_MRK_DATA_FROM_L2MISS 633 #define POWER9_PME_PM_MRK_DATA_FROM_L2_NO_CONFLICT_CYC 634 #define POWER9_PME_PM_MRK_DATA_FROM_L2_NO_CONFLICT 635 #define POWER9_PME_PM_MRK_DATA_FROM_L2 636 #define POWER9_PME_PM_MRK_DATA_FROM_L31_ECO_MOD_CYC 637 #define POWER9_PME_PM_MRK_DATA_FROM_L31_ECO_MOD 638 #define POWER9_PME_PM_MRK_DATA_FROM_L31_ECO_SHR_CYC 639 #define POWER9_PME_PM_MRK_DATA_FROM_L31_ECO_SHR 640 #define POWER9_PME_PM_MRK_DATA_FROM_L31_MOD_CYC 641 #define POWER9_PME_PM_MRK_DATA_FROM_L31_MOD 642 #define POWER9_PME_PM_MRK_DATA_FROM_L31_SHR_CYC 643 #define POWER9_PME_PM_MRK_DATA_FROM_L31_SHR 644 #define POWER9_PME_PM_MRK_DATA_FROM_L3_CYC 645 #define POWER9_PME_PM_MRK_DATA_FROM_L3_DISP_CONFLICT_CYC 646 #define POWER9_PME_PM_MRK_DATA_FROM_L3_DISP_CONFLICT 647 #define POWER9_PME_PM_MRK_DATA_FROM_L3_MEPF_CYC 648 #define POWER9_PME_PM_MRK_DATA_FROM_L3_MEPF 649 #define POWER9_PME_PM_MRK_DATA_FROM_L3MISS_CYC 650 #define POWER9_PME_PM_MRK_DATA_FROM_L3MISS 651 #define POWER9_PME_PM_MRK_DATA_FROM_L3_NO_CONFLICT_CYC 652 #define POWER9_PME_PM_MRK_DATA_FROM_L3_NO_CONFLICT 653 #define POWER9_PME_PM_MRK_DATA_FROM_L3 654 #define POWER9_PME_PM_MRK_DATA_FROM_LL4_CYC 655 #define POWER9_PME_PM_MRK_DATA_FROM_LL4 656 #define POWER9_PME_PM_MRK_DATA_FROM_LMEM_CYC 657 #define POWER9_PME_PM_MRK_DATA_FROM_LMEM 658 #define POWER9_PME_PM_MRK_DATA_FROM_MEMORY_CYC 659 #define POWER9_PME_PM_MRK_DATA_FROM_MEMORY 660 #define POWER9_PME_PM_MRK_DATA_FROM_OFF_CHIP_CACHE_CYC 661 #define POWER9_PME_PM_MRK_DATA_FROM_OFF_CHIP_CACHE 662 #define POWER9_PME_PM_MRK_DATA_FROM_ON_CHIP_CACHE_CYC 663 #define POWER9_PME_PM_MRK_DATA_FROM_ON_CHIP_CACHE 664 #define POWER9_PME_PM_MRK_DATA_FROM_RL2L3_MOD_CYC 665 #define POWER9_PME_PM_MRK_DATA_FROM_RL2L3_MOD 666 #define POWER9_PME_PM_MRK_DATA_FROM_RL2L3_SHR_CYC 667 #define POWER9_PME_PM_MRK_DATA_FROM_RL2L3_SHR 668 #define POWER9_PME_PM_MRK_DATA_FROM_RL4_CYC 669 #define POWER9_PME_PM_MRK_DATA_FROM_RL4 670 #define POWER9_PME_PM_MRK_DATA_FROM_RMEM_CYC 671 #define POWER9_PME_PM_MRK_DATA_FROM_RMEM 672 #define POWER9_PME_PM_MRK_DCACHE_RELOAD_INTV 673 #define POWER9_PME_PM_MRK_DERAT_MISS_16G 674 #define POWER9_PME_PM_MRK_DERAT_MISS_16M 675 #define POWER9_PME_PM_MRK_DERAT_MISS_1G 676 #define POWER9_PME_PM_MRK_DERAT_MISS_2M 677 #define POWER9_PME_PM_MRK_DERAT_MISS_4K 678 #define POWER9_PME_PM_MRK_DERAT_MISS_64K 679 #define POWER9_PME_PM_MRK_DERAT_MISS 680 #define POWER9_PME_PM_MRK_DFU_FIN 681 #define POWER9_PME_PM_MRK_DPTEG_FROM_DL2L3_MOD 682 #define POWER9_PME_PM_MRK_DPTEG_FROM_DL2L3_SHR 683 #define POWER9_PME_PM_MRK_DPTEG_FROM_DL4 684 #define POWER9_PME_PM_MRK_DPTEG_FROM_DMEM 685 #define POWER9_PME_PM_MRK_DPTEG_FROM_L21_MOD 686 #define POWER9_PME_PM_MRK_DPTEG_FROM_L21_SHR 687 #define POWER9_PME_PM_MRK_DPTEG_FROM_L2_MEPF 688 #define POWER9_PME_PM_MRK_DPTEG_FROM_L2MISS 689 #define POWER9_PME_PM_MRK_DPTEG_FROM_L2_NO_CONFLICT 690 #define POWER9_PME_PM_MRK_DPTEG_FROM_L2 691 #define POWER9_PME_PM_MRK_DPTEG_FROM_L31_ECO_MOD 692 #define POWER9_PME_PM_MRK_DPTEG_FROM_L31_ECO_SHR 693 #define POWER9_PME_PM_MRK_DPTEG_FROM_L31_MOD 694 #define POWER9_PME_PM_MRK_DPTEG_FROM_L31_SHR 695 #define POWER9_PME_PM_MRK_DPTEG_FROM_L3_DISP_CONFLICT 696 #define POWER9_PME_PM_MRK_DPTEG_FROM_L3_MEPF 697 #define POWER9_PME_PM_MRK_DPTEG_FROM_L3MISS 698 #define POWER9_PME_PM_MRK_DPTEG_FROM_L3_NO_CONFLICT 699 #define POWER9_PME_PM_MRK_DPTEG_FROM_L3 700 #define POWER9_PME_PM_MRK_DPTEG_FROM_LL4 701 #define POWER9_PME_PM_MRK_DPTEG_FROM_LMEM 702 #define POWER9_PME_PM_MRK_DPTEG_FROM_MEMORY 703 #define POWER9_PME_PM_MRK_DPTEG_FROM_OFF_CHIP_CACHE 704 #define POWER9_PME_PM_MRK_DPTEG_FROM_ON_CHIP_CACHE 705 #define POWER9_PME_PM_MRK_DPTEG_FROM_RL2L3_MOD 706 #define POWER9_PME_PM_MRK_DPTEG_FROM_RL2L3_SHR 707 #define POWER9_PME_PM_MRK_DPTEG_FROM_RL4 708 #define POWER9_PME_PM_MRK_DPTEG_FROM_RMEM 709 #define POWER9_PME_PM_MRK_DTLB_MISS_16G 710 #define POWER9_PME_PM_MRK_DTLB_MISS_16M 711 #define POWER9_PME_PM_MRK_DTLB_MISS_1G 712 #define POWER9_PME_PM_MRK_DTLB_MISS_4K 713 #define POWER9_PME_PM_MRK_DTLB_MISS_64K 714 #define POWER9_PME_PM_MRK_DTLB_MISS 715 #define POWER9_PME_PM_MRK_FAB_RSP_BKILL_CYC 716 #define POWER9_PME_PM_MRK_FAB_RSP_BKILL 717 #define POWER9_PME_PM_MRK_FAB_RSP_CLAIM_RTY 718 #define POWER9_PME_PM_MRK_FAB_RSP_DCLAIM_CYC 719 #define POWER9_PME_PM_MRK_FAB_RSP_DCLAIM 720 #define POWER9_PME_PM_MRK_FAB_RSP_RD_RTY 721 #define POWER9_PME_PM_MRK_FAB_RSP_RD_T_INTV 722 #define POWER9_PME_PM_MRK_FAB_RSP_RWITM_CYC 723 #define POWER9_PME_PM_MRK_FAB_RSP_RWITM_RTY 724 #define POWER9_PME_PM_MRK_FXU_FIN 725 #define POWER9_PME_PM_MRK_IC_MISS 726 #define POWER9_PME_PM_MRK_INST_CMPL 727 #define POWER9_PME_PM_MRK_INST_DECODED 728 #define POWER9_PME_PM_MRK_INST_DISP 729 #define POWER9_PME_PM_MRK_INST_FIN 730 #define POWER9_PME_PM_MRK_INST_FROM_L3MISS 731 #define POWER9_PME_PM_MRK_INST_ISSUED 732 #define POWER9_PME_PM_MRK_INST_TIMEO 733 #define POWER9_PME_PM_MRK_INST 734 #define POWER9_PME_PM_MRK_L1_ICACHE_MISS 735 #define POWER9_PME_PM_MRK_L1_RELOAD_VALID 736 #define POWER9_PME_PM_MRK_L2_RC_DISP 737 #define POWER9_PME_PM_MRK_L2_RC_DONE 738 #define POWER9_PME_PM_MRK_L2_TM_REQ_ABORT 739 #define POWER9_PME_PM_MRK_L2_TM_ST_ABORT_SISTER 740 #define POWER9_PME_PM_MRK_LARX_FIN 741 #define POWER9_PME_PM_MRK_LD_MISS_EXPOSED_CYC 742 #define POWER9_PME_PM_MRK_LD_MISS_L1_CYC 743 #define POWER9_PME_PM_MRK_LD_MISS_L1 744 #define POWER9_PME_PM_MRK_LSU_DERAT_MISS 745 #define POWER9_PME_PM_MRK_LSU_FIN 746 #define POWER9_PME_PM_MRK_LSU_FLUSH_ATOMIC 747 #define POWER9_PME_PM_MRK_LSU_FLUSH_EMSH 748 #define POWER9_PME_PM_MRK_LSU_FLUSH_LARX_STCX 749 #define POWER9_PME_PM_MRK_LSU_FLUSH_LHL_SHL 750 #define POWER9_PME_PM_MRK_LSU_FLUSH_LHS 751 #define POWER9_PME_PM_MRK_LSU_FLUSH_RELAUNCH_MISS 752 #define POWER9_PME_PM_MRK_LSU_FLUSH_SAO 753 #define POWER9_PME_PM_MRK_LSU_FLUSH_UE 754 #define POWER9_PME_PM_MRK_NTC_CYC 755 #define POWER9_PME_PM_MRK_NTF_FIN 756 #define POWER9_PME_PM_MRK_PROBE_NOP_CMPL 757 #define POWER9_PME_PM_MRK_RUN_CYC 758 #define POWER9_PME_PM_MRK_STALL_CMPLU_CYC 759 #define POWER9_PME_PM_MRK_ST_CMPL_INT 760 #define POWER9_PME_PM_MRK_ST_CMPL 761 #define POWER9_PME_PM_MRK_STCX_FAIL 762 #define POWER9_PME_PM_MRK_STCX_FIN 763 #define POWER9_PME_PM_MRK_ST_DONE_L2 764 #define POWER9_PME_PM_MRK_ST_DRAIN_TO_L2DISP_CYC 765 #define POWER9_PME_PM_MRK_ST_FWD 766 #define POWER9_PME_PM_MRK_ST_L2DISP_TO_CMPL_CYC 767 #define POWER9_PME_PM_MRK_ST_NEST 768 #define POWER9_PME_PM_MRK_TEND_FAIL 769 #define POWER9_PME_PM_MRK_VSU_FIN 770 #define POWER9_PME_PM_MULT_MRK 771 #define POWER9_PME_PM_NEST_REF_CLK 772 #define POWER9_PME_PM_NON_DATA_STORE 773 #define POWER9_PME_PM_NON_FMA_FLOP_CMPL 774 #define POWER9_PME_PM_NON_MATH_FLOP_CMPL 775 #define POWER9_PME_PM_NON_TM_RST_SC 776 #define POWER9_PME_PM_NTC_ALL_FIN 777 #define POWER9_PME_PM_NTC_FIN 778 #define POWER9_PME_PM_NTC_ISSUE_HELD_ARB 779 #define POWER9_PME_PM_NTC_ISSUE_HELD_DARQ_FULL 780 #define POWER9_PME_PM_NTC_ISSUE_HELD_OTHER 781 #define POWER9_PME_PM_PARTIAL_ST_FIN 782 #define POWER9_PME_PM_PMC1_OVERFLOW 783 #define POWER9_PME_PM_PMC1_REWIND 784 #define POWER9_PME_PM_PMC1_SAVED 785 #define POWER9_PME_PM_PMC2_OVERFLOW 786 #define POWER9_PME_PM_PMC2_REWIND 787 #define POWER9_PME_PM_PMC2_SAVED 788 #define POWER9_PME_PM_PMC3_OVERFLOW 789 #define POWER9_PME_PM_PMC3_REWIND 790 #define POWER9_PME_PM_PMC3_SAVED 791 #define POWER9_PME_PM_PMC4_OVERFLOW 792 #define POWER9_PME_PM_PMC4_REWIND 793 #define POWER9_PME_PM_PMC4_SAVED 794 #define POWER9_PME_PM_PMC5_OVERFLOW 795 #define POWER9_PME_PM_PMC6_OVERFLOW 796 #define POWER9_PME_PM_PROBE_NOP_DISP 797 #define POWER9_PME_PM_PTE_PREFETCH 798 #define POWER9_PME_PM_PTESYNC 799 #define POWER9_PME_PM_PUMP_CPRED 800 #define POWER9_PME_PM_PUMP_MPRED 801 #define POWER9_PME_PM_RADIX_PWC_L1_HIT 802 #define POWER9_PME_PM_RADIX_PWC_L1_PDE_FROM_L2 803 #define POWER9_PME_PM_RADIX_PWC_L1_PDE_FROM_L3MISS 804 #define POWER9_PME_PM_RADIX_PWC_L1_PDE_FROM_L3 805 #define POWER9_PME_PM_RADIX_PWC_L2_HIT 806 #define POWER9_PME_PM_RADIX_PWC_L2_PDE_FROM_L2 807 #define POWER9_PME_PM_RADIX_PWC_L2_PDE_FROM_L3 808 #define POWER9_PME_PM_RADIX_PWC_L2_PTE_FROM_L2 809 #define POWER9_PME_PM_RADIX_PWC_L2_PTE_FROM_L3MISS 810 #define POWER9_PME_PM_RADIX_PWC_L2_PTE_FROM_L3 811 #define POWER9_PME_PM_RADIX_PWC_L3_HIT 812 #define POWER9_PME_PM_RADIX_PWC_L3_PDE_FROM_L2 813 #define POWER9_PME_PM_RADIX_PWC_L3_PDE_FROM_L3 814 #define POWER9_PME_PM_RADIX_PWC_L3_PTE_FROM_L2 815 #define POWER9_PME_PM_RADIX_PWC_L3_PTE_FROM_L3MISS 816 #define POWER9_PME_PM_RADIX_PWC_L3_PTE_FROM_L3 817 #define POWER9_PME_PM_RADIX_PWC_L4_PTE_FROM_L2 818 #define POWER9_PME_PM_RADIX_PWC_L4_PTE_FROM_L3MISS 819 #define POWER9_PME_PM_RADIX_PWC_L4_PTE_FROM_L3 820 #define POWER9_PME_PM_RADIX_PWC_MISS 821 #define POWER9_PME_PM_RC0_BUSY 822 #define POWER9_PME_PM_RC0_BUSY_ALT 823 #define POWER9_PME_PM_RC_USAGE 824 #define POWER9_PME_PM_RD_CLEARING_SC 825 #define POWER9_PME_PM_RD_FORMING_SC 826 #define POWER9_PME_PM_RD_HIT_PF 827 #define POWER9_PME_PM_RUN_CYC_SMT2_MODE 828 #define POWER9_PME_PM_RUN_CYC_SMT4_MODE 829 #define POWER9_PME_PM_RUN_CYC_ST_MODE 830 #define POWER9_PME_PM_RUN_CYC 831 #define POWER9_PME_PM_RUN_INST_CMPL 832 #define POWER9_PME_PM_RUN_PURR 833 #define POWER9_PME_PM_RUN_SPURR 834 #define POWER9_PME_PM_S2Q_FULL 835 #define POWER9_PME_PM_SCALAR_FLOP_CMPL 836 #define POWER9_PME_PM_SHL_CREATED 837 #define POWER9_PME_PM_SHL_ST_DEP_CREATED 838 #define POWER9_PME_PM_SHL_ST_DISABLE 839 #define POWER9_PME_PM_SLB_TABLEWALK_CYC 840 #define POWER9_PME_PM_SN0_BUSY 841 #define POWER9_PME_PM_SN0_BUSY_ALT 842 #define POWER9_PME_PM_SN_HIT 843 #define POWER9_PME_PM_SN_INVL 844 #define POWER9_PME_PM_SN_MISS 845 #define POWER9_PME_PM_SNOOP_TLBIE 846 #define POWER9_PME_PM_SNP_TM_HIT_M 847 #define POWER9_PME_PM_SNP_TM_HIT_T 848 #define POWER9_PME_PM_SN_USAGE 849 #define POWER9_PME_PM_SP_FLOP_CMPL 850 #define POWER9_PME_PM_SRQ_EMPTY_CYC 851 #define POWER9_PME_PM_SRQ_SYNC_CYC 852 #define POWER9_PME_PM_STALL_END_ICT_EMPTY 853 #define POWER9_PME_PM_ST_CAUSED_FAIL 854 #define POWER9_PME_PM_ST_CMPL 855 #define POWER9_PME_PM_STCX_FAIL 856 #define POWER9_PME_PM_STCX_FIN 857 #define POWER9_PME_PM_STCX_SUCCESS_CMPL 858 #define POWER9_PME_PM_ST_FIN 859 #define POWER9_PME_PM_ST_FWD 860 #define POWER9_PME_PM_ST_MISS_L1 861 #define POWER9_PME_PM_STOP_FETCH_PENDING_CYC 862 #define POWER9_PME_PM_SUSPENDED 863 #define POWER9_PME_PM_SYNC_MRK_BR_LINK 864 #define POWER9_PME_PM_SYNC_MRK_BR_MPRED 865 #define POWER9_PME_PM_SYNC_MRK_FX_DIVIDE 866 #define POWER9_PME_PM_SYNC_MRK_L2HIT 867 #define POWER9_PME_PM_SYNC_MRK_L2MISS 868 #define POWER9_PME_PM_SYNC_MRK_L3MISS 869 #define POWER9_PME_PM_SYNC_MRK_PROBE_NOP 870 #define POWER9_PME_PM_SYS_PUMP_CPRED 871 #define POWER9_PME_PM_SYS_PUMP_MPRED_RTY 872 #define POWER9_PME_PM_SYS_PUMP_MPRED 873 #define POWER9_PME_PM_TABLEWALK_CYC_PREF 874 #define POWER9_PME_PM_TABLEWALK_CYC 875 #define POWER9_PME_PM_TAGE_CORRECT_TAKEN_CMPL 876 #define POWER9_PME_PM_TAGE_CORRECT 877 #define POWER9_PME_PM_TAGE_OVERRIDE_WRONG_SPEC 878 #define POWER9_PME_PM_TAGE_OVERRIDE_WRONG 879 #define POWER9_PME_PM_TAKEN_BR_MPRED_CMPL 880 #define POWER9_PME_PM_TB_BIT_TRANS 881 #define POWER9_PME_PM_TEND_PEND_CYC 882 #define POWER9_PME_PM_THRD_ALL_RUN_CYC 883 #define POWER9_PME_PM_THRD_CONC_RUN_INST 884 #define POWER9_PME_PM_THRD_PRIO_0_1_CYC 885 #define POWER9_PME_PM_THRD_PRIO_2_3_CYC 886 #define POWER9_PME_PM_THRD_PRIO_4_5_CYC 887 #define POWER9_PME_PM_THRD_PRIO_6_7_CYC 888 #define POWER9_PME_PM_THRESH_ACC 889 #define POWER9_PME_PM_THRESH_EXC_1024 890 #define POWER9_PME_PM_THRESH_EXC_128 891 #define POWER9_PME_PM_THRESH_EXC_2048 892 #define POWER9_PME_PM_THRESH_EXC_256 893 #define POWER9_PME_PM_THRESH_EXC_32 894 #define POWER9_PME_PM_THRESH_EXC_4096 895 #define POWER9_PME_PM_THRESH_EXC_512 896 #define POWER9_PME_PM_THRESH_EXC_64 897 #define POWER9_PME_PM_THRESH_MET 898 #define POWER9_PME_PM_THRESH_NOT_MET 899 #define POWER9_PME_PM_TLB_HIT 900 #define POWER9_PME_PM_TLBIE_FIN 901 #define POWER9_PME_PM_TLB_MISS 902 #define POWER9_PME_PM_TM_ABORTS 903 #define POWER9_PME_PM_TMA_REQ_L2 904 #define POWER9_PME_PM_TM_CAM_OVERFLOW 905 #define POWER9_PME_PM_TM_CAP_OVERFLOW 906 #define POWER9_PME_PM_TM_FAIL_CONF_NON_TM 907 #define POWER9_PME_PM_TM_FAIL_CONF_TM 908 #define POWER9_PME_PM_TM_FAIL_FOOTPRINT_OVERFLOW 909 #define POWER9_PME_PM_TM_FAIL_NON_TX_CONFLICT 910 #define POWER9_PME_PM_TM_FAIL_SELF 911 #define POWER9_PME_PM_TM_FAIL_TLBIE 912 #define POWER9_PME_PM_TM_FAIL_TX_CONFLICT 913 #define POWER9_PME_PM_TM_FAV_CAUSED_FAIL 914 #define POWER9_PME_PM_TM_FAV_TBEGIN 915 #define POWER9_PME_PM_TM_LD_CAUSED_FAIL 916 #define POWER9_PME_PM_TM_LD_CONF 917 #define POWER9_PME_PM_TM_NESTED_TBEGIN 918 #define POWER9_PME_PM_TM_NESTED_TEND 919 #define POWER9_PME_PM_TM_NON_FAV_TBEGIN 920 #define POWER9_PME_PM_TM_OUTER_TBEGIN_DISP 921 #define POWER9_PME_PM_TM_OUTER_TBEGIN 922 #define POWER9_PME_PM_TM_OUTER_TEND 923 #define POWER9_PME_PM_TM_PASSED 924 #define POWER9_PME_PM_TM_RST_SC 925 #define POWER9_PME_PM_TM_SC_CO 926 #define POWER9_PME_PM_TM_ST_CAUSED_FAIL 927 #define POWER9_PME_PM_TM_ST_CONF 928 #define POWER9_PME_PM_TM_TABORT_TRECLAIM 929 #define POWER9_PME_PM_TM_TRANS_RUN_CYC 930 #define POWER9_PME_PM_TM_TRANS_RUN_INST 931 #define POWER9_PME_PM_TM_TRESUME 932 #define POWER9_PME_PM_TM_TSUSPEND 933 #define POWER9_PME_PM_TM_TX_PASS_RUN_CYC 934 #define POWER9_PME_PM_TM_TX_PASS_RUN_INST 935 #define POWER9_PME_PM_VECTOR_FLOP_CMPL 936 #define POWER9_PME_PM_VECTOR_LD_CMPL 937 #define POWER9_PME_PM_VECTOR_ST_CMPL 938 #define POWER9_PME_PM_VSU_DP_FSQRT_FDIV 939 #define POWER9_PME_PM_VSU_FIN 940 #define POWER9_PME_PM_VSU_FSQRT_FDIV 941 #define POWER9_PME_PM_VSU_NON_FLOP_CMPL 942 #define POWER9_PME_PM_XLATE_HPT_MODE 943 #define POWER9_PME_PM_XLATE_MISS 944 #define POWER9_PME_PM_XLATE_RADIX_MODE 945 #define POWER9_PME_PM_BR_2PATH_ALT 946 #define POWER9_PME_PM_CYC_ALT 947 #define POWER9_PME_PM_CYC_ALT2 948 #define POWER9_PME_PM_CYC_ALT3 949 #define POWER9_PME_PM_INST_CMPL_ALT 950 #define POWER9_PME_PM_INST_CMPL_ALT2 951 #define POWER9_PME_PM_INST_CMPL_ALT3 952 #define POWER9_PME_PM_INST_DISP_ALT 953 #define POWER9_PME_PM_LD_MISS_L1_ALT 954 #define POWER9_PME_PM_SUSPENDED_ALT 955 #define POWER9_PME_PM_SUSPENDED_ALT2 956 #define POWER9_PME_PM_SUSPENDED_ALT3 957 static const pme_power_entry_t power9_pe[] = { [ POWER9_PME_PM_1FLOP_CMPL ] = { .pme_name = "PM_1FLOP_CMPL", .pme_code = 0x0000045050, .pme_short_desc = "one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation completed", .pme_long_desc = "one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation completed", }, [ POWER9_PME_PM_1PLUS_PPC_CMPL ] = { .pme_name = "PM_1PLUS_PPC_CMPL", .pme_code = 0x00000100F2, .pme_short_desc = "1 or more ppc insts finished", .pme_long_desc = "1 or more ppc insts finished", }, [ POWER9_PME_PM_1PLUS_PPC_DISP ] = { .pme_name = "PM_1PLUS_PPC_DISP", .pme_code = 0x00000400F2, .pme_short_desc = "Cycles at least one Instr Dispatched", .pme_long_desc = "Cycles at least one Instr Dispatched", }, [ POWER9_PME_PM_2FLOP_CMPL ] = { .pme_name = "PM_2FLOP_CMPL", .pme_code = 0x000004D052, .pme_short_desc = "DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg ", .pme_long_desc = "DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg ", }, [ POWER9_PME_PM_4FLOP_CMPL ] = { .pme_name = "PM_4FLOP_CMPL", .pme_code = 0x0000045052, .pme_short_desc = "4 FLOP instruction completed", .pme_long_desc = "4 FLOP instruction completed", }, [ POWER9_PME_PM_8FLOP_CMPL ] = { .pme_name = "PM_8FLOP_CMPL", .pme_code = 0x000004D054, .pme_short_desc = "8 FLOP instruction completed", .pme_long_desc = "8 FLOP instruction completed", }, [ POWER9_PME_PM_ANY_THRD_RUN_CYC ] = { .pme_name = "PM_ANY_THRD_RUN_CYC", .pme_code = 0x00000100FA, .pme_short_desc = "Cycles in which at least one thread has the run latch set", .pme_long_desc = "Cycles in which at least one thread has the run latch set", }, [ POWER9_PME_PM_BACK_BR_CMPL ] = { .pme_name = "PM_BACK_BR_CMPL", .pme_code = 0x000002505E, .pme_short_desc = "Branch instruction completed with a target address less than current instruction address", .pme_long_desc = "Branch instruction completed with a target address less than current instruction address", }, [ POWER9_PME_PM_BANK_CONFLICT ] = { .pme_name = "PM_BANK_CONFLICT", .pme_code = 0x0000004880, .pme_short_desc = "Read blocked due to interleave conflict.", .pme_long_desc = "Read blocked due to interleave conflict. The ifar logic will detect an interleave conflict and kill the data that was read that cycle.", }, [ POWER9_PME_PM_BFU_BUSY ] = { .pme_name = "PM_BFU_BUSY", .pme_code = 0x000003005C, .pme_short_desc = "Cycles in which all 4 Binary Floating Point units are busy.", .pme_long_desc = "Cycles in which all 4 Binary Floating Point units are busy. The BFU is running at capacity", }, /* See also alternate entries for 0000020036 / POWER9_PME_PM_BR_2PATH with code(s) 0000040036 at the bottom of this table. \n */ [ POWER9_PME_PM_BR_2PATH ] = { .pme_name = "PM_BR_2PATH", .pme_code = 0x0000020036, .pme_short_desc = "Branches that are not strongly biased", .pme_long_desc = "Branches that are not strongly biased", }, [ POWER9_PME_PM_BR_CMPL ] = { .pme_name = "PM_BR_CMPL", .pme_code = 0x000004D05E, .pme_short_desc = "Any Branch instruction completed", .pme_long_desc = "Any Branch instruction completed", }, [ POWER9_PME_PM_BR_CORECT_PRED_TAKEN_CMPL ] = { .pme_name = "PM_BR_CORECT_PRED_TAKEN_CMPL", .pme_code = 0x000000489C, .pme_short_desc = "Conditional Branch Completed in which the HW correctly predicted the direction as taken.", .pme_long_desc = "Conditional Branch Completed in which the HW correctly predicted the direction as taken. Counted at completion time", }, [ POWER9_PME_PM_BR_MPRED_CCACHE ] = { .pme_name = "PM_BR_MPRED_CCACHE", .pme_code = 0x00000040AC, .pme_short_desc = "Conditional Branch Completed that was Mispredicted due to the Count Cache Target Prediction", .pme_long_desc = "Conditional Branch Completed that was Mispredicted due to the Count Cache Target Prediction", }, [ POWER9_PME_PM_BR_MPRED_CMPL ] = { .pme_name = "PM_BR_MPRED_CMPL", .pme_code = 0x00000400F6, .pme_short_desc = "Number of Branch Mispredicts", .pme_long_desc = "Number of Branch Mispredicts", }, [ POWER9_PME_PM_BR_MPRED_LSTACK ] = { .pme_name = "PM_BR_MPRED_LSTACK", .pme_code = 0x00000048AC, .pme_short_desc = "Conditional Branch Completed that was Mispredicted due to the Link Stack Target Prediction", .pme_long_desc = "Conditional Branch Completed that was Mispredicted due to the Link Stack Target Prediction", }, [ POWER9_PME_PM_BR_MPRED_PCACHE ] = { .pme_name = "PM_BR_MPRED_PCACHE", .pme_code = 0x00000048B0, .pme_short_desc = "Conditional Branch Completed that was Mispredicted due to pattern cache prediction", .pme_long_desc = "Conditional Branch Completed that was Mispredicted due to pattern cache prediction", }, [ POWER9_PME_PM_BR_MPRED_TAKEN_CR ] = { .pme_name = "PM_BR_MPRED_TAKEN_CR", .pme_code = 0x00000040B8, .pme_short_desc = "A Conditional Branch that resolved to taken was mispredicted as not taken (due to the BHT Direction Prediction).", .pme_long_desc = "A Conditional Branch that resolved to taken was mispredicted as not taken (due to the BHT Direction Prediction).", }, [ POWER9_PME_PM_BR_MPRED_TAKEN_TA ] = { .pme_name = "PM_BR_MPRED_TAKEN_TA", .pme_code = 0x00000048B8, .pme_short_desc = "Conditional Branch Completed that was Mispredicted due to the Target Address Prediction from the Count Cache or Link Stack.", .pme_long_desc = "Conditional Branch Completed that was Mispredicted due to the Target Address Prediction from the Count Cache or Link Stack. Only XL-form branches that resolved Taken set this event.", }, [ POWER9_PME_PM_BR_PRED_CCACHE ] = { .pme_name = "PM_BR_PRED_CCACHE", .pme_code = 0x00000040A4, .pme_short_desc = "Conditional Branch Completed that used the Count Cache for Target Prediction", .pme_long_desc = "Conditional Branch Completed that used the Count Cache for Target Prediction", }, [ POWER9_PME_PM_BR_PRED_LSTACK ] = { .pme_name = "PM_BR_PRED_LSTACK", .pme_code = 0x00000040A8, .pme_short_desc = "Conditional Branch Completed that used the Link Stack for Target Prediction", .pme_long_desc = "Conditional Branch Completed that used the Link Stack for Target Prediction", }, [ POWER9_PME_PM_BR_PRED_PCACHE ] = { .pme_name = "PM_BR_PRED_PCACHE", .pme_code = 0x00000048A0, .pme_short_desc = "Conditional branch completed that used pattern cache prediction", .pme_long_desc = "Conditional branch completed that used pattern cache prediction", }, [ POWER9_PME_PM_BR_PRED_TAKEN_CR ] = { .pme_name = "PM_BR_PRED_TAKEN_CR", .pme_code = 0x00000040B0, .pme_short_desc = "Conditional Branch that had its direction predicted.", .pme_long_desc = "Conditional Branch that had its direction predicted. I-form branches do not set this event. In addition, B-form branches which do not use the BHT do not set this event - these are branches with BO-field set to 'always taken' and branches", }, [ POWER9_PME_PM_BR_PRED_TA ] = { .pme_name = "PM_BR_PRED_TA", .pme_code = 0x00000040B4, .pme_short_desc = "Conditional Branch Completed that had its target address predicted.", .pme_long_desc = "Conditional Branch Completed that had its target address predicted. Only XL-form branches set this event. This equal the sum of CCACHE, LSTACK, and PCACHE", }, [ POWER9_PME_PM_BR_PRED ] = { .pme_name = "PM_BR_PRED", .pme_code = 0x000000409C, .pme_short_desc = "Conditional Branch Executed in which the HW predicted the Direction or Target.", .pme_long_desc = "Conditional Branch Executed in which the HW predicted the Direction or Target. Includes taken and not taken and is counted at execution time", }, [ POWER9_PME_PM_BR_TAKEN_CMPL ] = { .pme_name = "PM_BR_TAKEN_CMPL", .pme_code = 0x00000200FA, .pme_short_desc = "New event for Branch Taken", .pme_long_desc = "New event for Branch Taken", }, [ POWER9_PME_PM_BRU_FIN ] = { .pme_name = "PM_BRU_FIN", .pme_code = 0x0000010068, .pme_short_desc = "Branch Instruction Finished", .pme_long_desc = "Branch Instruction Finished", }, [ POWER9_PME_PM_BR_UNCOND ] = { .pme_name = "PM_BR_UNCOND", .pme_code = 0x00000040A0, .pme_short_desc = "Unconditional Branch Completed.", .pme_long_desc = "Unconditional Branch Completed. HW branch prediction was not used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch always, or a B-form branch which was covenrted to a Resolve.", }, [ POWER9_PME_PM_BTAC_BAD_RESULT ] = { .pme_name = "PM_BTAC_BAD_RESULT", .pme_code = 0x00000050B0, .pme_short_desc = "BTAC thinks branch will be taken but it is either predicted not-taken by the BHT, or the target address is wrong (less common).", .pme_long_desc = "BTAC thinks branch will be taken but it is either predicted not-taken by the BHT, or the target address is wrong (less common). In both cases, a redirect will happen", }, [ POWER9_PME_PM_BTAC_GOOD_RESULT ] = { .pme_name = "PM_BTAC_GOOD_RESULT", .pme_code = 0x00000058B0, .pme_short_desc = "BTAC predicts a taken branch and the BHT agrees, and the target address is correct", .pme_long_desc = "BTAC predicts a taken branch and the BHT agrees, and the target address is correct", }, [ POWER9_PME_PM_CHIP_PUMP_CPRED ] = { .pme_name = "PM_CHIP_PUMP_CPRED", .pme_code = 0x0000010050, .pme_short_desc = "Initial and Final Pump Scope was chip pump (prediction=correct) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)", .pme_long_desc = "Initial and Final Pump Scope was chip pump (prediction=correct) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)", }, [ POWER9_PME_PM_CLB_HELD ] = { .pme_name = "PM_CLB_HELD", .pme_code = 0x000000208C, .pme_short_desc = "CLB (control logic block - indicates quadword fetch block) Hold: Any Reason", .pme_long_desc = "CLB (control logic block - indicates quadword fetch block) Hold: Any Reason", }, [ POWER9_PME_PM_CMPLU_STALL_ANY_SYNC ] = { .pme_name = "PM_CMPLU_STALL_ANY_SYNC", .pme_code = 0x000001E05A, .pme_short_desc = "Cycles in which the NTC sync instruction (isync, lwsync or hwsync) is not allowed to complete", .pme_long_desc = "Cycles in which the NTC sync instruction (isync, lwsync or hwsync) is not allowed to complete", }, [ POWER9_PME_PM_CMPLU_STALL_BRU ] = { .pme_name = "PM_CMPLU_STALL_BRU", .pme_code = 0x000004D018, .pme_short_desc = "Completion stall due to a Branch Unit", .pme_long_desc = "Completion stall due to a Branch Unit", }, [ POWER9_PME_PM_CMPLU_STALL_CRYPTO ] = { .pme_name = "PM_CMPLU_STALL_CRYPTO", .pme_code = 0x000004C01E, .pme_short_desc = "Finish stall because the NTF instruction was routed to the crypto execution pipe and was waiting to finish", .pme_long_desc = "Finish stall because the NTF instruction was routed to the crypto execution pipe and was waiting to finish", }, [ POWER9_PME_PM_CMPLU_STALL_DCACHE_MISS ] = { .pme_name = "PM_CMPLU_STALL_DCACHE_MISS", .pme_code = 0x000002C012, .pme_short_desc = "Finish stall because the NTF instruction was a load that missed the L1 and was waiting for the data to return from the nest", .pme_long_desc = "Finish stall because the NTF instruction was a load that missed the L1 and was waiting for the data to return from the nest", }, [ POWER9_PME_PM_CMPLU_STALL_DFLONG ] = { .pme_name = "PM_CMPLU_STALL_DFLONG", .pme_code = 0x000001005A, .pme_short_desc = "Finish stall because the NTF instruction was a multi-cycle instruction issued to the Decimal Floating Point execution pipe and waiting to finish.", .pme_long_desc = "Finish stall because the NTF instruction was a multi-cycle instruction issued to the Decimal Floating Point execution pipe and waiting to finish. Includes decimal floating point instructions + 128 bit binary floating point instructions. Qualified by multicycle", }, [ POWER9_PME_PM_CMPLU_STALL_DFU ] = { .pme_name = "PM_CMPLU_STALL_DFU", .pme_code = 0x000002D012, .pme_short_desc = "Finish stall because the NTF instruction was issued to the Decimal Floating Point execution pipe and waiting to finish.", .pme_long_desc = "Finish stall because the NTF instruction was issued to the Decimal Floating Point execution pipe and waiting to finish. Includes decimal floating point instructions + 128 bit binary floating point instructions. Not qualified by multicycle", }, [ POWER9_PME_PM_CMPLU_STALL_DMISS_L21_L31 ] = { .pme_name = "PM_CMPLU_STALL_DMISS_L21_L31", .pme_code = 0x000002C018, .pme_short_desc = "Completion stall by Dcache miss which resolved on chip ( excluding local L2/L3)", .pme_long_desc = "Completion stall by Dcache miss which resolved on chip ( excluding local L2/L3)", }, [ POWER9_PME_PM_CMPLU_STALL_DMISS_L2L3_CONFLICT ] = { .pme_name = "PM_CMPLU_STALL_DMISS_L2L3_CONFLICT", .pme_code = 0x000004C016, .pme_short_desc = "Completion stall due to cache miss that resolves in the L2 or L3 with a conflict", .pme_long_desc = "Completion stall due to cache miss that resolves in the L2 or L3 with a conflict", }, [ POWER9_PME_PM_CMPLU_STALL_DMISS_L2L3 ] = { .pme_name = "PM_CMPLU_STALL_DMISS_L2L3", .pme_code = 0x000001003C, .pme_short_desc = "Completion stall by Dcache miss which resolved in L2/L3", .pme_long_desc = "Completion stall by Dcache miss which resolved in L2/L3", }, [ POWER9_PME_PM_CMPLU_STALL_DMISS_L3MISS ] = { .pme_name = "PM_CMPLU_STALL_DMISS_L3MISS", .pme_code = 0x000004C01A, .pme_short_desc = "Completion stall due to cache miss resolving missed the L3", .pme_long_desc = "Completion stall due to cache miss resolving missed the L3", }, [ POWER9_PME_PM_CMPLU_STALL_DMISS_LMEM ] = { .pme_name = "PM_CMPLU_STALL_DMISS_LMEM", .pme_code = 0x0000030038, .pme_short_desc = "Completion stall due to cache miss that resolves in local memory", .pme_long_desc = "Completion stall due to cache miss that resolves in local memory", }, [ POWER9_PME_PM_CMPLU_STALL_DMISS_REMOTE ] = { .pme_name = "PM_CMPLU_STALL_DMISS_REMOTE", .pme_code = 0x000002C01C, .pme_short_desc = "Completion stall by Dcache miss which resolved from remote chip (cache or memory)", .pme_long_desc = "Completion stall by Dcache miss which resolved from remote chip (cache or memory)", }, [ POWER9_PME_PM_CMPLU_STALL_DPLONG ] = { .pme_name = "PM_CMPLU_STALL_DPLONG", .pme_code = 0x000003405C, .pme_short_desc = "Finish stall because the NTF instruction was a scalar multi-cycle instruction issued to the Double Precision execution pipe and waiting to finish.", .pme_long_desc = "Finish stall because the NTF instruction was a scalar multi-cycle instruction issued to the Double Precision execution pipe and waiting to finish. Includes binary floating point instructions in 32 and 64 bit binary floating point format. Qualified by NOT vector AND multicycle", }, [ POWER9_PME_PM_CMPLU_STALL_DP ] = { .pme_name = "PM_CMPLU_STALL_DP", .pme_code = 0x000001005C, .pme_short_desc = "Finish stall because the NTF instruction was a scalar instruction issued to the Double Precision execution pipe and waiting to finish.", .pme_long_desc = "Finish stall because the NTF instruction was a scalar instruction issued to the Double Precision execution pipe and waiting to finish. Includes binary floating point instructions in 32 and 64 bit binary floating point format. Not qualified multicycle. Qualified by NOT vector", }, [ POWER9_PME_PM_CMPLU_STALL_EIEIO ] = { .pme_name = "PM_CMPLU_STALL_EIEIO", .pme_code = 0x000004D01A, .pme_short_desc = "Finish stall because the NTF instruction is an EIEIO waiting for response from L2", .pme_long_desc = "Finish stall because the NTF instruction is an EIEIO waiting for response from L2", }, [ POWER9_PME_PM_CMPLU_STALL_EMQ_FULL ] = { .pme_name = "PM_CMPLU_STALL_EMQ_FULL", .pme_code = 0x0000030004, .pme_short_desc = "Finish stall because the next to finish instruction suffered an ERAT miss and the EMQ was full", .pme_long_desc = "Finish stall because the next to finish instruction suffered an ERAT miss and the EMQ was full", }, [ POWER9_PME_PM_CMPLU_STALL_ERAT_MISS ] = { .pme_name = "PM_CMPLU_STALL_ERAT_MISS", .pme_code = 0x000004C012, .pme_short_desc = "Finish stall because the NTF instruction was a load or store that suffered a translation miss", .pme_long_desc = "Finish stall because the NTF instruction was a load or store that suffered a translation miss", }, [ POWER9_PME_PM_CMPLU_STALL_EXCEPTION ] = { .pme_name = "PM_CMPLU_STALL_EXCEPTION", .pme_code = 0x000003003A, .pme_short_desc = "Cycles in which the NTC instruction is not allowed to complete because it was interrupted by ANY exception, which has to be serviced before the instruction can complete", .pme_long_desc = "Cycles in which the NTC instruction is not allowed to complete because it was interrupted by ANY exception, which has to be serviced before the instruction can complete", }, [ POWER9_PME_PM_CMPLU_STALL_EXEC_UNIT ] = { .pme_name = "PM_CMPLU_STALL_EXEC_UNIT", .pme_code = 0x000002D018, .pme_short_desc = "Completion stall due to execution units (FXU/VSU/CRU)", .pme_long_desc = "Completion stall due to execution units (FXU/VSU/CRU)", }, [ POWER9_PME_PM_CMPLU_STALL_FLUSH_ANY_THREAD ] = { .pme_name = "PM_CMPLU_STALL_FLUSH_ANY_THREAD", .pme_code = 0x000001E056, .pme_short_desc = "Cycles in which the NTC instruction is not allowed to complete because any of the 4 threads in the same core suffered a flush, which blocks completion", .pme_long_desc = "Cycles in which the NTC instruction is not allowed to complete because any of the 4 threads in the same core suffered a flush, which blocks completion", }, [ POWER9_PME_PM_CMPLU_STALL_FXLONG ] = { .pme_name = "PM_CMPLU_STALL_FXLONG", .pme_code = 0x000004D016, .pme_short_desc = "Completion stall due to a long latency scalar fixed point instruction (division, square root)", .pme_long_desc = "Completion stall due to a long latency scalar fixed point instruction (division, square root)", }, [ POWER9_PME_PM_CMPLU_STALL_FXU ] = { .pme_name = "PM_CMPLU_STALL_FXU", .pme_code = 0x000002D016, .pme_short_desc = "Finish stall due to a scalar fixed point or CR instruction in the execution pipeline.", .pme_long_desc = "Finish stall due to a scalar fixed point or CR instruction in the execution pipeline. These instructions get routed to the ALU, ALU2, and DIV pipes", }, [ POWER9_PME_PM_CMPLU_STALL_HWSYNC ] = { .pme_name = "PM_CMPLU_STALL_HWSYNC", .pme_code = 0x0000030036, .pme_short_desc = "completion stall due to hwsync", .pme_long_desc = "completion stall due to hwsync", }, [ POWER9_PME_PM_CMPLU_STALL_LARX ] = { .pme_name = "PM_CMPLU_STALL_LARX", .pme_code = 0x000001002A, .pme_short_desc = "Finish stall because the NTF instruction was a larx waiting to be satisfied", .pme_long_desc = "Finish stall because the NTF instruction was a larx waiting to be satisfied", }, [ POWER9_PME_PM_CMPLU_STALL_LHS ] = { .pme_name = "PM_CMPLU_STALL_LHS", .pme_code = 0x000002C01A, .pme_short_desc = "Finish stall because the NTF instruction was a load that hit on an older store and it was waiting for store data", .pme_long_desc = "Finish stall because the NTF instruction was a load that hit on an older store and it was waiting for store data", }, [ POWER9_PME_PM_CMPLU_STALL_LMQ_FULL ] = { .pme_name = "PM_CMPLU_STALL_LMQ_FULL", .pme_code = 0x000004C014, .pme_short_desc = "Finish stall because the NTF instruction was a load that missed in the L1 and the LMQ was unable to accept this load miss request because it was full", .pme_long_desc = "Finish stall because the NTF instruction was a load that missed in the L1 and the LMQ was unable to accept this load miss request because it was full", }, [ POWER9_PME_PM_CMPLU_STALL_LOAD_FINISH ] = { .pme_name = "PM_CMPLU_STALL_LOAD_FINISH", .pme_code = 0x000004D014, .pme_short_desc = "Finish stall because the NTF instruction was a load instruction with all its dependencies satisfied just going through the LSU pipe to finish", .pme_long_desc = "Finish stall because the NTF instruction was a load instruction with all its dependencies satisfied just going through the LSU pipe to finish", }, [ POWER9_PME_PM_CMPLU_STALL_LRQ_FULL ] = { .pme_name = "PM_CMPLU_STALL_LRQ_FULL", .pme_code = 0x000002D014, .pme_short_desc = "Finish stall because the NTF instruction was a load that was held in LSAQ (load-store address queue) because the LRQ (load-reorder queue) was full", .pme_long_desc = "Finish stall because the NTF instruction was a load that was held in LSAQ (load-store address queue) because the LRQ (load-reorder queue) was full", }, [ POWER9_PME_PM_CMPLU_STALL_LRQ_OTHER ] = { .pme_name = "PM_CMPLU_STALL_LRQ_OTHER", .pme_code = 0x0000010004, .pme_short_desc = "Finish stall due to LRQ miscellaneous reasons, lost arbitration to LMQ slot, bank collisions, set prediction cleanup, set prediction multihit and others", .pme_long_desc = "Finish stall due to LRQ miscellaneous reasons, lost arbitration to LMQ slot, bank collisions, set prediction cleanup, set prediction multihit and others", }, [ POWER9_PME_PM_CMPLU_STALL_LSAQ_ARB ] = { .pme_name = "PM_CMPLU_STALL_LSAQ_ARB", .pme_code = 0x000004E016, .pme_short_desc = "Finish stall because the NTF instruction was a load or store that was held in LSAQ because an older instruction from SRQ or LRQ won arbitration to the LSU pipe when this instruction tried to launch", .pme_long_desc = "Finish stall because the NTF instruction was a load or store that was held in LSAQ because an older instruction from SRQ or LRQ won arbitration to the LSU pipe when this instruction tried to launch", }, [ POWER9_PME_PM_CMPLU_STALL_LSU_FIN ] = { .pme_name = "PM_CMPLU_STALL_LSU_FIN", .pme_code = 0x000001003A, .pme_short_desc = "Finish stall because the NTF instruction was an LSU op (other than a load or a store) with all its dependencies met and just going through the LSU pipe to finish", .pme_long_desc = "Finish stall because the NTF instruction was an LSU op (other than a load or a store) with all its dependencies met and just going through the LSU pipe to finish", }, [ POWER9_PME_PM_CMPLU_STALL_LSU_FLUSH_NEXT ] = { .pme_name = "PM_CMPLU_STALL_LSU_FLUSH_NEXT", .pme_code = 0x000002E01A, .pme_short_desc = "Completion stall of one cycle because the LSU requested to flush the next iop in the sequence.", .pme_long_desc = "Completion stall of one cycle because the LSU requested to flush the next iop in the sequence. It takes 1 cycle for the ISU to process this request before the LSU instruction is allowed to complete", }, [ POWER9_PME_PM_CMPLU_STALL_LSU_MFSPR ] = { .pme_name = "PM_CMPLU_STALL_LSU_MFSPR", .pme_code = 0x0000034056, .pme_short_desc = "Finish stall because the NTF instruction was a mfspr instruction targeting an LSU SPR and it was waiting for the register data to be returned", .pme_long_desc = "Finish stall because the NTF instruction was a mfspr instruction targeting an LSU SPR and it was waiting for the register data to be returned", }, [ POWER9_PME_PM_CMPLU_STALL_LSU ] = { .pme_name = "PM_CMPLU_STALL_LSU", .pme_code = 0x000002C010, .pme_short_desc = "Completion stall by LSU instruction", .pme_long_desc = "Completion stall by LSU instruction", }, [ POWER9_PME_PM_CMPLU_STALL_LWSYNC ] = { .pme_name = "PM_CMPLU_STALL_LWSYNC", .pme_code = 0x0000010036, .pme_short_desc = "completion stall due to lwsync", .pme_long_desc = "completion stall due to lwsync", }, [ POWER9_PME_PM_CMPLU_STALL_MTFPSCR ] = { .pme_name = "PM_CMPLU_STALL_MTFPSCR", .pme_code = 0x000004E012, .pme_short_desc = "Completion stall because the ISU is updating the register and notifying the Effective Address Table (EAT)", .pme_long_desc = "Completion stall because the ISU is updating the register and notifying the Effective Address Table (EAT)", }, [ POWER9_PME_PM_CMPLU_STALL_NESTED_TBEGIN ] = { .pme_name = "PM_CMPLU_STALL_NESTED_TBEGIN", .pme_code = 0x000001E05C, .pme_short_desc = "Completion stall because the ISU is updating the TEXASR to keep track of the nested tbegin.", .pme_long_desc = "Completion stall because the ISU is updating the TEXASR to keep track of the nested tbegin. This is a short delay, and it includes ROT", }, [ POWER9_PME_PM_CMPLU_STALL_NESTED_TEND ] = { .pme_name = "PM_CMPLU_STALL_NESTED_TEND", .pme_code = 0x000003003C, .pme_short_desc = "Completion stall because the ISU is updating the TEXASR to keep track of the nested tend and decrement the TEXASR nested level.", .pme_long_desc = "Completion stall because the ISU is updating the TEXASR to keep track of the nested tend and decrement the TEXASR nested level. This is a short delay", }, [ POWER9_PME_PM_CMPLU_STALL_NTC_DISP_FIN ] = { .pme_name = "PM_CMPLU_STALL_NTC_DISP_FIN", .pme_code = 0x000004E018, .pme_short_desc = "Finish stall because the NTF instruction was one that must finish at dispatch.", .pme_long_desc = "Finish stall because the NTF instruction was one that must finish at dispatch.", }, [ POWER9_PME_PM_CMPLU_STALL_NTC_FLUSH ] = { .pme_name = "PM_CMPLU_STALL_NTC_FLUSH", .pme_code = 0x000002E01E, .pme_short_desc = "Completion stall due to ntc flush", .pme_long_desc = "Completion stall due to ntc flush", }, [ POWER9_PME_PM_CMPLU_STALL_OTHER_CMPL ] = { .pme_name = "PM_CMPLU_STALL_OTHER_CMPL", .pme_code = 0x0000030006, .pme_short_desc = "Instructions the core completed while this tread was stalled", .pme_long_desc = "Instructions the core completed while this tread was stalled", }, [ POWER9_PME_PM_CMPLU_STALL_PASTE ] = { .pme_name = "PM_CMPLU_STALL_PASTE", .pme_code = 0x000002C016, .pme_short_desc = "Finish stall because the NTF instruction was a paste waiting for response from L2", .pme_long_desc = "Finish stall because the NTF instruction was a paste waiting for response from L2", }, [ POWER9_PME_PM_CMPLU_STALL_PM ] = { .pme_name = "PM_CMPLU_STALL_PM", .pme_code = 0x000003000A, .pme_short_desc = "Finish stall because the NTF instruction was issued to the Permute execution pipe and waiting to finish.", .pme_long_desc = "Finish stall because the NTF instruction was issued to the Permute execution pipe and waiting to finish. Includes permute and decimal fixed point instructions (128 bit BCD arithmetic) + a few 128 bit fixpoint add/subtract instructions with carry. Not qualified by vector or multicycle", }, [ POWER9_PME_PM_CMPLU_STALL_SLB ] = { .pme_name = "PM_CMPLU_STALL_SLB", .pme_code = 0x000001E052, .pme_short_desc = "Finish stall because the NTF instruction was awaiting L2 response for an SLB", .pme_long_desc = "Finish stall because the NTF instruction was awaiting L2 response for an SLB", }, [ POWER9_PME_PM_CMPLU_STALL_SPEC_FINISH ] = { .pme_name = "PM_CMPLU_STALL_SPEC_FINISH", .pme_code = 0x0000030028, .pme_short_desc = "Finish stall while waiting for the non-speculative finish of either a stcx waiting for its result or a load waiting for non-critical sectors of data and ECC", .pme_long_desc = "Finish stall while waiting for the non-speculative finish of either a stcx waiting for its result or a load waiting for non-critical sectors of data and ECC", }, [ POWER9_PME_PM_CMPLU_STALL_SRQ_FULL ] = { .pme_name = "PM_CMPLU_STALL_SRQ_FULL", .pme_code = 0x0000030016, .pme_short_desc = "Finish stall because the NTF instruction was a store that was held in LSAQ because the SRQ was full", .pme_long_desc = "Finish stall because the NTF instruction was a store that was held in LSAQ because the SRQ was full", }, [ POWER9_PME_PM_CMPLU_STALL_STCX ] = { .pme_name = "PM_CMPLU_STALL_STCX", .pme_code = 0x000002D01C, .pme_short_desc = "Finish stall because the NTF instruction was a stcx waiting for response from L2", .pme_long_desc = "Finish stall because the NTF instruction was a stcx waiting for response from L2", }, [ POWER9_PME_PM_CMPLU_STALL_ST_FWD ] = { .pme_name = "PM_CMPLU_STALL_ST_FWD", .pme_code = 0x000004C01C, .pme_short_desc = "Completion stall due to store forward", .pme_long_desc = "Completion stall due to store forward", }, [ POWER9_PME_PM_CMPLU_STALL_STORE_DATA ] = { .pme_name = "PM_CMPLU_STALL_STORE_DATA", .pme_code = 0x0000030026, .pme_short_desc = "Finish stall because the next to finish instruction was a store waiting on data", .pme_long_desc = "Finish stall because the next to finish instruction was a store waiting on data", }, [ POWER9_PME_PM_CMPLU_STALL_STORE_FIN_ARB ] = { .pme_name = "PM_CMPLU_STALL_STORE_FIN_ARB", .pme_code = 0x0000030014, .pme_short_desc = "Finish stall because the NTF instruction was a store waiting for a slot in the store finish pipe.", .pme_long_desc = "Finish stall because the NTF instruction was a store waiting for a slot in the store finish pipe. This means the instruction is ready to finish but there are instructions ahead of it, using the finish pipe", }, [ POWER9_PME_PM_CMPLU_STALL_STORE_FINISH ] = { .pme_name = "PM_CMPLU_STALL_STORE_FINISH", .pme_code = 0x000002C014, .pme_short_desc = "Finish stall because the NTF instruction was a store with all its dependencies met, just waiting to go through the LSU pipe to finish", .pme_long_desc = "Finish stall because the NTF instruction was a store with all its dependencies met, just waiting to go through the LSU pipe to finish", }, [ POWER9_PME_PM_CMPLU_STALL_STORE_PIPE_ARB ] = { .pme_name = "PM_CMPLU_STALL_STORE_PIPE_ARB", .pme_code = 0x000004C010, .pme_short_desc = "Finish stall because the NTF instruction was a store waiting for the next relaunch opportunity after an internal reject.", .pme_long_desc = "Finish stall because the NTF instruction was a store waiting for the next relaunch opportunity after an internal reject. This means the instruction is ready to relaunch and tried once but lost arbitration", }, [ POWER9_PME_PM_CMPLU_STALL_SYNC_PMU_INT ] = { .pme_name = "PM_CMPLU_STALL_SYNC_PMU_INT", .pme_code = 0x000002C01E, .pme_short_desc = "Cycles in which the NTC instruction is waiting for a synchronous PMU interrupt", .pme_long_desc = "Cycles in which the NTC instruction is waiting for a synchronous PMU interrupt", }, [ POWER9_PME_PM_CMPLU_STALL_TEND ] = { .pme_name = "PM_CMPLU_STALL_TEND", .pme_code = 0x000001E050, .pme_short_desc = "Finish stall because the NTF instruction was a tend instruction awaiting response from L2", .pme_long_desc = "Finish stall because the NTF instruction was a tend instruction awaiting response from L2", }, [ POWER9_PME_PM_CMPLU_STALL_THRD ] = { .pme_name = "PM_CMPLU_STALL_THRD", .pme_code = 0x000001001C, .pme_short_desc = "Completion Stalled because the thread was blocked", .pme_long_desc = "Completion Stalled because the thread was blocked", }, [ POWER9_PME_PM_CMPLU_STALL_TLBIE ] = { .pme_name = "PM_CMPLU_STALL_TLBIE", .pme_code = 0x000002E01C, .pme_short_desc = "Finish stall because the NTF instruction was a tlbie waiting for response from L2", .pme_long_desc = "Finish stall because the NTF instruction was a tlbie waiting for response from L2", }, [ POWER9_PME_PM_CMPLU_STALL ] = { .pme_name = "PM_CMPLU_STALL", .pme_code = 0x000001E054, .pme_short_desc = "Nothing completed and ICT not empty", .pme_long_desc = "Nothing completed and ICT not empty", }, [ POWER9_PME_PM_CMPLU_STALL_VDPLONG ] = { .pme_name = "PM_CMPLU_STALL_VDPLONG", .pme_code = 0x000003C05A, .pme_short_desc = "Finish stall because the NTF instruction was a scalar multi-cycle instruction issued to the Double Precision execution pipe and waiting to finish.", .pme_long_desc = "Finish stall because the NTF instruction was a scalar multi-cycle instruction issued to the Double Precision execution pipe and waiting to finish. Includes binary floating point instructions in 32 and 64 bit binary floating point format. Qualified by NOT vector AND multicycle", }, [ POWER9_PME_PM_CMPLU_STALL_VDP ] = { .pme_name = "PM_CMPLU_STALL_VDP", .pme_code = 0x000004405C, .pme_short_desc = "Finish stall because the NTF instruction was a vector instruction issued to the Double Precision execution pipe and waiting to finish.", .pme_long_desc = "Finish stall because the NTF instruction was a vector instruction issued to the Double Precision execution pipe and waiting to finish. Includes binary floating point instructions in 32 and 64 bit binary floating point format. Not qualified multicycle. Qualified by vector", }, [ POWER9_PME_PM_CMPLU_STALL_VFXLONG ] = { .pme_name = "PM_CMPLU_STALL_VFXLONG", .pme_code = 0x000002E018, .pme_short_desc = "Completion stall due to a long latency vector fixed point instruction (division, square root)", .pme_long_desc = "Completion stall due to a long latency vector fixed point instruction (division, square root)", }, [ POWER9_PME_PM_CMPLU_STALL_VFXU ] = { .pme_name = "PM_CMPLU_STALL_VFXU", .pme_code = 0x000003C05C, .pme_short_desc = "Finish stall due to a vector fixed point instruction in the execution pipeline.", .pme_long_desc = "Finish stall due to a vector fixed point instruction in the execution pipeline. These instructions get routed to the ALU, ALU2, and DIV pipes", }, [ POWER9_PME_PM_CO0_BUSY ] = { .pme_name = "PM_CO0_BUSY", .pme_code = 0x000003608C, .pme_short_desc = "CO mach 0 Busy.", .pme_long_desc = "CO mach 0 Busy. Used by PMU to sample ave CO lifetime (mach0 used as sample point)", }, [ POWER9_PME_PM_CO0_BUSY_ALT ] = { .pme_name = "PM_CO0_BUSY_ALT", .pme_code = 0x000004608C, .pme_short_desc = "CO mach 0 Busy.", .pme_long_desc = "CO mach 0 Busy. Used by PMU to sample ave CO lifetime (mach0 used as sample point)", }, [ POWER9_PME_PM_CO_DISP_FAIL ] = { .pme_name = "PM_CO_DISP_FAIL", .pme_code = 0x0000016886, .pme_short_desc = "CO dispatch failed due to all CO machines being busy", .pme_long_desc = "CO dispatch failed due to all CO machines being busy", }, [ POWER9_PME_PM_CO_TM_SC_FOOTPRINT ] = { .pme_name = "PM_CO_TM_SC_FOOTPRINT", .pme_code = 0x0000026086, .pme_short_desc = "L2 did a cleanifdirty CO to the L3 (ie created an SC line in the L3) OR L2 TM_store hit dirty HPC line and L3 indicated SC line formed in L3 on RDR bus", .pme_long_desc = "L2 did a cleanifdirty CO to the L3 (ie created an SC line in the L3) OR L2 TM_store hit dirty HPC line and L3 indicated SC line formed in L3 on RDR bus", }, [ POWER9_PME_PM_CO_USAGE ] = { .pme_name = "PM_CO_USAGE", .pme_code = 0x000002688C, .pme_short_desc = "Continuous 16 cycle (2to1) window where this signals rotates thru sampling each CO machine busy.", .pme_long_desc = "Continuous 16 cycle (2to1) window where this signals rotates thru sampling each CO machine busy. PMU uses this wave to then do 16 cyc count to sample total number of machs running", }, /* See also alternate entries for 000001001E / POWER9_PME_PM_CYC with code(s) 000002001E 000003001E 000004001E at the bottom of this table. \n */ [ POWER9_PME_PM_CYC ] = { .pme_name = "PM_CYC", .pme_code = 0x000001001E, .pme_short_desc = "Processor cycles", .pme_long_desc = "Processor cycles", }, [ POWER9_PME_PM_DARQ0_0_3_ENTRIES ] = { .pme_name = "PM_DARQ0_0_3_ENTRIES", .pme_code = 0x000004D04A, .pme_short_desc = "Cycles in which 3 or less DARQ entries (out of 12) are in use", .pme_long_desc = "Cycles in which 3 or less DARQ entries (out of 12) are in use", }, [ POWER9_PME_PM_DARQ0_10_12_ENTRIES ] = { .pme_name = "PM_DARQ0_10_12_ENTRIES", .pme_code = 0x000001D058, .pme_short_desc = "Cycles in which 10 or more DARQ entries (out of 12) are in use", .pme_long_desc = "Cycles in which 10 or more DARQ entries (out of 12) are in use", }, [ POWER9_PME_PM_DARQ0_4_6_ENTRIES ] = { .pme_name = "PM_DARQ0_4_6_ENTRIES", .pme_code = 0x000003504E, .pme_short_desc = "Cycles in which 4, 5, or 6 DARQ entries (out of 12) are in use", .pme_long_desc = "Cycles in which 4, 5, or 6 DARQ entries (out of 12) are in use", }, [ POWER9_PME_PM_DARQ0_7_9_ENTRIES ] = { .pme_name = "PM_DARQ0_7_9_ENTRIES", .pme_code = 0x000002E050, .pme_short_desc = "Cycles in which 7,8, or 9 DARQ entries (out of 12) are in use", .pme_long_desc = "Cycles in which 7,8, or 9 DARQ entries (out of 12) are in use", }, [ POWER9_PME_PM_DARQ1_0_3_ENTRIES ] = { .pme_name = "PM_DARQ1_0_3_ENTRIES", .pme_code = 0x000004C122, .pme_short_desc = "Cycles in which 3 or fewer DARQ1 entries (out of 12) are in use", .pme_long_desc = "Cycles in which 3 or fewer DARQ1 entries (out of 12) are in use", }, [ POWER9_PME_PM_DARQ1_10_12_ENTRIES ] = { .pme_name = "PM_DARQ1_10_12_ENTRIES", .pme_code = 0x0000020058, .pme_short_desc = "Cycles in which 10 or more DARQ1 entries (out of 12) are in use", .pme_long_desc = "Cycles in which 10 or more DARQ1 entries (out of 12) are in use", }, [ POWER9_PME_PM_DARQ1_4_6_ENTRIES ] = { .pme_name = "PM_DARQ1_4_6_ENTRIES", .pme_code = 0x000003E050, .pme_short_desc = "Cycles in which 4, 5, or 6 DARQ1 entries (out of 12) are in use", .pme_long_desc = "Cycles in which 4, 5, or 6 DARQ1 entries (out of 12) are in use", }, [ POWER9_PME_PM_DARQ1_7_9_ENTRIES ] = { .pme_name = "PM_DARQ1_7_9_ENTRIES", .pme_code = 0x000002005A, .pme_short_desc = "Cycles in which 7 to 9 DARQ1 entries (out of 12) are in use", .pme_long_desc = "Cycles in which 7 to 9 DARQ1 entries (out of 12) are in use", }, [ POWER9_PME_PM_DARQ_STORE_REJECT ] = { .pme_name = "PM_DARQ_STORE_REJECT", .pme_code = 0x000004405E, .pme_short_desc = "The DARQ attempted to transmit a store into an LSAQ or SRQ entry but It was rejected.", .pme_long_desc = "The DARQ attempted to transmit a store into an LSAQ or SRQ entry but It was rejected. Divide by PM_DARQ_STORE_XMIT to get reject ratio", }, [ POWER9_PME_PM_DARQ_STORE_XMIT ] = { .pme_name = "PM_DARQ_STORE_XMIT", .pme_code = 0x0000030064, .pme_short_desc = "The DARQ attempted to transmit a store into an LSAQ or SRQ entry.", .pme_long_desc = "The DARQ attempted to transmit a store into an LSAQ or SRQ entry. Includes rejects. Not qualified by thread, so it includes counts for the whole core", }, [ POWER9_PME_PM_DATA_CHIP_PUMP_CPRED ] = { .pme_name = "PM_DATA_CHIP_PUMP_CPRED", .pme_code = 0x000001C050, .pme_short_desc = "Initial and Final Pump Scope was chip pump (prediction=correct) for a demand load", .pme_long_desc = "Initial and Final Pump Scope was chip pump (prediction=correct) for a demand load", }, [ POWER9_PME_PM_DATA_FROM_DL2L3_MOD ] = { .pme_name = "PM_DATA_FROM_DL2L3_MOD", .pme_code = 0x000004C048, .pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load", .pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load", }, [ POWER9_PME_PM_DATA_FROM_DL2L3_SHR ] = { .pme_name = "PM_DATA_FROM_DL2L3_SHR", .pme_code = 0x000003C048, .pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load", .pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load", }, [ POWER9_PME_PM_DATA_FROM_DL4 ] = { .pme_name = "PM_DATA_FROM_DL4", .pme_code = 0x000003C04C, .pme_short_desc = "The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to a demand load", .pme_long_desc = "The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to a demand load", }, [ POWER9_PME_PM_DATA_FROM_DMEM ] = { .pme_name = "PM_DATA_FROM_DMEM", .pme_code = 0x000004C04C, .pme_short_desc = "The processor's data cache was reloaded from another chip's memory on the same Node or Group (Distant) due to a demand load", .pme_long_desc = "The processor's data cache was reloaded from another chip's memory on the same Node or Group (Distant) due to a demand load", }, [ POWER9_PME_PM_DATA_FROM_L21_MOD ] = { .pme_name = "PM_DATA_FROM_L21_MOD", .pme_code = 0x000004C046, .pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another core's L2 on the same chip due to a demand load", .pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another core's L2 on the same chip due to a demand load", }, [ POWER9_PME_PM_DATA_FROM_L21_SHR ] = { .pme_name = "PM_DATA_FROM_L21_SHR", .pme_code = 0x000003C046, .pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to a demand load", .pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to a demand load", }, [ POWER9_PME_PM_DATA_FROM_L2_DISP_CONFLICT_LDHITST ] = { .pme_name = "PM_DATA_FROM_L2_DISP_CONFLICT_LDHITST", .pme_code = 0x000003C040, .pme_short_desc = "The processor's data cache was reloaded from local core's L2 with load hit store conflict due to a demand load", .pme_long_desc = "The processor's data cache was reloaded from local core's L2 with load hit store conflict due to a demand load", }, [ POWER9_PME_PM_DATA_FROM_L2_DISP_CONFLICT_OTHER ] = { .pme_name = "PM_DATA_FROM_L2_DISP_CONFLICT_OTHER", .pme_code = 0x000004C040, .pme_short_desc = "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to a demand load", .pme_long_desc = "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to a demand load", }, [ POWER9_PME_PM_DATA_FROM_L2_MEPF ] = { .pme_name = "PM_DATA_FROM_L2_MEPF", .pme_code = 0x000002C040, .pme_short_desc = "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state due to a demand load", .pme_long_desc = "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state due to a demand load", }, [ POWER9_PME_PM_DATA_FROM_L2MISS_MOD ] = { .pme_name = "PM_DATA_FROM_L2MISS_MOD", .pme_code = 0x000001C04E, .pme_short_desc = "The processor's data cache was reloaded from a location other than the local core's L2 due to a demand load", .pme_long_desc = "The processor's data cache was reloaded from a location other than the local core's L2 due to a demand load", }, [ POWER9_PME_PM_DATA_FROM_L2MISS ] = { .pme_name = "PM_DATA_FROM_L2MISS", .pme_code = 0x00000200FE, .pme_short_desc = "Demand LD - L2 Miss (not L2 hit)", .pme_long_desc = "Demand LD - L2 Miss (not L2 hit)", }, [ POWER9_PME_PM_DATA_FROM_L2_NO_CONFLICT ] = { .pme_name = "PM_DATA_FROM_L2_NO_CONFLICT", .pme_code = 0x000001C040, .pme_short_desc = "The processor's data cache was reloaded from local core's L2 without conflict due to a demand load", .pme_long_desc = "The processor's data cache was reloaded from local core's L2 without conflict due to a demand load", }, [ POWER9_PME_PM_DATA_FROM_L2 ] = { .pme_name = "PM_DATA_FROM_L2", .pme_code = 0x000001C042, .pme_short_desc = "The processor's data cache was reloaded from local core's L2 due to a demand load", .pme_long_desc = "The processor's data cache was reloaded from local core's L2 due to a demand load", }, [ POWER9_PME_PM_DATA_FROM_L31_ECO_MOD ] = { .pme_name = "PM_DATA_FROM_L31_ECO_MOD", .pme_code = 0x000004C044, .pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to a demand load", .pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to a demand load", }, [ POWER9_PME_PM_DATA_FROM_L31_ECO_SHR ] = { .pme_name = "PM_DATA_FROM_L31_ECO_SHR", .pme_code = 0x000003C044, .pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to a demand load", .pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to a demand load", }, [ POWER9_PME_PM_DATA_FROM_L31_MOD ] = { .pme_name = "PM_DATA_FROM_L31_MOD", .pme_code = 0x000002C044, .pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another core's L3 on the same chip due to a demand load", .pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another core's L3 on the same chip due to a demand load", }, [ POWER9_PME_PM_DATA_FROM_L31_SHR ] = { .pme_name = "PM_DATA_FROM_L31_SHR", .pme_code = 0x000001C046, .pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another core's L3 on the same chip due to a demand load", .pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another core's L3 on the same chip due to a demand load", }, [ POWER9_PME_PM_DATA_FROM_L3_DISP_CONFLICT ] = { .pme_name = "PM_DATA_FROM_L3_DISP_CONFLICT", .pme_code = 0x000003C042, .pme_short_desc = "The processor's data cache was reloaded from local core's L3 with dispatch conflict due to a demand load", .pme_long_desc = "The processor's data cache was reloaded from local core's L3 with dispatch conflict due to a demand load", }, [ POWER9_PME_PM_DATA_FROM_L3_MEPF ] = { .pme_name = "PM_DATA_FROM_L3_MEPF", .pme_code = 0x000002C042, .pme_short_desc = "The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state due to a demand load", .pme_long_desc = "The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state due to a demand load", }, [ POWER9_PME_PM_DATA_FROM_L3MISS_MOD ] = { .pme_name = "PM_DATA_FROM_L3MISS_MOD", .pme_code = 0x000004C04E, .pme_short_desc = "The processor's data cache was reloaded from a location other than the local core's L3 due to a demand load", .pme_long_desc = "The processor's data cache was reloaded from a location other than the local core's L3 due to a demand load", }, [ POWER9_PME_PM_DATA_FROM_L3MISS ] = { .pme_name = "PM_DATA_FROM_L3MISS", .pme_code = 0x00000300FE, .pme_short_desc = "Demand LD - L3 Miss (not L2 hit and not L3 hit)", .pme_long_desc = "Demand LD - L3 Miss (not L2 hit and not L3 hit)", }, [ POWER9_PME_PM_DATA_FROM_L3_NO_CONFLICT ] = { .pme_name = "PM_DATA_FROM_L3_NO_CONFLICT", .pme_code = 0x000001C044, .pme_short_desc = "The processor's data cache was reloaded from local core's L3 without conflict due to a demand load", .pme_long_desc = "The processor's data cache was reloaded from local core's L3 without conflict due to a demand load", }, [ POWER9_PME_PM_DATA_FROM_L3 ] = { .pme_name = "PM_DATA_FROM_L3", .pme_code = 0x000004C042, .pme_short_desc = "The processor's data cache was reloaded from local core's L3 due to a demand load", .pme_long_desc = "The processor's data cache was reloaded from local core's L3 due to a demand load", }, [ POWER9_PME_PM_DATA_FROM_LL4 ] = { .pme_name = "PM_DATA_FROM_LL4", .pme_code = 0x000001C04C, .pme_short_desc = "The processor's data cache was reloaded from the local chip's L4 cache due to a demand load", .pme_long_desc = "The processor's data cache was reloaded from the local chip's L4 cache due to a demand load", }, [ POWER9_PME_PM_DATA_FROM_LMEM ] = { .pme_name = "PM_DATA_FROM_LMEM", .pme_code = 0x000002C048, .pme_short_desc = "The processor's data cache was reloaded from the local chip's Memory due to a demand load", .pme_long_desc = "The processor's data cache was reloaded from the local chip's Memory due to a demand load", }, [ POWER9_PME_PM_DATA_FROM_MEMORY ] = { .pme_name = "PM_DATA_FROM_MEMORY", .pme_code = 0x00000400FE, .pme_short_desc = "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a demand load", .pme_long_desc = "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a demand load", }, [ POWER9_PME_PM_DATA_FROM_OFF_CHIP_CACHE ] = { .pme_name = "PM_DATA_FROM_OFF_CHIP_CACHE", .pme_code = 0x000004C04A, .pme_short_desc = "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a demand load", .pme_long_desc = "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a demand load", }, [ POWER9_PME_PM_DATA_FROM_ON_CHIP_CACHE ] = { .pme_name = "PM_DATA_FROM_ON_CHIP_CACHE", .pme_code = 0x000001C048, .pme_short_desc = "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to a demand load", .pme_long_desc = "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to a demand load", }, [ POWER9_PME_PM_DATA_FROM_RL2L3_MOD ] = { .pme_name = "PM_DATA_FROM_RL2L3_MOD", .pme_code = 0x000002C046, .pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a demand load", .pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a demand load", }, [ POWER9_PME_PM_DATA_FROM_RL2L3_SHR ] = { .pme_name = "PM_DATA_FROM_RL2L3_SHR", .pme_code = 0x000001C04A, .pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a demand load", .pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a demand load", }, [ POWER9_PME_PM_DATA_FROM_RL4 ] = { .pme_name = "PM_DATA_FROM_RL4", .pme_code = 0x000002C04A, .pme_short_desc = "The processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to a demand load", .pme_long_desc = "The processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to a demand load", }, [ POWER9_PME_PM_DATA_FROM_RMEM ] = { .pme_name = "PM_DATA_FROM_RMEM", .pme_code = 0x000003C04A, .pme_short_desc = "The processor's data cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to a demand load", .pme_long_desc = "The processor's data cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to a demand load", }, [ POWER9_PME_PM_DATA_GRP_PUMP_CPRED ] = { .pme_name = "PM_DATA_GRP_PUMP_CPRED", .pme_code = 0x000002C050, .pme_short_desc = "Initial and Final Pump Scope was group pump (prediction=correct) for a demand load", .pme_long_desc = "Initial and Final Pump Scope was group pump (prediction=correct) for a demand load", }, [ POWER9_PME_PM_DATA_GRP_PUMP_MPRED_RTY ] = { .pme_name = "PM_DATA_GRP_PUMP_MPRED_RTY", .pme_code = 0x000001C052, .pme_short_desc = "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for a demand load", .pme_long_desc = "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for a demand load", }, [ POWER9_PME_PM_DATA_GRP_PUMP_MPRED ] = { .pme_name = "PM_DATA_GRP_PUMP_MPRED", .pme_code = 0x000002C052, .pme_short_desc = "Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for a demand load", .pme_long_desc = "Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for a demand load", }, [ POWER9_PME_PM_DATA_PUMP_CPRED ] = { .pme_name = "PM_DATA_PUMP_CPRED", .pme_code = 0x000001C054, .pme_short_desc = "Pump prediction correct.", .pme_long_desc = "Pump prediction correct. Counts across all types of pumps for a demand load", }, [ POWER9_PME_PM_DATA_PUMP_MPRED ] = { .pme_name = "PM_DATA_PUMP_MPRED", .pme_code = 0x000004C052, .pme_short_desc = "Pump misprediction.", .pme_long_desc = "Pump misprediction. Counts across all types of pumps for a demand load", }, [ POWER9_PME_PM_DATA_STORE ] = { .pme_name = "PM_DATA_STORE", .pme_code = 0x000000F0A0, .pme_short_desc = "All ops that drain from s2q to L2 containing data", .pme_long_desc = "All ops that drain from s2q to L2 containing data", }, [ POWER9_PME_PM_DATA_SYS_PUMP_CPRED ] = { .pme_name = "PM_DATA_SYS_PUMP_CPRED", .pme_code = 0x000003C050, .pme_short_desc = "Initial and Final Pump Scope was system pump (prediction=correct) for a demand load", .pme_long_desc = "Initial and Final Pump Scope was system pump (prediction=correct) for a demand load", }, [ POWER9_PME_PM_DATA_SYS_PUMP_MPRED_RTY ] = { .pme_name = "PM_DATA_SYS_PUMP_MPRED_RTY", .pme_code = 0x000004C050, .pme_short_desc = "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for a demand load", .pme_long_desc = "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for a demand load", }, [ POWER9_PME_PM_DATA_SYS_PUMP_MPRED ] = { .pme_name = "PM_DATA_SYS_PUMP_MPRED", .pme_code = 0x000003C052, .pme_short_desc = "Final Pump Scope (system) mispredicted.", .pme_long_desc = "Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for a demand load", }, [ POWER9_PME_PM_DATA_TABLEWALK_CYC ] = { .pme_name = "PM_DATA_TABLEWALK_CYC", .pme_code = 0x000003001A, .pme_short_desc = "Data Tablewalk Cycles.", .pme_long_desc = "Data Tablewalk Cycles. Could be 1 or 2 active tablewalks. Includes data prefetches.", }, [ POWER9_PME_PM_DC_DEALLOC_NO_CONF ] = { .pme_name = "PM_DC_DEALLOC_NO_CONF", .pme_code = 0x000000F8AC, .pme_short_desc = "A demand load referenced a line in an active fuzzy prefetch stream.", .pme_long_desc = "A demand load referenced a line in an active fuzzy prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software.Fuzzy stream confirm (out of order effects, or pf cant keep up)", }, [ POWER9_PME_PM_DC_PREF_CONF ] = { .pme_name = "PM_DC_PREF_CONF", .pme_code = 0x000000F0A8, .pme_short_desc = "A demand load referenced a line in an active prefetch stream.", .pme_long_desc = "A demand load referenced a line in an active prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software. Includes forwards and backwards streams", }, [ POWER9_PME_PM_DC_PREF_CONS_ALLOC ] = { .pme_name = "PM_DC_PREF_CONS_ALLOC", .pme_code = 0x000000F0B4, .pme_short_desc = "Prefetch stream allocated in the conservative phase by either the hardware prefetch mechanism or software prefetch", .pme_long_desc = "Prefetch stream allocated in the conservative phase by either the hardware prefetch mechanism or software prefetch", }, [ POWER9_PME_PM_DC_PREF_FUZZY_CONF ] = { .pme_name = "PM_DC_PREF_FUZZY_CONF", .pme_code = 0x000000F8A8, .pme_short_desc = "A demand load referenced a line in an active fuzzy prefetch stream.", .pme_long_desc = "A demand load referenced a line in an active fuzzy prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software.Fuzzy stream confirm (out of order effects, or pf cant keep up)", }, [ POWER9_PME_PM_DC_PREF_HW_ALLOC ] = { .pme_name = "PM_DC_PREF_HW_ALLOC", .pme_code = 0x000000F0A4, .pme_short_desc = "Prefetch stream allocated by the hardware prefetch mechanism", .pme_long_desc = "Prefetch stream allocated by the hardware prefetch mechanism", }, [ POWER9_PME_PM_DC_PREF_STRIDED_CONF ] = { .pme_name = "PM_DC_PREF_STRIDED_CONF", .pme_code = 0x000000F0AC, .pme_short_desc = "A demand load referenced a line in an active strided prefetch stream.", .pme_long_desc = "A demand load referenced a line in an active strided prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software.", }, [ POWER9_PME_PM_DC_PREF_SW_ALLOC ] = { .pme_name = "PM_DC_PREF_SW_ALLOC", .pme_code = 0x000000F8A4, .pme_short_desc = "Prefetch stream allocated by software prefetching", .pme_long_desc = "Prefetch stream allocated by software prefetching", }, [ POWER9_PME_PM_DC_PREF_XCONS_ALLOC ] = { .pme_name = "PM_DC_PREF_XCONS_ALLOC", .pme_code = 0x000000F8B4, .pme_short_desc = "Prefetch stream allocated in the Ultra conservative phase by either the hardware prefetch mechanism or software prefetch", .pme_long_desc = "Prefetch stream allocated in the Ultra conservative phase by either the hardware prefetch mechanism or software prefetch", }, [ POWER9_PME_PM_DECODE_FUSION_CONST_GEN ] = { .pme_name = "PM_DECODE_FUSION_CONST_GEN", .pme_code = 0x00000048B4, .pme_short_desc = "32-bit constant generation", .pme_long_desc = "32-bit constant generation", }, [ POWER9_PME_PM_DECODE_FUSION_EXT_ADD ] = { .pme_name = "PM_DECODE_FUSION_EXT_ADD", .pme_code = 0x0000005084, .pme_short_desc = "32-bit extended addition", .pme_long_desc = "32-bit extended addition", }, [ POWER9_PME_PM_DECODE_FUSION_LD_ST_DISP ] = { .pme_name = "PM_DECODE_FUSION_LD_ST_DISP", .pme_code = 0x00000048A8, .pme_short_desc = "32-bit displacement D-form and 16-bit displacement X-form", .pme_long_desc = "32-bit displacement D-form and 16-bit displacement X-form", }, [ POWER9_PME_PM_DECODE_FUSION_OP_PRESERV ] = { .pme_name = "PM_DECODE_FUSION_OP_PRESERV", .pme_code = 0x0000005088, .pme_short_desc = "Destructive op operand preservation", .pme_long_desc = "Destructive op operand preservation", }, [ POWER9_PME_PM_DECODE_HOLD_ICT_FULL ] = { .pme_name = "PM_DECODE_HOLD_ICT_FULL", .pme_code = 0x00000058A8, .pme_short_desc = "Counts the number of cycles in which the IFU was not able to decode and transmit one or more instructions because all itags were in use.", .pme_long_desc = "Counts the number of cycles in which the IFU was not able to decode and transmit one or more instructions because all itags were in use. This means the ICT is full for this thread", }, [ POWER9_PME_PM_DECODE_LANES_NOT_AVAIL ] = { .pme_name = "PM_DECODE_LANES_NOT_AVAIL", .pme_code = 0x0000005884, .pme_short_desc = "Decode has something to transmit but dispatch lanes are not available", .pme_long_desc = "Decode has something to transmit but dispatch lanes are not available", }, [ POWER9_PME_PM_DERAT_MISS_16G ] = { .pme_name = "PM_DERAT_MISS_16G", .pme_code = 0x000004C054, .pme_short_desc = "Data ERAT Miss (Data TLB Access) page size 16G", .pme_long_desc = "Data ERAT Miss (Data TLB Access) page size 16G", }, [ POWER9_PME_PM_DERAT_MISS_16M ] = { .pme_name = "PM_DERAT_MISS_16M", .pme_code = 0x000003C054, .pme_short_desc = "Data ERAT Miss (Data TLB Access) page size 16M", .pme_long_desc = "Data ERAT Miss (Data TLB Access) page size 16M", }, [ POWER9_PME_PM_DERAT_MISS_1G ] = { .pme_name = "PM_DERAT_MISS_1G", .pme_code = 0x000002C05A, .pme_short_desc = "Data ERAT Miss (Data TLB Access) page size 1G.", .pme_long_desc = "Data ERAT Miss (Data TLB Access) page size 1G. Implies radix translation", }, [ POWER9_PME_PM_DERAT_MISS_2M ] = { .pme_name = "PM_DERAT_MISS_2M", .pme_code = 0x000001C05A, .pme_short_desc = "Data ERAT Miss (Data TLB Access) page size 2M.", .pme_long_desc = "Data ERAT Miss (Data TLB Access) page size 2M. Implies radix translation", }, [ POWER9_PME_PM_DERAT_MISS_4K ] = { .pme_name = "PM_DERAT_MISS_4K", .pme_code = 0x000001C056, .pme_short_desc = "Data ERAT Miss (Data TLB Access) page size 4K", .pme_long_desc = "Data ERAT Miss (Data TLB Access) page size 4K", }, [ POWER9_PME_PM_DERAT_MISS_64K ] = { .pme_name = "PM_DERAT_MISS_64K", .pme_code = 0x000002C054, .pme_short_desc = "Data ERAT Miss (Data TLB Access) page size 64K", .pme_long_desc = "Data ERAT Miss (Data TLB Access) page size 64K", }, [ POWER9_PME_PM_DFU_BUSY ] = { .pme_name = "PM_DFU_BUSY", .pme_code = 0x000004D04C, .pme_short_desc = "Cycles in which all 4 Decimal Floating Point units are busy.", .pme_long_desc = "Cycles in which all 4 Decimal Floating Point units are busy. The DFU is running at capacity", }, [ POWER9_PME_PM_DISP_CLB_HELD_BAL ] = { .pme_name = "PM_DISP_CLB_HELD_BAL", .pme_code = 0x000000288C, .pme_short_desc = "Dispatch/CLB Hold: Balance Flush", .pme_long_desc = "Dispatch/CLB Hold: Balance Flush", }, [ POWER9_PME_PM_DISP_CLB_HELD_SB ] = { .pme_name = "PM_DISP_CLB_HELD_SB", .pme_code = 0x0000002090, .pme_short_desc = "Dispatch/CLB Hold: Scoreboard", .pme_long_desc = "Dispatch/CLB Hold: Scoreboard", }, [ POWER9_PME_PM_DISP_CLB_HELD_TLBIE ] = { .pme_name = "PM_DISP_CLB_HELD_TLBIE", .pme_code = 0x0000002890, .pme_short_desc = "Dispatch Hold: Due to TLBIE", .pme_long_desc = "Dispatch Hold: Due to TLBIE", }, [ POWER9_PME_PM_DISP_HELD_HB_FULL ] = { .pme_name = "PM_DISP_HELD_HB_FULL", .pme_code = 0x000003D05C, .pme_short_desc = "Dispatch held due to History Buffer full.", .pme_long_desc = "Dispatch held due to History Buffer full. Could be GPR/VSR/VMR/FPR/CR/XVF; CR; XVF (XER/VSCR/FPSCR)", }, [ POWER9_PME_PM_DISP_HELD_ISSQ_FULL ] = { .pme_name = "PM_DISP_HELD_ISSQ_FULL", .pme_code = 0x0000020006, .pme_short_desc = "Dispatch held due to Issue q full.", .pme_long_desc = "Dispatch held due to Issue q full. Includes issue queue and branch queue", }, [ POWER9_PME_PM_DISP_HELD_SYNC_HOLD ] = { .pme_name = "PM_DISP_HELD_SYNC_HOLD", .pme_code = 0x000004003C, .pme_short_desc = "Cycles in which dispatch is held because of a synchronizing instruction in the pipeline", .pme_long_desc = "Cycles in which dispatch is held because of a synchronizing instruction in the pipeline", }, [ POWER9_PME_PM_DISP_HELD_TBEGIN ] = { .pme_name = "PM_DISP_HELD_TBEGIN", .pme_code = 0x00000028B0, .pme_short_desc = "This outer tbegin transaction cannot be dispatched until the previous tend instruction completes", .pme_long_desc = "This outer tbegin transaction cannot be dispatched until the previous tend instruction completes", }, [ POWER9_PME_PM_DISP_HELD ] = { .pme_name = "PM_DISP_HELD", .pme_code = 0x0000010006, .pme_short_desc = "Dispatch Held", .pme_long_desc = "Dispatch Held", }, [ POWER9_PME_PM_DISP_STARVED ] = { .pme_name = "PM_DISP_STARVED", .pme_code = 0x0000030008, .pme_short_desc = "Dispatched Starved", .pme_long_desc = "Dispatched Starved", }, [ POWER9_PME_PM_DP_QP_FLOP_CMPL ] = { .pme_name = "PM_DP_QP_FLOP_CMPL", .pme_code = 0x000004D05C, .pme_short_desc = "Double-Precion or Quad-Precision instruction completed", .pme_long_desc = "Double-Precion or Quad-Precision instruction completed", }, [ POWER9_PME_PM_DPTEG_FROM_DL2L3_MOD ] = { .pme_name = "PM_DPTEG_FROM_DL2L3_MOD", .pme_code = 0x000004E048, .pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request.", .pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", }, [ POWER9_PME_PM_DPTEG_FROM_DL2L3_SHR ] = { .pme_name = "PM_DPTEG_FROM_DL2L3_SHR", .pme_code = 0x000003E048, .pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request.", .pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", }, [ POWER9_PME_PM_DPTEG_FROM_DL4 ] = { .pme_name = "PM_DPTEG_FROM_DL4", .pme_code = 0x000003E04C, .pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a data side request.", .pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", }, [ POWER9_PME_PM_DPTEG_FROM_DMEM ] = { .pme_name = "PM_DPTEG_FROM_DMEM", .pme_code = 0x000004E04C, .pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a data side request.", .pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", }, [ POWER9_PME_PM_DPTEG_FROM_L21_MOD ] = { .pme_name = "PM_DPTEG_FROM_L21_MOD", .pme_code = 0x000004E046, .pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a data side request.", .pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", }, [ POWER9_PME_PM_DPTEG_FROM_L21_SHR ] = { .pme_name = "PM_DPTEG_FROM_L21_SHR", .pme_code = 0x000003E046, .pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a data side request.", .pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", }, [ POWER9_PME_PM_DPTEG_FROM_L2_MEPF ] = { .pme_name = "PM_DPTEG_FROM_L2_MEPF", .pme_code = 0x000002E040, .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state.", .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", }, [ POWER9_PME_PM_DPTEG_FROM_L2MISS ] = { .pme_name = "PM_DPTEG_FROM_L2MISS", .pme_code = 0x000001E04E, .pme_short_desc = "A Page Table Entry was loaded into the TLB from a location other than the local core's L2 due to a data side request.", .pme_long_desc = "A Page Table Entry was loaded into the TLB from a location other than the local core's L2 due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", }, [ POWER9_PME_PM_DPTEG_FROM_L2_NO_CONFLICT ] = { .pme_name = "PM_DPTEG_FROM_L2_NO_CONFLICT", .pme_code = 0x000001E040, .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a data side request.", .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", }, [ POWER9_PME_PM_DPTEG_FROM_L2 ] = { .pme_name = "PM_DPTEG_FROM_L2", .pme_code = 0x000001E042, .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 due to a data side request.", .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", }, [ POWER9_PME_PM_DPTEG_FROM_L31_ECO_MOD ] = { .pme_name = "PM_DPTEG_FROM_L31_ECO_MOD", .pme_code = 0x000004E044, .pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a data side request.", .pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", }, [ POWER9_PME_PM_DPTEG_FROM_L31_ECO_SHR ] = { .pme_name = "PM_DPTEG_FROM_L31_ECO_SHR", .pme_code = 0x000003E044, .pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a data side request.", .pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", }, [ POWER9_PME_PM_DPTEG_FROM_L31_MOD ] = { .pme_name = "PM_DPTEG_FROM_L31_MOD", .pme_code = 0x000002E044, .pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a data side request.", .pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", }, [ POWER9_PME_PM_DPTEG_FROM_L31_SHR ] = { .pme_name = "PM_DPTEG_FROM_L31_SHR", .pme_code = 0x000001E046, .pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a data side request.", .pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", }, [ POWER9_PME_PM_DPTEG_FROM_L3_DISP_CONFLICT ] = { .pme_name = "PM_DPTEG_FROM_L3_DISP_CONFLICT", .pme_code = 0x000003E042, .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a data side request.", .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", }, [ POWER9_PME_PM_DPTEG_FROM_L3_MEPF ] = { .pme_name = "PM_DPTEG_FROM_L3_MEPF", .pme_code = 0x000002E042, .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state.", .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", }, [ POWER9_PME_PM_DPTEG_FROM_L3MISS ] = { .pme_name = "PM_DPTEG_FROM_L3MISS", .pme_code = 0x000004E04E, .pme_short_desc = "A Page Table Entry was loaded into the TLB from a location other than the local core's L3 due to a data side request.", .pme_long_desc = "A Page Table Entry was loaded into the TLB from a location other than the local core's L3 due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", }, [ POWER9_PME_PM_DPTEG_FROM_L3_NO_CONFLICT ] = { .pme_name = "PM_DPTEG_FROM_L3_NO_CONFLICT", .pme_code = 0x000001E044, .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a data side request.", .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", }, [ POWER9_PME_PM_DPTEG_FROM_L3 ] = { .pme_name = "PM_DPTEG_FROM_L3", .pme_code = 0x000004E042, .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 due to a data side request.", .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", }, [ POWER9_PME_PM_DPTEG_FROM_LL4 ] = { .pme_name = "PM_DPTEG_FROM_LL4", .pme_code = 0x000001E04C, .pme_short_desc = "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a data side request.", .pme_long_desc = "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", }, [ POWER9_PME_PM_DPTEG_FROM_LMEM ] = { .pme_name = "PM_DPTEG_FROM_LMEM", .pme_code = 0x000002E048, .pme_short_desc = "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a data side request.", .pme_long_desc = "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", }, [ POWER9_PME_PM_DPTEG_FROM_MEMORY ] = { .pme_name = "PM_DPTEG_FROM_MEMORY", .pme_code = 0x000002E04C, .pme_short_desc = "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a data side request.", .pme_long_desc = "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", }, [ POWER9_PME_PM_DPTEG_FROM_OFF_CHIP_CACHE ] = { .pme_name = "PM_DPTEG_FROM_OFF_CHIP_CACHE", .pme_code = 0x000004E04A, .pme_short_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a data side request.", .pme_long_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", }, [ POWER9_PME_PM_DPTEG_FROM_ON_CHIP_CACHE ] = { .pme_name = "PM_DPTEG_FROM_ON_CHIP_CACHE", .pme_code = 0x000001E048, .pme_short_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a data side request.", .pme_long_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", }, [ POWER9_PME_PM_DPTEG_FROM_RL2L3_MOD ] = { .pme_name = "PM_DPTEG_FROM_RL2L3_MOD", .pme_code = 0x000002E046, .pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a data side request.", .pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", }, [ POWER9_PME_PM_DPTEG_FROM_RL2L3_SHR ] = { .pme_name = "PM_DPTEG_FROM_RL2L3_SHR", .pme_code = 0x000001E04A, .pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a data side request.", .pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", }, [ POWER9_PME_PM_DPTEG_FROM_RL4 ] = { .pme_name = "PM_DPTEG_FROM_RL4", .pme_code = 0x000002E04A, .pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a data side request.", .pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", }, [ POWER9_PME_PM_DPTEG_FROM_RMEM ] = { .pme_name = "PM_DPTEG_FROM_RMEM", .pme_code = 0x000003E04A, .pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a data side request.", .pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", }, [ POWER9_PME_PM_DSIDE_L2MEMACC ] = { .pme_name = "PM_DSIDE_L2MEMACC", .pme_code = 0x0000036092, .pme_short_desc = "Valid when first beat of data comes in for an D-side fetch where data came EXCLUSIVELY from memory (excluding hpcread64 accesses), i.", .pme_long_desc = "Valid when first beat of data comes in for an D-side fetch where data came EXCLUSIVELY from memory (excluding hpcread64 accesses), i.e., total memory accesses by RCs", }, [ POWER9_PME_PM_DSIDE_MRU_TOUCH ] = { .pme_name = "PM_DSIDE_MRU_TOUCH", .pme_code = 0x0000026884, .pme_short_desc = "D-side L2 MRU touch sent to L2", .pme_long_desc = "D-side L2 MRU touch sent to L2", }, [ POWER9_PME_PM_DSIDE_OTHER_64B_L2MEMACC ] = { .pme_name = "PM_DSIDE_OTHER_64B_L2MEMACC", .pme_code = 0x0000036892, .pme_short_desc = "Valid when first beat of data comes in for an D-side fetch where data came EXCLUSIVELY from memory that was for hpc_read64, (RC had to fetch other 64B of a line from MC) i.", .pme_long_desc = "Valid when first beat of data comes in for an D-side fetch where data came EXCLUSIVELY from memory that was for hpc_read64, (RC had to fetch other 64B of a line from MC) i.e., number of times RC had to go to memory to get 'missing' 64B", }, [ POWER9_PME_PM_DSLB_MISS ] = { .pme_name = "PM_DSLB_MISS", .pme_code = 0x000000D0A8, .pme_short_desc = "Data SLB Miss - Total of all segment sizes", .pme_long_desc = "Data SLB Miss - Total of all segment sizes", }, [ POWER9_PME_PM_DSLB_MISS_ALT ] = { .pme_name = "PM_DSLB_MISS_ALT", .pme_code = 0x0000010016, .pme_short_desc = "gate_and(sd_pc_c0_comp_valid AND sd_pc_c0_comp_thread(0:1)=tid,sd_pc_c0_comp_ppc_count(0:3)) + gate_and(sd_pc_c1_comp_valid AND sd_pc_c1_comp_thread(0:1)=tid,sd_pc_c1_comp_ppc_count(0:3))", .pme_long_desc = "gate_and(sd_pc_c0_comp_valid AND sd_pc_c0_comp_thread(0:1)=tid,sd_pc_c0_comp_ppc_count(0:3)) + gate_and(sd_pc_c1_comp_valid AND sd_pc_c1_comp_thread(0:1)=tid,sd_pc_c1_comp_ppc_count(0:3))", }, [ POWER9_PME_PM_DTLB_MISS_16G ] = { .pme_name = "PM_DTLB_MISS_16G", .pme_code = 0x000001C058, .pme_short_desc = "Data TLB Miss page size 16G", .pme_long_desc = "Data TLB Miss page size 16G", }, [ POWER9_PME_PM_DTLB_MISS_16M ] = { .pme_name = "PM_DTLB_MISS_16M", .pme_code = 0x000004C056, .pme_short_desc = "Data TLB Miss page size 16M", .pme_long_desc = "Data TLB Miss page size 16M", }, [ POWER9_PME_PM_DTLB_MISS_1G ] = { .pme_name = "PM_DTLB_MISS_1G", .pme_code = 0x000004C05A, .pme_short_desc = "Data TLB reload (after a miss) page size 1G.", .pme_long_desc = "Data TLB reload (after a miss) page size 1G. Implies radix translation was used", }, [ POWER9_PME_PM_DTLB_MISS_2M ] = { .pme_name = "PM_DTLB_MISS_2M", .pme_code = 0x000001C05C, .pme_short_desc = "Data TLB reload (after a miss) page size 2M.", .pme_long_desc = "Data TLB reload (after a miss) page size 2M. Implies radix translation was used", }, [ POWER9_PME_PM_DTLB_MISS_4K ] = { .pme_name = "PM_DTLB_MISS_4K", .pme_code = 0x000002C056, .pme_short_desc = "Data TLB Miss page size 4k", .pme_long_desc = "Data TLB Miss page size 4k", }, [ POWER9_PME_PM_DTLB_MISS_64K ] = { .pme_name = "PM_DTLB_MISS_64K", .pme_code = 0x000003C056, .pme_short_desc = "Data TLB Miss page size 64K", .pme_long_desc = "Data TLB Miss page size 64K", }, [ POWER9_PME_PM_DTLB_MISS ] = { .pme_name = "PM_DTLB_MISS", .pme_code = 0x00000300FC, .pme_short_desc = "Data PTEG reload", .pme_long_desc = "Data PTEG reload", }, [ POWER9_PME_PM_SPACEHOLDER_0000040062 ] = { .pme_name = "PM_SPACEHOLDER_0000040062", .pme_code = 0x0000040062, .pme_short_desc = "SPACE_HOLDER for event 0000040062", .pme_long_desc = "SPACE_HOLDER for event 0000040062", }, [ POWER9_PME_PM_SPACEHOLDER_0000040064 ] = { .pme_name = "PM_SPACEHOLDER_0000040064", .pme_code = 0x0000040064, .pme_short_desc = "SPACE_HOLDER for event 0000040064", .pme_long_desc = "SPACE_HOLDER for event 0000040064", }, [ POWER9_PME_PM_EAT_FORCE_MISPRED ] = { .pme_name = "PM_EAT_FORCE_MISPRED", .pme_code = 0x00000050A8, .pme_short_desc = "XL-form branch was mispredicted due to the predicted target address missing from EAT.", .pme_long_desc = "XL-form branch was mispredicted due to the predicted target address missing from EAT. The EAT forces a mispredict in this case since there is no predicated target to validate. This is a rare case that may occur when the EAT is full and a branch is issued", }, [ POWER9_PME_PM_EAT_FULL_CYC ] = { .pme_name = "PM_EAT_FULL_CYC", .pme_code = 0x0000004084, .pme_short_desc = "Cycles No room in EAT", .pme_long_desc = "Cycles No room in EAT", }, [ POWER9_PME_PM_EE_OFF_EXT_INT ] = { .pme_name = "PM_EE_OFF_EXT_INT", .pme_code = 0x0000002080, .pme_short_desc = "CyclesMSR[EE] is off and external interrupts are active", .pme_long_desc = "CyclesMSR[EE] is off and external interrupts are active", }, [ POWER9_PME_PM_EXT_INT ] = { .pme_name = "PM_EXT_INT", .pme_code = 0x00000200F8, .pme_short_desc = "external interrupt", .pme_long_desc = "external interrupt", }, [ POWER9_PME_PM_FLOP_CMPL ] = { .pme_name = "PM_FLOP_CMPL", .pme_code = 0x000004505E, .pme_short_desc = "Floating Point Operation Finished", .pme_long_desc = "Floating Point Operation Finished", }, [ POWER9_PME_PM_FLUSH_COMPLETION ] = { .pme_name = "PM_FLUSH_COMPLETION", .pme_code = 0x0000030012, .pme_short_desc = "The instruction that was next to complete did not complete because it suffered a flush", .pme_long_desc = "The instruction that was next to complete did not complete because it suffered a flush", }, [ POWER9_PME_PM_FLUSH_DISP_SB ] = { .pme_name = "PM_FLUSH_DISP_SB", .pme_code = 0x0000002088, .pme_short_desc = "Dispatch Flush: Scoreboard", .pme_long_desc = "Dispatch Flush: Scoreboard", }, [ POWER9_PME_PM_FLUSH_DISP_TLBIE ] = { .pme_name = "PM_FLUSH_DISP_TLBIE", .pme_code = 0x0000002888, .pme_short_desc = "Dispatch Flush: TLBIE", .pme_long_desc = "Dispatch Flush: TLBIE", }, [ POWER9_PME_PM_FLUSH_DISP ] = { .pme_name = "PM_FLUSH_DISP", .pme_code = 0x0000002880, .pme_short_desc = "Dispatch flush", .pme_long_desc = "Dispatch flush", }, [ POWER9_PME_PM_FLUSH_HB_RESTORE_CYC ] = { .pme_name = "PM_FLUSH_HB_RESTORE_CYC", .pme_code = 0x0000002084, .pme_short_desc = "Cycles in which no new instructions can be dispatched to the ICT after a flush.", .pme_long_desc = "Cycles in which no new instructions can be dispatched to the ICT after a flush. History buffer recovery", }, [ POWER9_PME_PM_FLUSH_LSU ] = { .pme_name = "PM_FLUSH_LSU", .pme_code = 0x00000058A4, .pme_short_desc = "LSU flushes.", .pme_long_desc = "LSU flushes. Includes all lsu flushes", }, [ POWER9_PME_PM_FLUSH_MPRED ] = { .pme_name = "PM_FLUSH_MPRED", .pme_code = 0x00000050A4, .pme_short_desc = "Branch mispredict flushes.", .pme_long_desc = "Branch mispredict flushes. Includes target and address misprecition", }, [ POWER9_PME_PM_FLUSH ] = { .pme_name = "PM_FLUSH", .pme_code = 0x00000400F8, .pme_short_desc = "Flush (any type)", .pme_long_desc = "Flush (any type)", }, [ POWER9_PME_PM_FMA_CMPL ] = { .pme_name = "PM_FMA_CMPL", .pme_code = 0x0000045054, .pme_short_desc = "two flops operation completed (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only.", .pme_long_desc = "two flops operation completed (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only. ", }, [ POWER9_PME_PM_FORCED_NOP ] = { .pme_name = "PM_FORCED_NOP", .pme_code = 0x000000509C, .pme_short_desc = "Instruction was forced to execute as a nop because it was found to behave like a nop (have no effect) at decode time", .pme_long_desc = "Instruction was forced to execute as a nop because it was found to behave like a nop (have no effect) at decode time", }, [ POWER9_PME_PM_FREQ_DOWN ] = { .pme_name = "PM_FREQ_DOWN", .pme_code = 0x000003000C, .pme_short_desc = "Power Management: Below Threshold B", .pme_long_desc = "Power Management: Below Threshold B", }, [ POWER9_PME_PM_FREQ_UP ] = { .pme_name = "PM_FREQ_UP", .pme_code = 0x000004000C, .pme_short_desc = "Power Management: Above Threshold A", .pme_long_desc = "Power Management: Above Threshold A", }, [ POWER9_PME_PM_FXU_1PLUS_BUSY ] = { .pme_name = "PM_FXU_1PLUS_BUSY", .pme_code = 0x000003000E, .pme_short_desc = "At least one of the 4 FXU units is busy", .pme_long_desc = "At least one of the 4 FXU units is busy", }, [ POWER9_PME_PM_FXU_BUSY ] = { .pme_name = "PM_FXU_BUSY", .pme_code = 0x000002000E, .pme_short_desc = "Cycles in which all 4 FXUs are busy.", .pme_long_desc = "Cycles in which all 4 FXUs are busy. The FXU is running at capacity", }, [ POWER9_PME_PM_FXU_FIN ] = { .pme_name = "PM_FXU_FIN", .pme_code = 0x0000040004, .pme_short_desc = "The fixed point unit Unit finished an instruction.", .pme_long_desc = "The fixed point unit Unit finished an instruction. Instructions that finish may not necessary complete.", }, [ POWER9_PME_PM_FXU_IDLE ] = { .pme_name = "PM_FXU_IDLE", .pme_code = 0x0000024052, .pme_short_desc = "Cycles in which FXU0, FXU1, FXU2, and FXU3 are all idle", .pme_long_desc = "Cycles in which FXU0, FXU1, FXU2, and FXU3 are all idle", }, [ POWER9_PME_PM_GRP_PUMP_CPRED ] = { .pme_name = "PM_GRP_PUMP_CPRED", .pme_code = 0x0000020050, .pme_short_desc = "Initial and Final Pump Scope and data sourced across this scope was group pump for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)", .pme_long_desc = "Initial and Final Pump Scope and data sourced across this scope was group pump for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)", }, [ POWER9_PME_PM_GRP_PUMP_MPRED_RTY ] = { .pme_name = "PM_GRP_PUMP_MPRED_RTY", .pme_code = 0x0000010052, .pme_short_desc = "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)", .pme_long_desc = "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)", }, [ POWER9_PME_PM_GRP_PUMP_MPRED ] = { .pme_name = "PM_GRP_PUMP_MPRED", .pme_code = 0x0000020052, .pme_short_desc = "Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)", .pme_long_desc = "Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)", }, [ POWER9_PME_PM_HV_CYC ] = { .pme_name = "PM_HV_CYC", .pme_code = 0x000002000A, .pme_short_desc = "Cycles in which msr_hv is high.", .pme_long_desc = "Cycles in which msr_hv is high. Note that this event does not take msr_pr into consideration", }, [ POWER9_PME_PM_HWSYNC ] = { .pme_name = "PM_HWSYNC", .pme_code = 0x00000050A0, .pme_short_desc = "Hwsync instruction decoded and transferred", .pme_long_desc = "Hwsync instruction decoded and transferred", }, [ POWER9_PME_PM_IBUF_FULL_CYC ] = { .pme_name = "PM_IBUF_FULL_CYC", .pme_code = 0x0000004884, .pme_short_desc = "Cycles No room in ibuff", .pme_long_desc = "Cycles No room in ibuff", }, [ POWER9_PME_PM_IC_DEMAND_CYC ] = { .pme_name = "PM_IC_DEMAND_CYC", .pme_code = 0x0000010018, .pme_short_desc = "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for a demand load", .pme_long_desc = "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for a demand load", }, [ POWER9_PME_PM_IC_DEMAND_L2_BHT_REDIRECT ] = { .pme_name = "PM_IC_DEMAND_L2_BHT_REDIRECT", .pme_code = 0x0000004098, .pme_short_desc = "L2 I cache demand request due to BHT redirect, branch redirect ( 2 bubbles 3 cycles)", .pme_long_desc = "L2 I cache demand request due to BHT redirect, branch redirect ( 2 bubbles 3 cycles)", }, [ POWER9_PME_PM_IC_DEMAND_L2_BR_REDIRECT ] = { .pme_name = "PM_IC_DEMAND_L2_BR_REDIRECT", .pme_code = 0x0000004898, .pme_short_desc = "L2 I cache demand request due to branch Mispredict ( 15 cycle path)", .pme_long_desc = "L2 I cache demand request due to branch Mispredict ( 15 cycle path)", }, [ POWER9_PME_PM_IC_DEMAND_REQ ] = { .pme_name = "PM_IC_DEMAND_REQ", .pme_code = 0x0000004088, .pme_short_desc = "Demand Instruction fetch request", .pme_long_desc = "Demand Instruction fetch request", }, [ POWER9_PME_PM_IC_INVALIDATE ] = { .pme_name = "PM_IC_INVALIDATE", .pme_code = 0x0000005888, .pme_short_desc = "Ic line invalidated", .pme_long_desc = "Ic line invalidated", }, [ POWER9_PME_PM_IC_MISS_CMPL ] = { .pme_name = "PM_IC_MISS_CMPL", .pme_code = 0x0000045058, .pme_short_desc = "Non-speculative icache miss, counted at completion", .pme_long_desc = "Non-speculative icache miss, counted at completion", }, [ POWER9_PME_PM_IC_MISS_ICBI ] = { .pme_name = "PM_IC_MISS_ICBI", .pme_code = 0x0000005094, .pme_short_desc = "threaded version, IC Misses where we got EA dir hit but no sector valids were on.", .pme_long_desc = "threaded version, IC Misses where we got EA dir hit but no sector valids were on. ICBI took line out", }, [ POWER9_PME_PM_IC_PREF_CANCEL_HIT ] = { .pme_name = "PM_IC_PREF_CANCEL_HIT", .pme_code = 0x0000004890, .pme_short_desc = "Prefetch Canceled due to icache hit", .pme_long_desc = "Prefetch Canceled due to icache hit", }, [ POWER9_PME_PM_IC_PREF_CANCEL_L2 ] = { .pme_name = "PM_IC_PREF_CANCEL_L2", .pme_code = 0x0000004094, .pme_short_desc = "L2 Squashed a demand or prefetch request", .pme_long_desc = "L2 Squashed a demand or prefetch request", }, [ POWER9_PME_PM_IC_PREF_CANCEL_PAGE ] = { .pme_name = "PM_IC_PREF_CANCEL_PAGE", .pme_code = 0x0000004090, .pme_short_desc = "Prefetch Canceled due to page boundary", .pme_long_desc = "Prefetch Canceled due to page boundary", }, [ POWER9_PME_PM_IC_PREF_REQ ] = { .pme_name = "PM_IC_PREF_REQ", .pme_code = 0x0000004888, .pme_short_desc = "Instruction prefetch requests", .pme_long_desc = "Instruction prefetch requests", }, [ POWER9_PME_PM_IC_PREF_WRITE ] = { .pme_name = "PM_IC_PREF_WRITE", .pme_code = 0x000000488C, .pme_short_desc = "Instruction prefetch written into IL1", .pme_long_desc = "Instruction prefetch written into IL1", }, [ POWER9_PME_PM_IC_RELOAD_PRIVATE ] = { .pme_name = "PM_IC_RELOAD_PRIVATE", .pme_code = 0x0000004894, .pme_short_desc = "Reloading line was brought in private for a specific thread.", .pme_long_desc = "Reloading line was brought in private for a specific thread. Most lines are brought in shared for all eight threads. If RA does not match then invalidates and then brings it shared to other thread. In P7 line brought in private , then line was invalidat", }, [ POWER9_PME_PM_ICT_EMPTY_CYC ] = { .pme_name = "PM_ICT_EMPTY_CYC", .pme_code = 0x0000020008, .pme_short_desc = "Cycles in which the ICT is completely empty.", .pme_long_desc = "Cycles in which the ICT is completely empty. No itags are assigned to any thread", }, [ POWER9_PME_PM_ICT_NOSLOT_BR_MPRED_ICMISS ] = { .pme_name = "PM_ICT_NOSLOT_BR_MPRED_ICMISS", .pme_code = 0x0000034058, .pme_short_desc = "Ict empty for this thread due to Icache Miss and branch mispred", .pme_long_desc = "Ict empty for this thread due to Icache Miss and branch mispred", }, [ POWER9_PME_PM_ICT_NOSLOT_BR_MPRED ] = { .pme_name = "PM_ICT_NOSLOT_BR_MPRED", .pme_code = 0x000004D01E, .pme_short_desc = "Ict empty for this thread due to branch mispred", .pme_long_desc = "Ict empty for this thread due to branch mispred", }, [ POWER9_PME_PM_ICT_NOSLOT_CYC ] = { .pme_name = "PM_ICT_NOSLOT_CYC", .pme_code = 0x00000100F8, .pme_short_desc = "Number of cycles the ICT has no itags assigned to this thread", .pme_long_desc = "Number of cycles the ICT has no itags assigned to this thread", }, [ POWER9_PME_PM_ICT_NOSLOT_DISP_HELD_HB_FULL ] = { .pme_name = "PM_ICT_NOSLOT_DISP_HELD_HB_FULL", .pme_code = 0x0000030018, .pme_short_desc = "Ict empty for this thread due to dispatch holds because the History Buffer was full.", .pme_long_desc = "Ict empty for this thread due to dispatch holds because the History Buffer was full. Could be GPR/VSR/VMR/FPR/CR/XVF; CR; XVF (XER/VSCR/FPSCR)", }, [ POWER9_PME_PM_ICT_NOSLOT_DISP_HELD_ISSQ ] = { .pme_name = "PM_ICT_NOSLOT_DISP_HELD_ISSQ", .pme_code = 0x000002D01E, .pme_short_desc = "Ict empty for this thread due to dispatch hold on this thread due to Issue q full, BRQ full, XVCF Full, Count cache, Link, Tar full", .pme_long_desc = "Ict empty for this thread due to dispatch hold on this thread due to Issue q full, BRQ full, XVCF Full, Count cache, Link, Tar full", }, [ POWER9_PME_PM_ICT_NOSLOT_DISP_HELD_SYNC ] = { .pme_name = "PM_ICT_NOSLOT_DISP_HELD_SYNC", .pme_code = 0x000004D01C, .pme_short_desc = "Dispatch held due to a synchronizing instruction at dispatch", .pme_long_desc = "Dispatch held due to a synchronizing instruction at dispatch", }, [ POWER9_PME_PM_ICT_NOSLOT_DISP_HELD_TBEGIN ] = { .pme_name = "PM_ICT_NOSLOT_DISP_HELD_TBEGIN", .pme_code = 0x0000010064, .pme_short_desc = "the NTC instruction is being held at dispatch because it is a tbegin instruction and there is an older tbegin in the pipeline that must complete before the younger tbegin can dispatch", .pme_long_desc = "the NTC instruction is being held at dispatch because it is a tbegin instruction and there is an older tbegin in the pipeline that must complete before the younger tbegin can dispatch", }, [ POWER9_PME_PM_ICT_NOSLOT_DISP_HELD ] = { .pme_name = "PM_ICT_NOSLOT_DISP_HELD", .pme_code = 0x000004E01A, .pme_short_desc = "Cycles in which the NTC instruction is held at dispatch for any reason", .pme_long_desc = "Cycles in which the NTC instruction is held at dispatch for any reason", }, [ POWER9_PME_PM_ICT_NOSLOT_IC_L3MISS ] = { .pme_name = "PM_ICT_NOSLOT_IC_L3MISS", .pme_code = 0x000004E010, .pme_short_desc = "Ict empty for this thread due to icache misses that were sourced from beyond the local L3.", .pme_long_desc = "Ict empty for this thread due to icache misses that were sourced from beyond the local L3. The source could be local/remote/distant memory or another core's cache", }, [ POWER9_PME_PM_ICT_NOSLOT_IC_L3 ] = { .pme_name = "PM_ICT_NOSLOT_IC_L3", .pme_code = 0x000003E052, .pme_short_desc = "Ict empty for this thread due to icache misses that were sourced from the local L3", .pme_long_desc = "Ict empty for this thread due to icache misses that were sourced from the local L3", }, [ POWER9_PME_PM_ICT_NOSLOT_IC_MISS ] = { .pme_name = "PM_ICT_NOSLOT_IC_MISS", .pme_code = 0x000002D01A, .pme_short_desc = "Ict empty for this thread due to Icache Miss", .pme_long_desc = "Ict empty for this thread due to Icache Miss", }, [ POWER9_PME_PM_IERAT_RELOAD_16M ] = { .pme_name = "PM_IERAT_RELOAD_16M", .pme_code = 0x000004006A, .pme_short_desc = "IERAT Reloaded (Miss) for a 16M page", .pme_long_desc = "IERAT Reloaded (Miss) for a 16M page", }, [ POWER9_PME_PM_IERAT_RELOAD_4K ] = { .pme_name = "PM_IERAT_RELOAD_4K", .pme_code = 0x0000020064, .pme_short_desc = "IERAT reloaded (after a miss) for 4K pages", .pme_long_desc = "IERAT reloaded (after a miss) for 4K pages", }, [ POWER9_PME_PM_IERAT_RELOAD_64K ] = { .pme_name = "PM_IERAT_RELOAD_64K", .pme_code = 0x000003006A, .pme_short_desc = "IERAT Reloaded (Miss) for a 64k page", .pme_long_desc = "IERAT Reloaded (Miss) for a 64k page", }, [ POWER9_PME_PM_IERAT_RELOAD ] = { .pme_name = "PM_IERAT_RELOAD", .pme_code = 0x00000100F6, .pme_short_desc = "Number of I-ERAT reloads", .pme_long_desc = "Number of I-ERAT reloads", }, [ POWER9_PME_PM_IFETCH_THROTTLE ] = { .pme_name = "PM_IFETCH_THROTTLE", .pme_code = 0x000003405E, .pme_short_desc = "Cycles in which Instruction fetch throttle was active.", .pme_long_desc = "Cycles in which Instruction fetch throttle was active.", }, [ POWER9_PME_PM_INST_CHIP_PUMP_CPRED ] = { .pme_name = "PM_INST_CHIP_PUMP_CPRED", .pme_code = 0x0000014050, .pme_short_desc = "Initial and Final Pump Scope was chip pump (prediction=correct) for an instruction fetch", .pme_long_desc = "Initial and Final Pump Scope was chip pump (prediction=correct) for an instruction fetch", }, /* See also alternate entries for 0000010002 / POWER9_PME_PM_INST_CMPL with code(s) 0000020002 0000030002 0000040002 at the bottom of this table. \n */ [ POWER9_PME_PM_INST_CMPL ] = { .pme_name = "PM_INST_CMPL", .pme_code = 0x0000010002, .pme_short_desc = "Number of PowerPC Instructions that completed.", .pme_long_desc = "Number of PowerPC Instructions that completed.", }, /* See also alternate entries for 00000200F2 / POWER9_PME_PM_INST_DISP with code(s) 00000300F2 at the bottom of this table. \n */ [ POWER9_PME_PM_INST_DISP ] = { .pme_name = "PM_INST_DISP", .pme_code = 0x00000200F2, .pme_short_desc = "# PPC Dispatched", .pme_long_desc = "# PPC Dispatched", }, [ POWER9_PME_PM_INST_FROM_DL2L3_MOD ] = { .pme_name = "PM_INST_FROM_DL2L3_MOD", .pme_code = 0x0000044048, .pme_short_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to an instruction fetch (not prefetch)", .pme_long_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to an instruction fetch (not prefetch)", }, [ POWER9_PME_PM_INST_FROM_DL2L3_SHR ] = { .pme_name = "PM_INST_FROM_DL2L3_SHR", .pme_code = 0x0000034048, .pme_short_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to an instruction fetch (not prefetch)", .pme_long_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to an instruction fetch (not prefetch)", }, [ POWER9_PME_PM_INST_FROM_DL4 ] = { .pme_name = "PM_INST_FROM_DL4", .pme_code = 0x000003404C, .pme_short_desc = "The processor's Instruction cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to an instruction fetch (not prefetch)", .pme_long_desc = "The processor's Instruction cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to an instruction fetch (not prefetch)", }, [ POWER9_PME_PM_INST_FROM_DMEM ] = { .pme_name = "PM_INST_FROM_DMEM", .pme_code = 0x000004404C, .pme_short_desc = "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group (Distant) due to an instruction fetch (not prefetch)", .pme_long_desc = "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group (Distant) due to an instruction fetch (not prefetch)", }, [ POWER9_PME_PM_INST_FROM_L1 ] = { .pme_name = "PM_INST_FROM_L1", .pme_code = 0x0000004080, .pme_short_desc = "Instruction fetches from L1.", .pme_long_desc = "Instruction fetches from L1. L1 instruction hit", }, [ POWER9_PME_PM_INST_FROM_L21_MOD ] = { .pme_name = "PM_INST_FROM_L21_MOD", .pme_code = 0x0000044046, .pme_short_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another core's L2 on the same chip due to an instruction fetch (not prefetch)", .pme_long_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another core's L2 on the same chip due to an instruction fetch (not prefetch)", }, [ POWER9_PME_PM_INST_FROM_L21_SHR ] = { .pme_name = "PM_INST_FROM_L21_SHR", .pme_code = 0x0000034046, .pme_short_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another core's L2 on the same chip due to an instruction fetch (not prefetch)", .pme_long_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another core's L2 on the same chip due to an instruction fetch (not prefetch)", }, [ POWER9_PME_PM_INST_FROM_L2_DISP_CONFLICT_LDHITST ] = { .pme_name = "PM_INST_FROM_L2_DISP_CONFLICT_LDHITST", .pme_code = 0x0000034040, .pme_short_desc = "The processor's Instruction cache was reloaded from local core's L2 with load hit store conflict due to an instruction fetch (not prefetch)", .pme_long_desc = "The processor's Instruction cache was reloaded from local core's L2 with load hit store conflict due to an instruction fetch (not prefetch)", }, [ POWER9_PME_PM_INST_FROM_L2_DISP_CONFLICT_OTHER ] = { .pme_name = "PM_INST_FROM_L2_DISP_CONFLICT_OTHER", .pme_code = 0x0000044040, .pme_short_desc = "The processor's Instruction cache was reloaded from local core's L2 with dispatch conflict due to an instruction fetch (not prefetch)", .pme_long_desc = "The processor's Instruction cache was reloaded from local core's L2 with dispatch conflict due to an instruction fetch (not prefetch)", }, [ POWER9_PME_PM_INST_FROM_L2_MEPF ] = { .pme_name = "PM_INST_FROM_L2_MEPF", .pme_code = 0x0000024040, .pme_short_desc = "The processor's Instruction cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state.", .pme_long_desc = "The processor's Instruction cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state. due to an instruction fetch (not prefetch)", }, [ POWER9_PME_PM_INST_FROM_L2MISS ] = { .pme_name = "PM_INST_FROM_L2MISS", .pme_code = 0x000001404E, .pme_short_desc = "The processor's Instruction cache was reloaded from a location other than the local core's L2 due to an instruction fetch (not prefetch)", .pme_long_desc = "The processor's Instruction cache was reloaded from a location other than the local core's L2 due to an instruction fetch (not prefetch)", }, [ POWER9_PME_PM_INST_FROM_L2_NO_CONFLICT ] = { .pme_name = "PM_INST_FROM_L2_NO_CONFLICT", .pme_code = 0x0000014040, .pme_short_desc = "The processor's Instruction cache was reloaded from local core's L2 without conflict due to an instruction fetch (not prefetch)", .pme_long_desc = "The processor's Instruction cache was reloaded from local core's L2 without conflict due to an instruction fetch (not prefetch)", }, [ POWER9_PME_PM_INST_FROM_L2 ] = { .pme_name = "PM_INST_FROM_L2", .pme_code = 0x0000014042, .pme_short_desc = "The processor's Instruction cache was reloaded from local core's L2 due to an instruction fetch (not prefetch)", .pme_long_desc = "The processor's Instruction cache was reloaded from local core's L2 due to an instruction fetch (not prefetch)", }, [ POWER9_PME_PM_INST_FROM_L31_ECO_MOD ] = { .pme_name = "PM_INST_FROM_L31_ECO_MOD", .pme_code = 0x0000044044, .pme_short_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to an instruction fetch (not prefetch)", .pme_long_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to an instruction fetch (not prefetch)", }, [ POWER9_PME_PM_INST_FROM_L31_ECO_SHR ] = { .pme_name = "PM_INST_FROM_L31_ECO_SHR", .pme_code = 0x0000034044, .pme_short_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to an instruction fetch (not prefetch)", .pme_long_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to an instruction fetch (not prefetch)", }, [ POWER9_PME_PM_INST_FROM_L31_MOD ] = { .pme_name = "PM_INST_FROM_L31_MOD", .pme_code = 0x0000024044, .pme_short_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another core's L3 on the same chip due to an instruction fetch (not prefetch)", .pme_long_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another core's L3 on the same chip due to an instruction fetch (not prefetch)", }, [ POWER9_PME_PM_INST_FROM_L31_SHR ] = { .pme_name = "PM_INST_FROM_L31_SHR", .pme_code = 0x0000014046, .pme_short_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another core's L3 on the same chip due to an instruction fetch (not prefetch)", .pme_long_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another core's L3 on the same chip due to an instruction fetch (not prefetch)", }, [ POWER9_PME_PM_INST_FROM_L3_DISP_CONFLICT ] = { .pme_name = "PM_INST_FROM_L3_DISP_CONFLICT", .pme_code = 0x0000034042, .pme_short_desc = "The processor's Instruction cache was reloaded from local core's L3 with dispatch conflict due to an instruction fetch (not prefetch)", .pme_long_desc = "The processor's Instruction cache was reloaded from local core's L3 with dispatch conflict due to an instruction fetch (not prefetch)", }, [ POWER9_PME_PM_INST_FROM_L3_MEPF ] = { .pme_name = "PM_INST_FROM_L3_MEPF", .pme_code = 0x0000024042, .pme_short_desc = "The processor's Instruction cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state.", .pme_long_desc = "The processor's Instruction cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to an instruction fetch (not prefetch)", }, [ POWER9_PME_PM_INST_FROM_L3MISS_MOD ] = { .pme_name = "PM_INST_FROM_L3MISS_MOD", .pme_code = 0x000004404E, .pme_short_desc = "The processor's Instruction cache was reloaded from a location other than the local core's L3 due to a instruction fetch", .pme_long_desc = "The processor's Instruction cache was reloaded from a location other than the local core's L3 due to a instruction fetch", }, [ POWER9_PME_PM_INST_FROM_L3MISS ] = { .pme_name = "PM_INST_FROM_L3MISS", .pme_code = 0x00000300FA, .pme_short_desc = "Marked instruction was reloaded from a location beyond the local chiplet", .pme_long_desc = "Marked instruction was reloaded from a location beyond the local chiplet", }, [ POWER9_PME_PM_INST_FROM_L3_NO_CONFLICT ] = { .pme_name = "PM_INST_FROM_L3_NO_CONFLICT", .pme_code = 0x0000014044, .pme_short_desc = "The processor's Instruction cache was reloaded from local core's L3 without conflict due to an instruction fetch (not prefetch)", .pme_long_desc = "The processor's Instruction cache was reloaded from local core's L3 without conflict due to an instruction fetch (not prefetch)", }, [ POWER9_PME_PM_INST_FROM_L3 ] = { .pme_name = "PM_INST_FROM_L3", .pme_code = 0x0000044042, .pme_short_desc = "The processor's Instruction cache was reloaded from local core's L3 due to an instruction fetch (not prefetch)", .pme_long_desc = "The processor's Instruction cache was reloaded from local core's L3 due to an instruction fetch (not prefetch)", }, [ POWER9_PME_PM_INST_FROM_LL4 ] = { .pme_name = "PM_INST_FROM_LL4", .pme_code = 0x000001404C, .pme_short_desc = "The processor's Instruction cache was reloaded from the local chip's L4 cache due to an instruction fetch (not prefetch)", .pme_long_desc = "The processor's Instruction cache was reloaded from the local chip's L4 cache due to an instruction fetch (not prefetch)", }, [ POWER9_PME_PM_INST_FROM_LMEM ] = { .pme_name = "PM_INST_FROM_LMEM", .pme_code = 0x0000024048, .pme_short_desc = "The processor's Instruction cache was reloaded from the local chip's Memory due to an instruction fetch (not prefetch)", .pme_long_desc = "The processor's Instruction cache was reloaded from the local chip's Memory due to an instruction fetch (not prefetch)", }, [ POWER9_PME_PM_INST_FROM_MEMORY ] = { .pme_name = "PM_INST_FROM_MEMORY", .pme_code = 0x000002404C, .pme_short_desc = "The processor's Instruction cache was reloaded from a memory location including L4 from local remote or distant due to an instruction fetch (not prefetch)", .pme_long_desc = "The processor's Instruction cache was reloaded from a memory location including L4 from local remote or distant due to an instruction fetch (not prefetch)", }, [ POWER9_PME_PM_INST_FROM_OFF_CHIP_CACHE ] = { .pme_name = "PM_INST_FROM_OFF_CHIP_CACHE", .pme_code = 0x000004404A, .pme_short_desc = "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to an instruction fetch (not prefetch)", .pme_long_desc = "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to an instruction fetch (not prefetch)", }, [ POWER9_PME_PM_INST_FROM_ON_CHIP_CACHE ] = { .pme_name = "PM_INST_FROM_ON_CHIP_CACHE", .pme_code = 0x0000014048, .pme_short_desc = "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to an instruction fetch (not prefetch)", .pme_long_desc = "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to an instruction fetch (not prefetch)", }, [ POWER9_PME_PM_INST_FROM_RL2L3_MOD ] = { .pme_name = "PM_INST_FROM_RL2L3_MOD", .pme_code = 0x0000024046, .pme_short_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction fetch (not prefetch)", .pme_long_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction fetch (not prefetch)", }, [ POWER9_PME_PM_INST_FROM_RL2L3_SHR ] = { .pme_name = "PM_INST_FROM_RL2L3_SHR", .pme_code = 0x000001404A, .pme_short_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction fetch (not prefetch)", .pme_long_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction fetch (not prefetch)", }, [ POWER9_PME_PM_INST_FROM_RL4 ] = { .pme_name = "PM_INST_FROM_RL4", .pme_code = 0x000002404A, .pme_short_desc = "The processor's Instruction cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to an instruction fetch (not prefetch)", .pme_long_desc = "The processor's Instruction cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to an instruction fetch (not prefetch)", }, [ POWER9_PME_PM_INST_FROM_RMEM ] = { .pme_name = "PM_INST_FROM_RMEM", .pme_code = 0x000003404A, .pme_short_desc = "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to an instruction fetch (not prefetch)", .pme_long_desc = "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to an instruction fetch (not prefetch)", }, [ POWER9_PME_PM_INST_GRP_PUMP_CPRED ] = { .pme_name = "PM_INST_GRP_PUMP_CPRED", .pme_code = 0x000002C05C, .pme_short_desc = "Initial and Final Pump Scope was group pump (prediction=correct) for an instruction fetch (demand only)", .pme_long_desc = "Initial and Final Pump Scope was group pump (prediction=correct) for an instruction fetch (demand only)", }, [ POWER9_PME_PM_INST_GRP_PUMP_MPRED_RTY ] = { .pme_name = "PM_INST_GRP_PUMP_MPRED_RTY", .pme_code = 0x0000014052, .pme_short_desc = "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for an instruction fetch", .pme_long_desc = "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for an instruction fetch", }, [ POWER9_PME_PM_INST_GRP_PUMP_MPRED ] = { .pme_name = "PM_INST_GRP_PUMP_MPRED", .pme_code = 0x000002C05E, .pme_short_desc = "Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for an instruction fetch (demand only)", .pme_long_desc = "Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for an instruction fetch (demand only)", }, [ POWER9_PME_PM_INST_IMC_MATCH_CMPL ] = { .pme_name = "PM_INST_IMC_MATCH_CMPL", .pme_code = 0x000004001C, .pme_short_desc = "IMC Match Count", .pme_long_desc = "IMC Match Count", }, [ POWER9_PME_PM_INST_PUMP_CPRED ] = { .pme_name = "PM_INST_PUMP_CPRED", .pme_code = 0x0000014054, .pme_short_desc = "Pump prediction correct.", .pme_long_desc = "Pump prediction correct. Counts across all types of pumps for an instruction fetch", }, [ POWER9_PME_PM_INST_PUMP_MPRED ] = { .pme_name = "PM_INST_PUMP_MPRED", .pme_code = 0x0000044052, .pme_short_desc = "Pump misprediction.", .pme_long_desc = "Pump misprediction. Counts across all types of pumps for an instruction fetch", }, [ POWER9_PME_PM_INST_SYS_PUMP_CPRED ] = { .pme_name = "PM_INST_SYS_PUMP_CPRED", .pme_code = 0x0000034050, .pme_short_desc = "Initial and Final Pump Scope was system pump (prediction=correct) for an instruction fetch", .pme_long_desc = "Initial and Final Pump Scope was system pump (prediction=correct) for an instruction fetch", }, [ POWER9_PME_PM_INST_SYS_PUMP_MPRED_RTY ] = { .pme_name = "PM_INST_SYS_PUMP_MPRED_RTY", .pme_code = 0x0000044050, .pme_short_desc = "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for an instruction fetch", .pme_long_desc = "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for an instruction fetch", }, [ POWER9_PME_PM_INST_SYS_PUMP_MPRED ] = { .pme_name = "PM_INST_SYS_PUMP_MPRED", .pme_code = 0x0000034052, .pme_short_desc = "Final Pump Scope (system) mispredicted.", .pme_long_desc = "Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for an instruction fetch", }, [ POWER9_PME_PM_IOPS_CMPL ] = { .pme_name = "PM_IOPS_CMPL", .pme_code = 0x0000024050, .pme_short_desc = "Internal Operations completed", .pme_long_desc = "Internal Operations completed", }, [ POWER9_PME_PM_IPTEG_FROM_DL2L3_MOD ] = { .pme_name = "PM_IPTEG_FROM_DL2L3_MOD", .pme_code = 0x0000045048, .pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a instruction side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a instruction side request", }, [ POWER9_PME_PM_IPTEG_FROM_DL2L3_SHR ] = { .pme_name = "PM_IPTEG_FROM_DL2L3_SHR", .pme_code = 0x0000035048, .pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a instruction side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a instruction side request", }, [ POWER9_PME_PM_IPTEG_FROM_DL4 ] = { .pme_name = "PM_IPTEG_FROM_DL4", .pme_code = 0x000003504C, .pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a instruction side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a instruction side request", }, [ POWER9_PME_PM_IPTEG_FROM_DMEM ] = { .pme_name = "PM_IPTEG_FROM_DMEM", .pme_code = 0x000004504C, .pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a instruction side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a instruction side request", }, [ POWER9_PME_PM_IPTEG_FROM_L21_MOD ] = { .pme_name = "PM_IPTEG_FROM_L21_MOD", .pme_code = 0x0000045046, .pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a instruction side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a instruction side request", }, [ POWER9_PME_PM_IPTEG_FROM_L21_SHR ] = { .pme_name = "PM_IPTEG_FROM_L21_SHR", .pme_code = 0x0000035046, .pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a instruction side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a instruction side request", }, [ POWER9_PME_PM_IPTEG_FROM_L2_MEPF ] = { .pme_name = "PM_IPTEG_FROM_L2_MEPF", .pme_code = 0x0000025040, .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state.", .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a instruction side request", }, [ POWER9_PME_PM_IPTEG_FROM_L2MISS ] = { .pme_name = "PM_IPTEG_FROM_L2MISS", .pme_code = 0x000001504E, .pme_short_desc = "A Page Table Entry was loaded into the TLB from a location other than the local core's L2 due to a instruction side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from a location other than the local core's L2 due to a instruction side request", }, [ POWER9_PME_PM_IPTEG_FROM_L2_NO_CONFLICT ] = { .pme_name = "PM_IPTEG_FROM_L2_NO_CONFLICT", .pme_code = 0x0000015040, .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a instruction side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a instruction side request", }, [ POWER9_PME_PM_IPTEG_FROM_L2 ] = { .pme_name = "PM_IPTEG_FROM_L2", .pme_code = 0x0000015042, .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 due to a instruction side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 due to a instruction side request", }, [ POWER9_PME_PM_IPTEG_FROM_L31_ECO_MOD ] = { .pme_name = "PM_IPTEG_FROM_L31_ECO_MOD", .pme_code = 0x0000045044, .pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a instruction side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a instruction side request", }, [ POWER9_PME_PM_IPTEG_FROM_L31_ECO_SHR ] = { .pme_name = "PM_IPTEG_FROM_L31_ECO_SHR", .pme_code = 0x0000035044, .pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a instruction side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a instruction side request", }, [ POWER9_PME_PM_IPTEG_FROM_L31_MOD ] = { .pme_name = "PM_IPTEG_FROM_L31_MOD", .pme_code = 0x0000025044, .pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a instruction side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a instruction side request", }, [ POWER9_PME_PM_IPTEG_FROM_L31_SHR ] = { .pme_name = "PM_IPTEG_FROM_L31_SHR", .pme_code = 0x0000015046, .pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a instruction side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a instruction side request", }, [ POWER9_PME_PM_IPTEG_FROM_L3_DISP_CONFLICT ] = { .pme_name = "PM_IPTEG_FROM_L3_DISP_CONFLICT", .pme_code = 0x0000035042, .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a instruction side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a instruction side request", }, [ POWER9_PME_PM_IPTEG_FROM_L3_MEPF ] = { .pme_name = "PM_IPTEG_FROM_L3_MEPF", .pme_code = 0x0000025042, .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state.", .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a instruction side request", }, [ POWER9_PME_PM_IPTEG_FROM_L3MISS ] = { .pme_name = "PM_IPTEG_FROM_L3MISS", .pme_code = 0x000004504E, .pme_short_desc = "A Page Table Entry was loaded into the TLB from a location other than the local core's L3 due to a instruction side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from a location other than the local core's L3 due to a instruction side request", }, [ POWER9_PME_PM_IPTEG_FROM_L3_NO_CONFLICT ] = { .pme_name = "PM_IPTEG_FROM_L3_NO_CONFLICT", .pme_code = 0x0000015044, .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a instruction side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a instruction side request", }, [ POWER9_PME_PM_IPTEG_FROM_L3 ] = { .pme_name = "PM_IPTEG_FROM_L3", .pme_code = 0x0000045042, .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 due to a instruction side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 due to a instruction side request", }, [ POWER9_PME_PM_IPTEG_FROM_LL4 ] = { .pme_name = "PM_IPTEG_FROM_LL4", .pme_code = 0x000001504C, .pme_short_desc = "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a instruction side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a instruction side request", }, [ POWER9_PME_PM_IPTEG_FROM_LMEM ] = { .pme_name = "PM_IPTEG_FROM_LMEM", .pme_code = 0x0000025048, .pme_short_desc = "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a instruction side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a instruction side request", }, [ POWER9_PME_PM_IPTEG_FROM_MEMORY ] = { .pme_name = "PM_IPTEG_FROM_MEMORY", .pme_code = 0x000002504C, .pme_short_desc = "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a instruction side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a instruction side request", }, [ POWER9_PME_PM_IPTEG_FROM_OFF_CHIP_CACHE ] = { .pme_name = "PM_IPTEG_FROM_OFF_CHIP_CACHE", .pme_code = 0x000004504A, .pme_short_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a instruction side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a instruction side request", }, [ POWER9_PME_PM_IPTEG_FROM_ON_CHIP_CACHE ] = { .pme_name = "PM_IPTEG_FROM_ON_CHIP_CACHE", .pme_code = 0x0000015048, .pme_short_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a instruction side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a instruction side request", }, [ POWER9_PME_PM_IPTEG_FROM_RL2L3_MOD ] = { .pme_name = "PM_IPTEG_FROM_RL2L3_MOD", .pme_code = 0x0000025046, .pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request", }, [ POWER9_PME_PM_IPTEG_FROM_RL2L3_SHR ] = { .pme_name = "PM_IPTEG_FROM_RL2L3_SHR", .pme_code = 0x000001504A, .pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request", }, [ POWER9_PME_PM_IPTEG_FROM_RL4 ] = { .pme_name = "PM_IPTEG_FROM_RL4", .pme_code = 0x000002504A, .pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a instruction side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a instruction side request", }, [ POWER9_PME_PM_IPTEG_FROM_RMEM ] = { .pme_name = "PM_IPTEG_FROM_RMEM", .pme_code = 0x000003504A, .pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a instruction side request", .pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a instruction side request", }, [ POWER9_PME_PM_ISIDE_DISP_FAIL_ADDR ] = { .pme_name = "PM_ISIDE_DISP_FAIL_ADDR", .pme_code = 0x000002608A, .pme_short_desc = "All I-side dispatch attempts for this thread that failed due to a addr collision with another machine (excludes i_l2mru_tch_reqs)", .pme_long_desc = "All I-side dispatch attempts for this thread that failed due to a addr collision with another machine (excludes i_l2mru_tch_reqs)", }, [ POWER9_PME_PM_ISIDE_DISP_FAIL_OTHER ] = { .pme_name = "PM_ISIDE_DISP_FAIL_OTHER", .pme_code = 0x000002688A, .pme_short_desc = "All I-side dispatch attempts for this thread that failed due to a reason other than addrs collision (excludes i_l2mru_tch_reqs)", .pme_long_desc = "All I-side dispatch attempts for this thread that failed due to a reason other than addrs collision (excludes i_l2mru_tch_reqs)", }, [ POWER9_PME_PM_ISIDE_DISP ] = { .pme_name = "PM_ISIDE_DISP", .pme_code = 0x000001688A, .pme_short_desc = "All I-side dispatch attempts for this thread (excludes i_l2mru_tch_reqs)", .pme_long_desc = "All I-side dispatch attempts for this thread (excludes i_l2mru_tch_reqs)", }, [ POWER9_PME_PM_ISIDE_L2MEMACC ] = { .pme_name = "PM_ISIDE_L2MEMACC", .pme_code = 0x0000026890, .pme_short_desc = "Valid when first beat of data comes in for an I-side fetch where data came from memory", .pme_long_desc = "Valid when first beat of data comes in for an I-side fetch where data came from memory", }, [ POWER9_PME_PM_ISIDE_MRU_TOUCH ] = { .pme_name = "PM_ISIDE_MRU_TOUCH", .pme_code = 0x0000046880, .pme_short_desc = "I-side L2 MRU touch sent to L2 for this thread", .pme_long_desc = "I-side L2 MRU touch sent to L2 for this thread", }, [ POWER9_PME_PM_ISLB_MISS ] = { .pme_name = "PM_ISLB_MISS", .pme_code = 0x000000D8A8, .pme_short_desc = "Instruction SLB Miss - Total of all segment sizes", .pme_long_desc = "Instruction SLB Miss - Total of all segment sizes", }, [ POWER9_PME_PM_ISLB_MISS_ALT ] = { .pme_name = "PM_ISLB_MISS_ALT", .pme_code = 0x0000040006, .pme_short_desc = "Number of ISLB misses for this thread", .pme_long_desc = "Number of ISLB misses for this thread", }, [ POWER9_PME_PM_ISQ_0_8_ENTRIES ] = { .pme_name = "PM_ISQ_0_8_ENTRIES", .pme_code = 0x000003005A, .pme_short_desc = "Cycles in which 8 or less Issue Queue entries are in use.", .pme_long_desc = "Cycles in which 8 or less Issue Queue entries are in use. This is a shared event, not per thread", }, [ POWER9_PME_PM_ISQ_36_44_ENTRIES ] = { .pme_name = "PM_ISQ_36_44_ENTRIES", .pme_code = 0x000004000A, .pme_short_desc = "Cycles in which 36 or more Issue Queue entries are in use.", .pme_long_desc = "Cycles in which 36 or more Issue Queue entries are in use. This is a shared event, not per thread. There are 44 issue queue entries across 4 slices in the whole core", }, [ POWER9_PME_PM_ISU0_ISS_HOLD_ALL ] = { .pme_name = "PM_ISU0_ISS_HOLD_ALL", .pme_code = 0x0000003080, .pme_short_desc = "All ISU rejects", .pme_long_desc = "All ISU rejects", }, [ POWER9_PME_PM_ISU1_ISS_HOLD_ALL ] = { .pme_name = "PM_ISU1_ISS_HOLD_ALL", .pme_code = 0x0000003084, .pme_short_desc = "All ISU rejects", .pme_long_desc = "All ISU rejects", }, [ POWER9_PME_PM_ISU2_ISS_HOLD_ALL ] = { .pme_name = "PM_ISU2_ISS_HOLD_ALL", .pme_code = 0x0000003880, .pme_short_desc = "All ISU rejects", .pme_long_desc = "All ISU rejects", }, [ POWER9_PME_PM_ISU3_ISS_HOLD_ALL ] = { .pme_name = "PM_ISU3_ISS_HOLD_ALL", .pme_code = 0x0000003884, .pme_short_desc = "All ISU rejects", .pme_long_desc = "All ISU rejects", }, [ POWER9_PME_PM_ISYNC ] = { .pme_name = "PM_ISYNC", .pme_code = 0x0000002884, .pme_short_desc = "Isync completion count per thread", .pme_long_desc = "Isync completion count per thread", }, [ POWER9_PME_PM_ITLB_MISS ] = { .pme_name = "PM_ITLB_MISS", .pme_code = 0x00000400FC, .pme_short_desc = "ITLB Reloaded.", .pme_long_desc = "ITLB Reloaded. Counts 1 per ITLB miss for HPT but multiple for radix depending on number of levels traveresed", }, [ POWER9_PME_PM_L1_DCACHE_RELOADED_ALL ] = { .pme_name = "PM_L1_DCACHE_RELOADED_ALL", .pme_code = 0x000001002C, .pme_short_desc = "L1 data cache reloaded for demand.", .pme_long_desc = "L1 data cache reloaded for demand. If MMCR1[16] is 1, prefetches will be included as well", }, [ POWER9_PME_PM_L1_DCACHE_RELOAD_VALID ] = { .pme_name = "PM_L1_DCACHE_RELOAD_VALID", .pme_code = 0x00000300F6, .pme_short_desc = "DL1 reloaded due to Demand Load", .pme_long_desc = "DL1 reloaded due to Demand Load", }, [ POWER9_PME_PM_L1_DEMAND_WRITE ] = { .pme_name = "PM_L1_DEMAND_WRITE", .pme_code = 0x000000408C, .pme_short_desc = "Instruction Demand sectors written into IL1", .pme_long_desc = "Instruction Demand sectors written into IL1", }, [ POWER9_PME_PM_L1_ICACHE_MISS ] = { .pme_name = "PM_L1_ICACHE_MISS", .pme_code = 0x00000200FD, .pme_short_desc = "Demand iCache Miss", .pme_long_desc = "Demand iCache Miss", }, [ POWER9_PME_PM_L1_ICACHE_RELOADED_ALL ] = { .pme_name = "PM_L1_ICACHE_RELOADED_ALL", .pme_code = 0x0000040012, .pme_short_desc = "Counts all Icache reloads includes demand, prefetch, prefetch turned into demand and demand turned into prefetch", .pme_long_desc = "Counts all Icache reloads includes demand, prefetch, prefetch turned into demand and demand turned into prefetch", }, [ POWER9_PME_PM_L1_ICACHE_RELOADED_PREF ] = { .pme_name = "PM_L1_ICACHE_RELOADED_PREF", .pme_code = 0x0000030068, .pme_short_desc = "Counts all Icache prefetch reloads ( includes demand turned into prefetch)", .pme_long_desc = "Counts all Icache prefetch reloads ( includes demand turned into prefetch)", }, [ POWER9_PME_PM_L1PF_L2MEMACC ] = { .pme_name = "PM_L1PF_L2MEMACC", .pme_code = 0x0000016890, .pme_short_desc = "Valid when first beat of data comes in for an L1PF where data came from memory", .pme_long_desc = "Valid when first beat of data comes in for an L1PF where data came from memory", }, [ POWER9_PME_PM_L1_PREF ] = { .pme_name = "PM_L1_PREF", .pme_code = 0x0000020054, .pme_short_desc = "A data line was written to the L1 due to a hardware or software prefetch", .pme_long_desc = "A data line was written to the L1 due to a hardware or software prefetch", }, [ POWER9_PME_PM_L1_SW_PREF ] = { .pme_name = "PM_L1_SW_PREF", .pme_code = 0x000000E880, .pme_short_desc = "Software L1 Prefetches, including SW Transient Prefetches", .pme_long_desc = "Software L1 Prefetches, including SW Transient Prefetches", }, [ POWER9_PME_PM_L2_CASTOUT_MOD ] = { .pme_name = "PM_L2_CASTOUT_MOD", .pme_code = 0x0000016082, .pme_short_desc = "L2 Castouts - Modified (M,Mu,Me)", .pme_long_desc = "L2 Castouts - Modified (M,Mu,Me)", }, [ POWER9_PME_PM_L2_CASTOUT_SHR ] = { .pme_name = "PM_L2_CASTOUT_SHR", .pme_code = 0x0000016882, .pme_short_desc = "L2 Castouts - Shared (Tx,Sx)", .pme_long_desc = "L2 Castouts - Shared (Tx,Sx)", }, [ POWER9_PME_PM_L2_CHIP_PUMP ] = { .pme_name = "PM_L2_CHIP_PUMP", .pme_code = 0x0000046088, .pme_short_desc = "RC requests that were local (aka chip) pump attempts", .pme_long_desc = "RC requests that were local (aka chip) pump attempts", }, [ POWER9_PME_PM_L2_DC_INV ] = { .pme_name = "PM_L2_DC_INV", .pme_code = 0x0000026882, .pme_short_desc = "D-cache invalidates sent over the reload bus to the core", .pme_long_desc = "D-cache invalidates sent over the reload bus to the core", }, [ POWER9_PME_PM_L2_DISP_ALL_L2MISS ] = { .pme_name = "PM_L2_DISP_ALL_L2MISS", .pme_code = 0x0000046080, .pme_short_desc = "All successful Ld/St dispatches for this thread that were an L2 miss (excludes i_l2mru_tch_reqs)", .pme_long_desc = "All successful Ld/St dispatches for this thread that were an L2 miss (excludes i_l2mru_tch_reqs)", }, [ POWER9_PME_PM_L2_GROUP_PUMP ] = { .pme_name = "PM_L2_GROUP_PUMP", .pme_code = 0x0000046888, .pme_short_desc = "RC requests that were on group (aka nodel) pump attempts", .pme_long_desc = "RC requests that were on group (aka nodel) pump attempts", }, [ POWER9_PME_PM_L2_GRP_GUESS_CORRECT ] = { .pme_name = "PM_L2_GRP_GUESS_CORRECT", .pme_code = 0x0000026088, .pme_short_desc = "L2 guess grp (GS or NNS) and guess was correct (data intra-group AND ^on-chip)", .pme_long_desc = "L2 guess grp (GS or NNS) and guess was correct (data intra-group AND ^on-chip)", }, [ POWER9_PME_PM_L2_GRP_GUESS_WRONG ] = { .pme_name = "PM_L2_GRP_GUESS_WRONG", .pme_code = 0x0000026888, .pme_short_desc = "L2 guess grp (GS or NNS) and guess was not correct (ie data on-chip OR beyond-group)", .pme_long_desc = "L2 guess grp (GS or NNS) and guess was not correct (ie data on-chip OR beyond-group)", }, [ POWER9_PME_PM_L2_IC_INV ] = { .pme_name = "PM_L2_IC_INV", .pme_code = 0x0000026082, .pme_short_desc = "I-cache Invalidates sent over the realod bus to the core", .pme_long_desc = "I-cache Invalidates sent over the realod bus to the core", }, [ POWER9_PME_PM_L2_INST_MISS ] = { .pme_name = "PM_L2_INST_MISS", .pme_code = 0x0000036880, .pme_short_desc = "All successful I-side dispatches that were an L2 miss for this thread (excludes i_l2mru_tch reqs)", .pme_long_desc = "All successful I-side dispatches that were an L2 miss for this thread (excludes i_l2mru_tch reqs)", }, [ POWER9_PME_PM_L2_INST_MISS_ALT ] = { .pme_name = "PM_L2_INST_MISS_ALT", .pme_code = 0x000004609E, .pme_short_desc = "All successful I-side dispatches that were an L2 miss for this thread (excludes i_l2mru_tch reqs)", .pme_long_desc = "All successful I-side dispatches that were an L2 miss for this thread (excludes i_l2mru_tch reqs)", }, [ POWER9_PME_PM_L2_INST ] = { .pme_name = "PM_L2_INST", .pme_code = 0x0000036080, .pme_short_desc = "All successful I-side dispatches for this thread (excludes i_l2mru_tch reqs)", .pme_long_desc = "All successful I-side dispatches for this thread (excludes i_l2mru_tch reqs)", }, [ POWER9_PME_PM_L2_INST_ALT ] = { .pme_name = "PM_L2_INST_ALT", .pme_code = 0x000003609E, .pme_short_desc = "All successful I-side dispatches for this thread (excludes i_l2mru_tch reqs)", .pme_long_desc = "All successful I-side dispatches for this thread (excludes i_l2mru_tch reqs)", }, [ POWER9_PME_PM_L2_LD_DISP ] = { .pme_name = "PM_L2_LD_DISP", .pme_code = 0x000001609E, .pme_short_desc = "All successful D-side load dispatches for this thread (L2 miss + L2 hits)", .pme_long_desc = "All successful D-side load dispatches for this thread (L2 miss + L2 hits)", }, [ POWER9_PME_PM_L2_LD_DISP_ALT ] = { .pme_name = "PM_L2_LD_DISP_ALT", .pme_code = 0x0000036082, .pme_short_desc = "All successful I-or-D side load dispatches for this thread (excludes i_l2mru_tch_reqs)", .pme_long_desc = "All successful I-or-D side load dispatches for this thread (excludes i_l2mru_tch_reqs)", }, [ POWER9_PME_PM_L2_LD_HIT ] = { .pme_name = "PM_L2_LD_HIT", .pme_code = 0x000002609E, .pme_short_desc = "All successful D-side load dispatches that were L2 hits for this thread", .pme_long_desc = "All successful D-side load dispatches that were L2 hits for this thread", }, [ POWER9_PME_PM_L2_LD_HIT_ALT ] = { .pme_name = "PM_L2_LD_HIT_ALT", .pme_code = 0x0000036882, .pme_short_desc = "All successful I-or-D side load dispatches for this thread that were L2 hits (excludes i_l2mru_tch_reqs)", .pme_long_desc = "All successful I-or-D side load dispatches for this thread that were L2 hits (excludes i_l2mru_tch_reqs)", }, [ POWER9_PME_PM_L2_LD_MISS_128B ] = { .pme_name = "PM_L2_LD_MISS_128B", .pme_code = 0x0000016092, .pme_short_desc = "All successful D-side load dispatches that were an L2 miss (NOT Sx,Tx,Mx) for this thread and the RC calculated the request should be for 128B (i.", .pme_long_desc = "All successful D-side load dispatches that were an L2 miss (NOT Sx,Tx,Mx) for this thread and the RC calculated the request should be for 128B (i.e., M=0)", }, [ POWER9_PME_PM_L2_LD_MISS_64B ] = { .pme_name = "PM_L2_LD_MISS_64B", .pme_code = 0x0000026092, .pme_short_desc = "All successful D-side load dispatches that were an L2 miss (NOT Sx,Tx,Mx) for this thread and the RC calculated the request should be for 64B(i.", .pme_long_desc = "All successful D-side load dispatches that were an L2 miss (NOT Sx,Tx,Mx) for this thread and the RC calculated the request should be for 64B(i.e., M=1)", }, [ POWER9_PME_PM_L2_LD_MISS ] = { .pme_name = "PM_L2_LD_MISS", .pme_code = 0x0000026080, .pme_short_desc = "All successful D-Side Load dispatches that were an L2 miss for this thread", .pme_long_desc = "All successful D-Side Load dispatches that were an L2 miss for this thread", }, [ POWER9_PME_PM_L2_LD ] = { .pme_name = "PM_L2_LD", .pme_code = 0x0000016080, .pme_short_desc = "All successful D-side Load dispatches for this thread (L2 miss + L2 hits)", .pme_long_desc = "All successful D-side Load dispatches for this thread (L2 miss + L2 hits)", }, [ POWER9_PME_PM_L2_LOC_GUESS_CORRECT ] = { .pme_name = "PM_L2_LOC_GUESS_CORRECT", .pme_code = 0x0000016088, .pme_short_desc = "L2 guess local (LNS) and guess was correct (ie data local)", .pme_long_desc = "L2 guess local (LNS) and guess was correct (ie data local)", }, [ POWER9_PME_PM_L2_LOC_GUESS_WRONG ] = { .pme_name = "PM_L2_LOC_GUESS_WRONG", .pme_code = 0x0000016888, .pme_short_desc = "L2 guess local (LNS) and guess was not correct (ie data not on chip)", .pme_long_desc = "L2 guess local (LNS) and guess was not correct (ie data not on chip)", }, [ POWER9_PME_PM_L2_RCLD_DISP_FAIL_ADDR ] = { .pme_name = "PM_L2_RCLD_DISP_FAIL_ADDR", .pme_code = 0x0000016884, .pme_short_desc = "All I-od-D side load dispatch attempts for this thread that failed due to address collision with RC/CO/SN/SQ machine (excludes i_l2mru_tch_reqs)", .pme_long_desc = "All I-od-D side load dispatch attempts for this thread that failed due to address collision with RC/CO/SN/SQ machine (excludes i_l2mru_tch_reqs)", }, [ POWER9_PME_PM_L2_RCLD_DISP_FAIL_OTHER ] = { .pme_name = "PM_L2_RCLD_DISP_FAIL_OTHER", .pme_code = 0x0000026084, .pme_short_desc = "All I-or-D side load dispatch attempts for this thread that failed due to reason other than address collision (excludes i_l2mru_tch_reqs)", .pme_long_desc = "All I-or-D side load dispatch attempts for this thread that failed due to reason other than address collision (excludes i_l2mru_tch_reqs)", }, [ POWER9_PME_PM_L2_RCLD_DISP ] = { .pme_name = "PM_L2_RCLD_DISP", .pme_code = 0x0000016084, .pme_short_desc = "All I-or-D side load dispatch attempts for this thread (excludes i_l2mru_tch_reqs)", .pme_long_desc = "All I-or-D side load dispatch attempts for this thread (excludes i_l2mru_tch_reqs)", }, [ POWER9_PME_PM_L2_RCST_DISP_FAIL_ADDR ] = { .pme_name = "PM_L2_RCST_DISP_FAIL_ADDR", .pme_code = 0x0000036884, .pme_short_desc = "All D-side store dispatch attempts for this thread that failed due to address collision with RC/CO/SN/SQ", .pme_long_desc = "All D-side store dispatch attempts for this thread that failed due to address collision with RC/CO/SN/SQ", }, [ POWER9_PME_PM_L2_RCST_DISP_FAIL_OTHER ] = { .pme_name = "PM_L2_RCST_DISP_FAIL_OTHER", .pme_code = 0x0000046084, .pme_short_desc = "All D-side store dispatch attempts for this thread that failed due to reason other than address collision", .pme_long_desc = "All D-side store dispatch attempts for this thread that failed due to reason other than address collision", }, [ POWER9_PME_PM_L2_RCST_DISP ] = { .pme_name = "PM_L2_RCST_DISP", .pme_code = 0x0000036084, .pme_short_desc = "All D-side store dispatch attempts for this thread", .pme_long_desc = "All D-side store dispatch attempts for this thread", }, [ POWER9_PME_PM_L2_RC_ST_DONE ] = { .pme_name = "PM_L2_RC_ST_DONE", .pme_code = 0x0000036086, .pme_short_desc = "RC did store to line that was Tx or Sx", .pme_long_desc = "RC did store to line that was Tx or Sx", }, [ POWER9_PME_PM_L2_RTY_LD ] = { .pme_name = "PM_L2_RTY_LD", .pme_code = 0x000003688A, .pme_short_desc = "RC retries on PB for any load from core (excludes DCBFs)", .pme_long_desc = "RC retries on PB for any load from core (excludes DCBFs)", }, [ POWER9_PME_PM_L2_RTY_LD_ALT ] = { .pme_name = "PM_L2_RTY_LD_ALT", .pme_code = 0x000003689E, .pme_short_desc = "RC retries on PB for any load from core (excludes DCBFs)", .pme_long_desc = "RC retries on PB for any load from core (excludes DCBFs)", }, [ POWER9_PME_PM_L2_RTY_ST ] = { .pme_name = "PM_L2_RTY_ST", .pme_code = 0x000003608A, .pme_short_desc = "RC retries on PB for any store from core (excludes DCBFs)", .pme_long_desc = "RC retries on PB for any store from core (excludes DCBFs)", }, [ POWER9_PME_PM_L2_RTY_ST_ALT ] = { .pme_name = "PM_L2_RTY_ST_ALT", .pme_code = 0x000004689E, .pme_short_desc = "RC retries on PB for any store from core (excludes DCBFs)", .pme_long_desc = "RC retries on PB for any store from core (excludes DCBFs)", }, [ POWER9_PME_PM_L2_SN_M_RD_DONE ] = { .pme_name = "PM_L2_SN_M_RD_DONE", .pme_code = 0x0000046086, .pme_short_desc = "SNP dispatched for a read and was M (true M)", .pme_long_desc = "SNP dispatched for a read and was M (true M)", }, [ POWER9_PME_PM_L2_SN_M_WR_DONE ] = { .pme_name = "PM_L2_SN_M_WR_DONE", .pme_code = 0x0000016086, .pme_short_desc = "SNP dispatched for a write and was M (true M); for DMA cacheinj this will pulse if rty/push is required (won't pulse if cacheinj is accepted)", .pme_long_desc = "SNP dispatched for a write and was M (true M); for DMA cacheinj this will pulse if rty/push is required (won't pulse if cacheinj is accepted)", }, [ POWER9_PME_PM_L2_SN_M_WR_DONE_ALT ] = { .pme_name = "PM_L2_SN_M_WR_DONE_ALT", .pme_code = 0x0000046886, .pme_short_desc = "SNP dispatched for a write and was M (true M); for DMA cacheinj this will pulse if rty/push is required (won't pulse if cacheinj is accepted)", .pme_long_desc = "SNP dispatched for a write and was M (true M); for DMA cacheinj this will pulse if rty/push is required (won't pulse if cacheinj is accepted)", }, [ POWER9_PME_PM_L2_SN_SX_I_DONE ] = { .pme_name = "PM_L2_SN_SX_I_DONE", .pme_code = 0x0000036886, .pme_short_desc = "SNP dispatched and went from Sx to Ix", .pme_long_desc = "SNP dispatched and went from Sx to Ix", }, [ POWER9_PME_PM_L2_ST_DISP ] = { .pme_name = "PM_L2_ST_DISP", .pme_code = 0x0000046082, .pme_short_desc = "All successful D-side store dispatches for this thread", .pme_long_desc = "All successful D-side store dispatches for this thread", }, [ POWER9_PME_PM_L2_ST_DISP_ALT ] = { .pme_name = "PM_L2_ST_DISP_ALT", .pme_code = 0x000001689E, .pme_short_desc = "All successful D-side store dispatches for this thread (L2 miss + L2 hits)", .pme_long_desc = "All successful D-side store dispatches for this thread (L2 miss + L2 hits)", }, [ POWER9_PME_PM_L2_ST_HIT ] = { .pme_name = "PM_L2_ST_HIT", .pme_code = 0x0000046882, .pme_short_desc = "All successful D-side store dispatches for this thread that were L2 hits", .pme_long_desc = "All successful D-side store dispatches for this thread that were L2 hits", }, [ POWER9_PME_PM_L2_ST_HIT_ALT ] = { .pme_name = "PM_L2_ST_HIT_ALT", .pme_code = 0x000002689E, .pme_short_desc = "All successful D-side store dispatches that were L2 hits for this thread", .pme_long_desc = "All successful D-side store dispatches that were L2 hits for this thread", }, [ POWER9_PME_PM_L2_ST_MISS_128B ] = { .pme_name = "PM_L2_ST_MISS_128B", .pme_code = 0x0000016892, .pme_short_desc = "All successful D-side store dispatches that were an L2 miss (NOT Sx,Tx,Mx) for this thread and the RC calculated the request should be for 128B (i.", .pme_long_desc = "All successful D-side store dispatches that were an L2 miss (NOT Sx,Tx,Mx) for this thread and the RC calculated the request should be for 128B (i.e., M=0)", }, [ POWER9_PME_PM_L2_ST_MISS_64B ] = { .pme_name = "PM_L2_ST_MISS_64B", .pme_code = 0x0000026892, .pme_short_desc = "All successful D-side store dispatches that were an L2 miss (NOT Sx,Tx,Mx) for this thread and the RC calculated the request should be for 64B (i.", .pme_long_desc = "All successful D-side store dispatches that were an L2 miss (NOT Sx,Tx,Mx) for this thread and the RC calculated the request should be for 64B (i.e., M=1)", }, [ POWER9_PME_PM_L2_ST_MISS ] = { .pme_name = "PM_L2_ST_MISS", .pme_code = 0x0000026880, .pme_short_desc = "All successful D-Side Store dispatches that were an L2 miss for this thread", .pme_long_desc = "All successful D-Side Store dispatches that were an L2 miss for this thread", }, [ POWER9_PME_PM_L2_ST ] = { .pme_name = "PM_L2_ST", .pme_code = 0x0000016880, .pme_short_desc = "All successful D-side store dispatches for this thread (L2 miss + L2 hits)", .pme_long_desc = "All successful D-side store dispatches for this thread (L2 miss + L2 hits)", }, [ POWER9_PME_PM_L2_SYS_GUESS_CORRECT ] = { .pme_name = "PM_L2_SYS_GUESS_CORRECT", .pme_code = 0x0000036088, .pme_short_desc = "L2 guess system (VGS or RNS) and guess was correct (ie data beyond-group)", .pme_long_desc = "L2 guess system (VGS or RNS) and guess was correct (ie data beyond-group)", }, [ POWER9_PME_PM_L2_SYS_GUESS_WRONG ] = { .pme_name = "PM_L2_SYS_GUESS_WRONG", .pme_code = 0x0000036888, .pme_short_desc = "L2 guess system (VGS or RNS) and guess was not correct (ie data ^beyond-group)", .pme_long_desc = "L2 guess system (VGS or RNS) and guess was not correct (ie data ^beyond-group)", }, [ POWER9_PME_PM_L2_SYS_PUMP ] = { .pme_name = "PM_L2_SYS_PUMP", .pme_code = 0x000004688A, .pme_short_desc = "RC requests that were system pump attempts", .pme_long_desc = "RC requests that were system pump attempts", }, [ POWER9_PME_PM_L3_CI_HIT ] = { .pme_name = "PM_L3_CI_HIT", .pme_code = 0x00000260A2, .pme_short_desc = "L3 Castins Hit (total count)", .pme_long_desc = "L3 Castins Hit (total count)", }, [ POWER9_PME_PM_L3_CI_MISS ] = { .pme_name = "PM_L3_CI_MISS", .pme_code = 0x00000268A2, .pme_short_desc = "L3 castins miss (total count)", .pme_long_desc = "L3 castins miss (total count)", }, [ POWER9_PME_PM_L3_CINJ ] = { .pme_name = "PM_L3_CINJ", .pme_code = 0x00000368A4, .pme_short_desc = "L3 castin of cache inject", .pme_long_desc = "L3 castin of cache inject", }, [ POWER9_PME_PM_L3_CI_USAGE ] = { .pme_name = "PM_L3_CI_USAGE", .pme_code = 0x00000168AC, .pme_short_desc = "Rotating sample of 16 CI or CO actives", .pme_long_desc = "Rotating sample of 16 CI or CO actives", }, [ POWER9_PME_PM_L3_CO0_BUSY ] = { .pme_name = "PM_L3_CO0_BUSY", .pme_code = 0x00000368AC, .pme_short_desc = "Lifetime, sample of CO machine 0 valid", .pme_long_desc = "Lifetime, sample of CO machine 0 valid", }, [ POWER9_PME_PM_L3_CO0_BUSY_ALT ] = { .pme_name = "PM_L3_CO0_BUSY_ALT", .pme_code = 0x00000468AC, .pme_short_desc = "Lifetime, sample of CO machine 0 valid", .pme_long_desc = "Lifetime, sample of CO machine 0 valid", }, [ POWER9_PME_PM_L3_CO_L31 ] = { .pme_name = "PM_L3_CO_L31", .pme_code = 0x00000268A0, .pme_short_desc = "L3 CO to L3.", .pme_long_desc = "L3 CO to L3.1 OR of port 0 and 1 (lossy = may undercount if two cresps come in the same cyc)", }, [ POWER9_PME_PM_L3_CO_LCO ] = { .pme_name = "PM_L3_CO_LCO", .pme_code = 0x00000360A4, .pme_short_desc = "Total L3 COs occurred on LCO L3.", .pme_long_desc = "Total L3 COs occurred on LCO L3.1 (good cresp, may end up in mem on a retry)", }, [ POWER9_PME_PM_L3_CO_MEM ] = { .pme_name = "PM_L3_CO_MEM", .pme_code = 0x00000260A0, .pme_short_desc = "L3 CO to memory OR of port 0 and 1 (lossy = may undercount if two cresp come in the same cyc)", .pme_long_desc = "L3 CO to memory OR of port 0 and 1 (lossy = may undercount if two cresp come in the same cyc)", }, [ POWER9_PME_PM_L3_CO_MEPF ] = { .pme_name = "PM_L3_CO_MEPF", .pme_code = 0x000003E05E, .pme_short_desc = "L3 castouts in Mepf state for this thread", .pme_long_desc = "L3 castouts in Mepf state for this thread", }, [ POWER9_PME_PM_L3_CO_MEPF_ALT ] = { .pme_name = "PM_L3_CO_MEPF_ALT", .pme_code = 0x00000168A0, .pme_short_desc = "L3 CO of line in Mep state (includes casthrough to memory).", .pme_long_desc = "L3 CO of line in Mep state (includes casthrough to memory). The Mepf state indicates that a line was brought in to satisfy an L3 prefetch request", }, [ POWER9_PME_PM_L3_CO ] = { .pme_name = "PM_L3_CO", .pme_code = 0x00000360A8, .pme_short_desc = "L3 castout occurring (does not include casthrough or log writes (cinj/dmaw))", .pme_long_desc = "L3 castout occurring (does not include casthrough or log writes (cinj/dmaw))", }, [ POWER9_PME_PM_L3_GRP_GUESS_CORRECT ] = { .pme_name = "PM_L3_GRP_GUESS_CORRECT", .pme_code = 0x00000168B2, .pme_short_desc = "Initial scope=group (GS or NNS) and data from same group (near) (pred successful)", .pme_long_desc = "Initial scope=group (GS or NNS) and data from same group (near) (pred successful)", }, [ POWER9_PME_PM_L3_GRP_GUESS_WRONG_HIGH ] = { .pme_name = "PM_L3_GRP_GUESS_WRONG_HIGH", .pme_code = 0x00000368B2, .pme_short_desc = "Initial scope=group (GS or NNS) but data from local node.", .pme_long_desc = "Initial scope=group (GS or NNS) but data from local node. Prediction too high", }, [ POWER9_PME_PM_L3_GRP_GUESS_WRONG_LOW ] = { .pme_name = "PM_L3_GRP_GUESS_WRONG_LOW", .pme_code = 0x00000360B2, .pme_short_desc = "Initial scope=group (GS or NNS) but data from outside group (far or rem).", .pme_long_desc = "Initial scope=group (GS or NNS) but data from outside group (far or rem). Prediction too Low", }, [ POWER9_PME_PM_L3_HIT ] = { .pme_name = "PM_L3_HIT", .pme_code = 0x00000160A4, .pme_short_desc = "L3 Hits (L2 miss hitting L3, including data/instrn/xlate)", .pme_long_desc = "L3 Hits (L2 miss hitting L3, including data/instrn/xlate)", }, [ POWER9_PME_PM_L3_L2_CO_HIT ] = { .pme_name = "PM_L3_L2_CO_HIT", .pme_code = 0x00000360A2, .pme_short_desc = "L2 CO hits", .pme_long_desc = "L2 CO hits", }, [ POWER9_PME_PM_L3_L2_CO_MISS ] = { .pme_name = "PM_L3_L2_CO_MISS", .pme_code = 0x00000368A2, .pme_short_desc = "L2 CO miss", .pme_long_desc = "L2 CO miss", }, [ POWER9_PME_PM_L3_LAT_CI_HIT ] = { .pme_name = "PM_L3_LAT_CI_HIT", .pme_code = 0x00000460A2, .pme_short_desc = "L3 Lateral Castins Hit", .pme_long_desc = "L3 Lateral Castins Hit", }, [ POWER9_PME_PM_L3_LAT_CI_MISS ] = { .pme_name = "PM_L3_LAT_CI_MISS", .pme_code = 0x00000468A2, .pme_short_desc = "L3 Lateral Castins Miss", .pme_long_desc = "L3 Lateral Castins Miss", }, [ POWER9_PME_PM_L3_LD_HIT ] = { .pme_name = "PM_L3_LD_HIT", .pme_code = 0x00000260A4, .pme_short_desc = "L3 Hits for demand LDs", .pme_long_desc = "L3 Hits for demand LDs", }, [ POWER9_PME_PM_L3_LD_MISS ] = { .pme_name = "PM_L3_LD_MISS", .pme_code = 0x00000268A4, .pme_short_desc = "L3 Misses for demand LDs", .pme_long_desc = "L3 Misses for demand LDs", }, [ POWER9_PME_PM_L3_LD_PREF ] = { .pme_name = "PM_L3_LD_PREF", .pme_code = 0x000000F0B0, .pme_short_desc = "L3 load prefetch, sourced from a hardware or software stream, was sent to the nest", .pme_long_desc = "L3 load prefetch, sourced from a hardware or software stream, was sent to the nest", }, [ POWER9_PME_PM_L3_LOC_GUESS_CORRECT ] = { .pme_name = "PM_L3_LOC_GUESS_CORRECT", .pme_code = 0x00000160B2, .pme_short_desc = "initial scope=node/chip (LNS) and data from local node (local) (pred successful) - always PFs only", .pme_long_desc = "initial scope=node/chip (LNS) and data from local node (local) (pred successful) - always PFs only", }, [ POWER9_PME_PM_L3_LOC_GUESS_WRONG ] = { .pme_name = "PM_L3_LOC_GUESS_WRONG", .pme_code = 0x00000268B2, .pme_short_desc = "Initial scope=node (LNS) but data from out side local node (near or far or rem).", .pme_long_desc = "Initial scope=node (LNS) but data from out side local node (near or far or rem). Prediction too Low", }, [ POWER9_PME_PM_L3_MISS ] = { .pme_name = "PM_L3_MISS", .pme_code = 0x00000168A4, .pme_short_desc = "L3 Misses (L2 miss also missing L3, including data/instrn/xlate)", .pme_long_desc = "L3 Misses (L2 miss also missing L3, including data/instrn/xlate)", }, [ POWER9_PME_PM_L3_P0_CO_L31 ] = { .pme_name = "PM_L3_P0_CO_L31", .pme_code = 0x00000460AA, .pme_short_desc = "L3 CO to L3.", .pme_long_desc = "L3 CO to L3.1 (LCO) port 0 with or without data", }, [ POWER9_PME_PM_L3_P0_CO_MEM ] = { .pme_name = "PM_L3_P0_CO_MEM", .pme_code = 0x00000360AA, .pme_short_desc = "L3 CO to memory port 0 with or without data", .pme_long_desc = "L3 CO to memory port 0 with or without data", }, [ POWER9_PME_PM_L3_P0_CO_RTY ] = { .pme_name = "PM_L3_P0_CO_RTY", .pme_code = 0x00000360AE, .pme_short_desc = "L3 CO received retry port 0 (memory only), every retry counted", .pme_long_desc = "L3 CO received retry port 0 (memory only), every retry counted", }, [ POWER9_PME_PM_L3_P0_CO_RTY_ALT ] = { .pme_name = "PM_L3_P0_CO_RTY_ALT", .pme_code = 0x00000460AE, .pme_short_desc = "L3 CO received retry port 2 (memory only), every retry counted", .pme_long_desc = "L3 CO received retry port 2 (memory only), every retry counted", }, [ POWER9_PME_PM_L3_P0_GRP_PUMP ] = { .pme_name = "PM_L3_P0_GRP_PUMP", .pme_code = 0x00000260B0, .pme_short_desc = "L3 PF sent with grp scope port 0, counts even retried requests", .pme_long_desc = "L3 PF sent with grp scope port 0, counts even retried requests", }, [ POWER9_PME_PM_L3_P0_LCO_DATA ] = { .pme_name = "PM_L3_P0_LCO_DATA", .pme_code = 0x00000260AA, .pme_short_desc = "LCO sent with data port 0", .pme_long_desc = "LCO sent with data port 0", }, [ POWER9_PME_PM_L3_P0_LCO_NO_DATA ] = { .pme_name = "PM_L3_P0_LCO_NO_DATA", .pme_code = 0x00000160AA, .pme_short_desc = "Dataless L3 LCO sent port 0", .pme_long_desc = "Dataless L3 LCO sent port 0", }, [ POWER9_PME_PM_L3_P0_LCO_RTY ] = { .pme_name = "PM_L3_P0_LCO_RTY", .pme_code = 0x00000160B4, .pme_short_desc = "L3 initiated LCO received retry on port 0 (can try 4 times)", .pme_long_desc = "L3 initiated LCO received retry on port 0 (can try 4 times)", }, [ POWER9_PME_PM_L3_P0_NODE_PUMP ] = { .pme_name = "PM_L3_P0_NODE_PUMP", .pme_code = 0x00000160B0, .pme_short_desc = "L3 PF sent with nodal scope port 0, counts even retried requests", .pme_long_desc = "L3 PF sent with nodal scope port 0, counts even retried requests", }, [ POWER9_PME_PM_L3_P0_PF_RTY ] = { .pme_name = "PM_L3_P0_PF_RTY", .pme_code = 0x00000160AE, .pme_short_desc = "L3 PF received retry port 0, every retry counted", .pme_long_desc = "L3 PF received retry port 0, every retry counted", }, [ POWER9_PME_PM_L3_P0_PF_RTY_ALT ] = { .pme_name = "PM_L3_P0_PF_RTY_ALT", .pme_code = 0x00000260AE, .pme_short_desc = "L3 PF received retry port 2, every retry counted", .pme_long_desc = "L3 PF received retry port 2, every retry counted", }, [ POWER9_PME_PM_L3_P0_SYS_PUMP ] = { .pme_name = "PM_L3_P0_SYS_PUMP", .pme_code = 0x00000360B0, .pme_short_desc = "L3 PF sent with sys scope port 0, counts even retried requests", .pme_long_desc = "L3 PF sent with sys scope port 0, counts even retried requests", }, [ POWER9_PME_PM_L3_P1_CO_L31 ] = { .pme_name = "PM_L3_P1_CO_L31", .pme_code = 0x00000468AA, .pme_short_desc = "L3 CO to L3.", .pme_long_desc = "L3 CO to L3.1 (LCO) port 1 with or without data", }, [ POWER9_PME_PM_L3_P1_CO_MEM ] = { .pme_name = "PM_L3_P1_CO_MEM", .pme_code = 0x00000368AA, .pme_short_desc = "L3 CO to memory port 1 with or without data", .pme_long_desc = "L3 CO to memory port 1 with or without data", }, [ POWER9_PME_PM_L3_P1_CO_RTY ] = { .pme_name = "PM_L3_P1_CO_RTY", .pme_code = 0x00000368AE, .pme_short_desc = "L3 CO received retry port 1 (memory only), every retry counted", .pme_long_desc = "L3 CO received retry port 1 (memory only), every retry counted", }, [ POWER9_PME_PM_L3_P1_CO_RTY_ALT ] = { .pme_name = "PM_L3_P1_CO_RTY_ALT", .pme_code = 0x00000468AE, .pme_short_desc = "L3 CO received retry port 3 (memory only), every retry counted", .pme_long_desc = "L3 CO received retry port 3 (memory only), every retry counted", }, [ POWER9_PME_PM_L3_P1_GRP_PUMP ] = { .pme_name = "PM_L3_P1_GRP_PUMP", .pme_code = 0x00000268B0, .pme_short_desc = "L3 PF sent with grp scope port 1, counts even retried requests", .pme_long_desc = "L3 PF sent with grp scope port 1, counts even retried requests", }, [ POWER9_PME_PM_L3_P1_LCO_DATA ] = { .pme_name = "PM_L3_P1_LCO_DATA", .pme_code = 0x00000268AA, .pme_short_desc = "LCO sent with data port 1", .pme_long_desc = "LCO sent with data port 1", }, [ POWER9_PME_PM_L3_P1_LCO_NO_DATA ] = { .pme_name = "PM_L3_P1_LCO_NO_DATA", .pme_code = 0x00000168AA, .pme_short_desc = "Dataless L3 LCO sent port 1", .pme_long_desc = "Dataless L3 LCO sent port 1", }, [ POWER9_PME_PM_L3_P1_LCO_RTY ] = { .pme_name = "PM_L3_P1_LCO_RTY", .pme_code = 0x00000168B4, .pme_short_desc = "L3 initiated LCO received retry on port 1 (can try 4 times)", .pme_long_desc = "L3 initiated LCO received retry on port 1 (can try 4 times)", }, [ POWER9_PME_PM_L3_P1_NODE_PUMP ] = { .pme_name = "PM_L3_P1_NODE_PUMP", .pme_code = 0x00000168B0, .pme_short_desc = "L3 PF sent with nodal scope port 1, counts even retried requests", .pme_long_desc = "L3 PF sent with nodal scope port 1, counts even retried requests", }, [ POWER9_PME_PM_L3_P1_PF_RTY ] = { .pme_name = "PM_L3_P1_PF_RTY", .pme_code = 0x00000168AE, .pme_short_desc = "L3 PF received retry port 1, every retry counted", .pme_long_desc = "L3 PF received retry port 1, every retry counted", }, [ POWER9_PME_PM_L3_P1_PF_RTY_ALT ] = { .pme_name = "PM_L3_P1_PF_RTY_ALT", .pme_code = 0x00000268AE, .pme_short_desc = "L3 PF received retry port 3, every retry counted", .pme_long_desc = "L3 PF received retry port 3, every retry counted", }, [ POWER9_PME_PM_L3_P1_SYS_PUMP ] = { .pme_name = "PM_L3_P1_SYS_PUMP", .pme_code = 0x00000368B0, .pme_short_desc = "L3 PF sent with sys scope port 1, counts even retried requests", .pme_long_desc = "L3 PF sent with sys scope port 1, counts even retried requests", }, [ POWER9_PME_PM_L3_P2_LCO_RTY ] = { .pme_name = "PM_L3_P2_LCO_RTY", .pme_code = 0x00000260B4, .pme_short_desc = "L3 initiated LCO received retry on port 2 (can try 4 times)", .pme_long_desc = "L3 initiated LCO received retry on port 2 (can try 4 times)", }, [ POWER9_PME_PM_L3_P3_LCO_RTY ] = { .pme_name = "PM_L3_P3_LCO_RTY", .pme_code = 0x00000268B4, .pme_short_desc = "L3 initiated LCO received retry on port 3 (can try 4 times)", .pme_long_desc = "L3 initiated LCO received retry on port 3 (can try 4 times)", }, [ POWER9_PME_PM_L3_PF0_BUSY ] = { .pme_name = "PM_L3_PF0_BUSY", .pme_code = 0x00000360B4, .pme_short_desc = "Lifetime, sample of PF machine 0 valid", .pme_long_desc = "Lifetime, sample of PF machine 0 valid", }, [ POWER9_PME_PM_L3_PF0_BUSY_ALT ] = { .pme_name = "PM_L3_PF0_BUSY_ALT", .pme_code = 0x00000460B4, .pme_short_desc = "Lifetime, sample of PF machine 0 valid", .pme_long_desc = "Lifetime, sample of PF machine 0 valid", }, [ POWER9_PME_PM_L3_PF_HIT_L3 ] = { .pme_name = "PM_L3_PF_HIT_L3", .pme_code = 0x00000260A8, .pme_short_desc = "L3 PF hit in L3 (abandoned)", .pme_long_desc = "L3 PF hit in L3 (abandoned)", }, [ POWER9_PME_PM_L3_PF_MISS_L3 ] = { .pme_name = "PM_L3_PF_MISS_L3", .pme_code = 0x00000160A0, .pme_short_desc = "L3 PF missed in L3", .pme_long_desc = "L3 PF missed in L3", }, [ POWER9_PME_PM_L3_PF_OFF_CHIP_CACHE ] = { .pme_name = "PM_L3_PF_OFF_CHIP_CACHE", .pme_code = 0x00000368A0, .pme_short_desc = "L3 PF from Off chip cache", .pme_long_desc = "L3 PF from Off chip cache", }, [ POWER9_PME_PM_L3_PF_OFF_CHIP_MEM ] = { .pme_name = "PM_L3_PF_OFF_CHIP_MEM", .pme_code = 0x00000468A0, .pme_short_desc = "L3 PF from Off chip memory", .pme_long_desc = "L3 PF from Off chip memory", }, [ POWER9_PME_PM_L3_PF_ON_CHIP_CACHE ] = { .pme_name = "PM_L3_PF_ON_CHIP_CACHE", .pme_code = 0x00000360A0, .pme_short_desc = "L3 PF from On chip cache", .pme_long_desc = "L3 PF from On chip cache", }, [ POWER9_PME_PM_L3_PF_ON_CHIP_MEM ] = { .pme_name = "PM_L3_PF_ON_CHIP_MEM", .pme_code = 0x00000460A0, .pme_short_desc = "L3 PF from On chip memory", .pme_long_desc = "L3 PF from On chip memory", }, [ POWER9_PME_PM_L3_PF_USAGE ] = { .pme_name = "PM_L3_PF_USAGE", .pme_code = 0x00000260AC, .pme_short_desc = "Rotating sample of 32 PF actives", .pme_long_desc = "Rotating sample of 32 PF actives", }, [ POWER9_PME_PM_L3_RD0_BUSY ] = { .pme_name = "PM_L3_RD0_BUSY", .pme_code = 0x00000368B4, .pme_short_desc = "Lifetime, sample of RD machine 0 valid", .pme_long_desc = "Lifetime, sample of RD machine 0 valid", }, [ POWER9_PME_PM_L3_RD0_BUSY_ALT ] = { .pme_name = "PM_L3_RD0_BUSY_ALT", .pme_code = 0x00000468B4, .pme_short_desc = "Lifetime, sample of RD machine 0 valid", .pme_long_desc = "Lifetime, sample of RD machine 0 valid", }, [ POWER9_PME_PM_L3_RD_USAGE ] = { .pme_name = "PM_L3_RD_USAGE", .pme_code = 0x00000268AC, .pme_short_desc = "Rotating sample of 16 RD actives", .pme_long_desc = "Rotating sample of 16 RD actives", }, [ POWER9_PME_PM_L3_SN0_BUSY ] = { .pme_name = "PM_L3_SN0_BUSY", .pme_code = 0x00000360AC, .pme_short_desc = "Lifetime, sample of snooper machine 0 valid", .pme_long_desc = "Lifetime, sample of snooper machine 0 valid", }, [ POWER9_PME_PM_L3_SN0_BUSY_ALT ] = { .pme_name = "PM_L3_SN0_BUSY_ALT", .pme_code = 0x00000460AC, .pme_short_desc = "Lifetime, sample of snooper machine 0 valid", .pme_long_desc = "Lifetime, sample of snooper machine 0 valid", }, [ POWER9_PME_PM_L3_SN_USAGE ] = { .pme_name = "PM_L3_SN_USAGE", .pme_code = 0x00000160AC, .pme_short_desc = "Rotating sample of 16 snoop valids", .pme_long_desc = "Rotating sample of 16 snoop valids", }, [ POWER9_PME_PM_L3_SW_PREF ] = { .pme_name = "PM_L3_SW_PREF", .pme_code = 0x000000F8B0, .pme_short_desc = "L3 load prefetch, sourced from a software prefetch stream, was sent to the nest", .pme_long_desc = "L3 load prefetch, sourced from a software prefetch stream, was sent to the nest", }, [ POWER9_PME_PM_L3_SYS_GUESS_CORRECT ] = { .pme_name = "PM_L3_SYS_GUESS_CORRECT", .pme_code = 0x00000260B2, .pme_short_desc = "Initial scope=system (VGS or RNS) and data from outside group (far or rem)(pred successful)", .pme_long_desc = "Initial scope=system (VGS or RNS) and data from outside group (far or rem)(pred successful)", }, [ POWER9_PME_PM_L3_SYS_GUESS_WRONG ] = { .pme_name = "PM_L3_SYS_GUESS_WRONG", .pme_code = 0x00000460B2, .pme_short_desc = "Initial scope=system (VGS or RNS) but data from local or near.", .pme_long_desc = "Initial scope=system (VGS or RNS) but data from local or near. Prediction too high", }, [ POWER9_PME_PM_L3_TRANS_PF ] = { .pme_name = "PM_L3_TRANS_PF", .pme_code = 0x00000468A4, .pme_short_desc = "L3 Transient prefetch received from L2", .pme_long_desc = "L3 Transient prefetch received from L2", }, [ POWER9_PME_PM_L3_WI0_BUSY ] = { .pme_name = "PM_L3_WI0_BUSY", .pme_code = 0x00000160B6, .pme_short_desc = "Rotating sample of 8 WI valid", .pme_long_desc = "Rotating sample of 8 WI valid", }, [ POWER9_PME_PM_L3_WI0_BUSY_ALT ] = { .pme_name = "PM_L3_WI0_BUSY_ALT", .pme_code = 0x00000260B6, .pme_short_desc = "Rotating sample of 8 WI valid (duplicate)", .pme_long_desc = "Rotating sample of 8 WI valid (duplicate)", }, [ POWER9_PME_PM_L3_WI_USAGE ] = { .pme_name = "PM_L3_WI_USAGE", .pme_code = 0x00000168A8, .pme_short_desc = "Lifetime, sample of Write Inject machine 0 valid", .pme_long_desc = "Lifetime, sample of Write Inject machine 0 valid", }, [ POWER9_PME_PM_LARX_FIN ] = { .pme_name = "PM_LARX_FIN", .pme_code = 0x000003C058, .pme_short_desc = "Larx finished", .pme_long_desc = "Larx finished", }, [ POWER9_PME_PM_LD_CMPL ] = { .pme_name = "PM_LD_CMPL", .pme_code = 0x000004003E, .pme_short_desc = "count of Loads completed", .pme_long_desc = "count of Loads completed", }, [ POWER9_PME_PM_LD_L3MISS_PEND_CYC ] = { .pme_name = "PM_LD_L3MISS_PEND_CYC", .pme_code = 0x0000010062, .pme_short_desc = "Cycles L3 miss was pending for this thread", .pme_long_desc = "Cycles L3 miss was pending for this thread", }, [ POWER9_PME_PM_LD_MISS_L1_FIN ] = { .pme_name = "PM_LD_MISS_L1_FIN", .pme_code = 0x000002C04E, .pme_short_desc = "Number of load instructions that finished with an L1 miss.", .pme_long_desc = "Number of load instructions that finished with an L1 miss. Note that even if a load spans multiple slices this event will increment only once per load op.", }, /* See also alternate entries for 000003E054 / POWER9_PME_PM_LD_MISS_L1 with code(s) 00000400F0 at the bottom of this table. \n */ [ POWER9_PME_PM_LD_MISS_L1 ] = { .pme_name = "PM_LD_MISS_L1", .pme_code = 0x000003E054, .pme_short_desc = "Load Missed L1, counted at execution time (can be greater than loads finished).", .pme_long_desc = "Load Missed L1, counted at execution time (can be greater than loads finished). LMQ merges are not included in this count. i.e. if a load instruction misses on an address that is already allocated on the LMQ, this event will not increment for that load). Note that this count is per slice, so if a load spans multiple slices this event will increment multiple times for a single load.", }, [ POWER9_PME_PM_LD_REF_L1 ] = { .pme_name = "PM_LD_REF_L1", .pme_code = 0x00000100FC, .pme_short_desc = "All L1 D cache load references counted at finish, gated by reject", .pme_long_desc = "All L1 D cache load references counted at finish, gated by reject", }, [ POWER9_PME_PM_LINK_STACK_CORRECT ] = { .pme_name = "PM_LINK_STACK_CORRECT", .pme_code = 0x00000058A0, .pme_short_desc = "Link stack predicts right address", .pme_long_desc = "Link stack predicts right address", }, [ POWER9_PME_PM_LINK_STACK_INVALID_PTR ] = { .pme_name = "PM_LINK_STACK_INVALID_PTR", .pme_code = 0x0000005898, .pme_short_desc = "It is most often caused by certain types of flush where the pointer is not available.", .pme_long_desc = "It is most often caused by certain types of flush where the pointer is not available. Can result in the data in the link stack becoming unusable.", }, [ POWER9_PME_PM_LINK_STACK_WRONG_ADD_PRED ] = { .pme_name = "PM_LINK_STACK_WRONG_ADD_PRED", .pme_code = 0x0000005098, .pme_short_desc = "Link stack predicts wrong address, because of link stack design limitation or software violating the coding conventions", .pme_long_desc = "Link stack predicts wrong address, because of link stack design limitation or software violating the coding conventions", }, [ POWER9_PME_PM_LMQ_EMPTY_CYC ] = { .pme_name = "PM_LMQ_EMPTY_CYC", .pme_code = 0x000002E05E, .pme_short_desc = "Cycles in which the LMQ has no pending load misses for this thread", .pme_long_desc = "Cycles in which the LMQ has no pending load misses for this thread", }, [ POWER9_PME_PM_LMQ_MERGE ] = { .pme_name = "PM_LMQ_MERGE", .pme_code = 0x000001002E, .pme_short_desc = "A demand miss collides with a prefetch for the same line", .pme_long_desc = "A demand miss collides with a prefetch for the same line", }, [ POWER9_PME_PM_LRQ_REJECT ] = { .pme_name = "PM_LRQ_REJECT", .pme_code = 0x000002E05A, .pme_short_desc = "Internal LSU reject from LRQ.", .pme_long_desc = "Internal LSU reject from LRQ. Rejects cause the load to go back to LRQ, but it stays contained within the LSU once it gets issued. This event counts the number of times the LRQ attempts to relaunch an instruction after a reject. Any load can suffer multiple rejects", }, [ POWER9_PME_PM_LS0_DC_COLLISIONS ] = { .pme_name = "PM_LS0_DC_COLLISIONS", .pme_code = 0x000000D090, .pme_short_desc = "Read-write data cache collisions", .pme_long_desc = "Read-write data cache collisions", }, [ POWER9_PME_PM_LS0_ERAT_MISS_PREF ] = { .pme_name = "PM_LS0_ERAT_MISS_PREF", .pme_code = 0x000000E084, .pme_short_desc = "LS0 Erat miss due to prefetch", .pme_long_desc = "LS0 Erat miss due to prefetch", }, [ POWER9_PME_PM_LS0_LAUNCH_HELD_PREF ] = { .pme_name = "PM_LS0_LAUNCH_HELD_PREF", .pme_code = 0x000000C09C, .pme_short_desc = "Number of times a load or store instruction was unable to launch/relaunch because a high priority prefetch used that relaunch cycle", .pme_long_desc = "Number of times a load or store instruction was unable to launch/relaunch because a high priority prefetch used that relaunch cycle", }, [ POWER9_PME_PM_LS0_PTE_TABLEWALK_CYC ] = { .pme_name = "PM_LS0_PTE_TABLEWALK_CYC", .pme_code = 0x000000E0BC, .pme_short_desc = "Cycles when a tablewalk is pending on this thread on table 0", .pme_long_desc = "Cycles when a tablewalk is pending on this thread on table 0", }, [ POWER9_PME_PM_LS0_TM_DISALLOW ] = { .pme_name = "PM_LS0_TM_DISALLOW", .pme_code = 0x000000E0B4, .pme_short_desc = "A TM-ineligible instruction tries to execute inside a transaction and the LSU disallows it", .pme_long_desc = "A TM-ineligible instruction tries to execute inside a transaction and the LSU disallows it", }, [ POWER9_PME_PM_LS0_UNALIGNED_LD ] = { .pme_name = "PM_LS0_UNALIGNED_LD", .pme_code = 0x000000C094, .pme_short_desc = "Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size.", .pme_long_desc = "Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size. If the load wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty", }, [ POWER9_PME_PM_LS0_UNALIGNED_ST ] = { .pme_name = "PM_LS0_UNALIGNED_ST", .pme_code = 0x000000F0B8, .pme_short_desc = "Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size.", .pme_long_desc = "Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size. If the Store wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty", }, [ POWER9_PME_PM_LS1_DC_COLLISIONS ] = { .pme_name = "PM_LS1_DC_COLLISIONS", .pme_code = 0x000000D890, .pme_short_desc = "Read-write data cache collisions", .pme_long_desc = "Read-write data cache collisions", }, [ POWER9_PME_PM_LS1_ERAT_MISS_PREF ] = { .pme_name = "PM_LS1_ERAT_MISS_PREF", .pme_code = 0x000000E884, .pme_short_desc = "LS1 Erat miss due to prefetch", .pme_long_desc = "LS1 Erat miss due to prefetch", }, [ POWER9_PME_PM_LS1_LAUNCH_HELD_PREF ] = { .pme_name = "PM_LS1_LAUNCH_HELD_PREF", .pme_code = 0x000000C89C, .pme_short_desc = "Number of times a load or store instruction was unable to launch/relaunch because a high priority prefetch used that relaunch cycle", .pme_long_desc = "Number of times a load or store instruction was unable to launch/relaunch because a high priority prefetch used that relaunch cycle", }, [ POWER9_PME_PM_LS1_PTE_TABLEWALK_CYC ] = { .pme_name = "PM_LS1_PTE_TABLEWALK_CYC", .pme_code = 0x000000E8BC, .pme_short_desc = "Cycles when a tablewalk is pending on this thread on table 1", .pme_long_desc = "Cycles when a tablewalk is pending on this thread on table 1", }, [ POWER9_PME_PM_LS1_TM_DISALLOW ] = { .pme_name = "PM_LS1_TM_DISALLOW", .pme_code = 0x000000E8B4, .pme_short_desc = "A TM-ineligible instruction tries to execute inside a transaction and the LSU disallows it", .pme_long_desc = "A TM-ineligible instruction tries to execute inside a transaction and the LSU disallows it", }, [ POWER9_PME_PM_LS1_UNALIGNED_LD ] = { .pme_name = "PM_LS1_UNALIGNED_LD", .pme_code = 0x000000C894, .pme_short_desc = "Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size.", .pme_long_desc = "Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size. If the load wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty", }, [ POWER9_PME_PM_LS1_UNALIGNED_ST ] = { .pme_name = "PM_LS1_UNALIGNED_ST", .pme_code = 0x000000F8B8, .pme_short_desc = "Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size.", .pme_long_desc = "Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size. If the Store wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty", }, [ POWER9_PME_PM_LS2_DC_COLLISIONS ] = { .pme_name = "PM_LS2_DC_COLLISIONS", .pme_code = 0x000000D094, .pme_short_desc = "Read-write data cache collisions", .pme_long_desc = "Read-write data cache collisions", }, [ POWER9_PME_PM_LS2_ERAT_MISS_PREF ] = { .pme_name = "PM_LS2_ERAT_MISS_PREF", .pme_code = 0x000000E088, .pme_short_desc = "LS0 Erat miss due to prefetch", .pme_long_desc = "LS0 Erat miss due to prefetch", }, [ POWER9_PME_PM_LS2_TM_DISALLOW ] = { .pme_name = "PM_LS2_TM_DISALLOW", .pme_code = 0x000000E0B8, .pme_short_desc = "A TM-ineligible instruction tries to execute inside a transaction and the LSU disallows it", .pme_long_desc = "A TM-ineligible instruction tries to execute inside a transaction and the LSU disallows it", }, [ POWER9_PME_PM_LS2_UNALIGNED_LD ] = { .pme_name = "PM_LS2_UNALIGNED_LD", .pme_code = 0x000000C098, .pme_short_desc = "Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size.", .pme_long_desc = "Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size. If the load wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty", }, [ POWER9_PME_PM_LS2_UNALIGNED_ST ] = { .pme_name = "PM_LS2_UNALIGNED_ST", .pme_code = 0x000000F0BC, .pme_short_desc = "Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size.", .pme_long_desc = "Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size. If the Store wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty", }, [ POWER9_PME_PM_LS3_DC_COLLISIONS ] = { .pme_name = "PM_LS3_DC_COLLISIONS", .pme_code = 0x000000D894, .pme_short_desc = "Read-write data cache collisions", .pme_long_desc = "Read-write data cache collisions", }, [ POWER9_PME_PM_LS3_ERAT_MISS_PREF ] = { .pme_name = "PM_LS3_ERAT_MISS_PREF", .pme_code = 0x000000E888, .pme_short_desc = "LS1 Erat miss due to prefetch", .pme_long_desc = "LS1 Erat miss due to prefetch", }, [ POWER9_PME_PM_LS3_TM_DISALLOW ] = { .pme_name = "PM_LS3_TM_DISALLOW", .pme_code = 0x000000E8B8, .pme_short_desc = "A TM-ineligible instruction tries to execute inside a transaction and the LSU disallows it", .pme_long_desc = "A TM-ineligible instruction tries to execute inside a transaction and the LSU disallows it", }, [ POWER9_PME_PM_LS3_UNALIGNED_LD ] = { .pme_name = "PM_LS3_UNALIGNED_LD", .pme_code = 0x000000C898, .pme_short_desc = "Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size.", .pme_long_desc = "Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size. If the load wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty", }, [ POWER9_PME_PM_LS3_UNALIGNED_ST ] = { .pme_name = "PM_LS3_UNALIGNED_ST", .pme_code = 0x000000F8BC, .pme_short_desc = "Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size.", .pme_long_desc = "Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size. If the Store wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty", }, [ POWER9_PME_PM_LSU0_1_LRQF_FULL_CYC ] = { .pme_name = "PM_LSU0_1_LRQF_FULL_CYC", .pme_code = 0x000000D0BC, .pme_short_desc = "Counts the number of cycles the LRQF is full.", .pme_long_desc = "Counts the number of cycles the LRQF is full. LRQF is the queue that holds loads between finish and completion. If it fills up, instructions stay in LRQ until completion, potentially backing up the LRQ", }, [ POWER9_PME_PM_LSU0_ERAT_HIT ] = { .pme_name = "PM_LSU0_ERAT_HIT", .pme_code = 0x000000E08C, .pme_short_desc = "Primary ERAT hit.", .pme_long_desc = "Primary ERAT hit. There is no secondary ERAT", }, [ POWER9_PME_PM_LSU0_FALSE_LHS ] = { .pme_name = "PM_LSU0_FALSE_LHS", .pme_code = 0x000000C0A0, .pme_short_desc = "False LHS match detected", .pme_long_desc = "False LHS match detected", }, [ POWER9_PME_PM_LSU0_L1_CAM_CANCEL ] = { .pme_name = "PM_LSU0_L1_CAM_CANCEL", .pme_code = 0x000000F090, .pme_short_desc = "ls0 l1 tm cam cancel", .pme_long_desc = "ls0 l1 tm cam cancel", }, [ POWER9_PME_PM_LSU0_LDMX_FIN ] = { .pme_name = "PM_LSU0_LDMX_FIN", .pme_code = 0x000000D088, .pme_short_desc = "New P9 instruction LDMX.", .pme_long_desc = "New P9 instruction LDMX. The definition of this new PMU event is (from the ldmx RFC02491): The thread has executed an ldmx instruction that accessed a doubleword that contains an effective address within an enabled section of the Load Monitored region. This event, therefore, should not occur if the FSCR has disabled the load monitored facility (FSCR[52]) or disabled the EBB facility (FSCR[56]).", }, [ POWER9_PME_PM_LSU0_LMQ_S0_VALID ] = { .pme_name = "PM_LSU0_LMQ_S0_VALID", .pme_code = 0x000000D8B8, .pme_short_desc = "Slot 0 of LMQ valid", .pme_long_desc = "Slot 0 of LMQ valid", }, [ POWER9_PME_PM_LSU0_LRQ_S0_VALID_CYC ] = { .pme_name = "PM_LSU0_LRQ_S0_VALID_CYC", .pme_code = 0x000000D8B4, .pme_short_desc = "Slot 0 of LRQ valid", .pme_long_desc = "Slot 0 of LRQ valid", }, [ POWER9_PME_PM_LSU0_SET_MPRED ] = { .pme_name = "PM_LSU0_SET_MPRED", .pme_code = 0x000000D080, .pme_short_desc = "Set prediction(set-p) miss.", .pme_long_desc = "Set prediction(set-p) miss. The entry was not found in the Set prediction table", }, [ POWER9_PME_PM_LSU0_SRQ_S0_VALID_CYC ] = { .pme_name = "PM_LSU0_SRQ_S0_VALID_CYC", .pme_code = 0x000000D0B4, .pme_short_desc = "Slot 0 of SRQ valid", .pme_long_desc = "Slot 0 of SRQ valid", }, [ POWER9_PME_PM_LSU0_STORE_REJECT ] = { .pme_name = "PM_LSU0_STORE_REJECT", .pme_code = 0x000000F088, .pme_short_desc = "All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up to try again after the condition has been met", .pme_long_desc = "All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up to try again after the condition has been met", }, [ POWER9_PME_PM_LSU0_TM_L1_HIT ] = { .pme_name = "PM_LSU0_TM_L1_HIT", .pme_code = 0x000000E094, .pme_short_desc = "Load tm hit in L1", .pme_long_desc = "Load tm hit in L1", }, [ POWER9_PME_PM_LSU0_TM_L1_MISS ] = { .pme_name = "PM_LSU0_TM_L1_MISS", .pme_code = 0x000000E09C, .pme_short_desc = "Load tm L1 miss", .pme_long_desc = "Load tm L1 miss", }, [ POWER9_PME_PM_LSU1_ERAT_HIT ] = { .pme_name = "PM_LSU1_ERAT_HIT", .pme_code = 0x000000E88C, .pme_short_desc = "Primary ERAT hit.", .pme_long_desc = "Primary ERAT hit. There is no secondary ERAT", }, [ POWER9_PME_PM_LSU1_FALSE_LHS ] = { .pme_name = "PM_LSU1_FALSE_LHS", .pme_code = 0x000000C8A0, .pme_short_desc = "False LHS match detected", .pme_long_desc = "False LHS match detected", }, [ POWER9_PME_PM_LSU1_L1_CAM_CANCEL ] = { .pme_name = "PM_LSU1_L1_CAM_CANCEL", .pme_code = 0x000000F890, .pme_short_desc = "ls1 l1 tm cam cancel", .pme_long_desc = "ls1 l1 tm cam cancel", }, [ POWER9_PME_PM_LSU1_LDMX_FIN ] = { .pme_name = "PM_LSU1_LDMX_FIN", .pme_code = 0x000000D888, .pme_short_desc = "New P9 instruction LDMX.", .pme_long_desc = "New P9 instruction LDMX. The definition of this new PMU event is (from the ldmx RFC02491): The thread has executed an ldmx instruction that accessed a doubleword that contains an effective address within an enabled section of the Load Monitored region. This event, therefore, should not occur if the FSCR has disabled the load monitored facility (FSCR[52]) or disabled the EBB facility (FSCR[56]).", }, [ POWER9_PME_PM_LSU1_SET_MPRED ] = { .pme_name = "PM_LSU1_SET_MPRED", .pme_code = 0x000000D880, .pme_short_desc = "Set prediction(set-p) miss.", .pme_long_desc = "Set prediction(set-p) miss. The entry was not found in the Set prediction table", }, [ POWER9_PME_PM_LSU1_STORE_REJECT ] = { .pme_name = "PM_LSU1_STORE_REJECT", .pme_code = 0x000000F888, .pme_short_desc = "All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up to try again after the condition has been met", .pme_long_desc = "All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up to try again after the condition has been met", }, [ POWER9_PME_PM_LSU1_TM_L1_HIT ] = { .pme_name = "PM_LSU1_TM_L1_HIT", .pme_code = 0x000000E894, .pme_short_desc = "Load tm hit in L1", .pme_long_desc = "Load tm hit in L1", }, [ POWER9_PME_PM_LSU1_TM_L1_MISS ] = { .pme_name = "PM_LSU1_TM_L1_MISS", .pme_code = 0x000000E89C, .pme_short_desc = "Load tm L1 miss", .pme_long_desc = "Load tm L1 miss", }, [ POWER9_PME_PM_LSU2_3_LRQF_FULL_CYC ] = { .pme_name = "PM_LSU2_3_LRQF_FULL_CYC", .pme_code = 0x000000D8BC, .pme_short_desc = "Counts the number of cycles the LRQF is full.", .pme_long_desc = "Counts the number of cycles the LRQF is full. LRQF is the queue that holds loads between finish and completion. If it fills up, instructions stay in LRQ until completion, potentially backing up the LRQ", }, [ POWER9_PME_PM_LSU2_ERAT_HIT ] = { .pme_name = "PM_LSU2_ERAT_HIT", .pme_code = 0x000000E090, .pme_short_desc = "Primary ERAT hit.", .pme_long_desc = "Primary ERAT hit. There is no secondary ERAT", }, [ POWER9_PME_PM_LSU2_FALSE_LHS ] = { .pme_name = "PM_LSU2_FALSE_LHS", .pme_code = 0x000000C0A4, .pme_short_desc = "False LHS match detected", .pme_long_desc = "False LHS match detected", }, [ POWER9_PME_PM_LSU2_L1_CAM_CANCEL ] = { .pme_name = "PM_LSU2_L1_CAM_CANCEL", .pme_code = 0x000000F094, .pme_short_desc = "ls2 l1 tm cam cancel", .pme_long_desc = "ls2 l1 tm cam cancel", }, [ POWER9_PME_PM_LSU2_LDMX_FIN ] = { .pme_name = "PM_LSU2_LDMX_FIN", .pme_code = 0x000000D08C, .pme_short_desc = "New P9 instruction LDMX.", .pme_long_desc = "New P9 instruction LDMX. The definition of this new PMU event is (from the ldmx RFC02491): The thread has executed an ldmx instruction that accessed a doubleword that contains an effective address within an enabled section of the Load Monitored region. This event, therefore, should not occur if the FSCR has disabled the load monitored facility (FSCR[52]) or disabled the EBB facility (FSCR[56]).", }, [ POWER9_PME_PM_LSU2_SET_MPRED ] = { .pme_name = "PM_LSU2_SET_MPRED", .pme_code = 0x000000D084, .pme_short_desc = "Set prediction(set-p) miss.", .pme_long_desc = "Set prediction(set-p) miss. The entry was not found in the Set prediction table", }, [ POWER9_PME_PM_LSU2_STORE_REJECT ] = { .pme_name = "PM_LSU2_STORE_REJECT", .pme_code = 0x000000F08C, .pme_short_desc = "All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up to try again after the condition has been met", .pme_long_desc = "All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up to try again after the condition has been met", }, [ POWER9_PME_PM_LSU2_TM_L1_HIT ] = { .pme_name = "PM_LSU2_TM_L1_HIT", .pme_code = 0x000000E098, .pme_short_desc = "Load tm hit in L1", .pme_long_desc = "Load tm hit in L1", }, [ POWER9_PME_PM_LSU2_TM_L1_MISS ] = { .pme_name = "PM_LSU2_TM_L1_MISS", .pme_code = 0x000000E0A0, .pme_short_desc = "Load tm L1 miss", .pme_long_desc = "Load tm L1 miss", }, [ POWER9_PME_PM_LSU3_ERAT_HIT ] = { .pme_name = "PM_LSU3_ERAT_HIT", .pme_code = 0x000000E890, .pme_short_desc = "Primary ERAT hit.", .pme_long_desc = "Primary ERAT hit. There is no secondary ERAT", }, [ POWER9_PME_PM_LSU3_FALSE_LHS ] = { .pme_name = "PM_LSU3_FALSE_LHS", .pme_code = 0x000000C8A4, .pme_short_desc = "False LHS match detected", .pme_long_desc = "False LHS match detected", }, [ POWER9_PME_PM_LSU3_L1_CAM_CANCEL ] = { .pme_name = "PM_LSU3_L1_CAM_CANCEL", .pme_code = 0x000000F894, .pme_short_desc = "ls3 l1 tm cam cancel", .pme_long_desc = "ls3 l1 tm cam cancel", }, [ POWER9_PME_PM_LSU3_LDMX_FIN ] = { .pme_name = "PM_LSU3_LDMX_FIN", .pme_code = 0x000000D88C, .pme_short_desc = "New P9 instruction LDMX.", .pme_long_desc = "New P9 instruction LDMX. The definition of this new PMU event is (from the ldmx RFC02491): The thread has executed an ldmx instruction that accessed a doubleword that contains an effective address within an enabled section of the Load Monitored region. This event, therefore, should not occur if the FSCR has disabled the load monitored facility (FSCR[52]) or disabled the EBB facility (FSCR[56]).", }, [ POWER9_PME_PM_LSU3_SET_MPRED ] = { .pme_name = "PM_LSU3_SET_MPRED", .pme_code = 0x000000D884, .pme_short_desc = "Set prediction(set-p) miss.", .pme_long_desc = "Set prediction(set-p) miss. The entry was not found in the Set prediction table", }, [ POWER9_PME_PM_LSU3_STORE_REJECT ] = { .pme_name = "PM_LSU3_STORE_REJECT", .pme_code = 0x000000F88C, .pme_short_desc = "All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up to try again after the condition has been met", .pme_long_desc = "All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up to try again after the condition has been met", }, [ POWER9_PME_PM_LSU3_TM_L1_HIT ] = { .pme_name = "PM_LSU3_TM_L1_HIT", .pme_code = 0x000000E898, .pme_short_desc = "Load tm hit in L1", .pme_long_desc = "Load tm hit in L1", }, [ POWER9_PME_PM_LSU3_TM_L1_MISS ] = { .pme_name = "PM_LSU3_TM_L1_MISS", .pme_code = 0x000000E8A0, .pme_short_desc = "Load tm L1 miss", .pme_long_desc = "Load tm L1 miss", }, [ POWER9_PME_PM_LSU_DERAT_MISS ] = { .pme_name = "PM_LSU_DERAT_MISS", .pme_code = 0x00000200F6, .pme_short_desc = "DERAT Reloaded due to a DERAT miss", .pme_long_desc = "DERAT Reloaded due to a DERAT miss", }, [ POWER9_PME_PM_LSU_FIN ] = { .pme_name = "PM_LSU_FIN", .pme_code = 0x0000030066, .pme_short_desc = "LSU Finished a PPC instruction (up to 4 per cycle)", .pme_long_desc = "LSU Finished a PPC instruction (up to 4 per cycle)", }, [ POWER9_PME_PM_LSU_FLUSH_ATOMIC ] = { .pme_name = "PM_LSU_FLUSH_ATOMIC", .pme_code = 0x000000C8A8, .pme_short_desc = "Quad-word loads (lq) are considered atomic because they always span at least 2 slices.", .pme_long_desc = "Quad-word loads (lq) are considered atomic because they always span at least 2 slices. If a snoop or store from another thread changes the data the load is accessing between the 2 or 3 pieces of the lq instruction, the lq will be flushed", }, [ POWER9_PME_PM_LSU_FLUSH_CI ] = { .pme_name = "PM_LSU_FLUSH_CI", .pme_code = 0x000000C0A8, .pme_short_desc = "Load was not issued to LSU as a cache inhibited (non-cacheable) load but it was later determined to be cache inhibited", .pme_long_desc = "Load was not issued to LSU as a cache inhibited (non-cacheable) load but it was later determined to be cache inhibited", }, [ POWER9_PME_PM_LSU_FLUSH_EMSH ] = { .pme_name = "PM_LSU_FLUSH_EMSH", .pme_code = 0x000000C0AC, .pme_short_desc = "An ERAT miss was detected after a set-p hit.", .pme_long_desc = "An ERAT miss was detected after a set-p hit. Erat tracker indicates fail due to tlbmiss and the instruction gets flushed because the instruction was working on the wrong address", }, [ POWER9_PME_PM_LSU_FLUSH_LARX_STCX ] = { .pme_name = "PM_LSU_FLUSH_LARX_STCX", .pme_code = 0x000000C8B8, .pme_short_desc = "A larx is flushed because an older larx has an LMQ reservation for the same thread.", .pme_long_desc = "A larx is flushed because an older larx has an LMQ reservation for the same thread. A stcx is flushed because an older stcx is in the LMQ. The flush happens when the older larx/stcx relaunches", }, [ POWER9_PME_PM_LSU_FLUSH_LHL_SHL ] = { .pme_name = "PM_LSU_FLUSH_LHL_SHL", .pme_code = 0x000000C8B4, .pme_short_desc = "The instruction was flushed because of a sequential load/store consistency.", .pme_long_desc = "The instruction was flushed because of a sequential load/store consistency. If a load or store hits on an older load that has either been snooped (for loads) or has stale data (for stores).", }, [ POWER9_PME_PM_LSU_FLUSH_LHS ] = { .pme_name = "PM_LSU_FLUSH_LHS", .pme_code = 0x000000C8B0, .pme_short_desc = "Effective Address alias flush : no EA match but Real Address match.", .pme_long_desc = "Effective Address alias flush : no EA match but Real Address match. If the data has not yet been returned for this load, the instruction will just be rejected, but if it has returned data, it will be flushed", }, [ POWER9_PME_PM_LSU_FLUSH_NEXT ] = { .pme_name = "PM_LSU_FLUSH_NEXT", .pme_code = 0x00000020B0, .pme_short_desc = "LSU flush next reported at flush time.", .pme_long_desc = "LSU flush next reported at flush time. Sometimes these also come with an exception", }, [ POWER9_PME_PM_LSU_FLUSH_OTHER ] = { .pme_name = "PM_LSU_FLUSH_OTHER", .pme_code = 0x000000C0BC, .pme_short_desc = "Other LSU flushes including: Sync (sync ack from L2 caused search of LRQ for oldest snooped load, This will either signal a Precise Flush of the oldest snooped loa or a Flush Next PPC); Data Valid Flush Next (several cases of this, one example is store and reload are lined up such that a store-hit-reload scenario exists and the CDF has already launched and has gotten bad/stale data); Bad Data Valid Flush Next (might be a few cases of this, one example is a larxa (D$ hit) return data and dval but can't allocate to LMQ (LMQ full or other reason).", .pme_long_desc = "Other LSU flushes including: Sync (sync ack from L2 caused search of LRQ for oldest snooped load, This will either signal a Precise Flush of the oldest snooped loa or a Flush Next PPC); Data Valid Flush Next (several cases of this, one example is store and reload are lined up such that a store-hit-reload scenario exists and the CDF has already launched and has gotten bad/stale data); Bad Data Valid Flush Next (might be a few cases of this, one example is a larxa (D$ hit) return data and dval but can't allocate to LMQ (LMQ full or other reason). Already gave dval but can't watch it for snoop_hit_larx. Need to take the “bad dval” back and flush all younger ops)", }, [ POWER9_PME_PM_LSU_FLUSH_RELAUNCH_MISS ] = { .pme_name = "PM_LSU_FLUSH_RELAUNCH_MISS", .pme_code = 0x000000C8AC, .pme_short_desc = "If a load that has already returned data and has to relaunch for any reason then gets a miss (erat, setp, data cache), it will often be flushed at relaunch time because the data might be inconsistent", .pme_long_desc = "If a load that has already returned data and has to relaunch for any reason then gets a miss (erat, setp, data cache), it will often be flushed at relaunch time because the data might be inconsistent", }, [ POWER9_PME_PM_LSU_FLUSH_SAO ] = { .pme_name = "PM_LSU_FLUSH_SAO", .pme_code = 0x000000C0B8, .pme_short_desc = "A load-hit-load condition with Strong Address Ordering will have address compare disabled and flush", .pme_long_desc = "A load-hit-load condition with Strong Address Ordering will have address compare disabled and flush", }, [ POWER9_PME_PM_LSU_FLUSH_UE ] = { .pme_name = "PM_LSU_FLUSH_UE", .pme_code = 0x000000C0B0, .pme_short_desc = "Correctable ECC error on reload data, reported at critical data forward time", .pme_long_desc = "Correctable ECC error on reload data, reported at critical data forward time", }, [ POWER9_PME_PM_LSU_FLUSH_WRK_ARND ] = { .pme_name = "PM_LSU_FLUSH_WRK_ARND", .pme_code = 0x000000C0B4, .pme_short_desc = "LSU workaround flush.", .pme_long_desc = "LSU workaround flush. These flushes are setup with programmable scan only latches to perform various actions when the flush macro receives a trigger from the dbg macros. These actions include things like flushing the next op encountered for a particular thread or flushing the next op that is NTC op that is encountered on a particular slice. The kind of flush that the workaround is setup to perform is highly variable.", }, [ POWER9_PME_PM_LSU_LMQ_FULL_CYC ] = { .pme_name = "PM_LSU_LMQ_FULL_CYC", .pme_code = 0x000000D0B8, .pme_short_desc = "Counts the number of cycles the LMQ is full", .pme_long_desc = "Counts the number of cycles the LMQ is full", }, [ POWER9_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC ] = { .pme_name = "PM_LSU_LMQ_SRQ_EMPTY_CYC", .pme_code = 0x000002003E, .pme_short_desc = "Cycles in which the LSU is empty for all threads (lmq and srq are completely empty)", .pme_long_desc = "Cycles in which the LSU is empty for all threads (lmq and srq are completely empty)", }, [ POWER9_PME_PM_LSU_NCST ] = { .pme_name = "PM_LSU_NCST", .pme_code = 0x000000C890, .pme_short_desc = "Asserts when a i=1 store op is sent to the nest.", .pme_long_desc = "Asserts when a i=1 store op is sent to the nest. No record of issue pipe (LS0/LS1) is maintained so this is for both pipes. Probably don't need separate LS0 and LS1", }, [ POWER9_PME_PM_LSU_REJECT_ERAT_MISS ] = { .pme_name = "PM_LSU_REJECT_ERAT_MISS", .pme_code = 0x000002E05C, .pme_short_desc = "LSU Reject due to ERAT (up to 4 per cycles)", .pme_long_desc = "LSU Reject due to ERAT (up to 4 per cycles)", }, [ POWER9_PME_PM_LSU_REJECT_LHS ] = { .pme_name = "PM_LSU_REJECT_LHS", .pme_code = 0x000004E05C, .pme_short_desc = "LSU Reject due to LHS (up to 4 per cycle)", .pme_long_desc = "LSU Reject due to LHS (up to 4 per cycle)", }, [ POWER9_PME_PM_LSU_REJECT_LMQ_FULL ] = { .pme_name = "PM_LSU_REJECT_LMQ_FULL", .pme_code = 0x000003001C, .pme_short_desc = "LSU Reject due to LMQ full (up to 4 per cycles)", .pme_long_desc = "LSU Reject due to LMQ full (up to 4 per cycles)", }, [ POWER9_PME_PM_LSU_SRQ_FULL_CYC ] = { .pme_name = "PM_LSU_SRQ_FULL_CYC", .pme_code = 0x000001001A, .pme_short_desc = "Cycles in which the Store Queue is full on all 4 slices.", .pme_long_desc = "Cycles in which the Store Queue is full on all 4 slices. This is event is not per thread. All the threads will see the same count for this core resource", }, [ POWER9_PME_PM_LSU_STCX_FAIL ] = { .pme_name = "PM_LSU_STCX_FAIL", .pme_code = 0x000000F080, .pme_short_desc = "", .pme_long_desc = "", }, [ POWER9_PME_PM_LSU_STCX ] = { .pme_name = "PM_LSU_STCX", .pme_code = 0x000000C090, .pme_short_desc = "STCX sent to nest, i.", .pme_long_desc = "STCX sent to nest, i.e. total", }, [ POWER9_PME_PM_LWSYNC ] = { .pme_name = "PM_LWSYNC", .pme_code = 0x0000005894, .pme_short_desc = "Lwsync instruction decoded and transferred", .pme_long_desc = "Lwsync instruction decoded and transferred", }, [ POWER9_PME_PM_MATH_FLOP_CMPL ] = { .pme_name = "PM_MATH_FLOP_CMPL", .pme_code = 0x000004505C, .pme_short_desc = "Math flop instruction completed", .pme_long_desc = "Math flop instruction completed", }, [ POWER9_PME_PM_MEM_CO ] = { .pme_name = "PM_MEM_CO", .pme_code = 0x000004C058, .pme_short_desc = "Memory castouts from this thread", .pme_long_desc = "Memory castouts from this thread", }, [ POWER9_PME_PM_MEM_LOC_THRESH_IFU ] = { .pme_name = "PM_MEM_LOC_THRESH_IFU", .pme_code = 0x0000010058, .pme_short_desc = "Local Memory above threshold for IFU speculation control", .pme_long_desc = "Local Memory above threshold for IFU speculation control", }, [ POWER9_PME_PM_MEM_LOC_THRESH_LSU_HIGH ] = { .pme_name = "PM_MEM_LOC_THRESH_LSU_HIGH", .pme_code = 0x0000040056, .pme_short_desc = "Local memory above threshold for LSU medium", .pme_long_desc = "Local memory above threshold for LSU medium", }, [ POWER9_PME_PM_MEM_LOC_THRESH_LSU_MED ] = { .pme_name = "PM_MEM_LOC_THRESH_LSU_MED", .pme_code = 0x000001C05E, .pme_short_desc = "Local memory above threshold for data prefetch", .pme_long_desc = "Local memory above threshold for data prefetch", }, [ POWER9_PME_PM_MEM_PREF ] = { .pme_name = "PM_MEM_PREF", .pme_code = 0x000002C058, .pme_short_desc = "Memory prefetch for this thread.", .pme_long_desc = "Memory prefetch for this thread. Includes L4", }, [ POWER9_PME_PM_MEM_READ ] = { .pme_name = "PM_MEM_READ", .pme_code = 0x0000010056, .pme_short_desc = "Reads from Memory from this thread (includes data/inst/xlate/l1prefetch/inst prefetch).", .pme_long_desc = "Reads from Memory from this thread (includes data/inst/xlate/l1prefetch/inst prefetch). Includes L4", }, [ POWER9_PME_PM_MEM_RWITM ] = { .pme_name = "PM_MEM_RWITM", .pme_code = 0x000003C05E, .pme_short_desc = "Memory Read With Intent to Modify for this thread", .pme_long_desc = "Memory Read With Intent to Modify for this thread", }, [ POWER9_PME_PM_MRK_BACK_BR_CMPL ] = { .pme_name = "PM_MRK_BACK_BR_CMPL", .pme_code = 0x000003515E, .pme_short_desc = "Marked branch instruction completed with a target address less than current instruction address", .pme_long_desc = "Marked branch instruction completed with a target address less than current instruction address", }, [ POWER9_PME_PM_MRK_BR_2PATH ] = { .pme_name = "PM_MRK_BR_2PATH", .pme_code = 0x0000010138, .pme_short_desc = "marked branches which are not strongly biased", .pme_long_desc = "marked branches which are not strongly biased", }, [ POWER9_PME_PM_MRK_BR_CMPL ] = { .pme_name = "PM_MRK_BR_CMPL", .pme_code = 0x000001016E, .pme_short_desc = "Branch Instruction completed", .pme_long_desc = "Branch Instruction completed", }, [ POWER9_PME_PM_MRK_BR_MPRED_CMPL ] = { .pme_name = "PM_MRK_BR_MPRED_CMPL", .pme_code = 0x00000301E4, .pme_short_desc = "Marked Branch Mispredicted", .pme_long_desc = "Marked Branch Mispredicted", }, [ POWER9_PME_PM_MRK_BR_TAKEN_CMPL ] = { .pme_name = "PM_MRK_BR_TAKEN_CMPL", .pme_code = 0x00000101E2, .pme_short_desc = "Marked Branch Taken completed", .pme_long_desc = "Marked Branch Taken completed", }, [ POWER9_PME_PM_MRK_BRU_FIN ] = { .pme_name = "PM_MRK_BRU_FIN", .pme_code = 0x000002013A, .pme_short_desc = "bru marked instr finish", .pme_long_desc = "bru marked instr finish", }, [ POWER9_PME_PM_MRK_DATA_FROM_DL2L3_MOD_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_DL2L3_MOD_CYC", .pme_code = 0x000004D12E, .pme_short_desc = "Duration in cycles to reload with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load", .pme_long_desc = "Duration in cycles to reload with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load", }, [ POWER9_PME_PM_MRK_DATA_FROM_DL2L3_MOD ] = { .pme_name = "PM_MRK_DATA_FROM_DL2L3_MOD", .pme_code = 0x000003D14E, .pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load", .pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load", }, [ POWER9_PME_PM_MRK_DATA_FROM_DL2L3_SHR_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_DL2L3_SHR_CYC", .pme_code = 0x000002C128, .pme_short_desc = "Duration in cycles to reload with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load", .pme_long_desc = "Duration in cycles to reload with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load", }, [ POWER9_PME_PM_MRK_DATA_FROM_DL2L3_SHR ] = { .pme_name = "PM_MRK_DATA_FROM_DL2L3_SHR", .pme_code = 0x000001D150, .pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load", .pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load", }, [ POWER9_PME_PM_MRK_DATA_FROM_DL4_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_DL4_CYC", .pme_code = 0x000002C12C, .pme_short_desc = "Duration in cycles to reload from another chip's L4 on a different Node or Group (Distant) due to a marked load", .pme_long_desc = "Duration in cycles to reload from another chip's L4 on a different Node or Group (Distant) due to a marked load", }, [ POWER9_PME_PM_MRK_DATA_FROM_DL4 ] = { .pme_name = "PM_MRK_DATA_FROM_DL4", .pme_code = 0x000001D152, .pme_short_desc = "The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to a marked load", .pme_long_desc = "The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to a marked load", }, [ POWER9_PME_PM_MRK_DATA_FROM_DMEM_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_DMEM_CYC", .pme_code = 0x000004E11E, .pme_short_desc = "Duration in cycles to reload from another chip's memory on the same Node or Group (Distant) due to a marked load", .pme_long_desc = "Duration in cycles to reload from another chip's memory on the same Node or Group (Distant) due to a marked load", }, [ POWER9_PME_PM_MRK_DATA_FROM_DMEM ] = { .pme_name = "PM_MRK_DATA_FROM_DMEM", .pme_code = 0x000003D14C, .pme_short_desc = "The processor's data cache was reloaded from another chip's memory on the same Node or Group (Distant) due to a marked load", .pme_long_desc = "The processor's data cache was reloaded from another chip's memory on the same Node or Group (Distant) due to a marked load", }, [ POWER9_PME_PM_MRK_DATA_FROM_L21_MOD_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L21_MOD_CYC", .pme_code = 0x000003D148, .pme_short_desc = "Duration in cycles to reload with Modified (M) data from another core's L2 on the same chip due to a marked load", .pme_long_desc = "Duration in cycles to reload with Modified (M) data from another core's L2 on the same chip due to a marked load", }, [ POWER9_PME_PM_MRK_DATA_FROM_L21_MOD ] = { .pme_name = "PM_MRK_DATA_FROM_L21_MOD", .pme_code = 0x000004D146, .pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another core's L2 on the same chip due to a marked load", .pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another core's L2 on the same chip due to a marked load", }, [ POWER9_PME_PM_MRK_DATA_FROM_L21_SHR_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L21_SHR_CYC", .pme_code = 0x000001D154, .pme_short_desc = "Duration in cycles to reload with Shared (S) data from another core's L2 on the same chip due to a marked load", .pme_long_desc = "Duration in cycles to reload with Shared (S) data from another core's L2 on the same chip due to a marked load", }, [ POWER9_PME_PM_MRK_DATA_FROM_L21_SHR ] = { .pme_name = "PM_MRK_DATA_FROM_L21_SHR", .pme_code = 0x000002D14E, .pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to a marked load", .pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to a marked load", }, [ POWER9_PME_PM_MRK_DATA_FROM_L2_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L2_CYC", .pme_code = 0x0000014156, .pme_short_desc = "Duration in cycles to reload from local core's L2 due to a marked load", .pme_long_desc = "Duration in cycles to reload from local core's L2 due to a marked load", }, [ POWER9_PME_PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST_CYC", .pme_code = 0x000001415A, .pme_short_desc = "Duration in cycles to reload from local core's L2 with load hit store conflict due to a marked load", .pme_long_desc = "Duration in cycles to reload from local core's L2 with load hit store conflict due to a marked load", }, [ POWER9_PME_PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST ] = { .pme_name = "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST", .pme_code = 0x000002D148, .pme_short_desc = "The processor's data cache was reloaded from local core's L2 with load hit store conflict due to a marked load", .pme_long_desc = "The processor's data cache was reloaded from local core's L2 with load hit store conflict due to a marked load", }, [ POWER9_PME_PM_MRK_DATA_FROM_L2_DISP_CONFLICT_OTHER_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_OTHER_CYC", .pme_code = 0x000003D140, .pme_short_desc = "Duration in cycles to reload from local core's L2 with dispatch conflict due to a marked load", .pme_long_desc = "Duration in cycles to reload from local core's L2 with dispatch conflict due to a marked load", }, [ POWER9_PME_PM_MRK_DATA_FROM_L2_DISP_CONFLICT_OTHER ] = { .pme_name = "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_OTHER", .pme_code = 0x000002C124, .pme_short_desc = "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to a marked load", .pme_long_desc = "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to a marked load", }, [ POWER9_PME_PM_MRK_DATA_FROM_L2_MEPF_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L2_MEPF_CYC", .pme_code = 0x000003D144, .pme_short_desc = "Duration in cycles to reload from local core's L2 hit without dispatch conflicts on Mepf state.", .pme_long_desc = "Duration in cycles to reload from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked load", }, [ POWER9_PME_PM_MRK_DATA_FROM_L2_MEPF ] = { .pme_name = "PM_MRK_DATA_FROM_L2_MEPF", .pme_code = 0x000004C120, .pme_short_desc = "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state.", .pme_long_desc = "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked load", }, [ POWER9_PME_PM_MRK_DATA_FROM_L2MISS_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L2MISS_CYC", .pme_code = 0x0000035152, .pme_short_desc = "Duration in cycles to reload from a location other than the local core's L2 due to a marked load", .pme_long_desc = "Duration in cycles to reload from a location other than the local core's L2 due to a marked load", }, [ POWER9_PME_PM_MRK_DATA_FROM_L2MISS ] = { .pme_name = "PM_MRK_DATA_FROM_L2MISS", .pme_code = 0x00000401E8, .pme_short_desc = "The processor's data cache was reloaded from a location other than the local core's L2 due to a marked load", .pme_long_desc = "The processor's data cache was reloaded from a location other than the local core's L2 due to a marked load", }, [ POWER9_PME_PM_MRK_DATA_FROM_L2_NO_CONFLICT_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L2_NO_CONFLICT_CYC", .pme_code = 0x0000014158, .pme_short_desc = "Duration in cycles to reload from local core's L2 without conflict due to a marked load", .pme_long_desc = "Duration in cycles to reload from local core's L2 without conflict due to a marked load", }, [ POWER9_PME_PM_MRK_DATA_FROM_L2_NO_CONFLICT ] = { .pme_name = "PM_MRK_DATA_FROM_L2_NO_CONFLICT", .pme_code = 0x000002C120, .pme_short_desc = "The processor's data cache was reloaded from local core's L2 without conflict due to a marked load", .pme_long_desc = "The processor's data cache was reloaded from local core's L2 without conflict due to a marked load", }, [ POWER9_PME_PM_MRK_DATA_FROM_L2 ] = { .pme_name = "PM_MRK_DATA_FROM_L2", .pme_code = 0x000002C126, .pme_short_desc = "The processor's data cache was reloaded from local core's L2 due to a marked load", .pme_long_desc = "The processor's data cache was reloaded from local core's L2 due to a marked load", }, [ POWER9_PME_PM_MRK_DATA_FROM_L31_ECO_MOD_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L31_ECO_MOD_CYC", .pme_code = 0x0000035158, .pme_short_desc = "Duration in cycles to reload with Modified (M) data from another core's ECO L3 on the same chip due to a marked load", .pme_long_desc = "Duration in cycles to reload with Modified (M) data from another core's ECO L3 on the same chip due to a marked load", }, [ POWER9_PME_PM_MRK_DATA_FROM_L31_ECO_MOD ] = { .pme_name = "PM_MRK_DATA_FROM_L31_ECO_MOD", .pme_code = 0x000004D144, .pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to a marked load", .pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to a marked load", }, [ POWER9_PME_PM_MRK_DATA_FROM_L31_ECO_SHR_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L31_ECO_SHR_CYC", .pme_code = 0x000001D142, .pme_short_desc = "Duration in cycles to reload with Shared (S) data from another core's ECO L3 on the same chip due to a marked load", .pme_long_desc = "Duration in cycles to reload with Shared (S) data from another core's ECO L3 on the same chip due to a marked load", }, [ POWER9_PME_PM_MRK_DATA_FROM_L31_ECO_SHR ] = { .pme_name = "PM_MRK_DATA_FROM_L31_ECO_SHR", .pme_code = 0x000002D14C, .pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to a marked load", .pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to a marked load", }, [ POWER9_PME_PM_MRK_DATA_FROM_L31_MOD_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L31_MOD_CYC", .pme_code = 0x000001D140, .pme_short_desc = "Duration in cycles to reload with Modified (M) data from another core's L3 on the same chip due to a marked load", .pme_long_desc = "Duration in cycles to reload with Modified (M) data from another core's L3 on the same chip due to a marked load", }, [ POWER9_PME_PM_MRK_DATA_FROM_L31_MOD ] = { .pme_name = "PM_MRK_DATA_FROM_L31_MOD", .pme_code = 0x000002D144, .pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another core's L3 on the same chip due to a marked load", .pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another core's L3 on the same chip due to a marked load", }, [ POWER9_PME_PM_MRK_DATA_FROM_L31_SHR_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L31_SHR_CYC", .pme_code = 0x0000035156, .pme_short_desc = "Duration in cycles to reload with Shared (S) data from another core's L3 on the same chip due to a marked load", .pme_long_desc = "Duration in cycles to reload with Shared (S) data from another core's L3 on the same chip due to a marked load", }, [ POWER9_PME_PM_MRK_DATA_FROM_L31_SHR ] = { .pme_name = "PM_MRK_DATA_FROM_L31_SHR", .pme_code = 0x000004D124, .pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another core's L3 on the same chip due to a marked load", .pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another core's L3 on the same chip due to a marked load", }, [ POWER9_PME_PM_MRK_DATA_FROM_L3_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L3_CYC", .pme_code = 0x0000035154, .pme_short_desc = "Duration in cycles to reload from local core's L3 due to a marked load", .pme_long_desc = "Duration in cycles to reload from local core's L3 due to a marked load", }, [ POWER9_PME_PM_MRK_DATA_FROM_L3_DISP_CONFLICT_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L3_DISP_CONFLICT_CYC", .pme_code = 0x000002C122, .pme_short_desc = "Duration in cycles to reload from local core's L3 with dispatch conflict due to a marked load", .pme_long_desc = "Duration in cycles to reload from local core's L3 with dispatch conflict due to a marked load", }, [ POWER9_PME_PM_MRK_DATA_FROM_L3_DISP_CONFLICT ] = { .pme_name = "PM_MRK_DATA_FROM_L3_DISP_CONFLICT", .pme_code = 0x000001D144, .pme_short_desc = "The processor's data cache was reloaded from local core's L3 with dispatch conflict due to a marked load", .pme_long_desc = "The processor's data cache was reloaded from local core's L3 with dispatch conflict due to a marked load", }, [ POWER9_PME_PM_MRK_DATA_FROM_L3_MEPF_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L3_MEPF_CYC", .pme_code = 0x000001415C, .pme_short_desc = "Duration in cycles to reload from local core's L3 without dispatch conflicts hit on Mepf state due to a marked load", .pme_long_desc = "Duration in cycles to reload from local core's L3 without dispatch conflicts hit on Mepf state due to a marked load", }, [ POWER9_PME_PM_MRK_DATA_FROM_L3_MEPF ] = { .pme_name = "PM_MRK_DATA_FROM_L3_MEPF", .pme_code = 0x000002D142, .pme_short_desc = "The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state.", .pme_long_desc = "The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked load", }, [ POWER9_PME_PM_MRK_DATA_FROM_L3MISS_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L3MISS_CYC", .pme_code = 0x000001415E, .pme_short_desc = "Duration in cycles to reload from a location other than the local core's L3 due to a marked load", .pme_long_desc = "Duration in cycles to reload from a location other than the local core's L3 due to a marked load", }, [ POWER9_PME_PM_MRK_DATA_FROM_L3MISS ] = { .pme_name = "PM_MRK_DATA_FROM_L3MISS", .pme_code = 0x00000201E4, .pme_short_desc = "The processor's data cache was reloaded from a location other than the local core's L3 due to a marked load", .pme_long_desc = "The processor's data cache was reloaded from a location other than the local core's L3 due to a marked load", }, [ POWER9_PME_PM_MRK_DATA_FROM_L3_NO_CONFLICT_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L3_NO_CONFLICT_CYC", .pme_code = 0x000004C124, .pme_short_desc = "Duration in cycles to reload from local core's L3 without conflict due to a marked load", .pme_long_desc = "Duration in cycles to reload from local core's L3 without conflict due to a marked load", }, [ POWER9_PME_PM_MRK_DATA_FROM_L3_NO_CONFLICT ] = { .pme_name = "PM_MRK_DATA_FROM_L3_NO_CONFLICT", .pme_code = 0x000003D146, .pme_short_desc = "The processor's data cache was reloaded from local core's L3 without conflict due to a marked load", .pme_long_desc = "The processor's data cache was reloaded from local core's L3 without conflict due to a marked load", }, [ POWER9_PME_PM_MRK_DATA_FROM_L3 ] = { .pme_name = "PM_MRK_DATA_FROM_L3", .pme_code = 0x000004D142, .pme_short_desc = "The processor's data cache was reloaded from local core's L3 due to a marked load", .pme_long_desc = "The processor's data cache was reloaded from local core's L3 due to a marked load", }, [ POWER9_PME_PM_MRK_DATA_FROM_LL4_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_LL4_CYC", .pme_code = 0x000002C12E, .pme_short_desc = "Duration in cycles to reload from the local chip's L4 cache due to a marked load", .pme_long_desc = "Duration in cycles to reload from the local chip's L4 cache due to a marked load", }, [ POWER9_PME_PM_MRK_DATA_FROM_LL4 ] = { .pme_name = "PM_MRK_DATA_FROM_LL4", .pme_code = 0x000001D14C, .pme_short_desc = "The processor's data cache was reloaded from the local chip's L4 cache due to a marked load", .pme_long_desc = "The processor's data cache was reloaded from the local chip's L4 cache due to a marked load", }, [ POWER9_PME_PM_MRK_DATA_FROM_LMEM_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_LMEM_CYC", .pme_code = 0x000004D128, .pme_short_desc = "Duration in cycles to reload from the local chip's Memory due to a marked load", .pme_long_desc = "Duration in cycles to reload from the local chip's Memory due to a marked load", }, [ POWER9_PME_PM_MRK_DATA_FROM_LMEM ] = { .pme_name = "PM_MRK_DATA_FROM_LMEM", .pme_code = 0x000003D142, .pme_short_desc = "The processor's data cache was reloaded from the local chip's Memory due to a marked load", .pme_long_desc = "The processor's data cache was reloaded from the local chip's Memory due to a marked load", }, [ POWER9_PME_PM_MRK_DATA_FROM_MEMORY_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_MEMORY_CYC", .pme_code = 0x000001D146, .pme_short_desc = "Duration in cycles to reload from a memory location including L4 from local remote or distant due to a marked load", .pme_long_desc = "Duration in cycles to reload from a memory location including L4 from local remote or distant due to a marked load", }, [ POWER9_PME_PM_MRK_DATA_FROM_MEMORY ] = { .pme_name = "PM_MRK_DATA_FROM_MEMORY", .pme_code = 0x00000201E0, .pme_short_desc = "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a marked load", .pme_long_desc = "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a marked load", }, [ POWER9_PME_PM_MRK_DATA_FROM_OFF_CHIP_CACHE_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_OFF_CHIP_CACHE_CYC", .pme_code = 0x000001D14E, .pme_short_desc = "Duration in cycles to reload either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked load", .pme_long_desc = "Duration in cycles to reload either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked load", }, [ POWER9_PME_PM_MRK_DATA_FROM_OFF_CHIP_CACHE ] = { .pme_name = "PM_MRK_DATA_FROM_OFF_CHIP_CACHE", .pme_code = 0x000002D120, .pme_short_desc = "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked load", .pme_long_desc = "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked load", }, [ POWER9_PME_PM_MRK_DATA_FROM_ON_CHIP_CACHE_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_ON_CHIP_CACHE_CYC", .pme_code = 0x000003515A, .pme_short_desc = "Duration in cycles to reload either shared or modified data from another core's L2/L3 on the same chip due to a marked load", .pme_long_desc = "Duration in cycles to reload either shared or modified data from another core's L2/L3 on the same chip due to a marked load", }, [ POWER9_PME_PM_MRK_DATA_FROM_ON_CHIP_CACHE ] = { .pme_name = "PM_MRK_DATA_FROM_ON_CHIP_CACHE", .pme_code = 0x000004D140, .pme_short_desc = "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to a marked load", .pme_long_desc = "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to a marked load", }, [ POWER9_PME_PM_MRK_DATA_FROM_RL2L3_MOD_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_RL2L3_MOD_CYC", .pme_code = 0x000002D14A, .pme_short_desc = "Duration in cycles to reload with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load", .pme_long_desc = "Duration in cycles to reload with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load", }, [ POWER9_PME_PM_MRK_DATA_FROM_RL2L3_MOD ] = { .pme_name = "PM_MRK_DATA_FROM_RL2L3_MOD", .pme_code = 0x000001D14A, .pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load", .pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load", }, [ POWER9_PME_PM_MRK_DATA_FROM_RL2L3_SHR_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_RL2L3_SHR_CYC", .pme_code = 0x000004C12A, .pme_short_desc = "Duration in cycles to reload with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load", .pme_long_desc = "Duration in cycles to reload with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load", }, [ POWER9_PME_PM_MRK_DATA_FROM_RL2L3_SHR ] = { .pme_name = "PM_MRK_DATA_FROM_RL2L3_SHR", .pme_code = 0x0000035150, .pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load", .pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load", }, [ POWER9_PME_PM_MRK_DATA_FROM_RL4_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_RL4_CYC", .pme_code = 0x000004D12A, .pme_short_desc = "Duration in cycles to reload from another chip's L4 on the same Node or Group ( Remote) due to a marked load", .pme_long_desc = "Duration in cycles to reload from another chip's L4 on the same Node or Group ( Remote) due to a marked load", }, [ POWER9_PME_PM_MRK_DATA_FROM_RL4 ] = { .pme_name = "PM_MRK_DATA_FROM_RL4", .pme_code = 0x000003515C, .pme_short_desc = "The processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to a marked load", .pme_long_desc = "The processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to a marked load", }, [ POWER9_PME_PM_MRK_DATA_FROM_RMEM_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_RMEM_CYC", .pme_code = 0x000002C12A, .pme_short_desc = "Duration in cycles to reload from another chip's memory on the same Node or Group ( Remote) due to a marked load", .pme_long_desc = "Duration in cycles to reload from another chip's memory on the same Node or Group ( Remote) due to a marked load", }, [ POWER9_PME_PM_MRK_DATA_FROM_RMEM ] = { .pme_name = "PM_MRK_DATA_FROM_RMEM", .pme_code = 0x000001D148, .pme_short_desc = "The processor's data cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to a marked load", .pme_long_desc = "The processor's data cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to a marked load", }, [ POWER9_PME_PM_MRK_DCACHE_RELOAD_INTV ] = { .pme_name = "PM_MRK_DCACHE_RELOAD_INTV", .pme_code = 0x0000040118, .pme_short_desc = "Combined Intervention event", .pme_long_desc = "Combined Intervention event", }, [ POWER9_PME_PM_MRK_DERAT_MISS_16G ] = { .pme_name = "PM_MRK_DERAT_MISS_16G", .pme_code = 0x000004C15C, .pme_short_desc = "Marked Data ERAT Miss (Data TLB Access) page size 16G", .pme_long_desc = "Marked Data ERAT Miss (Data TLB Access) page size 16G", }, [ POWER9_PME_PM_MRK_DERAT_MISS_16M ] = { .pme_name = "PM_MRK_DERAT_MISS_16M", .pme_code = 0x000003D154, .pme_short_desc = "Marked Data ERAT Miss (Data TLB Access) page size 16M", .pme_long_desc = "Marked Data ERAT Miss (Data TLB Access) page size 16M", }, [ POWER9_PME_PM_MRK_DERAT_MISS_1G ] = { .pme_name = "PM_MRK_DERAT_MISS_1G", .pme_code = 0x000003D152, .pme_short_desc = "Marked Data ERAT Miss (Data TLB Access) page size 1G.", .pme_long_desc = "Marked Data ERAT Miss (Data TLB Access) page size 1G. Implies radix translation", }, [ POWER9_PME_PM_MRK_DERAT_MISS_2M ] = { .pme_name = "PM_MRK_DERAT_MISS_2M", .pme_code = 0x000002D152, .pme_short_desc = "Marked Data ERAT Miss (Data TLB Access) page size 2M.", .pme_long_desc = "Marked Data ERAT Miss (Data TLB Access) page size 2M. Implies radix translation", }, [ POWER9_PME_PM_MRK_DERAT_MISS_4K ] = { .pme_name = "PM_MRK_DERAT_MISS_4K", .pme_code = 0x000002D150, .pme_short_desc = "Marked Data ERAT Miss (Data TLB Access) page size 4K", .pme_long_desc = "Marked Data ERAT Miss (Data TLB Access) page size 4K", }, [ POWER9_PME_PM_MRK_DERAT_MISS_64K ] = { .pme_name = "PM_MRK_DERAT_MISS_64K", .pme_code = 0x000002D154, .pme_short_desc = "Marked Data ERAT Miss (Data TLB Access) page size 64K", .pme_long_desc = "Marked Data ERAT Miss (Data TLB Access) page size 64K", }, [ POWER9_PME_PM_MRK_DERAT_MISS ] = { .pme_name = "PM_MRK_DERAT_MISS", .pme_code = 0x00000301E6, .pme_short_desc = "Erat Miss (TLB Access) All page sizes", .pme_long_desc = "Erat Miss (TLB Access) All page sizes", }, [ POWER9_PME_PM_MRK_DFU_FIN ] = { .pme_name = "PM_MRK_DFU_FIN", .pme_code = 0x0000020132, .pme_short_desc = "Decimal Unit marked Instruction Finish", .pme_long_desc = "Decimal Unit marked Instruction Finish", }, [ POWER9_PME_PM_MRK_DPTEG_FROM_DL2L3_MOD ] = { .pme_name = "PM_MRK_DPTEG_FROM_DL2L3_MOD", .pme_code = 0x000004F148, .pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request.", .pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", }, [ POWER9_PME_PM_MRK_DPTEG_FROM_DL2L3_SHR ] = { .pme_name = "PM_MRK_DPTEG_FROM_DL2L3_SHR", .pme_code = 0x000003F148, .pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request.", .pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", }, [ POWER9_PME_PM_MRK_DPTEG_FROM_DL4 ] = { .pme_name = "PM_MRK_DPTEG_FROM_DL4", .pme_code = 0x000003F14C, .pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a marked data side request.", .pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", }, [ POWER9_PME_PM_MRK_DPTEG_FROM_DMEM ] = { .pme_name = "PM_MRK_DPTEG_FROM_DMEM", .pme_code = 0x000004F14C, .pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a marked data side request.", .pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", }, [ POWER9_PME_PM_MRK_DPTEG_FROM_L21_MOD ] = { .pme_name = "PM_MRK_DPTEG_FROM_L21_MOD", .pme_code = 0x000004F146, .pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a marked data side request.", .pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", }, [ POWER9_PME_PM_MRK_DPTEG_FROM_L21_SHR ] = { .pme_name = "PM_MRK_DPTEG_FROM_L21_SHR", .pme_code = 0x000003F146, .pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a marked data side request.", .pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", }, [ POWER9_PME_PM_MRK_DPTEG_FROM_L2_MEPF ] = { .pme_name = "PM_MRK_DPTEG_FROM_L2_MEPF", .pme_code = 0x000002F140, .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state.", .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", }, [ POWER9_PME_PM_MRK_DPTEG_FROM_L2MISS ] = { .pme_name = "PM_MRK_DPTEG_FROM_L2MISS", .pme_code = 0x000001F14E, .pme_short_desc = "A Page Table Entry was loaded into the TLB from a location other than the local core's L2 due to a marked data side request.", .pme_long_desc = "A Page Table Entry was loaded into the TLB from a location other than the local core's L2 due to a marked data side request.. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", }, [ POWER9_PME_PM_MRK_DPTEG_FROM_L2_NO_CONFLICT ] = { .pme_name = "PM_MRK_DPTEG_FROM_L2_NO_CONFLICT", .pme_code = 0x000001F140, .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a marked data side request.", .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", }, [ POWER9_PME_PM_MRK_DPTEG_FROM_L2 ] = { .pme_name = "PM_MRK_DPTEG_FROM_L2", .pme_code = 0x000001F142, .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 due to a marked data side request.", .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", }, [ POWER9_PME_PM_MRK_DPTEG_FROM_L31_ECO_MOD ] = { .pme_name = "PM_MRK_DPTEG_FROM_L31_ECO_MOD", .pme_code = 0x000004F144, .pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a marked data side request.", .pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", }, [ POWER9_PME_PM_MRK_DPTEG_FROM_L31_ECO_SHR ] = { .pme_name = "PM_MRK_DPTEG_FROM_L31_ECO_SHR", .pme_code = 0x000003F144, .pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a marked data side request.", .pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", }, [ POWER9_PME_PM_MRK_DPTEG_FROM_L31_MOD ] = { .pme_name = "PM_MRK_DPTEG_FROM_L31_MOD", .pme_code = 0x000002F144, .pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a marked data side request.", .pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", }, [ POWER9_PME_PM_MRK_DPTEG_FROM_L31_SHR ] = { .pme_name = "PM_MRK_DPTEG_FROM_L31_SHR", .pme_code = 0x000001F146, .pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a marked data side request.", .pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a marked data side request.. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", }, [ POWER9_PME_PM_MRK_DPTEG_FROM_L3_DISP_CONFLICT ] = { .pme_name = "PM_MRK_DPTEG_FROM_L3_DISP_CONFLICT", .pme_code = 0x000003F142, .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a marked data side request.", .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", }, [ POWER9_PME_PM_MRK_DPTEG_FROM_L3_MEPF ] = { .pme_name = "PM_MRK_DPTEG_FROM_L3_MEPF", .pme_code = 0x000002F142, .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state.", .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", }, [ POWER9_PME_PM_MRK_DPTEG_FROM_L3MISS ] = { .pme_name = "PM_MRK_DPTEG_FROM_L3MISS", .pme_code = 0x000004F14E, .pme_short_desc = "A Page Table Entry was loaded into the TLB from a location other than the local core's L3 due to a marked data side request.", .pme_long_desc = "A Page Table Entry was loaded into the TLB from a location other than the local core's L3 due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", }, [ POWER9_PME_PM_MRK_DPTEG_FROM_L3_NO_CONFLICT ] = { .pme_name = "PM_MRK_DPTEG_FROM_L3_NO_CONFLICT", .pme_code = 0x000001F144, .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a marked data side request.", .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", }, [ POWER9_PME_PM_MRK_DPTEG_FROM_L3 ] = { .pme_name = "PM_MRK_DPTEG_FROM_L3", .pme_code = 0x000004F142, .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 due to a marked data side request.", .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", }, [ POWER9_PME_PM_MRK_DPTEG_FROM_LL4 ] = { .pme_name = "PM_MRK_DPTEG_FROM_LL4", .pme_code = 0x000001F14C, .pme_short_desc = "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a marked data side request.", .pme_long_desc = "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a marked data side request.. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", }, [ POWER9_PME_PM_MRK_DPTEG_FROM_LMEM ] = { .pme_name = "PM_MRK_DPTEG_FROM_LMEM", .pme_code = 0x000002F148, .pme_short_desc = "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a marked data side request.", .pme_long_desc = "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", }, [ POWER9_PME_PM_MRK_DPTEG_FROM_MEMORY ] = { .pme_name = "PM_MRK_DPTEG_FROM_MEMORY", .pme_code = 0x000002F14C, .pme_short_desc = "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a marked data side request.", .pme_long_desc = "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", }, [ POWER9_PME_PM_MRK_DPTEG_FROM_OFF_CHIP_CACHE ] = { .pme_name = "PM_MRK_DPTEG_FROM_OFF_CHIP_CACHE", .pme_code = 0x000004F14A, .pme_short_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked data side request.", .pme_long_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", }, [ POWER9_PME_PM_MRK_DPTEG_FROM_ON_CHIP_CACHE ] = { .pme_name = "PM_MRK_DPTEG_FROM_ON_CHIP_CACHE", .pme_code = 0x000001F148, .pme_short_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a marked data side request.", .pme_long_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a marked data side request.. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", }, [ POWER9_PME_PM_MRK_DPTEG_FROM_RL2L3_MOD ] = { .pme_name = "PM_MRK_DPTEG_FROM_RL2L3_MOD", .pme_code = 0x000002F146, .pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked data side request.", .pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", }, [ POWER9_PME_PM_MRK_DPTEG_FROM_RL2L3_SHR ] = { .pme_name = "PM_MRK_DPTEG_FROM_RL2L3_SHR", .pme_code = 0x000001F14A, .pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked data side request.", .pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked data side request.. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", }, [ POWER9_PME_PM_MRK_DPTEG_FROM_RL4 ] = { .pme_name = "PM_MRK_DPTEG_FROM_RL4", .pme_code = 0x000002F14A, .pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a marked data side request.", .pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", }, [ POWER9_PME_PM_MRK_DPTEG_FROM_RMEM ] = { .pme_name = "PM_MRK_DPTEG_FROM_RMEM", .pme_code = 0x000003F14A, .pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a marked data side request.", .pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", }, [ POWER9_PME_PM_MRK_DTLB_MISS_16G ] = { .pme_name = "PM_MRK_DTLB_MISS_16G", .pme_code = 0x000002D15E, .pme_short_desc = "Marked Data TLB Miss page size 16G", .pme_long_desc = "Marked Data TLB Miss page size 16G", }, [ POWER9_PME_PM_MRK_DTLB_MISS_16M ] = { .pme_name = "PM_MRK_DTLB_MISS_16M", .pme_code = 0x000004C15E, .pme_short_desc = "Marked Data TLB Miss page size 16M", .pme_long_desc = "Marked Data TLB Miss page size 16M", }, [ POWER9_PME_PM_MRK_DTLB_MISS_1G ] = { .pme_name = "PM_MRK_DTLB_MISS_1G", .pme_code = 0x000001D15C, .pme_short_desc = "Marked Data TLB reload (after a miss) page size 2M.", .pme_long_desc = "Marked Data TLB reload (after a miss) page size 2M. Implies radix translation was used", }, [ POWER9_PME_PM_MRK_DTLB_MISS_4K ] = { .pme_name = "PM_MRK_DTLB_MISS_4K", .pme_code = 0x000002D156, .pme_short_desc = "Marked Data TLB Miss page size 4k", .pme_long_desc = "Marked Data TLB Miss page size 4k", }, [ POWER9_PME_PM_MRK_DTLB_MISS_64K ] = { .pme_name = "PM_MRK_DTLB_MISS_64K", .pme_code = 0x000003D156, .pme_short_desc = "Marked Data TLB Miss page size 64K", .pme_long_desc = "Marked Data TLB Miss page size 64K", }, [ POWER9_PME_PM_MRK_DTLB_MISS ] = { .pme_name = "PM_MRK_DTLB_MISS", .pme_code = 0x00000401E4, .pme_short_desc = "Marked dtlb miss", .pme_long_desc = "Marked dtlb miss", }, [ POWER9_PME_PM_MRK_FAB_RSP_BKILL_CYC ] = { .pme_name = "PM_MRK_FAB_RSP_BKILL_CYC", .pme_code = 0x000001F152, .pme_short_desc = "cycles L2 RC took for a bkill", .pme_long_desc = "cycles L2 RC took for a bkill", }, [ POWER9_PME_PM_MRK_FAB_RSP_BKILL ] = { .pme_name = "PM_MRK_FAB_RSP_BKILL", .pme_code = 0x0000040154, .pme_short_desc = "Marked store had to do a bkill", .pme_long_desc = "Marked store had to do a bkill", }, [ POWER9_PME_PM_MRK_FAB_RSP_CLAIM_RTY ] = { .pme_name = "PM_MRK_FAB_RSP_CLAIM_RTY", .pme_code = 0x000003015E, .pme_short_desc = "Sampled store did a rwitm and got a rty", .pme_long_desc = "Sampled store did a rwitm and got a rty", }, [ POWER9_PME_PM_MRK_FAB_RSP_DCLAIM_CYC ] = { .pme_name = "PM_MRK_FAB_RSP_DCLAIM_CYC", .pme_code = 0x000002F152, .pme_short_desc = "cycles L2 RC took for a dclaim", .pme_long_desc = "cycles L2 RC took for a dclaim", }, [ POWER9_PME_PM_MRK_FAB_RSP_DCLAIM ] = { .pme_name = "PM_MRK_FAB_RSP_DCLAIM", .pme_code = 0x0000030154, .pme_short_desc = "Marked store had to do a dclaim", .pme_long_desc = "Marked store had to do a dclaim", }, [ POWER9_PME_PM_MRK_FAB_RSP_RD_RTY ] = { .pme_name = "PM_MRK_FAB_RSP_RD_RTY", .pme_code = 0x000004015E, .pme_short_desc = "Sampled L2 reads retry count", .pme_long_desc = "Sampled L2 reads retry count", }, [ POWER9_PME_PM_MRK_FAB_RSP_RD_T_INTV ] = { .pme_name = "PM_MRK_FAB_RSP_RD_T_INTV", .pme_code = 0x000001015E, .pme_short_desc = "Sampled Read got a T intervention", .pme_long_desc = "Sampled Read got a T intervention", }, [ POWER9_PME_PM_MRK_FAB_RSP_RWITM_CYC ] = { .pme_name = "PM_MRK_FAB_RSP_RWITM_CYC", .pme_code = 0x000004F150, .pme_short_desc = "cycles L2 RC took for a rwitm", .pme_long_desc = "cycles L2 RC took for a rwitm", }, [ POWER9_PME_PM_MRK_FAB_RSP_RWITM_RTY ] = { .pme_name = "PM_MRK_FAB_RSP_RWITM_RTY", .pme_code = 0x000002015E, .pme_short_desc = "Sampled store did a rwitm and got a rty", .pme_long_desc = "Sampled store did a rwitm and got a rty", }, [ POWER9_PME_PM_MRK_FXU_FIN ] = { .pme_name = "PM_MRK_FXU_FIN", .pme_code = 0x0000020134, .pme_short_desc = "fxu marked instr finish", .pme_long_desc = "fxu marked instr finish", }, [ POWER9_PME_PM_MRK_IC_MISS ] = { .pme_name = "PM_MRK_IC_MISS", .pme_code = 0x000004013A, .pme_short_desc = "Marked instruction experienced I cache miss", .pme_long_desc = "Marked instruction experienced I cache miss", }, [ POWER9_PME_PM_MRK_INST_CMPL ] = { .pme_name = "PM_MRK_INST_CMPL", .pme_code = 0x00000401E0, .pme_short_desc = "marked instruction completed", .pme_long_desc = "marked instruction completed", }, [ POWER9_PME_PM_MRK_INST_DECODED ] = { .pme_name = "PM_MRK_INST_DECODED", .pme_code = 0x0000020130, .pme_short_desc = "An instruction was marked at decode time.", .pme_long_desc = "An instruction was marked at decode time. Random Instruction Sampling (RIS) only", }, [ POWER9_PME_PM_MRK_INST_DISP ] = { .pme_name = "PM_MRK_INST_DISP", .pme_code = 0x00000101E0, .pme_short_desc = "The thread has dispatched a randomly sampled marked instruction", .pme_long_desc = "The thread has dispatched a randomly sampled marked instruction", }, [ POWER9_PME_PM_MRK_INST_FIN ] = { .pme_name = "PM_MRK_INST_FIN", .pme_code = 0x0000030130, .pme_short_desc = "marked instruction finished", .pme_long_desc = "marked instruction finished", }, [ POWER9_PME_PM_MRK_INST_FROM_L3MISS ] = { .pme_name = "PM_MRK_INST_FROM_L3MISS", .pme_code = 0x00000401E6, .pme_short_desc = "Marked instruction was reloaded from a location beyond the local chiplet", .pme_long_desc = "Marked instruction was reloaded from a location beyond the local chiplet", }, [ POWER9_PME_PM_MRK_INST_ISSUED ] = { .pme_name = "PM_MRK_INST_ISSUED", .pme_code = 0x0000010132, .pme_short_desc = "Marked instruction issued", .pme_long_desc = "Marked instruction issued", }, [ POWER9_PME_PM_MRK_INST_TIMEO ] = { .pme_name = "PM_MRK_INST_TIMEO", .pme_code = 0x0000040134, .pme_short_desc = "marked Instruction finish timeout (instruction lost)", .pme_long_desc = "marked Instruction finish timeout (instruction lost)", }, [ POWER9_PME_PM_MRK_INST ] = { .pme_name = "PM_MRK_INST", .pme_code = 0x0000024058, .pme_short_desc = "An instruction was marked.", .pme_long_desc = "An instruction was marked. Includes both Random Instruction Sampling (RIS) at decode time and Random Event Sampling (RES) at the time the configured event happens", }, [ POWER9_PME_PM_MRK_L1_ICACHE_MISS ] = { .pme_name = "PM_MRK_L1_ICACHE_MISS", .pme_code = 0x00000101E4, .pme_short_desc = "sampled Instruction suffered an icache Miss", .pme_long_desc = "sampled Instruction suffered an icache Miss", }, [ POWER9_PME_PM_MRK_L1_RELOAD_VALID ] = { .pme_name = "PM_MRK_L1_RELOAD_VALID", .pme_code = 0x00000101EA, .pme_short_desc = "Marked demand reload", .pme_long_desc = "Marked demand reload", }, [ POWER9_PME_PM_MRK_L2_RC_DISP ] = { .pme_name = "PM_MRK_L2_RC_DISP", .pme_code = 0x0000020114, .pme_short_desc = "Marked Instruction RC dispatched in L2", .pme_long_desc = "Marked Instruction RC dispatched in L2", }, [ POWER9_PME_PM_MRK_L2_RC_DONE ] = { .pme_name = "PM_MRK_L2_RC_DONE", .pme_code = 0x000003012A, .pme_short_desc = "Marked RC done", .pme_long_desc = "Marked RC done", }, [ POWER9_PME_PM_MRK_L2_TM_REQ_ABORT ] = { .pme_name = "PM_MRK_L2_TM_REQ_ABORT", .pme_code = 0x000001E15E, .pme_short_desc = "TM abort", .pme_long_desc = "TM abort", }, [ POWER9_PME_PM_MRK_L2_TM_ST_ABORT_SISTER ] = { .pme_name = "PM_MRK_L2_TM_ST_ABORT_SISTER", .pme_code = 0x000003E15C, .pme_short_desc = "TM marked store abort for this thread", .pme_long_desc = "TM marked store abort for this thread", }, [ POWER9_PME_PM_MRK_LARX_FIN ] = { .pme_name = "PM_MRK_LARX_FIN", .pme_code = 0x0000040116, .pme_short_desc = "Larx finished", .pme_long_desc = "Larx finished", }, [ POWER9_PME_PM_MRK_LD_MISS_EXPOSED_CYC ] = { .pme_name = "PM_MRK_LD_MISS_EXPOSED_CYC", .pme_code = 0x000001013E, .pme_short_desc = "Marked Load exposed Miss (use edge detect to count #)", .pme_long_desc = "Marked Load exposed Miss (use edge detect to count #)", }, [ POWER9_PME_PM_MRK_LD_MISS_L1_CYC ] = { .pme_name = "PM_MRK_LD_MISS_L1_CYC", .pme_code = 0x000001D056, .pme_short_desc = "Marked ld latency", .pme_long_desc = "Marked ld latency", }, [ POWER9_PME_PM_MRK_LD_MISS_L1 ] = { .pme_name = "PM_MRK_LD_MISS_L1", .pme_code = 0x00000201E2, .pme_short_desc = "Marked DL1 Demand Miss counted at exec time.", .pme_long_desc = "Marked DL1 Demand Miss counted at exec time. Note that this count is per slice, so if a load spans multiple slices this event will increment multiple times for a single load.", }, [ POWER9_PME_PM_MRK_LSU_DERAT_MISS ] = { .pme_name = "PM_MRK_LSU_DERAT_MISS", .pme_code = 0x0000030162, .pme_short_desc = "Marked derat reload (miss) for any page size", .pme_long_desc = "Marked derat reload (miss) for any page size", }, [ POWER9_PME_PM_MRK_LSU_FIN ] = { .pme_name = "PM_MRK_LSU_FIN", .pme_code = 0x0000040132, .pme_short_desc = "lsu marked instr PPC finish", .pme_long_desc = "lsu marked instr PPC finish", }, [ POWER9_PME_PM_MRK_LSU_FLUSH_ATOMIC ] = { .pme_name = "PM_MRK_LSU_FLUSH_ATOMIC", .pme_code = 0x000000D098, .pme_short_desc = "Quad-word loads (lq) are considered atomic because they always span at least 2 slices.", .pme_long_desc = "Quad-word loads (lq) are considered atomic because they always span at least 2 slices. If a snoop or store from another thread changes the data the load is accessing between the 2 or 3 pieces of the lq instruction, the lq will be flushed", }, [ POWER9_PME_PM_MRK_LSU_FLUSH_EMSH ] = { .pme_name = "PM_MRK_LSU_FLUSH_EMSH", .pme_code = 0x000000D898, .pme_short_desc = "An ERAT miss was detected after a set-p hit.", .pme_long_desc = "An ERAT miss was detected after a set-p hit. Erat tracker indicates fail due to tlbmiss and the instruction gets flushed because the instruction was working on the wrong address", }, [ POWER9_PME_PM_MRK_LSU_FLUSH_LARX_STCX ] = { .pme_name = "PM_MRK_LSU_FLUSH_LARX_STCX", .pme_code = 0x000000D8A4, .pme_short_desc = "A larx is flushed because an older larx has an LMQ reservation for the same thread.", .pme_long_desc = "A larx is flushed because an older larx has an LMQ reservation for the same thread. A stcx is flushed because an older stcx is in the LMQ. The flush happens when the older larx/stcx relaunches", }, [ POWER9_PME_PM_MRK_LSU_FLUSH_LHL_SHL ] = { .pme_name = "PM_MRK_LSU_FLUSH_LHL_SHL", .pme_code = 0x000000D8A0, .pme_short_desc = "The instruction was flushed because of a sequential load/store consistency.", .pme_long_desc = "The instruction was flushed because of a sequential load/store consistency. If a load or store hits on an older load that has either been snooped (for loads) or has stale data (for stores).", }, [ POWER9_PME_PM_MRK_LSU_FLUSH_LHS ] = { .pme_name = "PM_MRK_LSU_FLUSH_LHS", .pme_code = 0x000000D0A0, .pme_short_desc = "Effective Address alias flush : no EA match but Real Address match.", .pme_long_desc = "Effective Address alias flush : no EA match but Real Address match. If the data has not yet been returned for this load, the instruction will just be rejected, but if it has returned data, it will be flushed", }, [ POWER9_PME_PM_MRK_LSU_FLUSH_RELAUNCH_MISS ] = { .pme_name = "PM_MRK_LSU_FLUSH_RELAUNCH_MISS", .pme_code = 0x000000D09C, .pme_short_desc = "If a load that has already returned data and has to relaunch for any reason then gets a miss (erat, setp, data cache), it will often be flushed at relaunch time because the data might be inconsistent", .pme_long_desc = "If a load that has already returned data and has to relaunch for any reason then gets a miss (erat, setp, data cache), it will often be flushed at relaunch time because the data might be inconsistent", }, [ POWER9_PME_PM_MRK_LSU_FLUSH_SAO ] = { .pme_name = "PM_MRK_LSU_FLUSH_SAO", .pme_code = 0x000000D0A4, .pme_short_desc = "A load-hit-load condition with Strong Address Ordering will have address compare disabled and flush", .pme_long_desc = "A load-hit-load condition with Strong Address Ordering will have address compare disabled and flush", }, [ POWER9_PME_PM_MRK_LSU_FLUSH_UE ] = { .pme_name = "PM_MRK_LSU_FLUSH_UE", .pme_code = 0x000000D89C, .pme_short_desc = "Correctable ECC error on reload data, reported at critical data forward time", .pme_long_desc = "Correctable ECC error on reload data, reported at critical data forward time", }, [ POWER9_PME_PM_MRK_NTC_CYC ] = { .pme_name = "PM_MRK_NTC_CYC", .pme_code = 0x000002011C, .pme_short_desc = "Cycles during which the marked instruction is next to complete (completion is held up because the marked instruction hasn't completed yet)", .pme_long_desc = "Cycles during which the marked instruction is next to complete (completion is held up because the marked instruction hasn't completed yet)", }, [ POWER9_PME_PM_MRK_NTF_FIN ] = { .pme_name = "PM_MRK_NTF_FIN", .pme_code = 0x0000020112, .pme_short_desc = "Marked next to finish instruction finished", .pme_long_desc = "Marked next to finish instruction finished", }, [ POWER9_PME_PM_MRK_PROBE_NOP_CMPL ] = { .pme_name = "PM_MRK_PROBE_NOP_CMPL", .pme_code = 0x000001F05E, .pme_short_desc = "Marked probeNops completed", .pme_long_desc = "Marked probeNops completed", }, [ POWER9_PME_PM_MRK_RUN_CYC ] = { .pme_name = "PM_MRK_RUN_CYC", .pme_code = 0x000001D15E, .pme_short_desc = "Run cycles in which a marked instruction is in the pipeline", .pme_long_desc = "Run cycles in which a marked instruction is in the pipeline", }, [ POWER9_PME_PM_MRK_STALL_CMPLU_CYC ] = { .pme_name = "PM_MRK_STALL_CMPLU_CYC", .pme_code = 0x000003013E, .pme_short_desc = "Number of cycles the marked instruction is experiencing a stall while it is next to complete (NTC)", .pme_long_desc = "Number of cycles the marked instruction is experiencing a stall while it is next to complete (NTC)", }, [ POWER9_PME_PM_MRK_ST_CMPL_INT ] = { .pme_name = "PM_MRK_ST_CMPL_INT", .pme_code = 0x0000030134, .pme_short_desc = "marked store finished with intervention", .pme_long_desc = "marked store finished with intervention", }, [ POWER9_PME_PM_MRK_ST_CMPL ] = { .pme_name = "PM_MRK_ST_CMPL", .pme_code = 0x00000301E2, .pme_short_desc = "Marked store completed and sent to nest", .pme_long_desc = "Marked store completed and sent to nest", }, [ POWER9_PME_PM_MRK_STCX_FAIL ] = { .pme_name = "PM_MRK_STCX_FAIL", .pme_code = 0x000003E158, .pme_short_desc = "marked stcx failed", .pme_long_desc = "marked stcx failed", }, [ POWER9_PME_PM_MRK_STCX_FIN ] = { .pme_name = "PM_MRK_STCX_FIN", .pme_code = 0x0000024056, .pme_short_desc = "Number of marked stcx instructions finished.", .pme_long_desc = "Number of marked stcx instructions finished. This includes instructions in the speculative path of a branch that may be flushed", }, [ POWER9_PME_PM_MRK_ST_DONE_L2 ] = { .pme_name = "PM_MRK_ST_DONE_L2", .pme_code = 0x0000010134, .pme_short_desc = "marked store completed in L2 ( RC machine done)", .pme_long_desc = "marked store completed in L2 ( RC machine done)", }, [ POWER9_PME_PM_MRK_ST_DRAIN_TO_L2DISP_CYC ] = { .pme_name = "PM_MRK_ST_DRAIN_TO_L2DISP_CYC", .pme_code = 0x000003F150, .pme_short_desc = "cycles to drain st from core to L2", .pme_long_desc = "cycles to drain st from core to L2", }, [ POWER9_PME_PM_MRK_ST_FWD ] = { .pme_name = "PM_MRK_ST_FWD", .pme_code = 0x000003012C, .pme_short_desc = "Marked st forwards", .pme_long_desc = "Marked st forwards", }, [ POWER9_PME_PM_MRK_ST_L2DISP_TO_CMPL_CYC ] = { .pme_name = "PM_MRK_ST_L2DISP_TO_CMPL_CYC", .pme_code = 0x000001F150, .pme_short_desc = "cycles from L2 rc disp to l2 rc completion", .pme_long_desc = "cycles from L2 rc disp to l2 rc completion", }, [ POWER9_PME_PM_MRK_ST_NEST ] = { .pme_name = "PM_MRK_ST_NEST", .pme_code = 0x0000020138, .pme_short_desc = "Marked store sent to nest", .pme_long_desc = "Marked store sent to nest", }, [ POWER9_PME_PM_MRK_TEND_FAIL ] = { .pme_name = "PM_MRK_TEND_FAIL", .pme_code = 0x00000028A4, .pme_short_desc = "Nested or not nested tend failed for a marked tend instruction", .pme_long_desc = "Nested or not nested tend failed for a marked tend instruction", }, [ POWER9_PME_PM_MRK_VSU_FIN ] = { .pme_name = "PM_MRK_VSU_FIN", .pme_code = 0x0000030132, .pme_short_desc = "VSU marked instr finish", .pme_long_desc = "VSU marked instr finish", }, [ POWER9_PME_PM_MULT_MRK ] = { .pme_name = "PM_MULT_MRK", .pme_code = 0x000003D15E, .pme_short_desc = "mult marked instr", .pme_long_desc = "mult marked instr", }, [ POWER9_PME_PM_NEST_REF_CLK ] = { .pme_name = "PM_NEST_REF_CLK", .pme_code = 0x000003006E, .pme_short_desc = "Multiply by 4 to obtain the number of PB cycles", .pme_long_desc = "Multiply by 4 to obtain the number of PB cycles", }, [ POWER9_PME_PM_NON_DATA_STORE ] = { .pme_name = "PM_NON_DATA_STORE", .pme_code = 0x000000F8A0, .pme_short_desc = "All ops that drain from s2q to L2 and contain no data", .pme_long_desc = "All ops that drain from s2q to L2 and contain no data", }, [ POWER9_PME_PM_NON_FMA_FLOP_CMPL ] = { .pme_name = "PM_NON_FMA_FLOP_CMPL", .pme_code = 0x000004D056, .pme_short_desc = "Non FMA instruction completed", .pme_long_desc = "Non FMA instruction completed", }, [ POWER9_PME_PM_NON_MATH_FLOP_CMPL ] = { .pme_name = "PM_NON_MATH_FLOP_CMPL", .pme_code = 0x000004D05A, .pme_short_desc = "Non FLOP operation completed", .pme_long_desc = "Non FLOP operation completed", }, [ POWER9_PME_PM_NON_TM_RST_SC ] = { .pme_name = "PM_NON_TM_RST_SC", .pme_code = 0x00000260A6, .pme_short_desc = "Non-TM snp rst TM SC", .pme_long_desc = "Non-TM snp rst TM SC", }, [ POWER9_PME_PM_NTC_ALL_FIN ] = { .pme_name = "PM_NTC_ALL_FIN", .pme_code = 0x000002001A, .pme_short_desc = "Cycles after all instructions have finished to group completed", .pme_long_desc = "Cycles after all instructions have finished to group completed", }, [ POWER9_PME_PM_NTC_FIN ] = { .pme_name = "PM_NTC_FIN", .pme_code = 0x000002405A, .pme_short_desc = "Cycles in which the oldest instruction in the pipeline (NTC) finishes.", .pme_long_desc = "Cycles in which the oldest instruction in the pipeline (NTC) finishes. This event is used to account for cycles in which work is being completed in the CPI stack", }, [ POWER9_PME_PM_NTC_ISSUE_HELD_ARB ] = { .pme_name = "PM_NTC_ISSUE_HELD_ARB", .pme_code = 0x000002E016, .pme_short_desc = "The NTC instruction is being held at dispatch because it lost arbitration onto the issue pipe to another instruction (from the same thread or a different thread)", .pme_long_desc = "The NTC instruction is being held at dispatch because it lost arbitration onto the issue pipe to another instruction (from the same thread or a different thread)", }, [ POWER9_PME_PM_NTC_ISSUE_HELD_DARQ_FULL ] = { .pme_name = "PM_NTC_ISSUE_HELD_DARQ_FULL", .pme_code = 0x000001006A, .pme_short_desc = "The NTC instruction is being held at dispatch because there are no slots in the DARQ for it", .pme_long_desc = "The NTC instruction is being held at dispatch because there are no slots in the DARQ for it", }, [ POWER9_PME_PM_NTC_ISSUE_HELD_OTHER ] = { .pme_name = "PM_NTC_ISSUE_HELD_OTHER", .pme_code = 0x000003D05A, .pme_short_desc = "The NTC instruction is being held at dispatch during regular pipeline cycles, or because the VSU is busy with multi-cycle instructions, or because of a write-back collision with VSU", .pme_long_desc = "The NTC instruction is being held at dispatch during regular pipeline cycles, or because the VSU is busy with multi-cycle instructions, or because of a write-back collision with VSU", }, [ POWER9_PME_PM_PARTIAL_ST_FIN ] = { .pme_name = "PM_PARTIAL_ST_FIN", .pme_code = 0x0000034054, .pme_short_desc = "Any store finished by an LSU slice", .pme_long_desc = "Any store finished by an LSU slice", }, [ POWER9_PME_PM_PMC1_OVERFLOW ] = { .pme_name = "PM_PMC1_OVERFLOW", .pme_code = 0x0000020010, .pme_short_desc = "Overflow from counter 1", .pme_long_desc = "Overflow from counter 1", }, [ POWER9_PME_PM_PMC1_REWIND ] = { .pme_name = "PM_PMC1_REWIND", .pme_code = 0x000004D02C, .pme_short_desc = "", .pme_long_desc = "", }, [ POWER9_PME_PM_PMC1_SAVED ] = { .pme_name = "PM_PMC1_SAVED", .pme_code = 0x000004D010, .pme_short_desc = "PMC1 Rewind Value saved", .pme_long_desc = "PMC1 Rewind Value saved", }, [ POWER9_PME_PM_PMC2_OVERFLOW ] = { .pme_name = "PM_PMC2_OVERFLOW", .pme_code = 0x0000030010, .pme_short_desc = "Overflow from counter 2", .pme_long_desc = "Overflow from counter 2", }, [ POWER9_PME_PM_PMC2_REWIND ] = { .pme_name = "PM_PMC2_REWIND", .pme_code = 0x0000030020, .pme_short_desc = "PMC2 Rewind Event (did not match condition)", .pme_long_desc = "PMC2 Rewind Event (did not match condition)", }, [ POWER9_PME_PM_PMC2_SAVED ] = { .pme_name = "PM_PMC2_SAVED", .pme_code = 0x0000010022, .pme_short_desc = "PMC2 Rewind Value saved", .pme_long_desc = "PMC2 Rewind Value saved", }, [ POWER9_PME_PM_PMC3_OVERFLOW ] = { .pme_name = "PM_PMC3_OVERFLOW", .pme_code = 0x0000040010, .pme_short_desc = "Overflow from counter 3", .pme_long_desc = "Overflow from counter 3", }, [ POWER9_PME_PM_PMC3_REWIND ] = { .pme_name = "PM_PMC3_REWIND", .pme_code = 0x000001000A, .pme_short_desc = "PMC3 rewind event.", .pme_long_desc = "PMC3 rewind event. A rewind happens when a speculative event (such as latency or CPI stack) is selected on PMC3 and the stall reason or reload source did not match the one programmed in PMC3. When this occurs, the count in PMC3 will not change.", }, [ POWER9_PME_PM_PMC3_SAVED ] = { .pme_name = "PM_PMC3_SAVED", .pme_code = 0x000004D012, .pme_short_desc = "PMC3 Rewind Value saved", .pme_long_desc = "PMC3 Rewind Value saved", }, [ POWER9_PME_PM_PMC4_OVERFLOW ] = { .pme_name = "PM_PMC4_OVERFLOW", .pme_code = 0x0000010010, .pme_short_desc = "Overflow from counter 4", .pme_long_desc = "Overflow from counter 4", }, [ POWER9_PME_PM_PMC4_REWIND ] = { .pme_name = "PM_PMC4_REWIND", .pme_code = 0x0000010020, .pme_short_desc = "PMC4 Rewind Event", .pme_long_desc = "PMC4 Rewind Event", }, [ POWER9_PME_PM_PMC4_SAVED ] = { .pme_name = "PM_PMC4_SAVED", .pme_code = 0x0000030022, .pme_short_desc = "PMC4 Rewind Value saved (matched condition)", .pme_long_desc = "PMC4 Rewind Value saved (matched condition)", }, [ POWER9_PME_PM_PMC5_OVERFLOW ] = { .pme_name = "PM_PMC5_OVERFLOW", .pme_code = 0x0000010024, .pme_short_desc = "Overflow from counter 5", .pme_long_desc = "Overflow from counter 5", }, [ POWER9_PME_PM_PMC6_OVERFLOW ] = { .pme_name = "PM_PMC6_OVERFLOW", .pme_code = 0x0000030024, .pme_short_desc = "Overflow from counter 6", .pme_long_desc = "Overflow from counter 6", }, [ POWER9_PME_PM_PROBE_NOP_DISP ] = { .pme_name = "PM_PROBE_NOP_DISP", .pme_code = 0x0000040014, .pme_short_desc = "ProbeNops dispatched", .pme_long_desc = "ProbeNops dispatched", }, [ POWER9_PME_PM_PTE_PREFETCH ] = { .pme_name = "PM_PTE_PREFETCH", .pme_code = 0x000000F084, .pme_short_desc = "PTE prefetches", .pme_long_desc = "PTE prefetches", }, [ POWER9_PME_PM_PTESYNC ] = { .pme_name = "PM_PTESYNC", .pme_code = 0x000000589C, .pme_short_desc = "ptesync instruction counted when the instruction is decoded and transmitted", .pme_long_desc = "ptesync instruction counted when the instruction is decoded and transmitted", }, [ POWER9_PME_PM_PUMP_CPRED ] = { .pme_name = "PM_PUMP_CPRED", .pme_code = 0x0000010054, .pme_short_desc = "Pump prediction correct.", .pme_long_desc = "Pump prediction correct. Counts across all types of pumps for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)", }, [ POWER9_PME_PM_PUMP_MPRED ] = { .pme_name = "PM_PUMP_MPRED", .pme_code = 0x0000040052, .pme_short_desc = "Pump misprediction.", .pme_long_desc = "Pump misprediction. Counts across all types of pumps for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)", }, [ POWER9_PME_PM_RADIX_PWC_L1_HIT ] = { .pme_name = "PM_RADIX_PWC_L1_HIT", .pme_code = 0x000001F056, .pme_short_desc = "A radix translation attempt missed in the TLB and only the first level page walk cache was a hit.", .pme_long_desc = "A radix translation attempt missed in the TLB and only the first level page walk cache was a hit.", }, [ POWER9_PME_PM_RADIX_PWC_L1_PDE_FROM_L2 ] = { .pme_name = "PM_RADIX_PWC_L1_PDE_FROM_L2", .pme_code = 0x000002D026, .pme_short_desc = "A Page Directory Entry was reloaded to a level 1 page walk cache from the core's L2 data cache", .pme_long_desc = "A Page Directory Entry was reloaded to a level 1 page walk cache from the core's L2 data cache", }, [ POWER9_PME_PM_RADIX_PWC_L1_PDE_FROM_L3MISS ] = { .pme_name = "PM_RADIX_PWC_L1_PDE_FROM_L3MISS", .pme_code = 0x000004F056, .pme_short_desc = "A Page Directory Entry was reloaded to a level 1 page walk cache from beyond the core's L3 data cache.", .pme_long_desc = "A Page Directory Entry was reloaded to a level 1 page walk cache from beyond the core's L3 data cache. The source could be local/remote/distant memory or another core's cache", }, [ POWER9_PME_PM_RADIX_PWC_L1_PDE_FROM_L3 ] = { .pme_name = "PM_RADIX_PWC_L1_PDE_FROM_L3", .pme_code = 0x000003F058, .pme_short_desc = "A Page Directory Entry was reloaded to a level 1 page walk cache from the core's L3 data cache", .pme_long_desc = "A Page Directory Entry was reloaded to a level 1 page walk cache from the core's L3 data cache", }, [ POWER9_PME_PM_RADIX_PWC_L2_HIT ] = { .pme_name = "PM_RADIX_PWC_L2_HIT", .pme_code = 0x000002D024, .pme_short_desc = "A radix translation attempt missed in the TLB but hit on both the first and second levels of page walk cache.", .pme_long_desc = "A radix translation attempt missed in the TLB but hit on both the first and second levels of page walk cache.", }, [ POWER9_PME_PM_RADIX_PWC_L2_PDE_FROM_L2 ] = { .pme_name = "PM_RADIX_PWC_L2_PDE_FROM_L2", .pme_code = 0x000002D028, .pme_short_desc = "A Page Directory Entry was reloaded to a level 2 page walk cache from the core's L2 data cache", .pme_long_desc = "A Page Directory Entry was reloaded to a level 2 page walk cache from the core's L2 data cache", }, [ POWER9_PME_PM_RADIX_PWC_L2_PDE_FROM_L3 ] = { .pme_name = "PM_RADIX_PWC_L2_PDE_FROM_L3", .pme_code = 0x000003F05A, .pme_short_desc = "A Page Directory Entry was reloaded to a level 2 page walk cache from the core's L3 data cache", .pme_long_desc = "A Page Directory Entry was reloaded to a level 2 page walk cache from the core's L3 data cache", }, [ POWER9_PME_PM_RADIX_PWC_L2_PTE_FROM_L2 ] = { .pme_name = "PM_RADIX_PWC_L2_PTE_FROM_L2", .pme_code = 0x000001F058, .pme_short_desc = "A Page Table Entry was reloaded to a level 2 page walk cache from the core's L2 data cache.", .pme_long_desc = "A Page Table Entry was reloaded to a level 2 page walk cache from the core's L2 data cache. This implies that level 3 and level 4 PWC accesses were not necessary for this translation", }, [ POWER9_PME_PM_RADIX_PWC_L2_PTE_FROM_L3MISS ] = { .pme_name = "PM_RADIX_PWC_L2_PTE_FROM_L3MISS", .pme_code = 0x000004F05C, .pme_short_desc = "A Page Table Entry was reloaded to a level 2 page walk cache from beyond the core's L3 data cache.", .pme_long_desc = "A Page Table Entry was reloaded to a level 2 page walk cache from beyond the core's L3 data cache. This implies that level 3 and level 4 PWC accesses were not necessary for this translation. The source could be local/remote/distant memory or another core's cache", }, [ POWER9_PME_PM_RADIX_PWC_L2_PTE_FROM_L3 ] = { .pme_name = "PM_RADIX_PWC_L2_PTE_FROM_L3", .pme_code = 0x000004F058, .pme_short_desc = "A Page Table Entry was reloaded to a level 2 page walk cache from the core's L3 data cache.", .pme_long_desc = "A Page Table Entry was reloaded to a level 2 page walk cache from the core's L3 data cache. This implies that level 3 and level 4 PWC accesses were not necessary for this translation", }, [ POWER9_PME_PM_RADIX_PWC_L3_HIT ] = { .pme_name = "PM_RADIX_PWC_L3_HIT", .pme_code = 0x000003F056, .pme_short_desc = "A radix translation attempt missed in the TLB but hit on the first, second, and third levels of page walk cache.", .pme_long_desc = "A radix translation attempt missed in the TLB but hit on the first, second, and third levels of page walk cache.", }, [ POWER9_PME_PM_RADIX_PWC_L3_PDE_FROM_L2 ] = { .pme_name = "PM_RADIX_PWC_L3_PDE_FROM_L2", .pme_code = 0x000002D02A, .pme_short_desc = "A Page Directory Entry was reloaded to a level 3 page walk cache from the core's L2 data cache", .pme_long_desc = "A Page Directory Entry was reloaded to a level 3 page walk cache from the core's L2 data cache", }, [ POWER9_PME_PM_RADIX_PWC_L3_PDE_FROM_L3 ] = { .pme_name = "PM_RADIX_PWC_L3_PDE_FROM_L3", .pme_code = 0x000001F15C, .pme_short_desc = "A Page Directory Entry was reloaded to a level 3 page walk cache from the core's L3 data cache", .pme_long_desc = "A Page Directory Entry was reloaded to a level 3 page walk cache from the core's L3 data cache", }, [ POWER9_PME_PM_RADIX_PWC_L3_PTE_FROM_L2 ] = { .pme_name = "PM_RADIX_PWC_L3_PTE_FROM_L2", .pme_code = 0x000002D02E, .pme_short_desc = "A Page Table Entry was reloaded to a level 3 page walk cache from the core's L2 data cache.", .pme_long_desc = "A Page Table Entry was reloaded to a level 3 page walk cache from the core's L2 data cache. This implies that a level 4 PWC access was not necessary for this translation", }, [ POWER9_PME_PM_RADIX_PWC_L3_PTE_FROM_L3MISS ] = { .pme_name = "PM_RADIX_PWC_L3_PTE_FROM_L3MISS", .pme_code = 0x000004F05E, .pme_short_desc = "A Page Table Entry was reloaded to a level 3 page walk cache from beyond the core's L3 data cache.", .pme_long_desc = "A Page Table Entry was reloaded to a level 3 page walk cache from beyond the core's L3 data cache. This implies that a level 4 PWC access was not necessary for this translation. The source could be local/remote/distant memory or another core's cache", }, [ POWER9_PME_PM_RADIX_PWC_L3_PTE_FROM_L3 ] = { .pme_name = "PM_RADIX_PWC_L3_PTE_FROM_L3", .pme_code = 0x000003F05E, .pme_short_desc = "A Page Table Entry was reloaded to a level 3 page walk cache from the core's L3 data cache.", .pme_long_desc = "A Page Table Entry was reloaded to a level 3 page walk cache from the core's L3 data cache. This implies that a level 4 PWC access was not necessary for this translation", }, [ POWER9_PME_PM_RADIX_PWC_L4_PTE_FROM_L2 ] = { .pme_name = "PM_RADIX_PWC_L4_PTE_FROM_L2", .pme_code = 0x000001F05A, .pme_short_desc = "A Page Table Entry was reloaded to a level 4 page walk cache from the core's L2 data cache.", .pme_long_desc = "A Page Table Entry was reloaded to a level 4 page walk cache from the core's L2 data cache. This is the deepest level of PWC possible for a translation", }, [ POWER9_PME_PM_RADIX_PWC_L4_PTE_FROM_L3MISS ] = { .pme_name = "PM_RADIX_PWC_L4_PTE_FROM_L3MISS", .pme_code = 0x000003F054, .pme_short_desc = "A Page Table Entry was reloaded to a level 4 page walk cache from beyond the core's L3 data cache.", .pme_long_desc = "A Page Table Entry was reloaded to a level 4 page walk cache from beyond the core's L3 data cache. This is the deepest level of PWC possible for a translation. The source could be local/remote/distant memory or another core's cache", }, [ POWER9_PME_PM_RADIX_PWC_L4_PTE_FROM_L3 ] = { .pme_name = "PM_RADIX_PWC_L4_PTE_FROM_L3", .pme_code = 0x000004F05A, .pme_short_desc = "A Page Table Entry was reloaded to a level 4 page walk cache from the core's L3 data cache.", .pme_long_desc = "A Page Table Entry was reloaded to a level 4 page walk cache from the core's L3 data cache. This is the deepest level of PWC possible for a translation", }, [ POWER9_PME_PM_RADIX_PWC_MISS ] = { .pme_name = "PM_RADIX_PWC_MISS", .pme_code = 0x000004F054, .pme_short_desc = "A radix translation attempt missed in the TLB and all levels of page walk cache.", .pme_long_desc = "A radix translation attempt missed in the TLB and all levels of page walk cache.", }, [ POWER9_PME_PM_RC0_BUSY ] = { .pme_name = "PM_RC0_BUSY", .pme_code = 0x000001608C, .pme_short_desc = "RC mach 0 Busy.", .pme_long_desc = "RC mach 0 Busy. Used by PMU to sample ave RC lifetime (mach0 used as sample point)", }, [ POWER9_PME_PM_RC0_BUSY_ALT ] = { .pme_name = "PM_RC0_BUSY_ALT", .pme_code = 0x000002608C, .pme_short_desc = "RC mach 0 Busy.", .pme_long_desc = "RC mach 0 Busy. Used by PMU to sample ave RC lifetime (mach0 used as sample point)", }, [ POWER9_PME_PM_RC_USAGE ] = { .pme_name = "PM_RC_USAGE", .pme_code = 0x000001688C, .pme_short_desc = "Continuous 16 cycle (2to1) window where this signals rotates thru sampling each RC machine busy.", .pme_long_desc = "Continuous 16 cycle (2to1) window where this signals rotates thru sampling each RC machine busy. PMU uses this wave to then do 16 cyc count to sample total number of machs running", }, [ POWER9_PME_PM_RD_CLEARING_SC ] = { .pme_name = "PM_RD_CLEARING_SC", .pme_code = 0x00000468A6, .pme_short_desc = "Read clearing SC", .pme_long_desc = "Read clearing SC", }, [ POWER9_PME_PM_RD_FORMING_SC ] = { .pme_name = "PM_RD_FORMING_SC", .pme_code = 0x00000460A6, .pme_short_desc = "Read forming SC", .pme_long_desc = "Read forming SC", }, [ POWER9_PME_PM_RD_HIT_PF ] = { .pme_name = "PM_RD_HIT_PF", .pme_code = 0x00000268A8, .pme_short_desc = "RD machine hit L3 PF machine", .pme_long_desc = "RD machine hit L3 PF machine", }, [ POWER9_PME_PM_RUN_CYC_SMT2_MODE ] = { .pme_name = "PM_RUN_CYC_SMT2_MODE", .pme_code = 0x000003006C, .pme_short_desc = "Cycles in which this thread's run latch is set and the core is in SMT2 mode", .pme_long_desc = "Cycles in which this thread's run latch is set and the core is in SMT2 mode", }, [ POWER9_PME_PM_RUN_CYC_SMT4_MODE ] = { .pme_name = "PM_RUN_CYC_SMT4_MODE", .pme_code = 0x000002006C, .pme_short_desc = "Cycles in which this thread's run latch is set and the core is in SMT4 mode", .pme_long_desc = "Cycles in which this thread's run latch is set and the core is in SMT4 mode", }, [ POWER9_PME_PM_RUN_CYC_ST_MODE ] = { .pme_name = "PM_RUN_CYC_ST_MODE", .pme_code = 0x000001006C, .pme_short_desc = "Cycles run latch is set and core is in ST mode", .pme_long_desc = "Cycles run latch is set and core is in ST mode", }, [ POWER9_PME_PM_RUN_CYC ] = { .pme_name = "PM_RUN_CYC", .pme_code = 0x00000200F4, .pme_short_desc = "Run_cycles", .pme_long_desc = "Run_cycles", }, [ POWER9_PME_PM_RUN_INST_CMPL ] = { .pme_name = "PM_RUN_INST_CMPL", .pme_code = 0x00000400FA, .pme_short_desc = "Run_Instructions", .pme_long_desc = "Run_Instructions", }, [ POWER9_PME_PM_RUN_PURR ] = { .pme_name = "PM_RUN_PURR", .pme_code = 0x00000400F4, .pme_short_desc = "Run_PURR", .pme_long_desc = "Run_PURR", }, [ POWER9_PME_PM_RUN_SPURR ] = { .pme_name = "PM_RUN_SPURR", .pme_code = 0x0000010008, .pme_short_desc = "Run SPURR", .pme_long_desc = "Run SPURR", }, [ POWER9_PME_PM_S2Q_FULL ] = { .pme_name = "PM_S2Q_FULL", .pme_code = 0x000000E080, .pme_short_desc = "Cycles during which the S2Q is full", .pme_long_desc = "Cycles during which the S2Q is full", }, [ POWER9_PME_PM_SCALAR_FLOP_CMPL ] = { .pme_name = "PM_SCALAR_FLOP_CMPL", .pme_code = 0x0000045056, .pme_short_desc = "Scalar flop operation completed", .pme_long_desc = "Scalar flop operation completed", }, [ POWER9_PME_PM_SHL_CREATED ] = { .pme_name = "PM_SHL_CREATED", .pme_code = 0x000000508C, .pme_short_desc = "Store-Hit-Load Table Entry Created", .pme_long_desc = "Store-Hit-Load Table Entry Created", }, [ POWER9_PME_PM_SHL_ST_DEP_CREATED ] = { .pme_name = "PM_SHL_ST_DEP_CREATED", .pme_code = 0x000000588C, .pme_short_desc = "Store-Hit-Load Table Read Hit with entry Enabled", .pme_long_desc = "Store-Hit-Load Table Read Hit with entry Enabled", }, [ POWER9_PME_PM_SHL_ST_DISABLE ] = { .pme_name = "PM_SHL_ST_DISABLE", .pme_code = 0x0000005090, .pme_short_desc = "Store-Hit-Load Table Read Hit with entry Disabled (entry was disabled due to the entry shown to not prevent the flush)", .pme_long_desc = "Store-Hit-Load Table Read Hit with entry Disabled (entry was disabled due to the entry shown to not prevent the flush)", }, [ POWER9_PME_PM_SLB_TABLEWALK_CYC ] = { .pme_name = "PM_SLB_TABLEWALK_CYC", .pme_code = 0x000000F09C, .pme_short_desc = "Cycles when a tablewalk is pending on this thread on the SLB table", .pme_long_desc = "Cycles when a tablewalk is pending on this thread on the SLB table", }, [ POWER9_PME_PM_SN0_BUSY ] = { .pme_name = "PM_SN0_BUSY", .pme_code = 0x0000016090, .pme_short_desc = "SN mach 0 Busy.", .pme_long_desc = "SN mach 0 Busy. Used by PMU to sample ave SN lifetime (mach0 used as sample point)", }, [ POWER9_PME_PM_SN0_BUSY_ALT ] = { .pme_name = "PM_SN0_BUSY_ALT", .pme_code = 0x0000026090, .pme_short_desc = "SN mach 0 Busy.", .pme_long_desc = "SN mach 0 Busy. Used by PMU to sample ave SN lifetime (mach0 used as sample point)", }, [ POWER9_PME_PM_SN_HIT ] = { .pme_name = "PM_SN_HIT", .pme_code = 0x00000460A8, .pme_short_desc = "Any port snooper hit L3.", .pme_long_desc = "Any port snooper hit L3. Up to 4 can happen in a cycle but we only count 1", }, [ POWER9_PME_PM_SN_INVL ] = { .pme_name = "PM_SN_INVL", .pme_code = 0x00000368A8, .pme_short_desc = "Any port snooper detects a store to a line in the Sx state and invalidates the line.", .pme_long_desc = "Any port snooper detects a store to a line in the Sx state and invalidates the line. Up to 4 can happen in a cycle but we only count 1", }, [ POWER9_PME_PM_SN_MISS ] = { .pme_name = "PM_SN_MISS", .pme_code = 0x00000468A8, .pme_short_desc = "Any port snooper L3 miss or collision.", .pme_long_desc = "Any port snooper L3 miss or collision. Up to 4 can happen in a cycle but we only count 1", }, [ POWER9_PME_PM_SNOOP_TLBIE ] = { .pme_name = "PM_SNOOP_TLBIE", .pme_code = 0x000000F880, .pme_short_desc = "TLBIE snoop", .pme_long_desc = "TLBIE snoop", }, [ POWER9_PME_PM_SNP_TM_HIT_M ] = { .pme_name = "PM_SNP_TM_HIT_M", .pme_code = 0x00000360A6, .pme_short_desc = "Snp TM st hit M/Mu", .pme_long_desc = "Snp TM st hit M/Mu", }, [ POWER9_PME_PM_SNP_TM_HIT_T ] = { .pme_name = "PM_SNP_TM_HIT_T", .pme_code = 0x00000368A6, .pme_short_desc = "Snp TM sthit T/Tn/Te", .pme_long_desc = "Snp TM sthit T/Tn/Te", }, [ POWER9_PME_PM_SN_USAGE ] = { .pme_name = "PM_SN_USAGE", .pme_code = 0x000003688C, .pme_short_desc = "Continuous 16 cycle (2to1) window where this signals rotates thru sampling each SN machine busy.", .pme_long_desc = "Continuous 16 cycle (2to1) window where this signals rotates thru sampling each SN machine busy. PMU uses this wave to then do 16 cyc count to sample total number of machs running", }, [ POWER9_PME_PM_SP_FLOP_CMPL ] = { .pme_name = "PM_SP_FLOP_CMPL", .pme_code = 0x000004505A, .pme_short_desc = "SP instruction completed", .pme_long_desc = "SP instruction completed", }, [ POWER9_PME_PM_SRQ_EMPTY_CYC ] = { .pme_name = "PM_SRQ_EMPTY_CYC", .pme_code = 0x0000040008, .pme_short_desc = "Cycles in which the SRQ has at least one (out of four) empty slice", .pme_long_desc = "Cycles in which the SRQ has at least one (out of four) empty slice", }, [ POWER9_PME_PM_SRQ_SYNC_CYC ] = { .pme_name = "PM_SRQ_SYNC_CYC", .pme_code = 0x000000D0AC, .pme_short_desc = "A sync is in the S2Q (edge detect to count)", .pme_long_desc = "A sync is in the S2Q (edge detect to count)", }, [ POWER9_PME_PM_STALL_END_ICT_EMPTY ] = { .pme_name = "PM_STALL_END_ICT_EMPTY", .pme_code = 0x0000010028, .pme_short_desc = "The number a times the core transitioned from a stall to ICT-empty for this thread", .pme_long_desc = "The number a times the core transitioned from a stall to ICT-empty for this thread", }, [ POWER9_PME_PM_ST_CAUSED_FAIL ] = { .pme_name = "PM_ST_CAUSED_FAIL", .pme_code = 0x000001608E, .pme_short_desc = "Non-TM Store caused any thread to fail", .pme_long_desc = "Non-TM Store caused any thread to fail", }, [ POWER9_PME_PM_ST_CMPL ] = { .pme_name = "PM_ST_CMPL", .pme_code = 0x00000200F0, .pme_short_desc = "Stores completed from S2Q (2nd-level store queue).", .pme_long_desc = "Stores completed from S2Q (2nd-level store queue).", }, [ POWER9_PME_PM_STCX_FAIL ] = { .pme_name = "PM_STCX_FAIL", .pme_code = 0x000001E058, .pme_short_desc = "stcx failed", .pme_long_desc = "stcx failed", }, [ POWER9_PME_PM_STCX_FIN ] = { .pme_name = "PM_STCX_FIN", .pme_code = 0x000002E014, .pme_short_desc = "Number of stcx instructions finished.", .pme_long_desc = "Number of stcx instructions finished. This includes instructions in the speculative path of a branch that may be flushed", }, [ POWER9_PME_PM_STCX_SUCCESS_CMPL ] = { .pme_name = "PM_STCX_SUCCESS_CMPL", .pme_code = 0x000000C8BC, .pme_short_desc = "Number of stcx instructions that completed successfully", .pme_long_desc = "Number of stcx instructions that completed successfully", }, [ POWER9_PME_PM_ST_FIN ] = { .pme_name = "PM_ST_FIN", .pme_code = 0x0000020016, .pme_short_desc = "Store finish count.", .pme_long_desc = "Store finish count. Includes speculative activity", }, [ POWER9_PME_PM_ST_FWD ] = { .pme_name = "PM_ST_FWD", .pme_code = 0x0000020018, .pme_short_desc = "Store forwards that finished", .pme_long_desc = "Store forwards that finished", }, [ POWER9_PME_PM_ST_MISS_L1 ] = { .pme_name = "PM_ST_MISS_L1", .pme_code = 0x00000300F0, .pme_short_desc = "Store Missed L1", .pme_long_desc = "Store Missed L1", }, [ POWER9_PME_PM_STOP_FETCH_PENDING_CYC ] = { .pme_name = "PM_STOP_FETCH_PENDING_CYC", .pme_code = 0x00000048A4, .pme_short_desc = "Fetching is stopped due to an incoming instruction that will result in a flush", .pme_long_desc = "Fetching is stopped due to an incoming instruction that will result in a flush", }, /* See also alternate entries for 0000010000 / POWER9_PME_PM_SUSPENDED with code(s) 0000020000 0000030000 0000040000 at the bottom of this table. \n */ [ POWER9_PME_PM_SUSPENDED ] = { .pme_name = "PM_SUSPENDED", .pme_code = 0x0000010000, .pme_short_desc = "Counter OFF", .pme_long_desc = "Counter OFF", }, [ POWER9_PME_PM_SYNC_MRK_BR_LINK ] = { .pme_name = "PM_SYNC_MRK_BR_LINK", .pme_code = 0x0000015152, .pme_short_desc = "Marked Branch and link branch that can cause a synchronous interrupt", .pme_long_desc = "Marked Branch and link branch that can cause a synchronous interrupt", }, [ POWER9_PME_PM_SYNC_MRK_BR_MPRED ] = { .pme_name = "PM_SYNC_MRK_BR_MPRED", .pme_code = 0x000001515C, .pme_short_desc = "Marked Branch mispredict that can cause a synchronous interrupt", .pme_long_desc = "Marked Branch mispredict that can cause a synchronous interrupt", }, [ POWER9_PME_PM_SYNC_MRK_FX_DIVIDE ] = { .pme_name = "PM_SYNC_MRK_FX_DIVIDE", .pme_code = 0x0000015156, .pme_short_desc = "Marked fixed point divide that can cause a synchronous interrupt", .pme_long_desc = "Marked fixed point divide that can cause a synchronous interrupt", }, [ POWER9_PME_PM_SYNC_MRK_L2HIT ] = { .pme_name = "PM_SYNC_MRK_L2HIT", .pme_code = 0x0000015158, .pme_short_desc = "Marked L2 Hits that can throw a synchronous interrupt", .pme_long_desc = "Marked L2 Hits that can throw a synchronous interrupt", }, [ POWER9_PME_PM_SYNC_MRK_L2MISS ] = { .pme_name = "PM_SYNC_MRK_L2MISS", .pme_code = 0x000001515A, .pme_short_desc = "Marked L2 Miss that can throw a synchronous interrupt", .pme_long_desc = "Marked L2 Miss that can throw a synchronous interrupt", }, [ POWER9_PME_PM_SYNC_MRK_L3MISS ] = { .pme_name = "PM_SYNC_MRK_L3MISS", .pme_code = 0x0000015154, .pme_short_desc = "Marked L3 misses that can throw a synchronous interrupt", .pme_long_desc = "Marked L3 misses that can throw a synchronous interrupt", }, [ POWER9_PME_PM_SYNC_MRK_PROBE_NOP ] = { .pme_name = "PM_SYNC_MRK_PROBE_NOP", .pme_code = 0x0000015150, .pme_short_desc = "Marked probeNops which can cause synchronous interrupts", .pme_long_desc = "Marked probeNops which can cause synchronous interrupts", }, [ POWER9_PME_PM_SYS_PUMP_CPRED ] = { .pme_name = "PM_SYS_PUMP_CPRED", .pme_code = 0x0000030050, .pme_short_desc = "Initial and Final Pump Scope was system pump for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)", .pme_long_desc = "Initial and Final Pump Scope was system pump for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)", }, [ POWER9_PME_PM_SYS_PUMP_MPRED_RTY ] = { .pme_name = "PM_SYS_PUMP_MPRED_RTY", .pme_code = 0x0000040050, .pme_short_desc = "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)", .pme_long_desc = "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)", }, [ POWER9_PME_PM_SYS_PUMP_MPRED ] = { .pme_name = "PM_SYS_PUMP_MPRED", .pme_code = 0x0000030052, .pme_short_desc = "Final Pump Scope (system) mispredicted.", .pme_long_desc = "Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)", }, [ POWER9_PME_PM_TABLEWALK_CYC_PREF ] = { .pme_name = "PM_TABLEWALK_CYC_PREF", .pme_code = 0x000000F884, .pme_short_desc = "tablewalk qualified for pte prefetches", .pme_long_desc = "tablewalk qualified for pte prefetches", }, [ POWER9_PME_PM_TABLEWALK_CYC ] = { .pme_name = "PM_TABLEWALK_CYC", .pme_code = 0x0000010026, .pme_short_desc = "Cycles when an instruction tablewalk is active", .pme_long_desc = "Cycles when an instruction tablewalk is active", }, [ POWER9_PME_PM_TAGE_CORRECT_TAKEN_CMPL ] = { .pme_name = "PM_TAGE_CORRECT_TAKEN_CMPL", .pme_code = 0x00000050B4, .pme_short_desc = "The TAGE overrode BHT direction prediction and it was correct.", .pme_long_desc = "The TAGE overrode BHT direction prediction and it was correct. Counted at completion for taken branches only", }, [ POWER9_PME_PM_TAGE_CORRECT ] = { .pme_name = "PM_TAGE_CORRECT", .pme_code = 0x00000058B4, .pme_short_desc = "The TAGE overrode BHT direction prediction and it was correct.", .pme_long_desc = "The TAGE overrode BHT direction prediction and it was correct. Includes taken and not taken and is counted at execution time", }, [ POWER9_PME_PM_TAGE_OVERRIDE_WRONG_SPEC ] = { .pme_name = "PM_TAGE_OVERRIDE_WRONG_SPEC", .pme_code = 0x00000058B8, .pme_short_desc = "The TAGE overrode BHT direction prediction and it was correct.", .pme_long_desc = "The TAGE overrode BHT direction prediction and it was correct. Includes taken and not taken and is counted at execution time", }, [ POWER9_PME_PM_TAGE_OVERRIDE_WRONG ] = { .pme_name = "PM_TAGE_OVERRIDE_WRONG", .pme_code = 0x00000050B8, .pme_short_desc = "The TAGE overrode BHT direction prediction but it was incorrect.", .pme_long_desc = "The TAGE overrode BHT direction prediction but it was incorrect. Counted at completion for taken branches only", }, [ POWER9_PME_PM_TAKEN_BR_MPRED_CMPL ] = { .pme_name = "PM_TAKEN_BR_MPRED_CMPL", .pme_code = 0x0000020056, .pme_short_desc = "Total number of taken branches that were incorrectly predicted as not-taken.", .pme_long_desc = "Total number of taken branches that were incorrectly predicted as not-taken. This event counts branches completed and does not include speculative instructions", }, [ POWER9_PME_PM_TB_BIT_TRANS ] = { .pme_name = "PM_TB_BIT_TRANS", .pme_code = 0x00000300F8, .pme_short_desc = "timebase event", .pme_long_desc = "timebase event", }, [ POWER9_PME_PM_TEND_PEND_CYC ] = { .pme_name = "PM_TEND_PEND_CYC", .pme_code = 0x000000E8B0, .pme_short_desc = "TEND latency per thread", .pme_long_desc = "TEND latency per thread", }, [ POWER9_PME_PM_THRD_ALL_RUN_CYC ] = { .pme_name = "PM_THRD_ALL_RUN_CYC", .pme_code = 0x000002000C, .pme_short_desc = "Cycles in which all the threads have the run latch set", .pme_long_desc = "Cycles in which all the threads have the run latch set", }, [ POWER9_PME_PM_THRD_CONC_RUN_INST ] = { .pme_name = "PM_THRD_CONC_RUN_INST", .pme_code = 0x00000300F4, .pme_short_desc = "PPC Instructions Finished by this thread when all threads in the core had the run-latch set", .pme_long_desc = "PPC Instructions Finished by this thread when all threads in the core had the run-latch set", }, [ POWER9_PME_PM_THRD_PRIO_0_1_CYC ] = { .pme_name = "PM_THRD_PRIO_0_1_CYC", .pme_code = 0x00000040BC, .pme_short_desc = "Cycles thread running at priority level 0 or 1", .pme_long_desc = "Cycles thread running at priority level 0 or 1", }, [ POWER9_PME_PM_THRD_PRIO_2_3_CYC ] = { .pme_name = "PM_THRD_PRIO_2_3_CYC", .pme_code = 0x00000048BC, .pme_short_desc = "Cycles thread running at priority level 2 or 3", .pme_long_desc = "Cycles thread running at priority level 2 or 3", }, [ POWER9_PME_PM_THRD_PRIO_4_5_CYC ] = { .pme_name = "PM_THRD_PRIO_4_5_CYC", .pme_code = 0x0000005080, .pme_short_desc = "Cycles thread running at priority level 4 or 5", .pme_long_desc = "Cycles thread running at priority level 4 or 5", }, [ POWER9_PME_PM_THRD_PRIO_6_7_CYC ] = { .pme_name = "PM_THRD_PRIO_6_7_CYC", .pme_code = 0x0000005880, .pme_short_desc = "Cycles thread running at priority level 6 or 7", .pme_long_desc = "Cycles thread running at priority level 6 or 7", }, [ POWER9_PME_PM_THRESH_ACC ] = { .pme_name = "PM_THRESH_ACC", .pme_code = 0x0000024154, .pme_short_desc = "This event increments every time the threshold event counter ticks.", .pme_long_desc = "This event increments every time the threshold event counter ticks. Thresholding must be enabled (via MMCRA) and the thresholding start event must occur for this counter to increment. It will stop incrementing when the thresholding stop event occurs or when thresholding is disabled, until the next time a configured thresholding start event occurs.", }, [ POWER9_PME_PM_THRESH_EXC_1024 ] = { .pme_name = "PM_THRESH_EXC_1024", .pme_code = 0x00000301EA, .pme_short_desc = "Threshold counter exceeded a value of 1024", .pme_long_desc = "Threshold counter exceeded a value of 1024", }, [ POWER9_PME_PM_THRESH_EXC_128 ] = { .pme_name = "PM_THRESH_EXC_128", .pme_code = 0x00000401EA, .pme_short_desc = "Threshold counter exceeded a value of 128", .pme_long_desc = "Threshold counter exceeded a value of 128", }, [ POWER9_PME_PM_THRESH_EXC_2048 ] = { .pme_name = "PM_THRESH_EXC_2048", .pme_code = 0x00000401EC, .pme_short_desc = "Threshold counter exceeded a value of 2048", .pme_long_desc = "Threshold counter exceeded a value of 2048", }, [ POWER9_PME_PM_THRESH_EXC_256 ] = { .pme_name = "PM_THRESH_EXC_256", .pme_code = 0x00000101E8, .pme_short_desc = "Threshold counter exceed a count of 256", .pme_long_desc = "Threshold counter exceed a count of 256", }, [ POWER9_PME_PM_THRESH_EXC_32 ] = { .pme_name = "PM_THRESH_EXC_32", .pme_code = 0x00000201E6, .pme_short_desc = "Threshold counter exceeded a value of 32", .pme_long_desc = "Threshold counter exceeded a value of 32", }, [ POWER9_PME_PM_THRESH_EXC_4096 ] = { .pme_name = "PM_THRESH_EXC_4096", .pme_code = 0x00000101E6, .pme_short_desc = "Threshold counter exceed a count of 4096", .pme_long_desc = "Threshold counter exceed a count of 4096", }, [ POWER9_PME_PM_THRESH_EXC_512 ] = { .pme_name = "PM_THRESH_EXC_512", .pme_code = 0x00000201E8, .pme_short_desc = "Threshold counter exceeded a value of 512", .pme_long_desc = "Threshold counter exceeded a value of 512", }, [ POWER9_PME_PM_THRESH_EXC_64 ] = { .pme_name = "PM_THRESH_EXC_64", .pme_code = 0x00000301E8, .pme_short_desc = "Threshold counter exceeded a value of 64", .pme_long_desc = "Threshold counter exceeded a value of 64", }, [ POWER9_PME_PM_THRESH_MET ] = { .pme_name = "PM_THRESH_MET", .pme_code = 0x00000101EC, .pme_short_desc = "threshold exceeded", .pme_long_desc = "threshold exceeded", }, [ POWER9_PME_PM_THRESH_NOT_MET ] = { .pme_name = "PM_THRESH_NOT_MET", .pme_code = 0x000004016E, .pme_short_desc = "Threshold counter did not meet threshold", .pme_long_desc = "Threshold counter did not meet threshold", }, [ POWER9_PME_PM_TLB_HIT ] = { .pme_name = "PM_TLB_HIT", .pme_code = 0x000001F054, .pme_short_desc = "Number of times the TLB had the data required by the instruction.", .pme_long_desc = "Number of times the TLB had the data required by the instruction. Applies to both HPT and RPT", }, [ POWER9_PME_PM_TLBIE_FIN ] = { .pme_name = "PM_TLBIE_FIN", .pme_code = 0x0000030058, .pme_short_desc = "tlbie finished", .pme_long_desc = "tlbie finished", }, [ POWER9_PME_PM_TLB_MISS ] = { .pme_name = "PM_TLB_MISS", .pme_code = 0x0000020066, .pme_short_desc = "TLB Miss (I + D)", .pme_long_desc = "TLB Miss (I + D)", }, [ POWER9_PME_PM_TM_ABORTS ] = { .pme_name = "PM_TM_ABORTS", .pme_code = 0x0000030056, .pme_short_desc = "Number of TM transactions aborted", .pme_long_desc = "Number of TM transactions aborted", }, [ POWER9_PME_PM_TMA_REQ_L2 ] = { .pme_name = "PM_TMA_REQ_L2", .pme_code = 0x000000E0A4, .pme_short_desc = "addrs only req to L2 only on the first one,Indication that Load footprint is not expanding", .pme_long_desc = "addrs only req to L2 only on the first one,Indication that Load footprint is not expanding", }, [ POWER9_PME_PM_TM_CAM_OVERFLOW ] = { .pme_name = "PM_TM_CAM_OVERFLOW", .pme_code = 0x00000168A6, .pme_short_desc = "L3 TM cam overflow during L2 co of SC", .pme_long_desc = "L3 TM cam overflow during L2 co of SC", }, [ POWER9_PME_PM_TM_CAP_OVERFLOW ] = { .pme_name = "PM_TM_CAP_OVERFLOW", .pme_code = 0x000004608E, .pme_short_desc = "TM Footprint Capacity Overflow", .pme_long_desc = "TM Footprint Capacity Overflow", }, [ POWER9_PME_PM_TM_FAIL_CONF_NON_TM ] = { .pme_name = "PM_TM_FAIL_CONF_NON_TM", .pme_code = 0x00000028A8, .pme_short_desc = "TM aborted because a conflict occurred with a non-transactional access by another processor", .pme_long_desc = "TM aborted because a conflict occurred with a non-transactional access by another processor", }, [ POWER9_PME_PM_TM_FAIL_CONF_TM ] = { .pme_name = "PM_TM_FAIL_CONF_TM", .pme_code = 0x00000020AC, .pme_short_desc = "TM aborted because a conflict occurred with another transaction.", .pme_long_desc = "TM aborted because a conflict occurred with another transaction.", }, [ POWER9_PME_PM_TM_FAIL_FOOTPRINT_OVERFLOW ] = { .pme_name = "PM_TM_FAIL_FOOTPRINT_OVERFLOW", .pme_code = 0x00000020A8, .pme_short_desc = "TM aborted because the tracking limit for transactional storage accesses was exceeded.", .pme_long_desc = "TM aborted because the tracking limit for transactional storage accesses was exceeded.. Asynchronous", }, [ POWER9_PME_PM_TM_FAIL_NON_TX_CONFLICT ] = { .pme_name = "PM_TM_FAIL_NON_TX_CONFLICT", .pme_code = 0x000000E0B0, .pme_short_desc = "Non transactional conflict from LSU, gets reported to TEXASR", .pme_long_desc = "Non transactional conflict from LSU, gets reported to TEXASR", }, [ POWER9_PME_PM_TM_FAIL_SELF ] = { .pme_name = "PM_TM_FAIL_SELF", .pme_code = 0x00000028AC, .pme_short_desc = "TM aborted because a self-induced conflict occurred in Suspended state, due to one of the following: a store to a storage location that was previously accessed transactionally; a dcbf, dcbi, or icbi specify- ing a block that was previously accessed transactionally; a dcbst specifying a block that was previously written transactionally; or a tlbie that specifies a translation that was pre- viously used transactionally", .pme_long_desc = "TM aborted because a self-induced conflict occurred in Suspended state, due to one of the following: a store to a storage location that was previously accessed transactionally; a dcbf, dcbi, or icbi specify- ing a block that was previously accessed transactionally; a dcbst specifying a block that was previously written transactionally; or a tlbie that specifies a translation that was pre- viously used transactionally", }, [ POWER9_PME_PM_TM_FAIL_TLBIE ] = { .pme_name = "PM_TM_FAIL_TLBIE", .pme_code = 0x000000E0AC, .pme_short_desc = "Transaction failed because there was a TLBIE hit in the bloom filter", .pme_long_desc = "Transaction failed because there was a TLBIE hit in the bloom filter", }, [ POWER9_PME_PM_TM_FAIL_TX_CONFLICT ] = { .pme_name = "PM_TM_FAIL_TX_CONFLICT", .pme_code = 0x000000E8AC, .pme_short_desc = "Transactional conflict from LSU, gets reported to TEXASR", .pme_long_desc = "Transactional conflict from LSU, gets reported to TEXASR", }, [ POWER9_PME_PM_TM_FAV_CAUSED_FAIL ] = { .pme_name = "PM_TM_FAV_CAUSED_FAIL", .pme_code = 0x000002688E, .pme_short_desc = "TM Load (fav) caused another thread to fail", .pme_long_desc = "TM Load (fav) caused another thread to fail", }, [ POWER9_PME_PM_TM_FAV_TBEGIN ] = { .pme_name = "PM_TM_FAV_TBEGIN", .pme_code = 0x000000209C, .pme_short_desc = "Dispatch time Favored tbegin", .pme_long_desc = "Dispatch time Favored tbegin", }, [ POWER9_PME_PM_TM_LD_CAUSED_FAIL ] = { .pme_name = "PM_TM_LD_CAUSED_FAIL", .pme_code = 0x000001688E, .pme_short_desc = "Non-TM Load caused any thread to fail", .pme_long_desc = "Non-TM Load caused any thread to fail", }, [ POWER9_PME_PM_TM_LD_CONF ] = { .pme_name = "PM_TM_LD_CONF", .pme_code = 0x000002608E, .pme_short_desc = "TM Load (fav or non-fav) ran into conflict (failed)", .pme_long_desc = "TM Load (fav or non-fav) ran into conflict (failed)", }, [ POWER9_PME_PM_TM_NESTED_TBEGIN ] = { .pme_name = "PM_TM_NESTED_TBEGIN", .pme_code = 0x00000020A0, .pme_short_desc = "Completion Tm nested tbegin", .pme_long_desc = "Completion Tm nested tbegin", }, [ POWER9_PME_PM_TM_NESTED_TEND ] = { .pme_name = "PM_TM_NESTED_TEND", .pme_code = 0x0000002098, .pme_short_desc = "Completion time nested tend", .pme_long_desc = "Completion time nested tend", }, [ POWER9_PME_PM_TM_NON_FAV_TBEGIN ] = { .pme_name = "PM_TM_NON_FAV_TBEGIN", .pme_code = 0x000000289C, .pme_short_desc = "Dispatch time non favored tbegin", .pme_long_desc = "Dispatch time non favored tbegin", }, [ POWER9_PME_PM_TM_OUTER_TBEGIN_DISP ] = { .pme_name = "PM_TM_OUTER_TBEGIN_DISP", .pme_code = 0x000004E05E, .pme_short_desc = "Number of outer tbegin instructions dispatched.", .pme_long_desc = "Number of outer tbegin instructions dispatched. The dispatch unit determines whether the tbegin instruction is outer or nested. This is a speculative count, which includes flushed instructions", }, [ POWER9_PME_PM_TM_OUTER_TBEGIN ] = { .pme_name = "PM_TM_OUTER_TBEGIN", .pme_code = 0x0000002094, .pme_short_desc = "Completion time outer tbegin", .pme_long_desc = "Completion time outer tbegin", }, [ POWER9_PME_PM_TM_OUTER_TEND ] = { .pme_name = "PM_TM_OUTER_TEND", .pme_code = 0x0000002894, .pme_short_desc = "Completion time outer tend", .pme_long_desc = "Completion time outer tend", }, [ POWER9_PME_PM_TM_PASSED ] = { .pme_name = "PM_TM_PASSED", .pme_code = 0x000002E052, .pme_short_desc = "Number of TM transactions that passed", .pme_long_desc = "Number of TM transactions that passed", }, [ POWER9_PME_PM_TM_RST_SC ] = { .pme_name = "PM_TM_RST_SC", .pme_code = 0x00000268A6, .pme_short_desc = "TM-snp rst RM SC", .pme_long_desc = "TM-snp rst RM SC", }, [ POWER9_PME_PM_TM_SC_CO ] = { .pme_name = "PM_TM_SC_CO", .pme_code = 0x00000160A6, .pme_short_desc = "L3 castout TM SC line", .pme_long_desc = "L3 castout TM SC line", }, [ POWER9_PME_PM_TM_ST_CAUSED_FAIL ] = { .pme_name = "PM_TM_ST_CAUSED_FAIL", .pme_code = 0x000003688E, .pme_short_desc = "TM Store (fav or non-fav) caused another thread to fail", .pme_long_desc = "TM Store (fav or non-fav) caused another thread to fail", }, [ POWER9_PME_PM_TM_ST_CONF ] = { .pme_name = "PM_TM_ST_CONF", .pme_code = 0x000003608E, .pme_short_desc = "TM Store (fav or non-fav) ran into conflict (failed)", .pme_long_desc = "TM Store (fav or non-fav) ran into conflict (failed)", }, [ POWER9_PME_PM_TM_TABORT_TRECLAIM ] = { .pme_name = "PM_TM_TABORT_TRECLAIM", .pme_code = 0x0000002898, .pme_short_desc = "Completion time tabortnoncd, tabortcd, treclaim", .pme_long_desc = "Completion time tabortnoncd, tabortcd, treclaim", }, [ POWER9_PME_PM_TM_TRANS_RUN_CYC ] = { .pme_name = "PM_TM_TRANS_RUN_CYC", .pme_code = 0x0000010060, .pme_short_desc = "run cycles in transactional state", .pme_long_desc = "run cycles in transactional state", }, [ POWER9_PME_PM_TM_TRANS_RUN_INST ] = { .pme_name = "PM_TM_TRANS_RUN_INST", .pme_code = 0x0000030060, .pme_short_desc = "Run instructions completed in transactional state (gated by the run latch)", .pme_long_desc = "Run instructions completed in transactional state (gated by the run latch)", }, [ POWER9_PME_PM_TM_TRESUME ] = { .pme_name = "PM_TM_TRESUME", .pme_code = 0x00000020A4, .pme_short_desc = "TM resume instruction completed", .pme_long_desc = "TM resume instruction completed", }, [ POWER9_PME_PM_TM_TSUSPEND ] = { .pme_name = "PM_TM_TSUSPEND", .pme_code = 0x00000028A0, .pme_short_desc = "TM suspend instruction completed", .pme_long_desc = "TM suspend instruction completed", }, [ POWER9_PME_PM_TM_TX_PASS_RUN_CYC ] = { .pme_name = "PM_TM_TX_PASS_RUN_CYC", .pme_code = 0x000002E012, .pme_short_desc = "cycles spent in successful transactions", .pme_long_desc = "cycles spent in successful transactions", }, [ POWER9_PME_PM_TM_TX_PASS_RUN_INST ] = { .pme_name = "PM_TM_TX_PASS_RUN_INST", .pme_code = 0x000004E014, .pme_short_desc = "Run instructions spent in successful transactions", .pme_long_desc = "Run instructions spent in successful transactions", }, [ POWER9_PME_PM_VECTOR_FLOP_CMPL ] = { .pme_name = "PM_VECTOR_FLOP_CMPL", .pme_code = 0x000004D058, .pme_short_desc = "Vector FP instruction completed", .pme_long_desc = "Vector FP instruction completed", }, [ POWER9_PME_PM_VECTOR_LD_CMPL ] = { .pme_name = "PM_VECTOR_LD_CMPL", .pme_code = 0x0000044054, .pme_short_desc = "Number of vector load instructions completed", .pme_long_desc = "Number of vector load instructions completed", }, [ POWER9_PME_PM_VECTOR_ST_CMPL ] = { .pme_name = "PM_VECTOR_ST_CMPL", .pme_code = 0x0000044056, .pme_short_desc = "Number of vector store instructions completed", .pme_long_desc = "Number of vector store instructions completed", }, [ POWER9_PME_PM_VSU_DP_FSQRT_FDIV ] = { .pme_name = "PM_VSU_DP_FSQRT_FDIV", .pme_code = 0x000003D058, .pme_short_desc = "vector versions of fdiv,fsqrt", .pme_long_desc = "vector versions of fdiv,fsqrt", }, [ POWER9_PME_PM_VSU_FIN ] = { .pme_name = "PM_VSU_FIN", .pme_code = 0x000002505C, .pme_short_desc = "VSU instruction finished.", .pme_long_desc = "VSU instruction finished. Up to 4 per cycle", }, [ POWER9_PME_PM_VSU_FSQRT_FDIV ] = { .pme_name = "PM_VSU_FSQRT_FDIV", .pme_code = 0x000004D04E, .pme_short_desc = "four flops operation (fdiv,fsqrt) Scalar Instructions only", .pme_long_desc = "four flops operation (fdiv,fsqrt) Scalar Instructions only", }, [ POWER9_PME_PM_VSU_NON_FLOP_CMPL ] = { .pme_name = "PM_VSU_NON_FLOP_CMPL", .pme_code = 0x000004D050, .pme_short_desc = "Non FLOP operation completed", .pme_long_desc = "Non FLOP operation completed", }, [ POWER9_PME_PM_XLATE_HPT_MODE ] = { .pme_name = "PM_XLATE_HPT_MODE", .pme_code = 0x000000F098, .pme_short_desc = "LSU reports every cycle the thread is in HPT translation mode (as opposed to radix mode)", .pme_long_desc = "LSU reports every cycle the thread is in HPT translation mode (as opposed to radix mode)", }, [ POWER9_PME_PM_XLATE_MISS ] = { .pme_name = "PM_XLATE_MISS", .pme_code = 0x000000F89C, .pme_short_desc = "The LSU requested a line from L2 for translation.", .pme_long_desc = "The LSU requested a line from L2 for translation. It may be satisfied from any source beyond L2. Includes speculative instructions", }, [ POWER9_PME_PM_XLATE_RADIX_MODE ] = { .pme_name = "PM_XLATE_RADIX_MODE", .pme_code = 0x000000F898, .pme_short_desc = "LSU reports every cycle the thread is in radix translation mode (as opposed to HPT mode)", .pme_long_desc = "LSU reports every cycle the thread is in radix translation mode (as opposed to HPT mode)", }, [ POWER9_PME_PM_BR_2PATH_ALT ] = { .pme_name = "PM_BR_2PATH_ALT", .pme_code = 0x0000040036, .pme_short_desc = "Branches that are not strongly biased", .pme_long_desc = "Branches that are not strongly biased", }, [ POWER9_PME_PM_CYC_ALT ] = { .pme_name = "PM_CYC_ALT", .pme_code = 0x000002001E, .pme_short_desc = "Processor cycles", .pme_long_desc = "Processor cycles", }, [ POWER9_PME_PM_CYC_ALT2 ] = { .pme_name = "PM_CYC_ALT2", .pme_code = 0x000003001E, .pme_short_desc = "Processor cycles", .pme_long_desc = "Processor cycles", }, [ POWER9_PME_PM_CYC_ALT3 ] = { .pme_name = "PM_CYC_ALT3", .pme_code = 0x000004001E, .pme_short_desc = "Processor cycles", .pme_long_desc = "Processor cycles", }, [ POWER9_PME_PM_INST_CMPL_ALT ] = { .pme_name = "PM_INST_CMPL_ALT", .pme_code = 0x0000020002, .pme_short_desc = "Number of PowerPC Instructions that completed.", .pme_long_desc = "Number of PowerPC Instructions that completed.", }, [ POWER9_PME_PM_INST_CMPL_ALT2 ] = { .pme_name = "PM_INST_CMPL_ALT2", .pme_code = 0x0000030002, .pme_short_desc = "Number of PowerPC Instructions that completed.", .pme_long_desc = "Number of PowerPC Instructions that completed.", }, [ POWER9_PME_PM_INST_CMPL_ALT3 ] = { .pme_name = "PM_INST_CMPL_ALT3", .pme_code = 0x0000040002, .pme_short_desc = "Number of PowerPC Instructions that completed.", .pme_long_desc = "Number of PowerPC Instructions that completed.", }, [ POWER9_PME_PM_INST_DISP_ALT ] = { .pme_name = "PM_INST_DISP_ALT", .pme_code = 0x00000300F2, .pme_short_desc = "# PPC Dispatched", .pme_long_desc = "# PPC Dispatched", }, [ POWER9_PME_PM_LD_MISS_L1_ALT ] = { .pme_name = "PM_LD_MISS_L1_ALT", .pme_code = 0x00000400F0, .pme_short_desc = "Load Missed L1, counted at execution time (can be greater than loads finished).", .pme_long_desc = "Load Missed L1, counted at execution time (can be greater than loads finished). LMQ merges are not included in this count. i.e. if a load instruction misses on an address that is already allocated on the LMQ, this event will not increment for that load). Note that this count is per slice, so if a load spans multiple slices this event will increment multiple times for a single load.", }, [ POWER9_PME_PM_SUSPENDED_ALT ] = { .pme_name = "PM_SUSPENDED_ALT", .pme_code = 0x0000020000, .pme_short_desc = "Counter OFF", .pme_long_desc = "Counter OFF", }, [ POWER9_PME_PM_SUSPENDED_ALT2 ] = { .pme_name = "PM_SUSPENDED_ALT2", .pme_code = 0x0000030000, .pme_short_desc = "Counter OFF", .pme_long_desc = "Counter OFF", }, [ POWER9_PME_PM_SUSPENDED_ALT3 ] = { .pme_name = "PM_SUSPENDED_ALT3", .pme_code = 0x0000040000, .pme_short_desc = "Counter OFF", .pme_long_desc = "Counter OFF", }, /* total 957 */ }; #endif libpfm-4.9.0/lib/events/amd64_events_fam10h.h0000664000175000017500000021055213223402656020501 0ustar eranianeranian/* * Copyright (c) 2011 Google, Inc * Contributed by Stephane Eranian * * Regenerated from previous version by: * Copyright (c) 2007 Advanced Micro Devices, Inc. * Contributed by Robert Richter * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * This file has been automatically generated. * * PMU: amd64_fam10h (AMD64 Fam10h) */ /* History * * May 28 2010 -- Robert Richter, robert.richter@amd.com: * * Update from: BIOS and Kernel Developer's Guide (BKDG) For AMD * Family 10h Processors, 31116 Rev 3.48 - April 22, 2010 * * Feb 06 2009 -- Robert Richter, robert.richter@amd.com: * * Update for Family 10h RevD (Istanbul) from: BIOS and Kernel * Developer's Guide (BKDG) For AMD Family 10h Processors, 31116 Rev * 3.20 - February 04, 2009 * This file has been automatically generated. * * Update for Family 10h RevC (Shanghai) from: BIOS and Kernel * Developer's Guide (BKDG) For AMD Family 10h Processors, 31116 Rev * 3.20 - February 04, 2009 * * * Dec 12 2007 -- Robert Richter, robert.richter@amd.com: * * Created from: BIOS and Kernel Developer's Guide (BKDG) For AMD * Family 10h Processors, 31116 Rev 3.00 - September 07, 2007 * PMU: amd64_fam10h (AMD64 Fam10h) */ static const amd64_umask_t amd64_fam10h_dispatched_fpu[]={ { .uname = "OPS_ADD", .udesc = "Add pipe ops excluding load ops and SSE move ops", .ucode = 0x1, }, { .uname = "OPS_MULTIPLY", .udesc = "Multiply pipe ops excluding load ops and SSE move ops", .ucode = 0x2, }, { .uname = "OPS_STORE", .udesc = "Store pipe ops excluding load ops and SSE move ops", .ucode = 0x4, }, { .uname = "OPS_ADD_PIPE_LOAD_OPS", .udesc = "Add pipe load ops and SSE move ops", .ucode = 0x8, }, { .uname = "OPS_MULTIPLY_PIPE_LOAD_OPS", .udesc = "Multiply pipe load ops and SSE move ops", .ucode = 0x10, }, { .uname = "OPS_STORE_PIPE_LOAD_OPS", .udesc = "Store pipe load ops and SSE move ops", .ucode = 0x20, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam10h_retired_sse_operations[]={ { .uname = "SINGLE_ADD_SUB_OPS", .udesc = "Single precision add/subtract ops", .ucode = 0x1, }, { .uname = "SINGLE_MUL_OPS", .udesc = "Single precision multiply ops", .ucode = 0x2, }, { .uname = "SINGLE_DIV_OPS", .udesc = "Single precision divide/square root ops", .ucode = 0x4, }, { .uname = "DOUBLE_ADD_SUB_OPS", .udesc = "Double precision add/subtract ops", .ucode = 0x8, }, { .uname = "DOUBLE_MUL_OPS", .udesc = "Double precision multiply ops", .ucode = 0x10, }, { .uname = "DOUBLE_DIV_OPS", .udesc = "Double precision divide/square root ops", .ucode = 0x20, }, { .uname = "OP_TYPE", .udesc = "Op type: 0=uops. 1=FLOPS", .ucode = 0x40, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x7f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam10h_retired_move_ops[]={ { .uname = "LOW_QW_MOVE_UOPS", .udesc = "Merging low quadword move uops", .ucode = 0x1, }, { .uname = "HIGH_QW_MOVE_UOPS", .udesc = "Merging high quadword move uops", .ucode = 0x2, }, { .uname = "ALL_OTHER_MERGING_MOVE_UOPS", .udesc = "All other merging move uops", .ucode = 0x4, }, { .uname = "ALL_OTHER_MOVE_UOPS", .udesc = "All other move uops", .ucode = 0x8, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xf, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam10h_retired_serializing_ops[]={ { .uname = "SSE_BOTTOM_EXECUTING_UOPS", .udesc = "SSE bottom-executing uops retired", .ucode = 0x1, }, { .uname = "SSE_BOTTOM_SERIALIZING_UOPS", .udesc = "SSE bottom-serializing uops retired", .ucode = 0x2, }, { .uname = "X87_BOTTOM_EXECUTING_UOPS", .udesc = "X87 bottom-executing uops retired", .ucode = 0x4, }, { .uname = "X87_BOTTOM_SERIALIZING_UOPS", .udesc = "X87 bottom-serializing uops retired", .ucode = 0x8, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xf, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam10h_fp_scheduler_cycles[]={ { .uname = "BOTTOM_EXECUTE_CYCLES", .udesc = "Number of cycles a bottom-execute uop is in the FP scheduler", .ucode = 0x1, }, { .uname = "BOTTOM_SERIALIZING_CYCLES", .udesc = "Number of cycles a bottom-serializing uop is in the FP scheduler", .ucode = 0x2, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam10h_segment_register_loads[]={ { .uname = "ES", .udesc = "ES", .ucode = 0x1, }, { .uname = "CS", .udesc = "CS", .ucode = 0x2, }, { .uname = "SS", .udesc = "SS", .ucode = 0x4, }, { .uname = "DS", .udesc = "DS", .ucode = 0x8, }, { .uname = "FS", .udesc = "FS", .ucode = 0x10, }, { .uname = "GS", .udesc = "GS", .ucode = 0x20, }, { .uname = "HS", .udesc = "HS", .ucode = 0x40, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x7f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam10h_locked_ops[]={ { .uname = "EXECUTED", .udesc = "The number of locked instructions executed", .ucode = 0x1, }, { .uname = "CYCLES_SPECULATIVE_PHASE", .udesc = "The number of cycles spent in speculative phase", .ucode = 0x2, }, { .uname = "CYCLES_NON_SPECULATIVE_PHASE", .udesc = "The number of cycles spent in non-speculative phase (including cache miss penalty)", .ucode = 0x4, }, { .uname = "CYCLES_WAITING", .udesc = "The number of cycles waiting for a cache hit (cache miss penalty).", .ucode = 0x8, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xf, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam10h_cancelled_store_to_load_forward_operations[]={ { .uname = "ADDRESS_MISMATCHES", .udesc = "Address mismatches (starting byte not the same).", .ucode = 0x1, }, { .uname = "STORE_IS_SMALLER_THAN_LOAD", .udesc = "Store is smaller than load.", .ucode = 0x2, }, { .uname = "MISALIGNED", .udesc = "Misaligned.", .ucode = 0x4, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x7, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam10h_data_cache_refills[]={ { .uname = "SYSTEM", .udesc = "Refill from the Northbridge", .ucode = 0x1, }, { .uname = "L2_SHARED", .udesc = "Shared-state line from L2", .ucode = 0x2, }, { .uname = "L2_EXCLUSIVE", .udesc = "Exclusive-state line from L2", .ucode = 0x4, }, { .uname = "L2_OWNED", .udesc = "Owned-state line from L2", .ucode = 0x8, }, { .uname = "L2_MODIFIED", .udesc = "Modified-state line from L2", .ucode = 0x10, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x1f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam10h_data_cache_refills_from_system[]={ { .uname = "INVALID", .udesc = "Invalid", .ucode = 0x1, }, { .uname = "SHARED", .udesc = "Shared", .ucode = 0x2, }, { .uname = "EXCLUSIVE", .udesc = "Exclusive", .ucode = 0x4, }, { .uname = "OWNED", .udesc = "Owned", .ucode = 0x8, }, { .uname = "MODIFIED", .udesc = "Modified", .ucode = 0x10, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x1f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam10h_data_cache_lines_evicted[]={ { .uname = "INVALID", .udesc = "Invalid", .ucode = 0x1, }, { .uname = "SHARED", .udesc = "Shared", .ucode = 0x2, }, { .uname = "EXCLUSIVE", .udesc = "Exclusive", .ucode = 0x4, }, { .uname = "OWNED", .udesc = "Owned", .ucode = 0x8, }, { .uname = "MODIFIED", .udesc = "Modified", .ucode = 0x10, }, { .uname = "BY_PREFETCHNTA", .udesc = "Cache line evicted was brought into the cache with by a PrefetchNTA instruction.", .ucode = 0x20, }, { .uname = "NOT_BY_PREFETCHNTA", .udesc = "Cache line evicted was not brought into the cache with by a PrefetchNTA instruction.", .ucode = 0x40, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x7f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam10h_l1_dtlb_miss_and_l2_dtlb_hit[]={ { .uname = "L2_4K_TLB_HIT", .udesc = "L2 4K TLB hit", .ucode = 0x1, }, { .uname = "L2_2M_TLB_HIT", .udesc = "L2 2M TLB hit", .ucode = 0x2, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL | AMD64_FL_TILL_FAM10H_REV_B, }, { .uname = "L2_1G_TLB_HIT", .udesc = "L2 1G TLB hit", .ucode = 0x4, .uflags= AMD64_FL_FAM10H_REV_C, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x7, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL | AMD64_FL_FAM10H_REV_C, }, }; static const amd64_umask_t amd64_fam10h_l1_dtlb_and_l2_dtlb_miss[]={ { .uname = "4K_TLB_RELOAD", .udesc = "4K TLB reload", .ucode = 0x1, }, { .uname = "2M_TLB_RELOAD", .udesc = "2M TLB reload", .ucode = 0x2, }, { .uname = "1G_TLB_RELOAD", .udesc = "1G TLB reload", .ucode = 0x4, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x7, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam10h_scrubber_single_bit_ecc_errors[]={ { .uname = "SCRUBBER_ERROR", .udesc = "Scrubber error", .ucode = 0x1, }, { .uname = "PIGGYBACK_ERROR", .udesc = "Piggyback scrubber errors", .ucode = 0x2, }, { .uname = "LOAD_PIPE_ERROR", .udesc = "Load pipe error", .ucode = 0x4, }, { .uname = "STORE_WRITE_PIPE_ERROR", .udesc = "Store write pipe error", .ucode = 0x8, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xf, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam10h_prefetch_instructions_dispatched[]={ { .uname = "LOAD", .udesc = "Load (Prefetch, PrefetchT0/T1/T2)", .ucode = 0x1, }, { .uname = "STORE", .udesc = "Store (PrefetchW)", .ucode = 0x2, }, { .uname = "NTA", .udesc = "NTA (PrefetchNTA)", .ucode = 0x4, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x7, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam10h_dcache_misses_by_locked_instructions[]={ { .uname = "DATA_CACHE_MISSES_BY_LOCKED_INSTRUCTIONS", .udesc = "Data cache misses by locked instructions", .ucode = 0x2, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x2, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam10h_l1_dtlb_hit[]={ { .uname = "L1_4K_TLB_HIT", .udesc = "L1 4K TLB hit", .ucode = 0x1, }, { .uname = "L1_2M_TLB_HIT", .udesc = "L1 2M TLB hit", .ucode = 0x2, }, { .uname = "L1_1G_TLB_HIT", .udesc = "L1 1G TLB hit", .ucode = 0x4, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x7, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam10h_ineffective_sw_prefetches[]={ { .uname = "SW_PREFETCH_HIT_IN_L1", .udesc = "Software prefetch hit in the L1.", .ucode = 0x1, }, { .uname = "SW_PREFETCH_HIT_IN_L2", .udesc = "Software prefetch hit in L2.", .ucode = 0x8, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x9, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam10h_memory_requests[]={ { .uname = "NON_CACHEABLE", .udesc = "Requests to non-cacheable (UC) memory", .ucode = 0x1, }, { .uname = "WRITE_COMBINING", .udesc = "Requests to write-combining (WC) memory or WC buffer flushes to WB memory", .ucode = 0x2, }, { .uname = "STREAMING_STORE", .udesc = "Streaming store (SS) requests", .ucode = 0x80, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x83, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam10h_data_prefetches[]={ { .uname = "CANCELLED", .udesc = "Cancelled prefetches", .ucode = 0x1, }, { .uname = "ATTEMPTED", .udesc = "Prefetch attempts", .ucode = 0x2, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam10h_mab_requests[]={ { .uname = "BUFFER_0", .udesc = "Buffer 0", .ucode = 0x0, .uflags= AMD64_FL_NCOMBO, }, { .uname = "BUFFER_1", .udesc = "Buffer 1", .ucode = 0x1, .uflags= AMD64_FL_NCOMBO, }, { .uname = "BUFFER_2", .udesc = "Buffer 2", .ucode = 0x2, .uflags= AMD64_FL_NCOMBO, }, { .uname = "BUFFER_3", .udesc = "Buffer 3", .ucode = 0x3, .uflags= AMD64_FL_NCOMBO, }, { .uname = "BUFFER_4", .udesc = "Buffer 4", .ucode = 0x4, .uflags= AMD64_FL_NCOMBO, }, { .uname = "BUFFER_5", .udesc = "Buffer 5", .ucode = 0x5, .uflags= AMD64_FL_NCOMBO, }, { .uname = "BUFFER_6", .udesc = "Buffer 6", .ucode = 0x6, .uflags= AMD64_FL_NCOMBO, }, { .uname = "BUFFER_7", .udesc = "Buffer 7", .ucode = 0x7, .uflags= AMD64_FL_NCOMBO, }, { .uname = "BUFFER_8", .udesc = "Buffer 8", .ucode = 0x8, .uflags= AMD64_FL_NCOMBO, }, { .uname = "BUFFER_9", .udesc = "Buffer 9", .ucode = 0x9, .uflags= AMD64_FL_NCOMBO, }, }; static const amd64_umask_t amd64_fam10h_system_read_responses[]={ { .uname = "EXCLUSIVE", .udesc = "Exclusive", .ucode = 0x1, }, { .uname = "MODIFIED", .udesc = "Modified", .ucode = 0x2, }, { .uname = "SHARED", .udesc = "Shared", .ucode = 0x4, }, { .uname = "OWNED", .udesc = "Owned", .ucode = 0x8, }, { .uname = "DATA_ERROR", .udesc = "Data Error", .ucode = 0x10, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x1f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam10h_quadwords_written_to_system[]={ { .uname = "QUADWORD_WRITE_TRANSFER", .udesc = "Octword write transfer", .ucode = 0x1, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x1, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam10h_requests_to_l2[]={ { .uname = "INSTRUCTIONS", .udesc = "IC fill", .ucode = 0x1, }, { .uname = "DATA", .udesc = "DC fill", .ucode = 0x2, }, { .uname = "TLB_WALK", .udesc = "TLB fill (page table walks)", .ucode = 0x4, }, { .uname = "SNOOP", .udesc = "Tag snoop request", .ucode = 0x8, }, { .uname = "CANCELLED", .udesc = "Cancelled request", .ucode = 0x10, }, { .uname = "HW_PREFETCH_FROM_DC", .udesc = "Hardware prefetch from DC", .ucode = 0x20, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam10h_l2_cache_miss[]={ { .uname = "INSTRUCTIONS", .udesc = "IC fill", .ucode = 0x1, }, { .uname = "DATA", .udesc = "DC fill (includes possible replays, whereas EventSelect 041h does not)", .ucode = 0x2, }, { .uname = "TLB_WALK", .udesc = "TLB page table walk", .ucode = 0x4, }, { .uname = "HW_PREFETCH_FROM_DC", .udesc = "Hardware prefetch from DC", .ucode = 0x8, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xf, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam10h_l2_fill_writeback[]={ { .uname = "L2_FILLS", .udesc = "L2 fills (victims from L1 caches, TLB page table walks and data prefetches)", .ucode = 0x1, }, { .uname = "L2_WRITEBACKS", .udesc = "L2 Writebacks to system.", .ucode = 0x2, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam10h_l1_itlb_miss_and_l2_itlb_miss[]={ { .uname = "4K_PAGE_FETCHES", .udesc = "Instruction fetches to a 4K page.", .ucode = 0x1, }, { .uname = "2M_PAGE_FETCHES", .udesc = "Instruction fetches to a 2M page.", .ucode = 0x2, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam10h_instruction_cache_lines_invalidated[]={ { .uname = "INVALIDATING_PROBE_NO_IN_FLIGHT", .udesc = "Invalidating probe that did not hit any in-flight instructions.", .ucode = 0x1, }, { .uname = "INVALIDATING_PROBE_ONE_OR_MORE_IN_FLIGHT", .udesc = "Invalidating probe that hit one or more in-flight instructions.", .ucode = 0x2, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam10h_retired_mmx_and_fp_instructions[]={ { .uname = "X87", .udesc = "X87 instructions", .ucode = 0x1, }, { .uname = "MMX_AND_3DNOW", .udesc = "MMX and 3DNow! instructions", .ucode = 0x2, }, { .uname = "PACKED_SSE_AND_SSE2", .udesc = "SSE instructions (SSE, SSE2, SSE3, and SSE4A)", .ucode = 0x4, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x7, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam10h_retired_fastpath_double_op_instructions[]={ { .uname = "POSITION_0", .udesc = "With low op in position 0", .ucode = 0x1, }, { .uname = "POSITION_1", .udesc = "With low op in position 1", .ucode = 0x2, }, { .uname = "POSITION_2", .udesc = "With low op in position 2", .ucode = 0x4, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x7, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam10h_fpu_exceptions[]={ { .uname = "X87_RECLASS_MICROFAULTS", .udesc = "X87 reclass microfaults", .ucode = 0x1, }, { .uname = "SSE_RETYPE_MICROFAULTS", .udesc = "SSE retype microfaults", .ucode = 0x2, }, { .uname = "SSE_RECLASS_MICROFAULTS", .udesc = "SSE reclass microfaults", .ucode = 0x4, }, { .uname = "SSE_AND_X87_MICROTRAPS", .udesc = "SSE and x87 microtraps", .ucode = 0x8, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xf, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam10h_dram_accesses_page[]={ { .uname = "HIT", .udesc = "DCT0 Page hit", .ucode = 0x1, }, { .uname = "MISS", .udesc = "DCT0 Page Miss", .ucode = 0x2, }, { .uname = "CONFLICT", .udesc = "DCT0 Page Conflict", .ucode = 0x4, }, { .uname = "DCT1_PAGE_HIT", .udesc = "DCT1 Page hit", .ucode = 0x8, }, { .uname = "DCT1_PAGE_MISS", .udesc = "DCT1 Page Miss", .ucode = 0x10, }, { .uname = "DCT1_PAGE_CONFLICT", .udesc = "DCT1 Page Conflict", .ucode = 0x20, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam10h_memory_controller_page_table_overflows[]={ { .uname = "DCT0_PAGE_TABLE_OVERFLOW", .udesc = "DCT0 Page Table Overflow", .ucode = 0x1, }, { .uname = "DCT1_PAGE_TABLE_OVERFLOW", .udesc = "DCT1 Page Table Overflow", .ucode = 0x2, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam10h_memory_controller_slot_misses[]={ { .uname = "DCT0_COMMAND_SLOTS_MISSED", .udesc = "DCT0 Command Slots Missed", .ucode = 0x1, }, { .uname = "DCT1_COMMAND_SLOTS_MISSED", .udesc = "DCT1 Command Slots Missed", .ucode = 0x2, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam10h_memory_controller_turnarounds[]={ { .uname = "CHIP_SELECT", .udesc = "DCT0 DIMM (chip select) turnaround", .ucode = 0x1, }, { .uname = "READ_TO_WRITE", .udesc = "DCT0 Read to write turnaround", .ucode = 0x2, }, { .uname = "WRITE_TO_READ", .udesc = "DCT0 Write to read turnaround", .ucode = 0x4, }, { .uname = "DCT1_DIMM", .udesc = "DCT1 DIMM (chip select) turnaround", .ucode = 0x8, }, { .uname = "DCT1_READ_TO_WRITE_TURNAROUND", .udesc = "DCT1 Read to write turnaround", .ucode = 0x10, }, { .uname = "DCT1_WRITE_TO_READ_TURNAROUND", .udesc = "DCT1 Write to read turnaround", .ucode = 0x20, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam10h_memory_controller_bypass[]={ { .uname = "HIGH_PRIORITY", .udesc = "Memory controller high priority bypass", .ucode = 0x1, }, { .uname = "LOW_PRIORITY", .udesc = "Memory controller medium priority bypass", .ucode = 0x2, }, { .uname = "DRAM_INTERFACE", .udesc = "DCT0 DCQ bypass", .ucode = 0x4, }, { .uname = "DRAM_QUEUE", .udesc = "DCT1 DCQ bypass", .ucode = 0x8, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xf, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam10h_thermal_status_and_ecc_errors[]={ { .uname = "CLKS_DIE_TEMP_TOO_HIGH", .udesc = "Number of times the HTC trip point is crossed", .ucode = 0x4, }, { .uname = "CLKS_TEMP_THRESHOLD_EXCEEDED", .udesc = "Number of clocks when STC trip point active", .ucode = 0x8, }, { .uname = "STC_TRIP_POINTS_CROSSED", .udesc = "Number of times the STC trip point is crossed", .ucode = 0x10, }, { .uname = "CLOCKS_HTC_P_STATE_INACTIVE", .udesc = "Number of clocks HTC P-state is inactive.", .ucode = 0x20, }, { .uname = "CLOCKS_HTC_P_STATE_ACTIVE", .udesc = "Number of clocks HTC P-state is active", .ucode = 0x40, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x7c, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam10h_cpu_io_requests_to_memory_io[]={ { .uname = "I_O_TO_I_O", .udesc = "IO to IO", .ucode = 0x1, }, { .uname = "I_O_TO_MEM", .udesc = "IO to Mem", .ucode = 0x2, }, { .uname = "CPU_TO_I_O", .udesc = "CPU to IO", .ucode = 0x4, }, { .uname = "CPU_TO_MEM", .udesc = "CPU to Mem", .ucode = 0x8, }, { .uname = "TO_REMOTE_NODE", .udesc = "To remote node", .ucode = 0x10, }, { .uname = "TO_LOCAL_NODE", .udesc = "To local node", .ucode = 0x20, }, { .uname = "FROM_REMOTE_NODE", .udesc = "From remote node", .ucode = 0x40, }, { .uname = "FROM_LOCAL_NODE", .udesc = "From local node", .ucode = 0x80, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xff, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam10h_cache_block[]={ { .uname = "VICTIM_WRITEBACK", .udesc = "Victim Block (Writeback)", .ucode = 0x1, }, { .uname = "DCACHE_LOAD_MISS", .udesc = "Read Block (Dcache load miss refill)", .ucode = 0x4, }, { .uname = "SHARED_ICACHE_REFILL", .udesc = "Read Block Shared (Icache refill)", .ucode = 0x8, }, { .uname = "READ_BLOCK_MODIFIED", .udesc = "Read Block Modified (Dcache store miss refill)", .ucode = 0x10, }, { .uname = "READ_TO_DIRTY", .udesc = "Change-to-Dirty (first store to clean block already in cache)", .ucode = 0x20, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3d, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam10h_sized_commands[]={ { .uname = "NON_POSTED_WRITE_BYTE", .udesc = "Non-Posted SzWr Byte (1-32 bytes) Legacy or mapped IO, typically 1-4 bytes", .ucode = 0x1, }, { .uname = "NON_POSTED_WRITE_DWORD", .udesc = "Non-Posted SzWr DW (1-16 dwords) Legacy or mapped IO, typically 1 DWORD", .ucode = 0x2, }, { .uname = "POSTED_WRITE_BYTE", .udesc = "Posted SzWr Byte (1-32 bytes) Subcache-line DMA writes, size varies; also flushes of partially-filled Write Combining buffer", .ucode = 0x4, }, { .uname = "POSTED_WRITE_DWORD", .udesc = "Posted SzWr DW (1-16 dwords) Block-oriented DMA writes, often cache-line sized; also processor Write Combining buffer flushes", .ucode = 0x8, }, { .uname = "READ_BYTE_4_BYTES", .udesc = "SzRd Byte (4 bytes) Legacy or mapped IO", .ucode = 0x10, }, { .uname = "READ_DWORD_1_16_DWORDS", .udesc = "SzRd DW (1-16 dwords) Block-oriented DMA reads, typically cache-line size", .ucode = 0x20, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam10h_probe[]={ { .uname = "MISS", .udesc = "Probe miss", .ucode = 0x1, }, { .uname = "HIT_CLEAN", .udesc = "Probe hit clean", .ucode = 0x2, }, { .uname = "HIT_DIRTY_NO_MEMORY_CANCEL", .udesc = "Probe hit dirty without memory cancel (probed by Sized Write or Change2Dirty)", .ucode = 0x4, }, { .uname = "HIT_DIRTY_WITH_MEMORY_CANCEL", .udesc = "Probe hit dirty with memory cancel (probed by DMA read or cache refill request)", .ucode = 0x8, }, { .uname = "UPSTREAM_DISPLAY_REFRESH_READS", .udesc = "Upstream display refresh/ISOC reads", .ucode = 0x10, }, { .uname = "UPSTREAM_NON_DISPLAY_REFRESH_READS", .udesc = "Upstream non-display refresh reads", .ucode = 0x20, }, { .uname = "UPSTREAM_WRITES", .udesc = "Upstream ISOC writes", .ucode = 0x40, }, { .uname = "UPSTREAM_NON_ISOC_WRITES", .udesc = "Upstream non-ISOC writes", .ucode = 0x80, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xff, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam10h_gart[]={ { .uname = "APERTURE_HIT_FROM_CPU", .udesc = "GART aperture hit on access from CPU", .ucode = 0x1, }, { .uname = "APERTURE_HIT_FROM_IO", .udesc = "GART aperture hit on access from IO", .ucode = 0x2, }, { .uname = "MISS", .udesc = "GART miss", .ucode = 0x4, }, { .uname = "REQUEST_HIT_TABLE_WALK", .udesc = "GART/DEV Request hit table walk in progress", .ucode = 0x8, }, { .uname = "DEV_HIT", .udesc = "DEV hit", .ucode = 0x10, }, { .uname = "DEV_MISS", .udesc = "DEV miss", .ucode = 0x20, }, { .uname = "DEV_ERROR", .udesc = "DEV error", .ucode = 0x40, }, { .uname = "MULTIPLE_TABLE_WALK", .udesc = "GART/DEV multiple table walk in progress", .ucode = 0x80, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xff, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam10h_memory_controller_requests[]={ { .uname = "WRITE_REQUESTS", .udesc = "Write requests sent to the DCT", .ucode = 0x1, }, { .uname = "READ_REQUESTS", .udesc = "Read requests (including prefetch requests) sent to the DCT", .ucode = 0x2, }, { .uname = "PREFETCH_REQUESTS", .udesc = "Prefetch requests sent to the DCT", .ucode = 0x4, }, { .uname = "32_BYTES_WRITES", .udesc = "32 Bytes Sized Writes", .ucode = 0x8, }, { .uname = "64_BYTES_WRITES", .udesc = "64 Bytes Sized Writes", .ucode = 0x10, }, { .uname = "32_BYTES_READS", .udesc = "32 Bytes Sized Reads", .ucode = 0x20, }, { .uname = "64_BYTES_READS", .udesc = "64 Byte Sized Reads", .ucode = 0x40, }, { .uname = "READ_REQUESTS_WHILE_WRITES_REQUESTS", .udesc = "Read requests sent to the DCT while writes requests are pending in the DCT", .ucode = 0x80, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xff, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam10h_cpu_to_dram_requests_to_target_node[]={ { .uname = "LOCAL_TO_0", .udesc = "From Local node to Node 0", .ucode = 0x1, }, { .uname = "LOCAL_TO_1", .udesc = "From Local node to Node 1", .ucode = 0x2, }, { .uname = "LOCAL_TO_2", .udesc = "From Local node to Node 2", .ucode = 0x4, }, { .uname = "LOCAL_TO_3", .udesc = "From Local node to Node 3", .ucode = 0x8, }, { .uname = "LOCAL_TO_4", .udesc = "From Local node to Node 4", .ucode = 0x10, }, { .uname = "LOCAL_TO_5", .udesc = "From Local node to Node 5", .ucode = 0x20, }, { .uname = "LOCAL_TO_6", .udesc = "From Local node to Node 6", .ucode = 0x40, }, { .uname = "LOCAL_TO_7", .udesc = "From Local node to Node 7", .ucode = 0x80, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xff, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam10h_cpu_read_command_latency_to_target_node_0_3[]={ { .uname = "READ_BLOCK", .udesc = "Read block", .ucode = 0x1, }, { .uname = "READ_BLOCK_SHARED", .udesc = "Read block shared", .ucode = 0x2, }, { .uname = "READ_BLOCK_MODIFIED", .udesc = "Read block modified", .ucode = 0x4, }, { .uname = "CHANGE_TO_DIRTY", .udesc = "Change-to-Dirty", .ucode = 0x8, }, { .uname = "LOCAL_TO_0", .udesc = "From Local node to Node 0", .ucode = 0x10, }, { .uname = "LOCAL_TO_1", .udesc = "From Local node to Node 1", .ucode = 0x20, }, { .uname = "LOCAL_TO_2", .udesc = "From Local node to Node 2", .ucode = 0x40, }, { .uname = "LOCAL_TO_3", .udesc = "From Local node to Node 3", .ucode = 0x80, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xff, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam10h_cpu_read_command_latency_to_target_node_4_7[]={ { .uname = "READ_BLOCK", .udesc = "Read block", .ucode = 0x1, }, { .uname = "READ_BLOCK_SHARED", .udesc = "Read block shared", .ucode = 0x2, }, { .uname = "READ_BLOCK_MODIFIED", .udesc = "Read block modified", .ucode = 0x4, }, { .uname = "CHANGE_TO_DIRTY", .udesc = "Change-to-Dirty", .ucode = 0x8, }, { .uname = "LOCAL_TO_4", .udesc = "From Local node to Node 4", .ucode = 0x10, }, { .uname = "LOCAL_TO_5", .udesc = "From Local node to Node 5", .ucode = 0x20, }, { .uname = "LOCAL_TO_6", .udesc = "From Local node to Node 6", .ucode = 0x40, }, { .uname = "LOCAL_TO_7", .udesc = "From Local node to Node 7", .ucode = 0x80, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xff, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam10h_cpu_command_latency_to_target_node_0_3_4_7[]={ { .uname = "READ_SIZED", .udesc = "Read Sized", .ucode = 0x1, }, { .uname = "WRITE_SIZED", .udesc = "Write Sized", .ucode = 0x2, }, { .uname = "VICTIM_BLOCK", .udesc = "Victim Block", .ucode = 0x4, }, { .uname = "NODE_GROUP_SELECT", .udesc = "Node Group Select. 0=Nodes 0-3. 1= Nodes 4-7.", .ucode = 0x8, }, { .uname = "LOCAL_TO_0_4", .udesc = "From Local node to Node 0/4", .ucode = 0x10, }, { .uname = "LOCAL_TO_1_5", .udesc = "From Local node to Node 1/5", .ucode = 0x20, }, { .uname = "LOCAL_TO_2_6", .udesc = "From Local node to Node 2/6", .ucode = 0x40, }, { .uname = "LOCAL_TO_3_7", .udesc = "From Local node to Node 3/7", .ucode = 0x80, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xff, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam10h_hypertransport_link0[]={ { .uname = "COMMAND_DWORD_SENT", .udesc = "Command DWORD sent", .ucode = 0x1, .grpid = 0, }, { .uname = "DATA_DWORD_SENT", .udesc = "Data DWORD sent", .ucode = 0x2, .grpid = 0, }, { .uname = "BUFFER_RELEASE_DWORD_SENT", .udesc = "Buffer release DWORD sent", .ucode = 0x4, .grpid = 0, }, { .uname = "NOP_DWORD_SENT", .udesc = "Nop DW sent (idle)", .ucode = 0x8, .grpid = 0, }, { .uname = "ADDRESS_EXT_DWORD_SENT", .udesc = "Address extension DWORD sent", .ucode = 0x10, .grpid = 0, }, { .uname = "PER_PACKET_CRC_SENT", .udesc = "Per packet CRC sent", .ucode = 0x20, .grpid = 0, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, .grpid = 0, }, { .uname = "SUBLINK_MASK", .udesc = "SubLink Mask", .ucode = 0x80, .uflags= AMD64_FL_OMIT, .grpid = 1, }, }; static const amd64_umask_t amd64_fam10h_hypertransport_link3[]={ { .uname = "COMMAND_DWORD_SENT", .udesc = "Command DWORD sent", .ucode = 0x1, .grpid = 0, }, { .uname = "DATA_DWORD_SENT", .udesc = "Data DWORD sent", .ucode = 0x2, .grpid = 0, }, { .uname = "BUFFER_RELEASE_DWORD_SENT", .udesc = "Buffer release DWORD sent", .ucode = 0x4, .grpid = 0, }, { .uname = "NOP_DWORD_SENT", .udesc = "Nop DW sent (idle)", .ucode = 0x8, .grpid = 0, }, { .uname = "ADDRESS_EXT_DWORD_SENT", .udesc = "Address DWORD sent", .ucode = 0x10, .grpid = 0, }, { .uname = "PER_PACKET_CRC_SENT", .udesc = "Per packet CRC sent", .ucode = 0x20, .grpid = 0, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, .grpid = 0, }, { .uname = "SUBLINK_MASK", .udesc = "SubLink Mask", .ucode = 0x80, .uflags= AMD64_FL_OMIT, .grpid = 1, }, }; static const amd64_umask_t amd64_fam10h_read_request_to_l3_cache[]={ { .uname = "READ_BLOCK_EXCLUSIVE", .udesc = "Read Block Exclusive (Data cache read)", .ucode = 0x1, .grpid = 0, }, { .uname = "READ_BLOCK_SHARED", .udesc = "Read Block Shared (Instruction cache read)", .ucode = 0x2, .grpid = 0, }, { .uname = "READ_BLOCK_MODIFY", .udesc = "Read Block Modify", .ucode = 0x4, .grpid = 0, }, { .uname = "ANY_READ", .udesc = "Any read modes (exclusive, shared, modify)", .ucode = 0x7, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, .grpid = 0, }, { .uname = "ALL_CORES", .udesc = "All sub-events selected", .ucode = 0xf0, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, .grpid = 1, }, }; static const amd64_umask_t amd64_fam10h_l3_cache_misses[]={ { .uname = "READ_BLOCK_EXCLUSIVE", .udesc = "Read Block Exclusive (Data cache read)", .ucode = 0x1, .grpid = 0, }, { .uname = "READ_BLOCK_SHARED", .udesc = "Read Block Shared (Instruction cache read)", .ucode = 0x2, .grpid = 0, }, { .uname = "READ_BLOCK_MODIFY", .udesc = "Read Block Modify", .ucode = 0x4, .grpid = 0, }, { .uname = "ANY_READ", .udesc = "Any read modes (exclusive, shared, modify)", .ucode = 0x7, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, .grpid = 0, }, { .uname = "ALL_CORES", .udesc = "All cores", .ucode = 0xf0, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, .grpid = 1, }, }; static const amd64_umask_t amd64_fam10h_l3_fills_caused_by_l2_evictions[]={ { .uname = "SHARED", .udesc = "Shared", .ucode = 0x1, .grpid = 0, }, { .uname = "EXCLUSIVE", .udesc = "Exclusive", .ucode = 0x2, .grpid = 0, }, { .uname = "OWNED", .udesc = "Owned", .ucode = 0x4, .grpid = 0, }, { .uname = "MODIFIED", .udesc = "Modified", .ucode = 0x8, .grpid = 0, }, { .uname = "ANY_STATE", .udesc = "Any line state (shared, owned, exclusive, modified)", .ucode = 0xf, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, .grpid = 0, }, { .uname = "ALL_CORES", .udesc = "All cores", .ucode = 0xf0, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, .grpid = 1, }, }; static const amd64_umask_t amd64_fam10h_l3_evictions[]={ { .uname = "SHARED", .udesc = "Shared", .ucode = 0x1, }, { .uname = "EXCLUSIVE", .udesc = "Exclusive", .ucode = 0x2, }, { .uname = "OWNED", .udesc = "Owned", .ucode = 0x4, }, { .uname = "MODIFIED", .udesc = "Modified", .ucode = 0x8, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xf, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam10h_page_size_mismatches[]={ { .uname = "GUEST_LARGER", .udesc = "Guest page size is larger than the host page size.", .ucode = 0x1, }, { .uname = "MTRR_MISMATCH", .udesc = "MTRR mismatch.", .ucode = 0x2, }, { .uname = "HOST_LARGER", .udesc = "Host page size is larger than the guest page size.", .ucode = 0x4, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x7, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_fam10h_retired_x87_ops[]={ { .uname = "ADD_SUB_OPS", .udesc = "Add/subtract ops", .ucode = 0x1, }, { .uname = "MUL_OPS", .udesc = "Multiply ops", .ucode = 0x2, }, { .uname = "DIV_OPS", .udesc = "Divide ops", .ucode = 0x4, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x7, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_entry_t amd64_fam10h_pe[]={ { .name = "DISPATCHED_FPU", .desc = "Dispatched FPU Operations", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x0, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_dispatched_fpu), .ngrp = 1, .umasks = amd64_fam10h_dispatched_fpu, }, { .name = "CYCLES_NO_FPU_OPS_RETIRED", .desc = "Cycles in which the FPU is Empty", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x1, }, { .name = "DISPATCHED_FPU_OPS_FAST_FLAG", .desc = "Dispatched Fast Flag FPU Operations", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x2, }, { .name = "RETIRED_SSE_OPERATIONS", .desc = "Retired SSE Operations", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x3, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_retired_sse_operations), .ngrp = 1, .umasks = amd64_fam10h_retired_sse_operations, }, { .name = "RETIRED_MOVE_OPS", .desc = "Retired Move Ops", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x4, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_retired_move_ops), .ngrp = 1, .umasks = amd64_fam10h_retired_move_ops, }, { .name = "RETIRED_SERIALIZING_OPS", .desc = "Retired Serializing Ops", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x5, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_retired_serializing_ops), .ngrp = 1, .umasks = amd64_fam10h_retired_serializing_ops, }, { .name = "FP_SCHEDULER_CYCLES", .desc = "Number of Cycles that a Serializing uop is in the FP Scheduler", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x6, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_fp_scheduler_cycles), .ngrp = 1, .umasks = amd64_fam10h_fp_scheduler_cycles, }, { .name = "SEGMENT_REGISTER_LOADS", .desc = "Segment Register Loads", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x20, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_segment_register_loads), .ngrp = 1, .umasks = amd64_fam10h_segment_register_loads, }, { .name = "PIPELINE_RESTART_DUE_TO_SELF_MODIFYING_CODE", .desc = "Pipeline Restart Due to Self-Modifying Code", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x21, }, { .name = "PIPELINE_RESTART_DUE_TO_PROBE_HIT", .desc = "Pipeline Restart Due to Probe Hit", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x22, }, { .name = "LS_BUFFER_2_FULL_CYCLES", .desc = "LS Buffer 2 Full", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x23, }, { .name = "LOCKED_OPS", .desc = "Locked Operations", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x24, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_locked_ops), .ngrp = 1, .umasks = amd64_fam10h_locked_ops, }, { .name = "RETIRED_CLFLUSH_INSTRUCTIONS", .desc = "Retired CLFLUSH Instructions", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x26, }, { .name = "RETIRED_CPUID_INSTRUCTIONS", .desc = "Retired CPUID Instructions", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x27, }, { .name = "CANCELLED_STORE_TO_LOAD_FORWARD_OPERATIONS", .desc = "Cancelled Store to Load Forward Operations", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x2a, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_cancelled_store_to_load_forward_operations), .ngrp = 1, .umasks = amd64_fam10h_cancelled_store_to_load_forward_operations, }, { .name = "SMIS_RECEIVED", .desc = "SMIs Received", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x2b, }, { .name = "DATA_CACHE_ACCESSES", .desc = "Data Cache Accesses", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x40, }, { .name = "DATA_CACHE_MISSES", .desc = "Data Cache Misses", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x41, }, { .name = "DATA_CACHE_REFILLS", .desc = "Data Cache Refills from L2 or Northbridge", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x42, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_data_cache_refills), .ngrp = 1, .umasks = amd64_fam10h_data_cache_refills, }, { .name = "DATA_CACHE_REFILLS_FROM_SYSTEM", .desc = "Data Cache Refills from the Northbridge", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x43, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_data_cache_refills_from_system), .ngrp = 1, .umasks = amd64_fam10h_data_cache_refills_from_system, }, { .name = "DATA_CACHE_LINES_EVICTED", .desc = "Data Cache Lines Evicted", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x44, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_data_cache_lines_evicted), .ngrp = 1, .umasks = amd64_fam10h_data_cache_lines_evicted, }, { .name = "L1_DTLB_MISS_AND_L2_DTLB_HIT", .desc = "L1 DTLB Miss and L2 DTLB Hit", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x45, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_l1_dtlb_miss_and_l2_dtlb_hit), .ngrp = 1, .umasks = amd64_fam10h_l1_dtlb_miss_and_l2_dtlb_hit, }, { .name = "L1_DTLB_AND_L2_DTLB_MISS", .desc = "L1 DTLB and L2 DTLB Miss", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x46, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_l1_dtlb_and_l2_dtlb_miss), .ngrp = 1, .umasks = amd64_fam10h_l1_dtlb_and_l2_dtlb_miss, }, { .name = "MISALIGNED_ACCESSES", .desc = "Misaligned Accesses", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x47, }, { .name = "MICROARCHITECTURAL_LATE_CANCEL_OF_AN_ACCESS", .desc = "Microarchitectural Late Cancel of an Access", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x48, }, { .name = "MICROARCHITECTURAL_EARLY_CANCEL_OF_AN_ACCESS", .desc = "Microarchitectural Early Cancel of an Access", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x49, }, { .name = "SCRUBBER_SINGLE_BIT_ECC_ERRORS", .desc = "Single-bit ECC Errors Recorded by Scrubber", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x4a, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_scrubber_single_bit_ecc_errors), .ngrp = 1, .umasks = amd64_fam10h_scrubber_single_bit_ecc_errors, }, { .name = "PREFETCH_INSTRUCTIONS_DISPATCHED", .desc = "Prefetch Instructions Dispatched", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x4b, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_prefetch_instructions_dispatched), .ngrp = 1, .umasks = amd64_fam10h_prefetch_instructions_dispatched, }, { .name = "DCACHE_MISSES_BY_LOCKED_INSTRUCTIONS", .desc = "DCACHE Misses by Locked Instructions", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x4c, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_dcache_misses_by_locked_instructions), .ngrp = 1, .umasks = amd64_fam10h_dcache_misses_by_locked_instructions, }, { .name = "L1_DTLB_HIT", .desc = "L1 DTLB Hit", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x4d, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_l1_dtlb_hit), .ngrp = 1, .umasks = amd64_fam10h_l1_dtlb_hit, }, { .name = "INEFFECTIVE_SW_PREFETCHES", .desc = "Ineffective Software Prefetches", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x52, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_ineffective_sw_prefetches), .ngrp = 1, .umasks = amd64_fam10h_ineffective_sw_prefetches, }, { .name = "GLOBAL_TLB_FLUSHES", .desc = "Global TLB Flushes", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x54, }, { .name = "MEMORY_REQUESTS", .desc = "Memory Requests by Type", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x65, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_memory_requests), .ngrp = 1, .umasks = amd64_fam10h_memory_requests, }, { .name = "DATA_PREFETCHES", .desc = "Data Prefetcher", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x67, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_data_prefetches), .ngrp = 1, .umasks = amd64_fam10h_data_prefetches, }, { .name = "MAB_REQUESTS", .desc = "Average L1 refill latency for Icache and Dcache misses (request count for cache refills)", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x68, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_mab_requests), .ngrp = 1, .umasks = amd64_fam10h_mab_requests, }, { .name = "MAB_WAIT_CYCLES", .desc = "Average L1 refill latency for Icache and Dcache misses (cycles that requests spent waiting for the refills)", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x69, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_mab_requests), .ngrp = 1, .umasks = amd64_fam10h_mab_requests, /* identical to actual umasks list for this event */ }, { .name = "SYSTEM_READ_RESPONSES", .desc = "Northbridge Read Responses by Coherency State", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x6c, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_system_read_responses), .ngrp = 1, .umasks = amd64_fam10h_system_read_responses, }, { .name = "QUADWORDS_WRITTEN_TO_SYSTEM", .desc = "Octwords Written to System", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x6d, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_quadwords_written_to_system), .ngrp = 1, .umasks = amd64_fam10h_quadwords_written_to_system, }, { .name = "CPU_CLK_UNHALTED", .desc = "CPU Clocks not Halted", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x76, }, { .name = "REQUESTS_TO_L2", .desc = "Requests to L2 Cache", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x7d, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_requests_to_l2), .ngrp = 1, .umasks = amd64_fam10h_requests_to_l2, }, { .name = "L2_CACHE_MISS", .desc = "L2 Cache Misses", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x7e, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_l2_cache_miss), .ngrp = 1, .umasks = amd64_fam10h_l2_cache_miss, }, { .name = "L2_FILL_WRITEBACK", .desc = "L2 Fill/Writeback", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x7f, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_l2_fill_writeback), .ngrp = 1, .umasks = amd64_fam10h_l2_fill_writeback, }, { .name = "INSTRUCTION_CACHE_FETCHES", .desc = "Instruction Cache Fetches", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x80, }, { .name = "INSTRUCTION_CACHE_MISSES", .desc = "Instruction Cache Misses", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x81, }, { .name = "INSTRUCTION_CACHE_REFILLS_FROM_L2", .desc = "Instruction Cache Refills from L2", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x82, }, { .name = "INSTRUCTION_CACHE_REFILLS_FROM_SYSTEM", .desc = "Instruction Cache Refills from System", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x83, }, { .name = "L1_ITLB_MISS_AND_L2_ITLB_HIT", .desc = "L1 ITLB Miss and L2 ITLB Hit", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x84, }, { .name = "L1_ITLB_MISS_AND_L2_ITLB_MISS", .desc = "L1 ITLB Miss and L2 ITLB Miss", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x85, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_l1_itlb_miss_and_l2_itlb_miss), .ngrp = 1, .umasks = amd64_fam10h_l1_itlb_miss_and_l2_itlb_miss, }, { .name = "PIPELINE_RESTART_DUE_TO_INSTRUCTION_STREAM_PROBE", .desc = "Pipeline Restart Due to Instruction Stream Probe", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x86, }, { .name = "INSTRUCTION_FETCH_STALL", .desc = "Instruction Fetch Stall", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x87, }, { .name = "RETURN_STACK_HITS", .desc = "Return Stack Hits", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x88, }, { .name = "RETURN_STACK_OVERFLOWS", .desc = "Return Stack Overflows", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x89, }, { .name = "INSTRUCTION_CACHE_VICTIMS", .desc = "Instruction Cache Victims", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x8b, }, { .name = "INSTRUCTION_CACHE_LINES_INVALIDATED", .desc = "Instruction Cache Lines Invalidated", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x8c, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_instruction_cache_lines_invalidated), .ngrp = 1, .umasks = amd64_fam10h_instruction_cache_lines_invalidated, }, { .name = "ITLB_RELOADS", .desc = "ITLB Reloads", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x99, }, { .name = "ITLB_RELOADS_ABORTED", .desc = "ITLB Reloads Aborted", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x9a, }, { .name = "RETIRED_INSTRUCTIONS", .desc = "Retired Instructions", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xc0, }, { .name = "RETIRED_UOPS", .desc = "Retired uops", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xc1, }, { .name = "RETIRED_BRANCH_INSTRUCTIONS", .desc = "Retired Branch Instructions", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xc2, }, { .name = "RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS", .desc = "Retired Mispredicted Branch Instructions", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xc3, }, { .name = "RETIRED_TAKEN_BRANCH_INSTRUCTIONS", .desc = "Retired Taken Branch Instructions", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xc4, }, { .name = "RETIRED_TAKEN_BRANCH_INSTRUCTIONS_MISPREDICTED", .desc = "Retired Taken Branch Instructions Mispredicted", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xc5, }, { .name = "RETIRED_FAR_CONTROL_TRANSFERS", .desc = "Retired Far Control Transfers", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xc6, }, { .name = "RETIRED_BRANCH_RESYNCS", .desc = "Retired Branch Resyncs", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xc7, }, { .name = "RETIRED_NEAR_RETURNS", .desc = "Retired Near Returns", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xc8, }, { .name = "RETIRED_NEAR_RETURNS_MISPREDICTED", .desc = "Retired Near Returns Mispredicted", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xc9, }, { .name = "RETIRED_INDIRECT_BRANCHES_MISPREDICTED", .desc = "Retired Indirect Branches Mispredicted", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xca, }, { .name = "RETIRED_MMX_AND_FP_INSTRUCTIONS", .desc = "Retired MMX/FP Instructions", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xcb, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_retired_mmx_and_fp_instructions), .ngrp = 1, .umasks = amd64_fam10h_retired_mmx_and_fp_instructions, }, { .name = "RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS", .desc = "Retired Fastpath Double Op Instructions", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xcc, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_retired_fastpath_double_op_instructions), .ngrp = 1, .umasks = amd64_fam10h_retired_fastpath_double_op_instructions, }, { .name = "INTERRUPTS_MASKED_CYCLES", .desc = "Interrupts-Masked Cycles", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xcd, }, { .name = "INTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDING", .desc = "Interrupts-Masked Cycles with Interrupt Pending", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xce, }, { .name = "INTERRUPTS_TAKEN", .desc = "Interrupts Taken", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xcf, }, { .name = "DECODER_EMPTY", .desc = "Decoder Empty", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xd0, }, { .name = "DISPATCH_STALLS", .desc = "Dispatch Stalls", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xd1, }, { .name = "DISPATCH_STALL_FOR_BRANCH_ABORT", .desc = "Dispatch Stall for Branch Abort to Retire", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xd2, }, { .name = "DISPATCH_STALL_FOR_SERIALIZATION", .desc = "Dispatch Stall for Serialization", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xd3, }, { .name = "DISPATCH_STALL_FOR_SEGMENT_LOAD", .desc = "Dispatch Stall for Segment Load", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xd4, }, { .name = "DISPATCH_STALL_FOR_REORDER_BUFFER_FULL", .desc = "Dispatch Stall for Reorder Buffer Full", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xd5, }, { .name = "DISPATCH_STALL_FOR_RESERVATION_STATION_FULL", .desc = "Dispatch Stall for Reservation Station Full", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xd6, }, { .name = "DISPATCH_STALL_FOR_FPU_FULL", .desc = "Dispatch Stall for FPU Full", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xd7, }, { .name = "DISPATCH_STALL_FOR_LS_FULL", .desc = "Dispatch Stall for LS Full", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xd8, }, { .name = "DISPATCH_STALL_WAITING_FOR_ALL_QUIET", .desc = "Dispatch Stall Waiting for All Quiet", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xd9, }, { .name = "DISPATCH_STALL_FOR_FAR_TRANSFER_OR_RSYNC", .desc = "Dispatch Stall for Far Transfer or Resync to Retire", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xda, }, { .name = "FPU_EXCEPTIONS", .desc = "FPU Exceptions", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xdb, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_fpu_exceptions), .ngrp = 1, .umasks = amd64_fam10h_fpu_exceptions, }, { .name = "DR0_BREAKPOINT_MATCHES", .desc = "DR0 Breakpoint Matches", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xdc, }, { .name = "DR1_BREAKPOINT_MATCHES", .desc = "DR1 Breakpoint Matches", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xdd, }, { .name = "DR2_BREAKPOINT_MATCHES", .desc = "DR2 Breakpoint Matches", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xde, }, { .name = "DR3_BREAKPOINT_MATCHES", .desc = "DR3 Breakpoint Matches", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xdf, }, { .name = "DRAM_ACCESSES_PAGE", .desc = "DRAM Accesses", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xe0, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_dram_accesses_page), .ngrp = 1, .umasks = amd64_fam10h_dram_accesses_page, }, { .name = "MEMORY_CONTROLLER_PAGE_TABLE_OVERFLOWS", .desc = "DRAM Controller Page Table Overflows", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xe1, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_memory_controller_page_table_overflows), .ngrp = 1, .umasks = amd64_fam10h_memory_controller_page_table_overflows, }, { .name = "MEMORY_CONTROLLER_SLOT_MISSES", .desc = "Memory Controller DRAM Command Slots Missed", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xe2, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_memory_controller_slot_misses), .ngrp = 1, .umasks = amd64_fam10h_memory_controller_slot_misses, }, { .name = "MEMORY_CONTROLLER_TURNAROUNDS", .desc = "Memory Controller Turnarounds", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xe3, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_memory_controller_turnarounds), .ngrp = 1, .umasks = amd64_fam10h_memory_controller_turnarounds, }, { .name = "MEMORY_CONTROLLER_BYPASS", .desc = "Memory Controller Bypass Counter Saturation", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xe4, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_memory_controller_bypass), .ngrp = 1, .umasks = amd64_fam10h_memory_controller_bypass, }, { .name = "THERMAL_STATUS_AND_ECC_ERRORS", .desc = "Thermal Status", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xe8, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_thermal_status_and_ecc_errors), .ngrp = 1, .umasks = amd64_fam10h_thermal_status_and_ecc_errors, }, { .name = "CPU_IO_REQUESTS_TO_MEMORY_IO", .desc = "CPU/IO Requests to Memory/IO", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xe9, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_cpu_io_requests_to_memory_io), .ngrp = 1, .umasks = amd64_fam10h_cpu_io_requests_to_memory_io, }, { .name = "CACHE_BLOCK", .desc = "Cache Block Commands", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xea, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_cache_block), .ngrp = 1, .umasks = amd64_fam10h_cache_block, }, { .name = "SIZED_COMMANDS", .desc = "Sized Commands", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xeb, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_sized_commands), .ngrp = 1, .umasks = amd64_fam10h_sized_commands, }, { .name = "PROBE", .desc = "Probe Responses and Upstream Requests", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xec, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_probe), .ngrp = 1, .umasks = amd64_fam10h_probe, }, { .name = "GART", .desc = "GART Events", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xee, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_gart), .ngrp = 1, .umasks = amd64_fam10h_gart, }, { .name = "MEMORY_CONTROLLER_REQUESTS", .desc = "Memory Controller Requests", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x1f0, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_memory_controller_requests), .ngrp = 1, .umasks = amd64_fam10h_memory_controller_requests, }, { .name = "CPU_TO_DRAM_REQUESTS_TO_TARGET_NODE", .desc = "CPU to DRAM Requests to Target Node", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x1e0, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_cpu_to_dram_requests_to_target_node), .ngrp = 1, .umasks = amd64_fam10h_cpu_to_dram_requests_to_target_node, }, { .name = "IO_TO_DRAM_REQUESTS_TO_TARGET_NODE", .desc = "IO to DRAM Requests to Target Node", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x1e1, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_cpu_to_dram_requests_to_target_node), .ngrp = 1, .umasks = amd64_fam10h_cpu_to_dram_requests_to_target_node, /* identical to actual umasks list for this event */ }, { .name = "CPU_READ_COMMAND_LATENCY_TO_TARGET_NODE_0_3", .desc = "CPU Read Command Latency to Target Node 0-3", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x1e2, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_cpu_read_command_latency_to_target_node_0_3), .ngrp = 1, .umasks = amd64_fam10h_cpu_read_command_latency_to_target_node_0_3, }, { .name = "CPU_READ_COMMAND_REQUESTS_TO_TARGET_NODE_0_3", .desc = "CPU Read Command Requests to Target Node 0-3", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x1e3, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_cpu_read_command_latency_to_target_node_0_3), .ngrp = 1, .umasks = amd64_fam10h_cpu_read_command_latency_to_target_node_0_3, /* identical to actual umasks list for this event */ }, { .name = "CPU_READ_COMMAND_LATENCY_TO_TARGET_NODE_4_7", .desc = "CPU Read Command Latency to Target Node 4-7", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x1e4, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_cpu_read_command_latency_to_target_node_4_7), .ngrp = 1, .umasks = amd64_fam10h_cpu_read_command_latency_to_target_node_4_7, }, { .name = "CPU_READ_COMMAND_REQUESTS_TO_TARGET_NODE_4_7", .desc = "CPU Read Command Requests to Target Node 4-7", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x1e5, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_cpu_read_command_latency_to_target_node_4_7), .ngrp = 1, .umasks = amd64_fam10h_cpu_read_command_latency_to_target_node_4_7, /* identical to actual umasks list for this event */ }, { .name = "CPU_COMMAND_LATENCY_TO_TARGET_NODE_0_3_4_7", .desc = "CPU Command Latency to Target Node 0-3/4-7", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x1e6, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_cpu_command_latency_to_target_node_0_3_4_7), .ngrp = 1, .umasks = amd64_fam10h_cpu_command_latency_to_target_node_0_3_4_7, }, { .name = "CPU_REQUESTS_TO_TARGET_NODE_0_3_4_7", .desc = "CPU Requests to Target Node 0-3/4-7", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x1e7, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_cpu_command_latency_to_target_node_0_3_4_7), .ngrp = 1, .umasks = amd64_fam10h_cpu_command_latency_to_target_node_0_3_4_7, /* identical to actual umasks list for this event */ }, { .name = "HYPERTRANSPORT_LINK0", .desc = "HyperTransport Link 0 Transmit Bandwidth", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xf6, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_hypertransport_link0), .ngrp = 2, .umasks = amd64_fam10h_hypertransport_link0, }, { .name = "HYPERTRANSPORT_LINK1", .desc = "HyperTransport Link 1 Transmit Bandwidth", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xf7, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_hypertransport_link0), .ngrp = 2, .umasks = amd64_fam10h_hypertransport_link0, /* identical to actual umasks list for this event */ }, { .name = "HYPERTRANSPORT_LINK2", .desc = "HyperTransport Link 2 Transmit Bandwidth", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xf8, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_hypertransport_link0), .ngrp = 2, .umasks = amd64_fam10h_hypertransport_link0, /* identical to actual umasks list for this event */ }, { .name = "HYPERTRANSPORT_LINK3", .desc = "HyperTransport Link 3 Transmit Bandwidth", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x1f9, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_hypertransport_link3), .ngrp = 2, .umasks = amd64_fam10h_hypertransport_link3, }, { .name = "READ_REQUEST_TO_L3_CACHE", .desc = "Read Request to L3 Cache", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x4e0, .flags = AMD64_FL_TILL_FAM10H_REV_C, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_read_request_to_l3_cache), .ngrp = 2, .umasks = amd64_fam10h_read_request_to_l3_cache, }, { .name = "L3_CACHE_MISSES", .desc = "L3 Cache Misses", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x4e1, .flags = AMD64_FL_TILL_FAM10H_REV_C, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_l3_cache_misses), .ngrp = 2, .umasks = amd64_fam10h_l3_cache_misses, }, { .name = "L3_FILLS_CAUSED_BY_L2_EVICTIONS", .desc = "L3 Fills caused by L2 Evictions", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x4e2, .flags = AMD64_FL_TILL_FAM10H_REV_C, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_l3_fills_caused_by_l2_evictions), .ngrp = 2, .umasks = amd64_fam10h_l3_fills_caused_by_l2_evictions, }, { .name = "L3_EVICTIONS", .desc = "L3 Evictions", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x4e3, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_l3_evictions), .ngrp = 1, .umasks = amd64_fam10h_l3_evictions, }, { .name = "PAGE_SIZE_MISMATCHES", .desc = "Page Size Mismatches", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x165, .flags = AMD64_FL_FAM10H_REV_C, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_page_size_mismatches), .ngrp = 1, .umasks = amd64_fam10h_page_size_mismatches, }, { .name = "RETIRED_X87_OPS", .desc = "Retired x87 Floating Point Operations", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x1c0, .flags = AMD64_FL_FAM10H_REV_C, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_retired_x87_ops), .ngrp = 1, .umasks = amd64_fam10h_retired_x87_ops, }, { .name = "IBS_OPS_TAGGED", .desc = "IBS Ops Tagged", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x1cf, .flags = AMD64_FL_FAM10H_REV_C, }, { .name = "LFENCE_INST_RETIRED", .desc = "LFENCE Instructions Retired", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x1d3, .flags = AMD64_FL_FAM10H_REV_C, }, { .name = "SFENCE_INST_RETIRED", .desc = "SFENCE Instructions Retired", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x1d4, .flags = AMD64_FL_FAM10H_REV_C, }, { .name = "MFENCE_INST_RETIRED", .desc = "MFENCE Instructions Retired", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x1d5, .flags = AMD64_FL_FAM10H_REV_C, }, { .name = "READ_REQUEST_TO_L3_CACHE", .desc = "Read Request to L3 Cache", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x4e0, .flags = AMD64_FL_FAM10H_REV_D, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_l3_cache_misses), .ngrp = 2, .umasks = amd64_fam10h_l3_cache_misses, /* identical to actual umasks list for this event */ }, { .name = "L3_CACHE_MISSES", .desc = "L3 Cache Misses", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x4e1, .flags = AMD64_FL_FAM10H_REV_D, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_l3_cache_misses), .ngrp = 2, .umasks = amd64_fam10h_l3_cache_misses, /* identical to actual umasks list for this event */ }, { .name = "L3_FILLS_CAUSED_BY_L2_EVICTIONS", .desc = "L3 Fills caused by L2 Evictions", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x4e2, .flags = AMD64_FL_FAM10H_REV_D, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_l3_fills_caused_by_l2_evictions), .ngrp = 2, .umasks = amd64_fam10h_l3_fills_caused_by_l2_evictions, /* identical to actual umasks list for this event */ }, { .name = "NON_CANCELLED_L3_READ_REQUESTS", .desc = "Non-cancelled L3 Read Requests", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x4ed, .flags = AMD64_FL_FAM10H_REV_D, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_l3_cache_misses), .ngrp = 2, .umasks = amd64_fam10h_l3_cache_misses, /* identical to actual umasks list for this event */ }, }; libpfm-4.9.0/lib/events/amd64_events_k8.h0000664000175000017500000011147513223402656017753 0ustar eranianeranian/* * Copyright (c) 2011 Google, Inc * Contributed by Stephane Eranian * * Regenerated from previous version by: * * Copyright (c) 2006, 2007 Advanced Micro Devices, Inc. * Contributed by Ray Bryant * Contributed by Robert Richter * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * This file has been automatically generated. * * PMU: amd64_k8 (AMD64 K8) */ /* History * * Feb 10 2006 -- Ray Bryant, raybry@mpdtxmail.amd.com * * Brought event table up-to-date with the 3.85 (October 2005) version of the * "BIOS and Kernel Developer's Guide for the AMD Athlon[tm] 64 and * AMD Opteron[tm] Processors," AMD Publication # 26094. * * Dec 12 2007 -- Robert Richter, robert.richter@amd.com * * Updated to: BIOS and Kernel Developer's Guide for AMD NPT Family * 0Fh Processors, Publication # 32559, Revision: 3.08, Issue Date: * July 2007 * * Feb 26 2009 -- Robert Richter, robert.richter@amd.com * * Updates and fixes of some revision flags and descriptions according * to these documents: * BIOS and Kernel Developer's Guide, #26094, Revision: 3.30 * BIOS and Kernel Developer's Guide, #32559, Revision: 3.12 */ static const amd64_umask_t amd64_k8_dispatched_fpu[]={ { .uname = "OPS_ADD", .udesc = "Add pipe ops", .ucode = 0x1, }, { .uname = "OPS_MULTIPLY", .udesc = "Multiply pipe ops", .ucode = 0x2, }, { .uname = "OPS_STORE", .udesc = "Store pipe ops", .ucode = 0x4, }, { .uname = "OPS_ADD_PIPE_LOAD_OPS", .udesc = "Add pipe load ops", .ucode = 0x8, }, { .uname = "OPS_MULTIPLY_PIPE_LOAD_OPS", .udesc = "Multiply pipe load ops", .ucode = 0x10, }, { .uname = "OPS_STORE_PIPE_LOAD_OPS", .udesc = "Store pipe load ops", .ucode = 0x20, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_k8_segment_register_loads[]={ { .uname = "ES", .udesc = "ES", .ucode = 0x1, }, { .uname = "CS", .udesc = "CS", .ucode = 0x2, }, { .uname = "SS", .udesc = "SS", .ucode = 0x4, }, { .uname = "DS", .udesc = "DS", .ucode = 0x8, }, { .uname = "FS", .udesc = "FS", .ucode = 0x10, }, { .uname = "GS", .udesc = "GS", .ucode = 0x20, }, { .uname = "HS", .udesc = "HS", .ucode = 0x40, }, { .uname = "ALL", .udesc = "All segments", .ucode = 0x7f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_k8_locked_ops[]={ { .uname = "EXECUTED", .udesc = "The number of locked instructions executed", .ucode = 0x1, }, { .uname = "CYCLES_SPECULATIVE_PHASE", .udesc = "The number of cycles spent in speculative phase", .ucode = 0x2, }, { .uname = "CYCLES_NON_SPECULATIVE_PHASE", .udesc = "The number of cycles spent in non-speculative phase (including cache miss penalty)", .ucode = 0x4, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x7, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_k8_memory_requests[]={ { .uname = "NON_CACHEABLE", .udesc = "Requests to non-cacheable (UC) memory", .ucode = 0x1, }, { .uname = "WRITE_COMBINING", .udesc = "Requests to write-combining (WC) memory or WC buffer flushes to WB memory", .ucode = 0x2, }, { .uname = "STREAMING_STORE", .udesc = "Streaming store (SS) requests", .ucode = 0x80, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x83, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_k8_data_cache_refills[]={ { .uname = "SYSTEM", .udesc = "Refill from System", .ucode = 0x1, }, { .uname = "L2_SHARED", .udesc = "Shared-state line from L2", .ucode = 0x2, }, { .uname = "L2_EXCLUSIVE", .udesc = "Exclusive-state line from L2", .ucode = 0x4, }, { .uname = "L2_OWNED", .udesc = "Owned-state line from L2", .ucode = 0x8, }, { .uname = "L2_MODIFIED", .udesc = "Modified-state line from L2", .ucode = 0x10, }, { .uname = "ALL", .udesc = "Shared, Exclusive, Owned, Modified State Refills", .ucode = 0x1f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_k8_data_cache_refills_from_system[]={ { .uname = "INVALID", .udesc = "Invalid", .ucode = 0x1, }, { .uname = "SHARED", .udesc = "Shared", .ucode = 0x2, }, { .uname = "EXCLUSIVE", .udesc = "Exclusive", .ucode = 0x4, }, { .uname = "OWNED", .udesc = "Owned", .ucode = 0x8, }, { .uname = "MODIFIED", .udesc = "Modified", .ucode = 0x10, }, { .uname = "ALL", .udesc = "Invalid, Shared, Exclusive, Owned, Modified", .ucode = 0x1f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_k8_scrubber_single_bit_ecc_errors[]={ { .uname = "SCRUBBER_ERROR", .udesc = "Scrubber error", .ucode = 0x1, }, { .uname = "PIGGYBACK_ERROR", .udesc = "Piggyback scrubber errors", .ucode = 0x2, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_k8_prefetch_instructions_dispatched[]={ { .uname = "LOAD", .udesc = "Load (Prefetch, PrefetchT0/T1/T2)", .ucode = 0x1, }, { .uname = "STORE", .udesc = "Store (PrefetchW)", .ucode = 0x2, }, { .uname = "NTA", .udesc = "NTA (PrefetchNTA)", .ucode = 0x4, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x7, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_k8_dcache_misses_by_locked_instructions[]={ { .uname = "DATA_CACHE_MISSES_BY_LOCKED_INSTRUCTIONS", .udesc = "Data cache misses by locked instructions", .ucode = 0x2, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x2, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_k8_data_prefetches[]={ { .uname = "CANCELLED", .udesc = "Cancelled prefetches", .ucode = 0x1, }, { .uname = "ATTEMPTED", .udesc = "Prefetch attempts", .ucode = 0x2, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_k8_system_read_responses[]={ { .uname = "EXCLUSIVE", .udesc = "Exclusive", .ucode = 0x1, }, { .uname = "MODIFIED", .udesc = "Modified", .ucode = 0x2, }, { .uname = "SHARED", .udesc = "Shared", .ucode = 0x4, }, { .uname = "ALL", .udesc = "Exclusive, Modified, Shared", .ucode = 0x7, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_k8_quadwords_written_to_system[]={ { .uname = "QUADWORD_WRITE_TRANSFER", .udesc = "Quadword write transfer", .ucode = 0x1, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x1, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_k8_requests_to_l2[]={ { .uname = "INSTRUCTIONS", .udesc = "IC fill", .ucode = 0x1, }, { .uname = "DATA", .udesc = "DC fill", .ucode = 0x2, }, { .uname = "TLB_WALK", .udesc = "TLB fill (page table walks)", .ucode = 0x4, }, { .uname = "SNOOP", .udesc = "Tag snoop request", .ucode = 0x8, }, { .uname = "CANCELLED", .udesc = "Cancelled request", .ucode = 0x10, }, { .uname = "ALL", .udesc = "All non-cancelled requests", .ucode = 0x1f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_k8_l2_cache_miss[]={ { .uname = "INSTRUCTIONS", .udesc = "IC fill", .ucode = 0x1, }, { .uname = "DATA", .udesc = "DC fill (includes possible replays, whereas event 41h does not)", .ucode = 0x2, }, { .uname = "TLB_WALK", .udesc = "TLB page table walk", .ucode = 0x4, }, { .uname = "ALL", .udesc = "Instructions, Data, TLB walk", .ucode = 0x7, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_k8_l2_fill_writeback[]={ { .uname = "L2_FILLS", .udesc = "L2 fills (victims from L1 caches, TLB page table walks and data prefetches)", .ucode = 0x1, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x1, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL | AMD64_FL_TILL_K8_REV_E, }, { .uname = "L2_WRITEBACKS", .udesc = "L2 Writebacks to system.", .ucode = 0x2, .uflags= AMD64_FL_K8_REV_F, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL | AMD64_FL_K8_REV_F, }, }; static const amd64_umask_t amd64_k8_retired_mmx_and_fp_instructions[]={ { .uname = "X87", .udesc = "X87 instructions", .ucode = 0x1, }, { .uname = "MMX_AND_3DNOW", .udesc = "MMX and 3DNow! instructions", .ucode = 0x2, }, { .uname = "PACKED_SSE_AND_SSE2", .udesc = "Packed SSE and SSE2 instructions", .ucode = 0x4, }, { .uname = "SCALAR_SSE_AND_SSE2", .udesc = "Scalar SSE and SSE2 instructions", .ucode = 0x8, }, { .uname = "ALL", .udesc = "X87, MMX(TM), 3DNow!(TM), Scalar and Packed SSE and SSE2 instructions", .ucode = 0xf, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_k8_retired_fastpath_double_op_instructions[]={ { .uname = "POSITION_0", .udesc = "With low op in position 0", .ucode = 0x1, }, { .uname = "POSITION_1", .udesc = "With low op in position 1", .ucode = 0x2, }, { .uname = "POSITION_2", .udesc = "With low op in position 2", .ucode = 0x4, }, { .uname = "ALL", .udesc = "With low op in position 0, 1, or 2", .ucode = 0x7, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_k8_fpu_exceptions[]={ { .uname = "X87_RECLASS_MICROFAULTS", .udesc = "X87 reclass microfaults", .ucode = 0x1, }, { .uname = "SSE_RETYPE_MICROFAULTS", .udesc = "SSE retype microfaults", .ucode = 0x2, }, { .uname = "SSE_RECLASS_MICROFAULTS", .udesc = "SSE reclass microfaults", .ucode = 0x4, }, { .uname = "SSE_AND_X87_MICROTRAPS", .udesc = "SSE and x87 microtraps", .ucode = 0x8, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xf, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_k8_dram_accesses_page[]={ { .uname = "HIT", .udesc = "Page hit", .ucode = 0x1, }, { .uname = "MISS", .udesc = "Page Miss", .ucode = 0x2, }, { .uname = "CONFLICT", .udesc = "Page Conflict", .ucode = 0x4, }, { .uname = "ALL", .udesc = "Page Hit, Miss, or Conflict", .ucode = 0x7, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_k8_memory_controller_turnarounds[]={ { .uname = "CHIP_SELECT", .udesc = "DIMM (chip select) turnaround", .ucode = 0x1, }, { .uname = "READ_TO_WRITE", .udesc = "Read to write turnaround", .ucode = 0x2, }, { .uname = "WRITE_TO_READ", .udesc = "Write to read turnaround", .ucode = 0x4, }, { .uname = "ALL", .udesc = "All Memory Controller Turnarounds", .ucode = 0x7, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_k8_memory_controller_bypass[]={ { .uname = "HIGH_PRIORITY", .udesc = "Memory controller high priority bypass", .ucode = 0x1, }, { .uname = "LOW_PRIORITY", .udesc = "Memory controller low priority bypass", .ucode = 0x2, }, { .uname = "DRAM_INTERFACE", .udesc = "DRAM controller interface bypass", .ucode = 0x4, }, { .uname = "DRAM_QUEUE", .udesc = "DRAM controller queue bypass", .ucode = 0x8, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xf, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_k8_sized_blocks[]={ { .uname = "32_BYTE_WRITES", .udesc = "32-byte Sized Writes", .ucode = 0x4, }, { .uname = "64_BYTE_WRITES", .udesc = "64-byte Sized Writes", .ucode = 0x8, }, { .uname = "32_BYTE_READS", .udesc = "32-byte Sized Reads", .ucode = 0x10, }, { .uname = "64_BYTE_READS", .udesc = "64-byte Sized Reads", .ucode = 0x20, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3c, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_k8_thermal_status_and_ecc_errors[]={ { .uname = "CLKS_CPU_ACTIVE", .udesc = "Number of clocks CPU is active when HTC is active", .ucode = 0x1, .uflags= AMD64_FL_K8_REV_F, }, { .uname = "CLKS_CPU_INACTIVE", .udesc = "Number of clocks CPU clock is inactive when HTC is active", .ucode = 0x2, .uflags= AMD64_FL_K8_REV_F, }, { .uname = "CLKS_DIE_TEMP_TOO_HIGH", .udesc = "Number of clocks when die temperature is higher than the software high temperature threshold", .ucode = 0x4, .uflags= AMD64_FL_K8_REV_F, }, { .uname = "CLKS_TEMP_THRESHOLD_EXCEEDED", .udesc = "Number of clocks when high temperature threshold was exceeded", .ucode = 0x8, .uflags= AMD64_FL_K8_REV_F, }, { .uname = "DRAM_ECC_ERRORS", .udesc = "Number of correctable and Uncorrectable DRAM ECC errors", .ucode = 0x80, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x80, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL | AMD64_FL_TILL_K8_REV_E, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x8f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL | AMD64_FL_K8_REV_F, }, }; static const amd64_umask_t amd64_k8_cpu_io_requests_to_memory_io[]={ { .uname = "I_O_TO_I_O", .udesc = "I/O to I/O", .ucode = 0x1, }, { .uname = "I_O_TO_MEM", .udesc = "I/O to Mem", .ucode = 0x2, }, { .uname = "CPU_TO_I_O", .udesc = "CPU to I/O", .ucode = 0x4, }, { .uname = "CPU_TO_MEM", .udesc = "CPU to Mem", .ucode = 0x8, }, { .uname = "TO_REMOTE_NODE", .udesc = "To remote node", .ucode = 0x10, }, { .uname = "TO_LOCAL_NODE", .udesc = "To local node", .ucode = 0x20, }, { .uname = "FROM_REMOTE_NODE", .udesc = "From remote node", .ucode = 0x40, }, { .uname = "FROM_LOCAL_NODE", .udesc = "From local node", .ucode = 0x80, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xff, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_k8_cache_block[]={ { .uname = "VICTIM_WRITEBACK", .udesc = "Victim Block (Writeback)", .ucode = 0x1, }, { .uname = "DCACHE_LOAD_MISS", .udesc = "Read Block (Dcache load miss refill)", .ucode = 0x4, }, { .uname = "SHARED_ICACHE_REFILL", .udesc = "Read Block Shared (Icache refill)", .ucode = 0x8, }, { .uname = "READ_BLOCK_MODIFIED", .udesc = "Read Block Modified (Dcache store miss refill)", .ucode = 0x10, }, { .uname = "READ_TO_DIRTY", .udesc = "Change to Dirty (first store to clean block already in cache)", .ucode = 0x20, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3d, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_k8_sized_commands[]={ { .uname = "NON_POSTED_WRITE_BYTE", .udesc = "NonPosted SzWr Byte (1-32 bytes) Legacy or mapped I/O, typically 1-4 bytes", .ucode = 0x1, }, { .uname = "NON_POSTED_WRITE_DWORD", .udesc = "NonPosted SzWr Dword (1-16 dwords) Legacy or mapped I/O, typically 1 dword", .ucode = 0x2, }, { .uname = "POSTED_WRITE_BYTE", .udesc = "Posted SzWr Byte (1-32 bytes) Sub-cache-line DMA writes, size varies; also flushes of partially-filled Write Combining buffer", .ucode = 0x4, }, { .uname = "POSTED_WRITE_DWORD", .udesc = "Posted SzWr Dword (1-16 dwords) Block-oriented DMA writes, often cache-line sized; also processor Write Combining buffer flushes", .ucode = 0x8, }, { .uname = "READ_BYTE_4_BYTES", .udesc = "SzRd Byte (4 bytes) Legacy or mapped I/O", .ucode = 0x10, }, { .uname = "READ_DWORD_1_16_DWORDS", .udesc = "SzRd Dword (1-16 dwords) Block-oriented DMA reads, typically cache-line size", .ucode = 0x20, }, { .uname = "READ_MODIFY_WRITE", .udesc = "RdModWr", .ucode = 0x40, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x7f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_k8_probe[]={ { .uname = "MISS", .udesc = "Probe miss", .ucode = 0x1, }, { .uname = "HIT_CLEAN", .udesc = "Probe hit clean", .ucode = 0x2, }, { .uname = "HIT_DIRTY_NO_MEMORY_CANCEL", .udesc = "Probe hit dirty without memory cancel (probed by Sized Write or Change2Dirty)", .ucode = 0x4, }, { .uname = "HIT_DIRTY_WITH_MEMORY_CANCEL", .udesc = "Probe hit dirty with memory cancel (probed by DMA read or cache refill request)", .ucode = 0x8, }, { .uname = "UPSTREAM_DISPLAY_REFRESH_READS", .udesc = "Upstream display refresh reads", .ucode = 0x10, }, { .uname = "UPSTREAM_NON_DISPLAY_REFRESH_READS", .udesc = "Upstream non-display refresh reads", .ucode = 0x20, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL | AMD64_FL_TILL_K8_REV_C, }, { .uname = "UPSTREAM_WRITES", .udesc = "Upstream writes", .ucode = 0x40, .uflags= AMD64_FL_K8_REV_D, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x7f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL | AMD64_FL_K8_REV_D, }, }; static const amd64_umask_t amd64_k8_gart[]={ { .uname = "APERTURE_HIT_FROM_CPU", .udesc = "GART aperture hit on access from CPU", .ucode = 0x1, }, { .uname = "APERTURE_HIT_FROM_IO", .udesc = "GART aperture hit on access from I/O", .ucode = 0x2, }, { .uname = "MISS", .udesc = "GART miss", .ucode = 0x4, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x7, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_k8_hypertransport_link0[]={ { .uname = "COMMAND_DWORD_SENT", .udesc = "Command dword sent", .ucode = 0x1, }, { .uname = "DATA_DWORD_SENT", .udesc = "Data dword sent", .ucode = 0x2, }, { .uname = "BUFFER_RELEASE_DWORD_SENT", .udesc = "Buffer release dword sent", .ucode = 0x4, }, { .uname = "NOP_DWORD_SENT", .udesc = "Nop dword sent (idle)", .ucode = 0x8, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xf, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_entry_t amd64_k8_pe[]={ { .name = "DISPATCHED_FPU", .desc = "Dispatched FPU Operations", .modmsk = AMD64_BASIC_ATTRS, .code = 0x0, .numasks = LIBPFM_ARRAY_SIZE(amd64_k8_dispatched_fpu), .ngrp = 1, .umasks = amd64_k8_dispatched_fpu, }, { .name = "CYCLES_NO_FPU_OPS_RETIRED", .desc = "Cycles with no FPU Ops Retired", .modmsk = AMD64_BASIC_ATTRS, .code = 0x1, }, { .name = "DISPATCHED_FPU_OPS_FAST_FLAG", .desc = "Dispatched Fast Flag FPU Operations", .modmsk = AMD64_BASIC_ATTRS, .code = 0x2, }, { .name = "SEGMENT_REGISTER_LOADS", .desc = "Segment Register Loads", .modmsk = AMD64_BASIC_ATTRS, .code = 0x20, .numasks = LIBPFM_ARRAY_SIZE(amd64_k8_segment_register_loads), .ngrp = 1, .umasks = amd64_k8_segment_register_loads, }, { .name = "PIPELINE_RESTART_DUE_TO_SELF_MODIFYING_CODE", .desc = "Pipeline restart due to self-modifying code", .modmsk = AMD64_BASIC_ATTRS, .code = 0x21, }, { .name = "PIPELINE_RESTART_DUE_TO_PROBE_HIT", .desc = "Pipeline restart due to probe hit", .modmsk = AMD64_BASIC_ATTRS, .code = 0x22, }, { .name = "LS_BUFFER_2_FULL_CYCLES", .desc = "LS Buffer 2 Full", .modmsk = AMD64_BASIC_ATTRS, .code = 0x23, }, { .name = "LOCKED_OPS", .desc = "Locked Operations", .modmsk = AMD64_BASIC_ATTRS, .code = 0x24, .numasks = LIBPFM_ARRAY_SIZE(amd64_k8_locked_ops), .ngrp = 1, .umasks = amd64_k8_locked_ops, }, { .name = "MEMORY_REQUESTS", .desc = "Memory Requests by Type", .modmsk = AMD64_BASIC_ATTRS, .code = 0x65, .numasks = LIBPFM_ARRAY_SIZE(amd64_k8_memory_requests), .ngrp = 1, .umasks = amd64_k8_memory_requests, }, { .name = "DATA_CACHE_ACCESSES", .desc = "Data Cache Accesses", .modmsk = AMD64_BASIC_ATTRS, .code = 0x40, }, { .name = "DATA_CACHE_MISSES", .desc = "Data Cache Misses", .modmsk = AMD64_BASIC_ATTRS, .code = 0x41, }, { .name = "DATA_CACHE_REFILLS", .desc = "Data Cache Refills from L2 or System", .modmsk = AMD64_BASIC_ATTRS, .code = 0x42, .numasks = LIBPFM_ARRAY_SIZE(amd64_k8_data_cache_refills), .ngrp = 1, .umasks = amd64_k8_data_cache_refills, }, { .name = "DATA_CACHE_REFILLS_FROM_SYSTEM", .desc = "Data Cache Refills from System", .modmsk = AMD64_BASIC_ATTRS, .code = 0x43, .numasks = LIBPFM_ARRAY_SIZE(amd64_k8_data_cache_refills_from_system), .ngrp = 1, .umasks = amd64_k8_data_cache_refills_from_system, }, { .name = "DATA_CACHE_LINES_EVICTED", .desc = "Data Cache Lines Evicted", .modmsk = AMD64_BASIC_ATTRS, .code = 0x44, .numasks = LIBPFM_ARRAY_SIZE(amd64_k8_data_cache_refills_from_system), .ngrp = 1, .umasks = amd64_k8_data_cache_refills_from_system, /* identical to actual umasks list for this event */ }, { .name = "L1_DTLB_MISS_AND_L2_DTLB_HIT", .desc = "L1 DTLB Miss and L2 DTLB Hit", .modmsk = AMD64_BASIC_ATTRS, .code = 0x45, }, { .name = "L1_DTLB_AND_L2_DTLB_MISS", .desc = "L1 DTLB and L2 DTLB Miss", .modmsk = AMD64_BASIC_ATTRS, .code = 0x46, }, { .name = "MISALIGNED_ACCESSES", .desc = "Misaligned Accesses", .modmsk = AMD64_BASIC_ATTRS, .code = 0x47, }, { .name = "MICROARCHITECTURAL_LATE_CANCEL_OF_AN_ACCESS", .desc = "Microarchitectural Late Cancel of an Access", .modmsk = AMD64_BASIC_ATTRS, .code = 0x48, }, { .name = "MICROARCHITECTURAL_EARLY_CANCEL_OF_AN_ACCESS", .desc = "Microarchitectural Early Cancel of an Access", .modmsk = AMD64_BASIC_ATTRS, .code = 0x49, }, { .name = "SCRUBBER_SINGLE_BIT_ECC_ERRORS", .desc = "Single-bit ECC Errors Recorded by Scrubber", .modmsk = AMD64_BASIC_ATTRS, .code = 0x4a, .numasks = LIBPFM_ARRAY_SIZE(amd64_k8_scrubber_single_bit_ecc_errors), .ngrp = 1, .umasks = amd64_k8_scrubber_single_bit_ecc_errors, }, { .name = "PREFETCH_INSTRUCTIONS_DISPATCHED", .desc = "Prefetch Instructions Dispatched", .modmsk = AMD64_BASIC_ATTRS, .code = 0x4b, .numasks = LIBPFM_ARRAY_SIZE(amd64_k8_prefetch_instructions_dispatched), .ngrp = 1, .umasks = amd64_k8_prefetch_instructions_dispatched, }, { .name = "DCACHE_MISSES_BY_LOCKED_INSTRUCTIONS", .desc = "DCACHE Misses by Locked Instructions", .modmsk = AMD64_BASIC_ATTRS, .code = 0x4c, .numasks = LIBPFM_ARRAY_SIZE(amd64_k8_dcache_misses_by_locked_instructions), .ngrp = 1, .umasks = amd64_k8_dcache_misses_by_locked_instructions, }, { .name = "DATA_PREFETCHES", .desc = "Data Prefetcher", .modmsk = AMD64_BASIC_ATTRS, .code = 0x67, .numasks = LIBPFM_ARRAY_SIZE(amd64_k8_data_prefetches), .ngrp = 1, .umasks = amd64_k8_data_prefetches, }, { .name = "SYSTEM_READ_RESPONSES", .desc = "System Read Responses by Coherency State", .modmsk = AMD64_BASIC_ATTRS, .code = 0x6c, .numasks = LIBPFM_ARRAY_SIZE(amd64_k8_system_read_responses), .ngrp = 1, .umasks = amd64_k8_system_read_responses, }, { .name = "QUADWORDS_WRITTEN_TO_SYSTEM", .desc = "Quadwords Written to System", .modmsk = AMD64_BASIC_ATTRS, .code = 0x6d, .numasks = LIBPFM_ARRAY_SIZE(amd64_k8_quadwords_written_to_system), .ngrp = 1, .umasks = amd64_k8_quadwords_written_to_system, }, { .name = "REQUESTS_TO_L2", .desc = "Requests to L2 Cache", .modmsk = AMD64_BASIC_ATTRS, .code = 0x7d, .numasks = LIBPFM_ARRAY_SIZE(amd64_k8_requests_to_l2), .ngrp = 1, .umasks = amd64_k8_requests_to_l2, }, { .name = "L2_CACHE_MISS", .desc = "L2 Cache Misses", .modmsk = AMD64_BASIC_ATTRS, .code = 0x7e, .numasks = LIBPFM_ARRAY_SIZE(amd64_k8_l2_cache_miss), .ngrp = 1, .umasks = amd64_k8_l2_cache_miss, }, { .name = "L2_FILL_WRITEBACK", .desc = "L2 Fill/Writeback", .modmsk = AMD64_BASIC_ATTRS, .code = 0x7f, .numasks = LIBPFM_ARRAY_SIZE(amd64_k8_l2_fill_writeback), .ngrp = 1, .umasks = amd64_k8_l2_fill_writeback, }, { .name = "INSTRUCTION_CACHE_FETCHES", .desc = "Instruction Cache Fetches", .modmsk = AMD64_BASIC_ATTRS, .code = 0x80, }, { .name = "INSTRUCTION_CACHE_MISSES", .desc = "Instruction Cache Misses", .modmsk = AMD64_BASIC_ATTRS, .code = 0x81, }, { .name = "INSTRUCTION_CACHE_REFILLS_FROM_L2", .desc = "Instruction Cache Refills from L2", .modmsk = AMD64_BASIC_ATTRS, .code = 0x82, }, { .name = "INSTRUCTION_CACHE_REFILLS_FROM_SYSTEM", .desc = "Instruction Cache Refills from System", .modmsk = AMD64_BASIC_ATTRS, .code = 0x83, }, { .name = "L1_ITLB_MISS_AND_L2_ITLB_HIT", .desc = "L1 ITLB Miss and L2 ITLB Hit", .modmsk = AMD64_BASIC_ATTRS, .code = 0x84, }, { .name = "L1_ITLB_MISS_AND_L2_ITLB_MISS", .desc = "L1 ITLB Miss and L2 ITLB Miss", .modmsk = AMD64_BASIC_ATTRS, .code = 0x85, }, { .name = "PIPELINE_RESTART_DUE_TO_INSTRUCTION_STREAM_PROBE", .desc = "Pipeline Restart Due to Instruction Stream Probe", .modmsk = AMD64_BASIC_ATTRS, .code = 0x86, }, { .name = "INSTRUCTION_FETCH_STALL", .desc = "Instruction Fetch Stall", .modmsk = AMD64_BASIC_ATTRS, .code = 0x87, }, { .name = "RETURN_STACK_HITS", .desc = "Return Stack Hits", .modmsk = AMD64_BASIC_ATTRS, .code = 0x88, }, { .name = "RETURN_STACK_OVERFLOWS", .desc = "Return Stack Overflows", .modmsk = AMD64_BASIC_ATTRS, .code = 0x89, }, { .name = "RETIRED_CLFLUSH_INSTRUCTIONS", .desc = "Retired CLFLUSH Instructions", .modmsk = AMD64_BASIC_ATTRS, .code = 0x26, }, { .name = "RETIRED_CPUID_INSTRUCTIONS", .desc = "Retired CPUID Instructions", .modmsk = AMD64_BASIC_ATTRS, .code = 0x27, }, { .name = "CPU_CLK_UNHALTED", .desc = "CPU Clocks not Halted", .modmsk = AMD64_BASIC_ATTRS, .code = 0x76, }, { .name = "RETIRED_INSTRUCTIONS", .desc = "Retired Instructions", .modmsk = AMD64_BASIC_ATTRS, .code = 0xc0, }, { .name = "RETIRED_UOPS", .desc = "Retired uops", .modmsk = AMD64_BASIC_ATTRS, .code = 0xc1, }, { .name = "RETIRED_BRANCH_INSTRUCTIONS", .desc = "Retired Branch Instructions", .modmsk = AMD64_BASIC_ATTRS, .code = 0xc2, }, { .name = "RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS", .desc = "Retired Mispredicted Branch Instructions", .modmsk = AMD64_BASIC_ATTRS, .code = 0xc3, }, { .name = "RETIRED_TAKEN_BRANCH_INSTRUCTIONS", .desc = "Retired Taken Branch Instructions", .modmsk = AMD64_BASIC_ATTRS, .code = 0xc4, }, { .name = "RETIRED_TAKEN_BRANCH_INSTRUCTIONS_MISPREDICTED", .desc = "Retired Taken Branch Instructions Mispredicted", .modmsk = AMD64_BASIC_ATTRS, .code = 0xc5, }, { .name = "RETIRED_FAR_CONTROL_TRANSFERS", .desc = "Retired Far Control Transfers", .modmsk = AMD64_BASIC_ATTRS, .code = 0xc6, }, { .name = "RETIRED_BRANCH_RESYNCS", .desc = "Retired Branch Resyncs", .modmsk = AMD64_BASIC_ATTRS, .code = 0xc7, }, { .name = "RETIRED_NEAR_RETURNS", .desc = "Retired Near Returns", .modmsk = AMD64_BASIC_ATTRS, .code = 0xc8, }, { .name = "RETIRED_NEAR_RETURNS_MISPREDICTED", .desc = "Retired Near Returns Mispredicted", .modmsk = AMD64_BASIC_ATTRS, .code = 0xc9, }, { .name = "RETIRED_INDIRECT_BRANCHES_MISPREDICTED", .desc = "Retired Indirect Branches Mispredicted", .modmsk = AMD64_BASIC_ATTRS, .code = 0xca, }, { .name = "RETIRED_MMX_AND_FP_INSTRUCTIONS", .desc = "Retired MMX/FP Instructions", .modmsk = AMD64_BASIC_ATTRS, .code = 0xcb, .numasks = LIBPFM_ARRAY_SIZE(amd64_k8_retired_mmx_and_fp_instructions), .ngrp = 1, .umasks = amd64_k8_retired_mmx_and_fp_instructions, }, { .name = "RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS", .desc = "Retired Fastpath Double Op Instructions", .modmsk = AMD64_BASIC_ATTRS, .code = 0xcc, .numasks = LIBPFM_ARRAY_SIZE(amd64_k8_retired_fastpath_double_op_instructions), .ngrp = 1, .umasks = amd64_k8_retired_fastpath_double_op_instructions, }, { .name = "INTERRUPTS_MASKED_CYCLES", .desc = "Interrupts-Masked Cycles", .modmsk = AMD64_BASIC_ATTRS, .code = 0xcd, }, { .name = "INTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDING", .desc = "Interrupts-Masked Cycles with Interrupt Pending", .modmsk = AMD64_BASIC_ATTRS, .code = 0xce, }, { .name = "INTERRUPTS_TAKEN", .desc = "Interrupts Taken", .modmsk = AMD64_BASIC_ATTRS, .code = 0xcf, }, { .name = "DECODER_EMPTY", .desc = "Decoder Empty", .modmsk = AMD64_BASIC_ATTRS, .code = 0xd0, }, { .name = "DISPATCH_STALLS", .desc = "Dispatch Stalls", .modmsk = AMD64_BASIC_ATTRS, .code = 0xd1, }, { .name = "DISPATCH_STALL_FOR_BRANCH_ABORT", .desc = "Dispatch Stall for Branch Abort to Retire", .modmsk = AMD64_BASIC_ATTRS, .code = 0xd2, }, { .name = "DISPATCH_STALL_FOR_SERIALIZATION", .desc = "Dispatch Stall for Serialization", .modmsk = AMD64_BASIC_ATTRS, .code = 0xd3, }, { .name = "DISPATCH_STALL_FOR_SEGMENT_LOAD", .desc = "Dispatch Stall for Segment Load", .modmsk = AMD64_BASIC_ATTRS, .code = 0xd4, }, { .name = "DISPATCH_STALL_FOR_REORDER_BUFFER_FULL", .desc = "Dispatch Stall for Reorder Buffer Full", .modmsk = AMD64_BASIC_ATTRS, .code = 0xd5, }, { .name = "DISPATCH_STALL_FOR_RESERVATION_STATION_FULL", .desc = "Dispatch Stall for Reservation Station Full", .modmsk = AMD64_BASIC_ATTRS, .code = 0xd6, }, { .name = "DISPATCH_STALL_FOR_FPU_FULL", .desc = "Dispatch Stall for FPU Full", .modmsk = AMD64_BASIC_ATTRS, .code = 0xd7, }, { .name = "DISPATCH_STALL_FOR_LS_FULL", .desc = "Dispatch Stall for LS Full", .modmsk = AMD64_BASIC_ATTRS, .code = 0xd8, }, { .name = "DISPATCH_STALL_WAITING_FOR_ALL_QUIET", .desc = "Dispatch Stall Waiting for All Quiet", .modmsk = AMD64_BASIC_ATTRS, .code = 0xd9, }, { .name = "DISPATCH_STALL_FOR_FAR_TRANSFER_OR_RSYNC", .desc = "Dispatch Stall for Far Transfer or Resync to Retire", .modmsk = AMD64_BASIC_ATTRS, .code = 0xda, }, { .name = "FPU_EXCEPTIONS", .desc = "FPU Exceptions", .modmsk = AMD64_BASIC_ATTRS, .code = 0xdb, .numasks = LIBPFM_ARRAY_SIZE(amd64_k8_fpu_exceptions), .ngrp = 1, .umasks = amd64_k8_fpu_exceptions, }, { .name = "DR0_BREAKPOINT_MATCHES", .desc = "DR0 Breakpoint Matches", .modmsk = AMD64_BASIC_ATTRS, .code = 0xdc, }, { .name = "DR1_BREAKPOINT_MATCHES", .desc = "DR1 Breakpoint Matches", .modmsk = AMD64_BASIC_ATTRS, .code = 0xdd, }, { .name = "DR2_BREAKPOINT_MATCHES", .desc = "DR2 Breakpoint Matches", .modmsk = AMD64_BASIC_ATTRS, .code = 0xde, }, { .name = "DR3_BREAKPOINT_MATCHES", .desc = "DR3 Breakpoint Matches", .modmsk = AMD64_BASIC_ATTRS, .code = 0xdf, }, { .name = "DRAM_ACCESSES_PAGE", .desc = "DRAM Accesses", .modmsk = AMD64_BASIC_ATTRS, .code = 0xe0, .numasks = LIBPFM_ARRAY_SIZE(amd64_k8_dram_accesses_page), .ngrp = 1, .umasks = amd64_k8_dram_accesses_page, }, { .name = "MEMORY_CONTROLLER_PAGE_TABLE_OVERFLOWS", .desc = "Memory Controller Page Table Overflows", .modmsk = AMD64_BASIC_ATTRS, .code = 0xe1, }, { .name = "MEMORY_CONTROLLER_TURNAROUNDS", .desc = "Memory Controller Turnarounds", .modmsk = AMD64_BASIC_ATTRS, .code = 0xe3, .numasks = LIBPFM_ARRAY_SIZE(amd64_k8_memory_controller_turnarounds), .ngrp = 1, .umasks = amd64_k8_memory_controller_turnarounds, }, { .name = "MEMORY_CONTROLLER_BYPASS", .desc = "Memory Controller Bypass Counter Saturation", .modmsk = AMD64_BASIC_ATTRS, .code = 0xe4, .numasks = LIBPFM_ARRAY_SIZE(amd64_k8_memory_controller_bypass), .ngrp = 1, .umasks = amd64_k8_memory_controller_bypass, }, { .name = "SIZED_BLOCKS", .desc = "Sized Blocks", .modmsk = AMD64_BASIC_ATTRS, .code = 0xe5, .flags = AMD64_FL_K8_REV_D, .numasks = LIBPFM_ARRAY_SIZE(amd64_k8_sized_blocks), .ngrp = 1, .umasks = amd64_k8_sized_blocks, }, { .name = "THERMAL_STATUS_AND_ECC_ERRORS", .desc = "Thermal Status and ECC Errors", .modmsk = AMD64_BASIC_ATTRS, .code = 0xe8, .flags = AMD64_FL_K8_REV_E, .numasks = LIBPFM_ARRAY_SIZE(amd64_k8_thermal_status_and_ecc_errors), .ngrp = 1, .umasks = amd64_k8_thermal_status_and_ecc_errors, }, { .name = "CPU_IO_REQUESTS_TO_MEMORY_IO", .desc = "CPU/IO Requests to Memory/IO", .modmsk = AMD64_BASIC_ATTRS, .code = 0xe9, .flags = AMD64_FL_K8_REV_E, .numasks = LIBPFM_ARRAY_SIZE(amd64_k8_cpu_io_requests_to_memory_io), .ngrp = 1, .umasks = amd64_k8_cpu_io_requests_to_memory_io, }, { .name = "CACHE_BLOCK", .desc = "Cache Block Commands", .modmsk = AMD64_BASIC_ATTRS, .code = 0xea, .flags = AMD64_FL_K8_REV_E, .numasks = LIBPFM_ARRAY_SIZE(amd64_k8_cache_block), .ngrp = 1, .umasks = amd64_k8_cache_block, }, { .name = "SIZED_COMMANDS", .desc = "Sized Commands", .modmsk = AMD64_BASIC_ATTRS, .code = 0xeb, .numasks = LIBPFM_ARRAY_SIZE(amd64_k8_sized_commands), .ngrp = 1, .umasks = amd64_k8_sized_commands, }, { .name = "PROBE", .desc = "Probe Responses and Upstream Requests", .modmsk = AMD64_BASIC_ATTRS, .code = 0xec, .numasks = LIBPFM_ARRAY_SIZE(amd64_k8_probe), .ngrp = 1, .umasks = amd64_k8_probe, }, { .name = "GART", .desc = "GART Events", .modmsk = AMD64_BASIC_ATTRS, .code = 0xee, .numasks = LIBPFM_ARRAY_SIZE(amd64_k8_gart), .ngrp = 1, .umasks = amd64_k8_gart, }, { .name = "HYPERTRANSPORT_LINK0", .desc = "HyperTransport Link 0 Transmit Bandwidth", .modmsk = AMD64_BASIC_ATTRS, .code = 0xf6, .numasks = LIBPFM_ARRAY_SIZE(amd64_k8_hypertransport_link0), .ngrp = 1, .umasks = amd64_k8_hypertransport_link0, }, { .name = "HYPERTRANSPORT_LINK1", .desc = "HyperTransport Link 1 Transmit Bandwidth", .modmsk = AMD64_BASIC_ATTRS, .code = 0xf7, .numasks = LIBPFM_ARRAY_SIZE(amd64_k8_hypertransport_link0), .ngrp = 1, .umasks = amd64_k8_hypertransport_link0, /* identical to actual umasks list for this event */ }, { .name = "HYPERTRANSPORT_LINK2", .desc = "HyperTransport Link 2 Transmit Bandwidth", .modmsk = AMD64_BASIC_ATTRS, .code = 0xf8, .numasks = LIBPFM_ARRAY_SIZE(amd64_k8_hypertransport_link0), .ngrp = 1, .umasks = amd64_k8_hypertransport_link0, /* identical to actual umasks list for this event */ }, }; libpfm-4.9.0/lib/events/intel_hswep_unc_qpi_events.h0000664000175000017500000005215413223402656022473 0ustar eranianeranian/* * Copyright (c) 2014 Google Inc. All rights reserved * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * PMU: hswep_unc_qpi (Intel Haswell-EP QPI uncore) */ static const intel_x86_umask_t hswep_unc_q_direct2core[]={ { .uname = "FAILURE_CREDITS", .udesc = "Number of spawn failures due to lack of Egress credits", .ucode = 0x200, }, { .uname = "FAILURE_CREDITS_RBT", .udesc = "Number of spawn failures due to lack of Egress credit and route-back table (RBT) bit was not set", .ucode = 0x800, }, { .uname = "FAILURE_RBT_HIT", .udesc = "Number of spawn failures because route-back table (RBT) specified that the transaction should not trigger a direct2core transaction", .ucode = 0x400, }, { .uname = "SUCCESS_RBT_HIT", .udesc = "Number of spawn successes", .ucode = 0x100, }, { .uname = "FAILURE_MISS", .udesc = "Number of spawn failures due to RBT tag not matching although the valid bit was set and there was enough Egress credits", .ucode = 0x1000, }, { .uname = "FAILURE_CREDITS_MISS", .udesc = "Number of spawn failures due to RBT tag not matching and they were not enough Egress credits. The valid bit was set", .ucode = 0x2000, }, { .uname = "FAILURE_RBT_MISS", .udesc = "Number of spawn failures due to RBT tag not matching, the valid bit was not set but there were enough Egress credits", .ucode = 0x4000, }, { .uname = "FAILURE_CREDITS_RBT_MISS", .udesc = "Number of spawn failures due to RBT tag not matching, the valid bit was not set and there were not enough Egress credits", .ucode = 0x8000, }, }; static const intel_x86_umask_t hswep_unc_q_rxl_credits_consumed_vn0[]={ { .uname = "DRS", .udesc = "Number of times VN0 consumed for DRS message class", .ucode = 0x100, }, { .uname = "HOM", .udesc = "Number of times VN0 consumed for HOM message class", .ucode = 0x800, }, { .uname = "NCB", .udesc = "Number of times VN0 consumed for NCB message class", .ucode = 0x200, }, { .uname = "NCS", .udesc = "Number of times VN0 consumed for NCS message class", .ucode = 0x400, }, { .uname = "NDR", .udesc = "Number of times VN0 consumed for NDR message class", .ucode = 0x2000, }, { .uname = "SNP", .udesc = "Number of times VN0 consumed for SNP message class", .ucode = 0x1000, }, }; static const intel_x86_umask_t hswep_unc_q_rxl_credits_consumed_vn1[]={ { .uname = "DRS", .udesc = "Number of times VN1 consumed for DRS message class", .ucode = 0x100, }, { .uname = "HOM", .udesc = "Number of times VN1 consumed for HOM message class", .ucode = 0x800, }, { .uname = "NCB", .udesc = "Number of times VN1 consumed for NCB message class", .ucode = 0x200, }, { .uname = "NCS", .udesc = "Number of times VN1 consumed for NCS message class", .ucode = 0x400, }, { .uname = "NDR", .udesc = "Number of times VN1 consumed for NDR message class", .ucode = 0x2000, }, { .uname = "SNP", .udesc = "Number of times VN1 consumed for SNP message class", .ucode = 0x1000, }, }; static const intel_x86_umask_t hswep_unc_q_txl_flits_g0[]={ { .uname = "DATA", .udesc = "Number of data flits over QPI", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "NON_DATA", .udesc = "Number of non-NULL non-data flits over QPI", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t hswep_unc_q_rxl_flits_g1[]={ { .uname = "DRS", .udesc = "Number of flits over QPI on the Data Response (DRS) channel", .ucode = 0x1800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "DRS_DATA", .udesc = "Number of data flits over QPI on the Data Response (DRS) channel", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "DRS_NONDATA", .udesc = "Number of protocol flits over QPI on the Data Response (DRS) channel", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "HOM", .udesc = "Number of flits over QPI on the home channel", .ucode = 0x600, .uflags = INTEL_X86_NCOMBO, }, { .uname = "HOM_NONREQ", .udesc = "Number of non-request flits over QPI on the home channel", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "HOM_REQ", .udesc = "Number of data requests over QPI on the home channel", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "SNP", .udesc = "Number of snoop requests flits over QPI", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t hswep_unc_q_rxl_flits_g2[]={ { .uname = "NCB", .udesc = "Number of non-coherent bypass flits", .ucode = 0xc00, .uflags = INTEL_X86_NCOMBO, }, { .uname = "NCB_DATA", .udesc = "Number of non-coherent data flits", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "NCB_NONDATA", .udesc = "Number of bypass non-data flits", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "NCS", .udesc = "Number of non-coherent standard (NCS) flits", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "NDR_AD", .udesc = "Number of flits received over Non-data response (NDR) channel", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "NDR_AK", .udesc = "Number of flits received on the Non-data response (NDR) channel)", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t hswep_unc_q_txr_ad_hom_credit_acquired[]={ { .uname = "VN0", .udesc = "for VN0", .ucode = 0x100, }, { .uname = "VN1", .udesc = "for VN1", .ucode = 0x200, }, }; static const intel_x86_umask_t hswep_unc_q_txr_bl_drs_credit_acquired[]={ { .uname = "VN0", .udesc = "for VN0", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "VN1", .udesc = "for VN1", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "VN_SHR", .udesc = "for shared VN", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_entry_t intel_hswep_unc_q_pe[]={ { .name = "UNC_Q_CLOCKTICKS", .desc = "Number of qfclks", .code = 0x14, .cntmsk = 0xf, .modmsk = HSWEP_UNC_QPI_ATTRS, }, { .name = "UNC_Q_CTO_COUNT", .desc = "Count of CTO Events", .code = 0x38 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = HSWEP_UNC_QPI_ATTRS, }, { .name = "UNC_Q_DIRECT2CORE", .desc = "Direct 2 Core Spawning", .code = 0x13, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_q_direct2core), .umasks = hswep_unc_q_direct2core }, { .name = "UNC_Q_L1_POWER_CYCLES", .desc = "Cycles in L1", .code = 0x12, .cntmsk = 0xf, .modmsk = HSWEP_UNC_QPI_ATTRS, }, { .name = "UNC_Q_RXL0P_POWER_CYCLES", .desc = "Cycles in L0p", .code = 0x10, .cntmsk = 0xf, .modmsk = HSWEP_UNC_QPI_ATTRS, }, { .name = "UNC_Q_RXL0_POWER_CYCLES", .desc = "Cycles in L0", .code = 0xf, .cntmsk = 0xf, .modmsk = HSWEP_UNC_QPI_ATTRS, }, { .name = "UNC_Q_RXL_BYPASSED", .desc = "Rx Flit Buffer Bypassed", .code = 0x9, .cntmsk = 0xf, .modmsk = HSWEP_UNC_QPI_ATTRS, }, { .name = "UNC_Q_RXL_CREDITS_CONSUMED_VN0", .desc = "VN0 Credit Consumed", .code = 0x1e | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_q_rxl_credits_consumed_vn0), .umasks = hswep_unc_q_rxl_credits_consumed_vn0 }, { .name = "UNC_Q_RXL_CREDITS_CONSUMED_VN1", .desc = "VN1 Credit Consumed", .code = 0x39 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_q_rxl_credits_consumed_vn1), .umasks = hswep_unc_q_rxl_credits_consumed_vn1 }, { .name = "UNC_Q_RXL_CREDITS_CONSUMED_VNA", .desc = "VNA Credit Consumed", .code = 0x1d | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = HSWEP_UNC_QPI_ATTRS, }, { .name = "UNC_Q_RXL_CYCLES_NE", .desc = "RxQ Cycles Not Empty", .code = 0xa, .cntmsk = 0xf, .modmsk = HSWEP_UNC_QPI_ATTRS, }, { .name = "UNC_Q_RXL_FLITS_G1", .desc = "Flits Received - Group 1", .code = 0x2 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_q_rxl_flits_g1), .umasks = hswep_unc_q_rxl_flits_g1 }, { .name = "UNC_Q_RXL_FLITS_G2", .desc = "Flits Received - Group 2", .code = 0x3 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_q_rxl_flits_g2), .umasks = hswep_unc_q_rxl_flits_g2 }, { .name = "UNC_Q_RXL_INSERTS", .desc = "Rx Flit Buffer Allocations", .code = 0x8, .cntmsk = 0xf, .modmsk = HSWEP_UNC_QPI_ATTRS, }, { .name = "UNC_Q_RXL_INSERTS_DRS", .desc = "Rx Flit Buffer Allocations - DRS", .code = 0x9 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = HSWEP_UNC_QPI_ATTRS, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_q_txr_ad_hom_credit_acquired), .umasks = hswep_unc_q_txr_ad_hom_credit_acquired, }, { .name = "UNC_Q_RXL_INSERTS_HOM", .desc = "Rx Flit Buffer Allocations - HOM", .code = 0xc | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = HSWEP_UNC_QPI_ATTRS, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_q_txr_ad_hom_credit_acquired), .umasks = hswep_unc_q_txr_ad_hom_credit_acquired, }, { .name = "UNC_Q_RXL_INSERTS_NCB", .desc = "Rx Flit Buffer Allocations - NCB", .code = 0xa | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = HSWEP_UNC_QPI_ATTRS, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_q_txr_ad_hom_credit_acquired), .umasks = hswep_unc_q_txr_ad_hom_credit_acquired, }, { .name = "UNC_Q_RXL_INSERTS_NCS", .desc = "Rx Flit Buffer Allocations - NCS", .code = 0xb | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = HSWEP_UNC_QPI_ATTRS, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_q_txr_ad_hom_credit_acquired), .umasks = hswep_unc_q_txr_ad_hom_credit_acquired, }, { .name = "UNC_Q_RXL_INSERTS_NDR", .desc = "Rx Flit Buffer Allocations - NDR", .code = 0xe | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = HSWEP_UNC_QPI_ATTRS, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_q_txr_ad_hom_credit_acquired), .umasks = hswep_unc_q_txr_ad_hom_credit_acquired, }, { .name = "UNC_Q_RXL_INSERTS_SNP", .desc = "Rx Flit Buffer Allocations - SNP", .code = 0xd | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = HSWEP_UNC_QPI_ATTRS, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_q_txr_ad_hom_credit_acquired), .umasks = hswep_unc_q_txr_ad_hom_credit_acquired, }, { .name = "UNC_Q_RXL_OCCUPANCY", .desc = "RxQ Occupancy - All Packets", .code = 0xb, .cntmsk = 0xf, .modmsk = HSWEP_UNC_QPI_ATTRS, }, { .name = "UNC_Q_RXL_OCCUPANCY_DRS", .desc = "RxQ Occupancy - DRS", .code = 0x15 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = HSWEP_UNC_QPI_ATTRS, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_q_txr_ad_hom_credit_acquired), .umasks = hswep_unc_q_txr_ad_hom_credit_acquired, }, { .name = "UNC_Q_RXL_OCCUPANCY_HOM", .desc = "RxQ Occupancy - HOM", .code = 0x18 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = HSWEP_UNC_QPI_ATTRS, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_q_txr_ad_hom_credit_acquired), .umasks = hswep_unc_q_txr_ad_hom_credit_acquired, }, { .name = "UNC_Q_RXL_OCCUPANCY_NCB", .desc = "RxQ Occupancy - NCB", .code = 0x16 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = HSWEP_UNC_QPI_ATTRS, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_q_txr_ad_hom_credit_acquired), .umasks = hswep_unc_q_txr_ad_hom_credit_acquired, }, { .name = "UNC_Q_RXL_OCCUPANCY_NCS", .desc = "RxQ Occupancy - NCS", .code = 0x17 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = HSWEP_UNC_QPI_ATTRS, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_q_txr_ad_hom_credit_acquired), .umasks = hswep_unc_q_txr_ad_hom_credit_acquired, }, { .name = "UNC_Q_RXL_OCCUPANCY_NDR", .desc = "RxQ Occupancy - NDR", .code = 0x1a | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = HSWEP_UNC_QPI_ATTRS, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_q_txr_ad_hom_credit_acquired), .umasks = hswep_unc_q_txr_ad_hom_credit_acquired, }, { .name = "UNC_Q_RXL_OCCUPANCY_SNP", .desc = "RxQ Occupancy - SNP", .code = 0x19 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = HSWEP_UNC_QPI_ATTRS, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_q_txr_ad_hom_credit_acquired), .umasks = hswep_unc_q_txr_ad_hom_credit_acquired, }, { .name = "UNC_Q_TXL0P_POWER_CYCLES", .desc = "Cycles in L0p", .code = 0xd, .cntmsk = 0xf, .modmsk = HSWEP_UNC_QPI_ATTRS, }, { .name = "UNC_Q_TXL0_POWER_CYCLES", .desc = "Cycles in L0", .code = 0xc, .cntmsk = 0xf, .modmsk = HSWEP_UNC_QPI_ATTRS, }, { .name = "UNC_Q_TXL_BYPASSED", .desc = "Tx Flit Buffer Bypassed", .code = 0x5, .cntmsk = 0xf, .modmsk = HSWEP_UNC_QPI_ATTRS, }, { .name = "UNC_Q_TXL_CYCLES_NE", .desc = "Tx Flit Buffer Cycles not Empty", .code = 0x6, .cntmsk = 0xf, .modmsk = HSWEP_UNC_QPI_ATTRS, }, { .name = "UNC_Q_TXL_FLITS_G0", .desc = "Flits Transferred - Group 0", .code = 0x0, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_q_txl_flits_g0), .umasks = hswep_unc_q_txl_flits_g0 }, { .name = "UNC_Q_TXL_FLITS_G1", .desc = "Flits Transferred - Group 1", .code = 0x0 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_q_rxl_flits_g1), .umasks = hswep_unc_q_rxl_flits_g1 /* shared with rxl_flits_g1 */ }, { .name = "UNC_Q_TXL_FLITS_G2", .desc = "Flits Transferred - Group 2", .code = 0x1 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_q_rxl_flits_g2), .umasks = hswep_unc_q_rxl_flits_g2 /* shared with rxl_flits_g2 */ }, { .name = "UNC_Q_TXL_INSERTS", .desc = "Tx Flit Buffer Allocations", .code = 0x4, .cntmsk = 0xf, .modmsk = HSWEP_UNC_QPI_ATTRS, }, { .name = "UNC_Q_TXL_OCCUPANCY", .desc = "Tx Flit Buffer Occupancy", .code = 0x7, .cntmsk = 0xf, .modmsk = HSWEP_UNC_QPI_ATTRS, }, { .name = "UNC_Q_VNA_CREDIT_RETURNS", .desc = "VNA Credits Returned", .code = 0x1c | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = HSWEP_UNC_QPI_ATTRS, }, { .name = "UNC_Q_VNA_CREDIT_RETURN_OCCUPANCY", .desc = "VNA Credits Pending Return - Occupancy", .code = 0x1b | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .modmsk = HSWEP_UNC_QPI_ATTRS, }, { .name = "UNC_Q_TXR_AD_HOM_CREDIT_ACQUIRED", .desc = "R3QPI Egress credit occupancy AD HOM", .code = 0x26 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_q_txr_ad_hom_credit_acquired), .umasks = hswep_unc_q_txr_ad_hom_credit_acquired, }, { .name = "UNC_Q_TXR_AD_HOM_CREDIT_OCCUPANCY", .desc = "R3QPI Egress credit occupancy AD HOM", .code = 0x22 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_q_txr_ad_hom_credit_acquired), /* shared */ .umasks = hswep_unc_q_txr_ad_hom_credit_acquired, }, { .name = "UNC_Q_TXR_AD_NDR_CREDIT_ACQUIRED", .desc = "R3QPI Egress credit occupancy AD NDR", .code = 0x28 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_q_txr_ad_hom_credit_acquired), .umasks = hswep_unc_q_txr_ad_hom_credit_acquired, }, { .name = "UNC_Q_TXR_AD_NDR_CREDIT_OCCUPANCY", .desc = "R3QPI Egress credit occupancy AD NDR", .code = 0x24 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_q_txr_ad_hom_credit_acquired), /* shared */ .umasks = hswep_unc_q_txr_ad_hom_credit_acquired, }, { .name = "UNC_Q_TXR_AD_SNP_CREDIT_ACQUIRED", .desc = "R3QPI Egress credit occupancy AD SNP", .code = 0x27 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_q_txr_ad_hom_credit_acquired), .umasks = hswep_unc_q_txr_ad_hom_credit_acquired, }, { .name = "UNC_Q_TXR_AD_SNP_CREDIT_OCCUPANCY", .desc = "R3QPI Egress credit occupancy AD SNP", .code = 0x23 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_q_txr_ad_hom_credit_acquired), /* shared */ .umasks = hswep_unc_q_txr_ad_hom_credit_acquired, }, { .name = "UNC_Q_TXR_AK_NDR_CREDIT_ACQUIRED", .desc = "R3QPI Egress credit occupancy AK NDR", .code = 0x29 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_q_txr_ad_hom_credit_acquired), .umasks = hswep_unc_q_txr_ad_hom_credit_acquired, }, { .name = "UNC_Q_TXR_AK_NDR_CREDIT_OCCUPANCY", .desc = "R3QPI Egress credit occupancy AD NDR", .code = 0x25 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_q_txr_ad_hom_credit_acquired), /* shared */ .umasks = hswep_unc_q_txr_ad_hom_credit_acquired, }, { .name = "UNC_Q_TXR_BL_DRS_CREDIT_ACQUIRED", .desc = "R3QPI Egress credit occupancy BL DRS", .code = 0x2a | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_q_txr_bl_drs_credit_acquired), .umasks = hswep_unc_q_txr_bl_drs_credit_acquired, }, { .name = "UNC_Q_TXR_BL_DRS_CREDIT_OCCUPANCY", .desc = "R3QPI Egress credit occupancy BL DRS", .code = 0x1f | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_q_txr_bl_drs_credit_acquired), /* shared */ .umasks = hswep_unc_q_txr_bl_drs_credit_acquired, }, { .name = "UNC_Q_TXR_BL_NCB_CREDIT_ACQUIRED", .desc = "R3QPI Egress credit occupancy BL NCB", .code = 0x2b | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_q_txr_ad_hom_credit_acquired), .umasks = hswep_unc_q_txr_ad_hom_credit_acquired, }, { .name = "UNC_Q_TXR_BL_NCB_CREDIT_OCCUPANCY", .desc = "R3QPI Egress credit occupancy BL NCB", .code = 0x20 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_q_txr_ad_hom_credit_acquired), /* shared */ .umasks = hswep_unc_q_txr_ad_hom_credit_acquired, }, { .name = "UNC_Q_TXR_BL_NCS_CREDIT_ACQUIRED", .desc = "R3QPI Egress credit occupancy BL NCS", .code = 0x2c | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_q_txr_ad_hom_credit_acquired), .umasks = hswep_unc_q_txr_ad_hom_credit_acquired, }, { .name = "UNC_Q_TXR_BL_NCS_CREDIT_OCCUPANCY", .desc = "R3QPI Egress credit occupancy BL NCS", .code = 0x21 | (1ULL << 21), /* sel_ext */ .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_q_txr_ad_hom_credit_acquired), /* shared */ .umasks = hswep_unc_q_txr_ad_hom_credit_acquired, }, }; libpfm-4.9.0/lib/events/amd64_events_k7.h0000664000175000017500000001555713223402656017756 0ustar eranianeranian/* * Copyright (c) 2011 Google, Inc * Contributed by Stephane Eranian * * Regenerated from previous version by: * * Copyright (c) 2006, 2007 Advanced Micro Devices, Inc. * Contributed by Ray Bryant * Contributed by Robert Richter * Modified for K7 by Vince Weaver * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * This file has been automatically generated. * * PMU: amd64_k7 (AMD64 K7) */ /* * Definitions taken from "AMD Athlon Processor x86 Code Optimization Guide" * Table 11 February 2002 */ static const amd64_umask_t amd64_k7_data_cache_refills[]={ { .uname = "L2_INVALID", .udesc = "Invalid line from L2", .ucode = 0x1, }, { .uname = "L2_SHARED", .udesc = "Shared-state line from L2", .ucode = 0x2, }, { .uname = "L2_EXCLUSIVE", .udesc = "Exclusive-state line from L2", .ucode = 0x4, }, { .uname = "L2_OWNED", .udesc = "Owned-state line from L2", .ucode = 0x8, }, { .uname = "L2_MODIFIED", .udesc = "Modified-state line from L2", .ucode = 0x10, }, { .uname = "ALL", .udesc = "Shared, Exclusive, Owned, Modified State Refills", .ucode = 0x1f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_umask_t amd64_k7_data_cache_refills_from_system[]={ { .uname = "INVALID", .udesc = "Invalid", .ucode = 0x1, }, { .uname = "SHARED", .udesc = "Shared", .ucode = 0x2, }, { .uname = "EXCLUSIVE", .udesc = "Exclusive", .ucode = 0x4, }, { .uname = "OWNED", .udesc = "Owned", .ucode = 0x8, }, { .uname = "MODIFIED", .udesc = "Modified", .ucode = 0x10, }, { .uname = "ALL", .udesc = "Invalid, Shared, Exclusive, Owned, Modified", .ucode = 0x1f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_entry_t amd64_k7_pe[]={ { .name = "DATA_CACHE_ACCESSES", .desc = "Data Cache Accesses", .modmsk = AMD64_BASIC_ATTRS, .code = 0x40, }, { .name = "DATA_CACHE_MISSES", .desc = "Data Cache Misses", .modmsk = AMD64_BASIC_ATTRS, .code = 0x41, }, { .name = "DATA_CACHE_REFILLS", .desc = "Data Cache Refills from L2", .modmsk = AMD64_BASIC_ATTRS, .code = 0x42, .numasks = LIBPFM_ARRAY_SIZE(amd64_k7_data_cache_refills), .ngrp = 1, .umasks = amd64_k7_data_cache_refills, }, { .name = "DATA_CACHE_REFILLS_FROM_SYSTEM", .desc = "Data Cache Refills from System", .modmsk = AMD64_BASIC_ATTRS, .code = 0x43, .numasks = LIBPFM_ARRAY_SIZE(amd64_k7_data_cache_refills_from_system), .ngrp = 1, .umasks = amd64_k7_data_cache_refills_from_system, }, { .name = "DATA_CACHE_LINES_EVICTED", .desc = "Data Cache Lines Evicted", .modmsk = AMD64_BASIC_ATTRS, .code = 0x44, .numasks = LIBPFM_ARRAY_SIZE(amd64_k7_data_cache_refills_from_system), .ngrp = 1, .umasks = amd64_k7_data_cache_refills_from_system, /* identical to actual umasks list for this event */ }, { .name = "L1_DTLB_MISS_AND_L2_DTLB_HIT", .desc = "L1 DTLB Miss and L2 DTLB Hit", .modmsk = AMD64_BASIC_ATTRS, .code = 0x45, }, { .name = "L1_DTLB_AND_L2_DTLB_MISS", .desc = "L1 DTLB and L2 DTLB Miss", .modmsk = AMD64_BASIC_ATTRS, .code = 0x46, }, { .name = "MISALIGNED_ACCESSES", .desc = "Misaligned Accesses", .modmsk = AMD64_BASIC_ATTRS, .code = 0x47, }, { .name = "CPU_CLK_UNHALTED", .desc = "CPU Clocks not Halted", .modmsk = AMD64_BASIC_ATTRS, .code = 0x76, }, { .name = "INSTRUCTION_CACHE_FETCHES", .desc = "Instruction Cache Fetches", .modmsk = AMD64_BASIC_ATTRS, .code = 0x80, }, { .name = "INSTRUCTION_CACHE_MISSES", .desc = "Instruction Cache Misses", .modmsk = AMD64_BASIC_ATTRS, .code = 0x81, }, { .name = "L1_ITLB_MISS_AND_L2_ITLB_HIT", .desc = "L1 ITLB Miss and L2 ITLB Hit", .modmsk = AMD64_BASIC_ATTRS, .code = 0x84, }, { .name = "L1_ITLB_MISS_AND_L2_ITLB_MISS", .desc = "L1 ITLB Miss and L2 ITLB Miss", .modmsk = AMD64_BASIC_ATTRS, .code = 0x85, }, { .name = "RETIRED_INSTRUCTIONS", .desc = "Retired Instructions (includes exceptions, interrupts, resyncs)", .modmsk = AMD64_BASIC_ATTRS, .code = 0xc0, }, { .name = "RETIRED_UOPS", .desc = "Retired uops", .modmsk = AMD64_BASIC_ATTRS, .code = 0xc1, }, { .name = "RETIRED_BRANCH_INSTRUCTIONS", .desc = "Retired Branch Instructions", .modmsk = AMD64_BASIC_ATTRS, .code = 0xc2, }, { .name = "RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS", .desc = "Retired Mispredicted Branch Instructions", .modmsk = AMD64_BASIC_ATTRS, .code = 0xc3, }, { .name = "RETIRED_TAKEN_BRANCH_INSTRUCTIONS", .desc = "Retired Taken Branch Instructions", .modmsk = AMD64_BASIC_ATTRS, .code = 0xc4, }, { .name = "RETIRED_TAKEN_BRANCH_INSTRUCTIONS_MISPREDICTED", .desc = "Retired Taken Branch Instructions Mispredicted", .modmsk = AMD64_BASIC_ATTRS, .code = 0xc5, }, { .name = "RETIRED_FAR_CONTROL_TRANSFERS", .desc = "Retired Far Control Transfers", .modmsk = AMD64_BASIC_ATTRS, .code = 0xc6, }, { .name = "RETIRED_BRANCH_RESYNCS", .desc = "Retired Branch Resyncs (only non-control transfer branches)", .modmsk = AMD64_BASIC_ATTRS, .code = 0xc7, }, { .name = "INTERRUPTS_MASKED_CYCLES", .desc = "Interrupts-Masked Cycles", .modmsk = AMD64_BASIC_ATTRS, .code = 0xcd, }, { .name = "INTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDING", .desc = "Interrupts-Masked Cycles with Interrupt Pending", .modmsk = AMD64_BASIC_ATTRS, .code = 0xce, }, { .name = "INTERRUPTS_TAKEN", .desc = "Interrupts Taken", .modmsk = AMD64_BASIC_ATTRS, .code = 0xcf, }, }; libpfm-4.9.0/lib/events/intel_ivbep_unc_imc_events.h0000664000175000017500000004372313223402656022433 0ustar eranianeranian/* * Copyright (c) 2014 Google Inc. All rights reserved * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * PMU: ivbep_unc_imc (Intel IvyBridge-EP IMC uncore PMU) */ static const intel_x86_umask_t ivbep_unc_m_cas_count[]={ { .uname = "ALL", .udesc = "Counts total number of DRAM CAS commands issued on this channel", .ucode = 0xf00, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "RD", .udesc = "Counts all DRAM reads on this channel, incl. underfills", .ucode = 0x300, .uflags = INTEL_X86_NCOMBO, }, { .uname = "RD_REG", .udesc = "Counts number of DRAM read CAS commands issued on this channel, incl. regular read CAS and those with implicit precharge", .ucode = 0x100, }, { .uname = "RD_UNDERFILL", .udesc = "Counts number of underfill reads issued by the memory controller", .ucode = 0x200, }, { .uname = "WR", .udesc = "Counts number of DRAM write CAS commands on this channel", .ucode = 0xc00, .uflags = INTEL_X86_NCOMBO, }, { .uname = "WR_RMM", .udesc = "Counts Number of opportunistic DRAM write CAS commands issued on this channel", .ucode = 0x800, }, { .uname = "WR_WMM", .udesc = "Counts number of DRAM write CAS commands issued on this channel while in Write-Major mode", .ucode = 0x400, }, { .uname = "RD_RMM", .udesc = "Counts Number of opportunistic DRAM read CAS commands issued on this channel", .ucode = 0x1000, }, { .uname = "RD_WMM", .udesc = "Counts number of DRAM read CAS commands issued on this channel while in Write-Major mode", .ucode = 0x2000, }, }; static const intel_x86_umask_t ivbep_unc_m_dram_refresh[]={ { .uname = "HIGH", .udesc = "TBD", .ucode = 0x400, }, { .uname = "PANIC", .udesc = "TBD", .ucode = 0x200, }, }; static const intel_x86_umask_t ivbep_unc_m_major_modes[]={ { .uname = "ISOCH", .udesc = "Counts cycles in ISOCH Major mode", .ucode = 0x800, }, { .uname = "PARTIAL", .udesc = "Counts cycles in Partial Major mode", .ucode = 0x400, }, { .uname = "READ", .udesc = "Counts cycles in Read Major mode", .ucode = 0x100, }, { .uname = "WRITE", .udesc = "Counts cycles in Write Major mode", .ucode = 0x200, }, }; static const intel_x86_umask_t ivbep_unc_m_power_cke_cycles[]={ { .uname = "RANK0", .udesc = "Count cycles for rank 0", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "RANK1", .udesc = "Count cycles for rank 1", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "RANK2", .udesc = "Count cycles for rank 2", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "RANK3", .udesc = "Count cycles for rank 3", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "RANK4", .udesc = "Count cycles for rank 4", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "RANK5", .udesc = "Count cycles for rank 5", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "RANK6", .udesc = "Count cycles for rank 6", .ucode = 0x4000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "RANK7", .udesc = "Count cycles for rank 7", .ucode = 0x8000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t ivbep_unc_m_preemption[]={ { .uname = "RD_PREEMPT_RD", .udesc = "Counts read over read preemptions", .ucode = 0x100, }, { .uname = "RD_PREEMPT_WR", .udesc = "Counts read over write preemptions", .ucode = 0x200, }, }; static const intel_x86_umask_t ivbep_unc_m_pre_count[]={ { .uname = "PAGE_CLOSE", .udesc = "Counts number of DRAM precharge commands sent on this channel as a result of the page close counter expiring", .ucode = 0x200, }, { .uname = "PAGE_MISS", .udesc = "Counts number of DRAM precharge commands sent on this channel as a result of page misses", .ucode = 0x100, }, { .uname = "RD", .udesc = "Precharge due to read", .ucode = 0x400, }, { .uname = "WR", .udesc = "Precharge due to write", .ucode = 0x800, }, { .uname = "BYP", .udesc = "Precharge due to bypass", .ucode = 0x1000, }, }; static const intel_x86_umask_t ivbep_unc_m_act_count[]={ { .uname = "RD", .udesc = "Activate due to read", .ucode = 0x100, }, { .uname = "WR", .udesc = "Activate due to write", .ucode = 0x200, }, { .uname = "BYP", .udesc = "Activate due to bypass", .ucode = 0x800, }, }; static const intel_x86_umask_t ivbep_unc_m_byp_cmds[]={ { .uname = "ACT", .udesc = "ACT command issued by 2 cycle bypass", .ucode = 0x100, }, { .uname = "CAS", .udesc = "CAS command issued by 2 cycle bypass", .ucode = 0x200, }, { .uname = "PRE", .udesc = "PRE command issued by 2 cycle bypass", .ucode = 0x400, }, }; static const intel_x86_umask_t ivbep_unc_m_rd_cas_prio[]={ { .uname = "LOW", .udesc = "Read CAS issued with low priority", .ucode = 0x100, }, { .uname = "MED", .udesc = "Read CAS issued with medium priority", .ucode = 0x200, }, { .uname = "HIGH", .udesc = "Read CAS issued with high priority", .ucode = 0x400, }, { .uname = "PANIC", .udesc = "Read CAS issued with panic non isoch priority (starved)", .ucode = 0x800, }, }; static const intel_x86_umask_t ivbep_unc_m_rd_cas_rank0[]={ { .uname = "BANK0", .udesc = "Bank 0", .ucode = 0x100, }, { .uname = "BANK1", .udesc = "Bank 1", .ucode = 0x200, }, { .uname = "BANK2", .udesc = "Bank 2", .ucode = 0x400, }, { .uname = "BANK3", .udesc = "Bank 3", .ucode = 0x800, }, { .uname = "BANK4", .udesc = "Bank 4", .ucode = 0x1000, }, { .uname = "BANK5", .udesc = "Bank 5", .ucode = 0x2000, }, { .uname = "BANK6", .udesc = "Bank 6", .ucode = 0x4000, }, { .uname = "BANK7", .udesc = "Bank 7", .ucode = 0x8000, } }; static const intel_x86_umask_t ivbep_unc_m_vmse_wr_push[]={ { .uname = "WMM", .udesc = "VMSE write push issued in WMM", .ucode = 0x100, }, { .uname = "RMM", .udesc = "VMSE write push issued in RMM", .ucode = 0x200, } }; static const intel_x86_umask_t ivbep_unc_m_wmm_to_rmm[]={ { .uname = "LOW_THRES", .udesc = "Transition from WMM to RMM because of starve counter", .ucode = 0x100, }, { .uname = "STARVE", .udesc = "TBD", .ucode = 0x200, }, { .uname = "VMSE_RETRY", .udesc = "TBD", .ucode = 0x400, } }; static const intel_x86_entry_t intel_ivbep_unc_m_pe[]={ { .name = "UNC_M_CLOCKTICKS", .desc = "IMC Uncore clockticks (fixed counter)", .modmsk = 0x0, .cntmsk = 0x100000000ull, .code = 0xff, /* perf pseudo encoding for fixed counter */ .flags = INTEL_X86_FIXED, }, { .name = "UNC_M_DCLOCKTICKS", .desc = "IMC Uncore clockticks (generic counters)", .modmsk = IVBEP_UNC_IMC_ATTRS, .cntmsk = 0xf, .code = 0x00, /*encoding for generic counters */ }, { .name = "UNC_M_ACT_COUNT", .desc = "DRAM Activate Count", .code = 0x1, .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_IMC_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_m_act_count), .umasks = ivbep_unc_m_act_count }, { .name = "UNC_M_CAS_COUNT", .desc = "DRAM RD_CAS and WR_CAS Commands.", .code = 0x4, .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_IMC_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_m_cas_count), .umasks = ivbep_unc_m_cas_count }, { .name = "UNC_M_DRAM_PRE_ALL", .desc = "DRAM Precharge All Commands", .code = 0x6, .cntmsk = 0xf, .modmsk = IVBEP_UNC_IMC_ATTRS, }, { .name = "UNC_M_DRAM_REFRESH", .desc = "Number of DRAM Refreshes Issued", .code = 0x5, .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_IMC_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_m_dram_refresh), .umasks = ivbep_unc_m_dram_refresh }, { .name = "UNC_M_ECC_CORRECTABLE_ERRORS", .desc = "ECC Correctable Errors", .code = 0x9, .cntmsk = 0xf, .modmsk = IVBEP_UNC_IMC_ATTRS, }, { .name = "UNC_M_MAJOR_MODES", .desc = "Cycles in a Major Mode", .code = 0x7, .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_IMC_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_m_major_modes), .umasks = ivbep_unc_m_major_modes }, { .name = "UNC_M_POWER_CHANNEL_DLLOFF", .desc = "Channel DLLOFF Cycles", .code = 0x84, .cntmsk = 0xf, .modmsk = IVBEP_UNC_IMC_ATTRS, }, { .name = "UNC_M_POWER_CHANNEL_PPD", .desc = "Channel PPD Cycles", .code = 0x85, .cntmsk = 0xf, .modmsk = IVBEP_UNC_IMC_ATTRS, }, { .name = "UNC_M_POWER_CKE_CYCLES", .desc = "CKE_ON_CYCLES by Rank", .code = 0x83, .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_IMC_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_m_power_cke_cycles), .umasks = ivbep_unc_m_power_cke_cycles }, { .name = "UNC_M_POWER_CRITICAL_THROTTLE_CYCLES", .desc = "Critical Throttle Cycles", .code = 0x86, .cntmsk = 0xf, .modmsk = IVBEP_UNC_IMC_ATTRS, }, { .name = "UNC_M_POWER_SELF_REFRESH", .desc = "Clock-Enabled Self-Refresh", .code = 0x43, .cntmsk = 0xf, .modmsk = IVBEP_UNC_IMC_ATTRS, }, { .name = "UNC_M_POWER_THROTTLE_CYCLES", .desc = "Throttle Cycles", .code = 0x41, .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_IMC_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_m_power_cke_cycles), .umasks = ivbep_unc_m_power_cke_cycles /* identical to snbep_unc_m_power_cke_cycles */ }, { .name = "UNC_M_PREEMPTION", .desc = "Read Preemption Count", .code = 0x8, .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_IMC_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_m_preemption), .umasks = ivbep_unc_m_preemption }, { .name = "UNC_M_PRE_COUNT", .desc = "DRAM Precharge commands.", .code = 0x2, .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_IMC_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_m_pre_count), .umasks = ivbep_unc_m_pre_count }, { .name = "UNC_M_RPQ_CYCLES_NE", .desc = "Read Pending Queue Not Empty", .code = 0x11, .cntmsk = 0xf, .modmsk = IVBEP_UNC_IMC_ATTRS, }, { .name = "UNC_M_RPQ_INSERTS", .desc = "Read Pending Queue Allocations", .code = 0x10, .cntmsk = 0xf, .modmsk = IVBEP_UNC_IMC_ATTRS, }, { .name = "UNC_M_WPQ_CYCLES_FULL", .desc = "Write Pending Queue Full Cycles", .code = 0x22, .cntmsk = 0xf, .modmsk = IVBEP_UNC_IMC_ATTRS, }, { .name = "UNC_M_WPQ_CYCLES_NE", .desc = "Write Pending Queue Not Empty", .code = 0x21, .cntmsk = 0xf, .modmsk = IVBEP_UNC_IMC_ATTRS, }, { .name = "UNC_M_WPQ_INSERTS", .desc = "Write Pending Queue Allocations", .code = 0x20, .cntmsk = 0xf, .modmsk = IVBEP_UNC_IMC_ATTRS, }, { .name = "UNC_M_WPQ_READ_HIT", .desc = "Write Pending Queue CAM Match", .code = 0x23, .cntmsk = 0xf, .modmsk = IVBEP_UNC_IMC_ATTRS, }, { .name = "UNC_M_WPQ_WRITE_HIT", .desc = "Write Pending Queue CAM Match", .code = 0x24, .cntmsk = 0xf, .modmsk = IVBEP_UNC_IMC_ATTRS, }, { .name = "UNC_M_BYP_CMDS", .desc = "Bypass command event", .code = 0xa1, .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_IMC_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_m_byp_cmds), .umasks = ivbep_unc_m_byp_cmds }, { .name = "UNC_M_RD_CAS_PRIO", .desc = "Read CAS priority", .code = 0xa0, .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_IMC_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_m_rd_cas_prio), .umasks = ivbep_unc_m_rd_cas_prio }, { .name = "UNC_M_RD_CAS_RANK0", .desc = "Read CAS access to Rank 0", .code = 0xb0, .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_IMC_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_m_rd_cas_rank0), .umasks = ivbep_unc_m_rd_cas_rank0 }, { .name = "UNC_M_RD_CAS_RANK1", .desc = "Read CAS access to Rank 1", .code = 0xb1, .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_IMC_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_m_rd_cas_rank0), /* shared */ .umasks = ivbep_unc_m_rd_cas_rank0 }, { .name = "UNC_M_RD_CAS_RANK2", .desc = "Read CAS access to Rank 2", .code = 0xb2, .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_IMC_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_m_rd_cas_rank0), /* shared */ .umasks = ivbep_unc_m_rd_cas_rank0 }, { .name = "UNC_M_RD_CAS_RANK3", .desc = "Read CAS access to Rank 3", .code = 0xb3, .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_IMC_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_m_rd_cas_rank0), /* shared */ .umasks = ivbep_unc_m_rd_cas_rank0 }, { .name = "UNC_M_RD_CAS_RANK4", .desc = "Read CAS access to Rank 4", .code = 0xb4, .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_IMC_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_m_rd_cas_rank0), /* shared */ .umasks = ivbep_unc_m_rd_cas_rank0 }, { .name = "UNC_M_RD_CAS_RANK5", .desc = "Read CAS access to Rank 5", .code = 0xb5, .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_IMC_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_m_rd_cas_rank0), /* shared */ .umasks = ivbep_unc_m_rd_cas_rank0 }, { .name = "UNC_M_RD_CAS_RANK6", .desc = "Read CAS access to Rank 6", .code = 0xb6, .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_IMC_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_m_rd_cas_rank0), /* shared */ .umasks = ivbep_unc_m_rd_cas_rank0 }, { .name = "UNC_M_RD_CAS_RANK7", .desc = "Read CAS access to Rank 7", .code = 0xb7, .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_IMC_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_m_rd_cas_rank0), /* shared */ .umasks = ivbep_unc_m_rd_cas_rank0 }, { .name = "UNC_M_VMSE_MXB_WR_OCCUPANCY", .desc = "VMSE MXB write buffer occupancy", .code = 0x91, .cntmsk = 0xf, .modmsk = IVBEP_UNC_IMC_ATTRS, }, { .name = "UNC_M_VMSE_WR_PUSH", .desc = "VMSE WR push issued", .code = 0x90, .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_IMC_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_m_vmse_wr_push), .umasks = ivbep_unc_m_vmse_wr_push }, { .name = "UNC_M_WMM_TO_RMM", .desc = "Transitions from WMM to RMM because of low threshold", .code = 0xc0, .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_IMC_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_m_wmm_to_rmm), .umasks = ivbep_unc_m_wmm_to_rmm }, { .name = "UNC_M_WRONG_MM", .desc = "Not getting the requested major mode", .code = 0xc1, .cntmsk = 0xf, .modmsk = IVBEP_UNC_IMC_ATTRS, }, { .name = "UNC_M_WR_CAS_RANK0", .desc = "Write CAS access to Rank 0", .code = 0xb8, .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_IMC_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_m_rd_cas_rank0), /* shared */ .umasks = ivbep_unc_m_rd_cas_rank0 }, { .name = "UNC_M_WR_CAS_RANK1", .desc = "Write CAS access to Rank 1", .code = 0xb9, .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_IMC_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_m_rd_cas_rank0), /* shared */ .umasks = ivbep_unc_m_rd_cas_rank0 }, { .name = "UNC_M_WR_CAS_RANK2", .desc = "Write CAS access to Rank 2", .code = 0xba, .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_IMC_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_m_rd_cas_rank0), /* shared */ .umasks = ivbep_unc_m_rd_cas_rank0 }, { .name = "UNC_M_WR_CAS_RANK3", .desc = "Write CAS access to Rank 3", .code = 0xbb, .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_IMC_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_m_rd_cas_rank0), /* shared */ .umasks = ivbep_unc_m_rd_cas_rank0 }, { .name = "UNC_M_WR_CAS_RANK4", .desc = "Write CAS access to Rank 4", .code = 0xbc, .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_IMC_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_m_rd_cas_rank0), /* shared */ .umasks = ivbep_unc_m_rd_cas_rank0 }, { .name = "UNC_M_WR_CAS_RANK5", .desc = "Write CAS access to Rank 5", .code = 0xbd, .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_IMC_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_m_rd_cas_rank0), /* shared */ .umasks = ivbep_unc_m_rd_cas_rank0 }, { .name = "UNC_M_WR_CAS_RANK6", .desc = "Write CAS access to Rank 6", .code = 0xbe, .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_IMC_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_m_rd_cas_rank0), /* shared */ .umasks = ivbep_unc_m_rd_cas_rank0 }, { .name = "UNC_M_WR_CAS_RANK7", .desc = "Write CAS access to Rank 7", .code = 0xbf, .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_IMC_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_m_rd_cas_rank0), /* shared */ .umasks = ivbep_unc_m_rd_cas_rank0 }, }; libpfm-4.9.0/lib/events/sparc_ultra12_events.h0000664000175000017500000000616013223402656021112 0ustar eranianeranianstatic const sparc_entry_t ultra12_pe[] = { /* These two must always be first. */ { .name = "Cycle_cnt", .desc = "Accumulated cycles", .ctrl = PME_CTRL_S0 | PME_CTRL_S1, .code = 0x0, }, { .name = "Instr_cnt", .desc = "Number of instructions completed", .ctrl = PME_CTRL_S0 | PME_CTRL_S1, .code = 0x1, }, { .name = "Dispatch0_IC_miss", .desc = "I-buffer is empty from I-Cache miss", .ctrl = PME_CTRL_S0, .code = 0x2, }, /* PIC0 events for UltraSPARC-I/II/IIi/IIe */ { .name = "Dispatch0_storeBuf", .desc = "Store buffer can not hold additional stores", .ctrl = PME_CTRL_S0, .code = 0x3, }, { .name = "IC_ref", .desc = "I-cache references", .ctrl = PME_CTRL_S0, .code = 0x8, }, { .name = "DC_rd", .desc = "D-cache read references (including accesses that subsequently trap)", .ctrl = PME_CTRL_S0, .code = 0x9, }, { .name = "DC_wr", .desc = "D-cache write references (including accesses that subsequently trap)", .ctrl = PME_CTRL_S0, .code = 0xa, }, { .name = "Load_use", .desc = "An instruction in the execute stage depends on an earlier load result that is not yet available", .ctrl = PME_CTRL_S0, .code = 0xb, }, { .name = "EC_ref", .desc = "Total E-cache references", .ctrl = PME_CTRL_S0, .code = 0xc, }, { .name = "EC_write_hit_RDO", .desc = "E-cache hits that do a read for ownership UPA transaction", .ctrl = PME_CTRL_S0, .code = 0xd, }, { .name = "EC_snoop_inv", .desc = "E-cache invalidates from the following UPA transactions: S_INV_REQ, S_CPI_REQ", .ctrl = PME_CTRL_S0, .code = 0xe, }, { .name = "EC_rd_hit", .desc = "E-cache read hits from D-cache misses", .ctrl = PME_CTRL_S0, .code = 0xf, }, /* PIC1 events for UltraSPARC-I/II/IIi/IIe */ { .name = "Dispatch0_mispred", .desc = "I-buffer is empty from Branch misprediction", .ctrl = PME_CTRL_S1, .code = 0x2, }, { .name = "Dispatch0_FP_use", .desc = "First instruction in the group depends on an earlier floating point result that is not yet available", .ctrl = PME_CTRL_S1, .code = 0x3, }, { .name = "IC_hit", .desc = "I-cache hits", .ctrl = PME_CTRL_S1, .code = 0x8, }, { .name = "DC_rd_hit", .desc = "D-cache read hits", .ctrl = PME_CTRL_S1, .code = 0x9, }, { .name = "DC_wr_hit", .desc = "D-cache write hits", .ctrl = PME_CTRL_S1, .code = 0xa, }, { .name = "Load_use_RAW", .desc = "There is a load use in the execute stage and there is a read-after-write hazard on the oldest outstanding load", .ctrl = PME_CTRL_S1, .code = 0xb, }, { .name = "EC_hit", .desc = "Total E-cache hits", .ctrl = PME_CTRL_S1, .code = 0xc, }, { .name = "EC_wb", .desc = "E-cache misses that do writebacks", .ctrl = PME_CTRL_S1, .code = 0xd, }, { .name = "EC_snoop_cb", .desc = "E-cache snoop copy-backs from the following UPA transactions: S_CPB_REQ, S_CPI_REQ, S_CPD_REQ, S_CPB_MIS_REQ", .ctrl = PME_CTRL_S1, .code = 0xe, }, { .name = "EC_ic_hit", .desc = "E-cache read hits from I-cache misses", .ctrl = PME_CTRL_S1, .code = 0xf, }, }; #define PME_SPARC_ULTRA12_EVENT_COUNT (sizeof(ultra12_pe)/sizeof(sparc_entry_t)) libpfm-4.9.0/lib/events/intel_hswep_unc_ha_events.h0000664000175000017500000010207413223402656022267 0ustar eranianeranian/* * Copyright (c) 2014 Google Inc. All rights reserved * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * PMU: hswep_unc_ha (Intel Haswell-EP HA uncore PMU) */ static const intel_x86_umask_t hswep_unc_h_directory_lookup[]={ { .uname = "NO_SNP", .udesc = "Snoop not needed", .ucode = 0x200, }, { .uname = "SNOOP", .udesc = "SNooop needed", .ucode = 0x100, }, }; static const intel_x86_umask_t hswep_unc_h_bypass_imc[]={ { .uname = "TAKEN", .udesc = "Bypass taken", .ucode = 0x100, }, { .uname = "NOT_TAKEN", .udesc = "Bypass not taken", .ucode = 0x200, }, }; static const intel_x86_umask_t hswep_unc_h_directory_update[]={ { .uname = "ANY", .udesc = "Counts any directory update", .ucode = 0x300, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "CLEAR", .udesc = "Directory clears", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "SET", .udesc = "Directory set", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t hswep_unc_h_hitme_hit[]={ { .uname = "ALL", .udesc = "All requests", .ucode = 0xff00, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "READ_OR_INVITOE", .udesc = "Number of hits with opcode RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvToE", .ucode = 0x100, }, { .uname = "WBMTOI", .udesc = "Number of hits with opcode WbToMtoI", .ucode = 0x200, }, { .uname = "ACKCNFLTWBI", .udesc = "Number of hits with opcode AckCnfltWbI", .ucode = 0x400, }, { .uname = "WBMTOE_OR_S", .udesc = "Number of hits with opcode WbMtoE or WbMtoS", .ucode = 0x800, }, { .uname = "HOM", .udesc = "Number of hits with HOM requests", .ucode = 0xf00, .uflags = INTEL_X86_NCOMBO, }, { .uname = "RSPFWDI_REMOTE", .udesc = "Number of hits with opcode RspIFwd, RspIFwdWb for remore requests", .ucode = 0x1000, }, { .uname = "RSPFWDI_LOCAL", .udesc = "Number of hits with opcode RspIFwd, RspIFwdWb for local requests", .ucode = 0x2000, }, { .uname = "INVALS", .udesc = "Number of hits for invalidations", .ucode = 0x2600, .uflags = INTEL_X86_NCOMBO, }, { .uname = "RSPFWDS", .udesc = "Number of hits with opcode RsSFwd, RspSFwdWb", .ucode = 0x4000, }, { .uname = "EVICTS", .udesc = "Number of hits for allocations", .ucode = 0x4200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ALLOCS", .udesc = "Number of hits for allocations", .ucode = 0x7000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "RSP", .udesc = "Number of hits with opcode RspI, RspIWb, RspSWb, RspCnflt, RspCnfltWbI", .ucode = 0x8000, } }; static const intel_x86_umask_t hswep_unc_h_hitme_hit_pv_bits_set[]={ { .uname = "ALL", .udesc = "All requests", .ucode = 0xff00, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "READ_OR_INVITOE", .udesc = "Number of hits with opcode RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvToE", .ucode = 0x100, }, { .uname = "WBMTOI", .udesc = "Number of hits with opcode WbToMtoI", .ucode = 0x200, }, { .uname = "ACKCNFLTWBI", .udesc = "Number of hits with opcode AckCnfltWbI", .ucode = 0x400, }, { .uname = "WBMTOE_OR_S", .udesc = "Number of hits with opcode WbMtoE or WbMtoS", .ucode = 0x800, }, { .uname = "HOM", .udesc = "Number of hits with HOM requests", .ucode = 0xf00, .uflags = INTEL_X86_NCOMBO, }, { .uname = "RSPFWDI_REMOTE", .udesc = "Number of hits with opcode RspIFwd, RspIFwdWb for remore requests", .ucode = 0x1000, }, { .uname = "RSPFWDI_LOCAL", .udesc = "Number of hits with opcode RspIFwd, RspIFwdWb for local requests", .ucode = 0x2000, }, { .uname = "RSPFWDS", .udesc = "Number of hits with opcode RsSFwd, RspSFwdWb", .ucode = 0x4000, }, { .uname = "RSP", .udesc = "Number of hits with opcode RspI, RspIWb, RspSWb, RspCnflt, RspCnfltWbI", .ucode = 0x8000, } }; static const intel_x86_umask_t hswep_unc_h_igr_no_credit_cycles[]={ { .uname = "AD_QPI0", .udesc = "AD to QPI link 0", .ucode = 0x100, }, { .uname = "AD_QPI1", .udesc = "AD to QPI link 1", .ucode = 0x200, }, { .uname = "BL_QPI0", .udesc = "BL to QPI link 0", .ucode = 0x400, }, { .uname = "BL_QPI1", .udesc = "BL to QPI link 1", .ucode = 0x800, }, { .uname = "AD_QPI2", .udesc = "AD to QPI link 2", .ucode = 0x1000, }, { .uname = "BL_QPI2", .udesc = "BL to QPI link 2", .ucode = 0x2000, }, }; static const intel_x86_umask_t hswep_unc_h_imc_writes[]={ { .uname = "ALL", .udesc = "Counts all writes", .ucode = 0xf00, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "FULL", .udesc = "Counts full line non ISOCH", .ucode = 0x100, }, { .uname = "PARTIAL", .udesc = "Counts partial non-ISOCH", .ucode = 0x200, }, { .uname = "FULL_ISOCH", .udesc = "Counts ISOCH full line", .ucode = 0x400, }, { .uname = "PARTIAL_ISOCH", .udesc = "Counts ISOCH partial", .ucode = 0x800, }, }; static const intel_x86_umask_t hswep_unc_h_imc_reads[]={ { .uname = "NORMAL", .udesc = "Normal priority", .ucode = 0x100, .uflags = INTEL_X86_DFL, }, }; static const intel_x86_umask_t hswep_unc_h_requests[]={ { .uname = "READS", .udesc = "Counts incoming read requests. Good proxy for LLC read misses, incl. RFOs", .ucode = 0x300, .uflags = INTEL_X86_NCOMBO, }, { .uname = "READS_LOCAL", .udesc = "Counts incoming read requests coming from local socket. Good proxy for LLC read misses, incl. RFOs from the local socket", .ucode = 0x100, }, { .uname = "READS_REMOTE", .udesc = "Counts incoming read requests coming from remote socket. Good proxy for LLC read misses, incl. RFOs from the remote socket", .ucode = 0x200, }, { .uname = "WRITES", .udesc = "Counts incoming writes", .ucode = 0xc00, .uflags = INTEL_X86_NCOMBO, }, { .uname = "WRITES_LOCAL", .udesc = "Counts incoming writes from local socket", .ucode = 0x400, }, { .uname = "WRITES_REMOTE", .udesc = "Counts incoming writes from remote socket", .ucode = 0x800, }, { .uname = "INVITOE_LOCAL", .udesc = "Counts InvItoE coming from local socket", .ucode = 0x1000, }, { .uname = "INVITOE_REMOTE", .udesc = "Counts InvItoE coming from remote socket", .ucode = 0x2000, } }; static const intel_x86_umask_t hswep_unc_h_rpq_cycles_no_reg_credits[]={ { .uname = "CHN0", .udesc = "Channel 0", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "CHN1", .udesc = "Channel 1", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "CHN2", .udesc = "channel 2", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "CHN3", .udesc = "Chanel 3", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t hswep_unc_h_tad_requests_g0[]={ { .uname = "REGION0", .udesc = "Counts for TAD Region 0", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "REGION1", .udesc = "Counts for TAD Region 1", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "REGION2", .udesc = "Counts for TAD Region 2", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "REGION3", .udesc = "Counts for TAD Region 3", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "REGION4", .udesc = "Counts for TAD Region 4", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "REGION5", .udesc = "Counts for TAD Region 5", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "REGION6", .udesc = "Counts for TAD Region 6", .ucode = 0x4000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "REGION7", .udesc = "Counts for TAD Region 7", .ucode = 0x8000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t hswep_unc_h_tad_requests_g1[]={ { .uname = "REGION8", .udesc = "Counts for TAD Region 8", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "REGION9", .udesc = "Counts for TAD Region 9", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "REGION10", .udesc = "Counts for TAD Region 10", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "REGION11", .udesc = "Counts for TAD Region 11", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t hswep_unc_h_snoop_resp[]={ { .uname = "RSPI", .udesc = "Filters for snoop responses of RspI. RspI is returned when the remote cache does not have the data or when the remote cache silently evicts data (e.g. RFO hit non-modified line)", .ucode = 0x100, }, { .uname = "RSPS", .udesc = "Filters for snoop responses of RspS. RspS is returned when the remote cache has the data but is not forwarding it. It is a way to let the requesting socket know that it cannot allocate the data in E-state", .ucode = 0x200, }, { .uname = "RSPIFWD", .udesc = "Filters for snoop responses of RspIFwd. RspIFwd is returned when the remote cache agent forwards data and the requesting agent is able to acquire the data in E or M state. This is commonly returned with RFO transacations. It can be either HitM or HitFE", .ucode = 0x400, }, { .uname = "RSPSFWD", .udesc = "Filters for snoop responses of RspSFwd. RspSFwd is returned when the remote cache agent forwards data but holds on to its current copy. This is common for data and code reads that hit in a remote socket in E or F state", .ucode = 0x800, }, { .uname = "RSP_WB", .udesc = "Filters for snoop responses of RspIWB or RspSWB. This is returned when a non-RFO requests hits in M-state. Data and code reads can return either RspIWB or RspSWB depending on how the system has been configured. InvItoE transactions will also return RspIWB because they must acquire ownership", .ucode = 0x1000, }, { .uname = "RSP_FWD_WB", .udesc = "Filters for snoop responses of RspxFwdxWB. This snoop response is only used in 4s systems. It is used when a snoop HITM in a remote caching agent and it directly forwards data to a requester and simultaneously returns data to the home to be written back to memory", .ucode = 0x2000, }, { .uname = "RSPCNFLCT", .udesc = "Filters for snoop responses of RspConflict. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CMAs that caching agent. This triggers the conflict resolution hardware. This covers both RspConflct and RspCnflctWBI", .ucode = 0x4000, }, }; static const intel_x86_umask_t hswep_unc_h_txr_ad_cycles_full[]={ { .uname = "ALL", .udesc = "Counts cycles full from both schedulers", .ucode = 0x300, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "SCHED0", .udesc = "Counts cycles full from scheduler bank 0", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "SCHED1", .udesc = "Counts cycles full from scheduler bank 1", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t hswep_unc_h_txr_bl_occupancy[]={ { .uname = "SCHED0", .udesc = "Counts cycles full from scheduler bank 0", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "SCHED1", .udesc = "Counts cycles full from scheduler bank 1", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t hswep_unc_h_txr_ak_cycles_full[]={ { .uname = "ALL", .udesc = "Counts cycles from both schedulers", .ucode = 0x300, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "SCHED0", .udesc = "Counts cycles from scheduler bank 0", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "SCHED1", .udesc = "Counts cycles from scheduler bank 1", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t hswep_unc_h_txr_bl[]={ { .uname = "DRS_CACHE", .udesc = "Counts data being sent to the cache", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "DRS_CORE", .udesc = "Counts data being sent directly to the requesting core", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "DRS_QPI", .udesc = "Counts data being sent to a remote socket over QPI", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t hswep_unc_h_osb[]={ { .uname = "REMOTE", .udesc = "Remote", .ucode = 0x800, }, { .uname = "READS_LOCAL", .udesc = "Local reads", .ucode = 0x200, }, { .uname = "INVITOE_LOCAL", .udesc = "Local InvItoE", .ucode = 0x400, }, { .uname = "CANCELLED", .udesc = "Cancelled due to D2C or Other", .ucode = 0x1000, }, { .uname = "READS_LOCAL_USEFUL", .udesc = "Local reads - useful", .ucode = 0x2000, }, { .uname = "REMOTE_USEFUL", .udesc = "Remote - useful", .ucode = 0x4000, } }; static const intel_x86_umask_t hswep_unc_h_osb_edr[]={ { .uname = "ALL", .udesc = "All data returns", .ucode = 0x100, .uflags = INTEL_X86_DFL | INTEL_X86_NCOMBO, }, { .uname = "READS_LOCAL_I", .udesc = "Reads to local I", .ucode = 0x200, }, { .uname = "READS_REMOTE_I", .udesc = "Reads to remote I", .ucode = 0x400, }, { .uname = "READS_LOCAL_S", .udesc = "Reads to local S", .ucode = 0x800, }, { .uname = "READS_REMOTE_S", .udesc = "Reads to remote S", .ucode = 0x1000, } }; static const intel_x86_umask_t hswep_unc_h_ring_ad_used[]={ { .uname = "CCW_EVEN", .udesc = "Counter-clockwise and even ring polarity", .ucode = 0x400, }, { .uname = "CCW_ODD", .udesc = "Counter-clockwise and odd ring polarity", .ucode = 0x800, }, { .uname = "CW_EVEN", .udesc = "Clockwise and even ring polarity", .ucode = 0x100, }, { .uname = "CW_ODD", .udesc = "Clockwise and odd ring polarity", .ucode = 0x200, }, { .uname = "CW", .udesc = "Clockwise with any polarity", .ucode = 0x3300, .uflags = INTEL_X86_NCOMBO, }, { .uname = "CCW", .udesc = "Counter-clockwise with any polarity", .ucode = 0xcc00, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t hswep_unc_h_snp_resp_recv_local[]={ { .uname = "RSPI", .udesc = "Filters for snoop responses of RspI. RspI is returned when the remote cache does not have the data or when the remote cache silently evicts data (e.g. RFO hit non-modified line)", .ucode = 0x100, }, { .uname = "RSPS", .udesc = "Filters for snoop responses of RspS. RspS is returned when the remote cache has the data but is not forwarding it. It is a way to let the requesting socket know that it cannot allocate the data in E-state", .ucode = 0x200, }, { .uname = "RSPIFWD", .udesc = "Filters for snoop responses of RspIFwd. RspIFwd is returned when the remote cache agent forwards data and the requesting agent is able to acquire the data in E or M state. This is commonly returned with RFO transacations. It can be either HitM or HitFE", .ucode = 0x400, }, { .uname = "RSPSFWD", .udesc = "Filters for snoop responses of RspSFwd. RspSFwd is returned when the remote cache agent forwards data but holds on to its current copy. This is common for data and code reads that hit in a remote socket in E or F state", .ucode = 0x800, }, { .uname = "RSP_WB", .udesc = "Filters for snoop responses of RspIWB or RspSWB. This is returned when a non-RFO requests hits in M-state. Data and code reads can return either RspIWB or RspSWB depending on how the system has been configured. InvItoE transactions will also return RspIWB because they must acquire ownership", .ucode = 0x1000, }, { .uname = "RSP_FWD_WB", .udesc = "Filters for snoop responses of RspxFwdxWB. This snoop response is only used in 4s systems. It is used when a snoop HITM in a remote caching agent and it directly forwards data to a requester and simultaneously returns data to the home to be written back to memory", .ucode = 0x2000, }, { .uname = "RSPCNFLCT", .udesc = "Filters for snoop responses of RspConflict. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CMAs that caching agent. This triggers the conflict resolution hardware. This covers both RspConflct and RspCnflctWBI", .ucode = 0x4000, }, { .uname = "OTHER", .udesc = "Filters all other snoop responses", .ucode = 0x8000, }, }; static const intel_x86_umask_t hswep_unc_h_sbo0_credits_acquired[]={ { .uname = "AD", .udesc = "For AD ring", .ucode = 0x100, }, { .uname = "BL", .udesc = "For BL ring", .ucode = 0x200, }, }; static const intel_x86_umask_t hswep_unc_h_snoops_rsp_after_data[]={ { .uname = "LOCAL", .udesc = "Local", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "REMOTE", .udesc = "Remote", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t hswep_unc_h_snoops_cycles_ne[]={ { .uname = "ALL", .udesc = "Local", .ucode = 0x300, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "LOCAL", .udesc = "Local", .ucode = 0x100, }, { .uname = "REMOTE", .udesc = "Remote", .ucode = 0x200, }, }; static const intel_x86_umask_t hswep_unc_h_txr_ak[]={ { .uname = "NDR", .udesc = "Number of outbound NDR (non-data response) transactions send on the AK ring. AK NDR is used for messages to the local socket", .ucode = 0x100, }, { .uname = "CRD_CBO", .udesc = "Number of outbound CDR transactions send on the AK ring to CBO", .ucode = 0x200, }, { .uname = "CRD_QPI", .udesc = "Number of outbound CDR transactions send on the AK ring to QPI", .ucode = 0x400, }, }; static const intel_x86_umask_t hswep_unc_h_stall_no_sbo_credit[]={ { .uname = "SBO0_AD", .udesc = "No credit for SBO0 AD Ring", .ucode = 0x100, }, { .uname = "SBO1_AD", .udesc = "No credit for SBO1 AD Ring", .ucode = 0x200, }, { .uname = "SBO0_BL", .udesc = "No credit for SBO0 BL Ring", .ucode = 0x400, }, { .uname = "SBO1_BL", .udesc = "No credit for SBO1 BL Ring", .ucode = 0x800, }, }; static const intel_x86_umask_t hswep_unc_h_tracker_occupancy[]={ { .uname = "READS_LOCAL", .udesc = "Local read requests", .ucode = 0x400, }, { .uname = "READS_REMOTE", .udesc = "Remote read requests", .ucode = 0x800, }, { .uname = "WRITES_LOCAL", .udesc = "Local write requests", .ucode = 0x1000, }, { .uname = "WRITES_REMOTE", .udesc = "Remote write requests", .ucode = 0x2000, }, { .uname = "INVITOE_LOCAL", .udesc = "Local InvItoE requests", .ucode = 0x4000, }, { .uname = "INVITOE_REMOTE", .udesc = "Remote InvItoE requests", .ucode = 0x8000, } }; static const intel_x86_umask_t hswep_unc_h_txr_starved[]={ { .uname = "AK", .udesc = "For AD ring", .ucode = 0x100, }, { .uname = "BL", .udesc = "For BL ring", .ucode = 0x200, }, }; static const intel_x86_entry_t intel_hswep_unc_h_pe[]={ { .name = "UNC_H_CLOCKTICKS", .desc = "HA Uncore clockticks", .modmsk = HSWEP_UNC_HA_ATTRS, .cntmsk = 0xf, .code = 0x00, }, { .name = "UNC_H_CONFLICT_CYCLES", .desc = "Conflict Checks", .code = 0xb, .cntmsk = 0x2, .modmsk = HSWEP_UNC_HA_ATTRS, }, { .name = "UNC_H_DIRECT2CORE_COUNT", .desc = "Direct2Core Messages Sent", .code = 0x11, .cntmsk = 0xf, .modmsk = HSWEP_UNC_HA_ATTRS, }, { .name = "UNC_H_DIRECT2CORE_CYCLES_DISABLED", .desc = "Cycles when Direct2Core was Disabled", .code = 0x12, .cntmsk = 0xf, .modmsk = HSWEP_UNC_HA_ATTRS, }, { .name = "UNC_H_DIRECT2CORE_TXN_OVERRIDE", .desc = "Number of Reads that had Direct2Core Overridden", .code = 0x13, .cntmsk = 0xf, .modmsk = HSWEP_UNC_HA_ATTRS, }, { .name = "UNC_H_DIRECTORY_LOOKUP", .desc = "Directory Lookups", .code = 0xc, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_h_directory_lookup), .umasks = hswep_unc_h_directory_lookup }, { .name = "UNC_H_DIRECTORY_UPDATE", .desc = "Directory Updates", .code = 0xd, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_h_directory_update), .umasks = hswep_unc_h_directory_update }, { .name = "UNC_H_IGR_NO_CREDIT_CYCLES", .desc = "Cycles without QPI Ingress Credits", .code = 0x22, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_h_igr_no_credit_cycles), .umasks = hswep_unc_h_igr_no_credit_cycles }, { .name = "UNC_H_IMC_RETRY", .desc = "Retry Events", .code = 0x1e, .cntmsk = 0xf, .modmsk = HSWEP_UNC_HA_ATTRS, }, { .name = "UNC_H_IMC_WRITES", .desc = "HA to IMC Full Line Writes Issued", .code = 0x1a, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_h_imc_writes), .umasks = hswep_unc_h_imc_writes }, { .name = "UNC_H_IMC_READS", .desc = "HA to IMC normal priority reads issued", .code = 0x17, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_h_imc_reads), .umasks = hswep_unc_h_imc_reads }, { .name = "UNC_H_REQUESTS", .desc = "Read and Write Requests", .code = 0x1, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_h_requests), .umasks = hswep_unc_h_requests }, { .name = "UNC_H_RPQ_CYCLES_NO_REG_CREDITS", .desc = "IMC RPQ Credits Empty", .code = 0x15, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_h_rpq_cycles_no_reg_credits), .umasks = hswep_unc_h_rpq_cycles_no_reg_credits }, { .name = "UNC_H_TAD_REQUESTS_G0", .desc = "HA Requests to a TAD Region", .code = 0x1b, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_h_tad_requests_g0), .umasks = hswep_unc_h_tad_requests_g0 }, { .name = "UNC_H_TAD_REQUESTS_G1", .desc = "HA Requests to a TAD Region", .code = 0x1c, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_h_tad_requests_g1), .umasks = hswep_unc_h_tad_requests_g1 }, { .name = "UNC_H_TXR_AD_CYCLES_FULL", .desc = "AD Egress Full", .code = 0x2a, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_h_txr_ad_cycles_full), .umasks = hswep_unc_h_txr_ad_cycles_full }, { .name = "UNC_H_TXR_AK_CYCLES_FULL", .desc = "AK Egress Full", .code = 0x32, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_h_txr_ak_cycles_full), .umasks = hswep_unc_h_txr_ak_cycles_full }, { .name = "UNC_H_TXR_AK", .desc = "Outbound Ring Transactions on AK", .code = 0xe, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_h_txr_ak), .umasks = hswep_unc_h_txr_ak }, { .name = "UNC_H_TXR_BL", .desc = "Outbound DRS Ring Transactions to Cache", .code = 0x10, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_h_txr_bl), .umasks = hswep_unc_h_txr_bl }, { .name = "UNC_H_TXR_BL_CYCLES_FULL", .desc = "BL Egress Full", .code = 0x36, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_h_txr_ak_cycles_full), .umasks = hswep_unc_h_txr_ak_cycles_full, /* identical to snbep_unc_h_txr_ak_cycles_full */ }, { .name = "UNC_H_WPQ_CYCLES_NO_REG_CREDITS", .desc = "HA IMC CHN0 WPQ Credits Empty", .code = 0x18, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_h_rpq_cycles_no_reg_credits), .umasks = hswep_unc_h_rpq_cycles_no_reg_credits, /* shared */ }, { .name = "UNC_H_BT_BYPASS", .desc = "Backup Tracker bypass", .code = 0x52, .cntmsk = 0xf, .modmsk = HSWEP_UNC_HA_ATTRS, }, { .name = "UNC_H_BYPASS_IMC", .desc = "HA to IMC bypass", .code = 0x14, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_h_bypass_imc), .umasks = hswep_unc_h_bypass_imc, }, { .name = "UNC_H_BT_CYCLES_NE", .desc = "Backup Tracker cycles not empty", .code = 0x42, .cntmsk = 0xf, .modmsk = HSWEP_UNC_HA_ATTRS, }, { .name = "UNC_H_BT_OCCUPANCY", .desc = "Backup Tracker inserts", .code = 0x43, .cntmsk = 0xf, .modmsk = HSWEP_UNC_HA_ATTRS, }, { .name = "UNC_H_OSB", .desc = "OSB snoop broadcast", .code = 0x53, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_h_osb), .umasks = hswep_unc_h_osb, }, { .name = "UNC_H_OSB_EDR", .desc = "OSB early data return", .code = 0x54, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_h_osb_edr), .umasks = hswep_unc_h_osb_edr, }, { .name = "UNC_H_RING_AD_USED", .desc = "AD ring in use", .code = 0x3e, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_h_ring_ad_used), .umasks = hswep_unc_h_ring_ad_used, }, { .name = "UNC_H_RING_AK_USED", .desc = "AK ring in use", .code = 0x3f, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_h_ring_ad_used), /* shared */ .umasks = hswep_unc_h_ring_ad_used, }, { .name = "UNC_H_RING_BL_USED", .desc = "BL ring in use", .code = 0x40, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_h_ring_ad_used), /* shared */ .umasks = hswep_unc_h_ring_ad_used, }, { .name = "UNC_H_DIRECTORY_LAT_OPT", .desc = "Directory latency optimization data return path taken", .code = 0x41, .cntmsk = 0xf, .modmsk = HSWEP_UNC_HA_ATTRS, }, { .name = "UNC_H_SNOOP_RESP_RECV_LOCAL", .desc = "Snoop responses received local", .code = 0x60, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_h_snp_resp_recv_local), .umasks = hswep_unc_h_snp_resp_recv_local, }, { .name = "UNC_H_SNP_RESP_RECV_LOCAL", .desc = "Snoop responses received local", .code = 0x60, .cntmsk = 0xf, .ngrp = 1, .equiv = "UNC_H_SNOOP_RESP_RECV_LOCAL", .modmsk = HSWEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_h_snp_resp_recv_local), .umasks = hswep_unc_h_snp_resp_recv_local, }, { .name = "UNC_H_TXR_BL_OCCUPANCY", .desc = "BL Egress occupancy", .code = 0x34, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_h_txr_bl_occupancy), .umasks = hswep_unc_h_txr_bl_occupancy, }, { .name = "UNC_H_SNOOP_RESP", .desc = "Snoop responses received", .code = 0x21, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_h_snoop_resp), .umasks = hswep_unc_h_snoop_resp }, { .name = "UNC_H_HITME_HIT", .desc = "Hits in the HitMe cache", .code = 0x71, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_h_hitme_hit), .umasks = hswep_unc_h_hitme_hit }, { .name = "UNC_H_HITME_HIT_PV_BITS_SET", .desc = "Number of PV bits set on HitMe cache hits", .code = 0x72, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_h_hitme_hit_pv_bits_set), .umasks = hswep_unc_h_hitme_hit_pv_bits_set }, { .name = "UNC_H_HITME_LOOKUP", .desc = "Number of accesses to HitMe cache", .code = 0x70, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_h_hitme_hit), /* shared with hswep_unc_h_hitme_hit */ .umasks = hswep_unc_h_hitme_hit }, { .name = "UNC_H_SBO0_CREDIT_ACQUIRED", .desc = "SBO0 credits acquired", .code = 0x68, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_h_sbo0_credits_acquired), .umasks = hswep_unc_h_sbo0_credits_acquired, }, { .name = "UNC_H_SBO0_CREDIT_OCCUPANCY", .desc = "SBO0 credits occupancy", .code = 0x6a, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_h_sbo0_credits_acquired), .umasks = hswep_unc_h_sbo0_credits_acquired, /* shared with hswep_unc_h_sbo0_credits_acquired */ }, { .name = "UNC_H_SBO1_CREDIT_ACQUIRED", .desc = "SBO1 credits acquired", .code = 0x69, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_h_sbo0_credits_acquired), .umasks = hswep_unc_h_sbo0_credits_acquired,/* shared with hswep_unc_h_sbo0_credits_acquired */ }, { .name = "UNC_H_SBO0_CREDIT_OCCUPANCY", .desc = "SBO1 credits occupancy", .code = 0x6b, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_h_sbo0_credits_acquired), .umasks = hswep_unc_h_sbo0_credits_acquired, }, { .name = "UNC_H_SNOOPS_RSP_AFTER_DATA", .desc = "Number of reads when the snoops was on the critical path to the data return", .code = 0xa, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_h_snoops_rsp_after_data), .umasks = hswep_unc_h_snoops_rsp_after_data, }, { .name = "UNC_H_SNOOPS_CYCLES_NE", .desc = "Number of cycles when one or more snoops are outstanding", .code = 0x8, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_h_snoops_cycles_ne), .umasks = hswep_unc_h_snoops_cycles_ne, }, { .name = "UNC_H_SNOOPS_OCCUPANCY", .desc = "Tracker snoops outstanding accumulator", .code = 0x9, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_h_snoops_rsp_after_data), .umasks = hswep_unc_h_snoops_rsp_after_data, /* shared */ }, { .name = "UNC_H_STALL_NO_SBO_CREDIT", .desc = "Stalls on no SBO credits", .code = 0x6c, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_h_stall_no_sbo_credit), .umasks = hswep_unc_h_stall_no_sbo_credit, }, { .name = "UNC_H_TRACKER_CYCLES_NE", .desc = "Tracker cycles not empty", .code = 0x3, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_h_snoops_cycles_ne), .umasks = hswep_unc_h_snoops_cycles_ne, /* shared */ }, { .name = "UNC_H_TRACKER_OCCUPANCY", .desc = "Tracker occupancy accumulator", .code = 0x4, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_h_tracker_occupancy), .umasks = hswep_unc_h_tracker_occupancy, }, { .name = "UNC_H_TRACKER_PENDING_OCCUPANCY", .desc = "Data pending occupancy accumulator", .code = 0x5, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_h_snoops_rsp_after_data), .umasks = hswep_unc_h_snoops_rsp_after_data, /* shared */ }, { .name = "UNC_H_TXR_STARVED", .desc = "Injection starvation", .code = 0x6d, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_h_txr_starved), .umasks = hswep_unc_h_txr_starved, }, }; libpfm-4.9.0/lib/events/ppc970mp_events.h0000664000175000017500000021202413223402656020005 0ustar eranianeranian/****************************/ /* THIS IS OPEN SOURCE CODE */ /****************************/ #ifndef __PPC970MP_EVENTS_H__ #define __PPC970MP_EVENTS_H__ /* * File: ppc970mp_events.h * CVS: * Author: Corey Ashford * cjashfor@us.ibm.com * Mods: * * * (C) Copyright IBM Corporation, 2009. All Rights Reserved. * Contributed by Corey Ashford * * Note: This code was automatically generated and should not be modified by * hand. * */ #define PPC970MP_PME_PM_LSU_REJECT_RELOAD_CDF 0 #define PPC970MP_PME_PM_MRK_LSU_SRQ_INST_VALID 1 #define PPC970MP_PME_PM_FPU1_SINGLE 2 #define PPC970MP_PME_PM_FPU0_STALL3 3 #define PPC970MP_PME_PM_TB_BIT_TRANS 4 #define PPC970MP_PME_PM_GPR_MAP_FULL_CYC 5 #define PPC970MP_PME_PM_MRK_ST_CMPL 6 #define PPC970MP_PME_PM_FPU0_STF 7 #define PPC970MP_PME_PM_FPU1_FMA 8 #define PPC970MP_PME_PM_LSU1_FLUSH_ULD 9 #define PPC970MP_PME_PM_MRK_INST_FIN 10 #define PPC970MP_PME_PM_MRK_LSU0_FLUSH_UST 11 #define PPC970MP_PME_PM_LSU_LRQ_S0_ALLOC 12 #define PPC970MP_PME_PM_FPU_FDIV 13 #define PPC970MP_PME_PM_FPU0_FULL_CYC 14 #define PPC970MP_PME_PM_FPU_SINGLE 15 #define PPC970MP_PME_PM_FPU0_FMA 16 #define PPC970MP_PME_PM_MRK_LSU1_FLUSH_ULD 17 #define PPC970MP_PME_PM_LSU1_FLUSH_LRQ 18 #define PPC970MP_PME_PM_DTLB_MISS 19 #define PPC970MP_PME_PM_CMPLU_STALL_FXU 20 #define PPC970MP_PME_PM_MRK_ST_MISS_L1 21 #define PPC970MP_PME_PM_EXT_INT 22 #define PPC970MP_PME_PM_MRK_LSU1_FLUSH_LRQ 23 #define PPC970MP_PME_PM_MRK_ST_GPS 24 #define PPC970MP_PME_PM_GRP_DISP_SUCCESS 25 #define PPC970MP_PME_PM_LSU1_LDF 26 #define PPC970MP_PME_PM_LSU0_SRQ_STFWD 27 #define PPC970MP_PME_PM_CR_MAP_FULL_CYC 28 #define PPC970MP_PME_PM_MRK_LSU0_FLUSH_ULD 29 #define PPC970MP_PME_PM_LSU_DERAT_MISS 30 #define PPC970MP_PME_PM_FPU0_SINGLE 31 #define PPC970MP_PME_PM_FPU1_FDIV 32 #define PPC970MP_PME_PM_FPU1_FEST 33 #define PPC970MP_PME_PM_FPU0_FRSP_FCONV 34 #define PPC970MP_PME_PM_GCT_EMPTY_SRQ_FULL 35 #define PPC970MP_PME_PM_MRK_ST_CMPL_INT 36 #define PPC970MP_PME_PM_FLUSH_BR_MPRED 37 #define PPC970MP_PME_PM_FXU_FIN 38 #define PPC970MP_PME_PM_FPU_STF 39 #define PPC970MP_PME_PM_DSLB_MISS 40 #define PPC970MP_PME_PM_FXLS1_FULL_CYC 41 #define PPC970MP_PME_PM_CMPLU_STALL_FPU 42 #define PPC970MP_PME_PM_LSU_LMQ_LHR_MERGE 43 #define PPC970MP_PME_PM_MRK_STCX_FAIL 44 #define PPC970MP_PME_PM_FXU0_BUSY_FXU1_IDLE 45 #define PPC970MP_PME_PM_CMPLU_STALL_LSU 46 #define PPC970MP_PME_PM_MRK_DATA_FROM_L25_SHR 47 #define PPC970MP_PME_PM_LSU_FLUSH_ULD 48 #define PPC970MP_PME_PM_MRK_BRU_FIN 49 #define PPC970MP_PME_PM_IERAT_XLATE_WR 50 #define PPC970MP_PME_PM_GCT_EMPTY_BR_MPRED 51 #define PPC970MP_PME_PM_LSU0_BUSY 52 #define PPC970MP_PME_PM_DATA_FROM_MEM 53 #define PPC970MP_PME_PM_FPR_MAP_FULL_CYC 54 #define PPC970MP_PME_PM_FPU1_FULL_CYC 55 #define PPC970MP_PME_PM_FPU0_FIN 56 #define PPC970MP_PME_PM_GRP_BR_REDIR 57 #define PPC970MP_PME_PM_GCT_EMPTY_IC_MISS 58 #define PPC970MP_PME_PM_THRESH_TIMEO 59 #define PPC970MP_PME_PM_FPU_FSQRT 60 #define PPC970MP_PME_PM_MRK_LSU0_FLUSH_LRQ 61 #define PPC970MP_PME_PM_PMC1_OVERFLOW 62 #define PPC970MP_PME_PM_FXLS0_FULL_CYC 63 #define PPC970MP_PME_PM_FPU0_ALL 64 #define PPC970MP_PME_PM_DATA_TABLEWALK_CYC 65 #define PPC970MP_PME_PM_FPU0_FEST 66 #define PPC970MP_PME_PM_DATA_FROM_L25_MOD 67 #define PPC970MP_PME_PM_LSU0_REJECT_ERAT_MISS 68 #define PPC970MP_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC 69 #define PPC970MP_PME_PM_LSU0_REJECT_RELOAD_CDF 70 #define PPC970MP_PME_PM_FPU_FEST 71 #define PPC970MP_PME_PM_0INST_FETCH 72 #define PPC970MP_PME_PM_LD_MISS_L1_LSU0 73 #define PPC970MP_PME_PM_LSU1_REJECT_RELOAD_CDF 74 #define PPC970MP_PME_PM_L1_PREF 75 #define PPC970MP_PME_PM_FPU1_STALL3 76 #define PPC970MP_PME_PM_BRQ_FULL_CYC 77 #define PPC970MP_PME_PM_PMC8_OVERFLOW 78 #define PPC970MP_PME_PM_PMC7_OVERFLOW 79 #define PPC970MP_PME_PM_WORK_HELD 80 #define PPC970MP_PME_PM_MRK_LD_MISS_L1_LSU0 81 #define PPC970MP_PME_PM_FXU_IDLE 82 #define PPC970MP_PME_PM_INST_CMPL 83 #define PPC970MP_PME_PM_LSU1_FLUSH_UST 84 #define PPC970MP_PME_PM_LSU0_FLUSH_ULD 85 #define PPC970MP_PME_PM_LSU_FLUSH 86 #define PPC970MP_PME_PM_INST_FROM_L2 87 #define PPC970MP_PME_PM_LSU1_REJECT_LMQ_FULL 88 #define PPC970MP_PME_PM_PMC2_OVERFLOW 89 #define PPC970MP_PME_PM_FPU0_DENORM 90 #define PPC970MP_PME_PM_FPU1_FMOV_FEST 91 #define PPC970MP_PME_PM_INST_FETCH_CYC 92 #define PPC970MP_PME_PM_GRP_DISP_REJECT 93 #define PPC970MP_PME_PM_LSU_LDF 94 #define PPC970MP_PME_PM_INST_DISP 95 #define PPC970MP_PME_PM_DATA_FROM_L25_SHR 96 #define PPC970MP_PME_PM_L1_DCACHE_RELOAD_VALID 97 #define PPC970MP_PME_PM_MRK_GRP_ISSUED 98 #define PPC970MP_PME_PM_FPU_FMA 99 #define PPC970MP_PME_PM_MRK_CRU_FIN 100 #define PPC970MP_PME_PM_CMPLU_STALL_REJECT 101 #define PPC970MP_PME_PM_MRK_LSU1_FLUSH_UST 102 #define PPC970MP_PME_PM_MRK_FXU_FIN 103 #define PPC970MP_PME_PM_LSU1_REJECT_ERAT_MISS 104 #define PPC970MP_PME_PM_BR_ISSUED 105 #define PPC970MP_PME_PM_PMC4_OVERFLOW 106 #define PPC970MP_PME_PM_EE_OFF 107 #define PPC970MP_PME_PM_INST_FROM_L25_MOD 108 #define PPC970MP_PME_PM_CMPLU_STALL_ERAT_MISS 109 #define PPC970MP_PME_PM_ITLB_MISS 110 #define PPC970MP_PME_PM_FXU1_BUSY_FXU0_IDLE 111 #define PPC970MP_PME_PM_GRP_DISP_VALID 112 #define PPC970MP_PME_PM_MRK_GRP_DISP 113 #define PPC970MP_PME_PM_LSU_FLUSH_UST 114 #define PPC970MP_PME_PM_FXU1_FIN 115 #define PPC970MP_PME_PM_GRP_CMPL 116 #define PPC970MP_PME_PM_FPU_FRSP_FCONV 117 #define PPC970MP_PME_PM_MRK_LSU0_FLUSH_SRQ 118 #define PPC970MP_PME_PM_CMPLU_STALL_OTHER 119 #define PPC970MP_PME_PM_LSU_LMQ_FULL_CYC 120 #define PPC970MP_PME_PM_ST_REF_L1_LSU0 121 #define PPC970MP_PME_PM_LSU0_DERAT_MISS 122 #define PPC970MP_PME_PM_LSU_SRQ_SYNC_CYC 123 #define PPC970MP_PME_PM_FPU_STALL3 124 #define PPC970MP_PME_PM_LSU_REJECT_ERAT_MISS 125 #define PPC970MP_PME_PM_MRK_DATA_FROM_L2 126 #define PPC970MP_PME_PM_LSU0_FLUSH_SRQ 127 #define PPC970MP_PME_PM_FPU0_FMOV_FEST 128 #define PPC970MP_PME_PM_IOPS_CMPL 129 #define PPC970MP_PME_PM_LD_REF_L1_LSU0 130 #define PPC970MP_PME_PM_LSU1_FLUSH_SRQ 131 #define PPC970MP_PME_PM_CMPLU_STALL_DIV 132 #define PPC970MP_PME_PM_GRP_BR_MPRED 133 #define PPC970MP_PME_PM_LSU_LMQ_S0_ALLOC 134 #define PPC970MP_PME_PM_LSU0_REJECT_LMQ_FULL 135 #define PPC970MP_PME_PM_ST_REF_L1 136 #define PPC970MP_PME_PM_MRK_VMX_FIN 137 #define PPC970MP_PME_PM_LSU_SRQ_EMPTY_CYC 138 #define PPC970MP_PME_PM_FPU1_STF 139 #define PPC970MP_PME_PM_RUN_CYC 140 #define PPC970MP_PME_PM_LSU_LMQ_S0_VALID 141 #define PPC970MP_PME_PM_LSU0_LDF 142 #define PPC970MP_PME_PM_LSU_LRQ_S0_VALID 143 #define PPC970MP_PME_PM_PMC3_OVERFLOW 144 #define PPC970MP_PME_PM_MRK_IMR_RELOAD 145 #define PPC970MP_PME_PM_MRK_GRP_TIMEO 146 #define PPC970MP_PME_PM_FPU_FMOV_FEST 147 #define PPC970MP_PME_PM_GRP_DISP_BLK_SB_CYC 148 #define PPC970MP_PME_PM_XER_MAP_FULL_CYC 149 #define PPC970MP_PME_PM_ST_MISS_L1 150 #define PPC970MP_PME_PM_STOP_COMPLETION 151 #define PPC970MP_PME_PM_MRK_GRP_CMPL 152 #define PPC970MP_PME_PM_ISLB_MISS 153 #define PPC970MP_PME_PM_SUSPENDED 154 #define PPC970MP_PME_PM_CYC 155 #define PPC970MP_PME_PM_LD_MISS_L1_LSU1 156 #define PPC970MP_PME_PM_STCX_FAIL 157 #define PPC970MP_PME_PM_LSU1_SRQ_STFWD 158 #define PPC970MP_PME_PM_GRP_DISP 159 #define PPC970MP_PME_PM_L2_PREF 160 #define PPC970MP_PME_PM_FPU1_DENORM 161 #define PPC970MP_PME_PM_DATA_FROM_L2 162 #define PPC970MP_PME_PM_FPU0_FPSCR 163 #define PPC970MP_PME_PM_MRK_DATA_FROM_L25_MOD 164 #define PPC970MP_PME_PM_FPU0_FSQRT 165 #define PPC970MP_PME_PM_LD_REF_L1 166 #define PPC970MP_PME_PM_MRK_L1_RELOAD_VALID 167 #define PPC970MP_PME_PM_1PLUS_PPC_CMPL 168 #define PPC970MP_PME_PM_INST_FROM_L1 169 #define PPC970MP_PME_PM_EE_OFF_EXT_INT 170 #define PPC970MP_PME_PM_PMC6_OVERFLOW 171 #define PPC970MP_PME_PM_LSU_LRQ_FULL_CYC 172 #define PPC970MP_PME_PM_IC_PREF_INSTALL 173 #define PPC970MP_PME_PM_DC_PREF_OUT_OF_STREAMS 174 #define PPC970MP_PME_PM_MRK_LSU1_FLUSH_SRQ 175 #define PPC970MP_PME_PM_GCT_FULL_CYC 176 #define PPC970MP_PME_PM_INST_FROM_MEM 177 #define PPC970MP_PME_PM_FLUSH_LSU_BR_MPRED 178 #define PPC970MP_PME_PM_FXU_BUSY 179 #define PPC970MP_PME_PM_ST_REF_L1_LSU1 180 #define PPC970MP_PME_PM_MRK_LD_MISS_L1 181 #define PPC970MP_PME_PM_L1_WRITE_CYC 182 #define PPC970MP_PME_PM_LSU1_BUSY 183 #define PPC970MP_PME_PM_LSU_REJECT_LMQ_FULL 184 #define PPC970MP_PME_PM_CMPLU_STALL_FDIV 185 #define PPC970MP_PME_PM_FPU_ALL 186 #define PPC970MP_PME_PM_LSU_SRQ_S0_ALLOC 187 #define PPC970MP_PME_PM_INST_FROM_L25_SHR 188 #define PPC970MP_PME_PM_GRP_MRK 189 #define PPC970MP_PME_PM_BR_MPRED_CR 190 #define PPC970MP_PME_PM_DC_PREF_STREAM_ALLOC 191 #define PPC970MP_PME_PM_FPU1_FIN 192 #define PPC970MP_PME_PM_LSU_REJECT_SRQ 193 #define PPC970MP_PME_PM_BR_MPRED_TA 194 #define PPC970MP_PME_PM_CRQ_FULL_CYC 195 #define PPC970MP_PME_PM_LD_MISS_L1 196 #define PPC970MP_PME_PM_INST_FROM_PREF 197 #define PPC970MP_PME_PM_STCX_PASS 198 #define PPC970MP_PME_PM_DC_INV_L2 199 #define PPC970MP_PME_PM_LSU_SRQ_FULL_CYC 200 #define PPC970MP_PME_PM_LSU0_FLUSH_LRQ 201 #define PPC970MP_PME_PM_LSU_SRQ_S0_VALID 202 #define PPC970MP_PME_PM_LARX_LSU0 203 #define PPC970MP_PME_PM_GCT_EMPTY_CYC 204 #define PPC970MP_PME_PM_FPU1_ALL 205 #define PPC970MP_PME_PM_FPU1_FSQRT 206 #define PPC970MP_PME_PM_FPU_FIN 207 #define PPC970MP_PME_PM_LSU_SRQ_STFWD 208 #define PPC970MP_PME_PM_MRK_LD_MISS_L1_LSU1 209 #define PPC970MP_PME_PM_FXU0_FIN 210 #define PPC970MP_PME_PM_MRK_FPU_FIN 211 #define PPC970MP_PME_PM_PMC5_OVERFLOW 212 #define PPC970MP_PME_PM_SNOOP_TLBIE 213 #define PPC970MP_PME_PM_FPU1_FRSP_FCONV 214 #define PPC970MP_PME_PM_FPU0_FDIV 215 #define PPC970MP_PME_PM_LD_REF_L1_LSU1 216 #define PPC970MP_PME_PM_HV_CYC 217 #define PPC970MP_PME_PM_LR_CTR_MAP_FULL_CYC 218 #define PPC970MP_PME_PM_FPU_DENORM 219 #define PPC970MP_PME_PM_LSU0_REJECT_SRQ 220 #define PPC970MP_PME_PM_LSU1_REJECT_SRQ 221 #define PPC970MP_PME_PM_LSU1_DERAT_MISS 222 #define PPC970MP_PME_PM_IC_PREF_REQ 223 #define PPC970MP_PME_PM_MRK_LSU_FIN 224 #define PPC970MP_PME_PM_MRK_DATA_FROM_MEM 225 #define PPC970MP_PME_PM_CMPLU_STALL_DCACHE_MISS 226 #define PPC970MP_PME_PM_LSU0_FLUSH_UST 227 #define PPC970MP_PME_PM_LSU_FLUSH_LRQ 228 #define PPC970MP_PME_PM_LSU_FLUSH_SRQ 229 static const pme_power_entry_t ppc970mp_pe[] = { [ PPC970MP_PME_PM_LSU_REJECT_RELOAD_CDF ] = { .pme_name = "PM_LSU_REJECT_RELOAD_CDF", .pme_code = 0x6920, .pme_short_desc = "LSU reject due to reload CDF or tag update collision", .pme_long_desc = "LSU reject due to reload CDF or tag update collision", }, [ PPC970MP_PME_PM_MRK_LSU_SRQ_INST_VALID ] = { .pme_name = "PM_MRK_LSU_SRQ_INST_VALID", .pme_code = 0x936, .pme_short_desc = "Marked instruction valid in SRQ", .pme_long_desc = "This signal is asserted every cycle when a marked request is resident in the Store Request Queue", }, [ PPC970MP_PME_PM_FPU1_SINGLE ] = { .pme_name = "PM_FPU1_SINGLE", .pme_code = 0x127, .pme_short_desc = "FPU1 executed single precision instruction", .pme_long_desc = "This signal is active for one cycle when fp1 is executing single precision instruction.", }, [ PPC970MP_PME_PM_FPU0_STALL3 ] = { .pme_name = "PM_FPU0_STALL3", .pme_code = 0x121, .pme_short_desc = "FPU0 stalled in pipe3", .pme_long_desc = "This signal indicates that fp0 has generated a stall in pipe3 due to overflow, underflow, massive cancel, convert to integer (sometimes), or convert from integer (always). This signal is active during the entire duration of the stall. ", }, [ PPC970MP_PME_PM_TB_BIT_TRANS ] = { .pme_name = "PM_TB_BIT_TRANS", .pme_code = 0x8005, .pme_short_desc = "Time Base bit transition", .pme_long_desc = "When the selected time base bit (as specified in MMCR0[TBSEL])transitions from 0 to 1 ", }, [ PPC970MP_PME_PM_GPR_MAP_FULL_CYC ] = { .pme_name = "PM_GPR_MAP_FULL_CYC", .pme_code = 0x335, .pme_short_desc = "Cycles GPR mapper full", .pme_long_desc = "The ISU sends a signal indicating that the gpr mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.", }, [ PPC970MP_PME_PM_MRK_ST_CMPL ] = { .pme_name = "PM_MRK_ST_CMPL", .pme_code = 0x1003, .pme_short_desc = "Marked store instruction completed", .pme_long_desc = "A sampled store has completed (data home)", }, [ PPC970MP_PME_PM_FPU0_STF ] = { .pme_name = "PM_FPU0_STF", .pme_code = 0x122, .pme_short_desc = "FPU0 executed store instruction", .pme_long_desc = "This signal is active for one cycle when fp0 is executing a store instruction.", }, [ PPC970MP_PME_PM_FPU1_FMA ] = { .pme_name = "PM_FPU1_FMA", .pme_code = 0x105, .pme_short_desc = "FPU1 executed multiply-add instruction", .pme_long_desc = "This signal is active for one cycle when fp1 is executing multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs.", }, [ PPC970MP_PME_PM_LSU1_FLUSH_ULD ] = { .pme_name = "PM_LSU1_FLUSH_ULD", .pme_code = 0x804, .pme_short_desc = "LSU1 unaligned load flushes", .pme_long_desc = "A load was flushed from unit 1 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)", }, [ PPC970MP_PME_PM_MRK_INST_FIN ] = { .pme_name = "PM_MRK_INST_FIN", .pme_code = 0x7005, .pme_short_desc = "Marked instruction finished", .pme_long_desc = "One of the execution units finished a marked instruction. Instructions that finish may not necessary complete", }, [ PPC970MP_PME_PM_MRK_LSU0_FLUSH_UST ] = { .pme_name = "PM_MRK_LSU0_FLUSH_UST", .pme_code = 0x711, .pme_short_desc = "LSU0 marked unaligned store flushes", .pme_long_desc = "A marked store was flushed from unit 0 because it was unaligned", }, [ PPC970MP_PME_PM_LSU_LRQ_S0_ALLOC ] = { .pme_name = "PM_LSU_LRQ_S0_ALLOC", .pme_code = 0x826, .pme_short_desc = "LRQ slot 0 allocated", .pme_long_desc = "LRQ slot zero was allocated", }, [ PPC970MP_PME_PM_FPU_FDIV ] = { .pme_name = "PM_FPU_FDIV", .pme_code = 0x1100, .pme_short_desc = "FPU executed FDIV instruction", .pme_long_desc = "This signal is active for one cycle at the end of the microcode executed when FPU is executing a divide instruction. This could be fdiv, fdivs, fdiv. fdivs. Combined Unit 0 + Unit 1", }, [ PPC970MP_PME_PM_FPU0_FULL_CYC ] = { .pme_name = "PM_FPU0_FULL_CYC", .pme_code = 0x303, .pme_short_desc = "Cycles FPU0 issue queue full", .pme_long_desc = "The issue queue for FPU unit 0 cannot accept any more instructions. Issue is stopped", }, [ PPC970MP_PME_PM_FPU_SINGLE ] = { .pme_name = "PM_FPU_SINGLE", .pme_code = 0x5120, .pme_short_desc = "FPU executed single precision instruction", .pme_long_desc = "FPU is executing single precision instruction. Combined Unit 0 + Unit 1", }, [ PPC970MP_PME_PM_FPU0_FMA ] = { .pme_name = "PM_FPU0_FMA", .pme_code = 0x101, .pme_short_desc = "FPU0 executed multiply-add instruction", .pme_long_desc = "This signal is active for one cycle when fp0 is executing multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs.", }, [ PPC970MP_PME_PM_MRK_LSU1_FLUSH_ULD ] = { .pme_name = "PM_MRK_LSU1_FLUSH_ULD", .pme_code = 0x714, .pme_short_desc = "LSU1 marked unaligned load flushes", .pme_long_desc = "A marked load was flushed from unit 1 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)", }, [ PPC970MP_PME_PM_LSU1_FLUSH_LRQ ] = { .pme_name = "PM_LSU1_FLUSH_LRQ", .pme_code = 0x806, .pme_short_desc = "LSU1 LRQ flushes", .pme_long_desc = "A load was flushed by unit 1 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.", }, [ PPC970MP_PME_PM_DTLB_MISS ] = { .pme_name = "PM_DTLB_MISS", .pme_code = 0x704, .pme_short_desc = "Data TLB misses", .pme_long_desc = "A TLB miss for a data request occurred. Requests that miss the TLB may be retried until the instruction is in the next to complete group (unless HID4 is set to allow speculative tablewalks). This may result in multiple TLB misses for the same instruction.", }, [ PPC970MP_PME_PM_CMPLU_STALL_FXU ] = { .pme_name = "PM_CMPLU_STALL_FXU", .pme_code = 0x508b, .pme_short_desc = "Completion stall caused by FXU instruction", .pme_long_desc = "Completion stall caused by FXU instruction", }, [ PPC970MP_PME_PM_MRK_ST_MISS_L1 ] = { .pme_name = "PM_MRK_ST_MISS_L1", .pme_code = 0x723, .pme_short_desc = "Marked L1 D cache store misses", .pme_long_desc = "A marked store missed the dcache", }, [ PPC970MP_PME_PM_EXT_INT ] = { .pme_name = "PM_EXT_INT", .pme_code = 0x8002, .pme_short_desc = "External interrupts", .pme_long_desc = "An external interrupt occurred", }, [ PPC970MP_PME_PM_MRK_LSU1_FLUSH_LRQ ] = { .pme_name = "PM_MRK_LSU1_FLUSH_LRQ", .pme_code = 0x716, .pme_short_desc = "LSU1 marked LRQ flushes", .pme_long_desc = "A marked load was flushed by unit 1 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.", }, [ PPC970MP_PME_PM_MRK_ST_GPS ] = { .pme_name = "PM_MRK_ST_GPS", .pme_code = 0x6003, .pme_short_desc = "Marked store sent to GPS", .pme_long_desc = "A sampled store has been sent to the memory subsystem", }, [ PPC970MP_PME_PM_GRP_DISP_SUCCESS ] = { .pme_name = "PM_GRP_DISP_SUCCESS", .pme_code = 0x5001, .pme_short_desc = "Group dispatch success", .pme_long_desc = "Number of groups sucessfully dispatched (not rejected)", }, [ PPC970MP_PME_PM_LSU1_LDF ] = { .pme_name = "PM_LSU1_LDF", .pme_code = 0x734, .pme_short_desc = "LSU1 executed Floating Point load instruction", .pme_long_desc = "A floating point load was executed from LSU unit 1", }, [ PPC970MP_PME_PM_LSU0_SRQ_STFWD ] = { .pme_name = "PM_LSU0_SRQ_STFWD", .pme_code = 0x820, .pme_short_desc = "LSU0 SRQ store forwarded", .pme_long_desc = "Data from a store instruction was forwarded to a load on unit 0", }, [ PPC970MP_PME_PM_CR_MAP_FULL_CYC ] = { .pme_name = "PM_CR_MAP_FULL_CYC", .pme_code = 0x304, .pme_short_desc = "Cycles CR logical operation mapper full", .pme_long_desc = "The ISU sends a signal indicating that the cr mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.", }, [ PPC970MP_PME_PM_MRK_LSU0_FLUSH_ULD ] = { .pme_name = "PM_MRK_LSU0_FLUSH_ULD", .pme_code = 0x710, .pme_short_desc = "LSU0 marked unaligned load flushes", .pme_long_desc = "A marked load was flushed from unit 0 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)", }, [ PPC970MP_PME_PM_LSU_DERAT_MISS ] = { .pme_name = "PM_LSU_DERAT_MISS", .pme_code = 0x6700, .pme_short_desc = "DERAT misses", .pme_long_desc = "Total D-ERAT Misses (Unit 0 + Unit 1). Requests that miss the Derat are rejected and retried until the request hits in the Erat. This may result in multiple erat misses for the same instruction.", }, [ PPC970MP_PME_PM_FPU0_SINGLE ] = { .pme_name = "PM_FPU0_SINGLE", .pme_code = 0x123, .pme_short_desc = "FPU0 executed single precision instruction", .pme_long_desc = "This signal is active for one cycle when fp0 is executing single precision instruction.", }, [ PPC970MP_PME_PM_FPU1_FDIV ] = { .pme_name = "PM_FPU1_FDIV", .pme_code = 0x104, .pme_short_desc = "FPU1 executed FDIV instruction", .pme_long_desc = "This signal is active for one cycle at the end of the microcode executed when fp1 is executing a divide instruction. This could be fdiv, fdivs, fdiv. fdivs.", }, [ PPC970MP_PME_PM_FPU1_FEST ] = { .pme_name = "PM_FPU1_FEST", .pme_code = 0x116, .pme_short_desc = "FPU1 executed FEST instruction", .pme_long_desc = "This signal is active for one cycle when fp1 is executing one of the estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ. ", }, [ PPC970MP_PME_PM_FPU0_FRSP_FCONV ] = { .pme_name = "PM_FPU0_FRSP_FCONV", .pme_code = 0x111, .pme_short_desc = "FPU0 executed FRSP or FCONV instructions", .pme_long_desc = "This signal is active for one cycle when fp0 is executing frsp or convert kind of instruction. This could be frsp*, fcfid*, fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs.", }, [ PPC970MP_PME_PM_GCT_EMPTY_SRQ_FULL ] = { .pme_name = "PM_GCT_EMPTY_SRQ_FULL", .pme_code = 0x200b, .pme_short_desc = "GCT empty caused by SRQ full", .pme_long_desc = "GCT empty caused by SRQ full", }, [ PPC970MP_PME_PM_MRK_ST_CMPL_INT ] = { .pme_name = "PM_MRK_ST_CMPL_INT", .pme_code = 0x3003, .pme_short_desc = "Marked store completed with intervention", .pme_long_desc = "A marked store previously sent to the memory subsystem completed (data home) after requiring intervention", }, [ PPC970MP_PME_PM_FLUSH_BR_MPRED ] = { .pme_name = "PM_FLUSH_BR_MPRED", .pme_code = 0x316, .pme_short_desc = "Flush caused by branch mispredict", .pme_long_desc = "Flush caused by branch mispredict", }, [ PPC970MP_PME_PM_FXU_FIN ] = { .pme_name = "PM_FXU_FIN", .pme_code = 0x3330, .pme_short_desc = "FXU produced a result", .pme_long_desc = "The fixed point unit (Unit 0 + Unit 1) finished an instruction. Instructions that finish may not necessary complete.", }, [ PPC970MP_PME_PM_FPU_STF ] = { .pme_name = "PM_FPU_STF", .pme_code = 0x6120, .pme_short_desc = "FPU executed store instruction", .pme_long_desc = "FPU is executing a store instruction. Combined Unit 0 + Unit 1", }, [ PPC970MP_PME_PM_DSLB_MISS ] = { .pme_name = "PM_DSLB_MISS", .pme_code = 0x705, .pme_short_desc = "Data SLB misses", .pme_long_desc = "A SLB miss for a data request occurred. SLB misses trap to the operating system to resolve", }, [ PPC970MP_PME_PM_FXLS1_FULL_CYC ] = { .pme_name = "PM_FXLS1_FULL_CYC", .pme_code = 0x314, .pme_short_desc = "Cycles FXU1/LS1 queue full", .pme_long_desc = "The issue queue for FXU/LSU unit 0 cannot accept any more instructions. Issue is stopped", }, [ PPC970MP_PME_PM_CMPLU_STALL_FPU ] = { .pme_name = "PM_CMPLU_STALL_FPU", .pme_code = 0x704b, .pme_short_desc = "Completion stall caused by FPU instruction", .pme_long_desc = "Completion stall caused by FPU instruction", }, [ PPC970MP_PME_PM_LSU_LMQ_LHR_MERGE ] = { .pme_name = "PM_LSU_LMQ_LHR_MERGE", .pme_code = 0x935, .pme_short_desc = "LMQ LHR merges", .pme_long_desc = "A dcache miss occurred for the same real cache line address as an earlier request already in the Load Miss Queue and was merged into the LMQ entry.", }, [ PPC970MP_PME_PM_MRK_STCX_FAIL ] = { .pme_name = "PM_MRK_STCX_FAIL", .pme_code = 0x726, .pme_short_desc = "Marked STCX failed", .pme_long_desc = "A marked stcx (stwcx or stdcx) failed", }, [ PPC970MP_PME_PM_FXU0_BUSY_FXU1_IDLE ] = { .pme_name = "PM_FXU0_BUSY_FXU1_IDLE", .pme_code = 0x7002, .pme_short_desc = "FXU0 busy FXU1 idle", .pme_long_desc = "FXU0 is busy while FXU1 was idle", }, [ PPC970MP_PME_PM_CMPLU_STALL_LSU ] = { .pme_name = "PM_CMPLU_STALL_LSU", .pme_code = 0x504b, .pme_short_desc = "Completion stall caused by LSU instruction", .pme_long_desc = "Completion stall caused by LSU instruction", }, [ PPC970MP_PME_PM_MRK_DATA_FROM_L25_SHR ] = { .pme_name = "PM_MRK_DATA_FROM_L25_SHR", .pme_code = 0x5937, .pme_short_desc = "Marked data loaded from L2.5 shared", .pme_long_desc = "DL1 was reloaded with shared (T or SL) data from the L2 of a chip on this MCM due to a marked demand load", }, [ PPC970MP_PME_PM_LSU_FLUSH_ULD ] = { .pme_name = "PM_LSU_FLUSH_ULD", .pme_code = 0x1800, .pme_short_desc = "LRQ unaligned load flushes", .pme_long_desc = "A load was flushed because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)", }, [ PPC970MP_PME_PM_MRK_BRU_FIN ] = { .pme_name = "PM_MRK_BRU_FIN", .pme_code = 0x2005, .pme_short_desc = "Marked instruction BRU processing finished", .pme_long_desc = "The branch unit finished a marked instruction. Instructions that finish may not necessary complete", }, [ PPC970MP_PME_PM_IERAT_XLATE_WR ] = { .pme_name = "PM_IERAT_XLATE_WR", .pme_code = 0x430, .pme_short_desc = "Translation written to ierat", .pme_long_desc = "This signal will be asserted each time the I-ERAT is written. This indicates that an ERAT miss has been serviced. ERAT misses will initiate a sequence resulting in the ERAT being written. ERAT misses that are later ignored will not be counted unless the ERAT is written before the instruction stream is changed, This should be a fairly accurate count of ERAT missed (best available).", }, [ PPC970MP_PME_PM_GCT_EMPTY_BR_MPRED ] = { .pme_name = "PM_GCT_EMPTY_BR_MPRED", .pme_code = 0x708c, .pme_short_desc = "GCT empty due to branch mispredict", .pme_long_desc = "GCT empty due to branch mispredict", }, [ PPC970MP_PME_PM_LSU0_BUSY ] = { .pme_name = "PM_LSU0_BUSY", .pme_code = 0x823, .pme_short_desc = "LSU0 busy", .pme_long_desc = "LSU unit 0 is busy rejecting instructions", }, [ PPC970MP_PME_PM_DATA_FROM_MEM ] = { .pme_name = "PM_DATA_FROM_MEM", .pme_code = 0x2837, .pme_short_desc = "Data loaded from memory", .pme_long_desc = "Data loaded from memory", }, [ PPC970MP_PME_PM_FPR_MAP_FULL_CYC ] = { .pme_name = "PM_FPR_MAP_FULL_CYC", .pme_code = 0x301, .pme_short_desc = "Cycles FPR mapper full", .pme_long_desc = "The ISU sends a signal indicating that the FPR mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.", }, [ PPC970MP_PME_PM_FPU1_FULL_CYC ] = { .pme_name = "PM_FPU1_FULL_CYC", .pme_code = 0x307, .pme_short_desc = "Cycles FPU1 issue queue full", .pme_long_desc = "The issue queue for FPU unit 1 cannot accept any more instructions. Issue is stopped", }, [ PPC970MP_PME_PM_FPU0_FIN ] = { .pme_name = "PM_FPU0_FIN", .pme_code = 0x113, .pme_short_desc = "FPU0 produced a result", .pme_long_desc = "fp0 finished, produced a result This only indicates finish, not completion. ", }, [ PPC970MP_PME_PM_GRP_BR_REDIR ] = { .pme_name = "PM_GRP_BR_REDIR", .pme_code = 0x326, .pme_short_desc = "Group experienced branch redirect", .pme_long_desc = "Group experienced branch redirect", }, [ PPC970MP_PME_PM_GCT_EMPTY_IC_MISS ] = { .pme_name = "PM_GCT_EMPTY_IC_MISS", .pme_code = 0x508c, .pme_short_desc = "GCT empty due to I cache miss", .pme_long_desc = "GCT empty due to I cache miss", }, [ PPC970MP_PME_PM_THRESH_TIMEO ] = { .pme_name = "PM_THRESH_TIMEO", .pme_code = 0x2003, .pme_short_desc = "Threshold timeout", .pme_long_desc = "The threshold timer expired", }, [ PPC970MP_PME_PM_FPU_FSQRT ] = { .pme_name = "PM_FPU_FSQRT", .pme_code = 0x6100, .pme_short_desc = "FPU executed FSQRT instruction", .pme_long_desc = "This signal is active for one cycle at the end of the microcode executed when FPU is executing a square root instruction. This could be fsqrt* where XYZ* means XYZ, XYZs, XYZ., XYZs. Combined Unit 0 + Unit 1", }, [ PPC970MP_PME_PM_MRK_LSU0_FLUSH_LRQ ] = { .pme_name = "PM_MRK_LSU0_FLUSH_LRQ", .pme_code = 0x712, .pme_short_desc = "LSU0 marked LRQ flushes", .pme_long_desc = "A marked load was flushed by unit 0 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.", }, [ PPC970MP_PME_PM_PMC1_OVERFLOW ] = { .pme_name = "PM_PMC1_OVERFLOW", .pme_code = 0x200a, .pme_short_desc = "PMC1 Overflow", .pme_long_desc = "PMC1 Overflow", }, [ PPC970MP_PME_PM_FXLS0_FULL_CYC ] = { .pme_name = "PM_FXLS0_FULL_CYC", .pme_code = 0x310, .pme_short_desc = "Cycles FXU0/LS0 queue full", .pme_long_desc = "The issue queue for FXU/LSU unit 0 cannot accept any more instructions. Issue is stopped", }, [ PPC970MP_PME_PM_FPU0_ALL ] = { .pme_name = "PM_FPU0_ALL", .pme_code = 0x103, .pme_short_desc = "FPU0 executed add, mult, sub, cmp or sel instruction", .pme_long_desc = "This signal is active for one cycle when fp0 is executing an add, mult, sub, compare, or fsel kind of instruction. This could be fadd*, fmul*, fsub*, fcmp**, fsel where XYZ* means XYZ, XYZs, XYZ., XYZs. and XYZ** means XYZu, XYZo", }, [ PPC970MP_PME_PM_DATA_TABLEWALK_CYC ] = { .pme_name = "PM_DATA_TABLEWALK_CYC", .pme_code = 0x707, .pme_short_desc = "Cycles doing data tablewalks", .pme_long_desc = "This signal is asserted every cycle when a tablewalk is active. While a tablewalk is active any request attempting to access the TLB will be rejected and retried.", }, [ PPC970MP_PME_PM_FPU0_FEST ] = { .pme_name = "PM_FPU0_FEST", .pme_code = 0x112, .pme_short_desc = "FPU0 executed FEST instruction", .pme_long_desc = "This signal is active for one cycle when fp0 is executing one of the estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ. ", }, [ PPC970MP_PME_PM_DATA_FROM_L25_MOD ] = { .pme_name = "PM_DATA_FROM_L25_MOD", .pme_code = 0x6837, .pme_short_desc = "Data loaded from L2.5 modified", .pme_long_desc = "DL1 was reloaded with modified (M) data from the L2 of a chip on this MCM due to a demand load", }, [ PPC970MP_PME_PM_LSU0_REJECT_ERAT_MISS ] = { .pme_name = "PM_LSU0_REJECT_ERAT_MISS", .pme_code = 0x923, .pme_short_desc = "LSU0 reject due to ERAT miss", .pme_long_desc = "LSU0 reject due to ERAT miss", }, [ PPC970MP_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC ] = { .pme_name = "PM_LSU_LMQ_SRQ_EMPTY_CYC", .pme_code = 0x2002, .pme_short_desc = "Cycles LMQ and SRQ empty", .pme_long_desc = "Cycles when both the LMQ and SRQ are empty (LSU is idle)", }, [ PPC970MP_PME_PM_LSU0_REJECT_RELOAD_CDF ] = { .pme_name = "PM_LSU0_REJECT_RELOAD_CDF", .pme_code = 0x922, .pme_short_desc = "LSU0 reject due to reload CDF or tag update collision", .pme_long_desc = "LSU0 reject due to reload CDF or tag update collision", }, [ PPC970MP_PME_PM_FPU_FEST ] = { .pme_name = "PM_FPU_FEST", .pme_code = 0x3110, .pme_short_desc = "FPU executed FEST instruction", .pme_long_desc = "This signal is active for one cycle when executing one of the estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ. Combined Unit 0 + Unit 1.", }, [ PPC970MP_PME_PM_0INST_FETCH ] = { .pme_name = "PM_0INST_FETCH", .pme_code = 0x442d, .pme_short_desc = "No instructions fetched", .pme_long_desc = "No instructions were fetched this cycles (due to IFU hold, redirect, or icache miss)", }, [ PPC970MP_PME_PM_LD_MISS_L1_LSU0 ] = { .pme_name = "PM_LD_MISS_L1_LSU0", .pme_code = 0x812, .pme_short_desc = "LSU0 L1 D cache load misses", .pme_long_desc = "A load, executing on unit 0, missed the dcache", }, [ PPC970MP_PME_PM_LSU1_REJECT_RELOAD_CDF ] = { .pme_name = "PM_LSU1_REJECT_RELOAD_CDF", .pme_code = 0x926, .pme_short_desc = "LSU1 reject due to reload CDF or tag update collision", .pme_long_desc = "LSU1 reject due to reload CDF or tag update collision", }, [ PPC970MP_PME_PM_L1_PREF ] = { .pme_name = "PM_L1_PREF", .pme_code = 0x731, .pme_short_desc = "L1 cache data prefetches", .pme_long_desc = "A request to prefetch data into the L1 was made", }, [ PPC970MP_PME_PM_FPU1_STALL3 ] = { .pme_name = "PM_FPU1_STALL3", .pme_code = 0x125, .pme_short_desc = "FPU1 stalled in pipe3", .pme_long_desc = "This signal indicates that fp1 has generated a stall in pipe3 due to overflow, underflow, massive cancel, convert to integer (sometimes), or convert from integer (always). This signal is active during the entire duration of the stall. ", }, [ PPC970MP_PME_PM_BRQ_FULL_CYC ] = { .pme_name = "PM_BRQ_FULL_CYC", .pme_code = 0x305, .pme_short_desc = "Cycles branch queue full", .pme_long_desc = "The ISU sends a signal indicating that the issue queue that feeds the ifu br unit cannot accept any more group (queue is full of groups).", }, [ PPC970MP_PME_PM_PMC8_OVERFLOW ] = { .pme_name = "PM_PMC8_OVERFLOW", .pme_code = 0x100a, .pme_short_desc = "PMC8 Overflow", .pme_long_desc = "PMC8 Overflow", }, [ PPC970MP_PME_PM_PMC7_OVERFLOW ] = { .pme_name = "PM_PMC7_OVERFLOW", .pme_code = 0x800a, .pme_short_desc = "PMC7 Overflow", .pme_long_desc = "PMC7 Overflow", }, [ PPC970MP_PME_PM_WORK_HELD ] = { .pme_name = "PM_WORK_HELD", .pme_code = 0x2001, .pme_short_desc = "Work held", .pme_long_desc = "RAS Unit has signaled completion to stop and there are groups waiting to complete", }, [ PPC970MP_PME_PM_MRK_LD_MISS_L1_LSU0 ] = { .pme_name = "PM_MRK_LD_MISS_L1_LSU0", .pme_code = 0x720, .pme_short_desc = "LSU0 L1 D cache load misses", .pme_long_desc = "A marked load, executing on unit 0, missed the dcache", }, [ PPC970MP_PME_PM_FXU_IDLE ] = { .pme_name = "PM_FXU_IDLE", .pme_code = 0x5002, .pme_short_desc = "FXU idle", .pme_long_desc = "FXU0 and FXU1 are both idle", }, [ PPC970MP_PME_PM_INST_CMPL ] = { .pme_name = "PM_INST_CMPL", .pme_code = 0x1, .pme_short_desc = "Instructions completed", .pme_long_desc = "Number of Eligible Instructions that completed. ", }, [ PPC970MP_PME_PM_LSU1_FLUSH_UST ] = { .pme_name = "PM_LSU1_FLUSH_UST", .pme_code = 0x805, .pme_short_desc = "LSU1 unaligned store flushes", .pme_long_desc = "A store was flushed from unit 1 because it was unaligned (crossed a 4k boundary)", }, [ PPC970MP_PME_PM_LSU0_FLUSH_ULD ] = { .pme_name = "PM_LSU0_FLUSH_ULD", .pme_code = 0x800, .pme_short_desc = "LSU0 unaligned load flushes", .pme_long_desc = "A load was flushed from unit 0 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)", }, [ PPC970MP_PME_PM_LSU_FLUSH ] = { .pme_name = "PM_LSU_FLUSH", .pme_code = 0x315, .pme_short_desc = "Flush initiated by LSU", .pme_long_desc = "Flush initiated by LSU", }, [ PPC970MP_PME_PM_INST_FROM_L2 ] = { .pme_name = "PM_INST_FROM_L2", .pme_code = 0x1426, .pme_short_desc = "Instructions fetched from L2", .pme_long_desc = "An instruction fetch group was fetched from L2. Fetch Groups can contain up to 8 instructions", }, [ PPC970MP_PME_PM_LSU1_REJECT_LMQ_FULL ] = { .pme_name = "PM_LSU1_REJECT_LMQ_FULL", .pme_code = 0x925, .pme_short_desc = "LSU1 reject due to LMQ full or missed data coming", .pme_long_desc = "LSU1 reject due to LMQ full or missed data coming", }, [ PPC970MP_PME_PM_PMC2_OVERFLOW ] = { .pme_name = "PM_PMC2_OVERFLOW", .pme_code = 0x300a, .pme_short_desc = "PMC2 Overflow", .pme_long_desc = "PMC2 Overflow", }, [ PPC970MP_PME_PM_FPU0_DENORM ] = { .pme_name = "PM_FPU0_DENORM", .pme_code = 0x120, .pme_short_desc = "FPU0 received denormalized data", .pme_long_desc = "This signal is active for one cycle when one of the operands is denormalized.", }, [ PPC970MP_PME_PM_FPU1_FMOV_FEST ] = { .pme_name = "PM_FPU1_FMOV_FEST", .pme_code = 0x114, .pme_short_desc = "FPU1 executing FMOV or FEST instructions", .pme_long_desc = "This signal is active for one cycle when fp1 is executing a move kind of instruction or one of the estimate instructions.. This could be fmr*, fneg*, fabs*, fnabs* , fres* or frsqrte* where XYZ* means XYZ or XYZ", }, [ PPC970MP_PME_PM_INST_FETCH_CYC ] = { .pme_name = "PM_INST_FETCH_CYC", .pme_code = 0x424, .pme_short_desc = "Cycles at least 1 instruction fetched", .pme_long_desc = "Asserted each cycle when the IFU sends at least one instruction to the IDU. ", }, [ PPC970MP_PME_PM_GRP_DISP_REJECT ] = { .pme_name = "PM_GRP_DISP_REJECT", .pme_code = 0x324, .pme_short_desc = "Group dispatch rejected", .pme_long_desc = "A group that previously attempted dispatch was rejected.", }, [ PPC970MP_PME_PM_LSU_LDF ] = { .pme_name = "PM_LSU_LDF", .pme_code = 0x8730, .pme_short_desc = "LSU executed Floating Point load instruction", .pme_long_desc = "LSU executed Floating Point load instruction", }, [ PPC970MP_PME_PM_INST_DISP ] = { .pme_name = "PM_INST_DISP", .pme_code = 0x320, .pme_short_desc = "Instructions dispatched", .pme_long_desc = "The ISU sends the number of instructions dispatched.", }, [ PPC970MP_PME_PM_DATA_FROM_L25_SHR ] = { .pme_name = "PM_DATA_FROM_L25_SHR", .pme_code = 0x5837, .pme_short_desc = "Data loaded from L2.5 shared", .pme_long_desc = "DL1 was reloaded with shared (T or SL) data from the L2 of a chip on this MCM due to a demand load", }, [ PPC970MP_PME_PM_L1_DCACHE_RELOAD_VALID ] = { .pme_name = "PM_L1_DCACHE_RELOAD_VALID", .pme_code = 0x834, .pme_short_desc = "L1 reload data source valid", .pme_long_desc = "The data source information is valid", }, [ PPC970MP_PME_PM_MRK_GRP_ISSUED ] = { .pme_name = "PM_MRK_GRP_ISSUED", .pme_code = 0x6005, .pme_short_desc = "Marked group issued", .pme_long_desc = "A sampled instruction was issued", }, [ PPC970MP_PME_PM_FPU_FMA ] = { .pme_name = "PM_FPU_FMA", .pme_code = 0x2100, .pme_short_desc = "FPU executed multiply-add instruction", .pme_long_desc = "This signal is active for one cycle when FPU is executing multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs. Combined Unit 0 + Unit 1", }, [ PPC970MP_PME_PM_MRK_CRU_FIN ] = { .pme_name = "PM_MRK_CRU_FIN", .pme_code = 0x4005, .pme_short_desc = "Marked instruction CRU processing finished", .pme_long_desc = "The Condition Register Unit finished a marked instruction. Instructions that finish may not necessary complete", }, [ PPC970MP_PME_PM_CMPLU_STALL_REJECT ] = { .pme_name = "PM_CMPLU_STALL_REJECT", .pme_code = 0x70cb, .pme_short_desc = "Completion stall caused by reject", .pme_long_desc = "Completion stall caused by reject", }, [ PPC970MP_PME_PM_MRK_LSU1_FLUSH_UST ] = { .pme_name = "PM_MRK_LSU1_FLUSH_UST", .pme_code = 0x715, .pme_short_desc = "LSU1 marked unaligned store flushes", .pme_long_desc = "A marked store was flushed from unit 1 because it was unaligned (crossed a 4k boundary)", }, [ PPC970MP_PME_PM_MRK_FXU_FIN ] = { .pme_name = "PM_MRK_FXU_FIN", .pme_code = 0x6004, .pme_short_desc = "Marked instruction FXU processing finished", .pme_long_desc = "Marked instruction FXU processing finished", }, [ PPC970MP_PME_PM_LSU1_REJECT_ERAT_MISS ] = { .pme_name = "PM_LSU1_REJECT_ERAT_MISS", .pme_code = 0x927, .pme_short_desc = "LSU1 reject due to ERAT miss", .pme_long_desc = "LSU1 reject due to ERAT miss", }, [ PPC970MP_PME_PM_BR_ISSUED ] = { .pme_name = "PM_BR_ISSUED", .pme_code = 0x431, .pme_short_desc = "Branches issued", .pme_long_desc = "This signal will be asserted each time the ISU issues a branch instruction. This signal will be asserted each time the ISU selects a branch instruction to issue.", }, [ PPC970MP_PME_PM_PMC4_OVERFLOW ] = { .pme_name = "PM_PMC4_OVERFLOW", .pme_code = 0x500a, .pme_short_desc = "PMC4 Overflow", .pme_long_desc = "PMC4 Overflow", }, [ PPC970MP_PME_PM_EE_OFF ] = { .pme_name = "PM_EE_OFF", .pme_code = 0x333, .pme_short_desc = "Cycles MSR(EE) bit off", .pme_long_desc = "The number of Cycles MSR(EE) bit was off.", }, [ PPC970MP_PME_PM_INST_FROM_L25_MOD ] = { .pme_name = "PM_INST_FROM_L25_MOD", .pme_code = 0x6426, .pme_short_desc = "Instruction fetched from L2.5 modified", .pme_long_desc = "Instruction fetched from L2.5 modified", }, [ PPC970MP_PME_PM_CMPLU_STALL_ERAT_MISS ] = { .pme_name = "PM_CMPLU_STALL_ERAT_MISS", .pme_code = 0x704c, .pme_short_desc = "Completion stall caused by ERAT miss", .pme_long_desc = "Completion stall caused by ERAT miss", }, [ PPC970MP_PME_PM_ITLB_MISS ] = { .pme_name = "PM_ITLB_MISS", .pme_code = 0x700, .pme_short_desc = "Instruction TLB misses", .pme_long_desc = "A TLB miss for an Instruction Fetch has occurred", }, [ PPC970MP_PME_PM_FXU1_BUSY_FXU0_IDLE ] = { .pme_name = "PM_FXU1_BUSY_FXU0_IDLE", .pme_code = 0x4002, .pme_short_desc = "FXU1 busy FXU0 idle", .pme_long_desc = "FXU0 was idle while FXU1 was busy", }, [ PPC970MP_PME_PM_GRP_DISP_VALID ] = { .pme_name = "PM_GRP_DISP_VALID", .pme_code = 0x323, .pme_short_desc = "Group dispatch valid", .pme_long_desc = "Dispatch has been attempted for a valid group. Some groups may be rejected. The total number of successful dispatches is the number of dispatch valid minus dispatch reject.", }, [ PPC970MP_PME_PM_MRK_GRP_DISP ] = { .pme_name = "PM_MRK_GRP_DISP", .pme_code = 0x1002, .pme_short_desc = "Marked group dispatched", .pme_long_desc = "A group containing a sampled instruction was dispatched", }, [ PPC970MP_PME_PM_LSU_FLUSH_UST ] = { .pme_name = "PM_LSU_FLUSH_UST", .pme_code = 0x2800, .pme_short_desc = "SRQ unaligned store flushes", .pme_long_desc = "A store was flushed because it was unaligned", }, [ PPC970MP_PME_PM_FXU1_FIN ] = { .pme_name = "PM_FXU1_FIN", .pme_code = 0x336, .pme_short_desc = "FXU1 produced a result", .pme_long_desc = "The Fixed Point unit 1 finished an instruction and produced a result", }, [ PPC970MP_PME_PM_GRP_CMPL ] = { .pme_name = "PM_GRP_CMPL", .pme_code = 0x7003, .pme_short_desc = "Group completed", .pme_long_desc = "A group completed. Microcoded instructions that span multiple groups will generate this event once per group.", }, [ PPC970MP_PME_PM_FPU_FRSP_FCONV ] = { .pme_name = "PM_FPU_FRSP_FCONV", .pme_code = 0x7110, .pme_short_desc = "FPU executed FRSP or FCONV instructions", .pme_long_desc = "This signal is active for one cycle when executing frsp or convert kind of instruction. This could be frsp*, fcfid*, fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs. Combined Unit 0 + Unit 1", }, [ PPC970MP_PME_PM_MRK_LSU0_FLUSH_SRQ ] = { .pme_name = "PM_MRK_LSU0_FLUSH_SRQ", .pme_code = 0x713, .pme_short_desc = "LSU0 marked SRQ flushes", .pme_long_desc = "A marked store was flushed because younger load hits and older store that is already in the SRQ or in the same group.", }, [ PPC970MP_PME_PM_CMPLU_STALL_OTHER ] = { .pme_name = "PM_CMPLU_STALL_OTHER", .pme_code = 0x100b, .pme_short_desc = "Completion stall caused by other reason", .pme_long_desc = "Completion stall caused by other reason", }, [ PPC970MP_PME_PM_LSU_LMQ_FULL_CYC ] = { .pme_name = "PM_LSU_LMQ_FULL_CYC", .pme_code = 0x837, .pme_short_desc = "Cycles LMQ full", .pme_long_desc = "The LMQ was full", }, [ PPC970MP_PME_PM_ST_REF_L1_LSU0 ] = { .pme_name = "PM_ST_REF_L1_LSU0", .pme_code = 0x811, .pme_short_desc = "LSU0 L1 D cache store references", .pme_long_desc = "A store executed on unit 0", }, [ PPC970MP_PME_PM_LSU0_DERAT_MISS ] = { .pme_name = "PM_LSU0_DERAT_MISS", .pme_code = 0x702, .pme_short_desc = "LSU0 DERAT misses", .pme_long_desc = "A data request (load or store) from LSU Unit 0 missed the ERAT and resulted in an ERAT reload. Multiple instructions may miss the ERAT entry for the same 4K page, but only one reload will occur.", }, [ PPC970MP_PME_PM_LSU_SRQ_SYNC_CYC ] = { .pme_name = "PM_LSU_SRQ_SYNC_CYC", .pme_code = 0x735, .pme_short_desc = "SRQ sync duration", .pme_long_desc = "This signal is asserted every cycle when a sync is in the SRQ.", }, [ PPC970MP_PME_PM_FPU_STALL3 ] = { .pme_name = "PM_FPU_STALL3", .pme_code = 0x2120, .pme_short_desc = "FPU stalled in pipe3", .pme_long_desc = "FPU has generated a stall in pipe3 due to overflow, underflow, massive cancel, convert to integer (sometimes), or convert from integer (always). This signal is active during the entire duration of the stall. Combined Unit 0 + Unit 1", }, [ PPC970MP_PME_PM_LSU_REJECT_ERAT_MISS ] = { .pme_name = "PM_LSU_REJECT_ERAT_MISS", .pme_code = 0x5920, .pme_short_desc = "LSU reject due to ERAT miss", .pme_long_desc = "LSU reject due to ERAT miss", }, [ PPC970MP_PME_PM_MRK_DATA_FROM_L2 ] = { .pme_name = "PM_MRK_DATA_FROM_L2", .pme_code = 0x1937, .pme_short_desc = "Marked data loaded from L2", .pme_long_desc = "DL1 was reloaded from the local L2 due to a marked demand load", }, [ PPC970MP_PME_PM_LSU0_FLUSH_SRQ ] = { .pme_name = "PM_LSU0_FLUSH_SRQ", .pme_code = 0x803, .pme_short_desc = "LSU0 SRQ flushes", .pme_long_desc = "A store was flushed because younger load hits and older store that is already in the SRQ or in the same group.", }, [ PPC970MP_PME_PM_FPU0_FMOV_FEST ] = { .pme_name = "PM_FPU0_FMOV_FEST", .pme_code = 0x110, .pme_short_desc = "FPU0 executed FMOV or FEST instructions", .pme_long_desc = "This signal is active for one cycle when fp0 is executing a move kind of instruction or one of the estimate instructions.. This could be fmr*, fneg*, fabs*, fnabs* , fres* or frsqrte* where XYZ* means XYZ or XYZ", }, [ PPC970MP_PME_PM_IOPS_CMPL ] = { .pme_name = "PM_IOPS_CMPL", .pme_code = 0x1001, .pme_short_desc = "IOPS instructions completed", .pme_long_desc = "Number of IOPS Instructions that completed.", }, [ PPC970MP_PME_PM_LD_REF_L1_LSU0 ] = { .pme_name = "PM_LD_REF_L1_LSU0", .pme_code = 0x810, .pme_short_desc = "LSU0 L1 D cache load references", .pme_long_desc = "A load executed on unit 0", }, [ PPC970MP_PME_PM_LSU1_FLUSH_SRQ ] = { .pme_name = "PM_LSU1_FLUSH_SRQ", .pme_code = 0x807, .pme_short_desc = "LSU1 SRQ flushes", .pme_long_desc = "A store was flushed because younger load hits and older store that is already in the SRQ or in the same group. ", }, [ PPC970MP_PME_PM_CMPLU_STALL_DIV ] = { .pme_name = "PM_CMPLU_STALL_DIV", .pme_code = 0x708b, .pme_short_desc = "Completion stall caused by DIV instruction", .pme_long_desc = "Completion stall caused by DIV instruction", }, [ PPC970MP_PME_PM_GRP_BR_MPRED ] = { .pme_name = "PM_GRP_BR_MPRED", .pme_code = 0x327, .pme_short_desc = "Group experienced a branch mispredict", .pme_long_desc = "Group experienced a branch mispredict", }, [ PPC970MP_PME_PM_LSU_LMQ_S0_ALLOC ] = { .pme_name = "PM_LSU_LMQ_S0_ALLOC", .pme_code = 0x836, .pme_short_desc = "LMQ slot 0 allocated", .pme_long_desc = "The first entry in the LMQ was allocated.", }, [ PPC970MP_PME_PM_LSU0_REJECT_LMQ_FULL ] = { .pme_name = "PM_LSU0_REJECT_LMQ_FULL", .pme_code = 0x921, .pme_short_desc = "LSU0 reject due to LMQ full or missed data coming", .pme_long_desc = "LSU0 reject due to LMQ full or missed data coming", }, [ PPC970MP_PME_PM_ST_REF_L1 ] = { .pme_name = "PM_ST_REF_L1", .pme_code = 0x7810, .pme_short_desc = "L1 D cache store references", .pme_long_desc = "Total DL1 Store references", }, [ PPC970MP_PME_PM_MRK_VMX_FIN ] = { .pme_name = "PM_MRK_VMX_FIN", .pme_code = 0x3005, .pme_short_desc = "Marked instruction VMX processing finished", .pme_long_desc = "Marked instruction VMX processing finished", }, [ PPC970MP_PME_PM_LSU_SRQ_EMPTY_CYC ] = { .pme_name = "PM_LSU_SRQ_EMPTY_CYC", .pme_code = 0x4003, .pme_short_desc = "Cycles SRQ empty", .pme_long_desc = "The Store Request Queue is empty", }, [ PPC970MP_PME_PM_FPU1_STF ] = { .pme_name = "PM_FPU1_STF", .pme_code = 0x126, .pme_short_desc = "FPU1 executed store instruction", .pme_long_desc = "This signal is active for one cycle when fp1 is executing a store instruction.", }, [ PPC970MP_PME_PM_RUN_CYC ] = { .pme_name = "PM_RUN_CYC", .pme_code = 0x1005, .pme_short_desc = "Run cycles", .pme_long_desc = "Processor Cycles gated by the run latch", }, [ PPC970MP_PME_PM_LSU_LMQ_S0_VALID ] = { .pme_name = "PM_LSU_LMQ_S0_VALID", .pme_code = 0x835, .pme_short_desc = "LMQ slot 0 valid", .pme_long_desc = "This signal is asserted every cycle when the first entry in the LMQ is valid. The LMQ had eight entries that are allocated FIFO", }, [ PPC970MP_PME_PM_LSU0_LDF ] = { .pme_name = "PM_LSU0_LDF", .pme_code = 0x730, .pme_short_desc = "LSU0 executed Floating Point load instruction", .pme_long_desc = "A floating point load was executed from LSU unit 0", }, [ PPC970MP_PME_PM_LSU_LRQ_S0_VALID ] = { .pme_name = "PM_LSU_LRQ_S0_VALID", .pme_code = 0x822, .pme_short_desc = "LRQ slot 0 valid", .pme_long_desc = "This signal is asserted every cycle that the Load Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin.", }, [ PPC970MP_PME_PM_PMC3_OVERFLOW ] = { .pme_name = "PM_PMC3_OVERFLOW", .pme_code = 0x400a, .pme_short_desc = "PMC3 Overflow", .pme_long_desc = "PMC3 Overflow", }, [ PPC970MP_PME_PM_MRK_IMR_RELOAD ] = { .pme_name = "PM_MRK_IMR_RELOAD", .pme_code = 0x722, .pme_short_desc = "Marked IMR reloaded", .pme_long_desc = "A DL1 reload occurred due to marked load", }, [ PPC970MP_PME_PM_MRK_GRP_TIMEO ] = { .pme_name = "PM_MRK_GRP_TIMEO", .pme_code = 0x5005, .pme_short_desc = "Marked group completion timeout", .pme_long_desc = "The sampling timeout expired indicating that the previously sampled instruction is no longer in the processor", }, [ PPC970MP_PME_PM_FPU_FMOV_FEST ] = { .pme_name = "PM_FPU_FMOV_FEST", .pme_code = 0x8110, .pme_short_desc = "FPU executing FMOV or FEST instructions", .pme_long_desc = "This signal is active for one cycle when executing a move kind of instruction or one of the estimate instructions.. This could be fmr*, fneg*, fabs*, fnabs* , fres* or frsqrte* where XYZ* means XYZ or XYZ . Combined Unit 0 + Unit 1", }, [ PPC970MP_PME_PM_GRP_DISP_BLK_SB_CYC ] = { .pme_name = "PM_GRP_DISP_BLK_SB_CYC", .pme_code = 0x331, .pme_short_desc = "Cycles group dispatch blocked by scoreboard", .pme_long_desc = "The ISU sends a signal indicating that dispatch is blocked by scoreboard.", }, [ PPC970MP_PME_PM_XER_MAP_FULL_CYC ] = { .pme_name = "PM_XER_MAP_FULL_CYC", .pme_code = 0x302, .pme_short_desc = "Cycles XER mapper full", .pme_long_desc = "The ISU sends a signal indicating that the xer mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.", }, [ PPC970MP_PME_PM_ST_MISS_L1 ] = { .pme_name = "PM_ST_MISS_L1", .pme_code = 0x813, .pme_short_desc = "L1 D cache store misses", .pme_long_desc = "A store missed the dcache", }, [ PPC970MP_PME_PM_STOP_COMPLETION ] = { .pme_name = "PM_STOP_COMPLETION", .pme_code = 0x3001, .pme_short_desc = "Completion stopped", .pme_long_desc = "RAS Unit has signaled completion to stop", }, [ PPC970MP_PME_PM_MRK_GRP_CMPL ] = { .pme_name = "PM_MRK_GRP_CMPL", .pme_code = 0x4004, .pme_short_desc = "Marked group completed", .pme_long_desc = "A group containing a sampled instruction completed. Microcoded instructions that span multiple groups will generate this event once per group.", }, [ PPC970MP_PME_PM_ISLB_MISS ] = { .pme_name = "PM_ISLB_MISS", .pme_code = 0x701, .pme_short_desc = "Instruction SLB misses", .pme_long_desc = "A SLB miss for an instruction fetch as occurred", }, [ PPC970MP_PME_PM_SUSPENDED ] = { .pme_name = "PM_SUSPENDED", .pme_code = 0x0, .pme_short_desc = "Suspended", .pme_long_desc = "Suspended", }, [ PPC970MP_PME_PM_CYC ] = { .pme_name = "PM_CYC", .pme_code = 0x7, .pme_short_desc = "Processor cycles", .pme_long_desc = "Processor cycles", }, [ PPC970MP_PME_PM_LD_MISS_L1_LSU1 ] = { .pme_name = "PM_LD_MISS_L1_LSU1", .pme_code = 0x816, .pme_short_desc = "LSU1 L1 D cache load misses", .pme_long_desc = "A load, executing on unit 1, missed the dcache", }, [ PPC970MP_PME_PM_STCX_FAIL ] = { .pme_name = "PM_STCX_FAIL", .pme_code = 0x721, .pme_short_desc = "STCX failed", .pme_long_desc = "A stcx (stwcx or stdcx) failed", }, [ PPC970MP_PME_PM_LSU1_SRQ_STFWD ] = { .pme_name = "PM_LSU1_SRQ_STFWD", .pme_code = 0x824, .pme_short_desc = "LSU1 SRQ store forwarded", .pme_long_desc = "Data from a store instruction was forwarded to a load on unit 1", }, [ PPC970MP_PME_PM_GRP_DISP ] = { .pme_name = "PM_GRP_DISP", .pme_code = 0x2004, .pme_short_desc = "Group dispatches", .pme_long_desc = "A group was dispatched", }, [ PPC970MP_PME_PM_L2_PREF ] = { .pme_name = "PM_L2_PREF", .pme_code = 0x733, .pme_short_desc = "L2 cache prefetches", .pme_long_desc = "A request to prefetch data into L2 was made", }, [ PPC970MP_PME_PM_FPU1_DENORM ] = { .pme_name = "PM_FPU1_DENORM", .pme_code = 0x124, .pme_short_desc = "FPU1 received denormalized data", .pme_long_desc = "This signal is active for one cycle when one of the operands is denormalized.", }, [ PPC970MP_PME_PM_DATA_FROM_L2 ] = { .pme_name = "PM_DATA_FROM_L2", .pme_code = 0x1837, .pme_short_desc = "Data loaded from L2", .pme_long_desc = "DL1 was reloaded from the local L2 due to a demand load", }, [ PPC970MP_PME_PM_FPU0_FPSCR ] = { .pme_name = "PM_FPU0_FPSCR", .pme_code = 0x130, .pme_short_desc = "FPU0 executed FPSCR instruction", .pme_long_desc = "This signal is active for one cycle when fp0 is executing fpscr move related instruction. This could be mtfsfi*, mtfsb0*, mtfsb1*. mffs*, mtfsf*, mcrsf* where XYZ* means XYZ, XYZs, XYZ., XYZs", }, [ PPC970MP_PME_PM_MRK_DATA_FROM_L25_MOD ] = { .pme_name = "PM_MRK_DATA_FROM_L25_MOD", .pme_code = 0x6937, .pme_short_desc = "Marked data loaded from L2.5 modified", .pme_long_desc = "DL1 was reloaded with modified (M) data from the L2 of a chip on this MCM due to a marked demand load", }, [ PPC970MP_PME_PM_FPU0_FSQRT ] = { .pme_name = "PM_FPU0_FSQRT", .pme_code = 0x102, .pme_short_desc = "FPU0 executed FSQRT instruction", .pme_long_desc = "This signal is active for one cycle at the end of the microcode executed when fp0 is executing a square root instruction. This could be fsqrt* where XYZ* means XYZ, XYZs, XYZ., XYZs.", }, [ PPC970MP_PME_PM_LD_REF_L1 ] = { .pme_name = "PM_LD_REF_L1", .pme_code = 0x8810, .pme_short_desc = "L1 D cache load references", .pme_long_desc = "Total DL1 Load references", }, [ PPC970MP_PME_PM_MRK_L1_RELOAD_VALID ] = { .pme_name = "PM_MRK_L1_RELOAD_VALID", .pme_code = 0x934, .pme_short_desc = "Marked L1 reload data source valid", .pme_long_desc = "The source information is valid and is for a marked load", }, [ PPC970MP_PME_PM_1PLUS_PPC_CMPL ] = { .pme_name = "PM_1PLUS_PPC_CMPL", .pme_code = 0x5003, .pme_short_desc = "One or more PPC instruction completed", .pme_long_desc = "A group containing at least one PPC instruction completed. For microcoded instructions that span multiple groups, this will only occur once.", }, [ PPC970MP_PME_PM_INST_FROM_L1 ] = { .pme_name = "PM_INST_FROM_L1", .pme_code = 0x142d, .pme_short_desc = "Instruction fetched from L1", .pme_long_desc = "An instruction fetch group was fetched from L1. Fetch Groups can contain up to 8 instructions", }, [ PPC970MP_PME_PM_EE_OFF_EXT_INT ] = { .pme_name = "PM_EE_OFF_EXT_INT", .pme_code = 0x337, .pme_short_desc = "Cycles MSR(EE) bit off and external interrupt pending", .pme_long_desc = "Cycles MSR(EE) bit off and external interrupt pending", }, [ PPC970MP_PME_PM_PMC6_OVERFLOW ] = { .pme_name = "PM_PMC6_OVERFLOW", .pme_code = 0x700a, .pme_short_desc = "PMC6 Overflow", .pme_long_desc = "PMC6 Overflow", }, [ PPC970MP_PME_PM_LSU_LRQ_FULL_CYC ] = { .pme_name = "PM_LSU_LRQ_FULL_CYC", .pme_code = 0x312, .pme_short_desc = "Cycles LRQ full", .pme_long_desc = "The ISU sends this signal when the LRQ is full.", }, [ PPC970MP_PME_PM_IC_PREF_INSTALL ] = { .pme_name = "PM_IC_PREF_INSTALL", .pme_code = 0x427, .pme_short_desc = "Instruction prefetched installed in prefetch", .pme_long_desc = "New line coming into the prefetch buffer", }, [ PPC970MP_PME_PM_DC_PREF_OUT_OF_STREAMS ] = { .pme_name = "PM_DC_PREF_OUT_OF_STREAMS", .pme_code = 0x732, .pme_short_desc = "D cache out of streams", .pme_long_desc = "out of streams", }, [ PPC970MP_PME_PM_MRK_LSU1_FLUSH_SRQ ] = { .pme_name = "PM_MRK_LSU1_FLUSH_SRQ", .pme_code = 0x717, .pme_short_desc = "LSU1 marked SRQ flushes", .pme_long_desc = "A marked store was flushed because younger load hits and older store that is already in the SRQ or in the same group.", }, [ PPC970MP_PME_PM_GCT_FULL_CYC ] = { .pme_name = "PM_GCT_FULL_CYC", .pme_code = 0x300, .pme_short_desc = "Cycles GCT full", .pme_long_desc = "The ISU sends a signal indicating the gct is full. ", }, [ PPC970MP_PME_PM_INST_FROM_MEM ] = { .pme_name = "PM_INST_FROM_MEM", .pme_code = 0x2426, .pme_short_desc = "Instruction fetched from memory", .pme_long_desc = "Instruction fetched from memory", }, [ PPC970MP_PME_PM_FLUSH_LSU_BR_MPRED ] = { .pme_name = "PM_FLUSH_LSU_BR_MPRED", .pme_code = 0x317, .pme_short_desc = "Flush caused by LSU or branch mispredict", .pme_long_desc = "Flush caused by LSU or branch mispredict", }, [ PPC970MP_PME_PM_FXU_BUSY ] = { .pme_name = "PM_FXU_BUSY", .pme_code = 0x6002, .pme_short_desc = "FXU busy", .pme_long_desc = "FXU0 and FXU1 are both busy", }, [ PPC970MP_PME_PM_ST_REF_L1_LSU1 ] = { .pme_name = "PM_ST_REF_L1_LSU1", .pme_code = 0x815, .pme_short_desc = "LSU1 L1 D cache store references", .pme_long_desc = "A store executed on unit 1", }, [ PPC970MP_PME_PM_MRK_LD_MISS_L1 ] = { .pme_name = "PM_MRK_LD_MISS_L1", .pme_code = 0x1720, .pme_short_desc = "Marked L1 D cache load misses", .pme_long_desc = "Marked L1 D cache load misses", }, [ PPC970MP_PME_PM_L1_WRITE_CYC ] = { .pme_name = "PM_L1_WRITE_CYC", .pme_code = 0x434, .pme_short_desc = "Cycles writing to instruction L1", .pme_long_desc = "This signal is asserted each cycle a cache write is active.", }, [ PPC970MP_PME_PM_LSU1_BUSY ] = { .pme_name = "PM_LSU1_BUSY", .pme_code = 0x827, .pme_short_desc = "LSU1 busy", .pme_long_desc = "LSU unit 0 is busy rejecting instructions ", }, [ PPC970MP_PME_PM_LSU_REJECT_LMQ_FULL ] = { .pme_name = "PM_LSU_REJECT_LMQ_FULL", .pme_code = 0x2920, .pme_short_desc = "LSU reject due to LMQ full or missed data coming", .pme_long_desc = "LSU reject due to LMQ full or missed data coming", }, [ PPC970MP_PME_PM_CMPLU_STALL_FDIV ] = { .pme_name = "PM_CMPLU_STALL_FDIV", .pme_code = 0x504c, .pme_short_desc = "Completion stall caused by FDIV or FQRT instruction", .pme_long_desc = "Completion stall caused by FDIV or FQRT instruction", }, [ PPC970MP_PME_PM_FPU_ALL ] = { .pme_name = "PM_FPU_ALL", .pme_code = 0x5100, .pme_short_desc = "FPU executed add, mult, sub, cmp or sel instruction", .pme_long_desc = "This signal is active for one cycle when FPU is executing an add, mult, sub, compare, or fsel kind of instruction. This could be fadd*, fmul*, fsub*, fcmp**, fsel where XYZ* means XYZ, XYZs, XYZ., XYZs. and XYZ** means XYZu, XYZo. Combined Unit 0 + Unit 1", }, [ PPC970MP_PME_PM_LSU_SRQ_S0_ALLOC ] = { .pme_name = "PM_LSU_SRQ_S0_ALLOC", .pme_code = 0x825, .pme_short_desc = "SRQ slot 0 allocated", .pme_long_desc = "SRQ Slot zero was allocated", }, [ PPC970MP_PME_PM_INST_FROM_L25_SHR ] = { .pme_name = "PM_INST_FROM_L25_SHR", .pme_code = 0x5426, .pme_short_desc = "Instruction fetched from L2.5 shared", .pme_long_desc = "Instruction fetched from L2.5 shared", }, [ PPC970MP_PME_PM_GRP_MRK ] = { .pme_name = "PM_GRP_MRK", .pme_code = 0x5004, .pme_short_desc = "Group marked in IDU", .pme_long_desc = "A group was sampled (marked)", }, [ PPC970MP_PME_PM_BR_MPRED_CR ] = { .pme_name = "PM_BR_MPRED_CR", .pme_code = 0x432, .pme_short_desc = "Branch mispredictions due to CR bit setting", .pme_long_desc = "This signal is asserted when the branch execution unit detects a branch mispredict because the CR value is opposite of the predicted value. This signal is asserted after a branch issue event and will result in a branch redirect flush if not overridden by a flush of an older instruction.", }, [ PPC970MP_PME_PM_DC_PREF_STREAM_ALLOC ] = { .pme_name = "PM_DC_PREF_STREAM_ALLOC", .pme_code = 0x737, .pme_short_desc = "D cache new prefetch stream allocated", .pme_long_desc = "A new Prefetch Stream was allocated", }, [ PPC970MP_PME_PM_FPU1_FIN ] = { .pme_name = "PM_FPU1_FIN", .pme_code = 0x117, .pme_short_desc = "FPU1 produced a result", .pme_long_desc = "fp1 finished, produced a result. This only indicates finish, not completion. ", }, [ PPC970MP_PME_PM_LSU_REJECT_SRQ ] = { .pme_name = "PM_LSU_REJECT_SRQ", .pme_code = 0x1920, .pme_short_desc = "LSU SRQ rejects", .pme_long_desc = "LSU SRQ rejects", }, [ PPC970MP_PME_PM_BR_MPRED_TA ] = { .pme_name = "PM_BR_MPRED_TA", .pme_code = 0x433, .pme_short_desc = "Branch mispredictions due to target address", .pme_long_desc = "branch miss predict due to a target address prediction. This signal will be asserted each time the branch execution unit detects an incorrect target address prediction. This signal will be asserted after a valid branch execution unit issue and will cause a branch mispredict flush unless a flush is detected from an older instruction.", }, [ PPC970MP_PME_PM_CRQ_FULL_CYC ] = { .pme_name = "PM_CRQ_FULL_CYC", .pme_code = 0x311, .pme_short_desc = "Cycles CR issue queue full", .pme_long_desc = "The ISU sends a signal indicating that the issue queue that feeds the ifu cr unit cannot accept any more group (queue is full of groups).", }, [ PPC970MP_PME_PM_LD_MISS_L1 ] = { .pme_name = "PM_LD_MISS_L1", .pme_code = 0x3810, .pme_short_desc = "L1 D cache load misses", .pme_long_desc = "Total DL1 Load references that miss the DL1", }, [ PPC970MP_PME_PM_INST_FROM_PREF ] = { .pme_name = "PM_INST_FROM_PREF", .pme_code = 0x342d, .pme_short_desc = "Instructions fetched from prefetch", .pme_long_desc = "An instruction fetch group was fetched from the prefetch buffer. Fetch Groups can contain up to 8 instructions", }, [ PPC970MP_PME_PM_STCX_PASS ] = { .pme_name = "PM_STCX_PASS", .pme_code = 0x725, .pme_short_desc = "Stcx passes", .pme_long_desc = "A stcx (stwcx or stdcx) instruction was successful", }, [ PPC970MP_PME_PM_DC_INV_L2 ] = { .pme_name = "PM_DC_INV_L2", .pme_code = 0x817, .pme_short_desc = "L1 D cache entries invalidated from L2", .pme_long_desc = "A dcache invalidated was received from the L2 because a line in L2 was castout.", }, [ PPC970MP_PME_PM_LSU_SRQ_FULL_CYC ] = { .pme_name = "PM_LSU_SRQ_FULL_CYC", .pme_code = 0x313, .pme_short_desc = "Cycles SRQ full", .pme_long_desc = "The ISU sends this signal when the srq is full.", }, [ PPC970MP_PME_PM_LSU0_FLUSH_LRQ ] = { .pme_name = "PM_LSU0_FLUSH_LRQ", .pme_code = 0x802, .pme_short_desc = "LSU0 LRQ flushes", .pme_long_desc = "A load was flushed by unit 1 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.", }, [ PPC970MP_PME_PM_LSU_SRQ_S0_VALID ] = { .pme_name = "PM_LSU_SRQ_S0_VALID", .pme_code = 0x821, .pme_short_desc = "SRQ slot 0 valid", .pme_long_desc = "This signal is asserted every cycle that the Store Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin.", }, [ PPC970MP_PME_PM_LARX_LSU0 ] = { .pme_name = "PM_LARX_LSU0", .pme_code = 0x727, .pme_short_desc = "Larx executed on LSU0", .pme_long_desc = "A larx (lwarx or ldarx) was executed on side 0 (there is no coresponding unit 1 event since larx instructions can only execute on unit 0)", }, [ PPC970MP_PME_PM_GCT_EMPTY_CYC ] = { .pme_name = "PM_GCT_EMPTY_CYC", .pme_code = 0x1004, .pme_short_desc = "Cycles GCT empty", .pme_long_desc = "The Global Completion Table is completely empty", }, [ PPC970MP_PME_PM_FPU1_ALL ] = { .pme_name = "PM_FPU1_ALL", .pme_code = 0x107, .pme_short_desc = "FPU1 executed add, mult, sub, cmp or sel instruction", .pme_long_desc = "This signal is active for one cycle when fp1 is executing an add, mult, sub, compare, or fsel kind of instruction. This could be fadd*, fmul*, fsub*, fcmp**, fsel where XYZ* means XYZ, XYZs, XYZ., XYZs. and XYZ** means XYZu, XYZo", }, [ PPC970MP_PME_PM_FPU1_FSQRT ] = { .pme_name = "PM_FPU1_FSQRT", .pme_code = 0x106, .pme_short_desc = "FPU1 executed FSQRT instruction", .pme_long_desc = "This signal is active for one cycle at the end of the microcode executed when fp1 is executing a square root instruction. This could be fsqrt* where XYZ* means XYZ, XYZs, XYZ., XYZs.", }, [ PPC970MP_PME_PM_FPU_FIN ] = { .pme_name = "PM_FPU_FIN", .pme_code = 0x4110, .pme_short_desc = "FPU produced a result", .pme_long_desc = "FPU finished, produced a result This only indicates finish, not completion. Combined Unit 0 + Unit 1", }, [ PPC970MP_PME_PM_LSU_SRQ_STFWD ] = { .pme_name = "PM_LSU_SRQ_STFWD", .pme_code = 0x1820, .pme_short_desc = "SRQ store forwarded", .pme_long_desc = "Data from a store instruction was forwarded to a load", }, [ PPC970MP_PME_PM_MRK_LD_MISS_L1_LSU1 ] = { .pme_name = "PM_MRK_LD_MISS_L1_LSU1", .pme_code = 0x724, .pme_short_desc = "LSU1 L1 D cache load misses", .pme_long_desc = "A marked load, executing on unit 1, missed the dcache", }, [ PPC970MP_PME_PM_FXU0_FIN ] = { .pme_name = "PM_FXU0_FIN", .pme_code = 0x332, .pme_short_desc = "FXU0 produced a result", .pme_long_desc = "The Fixed Point unit 0 finished an instruction and produced a result", }, [ PPC970MP_PME_PM_MRK_FPU_FIN ] = { .pme_name = "PM_MRK_FPU_FIN", .pme_code = 0x7004, .pme_short_desc = "Marked instruction FPU processing finished", .pme_long_desc = "One of the Floating Point Units finished a marked instruction. Instructions that finish may not necessary complete", }, [ PPC970MP_PME_PM_PMC5_OVERFLOW ] = { .pme_name = "PM_PMC5_OVERFLOW", .pme_code = 0x600a, .pme_short_desc = "PMC5 Overflow", .pme_long_desc = "PMC5 Overflow", }, [ PPC970MP_PME_PM_SNOOP_TLBIE ] = { .pme_name = "PM_SNOOP_TLBIE", .pme_code = 0x703, .pme_short_desc = "Snoop TLBIE", .pme_long_desc = "A TLB miss for a data request occurred. Requests that miss the TLB may be retried until the instruction is in the next to complete group (unless HID4 is set to allow speculative tablewalks). This may result in multiple TLB misses for the same instruction.", }, [ PPC970MP_PME_PM_FPU1_FRSP_FCONV ] = { .pme_name = "PM_FPU1_FRSP_FCONV", .pme_code = 0x115, .pme_short_desc = "FPU1 executed FRSP or FCONV instructions", .pme_long_desc = "This signal is active for one cycle when fp1 is executing frsp or convert kind of instruction. This could be frsp*, fcfid*, fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs.", }, [ PPC970MP_PME_PM_FPU0_FDIV ] = { .pme_name = "PM_FPU0_FDIV", .pme_code = 0x100, .pme_short_desc = "FPU0 executed FDIV instruction", .pme_long_desc = "This signal is active for one cycle at the end of the microcode executed when fp0 is executing a divide instruction. This could be fdiv, fdivs, fdiv. fdivs.", }, [ PPC970MP_PME_PM_LD_REF_L1_LSU1 ] = { .pme_name = "PM_LD_REF_L1_LSU1", .pme_code = 0x814, .pme_short_desc = "LSU1 L1 D cache load references", .pme_long_desc = "A load executed on unit 1", }, [ PPC970MP_PME_PM_HV_CYC ] = { .pme_name = "PM_HV_CYC", .pme_code = 0x3004, .pme_short_desc = "Hypervisor Cycles", .pme_long_desc = "Cycles when the processor is executing in Hypervisor (MSR[HV] = 1 and MSR[PR]=0)", }, [ PPC970MP_PME_PM_LR_CTR_MAP_FULL_CYC ] = { .pme_name = "PM_LR_CTR_MAP_FULL_CYC", .pme_code = 0x306, .pme_short_desc = "Cycles LR/CTR mapper full", .pme_long_desc = "The ISU sends a signal indicating that the lr/ctr mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.", }, [ PPC970MP_PME_PM_FPU_DENORM ] = { .pme_name = "PM_FPU_DENORM", .pme_code = 0x1120, .pme_short_desc = "FPU received denormalized data", .pme_long_desc = "This signal is active for one cycle when one of the operands is denormalized. Combined Unit 0 + Unit 1", }, [ PPC970MP_PME_PM_LSU0_REJECT_SRQ ] = { .pme_name = "PM_LSU0_REJECT_SRQ", .pme_code = 0x920, .pme_short_desc = "LSU0 SRQ rejects", .pme_long_desc = "LSU0 SRQ rejects", }, [ PPC970MP_PME_PM_LSU1_REJECT_SRQ ] = { .pme_name = "PM_LSU1_REJECT_SRQ", .pme_code = 0x924, .pme_short_desc = "LSU1 SRQ rejects", .pme_long_desc = "LSU1 SRQ rejects", }, [ PPC970MP_PME_PM_LSU1_DERAT_MISS ] = { .pme_name = "PM_LSU1_DERAT_MISS", .pme_code = 0x706, .pme_short_desc = "LSU1 DERAT misses", .pme_long_desc = "A data request (load or store) from LSU Unit 1 missed the ERAT and resulted in an ERAT reload. Multiple instructions may miss the ERAT entry for the same 4K page, but only one reload will occur.", }, [ PPC970MP_PME_PM_IC_PREF_REQ ] = { .pme_name = "PM_IC_PREF_REQ", .pme_code = 0x426, .pme_short_desc = "Instruction prefetch requests", .pme_long_desc = "Asserted when a non-canceled prefetch is made to the cache interface unit (CIU).", }, [ PPC970MP_PME_PM_MRK_LSU_FIN ] = { .pme_name = "PM_MRK_LSU_FIN", .pme_code = 0x8004, .pme_short_desc = "Marked instruction LSU processing finished", .pme_long_desc = "One of the Load/Store Units finished a marked instruction. Instructions that finish may not necessary complete", }, [ PPC970MP_PME_PM_MRK_DATA_FROM_MEM ] = { .pme_name = "PM_MRK_DATA_FROM_MEM", .pme_code = 0x2937, .pme_short_desc = "Marked data loaded from memory", .pme_long_desc = "Marked data loaded from memory", }, [ PPC970MP_PME_PM_CMPLU_STALL_DCACHE_MISS ] = { .pme_name = "PM_CMPLU_STALL_DCACHE_MISS", .pme_code = 0x50cb, .pme_short_desc = "Completion stall caused by D cache miss", .pme_long_desc = "Completion stall caused by D cache miss", }, [ PPC970MP_PME_PM_LSU0_FLUSH_UST ] = { .pme_name = "PM_LSU0_FLUSH_UST", .pme_code = 0x801, .pme_short_desc = "LSU0 unaligned store flushes", .pme_long_desc = "A store was flushed from unit 0 because it was unaligned (crossed a 4k boundary)", }, [ PPC970MP_PME_PM_LSU_FLUSH_LRQ ] = { .pme_name = "PM_LSU_FLUSH_LRQ", .pme_code = 0x6800, .pme_short_desc = "LRQ flushes", .pme_long_desc = "A load was flushed because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.", }, [ PPC970MP_PME_PM_LSU_FLUSH_SRQ ] = { .pme_name = "PM_LSU_FLUSH_SRQ", .pme_code = 0x5800, .pme_short_desc = "SRQ flushes", .pme_long_desc = "A store was flushed because younger load hits and older store that is already in the SRQ or in the same group.", } }; #endif libpfm-4.9.0/lib/events/arm_cortex_a15_events.h0000664000175000017500000002325113223402656021241 0ustar eranianeranian/* * Copyright (c) 2012 Google, Inc * Contributed by Stephane Eranian * Contributed by Will Deacon * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * Cortex A15 r2p0 * based on Table 11-6 from the "Cortex A15 Technical Reference Manual" */ static const arm_entry_t arm_cortex_a15_pe[]={ {.name = "SW_INCR", .modmsk = ARMV7_A15_ATTRS, .code = 0x00, .desc = "Instruction architecturally executed (condition check pass) Software increment" }, {.name = "L1I_CACHE_REFILL", .modmsk = ARMV7_A15_ATTRS, .code = 0x01, .desc = "Level 1 instruction cache refill" }, {.name = "L1I_TLB_REFILL", .modmsk = ARMV7_A15_ATTRS, .code = 0x02, .desc = "Level 1 instruction TLB refill" }, {.name = "L1D_CACHE_REFILL", .modmsk = ARMV7_A15_ATTRS, .code = 0x03, .desc = "Level 1 data cache refill" }, {.name = "L1D_CACHE_ACCESS", .modmsk = ARMV7_A15_ATTRS, .code = 0x04, .desc = "Level 1 data cache access" }, {.name = "L1D_TLB_REFILL", .modmsk = ARMV7_A15_ATTRS, .code = 0x05, .desc = "Level 1 data TLB refill" }, {.name = "INST_RETIRED", .modmsk = ARMV7_A15_ATTRS, .code = 0x08, .desc = "Instruction architecturally executed" }, {.name = "EXCEPTION_TAKEN", .modmsk = ARMV7_A15_ATTRS, .code = 0x09, .desc = "Exception taken" }, {.name = "EXCEPTION_RETURN", .modmsk = ARMV7_A15_ATTRS, .code = 0x0a, .desc = "Instruction architecturally executed (condition check pass) Exception return" }, {.name = "CID_WRITE_RETIRED", .modmsk = ARMV7_A15_ATTRS, .code = 0x0b, .desc = "Instruction architecturally executed (condition check pass) Write to CONTEXTIDR" }, {.name = "BRANCH_MISPRED", .modmsk = ARMV7_A15_ATTRS, .code = 0x10, .desc = "Mispredicted or not predicted branch speculatively executed" }, {.name = "CPU_CYCLES", .modmsk = ARMV7_A15_ATTRS, .code = 0x11, .desc = "Cycles" }, {.name = "BRANCH_PRED", .modmsk = ARMV7_A15_ATTRS, .code = 0x12, .desc = "Predictable branch speculatively executed" }, {.name = "DATA_MEM_ACCESS", .modmsk = ARMV7_A15_ATTRS, .code = 0x13, .desc = "Data memory access" }, {.name = "L1I_CACHE_ACCESS", .modmsk = ARMV7_A15_ATTRS, .code = 0x14, .desc = "Level 1 instruction cache access" }, {.name = "L1D_CACHE_WB", .modmsk = ARMV7_A15_ATTRS, .code = 0x15, .desc = "Level 1 data cache WriteBack" }, {.name = "L2D_CACHE_ACCESS", .modmsk = ARMV7_A15_ATTRS, .code = 0x16, .desc = "Level 2 data cache access" }, {.name = "L2D_CACHE_REFILL", .modmsk = ARMV7_A15_ATTRS, .code = 0x17, .desc = "Level 2 data cache refill" }, {.name = "L2D_CACHE_WB", .modmsk = ARMV7_A15_ATTRS, .code = 0x18, .desc = "Level 2 data cache WriteBack" }, {.name = "BUS_ACCESS", .modmsk = ARMV7_A15_ATTRS, .code = 0x19, .desc = "Bus access" }, {.name = "LOCAL_MEMORY_ERROR", .modmsk = ARMV7_A15_ATTRS, .code = 0x1a, .desc = "Local memory error" }, {.name = "INST_SPEC_EXEC", .modmsk = ARMV7_A15_ATTRS, .code = 0x1b, .desc = "Instruction speculatively executed" }, {.name = "TTBR_WRITE_RETIRED", .modmsk = ARMV7_A15_ATTRS, .code = 0x1c, .desc = "Instruction architecturally executed (condition check pass) Write to translation table base" }, {.name = "BUS_CYCLES", .modmsk = ARMV7_A15_ATTRS, .code = 0x1d, .desc = "Bus cycle" }, {.name = "L1D_READ_ACCESS", .modmsk = ARMV7_A15_ATTRS, .code = 0x40, .desc = "Level 1 data cache read access" }, {.name = "L1D_WRITE_ACCESS", .modmsk = ARMV7_A15_ATTRS, .code = 0x41, .desc = "Level 1 data cache write access" }, {.name = "L1D_READ_REFILL", .modmsk = ARMV7_A15_ATTRS, .code = 0x42, .desc = "Level 1 data cache read refill" }, {.name = "L1D_WRITE_REFILL", .modmsk = ARMV7_A15_ATTRS, .code = 0x43, .desc = "Level 1 data cache write refill" }, {.name = "L1D_WB_VICTIM", .modmsk = ARMV7_A15_ATTRS, .code = 0x46, .desc = "Level 1 data cache writeback victim" }, {.name = "L1D_WB_CLEAN_COHERENCY", .modmsk = ARMV7_A15_ATTRS, .code = 0x47, .desc = "Level 1 data cache writeback cleaning and coherency" }, {.name = "L1D_INVALIDATE", .modmsk = ARMV7_A15_ATTRS, .code = 0x48, .desc = "Level 1 data cache invalidate" }, {.name = "L1D_TLB_READ_REFILL", .modmsk = ARMV7_A15_ATTRS, .code = 0x4c, .desc = "Level 1 data TLB read refill" }, {.name = "L1D_TLB_WRITE_REFILL", .modmsk = ARMV7_A15_ATTRS, .code = 0x4d, .desc = "Level 1 data TLB write refill" }, {.name = "L2D_READ_ACCESS", .modmsk = ARMV7_A15_ATTRS, .code = 0x50, .desc = "Level 2 data cache read access" }, {.name = "L2D_WRITE_ACCESS", .modmsk = ARMV7_A15_ATTRS, .code = 0x51, .desc = "Level 2 data cache write access" }, {.name = "L2D_READ_REFILL", .modmsk = ARMV7_A15_ATTRS, .code = 0x52, .desc = "Level 2 data cache read refill" }, {.name = "L2D_WRITE_REFILL", .modmsk = ARMV7_A15_ATTRS, .code = 0x53, .desc = "Level 2 data cache write refill" }, {.name = "L2D_WB_VICTIM", .modmsk = ARMV7_A15_ATTRS, .code = 0x56, .desc = "Level 2 data cache writeback victim" }, {.name = "L2D_WB_CLEAN_COHERENCY", .modmsk = ARMV7_A15_ATTRS, .code = 0x57, .desc = "Level 2 data cache writeback cleaning and coherency" }, {.name = "L2D_INVALIDATE", .modmsk = ARMV7_A15_ATTRS, .code = 0x58, .desc = "Level 2 data cache invalidate" }, {.name = "BUS_READ_ACCESS", .modmsk = ARMV7_A15_ATTRS, .code = 0x60, .desc = "Bus read access" }, {.name = "BUS_WRITE_ACCESS", .modmsk = ARMV7_A15_ATTRS, .code = 0x61, .desc = "Bus write access" }, {.name = "BUS_NORMAL_ACCESS", .modmsk = ARMV7_A15_ATTRS, .code = 0x62, .desc = "Bus normal access" }, {.name = "BUS_NOT_NORMAL_ACCESS", .modmsk = ARMV7_A15_ATTRS, .code = 0x63, .desc = "Bus not normal access" }, {.name = "BUS_NORMAL_ACCESS_2", .modmsk = ARMV7_A15_ATTRS, .code = 0x64, .desc = "Bus normal access" }, {.name = "BUS_PERIPH_ACCESS", .modmsk = ARMV7_A15_ATTRS, .code = 0x65, .desc = "Bus peripheral access" }, {.name = "DATA_MEM_READ_ACCESS", .modmsk = ARMV7_A15_ATTRS, .code = 0x66, .desc = "Data memory read access" }, {.name = "DATA_MEM_WRITE_ACCESS", .modmsk = ARMV7_A15_ATTRS, .code = 0x67, .desc = "Data memory write access" }, {.name = "UNALIGNED_READ_ACCESS", .modmsk = ARMV7_A15_ATTRS, .code = 0x68, .desc = "Unaligned read access" }, {.name = "UNALIGNED_WRITE_ACCESS", .modmsk = ARMV7_A15_ATTRS, .code = 0x69, .desc = "Unaligned read access" }, {.name = "UNALIGNED_ACCESS", .modmsk = ARMV7_A15_ATTRS, .code = 0x6a, .desc = "Unaligned access" }, {.name = "INST_SPEC_EXEC_LDREX", .modmsk = ARMV7_A15_ATTRS, .code = 0x6c, .desc = "LDREX exclusive instruction speculatively executed" }, {.name = "INST_SPEC_EXEC_STREX_PASS", .modmsk = ARMV7_A15_ATTRS, .code = 0x6d, .desc = "STREX pass exclusive instruction speculatively executed" }, {.name = "INST_SPEC_EXEC_STREX_FAIL", .modmsk = ARMV7_A15_ATTRS, .code = 0x6e, .desc = "STREX fail exclusive instruction speculatively executed" }, {.name = "INST_SPEC_EXEC_LOAD", .modmsk = ARMV7_A15_ATTRS, .code = 0x70, .desc = "Load instruction speculatively executed" }, {.name = "INST_SPEC_EXEC_STORE", .modmsk = ARMV7_A15_ATTRS, .code = 0x71, .desc = "Store instruction speculatively executed" }, {.name = "INST_SPEC_EXEC_LOAD_STORE", .modmsk = ARMV7_A15_ATTRS, .code = 0x72, .desc = "Load or store instruction speculatively executed" }, {.name = "INST_SPEC_EXEC_INTEGER_INST", .modmsk = ARMV7_A15_ATTRS, .code = 0x73, .desc = "Integer data processing instruction speculatively executed" }, {.name = "INST_SPEC_EXEC_SIMD", .modmsk = ARMV7_A15_ATTRS, .code = 0x74, .desc = "Advanced SIMD instruction speculatively executed" }, {.name = "INST_SPEC_EXEC_VFP", .modmsk = ARMV7_A15_ATTRS, .code = 0x75, .desc = "VFP instruction speculatively executed" }, {.name = "INST_SPEC_EXEC_SOFT_PC", .modmsk = ARMV7_A15_ATTRS, .code = 0x76, .desc = "Software of the PC instruction speculatively executed" }, {.name = "BRANCH_SPEC_EXEC_IMM_BRANCH", .modmsk = ARMV7_A15_ATTRS, .code = 0x78, .desc = "Immediate branch speculatively executed" }, {.name = "BRANCH_SPEC_EXEC_RET", .modmsk = ARMV7_A15_ATTRS, .code = 0x79, .desc = "Return branch speculatively executed" }, {.name = "BRANCH_SPEC_EXEC_IND", .modmsk = ARMV7_A15_ATTRS, .code = 0x7a, .desc = "Indirect branch speculatively executed" }, {.name = "BARRIER_SPEC_EXEC_ISB", .modmsk = ARMV7_A15_ATTRS, .code = 0x7c, .desc = "ISB barrier speculatively executed" }, {.name = "BARRIER_SPEC_EXEC_DSB", .modmsk = ARMV7_A15_ATTRS, .code = 0x7d, .desc = "DSB barrier speculatively executed" }, {.name = "BARRIER_SPEC_EXEC_DMB", .modmsk = ARMV7_A15_ATTRS, .code = 0x7e, .desc = "DMB barrier speculatively executed" }, }; libpfm-4.9.0/lib/events/intel_knc_events.h0000664000175000017500000003546013223402656020403 0ustar eranianeranian/* * Copyright (c) 2012 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * PMU: knc (Intel Knights Corners) */ static const intel_x86_entry_t intel_knc_pe[]={ { .name = "BANK_CONFLICTS", .desc = "Number of actual bank conflicts", .code = 0xa, .cntmsk = 0x3, .modmsk = INTEL_V3_ATTRS, }, { .name = "BRANCHES", .desc = "Number of taken and not taken branches, including: conditional branches, jumps, calls, returns, software interrupts, and interrupt returns", .code = 0x12, .cntmsk = 0x3, .modmsk = INTEL_V3_ATTRS, }, { .name = "BRANCHES_MISPREDICTED", .desc = "Number of branch mispredictions that occurred on BTB hits. BTB misses are not considered branch mispredicts because no prediction exists for them yet.", .code = 0x2b, .cntmsk = 0x3, .modmsk = INTEL_V3_ATTRS, }, { .name = "CODE_CACHE_MISS", .desc = "Number of instruction reads that miss the internal code cache; whether the read is cacheable or noncacheable", .code = 0xe, .cntmsk = 0x3, .modmsk = INTEL_V3_ATTRS, }, { .name = "CODE_PAGE_WALK", .desc = "Number of code page walks", .code = 0xd, .cntmsk = 0x3, .modmsk = INTEL_V3_ATTRS, }, { .name = "CODE_READ", .desc = "Number of instruction reads; whether the read is cacheable or noncacheable", .code = 0xc, .cntmsk = 0x3, .modmsk = INTEL_V3_ATTRS, }, { .name = "CPU_CLK_UNHALTED", .desc = "Number of cycles during which the processor is not halted.", .code = 0x2a, .cntmsk = 0x3, .modmsk = INTEL_V3_ATTRS, }, { .name = "DATA_CACHE_LINES_WRITTEN_BACK", .desc = "Number of dirty lines (all) that are written back, regardless of the cause", .code = 0x6, .cntmsk = 0x3, .modmsk = INTEL_V3_ATTRS, }, { .name = "DATA_PAGE_WALK", .desc = "Number of data page walks", .code = 0x2, .cntmsk = 0x3, .modmsk = INTEL_V3_ATTRS, }, { .name = "DATA_READ", .desc = "Number of successful memory data reads committed by the K-unit (L1). Cache accesses resulting from prefetch instructions are included for A0 stepping.", .code = 0x0, .cntmsk = 0x3, .modmsk = INTEL_V3_ATTRS, }, { .name = "DATA_READ_MISS", .desc = "Number of memory read accesses that miss the internal data cache whether or not the access is cacheable or noncacheable. Cache accesses resulting from prefetch instructions are not included.", .code = 0x3, .cntmsk = 0x3, .modmsk = INTEL_V3_ATTRS, }, { .name = "DATA_READ_MISS_OR_WRITE_MISS", .desc = "Number of memory read and/or write accesses that miss the internal data cache, whether or not the access is cacheable or noncacheable", .code = 0x29, .cntmsk = 0x3, .modmsk = INTEL_V3_ATTRS, }, { .name = "DATA_READ_OR_WRITE", .desc = "Number of memory data reads and/or writes (internal data cache hit and miss combined). Read cache accesses resulting from prefetch instructions are included for A0 stepping.", .code = 0x28, .cntmsk = 0x3, .modmsk = INTEL_V3_ATTRS, }, { .name = "DATA_WRITE", .desc = "Number of successful memory data writes committed by the K-unit (L1). Streaming stores (hit/miss L1), cacheable write partials, and UC promotions are all included.", .code = 0x1, .cntmsk = 0x3, .modmsk = INTEL_V3_ATTRS, }, { .name = "DATA_WRITE_MISS", .desc = "Number of memory write accesses that miss the internal data cache whether or not the access is cacheable. Non-cacheable misses are not included.", .code = 0x4, .cntmsk = 0x3, .modmsk = INTEL_V3_ATTRS, }, { .name = "EXEC_STAGE_CYCLES", .desc = "Number of E-stage cycles that were successfully completed. Includes cycles generated by multi-cycle E-stage instructions. For instructions destined for the FPU or VPU pipelines, this event only counts occupancy in the integer E-stage.", .code = 0x2e, .cntmsk = 0x3, .modmsk = INTEL_V3_ATTRS, }, { .name = "FE_STALLED", .desc = "Number of cycles where the front-end could not advance. Any multi-cycle instructions which delay pipeline advance and apply backpressure to the front-end will be included, e.g. read-modify-write instructions. Includes cycles when the front-end did not have any instructions to issue.", .code = 0x2d, .cntmsk = 0x3, .modmsk = INTEL_V3_ATTRS, }, { .name = "INSTRUCTIONS_EXECUTED", .desc = "Number of instructions executed (up to two per clock)", .code = 0x16, .cntmsk = 0x3, .modmsk = INTEL_V3_ATTRS, }, { .name = "INSTRUCTIONS_EXECUTED_V_PIPE", .desc = "Number of instructions executed in the V_pipe. The event indicates the number of instructions that were paired.", .code = 0x17, .cntmsk = 0x3, .modmsk = INTEL_V3_ATTRS, }, { .name = "L1_DATA_HIT_INFLIGHT_PF1", .desc = "Number of data requests which hit an in-flight vprefetch0. The in-flight vprefetch0 was not necessarily issued from the same thread as the data request.", .code = 0x20, .cntmsk = 0x3, .modmsk = INTEL_V3_ATTRS, }, { .name = "L1_DATA_PF1", .desc = "Number of data vprefetch0 requests seen by the L1.", .code = 0x11, .cntmsk = 0x3, .modmsk = INTEL_V3_ATTRS, }, { .name = "L1_DATA_PF1_DROP", .desc = "Number of data vprefetch0 requests seen by the L1 which were dropped for any reason. A vprefetch0 can be dropped if the requested address matches another in-flight request or if it has a UC memtype.", .code = 0x1e, .cntmsk = 0x3, .modmsk = INTEL_V3_ATTRS, }, { .name = "L1_DATA_PF1_MISS", .desc = "Number of data vprefetch0 requests seen by the L1 which missed L1. Does not include vprefetch1 requests which are counted in L1_DATA_PF1_DROP.", .code = 0x1c, .cntmsk = 0x3, .modmsk = INTEL_V3_ATTRS, }, { .name = "L1_DATA_PF2", .desc = "Number of data vprefetch1 requests seen by the L1. This is not necessarily the same number as seen by the L2 because this count includes requests that are dropped by the core. A vprefetch1 can be dropped by the core if the requested address matches another in-flight request or if it has a UC memtype.", .code = 0x37, .cntmsk = 0x3, .modmsk = INTEL_V3_ATTRS, }, { .name = "L2_CODE_READ_MISS_CACHE_FILL", .desc = "Number of code read accesses that missed the L2 cache and were satisfied by another L2 cache. Can include promoted read misses that started as DATA accesses.", .code = 0x10f0, .cntmsk = 0x3, .modmsk = INTEL_V3_ATTRS, }, { .name = "L2_CODE_READ_MISS_MEM_FILL", .desc = "Number of code read accesses that missed the L2 cache and were satisfied by main memory. Can include promoted read misses that started as DATA accesses.", .code = 0x10f5, .cntmsk = 0x3, .modmsk = INTEL_V3_ATTRS, }, { .name = "L2_DATA_HIT_INFLIGHT_PF2", .desc = "Number of data requests which hit an in-flight vprefetch1. The in-flight vprefetch1 was not necessarily issued from the same thread as the data request.", .code = 0x10ff, .cntmsk = 0x1, .modmsk = INTEL_V3_ATTRS, }, { .name = "L2_DATA_PF1_MISS", .desc = "Number of data vprefetch0 requests seen by the L2 which missed L2.", .code = 0x38, .cntmsk = 0x3, .modmsk = INTEL_V3_ATTRS, }, { .name = "L2_DATA_PF2", .desc = "Number of data vprefetch1 requests seen by the L2. Only counts vprefetch1 hits on A0 stepping.", .code = 0x10fc, .cntmsk = 0x1, .modmsk = INTEL_V3_ATTRS, }, { .name = "L2_DATA_PF2_DROP", .desc = "Number of data vprefetch1 requests seen by the L2 which were dropped for any reason.", .code = 0x10fd, .cntmsk = 0x1, .modmsk = INTEL_V3_ATTRS, }, { .name = "L2_DATA_PF2_MISS", .desc = "Number of data vprefetch1 requests seen by the L2 which missed L2. Does not include vprefetch2 requests which are counted in L2_DATA_PF2_DROP.", .code = 0x10fe, .cntmsk = 0x1, .modmsk = INTEL_V3_ATTRS, }, { .name = "L2_DATA_READ_MISS_CACHE_FILL", .desc = "Number of data read accesses that missed the L2 cache and were satisfied by another L2 cache. Can include promoted read misses that started as CODE accesses.", .code = 0x10f1, .cntmsk = 0x1, .modmsk = INTEL_V3_ATTRS, }, { .name = "L2_DATA_READ_MISS_MEM_FILL", .desc = "Number of data read accesses that missed the L2 cache and were satisfied by main memory. Can include promoted read misses that started as CODE accesses.", .code = 0x10f6, .cntmsk = 0x1, .modmsk = INTEL_V3_ATTRS, }, { .name = "L2_DATA_WRITE_MISS_CACHE_FILL", .desc = "Number of data write (RFO) accesses that missed the L2 cache and were satisfied by another L2 cache.", .code = 0x10f2, .cntmsk = 0x1, .modmsk = INTEL_V3_ATTRS, }, { .name = "L2_DATA_WRITE_MISS_MEM_FILL", .desc = "Number of data write (RFO) accesses that missed the L2 cache and were satisfied by main memory.", .code = 0x10f7, .cntmsk = 0x1, .modmsk = INTEL_V3_ATTRS, }, { .name = "L2_READ_HIT_E", .desc = "L2 Read Hit E State, may include prefetches on A0 stepping.", .code = 0x10c8, .cntmsk = 0x1, .modmsk = INTEL_V3_ATTRS, }, { .name = "L2_READ_HIT_M", .desc = "L2 Read Hit M State", .code = 0x10c9, .cntmsk = 0x1, .modmsk = INTEL_V3_ATTRS, }, { .name = "L2_READ_HIT_S", .desc = "L2 Read Hit S State", .code = 0x10ca, .cntmsk = 0x1, .modmsk = INTEL_V3_ATTRS, }, { .name = "L2_READ_MISS", .desc = "L2 Read Misses. Prefetch and demand requests to the same address will produce double counting.", .code = 0x10cb, .cntmsk = 0x1, .modmsk = INTEL_V3_ATTRS, }, { .name = "L2_VICTIM_REQ_WITH_DATA", .desc = "L2 received a victim request and responded with data", .code = 0x10d7, .cntmsk = 0x1, .modmsk = INTEL_V3_ATTRS, }, { .name = "L2_WRITE_HIT", .desc = "L2 Write HIT, may undercount on A0 stepping.", .code = 0x10cc, .cntmsk = 0x1, .modmsk = INTEL_V3_ATTRS, }, { .name = "LONG_CODE_PAGE_WALK", .desc = "Number of long code page walks, i.e. page walks that also missed the L2 uTLB. Subset of DATA_CODE_WALK event", .code = 0x3b, .cntmsk = 0x3, .modmsk = INTEL_V3_ATTRS, }, { .name = "LONG_DATA_PAGE_WALK", .desc = "Number of long data page walks, i.e. page walks that also missed the L2 uTLB. Subset of DATA_PAGE_WALK event", .code = 0x3a, .cntmsk = 0x3, .modmsk = INTEL_V3_ATTRS, }, { .name = "MEMORY_ACCESSES_IN_BOTH_PIPES", .desc = "Number of data memory reads or writes that are paired in both pipes of the pipeline", .code = 0x9, .cntmsk = 0x3, .modmsk = INTEL_V3_ATTRS, }, { .name = "MICROCODE_CYCLES", .desc = "The number of cycles microcode is executing. While microcode is executing, all other threads are stalled.", .code = 0x2c, .cntmsk = 0x3, .modmsk = INTEL_V3_ATTRS, }, { .name = "PIPELINE_AGI_STALLS", .desc = "Number of address generation interlock (AGI) stalls. An AGI occurring in both the U- and V- pipelines in the same clock signals this event twice.", .code = 0x1f, .cntmsk = 0x3, .modmsk = INTEL_V3_ATTRS, }, { .name = "PIPELINE_FLUSHES", .desc = "Number of pipeline flushes that occur. Pipeline flushes are caused by BTB misses on taken branches, mispredictions, exceptions, interrupts, and some segment descriptor loads.", .code = 0x15, .cntmsk = 0x3, .modmsk = INTEL_V3_ATTRS, }, { .name = "PIPELINE_SG_AGI_STALLS", .desc = "Number of address generation interlock (AGI) stalls due to vscatter* and vgather* instructions.", .code = 0x21, .cntmsk = 0x3, .modmsk = INTEL_V3_ATTRS, }, { .name = "SNP_HITM_BUNIT", .desc = "Snoop HITM in BUNIT", .code = 0x10e3, .cntmsk = 0x1, .modmsk = INTEL_V3_ATTRS, }, { .name = "SNP_HITM_L2", .desc = "Snoop HITM in L2", .code = 0x10e7, .cntmsk = 0x1, .modmsk = INTEL_V3_ATTRS, }, { .name = "SNP_HIT_L2", .desc = "Snoop HIT in L2", .code = 0x10e6, .cntmsk = 0x1, .modmsk = INTEL_V3_ATTRS, }, { .name = "VPU_DATA_READ", .desc = "Number of read transactions that were issued. In general each read transaction will read 1 64B cacheline. If there are alignment issues, then reads against multiple cache lines will each be counted individually.", .code = 0x2000, .cntmsk = 0x3, .modmsk = INTEL_V3_ATTRS, }, { .name = "VPU_DATA_READ_MISS", .desc = "VPU L1 data cache readmiss. Counts the number of occurrences.", .code = 0x2003, .cntmsk = 0x3, .modmsk = INTEL_V3_ATTRS, }, { .name = "VPU_DATA_WRITE", .desc = "Number of write transactions that were issued. . In general each write transaction will write 1 64B cacheline. If there are alignment issues, then write against multiple cache lines will each be counted individually.", .code = 0x2001, .cntmsk = 0x3, .modmsk = INTEL_V3_ATTRS, }, { .name = "VPU_DATA_WRITE_MISS", .desc = "VPU L1 data cache write miss. Counts the number of occurrences.", .code = 0x2004, .cntmsk = 0x3, .modmsk = INTEL_V3_ATTRS, }, { .name = "VPU_ELEMENTS_ACTIVE", .desc = "Counts the cumulative number of elements active (via mask) for VPU instructions issued.", .code = 0x2018, .cntmsk = 0x3, .modmsk = INTEL_V3_ATTRS, }, { .name = "VPU_INSTRUCTIONS_EXECUTED", .desc = "Counts the number of VPU instructions executed in both u- and v-pipes.", .code = 0x2016, .cntmsk = 0x3, .modmsk = INTEL_V3_ATTRS, }, { .name = "VPU_INSTRUCTIONS_EXECUTED_V_PIPE", .desc = "Counts the number of VPU instructions that paired and executed in the v-pipe.", .code = 0x2017, .cntmsk = 0x3, .modmsk = INTEL_V3_ATTRS, }, { .name = "VPU_STALL_REG", .desc = "VPU stall on Register Dependency. Counts the number of occurrences. Dependencies will include RAW, WAW, WAR.", .code = 0x2005, .cntmsk = 0x3, .modmsk = INTEL_V3_ATTRS, }, }; libpfm-4.9.0/lib/events/intel_slm_events.h0000664000175000017500000007340113223402656020420 0ustar eranianeranian/* * Copyright (c) 2013 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * PMU: slm (Intel Silvermont) */ static const intel_x86_umask_t slm_icache[]={ { .uname = "ACCESSES", .udesc = "Instruction fetches, including uncacheacble fetches", .ucode = 0x300, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "MISSES", .udesc = "Count all instructions fetches that miss the icache or produce memory requests. This includes uncacheache fetches. Any instruction fetch miss is counted only once and not once for every cycle it is outstanding", .ucode = 0x200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "HIT", .udesc = "Count all instructions fetches from the instruction cache", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t slm_uops_retired[]={ { .uname = "ANY", .udesc = "Micro-ops retired", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "MS", .udesc = "Micro-ops retired that were supplied fro MSROM", .ucode = 0x0100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "STALLED_CYCLES", .udesc = "Cycles no micro-ops retired", .ucode = 0x1000 | INTEL_X86_MOD_INV | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_I | _INTEL_X86_ATTR_C, }, { .uname = "STALLS", .udesc = "Periods no micro-ops retired", .ucode = 0x1000 | INTEL_X86_MOD_EDGE | INTEL_X86_MOD_INV | (0x1 << INTEL_X86_CMASK_BIT), .uflags= INTEL_X86_NCOMBO, .modhw = _INTEL_X86_ATTR_I | _INTEL_X86_ATTR_C | _INTEL_X86_ATTR_E, }, }; static const intel_x86_umask_t slm_inst_retired[]={ { .uname = "ANY_P", .udesc = "Instructions retired using generic counter (precise event)", .ucode = 0x0, .uflags= INTEL_X86_PEBS | INTEL_X86_DFL, }, { .uname = "ANY", .udesc = "Instructions retired using generic counter (precise event)", .uequiv = "ANY_P", .ucode = 0x0, .uflags= INTEL_X86_PEBS, }, }; static const intel_x86_umask_t slm_l2_reject_xq[]={ { .uname = "ALL", .udesc = "Number of demand and prefetch transactions that the L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the IDI link. The XQ may reject transactions from the L2Q (non-cacheable requests), BBS (L2 misses) and WOB (L2 write-back victims)", .ucode = 0x000, .uflags= INTEL_X86_DFL, }, }; static const intel_x86_umask_t slm_machine_clears[]={ { .uname = "SMC", .udesc = "Self-Modifying Code detected", .ucode = 0x100, .uflags= INTEL_X86_DFL, }, { .uname = "MEMORY_ORDERING", .udesc = "Number of stalled cycles due to memory ordering", .ucode = 0x200, }, { .uname = "FP_ASSIST", .udesc = "Number of stalled cycle due to FPU assist", .ucode = 0x400, }, { .uname = "ALL", .udesc = "Count any the machine clears", .ucode = 0x800, }, { .uname = "ANY", .udesc = "Count any the machine clears", .uequiv = "ALL", .ucode = 0x800, }, }; static const intel_x86_umask_t slm_br_inst_retired[]={ { .uname = "ANY", .udesc = "Any retired branch instruction (Precise Event)", .ucode = 0x0, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL | INTEL_X86_PEBS, }, { .uname = "ALL_BRANCHES", .udesc = "Any Retired branch instruction (Precise Event)", .uequiv = "ANY", .ucode = 0x0, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "ALL_TAKEN_BRANCHES", .udesc = "Retired branch instructions (Precise Event)", .ucode = 0x8000, .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, .grpid = 0, .ucntmsk = 0xfull, }, { .uname = "JCC", .udesc = "JCC instructions retired (Precise Event)", .ucode = 0x7e00, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "TAKEN_JCC", .udesc = "Taken JCC instructions retired (Precise Event)", .ucode = 0xfe00, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "CALL", .udesc = "Near call instructions retired (Precise Event)", .ucode = 0xf900, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "REL_CALL", .udesc = "Near relative call instructions retired (Precise Event)", .ucode = 0xfd00, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "IND_CALL", .udesc = "Near indirect call instructions retired (Precise Event)", .ucode = 0xfb00, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "RETURN", .udesc = "Near ret instructions retired (Precise Event)", .ucode = 0xf700, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "NON_RETURN_IND", .udesc = "Number of near indirect jmp and near indirect call instructions retired (Precise Event)", .ucode = 0xeb00, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "FAR_BRANCH", .udesc = "Far branch instructions retired (Precise Event)", .uequiv = "FAR", .ucode = 0xbf00, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "FAR", .udesc = "Far branch instructions retired (Precise Event)", .ucode = 0xbf00, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, }; static const intel_x86_umask_t slm_baclears[]={ { .uname = "ANY", .udesc = "BACLEARS asserted", .uequiv = "ALL", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ALL", .udesc = "BACLEARS asserted", .ucode = 0x100, .uflags= INTEL_X86_DFL | INTEL_X86_NCOMBO, }, { .uname = "RETURN", .udesc = "Number of baclears for return branches", .ucode = 0x800, .uflags= INTEL_X86_NCOMBO, }, { .uname = "COND", .udesc = "Number of baclears for conditional branches", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t slm_cpu_clk_unhalted[]={ { .uname = "CORE_P", .udesc = "Core cycles when core is not halted", .ucode = 0x0, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "BUS", .udesc = "Bus cycles when core is not halted. This event can give a measurement of the elapsed time. This events has a constant ratio with CPU_CLK_UNHALTED:REF event, which is the maximum bus to processor frequency ratio", .uequiv = "REF", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "REF", .udesc = "Number of reference cycles that the core is not in a halted state. The core enters the halted state when it is running the HLT instruction. In mobile systems, the core frequency may change from time to time. This event is not affected by core frequency changes but counts as if the core is running a the same maximum frequency all the time", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t slm_mem_uop_retired[]={ { .uname = "LD_DCU_MISS", .udesc = "Number of load uops retired that miss in L1 data cache. Note that prefetch misses will not be counted", .ucode = 0x100, }, { .uname = "LD_L2_HIT", .udesc = "Number of load uops retired that hit L2 (Precise Event)", .ucode = 0x200, .uflags= INTEL_X86_PEBS, }, { .uname = "LD_L2_MISS", .udesc = "Number of load uops retired that missed L2 (Precise Event)", .ucode = 0x400, .uflags= INTEL_X86_PEBS, }, { .uname = "LD_DTLB_MISS", .udesc = "Number of load uops retired that had a DTLB miss (Precise Event)", .ucode = 0x800, .uflags= INTEL_X86_PEBS, }, { .uname = "LD_UTLB_MISS", .udesc = "Number of load uops retired that had a UTLB miss", .ucode = 0x1000, }, { .uname = "HITM", .udesc = "Number of load uops retired that got data from the other core or from the other module and the line was modified (Precise Event)", .ucode = 0x2000, .uflags= INTEL_X86_PEBS, }, { .uname = "ANY_LD", .udesc = "Number of load uops retired", .ucode = 0x4000, }, { .uname = "ANY_ST", .udesc = "Number of store uops retired", .ucode = 0x8000, }, }; static const intel_x86_umask_t slm_llc_rqsts[]={ { .uname = "MISS", .udesc = "Number of L2 cache misses", .ucode = 0x4100, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ANY", .udesc = "Number of L2 cache references", .ucode = 0x4f00, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t slm_rehabq[]={ { .uname = "LD_BLOCK_ST_FORWARD", .udesc = "Number of retired loads that were prohibited from receiving forwarded data from the store because of address mismatch (Precise Event)", .ucode = 0x0100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "LD_BLOCK_STD_NOTREADY", .udesc = "Number of times forward was technically possible but did not occur because the store data was not available at the right time", .ucode = 0x0200, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ST_SPLITS", .udesc = "Number of retired stores that experienced cache line boundary splits", .ucode = 0x0400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "LD_SPLITS", .udesc = "Number of retired loads that experienced cache line boundary splits (Precise Event)", .ucode = 0x0800, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "LOCK", .udesc = "Number of retired memory operations with lock semantics. These are either implicit locked instructions such as XCHG or instructions with an explicit LOCK prefix", .ucode = 0x1000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "STA_FULL", .udesc = "Number of retired stores that are delayed because there is not a store address buffer available", .ucode = 0x2000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ANY_LD", .udesc = "Number of load uops reissued from RehabQ", .ucode = 0x4000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ANY_ST", .udesc = "Number of store uops reissued from RehabQ", .ucode = 0x8000, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t slm_offcore_response[]={ { .uname = "DMND_DATA_RD", .udesc = "Request: number of demand and DCU prefetch data reads of full and partial cachelines as well as demand data page table entry cacheline reads. Does not count L2 data read prefetches or instruction fetches", .ucode = 1ULL << (0 + 8), .grpid = 0, }, { .uname = "DMND_RFO", .udesc = "Request: number of demand and DCU prefetch reads for ownership (RFO) requests generated by a write to data cacheline. Does not count L2 RFO prefetches", .ucode = 1ULL << (1 + 8), .grpid = 0, }, { .uname = "DMND_IFETCH", .udesc = "Request: number of demand and DCU prefetch instruction cacheline reads. Does not count L2 code read prefetches", .ucode = 1ULL << (2 + 8), .grpid = 0, }, { .uname = "WB", .udesc = "Request: number of writebacks (modified to exclusive) transactions", .ucode = 1ULL << (3 + 8), .grpid = 0, }, { .uname = "PF_L2_DATA_RD", .udesc = "Request: number of data cacheline reads generated by L2 prefetchers", .ucode = 1ULL << (4 + 8), .grpid = 0, }, { .uname = "PF_RFO", .udesc = "Request: number of RFO requests generated by L2 prefetchers", .ucode = 1ULL << (5 + 8), .grpid = 0, }, { .uname = "PF_IFETCH", .udesc = "Request: number of code reads generated by L2 prefetchers", .ucode = 1ULL << (6 + 8), .grpid = 0, }, { .uname = "PARTIAL_READ", .udesc = "Request: number of demand reads of partial cachelines (including UC, WC)", .ucode = 1ULL << (7 + 8), .grpid = 0, }, { .uname = "PARTIAL_WRITE", .udesc = "Request: number of demand RFO requests to write to partial cache lines (includes UC, WT, WP)", .ucode = 1ULL << (8 + 8), .grpid = 0, }, { .uname = "UC_IFETCH", .udesc = "Request: number of UC instruction fetches", .ucode = 1ULL << (9 + 8), .grpid = 0, }, { .uname = "BUS_LOCKS", .udesc = "Request: number bus lock and split lock requests", .ucode = 1ULL << (10 + 8), .grpid = 0, }, { .uname = "STRM_ST", .udesc = "Request: number of streaming store requests", .ucode = 1ULL << (11 + 8), .grpid = 0, }, { .uname = "SW_PREFETCH", .udesc = "Request: number of software prefetch requests", .ucode = 1ULL << (12 + 8), .grpid = 0, }, { .uname = "PF_L1_DATA_RD", .udesc = "Request: number of data cacheline reads generated by L1 prefetchers", .ucode = 1ULL << (13 + 8), .grpid = 0, }, { .uname = "PARTIAL_STRM_ST", .udesc = "Request: number of partial streaming store requests", .ucode = 1ULL << (14 + 8), .grpid = 0, }, { .uname = "OTHER", .udesc = "Request: counts one any other request that crosses IDI, including I/O", .ucode = 1ULL << (15+8), .grpid = 0, }, { .uname = "ANY_IFETCH", .udesc = "Request: combination of PF_IFETCH | DMND_IFETCH | UC_IFETCH", .uequiv = "PF_IFETCH:DMND_IFETCH:UC_IFETCH", .ucode = (1ULL << 6 | 1ULL << 2 | 1ULL << 9) << 8, .grpid = 0, }, { .uname = "ANY_REQUEST", .udesc = "Request: combination of all request umasks", .uequiv = "DMND_DATA_RD:DMND_RFO:DMND_IFETCH:WB:PF_L2_DATA_RD:PF_RFO:PF_IFETCH:PARTIAL_READ:PARTIAL_WRITE:UC_IFETCH:BUS_LOCKS:STRM_ST:SW_PREFETCH:PF_L1_DATA_RD:PARTIAL_STRM_ST:OTHER", .ucode = 0xffff00, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, .grpid = 0, }, { .uname = "ANY_DATA", .udesc = "Request: combination of DMND_DATA | PF_L1_DATA_RD | PF_L2_DATA_RD", .uequiv = "DMND_DATA_RD:PF_L1_DATA_RD:PF_L2_DATA_RD", .ucode = (1ULL << 0 | 1ULL << 4 | 1ULL << 13) << 8, .grpid = 0, }, { .uname = "ANY_RFO", .udesc = "Request: combination of DMND_RFO | PF_RFO", .uequiv = "DMND_RFO:PF_RFO", .ucode = (1ULL << 1 | 1ULL << 5) << 8, .grpid = 0, }, { .uname = "ANY_RESPONSE", .udesc = "Response: count any response type", .ucode = 1ULL << (16+8), .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL | INTEL_X86_EXCL_GRP_GT, .grpid = 1, }, { .uname = "L2_HIT", .udesc = "Supplier: counts L2 hits in M/E/S states", .ucode = 1ULL << (18+8), .grpid = 1, }, { .uname = "SNP_NONE", .udesc = "Snoop: counts number of times no snoop-related information is available", .ucode = 1ULL << (31+8), .grpid = 2, }, { .uname = "SNP_MISS", .udesc = "Snoop: counts number of times a snoop was needed and it missed all snooped caches", .ucode = 1ULL << (33+8), .grpid = 2, }, { .uname = "SNP_HIT", .udesc = "Snoop: counts number of times a snoop hits in the other module where no modified copies were found in the L1 cache of the other core", .ucode = 1ULL << (34+8), .grpid = 2, }, { .uname = "SNP_HITM", .udesc = "Snoop: counts number of times a snoop hits in the other module where modified copies were found in the L1 cache of the other core", .ucode = 1ULL << (36+8), .grpid = 2, }, { .uname = "NON_DRAM", .udesc = "Snoop: counts number of times target was a non-DRAM system address. This includes MMIO transactions", .ucode = 1ULL << (37+8), .grpid = 2, }, { .uname = "SNP_ANY", .udesc = "Snoop: any snoop reason", .ucode = 0x7dULL << (31+8), .uequiv = "SNP_NONE:SNP_MISS:SNP_HIT:SNP_HITM:NON_DRAM", .uflags= INTEL_X86_DFL, .grpid = 2, }, }; static const intel_x86_umask_t slm_br_misp_retired[]={ { .uname = "ALL_BRANCHES", .udesc = "All mispredicted branches (Precise Event)", .uequiv = "ANY", .ucode = 0x0000, /* architectural encoding */ .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "ANY", .udesc = "All mispredicted branches (Precise Event)", .ucode = 0x0000, /* architectural encoding */ .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS | INTEL_X86_DFL, }, { .uname = "JCC", .udesc = "Number of mispredicted conditional branch instructions retired (Precise Event)", .ucode = 0x7e00, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "NON_RETURN_IND", .udesc = "Number of mispredicted non-return branch instructions retired (Precise Event)", .ucode = 0xeb00, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "RETURN", .udesc = "Number of mispredicted return branch instructions retired (Precise Event)", .ucode = 0xf700, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "IND_CALL", .udesc = "Number of mispredicted indirect call branch instructions retired (Precise Event)", .ucode = 0xfb00, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, { .uname = "TAKEN_JCC", .udesc = "Number of mispredicted taken conditional branch instructions retired (Precise Event)", .ucode = 0xfe00, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, }, }; static const intel_x86_umask_t slm_no_alloc_cycles[]={ { .uname = "ANY", .udesc = "Number of cycles when the front-end does not provide any instructions to be allocated for any reason", .ucode = 0x3f00, .uequiv = "ALL", .uflags = INTEL_X86_NCOMBO, }, { .uname = "ALL", .udesc = "Number of cycles when the front-end does not provide any instructions to be allocated for any reason", .ucode = 0x3f00, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "NOT_DELIVERED", .udesc = "Number of cycles when the front-end does not provide any instructions to be allocated but the back-end is not stalled", .ucode = 0x5000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "MISPREDICTS", .udesc = "Number of cycles when no uops are allocated and the alloc pipe is stalled waiting for a mispredicted jump to retire", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, }, { .uname = "RAT_STALL", .udesc = "Number of cycles when no uops are allocated and a RAT stall is asserted", .ucode = 0x2000, .uflags= INTEL_X86_NCOMBO, }, { .uname = "ROB_FULL", .udesc = "Number of cycles when no uops are allocated and the ROB is full (less than 2 entries available)", .ucode = 0x0100, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t slm_rs_full_stall[]={ { .uname = "MEC", .udesc = "Number of cycles when the allocation pipeline is stalled due to the RS for the MEC cluster is full", .ucode = 0x0100, }, { .uname = "ALL", .udesc = "Number of cycles when the allocation pipeline is stalled due any one of the RS being full", .ucode = 0x1f00, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "ANY", .udesc = "Number of cycles when the allocation pipeline is stalled due any one of the RS being full", .ucode = 0x1f00, .uequiv = "ALL", .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t slm_cycles_div_busy[]={ { .uname = "ANY", .udesc = "Number of cycles the divider is busy", .ucode = 0x0100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t slm_ms_decoded[]={ { .uname = "ENTRY", .udesc = "Number of times the MSROM starts a flow of uops", .ucode = 0x0100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t slm_decode_restriction[]={ { .uname = "PREDECODE_WRONG", .udesc = "Number of times the prediction (from the predecode cache) for instruction length is incorrect", .ucode = 0x0100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t slm_fetch_stall[]={ { .uname = "ICACHE_FILL_PENDING_CYCLES", .udesc = "Number of cycles the NIP stalls because of an icache miss. This is a cumulative count of cycles the NIP stalled for all icache misses", .ucode = 0x0400, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t slm_core_reject_l2q[]={ { .uname = "ALL", .udesc = "Number of requests that were not accepted into the L2Q because the L2Q was FULL", .ucode = 0x0000, .uflags = INTEL_X86_DFL, }, }; static const intel_x86_umask_t slm_page_walks[]={ { .uname = "CYCLES", .udesc = "Total cycles for all the page walks. (I-side and D-side)", .ucode = 0x0300, .uflags= INTEL_X86_NCOMBO, }, { .uname = "WALKS", .udesc = "Total number of page walks. (I-side and D-side)", .ucode = 0x0300 | INTEL_X86_MOD_EDGE, .uequiv = "D_SIDE_WALKS:I_SIDE_WALKS", .uflags = INTEL_X86_NCOMBO, }, { .uname = "D_SIDE_CYCLES", .udesc = "Number of cycles when a D-side page walk is in progress", .ucode = 0x0100, }, { .uname = "D_SIDE_WALKS", .udesc = "Number of D-side page walks", .ucode = 0x0100 | INTEL_X86_MOD_EDGE, .uequiv = "D_SIDE_CYCLES:e", }, { .uname = "I_SIDE_CYCLES", .udesc = "Number of cycles when a I-side page walk is in progress", .ucode = 0x0200, }, { .uname = "I_SIDE_WALKS", .udesc = "Number of I-side page walks", .ucode = 0x0200 | INTEL_X86_MOD_EDGE, .uequiv = "I_SIDE_CYCLES:e", }, }; static const intel_x86_entry_t intel_slm_pe[]={ { .name = "UNHALTED_CORE_CYCLES", .desc = "Unhalted core cycles", .modmsk = INTEL_V2_ATTRS, .cntmsk = 0x200000003ull, .code = 0x3c, }, { .name = "UNHALTED_REFERENCE_CYCLES", .desc = "Unhalted reference cycle", .modmsk = INTEL_FIXED3_ATTRS, .cntmsk = 0x400000000ull, .code = 0x0300, /* pseudo encoding */ .flags = INTEL_X86_FIXED, }, { .name = "INSTRUCTION_RETIRED", .desc = "Instructions retired", .modmsk = INTEL_V2_ATTRS, .cntmsk = 0x100000003ull, .code = 0xc0, }, { .name = "INSTRUCTIONS_RETIRED", .desc = "This is an alias for INSTRUCTION_RETIRED", .modmsk = INTEL_V2_ATTRS, .equiv = "INSTRUCTION_RETIRED", .cntmsk = 0x10003, .code = 0xc0, }, { .name = "LLC_REFERENCES", .desc = "Last level of cache references", .modmsk = INTEL_V2_ATTRS, .cntmsk = 0x3, .code = 0x4f2e, }, { .name = "LAST_LEVEL_CACHE_REFERENCES", .desc = "This is an alias for LLC_REFERENCES", .modmsk = INTEL_V2_ATTRS, .equiv = "LLC_REFERENCES", .cntmsk = 0x3, .code = 0x4f2e, }, { .name = "LLC_MISSES", .desc = "Last level of cache misses", .modmsk = INTEL_V2_ATTRS, .cntmsk = 0x3, .code = 0x412e, }, { .name = "LAST_LEVEL_CACHE_MISSES", .desc = "This is an alias for LLC_MISSES", .modmsk = INTEL_V2_ATTRS, .equiv = "LLC_MISSES", .cntmsk = 0x3, .code = 0x412e, }, { .name = "BRANCH_INSTRUCTIONS_RETIRED", .desc = "Branch instructions retired", .modmsk = INTEL_V2_ATTRS, .equiv = "BR_INST_RETIRED:ANY", .cntmsk = 0x3, .code = 0xc4, }, { .name = "MISPREDICTED_BRANCH_RETIRED", .desc = "Mispredicted branch instruction retired", .equiv = "BR_MISP_RETIRED", .modmsk = INTEL_V2_ATTRS, .cntmsk = 0x3, .code = 0xc5, .flags= INTEL_X86_PEBS, }, /* begin model specific events */ { .name = "DECODE_RESTRICTION", .desc = "Instruction length prediction delay", .modmsk = INTEL_V2_ATTRS, .cntmsk = 0x3, .code = 0xe9, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(slm_decode_restriction), .umasks = slm_decode_restriction, }, { .name = "L2_REJECT_XQ", .desc = "Rejected L2 requests to XQ", .modmsk = INTEL_V2_ATTRS, .cntmsk = 0x3, .code = 0x30, .numasks = LIBPFM_ARRAY_SIZE(slm_l2_reject_xq), .ngrp = 1, .umasks = slm_l2_reject_xq, }, { .name = "ICACHE", .desc = "Instruction fetches", .modmsk = INTEL_V2_ATTRS, .cntmsk = 0x3, .code = 0x80, .numasks = LIBPFM_ARRAY_SIZE(slm_icache), .ngrp = 1, .umasks = slm_icache, }, { .name = "UOPS_RETIRED", .desc = "Micro-ops retired", .modmsk = INTEL_V2_ATTRS, .cntmsk = 0x3, .code = 0xc2, .numasks = LIBPFM_ARRAY_SIZE(slm_uops_retired), .ngrp = 1, .umasks = slm_uops_retired, }, { .name = "INST_RETIRED", .desc = "Instructions retired", .modmsk = INTEL_V2_ATTRS, .cntmsk = 0x3, .code = 0xc0, .flags= INTEL_X86_PEBS, .numasks = LIBPFM_ARRAY_SIZE(slm_inst_retired), .ngrp = 1, .umasks = slm_inst_retired, }, { .name = "CYCLES_DIV_BUSY", .desc = "Cycles the divider is busy", .modmsk = INTEL_V2_ATTRS, .cntmsk = 0x3, .code = 0xcd, .numasks = LIBPFM_ARRAY_SIZE(slm_cycles_div_busy), .ngrp = 1, .umasks = slm_cycles_div_busy, }, { .name = "RS_FULL_STALL", .desc = "RS full", .modmsk = INTEL_V2_ATTRS, .cntmsk = 0x3, .code = 0xcb, .numasks = LIBPFM_ARRAY_SIZE(slm_rs_full_stall), .ngrp = 1, .umasks = slm_rs_full_stall, }, { .name = "LLC_RQSTS", .desc = "L2 cache requests", .modmsk = INTEL_V2_ATTRS, .cntmsk = 0x3, .code = 0x2e, .numasks = LIBPFM_ARRAY_SIZE(slm_llc_rqsts), .ngrp = 1, .umasks = slm_llc_rqsts, }, { .name = "MACHINE_CLEARS", .desc = "Self-Modifying Code detected", .modmsk = INTEL_V2_ATTRS, .cntmsk = 0x3, .code = 0xc3, .numasks = LIBPFM_ARRAY_SIZE(slm_machine_clears), .ngrp = 1, .umasks = slm_machine_clears, }, { .name = "BR_INST_RETIRED", .desc = "Retired branch instructions", .modmsk = INTEL_V2_ATTRS, .cntmsk = 0x3, .code = 0xc4, .numasks = LIBPFM_ARRAY_SIZE(slm_br_inst_retired), .flags= INTEL_X86_PEBS, .ngrp = 1, .umasks = slm_br_inst_retired, }, { .name = "BR_MISP_RETIRED", .desc = "Mispredicted retired branch instructions (Precise Event)", .modmsk = INTEL_V2_ATTRS, .cntmsk = 0x3, .code = 0xc5, .flags= INTEL_X86_PEBS, .numasks = LIBPFM_ARRAY_SIZE(slm_br_misp_retired), .ngrp = 1, .umasks = slm_br_misp_retired, }, { .name = "BR_MISP_INST_RETIRED", /* for backward compatibility with older version */ .desc = "Mispredicted retired branch instructions (Precise Event)", .modmsk = INTEL_V2_ATTRS, .equiv = "BR_MISP_RETIRED", .cntmsk = 0x3, .code = 0xc5, .flags= INTEL_X86_PEBS, .numasks = LIBPFM_ARRAY_SIZE(slm_br_misp_retired), .ngrp = 1, .umasks = slm_br_misp_retired, }, { .name = "MS_DECODED", .desc = "MS decoder", .modmsk = INTEL_V2_ATTRS, .cntmsk = 0x3, .code = 0xe7, .numasks = LIBPFM_ARRAY_SIZE(slm_ms_decoded), .ngrp = 1, .umasks = slm_ms_decoded, }, { .name = "BACLEARS", .desc = "Branch address calculator", .modmsk = INTEL_V2_ATTRS, .cntmsk = 0x3, .code = 0xe6, .numasks = LIBPFM_ARRAY_SIZE(slm_baclears), .ngrp = 1, .umasks = slm_baclears, }, { .name = "NO_ALLOC_CYCLES", .desc = "Front-end allocation", .modmsk = INTEL_V2_ATTRS, .cntmsk = 0x3, .code = 0xca, .numasks = LIBPFM_ARRAY_SIZE(slm_no_alloc_cycles), .ngrp = 1, .umasks = slm_no_alloc_cycles, }, { .name = "CPU_CLK_UNHALTED", .desc = "Core cycles when core is not halted", .modmsk = INTEL_V2_ATTRS, .cntmsk = 0x3, .code = 0x3c, .numasks = LIBPFM_ARRAY_SIZE(slm_cpu_clk_unhalted), .ngrp = 1, .umasks = slm_cpu_clk_unhalted, }, { .name = "MEM_UOP_RETIRED", .desc = "Retired loads micro-ops", .modmsk = INTEL_V2_ATTRS, .cntmsk = 0x3, .code = 0x4, .flags= INTEL_X86_PEBS, .numasks = LIBPFM_ARRAY_SIZE(slm_mem_uop_retired), .ngrp = 1, .umasks = slm_mem_uop_retired, }, { .name = "CORE_REJECT_L2Q", .desc = "Demand and L1 prefetcher requests rejected by L2", .modmsk = INTEL_V2_ATTRS, .cntmsk = 0x3, .code = 0x31, .numasks = LIBPFM_ARRAY_SIZE(slm_core_reject_l2q), .ngrp = 1, .umasks = slm_core_reject_l2q, }, { .name = "REHABQ", .desc = "Memory reference queue", .modmsk = INTEL_V2_ATTRS, .cntmsk = 0x3, .code = 0x03, .flags= INTEL_X86_PEBS, .numasks = LIBPFM_ARRAY_SIZE(slm_rehabq), .ngrp = 1, .umasks = slm_rehabq, }, { .name = "FETCH_STALL", .desc = "Fetch stalls", .modmsk = INTEL_V2_ATTRS, .cntmsk = 0x3, .code = 0x86, .numasks = LIBPFM_ARRAY_SIZE(slm_fetch_stall), .ngrp = 1, .umasks = slm_fetch_stall, }, { .name = "PAGE_WALKS", .desc = "Page walker", .modmsk = INTEL_V2_ATTRS, .cntmsk = 0x3, .code = 0x5, .numasks = LIBPFM_ARRAY_SIZE(slm_page_walks), .ngrp = 1, .umasks = slm_page_walks, }, { .name = "OFFCORE_RESPONSE_0", .desc = "Offcore response event (must provide at least one request type and either any_response or any combination of supplier + snoop)", .modmsk = INTEL_V2_ATTRS, .cntmsk = 0xf, .code = 0x01b7, .flags= INTEL_X86_NHM_OFFCORE, .numasks = LIBPFM_ARRAY_SIZE(slm_offcore_response), .ngrp = 3, .umasks = slm_offcore_response, }, { .name = "OFFCORE_RESPONSE_1", .desc = "Offcore response event (must provide at least one request type and either any_response or any combination of supplier + snoop)", .modmsk = INTEL_V2_ATTRS, .cntmsk = 0xf, .code = 0x02b7, .flags= INTEL_X86_NHM_OFFCORE, .numasks = LIBPFM_ARRAY_SIZE(slm_offcore_response), .ngrp = 3, .umasks = slm_offcore_response, /* identical to actual umasks list for this event */ }, }; libpfm-4.9.0/lib/events/intel_knl_unc_edc_events.h0000664000175000017500000000551613223402656022073 0ustar eranianeranian/* * Copyright (c) 2016 Intel Corp. All rights reserved * Contributed by Peinan Zhang * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * PMU: knl_unc_edc (Intel Knights Landing EDC_UCLK, EDC_ECLK uncore PMUs) */ static const intel_x86_umask_t knl_unc_edc_uclk_access_count[]={ { .uname = "HIT_CLEAN", .udesc = "Hit E", .ucode = 0x0100, }, { .uname = "HIT_DIRTY", .udesc = "Hit M", .ucode = 0x0200, }, { .uname = "MISS_CLEAN", .udesc = "Miss E", .ucode = 0x0400, }, { .uname = "MISS_DIRTY", .udesc = "Miss M", .ucode = 0x0800, }, { .uname = "MISS_INVALID", .udesc = "Miss I", .ucode = 0x1000, }, { .uname = "MISS_GARBAGE", .udesc = "Miss G", .ucode = 0x2000, }, }; static const intel_x86_entry_t intel_knl_unc_edc_uclk_pe[]={ { .name = "UNC_E_U_CLOCKTICKS", .desc = "EDC UCLK clockticks (generic counters)", .code = 0x00, /*encoding for generic counters */ .cntmsk = 0xf, }, { .name = "UNC_E_EDC_ACCESS", .desc = "Number of EDC Access Hits or Misses.", .code = 0x02, .cntmsk = 0xf, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_edc_uclk_access_count), .umasks = knl_unc_edc_uclk_access_count }, }; static const intel_x86_entry_t intel_knl_unc_edc_eclk_pe[]={ { .name = "UNC_E_E_CLOCKTICKS", .desc = "EDC ECLK clockticks (generic counters)", .code = 0x00, /*encoding for generic counters */ .cntmsk = 0xf, }, { .name = "UNC_E_RPQ_INSERTS", .desc = "Counts total number of EDC RPQ insers", .code = 0x0101, .cntmsk = 0xf, }, { .name = "UNC_E_WPQ_INSERTS", .desc = "Counts total number of EDC WPQ insers", .code = 0x0102, .cntmsk = 0xf, }, }; libpfm-4.9.0/lib/events/intel_hswep_unc_imc_events.h0000664000175000017500000004721113223402656022450 0ustar eranianeranian/* * Copyright (c) 2014 Google Inc. All rights reserved * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * PMU: hswep_unc_imc (Intel Haswell-EP IMC uncore PMU) */ static const intel_x86_umask_t hswep_unc_m_cas_count[]={ { .uname = "ALL", .udesc = "Counts total number of DRAM CAS commands issued on this channel", .ucode = 0xf00, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "RD", .udesc = "Counts all DRAM reads on this channel, incl. underfills", .ucode = 0x300, .uflags = INTEL_X86_NCOMBO, }, { .uname = "RD_REG", .udesc = "Counts number of DRAM read CAS commands issued on this channel, incl. regular read CAS and those with implicit precharge", .ucode = 0x100, }, { .uname = "RD_UNDERFILL", .udesc = "Counts number of underfill reads issued by the memory controller", .ucode = 0x200, }, { .uname = "WR", .udesc = "Counts number of DRAM write CAS commands on this channel", .ucode = 0xc00, .uflags = INTEL_X86_NCOMBO, }, { .uname = "WR_RMM", .udesc = "Counts Number of opportunistic DRAM write CAS commands issued on this channel", .ucode = 0x800, }, { .uname = "WR_WMM", .udesc = "Counts number of DRAM write CAS commands issued on this channel while in Write-Major mode", .ucode = 0x400, }, { .uname = "RD_RMM", .udesc = "Counts Number of opportunistic DRAM read CAS commands issued on this channel", .ucode = 0x1000, }, { .uname = "RD_WMM", .udesc = "Counts number of DRAM read CAS commands issued on this channel while in Write-Major mode", .ucode = 0x2000, }, }; static const intel_x86_umask_t hswep_unc_m_dram_refresh[]={ { .uname = "HIGH", .udesc = "High", .ucode = 0x400, }, { .uname = "PANIC", .udesc = "Panic", .ucode = 0x200, }, }; static const intel_x86_umask_t hswep_unc_m_major_modes[]={ { .uname = "ISOCH", .udesc = "Counts cycles in ISOCH Major mode", .ucode = 0x800, }, { .uname = "PARTIAL", .udesc = "Counts cycles in Partial Major mode", .ucode = 0x400, }, { .uname = "READ", .udesc = "Counts cycles in Read Major mode", .ucode = 0x100, }, { .uname = "WRITE", .udesc = "Counts cycles in Write Major mode", .ucode = 0x200, }, }; static const intel_x86_umask_t hswep_unc_m_power_cke_cycles[]={ { .uname = "RANK0", .udesc = "Count cycles for rank 0", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "RANK1", .udesc = "Count cycles for rank 1", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "RANK2", .udesc = "Count cycles for rank 2", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "RANK3", .udesc = "Count cycles for rank 3", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "RANK4", .udesc = "Count cycles for rank 4", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "RANK5", .udesc = "Count cycles for rank 5", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "RANK6", .udesc = "Count cycles for rank 6", .ucode = 0x4000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "RANK7", .udesc = "Count cycles for rank 7", .ucode = 0x8000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t hswep_unc_m_preemption[]={ { .uname = "RD_PREEMPT_RD", .udesc = "Counts read over read preemptions", .ucode = 0x100, }, { .uname = "RD_PREEMPT_WR", .udesc = "Counts read over write preemptions", .ucode = 0x200, }, }; static const intel_x86_umask_t hswep_unc_m_pre_count[]={ { .uname = "PAGE_CLOSE", .udesc = "Counts number of DRAM precharge commands sent on this channel as a result of the page close counter expiring", .ucode = 0x200, }, { .uname = "PAGE_MISS", .udesc = "Counts number of DRAM precharge commands sent on this channel as a result of page misses", .ucode = 0x100, }, { .uname = "RD", .udesc = "Precharge due to read", .ucode = 0x400, }, { .uname = "WR", .udesc = "Precharge due to write", .ucode = 0x800, }, { .uname = "BYP", .udesc = "Precharge due to bypass", .ucode = 0x1000, }, }; static const intel_x86_umask_t hswep_unc_m_act_count[]={ { .uname = "RD", .udesc = "Activate due to read", .ucode = 0x100, }, { .uname = "WR", .udesc = "Activate due to write", .ucode = 0x200, }, { .uname = "BYP", .udesc = "Activate due to bypass", .ucode = 0x800, }, }; static const intel_x86_umask_t hswep_unc_m_byp_cmds[]={ { .uname = "ACT", .udesc = "ACT command issued by 2 cycle bypass", .ucode = 0x100, }, { .uname = "CAS", .udesc = "CAS command issued by 2 cycle bypass", .ucode = 0x200, }, { .uname = "PRE", .udesc = "PRE command issued by 2 cycle bypass", .ucode = 0x400, }, }; static const intel_x86_umask_t hswep_unc_m_rd_cas_prio[]={ { .uname = "LOW", .udesc = "Read CAS issued with low priority", .ucode = 0x100, }, { .uname = "MED", .udesc = "Read CAS issued with medium priority", .ucode = 0x200, }, { .uname = "HIGH", .udesc = "Read CAS issued with high priority", .ucode = 0x400, }, { .uname = "PANIC", .udesc = "Read CAS issued with panic non isoch priority (starved)", .ucode = 0x800, }, }; static const intel_x86_umask_t hswep_unc_m_rd_cas_rank0[]={ { .uname = "BANK0", .udesc = "Bank 0", .ucode = 0x0000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "BANK1", .udesc = "Bank 1", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "BANK2", .udesc = "Bank 2", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "BANK3", .udesc = "Bank 3", .ucode = 0x300, .uflags = INTEL_X86_NCOMBO, }, { .uname = "BANK4", .udesc = "Bank 4", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "BANK5", .udesc = "Bank 5", .ucode = 0x500, .uflags = INTEL_X86_NCOMBO, }, { .uname = "BANK6", .udesc = "Bank 6", .ucode = 0x600, .uflags = INTEL_X86_NCOMBO, }, { .uname = "BANK7", .udesc = "Bank 7", .ucode = 0x700, .uflags = INTEL_X86_NCOMBO, }, { .uname = "BANK8", .udesc = "Bank 8", .ucode = 0x0800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "BANK9", .udesc = "Bank 9", .ucode = 0x900, .uflags = INTEL_X86_NCOMBO, }, { .uname = "BANK10", .udesc = "Bank 10", .ucode = 0xa00, .uflags = INTEL_X86_NCOMBO, }, { .uname = "BANK11", .udesc = "Bank 11", .ucode = 0xb00, .uflags = INTEL_X86_NCOMBO, }, { .uname = "BANK12", .udesc = "Bank 12", .ucode = 0xc000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "BANK13", .udesc = "Bank 13", .ucode = 0xd000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "BANK14", .udesc = "Bank 14", .ucode = 0xe000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "BANK15", .udesc = "Bank 15", .ucode = 0xf000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ALLBANKS", .udesc = "Bank 15", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "BANKG0", .udesc = "Bank Group 0 (bank 0-3)", .ucode = 0x1100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "BANKG1", .udesc = "Bank Group 1 (bank 4-7)", .ucode = 0x12000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "BANKG2", .udesc = "Bank Group 2 (8-11)", .ucode = 0x13000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "BANKG3", .udesc = "Bank Group 3 (12-15)", .ucode = 0x14000, .uflags = INTEL_X86_NCOMBO, } }; static const intel_x86_umask_t hswep_unc_m_vmse_wr_push[]={ { .uname = "WMM", .udesc = "VMSE write push issued in WMM", .ucode = 0x100, }, { .uname = "RMM", .udesc = "VMSE write push issued in RMM", .ucode = 0x200, } }; static const intel_x86_umask_t hswep_unc_m_wmm_to_rmm[]={ { .uname = "LOW_THRES", .udesc = "Transition from WMM to RMM because of starve counter", .ucode = 0x100, }, { .uname = "STARVE", .udesc = "Starve", .ucode = 0x200, }, { .uname = "VMSE_RETRY", .udesc = "VMSE retry", .ucode = 0x400, } }; static const intel_x86_entry_t intel_hswep_unc_m_pe[]={ { .name = "UNC_M_CLOCKTICKS", .desc = "IMC Uncore clockticks (fixed counter)", .modmsk = 0x0, .cntmsk = 0x100000000ull, .code = 0xff, /* perf pseudo encoding for fixed counter */ .flags = INTEL_X86_FIXED, }, { .name = "UNC_M_DCLOCKTICKS", .desc = "IMC Uncore clockticks (generic counters)", .modmsk = HSWEP_UNC_IMC_ATTRS, .cntmsk = 0xf, .code = 0x00, /*encoding for generic counters */ }, { .name = "UNC_M_ACT_COUNT", .desc = "DRAM Activate Count", .code = 0x1, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_IMC_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_m_act_count), .umasks = hswep_unc_m_act_count }, { .name = "UNC_M_CAS_COUNT", .desc = "DRAM RD_CAS and WR_CAS Commands.", .code = 0x4, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_IMC_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_m_cas_count), .umasks = hswep_unc_m_cas_count }, { .name = "UNC_M_DRAM_PRE_ALL", .desc = "DRAM Precharge All Commands", .code = 0x6, .cntmsk = 0xf, .modmsk = HSWEP_UNC_IMC_ATTRS, }, { .name = "UNC_M_DRAM_REFRESH", .desc = "Number of DRAM Refreshes Issued", .code = 0x5, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_IMC_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_m_dram_refresh), .umasks = hswep_unc_m_dram_refresh }, { .name = "UNC_M_ECC_CORRECTABLE_ERRORS", .desc = "ECC Correctable Errors", .code = 0x9, .cntmsk = 0xf, .modmsk = HSWEP_UNC_IMC_ATTRS, }, { .name = "UNC_M_MAJOR_MODES", .desc = "Cycles in a Major Mode", .code = 0x7, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_IMC_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_m_major_modes), .umasks = hswep_unc_m_major_modes }, { .name = "UNC_M_POWER_CHANNEL_DLLOFF", .desc = "Channel DLLOFF Cycles", .code = 0x84, .cntmsk = 0xf, .modmsk = HSWEP_UNC_IMC_ATTRS, }, { .name = "UNC_M_POWER_CHANNEL_PPD", .desc = "Channel PPD Cycles", .code = 0x85, .cntmsk = 0xf, .modmsk = HSWEP_UNC_IMC_ATTRS, }, { .name = "UNC_M_POWER_CKE_CYCLES", .desc = "CKE_ON_CYCLES by Rank", .code = 0x83, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_IMC_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_m_power_cke_cycles), .umasks = hswep_unc_m_power_cke_cycles }, { .name = "UNC_M_POWER_CRITICAL_THROTTLE_CYCLES", .desc = "Critical Throttle Cycles", .code = 0x86, .cntmsk = 0xf, .modmsk = HSWEP_UNC_IMC_ATTRS, }, { .name = "UNC_M_POWER_SELF_REFRESH", .desc = "Clock-Enabled Self-Refresh", .code = 0x43, .cntmsk = 0xf, .modmsk = HSWEP_UNC_IMC_ATTRS, }, { .name = "UNC_M_POWER_THROTTLE_CYCLES", .desc = "Throttle Cycles", .code = 0x41, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_IMC_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_m_power_cke_cycles), .umasks = hswep_unc_m_power_cke_cycles /* identical to snbep_unc_m_power_cke_cycles */ }, { .name = "UNC_M_POWER_PCU_THROTTLING", .desc = "PCU throttling", .code = 0x42, .cntmsk = 0xf, .modmsk = HSWEP_UNC_IMC_ATTRS, }, { .name = "UNC_M_PREEMPTION", .desc = "Read Preemption Count", .code = 0x8, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_IMC_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_m_preemption), .umasks = hswep_unc_m_preemption }, { .name = "UNC_M_PRE_COUNT", .desc = "DRAM Precharge commands.", .code = 0x2, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_IMC_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_m_pre_count), .umasks = hswep_unc_m_pre_count }, { .name = "UNC_M_RPQ_CYCLES_NE", .desc = "Read Pending Queue Not Empty", .code = 0x11, .cntmsk = 0xf, .modmsk = HSWEP_UNC_IMC_ATTRS, }, { .name = "UNC_M_RPQ_INSERTS", .desc = "Read Pending Queue Allocations", .code = 0x10, .cntmsk = 0xf, .modmsk = HSWEP_UNC_IMC_ATTRS, }, { .name = "UNC_M_WPQ_CYCLES_FULL", .desc = "Write Pending Queue Full Cycles", .code = 0x22, .cntmsk = 0xf, .modmsk = HSWEP_UNC_IMC_ATTRS, }, { .name = "UNC_M_WPQ_CYCLES_NE", .desc = "Write Pending Queue Not Empty", .code = 0x21, .cntmsk = 0xf, .modmsk = HSWEP_UNC_IMC_ATTRS, }, { .name = "UNC_M_WPQ_READ_HIT", .desc = "Write Pending Queue CAM Match", .code = 0x23, .cntmsk = 0xf, .modmsk = HSWEP_UNC_IMC_ATTRS, }, { .name = "UNC_M_WPQ_WRITE_HIT", .desc = "Write Pending Queue CAM Match", .code = 0x24, .cntmsk = 0xf, .modmsk = HSWEP_UNC_IMC_ATTRS, }, { .name = "UNC_M_BYP_CMDS", .desc = "Bypass command event", .code = 0xa1, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_IMC_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_m_byp_cmds), .umasks = hswep_unc_m_byp_cmds }, { .name = "UNC_M_RD_CAS_PRIO", .desc = "Read CAS priority", .code = 0xa0, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_IMC_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_m_rd_cas_prio), .umasks = hswep_unc_m_rd_cas_prio }, { .name = "UNC_M_RD_CAS_RANK0", .desc = "Read CAS access to Rank 0", .code = 0xb0, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_IMC_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_m_rd_cas_rank0), .umasks = hswep_unc_m_rd_cas_rank0 }, { .name = "UNC_M_RD_CAS_RANK1", .desc = "Read CAS access to Rank 1", .code = 0xb1, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_IMC_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_m_rd_cas_rank0), /* shared */ .umasks = hswep_unc_m_rd_cas_rank0 }, { .name = "UNC_M_RD_CAS_RANK2", .desc = "Read CAS access to Rank 2", .code = 0xb2, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_IMC_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_m_rd_cas_rank0), /* shared */ .umasks = hswep_unc_m_rd_cas_rank0 }, { .name = "UNC_M_RD_CAS_RANK3", .desc = "Read CAS access to Rank 3", .code = 0xb3, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_IMC_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_m_rd_cas_rank0), /* shared */ .umasks = hswep_unc_m_rd_cas_rank0 }, { .name = "UNC_M_RD_CAS_RANK4", .desc = "Read CAS access to Rank 4", .code = 0xb4, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_IMC_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_m_rd_cas_rank0), /* shared */ .umasks = hswep_unc_m_rd_cas_rank0 }, { .name = "UNC_M_RD_CAS_RANK5", .desc = "Read CAS access to Rank 5", .code = 0xb5, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_IMC_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_m_rd_cas_rank0), /* shared */ .umasks = hswep_unc_m_rd_cas_rank0 }, { .name = "UNC_M_RD_CAS_RANK6", .desc = "Read CAS access to Rank 6", .code = 0xb6, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_IMC_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_m_rd_cas_rank0), /* shared */ .umasks = hswep_unc_m_rd_cas_rank0 }, { .name = "UNC_M_RD_CAS_RANK7", .desc = "Read CAS access to Rank 7", .code = 0xb7, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_IMC_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_m_rd_cas_rank0), /* shared */ .umasks = hswep_unc_m_rd_cas_rank0 }, { .name = "UNC_M_VMSE_MXB_WR_OCCUPANCY", .desc = "VMSE MXB write buffer occupancy", .code = 0x91, .cntmsk = 0xf, .modmsk = HSWEP_UNC_IMC_ATTRS, }, { .name = "UNC_M_VMSE_WR_PUSH", .desc = "VMSE WR push issued", .code = 0x90, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_IMC_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_m_vmse_wr_push), .umasks = hswep_unc_m_vmse_wr_push }, { .name = "UNC_M_WMM_TO_RMM", .desc = "Transitions from WMM to RMM because of low threshold", .code = 0xc0, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_IMC_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_m_wmm_to_rmm), .umasks = hswep_unc_m_wmm_to_rmm }, { .name = "UNC_M_WRONG_MM", .desc = "Not getting the requested major mode", .code = 0xc1, .cntmsk = 0xf, .modmsk = HSWEP_UNC_IMC_ATTRS, }, { .name = "UNC_M_WR_CAS_RANK0", .desc = "Write CAS access to Rank 0", .code = 0xb8, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_IMC_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_m_rd_cas_rank0), /* shared */ .umasks = hswep_unc_m_rd_cas_rank0 }, { .name = "UNC_M_WR_CAS_RANK1", .desc = "Write CAS access to Rank 1", .code = 0xb9, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_IMC_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_m_rd_cas_rank0), /* shared */ .umasks = hswep_unc_m_rd_cas_rank0 }, { .name = "UNC_M_WR_CAS_RANK2", .desc = "Write CAS access to Rank 2", .code = 0xba, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_IMC_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_m_rd_cas_rank0), /* shared */ .umasks = hswep_unc_m_rd_cas_rank0 }, { .name = "UNC_M_WR_CAS_RANK3", .desc = "Write CAS access to Rank 3", .code = 0xbb, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_IMC_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_m_rd_cas_rank0), /* shared */ .umasks = hswep_unc_m_rd_cas_rank0 }, { .name = "UNC_M_WR_CAS_RANK4", .desc = "Write CAS access to Rank 4", .code = 0xbc, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_IMC_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_m_rd_cas_rank0), /* shared */ .umasks = hswep_unc_m_rd_cas_rank0 }, { .name = "UNC_M_WR_CAS_RANK5", .desc = "Write CAS access to Rank 5", .code = 0xbd, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_IMC_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_m_rd_cas_rank0), /* shared */ .umasks = hswep_unc_m_rd_cas_rank0 }, { .name = "UNC_M_WR_CAS_RANK6", .desc = "Write CAS access to Rank 6", .code = 0xbe, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_IMC_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_m_rd_cas_rank0), /* shared */ .umasks = hswep_unc_m_rd_cas_rank0 }, { .name = "UNC_M_WR_CAS_RANK7", .desc = "Write CAS access to Rank 7", .code = 0xbf, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_IMC_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_m_rd_cas_rank0), /* shared */ .umasks = hswep_unc_m_rd_cas_rank0 }, }; libpfm-4.9.0/lib/events/intel_knl_unc_imc_events.h0000664000175000017500000000461113223402656022103 0ustar eranianeranian/* * Copyright (c) 2016 Intel Corp. All rights reserved * Contributed by Peinan Zhang * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * PMU: knl_unc_imc (Intel Knights Landing IMC uncore PMU) */ static const intel_x86_umask_t knl_unc_m_cas_count[]={ { .uname = "ALL", .udesc = "Counts total number of DRAM CAS commands issued on this channel", .ucode = 0x0300, }, { .uname = "RD", .udesc = "Counts all DRAM reads on this channel, incl. underfills", .ucode = 0x0100, }, { .uname = "WR", .udesc = "Counts number of DRAM write CAS commands on this channel", .ucode = 0x0200, }, }; static const intel_x86_entry_t intel_knl_unc_imc_pe[]={ { .name = "UNC_M_D_CLOCKTICKS", .desc = "IMC Uncore DCLK counts", .code = 0x00, /*encoding for generic counters */ .cntmsk = 0xf, }, { .name = "UNC_M_CAS_COUNT", .desc = "DRAM RD_CAS and WR_CAS Commands.", .code = 0x03, .cntmsk = 0xf, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(knl_unc_m_cas_count), .umasks = knl_unc_m_cas_count, }, }; static const intel_x86_entry_t intel_knl_unc_imc_uclk_pe[]={ { .name = "UNC_M_U_CLOCKTICKS", .desc = "IMC UCLK counts", .code = 0x00, /*encoding for generic counters */ .cntmsk = 0xf, }, }; libpfm-4.9.0/lib/events/montecito_events.h0000664000175000017500000037213713223402656020443 0ustar eranianeranian/* * Copyright (c) 2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. */ /* * This file is generated automatically * !! DO NOT CHANGE !! */ static pme_mont_entry_t montecito_pe []={ #define PME_MONT_ALAT_CAPACITY_MISS_ALL 0 { "ALAT_CAPACITY_MISS_ALL", {0x30058}, 0xfff0, 2, {0xffff0007}, "ALAT Entry Replaced -- both integer and floating point instructions"}, #define PME_MONT_ALAT_CAPACITY_MISS_FP 1 { "ALAT_CAPACITY_MISS_FP", {0x20058}, 0xfff0, 2, {0xffff0007}, "ALAT Entry Replaced -- only floating point instructions"}, #define PME_MONT_ALAT_CAPACITY_MISS_INT 2 { "ALAT_CAPACITY_MISS_INT", {0x10058}, 0xfff0, 2, {0xffff0007}, "ALAT Entry Replaced -- only integer instructions"}, #define PME_MONT_BACK_END_BUBBLE_ALL 3 { "BACK_END_BUBBLE_ALL", {0x0}, 0xfff0, 1, {0xffff0000}, "Full Pipe Bubbles in Main Pipe -- Front-end, RSE, EXE, FPU/L1D stall or a pipeline flush due to an exception/branch misprediction"}, #define PME_MONT_BACK_END_BUBBLE_FE 4 { "BACK_END_BUBBLE_FE", {0x10000}, 0xfff0, 1, {0xffff0000}, "Full Pipe Bubbles in Main Pipe -- front-end"}, #define PME_MONT_BACK_END_BUBBLE_L1D_FPU_RSE 5 { "BACK_END_BUBBLE_L1D_FPU_RSE", {0x20000}, 0xfff0, 1, {0xffff0000}, "Full Pipe Bubbles in Main Pipe -- L1D_FPU or RSE."}, #define PME_MONT_BE_BR_MISPRED_DETAIL_ANY 6 { "BE_BR_MISPRED_DETAIL_ANY", {0x61}, 0xfff0, 1, {0xffff0003}, "BE Branch Misprediction Detail -- any back-end (be) mispredictions"}, #define PME_MONT_BE_BR_MISPRED_DETAIL_PFS 7 { "BE_BR_MISPRED_DETAIL_PFS", {0x30061}, 0xfff0, 1, {0xffff0003}, "BE Branch Misprediction Detail -- only back-end pfs mispredictions for taken branches"}, #define PME_MONT_BE_BR_MISPRED_DETAIL_ROT 8 { "BE_BR_MISPRED_DETAIL_ROT", {0x20061}, 0xfff0, 1, {0xffff0003}, "BE Branch Misprediction Detail -- only back-end rotate mispredictions"}, #define PME_MONT_BE_BR_MISPRED_DETAIL_STG 9 { "BE_BR_MISPRED_DETAIL_STG", {0x10061}, 0xfff0, 1, {0xffff0003}, "BE Branch Misprediction Detail -- only back-end stage mispredictions"}, #define PME_MONT_BE_EXE_BUBBLE_ALL 10 { "BE_EXE_BUBBLE_ALL", {0x2}, 0xfff0, 1, {0xffff0000}, "Full Pipe Bubbles in Main Pipe due to Execution Unit Stalls -- Back-end was stalled by exe"}, #define PME_MONT_BE_EXE_BUBBLE_ARCR 11 { "BE_EXE_BUBBLE_ARCR", {0x40002}, 0xfff0, 1, {0xffff0000}, "Full Pipe Bubbles in Main Pipe due to Execution Unit Stalls -- Back-end was stalled by exe due to AR or CR dependency"}, #define PME_MONT_BE_EXE_BUBBLE_ARCR_PR_CANCEL_BANK 12 { "BE_EXE_BUBBLE_ARCR_PR_CANCEL_BANK", {0x80002}, 0xfff0, 1, {0xffff0000}, "Full Pipe Bubbles in Main Pipe due to Execution Unit Stalls -- ARCR, PR, CANCEL or BANK_SWITCH"}, #define PME_MONT_BE_EXE_BUBBLE_BANK_SWITCH 13 { "BE_EXE_BUBBLE_BANK_SWITCH", {0x70002}, 0xfff0, 1, {0xffff0000}, "Full Pipe Bubbles in Main Pipe due to Execution Unit Stalls -- Back-end was stalled by exe due to bank switching."}, #define PME_MONT_BE_EXE_BUBBLE_CANCEL 14 { "BE_EXE_BUBBLE_CANCEL", {0x60002}, 0xfff0, 1, {0xffff0000}, "Full Pipe Bubbles in Main Pipe due to Execution Unit Stalls -- Back-end was stalled by exe due to a canceled load"}, #define PME_MONT_BE_EXE_BUBBLE_FRALL 15 { "BE_EXE_BUBBLE_FRALL", {0x20002}, 0xfff0, 1, {0xffff0000}, "Full Pipe Bubbles in Main Pipe due to Execution Unit Stalls -- Back-end was stalled by exe due to FR/FR or FR/load dependency"}, #define PME_MONT_BE_EXE_BUBBLE_GRALL 16 { "BE_EXE_BUBBLE_GRALL", {0x10002}, 0xfff0, 1, {0xffff0000}, "Full Pipe Bubbles in Main Pipe due to Execution Unit Stalls -- Back-end was stalled by exe due to GR/GR or GR/load dependency"}, #define PME_MONT_BE_EXE_BUBBLE_GRGR 17 { "BE_EXE_BUBBLE_GRGR", {0x50002}, 0xfff0, 1, {0xffff0000}, "Full Pipe Bubbles in Main Pipe due to Execution Unit Stalls -- Back-end was stalled by exe due to GR/GR dependency"}, #define PME_MONT_BE_EXE_BUBBLE_PR 18 { "BE_EXE_BUBBLE_PR", {0x30002}, 0xfff0, 1, {0xffff0000}, "Full Pipe Bubbles in Main Pipe due to Execution Unit Stalls -- Back-end was stalled by exe due to PR dependency"}, #define PME_MONT_BE_FLUSH_BUBBLE_ALL 19 { "BE_FLUSH_BUBBLE_ALL", {0x4}, 0xfff0, 1, {0xffff0000}, "Full Pipe Bubbles in Main Pipe due to Flushes. -- Back-end was stalled due to either an exception/interruption or branch misprediction flush"}, #define PME_MONT_BE_FLUSH_BUBBLE_BRU 20 { "BE_FLUSH_BUBBLE_BRU", {0x10004}, 0xfff0, 1, {0xffff0000}, "Full Pipe Bubbles in Main Pipe due to Flushes. -- Back-end was stalled due to a branch misprediction flush"}, #define PME_MONT_BE_FLUSH_BUBBLE_XPN 21 { "BE_FLUSH_BUBBLE_XPN", {0x20004}, 0xfff0, 1, {0xffff0000}, "Full Pipe Bubbles in Main Pipe due to Flushes. -- Back-end was stalled due to an exception/interruption flush"}, #define PME_MONT_BE_L1D_FPU_BUBBLE_ALL 22 { "BE_L1D_FPU_BUBBLE_ALL", {0xca}, 0xfff0, 1, {0x5210000}, "Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D or FPU"}, #define PME_MONT_BE_L1D_FPU_BUBBLE_FPU 23 { "BE_L1D_FPU_BUBBLE_FPU", {0x100ca}, 0xfff0, 1, {0x5210000}, "Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by FPU."}, #define PME_MONT_BE_L1D_FPU_BUBBLE_L1D 24 { "BE_L1D_FPU_BUBBLE_L1D", {0x200ca}, 0xfff0, 1, {0x5210000}, "Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D. This includes all stalls caused by the L1 pipeline (created in the L1D stage of the L1 pipeline which corresponds to the DET stage of the main pipe)."}, #define PME_MONT_BE_L1D_FPU_BUBBLE_L1D_AR_CR 25 { "BE_L1D_FPU_BUBBLE_L1D_AR_CR", {0x800ca}, 0xfff0, 1, {0x5210000}, "Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to ar/cr requiring a stall"}, #define PME_MONT_BE_L1D_FPU_BUBBLE_L1D_FILLCONF 26 { "BE_L1D_FPU_BUBBLE_L1D_FILLCONF", {0x700ca}, 0xfff0, 1, {0x5210000}, "Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due a store in conflict with a returning fill."}, #define PME_MONT_BE_L1D_FPU_BUBBLE_L1D_FULLSTBUF 27 { "BE_L1D_FPU_BUBBLE_L1D_FULLSTBUF", {0x300ca}, 0xfff0, 1, {0x5210000}, "Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to store buffer being full"}, #define PME_MONT_BE_L1D_FPU_BUBBLE_L1D_HPW 28 { "BE_L1D_FPU_BUBBLE_L1D_HPW", {0x500ca}, 0xfff0, 1, {0x5210000}, "Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to Hardware Page Walker"}, #define PME_MONT_BE_L1D_FPU_BUBBLE_L1D_L2BPRESS 29 { "BE_L1D_FPU_BUBBLE_L1D_L2BPRESS", {0x900ca}, 0xfff0, 1, {0x5210000}, "Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to L2 Back Pressure"}, #define PME_MONT_BE_L1D_FPU_BUBBLE_L1D_LDCHK 30 { "BE_L1D_FPU_BUBBLE_L1D_LDCHK", {0xc00ca}, 0xfff0, 1, {0x5210000}, "Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to architectural ordering conflict"}, #define PME_MONT_BE_L1D_FPU_BUBBLE_L1D_LDCONF 31 { "BE_L1D_FPU_BUBBLE_L1D_LDCONF", {0xb00ca}, 0xfff0, 1, {0x5210000}, "Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to architectural ordering conflict"}, #define PME_MONT_BE_L1D_FPU_BUBBLE_L1D_NAT 32 { "BE_L1D_FPU_BUBBLE_L1D_NAT", {0xd00ca}, 0xfff0, 1, {0x5210000}, "Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to L1D data return needing recirculated NaT generation."}, #define PME_MONT_BE_L1D_FPU_BUBBLE_L1D_NATCONF 33 { "BE_L1D_FPU_BUBBLE_L1D_NATCONF", {0xf00ca}, 0xfff0, 1, {0x5210000}, "Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to ld8.fill conflict with st8.spill not written to unat."}, #define PME_MONT_BE_L1D_FPU_BUBBLE_L1D_PIPE_RECIRC 34 { "BE_L1D_FPU_BUBBLE_L1D_PIPE_RECIRC", {0x400ca}, 0xfff0, 1, {0x5210000}, "Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to recirculate"}, #define PME_MONT_BE_L1D_FPU_BUBBLE_L1D_STBUFRECIR 35 { "BE_L1D_FPU_BUBBLE_L1D_STBUFRECIR", {0xe00ca}, 0xfff0, 1, {0x5210000}, "Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to store buffer cancel needing recirculate."}, #define PME_MONT_BE_L1D_FPU_BUBBLE_L1D_TLB 36 { "BE_L1D_FPU_BUBBLE_L1D_TLB", {0xa00ca}, 0xfff0, 1, {0x5210000}, "Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to L2DTLB to L1DTLB transfer"}, #define PME_MONT_BE_LOST_BW_DUE_TO_FE_ALL 37 { "BE_LOST_BW_DUE_TO_FE_ALL", {0x72}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles if BE Not Stalled for Other Reasons. -- count regardless of cause"}, #define PME_MONT_BE_LOST_BW_DUE_TO_FE_BI 38 { "BE_LOST_BW_DUE_TO_FE_BI", {0x90072}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles if BE Not Stalled for Other Reasons. -- only if caused by branch initialization stall"}, #define PME_MONT_BE_LOST_BW_DUE_TO_FE_BRQ 39 { "BE_LOST_BW_DUE_TO_FE_BRQ", {0xa0072}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles if BE Not Stalled for Other Reasons. -- only if caused by branch retirement queue stall"}, #define PME_MONT_BE_LOST_BW_DUE_TO_FE_BR_ILOCK 40 { "BE_LOST_BW_DUE_TO_FE_BR_ILOCK", {0xc0072}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles if BE Not Stalled for Other Reasons. -- only if caused by branch interlock stall"}, #define PME_MONT_BE_LOST_BW_DUE_TO_FE_BUBBLE 41 { "BE_LOST_BW_DUE_TO_FE_BUBBLE", {0xd0072}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles if BE Not Stalled for Other Reasons. -- only if caused by branch resteer bubble stall"}, #define PME_MONT_BE_LOST_BW_DUE_TO_FE_FEFLUSH 42 { "BE_LOST_BW_DUE_TO_FE_FEFLUSH", {0x10072}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles if BE Not Stalled for Other Reasons. -- only if caused by a front-end flush"}, #define PME_MONT_BE_LOST_BW_DUE_TO_FE_FILL_RECIRC 43 { "BE_LOST_BW_DUE_TO_FE_FILL_RECIRC", {0x80072}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles if BE Not Stalled for Other Reasons. -- only if caused by a recirculate for a cache line fill operation"}, #define PME_MONT_BE_LOST_BW_DUE_TO_FE_IBFULL 44 { "BE_LOST_BW_DUE_TO_FE_IBFULL", {0x50072}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles if BE Not Stalled for Other Reasons. -- (* meaningless for this event *)"}, #define PME_MONT_BE_LOST_BW_DUE_TO_FE_IMISS 45 { "BE_LOST_BW_DUE_TO_FE_IMISS", {0x60072}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles if BE Not Stalled for Other Reasons. -- only if caused by instruction cache miss stall"}, #define PME_MONT_BE_LOST_BW_DUE_TO_FE_PLP 46 { "BE_LOST_BW_DUE_TO_FE_PLP", {0xb0072}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles if BE Not Stalled for Other Reasons. -- only if caused by perfect loop prediction stall"}, #define PME_MONT_BE_LOST_BW_DUE_TO_FE_TLBMISS 47 { "BE_LOST_BW_DUE_TO_FE_TLBMISS", {0x70072}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles if BE Not Stalled for Other Reasons. -- only if caused by TLB stall"}, #define PME_MONT_BE_LOST_BW_DUE_TO_FE_UNREACHED 48 { "BE_LOST_BW_DUE_TO_FE_UNREACHED", {0x40072}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles if BE Not Stalled for Other Reasons. -- only if caused by unreachable bundle"}, #define PME_MONT_BE_RSE_BUBBLE_ALL 49 { "BE_RSE_BUBBLE_ALL", {0x1}, 0xfff0, 1, {0xffff0000}, "Full Pipe Bubbles in Main Pipe due to RSE Stalls -- Back-end was stalled by RSE"}, #define PME_MONT_BE_RSE_BUBBLE_AR_DEP 50 { "BE_RSE_BUBBLE_AR_DEP", {0x20001}, 0xfff0, 1, {0xffff0000}, "Full Pipe Bubbles in Main Pipe due to RSE Stalls -- Back-end was stalled by RSE due to AR dependencies"}, #define PME_MONT_BE_RSE_BUBBLE_BANK_SWITCH 51 { "BE_RSE_BUBBLE_BANK_SWITCH", {0x10001}, 0xfff0, 1, {0xffff0000}, "Full Pipe Bubbles in Main Pipe due to RSE Stalls -- Back-end was stalled by RSE due to bank switching"}, #define PME_MONT_BE_RSE_BUBBLE_LOADRS 52 { "BE_RSE_BUBBLE_LOADRS", {0x50001}, 0xfff0, 1, {0xffff0000}, "Full Pipe Bubbles in Main Pipe due to RSE Stalls -- Back-end was stalled by RSE due to loadrs calculations"}, #define PME_MONT_BE_RSE_BUBBLE_OVERFLOW 53 { "BE_RSE_BUBBLE_OVERFLOW", {0x30001}, 0xfff0, 1, {0xffff0000}, "Full Pipe Bubbles in Main Pipe due to RSE Stalls -- Back-end was stalled by RSE due to need to spill"}, #define PME_MONT_BE_RSE_BUBBLE_UNDERFLOW 54 { "BE_RSE_BUBBLE_UNDERFLOW", {0x40001}, 0xfff0, 1, {0xffff0000}, "Full Pipe Bubbles in Main Pipe due to RSE Stalls -- Back-end was stalled by RSE due to need to fill"}, #define PME_MONT_BR_MISPRED_DETAIL_ALL_ALL_PRED 55 { "BR_MISPRED_DETAIL_ALL_ALL_PRED", {0x5b}, 0xfff0, 3, {0xffff0003}, "FE Branch Mispredict Detail -- All branch types regardless of prediction result"}, #define PME_MONT_BR_MISPRED_DETAIL_ALL_CORRECT_PRED 56 { "BR_MISPRED_DETAIL_ALL_CORRECT_PRED", {0x1005b}, 0xfff0, 3, {0xffff0003}, "FE Branch Mispredict Detail -- All branch types, correctly predicted branches (outcome and target)"}, #define PME_MONT_BR_MISPRED_DETAIL_ALL_WRONG_PATH 57 { "BR_MISPRED_DETAIL_ALL_WRONG_PATH", {0x2005b}, 0xfff0, 3, {0xffff0003}, "FE Branch Mispredict Detail -- All branch types, mispredicted branches due to wrong branch direction"}, #define PME_MONT_BR_MISPRED_DETAIL_ALL_WRONG_TARGET 58 { "BR_MISPRED_DETAIL_ALL_WRONG_TARGET", {0x3005b}, 0xfff0, 3, {0xffff0003}, "FE Branch Mispredict Detail -- All branch types, mispredicted branches due to wrong target for taken branches"}, #define PME_MONT_BR_MISPRED_DETAIL_IPREL_ALL_PRED 59 { "BR_MISPRED_DETAIL_IPREL_ALL_PRED", {0x4005b}, 0xfff0, 3, {0xffff0003}, "FE Branch Mispredict Detail -- Only IP relative branches, regardless of prediction result"}, #define PME_MONT_BR_MISPRED_DETAIL_IPREL_CORRECT_PRED 60 { "BR_MISPRED_DETAIL_IPREL_CORRECT_PRED", {0x5005b}, 0xfff0, 3, {0xffff0003}, "FE Branch Mispredict Detail -- Only IP relative branches, correctly predicted branches (outcome and target)"}, #define PME_MONT_BR_MISPRED_DETAIL_IPREL_WRONG_PATH 61 { "BR_MISPRED_DETAIL_IPREL_WRONG_PATH", {0x6005b}, 0xfff0, 3, {0xffff0003}, "FE Branch Mispredict Detail -- Only IP relative branches, mispredicted branches due to wrong branch direction"}, #define PME_MONT_BR_MISPRED_DETAIL_IPREL_WRONG_TARGET 62 { "BR_MISPRED_DETAIL_IPREL_WRONG_TARGET", {0x7005b}, 0xfff0, 3, {0xffff0003}, "FE Branch Mispredict Detail -- Only IP relative branches, mispredicted branches due to wrong target for taken branches"}, #define PME_MONT_BR_MISPRED_DETAIL_NRETIND_ALL_PRED 63 { "BR_MISPRED_DETAIL_NRETIND_ALL_PRED", {0xc005b}, 0xfff0, 3, {0xffff0003}, "FE Branch Mispredict Detail -- Only non-return indirect branches, regardless of prediction result"}, #define PME_MONT_BR_MISPRED_DETAIL_NRETIND_CORRECT_PRED 64 { "BR_MISPRED_DETAIL_NRETIND_CORRECT_PRED", {0xd005b}, 0xfff0, 3, {0xffff0003}, "FE Branch Mispredict Detail -- Only non-return indirect branches, correctly predicted branches (outcome and target)"}, #define PME_MONT_BR_MISPRED_DETAIL_NRETIND_WRONG_PATH 65 { "BR_MISPRED_DETAIL_NRETIND_WRONG_PATH", {0xe005b}, 0xfff0, 3, {0xffff0003}, "FE Branch Mispredict Detail -- Only non-return indirect branches, mispredicted branches due to wrong branch direction"}, #define PME_MONT_BR_MISPRED_DETAIL_NRETIND_WRONG_TARGET 66 { "BR_MISPRED_DETAIL_NRETIND_WRONG_TARGET", {0xf005b}, 0xfff0, 3, {0xffff0003}, "FE Branch Mispredict Detail -- Only non-return indirect branches, mispredicted branches due to wrong target for taken branches"}, #define PME_MONT_BR_MISPRED_DETAIL_RETURN_ALL_PRED 67 { "BR_MISPRED_DETAIL_RETURN_ALL_PRED", {0x8005b}, 0xfff0, 3, {0xffff0003}, "FE Branch Mispredict Detail -- Only return type branches, regardless of prediction result"}, #define PME_MONT_BR_MISPRED_DETAIL_RETURN_CORRECT_PRED 68 { "BR_MISPRED_DETAIL_RETURN_CORRECT_PRED", {0x9005b}, 0xfff0, 3, {0xffff0003}, "FE Branch Mispredict Detail -- Only return type branches, correctly predicted branches (outcome and target)"}, #define PME_MONT_BR_MISPRED_DETAIL_RETURN_WRONG_PATH 69 { "BR_MISPRED_DETAIL_RETURN_WRONG_PATH", {0xa005b}, 0xfff0, 3, {0xffff0003}, "FE Branch Mispredict Detail -- Only return type branches, mispredicted branches due to wrong branch direction"}, #define PME_MONT_BR_MISPRED_DETAIL_RETURN_WRONG_TARGET 70 { "BR_MISPRED_DETAIL_RETURN_WRONG_TARGET", {0xb005b}, 0xfff0, 3, {0xffff0003}, "FE Branch Mispredict Detail -- Only return type branches, mispredicted branches due to wrong target for taken branches"}, #define PME_MONT_BR_MISPRED_DETAIL2_ALL_ALL_UNKNOWN_PRED 71 { "BR_MISPRED_DETAIL2_ALL_ALL_UNKNOWN_PRED", {0x68}, 0xfff0, 2, {0xffff0003}, "FE Branch Mispredict Detail (Unknown Path Component) -- All branch types, branches with unknown path prediction"}, #define PME_MONT_BR_MISPRED_DETAIL2_ALL_UNKNOWN_PATH_CORRECT_PRED 72 { "BR_MISPRED_DETAIL2_ALL_UNKNOWN_PATH_CORRECT_PRED", {0x10068}, 0xfff0, 2, {0xffff0003}, "FE Branch Mispredict Detail (Unknown Path Component) -- All branch types, branches with unknown path prediction and correctly predicted branch (outcome & target)"}, #define PME_MONT_BR_MISPRED_DETAIL2_ALL_UNKNOWN_PATH_WRONG_PATH 73 { "BR_MISPRED_DETAIL2_ALL_UNKNOWN_PATH_WRONG_PATH", {0x20068}, 0xfff0, 2, {0xffff0003}, "FE Branch Mispredict Detail (Unknown Path Component) -- All branch types, branches with unknown path prediction and wrong branch direction"}, #define PME_MONT_BR_MISPRED_DETAIL2_IPREL_ALL_UNKNOWN_PRED 74 { "BR_MISPRED_DETAIL2_IPREL_ALL_UNKNOWN_PRED", {0x40068}, 0xfff0, 2, {0xffff0003}, "FE Branch Mispredict Detail (Unknown Path Component) -- Only IP relative branches, branches with unknown path prediction"}, #define PME_MONT_BR_MISPRED_DETAIL2_IPREL_UNKNOWN_PATH_CORRECT_PRED 75 { "BR_MISPRED_DETAIL2_IPREL_UNKNOWN_PATH_CORRECT_PRED", {0x50068}, 0xfff0, 2, {0xffff0003}, "FE Branch Mispredict Detail (Unknown Path Component) -- Only IP relative branches, branches with unknown path prediction and correct predicted branch (outcome & target)"}, #define PME_MONT_BR_MISPRED_DETAIL2_IPREL_UNKNOWN_PATH_WRONG_PATH 76 { "BR_MISPRED_DETAIL2_IPREL_UNKNOWN_PATH_WRONG_PATH", {0x60068}, 0xfff0, 2, {0xffff0003}, "FE Branch Mispredict Detail (Unknown Path Component) -- Only IP relative branches, branches with unknown path prediction and wrong branch direction"}, #define PME_MONT_BR_MISPRED_DETAIL2_NRETIND_ALL_UNKNOWN_PRED 77 { "BR_MISPRED_DETAIL2_NRETIND_ALL_UNKNOWN_PRED", {0xc0068}, 0xfff0, 2, {0xffff0003}, "FE Branch Mispredict Detail (Unknown Path Component) -- Only non-return indirect branches, branches with unknown path prediction"}, #define PME_MONT_BR_MISPRED_DETAIL2_NRETIND_UNKNOWN_PATH_CORRECT_PRED 78 { "BR_MISPRED_DETAIL2_NRETIND_UNKNOWN_PATH_CORRECT_PRED", {0xd0068}, 0xfff0, 2, {0xffff0003}, "FE Branch Mispredict Detail (Unknown Path Component) -- Only non-return indirect branches, branches with unknown path prediction and correct predicted branch (outcome & target)"}, #define PME_MONT_BR_MISPRED_DETAIL2_NRETIND_UNKNOWN_PATH_WRONG_PATH 79 { "BR_MISPRED_DETAIL2_NRETIND_UNKNOWN_PATH_WRONG_PATH", {0xe0068}, 0xfff0, 2, {0xffff0003}, "FE Branch Mispredict Detail (Unknown Path Component) -- Only non-return indirect branches, branches with unknown path prediction and wrong branch direction"}, #define PME_MONT_BR_MISPRED_DETAIL2_RETURN_ALL_UNKNOWN_PRED 80 { "BR_MISPRED_DETAIL2_RETURN_ALL_UNKNOWN_PRED", {0x80068}, 0xfff0, 2, {0xffff0003}, "FE Branch Mispredict Detail (Unknown Path Component) -- Only return type branches, branches with unknown path prediction"}, #define PME_MONT_BR_MISPRED_DETAIL2_RETURN_UNKNOWN_PATH_CORRECT_PRED 81 { "BR_MISPRED_DETAIL2_RETURN_UNKNOWN_PATH_CORRECT_PRED", {0x90068}, 0xfff0, 2, {0xffff0003}, "FE Branch Mispredict Detail (Unknown Path Component) -- Only return type branches, branches with unknown path prediction and correct predicted branch (outcome & target)"}, #define PME_MONT_BR_MISPRED_DETAIL2_RETURN_UNKNOWN_PATH_WRONG_PATH 82 { "BR_MISPRED_DETAIL2_RETURN_UNKNOWN_PATH_WRONG_PATH", {0xa0068}, 0xfff0, 2, {0xffff0003}, "FE Branch Mispredict Detail (Unknown Path Component) -- Only return type branches, branches with unknown path prediction and wrong branch direction"}, #define PME_MONT_BR_PATH_PRED_ALL_MISPRED_NOTTAKEN 83 { "BR_PATH_PRED_ALL_MISPRED_NOTTAKEN", {0x54}, 0xfff0, 3, {0xffff0003}, "FE Branch Path Prediction Detail -- All branch types, incorrectly predicted path and not taken branch"}, #define PME_MONT_BR_PATH_PRED_ALL_MISPRED_TAKEN 84 { "BR_PATH_PRED_ALL_MISPRED_TAKEN", {0x10054}, 0xfff0, 3, {0xffff0003}, "FE Branch Path Prediction Detail -- All branch types, incorrectly predicted path and taken branch"}, #define PME_MONT_BR_PATH_PRED_ALL_OKPRED_NOTTAKEN 85 { "BR_PATH_PRED_ALL_OKPRED_NOTTAKEN", {0x20054}, 0xfff0, 3, {0xffff0003}, "FE Branch Path Prediction Detail -- All branch types, correctly predicted path and not taken branch"}, #define PME_MONT_BR_PATH_PRED_ALL_OKPRED_TAKEN 86 { "BR_PATH_PRED_ALL_OKPRED_TAKEN", {0x30054}, 0xfff0, 3, {0xffff0003}, "FE Branch Path Prediction Detail -- All branch types, correctly predicted path and taken branch"}, #define PME_MONT_BR_PATH_PRED_IPREL_MISPRED_NOTTAKEN 87 { "BR_PATH_PRED_IPREL_MISPRED_NOTTAKEN", {0x40054}, 0xfff0, 3, {0xffff0003}, "FE Branch Path Prediction Detail -- Only IP relative branches, incorrectly predicted path and not taken branch"}, #define PME_MONT_BR_PATH_PRED_IPREL_MISPRED_TAKEN 88 { "BR_PATH_PRED_IPREL_MISPRED_TAKEN", {0x50054}, 0xfff0, 3, {0xffff0003}, "FE Branch Path Prediction Detail -- Only IP relative branches, incorrectly predicted path and taken branch"}, #define PME_MONT_BR_PATH_PRED_IPREL_OKPRED_NOTTAKEN 89 { "BR_PATH_PRED_IPREL_OKPRED_NOTTAKEN", {0x60054}, 0xfff0, 3, {0xffff0003}, "FE Branch Path Prediction Detail -- Only IP relative branches, correctly predicted path and not taken branch"}, #define PME_MONT_BR_PATH_PRED_IPREL_OKPRED_TAKEN 90 { "BR_PATH_PRED_IPREL_OKPRED_TAKEN", {0x70054}, 0xfff0, 3, {0xffff0003}, "FE Branch Path Prediction Detail -- Only IP relative branches, correctly predicted path and taken branch"}, #define PME_MONT_BR_PATH_PRED_NRETIND_MISPRED_NOTTAKEN 91 { "BR_PATH_PRED_NRETIND_MISPRED_NOTTAKEN", {0xc0054}, 0xfff0, 3, {0xffff0003}, "FE Branch Path Prediction Detail -- Only non-return indirect branches, incorrectly predicted path and not taken branch"}, #define PME_MONT_BR_PATH_PRED_NRETIND_MISPRED_TAKEN 92 { "BR_PATH_PRED_NRETIND_MISPRED_TAKEN", {0xd0054}, 0xfff0, 3, {0xffff0003}, "FE Branch Path Prediction Detail -- Only non-return indirect branches, incorrectly predicted path and taken branch"}, #define PME_MONT_BR_PATH_PRED_NRETIND_OKPRED_NOTTAKEN 93 { "BR_PATH_PRED_NRETIND_OKPRED_NOTTAKEN", {0xe0054}, 0xfff0, 3, {0xffff0003}, "FE Branch Path Prediction Detail -- Only non-return indirect branches, correctly predicted path and not taken branch"}, #define PME_MONT_BR_PATH_PRED_NRETIND_OKPRED_TAKEN 94 { "BR_PATH_PRED_NRETIND_OKPRED_TAKEN", {0xf0054}, 0xfff0, 3, {0xffff0003}, "FE Branch Path Prediction Detail -- Only non-return indirect branches, correctly predicted path and taken branch"}, #define PME_MONT_BR_PATH_PRED_RETURN_MISPRED_NOTTAKEN 95 { "BR_PATH_PRED_RETURN_MISPRED_NOTTAKEN", {0x80054}, 0xfff0, 3, {0xffff0003}, "FE Branch Path Prediction Detail -- Only return type branches, incorrectly predicted path and not taken branch"}, #define PME_MONT_BR_PATH_PRED_RETURN_MISPRED_TAKEN 96 { "BR_PATH_PRED_RETURN_MISPRED_TAKEN", {0x90054}, 0xfff0, 3, {0xffff0003}, "FE Branch Path Prediction Detail -- Only return type branches, incorrectly predicted path and taken branch"}, #define PME_MONT_BR_PATH_PRED_RETURN_OKPRED_NOTTAKEN 97 { "BR_PATH_PRED_RETURN_OKPRED_NOTTAKEN", {0xa0054}, 0xfff0, 3, {0xffff0003}, "FE Branch Path Prediction Detail -- Only return type branches, correctly predicted path and not taken branch"}, #define PME_MONT_BR_PATH_PRED_RETURN_OKPRED_TAKEN 98 { "BR_PATH_PRED_RETURN_OKPRED_TAKEN", {0xb0054}, 0xfff0, 3, {0xffff0003}, "FE Branch Path Prediction Detail -- Only return type branches, correctly predicted path and taken branch"}, #define PME_MONT_BR_PATH_PRED2_ALL_UNKNOWNPRED_NOTTAKEN 99 { "BR_PATH_PRED2_ALL_UNKNOWNPRED_NOTTAKEN", {0x6a}, 0xfff0, 2, {0xffff0003}, "FE Branch Path Prediction Detail (Unknown pred component) -- All branch types, unknown predicted path and not taken branch (which impacts OKPRED_NOTTAKEN)"}, #define PME_MONT_BR_PATH_PRED2_ALL_UNKNOWNPRED_TAKEN 100 { "BR_PATH_PRED2_ALL_UNKNOWNPRED_TAKEN", {0x1006a}, 0xfff0, 2, {0xffff0003}, "FE Branch Path Prediction Detail (Unknown pred component) -- All branch types, unknown predicted path and taken branch (which impacts MISPRED_TAKEN)"}, #define PME_MONT_BR_PATH_PRED2_IPREL_UNKNOWNPRED_NOTTAKEN 101 { "BR_PATH_PRED2_IPREL_UNKNOWNPRED_NOTTAKEN", {0x4006a}, 0xfff0, 2, {0xffff0003}, "FE Branch Path Prediction Detail (Unknown pred component) -- Only IP relative branches, unknown predicted path and not taken branch (which impacts OKPRED_NOTTAKEN)"}, #define PME_MONT_BR_PATH_PRED2_IPREL_UNKNOWNPRED_TAKEN 102 { "BR_PATH_PRED2_IPREL_UNKNOWNPRED_TAKEN", {0x5006a}, 0xfff0, 2, {0xffff0003}, "FE Branch Path Prediction Detail (Unknown pred component) -- Only IP relative branches, unknown predicted path and taken branch (which impacts MISPRED_TAKEN)"}, #define PME_MONT_BR_PATH_PRED2_NRETIND_UNKNOWNPRED_NOTTAKEN 103 { "BR_PATH_PRED2_NRETIND_UNKNOWNPRED_NOTTAKEN", {0xc006a}, 0xfff0, 2, {0xffff0003}, "FE Branch Path Prediction Detail (Unknown pred component) -- Only non-return indirect branches, unknown predicted path and not taken branch (which impacts OKPRED_NOTTAKEN)"}, #define PME_MONT_BR_PATH_PRED2_NRETIND_UNKNOWNPRED_TAKEN 104 { "BR_PATH_PRED2_NRETIND_UNKNOWNPRED_TAKEN", {0xd006a}, 0xfff0, 2, {0xffff0003}, "FE Branch Path Prediction Detail (Unknown pred component) -- Only non-return indirect branches, unknown predicted path and taken branch (which impacts MISPRED_TAKEN)"}, #define PME_MONT_BR_PATH_PRED2_RETURN_UNKNOWNPRED_NOTTAKEN 105 { "BR_PATH_PRED2_RETURN_UNKNOWNPRED_NOTTAKEN", {0x8006a}, 0xfff0, 2, {0xffff0003}, "FE Branch Path Prediction Detail (Unknown pred component) -- Only return type branches, unknown predicted path and not taken branch (which impacts OKPRED_NOTTAKEN)"}, #define PME_MONT_BR_PATH_PRED2_RETURN_UNKNOWNPRED_TAKEN 106 { "BR_PATH_PRED2_RETURN_UNKNOWNPRED_TAKEN", {0x9006a}, 0xfff0, 2, {0xffff0003}, "FE Branch Path Prediction Detail (Unknown pred component) -- Only return type branches, unknown predicted path and taken branch (which impacts MISPRED_TAKEN)"}, #define PME_MONT_BUS_ALL_ANY 107 { "BUS_ALL_ANY", {0x31887}, 0x03f0, 1, {0xffff0000}, "Bus Transactions -- CPU or non-CPU (all transactions)."}, #define PME_MONT_BUS_ALL_EITHER 108 { "BUS_ALL_EITHER", {0x1887}, 0x03f0, 1, {0xffff0000}, "Bus Transactions -- transactions initiated by either cpu core"}, #define PME_MONT_BUS_ALL_IO 109 { "BUS_ALL_IO", {0x11887}, 0x03f0, 1, {0xffff0000}, "Bus Transactions -- transactions initiated by non-CPU priority agents"}, #define PME_MONT_BUS_ALL_SELF 110 { "BUS_ALL_SELF", {0x21887}, 0x03f0, 1, {0xffff0000}, "Bus Transactions -- transactions initiated by 'this' cpu core"}, #define PME_MONT_BUS_B2B_DATA_CYCLES_ANY 111 { "BUS_B2B_DATA_CYCLES_ANY", {0x31093}, 0x03f0, 1, {0xffff0000}, "Back to Back Data Cycles on the Bus -- CPU or non-CPU (all transactions)."}, #define PME_MONT_BUS_B2B_DATA_CYCLES_EITHER 112 { "BUS_B2B_DATA_CYCLES_EITHER", {0x1093}, 0x03f0, 1, {0xffff0000}, "Back to Back Data Cycles on the Bus -- transactions initiated by either cpu core"}, #define PME_MONT_BUS_B2B_DATA_CYCLES_IO 113 { "BUS_B2B_DATA_CYCLES_IO", {0x11093}, 0x03f0, 1, {0xffff0000}, "Back to Back Data Cycles on the Bus -- transactions initiated by non-CPU priority agents"}, #define PME_MONT_BUS_B2B_DATA_CYCLES_SELF 114 { "BUS_B2B_DATA_CYCLES_SELF", {0x21093}, 0x03f0, 1, {0xffff0000}, "Back to Back Data Cycles on the Bus -- transactions initiated by 'this' cpu core"}, #define PME_MONT_BUS_DATA_CYCLE_ANY 115 { "BUS_DATA_CYCLE_ANY", {0x31088}, 0x03f0, 1, {0xffff0000}, "Valid Data Cycle on the Bus -- CPU or non-CPU (all transactions)."}, #define PME_MONT_BUS_DATA_CYCLE_EITHER 116 { "BUS_DATA_CYCLE_EITHER", {0x1088}, 0x03f0, 1, {0xffff0000}, "Valid Data Cycle on the Bus -- transactions initiated by either cpu core"}, #define PME_MONT_BUS_DATA_CYCLE_IO 117 { "BUS_DATA_CYCLE_IO", {0x11088}, 0x03f0, 1, {0xffff0000}, "Valid Data Cycle on the Bus -- transactions initiated by non-CPU priority agents"}, #define PME_MONT_BUS_DATA_CYCLE_SELF 118 { "BUS_DATA_CYCLE_SELF", {0x21088}, 0x03f0, 1, {0xffff0000}, "Valid Data Cycle on the Bus -- transactions initiated by 'this' cpu core"}, #define PME_MONT_BUS_HITM_ANY 119 { "BUS_HITM_ANY", {0x31884}, 0x03f0, 1, {0xffff0000}, "Bus Hit Modified Line Transactions -- CPU or non-CPU (all transactions)."}, #define PME_MONT_BUS_HITM_EITHER 120 { "BUS_HITM_EITHER", {0x1884}, 0x03f0, 1, {0xffff0000}, "Bus Hit Modified Line Transactions -- transactions initiated by either cpu core"}, #define PME_MONT_BUS_HITM_IO 121 { "BUS_HITM_IO", {0x11884}, 0x03f0, 1, {0xffff0000}, "Bus Hit Modified Line Transactions -- transactions initiated by non-CPU priority agents"}, #define PME_MONT_BUS_HITM_SELF 122 { "BUS_HITM_SELF", {0x21884}, 0x03f0, 1, {0xffff0000}, "Bus Hit Modified Line Transactions -- transactions initiated by 'this' cpu core"}, #define PME_MONT_BUS_IO_ANY 123 { "BUS_IO_ANY", {0x31890}, 0x03f0, 1, {0xffff0000}, "IA-32 Compatible IO Bus Transactions -- CPU or non-CPU (all transactions)."}, #define PME_MONT_BUS_IO_EITHER 124 { "BUS_IO_EITHER", {0x1890}, 0x03f0, 1, {0xffff0000}, "IA-32 Compatible IO Bus Transactions -- transactions initiated by either cpu core"}, #define PME_MONT_BUS_IO_IO 125 { "BUS_IO_IO", {0x11890}, 0x03f0, 1, {0xffff0000}, "IA-32 Compatible IO Bus Transactions -- transactions initiated by non-CPU priority agents"}, #define PME_MONT_BUS_IO_SELF 126 { "BUS_IO_SELF", {0x21890}, 0x03f0, 1, {0xffff0000}, "IA-32 Compatible IO Bus Transactions -- transactions initiated by 'this' cpu core"}, #define PME_MONT_BUS_MEMORY_ALL_ANY 127 { "BUS_MEMORY_ALL_ANY", {0xf188a}, 0x03f0, 1, {0xffff0000}, "Bus Memory Transactions -- All bus transactions from CPU or non-CPU (all transactions)."}, #define PME_MONT_BUS_MEMORY_ALL_EITHER 128 { "BUS_MEMORY_ALL_EITHER", {0xc188a}, 0x03f0, 1, {0xffff0000}, "Bus Memory Transactions -- All bus transactions from non-CPU priority agents"}, #define PME_MONT_BUS_MEMORY_ALL_IO 129 { "BUS_MEMORY_ALL_IO", {0xd188a}, 0x03f0, 1, {0xffff0000}, "Bus Memory Transactions -- All bus transactions from 'this' local processor"}, #define PME_MONT_BUS_MEMORY_ALL_SELF 130 { "BUS_MEMORY_ALL_SELF", {0xe188a}, 0x03f0, 1, {0xffff0000}, "Bus Memory Transactions -- All bus transactions from CPU or non-CPU (all transactions)."}, #define PME_MONT_BUS_MEMORY_EQ_128BYTE_ANY 131 { "BUS_MEMORY_EQ_128BYTE_ANY", {0x7188a}, 0x03f0, 1, {0xffff0000}, "Bus Memory Transactions -- number of less than full cache line transactions (BRP, BWP, BIL) from either local processor"}, #define PME_MONT_BUS_MEMORY_EQ_128BYTE_EITHER 132 { "BUS_MEMORY_EQ_128BYTE_EITHER", {0x4188a}, 0x03f0, 1, {0xffff0000}, "Bus Memory Transactions -- number of full cache line transactions (BRL, BRIL, BWL, BRC, BCR, BCCL) from non-CPU priority agents"}, #define PME_MONT_BUS_MEMORY_EQ_128BYTE_IO 133 { "BUS_MEMORY_EQ_128BYTE_IO", {0x5188a}, 0x03f0, 1, {0xffff0000}, "Bus Memory Transactions -- number of full cache line transactions (BRL, BRIL, BWL, BRC, BCR, BCCL) from 'this' processor"}, #define PME_MONT_BUS_MEMORY_EQ_128BYTE_SELF 134 { "BUS_MEMORY_EQ_128BYTE_SELF", {0x6188a}, 0x03f0, 1, {0xffff0000}, "Bus Memory Transactions -- number of full cache line transactions (BRL, BRIL, BWL, BRC, BCR, BCCL) from CPU or non-CPU (all transactions)."}, #define PME_MONT_BUS_MEMORY_LT_128BYTE_ANY 135 { "BUS_MEMORY_LT_128BYTE_ANY", {0xb188a}, 0x03f0, 1, {0xffff0000}, "Bus Memory Transactions -- All bus transactions from either local processor"}, #define PME_MONT_BUS_MEMORY_LT_128BYTE_EITHER 136 { "BUS_MEMORY_LT_128BYTE_EITHER", {0x8188a}, 0x03f0, 1, {0xffff0000}, "Bus Memory Transactions -- number of less than full cache line transactions (BRP, BWP, BIL) from non-CPU priority agents"}, #define PME_MONT_BUS_MEMORY_LT_128BYTE_IO 137 { "BUS_MEMORY_LT_128BYTE_IO", {0x9188a}, 0x03f0, 1, {0xffff0000}, "Bus Memory Transactions -- number of less than full cache line transactions (BRP, BWP, BIL) from 'this' processor"}, #define PME_MONT_BUS_MEMORY_LT_128BYTE_SELF 138 { "BUS_MEMORY_LT_128BYTE_SELF", {0xa188a}, 0x03f0, 1, {0xffff0000}, "Bus Memory Transactions -- number of less than full cache line transactions (BRP, BWP, BIL) CPU or non-CPU (all transactions)."}, #define PME_MONT_BUS_MEM_READ_ALL_ANY 139 { "BUS_MEM_READ_ALL_ANY", {0xf188b}, 0x03f0, 1, {0xffff0000}, "Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- All memory read transactions from CPU or non-CPU (all transactions)."}, #define PME_MONT_BUS_MEM_READ_ALL_EITHER 140 { "BUS_MEM_READ_ALL_EITHER", {0xc188b}, 0x03f0, 1, {0xffff0000}, "Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- All memory read transactions from either local processor"}, #define PME_MONT_BUS_MEM_READ_ALL_IO 141 { "BUS_MEM_READ_ALL_IO", {0xd188b}, 0x03f0, 1, {0xffff0000}, "Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- All memory read transactions from non-CPU priority agents"}, #define PME_MONT_BUS_MEM_READ_ALL_SELF 142 { "BUS_MEM_READ_ALL_SELF", {0xe188b}, 0x03f0, 1, {0xffff0000}, "Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- All memory read transactions from local processor"}, #define PME_MONT_BUS_MEM_READ_BIL_ANY 143 { "BUS_MEM_READ_BIL_ANY", {0x3188b}, 0x03f0, 1, {0xffff0000}, "Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- Number of BIL 0-byte memory read invalidate transactions from CPU or non-CPU (all transactions)."}, #define PME_MONT_BUS_MEM_READ_BIL_EITHER 144 { "BUS_MEM_READ_BIL_EITHER", {0x188b}, 0x03f0, 1, {0xffff0000}, "Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- Number of BIL 0-byte memory read invalidate transactions from either local processor"}, #define PME_MONT_BUS_MEM_READ_BIL_IO 145 { "BUS_MEM_READ_BIL_IO", {0x1188b}, 0x03f0, 1, {0xffff0000}, "Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- Number of BIL 0-byte memory read invalidate transactions from non-CPU priority agents"}, #define PME_MONT_BUS_MEM_READ_BIL_SELF 146 { "BUS_MEM_READ_BIL_SELF", {0x2188b}, 0x03f0, 1, {0xffff0000}, "Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- Number of BIL 0-byte memory read invalidate transactions from local processor"}, #define PME_MONT_BUS_MEM_READ_BRIL_ANY 147 { "BUS_MEM_READ_BRIL_ANY", {0xb188b}, 0x03f0, 1, {0xffff0000}, "Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- Number of full cache line memory read invalidate transactions from CPU or non-CPU (all transactions)."}, #define PME_MONT_BUS_MEM_READ_BRIL_EITHER 148 { "BUS_MEM_READ_BRIL_EITHER", {0x8188b}, 0x03f0, 1, {0xffff0000}, "Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- Number of full cache line memory read invalidate transactions from either local processor"}, #define PME_MONT_BUS_MEM_READ_BRIL_IO 149 { "BUS_MEM_READ_BRIL_IO", {0x9188b}, 0x03f0, 1, {0xffff0000}, "Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- Number of full cache line memory read invalidate transactions from non-CPU priority agents"}, #define PME_MONT_BUS_MEM_READ_BRIL_SELF 150 { "BUS_MEM_READ_BRIL_SELF", {0xa188b}, 0x03f0, 1, {0xffff0000}, "Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- Number of full cache line memory read invalidate transactions from local processor"}, #define PME_MONT_BUS_MEM_READ_BRL_ANY 151 { "BUS_MEM_READ_BRL_ANY", {0x7188b}, 0x03f0, 1, {0xffff0000}, "Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- Number of full cache line memory read transactions from CPU or non-CPU (all transactions)."}, #define PME_MONT_BUS_MEM_READ_BRL_EITHER 152 { "BUS_MEM_READ_BRL_EITHER", {0x4188b}, 0x03f0, 1, {0xffff0000}, "Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- Number of full cache line memory read transactions from either local processor"}, #define PME_MONT_BUS_MEM_READ_BRL_IO 153 { "BUS_MEM_READ_BRL_IO", {0x5188b}, 0x03f0, 1, {0xffff0000}, "Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- Number of full cache line memory read transactions from non-CPU priority agents"}, #define PME_MONT_BUS_MEM_READ_BRL_SELF 154 { "BUS_MEM_READ_BRL_SELF", {0x6188b}, 0x03f0, 1, {0xffff0000}, "Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- Number of full cache line memory read transactions from local processor"}, #define PME_MONT_BUS_RD_DATA_ANY 155 { "BUS_RD_DATA_ANY", {0x3188c}, 0x03f0, 1, {0xffff0000}, "Bus Read Data Transactions -- CPU or non-CPU (all transactions)."}, #define PME_MONT_BUS_RD_DATA_EITHER 156 { "BUS_RD_DATA_EITHER", {0x188c}, 0x03f0, 1, {0xffff0000}, "Bus Read Data Transactions -- transactions initiated by either cpu core"}, #define PME_MONT_BUS_RD_DATA_IO 157 { "BUS_RD_DATA_IO", {0x1188c}, 0x03f0, 1, {0xffff0000}, "Bus Read Data Transactions -- transactions initiated by non-CPU priority agents"}, #define PME_MONT_BUS_RD_DATA_SELF 158 { "BUS_RD_DATA_SELF", {0x2188c}, 0x03f0, 1, {0xffff0000}, "Bus Read Data Transactions -- transactions initiated by 'this' cpu core"}, #define PME_MONT_BUS_RD_HIT_ANY 159 { "BUS_RD_HIT_ANY", {0x31880}, 0x03f0, 1, {0xffff0000}, "Bus Read Hit Clean Non-local Cache Transactions -- CPU or non-CPU (all transactions)."}, #define PME_MONT_BUS_RD_HIT_EITHER 160 { "BUS_RD_HIT_EITHER", {0x1880}, 0x03f0, 1, {0xffff0000}, "Bus Read Hit Clean Non-local Cache Transactions -- transactions initiated by either cpu core"}, #define PME_MONT_BUS_RD_HIT_IO 161 { "BUS_RD_HIT_IO", {0x11880}, 0x03f0, 1, {0xffff0000}, "Bus Read Hit Clean Non-local Cache Transactions -- transactions initiated by non-CPU priority agents"}, #define PME_MONT_BUS_RD_HIT_SELF 162 { "BUS_RD_HIT_SELF", {0x21880}, 0x03f0, 1, {0xffff0000}, "Bus Read Hit Clean Non-local Cache Transactions -- transactions initiated by 'this' cpu core"}, #define PME_MONT_BUS_RD_HITM_ANY 163 { "BUS_RD_HITM_ANY", {0x31881}, 0x03f0, 1, {0xffff0000}, "Bus Read Hit Modified Non-local Cache Transactions -- CPU or non-CPU (all transactions)."}, #define PME_MONT_BUS_RD_HITM_EITHER 164 { "BUS_RD_HITM_EITHER", {0x1881}, 0x03f0, 1, {0xffff0000}, "Bus Read Hit Modified Non-local Cache Transactions -- transactions initiated by either cpu core"}, #define PME_MONT_BUS_RD_HITM_IO 165 { "BUS_RD_HITM_IO", {0x11881}, 0x03f0, 1, {0xffff0000}, "Bus Read Hit Modified Non-local Cache Transactions -- transactions initiated by non-CPU priority agents"}, #define PME_MONT_BUS_RD_HITM_SELF 166 { "BUS_RD_HITM_SELF", {0x21881}, 0x03f0, 1, {0xffff0000}, "Bus Read Hit Modified Non-local Cache Transactions -- transactions initiated by 'this' cpu core"}, #define PME_MONT_BUS_RD_INVAL_BST_HITM_ANY 167 { "BUS_RD_INVAL_BST_HITM_ANY", {0x31883}, 0x03f0, 1, {0xffff0000}, "Bus BRIL Transaction Results in HITM -- CPU or non-CPU (all transactions)."}, #define PME_MONT_BUS_RD_INVAL_BST_HITM_EITHER 168 { "BUS_RD_INVAL_BST_HITM_EITHER", {0x1883}, 0x03f0, 1, {0xffff0000}, "Bus BRIL Transaction Results in HITM -- transactions initiated by either cpu core"}, #define PME_MONT_BUS_RD_INVAL_BST_HITM_IO 169 { "BUS_RD_INVAL_BST_HITM_IO", {0x11883}, 0x03f0, 1, {0xffff0000}, "Bus BRIL Transaction Results in HITM -- transactions initiated by non-CPU priority agents"}, #define PME_MONT_BUS_RD_INVAL_BST_HITM_SELF 170 { "BUS_RD_INVAL_BST_HITM_SELF", {0x21883}, 0x03f0, 1, {0xffff0000}, "Bus BRIL Transaction Results in HITM -- transactions initiated by 'this' cpu core"}, #define PME_MONT_BUS_RD_INVAL_HITM_ANY 171 { "BUS_RD_INVAL_HITM_ANY", {0x31882}, 0x03f0, 1, {0xffff0000}, "Bus BIL Transaction Results in HITM -- CPU or non-CPU (all transactions)."}, #define PME_MONT_BUS_RD_INVAL_HITM_EITHER 172 { "BUS_RD_INVAL_HITM_EITHER", {0x1882}, 0x03f0, 1, {0xffff0000}, "Bus BIL Transaction Results in HITM -- transactions initiated by either cpu core"}, #define PME_MONT_BUS_RD_INVAL_HITM_IO 173 { "BUS_RD_INVAL_HITM_IO", {0x11882}, 0x03f0, 1, {0xffff0000}, "Bus BIL Transaction Results in HITM -- transactions initiated by non-CPU priority agents"}, #define PME_MONT_BUS_RD_INVAL_HITM_SELF 174 { "BUS_RD_INVAL_HITM_SELF", {0x21882}, 0x03f0, 1, {0xffff0000}, "Bus BIL Transaction Results in HITM -- transactions initiated by 'this' cpu core"}, #define PME_MONT_BUS_RD_IO_ANY 175 { "BUS_RD_IO_ANY", {0x31891}, 0x03f0, 1, {0xffff0000}, "IA-32 Compatible IO Read Transactions -- CPU or non-CPU (all transactions)."}, #define PME_MONT_BUS_RD_IO_EITHER 176 { "BUS_RD_IO_EITHER", {0x1891}, 0x03f0, 1, {0xffff0000}, "IA-32 Compatible IO Read Transactions -- transactions initiated by either cpu core"}, #define PME_MONT_BUS_RD_IO_IO 177 { "BUS_RD_IO_IO", {0x11891}, 0x03f0, 1, {0xffff0000}, "IA-32 Compatible IO Read Transactions -- transactions initiated by non-CPU priority agents"}, #define PME_MONT_BUS_RD_IO_SELF 178 { "BUS_RD_IO_SELF", {0x21891}, 0x03f0, 1, {0xffff0000}, "IA-32 Compatible IO Read Transactions -- transactions initiated by 'this' cpu core"}, #define PME_MONT_BUS_RD_PRTL_ANY 179 { "BUS_RD_PRTL_ANY", {0x3188d}, 0x03f0, 1, {0xffff0000}, "Bus Read Partial Transactions -- CPU or non-CPU (all transactions)."}, #define PME_MONT_BUS_RD_PRTL_EITHER 180 { "BUS_RD_PRTL_EITHER", {0x188d}, 0x03f0, 1, {0xffff0000}, "Bus Read Partial Transactions -- transactions initiated by either cpu core"}, #define PME_MONT_BUS_RD_PRTL_IO 181 { "BUS_RD_PRTL_IO", {0x1188d}, 0x03f0, 1, {0xffff0000}, "Bus Read Partial Transactions -- transactions initiated by non-CPU priority agents"}, #define PME_MONT_BUS_RD_PRTL_SELF 182 { "BUS_RD_PRTL_SELF", {0x2188d}, 0x03f0, 1, {0xffff0000}, "Bus Read Partial Transactions -- transactions initiated by 'this' cpu core"}, #define PME_MONT_BUS_SNOOP_STALL_CYCLES_ANY 183 { "BUS_SNOOP_STALL_CYCLES_ANY", {0x3188f}, 0x03f0, 1, {0xffff0000}, "Bus Snoop Stall Cycles (from any agent) -- CPU or non-CPU (all transactions)."}, #define PME_MONT_BUS_SNOOP_STALL_CYCLES_EITHER 184 { "BUS_SNOOP_STALL_CYCLES_EITHER", {0x188f}, 0x03f0, 1, {0xffff0000}, "Bus Snoop Stall Cycles (from any agent) -- transactions initiated by either cpu core"}, #define PME_MONT_BUS_SNOOP_STALL_CYCLES_SELF 185 { "BUS_SNOOP_STALL_CYCLES_SELF", {0x2188f}, 0x03f0, 1, {0xffff0000}, "Bus Snoop Stall Cycles (from any agent) -- local processor"}, #define PME_MONT_BUS_WR_WB_ALL_ANY 186 { "BUS_WR_WB_ALL_ANY", {0xf1892}, 0x03f0, 1, {0xffff0000}, "Bus Write Back Transactions -- CPU or non-CPU (all transactions)."}, #define PME_MONT_BUS_WR_WB_ALL_IO 187 { "BUS_WR_WB_ALL_IO", {0xd1892}, 0x03f0, 1, {0xffff0000}, "Bus Write Back Transactions -- non-CPU priority agents"}, #define PME_MONT_BUS_WR_WB_ALL_SELF 188 { "BUS_WR_WB_ALL_SELF", {0xe1892}, 0x03f0, 1, {0xffff0000}, "Bus Write Back Transactions -- this' processor"}, #define PME_MONT_BUS_WR_WB_CCASTOUT_ANY 189 { "BUS_WR_WB_CCASTOUT_ANY", {0xb1892}, 0x03f0, 1, {0xffff0000}, "Bus Write Back Transactions -- CPU or non-CPU (all transactions)/Only 0-byte transactions with write back attribute (clean cast outs) will be counted"}, #define PME_MONT_BUS_WR_WB_CCASTOUT_SELF 190 { "BUS_WR_WB_CCASTOUT_SELF", {0xa1892}, 0x03f0, 1, {0xffff0000}, "Bus Write Back Transactions -- this' processor/Only 0-byte transactions with write back attribute (clean cast outs) will be counted"}, #define PME_MONT_BUS_WR_WB_EQ_128BYTE_ANY 191 { "BUS_WR_WB_EQ_128BYTE_ANY", {0x71892}, 0x03f0, 1, {0xffff0000}, "Bus Write Back Transactions -- CPU or non-CPU (all transactions)./Only cache line transactions with write back or write coalesce attributes will be counted."}, #define PME_MONT_BUS_WR_WB_EQ_128BYTE_IO 192 { "BUS_WR_WB_EQ_128BYTE_IO", {0x51892}, 0x03f0, 1, {0xffff0000}, "Bus Write Back Transactions -- non-CPU priority agents/Only cache line transactions with write back or write coalesce attributes will be counted."}, #define PME_MONT_BUS_WR_WB_EQ_128BYTE_SELF 193 { "BUS_WR_WB_EQ_128BYTE_SELF", {0x61892}, 0x03f0, 1, {0xffff0000}, "Bus Write Back Transactions -- this' processor/Only cache line transactions with write back or write coalesce attributes will be counted."}, #define PME_MONT_CPU_CPL_CHANGES_ALL 194 { "CPU_CPL_CHANGES_ALL", {0xf0013}, 0xfff0, 1, {0xffff0000}, "Privilege Level Changes -- All changes in cpl counted"}, #define PME_MONT_CPU_CPL_CHANGES_LVL0 195 { "CPU_CPL_CHANGES_LVL0", {0x10013}, 0xfff0, 1, {0xffff0000}, "Privilege Level Changes -- All changes to/from privilege level0 are counted"}, #define PME_MONT_CPU_CPL_CHANGES_LVL1 196 { "CPU_CPL_CHANGES_LVL1", {0x20013}, 0xfff0, 1, {0xffff0000}, "Privilege Level Changes -- All changes to/from privilege level1 are counted"}, #define PME_MONT_CPU_CPL_CHANGES_LVL2 197 { "CPU_CPL_CHANGES_LVL2", {0x40013}, 0xfff0, 1, {0xffff0000}, "Privilege Level Changes -- All changes to/from privilege level2 are counted"}, #define PME_MONT_CPU_CPL_CHANGES_LVL3 198 { "CPU_CPL_CHANGES_LVL3", {0x80013}, 0xfff0, 1, {0xffff0000}, "Privilege Level Changes -- All changes to/from privilege level3 are counted"}, #define PME_MONT_CPU_OP_CYCLES_ALL 199 { "CPU_OP_CYCLES_ALL", {0x1012}, 0xfff0, 1, {0xffff0000}, "CPU Operating Cycles -- All CPU cycles counted"}, #define PME_MONT_CPU_OP_CYCLES_QUAL 200 { "CPU_OP_CYCLES_QUAL", {0x11012}, 0xfff0, 1, {0xffff0003}, "CPU Operating Cycles -- Qualified cycles only"}, #define PME_MONT_CPU_OP_CYCLES_HALTED 201 { "CPU_OP_CYCLES_HALTED", {0x1018}, 0x0400, 7, {0xffff0000}, "CPU Operating Cycles Halted"}, #define PME_MONT_DATA_DEBUG_REGISTER_FAULT 202 { "DATA_DEBUG_REGISTER_FAULT", {0x52}, 0xfff0, 1, {0xffff0000}, "Fault Due to Data Debug Reg. Match to Load/Store Instruction"}, #define PME_MONT_DATA_DEBUG_REGISTER_MATCHES 203 { "DATA_DEBUG_REGISTER_MATCHES", {0xc6}, 0xfff0, 1, {0xffff0007}, "Data Debug Register Matches Data Address of Memory Reference."}, #define PME_MONT_DATA_EAR_ALAT 204 { "DATA_EAR_ALAT", {0xec8}, 0xfff0, 1, {0xffff0007}, "Data EAR ALAT"}, #define PME_MONT_DATA_EAR_CACHE_LAT1024 205 { "DATA_EAR_CACHE_LAT1024", {0x80dc8}, 0xfff0, 1, {0xffff0007}, "Data EAR Cache -- >= 1024 Cycles"}, #define PME_MONT_DATA_EAR_CACHE_LAT128 206 { "DATA_EAR_CACHE_LAT128", {0x50dc8}, 0xfff0, 1, {0xffff0007}, "Data EAR Cache -- >= 128 Cycles"}, #define PME_MONT_DATA_EAR_CACHE_LAT16 207 { "DATA_EAR_CACHE_LAT16", {0x20dc8}, 0xfff0, 1, {0xffff0007}, "Data EAR Cache -- >= 16 Cycles"}, #define PME_MONT_DATA_EAR_CACHE_LAT2048 208 { "DATA_EAR_CACHE_LAT2048", {0x90dc8}, 0xfff0, 1, {0xffff0007}, "Data EAR Cache -- >= 2048 Cycles"}, #define PME_MONT_DATA_EAR_CACHE_LAT256 209 { "DATA_EAR_CACHE_LAT256", {0x60dc8}, 0xfff0, 1, {0xffff0007}, "Data EAR Cache -- >= 256 Cycles"}, #define PME_MONT_DATA_EAR_CACHE_LAT32 210 { "DATA_EAR_CACHE_LAT32", {0x30dc8}, 0xfff0, 1, {0xffff0007}, "Data EAR Cache -- >= 32 Cycles"}, #define PME_MONT_DATA_EAR_CACHE_LAT4 211 { "DATA_EAR_CACHE_LAT4", {0xdc8}, 0xfff0, 1, {0xffff0007}, "Data EAR Cache -- >= 4 Cycles"}, #define PME_MONT_DATA_EAR_CACHE_LAT4096 212 { "DATA_EAR_CACHE_LAT4096", {0xa0dc8}, 0xfff0, 1, {0xffff0007}, "Data EAR Cache -- >= 4096 Cycles"}, #define PME_MONT_DATA_EAR_CACHE_LAT512 213 { "DATA_EAR_CACHE_LAT512", {0x70dc8}, 0xfff0, 1, {0xffff0007}, "Data EAR Cache -- >= 512 Cycles"}, #define PME_MONT_DATA_EAR_CACHE_LAT64 214 { "DATA_EAR_CACHE_LAT64", {0x40dc8}, 0xfff0, 1, {0xffff0007}, "Data EAR Cache -- >= 64 Cycles"}, #define PME_MONT_DATA_EAR_CACHE_LAT8 215 { "DATA_EAR_CACHE_LAT8", {0x10dc8}, 0xfff0, 1, {0xffff0007}, "Data EAR Cache -- >= 8 Cycles"}, #define PME_MONT_DATA_EAR_EVENTS 216 { "DATA_EAR_EVENTS", {0x8c8}, 0xfff0, 1, {0xffff0007}, "L1 Data Cache EAR Events"}, #define PME_MONT_DATA_EAR_TLB_ALL 217 { "DATA_EAR_TLB_ALL", {0xe0cc8}, 0xfff0, 1, {0xffff0007}, "Data EAR TLB -- All L1 DTLB Misses"}, #define PME_MONT_DATA_EAR_TLB_FAULT 218 { "DATA_EAR_TLB_FAULT", {0x80cc8}, 0xfff0, 1, {0xffff0007}, "Data EAR TLB -- DTLB Misses which produce a software fault"}, #define PME_MONT_DATA_EAR_TLB_L2DTLB 219 { "DATA_EAR_TLB_L2DTLB", {0x20cc8}, 0xfff0, 1, {0xffff0007}, "Data EAR TLB -- L1 DTLB Misses which hit L2 DTLB"}, #define PME_MONT_DATA_EAR_TLB_L2DTLB_OR_FAULT 220 { "DATA_EAR_TLB_L2DTLB_OR_FAULT", {0xa0cc8}, 0xfff0, 1, {0xffff0007}, "Data EAR TLB -- L1 DTLB Misses which hit L2 DTLB or produce a software fault"}, #define PME_MONT_DATA_EAR_TLB_L2DTLB_OR_VHPT 221 { "DATA_EAR_TLB_L2DTLB_OR_VHPT", {0x60cc8}, 0xfff0, 1, {0xffff0007}, "Data EAR TLB -- L1 DTLB Misses which hit L2 DTLB or VHPT"}, #define PME_MONT_DATA_EAR_TLB_VHPT 222 { "DATA_EAR_TLB_VHPT", {0x40cc8}, 0xfff0, 1, {0xffff0007}, "Data EAR TLB -- L1 DTLB Misses which hit VHPT"}, #define PME_MONT_DATA_EAR_TLB_VHPT_OR_FAULT 223 { "DATA_EAR_TLB_VHPT_OR_FAULT", {0xc0cc8}, 0xfff0, 1, {0xffff0007}, "Data EAR TLB -- L1 DTLB Misses which hit VHPT or produce a software fault"}, #define PME_MONT_DATA_REFERENCES_SET0 224 { "DATA_REFERENCES_SET0", {0xc3}, 0xfff0, 4, {0x5010007}, "Data Memory References Issued to Memory Pipeline"}, #define PME_MONT_DATA_REFERENCES_SET1 225 { "DATA_REFERENCES_SET1", {0xc5}, 0xfff0, 4, {0x5110007}, "Data Memory References Issued to Memory Pipeline"}, #define PME_MONT_DISP_STALLED 226 { "DISP_STALLED", {0x49}, 0xfff0, 1, {0xffff0000}, "Number of Cycles Dispersal Stalled"}, #define PME_MONT_DTLB_INSERTS_HPW 227 { "DTLB_INSERTS_HPW", {0x8c9}, 0xfff0, 4, {0xffff0000}, "Hardware Page Walker Installs to DTLB"}, #define PME_MONT_ENCBR_MISPRED_DETAIL_ALL_ALL_PRED 228 { "ENCBR_MISPRED_DETAIL_ALL_ALL_PRED", {0x63}, 0xfff0, 3, {0xffff0003}, "Number of Encoded Branches Retired -- All encoded branches regardless of prediction result"}, #define PME_MONT_ENCBR_MISPRED_DETAIL_ALL_CORRECT_PRED 229 { "ENCBR_MISPRED_DETAIL_ALL_CORRECT_PRED", {0x10063}, 0xfff0, 3, {0xffff0003}, "Number of Encoded Branches Retired -- All encoded branches, correctly predicted branches (outcome and target)"}, #define PME_MONT_ENCBR_MISPRED_DETAIL_ALL_WRONG_PATH 230 { "ENCBR_MISPRED_DETAIL_ALL_WRONG_PATH", {0x20063}, 0xfff0, 3, {0xffff0003}, "Number of Encoded Branches Retired -- All encoded branches, mispredicted branches due to wrong branch direction"}, #define PME_MONT_ENCBR_MISPRED_DETAIL_ALL_WRONG_TARGET 231 { "ENCBR_MISPRED_DETAIL_ALL_WRONG_TARGET", {0x30063}, 0xfff0, 3, {0xffff0003}, "Number of Encoded Branches Retired -- All encoded branches, mispredicted branches due to wrong target for taken branches"}, #define PME_MONT_ENCBR_MISPRED_DETAIL_ALL2_ALL_PRED 232 { "ENCBR_MISPRED_DETAIL_ALL2_ALL_PRED", {0xc0063}, 0xfff0, 3, {0xffff0003}, "Number of Encoded Branches Retired -- Only non-return indirect branches, regardless of prediction result"}, #define PME_MONT_ENCBR_MISPRED_DETAIL_ALL2_CORRECT_PRED 233 { "ENCBR_MISPRED_DETAIL_ALL2_CORRECT_PRED", {0xd0063}, 0xfff0, 3, {0xffff0003}, "Number of Encoded Branches Retired -- Only non-return indirect branches, correctly predicted branches (outcome and target)"}, #define PME_MONT_ENCBR_MISPRED_DETAIL_ALL2_WRONG_PATH 234 { "ENCBR_MISPRED_DETAIL_ALL2_WRONG_PATH", {0xe0063}, 0xfff0, 3, {0xffff0003}, "Number of Encoded Branches Retired -- Only non-return indirect branches, mispredicted branches due to wrong branch direction"}, #define PME_MONT_ENCBR_MISPRED_DETAIL_ALL2_WRONG_TARGET 235 { "ENCBR_MISPRED_DETAIL_ALL2_WRONG_TARGET", {0xf0063}, 0xfff0, 3, {0xffff0003}, "Number of Encoded Branches Retired -- Only non-return indirect branches, mispredicted branches due to wrong target for taken branches"}, #define PME_MONT_ENCBR_MISPRED_DETAIL_OVERSUB_ALL_PRED 236 { "ENCBR_MISPRED_DETAIL_OVERSUB_ALL_PRED", {0x80063}, 0xfff0, 3, {0xffff0003}, "Number of Encoded Branches Retired -- Only return type branches, regardless of prediction result"}, #define PME_MONT_ENCBR_MISPRED_DETAIL_OVERSUB_CORRECT_PRED 237 { "ENCBR_MISPRED_DETAIL_OVERSUB_CORRECT_PRED", {0x90063}, 0xfff0, 3, {0xffff0003}, "Number of Encoded Branches Retired -- Only return type branches, correctly predicted branches (outcome and target)"}, #define PME_MONT_ENCBR_MISPRED_DETAIL_OVERSUB_WRONG_PATH 238 { "ENCBR_MISPRED_DETAIL_OVERSUB_WRONG_PATH", {0xa0063}, 0xfff0, 3, {0xffff0003}, "Number of Encoded Branches Retired -- Only return type branches, mispredicted branches due to wrong branch direction"}, #define PME_MONT_ENCBR_MISPRED_DETAIL_OVERSUB_WRONG_TARGET 239 { "ENCBR_MISPRED_DETAIL_OVERSUB_WRONG_TARGET", {0xb0063}, 0xfff0, 3, {0xffff0003}, "Number of Encoded Branches Retired -- Only return type branches, mispredicted branches due to wrong target for taken branches"}, #define PME_MONT_ER_BKSNP_ME_ACCEPTED 240 { "ER_BKSNP_ME_ACCEPTED", {0x10bb}, 0x03f0, 2, {0xffff0000}, "Backsnoop Me Accepted"}, #define PME_MONT_ER_BRQ_LIVE_REQ_HI 241 { "ER_BRQ_LIVE_REQ_HI", {0x10b8}, 0x03f0, 2, {0xffff0000}, "BRQ Live Requests (upper 2 bits)"}, #define PME_MONT_ER_BRQ_LIVE_REQ_LO 242 { "ER_BRQ_LIVE_REQ_LO", {0x10b9}, 0x03f0, 7, {0xffff0000}, "BRQ Live Requests (lower 3 bits)"}, #define PME_MONT_ER_BRQ_REQ_INSERTED 243 { "ER_BRQ_REQ_INSERTED", {0x8ba}, 0x03f0, 1, {0xffff0000}, "BRQ Requests Inserted"}, #define PME_MONT_ER_MEM_READ_OUT_HI 244 { "ER_MEM_READ_OUT_HI", {0x8b4}, 0x03f0, 2, {0xffff0000}, "Outstanding Memory Read Transactions (upper 2 bits)"}, #define PME_MONT_ER_MEM_READ_OUT_LO 245 { "ER_MEM_READ_OUT_LO", {0x8b5}, 0x03f0, 7, {0xffff0000}, "Outstanding Memory Read Transactions (lower 3 bits)"}, #define PME_MONT_ER_REJECT_ALL_L1D_REQ 246 { "ER_REJECT_ALL_L1D_REQ", {0x10bd}, 0x03f0, 1, {0xffff0000}, "Reject All L1D Requests"}, #define PME_MONT_ER_REJECT_ALL_L1I_REQ 247 { "ER_REJECT_ALL_L1I_REQ", {0x10be}, 0x03f0, 1, {0xffff0000}, "Reject All L1I Requests"}, #define PME_MONT_ER_REJECT_ALL_L1_REQ 248 { "ER_REJECT_ALL_L1_REQ", {0x10bc}, 0x03f0, 1, {0xffff0000}, "Reject All L1 Requests"}, #define PME_MONT_ER_SNOOPQ_REQ_HI 249 { "ER_SNOOPQ_REQ_HI", {0x10b6}, 0x03f0, 2, {0xffff0000}, "Outstanding Snoops (upper bit)"}, #define PME_MONT_ER_SNOOPQ_REQ_LO 250 { "ER_SNOOPQ_REQ_LO", {0x10b7}, 0x03f0, 7, {0xffff0000}, "Outstanding Snoops (lower 3 bits)"}, #define PME_MONT_ETB_EVENT 251 { "ETB_EVENT", {0x111}, 0xfff0, 1, {0xffff0003}, "Execution Trace Buffer Event Captured"}, #define PME_MONT_FE_BUBBLE_ALL 252 { "FE_BUBBLE_ALL", {0x71}, 0xfff0, 1, {0xffff0000}, "Bubbles Seen by FE -- count regardless of cause"}, #define PME_MONT_FE_BUBBLE_ALLBUT_FEFLUSH_BUBBLE 253 { "FE_BUBBLE_ALLBUT_FEFLUSH_BUBBLE", {0xb0071}, 0xfff0, 1, {0xffff0000}, "Bubbles Seen by FE -- ALL except FEFLUSH and BUBBLE"}, #define PME_MONT_FE_BUBBLE_ALLBUT_IBFULL 254 { "FE_BUBBLE_ALLBUT_IBFULL", {0xc0071}, 0xfff0, 1, {0xffff0000}, "Bubbles Seen by FE -- ALL except IBFULl"}, #define PME_MONT_FE_BUBBLE_BRANCH 255 { "FE_BUBBLE_BRANCH", {0x90071}, 0xfff0, 1, {0xffff0000}, "Bubbles Seen by FE -- only if caused by any of 4 branch recirculates"}, #define PME_MONT_FE_BUBBLE_BUBBLE 256 { "FE_BUBBLE_BUBBLE", {0xd0071}, 0xfff0, 1, {0xffff0000}, "Bubbles Seen by FE -- only if caused by branch bubble stall"}, #define PME_MONT_FE_BUBBLE_FEFLUSH 257 { "FE_BUBBLE_FEFLUSH", {0x10071}, 0xfff0, 1, {0xffff0000}, "Bubbles Seen by FE -- only if caused by a front-end flush"}, #define PME_MONT_FE_BUBBLE_FILL_RECIRC 258 { "FE_BUBBLE_FILL_RECIRC", {0x80071}, 0xfff0, 1, {0xffff0000}, "Bubbles Seen by FE -- only if caused by a recirculate for a cache line fill operation"}, #define PME_MONT_FE_BUBBLE_GROUP1 259 { "FE_BUBBLE_GROUP1", {0x30071}, 0xfff0, 1, {0xffff0000}, "Bubbles Seen by FE -- BUBBLE or BRANCH"}, #define PME_MONT_FE_BUBBLE_GROUP2 260 { "FE_BUBBLE_GROUP2", {0x40071}, 0xfff0, 1, {0xffff0000}, "Bubbles Seen by FE -- IMISS or TLBMISS"}, #define PME_MONT_FE_BUBBLE_GROUP3 261 { "FE_BUBBLE_GROUP3", {0xa0071}, 0xfff0, 1, {0xffff0000}, "Bubbles Seen by FE -- FILL_RECIRC or BRANCH"}, #define PME_MONT_FE_BUBBLE_IBFULL 262 { "FE_BUBBLE_IBFULL", {0x50071}, 0xfff0, 1, {0xffff0000}, "Bubbles Seen by FE -- only if caused by instruction buffer full stall"}, #define PME_MONT_FE_BUBBLE_IMISS 263 { "FE_BUBBLE_IMISS", {0x60071}, 0xfff0, 1, {0xffff0000}, "Bubbles Seen by FE -- only if caused by instruction cache miss stall"}, #define PME_MONT_FE_BUBBLE_TLBMISS 264 { "FE_BUBBLE_TLBMISS", {0x70071}, 0xfff0, 1, {0xffff0000}, "Bubbles Seen by FE -- only if caused by TLB stall"}, #define PME_MONT_FE_LOST_BW_ALL 265 { "FE_LOST_BW_ALL", {0x70}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles at the Entrance to IB -- count regardless of cause"}, #define PME_MONT_FE_LOST_BW_BI 266 { "FE_LOST_BW_BI", {0x90070}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles at the Entrance to IB -- only if caused by branch initialization stall"}, #define PME_MONT_FE_LOST_BW_BRQ 267 { "FE_LOST_BW_BRQ", {0xa0070}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles at the Entrance to IB -- only if caused by branch retirement queue stall"}, #define PME_MONT_FE_LOST_BW_BR_ILOCK 268 { "FE_LOST_BW_BR_ILOCK", {0xc0070}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles at the Entrance to IB -- only if caused by branch interlock stall"}, #define PME_MONT_FE_LOST_BW_BUBBLE 269 { "FE_LOST_BW_BUBBLE", {0xd0070}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles at the Entrance to IB -- only if caused by branch resteer bubble stall"}, #define PME_MONT_FE_LOST_BW_FEFLUSH 270 { "FE_LOST_BW_FEFLUSH", {0x10070}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles at the Entrance to IB -- only if caused by a front-end flush"}, #define PME_MONT_FE_LOST_BW_FILL_RECIRC 271 { "FE_LOST_BW_FILL_RECIRC", {0x80070}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles at the Entrance to IB -- only if caused by a recirculate for a cache line fill operation"}, #define PME_MONT_FE_LOST_BW_IBFULL 272 { "FE_LOST_BW_IBFULL", {0x50070}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles at the Entrance to IB -- only if caused by instruction buffer full stall"}, #define PME_MONT_FE_LOST_BW_IMISS 273 { "FE_LOST_BW_IMISS", {0x60070}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles at the Entrance to IB -- only if caused by instruction cache miss stall"}, #define PME_MONT_FE_LOST_BW_PLP 274 { "FE_LOST_BW_PLP", {0xb0070}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles at the Entrance to IB -- only if caused by perfect loop prediction stall"}, #define PME_MONT_FE_LOST_BW_TLBMISS 275 { "FE_LOST_BW_TLBMISS", {0x70070}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles at the Entrance to IB -- only if caused by TLB stall"}, #define PME_MONT_FE_LOST_BW_UNREACHED 276 { "FE_LOST_BW_UNREACHED", {0x40070}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles at the Entrance to IB -- only if caused by unreachable bundle"}, #define PME_MONT_FP_FAILED_FCHKF 277 { "FP_FAILED_FCHKF", {0x6}, 0xfff0, 1, {0xffff0001}, "Failed fchkf"}, #define PME_MONT_FP_FALSE_SIRSTALL 278 { "FP_FALSE_SIRSTALL", {0x5}, 0xfff0, 1, {0xffff0001}, "SIR Stall Without a Trap"}, #define PME_MONT_FP_FLUSH_TO_ZERO_FTZ_POSS 279 { "FP_FLUSH_TO_ZERO_FTZ_POSS", {0x1000b}, 0xfff0, 2, {0xffff0001}, "FP Result Flushed to Zero -- "}, #define PME_MONT_FP_FLUSH_TO_ZERO_FTZ_REAL 280 { "FP_FLUSH_TO_ZERO_FTZ_REAL", {0xb}, 0xfff0, 2, {0xffff0001}, "FP Result Flushed to Zero -- Times FTZ"}, #define PME_MONT_FP_OPS_RETIRED 281 { "FP_OPS_RETIRED", {0x9}, 0xfff0, 6, {0xffff0001}, "Retired FP Operations"}, #define PME_MONT_FP_TRUE_SIRSTALL 282 { "FP_TRUE_SIRSTALL", {0x3}, 0xfff0, 1, {0xffff0001}, "SIR stall asserted and leads to a trap"}, #define PME_MONT_HPW_DATA_REFERENCES 283 { "HPW_DATA_REFERENCES", {0x2d}, 0xfff0, 4, {0xffff0000}, "Data Memory References to VHPT"}, #define PME_MONT_IA64_INST_RETIRED_THIS 284 { "IA64_INST_RETIRED_THIS", {0x8}, 0xfff0, 6, {0xffff0003}, "Retired IA-64 Instructions -- Retired IA-64 Instructions"}, #define PME_MONT_IA64_TAGGED_INST_RETIRED_IBRP0_PMC32_33 285 { "IA64_TAGGED_INST_RETIRED_IBRP0_PMC32_33", {0x8}, 0xfff0, 6, {0xffff0003}, "Retired Tagged Instructions -- Instruction tagged by Instruction Breakpoint Pair 0 and the opcode matcher pair PMC32 and PMC33."}, #define PME_MONT_IA64_TAGGED_INST_RETIRED_IBRP1_PMC34_35 286 { "IA64_TAGGED_INST_RETIRED_IBRP1_PMC34_35", {0x10008}, 0xfff0, 6, {0xffff0003}, "Retired Tagged Instructions -- Instruction tagged by Instruction Breakpoint Pair 1 and the opcode matcher pair PMC34 and PMC35."}, #define PME_MONT_IA64_TAGGED_INST_RETIRED_IBRP2_PMC32_33 287 { "IA64_TAGGED_INST_RETIRED_IBRP2_PMC32_33", {0x20008}, 0xfff0, 6, {0xffff0003}, "Retired Tagged Instructions -- Instruction tagged by Instruction Breakpoint Pair 2 and the opcode matcher pair PMC32 and PMC33."}, #define PME_MONT_IA64_TAGGED_INST_RETIRED_IBRP3_PMC34_35 288 { "IA64_TAGGED_INST_RETIRED_IBRP3_PMC34_35", {0x30008}, 0xfff0, 6, {0xffff0003}, "Retired Tagged Instructions -- Instruction tagged by Instruction Breakpoint Pair 3 and the opcode matcher pair PMC34 and PMC35."}, #define PME_MONT_IDEAL_BE_LOST_BW_DUE_TO_FE_ALL 289 { "IDEAL_BE_LOST_BW_DUE_TO_FE_ALL", {0x73}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles at the Exit from IB -- count regardless of cause"}, #define PME_MONT_IDEAL_BE_LOST_BW_DUE_TO_FE_BI 290 { "IDEAL_BE_LOST_BW_DUE_TO_FE_BI", {0x90073}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles at the Exit from IB -- only if caused by branch initialization stall"}, #define PME_MONT_IDEAL_BE_LOST_BW_DUE_TO_FE_BRQ 291 { "IDEAL_BE_LOST_BW_DUE_TO_FE_BRQ", {0xa0073}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles at the Exit from IB -- only if caused by branch retirement queue stall"}, #define PME_MONT_IDEAL_BE_LOST_BW_DUE_TO_FE_BR_ILOCK 292 { "IDEAL_BE_LOST_BW_DUE_TO_FE_BR_ILOCK", {0xc0073}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles at the Exit from IB -- only if caused by branch interlock stall"}, #define PME_MONT_IDEAL_BE_LOST_BW_DUE_TO_FE_BUBBLE 293 { "IDEAL_BE_LOST_BW_DUE_TO_FE_BUBBLE", {0xd0073}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles at the Exit from IB -- only if caused by branch resteer bubble stall"}, #define PME_MONT_IDEAL_BE_LOST_BW_DUE_TO_FE_FEFLUSH 294 { "IDEAL_BE_LOST_BW_DUE_TO_FE_FEFLUSH", {0x10073}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles at the Exit from IB -- only if caused by a front-end flush"}, #define PME_MONT_IDEAL_BE_LOST_BW_DUE_TO_FE_FILL_RECIRC 295 { "IDEAL_BE_LOST_BW_DUE_TO_FE_FILL_RECIRC", {0x80073}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles at the Exit from IB -- only if caused by a recirculate for a cache line fill operation"}, #define PME_MONT_IDEAL_BE_LOST_BW_DUE_TO_FE_IBFULL 296 { "IDEAL_BE_LOST_BW_DUE_TO_FE_IBFULL", {0x50073}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles at the Exit from IB -- (* meaningless for this event *)"}, #define PME_MONT_IDEAL_BE_LOST_BW_DUE_TO_FE_IMISS 297 { "IDEAL_BE_LOST_BW_DUE_TO_FE_IMISS", {0x60073}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles at the Exit from IB -- only if caused by instruction cache miss stall"}, #define PME_MONT_IDEAL_BE_LOST_BW_DUE_TO_FE_PLP 298 { "IDEAL_BE_LOST_BW_DUE_TO_FE_PLP", {0xb0073}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles at the Exit from IB -- only if caused by perfect loop prediction stall"}, #define PME_MONT_IDEAL_BE_LOST_BW_DUE_TO_FE_TLBMISS 299 { "IDEAL_BE_LOST_BW_DUE_TO_FE_TLBMISS", {0x70073}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles at the Exit from IB -- only if caused by TLB stall"}, #define PME_MONT_IDEAL_BE_LOST_BW_DUE_TO_FE_UNREACHED 300 { "IDEAL_BE_LOST_BW_DUE_TO_FE_UNREACHED", {0x40073}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles at the Exit from IB -- only if caused by unreachable bundle"}, #define PME_MONT_INST_CHKA_LDC_ALAT_ALL 301 { "INST_CHKA_LDC_ALAT_ALL", {0x30056}, 0xfff0, 2, {0xffff0007}, "Retired chk.a and ld.c Instructions -- both integer and floating point instructions"}, #define PME_MONT_INST_CHKA_LDC_ALAT_FP 302 { "INST_CHKA_LDC_ALAT_FP", {0x20056}, 0xfff0, 2, {0xffff0007}, "Retired chk.a and ld.c Instructions -- only floating point instructions"}, #define PME_MONT_INST_CHKA_LDC_ALAT_INT 303 { "INST_CHKA_LDC_ALAT_INT", {0x10056}, 0xfff0, 2, {0xffff0007}, "Retired chk.a and ld.c Instructions -- only integer instructions"}, #define PME_MONT_INST_DISPERSED 304 { "INST_DISPERSED", {0x4d}, 0xfff0, 6, {0xffff0001}, "Syllables Dispersed from REN to REG stage"}, #define PME_MONT_INST_FAILED_CHKA_LDC_ALAT_ALL 305 { "INST_FAILED_CHKA_LDC_ALAT_ALL", {0x30057}, 0xfff0, 1, {0xffff0007}, "Failed chk.a and ld.c Instructions -- both integer and floating point instructions"}, #define PME_MONT_INST_FAILED_CHKA_LDC_ALAT_FP 306 { "INST_FAILED_CHKA_LDC_ALAT_FP", {0x20057}, 0xfff0, 1, {0xffff0007}, "Failed chk.a and ld.c Instructions -- only floating point instructions"}, #define PME_MONT_INST_FAILED_CHKA_LDC_ALAT_INT 307 { "INST_FAILED_CHKA_LDC_ALAT_INT", {0x10057}, 0xfff0, 1, {0xffff0007}, "Failed chk.a and ld.c Instructions -- only integer instructions"}, #define PME_MONT_INST_FAILED_CHKS_RETIRED_ALL 308 { "INST_FAILED_CHKS_RETIRED_ALL", {0x30055}, 0xfff0, 1, {0xffff0000}, "Failed chk.s Instructions -- both integer and floating point instructions"}, #define PME_MONT_INST_FAILED_CHKS_RETIRED_FP 309 { "INST_FAILED_CHKS_RETIRED_FP", {0x20055}, 0xfff0, 1, {0xffff0000}, "Failed chk.s Instructions -- only floating point instructions"}, #define PME_MONT_INST_FAILED_CHKS_RETIRED_INT 310 { "INST_FAILED_CHKS_RETIRED_INT", {0x10055}, 0xfff0, 1, {0xffff0000}, "Failed chk.s Instructions -- only integer instructions"}, #define PME_MONT_ISB_BUNPAIRS_IN 311 { "ISB_BUNPAIRS_IN", {0x46}, 0xfff0, 1, {0xffff0001}, "Bundle Pairs Written from L2I into FE"}, #define PME_MONT_ITLB_MISSES_FETCH_ALL 312 { "ITLB_MISSES_FETCH_ALL", {0x30047}, 0xfff0, 1, {0xffff0001}, "ITLB Misses Demand Fetch -- All tlb misses will be counted. Note that this is not equal to sum of the L1ITLB and L2ITLB umasks because any access could be a miss in L1ITLB and L2ITLB."}, #define PME_MONT_ITLB_MISSES_FETCH_L1ITLB 313 { "ITLB_MISSES_FETCH_L1ITLB", {0x10047}, 0xfff0, 1, {0xffff0001}, "ITLB Misses Demand Fetch -- All misses in L1ITLB will be counted. even if L1ITLB is not updated for an access (Uncacheable/nat page/not present page/faulting/some flushed), it will be counted here."}, #define PME_MONT_ITLB_MISSES_FETCH_L2ITLB 314 { "ITLB_MISSES_FETCH_L2ITLB", {0x20047}, 0xfff0, 1, {0xffff0001}, "ITLB Misses Demand Fetch -- All misses in L1ITLB which also missed in L2ITLB will be counted."}, #define PME_MONT_L1DTLB_TRANSFER 315 { "L1DTLB_TRANSFER", {0xc0}, 0xfff0, 1, {0x5010007}, "L1DTLB Misses That Hit in the L2DTLB for Accesses Counted in L1D_READS"}, #define PME_MONT_L1D_READS_SET0 316 { "L1D_READS_SET0", {0xc2}, 0xfff0, 2, {0x5010007}, "L1 Data Cache Reads"}, #define PME_MONT_L1D_READS_SET1 317 { "L1D_READS_SET1", {0xc4}, 0xfff0, 2, {0x5110007}, "L1 Data Cache Reads"}, #define PME_MONT_L1D_READ_MISSES_ALL 318 { "L1D_READ_MISSES_ALL", {0xc7}, 0xfff0, 2, {0x5110007}, "L1 Data Cache Read Misses -- all L1D read misses will be counted."}, #define PME_MONT_L1D_READ_MISSES_RSE_FILL 319 { "L1D_READ_MISSES_RSE_FILL", {0x100c7}, 0xfff0, 2, {0x5110007}, "L1 Data Cache Read Misses -- only L1D read misses caused by RSE fills will be counted"}, #define PME_MONT_L1ITLB_INSERTS_HPW 320 { "L1ITLB_INSERTS_HPW", {0x48}, 0xfff0, 1, {0xffff0001}, "L1ITLB Hardware Page Walker Inserts"}, #define PME_MONT_L1I_EAR_CACHE_LAT0 321 { "L1I_EAR_CACHE_LAT0", {0x400b43}, 0xfff0, 1, {0xffff0001}, "L1I EAR Cache -- > 0 Cycles (All L1 Misses)"}, #define PME_MONT_L1I_EAR_CACHE_LAT1024 322 { "L1I_EAR_CACHE_LAT1024", {0xc00b43}, 0xfff0, 1, {0xffff0001}, "L1I EAR Cache -- >= 1024 Cycles"}, #define PME_MONT_L1I_EAR_CACHE_LAT128 323 { "L1I_EAR_CACHE_LAT128", {0xf00b43}, 0xfff0, 1, {0xffff0001}, "L1I EAR Cache -- >= 128 Cycles"}, #define PME_MONT_L1I_EAR_CACHE_LAT16 324 { "L1I_EAR_CACHE_LAT16", {0xfc0b43}, 0xfff0, 1, {0xffff0001}, "L1I EAR Cache -- >= 16 Cycles"}, #define PME_MONT_L1I_EAR_CACHE_LAT256 325 { "L1I_EAR_CACHE_LAT256", {0xe00b43}, 0xfff0, 1, {0xffff0001}, "L1I EAR Cache -- >= 256 Cycles"}, #define PME_MONT_L1I_EAR_CACHE_LAT32 326 { "L1I_EAR_CACHE_LAT32", {0xf80b43}, 0xfff0, 1, {0xffff0001}, "L1I EAR Cache -- >= 32 Cycles"}, #define PME_MONT_L1I_EAR_CACHE_LAT4 327 { "L1I_EAR_CACHE_LAT4", {0xff0b43}, 0xfff0, 1, {0xffff0001}, "L1I EAR Cache -- >= 4 Cycles"}, #define PME_MONT_L1I_EAR_CACHE_LAT4096 328 { "L1I_EAR_CACHE_LAT4096", {0x800b43}, 0xfff0, 1, {0xffff0001}, "L1I EAR Cache -- >= 4096 Cycles"}, #define PME_MONT_L1I_EAR_CACHE_LAT8 329 { "L1I_EAR_CACHE_LAT8", {0xfe0b43}, 0xfff0, 1, {0xffff0001}, "L1I EAR Cache -- >= 8 Cycles"}, #define PME_MONT_L1I_EAR_CACHE_RAB 330 { "L1I_EAR_CACHE_RAB", {0xb43}, 0xfff0, 1, {0xffff0001}, "L1I EAR Cache -- RAB HIT"}, #define PME_MONT_L1I_EAR_EVENTS 331 { "L1I_EAR_EVENTS", {0x843}, 0xfff0, 1, {0xffff0001}, "Instruction EAR Events"}, #define PME_MONT_L1I_EAR_TLB_ALL 332 { "L1I_EAR_TLB_ALL", {0x70a43}, 0xfff0, 1, {0xffff0001}, "L1I EAR TLB -- All L1 ITLB Misses"}, #define PME_MONT_L1I_EAR_TLB_FAULT 333 { "L1I_EAR_TLB_FAULT", {0x40a43}, 0xfff0, 1, {0xffff0001}, "L1I EAR TLB -- ITLB Misses which produced a fault"}, #define PME_MONT_L1I_EAR_TLB_L2TLB 334 { "L1I_EAR_TLB_L2TLB", {0x10a43}, 0xfff0, 1, {0xffff0001}, "L1I EAR TLB -- L1 ITLB Misses which hit L2 ITLB"}, #define PME_MONT_L1I_EAR_TLB_L2TLB_OR_FAULT 335 { "L1I_EAR_TLB_L2TLB_OR_FAULT", {0x50a43}, 0xfff0, 1, {0xffff0001}, "L1I EAR TLB -- L1 ITLB Misses which hit L2 ITLB or produce a software fault"}, #define PME_MONT_L1I_EAR_TLB_L2TLB_OR_VHPT 336 { "L1I_EAR_TLB_L2TLB_OR_VHPT", {0x30a43}, 0xfff0, 1, {0xffff0001}, "L1I EAR TLB -- L1 ITLB Misses which hit L2 ITLB or VHPT"}, #define PME_MONT_L1I_EAR_TLB_VHPT 337 { "L1I_EAR_TLB_VHPT", {0x20a43}, 0xfff0, 1, {0xffff0001}, "L1I EAR TLB -- L1 ITLB Misses which hit VHPT"}, #define PME_MONT_L1I_EAR_TLB_VHPT_OR_FAULT 338 { "L1I_EAR_TLB_VHPT_OR_FAULT", {0x60a43}, 0xfff0, 1, {0xffff0001}, "L1I EAR TLB -- L1 ITLB Misses which hit VHPT or produce a software fault"}, #define PME_MONT_L1I_FETCH_ISB_HIT 339 { "L1I_FETCH_ISB_HIT", {0x66}, 0xfff0, 1, {0xffff0001}, "\"Just-In-Time\" Instruction Fetch Hitting in and Being Bypassed from ISB"}, #define PME_MONT_L1I_FETCH_RAB_HIT 340 { "L1I_FETCH_RAB_HIT", {0x65}, 0xfff0, 1, {0xffff0001}, "Instruction Fetch Hitting in RAB"}, #define PME_MONT_L1I_FILLS 341 { "L1I_FILLS", {0x841}, 0xfff0, 1, {0xffff0001}, "L1 Instruction Cache Fills"}, #define PME_MONT_L1I_PREFETCHES 342 { "L1I_PREFETCHES", {0x44}, 0xfff0, 1, {0xffff0001}, "L1 Instruction Prefetch Requests"}, #define PME_MONT_L1I_PREFETCH_STALL_ALL 343 { "L1I_PREFETCH_STALL_ALL", {0x30067}, 0xfff0, 1, {0xffff0000}, "Prefetch Pipeline Stalls -- Number of clocks prefetch pipeline is stalled"}, #define PME_MONT_L1I_PREFETCH_STALL_FLOW 344 { "L1I_PREFETCH_STALL_FLOW", {0x20067}, 0xfff0, 1, {0xffff0000}, "Prefetch Pipeline Stalls -- Asserted when the streaming prefetcher is working close to the instructions being fetched for demand reads, and is not asserted when the streaming prefetcher is ranging way ahead of the demand reads."}, #define PME_MONT_L1I_PURGE 345 { "L1I_PURGE", {0x104b}, 0xfff0, 1, {0xffff0001}, "L1ITLB Purges Handled by L1I"}, #define PME_MONT_L1I_PVAB_OVERFLOW 346 { "L1I_PVAB_OVERFLOW", {0x69}, 0xfff0, 1, {0xffff0000}, "PVAB Overflow"}, #define PME_MONT_L1I_RAB_ALMOST_FULL 347 { "L1I_RAB_ALMOST_FULL", {0x1064}, 0xfff0, 1, {0xffff0000}, "Is RAB Almost Full?"}, #define PME_MONT_L1I_RAB_FULL 348 { "L1I_RAB_FULL", {0x1060}, 0xfff0, 1, {0xffff0000}, "Is RAB Full?"}, #define PME_MONT_L1I_READS 349 { "L1I_READS", {0x40}, 0xfff0, 1, {0xffff0001}, "L1 Instruction Cache Reads"}, #define PME_MONT_L1I_SNOOP 350 { "L1I_SNOOP", {0x104a}, 0xfff0, 1, {0xffff0007}, "Snoop Requests Handled by L1I"}, #define PME_MONT_L1I_STRM_PREFETCHES 351 { "L1I_STRM_PREFETCHES", {0x5f}, 0xfff0, 1, {0xffff0001}, "L1 Instruction Cache Line Prefetch Requests"}, #define PME_MONT_L2DTLB_MISSES 352 { "L2DTLB_MISSES", {0xc1}, 0xfff0, 4, {0x5010007}, "L2DTLB Misses"}, #define PME_MONT_L2D_BAD_LINES_SELECTED_ANY 353 { "L2D_BAD_LINES_SELECTED_ANY", {0x8ec}, 0xfff0, 4, {0x4520007}, "Valid Line Replaced When Invalid Line Is Available -- Valid line replaced when invalid line is available"}, #define PME_MONT_L2D_BYPASS_L2_DATA1 354 { "L2D_BYPASS_L2_DATA1", {0x8e4}, 0xfff0, 1, {0x4120007}, "Count L2D Bypasses -- Count only L2D data bypasses (L1D to L2A)"}, #define PME_MONT_L2D_BYPASS_L2_DATA2 355 { "L2D_BYPASS_L2_DATA2", {0x108e4}, 0xfff0, 1, {0x4120007}, "Count L2D Bypasses -- Count only L2D data bypasses (L1W to L2I)"}, #define PME_MONT_L2D_BYPASS_L3_DATA1 356 { "L2D_BYPASS_L3_DATA1", {0x208e4}, 0xfff0, 1, {0x4120007}, "Count L2D Bypasses -- Count only L3 data bypasses (L1D to L2A)"}, #define PME_MONT_L2D_FILLB_FULL_THIS 357 { "L2D_FILLB_FULL_THIS", {0x8f1}, 0xfff0, 1, {0x4720000}, "L2D Fill Buffer Is Full -- L2D Fill buffer is full"}, #define PME_MONT_L2D_FILL_MESI_STATE_E 358 { "L2D_FILL_MESI_STATE_E", {0x108f2}, 0xfff0, 1, {0x4820000}, "L2D Cache Fills with MESI state -- "}, #define PME_MONT_L2D_FILL_MESI_STATE_I 359 { "L2D_FILL_MESI_STATE_I", {0x308f2}, 0xfff0, 1, {0x4820000}, "L2D Cache Fills with MESI state -- "}, #define PME_MONT_L2D_FILL_MESI_STATE_M 360 { "L2D_FILL_MESI_STATE_M", {0x8f2}, 0xfff0, 1, {0x4820000}, "L2D Cache Fills with MESI state -- "}, #define PME_MONT_L2D_FILL_MESI_STATE_P 361 { "L2D_FILL_MESI_STATE_P", {0x408f2}, 0xfff0, 1, {0x4820000}, "L2D Cache Fills with MESI state -- "}, #define PME_MONT_L2D_FILL_MESI_STATE_S 362 { "L2D_FILL_MESI_STATE_S", {0x208f2}, 0xfff0, 1, {0x4820000}, "L2D Cache Fills with MESI state -- "}, #define PME_MONT_L2D_FORCE_RECIRC_FILL_HIT 363 { "L2D_FORCE_RECIRC_FILL_HIT", {0x808ea}, 0xfff0, 4, {0x4420007}, "Forced Recirculates -- Count only those caused by an L2D miss which hit in the fill buffer."}, #define PME_MONT_L2D_FORCE_RECIRC_FRC_RECIRC 364 { "L2D_FORCE_RECIRC_FRC_RECIRC", {0x908ea}, 0xfff0, 4, {0x4420007}, "Forced Recirculates -- Caused by an L2D miss when a force recirculate already existed in the Ozq."}, #define PME_MONT_L2D_FORCE_RECIRC_L1W 365 { "L2D_FORCE_RECIRC_L1W", {0xc08ea}, 0xfff0, 4, {0x4420007}, "Forced Recirculates -- Count only those caused by a L2D miss one cycle ahead of the current op."}, #define PME_MONT_L2D_FORCE_RECIRC_LIMBO 366 { "L2D_FORCE_RECIRC_LIMBO", {0x108ea}, 0xfff0, 4, {0x4420007}, "Forced Recirculates -- Count operations that went into the LIMBO Ozq state. This state is entered when the the op sees a FILL_HIT or OZQ_MISS event."}, #define PME_MONT_L2D_FORCE_RECIRC_OZQ_MISS 367 { "L2D_FORCE_RECIRC_OZQ_MISS", {0xb08ea}, 0xfff0, 4, {0x4420007}, "Forced Recirculates -- Caused by an L2D miss when an L2D miss was already in the OZQ."}, #define PME_MONT_L2D_FORCE_RECIRC_RECIRC 368 { "L2D_FORCE_RECIRC_RECIRC", {0x8ea}, 0xfff0, 4, {0x4420007}, "Forced Recirculates -- Counts inserts into OzQ due to a recirculate. The recirculate due to secondary misses or various other conflicts"}, #define PME_MONT_L2D_FORCE_RECIRC_SAME_INDEX 369 { "L2D_FORCE_RECIRC_SAME_INDEX", {0xa08ea}, 0xfff0, 4, {0x4420007}, "Forced Recirculates -- Caused by an L2D miss when a miss to the same index was in the same issue group."}, #define PME_MONT_L2D_FORCE_RECIRC_SECONDARY_ALL 370 { "L2D_FORCE_RECIRC_SECONDARY_ALL", {0xf08ea}, 0xfff0, 4, {0x4420007}, "Forced Recirculates -- CSaused by any L2D op that saw a miss to the same address in OZQ, L2 fill buffer, or one cycle ahead in the main pipeline."}, #define PME_MONT_L2D_FORCE_RECIRC_SECONDARY_READ 371 { "L2D_FORCE_RECIRC_SECONDARY_READ", {0xd08ea}, 0xfff0, 4, {0x4420007}, "Forced Recirculates -- Caused by L2D read op that saw a miss to the same address in OZQ, L2 fill buffer, or one cycle ahead in the main pipeline."}, #define PME_MONT_L2D_FORCE_RECIRC_SECONDARY_WRITE 372 { "L2D_FORCE_RECIRC_SECONDARY_WRITE", {0xe08ea}, 0xfff0, 4, {0x4420007}, "Forced Recirculates -- Caused by L2D write op that saw a miss to the same address in OZQ, L2 fill buffer, or one cycle ahead in the main pipeline."}, #define PME_MONT_L2D_FORCE_RECIRC_SNP_OR_L3 373 { "L2D_FORCE_RECIRC_SNP_OR_L3", {0x608ea}, 0xfff0, 4, {0x4420007}, "Forced Recirculates -- Count only those caused by a snoop or L3 issue."}, #define PME_MONT_L2D_FORCE_RECIRC_TAG_NOTOK 374 { "L2D_FORCE_RECIRC_TAG_NOTOK", {0x408ea}, 0xfff0, 4, {0x4420007}, "Forced Recirculates -- Count only those caused by L2D hits caused by in flight snoops, stores with a sibling miss to the same index, sibling probe to the same line or a pending mf.a instruction. This count can usually be ignored since its events are rare, unpredictable, and/or show up in one of the other events."}, #define PME_MONT_L2D_FORCE_RECIRC_TAG_OK 375 { "L2D_FORCE_RECIRC_TAG_OK", {0x708ea}, 0xfff0, 4, {0x4420007}, "Forced Recirculates -- Count operations that inserted to Ozq as a hit. Thus it was NOT forced to recirculate. Likely identical to L2D_INSERT_HITS."}, #define PME_MONT_L2D_FORCE_RECIRC_TRAN_PREF 376 { "L2D_FORCE_RECIRC_TRAN_PREF", {0x508ea}, 0xfff0, 4, {0x4420007}, "Forced Recirculates -- Count only those caused by L2D miss requests that transformed to prefetches"}, #define PME_MONT_L2D_INSERT_HITS 377 { "L2D_INSERT_HITS", {0x8b1}, 0xfff0, 4, {0xffff0007}, "Count Number of Times an Inserting Data Request Hit in the L2D."}, #define PME_MONT_L2D_INSERT_MISSES 378 { "L2D_INSERT_MISSES", {0x8b0}, 0xfff0, 4, {0xffff0007}, "Count Number of Times an Inserting Data Request Missed the L2D."}, #define PME_MONT_L2D_ISSUED_RECIRC_OZQ_ACC 379 { "L2D_ISSUED_RECIRC_OZQ_ACC", {0x8eb}, 0xfff0, 1, {0x4420007}, "Count Number of Times a Recirculate Issue Was Attempted and Not Preempted"}, #define PME_MONT_L2D_L3ACCESS_CANCEL_ANY 380 { "L2D_L3ACCESS_CANCEL_ANY", {0x208e8}, 0xfff0, 1, {0x4320007}, "L2D Access Cancelled by L2D -- count cancels due to any reason. This umask will count more than the sum of all the other umasks. It will count things that weren't committed accesses when they reached L1w, but the L2D attempted to bypass them to the L3 anyway (speculatively). This will include accesses made repeatedly while the main pipeline is stalled and the L1D is attempting to recirculate an access down the L1D pipeline. Thus, an access could get counted many times before it really does get bypassed to the L3. It is a measure of how many times we asserted a request to the L3 but didn't confirm it."}, #define PME_MONT_L2D_L3ACCESS_CANCEL_ER_REJECT 381 { "L2D_L3ACCESS_CANCEL_ER_REJECT", {0x308e8}, 0xfff0, 1, {0x4320007}, "L2D Access Cancelled by L2D -- Count only requests that were rejected by ER"}, #define PME_MONT_L2D_L3ACCESS_CANCEL_INV_L3_BYP 382 { "L2D_L3ACCESS_CANCEL_INV_L3_BYP", {0x8e8}, 0xfff0, 1, {0x4320007}, "L2D Access Cancelled by L2D -- L2D cancelled a bypass because it did not commit, or was not a valid opcode to bypass, or was not a true miss of L2D (either hit,recirc,or limbo)."}, #define PME_MONT_L2D_L3ACCESS_CANCEL_P2_COV_SNP_FILL_NOSNP 383 { "L2D_L3ACCESS_CANCEL_P2_COV_SNP_FILL_NOSNP", {0x608e8}, 0xfff0, 1, {0x4320007}, "L2D Access Cancelled by L2D -- A snoop and a fill to the same address reached the L2D within a 3 cycle window of each other or a snoop hit a nosnoops entry in Ozq."}, #define PME_MONT_L2D_L3ACCESS_CANCEL_P2_COV_SNP_TEM 384 { "L2D_L3ACCESS_CANCEL_P2_COV_SNP_TEM", {0x408e8}, 0xfff0, 1, {0x4320007}, "L2D Access Cancelled by L2D -- A snoop saw an L2D tag error and missed/"}, #define PME_MONT_L2D_L3ACCESS_CANCEL_P2_COV_SNP_VIC 385 { "L2D_L3ACCESS_CANCEL_P2_COV_SNP_VIC", {0x508e8}, 0xfff0, 1, {0x4320007}, "L2D Access Cancelled by L2D -- A snoop hit in the L1D victim buffer"}, #define PME_MONT_L2D_L3ACCESS_CANCEL_SPEC_L3_BYP 386 { "L2D_L3ACCESS_CANCEL_SPEC_L3_BYP", {0x108e8}, 0xfff0, 1, {0x4320007}, "L2D Access Cancelled by L2D -- L2D cancelled speculative L3 bypasses because it was not a WB memory attribute or it was an effective release."}, #define PME_MONT_L2D_L3ACCESS_CANCEL_TAIL_TRANS_DIS 387 { "L2D_L3ACCESS_CANCEL_TAIL_TRANS_DIS", {0x708e8}, 0xfff0, 1, {0x4320007}, "L2D Access Cancelled by L2D -- Count the number of cycles that either transform to prefetches or Ozq tail collapse have been dynamically disabled. This would indicate that memory contention has lead the L2D to throttle request to prevent livelock scenarios."}, #define PME_MONT_L2D_MISSES 388 { "L2D_MISSES", {0x8cb}, 0xfff0, 1, {0xffff0007}, "L2 Misses"}, #define PME_MONT_L2D_OPS_ISSUED_FP_LOAD 389 { "L2D_OPS_ISSUED_FP_LOAD", {0x108f0}, 0xfff0, 4, {0xffff0007}, "Operations Issued By L2D -- Count only valid floating-point loads"}, #define PME_MONT_L2D_OPS_ISSUED_INT_LOAD 390 { "L2D_OPS_ISSUED_INT_LOAD", {0x8f0}, 0xfff0, 4, {0xffff0007}, "Operations Issued By L2D -- Count only valid integer loads, including ld16."}, #define PME_MONT_L2D_OPS_ISSUED_LFETCH 391 { "L2D_OPS_ISSUED_LFETCH", {0x408f0}, 0xfff0, 4, {0xffff0007}, "Operations Issued By L2D -- Count only lfetch operations."}, #define PME_MONT_L2D_OPS_ISSUED_OTHER 392 { "L2D_OPS_ISSUED_OTHER", {0x508f0}, 0xfff0, 4, {0xffff0007}, "Operations Issued By L2D -- Count only valid non-load, no-store accesses that are not in any of the above sections."}, #define PME_MONT_L2D_OPS_ISSUED_RMW 393 { "L2D_OPS_ISSUED_RMW", {0x208f0}, 0xfff0, 4, {0xffff0007}, "Operations Issued By L2D -- Count only valid read_modify_write stores and semaphores including cmp8xchg16."}, #define PME_MONT_L2D_OPS_ISSUED_STORE 394 { "L2D_OPS_ISSUED_STORE", {0x308f0}, 0xfff0, 4, {0xffff0007}, "Operations Issued By L2D -- Count only valid non-read_modify_write stores, including st16."}, #define PME_MONT_L2D_OZDB_FULL_THIS 395 { "L2D_OZDB_FULL_THIS", {0x8e9}, 0xfff0, 1, {0x4320000}, "L2D OZ Data Buffer Is Full -- L2 OZ Data Buffer is full"}, #define PME_MONT_L2D_OZQ_ACQUIRE 396 { "L2D_OZQ_ACQUIRE", {0x8ef}, 0xfff0, 1, {0x4620000}, "Acquire Ordering Attribute Exists in L2D OZQ"}, #define PME_MONT_L2D_OZQ_CANCELS0_ACQ 397 { "L2D_OZQ_CANCELS0_ACQ", {0x608e0}, 0xfff0, 4, {0x4020007}, "L2D OZQ Cancels (Specific Reason Set 0) -- caused by an acquire somewhere in Ozq or ER."}, #define PME_MONT_L2D_OZQ_CANCELS0_BANK_CONF 398 { "L2D_OZQ_CANCELS0_BANK_CONF", {0x808e0}, 0xfff0, 4, {0x4020007}, "L2D OZQ Cancels (Specific Reason Set 0) -- a bypassed L2D hit operation had a bank conflict with an older sibling bypass or an older operation in the L2D pipeline."}, #define PME_MONT_L2D_OZQ_CANCELS0_CANC_L2M_TO_L2C_ST 399 { "L2D_OZQ_CANCELS0_CANC_L2M_TO_L2C_ST", {0x108e0}, 0xfff0, 4, {0x4020007}, "L2D OZQ Cancels (Specific Reason Set 0) -- caused by a canceled store in L2M,L2D or L2C. This is the combination of following subevents that were available separately in Itanium2: CANC_L2M_ST=caused by canceled store in L2M, CANC_L2D_ST=caused by canceled store in L2D, CANC_L2C_ST=caused by canceled store in L2C"}, #define PME_MONT_L2D_OZQ_CANCELS0_FILL_ST_CONF 400 { "L2D_OZQ_CANCELS0_FILL_ST_CONF", {0xe08e0}, 0xfff0, 4, {0x4020007}, "L2D OZQ Cancels (Specific Reason Set 0) -- an OZQ store conflicted with a returning L2D fill"}, #define PME_MONT_L2D_OZQ_CANCELS0_L2A_ST_MAT 401 { "L2D_OZQ_CANCELS0_L2A_ST_MAT", {0x208e0}, 0xfff0, 4, {0x4020007}, "L2D OZQ Cancels (Specific Reason Set 0) -- canceled due to an uncanceled store match in L2A"}, #define PME_MONT_L2D_OZQ_CANCELS0_L2C_ST_MAT 402 { "L2D_OZQ_CANCELS0_L2C_ST_MAT", {0x508e0}, 0xfff0, 4, {0x4020007}, "L2D OZQ Cancels (Specific Reason Set 0) -- canceled due to an uncanceled store match in L2C"}, #define PME_MONT_L2D_OZQ_CANCELS0_L2D_ST_MAT 403 { "L2D_OZQ_CANCELS0_L2D_ST_MAT", {0x408e0}, 0xfff0, 4, {0x4020007}, "L2D OZQ Cancels (Specific Reason Set 0) -- canceled due to an uncanceled store match in L2D"}, #define PME_MONT_L2D_OZQ_CANCELS0_L2M_ST_MAT 404 { "L2D_OZQ_CANCELS0_L2M_ST_MAT", {0x308e0}, 0xfff0, 4, {0x4020007}, "L2D OZQ Cancels (Specific Reason Set 0) -- canceled due to an uncanceled store match in L2M"}, #define PME_MONT_L2D_OZQ_CANCELS0_MISC_ORDER 405 { "L2D_OZQ_CANCELS0_MISC_ORDER", {0xd08e0}, 0xfff0, 4, {0x4020007}, "L2D OZQ Cancels (Specific Reason Set 0) -- a sync.i or mf.a . This is the combination of following subevents that were available separately in Itanium2: SYNC=caused by sync.i, MFA=a memory fence instruction"}, #define PME_MONT_L2D_OZQ_CANCELS0_OVER_SUB 406 { "L2D_OZQ_CANCELS0_OVER_SUB", {0xa08e0}, 0xfff0, 4, {0x4020007}, "L2D OZQ Cancels (Specific Reason Set 0) -- a high Ozq issue rate resulted in the L2D having to cancel due to hardware restrictions. This is the combination of following subevents that were available separately in Itanium2: OVER_SUB=oversubscription, L1DF_L2M=L1D fill in L2M"}, #define PME_MONT_L2D_OZQ_CANCELS0_OZDATA_CONF 407 { "L2D_OZQ_CANCELS0_OZDATA_CONF", {0xf08e0}, 0xfff0, 4, {0x4020007}, "L2D OZQ Cancels (Specific Reason Set 0) -- an OZQ operation that needed to read the OZQ data buffer conflicted with a fill return that needed to do the same."}, #define PME_MONT_L2D_OZQ_CANCELS0_OZQ_PREEMPT 408 { "L2D_OZQ_CANCELS0_OZQ_PREEMPT", {0xb08e0}, 0xfff0, 4, {0x4020007}, "L2D OZQ Cancels (Specific Reason Set 0) -- an L2D fill return conflicted with, and cancelled, an ozq request for various reasons. Formerly known as L1_FILL_CONF."}, #define PME_MONT_L2D_OZQ_CANCELS0_RECIRC 409 { "L2D_OZQ_CANCELS0_RECIRC", {0x8e0}, 0xfff0, 4, {0x4020007}, "L2D OZQ Cancels (Specific Reason Set 0) -- a recirculate was cancelled due h/w limitations on recirculate issue rate. This is the combination of following subevents that were available separately in Itanium2: RECIRC_OVER_SUB=caused by a recirculate oversubscription, DIDNT_RECIRC=caused because it did not recirculate, WEIRD=counts the cancels caused by attempted 5-cycle bypasses for non-aligned accesses and bypasses blocking recirculates for too long"}, #define PME_MONT_L2D_OZQ_CANCELS0_REL 410 { "L2D_OZQ_CANCELS0_REL", {0x708e0}, 0xfff0, 4, {0x4020007}, "L2D OZQ Cancels (Specific Reason Set 0) -- a release was cancelled due to some other operation"}, #define PME_MONT_L2D_OZQ_CANCELS0_SEMA 411 { "L2D_OZQ_CANCELS0_SEMA", {0x908e0}, 0xfff0, 4, {0x4020007}, "L2D OZQ Cancels (Specific Reason Set 0) -- a semaphore op was cancelled for various ordering or h/w restriction reasons. This is the combination of following subevents that were available separately in Itanium 2: SEM=a semaphore, CCV=a CCV"}, #define PME_MONT_L2D_OZQ_CANCELS0_WB_CONF 412 { "L2D_OZQ_CANCELS0_WB_CONF", {0xc08e0}, 0xfff0, 4, {0x4020007}, "L2D OZQ Cancels (Specific Reason Set 0) -- an OZQ request conflicted with an L2D data array read for a writeback. This is the combination of following subevents that were available separately in Itanium2: READ_WB_CONF=a write back conflict, ST_FILL_CONF=a store fill conflict"}, #define PME_MONT_L2D_OZQ_CANCELS1_ANY 413 { "L2D_OZQ_CANCELS1_ANY", {0x8e2}, 0xfff0, 4, {0x4020007}, "L2D OZQ Cancels (Late or Any) -- counts the total OZ Queue cancels"}, #define PME_MONT_L2D_OZQ_CANCELS1_LATE_BYP_EFFRELEASE 414 { "L2D_OZQ_CANCELS1_LATE_BYP_EFFRELEASE", {0x308e2}, 0xfff0, 4, {0x4020007}, "L2D OZQ Cancels (Late or Any) -- counts the late cancels caused by L1D to L2A bypass effective releases"}, #define PME_MONT_L2D_OZQ_CANCELS1_LATE_SPEC_BYP 415 { "L2D_OZQ_CANCELS1_LATE_SPEC_BYP", {0x108e2}, 0xfff0, 4, {0x4020007}, "L2D OZQ Cancels (Late or Any) -- counts the late cancels caused by speculative bypasses"}, #define PME_MONT_L2D_OZQ_CANCELS1_SIBLING_ACQ_REL 416 { "L2D_OZQ_CANCELS1_SIBLING_ACQ_REL", {0x208e2}, 0xfff0, 4, {0x4020007}, "L2D OZQ Cancels (Late or Any) -- counts the late cancels caused by releases and acquires in the same issue group. This is the combination of following subevents that were available separately in Itanium2: LATE_ACQUIRE=late cancels caused by acquires, LATE_RELEASE=late cancles caused by releases"}, #define PME_MONT_L2D_OZQ_FULL_THIS 417 { "L2D_OZQ_FULL_THIS", {0x8bc}, 0xfff0, 1, {0x4520000}, "L2D OZQ Is Full -- L2D OZQ is full"}, #define PME_MONT_L2D_OZQ_RELEASE 418 { "L2D_OZQ_RELEASE", {0x8e5}, 0xfff0, 1, {0x4120000}, "Release Ordering Attribute Exists in L2D OZQ"}, #define PME_MONT_L2D_REFERENCES_ALL 419 { "L2D_REFERENCES_ALL", {0x308e6}, 0xfff0, 4, {0x4220007}, "Data Read/Write Access to L2D -- count both read and write operations (semaphores will count as 2)"}, #define PME_MONT_L2D_REFERENCES_READS 420 { "L2D_REFERENCES_READS", {0x108e6}, 0xfff0, 4, {0x4220007}, "Data Read/Write Access to L2D -- count only data read and semaphore operations."}, #define PME_MONT_L2D_REFERENCES_WRITES 421 { "L2D_REFERENCES_WRITES", {0x208e6}, 0xfff0, 4, {0x4220007}, "Data Read/Write Access to L2D -- count only data write and semaphore operations"}, #define PME_MONT_L2D_STORE_HIT_SHARED_ANY 422 { "L2D_STORE_HIT_SHARED_ANY", {0x8ed}, 0xfff0, 2, {0x4520007}, "Store Hit a Shared Line -- Store hit a shared line"}, #define PME_MONT_L2D_VICTIMB_FULL_THIS 423 { "L2D_VICTIMB_FULL_THIS", {0x8f3}, 0xfff0, 1, {0x4820000}, "L2D Victim Buffer Is Full -- L2D victim buffer is full"}, #define PME_MONT_L2I_DEMAND_READS 424 { "L2I_DEMAND_READS", {0x42}, 0xfff0, 1, {0xffff0001}, "L2 Instruction Demand Fetch Requests"}, #define PME_MONT_L2I_HIT_CONFLICTS_ALL_ALL 425 { "L2I_HIT_CONFLICTS_ALL_ALL", {0xf087d}, 0xfff0, 1, {0xffff0001}, "L2I hit conflicts -- All fetches that reference L2I are counted"}, #define PME_MONT_L2I_HIT_CONFLICTS_ALL_DMND 426 { "L2I_HIT_CONFLICTS_ALL_DMND", {0xd087d}, 0xfff0, 1, {0xffff0001}, "L2I hit conflicts -- Only demand fetches that reference L2I are counted"}, #define PME_MONT_L2I_HIT_CONFLICTS_ALL_PFTCH 427 { "L2I_HIT_CONFLICTS_ALL_PFTCH", {0xe087d}, 0xfff0, 1, {0xffff0001}, "L2I hit conflicts -- Only prefetches that reference L2I are counted"}, #define PME_MONT_L2I_HIT_CONFLICTS_HIT_ALL 428 { "L2I_HIT_CONFLICTS_HIT_ALL", {0x7087d}, 0xfff0, 1, {0xffff0001}, "L2I hit conflicts -- All fetches that hit in L2I counted"}, #define PME_MONT_L2I_HIT_CONFLICTS_HIT_DMND 429 { "L2I_HIT_CONFLICTS_HIT_DMND", {0x5087d}, 0xfff0, 1, {0xffff0001}, "L2I hit conflicts -- Only demand fetches that hit in L2I are counted"}, #define PME_MONT_L2I_HIT_CONFLICTS_HIT_PFTCH 430 { "L2I_HIT_CONFLICTS_HIT_PFTCH", {0x6087d}, 0xfff0, 1, {0xffff0001}, "L2I hit conflicts -- Only prefetches that hit in L2I are counted"}, #define PME_MONT_L2I_HIT_CONFLICTS_MISS_ALL 431 { "L2I_HIT_CONFLICTS_MISS_ALL", {0xb087d}, 0xfff0, 1, {0xffff0001}, "L2I hit conflicts -- All fetches that miss in L2I are counted"}, #define PME_MONT_L2I_HIT_CONFLICTS_MISS_DMND 432 { "L2I_HIT_CONFLICTS_MISS_DMND", {0x9087d}, 0xfff0, 1, {0xffff0001}, "L2I hit conflicts -- Only demand fetches that miss in L2I are counted"}, #define PME_MONT_L2I_HIT_CONFLICTS_MISS_PFTCH 433 { "L2I_HIT_CONFLICTS_MISS_PFTCH", {0xa087d}, 0xfff0, 1, {0xffff0001}, "L2I hit conflicts -- Only prefetches that miss in L2I are counted"}, #define PME_MONT_L2I_L3_REJECTS_ALL_ALL 434 { "L2I_L3_REJECTS_ALL_ALL", {0xf087c}, 0xfff0, 1, {0xffff0001}, "L3 rejects -- All fetches that reference L2I are counted"}, #define PME_MONT_L2I_L3_REJECTS_ALL_DMND 435 { "L2I_L3_REJECTS_ALL_DMND", {0xd087c}, 0xfff0, 1, {0xffff0001}, "L3 rejects -- Only demand fetches that reference L2I are counted"}, #define PME_MONT_L2I_L3_REJECTS_ALL_PFTCH 436 { "L2I_L3_REJECTS_ALL_PFTCH", {0xe087c}, 0xfff0, 1, {0xffff0001}, "L3 rejects -- Only prefetches that reference L2I are counted"}, #define PME_MONT_L2I_L3_REJECTS_HIT_ALL 437 { "L2I_L3_REJECTS_HIT_ALL", {0x7087c}, 0xfff0, 1, {0xffff0001}, "L3 rejects -- All fetches that hit in L2I counted"}, #define PME_MONT_L2I_L3_REJECTS_HIT_DMND 438 { "L2I_L3_REJECTS_HIT_DMND", {0x5087c}, 0xfff0, 1, {0xffff0001}, "L3 rejects -- Only demand fetches that hit in L2I are counted"}, #define PME_MONT_L2I_L3_REJECTS_HIT_PFTCH 439 { "L2I_L3_REJECTS_HIT_PFTCH", {0x6087c}, 0xfff0, 1, {0xffff0001}, "L3 rejects -- Only prefetches that hit in L2I are counted"}, #define PME_MONT_L2I_L3_REJECTS_MISS_ALL 440 { "L2I_L3_REJECTS_MISS_ALL", {0xb087c}, 0xfff0, 1, {0xffff0001}, "L3 rejects -- All fetches that miss in L2I are counted"}, #define PME_MONT_L2I_L3_REJECTS_MISS_DMND 441 { "L2I_L3_REJECTS_MISS_DMND", {0x9087c}, 0xfff0, 1, {0xffff0001}, "L3 rejects -- Only demand fetches that miss in L2I are counted"}, #define PME_MONT_L2I_L3_REJECTS_MISS_PFTCH 442 { "L2I_L3_REJECTS_MISS_PFTCH", {0xa087c}, 0xfff0, 1, {0xffff0001}, "L3 rejects -- Only prefetches that miss in L2I are counted"}, #define PME_MONT_L2I_PREFETCHES 443 { "L2I_PREFETCHES", {0x45}, 0xfff0, 1, {0xffff0001}, "L2 Instruction Prefetch Requests"}, #define PME_MONT_L2I_READS_ALL_ALL 444 { "L2I_READS_ALL_ALL", {0xf0878}, 0xfff0, 1, {0xffff0001}, "L2I Cacheable Reads -- All fetches that reference L2I are counted"}, #define PME_MONT_L2I_READS_ALL_DMND 445 { "L2I_READS_ALL_DMND", {0xd0878}, 0xfff0, 1, {0xffff0001}, "L2I Cacheable Reads -- Only demand fetches that reference L2I are counted"}, #define PME_MONT_L2I_READS_ALL_PFTCH 446 { "L2I_READS_ALL_PFTCH", {0xe0878}, 0xfff0, 1, {0xffff0001}, "L2I Cacheable Reads -- Only prefetches that reference L2I are counted"}, #define PME_MONT_L2I_READS_HIT_ALL 447 { "L2I_READS_HIT_ALL", {0x70878}, 0xfff0, 1, {0xffff0001}, "L2I Cacheable Reads -- All fetches that hit in L2I counted"}, #define PME_MONT_L2I_READS_HIT_DMND 448 { "L2I_READS_HIT_DMND", {0x50878}, 0xfff0, 1, {0xffff0001}, "L2I Cacheable Reads -- Only demand fetches that hit in L2I are counted"}, #define PME_MONT_L2I_READS_HIT_PFTCH 449 { "L2I_READS_HIT_PFTCH", {0x60878}, 0xfff0, 1, {0xffff0001}, "L2I Cacheable Reads -- Only prefetches that hit in L2I are counted"}, #define PME_MONT_L2I_READS_MISS_ALL 450 { "L2I_READS_MISS_ALL", {0xb0878}, 0xfff0, 1, {0xffff0001}, "L2I Cacheable Reads -- All fetches that miss in L2I are counted"}, #define PME_MONT_L2I_READS_MISS_DMND 451 { "L2I_READS_MISS_DMND", {0x90878}, 0xfff0, 1, {0xffff0001}, "L2I Cacheable Reads -- Only demand fetches that miss in L2I are counted"}, #define PME_MONT_L2I_READS_MISS_PFTCH 452 { "L2I_READS_MISS_PFTCH", {0xa0878}, 0xfff0, 1, {0xffff0001}, "L2I Cacheable Reads -- Only prefetches that miss in L2I are counted"}, #define PME_MONT_L2I_RECIRCULATES_ALL_ALL 453 { "L2I_RECIRCULATES_ALL_ALL", {0xf087b}, 0xfff0, 1, {0xffff0001}, "L2I recirculates -- All fetches that reference L2I are counted"}, #define PME_MONT_L2I_RECIRCULATES_ALL_DMND 454 { "L2I_RECIRCULATES_ALL_DMND", {0xd087b}, 0xfff0, 1, {0xffff0001}, "L2I recirculates -- Only demand fetches that reference L2I are counted"}, #define PME_MONT_L2I_RECIRCULATES_ALL_PFTCH 455 { "L2I_RECIRCULATES_ALL_PFTCH", {0xe087b}, 0xfff0, 1, {0xffff0001}, "L2I recirculates -- Only prefetches that reference L2I are counted"}, #define PME_MONT_L2I_RECIRCULATES_HIT_ALL 456 { "L2I_RECIRCULATES_HIT_ALL", {0x7087b}, 0xfff0, 1, {0xffff0001}, "L2I recirculates -- All fetches that hit in L2I counted"}, #define PME_MONT_L2I_RECIRCULATES_HIT_DMND 457 { "L2I_RECIRCULATES_HIT_DMND", {0x5087b}, 0xfff0, 1, {0xffff0001}, "L2I recirculates -- Only demand fetches that hit in L2I are counted"}, #define PME_MONT_L2I_RECIRCULATES_HIT_PFTCH 458 { "L2I_RECIRCULATES_HIT_PFTCH", {0x6087b}, 0xfff0, 1, {0xffff0001}, "L2I recirculates -- Only prefetches that hit in L2I are counted"}, #define PME_MONT_L2I_RECIRCULATES_MISS_ALL 459 { "L2I_RECIRCULATES_MISS_ALL", {0xb087b}, 0xfff0, 1, {0xffff0001}, "L2I recirculates -- All fetches that miss in L2I are counted"}, #define PME_MONT_L2I_RECIRCULATES_MISS_DMND 460 { "L2I_RECIRCULATES_MISS_DMND", {0x9087b}, 0xfff0, 1, {0xffff0001}, "L2I recirculates -- Only demand fetches that miss in L2I are counted"}, #define PME_MONT_L2I_RECIRCULATES_MISS_PFTCH 461 { "L2I_RECIRCULATES_MISS_PFTCH", {0xa087b}, 0xfff0, 1, {0xffff0001}, "L2I recirculates -- Only prefetches that miss in L2I are counted"}, #define PME_MONT_L2I_SNOOP_HITS 462 { "L2I_SNOOP_HITS", {0x107f}, 0xfff0, 1, {0xffff0000}, "L2I snoop hits"}, #define PME_MONT_L2I_SPEC_ABORTS 463 { "L2I_SPEC_ABORTS", {0x87e}, 0xfff0, 1, {0xffff0001}, "L2I speculative aborts"}, #define PME_MONT_L2I_UC_READS_ALL_ALL 464 { "L2I_UC_READS_ALL_ALL", {0xf0879}, 0xfff0, 1, {0xffff0001}, "L2I Uncacheable reads -- All fetches that reference L2I are counted"}, #define PME_MONT_L2I_UC_READS_ALL_DMND 465 { "L2I_UC_READS_ALL_DMND", {0xd0879}, 0xfff0, 1, {0xffff0001}, "L2I Uncacheable reads -- Only demand fetches that reference L2I are counted"}, #define PME_MONT_L2I_UC_READS_ALL_PFTCH 466 { "L2I_UC_READS_ALL_PFTCH", {0xe0879}, 0xfff0, 1, {0xffff0001}, "L2I Uncacheable reads -- Only prefetches that reference L2I are counted"}, #define PME_MONT_L2I_UC_READS_HIT_ALL 467 { "L2I_UC_READS_HIT_ALL", {0x70879}, 0xfff0, 1, {0xffff0001}, "L2I Uncacheable reads -- All fetches that hit in L2I counted"}, #define PME_MONT_L2I_UC_READS_HIT_DMND 468 { "L2I_UC_READS_HIT_DMND", {0x50879}, 0xfff0, 1, {0xffff0001}, "L2I Uncacheable reads -- Only demand fetches that hit in L2I are counted"}, #define PME_MONT_L2I_UC_READS_HIT_PFTCH 469 { "L2I_UC_READS_HIT_PFTCH", {0x60879}, 0xfff0, 1, {0xffff0001}, "L2I Uncacheable reads -- Only prefetches that hit in L2I are counted"}, #define PME_MONT_L2I_UC_READS_MISS_ALL 470 { "L2I_UC_READS_MISS_ALL", {0xb0879}, 0xfff0, 1, {0xffff0001}, "L2I Uncacheable reads -- All fetches that miss in L2I are counted"}, #define PME_MONT_L2I_UC_READS_MISS_DMND 471 { "L2I_UC_READS_MISS_DMND", {0x90879}, 0xfff0, 1, {0xffff0001}, "L2I Uncacheable reads -- Only demand fetches that miss in L2I are counted"}, #define PME_MONT_L2I_UC_READS_MISS_PFTCH 472 { "L2I_UC_READS_MISS_PFTCH", {0xa0879}, 0xfff0, 1, {0xffff0001}, "L2I Uncacheable reads -- Only prefetches that miss in L2I are counted"}, #define PME_MONT_L2I_VICTIMIZATION 473 { "L2I_VICTIMIZATION", {0x87a}, 0xfff0, 1, {0xffff0001}, "L2I victimizations"}, #define PME_MONT_L3_INSERTS 474 { "L3_INSERTS", {0x8da}, 0xfff0, 1, {0xffff0017}, "L3 Cache Lines inserts"}, #define PME_MONT_L3_LINES_REPLACED 475 { "L3_LINES_REPLACED", {0x8df}, 0xfff0, 1, {0xffff0010}, "L3 Cache Lines Replaced"}, #define PME_MONT_L3_MISSES 476 { "L3_MISSES", {0x8dc}, 0xfff0, 1, {0xffff0007}, "L3 Misses"}, #define PME_MONT_L3_READS_ALL_ALL 477 { "L3_READS_ALL_ALL", {0xf08dd}, 0xfff0, 1, {0xffff0017}, "L3 Reads -- L3 Read References"}, #define PME_MONT_L3_READS_ALL_HIT 478 { "L3_READS_ALL_HIT", {0xd08dd}, 0xfff0, 1, {0xffff0017}, "L3 Reads -- L3 Read Hits"}, #define PME_MONT_L3_READS_ALL_MISS 479 { "L3_READS_ALL_MISS", {0xe08dd}, 0xfff0, 1, {0xffff0017}, "L3 Reads -- L3 Read Misses"}, #define PME_MONT_L3_READS_DATA_READ_ALL 480 { "L3_READS_DATA_READ_ALL", {0xb08dd}, 0xfff0, 1, {0xffff0017}, "L3 Reads -- L3 Load References (excludes reads for ownership used to satisfy stores)"}, #define PME_MONT_L3_READS_DATA_READ_HIT 481 { "L3_READS_DATA_READ_HIT", {0x908dd}, 0xfff0, 1, {0xffff0017}, "L3 Reads -- L3 Load Hits (excludes reads for ownership used to satisfy stores)"}, #define PME_MONT_L3_READS_DATA_READ_MISS 482 { "L3_READS_DATA_READ_MISS", {0xa08dd}, 0xfff0, 1, {0xffff0017}, "L3 Reads -- L3 Load Misses (excludes reads for ownership used to satisfy stores)"}, #define PME_MONT_L3_READS_DINST_FETCH_ALL 483 { "L3_READS_DINST_FETCH_ALL", {0x308dd}, 0xfff0, 1, {0xffff0017}, "L3 Reads -- L3 Demand Instruction References"}, #define PME_MONT_L3_READS_DINST_FETCH_HIT 484 { "L3_READS_DINST_FETCH_HIT", {0x108dd}, 0xfff0, 1, {0xffff0017}, "L3 Reads -- L3 Demand Instruction Fetch Hits"}, #define PME_MONT_L3_READS_DINST_FETCH_MISS 485 { "L3_READS_DINST_FETCH_MISS", {0x208dd}, 0xfff0, 1, {0xffff0017}, "L3 Reads -- L3 Demand Instruction Fetch Misses"}, #define PME_MONT_L3_READS_INST_FETCH_ALL 486 { "L3_READS_INST_FETCH_ALL", {0x708dd}, 0xfff0, 1, {0xffff0017}, "L3 Reads -- L3 Instruction Fetch and Prefetch References"}, #define PME_MONT_L3_READS_INST_FETCH_HIT 487 { "L3_READS_INST_FETCH_HIT", {0x508dd}, 0xfff0, 1, {0xffff0017}, "L3 Reads -- L3 Instruction Fetch and Prefetch Hits"}, #define PME_MONT_L3_READS_INST_FETCH_MISS 488 { "L3_READS_INST_FETCH_MISS", {0x608dd}, 0xfff0, 1, {0xffff0017}, "L3 Reads -- L3 Instruction Fetch and Prefetch Misses"}, #define PME_MONT_L3_REFERENCES 489 { "L3_REFERENCES", {0x8db}, 0xfff0, 1, {0xffff0007}, "L3 References"}, #define PME_MONT_L3_WRITES_ALL_ALL 490 { "L3_WRITES_ALL_ALL", {0xf08de}, 0xfff0, 1, {0xffff0017}, "L3 Writes -- L3 Write References"}, #define PME_MONT_L3_WRITES_ALL_HIT 491 { "L3_WRITES_ALL_HIT", {0xd08de}, 0xfff0, 1, {0xffff0017}, "L3 Writes -- L3 Write Hits"}, #define PME_MONT_L3_WRITES_ALL_MISS 492 { "L3_WRITES_ALL_MISS", {0xe08de}, 0xfff0, 1, {0xffff0017}, "L3 Writes -- L3 Write Misses"}, #define PME_MONT_L3_WRITES_DATA_WRITE_ALL 493 { "L3_WRITES_DATA_WRITE_ALL", {0x708de}, 0xfff0, 1, {0xffff0017}, "L3 Writes -- L3 Store References (excludes L2 write backs, includes L3 read for ownership requests that satisfy stores)"}, #define PME_MONT_L3_WRITES_DATA_WRITE_HIT 494 { "L3_WRITES_DATA_WRITE_HIT", {0x508de}, 0xfff0, 1, {0xffff0017}, "L3 Writes -- L3 Store Hits (excludes L2 write backs, includes L3 read for ownership requests that satisfy stores)"}, #define PME_MONT_L3_WRITES_DATA_WRITE_MISS 495 { "L3_WRITES_DATA_WRITE_MISS", {0x608de}, 0xfff0, 1, {0xffff0017}, "L3 Writes -- L3 Store Misses (excludes L2 write backs, includes L3 read for ownership requests that satisfy stores)"}, #define PME_MONT_L3_WRITES_L2_WB_ALL 496 { "L3_WRITES_L2_WB_ALL", {0xb08de}, 0xfff0, 1, {0xffff0017}, "L3 Writes -- L2 Write Back References"}, #define PME_MONT_L3_WRITES_L2_WB_HIT 497 { "L3_WRITES_L2_WB_HIT", {0x908de}, 0xfff0, 1, {0xffff0017}, "L3 Writes -- L2 Write Back Hits"}, #define PME_MONT_L3_WRITES_L2_WB_MISS 498 { "L3_WRITES_L2_WB_MISS", {0xa08de}, 0xfff0, 1, {0xffff0017}, "L3 Writes -- L2 Write Back Misses"}, #define PME_MONT_LOADS_RETIRED 499 { "LOADS_RETIRED", {0xcd}, 0xfff0, 4, {0x5310007}, "Retired Loads"}, #define PME_MONT_LOADS_RETIRED_INTG 500 { "LOADS_RETIRED_INTG", {0xd8}, 0xfff0, 2, {0x5610007}, "Integer loads retired"}, #define PME_MONT_MEM_READ_CURRENT_ANY 501 { "MEM_READ_CURRENT_ANY", {0x31089}, 0xfff0, 1, {0xffff0000}, "Current Mem Read Transactions On Bus -- CPU or non-CPU (all transactions)."}, #define PME_MONT_MEM_READ_CURRENT_IO 502 { "MEM_READ_CURRENT_IO", {0x11089}, 0xfff0, 1, {0xffff0000}, "Current Mem Read Transactions On Bus -- non-CPU priority agents"}, #define PME_MONT_MISALIGNED_LOADS_RETIRED 503 { "MISALIGNED_LOADS_RETIRED", {0xce}, 0xfff0, 4, {0x5310007}, "Retired Misaligned Load Instructions"}, #define PME_MONT_MISALIGNED_STORES_RETIRED 504 { "MISALIGNED_STORES_RETIRED", {0xd2}, 0xfff0, 2, {0x5410007}, "Retired Misaligned Store Instructions"}, #define PME_MONT_NOPS_RETIRED 505 { "NOPS_RETIRED", {0x50}, 0xfff0, 6, {0xffff0003}, "Retired NOP Instructions"}, #define PME_MONT_PREDICATE_SQUASHED_RETIRED 506 { "PREDICATE_SQUASHED_RETIRED", {0x51}, 0xfff0, 6, {0xffff0003}, "Instructions Squashed Due to Predicate Off"}, #define PME_MONT_RSE_CURRENT_REGS_2_TO_0 507 { "RSE_CURRENT_REGS_2_TO_0", {0x2b}, 0xfff0, 7, {0xffff0000}, "Current RSE Registers (Bits 2:0)"}, #define PME_MONT_RSE_CURRENT_REGS_5_TO_3 508 { "RSE_CURRENT_REGS_5_TO_3", {0x2a}, 0xfff0, 7, {0xffff0000}, "Current RSE Registers (Bits 5:3)"}, #define PME_MONT_RSE_CURRENT_REGS_6 509 { "RSE_CURRENT_REGS_6", {0x26}, 0xfff0, 1, {0xffff0000}, "Current RSE Registers (Bit 6)"}, #define PME_MONT_RSE_DIRTY_REGS_2_TO_0 510 { "RSE_DIRTY_REGS_2_TO_0", {0x29}, 0xfff0, 7, {0xffff0000}, "Dirty RSE Registers (Bits 2:0)"}, #define PME_MONT_RSE_DIRTY_REGS_5_TO_3 511 { "RSE_DIRTY_REGS_5_TO_3", {0x28}, 0xfff0, 7, {0xffff0000}, "Dirty RSE Registers (Bits 5:3)"}, #define PME_MONT_RSE_DIRTY_REGS_6 512 { "RSE_DIRTY_REGS_6", {0x24}, 0xfff0, 1, {0xffff0000}, "Dirty RSE Registers (Bit 6)"}, #define PME_MONT_RSE_EVENT_RETIRED 513 { "RSE_EVENT_RETIRED", {0x32}, 0xfff0, 1, {0xffff0000}, "Retired RSE operations"}, #define PME_MONT_RSE_REFERENCES_RETIRED_ALL 514 { "RSE_REFERENCES_RETIRED_ALL", {0x30020}, 0xfff0, 2, {0xffff0007}, "RSE Accesses -- Both RSE loads and stores will be counted."}, #define PME_MONT_RSE_REFERENCES_RETIRED_LOAD 515 { "RSE_REFERENCES_RETIRED_LOAD", {0x10020}, 0xfff0, 2, {0xffff0007}, "RSE Accesses -- Only RSE loads will be counted."}, #define PME_MONT_RSE_REFERENCES_RETIRED_STORE 516 { "RSE_REFERENCES_RETIRED_STORE", {0x20020}, 0xfff0, 2, {0xffff0007}, "RSE Accesses -- Only RSE stores will be counted."}, #define PME_MONT_SERIALIZATION_EVENTS 517 { "SERIALIZATION_EVENTS", {0x53}, 0xfff0, 1, {0xffff0000}, "Number of srlz.i Instructions"}, #define PME_MONT_SI_CCQ_COLLISIONS_EITHER 518 { "SI_CCQ_COLLISIONS_EITHER", {0x10a8}, 0xfff0, 2, {0xffff0000}, "Clean Castout Queue Collisions -- transactions initiated by either cpu core"}, #define PME_MONT_SI_CCQ_COLLISIONS_SELF 519 { "SI_CCQ_COLLISIONS_SELF", {0x110a8}, 0xfff0, 2, {0xffff0000}, "Clean Castout Queue Collisions -- transactions initiated by 'this' cpu core"}, #define PME_MONT_SI_CCQ_INSERTS_EITHER 520 { "SI_CCQ_INSERTS_EITHER", {0x18a5}, 0xfff0, 2, {0xffff0000}, "Clean Castout Queue Insertions -- transactions initiated by either cpu core"}, #define PME_MONT_SI_CCQ_INSERTS_SELF 521 { "SI_CCQ_INSERTS_SELF", {0x118a5}, 0xfff0, 2, {0xffff0000}, "Clean Castout Queue Insertions -- transactions initiated by 'this' cpu core"}, #define PME_MONT_SI_CCQ_LIVE_REQ_HI_EITHER 522 { "SI_CCQ_LIVE_REQ_HI_EITHER", {0x10a7}, 0xfff0, 1, {0xffff0000}, "Clean Castout Queue Requests (upper bit) -- transactions initiated by either cpu core"}, #define PME_MONT_SI_CCQ_LIVE_REQ_HI_SELF 523 { "SI_CCQ_LIVE_REQ_HI_SELF", {0x110a7}, 0xfff0, 1, {0xffff0000}, "Clean Castout Queue Requests (upper bit) -- transactions initiated by 'this' cpu core"}, #define PME_MONT_SI_CCQ_LIVE_REQ_LO_EITHER 524 { "SI_CCQ_LIVE_REQ_LO_EITHER", {0x10a6}, 0xfff0, 7, {0xffff0000}, "Clean Castout Queue Requests (lower three bits) -- transactions initiated by either cpu core"}, #define PME_MONT_SI_CCQ_LIVE_REQ_LO_SELF 525 { "SI_CCQ_LIVE_REQ_LO_SELF", {0x110a6}, 0xfff0, 7, {0xffff0000}, "Clean Castout Queue Requests (lower three bits) -- transactions initiated by 'this' cpu core"}, #define PME_MONT_SI_CYCLES 526 { "SI_CYCLES", {0x108e}, 0xfff0, 1, {0xffff0000}, "SI Cycles"}, #define PME_MONT_SI_IOQ_COLLISIONS 527 { "SI_IOQ_COLLISIONS", {0x10aa}, 0xfff0, 2, {0xffff0000}, "In Order Queue Collisions"}, #define PME_MONT_SI_IOQ_LIVE_REQ_HI 528 { "SI_IOQ_LIVE_REQ_HI", {0x1098}, 0xfff0, 2, {0xffff0000}, "Inorder Bus Queue Requests (upper bit)"}, #define PME_MONT_SI_IOQ_LIVE_REQ_LO 529 { "SI_IOQ_LIVE_REQ_LO", {0x1097}, 0xfff0, 3, {0xffff0000}, "Inorder Bus Queue Requests (lower three bits)"}, #define PME_MONT_SI_RQ_INSERTS_EITHER 530 { "SI_RQ_INSERTS_EITHER", {0x189e}, 0xfff0, 2, {0xffff0000}, "Request Queue Insertions -- transactions initiated by either cpu core"}, #define PME_MONT_SI_RQ_INSERTS_SELF 531 { "SI_RQ_INSERTS_SELF", {0x1189e}, 0xfff0, 2, {0xffff0000}, "Request Queue Insertions -- transactions initiated by 'this' cpu core"}, #define PME_MONT_SI_RQ_LIVE_REQ_HI_EITHER 532 { "SI_RQ_LIVE_REQ_HI_EITHER", {0x10a0}, 0xfff0, 1, {0xffff0000}, "Request Queue Requests (upper bit) -- transactions initiated by either cpu core"}, #define PME_MONT_SI_RQ_LIVE_REQ_HI_SELF 533 { "SI_RQ_LIVE_REQ_HI_SELF", {0x110a0}, 0xfff0, 1, {0xffff0000}, "Request Queue Requests (upper bit) -- transactions initiated by 'this' cpu core"}, #define PME_MONT_SI_RQ_LIVE_REQ_LO_EITHER 534 { "SI_RQ_LIVE_REQ_LO_EITHER", {0x109f}, 0xfff0, 7, {0xffff0000}, "Request Queue Requests (lower three bits) -- transactions initiated by either cpu core"}, #define PME_MONT_SI_RQ_LIVE_REQ_LO_SELF 535 { "SI_RQ_LIVE_REQ_LO_SELF", {0x1109f}, 0xfff0, 7, {0xffff0000}, "Request Queue Requests (lower three bits) -- transactions initiated by 'this' cpu core"}, #define PME_MONT_SI_SCB_INSERTS_ALL_EITHER 536 { "SI_SCB_INSERTS_ALL_EITHER", {0xc10ab}, 0xfff0, 4, {0xffff0000}, "Snoop Coalescing Buffer Insertions -- count all snoop signoffs (plus backsnoop inserts) from either cpu core"}, #define PME_MONT_SI_SCB_INSERTS_ALL_SELF 537 { "SI_SCB_INSERTS_ALL_SELF", {0xd10ab}, 0xfff0, 4, {0xffff0000}, "Snoop Coalescing Buffer Insertions -- count all snoop signoffs (plus backsnoop inserts) from 'this' cpu core"}, #define PME_MONT_SI_SCB_INSERTS_HIT_EITHER 538 { "SI_SCB_INSERTS_HIT_EITHER", {0x410ab}, 0xfff0, 4, {0xffff0000}, "Snoop Coalescing Buffer Insertions -- count HIT snoop signoffs from either cpu core"}, #define PME_MONT_SI_SCB_INSERTS_HIT_SELF 539 { "SI_SCB_INSERTS_HIT_SELF", {0x510ab}, 0xfff0, 4, {0xffff0000}, "Snoop Coalescing Buffer Insertions -- count HIT snoop signoffs from 'this' cpu core"}, #define PME_MONT_SI_SCB_INSERTS_HITM_EITHER 540 { "SI_SCB_INSERTS_HITM_EITHER", {0x810ab}, 0xfff0, 4, {0xffff0000}, "Snoop Coalescing Buffer Insertions -- count HITM snoop signoffs from either cpu core"}, #define PME_MONT_SI_SCB_INSERTS_HITM_SELF 541 { "SI_SCB_INSERTS_HITM_SELF", {0x910ab}, 0xfff0, 4, {0xffff0000}, "Snoop Coalescing Buffer Insertions -- count HITM snoop signoffs from 'this' cpu core"}, #define PME_MONT_SI_SCB_INSERTS_MISS_EITHER 542 { "SI_SCB_INSERTS_MISS_EITHER", {0x10ab}, 0xfff0, 4, {0xffff0000}, "Snoop Coalescing Buffer Insertions -- count MISS snoop signoffs (plus backsnoop inserts) from either cpu core"}, #define PME_MONT_SI_SCB_INSERTS_MISS_SELF 543 { "SI_SCB_INSERTS_MISS_SELF", {0x110ab}, 0xfff0, 4, {0xffff0000}, "Snoop Coalescing Buffer Insertions -- count MISS snoop signoffs (plus backsnoop inserts) from 'this' cpu core"}, #define PME_MONT_SI_SCB_LIVE_REQ_HI_EITHER 544 { "SI_SCB_LIVE_REQ_HI_EITHER", {0x10ad}, 0xfff0, 1, {0xffff0000}, "Snoop Coalescing Buffer Requests (upper bit) -- transactions initiated by either cpu core"}, #define PME_MONT_SI_SCB_LIVE_REQ_HI_SELF 545 { "SI_SCB_LIVE_REQ_HI_SELF", {0x110ad}, 0xfff0, 1, {0xffff0000}, "Snoop Coalescing Buffer Requests (upper bit) -- transactions initiated by 'this' cpu core"}, #define PME_MONT_SI_SCB_LIVE_REQ_LO_EITHER 546 { "SI_SCB_LIVE_REQ_LO_EITHER", {0x10ac}, 0xfff0, 7, {0xffff0000}, "Snoop Coalescing Buffer Requests (lower three bits) -- transactions initiated by either cpu core"}, #define PME_MONT_SI_SCB_LIVE_REQ_LO_SELF 547 { "SI_SCB_LIVE_REQ_LO_SELF", {0x110ac}, 0xfff0, 7, {0xffff0000}, "Snoop Coalescing Buffer Requests (lower three bits) -- transactions initiated by 'this' cpu core"}, #define PME_MONT_SI_SCB_SIGNOFFS_ALL 548 { "SI_SCB_SIGNOFFS_ALL", {0xc10ae}, 0xfff0, 1, {0xffff0000}, "Snoop Coalescing Buffer Coherency Signoffs -- count all snoop signoffs"}, #define PME_MONT_SI_SCB_SIGNOFFS_HIT 549 { "SI_SCB_SIGNOFFS_HIT", {0x410ae}, 0xfff0, 1, {0xffff0000}, "Snoop Coalescing Buffer Coherency Signoffs -- count HIT snoop signoffs"}, #define PME_MONT_SI_SCB_SIGNOFFS_HITM 550 { "SI_SCB_SIGNOFFS_HITM", {0x810ae}, 0xfff0, 1, {0xffff0000}, "Snoop Coalescing Buffer Coherency Signoffs -- count HITM snoop signoffs"}, #define PME_MONT_SI_SCB_SIGNOFFS_MISS 551 { "SI_SCB_SIGNOFFS_MISS", {0x10ae}, 0xfff0, 1, {0xffff0000}, "Snoop Coalescing Buffer Coherency Signoffs -- count MISS snoop signoffs"}, #define PME_MONT_SI_WAQ_COLLISIONS_EITHER 552 { "SI_WAQ_COLLISIONS_EITHER", {0x10a4}, 0xfff0, 1, {0xffff0000}, "Write Address Queue Collisions -- transactions initiated by either cpu core"}, #define PME_MONT_SI_WAQ_COLLISIONS_SELF 553 { "SI_WAQ_COLLISIONS_SELF", {0x110a4}, 0xfff0, 1, {0xffff0000}, "Write Address Queue Collisions -- transactions initiated by 'this' cpu core"}, #define PME_MONT_SI_WDQ_ECC_ERRORS_ALL_EITHER 554 { "SI_WDQ_ECC_ERRORS_ALL_EITHER", {0x810af}, 0xfff0, 2, {0xffff0000}, "Write Data Queue ECC Errors -- count all ECC errors from either cpu core"}, #define PME_MONT_SI_WDQ_ECC_ERRORS_ALL_SELF 555 { "SI_WDQ_ECC_ERRORS_ALL_SELF", {0x910af}, 0xfff0, 2, {0xffff0000}, "Write Data Queue ECC Errors -- count all ECC errors from 'this' cpu core"}, #define PME_MONT_SI_WDQ_ECC_ERRORS_DBL_EITHER 556 { "SI_WDQ_ECC_ERRORS_DBL_EITHER", {0x410af}, 0xfff0, 2, {0xffff0000}, "Write Data Queue ECC Errors -- count double-bit ECC errors from either cpu core"}, #define PME_MONT_SI_WDQ_ECC_ERRORS_DBL_SELF 557 { "SI_WDQ_ECC_ERRORS_DBL_SELF", {0x510af}, 0xfff0, 2, {0xffff0000}, "Write Data Queue ECC Errors -- count double-bit ECC errors from 'this' cpu core"}, #define PME_MONT_SI_WDQ_ECC_ERRORS_SGL_EITHER 558 { "SI_WDQ_ECC_ERRORS_SGL_EITHER", {0x10af}, 0xfff0, 2, {0xffff0000}, "Write Data Queue ECC Errors -- count single-bit ECC errors from either cpu core"}, #define PME_MONT_SI_WDQ_ECC_ERRORS_SGL_SELF 559 { "SI_WDQ_ECC_ERRORS_SGL_SELF", {0x110af}, 0xfff0, 2, {0xffff0000}, "Write Data Queue ECC Errors -- count single-bit ECC errors from 'this' cpu core"}, #define PME_MONT_SI_WRITEQ_INSERTS_ALL_EITHER 560 { "SI_WRITEQ_INSERTS_ALL_EITHER", {0x18a1}, 0xfff0, 2, {0xffff0000}, "Write Queue Insertions -- "}, #define PME_MONT_SI_WRITEQ_INSERTS_ALL_SELF 561 { "SI_WRITEQ_INSERTS_ALL_SELF", {0x118a1}, 0xfff0, 2, {0xffff0000}, "Write Queue Insertions -- "}, #define PME_MONT_SI_WRITEQ_INSERTS_EWB_EITHER 562 { "SI_WRITEQ_INSERTS_EWB_EITHER", {0x418a1}, 0xfff0, 2, {0xffff0000}, "Write Queue Insertions -- "}, #define PME_MONT_SI_WRITEQ_INSERTS_EWB_SELF 563 { "SI_WRITEQ_INSERTS_EWB_SELF", {0x518a1}, 0xfff0, 2, {0xffff0000}, "Write Queue Insertions -- "}, #define PME_MONT_SI_WRITEQ_INSERTS_IWB_EITHER 564 { "SI_WRITEQ_INSERTS_IWB_EITHER", {0x218a1}, 0xfff0, 2, {0xffff0000}, "Write Queue Insertions -- "}, #define PME_MONT_SI_WRITEQ_INSERTS_IWB_SELF 565 { "SI_WRITEQ_INSERTS_IWB_SELF", {0x318a1}, 0xfff0, 2, {0xffff0000}, "Write Queue Insertions -- "}, #define PME_MONT_SI_WRITEQ_INSERTS_NEWB_EITHER 566 { "SI_WRITEQ_INSERTS_NEWB_EITHER", {0xc18a1}, 0xfff0, 2, {0xffff0000}, "Write Queue Insertions -- "}, #define PME_MONT_SI_WRITEQ_INSERTS_NEWB_SELF 567 { "SI_WRITEQ_INSERTS_NEWB_SELF", {0xd18a1}, 0xfff0, 2, {0xffff0000}, "Write Queue Insertions -- "}, #define PME_MONT_SI_WRITEQ_INSERTS_WC16_EITHER 568 { "SI_WRITEQ_INSERTS_WC16_EITHER", {0x818a1}, 0xfff0, 2, {0xffff0000}, "Write Queue Insertions -- "}, #define PME_MONT_SI_WRITEQ_INSERTS_WC16_SELF 569 { "SI_WRITEQ_INSERTS_WC16_SELF", {0x918a1}, 0xfff0, 2, {0xffff0000}, "Write Queue Insertions -- "}, #define PME_MONT_SI_WRITEQ_INSERTS_WC1_8A_EITHER 570 { "SI_WRITEQ_INSERTS_WC1_8A_EITHER", {0x618a1}, 0xfff0, 2, {0xffff0000}, "Write Queue Insertions -- "}, #define PME_MONT_SI_WRITEQ_INSERTS_WC1_8A_SELF 571 { "SI_WRITEQ_INSERTS_WC1_8A_SELF", {0x718a1}, 0xfff0, 2, {0xffff0000}, "Write Queue Insertions -- "}, #define PME_MONT_SI_WRITEQ_INSERTS_WC1_8B_EITHER 572 { "SI_WRITEQ_INSERTS_WC1_8B_EITHER", {0xe18a1}, 0xfff0, 2, {0xffff0000}, "Write Queue Insertions -- "}, #define PME_MONT_SI_WRITEQ_INSERTS_WC1_8B_SELF 573 { "SI_WRITEQ_INSERTS_WC1_8B_SELF", {0xf18a1}, 0xfff0, 2, {0xffff0000}, "Write Queue Insertions -- "}, #define PME_MONT_SI_WRITEQ_INSERTS_WC32_EITHER 574 { "SI_WRITEQ_INSERTS_WC32_EITHER", {0xa18a1}, 0xfff0, 2, {0xffff0000}, "Write Queue Insertions -- "}, #define PME_MONT_SI_WRITEQ_INSERTS_WC32_SELF 575 { "SI_WRITEQ_INSERTS_WC32_SELF", {0xb18a1}, 0xfff0, 2, {0xffff0000}, "Write Queue Insertions -- "}, #define PME_MONT_SI_WRITEQ_LIVE_REQ_HI_EITHER 576 { "SI_WRITEQ_LIVE_REQ_HI_EITHER", {0x10a3}, 0xfff0, 1, {0xffff0000}, "Write Queue Requests (upper bit) -- transactions initiated by either cpu core"}, #define PME_MONT_SI_WRITEQ_LIVE_REQ_HI_SELF 577 { "SI_WRITEQ_LIVE_REQ_HI_SELF", {0x110a3}, 0xfff0, 1, {0xffff0000}, "Write Queue Requests (upper bit) -- transactions initiated by 'this' cpu core"}, #define PME_MONT_SI_WRITEQ_LIVE_REQ_LO_EITHER 578 { "SI_WRITEQ_LIVE_REQ_LO_EITHER", {0x10a2}, 0xfff0, 7, {0xffff0000}, "Write Queue Requests (lower three bits) -- transactions initiated by either cpu core"}, #define PME_MONT_SI_WRITEQ_LIVE_REQ_LO_SELF 579 { "SI_WRITEQ_LIVE_REQ_LO_SELF", {0x110a2}, 0xfff0, 7, {0xffff0000}, "Write Queue Requests (lower three bits) -- transactions initiated by 'this' cpu core"}, #define PME_MONT_SPEC_LOADS_NATTED_ALL 580 { "SPEC_LOADS_NATTED_ALL", {0xd9}, 0xfff0, 2, {0xffff0005}, "Number of speculative inter loads that are NaTd -- Count all NaT'd loads"}, #define PME_MONT_SPEC_LOADS_NATTED_DEF_PSR_ED 581 { "SPEC_LOADS_NATTED_DEF_PSR_ED", {0x500d9}, 0xfff0, 2, {0xffff0005}, "Number of speculative inter loads that are NaTd -- Only loads NaT'd due to effect of PSR.ed"}, #define PME_MONT_SPEC_LOADS_NATTED_DEF_TLB_FAULT 582 { "SPEC_LOADS_NATTED_DEF_TLB_FAULT", {0x300d9}, 0xfff0, 2, {0xffff0005}, "Number of speculative inter loads that are NaTd -- Only loads NaT'd due to deferred TLB faults"}, #define PME_MONT_SPEC_LOADS_NATTED_DEF_TLB_MISS 583 { "SPEC_LOADS_NATTED_DEF_TLB_MISS", {0x200d9}, 0xfff0, 2, {0xffff0005}, "Number of speculative inter loads that are NaTd -- Only loads NaT'd due to deferred TLB misses"}, #define PME_MONT_SPEC_LOADS_NATTED_NAT_CNSM 584 { "SPEC_LOADS_NATTED_NAT_CNSM", {0x400d9}, 0xfff0, 2, {0xffff0005}, "Number of speculative inter loads that are NaTd -- Only loads NaT'd due to NaT consumption"}, #define PME_MONT_SPEC_LOADS_NATTED_VHPT_MISS 585 { "SPEC_LOADS_NATTED_VHPT_MISS", {0x100d9}, 0xfff0, 2, {0xffff0005}, "Number of speculative inter loads that are NaTd -- Only loads NaT'd due to VHPT miss"}, #define PME_MONT_STORES_RETIRED 586 { "STORES_RETIRED", {0xd1}, 0xfff0, 2, {0x5410007}, "Retired Stores"}, #define PME_MONT_SYLL_NOT_DISPERSED_ALL 587 { "SYLL_NOT_DISPERSED_ALL", {0xf004e}, 0xfff0, 5, {0xffff0001}, "Syllables Not Dispersed -- Counts all syllables not dispersed. NOTE: Any combination of b0000-b1111 is valid."}, #define PME_MONT_SYLL_NOT_DISPERSED_EXPL 588 { "SYLL_NOT_DISPERSED_EXPL", {0x1004e}, 0xfff0, 5, {0xffff0001}, "Syllables Not Dispersed -- Count syllables not dispersed due to explicit stop bits. These consist of programmer specified architected S-bit and templates 1 and 5. Dispersal takes a 6-syllable (3-syllable) hit for every template 1/5 in bundle 0(1). Dispersal takes a 3-syllable (0 syllable) hit for every S-bit in bundle 0(1)"}, #define PME_MONT_SYLL_NOT_DISPERSED_EXPL_OR_FE 589 { "SYLL_NOT_DISPERSED_EXPL_OR_FE", {0x5004e}, 0xfff0, 5, {0xffff0001}, "Syllables Not Dispersed -- Count syllables not dispersed due to explicit stop bits or front-end not providing valid bundles or providing valid illegal templates."}, #define PME_MONT_SYLL_NOT_DISPERSED_EXPL_OR_FE_OR_MLX 590 { "SYLL_NOT_DISPERSED_EXPL_OR_FE_OR_MLX", {0xd004e}, 0xfff0, 5, {0xffff0001}, "Syllables Not Dispersed -- Count syllables not dispersed due to explicit stop bits or due to front-end not providing valid bundles or providing valid illegal templates or due to MLX bundle and resteers to non-0 syllable."}, #define PME_MONT_SYLL_NOT_DISPERSED_EXPL_OR_IMPL 591 { "SYLL_NOT_DISPERSED_EXPL_OR_IMPL", {0x3004e}, 0xfff0, 5, {0xffff0001}, "Syllables Not Dispersed -- Count syllables not dispersed due to explicit/implicit stop bits."}, #define PME_MONT_SYLL_NOT_DISPERSED_EXPL_OR_IMPL_OR_FE 592 { "SYLL_NOT_DISPERSED_EXPL_OR_IMPL_OR_FE", {0x7004e}, 0xfff0, 5, {0xffff0001}, "Syllables Not Dispersed -- Count syllables not dispersed due to explicit or implicit stop bits or due to front-end not providing valid bundles or providing valid illegal template."}, #define PME_MONT_SYLL_NOT_DISPERSED_EXPL_OR_IMPL_OR_MLX 593 { "SYLL_NOT_DISPERSED_EXPL_OR_IMPL_OR_MLX", {0xb004e}, 0xfff0, 5, {0xffff0001}, "Syllables Not Dispersed -- Count syllables not dispersed due to explicit or implicit stop bits or due to MLX bundle and resteers to non-0 syllable."}, #define PME_MONT_SYLL_NOT_DISPERSED_EXPL_OR_MLX 594 { "SYLL_NOT_DISPERSED_EXPL_OR_MLX", {0x9004e}, 0xfff0, 5, {0xffff0001}, "Syllables Not Dispersed -- Count syllables not dispersed due to explicit stop bits or to MLX bundle and resteers to non-0 syllable."}, #define PME_MONT_SYLL_NOT_DISPERSED_FE 595 { "SYLL_NOT_DISPERSED_FE", {0x4004e}, 0xfff0, 5, {0xffff0001}, "Syllables Not Dispersed -- Count syllables not dispersed due to front-end not providing valid bundles or providing valid illegal templates. Dispersal takes a 3-syllable hit for every invalid bundle or valid illegal template from front-end. Bundle 1 with front-end fault, is counted here (3-syllable hit).."}, #define PME_MONT_SYLL_NOT_DISPERSED_FE_OR_MLX 596 { "SYLL_NOT_DISPERSED_FE_OR_MLX", {0xc004e}, 0xfff0, 5, {0xffff0001}, "Syllables Not Dispersed -- Count syllables not dispersed due to MLI bundle and resteers to non-0 syllable or due to front-end not providing valid bundles or providing valid illegal templates."}, #define PME_MONT_SYLL_NOT_DISPERSED_IMPL 597 { "SYLL_NOT_DISPERSED_IMPL", {0x2004e}, 0xfff0, 5, {0xffff0001}, "Syllables Not Dispersed -- Count syllables not dispersed due to implicit stop bits. These consist of all of the non-architected stop bits (asymmetry, oversubscription, implicit). Dispersal takes a 6-syllable(3-syllable) hit for every implicit stop bits in bundle 0(1)."}, #define PME_MONT_SYLL_NOT_DISPERSED_IMPL_OR_FE 598 { "SYLL_NOT_DISPERSED_IMPL_OR_FE", {0x6004e}, 0xfff0, 5, {0xffff0001}, "Syllables Not Dispersed -- Count syllables not dispersed due to implicit stop bits or to front-end not providing valid bundles or providing valid illegal templates."}, #define PME_MONT_SYLL_NOT_DISPERSED_IMPL_OR_FE_OR_MLX 599 { "SYLL_NOT_DISPERSED_IMPL_OR_FE_OR_MLX", {0xe004e}, 0xfff0, 5, {0xffff0001}, "Syllables Not Dispersed -- Count syllables not dispersed due to implicit stop bits or due to front-end not providing valid bundles or providing valid illegal templates or due to MLX bundle and resteers to non-0 syllable."}, #define PME_MONT_SYLL_NOT_DISPERSED_IMPL_OR_MLX 600 { "SYLL_NOT_DISPERSED_IMPL_OR_MLX", {0xa004e}, 0xfff0, 5, {0xffff0001}, "Syllables Not Dispersed -- Count syllables not dispersed due to implicit stop bits or to MLX bundle and resteers to non-0 syllable."}, #define PME_MONT_SYLL_NOT_DISPERSED_MLX 601 { "SYLL_NOT_DISPERSED_MLX", {0x8004e}, 0xfff0, 5, {0xffff0001}, "Syllables Not Dispersed -- Count syllables not dispersed due to MLX bundle and resteers to non-0 syllable. Dispersal takes a 1 syllable hit for each MLX bundle . Dispersal could take 0-2 syllable hit depending on which syllable we resteer to. Bundle 1 with front-end fault which is split, is counted here (0-2 syllable hit)."}, #define PME_MONT_SYLL_OVERCOUNT_ALL 602 { "SYLL_OVERCOUNT_ALL", {0x3004f}, 0xfff0, 2, {0xffff0001}, "Syllables Overcounted -- syllables overcounted in implicit & explicit bucket"}, #define PME_MONT_SYLL_OVERCOUNT_EXPL 603 { "SYLL_OVERCOUNT_EXPL", {0x1004f}, 0xfff0, 2, {0xffff0001}, "Syllables Overcounted -- Only syllables overcounted in the explicit bucket"}, #define PME_MONT_SYLL_OVERCOUNT_IMPL 604 { "SYLL_OVERCOUNT_IMPL", {0x2004f}, 0xfff0, 2, {0xffff0001}, "Syllables Overcounted -- Only syllables overcounted in the implicit bucket"}, #define PME_MONT_THREAD_SWITCH_CYCLE_ALL_GATED 605 { "THREAD_SWITCH_CYCLE_ALL_GATED", {0x6000e}, 0xfff0, 1, {0xffff0000}, "Thread switch overhead cycles. -- Cycles TSs are gated due to any reason"}, #define PME_MONT_THREAD_SWITCH_CYCLE_ANYSTALL 606 { "THREAD_SWITCH_CYCLE_ANYSTALL", {0x3000e}, 0xfff0, 1, {0xffff0000}, "Thread switch overhead cycles. -- Cycles TSs are stalled due to any reason"}, #define PME_MONT_THREAD_SWITCH_CYCLE_CRAB 607 { "THREAD_SWITCH_CYCLE_CRAB", {0x1000e}, 0xfff0, 1, {0xffff0000}, "Thread switch overhead cycles. -- Cycles TSs are stalled due to CRAB operation"}, #define PME_MONT_THREAD_SWITCH_CYCLE_L2D 608 { "THREAD_SWITCH_CYCLE_L2D", {0x2000e}, 0xfff0, 1, {0xffff0000}, "Thread switch overhead cycles. -- Cycles TSs are stalled due to L2D return operation"}, #define PME_MONT_THREAD_SWITCH_CYCLE_PCR 609 { "THREAD_SWITCH_CYCLE_PCR", {0x4000e}, 0xfff0, 1, {0xffff0000}, "Thread switch overhead cycles. -- Cycles we run with PCR.sd set"}, #define PME_MONT_THREAD_SWITCH_CYCLE_TOTAL 610 { "THREAD_SWITCH_CYCLE_TOTAL", {0x7000e}, 0xfff0, 1, {0xffff0000}, "Thread switch overhead cycles. -- Total time from TS opportunity is seized to TS happens."}, #define PME_MONT_THREAD_SWITCH_EVENTS_ALL 611 { "THREAD_SWITCH_EVENTS_ALL", {0x7000c}, 0xfff0, 1, {0xffff0000}, "Thread switch events. -- All taken TSs"}, #define PME_MONT_THREAD_SWITCH_EVENTS_DBG 612 { "THREAD_SWITCH_EVENTS_DBG", {0x5000c}, 0xfff0, 1, {0xffff0000}, "Thread switch events. -- TSs due to debug operations"}, #define PME_MONT_THREAD_SWITCH_EVENTS_HINT 613 { "THREAD_SWITCH_EVENTS_HINT", {0x3000c}, 0xfff0, 1, {0xffff0000}, "Thread switch events. -- TSs due to hint instruction"}, #define PME_MONT_THREAD_SWITCH_EVENTS_L3MISS 614 { "THREAD_SWITCH_EVENTS_L3MISS", {0x1000c}, 0xfff0, 1, {0xffff0000}, "Thread switch events. -- TSs due to L3 miss"}, #define PME_MONT_THREAD_SWITCH_EVENTS_LP 615 { "THREAD_SWITCH_EVENTS_LP", {0x4000c}, 0xfff0, 1, {0xffff0000}, "Thread switch events. -- TSs due to low power operation"}, #define PME_MONT_THREAD_SWITCH_EVENTS_MISSED 616 { "THREAD_SWITCH_EVENTS_MISSED", {0xc}, 0xfff0, 1, {0xffff0000}, "Thread switch events. -- TS opportunities missed"}, #define PME_MONT_THREAD_SWITCH_EVENTS_TIMER 617 { "THREAD_SWITCH_EVENTS_TIMER", {0x2000c}, 0xfff0, 1, {0xffff0000}, "Thread switch events. -- TSs due to time out"}, #define PME_MONT_THREAD_SWITCH_GATED_ALL 618 { "THREAD_SWITCH_GATED_ALL", {0x7000d}, 0xfff0, 1, {0xffff0000}, "Thread switches gated -- TSs gated for any reason"}, #define PME_MONT_THREAD_SWITCH_GATED_FWDPRO 619 { "THREAD_SWITCH_GATED_FWDPRO", {0x5000d}, 0xfff0, 1, {0xffff0000}, "Thread switches gated -- Gated due to forward progress reasons"}, #define PME_MONT_THREAD_SWITCH_GATED_LP 620 { "THREAD_SWITCH_GATED_LP", {0x1000d}, 0xfff0, 1, {0xffff0000}, "Thread switches gated -- TSs gated due to LP"}, #define PME_MONT_THREAD_SWITCH_GATED_PIPE 621 { "THREAD_SWITCH_GATED_PIPE", {0x4000d}, 0xfff0, 1, {0xffff0000}, "Thread switches gated -- Gated due to pipeline operations"}, #define PME_MONT_THREAD_SWITCH_STALL_GTE_1024 622 { "THREAD_SWITCH_STALL_GTE_1024", {0x8000f}, 0xfff0, 1, {0xffff0000}, "Thread switch stall -- Thread switch stall >= 1024 cycles"}, #define PME_MONT_THREAD_SWITCH_STALL_GTE_128 623 { "THREAD_SWITCH_STALL_GTE_128", {0x5000f}, 0xfff0, 1, {0xffff0000}, "Thread switch stall -- Thread switch stall >= 128 cycles"}, #define PME_MONT_THREAD_SWITCH_STALL_GTE_16 624 { "THREAD_SWITCH_STALL_GTE_16", {0x2000f}, 0xfff0, 1, {0xffff0000}, "Thread switch stall -- Thread switch stall >= 16 cycles"}, #define PME_MONT_THREAD_SWITCH_STALL_GTE_2048 625 { "THREAD_SWITCH_STALL_GTE_2048", {0x9000f}, 0xfff0, 1, {0xffff0000}, "Thread switch stall -- Thread switch stall >= 2048 cycles"}, #define PME_MONT_THREAD_SWITCH_STALL_GTE_256 626 { "THREAD_SWITCH_STALL_GTE_256", {0x6000f}, 0xfff0, 1, {0xffff0000}, "Thread switch stall -- Thread switch stall >= 256 cycles"}, #define PME_MONT_THREAD_SWITCH_STALL_GTE_32 627 { "THREAD_SWITCH_STALL_GTE_32", {0x3000f}, 0xfff0, 1, {0xffff0000}, "Thread switch stall -- Thread switch stall >= 32 cycles"}, #define PME_MONT_THREAD_SWITCH_STALL_GTE_4 628 { "THREAD_SWITCH_STALL_GTE_4", {0xf}, 0xfff0, 1, {0xffff0000}, "Thread switch stall -- Thread switch stall >= 4 cycles"}, #define PME_MONT_THREAD_SWITCH_STALL_GTE_4096 629 { "THREAD_SWITCH_STALL_GTE_4096", {0xa000f}, 0xfff0, 1, {0xffff0000}, "Thread switch stall -- Thread switch stall >= 4096 cycles"}, #define PME_MONT_THREAD_SWITCH_STALL_GTE_512 630 { "THREAD_SWITCH_STALL_GTE_512", {0x7000f}, 0xfff0, 1, {0xffff0000}, "Thread switch stall -- Thread switch stall >= 512 cycles"}, #define PME_MONT_THREAD_SWITCH_STALL_GTE_64 631 { "THREAD_SWITCH_STALL_GTE_64", {0x4000f}, 0xfff0, 1, {0xffff0000}, "Thread switch stall -- Thread switch stall >= 64 cycles"}, #define PME_MONT_THREAD_SWITCH_STALL_GTE_8 632 { "THREAD_SWITCH_STALL_GTE_8", {0x1000f}, 0xfff0, 1, {0xffff0000}, "Thread switch stall -- Thread switch stall >= 8 cycles"}, #define PME_MONT_UC_LOADS_RETIRED 633 { "UC_LOADS_RETIRED", {0xcf}, 0xfff0, 4, {0x5310007}, "Retired Uncacheable Loads"}, #define PME_MONT_UC_STORES_RETIRED 634 { "UC_STORES_RETIRED", {0xd0}, 0xfff0, 2, {0x5410007}, "Retired Uncacheable Stores"}, #define PME_MONT_IA64_INST_RETIRED 635 { "IA64_INST_RETIRED", {0x8}, 0xfff0, 6, {0xffff0003}, "Retired IA-64 Instructions -- Retired IA-64 Instructions -- Alias to IA64_INST_RETIRED_THIS"}, #define PME_MONT_BRANCH_EVENT 636 { "BRANCH_EVENT", {0x111}, 0xfff0, 1, {0xffff0003}, "Execution Trace Buffer Event Captured. Alias to ETB_EVENT"}, }; #define PME_MONT_EVENT_COUNT (sizeof(montecito_pe)/sizeof(pme_mont_entry_t)) libpfm-4.9.0/lib/events/intel_hswep_unc_ubo_events.h0000664000175000017500000000465213223402656022467 0ustar eranianeranian/* * Copyright (c) 2014 Google Inc. All rights reserved * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * PMU: hswep_unc_ubo (Intel Haswell-EP U-Box uncore PMU) */ static const intel_x86_umask_t hswep_unc_u_event_msg[]={ { .uname = "DOORBELL_RCVD", .udesc = "TBD", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t hswep_unc_u_phold_cycles[]={ { .uname = "ASSERT_TO_ACK", .udesc = "Number of cycles asserted to ACK", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_entry_t intel_hswep_unc_u_pe[]={ { .name = "UNC_U_EVENT_MSG", .desc = "VLW Received", .code = 0x42, .cntmsk = 0x3, .ngrp = 1, .modmsk = HSWEP_UNC_UBO_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_u_event_msg), .umasks = hswep_unc_u_event_msg }, { .name = "UNC_U_PHOLD_CYCLES", .desc = "Cycles PHOLD asserts to Ack", .code = 0x45, .cntmsk = 0x3, .ngrp = 1, .modmsk = HSWEP_UNC_UBO_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_u_phold_cycles), .umasks = hswep_unc_u_phold_cycles }, { .name = "UNC_U_RACU_REQUESTS", .desc = "RACU requests", .code = 0x46, .cntmsk = 0x3, .modmsk = HSWEP_UNC_UBO_ATTRS, }, }; libpfm-4.9.0/lib/events/intel_bdx_unc_ubo_events.h0000664000175000017500000000471613223402656022117 0ustar eranianeranian/* * Copyright (c) 2017 Google Inc. All rights reserved * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * PMU: bdx_unc_ubo */ static intel_x86_umask_t bdx_unc_u_event_msg[]={ { .uname = "DOORBELL_RCVD", .ucode = 0x800, .udesc = "VLW Received", .uflags = INTEL_X86_DFL, }, }; static intel_x86_umask_t bdx_unc_u_phold_cycles[]={ { .uname = "ASSERT_TO_ACK", .ucode = 0x100, .udesc = "Cycles PHOLD Assert to Ack. Assert to ACK", .uflags = INTEL_X86_DFL, }, }; static intel_x86_entry_t intel_bdx_unc_u_pe[]={ { .name = "UNC_U_EVENT_MSG", .code = 0x42, .desc = "Virtual Logical Wire (legacy) message were received from uncore", .modmsk = BDX_UNC_UBO_ATTRS, .cntmsk = 0x3, .ngrp = 1, .umasks = bdx_unc_u_event_msg, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_u_event_msg), }, { .name = "UNC_U_PHOLD_CYCLES", .code = 0x45, .desc = "PHOLD cycles. Filter from source CoreID.", .modmsk = BDX_UNC_UBO_ATTRS, .cntmsk = 0x3, .ngrp = 1, .umasks = bdx_unc_u_phold_cycles, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_u_phold_cycles), }, { .name = "UNC_U_RACU_REQUESTS", .code = 0x46, .desc = "Number outstanding register requests within message channel tracker", .modmsk = BDX_UNC_UBO_ATTRS, .cntmsk = 0x3, }, }; libpfm-4.9.0/lib/events/intel_ivbep_unc_ha_events.h0000664000175000017500000006473713223402656022263 0ustar eranianeranian/* * Copyright (c) 2014 Google Inc. All rights reserved * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * This file has been automatically generated. * * PMU: ivbep_unc_ha (Intel IvyBridge-EP HA uncore PMU) */ static const intel_x86_umask_t ivbep_unc_h_conflict_cycles[]={ { .uname = "CONFLICT", .udesc = "Number of cycles that we are handling conflicts", .ucode = 0x200, }, { .uname = "LAST", .udesc = "Count every last conflictor in conflict chain. Can be used to compute average conflict chain length", .ucode = 0x400, }, { .uname = "CMP_FWDS", .udesc = "Count the number of cmp_fwd. This gives the number of late conflicts", .ucode = 0x1000, }, { .uname = "ACKCNFLTS", .udesc = "Count the number Acknflts", .ucode = 0x800, }, }; static const intel_x86_umask_t ivbep_unc_h_directory_lookup[]={ { .uname = "NO_SNP", .udesc = "Snoop not needed", .ucode = 0x200, }, { .uname = "SNOOP", .udesc = "SNooop needed", .ucode = 0x100, }, }; static const intel_x86_umask_t ivbep_unc_h_bypass_imc[]={ { .uname = "TAKEN", .udesc = "Bypass taken", .ucode = 0x200, }, { .uname = "NOT_TAKEN", .udesc = "Bypass not taken", .ucode = 0x100, }, }; static const intel_x86_umask_t ivbep_unc_h_directory_update[]={ { .uname = "ANY", .udesc = "Counts any directory update", .ucode = 0x300, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "CLEAR", .udesc = "Directory clears", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "SET", .udesc = "Directory set", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t ivbep_unc_h_igr_no_credit_cycles[]={ { .uname = "AD_QPI0", .udesc = "AD to QPI link 0", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "AD_QPI1", .udesc = "AD to QPI link 1", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "BL_QPI0", .udesc = "BL to QPI link 0", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "BL_QPI1", .udesc = "BL to QPI link 1", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t ivbep_unc_h_imc_writes[]={ { .uname = "ALL", .udesc = "Counts all writes", .ucode = 0xf00, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "FULL", .udesc = "Counts full line non ISOCH", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "FULL_ISOCH", .udesc = "Counts ISOCH full line", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "PARTIAL", .udesc = "Counts partial non-ISOCH", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "PARTIAL_ISOCH", .udesc = "Counts ISOCH partial", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t ivbep_unc_h_imc_reads[]={ { .uname = "NORMAL", .udesc = "Normal priority", .ucode = 0x100, .uflags = INTEL_X86_DFL, }, }; static const intel_x86_umask_t ivbep_unc_h_requests[]={ { .uname = "READS", .udesc = "Counts incoming read requests. Good proxy for LLC read misses, incl. RFOs", .ucode = 0x300, .uflags = INTEL_X86_NCOMBO, }, { .uname = "READS_LOCAL", .udesc = "Counts incoming read requests coming from local socket. Good proxy for LLC read misses, incl. RFOs from the local socket", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "READS_REMOTE", .udesc = "Counts incoming read requests coming from remote socket. Good proxy for LLC read misses, incl. RFOs from the remote socket", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "WRITES", .udesc = "Counts incoming writes", .ucode = 0xc00, .uflags = INTEL_X86_NCOMBO, }, { .uname = "WRITES_LOCAL", .udesc = "Counts incoming writes from local socket", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "WRITES_REMOTE", .udesc = "Counts incoming writes from remote socket", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "INVITOE_LOCAL", .udesc = "Counts InvItoE coming from local socket", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "INVITOE_REMOTE", .udesc = "Counts InvItoE coming from remote socket", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO, } }; static const intel_x86_umask_t ivbep_unc_h_rpq_cycles_no_reg_credits[]={ { .uname = "CHN0", .udesc = "Channel 0", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "CHN1", .udesc = "Channel 1", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "CHN2", .udesc = "channel 2", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "CHN3", .udesc = "Chanell 3", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t ivbep_unc_h_tad_requests_g0[]={ { .uname = "REGION0", .udesc = "Counts for TAD Region 0", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "REGION1", .udesc = "Counts for TAD Region 1", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "REGION2", .udesc = "Counts for TAD Region 2", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "REGION3", .udesc = "Counts for TAD Region 3", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, { .uname = "REGION4", .udesc = "Counts for TAD Region 4", .ucode = 0x1000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "REGION5", .udesc = "Counts for TAD Region 5", .ucode = 0x2000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "REGION6", .udesc = "Counts for TAD Region 6", .ucode = 0x4000, .uflags = INTEL_X86_NCOMBO, }, { .uname = "REGION7", .udesc = "Counts for TAD Region 7", .ucode = 0x8000, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t ivbep_unc_h_tad_requests_g1[]={ { .uname = "REGION8", .udesc = "Counts for TAD Region 8", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "REGION9", .udesc = "Counts for TAD Region 9", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "REGION10", .udesc = "Counts for TAD Region 10", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, { .uname = "REGION11", .udesc = "Counts for TAD Region 11", .ucode = 0x800, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t ivbep_unc_h_snoop_resp[]={ { .uname = "RSPI", .udesc = "Filters for snoop responses of RspI. RspI is returned when the remote cache does not have the data or when the remote cache silently evicts data (e.g. RFO hit non-modified line)", .ucode = 0x100, }, { .uname = "RSPS", .udesc = "Filters for snoop responses of RspS. RspS is returned when the remote cache has the data but is not forwarding it. It is a way to let the requesting socket know that it cannot allocate the data in E-state", .ucode = 0x200, }, { .uname = "RSPIFWD", .udesc = "Filters for snoop responses of RspIFwd. RspIFwd is returned when the remote cache agent forwards data and the requesting agent is able to acquire the data in E or M state. This is commonly returned with RFO transacations. It can be either HitM or HitFE", .ucode = 0x400, }, { .uname = "RSPSFWD", .udesc = "Filters for snoop responses of RspSFwd. RspSFwd is returned when the remote cache agent forwards data but holds on to its current copy. This is common for data and code reads that hit in a remote socket in E or F state", .ucode = 0x800, }, { .uname = "RSP_WB", .udesc = "Filters for snoop responses of RspIWB or RspSWB. This is returned when a non-RFO requests hits in M-state. Data and code reads can return either RspIWB or RspSWB depending on how the system has been configured. InvItoE transactions will also return RspIWB because they must acquire ownership", .ucode = 0x1000, }, { .uname = "RSP_FWD_WB", .udesc = "Filters for snoop responses of RspxFwdxWB. This snoop response is only used in 4s systems. It is used when a snoop HITM in a remote caching agent and it directly forwards data to a requester and simultaneously returns data to the home to be written back to memory", .ucode = 0x2000, }, { .uname = "RSPCNFLCT", .udesc = "Filters for snoop responses of RspConflict. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CMAs that caching agent. This triggers the conflict resolution hardware. This covers both RspConflct and RspCnflctWBI", .ucode = 0x4000, }, }; static const intel_x86_umask_t ivbep_unc_h_txr_ad_cycles_full[]={ { .uname = "ALL", .udesc = "Counts cycles full from both schedulers", .ucode = 0x300, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "SCHED0", .udesc = "Counts cycles full from scheduler bank 0", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "SCHED1", .udesc = "Counts cycles full from scheduler bank 1", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t ivbep_unc_h_txr_bl_occupancy[]={ { .uname = "SCHED0", .udesc = "Counts cycles full from scheduler bank 0", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "SCHED1", .udesc = "Counts cycles full from scheduler bank 1", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t ivbep_unc_h_txr_ak_cycles_full[]={ { .uname = "ALL", .udesc = "Counts cycles from both schedulers", .ucode = 0x300, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "SCHED0", .udesc = "Counts cycles from scheduler bank 0", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "SCHED1", .udesc = "Counts cycles from scheduler bank 1", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t ivbep_unc_h_txr_bl[]={ { .uname = "DRS_CACHE", .udesc = "Counts data being sent to the cache", .ucode = 0x100, .uflags = INTEL_X86_NCOMBO, }, { .uname = "DRS_CORE", .udesc = "Counts data being sent directly to the requesting core", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "DRS_QPI", .udesc = "Counts data being sent to a remote socket over QPI", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, }; #if 0 static const intel_x86_umask_t ivbep_unc_h_addr_opc_match[]={ { .uname = "FILT", .udesc = "Number of addr and opcode matches (opc via opc= or address via addr= modifiers)", .ucode = 0x300, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL | INTEL_X86_ADDR, }, }; #endif static const intel_x86_umask_t ivbep_unc_h_bt_occupancy[]={ { .uname = "LOCAL", .udesc = "Local", .ucode = 0x100, }, { .uname = "REMOTE", .udesc = "Remote", .ucode = 0x200, }, { .uname = "READS_REMOTE", .udesc = "Reads remote", .ucode = 0x800, }, { .uname = "WRITES_LOCAL", .udesc = "Writes local", .ucode = 0x1000, }, { .uname = "WRITES_REMOTE", .udesc = "Writes remote", .ucode = 0x2000, }, }; static const intel_x86_umask_t ivbep_unc_h_osb[]={ { .uname = "REMOTE", .udesc = "Remote", .ucode = 0x800, }, { .uname = "READS_LOCAL", .udesc = "Local reads", .ucode = 0x200, }, { .uname = "INVITOE_LOCAL", .udesc = "Local InvItoE", .ucode = 0x400, } }; static const intel_x86_umask_t ivbep_unc_h_osb_edr[]={ { .uname = "ALL", .udesc = "All data returns", .ucode = 0x100, .uflags = INTEL_X86_DFL | INTEL_X86_NCOMBO, }, { .uname = "READS_LOCAL_I", .udesc = "Reads to local I", .ucode = 0x200, }, { .uname = "READS_REMOTE_I", .udesc = "Reads to remote I", .ucode = 0x400, }, { .uname = "READS_LOCAL_S", .udesc = "Reads to local S", .ucode = 0x800, }, { .uname = "READS_REMOTE_S", .udesc = "Reads to remote S", .ucode = 0x1000, } }; static const intel_x86_umask_t ivbep_unc_h_ring_ad_used[]={ { .uname = "CCW_VR0_EVEN", .udesc = "Counter-clockwise and even ring polarity on virtual ring 0", .ucode = 0x400, }, { .uname = "CCW_VR0_ODD", .udesc = "Counter-clockwise and odd ring polarity on virtual ring 0", .ucode = 0x800, }, { .uname = "CW_VR0_EVEN", .udesc = "Clockwise and even ring polarity on virtual ring 0", .ucode = 0x100, }, { .uname = "CW_VR0_ODD", .udesc = "Clockwise and odd ring polarity on virtual ring 0", .ucode = 0x200, }, { .uname = "CCW_VR1_EVEN", .udesc = "Counter-clockwise and even ring polarity on virtual ring 1", .ucode = 0x400, }, { .uname = "CCW_VR1_ODD", .udesc = "Counter-clockwise and odd ring polarity on virtual ring 1", .ucode = 0x800, }, { .uname = "CW_VR1_EVEN", .udesc = "Clockwise and even ring polarity on virtual ring 1", .ucode = 0x100, }, { .uname = "CW_VR1_ODD", .udesc = "Clockwise and odd ring polarity on virtual ring 1", .ucode = 0x200, }, { .uname = "CW", .udesc = "Clockwise with any polarity on either virtual rings", .ucode = 0x3300, }, { .uname = "CCW", .udesc = "Counter-clockwise with any polarity on either virtual rings", .ucode = 0xcc00, }, }; static const intel_x86_umask_t ivbep_unc_h_snp_resp_recv_local[]={ { .uname = "RSPI", .udesc = "Filters for snoop responses of RspI. RspI is returned when the remote cache does not have the data or when the remote cache silently evicts data (e.g. RFO hit non-modified line)", .ucode = 0x100, }, { .uname = "RSPS", .udesc = "Filters for snoop responses of RspS. RspS is returned when the remote cache has the data but is not forwarding it. It is a way to let the requesting socket know that it cannot allocate the data in E-state", .ucode = 0x200, }, { .uname = "RSPIFWD", .udesc = "Filters for snoop responses of RspIFwd. RspIFwd is returned when the remote cache agent forwards data and the requesting agent is able to acquire the data in E or M state. This is commonly returned with RFO transacations. It can be either HitM or HitFE", .ucode = 0x400, }, { .uname = "RSPSFWD", .udesc = "Filters for snoop responses of RspSFwd. RspSFwd is returned when the remote cache agent forwards data but holds on to its current copy. This is common for data and code reads that hit in a remote socket in E or F state", .ucode = 0x800, }, { .uname = "RSP_WB", .udesc = "Filters for snoop responses of RspIWB or RspSWB. This is returned when a non-RFO requests hits in M-state. Data and code reads can return either RspIWB or RspSWB depending on how the system has been configured. InvItoE transactions will also return RspIWB because they must acquire ownership", .ucode = 0x1000, }, { .uname = "RSP_FWD_WB", .udesc = "Filters for snoop responses of RspxFwdxWB. This snoop response is only used in 4s systems. It is used when a snoop HITM in a remote caching agent and it directly forwards data to a requester and simultaneously returns data to the home to be written back to memory", .ucode = 0x2000, }, { .uname = "RSPCNFLCT", .udesc = "Filters for snoop responses of RspConflict. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CMAs that caching agent. This triggers the conflict resolution hardware. This covers both RspConflct and RspCnflctWBI", .ucode = 0x4000, }, { .uname = "OTHER", .udesc = "Filters all other snoop responses", .ucode = 0x8000, }, }; static const intel_x86_umask_t ivbep_unc_h_txr_ak[]={ { .uname = "NDR", .udesc = "Number of outbound NDR (non-data response) transactions send on the AK ring. AK NDR is used for messages to the local socket", .ucode = 0x100, }, { .uname = "CRD_CBO", .udesc = "Number of outbound CDR transactions send on the AK ring to CBO", .ucode = 0x200, }, { .uname = "CRD_QPI", .udesc = "Number of outbound CDR transactions send on the AK ring to QPI", .ucode = 0x400, }, }; static const intel_x86_umask_t ivbep_unc_h_iodc_conflicts[]={ { .uname = "ANY", .udesc = "Any conflict", .ucode = 0x100, .uflags = INTEL_X86_DFL | INTEL_X86_NCOMBO, }, { .uname = "LAST", .udesc = "Last conflict", .ucode = 0x400, } }; static const intel_x86_entry_t intel_ivbep_unc_h_pe[]={ { .name = "UNC_H_CLOCKTICKS", .desc = "HA Uncore clockticks", .modmsk = IVBEP_UNC_HA_ATTRS, .cntmsk = 0xf, .code = 0x00, }, { .name = "UNC_H_CONFLICT_CYCLES", .desc = "Conflict Checks", .code = 0xb, .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_h_conflict_cycles), .umasks = ivbep_unc_h_conflict_cycles, }, { .name = "UNC_H_DIRECT2CORE_COUNT", .desc = "Direct2Core Messages Sent", .code = 0x11, .cntmsk = 0xf, .modmsk = IVBEP_UNC_HA_ATTRS, }, { .name = "UNC_H_DIRECT2CORE_CYCLES_DISABLED", .desc = "Cycles when Direct2Core was Disabled", .code = 0x12, .cntmsk = 0xf, .modmsk = IVBEP_UNC_HA_ATTRS, }, { .name = "UNC_H_DIRECT2CORE_TXN_OVERRIDE", .desc = "Number of Reads that had Direct2Core Overridden", .code = 0x13, .cntmsk = 0xf, .modmsk = IVBEP_UNC_HA_ATTRS, }, { .name = "UNC_H_DIRECTORY_LOOKUP", .desc = "Directory Lookups", .code = 0xc, .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_h_directory_lookup), .umasks = ivbep_unc_h_directory_lookup }, { .name = "UNC_H_DIRECTORY_UPDATE", .desc = "Directory Updates", .code = 0xd, .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_h_directory_update), .umasks = ivbep_unc_h_directory_update }, { .name = "UNC_H_IGR_NO_CREDIT_CYCLES", .desc = "Cycles without QPI Ingress Credits", .code = 0x22, .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_h_igr_no_credit_cycles), .umasks = ivbep_unc_h_igr_no_credit_cycles }, { .name = "UNC_H_IMC_RETRY", .desc = "Retry Events", .code = 0x1e, .cntmsk = 0xf, .modmsk = IVBEP_UNC_HA_ATTRS, }, { .name = "UNC_H_IMC_WRITES", .desc = "HA to IMC Full Line Writes Issued", .code = 0x1a, .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_h_imc_writes), .umasks = ivbep_unc_h_imc_writes }, { .name = "UNC_H_IMC_READS", .desc = "HA to IMC normal priority reads issued", .code = 0x17, .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_h_imc_reads), .umasks = ivbep_unc_h_imc_reads }, { .name = "UNC_H_REQUESTS", .desc = "Read and Write Requests", .code = 0x1, .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_h_requests), .umasks = ivbep_unc_h_requests }, { .name = "UNC_H_RPQ_CYCLES_NO_REG_CREDITS", .desc = "IMC RPQ Credits Empty", .code = 0x15, .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_h_rpq_cycles_no_reg_credits), .umasks = ivbep_unc_h_rpq_cycles_no_reg_credits }, { .name = "UNC_H_TAD_REQUESTS_G0", .desc = "HA Requests to a TAD Region", .code = 0x1b, .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_h_tad_requests_g0), .umasks = ivbep_unc_h_tad_requests_g0 }, { .name = "UNC_H_TAD_REQUESTS_G1", .desc = "HA Requests to a TAD Region", .code = 0x1c, .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_h_tad_requests_g1), .umasks = ivbep_unc_h_tad_requests_g1 }, { .name = "UNC_H_TXR_AD_CYCLES_FULL", .desc = "AD Egress Full", .code = 0x2a, .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_h_txr_ad_cycles_full), .umasks = ivbep_unc_h_txr_ad_cycles_full }, { .name = "UNC_H_TXR_AK_CYCLES_FULL", .desc = "AK Egress Full", .code = 0x32, .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_h_txr_ak_cycles_full), .umasks = ivbep_unc_h_txr_ak_cycles_full }, { .name = "UNC_H_TXR_AK", .desc = "Outbound Ring Transactions on AK", .code = 0xe, .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_h_txr_ak), .umasks = ivbep_unc_h_txr_ak }, { .name = "UNC_H_TXR_BL", .desc = "Outbound DRS Ring Transactions to Cache", .code = 0x10, .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_h_txr_bl), .umasks = ivbep_unc_h_txr_bl }, { .name = "UNC_H_TXR_BL_CYCLES_FULL", .desc = "BL Egress Full", .code = 0x36, .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_h_txr_ak_cycles_full), .umasks = ivbep_unc_h_txr_ak_cycles_full, /* identical to snbep_unc_h_txr_ak_cycles_full */ }, { .name = "UNC_H_WPQ_CYCLES_NO_REG_CREDITS", .desc = "HA IMC CHN0 WPQ Credits Empty", .code = 0x18, .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_h_rpq_cycles_no_reg_credits), .umasks = ivbep_unc_h_rpq_cycles_no_reg_credits, /* shared */ }, { .name = "UNC_H_BT_BYPASS", .desc = "Backup Tracker bypass", .code = 0x52, .cntmsk = 0xf, .modmsk = IVBEP_UNC_HA_ATTRS, }, { .name = "UNC_H_BYPASS_IMC", .desc = "HA to IMC bypass", .code = 0x14, .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_h_bypass_imc), .umasks = ivbep_unc_h_bypass_imc, }, { .name = "UNC_H_BT_CYCLES_NE", .desc = "Backup Tracker cycles not empty", .code = 0x42, .cntmsk = 0xf, .modmsk = IVBEP_UNC_HA_ATTRS, }, { .name = "UNC_H_BT_OCCUPANCY", .desc = "Backup Tracker inserts", .code = 0x43, .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_h_bt_occupancy), .umasks = ivbep_unc_h_bt_occupancy, }, { .name = "UNC_H_IGR_AD_QPI2", .desc = "AD QPI Link 2 credit accumulator", .code = 0x59, .cntmsk = 0xf, .modmsk = IVBEP_UNC_HA_ATTRS, }, { .name = "UNC_H_IGR_BL_QPI2", .desc = "BL QPI Link 2 credit accumulator", .code = 0x5a, .cntmsk = 0xf, .modmsk = IVBEP_UNC_HA_ATTRS, }, { .name = "UNC_H_IODC_INSERTS", .desc = "IODC inserts", .code = 0x56, .cntmsk = 0xf, .modmsk = IVBEP_UNC_HA_ATTRS, }, { .name = "UNC_H_IODC_CONFLICTS", .desc = "IODC conflicts", .code = 0x57, .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_h_iodc_conflicts), .umasks = ivbep_unc_h_iodc_conflicts, }, { .name = "UNC_H_IODC_OLEN_WBMTOI", .desc = "IODC zero length writes", .code = 0x58, .cntmsk = 0xf, .modmsk = IVBEP_UNC_HA_ATTRS, }, { .name = "UNC_H_OSB", .desc = "OSB snoop broadcast", .code = 0x53, .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_h_osb), .umasks = ivbep_unc_h_osb, }, { .name = "UNC_H_OSB_EDR", .desc = "OSB early data return", .code = 0x54, .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_h_osb_edr), .umasks = ivbep_unc_h_osb_edr, }, { .name = "UNC_H_RING_AD_USED", .desc = "AD ring in use", .code = 0x3e, .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_h_ring_ad_used), .umasks = ivbep_unc_h_ring_ad_used, }, { .name = "UNC_H_RING_AK_USED", .desc = "AK ring in use", .code = 0x3f, .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_h_ring_ad_used), /* shared */ .umasks = ivbep_unc_h_ring_ad_used, }, { .name = "UNC_H_RING_BL_USED", .desc = "BL ring in use", .code = 0x40, .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_h_ring_ad_used), /* shared */ .umasks = ivbep_unc_h_ring_ad_used, }, { .name = "UNC_H_DIRECTORY_LAT_OPT", .desc = "Directory latency optimization data return path taken", .code = 0x41, .cntmsk = 0xf, .modmsk = IVBEP_UNC_HA_ATTRS, }, { .name = "UNC_H_SNP_RESP_RECV_LOCAL", .desc = "Snoop responses received local", .code = 0x60, .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_h_snp_resp_recv_local), .umasks = ivbep_unc_h_snp_resp_recv_local, }, { .name = "UNC_H_TXR_BL_OCCUPANCY", .desc = "BL Egress occupancy", .code = 0x34, .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_h_txr_bl_occupancy), .umasks = ivbep_unc_h_txr_bl_occupancy, }, { .name = "UNC_H_SNOOP_RESP", .desc = "Snoop responses received", .code = 0x21, .cntmsk = 0xf, .ngrp = 1, .modmsk = IVBEP_UNC_HA_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_h_snoop_resp), .umasks = ivbep_unc_h_snoop_resp }, }; libpfm-4.9.0/lib/events/intel_snb_unc_events.h0000664000175000017500000001342313223402656021252 0ustar eranianeranian/* * Copyright (c) 2012 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * PMU: snb_unc (Intel Sandy Bridge uncore PMU) */ static const intel_x86_umask_t snb_unc_cbo_xsnp_response[]={ { .uname = "MISS", .udesc = "Number of snoop misses", .ucode = 0x100, .grpid = 0, }, { .uname = "INVAL", .udesc = "Number of snoop invalidates of a non-modified line", .ucode = 0x200, .grpid = 0, }, { .uname = "HIT", .udesc = "Number of snoop hits of a non-modified line", .ucode = 0x400, .grpid = 0, }, { .uname = "HITM", .udesc = "Number of snoop hits of a modified line", .ucode = 0x800, .grpid = 0, }, { .uname = "INVAL_M", .udesc = "Number of snoop invalidates of a modified line", .ucode = 0x1000, .grpid = 0, }, { .uname = "ANY_SNP", .udesc = "Number of snoops", .ucode = 0x1f00, .grpid = 0, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "EXTERNAL_FILTER", .udesc = "Filter on cross-core snoops initiated by this Cbox due to external snoop request", .ucode = 0x2000, .grpid = 1, .uflags = INTEL_X86_NCOMBO, }, { .uname = "XCORE_FILTER", .udesc = "Filter on cross-core snoops initiated by this Cbox due to processor core memory request", .ucode = 0x4000, .grpid = 1, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "EVICTION_FILTER", .udesc = "Filter on cross-core snoops initiated by this Cbox due to LLC eviction", .ucode = 0x8000, .grpid = 1, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t snb_unc_cbo_cache_lookup[]={ { .uname = "STATE_M", .udesc = "Number of LLC lookup requests for a line in modified state", .ucode = 0x100, .grpid = 0, .uflags = INTEL_X86_NCOMBO, }, { .uname = "STATE_E", .udesc = "Number of LLC lookup requests for a line in exclusive state", .ucode = 0x200, .grpid = 0, .uflags = INTEL_X86_NCOMBO, }, { .uname = "STATE_S", .udesc = "Number of LLC lookup requests for a line in shared state", .ucode = 0x400, .grpid = 0, .uflags = INTEL_X86_NCOMBO, }, { .uname = "STATE_I", .udesc = "Number of LLC lookup requests for a line in invalid state", .ucode = 0x800, .grpid = 0, .uflags = INTEL_X86_NCOMBO, }, { .uname = "STATE_MESI", .udesc = "Number of LLC lookup requests for a line", .ucode = 0xf00, .grpid = 0, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "READ_FILTER", .udesc = "Filter on processor core initiated cacheable read requests", .ucode = 0x1000, .grpid = 1, .uflags = INTEL_X86_NCOMBO, }, { .uname = "WRITE_FILTER", .udesc = "Filter on processor core initiated cacheable write requests", .ucode = 0x2000, .grpid = 1, .uflags = INTEL_X86_NCOMBO, }, { .uname = "EXTSNP_FILTER", .udesc = "Filter on external snoop requests", .ucode = 0x4000, .grpid = 1, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ANY_FILTER", .udesc = "Filter on any IRQ or IPQ initiated requests including uncacheable, non-coherent requests", .ucode = 0x8000, .grpid = 1, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_entry_t intel_snb_unc_cbo0_pe[]={ { .name = "UNC_CLOCKTICKS", .desc = "uncore clock ticks", .cntmsk = 1ULL << 32, .code = 0xff, /* perf_event pseudo encoding */ .flags = INTEL_X86_FIXED, }, { .name = "UNC_CBO_XSNP_RESPONSE", .desc = "Snoop responses", .modmsk = INTEL_SNB_UNC_ATTRS, .cntmsk = 0xff, .code = 0x22, .numasks = LIBPFM_ARRAY_SIZE(snb_unc_cbo_xsnp_response), .ngrp = 2, .umasks = snb_unc_cbo_xsnp_response, }, { .name = "UNC_CBO_CACHE_LOOKUP", .desc = "LLC cache lookups", .modmsk = INTEL_SNB_UNC_ATTRS, .cntmsk = 0xff, .code = 0x34, .numasks = LIBPFM_ARRAY_SIZE(snb_unc_cbo_cache_lookup), .ngrp = 2, .umasks = snb_unc_cbo_cache_lookup, }, }; static const intel_x86_entry_t intel_snb_unc_cbo_pe[]={ { .name = "UNC_CBO_XSNP_RESPONSE", .desc = "Snoop responses (must provide a snoop type and filter)", .modmsk = INTEL_SNB_UNC_ATTRS, .cntmsk = 0xff, .code = 0x22, .numasks = LIBPFM_ARRAY_SIZE(snb_unc_cbo_xsnp_response), .ngrp = 2, .umasks = snb_unc_cbo_xsnp_response, }, { .name = "UNC_CBO_CACHE_LOOKUP", .desc = "LLC cache lookups", .modmsk = INTEL_SNB_UNC_ATTRS, .cntmsk = 0xff, .code = 0x34, .numasks = LIBPFM_ARRAY_SIZE(snb_unc_cbo_cache_lookup), .ngrp = 2, .umasks = snb_unc_cbo_cache_lookup, }, }; libpfm-4.9.0/lib/events/intel_bdx_unc_qpi_events.h0000664000175000017500000012205713223402656022122 0ustar eranianeranian/* * Copyright (c) 2017 Google Inc. All rights reserved * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * PMU: bdx_unc_qpi */ static intel_x86_umask_t bdx_unc_q_direct2core[]={ { .uname = "FAILURE_CREDITS", .ucode = 0x200, .udesc = "Direct 2 Core Spawning -- Spawn Failure - Egress Credits", }, { .uname = "FAILURE_CREDITS_MISS", .ucode = 0x2000, .udesc = "Direct 2 Core Spawning -- Spawn Failure - Egress and RBT Miss", }, { .uname = "FAILURE_CREDITS_RBT", .ucode = 0x800, .udesc = "Direct 2 Core Spawning -- Spawn Failure - Egress and RBT Invalid", }, { .uname = "FAILURE_CREDITS_RBT_MISS", .ucode = 0x8000, .udesc = "Direct 2 Core Spawning -- Spawn Failure - Egress and RBT Miss, Invalid", }, { .uname = "FAILURE_MISS", .ucode = 0x1000, .udesc = "Direct 2 Core Spawning -- Spawn Failure - RBT Miss", }, { .uname = "FAILURE_RBT_HIT", .ucode = 0x400, .udesc = "Direct 2 Core Spawning -- Spawn Failure - RBT Invalid", }, { .uname = "FAILURE_RBT_MISS", .ucode = 0x4000, .udesc = "Direct 2 Core Spawning -- Spawn Failure - RBT Miss and Invalid", }, { .uname = "SUCCESS_RBT_HIT", .ucode = 0x100, .udesc = "Direct 2 Core Spawning -- Spawn Success", }, }; static intel_x86_umask_t bdx_unc_q_rxl_credits_consumed_vn0[]={ { .uname = "DRS", .ucode = 0x100, .udesc = "VN0 Credit Consumed -- DRS", }, { .uname = "HOM", .ucode = 0x800, .udesc = "VN0 Credit Consumed -- HOM", }, { .uname = "NCB", .ucode = 0x200, .udesc = "VN0 Credit Consumed -- NCB", }, { .uname = "NCS", .ucode = 0x400, .udesc = "VN0 Credit Consumed -- NCS", }, { .uname = "NDR", .ucode = 0x2000, .udesc = "VN0 Credit Consumed -- NDR", }, { .uname = "SNP", .ucode = 0x1000, .udesc = "VN0 Credit Consumed -- SNP", }, }; static intel_x86_umask_t bdx_unc_q_rxl_flits_g1[]={ { .uname = "DRS", .ucode = 0x1800, .udesc = "Flits Received - Group 1 -- DRS Flits (both Header and Data)", .uflags = INTEL_X86_NCOMBO, }, { .uname = "DRS_DATA", .ucode = 0x800, .udesc = "Flits Received - Group 1 -- DRS Data Flits", .uflags = INTEL_X86_NCOMBO, }, { .uname = "DRS_NONDATA", .ucode = 0x1000, .udesc = "Flits Received - Group 1 -- DRS Header Flits", .uflags = INTEL_X86_NCOMBO, }, { .uname = "HOM", .ucode = 0x600, .udesc = "Flits Received - Group 1 -- HOM Flits", .uflags = INTEL_X86_NCOMBO, }, { .uname = "HOM_NONREQ", .ucode = 0x400, .udesc = "Flits Received - Group 1 -- HOM Non-Request Flits", .uflags = INTEL_X86_NCOMBO, }, { .uname = "HOM_REQ", .ucode = 0x200, .udesc = "Flits Received - Group 1 -- HOM Request Flits", .uflags = INTEL_X86_NCOMBO, }, { .uname = "SNP", .ucode = 0x100, .udesc = "Flits Received - Group 1 -- SNP Flits", .uflags = INTEL_X86_NCOMBO, }, }; static intel_x86_umask_t bdx_unc_q_rxl_flits_g2[]={ { .uname = "NCB", .ucode = 0xc00, .udesc = "Flits Received - Group 2 -- Non-Coherent Rx Flits", .uflags = INTEL_X86_NCOMBO, }, { .uname = "NCB_DATA", .ucode = 0x400, .udesc = "Flits Received - Group 2 -- Non-Coherent data Rx Flits", .uflags = INTEL_X86_NCOMBO, }, { .uname = "NCB_NONDATA", .ucode = 0x800, .udesc = "Flits Received - Group 2 -- Non-Coherent non-data Rx Flits", .uflags = INTEL_X86_NCOMBO, }, { .uname = "NCS", .ucode = 0x1000, .udesc = "Flits Received - Group 2 -- Non-Coherent standard Rx Flits", .uflags = INTEL_X86_NCOMBO, }, { .uname = "NDR_AD", .ucode = 0x100, .udesc = "Flits Received - Group 2 -- Non-Data Response Rx Flits - AD", .uflags = INTEL_X86_NCOMBO, }, { .uname = "NDR_AK", .ucode = 0x200, .udesc = "Flits Received - Group 2 -- Non-Data Response Rx Flits - AK", .uflags = INTEL_X86_NCOMBO, }, }; static intel_x86_umask_t bdx_unc_q_rxl_inserts_drs[]={ { .uname = "VN0", .ucode = 0x100, .udesc = "for VN0", }, { .uname = "VN1", .ucode = 0x200, .udesc = "for VN1", }, }; static const intel_x86_umask_t bdx_unc_q_rxl_flits_g0[]={ { .uname = "IDLE", .udesc = "Number of data flits over QPI that do not hold payload. When QPI is not in a power saving state, it continuously transmits flits across the link. When there are no protocol flits to send, it will send IDLE and NULL flits across", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "DATA", .udesc = "Number of data flits over QPI", .ucode = 0x200, .uflags = INTEL_X86_NCOMBO, }, { .uname = "NON_DATA", .udesc = "Number of non-NULL non-data flits over QPI", .ucode = 0x400, .uflags = INTEL_X86_NCOMBO, }, }; static intel_x86_umask_t bdx_unc_q_txl_flits_g0[]={ { .uname = "DATA", .ucode = 0x200, .udesc = "Flits Transferred - Group 0 -- Data Tx Flits", .uflags = INTEL_X86_NCOMBO, }, { .uname = "NON_DATA", .ucode = 0x400, .udesc = "Flits Transferred - Group 0 -- Non-Data protocol Tx Flits", .uflags = INTEL_X86_NCOMBO, }, }; static intel_x86_umask_t bdx_unc_q_txl_flits_g1[]={ { .uname = "DRS", .ucode = 0x1800, .udesc = "Flits Transferred - Group 1 -- DRS Flits (both Header and Data)", .uflags = INTEL_X86_NCOMBO, }, { .uname = "DRS_DATA", .ucode = 0x800, .udesc = "Flits Transferred - Group 1 -- DRS Data Flits", .uflags = INTEL_X86_NCOMBO, }, { .uname = "DRS_NONDATA", .ucode = 0x1000, .udesc = "Flits Transferred - Group 1 -- DRS Header Flits", .uflags = INTEL_X86_NCOMBO, }, { .uname = "HOM", .ucode = 0x600, .udesc = "Flits Transferred - Group 1 -- HOM Flits", .uflags = INTEL_X86_NCOMBO, }, { .uname = "HOM_NONREQ", .ucode = 0x400, .udesc = "Flits Transferred - Group 1 -- HOM Non-Request Flits", .uflags = INTEL_X86_NCOMBO, }, { .uname = "HOM_REQ", .ucode = 0x200, .udesc = "Flits Transferred - Group 1 -- HOM Request Flits", .uflags = INTEL_X86_NCOMBO, }, { .uname = "SNP", .ucode = 0x100, .udesc = "Flits Transferred - Group 1 -- SNP Flits", .uflags = INTEL_X86_NCOMBO, }, }; static intel_x86_umask_t bdx_unc_q_txl_flits_g2[]={ { .uname = "NCB", .ucode = 0xc00, .udesc = "Flits Transferred - Group 2 -- Non-Coherent Bypass Tx Flits", .uflags = INTEL_X86_NCOMBO, }, { .uname = "NCB_DATA", .ucode = 0x400, .udesc = "Flits Transferred - Group 2 -- Non-Coherent data Tx Flits", .uflags = INTEL_X86_NCOMBO, }, { .uname = "NCB_NONDATA", .ucode = 0x800, .udesc = "Flits Transferred - Group 2 -- Non-Coherent non-data Tx Flits", .uflags = INTEL_X86_NCOMBO, }, { .uname = "NCS", .ucode = 0x1000, .udesc = "Flits Transferred - Group 2 -- Non-Coherent standard Tx Flits", .uflags = INTEL_X86_NCOMBO, }, { .uname = "NDR_AD", .ucode = 0x100, .udesc = "Flits Transferred - Group 2 -- Non-Data Response Tx Flits - AD", .uflags = INTEL_X86_NCOMBO, }, { .uname = "NDR_AK", .ucode = 0x200, .udesc = "Flits Transferred - Group 2 -- Non-Data Response Tx Flits - AK", .uflags = INTEL_X86_NCOMBO, }, }; static intel_x86_umask_t bdx_unc_q_txr_bl_drs_credit_acquired[]={ { .uname = "VN0", .ucode = 0x100, .udesc = "R3QPI Egress Credit Occupancy - DRS -- for VN0", .uflags = INTEL_X86_NCOMBO, }, { .uname = "VN1", .ucode = 0x200, .udesc = "R3QPI Egress Credit Occupancy - DRS -- for VN1", .uflags = INTEL_X86_NCOMBO, }, { .uname = "VN_SHR", .ucode = 0x400, .udesc = "R3QPI Egress Credit Occupancy - DRS -- for Shared VN", .uflags = INTEL_X86_NCOMBO, }, }; static intel_x86_entry_t intel_bdx_unc_q_pe[]={ { .name = "UNC_Q_CLOCKTICKS", .code = 0x14, .desc = "Counts the number of clocks in the QPI LL. This clock runs at 1/4th the GT/s speed of the QPI link. For example, a 4GT/s link will have qfclk or 1GHz. BDX does not support dynamic link speeds, so this frequency is fixexed.", .modmsk = BDX_UNC_QPI_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_Q_CTO_COUNT", .code = 0x38 | (1 << 21), /* extra ev_sel_ext bit set */ .desc = "Counts the number of CTO (cluster trigger outs) events that were asserted across the two slots. If both slots trigger in a given cycle, the event will increment by 2. You can use edge detect to count the number of cases when both events triggered.", .modmsk = BDX_UNC_QPI_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_Q_DIRECT2CORE", .code = 0x13, .desc = "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exlusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.", .modmsk = BDX_UNC_QPI_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_q_direct2core, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_q_direct2core), }, { .name = "UNC_Q_L1_POWER_CYCLES", .code = 0x12, .desc = "Number of QPI qfclk cycles spent in L1 power mode. L1 is a mode that totally shuts down a QPI link. Use edge detect to count the number of instances when the QPI link entered L1. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. Because L1 totally shuts down the link, it takes a good amount of time to exit this mode.", .modmsk = BDX_UNC_QPI_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_Q_RXL0P_POWER_CYCLES", .code = 0x10, .desc = "Number of QPI qfclk cycles spent in L0p power mode. L0p is a mode where we disable 1/2 of the QPI lanes, decreasing our bandwidth in order to save power. It increases snoop and data transfer latencies and decreases overall bandwidth. This mode can be very useful in NUMA optimized workloads that largely only utilize QPI for snoops and their responses. Use edge detect to count the number of instances when the QPI link entered L0p. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.", .modmsk = BDX_UNC_QPI_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_Q_RXL0_POWER_CYCLES", .code = 0xf, .desc = "Number of QPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event.", .modmsk = BDX_UNC_QPI_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_Q_RXL_BYPASSED", .code = 0x9, .desc = "Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of flits transfered, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", .modmsk = BDX_UNC_QPI_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_Q_RXL_CREDITS_CONSUMED_VN0", .code = 0x1e | (1 << 21), /* extra ev_sel_ext bit set */ .desc = "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.", .modmsk = BDX_UNC_QPI_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_q_rxl_credits_consumed_vn0, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_q_rxl_credits_consumed_vn0), }, { .name = "UNC_Q_RXL_CREDITS_CONSUMED_VN1", .code = 0x39 | (1 << 21), /* extra ev_sel_ext bit set */ .desc = "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.", .modmsk = BDX_UNC_QPI_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_q_rxl_credits_consumed_vn0, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_q_rxl_credits_consumed_vn0), }, { .name = "UNC_Q_RXL_CREDITS_CONSUMED_VNA", .code = 0x1d | (1 << 21), /* extra ev_sel_ext bit set */ .desc = "Counts the number of times that an RxQ VNA credit was consumed (i.e. message uses a VNA credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.", .modmsk = BDX_UNC_QPI_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_Q_RXL_CYCLES_NE", .code = 0xa, .desc = "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.", .modmsk = BDX_UNC_QPI_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_Q_RXL_FLITS_G0", .code = 0x1, .desc = "Counts the number of flits received from the QPI Link.", .modmsk = BDX_UNC_QPI_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_q_rxl_flits_g0, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_q_rxl_flits_g0), }, { .name = "UNC_Q_RXL_FLITS_G1", .code = 0x2 | (1 << 21), /* extra ev_sel_ext bit set */ .desc = "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: datld therefore do: data flits * 8B / time.", .modmsk = BDX_UNC_QPI_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_q_rxl_flits_g1, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_q_rxl_flits_g1), }, { .name = "UNC_Q_RXL_FLITS_G2", .code = 0x3 | (1 << 21), /* extra ev_sel_ext bit set */ .desc = "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: datld therefore do: data flits * 8B / time.", .modmsk = BDX_UNC_QPI_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_q_rxl_flits_g2, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_q_rxl_flits_g2), }, { .name = "UNC_Q_RXL_INSERTS", .code = 0x8, .desc = "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.", .modmsk = BDX_UNC_QPI_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_Q_RXL_INSERTS_DRS", .code = 0x9 | (1 << 21), /* extra ev_sel_ext bit set */ .desc = "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only DRS flits.", .modmsk = BDX_UNC_QPI_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_q_rxl_inserts_drs, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_q_rxl_inserts_drs), }, { .name = "UNC_Q_RXL_INSERTS_HOM", .code = 0xc | (1 << 21), /* extra ev_sel_ext bit set */ .desc = "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only HOM flits.", .modmsk = BDX_UNC_QPI_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_q_rxl_inserts_drs, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_q_rxl_inserts_drs), }, { .name = "UNC_Q_RXL_INSERTS_NCB", .code = 0xa | (1 << 21), /* extra ev_sel_ext bit set */ .desc = "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCB flits.", .modmsk = BDX_UNC_QPI_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_q_rxl_inserts_drs, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_q_rxl_inserts_drs), }, { .name = "UNC_Q_RXL_INSERTS_NCS", .code = 0xb | (1 << 21), /* extra ev_sel_ext bit set */ .desc = "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCS flits.", .modmsk = BDX_UNC_QPI_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_q_rxl_inserts_drs, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_q_rxl_inserts_drs), }, { .name = "UNC_Q_RXL_INSERTS_NDR", .code = 0xe | (1 << 21), /* extra ev_sel_ext bit set */ .desc = "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NDR flits.", .modmsk = BDX_UNC_QPI_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_q_rxl_inserts_drs, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_q_rxl_inserts_drs), }, { .name = "UNC_Q_RXL_INSERTS_SNP", .code = 0xd | (1 << 21), /* extra ev_sel_ext bit set */ .desc = "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only SNP flits.", .modmsk = BDX_UNC_QPI_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_q_rxl_inserts_drs, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_q_rxl_inserts_drs), }, { .name = "UNC_Q_RXL_OCCUPANCY", .code = 0xb, .desc = "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.", .modmsk = BDX_UNC_QPI_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_Q_RXL_OCCUPANCY_DRS", .code = 0x15 | (1 << 21), /* extra ev_sel_ext bit set */ .desc = "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors DRS flits only.", .modmsk = BDX_UNC_QPI_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_q_rxl_inserts_drs, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_q_rxl_inserts_drs), }, { .name = "UNC_Q_RXL_OCCUPANCY_HOM", .code = 0x18 | (1 << 21), /* extra ev_sel_ext bit set */ .desc = "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors HOM flits only.", .modmsk = BDX_UNC_QPI_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_q_rxl_inserts_drs, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_q_rxl_inserts_drs), }, { .name = "UNC_Q_RXL_OCCUPANCY_NCB", .code = 0x16 | (1 << 21), /* extra ev_sel_ext bit set */ .desc = "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCB flits only.", .modmsk = BDX_UNC_QPI_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_q_rxl_inserts_drs, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_q_rxl_inserts_drs), }, { .name = "UNC_Q_RXL_OCCUPANCY_NCS", .code = 0x17 | (1 << 21), /* extra ev_sel_ext bit set */ .desc = "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCS flits only.", .modmsk = BDX_UNC_QPI_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_q_rxl_inserts_drs, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_q_rxl_inserts_drs), }, { .name = "UNC_Q_RXL_OCCUPANCY_NDR", .code = 0x1a | (1 << 21), /* extra ev_sel_ext bit set */ .desc = "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NDR flits only.", .modmsk = BDX_UNC_QPI_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_q_rxl_inserts_drs, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_q_rxl_inserts_drs), }, { .name = "UNC_Q_RXL_OCCUPANCY_SNP", .code = 0x19 | (1 << 21), /* extra ev_sel_ext bit set */ .desc = "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors SNP flits only.", .modmsk = BDX_UNC_QPI_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_q_rxl_inserts_drs, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_q_rxl_inserts_drs), }, { .name = "UNC_Q_TXL0P_POWER_CYCLES", .code = 0xd, .desc = "Number of QPI qfclk cycles spent in L0p power mode. L0p is a mode where we disable 1/2 of the QPI lanes, decreasing our bandwidth in order to save power. It increases snoop and data transfer latencies and decreases overall bandwidth. This mode can be very useful in NUMA optimized workloads that largely only utilize QPI for snoops and their responses. Use edge detect to count the number of instances when the QPI link entered L0p. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.", .modmsk = BDX_UNC_QPI_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_Q_TXL0_POWER_CYCLES", .code = 0xc, .desc = "Number of QPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event.", .modmsk = BDX_UNC_QPI_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_Q_TXL_BYPASSED", .code = 0x5, .desc = "Counts the number of times that an incoming flit was able to bypass the Tx flit buffer and pass directly out the QPI Link. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.", .modmsk = BDX_UNC_QPI_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_Q_TXL_CYCLES_NE", .code = 0x6, .desc = "Counts the number of cycles when the TxQ is not empty. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.", .modmsk = BDX_UNC_QPI_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_Q_TXL_FLITS_G0", .code = 0x0, .desc = "Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instfor L0) or 4B instead of 8B for L0p.", .modmsk = BDX_UNC_QPI_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_q_txl_flits_g0, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_q_txl_flits_g0), }, { .name = "UNC_Q_TXL_FLITS_G1", .code = 0x0 | (1 << 21), /* extra ev_sel_ext bit set */ .desc = "Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instfor L0) or 4B instead of 8B for L0p.", .modmsk = BDX_UNC_QPI_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_q_txl_flits_g1, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_q_txl_flits_g1), }, { .name = "UNC_Q_TXL_FLITS_G2", .code = 0x1 | (1 << 21), /* extra ev_sel_ext bit set */ .desc = "Counts the number of flits trasmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: datld therefore do: data flits * 8B / time.", .modmsk = BDX_UNC_QPI_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_q_txl_flits_g2, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_q_txl_flits_g2), }, { .name = "UNC_Q_TXL_INSERTS", .code = 0x4, .desc = "Number of allocations into the QPI Tx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.", .modmsk = BDX_UNC_QPI_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_Q_TXL_OCCUPANCY", .code = 0x7, .desc = "Accumulates the number of flits in the TxQ. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This can be used with the cycles not empty event to track average occupancy, or the allocations event to track average lifetime in the TxQ.", .modmsk = BDX_UNC_QPI_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_Q_TXR_AD_HOM_CREDIT_ACQUIRED", .code = 0x26 | (1 << 21), /* extra ev_sel_ext bit set */ .desc = "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Home messages on AD.", .modmsk = BDX_UNC_QPI_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_q_rxl_inserts_drs, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_q_rxl_inserts_drs), }, { .name = "UNC_Q_TXR_AD_HOM_CREDIT_OCCUPANCY", .code = 0x22 | (1 << 21), /* extra ev_sel_ext bit set */ .desc = "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for HOM messages on AD.", .modmsk = BDX_UNC_QPI_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_q_rxl_inserts_drs, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_q_rxl_inserts_drs), }, { .name = "UNC_Q_TXR_AD_NDR_CREDIT_ACQUIRED", .code = 0x28 | (1 << 21), /* extra ev_sel_ext bit set */ .desc = "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for NDR messages on AD.", .modmsk = BDX_UNC_QPI_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_q_rxl_inserts_drs, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_q_rxl_inserts_drs), }, { .name = "UNC_Q_TXR_AD_NDR_CREDIT_OCCUPANCY", .code = 0x24 | (1 << 21), /* extra ev_sel_ext bit set */ .desc = "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for NDR messages on AD.", .modmsk = BDX_UNC_QPI_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_q_rxl_inserts_drs, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_q_rxl_inserts_drs), }, { .name = "UNC_Q_TXR_AD_SNP_CREDIT_ACQUIRED", .code = 0x27 | (1 << 21), /* extra ev_sel_ext bit set */ .desc = "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Snoop messages on AD.", .modmsk = BDX_UNC_QPI_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_q_rxl_inserts_drs, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_q_rxl_inserts_drs), }, { .name = "UNC_Q_TXR_AD_SNP_CREDIT_OCCUPANCY", .code = 0x23 | (1 << 21), /* extra ev_sel_ext bit set */ .desc = "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO fro Snoop messages on AD.", .modmsk = BDX_UNC_QPI_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_q_rxl_inserts_drs, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_q_rxl_inserts_drs), }, { .name = "UNC_Q_TXR_AK_NDR_CREDIT_ACQUIRED", .code = 0x29 | (1 << 21), /* extra ev_sel_ext bit set */ .desc = "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. Local NDR message class to AK Egress.", .modmsk = BDX_UNC_QPI_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_Q_TXR_AK_NDR_CREDIT_OCCUPANCY", .code = 0x25 | (1 << 21), /* extra ev_sel_ext bit set */ .desc = "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. Local NDR message class to AK Egress.", .modmsk = BDX_UNC_QPI_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_Q_TXR_BL_DRS_CREDIT_ACQUIRED", .code = 0x2a | (1 << 21), /* extra ev_sel_ext bit set */ .desc = "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. DRS message class to BL Egress.", .modmsk = BDX_UNC_QPI_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_q_txr_bl_drs_credit_acquired, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_q_txr_bl_drs_credit_acquired), }, { .name = "UNC_Q_TXR_BL_DRS_CREDIT_OCCUPANCY", .code = 0x1f | (1 << 21), /* extra ev_sel_ext bit set */ .desc = "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. DRS message class to BL Egress.", .modmsk = BDX_UNC_QPI_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_q_txr_bl_drs_credit_acquired, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_q_txr_bl_drs_credit_acquired), }, { .name = "UNC_Q_TXR_BL_NCB_CREDIT_ACQUIRED", .code = 0x2b | (1 << 21), /* extra ev_sel_ext bit set */ .desc = "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCB message class to BL Egress.", .modmsk = BDX_UNC_QPI_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_q_rxl_inserts_drs, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_q_rxl_inserts_drs), }, { .name = "UNC_Q_TXR_BL_NCB_CREDIT_OCCUPANCY", .code = 0x20 | (1 << 21), /* extra ev_sel_ext bit set */ .desc = "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. NCB message class to BL Egress.", .modmsk = BDX_UNC_QPI_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_q_rxl_inserts_drs, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_q_rxl_inserts_drs), }, { .name = "UNC_Q_TXR_BL_NCS_CREDIT_ACQUIRED", .code = 0x2c | (1 << 21), /* extra ev_sel_ext bit set */ .desc = "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCS message class to BL Egress.", .modmsk = BDX_UNC_QPI_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_q_rxl_inserts_drs, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_q_rxl_inserts_drs), }, { .name = "UNC_Q_TXR_BL_NCS_CREDIT_OCCUPANCY", .code = 0x21 | (1 << 21), /* extra ev_sel_ext bit set */ .desc = "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. NCS message class to BL Egress.", .modmsk = BDX_UNC_QPI_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_q_rxl_inserts_drs, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_q_rxl_inserts_drs), }, { .name = "UNC_Q_VNA_CREDIT_RETURNS", .code = 0x1c | (1 << 21), /* extra ev_sel_ext bit set */ .desc = "Number of VNA credits returned.", .modmsk = BDX_UNC_QPI_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_Q_VNA_CREDIT_RETURN_OCCUPANCY", .code = 0x1b | (1 << 21), /* extra ev_sel_ext bit set */ .desc = "Number of VNA credits in the Rx side that are waitng to be returned back across the link.", .modmsk = BDX_UNC_QPI_ATTRS, .cntmsk = 0xf, }, }; libpfm-4.9.0/lib/events/sparc_ultra4plus_events.h0000664000175000017500000004364013223402656021743 0ustar eranianeranianstatic const sparc_entry_t ultra4plus_pe[] = { /* These two must always be first. */ { .name = "Cycle_cnt", .desc = "Accumulated cycles", .ctrl = PME_CTRL_S0 | PME_CTRL_S1, .code = 0x0, }, { .name = "Instr_cnt", .desc = "Number of instructions completed", .ctrl = PME_CTRL_S0 | PME_CTRL_S1, .code = 0x1, }, /* PIC0 UltraSPARC-IV+ events */ { .name = "Dispatch0_IC_miss", .desc = "I-buffer is empty from I-Cache miss", .ctrl = PME_CTRL_S0, .code = 0x2, }, { .name = "IU_stat_jmp_correct_pred", .desc = "Retired non-annulled register indirect jumps predicted correctly", .ctrl = PME_CTRL_S0, .code = 0x3, }, { .name = "Dispatch0_2nd_br", .desc = "Stall cycles due to having two branch instructions line-up in one 4-instruction group causing the second branch in the group to be re-fetched, delaying it's entrance into the I-buffer", .ctrl = PME_CTRL_S0, .code = 0x4, }, { .name = "Rstall_storeQ", .desc = "R-stage stall for a store instruction which is the next instruction to be executed, but it stalled due to the store queue being full", .ctrl = PME_CTRL_S0, .code = 0x5, }, { .name = "Rstall_IU_use", .desc = "R-stage stall for an event that the next instruction to be executed depends on the result of a preceding integer instruction in the pipeline that is not yet available", .ctrl = PME_CTRL_S0, .code = 0x6, }, { .name = "IU_stat_ret_correct_pred", .desc = "Retired non-annulled returns predicted correctly", .ctrl = PME_CTRL_S0, .code = 0x7, }, { .name = "IC_ref", .desc = "I-cache references", .ctrl = PME_CTRL_S0, .code = 0x8, }, { .name = "DC_rd", .desc = "D-cache read references (including accesses that subsequently trap)", .ctrl = PME_CTRL_S0, .code = 0x9, }, { .name = "Rstall_FP_use", .desc = "R-stage stall for an event that the next instruction to be executed depends on the result of a preceding floating-point instruction in the pipeline that is not yet available", .ctrl = PME_CTRL_S0, .code = 0xa, }, { .name = "SW_pf_instr", .desc = "Retired SW prefetch instructions", .ctrl = PME_CTRL_S0, .code = 0xb, }, { .name = "L2_ref", .desc = "L2-cache references", .ctrl = PME_CTRL_S0, .code = 0xc, }, { .name = "L2_write_hit_RTO", .desc = "L2-cache exclusive requests that hit L2-cache in S, O, or Os state and thus, do a read-to-own bus transaction", .ctrl = PME_CTRL_S0, .code = 0xd, }, { .name = "L2_snoop_inv_sh", .desc = "L2 cache lines that were written back to the L3 cache due to requests from both cores", .ctrl = PME_CTRL_S0, .code = 0xe, }, { .name = "L2_rd_miss", .desc = "L2-cache miss events (including atomics) from D-cache events", .ctrl = PME_CTRL_S0, .code = 0xf, }, { .name = "PC_rd", .desc = "P-cache cacheable loads", .ctrl = PME_CTRL_S0, .code = 0x10, }, { .name = "SI_snoop_sh", .desc = "Counts snoops from remote processor(s) including RTS, RTSR, RTO, RTOR, RS, RSR, RTSM, and WS", .ctrl = PME_CTRL_S0, .code = 0x11, }, { .name = "SI_ciq_flow_sh", .desc = "Counts system clock cycles when the flow control (PauseOut) signal is asserted", .ctrl = PME_CTRL_S0, .code = 0x12, }, { .name = "Re_DC_miss", .desc = "Stall due to loads that miss D-cache and get recirculated", .ctrl = PME_CTRL_S0, .code = 0x13, }, { .name = "SW_count_NOP0", .desc = "Retired, non-annulled special software NOP instructions (which is equivalent to 'sethi %hi(0xfc000), %g0' instruction)", .ctrl = PME_CTRL_S0, .code = 0x14, }, { .name = "IU_Stat_Br_miss_taken", .desc = "Retired branches that were predicted to be taken, but in fact were not taken", .ctrl = PME_CTRL_S0, .code = 0x15, }, { .name = "IU_Stat_Br_Count_taken", .desc = "Retired taken branches", .ctrl = PME_CTRL_S0, .code = 0x16, }, { .name = "HW_pf_exec", .desc = "Hardware prefetches enqueued in the prefetch queue", .ctrl = PME_CTRL_S0, .code = 0x17, }, { .name = "FA_pipe_completion", .desc = "Instructions that complete execution on the FPG ALU pipelines", .ctrl = PME_CTRL_S0, .code = 0x18, }, { .name = "SSM_L3_wb_remote", .desc = "L3 cache line victimizations from this core which generate R_WB transactions to non-LPA (remote physical address) regions", .ctrl = PME_CTRL_S0, .code = 0x19, }, { .name = "SSM_L3_miss_local", .desc = "L3 cache misses to LPA (local physical address) from this core which generate an RTS, RTO, or RS transaction", .ctrl = PME_CTRL_S0, .code = 0x1a, }, { .name = "SSM_L3_miss_mtag_remote", .desc = "L3 cache misses to LPA (local physical address) from this core which generate retry (R_*) transactions including R_RTS, R_RTO, and R_RS", .ctrl = PME_CTRL_S0, .code = 0x1b, }, { .name = "SW_pf_str_trapped", .desc = "Strong software prefetch instructions trapping due to TLB miss", .ctrl = PME_CTRL_S0, .code = 0x1c, }, { .name = "SW_pf_PC_installed", .desc = "Software prefetch instructions that installed lines in the P-cache", .ctrl = PME_CTRL_S0, .code = 0x1d, }, { .name = "IPB_to_IC_fill", .desc = "I-cache fills from the instruction prefetch buffer", .ctrl = PME_CTRL_S0, .code = 0x1e, }, { .name = "L2_write_miss", .desc = "L2-cache misses from this core by cacheable store requests", .ctrl = PME_CTRL_S0, .code = 0x1f, }, { .name = "MC_reads_0_sh", .desc = "Read requests completed to memory bank 0", .ctrl = PME_CTRL_S0, .code = 0x20, }, { .name = "MC_reads_1_sh", .desc = "Read requests completed to memory bank 1", .ctrl = PME_CTRL_S0, .code = 0x21, }, { .name = "MC_reads_2_sh", .desc = "Read requests completed to memory bank 2", .ctrl = PME_CTRL_S0, .code = 0x22, }, { .name = "MC_reads_3_sh", .desc = "Read requests completed to memory bank 3", .ctrl = PME_CTRL_S0, .code = 0x23, }, { .name = "MC_stalls_0_sh", .desc = "Clock cycles that requests were stalled in the MCU queues because bank 0 was busy with a previous request", .ctrl = PME_CTRL_S0, .code = 0x24, }, { .name = "MC_stalls_2_sh", .desc = "Clock cycles that requests were stalled in the MCU queues because bank 2 was busy with a previous request", .ctrl = PME_CTRL_S0, .code = 0x25, }, { .name = "L2_hit_other_half", .desc = "L2 cache hits from this core to the ways filled by the other core when the cache is in the pseudo-split mode", .ctrl = PME_CTRL_S0, .code = 0x26, }, { .name = "L3_rd_miss", .desc = "L3 cache misses sent out to SIU from this code by cacheable I-cache, D-cache, PO-cache, and W-cache (excluding block store) requests", .ctrl = PME_CTRL_S0, .code = 0x28, }, { .name = "Re_L2_miss", .desc = "Stall cycles due to recirculation of cacheable loads that miss both D-cache and L2 cache", .ctrl = PME_CTRL_S0, .code = 0x29, }, { .name = "IC_miss_cancelled", .desc = "I-cache miss requests cancelled due to new fetch stream", .ctrl = PME_CTRL_S0, .code = 0x2a, }, { .name = "DC_wr_miss", .desc = "D-cache store accesses that miss D-cache", .ctrl = PME_CTRL_S0, .code = 0x2b, }, { .name = "L3_hit_I_state_sh", .desc = "Tag hits in L3 cache when the line is in I state", .ctrl = PME_CTRL_S0, .code = 0x2c, }, { .name = "SI_RTS_src_data", .desc = "Local RTS transactions due to I-cache, D-cache, or P-cache requests from this core where data is from the cache of another processor on the system, not from memory", .ctrl = PME_CTRL_S0, .code = 0x2d, }, { .name = "L2_IC_miss", .desc = "L2 cache misses from this code by cacheable I-cache requests", .ctrl = PME_CTRL_S0, .code = 0x2e, }, { .name = "SSM_new_transaction_sh", .desc = "New SSM transactions (RTSU, RTOU, UGM) observed by this processor on the Fireplane Interconnect", .ctrl = PME_CTRL_S0, .code = 0x2f, }, { .name = "L2_SW_pf_miss", .desc = "L2 cache misses by software prefetch requests from this core", .ctrl = PME_CTRL_S0, .code = 0x30, }, { .name = "L2_wb", .desc = "L2 cache lines that were written back to the L3 cache because of requests from this core", .ctrl = PME_CTRL_S0, .code = 0x31, }, { .name = "L2_wb_sh", .desc = "L2 cache lines that were written back to the L3 cache because of requests from both cores", .ctrl = PME_CTRL_S0, .code = 0x32, }, { .name = "L2_snoop_cb_sh", .desc = "L2 cache lines that were copied back due to other processors", .ctrl = PME_CTRL_S0, .code = 0x33, }, /* PIC1 UltraSPARC-IV+ events */ { .name = "Dispatch0_other", .desc = "Stall cycles due to the event that no instructions are dispatched because the I-queue is empty due to various other events, including branch target address fetch and various events which cause an instruction to be refetched", .ctrl = PME_CTRL_S1, .code = 0x2, }, { .name = "DC_wr", .desc = "D-cache write references by cacheable stores (excluding block stores)", .ctrl = PME_CTRL_S1, .code = 0x3, }, { .name = "Re_DC_missovhd", .desc = "Stall cycles due to D-cache load miss", .ctrl = PME_CTRL_S1, .code = 0x4, }, { .name = "Re_FPU_bypass", .desc = "Stall due to recirculation when an FPU bypass condition that does not have a direct bypass path occurs", .ctrl = PME_CTRL_S1, .code = 0x5, }, { .name = "L3_write_hit_RTO", .desc = "L3 cache hits in O, Os, or S state by cacheable store requests from this core that do a read-to-own (RTO) bus transaction", .ctrl = PME_CTRL_S1, .code = 0x6, }, { .name = "L2L3_snoop_inv_sh", .desc = "L2 and L3 cache lines that were invalidated due to other processors doing RTO, RTOR, RTOU, or WS transactions", .ctrl = PME_CTRL_S1, .code = 0x7, }, { .name = "IC_L2_req", .desc = "I-cache requests sent to L2 cache", .ctrl = PME_CTRL_S1, .code = 0x8, }, { .name = "DC_rd_miss", .desc = "Cacheable loads (excluding atomics and block loads) that miss D-cache as well as P-cache (for FP loads)", .ctrl = PME_CTRL_S1, .code = 0x9, }, { .name = "L2_hit_I_state_sh", .desc = "Tag hits in L2 cache when the line is in I state", .ctrl = PME_CTRL_S1, .code = 0xa, }, { .name = "L3_write_miss_RTO", .desc = "L3 cache misses from this core by cacheable store requests that do a read-to-own (RTO) bus transaction. This count does not include RTO requests for prefetch (fcn=2,3/22,23) instructions", .ctrl = PME_CTRL_S1, .code = 0xb, }, { .name = "L2_miss", .desc = "L2 cache misses from this core by cacheable I-cache, D-cache, P-cache, and W-cache (excluding block stores) requests", .ctrl = PME_CTRL_S1, .code = 0xc, }, { .name = "SI_owned_sh", .desc = "Number of times owned_in is asserted on bus requests from the local processor", .ctrl = PME_CTRL_S1, .code = 0xd, }, { .name = "SI_RTO_src_data", .desc = "Number of local RTO transactions due to W-cache or P-cache requests from this core where data is from the cache of another processor on the system, not from memory", .ctrl = PME_CTRL_S1, .code = 0xe, }, { .name = "SW_pf_duplicate", .desc = "Number of software prefetch instructions that were dropped because the prefetch request matched an outstanding requests in the prefetch queue or the request hit the P-cache", .ctrl = PME_CTRL_S1, .code = 0xf, }, { .name = "IU_stat_jmp_mispred", .desc = "Number of retired non-annulled register indirect jumps mispredicted", .ctrl = PME_CTRL_S1, .code = 0x10, }, { .name = "ITLB_miss", .desc = "I-TLB misses", .ctrl = PME_CTRL_S1, .code = 0x11, }, { .name = "DTLB_miss", .desc = "D-TLB misses", .ctrl = PME_CTRL_S1, .code = 0x12, }, { .name = "WC_miss", .desc = "W-cache misses", .ctrl = PME_CTRL_S1, .code = 0x13, }, { .name = "IC_fill", .desc = "Number of I-cache fills excluding fills from the instruction prefetch buffer. This is the best approximation of the number of I-cache misses for instructions that were actually executed", .ctrl = PME_CTRL_S1, .code = 0x14, }, { .name = "IU_stat_ret_mispred", .desc = "Number of retired non-annulled returns mispredicted", .ctrl = PME_CTRL_S1, .code = 0x15, }, { .name = "Re_L3_miss", .desc = "Stall cycles due to recirculation of cacheable loads that miss D-cache, L2, and L3 cache", .ctrl = PME_CTRL_S1, .code = 0x16, }, { .name = "Re_PFQ_full", .desc = "Stall cycles due to recirculation of prefetch instructions because the prefetch queue (PFQ) was full", .ctrl = PME_CTRL_S1, .code = 0x17, }, { .name = "PC_soft_hit", .desc = "Number of cacheable FP loads that hit a P-cache line that was prefetched by a software prefetch instruction", .ctrl = PME_CTRL_S1, .code = 0x18, }, { .name = "PC_inv", .desc = "Number of P-cache lines that were invalidated due to external snoops, internal stores, and L2 evictions", .ctrl = PME_CTRL_S1, .code = 0x19, }, { .name = "PC_hard_hit", .desc = "Number of FP loads that hit a P-cache line that was fetched by a FP load or a hardware prefetch, irrespective of whether the loads hit or miss the D-cache", .ctrl = PME_CTRL_S1, .code = 0x1a, }, { .name = "IC_pf", .desc = "Number of I-cache prefetch requests sent to L2 cache", .ctrl = PME_CTRL_S1, .code = 0x1b, }, { .name = "SW_count_NOP1", .desc = "Retired, non-annulled special software NOP instructions (which is equivalent to 'sethi %hi(0xfc000), %g0' instruction)", .ctrl = PME_CTRL_S1, .code = 0x1c, }, { .name = "IU_stat_br_miss_untaken", .desc = "Number of retired non-annulled conditional branches that were predicted to be not taken, but in fact were taken", .ctrl = PME_CTRL_S1, .code = 0x1d, }, { .name = "IU_stat_br_count_taken", .desc = "Number of retired non-annulled conditional branches that were taken", .ctrl = PME_CTRL_S1, .code = 0x1e, }, { .name = "PC_miss", .desc = "Number of cacheable FP loads that miss P-cache, irrespective of whether the loads hit or miss the D-cache", .ctrl = PME_CTRL_S1, .code = 0x1f, }, { .name = "MC_writes_0_sh", .desc = "Number of write requests complete to memory bank 0", .ctrl = PME_CTRL_S1, .code = 0x20, }, { .name = "MC_writes_1_sh", .desc = "Number of write requests complete to memory bank 1", .ctrl = PME_CTRL_S1, .code = 0x21, }, { .name = "MC_writes_2_sh", .desc = "Number of write requests complete to memory bank 2", .ctrl = PME_CTRL_S1, .code = 0x22, }, { .name = "MC_writes_3_sh", .desc = "Number of write requests complete to memory bank 3", .ctrl = PME_CTRL_S1, .code = 0x23, }, { .name = "MC_stalls_1_sh", .desc = "Number of processor cycles that requests were stalled in the MCU queues because bank 0 was busy with a previous requests", .ctrl = PME_CTRL_S1, .code = 0x24, }, { .name = "MC_stalls_3_sh", .desc = "Number of processor cycles that requests were stalled in the MCU queues because bank 3 was busy with a previous requests", .ctrl = PME_CTRL_S1, .code = 0x25, }, { .name = "Re_RAW_miss", .desc = "Stall cycles due to recirculation when there is a load instruction in the E-stage of the pipeline which has a non-bypassable read-after-write (RAW) hazard with an earlier store instruction", .ctrl = PME_CTRL_S1, .code = 0x26, }, { .name = "FM_pipe_completion", .desc = "Number of retired instructions that complete execution on the FLoat-Point/Graphics Multiply pipeline", .ctrl = PME_CTRL_S1, .code = 0x27, }, { .name = "SSM_L3_miss_mtag_remote", .desc = "Number of L3 cache misses to LPA (local physical address) from this core which generate retry (R_*) transactions including R_RTS, R_RTO, and R_RS", .ctrl = PME_CTRL_S1, .code = 0x28, }, { .name = "SSM_L3_miss_remote", .desc = "Number of L3 cache misses from this core which generate retry (R_*) transactions to non-LPA (non-local physical address) address space, or R_WS transactions due to block store (BST) / block store commit (BSTC) to any address space (LPA or non-LPA), or R_RTO due to atomic request on Os state to LPA space.", .ctrl = PME_CTRL_S1, .code = 0x29, }, { .name = "SW_pf_exec", .desc = "Number of retired, non-trapping software prefetch instructions that completed, i.e. number of retired prefetch instructions that were not dropped due to the prefecth queue being full", .ctrl = PME_CTRL_S1, .code = 0x2a, }, { .name = "SW_pf_str_exec", .desc = "Number of retired, non-trapping strong prefetch instructions that completed", .ctrl = PME_CTRL_S1, .code = 0x2b, }, { .name = "SW_pf_dropped", .desc = "Number of software prefetch instructions dropped due to TLB miss or due to the prefetch queue being full", .ctrl = PME_CTRL_S1, .code = 0x2c, }, { .name = "SW_pf_L2_installed", .desc = "Number of software prefetch instructions that installed lines in the L2 cache", .ctrl = PME_CTRL_S1, .code = 0x2d, }, { .name = "L2_HW_pf_miss", .desc = "Number of L2 cache misses by hardware prefetch requests from this core", .ctrl = PME_CTRL_S1, .code = 0x2f, }, { .name = "L3_miss", .desc = "Number of L3 cache misses sent out to SIU from this core by cacheable I-cache, D-cache, P-cache, and W-cache (excluding block stores) requests", .ctrl = PME_CTRL_S1, .code = 0x31, }, { .name = "L3_IC_miss", .desc = "Number of L3 cache misses by cacheable I-cache requests from this core", .ctrl = PME_CTRL_S1, .code = 0x32, }, { .name = "L3_SW_pf_miss", .desc = "Number of L3 cache misses by software prefetch requests from this core", .ctrl = PME_CTRL_S1, .code = 0x33, }, { .name = "L3_hit_other_half", .desc = "Number of L3 cache hits from this core to the ways filled by the other core when the cache is in pseudo-split mode", .ctrl = PME_CTRL_S1, .code = 0x34, }, { .name = "L3_wb", .desc = "Number of L3 cache lines that were written back because of requests from this core", .ctrl = PME_CTRL_S1, .code = 0x35, }, { .name = "L3_wb_sh", .desc = "Number of L3 cache lines that were written back because of requests from both cores", .ctrl = PME_CTRL_S1, .code = 0x36, }, { .name = "L2L3_snoop_cb_sh", .desc = "Total number of L2 and L3 cache lines that were copied back due to other processors", .ctrl = PME_CTRL_S1, .code = 0x37, }, }; #define PME_SPARC_ULTRA4PLUS_EVENT_COUNT (sizeof(ultra4plus_pe)/sizeof(sparc_entry_t)) libpfm-4.9.0/lib/events/intel_ivbep_unc_r3qpi_events.h0000664000175000017500000003444013223402656022715 0ustar eranianeranian/* * Copyright (c) 2014 Google Inc. All rights reserved * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * This file has been automatically generated. * * PMU: ivbep_unc_r3qpi (Intel IvyBridge-EP R3QPI uncore) */ static const intel_x86_umask_t ivbep_unc_r3_ring_ad_used[]={ { .uname = "CCW_VR0_EVEN", .udesc = "Counter-Clockwise and even ring polarity on virtual ring 0", .ucode = 0x400, }, { .uname = "CCW_VR0_ODD", .udesc = "Counter-Clockwise and odd ring polarity on virtual ring 0", .ucode = 0x800, }, { .uname = "CW_VR0_EVEN", .udesc = "Clockwise and even ring polarity on virtual ring 0", .ucode = 0x100, }, { .uname = "CW_VR0_ODD", .udesc = "Clockwise and odd ring polarity on virtual ring 0", .ucode = 0x200, }, { .uname = "CW", .udesc = "Clockwise with any polarity on either virtual rings", .ucode = 0x3300, }, { .uname = "CCW", .udesc = "Counter-clockwise with any polarity on either virtual rings", .ucode = 0xcc00, }, }; static const intel_x86_umask_t ivbep_unc_r3_ring_iv_used[]={ { .uname = "CW", .udesc = "Clockwise with any polarity on either virtual rings", .ucode = 0x3300, }, { .uname = "CCW", .udesc = "Counter-clockwise with any polarity on either virtual rings", .ucode = 0xcc00, }, { .uname = "ANY", .udesc = "Counter-clockwise with any polarity on either virtual rings", .ucode = 0xff00, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t ivbep_unc_r3_rxr_cycles_ne[]={ { .uname = "HOM", .udesc = "HOM Ingress queue", .ucode = 0x100, }, { .uname = "SNP", .udesc = "SNP Ingress queue", .ucode = 0x200, }, { .uname = "NDR", .udesc = "NDR Ingress queue", .ucode = 0x400, }, }; static const intel_x86_umask_t ivbep_unc_r3_rxr_inserts[]={ { .uname = "DRS", .udesc = "DRS Ingress queue", .ucode = 0x800, }, { .uname = "HOM", .udesc = "HOM Ingress queue", .ucode = 0x100, }, { .uname = "NCB", .udesc = "NCB Ingress queue", .ucode = 0x1000, }, { .uname = "NCS", .udesc = "NCS Ingress queue", .ucode = 0x2000, }, { .uname = "NDR", .udesc = "NDR Ingress queue", .ucode = 0x400, }, { .uname = "SNP", .udesc = "SNP Ingress queue", .ucode = 0x200, }, }; static const intel_x86_umask_t ivbep_unc_r3_vn0_credits_used[]={ { .uname = "HOM", .udesc = "Filter HOM message class", .ucode = 0x100, }, { .uname = "SNP", .udesc = "Filter SNP message class", .ucode = 0x200, }, { .uname = "NDR", .udesc = "Filter NDR message class", .ucode = 0x400, }, { .uname = "DRS", .udesc = "Filter DRS message class", .ucode = 0x800, }, { .uname = "NCB", .udesc = "Filter NCB message class", .ucode = 0x1000, }, { .uname = "NCS", .udesc = "Filter NCS message class", .ucode = 0x2000, }, }; static const intel_x86_umask_t ivbep_unc_r3_c_hi_ad_credits_empty[]={ { .uname = "CBO8", .udesc = "CBox 8", .ucode = 0x100, }, { .uname = "CBO9", .udesc = "CBox 9", .ucode = 0x200, }, { .uname = "CBO10", .udesc = "CBox 10", .ucode = 0x400, }, { .uname = "CBO11", .udesc = "CBox 11", .ucode = 0x800, }, { .uname = "CBO12", .udesc = "CBox 12", .ucode = 0x1000, }, { .uname = "CBO13", .udesc = "CBox 13", .ucode = 0x2000, }, { .uname = "CBO14", .udesc = "CBox 14 & 16", .ucode = 0x4000, }, }; static const intel_x86_umask_t ivbep_unc_r3_c_lo_ad_credits_empty[]={ { .uname = "CBO0", .udesc = "CBox 0", .ucode = 0x100, }, { .uname = "CBO1", .udesc = "CBox 1", .ucode = 0x200, }, { .uname = "CBO2", .udesc = "CBox 2", .ucode = 0x400, }, { .uname = "CBO3", .udesc = "CBox 3", .ucode = 0x800, }, { .uname = "CBO4", .udesc = "CBox 4", .ucode = 0x1000, }, { .uname = "CBO5", .udesc = "CBox 5", .ucode = 0x2000, }, { .uname = "CBO6", .udesc = "CBox 6", .ucode = 0x4000, }, { .uname = "CBO7", .udesc = "CBox 7", .ucode = 0x8000, } }; static const intel_x86_umask_t ivbep_unc_r3_ha_r2_bl_credits_empty[]={ { .uname = "HA0", .udesc = "HA0", .ucode = 0x100, }, { .uname = "HA1", .udesc = "HA1", .ucode = 0x200, }, { .uname = "R2_NCB", .udesc = "R2 NCB messages", .ucode = 0x400, }, { .uname = "R2_NCS", .udesc = "R2 NCS messages", .ucode = 0x800, } }; static const intel_x86_umask_t ivbep_unc_r3_qpi0_ad_credits_empty[]={ { .uname = "VNA", .udesc = "VNA", .ucode = 0x100, }, { .uname = "VN0_HOM", .udesc = "VN0 HOM messages", .ucode = 0x200, }, { .uname = "VN0_SNP", .udesc = "VN0 SNP messages", .ucode = 0x400, }, { .uname = "VN0_NDR", .udesc = "VN0 NDR messages", .ucode = 0x800, }, { .uname = "VN1_HOM", .udesc = "VN1 HOM messages", .ucode = 0x1000, }, { .uname = "VN1_SNP", .udesc = "VN1 SNP messages", .ucode = 0x2000, }, { .uname = "VN1_NDR", .udesc = "VN1 NDR messages", .ucode = 0x4000, }, }; static const intel_x86_umask_t ivbep_unc_r3_txr_nack_ccw[]={ { .uname = "AD", .udesc = "BL counter-clockwise Egress queue", .ucode = 0x100, }, { .uname = "AK", .udesc = "AD clockwise Egress queue", .ucode = 0x200, }, { .uname = "BL", .udesc = "AD counter-clockwise Egress queue", .ucode = 0x400, }, }; static const intel_x86_umask_t ivbep_unc_r3_txr_nack_cw[]={ { .uname = "AD", .udesc = "AD clockwise Egress queue", .ucode = 0x100, }, { .uname = "AK", .udesc = "AD counter-clockwise Egress queue", .ucode = 0x200, }, { .uname = "BL", .udesc = "BL clockwise Egress queue", .ucode = 0x400, }, }; static const intel_x86_umask_t ivbep_unc_r3_vna_credits_acquired[]={ { .uname = "AD", .udesc = "For AD ring", .ucode = 0x100, }, { .uname = "BL", .udesc = "For BL ring", .ucode = 0x400, }, }; static const intel_x86_entry_t intel_ivbep_unc_r3_pe[]={ { .name = "UNC_R3_CLOCKTICKS", .desc = "Number of uclks in domain", .code = 0x1, .cntmsk = 0x7, .modmsk = IVBEP_UNC_R3QPI_ATTRS, }, { .name = "UNC_R3_RING_AD_USED", .desc = "R3 AD Ring in Use", .code = 0x7, .cntmsk = 0x7, .ngrp = 1, .modmsk = IVBEP_UNC_R3QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r3_ring_ad_used), .umasks = ivbep_unc_r3_ring_ad_used }, { .name = "UNC_R3_RING_AK_USED", .desc = "R3 AK Ring in Use", .code = 0x8, .cntmsk = 0x7, .ngrp = 1, .modmsk = IVBEP_UNC_R3QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r3_ring_ad_used), .umasks = ivbep_unc_r3_ring_ad_used /* shared */ }, { .name = "UNC_R3_RING_BL_USED", .desc = "R3 BL Ring in Use", .code = 0x9, .cntmsk = 0x7, .ngrp = 1, .modmsk = IVBEP_UNC_R3QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r3_ring_ad_used), .umasks = ivbep_unc_r3_ring_ad_used /* shared */ }, { .name = "UNC_R3_RING_IV_USED", .desc = "R3 IV Ring in Use", .code = 0xa, .cntmsk = 0x7, .ngrp = 1, .modmsk = IVBEP_UNC_R3QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r3_ring_iv_used), .umasks = ivbep_unc_r3_ring_iv_used }, { .name = "UNC_R3_RXR_AD_BYPASSED", .desc = "Ingress Bypassed", .code = 0x12, .cntmsk = 0x3, .modmsk = IVBEP_UNC_R3QPI_ATTRS, }, { .name = "UNC_R3_RXR_CYCLES_NE", .desc = "Ingress Cycles Not Empty", .code = 0x10, .cntmsk = 0x3, .ngrp = 1, .modmsk = IVBEP_UNC_R3QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r3_rxr_cycles_ne), .umasks = ivbep_unc_r3_rxr_cycles_ne }, { .name = "UNC_R3_RXR_INSERTS", .desc = "Ingress Allocations", .code = 0x11, .cntmsk = 0x3, .ngrp = 1, .modmsk = IVBEP_UNC_R3QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r3_rxr_inserts), .umasks = ivbep_unc_r3_rxr_inserts }, { .name = "UNC_R3_RXR_OCCUPANCY", .desc = "Ingress Occupancy Accumulator", .code = 0x13, .cntmsk = 0x1, .ngrp = 1, .modmsk = IVBEP_UNC_R3QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r3_rxr_inserts), .umasks = ivbep_unc_r3_rxr_inserts/* shared */ }, { .name = "UNC_R3_TXR_CYCLES_FULL", .desc = "Egress cycles full", .code = 0x25, .cntmsk = 0x3, .modmsk = IVBEP_UNC_R3QPI_ATTRS, }, { .name = "UNC_R3_VN0_CREDITS_REJECT", .desc = "VN0 Credit Acquisition Failed", .code = 0x37, .cntmsk = 0x3, .ngrp = 1, .modmsk = IVBEP_UNC_R3QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r3_vn0_credits_used), .umasks = ivbep_unc_r3_vn0_credits_used }, { .name = "UNC_R3_VN0_CREDITS_USED", .desc = "VN0 Credit Used", .code = 0x36, .cntmsk = 0x3, .ngrp = 1, .modmsk = IVBEP_UNC_R3QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r3_vn0_credits_used), .umasks = ivbep_unc_r3_vn0_credits_used }, { .name = "UNC_R3_VNA_CREDITS_ACQUIRED", .desc = "VNA credit Acquisitions", .code = 0x33, .cntmsk = 0x3, .ngrp = 1, .modmsk = IVBEP_UNC_R3QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r3_vna_credits_acquired), .umasks = ivbep_unc_r3_vna_credits_acquired }, { .name = "UNC_R3_VNA_CREDITS_REJECT", .desc = "VNA Credit Reject", .code = 0x34, .cntmsk = 0x3, .ngrp = 1, .modmsk = IVBEP_UNC_R3QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r3_vn0_credits_used), .umasks = ivbep_unc_r3_vn0_credits_used /* shared */ }, { .name = "UNC_R3_VNA_CREDIT_CYCLES_OUT", .desc = "Cycles with no VNA credits available", .code = 0x31, .cntmsk = 0x3, .modmsk = IVBEP_UNC_R3QPI_ATTRS, }, { .name = "UNC_R3_VNA_CREDIT_CYCLES_USED", .desc = "Cycles with 1 or more VNA credits in use", .code = 0x32, .cntmsk = 0x3, .modmsk = IVBEP_UNC_R3QPI_ATTRS, }, { .name = "UNC_R3_C_HI_AD_CREDITS_EMPTY", .desc = "Cbox AD credits empty", .code = 0x2c, .cntmsk = 0x3, .ngrp = 1, .modmsk = IVBEP_UNC_R3QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r3_c_hi_ad_credits_empty), .umasks = ivbep_unc_r3_c_hi_ad_credits_empty }, { .name = "UNC_R3_C_LO_AD_CREDITS_EMPTY", .desc = "Cbox AD credits empty", .code = 0x2b, .cntmsk = 0x3, .ngrp = 1, .modmsk = IVBEP_UNC_R3QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r3_c_lo_ad_credits_empty), .umasks = ivbep_unc_r3_c_lo_ad_credits_empty }, { .name = "UNC_R3_HA_R2_BL_CREDITS_EMPTY", .desc = "HA/R2 AD credits empty", .code = 0x2f, .cntmsk = 0x3, .ngrp = 1, .modmsk = IVBEP_UNC_R3QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r3_ha_r2_bl_credits_empty), .umasks = ivbep_unc_r3_ha_r2_bl_credits_empty }, { .name = "UNC_R3_QPI0_AD_CREDITS_EMPTY", .desc = "QPI0 AD credits empty", .code = 0x29, .cntmsk = 0x3, .ngrp = 1, .modmsk = IVBEP_UNC_R3QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r3_qpi0_ad_credits_empty), .umasks = ivbep_unc_r3_qpi0_ad_credits_empty }, { .name = "UNC_R3_QPI0_BL_CREDITS_EMPTY", .desc = "QPI0 BL credits empty", .code = 0x2d, .cntmsk = 0x3, .ngrp = 1, .modmsk = IVBEP_UNC_R3QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r3_qpi0_ad_credits_empty), /* shared */ .umasks = ivbep_unc_r3_qpi0_ad_credits_empty }, { .name = "UNC_R3_QPI1_AD_CREDITS_EMPTY", .desc = "QPI1 AD credits empty", .code = 0x2a, .cntmsk = 0x3, .ngrp = 1, .modmsk = IVBEP_UNC_R3QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r3_qpi0_ad_credits_empty), /* shared */ .umasks = ivbep_unc_r3_qpi0_ad_credits_empty }, { .name = "UNC_R3_QPI1_BL_CREDITS_EMPTY", .desc = "QPI1 BL credits empty", .code = 0x2e, .cntmsk = 0x3, .ngrp = 1, .modmsk = IVBEP_UNC_R3QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r3_qpi0_ad_credits_empty), /* shared */ .umasks = ivbep_unc_r3_qpi0_ad_credits_empty }, { .name = "UNC_R3_TXR_CYCLES_NE", .desc = "Egress cycles not empty", .code = 0x23, .cntmsk = 0x3, .modmsk = IVBEP_UNC_R3QPI_ATTRS, }, { .name = "UNC_R3_TXR_NACK_CCW", .desc = "Egress NACK counter-clockwise", .code = 0x28, .cntmsk = 0x3, .ngrp = 1, .modmsk = IVBEP_UNC_R3QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r3_txr_nack_ccw), .umasks = ivbep_unc_r3_txr_nack_ccw }, { .name = "UNC_R3_TXR_NACK_CW", .desc = "Egress NACK counter-clockwise", .code = 0x26, .cntmsk = 0x3, .ngrp = 1, .modmsk = IVBEP_UNC_R3QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r3_txr_nack_cw), .umasks = ivbep_unc_r3_txr_nack_cw }, { .name = "UNC_R3_VN1_CREDITS_REJECT", .desc = "VN1 Credit Acquisition Failed", .code = 0x39, .cntmsk = 0x3, .ngrp = 1, .modmsk = IVBEP_UNC_R3QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r3_vn0_credits_used), /* shared */ .umasks = ivbep_unc_r3_vn0_credits_used }, { .name = "UNC_R3_VN1_CREDITS_USED", .desc = "VN0 Credit Used", .code = 0x38, .cntmsk = 0x3, .ngrp = 1, .modmsk = IVBEP_UNC_R3QPI_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r3_vn0_credits_used), /* shared */ .umasks = ivbep_unc_r3_vn0_credits_used }, }; libpfm-4.9.0/lib/events/amd64_events_fam16h.h0000664000175000017500000010661213223402656020510 0ustar eranianeranian/* * Copyright (c) 2017 by Vince Weaver * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * PMU: amd64_fam16h (AMD64 Fam16h) */ /* Dispatched FPU 0x0 */ static const amd64_umask_t amd64_fam16h_dispatched_fpu[]={ { .uname = "PIPE0", .udesc = "Pipe0 dispatches", .ucode = 0x1, }, { .uname = "PIPE1", .udesc = "Pipe1 dispatches", .ucode = 0x2, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; /* Retired SSE/AVX 0x03 */ static const amd64_umask_t amd64_fam16h_retired_sse_operations[]={ { .uname = "SINGLE_ADD_SUB_OPS", .udesc = "Single precision add/subtract ops", .ucode = 0x1, }, { .uname = "SINGLE_MUL_OPS", .udesc = "Single precision multiply ops", .ucode = 0x2, }, { .uname = "SINGLE_DIV_OPS", .udesc = "Single precision divide/square root ops", .ucode = 0x4, }, { .uname = "DOUBLE_ADD_SUB_OPS", .udesc = "Double precision add/subtract ops", .ucode = 0x10, }, { .uname = "DOUBLE_MUL_OPS", .udesc = "Double precision multiply ops", .ucode = 0x20, }, { .uname = "DOUBLE_DIV_OPS", .udesc = "Double precision divide/square root ops", .ucode = 0x40, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x7f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; /* Retired serializing ops 0x05 */ static const amd64_umask_t amd64_fam16h_retired_serializing_ops[]={ { .uname = "SSE_BOTTOM_EXECUTING_UOPS", .udesc = "SSE bottom-executing uops retired", .ucode = 0x1, }, { .uname = "SSE_CONTROL_RENAMING_UOPS", .udesc = "SSE control-renaming uops retired", .ucode = 0x2, }, { .uname = "X87_BOTTOM_EXECUTING_UOPS", .udesc = "X87 bottom-executing uops retired", .ucode = 0x4, }, { .uname = "X87_CONTROL_RENAMING_UOPS", .udesc = "X87 control-renaming uops retired", .ucode = 0x8, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xf, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; /* Retired x87 ops 0x11 */ static const amd64_umask_t amd64_fam16h_retired_x87_ops[]={ { .uname = "ADD_AND_SUB", .udesc = "Add and subtract", .ucode = 0x1, }, { .uname = "MULTIPLY", .udesc = "Multiply", .ucode = 0x2, }, { .uname = "DIVIDE_AND_FSQRT", .udesc = "Divide and fsqrt", .ucode = 0x4, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xf, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; /* Segment Register Loads 0x20 */ static const amd64_umask_t amd64_fam16h_segment_register_loads[]={ { .uname = "ES", .udesc = "ES", .ucode = 0x1, }, { .uname = "CS", .udesc = "CS", .ucode = 0x2, }, { .uname = "SS", .udesc = "SS", .ucode = 0x4, }, { .uname = "DS", .udesc = "DS", .ucode = 0x8, }, { .uname = "FS", .udesc = "FS", .ucode = 0x10, }, { .uname = "GS", .udesc = "GS", .ucode = 0x20, }, { .uname = "HS", .udesc = "HS", .ucode = 0x40, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x7f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; /* Pipeline Restart 0x21 */ static const amd64_umask_t amd64_fam16h_pipeline_restart[]={ { .uname = "INVALIDATING_PROBES", .udesc = "Evictions caused by invalidating probes", .ucode = 0x1, }, { .uname = "FILLS", .udesc = "Evictions caused by fills", .ucode = 0x2, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; /* Locked Operations 0x24 */ static const amd64_umask_t amd64_fam16h_locked_ops[]={ { .uname = "EXECUTED", .udesc = "The number of locked instructions executed", .ucode = 0x1, }, { .uname = "CYCLES_TO_ACQUIRE", .udesc = "The number of cycles to acquire bus lock", .ucode = 0x2, }, { .uname = "CYCLES_TO_UNLOCK", .udesc = "The number of cycles to unlock cache line", .ucode = 0x4, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x7, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; /* LS Dispatch 0x29 */ static const amd64_umask_t amd64_fam16h_ls_dispatch[]={ { .uname = "LOADS", .udesc = "The number of loads", .ucode = 0x1, }, { .uname = "STORES", .udesc = "The number of stores", .ucode = 0x2, }, { .uname = "LOAD_OP_STORES", .udesc = "The number of load-op-stores", .ucode = 0x4, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x7, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; /* Cancells Store to Load 0x2a */ static const amd64_umask_t amd64_fam16h_cancelled_store_to_load_forward_operations[]={ { .uname = "ADDRESS_MISMATCHES", .udesc = "Address mismatches (starting byte not the same).", .ucode = 0x1, }, { .uname = "STORE_IS_SMALLER_THAN_LOAD", .udesc = "Store is smaller than load.", .ucode = 0x2, }, { .uname = "MISALIGNED", .udesc = "Misaligned.", .ucode = 0x4, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x7, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; /* Data cache refills 0x42 */ static const amd64_umask_t amd64_fam16h_data_cache_refills[]={ { .uname = "NON_CACHABLE", .udesc = "Non-cachable", .ucode = 0x1, }, { .uname = "SHARED", .udesc = "Shared", .ucode = 0x2, }, { .uname = "EXCLUSIVE", .udesc = "Exclusive", .ucode = 0x4, }, { .uname = "OWNED", .udesc = "Owned", .ucode = 0x8, }, { .uname = "MODIFIED", .udesc = "Modified", .ucode = 0x10, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x1f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; /* Cache refills from northbridge 0x43 */ static const amd64_umask_t amd64_fam16h_data_cache_refills_from_system[]={ { .uname = "NON_CACHABLE", .udesc = "non-cachable", .ucode = 0x1, }, { .uname = "SHARED", .udesc = "Shared", .ucode = 0x2, }, { .uname = "EXCLUSIVE", .udesc = "Exclusive", .ucode = 0x4, }, { .uname = "OWNED", .udesc = "Owned", .ucode = 0x8, }, { .uname = "MODIFIED", .udesc = "Modified", .ucode = 0x10, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x1f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; /* Data cache lines evicted 0x44 */ static const amd64_umask_t amd64_fam16h_data_cache_lines_evicted[]={ { .uname = "EVICTED", .udesc = "Evicted from probe", .ucode = 0x1, }, { .uname = "SHARED", .udesc = "Shared eviction", .ucode = 0x2, }, { .uname = "EXCLUSIVE", .udesc = "Exclusive eviction", .ucode = 0x4, }, { .uname = "OWNED", .udesc = "Owned eviction", .ucode = 0x8, }, { .uname = "MODIFIED", .udesc = "Modified eviction", .ucode = 0x10, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x1f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; /* DTLB Miss 0x46 */ static const amd64_umask_t amd64_fam16h_dtlb_miss[]={ { .uname = "STORES_L1TLB", .udesc = "Stores that miss L1TLB", .ucode = 0x1, }, { .uname = "LOADS_L1TLB", .udesc = "Loads that miss L1TLB", .ucode = 0x2, }, { .uname = "STORES_L2TLB", .udesc = "Stores that miss L2TLB", .ucode = 0x4, }, { .uname = "LOADS_L2TLB", .udesc = "Loads that miss L2TLB", .ucode = 0x8, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xf, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; /* Misaligned accesses 0x47 */ static const amd64_umask_t amd64_fam16h_misaligned_accesses[]={ { .uname = "MISALIGN_16B", .udesc = "Misaligns that cross 16 Byte boundary", .ucode = 0x1, }, { .uname = "MISALIGN_4KB", .udesc = "Misaligns that cross a 4kB boundary", .ucode = 0x2, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; /* Prefetch Instruction Dispatched 0x4b */ static const amd64_umask_t amd64_fam16h_prefetch_instructions_dispatched[]={ { .uname = "LOAD", .udesc = "Load (Prefetch, PrefetchT0/T1/T2)", .ucode = 0x1, }, { .uname = "STORE", .udesc = "Store (PrefetchW)", .ucode = 0x2, }, { .uname = "NTA", .udesc = "NTA (PrefetchNTA)", .ucode = 0x4, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x7, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; /* L1 DTLB Hit 0x4d */ static const amd64_umask_t amd64_fam16h_l1_dtlb_hit[]={ { .uname = "L1_4K_TLB_HIT", .udesc = "L1 4K TLB hit", .ucode = 0x1, }, { .uname = "L1_2M_TLB_HIT", .udesc = "L1 2M TLB hit", .ucode = 0x2, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; /* Ineffective SW Prefetch 0x52 */ static const amd64_umask_t amd64_fam16h_ineffective_sw_prefetches[]={ { .uname = "SW_PREFETCH_DATA_CACHE", .udesc = "Software prefetch hit in data cache", .ucode = 0x1, }, { .uname = "SW_PREFETCH_PENDING_FILL", .udesc = "Software prefetch hit a pending fill", .ucode = 0x2, }, { .uname = "SW_PREFETCH_MAB", .udesc = "Software prefetches that don't get a MAB", .ucode = 0x4, }, { .uname = "SW_PREFETCH_HIT_L2", .udesc = "Software prefetches that hit in L2", .ucode = 0x8, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xf, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; /* Uncachable Memory 0x61 */ static const amd64_umask_t amd64_fam16h_uncachable_memory[]={ { .uname = "READ_BYTE", .udesc = "Read byte", .ucode = 0x1, }, { .uname = "READ_DOUBLEWORD", .udesc = "Read doubleword", .ucode = 0x2, }, { .uname = "WRITE_BYTE", .udesc = "Write byte", .ucode = 0x10, }, { .uname = "WRITE_DOUBLEWORD", .udesc = "Write doubleword", .ucode = 0x20, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x33, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; /* Read Block Operations 0x62 */ static const amd64_umask_t amd64_fam16h_read_block[]={ { .uname = "READ_BLOCK", .udesc = "Read block", .ucode = 0x1, }, { .uname = "RDBLKMOD", .udesc = "RdBlkMod", .ucode = 0x2, }, { .uname = "READ_BLOCK_SHARED", .udesc = "Read block shared", .ucode = 0x4, }, { .uname = "READ_BLOCK_SPEC", .udesc = "Read block speculative", .ucode = 0x10, }, { .uname = "READ_BLOCK_SPEC_MOD", .udesc = "Read block speculative modified", .ucode = 0x20, }, { .uname = "READ_BLOCK_SPEC_SHARED", .udesc = "Read block speculative shared", .ucode = 0x40, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x77, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; /* Change to Dirty 0x63 */ static const amd64_umask_t amd64_fam16h_change_dirty[]={ { .uname = "CHANGE_DIRTY", .udesc = "Change to dirty", .ucode = 0x10, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x10, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; /* Memory Requests 0x65 */ static const amd64_umask_t amd64_fam16h_memory_requests[]={ { .uname = "NON_CACHEABLE", .udesc = "Requests to non-cacheable (UC) memory", .ucode = 0x1, }, { .uname = "WRITE_COMBINING", .udesc = "Requests to write-combining (WC) memory or WC buffer flushes to WB memory", .ucode = 0x2, }, { .uname = "STREAMING_STORE", .udesc = "Streaming store (SS) requests", .ucode = 0x80, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x83, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; /* Data Cache Prefetches 0x67 */ static const amd64_umask_t amd64_fam16h_data_prefetches[]={ { .uname = "ATTEMPTED", .udesc = "Prefetch attempts", .ucode = 0x2, }, { .uname = "MAB", .udesc = "Hits on MAB", .ucode = 0x8, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xa, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; /* MAB Requests 0x68 and 0x69 */ static const amd64_umask_t amd64_fam16h_mab_requests[]={ { .uname = "DC_MISS0", .udesc = "Data cache miss buffer 0", .ucode = 0x1, }, { .uname = "DC_MISS1", .udesc = "Data cache miss buffer 1", .ucode = 0x2, }, { .uname = "DC_MISS2", .udesc = "Data cache miss buffer 2", .ucode = 0x4, }, { .uname = "DC_MISS3", .udesc = "Data cache miss buffer 3", .ucode = 0x8, }, { .uname = "DC_MISS4", .udesc = "Data cache miss buffer 4", .ucode = 0x10, }, { .uname = "DC_MISS5", .udesc = "Data cache miss buffer 5", .ucode = 0x20, }, { .uname = "DC_MISS6", .udesc = "Data cache miss buffer 6", .ucode = 0x40, }, { .uname = "DC_MISS7", .udesc = "Data cache miss buffer 7", .ucode = 0x80, }, { .uname = "IC_MISS0", .udesc = "Instruction cache miss buffer 0", .ucode = 0x100, }, { .uname = "IC_MISS1", .udesc = "Instruction cache miss buffer 1", .ucode = 0x200, }, { .uname = "DC_ANY", .udesc = "Any data cache miss buffer", .ucode = 0x800, }, { .uname = "IC_ANY", .udesc = "Any instruction cache miss buffer", .ucode = 0x1000, }, }; /* System Response by Coherence 0x6c */ static const amd64_umask_t amd64_fam16h_system_responses[]={ { .uname = "EXCLUSIVE", .udesc = "Exclusive", .ucode = 0x1, }, { .uname = "MODIFIED", .udesc = "Modified", .ucode = 0x2, }, { .uname = "SHARED", .udesc = "Shared", .ucode = 0x4, }, { .uname = "OWNED", .udesc = "Owned", .ucode = 0x8, }, { .uname = "DATA_ERROR", .udesc = "Data Error", .ucode = 0x10, }, { .uname = "CHANGE_DIRTY", .udesc = "Change to dirty success", .ucode = 0x20, }, { .uname = "UNCACHEABLE", .udesc = "Uncacheable", .ucode = 0x40, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x7f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; /* Data written to system 0x6d */ static const amd64_umask_t amd64_fam16h_data_written_to_system[]={ { .uname = "DATA_LINE_EVICTIONS", .udesc = "Data line evictions", .ucode = 0x1, }, { .uname = "INSTRUCTION_ATTRIBUTE_EVICTIONS", .udesc = "Instruction attribute evictions", .ucode = 0x2, }, { .uname = "BYTE_ENABLE_MASK_UNCACHEABLE", .udesc = "Byte enable mask for uncacheabe or I/O store", .ucode = 0x4, }, { .uname = "DATA_FOR_UNCACHEABLE", .udesc = "Data for uncacheabe or I/O store", .ucode = 0x8, }, { .uname = "BYTE_ENABLE_MASK_WRITE_COMBINE", .udesc = "Byte enable mask for write combine context flush", .ucode = 0x10, }, { .uname = "DATA_FOR_WRITE_COMBINE", .udesc = "Data for write combine contet flush", .ucode = 0x20, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; /* cache cross invalidate 0x75 */ static const amd64_umask_t amd64_fam16h_cache_cross_invalidates[]={ { .uname = "DC_INVALIDATES_IC", .udesc = "Modification of instructions of data too close to code", .ucode = 0x1, }, { .uname = "DC_INVALIDATES_DC", .udesc = "CD or WBINVD", .ucode = 0x2, }, { .uname = "IC_INVALIDATES_IC", .udesc = "aliasing", .ucode = 0x4, }, { .uname = "IC_INVALIDATES_DC_DIRTY", .udesc = "Exection of modified instruction or data too close to code", .ucode = 0x8, }, { .uname = "IC_HITS_DC_CLEAN_LINE", .udesc = "Reading code", .ucode = 0x10, }, { .uname = "DC_PROBE_REJECTED_EARLY", .udesc = "DC probe rejected early", .ucode = 0x20, }, { .uname = "DC_PROBE_REJECTED_LATE", .udesc = "DC probe rejected late", .ucode = 0x40, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x7f, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; /* PDC Miss 0x162 */ static const amd64_umask_t amd64_fam16h_pdc_miss[]={ { .uname = "HOST_PDE_LEVEL", .udesc = "Host: PDE level", .ucode = 0x1, }, { .uname = "HOST_PDPE_LEVEL", .udesc = "Host: PDPE level", .ucode = 0x2, }, { .uname = "HOST_PML4E_LEVEL", .udesc = "Host: PML4E level", .ucode = 0x4, }, { .uname = "GUEST_PDE_LEVEL", .udesc = "Guest: PDE level", .ucode = 0x10, }, { .uname = "GUEST_PDPE_LEVEL", .udesc = "Guest: PDPE level", .ucode = 0x20, }, { .uname = "GUEST_PML4E_LEVEL", .udesc = "Guest: PML4E level", .ucode = 0x40, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x77, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; /* ITLB Miss 0x85 */ static const amd64_umask_t amd64_fam16h_itlb_miss[]={ { .uname = "4K_PAGE_FETCHES", .udesc = "Instruction fetches to a 4K page.", .ucode = 0x1, }, { .uname = "2M_PAGE_FETCHES", .udesc = "Instruction fetches to a 2M page.", .ucode = 0x2, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; /* Instruction Cache Lines Invalidated 0x8c */ static const amd64_umask_t amd64_fam16h_instruction_cache_lines_invalidated[]={ { .uname = "IC_INVALIDATE_LS_PROBE", .udesc = "Instruction cache invalidate due to LS probe", .ucode = 0x1, }, { .uname = "IC_INVALIDATE_BU_PROBE", .udesc = "Instruction cache invalidate due to BU probe", .ucode = 0x2, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; /* Retired indirect branch info (0x19a) */ static const amd64_umask_t amd64_fam16h_retired_branch_info[]={ { .uname = "RETIRED", .udesc = "Retired indirect branch instruction.", .ucode = 0x1, }, { .uname = "MISPREDICTED", .udesc = "Retired mispredicted near unconditional jump.", .ucode = 0x2, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; /* Retired MMX/FP instructions 0xcb */ static const amd64_umask_t amd64_fam16h_retired_mmx_and_fp_instructions[]={ { .uname = "X87", .udesc = "X87 instructions", .ucode = 0x1, }, { .uname = "SSE", .udesc = "SSE, SSE2, SSE3, MNI instructions", .ucode = 0x2, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0x3, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; /* FPU exceptions 0xdb */ static const amd64_umask_t amd64_fam16h_fpu_exceptions[]={ { .uname = "X87_RECLASS_MICROFAULTS", .udesc = "X87 reclass microfaults", .ucode = 0x1, }, { .uname = "SSE_RETYPE_MICROFAULTS", .udesc = "SSE retype microfaults", .ucode = 0x2, }, { .uname = "SSE_RECLASS_MICROFAULTS", .udesc = "SSE reclass microfaults", .ucode = 0x4, }, { .uname = "SSE_AND_X87_MICROTRAPS", .udesc = "SSE and x87 microtraps", .ucode = 0x8, }, { .uname = "ALL", .udesc = "All sub-events selected", .ucode = 0xf, .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, }, }; static const amd64_entry_t amd64_fam16h_pe[]={ { .name = "DISPATCHED_FPU", .desc = "Dispatched FPU Operations", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x0, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam16h_dispatched_fpu), .ngrp = 1, .umasks = amd64_fam16h_dispatched_fpu, }, { .name = "FP_SCHEDULER_EMPTY", .desc = "Cycles in which the FPU is Empty", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x1, }, { .name = "DISPATCHED_FPU_OPS_FAST_FLAG", .desc = "Dispatched Fast Flag FPU Operations", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x2, }, { .name = "RETIRED_SSE_AVX_OPERATIONS", .desc = "Retired SSE/AVX Operations", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x3, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam16h_retired_sse_operations), .ngrp = 1, .umasks = amd64_fam16h_retired_sse_operations, }, { .name = "RETIRED_SERIALIZING_OPS", .desc = "Retired Serializing Ops", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x5, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam16h_retired_serializing_ops), .ngrp = 1, .umasks = amd64_fam16h_retired_serializing_ops, }, { .name = "RETIRED_X87_OPERATIONS", .desc = "Retired x87 operations", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x11, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam16h_retired_x87_ops), .ngrp = 1, .umasks = amd64_fam16h_retired_x87_ops, }, { .name = "SEGMENT_REGISTER_LOADS", .desc = "Segment Register Loads", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x20, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam16h_segment_register_loads), .ngrp = 1, .umasks = amd64_fam16h_segment_register_loads, }, { .name = "PIPELINE_RESTART_DUE_TO_SELF_MODIFYING_CODE", .desc = "Pipeline Restart Due to Self-Modifying Code", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x21, }, { .name = "PIPELINE_RESTART_DUE_TO_PROBE_HIT", .desc = "Pipeline Restart Due to Probe Hit", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x22, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam16h_pipeline_restart), .ngrp = 1, .umasks = amd64_fam16h_pipeline_restart, }, { .name = "LOCKED_OPS", .desc = "Locked Operations", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x24, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam16h_locked_ops), .ngrp = 1, .umasks = amd64_fam16h_locked_ops, }, { .name = "RETIRED_CLFLUSH_INSTRUCTIONS", .desc = "Retired CLFLUSH Instructions", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x26, }, { .name = "RETIRED_CPUID_INSTRUCTIONS", .desc = "Retired CPUID Instructions", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x27, }, { .name = "LS_DISPATCH", .desc = "Transactions dispatched to load-store unit", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x29, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam16h_ls_dispatch), .ngrp = 1, .umasks = amd64_fam16h_ls_dispatch, }, { .name = "CANCELLED_STORE_TO_LOAD_FORWARD_OPERATIONS", .desc = "Cancelled Store to Load Forward Operations", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x2a, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam16h_cancelled_store_to_load_forward_operations), .ngrp = 1, .umasks = amd64_fam16h_cancelled_store_to_load_forward_operations, }, { .name = "DATA_CACHE_ACCESSES", .desc = "Data Cache Accesses", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x40, }, { .name = "DATA_CACHE_MISSES", .desc = "Data Cache Misses", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x41, }, { .name = "DATA_CACHE_REFILLS", .desc = "Data Cache Refills from L2 or Northbridge", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x42, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam16h_data_cache_refills), .ngrp = 1, .umasks = amd64_fam16h_data_cache_refills, }, { .name = "DATA_CACHE_REFILLS_FROM_NORTHBRIDGE", .desc = "Data Cache Refills from the Northbridge", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x43, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam16h_data_cache_refills_from_system), .ngrp = 1, .umasks = amd64_fam16h_data_cache_refills_from_system, }, { .name = "DATA_CACHE_LINES_EVICTED", .desc = "Data Cache Lines Evicted", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x44, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam16h_data_cache_lines_evicted), .ngrp = 1, .umasks = amd64_fam16h_data_cache_lines_evicted, }, { .name = "L1_DTLB_MISS_AND_L2_DTLB_HIT", .desc = "L1 DTLB Miss and L2 DTLB Hit", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x45, }, { .name = "DTLB_MISS", .desc = "L1 DTLB and L2 DTLB Miss", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x46, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam16h_dtlb_miss), .ngrp = 1, .umasks = amd64_fam16h_dtlb_miss, }, { .name = "MISALIGNED_ACCESSES", .desc = "Misaligned Accesses", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x47, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam16h_misaligned_accesses), .ngrp = 1, .umasks = amd64_fam16h_misaligned_accesses, }, { .name = "PREFETCH_INSTRUCTIONS_DISPATCHED", .desc = "Prefetch Instructions Dispatched", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x4b, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam16h_prefetch_instructions_dispatched), .ngrp = 1, .umasks = amd64_fam16h_prefetch_instructions_dispatched, }, { .name = "DCACHE_MISSES_BY_LOCKED_INSTRUCTIONS", .desc = "DCACHE Misses by Locked Instructions", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x4c, }, { .name = "L1_DTLB_HIT", .desc = "L1 DTLB Hit", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x4d, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam16h_l1_dtlb_hit), .ngrp = 1, .umasks = amd64_fam16h_l1_dtlb_hit, }, { .name = "INEFFECTIVE_SW_PREFETCHES", .desc = "Ineffective Software Prefetches", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x52, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam16h_ineffective_sw_prefetches), .ngrp = 1, .umasks = amd64_fam16h_ineffective_sw_prefetches, }, { .name = "GLOBAL_TLB_FLUSHES", .desc = "Global TLB Flushes", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x54, }, /* fam30h only */ { .name = "COMMAND_RELATED_UNCACHABLE", .desc = "Commands realted to uncachable memory and I/O", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x61, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam16h_uncachable_memory), .ngrp = 1, .umasks = amd64_fam16h_uncachable_memory, }, { .name = "COMMAND_RELATED_READ_BLOCK", .desc = "Commands realted to read block operations", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x62, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam16h_read_block), .ngrp = 1, .umasks = amd64_fam16h_read_block, }, { .name = "COMMAND_RELATED_DIRTY", .desc = "Commands realted to change dirty operations", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x63, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam16h_change_dirty), .ngrp = 1, .umasks = amd64_fam16h_change_dirty, }, { .name = "MEMORY_REQUESTS", .desc = "Memory Requests by Type", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x65, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam16h_memory_requests), .ngrp = 1, .umasks = amd64_fam16h_memory_requests, }, { .name = "DATA_PREFETCHES", .desc = "Data Prefetches", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x67, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam16h_data_prefetches), .ngrp = 1, .umasks = amd64_fam16h_data_prefetches, }, { .name = "MAB_REQUESTS", .desc = "Miss address buffer requests", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x68, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam16h_mab_requests), .ngrp = 1, .umasks = amd64_fam16h_mab_requests, }, { .name = "MAB_WAIT_CYCLES", .desc = "Miss address buffer wait cycles", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x69, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam16h_mab_requests), .ngrp = 1, .umasks = amd64_fam16h_mab_requests, }, { .name = "SYSTEM_RESPONSES", .desc = "L2I Responses by Coherency State", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x6c, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam16h_system_responses), .ngrp = 1, .umasks = amd64_fam16h_system_responses, }, { .name = "DATA_WRITTEN_TO_SYSTEM", .desc = "16-byte transfers written to system", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x6d, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam16h_data_written_to_system), .ngrp = 1, .umasks = amd64_fam16h_data_written_to_system, }, { .name = "CACHE_CROSS_INVALIDATES", .desc = "Internal probes causing cache lines to be invalidated", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x75, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam16h_cache_cross_invalidates), .ngrp = 1, .umasks = amd64_fam16h_cache_cross_invalidates, }, { .name = "CPU_CLK_UNHALTED", .desc = "CPU Clocks not Halted", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x76, }, { .name = "PDC_MISS", .desc = "Number of PDC misses", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x162, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam16h_pdc_miss), .ngrp = 1, .umasks = amd64_fam16h_pdc_miss, }, { .name = "INSTRUCTION_CACHE_FETCHES", .desc = "Instruction Cache Fetches", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x80, }, { .name = "INSTRUCTION_CACHE_MISSES", .desc = "Instruction Cache Misses", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x81, }, { .name = "INSTRUCTION_CACHE_REFILLS_FROM_L2", .desc = "Instruction Cache Refills from L2", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x82, }, { .name = "INSTRUCTION_CACHE_REFILLS_FROM_SYSTEM", .desc = "Instruction Cache Refills from System", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x83, }, { .name = "L1_ITLB_MISS_AND_L2_ITLB_HIT", .desc = "L1 ITLB Miss and L2 ITLB Hit", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x84, }, { .name = "ITLB_MISS", .desc = "Instruction fetches that miss in 4k and 2M ITLB", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x85, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam16h_itlb_miss), .ngrp = 1, .umasks = amd64_fam16h_itlb_miss, }, { .name = "INSTRUCTION_FETCH_STALL", .desc = "Instruction Fetch Stall", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x87, }, { .name = "RETURN_STACK_HITS", .desc = "Return Stack Hits", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x88, }, { .name = "RETURN_STACK_OVERFLOWS", .desc = "Return Stack Overflows", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x89, }, { .name = "INSTRUCTION_CACHE_VICTIMS", .desc = "Instruction Cache Victims", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x8b, }, { .name = "INSTRUCTION_CACHE_LINES_INVALIDATED", .desc = "Instruction Cache Lines Invalidated", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x8c, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam16h_instruction_cache_lines_invalidated), .ngrp = 1, .umasks = amd64_fam16h_instruction_cache_lines_invalidated, }, { .name = "ITLB_RELOADS", .desc = "ITLB Reloads", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x99, }, { .name = "ITLB_RELOADS_ABORTED", .desc = "ITLB reloads aborted", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x9a, }, { .name = "RETIRED_INDIRECT_BRANCH_INFO", .desc = "Retired indirect branch info", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x19a, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam16h_retired_branch_info), .ngrp = 1, .umasks = amd64_fam16h_retired_branch_info, }, { .name = "RETIRED_INSTRUCTIONS", .desc = "Retired Instructions", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xc0, }, { .name = "RETIRED_UOPS", .desc = "Retired uops", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xc1, }, { .name = "RETIRED_BRANCH_INSTRUCTIONS", .desc = "Retired Branch Instructions", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xc2, }, { .name = "RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS", .desc = "Retired Mispredicted Branch Instructions", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xc3, }, { .name = "RETIRED_TAKEN_BRANCH_INSTRUCTIONS", .desc = "Retired Taken Branch Instructions", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xc4, }, { .name = "RETIRED_TAKEN_BRANCH_INSTRUCTIONS_MISPREDICTED", .desc = "Retired Taken Branch Instructions Mispredicted", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xc5, }, { .name = "RETIRED_FAR_CONTROL_TRANSFERS", .desc = "Retired Far Control Transfers", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xc6, }, { .name = "RETIRED_BRANCH_RESYNCS", .desc = "Retired Branch Resyncs", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xc7, }, { .name = "RETIRED_NEAR_RETURNS", .desc = "Retired Near Returns", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xc8, }, { .name = "RETIRED_NEAR_RETURNS_MISPREDICTED", .desc = "Retired Near Returns Mispredicted", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xc9, }, { .name = "RETIRED_MISPREDICTED_TAKEN", .desc = "Retired mispredicted taken branches due to target mismatch", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xca, }, { .name = "RETIRED_MMX_AND_FP_INSTRUCTIONS", .desc = "Retired MMX/FP Instructions", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xcb, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam16h_retired_mmx_and_fp_instructions), .ngrp = 1, .umasks = amd64_fam16h_retired_mmx_and_fp_instructions, }, { .name = "INTERRUPTS_MASKED_CYCLES", .desc = "Interrupts-Masked Cycles", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xcd, }, { .name = "INTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDING", .desc = "Interrupts-Masked Cycles with Interrupt Pending", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xce, }, { .name = "INTERRUPTS_TAKEN", .desc = "Interrupts Taken", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xcf, }, { .name = "FPU_EXCEPTIONS", .desc = "FPU Exceptions", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xdb, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam16h_fpu_exceptions), .ngrp = 1, .umasks = amd64_fam16h_fpu_exceptions, }, { .name = "DR0_BREAKPOINT_MATCHES", .desc = "DR0 Breakpoint Matches", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xdc, }, { .name = "DR1_BREAKPOINT_MATCHES", .desc = "DR1 Breakpoint Matches", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xdd, }, { .name = "DR2_BREAKPOINT_MATCHES", .desc = "DR2 Breakpoint Matches", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xde, }, { .name = "DR3_BREAKPOINT_MATCHES", .desc = "DR3 Breakpoint Matches", .modmsk = AMD64_FAM10H_ATTRS, .code = 0xdf, }, { .name = "TAGGED_IBS_OPS", .desc = "Ops tagged by IBS", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x1cf, }, { .name = "TAGGED_IBS_OPS_RETIRED", .desc = "Ops tagged by IBS that retired", .modmsk = AMD64_FAM10H_ATTRS, .code = 0x1d0, }, }; libpfm-4.9.0/lib/events/intel_bdx_unc_r2pcie_events.h0000664000175000017500000002666513223402656022525 0ustar eranianeranian/* * Copyright (c) 2017 Google Inc. All rights reserved * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * PMU: bdx_unc_r2pcie */ static intel_x86_umask_t bdx_unc_r2_iio_credit[]={ { .uname = "ISOCH_QPI0", .ucode = 0x400, .udesc = "TBD", }, { .uname = "ISOCH_QPI1", .ucode = 0x800, .udesc = "TBD", }, { .uname = "PRQ_QPI0", .ucode = 0x100, .udesc = "TBD", }, { .uname = "PRQ_QPI1", .ucode = 0x200, .udesc = "TBD", }, }; static intel_x86_umask_t bdx_unc_r2_ring_ad_used[]={ { .uname = "CCW", .ucode = 0xc00, .udesc = "Counterclockwise", .uflags = INTEL_X86_NCOMBO, }, { .uname = "CCW_EVEN", .ucode = 0x400, .udesc = "Counterclockwise and Even", }, { .uname = "CCW_ODD", .ucode = 0x800, .udesc = "Counterclockwise and Odd", }, { .uname = "CW", .ucode = 0x300, .udesc = "Clockwise", .uflags = INTEL_X86_NCOMBO, }, { .uname = "CW_EVEN", .ucode = 0x100, .udesc = "Clockwise and Even", }, { .uname = "CW_ODD", .ucode = 0x200, .udesc = "Clockwise and Odd", }, }; static intel_x86_umask_t bdx_unc_r2_ring_ak_bounces[]={ { .uname = "DN", .ucode = 0x200, .udesc = "AK Ingress Bounced -- Dn", }, { .uname = "UP", .ucode = 0x100, .udesc = "AK Ingress Bounced -- Up", }, }; static intel_x86_umask_t bdx_unc_r2_ring_iv_used[]={ { .uname = "ANY", .ucode = 0xf00, .udesc = "Any directions", .uflags = INTEL_X86_DFL, }, { .uname = "CCW", .ucode = 0xc00, .udesc = "Counterclockwise", .uflags = INTEL_X86_NCOMBO, }, { .uname = "CW", .ucode = 0x300, .udesc = "Clockwise", .uflags = INTEL_X86_NCOMBO, }, }; static intel_x86_umask_t bdx_unc_r2_rxr_cycles_ne[]={ { .uname = "NCB", .ucode = 0x1000, .udesc = "NCB", }, { .uname = "NCS", .ucode = 0x2000, .udesc = "NCS", }, }; static intel_x86_umask_t bdx_unc_r2_rxr_occupancy[]={ { .uname = "DRS", .ucode = 0x800, .udesc = "Ingress Occupancy Accumulator -- DRS", .uflags = INTEL_X86_DFL, }, }; static intel_x86_umask_t bdx_unc_r2_sbo0_credits_acquired[]={ { .uname = "AD", .ucode = 0x100, .udesc = "SBo0 Credits Acquired -- For AD Ring", }, { .uname = "BL", .ucode = 0x200, .udesc = "SBo0 Credits Acquired -- For BL Ring", }, }; static intel_x86_umask_t bdx_unc_r2_stall_no_sbo_credit[]={ { .uname = "SBO0_AD", .ucode = 0x100, .udesc = "Stall on No Sbo Credits -- For SBo0, AD Ring", }, { .uname = "SBO0_BL", .ucode = 0x400, .udesc = "Stall on No Sbo Credits -- For SBo0, BL Ring", }, { .uname = "SBO1_AD", .ucode = 0x200, .udesc = "Stall on No Sbo Credits -- For SBo1, AD Ring", }, { .uname = "SBO1_BL", .ucode = 0x800, .udesc = "Stall on No Sbo Credits -- For SBo1, BL Ring", }, }; static intel_x86_umask_t bdx_unc_r2_txr_cycles_full[]={ { .uname = "AD", .ucode = 0x100, .udesc = "Egress Cycles Full -- AD", }, { .uname = "AK", .ucode = 0x200, .udesc = "Egress Cycles Full -- AK", }, { .uname = "BL", .ucode = 0x400, .udesc = "Egress Cycles Full -- BL", }, }; static intel_x86_umask_t bdx_unc_r2_txr_cycles_ne[]={ { .uname = "AD", .ucode = 0x100, .udesc = "Egress Cycles Not Empty -- AD", }, { .uname = "AK", .ucode = 0x200, .udesc = "Egress Cycles Not Empty -- AK", }, { .uname = "BL", .ucode = 0x400, .udesc = "Egress Cycles Not Empty -- BL", }, }; static intel_x86_umask_t bdx_unc_r2_txr_nack_cw[]={ { .uname = "DN_AD", .ucode = 0x100, .udesc = "Egress CCW NACK -- AD CCW", }, { .uname = "DN_AK", .ucode = 0x400, .udesc = "Egress CCW NACK -- AK CCW", }, { .uname = "DN_BL", .ucode = 0x200, .udesc = "Egress CCW NACK -- BL CCW", }, { .uname = "UP_AD", .ucode = 0x800, .udesc = "Egress CCW NACK -- AK CCW", }, { .uname = "UP_AK", .ucode = 0x2000, .udesc = "Egress CCW NACK -- BL CW", }, { .uname = "UP_BL", .ucode = 0x1000, .udesc = "Egress CCW NACK -- BL CCW", }, }; static intel_x86_entry_t intel_bdx_unc_r2_pe[]={ { .name = "UNC_R2_CLOCKTICKS", .code = 0x1, .desc = "Counts the number of uclks in the R2PCIe uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the R2PCIe is close to the Ubox, they generally should not diverge by more than a handful of cycles.", .modmsk = BDX_UNC_R2PCIE_ATTRS, .cntmsk = 0xf, }, { .name = "UNC_R2_IIO_CREDIT", .code = 0x2d, .desc = "TBD", .modmsk = BDX_UNC_R2PCIE_ATTRS, .cntmsk = 0x3, .ngrp = 1, .umasks = bdx_unc_r2_iio_credit, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_r2_iio_credit), }, { .name = "UNC_R2_RING_AD_USED", .code = 0x7, .desc = "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", .modmsk = BDX_UNC_R2PCIE_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_r2_ring_ad_used, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_r2_ring_ad_used), }, { .name = "UNC_R2_RING_AK_BOUNCES", .code = 0x12, .desc = "Counts the number of times when a request destined for the AK ingress bounced.", .modmsk = BDX_UNC_R2PCIE_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_r2_ring_ak_bounces, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_r2_ring_ak_bounces), }, { .name = "UNC_R2_RING_AK_USED", .code = 0x8, .desc = "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", .modmsk = BDX_UNC_R2PCIE_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_r2_ring_ad_used, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_r2_ring_ad_used), }, { .name = "UNC_R2_RING_BL_USED", .code = 0x9, .desc = "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", .modmsk = BDX_UNC_R2PCIE_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_r2_ring_ad_used, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_r2_ring_ad_used), }, { .name = "UNC_R2_RING_IV_USED", .code = 0xa, .desc = "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.", .modmsk = BDX_UNC_R2PCIE_ATTRS, .cntmsk = 0xf, .ngrp = 1, .umasks = bdx_unc_r2_ring_iv_used, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_r2_ring_iv_used), }, { .name = "UNC_R2_RXR_CYCLES_NE", .code = 0x10, .desc = "Counts the number of cycles when the R2PCIe Ingress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.", .modmsk = BDX_UNC_R2PCIE_ATTRS, .cntmsk = 0x3, .ngrp = 1, .umasks = bdx_unc_r2_rxr_cycles_ne, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_r2_rxr_cycles_ne), }, { .name = "UNC_R2_RXR_INSERTS", .code = 0x11, .desc = "Counts the number of allocations into the R2PCIe Ingress. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.", .modmsk = BDX_UNC_R2PCIE_ATTRS, .cntmsk = 0x3, .ngrp = 1, .umasks = bdx_unc_r2_rxr_cycles_ne, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_r2_rxr_cycles_ne), }, { .name = "UNC_R2_RXR_OCCUPANCY", .code = 0x13, .desc = "Accumulates the occupancy of a given R2PCIe Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the R2PCIe Ingress Not Empty event to calculate average occupancy or the R2PCIe Ingress Allocations event in order to calculate average queuing latency.", .modmsk = BDX_UNC_R2PCIE_ATTRS, .cntmsk = 0x1, .ngrp = 1, .umasks = bdx_unc_r2_rxr_occupancy, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_r2_rxr_occupancy), }, { .name = "UNC_R2_SBO0_CREDITS_ACQUIRED", .code = 0x28, .desc = "Number of Sbo 0 credits acquired in a given cycle, per ring.", .modmsk = BDX_UNC_R2PCIE_ATTRS, .cntmsk = 0x3, .ngrp = 1, .umasks = bdx_unc_r2_sbo0_credits_acquired, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_r2_sbo0_credits_acquired), }, { .name = "UNC_R2_STALL_NO_SBO_CREDIT", .code = 0x2c, .desc = "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.", .modmsk = BDX_UNC_R2PCIE_ATTRS, .cntmsk = 0x3, .ngrp = 1, .umasks = bdx_unc_r2_stall_no_sbo_credit, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_r2_stall_no_sbo_credit), }, { .name = "UNC_R2_TXR_CYCLES_FULL", .code = 0x25, .desc = "Counts the number of cycles when the R2PCIe Egress buffer is full.", .modmsk = BDX_UNC_R2PCIE_ATTRS, .cntmsk = 0x1, .ngrp = 1, .umasks = bdx_unc_r2_txr_cycles_full, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_r2_txr_cycles_full), }, { .name = "UNC_R2_TXR_CYCLES_NE", .code = 0x23, .desc = "Counts the number of cycles when the R2PCIe Egress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy. Only a single Egress queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", .modmsk = BDX_UNC_R2PCIE_ATTRS, .cntmsk = 0x1, .ngrp = 1, .umasks = bdx_unc_r2_txr_cycles_ne, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_r2_txr_cycles_ne), }, { .name = "UNC_R2_TXR_NACK_CW", .code = 0x26, .desc = "TBD", .modmsk = BDX_UNC_R2PCIE_ATTRS, .cntmsk = 0x3, .ngrp = 1, .umasks = bdx_unc_r2_txr_nack_cw, .numasks= LIBPFM_ARRAY_SIZE(bdx_unc_r2_txr_nack_cw), }, }; libpfm-4.9.0/lib/events/intel_hswep_unc_r2pcie_events.h0000664000175000017500000002046513223402656023066 0ustar eranianeranian/* * Copyright (c) 2014 Google Inc. All rights reserved * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * PMU: hswep_unc_r2pcie (Intel Haswell-EP R2PCIe uncore) */ static const intel_x86_umask_t hswep_unc_r2_ring_ad_used[]={ { .uname = "CCW_EVEN", .udesc = "Counter-clockwise and even ring polarity on virtual ring", .ucode = 0x400, }, { .uname = "CCW_ODD", .udesc = "Counter-clockwise and odd ring polarity on virtual ring", .ucode = 0x800, }, { .uname = "CW_EVEN", .udesc = "Clockwise and even ring polarity on virtual ring", .ucode = 0x100, }, { .uname = "CW_ODD", .udesc = "Clockwise and odd ring polarity on virtual ring", .ucode = 0x200, }, { .uname = "CW", .udesc = "Clockwise with any polarity on either virtual rings", .ucode = 0x0300, .uflags = INTEL_X86_NCOMBO, }, { .uname = "CCW", .udesc = "Counter-clockwise with any polarity on either virtual rings", .ucode = 0x0c00, .uflags = INTEL_X86_NCOMBO, }, }; static const intel_x86_umask_t hswep_unc_r2_rxr_ak_bounces[]={ { .uname = "UP", .udesc = "Up", .ucode = 0x100, }, { .uname = "DOWN", .udesc = "Down", .ucode = 0x200, }, }; static const intel_x86_umask_t hswep_unc_r2_rxr_occupancy[]={ { .uname = "DRS", .udesc = "DRS Ingress queue", .ucode = 0x800, .uflags = INTEL_X86_DFL, }, }; static const intel_x86_umask_t hswep_unc_r2_ring_iv_used[]={ { .uname = "CW", .udesc = "Clockwise with any polarity on virtual ring", .ucode = 0x300, .uflags = INTEL_X86_NCOMBO, }, { .uname = "CCW", .udesc = "Counter-clockwise with any polarity on virtual ring", .ucode = 0xc00, .uflags = INTEL_X86_NCOMBO, }, { .uname = "ANY", .udesc = "any direction and any polarity on virtual ring", .ucode = 0xff00, .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, }, }; static const intel_x86_umask_t hswep_unc_r2_rxr_cycles_ne[]={ { .uname = "NCB", .udesc = "NCB Ingress queue", .ucode = 0x1000, }, { .uname = "NCS", .udesc = "NCS Ingress queue", .ucode = 0x2000, }, }; static const intel_x86_umask_t hswep_unc_r2_sbo0_credits_acquired[]={ { .uname = "AD", .udesc = "For ring AD", .ucode = 0x100, }, { .uname = "BL", .udesc = "For ring BL", .ucode = 0x200, }, }; static const intel_x86_umask_t hswep_unc_r2_iio_credit[]={ { .uname = "PRQ_QPI0", .udesc = "QPI0", .ucode = 0x100, }, { .uname = "PRQ_QPI1", .udesc = "QPI1", .ucode = 0x200, }, { .uname = "ISOCH_QPI0", .udesc = "Isochronous QPI0", .ucode = 0x400, }, { .uname = "ISOCH_QPI1", .udesc = "Isochronous QPI1", .ucode = 0x800, }, }; static const intel_x86_umask_t hswep_unc_r2_txr_nack_cw[]={ { .uname = "DN_AD", .udesc = "AD counter clockwise Egress queue", .ucode = 0x100, }, { .uname = "DN_BL", .udesc = "BL counter clockwise Egress queue", .ucode = 0x200, }, { .uname = "DN_AK", .udesc = "AK counter clockwise Egress queue", .ucode = 0x400, }, { .uname = "UP_AD", .udesc = "AD clockwise Egress queue", .ucode = 0x800, }, { .uname = "UP_BL", .udesc = "BL clockwise Egress queue", .ucode = 0x1000, }, { .uname = "UP_AK", .udesc = "AK clockwise Egress queue", .ucode = 0x2000, }, }; static const intel_x86_umask_t hswep_unc_r2_stall_no_sbo_credit[]={ { .uname = "SBO0_AD", .udesc = "For SBO0, AD ring", .ucode = 0x100, }, { .uname = "SBO1_AD", .udesc = "For SBO1, AD ring", .ucode = 0x100, }, { .uname = "SBO0_BL", .udesc = "For SBO0, BL ring", .ucode = 0x100, }, { .uname = "SBO1_BL", .udesc = "For SBO1, BL ring", .ucode = 0x100, }, }; static const intel_x86_entry_t intel_hswep_unc_r2_pe[]={ { .name = "UNC_R2_CLOCKTICKS", .desc = "Number of uclks in domain", .code = 0x1, .cntmsk = 0xf, .modmsk = HSWEP_UNC_R2PCIE_ATTRS, }, { .name = "UNC_R2_RING_AD_USED", .desc = "R2 AD Ring in Use", .code = 0x7, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_R2PCIE_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_r2_ring_ad_used), .umasks = hswep_unc_r2_ring_ad_used }, { .name = "UNC_R2_RING_AK_USED", .desc = "R2 AK Ring in Use", .code = 0x8, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_R2PCIE_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_r2_ring_ad_used), .umasks = hswep_unc_r2_ring_ad_used /* shared */ }, { .name = "UNC_R2_RING_BL_USED", .desc = "R2 BL Ring in Use", .code = 0x9, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_R2PCIE_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_r2_ring_ad_used), .umasks = hswep_unc_r2_ring_ad_used /* shared */ }, { .name = "UNC_R2_RING_IV_USED", .desc = "R2 IV Ring in Use", .code = 0xa, .cntmsk = 0xf, .ngrp = 1, .modmsk = HSWEP_UNC_R2PCIE_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_r2_ring_iv_used), .umasks = hswep_unc_r2_ring_iv_used }, { .name = "UNC_R2_RXR_AK_BOUNCES", .desc = "AK Ingress Bounced", .code = 0x12, .cntmsk = 0xf, .modmsk = HSWEP_UNC_R2PCIE_ATTRS, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_r2_rxr_ak_bounces), .umasks = hswep_unc_r2_rxr_ak_bounces }, { .name = "UNC_R2_RXR_OCCUPANCY", .desc = "Ingress occupancy accumulator", .code = 0x13, .cntmsk = 0x1, .modmsk = HSWEP_UNC_R2PCIE_ATTRS, .ngrp = 1, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_r2_rxr_occupancy), .umasks = hswep_unc_r2_rxr_occupancy }, { .name = "UNC_R2_RXR_CYCLES_NE", .desc = "Ingress Cycles Not Empty", .code = 0x10, .cntmsk = 0x3, .ngrp = 1, .modmsk = HSWEP_UNC_R2PCIE_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_r2_rxr_cycles_ne), .umasks = hswep_unc_r2_rxr_cycles_ne }, { .name = "UNC_R2_RXR_INSERTS", .desc = "Ingress inserts", .code = 0x11, .cntmsk = 0x3, .ngrp = 1, .modmsk = HSWEP_UNC_R2PCIE_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_r2_rxr_cycles_ne), .umasks = hswep_unc_r2_rxr_cycles_ne, /* shared */ }, { .name = "UNC_R2_TXR_NACK_CW", .desc = "Egress clockwise BACK", .code = 0x26, .cntmsk = 0x3, .ngrp = 1, .modmsk = HSWEP_UNC_R2PCIE_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_r2_txr_nack_cw), .umasks = hswep_unc_r2_txr_nack_cw, }, { .name = "UNC_R2_SBO0_CREDITS_ACQUIRED", .desc = "SBO0 credits acquired", .code = 0x28, .cntmsk = 0x3, .ngrp = 1, .modmsk = HSWEP_UNC_R2PCIE_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_r2_sbo0_credits_acquired), .umasks = hswep_unc_r2_sbo0_credits_acquired, }, { .name = "UNC_R2_STALL_NO_SBO_CREDIT", .desc = "Stall on No SBo Credits", .code = 0x2c, .cntmsk = 0x3, .ngrp = 1, .modmsk = HSWEP_UNC_R2PCIE_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_r2_stall_no_sbo_credit), .umasks = hswep_unc_r2_stall_no_sbo_credit }, { .name = "UNC_R2_IIO_CREDIT", .desc = "Egress counter-clockwise BACK", .code = 0x2d, .cntmsk = 0x3, .ngrp = 1, .modmsk = HSWEP_UNC_R2PCIE_ATTRS, .numasks = LIBPFM_ARRAY_SIZE(hswep_unc_r2_iio_credit), .umasks = hswep_unc_r2_iio_credit, }, }; libpfm-4.9.0/lib/events/intel_ppro_events.h0000664000175000017500000004657113223402656020615 0ustar eranianeranian/* * Copyright (c) 2011 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * This file has been automatically generated. * * PMU: ppro (Intel Pentium Pro) */ static const intel_x86_umask_t ppro_l2_ifetch[]={ { .uname = "I", .udesc = "Invalid state", .ucode = 0x100, }, { .uname = "S", .udesc = "Shared state", .ucode = 0x200, }, { .uname = "E", .udesc = "Exclusive state", .ucode = 0x400, }, { .uname = "M", .udesc = "Modified state", .ucode = 0x800, }, }; static const intel_x86_umask_t ppro_bus_drdy_clocks[]={ { .uname = "SELF", .udesc = "Clocks when processor is driving bus", .ucode = 0x0, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, { .uname = "ANY", .udesc = "Clocks when any agent is driving bus", .ucode = 0x2000, .uflags= INTEL_X86_NCOMBO, }, }; static const intel_x86_entry_t intel_ppro_pe[]={ { .name = "CPU_CLK_UNHALTED", .desc = "Number cycles during which the processor is not halted", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x79, }, { .name = "INST_RETIRED", .desc = "Number of instructions retired", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xc0, }, { .name = "DATA_MEM_REFS", .desc = "All loads from any memory type. All stores to any memory typeEach part of a split is counted separately. The internal logic counts not only memory loads and stores but also internal retries. 80-bit floating point accesses are double counted, since they are decomposed into a 16-bit exponent load and a 64-bit mantissa load. Memory accesses are only counted when they are actually performed (such as a load that gets squashed because a previous cache miss is outstanding to the same address, and which finally gets performed, is only counted once). Does not include I/O accesses or other non-memory accesses", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x43, }, { .name = "DCU_LINES_IN", .desc = "Total lines allocated in the DCU", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x45, }, { .name = "DCU_M_LINES_IN", .desc = "Number of M state lines allocated in the DCU", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x46, }, { .name = "DCU_M_LINES_OUT", .desc = "Number of M state lines evicted from the DCU. This includes evictions via snoop HITM, intervention or replacement", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x47, }, { .name = "DCU_MISS_OUTSTANDING", .desc = "Weighted number of cycle while a DCU miss is outstanding, incremented by the number of cache misses at any particular time. Cacheable read requests only are considered. Uncacheable requests are excluded Read-for-ownerships are counted, as well as line fills, invalidates, and stores", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x48, }, { .name = "IFU_IFETCH", .desc = "Number of instruction fetches, both cacheable and noncacheable including UC fetches", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x80, }, { .name = "IFU_IFETCH_MISS", .desc = "Number of instruction fetch misses. All instructions fetches that do not hit the IFU (i.e., that produce memory requests). Includes UC accesses", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x81, }, { .name = "ITLB_MISS", .desc = "Number of ITLB misses", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x85, }, { .name = "IFU_MEM_STALL", .desc = "Number of cycles instruction fetch is stalled for any reason. Includes IFU cache misses, ITLB misses, ITLB faults, and other minor stalls", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x86, }, { .name = "ILD_STALL", .desc = "Number of cycles that the instruction length decoder is stalled", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x87, }, { .name = "L2_IFETCH", .desc = "Number of L2 instruction fetches. This event indicates that a normal instruction fetch was received by the L2. The count includes only L2 cacheable instruction fetches: it does not include UC instruction fetches It does not include ITLB miss accesses", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x28, .numasks = LIBPFM_ARRAY_SIZE(ppro_l2_ifetch), .ngrp = 1, .umasks = ppro_l2_ifetch, }, { .name = "L2_ST", .desc = "Number of L2 data stores. This event indicates that a normal, unlocked, store memory access was received by the L2. Specifically, it indicates that the DCU sent a read-for ownership request to the L2. It also includes Invalid to Modified requests sent by the DCU to the L2. It includes only L2 cacheable memory accesses; it does not include I/O accesses, other non-memory accesses, or memory accesses such as UC/WT memory accesses. It does include L2 cacheable TLB miss memory accesses", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x2a, .numasks = LIBPFM_ARRAY_SIZE(ppro_l2_ifetch), .ngrp = 1, .umasks = ppro_l2_ifetch, /* identical to actual umasks list for this event */ }, { .name = "L2_M_LINES_INM", .desc = "Number of modified lines allocated in the L2", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x25, }, { .name = "L2_RQSTS", .desc = "Total number of L2 requests", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x2e, .numasks = LIBPFM_ARRAY_SIZE(ppro_l2_ifetch), .ngrp = 1, .umasks = ppro_l2_ifetch, /* identical to actual umasks list for this event */ }, { .name = "L2_ADS", .desc = "Number of L2 address strobes", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x21, }, { .name = "L2_DBUS_BUSY", .desc = "Number of cycles during which the L2 cache data bus was busy", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x22, }, { .name = "L2_DBUS_BUSY_RD", .desc = "Number of cycles during which the data bus was busy transferring read data from L2 to the processor", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x23, }, { .name = "BUS_DRDY_CLOCKS", .desc = "Number of clocks during which DRDY# is asserted. Utilization of the external system data bus during data transfers", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x62, .numasks = LIBPFM_ARRAY_SIZE(ppro_bus_drdy_clocks), .ngrp = 1, .umasks = ppro_bus_drdy_clocks, }, { .name = "BUS_LOCK_CLOCKS", .desc = "Number of clocks during which LOCK# is asserted on the external system bus", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x63, .numasks = LIBPFM_ARRAY_SIZE(ppro_bus_drdy_clocks), .ngrp = 1, .umasks = ppro_bus_drdy_clocks, /* identical to actual umasks list for this event */ }, { .name = "BUS_REQ_OUTSTANDING", .desc = "Number of bus requests outstanding. This counter is incremented by the number of cacheable read bus requests outstanding in any given cycle", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x60, }, { .name = "BUS_TRANS_BRD", .desc = "Number of burst read transactions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x65, .numasks = LIBPFM_ARRAY_SIZE(ppro_bus_drdy_clocks), .ngrp = 1, .umasks = ppro_bus_drdy_clocks, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRANS_RFO", .desc = "Number of completed read for ownership transactions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x66, .numasks = LIBPFM_ARRAY_SIZE(ppro_bus_drdy_clocks), .ngrp = 1, .umasks = ppro_bus_drdy_clocks, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRANS_WB", .desc = "Number of completed write back transactions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x67, .numasks = LIBPFM_ARRAY_SIZE(ppro_bus_drdy_clocks), .ngrp = 1, .umasks = ppro_bus_drdy_clocks, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRAN_IFETCH", .desc = "Number of completed instruction fetch transactions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x68, .numasks = LIBPFM_ARRAY_SIZE(ppro_bus_drdy_clocks), .ngrp = 1, .umasks = ppro_bus_drdy_clocks, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRAN_INVAL", .desc = "Number of completed invalidate transactions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x69, .numasks = LIBPFM_ARRAY_SIZE(ppro_bus_drdy_clocks), .ngrp = 1, .umasks = ppro_bus_drdy_clocks, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRAN_PWR", .desc = "Number of completed partial write transactions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x6a, .numasks = LIBPFM_ARRAY_SIZE(ppro_bus_drdy_clocks), .ngrp = 1, .umasks = ppro_bus_drdy_clocks, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRANS_P", .desc = "Number of completed partial transactions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x6b, .numasks = LIBPFM_ARRAY_SIZE(ppro_bus_drdy_clocks), .ngrp = 1, .umasks = ppro_bus_drdy_clocks, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRANS_IO", .desc = "Number of completed I/O transactions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x6c, .numasks = LIBPFM_ARRAY_SIZE(ppro_bus_drdy_clocks), .ngrp = 1, .umasks = ppro_bus_drdy_clocks, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRAN_DEF", .desc = "Number of completed deferred transactions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x6d, .numasks = LIBPFM_ARRAY_SIZE(ppro_bus_drdy_clocks), .ngrp = 1, .umasks = ppro_bus_drdy_clocks, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRAN_BURST", .desc = "Number of completed burst transactions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x6e, .numasks = LIBPFM_ARRAY_SIZE(ppro_bus_drdy_clocks), .ngrp = 1, .umasks = ppro_bus_drdy_clocks, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRAN_ANY", .desc = "Number of all completed bus transactions. Address bus utilization can be calculated knowing the minimum address bus occupancy. Includes special cycles, etc.", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x70, .numasks = LIBPFM_ARRAY_SIZE(ppro_bus_drdy_clocks), .ngrp = 1, .umasks = ppro_bus_drdy_clocks, /* identical to actual umasks list for this event */ }, { .name = "BUS_TRAN_MEM", .desc = "Number of completed memory transactions", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x6f, .numasks = LIBPFM_ARRAY_SIZE(ppro_bus_drdy_clocks), .ngrp = 1, .umasks = ppro_bus_drdy_clocks, /* identical to actual umasks list for this event */ }, { .name = "BUS_DATA_RECV", .desc = "Number of bus clock cycles during which this processor is receiving data", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x64, }, { .name = "BUS_BNR_DRV", .desc = "Number of bus clock cycles during which this processor is driving the BNR# pin", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x61, }, { .name = "BUS_HIT_DRV", .desc = "Number of bus clock cycles during which this processor is driving the HIT# pin", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x7a, }, { .name = "BUS_HITM_DRV", .desc = "Number of bus clock cycles during which this processor is driving the HITM# pin", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x7b, }, { .name = "BUS_SNOOP_STALL", .desc = "Number of clock cycles during which the bus is snoop stalled", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x7e, }, { .name = "FLOPS", .desc = "Number of computational floating-point operations retired. Excludes floating-point computational operations that cause traps or assists. Includes internal sub-operations for complex floating-point instructions like transcendentals. Excludes floating point loads and stores", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x1, .code = 0xc1, }, { .name = "FP_COMP_OPS_EXE", .desc = "Number of computational floating-point operations executed. The number of FADD, FSUB, FCOM, FMULs, integer MULs and IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This number does not include the number of cycles, but the number of operations. This event does not distinguish an FADD used in the middle of a transcendental flow from a separate FADD instruction", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x1, .code = 0x10, }, { .name = "FP_ASSIST", .desc = "Number of floating-point exception cases handled by microcode.", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x2, .code = 0x11, }, { .name = "MUL", .desc = "Number of multiplies.This count includes integer as well as FP multiplies and is speculative", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x2, .code = 0x12, }, { .name = "DIV", .desc = "Number of divides.This count includes integer as well as FP divides and is speculative", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x2, .code = 0x13, }, { .name = "CYCLES_DIV_BUSY", .desc = "Number of cycles during which the divider is busy, and cannot accept new divides. This includes integer and FP divides, FPREM, FPSQRT, etc. and is speculative", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x1, .code = 0x14, }, { .name = "LD_BLOCKS", .desc = "Number of load operations delayed due to store buffer blocks. Includes counts caused by preceding stores whose addresses are unknown, preceding stores whose addresses are known but whose data is unknown, and preceding stores that conflicts with the load but which incompletely overlap the load", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x3, }, { .name = "SB_DRAINS", .desc = "Number of store buffer drain cycles. Incremented every cycle the store buffer is draining. Draining is caused by serializing operations like CPUID, synchronizing operations like XCHG, interrupt acknowledgment, as well as other conditions (such as cache flushing).", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x4, }, { .name = "MISALIGN_MEM_REF", .desc = "Number of misaligned data memory references. Incremented by 1 every cycle during which, either the processor's load or store pipeline dispatches a misaligned micro-op Counting is performed if it is the first or second half or if it is blocked, squashed, or missed. In this context, misaligned means crossing a 64-bit boundary", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x5, }, { .name = "UOPS_RETIRED", .desc = "Number of micro-ops retired", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xc2, }, { .name = "INST_DECODED", .desc = "Number of instructions decoded", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xd0, }, { .name = "HW_INT_RX", .desc = "Number of hardware interrupts received", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xc8, }, { .name = "CYCLES_INT_MASKED", .desc = "Number of processor cycles for which interrupts are disabled", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xc6, }, { .name = "CYCLES_INT_PENDING_AND_MASKED", .desc = "Number of processor cycles for which interrupts are disabled and interrupts are pending.", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xc7, }, { .name = "BR_INST_RETIRED", .desc = "Number of branch instructions retired", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xc4, }, { .name = "BR_MISS_PRED_RETIRED", .desc = "Number of mispredicted branches retired", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xc5, }, { .name = "BR_TAKEN_RETIRED", .desc = "Number of taken branches retired", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xc9, }, { .name = "BR_MISS_PRED_TAKEN_RET", .desc = "Number of taken mispredicted branches retired", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xca, }, { .name = "BR_INST_DECODED", .desc = "Number of branch instructions decoded", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xe0, }, { .name = "BTB_MISSES", .desc = "Number of branches for which the BTB did not produce a prediction", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xe2, }, { .name = "BR_BOGUS", .desc = "Number of bogus branches", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xe4, }, { .name = "BACLEARS", .desc = "Number of times BACLEAR is asserted. This is the number of times that a static branch prediction was made, in which the branch decoder decided to make a branch prediction because the BTB did not", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xe6, }, { .name = "RESOURCE_STALLS", .desc = "Incremented by 1 during every cycle for which there is a resource related stall. Includes register renaming buffer entries, memory buffer entries. Does not include stalls due to bus queue full, too many cache misses, etc. In addition to resource related stalls, this event counts some other events. Includes stalls arising during branch misprediction recovery, such as if retirement of the mispredicted branch is delayed and stalls arising while store buffer is draining from synchronizing operations", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xa2, }, { .name = "PARTIAL_RAT_STALLS", .desc = "Number of cycles or events for partial stalls. This includes flag partial stalls", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0xd2, }, { .name = "SEGMENT_REG_LOADS", .desc = "Number of segment register loads.", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x6, }, { .name = "L2_LD", .desc = "Number of L2 data loads. This event indicates that a normal, unlocked, load memory access was received by the L2. It includes only L2 cacheable memory accesses; it does not include I/O accesses, other non-memory accesses, or memory accesses such as UC/WT memory accesses. It does include L2 cacheable TLB miss memory accesses", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x29, .numasks = LIBPFM_ARRAY_SIZE(ppro_l2_ifetch), .ngrp = 1, .umasks = ppro_l2_ifetch, /* identical to actual umasks list for this event */ }, { .name = "L2_LINES_IN", .desc = "Number of lines allocated in the L2", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x24, }, { .name = "L2_LINES_OUT", .desc = "Number of lines removed from the L2 for any reason", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x26, }, { .name = "L2_M_LINES_OUTM", .desc = "Number of modified lines removed from the L2 for any reason", .modmsk = INTEL_X86_ATTRS, .cntmsk = 0x3, .code = 0x27, }, }; libpfm-4.9.0/lib/events/arm_cortex_a53_events.h0000664000175000017500000001215613223402656021245 0ustar eranianeranian/* * Copyright (c) 2014 Google Inc. All rights reserved * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * Cortex A53 r0p2 * based on Table 12.9 from the "Cortex A53 Technical Reference Manual" */ static const arm_entry_t arm_cortex_a53_pe[]={ {.name = "SW_INCR", .modmsk = ARMV8_ATTRS, .code = 0x00, .desc = "Instruction architecturally executed (condition check pass) Software increment" }, {.name = "L1I_CACHE_REFILL", .modmsk = ARMV8_ATTRS, .code = 0x01, .desc = "Level 1 instruction cache refill" }, {.name = "L1I_TLB_REFILL", .modmsk = ARMV8_ATTRS, .code = 0x02, .desc = "Level 1 instruction TLB refill" }, {.name = "L1D_CACHE_REFILL", .modmsk = ARMV8_ATTRS, .code = 0x03, .desc = "Level 1 data cache refill" }, {.name = "L1D_CACHE_ACCESS", .modmsk = ARMV8_ATTRS, .code = 0x04, .desc = "Level 1 data cache access" }, {.name = "L1D_TLB_REFILL", .modmsk = ARMV8_ATTRS, .code = 0x05, .desc = "Level 1 data TLB refill" }, {.name = "LD_RETIRED", .modmsk = ARMV8_ATTRS, .code = 0x06, .desc = "Load Instruction architecturally executed, condition check", }, {.name = "ST_RETIRED", .modmsk = ARMV8_ATTRS, .code = 0x07, .desc = "Store Instruction architecturally executed, condition check", }, {.name = "INST_RETIRED", .modmsk = ARMV8_ATTRS, .code = 0x08, .desc = "Instruction architecturally executed" }, {.name = "EXCEPTION_TAKEN", .modmsk = ARMV8_ATTRS, .code = 0x09, .desc = "Exception taken" }, {.name = "EXCEPTION_RETURN", .modmsk = ARMV8_ATTRS, .code = 0x0a, .desc = "Instruction architecturally executed (condition check pass) Exception return" }, {.name = "CID_WRITE_RETIRED", .modmsk = ARMV8_ATTRS, .code = 0x0b, .desc = "Change to Context ID retired", }, {.name = "PC_WRITE_RETIRED", .modmsk = ARMV8_ATTRS, .code = 0x0c, .desc = "Write to CONTEXTIDR, instruction architecturally executed, condition check pass" }, {.name = "BR_IMMED_RETIRED", .modmsk = ARMV8_ATTRS, .code = 0x0d, .desc = "Software change of the PC, instruction architecturally executed, condition check pass" }, {.name = "UNALIGNED_LDST_RETIRED", .modmsk = ARMV8_ATTRS, .code = 0x0f, .desc = "Procedure return, instruction architecturally executed, condition check pass" }, {.name = "BRANCH_MISPRED", .modmsk = ARMV8_ATTRS, .code = 0x10, .desc = "Mispredicted or not predicted branch speculatively executed" }, {.name = "CPU_CYCLES", .modmsk = ARMV8_ATTRS, .code = 0x11, .desc = "Cycles" }, {.name = "BRANCH_PRED", .modmsk = ARMV8_ATTRS, .code = 0x12, .desc = "Predictable branch speculatively executed" }, {.name = "DATA_MEM_ACCESS", .modmsk = ARMV8_ATTRS, .code = 0x13, .desc = "Data memory access" }, {.name = "L1I_CACHE_ACCESS", .modmsk = ARMV8_ATTRS, .code = 0x14, .desc = "Level 1 instruction cache access" }, {.name = "L1D_CACHE_WB", .modmsk = ARMV8_ATTRS, .code = 0x15, .desc = "Level 1 data cache WriteBack" }, {.name = "L2D_CACHE_ACCESS", .modmsk = ARMV8_ATTRS, .code = 0x16, .desc = "Level 2 data cache access" }, {.name = "L2D_CACHE_REFILL", .modmsk = ARMV8_ATTRS, .code = 0x17, .desc = "Level 2 data cache refill" }, {.name = "L2D_CACHE_WB", .modmsk = ARMV8_ATTRS, .code = 0x18, .desc = "Level 2 data cache WriteBack" }, {.name = "BUS_ACCESS", .modmsk = ARMV8_ATTRS, .code = 0x19, .desc = "Bus access" }, {.name = "LOCAL_MEMORY_ERROR", .modmsk = ARMV8_ATTRS, .code = 0x1a, .desc = "Local memory error" }, {.name = "BUS_CYCLES", .modmsk = ARMV8_ATTRS, .code = 0x1d, .desc = "Bus cycle" }, {.name = "BUS_READ_ACCESS", .modmsk = ARMV8_ATTRS, .code = 0x60, .desc = "Bus read access" }, {.name = "BUS_WRITE_ACCESS", .modmsk = ARMV8_ATTRS, .code = 0x61, .desc = "Bus write access" }, {.name = "BRANCH_SPEC_EXEC_IND", .modmsk = ARMV8_ATTRS, .code = 0x7a, .desc = "Indirect branch speculatively executed" }, {.name = "EXCEPTION_IRQ", .modmsk = ARMV8_ATTRS, .code = 0x86, .desc = "Exception taken, irq" }, {.name = "EXCEPTION_FIQ", .modmsk = ARMV8_ATTRS, .code = 0x87, .desc = "Exception taken, irq" }, }; libpfm-4.9.0/lib/pfmlib_intel_snbep_unc_cbo.c0000664000175000017500000000707413223402656021063 0ustar eranianeranian/* * pfmlib_intel_snb_unc_cbo.c : Intel SandyBridge-EP C-Box uncore PMU * * Copyright (c) 2012 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_intel_x86_priv.h" #include "pfmlib_intel_snbep_unc_priv.h" #include "events/intel_snbep_unc_cbo_events.h" static void display_cbo(void *this, pfmlib_event_desc_t *e, void *val) { const intel_x86_entry_t *pe = this_pe(this); pfm_snbep_unc_reg_t *reg = val; pfm_snbep_unc_reg_t f; __pfm_vbprintf("[UNC_CBO=0x%"PRIx64" event=0x%x umask=0x%x en=%d " "inv=%d edge=%d thres=%d tid_en=%d] %s\n", reg->val, reg->cbo.unc_event, reg->cbo.unc_umask, reg->cbo.unc_en, reg->cbo.unc_inv, reg->cbo.unc_edge, reg->cbo.unc_thres, reg->cbo.unc_tid, pe[e->event].name); if (e->count == 1) return; f.val = e->codes[1]; __pfm_vbprintf("[UNC_CBOX_FILTER=0x%"PRIx64" tid=%d core=0x%x nid=0x%x" " state=0x%x opc=0x%x]\n", f.val, f.cbo_filt.tid, f.cbo_filt.cid, f.cbo_filt.nid, f.cbo_filt.state, f.cbo_filt.opc); } #define DEFINE_C_BOX(n) \ pfmlib_pmu_t intel_snbep_unc_cb##n##_support = {\ .desc = "Intel Sandy Bridge-EP C-Box "#n" uncore",\ .name = "snbep_unc_cbo"#n,\ .perf_name = "uncore_cbox_"#n,\ .pmu = PFM_PMU_INTEL_SNBEP_UNC_CB##n,\ .pme_count = LIBPFM_ARRAY_SIZE(intel_snbep_unc_c_pe),\ .type = PFM_PMU_TYPE_UNCORE,\ .num_cntrs = 4,\ .num_fixed_cntrs = 0,\ .max_encoding = 2,\ .pe = intel_snbep_unc_c_pe,\ .atdesc = snbep_unc_mods,\ .flags = PFMLIB_PMU_FL_RAW_UMASK\ | PFMLIB_PMU_FL_NO_SMPL,\ .pmu_detect = pfm_intel_snbep_unc_detect,\ .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding,\ PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding),\ .get_event_first = pfm_intel_x86_get_event_first,\ .get_event_next = pfm_intel_x86_get_event_next,\ .event_is_valid = pfm_intel_x86_event_is_valid,\ .validate_table = pfm_intel_x86_validate_table,\ .get_event_info = pfm_intel_x86_get_event_info,\ .get_event_attr_info = pfm_intel_snbep_unc_get_event_attr_info,\ PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs),\ .get_event_nattrs = pfm_intel_x86_get_event_nattrs,\ .can_auto_encode = pfm_intel_x86_can_auto_encode, \ .display_reg = display_cbo,\ } DEFINE_C_BOX(0); DEFINE_C_BOX(1); DEFINE_C_BOX(2); DEFINE_C_BOX(3); DEFINE_C_BOX(4); DEFINE_C_BOX(5); DEFINE_C_BOX(6); DEFINE_C_BOX(7); libpfm-4.9.0/lib/pfmlib_sparc_ultra4.c0000664000175000017500000000424713223402656017473 0ustar eranianeranian/* * pfmlib_sparc_ultra4.c : SPARC Ultra 4+ * * Copyright (c) 2011 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_sparc_priv.h" #include "events/sparc_ultra4plus_events.h" pfmlib_pmu_t sparc_ultra4plus_support={ .desc = "Ultra Sparc 4+", .name = "ultra4p", .pmu = PFM_PMU_SPARC_ULTRA4PLUS, .pme_count = LIBPFM_ARRAY_SIZE(ultra4plus_pe), .type = PFM_PMU_TYPE_CORE, .supported_plm = SPARC_PLM, .max_encoding = 2, .num_cntrs = 2, .pe = ultra4plus_pe, .atdesc = NULL, .flags = 0, .pmu_detect = pfm_sparc_detect, .get_event_encoding[PFM_OS_NONE] = pfm_sparc_get_encoding, PFMLIB_ENCODE_PERF(pfm_sparc_get_perf_encoding), .get_event_first = pfm_sparc_get_event_first, .get_event_next = pfm_sparc_get_event_next, .event_is_valid = pfm_sparc_event_is_valid, .validate_table = pfm_sparc_validate_table, .get_event_info = pfm_sparc_get_event_info, .get_event_attr_info = pfm_sparc_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_sparc_perf_validate_pattrs), .get_event_nattrs = pfm_sparc_get_event_nattrs, }; libpfm-4.9.0/lib/pfmlib_intel_hswep_unc_r2pcie.c0000664000175000017500000000604013223402656021513 0ustar eranianeranian/* * pfmlib_intel_hswep_r2pcie.c : Intel Haswell-EP R2PCIe uncore PMU * * Copyright (c) 2014 Google Inc. All rights reserved * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_intel_x86_priv.h" #include "pfmlib_intel_snbep_unc_priv.h" #include "events/intel_hswep_unc_r2pcie_events.h" static void display_r2(void *this, pfmlib_event_desc_t *e, void *val) { const intel_x86_entry_t *pe = this_pe(this); pfm_snbep_unc_reg_t *reg = val; __pfm_vbprintf("[UNC_R2PCIE=0x%"PRIx64" event=0x%x umask=0x%x en=%d " "inv=%d edge=%d thres=%d] %s\n", reg->val, reg->com.unc_event, reg->com.unc_umask, reg->com.unc_en, reg->com.unc_inv, reg->com.unc_edge, reg->com.unc_thres, pe[e->event].name); } pfmlib_pmu_t intel_hswep_unc_r2pcie_support = { .desc = "Intel Haswell-EP R2PCIe uncore", .name = "hswep_unc_r2pcie", .perf_name = "uncore_r2pcie", .pmu = PFM_PMU_INTEL_HSWEP_UNC_R2PCIE, .pme_count = LIBPFM_ARRAY_SIZE(intel_hswep_unc_r2_pe), .type = PFM_PMU_TYPE_UNCORE, .num_cntrs = 4, .num_fixed_cntrs = 0, .max_encoding = 1, .pe = intel_hswep_unc_r2_pe, .atdesc = snbep_unc_mods, .flags = PFMLIB_PMU_FL_RAW_UMASK, .pmu_detect = pfm_intel_hswep_unc_detect, .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding, PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding), PFMLIB_OS_DETECT(pfm_intel_x86_perf_detect), .get_event_first = pfm_intel_x86_get_event_first, .get_event_next = pfm_intel_x86_get_event_next, .event_is_valid = pfm_intel_x86_event_is_valid, .validate_table = pfm_intel_x86_validate_table, .get_event_info = pfm_intel_x86_get_event_info, .get_event_attr_info = pfm_intel_x86_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs), .get_event_nattrs = pfm_intel_x86_get_event_nattrs, .display_reg = display_r2, }; libpfm-4.9.0/lib/pfmlib_sparc_priv.h0000664000175000017500000000327213223402656017242 0ustar eranianeranian#ifndef __PFMLIB_SPARC_PRIV_H__ #define __PFMLIB_SPARC_PRIV_H__ typedef struct { char *uname; /* mask name */ char *udesc; /* mask description */ int ubit; /* umask bit position */ } sparc_mask_t; #define EVENT_MASK_BITS 8 typedef struct { char *name; /* event name */ char *desc; /* event description */ char ctrl; /* S0 or S1 */ char __pad; int code; /* S0/S1 encoding */ int numasks; /* number of entries in masks */ sparc_mask_t umasks[EVENT_MASK_BITS]; } sparc_entry_t; typedef union { unsigned int val; struct { unsigned int ctrl_s0 : 1; unsigned int ctrl_s1 : 1; unsigned int reserved1 : 14; unsigned int code : 8; unsigned int umask : 8; } config; } pfm_sparc_reg_t; #define PME_CTRL_S0 1 #define PME_CTRL_S1 2 #define SPARC_ATTR_K 0 #define SPARC_ATTR_U 1 #define SPARC_ATTR_H 2 #define SPARC_PLM (PFM_PLM0|PFM_PLM3) #define NIAGARA2_PLM (SPARC_PLM|PFM_PLMH) extern int pfm_sparc_detect(void *this); extern int pfm_sparc_get_encoding(void *this, pfmlib_event_desc_t *e); extern int pfm_sparc_get_event_first(void *this); extern int pfm_sparc_get_event_next(void *this, int idx); extern int pfm_sparc_event_is_valid(void *this, int pidx); extern int pfm_sparc_validate_table(void *this, FILE *fp); extern int pfm_sparc_get_event_attr_info(void *this, int pidx, int attr_idx, pfmlib_event_attr_info_t *info); extern int pfm_sparc_get_event_info(void *this, int idx, pfm_event_info_t *info); extern unsigned int pfm_sparc_get_event_nattrs(void *this, int pidx); extern void pfm_sparc_perf_validate_pattrs(void *this, pfmlib_event_desc_t *e); extern int pfm_sparc_get_perf_encoding(void *this, pfmlib_event_desc_t *e); #endif /* __PFMLIB_SPARC_PRIV_H__ */ libpfm-4.9.0/lib/pfmlib_perf_event.c0000664000175000017500000002671413223402656017230 0ustar eranianeranian/* * pfmlib_perf_events.c: encode events for perf_event API * * Copyright (c) 2009 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include #include #include "pfmlib_priv.h" #include "pfmlib_perf_event_priv.h" #define PERF_PROC_FILE "/proc/sys/kernel/perf_event_paranoid" #ifdef min #undef min #endif #define min(a, b) ((a) < (b) ? (a) : (b)) /* * contains ONLY attributes related to PMU features */ static const pfmlib_attr_desc_t perf_event_mods[]={ PFM_ATTR_B("u", "monitor at user level"), /* monitor user level */ PFM_ATTR_B("k", "monitor at kernel level"), /* monitor kernel level */ PFM_ATTR_B("h", "monitor at hypervisor level"), /* monitor hypervisor level */ PFM_ATTR_SKIP, PFM_ATTR_SKIP, PFM_ATTR_SKIP, PFM_ATTR_SKIP, PFM_ATTR_B("mg", "monitor guest execution"), /* monitor guest level */ PFM_ATTR_B("mh", "monitor host execution"), /* monitor host level */ PFM_ATTR_NULL /* end-marker to avoid exporting number of entries */ }; /* * contains all attributes controlled by perf_events. That includes PMU attributes * and pure software attributes such as sampling periods */ static const pfmlib_attr_desc_t perf_event_ext_mods[]={ PFM_ATTR_B("u", "monitor at user level"), /* monitor user level */ PFM_ATTR_B("k", "monitor at kernel level"), /* monitor kernel level */ PFM_ATTR_B("h", "monitor at hypervisor level"), /* monitor hypervisor level */ PFM_ATTR_I("period", "sampling period"), /* sampling period */ PFM_ATTR_I("freq", "sampling frequency (Hz)"), /* sampling frequency */ PFM_ATTR_I("precise", "precise ip"), /* anti-skid mechanism */ PFM_ATTR_B("excl", "exclusive access"), /* exclusive PMU access */ PFM_ATTR_B("mg", "monitor guest execution"), /* monitor guest level */ PFM_ATTR_B("mh", "monitor host execution"), /* monitor host level */ PFM_ATTR_I("cpu", "CPU to program"), /* CPU to program */ PFM_ATTR_B("pinned", "pin event to counters"), /* pin event to PMU */ PFM_ATTR_NULL /* end-marker to avoid exporting number of entries */ }; static int pfmlib_perf_event_encode(void *this, const char *str, int dfl_plm, void *data) { pfm_perf_encode_arg_t arg; pfm_perf_encode_arg_t *uarg = data; pfmlib_os_t *os = this; struct perf_event_attr my_attr, *attr; pfmlib_pmu_t *pmu; pfmlib_event_desc_t e; pfmlib_event_attr_info_t *a; size_t orig_sz, asz, sz = sizeof(arg); uint64_t ival; int has_plm = 0, has_vmx_plm = 0; int i, plm = 0, ret, vmx_plm = 0; int cpu = -1, pinned = 0; sz = pfmlib_check_struct(uarg, uarg->size, PFM_PERF_ENCODE_ABI0, sz); if (!sz) return PFM_ERR_INVAL; /* copy input */ memcpy(&arg, uarg, sz); /* pointer to our internal attr struct */ memset(&my_attr, 0, sizeof(my_attr)); attr = &my_attr; /* * copy user attr to our internal version * size == 0 is interpreted minimal possible * size (ABI_VER0) */ /* size of attr struct passed by user */ orig_sz = uarg->attr->size; if (orig_sz == 0) asz = PERF_ATTR_SIZE_VER0; else asz = min(sizeof(*attr), orig_sz); /* * we copy the user struct to preserve whatever may * have been initialized but that we do not use */ memcpy(attr, uarg->attr, asz); /* restore internal size (just in case we need it) */ attr->size = sizeof(my_attr); /* useful for debugging */ if (asz != sizeof(*attr)) __pfm_vbprintf("warning: mismatch attr struct size " "user=%d libpfm=%zu\n", asz, sizeof(*attr)); memset(&e, 0, sizeof(e)); e.osid = os->id; e.os_data = attr; e.dfl_plm = dfl_plm; /* after this call, need to call pfmlib_release_event() */ ret = pfmlib_parse_event(str, &e); if (ret != PFM_SUCCESS) return ret; pmu = e.pmu; ret = PFM_ERR_NOTSUPP; if (!pmu->get_event_encoding[e.osid]) { DPRINT("PMU %s does not support PFM_OS_NONE\n", pmu->name); goto done; } ret = pmu->get_event_encoding[e.osid](pmu, &e); if (ret != PFM_SUCCESS) goto done; /* * process perf_event attributes */ for (i = 0; i < e.nattrs; i++) { a = attr(&e, i); if (a->ctrl != PFM_ATTR_CTRL_PERF_EVENT) continue; ival = e.attrs[i].ival; switch(a->idx) { case PERF_ATTR_U: if (ival) plm |= PFM_PLM3; has_plm = 1; break; case PERF_ATTR_K: if (ival) plm |= PFM_PLM0; has_plm = 1; break; case PERF_ATTR_H: if (ival) plm |= PFM_PLMH; has_plm = 1; break; case PERF_ATTR_PE: if (!ival || attr->freq) { ret = PFM_ERR_ATTR_VAL; goto done; } attr->sample_period = ival; break; case PERF_ATTR_FR: if (!ival || attr->sample_period) { ret = PFM_ERR_ATTR_VAL; goto done; } attr->sample_freq = ival; attr->freq = 1; break; case PERF_ATTR_PR: if (ival > 3) { ret = PFM_ERR_ATTR_VAL; goto done; } attr->precise_ip = ival; break; case PERF_ATTR_EX: if (ival && !attr->exclusive) attr->exclusive = 1; break; case PERF_ATTR_MG: vmx_plm |= PFM_PLM3; has_vmx_plm = 1; break; case PERF_ATTR_MH: vmx_plm |= PFM_PLM0; has_vmx_plm = 1; break; case PERF_ATTR_CPU: if (ival >= INT_MAX) { ret = PFM_ERR_ATTR_VAL; goto done; } cpu = (int)ival; break; case PERF_ATTR_PIN: pinned = (int)!!ival; break; } } /* * if no priv level mask was provided * with the event, then use dfl_plm */ if (!has_plm) plm = dfl_plm; /* exclude_guest by default */ if (!has_vmx_plm) vmx_plm = PFM_PLM0; /* * perf_event plm work by exclusion, so use logical or * goal here is to set to zero any exclude_* not supported * by underlying PMU */ plm |= (~pmu->supported_plm) & PFM_PLM_ALL; vmx_plm |= (~pmu->supported_plm) & PFM_PLM_ALL; attr->exclude_user = !(plm & PFM_PLM3); attr->exclude_kernel = !(plm & PFM_PLM0); attr->exclude_hv = !(plm & PFM_PLMH); attr->exclude_guest = !(vmx_plm & PFM_PLM3); attr->exclude_host = !(vmx_plm & PFM_PLM0); attr->pinned = pinned; __pfm_vbprintf("PERF[type=%x config=0x%"PRIx64" config1=0x%"PRIx64 " excl=%d e_u=%d e_k=%d e_hv=%d e_host=%d e_gu=%d period=%"PRIu64" freq=%d" " precise=%d pinned=%d] %s\n", attr->type, attr->config, attr->config1, attr->exclusive, attr->exclude_user, attr->exclude_kernel, attr->exclude_hv, attr->exclude_host, attr->exclude_guest, attr->sample_period, attr->freq, attr->precise_ip, attr->pinned, str); /* * propagate event index if necessary */ arg.idx = pfmlib_pidx2idx(e.pmu, e.event); /* propagate cpu */ arg.cpu = cpu; /* propagate our changes, that overwrites attr->size */ memcpy(uarg->attr, attr, asz); /* restore user size */ uarg->attr->size = orig_sz; /* * fstr not requested, stop here */ ret = PFM_SUCCESS; if (!arg.fstr) { memcpy(uarg, &arg, sz); goto done; } for (i=0; i < e.npattrs; i++) { int idx; if (e.pattrs[i].ctrl != PFM_ATTR_CTRL_PERF_EVENT) continue; idx = e.pattrs[i].idx; switch (idx) { case PERF_ATTR_K: evt_strcat(e.fstr, ":%s=%lu", perf_event_ext_mods[idx].name, !!(plm & PFM_PLM0)); break; case PERF_ATTR_U: evt_strcat(e.fstr, ":%s=%lu", perf_event_ext_mods[idx].name, !!(plm & PFM_PLM3)); break; case PERF_ATTR_H: evt_strcat(e.fstr, ":%s=%lu", perf_event_ext_mods[idx].name, !!(plm & PFM_PLMH)); break; case PERF_ATTR_PR: evt_strcat(e.fstr, ":%s=%d", perf_event_ext_mods[idx].name, attr->precise_ip); break; case PERF_ATTR_PE: case PERF_ATTR_FR: if (attr->freq && attr->sample_period) evt_strcat(e.fstr, ":%s=%"PRIu64, perf_event_ext_mods[idx].name, attr->sample_period); else if (attr->sample_period) evt_strcat(e.fstr, ":%s=%"PRIu64, perf_event_ext_mods[idx].name, attr->sample_period); break; case PERF_ATTR_MG: evt_strcat(e.fstr, ":%s=%lu", perf_event_ext_mods[idx].name, !attr->exclude_guest); break; case PERF_ATTR_MH: evt_strcat(e.fstr, ":%s=%lu", perf_event_ext_mods[idx].name, !attr->exclude_host); break; case PERF_ATTR_EX: evt_strcat(e.fstr, ":%s=%lu", perf_event_ext_mods[idx].name, attr->exclusive); break; } } ret = pfmlib_build_fstr(&e, arg.fstr); if (ret == PFM_SUCCESS) memcpy(uarg, &arg, sz); done: pfmlib_release_event(&e); return ret; } /* * get OS-specific event attributes */ static int perf_get_os_nattrs(void *this, pfmlib_event_desc_t *e) { pfmlib_os_t *os = this; int i, n = 0; for (i = 0; os->atdesc[i].name; i++) if (!is_empty_attr(os->atdesc+i)) n++; return n; } static int perf_get_os_attr_info(void *this, pfmlib_event_desc_t *e) { pfmlib_os_t *os = this; pfmlib_event_attr_info_t *info; int i, k, j = e->npattrs; for (i = k = 0; os->atdesc[i].name; i++) { /* skip padding entries */ if (is_empty_attr(os->atdesc+i)) continue; info = e->pattrs + j + k; info->name = os->atdesc[i].name; info->desc = os->atdesc[i].desc; info->equiv= NULL; info->code = i; info->idx = i; /* namespace-specific index */ info->type = os->atdesc[i].type; info->is_dfl = 0; info->ctrl = PFM_ATTR_CTRL_PERF_EVENT; k++; } e->npattrs += k; return PFM_SUCCESS; } /* * old interface, maintained for backward compatibility with earlier versions of the library */ int pfm_get_perf_event_encoding(const char *str, int dfl_plm, struct perf_event_attr *attr, char **fstr, int *idx) { pfm_perf_encode_arg_t arg; int ret; if (PFMLIB_INITIALIZED() == 0) return PFM_ERR_NOINIT; /* idx and fstr can be NULL */ if (!(attr && str)) return PFM_ERR_INVAL; if (dfl_plm & ~(PFM_PLM_ALL)) return PFM_ERR_INVAL; memset(&arg, 0, sizeof(arg)); /* do not clear attr, some fields may be initialized by caller already, e.g., size */ arg.attr = attr; arg.fstr = fstr; ret = pfm_get_os_event_encoding(str, dfl_plm, PFM_OS_PERF_EVENT_EXT, &arg); if (ret != PFM_SUCCESS) return ret; if (idx) *idx = arg.idx; return PFM_SUCCESS; } static int pfm_perf_event_os_detect(void *this) { int ret = access(PERF_PROC_FILE, F_OK); return ret ? PFM_ERR_NOTSUPP : PFM_SUCCESS; } pfmlib_os_t pfmlib_os_perf={ .name = "perf_event", .id = PFM_OS_PERF_EVENT, .atdesc = perf_event_mods, .detect = pfm_perf_event_os_detect, .get_os_attr_info = perf_get_os_attr_info, .get_os_nattrs = perf_get_os_nattrs, .encode = pfmlib_perf_event_encode, }; pfmlib_os_t pfmlib_os_perf_ext={ .name = "perf_event extended", .id = PFM_OS_PERF_EVENT_EXT, .atdesc = perf_event_ext_mods, .detect = pfm_perf_event_os_detect, .get_os_attr_info = perf_get_os_attr_info, .get_os_nattrs = perf_get_os_nattrs, .encode = pfmlib_perf_event_encode, }; libpfm-4.9.0/lib/pfmlib_amd64_k8.c0000664000175000017500000000540113223402656016376 0ustar eranianeranian/* * pfmlib_amd64_k8.c : AMD64 K8 * * Copyright (c) 2010 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_amd64_priv.h" #include "events/amd64_events_k8.h" #define DEFINE_K8_REV(d, n, r, pmuid) \ pfmlib_pmu_t amd64_k8_##n##_support={ \ .desc = "AMD64 K8 "#d, \ .name = "amd64_k8_"#n, \ .pmu = pmuid, \ .pmu_rev = r, \ .pme_count = LIBPFM_ARRAY_SIZE(amd64_k8_pe),\ .type = PFM_PMU_TYPE_CORE, \ .supported_plm = AMD64_K7_PLM, \ .num_cntrs = 4, \ .max_encoding = 1, \ .pe = amd64_k8_pe, \ .atdesc = amd64_mods, \ .flags = PFMLIB_PMU_FL_RAW_UMASK, \ \ .cpu_family = pmuid, \ .pmu_detect = pfm_amd64_family_detect, \ .get_event_encoding[PFM_OS_NONE] = pfm_amd64_get_encoding, \ PFMLIB_ENCODE_PERF(pfm_amd64_get_perf_encoding), \ .get_event_first = pfm_amd64_get_event_first, \ .get_event_next = pfm_amd64_get_event_next, \ .event_is_valid = pfm_amd64_event_is_valid, \ .validate_table = pfm_amd64_validate_table, \ .get_event_info = pfm_amd64_get_event_info, \ .get_event_attr_info = pfm_amd64_get_event_attr_info,\ PFMLIB_VALID_PERF_PATTRS(pfm_amd64_perf_validate_pattrs),\ .get_event_nattrs = pfm_amd64_get_event_nattrs, \ .get_num_events = pfm_amd64_get_num_events, \ } DEFINE_K8_REV(RevB, revb, AMD64_K8_REV_B, PFM_PMU_AMD64_K8_REVB); DEFINE_K8_REV(RevC, revc, AMD64_K8_REV_C, PFM_PMU_AMD64_K8_REVC); DEFINE_K8_REV(RevD, revd, AMD64_K8_REV_D, PFM_PMU_AMD64_K8_REVD); DEFINE_K8_REV(RevE, reve, AMD64_K8_REV_E, PFM_PMU_AMD64_K8_REVE); DEFINE_K8_REV(RevF, revf, AMD64_K8_REV_F, PFM_PMU_AMD64_K8_REVF); DEFINE_K8_REV(RevG, revg, AMD64_K8_REV_G, PFM_PMU_AMD64_K8_REVG); libpfm-4.9.0/lib/pfmlib_intel_knl_unc_m2pcie.c0000664000175000017500000000604513223402656021151 0ustar eranianeranian/* * pfmlib_intel_knl_m2pcie.c : Intel Knights Landing M2PCIe uncore PMU * * Copyright (c) 2016 Intel Corp. All rights reserved * Contributed by Peinan Zhang * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_intel_x86_priv.h" #include "pfmlib_intel_snbep_unc_priv.h" #include "events/intel_knl_unc_m2pcie_events.h" static void display_m2p(void *this, pfmlib_event_desc_t *e, void *val) { const intel_x86_entry_t *pe = this_pe(this); pfm_snbep_unc_reg_t *reg = val; __pfm_vbprintf("[UNC_R2PCIE=0x%"PRIx64" event=0x%x umask=0x%x en=%d " "inv=%d edge=%d thres=%d] %s\n", reg->val, reg->com.unc_event, reg->com.unc_umask, reg->com.unc_en, reg->com.unc_inv, reg->com.unc_edge, reg->com.unc_thres, pe[e->event].name); } pfmlib_pmu_t intel_knl_unc_m2pcie_support = { .desc = "Intel Knights Landing M2PCIe uncore", .name = "knl_unc_m2pcie", .perf_name = "uncore_m2pcie", .pmu = PFM_PMU_INTEL_KNL_UNC_M2PCIE, .pme_count = LIBPFM_ARRAY_SIZE(intel_knl_unc_m2pcie_pe), .type = PFM_PMU_TYPE_UNCORE, .num_cntrs = 4, .num_fixed_cntrs = 0, .max_encoding = 1, .pe = intel_knl_unc_m2pcie_pe, .atdesc = snbep_unc_mods, .flags = PFMLIB_PMU_FL_RAW_UMASK, .pmu_detect = pfm_intel_knl_unc_detect, .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding, PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding), PFMLIB_OS_DETECT(pfm_intel_x86_perf_detect), .get_event_first = pfm_intel_x86_get_event_first, .get_event_next = pfm_intel_x86_get_event_next, .event_is_valid = pfm_intel_x86_event_is_valid, .validate_table = pfm_intel_x86_validate_table, .get_event_info = pfm_intel_x86_get_event_info, .get_event_attr_info = pfm_intel_x86_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs), .get_event_nattrs = pfm_intel_x86_get_event_nattrs, .display_reg = display_m2p, }; libpfm-4.9.0/lib/pfmlib_intel_hswep_unc_ha.c0000664000175000017500000000670013223402656020722 0ustar eranianeranian/* * pfmlib_intel_hswep_unc_ha.c : Intel Haswell-EP Home Agent (HA) uncore PMU * * Copyright (c) 2014 Google Inc. All rights reserved * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_intel_x86_priv.h" #include "pfmlib_intel_snbep_unc_priv.h" #include "events/intel_hswep_unc_ha_events.h" static void display_ha(void *this, pfmlib_event_desc_t *e, void *val) { const intel_x86_entry_t *pe = this_pe(this); pfm_snbep_unc_reg_t *reg = val; pfm_snbep_unc_reg_t f; __pfm_vbprintf("[UNC_HA=0x%"PRIx64" event=0x%x umask=0x%x en=%d " "inv=%d edge=%d thres=%d] %s\n", reg->val, reg->com.unc_event, reg->com.unc_umask, reg->com.unc_en, reg->com.unc_inv, reg->com.unc_edge, reg->com.unc_thres, pe[e->event].name); if (e->count == 1) return; f.val = e->codes[1]; __pfm_vbprintf("[UNC_HA_ADDR=0x%"PRIx64" lo_addr=0x%x hi_addr=0x%x]\n", f.val, f.ha_addr.lo_addr, f.ha_addr.hi_addr); f.val = e->codes[2]; __pfm_vbprintf("[UNC_HA_OPC=0x%"PRIx64" opc=0x%x]\n", f.val, f.ha_opc.opc); } #define DEFINE_HA_BOX(n) \ pfmlib_pmu_t intel_hswep_unc_ha##n##_support = {\ .desc = "Intel Haswell-EP HA "#n" uncore",\ .name = "hswep_unc_ha"#n,\ .perf_name = "uncore_ha_"#n,\ .pmu = PFM_PMU_INTEL_HSWEP_UNC_HA##n,\ .pme_count = LIBPFM_ARRAY_SIZE(intel_hswep_unc_h_pe),\ .type = PFM_PMU_TYPE_UNCORE,\ .num_cntrs = 4,\ .num_fixed_cntrs = 0,\ .max_encoding = 3, /* address matchers */\ .pe = intel_hswep_unc_h_pe,\ .atdesc = snbep_unc_mods,\ .flags = PFMLIB_PMU_FL_RAW_UMASK,\ .pmu_detect = pfm_intel_hswep_unc_detect,\ .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding,\ PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding),\ PFMLIB_OS_DETECT(pfm_intel_x86_perf_detect), \ .get_event_first = pfm_intel_x86_get_event_first,\ .get_event_next = pfm_intel_x86_get_event_next,\ .event_is_valid = pfm_intel_x86_event_is_valid,\ .validate_table = pfm_intel_x86_validate_table,\ .get_event_info = pfm_intel_x86_get_event_info,\ .get_event_attr_info = pfm_intel_x86_get_event_attr_info,\ PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs),\ .get_event_nattrs = pfm_intel_x86_get_event_nattrs,\ .display_reg = display_ha,\ } DEFINE_HA_BOX(0); DEFINE_HA_BOX(1); libpfm-4.9.0/lib/pfmlib_intel_bdx_unc_r3qpi.c0000664000175000017500000000622213223402656021016 0ustar eranianeranian/* * pfmlib_intel_bdx_r3qpi.c : Intel BroadwellX R3QPI uncore PMU * * Copyright (c) 2017 Google Inc. All rights reserved * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_intel_x86_priv.h" #include "pfmlib_intel_snbep_unc_priv.h" #include "events/intel_bdx_unc_r3qpi_events.h" static void display_r3(void *this, pfmlib_event_desc_t *e, void *val) { const intel_x86_entry_t *pe = this_pe(this); pfm_snbep_unc_reg_t *reg = val; __pfm_vbprintf("[UNC_R3QPI=0x%"PRIx64" event=0x%x umask=0x%x en=%d " "inv=%d edge=%d thres=%d] %s\n", reg->val, reg->com.unc_event, reg->com.unc_umask, reg->com.unc_en, reg->com.unc_inv, reg->com.unc_edge, reg->com.unc_thres, pe[e->event].name); } #define DEFINE_R3QPI_BOX(n) \ pfmlib_pmu_t intel_bdx_unc_r3qpi##n##_support = {\ .desc = "Intel BroadwellX R3QPI"#n" uncore", \ .name = "bdx_unc_r3qpi"#n,\ .perf_name = "uncore_r3qpi_"#n, \ .pmu = PFM_PMU_INTEL_BDX_UNC_R3QPI##n, \ .pme_count = LIBPFM_ARRAY_SIZE(intel_bdx_unc_r3_pe),\ .type = PFM_PMU_TYPE_UNCORE,\ .num_cntrs = 3,\ .num_fixed_cntrs = 0,\ .max_encoding = 1,\ .pe = intel_bdx_unc_r3_pe,\ .atdesc = snbep_unc_mods,\ .flags = PFMLIB_PMU_FL_RAW_UMASK,\ .pmu_detect = pfm_intel_bdx_unc_detect,\ .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding,\ PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding),\ PFMLIB_OS_DETECT(pfm_intel_x86_perf_detect), \ .get_event_first = pfm_intel_x86_get_event_first,\ .get_event_next = pfm_intel_x86_get_event_next,\ .event_is_valid = pfm_intel_x86_event_is_valid,\ .validate_table = pfm_intel_x86_validate_table,\ .get_event_info = pfm_intel_x86_get_event_info,\ .get_event_attr_info = pfm_intel_x86_get_event_attr_info,\ PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs),\ .get_event_nattrs = pfm_intel_x86_get_event_nattrs,\ .display_reg = display_r3,\ } DEFINE_R3QPI_BOX(0); DEFINE_R3QPI_BOX(1); DEFINE_R3QPI_BOX(2); libpfm-4.9.0/lib/pfmlib_intel_snb_unc.c0000664000175000017500000000546213223402656017712 0ustar eranianeranian/* * pfmlib_intel_snb_unc.c : Intel SandyBridge C-Box uncore PMU * * Copyright (c) 2012 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_intel_x86_priv.h" #define INTEL_SNB_UNC_ATTRS \ (_INTEL_X86_ATTR_I|_INTEL_X86_ATTR_E|_INTEL_X86_ATTR_C) #include "events/intel_snb_unc_events.h" static const int snb_models[] = { 42, /* Sandy Bridge (Core i7 26xx, 25xx) */ 0 }; #define SNB_UNC_CBOX(n, p) \ pfmlib_pmu_t intel_snb_unc_cbo##n##_support={ \ .desc = "Intel Sandy Bridge C-box"#n" uncore", \ .name = "snb_unc_cbo"#n, \ .perf_name = "uncore_cbox_"#n, \ .pmu = PFM_PMU_INTEL_SNB_UNC_CB##n, \ .pme_count = LIBPFM_ARRAY_SIZE(intel_snb_unc_##p##_pe), \ .type = PFM_PMU_TYPE_UNCORE, \ .num_cntrs = 2, \ .num_fixed_cntrs = 1, \ .max_encoding = 1,\ .pe = intel_snb_unc_##p##_pe, \ .atdesc = intel_x86_mods, \ .flags = PFMLIB_PMU_FL_RAW_UMASK\ | PFMLIB_PMU_FL_NO_SMPL,\ .cpu_family = 6,\ .cpu_models = snb_models, \ .pmu_detect = pfm_intel_x86_model_detect,\ .get_event_encoding[PFM_OS_NONE] = pfm_intel_x86_get_encoding, \ PFMLIB_ENCODE_PERF(pfm_intel_nhm_unc_get_perf_encoding), \ PFMLIB_OS_DETECT(pfm_intel_x86_perf_detect), \ .get_event_first = pfm_intel_x86_get_event_first, \ .get_event_next = pfm_intel_x86_get_event_next, \ .event_is_valid = pfm_intel_x86_event_is_valid, \ .validate_table = pfm_intel_x86_validate_table, \ .get_event_info = pfm_intel_x86_get_event_info, \ .get_event_attr_info = pfm_intel_x86_get_event_attr_info, \ PFMLIB_VALID_PERF_PATTRS(pfm_intel_x86_perf_validate_pattrs),\ .get_event_nattrs = pfm_intel_x86_get_event_nattrs,\ } SNB_UNC_CBOX(0, cbo0); SNB_UNC_CBOX(1, cbo); SNB_UNC_CBOX(2, cbo); SNB_UNC_CBOX(3, cbo); libpfm-4.9.0/lib/pfmlib_intel_snbep_unc_r2pcie.c0000664000175000017500000000506113223402656021476 0ustar eranianeranian/* * pfmlib_intel_snbep_r2pcie.c : Intel SandyBridge-EP R2PCIe uncore PMU * * Copyright (c) 2012 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_intel_x86_priv.h" #include "pfmlib_intel_snbep_unc_priv.h" #include "events/intel_snbep_unc_r2pcie_events.h" pfmlib_pmu_t intel_snbep_unc_r2pcie_support = { .desc = "Intel Sandy Bridge-EP R2PCIe uncore", .name = "snbep_unc_r2pcie", .perf_name = "uncore_r2pcie", .pmu = PFM_PMU_INTEL_SNBEP_UNC_R2PCIE, .pme_count = LIBPFM_ARRAY_SIZE(intel_snbep_unc_r2_pe), .type = PFM_PMU_TYPE_UNCORE, .num_cntrs = 4, .num_fixed_cntrs = 0, .max_encoding = 1, .pe = intel_snbep_unc_r2_pe, .atdesc = snbep_unc_mods, .flags = PFMLIB_PMU_FL_RAW_UMASK | PFMLIB_PMU_FL_NO_SMPL, .pmu_detect = pfm_intel_snbep_unc_detect, .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding, PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding), .get_event_first = pfm_intel_x86_get_event_first, .get_event_next = pfm_intel_x86_get_event_next, .event_is_valid = pfm_intel_x86_event_is_valid, .validate_table = pfm_intel_x86_validate_table, .get_event_info = pfm_intel_x86_get_event_info, .get_event_attr_info = pfm_intel_x86_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs), .get_event_nattrs = pfm_intel_x86_get_event_nattrs, }; libpfm-4.9.0/lib/pfmlib_itanium.c0000664000175000017500000010161313223402656016531 0ustar eranianeranian/* * pfmlib_itanium.c : support for Itanium-family PMU * * Copyright (c) 2001-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include /* public headers */ #include /* private headers */ #include "pfmlib_priv.h" /* library private */ #include "pfmlib_priv_ia64.h" /* architecture private */ #include "pfmlib_itanium_priv.h" /* PMU private */ #include "itanium_events.h" /* PMU private */ #define is_ear(i) event_is_ear(itanium_pe+(i)) #define is_ear_tlb(i) event_is_tlb_ear(itanium_pe+(i)) #define is_iear(i) event_is_iear(itanium_pe+(i)) #define is_dear(i) event_is_dear(itanium_pe+(i)) #define is_btb(i) event_is_btb(itanium_pe+(i)) #define has_opcm(i) event_opcm_ok(itanium_pe+(i)) #define has_iarr(i) event_iarr_ok(itanium_pe+(i)) #define has_darr(i) event_darr_ok(itanium_pe+(i)) #define evt_use_opcm(e) ((e)->pfp_ita_pmc8.opcm_used != 0 || (e)->pfp_ita_pmc9.opcm_used !=0) #define evt_use_irange(e) ((e)->pfp_ita_irange.rr_used) #define evt_use_drange(e) ((e)->pfp_ita_drange.rr_used) #define evt_umask(e) itanium_pe[(e)].pme_umask /* let's define some handy shortcuts! */ #define pmc_plm pmc_ita_count_reg.pmc_plm #define pmc_ev pmc_ita_count_reg.pmc_ev #define pmc_oi pmc_ita_count_reg.pmc_oi #define pmc_pm pmc_ita_count_reg.pmc_pm #define pmc_es pmc_ita_count_reg.pmc_es #define pmc_umask pmc_ita_count_reg.pmc_umask #define pmc_thres pmc_ita_count_reg.pmc_thres #define pmc_ism pmc_ita_count_reg.pmc_ism /* * Description of the PMC register mappings use by * this module (as reported in pfmlib_reg_t.reg_num): * * 0 -> PMC0 * 1 -> PMC1 * n -> PMCn * * The following are in the model specific rr_br[]: * IBR0 -> 0 * IBR1 -> 1 * ... * IBR7 -> 7 * DBR0 -> 0 * DBR1 -> 1 * ... * DBR7 -> 7 * * We do not use a mapping table, instead we make up the * values on the fly given the base. */ #define PFMLIB_ITA_PMC_BASE 0 static int pfm_ita_detect(void) { int ret = PFMLIB_ERR_NOTSUPP; /* * we support all chips (there is only one!) in the Itanium family */ if (pfm_ia64_get_cpu_family() == 0x07) ret = PFMLIB_SUCCESS; return ret; } /* * Part of the following code will eventually go into a perfmon library */ static int valid_assign(unsigned int *as, pfmlib_regmask_t *r_pmcs, unsigned int cnt) { unsigned int i; for(i=0; i < cnt; i++) { if (as[i]==0) return PFMLIB_ERR_NOASSIGN; /* * take care of restricted PMC registers */ if (pfm_regmask_isset(r_pmcs, as[i])) return PFMLIB_ERR_NOASSIGN; } return PFMLIB_SUCCESS; } /* * Automatically dispatch events to corresponding counters following constraints. */ static int pfm_ita_dispatch_counters(pfmlib_input_param_t *inp, pfmlib_ita_input_param_t *mod_in, pfmlib_output_param_t *outp) { #define has_counter(e,b) (itanium_pe[e].pme_counters & (1 << (b)) ? (b) : 0) pfmlib_ita_input_param_t *param = mod_in; pfm_ita_pmc_reg_t reg; pfmlib_event_t *e; pfmlib_reg_t *pc, *pd; pfmlib_regmask_t *r_pmcs; unsigned int i,j,k,l, m; unsigned int max_l0, max_l1, max_l2, max_l3; unsigned int assign[PMU_ITA_NUM_COUNTERS]; unsigned int cnt; e = inp->pfp_events; pc = outp->pfp_pmcs; pd = outp->pfp_pmds; cnt = inp->pfp_event_count; r_pmcs = &inp->pfp_unavail_pmcs; if (PFMLIB_DEBUG()) { for (m=0; m < cnt; m++) { DPRINT("ev[%d]=%s counters=0x%lx\n", m, itanium_pe[e[m].event].pme_name, itanium_pe[e[m].event].pme_counters); } } if (cnt > PMU_ITA_NUM_COUNTERS) return PFMLIB_ERR_TOOMANY; max_l0 = PMU_ITA_FIRST_COUNTER + PMU_ITA_NUM_COUNTERS; max_l1 = PMU_ITA_FIRST_COUNTER + PMU_ITA_NUM_COUNTERS*(cnt>1); max_l2 = PMU_ITA_FIRST_COUNTER + PMU_ITA_NUM_COUNTERS*(cnt>2); max_l3 = PMU_ITA_FIRST_COUNTER + PMU_ITA_NUM_COUNTERS*(cnt>3); DPRINT("max_l0=%u max_l1=%u max_l2=%u max_l3=%u\n", max_l0, max_l1, max_l2, max_l3); /* * This code needs fixing. It is not very pretty and * won't handle more than 4 counters if more become * available ! * For now, worst case in the loop nest: 4! (factorial) */ for (i=PMU_ITA_FIRST_COUNTER; i < max_l0; i++) { assign[0]= has_counter(e[0].event,i); if (max_l1 == PMU_ITA_FIRST_COUNTER && valid_assign(assign, r_pmcs, cnt) == PFMLIB_SUCCESS) goto done; for (j=PMU_ITA_FIRST_COUNTER; j < max_l1; j++) { if (j == i) continue; assign[1] = has_counter(e[1].event,j); if (max_l2 == PMU_ITA_FIRST_COUNTER && valid_assign(assign, r_pmcs, cnt) == PFMLIB_SUCCESS) goto done; for (k=PMU_ITA_FIRST_COUNTER; k < max_l2; k++) { if(k == i || k == j) continue; assign[2] = has_counter(e[2].event,k); if (max_l3 == PMU_ITA_FIRST_COUNTER && valid_assign(assign, r_pmcs, cnt) == PFMLIB_SUCCESS) goto done; for (l=PMU_ITA_FIRST_COUNTER; l < max_l3; l++) { if(l == i || l == j || l == k) continue; assign[3] = has_counter(e[3].event,l); if (valid_assign(assign, r_pmcs, cnt) == PFMLIB_SUCCESS) goto done; } } } } /* we cannot satisfy the constraints */ return PFMLIB_ERR_NOASSIGN; done: for (j=0; j < cnt ; j++ ) { reg.pmc_val = 0; /* clear all */ /* if plm is 0, then assume not specified per-event and use default */ reg.pmc_plm = e[j].plm ? e[j].plm : inp->pfp_dfl_plm; reg.pmc_oi = 1; /* overflow interrupt */ reg.pmc_pm = inp->pfp_flags & PFMLIB_PFP_SYSTEMWIDE ? 1 : 0; reg.pmc_thres = param ? param->pfp_ita_counters[j].thres: 0; reg.pmc_ism = param ? param->pfp_ita_counters[j].ism : PFMLIB_ITA_ISM_BOTH; reg.pmc_umask = is_ear(e[j].event) ? 0x0 : evt_umask(e[j].event); reg.pmc_es = itanium_pe[e[j].event].pme_code; pc[j].reg_num = assign[j]; pc[j].reg_value = reg.pmc_val; pc[j].reg_addr = assign[j]; pc[j].reg_alt_addr= assign[j]; pd[j].reg_num = assign[j]; pd[j].reg_addr = assign[j]; pd[j].reg_alt_addr = assign[j]; __pfm_vbprintf("[PMC%u(pmc%u)=0x%06lx thres=%d es=0x%02x plm=%d umask=0x%x pm=%d ism=0x%x oi=%d] %s\n", assign[j], assign[j], reg.pmc_val, reg.pmc_thres, reg.pmc_es,reg.pmc_plm, reg.pmc_umask, reg.pmc_pm, reg.pmc_ism, reg.pmc_oi, itanium_pe[e[j].event].pme_name); __pfm_vbprintf("[PMD%u(pmd%u)]\n", pd[j].reg_num, pd[j].reg_num); } /* number of PMC registers programmed */ outp->pfp_pmc_count = cnt; outp->pfp_pmd_count = cnt; return PFMLIB_SUCCESS; } static int pfm_dispatch_iear(pfmlib_input_param_t *inp, pfmlib_ita_input_param_t *mod_in, pfmlib_output_param_t *outp) { pfm_ita_pmc_reg_t reg; pfmlib_ita_input_param_t *param = mod_in; pfmlib_ita_input_param_t fake_param; pfmlib_reg_t *pc, *pd; unsigned int pos1, pos2; int iear_idx = -1; unsigned int i, count; pc = outp->pfp_pmcs; pd = outp->pfp_pmds; pos1 = outp->pfp_pmc_count; pos2 = outp->pfp_pmd_count; count = inp->pfp_event_count; for (i=0; i < count; i++) { if (is_iear(inp->pfp_events[i].event)) iear_idx = i; } if (param == NULL || mod_in->pfp_ita_iear.ear_used == 0) { /* * case 3: no I-EAR event, no (or nothing) in param->pfp_ita2_iear.ear_used */ if (iear_idx == -1) return PFMLIB_SUCCESS; memset(&fake_param, 0, sizeof(fake_param)); param = &fake_param; pfm_ita_get_ear_mode(inp->pfp_events[iear_idx].event, ¶m->pfp_ita_iear.ear_mode); param->pfp_ita_iear.ear_umask = evt_umask(inp->pfp_events[iear_idx].event); param->pfp_ita_iear.ear_ism = PFMLIB_ITA_ISM_BOTH; /* force both instruction sets */ DPRINT("I-EAR event with no info\n"); } /* sanity check on the mode */ if (param->pfp_ita_iear.ear_mode < 0 || param->pfp_ita_iear.ear_mode > 2) return PFMLIB_ERR_INVAL; /* * case 2: ear_used=1, event is defined, we use the param info as it is more precise * case 4: ear_used=1, no event (free running I-EAR), use param info */ reg.pmc_val = 0; /* if plm is 0, then assume not specified per-event and use default */ reg.pmc10_ita_reg.iear_plm = param->pfp_ita_iear.ear_plm ? param->pfp_ita_iear.ear_plm : inp->pfp_dfl_plm; reg.pmc10_ita_reg.iear_pm = inp->pfp_flags & PFMLIB_PFP_SYSTEMWIDE ? 1 : 0; reg.pmc10_ita_reg.iear_tlb = param->pfp_ita_iear.ear_mode; reg.pmc10_ita_reg.iear_umask = param->pfp_ita_iear.ear_umask; reg.pmc10_ita_reg.iear_ism = param->pfp_ita_iear.ear_ism; if (pfm_regmask_isset(&inp->pfp_unavail_pmcs, 10)) return PFMLIB_ERR_NOASSIGN; pc[pos1].reg_num = 10; /* PMC10 is I-EAR config register */ pc[pos1].reg_value = reg.pmc_val; pc[pos1].reg_addr = 10; pc[pos1].reg_alt_addr= 10; pos1++; pd[pos2].reg_num = 0; pd[pos2].reg_addr = 0; pd[pos2].reg_alt_addr = 0; pos2++; pd[pos2].reg_num = 1; pd[pos2].reg_addr = 1; pd[pos2].reg_alt_addr = 1; pos2++; __pfm_vbprintf("[PMC10(pmc10)=0x%lx tlb=%s plm=%d pm=%d ism=0x%x umask=0x%x]\n", reg.pmc_val, reg.pmc10_ita_reg.iear_tlb ? "Yes" : "No", reg.pmc10_ita_reg.iear_plm, reg.pmc10_ita_reg.iear_pm, reg.pmc10_ita_reg.iear_ism, reg.pmc10_ita_reg.iear_umask); __pfm_vbprintf("[PMD0(pmd0)]\n[PMD1(pmd1)\n"); /* update final number of entries used */ outp->pfp_pmc_count = pos1; outp->pfp_pmd_count = pos2; return PFMLIB_SUCCESS; } static int pfm_dispatch_dear(pfmlib_input_param_t *inp, pfmlib_ita_input_param_t *mod_in, pfmlib_output_param_t *outp) { pfm_ita_pmc_reg_t reg; pfmlib_ita_input_param_t *param = mod_in; pfmlib_ita_input_param_t fake_param; pfmlib_reg_t *pc, *pd; unsigned int pos1, pos2; int dear_idx = -1; unsigned int i, count; pc = outp->pfp_pmcs; pd = outp->pfp_pmds; pos1 = outp->pfp_pmc_count; pos2 = outp->pfp_pmd_count; count = inp->pfp_event_count; for (i=0; i < count; i++) { if (is_dear(inp->pfp_events[i].event)) dear_idx = i; } if (param == NULL || param->pfp_ita_dear.ear_used == 0) { /* * case 3: no D-EAR event, no (or nothing) in param->pfp_ita2_dear.ear_used */ if (dear_idx == -1) return PFMLIB_SUCCESS; memset(&fake_param, 0, sizeof(fake_param)); param = &fake_param; pfm_ita_get_ear_mode(inp->pfp_events[dear_idx].event, ¶m->pfp_ita_dear.ear_mode); param->pfp_ita_dear.ear_umask = evt_umask(inp->pfp_events[dear_idx].event); param->pfp_ita_dear.ear_ism = PFMLIB_ITA_ISM_BOTH; /* force both instruction sets */ DPRINT("D-EAR event with no info\n"); } /* sanity check on the mode */ if (param->pfp_ita_dear.ear_mode > 2) return PFMLIB_ERR_INVAL; /* * case 2: ear_used=1, event is defined, we use the param info as it is more precise * case 4: ear_used=1, no event (free running D-EAR), use param info */ reg.pmc_val = 0; /* if plm is 0, then assume not specified per-event and use default */ reg.pmc11_ita_reg.dear_plm = param->pfp_ita_dear.ear_plm ? param->pfp_ita_dear.ear_plm : inp->pfp_dfl_plm; reg.pmc11_ita_reg.dear_pm = inp->pfp_flags & PFMLIB_PFP_SYSTEMWIDE ? 1 : 0; reg.pmc11_ita_reg.dear_tlb = param->pfp_ita_dear.ear_mode; reg.pmc11_ita_reg.dear_ism = param->pfp_ita_dear.ear_ism; reg.pmc11_ita_reg.dear_umask = param->pfp_ita_dear.ear_umask; reg.pmc11_ita_reg.dear_pt = param->pfp_ita_drange.rr_used ? 0: 1; if (pfm_regmask_isset(&inp->pfp_unavail_pmcs, 11)) return PFMLIB_ERR_NOASSIGN; pc[pos1].reg_num = 11; /* PMC11 is D-EAR config register */ pc[pos1].reg_value = reg.pmc_val; pc[pos1].reg_addr = 11; pos1++; pd[pos2].reg_num = 2; pd[pos2].reg_addr = 2; pd[pos2].reg_alt_addr = 2; pos2++; pd[pos2].reg_num = 3; pd[pos2].reg_addr = 3; pd[pos2].reg_alt_addr = 3; pos2++; pd[pos2].reg_num = 17; pd[pos2].reg_addr = 17; pd[pos2].reg_alt_addr = 17; pos2++; __pfm_vbprintf("[PMC11(pmc11)=0x%lx tlb=%s plm=%d pm=%d ism=0x%x umask=0x%x pt=%d]\n", reg.pmc_val, reg.pmc11_ita_reg.dear_tlb ? "Yes" : "No", reg.pmc11_ita_reg.dear_plm, reg.pmc11_ita_reg.dear_pm, reg.pmc11_ita_reg.dear_ism, reg.pmc11_ita_reg.dear_umask, reg.pmc11_ita_reg.dear_pt); __pfm_vbprintf("[PMD2(pmd2)]\n[PMD3(pmd3)\nPMD17(pmd17)\n"); /* update final number of entries used */ outp->pfp_pmc_count = pos1; outp->pfp_pmd_count = pos2; return PFMLIB_SUCCESS; } static int pfm_dispatch_opcm(pfmlib_input_param_t *inp, pfmlib_ita_input_param_t *mod_in, pfmlib_output_param_t *outp) { pfmlib_ita_input_param_t *param = mod_in; pfm_ita_pmc_reg_t reg; pfmlib_reg_t *pc = outp->pfp_pmcs; int pos = outp->pfp_pmc_count; if (param == NULL) return PFMLIB_SUCCESS; if (param->pfp_ita_pmc8.opcm_used) { reg.pmc_val = param->pfp_ita_pmc8.pmc_val; if (pfm_regmask_isset(&inp->pfp_unavail_pmcs, 8)) return PFMLIB_ERR_NOASSIGN; pc[pos].reg_num = 8; pc[pos].reg_value = reg.pmc_val; pc[pos].reg_addr = 8; pc[pos].reg_alt_addr = 8; pos++; __pfm_vbprintf("[PMC8(pmc8)=0x%lx m=%d i=%d f=%d b=%d match=0x%x mask=0x%x]\n", reg.pmc_val, reg.pmc8_9_ita_reg.m, reg.pmc8_9_ita_reg.i, reg.pmc8_9_ita_reg.f, reg.pmc8_9_ita_reg.b, reg.pmc8_9_ita_reg.match, reg.pmc8_9_ita_reg.mask); } if (param->pfp_ita_pmc9.opcm_used) { reg.pmc_val = param->pfp_ita_pmc9.pmc_val; if (pfm_regmask_isset(&inp->pfp_unavail_pmcs, 9)) return PFMLIB_ERR_NOASSIGN; pc[pos].reg_num = 9; pc[pos].reg_value = reg.pmc_val; pc[pos].reg_addr = 9; pc[pos].reg_alt_addr = 9; pos++; __pfm_vbprintf("[PMC9(pmc9)=0x%lx m=%d i=%d f=%d b=%d match=0x%x mask=0x%x]\n", reg.pmc_val, reg.pmc8_9_ita_reg.m, reg.pmc8_9_ita_reg.i, reg.pmc8_9_ita_reg.f, reg.pmc8_9_ita_reg.b, reg.pmc8_9_ita_reg.match, reg.pmc8_9_ita_reg.mask); } outp->pfp_pmc_count = pos; return PFMLIB_SUCCESS; } static int pfm_dispatch_btb(pfmlib_input_param_t *inp, pfmlib_ita_input_param_t *mod_in, pfmlib_output_param_t *outp) { pfm_ita_pmc_reg_t reg; pfmlib_ita_input_param_t *param = mod_in; pfmlib_ita_input_param_t fake_param; pfmlib_reg_t *pc, *pd; int found_btb=0; unsigned int i, count; unsigned int pos1, pos2; reg.pmc_val = 0; pc = outp->pfp_pmcs; pd = outp->pfp_pmds; pos1 = outp->pfp_pmc_count; pos2 = outp->pfp_pmd_count; count = inp->pfp_event_count; for (i=0; i < count; i++) { if (is_btb(inp->pfp_events[i].event)) found_btb = 1; } if (param == NULL || param->pfp_ita_btb.btb_used == 0) { /* * case 3: no BTB event, no param */ if (found_btb == 0) return PFMLIB_SUCCESS; /* * case 1: BTB event, no param, capture all branches */ memset(&fake_param, 0, sizeof(fake_param)); param = &fake_param; param->pfp_ita_btb.btb_tar = 0x1; /* capture TAR */ param->pfp_ita_btb.btb_tm = 0x3; /* all branches */ param->pfp_ita_btb.btb_ptm = 0x3; /* all branches */ param->pfp_ita_btb.btb_ppm = 0x3; /* all branches */ param->pfp_ita_btb.btb_tac = 0x1; /* capture TAC */ param->pfp_ita_btb.btb_bac = 0x1; /* capture BAC */ DPRINT("BTB event with no info\n"); } /* * case 2: BTB event, param * case 4: no BTB event, param (free running mode) */ /* if plm is 0, then assume not specified per-event and use default */ reg.pmc12_ita_reg.btbc_plm = param->pfp_ita_btb.btb_plm ? param->pfp_ita_btb.btb_plm : inp->pfp_dfl_plm; reg.pmc12_ita_reg.btbc_pm = inp->pfp_flags & PFMLIB_PFP_SYSTEMWIDE ? 1 : 0; reg.pmc12_ita_reg.btbc_tar = param->pfp_ita_btb.btb_tar & 0x1; reg.pmc12_ita_reg.btbc_tm = param->pfp_ita_btb.btb_tm & 0x3; reg.pmc12_ita_reg.btbc_ptm = param->pfp_ita_btb.btb_ptm & 0x3; reg.pmc12_ita_reg.btbc_ppm = param->pfp_ita_btb.btb_ppm & 0x3; reg.pmc12_ita_reg.btbc_bpt = param->pfp_ita_btb.btb_tac & 0x1; reg.pmc12_ita_reg.btbc_bac = param->pfp_ita_btb.btb_bac & 0x1; if (pfm_regmask_isset(&inp->pfp_unavail_pmcs, 12)) return PFMLIB_ERR_NOASSIGN; pc[pos1].reg_num = 12; pc[pos1].reg_value = reg.pmc_val; pc[pos1].reg_value = 12; pos1++; __pfm_vbprintf("[PMC12(pmc12)=0x%lx plm=%d pm=%d tar=%d tm=%d ptm=%d ppm=%d bpt=%d bac=%d]\n", reg.pmc_val, reg.pmc12_ita_reg.btbc_plm, reg.pmc12_ita_reg.btbc_pm, reg.pmc12_ita_reg.btbc_tar, reg.pmc12_ita_reg.btbc_tm, reg.pmc12_ita_reg.btbc_ptm, reg.pmc12_ita_reg.btbc_ppm, reg.pmc12_ita_reg.btbc_bpt, reg.pmc12_ita_reg.btbc_bac); /* * PMD16 is included in list of used PMD */ for(i=8; i < 17; i++, pos2++) { pd[pos2].reg_num = i; pd[pos2].reg_addr = i; pd[pos2].reg_alt_addr = i; __pfm_vbprintf("[PMD%u(pmd%u)]\n", pd[pos2].reg_num, pd[pos2].reg_num); } /* update final number of entries used */ outp->pfp_pmc_count = pos1; outp->pfp_pmd_count = pos2; return PFMLIB_SUCCESS; } /* * mode = 0 -> check code (enforce bundle alignment) * mode = 1 -> check data */ static int check_intervals(pfmlib_ita_input_rr_t *irr, int mode, int *n_intervals) { int i; pfmlib_ita_input_rr_desc_t *lim = irr->rr_limits; for(i=0; i < 4; i++) { /* end marker */ if (lim[i].rr_start == 0 && lim[i].rr_end == 0) break; /* invalid entry */ if (lim[i].rr_start >= lim[i].rr_end) return PFMLIB_ERR_IRRINVAL; if (mode == 0 && (lim[i].rr_start & 0xf || lim[i].rr_end & 0xf)) return PFMLIB_ERR_IRRALIGN; } *n_intervals = i; return PFMLIB_SUCCESS; } static void do_normal_rr(unsigned long start, unsigned long end, pfmlib_reg_t *br, int nbr, int dir, int *idx, int *reg_idx, int plm) { unsigned long size, l_addr, c; unsigned long l_offs = 0, r_offs = 0; unsigned long l_size, r_size; dbreg_t db; int p2; if (nbr < 1 || end <= start) return; size = end - start; DPRINT("start=0x%016lx end=0x%016lx size=0x%lx bytes (%lu bundles) nbr=%d dir=%d\n", start, end, size, size >> 4, nbr, dir); p2 = pfm_ia64_fls(size); c = ALIGN_DOWN(end, p2); DPRINT("largest power of two possible: 2^%d=0x%lx, crossing=0x%016lx\n", p2, 1UL << p2, c); if ((c - (1UL<= start) { l_addr = c - (1UL << p2); } else { p2--; if ((c + (1UL<>l_offs: 0x%lx\n", l_offs); } } else if (dir == 1 && r_size != 0 && nbr == 1) { p2++; l_addr = start; if (PFMLIB_DEBUG()) { r_offs = l_addr+(1UL<>r_offs: 0x%lx\n", r_offs); } } l_size = l_addr - start; r_size = end - l_addr-(1UL<>largest chunk: 2^%d @0x%016lx-0x%016lx\n", p2, l_addr, l_addr+(1UL<>before: 0x%016lx-0x%016lx\n", start, l_addr); if (r_size && !r_offs) DPRINT(">>after : 0x%016lx-0x%016lx\n", l_addr+(1UL<>1; if (nbr & 0x1) { /* * our simple heuristic is: * we assign the largest number of registers to the largest * of the two chunks */ if (l_size > r_size) { l_nbr++; } else { r_nbr++; } } do_normal_rr(start, l_addr, br, l_nbr, 0, idx, reg_idx, plm); do_normal_rr(l_addr+(1UL<rr_start, in_rr->rr_end, n_pairs); __pfm_vbprintf("start offset: -0x%lx end_offset: +0x%lx\n", out_rr->rr_soff, out_rr->rr_eoff); for (j=0; j < n_pairs; j++, base_idx += 2) { d.val = dbr[base_idx+1].reg_value; r_end = dbr[base_idx].reg_value+((~(d.db.db_mask)) & ~(0xffUL << 56)); __pfm_vbprintf("brp%u: db%u: 0x%016lx db%u: plm=0x%x mask=0x%016lx end=0x%016lx\n", dbr[base_idx].reg_num>>1, dbr[base_idx].reg_num, dbr[base_idx].reg_value, dbr[base_idx+1].reg_num, d.db.db_plm, (unsigned long) d.db.db_mask, r_end); } } static int compute_normal_rr(pfmlib_ita_input_rr_t *irr, int dfl_plm, int n, int *base_idx, pfmlib_ita_output_rr_t *orr) { pfmlib_ita_input_rr_desc_t *in_rr; pfmlib_ita_output_rr_desc_t *out_rr; unsigned long r_end; pfmlib_reg_t *br; dbreg_t d; int i, j, br_index, reg_idx, prev_index; in_rr = irr->rr_limits; out_rr = orr->rr_infos; br = orr->rr_br; reg_idx = *base_idx; br_index = 0; for (i=0; i < n; i++, in_rr++, out_rr++) { /* * running out of registers */ if (br_index == 8) break; prev_index = br_index; do_normal_rr( in_rr->rr_start, in_rr->rr_end, br, 4 - (reg_idx>>1), /* how many pairs available */ 0, &br_index, ®_idx, in_rr->rr_plm ? in_rr->rr_plm : dfl_plm); DPRINT("br_index=%d reg_idx=%d\n", br_index, reg_idx); /* * compute offsets */ out_rr->rr_soff = out_rr->rr_eoff = 0; for(j=prev_index; j < br_index; j+=2) { d.val = br[j+1].reg_value; r_end = br[j].reg_value+((~(d.db.db_mask)+1) & ~(0xffUL << 56)); if (br[j].reg_value <= in_rr->rr_start) out_rr->rr_soff = in_rr->rr_start - br[j].reg_value; if (r_end >= in_rr->rr_end) out_rr->rr_eoff = r_end - in_rr->rr_end; } if (PFMLIB_VERBOSE()) print_one_range(in_rr, out_rr, br, prev_index, (br_index-prev_index)>>1); } /* do not have enough registers to cover all the ranges */ if (br_index == 8 && i < n) return PFMLIB_ERR_TOOMANY; orr->rr_nbr_used = br_index; return PFMLIB_SUCCESS; } static int pfm_dispatch_irange(pfmlib_input_param_t *inp, pfmlib_ita_input_param_t *mod_in, pfmlib_output_param_t *outp, pfmlib_ita_output_param_t *mod_out) { pfm_ita_pmc_reg_t reg; pfmlib_ita_input_param_t *param = mod_in; pfmlib_reg_t *pc = outp->pfp_pmcs; pfmlib_ita_input_rr_t *irr; pfmlib_ita_output_rr_t *orr; int pos = outp->pfp_pmc_count; int ret, base_idx = 0; int n_intervals; if (param == NULL || param->pfp_ita_irange.rr_used == 0) return PFMLIB_SUCCESS; if (mod_out == NULL) return PFMLIB_ERR_INVAL; irr = ¶m->pfp_ita_irange; orr = &mod_out->pfp_ita_irange; ret = check_intervals(irr, 0, &n_intervals); if (ret != PFMLIB_SUCCESS) return ret; if (n_intervals < 1) return PFMLIB_ERR_IRRINVAL; DPRINT("n_intervals=%d\n", n_intervals); ret = compute_normal_rr(irr, inp->pfp_dfl_plm, n_intervals, &base_idx, orr); if (ret != PFMLIB_SUCCESS) { return ret == PFMLIB_ERR_TOOMANY ? PFMLIB_ERR_IRRTOOMANY : ret; } reg.pmc_val = 0; reg.pmc13_ita_reg.irange_ta = 0x0; if (pfm_regmask_isset(&inp->pfp_unavail_pmcs, 13)) return PFMLIB_ERR_NOASSIGN; pc[pos].reg_num = 13; pc[pos].reg_value = reg.pmc_val; pc[pos].reg_addr = 13; pc[pos].reg_alt_addr= 13; pos++; __pfm_vbprintf("[PMC13(pmc13)=0x%lx ta=%d]\n", reg.pmc_val, reg.pmc13_ita_reg.irange_ta); outp->pfp_pmc_count = pos; return PFMLIB_SUCCESS; } static int pfm_dispatch_drange(pfmlib_input_param_t *inp, pfmlib_ita_input_param_t *mod_in, pfmlib_output_param_t *outp, pfmlib_ita_output_param_t *mod_out) { pfmlib_ita_input_param_t *param = mod_in; pfmlib_event_t *e = inp->pfp_events; pfmlib_reg_t *pc = outp->pfp_pmcs; pfmlib_ita_input_rr_t *irr; pfmlib_ita_output_rr_t *orr; pfm_ita_pmc_reg_t reg; unsigned int i, count; int pos = outp->pfp_pmc_count; int ret, base_idx = 0; int n_intervals; if (param == NULL || param->pfp_ita_drange.rr_used == 0) return PFMLIB_SUCCESS; if (mod_out == NULL) return PFMLIB_ERR_INVAL; irr = ¶m->pfp_ita_drange; orr = &mod_out->pfp_ita_drange; ret = check_intervals(irr, 1 , &n_intervals); if (ret != PFMLIB_SUCCESS) return ret; if (n_intervals < 1) return PFMLIB_ERR_DRRINVAL; DPRINT("n_intervals=%d\n", n_intervals); ret = compute_normal_rr(irr, inp->pfp_dfl_plm, n_intervals, &base_idx, orr); if (ret != PFMLIB_SUCCESS) { return ret == PFMLIB_ERR_TOOMANY ? PFMLIB_ERR_DRRTOOMANY : ret; } count = inp->pfp_event_count; for (i=0; i < count; i++) { if (is_dear(e[i].event)) return PFMLIB_SUCCESS; /* will be done there */ } reg.pmc_val = 0UL; /* * here we have no other choice but to use the default priv level as there is no * specific D-EAR event provided */ reg.pmc11_ita_reg.dear_plm = inp->pfp_dfl_plm; if (pfm_regmask_isset(&inp->pfp_unavail_pmcs, 11)) return PFMLIB_ERR_NOASSIGN; pc[pos].reg_num = 11; pc[pos].reg_value = reg.pmc_val; pc[pos].reg_addr = 11; pc[pos].reg_alt_addr= 11; pos++; __pfm_vbprintf("[PMC11(pmc11)=0x%lx tlb=%s plm=%d pm=%d ism=0x%x umask=0x%x pt=%d]\n", reg.pmc_val, reg.pmc11_ita_reg.dear_tlb ? "Yes" : "No", reg.pmc11_ita_reg.dear_plm, reg.pmc11_ita_reg.dear_pm, reg.pmc11_ita_reg.dear_ism, reg.pmc11_ita_reg.dear_umask, reg.pmc11_ita_reg.dear_pt); outp->pfp_pmc_count = pos; return PFMLIB_SUCCESS; } static int check_qualifier_constraints(pfmlib_input_param_t *inp, pfmlib_ita_input_param_t *mod_in) { pfmlib_event_t *e = inp->pfp_events; unsigned int i, count; count = inp->pfp_event_count; for(i=0; i < count; i++) { /* * skip check for counter which requested it. Use at your own risk. * No all counters have necessarily been validated for use with * qualifiers. Typically the event is counted as if no constraint * existed. */ if (mod_in->pfp_ita_counters[i].flags & PFMLIB_ITA_FL_EVT_NO_QUALCHECK) continue; if (evt_use_irange(mod_in) && has_iarr(e[i].event) == 0) return PFMLIB_ERR_FEATCOMB; if (evt_use_drange(mod_in) && has_darr(e[i].event) == 0) return PFMLIB_ERR_FEATCOMB; if (evt_use_opcm(mod_in) && has_opcm(e[i].event) == 0) return PFMLIB_ERR_FEATCOMB; } return PFMLIB_SUCCESS; } static int check_range_plm(pfmlib_input_param_t *inp, pfmlib_ita_input_param_t *mod_in) { unsigned int i, count; if (mod_in->pfp_ita_drange.rr_used == 0 && mod_in->pfp_ita_irange.rr_used == 0) return PFMLIB_SUCCESS; /* * range restriction applies to all events, therefore we must have a consistent * set of plm and they must match the pfp_dfl_plm which is used to setup the debug * registers */ count = inp->pfp_event_count; for(i=0; i < count; i++) { if (inp->pfp_events[i].plm && inp->pfp_events[i].plm != inp->pfp_dfl_plm) return PFMLIB_ERR_FEATCOMB; } return PFMLIB_SUCCESS; } static int pfm_ita_dispatch_events(pfmlib_input_param_t *inp, void *model_in, pfmlib_output_param_t *outp, void *model_out) { int ret; pfmlib_ita_input_param_t *mod_in = (pfmlib_ita_input_param_t *)model_in; pfmlib_ita_output_param_t *mod_out = (pfmlib_ita_output_param_t *)model_out; /* * nothing will come out of this combination */ if (mod_out && mod_in == NULL) return PFMLIB_ERR_INVAL; /* check opcode match, range restriction qualifiers */ if (mod_in && check_qualifier_constraints(inp, mod_in) != PFMLIB_SUCCESS) return PFMLIB_ERR_FEATCOMB; /* check for problems with raneg restriction and per-event plm */ if (mod_in && check_range_plm(inp, mod_in) != PFMLIB_SUCCESS) return PFMLIB_ERR_FEATCOMB; ret = pfm_ita_dispatch_counters(inp, mod_in, outp); if (ret != PFMLIB_SUCCESS) return ret; /* now check for I-EAR */ ret = pfm_dispatch_iear(inp, mod_in, outp); if (ret != PFMLIB_SUCCESS) return ret; /* now check for D-EAR */ ret = pfm_dispatch_dear(inp, mod_in, outp); if (ret != PFMLIB_SUCCESS) return ret; /* now check for Opcode matchers */ ret = pfm_dispatch_opcm(inp, mod_in, outp); if (ret != PFMLIB_SUCCESS) return ret; ret = pfm_dispatch_btb(inp, mod_in, outp); if (ret != PFMLIB_SUCCESS) return ret; ret = pfm_dispatch_irange(inp, mod_in, outp, mod_out);; if (ret != PFMLIB_SUCCESS) return ret; ret = pfm_dispatch_drange(inp, mod_in, outp, mod_out);; return ret; } /* XXX: return value is also error code */ int pfm_ita_get_event_maxincr(unsigned int i, unsigned int *maxincr) { if (i >= PME_ITA_EVENT_COUNT || maxincr == NULL) return PFMLIB_ERR_INVAL; *maxincr = itanium_pe[i].pme_maxincr; return PFMLIB_SUCCESS; } int pfm_ita_is_ear(unsigned int i) { return i >= PME_ITA_EVENT_COUNT || ! is_ear(i) ? 0 : 1; } int pfm_ita_is_dear(unsigned int i) { return i >= PME_ITA_EVENT_COUNT || ! is_dear(i) ? 0 : 1; } int pfm_ita_is_dear_tlb(unsigned int i) { return i >= PME_ITA_EVENT_COUNT || ! (is_dear(i) && is_ear_tlb(i)) ? 0 : 1; } int pfm_ita_is_dear_cache(unsigned int i) { return i >= PME_ITA_EVENT_COUNT || ! (is_dear(i) && !is_ear_tlb(i)) ? 0 : 1; } int pfm_ita_is_iear(unsigned int i) { return i >= PME_ITA_EVENT_COUNT || ! is_iear(i) ? 0 : 1; } int pfm_ita_is_iear_tlb(unsigned int i) { return i >= PME_ITA_EVENT_COUNT || ! (is_iear(i) && is_ear_tlb(i)) ? 0 : 1; } int pfm_ita_is_iear_cache(unsigned int i) { return i >= PME_ITA_EVENT_COUNT || ! (is_iear(i) && !is_ear_tlb(i)) ? 0 : 1; } int pfm_ita_is_btb(unsigned int i) { return i >= PME_ITA_EVENT_COUNT || ! is_btb(i) ? 0 : 1; } int pfm_ita_support_iarr(unsigned int i) { return i >= PME_ITA_EVENT_COUNT || ! has_iarr(i) ? 0 : 1; } int pfm_ita_support_darr(unsigned int i) { return i >= PME_ITA_EVENT_COUNT || ! has_darr(i) ? 0 : 1; } int pfm_ita_support_opcm(unsigned int i) { return i >= PME_ITA_EVENT_COUNT || ! has_opcm(i) ? 0 : 1; } int pfm_ita_get_ear_mode(unsigned int i, pfmlib_ita_ear_mode_t *m) { if (!is_ear(i) || m == NULL) return PFMLIB_ERR_INVAL; *m = is_ear_tlb(i) ? PFMLIB_ITA_EAR_TLB_MODE : PFMLIB_ITA_EAR_CACHE_MODE; return PFMLIB_SUCCESS; } static int pfm_ita_get_event_code(unsigned int i, unsigned int cnt, int *code) { if (cnt != PFMLIB_CNT_FIRST && (cnt < 4 || cnt > 7)) return PFMLIB_ERR_INVAL; *code = (int)itanium_pe[i].pme_code; return PFMLIB_SUCCESS; } /* * This function is accessible directly to the user */ int pfm_ita_get_event_umask(unsigned int i, unsigned long *umask) { if (i >= PME_ITA_EVENT_COUNT || umask == NULL) return PFMLIB_ERR_INVAL; *umask = evt_umask(i); return PFMLIB_SUCCESS; } static char * pfm_ita_get_event_name(unsigned int i) { return itanium_pe[i].pme_name; } static void pfm_ita_get_event_counters(unsigned int j, pfmlib_regmask_t *counters) { unsigned int i; unsigned long m; memset(counters, 0, sizeof(*counters)); m =itanium_pe[j].pme_counters; for(i=0; m ; i++, m>>=1) { if (m & 0x1) pfm_regmask_set(counters, i); } } static void pfm_ita_get_impl_pmcs(pfmlib_regmask_t *impl_pmcs) { unsigned int i = 0; /* all pmcs are contiguous */ for(i=0; i < PMU_ITA_NUM_PMCS; i++) pfm_regmask_set(impl_pmcs, i); } static void pfm_ita_get_impl_pmds(pfmlib_regmask_t *impl_pmds) { unsigned int i = 0; /* all pmds are contiguous */ for(i=0; i < PMU_ITA_NUM_PMDS; i++) pfm_regmask_set(impl_pmds, i); } static void pfm_ita_get_impl_counters(pfmlib_regmask_t *impl_counters) { unsigned int i = 0; /* counting pmds are contiguous */ for(i=4; i < 8; i++) pfm_regmask_set(impl_counters, i); } static void pfm_ita_get_hw_counter_width(unsigned int *width) { *width = PMU_ITA_COUNTER_WIDTH; } static int pfm_ita_get_cycle_event(pfmlib_event_t *e) { e->event = PME_ITA_CPU_CYCLES; return PFMLIB_SUCCESS; } static int pfm_ita_get_inst_retired(pfmlib_event_t *e) { e->event = PME_ITA_IA64_INST_RETIRED; return PFMLIB_SUCCESS; } pfm_pmu_support_t itanium_support={ .pmu_name = "itanium", .pmu_type = PFMLIB_ITANIUM_PMU, .pme_count = PME_ITA_EVENT_COUNT, .pmc_count = PMU_ITA_NUM_PMCS, .pmd_count = PMU_ITA_NUM_PMDS, .num_cnt = PMU_ITA_NUM_COUNTERS, .get_event_code = pfm_ita_get_event_code, .get_event_name = pfm_ita_get_event_name, .get_event_counters = pfm_ita_get_event_counters, .dispatch_events = pfm_ita_dispatch_events, .pmu_detect = pfm_ita_detect, .get_impl_pmcs = pfm_ita_get_impl_pmcs, .get_impl_pmds = pfm_ita_get_impl_pmds, .get_impl_counters = pfm_ita_get_impl_counters, .get_hw_counter_width = pfm_ita_get_hw_counter_width, .get_cycle_event = pfm_ita_get_cycle_event, .get_inst_retired_event = pfm_ita_get_inst_retired /* no event description available for Itanium */ }; libpfm-4.9.0/lib/pfmlib_power7.c0000664000175000017500000000440613223402656016310 0ustar eranianeranian/* * pfmlib_power7.c : IBM Power7 support * * Copyright (C) IBM Corporation, 2009. All rights reserved. * Contributed by Corey Ashford (cjashfor@us.ibm.com) * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_power_priv.h" #include "events/power7_events.h" static int pfm_power7_detect(void* this) { if (__is_processor(PV_POWER7) || __is_processor(PV_POWER7p)) return PFM_SUCCESS; return PFM_ERR_NOTSUPP; } pfmlib_pmu_t power7_support={ .desc = "POWER7", .name = "power7", .pmu = PFM_PMU_POWER7, .pme_count = LIBPFM_ARRAY_SIZE(power7_pe), .type = PFM_PMU_TYPE_CORE, .num_cntrs = 4, .num_fixed_cntrs = 2, .max_encoding = 1, .pe = power7_pe, .pmu_detect = pfm_power7_detect, .get_event_encoding[PFM_OS_NONE] = pfm_gen_powerpc_get_encoding, PFMLIB_ENCODE_PERF(pfm_gen_powerpc_get_perf_encoding), PFMLIB_VALID_PERF_PATTRS(pfm_gen_powerpc_perf_validate_pattrs), .get_event_first = pfm_gen_powerpc_get_event_first, .get_event_next = pfm_gen_powerpc_get_event_next, .event_is_valid = pfm_gen_powerpc_event_is_valid, .validate_table = pfm_gen_powerpc_validate_table, .get_event_info = pfm_gen_powerpc_get_event_info, .get_event_attr_info = pfm_gen_powerpc_get_event_attr_info, }; libpfm-4.9.0/lib/pfmlib_intel_ivbep_unc_r3qpi.c0000664000175000017500000000532613223402656021352 0ustar eranianeranian/* * pfmlib_intel_ivbep_r3qpi.c : Intel IvyBridge-EP R3QPI uncore PMU * * Copyright (c) 2014 Google Inc. All rights reserved * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_intel_x86_priv.h" #include "pfmlib_intel_snbep_unc_priv.h" #include "events/intel_ivbep_unc_r3qpi_events.h" #define DEFINE_R3QPI_BOX(n) \ pfmlib_pmu_t intel_ivbep_unc_r3qpi##n##_support = {\ .desc = "Intel Ivy Bridge-EP R3QPI"#n" uncore", \ .name = "ivbep_unc_r3qpi"#n,\ .perf_name = "uncore_r3qpi_"#n, \ .pmu = PFM_PMU_INTEL_IVBEP_UNC_R3QPI##n, \ .pme_count = LIBPFM_ARRAY_SIZE(intel_ivbep_unc_r3_pe),\ .type = PFM_PMU_TYPE_UNCORE,\ .num_cntrs = 3,\ .num_fixed_cntrs = 0,\ .max_encoding = 1,\ .pe = intel_ivbep_unc_r3_pe,\ .atdesc = snbep_unc_mods,\ .flags = PFMLIB_PMU_FL_RAW_UMASK,\ .pmu_detect = pfm_intel_ivbep_unc_detect,\ .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding,\ PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding),\ PFMLIB_OS_DETECT(pfm_intel_x86_perf_detect), \ .get_event_first = pfm_intel_x86_get_event_first,\ .get_event_next = pfm_intel_x86_get_event_next,\ .event_is_valid = pfm_intel_x86_event_is_valid,\ .validate_table = pfm_intel_x86_validate_table,\ .get_event_info = pfm_intel_x86_get_event_info,\ .get_event_attr_info = pfm_intel_x86_get_event_attr_info,\ PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs),\ .get_event_nattrs = pfm_intel_x86_get_event_nattrs,\ } DEFINE_R3QPI_BOX(0); DEFINE_R3QPI_BOX(1); DEFINE_R3QPI_BOX(2); libpfm-4.9.0/lib/pfmlib_amd64_fam10h.c0000664000175000017500000000525613223402656017140 0ustar eranianeranian/* * pfmlib_amd64_fam10h.c : AMD64 Family 10h * * Copyright (c) 2010 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_amd64_priv.h" #include "events/amd64_events_fam10h.h" #define DEFINE_FAM10H_REV(d, n, r, pmuid) \ pfmlib_pmu_t amd64_fam10h_##n##_support={ \ .desc = "AMD64 Fam10h "#d, \ .name = "amd64_fam10h_"#n, \ .pmu = pmuid, \ .pmu_rev = r, \ .pme_count = LIBPFM_ARRAY_SIZE(amd64_fam10h_pe),\ .type = PFM_PMU_TYPE_CORE, \ .supported_plm = AMD64_FAM10H_PLM, \ .num_cntrs = 4, \ .max_encoding = 1, \ .pe = amd64_fam10h_pe, \ .atdesc = amd64_mods, \ .flags = PFMLIB_PMU_FL_RAW_UMASK, \ \ .cpu_family = pmuid, \ .pmu_detect = pfm_amd64_family_detect, \ .get_event_encoding[PFM_OS_NONE] = pfm_amd64_get_encoding,\ PFMLIB_ENCODE_PERF(pfm_amd64_get_perf_encoding), \ .get_event_first = pfm_amd64_get_event_first, \ .get_event_next = pfm_amd64_get_event_next, \ .event_is_valid = pfm_amd64_event_is_valid, \ .validate_table = pfm_amd64_validate_table, \ .get_event_info = pfm_amd64_get_event_info, \ .get_event_attr_info = pfm_amd64_get_event_attr_info,\ PFMLIB_VALID_PERF_PATTRS(pfm_amd64_perf_validate_pattrs),\ .get_event_nattrs = pfm_amd64_get_event_nattrs, \ .get_num_events = pfm_amd64_get_num_events, \ } DEFINE_FAM10H_REV(Barcelona, barcelona, AMD64_FAM10H_REV_B, PFM_PMU_AMD64_FAM10H_BARCELONA); DEFINE_FAM10H_REV(Shanghai, shanghai, AMD64_FAM10H_REV_C, PFM_PMU_AMD64_FAM10H_SHANGHAI); DEFINE_FAM10H_REV(Istanbul, istanbul, AMD64_FAM10H_REV_D, PFM_PMU_AMD64_FAM10H_ISTANBUL); libpfm-4.9.0/lib/pfmlib_intel_ivb_unc.c0000664000175000017500000000574213223402656017711 0ustar eranianeranian/* * pfmlib_intel_ivb_unc.c : Intel IvyBridge C-Box uncore PMU * * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_intel_x86_priv.h" #define INTEL_SNB_UNC_ATTRS \ (_INTEL_X86_ATTR_I|_INTEL_X86_ATTR_E|_INTEL_X86_ATTR_C) /* same event table as SNB */ #include "events/intel_snb_unc_events.h" static int pfm_ivb_unc_detect(void *this) { int ret; ret = pfm_intel_x86_detect(); if (ret != PFM_SUCCESS) return ret; if (pfm_intel_x86_cfg.family != 6) return PFM_ERR_NOTSUPP; switch (pfm_intel_x86_cfg.model) { case 58: /* IvyBridge */ break; default: return PFM_ERR_NOTSUPP; } return PFM_SUCCESS; } #define IVB_UNC_CBOX(n, p) \ pfmlib_pmu_t intel_ivb_unc_cbo##n##_support={ \ .desc = "Intel Ivy Bridge C-box"#n" uncore", \ .name = "ivb_unc_cbo"#n, \ .perf_name = "uncore_cbox_"#n, \ .pmu = PFM_PMU_INTEL_IVB_UNC_CB##n, \ .pme_count = LIBPFM_ARRAY_SIZE(intel_snb_unc_##p##_pe), \ .type = PFM_PMU_TYPE_UNCORE, \ .num_cntrs = 2, \ .num_fixed_cntrs = 1, \ .max_encoding = 1,\ .pe = intel_snb_unc_##p##_pe, \ .atdesc = intel_x86_mods, \ .flags = PFMLIB_PMU_FL_RAW_UMASK\ | PFMLIB_PMU_FL_NO_SMPL,\ .pmu_detect = pfm_ivb_unc_detect, \ .get_event_encoding[PFM_OS_NONE] = pfm_intel_x86_get_encoding, \ PFMLIB_ENCODE_PERF(pfm_intel_nhm_unc_get_perf_encoding), \ PFMLIB_OS_DETECT(pfm_intel_x86_perf_detect), \ .get_event_first = pfm_intel_x86_get_event_first, \ .get_event_next = pfm_intel_x86_get_event_next, \ .event_is_valid = pfm_intel_x86_event_is_valid, \ .validate_table = pfm_intel_x86_validate_table, \ .get_event_info = pfm_intel_x86_get_event_info, \ .get_event_attr_info = pfm_intel_x86_get_event_attr_info, \ PFMLIB_VALID_PERF_PATTRS(pfm_intel_x86_perf_validate_pattrs),\ .get_event_nattrs = pfm_intel_x86_get_event_nattrs,\ } IVB_UNC_CBOX(0, cbo0); IVB_UNC_CBOX(1, cbo); IVB_UNC_CBOX(2, cbo); IVB_UNC_CBOX(3, cbo); libpfm-4.9.0/lib/pfmlib_amd64_fam17h.c0000664000175000017500000000441113223402656017137 0ustar eranianeranian/* * pfmlib_amd64_fam17h.c : AMD64 Family 17h * * Copyright (c) 2017 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_amd64_priv.h" #include "events/amd64_events_fam17h.h" pfmlib_pmu_t amd64_fam17h_support={ .desc = "AMD64 Fam17h Zen", .name = "amd64_fam17h", .pmu = PFM_PMU_AMD64_FAM17H, .pmu_rev = 0, .pme_count = LIBPFM_ARRAY_SIZE(amd64_fam17h_pe), .type = PFM_PMU_TYPE_CORE, .supported_plm = AMD64_FAM10H_PLM, .num_cntrs = 6, .max_encoding = 1, .pe = amd64_fam17h_pe, .atdesc = amd64_mods, .flags = PFMLIB_PMU_FL_RAW_UMASK, .cpu_family = PFM_PMU_AMD64_FAM17H, .pmu_detect = pfm_amd64_family_detect, .get_event_encoding[PFM_OS_NONE] = pfm_amd64_get_encoding, PFMLIB_ENCODE_PERF(pfm_amd64_get_perf_encoding), .get_event_first = pfm_amd64_get_event_first, .get_event_next = pfm_amd64_get_event_next, .event_is_valid = pfm_amd64_event_is_valid, .validate_table = pfm_amd64_validate_table, .get_event_info = pfm_amd64_get_event_info, .get_event_attr_info = pfm_amd64_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_amd64_perf_validate_pattrs), .get_event_nattrs = pfm_amd64_get_event_nattrs, }; libpfm-4.9.0/lib/pfmlib_intel_x86.c0000664000175000017500000007456713223402656016724 0ustar eranianeranian/* pfmlib_intel_x86.c : common code for Intel X86 processors * * Copyright (c) 2009 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file implements the common code for all Intel X86 processors. */ #include #include #include #include #include /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_intel_x86_priv.h" const pfmlib_attr_desc_t intel_x86_mods[]={ PFM_ATTR_B("k", "monitor at priv level 0"), /* monitor priv level 0 */ PFM_ATTR_B("u", "monitor at priv level 1, 2, 3"), /* monitor priv level 1, 2, 3 */ PFM_ATTR_B("e", "edge level (may require counter-mask >= 1)"), /* edge */ PFM_ATTR_B("i", "invert"), /* invert */ PFM_ATTR_I("c", "counter-mask in range [0-255]"), /* counter-mask */ PFM_ATTR_B("t", "measure any thread"), /* monitor on both threads */ PFM_ATTR_I("ldlat", "load latency threshold (cycles, [3-65535])"), /* load latency threshold */ PFM_ATTR_B("intx", "monitor only inside transactional memory region"), PFM_ATTR_B("intxcp", "do not count occurrences inside aborted transactional memory region"), PFM_ATTR_I("fe_thres", "frontend bubble latency threshold in cycles ([1-4095]"), PFM_ATTR_NULL /* end-marker to avoid exporting number of entries */ }; pfm_intel_x86_config_t pfm_intel_x86_cfg; #define mdhw(m, u, at) (m & u & _INTEL_X86_##at) /* * .byte 0x53 == push ebx. it's universal for 32 and 64 bit * .byte 0x5b == pop ebx. * Some gcc's (4.1.2 on Core2) object to pairing push/pop and ebx in 64 bit mode. * Using the opcode directly avoids this problem. */ static inline void cpuid(unsigned int op, unsigned int *a, unsigned int *b, unsigned int *c, unsigned int *d) { __asm__ __volatile__ (".byte 0x53\n\tcpuid\n\tmovl %%ebx, %%esi\n\t.byte 0x5b" : "=a" (*a), "=S" (*b), "=c" (*c), "=d" (*d) : "a" (op)); } static void pfm_intel_x86_display_reg(void *this, pfmlib_event_desc_t *e) { const intel_x86_entry_t *pe = this_pe(this); pfm_intel_x86_reg_t reg; int i; reg.val = e->codes[0]; /* * handle generic counters */ __pfm_vbprintf("[0x%"PRIx64" event_sel=0x%x umask=0x%x os=%d usr=%d " "en=%d int=%d inv=%d edge=%d cnt_mask=%d", reg.val, reg.sel_event_select, reg.sel_unit_mask, reg.sel_os, reg.sel_usr, reg.sel_en, reg.sel_int, reg.sel_inv, reg.sel_edge, reg.sel_cnt_mask); if (pe[e->event].modmsk & _INTEL_X86_ATTR_T) __pfm_vbprintf(" any=%d", reg.sel_anythr); __pfm_vbprintf("]", e->fstr); for (i = 1 ; i < e->count; i++) __pfm_vbprintf(" [0x%"PRIx64"]", e->codes[i]); __pfm_vbprintf(" %s\n", e->fstr); } /* * number of HW modifiers */ static int intel_x86_num_mods(void *this, int idx) { const intel_x86_entry_t *pe = this_pe(this); unsigned int mask; mask = pe[idx].modmsk; return pfmlib_popcnt(mask); } int intel_x86_attr2mod(void *this, int pidx, int attr_idx) { const intel_x86_entry_t *pe = this_pe(this); size_t x; int n, numasks; numasks = intel_x86_num_umasks(this, pidx); n = attr_idx - numasks; pfmlib_for_each_bit(x, pe[pidx].modmsk) { if (n == 0) break; n--; } return x; } /* * detect processor model using cpuid() * based on documentation * http://www.intel.com/Assets/PDF/appnote/241618.pdf */ int pfm_intel_x86_detect(void) { unsigned int a, b, c, d; char buffer[64]; if (pfm_intel_x86_cfg.family) return PFM_SUCCESS; cpuid(0, &a, &b, &c, &d); strncpy(&buffer[0], (char *)(&b), 4); strncpy(&buffer[4], (char *)(&d), 4); strncpy(&buffer[8], (char *)(&c), 4); buffer[12] = '\0'; /* must be Intel */ if (strcmp(buffer, "GenuineIntel")) return PFM_ERR_NOTSUPP; cpuid(1, &a, &b, &c, &d); pfm_intel_x86_cfg.family = (a >> 8) & 0xf; // bits 11 - 8 pfm_intel_x86_cfg.model = (a >> 4) & 0xf; // Bits 7 - 4 pfm_intel_x86_cfg.stepping = a & 0xf; // Bits 0 - 3 /* extended family */ if (pfm_intel_x86_cfg.family == 0xf) pfm_intel_x86_cfg.family += (a >> 20) & 0xff; /* extended model */ if (pfm_intel_x86_cfg.family >= 0x6) pfm_intel_x86_cfg.model += ((a >> 16) & 0xf) << 4; return PFM_SUCCESS; } int pfm_intel_x86_model_detect(void *this) { pfmlib_pmu_t *pmu = this; const int *p; int ret; ret = pfm_intel_x86_detect(); if (ret != PFM_SUCCESS) return ret; if (pfm_intel_x86_cfg.family != pmu->cpu_family) return PFM_ERR_NOTSUPP; for (p = pmu->cpu_models; *p; p++) { if (*p == pfm_intel_x86_cfg.model) return PFM_SUCCESS; } return PFM_ERR_NOTSUPP; } int pfm_intel_x86_add_defaults(void *this, pfmlib_event_desc_t *e, unsigned int msk, uint64_t *umask, unsigned short max_grpid, int excl_grp_but_0) { const intel_x86_entry_t *pe = this_pe(this); const intel_x86_entry_t *ent; unsigned int i; unsigned short grpid; int j, k, added, skip; int idx; k = e->nattrs; ent = pe+e->event; for(i=0; msk; msk >>=1, i++) { if (!(msk & 0x1)) continue; added = skip = 0; /* * must scan list of possible attributes * (not all possible attributes) */ for (j = 0; j < e->npattrs; j++) { if (e->pattrs[j].ctrl != PFM_ATTR_CTRL_PMU) continue; if (e->pattrs[j].type != PFM_ATTR_UMASK) continue; idx = e->pattrs[j].idx; if (ent->umasks[idx].grpid != i) continue; if (max_grpid != INTEL_X86_MAX_GRPID && i > max_grpid) { skip = 1; continue; } if (intel_x86_uflag(this, e->event, idx, INTEL_X86_GRP_DFL_NONE)) { skip = 1; continue; } grpid = ent->umasks[idx].grpid; if (excl_grp_but_0 != -1 && grpid != 0 && excl_grp_but_0 != grpid) { skip = 1; continue; } /* umask is default for group */ if (intel_x86_uflag(this, e->event, idx, INTEL_X86_DFL)) { DPRINT("added default %s for group %d j=%d idx=%d ucode=0x%"PRIx64"\n", ent->umasks[idx].uname, i, j, idx, ent->umasks[idx].ucode); /* * default could be an alias, but * ucode must reflect actual code */ *umask |= ent->umasks[idx].ucode >> 8; e->attrs[k].id = j; /* pattrs index */ e->attrs[k].ival = 0; k++; added++; if (intel_x86_eflag(this, e->event, INTEL_X86_GRP_EXCL)) goto done; if (intel_x86_uflag(this, e->event, idx, INTEL_X86_EXCL_GRP_GT)) { if (max_grpid != INTEL_X86_MAX_GRPID) { DPRINT("two max_grpid, old=%d new=%d\n", max_grpid, ent->umasks[idx].grpid); return PFM_ERR_UMASK; } max_grpid = ent->umasks[idx].grpid; } } } if (!added && !skip) { DPRINT("no default found for event %s unit mask group %d (max_grpid=%d)\n", ent->name, i, max_grpid); return PFM_ERR_UMASK; } } DPRINT("max_grpid=%d nattrs=%d k=%d umask=0x%"PRIx64"\n", max_grpid, e->nattrs, k, *umask); done: e->nattrs = k; return PFM_SUCCESS; } static int intel_x86_check_pebs(void *this, pfmlib_event_desc_t *e) { const intel_x86_entry_t *pe = this_pe(this); pfmlib_event_attr_info_t *a; int numasks = 0, pebs = 0; int i; #if 1 if (1) // !intel_x86_requesting_pebs(e)) return PFM_SUCCESS; #endif /* * if event has no umask and is PEBS, then we are okay */ if (!pe[e->event].numasks && intel_x86_eflag(this, e->event, INTEL_X86_PEBS)) return PFM_SUCCESS; /* * if the event sets PEBS, then it measn at least one umask * supports PEBS, so we need to check */ for (i = 0; i < e->nattrs; i++) { a = attr(e, i); if (a->ctrl != PFM_ATTR_CTRL_PMU) continue; if (a->type == PFM_ATTR_UMASK) { /* count number of umasks */ numasks++; /* and those that support PEBS */ if (intel_x86_uflag(this, e->event, a->idx, INTEL_X86_PEBS)) pebs++; } } /* * pass if user requested only PEBS umasks */ return pebs != numasks ? PFM_ERR_FEATCOMB : PFM_SUCCESS; } static int intel_x86_check_max_grpid(void *this, pfmlib_event_desc_t *e, unsigned short max_grpid) { const intel_x86_entry_t *pe; pfmlib_event_attr_info_t *a; unsigned short grpid; int i; DPRINT("check: max_grpid=%d\n", max_grpid); pe = this_pe(this); for (i = 0; i < e->nattrs; i++) { a = attr(e, i); if (a->ctrl != PFM_ATTR_CTRL_PMU) continue; if (a->type == PFM_ATTR_UMASK) { grpid = pe[e->event].umasks[a->idx].grpid; if (grpid > max_grpid) return PFM_ERR_FEATCOMB; } } return PFM_SUCCESS; } static int pfm_intel_x86_encode_gen(void *this, pfmlib_event_desc_t *e) { pfmlib_pmu_t *pmu = this; pfmlib_event_attr_info_t *a; const intel_x86_entry_t *pe; pfm_intel_x86_reg_t reg, reg2; unsigned int grpmsk, ugrpmsk = 0; uint64_t umask1, umask2, ucode, last_ucode = ~0ULL; unsigned int modhw = 0; unsigned int plmmsk = 0; int umodmsk = 0, modmsk_r = 0; int k, ret, id; unsigned short max_grpid = INTEL_X86_MAX_GRPID; unsigned short last_grpid = INTEL_X86_MAX_GRPID; unsigned short grpid; int ldlat = 0, ldlat_um = 0; int fe_thr= 0, fe_thr_um = 0; int excl_grp_but_0 = -1; int grpcounts[INTEL_X86_NUM_GRP]; int ncombo[INTEL_X86_NUM_GRP]; memset(grpcounts, 0, sizeof(grpcounts)); memset(ncombo, 0, sizeof(ncombo)); pe = this_pe(this); e->fstr[0] = '\0'; /* * preset certain fields from event code * including modifiers */ reg.val = pe[e->event].code; grpmsk = (1 << pe[e->event].ngrp)-1; /* take into account hardcoded umask */ umask1 = (reg.val >> 8) & 0xff; umask2 = 0; modmsk_r = pe[e->event].modmsk_req; for (k = 0; k < e->nattrs; k++) { a = attr(e, k); if (a->ctrl != PFM_ATTR_CTRL_PMU) continue; if (a->type == PFM_ATTR_UMASK) { grpid = pe[e->event].umasks[a->idx].grpid; /* * certain event groups are meant to be * exclusive, i.e., only unit masks of one group * can be used */ if (last_grpid != INTEL_X86_MAX_GRPID && grpid != last_grpid && intel_x86_eflag(this, e->event, INTEL_X86_GRP_EXCL)) { DPRINT("exclusive unit mask group error\n"); return PFM_ERR_FEATCOMB; } /* * selecting certain umasks in a group may exclude any umasks * from any groups with a higher index * * enforcement requires looking at the grpid of all the umasks */ if (intel_x86_uflag(this, e->event, a->idx, INTEL_X86_EXCL_GRP_GT)) max_grpid = grpid; if (intel_x86_uflag(this, e->event, a->idx, INTEL_X86_EXCL_GRP_BUT_0)) excl_grp_but_0 = grpid; /* * upper layer has removed duplicates * so if we come here more than once, it is for two * disinct umasks * * NCOMBO=no combination of unit masks within the same * umask group */ ++grpcounts[grpid]; /* mark that we have a umask with NCOMBO in this group */ if (intel_x86_uflag(this, e->event, a->idx, INTEL_X86_NCOMBO)) ncombo[grpid] = 1; if (intel_x86_uflag(this, e->event, a->idx, INTEL_X86_LDLAT)) ldlat_um = 1; if (intel_x86_uflag(this, e->event, a->idx, INTEL_X86_FETHR)) fe_thr_um = 1; /* * if more than one umask in this group but one is marked * with ncombo, then fail. It is okay to combine umask within * a group as long as none is tagged with NCOMBO */ if (grpcounts[grpid] > 1 && ncombo[grpid]) { DPRINT("umask %s does not support unit mask combination within group %d\n", pe[e->event].umasks[a->idx].uname, grpid); return PFM_ERR_FEATCOMB; } last_grpid = grpid; ucode = pe[e->event].umasks[a->idx].ucode; modhw |= pe[e->event].umasks[a->idx].modhw; umask2 |= ucode >> 8; ugrpmsk |= 1 << pe[e->event].umasks[a->idx].grpid; modmsk_r |= pe[e->event].umasks[a->idx].umodmsk_req; if (intel_x86_uflag(this, e->event, a->idx, INTEL_X86_CODE_OVERRIDE)) { if (last_ucode != ~0ULL && (ucode & 0xff) != last_ucode) { DPRINT("cannot override event with two different codes for %s\n", pe[e->event].name); return PFM_ERR_FEATCOMB; } last_ucode = ucode & 0xff; reg.sel_event_select = last_ucode; } } else if (a->type == PFM_ATTR_RAW_UMASK) { int ofr_bits = 8; uint64_t rmask; /* set limit on width of raw umask */ if (intel_x86_eflag(this, e->event, INTEL_X86_NHM_OFFCORE)) { ofr_bits = 38; if (e->pmu->pmu == PFM_PMU_INTEL_WSM || e->pmu->pmu == PFM_PMU_INTEL_WSM_DP) ofr_bits = 16; } rmask = (1ULL << ofr_bits) - 1; if (a->idx & ~rmask) { DPRINT("raw umask is too wide max %d bits\n", ofr_bits); return PFM_ERR_ATTR; } /* override umask */ umask2 = a->idx & rmask; ugrpmsk = grpmsk; } else { uint64_t ival = e->attrs[k].ival; switch(a->idx) { case INTEL_X86_ATTR_I: /* invert */ reg.sel_inv = !!ival; umodmsk |= _INTEL_X86_ATTR_I; break; case INTEL_X86_ATTR_E: /* edge */ reg.sel_edge = !!ival; umodmsk |= _INTEL_X86_ATTR_E; break; case INTEL_X86_ATTR_C: /* counter-mask */ if (ival > 255) return PFM_ERR_ATTR_VAL; reg.sel_cnt_mask = ival; umodmsk |= _INTEL_X86_ATTR_C; break; case INTEL_X86_ATTR_U: /* USR */ reg.sel_usr = !!ival; plmmsk |= _INTEL_X86_ATTR_U; umodmsk |= _INTEL_X86_ATTR_U; break; case INTEL_X86_ATTR_K: /* OS */ reg.sel_os = !!ival; plmmsk |= _INTEL_X86_ATTR_K; umodmsk |= _INTEL_X86_ATTR_K; break; case INTEL_X86_ATTR_T: /* anythread (v3 and above) */ reg.sel_anythr = !!ival; umodmsk |= _INTEL_X86_ATTR_T; break; case INTEL_X86_ATTR_LDLAT: /* load latency */ if (ival < 3 || ival > 65535) return PFM_ERR_ATTR_VAL; ldlat = ival; break; case INTEL_X86_ATTR_INTX: /* in_tx */ reg.sel_intx = !!ival; umodmsk |= _INTEL_X86_ATTR_INTX; break; case INTEL_X86_ATTR_INTXCP: /* in_tx_cp */ reg.sel_intxcp = !!ival; umodmsk |= _INTEL_X86_ATTR_INTXCP; break; case INTEL_X86_ATTR_FETHR: /* precise frontend latency threshold */ if (ival < 1 || ival > 4095) return PFM_ERR_ATTR_VAL; fe_thr = ival; break; } } } /* * we need to wait until all the attributes have been parsed to check * for conflicts between hardcoded attributes and user-provided attributes. * we do not want to depend on the order in which they are specified * * The test check for conflicts. It is okay to specify an attribute if * it encodes to the same same value as the hardcoded value. That allows * use to prase a FQESTR (fully-qualified event string) as returned by * the library */ reg2.val = (umask1 | umask2) << 8; if (mdhw(modhw, umodmsk, ATTR_I) && reg2.sel_inv != reg.sel_inv) return PFM_ERR_ATTR_SET; if (mdhw(modhw, umodmsk, ATTR_E) && reg2.sel_edge != reg.sel_edge) return PFM_ERR_ATTR_SET; if (mdhw(modhw, umodmsk, ATTR_C) && reg2.sel_cnt_mask != reg.sel_cnt_mask) return PFM_ERR_ATTR_SET; if (mdhw(modhw, umodmsk, ATTR_U) && reg2.sel_usr != reg.sel_usr) return PFM_ERR_ATTR_SET; if (mdhw(modhw, umodmsk, ATTR_K) && reg2.sel_os != reg.sel_os) return PFM_ERR_ATTR_SET; if (mdhw(modhw, umodmsk, ATTR_T) && reg2.sel_anythr != reg.sel_anythr) return PFM_ERR_ATTR_SET; if (mdhw(modhw, umodmsk, ATTR_INTX) && reg2.sel_intx != reg.sel_intx) return PFM_ERR_ATTR_SET; if (mdhw(modhw, umodmsk, ATTR_INTXCP) && reg2.sel_intxcp != reg.sel_intxcp) return PFM_ERR_ATTR_SET; /* * handle case where no priv level mask was passed. * then we use the dfl_plm */ if (!(plmmsk & (_INTEL_X86_ATTR_K|_INTEL_X86_ATTR_U))) { if ((e->dfl_plm & PFM_PLM0) && (pmu->supported_plm & PFM_PLM0)) reg.sel_os = 1; if ((e->dfl_plm & PFM_PLM3) && (pmu->supported_plm & PFM_PLM3)) reg.sel_usr = 1; } /* * check that there is at least of unit mask in each unit * mask group */ if ((ugrpmsk != grpmsk && !intel_x86_eflag(this, e->event, INTEL_X86_GRP_EXCL)) || ugrpmsk == 0) { ugrpmsk ^= grpmsk; ret = pfm_intel_x86_add_defaults(this, e, ugrpmsk, &umask2, max_grpid, excl_grp_but_0); if (ret != PFM_SUCCESS) return ret; } /* * GRP_EXCL_BUT_0 groups require at least one bit set in grpid = 0 and one in theirs * applies to OFFCORE_RESPONSE umasks on some processors (e.g., Goldmont) */ DPRINT("excl_grp_but_0=%d\n", excl_grp_but_0); if (excl_grp_but_0 != -1) { /* skip group 0, because it is authorized */ for (k = 1; k < INTEL_X86_NUM_GRP; k++) { DPRINT("grpcounts[%d]=%d\n", k, grpcounts[k]); if (grpcounts[k] && k != excl_grp_but_0) { DPRINT("GRP_EXCL_BUT_0 but grpcounts[%d]=%d\n", k, grpcounts[k]); return PFM_ERR_FEATCOMB; } } } ret = intel_x86_check_pebs(this, e); if (ret != PFM_SUCCESS) return ret; /* * check no umask violates the max_grpid constraint */ if (max_grpid != INTEL_X86_MAX_GRPID) { ret = intel_x86_check_max_grpid(this, e, max_grpid); if (ret != PFM_SUCCESS) { DPRINT("event %s: umask from grp > %d\n", pe[e->event].name, max_grpid); return ret; } } if (modmsk_r && (umodmsk ^ modmsk_r)) { DPRINT("required modifiers missing: 0x%x\n", modmsk_r); return PFM_ERR_ATTR; } /* * reorder all the attributes such that the fstr appears always * the same regardless of how the attributes were submitted. */ evt_strcat(e->fstr, "%s", pe[e->event].name); pfmlib_sort_attr(e); for(k=0; k < e->nattrs; k++) { a = attr(e, k); if (a->ctrl != PFM_ATTR_CTRL_PMU) continue; if (a->type == PFM_ATTR_UMASK) evt_strcat(e->fstr, ":%s", pe[e->event].umasks[a->idx].uname); else if (a->type == PFM_ATTR_RAW_UMASK) evt_strcat(e->fstr, ":0x%x", a->idx); } if (fe_thr_um && !fe_thr) { /* try extracting te latency threshold from the event umask first */ fe_thr = (umask2 >> 8) & 0x7; /* if not in the umask ,then use default */ if (!fe_thr) { DPRINT("missing fe_thres= for umask, forcing to default %d cycles\n", INTEL_X86_FETHR_DEFAULT); fe_thr = INTEL_X86_FETHR_DEFAULT; } } /* * encode threshold in final position in extra register */ if (fe_thr && fe_thr_um) { umask2 |= fe_thr << 8; } /* * offcore_response or precise frontend require a separate register */ if (intel_x86_eflag(this, e->event, INTEL_X86_NHM_OFFCORE) || intel_x86_eflag(this, e->event, INTEL_X86_FRONTEND)) { e->codes[1] = umask2; e->count = 2; umask2 = 0; } else { e->count = 1; } if (ldlat && !ldlat_um) { DPRINT("passed ldlat= but not using ldlat umask\n"); return PFM_ERR_ATTR; } /* * force a default ldlat (will not appear in display_reg) */ if (ldlat_um && !ldlat) { DPRINT("missing ldlat= for umask, forcing to default %d cycles\n", INTEL_X86_LDLAT_DEFAULT); ldlat = INTEL_X86_LDLAT_DEFAULT; } if (ldlat && ldlat_um) { e->codes[1] = ldlat; e->count = 2; } /* take into account hardcoded modifiers, so use or on reg.val */ reg.val |= (umask1 | umask2) << 8; reg.sel_en = 1; /* force enable bit to 1 */ reg.sel_int = 1; /* force APIC int to 1 */ e->codes[0] = reg.val; /* * on recent processors (except Atom), edge requires cmask >=1 */ if ((pmu->flags & INTEL_X86_PMU_FL_ECMASK) && reg.sel_edge && !reg.sel_cnt_mask) { DPRINT("edge requires cmask >= 1\n"); return PFM_ERR_ATTR; } /* * decode ALL modifiers */ for (k = 0; k < e->npattrs; k++) { if (e->pattrs[k].ctrl != PFM_ATTR_CTRL_PMU) continue; if (e->pattrs[k].type == PFM_ATTR_UMASK) continue; id = e->pattrs[k].idx; switch(id) { case INTEL_X86_ATTR_U: evt_strcat(e->fstr, ":%s=%lu", intel_x86_mods[id].name, reg.sel_usr); break; case INTEL_X86_ATTR_K: evt_strcat(e->fstr, ":%s=%lu", intel_x86_mods[id].name, reg.sel_os); break; case INTEL_X86_ATTR_E: evt_strcat(e->fstr, ":%s=%lu", intel_x86_mods[id].name, reg.sel_edge); break; case INTEL_X86_ATTR_I: evt_strcat(e->fstr, ":%s=%lu", intel_x86_mods[id].name, reg.sel_inv); break; case INTEL_X86_ATTR_C: evt_strcat(e->fstr, ":%s=%lu", intel_x86_mods[id].name, reg.sel_cnt_mask); break; case INTEL_X86_ATTR_T: evt_strcat(e->fstr, ":%s=%lu", intel_x86_mods[id].name, reg.sel_anythr); break; case INTEL_X86_ATTR_LDLAT: evt_strcat(e->fstr, ":%s=%d", intel_x86_mods[id].name, ldlat); break; case INTEL_X86_ATTR_INTX: evt_strcat(e->fstr, ":%s=%lu", intel_x86_mods[id].name, reg.sel_intx); break; case INTEL_X86_ATTR_INTXCP: evt_strcat(e->fstr, ":%s=%lu", intel_x86_mods[id].name, reg.sel_intxcp); break; case INTEL_X86_ATTR_FETHR: evt_strcat(e->fstr, ":%s=%lu", intel_x86_mods[id].name, fe_thr); break; } } return PFM_SUCCESS; } int pfm_intel_x86_get_encoding(void *this, pfmlib_event_desc_t *e) { int ret; ret = pfm_intel_x86_encode_gen(this, e); if (ret != PFM_SUCCESS) return ret; pfm_intel_x86_display_reg(this, e); return PFM_SUCCESS; } int pfm_intel_x86_get_event_first(void *this) { pfmlib_pmu_t *p = this; int idx = 0; /* skip event for different models */ while (idx < p->pme_count && !is_model_event(this, idx)) idx++; return idx < p->pme_count ? idx : -1; } int pfm_intel_x86_get_event_next(void *this, int idx) { pfmlib_pmu_t *p = this; /* pme_count is always >= 1*/ if (idx >= (p->pme_count-1)) return -1; idx++; /* skip event for different models */ while (idx < p->pme_count && !is_model_event(this, idx)) idx++; return idx < p->pme_count ? idx : -1; } int pfm_intel_x86_event_is_valid(void *this, int pidx) { pfmlib_pmu_t *p = this; return pidx >= 0 && pidx < p->pme_count && is_model_event(this, pidx); } int pfm_intel_x86_validate_table(void *this, FILE *fp) { pfmlib_pmu_t *pmu = this; const intel_x86_entry_t *pe = this_pe(this); int ndfl[INTEL_X86_NUM_GRP]; int i, j, error = 0; unsigned int u, v; int npebs; if (!pmu->atdesc) { fprintf(fp, "pmu: %s missing attr_desc\n", pmu->name); error++; } if (!pmu->supported_plm && pmu->type == PFM_PMU_TYPE_CORE) { fprintf(fp, "pmu: %s supported_plm not set\n", pmu->name); error++; } for(i=0; i < pmu->pme_count; i++) { if (!is_model_event(this, i)) continue; if (!pe[i].name) { fprintf(fp, "pmu: %s event%d: :: no name (prev event was %s)\n", pmu->name, i, i > 1 ? pe[i-1].name : "??"); error++; } if (!pe[i].desc) { fprintf(fp, "pmu: %s event%d: %s :: no description\n", pmu->name, i, pe[i].name); error++; } if (!pe[i].cntmsk) { fprintf(fp, "pmu: %s event%d: %s :: cntmsk=0\n", pmu->name, i, pe[i].name); error++; } if (pe[i].numasks && pe[i].ngrp == 0) { fprintf(fp, "pmu: %s event%d: %s :: ngrp cannot be zero\n", pmu->name, i, pe[i].name); error++; } if (pe[i].numasks && pe[i].umasks == NULL) { fprintf(fp, "pmu: %s event%d: %s :: numasks but no umasks\n", pmu->name, i, pe[i].name); error++; } if (pe[i].numasks == 0 && pe[i].umasks) { fprintf(fp, "pmu: %s event%d: %s :: numasks=0 but umasks defined\n", pmu->name, i, pe[i].name); error++; } if (pe[i].numasks == 0 && pe[i].ngrp) { fprintf(fp, "pmu: %s event%d: %s :: ngrp must be zero\n", pmu->name, i, pe[i].name); error++; } if (pe[i].ngrp >= INTEL_X86_NUM_GRP) { fprintf(fp, "pmu: %s event%d: %s :: ngrp too big (max=%d)\n", pmu->name, i, pe[i].name, INTEL_X86_NUM_GRP); error++; } if (pe[i].model >= PFM_PMU_MAX) { fprintf(fp, "pmu: %s event%d: %s :: model too big (max=%d)\n", pmu->name, i, pe[i].name, PFM_PMU_MAX); error++; } for (j=i+1; j < (int)pmu->pme_count; j++) { if (pe[i].code == pe[j].code && !(pe[j].equiv || pe[i].equiv) && pe[j].cntmsk == pe[i].cntmsk) { fprintf(fp, "pmu: %s events %s and %s have the same code 0x%x\n", pmu->name, pe[i].name, pe[j].name, pe[i].code); error++; } } for(j=0; j < INTEL_X86_NUM_GRP; j++) ndfl[j] = 0; for(j=0, npebs = 0; j < (int)pe[i].numasks; j++) { if (!pe[i].umasks[j].uname) { fprintf(fp, "pmu: %s event%d: %s umask%d :: no name\n", pmu->name, i, pe[i].name, j); error++; } if (pe[i].umasks[j].modhw && (pe[i].umasks[j].modhw | pe[i].modmsk) != pe[i].modmsk) { fprintf(fp, "pmu: %s event%d: %s umask%d: %s :: modhw not subset of modmsk\n", pmu->name, i, pe[i].name, j, pe[i].umasks[j].uname); error++; } if (!pe[i].umasks[j].udesc) { fprintf(fp, "pmu: %s event%d: umask%d: %s :: no description\n", pmu->name, i, j, pe[i].umasks[j].uname); error++; } if (pe[i].ngrp && pe[i].umasks[j].grpid >= pe[i].ngrp) { fprintf(fp, "pmu: %s event%d: %s umask%d: %s :: invalid grpid %d (must be < %d)\n", pmu->name, i, pe[i].name, j, pe[i].umasks[j].uname, pe[i].umasks[j].grpid, pe[i].ngrp); error++; } if (pe[i].umasks[j].umodel >= PFM_PMU_MAX) { fprintf(fp, "pmu: %s event%d: %s umask%d: %s :: model too big (max=%d)\n", pmu->name, i, pe[i].name, j, pe[i].umasks[j].uname, PFM_PMU_MAX); error++; } if (pe[i].umasks[j].uflags & INTEL_X86_DFL) ndfl[pe[i].umasks[j].grpid]++; if (pe[i].umasks[j].uflags & INTEL_X86_PEBS) npebs++; } if (npebs && !intel_x86_eflag(this, i, INTEL_X86_PEBS)) { fprintf(fp, "pmu: %s event%d: %s, pebs umasks but event pebs flag not set\n", pmu->name, i, pe[i].name); error++; } if (intel_x86_eflag(this, i, INTEL_X86_PEBS) && pe[i].numasks && npebs == 0) { fprintf(fp, "pmu: %s event%d: %s, pebs event flag but not umask has pebs flag\n", pmu->name, i, pe[i].name); error++; } /* if only one umask, then ought to be default */ if (pe[i].numasks == 1 && !(pe[i].umasks[0].uflags & INTEL_X86_DFL)) { fprintf(fp, "pmu: %s event%d: %s, only one umask but no default\n", pmu->name, i, pe[i].name); error++; } if (pe[i].numasks) { unsigned int *dfl_model = malloc(sizeof(*dfl_model) * pe[i].numasks); if (!dfl_model) goto skip_dfl; for(u=0; u < pe[i].ngrp; u++) { int l = 0, m; for (v = 0; v < pe[i].numasks; v++) { if (pe[i].umasks[v].grpid != u) continue; if (pe[i].umasks[v].uflags & INTEL_X86_DFL) { for (m = 0; m < l; m++) { if (dfl_model[m] == pe[i].umasks[v].umodel || dfl_model[m] == 0) { fprintf(fp, "pmu: %s event%d: %s grpid %d has 2 default umasks\n", pmu->name, i, pe[i].name, u); error++; } } if (m == l) dfl_model[l++] = pe[i].umasks[v].umodel; } } } free(dfl_model); } skip_dfl: if (pe[i].flags & INTEL_X86_NCOMBO) { fprintf(fp, "pmu: %s event%d: %s :: NCOMBO is unit mask only flag\n", pmu->name, i, pe[i].name); error++; } for(u=0; u < pe[i].numasks; u++) { if (pe[i].umasks[u].uequiv) continue; if (pe[i].umasks[u].uflags & INTEL_X86_NCOMBO) continue; for(v=j+1; v < pe[i].numasks; v++) { if (pe[i].umasks[v].uequiv) continue; if (pe[i].umasks[v].uflags & INTEL_X86_NCOMBO) continue; if (pe[i].umasks[v].grpid != pe[i].umasks[u].grpid) continue; if ((pe[i].umasks[u].ucode & pe[i].umasks[v].ucode) && pe[i].umasks[u].umodel == pe[i].umasks[v].umodel) { fprintf(fp, "pmu: %s event%d: %s :: umask %s and %s have overlapping code bits\n", pmu->name, i, pe[i].name, pe[i].umasks[u].uname, pe[i].umasks[v].uname); error++; } } } } return error ? PFM_ERR_INVAL : PFM_SUCCESS; } int pfm_intel_x86_get_event_attr_info(void *this, int pidx, int attr_idx, pfmlib_event_attr_info_t *info) { const intel_x86_entry_t *pe = this_pe(this); const pfmlib_attr_desc_t *atdesc = this_atdesc(this); int numasks, idx; if (!is_model_event(this, pidx)) { DPRINT("invalid event index %d\n", pidx); return PFM_ERR_INVAL; } numasks = intel_x86_num_umasks(this, pidx); if (attr_idx < numasks) { idx = intel_x86_attr2umask(this, pidx, attr_idx); info->name = pe[pidx].umasks[idx].uname; info->desc = pe[pidx].umasks[idx].udesc; info->equiv= pe[pidx].umasks[idx].uequiv; info->code = pe[pidx].umasks[idx].ucode; if (!intel_x86_uflag(this, pidx, idx, INTEL_X86_CODE_OVERRIDE)) info->code >>= 8; info->type = PFM_ATTR_UMASK; info->is_dfl = intel_x86_uflag(this, pidx, idx, INTEL_X86_DFL); info->is_precise = intel_x86_uflag(this, pidx, idx, INTEL_X86_PEBS); } else { idx = intel_x86_attr2mod(this, pidx, attr_idx); info->name = atdesc[idx].name; info->desc = atdesc[idx].desc; info->type = atdesc[idx].type; info->equiv= NULL; info->code = idx; info->is_dfl = 0; info->is_precise = 0; } info->ctrl = PFM_ATTR_CTRL_PMU; info->idx = idx; /* namespace specific index */ info->dfl_val64 = 0; return PFM_SUCCESS; } int pfm_intel_x86_get_event_info(void *this, int idx, pfm_event_info_t *info) { const intel_x86_entry_t *pe = this_pe(this); pfmlib_pmu_t *pmu = this; if (!is_model_event(this, idx)) { DPRINT("invalid event index %d\n", idx); return PFM_ERR_INVAL; } info->name = pe[idx].name; info->desc = pe[idx].desc; info->code = pe[idx].code; info->equiv = pe[idx].equiv; info->idx = idx; /* private index */ info->pmu = pmu->pmu; /* * no umask: event supports PEBS * with umasks: at least one umask supports PEBS */ info->is_precise = intel_x86_eflag(this, idx, INTEL_X86_PEBS); info->nattrs = intel_x86_num_umasks(this, idx); info->nattrs += intel_x86_num_mods(this, idx); return PFM_SUCCESS; } int pfm_intel_x86_valid_pebs(pfmlib_event_desc_t *e) { pfmlib_event_attr_info_t *a; int i, npebs = 0, numasks = 0; /* first check at the event level */ if (intel_x86_eflag(e->pmu, e->event, INTEL_X86_PEBS)) return PFM_SUCCESS; /* * next check the umasks * * we do not assume we are calling after * pfm_intel_x86_ge_event_encoding(), therefore * we check the unit masks again. * They must all be PEBS-capable. */ for(i=0; i < e->nattrs; i++) { a = attr(e, i); if (a->ctrl != PFM_ATTR_CTRL_PMU || a->type != PFM_ATTR_UMASK) continue; numasks++; if (intel_x86_uflag(e->pmu, e->event, a->idx, INTEL_X86_PEBS)) npebs++; } return npebs == numasks ? PFM_SUCCESS : PFM_ERR_FEATCOMB; } unsigned int pfm_intel_x86_get_event_nattrs(void *this, int pidx) { unsigned int nattrs; nattrs = intel_x86_num_umasks(this, pidx); nattrs += intel_x86_num_mods(this, pidx); return nattrs; } int pfm_intel_x86_can_auto_encode(void *this, int pidx, int uidx) { int numasks; if (intel_x86_eflag(this, pidx, INTEL_X86_NO_AUTOENCODE)) return 0; numasks = intel_x86_num_umasks(this, pidx); if (uidx >= numasks) return 0; return !intel_x86_uflag(this, pidx, uidx, INTEL_X86_NO_AUTOENCODE); } libpfm-4.9.0/lib/pfmlib_intel_snbep_unc_ubo.c0000664000175000017500000000504113223402656021075 0ustar eranianeranian/* * pfmlib_intel_snbep_unc_ubo.c : Intel SandyBridge-EP U-Box uncore PMU * * Copyright (c) 2012 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_intel_x86_priv.h" #include "pfmlib_intel_snbep_unc_priv.h" #include "events/intel_snbep_unc_ubo_events.h" pfmlib_pmu_t intel_snbep_unc_ubo_support = { .desc = "Intel Sandy Bridge-EP U-Box uncore", .name = "snbep_unc_ubo", .perf_name = "uncore_ubox", .pmu = PFM_PMU_INTEL_SNBEP_UNC_UBOX, .pme_count = LIBPFM_ARRAY_SIZE(intel_snbep_unc_u_pe), .type = PFM_PMU_TYPE_UNCORE, .num_cntrs = 2, .num_fixed_cntrs = 1, .max_encoding = 1, .pe = intel_snbep_unc_u_pe, .atdesc = snbep_unc_mods, .flags = PFMLIB_PMU_FL_RAW_UMASK | PFMLIB_PMU_FL_NO_SMPL, .pmu_detect = pfm_intel_snbep_unc_detect, .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding, PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding), .get_event_first = pfm_intel_x86_get_event_first, .get_event_next = pfm_intel_x86_get_event_next, .event_is_valid = pfm_intel_x86_event_is_valid, .validate_table = pfm_intel_x86_validate_table, .get_event_info = pfm_intel_x86_get_event_info, .get_event_attr_info = pfm_intel_x86_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs), .get_event_nattrs = pfm_intel_x86_get_event_nattrs, }; libpfm-4.9.0/lib/pfmlib_cell.c0000664000175000017500000004354513223402656016013 0ustar eranianeranian/* * pfmlib_cell.c : support for the Cell PMU family * * Copyright (c) 2007 TOSHIBA CORPORATION based on code from * Copyright (c) 2001-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include /* public headers */ #include /* private headers */ #include "pfmlib_priv.h" /* library private */ #include "pfmlib_cell_priv.h" /* architecture private */ #include "cell_events.h" /* PMU private */ #define SIGNAL_TYPE_CYCLES 0 #define PM_COUNTER_CTRL_CYLES 0x42C00000U #define PFM_CELL_NUM_PMCS 24 #define PFM_CELL_EVENT_MIN 1 #define PFM_CELL_EVENT_MAX 8 #define PMX_MIN_NUM 1 #define PMX_MAX_NUM 8 #define PFM_CELL_16BIT_CNTR_EVENT_MAX 8 #define PFM_CELL_32BIT_CNTR_EVENT_MAX 4 #define COMMON_REG_NUMS 8 #define ENABLE_WORD0 0 #define ENABLE_WORD1 1 #define ENABLE_WORD2 2 #define PFM_CELL_GRP_CONTROL_REG_GRP0_BIT 30 #define PFM_CELL_GRP_CONTROL_REG_GRP1_BIT 28 #define PFM_CELL_BASE_WORD_UNIT_FIELD_BIT 24 #define PFM_CELL_WORD_UNIT_FIELD_WIDTH 2 #define PFM_CELL_MAX_WORD_NUMBER 3 #define PFM_CELL_COUNTER_CONTROL_GRP1 0x80000000U #define PFM_CELL_DEFAULT_TRIGGER_EVENT_UNIT 0x00555500U #define PFM_CELL_PM_CONTROL_16BIT_CNTR_MASK 0x01E00000U #define PFM_CELL_PM_CONTROL_PPU_CNTR_MODE_PROBLEM 0x00080000U #define PFM_CELL_PM_CONTROL_PPU_CNTR_MODE_SUPERVISOR 0x00000000U #define PFM_CELL_PM_CONTROL_PPU_CNTR_MODE_HYPERVISOR 0x00040000U #define PFM_CELL_PM_CONTROL_PPU_CNTR_MODE_ALL 0x000C0000U #define PFM_CELL_PM_CONTROL_PPU_CNTR_MODE_MASK 0x000C0000U #define ONLY_WORD(x) \ ((x == WORD_0_ONLY)||(x == WORD_2_ONLY)) ? x : 0 struct pfm_cell_signal_group_desc { unsigned int signal_type; unsigned int word_type; unsigned long long word; unsigned long long freq; unsigned int subunit; }; #define swap_int(num1, num2) do { \ int tmp = num1; \ num1 = num2; \ num2 = tmp; \ } while(0) static int pfm_cell_detect(void) { int ret; char buffer[128]; ret = __pfm_getcpuinfo_attr("cpu", buffer, sizeof(buffer)); if (ret == -1) { return PFMLIB_ERR_NOTSUPP; } if (strcmp(buffer, "Cell Broadband Engine, altivec supported")) { return PFMLIB_ERR_NOTSUPP; } return PFMLIB_SUCCESS; } static int get_pmx_offset(int pmx_num, unsigned int *pmx_ctrl_bits) { /* pmx_num==0 -> not specified * pmx_num==1 -> pm0 * : * pmx_num==8 -> pm7 */ int i = 0; int offset; if ((pmx_num >= PMX_MIN_NUM) && (pmx_num <= PMX_MAX_NUM)) { /* offset is specified */ offset = (pmx_num - 1); if ((~*pmx_ctrl_bits >> offset) & 0x1) { *pmx_ctrl_bits |= (0x1 << offset); return offset; } else { /* offset is used */ return PFMLIB_ERR_INVAL; } } else if (pmx_num == 0){ /* offset is not specified */ while (((*pmx_ctrl_bits >> i) & 0x1) && (i < PMX_MAX_NUM)) { i++; } *pmx_ctrl_bits |= (0x1 << i); return i; } /* pmx_num is invalid */ return PFMLIB_ERR_INVAL; } static unsigned long long search_enable_word(int word) { unsigned long long count = 0; while ((~word) & 0x1) { count++; word >>= 1; } return count; } static int get_count_bit(unsigned int type) { int count = 0; while(type) { if (type & 1) { count++; } type >>= 1; } return count; } static int get_debug_bus_word(struct pfm_cell_signal_group_desc *group0, struct pfm_cell_signal_group_desc *group1) { unsigned int word_type0, word_type1; /* search enable word */ word_type0 = group0->word_type; word_type1 = group1->word_type; if (group1->signal_type == NONE_SIGNAL) { group0->word = search_enable_word(word_type0); goto found; } /* swap */ if ((get_count_bit(word_type0) > get_count_bit(word_type1)) || (group0->freq == PFM_CELL_PME_FREQ_SPU)) { swap_int(group0->signal_type, group1->signal_type); swap_int(group0->freq, group1->freq); swap_int(group0->word_type, group1->word_type); swap_int(group0->subunit, group1->subunit); swap_int(word_type0, word_type1); } if ((ONLY_WORD(word_type0) != 0) && (word_type0 == word_type1)) { return PFMLIB_ERR_INVAL; } if (ONLY_WORD(word_type0)) { group0->word = search_enable_word(ONLY_WORD(word_type0)); word_type1 &= ~(1UL << (group0->word)); group1->word = search_enable_word(word_type1); } else if (ONLY_WORD(word_type1)) { group1->word = search_enable_word(ONLY_WORD(word_type1)); word_type0 &= ~(1UL << (group1->word)); group0->word = search_enable_word(word_type0); } else { group0->word = ENABLE_WORD0; if (word_type1 == WORD_0_AND_1) { group1->word = ENABLE_WORD1; } else if(word_type1 == WORD_0_AND_2) { group1->word = ENABLE_WORD2; } else { return PFMLIB_ERR_INVAL; } } found: return PFMLIB_SUCCESS; } static unsigned int get_signal_type(unsigned long long event_code) { return (event_code & 0x00000000FFFFFFFFULL) / 100; } static unsigned int get_signal_bit(unsigned long long event_code) { return (event_code & 0x00000000FFFFFFFFULL) % 100; } static int is_spe_signal_group(unsigned int signal_type) { if (41 <= signal_type && signal_type <= 56) { return 1; } else { return 0; } } static int check_signal_type(pfmlib_input_param_t *inp, pfmlib_cell_input_param_t *mod_in, struct pfm_cell_signal_group_desc *group0, struct pfm_cell_signal_group_desc *group1) { pfmlib_event_t *e; unsigned int event_cnt; int signal_cnt = 0; int i; int cycles_signal_cnt = 0; unsigned int signal_type, subunit; e = inp->pfp_events; event_cnt = inp->pfp_event_count; for(i = 0; i < event_cnt; i++) { signal_type = get_signal_type(cell_pe[e[i].event].pme_code); if ((signal_type == SIGNAL_SPU_TRIGGER) || (signal_type == SIGNAL_SPU_EVENT)) { continue; } if (signal_type == SIGNAL_TYPE_CYCLES) { cycles_signal_cnt = 1; continue; } subunit = 0; if (is_spe_signal_group(signal_type)) { subunit = mod_in->pfp_cell_counters[i].spe_subunit; } switch(signal_cnt) { case 0: group0->signal_type = signal_type; group0->word_type = cell_pe[e[i].event].pme_enable_word; group0->freq = cell_pe[e[i].event].pme_freq; group0->subunit = subunit; signal_cnt++; break; case 1: if ((group0->signal_type != signal_type) || (is_spe_signal_group(signal_type) && group0->subunit != subunit)) { group1->signal_type = signal_type; group1->word_type = cell_pe[e[i].event].pme_enable_word; group1->freq = cell_pe[e[i].event].pme_freq; group1->subunit = subunit; signal_cnt++; } break; case 2: if ((group0->signal_type != signal_type) && (group1->signal_type != signal_type)) { DPRINT("signal count is invalid\n"); return PFMLIB_ERR_INVAL; } break; default: DPRINT("signal count is invalid\n"); return PFMLIB_ERR_INVAL; } } return (signal_cnt + cycles_signal_cnt); } /* * The assignment between the privilege leve options * and ppu-count-mode field in pm_control register. * * option ppu count mode(pm_control) * --------------------------------- * -u(-3) 0b10 : Problem mode * -k(-0) 0b00 : Supervisor mode * -1 0b00 : Supervisor mode * -2 0b01 : Hypervisor mode * two options 0b11 : Any mode * * Note : Hypervisor-mode and Any-mode don't work on PS3. * */ static unsigned int get_ppu_count_mode(unsigned int plm) { unsigned int ppu_count_mode = 0; switch (plm) { case PFM_PLM0: case PFM_PLM1: ppu_count_mode = PFM_CELL_PM_CONTROL_PPU_CNTR_MODE_SUPERVISOR; break; case PFM_PLM2: ppu_count_mode = PFM_CELL_PM_CONTROL_PPU_CNTR_MODE_HYPERVISOR; break; case PFM_PLM3: ppu_count_mode = PFM_CELL_PM_CONTROL_PPU_CNTR_MODE_PROBLEM; break; default : ppu_count_mode = PFM_CELL_PM_CONTROL_PPU_CNTR_MODE_ALL; break; } return ppu_count_mode; } static int pfm_cell_dispatch_counters(pfmlib_input_param_t *inp, pfmlib_cell_input_param_t *mod_in, pfmlib_output_param_t *outp) { pfmlib_event_t *e; pfmlib_reg_t *pc, *pd; unsigned int event_cnt; unsigned int signal_cnt = 0, pmcs_cnt = 0; unsigned int signal_type; unsigned long long signal_bit; struct pfm_cell_signal_group_desc group[2]; int pmx_offset = 0; int i, ret; int input_control, polarity, count_cycle, count_enable; unsigned long long subunit; int shift0, shift1; unsigned int pmx_ctrl_bits; int max_event_cnt = PFM_CELL_32BIT_CNTR_EVENT_MAX; count_enable = 1; group[0].signal_type = group[1].signal_type = NONE_SIGNAL; group[0].word = group[1].word = 0L; group[0].freq = group[1].freq = 0L; group[0].subunit = group[1].subunit = 0; group[0].word_type = group[1].word_type = WORD_NONE; event_cnt = inp->pfp_event_count; e = inp->pfp_events; pc = outp->pfp_pmcs; pd = outp->pfp_pmds; /* check event_cnt */ if (mod_in->control & PFM_CELL_PM_CONTROL_16BIT_CNTR_MASK) max_event_cnt = PFM_CELL_16BIT_CNTR_EVENT_MAX; if (event_cnt < PFM_CELL_EVENT_MIN) return PFMLIB_ERR_NOTFOUND; if (event_cnt > max_event_cnt) return PFMLIB_ERR_TOOMANY; /* check signal type */ signal_cnt = check_signal_type(inp, mod_in, &group[0], &group[1]); if (signal_cnt == PFMLIB_ERR_INVAL) return PFMLIB_ERR_NOASSIGN; /* decide debug_bus word */ if (signal_cnt != 0 && group[0].signal_type != NONE_SIGNAL) { ret = get_debug_bus_word(&group[0], &group[1]); if (ret != PFMLIB_SUCCESS) return PFMLIB_ERR_NOASSIGN; } /* common register setting */ pc[pmcs_cnt].reg_num = REG_GROUP_CONTROL; if (signal_cnt == 1) { pc[pmcs_cnt].reg_value = group[0].word << PFM_CELL_GRP_CONTROL_REG_GRP0_BIT; } else if (signal_cnt == 2) { pc[pmcs_cnt].reg_value = (group[0].word << PFM_CELL_GRP_CONTROL_REG_GRP0_BIT) | (group[1].word << PFM_CELL_GRP_CONTROL_REG_GRP1_BIT); } pmcs_cnt++; pc[pmcs_cnt].reg_num = REG_DEBUG_BUS_CONTROL; if (signal_cnt == 1) { shift0 = PFM_CELL_BASE_WORD_UNIT_FIELD_BIT + ((PFM_CELL_MAX_WORD_NUMBER - group[0].word) * PFM_CELL_WORD_UNIT_FIELD_WIDTH); pc[pmcs_cnt].reg_value = group[0].freq << shift0; } else if (signal_cnt == 2) { shift0 = PFM_CELL_BASE_WORD_UNIT_FIELD_BIT + ((PFM_CELL_MAX_WORD_NUMBER - group[0].word) * PFM_CELL_WORD_UNIT_FIELD_WIDTH); shift1 = PFM_CELL_BASE_WORD_UNIT_FIELD_BIT + ((PFM_CELL_MAX_WORD_NUMBER - group[1].word) * PFM_CELL_WORD_UNIT_FIELD_WIDTH); pc[pmcs_cnt].reg_value = (group[0].freq << shift0) | (group[1].freq << shift1); } pc[pmcs_cnt].reg_value |= PFM_CELL_DEFAULT_TRIGGER_EVENT_UNIT; pmcs_cnt++; pc[pmcs_cnt].reg_num = REG_TRACE_ADDRESS; pc[pmcs_cnt].reg_value = 0; pmcs_cnt++; pc[pmcs_cnt].reg_num = REG_EXT_TRACE_TIMER; pc[pmcs_cnt].reg_value = 0; pmcs_cnt++; pc[pmcs_cnt].reg_num = REG_PM_STATUS; pc[pmcs_cnt].reg_value = 0; pmcs_cnt++; pc[pmcs_cnt].reg_num = REG_PM_CONTROL; pc[pmcs_cnt].reg_value = (mod_in->control & ~PFM_CELL_PM_CONTROL_PPU_CNTR_MODE_MASK) | get_ppu_count_mode(inp->pfp_dfl_plm); pmcs_cnt++; pc[pmcs_cnt].reg_num = REG_PM_INTERVAL; pc[pmcs_cnt].reg_value = mod_in->interval; pmcs_cnt++; pc[pmcs_cnt].reg_num = REG_PM_START_STOP; pc[pmcs_cnt].reg_value = mod_in->triggers; pmcs_cnt++; pmx_ctrl_bits = 0; /* pmX register setting */ for(i = 0; i < event_cnt; i++) { /* PMX_CONTROL */ pmx_offset = get_pmx_offset(mod_in->pfp_cell_counters[i].pmX_control_num, &pmx_ctrl_bits); if (pmx_offset == PFMLIB_ERR_INVAL) { DPRINT("pmX already used\n"); return PFMLIB_ERR_INVAL; } signal_type = get_signal_type(cell_pe[e[i].event].pme_code); if (signal_type == SIGNAL_TYPE_CYCLES) { pc[pmcs_cnt].reg_value = PM_COUNTER_CTRL_CYLES; pc[pmcs_cnt].reg_num = REG_PM0_CONTROL + pmx_offset; pmcs_cnt++; pc[pmcs_cnt].reg_value = cell_pe[e[i].event].pme_code; pc[pmcs_cnt].reg_num = REG_PM0_EVENT + pmx_offset; pmcs_cnt++; pd[i].reg_num = pmx_offset; pd[i].reg_value = 0; continue; } switch(cell_pe[e[i].event].pme_type) { case COUNT_TYPE_BOTH_TYPE: case COUNT_TYPE_CUMULATIVE_LEN: case COUNT_TYPE_MULTI_CYCLE: case COUNT_TYPE_SINGLE_CYCLE: count_cycle = 1; break; case COUNT_TYPE_OCCURRENCE: count_cycle = 0; break; default: return PFMLIB_ERR_INVAL; } signal_bit = get_signal_bit(cell_pe[e[i].event].pme_code); polarity = mod_in->pfp_cell_counters[i].polarity; input_control = mod_in->pfp_cell_counters[i].input_control; subunit = 0; if (is_spe_signal_group(signal_type)) { subunit = mod_in->pfp_cell_counters[i].spe_subunit; } pc[pmcs_cnt].reg_value = ( (signal_bit << (31 - 5)) | (input_control << (31 - 6)) | (polarity << (31 - 7)) | (count_cycle << (31 - 8)) | (count_enable << (31 - 9)) ); pc[pmcs_cnt].reg_num = REG_PM0_CONTROL + pmx_offset; if (signal_type == group[1].signal_type && subunit == group[1].subunit) { pc[pmcs_cnt].reg_value |= PFM_CELL_COUNTER_CONTROL_GRP1; } pmcs_cnt++; /* PMX_EVENT */ pc[pmcs_cnt].reg_num = REG_PM0_EVENT + pmx_offset; /* debug bus word setting */ if (signal_type == group[0].signal_type && subunit == group[0].subunit) { pc[pmcs_cnt].reg_value = (cell_pe[e[i].event].pme_code | (group[0].word << 48) | (subunit << 32)); } else if (signal_type == group[1].signal_type && subunit == group[1].subunit) { pc[pmcs_cnt].reg_value = (cell_pe[e[i].event].pme_code | (group[1].word << 48) | (subunit << 32)); } else if ((signal_type == SIGNAL_SPU_TRIGGER) || (signal_type == SIGNAL_SPU_EVENT)) { pc[pmcs_cnt].reg_value = cell_pe[e[i].event].pme_code | (subunit << 32); } else { return PFMLIB_ERR_INVAL; } pmcs_cnt++; /* pmd setting */ pd[i].reg_num = pmx_offset; pd[i].reg_value = 0; } outp->pfp_pmc_count = pmcs_cnt; outp->pfp_pmd_count = event_cnt; return PFMLIB_SUCCESS; } static int pfm_cell_dispatch_events(pfmlib_input_param_t *inp, void *model_in, pfmlib_output_param_t *outp, void *model_out) { pfmlib_cell_input_param_t *mod_in = (pfmlib_cell_input_param_t *)model_in; pfmlib_cell_input_param_t default_model_in; int i; if (model_in) { mod_in = (pfmlib_cell_input_param_t *)model_in; } else { mod_in = &default_model_in; mod_in->control = 0x80000000; mod_in->interval = 0; mod_in->triggers = 0; for (i = 0; i < PMU_CELL_NUM_COUNTERS; i++) { mod_in->pfp_cell_counters[i].pmX_control_num = 0; mod_in->pfp_cell_counters[i].spe_subunit = 0; mod_in->pfp_cell_counters[i].polarity = 1; mod_in->pfp_cell_counters[i].input_control = 0; mod_in->pfp_cell_counters[i].cnt_mask = 0; mod_in->pfp_cell_counters[i].flags = 0; } } return pfm_cell_dispatch_counters(inp, mod_in, outp); } static int pfm_cell_get_event_code(unsigned int i, unsigned int cnt, int *code) { // if (cnt != PFMLIB_CNT_FIRST && cnt > 2) { if (cnt != PFMLIB_CNT_FIRST && cnt > cell_support.num_cnt) { return PFMLIB_ERR_INVAL; } *code = cell_pe[i].pme_code; return PFMLIB_SUCCESS; } static void pfm_cell_get_event_counters(unsigned int j, pfmlib_regmask_t *counters) { unsigned int i; memset(counters, 0, sizeof(*counters)); for(i=0; i < PMU_CELL_NUM_COUNTERS; i++) { pfm_regmask_set(counters, i); } } static void pfm_cell_get_impl_pmcs(pfmlib_regmask_t *impl_pmcs) { unsigned int i; memset(impl_pmcs, 0, sizeof(*impl_pmcs)); for(i=0; i < PFM_CELL_NUM_PMCS; i++) { pfm_regmask_set(impl_pmcs, i); } } static void pfm_cell_get_impl_pmds(pfmlib_regmask_t *impl_pmds) { unsigned int i; memset(impl_pmds, 0, sizeof(*impl_pmds)); for(i=0; i < PMU_CELL_NUM_PERFCTR; i++) { pfm_regmask_set(impl_pmds, i); } } static void pfm_cell_get_impl_counters(pfmlib_regmask_t *impl_counters) { unsigned int i; for(i=0; i < PMU_CELL_NUM_COUNTERS; i++) { pfm_regmask_set(impl_counters, i); } } static char* pfm_cell_get_event_name(unsigned int i) { return cell_pe[i].pme_name; } static int pfm_cell_get_event_desc(unsigned int ev, char **str) { char *s; s = cell_pe[ev].pme_desc; if (s) { *str = strdup(s); } else { *str = NULL; } return PFMLIB_SUCCESS; } static int pfm_cell_get_cycle_event(pfmlib_event_t *e) { int i; for (i = 0; i < PME_CELL_EVENT_COUNT; i++) { if (!strcmp(cell_pe[i].pme_name, "CYCLES")) { e->event = i; return PFMLIB_SUCCESS; } } return PFMLIB_ERR_NOTFOUND; } int pfm_cell_spe_event(unsigned int event_index) { if (event_index >= PME_CELL_EVENT_COUNT) return 0; return is_spe_signal_group(get_signal_type(cell_pe[event_index].pme_code)); } pfm_pmu_support_t cell_support={ .pmu_name = "CELL", .pmu_type = PFMLIB_CELL_PMU, .pme_count = PME_CELL_EVENT_COUNT, .pmc_count = PFM_CELL_NUM_PMCS, .pmd_count = PMU_CELL_NUM_PERFCTR, .num_cnt = PMU_CELL_NUM_COUNTERS, .get_event_code = pfm_cell_get_event_code, .get_event_name = pfm_cell_get_event_name, .get_event_counters = pfm_cell_get_event_counters, .dispatch_events = pfm_cell_dispatch_events, .pmu_detect = pfm_cell_detect, .get_impl_pmcs = pfm_cell_get_impl_pmcs, .get_impl_pmds = pfm_cell_get_impl_pmds, .get_impl_counters = pfm_cell_get_impl_counters, .get_event_desc = pfm_cell_get_event_desc, .get_cycle_event = pfm_cell_get_cycle_event }; libpfm-4.9.0/lib/pfmlib_sparc_ultra12.c0000664000175000017500000000431713223402656017550 0ustar eranianeranian/* * pfmlib_sparc_ultra12.c : SPARC Ultra I, II * * Copyright (c) 2011 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * Core PMU = architectural perfmon v2 + PEBS */ /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_sparc_priv.h" #include "events/sparc_ultra12_events.h" pfmlib_pmu_t sparc_ultra12_support={ .desc = "Ultra Sparc I/II", .name = "ultra12", .pmu = PFM_PMU_SPARC_ULTRA12, .pme_count = LIBPFM_ARRAY_SIZE(ultra12_pe), .type = PFM_PMU_TYPE_CORE, .supported_plm = SPARC_PLM, .max_encoding = 2, .num_cntrs = 2, .pe = ultra12_pe, .atdesc = NULL, .flags = 0, .pmu_detect = pfm_sparc_detect, .get_event_encoding[PFM_OS_NONE] = pfm_sparc_get_encoding, PFMLIB_ENCODE_PERF(pfm_sparc_get_perf_encoding), .get_event_first = pfm_sparc_get_event_first, .get_event_next = pfm_sparc_get_event_next, .event_is_valid = pfm_sparc_event_is_valid, .validate_table = pfm_sparc_validate_table, .get_event_info = pfm_sparc_get_event_info, .get_event_attr_info = pfm_sparc_get_event_attr_info, PFMLIB_VALID_PERF_PATTRS(pfm_sparc_perf_validate_pattrs), .get_event_nattrs = pfm_sparc_get_event_nattrs, }; libpfm-4.9.0/lib/pfmlib_arm.c0000664000175000017500000001705513223402656015650 0ustar eranianeranian/* * pfmlib_arm.c : support for ARM chips * * Copyright (c) 2010 University of Tennessee * Contributed by Vince Weaver * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ #include #include #include #include #include /* private headers */ #include "pfmlib_priv.h" /* library private */ #include "pfmlib_arm_priv.h" const pfmlib_attr_desc_t arm_mods[]={ PFM_ATTR_B("k", "monitor at kernel level"), PFM_ATTR_B("u", "monitor at user level"), PFM_ATTR_B("hv", "monitor in hypervisor"), PFM_ATTR_NULL /* end-marker to avoid exporting number of entries */ }; pfm_arm_config_t pfm_arm_cfg; #ifdef CONFIG_PFMLIB_OS_LINUX /* * helper function to retrieve one value from /proc/cpuinfo * for internal libpfm use only * attr: the attribute (line) to look for * ret_buf: a buffer to store the value of the attribute (as a string) * maxlen : number of bytes of capacity in ret_buf * * ret_buf is null terminated. * * Return: * 0 : attribute found, ret_buf populated * -1: attribute not found */ static int pfmlib_getcpuinfo_attr(const char *attr, char *ret_buf, size_t maxlen) { FILE *fp = NULL; int ret = -1; size_t attr_len, buf_len = 0; char *p, *value = NULL; char *buffer = NULL; if (attr == NULL || ret_buf == NULL || maxlen < 1) return -1; attr_len = strlen(attr); fp = fopen("/proc/cpuinfo", "r"); if (fp == NULL) return -1; while(pfmlib_getl(&buffer, &buf_len, fp) != -1){ /* skip blank lines */ if (*buffer == '\n') continue; p = strchr(buffer, ':'); if (p == NULL) goto error; /* * p+2: +1 = space, +2= firt character * strlen()-1 gets rid of \n */ *p = '\0'; value = p+2; value[strlen(value)-1] = '\0'; if (!strncmp(attr, buffer, attr_len)) break; } strncpy(ret_buf, value, maxlen-1); ret_buf[maxlen-1] = '\0'; ret = 0; error: free(buffer); fclose(fp); return ret; } #else static int pfmlib_getcpuinfo_attr(const char *attr, char *ret_buf, size_t maxlen) { return -1; } #endif static int arm_num_mods(void *this, int idx) { const arm_entry_t *pe = this_pe(this); unsigned int mask; mask = pe[idx].modmsk; return pfmlib_popcnt(mask); } static inline int arm_attr2mod(void *this, int pidx, int attr_idx) { const arm_entry_t *pe = this_pe(this); size_t x; int n; n = attr_idx; pfmlib_for_each_bit(x, pe[pidx].modmsk) { if (n == 0) break; n--; } return x; } static void pfm_arm_display_reg(void *this, pfmlib_event_desc_t *e, pfm_arm_reg_t reg) { __pfm_vbprintf("[0x%x] %s\n", reg.val, e->fstr); } int pfm_arm_detect(void *this) { int ret; char buffer[128]; ret = pfmlib_getcpuinfo_attr("CPU implementer", buffer, sizeof(buffer)); if (ret == -1) return PFM_ERR_NOTSUPP; pfm_arm_cfg.implementer = strtol(buffer, NULL, 16); ret = pfmlib_getcpuinfo_attr("CPU part", buffer, sizeof(buffer)); if (ret == -1) return PFM_ERR_NOTSUPP; pfm_arm_cfg.part = strtol(buffer, NULL, 16); ret = pfmlib_getcpuinfo_attr("CPU architecture", buffer, sizeof(buffer)); if (ret == -1) return PFM_ERR_NOTSUPP; pfm_arm_cfg.architecture = strtol(buffer, NULL, 16); return PFM_SUCCESS; } int pfm_arm_get_encoding(void *this, pfmlib_event_desc_t *e) { const arm_entry_t *pe = this_pe(this); pfmlib_event_attr_info_t *a; pfm_arm_reg_t reg; unsigned int plm = 0; int i, idx, has_plm = 0; reg.val = pe[e->event].code; for (i = 0; i < e->nattrs; i++) { a = attr(e, i); if (a->ctrl != PFM_ATTR_CTRL_PMU) continue; if (a->type > PFM_ATTR_UMASK) { uint64_t ival = e->attrs[i].ival; switch(a->idx) { case ARM_ATTR_U: /* USR */ if (ival) plm |= PFM_PLM3; has_plm = 1; break; case ARM_ATTR_K: /* OS */ if (ival) plm |= PFM_PLM0; has_plm = 1; break; case ARM_ATTR_HV: /* HYPERVISOR */ if (ival) plm |= PFM_PLMH; has_plm = 1; break; default: return PFM_ERR_ATTR; } } } if (arm_has_plm(this, e)) { if (!has_plm) plm = e->dfl_plm; reg.evtsel.excl_pl1 = !(plm & PFM_PLM0); reg.evtsel.excl_usr = !(plm & PFM_PLM3); reg.evtsel.excl_hyp = !(plm & PFM_PLMH); } evt_strcat(e->fstr, "%s", pe[e->event].name); e->codes[0] = reg.val; e->count = 1; for (i = 0; i < e->npattrs; i++) { if (e->pattrs[i].ctrl != PFM_ATTR_CTRL_PMU) continue; if (e->pattrs[i].type == PFM_ATTR_UMASK) continue; idx = e->pattrs[i].idx; switch(idx) { case ARM_ATTR_K: evt_strcat(e->fstr, ":%s=%lu", arm_mods[idx].name, !reg.evtsel.excl_pl1); break; case ARM_ATTR_U: evt_strcat(e->fstr, ":%s=%lu", arm_mods[idx].name, !reg.evtsel.excl_usr); break; case ARM_ATTR_HV: evt_strcat(e->fstr, ":%s=%lu", arm_mods[idx].name, !reg.evtsel.excl_hyp); break; } } pfm_arm_display_reg(this, e, reg); return PFM_SUCCESS; } int pfm_arm_get_event_first(void *this) { return 0; } int pfm_arm_get_event_next(void *this, int idx) { pfmlib_pmu_t *p = this; if (idx >= (p->pme_count-1)) return -1; return idx+1; } int pfm_arm_event_is_valid(void *this, int pidx) { pfmlib_pmu_t *p = this; return pidx >= 0 && pidx < p->pme_count; } int pfm_arm_validate_table(void *this, FILE *fp) { pfmlib_pmu_t *pmu = this; const arm_entry_t *pe = this_pe(this); int i, error = 0; for(i=0; i < pmu->pme_count; i++) { if (!pe[i].name) { fprintf(fp, "pmu: %s event%d: :: no name (prev event was %s)\n", pmu->name, i, i > 1 ? pe[i-1].name : "??"); error++; } if (!pe[i].desc) { fprintf(fp, "pmu: %s event%d: %s :: no description\n", pmu->name, i, pe[i].name); error++; } } return error ? PFM_ERR_INVAL : PFM_SUCCESS; } int pfm_arm_get_event_attr_info(void *this, int pidx, int attr_idx, pfmlib_event_attr_info_t *info) { int idx; idx = arm_attr2mod(this, pidx, attr_idx); info->name = arm_mods[idx].name; info->desc = arm_mods[idx].desc; info->type = arm_mods[idx].type; info->code = idx; info->is_dfl = 0; info->equiv = NULL; info->ctrl = PFM_ATTR_CTRL_PMU; info->idx = idx; /* namespace specific index */ info->dfl_val64 = 0; info->is_precise = 0; return PFM_SUCCESS; } unsigned int pfm_arm_get_event_nattrs(void *this, int pidx) { return arm_num_mods(this, pidx); } int pfm_arm_get_event_info(void *this, int idx, pfm_event_info_t *info) { pfmlib_pmu_t *pmu = this; const arm_entry_t *pe = this_pe(this); info->name = pe[idx].name; info->desc = pe[idx].desc; info->code = pe[idx].code; info->equiv = NULL; info->idx = idx; /* private index */ info->pmu = pmu->pmu; info->is_precise = 0; /* no attributes defined for ARM yet */ info->nattrs = 0; return PFM_SUCCESS; } libpfm-4.9.0/rules.mk0000664000175000017500000000300413223402656014276 0ustar eranianeranian# # Copyright (c) 2002-2006 Hewlett-Packard Development Company, L.P. # Contributed by Stephane Eranian # # Permission is hereby granted, free of charge, to any person obtaining a copy # of this software and associated documentation files (the "Software"), to deal # in the Software without restriction, including without limitation the rights # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies # of the Software, and to permit persons to whom the Software is furnished to do so, # subject to the following conditions: # # The above copyright notice and this permission notice shall be included in all # copies or substantial portions of the Software. # # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, # INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A # PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT # HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF # CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE # OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # # This file is part of libpfm, a performance monitoring support library for # applications on Linux/ia64. # .SUFFIXES: .c .S .o .lo .cpp .S.o: $(CC) $(CFLAGS) -c $*.S .c.o: $(CC) $(CFLAGS) -c $*.c .cpp.o: $(CXX) $(CFLAGS) -c $*.cpp .c.lo: $(CC) -fPIC -DPIC $(CFLAGS) -c $*.c -o $*.lo .S.lo: $(CC) -fPIC -DPIC $(CFLAGS) -c $*.S -o $*.lo libpfm-4.9.0/perf_examples/0000775000175000017500000000000013223402656015450 5ustar eranianeranianlibpfm-4.9.0/perf_examples/evt2raw.c0000664000175000017500000000563413223402656017216 0ustar eranianeranian/* * evt2raw.c - example which converts an event string (event + modifiers) to * a raw event code usable by the perf tool. * * Copyright (c) 2010 IBM Corp. * Contributed by Corey Ashford * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include #include static void usage(void) { printf("usage: evt2raw [-v] \n" " is the symbolic event, including modifiers, to " "translate to a raw code.\n"); } #define MAX_MODIFIER_CHARS 5 /* u,k,h plus the colon and null terminator */ int main(int argc, char **argv) { int ret, c, verbose = 0; struct perf_event_attr pea; char *event_str, *fstr = NULL; char modifiers[MAX_MODIFIER_CHARS]; if (argc < 2) { usage(); return 1; } while ( (c=getopt(argc, argv, "hv")) != -1) { switch(c) { case 'h': usage(); exit(0); case 'v': verbose = 1; break; default: exit(1); } } event_str = argv[optind]; ret = pfm_initialize(); if (ret != PFM_SUCCESS) errx(1, "Internal error: pfm_initialize returned %s", pfm_strerror(ret)); pea.size = sizeof(struct perf_event_attr); ret = pfm_get_perf_event_encoding(event_str, PFM_PLM0|PFM_PLM3|PFM_PLMH, &pea, &fstr, NULL); if (ret != PFM_SUCCESS) errx(1, "Error: pfm_get_perf_encoding returned %s", pfm_strerror(ret)); if (pea.type != PERF_TYPE_RAW) errx(1, "Error: %s is not a raw hardware event", event_str); modifiers[0] = '\0'; if (pea.exclude_user | pea.exclude_kernel | pea.exclude_hv) { strcat(modifiers, ":"); if (!pea.exclude_user) strcat(modifiers, "u"); if (!pea.exclude_kernel) strcat(modifiers, "k"); if (!pea.exclude_hv) strcat(modifiers, "h"); } if (verbose) printf("r%"PRIx64"%s\t%s\n", pea.config, modifiers, fstr); else printf("r%"PRIx64"%s\n", pea.config, modifiers); if (fstr) free(fstr); return 0; } libpfm-4.9.0/perf_examples/Makefile0000664000175000017500000000516213223402656017114 0ustar eranianeranian# # Copyright (c) 2002-2006 Hewlett-Packard Development Company, L.P. # Contributed by Stephane Eranian # # Permission is hereby granted, free of charge, to any person obtaining a copy # of this software and associated documentation files (the "Software"), to deal # in the Software without restriction, including without limitation the rights # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies # of the Software, and to permit persons to whom the Software is furnished to do so, # subject to the following conditions: # # The above copyright notice and this permission notice shall be included in all # copies or substantial portions of the Software. # # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, # INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A # PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT # HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF # CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE # OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # TOPDIR := $(shell if [ "$$PWD" != "" ]; then echo $$PWD; else pwd; fi)/.. include $(TOPDIR)/config.mk include $(TOPDIR)/rules.mk DIRS= ifeq ($(ARCH),ia64) #DIRS +=ia64 endif ifeq ($(ARCH),x86_64) DIRS += x86 endif ifeq ($(ARCH),i386) DIRS += x86 endif CFLAGS+= -I. -D_GNU_SOURCE -pthread PERF_EVENT_HDR=$(TOPDIR)/include/perfmon/pfmlib_perf_event.h LPC_UTILS=perf_util.o LPC_UTILS_HDR=perf_util.h TARGETS+=self self_basic self_count task task_attach_timeout syst \ notify_self notify_group task_smpl self_smpl_multi \ self_pipe syst_count task_cpu syst_smpl evt2raw \ branch_smpl EXAMPLESDIR=$(DESTDIR)$(DOCDIR)/perf_examples all: $(TARGETS) @set -e ; for d in $(DIRS) ; do $(MAKE) -C $$d $@ ; done # # Many systems don't have ncurses-devel installed # rtop: rtop.o $(PFMLIB) -$(CC) $(CFLAGS) $(LDFLAGS) -D_GNU_SOURCE -o $@ $^ $(LIBS) -lpthread -lncurses -lm $(TARGETS): %:%.o $(LPC_UTILS) $(PFMLIB) $(PERF_EVENT_HDR) $(CC) $(CFLAGS) -o $@ $(LDFLAGS) $< $(LPC_UTILS) $(PFMLIB) $(LIBS) $(LPC_UTILS): $(LPC_UTILS_HDR) clean: @set -e ; for d in $(DIRS) ; do $(MAKE) -C $$d $@ ; done $(RM) -f *.o $(TARGETS) *~ distclean: clean install_examples: $(TARGETS) @echo installing: $(TARGETS) -mkdir -p $(EXAMPLESDIR) $(INSTALL) -m 755 $(TARGETS) $(EXAMPLESDIR) @set -e ; for d in $(DIRS) ; do $(MAKE) -C $$d $@ ; done # # examples are installed as part of the RPM install, typically in /usr/share/doc/libpfm-X.Y/ # .PHONY: install depend install_examples libpfm-4.9.0/perf_examples/task.c0000664000175000017500000002112613223402656016560 0ustar eranianeranian/* * task_inherit.c - example of a task counting event in a tree of child processes * * Copyright (c) 2009 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include #include #include #include #include #include #include #include "perf_util.h" #define MAX_GROUPS 256 typedef struct { const char *events[MAX_GROUPS]; int num_groups; int format_group; int inherit; int print; int pin; pid_t pid; } options_t; static options_t options; static volatile int quit; int child(char **arg) { /* * execute the requested command */ execvp(arg[0], arg); errx(1, "cannot exec: %s\n", arg[0]); /* not reached */ } static void read_groups(perf_event_desc_t *fds, int num) { uint64_t *values = NULL; size_t new_sz, sz = 0; int i, evt; ssize_t ret; /* * { u64 nr; * { u64 time_enabled; } && PERF_FORMAT_ENABLED * { u64 time_running; } && PERF_FORMAT_RUNNING * { u64 value; * { u64 id; } && PERF_FORMAT_ID * } cntr[nr]; * } && PERF_FORMAT_GROUP * * we do not use FORMAT_ID in this program */ for (evt = 0; evt < num; ) { int num_evts_to_read; if (options.format_group) { num_evts_to_read = perf_get_group_nevents(fds, num, evt); new_sz = sizeof(uint64_t) * (3 + num_evts_to_read); } else { num_evts_to_read = 1; new_sz = sizeof(uint64_t) * 3; } if (new_sz > sz) { sz = new_sz; values = realloc(values, sz); } if (!values) err(1, "cannot allocate memory for values\n"); ret = read(fds[evt].fd, values, new_sz); if (ret != (ssize_t)new_sz) { /* unsigned */ if (ret == -1) err(1, "cannot read values event %s", fds[evt].name); /* likely pinned and could not be loaded */ warnx("could not read event %d, tried to read %zu bytes, but got %zd", evt, new_sz, ret); } /* * propagate to save area */ for (i = evt; i < (evt + num_evts_to_read); i++) { if (options.format_group) values[0] = values[3 + (i - evt)]; /* * scaling because we may be sharing the PMU and * thus may be multiplexed */ fds[i].values[0] = values[0]; fds[i].values[1] = values[1]; fds[i].values[2] = values[2]; } evt += num_evts_to_read; } if (values) free(values); } static void print_counts(perf_event_desc_t *fds, int num) { double ratio; uint64_t val, delta; int i; read_groups(fds, num); for(i=0; i < num; i++) { val = perf_scale(fds[i].values); delta = perf_scale_delta(fds[i].values, fds[i].prev_values); ratio = perf_scale_ratio(fds[i].values); /* separate groups */ if (perf_is_group_leader(fds, i)) putchar('\n'); if (options.print) printf("%'20"PRIu64" %'20"PRIu64" %s (%.2f%% scaling, ena=%'"PRIu64", run=%'"PRIu64")\n", val, delta, fds[i].name, (1.0-ratio)*100.0, fds[i].values[1], fds[i].values[2]); else printf("%'20"PRIu64" %s (%.2f%% scaling, ena=%'"PRIu64", run=%'"PRIu64")\n", val, fds[i].name, (1.0-ratio)*100.0, fds[i].values[1], fds[i].values[2]); fds[i].prev_values[0] = fds[i].values[0]; fds[i].prev_values[1] = fds[i].values[1]; fds[i].prev_values[2] = fds[i].values[2]; } } static void sig_handler(int n) { quit = 1; } int parent(char **arg) { perf_event_desc_t *fds = NULL; int status, ret, i, num_fds = 0, grp, group_fd; int ready[2], go[2]; char buf; pid_t pid; go[0] = go[1] = -1; if (pfm_initialize() != PFM_SUCCESS) errx(1, "libpfm initialization failed"); for (grp = 0; grp < options.num_groups; grp++) { int ret; ret = perf_setup_list_events(options.events[grp], &fds, &num_fds); if (ret || !num_fds) exit(1); } pid = options.pid; if (!pid) { ret = pipe(ready); if (ret) err(1, "cannot create pipe ready"); ret = pipe(go); if (ret) err(1, "cannot create pipe go"); /* * Create the child task */ if ((pid=fork()) == -1) err(1, "Cannot fork process"); /* * and launch the child code * * The pipe is used to avoid a race condition * between for() and exec(). We need the pid * of the new tak but we want to start measuring * at the first user level instruction. Thus we * need to prevent exec until we have attached * the events. */ if (pid == 0) { close(ready[0]); close(go[1]); /* * let the parent know we exist */ close(ready[1]); if (read(go[0], &buf, 1) == -1) err(1, "unable to read go_pipe"); exit(child(arg)); } close(ready[1]); close(go[0]); if (read(ready[0], &buf, 1) == -1) err(1, "unable to read child_ready_pipe"); close(ready[0]); } for(i=0; i < num_fds; i++) { int is_group_leader; /* boolean */ is_group_leader = perf_is_group_leader(fds, i); if (is_group_leader) { /* this is the group leader */ group_fd = -1; } else { group_fd = fds[fds[i].group_leader].fd; } /* * create leader disabled with enable_on-exec */ if (!options.pid) { fds[i].hw.disabled = is_group_leader; fds[i].hw.enable_on_exec = is_group_leader; } fds[i].hw.read_format = PERF_FORMAT_SCALE; /* request timing information necessary for scaling counts */ if (is_group_leader && options.format_group) fds[i].hw.read_format |= PERF_FORMAT_GROUP; if (options.inherit) fds[i].hw.inherit = 1; if (options.pin && is_group_leader) fds[i].hw.pinned = 1; fds[i].fd = perf_event_open(&fds[i].hw, pid, -1, group_fd, 0); if (fds[i].fd == -1) { warn("cannot attach event%d %s", i, fds[i].name); goto error; } } if (!options.pid && go[1] > -1) close(go[1]); if (options.print) { if (!options.pid) { while(waitpid(pid, &status, WNOHANG) == 0) { sleep(1); print_counts(fds, num_fds); } } else { while(quit == 0) { sleep(1); print_counts(fds, num_fds); } } } else { if (!options.pid) waitpid(pid, &status, 0); else pause(); print_counts(fds, num_fds); } for(i=0; i < num_fds; i++) close(fds[i].fd); perf_free_fds(fds, num_fds); /* free libpfm resources cleanly */ pfm_terminate(); return 0; error: free(fds); if (!options.pid) kill(SIGKILL, pid); /* free libpfm resources cleanly */ pfm_terminate(); return -1; } static void usage(void) { printf("usage: task [-h] [-i] [-g] [-p] [-P] [-t pid] [-e event1,event2,...] cmd\n" "-h\t\tget help\n" "-i\t\tinherit across fork\n" "-f\t\tuse PERF_FORMAT_GROUP for reading up counts (experimental, not working)\n" "-p\t\tprint counts every second\n" "-P\t\tpin events\n" "-t pid\tmeasure existing pid\n" "-e ev,ev\tgroup of events to measure (multiple -e switches are allowed)\n" ); } int main(int argc, char **argv) { int c; setlocale(LC_ALL, ""); while ((c=getopt(argc, argv,"+he:ifpPt:")) != -1) { switch(c) { case 'e': if (options.num_groups < MAX_GROUPS) { options.events[options.num_groups++] = optarg; } else { errx(1, "you cannot specify more than %d groups.\n", MAX_GROUPS); } break; case 'f': options.format_group = 1; break; case 'p': options.print = 1; break; case 'P': options.pin = 1; break; case 'i': options.inherit = 1; break; case 't': options.pid = atoi(optarg); break; case 'h': usage(); exit(0); default: errx(1, "unknown error"); } } if (options.num_groups == 0) { options.events[0] = "cycles,instructions"; options.num_groups = 1; } if (!argv[optind] && !options.pid) errx(1, "you must specify a command to execute or a thread to attach to\n"); signal(SIGINT, sig_handler); return parent(argv+optind); } libpfm-4.9.0/perf_examples/self_basic.c0000664000175000017500000000766413223402656017723 0ustar eranianeranian/* * self-basic.c - example of a simple self monitoring task no-helper * * Copyright (c) 2010 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. */ #include #include #include #include #include #include #include #include #include #include #include #include #define N 30 static unsigned long fib(unsigned long n) { if (n == 0) return 0; if (n == 1) return 2; return fib(n-1)+fib(n-2); } int main(int argc, char **argv) { struct perf_event_attr attr; int fd, ret; uint64_t count = 0, values[3]; setlocale(LC_ALL, ""); /* * Initialize libpfm library (required before we can use it) */ ret = pfm_initialize(); if (ret != PFM_SUCCESS) errx(1, "cannot initialize library: %s", pfm_strerror(ret)); memset(&attr, 0, sizeof(attr)); /* * 1st argument: event string * 2nd argument: default privilege level (used if not specified in the event string) * 3rd argument: the perf_event_attr to initialize */ ret = pfm_get_perf_event_encoding("cycles", PFM_PLM0|PFM_PLM3, &attr, NULL, NULL); if (ret != PFM_SUCCESS) errx(1, "cannot find encoding: %s", pfm_strerror(ret)); /* * request timing information because event may be multiplexed * and thus it may not count all the time. The scaling information * will be used to scale the raw count as if the event had run all * along */ attr.read_format = PERF_FORMAT_TOTAL_TIME_ENABLED|PERF_FORMAT_TOTAL_TIME_RUNNING; /* do not start immediately after perf_event_open() */ attr.disabled = 1; /* * create the event and attach to self * Note that it attaches only to the main thread, there is no inheritance * to threads that may be created subsequently. * * if mulithreaded, then getpid() must be replaced by gettid() */ fd = perf_event_open(&attr, getpid(), -1, -1, 0); if (fd < 0) err(1, "cannot create event"); /* * start counting now */ ret = ioctl(fd, PERF_EVENT_IOC_ENABLE, 0); if (ret) err(1, "ioctl(enable) failed"); printf("Fibonacci(%d)=%lu\n", N, fib(N)); /* * stop counting */ ret = ioctl(fd, PERF_EVENT_IOC_DISABLE, 0); if (ret) err(1, "ioctl(disable) failed"); /* * read the count + scaling values * * It is not necessary to stop an event to read its value */ ret = read(fd, values, sizeof(values)); if (ret != sizeof(values)) err(1, "cannot read results: %s", strerror(errno)); /* * scale count * * values[0] = raw count * values[1] = TIME_ENABLED * values[2] = TIME_RUNNING */ if (values[2]) count = (uint64_t)((double)values[0] * values[1]/values[2]); printf("count=%'"PRIu64"\n", count); close(fd); /* free libpfm resources cleanly */ pfm_terminate(); return 0; } libpfm-4.9.0/perf_examples/perf_util.h0000664000175000017500000001115213223402656017612 0ustar eranianeranian/* * perf_util.h - helper functions for perf_events * * Copyright (c) 2009 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef __PERF_UTIL_H__ #define __PERF_UTIL_H__ #include #include #include #include typedef struct { struct perf_event_attr hw; uint64_t values[3]; uint64_t prev_values[3]; char *name; uint64_t id; /* event id kernel */ void *buf; size_t pgmsk; int group_leader; int fd; int max_fds; int idx; /* opaque libpfm event identifier */ int cpu; /* cpu to program */ char *fstr; /* fstr from library, must be freed */ } perf_event_desc_t; /* handy shortcut */ #define PERF_FORMAT_SCALE (PERF_FORMAT_TOTAL_TIME_ENABLED|PERF_FORMAT_TOTAL_TIME_RUNNING) extern int perf_setup_argv_events(const char **argv, perf_event_desc_t **fd, int *num_fds); extern int perf_setup_list_events(const char *events, perf_event_desc_t **fd, int *num_fds); extern int perf_read_buffer(perf_event_desc_t *hw, void *buf, size_t sz); extern void perf_free_fds(perf_event_desc_t *fds, int num_fds); extern void perf_skip_buffer(perf_event_desc_t *hw, size_t sz); static inline int perf_read_buffer_32(perf_event_desc_t *hw, void *buf) { return perf_read_buffer(hw, buf, sizeof(uint32_t)); } static inline int perf_read_buffer_64(perf_event_desc_t *hw, void *buf) { return perf_read_buffer(hw, buf, sizeof(uint64_t)); } /* * values[0] = raw count * values[1] = TIME_ENABLED * values[2] = TIME_RUNNING */ static inline uint64_t perf_scale(uint64_t *values) { uint64_t res = 0; if (!values[2] && !values[1] && values[0]) warnx("WARNING: time_running = 0 = time_enabled, raw count not zero\n"); if (values[2] > values[1]) warnx("WARNING: time_running > time_enabled\n"); if (values[2]) res = (uint64_t)((double)values[0] * values[1]/values[2]); return res; } static inline uint64_t perf_scale_delta(uint64_t *values, uint64_t *prev_values) { double pval[3], val[3]; uint64_t res = 0; if (!values[2] && !values[1] && values[0]) warnx("WARNING: time_running = 0 = time_enabled, raw count not zero\n"); if (values[2] > values[1]) warnx("WARNING: time_running > time_enabled\n"); if (values[2] - prev_values[2]) { /* covnert everything to double to avoid overflows! */ pval[0] = prev_values[0]; pval[1] = prev_values[1]; pval[2] = prev_values[2]; val[0] = values[0]; val[1] = values[1]; val[2] = values[2]; res = (uint64_t)(((val[0] - pval[0]) * (val[1] - pval[1])/ (val[2] - pval[2]))); } return res; } /* * TIME_RUNNING/TIME_ENABLED */ static inline double perf_scale_ratio(uint64_t *values) { if (!values[1]) return 0.0; return values[2]*1.0/values[1]; } static inline int perf_fd2event(perf_event_desc_t *fds, int num_events, int fd) { int i; for(i=0; i < num_events; i++) if (fds[i].fd == fd) return i; return -1; } /* * id = PERF_FORMAT_ID */ static inline int perf_id2event(perf_event_desc_t *fds, int num_events, uint64_t id) { int j; for(j=0; j < num_events; j++) if (fds[j].id == id) return j; return -1; } static inline int perf_is_group_leader(perf_event_desc_t *fds, int idx) { return fds[idx].group_leader == idx; } extern int perf_get_group_nevents(perf_event_desc_t *fds, int num, int leader); extern int perf_display_sample(perf_event_desc_t *fds, int num_fds, int idx, struct perf_event_header *ehdr, FILE *fp); extern uint64_t display_lost(perf_event_desc_t *hw, perf_event_desc_t *fds, int num_fds, FILE *fp); extern void display_exit(perf_event_desc_t *hw, FILE *fp); extern void display_freq(int mode, perf_event_desc_t *hw, FILE *fp); #endif libpfm-4.9.0/perf_examples/x86/0000775000175000017500000000000013223402656016075 5ustar eranianeranianlibpfm-4.9.0/perf_examples/x86/Makefile0000664000175000017500000000366213223402656017544 0ustar eranianeranian# # Copyright (c) 2002-2006 Hewlett-Packard Development Company, L.P. # Contributed by Stephane Eranian # # Permission is hereby granted, free of charge, to any person obtaining a copy # of this software and associated documentation files (the "Software"), to deal # in the Software without restriction, including without limitation the rights # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies # of the Software, and to permit persons to whom the Software is furnished to do so, # subject to the following conditions: # # The above copyright notice and this permission notice shall be included in all # copies or substantial portions of the Software. # # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, # INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A # PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT # HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF # CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE # OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # TOPDIR := $(shell if [ "$$PWD" != "" ]; then echo $$PWD; else pwd; fi)/../.. include $(TOPDIR)/config.mk include $(TOPDIR)/rules.mk CFLAGS+= -I. -D_GNU_SOURCE -I.. LIBS += -lm ifeq ($(SYS),Linux) CFLAGS+= -pthread endif TARGETS= ifeq ($(SYS),Linux) LPC_UTILS=../perf_util.o TARGETS += bts_smpl endif EXAMPLESDIR=$(DOCDIR)/perf_examples/x86 all: $(TARGETS) $(TARGETS): %:%.o $(LPC_UTILS) $(PFMLIB) $(CC) $(CFLAGS) -o $@ $(LDFLAGS) $^ $(LIBS) clean: $(RM) -f *.o $(TARGETS) *~ distclean: clean install_examples: $(TARGETS) @echo installing: $(TARGETS) -mkdir -p $(DESTDIR)$(EXAMPLESDIR) $(INSTALL) -m 755 $(TARGETS) $(TARGET_GEN) $(DESTDIR)$(EXAMPLESDIR) @set -e ; for d in $(DIRS) ; do $(MAKE) -C $$d $@ ; done .PHONY: install depend install_examples libpfm-4.9.0/perf_examples/x86/bts_smpl.c0000664000175000017500000001544413223402656020074 0ustar eranianeranian/* * bts_smpl.c - example of Intel Branch Trace Stack sampling * * Copyright (c) 2009 Google, Inc * Contributed by Stephane Eranian * * Based on: * Copyright (c) 2003-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "perf_util.h" #define SMPL_PERIOD 24000000ULL typedef struct { int opt_no_show; int opt_inherit; int mmap_pages; } options_t; static jmp_buf jbuf; static uint64_t collected_samples, lost_samples; static perf_event_desc_t *fds; static int num_fds; static options_t options; static struct option the_options[]={ { "help", 0, 0, 1}, { "no-show", 0, &options.opt_no_show, 1}, { 0, 0, 0, 0} }; static void cld_handler(int n) { longjmp(jbuf, 1); } int child(char **arg) { /* * force the task to stop before executing the first * user level instruction */ ptrace(PTRACE_TRACEME, 0, NULL, NULL); execvp(arg[0], arg); /* not reached */ return -1; } struct timeval last_read, this_read; static void process_smpl_buf(perf_event_desc_t *hw) { struct perf_event_header ehdr; int ret; for(;;) { ret = perf_read_buffer(hw, &ehdr, sizeof(ehdr)); if (ret) return; /* nothing to read */ switch(ehdr.type) { case PERF_RECORD_SAMPLE: perf_display_sample(fds, num_fds, hw - fds, &ehdr, stdout); collected_samples++; break; case PERF_RECORD_EXIT: display_exit(hw, stdout); break; case PERF_RECORD_LOST: display_lost(hw, fds, num_fds, stdout); break; case PERF_RECORD_THROTTLE: display_freq(1, hw, stdout); break; case PERF_RECORD_UNTHROTTLE: display_freq(0, hw, stdout); break; default: printf("unknown sample type %d sz=%d\n", ehdr.type, ehdr.size); perf_skip_buffer(hw, ehdr.size - sizeof(ehdr)); } } } int mainloop(char **arg) { static uint64_t ovfl_count; /* static to avoid setjmp issue */ struct pollfd pollfds[1]; size_t map_size = 0; sigset_t bmask; pid_t pid; uint64_t val[2]; int status, ret; if (pfm_initialize() != PFM_SUCCESS) errx(1, "libpfm initialization failed\n"); map_size = (options.mmap_pages+1)*getpagesize(); /* * does allocate fds */ ret = perf_setup_list_events("branches:u", &fds, &num_fds); if (ret || !num_fds) errx(1, "cannot setup event"); memset(pollfds, 0, sizeof(pollfds)); /* * Create the child task */ if ((pid=fork()) == -1) err(1, "cannot fork process\n"); if (pid == 0) exit(child(arg)); /* * wait for the child to exec */ ret = waitpid(pid, &status, WUNTRACED); if (ret == -1) err(1, "waitpid failed"); if (WIFEXITED(status)) errx(1, "task %s [%d] exited already status %d\n", arg[0], pid, WEXITSTATUS(status)); fds[0].fd = -1; fds[0].hw.disabled = 0; /* start immediately */ if (options.opt_inherit) fds[0].hw.inherit = 1; fds[0].hw.sample_type = PERF_SAMPLE_IP|PERF_SAMPLE_ADDR; /* * BTS only supported at user level */ if (fds[0].hw.exclude_user ||fds[0].hw.exclude_kernel == 0) errx(1, "BTS currently supported only at the user level\n"); /* * period MUST be one to trigger BTS: tracing not sampling anymore */ fds[0].hw.sample_period = 1; fds[0].hw.exclude_kernel = 1; fds[0].hw.exclude_hv = 1; fds[0].hw.read_format |= PERF_FORMAT_ID; fds[0].fd = perf_event_open(&fds[0].hw, pid, -1, -1, 0); if (fds[0].fd == -1) err(1, "cannot attach event %s", fds[0].name); fds[0].buf = mmap(NULL, map_size, PROT_READ|PROT_WRITE, MAP_SHARED, fds[0].fd, 0); if (fds[0].buf == MAP_FAILED) err(1, "cannot mmap buffer"); /* does not include header page */ fds[0].pgmsk = (options.mmap_pages*getpagesize())-1; ret = read(fds[0].fd, val, sizeof(val)); if (ret == -1) err(1, "cannot read id %zu", sizeof(val)); fds[0].id = val[1]; printf("%"PRIu64" %s\n", fds[0].id, fds[0].name); /* * effectively activate monitoring */ ptrace(PTRACE_DETACH, pid, NULL, 0); signal(SIGCHLD, cld_handler); pollfds[0].fd = fds[0].fd; pollfds[0].events = POLLIN; if (setjmp(jbuf) == 1) goto terminate_session; sigemptyset(&bmask); sigaddset(&bmask, SIGCHLD); /* * core loop */ for(;;) { ret = poll(pollfds, 1, -1); if (ret < 0 && errno == EINTR) break; ovfl_count++; ret = sigprocmask(SIG_SETMASK, &bmask, NULL); if (ret) err(1, "setmask"); process_smpl_buf(&fds[0]); ret = sigprocmask(SIG_UNBLOCK, &bmask, NULL); if (ret) err(1, "unblock"); } terminate_session: /* * cleanup child */ wait4(pid, &status, 0, NULL); close(fds[0].fd); /* check for partial event buffer */ process_smpl_buf(&fds[0]); munmap(fds[0].buf, map_size); free(fds); printf("%"PRIu64" samples collected in %"PRIu64" poll events, %"PRIu64" lost samples\n", collected_samples, ovfl_count, lost_samples); return 0; } static void usage(void) { printf("usage: bts_smpl [-h] [--help] [-i] [-m mmap_pages] cmd\n"); } int main(int argc, char **argv) { int c; while ((c=getopt_long(argc, argv,"+hm:p:if", the_options, 0)) != -1) { switch(c) { case 0: continue; case 'i': options.opt_inherit = 1; break; case 'm': if (options.mmap_pages) errx(1, "mmap pages already set\n"); options.mmap_pages = atoi(optarg); break; case 'h': usage(); exit(0); default: errx(1, "unknown option"); } } if (argv[optind] == NULL) errx(1, "you must specify a command to execute\n"); if (!options.mmap_pages) options.mmap_pages = 4; return mainloop(argv+optind); } libpfm-4.9.0/perf_examples/self_count.c0000664000175000017500000001405613223402656017763 0ustar eranianeranian/* * self_count.c - example of a simple self monitoring using mmapped page * * Copyright (c) 2009 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. */ #include #include #include #include #include #include #include #include #include #include #include #include #include "perf_util.h" static const char *gen_events[]={ "cycles", NULL }; static volatile int quit; void sig_handler(int n) { quit = 1; } #if defined(__x86_64__) || defined(__i386__) #ifdef __x86_64__ #define DECLARE_ARGS(val, low, high) unsigned low, high #define EAX_EDX_VAL(val, low, high) ((low) | ((uint64_t )(high) << 32)) #define EAX_EDX_ARGS(val, low, high) "a" (low), "d" (high) #define EAX_EDX_RET(val, low, high) "=a" (low), "=d" (high) #else #define DECLARE_ARGS(val, low, high) unsigned long long val #define EAX_EDX_VAL(val, low, high) (val) #define EAX_EDX_ARGS(val, low, high) "A" (val) #define EAX_EDX_RET(val, low, high) "=A" (val) #endif #define barrier() __asm__ __volatile__("": : :"memory") static inline int rdpmc(struct perf_event_mmap_page *hdr, uint64_t *value) { int counter = hdr->index - 1; DECLARE_ARGS(val, low, high); if (counter < 0) return -1; asm volatile("rdpmc" : EAX_EDX_RET(val, low, high) : "c" (counter)); *value = EAX_EDX_VAL(val, low, high); return 0; } #else /* * Default barrier macro. * Given this is architecture specific, it must be defined when * libpfm is ported to new architecture. The default macro below * simply does nothing. */ #define barrier() {} /* * Default function to read counter directly from user level mode. * Given this is architecture specific, it must be defined when * libpfm is ported to new architecture. The default routine below * simply fails and the caller falls backs to syscall. */ static inline int rdpmc(struct perf_event_mmap_page *hdr, uint64_t *value) { int counter = hdr->index - 1; if (counter < 0) return -1; printf("your architecture does not have a way to read counters from user mode\n"); return -1; } #endif /* * our test code (function cannot be made static otherwise it is optimized away) */ unsigned long fib(unsigned long n) { if (n == 0) return 0; if (n == 1) return 2; return fib(n-1)+fib(n-2); } uint64_t read_count(perf_event_desc_t *fds) { struct perf_event_mmap_page *hdr; uint64_t values[3]; uint64_t count = 0; uint32_t width; unsigned int seq; ssize_t ret; int idx = -1; hdr = fds->buf; width = hdr->pmc_width; do { seq = hdr->lock; barrier(); /* try reading directly from user mode */ if (!rdpmc(hdr, &values[0])) { values[1] = hdr->time_enabled; values[2] = hdr->time_running; ret = 0; } else { idx = -1; ret = read(fds->fd, values, sizeof(values)); if (ret < (ssize_t)sizeof(values)) errx(1, "cannot read values"); printf("using read\n"); break; } barrier(); } while (hdr->lock != seq); printf("raw=0x%"PRIx64 " width=%d ena=%"PRIu64 " run=%"PRIu64" idx=%d\n", values[0], width, values[1], values[2], idx); count = values[0]; count <<= 64 - width; count >>= 64 - width; values[0] = count; return perf_scale(values); } int main(int argc, char **argv) { perf_event_desc_t *fds = NULL; long lret; size_t pgsz; uint64_t val, prev_val; int i, ret, num_fds = 0; lret = sysconf(_SC_PAGESIZE); if (lret < 0) err(1, "cannot get page size"); pgsz = (size_t)lret; /* * Initialize pfm library (required before we can use it) */ ret = pfm_initialize(); if (ret != PFM_SUCCESS) errx(1, "Cannot initialize library: %s", pfm_strerror(ret)); ret = perf_setup_argv_events(argc > 1 ? (const char **)argv+1 : gen_events, &fds, &num_fds); if (ret || !num_fds) errx(1, "cannot setup events"); fds[0].fd = -1; for(i=0; i < num_fds; i++) { /* request timing information necesaary for scaling */ fds[i].hw.read_format = PERF_FORMAT_SCALE; fds[i].hw.disabled = 0; //fds[i].fd = perf_event_open(&fds[i].hw, 0, -1, fds[0].fd, 0); fds[i].fd = perf_event_open(&fds[i].hw, 0, -1, -1, 0); if (fds[i].fd == -1) err(1, "cannot open event %d", i); fds[i].buf = mmap(NULL, pgsz, PROT_READ, MAP_SHARED, fds[i].fd, 0); if (fds[i].buf == MAP_FAILED) err(1, "cannot mmap page"); } signal(SIGALRM, sig_handler); /* * enable all counters attached to this thread */ ioctl(fds[0].fd, PERF_EVENT_IOC_ENABLE, 0); alarm(10); prev_val = 0; for(;quit == 0;) { for (i = 0; i < num_fds; i++) { val = read_count(&fds[i]); /* print evnet deltas */ printf("%20"PRIu64" %s\n", val - prev_val, fds[i].name); prev_val = val; } fib(35); } /* * disable all counters attached to this thread */ ioctl(fds[0].fd, PERF_EVENT_IOC_DISABLE, 0); for (i=0; i < num_fds; i++) { munmap(fds[i].buf, pgsz); close(fds[i].fd); } perf_free_fds(fds, num_fds); /* free libpfm resources cleanly */ pfm_terminate(); return 0; } libpfm-4.9.0/perf_examples/syst_smpl.c0000775000175000017500000002332413223402656017660 0ustar eranianeranian/* * syst_smpl.c - example of a system-wide sampling * * Copyright (c) 2010 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "perf_util.h" #define SMPL_PERIOD 240000000ULL #define MAX_PATH 1024 #ifndef STR # define _STR(x) #x # define STR(x) _STR(x) #endif typedef struct { int opt_no_show; int mmap_pages; int cpu; int pin; int delay; char *events; char *cgroup; } options_t; static jmp_buf jbuf; static uint64_t collected_samples, lost_samples; static perf_event_desc_t *fds; static int num_fds; static options_t options; static size_t pgsz; static size_t map_size; static struct option the_options[]={ { "help", 0, 0, 1}, { "no-show", 0, &options.opt_no_show, 1}, { 0, 0, 0, 0} }; static const char *gen_events = "cycles,instructions"; static void process_smpl_buf(perf_event_desc_t *hw) { struct perf_event_header ehdr; int ret; for(;;) { ret = perf_read_buffer(hw, &ehdr, sizeof(ehdr)); if (ret) return; /* nothing to read */ switch(ehdr.type) { case PERF_RECORD_SAMPLE: ret = perf_display_sample(fds, num_fds, hw - fds, &ehdr, stdout); if (ret) errx(1, "cannot parse sample"); collected_samples++; break; case PERF_RECORD_EXIT: display_exit(hw, stdout); break; case PERF_RECORD_LOST: lost_samples += display_lost(hw, fds, num_fds, stdout); break; case PERF_RECORD_THROTTLE: display_freq(1, hw, stdout); break; case PERF_RECORD_UNTHROTTLE: display_freq(0, hw, stdout); break; default: printf("unknown sample type %d\n", ehdr.type); perf_skip_buffer(hw, ehdr.size - sizeof(ehdr)); } } } int setup_cpu(int cpu, int fd) { int ret, flags; int i, pid; /* * does allocate fds */ ret = perf_setup_list_events(options.events, &fds, &num_fds); if (ret || !num_fds) errx(1, "cannot setup event list"); if (!fds[0].hw.sample_period) errx(1, "need to set sampling period or freq on first event, use :period= or :freq="); fds[0].fd = -1; for(i=0; i < num_fds; i++) { fds[i].hw.disabled = !i; /* start immediately */ if (options.cgroup) { flags = PERF_FLAG_PID_CGROUP; pid = fd; } else { flags = 0; pid = -1; } if (options.pin) fds[i].hw.pinned = 1; if (fds[i].hw.sample_period) { /* * set notification threshold to be halfway through the buffer */ if (fds[i].hw.sample_period) { fds[i].hw.wakeup_watermark = (options.mmap_pages*pgsz) / 2; fds[i].hw.watermark = 1; } fds[i].hw.sample_type = PERF_SAMPLE_IP|PERF_SAMPLE_TID|PERF_SAMPLE_READ|PERF_SAMPLE_TIME|PERF_SAMPLE_PERIOD|PERF_SAMPLE_STREAM_ID|PERF_SAMPLE_CPU; /* * if we have more than one event, then record event identifier to help with parsing */ if (num_fds > 1) fds[i].hw.sample_type |= PERF_SAMPLE_IDENTIFIER; printf("%s period=%"PRIu64" freq=%d\n", fds[i].name, fds[i].hw.sample_period, fds[i].hw.freq); fds[i].hw.read_format = PERF_FORMAT_SCALE; if (fds[i].hw.freq) fds[i].hw.sample_type |= PERF_SAMPLE_PERIOD; } fds[i].fd = perf_event_open(&fds[i].hw, pid, cpu, fds[0].fd, flags); if (fds[i].fd == -1) { if (fds[i].hw.precise_ip) err(1, "cannot attach event %s: precise mode may not be supported", fds[i].name); err(1, "cannot attach event %s", fds[i].name); } } /* * kernel adds the header page to the size of the mmapped region */ fds[0].buf = mmap(NULL, map_size, PROT_READ|PROT_WRITE, MAP_SHARED, fds[0].fd, 0); if (fds[0].buf == MAP_FAILED) err(1, "cannot mmap buffer"); /* does not include header page */ fds[0].pgmsk = (options.mmap_pages*pgsz)-1; /* * send samples for all events to first event's buffer */ for (i = 1; i < num_fds; i++) { if (!fds[i].hw.sample_period) continue; ret = ioctl(fds[i].fd, PERF_EVENT_IOC_SET_OUTPUT, fds[0].fd); if (ret) err(1, "cannot redirect sampling output"); } /* * collect event ids */ if (num_fds > 1 && fds[0].fd > -1) { for(i = 0; i < num_fds; i++) { /* * read the event identifier using ioctl * new method replaced the trick with PERF_FORMAT_GROUP + PERF_FORMAT_ID + read() */ ret = ioctl(fds[i].fd, PERF_EVENT_IOC_ID, &fds[i].id); if (ret == -1) err(1, "cannot read ID"); printf("ID %"PRIu64" %s\n", fds[i].id, fds[i].name); } } return 0; } static void start_cpu(void) { int ret; ret = ioctl(fds[0].fd, PERF_EVENT_IOC_ENABLE, 0); if (ret) err(1, "cannot start counter"); } static int cgroupfs_find_mountpoint(char *buf, size_t maxlen) { FILE *fp; char mountpoint[MAX_PATH+1], tokens[MAX_PATH+1], type[MAX_PATH+1]; char *token, *saved_ptr = NULL; int found = 0; fp = fopen("/proc/mounts", "r"); if (!fp) return -1; /* * in order to handle split hierarchy, we need to scan /proc/mounts * and inspect every cgroupfs mount point to find one that has * perf_event subsystem */ while (fscanf(fp, "%*s %"STR(MAX_PATH)"s %"STR(MAX_PATH)"s %" STR(MAX_PATH)"s %*d %*d\n", mountpoint, type, tokens) == 3) { if (!strcmp(type, "cgroup")) { token = strtok_r(tokens, ",", &saved_ptr); while (token != NULL) { if (!strcmp(token, "perf_event")) { found = 1; break; } token = strtok_r(NULL, ",", &saved_ptr); } } if (found) break; } fclose(fp); if (!found) return -1; if (strlen(mountpoint) < maxlen) { strcpy(buf, mountpoint); return 0; } return -1; } int open_cgroup(char *name) { char path[MAX_PATH+1]; char mnt[MAX_PATH+1]; int cfd; if (cgroupfs_find_mountpoint(mnt, MAX_PATH+1)) errx(1, "cannot find cgroup fs mount point"); snprintf(path, MAX_PATH, "%s/%s", mnt, name); cfd = open(path, O_RDONLY); if (cfd == -1) warn("no access to cgroup %s\n", name); return cfd; } static void handler(int n) { longjmp(jbuf, 1); } int mainloop(char **arg) { static uint64_t ovfl_count = 0; /* static to avoid setjmp issue */ struct pollfd pollfds[1]; int ret; int fd = -1; int i; if (pfm_initialize() != PFM_SUCCESS) errx(1, "libpfm initialization failed\n"); pgsz = sysconf(_SC_PAGESIZE); map_size = (options.mmap_pages+1)*pgsz; if (options.cgroup) { fd = open_cgroup(options.cgroup); if (fd == -1) err(1, "cannot open cgroup file %s\n", options.cgroup); } setup_cpu(options.cpu, fd); /* done with cgroup */ if (fd != -1) close(fd); signal(SIGALRM, handler); signal(SIGINT, handler); pollfds[0].fd = fds[0].fd; pollfds[0].events = POLLIN; printf("monitoring on CPU%d, session ending in %ds\n", options.cpu, options.delay); if (setjmp(jbuf) == 1) goto terminate_session; start_cpu(); alarm(options.delay); /* * core loop */ for(;;) { ret = poll(pollfds, 1, -1); if (ret < 0 && errno == EINTR) break; ovfl_count++; process_smpl_buf(&fds[0]); } terminate_session: for(i=0; i < num_fds; i++) close(fds[i].fd); /* check for partial event buffer */ process_smpl_buf(&fds[0]); munmap(fds[0].buf, map_size); perf_free_fds(fds, num_fds); printf("%"PRIu64" samples collected in %"PRIu64" poll events, %"PRIu64" lost samples\n", collected_samples, ovfl_count, lost_samples); return 0; } static void usage(void) { printf("usage: syst_smpl [-h] [-P] [--help] [-m mmap_pages] [-f] [-e event1,...,eventn] [-c cpu] [-d seconds]\n"); } int main(int argc, char **argv) { int c; setlocale(LC_ALL, ""); options.cpu = -1; options.delay = -1; while ((c=getopt_long(argc, argv,"hPe:m:c:d:G:", the_options, 0)) != -1) { switch(c) { case 0: continue; case 'e': if (options.events) errx(1, "events specified twice\n"); options.events = optarg; break; case 'm': if (options.mmap_pages) errx(1, "mmap pages already set\n"); options.mmap_pages = atoi(optarg); break; case 'P': options.pin = 1; break; case 'd': options.delay = atoi(optarg); break; case 'G': options.cgroup = optarg; break; case 'c': options.cpu = atoi(optarg); break; case 'h': usage(); exit(0); default: errx(1, "unknown option"); } } if (!options.events) options.events = strdup(gen_events); if (!options.mmap_pages) options.mmap_pages = 1; if (options.cpu == -1) options.cpu = random() % sysconf(_SC_NPROCESSORS_ONLN); if (options.delay == -1) options.delay = 10; if (options.mmap_pages > 1 && ((options.mmap_pages) & 0x1)) errx(1, "number of pages must be power of 2\n"); return mainloop(argv+optind); } libpfm-4.9.0/perf_examples/self_smpl_multi.c0000664000175000017500000002642413223402656021022 0ustar eranianeranian/* * * self_smpl_multi.c - multi-thread self-sampling program * * Copyright (c) 2009 Google, Inc * Modified by Stephane Eranian * * Based on: * Copyright (c) 2008 Mark W. Krentel * Contributed by Mark W. Krentel * Modified by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. * * Test perfmon overflow without PAPI. * * Create a new thread, launch perfmon overflow counters in both * threads, print the number of interrupts per thread and per second, * and look for anomalous interrupts. Look for mismatched thread * ids, bad message type, or failed pfm_restart(). * * self_smpl_multi is a test program to stress signal delivery in the context * of a multi-threaded self-sampling program which is common with PAPI and HPC. * * There is an issue with existing (as of 2.6.30) kernel which do not provide * a reliable way of having the signal delivered to the thread in which the * counter overflow occurred. This is problematic for many self-monitoring * program. * * This program demonstrates the issue by tracking the number of times * the signal goes to the wrong thread. The bad behavior is exacerbated * if the monitored threads, themselves, already use signals. Here we * use SIGLARM. * * Note that kernel developers have been made aware of this problem and * a fix has been proposed. It introduces a new F_SETOWN_EX command to * fcntl(). */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "perf_util.h" #define PROGRAM_TIME 8 #define THRESHOLD 20000000 static int program_time = PROGRAM_TIME; static int threshold = THRESHOLD; static int signum = SIGIO; static pthread_barrier_t barrier; static int buffer_pages = 1; #define MAX_THR 128 /* * the following definitions come * from the F_SETOWN_EX patch from Peter Zijlstra * Check out: http://lkml.org/lkml/2009/8/4/128 */ #ifndef F_SETOWN_EX #define F_SETOWN_EX 15 #define F_GETOWN_EX 16 #define F_OWNER_TID 0 #define F_OWNER_PID 1 #define F_OWNER_PGRP 2 struct f_owner_ex { int type; pid_t pid; }; #endif struct over_args { int fd; pid_t tid; int id; perf_event_desc_t *fds; }; struct over_args fd2ov[MAX_THR]; long count[MAX_THR]; long total[MAX_THR]; long iter[MAX_THR]; long mismatch[MAX_THR]; long bad_msg[MAX_THR]; long bad_restart[MAX_THR]; int fown; static __thread int myid; /* TLS */ static __thread perf_event_desc_t *fds; /* TLS */ static __thread int num_fds; /* TLS */ pid_t gettid(void) { return (pid_t)syscall(__NR_gettid); } void user_callback(int m) { count[m]++; total[m]++; } void do_cycles(void) { struct timeval start, last, now; unsigned long x, sum; gettimeofday(&start, NULL); last = start; count[myid] = 0; total[myid] = 0; iter[myid] = 0; do { sum = 1; for (x = 1; x < 250000; x++) { /* signal pending to private queue because of * pthread_kill(), i.e., tkill() */ if ((x % 5000) == 0) pthread_kill(pthread_self(), SIGUSR1); sum += x; } iter[myid]++; gettimeofday(&now, NULL); if (now.tv_sec > last.tv_sec) { printf("%ld: myid = %3d, fd = %3d, count = %4ld, iter = %4ld, rate = %ld/Kiter\n", (long)(now.tv_sec - start.tv_sec), myid, fd2ov[myid].fd, count[myid], iter[myid], (1000 * count[myid])/iter[myid]); count[myid] = 0; iter[myid] = 0; last = now; } } while (now.tv_sec < start.tv_sec + program_time); } #define DPRINT(str) \ printf("(%s) si->fd = %d, ov->self = 0x%lx, self = 0x%lx\n", \ str, fd, (unsigned long)ov->self, (unsigned long)self) void sigusr1_handler(int sig, siginfo_t *info, void *context) { } /* * a signal handler cannot safely invoke printf() */ void sigio_handler(int sig, siginfo_t *info, void *context) { perf_event_desc_t *fdx; struct perf_event_header ehdr; struct over_args *ov; int fd, i, ret; pid_t tid; /* * positive si_code indicate kernel generated signal * which is normal for SIGIO */ if (info->si_code < 0) errx(1, "signal not generated by kernel"); /* * SIGPOLL = SIGIO * expect POLL_HUP instead of POLL_IN because we are * in one-shot mode (IOC_REFRESH) */ if (info->si_code != POLL_HUP) errx(1, "signal not generated by SIGIO: %d", info->si_code); fd = info->si_fd; tid = gettid(); for(i=0; i < MAX_THR; i++) if (fd2ov[i].fd == fd) break; if (i == MAX_THR) errx(1, "bad info.si_fd: %d", fd); ov = &fd2ov[i]; /* * current thread id may not always match the id * associated with the file descriptor * * We need to use the other's thread fds info * otherwise, it is going to get stuck with no * more samples generated */ if (tid != ov->tid) { mismatch[myid]++; fdx = ov->fds; } else { fdx = fds; } /* * read sample header */ ret = perf_read_buffer(fdx+0, &ehdr, sizeof(ehdr)); if (ret) { errx(1, "cannot read event header"); } /* * message we do not handle */ if (ehdr.type != PERF_RECORD_SAMPLE) { bad_msg[myid]++; goto skip; } user_callback(myid); skip: /* mark sample as consumed */ perf_skip_buffer(fdx+0, ehdr.size); /* * re-arm period, next notification after wakeup_events */ ret = ioctl(fd, PERF_EVENT_IOC_REFRESH, 1); if (ret) err(1, "cannot refresh"); } void overflow_start(char *name) { struct f_owner_ex fown_ex; struct over_args *ov; size_t pgsz; int ret, fd, flags; fds = NULL; num_fds = 0; ret = perf_setup_list_events("cycles", &fds, &num_fds); if (ret || !num_fds) errx(1, "cannot monitor event"); pgsz = sysconf(_SC_PAGESIZE); ov = &fd2ov[myid]; /* do not enable now */ fds[0].hw.disabled = 1; /* notify after 1 sample */ fds[0].hw.wakeup_events = 1; fds[0].hw.sample_type = PERF_SAMPLE_IP; fds[0].hw.sample_period = threshold; fds[0].hw.read_format = 0; fds[0].fd = fd = perf_event_open(&fds[0].hw, gettid(), -1, -1, 0); if (fd == -1) err(1, "cannot attach event %s", fds[0].name); ov->fd = fd; ov->tid = gettid(); ov->id = myid; ov->fds = fds; flags = fcntl(fd, F_GETFL, 0); if (fcntl(fd, F_SETFL, flags | O_ASYNC) < 0) err(1, "fcntl SETFL failed"); fown_ex.type = F_OWNER_TID; fown_ex.pid = gettid(); ret = fcntl(fd, (fown ? F_SETOWN_EX : F_SETOWN), (fown ? (unsigned long)&fown_ex: (unsigned long)gettid())); if (ret) err(1, "fcntl SETOWN failed"); if (fcntl(fd, F_SETSIG, signum) < 0) err(1, "fcntl SETSIG failed"); fds[0].buf = mmap(NULL, (buffer_pages + 1)* pgsz, PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0); if (fds[0].buf == MAP_FAILED) err(1, "cannot mmap buffer"); fds[0].pgmsk = (buffer_pages * pgsz) - 1; printf("launch %s: fd: %d, tid: %d\n", name, fd, ov->tid); /* * activate event for wakeup_events (samples) */ ret = ioctl(fd, PERF_EVENT_IOC_REFRESH , 1); if (ret == -1) err(1, "cannot refresh"); } void overflow_stop(void) { int ret; ret = ioctl(fd2ov[myid].fd, PERF_EVENT_IOC_DISABLE, 0); if (ret) err(1, "cannot stop"); } void * my_thread(void *v) { int retval = 0; myid = (unsigned long)v; pthread_barrier_wait(&barrier); overflow_start("side"); do_cycles(); overflow_stop(); perf_free_fds(fds, num_fds); pthread_exit((void *)&retval); } static void usage(void) { printf("self_smpl_multi [-t secs] [-p period] [-s signal] [-f] [-n threads]\n" "-t secs: duration of the run in seconds\n" "-p period: sampling period in CPU cycles\n" "-s signal: signal to use (default: SIGIO)\n" "-n thread: number of threads to create (default: 1)\n" "-f : use F_SETOWN_EX for correct delivery of signal to thread (default: off)\n"); } /* * Program args: program_time, threshold, signum. */ int main(int argc, char **argv) { struct sigaction sa; pthread_t allthr[MAX_THR]; sigset_t set, old, new; int i, ret, max_thr = 1; while ((i=getopt(argc, argv, "t:p:s:fhn:")) != EOF) { switch(i) { case 'h': usage(); return 0; case 't': program_time = atoi(optarg); break; case 'p': threshold = atoi(optarg); break; case 's': signum = atoi(optarg); break; case 'f': fown = 1; break; case 'n': max_thr = atoi(optarg); if (max_thr >= MAX_THR) errx(1, "no more than %d threads", MAX_THR); break; default: errx(1, "invalid option"); } } printf("program_time = %d, threshold = %d, signum = %d fcntl(%s), threads = %d\n", program_time, threshold, signum, fown ? "F_SETOWN_EX" : "F_SETOWN", max_thr); for (i = 0; i < MAX_THR; i++) { mismatch[i] = 0; bad_msg[i] = 0; bad_restart[i] = 0; } memset(&sa, 0, sizeof(sa)); sigemptyset(&set); sa.sa_sigaction = sigusr1_handler; sa.sa_mask = set; sa.sa_flags = SA_SIGINFO; if (sigaction(SIGUSR1, &sa, NULL) != 0) errx(1, "sigaction failed"); memset(&sa, 0, sizeof(sa)); sigemptyset(&set); sa.sa_sigaction = sigio_handler; sa.sa_mask = set; sa.sa_flags = SA_SIGINFO; if (sigaction(signum, &sa, NULL) != 0) errx(1, "sigaction failed"); if (pfm_initialize() != PFM_SUCCESS) errx(1, "pfm_initialize failed"); /* * +1 because main thread is also using the barrier */ pthread_barrier_init(&barrier, 0, max_thr+1); for(i=0; i < max_thr; i++) { ret = pthread_create(allthr+i, NULL, my_thread, (void *)(unsigned long)i); if (ret) err(1, "pthread_create failed"); } myid = i; sigemptyset(&set); sigemptyset(&new); sigaddset(&set, SIGIO); sigaddset(&new, SIGIO); if (pthread_sigmask(SIG_BLOCK, &set, NULL)) err(1, "cannot mask SIGIO in main thread"); ret = sigprocmask(SIG_SETMASK, NULL, &old); if (ret) err(1, "sigprocmask failed"); if (sigismember(&old, SIGIO)) { warnx("program started with SIGIO masked, unmasking it now\n"); ret = sigprocmask(SIG_UNBLOCK, &new, NULL); if (ret) err(1, "sigprocmask failed"); } pthread_barrier_wait(&barrier); printf("\n\n"); for (i = 0; i < max_thr; i++) { pthread_join(allthr[i], NULL); } printf("\n\n"); for (i = 0; i < max_thr; i++) { printf("myid = %3d, fd = %3d, total = %4ld, mismatch = %ld, " "bad_msg = %ld, bad_restart = %ld\n", fd2ov[i].id, fd2ov[i].fd, total[i], mismatch[i], bad_msg[i], bad_restart[i]); } /* free libpfm resources cleanly */ pfm_terminate(); return (0); } libpfm-4.9.0/perf_examples/task_attach_timeout.c0000664000175000017500000001165013223402656021653 0ustar eranianeranian/* * task_attach_timeout.c - attach to another task for monitoring for a short while * * Copyright (c) 2009 Google, Inc * Contributed by Stephane Eranian * * Based on: * Copyright (c) 2002-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include #include #include #include #include #include #include #include #include "perf_util.h" typedef struct { char *events; int delay; int print; int group; int pinned; } options_t; static options_t options; static void print_counts(perf_event_desc_t *fds, int num, int do_delta) { ssize_t ret; int i; /* * now simply read the results. */ for(i=0; i < num; i++) { uint64_t val; double ratio; ret = read(fds[i].fd, fds[i].values, sizeof(fds[i].values)); if (ret < (ssize_t)sizeof(fds[i].values)) { if (ret == -1) err(1, "cannot read values event %s", fds[i].name); else warnx("could not read event%d", i); } val = perf_scale(fds[i].values); ratio = perf_scale_ratio(fds[i].values); val = do_delta ? perf_scale_delta(fds[i].values, fds[i].prev_values) : val; fds[i].prev_values[0] = fds[i].values[0]; fds[i].prev_values[1] = fds[i].values[1]; fds[i].prev_values[2] = fds[i].values[2]; if (ratio == 1.0) printf("%20"PRIu64" %s\n", val, fds[i].name); else if (ratio == 0.0) printf("%20"PRIu64" %s (did not run: incompatible events, too many events in a group, competing session)\n", val, fds[i].name); else printf("%20"PRIu64" %s (scaled from %.2f%% of time)\n", val, fds[i].name, ratio*100.0); } } int measure(pid_t pid) { perf_event_desc_t *fds = NULL; int i, ret, num_fds = 0; char fn[32]; if (pfm_initialize() != PFM_SUCCESS) errx(1, "libpfm initialization failed\n"); ret = perf_setup_list_events(options.events, &fds, &num_fds); if (ret || (num_fds == 0)) exit(1); fds[0].fd = -1; for(i=0; i < num_fds; i++) { fds[i].hw.disabled = 0; /* start immediately */ /* request timing information necessary for scaling counts */ fds[i].hw.read_format = PERF_FORMAT_SCALE; fds[i].hw.pinned = !i && options.pinned; fds[i].fd = perf_event_open(&fds[i].hw, pid, -1, (options.group? fds[0].fd : -1), 0); if (fds[i].fd == -1) errx(1, "cannot attach event %s", fds[i].name); } /* * no notification is generated by perf_counters * when the monitored thread exits. Thus we need * to poll /proc/ to detect it has disappeared, * otherwise we have to wait until the end of the * timeout */ sprintf(fn, "/proc/%d/status", pid); while(access(fn, F_OK) == 0 && options.delay) { sleep(1); options.delay--; if (options.print) print_counts(fds, num_fds, 1); } if (options.delay) warn("thread %d terminated before timeout", pid); if (!options.print) print_counts(fds, num_fds, 0); for(i=0; i < num_fds; i++) close(fds[i].fd); perf_free_fds(fds, num_fds); /* free libpfm resources cleanly */ pfm_terminate(); return 0; } static void usage(void) { printf("usage: task_attach_timeout [-h] [-p] [-P] [-g] [-d delay] [-e event1,event2,...] pid\n"); } int main(int argc, char **argv) { int c; while ((c=getopt(argc, argv,"he:vd:pgP")) != -1) { switch(c) { case 'e': options.events = optarg; break; case 'p': options.print = 1; break; case 'P': options.pinned = 1; break; case 'g': options.group = 1; break; case 'd': options.delay = atoi(optarg); break; case 'h': usage(); exit(0); default: errx(1, "unknown error"); } } if (!options.events) options.events = strdup("cycles,instructions"); if (options.delay < 1) options.delay = 10; if (!argv[optind]) errx(1, "you must specify pid to attach to\n"); return measure(atoi(argv[optind])); } libpfm-4.9.0/perf_examples/branch_smpl.c0000664000175000017500000002636413223402656020117 0ustar eranianeranian/* * branch_smpl.c - example of a branch sampling on another task * * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "perf_util.h" #define DFL_BR_EVENT "branches:freq=100" typedef struct { int opt_no_show; int opt_inherit; uint64_t branch_filt; int cpu; int mmap_pages; char *events; FILE *output_file; } options_t; static jmp_buf jbuf; static uint64_t collected_samples, lost_samples; static perf_event_desc_t *fds; static int num_fds; static options_t options; static void cld_handler(int n) { longjmp(jbuf, 1); } int child(char **arg) { execvp(arg[0], arg); /* not reached */ return -1; } struct timeval last_read, this_read; static void process_smpl_buf(perf_event_desc_t *hw) { struct perf_event_header ehdr; int ret; for(;;) { ret = perf_read_buffer(hw, &ehdr, sizeof(ehdr)); if (ret) return; /* nothing to read */ if (options.opt_no_show) { perf_skip_buffer(hw, ehdr.size - sizeof(ehdr)); continue; } switch(ehdr.type) { case PERF_RECORD_SAMPLE: collected_samples++; ret = perf_display_sample(fds, num_fds, hw - fds, &ehdr, options.output_file); if (ret) errx(1, "cannot parse sample"); break; case PERF_RECORD_EXIT: display_exit(hw, options.output_file); break; case PERF_RECORD_LOST: lost_samples += display_lost(hw, fds, num_fds, options.output_file); break; case PERF_RECORD_THROTTLE: display_freq(1, hw, options.output_file); break; case PERF_RECORD_UNTHROTTLE: display_freq(0, hw, options.output_file); break; default: printf("unknown sample type %d\n", ehdr.type); perf_skip_buffer(hw, ehdr.size - sizeof(ehdr)); } } } int mainloop(char **arg) { static uint64_t ovfl_count; /* static to avoid setjmp issue */ struct pollfd pollfds[1]; sigset_t bmask; int go[2], ready[2]; size_t pgsz; size_t map_size = 0; pid_t pid; int status, ret; int i; char buf; if (pfm_initialize() != PFM_SUCCESS) errx(1, "libpfm initialization failed\n"); pgsz = sysconf(_SC_PAGESIZE); map_size = (options.mmap_pages+1)*pgsz; /* * does allocate fds */ ret = perf_setup_list_events(options.events, &fds, &num_fds); if (ret || !num_fds) errx(1, "cannot setup event list"); memset(pollfds, 0, sizeof(pollfds)); ret = pipe(ready); if (ret) err(1, "cannot create pipe ready"); ret = pipe(go); if (ret) err(1, "cannot create pipe go"); /* * Create the child task */ if ((pid=fork()) == -1) err(1, "cannot fork process\n"); if (pid == 0) { close(ready[0]); close(go[1]); /* * let the parent know we exist */ close(ready[1]); if (read(go[0], &buf, 1) == -1) err(1, "unable to read go_pipe"); exit(child(arg)); } close(ready[1]); close(go[0]); if (read(ready[0], &buf, 1) == -1) err(1, "unable to read child_ready_pipe"); close(ready[0]); fds[0].fd = -1; if (!fds[0].hw.sample_period) errx(1, "need to set sampling period or freq on first event, use :period= or :freq="); for(i=0; i < num_fds; i++) { if (i == 0) { fds[i].hw.disabled = 1; fds[i].hw.enable_on_exec = 1; /* start immediately */ } else fds[i].hw.disabled = 0; if (options.opt_inherit) fds[i].hw.inherit = 1; if (fds[i].hw.sample_period) { /* * set notification threshold to be halfway through the buffer */ fds[i].hw.wakeup_watermark = (options.mmap_pages*pgsz) / 2; fds[i].hw.watermark = 1; fds[i].hw.sample_type = PERF_SAMPLE_IP|PERF_SAMPLE_TID|PERF_SAMPLE_READ|PERF_SAMPLE_TIME|PERF_SAMPLE_PERIOD; /* * if we have more than one event, then record event identifier to help with parsing */ if (num_fds > 1) fds[i].hw.sample_type |= PERF_SAMPLE_IDENTIFIER; fprintf(options.output_file,"%s period=%"PRIu64" freq=%d\n", fds[i].name, fds[i].hw.sample_period, fds[i].hw.freq); fds[i].hw.read_format = PERF_FORMAT_SCALE; if (fds[i].hw.freq) fds[i].hw.sample_type |= PERF_SAMPLE_PERIOD; fds[i].hw.sample_type = PERF_SAMPLE_BRANCH_STACK; fds[i].hw.branch_sample_type = options.branch_filt; } /* * we are grouping the events, so there may be a limit */ fds[i].fd = perf_event_open(&fds[i].hw, pid, options.cpu, fds[0].fd, 0); if (fds[i].fd == -1) { if (fds[i].hw.precise_ip) err(1, "cannot attach event %s: precise mode may not be supported", fds[i].name); err(1, "cannot attach event %s", fds[i].name); } } /* * kernel adds the header page to the size of the mmapped region */ fds[0].buf = mmap(NULL, map_size, PROT_READ|PROT_WRITE, MAP_SHARED, fds[0].fd, 0); if (fds[0].buf == MAP_FAILED) err(1, "cannot mmap buffer"); /* does not include header page */ fds[0].pgmsk = (options.mmap_pages*pgsz)-1; /* * send samples for all events to first event's buffer */ for (i = 1; i < num_fds; i++) { if (!fds[i].hw.sample_period) continue; ret = ioctl(fds[i].fd, PERF_EVENT_IOC_SET_OUTPUT, fds[0].fd); if (ret) err(1, "cannot redirect sampling output"); } if (num_fds > 1 && fds[0].fd > -1) { for(i = 0; i < num_fds; i++) { /* * read the event identifier using ioctl * new method replaced the trick with PERF_FORMAT_GROUP + PERF_FORMAT_ID + read() */ ret = ioctl(fds[i].fd, PERF_EVENT_IOC_ID, &fds[i].id); if (ret == -1) err(1, "cannot read ID"); fprintf(options.output_file,"ID %"PRIu64" %s\n", fds[i].id, fds[i].name); } } pollfds[0].fd = fds[0].fd; pollfds[0].events = POLLIN; for(i=0; i < num_fds; i++) { ret = ioctl(fds[i].fd, PERF_EVENT_IOC_ENABLE, 0); if (ret) err(1, "cannot enable event %s\n", fds[i].name); } signal(SIGCHLD, cld_handler); close(go[1]); if (setjmp(jbuf) == 1) goto terminate_session; sigemptyset(&bmask); sigaddset(&bmask, SIGCHLD); /* * core loop */ for(;;) { ret = poll(pollfds, 1, -1); if (ret < 0 && errno == EINTR) break; ovfl_count++; ret = sigprocmask(SIG_SETMASK, &bmask, NULL); if (ret) err(1, "setmask"); process_smpl_buf(&fds[0]); ret = sigprocmask(SIG_UNBLOCK, &bmask, NULL); if (ret) err(1, "unblock"); } terminate_session: /* * cleanup child */ wait4(pid, &status, 0, NULL); for(i=0; i < num_fds; i++) close(fds[i].fd); /* check for partial event buffer */ process_smpl_buf(&fds[0]); munmap(fds[0].buf, map_size); perf_free_fds(fds, num_fds); fprintf(options.output_file, "%"PRIu64" samples collected in %"PRIu64" poll events, %"PRIu64" lost samples\n", collected_samples, ovfl_count, lost_samples); /* free libpfm resources cleanly */ pfm_terminate(); fclose(options.output_file); return 0; } typedef struct { const char *filt; const int flag; } branch_filt_t; #define FILT(a, b) { .filt = a, .flag = b } static const branch_filt_t br_filters[] = { /* priv level filters */ FILT("u", PERF_SAMPLE_BRANCH_USER), FILT("k", PERF_SAMPLE_BRANCH_KERNEL), FILT("hv", PERF_SAMPLE_BRANCH_HV), FILT("any", PERF_SAMPLE_BRANCH_ANY), FILT("call", PERF_SAMPLE_BRANCH_ANY_CALL), FILT("return", PERF_SAMPLE_BRANCH_ANY_RETURN), FILT("indirect", PERF_SAMPLE_BRANCH_IND_CALL), FILT("conditional", PERF_SAMPLE_BRANCH_COND), FILT("indirect_jump", PERF_SAMPLE_BRANCH_IND_JUMP), FILT(NULL, 0), }; static void parse_branch_arg(const char *arg) { const branch_filt_t *br; char *q, *p, *str; if (!arg) { options.branch_filt = PERF_SAMPLE_BRANCH_ANY; return; } str = q = strdup(arg); if (!str) err(1, "cannot allocate memory to dup string"); while (*q) { p = strchr(q, ','); if (p) *p = '\0'; for (br = br_filters; br->filt; br++) { if (!strcasecmp(q, br->filt)) options.branch_filt |= br->flag; } if (!br->filt) errx(1, "unknown branch filter %s", q); if (!p) break; str = p + 1; } free(str); #define BR_PLM (PERF_SAMPLE_BRANCH_USER|PERF_SAMPLE_BRANCH_KERNEL|PERF_SAMPLE_BRANCH_HV) if (!(options.branch_filt & ~BR_PLM)) errx(1, "no branch mode specified, privilege level does not define a branch type, use the any filter"); } static void usage(void) { printf("usage: branch_smpl [-h] [--help] [-i] [-c cpu] [-m mmap_pages] [-b] [-j br-filt] [-o output_file] [-e event1] cmd\n" "\t-j br-filt\t : comma separated list of branch filters among: u, k, any, call, returrn, indirect, conditional, indirect_jmp\n" "\t-b\t\t : sample any branch (equivalent to -j any), default mode\n"); } int main(int argc, char **argv) { int c; setlocale(LC_ALL, ""); options.cpu = -1; options.output_file = stdout; while ((c=getopt(argc, argv,"he:m:ic:o:j:b")) != -1) { switch(c) { case 0: continue; case 'e': if (options.events) errx(1, "events specified twice\n"); options.events = optarg; break; case 'i': options.opt_inherit = 1; break; case 'm': if (options.mmap_pages) errx(1, "mmap pages already set\n"); options.mmap_pages = atoi(optarg); break; case 'b': if (options.branch_filt) errx(1, "cannot use multiple branch filter options"); options.branch_filt = PERF_SAMPLE_BRANCH_ANY; break; case 'j': if (options.branch_filt) errx(1, "cannot set multiple branch options"); parse_branch_arg(optarg); break; case 'c': options.cpu = atoi(optarg); break; case 'o': options.output_file = fopen(optarg,"w"); if (!options.output_file) err(1, "cannot create file %s\n", optarg); break; case 'h': usage(); exit(0); default: errx(1, "unknown option"); } } if (argv[optind] == NULL) errx(1, "you must specify a command to execute\n"); if (!options.branch_filt) options.branch_filt = PERF_SAMPLE_BRANCH_ANY; /* * use low frequency rate to avoid flooding output * use generic branches event to make this test more portable */ if (!options.events) options.events = strdup(DFL_BR_EVENT); if (!options.mmap_pages) options.mmap_pages = 1; if (options.mmap_pages > 1 && ((options.mmap_pages) & 0x1)) errx(1, "number of pages must be power of 2 greater than 1\n"); printf("branch_filt=0x%"PRIx64"\n", options.branch_filt); printf("event=%s\n", options.events); return mainloop(argv+optind); } libpfm-4.9.0/perf_examples/self.c0000664000175000017500000001044713223402656016553 0ustar eranianeranian/* * self.c - example of a simple self monitoring task * * Copyright (c) 2009 Google, Inc * Contributed by Stephane Eranian * * Based on: * Copyright (c) 2002-2007 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include "perf_util.h" static const char *gen_events[]={ "cycles", "instructions", NULL }; static volatile int quit; void sig_handler(int n) { quit = 1; } void noploop(void) { for(;quit == 0;); } static void print_counts(perf_event_desc_t *fds, int num_fds, const char *msg) { uint64_t val; uint64_t values[3]; double ratio; int i; ssize_t ret; /* * now read the results. We use pfp_event_count because * libpfm guarantees that counters for the events always * come first. */ memset(values, 0, sizeof(values)); for (i = 0; i < num_fds; i++) { ret = read(fds[i].fd, values, sizeof(values)); if (ret < (ssize_t)sizeof(values)) { if (ret == -1) err(1, "cannot read results: %s", strerror(errno)); else warnx("could not read event%d", i); } /* * scaling is systematic because we may be sharing the PMU and * thus may be multiplexed */ val = perf_scale(values); ratio = perf_scale_ratio(values); printf("%s %'20"PRIu64" %s (%.2f%% scaling, raw=%'"PRIu64", ena=%'"PRIu64", run=%'"PRIu64")\n", msg, val, fds[i].name, (1.0-ratio)*100.0, values[0], values[1], values[2]); } } int main(int argc, char **argv) { perf_event_desc_t *fds = NULL; int i, ret, num_fds = 0; setlocale(LC_ALL, ""); /* * Initialize pfm library (required before we can use it) */ ret = pfm_initialize(); if (ret != PFM_SUCCESS) errx(1, "Cannot initialize library: %s", pfm_strerror(ret)); ret = perf_setup_argv_events(argc > 1 ? (const char **)argv+1 : gen_events, &fds, &num_fds); if (ret || !num_fds) errx(1, "cannot setup events"); fds[0].fd = -1; for(i=0; i < num_fds; i++) { /* request timing information necessary for scaling */ fds[i].hw.read_format = PERF_FORMAT_SCALE; fds[i].hw.disabled = 1; /* do not start now */ /* each event is in an independent group (multiplexing likely) */ fds[i].fd = perf_event_open(&fds[i].hw, 0, -1, -1, 0); if (fds[i].fd == -1) err(1, "cannot open event %d", i); } signal(SIGALRM, sig_handler); /* * enable all counters attached to this thread and created by it */ ret = prctl(PR_TASK_PERF_EVENTS_ENABLE); if (ret) err(1, "prctl(enable) failed"); print_counts(fds, num_fds, "INITIAL: "); alarm(10); noploop(); /* * disable all counters attached to this thread */ ret = prctl(PR_TASK_PERF_EVENTS_DISABLE); if (ret) err(1, "prctl(disable) failed"); printf("Final counts:\n"); print_counts(fds, num_fds, "FINAL: "); for (i = 0; i < num_fds; i++) close(fds[i].fd); perf_free_fds(fds, num_fds); /* free libpfm resources cleanly */ pfm_terminate(); return 0; } libpfm-4.9.0/perf_examples/rtop.c0000664000175000017500000003006213223402656016601 0ustar eranianeranian/* rtop.c - a simple PMU-based CPU utilization tool * * Copyright (c) 2009 Google, Inc * Contributed by Stephane Eranian * * Based on: * Copyright (c) 2004-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "perf_util.h" #define RTOP_VERSION "0.2" /* * max number of cpus (threads) supported */ #define RTOP_MAX_CPUS 2048 /* MUST BE power of 2 */ #define RTOP_CPUMASK_BITS (sizeof(unsigned long)<<3) #define RTOP_CPUMASK_COUNT (RTOP_MAX_CPUS/RTOP_CPUMASK_BITS) #define RTOP_CPUMASK_SET(m, g) ((m)[(g)/RTOP_CPUMASK_BITS] |= (1UL << ((g) % RTOP_CPUMASK_BITS))) #define RTOP_CPUMASK_CLEAR(m, g) ((m)[(g)/RTOP_CPUMASK_BITS] &= ~(1UL << ((g) % RTOP_CPUMASK_BITS))) #define RTOP_CPUMASK_ISSET(m, g) ((m)[(g)/RTOP_CPUMASK_BITS] & (1UL << ((g) % RTOP_CPUMASK_BITS))) typedef unsigned long rtop_cpumask_t[RTOP_CPUMASK_COUNT]; typedef struct { struct { int opt_verbose; int opt_delay; /* refresh delay in second */ int opt_delay_set; } program_opt_flags; rtop_cpumask_t cpu_mask; /* which CPUs to use in system wide mode */ long online_cpus; long selected_cpus; unsigned long cpu_mhz; } program_options_t; #define opt_verbose program_opt_flags.opt_verbose #define opt_delay program_opt_flags.opt_delay #define opt_delay_set program_opt_flags.opt_delay_set static program_options_t options; static struct termios saved_tty; static int time_to_quit; static int term_rows, term_cols; static void get_term_size(void) { int ret; struct winsize ws; ret = ioctl(1, TIOCGWINSZ, &ws); if (ret) err(1, "cannot determine screen size"); if (ws.ws_row > 10) { term_cols = ws.ws_col; term_rows = ws.ws_row; } else { term_cols = 80; term_rows = 24; } if (term_rows < options.selected_cpus) errx(1, "you need at least %ld rows on your terminal to display all CPUs", options.selected_cpus); } static void sigwinch_handler(int n) { get_term_size(); } static void setup_screen(void) { int ret; ret = tcgetattr(0, &saved_tty); if (ret == -1) errx(1, "cannot save tty settings\n"); get_term_size(); initscr(); nocbreak(); resizeterm(term_rows, term_cols); } static void close_screen(void) { endwin(); tcsetattr(0, TCSAFLUSH, &saved_tty); } static void fatal_errorw(char *fmt, ...) { va_list ap; close_screen(); va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); exit(1); } static void sigint_handler(int n) { time_to_quit = 1; } static unsigned long find_cpu_speed(void) { FILE *fp1; unsigned long f1 = 0, f2 = 0; char buffer[128], *p, *value; memset(buffer, 0, sizeof(buffer)); fp1 = fopen("/proc/cpuinfo", "r"); if (fp1 == NULL) return 0; for (;;) { buffer[0] = '\0'; p = fgets(buffer, 127, fp1); if (p == NULL) break; /* skip blank lines */ if (*p == '\n') continue; p = strchr(buffer, ':'); if (p == NULL) break; /* * p+2: +1 = space, +2= firt character * strlen()-1 gets rid of \n */ *p = '\0'; value = p+2; value[strlen(value)-1] = '\0'; if (!strncasecmp("cpu MHz", buffer, 7)) { float fl; sscanf(value, "%f", &fl); f1 = lroundf(fl); break; } if (!strncasecmp("BogoMIPS", buffer, 8)) { float fl; sscanf(value, "%f", &fl); f2 = lroundf(fl); } } fclose(fp1); return f1 == 0 ? f2 : f1; } static void setup_signals(void) { struct sigaction act; sigset_t my_set; /* * SIGINT is a asynchronous signal * sent to the process (not a specific thread). POSIX states * that one and only one thread will execute the handler. This * could be any thread that does not have the signal blocked. */ /* * install SIGINT handler */ memset(&act,0,sizeof(act)); sigemptyset(&my_set); act.sa_handler = sigint_handler; sigaction (SIGINT, &act, 0); /* * install SIGWINCH handler */ memset(&act,0,sizeof(act)); sigemptyset(&my_set); act.sa_handler = sigwinch_handler; sigaction (SIGWINCH, &act, 0); } static struct option rtop_cmd_options[]={ { "help", 0, 0, 1 }, { "version", 0, 0, 2 }, { "delay", 0, 0, 3 }, { "cpu-list", 1, 0, 4 }, { "verbose", 0, &options.opt_verbose, 1 }, { 0, 0, 0, 0} }; #define MAX_EVENTS 2 typedef struct { uint64_t prev_values[MAX_EVENTS]; int fd[MAX_EVENTS]; int cpu; } cpudesc_t; /* * { u64 nr; * { u64 time_enabled; } && PERF_FORMAT_ENABLED * { u64 time_running; } && PERF_FORMAT_RUNNING * { u64 value; * { u64 id; } && PERF_FORMAT_ID * } cntr[nr]; */ typedef struct { uint64_t nr; uint64_t time_enabled; uint64_t time_running; uint64_t values[2]; } rtop_grp_t; static void mainloop(void) { struct perf_event_attr ev[MAX_EVENTS]; unsigned long itc_delta; cpudesc_t *cpus; int i, j = 0, k, ncpus = 0; int num, ret; ncpus = options.selected_cpus; cpus = calloc(ncpus, sizeof(cpudesc_t)); if (!cpus) err(1, "cannot allocate file descriptors"); memset(ev, 0, sizeof(ev)); /* measure user cycles */ ev[0].type = PERF_TYPE_HARDWARE; ev[0].config = PERF_COUNT_HW_CPU_CYCLES; ev[0].read_format = PERF_FORMAT_SCALE|PERF_FORMAT_GROUP; ev[0].exclude_kernel = 1; ev[0].disabled = 1; ev[0].pinned = 0; /* measure kernel cycles */ ev[1].type = PERF_TYPE_HARDWARE; ev[1].config = PERF_COUNT_HW_CPU_CYCLES; ev[1].exclude_user = 1; ev[1].disabled = 1; ev[1].pinned = 0; num = 2; for(i=0, k = 0; ncpus; i++) { if (RTOP_CPUMASK_ISSET(options.cpu_mask, i) == 0) continue; cpus[k].cpu = i; cpus[k].fd[0] = -1; for(j=0 ; j < num; j++) { cpus[k].fd[j] = perf_event_open(ev+j, -1, i, cpus[k].fd[0], 0); if (cpus[k].fd[j] == -1) fatal_errorw("cannot open event %d on CPU%d: %s\n", j, i, strerror(errno)); } ncpus--; k++; } ncpus = options.selected_cpus; itc_delta = options.opt_delay * options.cpu_mhz * 1000000; for(i=0; i < ncpus; i++) for(j=0; j < num; j++) ioctl(cpus[i].fd[j], PERF_EVENT_IOC_ENABLE, 0); for(;time_to_quit == 0;) { sleep(options.opt_delay); move(0, 0); for(i=0; i < ncpus; i++) { uint64_t values[MAX_EVENTS]; uint64_t raw_values[5]; double k_cycles, u_cycles, i_cycles, ratio; /* * given our events are in the same group, we can do a * group read and get both counts + scaling information */ ret = read(cpus[i].fd[0], raw_values, sizeof(raw_values)); if (ret != sizeof(raw_values)) fatal_errorw("cannot read count for event %d on CPU%d\n", j, cpus[i].cpu); printw("nr=%"PRIu64"\n", raw_values[0]); printw("ena=%"PRIu64"\n", raw_values[1]); printw("run=%"PRIu64"\n", raw_values[2]); raw_values[0] = raw_values[3]; values[0] = perf_scale(raw_values); raw_values[0] = raw_values[4]; values[1] = perf_scale(raw_values); ratio = perf_scale_ratio(raw_values); k_cycles = (double)(values[1] - cpus[i].prev_values[1])*100.0/ (double)itc_delta; u_cycles = (double)(values[0] - cpus[i].prev_values[0])*100.0/ (double)itc_delta; i_cycles = 100.0 - (k_cycles + u_cycles); cpus[i].prev_values[0] = values[0]; cpus[i].prev_values[1] = values[1]; /* * adjust for rounding errors */ if (i_cycles < 0.0) i_cycles = 0.0; if (i_cycles > 100.0) i_cycles = 100.0; if (k_cycles > 100.0) k_cycles = 100.0; if (u_cycles > 100.0) u_cycles = 100.0; printw("CPU%-2ld %6.2f%% usr %6.2f%% sys %6.2f%% idle (scaling ratio %.2f%%)\n", i, u_cycles, k_cycles, i_cycles, ratio*100.0); } refresh(); } for(i=0; i < ncpus; i++) for(j=0; j < num; j++) close(cpus[i].fd[j]); free(cpus); } void populate_cpumask(char *cpu_list) { char *p; unsigned long start_cpu, end_cpu = 0; unsigned long i, count = 0; options.online_cpus = sysconf(_SC_NPROCESSORS_ONLN); if (options.online_cpus == -1) errx(1, "cannot figure out the number of online processors"); if (cpu_list == NULL) { if (options.online_cpus >= RTOP_MAX_CPUS) errx(1, "rtop can only handle to %u CPUs", RTOP_MAX_CPUS); for(i=0; i < options.online_cpus; i++) RTOP_CPUMASK_SET(options.cpu_mask, i); options.selected_cpus = options.online_cpus; return; } while(isdigit(*cpu_list)) { p = NULL; start_cpu = strtoul(cpu_list, &p, 0); /* auto-detect base */ if (start_cpu == ULONG_MAX || (*p != '\0' && *p != ',' && *p != '-')) goto invalid; if (p && *p == '-') { cpu_list = ++p; p = NULL; end_cpu = strtoul(cpu_list, &p, 0); /* auto-detect base */ if (end_cpu == ULONG_MAX || (*p != '\0' && *p != ',')) goto invalid; if (end_cpu < start_cpu) goto invalid_range; } else { end_cpu = start_cpu; } if (start_cpu >= RTOP_MAX_CPUS || end_cpu >= RTOP_MAX_CPUS) goto too_big; for (; start_cpu <= end_cpu; start_cpu++) { if (start_cpu >= options.online_cpus) goto not_online; /* XXX: assume contiguous range of CPUs */ if (RTOP_CPUMASK_ISSET(options.cpu_mask, start_cpu)) continue; RTOP_CPUMASK_SET(options.cpu_mask, start_cpu); count++; } if (*p) ++p; cpu_list = p; } options.selected_cpus = count; return; invalid: errx(1, "invalid cpu list argument: %s", cpu_list); /* no return */ not_online: errx(1, "cpu %lu is not online", start_cpu); /* no return */ invalid_range: errx(1, "cpu range %lu - %lu is invalid", start_cpu, end_cpu); /* no return */ too_big: errx(1, "rtop is limited to %u CPUs", RTOP_MAX_CPUS); /* no return */ } static void usage(void) { printf( "usage: rtop [options]:\n" "-h, --help\t\t\tdisplay this help and exit\n" "-v, --verbose\t\t\tverbose output\n" "-V, --version\t\t\tshow version and exit\n" "-d nsec, --delay=nsec\t\tnumber of seconds between refresh (default=1s)\n" "--cpu-list=cpu1,cpu2\t\tlist of CPUs to monitor(default=all)\n" ); } int main(int argc, char **argv) { int c; char *cpu_list = NULL; //if (geteuid()) err(1, "perf_event requires root privileges to create system-wide measurments\n"); while ((c=getopt_long(argc, argv,"+vhVd:", rtop_cmd_options, 0)) != -1) { switch(c) { case 0: continue; /* fast path for options */ case 'v': options.opt_verbose = 1; break; case 1: case 'h': usage(); exit(0); case 2: case 'V': printf("rtop version " RTOP_VERSION " Date: " __DATE__ "\n" "Copyright (C) 2009 Google, Inc\n"); exit(0); case 3: case 'd': options.opt_delay = atoi(optarg); if (options.opt_delay < 0) errx(1, "invalid delay, must be >= 0"); options.opt_delay_set = 1; break; case 4: if (*optarg == '\0') errx(1, "--cpu-list needs an argument\n"); cpu_list = optarg; break; default: errx(1, "unknown option\n"); } } /* * default refresh delay */ if (options.opt_delay_set == 0) options.opt_delay = 1; options.cpu_mhz = find_cpu_speed(); populate_cpumask(cpu_list); setup_signals(); setup_screen(); mainloop(); close_screen(); return 0; } libpfm-4.9.0/perf_examples/task_cpu.c0000664000175000017500000002273313223402656017434 0ustar eranianeranian/* * task_cpu.c - example of per-thread remote monitoring with per-cpu breakdown * * Copyright (c) 2010 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include #include #include #include #include #include #include #include #include "perf_util.h" #define MAX_GROUPS 256 #define MAX_CPUS 64 typedef struct { const char *events[MAX_GROUPS]; int num_groups; int format_group; int inherit; int print; int pin; int ncpus; pid_t pid; } options_t; static options_t options; static volatile int quit; int child(char **arg) { /* * execute the requested command */ execvp(arg[0], arg); errx(1, "cannot exec: %s\n", arg[0]); /* not reached */ } static void read_groups(perf_event_desc_t *fds, int num) { uint64_t *values = NULL; size_t new_sz, sz = 0; int i, evt; ssize_t ret; /* * { u64 nr; * { u64 time_enabled; } && PERF_FORMAT_ENABLED * { u64 time_running; } && PERF_FORMAT_RUNNING * { u64 value; * { u64 id; } && PERF_FORMAT_ID * } cntr[nr]; * } && PERF_FORMAT_GROUP * * we do not use FORMAT_ID in this program */ for (evt = 0; evt < num; ) { int num_evts_to_read; if (options.format_group) { num_evts_to_read = perf_get_group_nevents(fds, num, evt); new_sz = sizeof(uint64_t) * (3 + num_evts_to_read); } else { num_evts_to_read = 1; new_sz = sizeof(uint64_t) * 3; } if (new_sz > sz) { sz = new_sz; values = realloc(values, sz); } if (!values) err(1, "cannot allocate memory for values\n"); ret = read(fds[evt].fd, values, new_sz); if (ret != (ssize_t)new_sz) { /* unsigned */ if (ret == -1) err(1, "cannot read values event %s", fds[evt].name); /* likely pinned and could not be loaded */ warnx("could not read event %d, tried to read %zu bytes, but got %zd", evt, new_sz, ret); } /* * propagate to save area */ for (i = evt; i < (evt + num_evts_to_read); i++) { if (options.format_group) values[0] = values[3 + (i - evt)]; /* * scaling because we may be sharing the PMU and * thus may be multiplexed */ fds[i].values[0] = values[0]; fds[i].values[1] = values[1]; fds[i].values[2] = values[2]; } evt += num_evts_to_read; } if (values) free(values); } static void print_counts(perf_event_desc_t *fds, int num, int cpu) { double ratio; uint64_t val, delta; int i; read_groups(fds, num); for(i=0; i < num; i++) { val = perf_scale(fds[i].values); delta = perf_scale_delta(fds[i].values, fds[i].prev_values); ratio = perf_scale_ratio(fds[i].values); /* separate groups */ if (perf_is_group_leader(fds, i)) putchar('\n'); if (options.print) printf("CPU%-2d %'20"PRIu64" %'20"PRIu64" %s (%.2f%% scaling, ena=%'"PRIu64", run=%'"PRIu64")\n", cpu, val, delta, fds[i].name, (1.0-ratio)*100.0, fds[i].values[1], fds[i].values[2]); else printf("CPU%-2d %'20"PRIu64" %s (%.2f%% scaling, ena=%'"PRIu64", run=%'"PRIu64")\n", cpu, val, fds[i].name, (1.0-ratio)*100.0, fds[i].values[1], fds[i].values[2]); } } static void sig_handler(int n) { quit = 1; } int parent(char **arg) { perf_event_desc_t *fds, *fds_cpus[MAX_CPUS]; int status, ret, i, num_fds = 0, grp, group_fd; int ready[2], go[2], cpu; char buf; pid_t pid; go[0] = go[1] = -1; if (pfm_initialize() != PFM_SUCCESS) errx(1, "libpfm initialization failed"); if (options.ncpus >= MAX_CPUS) errx(1, "maximum number of cpus exceeded (%d)", MAX_CPUS); memset(fds_cpus, 0, sizeof(fds_cpus)); for (cpu=0; cpu < options.ncpus; cpu++) { for (grp = 0; grp < options.num_groups; grp++) { num_fds = 0; ret = perf_setup_list_events(options.events[grp], &fds_cpus[cpu], &num_fds); if (ret || !num_fds) exit(1); } } pid = options.pid; if (!pid) { ret = pipe(ready); if (ret) err(1, "cannot create pipe ready"); ret = pipe(go); if (ret) err(1, "cannot create pipe go"); /* * Create the child task */ if ((pid=fork()) == -1) err(1, "Cannot fork process"); /* * and launch the child code * * The pipe is used to avoid a race condition * between for() and exec(). We need the pid * of the new tak but we want to start measuring * at the first user level instruction. Thus we * need to prevent exec until we have attached * the events. */ if (pid == 0) { close(ready[0]); close(go[1]); /* * let the parent know we exist */ close(ready[1]); if (read(go[0], &buf, 1) == -1) err(1, "unable to read go_pipe"); exit(child(arg)); } close(ready[1]); close(go[0]); if (read(ready[0], &buf, 1) == -1) err(1, "unable to read child_ready_pipe"); close(ready[0]); } for (cpu=0; cpu < options.ncpus; cpu++) { fds = fds_cpus[cpu]; for(i=0; i < num_fds; i++) { int is_group_leader; /* boolean */ is_group_leader = perf_is_group_leader(fds, i); if (is_group_leader) { /* this is the group leader */ group_fd = -1; } else { group_fd = fds[fds[i].group_leader].fd; } /* * create leader disabled with enable_on-exec */ if (!options.pid) { fds[i].hw.disabled = is_group_leader; fds[i].hw.enable_on_exec = is_group_leader; } fds[i].hw.read_format = PERF_FORMAT_SCALE; /* request timing information necessary for scaling counts */ if (is_group_leader && options.format_group) fds[i].hw.read_format |= PERF_FORMAT_GROUP; if (options.inherit) fds[i].hw.inherit = 1; if (options.pin && is_group_leader) fds[i].hw.pinned = 1; fds[i].fd = perf_event_open(&fds[i].hw, pid, cpu, group_fd, 0); if (fds[i].fd == -1) { warn("cannot attach event%d %s", i, fds[i].name); goto error; } } } if (!options.pid && go[1] > -1) close(go[1]); if (options.print) { if (!options.pid) { while(waitpid(pid, &status, WNOHANG) == 0) { sleep(1); for (cpu=0; cpu < options.ncpus; cpu++) { fds = fds_cpus[cpu]; print_counts(fds, num_fds, cpu); } } } else { while(quit == 0) { sleep(1); for (cpu=0; cpu < options.ncpus; cpu++) { fds = fds_cpus[cpu]; print_counts(fds, num_fds, cpu); } } } } else { if (!options.pid) waitpid(pid, &status, 0); else { pause(); for (cpu=0; cpu < options.ncpus; cpu++) { fds = fds_cpus[cpu]; for(i=0; i < num_fds; i++) ioctl(fds[i].fd, PERF_EVENT_IOC_DISABLE, 0); } } for (cpu=0; cpu < options.ncpus; cpu++) { fds = fds_cpus[cpu]; print_counts(fds, num_fds, cpu); } } for (cpu=0; cpu < options.ncpus; cpu++) { fds = fds_cpus[cpu]; for(i=0; i < num_fds; i++) close(fds[i].fd); perf_free_fds(fds, num_fds); } /* free libpfm resources cleanly */ pfm_terminate(); return 0; error: free(fds); if (!options.pid) kill(SIGKILL, pid); /* free libpfm resources cleanly */ pfm_terminate(); return -1; } static void usage(void) { printf("usage: task_cpu [-h] [-i] [-g] [-p] [-P] [-t pid] [-e event1,event2,...] cmd\n" "-h\t\tget help\n" "-i\t\tinherit across fork\n" "-f\t\tuse PERF_FORMAT_GROUP for reading up counts (experimental, not working)\n" "-p\t\tprint counts every second\n" "-P\t\tpin events\n" "-t pid\tmeasure existing pid\n" "-e ev,ev\tgroup of events to measure (multiple -e switches are allowed)\n" ); } int main(int argc, char **argv) { int c; setlocale(LC_ALL, ""); while ((c=getopt(argc, argv,"+he:ifpPt:")) != -1) { switch(c) { case 'e': if (options.num_groups < MAX_GROUPS) { options.events[options.num_groups++] = optarg; } else { errx(1, "you cannot specify more than %d groups.\n", MAX_GROUPS); } break; case 'f': options.format_group = 1; break; case 'p': options.print = 1; break; case 'P': options.pin = 1; break; case 'i': options.inherit = 1; break; case 't': options.pid = atoi(optarg); break; case 'h': usage(); exit(0); default: errx(1, "unknown error"); } } options.ncpus = sysconf(_SC_NPROCESSORS_ONLN); if (options.ncpus < 1) errx(1, "cannot determine number of online processors"); if (options.num_groups == 0) { options.events[0] = "cycles,instructions"; options.num_groups = 1; } if (!argv[optind] && !options.pid) errx(1, "you must specify a command to execute or a thread to attach to\n"); signal(SIGINT, sig_handler); return parent(argv+optind); } libpfm-4.9.0/perf_examples/syst_count.c0000664000175000017500000002304313223402656020030 0ustar eranianeranian/* * syst.c - example of a simple system wide monitoring program * * Copyright (c) 2010 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include "perf_util.h" #define MAX_GROUPS 256 #define MAX_PATH 1024 #ifndef STR # define _STR(x) #x # define STR(x) _STR(x) #endif typedef struct { const char *events[MAX_GROUPS]; int nevents[MAX_GROUPS]; /* #events per group */ int num_groups; int delay; int excl; int pin; int interval; int cpu; char *cgroup_name; } options_t; static options_t options; static perf_event_desc_t **all_fds; static int cgroupfs_find_mountpoint(char *buf, size_t maxlen) { FILE *fp; char mountpoint[MAX_PATH+1], tokens[MAX_PATH+1], type[MAX_PATH+1]; char *token, *saved_ptr = NULL; int found = 0; fp = fopen("/proc/mounts", "r"); if (!fp) return -1; /* * in order to handle split hierarchy, we need to scan /proc/mounts * and inspect every cgroupfs mount point to find one that has * perf_event subsystem */ while (fscanf(fp, "%*s %"STR(MAX_PATH)"s %"STR(MAX_PATH)"s %" STR(MAX_PATH)"s %*d %*d\n", mountpoint, type, tokens) == 3) { if (!strcmp(type, "cgroup")) { token = strtok_r(tokens, ",", &saved_ptr); while (token != NULL) { if (!strcmp(token, "perf_event")) { found = 1; break; } token = strtok_r(NULL, ",", &saved_ptr); } } if (found) break; } fclose(fp); if (!found) return -1; if (strlen(mountpoint) < maxlen) { strcpy(buf, mountpoint); return 0; } return -1; } int open_cgroup(char *name) { char path[MAX_PATH+1]; char mnt[MAX_PATH+1]; int cfd; if (cgroupfs_find_mountpoint(mnt, MAX_PATH+1)) errx(1, "cannot find cgroup fs mount point"); snprintf(path, MAX_PATH, "%s/%s", mnt, name); cfd = open(path, O_RDONLY); if (cfd == -1) warn("no access to cgroup %s\n", name); return cfd; } void setup_cpu(int cpu, int cfd) { perf_event_desc_t *fds = NULL; int old_total, total = 0, num; int i, j, n, ret, is_lead, group_fd; unsigned long flags; pid_t pid; for(i=0, j=0; i < options.num_groups; i++) { old_total = total; ret = perf_setup_list_events(options.events[i], &fds, &total); if (ret) errx(1, "cannot setup events\n"); all_fds[cpu] = fds; num = total - old_total; options.nevents[i] = num; for(n=0; n < num; n++, j++) { is_lead = perf_is_group_leader(fds, j); if (is_lead) { fds[j].hw.disabled = 1; group_fd = -1; } else { fds[j].hw.disabled = 0; group_fd = fds[fds[j].group_leader].fd; } fds[j].hw.size = sizeof(struct perf_event_attr); if (options.cgroup_name) { flags = PERF_FLAG_PID_CGROUP; pid = cfd; //fds[j].hw.cgroup = 1; //fds[j].hw.cgroup_fd = cfd; } else { flags = 0; pid = -1; } if (options.pin && is_lead) fds[j].hw.pinned = 1; if (options.excl && is_lead) fds[j].hw.exclusive = 1; /* request timing information necessary for scaling counts */ fds[j].hw.read_format = PERF_FORMAT_SCALE; fds[j].fd = perf_event_open(&fds[j].hw, pid, cpu, group_fd, flags); if (fds[j].fd == -1) { if (errno == EACCES) err(1, "you need to be root to run system-wide on this machine"); warn("cannot attach event %s to CPU%ds, aborting", fds[j].name, cpu); exit(1); } } } } void start_cpu(int c) { perf_event_desc_t *fds = NULL; int j, ret, n = 0; fds = all_fds[c]; if (fds[0].fd == -1) return; for(j=0; j < options.num_groups; j++) { /* group leader always first in each group */ ret = ioctl(fds[n].fd, PERF_EVENT_IOC_ENABLE, 0); if (ret) err(1, "cannot enable event %s\n", fds[j].name); n += options.nevents[j]; } } void stop_cpu(int c) { perf_event_desc_t *fds = NULL; int j, ret, n = 0; fds = all_fds[c]; if (fds[0].fd == -1) return; for(j=0; j < options.num_groups; j++) { /* group leader always first in each group */ ret = ioctl(fds[n].fd, PERF_EVENT_IOC_DISABLE, 0); if (ret) err(1, "cannot disable event %s\n", fds[j].name); n += options.nevents[j]; } } void read_cpu(int c) { perf_event_desc_t *fds; uint64_t val, delta; double ratio; int i, j, n, ret; fds = all_fds[c]; if (fds[0].fd == -1) { printf("CPU%d not monitored\n", c); return; } for(i=0, j = 0; i < options.num_groups; i++) { for(n = 0; n < options.nevents[i]; n++, j++) { ret = read(fds[j].fd, fds[j].values, sizeof(fds[j].values)); if (ret != sizeof(fds[j].values)) { if (ret == -1) err(1, "cannot read event %s : %d", fds[j].name, ret); else { warnx("CPU%d G%-2d could not read event %s, read=%d", c, i, fds[j].name, ret); continue; } } /* * scaling because we may be sharing the PMU and * thus may be multiplexed */ delta = perf_scale_delta(fds[j].values, fds[j].prev_values); val = perf_scale(fds[j].values); ratio = perf_scale_ratio(fds[j].values); printf("CPU%-3d G%-2d %'20"PRIu64" %'20"PRIu64" %s (scaling %.2f%%, ena=%'"PRIu64", run=%'"PRIu64") %s\n", c, i, val, delta, fds[j].name, (1.0-ratio)*100, fds[j].values[1], fds[j].values[2], options.cgroup_name ? options.cgroup_name : ""); fds[j].prev_values[0] = fds[j].values[0]; fds[j].prev_values[1] = fds[j].values[1]; fds[j].prev_values[2] = fds[j].values[2]; if (fds[j].values[2] > fds[j].values[1]) errx(1, "WARNING: time_running > time_enabled %"PRIu64"\n", fds[j].values[2] - fds[j].values[1]); } } } void close_cpu(int c) { perf_event_desc_t *fds = NULL; int i, j; int total = 0; fds = all_fds[c]; if (fds[0].fd == -1) return; for(i=0; i < options.num_groups; i++) { for(j=0; j < options.nevents[i]; j++) close(fds[j].fd); total += options.nevents[i]; } perf_free_fds(fds, total); } void measure(void) { int c, cmin, cmax, ncpus; int cfd = -1; cmin = 0; cmax = (int)sysconf(_SC_NPROCESSORS_ONLN); ncpus = cmax; if (options.cpu != -1) { cmin = options.cpu; cmax = cmin + 1; } all_fds = malloc(ncpus * sizeof(perf_event_desc_t *)); if (!all_fds) err(1, "cannot allocate memory for all_fds"); if (options.cgroup_name) { cfd = open_cgroup(options.cgroup_name); if (cfd == -1) exit(1); } for(c=cmin ; c < cmax; c++) setup_cpu(c, cfd); if (options.cgroup_name) close(cfd); printf("\n", options.delay); /* * FIX this for hotplug CPU */ if (options.interval) { struct timespec tv; int delay; for (delay = 1 ; delay <= options.delay; delay++) { for(c=cmin ; c < cmax; c++) start_cpu(c); if (0) { tv.tv_sec = 0; tv.tv_nsec = 100000000; nanosleep(&tv, NULL); } else sleep(1); for(c=cmin ; c < cmax; c++) stop_cpu(c); for(c = cmin; c < cmax; c++) { printf("# %'ds -----\n", delay); read_cpu(c); } } } else { for(c=cmin ; c < cmax; c++) start_cpu(c); sleep(options.delay); if (0) for(c=cmin ; c < cmax; c++) stop_cpu(c); for(c = cmin; c < cmax; c++) { printf("# -----\n"); read_cpu(c); } } for(c = cmin; c < cmax; c++) close_cpu(c); free(all_fds); } static void usage(void) { printf("usage: syst [-c cpu] [-x] [-h] [-p] [-d delay] [-P] [-G cgroup name] [-e event1,event2,...]\n"); } int main(int argc, char **argv) { int c, ret; setlocale(LC_ALL, ""); options.cpu = -1; while ((c=getopt(argc, argv,"hc:e:d:xPpG:")) != -1) { switch(c) { case 'x': options.excl = 1; break; case 'p': options.interval = 1; break; case 'e': if (options.num_groups < MAX_GROUPS) { options.events[options.num_groups++] = optarg; } else { errx(1, "you cannot specify more than %d groups.\n", MAX_GROUPS); } break; case 'c': options.cpu = atoi(optarg); break; case 'd': options.delay = atoi(optarg); break; case 'P': options.pin = 1; break; case 'h': usage(); exit(0); case 'G': options.cgroup_name = optarg; break; default: errx(1, "unknown error"); } } if (!options.delay) options.delay = 20; if (!options.events[0]) { options.events[0] = "cycles,instructions"; options.num_groups = 1; } ret = pfm_initialize(); if (ret != PFM_SUCCESS) errx(1, "libpfm initialization failed: %s\n", pfm_strerror(ret)); measure(); /* free libpfm resources cleanly */ pfm_terminate(); return 0; } libpfm-4.9.0/perf_examples/notify_self.c0000664000175000017500000001630413223402656020141 0ustar eranianeranian/* * notify_self.c - example of how you can use overflow notifications * * Copyright (c) 2009 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include "perf_util.h" #define SMPL_PERIOD 2400000000ULL static volatile unsigned long notification_received; static perf_event_desc_t *fds = NULL; static int num_fds = 0; static int buffer_pages = 1; /* size of buffer payload (must be power of 2)*/ static void sigio_handler(int n, siginfo_t *info, void *uc) { struct perf_event_header ehdr; int ret, id; /* * positive si_code indicate kernel generated signal * which is normal for SIGIO */ if (info->si_code < 0) errx(1, "signal not generated by kernel"); /* * SIGPOLL = SIGIO * expect POLL_HUP instead of POLL_IN because we are * in one-shot mode (IOC_REFRESH) */ if (info->si_code != POLL_HUP) errx(1, "signal not generated by SIGIO"); id = perf_fd2event(fds, num_fds, info->si_fd); if (id == -1) errx(1, "no event associated with fd=%d", info->si_fd); ret = perf_read_buffer(fds+id, &ehdr, sizeof(ehdr)); if (ret) errx(1, "cannot read event header"); if (ehdr.type != PERF_RECORD_SAMPLE) { warnx("unexpected sample type=%d, skipping\n", ehdr.type); perf_skip_buffer(fds+id, ehdr.size); goto skip; } printf("Notification:%lu ", notification_received); ret = perf_display_sample(fds, num_fds, 0, &ehdr, stdout); /* * increment our notification counter */ notification_received++; skip: /* * rearm the counter for one more shot */ ret = ioctl(info->si_fd, PERF_EVENT_IOC_REFRESH, 1); if (ret == -1) err(1, "cannot refresh"); } /* * infinite loop waiting for notification to get out */ void busyloop(void) { /* * busy loop to burn CPU cycles */ for(;notification_received < 20;) ; } int main(int argc, char **argv) { struct sigaction act; sigset_t new, old; uint64_t *val; size_t sz, pgsz; int ret, i; setlocale(LC_ALL, ""); ret = pfm_initialize(); if (ret != PFM_SUCCESS) errx(1, "Cannot initialize library: %s", pfm_strerror(ret)); pgsz = sysconf(_SC_PAGESIZE); /* * Install the signal handler (SIGIO) * need SA_SIGINFO because we need the fd * in the signal handler */ memset(&act, 0, sizeof(act)); act.sa_sigaction = sigio_handler; act.sa_flags = SA_SIGINFO; sigaction (SIGIO, &act, 0); sigemptyset(&old); sigemptyset(&new); sigaddset(&new, SIGIO); ret = sigprocmask(SIG_SETMASK, NULL, &old); if (ret) err(1, "sigprocmask failed"); if (sigismember(&old, SIGIO)) { warnx("program started with SIGIO masked, unmasking it now\n"); ret = sigprocmask(SIG_UNBLOCK, &new, NULL); if (ret) err(1, "sigprocmask failed"); } /* * allocates fd for us */ ret = perf_setup_list_events("cycles," "instructions", &fds, &num_fds); if (ret || (num_fds == 0)) exit(1); fds[0].fd = -1; for(i=0; i < num_fds; i++) { /* want a notification for every each added to the buffer */ fds[i].hw.disabled = !i; if (!i) { fds[i].hw.wakeup_events = 1; fds[i].hw.sample_type = PERF_SAMPLE_IP|PERF_SAMPLE_READ|PERF_SAMPLE_PERIOD; fds[i].hw.sample_period = SMPL_PERIOD; /* read() returns event identification for signal handler */ fds[i].hw.read_format = PERF_FORMAT_GROUP|PERF_FORMAT_ID|PERF_FORMAT_SCALE; } fds[i].fd = perf_event_open(&fds[i].hw, 0, -1, fds[0].fd, 0); if (fds[i].fd == -1) err(1, "cannot attach event %s", fds[i].name); } sz = (3+2*num_fds)*sizeof(uint64_t); val = malloc(sz); if (!val) err(1, "cannot allocated memory"); /* * On overflow, the non lead events are stored in the sample. * However we need some key to figure the order in which they * were laid out in the buffer. The file descriptor does not * work for this. Instead, we extract a unique ID for each event. * That id will be part of the sample for each event value. * Therefore we will be able to match value to events * * PERF_FORMAT_ID: returns unique 64-bit identifier in addition * to event value. */ if (fds[0].fd == -1) errx(1, "cannot create event 0"); ret = read(fds[0].fd, val, sz); if (ret == -1) err(1, "cannot read id %zu", sizeof(val)); /* * we are using PERF_FORMAT_GROUP, therefore the structure * of val is as follows: * * { u64 nr; * { u64 time_enabled; } && PERF_FORMAT_ENABLED * { u64 time_running; } && PERF_FORMAT_RUNNING * { u64 value; * { u64 id; } && PERF_FORMAT_ID * } cntr[nr]; * We are skipping the first 3 values (nr, time_enabled, time_running) * and then for each event we get a pair of values. */ for(i=0; i < num_fds; i++) { fds[i].id = val[2*i+1+3]; printf("%"PRIu64" %s\n", fds[i].id, fds[i].name); } fds[0].buf = mmap(NULL, (buffer_pages+1)*pgsz, PROT_READ|PROT_WRITE, MAP_SHARED, fds[0].fd, 0); if (fds[0].buf == MAP_FAILED) err(1, "cannot mmap buffer"); fds[0].pgmsk = (buffer_pages * pgsz) - 1; /* * setup asynchronous notification on the file descriptor */ ret = fcntl(fds[0].fd, F_SETFL, fcntl(fds[0].fd, F_GETFL, 0) | O_ASYNC); if (ret == -1) err(1, "cannot set ASYNC"); /* * necessary if we want to get the file descriptor for * which the SIGIO is sent in siginfo->si_fd. * SA_SIGINFO in itself is not enough */ ret = fcntl(fds[0].fd, F_SETSIG, SIGIO); if (ret == -1) err(1, "cannot setsig"); /* * get ownership of the descriptor */ ret = fcntl(fds[0].fd, F_SETOWN, getpid()); if (ret == -1) err(1, "cannot setown"); /* * enable the group for one period */ ret = ioctl(fds[0].fd, PERF_EVENT_IOC_REFRESH , 1); if (ret == -1) err(1, "cannot refresh"); busyloop(); ret = ioctl(fds[0].fd, PERF_EVENT_IOC_DISABLE, 1); if (ret == -1) err(1, "cannot disable"); /* * destroy our session */ for(i=0; i < num_fds; i++) close(fds[i].fd); perf_free_fds(fds, num_fds); free(val); /* free libpfm resources cleanly */ pfm_terminate(); return 0; } libpfm-4.9.0/perf_examples/perf_util.c0000664000175000017500000004140413223402656017610 0ustar eranianeranian/* * perf_util.c - helper functions for perf_events * * Copyright (c) 2009 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include #include #include #include #include "perf_util.h" /* the **fd parameter must point to a null pointer on the first call * max_fds and num_fds must both point to a zero value on the first call * The return value is success (0) vs. failure (non-zero) */ int perf_setup_argv_events(const char **argv, perf_event_desc_t **fds, int *num_fds) { perf_event_desc_t *fd; pfm_perf_encode_arg_t arg; int new_max, ret, num, max_fds; int group_leader; if (!(argv && fds && num_fds)) return -1; fd = *fds; if (fd) { max_fds = fd[0].max_fds; if (max_fds < 2) return -1; num = *num_fds; } else { max_fds = num = 0; /* bootstrap */ } group_leader = num; while(*argv) { if (num == max_fds) { if (max_fds == 0) new_max = 2; else new_max = max_fds << 1; if (new_max < max_fds) { warn("too many entries"); goto error; } fd = realloc(fd, new_max * sizeof(*fd)); if (!fd) { warn("cannot allocate memory"); goto error; } /* reset newly allocated chunk */ memset(fd + max_fds, 0, (new_max - max_fds) * sizeof(*fd)); max_fds = new_max; /* update max size */ fd[0].max_fds = max_fds; } /* ABI compatibility, set before calling libpfm */ fd[num].hw.size = sizeof(fd[num].hw); memset(&arg, 0, sizeof(arg)); arg.attr = &fd[num].hw; arg.fstr = &fd[num].fstr; /* fd[].fstr is NULL */ ret = pfm_get_os_event_encoding(*argv, PFM_PLM0|PFM_PLM3, PFM_OS_PERF_EVENT_EXT, &arg); if (ret != PFM_SUCCESS) { warnx("event %s: %s", *argv, pfm_strerror(ret)); goto error; } fd[num].name = strdup(*argv); fd[num].group_leader = group_leader; fd[num].idx = arg.idx; fd[num].cpu = arg.cpu; num++; argv++; } *num_fds = num; *fds = fd; return 0; error: perf_free_fds(fd, num); return -1; } int perf_setup_list_events(const char *ev, perf_event_desc_t **fd, int *num_fds) { const char **argv; char *p, *q, *events; int i, ret, num = 0; if (!(ev && fd && num_fds)) return -1; events = strdup(ev); if (!events) return -1; q = events; while((p = strchr(q, ','))) { num++; q = p + 1; } num++; num++; /* terminator */ argv = malloc(num * sizeof(char *)); if (!argv) { free(events); return -1; } i = 0; q = events; while((p = strchr(q, ','))) { *p = '\0'; argv[i++] = q; q = p + 1; } argv[i++] = q; argv[i] = NULL; ret = perf_setup_argv_events(argv, fd, num_fds); free(argv); free(events); /* strdup in perf_setup_argv_events() */ return ret; } void perf_free_fds(perf_event_desc_t *fds, int num_fds) { int i; for (i = 0 ; i < num_fds; i++) { free(fds[i].name); free(fds[i].fstr); } free(fds); } int perf_get_group_nevents(perf_event_desc_t *fds, int num, int idx) { int leader; int i; if (idx < 0 || idx >= num) return 0; leader = fds[idx].group_leader; for (i = leader + 1; i < num; i++) { if (fds[i].group_leader != leader) { /* This is a new group leader, so the previous * event was the final event of the preceding * group. */ return i - leader; } } return i - leader; } int perf_read_buffer(perf_event_desc_t *hw, void *buf, size_t sz) { struct perf_event_mmap_page *hdr = hw->buf; size_t pgmsk = hw->pgmsk; void *data; unsigned long tail; size_t avail_sz, m, c; /* * data points to beginning of buffer payload */ data = ((void *)hdr)+sysconf(_SC_PAGESIZE); /* * position of tail within the buffer payload */ tail = hdr->data_tail & pgmsk; /* * size of what is available * * data_head, data_tail never wrap around */ avail_sz = hdr->data_head - hdr->data_tail; if (sz > avail_sz) return -1; /* * sz <= avail_sz, we can satisfy the request */ /* * c = size till end of buffer * * buffer payload size is necessarily * a power of two, so we can do: */ c = pgmsk + 1 - tail; /* * min with requested size */ m = c < sz ? c : sz; /* copy beginning */ memcpy(buf, data+tail, m); /* * copy wrapped around leftover */ if (sz > m) memcpy(buf+m, data, sz - m); //printf("\nhead=%lx tail=%lx new_tail=%lx sz=%zu\n", hdr->data_head, hdr->data_tail, hdr->data_tail+sz, sz); hdr->data_tail += sz; return 0; } void perf_skip_buffer(perf_event_desc_t *hw, size_t sz) { struct perf_event_mmap_page *hdr = hw->buf; if ((hdr->data_tail + sz) > hdr->data_head) sz = hdr->data_head - hdr->data_tail; hdr->data_tail += sz; } static size_t __perf_handle_raw(perf_event_desc_t *hw) { size_t sz = 0; uint32_t raw_sz, i; char *buf; int ret; ret = perf_read_buffer_32(hw, &raw_sz); if (ret) { warnx("cannot read raw size"); return -1; } sz += sizeof(raw_sz); printf("\n\tRAWSZ:%u\n", raw_sz); buf = malloc(raw_sz); if (!buf) { warn("cannot allocate raw buffer"); return -1; } ret = perf_read_buffer(hw, buf, raw_sz); if (ret) { warnx("cannot read raw data"); free(buf); return -1; } if (raw_sz) putchar('\t'); for(i=0; i < raw_sz; i++) { printf("0x%02x ", buf[i] & 0xff ); if (((i+1) % 16) == 0) printf("\n\t"); } if (raw_sz) putchar('\n'); free(buf); return sz + raw_sz; } static int perf_display_branch_stack(perf_event_desc_t *desc, FILE *fp) { struct perf_branch_entry b; uint64_t nr, n; int ret; ret = perf_read_buffer(desc, &n, sizeof(n)); if (ret) errx(1, "cannot read branch stack nr"); fprintf(fp, "\n\tBRANCH_STACK:%"PRIu64"\n", n); nr = n; /* * from most recent to least recent take branch */ while (nr--) { ret = perf_read_buffer(desc, &b, sizeof(b)); if (ret) errx(1, "cannot read branch stack entry"); fprintf(fp, "\tFROM:0x%016"PRIx64" TO:0x%016"PRIx64" MISPRED:%c PRED:%c IN_TX:%c ABORT:%c CYCLES:%d type:%d\n", b.from, b.to, !(b.mispred || b.predicted) ? '-': (b.mispred ? 'Y' :'N'), !(b.mispred || b.predicted) ? '-': (b.predicted? 'Y' :'N'), (b.in_tx? 'Y' :'N'), (b.abort? 'Y' :'N'), b.type, b.cycles); } return (int)(n * sizeof(b) + sizeof(n)); } static int perf_display_regs_user(perf_event_desc_t *hw, FILE *fp) { errx(1, "display regs_user not implemented yet\n"); return 0; } static int perf_display_regs_intr(perf_event_desc_t *hw, FILE *fp) { errx(1, "display regs_intr not implemented yet\n"); return 0; } static int perf_display_stack_user(perf_event_desc_t *hw, FILE *fp) { uint64_t nr; char buf[512]; size_t sz; int ret; ret = perf_read_buffer(hw, &nr, sizeof(nr)); if (ret) errx(1, "cannot user stack size"); fprintf(fp, "USER_STACK: SZ:%"PRIu64"\n", nr); /* consume content */ while (nr) { sz = nr; if (sz > sizeof(buf)) sz = sizeof(buf); ret = perf_read_buffer(hw, buf, sz); if (ret) errx(1, "cannot user stack content"); nr -= sz; } return 0; } int perf_display_sample(perf_event_desc_t *fds, int num_fds, int idx, struct perf_event_header *ehdr, FILE *fp) { perf_event_desc_t *hw; struct { uint32_t pid, tid; } pid; struct { uint64_t value, id; } grp; uint64_t time_enabled, time_running; size_t sz; uint64_t type, fmt; uint64_t val64; const char *str; int ret, e; if (!fds || !fp || !ehdr || num_fds < 0 || idx < 0 || idx >= num_fds) return -1; sz = ehdr->size - sizeof(*ehdr); hw = fds+idx; type = hw->hw.sample_type; fmt = hw->hw.read_format; if (type & PERF_SAMPLE_IDENTIFIER) { ret = perf_read_buffer_64(hw, &val64); if (ret) { warnx("cannot read IP"); return -1; } fprintf(fp, "ID:%"PRIu64" ", val64); sz -= sizeof(val64); } /* * the sample_type information is laid down * based on the PERF_RECORD_SAMPLE format specified * in the perf_event.h header file. * That order is different from the enum perf_event_sample_format */ if (type & PERF_SAMPLE_IP) { const char *xtra = " "; ret = perf_read_buffer_64(hw, &val64); if (ret) { warnx("cannot read IP"); return -1; } /* * MISC_EXACT_IP indicates that kernel is returning * th IIP of an instruction which caused the event, i.e., * no skid */ if (hw->hw.precise_ip && (ehdr->misc & PERF_RECORD_MISC_EXACT_IP)) xtra = " (exact) "; fprintf(fp, "IIP:%#016"PRIx64"%s", val64, xtra); sz -= sizeof(val64); } if (type & PERF_SAMPLE_TID) { ret = perf_read_buffer(hw, &pid, sizeof(pid)); if (ret) { warnx( "cannot read PID"); return -1; } fprintf(fp, "PID:%d TID:%d ", pid.pid, pid.tid); sz -= sizeof(pid); } if (type & PERF_SAMPLE_TIME) { ret = perf_read_buffer_64(hw, &val64); if (ret) { warnx( "cannot read time"); return -1; } fprintf(fp, "TIME:%'"PRIu64" ", val64); sz -= sizeof(val64); } if (type & PERF_SAMPLE_ADDR) { ret = perf_read_buffer_64(hw, &val64); if (ret) { warnx( "cannot read addr"); return -1; } fprintf(fp, "ADDR:%#016"PRIx64" ", val64); sz -= sizeof(val64); } if (type & PERF_SAMPLE_ID) { ret = perf_read_buffer_64(hw, &val64); if (ret) { warnx( "cannot read id"); return -1; } fprintf(fp, "ID:%"PRIu64" ", val64); sz -= sizeof(val64); } if (type & PERF_SAMPLE_STREAM_ID) { ret = perf_read_buffer_64(hw, &val64); if (ret) { warnx( "cannot read stream_id"); return -1; } fprintf(fp, "STREAM_ID:%"PRIu64" ", val64); sz -= sizeof(val64); } if (type & PERF_SAMPLE_CPU) { struct { uint32_t cpu, reserved; } cpu; ret = perf_read_buffer(hw, &cpu, sizeof(cpu)); if (ret) { warnx( "cannot read cpu"); return -1; } fprintf(fp, "CPU:%u ", cpu.cpu); sz -= sizeof(cpu); } if (type & PERF_SAMPLE_PERIOD) { ret = perf_read_buffer_64(hw, &val64); if (ret) { warnx( "cannot read period"); return -1; } fprintf(fp, "PERIOD:%'"PRIu64" ", val64); sz -= sizeof(val64); } /* struct read_format { * { u64 value; * { u64 time_enabled; } && PERF_FORMAT_ENABLED * { u64 time_running; } && PERF_FORMAT_RUNNING * { u64 id; } && PERF_FORMAT_ID * } && !PERF_FORMAT_GROUP * * { u64 nr; * { u64 time_enabled; } && PERF_FORMAT_ENABLED * { u64 time_running; } && PERF_FORMAT_RUNNING * { u64 value; * { u64 id; } && PERF_FORMAT_ID * } cntr[nr]; * } && PERF_FORMAT_GROUP * }; */ if (type & PERF_SAMPLE_READ) { uint64_t values[3]; uint64_t nr; if (fmt & PERF_FORMAT_GROUP) { ret = perf_read_buffer_64(hw, &nr); if (ret) { warnx( "cannot read nr"); return -1; } sz -= sizeof(nr); time_enabled = time_running = 1; if (fmt & PERF_FORMAT_TOTAL_TIME_ENABLED) { ret = perf_read_buffer_64(hw, &time_enabled); if (ret) { warnx( "cannot read timing info"); return -1; } sz -= sizeof(time_enabled); } if (fmt & PERF_FORMAT_TOTAL_TIME_RUNNING) { ret = perf_read_buffer_64(hw, &time_running); if (ret) { warnx( "cannot read timing info"); return -1; } sz -= sizeof(time_running); } fprintf(fp, "ENA=%'"PRIu64" RUN=%'"PRIu64" NR=%"PRIu64"\n", time_enabled, time_running, nr); values[1] = time_enabled; values[2] = time_running; while(nr--) { grp.id = -1; ret = perf_read_buffer_64(hw, &grp.value); if (ret) { warnx( "cannot read group value"); return -1; } sz -= sizeof(grp.value); if (fmt & PERF_FORMAT_ID) { ret = perf_read_buffer_64(hw, &grp.id); if (ret) { warnx( "cannot read leader id"); return -1; } sz -= sizeof(grp.id); } e = perf_id2event(fds, num_fds, grp.id); if (e == -1) str = "unknown sample event"; else str = fds[e].name; values[0] = grp.value; grp.value = perf_scale(values); fprintf(fp, "\t%'"PRIu64" %s (%"PRIu64"%s)\n", grp.value, str, grp.id, time_running != time_enabled ? ", scaled":""); } } else { time_enabled = time_running = 0; /* * this program does not use FORMAT_GROUP when there is only one event */ ret = perf_read_buffer_64(hw, &val64); if (ret) { warnx( "cannot read value"); return -1; } sz -= sizeof(val64); if (fmt & PERF_FORMAT_TOTAL_TIME_ENABLED) { ret = perf_read_buffer_64(hw, &time_enabled); if (ret) { warnx( "cannot read timing info"); return -1; } sz -= sizeof(time_enabled); } if (fmt & PERF_FORMAT_TOTAL_TIME_RUNNING) { ret = perf_read_buffer_64(hw, &time_running); if (ret) { warnx( "cannot read timing info"); return -1; } sz -= sizeof(time_running); } if (fmt & PERF_FORMAT_ID) { ret = perf_read_buffer_64(hw, &val64); if (ret) { warnx( "cannot read leader id"); return -1; } sz -= sizeof(val64); } fprintf(fp, "ENA=%'"PRIu64" RUN=%'"PRIu64"\n", time_enabled, time_running); values[0] = val64; values[1] = time_enabled; values[2] = time_running; val64 = perf_scale(values); fprintf(fp, "\t%'"PRIu64" %s %s\n", val64, fds[0].name, time_running != time_enabled ? ", scaled":""); } } if (type & PERF_SAMPLE_CALLCHAIN) { uint64_t nr, ip; ret = perf_read_buffer_64(hw, &nr); if (ret) { warnx( "cannot read callchain nr"); return -1; } sz -= sizeof(nr); while(nr--) { ret = perf_read_buffer_64(hw, &ip); if (ret) { warnx( "cannot read ip"); return -1; } sz -= sizeof(ip); fprintf(fp, "\t0x%"PRIx64"\n", ip); } } if (type & PERF_SAMPLE_RAW) { ret = __perf_handle_raw(hw); if (ret == -1) return -1; sz -= ret; } if (type & PERF_SAMPLE_BRANCH_STACK) { ret = perf_display_branch_stack(hw, fp); sz -= ret; } if (type & PERF_SAMPLE_REGS_USER) { ret = perf_display_regs_user(hw, fp); sz -= ret; } if (type & PERF_SAMPLE_STACK_USER) { ret = perf_display_stack_user(hw, fp); sz -= ret; } if (type & PERF_SAMPLE_WEIGHT) { ret = perf_read_buffer_64(hw, &val64); if (ret) { warnx( "cannot read weight"); return -1; } fprintf(fp, "WEIGHT:%'"PRIu64" ", val64); sz -= sizeof(val64); } if (type & PERF_SAMPLE_DATA_SRC) { ret = perf_read_buffer_64(hw, &val64); if (ret) { warnx( "cannot read data src"); return -1; } fprintf(fp, "DATA_SRC:%'"PRIu64" ", val64); sz -= sizeof(val64); } if (type & PERF_SAMPLE_TRANSACTION) { ret = perf_read_buffer_64(hw, &val64); if (ret) { warnx( "cannot read txn"); return -1; } fprintf(fp, "TXN:%'"PRIu64" ", val64); sz -= sizeof(val64); } if (type & PERF_SAMPLE_REGS_INTR) { ret = perf_display_regs_intr(hw, fp); sz -= ret; } /* * if we have some data left, it is because there is more * than what we know about. In fact, it is more complicated * because we may have the right size but wrong layout. But * that's the best we can do. */ if (sz) { warnx("did not correctly parse sample leftover=%zu", sz); perf_skip_buffer(hw, sz); } fputc('\n',fp); return 0; } uint64_t display_lost(perf_event_desc_t *hw, perf_event_desc_t *fds, int num_fds, FILE *fp) { struct { uint64_t id, lost; } lost; const char *str; int e, ret; ret = perf_read_buffer(hw, &lost, sizeof(lost)); if (ret) { warnx("cannot read lost info"); return 0; } e = perf_id2event(fds, num_fds, lost.id); if (e == -1) str = "unknown lost event"; else str = fds[e].name; fprintf(fp, "<<>>\n", lost.lost, str); return lost.lost; } void display_exit(perf_event_desc_t *hw, FILE *fp) { struct { pid_t pid, ppid, tid, ptid; } grp; int ret; ret = perf_read_buffer(hw, &grp, sizeof(grp)); if (ret) { warnx("cannot read exit info"); return; } fprintf(fp,"[%d] exited\n", grp.pid); } void display_freq(int mode, perf_event_desc_t *hw, FILE *fp) { struct { uint64_t time, id, stream_id; } thr; int ret; ret = perf_read_buffer(hw, &thr, sizeof(thr)); if (ret) { warnx("cannot read throttling info"); return; } fprintf(fp, "%s value=%"PRIu64" event ID=%"PRIu64"\n", mode ? "Throttled" : "Unthrottled", thr.id, thr.stream_id); } libpfm-4.9.0/perf_examples/self_pipe.c0000664000175000017500000001312313223402656017562 0ustar eranianeranian/* * self_pipe.c - dual process ping-pong example to stress PMU context switch of one process * * Copyright (c) 2008 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "perf_util.h" static struct { const char *events; int cpu; int delay; } options; int pin_cpu(pid_t pid, unsigned int cpu) { cpu_set_t mask; CPU_ZERO(&mask); CPU_SET(cpu, &mask); return sched_setaffinity(pid, sizeof(mask), &mask); } static volatile int quit; void sig_handler(int n) { quit = 1; } static void do_child(int fr, int fw) { char c; ssize_t ret; for(;;) { ret = read(fr, &c, 1); if (ret < 0) break; ret = write(fw, "c", 1); if (ret < 0) break; } printf("child exited\n"); exit(0); } static void measure(void) { perf_event_desc_t *fds = NULL; int num_fds = 0; uint64_t values[3]; ssize_t n; int i, ret; int pr[2], pw[2]; pid_t pid; char cc = '0'; ret = pfm_initialize(); if (ret != PFM_SUCCESS) err(1, "cannot initialize libpfm"); if (options.cpu == -1) { srandom(getpid()); options.cpu = random() % sysconf(_SC_NPROCESSORS_ONLN); } ret = pipe(pr); if (ret) err(1, "cannot create read pipe"); ret = pipe(pw); if (ret) err(1, "cannot create write pipe"); ret = perf_setup_list_events(options.events, &fds, &num_fds); if (ret || !num_fds) exit(1); for(i=0; i < num_fds; i++) { fds[i].hw.disabled = 1; fds[i].hw.read_format = PERF_FORMAT_SCALE; fds[i].fd = perf_event_open(&fds[i].hw, 0, -1, -1, 0); if (fds[i].fd == -1) err(1, "cannot open event %d", i); } /* * Pin to CPU0, inherited by child process. That will enforce * the ping-pionging and thus stress the PMU context switch * which is what we want */ ret = pin_cpu(getpid(), options.cpu); if (ret) err(1, "cannot pin to CPU%d", options.cpu); printf("Both processes pinned to CPU%d, running for %d seconds\n", options.cpu, options.delay); /* * create second process which is not monitoring at the moment */ switch(pid=fork()) { case -1: err(1, "cannot create child\n"); exit(1); /* not reached */ case 0: /* do not inherit session fd */ for(i=0; i < num_fds; i++) close(fds[i].fd); /* pr[]: write master, read child */ /* pw[]: read master, write child */ close(pr[1]); close(pw[0]); do_child(pr[0], pw[1]); exit(1); } close(pr[0]); close(pw[1]); /* * Let's roll now */ prctl(PR_TASK_PERF_EVENTS_ENABLE); signal(SIGALRM, sig_handler); alarm(options.delay); /* * ping pong loop */ while(!quit) { n = write(pr[1], "c", 1); if (n < 1) err(1, "write failed"); n = read(pw[0], &cc, 1); if (n < 1) err(1, "read failed"); } prctl(PR_TASK_PERF_EVENTS_DISABLE); for(i=0; i < num_fds; i++) { uint64_t val; double ratio; ret = read(fds[i].fd, values, sizeof(values)); if (ret == -1) err(1,"pfm_read error"); if (ret != sizeof(values)) errx(1, "did not read correct amount %d", ret); val = perf_scale(values); ratio = perf_scale_ratio(values); if (ratio == 1.0) printf("%20"PRIu64" %s\n", val, fds[i].name); else if (ratio == 0.0) printf("%20"PRIu64" %s (did not run: competing session)\n", val, fds[i].name); else printf("%20"PRIu64" %s (scaled from %.2f%% of time)\n", val, fds[i].name, ratio*100.0); } /* * kill child process */ kill(SIGKILL, pid); /* * close pipes */ close(pr[1]); close(pw[0]); /* * and destroy our session */ for(i=0; i < num_fds; i++) close(fds[i].fd); perf_free_fds(fds, num_fds); /* free libpfm resources cleanly */ pfm_terminate(); } static void usage(void) { printf("usage: self_pipe [-h] [-c cpu] [-d delay] [-e event1,event2,...]\n"); } int main(int argc, char **argv) { int c; options.cpu = -1; options.delay = -1; while ((c=getopt(argc, argv,"he:c:d:")) != -1) { switch(c) { case 'e': options.events = optarg; break; case 'c': options.cpu = atoi(optarg); break; case 'd': options.delay = atoi(optarg); break; case 'h': usage(); exit(0); default: errx(1, "unknown error"); } } if (!options.events) options.events = "cycles,instructions"; if (options.delay == -1) options.delay = 10; measure(); return 0; } libpfm-4.9.0/perf_examples/notify_group.c0000664000175000017500000001257713223402656020354 0ustar eranianeranian/* * notify_group.c - self-sampling multuiple events in one group * * Copyright (c) 2009 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include "perf_util.h" #define SMPL_PERIOD 2400000000ULL typedef struct { uint64_t ip; } sample_t; static volatile unsigned long notification_received; static perf_event_desc_t *fds; static int num_fds; static int buffer_pages = 1; /* size of buffer payload (must be power of 2) */ static void sigio_handler(int n, siginfo_t *info, struct sigcontext *sc) { struct perf_event_header ehdr; uint64_t ip; int id, ret; id = perf_fd2event(fds, num_fds, info->si_fd); if (id == -1) errx(1, "cannot find event for descriptor %d", info->si_fd); ret = perf_read_buffer(fds+id, &ehdr, sizeof(ehdr)); if (ret) errx(1, "cannot read event header"); if (ehdr.type != PERF_RECORD_SAMPLE) { warnx("unknown event type %d, skipping", ehdr.type); perf_skip_buffer(fds+id, ehdr.size - sizeof(ehdr)); goto skip; } ret = perf_read_buffer(fds+id, &ip, sizeof(ip)); if (ret) errx(1, "cannot read IP"); notification_received++; printf("Notification %lu: 0x%"PRIx64" fd=%d %s\n", notification_received, ip, info->si_fd, fds[id].name); skip: /* * rearm the counter for one more shot */ ret = ioctl(info->si_fd, PERF_EVENT_IOC_REFRESH, 1); if (ret == -1) err(1, "cannot refresh"); } /* * infinite loop waiting for notification to get out */ void busyloop(void) { /* * busy loop to burn CPU cycles */ for(;notification_received < 1024;) ; } int main(int argc, char **argv) { struct sigaction act; sigset_t new, old; size_t pgsz; int ret, i; ret = pfm_initialize(); if (ret != PFM_SUCCESS) errx(1, "Cannot initialize library: %s", pfm_strerror(ret)); pgsz = sysconf(_SC_PAGESIZE); /* * Install the signal handler (SIGIO) */ memset(&act, 0, sizeof(act)); act.sa_sigaction = (void *)sigio_handler; act.sa_flags = SA_SIGINFO; sigaction (SIGIO, &act, 0); sigemptyset(&old); sigemptyset(&new); sigaddset(&new, SIGIO); ret = sigprocmask(SIG_SETMASK, NULL, &old); if (ret) err(1, "sigprocmask failed"); if (sigismember(&old, SIGIO)) { warnx("program started with SIGIO masked, unmasking it now\n"); ret = sigprocmask(SIG_UNBLOCK, &new, NULL); if (ret) err(1, "sigprocmask failed"); } /* * allocates fd for us */ ret = perf_setup_list_events("cycles," "instructions," "cycles", &fds, &num_fds); if (ret || !num_fds) exit(1); fds[0].fd = -1; for(i=0; i < num_fds; i++) { /* want a notification for each sample added to the buffer */ fds[i].hw.disabled = !!i; printf("i=%d disabled=%d\n", i, fds[i].hw.disabled); fds[i].hw.wakeup_events = 1; fds[i].hw.sample_type = PERF_SAMPLE_IP; fds[i].hw.sample_period = SMPL_PERIOD; fds[i].fd = perf_event_open(&fds[i].hw, 0, -1, fds[0].fd, 0); if (fds[i].fd == -1) { warn("cannot attach event %s", fds[i].name); goto error; } fds[i].buf = mmap(NULL, (buffer_pages + 1)*pgsz, PROT_READ|PROT_WRITE, MAP_SHARED, fds[i].fd, 0); if (fds[i].buf == MAP_FAILED) err(1, "cannot mmap buffer"); /* * setup asynchronous notification on the file descriptor */ ret = fcntl(fds[i].fd, F_SETFL, fcntl(fds[i].fd, F_GETFL, 0) | O_ASYNC); if (ret == -1) err(1, "cannot set ASYNC"); /* * necessary if we want to get the file descriptor for * which the SIGIO is sent for in siginfo->si_fd. * SA_SIGINFO in itself is not enough */ ret = fcntl(fds[i].fd, F_SETSIG, SIGIO); if (ret == -1) err(1, "cannot setsig"); /* * get ownership of the descriptor */ ret = fcntl(fds[i].fd, F_SETOWN, getpid()); if (ret == -1) err(1, "cannot setown"); fds[i].pgmsk = (buffer_pages * pgsz) - 1; } for(i=0; i < num_fds; i++) { ret = ioctl(fds[i].fd, PERF_EVENT_IOC_REFRESH , 1); if (ret == -1) err(1, "cannot refresh"); } busyloop(); prctl(PR_TASK_PERF_EVENTS_DISABLE); error: /* * destroy our session */ for(i=0; i < num_fds; i++) if (fds[i].fd > -1) close(fds[i].fd); perf_free_fds(fds, num_fds); /* free libpfm resources cleanly */ pfm_terminate(); return 0; } libpfm-4.9.0/perf_examples/task_smpl.c0000664000175000017500000002340413223402656017614 0ustar eranianeranian/* * task_smpl.c - example of a task sampling another one using a randomized sampling period * * Copyright (c) 2009 Google, Inc * Contributed by Stephane Eranian * * Based on: * Copyright (c) 2003-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "perf_util.h" #define SMPL_PERIOD 240000000ULL typedef struct { int opt_no_show; int opt_inherit; int mem_mode; int branch_mode; int cpu; int mmap_pages; char *events; FILE *output_file; } options_t; static jmp_buf jbuf; static uint64_t collected_samples, lost_samples; static perf_event_desc_t *fds; static int num_fds; static options_t options; static struct option the_options[]={ { "help", 0, 0, 1}, { "no-show", 0, &options.opt_no_show, 1}, { 0, 0, 0, 0} }; static char *gen_events = "cycles,instructions"; static void cld_handler(int n) { longjmp(jbuf, 1); } int child(char **arg) { execvp(arg[0], arg); /* not reached */ return -1; } struct timeval last_read, this_read; static void process_smpl_buf(perf_event_desc_t *hw) { struct perf_event_header ehdr; int ret; for(;;) { ret = perf_read_buffer(hw, &ehdr, sizeof(ehdr)); if (ret) return; /* nothing to read */ if (options.opt_no_show) { perf_skip_buffer(hw, ehdr.size - sizeof(ehdr)); continue; } switch(ehdr.type) { case PERF_RECORD_SAMPLE: collected_samples++; ret = perf_display_sample(fds, num_fds, hw - fds, &ehdr, options.output_file); if (ret) errx(1, "cannot parse sample"); break; case PERF_RECORD_EXIT: display_exit(hw, options.output_file); break; case PERF_RECORD_LOST: lost_samples += display_lost(hw, fds, num_fds, options.output_file); break; case PERF_RECORD_THROTTLE: display_freq(1, hw, options.output_file); break; case PERF_RECORD_UNTHROTTLE: display_freq(0, hw, options.output_file); break; default: printf("unknown sample type %d\n", ehdr.type); perf_skip_buffer(hw, ehdr.size - sizeof(ehdr)); } } } int mainloop(char **arg) { static uint64_t ovfl_count; /* static to avoid setjmp issue */ struct pollfd pollfds[1]; sigset_t bmask; int go[2], ready[2]; size_t pgsz; size_t map_size = 0; pid_t pid; int status, ret; int i; char buf; if (pfm_initialize() != PFM_SUCCESS) errx(1, "libpfm initialization failed\n"); pgsz = sysconf(_SC_PAGESIZE); map_size = (options.mmap_pages+1)*pgsz; /* * does allocate fds */ ret = perf_setup_list_events(options.events, &fds, &num_fds); if (ret || !num_fds) errx(1, "cannot setup event list"); memset(pollfds, 0, sizeof(pollfds)); ret = pipe(ready); if (ret) err(1, "cannot create pipe ready"); ret = pipe(go); if (ret) err(1, "cannot create pipe go"); /* * Create the child task */ if ((pid=fork()) == -1) err(1, "cannot fork process\n"); if (pid == 0) { close(ready[0]); close(go[1]); /* * let the parent know we exist */ close(ready[1]); if (read(go[0], &buf, 1) == -1) err(1, "unable to read go_pipe"); exit(child(arg)); } close(ready[1]); close(go[0]); if (read(ready[0], &buf, 1) == -1) err(1, "unable to read child_ready_pipe"); close(ready[0]); fds[0].fd = -1; if (!fds[0].hw.sample_period) errx(1, "need to set sampling period or freq on first event, use :period= or :freq="); for(i=0; i < num_fds; i++) { if (i == 0) { fds[i].hw.disabled = 1; fds[i].hw.enable_on_exec = 1; /* start immediately */ } else fds[i].hw.disabled = 0; if (options.opt_inherit) fds[i].hw.inherit = 1; if (fds[i].hw.sample_period) { /* * set notification threshold to be halfway through the buffer */ fds[i].hw.wakeup_watermark = (options.mmap_pages*pgsz) / 2; fds[i].hw.watermark = 1; fds[i].hw.sample_type = PERF_SAMPLE_IP|PERF_SAMPLE_TID|PERF_SAMPLE_READ|PERF_SAMPLE_TIME|PERF_SAMPLE_PERIOD; /* * if we have more than one event, then record event identifier to help with parsing */ if (num_fds > 1) fds[i].hw.sample_type |= PERF_SAMPLE_IDENTIFIER; fprintf(options.output_file,"%s period=%"PRIu64" freq=%d\n", fds[i].name, fds[i].hw.sample_period, fds[i].hw.freq); fds[i].hw.read_format = PERF_FORMAT_SCALE; if (fds[i].hw.freq) fds[i].hw.sample_type |= PERF_SAMPLE_PERIOD; if (options.mem_mode) fds[i].hw.sample_type |= PERF_SAMPLE_WEIGHT | PERF_SAMPLE_DATA_SRC | PERF_SAMPLE_ADDR; if (options.branch_mode) { fds[i].hw.sample_type |= PERF_SAMPLE_BRANCH_STACK; fds[i].hw.branch_sample_type = PERF_SAMPLE_BRANCH_ANY; } } /* * we are grouping the events, so there may be a limit */ fds[i].fd = perf_event_open(&fds[i].hw, pid, options.cpu, fds[0].fd, 0); if (fds[i].fd == -1) { if (fds[i].hw.precise_ip) err(1, "cannot attach event %s: precise mode may not be supported", fds[i].name); err(1, "cannot attach event %s", fds[i].name); } } /* * kernel adds the header page to the size of the mmapped region */ fds[0].buf = mmap(NULL, map_size, PROT_READ|PROT_WRITE, MAP_SHARED, fds[0].fd, 0); if (fds[0].buf == MAP_FAILED) err(1, "cannot mmap buffer"); /* does not include header page */ fds[0].pgmsk = (options.mmap_pages*pgsz)-1; /* * send samples for all events to first event's buffer */ for (i = 1; i < num_fds; i++) { if (!fds[i].hw.sample_period) continue; ret = ioctl(fds[i].fd, PERF_EVENT_IOC_SET_OUTPUT, fds[0].fd); if (ret) err(1, "cannot redirect sampling output"); } if (num_fds > 1 && fds[0].fd > -1) { for(i = 0; i < num_fds; i++) { /* * read the event identifier using ioctl * new method replaced the trick with PERF_FORMAT_GROUP + PERF_FORMAT_ID + read() */ ret = ioctl(fds[i].fd, PERF_EVENT_IOC_ID, &fds[i].id); if (ret == -1) err(1, "cannot read ID"); fprintf(options.output_file,"ID %"PRIu64" %s\n", fds[i].id, fds[i].name); } } pollfds[0].fd = fds[0].fd; pollfds[0].events = POLLIN; for(i=0; i < num_fds; i++) { ret = ioctl(fds[i].fd, PERF_EVENT_IOC_ENABLE, 0); if (ret) err(1, "cannot enable event %s\n", fds[i].name); } signal(SIGCHLD, cld_handler); close(go[1]); if (setjmp(jbuf) == 1) goto terminate_session; sigemptyset(&bmask); sigaddset(&bmask, SIGCHLD); /* * core loop */ for(;;) { ret = poll(pollfds, 1, -1); if (ret < 0 && errno == EINTR) break; ovfl_count++; ret = sigprocmask(SIG_SETMASK, &bmask, NULL); if (ret) err(1, "setmask"); process_smpl_buf(&fds[0]); ret = sigprocmask(SIG_UNBLOCK, &bmask, NULL); if (ret) err(1, "unblock"); } terminate_session: /* * cleanup child */ wait4(pid, &status, 0, NULL); for(i=0; i < num_fds; i++) close(fds[i].fd); /* check for partial event buffer */ process_smpl_buf(&fds[0]); munmap(fds[0].buf, map_size); perf_free_fds(fds, num_fds); fprintf(options.output_file, "%"PRIu64" samples collected in %"PRIu64" poll events, %"PRIu64" lost samples\n", collected_samples, ovfl_count, lost_samples); /* free libpfm resources cleanly */ pfm_terminate(); fclose(options.output_file); return 0; } static void usage(void) { printf("usage: task_smpl [-h] [--help] [-i] [-c cpu] [-m mmap_pages] [-M] [-b] [-o output_file] [-e event1,...,eventn] cmd\n"); } int main(int argc, char **argv) { int c; setlocale(LC_ALL, ""); options.cpu = -1; options.output_file=stdout; while ((c=getopt_long(argc, argv,"+he:m:ic:o:Mb", the_options, 0)) != -1) { switch(c) { case 0: continue; case 'e': if (options.events) errx(1, "events specified twice\n"); options.events = optarg; break; case 'i': options.opt_inherit = 1; break; case 'm': if (options.mmap_pages) errx(1, "mmap pages already set\n"); options.mmap_pages = atoi(optarg); break; case 'M': options.mem_mode = 1; break; case 'b': options.branch_mode = 1; break; case 'c': options.cpu = atoi(optarg); break; case 'o': options.output_file=fopen(optarg,"w"); if (options.output_file==NULL) { printf("Invalid filename %s\n", optarg); exit(0); } break; case 'h': usage(); exit(0); default: errx(1, "unknown option"); } } if (argv[optind] == NULL) errx(1, "you must specify a command to execute\n"); if (!options.events) options.events = strdup(gen_events); if (!options.mmap_pages) options.mmap_pages = 1; if (options.mmap_pages > 1 && ((options.mmap_pages) & 0x1)) errx(1, "number of pages must be power of 2\n"); return mainloop(argv+optind); } libpfm-4.9.0/perf_examples/syst.c0000664000175000017500000001264613223402656016627 0ustar eranianeranian/* * syst.c - example of a simple system wide monitoring program * * Copyright (c) 2002-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include #include #include #include #include #include #include "perf_util.h" typedef struct { const char *events; int delay; int excl; int cpu; int group; } options_t; static options_t options; static perf_event_desc_t **all_fds; static int *num_fds; void setup_cpu(int cpu) { perf_event_desc_t *fds; int i, ret; ret = perf_setup_list_events(options.events, &all_fds[cpu], &num_fds[cpu]); if (ret || (num_fds == 0)) errx(1, "cannot setup events\n"); fds = all_fds[cpu]; /* temp */ fds[0].fd = -1; for(i=0; i < num_fds[cpu]; i++) { fds[i].hw.disabled = options.group ? !i : 1; if (options.excl && ((options.group && !i) || (!options.group))) fds[i].hw.exclusive = 1; fds[i].hw.disabled = options.group ? !i : 1; /* request timing information necessary for scaling counts */ fds[i].hw.read_format = PERF_FORMAT_SCALE; fds[i].fd = perf_event_open(&fds[i].hw, -1, cpu, (options.group ? fds[0].fd : -1), 0); if (fds[i].fd == -1) err(1, "cannot attach event to CPU%d %s", cpu, fds[i].name); } } void measure(void) { perf_event_desc_t *fds; long lret; int c, cmin, cmax, ncpus; int i, ret, l; printf("\n", options.delay); cmin = 0; lret = sysconf(_SC_NPROCESSORS_ONLN); if (lret < 0) err(1, "cannot get number of online processors"); cmax = (int)lret; ncpus = cmax; if (options.cpu != -1) { cmin = options.cpu; cmax = cmin + 1; } all_fds = calloc(ncpus, sizeof(perf_event_desc_t *)); num_fds = calloc(ncpus, sizeof(int)); if (!all_fds || !num_fds) err(1, "cannot allocate memory for internal structures"); for(c=cmin ; c < cmax; c++) setup_cpu(c); /* * FIX this for hotplug CPU */ for(c=cmin ; c < cmax; c++) { fds = all_fds[c]; if (options.group) ret = ioctl(fds[0].fd, PERF_EVENT_IOC_ENABLE, 0); else for(i=0; i < num_fds[c]; i++) { ret = ioctl(fds[i].fd, PERF_EVENT_IOC_ENABLE, 0); if (ret) err(1, "cannot enable event %s\n", fds[i].name); } } for(l=0; l < options.delay; l++) { sleep(1); puts("------------------------"); for(c = cmin; c < cmax; c++) { fds = all_fds[c]; for(i=0; i < num_fds[c]; i++) { uint64_t val, delta; double ratio; ret = read(fds[i].fd, fds[i].values, sizeof(fds[i].values)); if (ret != sizeof(fds[i].values)) { if (ret == -1) err(1, "cannot read event %d:%d", i, ret); else warnx("could not read event%d", i); } /* * scaling because we may be sharing the PMU and * thus may be multiplexed */ val = perf_scale(fds[i].values); ratio = perf_scale_ratio(fds[i].values); delta = perf_scale_delta(fds[i].values, fds[i].prev_values); printf("CPU%d val=%-20"PRIu64" %-20"PRIu64" raw=%"PRIu64" ena=%"PRIu64" run=%"PRIu64" ratio=%.2f %s\n", c, val, delta, fds[i].values[0], fds[i].values[1], fds[i].values[2], ratio, fds[i].name); fds[i].prev_values[0] = fds[i].values[0]; fds[i].prev_values[1] = fds[i].values[1]; fds[i].prev_values[2] = fds[i].values[2]; } } } for(c = cmin; c < cmax; c++) { fds = all_fds[c]; for(i=0; i < num_fds[c]; i++) close(fds[i].fd); perf_free_fds(fds, num_fds[c]); } } static void usage(void) { printf("usage: syst [-c cpu] [-x] [-h] [-d delay] [-g] [-e event1,event2,...]\n"); } int main(int argc, char **argv) { int c, ret; options.cpu = -1; while ((c=getopt(argc, argv,"hc:e:d:gx")) != -1) { switch(c) { case 'x': options.excl = 1; break; case 'e': options.events = optarg; break; case 'c': options.cpu = atoi(optarg); break; case 'g': options.group = 1; break; case 'd': options.delay = atoi(optarg); break; case 'h': usage(); exit(0); default: errx(1, "unknown error"); } } if (!options.delay) options.delay = 20; if (!options.events) options.events = "cycles,instructions"; ret = pfm_initialize(); if (ret != PFM_SUCCESS) errx(1, "libpfm initialization failed: %s\n", pfm_strerror(ret)); measure(); /* free libpfm resources cleanly */ pfm_terminate(); return 0; } libpfm-4.9.0/include/0000775000175000017500000000000013223402656014241 5ustar eranianeranianlibpfm-4.9.0/include/Makefile0000664000175000017500000000305713223402656015706 0ustar eranianeranian# # Copyright (c) 2002-2006 Hewlett-Packard Development Company, L.P. # Contributed by Stephane Eranian # # Permission is hereby granted, free of charge, to any person obtaining a copy # of this software and associated documentation files (the "Software"), to deal # in the Software without restriction, including without limitation the rights # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies # of the Software, and to permit persons to whom the Software is furnished to do so, # subject to the following conditions: # # The above copyright notice and this permission notice shall be included in all # copies or substantial portions of the Software. # # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, # INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A # PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT # HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF # CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE # OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # TOPDIR := $(shell if [ "$$PWD" != "" ]; then echo $$PWD; else pwd; fi)/.. include $(TOPDIR)/config.mk include $(TOPDIR)/rules.mk HEADERS= perfmon/pfmlib.h \ perfmon/perf_event.h \ perfmon/pfmlib_perf_event.h dir: -mkdir -p $(DESTDIR)$(INCDIR)/perfmon install: dir $(INSTALL) -m 644 $(HEADERS) $(DESTDIR)$(INCDIR)/perfmon .PHONY: all clean distclean depend dir libpfm-4.9.0/include/perfmon/0000775000175000017500000000000013223402656015707 5ustar eranianeranianlibpfm-4.9.0/include/perfmon/err.h0000775000175000017500000000325613223402656016661 0ustar eranianeranian/* * err.h: substitute header for compiling on Windows with MingGW * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef __PFM_ERR_H__ #define __PFM_ERR_H__ #ifndef PFMLIB_WINDOWS #include #else /* PFMLIB_WINDOWS */ #define warnx(...) do { \ fprintf (stderr, __VA_ARGS__); \ fprintf (stderr, "\n"); \ } while (0) #define errx(code, ...) do { \ fprintf (stderr, __VA_ARGS__); \ fprintf (stderr, "\n"); \ exit (code); \ } while (0) #define err(code, ...) do { \ fprintf (stderr, __VA_ARGS__); \ fprintf (stderr, " : %s\n", strerror(errno)); \ exit (code); \ } while (0) #endif #endif /* __PFM_ERR_H__ */ libpfm-4.9.0/include/perfmon/perf_event.h0000664000175000017500000004171713223402656020227 0ustar eranianeranian/* * Copyright (c) 2011 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef __PERFMON_PERF_EVENT_H__ #define __PERFMON_PERF_EVENT_H__ #pragma GCC visibility push(default) #include #include /* for syscall numbers */ #include #include /* for syscall stub macros */ #include /* for _IO */ #include /* for prctl() comamnds */ #ifdef __cplusplus extern "C" { #endif /* * avoid clashes with actual kernel header file */ #if !(defined(_LINUX_PERF_EVENT_H) || defined(_UAPI_LINUX_PERF_EVENT_H)) /* * attr->type field values */ enum perf_type_id { PERF_TYPE_HARDWARE = 0, PERF_TYPE_SOFTWARE = 1, PERF_TYPE_TRACEPOINT = 2, PERF_TYPE_HW_CACHE = 3, PERF_TYPE_RAW = 4, PERF_TYPE_BREAKPOINT = 5, PERF_TYPE_MAX }; /* * attr->config values for generic HW PMU events * * they get mapped onto actual events by the kernel */ enum perf_hw_id { PERF_COUNT_HW_CPU_CYCLES = 0, PERF_COUNT_HW_INSTRUCTIONS = 1, PERF_COUNT_HW_CACHE_REFERENCES = 2, PERF_COUNT_HW_CACHE_MISSES = 3, PERF_COUNT_HW_BRANCH_INSTRUCTIONS = 4, PERF_COUNT_HW_BRANCH_MISSES = 5, PERF_COUNT_HW_BUS_CYCLES = 6, PERF_COUNT_HW_STALLED_CYCLES_FRONTEND = 7, PERF_COUNT_HW_STALLED_CYCLES_BACKEND = 8, PERF_COUNT_HW_REF_CPU_CYCLES = 9, PERF_COUNT_HW_MAX }; /* * attr->config values for generic HW cache events * * they get mapped onto actual events by the kernel */ enum perf_hw_cache_id { PERF_COUNT_HW_CACHE_L1D = 0, PERF_COUNT_HW_CACHE_L1I = 1, PERF_COUNT_HW_CACHE_LL = 2, PERF_COUNT_HW_CACHE_DTLB = 3, PERF_COUNT_HW_CACHE_ITLB = 4, PERF_COUNT_HW_CACHE_BPU = 5, PERF_COUNT_HW_CACHE_NODE = 6, PERF_COUNT_HW_CACHE_MAX }; enum perf_hw_cache_op_id { PERF_COUNT_HW_CACHE_OP_READ = 0, PERF_COUNT_HW_CACHE_OP_WRITE = 1, PERF_COUNT_HW_CACHE_OP_PREFETCH = 2, PERF_COUNT_HW_CACHE_OP_MAX }; enum perf_hw_cache_op_result_id { PERF_COUNT_HW_CACHE_RESULT_ACCESS = 0, PERF_COUNT_HW_CACHE_RESULT_MISS = 1, PERF_COUNT_HW_CACHE_RESULT_MAX }; /* * attr->config values for SW events */ enum perf_sw_ids { PERF_COUNT_SW_CPU_CLOCK = 0, PERF_COUNT_SW_TASK_CLOCK = 1, PERF_COUNT_SW_PAGE_FAULTS = 2, PERF_COUNT_SW_CONTEXT_SWITCHES = 3, PERF_COUNT_SW_CPU_MIGRATIONS = 4, PERF_COUNT_SW_PAGE_FAULTS_MIN = 5, PERF_COUNT_SW_PAGE_FAULTS_MAJ = 6, PERF_COUNT_SW_ALIGNMENT_FAULTS = 7, PERF_COUNT_SW_EMULATION_FAULTS = 8, PERF_COUNT_SW_DUMMY = 9, PERF_COUNT_SW_BPF_OUTPUT = 10, PERF_COUNT_SW_MAX }; /* * attr->sample_type values */ enum perf_event_sample_format { PERF_SAMPLE_IP = 1U << 0, PERF_SAMPLE_TID = 1U << 1, PERF_SAMPLE_TIME = 1U << 2, PERF_SAMPLE_ADDR = 1U << 3, PERF_SAMPLE_READ = 1U << 4, PERF_SAMPLE_CALLCHAIN = 1U << 5, PERF_SAMPLE_ID = 1U << 6, PERF_SAMPLE_CPU = 1U << 7, PERF_SAMPLE_PERIOD = 1U << 8, PERF_SAMPLE_STREAM_ID = 1U << 9, PERF_SAMPLE_RAW = 1U << 10, PERF_SAMPLE_BRANCH_STACK = 1U << 11, PERF_SAMPLE_REGS_USER = 1U << 12, PERF_SAMPLE_STACK_USER = 1U << 13, PERF_SAMPLE_WEIGHT = 1U << 14, PERF_SAMPLE_DATA_SRC = 1U << 15, PERF_SAMPLE_IDENTIFIER = 1U << 16, PERF_SAMPLE_TRANSACTION = 1U << 17, PERF_SAMPLE_REGS_INTR = 1U << 18, PERF_SAMPLE_PHYS_ADDR = 1U << 19, PERF_SAMPLE_MAX = 1U << 19, }; enum { PERF_TXN_ELISION = (1 << 0), PERF_TXN_TRANSACTION = (1 << 1), PERF_TXN_SYNC = (1 << 2), PERF_TXN_ASYNC = (1 << 3), PERF_TXN_RETRY = (1 << 4), PERF_TXN_CONFLICT = (1 << 5), PERF_TXN_CAPACITY_WRITE = (1 << 6), PERF_TXN_CAPACITY_READ = (1 << 7), PERF_TXN_MAX = (1 << 8), PERF_TXN_ABORT_MASK = (0xffffffffULL << 32), PERF_TXN_ABORT_SHIFT = 32, }; /* * branch_sample_type values */ enum perf_branch_sample_type_shift { PERF_SAMPLE_BRANCH_USER_SHIFT = 0, PERF_SAMPLE_BRANCH_KERNEL_SHIFT = 1, PERF_SAMPLE_BRANCH_HV_SHIFT = 2, PERF_SAMPLE_BRANCH_ANY_SHIFT = 3, PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT = 4, PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT = 5, PERF_SAMPLE_BRANCH_IND_CALL_SHIFT = 6, PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT = 7, PERF_SAMPLE_BRANCH_IN_TX_SHIFT = 8, PERF_SAMPLE_BRANCH_NO_TX_SHIFT = 9, PERF_SAMPLE_BRANCH_COND_SHIFT = 10, PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT = 11, PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT = 12, PERF_SAMPLE_BRANCH_CALL_SHIFT = 13, PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT = 14, PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT = 15, PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT = 16, PERF_SAMPLE_BRANCH_MAX_SHIFT /* non-ABI */ }; enum perf_branch_sample_type { PERF_SAMPLE_BRANCH_USER = 1U << PERF_SAMPLE_BRANCH_USER_SHIFT, PERF_SAMPLE_BRANCH_KERNEL = 1U << PERF_SAMPLE_BRANCH_KERNEL_SHIFT, PERF_SAMPLE_BRANCH_HV = 1U << PERF_SAMPLE_BRANCH_HV_SHIFT, PERF_SAMPLE_BRANCH_ANY = 1U << PERF_SAMPLE_BRANCH_ANY_SHIFT, PERF_SAMPLE_BRANCH_ANY_CALL = 1U << PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT, PERF_SAMPLE_BRANCH_ANY_RETURN = 1U << PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT, PERF_SAMPLE_BRANCH_IND_CALL = 1U << PERF_SAMPLE_BRANCH_IND_CALL_SHIFT, PERF_SAMPLE_BRANCH_ABORT_TX = 1U << PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT, PERF_SAMPLE_BRANCH_IN_TX = 1U << PERF_SAMPLE_BRANCH_IN_TX_SHIFT, PERF_SAMPLE_BRANCH_NO_TX = 1U << PERF_SAMPLE_BRANCH_NO_TX_SHIFT, PERF_SAMPLE_BRANCH_COND = 1U << PERF_SAMPLE_BRANCH_COND_SHIFT, PERF_SAMPLE_BRANCH_CALL_STACK = 1U << PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT, PERF_SAMPLE_BRANCH_IND_JUMP = 1U << PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT, PERF_SAMPLE_BRANCH_CALL = 1U << PERF_SAMPLE_BRANCH_IND_CALL_SHIFT, PERF_SAMPLE_BRANCH_NO_FLAGS = 1U << PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT, PERF_SAMPLE_BRANCH_NO_CYCLES = 1U << PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT, PERF_SAMPLE_BRANCH_TYPE_SAVE = 1U << PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT, PERF_SAMPLE_BRANCH_MAX = 1U << PERF_SAMPLE_BRANCH_MAX_SHIFT, }; enum perf_sample_regs_abi { PERF_SAMPLE_REGS_ABI_NONE = 0, PERF_SAMPLE_REGS_ABI_32 = 1, PERF_SAMPLE_REGS_ABI_64 = 2, }; /* * attr->read_format values */ enum perf_event_read_format { PERF_FORMAT_TOTAL_TIME_ENABLED = 1U << 0, PERF_FORMAT_TOTAL_TIME_RUNNING = 1U << 1, PERF_FORMAT_ID = 1U << 2, PERF_FORMAT_GROUP = 1U << 3, PERF_FORMAT_MAX = 1U << 4, }; #define PERF_ATTR_SIZE_VER0 64 /* sizeof first published struct */ #define PERF_ATTR_SIZE_VER1 72 /* add: config2 */ #define PERF_ATTR_SIZE_VER2 80 /* add: branch_sample_type */ #define PERF_ATTR_SIZE_VER3 96 /* add: sample_regs_user */ /* add: sample_stack_user */ #define PERF_ATTR_SIZE_VER4 104 /* add: sample_regs_intr */ #define PERF_ATTR_SIZE_VER5 112 /* add: aux_watermark */ /* * SWIG doesn't deal well with anonymous nested structures * so we add names for the nested structure only when swig * is used. */ #ifdef SWIG #define SWIG_NAME(x) x #else #define SWIG_NAME(x) #endif /* SWIG */ /* * perf_event_attr struct passed to perf_event_open() */ typedef struct perf_event_attr { uint32_t type; uint32_t size; uint64_t config; union { uint64_t sample_period; uint64_t sample_freq; } SWIG_NAME(sample); uint64_t sample_type; uint64_t read_format; uint64_t disabled : 1, inherit : 1, pinned : 1, exclusive : 1, exclude_user : 1, exclude_kernel : 1, exclude_hv : 1, exclude_idle : 1, mmap : 1, comm : 1, freq : 1, inherit_stat : 1, enable_on_exec : 1, task : 1, watermark : 1, precise_ip : 2, mmap_data : 1, sample_id_all : 1, exclude_host : 1, exclude_guest : 1, exclude_callchain_kernel : 1, exclude_callchain_user : 1, mmap2 : 1, comm_exec : 1, use_clockid : 1, context_switch : 1, write_backward : 1, namespaces : 1, __reserved_1 : 35; union { uint32_t wakeup_events; uint32_t wakeup_watermark; } SWIG_NAME(wakeup); uint32_t bp_type; union { uint64_t bp_addr; uint64_t config1; /* extend config */ } SWIG_NAME(bpa); union { uint64_t bp_len; uint64_t config2; /* extend config1 */ } SWIG_NAME(bpb); uint64_t branch_sample_type; uint64_t sample_regs_user; uint32_t sample_stack_user; int32_t clockid; uint64_t sample_regs_intr; uint32_t aux_watermark; uint32_t __reserved_2; } perf_event_attr_t; struct perf_branch_entry { uint64_t from; uint64_t to; uint64_t mispred:1, /* target mispredicted */ predicted:1,/* target predicted */ in_tx:1, /* in transaction */ abort:1, /* transaction abort */ cycles:16, /* cycle count to last branch */ type:4, /* branch type */ reserved:40; }; /* * branch stack layout: * nr: number of taken branches stored in entries[] * * Note that nr can vary from sample to sample * branches (to, from) are stored from most recent * to least recent, i.e., entries[0] contains the most * recent branch. */ struct perf_branch_stack { uint64_t nr; struct perf_branch_entry entries[0]; }; /* * perf_events ioctl commands, use with event fd */ #define PERF_EVENT_IOC_ENABLE _IO ('$', 0) #define PERF_EVENT_IOC_DISABLE _IO ('$', 1) #define PERF_EVENT_IOC_REFRESH _IO ('$', 2) #define PERF_EVENT_IOC_RESET _IO ('$', 3) #define PERF_EVENT_IOC_PERIOD _IOW('$', 4, uint64_t) #define PERF_EVENT_IOC_SET_OUTPUT _IO ('$', 5) #define PERF_EVENT_IOC_SET_FILTER _IOW('$', 6, char *) #define PERF_EVENT_IOC_ID _IOR('$', 7, uint64_t *) #define PERF_EVENT_IOC_SET_BPF _IOW('$', 8, uint32_t) #define PERF_EVENT_IOC_PAUSE_OUTPUT _IOW('$', 9, __u32) /* * ioctl() 3rd argument */ enum perf_event_ioc_flags { PERF_IOC_FLAG_GROUP = 1U << 0, }; /* * mmapped sampling buffer layout * occupies a 4kb page */ struct perf_event_mmap_page { uint32_t version; uint32_t compat_version; uint32_t lock; uint32_t index; int64_t offset; uint64_t time_enabled; uint64_t time_running; union { uint64_t capabilities; struct { uint64_t cap_bit0:1, cap_bit0_is_deprecated:1, cap_usr_rdpmc:1, cap_user_time:1, cap_user_time_zero:1, cap_____res:59; } SWIG_NAME(rdmap_cap_s); } SWIG_NAME(rdmap_cap_u); uint16_t pmc_width; uint16_t time_shift; uint32_t time_mult; uint64_t time_offset; uint64_t time_zero; uint32_t size; uint8_t __reserved[118*8+4]; uint64_t data_head; uint64_t data_tail; uint64_t data_offset; uint64_t data_size; uint64_t aux_head; uint64_t aux_tail; uint64_t aux_offset; uint64_t aux_size; }; /* * sampling buffer event header */ struct perf_event_header { uint32_t type; uint16_t misc; uint16_t size; }; /* * event header misc field values */ #define PERF_EVENT_MISC_CPUMODE_MASK (3 << 0) #define PERF_EVENT_MISC_CPUMODE_UNKNOWN (0 << 0) #define PERF_EVENT_MISC_KERNEL (1 << 0) #define PERF_EVENT_MISC_USER (2 << 0) #define PERF_EVENT_MISC_HYPERVISOR (3 << 0) #define PERF_RECORD_MISC_GUEST_KERNEL (4 << 0) #define PERF_RECORD_MISC_GUEST_USER (5 << 0) #define PERF_RECORD_MISC_PROC_MAP_PARSE_TIMEOUT (1 << 12) #define PERF_RECORD_MISC_MMAP_DATA (1 << 13) #define PERF_RECORD_MISC_COMM_EXEC (1 << 13) #define PERF_RECORD_MISC_EXACT (1 << 14) #define PERF_RECORD_MISC_EXACT_IP (1 << 14) #define PERF_RECORD_MISC_EXT_RESERVED (1 << 15) /* * header->type values */ enum perf_event_type { PERF_RECORD_MMAP = 1, PERF_RECORD_LOST = 2, PERF_RECORD_COMM = 3, PERF_RECORD_EXIT = 4, PERF_RECORD_THROTTLE = 5, PERF_RECORD_UNTHROTTLE = 6, PERF_RECORD_FORK = 7, PERF_RECORD_READ = 8, PERF_RECORD_SAMPLE = 9, PERF_RECORD_MMAP2 = 10, PERF_RECORD_AUX = 11, PERF_RECORD_ITRACE_START = 12, PERF_RECORD_LOST_SAMPLES = 13, PERF_RECORD_SWITCH = 14, PERF_RECORD_SWITCH_CPU_WIDE = 15, PERF_RECORD_NAMESPACES = 16, PERF_RECORD_MAX }; enum perf_callchain_context { PERF_CONTEXT_HV = (uint64_t)-32, PERF_CONTEXT_KERNEL = (uint64_t)-128, PERF_CONTEXT_USER = (uint64_t)-512, PERF_CONTEXT_GUEST = (uint64_t)-2048, PERF_CONTEXT_GUEST_KERNEL = (uint64_t)-2176, PERF_CONTEXT_GUEST_USER = (uint64_t)-2560, PERF_CONTEXT_MAX = (uint64_t)-4095, }; #define PERF_AUX_FLAG_TRUNCATED 0x01 #define PERF_AUX_FLAG_OVERWRITE 0x02 /* * flags for perf_event_open() */ #define PERF_FLAG_FD_NO_GROUP (1U << 0) #define PERF_FLAG_FD_OUTPUT (1U << 1) #define PERF_FLAG_PID_CGROUP (1U << 2) #define PERF_FLAG_FD_CLOEXEC (1UL << 3) #endif /* _LINUX_PERF_EVENT_H */ #ifndef __NR_perf_event_open #ifdef __x86_64__ # define __NR_perf_event_open 298 #endif #ifdef __i386__ # define __NR_perf_event_open 336 #endif #ifdef __powerpc__ # define __NR_perf_event_open 319 #endif #ifdef __s390__ # define __NR_perf_event_open 331 #endif #ifdef __arm__ #if defined(__ARM_EABI__) || defined(__thumb__) # define __NR_perf_event_open 364 #else # define __NR_perf_event_open (0x900000+364) #endif #endif #ifdef __mips__ #if _MIPS_SIM == _MIPS_SIM_ABI32 # define __NR_perf_event_open __NR_Linux + 333 #elif _MIPS_SIM == _MIPS_SIM_ABI64 # define __NR_perf_event_open __NR_Linux + 292 #else /* if _MIPS_SIM == MIPS_SIM_NABI32 */ # define __NR_perf_event_open __NR_Linux + 296 #endif #endif #endif /* __NR_perf_event_open */ /* * perf_event_open() syscall stub */ static inline int perf_event_open( struct perf_event_attr *hw_event_uptr, pid_t pid, int cpu, int group_fd, unsigned long flags) { return syscall( __NR_perf_event_open, hw_event_uptr, pid, cpu, group_fd, flags); } /* * compensate for some distros which do not * have recent enough linux/prctl.h */ #ifndef PR_TASK_PERF_EVENTS_DISABLE #define PR_TASK_PERF_EVENTS_ENABLE 32 #define PR_TASK_PERF_EVENTS_DISABLE 31 #endif /* handle case of older system perf_event.h included before this file */ #ifndef PERF_MEM_OP_NA union perf_mem_data_src { uint64_t val; struct { uint64_t mem_op:5, /* type of opcode */ mem_lvl:14, /* memory hierarchy level */ mem_snoop:5, /* snoop mode */ mem_lock:2, /* lock instr */ mem_dtlb:7, /* tlb access */ mem_rsvd:31; }; }; /* type of opcode (load/store/prefetch,code) */ #define PERF_MEM_OP_NA 0x01 /* not available */ #define PERF_MEM_OP_LOAD 0x02 /* load instruction */ #define PERF_MEM_OP_STORE 0x04 /* store instruction */ #define PERF_MEM_OP_PFETCH 0x08 /* prefetch */ #define PERF_MEM_OP_EXEC 0x10 /* code (execution) */ #define PERF_MEM_OP_SHIFT 0 /* memory hierarchy (memory level, hit or miss) */ #define PERF_MEM_LVL_NA 0x01 /* not available */ #define PERF_MEM_LVL_HIT 0x02 /* hit level */ #define PERF_MEM_LVL_MISS 0x04 /* miss level */ #define PERF_MEM_LVL_L1 0x08 /* L1 */ #define PERF_MEM_LVL_LFB 0x10 /* Line Fill Buffer */ #define PERF_MEM_LVL_L2 0x20 /* L2 */ #define PERF_MEM_LVL_L3 0x40 /* L3 */ #define PERF_MEM_LVL_LOC_RAM 0x80 /* Local DRAM */ #define PERF_MEM_LVL_REM_RAM1 0x100 /* Remote DRAM (1 hop) */ #define PERF_MEM_LVL_REM_RAM2 0x200 /* Remote DRAM (2 hops) */ #define PERF_MEM_LVL_REM_CCE1 0x400 /* Remote Cache (1 hop) */ #define PERF_MEM_LVL_REM_CCE2 0x800 /* Remote Cache (2 hops) */ #define PERF_MEM_LVL_IO 0x1000 /* I/O memory */ #define PERF_MEM_LVL_UNC 0x2000 /* Uncached memory */ #define PERF_MEM_LVL_SHIFT 5 #define PERF_MEM_REMOTE_REMOTE 0x01 /* Remote */ #define PERF_MEM_REMOTE_SHIFT 37 /* snoop mode */ #define PERF_MEM_SNOOP_NA 0x01 /* not available */ #define PERF_MEM_SNOOP_NONE 0x02 /* no snoop */ #define PERF_MEM_SNOOP_HIT 0x04 /* snoop hit */ #define PERF_MEM_SNOOP_MISS 0x08 /* snoop miss */ #define PERF_MEM_SNOOP_HITM 0x10 /* snoop hit modified */ #define PERF_MEM_SNOOP_SHIFT 19 #define PERF_MEM_SNOOPX_FWD 0x01 /* forward */ #define PERF_MEM_SNOOPX_SHIFT 37 /* locked instruction */ #define PERF_MEM_LOCK_NA 0x01 /* not available */ #define PERF_MEM_LOCK_LOCKED 0x02 /* locked transaction */ #define PERF_MEM_LOCK_SHIFT 24 /* TLB access */ #define PERF_MEM_TLB_NA 0x01 /* not available */ #define PERF_MEM_TLB_HIT 0x02 /* hit level */ #define PERF_MEM_TLB_MISS 0x04 /* miss level */ #define PERF_MEM_TLB_L1 0x08 /* L1 */ #define PERF_MEM_TLB_L2 0x10 /* L2 */ #define PERF_MEM_TLB_WK 0x20 /* Hardware Walker*/ #define PERF_MEM_TLB_OS 0x40 /* OS fault handler */ #define PERF_MEM_TLB_SHIFT 26 #define PERF_MEM_S(a, s) \ (((u64)PERF_MEM_##a##_##s) << PERF_MEM_##a##_SHIFT) #endif /* PERF_MEM_OP_NA */ #ifdef __cplusplus /* extern C */ } #endif #pragma GCC visibility pop #endif /* __PERFMON_PERF_EVENT_H__ */ libpfm-4.9.0/include/perfmon/pfmlib.h0000664000175000017500000007342013223402656017337 0ustar eranianeranian/* * Copyright (c) 2009 Google, Inc * Contributed by Stephane Eranian * * Based on: * Copyright (c) 2001-2007 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef __PFMLIB_H__ #define __PFMLIB_H__ #pragma GCC visibility push(default) #ifdef __cplusplus extern "C" { #endif #include #include #include #include #define LIBPFM_VERSION (4 << 16 | 0) #define PFM_MAJ_VERSION(v) ((v)>>16) #define PFM_MIN_VERSION(v) ((v) & 0xffff) /* * ABI revision level */ #define LIBPFM_ABI_VERSION 0 /* * priv level mask (for dfl_plm) */ #define PFM_PLM0 0x01 /* kernel */ #define PFM_PLM1 0x02 /* not yet used */ #define PFM_PLM2 0x04 /* not yet used */ #define PFM_PLM3 0x08 /* priv level 3, 2, 1 (x86) */ #define PFM_PLMH 0x10 /* hypervisor */ /* * Performance Event Source * * The source is what is providing events. * It can be: * - Hardware Performance Monitoring Unit (PMU) * - a particular kernel subsystem * * Identifiers are guaranteed constant across libpfm revisions * * New sources must be added at the end before PFM_PMU_MAX */ typedef enum { PFM_PMU_NONE= 0, /* no PMU */ PFM_PMU_GEN_IA64, /* Intel IA-64 architected PMU */ PFM_PMU_ITANIUM, /* Intel Itanium */ PFM_PMU_ITANIUM2, /* Intel Itanium 2 */ PFM_PMU_MONTECITO, /* Intel Dual-Core Itanium 2 9000 */ PFM_PMU_AMD64, /* AMD AMD64 (obsolete) */ PFM_PMU_I386_P6, /* Intel PIII (P6 core) */ PFM_PMU_INTEL_NETBURST, /* Intel Netburst (Pentium 4) */ PFM_PMU_INTEL_NETBURST_P, /* Intel Netburst Prescott (Pentium 4) */ PFM_PMU_COREDUO, /* Intel Core Duo/Core Solo */ PFM_PMU_I386_PM, /* Intel Pentium M */ PFM_PMU_INTEL_CORE, /* Intel Core */ PFM_PMU_INTEL_PPRO, /* Intel Pentium Pro */ PFM_PMU_INTEL_PII, /* Intel Pentium II */ PFM_PMU_INTEL_ATOM, /* Intel Atom */ PFM_PMU_INTEL_NHM, /* Intel Nehalem core PMU */ PFM_PMU_INTEL_NHM_EX, /* Intel Nehalem-EX core PMU */ PFM_PMU_INTEL_NHM_UNC, /* Intel Nehalem uncore PMU */ PFM_PMU_INTEL_X86_ARCH, /* Intel X86 architectural PMU */ PFM_PMU_MIPS_20KC, /* MIPS 20KC */ PFM_PMU_MIPS_24K, /* MIPS 24K */ PFM_PMU_MIPS_25KF, /* MIPS 25KF */ PFM_PMU_MIPS_34K, /* MIPS 34K */ PFM_PMU_MIPS_5KC, /* MIPS 5KC */ PFM_PMU_MIPS_74K, /* MIPS 74K */ PFM_PMU_MIPS_R10000, /* MIPS R10000 */ PFM_PMU_MIPS_R12000, /* MIPS R12000 */ PFM_PMU_MIPS_RM7000, /* MIPS RM7000 */ PFM_PMU_MIPS_RM9000, /* MIPS RM9000 */ PFM_PMU_MIPS_SB1, /* MIPS SB1/SB1A */ PFM_PMU_MIPS_VR5432, /* MIPS VR5432 */ PFM_PMU_MIPS_VR5500, /* MIPS VR5500 */ PFM_PMU_MIPS_ICE9A, /* SiCortex ICE9A */ PFM_PMU_MIPS_ICE9B, /* SiCortex ICE9B */ PFM_PMU_POWERPC, /* POWERPC */ PFM_PMU_CELL, /* IBM CELL */ PFM_PMU_SPARC_ULTRA12, /* UltraSPARC I, II, IIi, and IIe */ PFM_PMU_SPARC_ULTRA3, /* UltraSPARC III */ PFM_PMU_SPARC_ULTRA3I, /* UltraSPARC IIIi and IIIi+ */ PFM_PMU_SPARC_ULTRA3PLUS, /* UltraSPARC III+ and IV */ PFM_PMU_SPARC_ULTRA4PLUS, /* UltraSPARC IV+ */ PFM_PMU_SPARC_NIAGARA1, /* Niagara-1 */ PFM_PMU_SPARC_NIAGARA2, /* Niagara-2 */ PFM_PMU_PPC970, /* IBM PowerPC 970(FX,GX) */ PFM_PMU_PPC970MP, /* IBM PowerPC 970MP */ PFM_PMU_POWER3, /* IBM POWER3 */ PFM_PMU_POWER4, /* IBM POWER4 */ PFM_PMU_POWER5, /* IBM POWER5 */ PFM_PMU_POWER5p, /* IBM POWER5+ */ PFM_PMU_POWER6, /* IBM POWER6 */ PFM_PMU_POWER7, /* IBM POWER7 */ PFM_PMU_PERF_EVENT, /* perf_event PMU */ PFM_PMU_INTEL_WSM, /* Intel Westmere single-socket (Clarkdale) */ PFM_PMU_INTEL_WSM_DP, /* Intel Westmere dual-socket (Westmere-EP, Gulftwon) */ PFM_PMU_INTEL_WSM_UNC, /* Intel Westmere uncore PMU */ PFM_PMU_AMD64_K7, /* AMD AMD64 K7 */ PFM_PMU_AMD64_K8_REVB, /* AMD AMD64 K8 RevB */ PFM_PMU_AMD64_K8_REVC, /* AMD AMD64 K8 RevC */ PFM_PMU_AMD64_K8_REVD, /* AMD AMD64 K8 RevD */ PFM_PMU_AMD64_K8_REVE, /* AMD AMD64 K8 RevE */ PFM_PMU_AMD64_K8_REVF, /* AMD AMD64 K8 RevF */ PFM_PMU_AMD64_K8_REVG, /* AMD AMD64 K8 RevG */ PFM_PMU_AMD64_FAM10H_BARCELONA, /* AMD AMD64 Fam10h Barcelona RevB */ PFM_PMU_AMD64_FAM10H_SHANGHAI, /* AMD AMD64 Fam10h Shanghai RevC */ PFM_PMU_AMD64_FAM10H_ISTANBUL, /* AMD AMD64 Fam10h Istanbul RevD */ PFM_PMU_ARM_CORTEX_A8, /* ARM Cortex A8 */ PFM_PMU_ARM_CORTEX_A9, /* ARM Cortex A9 */ PFM_PMU_TORRENT, /* IBM Torrent hub chip */ PFM_PMU_INTEL_SNB, /* Intel Sandy Bridge (single socket) */ PFM_PMU_AMD64_FAM14H_BOBCAT, /* AMD AMD64 Fam14h Bobcat */ PFM_PMU_AMD64_FAM15H_INTERLAGOS,/* AMD AMD64 Fam15h Interlagos */ PFM_PMU_INTEL_SNB_EP, /* Intel SandyBridge EP */ PFM_PMU_AMD64_FAM12H_LLANO, /* AMD AMD64 Fam12h Llano */ PFM_PMU_AMD64_FAM11H_TURION, /* AMD AMD64 Fam11h Turion */ PFM_PMU_INTEL_IVB, /* Intel IvyBridge */ PFM_PMU_ARM_CORTEX_A15, /* ARM Cortex A15 */ PFM_PMU_INTEL_SNB_UNC_CB0, /* Intel SandyBridge C-box 0 uncore PMU */ PFM_PMU_INTEL_SNB_UNC_CB1, /* Intel SandyBridge C-box 1 uncore PMU */ PFM_PMU_INTEL_SNB_UNC_CB2, /* Intel SandyBridge C-box 2 uncore PMU */ PFM_PMU_INTEL_SNB_UNC_CB3, /* Intel SandyBridge C-box 3 uncore PMU */ PFM_PMU_INTEL_SNBEP_UNC_CB0, /* Intel SandyBridge-EP C-Box core 0 uncore */ PFM_PMU_INTEL_SNBEP_UNC_CB1, /* Intel SandyBridge-EP C-Box core 1 uncore */ PFM_PMU_INTEL_SNBEP_UNC_CB2, /* Intel SandyBridge-EP C-Box core 2 uncore */ PFM_PMU_INTEL_SNBEP_UNC_CB3, /* Intel SandyBridge-EP C-Box core 3 uncore */ PFM_PMU_INTEL_SNBEP_UNC_CB4, /* Intel SandyBridge-EP C-Box core 4 uncore */ PFM_PMU_INTEL_SNBEP_UNC_CB5, /* Intel SandyBridge-EP C-Box core 5 uncore */ PFM_PMU_INTEL_SNBEP_UNC_CB6, /* Intel SandyBridge-EP C-Box core 6 uncore */ PFM_PMU_INTEL_SNBEP_UNC_CB7, /* Intel SandyBridge-EP C-Box core 7 uncore */ PFM_PMU_INTEL_SNBEP_UNC_HA, /* Intel SandyBridge-EP HA uncore */ PFM_PMU_INTEL_SNBEP_UNC_IMC0, /* Intel SandyBridge-EP IMC socket 0 uncore */ PFM_PMU_INTEL_SNBEP_UNC_IMC1, /* Intel SandyBridge-EP IMC socket 1 uncore */ PFM_PMU_INTEL_SNBEP_UNC_IMC2, /* Intel SandyBridge-EP IMC socket 2 uncore */ PFM_PMU_INTEL_SNBEP_UNC_IMC3, /* Intel SandyBridge-EP IMC socket 3 uncore */ PFM_PMU_INTEL_SNBEP_UNC_PCU, /* Intel SandyBridge-EP PCU uncore */ PFM_PMU_INTEL_SNBEP_UNC_QPI0, /* Intel SandyBridge-EP QPI link 0 uncore */ PFM_PMU_INTEL_SNBEP_UNC_QPI1, /* Intel SandyBridge-EP QPI link 1 uncore */ PFM_PMU_INTEL_SNBEP_UNC_UBOX, /* Intel SandyBridge-EP U-Box uncore */ PFM_PMU_INTEL_SNBEP_UNC_R2PCIE, /* Intel SandyBridge-EP R2PCIe uncore */ PFM_PMU_INTEL_SNBEP_UNC_R3QPI0, /* Intel SandyBridge-EP R3QPI 0 uncore */ PFM_PMU_INTEL_SNBEP_UNC_R3QPI1, /* Intel SandyBridge-EP R3QPI 1 uncore */ PFM_PMU_INTEL_KNC, /* Intel Knights Corner (Xeon Phi) */ PFM_PMU_S390X_CPUM_CF, /* s390x: CPU-M counter facility */ PFM_PMU_ARM_1176, /* ARM 1176 */ PFM_PMU_INTEL_IVB_EP, /* Intel IvyBridge EP */ PFM_PMU_INTEL_HSW, /* Intel Haswell */ PFM_PMU_INTEL_IVB_UNC_CB0, /* Intel IvyBridge C-box 0 uncore PMU */ PFM_PMU_INTEL_IVB_UNC_CB1, /* Intel IvyBridge C-box 1 uncore PMU */ PFM_PMU_INTEL_IVB_UNC_CB2, /* Intel IvyBridge C-box 2 uncore PMU */ PFM_PMU_INTEL_IVB_UNC_CB3, /* Intel IvyBridge C-box 3 uncore PMU */ PFM_PMU_POWER8, /* IBM POWER8 */ PFM_PMU_INTEL_RAPL, /* Intel RAPL */ PFM_PMU_INTEL_SLM, /* Intel Silvermont */ PFM_PMU_AMD64_FAM15H_NB, /* AMD AMD64 Fam15h NorthBridge */ PFM_PMU_ARM_QCOM_KRAIT, /* Qualcomm Krait */ PFM_PMU_PERF_EVENT_RAW, /* perf_events RAW event syntax */ PFM_PMU_INTEL_IVBEP_UNC_CB0, /* Intel IvyBridge-EP C-Box core 0 uncore */ PFM_PMU_INTEL_IVBEP_UNC_CB1, /* Intel IvyBridge-EP C-Box core 1 uncore */ PFM_PMU_INTEL_IVBEP_UNC_CB2, /* Intel IvyBridge-EP C-Box core 2 uncore */ PFM_PMU_INTEL_IVBEP_UNC_CB3, /* Intel IvyBridge-EP C-Box core 3 uncore */ PFM_PMU_INTEL_IVBEP_UNC_CB4, /* Intel IvyBridge-EP C-Box core 4 uncore */ PFM_PMU_INTEL_IVBEP_UNC_CB5, /* Intel IvyBridge-EP C-Box core 5 uncore */ PFM_PMU_INTEL_IVBEP_UNC_CB6, /* Intel IvyBridge-EP C-Box core 6 uncore */ PFM_PMU_INTEL_IVBEP_UNC_CB7, /* Intel IvyBridge-EP C-Box core 7 uncore */ PFM_PMU_INTEL_IVBEP_UNC_CB8, /* Intel IvyBridge-EP C-Box core 8 uncore */ PFM_PMU_INTEL_IVBEP_UNC_CB9, /* Intel IvyBridge-EP C-Box core 9 uncore */ PFM_PMU_INTEL_IVBEP_UNC_CB10, /* Intel IvyBridge-EP C-Box core 10 uncore */ PFM_PMU_INTEL_IVBEP_UNC_CB11, /* Intel IvyBridge-EP C-Box core 11 uncore */ PFM_PMU_INTEL_IVBEP_UNC_CB12, /* Intel IvyBridge-EP C-Box core 12 uncore */ PFM_PMU_INTEL_IVBEP_UNC_CB13, /* Intel IvyBridge-EP C-Box core 13 uncore */ PFM_PMU_INTEL_IVBEP_UNC_CB14, /* Intel IvyBridge-EP C-Box core 14 uncore */ PFM_PMU_INTEL_IVBEP_UNC_HA0, /* Intel IvyBridge-EP HA 0 uncore */ PFM_PMU_INTEL_IVBEP_UNC_HA1, /* Intel IvyBridge-EP HA 1 uncore */ PFM_PMU_INTEL_IVBEP_UNC_IMC0, /* Intel IvyBridge-EP IMC socket 0 uncore */ PFM_PMU_INTEL_IVBEP_UNC_IMC1, /* Intel IvyBridge-EP IMC socket 1 uncore */ PFM_PMU_INTEL_IVBEP_UNC_IMC2, /* Intel IvyBridge-EP IMC socket 2 uncore */ PFM_PMU_INTEL_IVBEP_UNC_IMC3, /* Intel IvyBridge-EP IMC socket 3 uncore */ PFM_PMU_INTEL_IVBEP_UNC_IMC4, /* Intel IvyBridge-EP IMC socket 4 uncore */ PFM_PMU_INTEL_IVBEP_UNC_IMC5, /* Intel IvyBridge-EP IMC socket 5 uncore */ PFM_PMU_INTEL_IVBEP_UNC_IMC6, /* Intel IvyBridge-EP IMC socket 6 uncore */ PFM_PMU_INTEL_IVBEP_UNC_IMC7, /* Intel IvyBridge-EP IMC socket 7 uncore */ PFM_PMU_INTEL_IVBEP_UNC_PCU, /* Intel IvyBridge-EP PCU uncore */ PFM_PMU_INTEL_IVBEP_UNC_QPI0, /* Intel IvyBridge-EP QPI link 0 uncore */ PFM_PMU_INTEL_IVBEP_UNC_QPI1, /* Intel IvyBridge-EP QPI link 1 uncore */ PFM_PMU_INTEL_IVBEP_UNC_QPI2, /* Intel IvyBridge-EP QPI link 2 uncore */ PFM_PMU_INTEL_IVBEP_UNC_UBOX, /* Intel IvyBridge-EP U-Box uncore */ PFM_PMU_INTEL_IVBEP_UNC_R2PCIE, /* Intel IvyBridge-EP R2PCIe uncore */ PFM_PMU_INTEL_IVBEP_UNC_R3QPI0, /* Intel IvyBridge-EP R3QPI 0 uncore */ PFM_PMU_INTEL_IVBEP_UNC_R3QPI1, /* Intel IvyBridge-EP R3QPI 1 uncore */ PFM_PMU_INTEL_IVBEP_UNC_R3QPI2, /* Intel IvyBridge-EP R3QPI 2 uncore */ PFM_PMU_INTEL_IVBEP_UNC_IRP, /* Intel IvyBridge-EP IRP uncore */ PFM_PMU_S390X_CPUM_SF, /* s390x: CPU-M sampling facility */ PFM_PMU_ARM_CORTEX_A57, /* ARM Cortex A57 (ARMv8) */ PFM_PMU_ARM_CORTEX_A53, /* ARM Cortex A53 (ARMv8) */ PFM_PMU_ARM_CORTEX_A7, /* ARM Cortex A7 */ PFM_PMU_INTEL_HSW_EP, /* Intel Haswell EP */ PFM_PMU_INTEL_BDW, /* Intel Broadwell */ PFM_PMU_ARM_XGENE, /* Applied Micro X-Gene (ARMv8) */ PFM_PMU_INTEL_HSWEP_UNC_CB0, /* Intel Haswell-EP C-Box core 0 uncore */ PFM_PMU_INTEL_HSWEP_UNC_CB1, /* Intel Haswell-EP C-Box core 1 uncore */ PFM_PMU_INTEL_HSWEP_UNC_CB2, /* Intel Haswell-EP C-Box core 2 uncore */ PFM_PMU_INTEL_HSWEP_UNC_CB3, /* Intel Haswell-EP C-Box core 3 uncore */ PFM_PMU_INTEL_HSWEP_UNC_CB4, /* Intel Haswell-EP C-Box core 4 uncore */ PFM_PMU_INTEL_HSWEP_UNC_CB5, /* Intel Haswell-EP C-Box core 5 uncore */ PFM_PMU_INTEL_HSWEP_UNC_CB6, /* Intel Haswell-EP C-Box core 6 uncore */ PFM_PMU_INTEL_HSWEP_UNC_CB7, /* Intel Haswell-EP C-Box core 7 uncore */ PFM_PMU_INTEL_HSWEP_UNC_CB8, /* Intel Haswell-EP C-Box core 8 uncore */ PFM_PMU_INTEL_HSWEP_UNC_CB9, /* Intel Haswell-EP C-Box core 9 uncore */ PFM_PMU_INTEL_HSWEP_UNC_CB10, /* Intel Haswell-EP C-Box core 10 uncore */ PFM_PMU_INTEL_HSWEP_UNC_CB11, /* Intel Haswell-EP C-Box core 11 uncore */ PFM_PMU_INTEL_HSWEP_UNC_CB12, /* Intel Haswell-EP C-Box core 12 uncore */ PFM_PMU_INTEL_HSWEP_UNC_CB13, /* Intel Haswell-EP C-Box core 13 uncore */ PFM_PMU_INTEL_HSWEP_UNC_CB14, /* Intel Haswell-EP C-Box core 14 uncore */ PFM_PMU_INTEL_HSWEP_UNC_CB15, /* Intel Haswell-EP C-Box core 15 uncore */ PFM_PMU_INTEL_HSWEP_UNC_CB16, /* Intel Haswell-EP C-Box core 16 uncore */ PFM_PMU_INTEL_HSWEP_UNC_CB17, /* Intel Haswell-EP C-Box core 17 uncore */ PFM_PMU_INTEL_HSWEP_UNC_HA0, /* Intel Haswell-EP HA 0 uncore */ PFM_PMU_INTEL_HSWEP_UNC_HA1, /* Intel Haswell-EP HA 1 uncore */ PFM_PMU_INTEL_HSWEP_UNC_IMC0, /* Intel Haswell-EP IMC socket 0 uncore */ PFM_PMU_INTEL_HSWEP_UNC_IMC1, /* Intel Haswell-EP IMC socket 1 uncore */ PFM_PMU_INTEL_HSWEP_UNC_IMC2, /* Intel Haswell-EP IMC socket 2 uncore */ PFM_PMU_INTEL_HSWEP_UNC_IMC3, /* Intel Haswell-EP IMC socket 3 uncore */ PFM_PMU_INTEL_HSWEP_UNC_IMC4, /* Intel Haswell-EP IMC socket 4 uncore */ PFM_PMU_INTEL_HSWEP_UNC_IMC5, /* Intel Haswell-EP IMC socket 5 uncore */ PFM_PMU_INTEL_HSWEP_UNC_IMC6, /* Intel Haswell-EP IMC socket 6 uncore */ PFM_PMU_INTEL_HSWEP_UNC_IMC7, /* Intel Haswell-EP IMC socket 7 uncore */ PFM_PMU_INTEL_HSWEP_UNC_PCU, /* Intel Haswell-EP PCU uncore */ PFM_PMU_INTEL_HSWEP_UNC_QPI0, /* Intel Haswell-EP QPI link 0 uncore */ PFM_PMU_INTEL_HSWEP_UNC_QPI1, /* Intel Haswell-EP QPI link 1 uncore */ PFM_PMU_INTEL_HSWEP_UNC_UBOX, /* Intel Haswell-EP U-Box uncore */ PFM_PMU_INTEL_HSWEP_UNC_R2PCIE, /* Intel Haswell-EP R2PCIe uncore */ PFM_PMU_INTEL_HSWEP_UNC_R3QPI0, /* Intel Haswell-EP R3QPI 0 uncore */ PFM_PMU_INTEL_HSWEP_UNC_R3QPI1, /* Intel Haswell-EP R3QPI 1 uncore */ PFM_PMU_INTEL_HSWEP_UNC_R3QPI2, /* Intel Haswell-EP R3QPI 2 uncore */ PFM_PMU_INTEL_HSWEP_UNC_IRP, /* Intel Haswell-EP IRP uncore */ PFM_PMU_INTEL_HSWEP_UNC_SB0, /* Intel Haswell-EP S-Box 0 uncore */ PFM_PMU_INTEL_HSWEP_UNC_SB1, /* Intel Haswell-EP S-Box 1 uncore */ PFM_PMU_INTEL_HSWEP_UNC_SB2, /* Intel Haswell-EP S-Box 2 uncore */ PFM_PMU_INTEL_HSWEP_UNC_SB3, /* Intel Haswell-EP S-Box 3 uncore */ PFM_PMU_POWERPC_NEST_MCS_READ_BW, /* POWERPC Nest Memory Read bandwidth */ PFM_PMU_POWERPC_NEST_MCS_WRITE_BW, /* POWERPC Nest Memory Write bandwidth */ PFM_PMU_INTEL_SKL, /* Intel Skylake */ PFM_PMU_INTEL_BDW_EP, /* Intel Broadwell EP */ PFM_PMU_INTEL_GLM, /* Intel Goldmont */ PFM_PMU_INTEL_KNL, /* Intel Knights Landing */ PFM_PMU_INTEL_KNL_UNC_IMC0, /* Intel KnightLanding IMC channel 0 uncore */ PFM_PMU_INTEL_KNL_UNC_IMC1, /* Intel KnightLanding IMC channel 1 uncore */ PFM_PMU_INTEL_KNL_UNC_IMC2, /* Intel KnightLanding IMC channel 2 uncore */ PFM_PMU_INTEL_KNL_UNC_IMC3, /* Intel KnightLanding IMC channel 3 uncore */ PFM_PMU_INTEL_KNL_UNC_IMC4, /* Intel KnightLanding IMC channel 4 uncore */ PFM_PMU_INTEL_KNL_UNC_IMC5, /* Intel KnightLanding IMC channel 5 uncore */ PFM_PMU_INTEL_KNL_UNC_IMC_UCLK0,/* Intel KnightLanding IMC UCLK unit 0 uncore */ PFM_PMU_INTEL_KNL_UNC_IMC_UCLK1,/* Intel KnightLanding IMC UCLK unit 1 uncore */ PFM_PMU_INTEL_KNL_UNC_EDC_ECLK0,/* Intel KnightLanding EDC ECLK unit 0 uncore */ PFM_PMU_INTEL_KNL_UNC_EDC_ECLK1,/* Intel KnightLanding EDC ECLK unit 1 uncore */ PFM_PMU_INTEL_KNL_UNC_EDC_ECLK2,/* Intel KnightLanding EDC ECLK unit 2 uncore */ PFM_PMU_INTEL_KNL_UNC_EDC_ECLK3,/* Intel KnightLanding EDC ECLK unit 3 uncore */ PFM_PMU_INTEL_KNL_UNC_EDC_ECLK4,/* Intel KnightLanding EDC ECLK unit 4 uncore */ PFM_PMU_INTEL_KNL_UNC_EDC_ECLK5,/* Intel KnightLanding EDC ECLK unit 5 uncore */ PFM_PMU_INTEL_KNL_UNC_EDC_ECLK6,/* Intel KnightLanding EDC ECLK unit 6 uncore */ PFM_PMU_INTEL_KNL_UNC_EDC_ECLK7,/* Intel KnightLanding EDC ECLK unit 7 uncore */ PFM_PMU_INTEL_KNL_UNC_EDC_UCLK0,/* Intel KnightLanding EDC UCLK unit 0 uncore */ PFM_PMU_INTEL_KNL_UNC_EDC_UCLK1,/* Intel KnightLanding EDC UCLK unit 1 uncore */ PFM_PMU_INTEL_KNL_UNC_EDC_UCLK2,/* Intel KnightLanding EDC UCLK unit 2 uncore */ PFM_PMU_INTEL_KNL_UNC_EDC_UCLK3,/* Intel KnightLanding EDC UCLK unit 3 uncore */ PFM_PMU_INTEL_KNL_UNC_EDC_UCLK4,/* Intel KnightLanding EDC UCLK unit 4 uncore */ PFM_PMU_INTEL_KNL_UNC_EDC_UCLK5,/* Intel KnightLanding EDC UCLK unit 5 uncore */ PFM_PMU_INTEL_KNL_UNC_EDC_UCLK6,/* Intel KnightLanding EDC UCLK unit 6 uncore */ PFM_PMU_INTEL_KNL_UNC_EDC_UCLK7,/* Intel KnightLanding EDC UCLK unit 7 uncore */ PFM_PMU_INTEL_KNL_UNC_CHA0, /* Intel KnightLanding CHA unit 0 uncore */ PFM_PMU_INTEL_KNL_UNC_CHA1, /* Intel KnightLanding CHA unit 1 uncore */ PFM_PMU_INTEL_KNL_UNC_CHA2, /* Intel KnightLanding CHA unit 2 uncore */ PFM_PMU_INTEL_KNL_UNC_CHA3, /* Intel KnightLanding CHA unit 3 uncore */ PFM_PMU_INTEL_KNL_UNC_CHA4, /* Intel KnightLanding CHA unit 4 uncore */ PFM_PMU_INTEL_KNL_UNC_CHA5, /* Intel KnightLanding CHA unit 5 uncore */ PFM_PMU_INTEL_KNL_UNC_CHA6, /* Intel KnightLanding CHA unit 6 uncore */ PFM_PMU_INTEL_KNL_UNC_CHA7, /* Intel KnightLanding CHA unit 7 uncore */ PFM_PMU_INTEL_KNL_UNC_CHA8, /* Intel KnightLanding CHA unit 8 uncore */ PFM_PMU_INTEL_KNL_UNC_CHA9, /* Intel KnightLanding CHA unit 9 uncore */ PFM_PMU_INTEL_KNL_UNC_CHA10, /* Intel KnightLanding CHA unit 10 uncore */ PFM_PMU_INTEL_KNL_UNC_CHA11, /* Intel KnightLanding CHA unit 11 uncore */ PFM_PMU_INTEL_KNL_UNC_CHA12, /* Intel KnightLanding CHA unit 12 uncore */ PFM_PMU_INTEL_KNL_UNC_CHA13, /* Intel KnightLanding CHA unit 13 uncore */ PFM_PMU_INTEL_KNL_UNC_CHA14, /* Intel KnightLanding CHA unit 14 uncore */ PFM_PMU_INTEL_KNL_UNC_CHA15, /* Intel KnightLanding CHA unit 15 uncore */ PFM_PMU_INTEL_KNL_UNC_CHA16, /* Intel KnightLanding CHA unit 16 uncore */ PFM_PMU_INTEL_KNL_UNC_CHA17, /* Intel KnightLanding CHA unit 17 uncore */ PFM_PMU_INTEL_KNL_UNC_CHA18, /* Intel KnightLanding CHA unit 18 uncore */ PFM_PMU_INTEL_KNL_UNC_CHA19, /* Intel KnightLanding CHA unit 19 uncore */ PFM_PMU_INTEL_KNL_UNC_CHA20, /* Intel KnightLanding CHA unit 20 uncore */ PFM_PMU_INTEL_KNL_UNC_CHA21, /* Intel KnightLanding CHA unit 21 uncore */ PFM_PMU_INTEL_KNL_UNC_CHA22, /* Intel KnightLanding CHA unit 22 uncore */ PFM_PMU_INTEL_KNL_UNC_CHA23, /* Intel KnightLanding CHA unit 23 uncore */ PFM_PMU_INTEL_KNL_UNC_CHA24, /* Intel KnightLanding CHA unit 24 uncore */ PFM_PMU_INTEL_KNL_UNC_CHA25, /* Intel KnightLanding CHA unit 25 uncore */ PFM_PMU_INTEL_KNL_UNC_CHA26, /* Intel KnightLanding CHA unit 26 uncore */ PFM_PMU_INTEL_KNL_UNC_CHA27, /* Intel KnightLanding CHA unit 27 uncore */ PFM_PMU_INTEL_KNL_UNC_CHA28, /* Intel KnightLanding CHA unit 28 uncore */ PFM_PMU_INTEL_KNL_UNC_CHA29, /* Intel KnightLanding CHA unit 29 uncore */ PFM_PMU_INTEL_KNL_UNC_CHA30, /* Intel KnightLanding CHA unit 30 uncore */ PFM_PMU_INTEL_KNL_UNC_CHA31, /* Intel KnightLanding CHA unit 31 uncore */ PFM_PMU_INTEL_KNL_UNC_CHA32, /* Intel KnightLanding CHA unit 32 uncore */ PFM_PMU_INTEL_KNL_UNC_CHA33, /* Intel KnightLanding CHA unit 33 uncore */ PFM_PMU_INTEL_KNL_UNC_CHA34, /* Intel KnightLanding CHA unit 34 uncore */ PFM_PMU_INTEL_KNL_UNC_CHA35, /* Intel KnightLanding CHA unit 35 uncore */ PFM_PMU_INTEL_KNL_UNC_CHA36, /* Intel KnightLanding CHA unit 36 uncore */ PFM_PMU_INTEL_KNL_UNC_CHA37, /* Intel KnightLanding CHA unit 37 uncore */ PFM_PMU_INTEL_KNL_UNC_UBOX, /* Intel KnightLanding Ubox uncore */ PFM_PMU_INTEL_KNL_UNC_M2PCIE, /* Intel KnightLanding M2PCIe uncore */ PFM_PMU_POWER9, /* IBM POWER9 */ PFM_PMU_INTEL_BDX_UNC_CB0, /* Intel Broadwell-X C-Box core 0 uncore */ PFM_PMU_INTEL_BDX_UNC_CB1, /* Intel Broadwell-X C-Box core 1 uncore */ PFM_PMU_INTEL_BDX_UNC_CB2, /* Intel Broadwell-X C-Box core 2 uncore */ PFM_PMU_INTEL_BDX_UNC_CB3, /* Intel Broadwell-X C-Box core 3 uncore */ PFM_PMU_INTEL_BDX_UNC_CB4, /* Intel Broadwell-X C-Box core 4 uncore */ PFM_PMU_INTEL_BDX_UNC_CB5, /* Intel Broadwell-X C-Box core 5 uncore */ PFM_PMU_INTEL_BDX_UNC_CB6, /* Intel Broadwell-X C-Box core 6 uncore */ PFM_PMU_INTEL_BDX_UNC_CB7, /* Intel Broadwell-X C-Box core 7 uncore */ PFM_PMU_INTEL_BDX_UNC_CB8, /* Intel Broadwell-X C-Box core 8 uncore */ PFM_PMU_INTEL_BDX_UNC_CB9, /* Intel Broadwell-X C-Box core 9 uncore */ PFM_PMU_INTEL_BDX_UNC_CB10, /* Intel Broadwell-X C-Box core 10 uncore */ PFM_PMU_INTEL_BDX_UNC_CB11, /* Intel Broadwell-X C-Box core 11 uncore */ PFM_PMU_INTEL_BDX_UNC_CB12, /* Intel Broadwell-X C-Box core 12 uncore */ PFM_PMU_INTEL_BDX_UNC_CB13, /* Intel Broadwell-X C-Box core 13 uncore */ PFM_PMU_INTEL_BDX_UNC_CB14, /* Intel Broadwell-X C-Box core 14 uncore */ PFM_PMU_INTEL_BDX_UNC_CB15, /* Intel Broadwell-X C-Box core 15 uncore */ PFM_PMU_INTEL_BDX_UNC_CB16, /* Intel Broadwell-X C-Box core 16 uncore */ PFM_PMU_INTEL_BDX_UNC_CB17, /* Intel Broadwell-X C-Box core 17 uncore */ PFM_PMU_INTEL_BDX_UNC_CB18, /* Intel Broadwell-X C-Box core 18 uncore */ PFM_PMU_INTEL_BDX_UNC_CB19, /* Intel Broadwell-X C-Box core 19 uncore */ PFM_PMU_INTEL_BDX_UNC_CB20, /* Intel Broadwell-X C-Box core 20 uncore */ PFM_PMU_INTEL_BDX_UNC_CB21, /* Intel Broadwell-X C-Box core 21 uncore */ PFM_PMU_INTEL_BDX_UNC_CB22, /* Intel Broadwell-X C-Box core 22 uncore */ PFM_PMU_INTEL_BDX_UNC_CB23, /* Intel Broadwell-X C-Box core 23 uncore */ PFM_PMU_INTEL_BDX_UNC_HA0, /* Intel Broadwell-X HA 0 uncore */ PFM_PMU_INTEL_BDX_UNC_HA1, /* Intel Broadwell-X HA 1 uncore */ PFM_PMU_INTEL_BDX_UNC_IMC0, /* Intel Broadwell-X IMC socket 0 uncore */ PFM_PMU_INTEL_BDX_UNC_IMC1, /* Intel Broadwell-X IMC socket 1 uncore */ PFM_PMU_INTEL_BDX_UNC_IMC2, /* Intel Broadwell-X IMC socket 2 uncore */ PFM_PMU_INTEL_BDX_UNC_IMC3, /* Intel Broadwell-X IMC socket 3 uncore */ PFM_PMU_INTEL_BDX_UNC_IMC4, /* Intel Broadwell-X IMC socket 4 uncore */ PFM_PMU_INTEL_BDX_UNC_IMC5, /* Intel Broadwell-X IMC socket 5 uncore */ PFM_PMU_INTEL_BDX_UNC_IMC6, /* Intel Broadwell-X IMC socket 6 uncore */ PFM_PMU_INTEL_BDX_UNC_IMC7, /* Intel Broadwell-X IMC socket 7 uncore */ PFM_PMU_INTEL_BDX_UNC_PCU, /* Intel Broadwell-X PCU uncore */ PFM_PMU_INTEL_BDX_UNC_QPI0, /* Intel Broadwell-X QPI link 0 uncore */ PFM_PMU_INTEL_BDX_UNC_QPI1, /* Intel Broadwell-X QPI link 1 uncore */ PFM_PMU_INTEL_BDX_UNC_QPI2, /* Intel Broadwell-X QPI link 2 uncore */ PFM_PMU_INTEL_BDX_UNC_UBOX, /* Intel Broadwell-X U-Box uncore */ PFM_PMU_INTEL_BDX_UNC_R2PCIE, /* Intel Broadwell-X R2PCIe uncore */ PFM_PMU_INTEL_BDX_UNC_R3QPI0, /* Intel Broadwell-X R3QPI 0 uncore */ PFM_PMU_INTEL_BDX_UNC_R3QPI1, /* Intel Broadwell-X R3QPI 1 uncore */ PFM_PMU_INTEL_BDX_UNC_R3QPI2, /* Intel Broadwell-X R3QPI 2 uncore */ PFM_PMU_INTEL_BDX_UNC_IRP, /* Intel Broadwell-X IRP uncore */ PFM_PMU_INTEL_BDX_UNC_SB0, /* Intel Broadwell-X S-Box 0 uncore */ PFM_PMU_INTEL_BDX_UNC_SB1, /* Intel Broadwell-X S-Box 1 uncore */ PFM_PMU_INTEL_BDX_UNC_SB2, /* Intel Broadwell-X S-Box 2 uncore */ PFM_PMU_INTEL_BDX_UNC_SB3, /* Intel Broadwell-X S-Box 3 uncore */ PFM_PMU_AMD64_FAM17H, /* AMD AMD64 Fam17h Zen */ PFM_PMU_AMD64_FAM16H, /* AMD AMD64 Fam16h Jaguar */ PFM_PMU_INTEL_SKX, /* Intel Skylake-X */ /* MUST ADD NEW PMU MODELS HERE */ PFM_PMU_MAX /* end marker */ } pfm_pmu_t; typedef enum { PFM_PMU_TYPE_UNKNOWN=0, /* unknown PMU type */ PFM_PMU_TYPE_CORE, /* processor core PMU */ PFM_PMU_TYPE_UNCORE, /* processor socket-level PMU */ PFM_PMU_TYPE_OS_GENERIC,/* generic OS-provided PMU */ PFM_PMU_TYPE_MAX } pfm_pmu_type_t; typedef enum { PFM_ATTR_NONE=0, /* no attribute */ PFM_ATTR_UMASK, /* unit mask */ PFM_ATTR_MOD_BOOL, /* register modifier */ PFM_ATTR_MOD_INTEGER, /* register modifier */ PFM_ATTR_RAW_UMASK, /* raw umask (not user visible) */ PFM_ATTR_MAX /* end-marker */ } pfm_attr_t; /* * define additional event data types beyond historic uint64 * what else can fit in 64 bits? */ typedef enum { PFM_DTYPE_UNKNOWN=0, /* unkown */ PFM_DTYPE_UINT64, /* uint64 */ PFM_DTYPE_INT64, /* int64 */ PFM_DTYPE_DOUBLE, /* IEEE double precision float */ PFM_DTYPE_FIXED, /* 32.32 fixed point */ PFM_DTYPE_RATIO, /* 32/32 integer ratio */ PFM_DTYPE_CHAR8, /* 8 char unterminated string */ PFM_DTYPE_MAX /* end-marker */ } pfm_dtype_t; /* * event attribute control: which layer is controlling * the attribute could be PMU, OS APIs */ typedef enum { PFM_ATTR_CTRL_UNKNOWN = 0, /* unknown */ PFM_ATTR_CTRL_PMU, /* PMU hardware */ PFM_ATTR_CTRL_PERF_EVENT, /* perf_events kernel interface */ PFM_ATTR_CTRL_MAX } pfm_attr_ctrl_t; /* * OS layer * Used when querying event or attribute information */ typedef enum { PFM_OS_NONE = 0, /* only PMU */ PFM_OS_PERF_EVENT, /* perf_events PMU attribute subset + PMU */ PFM_OS_PERF_EVENT_EXT, /* perf_events all attributes + PMU */ PFM_OS_MAX, } pfm_os_t; /* SWIG doesn't deal well with anonymous nested structures */ #ifdef SWIG #define SWIG_NAME(x) x #else #define SWIG_NAME(x) #endif /* SWIG */ /* * special data type for libpfm error value used to help * with Python support and in particular for SWIG. By using * a specific type we can detect library calls and trap errors * in one SWIG statement as opposed to having to keep track of * each call individually. Programs can use 'int' safely for * the return value. */ typedef int pfm_err_t; /* error if !PFM_SUCCESS */ typedef int os_err_t; /* error if a syscall fails */ typedef struct { const char *name; /* event name */ const char *desc; /* event description */ size_t size; /* struct sizeof */ pfm_pmu_t pmu; /* PMU identification */ pfm_pmu_type_t type; /* PMU type */ int nevents; /* how many events for this PMU */ int first_event; /* opaque index of first event */ int max_encoding; /* max number of uint64_t to encode an event */ int num_cntrs; /* number of generic counters */ int num_fixed_cntrs;/* number of fixed counters */ struct { unsigned int is_present:1; /* present on host system */ unsigned int is_dfl:1; /* is architecture default PMU */ unsigned int reserved_bits:30; } SWIG_NAME(flags); } pfm_pmu_info_t; typedef struct { const char *name; /* event name */ const char *desc; /* event description */ const char *equiv; /* event is equivalent to */ size_t size; /* struct sizeof */ uint64_t code; /* event raw code (not encoding) */ pfm_pmu_t pmu; /* which PMU */ pfm_dtype_t dtype; /* data type of event value */ int idx; /* unique event identifier */ int nattrs; /* number of attributes */ int reserved; /* for future use */ struct { unsigned int is_precise:1; /* precise sampling (Intel X86=PEBS) */ unsigned int reserved_bits:31; } SWIG_NAME(flags); } pfm_event_info_t; typedef struct { const char *name; /* attribute symbolic name */ const char *desc; /* attribute description */ const char *equiv; /* attribute is equivalent to */ size_t size; /* struct sizeof */ uint64_t code; /* attribute code */ pfm_attr_t type; /* attribute type */ int idx; /* attribute opaque index */ pfm_attr_ctrl_t ctrl; /* what is providing attr */ struct { unsigned int is_dfl:1; /* is default umask */ unsigned int is_precise:1; /* Intel X86: supports PEBS */ unsigned int reserved_bits:30; } SWIG_NAME(flags); union { uint64_t dfl_val64; /* default 64-bit value */ const char *dfl_str; /* default string value */ int dfl_bool; /* default boolean value */ int dfl_int; /* default integer value */ } SWIG_NAME(defaults); } pfm_event_attr_info_t; /* * use with PFM_OS_NONE for pfm_get_os_event_encoding() */ typedef struct { uint64_t *codes; /* out/in: event codes array */ char **fstr; /* out/in: fully qualified event string */ size_t size; /* sizeof struct */ int count; /* out/in: # of elements in array */ int idx; /* out: unique event identifier */ } pfm_pmu_encode_arg_t; #if __WORDSIZE == 64 #define PFM_PMU_INFO_ABI0 56 #define PFM_EVENT_INFO_ABI0 64 #define PFM_ATTR_INFO_ABI0 64 #define PFM_RAW_ENCODE_ABI0 32 #else #define PFM_PMU_INFO_ABI0 44 #define PFM_EVENT_INFO_ABI0 48 #define PFM_ATTR_INFO_ABI0 48 #define PFM_RAW_ENCODE_ABI0 20 #endif /* * initialization, configuration, errors */ extern pfm_err_t pfm_initialize(void); extern void pfm_terminate(void); extern const char *pfm_strerror(int code); extern int pfm_get_version(void); /* * PMU API */ extern pfm_err_t pfm_get_pmu_info(pfm_pmu_t pmu, pfm_pmu_info_t *output); /* * event API */ extern int pfm_get_event_next(int idx); extern int pfm_find_event(const char *str); extern pfm_err_t pfm_get_event_info(int idx, pfm_os_t os, pfm_event_info_t *output); /* * event encoding API * * content of args depends on value of os (refer to man page) */ extern pfm_err_t pfm_get_os_event_encoding(const char *str, int dfl_plm, pfm_os_t os, void *args); /* * attribute API */ extern pfm_err_t pfm_get_event_attr_info(int eidx, int aidx, pfm_os_t os, pfm_event_attr_info_t *output); /* * library validation API */ extern pfm_err_t pfm_pmu_validate(pfm_pmu_t pmu_id, FILE *fp); /* * older encoding API */ extern pfm_err_t pfm_get_event_encoding(const char *str, int dfl_plm, char **fstr, int *idx, uint64_t **codes, int *count); /* * error codes */ #define PFM_SUCCESS 0 /* success */ #define PFM_ERR_NOTSUPP -1 /* function not supported */ #define PFM_ERR_INVAL -2 /* invalid parameters */ #define PFM_ERR_NOINIT -3 /* library was not initialized */ #define PFM_ERR_NOTFOUND -4 /* event not found */ #define PFM_ERR_FEATCOMB -5 /* invalid combination of features */ #define PFM_ERR_UMASK -6 /* invalid or missing unit mask */ #define PFM_ERR_NOMEM -7 /* out of memory */ #define PFM_ERR_ATTR -8 /* invalid event attribute */ #define PFM_ERR_ATTR_VAL -9 /* invalid event attribute value */ #define PFM_ERR_ATTR_SET -10 /* attribute value already set */ #define PFM_ERR_TOOMANY -11 /* too many parameters */ #define PFM_ERR_TOOSMALL -12 /* parameter is too small */ /* * event, attribute iterators * must be used because no guarante indexes are contiguous * * for pmu, simply iterate over pfm_pmu_t enum and use * pfm_get_pmu_info() and the is_present field */ #define pfm_for_each_event_attr(x, z) \ for((x)=0; (x) < (z)->nattrs; (x) = (x)+1) #define pfm_for_all_pmus(x) \ for((x)= 0 ; (x) < PFM_PMU_MAX; (x)++) #ifdef __cplusplus /* extern C */ } #endif #pragma GCC visibility pop #endif /* __PFMLIB_H__ */ libpfm-4.9.0/include/perfmon/pfmlib_perf_event.h0000664000175000017500000000455413223402656021556 0ustar eranianeranian/* * Copyright (c) 2009 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef __PFMLIB_PERF_EVENTS_H__ #define __PFMLIB_PERF_EVENTS_H__ #include #include #pragma GCC visibility push(default) #ifdef __cplusplus extern "C" { #endif /* * use with PFM_OS_PERF, PFM_OS_PERF_EXT for pfm_get_os_event_encoding() */ typedef struct { struct perf_event_attr *attr; /* in/out: perf_event struct pointer */ char **fstr; /* out/in: fully qualified event string */ size_t size; /* sizeof struct */ int idx; /* out: opaque event identifier */ int cpu; /* out: cpu to program, -1 = not set */ int flags; /* out: perf_event_open() flags */ int pad0; /* explicit 64-bit mode padding */ } pfm_perf_encode_arg_t; #if __WORDSIZE == 64 #define PFM_PERF_ENCODE_ABI0 40 /* includes 4-byte padding */ #else #define PFM_PERF_ENCODE_ABI0 28 #endif /* * old interface, maintained for backward compatibility with older versions o * the library. Should use pfm_get_os_event_encoding() now */ extern pfm_err_t pfm_get_perf_event_encoding(const char *str, int dfl_plm, struct perf_event_attr *output, char **fstr, int *idx); #ifdef __cplusplus /* extern C */ } #endif #pragma GCC visibility pop #endif /* __PFMLIB_PERF_EVENT_H__ */ libpfm-4.9.0/debian/0000775000175000017500000000000013223402656014040 5ustar eranianeranianlibpfm-4.9.0/debian/README0000664000175000017500000000026013223402656014716 0ustar eranianeranianThe Debian Package libpfm4 ---------------------------- libpfm4 packaging tested on Ubuntu Lucid (amd64). -- Arun Sharma Mon, 21 Jun 2010 15:17:22 -0700 libpfm-4.9.0/debian/libpfm4-dev.install0000664000175000017500000000003513223402656017537 0ustar eranianeranianusr/include/* usr/lib/lib*.a libpfm-4.9.0/debian/libpfm4-dev.manpages0000664000175000017500000000001613223402656017663 0ustar eranianeraniandocs/man3/*.3 libpfm-4.9.0/debian/compat0000664000175000017500000000000213223402656015236 0ustar eranianeranian7 libpfm-4.9.0/debian/libpfm4-dev.dirs0000664000175000017500000000002413223402656017030 0ustar eranianeranianusr/lib usr/include libpfm-4.9.0/debian/rules0000775000175000017500000000127013223402656015120 0ustar eranianeranian#!/usr/bin/make -f # -*- makefile -*- # Sample debian/rules that uses debhelper. # This file was originally written by Joey Hess and Craig Small. # As a special exception, when this file is copied by dh-make into a # dh-make output file, you may use that output file without restriction. # This special exception was added by Craig Small in version 0.37 of dh-make. # Uncomment this to turn on verbose mode. #export DH_VERBOSE=1 include /usr/share/dpatch/dpatch.make build: patch-stamp clean: unpatch override_dh_auto_install: build dh_auto_test dh_testroot dh_prep dh_installdirs make install DESTDIR=$(CURDIR)/debian/tmp PREFIX=/usr CONFIG_PFMLIB_NOPYTHON=n LDCONFIG=true %: dh $@ libpfm-4.9.0/debian/changelog0000664000175000017500000000636213223402656015721 0ustar eranianeranianlibpfm4 (9.0) unstable; urgency=low * add support for Broadwell EP uncore PMUa * add support for Intel Skylake X * add support for AMD Fam17h * add support for IBM Power9 * add support for AMD Fam16h * various fixes and event table updates -- Stephane Eranian Thu, 4 Jan 2018 13:37:01 +0200 libpfm4 (8.0) unstable; urgency=low * add Intel Knights Landing support * add Intel Goldmont support * update Intel event tables * allow . as delimiter for event string * add SQ_MISC:SPLIT_LOCK * enable Broadwell EP * various fixes -- Stephane Eranian Sat, 5 Nov 2016 14:38:01 +0200 libpfm4 (7.0) unstable; urgency=low * add Intel Skylake support * add Intel Haswell-EP uncore PMU support * add Broadwell DE support * updated most Intel x86 event tables to match official tables * refreshed perf_event.h header to 4.2 * more bug fixes and minor updates -- Stephane Eranian Thu, 11 Feb 2016 16:56:01 +0200 libpfm4 (6.0) unstable; urgency=low * add Intel Broadwell (desktop) support * add Intel Haswell-EP support (core) * add Applied Micro X-Gene processor support * simplified X86 model detection for Intel processors * Intel SNB, IVB, HSW event table updates * IBM Power8 event table updates * add ARM Cortex A53 support * more bug fixes and minor updates -- Stephane Eranian Tue, 30 Dec 2014 16:56:01 +0200 libpfm4 (5.0) unstable; urgency=low * Intel IVB-EP uncore PMU support * Intel Silvermont support * Perf raw event syntax support * Intel RAPL event support * AMD Fam15h northbridge support * Qualcomm Krait support * IBM Power 8 support * IBM s390 updates * AMD Fam15h fixes * various IVB, SNB, HSW event table updates * more bug fixes -- Stephane Eranian Fri, 21 Feb 2014 18:45:01 +0200 libpfm4 (4.0) unstable; urgency=low * Intel IVB-EP support * Intel IVB updates support * Intel SNB updates support * Intel SNB-EP uncore support * ldlat support (PEBS-LL) * New Intel Atom support * bug fixes -- Stephane Eranian Fri, 08 JUn 2013 18:45:01 +0200 libpfm4 (3.0) unstable; urgency=low * ARM Cortex A15 support * updated Intel Sandy Bridge core PMU events * Intel Sandy Bridge desktop (model 42) uncore PMU support * Intel Ivy Bridge support * full perf_events generic event support * updated perf_examples * enabled Intel Nehalem/Westmere uncore PMU support * AMD LLano processor supoprt (Fam 12h) * AMD Turion rocessor supoprt (Fam 11h) * Intel Atom Cedarview processor support * Win32 compilation support * perf_events excl attribute * perf_events generic hw event aliases support * many bug fixes -- Stephane Eranian Mon, 27 Aug 2012 17:45:22 +0200 libpfm4 (2.0) unstable; urgency=low * updated event tables for Intel X86 processors * new AMD Fam15h support * new MIPS 74k support * updated ARM Cortex A8/A9 support * 30% size reduction for Intel/AMD X86 event tables * bug fixes and other improvements -- Stephane Eranian Fri, 7 Oct 2011 15:55:22 +0200 libpfm4 (1.0) unstable; urgency=low * Initial Release. -- Arun Sharma Mon, 21 Jun 2010 15:17:22 -0700 libpfm-4.9.0/debian/python-libpfm4.install0000664000175000017500000000012613223402656020303 0ustar eranianeranianusr/lib/python*/site-packages/perfmon/*.py usr/lib/python*/site-packages/perfmon/*.so libpfm-4.9.0/debian/docs0000664000175000017500000000000713223402656014710 0ustar eranianeranianREADME libpfm-4.9.0/debian/copyright0000664000175000017500000000270313223402656015775 0ustar eranianeranianThis work was packaged for Debian by: Arun Sharma on Mon, 21 Jun 2010 15:17:22 -0700 It was downloaded from: git://perfmon2.git.sourceforge.net/gitroot/perfmon2/libpfm4 Upstream Author(s): Stephane Eranian Packaging by: Copyright (C) 2010 Arun Sharma Library and packaging released under the following license: Copyright (c) 2002-2006 Hewlett-Packard Development Company, L.P. Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. libpfm-4.9.0/debian/control0000664000175000017500000000335013223402656015444 0ustar eranianeranianSource: libpfm4 Priority: extra Maintainer: Stephane Eranian Build-Depends: debhelper (>= 7), dpatch, python (>= 2.4), python-support, python-dev (>= 2.4), swig Standards-Version: 3.8.4 Section: libs Homepage: http://perfmon2.sourceforge.net/ Package: libpfm4-dev Section: libdevel Architecture: any Depends: ${shlibs:Depends}, ${misc:Depends} Description: A library to program the performance monitoring events Libpfm4 helps convert from an event name, expressed as a string, to the event encoding. The encoding can then be used with specific OS interfaces. Libpfm4 also provides OS-specific interfaces to directly setup OS-specific data structures to be passed to the kernel. The current libpfm4, for instance, provides support for the perf_events interface which was introduced in Linux v2.6.31. Package: libpfm4 Section: libs Architecture: any Depends: ${shlibs:Depends}, ${misc:Depends} Description: A library to program the performance monitoring events Libpfm4 helps convert from an event name, expressed as a string, to the event encoding. The encoding can then be used with specific OS interfaces. Libpfm4 also provides OS-specific interfaces to directly setup OS-specific data structures to be passed to the kernel. The current libpfm4, for instance, provides support for the perf_events interface which was introduced in Linux v2.6.31. Package: python-libpfm4 Depends: libpfm4, python, ${shlibs:Depends}, ${misc:Depends} Architecture: any Section: python Description: Python bindings for libpfm4 This package allows you to write simple python scripts that monitor various hardware performance monitoring events. It may be more efficient to use this approach instead of parsing the output of other tools. libpfm-4.9.0/debian/README.source0000664000175000017500000000013113223402656016212 0ustar eranianeranianSources were slightly modified to compile with -Werror -Arun Sharma (aruns@google.com) libpfm-4.9.0/debian/pyversions0000664000175000017500000000000513223402656016177 0ustar eranianeranian2.4- libpfm-4.9.0/debian/source/0000775000175000017500000000000013223402656015340 5ustar eranianeranianlibpfm-4.9.0/debian/source/format0000664000175000017500000000001413223402656016546 0ustar eranianeranian3.0 (quilt) libpfm-4.9.0/debian/libpfm4.install0000664000175000017500000000002213223402656016757 0ustar eranianeranianusr/lib/lib*.so.* libpfm-4.9.0/libpfm.spec0000664000175000017500000000665513223402656014757 0ustar eranianeranian%{!?with_python: %global with_python 1} %define python_sitearch %(python -c "from distutils.sysconfig import get_python_lib; print get_python_lib(1)") %define python_prefix %(python -c "import sys; print sys.prefix") Name: libpfm Version: 4.6.0 Release: 1%{?dist} Summary: Library to encode performance events for use by perf tool Group: System Environment/Libraries License: MIT URL: http://perfmon2.sourceforge.net/ Source0: http://sourceforge.net/projects/perfmon2/files/libpfm4/%{name}-%{version}.tar.gz %if %{with_python} BuildRequires: python-devel BuildRequires: python-setuptools BuildRequires: swig %endif BuildRoot: %{_tmppath}/%{name}-%{version}-%{release}-root-%(%{__id_u} -n) %description libpfm4 is a library to help encode events for use with operating system kernels performance monitoring interfaces. The current version provides support for the perf_events interface available in upstream Linux kernels since v2.6.31. %package devel Summary: Development library to encode performance events for perf_events based tools Group: Development/Libraries Requires: %{name} = %{version}-%{release} %description devel Development library and header files to create performance monitoring applications for the perf_events interface. %if %{with_python} %package python Summary: Python bindings for libpfm and perf_event_open system call Group: Development/Languages Requires: %{name} = %{version}-%{release} %description python Python bindings for libpfm4 and perf_event_open system call. %endif %prep %setup -q %build %if %{with_python} %global python_config CONFIG_PFMLIB_NOPYTHON=n %else %global python_config CONFIG_PFMLIB_NOPYTHON=y %endif make %{python_config} %{?_smp_mflags} %install rm -rf $RPM_BUILD_ROOT %if %{with_python} %global python_config CONFIG_PFMLIB_NOPYTHON=n %else %global python_config CONFIG_PFMLIB_NOPYTHON=y %endif make \ PREFIX=$RPM_BUILD_ROOT%{_prefix} \ LIBDIR=$RPM_BUILD_ROOT%{_libdir} \ PYTHON_PREFIX=$RPM_BUILD_ROOT/%{python_prefix} \ %{python_config} \ LDCONFIG=/bin/true \ install %clean rm -fr $RPM_BUILD_ROOT %post -p /sbin/ldconfig %postun -p /sbin/ldconfig %files %defattr(644,root,root,755) %doc README %attr(755,root,root) %{_libdir}/lib*.so* %files devel %defattr(644,root,root,755) %{_includedir}/* %{_mandir}/man3/* %{_libdir}/lib*.a %if %{with_python} %files python %defattr(644,root,root,755) %attr(755,root,root) %{python_sitearch}/* %endif %changelog * Tue Feb 9 2016 William Cohen 4.6.0-1 - Update spec file. * Wed Nov 13 2013 Lukas Berk 4.4.0-1 - Intel IVB-EP support - Intel IVB updates support - Intel SNB updates support - Intel SNB-EP uncore support - ldlat support (PEBS-LL) - New Intel Atom support - bug fixes * Tue Aug 28 2012 Stephane Eranian 4.3.0-1 - ARM Cortex A15 support - updated Intel Sandy Bridge core PMU events - Intel Sandy Bridge desktop (model 42) uncore PMU support - Intel Ivy Bridge support - full perf_events generic event support - updated perf_examples - enabled Intel Nehalem/Westmere uncore PMU support - AMD LLano processor supoprt (Fam 12h) - AMD Turion rocessor supoprt (Fam 11h) - Intel Atom Cedarview processor support - Win32 compilation support - perf_events excl attribute - perf_events generic hw event aliases support - many bug fixes * Wed Mar 14 2012 William Cohen 4.2.0-2 - Some spec file fixup. * Wed Jan 12 2011 Arun Sharma 4.2.0-0 Initial revision libpfm-4.9.0/docs/0000775000175000017500000000000013223402656013546 5ustar eranianeranianlibpfm-4.9.0/docs/Makefile0000664000175000017500000001036313223402656015211 0ustar eranianeranian# # Copyright (c) 2002-2006 Hewlett-Packard Development Company, L.P. # Contributed by Stephane Eranian # # Permission is hereby granted, free of charge, to any person obtaining a copy # of this software and associated documentation files (the "Software"), to deal # in the Software without restriction, including without limitation the rights # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies # of the Software, and to permit persons to whom the Software is furnished to do so, # subject to the following conditions: # # The above copyright notice and this permission notice shall be included in all # copies or substantial portions of the Software. # # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, # INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A # PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT # HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF # CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE # OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # TOPDIR := $(shell if [ "$$PWD" != "" ]; then echo $$PWD; else pwd; fi)/.. include $(TOPDIR)/config.mk include $(TOPDIR)/rules.mk .PHONY: all clean distclean depend ARCH_MAN= SYS_MAN= ifeq ($(CONFIG_PFMLIB_ARCH_X86),y) ARCH_MAN=libpfm_intel_core.3 \ libpfm_intel_x86_arch.3\ libpfm_amd64.3 \ libpfm_amd64_k7.3 \ libpfm_amd64_k8.3 \ libpfm_amd64_fam10h.3 \ libpfm_amd64_fam15h.3 \ libpfm_amd64_fam16h.3 \ libpfm_amd64_fam17h.3 \ libpfm_intel_atom.3 \ libpfm_intel_nhm.3 \ libpfm_intel_nhm_unc.3 \ libpfm_intel_wsm.3 \ libpfm_intel_wsm_unc.3 \ libpfm_intel_snb.3 \ libpfm_intel_snb_unc.3 \ libpfm_intel_ivb.3 \ libpfm_intel_ivb_unc.3 \ libpfm_intel_hsw.3 \ libpfm_intel_bdw.3 \ libpfm_intel_rapl.3 \ libpfm_intel_slm.3 \ libpfm_intel_skl.3 \ libpfm_intel_glm.3 \ libpfm_intel_knl.3 \ libpfm_intel_snbep_unc_cbo.3 \ libpfm_intel_snbep_unc_ha.3 \ libpfm_intel_snbep_unc_imc.3 \ libpfm_intel_snbep_unc_pcu.3 \ libpfm_intel_snbep_unc_qpi.3 \ libpfm_intel_snbep_unc_ubo.3 \ libpfm_intel_snbep_unc_r2pcie.3 \ libpfm_intel_snbep_unc_r3qpi.3 \ libpfm_intel_ivbep_unc_cbo.3 \ libpfm_intel_ivbep_unc_ha.3 \ libpfm_intel_ivbep_unc_imc.3 \ libpfm_intel_ivbep_unc_pcu.3 \ libpfm_intel_ivbep_unc_qpi.3 \ libpfm_intel_ivbep_unc_ubo.3 \ libpfm_intel_ivbep_unc_r2pcie.3 \ libpfm_intel_ivbep_unc_r3qpi.3 \ libpfm_intel_ivbep_unc_irp.3 \ libpfm_intel_knc.3 \ libpfm_intel_hswep_unc_cbo.3 \ libpfm_intel_hswep_unc_ha.3 \ libpfm_intel_hswep_unc_imc.3 \ libpfm_intel_hswep_unc_irp.3 \ libpfm_intel_hswep_unc_pcu.3 \ libpfm_intel_hswep_unc_qpi.3 \ libpfm_intel_hswep_unc_r2pcie.3 \ libpfm_intel_hswep_unc_r3qpi.3 \ libpfm_intel_hswep_unc_sbo.3 \ libpfm_intel_hswep_unc_ubo.3 \ libpfm_intel_bdx_unc_cbo.3 \ libpfm_intel_bdx_unc_ha.3 \ libpfm_intel_bdx_unc_imc.3 \ libpfm_intel_bdx_unc_irp.3 \ libpfm_intel_bdx_unc_pcu.3 \ libpfm_intel_bdx_unc_qpi.3 \ libpfm_intel_bdx_unc_r2pcie.3 \ libpfm_intel_bdx_unc_r3qpi.3 \ libpfm_intel_bdx_unc_sbo.3 \ libpfm_intel_bdx_unc_ubo.3 ifeq ($(CONFIG_PFMLIB_ARCH_I386),y) ARCH_MAN += libpfm_intel_p6.3 libpfm_intel_coreduo.3 endif endif ifeq ($(CONFIG_PFMLIB_ARCH_ARM),y) ARCH_MAN += libpfm_arm_xgene.3 \ libpfm_arm_ac7.3 \ libpfm_arm_ac57.3 \ libpfm_arm_ac53.3 \ libpfm_arm_ac15.3 \ libpfm_arm_ac8.3 \ libpfm_arm_ac9.3 \ libpfm_arm_qcom_krait.3 endif ifeq ($(CONFIG_PFMLIB_ARCH_ARM64),y) ARCH_MAN += libpfm_arm_xgene.3 \ libpfm_arm_ac57.3 \ libpfm_arm_ac53.3 endif ifeq ($(CONFIG_PFMLIB_ARCH_MIPS),y) ARCH_MAN += libpfm_mips_74k.3 endif GEN_MAN= libpfm.3 \ pfm_find_event.3 \ pfm_get_event_attr_info.3 \ pfm_get_event_info.3 \ pfm_get_event_encoding.3 \ pfm_get_event_next.3 \ pfm_get_pmu_info.3 \ pfm_get_os_event_encoding.3 \ pfm_get_version.3 \ pfm_initialize.3 \ pfm_terminate.3 \ pfm_strerror.3 ifeq ($(SYS),Linux) SYS_MAN=pfm_get_perf_event_encoding.3 libpfm_perf_event_raw.3 endif MAN=$(GEN_MAN) $(ARCH_MAN) $(SYS_MAN) install: -mkdir -p $(DESTDIR)$(MANDIR)/man3 ( cd man3; $(INSTALL) -m 644 $(MAN) $(DESTDIR)$(MANDIR)/man3 ) libpfm-4.9.0/docs/man3/0000775000175000017500000000000013223402656014404 5ustar eranianeranianlibpfm-4.9.0/docs/man3/libpfm_intel_bdw.30000664000175000017500000000771313223402656020000 0ustar eranianeranian.TH LIBPFM 3 "October, 2014" "" "Linux Programmer's Manual" .SH NAME libpfm_intel_bdw - support for Intel Broadwell core PMU .SH SYNOPSIS .nf .B #include .sp .B PMU name: bdw .B PMU desc: Intel Broadwell .sp .SH DESCRIPTION The library supports the Intel Broadwell core PMU. It should be noted that this PMU model only covers each core's PMU and not the socket level PMU. On Broadwell, the number of generic counters depends on the Hyperthreading (HT) mode. When HT is on, then only 4 generic counters are available. When HT is off, then 8 generic counters are available. The \fBpfm_get_pmu_info()\fR function returns the maximum number of generic counters in \fBnum_cntrs\fr. .SH MODIFIERS The following modifiers are supported on Intel Broadwell processors: .TP .B u Measure at user level which includes privilege levels 1, 2, 3. This corresponds to \fBPFM_PLM3\fR. This is a boolean modifier. .TP .B k Measure at kernel level which includes privilege level 0. This corresponds to \fBPFM_PLM0\fR. This is a boolean modifier. .TP .B i Invert the meaning of the event. The counter will now count cycles in which the event is \fBnot\fR occurring. This is a boolean modifier .TP .B e Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a counter mask modifier (m) with a value greater or equal to one. This is a boolean modifier. .TP .B c Set the counter mask value. The mask acts as a threshold. The counter will count the number of cycles in which the number of occurrences of the event is greater or equal to the threshold. This is an integer modifier with values in the range [0:255]. .TP .B t Measure on both threads at the same time assuming hyper-threading is enabled. This is a boolean modifier. .TP .B ldlat Pass a latency threshold to the MEM_TRANS_RETIRED:LOAD_LATENCY event. This is an integer attribute that must be in the range [3:65535]. It is required for this event. Note that the event must be used with precise sampling (PEBS). .TP .B intx Monitor the event only when executing inside a transactional memory region (in tx). Event does not count otherwise. This is a boolean modifiers. Default value is 0. .TP .B intxcp Do not count occurrences of the event when they are inside an aborted transactional memory region. This is a boolean modifier. Default value is 0. .SH OFFCORE_RESPONSE events Intel Broadwell provides two offcore_response events. They are called OFFCORE_RESPONSE_0 and OFFCORE_RESPONSE_1. Those events need special treatment in the performance monitoring infrastructure because each event uses an extra register to store some settings. Thus, in case multiple offcore_response events are monitored simultaneously, the kernel needs to manage the sharing of that extra register. The offcore_response events are exposed as a normal events by the library. The extra settings are exposed as regular umasks. The library takes care of encoding the events according to the underlying kernel interface. On Intel Broadwell, the umasks are divided into three categories: request, supplier and snoop. The user must provide at least one umask for each category. The categories are shown in the umask descriptions. There is also the special response umask called \fBANY_RESPONSE\fR. When this umask is used then it overrides any supplier and snoop umasks. In other words, users can specify either \fBANY_RESPONSE\fR \fBOR\fR any combinations of supplier + snoops. In case no supplier or snoop is specified, the library defaults to using \fBANY_RESPONSE\fR. For instance, the following are valid event selections: .TP .B OFFCORE_RESPONSE_0:DMND_DATA_RD:ANY_RESPONSE .TP .B OFFCORE_RESPONSE_0:ANY_REQUEST .TP .B OFFCORE_RESPONSE_0:ANY_RFO:LLC_HITM:SNOOP_ANY .P But the following are illegal: .TP .B OFFCORE_RESPONSE_0:ANY_RFO:LLC_HITM:ANY_RESPONSE .TP .B OFFCORE_RESPONSE_0:ANY_RFO:LLC_HITM:SNOOP_ANY:ANY_RESPONSE .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/libpfm_amd64_fam15h.30000664000175000017500000000353413223402656020102 0ustar eranianeranian.TH LIBPFM 3 "Nov, 2013" "" "Linux Programmer's Manual" .SH NAME libpfm_amd64_fam15h - support for AMD64 Family 15h processors .SH SYNOPSIS .nf .B #include .sp .B PMU name: amd64_fam15h_interlagos .B PMU desc: AMD64 Fam15h Interlagos .B PMU name: amd64_fam15h_nb .B PMU desc: AMD64 Fam15h Northbridge .sp .SH DESCRIPTION The library supports AMD Family 15h processors core PMU in both 32 and 64-bit modes. The uncore (NorthBridge) PMU is also supported as a separate PMU model. .SH MODIFIERS The following modifiers are supported on AMD64 Family 15h core PMU: .TP .B u Measure at user level which includes privilege levels 1, 2, 3. This corresponds to \fBPFM_PLM3\fR. This is a boolean modifier. .TP .B k Measure at kernel level which includes privilege level 0. This corresponds to \fBPFM_PLM0\fR. This is a boolean modifier. .TP .B h Measure at while executing in host mode (when using virtualization). This corresponds to \fBPFM_PLMH\fR. This modifier is available starting with Fam10h. This is a boolean modifier. .TP .B g Measure at while executing in guest mode (when using virtualization). This modifier is available starting with Fam10h. This is a boolean modifier. .TP .B i Invert the meaning of the event. The counter will now count cycles in which the event is \fBnot\fR occurring. This is a boolean modifier .TP .B e Enable edge detection, i.e., count only when there is a state transition. This is a boolean modifier. .TP .B c Set the counter mask value. The mask acts as a threshold. The counter will count the number of cycles in which the number of occurrences of the event is greater or equal to the threshold. This is an integer modifier with values in the range [0:255]. .TP The uncore (NorthBridge) PMU \fBdoes not support\fR any modifiers. .SH AUTHORS .nf Stephane Eranian Robert Richter .if .PP libpfm-4.9.0/docs/man3/pfm_initialize.30000664000175000017500000000171613223402656017500 0ustar eranianeranian.TH LIBPFM 3 "September, 2009" "" "Linux Programmer's Manual" .SH NAME pfm_initialize \- initialize library .SH SYNOPSIS .nf .B #include .sp .BI "int pfm_initialize(void);" .sp .SH DESCRIPTION This is the first function that a program \fBmust\fR call otherwise the library will not operate. This function probes the underlying hardware looking for valid PMU event tables to activate. Multiple distinct PMU tables may be activated at the same time. The function must be called only once. If the function is called more than once, it does not execute the initialization multiple times, it simply returns the same value as for the first call. .SH RETURN The function returns whether or not it was successful, i.e., at least one PMU was activated. A return value of \fBPFMLIB_SUCCESS\fR indicates success, otherwise the value is an error code. .SH ERRORS .TP .B PFMLIB_ERR_NOTSUPP No PMU was activated. .SH AUTHOR Stephane Eranian .PP libpfm-4.9.0/docs/man3/pfm_get_os_event_encoding.30000664000175000017500000001660013223402656021664 0ustar eranianeranian.TH LIBPFM 3 "January, 2011" "" "Linux Programmer's Manual" .SH NAME pfm_get_os_event_encoding \- get event encoding for a specific operating system .SH SYNOPSIS .nf .B #include .sp .BI "int pfm_get_os_event_encoding(const char *" str ", int " dfl_plm ", pfm_os_t " os ", void *" arg ");" .sp .SH DESCRIPTION This is the key function to retrieve the encoding of an event for a specific operating system interface. The event string passed in \fBstr\fR is parsed and encoded for the operating system specified by \fBos\fR. Only one event per call can be encoded. As such, \fBstr\fR can contain only one symbolic event name. The event is encoded to monitor at the privilege levels specified by the \fBdfl_plm\fR mask, if supported, otherwise this parameter is ignored. The operating system specific input and output arguments are passed in \fBarg\fR. The event string, \fBstr\fR, may contains sub-event masks (umask) and any other supported modifiers. Only one event is parsed from the string. For convenience, it is possible to pass a comma-separated list of events in \fBstr\fR but only the first event is encoded. The following values are supported for \fBos\fR: .TP .B PFM_OS_NONE This value causes the event to be encoded purely as specified by the PMU hardware. The \fBarg\fR argument must be a pointer to a \fBpfm_raw_pmu_encode_arg_t\fR structure which is defined as follows: .nf typedef struct { uint64_t *codes; char **fstr; size_t size; int count; int idx; } pfm_pmu_encode_arg_t; .fi The fields are defined as follows: .RS .TP .B codes A pointer to an array of 64-bit values. On input, if \fBcodes\fR is NULL, then the library allocates whatever is necessary to store the encoding of the event. If \fBcodes\fR is not NULL on input, then \fBcount\fR must reflect its actual number of elements. If \fBcount\fR is big enough, the library stores the encoding at the address provided. Otherwise, an error is returned. .TP .B count On input, the field contains the maximum number of elements in the array \fBcodes\fR. Upon return, it contains the number of actual entries in \fBcodes\fR. If \fBcodes\fR is NULL, then count must be zero. .TP .B fstr If the caller is interested in retrieving the fully qualified event string where all used unit masks and all modifiers are spelled out, this field must be set to a non-null address of a pointer to a string (char **). Upon return, if \fBfstr\fR was not NULL, then the string pointer passed on entry points to the event string. The string is dynamically allocated and \fBmust\fR eventually be freed by the caller. If \fBfstr\fR was NULL on entry, then nothing is returned in this field. The typical calling sequence looks as follows: .nf char *fstr = NULL pfm_pmu_encode_arg_t arg; arg.fstr = &fstr; ret = pfm_get_os_event_encoding("event", PFM_PLM0|PFM_PLM3, PFM_OS_NONE, &e); if (ret == PFM_SUCCESS) { printf("fstr=%s\n", fstr); free(fstr); } .fi .TP .B size This field contains the size of the struct passed. This field is used to provide for extensibility of the struct without compromising backward compatibility. The value should be set to \fBsizeof(pfm_pmu_encode_arg_t)\fR. If instead, a value of \fB0\fR is specified, the library assumes the struct passed is identical to the first ABI version which size is \fBPFM_RAW_ENCODE_ABI0\fR. Thus, if fields were added after the first ABI, they will not be set by the library. The library does check that bytes beyond what is implemented are zeroes. .TP .B idx Upon return, this field contains the opaque unique identifier for the event described in \fBstr\fR. This index can be used to retrieve information about the event using \fBpfm_get_event_info()\fR, for instance. .RE .TP .B PFM_OS_PERF_EVENT, PFM_OS_PERF_EVENT_EXT This value causes the event to be encoded for the perf_event Linux kernel interface (available since 2.6.31). The \fBarg\fR must be a pointer to a \fBpfm_perf_encode_arg_t\fR structure. The PFM_OS_PERF_EVENT layer provides the modifiers exported by the underlying PMU hardware, some of which may actually be overridden by the perf_event interface, such as the monitoring privilege levels. The \fBPFM_OS_PERF_EVENT_EXT\fR extends \fBPFM_OS_EVENT\fR to add modifiers controlled only by the perf_event interface, such as sampling period (\fBperiod\fR), frequency (\fBfreq\fR) and exclusive resource access (\fBexcl\fR). .nf typedef struct { struct perf_event_attr *attr; char **fstr; size_t size; int idx; int cpu; int flags; } pfm_perf_encode_arg_t; .fi The fields are defined as follows: .RS .TP .B attr A pointer to a struct perf_event_attr as defined in perf_event.h. This field cannot be NULL on entry. The struct is not completely overwritten by the call. The library only modifies the fields it knows about, thereby allowing perf_event ABI mismatch between caller and library. .TP .B fstr Same behavior as is described for PFM_OS_NONE above. .TP .B size This field contains the size of the struct passed. This field is used to provide for extensibility of the struct without compromising backward compatibility. The value should be set to \fBsizeof(pfm_perf_encode_arg_t)\fR. If instead, a value of \fB0\fR is specified, the library assumes the struct passed is identical to the first ABI version which size is \fBPFM_PERF_ENCODE_ABI0\fR. Thus, if fields were added after the first ABI, they will not be set by the library. The library does check that bytes beyond what is implemented are zeroes. .TP .B idx Upon return, this field contains the opaque unique identifier for the event described in \fBstr\fR. This index can be used to retrieve information about the event using \fBpfm_get_event_info()\fR, for instance. .TP .B cpu Not used yet. .TP .B flags Not used yet. .RE .PP Here is a example of how this function could be used with PFM_OS_NONE: .nf #include #include #include int main(int argc, char **argv) { pfm_raw_pmu_encode_t raw; int ret; ret = pfm_initialize(); if (ret != PFMLIB_SUCCESS) errx(1, "cannot initialize library %s", pfm_strerror(ret)); memset(&raw, 0, sizeof(raw)); ret = pfm_get_os_event_encoding("RETIRED_INSTRUCTIONS", PFM_PLM3, PFM_OS_NONE, &raw); if (ret != PFM_SUCCESS) err(1", cannot get encoding %s", pfm_strerror(ret)); for(i=0; i < raw.count; i++) printf("count[%d]=0x%"PRIx64"\\n", i, raw.codes[i]); free(raw.codes); return 0; } .fi .SH RETURN The function returns in \fBarg\fR the encoding of the event for the os passed in \fBos\fR. The content of \fBarg\fR depends on the \fBos\fR argument. Upon success, \fBPFM_SUCCESS\fR is returned otherwise a specific error code is returned. .SH ERRORS .TP .B PFM_ERR_TOOSMALL The \fBcode\fR argument is too small for the encoding. .TP .B PFM_ERR_INVAL The \fBcode\fR or \fBcount\fR argument is \fBNULL\fR or the \fBstr\fR contains more than one symbolic event. .TP .B PFM_ERR_NOMEM Not enough memory. .TP .B PFM_ERR_NOTFOUND Event not found. .TP .B PFM_ERR_ATTR Invalid event attribute (unit mask or modifier) .TP .B PFM_ERR_ATTR_VAL Invalid modifier value. .TP .B PFM_ERR_ATTR_SET attribute already set, cannot be changed. .TP .B PFM_ERR_ATTR_UMASK Missing unit mask. .TP .B PFM_ERR_ATTR_FEATCOMB Unit masks or features cannot be combined into a single event. .SH AUTHOR Stephane Eranian .PP libpfm-4.9.0/docs/man3/libpfm_intel_bdx_unc_sbo.30000664000175000017500000000356713223402656021514 0ustar eranianeranian.TH LIBPFM 3 "June, 2017" "" "Linux Programmer's Manual" .SH NAME libpfm_intel_bdx_unc_sbo - support for Intel Broadwell Server S-Box uncore PMU .SH SYNOPSIS .nf .B #include .sp .B PMU name: bdx_unc_sbo .B PMU desc: Intel Broadwell Server S-Box uncore PMU .sp .SH DESCRIPTION The library supports the Intel Broadwell server Ring Transfer unit (S-Box) uncore PMU. This PMU model only exists on various Broadwell server models (79, 86). .SH MODIFIERS The following modifiers are supported on Intel Broadwell server S-Box uncore PMU: .TP .B e Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one. This is a boolean modifier. .TP .B t Set the threshold value. When set to a non-zero value, the counter counts the number of HA cycles in which the number of occurrences of the event is greater or equal to the threshold. This is an integer modifier with values in the range [0:15]. .TP .B i Invert the meaning of the threshold or edge filter. If set, the event counts when strictly less than N occurrences occur per cycle if threshold is set to N. When invert is set, then threshold must be set to non-zero value. If set, the event counts when the event transitions from occurring to not occurring (falling edge) when edge detection is set. This is a boolean modifier .TP .B i Invert the meaning of the threshold or edge filter. If set, the event counts when strictly less than N occurrences occur per cycle if threshold is set to N. When invert is set, then threshold must be set to non-zero value. If set, the event counts when the event transitions from occurring to not occurring (falling edge) when edge detection is set. This is a boolean modifier .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/libpfm_intel_snb_unc.30000664000175000017500000000361313223402656020646 0ustar eranianeranian.TH LIBPFM 3 "August, 2012" "" "Linux Programmer's Manual" .SH NAME libpfm_intel_snb_unc - support for Intel Sandy Bridge uncore PMU .SH SYNOPSIS .nf .B #include .sp .B PMU name: snb_unc_cbo0, snb_unc_cbo1, snb_unc_cbo2, snb_unc_cbo3 .B PMU desc: Intel Sandy Bridge C-box uncore .sp .SH DESCRIPTION The library supports the Intel Sandy Bridge client part (model 42) uncore PMU. The support is currently limited to the Coherency Box, so called C-Box for up to 4 physical cores. Each physical core has an associated C-Box which it uses to communicate with the L3 cache. The C-boxes all support the same set of events. However, Core 0 C-box (snb_unc_cbo0) supports an additional uncore clock ticks event: \fBUNC_CLOCKTICKS\fR. .SH MODIFIERS The following modifiers are supported on Intel Sandy Bridge C-Box uncore PMU: .TP .B i Invert the meaning of the event. The counter will now count cycles in which the event is \fBnot\fR occurring. This is a boolean modifier .TP .B e Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a counter mask modifier (m) with a value greater or equal to one. This is a boolean modifier. .TP .B c Set the counter mask value. The mask acts as a threshold. The counter will count the number of cycles in which the number of occurrences of the event is greater or equal to the threshold. This is an integer modifier with values in the range [0:255]. .P Both the \fBUNC_CBO_CACHE_LOOKUP\fR and \fBUNC_CBO_XSNP_RESPONSE\fR requires two umasks to be valid. For \fBUNC_CBO_CACHE_LOOKUP\fR the first umask must be one of the MESI state umasks, the second has to be one of the filters. For \fBUNC_CBO_XSNP_RESPONSE\fR the first umask must be one of the snoop types, the second has to be one of the filters. .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/libpfm_mips_74k.30000664000175000017500000000363013223402656017460 0ustar eranianeranian.TH LIBPFM 3 "September, 2011" "" "Linux Programmer's Manual" .SH NAME libpfm_mips_74k - support for MIPS 74k processors .SH SYNOPSIS .nf .B #include .sp .B PMU name: mips_74k .B PMU desc: MIPS 74k .sp .SH DESCRIPTION The library supports MIPS 74k processors in big or little endian modes. .SH ENCODINGS On this processor, what is measured by an event depends on the event code and on the counter it is programmed on. Usually the meaning of the event code changes between odd and even indexed counters. For instance, event code \fB0x2\fR means 'PREDICTED_JR31' when programmed on even-indexed counters and it means 'JR_31_MISPREDICTIONS' when programmed on odd-indexed counters. To correctly measure an event, one needs both the event encoding and a list of possible counters. When \fRpfm_get_os_event_encoding()\fR is used with \fBPFM_OS_NONE\fR to return the raw PMU encoding, the library returns two values: the event encoding as per the architecture manual and a bitmask of valid counters to program it on. For instance, for 'JR_31_MISPREDICTIONS' The library returns codes[0] = 0x4a, codes[1]= 0xa (supported on counter 1, 3). The encoding for a specific kernel interface may vary and is handled internally by the library. .SH MODIFIERS The following modifiers are supported on MIPS 74k. .TP .B u Measure at user level. This corresponds to \fBPFM_PLM3\fR. This is a boolean modifier. .TP .B k Measure at kernel level. This corresponds to \fBPFM_PLM0\fR. This is a boolean modifier. .TP .B e Measure at exception level. This corresponds to \fBPFM_PLM2\fR. This is a boolean modifier. .TP .B s Measure at supervisor level. This corresponds to \fBPFM_PLM1\fR. This is a boolean modifier. It should be noted that those modifiers are available for encoding as raw mode with \fBPFM_OS_NONE\fR but they may not all be present with specific kernel interfaces. .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/libpfm_arm_ac7.30000664000175000017500000000142513223402656017334 0ustar eranianeranian.TH LIBPFM 3 "August, 2012" "" "Linux Programmer's Manual" .SH NAME libpfm_arm_ac7 - support for Arm Cortex A7 PMU .SH SYNOPSIS .nf .B #include .sp .B PMU name: arm_ac7 .B PMU desc: ARM Cortex A7 .sp .SH DESCRIPTION The library supports the ARM Cortex A7 core PMU. This PMU supports 4 counters and privilege levels filtering. .SH MODIFIERS The following modifiers are supported on ARM Cortex A7: .TP .B u Measure at the user level. This corresponds to \fBPFM_PLM3\fR. This is a boolean modifier. .TP .B k Measure at the kernel level. This corresponds to \fBPFM_PLM0\fR. This is a boolean modifier. .TP .B hv Measure at the hypervisor level. This corresponds to \fBPFM_PLMH\fR. This is a boolean modifier. .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/libpfm_intel_ivbep_unc_r3qpi.30000664000175000017500000000215413223402656022306 0ustar eranianeranian.TH LIBPFM 3 "February, 2014" "" "Linux Programmer's Manual" .SH NAME libpfm_intel_ivbep_unc_r3qpi - support for Intel Ivy Bridge-EP R3QPI uncore PMU .SH SYNOPSIS .nf .B #include .sp .B PMU name: ivbep_unc_r3qpi0, ivbep_unc_r3qpi1, ivbep_unc_r3qpi2 .B PMU desc: Intel Ivy Bridge-EP R3QPI uncore PMU .sp .SH DESCRIPTION The library supports the Intel Ivy Bridge R3QPI uncore PMU. This PMU model only exists on Ivy Bridge model 62. .SH MODIFIERS The following modifiers are supported on Intel Ivy Bridge R3PQI uncore PMU: .TP .B e Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one. This is a boolean modifier. .TP .B t Set the threshold value. When set to a non-zero value, the counter counts the number of R3QPI cycles in which the number of occurrences of the event is greater or equal to the threshold. This is an integer modifier with values in the range [0:15]. .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/libpfm_intel_knc.30000664000175000017500000000250413223402656017770 0ustar eranianeranian.TH LIBPFM 3 "September, 2012" "" "Linux Programmer's Manual" .SH NAME libpfm_intel_knc - support for Intel Knights Corner .SH SYNOPSIS .nf .B #include .sp .B PMU name: knc .B PMU desc: Intel Knights Corner .sp .SH DESCRIPTION The library supports Intel Knights Corner processors. .SH MODIFIERS The following modifiers are supported on Intel Knights Corner processors: .TP .B u Measure at user level which includes privilege levels 1, 2, 3. This corresponds to \fBPFM_PLM3\fR. This is a boolean modifier. .TP .B k Measure at kernel level which includes privilege level 0. This corresponds to \fBPFM_PLM0\fR. This is a boolean modifier. .TP .B i Invert the meaning of the event. The counter will now count cycles in which the event is \fBnot\fR occurring. This is a boolean modifier .TP .B e Enable edge detection, i.e., count only when there is a state transition. This is a boolean modifier. .TP .B c Set the counter mask value. The mask acts as a threshold. The counter will count the number of cycles in which the number of occurrences of the event is greater or equal to the threshold. This is an integer modifier with values in the range [0:255]. .TP .B t Measure on all threads at the same time assuming hyper-threading is enabled. This is a boolean modifier. .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/libpfm_intel_bdx_unc_pcu.30000664000175000017500000000467013223402656021514 0ustar eranianeranian.TH LIBPFM 3 "June, 2017" "" "Linux Programmer's Manual" .SH NAME libpfm_intel_bdx_unc_pcu - support for Intel Broadwell Server Power Controller Unit (PCU) uncore PMU .SH SYNOPSIS .nf .B #include .sp .B PMU name: bdx_unc_pcu .B PMU desc: Intel Broadwell Server PCU uncore PMU .sp .SH DESCRIPTION The library supports the Intel Broadwell Server Power Controller Unit uncore PMU. This PMU model only exists on various Broadwell server models (79, 86). .SH MODIFIERS The following modifiers are supported on Intel Broadwell server PCU uncore PMU: .TP .B e Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one. This is a boolean modifier. .TP .B t Set the threshold value. When set to a non-zero value, the counter counts the number of HA cycles in which the number of occurrences of the event is greater or equal to the threshold. This is an integer modifier with values in the range [0:15]. .TP .B i Invert the meaning of the threshold or edge filter. If set, the event counts when strictly less than N occurrences occur per cycle if threshold is set to N. When invert is set, then threshold must be set to non-zero value. If set, the event counts when the event transitions from occurring to not occurring (falling edge) when edge detection is set. This is a boolean modifier .TP .B ff Enable frequency band filtering. This modifier applies only to the UNC_P_FREQ_BANDx_CYCLES events, where x is [0-3]. The modifiers expects an integer in the range [0-255]. The value is interpreted as a frequency value to be multiplied by 100Mhz. Thus if the value is 32, then all cycles where the processor is running at 3.2GHz and more are counted. .SH Frequency band filtering There are 3 events which support frequency band filtering, namely, UNC_P_FREQ_BAND0_CYCLES, UNC_P_FREQ_BAND1_CYCLES, UNC_P_FREQ_BAND2_CYCLES, UNC_P_FREQ_BAND3_CYCLES. The frequency filter (available via the ff modifier) is stored into a PMU shared register which hold all 4 possible frequency bands, one per event. However, the library generate the encoding for each event individually because it processes events one at a time. The caller or the underlying kernel interface may have to merge the band filter settings to program the filter register properly. .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/libpfm_intel_bdx_unc_r3qpi.30000664000175000017500000000275513223402656021765 0ustar eranianeranian.TH LIBPFM 3 "June, 2017" "" "Linux Programmer's Manual" .SH NAME libpfm_intel_bdx_unc_r3qpi - support for Intel Broadwell Server R3QPI uncore PMU .SH SYNOPSIS .nf .B #include .sp .B PMU name: bdx_unc_r3qpi[0-2] .B PMU desc: Intel Broadwell server R3QPI uncore PMU .sp .SH DESCRIPTION The library supports the Intel Broadwell server R3QPI uncore PMU. This PMU model only exists on various Broadwell server models (79, 86). .SH MODIFIERS The following modifiers are supported on Intel Broadwell server R3PQI uncore PMU: .TP .B e Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one. This is a boolean modifier. .TP .B t Set the threshold value. When set to a non-zero value, the counter counts the number of R3QPI cycles in which the number of occurrences of the event is greater or equal to the threshold. This is an integer modifier with values in the range [0:15]. .TP .B i Invert the meaning of the threshold or edge filter. If set, the event counts when strictly less than N occurrences occur per cycle if threshold is set to N. When invert is set, then threshold must be set to non-zero value. If set, the event counts when the event transitions from occurring to not occurring (falling edge) when edge detection is set. This is a boolean modifier .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/libpfm_intel_hsw.30000664000175000017500000000777413223402656020034 0ustar eranianeranian.TH LIBPFM 3 "April, 2013" "" "Linux Programmer's Manual" .SH NAME libpfm_intel_hsw - support for Intel Haswell core PMU .SH SYNOPSIS .nf .B #include .sp .B PMU name: hsw .B PMU desc: Intel Haswell .B PMU name: hsw_ep .B PMU desc: Intel Haswell-EP .sp .SH DESCRIPTION The library supports the Intel Haswell and Haswell-EP core PMU. It should be noted that this PMU model only covers each core's PMU and not the socket level PMU. On Haswell, the number of generic counters depends on the Hyperthreading (HT) mode. When HT is on, then only 4 generic counters are available. When HT is off, then 8 generic counters are available. The \fBpfm_get_pmu_info()\fR function returns the maximum number of generic counters in \fBnum_cntrs\fr. .SH MODIFIERS The following modifiers are supported on Intel Haswell processors: .TP .B u Measure at user level which includes privilege levels 1, 2, 3. This corresponds to \fBPFM_PLM3\fR. This is a boolean modifier. .TP .B k Measure at kernel level which includes privilege level 0. This corresponds to \fBPFM_PLM0\fR. This is a boolean modifier. .TP .B i Invert the meaning of the event. The counter will now count cycles in which the event is \fBnot\fR occurring. This is a boolean modifier .TP .B e Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a counter mask modifier (m) with a value greater or equal to one. This is a boolean modifier. .TP .B c Set the counter mask value. The mask acts as a threshold. The counter will count the number of cycles in which the number of occurrences of the event is greater or equal to the threshold. This is an integer modifier with values in the range [0:255]. .TP .B t Measure on both threads at the same time assuming hyper-threading is enabled. This is a boolean modifier. .TP .B ldlat Pass a latency threshold to the MEM_TRANS_RETIRED:LOAD_LATENCY event. This is an integer attribute that must be in the range [3:65535]. It is required for this event. Note that the event must be used with precise sampling (PEBS). .TP .B intx Monitor the event only when executing inside a transactional memory region (in tx). Event does not count otherwise. This is a boolean modifiers. Default value is 0. .TP .B intxcp Do not count occurrences of the event when they are inside an aborted transactional memory region. This is a boolean modifier. Default value is 0. .SH OFFCORE_RESPONSE events Intel Haswell provides two offcore_response events. They are called OFFCORE_RESPONSE_0 and OFFCORE_RESPONSE_1. Those events need special treatment in the performance monitoring infrastructure because each event uses an extra register to store some settings. Thus, in case multiple offcore_response events are monitored simultaneously, the kernel needs to manage the sharing of that extra register. The offcore_response events are exposed as a normal events by the library. The extra settings are exposed as regular umasks. The library takes care of encoding the events according to the underlying kernel interface. On Intel Haswell, the umasks are divided into three categories: request, supplier and snoop. The user must provide at least one umask for each category. The categories are shown in the umask descriptions. There is also the special response umask called \fBANY_RESPONSE\fR. When this umask is used then it overrides any supplier and snoop umasks. In other words, users can specify either \fBANY_RESPONSE\fR \fBOR\fR any combinations of supplier + snoops. In case no supplier or snoop is specified, the library defaults to using \fBANY_RESPONSE\fR. For instance, the following are valid event selections: .TP .B OFFCORE_RESPONSE_0:DMND_DATA_RD:ANY_RESPONSE .TP .B OFFCORE_RESPONSE_0:ANY_REQUEST .TP .B OFFCORE_RESPONSE_0:ANY_RFO:LLC_HITM:SNOOP_ANY .P But the following are illegal: .TP .B OFFCORE_RESPONSE_0:ANY_RFO:LLC_HITM:ANY_RESPONSE .TP .B OFFCORE_RESPONSE_0:ANY_RFO:LLC_HITM:SNOOP_ANY:ANY_RESPONSE .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/libpfm_intel_ivbep_unc_irp.30000664000175000017500000000206113223402656022037 0ustar eranianeranian.TH LIBPFM 3 "February, 2014" "" "Linux Programmer's Manual" .SH NAME libpfm_intel_ivbep_unc_irp - support for Intel Ivy Bridge-EP IRP uncore PMU .SH SYNOPSIS .nf .B #include .sp .B PMU name: ivbep_unc_irp .B PMU desc: Intel Ivy Bridge-EP IRP uncore PMU .sp .SH DESCRIPTION The library supports the Intel Ivy Bridge uncore PMU. This PMU model only exists on Ivy Bridge model 62. .SH MODIFIERS The following modifiers are supported on Intel Ivy Bridge IRP uncore PMU: .TP .B e Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one. This is a boolean modifier. .TP .B t Set the threshold value. When set to a non-zero value, the counter counts the number of cycles in which the number of occurrences of the event is greater or equal to the threshold. This is an integer modifier with values in the range [0:255]. .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/libpfm_intel_ivbep_unc_pcu.30000664000175000017500000000402713223402656022040 0ustar eranianeranian.TH LIBPFM 3 "February, 2014" "" "Linux Programmer's Manual" .SH NAME libpfm_intel_ivbep_unc_pcu - support for Intel Ivy Bridge-EP Power Controller Unit (PCU) uncore PMU .SH SYNOPSIS .nf .B #include .sp .B PMU name: ivbep_unc_pcu .B PMU desc: Intel Ivy Bridge-EP PCU uncore PMU .sp .SH DESCRIPTION The library supports the Intel Ivy Bridge Power Controller Unit uncore PMU. This PMU model only exists on Ivy Bridge model 62. .SH MODIFIERS The following modifiers are supported on Intel Ivy Bridge PCU uncore PMU: .TP .B e Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one. This is a boolean modifier. .TP .B t Set the threshold value. When set to a non-zero value, the counter counts the number of HA cycles in which the number of occurrences of the event is greater or equal to the threshold. This is an integer modifier with values in the range [0:15]. .TP .B ff Enable frequency band filtering. This modifier applies only to the UNC_P_FREQ_BANDx_CYCLES events, where x is [0-3]. The modifiers expects an integer in the range [0-255]. The value is interpreted as a frequency value to be multiplied by 100Mhz. Thus if the value is 32, then all cycles where the processor is running at 3.2GHz and more are counted. .SH Frequency band filtering There are 3 events which support frequency band filtering, namely, UNC_P_FREQ_BAND0_CYCLES, UNC_P_FREQ_BAND1_CYCLES, UNC_P_FREQ_BAND2_CYCLES, UNC_P_FREQ_BAND3_CYCLES. The frequency filter (available via the ff modifier) is stored into a PMU shared register which hold all 4 possible frequency bands, one per event. However, the library generate the encoding for each event individually because it processes events one at a time. The caller or the underlying kernel interface may have to merge the band filter settings to program the filter register properly. .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/libpfm_intel_snbep_unc_cbo.30000664000175000017500000000643213223402656022020 0ustar eranianeranian.TH LIBPFM 3 "August, 2012" "" "Linux Programmer's Manual" .SH NAME libpfm_intel_snbep_unc_cbo - support for Intel Sandy Bridge-EP C-Box uncore PMU .SH SYNOPSIS .nf .B #include .sp .B PMU name: snbep_unc_cbo[0-7] .B PMU desc: Intel Sandy Bridge-EP C-Box uncore PMU .sp .SH DESCRIPTION The library supports the Intel Sandy Bridge C-Box (coherency engine) uncore PMU. This PMU model only exists on Sandy Bridge model 45. There is one C-box PMU per physical core. Therefore there are eight identical C-Box PMU instances numbered frmo 0 to 7. On dual-socket systems, the number refers to the C-Box PMU on the socket where the program runs. For instance, if running on CPU8, then snbep_unc_cbo0 refers to the C-Box for physical core 0 on socket 1. Conversely, if running on CPU0, then the same snbep_unc_cbo0 refers to the C-Box for physical core 0 but on socket 0. Each C-Box PMU implements 4 generic counters and a filter register used only with certain events and umasks. .SH MODIFIERS The following modifiers are supported on Intel Sandy Bridge C-Box uncore PMU: .TP .B i Invert the meaning of the event. The counter will now count C-Box cycles in which the event is \fBnot\fR occurring. This is a boolean modifier .TP .B e Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one. This is a boolean modifier. .TP .B t Set the threshold value. When set to a non-zero value, the counter counts the number of C-Box cycles in which the number of occurrences of the event is greater or equal to the threshold. This is an integer modifier with values in the range [0:255]. .TP .B nf Node filter. Certain events, such as UNC_C_LLC_LOOKUP, UNC_C_LLC_VICTIMS, provide a \fBNID\fR umask. Sometimes the \fBNID\fR is combined with other filtering capabilities, such as opcodes. The node filter is an 8-bit max bitmask. A node corresponds to a processor socket. The legal values therefore depend on the underlying hardware configuration. For dual-socket systems, the bitmask has two valid bits [0:1]. .TP .B cf Core Filter. This is a 3-bit filter which is used to filter based on physical core origin of the C-Box request. Possible values are 0-7. If the filter is not specified, then no filtering takes place. .TP .B tf Thread Filter. This is a 1-bit filter which is used to filter C-Box requests based on logical processor (hyper-thread) identification. Possibles values are 0-1. If the filter is not specified, then no filtering takes place. .SH Opcode filtering Certain events, such as UNC_C_TOR_INSERTS supports opcode matching on the C-BOX transaction type. To use this feature, first an opcode matching umask must be selected, e.g., MISS_OPCODE. Second, the opcode to match on must be selected via a second umask among the OPC_* umasks. For instance, UNC_C_TOR_INSERTS:OPCODE:OPC_RFO, counts the number of TOR insertions for RFO transactions. Opcode matching may be combined with node filtering with certain umasks. In general the filtering support is encoded into the umask name, e.g., NID_OPCODE supports both node and opcode filtering. For instance, UNC_C_TOR_INSERTS:NID_OPCODE:OPC_RFO:nf=1. .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/pfm_find_event.30000664000175000017500000000747113223402656017464 0ustar eranianeranian.TH LIBPFM 3 "September, 2009" "" "Linux Programmer's Manual" .SH NAME pfm_find_event \- search for an event masks .SH SYNOPSIS .nf .B #include .sp .BI "int pfm_find_event(const char *"str ");" .sp .SH DESCRIPTION This function is used to convert an event string passed in \fBstr\fR into an opaque event identifier, i.e., the return value. Events are first manipulated a strings which contain the event name, sub-event names and optional filters and modifiers. This function analyzes the string and try to find the matching event. The event string is a structured string and it is composed as follows: .TP .B [pmu_name::]event_name[:unit_mask][:modifier|:modifier=val] .PP The various components are separated by \fB:\fR or \fB::\fR, they are defined as follows: .TP .B pmu_name This is an optional prefix to designate a specific PMU model. With the prefix the event which matches the event_name is used. In case multiple PMU models are activated, there may be conflict with identical event names to mean the same or different things. In that case, it is necessary to fully specify the event with a pmu_name. That string corresponds to what is returned by \fBpfm_get_pmu_name()\fR. .TP .B event_name This is the event name and is required. The library is not case sensitive on event string. The event name must match \fBcompletely\fR the actual event name; it cannot be a substring. .TP .B unit_mask The optional unit mask which can be considered like a sub-event of the major event. If a event has unit masks, and there is no default, then at least one unit mask must be passed in the string. Multiple unit masks may be specified for a single event. .TP .B modifier A modifier is an optional filter which is provided by the hardware register hosting the event or by the underlying kernel infrastructure. Typical modifiers include privilege level filters. Some modifiers are simple boolean, in which case just passing their names is equivalent to setting their value to \fBtrue\fR. Other modifiers need a specific value, in which case it is provided after the equal sign. No space is tolerate around the equal sign. The list of modifiers depends on the host PMU and underlying kernel API. They are documented in PMU-specific documentation. Multiple modifiers may be passed. There is not order between unit masks and modifiers. .PP The library uses the generic term \fBattribute\fR to designate both unit masks and modifiers. Here are a few examples of event strings: .TP .B amd64::RETIRED_INSTRUCTIONS:u Event RETIRED_INSTRUCTION on AMD64 processor, measure at user privilege level only .TP .B RS_UOPS_DISPATCHED:c=1:i:u Event RS_UOPS_DISPATCHED measured at user privilege level only, and with counter-mask set to 1 .PP For the purpose of this function, only the pmu_name and event_name are considered, everything else is parsed, thus must be valid, but is ignored. The function searches only for one event per call. As a convenience, the function will identify the event up to the first comma. In other words, if \fBstr\fR is equal to "EVENTA,EVENTB", then the function will only look at EVENTA and will not return an error because of invalid event string. This is handy when parsing constant event strings containing multiple, comma-separated, events. .SH RETURN The function returns the opaque event identifier that corresponds that the event string. In case of error, a negative error code is returned instead. .SH ERRORS .TP .B PFMLIB_ERR_NOINIT The library has not been initialized properly. .TP .B PFMLIB_ERR_INVAL The event string is NULL. .TP .B PFMLIB_ERR_NOMEM The library ran out of memory. .TP .B PFMLIB_ERR_NOTFOUND The event was not found .TP .B PFMLIB_ERR_ATTR Invalid event attribute .TP .B PFMLIB_ERR_ATTR_VAL Invalid event attribute value .TP .B PFMLIB_ERR_TOOMANY Too many event attributes passed .SH AUTHOR Stephane Eranian .PP libpfm-4.9.0/docs/man3/libpfm_intel_glm.30000664000175000017500000001063313223402656017776 0ustar eranianeranian.TH LIBPFM 3 "July, 2016" "" "Linux Programmer's Manual" .SH NAME libpfm_intel_glm - support for Intel Goldmont core PMU .SH SYNOPSIS .nf .B #include .sp .B PMU name: glm .B PMU desc: Intel Goldmont .sp .SH DESCRIPTION The library supports the Intel Goldmont core PMU. It should be noted that this PMU model only covers each core's PMU and not the socket level PMU. On Goldmont, the number of generic counters is 4. There is no HyperThreading support. The \fBpfm_get_pmu_info()\fR function returns the maximum number of generic counters in \fBnum_cntrs\fr. .SH MODIFIERS The following modifiers are supported on Intel Goldmont processors: .TP .B u Measure at user level which includes privilege levels 1, 2, 3. This corresponds to \fBPFM_PLM3\fR. This is a boolean modifier. .TP .B k Measure at kernel level which includes privilege level 0. This corresponds to \fBPFM_PLM0\fR. This is a boolean modifier. .TP .B i Invert the meaning of the event. The counter will now count cycles in which the event is \fBnot\fR occurring. This is a boolean modifier .TP .B e Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a counter mask modifier (m) with a value greater or equal to one. This is a boolean modifier. .TP .B c Set the counter mask value. The mask acts as a threshold. The counter will count the number of cycles in which the number of occurrences of the event is greater or equal to the threshold. This is an integer modifier with values in the range [0:255]. .SH OFFCORE_RESPONSE events Intel Goldmont provides two offcore_response events. They are called OFFCORE_RESPONSE_0 and OFFCORE_RESPONSE_1. Those events need special treatment in the performance monitoring infrastructure because each event uses an extra register to store some settings. Thus, in case multiple offcore_response events are monitored simultaneously, the kernel needs to manage the sharing of that extra register. The offcore_response events are exposed as normal events by the library. The extra settings are exposed as regular umasks. The library takes care of encoding the events according to the underlying kernel interface. On Intel Goldmont, the umasks are divided into 4 categories: request, supplier and snoop and average latency. Offcore_response event has two modes of operations: normal and average latency. In the first mode, the two offcore_respnse events operate independently of each other. The user must provide at least one umask for each of the first 3 categories: request, supplier, snoop. In the second mode, the two offcore_response events are combined to compute an average latency per request type. For the normal mode, there is a special supplier (response) umask called \fBANY_RESPONSE\fR. When this umask is used then it overrides any supplier and snoop umasks. In other words, users can specify either \fBANY_RESPONSE\fR \fBOR\fR any combinations of supplier + snoops. In case no supplier or snoop is specified, the library defaults to using \fBANY_RESPONSE\fR. For instance, the following are valid event selections: .TP .B OFFCORE_RESPONSE_0:DMND_DATA_RD:ANY_RESPONSE .TP .B OFFCORE_RESPONSE_0:ANY_REQUEST .TP .B OFFCORE_RESPONSE_0:ANY_RFO:LLC_HITM:SNOOP_ANY .P But the following are illegal: .TP .B OFFCORE_RESPONSE_0:ANY_RFO:LLC_HITM:ANY_RESPONSE .TP .B OFFCORE_RESPONSE_0:ANY_RFO:LLC_HITM:SNOOP_ANY:ANY_RESPONSE .P In average latency mode, \fBOFFCORE_RESPONSE_0\fR must be programmed to select the request types of interest, for instance, \fBDMND_DATA_RD\fR, and the \fBOUTSTANDING\fR umask must be set and no others. the library will enforce that restriction as soon as the \fBOUTSTANDING\fR umask is used. Then \fBOFFCORE_RESPONSE_1\fR must be set with the same request types and the \fBANY_RESPONSE\fR umask. It should be noted that the library encodes events independently of each other and therefore cannot verify that the requests are matching between the two events. Example of average latency settings: .TP .B OFFCORE_RESPONSE_0:DMND_DATA_RD:OUTSTANDING+OFFCORE_RESPONSE_1:DMND_DATA_RD:ANY_RESPONSE .TP .B OFFCORE_RESPONSE_0:ANY_REQUEST:OUTSTANDING+OFFCORE_RESPONSE_1:ANY_REQUEST:ANY_RESPONSE .P The average latency for the request(s) is obtained by dividing the counts of \fBOFFCORE_RESPONSE_0\fR by the count of \fBOFFCORE_RESPONSE_1\fR. The ratio is expressed in core cycles. .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/libpfm_intel_ivbep_unc_cbo.30000664000175000017500000000711313223402656022013 0ustar eranianeranian.TH LIBPFM 3 "February, 2014" "" "Linux Programmer's Manual" .SH NAME libpfm_intel_ivbep_unc_cbo - support for Intel Ivy Bridge-EP C-Box uncore PMU .SH SYNOPSIS .nf .B #include .sp .B PMU name: ivbep_unc_cbo[0-7] .B PMU desc: Intel Ivy Bridge-EP C-Box uncore PMU .sp .SH DESCRIPTION The library supports the Intel Ivy Bridge C-Box (coherency engine) uncore PMU. This PMU model only exists on Ivy Bridge model 62. There is one C-box PMU per physical core. Therefore there are up to fifteen identical C-Box PMU instances numbered from 0 to 14. On dual-socket systems, the number refers to the C-Box PMU on the socket where the program runs. For instance, if running on CPU15, then ivbep_unc_cbo0 refers to the C-Box for physical core 0 on socket 1. Conversely, if running on CPU0, then the same ivbep_unc_cbo0 refers to the C-Box for physical core 0 but on socket 0. Each C-Box PMU implements 4 generic counters and two filter registers used only with certain events and umasks. .SH MODIFIERS The following modifiers are supported on Intel Ivy Bridge C-Box uncore PMU: .TP .B e Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one. This is a boolean modifier. .TP .B t Set the threshold value. When set to a non-zero value, the counter counts the number of C-Box cycles in which the number of occurrences of the event is greater or equal to the threshold. This is an integer modifier with values in the range [0:255]. .TP .B nf Node filter. Certain events, such as UNC_C_LLC_LOOKUP, UNC_C_LLC_VICTIMS, provide a \fBNID\fR umask. Sometimes the \fBNID\fR is combined with other filtering capabilities, such as opcodes. The node filter is an 8-bit max bitmask. A node corresponds to a processor socket. The legal values therefore depend on the underlying hardware configuration. For dual-socket systems, the bitmask has two valid bits [0:1]. .TP .B cf Core Filter. This is a 3-bit filter which is used to filter based on physical core origin of the C-Box request. Possible values are 0-7. If the filter is not specified, then no filtering takes place. .TP .B tf Thread Filter. This is a 1-bit filter which is used to filter C-Box requests based on logical processor (hyper-thread) identification. Possibles values are 0-1. If the filter is not specified, then no filtering takes place. .TP .B nc Non-Coherent. This is a 1-bit filter which is used to filter C-Box requests only for the TOR_INSERTS and TOR_OCCUPANCY umasks using the OPCODE matcher. If the filter is not specified, then no filtering takes place. .TP .B isoc Isochronous. This is a 1-bit filter which is used to filter C-Box requests only for the TOR_INSERTS and TOR_OCCUPANCY umasks using the OPCODE matcher. If the filter is not specified, then no filtering takes place. .SH Opcode filtering Certain events, such as UNC_C_TOR_INSERTS supports opcode matching on the C-BOX transaction type. To use this feature, first an opcode matching umask must be selected, e.g., MISS_OPCODE. Second, the opcode to match on must be selected via a second umask among the OPC_* umasks. For instance, UNC_C_TOR_INSERTS:OPCODE:OPC_RFO, counts the number of TOR insertions for RFO transactions. Opcode matching may be combined with node filtering with certain umasks. In general, the filtering support is encoded into the umask name, e.g., NID_OPCODE supports both node and opcode filtering. For instance, UNC_C_TOR_INSERTS:NID_OPCODE:OPC_RFO:nf=1. .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/pfm_get_event_info.30000664000175000017500000001055413223402656020332 0ustar eranianeranian.TH LIBPFM 3 "December, 2009" "" "Linux Programmer's Manual" .SH NAME pfm_get_event_info \- get event information .SH SYNOPSIS .nf .B #include .sp .BI "int pfm_get_event_info(int " idx ", pfm_os_t " os ", pfm_event_info_t *" info ");" .sp .SH DESCRIPTION This function returns in \fBinfo\fR information about a specific event designated by its opaque unique identifier in \fBidx\fR for the operating system specified in \fBos\fR. The \fBpfm_event_info_t\fR structure is defined as follows: .nf typedef struct { const char *name; const char *desc; const char *equiv; size_t size; uint64_t code; pfm_pmu_t pmu; pfm_dtype_t dtype int idx; int nattrs; struct { unsigned int is_precise:1; unsigned int reserved_bits:31; }; } pfm_event_info_t; .fi The fields of this structure are defined as follows: .TP .B name This is the name of the event. This is a read-only string. .TP .B desc This is the description of the event. This is a read-only string. It may contain multiple sentences. .TP .B equiv Certain events may be just variations of actual events. They may be provided as handy shortcuts to avoid supplying a long list of attributes. For those events, this field is not NULL and contains the complete equivalent event string. .TP .B code This is the raw event code. It should not be confused with the encoding of the event. This field represents only the event selection code, it does not include any unit mask or attribute settings. .TP .B pmu This is the identification of the PMU model this event belongs to. It is of type \fBpfm_pmu_t\fR. Using this value and the \fBpfm_get_pmu_info\fR function, it is possible to get PMU information. .TP .B dtype This field returns the representation of the event data. By default, it is \fBPFM_DATA_UINT64\fR. .B idx This is the event unique opaque identifier. It is identical to the idx passed to the call and is provided for completeness. .TP .B nattrs This is the number of attributes supported by this event. Attributes may be unit masks or modifiers. If the event has not attribute, then the value of this field is simply 0. .TP .B size This field contains the size of the struct passed. This field is used to provide for extensibility of the struct without compromising backward compatibility. The value should be set to \fBsizeof(pfm_event_info_t)\fR. If instead, a value of \fB0\fR is specified, the library assumes the struct passed is identical to the first ABI version which size is \fBPFM_EVENT_INFO_ABI0\fR. Thus, if fields were added after the first ABI, they will not be set by the library. The library does check that bytes beyond what is implemented are zeroes. .TP .B is_precise This bitfield indicates whether or not the event support precise sampling. Precise sampling is a hardware mechanism that avoids instruction address skid when using interrupt-based sampling. When the event has umasks, this field means that at least one umask supports precise sampling. On Intel X86 processors, this indicates whether the event supports Precise Event-Based Sampling (PEBS). .PP The \fBpfm_os_t\fR enumeration provides the following choices: .TP .B PFM_OS_NONE The returned information pertains only to what the PMU hardware exports. No operating system attributes is taken into account. .TP .B PFM_OS_PERF_EVENT The returned information includes the actual PMU hardware and the additional attributes exported by the perf_events kernel interface. The perf_event attributes pertain only the PMU hardware. In case perf_events is not detected, an error is returned. .TP .B PFM_OS_PERF_EVENT_EXT The returned information includes all of what is already provided by \fBPFM_OS_PERF_EVENT\fR plus all the software attributes controlled by perf_events, such as sampling period, precise sampling. .PP .SH RETURN If successful, the function returns \fBPFM_SUCCESS\fR and event information in \fBinfo\fR, otherwise it returns an error code. .SH ERRORS .TP .B PFMLIB_ERR_NOINIT Library has not been initialized properly. .TP .B PFMLIB_ERR_INVAL The \fBidx\fR argument is invalid or \fBinfo\fR is \fBNULL\fR or \fBsize\fR is not zero. .TP .B PFMLIB_ERR_NOTSUPP The requested \fBos\fR is not detected or supported. .SH AUTHOR Stephane Eranian .PP libpfm-4.9.0/docs/man3/libpfm_amd64.30000664000175000017500000000121513223402656016733 0ustar eranianeranian.TH LIBPFM 3 "August, 2010" "" "Linux Programmer's Manual" .SH NAME libpfm_amd64 - support for AMD64 processors .SH SYNOPSIS .nf .B #include .sp .SH DESCRIPTION The library supports all AMD64 processors in both 32 and 64-bit modes. The support is broken down in three groups: .TP .B AMD K7 processors (family 6) .TP .B AMD K8 processors (family 15) .TP .B AMD Family 10h processors (family 16) .sp .TP Each group has a distinct man page. See links below. .SH SEE ALSO libpfm_amd64_k7(3), libpfm_amd64_k8(3), libpfm_amd64_fam10h(3) .SH AUTHORS .nf Stephane Eranian Robert Richter .if .PP libpfm-4.9.0/docs/man3/libpfm_intel_hswep_unc_r2pcie.30000664000175000017500000000270013223402656022452 0ustar eranianeranian.TH LIBPFM 3 "May, 2015" "" "Linux Programmer's Manual" .SH NAME libpfm_intel_hswep_unc_r2pcie - support for Intel Haswell-EP R2 PCIe uncore PMU .SH SYNOPSIS .nf .B #include .sp .B PMU name: hswep_unc_r2pcie .B PMU desc: Intel Haswell-EP R2 PCIe uncore PMU .sp .SH DESCRIPTION The library supports the Intel Haswell R2 PCIe uncore PMU. This PMU model only exists on Haswell model 63. .SH MODIFIERS The following modifiers are supported on Intel Haswell R2PCIe uncore PMU: .TP .B e Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one. This is a boolean modifier. .TP .B t Set the threshold value. When set to a non-zero value, the counter counts the number of R2PCIe cycles in which the number of occurrences of the event is greater or equal to the threshold. This is an integer modifier with values in the range [0:15]. .TP .B i Invert the meaning of the threshold or edge filter. If set, the event counts when strictly less than N occurrences occur per cycle if threshold is set to N. When invert is set, then threshold must be set to non-zero value. If set, the event counts when the event transitions from occurring to not occurring (falling edge) when edge detection is set. This is a boolean modifier .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/libpfm_intel_snbep_unc_ubo.30000664000175000017500000000533613223402656022044 0ustar eranianeranian.TH LIBPFM 3 "August, 2012" "" "Linux Programmer's Manual" .SH NAME libpfm_intel_snbep_unc_ubo - support for Intel Sandy Bridge-EP U-Box uncore PMU .SH SYNOPSIS .nf .B #include .sp .B PMU name: snbep_unc_ubo .B PMU desc: Intel Sandy Bridge-EP U-Box uncore PMU .sp .SH DESCRIPTION The library supports the Intel Sandy Bridge system configuration unit (U-Box) uncore PMU. This PMU model only exists on Sandy Bridge model 45. There is only one U-Box PMU per processor socket. .SH MODIFIERS The following modifiers are supported on Intel Sandy Bridge U-Box uncore PMU: .TP .B i Invert the meaning of the event. The counter will now count HA cycles in which the event is \fBnot\fR occurring. This is a boolean modifier .TP .B e Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one. This is a boolean modifier. .TP .B t Set the threshold value. When set to a non-zero value, the counter counts the number of HA cycles in which the number of occurrences of the event is greater or equal to the threshold. This is an integer modifier with values in the range [0:15]. .TP .B oi Invert the meaning of the occupancy event POWER_STATE_OCCUPANCY. The counter will now count PCU cycles in which the event is \fBnot\fR occurring. This is a boolean modifier .TP .B oe Enable edge detection for the occupancy event POWER_STATE_OCCUPANCY. The event now counts only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one. This is a boolean modifier. .TP .B ff Enable frequency band filtering. This modifier applies only to the UNC_P_FREQ_BANDx_CYCLES events, where x is [0-3]. The modifiers expects an integer in the range [0-255]. The value is interpreted as a frequency value to be multiplied by 100Mhz. Thus if the value is 32, then all cycles where the processor is running at 3.2GHz and more are counted. .SH Frequency band filtering There are 3 events which support frequency band filtering, namely, UNC_P_FREQ_BAND0_CYCLES, UNC_P_FREQ_BAND1_CYCLES, UNC_P_FREQ_BAND2_CYCLES, UNC_P_FREQ_BAND3_CYCLES. The frequency filter (available via the ff modifier) is stored into a PMU shared register which hold all 4 possible frequency bands, one per event. However, the library generate the encoding for each event individually because it processes events one at a time. The caller or the underlying kernel interface may have to merge the band filter settings to program the filter register properly. .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/pfm_get_event_next.30000664000175000017500000000446713223402656020363 0ustar eranianeranian.TH LIBPFM 3 "September, 2009" "" "Linux Programmer's Manual" .SH NAME pfm_get_event_next \- iterate over events .SH SYNOPSIS .nf .B #include .sp .BI "int pfm_get_event_next(int "idx ");" .sp .SH DESCRIPTION Events are uniquely identified with opaque integer identifiers. There is no guaranteed order within identifiers. Thus, to list all the events, it is necessary to use iterators. Events are grouped in tables within the library. A table usually corresponds to a PMU model or family. The library contains support for multiple PMU models, thus it has multiple tables. Based on the host hardware and software environments, tables get activated when the library is initialized via \fBpfm_initialize()\fR. Events from activated tables are called active events. Events from non-activated tables are called supported events. Event identifiers are usually retrieved via \fBpfm_find_event()\fR or when encoding events. To iterate over a list of events for a given PMU model, all that is needed is an initial identifier for the PMU. The first event identifier is usually obtained via \fBpfm_get_pmu_info()\fR. The \fBpfm_get_event_next()\fR function returns the identifier of next supported event after the one passed in \fBidx\fR. This iterator stops when the last event for the PMU is passed as argument, in which case the function returns \-1. .sp .nf void list_pmu_events(pfm_pmu_t pmu) { struct pfm_event_info info; struct pfm_pmu_info pinfo; int i, ret; memset(&info, 0, sizeof(info)); memset(&pinfo, 0, sizeof(pinfo)); info.size = sizeof(info); pinfo.size = sizeof(pinfo); ret = pfm_get_pmu_info(pmu, &pinfo); if (ret != PFM_SUCCESS) errx(1, "cannot get pmu info"); for (i = pinfo.first_event; i != \-1; i = pfm_get_event_next(i)) { ret = pfm_get_event_info(i, &info); if (ret != PFM_SUCCESS) errx(1, "cannot get event info"); printf("%s Event: %s::%s\\n", pinfo.present ? "Active" : "Supported", pinfo.name, info.name); } } .fi .SH RETURN The function returns the identifier of the next supported event. It returns \-1 when the argument is already the last event for the PMU. .SH ERRORS No error code, besides \-1, is returned by this function. .SH SEE ALSO pfm_find_event(3) .SH AUTHOR Stephane Eranian .PP libpfm-4.9.0/docs/man3/libpfm_intel_nhm_unc.30000664000175000017500000000243513223402656020647 0ustar eranianeranian.TH LIBPFM 3 "September, 2009" "" "Linux Programmer's Manual" .SH NAME libpfm_intel_nhm_unc \- support for Intel Nehalem uncore PMU .SH SYNOPSIS .nf .B #include .sp .B PMU name: nhm_unc .B PMU desc: Intel Nehalem uncore .sp .SH DESCRIPTION The library supports the Nehalem uncore PMU as implemented by processors such as Intel Core i7, and Intel Core i5. The PMU is located at the socket-level and is therefore shared between the various cores. By construction it can only measure at all privilege levels. .SH MODIFIERS The following modifiers are supported on Intel Nehalem processors: .TP .B i Invert the meaning of the event. The counter will now count cycles in which the event is \fBnot\fR occurring. This is a boolean modifier .TP .B e Enable edge detection, i.e., count only when there is a state transition. This is a boolean modifier. .TP .B c Set the counter mask value. The mask acts as a threshold. The counter will count the number of cycles in which the number of occurrences of the event is greater or equal to the threshold. This is an integer modifier with values in the range [0:255]. .TP .B o Causes the queue occupancy counter associated with the event to be cleared (zeroed). This is a boolean modifier. .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/libpfm_intel_ivbep_unc_r2pcie.30000664000175000017500000000212213223402656022427 0ustar eranianeranian.TH LIBPFM 3 "February, 2014" "" "Linux Programmer's Manual" .SH NAME libpfm_intel_ivbep_unc_r2pcie - support for Intel Ivy Bridge-EP R2 PCIe uncore PMU .SH SYNOPSIS .nf .B #include .sp .B PMU name: ivbep_unc_r2pcie .B PMU desc: Intel Ivy Bridge-EP R2 PCIe uncore PMU .sp .SH DESCRIPTION The library supports the Intel Ivy Bridge R2 PCIe uncore PMU. This PMU model only exists on Ivy Bridge model 62. .SH MODIFIERS The following modifiers are supported on Intel Ivy Bridge R2PCIe uncore PMU: .TP .B e Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one. This is a boolean modifier. .TP .B t Set the threshold value. When set to a non-zero value, the counter counts the number of R2PCIe cycles in which the number of occurrences of the event is greater or equal to the threshold. This is an integer modifier with values in the range [0:15]. .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/libpfm_arm_ac57.30000664000175000017500000000150413223402656017417 0ustar eranianeranian.TH LIBPFM 3 "May, 2014" "" "Linux Programmer's Manual" .SH NAME libpfm_arm_ac57 - support for Arm Cortex A57 PMU .SH SYNOPSIS .nf .B #include .sp .B PMU name: arm_ac57 .B PMU desc: ARM Cortex A57 .sp .SH DESCRIPTION The library supports the ARM Cortex A57 core PMU. This PMU supports 6 counters and privilege levels filtering. It can operate in both 32 and 64 bit modes. .SH MODIFIERS The following modifiers are supported on ARM Cortex A57: .TP .B u Measure at the user level. This corresponds to \fBPFM_PLM3\fR. This is a boolean modifier. .TP .B k Measure at the kernel level. This corresponds to \fBPFM_PLM0\fR. This is a boolean modifier. .TP .B hv Measure at the hypervisor level. This corresponds to \fBPFM_PLMH\fR. This is a boolean modifier. .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/pfm_get_version.30000664000175000017500000000150013223402656017652 0ustar eranianeranian.TH LIBPFM 3 "September, 2009" "" "Linux Programmer's Manual" .SH NAME pfm_get_version \- get library version .SH SYNOPSIS .nf .B #include .sp .BI "int pfm_get_version(void)"; .sp .SH DESCRIPTION This function can be called at any time to get the revision level of the library. It is not necessary to have invoked \fBpfm_initialize()\fR prior to calling this function. The revision number is composed of two fields: a major number and a minor number. Both can be extracted using macros provided in the header file: .TP .B PFMLIB_MAJ_VERSION(v) returns the major number encoded in v. .TP .B PFMLIB_MIN_VERSION(v) returns the minor number encoded in v. .SH RETURN The function is always successful, i.e., it always returns the 32-bit version number. .SH ERRORS .SH AUTHOR Stephane Eranian .PP libpfm-4.9.0/docs/man3/libpfm_intel_snbep_unc_imc.30000664000175000017500000000250113223402656022016 0ustar eranianeranian.TH LIBPFM 3 "August, 2012" "" "Linux Programmer's Manual" .SH NAME libpfm_intel_snbep_unc_imc - support for Intel Sandy Bridge-EP Integrated Memory Controller (IMC) uncore PMU .SH SYNOPSIS .nf .B #include .sp .B PMU name: snbep_unc_imc[0-3] .B PMU desc: Intel Sandy Bridge-EP IMC uncore PMU .sp .SH DESCRIPTION The library supports the Intel Sandy Bridge Integrated Memory Controller (IMC) uncore PMU. This PMU model only exists on Sandy Bridge model 45. There are four IMC PMUs per socket. .SH MODIFIERS The following modifiers are supported on Intel Sandy Bridge C-Box uncore PMU: .TP .B i Invert the meaning of the event. The counter will now count IMC cycles in which the event is \fBnot\fR occurring. This is a boolean modifier .TP .B e Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one. This is a boolean modifier. .TP .B t Set the threshold value. When set to a non-zero value, the counter counts the number of IMC cycles in which the number of occurrences of the event is greater or equal to the threshold. This is an integer modifier with values in the range [0:255]. .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/libpfm_intel_hswep_unc_ubo.30000664000175000017500000000271113223402656022055 0ustar eranianeranian.TH LIBPFM 3 "May, 2015" "" "Linux Programmer's Manual" .SH NAME libpfm_intel_hswep_unc_ubo - support for Intel Haswell-EP U-Box uncore PMU .SH SYNOPSIS .nf .B #include .sp .B PMU name: hswep_unc_ubo .B PMU desc: Intel Haswell-EP U-Box uncore PMU .sp .SH DESCRIPTION The library supports the Intel Haswell system configuration unit (U-Box) uncore PMU. This PMU model only exists on Haswell model 63. .SH MODIFIERS The following modifiers are supported on Intel Haswell U-Box uncore PMU: .TP .B e Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one. This is a boolean modifier. .TP .B t Set the threshold value. When set to a non-zero value, the counter counts the number of HA cycles in which the number of occurrences of the event is greater or equal to the threshold. This is an integer modifier with values in the range [0:15]. .TP .B i Invert the meaning of the threshold or edge filter. If set, the event counts when strictly less than N occurrences occur per cycle if threshold is set to N. When invert is set, then threshold must be set to non-zero value. If set, the event counts when the event transitions from occurring to not occurring (falling edge) when edge detection is set. This is a boolean modifier .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/libpfm_intel_core.30000664000175000017500000000261113223402656020144 0ustar eranianeranian.TH LIBPFM 3 "September, 2009" "" "Linux Programmer's Manual" .SH NAME libpfm_intel_core - support for Intel Core-based processors .SH SYNOPSIS .nf .B #include .sp .B PMU name: core .B PMU desc: Intel Core .sp .SH DESCRIPTION The library supports all Intel Core-based processors that includes models 15, 23, 29. .SH MODIFIERS The following modifiers are supported on Intel Core processors: .TP .B u Measure at user level which includes privilege levels 1, 2, 3. This corresponds to \fBPFM_PLM3\fR. This is a boolean modifier. .TP .B k Measure at kernel level which includes privilege level 0. This corresponds to \fBPFM_PLM0\fR. This is a boolean modifier. .TP .B i Invert the meaning of the event. The counter will now count cycles in which the event is \fBnot\fR occurring. This is a boolean modifier .TP .B e Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a counter mask modifier (m) with a value greater or equal to one. This is a boolean modifier. .TP .B c Set the counter mask value. The mask acts as a threshold. The counter will count the number of cycles in which the number of occurrences of the event is greater or equal to the threshold. This is an integer modifier with values in the range [0:255]. .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/libpfm_intel_ivb.30000664000175000017500000000727713223402656020011 0ustar eranianeranian.TH LIBPFM 3 "August, 2012" "" "Linux Programmer's Manual" .SH NAME libpfm_intel_ivb - support for Intel Ivy Bridge core PMU .SH SYNOPSIS .nf .B #include .sp .B PMU name: ivb .B PMU desc: Intel Ivy Bridge .B PMU name: ivb_ep .B PMU desc: Intel Ivy Bridge EP .sp .SH DESCRIPTION The library supports the Intel Ivy Bridge core PMU. It should be noted that this PMU model only covers each core's PMU and not the socket level PMU. On Ivy Bridge, the number of generic counters depends on the Hyperthreading (HT) mode. When HT is on, then only 4 generic counters are available. When HT is off, then 8 generic counters are available. The \fBpfm_get_pmu_info()\fR function returns the maximum number of generic counters in \fBnum_cntrs\fr. .SH MODIFIERS The following modifiers are supported on Intel Ivy Bridge processors: .TP .B u Measure at user level which includes privilege levels 1, 2, 3. This corresponds to \fBPFM_PLM3\fR. This is a boolean modifier. .TP .B k Measure at kernel level which includes privilege level 0. This corresponds to \fBPFM_PLM0\fR. This is a boolean modifier. .TP .B i Invert the meaning of the event. The counter will now count cycles in which the event is \fBnot\fR occurring. This is a boolean modifier .TP .B e Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a counter mask modifier (m) with a value greater or equal to one. This is a boolean modifier. .TP .B c Set the counter mask value. The mask acts as a threshold. The counter will count the number of cycles in which the number of occurrences of the event is greater or equal to the threshold. This is an integer modifier with values in the range [0:255]. .TP .B t Measure on both threads at the same time assuming hyper-threading is enabled. This is a boolean modifier. .TP .B ldlat Pass a latency threshold to the MEM_TRANS_RETIRED:LATENCY_ABOVE_THRESHOLD event. This is an integer attribute that must be in the range [3:65535]. It is required for this event. Note that the event must be used with precise sampling (PEBS). .SH OFFCORE_RESPONSE events Intel Ivy Bridge provides two offcore_response events. They are called OFFCORE_RESPONSE_0 and OFFCORE_RESPONSE_1. Those events need special treatment in the performance monitoring infrastructure because each event uses an extra register to store some settings. Thus, in case multiple offcore_response events are monitored simultaneously, the kernel needs to manage the sharing of that extra register. The offcore_response events are exposed as a normal events by the library. The extra settings are exposed as regular umasks. The library takes care of encoding the events according to the underlying kernel interface. On Intel Ivy Bridge, the umasks are divided into three categories: request, supplier and snoop. The user must provide at least one umask for each category. The categories are shown in the umask descriptions. There is also the special response umask called \fBANY_RESPONSE\fR. When this umask is used then it overrides any supplier and snoop umasks. In other words, users can specify either \fBANY_RESPONSE\fR \fBOR\fR any combinations of supplier + snoops. In case no supplier or snoop is specified, the library defaults to using \fBANY_RESPONSE\fR. For instance, the following are valid event selections: .TP .B OFFCORE_RESPONSE_0:DMND_DATA_RD:ANY_RESPONSE .TP .B OFFCORE_RESPONSE_0:ANY_REQUEST .TP .B OFFCORE_RESPONSE_0:ANY_RFO:LLC_HITM:SNOOP_ANY .P But the following are illegal: .TP .B OFFCORE_RESPONSE_0:ANY_RFO:LLC_HITM:ANY_RESPONSE .TP .B OFFCORE_RESPONSE_0:ANY_RFO:LLC_HITM:SNOOP_ANY:ANY_RESPONSE .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/libpfm_intel_snbep_unc_qpi.30000664000175000017500000000243313223402656022043 0ustar eranianeranian.TH LIBPFM 3 "August, 2012" "" "Linux Programmer's Manual" .SH NAME libpfm_intel_snbep_unc_qpi - support for Intel Sandy Bridge-EP QPI uncore PMU .SH SYNOPSIS .nf .B #include .sp .B PMU name: snbep_unc_qpi0, snbep_unc_qpi1 .B PMU desc: Intel Sandy Bridge-EP QPI uncore PMU .sp .SH DESCRIPTION The library supports the Intel Sandy Bridge Power QPI uncore PMU. This PMU model only exists on Sandy Bridge model 45. There are two QPI PMUs per processor socket. .SH MODIFIERS The following modifiers are supported on Intel Sandy Bridge QPI uncore PMU: .TP .B i Invert the meaning of the event. The counter will now count QPI cycles in which the event is \fBnot\fR occurring. This is a boolean modifier .TP .B e Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one. This is a boolean modifier. .TP .B t Set the threshold value. When set to a non-zero value, the counter counts the number of QPI cycles in which the number of occurrences of the event is greater or equal to the threshold. This is an integer modifier with values in the range [0:255]. .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/libpfm_intel_x86_arch.30000664000175000017500000000336613223402656020646 0ustar eranianeranian.TH LIBPFM 3 "September, 2009" "" "Linux Programmer's Manual" .SH NAME libpfm_intel_x86_arch - support for Intel X86 architectural PMU .SH SYNOPSIS .nf .B #include .sp .B PMU name: ix86arch .B PMU desc: Intel X86 architectural PMU .sp .SH DESCRIPTION The library supports \fbany\fR processor implementing the Intel architectural PMU. This is a minimal PMU with a variable number of counters but predefined set of events. It is implemented in all recent processors starting with Intel Core Duo/Core Solo. It acts as a default PMU support in case the library is run on a very recent processor for which the specific support has not yet been implemented. .SH MODIFIERS The following modifiers are supported on Intel architectural PMU: .TP .B u Measure at user level which includes privilege levels 1, 2, 3. This corresponds to \fBPFM_PLM3\fR. This is a boolean modifier. .TP .B k Measure at kernel level which includes privilege level 0. This corresponds to \fBPFM_PLM0\fR. This is a boolean modifier. .TP .B i Invert the meaning of the event. The counter will now count cycles in which the event is \fBnot\fR occurring. This is a boolean modifier .TP .B e Enable edge detection, i.e., count only when there is a state transition. This is a boolean modifier. .TP .B c Set the counter mask value. The mask acts as a threshold. The counter will count the number of cycles in which the number of occurrences of the event is greater or equal to the threshold. This is an integer modifier with values in the range [0:255]. .TP .B t Measure on both threads at the same time assuming hyper-threading is enabled. This modifier requires at least version 3 of the architectural PMU. This is a boolean modifier. .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/pfm_terminate.30000664000175000017500000000104113223402656017316 0ustar eranianeranian.TH LIBPFM 3 "September, 2009" "" "Linux Programmer's Manual" .SH NAME pfm_terminate \- free resources used by library .SH SYNOPSIS .nf .B #include .sp .BI "int pfm_terminate(void);" .sp .SH DESCRIPTION This is the last function that a program \fBmust\fR call to free all the resources allocated by the library, e.g., memory. The function is not reentrant, caller must ensure only one thread at a time is executing it. .SH RETURN There is no return value to this function .SH AUTHOR Stephane Eranian .PP libpfm-4.9.0/docs/man3/libpfm_intel_slm.30000664000175000017500000000571613223402656020020 0ustar eranianeranian.TH LIBPFM 3 "November, 2013" "" "Linux Programmer's Manual" .SH NAME libpfm_intel_slm - support for Intel Silvermont core PMU .SH SYNOPSIS .nf .B #include .sp .B PMU name: slm .B PMU desc: Intel Silvermont .sp .SH DESCRIPTION The library supports the Intel Silvermont core PMU. .SH MODIFIERS The following modifiers are supported on Intel Silvermont processors: .TP .B u Measure at user level which includes privilege levels 1, 2, 3. This corresponds to \fBPFM_PLM3\fR. This is a boolean modifier. .TP .B k Measure at kernel level which includes privilege level 0. This corresponds to \fBPFM_PLM0\fR. This is a boolean modifier. .TP .B i Invert the meaning of the event. The counter will now count cycles in which the event is \fBnot\fR occurring. This is a boolean modifier .TP .B e Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a counter mask modifier (m) with a value greater or equal to one. This is a boolean modifier. .TP .B c Set the counter mask value. The mask acts as a threshold. The counter will count the number of cycles in which the number of occurrences of the event is greater or equal to the threshold. This is an integer modifier with values in the range [0:255]. .SH OFFCORE_RESPONSE events Intel Silvermont provides two offcore_response events: \fBOFFCORE_RESPONSE_0\fR and \fBOFFCORE_RESPONSE_1\fR. Those events need special treatment in the performance monitoring infrastructure because each event uses an extra register to store some settings. Thus, in case multiple offcore_response events are monitored simultaneously, the kernel needs to manage the sharing of that extra register. The offcore_response events are exposed as a normal event by the library. The extra settings are exposed as regular umasks. The library takes care of encoding the events according to the underlying kernel interface. On Intel Silvermont, the umasks are divided into three categories: request, supplier and snoop. The user must provide at least one umask for each category. The categories are shown in the umask descriptions. The library provides a default umask per category if not provided by the user. There is also the special response umask called \fBANY_RESPONSE\fR. When this umask is used then it overrides any supplier and snoop umasks. In other words, users can specify either \fBANY_RESPONSE\fR \fBOR\fR any combinations of supplier + snoops. In case no supplier or snoop is specified, the library defaults to using \fBANY_RESPONSE\fR. For instance, the following are valid event selections: .TP .B OFFCORE_RESPONSE_0:DMND_DATA_RD:ANY_RESPONSE .TP .B OFFCORE_RESPONSE_0:ANY_REQUEST .TP .B OFFCORE_RESPONSE_0:ANY_RFO:LLC_HITM:SNOOP_ANY .P But the following are illegal: .TP .B OFFCORE_RESPONSE_0:ANY_RFO:NON_DRAM:ANY_RESPONSE .TP .B OFFCORE_RESPONSE_0:ANY_RFO:L2_HIT:SNOOP_ANY:ANY_RESPONSE .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/libpfm_intel_hswep_unc_imc.30000664000175000017500000000275013223402656022043 0ustar eranianeranian.TH LIBPFM 3 "May, 2015" "" "Linux Programmer's Manual" .SH NAME libpfm_intel_hswep_unc_imc - support for Intel Haswell-EP Integrated Memory Controller (IMC) uncore PMU .SH SYNOPSIS .nf .B #include .sp .B PMU name: hswep_unc_imc[0-7] .B PMU desc: Intel Haswell-EP IMC uncore PMU .sp .SH DESCRIPTION The library supports the Intel Haswell Integrated Memory Controller (IMC) uncore PMU. This PMU model only exists on Haswell model 63. .SH MODIFIERS The following modifiers are supported on Intel Haswell C-Box uncore PMU: .TP .B e Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one. This is a boolean modifier. .TP .B t Set the threshold value. When set to a non-zero value, the counter counts the number of IMC cycles in which the number of occurrences of the event is greater or equal to the threshold. This is an integer modifier with values in the range [0:255]. .B i Invert the meaning of the threshold or edge filter. If set, the event counts when strictly less than N occurrences occur per cycle if threshold is set to N. When invert is set, then threshold must be set to non-zero value. If set, the event counts when the event transitions from occurring to not occurring (falling edge) when edge detection is set. This is a boolean modifier .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/libpfm_intel_ivbep_unc_qpi.30000664000175000017500000000212013223402656022032 0ustar eranianeranian.TH LIBPFM 3 "February, 2014" "" "Linux Programmer's Manual" .SH NAME libpfm_intel_ivbep_unc_qpi - support for Intel Ivy Bridge-EP QPI uncore PMU .SH SYNOPSIS .nf .B #include .sp .B PMU name: ivbep_unc_qpi0, ivbep_unc_qpi1 .B PMU desc: Intel Ivy Bridge-EP QPI uncore PMU .sp .SH DESCRIPTION The library supports the Intel Ivy Bridge Power QPI uncore PMU. This PMU model only exists on Ivy Bridge model 62. .SH MODIFIERS The following modifiers are supported on Intel Ivy Bridge QPI uncore PMU: .TP .B e Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one. This is a boolean modifier. .TP .B t Set the threshold value. When set to a non-zero value, the counter counts the number of QPI cycles in which the number of occurrences of the event is greater or equal to the threshold. This is an integer modifier with values in the range [0:255]. .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/libpfm_intel_snbep_unc_r2pcie.30000664000175000017500000000244713223402656022443 0ustar eranianeranian.TH LIBPFM 3 "August, 2012" "" "Linux Programmer's Manual" .SH NAME libpfm_intel_snbep_unc_r2pcie - support for Intel Sandy Bridge-EP R2 PCIe uncore PMU .SH SYNOPSIS .nf .B #include .sp .B PMU name: snbep_unc_r2pcie .B PMU desc: Intel Sandy Bridge-EP R2 PCIe uncore PMU .sp .SH DESCRIPTION The library supports the Intel Sandy Bridge R2 PCIe uncore PMU. This PMU model only exists on Sandy Bridge model 45. There is only one R2PCIe PMU per processor socket. .SH MODIFIERS The following modifiers are supported on Intel Sandy Bridge R2PCIe uncore PMU: .TP .B i Invert the meaning of the event. The counter will now count R2 PCIe cycles in which the event is \fBnot\fR occurring. This is a boolean modifier .TP .B e Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one. This is a boolean modifier. .TP .B t Set the threshold value. When set to a non-zero value, the counter counts the number of R2PCIe cycles in which the number of occurrences of the event is greater or equal to the threshold. This is an integer modifier with values in the range [0:15]. .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/libpfm_intel_ivb_unc.30000664000175000017500000000360113223402656020641 0ustar eranianeranian.TH LIBPFM 3 "June, 2013" "" "Linux Programmer's Manual" .SH NAME libpfm_intel_ivb_unc - support for Intel Ivy Bridge uncore PMU .SH SYNOPSIS .nf .B #include .sp .B PMU name: ivb_unc_cbo0, ivb_unc_cbo1, ivb_unc_cbo2, ivb_unc_cbo3 .B PMU desc: Intel Ivy Bridge C-box uncore .sp .SH DESCRIPTION The library supports the Intel Ivy Bridge client part (model 58) uncore PMU. The support is currently limited to the Coherency Box, so called C-Box for up to 4 physical cores. Each physical core has an associated C-Box which it uses to communicate with the L3 cache. The C-boxes all support the same set of events. However, Core 0 C-box (snb_unc_cbo0) supports an additional uncore clock ticks event: \fBUNC_CLOCKTICKS\fR. .SH MODIFIERS The following modifiers are supported on Intel Ivy Bridge C-Box uncore PMU: .TP .B i Invert the meaning of the event. The counter will now count cycles in which the event is \fBnot\fR occurring. This is a boolean modifier .TP .B e Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a counter mask modifier (m) with a value greater or equal to one. This is a boolean modifier. .TP .B c Set the counter mask value. The mask acts as a threshold. The counter will count the number of cycles in which the number of occurrences of the event is greater or equal to the threshold. This is an integer modifier with values in the range [0:255]. .P Both the \fBUNC_CBO_CACHE_LOOKUP\fR and \fBUNC_CBO_XSNP_RESPONSE\fR requires two umasks to be valid. For \fBUNC_CBO_CACHE_LOOKUP\fR the first umask must be one of the MESI state umasks, the second has to be one of the filters. For \fBUNC_CBO_XSNP_RESPONSE\fR the first umask must be one of the snoop types, the second has to be one of the filters. .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/libpfm_intel_bdx_unc_ha.30000664000175000017500000000276313223402656021316 0ustar eranianeranian.TH LIBPFM 3 "June, 2017" "" "Linux Programmer's Manual" .SH NAME libpfm_intel_bdx_unc_ha - support for Intel Broadwell Server Home Agent (HA) uncore PMU .SH SYNOPSIS .nf .B #include .sp .B PMU name: bdx_unc_ha0, bdx_unc_ha1 .B PMU desc: Intel Broadwell Server HA uncore PMU .sp .SH DESCRIPTION The library supports the Intel Broadwell Server Home Agent (HA) uncore PMU. This PMU model only exists on various Broadwell models (79, 86). .SH MODIFIERS The following modifiers are supported on Intel Broadwell server HA uncore PMU: .TP .B e Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one. This is a boolean modifier. .TP .B t Set the threshold value. When set to a non-zero value, the counter counts the number of HA cycles in which the number of occurrences of the event is greater or equal to the threshold. This is an integer modifier with values in the range [0:255]. .TP .B i Invert the meaning of the threshold or edge filter. If set, the event counts when strictly less than N occurrences occur per cycle if threshold is set to N. When invert is set, then threshold must be set to non-zero value. If set, the event counts when the event transitions from occurring to not occurring (falling edge) when edge detection is set. This is a boolean modifier .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/libpfm_intel_snbep_unc_pcu.30000664000175000017500000000434613223402656022046 0ustar eranianeranian.TH LIBPFM 3 "August, 2012" "" "Linux Programmer's Manual" .SH NAME libpfm_intel_snbep_unc_pcu - support for Intel Sandy Bridge-EP Power Controller Unit (PCU) uncore PMU .SH SYNOPSIS .nf .B #include .sp .B PMU name: snbep_unc_pcu .B PMU desc: Intel Sandy Bridge-EP PCU uncore PMU .sp .SH DESCRIPTION The library supports the Intel Sandy Bridge Power Controller Unit uncore PMU. This PMU model only exists on Sandy Bridge model 45. There is only one PCU PMU per processor socket. .SH MODIFIERS The following modifiers are supported on Intel Sandy Bridge C-Box uncore PMU: .TP .B i Invert the meaning of the event. The counter will now count HA cycles in which the event is \fBnot\fR occurring. This is a boolean modifier .TP .B e Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one. This is a boolean modifier. .TP .B t Set the threshold value. When set to a non-zero value, the counter counts the number of HA cycles in which the number of occurrences of the event is greater or equal to the threshold. This is an integer modifier with values in the range [0:15]. .TP .B ff Enable frequency band filtering. This modifier applies only to the UNC_P_FREQ_BANDx_CYCLES events, where x is [0-3]. The modifiers expects an integer in the range [0-255]. The value is interpreted as a frequency value to be multiplied by 100Mhz. Thus if the value is 32, then all cycles where the processor is running at 3.2GHz and more are counted. .SH Frequency band filtering There are 3 events which support frequency band filtering, namely, UNC_P_FREQ_BAND0_CYCLES, UNC_P_FREQ_BAND1_CYCLES, UNC_P_FREQ_BAND2_CYCLES, UNC_P_FREQ_BAND3_CYCLES. The frequency filter (available via the ff modifier) is stored into a PMU shared register which hold all 4 possible frequency bands, one per event. However, the library generate the encoding for each event individually because it processes events one at a time. The caller or the underlying kernel interface may have to merge the band filter settings to program the filter register properly. .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/libpfm_arm_qcom_krait.30000664000175000017500000000143013223402656021007 0ustar eranianeranian.TH LIBPFM 3 "January, 2014" "" "Linux Programmer's Manual" .SH NAME libpfm_arm_ac15 - support for Qualcomm Krait PMU .SH SYNOPSIS .nf .B #include .sp .B PMU name: qcom_krait .B PMU desc: Qualcomm Krait .sp .SH DESCRIPTION The library supports the Qualcomm Krait core PMU. This PMU supports 5 counters and privilege levels filtering. .SH MODIFIERS The following modifiers are supported on this PMU: .TP .B u Measure at the user level. This corresponds to \fBPFM_PLM3\fR. This is a boolean modifier. .TP .B k Measure at the kernel level. This corresponds to \fBPFM_PLM0\fR. This is a boolean modifier. .TP .B hv Measure at the hypervisor level. This corresponds to \fBPFM_PLMH\fR. This is a boolean modifier. .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/libpfm_arm_ac15.30000664000175000017500000000143313223402656017412 0ustar eranianeranian.TH LIBPFM 3 "August, 2012" "" "Linux Programmer's Manual" .SH NAME libpfm_arm_ac15 - support for Arm Cortex A15 PMU .SH SYNOPSIS .nf .B #include .sp .B PMU name: arm_ac15 .B PMU desc: ARM Cortex A15 .sp .SH DESCRIPTION The library supports the ARM Cortex A15 core PMU. This PMU supports 6 counters and privilege levels filtering. .SH MODIFIERS The following modifiers are supported on ARM Cortex A15: .TP .B u Measure at the user level. This corresponds to \fBPFM_PLM3\fR. This is a boolean modifier. .TP .B k Measure at the kernel level. This corresponds to \fBPFM_PLM0\fR. This is a boolean modifier. .TP .B hv Measure at the hypervisor level. This corresponds to \fBPFM_PLMH\fR. This is a boolean modifier. .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/libpfm_intel_snb.30000664000175000017500000000747413223402656020012 0ustar eranianeranian.TH LIBPFM 3 "January, 2011" "" "Linux Programmer's Manual" .SH NAME libpfm_intel_snb - support for Intel Sandy Bridge core PMU .SH SYNOPSIS .nf .B #include .sp .B PMU name: snb .B PMU desc: Intel Sandy Bridge .B PMU name: snb_ep .B PMU desc: Intel Sandy Bridge EP .sp .SH DESCRIPTION The library supports the Intel Sandy Bridge core PMU. It should be noted that this PMU model only covers each core's PMU and not the socket level PMU. For that refer to the Sandy Bridge uncore PMU support. On Sandy Bridge, the number of generic counters depends on the Hyperthreading (HT) mode. When HT is on, then only 4 generic counters are available. When HT is off, then 8 generic counters are available. The \fBpfm_get_pmu_info()\fR function returns the maximum number of generic counters in \fBnum_cntrs\fr. .SH MODIFIERS The following modifiers are supported on Intel Sandy Bridge processors: .TP .B u Measure at user level which includes privilege levels 1, 2, 3. This corresponds to \fBPFM_PLM3\fR. This is a boolean modifier. .TP .B k Measure at kernel level which includes privilege level 0. This corresponds to \fBPFM_PLM0\fR. This is a boolean modifier. .TP .B i Invert the meaning of the event. The counter will now count cycles in which the event is \fBnot\fR occurring. This is a boolean modifier .TP .B e Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a counter mask modifier (m) with a value greater or equal to one. This is a boolean modifier. .TP .B c Set the counter mask value. The mask acts as a threshold. The counter will count the number of cycles in which the number of occurrences of the event is greater or equal to the threshold. This is an integer modifier with values in the range [0:255]. .TP .B t Measure on both threads at the same time assuming hyper-threading is enabled. This is a boolean modifier. .TP .B ldlat Pass a latency threshold to the MEM_TRANS_RETIRED:LATENCY_ABOVE_THRESHOLD event. This is an integer attribute that must be in the range [3:65535]. It is required for this event. Note that the event must be used with precise sampling (PEBS). .SH OFFCORE_RESPONSE events Intel Sandy Bridge provides two offcore_response events, like Intel Westmere. They are called OFFCORE_RESPONSE_0 and OFFCORE_RESPONSE_1. Those events need special treatment in the performance monitoring infrastructure because each event uses an extra register to store some settings. Thus, in case multiple offcore_response events are monitored simultaneously, the kernel needs to manage the sharing of that extra register. The offcore_response events are exposed as a normal events by the library. The extra settings are exposed as regular umasks. The library takes care of encoding the events according to the underlying kernel interface. On Intel Sandy Bridge, the umasks are divided into three categories: request, supplier and snoop. The user must provide at least one umask for each category. The categories are shown in the umask descriptions. There is also the special response umask called \fBANY_RESPONSE\fR. When this umask is used then it overrides any supplier and snoop umasks. In other words, users can specify either \fBANY_RESPONSE\fR \fBOR\fR any combinations of supplier + snoops. In case no supplier or snoop is specified, the library defaults to using \fBANY_RESPONSE\fR. For instance, the following are valid event selections: .TP .B OFFCORE_RESPONSE_0:DMND_DATA_RD:ANY_RESPONSE .TP .B OFFCORE_RESPONSE_0:ANY_REQUEST .TP .B OFFCORE_RESPONSE_0:ANY_RFO:LLC_HITM:SNOOP_ANY .P But the following are illegal: .TP .B OFFCORE_RESPONSE_0:ANY_RFO:LLC_HITM:ANY_RESPONSE .TP .B OFFCORE_RESPONSE_0:ANY_RFO:LLC_HITM:SNOOP_ANY:ANY_RESPONSE .SH SEE ALSO libpfm_snb_unc(3) .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/libpfm_intel_knl.30000664000175000017500000001152013223402656017777 0ustar eranianeranian.TH LIBPFM 3 "July, 2016" "" "Linux Programmer's Manual" .SH NAME libpfm_intel_knl - support for Intel Kinghts Landing core PMU .SH SYNOPSIS .nf .B #include .sp .B PMU name: knl .B PMU desc: Intel Kinghts Landing .sp .SH DESCRIPTION The library supports the Intel Kinghts Landing core PMU. It should be noted that this PMU model only covers each core's PMU and not the socket level PMU. On Knights Landing, the number of generic counters is 4. There is 4-way HyperThreading support. The \fBpfm_get_pmu_info()\fR function returns the maximum number of generic counters in \fBnum_cntrs\fr. .SH MODIFIERS The following modifiers are supported on Intel Kinghts Landing processors: .TP .B u Measure at user level which includes privilege levels 1, 2, 3. This corresponds to \fBPFM_PLM3\fR. This is a boolean modifier. .TP .B k Measure at kernel level which includes privilege level 0. This corresponds to \fBPFM_PLM0\fR. This is a boolean modifier. .TP .B i Invert the meaning of the event. The counter will now count cycles in which the event is \fBnot\fR occurring. This is a boolean modifier .TP .B e Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a counter mask modifier (m) with a value greater or equal to one. This is a boolean modifier. .TP .B c Set the counter mask value. The mask acts as a threshold. The counter will count the number of cycles in which the number of occurrences of the event is greater or equal to the threshold. This is an integer modifier with values in the range [0:255]. .TP .B t Measure on any of the 4 hyper-threads at the same time assuming hyper-threading is enabled. This is a boolean modifier. This modifier is only available on fixed counters (unhalted_reference_cycles, instructions_retired, unhalted_core_cycles). Depending on the underlying kernel interface, the event may be programmed on a fixed counter or a generic counter, except for unhalted_reference_cycles, in which case, this modifier may be ignored or rejected. .SH OFFCORE_RESPONSE events Intel Knights Landing provides two offcore_response events. They are called OFFCORE_RESPONSE_0 and OFFCORE_RESPONSE_1. Those events need special treatment in the performance monitoring infrastructure because each event uses an extra register to store some settings. Thus, in case multiple offcore_response events are monitored simultaneously, the kernel needs to manage the sharing of that extra register. The offcore_response events are exposed as normal events by the library. The extra settings are exposed as regular umasks. The library takes care of encoding the events according to the underlying kernel interface. On Intel Knights Landing, the umasks are divided into 4 categories: request, supplier and snoop and average latency. Offcore_response event has two modes of operations: normal and average latency. In the first mode, the two offcore_respnse events operate independently of each other. The user must provide at least one umask for each of the first 3 categories: request, supplier, snoop. In the second mode, the two offcore_response events are combined to compute an average latency per request type. For the normal mode, there is a special supplier (response) umask called \fBANY_RESPONSE\fR. When this umask is used then it overrides any supplier and snoop umasks. In other words, users can specify either \fBANY_RESPONSE\fR \fBOR\fR any combinations of supplier + snoops. In case no supplier or snoop is specified, the library defaults to using \fBANY_RESPONSE\fR. For instance, the following are valid event selections: .TP .B OFFCORE_RESPONSE_0:DMND_DATA_RD:ANY_RESPONSE .TP .B OFFCORE_RESPONSE_0:ANY_REQUEST .TP .B OFFCORE_RESPONSE_0:ANY_RFO:DDR_NEAR .P But the following is illegal: .TP .B OFFCORE_RESPONSE_0:ANY_RFO:DDR_NEAR:ANY_RESPONSE .P In average latency mode, \fBOFFCORE_RESPONSE_0\fR must be programmed to select the request types of interest, for instance, \fBDMND_DATA_RD\fR, and the \fBOUTSTANDING\fR umask must be set and no others. the library will enforce that restriction as soon as the \fBOUTSTANDING\fR umask is used. Then \fBOFFCORE_RESPONSE_1\fR must be set with the same request types and the \fBANY_RESPONSE\fR umask. It should be noted that the library encodes events independently of each other and therefore cannot verify that the requests are matching between the two events. Example of average latency settings: .TP .B OFFCORE_RESPONSE_0:DMND_DATA_RD:OUTSTANDING+OFFCORE_RESPONSE_1:DMND_DATA_RD:ANY_RESPONSE .TP .B OFFCORE_RESPONSE_0:ANY_REQUEST:OUTSTANDING+OFFCORE_RESPONSE_1:ANY_REQUEST:ANY_RESPONSE .P The average latency for the request(s) is obtained by dividing the counts of \fBOFFCORE_RESPONSE_0\fR by the count of \fBOFFCORE_RESPONSE_1\fR. The ratio is expressed in core cycles. .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/libpfm_amd64_k7.30000664000175000017500000000242713223402656017342 0ustar eranianeranian.TH LIBPFM 3 "August, 2010" "" "Linux Programmer's Manual" .SH NAME libpfm_amd64_k7 - support for AMD64 K7 processors .SH SYNOPSIS .nf .B #include .sp .B PMU name: amd64_k7 .B PMU desc: AMD64 K7 .sp .SH DESCRIPTION The library supports AMD K7 processors in both 32 and 64-bit modes. They correspond to processor family 6. .SH MODIFIERS The following modifiers are supported on AMD64 K7 processors: .TP .B u Measure at user level which includes privilege levels 1, 2, 3. This corresponds to \fBPFM_PLM3\fR. This is a boolean modifier. .TP .B k Measure at kernel level which includes privilege level 0. This corresponds to \fBPFM_PLM0\fR. This is a boolean modifier. .TP .B i Invert the meaning of the event. The counter will now count cycles in which the event is \fBnot\fR occurring. This is a boolean modifier .TP .B e Enable edge detection, i.e., count only when there is a state transition. This is a boolean modifier. .TP .B c Set the counter mask value. The mask acts as a threshold. The counter will count the number of cycles in which the number of occurrences of the event is greater or equal to the threshold. This is an integer modifier with values in the range [0:255]. .SH AUTHORS .nf Stephane Eranian Robert Richter .if .PP libpfm-4.9.0/docs/man3/libpfm_intel_nhm.30000664000175000017500000000564213223402656020005 0ustar eranianeranian.TH LIBPFM 3 "September, 2009" "" "Linux Programmer's Manual" .SH NAME libpfm_intel_nhm - support for Intel Nehalem core PMU .SH SYNOPSIS .nf .B #include .sp .B PMU name: nhm .B PMU desc: Intel Nehalem .B PMU name: nhm_ex .B PMU desc: Intel Nehalem EX .sp .SH DESCRIPTION The library supports the Intel Nehalem core PMU. It should be noted that this PMU model only covers the each core's PMU and not the socket level PMU. It is provided separately. Support is provided for the Intel Core i7 and Core i5 processors. .SH MODIFIERS The following modifiers are supported on Intel Nehalem processors: .TP .B u Measure at user level which includes privilege levels 1, 2, 3. This corresponds to \fBPFM_PLM3\fR. This is a boolean modifier. .TP .B k Measure at kernel level which includes privilege level 0. This corresponds to \fBPFM_PLM0\fR. This is a boolean modifier. .TP .B i Invert the meaning of the event. The counter will now count cycles in which the event is \fBnot\fR occurring. This is a boolean modifier .TP .B e Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a counter mask modifier (m) with a value greater or equal to one. This is a boolean modifier. .TP .B c Set the counter mask value. The mask acts as a threshold. The counter will count the number of cycles in which the number of occurrences of the event is greater or equal to the threshold. This is an integer modifier with values in the range [0:255]. .TP .B t Measure on both threads at the same time assuming hyper-threading is enabled. This is a boolean modifier. .TP .B ldlat Pass a latency threshold to the MEM_INST_RETIRED:LATENCY_ABOVE_THRESHOLD event. This is an integer attribute that must be in the range [3:65535]. It is required for this event. Note that the event must be used with precise sampling (PEBS). .SH OFFCORE_RESPONSE event The library is able to encode the OFFCORE_RESPONSE_0 event. This is a special event because it needs a second MSR (0x1a6) to be programmed for the event to count properly. Thus two values are necessary. The first value can be programmed on any of the generic counters. The second value goes into the dedicated MSR (0x1a6). The OFFCORE_RESPONSE event is exposed as a normal event with several umasks which are divided in two groups: request and response. The user must provide \fBat least\fR one umask from each group. For instance, OFFCORE_RESPONSE_0:ANY_DATA:LOCAL_DRAM. When using \fBpfm_get_event_encoding()\fR, two 64-bit values are returned. The first value corresponds to what needs to be programmed into any of the generic counters. The second value must be programmed into the dedicated MSR (0x1a6). When using an OS-specific encoding routine, the way the event is encoded is OS specific. Refer to the corresponding man page for more information. .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/libpfm_amd64_fam16h.30000664000175000017500000000312113223402656020073 0ustar eranianeranian.TH LIBPFM 3 "July, 2017" "" "Linux Programmer's Manual" .SH NAME libpfm_amd64_fam16h - support for AMD64 Family 16h processors .SH SYNOPSIS .nf .B #include .sp .B PMU name: amd64_fam16h .B PMU desc: AMD64 Fam16h Zen .sp .SH DESCRIPTION The library supports AMD Family 16h processors core PMU in both 32 and 64-bit modes. .SH MODIFIERS The following modifiers are supported on AMD64 Family 16h core PMU: .TP .B u Measure at user level which includes privilege levels 1, 2, 3. This corresponds to \fBPFM_PLM3\fR. This is a boolean modifier. .TP .B k Measure at kernel level which includes privilege level 0. This corresponds to \fBPFM_PLM0\fR. This is a boolean modifier. .TP .B h Measure at while executing in host mode (when using virtualization). This corresponds to \fBPFM_PLMH\fR. This modifier is available starting with Fam10h. This is a boolean modifier. .TP .B g Measure at while executing in guest mode (when using virtualization). This modifier is available starting with Fam10h. This is a boolean modifier. .TP .B i Invert the meaning of the event. The counter will now count cycles in which the event is \fBnot\fR occurring. This is a boolean modifier .TP .B e Enable edge detection, i.e., count only when there is a state transition. This is a boolean modifier. .TP .B c Set the counter mask value. The mask acts as a threshold. The counter will count the number of cycles in which the number of occurrences of the event is greater or equal to the threshold. This is an integer modifier with values in the range [0:255]. .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/libpfm_intel_ivbep_unc_ha.30000664000175000017500000000213413223402656021636 0ustar eranianeranian.TH LIBPFM 3 "February, 2014" "" "Linux Programmer's Manual" .SH NAME libpfm_intel_ivbep_unc_ha - support for Intel Ivy Bridge-EP Home Agent (HA) uncore PMU .SH SYNOPSIS .nf .B #include .sp .B PMU name: ivbep_unc_ha0, ivbep_unc_ha1 .B PMU desc: Intel Ivy Bridge-EP HA uncore PMU .sp .SH DESCRIPTION The library supports the Intel Ivy Bridge Home Agent (HA) uncore PMU. This PMU model only exists on Ivy Bridge model 62. .SH MODIFIERS The following modifiers are supported on Intel Ivy Bridge HA uncore PMU: .TP .B e Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one. This is a boolean modifier. .TP .B t Set the threshold value. When set to a non-zero value, the counter counts the number of HA cycles in which the number of occurrences of the event is greater or equal to the threshold. This is an integer modifier with values in the range [0:255]. .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/pfm_strerror.30000664000175000017500000000224513223402656017217 0ustar eranianeranian.TH LIBPFM 3 "September, 2009" "" "Linux Programmer's Manual" .SH NAME pfm_strerror \- return constant string describing error code .SH SYNOPSIS .nf .B #include .sp .BI "const char *pfm_strerror(int "code); .sp .SH DESCRIPTION This function returns a string which describes the libpfm error value in \fBcode\fR. The string returned by the call is \fBread-only\fR. The function must \fBonly\fR be used with libpfm calls documented to return specific error codes. The value \-1 is not considered a specific error code. Strings and \fBpfm_pmu_t\fR return values cannot be used with this function. Typically \fBNULL\fR is returned in case of error for string values, and \fBPFM_PMU_NONE\fR is returned for \fBpfm_pmu_t\fR values. The function is also not designed to handle OS system call errors, i.e., errno values. .SH RETURN The function returns a pointer to the constant string describing the error code. The string is in English. If code is invalid then a default error message is returned. .SH ERRORS If the error code is invalid, then the function returns a pointer to a string which says "unknown error code". .SH AUTHOR Stephane Eranian .PP libpfm-4.9.0/docs/man3/libpfm_arm_xgene.30000664000175000017500000000160213223402656017765 0ustar eranianeranian.TH LIBPFM 3 "May, 2014" "" "Linux Programmer's Manual" .SH NAME libpfm_arm_ac57 - support for Applied Micro X-Gene PMU .SH SYNOPSIS .nf .B #include .sp .B PMU name: arm_xgene .B PMU desc: Applied Micro X-Gene .sp .SH DESCRIPTION The library supports the Applied Micro X-Gene PMU. This PMU supports 6 counters and privilege levels filtering. It can operate in both 32 and 64 bit modes. .SH MODIFIERS The following modifiers are supported on Applied Micro X-Gene: .TP .B u Measure at the user level. This corresponds to \fBPFM_PLM3\fR. This is a boolean modifier. .TP .B k Measure at the kernel level. This corresponds to \fBPFM_PLM0\fR. This is a boolean modifier. .TP .B hv Measure at the hypervisor level. This corresponds to \fBPFM_PLMH\fR. This is a boolean modifier. .SH AUTHORS .nf Stephane Eranian .if .nf William Cohen .if .PP libpfm-4.9.0/docs/man3/libpfm_intel_bdx_unc_cbo.30000664000175000017500000000726513223402656021473 0ustar eranianeranian.TH LIBPFM 3 "June, 2017" "" "Linux Programmer's Manual" .SH NAME libpfm_intel_bdx_unc_cbo - support for Intel Broadwell Server C-Box uncore PMU .SH SYNOPSIS .nf .B #include .sp .B PMU name: bdx_unc_cbo[0-21] .B PMU desc: Intel Broadwell Server C-Box uncore PMU .sp .SH DESCRIPTION The library supports the Intel Broadwell Server C-Box (coherency engine) uncore PMU. This PMU model exists on various Broadwell server models (79, 86) . There is one C-box PMU per physical core. Therefore there are up to twenty-one identical C-Box PMU instances numbered from 0 to 21. On dual-socket systems, the number refers to the C-Box PMU on the socket where the program runs. For instance, if running on CPU18, then bdx_unc_cbo0 refers to the C-Box for physical core 0 on socket 1. Conversely, if running on CPU0, then the same bdx_unc_cbo0 refers to the C-Box for physical core 0 but on socket 0. Each C-Box PMU implements 4 generic counters and two filter registers used only with certain events and umasks. .SH MODIFIERS The following modifiers are supported on Intel Broadwell C-Box uncore PMU: .TP .B e Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one. This is a boolean modifier. .TP .B t Set the threshold value. When set to a non-zero value, the counter counts the number of C-Box cycles in which the number of occurrences of the event is greater or equal to the threshold. This is an integer modifier with values in the range [0:255]. .TP .B nf Node filter. Certain events, such as UNC_C_LLC_LOOKUP, UNC_C_LLC_VICTIMS, provide a \fBNID\fR umask. Sometimes the \fBNID\fR is combined with other filtering capabilities, such as opcodes. The node filter is an 8-bit max bitmask. A node corresponds to a processor socket. The legal values therefore depend on the underlying hardware configuration. For dual-socket systems, the bitmask has two valid bits [0:1]. .TP .B cf Core Filter. This is a 5-bit filter which is used to filter based on physical core origin of the C-Box request. Possible values are 0-63. If the filter is not specified, then no filtering takes place. Bit 0-3 indicate the physical core id and bit 4 filters on non thread-related data. .TP .B tf Thread Filter. This is a 1-bit filter which is used to filter C-Box requests based on logical processor (hyper-thread) identification. Possibles values are 0-1. If the filter is not specified, then no filtering takes place. .TP .B nc Non-Coherent. This is a 1-bit filter which is used to filter C-Box requests only for the TOR_INSERTS and TOR_OCCUPANCY umasks using the OPCODE matcher. If the filter is not specified, then no filtering takes place. .TP .B isoc Isochronous. This is a 1-bit filter which is used to filter C-Box requests only for the TOR_INSERTS and TOR_OCCUPANCY umasks using the OPCODE matcher. If the filter is not specified, then no filtering takes place. .SH Opcode filtering Certain events, such as UNC_C_TOR_INSERTS supports opcode matching on the C-BOX transaction type. To use this feature, first an opcode matching umask must be selected, e.g., MISS_OPCODE. Second, the opcode to match on must be selected via a second umask among the OPC_* umasks. For instance, UNC_C_TOR_INSERTS:OPCODE:OPC_RFO, counts the number of TOR insertions for RFO transactions. Opcode matching may be combined with node filtering with certain umasks. In general, the filtering support is encoded into the umask name, e.g., NID_OPCODE supports both node and opcode filtering. For instance, UNC_C_TOR_INSERTS:NID_OPCODE:OPC_RFO:nf=1. .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/libpfm_intel_snbep_unc_ha.30000664000175000017500000000243713223402656021646 0ustar eranianeranian.TH LIBPFM 3 "August, 2012" "" "Linux Programmer's Manual" .SH NAME libpfm_intel_snbep_unc_ha - support for Intel Sandy Bridge-EP Home Agent (HA) uncore PMU .SH SYNOPSIS .nf .B #include .sp .B PMU name: snbep_unc_ha .B PMU desc: Intel Sandy Bridge-EP HA uncore PMU .sp .SH DESCRIPTION The library supports the Intel Sandy Bridge Home Agent (HA) uncore PMU. This PMU model only exists on Sandy Bridge model 45. There is only one Home Agent per processor socket. .SH MODIFIERS The following modifiers are supported on Intel Sandy Bridge C-Box uncore PMU: .TP .B i Invert the meaning of the event. The counter will now count HA cycles in which the event is \fBnot\fR occurring. This is a boolean modifier .TP .B e Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one. This is a boolean modifier. .TP .B t Set the threshold value. When set to a non-zero value, the counter counts the number of HA cycles in which the number of occurrences of the event is greater or equal to the threshold. This is an integer modifier with values in the range [0:255]. .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/libpfm.30000664000175000017500000001352713223402656015751 0ustar eranianeranian.TH LIBPFM 3 "May, 2010" "" "Linux Programmer's Manual" .SH NAME libpfm \- a helper library to develop monitoring tools .SH SYNOPSIS .nf .B #include .SH DESCRIPTION This is a helper library used by applications to program specific performance monitoring events. Those events are typically provided by the hardware or the OS kernel. The most common hardware events are provided by the Performance Monitoring Unit (PMU) of modern processors. They can measure elapsed cycles or the number of cache misses. Software events usually count kernel events such as the number of context switches, or pages faults. The library groups events based on which source is providing them. The term PMU is generalized to any event source, not just hardware sources. The library supports hardware performance events from most common processors, each group under a specific PMU name, such as Intel Core, IBM Power 6. Programming events is usually done through a kernel API, such as Oprofile, perfmon, perfctr, or perf_events on Linux. The library provides support for perf_events which is available in the Linux kernel as of v2.6.31. Perf_events supports selected PMU models and several software events. At its core, the library provides a simple translation service, whereby a user specifies an event to measure as a string and the library returns the parameters needed to invoke the kernel API. It is important to realize that the library does \fBnot\fR make the system call to program the event. \fBNote:\fR You must first call \fBpfm_initialize()\fR in order to use any of the other provided functions in the library. A first part of the library provides an event listing and query interface. This can be used to discover the events available on a specific hardware platform. The second part of the library provides a set of functions to obtain event encodings form event strings. Event encoding depends primarily on the underlying hardware but also on the kernel API. The library offers a generic API to address the first situation but it also provides entry points for specific kernel APIs such as perf_events. In that case, it is able to prepare the data structure which must be passed to the kernel to program a specific event. .SH EVENT DETECTION When the library is initialized via \fBpfm_initialize()\fR, it first detects the underlying hardware and software configuration. Based on this information it enables certain PMU support. Multiple events tables may be activated. It is possible to force activation of a specific PMU (group of events) using an environment variable. .SH EVENT STRINGS Events are expressed as strings. Those string are structured and may contain several components depending on the type of event and the underlying hardware. String parsing is always case insensitive. The string structure is defined as follows: .sp .ce .B [pmu::][event_name][:unit_mask][:modifier|:modifier=val] or .ce .B [pmu::][event_name][.unit_mask][.modifier|.modifier=val] The components are defined as follows: .TP .B pmu Optional name of the PMU (group of events) to which the event belongs to. This is useful to disambiguate events in case events from difference sources have the same name. If not specified, the first match is used. .TP .B event_name The name of the event. It must be the complete name, partial matches are not accepted. This component is required. .TP .B unit_mask This designate an optional sub-events. Some events can be refined using sub-events. Event may have multiple unit masks and it may or may be possible to combine them. If more than one unit masks needs to be passed, then the [:unit_mask] pattern can be repeated. .TP .B modifier A modifier is an optional filter which modifies how the event counts. Modifiers have a type and a value. The value is specified after the equal sign. No space is allowed. In case of boolean modifiers, it is possible to omit the value true (1). The presence of the modifier is interpreted as meaning true. Events may support multiple modifiers, in which case the [:modifier|:modifier=val] pattern can be repeated. The is no ordering constraint between modifier and unit masks. Modifiers may be specified before unit masks and vice-versa. .SH ENVIRONMENT VARIABLES It is possible to enable certain debug features of the library using environment variables. The following variables are defined: .TP .B LIBPFM_VERBOSE Enable verbose output. Value must be 0 or 1. .TP .B LIBPFM_DEBUG Enable debug output. Value must be 0 or 1 .TP .B LIBPFM_DEBUG_STDOUT Redirect verbose and debug output to the standard output file descriptor (stdout). By default, the output is directed to the standard error file descriptor (stderr). .TP .B LIBPFM_FORCE_PMU Force a specific PMU model to be activated. In this mode, only that one model is activated. The value of the variable must be the PMU name as returned by the \fBpfm_get_pmu_name()\fR function. Note for some PMU models, it may be possible to specify additional options, such as specific processor models or stepping. Additional parameters necessarily appears after a comma. For instance, LIBPFM_FORCE_PMU=amd64,16,2,1. .TP .B LIBPFM_ENCODE_INACTIVE Set this variable to 1 to enable encoding of events for non detected, but supported, PMUs models. .TP .B LIBPFM_DISABLED_PMUS Provides a list of PMU models to disable. This is a comma separated list of PMU models. The PMU model is the string in \fBname\fR field of the \fBpfm_pmu_info_t\fR structure. For instance: LIBPFM_DISABLE_PMUS=core,snb, will disable both the Intel Core and SandyBridge core PMU support. .SH AUTHORS .nf Stephane Eranian Robert Richter .fi .SH SEE ALSO libpfm_amd64_k7(3), libpfm_amd64_k8(3), libpfm_amd64_fam10h(3), libpfm_intel_core(3), libpfm_intel_atom(3), libpfm_intel_p6(3), libpfm_intel_nhm(3), libpfm_intel_nhm_unc(3), pfm_get_perf_event_encoding(3), pfm_initialize(3) .sp Some examples are shipped with the library libpfm-4.9.0/docs/man3/libpfm_perf_event_raw.30000664000175000017500000000715413223402656021036 0ustar eranianeranian.TH LIBPFM 3 "February, 2014" "" "Linux Programmer's Manual" .SH NAME libpfm_perf_event_raw - support for perf_events raw events syntax .SH SYNOPSIS .nf .B #include .sp .B PMU name: perf_raw .B PMU desc: Raw perf_events event syntax .sp .SH DESCRIPTION The library supports a pseudo PMU model to allow raw encodings of PMU events for the Linux perf_events kernel interface. With this PMU, it is possible to provide the raw hexadecimal encoding of any hardware event for any PMU models. The raw encoding is passed as is to the kernel. All events are encoded as \fBPERF_TYPE_RAW\fR. As such, perf_events generic events, such as cycles, instructions, cannot be encoded by this PMU. The syntax is very simple: rX. X is the hexadecimal 64-bit value for the event. It may include event filters on some PMU models. The hexadecimal number is passed without the 0x prefix, e.g., r01c4. The library's standard perf_events attributes are supported by this PMU model. They are separated with colons as is customary with the library. .SH MODIFIERS The following modifiers are supported by this PMU model: .TP .B u Measure at user level which includes privilege levels 1, 2, 3. This corresponds to \fBPFM_PLM3\fR. This is a boolean modifier. .TP .B k Measure at kernel level which includes privilege level 0. This corresponds to \fBPFM_PLM0\fR. This is a boolean modifier. .TP .B h Measure at the hypervisor level. This corresponds to \fBPFM_PLMH\fR. This is a boolean modifier .TP .B mg Measure guest execution only. This is a boolean modifier .TP .B mh Measure host execution only. This is a boolean modifier .TP .B period Specify the the sampling period value. Value can be expressed in decimal or hexadecimal. Value is 64-bit wide. This option is mutually exclusive with \fBfreq\fR. The period is expressed in the unit of the event. There is no default value. .TP .B freq Specify the the sampling frequency value. Value can be expressed in decimal or hexadecimal. Value is 64-bit wide. This options is mutually exclusive with \fBperiod\fR. The value is expressed in Hertz. For instance, freq=100, means that the event should be sampled 100 times per second on average. There is no default value. .TP .B excl The associated event is the only event measured on the PMU. This applies only to hardware events. This attribute requires admin privileges. Default is off. .TP .B precise Enables precise sampling mode. This option is only valid on sampling events. This is an integer value. It can have the following values: 1 enable precise sampling, 2 enable precise sampling and eliminate skid. Not all events necessarily support precise mode, this is dependent on the underlying PMU. Eliminating skid is a best effort feature. It may not work for all samples. .TP .B cpu This integer option is used with system-wide events, i.e., events attached to a CPU instead of a thread. The value designate the CPU to attach the event to. It is up to the caller of the library to use the cpu field in the library event encoding argument to create the event. No verification on the validity of the CPU number is made by the library. Default value is -1 for this field. .TP .B pinned This boolean option is used with system-wide events, i.e., events attached to a CPU instead of a thread. If set, then the event is marked as pinned. That means it needs to remain on the counters at all time, i.e., it cannot be multiplexed. There can only be as many pinned events as there are counters, yet the library does not check for that, the perf_event subsystem does. The default value for this field is false, i.e., the event is not pinned. .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/libpfm_amd64_fam10h.30000664000175000017500000000341413223402656020072 0ustar eranianeranian.TH LIBPFM 3 "August, 2010" "" "Linux Programmer's Manual" .SH NAME libpfm_amd64_fam10h - support for AMD64 Family 10h processors .SH SYNOPSIS .nf .B #include .sp .B PMU name: amd64_fam10h_barcelona, amd64_fam10h_shanghai, amd64_fam10h_istanbul .B PMU desc: AMD64 Fam10h Barcelona, AMD64 Fam10h Shanghai, AMD64 Fam10h Istanbul .sp .SH DESCRIPTION The library supports AMD Family 10h processors in both 32 and 64-bit modes. They correspond to processor family 16. .SH MODIFIERS The following modifiers are supported on AMD64 Family 10h (16) processors: .TP .B u Measure at user level which includes privilege levels 1, 2, 3. This corresponds to \fBPFM_PLM3\fR. This is a boolean modifier. .TP .B k Measure at kernel level which includes privilege level 0. This corresponds to \fBPFM_PLM0\fR. This is a boolean modifier. .TP .B h Measure at while executing in host mode (when using virtualization). This corresponds to \fBPFM_PLMH\fR. This modifier is available starting with Fam10h. This is a boolean modifier. .TP .B g Measure at while executing in guest mode (when using virtualization). This modifier is available starting with Fam10h. This is a boolean modifier. .TP .B i Invert the meaning of the event. The counter will now count cycles in which the event is \fBnot\fR occurring. This is a boolean modifier .TP .B e Enable edge detection, i.e., count only when there is a state transition. This is a boolean modifier. .TP .B c Set the counter mask value. The mask acts as a threshold. The counter will count the number of cycles in which the number of occurrences of the event is greater or equal to the threshold. This is an integer modifier with values in the range [0:255]. .SH AUTHORS .nf Stephane Eranian Robert Richter .if .PP libpfm-4.9.0/docs/man3/libpfm_arm_ac9.30000664000175000017500000000070213223402656017333 0ustar eranianeranian.TH LIBPFM 3 "August, 2012" "" "Linux Programmer's Manual" .SH NAME libpfm_arm_ac9 - support for ARM Cortex A9 PMU .SH SYNOPSIS .nf .B #include .sp .B PMU name: arm_ac9 .B PMU desc: ARM Cortex A9 .sp .SH DESCRIPTION The library supports the ARM Cortex A9 core PMU. This PMU supports 2 counters and has no privilege levels filtering. No event modifiers are available. .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/libpfm_intel_skl.30000664000175000017500000001036513223402656020012 0ustar eranianeranian.TH LIBPFM 3 "August, 2015" "" "Linux Programmer's Manual" .SH NAME libpfm_intel_skl - support for Intel SkyLake core PMU .SH SYNOPSIS .nf .B #include .sp .B PMU name: skl .B PMU desc: Intel SkyLake .sp .SH DESCRIPTION The library supports the Intel SkyLake core PMU. It should be noted that this PMU model only covers each core's PMU and not the socket level PMU. On SkyLake, the number of generic counters depends on the Hyperthreading (HT) mode. counters are available. The \fBpfm_get_pmu_info()\fR function returns the maximum number of generic counters in \fBnum_cntrs\fr. .SH MODIFIERS The following modifiers are supported on Intel SkyLake processors: .TP .B u Measure at user level which includes privilege levels 1, 2, 3. This corresponds to \fBPFM_PLM3\fR. This is a boolean modifier. .TP .B k Measure at kernel level which includes privilege level 0. This corresponds to \fBPFM_PLM0\fR. This is a boolean modifier. .TP .B i Invert the meaning of the event. The counter will now count cycles in which the event is \fBnot\fR occurring. This is a boolean modifier .TP .B e Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a counter mask modifier (m) with a value greater or equal to one. This is a boolean modifier. .TP .B c Set the counter mask value. The mask acts as a threshold. The counter will count the number of cycles in which the number of occurrences of the event is greater or equal to the threshold. This is an integer modifier with values in the range [0:255]. .TP .B t Measure on both threads at the same time assuming hyper-threading is enabled. This is a boolean modifier. .TP .B ldlat Pass a latency threshold to the MEM_TRANS_RETIRED:LOAD_LATENCY event. This is an integer attribute that must be in the range [3:65535]. It is required for this event. Note that the event must be used with precise sampling (PEBS). .TP .B intx Monitor the event only when executing inside a transactional memory region (in tx). Event does not count otherwise. This is a boolean modifiers. Default value is 0. .TP .B intxcp Do not count occurrences of the event when they are inside an aborted transactional memory region. This is a boolean modifier. Default value is 0. .TP .B fe_thres This modifier is for the FRONTEND_RETIRED event only. It defines the period in core cycles after which the IDQ_*_BUBBLES umask counts. It acts as a threshold, i.e., at least a period of N core cycles where the frontend did not deliver X uops. It can only be used with the IDQ_*_BUBBLES umasks. If not specified, the default threshold value is 1 cycle. the valid values are in [1-4095]. .SH OFFCORE_RESPONSE events Intel SkyLake provides two offcore_response events. They are called OFFCORE_RESPONSE_0 and OFFCORE_RESPONSE_1. Those events need special treatment in the performance monitoring infrastructure because each event uses an extra register to store some settings. Thus, in case multiple offcore_response events are monitored simultaneously, the kernel needs to manage the sharing of that extra register. The offcore_response events are exposed as a normal events by the library. The extra settings are exposed as regular umasks. The library takes care of encoding the events according to the underlying kernel interface. On Intel SkyLake, the umasks are divided into three categories: request, supplier and snoop. The user must provide at least one umask for each category. The categories are shown in the umask descriptions. There is also the special response umask called \fBANY_RESPONSE\fR. When this umask is used then it overrides any supplier and snoop umasks. In other words, users can specify either \fBANY_RESPONSE\fR \fBOR\fR any combinations of supplier + snoops. In case no supplier or snoop is specified, the library defaults to using \fBANY_RESPONSE\fR. For instance, the following are valid event selections: .TP .B OFFCORE_RESPONSE_0:DMND_DATA_RD:ANY_RESPONSE .TP .B OFFCORE_RESPONSE_0:ANY_REQUEST .TP .B OFFCORE_RESPONSE_0:ANY_RFO:LLC_HITM:SNOOP_ANY .P But the following are illegal: .TP .B OFFCORE_RESPONSE_0:ANY_RFO:LLC_HITM:ANY_RESPONSE .TP .B OFFCORE_RESPONSE_0:ANY_RFO:LLC_HITM:SNOOP_ANY:ANY_RESPONSE .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/libpfm_intel_atom.30000664000175000017500000000252413223402656020157 0ustar eranianeranian.TH LIBPFM 3 "September, 2009" "" "Linux Programmer's Manual" .SH NAME libpfm_intel_atom - support for Intel Atom processors .SH SYNOPSIS .nf .B #include .sp .B PMU name: atom .B PMU desc: Intel Atom .sp .SH DESCRIPTION The library supports all Intel Atom-based processors that includes family 6 model 28. .SH MODIFIERS The following modifiers are supported on Intel Atom processors: .TP .B u Measure at user level which includes privilege levels 1, 2, 3. This corresponds to \fBPFM_PLM3\fR. This is a boolean modifier. .TP .B k Measure at kernel level which includes privilege level 0. This corresponds to \fBPFM_PLM0\fR. This is a boolean modifier. .TP .B i Invert the meaning of the event. The counter will now count cycles in which the event is \fBnot\fR occurring. This is a boolean modifier .TP .B e Enable edge detection, i.e., count only when there is a state transition. This is a boolean modifier. .TP .B c Set the counter mask value. The mask acts as a threshold. The counter will count the number of cycles in which the number of occurrences of the event is greater or equal to the threshold. This is an integer modifier with values in the range [0:255]. .TP .B t Measure on both threads at the same time assuming hyper-threading is enabled. This is a boolean modifier. .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/libpfm_amd64_fam17h.30000664000175000017500000000312113223402656020074 0ustar eranianeranian.TH LIBPFM 3 "July, 2017" "" "Linux Programmer's Manual" .SH NAME libpfm_amd64_fam17h - support for AMD64 Family 17h processors .SH SYNOPSIS .nf .B #include .sp .B PMU name: amd64_fam15h .B PMU desc: AMD64 Fam17h Zen .sp .SH DESCRIPTION The library supports AMD Family 17h processors core PMU in both 32 and 64-bit modes. .SH MODIFIERS The following modifiers are supported on AMD64 Family 17h core PMU: .TP .B u Measure at user level which includes privilege levels 1, 2, 3. This corresponds to \fBPFM_PLM3\fR. This is a boolean modifier. .TP .B k Measure at kernel level which includes privilege level 0. This corresponds to \fBPFM_PLM0\fR. This is a boolean modifier. .TP .B h Measure at while executing in host mode (when using virtualization). This corresponds to \fBPFM_PLMH\fR. This modifier is available starting with Fam10h. This is a boolean modifier. .TP .B g Measure at while executing in guest mode (when using virtualization). This modifier is available starting with Fam10h. This is a boolean modifier. .TP .B i Invert the meaning of the event. The counter will now count cycles in which the event is \fBnot\fR occurring. This is a boolean modifier .TP .B e Enable edge detection, i.e., count only when there is a state transition. This is a boolean modifier. .TP .B c Set the counter mask value. The mask acts as a threshold. The counter will count the number of cycles in which the number of occurrences of the event is greater or equal to the threshold. This is an integer modifier with values in the range [0:255]. .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/libpfm_intel_bdx_unc_r2pcie.30000664000175000017500000000275413223402656022112 0ustar eranianeranian.TH LIBPFM 3 "June, 2017" "" "Linux Programmer's Manual" .SH NAME libpfm_intel_bdx_unc_r2pcie - support for Intel Broadwell Server R2 PCIe uncore PMU .SH SYNOPSIS .nf .B #include .sp .B PMU name: bdx_unc_r2pcie .B PMU desc: Intel Broadwell Server R2 PCIe uncore PMU .sp .SH DESCRIPTION The library supports the Intel Broadwell server R2 PCIe uncore PMU. This PMU model only exists on Broadwell server models (79, 86). .SH MODIFIERS The following modifiers are supported on Intel Broadwell server R2PCIe uncore PMU: .TP .B e Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one. This is a boolean modifier. .TP .B t Set the threshold value. When set to a non-zero value, the counter counts the number of R2PCIe cycles in which the number of occurrences of the event is greater or equal to the threshold. This is an integer modifier with values in the range [0:15]. .TP .B i Invert the meaning of the threshold or edge filter. If set, the event counts when strictly less than N occurrences occur per cycle if threshold is set to N. When invert is set, then threshold must be set to non-zero value. If set, the event counts when the event transitions from occurring to not occurring (falling edge) when edge detection is set. This is a boolean modifier .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/pfm_get_perf_event_encoding.30000664000175000017500000001233513223402656022200 0ustar eranianeranian.TH LIBPFM 3 "September, 2009" "" "Linux Programmer's Manual" .SH NAME pfm_get_perf_event_encoding \- encode event for perf_event API .SH SYNOPSIS .nf .B #include .sp .BI "int pfm_get_perf_event_encoding(const char *" str ", int " dfl_plm ", struct perf_event_attr *" attr ", char **" fstr ", int *" idx ");" .sp .SH DESCRIPTION This function can be used in conjunction with the perf_events Linux kernel API which provides access to hardware performance counters, kernel software counters and tracepoints. The function takes an event string in \fBstr\fR and a default privilege level mask in \fBdfl_plm\fR and fills out the relevant parts of the perf_events specific data structure in \fBattr\fR. This function is \fBdeprecated\fR. It is superseded by \fBpfm_get_os_event_encoding()\fR with the OS argument set to either \fBPFM_OS_PERF_EVENT\fR or \fBPFM_OS_PERF_EVENT_EXT\fR. Using this function provides extended support for perf_events. Certain perf_event configuration option are only available through this new interface. The following examples illustrates the transition: .nf struct perf_event_attr attr; int i, count = 0; uint64_t *codes; memset(&attr, 0, sizeof(attr)); ret = pfm_get_perf_event_encoding("RETIRED_INSTRUCTIONS", PFM_PLM3, &attrs, NULL, NULL); if (ret != PFM_SUCCESS) err(1", cannot get encoding %s", pfm_strerror(ret)); .fi is equivalent to: .nf #include struct perf_event_attr attr; pfm_perf_encode_arg_t arg; memset(&arg, 0, sizeof(arg)); arg.size = sizeof(arg); arg.attr = &attr; ret = pfm_get_os_event_encoding("RETIRED_INSTRUCTIONS", PFM_PLM3, PFM_OS_PERF, &arg); if (ret != PFM_SUCCESS) err(1", cannot get encoding %s", pfm_strerror(ret)); .nf The \fBdfl_plm\fR cannot be zero, though it may not necessarily be used by the event. Depending on the event, combination of the following privilege levels may be used: .TP .B PFM_PLM3 Measure at privilege level 3. This usually corresponds to user level. On X86, it corresponds to privilege levels 3, 2, 1. Check the PMU specific man page to verify if this level is supported by your PMU model. .TP .B PFM_PLM2 Measure at privilege level 2. Check the PMU specific man page to verify if this level is supported by your PMU model. .TP .B PFM_PLM1 Measure at privilege level 1. Check the PMU specific man page to verify if this level is supported by your PMU model. .TP .B PFM_PLM0 Measure at privilege level 0. This usually corresponds to kernel level. Check the PMU specific man page to verify if this level is supported by your PMU model. .TP .B PFM_PLMH Measure at hypervisor privilege level. This is used in conjunction with hardware virtualization. Check the PMU specific man page to verify if this level is supported by your PMU model. .PP If \fBfstr\fR is not NULL, the function will make it point to the fully qualified event string, i.e., a string with the event name, all unit masks set, and the value of all modifiers. The library will allocate memory to store the event string but it is the responsibility of the caller to eventually free that string using free(). If \fBidx\fR is not NULL, it returns the corresponding unique event identifier. Only select fields are modified by the function, the others are untouched. The following fields in \fBattr\fR are modified: .TP .B type The type of the event .TP .B config The encoding of the event .TP .B exclude_user Whether or not user level execution should be excluded from monitoring. The definition of user is PMU model specific. .TP .B exclude_kernel Whether or not kernel level execution should be excluded from monitoring. The definition of kernel is PMU model specific. .TP .B exclude_hv Whether or not hypervisor level execution should be excluded from monitoring. The definition of hypervisor is PMU model specific. .PP By default, if no privilege level modifier is specified in the event string, the library clears \fBexclude_user\fR, \fBexclude_kernel\fR and \fBexclude_hv\fR, resulting in the event being measured at all levels subject to hardware support. The function is able to work on only one event at a time. For convenience, it accepts event strings with commas. In that case, it will translate the first event up to the first comma. This is handy in case tools gets passed events as a comma-separated list. .SH RETURN The function returns in \fBattr\fR the perf_event encoding which corresponds to the event string. If \fBidx\fR is not NULL, then it will contain the unique event identifier upon successful return. The value \fBPFM_SUCCESS\fR is returned if successful, otherwise a negative error code is returned. .SH ERRORS .TP .B PFM_ERR_TOOSMALL The \fBcode\fR argument is too small for the encoding. .TP .B PFM_ERR_INVAL The \fBattr\fR argument is \fBNULL\fR. .TP .B PFM_ERR_NOMEM Not enough memory. .TP .B PFM_ERR_NOTFOUND Event not found. .TP .B PFM_ERR_ATTR Invalid event attribute (unit mask or modifier) .TP .B PFM_ERR_ATTR_VAL Invalid modifier value. .TP .B PFM_ERR_ATTR_SET attribute already set, cannot be changed. .TP .B PFM_ERR_ATTR_UMASK Missing unit mask. .TP .B PFM_ERR_ATTR_FEATCOMB Unit masks or features cannot be combined into a single event. .SH AUTHOR Stephane Eranian .SH SEE ALSO pfm_get_os_event_encoding(3) libpfm-4.9.0/docs/man3/libpfm_amd64_k8.30000664000175000017500000000266713223402656017351 0ustar eranianeranian.TH LIBPFM 3 "April, 2009" "" "Linux Programmer's Manual" .SH NAME libpfm_amd64_k8 - support for AMD64 K8 processors .SH SYNOPSIS .nf .B #include .sp .B PMU name: amd64_k8_revb, amd64_k8_revc, amd64_k8_revd, amd64_k8_reve, amd64_k8_revf, amd64_k8_revg .B PMU desc: AMD64 K8 RevB, AMD64 K8 RevC, AMD64 K8 RevD, AMD64 K8 RevE, AMD64 K8 RevF, AMD64 K8 RevG .sp .SH DESCRIPTION The library supports AMD K8 processors in both 32 and 64-bit modes. They correspond to processor family 15. .SH MODIFIERS The following modifiers are supported on AMD64 K8 processors: .TP .B u Measure at user level which includes privilege levels 1, 2, 3. This corresponds to \fBPFM_PLM3\fR. This is a boolean modifier. .TP .B k Measure at kernel level which includes privilege level 0. This corresponds to \fBPFM_PLM0\fR. This is a boolean modifier. .TP .B i Invert the meaning of the event. The counter will now count cycles in which the event is \fBnot\fR occurring. This is a boolean modifier .TP .B e Enable edge detection, i.e., count only when there is a state transition. This is a boolean modifier. .TP .B c Set the counter mask value. The mask acts as a threshold. The counter will count the number of cycles in which the number of occurrences of the event is greater or equal to the threshold. This is an integer modifier with values in the range [0:255]. .SH AUTHORS .nf Stephane Eranian Robert Richter .if .PP libpfm-4.9.0/docs/man3/libpfm_intel_bdx_unc_qpi.30000664000175000017500000000274413223402656021516 0ustar eranianeranian.TH LIBPFM 3 "June, 2017" "" "Linux Programmer's Manual" .SH NAME libpfm_intel_bdx_unc_qpi - support for Intel Broadwell Server QPI uncore PMU .SH SYNOPSIS .nf .B #include .sp .B PMU name: bdx_unc_qpi0, bdx_unc_qpi1 .B PMU desc: Intel Broadwell Server QPI uncore PMU .sp .SH DESCRIPTION The library supports the Intel Broadwell Server QPI uncore PMU. This PMU model only exists on various Broadwell server models (79, 86). .SH MODIFIERS The following modifiers are supported on Broadwell server QPI uncore PMU: .TP .B e Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one. This is a boolean modifier. .TP .B t Set the threshold value. When set to a non-zero value, the counter counts the number of QPI cycles in which the number of occurrences of the event is greater or equal to the threshold. This is an integer modifier with values in the range [0:255]. .TP .B i Invert the meaning of the threshold or edge filter. If set, the event counts when strictly less than N occurrences occur per cycle if threshold is set to N. When invert is set, then threshold must be set to non-zero value. If set, the event counts when the event transitions from occurring to not occurring (falling edge) when edge detection is set. This is a boolean modifier .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/libpfm_intel_p6.30000664000175000017500000000265213223402656017546 0ustar eranianeranian.TH LIBPFM 3 "September, 2009" "" "Linux Programmer's Manual" .SH NAME libpfm_intel_p6 - support for Intel P5 based processors .SH SYNOPSIS .nf .B #include .sp .B PMU name: pm, ppro, pii, piii, p6 .B PMU desc: Intel Pentium M, Intel Pentium Pro, Intel Pentium II, Intel Pentium III, Intel P6 .sp .SH DESCRIPTION The library supports all Intel P6-based processors all the way back to the Pentium Pro. Although all those processors offers the same PMU architecture, they differ in the events they provide. .SH MODIFIERS The following modifiers are supported on all Intel P6 processors: .TP .B u Measure at user level which includes privilege levels 1, 2, 3. This corresponds to \fBPFM_PLM3\fR. This is a boolean modifier. .TP .B k Measure at kernel level which includes privilege level 0. This corresponds to \fBPFM_PLM0\fR. This is a boolean modifier. .TP .B i Invert the meaning of the event. The counter will now count cycles in which the event is \fBnot\fR occurring. This is a boolean modifier .TP .B e Enable edge detection, i.e., count only when there is a state transition. This is a boolean modifier. .TP .B c Set the counter mask value. The mask acts as a threshold. The counter will count the number of cycles in which the number of occurrences of the event is greater or equal to the threshold. This is an integer modifier with values in the range [0:255]. .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/libpfm_intel_wsm_unc.30000664000175000017500000000246513223402656020676 0ustar eranianeranian.TH LIBPFM 3 "February, 2010" "" "Linux Programmer's Manual" .SH NAME libpfm_intel_wsm_unc \- support for Intel Westmere uncore PMU .SH SYNOPSIS .nf .B #include .sp .B PMU name: wsm_unc .B PMU desc: Intel Westmere uncore .sp .SH DESCRIPTION The library supports the Intel Westmere uncore PMU as implemented by processors such as Intel Core i7, and Intel Core i5 (models 37, 44). The PMU is located at the socket-level and is therefore shared between the various cores. By construction it can only measure at all privilege levels. .SH MODIFIERS The following modifiers are supported on Intel Westmere processors: .TP .B i Invert the meaning of the event. The counter will now count cycles in which the event is \fBnot\fR occurring. This is a boolean modifier .TP .B e Enable edge detection, i.e., count only when there is a state transition. This is a boolean modifier. .TP .B c Set the counter mask value. The mask acts as a threshold. The counter will count the number of cycles in which the number of occurrences of the event is greater or equal to the threshold. This is an integer modifier with values in the range [0:255]. .TP .B o Causes the queue occupancy counter associated with the event to be cleared (zeroed). This is a boolean modifier. .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/libpfm_intel_coreduo.30000664000175000017500000000274213223402656020661 0ustar eranianeranian.TH LIBPFM 3 "September, 2009" "" "Linux Programmer's Manual" .SH NAME libpfm_intel_coreduo - support for Intel Core Duo/Solo processors .SH SYNOPSIS .nf .B #include .sp .B PMU name: coreduo .B PMU desc: Intel Core Duo .sp .SH DESCRIPTION The library supports all Intel Yonah-based processors such as Intel Core Duo and Intel Core Solo processors. .SH MODIFIERS The following modifiers are supported on Intel Core Duo processors: .TP .B u Measure at user level which includes privilege levels 1, 2, 3. This corresponds to \fBPFM_PLM3\fR. This is a boolean modifier. .TP .B k Measure at kernel level which includes privilege level 0. This corresponds to \fBPFM_PLM0\fR. This is a boolean modifier. .TP .B i Invert the meaning of the event. The counter will now count cycles in which the event is \fBnot\fR occurring. This is a boolean modifier .TP .B e Enable edge detection, i.e., count only when there is a state transition. This is a boolean modifier. .TP .B c Set the counter mask value. The mask acts as a threshold. The counter will count the number of cycles in which the number of occurrences of the event is greater or equal to the threshold. This is an integer modifier with values in the range [0:255]. .SH ENVIRONMENT VARIABLES It is possible to force activation of the Intel Core Duo support using the \fBLIBPFM_FORCE_PMU\fR variable. The PMU name, coreduo, must be passed. No additional options are supported. .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/libpfm_intel_hswep_unc_sbo.30000664000175000017500000000350513223402656022055 0ustar eranianeranian.TH LIBPFM 3 "May, 2015" "" "Linux Programmer's Manual" .SH NAME libpfm_intel_hswep_unc_sbo - support for Intel Haswell-EP S-Box uncore PMU .SH SYNOPSIS .nf .B #include .sp .B PMU name: hswep_unc_sbo .B PMU desc: Intel Haswell-EP S-Box uncore PMU .sp .SH DESCRIPTION The library supports the Intel Haswell Rrint Transfer unit (S-Box) uncore PMU. This PMU model only exists on Haswell model 63. .SH MODIFIERS The following modifiers are supported on Intel Haswell S-Box uncore PMU: .TP .B e Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one. This is a boolean modifier. .TP .B t Set the threshold value. When set to a non-zero value, the counter counts the number of HA cycles in which the number of occurrences of the event is greater or equal to the threshold. This is an integer modifier with values in the range [0:15]. .TP .B i Invert the meaning of the threshold or edge filter. If set, the event counts when strictly less than N occurrences occur per cycle if threshold is set to N. When invert is set, then threshold must be set to non-zero value. If set, the event counts when the event transitions from occurring to not occurring (falling edge) when edge detection is set. This is a boolean modifier .TP .B i Invert the meaning of the threshold or edge filter. If set, the event counts when strictly less than N occurrences occur per cycle if threshold is set to N. When invert is set, then threshold must be set to non-zero value. If set, the event counts when the event transitions from occurring to not occurring (falling edge) when edge detection is set. This is a boolean modifier .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/libpfm_intel_snbep_unc_r3qpi.30000664000175000017500000000245113223402656022310 0ustar eranianeranian.TH LIBPFM 3 "August, 2012" "" "Linux Programmer's Manual" .SH NAME libpfm_intel_snbep_unc_r3qpi - support for Intel Sandy Bridge-EP R3QPI uncore PMU .SH SYNOPSIS .nf .B #include .sp .B PMU name: snbep_unc_r3qpi0, snbep_unc_r3qpi0 .B PMU desc: Intel Sandy Bridge-EP R3QPI uncore PMU .sp .SH DESCRIPTION The library supports the Intel Sandy Bridge R3QPI uncore PMU. This PMU model only exists on Sandy Bridge model 45. There are two R3QPI PMUs per processor socket. .SH MODIFIERS The following modifiers are supported on Intel Sandy Bridge R3PQI uncore PMU: .TP .B i Invert the meaning of the event. The counter will now count R3QPI cycles in which the event is \fBnot\fR occurring. This is a boolean modifier .TP .B e Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one. This is a boolean modifier. .TP .B t Set the threshold value. When set to a non-zero value, the counter counts the number of R3QPI cycles in which the number of occurrences of the event is greater or equal to the threshold. This is an integer modifier with values in the range [0:15]. .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/libpfm_intel_ivbep_unc_imc.30000664000175000017500000000217713223402656022025 0ustar eranianeranian.TH LIBPFM 3 "February, 2014" "" "Linux Programmer's Manual" .SH NAME libpfm_intel_ivbep_unc_imc - support for Intel Ivy Bridge-EP Integrated Memory Controller (IMC) uncore PMU .SH SYNOPSIS .nf .B #include .sp .B PMU name: ivbep_unc_imc[0-7] .B PMU desc: Intel Ivy Bridge-EP IMC uncore PMU .sp .SH DESCRIPTION The library supports the Intel Ivy Bridge Integrated Memory Controller (IMC) uncore PMU. This PMU model only exists on Ivy Bridge model 62. .SH MODIFIERS The following modifiers are supported on Intel Ivy Bridge C-Box uncore PMU: .TP .B e Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one. This is a boolean modifier. .TP .B t Set the threshold value. When set to a non-zero value, the counter counts the number of IMC cycles in which the number of occurrences of the event is greater or equal to the threshold. This is an integer modifier with values in the range [0:255]. .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/libpfm_arm_ac53.30000664000175000017500000000150413223402656017413 0ustar eranianeranian.TH LIBPFM 3 "May, 2014" "" "Linux Programmer's Manual" .SH NAME libpfm_arm_ac53 - support for ARM Cortex A53 PMU .SH SYNOPSIS .nf .B #include .sp .B PMU name: arm_ac53 .B PMU desc: ARM Cortex A53 .sp .SH DESCRIPTION The library supports the ARM Cortex A53 core PMU. This PMU supports 6 counters and privilege levels filtering. It can operate in both 32 and 64 bit modes. .SH MODIFIERS The following modifiers are supported on ARM Cortex A53: .TP .B u Measure at the user level. This corresponds to \fBPFM_PLM3\fR. This is a boolean modifier. .TP .B k Measure at the kernel level. This corresponds to \fBPFM_PLM0\fR. This is a boolean modifier. .TP .B hv Measure at the hypervisor level. This corresponds to \fBPFM_PLMH\fR. This is a boolean modifier. .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/libpfm_intel_hswep_unc_irp.30000664000175000017500000000263713223402656022071 0ustar eranianeranian.TH LIBPFM 3 "May, 2015" "" "Linux Programmer's Manual" .SH NAME libpfm_intel_hswep_unc_irp - support for Intel Haswell-EP IRP uncore PMU .SH SYNOPSIS .nf .B #include .sp .B PMU name: hswep_unc_irp .B PMU desc: Intel Haswell-EP IRP uncore PMU .sp .SH DESCRIPTION The library supports the Intel Haswell uncore PMU. This PMU model only exists on Haswell model 63. .SH MODIFIERS The following modifiers are supported on Intel Haswell IRP uncore PMU: .TP .B e Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one. This is a boolean modifier. .TP .B t Set the threshold value. When set to a non-zero value, the counter counts the number of cycles in which the number of occurrences of the event is greater or equal to the threshold. This is an integer modifier with values in the range [0:255]. .TP .B i Invert the meaning of the threshold or edge filter. If set, the event counts when strictly less than N occurrences occur per cycle if threshold is set to N. When invert is set, then threshold must be set to non-zero value. If set, the event counts when the event transitions from occurring to not occurring (falling edge) when edge detection is set. This is a boolean modifier .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/libpfm_intel_rapl.30000664000175000017500000000231013223402656020146 0ustar eranianeranian.TH LIBPFM 3 "November, 2013" "" "Linux Programmer's Manual" .SH NAME libpfm_intel_rapl - support for Intel RAPL PMU .SH SYNOPSIS .nf .B #include .sp .B PMU name: rapl .B PMU desc: Intel RAPL (Intel SandyBridge, IvyBridge, Haswell) .sp .SH DESCRIPTION The library supports the Intel Running Average Power Limit (RAPL) energy consumption counters. This is a socket-level set of counters which reports energy consumption in Joules. There are up to 3 counters each measuring only one event. The following events are defined: .TP .B RAPL_ENERGY_CORES On all processors, the event reports the number of Joules consumed by all cores. On all processors, .TP .B RAPL_ENERGYC_PKG On all processors, th event reports the number of Joules consumed by all the cores and Last Level cache (L3). .TP .B RAPL_ENERGY_DRAM On server processors, the event reports the number of Joules consumed n by the DRAM controller. By construction, the events are socket-level and can only be measured in system-wide mode. It is necessary and sufficient to measure only one CPU per socket to get meaningful results. .SH MODIFIERS The PMU does not support any modifiers. .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/libpfm_intel_hswep_unc_pcu.30000664000175000017500000000460513223402656022063 0ustar eranianeranian.TH LIBPFM 3 "May, 2015" "" "Linux Programmer's Manual" .SH NAME libpfm_intel_hswep_unc_pcu - support for Intel Haswell-EP Power Controller Unit (PCU) uncore PMU .SH SYNOPSIS .nf .B #include .sp .B PMU name: hswep_unc_pcu .B PMU desc: Intel Haswell-EP PCU uncore PMU .sp .SH DESCRIPTION The library supports the Intel Haswell Power Controller Unit uncore PMU. This PMU model only exists on Haswell model 63. .SH MODIFIERS The following modifiers are supported on Intel Haswell PCU uncore PMU: .TP .B e Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one. This is a boolean modifier. .TP .B t Set the threshold value. When set to a non-zero value, the counter counts the number of HA cycles in which the number of occurrences of the event is greater or equal to the threshold. This is an integer modifier with values in the range [0:15]. .TP .B i Invert the meaning of the threshold or edge filter. If set, the event counts when strictly less than N occurrences occur per cycle if threshold is set to N. When invert is set, then threshold must be set to non-zero value. If set, the event counts when the event transitions from occurring to not occurring (falling edge) when edge detection is set. This is a boolean modifier .TP .B ff Enable frequency band filtering. This modifier applies only to the UNC_P_FREQ_BANDx_CYCLES events, where x is [0-3]. The modifiers expects an integer in the range [0-255]. The value is interpreted as a frequency value to be multiplied by 100Mhz. Thus if the value is 32, then all cycles where the processor is running at 3.2GHz and more are counted. .SH Frequency band filtering There are 3 events which support frequency band filtering, namely, UNC_P_FREQ_BAND0_CYCLES, UNC_P_FREQ_BAND1_CYCLES, UNC_P_FREQ_BAND2_CYCLES, UNC_P_FREQ_BAND3_CYCLES. The frequency filter (available via the ff modifier) is stored into a PMU shared register which hold all 4 possible frequency bands, one per event. However, the library generate the encoding for each event individually because it processes events one at a time. The caller or the underlying kernel interface may have to merge the band filter settings to program the filter register properly. .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/libpfm_intel_hswep_unc_ha.30000664000175000017500000000271113223402656021660 0ustar eranianeranian.TH LIBPFM 3 "May, 2015" "" "Linux Programmer's Manual" .SH NAME libpfm_intel_hswep_unc_ha - support for Intel Haswell-EP Home Agent (HA) uncore PMU .SH SYNOPSIS .nf .B #include .sp .B PMU name: hswep_unc_ha0, hswep_unc_ha1 .B PMU desc: Intel Haswell-EP HA uncore PMU .sp .SH DESCRIPTION The library supports the Intel Haswell Home Agent (HA) uncore PMU. This PMU model only exists on Haswell model 63. .SH MODIFIERS The following modifiers are supported on Intel Haswell HA uncore PMU: .TP .B e Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one. This is a boolean modifier. .TP .B t Set the threshold value. When set to a non-zero value, the counter counts the number of HA cycles in which the number of occurrences of the event is greater or equal to the threshold. This is an integer modifier with values in the range [0:255]. .TP .B i Invert the meaning of the threshold or edge filter. If set, the event counts when strictly less than N occurrences occur per cycle if threshold is set to N. When invert is set, then threshold must be set to non-zero value. If set, the event counts when the event transitions from occurring to not occurring (falling edge) when edge detection is set. This is a boolean modifier .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/libpfm_intel_hswep_unc_cbo.30000664000175000017500000000721713223402656022041 0ustar eranianeranian.TH LIBPFM 3 "May, 2015" "" "Linux Programmer's Manual" .SH NAME libpfm_intel_hswep_unc_cbo - support for Intel Haswell-EP C-Box uncore PMU .SH SYNOPSIS .nf .B #include .sp .B PMU name: hswep_unc_cbo[0-17] .B PMU desc: Intel Haswell-EP C-Box uncore PMU .sp .SH DESCRIPTION The library supports the Intel Haswell C-Box (coherency engine) uncore PMU. This PMU model only exists on Haswell model 63. There is one C-box PMU per physical core. Therefore there are up to eighteen identical C-Box PMU instances numbered from 0 to 17. On dual-socket systems, the number refers to the C-Box PMU on the socket where the program runs. For instance, if running on CPU18, then hswep_unc_cbo0 refers to the C-Box for physical core 0 on socket 1. Conversely, if running on CPU0, then the same hswep_unc_cbo0 refers to the C-Box for physical core 0 but on socket 0. Each C-Box PMU implements 4 generic counters and two filter registers used only with certain events and umasks. .SH MODIFIERS The following modifiers are supported on Intel Haswell C-Box uncore PMU: .TP .B e Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one. This is a boolean modifier. .TP .B t Set the threshold value. When set to a non-zero value, the counter counts the number of C-Box cycles in which the number of occurrences of the event is greater or equal to the threshold. This is an integer modifier with values in the range [0:255]. .TP .B nf Node filter. Certain events, such as UNC_C_LLC_LOOKUP, UNC_C_LLC_VICTIMS, provide a \fBNID\fR umask. Sometimes the \fBNID\fR is combined with other filtering capabilities, such as opcodes. The node filter is an 8-bit max bitmask. A node corresponds to a processor socket. The legal values therefore depend on the underlying hardware configuration. For dual-socket systems, the bitmask has two valid bits [0:1]. .TP .B cf Core Filter. This is a 5-bit filter which is used to filter based on physical core origin of the C-Box request. Possible values are 0-63. If the filter is not specified, then no filtering takes place. Bit 0-3 indicate the physical core id and bit 4 filters on non thread-related data. .TP .B tf Thread Filter. This is a 1-bit filter which is used to filter C-Box requests based on logical processor (hyper-thread) identification. Possibles values are 0-1. If the filter is not specified, then no filtering takes place. .TP .B nc Non-Coherent. This is a 1-bit filter which is used to filter C-Box requests only for the TOR_INSERTS and TOR_OCCUPANCY umasks using the OPCODE matcher. If the filter is not specified, then no filtering takes place. .TP .B isoc Isochronous. This is a 1-bit filter which is used to filter C-Box requests only for the TOR_INSERTS and TOR_OCCUPANCY umasks using the OPCODE matcher. If the filter is not specified, then no filtering takes place. .SH Opcode filtering Certain events, such as UNC_C_TOR_INSERTS supports opcode matching on the C-BOX transaction type. To use this feature, first an opcode matching umask must be selected, e.g., MISS_OPCODE. Second, the opcode to match on must be selected via a second umask among the OPC_* umasks. For instance, UNC_C_TOR_INSERTS:OPCODE:OPC_RFO, counts the number of TOR insertions for RFO transactions. Opcode matching may be combined with node filtering with certain umasks. In general, the filtering support is encoded into the umask name, e.g., NID_OPCODE supports both node and opcode filtering. For instance, UNC_C_TOR_INSERTS:NID_OPCODE:OPC_RFO:nf=1. .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/libpfm_intel_bdx_unc_imc.30000664000175000017500000000303113223402656021463 0ustar eranianeranian.TH LIBPFM 3 "June, 2017" "" "Linux Programmer's Manual" .SH NAME libpfm_intel_bdx_unc_imc - support for Intel Broadwell Server Integrated Memory Controller (IMC) uncore PMU .SH SYNOPSIS .nf .B #include .sp .B PMU name: bdx_unc_imc[0-7] .B PMU desc: Intel Broadwell Server IMC uncore PMU .sp .SH DESCRIPTION The library supports the Intel Broadwell Server Integrated Memory Controller (IMC) uncore PMU. This PMU model only exists on various Broadwell server models (79, 86). .SH MODIFIERS The following modifiers are supported on Intel Broadwell server IMC uncore PMU: .TP .B e Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one. This is a boolean modifier. .TP .B t Set the threshold value. When set to a non-zero value, the counter counts the number of IMC cycles in which the number of occurrences of the event is greater or equal to the threshold. This is an integer modifier with values in the range [0:255]. .B i Invert the meaning of the threshold or edge filter. If set, the event counts when strictly less than N occurrences occur per cycle if threshold is set to N. When invert is set, then threshold must be set to non-zero value. If set, the event counts when the event transitions from occurring to not occurring (falling edge) when edge detection is set. This is a boolean modifier .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/pfm_get_event_encoding.30000664000175000017500000001057513223402656021170 0ustar eranianeranian.TH LIBPFM 3 "September, 2009" "" "Linux Programmer's Manual" .SH NAME pfm_get_event_encoding \- get raw event encoding .SH SYNOPSIS .nf .B #include .sp .BI "int pfm_get_event_encoding(const char *" str ",int " dfl_plm ", char **" fstr ", int *" idx ", uint64_t *"code ", int *" count ");" .sp .SH DESCRIPTION This function is used to retrieve the raw event encoding corresponding to the event string in \fBstr\fR. Only one event per call can be encoded. As such, \fBstr\fR can contain only one symbolic event name. The string may contain unit masks and modifiers. The default privilege level mask is passed in \fBdfl_plm\fR. It may be used depending on the event. This function is \fBdeprecated\fR. It is superseded by \fBpfm_get_os_event_encoding()\fR where the OS is set to \fBPFM_OS_NONE\fR. Encoding is retrieve through the \fBpfm_pmu_encode_arg_t\fR structure. The following examples illustrates the transition: .nf int i, count = 0; uint64_t *codes; ret = pfm_get_event_encoding("RETIRED_INSTRUCTIONS", PFM_PLM3, NULL, &codes, &count); if (ret != PFM_SUCCESS) err(1", cannot get encoding %s", pfm_strerror(ret)); for(i=0; i < count; i++) printf("count[%d]=0x%"PRIx64"\\n", i, codes[i]); .fi is equivalent to: .nf pfm_pmu_encode_arg_t arg; int i; memset(&arg, 0, sizeof(arg)); arg.size = sizeof(arg); ret = pfm_get_os_event_encoding("RETIRED_INSTRUCTIONS", PFM_PLM3, PFM_OS_NONE, &arg); if (ret != PFM_SUCCESS) err(1", cannot get encoding %s", pfm_strerror(ret)); for(i=0; i < arg.count; i++) printf("count[%d]=0x%"PRIx64"\\n", i, arg.codes[i]); free(arg.codes); .nf The encoding may take several 64-bit integers. The function can use the array passed in \fBcode\fR if the number of entries passed in \fBcount\fR is big enough. However, if both \fB*codes\fR is \fBNULL\fR and \fBcount\fR is 0, the function allocates the memory necessary to store the encoding. It is up to the caller to eventually free the memory. The number of 64-bit entries in \fBcodes\fR is reflected in \fB*count\fR upon return regardless of whether the \fBcodes\fR was allocated or used as is. If the number of 64-bit integers is greater than one, then the order in which each component is returned is PMU-model specific. Refer to the PMU specific man page. The raw encoding means the encoding as mandated by the underlying PMU model. It may not be directly suitable to pass to a kernel API. You may want to use API-specific library calls to ensure the correct encoding is passed. If \fBfstr\fR is not NULL, it will point to the fully qualified event string upon successful return. The string contains the event name, any umask set, and the value of all the modifiers. It reflects what the encoding will actually measure. The function allocates the memory to store the string. The caller must eventually free the string. Here is a example of how this function could be used: .nf #include #include #include int main(int argc, char **argv) { uint64_t *codes 0; int count = 0; int ret; ret = pfm_initialize(); if (ret != PFMLIB_SUCCESS) err(1", cannot initialize library %s", pfm_strerror(ret)); ret = pfm_get_event_encoding("RETIRED_INSTRUCTIONS", PFM_PLM3, NULL, &codes, &count); if (ret != PFM_SUCCESS) err(1", cannot get encoding %s", pfm_strerror(ret)); for(i=0; i < count; i++) printf("count[%d]=0x%"PRIx64"\\n", i, codes[i]); free(codes); return 0; } .fi .SH RETURN The function returns in \fB*codes\fR the encoding of the event and in \fB*count\fR the number of 64-bit integers to support that encoding. Upon success, \fBPFM_SUCCESS\fR is returned otherwise a specific error code is returned. .SH ERRORS .TP .B PFM_ERR_TOOSMALL The \fBcode\fR argument is too small for the encoding. .TP .B PFM_ERR_INVAL The \fBcode\fR or \fBcount\fR argument is \fBNULL\fR or the \fBstr\fR contains more than one symbolic event. .TP .B PFM_ERR_NOMEM Not enough memory. .TP .B PFM_ERR_NOTFOUND Event not found. .TP .B PFM_ERR_ATTR Invalid event attribute (unit mask or modifier) .TP .B PFM_ERR_ATTR_VAL Invalid modifier value. .TP .B PFM_ERR_ATTR_SET attribute already set, cannot be changed. .TP .B PFM_ERR_ATTR_UMASK Missing unit mask. .TP .B PFM_ERR_ATTR_FEATCOMB Unit masks or features cannot be combined into a single event. .SH AUTHOR Stephane Eranian .SH SEE ALSO pfm_get_os_event_encoding(3) libpfm-4.9.0/docs/man3/libpfm_intel_ivbep_unc_ubo.30000664000175000017500000000213313223402656022032 0ustar eranianeranian.TH LIBPFM 3 "February, 2014" "" "Linux Programmer's Manual" .SH NAME libpfm_intel_ivbep_unc_ubo - support for Intel Ivy Bridge-EP U-Box uncore PMU .SH SYNOPSIS .nf .B #include .sp .B PMU name: ivbep_unc_ubo .B PMU desc: Intel Ivy Bridge-EP U-Box uncore PMU .sp .SH DESCRIPTION The library supports the Intel Ivy Bridge system configuration unit (U-Box) uncore PMU. This PMU model only exists on Ivy Bridge model 62. .SH MODIFIERS The following modifiers are supported on Intel Ivy Bridge U-Box uncore PMU: .TP .B e Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one. This is a boolean modifier. .TP .B t Set the threshold value. When set to a non-zero value, the counter counts the number of HA cycles in which the number of occurrences of the event is greater or equal to the threshold. This is an integer modifier with values in the range [0:15]. .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/libpfm_intel_hswep_unc_r3qpi.30000664000175000017500000000267213223402656022334 0ustar eranianeranian.TH LIBPFM 3 "May, 2015" "" "Linux Programmer's Manual" .SH NAME libpfm_intel_hswep_unc_r3qpi - support for Intel Haswell-EP R3QPI uncore PMU .SH SYNOPSIS .nf .B #include .sp .B PMU name: hswep_unc_r3qpi[0-2] .B PMU desc: Intel Haswell-EP R3QPI uncore PMU .sp .SH DESCRIPTION The library supports the Intel Haswell R3QPI uncore PMU. This PMU model only exists on Haswell model 63. .SH MODIFIERS The following modifiers are supported on Intel Haswell R3PQI uncore PMU: .TP .B e Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one. This is a boolean modifier. .TP .B t Set the threshold value. When set to a non-zero value, the counter counts the number of R3QPI cycles in which the number of occurrences of the event is greater or equal to the threshold. This is an integer modifier with values in the range [0:15]. .TP .B i Invert the meaning of the threshold or edge filter. If set, the event counts when strictly less than N occurrences occur per cycle if threshold is set to N. When invert is set, then threshold must be set to non-zero value. If set, the event counts when the event transitions from occurring to not occurring (falling edge) when edge detection is set. This is a boolean modifier .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/pfm_get_event_attr_info.30000664000175000017500000001407513223402656021366 0ustar eranianeranian.TH LIBPFM 3 "December, 2009" "" "Linux Programmer's Manual" .SH NAME pfm_get_event_attr_info \- get event attribute information .SH SYNOPSIS .nf .B #include .sp .BI "int pfm_get_event_attr_info(int " idx ", int " attr ", pfm_os_t " os ", pfm_event_attr_info_t *" info ");" .sp .SH DESCRIPTION This function returns in \fBinfo\fR information about the attribute designated by \fBattr\fR for the event specified in \fBidx\fR and the os layer in \fBos\fR. The \fBpfm_os_t\fR enumeration provides the following choices: .TP .B PFM_OS_NONE The returned information pertains only to what the PMU hardware exports. No operating system attributes is taken into account. .TP .B PFM_OS_PERF_EVENT The returned information includes the actual PMU hardware and the additional attributes exported by the perf_events kernel interface. The perf_event attributes pertain only the PMU hardware. In case perf_events is not detected, an error is returned. .TP .B PFM_OS_PERF_EVENT_EXT The returned information includes all of what is already provided by \fBPFM_OS_PERF_EVENT\fR plus all the software attributes controlled by perf_events, such as sampling period, precise sampling. .PP The \fBpfm_event_attr_info_t\fR structure is defined as follows: .nf typedef struct { const char *name; const char *desc; const char *equiv; size_t size; uint64_t code; pfm_attr_t type; int idx; pfm_attr_ctrl_t ctrl; int reserved1; struct { int is_dfl:1; int is_precise:1; int reserved:30; }; union { uint64_t dfl_val64; const char *dfl_str; int dfl_bool; int dfl_int; }; } pfm_event_attr_info_t; .fi The fields of this structure are defined as follows: .TP .B name This is the name of the attribute. This is a read-only string. .TP .B desc This is the description of the attribute. This is a read-only string. It may contain multiple sentences. .TP .B equiv Certain attributes may be just variations of other attributes for the same event. They may be provided as handy shortcuts to avoid supplying a long list of attributes. For those attributes, this field is not NULL and contains the complete equivalent attribute string. This string, once appended to the event name, may be used library calls requiring an event string. .TP .B code This is the raw attribute code. For PFM_ATTR_UMASK, this is the unit mask code. For all other attributes, this is an opaque index. .TP .B type This is the type of the attribute. Attributes represent either sub-events or extra filters that can be applied to the event. Filters (also called modifiers) may be tied to the event or the PMU register the event is programmed into. The type of an attribute determines how it must be specified. The following types are defined: .RS .TP .B PFM_ATTR_UMASK This is a unit mask, i.e., a sub-event. It is specified using its name. Depending on the event, it may be possible to specify multiple unit masks. .TP .B PFM_ATTR_MOD_BOOL This is a boolean attribute. It has a value of 0, 1, y or n. The value is specified after the equal sign, e.g., foo=1. As a convenience, the equal sign and value may be omitted, in which case this is equivalent to =1. .TP .B PFM_ATTR_MOD_INTEGER This is an integer attribute. It has a value which must be passed after the equal sign. The range of valid values depends on the attribute and is usually specified in its description. .PP .RE .TP .B idx This is the attribute index. It is identical to the value of \fBattr\fR passed to the call and is provided for completeness. .TP .B size This field contains the size of the struct passed. This field is used to provide for extensibility of the struct without compromising backward compatibility. The value should be set to \fBsizeof(pfm_event_attr_info_t)\fR. If instead, a value of \fB0\fR is specified, the library assumes the struct passed is identical to the first ABI version which size is \fBPFM_ATTR_INFO_ABI0\fR. Thus, if fields were added after the first ABI, they will not be set by the library. The library does check that bytes beyond what is implemented are zeroes. .TP .B is_dfl This field indicates whether or not this attribute is set by default. This applies mostly for PFM_ATTR_UMASK. If a unit mask is marked as default, and no unit mask is specified in the event string, then the library uses it by default. Note that there may be multiple defaults per event depending on how unit masks are grouped. .TP .B is_precise This field indicates whether or not this umask supports precise sampling. Precise sampling is a hardware mechanism that avoids instruction address skid when using interrupt-based sampling. On Intel X86 processors, this field indicates that the umask supports Precise Event-Based Sampling (PEBS). .TP .B dfl_val64, dfl_str, dfl_bool, dfl_int This union contains the value of an attribute. For PFM_ATTR_UMASK, the is the unit mask code, for all other types this is the actual value of the attribute. .TP .B ctrl This field indicates which layer or source controls the attribute. The following sources are defined: .RS .TP .B PFM_ATTR_CTRL_UNKNOWN The source controlling the attribute is not known. .TP .B PFM_ATTR_CTRL_PMU The attribute is controlled by the PMU hardware. .TP .B PFM_ATTR_CTRL_PERF_EVENT The attribute is controlled by the perf_events kernel interface. .RE .TP .B reserved These fields must be set to zero. .PP .SH RETURN If successful, the function returns \fBPFM_SUCCESS\fR and attribute information in \fBinfo\fR, otherwise it returns an error code. .SH ERRORS .TP .B PFMLIB_ERR_NOINIT Library has not been initialized properly. .TP .B PFMLIB_ERR_INVAL The \fBidx\fR or \fBattr\fR arguments are invalid or \fBinfo\fR is \fBNULL\fR or \fBsize\fR is not zero. .TP .B PFM_ERR_NOTSUPP The requested os layer has not been detected on the host system. .SH AUTHOR Stephane Eranian .PP libpfm-4.9.0/docs/man3/libpfm_intel_bdx_unc_irp.30000664000175000017500000000274413223402656021517 0ustar eranianeranian.TH LIBPFM 3 "June, 2017" "" "Linux Programmer's Manual" .SH NAME libpfm_intel_bdx_unc_irp - support for Intel Broadwell Server IRP uncore PMU .SH SYNOPSIS .nf .B #include .sp .B PMU name: bdx_unc_irp .B PMU desc: Intel Broadwell Server IRP uncore PMU .sp .SH DESCRIPTION The library supports the Intel Broadwell Server IRP (IIO coherency) uncore PMU . This PMU model only exists various Broadwell server models (79, 86). .SH MODIFIERS The following modifiers are supported on Intel Broadwell server IRP uncore PMU: .TP .B e Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one. This is a boolean modifier. .TP .B t Set the threshold value. When set to a non-zero value, the counter counts the number of cycles in which the number of occurrences of the event is greater or equal to the threshold. This is an integer modifier with values in the range [0:255]. .TP .B i Invert the meaning of the threshold or edge filter. If set, the event counts when strictly less than N occurrences occur per cycle if threshold is set to N. When invert is set, then threshold must be set to non-zero value. If set, the event counts when the event transitions from occurring to not occurring (falling edge) when edge detection is set. This is a boolean modifier .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/libpfm_arm_ac8.30000664000175000017500000000070213223402656017332 0ustar eranianeranian.TH LIBPFM 3 "August, 2012" "" "Linux Programmer's Manual" .SH NAME libpfm_arm_ac8 - support for ARM Cortex A8 PMU .SH SYNOPSIS .nf .B #include .sp .B PMU name: arm_ac8 .B PMU desc: ARM Cortex A8 .sp .SH DESCRIPTION The library supports the ARM Cortex A8 core PMU. This PMU supports 2 counters and has no privilege levels filtering. No event modifiers are available. .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/pfm_get_pmu_info.30000664000175000017500000001064213223402656020010 0ustar eranianeranian.TH LIBPFM 3 "December, 2009" "" "Linux Programmer's Manual" .SH NAME pfm_get_pmu_info \- get PMU information .SH SYNOPSIS .nf .B #include .sp .BI "int pfm_get_pmu_info(pfm_pmu_t " pmu ", pfm_pmu_info_t *" info ");" .sp .SH DESCRIPTION This function returns in \fBinfo\fR information about a PMU model designated by its identifier in \fBpmu\fR. The \fBpfm_pmu_info\fR structure is defined as follows: .nf typedef struct { const char *name; const char *desc; pfm_pmu_t pmu; pfm_pmu_type_t type; int size; int nevents; int first_event; int max_encoding; int num_cntrs; int num_fixed_cntrs; struct { int is_present:1; int is_arch_default:1; int is_core:1; int is_uncore:1; int reserved:28; }; } pfm_pmu_info_t; .fi The fields of this structure are defined as follows: .TP .B name This is the symbolic name of the PMU. This name can be used as a prefix in an event string. This is a read-only string. .TP .B desc This is the description of PMU. This is a read-only string. .TP .B pmu This is the unique PMU identification code. It is identical to the value passed in \fBpmu\fR and it provided only for completeness. .TP .B type This field contains the type of the PMU. The following types are defined: .RS .TP .B PFM_PMU_TYPE_UNKNOWN The type of the PMU could not be determined. .TP .B PFM_PMU_TYPE_CORE This field is set to one when the PMU is implemented by the processor core. .TP .B PFM_PMU_TYPE_UNCORE This field is set to one when the PMU is implemented on the processor die but at the socket level, i.e., capturing events for all cores. .PP .RE .TP .B nevents This is the number of available events for this PMU model based on the host processor. It is \fBonly\fR valid if the \fBis_present\fR field is set to 1. Event identifiers are not guaranteed contiguous. In other words, it is not because \fBnevents\fR is equal to 100, that event identifiers go from 0 to 99. The iterator function \fBpfm_get_event_next()\fR must be used to go from one identifier to the next. .TP .B first_event This field returns the opaque index of the first event for this PMU model. The index can be used with \fBpfm_get_event_info()\fR or \fBpfm_get_event_next()\fR functions. In case no event is available, this field contains \fB-1\fR. .TP .B num_cntrs This field contains the number of generic counters supported by the PMU. A counter is generic if it can count more than one event. When it is not possible to determine the number of generic counters, this field contains \fb-1\fR. .TP .B num_fixed_cntrs This field contains the number of fixed counters supported by the PMU. A counter is fixed if it hardwired to count only one event. When it is not possible to determine the number of generic counters, this field contains \fb-1\fR. .TP .B size This field contains the size of the struct passed. This field is used to provide for extensibility of the struct without compromising backward compatibility. The value should be set to \fBsizeof(pfm_pmu_info_t)\fR. If instead, a value of \fB0\fR is specified, the library assumes the struct passed is identical to the first ABI version which size is \fBPFM_PMU_INFO_ABI0\fR. Thus, if fields were added after the first ABI, they will not be set by the library. The library does check that bytes beyond what is implemented are zeroes. .TP .B max_encoding This field returns the number of event codes returned by \fBpfm_get_event_encoding()\fR. .TP .B is_present This field is set to one is the PMU model has been detected on the host system. .TP .B is_dfl This field is set to one if the PMU is the default PMU for this architecture. Otherwise this field is zero. .PP .SH RETURN If successful, the function returns \fBPFM_SUCCESS\fR and PMU information in \fBinfo\fR, otherwise it returns an error code. .SH ERRORS .TP .B PFMLIB_ERR_NOINIT Library has not been initialized properly. .TP .B PFMLIB_ERR_NOTSUPP PMU model is not supported by the library. .TP .B PFMLIB_ERR_INVAL The \fBpmu\fR argument is invalid or \fBinfo\fR is \fBNULL\fR or \fBsize\fR is not zero. .SH SEE ALSO pfm_get_event_next(3) .SH AUTHOR Stephane Eranian .PP libpfm-4.9.0/docs/man3/libpfm_intel_hswep_unc_qpi.30000664000175000017500000000270013223402656022057 0ustar eranianeranian.TH LIBPFM 3 "May , 2015" "" "Linux Programmer's Manual" .SH NAME libpfm_intel_hswep_unc_qpi - support for Intel Haswell-EP QPI uncore PMU .SH SYNOPSIS .nf .B #include .sp .B PMU name: hswep_unc_qpi0, hswep_unc_qpi1 .B PMU desc: Intel Haswell-EP QPI uncore PMU .sp .SH DESCRIPTION The library supports the Intel Haswell Power QPI uncore PMU. This PMU model only exists on Haswell model 63. .SH MODIFIERS The following modifiers are supported on Haswell Bridge QPI uncore PMU: .TP .B e Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one. This is a boolean modifier. .TP .B t Set the threshold value. When set to a non-zero value, the counter counts the number of QPI cycles in which the number of occurrences of the event is greater or equal to the threshold. This is an integer modifier with values in the range [0:255]. .TP .B i Invert the meaning of the threshold or edge filter. If set, the event counts when strictly less than N occurrences occur per cycle if threshold is set to N. When invert is set, then threshold must be set to non-zero value. If set, the event counts when the event transitions from occurring to not occurring (falling edge) when edge detection is set. This is a boolean modifier .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/libpfm_intel_wsm.30000664000175000017500000000604013223402656020022 0ustar eranianeranian.TH LIBPFM 3 "September, 2009" "" "Linux Programmer's Manual" .SH NAME libpfm_intel_wsm - support for Intel Westmere core PMU .SH SYNOPSIS .nf .B #include .sp .B PMU name: wsm .B PMU desc: Intel Westmere .B PMU name: wsm_dp .B PMU desc: Intel Westmere DP .sp .SH DESCRIPTION The library supports the Intel Westmere core PMU. It should be noted that this PMU model only covers the each core's PMU and not the socket level PMU. It is provided separately. Support is provided for the Intel Core i7 and Core i5 processors (models 37, 44). .SH MODIFIERS The following modifiers are supported on Intel Westmere processors: .TP .B u Measure at user level which includes privilege levels 1, 2, 3. This corresponds to \fBPFM_PLM3\fR. This is a boolean modifier. .TP .B k Measure at kernel level which includes privilege level 0. This corresponds to \fBPFM_PLM0\fR. This is a boolean modifier. .TP .B i Invert the meaning of the event. The counter will now count cycles in which the event is \fBnot\fR occurring. This is a boolean modifier .TP .B e Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a counter mask modifier (m) with a value greater or equal to one. This is a boolean modifier. .TP .B c Set the counter mask value. The mask acts as a threshold. The counter will count the number of cycles in which the number of occurrences of the event is greater or equal to the threshold. This is an integer modifier with values in the range [0:255]. .TP .B t Measure on both threads at the same time assuming hyper-threading is enabled. This is a boolean modifier. .TP .B ldlat Pass a latency threshold to the MEM_INST_RETIRED:LATENCY_ABOVE_THRESHOLD event. This is an integer attribute that must be in the range [3:65535]. It is required for this event. Note that the event must be used with precise sampling (PEBS). .SH OFFCORE_RESPONSE events The library is able to encode the OFFCORE_RESPONSE_0 and OFFCORE_RESPONSE_1 events. Those are special events because they, each, need a second MSR (0x1a6 and 0x1a7 respectively) to be programmed for the event to count properly. Thus two values are necessary for each event. The first value can be programmed on any of the generic counters. The second value goes into the dedicated MSR (0x1a6 or 0x1a7). The OFFCORE_RESPONSE events are exposed as normal events with several umasks which are divided in two groups: request and response. The user must provide \fBat least\fR one umask from each group. For instance, OFFCORE_RESPONSE_0:ANY_DATA:LOCAL_DRAM. When using \fBpfm_get_event_encoding()\fR, two 64-bit values are returned. The first value corresponds to what needs to be programmed into any of the generic counters. The second value must be programmed into the corresponding dedicated MSR (0x1a6 or 0x1a7). When using an OS-specific encoding routine, the way the event is encoded is OS specific. Refer to the corresponding man page for more information. .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/docs/man3/libpfm_intel_bdx_unc_ubo.30000664000175000017500000000277413223402656021515 0ustar eranianeranian.TH LIBPFM 3 "June, 2017" "" "Linux Programmer's Manual" .SH NAME libpfm_intel_bdx_unc_ubo - support for Intel Broadwell Server U-Box uncore PMU .SH SYNOPSIS .nf .B #include .sp .B PMU name: bdx_unc_ubo .B PMU desc: Intel Broadwell Server U-Box uncore PMU .sp .SH DESCRIPTION The library supports the Intel Broadwell server system configuration unit (U-Box) uncore PMU. This PMU model only exists on various Broadwell server models (79, 86). .SH MODIFIERS The following modifiers are supported on Intel Broadwell server U-Box uncore PMU: .TP .B e Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one. This is a boolean modifier. .TP .B t Set the threshold value. When set to a non-zero value, the counter counts the number of HA cycles in which the number of occurrences of the event is greater or equal to the threshold. This is an integer modifier with values in the range [0:15]. .TP .B i Invert the meaning of the threshold or edge filter. If set, the event counts when strictly less than N occurrences occur per cycle if threshold is set to N. When invert is set, then threshold must be set to non-zero value. If set, the event counts when the event transitions from occurring to not occurring (falling edge) when edge detection is set. This is a boolean modifier .SH AUTHORS .nf Stephane Eranian .if .PP libpfm-4.9.0/config.mk0000664000175000017500000001311713223402656014417 0ustar eranianeranian# # Copyright (c) 2002-2006 Hewlett-Packard Development Company, L.P. # Contributed by Stephane Eranian # # Permission is hereby granted, free of charge, to any person obtaining a copy # of this software and associated documentation files (the "Software"), to deal # in the Software without restriction, including without limitation the rights # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies # of the Software, and to permit persons to whom the Software is furnished to do so, # subject to the following conditions: # # The above copyright notice and this permission notice shall be included in all # copies or substantial portions of the Software. # # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, # INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A # PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT # HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF # CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE # OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # # This file is part of libpfm, a performance monitoring support library for # applications on Linux. # # # This file defines the global compilation settings. # It is included by every Makefile # # SYS := $(shell uname -s) ARCH := $(shell uname -m) ifeq (i686,$(findstring i686,$(ARCH))) override ARCH=i386 endif ifeq (i586,$(findstring i586,$(ARCH))) override ARCH=i386 endif ifeq (i486,$(findstring i486,$(ARCH))) override ARCH=i386 endif ifeq (i386,$(findstring i386,$(ARCH))) override ARCH=i386 endif ifeq (i86pc,$(findstring i86pc,$(ARCH))) override ARCH=i386 endif ifeq (x86,$(findstring x86,$(ARCH))) override ARCH=x86_64 endif ifeq ($(ARCH),x86_64) override ARCH=x86_64 endif ifeq ($(ARCH),amd64) override ARCH=x86_64 endif ifeq (ppc,$(findstring ppc,$(ARCH))) override ARCH=powerpc endif ifeq (sparc64,$(findstring sparc64,$(ARCH))) override ARCH=sparc endif ifeq (armv6,$(findstring armv6,$(ARCH))) override ARCH=arm endif ifeq (armv7,$(findstring armv7,$(ARCH))) override ARCH=arm endif ifeq (armv7,$(findstring armv7,$(ARCH))) override ARCH=arm endif ifeq (aarch32,$(findstring aarch32,$(ARCH))) override ARCH=arm endif ifeq (armv8l,$(findstring armv8l,$(ARCH))) override ARCH=arm endif ifeq (mips64,$(findstring mips64,$(ARCH))) override ARCH=mips endif ifeq (mips,$(findstring mips,$(ARCH))) override ARCH=mips endif ifeq (MINGW,$(findstring MINGW,$(SYS))) override SYS=WINDOWS endif # # CONFIG_PFMLIB_SHARED: y=compile static and shared versions, n=static only # CONFIG_PFMLIB_DEBUG: enable debugging output support # CONFIG_PFMLIB_NOPYTHON: do not generate the python support, incompatible # with PFMLIB_SHARED=n # CONFIG_PFMLIB_SHARED?=y CONFIG_PFMLIB_DEBUG?=y CONFIG_PFMLIB_NOPYTHON?=y # # Cell Broadband Engine is reported as PPC but needs special handling. # ifeq ($(SYS),Linux) MACHINE := $(shell grep -q 'Cell Broadband Engine' /proc/cpuinfo && echo cell) ifeq (cell,$(MACHINE)) override ARCH=cell endif endif # # Library version # VERSION=4 REVISION=9 AGE=0 # # Where should things (lib, headers, man) go in the end. # PREFIX=/usr/local LIBDIR=$(PREFIX)/lib INCDIR=$(PREFIX)/include MANDIR=$(PREFIX)/share/man DOCDIR=$(PREFIX)/share/doc/libpfm-$(VERSION).$(REVISION).$(AGE) # # System header files # # SYSINCDIR : where to find standard header files (default to .) SYSINCDIR=. # # Configuration Paramaters for libpfm library # ifeq ($(ARCH),ia64) CONFIG_PFMLIB_ARCH_IA64=y endif ifeq ($(ARCH),x86_64) CONFIG_PFMLIB_ARCH_X86_64=y CONFIG_PFMLIB_ARCH_X86=y endif ifeq ($(ARCH),i386) CONFIG_PFMLIB_ARCH_I386=y CONFIG_PFMLIB_ARCH_X86=y endif ifeq ($(ARCH),mips) CONFIG_PFMLIB_ARCH_MIPS=y endif ifeq ($(ARCH),powerpc) CONFIG_PFMLIB_ARCH_POWERPC=y endif ifeq ($(ARCH),sparc) CONFIG_PFMLIB_ARCH_SPARC=y endif ifeq ($(ARCH),arm) CONFIG_PFMLIB_ARCH_ARM=y endif ifeq ($(ARCH),aarch64) CONFIG_PFMLIB_ARCH_ARM64=y endif ifeq ($(ARCH),arm64) CONFIG_PFMLIB_ARCH_ARM64=y endif ifeq ($(ARCH),s390x) CONFIG_PFMLIB_ARCH_S390X=y endif ifeq ($(ARCH),cell) CONFIG_PFMLIB_CELL=y endif # # you shouldn't have to touch anything beyond this point # # # The entire package can be compiled using # icc the Intel Itanium Compiler (7.x,8.x, 9.x) # or GNU C #CC=icc CC?=gcc LIBS= INSTALL=install LDCONFIG=ldconfig LN?=ln -sf PFMINCDIR=$(TOPDIR)/include PFMLIBDIR=$(TOPDIR)/lib # # -Wextra: to enable extra compiler sanity checks (e.g., signed vs. unsigned) # -Wno-unused-parameter: to avoid warnings on unused foo(void *this) parameter # DBG?=-g -Wall -Werror -Wextra -Wno-unused-parameter ifeq ($(SYS),Darwin) # older gcc-4.2 does not like -Wextra and some of our initialization code # Xcode uses a gcc version which is too old for some static initializers CC=clang DBG?=-g -Wall -Werror LDCONFIG=true endif ifeq ($(SYS),FreeBSD) # gcc-4.2 does not like -Wextra and some of our initialization code DBG=-g -Wall -Werror endif CFLAGS+=$(OPTIM) $(DBG) -I$(SYSINCDIR) -I$(PFMINCDIR) MKDEP=makedepend PFMLIB=$(PFMLIBDIR)/libpfm.a ifeq ($(CONFIG_PFMLIB_DEBUG),y) CFLAGS += -DCONFIG_PFMLIB_DEBUG endif CTAGS?=ctags # # Python is for use with perf_events # so it only works on Linux # ifneq ($(SYS),Linux) CONFIG_PFMLIB_NOPYTHON=y endif # # mark that we are compiling on Linux # ifeq ($(SYS),Linux) CFLAGS+= -DCONFIG_PFMLIB_OS_LINUX endif # # compile examples statically if library is # compile static # not compatible with python support, so disable for now # ifeq ($(CONFIG_PFMLIB_SHARED),n) LDFLAGS+= -static CONFIG_PFMLIB_NOPYTHON=y endif ifeq ($(SYS),WINDOWS) CFLAGS +=-DPFMLIB_WINDOWS endif libpfm-4.9.0/examples/0000775000175000017500000000000013223402656014434 5ustar eranianeranianlibpfm-4.9.0/examples/Makefile0000664000175000017500000000412713223402656016100 0ustar eranianeranian# # Copyright (c) 2002-2006 Hewlett-Packard Development Company, L.P. # Contributed by Stephane Eranian # # Permission is hereby granted, free of charge, to any person obtaining a copy # of this software and associated documentation files (the "Software"), to deal # in the Software without restriction, including without limitation the rights # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies # of the Software, and to permit persons to whom the Software is furnished to do so, # subject to the following conditions: # # The above copyright notice and this permission notice shall be included in all # copies or substantial portions of the Software. # # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, # INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A # PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT # HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF # CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE # OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # TOPDIR := $(shell if [ "$$PWD" != "" ]; then echo $$PWD; else pwd; fi)/.. include $(TOPDIR)/config.mk include $(TOPDIR)/rules.mk CFLAGS+= -I. -D_GNU_SOURCE LIBS += -lm ifeq ($(SYS),Linux) CFLAGS+= -pthread LIBS += -lrt endif ifeq ($(SYS),WINDOWS) LIBS += -lgnurx endif TARGETS=showevtinfo check_events EXAMPLESDIR=$(DESTDIR)$(DOCDIR)/examples all: $(TARGETS) @set -e ; for d in $(DIRS) ; do $(MAKE) -C $$d $@ ; done $(TARGETS): %:%.o $(PFMLIB) $(CC) $(CFLAGS) -o $@ $(LDFLAGS) $^ $(LIBS) clean: @set -e ; for d in $(DIRS) ; do $(MAKE) -C $$d $@ ; done $(RM) -f *.o $(TARGETS) *~ distclean: clean install_examples: $(TARGETS) @echo installing: $(TARGETS) -mkdir -p $(EXAMPLESDIR) $(INSTALL) -m 755 $(TARGETS) $(EXAMPLESDIR) @set -e ; for d in $(DIRS) ; do $(MAKE) -C $$d $@ ; done # # examples are installed as part of the RPM install, typically in /usr/share/doc/libpfm-X.Y/ # .PHONY: install depend install_examples libpfm-4.9.0/examples/showevtinfo.c0000664000175000017500000005023113223402656017154 0ustar eranianeranian/* * showevtinfo.c - show event information * * Copyright (c) 2010 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. */ #include #include #include #include #include #include #include #include #include #include #include #define MAXBUF 1024 #define COMBO_MAX 18 static struct { int compact; int sort; uint8_t encode; uint8_t combo; uint8_t combo_lim; uint8_t name_only; uint8_t desc; char *csv_sep; pfm_event_info_t efilter; pfm_event_attr_info_t ufilter; pfm_os_t os; uint64_t mask; } options; typedef struct { uint64_t code; int idx; } code_info_t; static void show_event_info_compact(pfm_event_info_t *info); static const char *srcs[PFM_ATTR_CTRL_MAX]={ [PFM_ATTR_CTRL_UNKNOWN] = "???", [PFM_ATTR_CTRL_PMU] = "PMU", [PFM_ATTR_CTRL_PERF_EVENT] = "perf_event", }; #ifdef PFMLIB_WINDOWS int set_env_var(const char *var, const char *value, int ov) { size_t len; char *str; int ret; len = strlen(var) + 1 + strlen(value) + 1; str = malloc(len); if (!str) return PFM_ERR_NOMEM; sprintf(str, "%s=%s", var, value); ret = putenv(str); free(str); return ret ? PFM_ERR_INVAL : PFM_SUCCESS; } #else static inline int set_env_var(const char *var, const char *value, int ov) { return setenv(var, value, ov); } #endif static int event_has_pname(char *s) { char *p; return (p = strchr(s, ':')) && *(p+1) == ':'; } static int print_codes(char *buf, int plm, int max_encoding) { uint64_t *codes = NULL; int j, ret, count = 0; ret = pfm_get_event_encoding(buf, PFM_PLM0|PFM_PLM3, NULL, NULL, &codes, &count); if (ret != PFM_SUCCESS) { if (ret == PFM_ERR_NOTFOUND) errx(1, "encoding failed, try setting env variable LIBPFM_ENCODE_INACTIVE=1"); return -1; } for(j = 0; j < max_encoding; j++) { if (j < count) printf("0x%"PRIx64, codes[j]); printf("%s", options.csv_sep); } free(codes); return 0; } static int check_valid(char *buf, int plm) { uint64_t *codes = NULL; int ret, count = 0; ret = pfm_get_event_encoding(buf, PFM_PLM0|PFM_PLM3, NULL, NULL, &codes, &count); if (ret != PFM_SUCCESS) return -1; free(codes); return 0; } static int match_ufilters(pfm_event_attr_info_t *info) { uint32_t ufilter1 = 0; uint32_t ufilter2 = 0; if (options.ufilter.is_dfl) ufilter1 |= 0x1; if (info->is_dfl) ufilter2 |= 0x1; if (options.ufilter.is_precise) ufilter1 |= 0x2; if (info->is_precise) ufilter2 |= 0x2; if (!ufilter1) return 1; /* at least one filter matches */ return ufilter1 & ufilter2; } static int match_efilters(pfm_event_info_t *info) { pfm_event_attr_info_t ainfo; int n = 0; int i, ret; if (options.efilter.is_precise && !info->is_precise) return 0; memset(&ainfo, 0, sizeof(ainfo)); ainfo.size = sizeof(ainfo); pfm_for_each_event_attr(i, info) { ret = pfm_get_event_attr_info(info->idx, i, options.os, &ainfo); if (ret != PFM_SUCCESS) continue; if (match_ufilters(&ainfo)) return 1; if (ainfo.type == PFM_ATTR_UMASK) n++; } return n ? 0 : 1; } static void show_event_info_combo(pfm_event_info_t *info) { pfm_event_attr_info_t *ainfo; pfm_pmu_info_t pinfo; char buf[MAXBUF]; size_t len; int numasks = 0; int i, j, ret; uint64_t total, m, u; memset(&pinfo, 0, sizeof(pinfo)); pinfo.size = sizeof(pinfo); ret = pfm_get_pmu_info(info->pmu, &pinfo); if (ret != PFM_SUCCESS) errx(1, "cannot get PMU info"); ainfo = calloc(info->nattrs, sizeof(*ainfo)); if (!ainfo) err(1, "event %s : ", info->name); /* * extract attribute information and count number * of umasks * * we cannot just drop non umasks because we need * to keep attributes in order for the enumeration * of 2^n */ pfm_for_each_event_attr(i, info) { ainfo[i].size = sizeof(*ainfo); ret = pfm_get_event_attr_info(info->idx, i, options.os, &ainfo[i]); if (ret != PFM_SUCCESS) errx(1, "cannot get attribute info: %s", pfm_strerror(ret)); if (ainfo[i].type == PFM_ATTR_UMASK) numasks++; } if (numasks > options.combo_lim) { warnx("event %s has too many umasks to print all combinations, dropping to simple enumeration", info->name); free(ainfo); show_event_info_compact(info); return; } if (numasks) { if (info->nattrs > (int)((sizeof(total)<<3))) { warnx("too many umasks, cannot show all combinations for event %s", info->name); goto end; } total = 1ULL << info->nattrs; for (u = 1; u < total; u++) { len = sizeof(buf); len -= snprintf(buf, len, "%s::%s", pinfo.name, info->name); if (len <= 0) { warnx("event name too long%s", info->name); goto end; } for(m = u, j = 0; m; m >>=1, j++) { if (m & 0x1ULL) { /* we have hit a non umasks attribute, skip */ if (ainfo[j].type != PFM_ATTR_UMASK) break; if (len < (1 + strlen(ainfo[j].name))) { warnx("umasks combination too long for event %s", buf); break; } strncat(buf, ":", len-1);buf[len-1] = '\0'; len--; strncat(buf, ainfo[j].name, len-1);buf[len-1] = '\0'; len -= strlen(ainfo[j].name); } } /* if found a valid umask combination, check encoding */ if (m == 0) { if (options.encode) ret = print_codes(buf, PFM_PLM0|PFM_PLM3, pinfo.max_encoding); else ret = check_valid(buf, PFM_PLM0|PFM_PLM3); if (!ret) printf("%s\n", buf); } } } else { snprintf(buf, sizeof(buf)-1, "%s::%s", pinfo.name, info->name); buf[sizeof(buf)-1] = '\0'; ret = options.encode ? print_codes(buf, PFM_PLM0|PFM_PLM3, pinfo.max_encoding) : 0; if (!ret) printf("%s\n", buf); } end: free(ainfo); } static void show_event_info_compact(pfm_event_info_t *info) { pfm_event_attr_info_t ainfo; pfm_pmu_info_t pinfo; char buf[MAXBUF]; int i, ret, um = 0; memset(&ainfo, 0, sizeof(ainfo)); memset(&pinfo, 0, sizeof(pinfo)); pinfo.size = sizeof(pinfo); ainfo.size = sizeof(ainfo); ret = pfm_get_pmu_info(info->pmu, &pinfo); if (ret != PFM_SUCCESS) errx(1, "cannot get pmu info: %s", pfm_strerror(ret)); if (options.name_only) { if (options.encode) printf("0x%-10"PRIx64, info->code); printf("%s\n", info->name); return; } pfm_for_each_event_attr(i, info) { ret = pfm_get_event_attr_info(info->idx, i, options.os, &ainfo); if (ret != PFM_SUCCESS) errx(1, "cannot get attribute info: %s", pfm_strerror(ret)); if (ainfo.type != PFM_ATTR_UMASK) continue; if (!match_ufilters(&ainfo)) continue; snprintf(buf, sizeof(buf)-1, "%s::%s:%s", pinfo.name, info->name, ainfo.name); buf[sizeof(buf)-1] = '\0'; ret = 0; if (options.encode) { ret = print_codes(buf, PFM_PLM0|PFM_PLM3, pinfo.max_encoding); } if (!ret) { printf("%s", buf); if (options.desc) { printf("%s", options.csv_sep); printf("\"%s. %s.\"", info->desc, ainfo.desc); } putchar('\n'); } um++; } if (um == 0) { if (!match_efilters(info)) return; snprintf(buf, sizeof(buf)-1, "%s::%s", pinfo.name, info->name); buf[sizeof(buf)-1] = '\0'; if (options.encode) { ret = print_codes(buf, PFM_PLM0|PFM_PLM3, pinfo.max_encoding); if (ret) return; } printf("%s", buf); if (options.desc) { printf("%s", options.csv_sep); printf("\"%s.\"", info->desc); } putchar('\n'); } } int compare_codes(const void *a, const void *b) { const code_info_t *aa = a; const code_info_t *bb = b; uint64_t m = options.mask; if ((aa->code & m) < (bb->code &m)) return -1; if ((aa->code & m) == (bb->code & m)) return 0; return 1; } static void print_event_flags(pfm_event_info_t *info) { int n = 0; if (info->is_precise) { printf("[precise] "); n++; } if (!n) printf("None"); } static void print_attr_flags(pfm_event_attr_info_t *info) { int n = 0; if (info->is_dfl) { printf("[default] "); n++; } if (info->is_precise) { printf("[precise] "); n++; } if (!n) printf("None "); } static void show_event_info(pfm_event_info_t *info) { pfm_event_attr_info_t ainfo; pfm_pmu_info_t pinfo; int mod = 0, um = 0; int i, ret; const char *src; if (options.name_only) { printf("%s\n", info->name); return; } memset(&ainfo, 0, sizeof(ainfo)); memset(&pinfo, 0, sizeof(pinfo)); pinfo.size = sizeof(pinfo); ainfo.size = sizeof(ainfo); if (!match_efilters(info)) return; ret = pfm_get_pmu_info(info->pmu, &pinfo); if (ret) errx(1, "cannot get pmu info: %s", pfm_strerror(ret)); printf("#-----------------------------\n" "IDX : %d\n" "PMU name : %s (%s)\n" "Name : %s\n" "Equiv : %s\n", info->idx, pinfo.name, pinfo.desc, info->name, info->equiv ? info->equiv : "None"); printf("Flags : "); print_event_flags(info); putchar('\n'); printf("Desc : %s\n", info->desc ? info->desc : "no description available"); printf("Code : 0x%"PRIx64"\n", info->code); pfm_for_each_event_attr(i, info) { ret = pfm_get_event_attr_info(info->idx, i, options.os, &ainfo); if (ret != PFM_SUCCESS) errx(1, "cannot retrieve event %s attribute info: %s", info->name, pfm_strerror(ret)); if (ainfo.ctrl >= PFM_ATTR_CTRL_MAX) { warnx("event: %s has unsupported attribute source %d", info->name, ainfo.ctrl); ainfo.ctrl = PFM_ATTR_CTRL_UNKNOWN; } src = srcs[ainfo.ctrl]; switch(ainfo.type) { case PFM_ATTR_UMASK: if (!match_ufilters(&ainfo)) continue; printf("Umask-%02u : 0x%02"PRIx64" : %s : [%s] : ", um, ainfo.code, src, ainfo.name); print_attr_flags(&ainfo); putchar(':'); if (ainfo.equiv) printf(" Alias to %s", ainfo.equiv); else printf(" %s", ainfo.desc); putchar('\n'); um++; break; case PFM_ATTR_MOD_BOOL: printf("Modif-%02u : 0x%02"PRIx64" : %s : [%s] : %s (boolean)\n", mod, ainfo.code, src, ainfo.name, ainfo.desc); mod++; break; case PFM_ATTR_MOD_INTEGER: printf("Modif-%02u : 0x%02"PRIx64" : %s : [%s] : %s (integer)\n", mod, ainfo.code, src, ainfo.name, ainfo.desc); mod++; break; default: printf("Attr-%02u : 0x%02"PRIx64" : %s : [%s] : %s\n", i, ainfo.code, ainfo.name, src, ainfo.desc); } } } static int show_info(char *event, regex_t *preg) { pfm_pmu_info_t pinfo; pfm_event_info_t info; int i, j, ret, match = 0, pname; size_t len, l = 0; char *fullname = NULL; memset(&pinfo, 0, sizeof(pinfo)); memset(&info, 0, sizeof(info)); pinfo.size = sizeof(pinfo); info.size = sizeof(info); pname = event_has_pname(event); /* * scan all supported events, incl. those * from undetected PMU models */ pfm_for_all_pmus(j) { ret = pfm_get_pmu_info(j, &pinfo); if (ret != PFM_SUCCESS) continue; /* no pmu prefix, just look for detected PMU models */ if (!pname && !pinfo.is_present) continue; for (i = pinfo.first_event; i != -1; i = pfm_get_event_next(i)) { ret = pfm_get_event_info(i, options.os, &info); if (ret != PFM_SUCCESS) errx(1, "cannot get event info: %s", pfm_strerror(ret)); len = strlen(info.name) + strlen(pinfo.name) + 1 + 2; if (len > l) { l = len; fullname = realloc(fullname, l); if (!fullname) err(1, "cannot allocate memory"); } sprintf(fullname, "%s::%s", pinfo.name, info.name); if (regexec(preg, fullname, 0, NULL, 0) == 0) { if (options.compact) if (options.combo) show_event_info_combo(&info); else show_event_info_compact(&info); else show_event_info(&info); match++; } } } if (fullname) free(fullname); return match; } static int show_info_sorted(char *event, regex_t *preg) { pfm_pmu_info_t pinfo; pfm_event_info_t info; unsigned int j; int i, ret, n, match = 0; size_t len, l = 0; char *fullname = NULL; code_info_t *codes; memset(&pinfo, 0, sizeof(pinfo)); memset(&info, 0, sizeof(info)); pinfo.size = sizeof(pinfo); info.size = sizeof(info); pfm_for_all_pmus(j) { ret = pfm_get_pmu_info(j, &pinfo); if (ret != PFM_SUCCESS) continue; codes = malloc(pinfo.nevents * sizeof(*codes)); if (!codes) err(1, "cannot allocate memory\n"); /* scans all supported events */ n = 0; for (i = pinfo.first_event; i != -1; i = pfm_get_event_next(i)) { ret = pfm_get_event_info(i, options.os, &info); if (ret != PFM_SUCCESS) errx(1, "cannot get event info: %s", pfm_strerror(ret)); if (info.pmu != j) continue; codes[n].idx = info.idx; codes[n].code = info.code; n++; } qsort(codes, n, sizeof(*codes), compare_codes); for(i=0; i < n; i++) { ret = pfm_get_event_info(codes[i].idx, options.os, &info); if (ret != PFM_SUCCESS) errx(1, "cannot get event info: %s", pfm_strerror(ret)); len = strlen(info.name) + strlen(pinfo.name) + 1 + 2; if (len > l) { l = len; fullname = realloc(fullname, l); if (!fullname) err(1, "cannot allocate memory"); } sprintf(fullname, "%s::%s", pinfo.name, info.name); if (regexec(preg, fullname, 0, NULL, 0) == 0) { if (options.compact) show_event_info_compact(&info); else show_event_info(&info); match++; } } free(codes); } if (fullname) free(fullname); return match; } static void usage(void) { printf("showevtinfo [-L] [-E] [-h] [-s] [-m mask]\n" "-L\t\tlist one event per line (compact mode)\n" "-E\t\tlist one event per line with encoding (compact mode)\n" "-M\t\tdisplay all valid unit masks combination (use with -L or -E)\n" "-h\t\tget help\n" "-s\t\tsort event by PMU and by code based on -m mask\n" "-l\t\tmaximum number of umasks to list all combinations (default: %d)\n" "-F\t\tshow only events and attributes with certain flags (precise,...)\n" "-m mask\t\thexadecimal event code mask, bits to match when sorting\n" "-x sep\t\tuse sep as field separator in compact mode\n" "-D\t\t\tprint event description in compact mode\n" "-O os\t\tshow attributes for the specific operating system\n", COMBO_MAX); } /* * keep: [pmu::]event * drop everything else */ static void drop_event_attributes(char *str) { char *p; p = strchr(str, ':'); if (!p) return; str = p+1; /* keep PMU name */ if (*str == ':') str++; /* stop string at 1st attribute */ p = strchr(str, ':'); if (p) *p = '\0'; } #define EVENT_FLAGS(n, f, l) { .name = n, .ebit = f, .ubit = l } struct attr_flags { const char *name; int ebit; /* bit position in pfm_event_info_t.flags, -1 means ignore */ int ubit; /* bit position in pfm_event_attr_info_t.flags, -1 means ignore */ }; static const struct attr_flags event_flags[]={ EVENT_FLAGS("precise", 0, 1), EVENT_FLAGS("pebs", 0, 1), EVENT_FLAGS("default", -1, 0), EVENT_FLAGS("dfl", -1, 0), EVENT_FLAGS(NULL, 0, 0) }; static void parse_filters(char *arg) { const struct attr_flags *attr; char *p; while (arg) { p = strchr(arg, ','); if (p) *p++ = 0; for (attr = event_flags; attr->name; attr++) { if (!strcasecmp(attr->name, arg)) { switch(attr->ebit) { case 0: options.efilter.is_precise = 1; break; case -1: break; default: errx(1, "unknown event flag %d", attr->ebit); } switch (attr->ubit) { case 0: options.ufilter.is_dfl = 1; break; case 1: options.ufilter.is_precise = 1; break; case -1: break; default: errx(1, "unknown umaks flag %d", attr->ubit); } break; } } arg = p; } } static const struct { char *name; pfm_os_t os; } supported_oses[]={ { .name = "none", .os = PFM_OS_NONE }, { .name = "raw", .os = PFM_OS_NONE }, { .name = "pmu", .os = PFM_OS_NONE }, { .name = "perf", .os = PFM_OS_PERF_EVENT}, { .name = "perf_ext", .os = PFM_OS_PERF_EVENT_EXT}, { .name = NULL, } }; static const char *pmu_types[]={ "unknown type", "core", "uncore", "OS generic", }; static void setup_os(char *ostr) { int i; for (i = 0; supported_oses[i].name; i++) { if (!strcmp(supported_oses[i].name, ostr)) { options.os = supported_oses[i].os; return; } } fprintf(stderr, "unknown OS layer %s, choose from:", ostr); for (i = 0; supported_oses[i].name; i++) { if (i) fputc(',', stderr); fprintf(stderr, " %s", supported_oses[i].name); } fputc('\n', stderr); exit(1); } int main(int argc, char **argv) { static char *argv_all[2] = { ".*", NULL }; pfm_pmu_info_t pinfo; char *endptr = NULL; char default_sep[2] = "\t"; char *ostr = NULL; char **args; int i, match; regex_t preg; int ret, c; memset(&pinfo, 0, sizeof(pinfo)); pinfo.size = sizeof(pinfo); while ((c=getopt(argc, argv,"hELsm:MNl:F:x:DO:")) != -1) { switch(c) { case 'L': options.compact = 1; break; case 'F': parse_filters(optarg); break; case 'E': options.compact = 1; options.encode = 1; break; case 'M': options.combo = 1; break; case 'N': options.name_only = 1; break; case 's': options.sort = 1; break; case 'D': options.desc = 1; break; case 'l': options.combo_lim = atoi(optarg); break; case 'x': options.csv_sep = optarg; break; case 'O': ostr = optarg; break; case 'm': options.mask = strtoull(optarg, &endptr, 16); if (*endptr) errx(1, "mask must be in hexadecimal\n"); break; case 'h': usage(); exit(0); default: errx(1, "unknown option error"); } } /* to allow encoding of events from non detected PMU models */ ret = set_env_var("LIBPFM_ENCODE_INACTIVE", "1", 1); if (ret != PFM_SUCCESS) errx(1, "cannot force inactive encoding"); ret = pfm_initialize(); if (ret != PFM_SUCCESS) errx(1, "cannot initialize libpfm: %s", pfm_strerror(ret)); if (options.mask == 0) options.mask = ~0; if (optind == argc) { args = argv_all; } else { args = argv + optind; } if (!options.csv_sep) options.csv_sep = default_sep; /* avoid combinatorial explosion */ if (options.combo_lim == 0) options.combo_lim = COMBO_MAX; if (ostr) setup_os(ostr); else options.os = PFM_OS_NONE; if (!options.compact) { int total_supported_events = 0; int total_available_events = 0; printf("Supported PMU models:\n"); pfm_for_all_pmus(i) { ret = pfm_get_pmu_info(i, &pinfo); if (ret != PFM_SUCCESS) continue; printf("\t[%d, %s, \"%s\"]\n", i, pinfo.name, pinfo.desc); } printf("Detected PMU models:\n"); pfm_for_all_pmus(i) { ret = pfm_get_pmu_info(i, &pinfo); if (ret != PFM_SUCCESS) continue; if (pinfo.is_present) { if (pinfo.type >= PFM_PMU_TYPE_MAX) pinfo.type = PFM_PMU_TYPE_UNKNOWN; printf("\t[%d, %s, \"%s\", %d events, %d max encoding, %d counters, %s PMU]\n", i, pinfo.name, pinfo.desc, pinfo.nevents, pinfo.max_encoding, pinfo.num_cntrs + pinfo.num_fixed_cntrs, pmu_types[pinfo.type]); total_supported_events += pinfo.nevents; } total_available_events += pinfo.nevents; } printf("Total events: %d available, %d supported\n", total_available_events, total_supported_events); } while(*args) { /* drop umasks and modifiers */ drop_event_attributes(*args); if (regcomp(&preg, *args, REG_ICASE)) errx(1, "error in regular expression for event \"%s\"", *argv); if (options.sort) match = show_info_sorted(*args, &preg); else match = show_info(*args, &preg); if (match == 0) errx(1, "event %s not found", *args); args++; } regfree(&preg); pfm_terminate(); return 0; } libpfm-4.9.0/examples/check_events.c0000664000175000017500000001064313223402656017245 0ustar eranianeranian/* * check_events.c - show event encoding * * Copyright (c) 2009 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. */ #include #include #include #include #include #include #include #include int pmu_is_present(pfm_pmu_t p) { pfm_pmu_info_t pinfo; int ret; memset(&pinfo, 0, sizeof(pinfo)); ret = pfm_get_pmu_info(p, &pinfo); return ret == PFM_SUCCESS ? pinfo.is_present : 0; } int main(int argc, const char **argv) { pfm_pmu_info_t pinfo; pfm_pmu_encode_arg_t e; const char *arg[3]; const char **p; char *fqstr; pfm_event_info_t info; int i, j, ret; int total_supported_events = 0; int total_available_events = 0; /* * Initialize pfm library (required before we can use it) */ ret = pfm_initialize(); if (ret != PFM_SUCCESS) errx(1, "cannot initialize library: %s\n", pfm_strerror(ret)); memset(&pinfo, 0, sizeof(pinfo)); memset(&info, 0, sizeof(info)); printf("Supported PMU models:\n"); for(i=0; i < PFM_PMU_MAX; i++) { ret = pfm_get_pmu_info(i, &pinfo); if (ret != PFM_SUCCESS) continue; printf("\t[%d, %s, \"%s\"]\n", i, pinfo.name, pinfo.desc); } printf("Detected PMU models:\n"); for(i=0; i < PFM_PMU_MAX; i++) { ret = pfm_get_pmu_info(i, &pinfo); if (ret != PFM_SUCCESS) continue; if (pinfo.is_present) { printf("\t[%d, %s, \"%s\"]\n", i, pinfo.name, pinfo.desc); total_supported_events += pinfo.nevents; } total_available_events += pinfo.nevents; } printf("Total events: %d available, %d supported\n", total_available_events, total_supported_events); /* * be nice to user! */ if (argc < 2 && pmu_is_present(PFM_PMU_PERF_EVENT)) { arg[0] = "PERF_COUNT_HW_CPU_CYCLES"; arg[1] = "PERF_COUNT_HW_INSTRUCTIONS"; arg[2] = NULL; p = arg; } else { p = argv+1; } if (!*p) errx(1, "you must pass at least one event"); memset(&e, 0, sizeof(e)); while(*p) { /* * extract raw event encoding * * For perf_event encoding, use * #include * and the function: * pfm_get_perf_event_encoding() */ fqstr = NULL; e.fstr = &fqstr; ret = pfm_get_os_event_encoding(*p, PFM_PLM0|PFM_PLM3, PFM_OS_NONE, &e); if (ret != PFM_SUCCESS) { /* * codes is too small for this event * free and let the library resize */ if (ret == PFM_ERR_TOOSMALL) { free(e.codes); e.codes = NULL; e.count = 0; free(fqstr); continue; } if (ret == PFM_ERR_NOTFOUND && strstr(*p, "::")) errx(1, "%s: try setting LIBPFM_ENCODE_INACTIVE=1", pfm_strerror(ret)); errx(1, "cannot encode event %s: %s", *p, pfm_strerror(ret)); } ret = pfm_get_event_info(e.idx, PFM_OS_NONE, &info); if (ret != PFM_SUCCESS) errx(1, "cannot get event info: %s", pfm_strerror(ret)); ret = pfm_get_pmu_info(info.pmu, &pinfo); if (ret != PFM_SUCCESS) errx(1, "cannot get PMU info: %s", pfm_strerror(ret)); printf("Requested Event: %s\n", *p); printf("Actual Event: %s\n", fqstr); printf("PMU : %s\n", pinfo.desc); printf("IDX : %d\n", e.idx); printf("Codes :"); for(j=0; j < e.count; j++) printf(" 0x%"PRIx64, e.codes[j]); putchar('\n'); free(fqstr); p++; } if (e.codes) free(e.codes); return 0; }