Verilog-Perl-3.482/0000755000177100017500000000000014553624441014024 5ustar wsnyderwsnyderVerilog-Perl-3.482/Std.pm0000644000177100017500000000636014553624343015122 0ustar wsnyderwsnyder# See copyright, etc in below POD section. ###################################################################### package Verilog::Std; use Config; use IO::File; use File::Path; use Verilog::Language; use Carp; use strict; use vars qw($VERSION); ###################################################################### #### Configuration Section $VERSION = '3.482'; ####################################################################### # It's a PITRA to have pure datafiles get installed properly, so we have # the std text here in this package. our $_Std_Text = <}) Return the definition of the std package. Optionally pass the language standard, defaulting to what Verilog::Language::language_standard returns if unspecified. =back =head1 DISTRIBUTION Verilog-Perl is part of the L free Verilog EDA software tool suite. The latest version is available from CPAN and from L. Copyright 2009-2024 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. =head1 AUTHORS Wilson Snyder =head1 SEE ALSO L =cut ###################################################################### Verilog-Perl-3.482/Parser/0000755000177100017500000000000014553624441015260 5ustar wsnyderwsnyderVerilog-Perl-3.482/Parser/VParseGrammar.h0000644000177100017500000000725014553624300020136 0ustar wsnyderwsnyder// -*- C++ -*- //************************************************************************* // // Copyright 2000-2024 by Wilson Snyder. This program is free software; // you can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. // // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // //************************************************************************* /// \file /// \brief Verilog::Parse: Parseess verilog code /// /// Authors: Wilson Snyder /// /// Code available from: https://www.veripool.org/verilog-perl /// //************************************************************************* #ifndef _VPARSEGRAMMAR_H_ #define _VPARSEGRAMMAR_H_ 1 #include #include #include #include using namespace std; #include "VFileLine.h" #include "VParse.h" #include "VAst.h" //============================================================================ // Containers of things to put out later struct VParseGPin { VFileLine* m_fl; string m_name; string m_conn; int m_number; VParseGPin(VFileLine* fl, const string& name, const string& conn, int number) : m_fl(fl), m_name(name), m_conn(conn), m_number(number) {} }; struct VParseNet { string m_name; string m_msb; string m_lsb; VParseNet(const string& net, const string& msb, const string& lsb) : m_name(net), m_msb(msb), m_lsb(lsb) {} VParseNet(const string& net) : m_name(net), m_msb(""), m_lsb("") {} }; struct VParseVar { string m_decl; string m_net; string m_io; string m_dtype; string m_range; }; //============================================================================ // We can't use bison's %union as the string type doesn't fit in a union. // It's fine to use a struct though! struct VParseBisonYYSType { string str; VFileLine* fl; VAstEnt* scp; // Symbol table scope for future lookups }; #define YYSTYPE VParseBisonYYSType //============================================================================ class VParseGrammar { static VParseGrammar* s_grammarp; ///< Current THIS, bison() isn't class based VParse* m_parsep; //int debug() { return 9; } public: // Only for VParseBison int m_pinNum; ///< Pin number being parsed VParseVar m_var; string m_cellMod; bool m_cellParam; bool m_portNextNetValid; string m_portNextNetName; string m_portNextNetMsb; string m_portNextNetLsb; bool m_withinPin; bool m_withinInst; deque m_pinStack; deque m_portStack; deque m_varStack; public: // But for internal use only static VParseGrammar* staticGrammarp() { return s_grammarp; } static VParse* staticParsep() { return staticGrammarp()->m_parsep; } static void bisonError(const char* text) { staticParsep()->error(text); } //static VFileLine* fileline() { return s_grammarp->m_fileline; } public: // CREATORS VParseGrammar(VParse* parsep) : m_parsep(parsep) { s_grammarp = this; m_pinNum = 0; m_cellParam = false; m_portNextNetValid = false; m_withinInst = false; m_withinPin = false; } ~VParseGrammar() { s_grammarp = NULL; } // ACCESSORS void debug(int level); int pinNum() const { return m_pinNum; } void pinNum(int flag) { m_pinNum = flag; } void pinNumInc() { m_pinNum++; } // METHODS int parse(); // See VParseBison.y static const char* tokenName(int token); }; #endif // Guard Verilog-Perl-3.482/Parser/VSymTable.cpp0000644000177100017500000001312214553624300017623 0ustar wsnyderwsnyder// -*- C++ -*- //************************************************************************* // // Copyright 2009-2024 by Wilson Snyder. This program is free software; // you can redistribute it and/or modify it under the terms of either the // GNU Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // //************************************************************************* /// \file /// \brief Verilog::Parse: Symbol table accessing /// /// Authors: Wilson Snyder /// /// Code available from: https://www.veripool.org/verilog-perl /// //************************************************************************* // // Verilog Name spaces: // Namespace Under Holds // (*attributes*) objects Not implemented // `textmacros comp-unit Preproc handles // .ports/inout module/cell ports // packages Global package // definitions comp-unit Non-nested (macro)module, primitive, program, interface // comp-unit comp-unit Func, task, param, events, nets, vars, types // module (macro)module,primitive,program,interface,package // module, intf, program, // blocks, func, task, inst, param, events, // vars, nets, types // block blocks(begin/fork), specify, func, task // blocks, specify, func, task, inst*, param, events, // vars, nets*, types // (*IEEE doesn't list but can be under generate blocks) // // Testcase: "generate if (1) begin wire b; ..." proves b is local. // // Turning this on its head: // // Object Namespace Under // ports/inouts .ports module/cell // // package packages comp-unit // // module, program, interface definitions comp-unit // [primitive(defs)] OR module module,primitive,program,interface,package // // func, task, param, events, comp-unit comp-unit // vars, nets, types, [blocks] module module,primitive,program,interface,package // [inst], [[specify]] OR block blocks(begin/fork), specify, func, task // // [...] indicates can only be under one of the lower name spaces, but won't // matter if the others are searched since the grammar won't create the // conflicting case. // // Since packages can't be declared under modules, and modules under // blocks. we can just have one hierarchical namespace that combines // comp-unit, module and block. //************************************************************************* #include "VSymTable.h" #include #include /* Perl */ extern "C" { # include "EXTERN.h" # include "perl.h" # include "XSUB.h" } //###################################################################### // VAstEnt // // A symtable is simply a hash(HV) by name of the object // Under each hash entry (HE) is an array (AV) // Under each array (AV) is an [SV with type, SV with HV of lower symtab] #if 0 # define DBG_UINFO(z,msg) {printf("%s:%d: ", __FILE__,__LINE__); cout << msg; } #else # define DBG_UINFO(z,msg) #endif //###################################################################### // VSymStack VSymStack::VSymStack(VFileLine* fl, struct av* symp) { assert(symp); ((VAstEnt*)(symp))->initNetlist(fl); pushScope((VAstEnt*)(symp)); } //###################################################################### // Self test class VFileLineTest : public VFileLine { public: VFileLineTest(int called_only_for_default) : VFileLine(called_only_for_default) {} virtual ~VFileLineTest() { } virtual VFileLine* create(const string& filename, int lineno) { return new VFileLineTest(true); } virtual void error(const string& msg) { cout << msg; } }; void VSymStack::selftest() { // GCC 3.3.5 requires this temporary string, so can't be a one liner { string max = VAstType(VAstType::_MAX).ascii(); assert(max == "_MAX"); } // Else probably missing word in ascii() // VFileLineTest flt(1); // GCC 3.3.5 requires temporary VFileLine* fl = flt.create(__FILE__,__LINE__); AV* topavp = newAV(); VSymStack stack(fl, topavp); // DBG_UINFO(9,"=============\n"); assert(stack.objofUpward() == "netlist"); assert(stack.findTypeUpward("missing") == VAstType::NOT_FOUND); DBG_UINFO(9,"=============\n"); stack.pushScope(stack.findInsert(VAstType::PACKAGE, "top")); { assert(stack.objofUpward() == "package"); assert(stack.findTypeUpward("top") == VAstType::PACKAGE); stack.findInsert(VAstType::TYPE, "a"); DBG_UINFO(9,"=============\n"); stack.pushScope(stack.findInsert(VAstType::MODULE, "lower")); { assert(stack.findTypeUpward("lower") == VAstType::MODULE); // IE ../lower exists. DBG_UINFO(9,"=============\n"); stack.pushScope(stack.findInsert(VAstType::FORK, "fork")); { assert(stack.findTypeUpward("lower") == VAstType::MODULE); // Ignores the fork } stack.popScope(fl); DBG_UINFO(9,"=============\n"); stack.pushScope(stack.findInsert(VAstType::CLASS, "a")); // Hides upper a { assert(stack.objofUpward() == "class"); assert(stack.findTypeUpward("a") == VAstType::CLASS); assert(stack.findTypeUpward("top") == VAstType::PACKAGE); } stack.popScope(fl); DBG_UINFO(9,"=============\n"); assert(stack.objofUpward() == "module"); assert(stack.findTypeUpward("a") == VAstType::CLASS); assert(stack.findTypeUpward("top") == VAstType::PACKAGE); } stack.popScope(fl); DBG_UINFO(9,"=============\n"); assert(stack.findTypeUpward("a") == VAstType::TYPE); } // av_undef(topavp); topavp=NULL; }; #undef DBG_UINFO Verilog-Perl-3.482/Parser/VParse.h0000644000177100017500000003074614553624300016635 0ustar wsnyderwsnyder// -*- C++ -*- //************************************************************************* // // Copyright 2000-2024 by Wilson Snyder. This program is free software; // you can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. // // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // //************************************************************************* /// \file /// \brief Verilog::Parse: Parses verilog code /// /// Authors: Wilson Snyder /// /// Code available from: https://www.veripool.org/verilog-perl /// //************************************************************************* #ifndef _VPREPROC_H_ #define _VPREPROC_H_ 1 #include #include #include #include #include using namespace std; #include "VFileLine.h" #include "VSymTable.h" class VParseLex; // Be sure not to include it, or the Bison class will get upset class VParseGrammar; // Be sure not to include it, or the Lex class will get upset struct VParseBisonYYSType; struct av; struct VParseHashElem { const char* keyp; enum {ELEM_STR, ELEM_INT} val_type; string val_str; // When val_type==ELEM_STR int val_int; // When val_type==ELEM_INT VParseHashElem() { keyp = NULL; } ~VParseHashElem() {} }; //********************************************************************** // VParse class VParse { private: // MEMBERS // Mode bool m_sigParser; ///< SigParser not simple Verilog::Parser // State VFileLine* m_inFilelinep; ///< Next token's starting point int m_debug; ///< Debugging level VParseLex* m_lexp; ///< Current lexer state (NULL = closed) VParseGrammar* m_grammarp; ///< Current bison state (NULL = closed) bool m_eof; ///< At end of file bool m_callbackMasterEna; ///< Callbacks are enabled bool m_useUnreadback;///< Need m_unreadback tracking bool m_useProtected; ///< Need `protected tracking bool m_usePinselects;///< Need bit-select parsing string m_unreadback; ///< Otherwise unprocessed whitespace before current token deque m_buffers; ///< Buffer of characters to process int m_anonNum; ///< Number of next anonymous object VSymStack m_syms; ///< Symbol stack VAstEnt* m_symTableNextId; ///< Symbol table for next lexer lookup public: // But for internalish use only // METHODS int lexToBison(VParseBisonYYSType* yylvalp); bool eofToLex() const { return m_eof && m_buffers.empty(); } bool inCellDefine() const; size_t inputToLex(char* buf, size_t max_size); // Symbol table VSymStack& syms() { return m_syms; } VAstEnt* symTableNextId() const { return m_symTableNextId; } void symTableNextId(VAstEnt* entp) { if (debug()) { if (entp) cout <<"symTableNextId under "<type().ascii()<replaceInsert(type,name)); } void symPushNewAnon(VAstType type) { string name = "__anon"; name += type.ascii() + cvtToStr(++m_anonNum); symPushNew(type,name); } void symPopScope(VAstType type) { if (m_syms.curType() != type) { string msg = (string)("Symbols suggest ending a '")+m_syms.curType().ascii()+"' but parser thinks ending a '"+type.ascii()+"'"; this->error(msg); return; } m_syms.popScope(inFilelinep()); } private: void fakeBison(); public: // CONSTRUCTORS VParse(VFileLine* filelinep, av* symsp, bool sigParser, bool useUnreadbackFlag, bool useProtected, bool usePinselects); virtual ~VParse(); // ACCESSORS /// Insert given file into this point in input stream int debug() const { return m_debug; } ///< Set debugging level void debug(int level); ///< Set debugging level void parse(const string& text); ///< Add given text to void setEof(); ///< Got a end of file bool sigParser() const { return m_sigParser; } void language(const char* valuep); void callbackMasterEna(bool flag) { m_callbackMasterEna=flag; } bool callbackMasterEna() const { return m_callbackMasterEna; } bool useProtected() const { return m_useProtected; } bool usePinSelects() const { return m_usePinselects; } VFileLine* inFilelinep() const; ///< File/Line number for last callback void inFileline(const string& filename, int lineno) { m_inFilelinep = m_inFilelinep->create(filename, lineno); } void inFilelineInc() { m_inFilelinep = inFilelinep()->create(inFilelinep()->lineno()+1); } void inLineDirective(const char* text) { int ign; m_inFilelinep = inFilelinep()->lineDirective(text, ign/*ref*/); } string unreadback() const { return (m_useUnreadback ? m_unreadback : "new(...,use_unreadback=>0) was used"); } void unreadback(const string& text) { if (m_useUnreadback && callbackMasterEna()) m_unreadback = text; } void unreadbackCat(const string& text) { if (m_useUnreadback && callbackMasterEna()) m_unreadback += text; } void unreadbackCat(const char* textp, size_t len) { unreadbackCat(string(textp,len)); } // The default behavior is to pass all unknown `defines right through. // This lets the user determine how to report the errors. It also nicely // allows `celldefine and such to remain in the output stream. // CONTROL METHODS // These options control how the parsing proceeds // CALLBACK METHODS // This probably will want to be overridden for given child users of this class. // CALLBACKGEN_H_VIRTUAL_0 // CALLBACKGEN_GENERATED_BEGIN - GENERATED AUTOMATICALLY by callbackgen // Verilog::Parser Callback methods virtual void attributeCb(VFileLine* fl, const string& text) = 0; virtual void commentCb(VFileLine* fl, const string& text) = 0; virtual void endparseCb(VFileLine* fl, const string& text) = 0; virtual void keywordCb(VFileLine* fl, const string& text) = 0; virtual void numberCb(VFileLine* fl, const string& text) = 0; virtual void operatorCb(VFileLine* fl, const string& text) = 0; virtual void preprocCb(VFileLine* fl, const string& text) = 0; virtual void stringCb(VFileLine* fl, const string& text) = 0; virtual void symbolCb(VFileLine* fl, const string& text) = 0; virtual void sysfuncCb(VFileLine* fl, const string& text) = 0; // Verilog::SigParser Callback methods virtual void classCb(VFileLine* fl, const string& kwd, const string& name, const string& virt) = 0; virtual void contassignCb(VFileLine* fl, const string& kwd, const string& lhs, const string& rhs) = 0; virtual void covergroupCb(VFileLine* fl, const string& kwd, const string& name) = 0; virtual void defparamCb(VFileLine* fl, const string& kwd, const string& lhs, const string& rhs) = 0; virtual void endcellCb(VFileLine* fl, const string& kwd) = 0; virtual void endclassCb(VFileLine* fl, const string& kwd) = 0; virtual void endgroupCb(VFileLine* fl, const string& kwd) = 0; virtual void endinterfaceCb(VFileLine* fl, const string& kwd) = 0; virtual void endmodportCb(VFileLine* fl, const string& kwd) = 0; virtual void endmoduleCb(VFileLine* fl, const string& kwd) = 0; virtual void endpackageCb(VFileLine* fl, const string& kwd) = 0; virtual void endprogramCb(VFileLine* fl, const string& kwd) = 0; virtual void endtaskfuncCb(VFileLine* fl, const string& kwd) = 0; virtual void functionCb(VFileLine* fl, const string& kwd, const string& name, const string& data_type) = 0; virtual void importCb(VFileLine* fl, const string& package, const string& id) = 0; virtual void instantCb(VFileLine* fl, const string& mod, const string& cell, const string& range) = 0; virtual void interfaceCb(VFileLine* fl, const string& kwd, const string& name) = 0; virtual void modportCb(VFileLine* fl, const string& kwd, const string& name) = 0; virtual void moduleCb(VFileLine* fl, const string& kwd, const string& name, bool, bool celldefine) = 0; virtual void packageCb(VFileLine* fl, const string& kwd, const string& name) = 0; virtual void parampinCb(VFileLine* fl, const string& name, const string& conn, int index) = 0; virtual void pinCb(VFileLine* fl, const string& name, const string& conn, int index) = 0; virtual void pinselectsCb(VFileLine* fl, const string& name, unsigned int arraycnt2, unsigned int elemcnt2, const VParseHashElem* conns2, int index) = 0; virtual void portCb(VFileLine* fl, const string& name, const string& objof, const string& direction, const string& data_type , const string& array, int index) = 0; virtual void programCb(VFileLine* fl, const string& kwd, const string& name) = 0; virtual void taskCb(VFileLine* fl, const string& kwd, const string& name) = 0; virtual void varCb(VFileLine* fl, const string& kwd, const string& name, const string& objof, const string& net , const string& data_type, const string& array, const string& value) = 0; // CALLBACKGEN_GENERATED_END - GENERATED AUTOMATICALLY by callbackgen // CALLBACKGEN_KEYWORDS // CALLBACKGEN_GENERATED_BEGIN - GENERATED AUTOMATICALLY by callbackgen static bool isKeyword(const char* kwd, int leng) { static set s_map; if (s_map.empty()) { const char* kwds[] = { "accept_on","alias","always","always_comb","always_ff","always_latch","and", "assert","assign","assume","automatic","before","begin","bind", "bins","binsof","bit","break","buf","bufif0","bufif1", "byte","case","casex","casez","cell","chandle","checker", "class","clocking","cmos","config","const","constraint","context", "continue","cover","covergroup","coverpoint","cross","deassign","default", "defparam","design","disable","dist","do","edge","else", "end","endcase","endchecker","endclass","endclocking","endconfig","endfunction", "endgenerate","endgroup","endinterface","endmodule","endpackage","endprimitive","endprogram", "endproperty","endsequence","endspecify","endtable","endtask","enum","event", "eventually","expect","export","extends","extern","final","first_match", "for","force","foreach","forever","fork","forkjoin","function", "generate","genvar","global","highz0","highz1","if","iff", "ifnone","ignore_bins","illegal_bins","implements","implies","import","incdir", "include","initial","inout","input","inside","instance","int", "integer","interconnect","interface","intersect","join","join_any","join_none", "large","let","liblist","library","local","localparam","logic", "longint","macromodule","matches","medium","modport","module","nand", "negedge","nettype","new","nexttime","nmos","nor","noshowcancelled", "not","notif0","notif1","null","or","output","package", "packed","parameter","pmos","posedge","primitive","priority","program", "property","protected","pull0","pull1","pulldown","pullup","pulsestyle_ondetect", "pulsestyle_onevent","pure","rand","randc","randcase","randsequence","rcmos", "real","realtime","ref","reg","reject_on","release","repeat", "restrict","return","rnmos","rpmos","rtran","rtranif0","rtranif1", "s_always","s_eventually","s_nexttime","s_until","s_until_with","scalared","sequence", "shortint","shortreal","showcancelled","signed","small","soft","solve", "specify","specparam","static","strength","string","strong","strong0", "strong1","struct","super","supply0","supply1","sync_accept_on","sync_reject_on", "table","tagged","task","this","throughout","time","timeprecision", "timeunit","tran","tranif0","tranif1","tri","tri0","tri1", "triand","trior","trireg","type","typedef","union","unique", "unique0","unsigned","until","until_with","untyped","use","uwire", "var","vectored","virtual","void","wait","wait_order","wand", "weak","weak0","weak1","while","wildcard","wire","with", "within","wor","xnor","xor",""}; for (const char** k=kwds; **k; k++) s_map.insert(*k); } string str(kwd,leng); return s_map.end() != s_map.find(str); } // CALLBACKGEN_GENERATED_END - GENERATED AUTOMATICALLY by callbackgen // UTILITIES void error(const string& msg) { inFilelinep()->error(msg); } ///< Report a error void fatal(const string& msg) { inFilelinep()->fatal(msg); } ///< Report a fatal error }; #endif // Guard Verilog-Perl-3.482/Parser/typemap0000644000177100017500000000153613422450702016656 0ustar wsnyderwsnyderTYPEMAP const char * T_PV VParserXs * O_CTHIS OUTPUT # The variable is stored into a pre-blessed $self->{_cthis} O_CTHIS // SELF->{_cthis} = THIS if( sv_isobject(SELF) && (SvTYPE(SvRV(SELF)) == SVt_PVHV) ) { SV **svp = hv_fetch((HV*)SvRV(SELF), \"_cthis\", 6, 1); sv_setiv(*svp, PTR2IV( $var )); XSRETURN_UNDEF; } else { warn( \"${Package}::$func_name() -- $var is not a Verilog::Parser object\" ); XSRETURN_UNDEF; } INPUT O_CTHIS $var = NULL; if( sv_isobject($arg) && (SvTYPE(SvRV( $arg )) == SVt_PVHV) ) { SV **svp = hv_fetch((HV*)SvRV(( $arg )), \"_cthis\", 6, 0); $var = NULL; if (svp) { $var = INT2PTR($type,SvIV( *svp )); } } if (!$var || !dynamic_cast($var)) { warn( \"${Package}::$func_name() -- $var is not a Verilog::Parser object\" ); XSRETURN_UNDEF; } Verilog-Perl-3.482/Parser/VAst.cpp0000644000177100017500000001533114553624300016636 0ustar wsnyderwsnyder// -*- C++ -*- //************************************************************************* // // Copyright 2009-2024 by Wilson Snyder. This program is free software; // you can redistribute it and/or modify it under the terms of either the // GNU Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // //************************************************************************* /// \file /// \brief Verilog::Parse: Symbol table accessing /// /// Authors: Wilson Snyder /// /// Code available from: https://www.veripool.org/verilog-perl /// //************************************************************************* #include "VSymTable.h" #include "VAst.h" #include #include /* Perl */ extern "C" { # include "EXTERN.h" # include "perl.h" # include "XSUB.h" } //###################################################################### // VAstEnt // // A symtable is simply a hash(HV) by name of the object // Under each hash entry (HE) is an array (AV) // Under each array (AV) is an [SV with type, SV with HV of lower symtab] #if 0 # define DBG_SV_DUMP(SVp) {printf("%s:%d:\n",__FILE__,__LINE__); Perl_sv_dump(aTHX_ (SV*)(SVp)); } # define DBG_UINFO(z,msg) {printf("%s:%d: ", __FILE__,__LINE__); cout << msg; } #else # define DBG_SV_DUMP(SVp) # define DBG_UINFO(z,msg) #endif int VAstEnt::s_debug = 0; // ACCESSORS VAstType VAstEnt::type() { assert(this); AV* avp = castAVp(); if (!avp || SvTYPE(avp) != SVt_PVAV || av_len(avp)<1) return VAstType::AN_ERROR; // $type_svpp = $this->[0] SV** type_svpp = av_fetch(avp, 0, 0); if (!type_svpp) return VAstType::AN_ERROR; VAstType type = (VAstType)(SvIV(*type_svpp)); return type; } HV* VAstEnt::subhash() { assert(this); AV* avp = castAVp(); if (!avp || SvTYPE(avp) != SVt_PVAV) return NULL; /*Error*/ // $type_svpp = $this->[2] SV** hash_svpp = av_fetch(avp, 2, 0); if (!hash_svpp || !SvROK(*hash_svpp) || SvTYPE(SvRV(*hash_svpp)) != SVt_PVHV) return NULL; /*Error*/ // $hash_hvp = %{$this->[2]} HV* hash_hvp = (HV*)(SvRV(*hash_svpp)); return hash_hvp; } VAstEnt* VAstEnt::parentp() { assert(this); AV* avp = castAVp(); if (!avp || SvTYPE(avp) != SVt_PVAV) return NULL; /*Error*/ // $parent_svpp = $this->[1] SV** parent_svpp = av_fetch(avp, 1, 0); if (!parent_svpp || !SvROK(*parent_svpp) || SvTYPE(SvRV(*parent_svpp)) != SVt_PVAV) return NULL; /*Error*/ // $parent_svp = @{$this->[1]} AV* parent_avp = (AV*)(SvRV(*parent_svpp)); return avToSymEnt(parent_avp); } // METHODS void VAstEnt::initNetlist(VFileLine* fl) { // Called on initial creation to check if this is a netlist, and/or create it assert(this); AV* avp = castAVp(); if (!avp || SvTYPE(avp) != SVt_PVAV) { fl->error("Parser->symbol_table isn't an array reference"); } if (type() == VAstType::AN_ERROR) { // Need init initAVEnt(avp, VAstType::NETLIST, NULL); } else if (type() == VAstType::NETLIST) { // Already inited } else { fl->error("Parser->symbol_table isn't a netlist object (not created by the parser?)"); } } AV* VAstEnt::newAVEnt(VAstType type) { AV* avp = newAV(); initAVEnt(avp, type, this->castAVp()); return avp; } void VAstEnt::initAVEnt(AV* avp, VAstType type, AV* parentp) { // $avp = [type, parent, {}] av_push(avp, newSViv(type)); if (parentp) { SV* parentsv = newRV((SV*)parentp); #ifdef SvWEAKREF // Newer perls // We're making a circular reference, so to garbage collect properly we need to break it // On older Perl's we'll just leak. sv_rvweaken(parentsv); #endif av_push(avp, parentsv ); } else { // netlist top av_push(avp, &PL_sv_undef); } av_push(avp, newRV_noinc((SV*)newHV()) ); } void VAstEnt::replaceInsert(VAstEnt* newentp, const string& name) { if (debug()) cout<<"VAstEnt::replaceInsert under="<ascii(name)<<"\"\n"; HV* hvp = subhash(); assert(hvp); // $svpp = $table{$name} SV** svpp = hv_fetch(hvp, name.c_str(), name.length(), 1/*create*/); if (svpp) {} // unused // $avp = $newentp (premade avp) hv_store(hvp, name.c_str(), name.length(), newRV((SV*)newentp), 0); } VAstEnt* VAstEnt::replaceInsert(VAstType type, const string& name) { if (debug()) cout<<"VAstEnt::replaceInsert under="<ascii(name)<<"\n"; return entp; } VAstEnt* VAstEnt::findInsert(VAstType type, const string& name) { if (debug()) cout<<"VAstEnt::findInsert under="<findSym(id_or_star)) { // We can just add a second reference to the same AstEnt object if (debug()) cout<<"VAstEnt::import under="<ascii()<<"\n"; replaceInsert(idEntp, id_or_star); } } else { // Walk old sym table HV* hvp = pkgEntp->subhash(); assert(hvp); hv_iterinit(hvp); while (HE* hep = hv_iternext(hvp)) { I32 retlen; const char* namep = hv_iterkey(hep, &retlen); string name = string(namep,retlen); SV* svp = hv_iterval(hvp, hep); VAstEnt* idEntp = avToSymEnt((AV*)(SvRV(svp))); if (debug()) cout<<"VAstEnt::import under="<ascii(name)<<"\n"; replaceInsert(idEntp, name); } } } string VAstEnt::ascii(const string& name) { string out = cvtToStr((void*)this)+"-"+type().ascii(); if (name!="") out += "-\""+name+"\""; return out; } #undef DBG_SV_DUMP #undef DBG_UINFO Verilog-Perl-3.482/Parser/callbackgen0000755000177100017500000003073114553624343017441 0ustar wsnyderwsnyder#!/usr/bin/perl -w # See copyright, etc in below POD section. ###################################################################### require 5.006_001; use Getopt::Long; use IO::File; use Pod::Usage; use strict; use vars qw($Debug $VERSION); # We need keywords, but haven't completely built yet, so can't use the blib # Thus we pull in Language.pm directly require "../Language.pm"; package main; $VERSION = '3.482'; # xs_manual=>1, -> The .xs file makes the handler itself my %Cbs = (attribute => {which=>'Parser', args => [text=>'string']}, comment => {which=>'Parser', args => [text=>'string']}, endparse => {which=>'Parser', args => [text=>'string']}, keyword => {which=>'Parser', args => [text=>'string']}, number => {which=>'Parser', args => [text=>'string']}, operator => {which=>'Parser', args => [text=>'string']}, preproc => {which=>'Parser', args => [text=>'string']}, string => {which=>'Parser', args => [text=>'string']}, symbol => {which=>'Parser', args => [text=>'string']}, sysfunc => {which=>'Parser', args => [text=>'string']}, # class => {which=>'SigParser', args => [kwd=>'string', name=>'string', virt=>'string']}, contassign => {which=>'SigParser', args => [kwd=>'string', lhs=>'string', rhs=>'string']}, covergroup => {which=>'SigParser', args => [kwd=>'string', name=>'string']}, defparam => {which=>'SigParser', args => [kwd=>'string', lhs=>'string', rhs=>'string']}, endcell => {which=>'SigParser', args => [kwd=>'string']}, endclass => {which=>'SigParser', args => [kwd=>'string']}, endgroup => {which=>'SigParser', args => [kwd=>'string']}, endinterface=>{which=>'SigParser', args => [kwd=>'string']}, endmodport => {which=>'SigParser', args => [kwd=>'string']}, endmodule => {which=>'SigParser', args => [kwd=>'string']}, endpackage => {which=>'SigParser', args => [kwd=>'string']}, endprogram => {which=>'SigParser', args => [kwd=>'string']}, endtaskfunc=> {which=>'SigParser', args => [kwd=>'string']}, function => {which=>'SigParser', args => [kwd=>'string', name=>'string', data_type=>'string']}, import => {which=>'SigParser', args => [package=>'string', id=>'string']}, instant => {which=>'SigParser', args => [mod=>'string', cell=>'string', range=>'string']}, interface => {which=>'SigParser', args => [kwd=>'string', name=>'string']}, modport => {which=>'SigParser', args => [kwd=>'string', name=>'string']}, module => {which=>'SigParser', args => [kwd=>'string', name=>'string', ignore3=>'undef', celldefine=>'bool'],}, package => {which=>'SigParser', args => [kwd=>'string', name=>'string']}, parampin => {which=>'SigParser', args => [name=>'string', conn=>'string', index=>'int']}, pin => {which=>'SigParser', args => [name=>'string', conn=>'string', index=>'int']}, pinselects => {which=>'SigParser', args => [name=>'string', conns=>'hash', index=>'int']}, port => {which=>'SigParser', args => [name=>'string', objof=>'string', direction=>'string', data_type=>'string', array=>'string', index=>'int']}, program => {which=>'SigParser', args => [kwd=>'string', name=>'string'],}, var => {which=>'SigParser', args => [kwd=>'string', name=>'string', objof=>'string', net=>'string', data_type=>'string', array=>'string', value=>'string'],}, task => {which=>'SigParser', args => [kwd=>'string', name=>'string']}, ); #====================================================================== # main our $Opt_Debug; autoflush STDOUT 1; autoflush STDERR 1; Getopt::Long::config("no_auto_abbrev"); if (! GetOptions ( # Local options "help" => \&usage, "version" => sub { print "Version $VERSION\n"; exit(0); }, "<>" => sub { die "%Error: Unknown parameter: $_[0]\n"; }, )) { die "%Error: Bad usage, try 'callbackgen --help'\n"; } process(); #---------------------------------------------------------------------- sub usage { print "Version $VERSION\n"; pod2usage(-verbose=>2, -exitval=>2, -output=>\*STDOUT, -noperldoc=>1); exit(1); } ####################################################################### sub process { filter("Parser.xs",0); filter("VParse.h",0); filter("Parser_callbackgen.cpp",1); } sub filter { my $filename = shift; my $make_xs = shift; my $fh = IO::File->new("<$filename"); my @lines; if (!$fh) { if ($make_xs) { @lines = ("// CALLBACKGEN_XS\n"); } else { die "%Error: $! $filename\n"; } } else { @lines = $fh->getlines; $fh->close; } my @orig = @lines; my $strip; my @out; foreach my $line (@lines) { if ($line =~ /CALLBACKGEN_GENERATED_BEGIN/) { $strip = 1; } else { if (!$strip) { push @out, $line; } if ($line =~ /CALLBACKGEN_GENERATED_END/) { $strip = 0; } elsif ($line =~ /CALLBACKGEN_H_MEMBERS/) { push @out, " // CALLBACKGEN_GENERATED_BEGIN - GENERATED AUTOMATICALLY by callbackgen\n"; push @out, _h_use_cb(); push @out, " // CALLBACKGEN_GENERATED_END - GENERATED AUTOMATICALLY by callbackgen\n"; } elsif ($line =~ /CALLBACKGEN_CB_USE/) { push @out, " // CALLBACKGEN_GENERATED_BEGIN - GENERATED AUTOMATICALLY by callbackgen\n"; push @out, _c_use_cb(); push @out, " // CALLBACKGEN_GENERATED_END - GENERATED AUTOMATICALLY by callbackgen\n"; } elsif ($line =~ /CALLBACKGEN_H_VIRTUAL(_0)?/) { my $zero = (($1||"") eq "_0") ? " = 0":""; push @out, " // CALLBACKGEN_GENERATED_BEGIN - GENERATED AUTOMATICALLY by callbackgen\n"; my $last_which = ""; foreach my $cb (sort {$Cbs{$a}{which} cmp $Cbs{$b}{which} || $a cmp $b} keys %Cbs) { my $which = $Cbs{$cb}{which}; if ($last_which ne $which) { push @out, " // Verilog::$which Callback methods\n"; $last_which = $which; } push @out, " virtual void "._func($cb)."("._arglist($cb).")".$zero.";\n"; } push @out, " // CALLBACKGEN_GENERATED_END - GENERATED AUTOMATICALLY by callbackgen\n"; } elsif ($line =~ /CALLBACKGEN_XS/) { push @out, "// CALLBACKGEN_GENERATED_BEGIN - GENERATED AUTOMATICALLY by callbackgen\n"; foreach my $cb (sort {$Cbs{$a}{which} cmp $Cbs{$b}{which} || $a cmp $b} keys %Cbs) { next if $Cbs{$cb}{xs_manual}; push @out, _xs($cb); } push @out, _xs_use_cb(); push @out, "// CALLBACKGEN_GENERATED_END - GENERATED AUTOMATICALLY by callbackgen\n"; } elsif ($line =~ /CALLBACKGEN_KEYWORDS/) { push @out, " // CALLBACKGEN_GENERATED_BEGIN - GENERATED AUTOMATICALLY by callbackgen\n"; push @out, _h_keywords(); push @out, " // CALLBACKGEN_GENERATED_END - GENERATED AUTOMATICALLY by callbackgen\n"; } elsif ($line =~ /CALLBACKGEN/) { die "%Error: callbackgen: Unknown pragma: $line"; } } } @lines = @out; if (join('',@lines) ne join('',@orig) || $make_xs) { # Generated file, so touch to apppease make print "callbackgen edited $filename\n"; $fh = IO::File->new(">$filename") or die "%Error: $! writing $filename\n"; $fh->write(join('',@lines)); $fh->close; } } sub _func { my $cb = shift; return $cb."Cb"; } sub _arglist { my $cb = shift; my $args = "VFileLine* fl"; my $n=0; for (my $i=0; $i<=$#{$Cbs{$cb}{args}}; $i+=2) { my ($arg,$type) = ($Cbs{$cb}{args}[$i],$Cbs{$cb}{args}[$i+1]); $args .= "\n\t" if (($n++%5)==4); if ($type eq 'string') { $args .= ", const string\& $arg"; } elsif ($type eq 'bool' || $type eq 'int') { $args .= ", $type $arg"; } elsif ($type eq 'hash') { $args .= ", unsigned int arraycnt${n}, unsigned int elemcnt${n}, const VParseHashElem* $arg${n}"; } elsif ($type eq 'undef') { $args .= ", bool"; } else { die "%Error: callbackgen: Unknown type: $arg=>$type\n"; } } return $args; } sub _xs { my $cb = shift; my @out; push @out, "// GENERATED AUTOMATICALLY by callbackgen\n"; push @out, "void VParserXs::"._func($cb)."("._arglist($cb).") {\n"; my $enable = "callbackMasterEna()"; $enable .= " && m_useCb_${cb}"; $enable .= " && $Cbs{$cb}{enable}" if $Cbs{$cb}{enable}; push @out, " if ($enable) {\n"; push @out, " cbFileline(fl);\n"; my $callargs=""; my $n=1; for (my $i=0; $i<=$#{$Cbs{$cb}{args}}; $i+=2) { my ($arg,$type) = ($Cbs{$cb}{args}[$i],$Cbs{$cb}{args}[$i+1]); if ($type eq 'string') { push @out, " static string hold${n}; hold${n} = $arg;\n"; $callargs .= ", hold${n}.c_str()"; } elsif ($type eq 'bool') { push @out, " static string hold${n}; hold${n} = $arg ? \"1\":\"0\";\n"; $callargs .= ", hold${n}.c_str()"; } elsif ($type eq 'int') { push @out, " static string hold${n}; static char num".$n."[30]; sprintf(num${n},\"%d\",$arg); hold${n}=num${n};\n"; $callargs .= ", hold${n}.c_str()"; } elsif ($type eq 'hash') { $callargs .= ", hasharray_param, arraycnt${n}, elemcnt${n}, ${arg}${n}"; } elsif ($type eq 'undef') { $callargs .= ", NULL"; } else { die "%Error: callbackgen: Unknown type: $arg=>$type\n"; } $n++; } my $narg = $n-1; push @out, " call(NULL, $narg, \"$cb\"$callargs);\n"; push @out, " }\n"; push @out, "}\n"; return @out; } ####################################################################### sub _h_use_cb { my @out; push @out, " struct { // Bit packed to help the cache\n"; foreach my $cb (sort {$a cmp $b} keys %Cbs) { push @out, " bool m_useCb_${cb}:1;\n"; } push @out, " };\n"; return @out; } sub _c_use_cb { my @out; push @out, " void set_cb_use() {\n"; foreach my $cb (sort {$a cmp $b} keys %Cbs) { push @out, " m_useCb_${cb} = true;\n"; } push @out, " }\n"; return @out; } sub _xs_use_cb { my @out; push @out, "// GENERATED AUTOMATICALLY by callbackgen\n"; # Trailing Ena so it doesn't look like it is a callback itself push @out, "void VParserXs::useCbEna(const char* name, bool flag) {\n"; push @out, " if (0) ;\n"; foreach my $cb (sort {$a cmp $b} keys %Cbs) { push @out, " else if (0==strcmp(name,\"${cb}\")) m_useCb_${cb} = flag;\n"; } push @out, "}\n"; return @out; } sub _h_keywords { my @out; (keys %Verilog::Language::Keyword) or die "%Error: Keyword loading failed,"; push @out, " static bool isKeyword(const char* kwd, int leng) {\n"; # If this gets slow, we can use a perfect hashing function and a table to compare push @out, "\tstatic set s_map;\n"; push @out, "\tif (s_map.empty()) {\n"; my $i=0; push @out, "\t const char* kwds[] = {"; foreach my $kwd (sort keys %Verilog::Language::Keyword) { next if $kwd !~ /^[a-zA-Z_]/; push @out, "\n\t\t" if ($i++%7)==0; push @out, "\"$kwd\","; } push @out, "\"\"};\n"; push @out, "\t for (const char** k=kwds; **k; k++) s_map.insert(*k);\n"; push @out, "\t}\n"; push @out, "\tstring str(kwd,leng);\n"; push @out, "\treturn s_map.end() != s_map.find(str);\n"; push @out, " }\n"; return @out; } ####################################################################### __END__ =pod =head1 NAME callbackgen - Create callback functions for Verilog-Perl internals =head1 SYNOPSIS make This will invoke callbackgen =head1 DESCRIPTION Callbackgen is an internal utility used in building Verilog::Parser. =head1 EXTENSIONS =over 4 =item //CALLBACKGEN_H_VIRTUAL Creates "virtual callbackCb(...);" =item //CALLBACKGEN_H_VIRTUAL_0 Creates "virtual callbackCb(...) = 0;" =item //CALLBACKGEN_XS Creates XS code for accepting the callback. =back =head1 ARGUMENTS =over 4 =item --help Displays this message and program version and exits. =item --debug Enable debug. =item --version Print the version number and exit. =back =head1 DISTRIBUTION This is part of the L free Verilog EDA software tool suite. The latest version is available from CPAN and from L. Copyright 2008-2024 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. =head1 AUTHORS Wilson Snyder =head1 SEE ALSO =cut ###################################################################### ### Local Variables: ### compile-command: "./callbackgen " ### End: Verilog-Perl-3.482/Parser/VParseBison.y0000644000177100017500000054767514553624300017667 0ustar wsnyderwsnyder// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilog-Perl bison parser // // This file is part of Verilog-Perl. // // Author: Wilson Snyder // // Code available from: https://www.veripool.org/verilog-perl // //************************************************************************* // // Copyright 2001-2024 by Wilson Snyder. This program is free software; // you can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. // // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // //************************************************************************* %{ #include #include #include #include #include #include #include #include #include #include #include #include "VParse.h" #include "VParseGrammar.h" #define YYERROR_VERBOSE 1 #define YYINITDEPTH 5000 // Large as the stack won't grow, since YYSTYPE_IS_TRIVIAL isn't defined #define YYMAXDEPTH 5000 // See VParseGrammar.h for the C++ interface to this parser // Include that instead of VParseBison.h //************************************************************************* #define GRAMMARP VParseGrammar::staticGrammarp() #define PARSEP VParseGrammar::staticParsep() #define NEWSTRING(text) (string((text))) #define SPACED(a,b) ((a)+(((a)=="" || (b)=="")?"":" ")+(b)) #define VARS_PUSH() { GRAMMARP->m_varStack.push_back(GRAMMARP->m_var); } #define VARS_POP() { GRAMMARP->m_var = GRAMMARP->m_varStack.back(); GRAMMARP->m_varStack.pop_back(); } #define VARRESET_LIST(decl) { GRAMMARP->pinNum(1); VARRESET(); VARDECL(decl); } // Start of pinlist #define VARRESET_NONLIST(decl) { GRAMMARP->pinNum(0); VARRESET(); VARDECL(decl); } // Not in a pinlist #define VARRESET() { VARDECL(""); VARIO(""); VARNET(""); VARDTYPE(""); } // Start of one variable decl // VARDECL("") indicates inside a port list or IO list and we shouldn't declare the variable #define VARDECL(type) \ { GRAMMARP->m_var.m_decl = (type); } // genvar, parameter, localparam #define VARIO(type) \ { GRAMMARP->m_var.m_io = (type); } // input, output, inout, ref, const ref #define VARNET(type) \ { GRAMMARP->m_var.m_net = (type); } // supply*,wire,tri #define VARDTYPE(type) \ { GRAMMARP->m_var.m_dtype = (type); } // "signed", "int", etc #define PINNUMINC() { GRAMMARP->pinNumInc(); } #define INSTPREP(cellmod,cellparam,withinInst) { GRAMMARP->pinNum(1); GRAMMARP->m_cellMod=(cellmod); GRAMMARP->m_cellParam=(cellparam); GRAMMARP->m_withinInst = 1; } #define INSTDONE() { GRAMMARP->m_withinInst = 0; } enum net_idx {NI_NETNAME = 0, NI_MSB, NI_LSB}; static void VARDONE(VFileLine * fl, const string& name, const string& array, const string& value) { if (GRAMMARP->m_var.m_io != "" && GRAMMARP->m_var.m_decl == "") GRAMMARP->m_var.m_decl = "port"; if (GRAMMARP->m_var.m_decl != "") { PARSEP->varCb(fl, GRAMMARP->m_var.m_decl, name, PARSEP->symObjofUpward(), GRAMMARP->m_var.m_net, GRAMMARP->m_var.m_dtype, array, value); } if (GRAMMARP->m_var.m_io != "" || GRAMMARP->pinNum()) { PARSEP->portCb(fl, name, PARSEP->symObjofUpward(), GRAMMARP->m_var.m_io, GRAMMARP->m_var.m_dtype, array, GRAMMARP->pinNum()); } if (GRAMMARP->m_var.m_dtype == "type") { PARSEP->syms().replaceInsert(VAstType::TYPE, name); } } static void VARDONETYPEDEF(VFileLine* fl, const string& name, const string& type, const string& array) { VARRESET(); VARDECL("typedef"); VARDTYPE(type); VARDONE(fl,name,array,""); // TYPE shouldn't override a more specific node type, as often is forward reference PARSEP->syms().replaceInsert(VAstType::TYPE, name); } static void parse_net_constants(VFileLine* fl, VParseHashElem nets[][3]) { VParseHashElem (*net)[3] = &nets[0]; VParseHashElem* nhp = net[0]; std::deque::iterator it = GRAMMARP->m_portStack.begin(); while (it != GRAMMARP->m_portStack.end()) { // Default net name is simply the complete token const char* netnamep = it->m_name.c_str(); size_t delim = it->m_name.find_first_of("'"); if (it->m_name[0] != '\\' && it->m_msb.empty() && delim != string::npos && it->m_name[delim] == '\'') { // Handle sized integer constants (e.g., 7'b0) specifically but ignore replications (e.g., {4{w}}) if (delim != 0 && netnamep[0] != '{') { // Handle the first part that indicates the width for sized constants (guaranteed to be a decimal) char* endp; errno = 0; long l = strtol(netnamep, &endp, 10); if ((errno == ERANGE && l == LONG_MAX) || l > INT_MAX || l <= 0) { fl->error((string)"Unexpected length in size of integer constant: \""+netnamep+"\"."); return; } // Skip whitespace while (endp < netnamep + delim && isspace(*endp)) { endp++; } if (endp != netnamep + delim) { fl->error((string)"Could not convert size of integer constant: \""+netnamep+"\"."); return; } int count = l; // Skip characters up to the delimiter ' to determine new netnamep netnamep += delim; // Test for legal base specifiers: // d, D, h, H, o, O , b, or B for the decimal, hexadecimal, octal, and binary bases, respectively char base = netnamep[1]; // 's' indicates a signed constant, is followed by the actual base; currently ignored if (base == 's' || base == 'S') { base = netnamep[2]; } if (strchr("dDhHoObB", base) == NULL) { fl->error((string)"Base specifier \""+base+"\" is not valid in integer constant \""+it->m_name.c_str()+"\"."); return; } // These assignments could be prettified with C++11 nhp[NI_MSB].keyp = "msb"; nhp[NI_MSB].val_type = VParseHashElem::ELEM_INT; nhp[NI_MSB].val_int = count - 1; nhp[NI_LSB].keyp = "lsb"; nhp[NI_LSB].val_type = VParseHashElem::ELEM_INT; nhp[NI_LSB].val_int = 0; } else { // fl->error increases the error count which would create regressions for no good reasons. // There is no ->warn or similar though but we could print, e.g., to stderr in these cases //fl->error((string)"Neither unsized integer constant nor replications are not fully supported in nets (\""+netnamep+"\")."); //fprintf(stderr, "Neither unsized integer constant nor replications are not fully supported in nets (\"%s\").\n", netnamep); } } else { // Ordinary net names might have a range attached or not. // If it does then parse its bounds into proper integers. const char *msbstr = it->m_msb.c_str(); if (msbstr[0] != '\0') { { // Parse NI_MSB char* endp; errno = 0; long l = strtol(msbstr, &endp, 10); // Test for range within int, and proper parsing if ((errno == ERANGE && l == LONG_MAX) || l > INT_MAX || l < 0 || (endp && l == 0 && errno == ERANGE)) { fl->error((string)"Unexpected length in msb specification of \""+netnamep+"\" (endp="+endp+", errno="+strerror(errno)+")."); return; } nhp[NI_MSB].keyp = "msb"; nhp[NI_MSB].val_type = VParseHashElem::ELEM_INT; nhp[NI_MSB].val_int = (int)l; } { // Parse NI_LSB char* endp; errno = 0; long l = strtol(it->m_lsb.c_str(), &endp, 10); if ((errno == ERANGE && l == LONG_MAX) || l > INT_MAX || l < 0 || (endp && l == 0 && errno == ERANGE)) { fl->error((string)"Unexpected length in lsb specification of \""+netnamep+"\"."); return; } nhp[NI_LSB].keyp = "lsb"; nhp[NI_LSB].val_type = VParseHashElem::ELEM_INT; nhp[NI_LSB].val_int = (int)l; } } else { nhp[NI_MSB].keyp = NULL; nhp[NI_LSB].keyp = NULL; } } nhp[NI_NETNAME].keyp = "netname"; nhp[NI_NETNAME].val_type = VParseHashElem::ELEM_STR; nhp[NI_NETNAME].val_str = netnamep; *it++; nhp += 3; // We operate on three elements in each iteration } } static void PINDONE(VFileLine* fl, const string& name, const string& expr) { if (GRAMMARP->m_cellParam) { // Stack them until we create the instance itself GRAMMARP->m_pinStack.push_back(VParseGPin(fl, name, expr, GRAMMARP->pinNum())); } else { PARSEP->pinCb(fl, name, expr, GRAMMARP->pinNum()); if (PARSEP->usePinSelects()) { if (GRAMMARP->m_portStack.empty()) { string netname; if (GRAMMARP->m_portNextNetName.empty()) { netname = expr; } else { netname = GRAMMARP->m_portNextNetName; } size_t elem_cnt = GRAMMARP->m_portNextNetMsb.empty() ? 1 : 3; VParseHashElem nets[elem_cnt]; // These assignments could be prettified with C++11 nets[NI_NETNAME].keyp = "netname"; nets[NI_NETNAME].val_type = VParseHashElem::ELEM_STR; nets[NI_NETNAME].val_str = netname; if (elem_cnt > 1) { nets[NI_MSB].keyp = "msb"; nets[NI_MSB].val_type = VParseHashElem::ELEM_STR; nets[NI_MSB].val_str = GRAMMARP->m_portNextNetMsb; nets[NI_LSB].keyp = "lsb"; nets[NI_LSB].val_type = VParseHashElem::ELEM_STR; nets[NI_LSB].val_str = GRAMMARP->m_portNextNetLsb; } PARSEP->pinselectsCb(fl, name, 1, elem_cnt, &nets[0], GRAMMARP->pinNum()); } else { // Connection with multiple pins was parsed completely. // There might be one net left in the pipe... if (GRAMMARP->m_portNextNetValid) { GRAMMARP->m_portStack.push_front(VParseNet(GRAMMARP->m_portNextNetName, GRAMMARP->m_portNextNetMsb, GRAMMARP->m_portNextNetLsb)); } unsigned int arraycnt = GRAMMARP->m_portStack.size(); VParseHashElem nets[arraycnt][3]; parse_net_constants(fl, nets); PARSEP->pinselectsCb(fl, name, arraycnt, 3, &nets[0][0], GRAMMARP->pinNum()); } // Clear all pin-related fields GRAMMARP->m_portNextNetValid = false; GRAMMARP->m_portNextNetName.clear(); GRAMMARP->m_portStack.clear(); GRAMMARP->m_portNextNetMsb.clear(); GRAMMARP->m_portNextNetLsb.clear(); } } } static void PINPARAMS() { // Throw out all the "pins" we found before we could do instanceCb while (!GRAMMARP->m_pinStack.empty()) { VParseGPin& pinr = GRAMMARP->m_pinStack.front(); PARSEP->parampinCb(pinr.m_fl, pinr.m_name, pinr.m_conn, pinr.m_number); GRAMMARP->m_pinStack.pop_front(); } GRAMMARP->m_withinPin = true; } static void PORTNET(VFileLine* fl, const string& name) { if (!GRAMMARP->m_withinInst) { return; } GRAMMARP->m_portNextNetValid = true; GRAMMARP->m_portNextNetName = name; GRAMMARP->m_portNextNetMsb.clear(); GRAMMARP->m_portNextNetLsb.clear(); } static void PORTRANGE(const string& msb, const string& lsb) { if (!GRAMMARP->m_withinInst) { return; } GRAMMARP->m_portNextNetMsb = msb; GRAMMARP->m_portNextNetLsb = lsb; } static void PIN_CONCAT_APPEND(const string& expr) { if (!GRAMMARP->m_withinPin) { return; } if (!GRAMMARP->m_portNextNetValid) { // Only while not within a valid net term the expression is part // of a replication constant. If that's detected ignore the // previous expression (that is actually just the contained // concatenation) in favor of the full replication expression. if (expr[0] == '{') { if (expr.find_first_of("{", 1) != string::npos) { // fprintf(stderr, "%d: ignoring \"%s\" in favor of \"%s\".\n", __LINE__, GRAMMARP->m_portStack.front().m_name.c_str(), expr.c_str()); GRAMMARP->m_portStack.pop_front(); GRAMMARP->m_portStack.push_front(VParseNet(expr)); } } else { GRAMMARP->m_portStack.push_front(VParseNet(expr)); } } else { GRAMMARP->m_portStack.push_front(VParseNet(GRAMMARP->m_portNextNetName, GRAMMARP->m_portNextNetMsb, GRAMMARP->m_portNextNetLsb)); } GRAMMARP->m_portNextNetValid = false; } /* Yacc */ static int VParseBisonlex(VParseBisonYYSType* yylvalp) { return PARSEP->lexToBison(yylvalp); } static void VParseBisonerror(const char *s) { VParseGrammar::bisonError(s); } static void ERRSVKWD(VFileLine* fileline, const string& tokname) { static int toldonce = 0; fileline->error((string)"Unexpected \""+tokname+"\": \""+tokname+"\" is a SystemVerilog keyword misused as an identifier."); if (!toldonce++) fileline->error("Modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language."); } static void NEED_S09(VFileLine*, const string&) { //Let lint tools worry about it //fileline->error((string)"Advanced feature: \""+tokname+"\" is a 1800-2009 construct, but used under --language 1800-2005 or earlier."); } // gcc-11 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98753 #if defined(__GNUC__) && __GNUC__ == 11 #pragma GCC diagnostic ignored "-Wfree-nonheap-object" #endif %} BISONPRE_VERSION(0.0, 2.999, %pure_parser) BISONPRE_VERSION(3.0, %pure-parser) BISONPRE_VERSION(0.0, 2.999, %token_table) BISONPRE_VERSION(3.0, %token-table) BISONPRE_VERSION(2.4, 2.999, %define lr.keep_unreachable_states) BISONPRE_VERSION(3.0, %define lr.keep-unreachable-state) // When writing Bison patterns we use yTOKEN instead of "token", // so Bison will error out on unknown "token"s. // Generic lexer tokens, for example a number // IEEE: real_number %token yaFLOATNUM "FLOATING-POINT NUMBER" // IEEE: identifier, class_identifier, class_variable_identifier, // covergroup_variable_identifier, dynamic_array_variable_identifier, // enum_identifier, interface_identifier, interface_instance_identifier, // package_identifier, type_identifier, variable_identifier, %token yaID__ETC "IDENTIFIER" %token yaID__LEX "IDENTIFIER-in-lex" %token yaID__aPACKAGE "PACKAGE-IDENTIFIER" %token yaID__aTYPE "TYPE-IDENTIFIER" // aCOVERGROUP is same as aTYPE // Can't predecode aFUNCTION, can declare after use // Can't predecode aINTERFACE, can declare after use // Can't predecode aTASK, can declare after use // IEEE: integral_number %token yaINTNUM "INTEGER NUMBER" // IEEE: time_literal + time_unit %token yaTIMENUM "TIME NUMBER" // IEEE: string_literal %token yaSTRING "STRING" %token yaSTRING__IGNORE "STRING-ignored" // Used when expr:string not allowed %token yaTIMINGSPEC "TIMING SPEC ELEMENT" %token ygenGATE "GATE keyword" %token ygenCONFIGKEYWORD "CONFIG keyword (cell/use/design/etc)" %token ygenOPERATOR "OPERATOR" %token ygenSTRENGTH "STRENGTH keyword (strong1/etc)" %token ygenSYSCALL "SYSCALL" %token '!' %token '#' %token '%' %token '&' %token '(' %token ')' %token '*' %token '+' %token ',' %token '-' %token '.' %token '/' %token ':' %token ';' %token '<' %token '=' %token '>' %token '?' %token '@' %token '[' %token ']' %token '^' %token '{' %token '|' %token '}' %token '~' // Specific keywords // yKEYWORD means match "keyword" // Other cases are yXX_KEYWORD where XX makes it unique, // for example yP_ for punctuation based operators. // Double underscores "yX__Y" means token X followed by Y, // and "yX__ETC" means X folled by everything but Y(s). %token yACCEPT_ON "accept_on" %token yALIAS "alias" %token yALWAYS "always" %token yAND "and" %token yASSERT "assert" %token yASSIGN "assign" %token yASSUME "assume" %token yAUTOMATIC "automatic" %token yBEFORE "before" %token yBEGIN "begin" %token yBIND "bind" %token yBINS "bins" %token yBINSOF "binsof" %token yBIT "bit" %token yBREAK "break" %token yBUF "buf" %token yBYTE "byte" %token yCASE "case" %token yCASEX "casex" %token yCASEZ "casez" %token yCHANDLE "chandle" %token yCHECKER "checker" %token yCLASS "class" %token yCLOCK "clock" %token yCLOCKING "clocking" %token yCONSTRAINT "constraint" %token yCONST__ETC "const" %token yCONST__LEX "const-in-lex" %token yCONST__LOCAL "const-then-local" %token yCONST__REF "const-then-ref" %token yCONTEXT "context" %token yCONTINUE "continue" %token yCOVER "cover" %token yCOVERGROUP "covergroup" %token yCOVERPOINT "coverpoint" %token yCROSS "cross" %token yDEASSIGN "deassign" %token yDEFAULT "default" %token yDEFPARAM "defparam" %token yDISABLE "disable" %token yDIST "dist" %token yDO "do" %token yEDGE "edge" %token yELSE "else" %token yEND "end" %token yENDCASE "endcase" %token yENDCHECKER "endchecker" %token yENDCLASS "endclass" %token yENDCLOCKING "endclocking" %token yENDFUNCTION "endfunction" %token yENDGENERATE "endgenerate" %token yENDGROUP "endgroup" %token yENDINTERFACE "endinterface" %token yENDMODULE "endmodule" %token yENDPACKAGE "endpackage" %token yENDPROGRAM "endprogram" %token yENDPROPERTY "endproperty" %token yENDSEQUENCE "endsequence" %token yENDSPECIFY "endspecify" %token yENDTABLE "endtable" %token yENDTASK "endtask" %token yENUM "enum" %token yEVENT "event" %token yEVENTUALLY "eventually" %token yEXPECT "expect" %token yEXPORT "export" %token yEXTENDS "extends" %token yEXTERN "extern" %token yFINAL "final" %token yFIRST_MATCH "first_match" %token yFOR "for" %token yFORCE "force" %token yFOREACH "foreach" %token yFOREVER "forever" %token yFORK "fork" %token yFORKJOIN "forkjoin" %token yFUNCTION__ETC "function" %token yFUNCTION__LEX "function-in-lex" %token yFUNCTION__aPUREV "function-is-pure-virtual" %token yGENERATE "generate" %token yGENVAR "genvar" %token yGLOBAL__CLOCKING "global-then-clocking" %token yGLOBAL__LEX "global-in-lex" %token yIF "if" %token yIFF "iff" %token yIGNORE_BINS "ignore_bins" %token yILLEGAL_BINS "illegal_bins" %token yIMPLEMENTS "implements" %token yIMPLIES "implies" %token yIMPORT "import" %token yINITIAL "initial" %token yINOUT "inout" %token yINPUT "input" %token yINSIDE "inside" %token yINT "int" %token yINTEGER "integer" %token yINTERCONNECT "interconnect" %token yINTERFACE "interface" %token yINTERSECT "intersect" %token yJOIN "join" %token yLET "let" %token yLOCALPARAM "localparam" %token yLOCAL__COLONCOLON "local-then-::" %token yLOCAL__ETC "local" %token yLOCAL__LEX "local-in-lex" %token yLOGIC "logic" %token yLONGINT "longint" %token yMATCHES "matches" %token yMODPORT "modport" %token yMODULE "module" %token yNAND "nand" %token yNEGEDGE "negedge" %token yNETTYPE "nettype" %token yNEW__ETC "new" %token yNEW__LEX "new-in-lex" %token yNEW__PAREN "new-then-paren" %token yNEXTTIME "nexttime" %token yNOR "nor" %token yNOT "not" %token yNULL "null" %token yOR "or" %token yOUTPUT "output" %token yPACKAGE "package" %token yPACKED "packed" %token yPARAMETER "parameter" %token yPOSEDGE "posedge" %token yPRIORITY "priority" %token yPROGRAM "program" %token yPROPERTY "property" %token yPROTECTED "protected" %token yPURE "pure" %token yRAND "rand" %token yRANDC "randc" %token yRANDCASE "randcase" %token yRANDSEQUENCE "randsequence" %token yREAL "real" %token yREALTIME "realtime" %token yREF "ref" %token yREG "reg" %token yREJECT_ON "reject_on" %token yRELEASE "release" %token yREPEAT "repeat" %token yRESTRICT "restrict" %token yRETURN "return" %token ySCALARED "scalared" %token ySEQUENCE "sequence" %token ySHORTINT "shortint" %token ySHORTREAL "shortreal" %token ySIGNED "signed" %token ySOFT "soft" %token ySOLVE "solve" %token ySPECIFY "specify" %token ySPECPARAM "specparam" %token ySTATIC__CONSTRAINT "static-then-constraint" %token ySTATIC__ETC "static" %token ySTATIC__LEX "static-in-lex" %token ySTRING "string" %token ySTRONG "strong" %token ySTRUCT "struct" %token ySUPER "super" %token ySUPPLY0 "supply0" %token ySUPPLY1 "supply1" %token ySYNC_ACCEPT_ON "sync_accept_on" %token ySYNC_REJECT_ON "sync_reject_on" %token yS_ALWAYS "s_always" %token yS_EVENTUALLY "s_eventually" %token yS_NEXTTIME "s_nexttime" %token yS_UNTIL "s_until" %token yS_UNTIL_WITH "s_until_with" %token yTABLE "table" %token yTAGGED "tagged" %token yTASK__ETC "task" %token yTASK__LEX "task-in-lex" %token yTASK__aPUREV "task-is-pure-virtual" %token yTHIS "this" %token yTHROUGHOUT "throughout" %token yTIME "time" %token yTIMEPRECISION "timeprecision" %token yTIMEUNIT "timeunit" %token yTRI "tri" %token yTRI0 "tri0" %token yTRI1 "tri1" %token yTRIAND "triand" %token yTRIOR "trior" %token yTRIREG "trireg" %token yTYPE "type" %token yTYPEDEF "typedef" %token yUNION "union" %token yUNIQUE "unique" %token yUNIQUE0 "unique0" %token yUNSIGNED "unsigned" %token yUNTIL "until" %token yUNTIL_WITH "until_with" %token yUNTYPED "untyped" %token yVAR "var" %token yVECTORED "vectored" %token yVIRTUAL__CLASS "virtual-then-class" %token yVIRTUAL__ETC "virtual" %token yVIRTUAL__INTERFACE "virtual-then-interface" %token yVIRTUAL__LEX "virtual-in-lex" %token yVIRTUAL__anyID "virtual-then-identifier" %token yVOID "void" %token yWAIT "wait" %token yWAIT_ORDER "wait_order" %token yWAND "wand" %token yWEAK "weak" %token yWHILE "while" %token yWILDCARD "wildcard" %token yWIRE "wire" %token yWITHIN "within" %token yWITH__BRA "with-then-[" %token yWITH__CUR "with-then-{" %token yWITH__ETC "with" %token yWITH__LEX "with-in-lex" %token yWITH__PAREN "with-then-(" %token yWOR "wor" %token yXNOR "xnor" %token yXOR "xor" %token yD_ERROR "$error" %token yD_FATAL "$fatal" %token yD_INFO "$info" %token yD_ROOT "$root" %token yD_UNIT "$unit" %token yD_WARNING "$warning" %token yP_TICK "'" %token yP_TICKBRA "'{" %token yP_OROR "||" %token yP_ANDAND "&&" %token yP_NOR "~|" %token yP_XNOR "^~" %token yP_NAND "~&" %token yP_EQUAL "==" %token yP_NOTEQUAL "!=" %token yP_CASEEQUAL "===" %token yP_CASENOTEQUAL "!==" %token yP_WILDEQUAL "==?" %token yP_WILDNOTEQUAL "!=?" %token yP_GTE ">=" %token yP_LTE "<=" %token yP_LTE__IGNORE "<=-ignored" // Used when expr:<= means assignment %token yP_SLEFT "<<" %token yP_SRIGHT ">>" %token yP_SSRIGHT ">>>" %token yP_POW "**" %token yP_PAR__IGNORE "(-ignored" // Used when sequence_expr:expr:( is ignored %token yP_PAR__STRENGTH "(-for-strength" %token yP_LTMINUSGT "<->" %token yP_PLUSCOLON "+:" %token yP_MINUSCOLON "-:" %token yP_MINUSGT "->" %token yP_MINUSGTGT "->>" %token yP_EQGT "=>" %token yP_ASTGT "*>" %token yP_ANDANDAND "&&&" %token yP_POUNDPOUND "##" %token yP_POUNDMINUSPD "#-#" %token yP_POUNDEQPD "#=#" %token yP_DOTSTAR ".*" %token yP_ATAT "@@" %token yP_COLONCOLON "::" %token yP_COLONEQ ":=" %token yP_COLONDIV ":/" %token yP_ORMINUSGT "|->" %token yP_OREQGT "|=>" %token yP_BRASTAR "[*" %token yP_BRAEQ "[=" %token yP_BRAMINUSGT "[->" %token yP_BRAPLUSKET "[+]" %token yP_PLUSPLUS "++" %token yP_MINUSMINUS "--" %token yP_PLUSEQ "+=" %token yP_MINUSEQ "-=" %token yP_TIMESEQ "*=" %token yP_DIVEQ "/=" %token yP_MODEQ "%=" %token yP_ANDEQ "&=" %token yP_OREQ "|=" %token yP_XOREQ "^=" %token yP_SLEFTEQ "<<=" %token yP_SRIGHTEQ ">>=" %token yP_SSRIGHTEQ ">>>=" // '( is not a operator, as "' (" is legal //******************** // Verilog op precedence %token prUNARYARITH %token prREDUCTION %token prNEGATION %token prEVENTBEGIN %token prTAGGED // These prevent other conflicts %left yP_ANDANDAND %left yMATCHES %left prTAGGED %left prSEQ_CLOCKING // Lowest precedence // These are in IEEE 17.7.1 %nonassoc yALWAYS yS_ALWAYS yEVENTUALLY yS_EVENTUALLY yACCEPT_ON yREJECT_ON ySYNC_ACCEPT_ON ySYNC_REJECT_ON %right yP_ORMINUSGT yP_OREQGT yP_POUNDMINUSPD yP_POUNDEQPD %right yUNTIL yS_UNTIL yUNTIL_WITH yS_UNTIL_WITH yIMPLIES %right yIFF %left yOR %left yAND %nonassoc yNOT yNEXTTIME yS_NEXTTIME %left yINTERSECT %left yWITHIN %right yTHROUGHOUT %left prPOUNDPOUND_MULTI %left yP_POUNDPOUND %left yP_BRASTAR yP_BRAEQ yP_BRAMINUSGT yP_BRAPLUSKET // Not specified, but needed higher than yOR, lower than normal non-pexpr expressions %left yPOSEDGE yNEGEDGE yEDGE %left '{' '}' //%nonassoc '=' yP_PLUSEQ yP_MINUSEQ yP_TIMESEQ yP_DIVEQ yP_MODEQ yP_ANDEQ yP_OREQ yP_XOREQ yP_SLEFTEQ yP_SRIGHTEQ yP_SSRIGHTEQ yP_COLONEQ yP_COLONDIV yP_LTE %right yP_MINUSGT yP_LTMINUSGT %right '?' ':' %left yP_OROR %left yP_ANDAND %left '|' yP_NOR %left '^' yP_XNOR %left '&' yP_NAND %left yP_EQUAL yP_NOTEQUAL yP_CASEEQUAL yP_CASENOTEQUAL yP_WILDEQUAL yP_WILDNOTEQUAL %left '>' '<' yP_GTE yP_LTE yP_LTE__IGNORE yINSIDE yDIST %left yP_SLEFT yP_SRIGHT yP_SSRIGHT %left '+' '-' %left '*' '/' '%' %left yP_POW %left prUNARYARITH yP_MINUSMINUS yP_PLUSPLUS prREDUCTION prNEGATION %left '.' // Not in IEEE, but need to avoid conflicts; TICK should bind tightly just lower than COLONCOLON %left yP_TICK //%left '(' ')' '[' ']' yP_COLONCOLON '.' %nonassoc prLOWER_THAN_ELSE %nonassoc yELSE //BISONPRE_TYPES // Blank lines for type insertion // Blank lines for type insertion // Blank lines for type insertion // Blank lines for type insertion // Blank lines for type insertion // Blank lines for type insertion // Blank lines for type insertion // Blank lines for type insertion // Blank lines for type insertion // Blank lines for type insertion // Blank lines for type insertion // Blank lines for type insertion // Blank lines for type insertion // Blank lines for type insertion // Blank lines for type insertion // Blank lines for type insertion // Blank lines for type insertion // Blank lines for type insertion // Blank lines for type insertion // Blank lines for type insertion // Blank lines for type insertion // Blank lines for type insertion // Blank lines for type insertion // Blank lines for type insertion // Blank lines for type insertion // Blank lines for type insertion // Blank lines for type insertion // Blank lines for type insertion // Blank lines for type insertion // Blank lines for type insertion %start source_text %% //********************************************************************** // Feedback to the Lexer // Note we read a parenthesis ahead, so this may not change the lexer at the right point. statePushVlg: // For PSL lexing, escape current state into Verilog state /* empty */ { } ; statePop: // Return to previous lexing state /* empty */ { } ; //********************************************************************** // Files source_text: // ==IEEE: source_text /* empty */ { } // // timeunits_declaration moved into description:package_item | descriptionList { } ; descriptionList: // IEEE: part of source_text description { } | descriptionList description { } ; description: // ==IEEE: description module_declaration { } // // udp_declaration moved into module_declaration | interface_declaration { } | program_declaration { } | package_declaration { } | package_item { } | bind_directive { } // unsupported // IEEE: config_declaration | error { } ; timeunits_declaration: // ==IEEE: timeunits_declaration yTIMEUNIT yaTIMENUM ';' { } | yTIMEUNIT yaTIMENUM '/' yaTIMENUM ';' { NEED_S09($1,"timeunit /"); } | yTIMEPRECISION yaTIMENUM ';' { } ; //********************************************************************** // Packages package_declaration: // ==IEEE: package_declaration packageFront package_itemListE yENDPACKAGE endLabelE { PARSEP->endpackageCb($3,$3); PARSEP->symPopScope(VAstType::PACKAGE); } ; packageFront: // // Lifetime is 1800-2009 yPACKAGE lifetimeE idAny ';' { PARSEP->symPushNew(VAstType::PACKAGE, $3); PARSEP->packageCb($1,$1, $3); } ; package_itemListE: // IEEE: [{ package_item }] /* empty */ { } | package_itemList { } ; package_itemList: // IEEE: { package_item } package_item { } | package_itemList package_item { } ; package_item: // ==IEEE: package_item package_or_generate_item_declaration { } | anonymous_program { } | package_export_declaration { } | timeunits_declaration { } ; package_or_generate_item_declaration: // ==IEEE: package_or_generate_item_declaration net_declaration { } | data_declaration { } | task_declaration { } | function_declaration { } | checker_declaration { } | dpi_import_export { } | extern_constraint_declaration { } | class_declaration { } // // class_constructor_declaration is part of function_declaration | local_parameter_declaration ';' { } | parameter_declaration ';' { } | covergroup_declaration { } | overload_declaration { } | assertion_item_declaration { } | ';' { } ; package_import_declarationList: package_import_declaration { } | package_import_declarationList package_import_declaration { } ; package_import_declaration: // ==IEEE: package_import_declaration yIMPORT package_import_itemList ';' { } ; package_import_itemList: package_import_item { } | package_import_itemList ',' package_import_item { } ; package_import_item: // ==IEEE: package_import_item yaID__aPACKAGE yP_COLONCOLON package_import_itemObj { PARSEP->syms().import($1,$1,$3); PARSEP->importCb($1,$1,$3); } ; package_import_itemObj: // IEEE: part of package_import_item idAny { $$=$1; $$=$1; } | '*' { $$=$1; $$=$1; } ; package_export_declaration: // IEEE: package_export_declaration yEXPORT '*' yP_COLONCOLON '*' ';' { } | yEXPORT package_import_itemList ';' { } ; //********************************************************************** // Module headers module_declaration: // ==IEEE: module_declaration // // timeunits_declaration instead in module_item // // IEEE: module_nonansi_header + module_ansi_header modFront importsAndParametersE portsStarE ';' module_itemListE yENDMODULE endLabelE { PARSEP->endmoduleCb($6,$6); PARSEP->symPopScope(VAstType::MODULE); } // | yEXTERN modFront importsAndParametersE portsStarE ';' { PARSEP->symPopScope(VAstType::MODULE); } ; modFront: // // General note: all *Front functions must call symPushNew before // // any formal arguments, as the arguments must land in the new scope. yMODULE lifetimeE idAny { PARSEP->symPushNew(VAstType::MODULE, $3); PARSEP->moduleCb($1,$1,$3,false,PARSEP->inCellDefine()); } ; importsAndParametersE: // IEEE: common part of module_declaration, interface_declaration, program_declaration // // { package_import_declaration } [ parameter_port_list ] parameter_port_listE { } | package_import_declarationList parameter_port_listE { } ; parameter_value_assignmentE: // IEEE: [ parameter_value_assignment ] /* empty */ { } | '#' '(' cellpinList ')' { } // // Side effect of combining *_instantiations | '#' delay_value { } ; parameter_port_listE: // IEEE: parameter_port_list + empty == parameter_value_assignment /* empty */ { } | '#' '(' ')' { } // // IEEE: '#' '(' list_of_param_assignments { ',' parameter_port_declaration } ')' // // IEEE: '#' '(' parameter_port_declaration { ',' parameter_port_declaration } ')' // // Can't just do that as "," conflicts with between vars and between stmts, so // // split into pre-comma and post-comma parts | '#' '(' {VARRESET_LIST("parameter");} paramPortDeclOrArgList ')' { VARRESET_NONLIST(""); } // // Note legal to start with "a=b" with no parameter statement ; paramPortDeclOrArgList: // IEEE: list_of_param_assignments + { parameter_port_declaration } paramPortDeclOrArg { } | paramPortDeclOrArgList ',' paramPortDeclOrArg { } ; paramPortDeclOrArg: // IEEE: param_assignment + parameter_port_declaration // // We combine the two as we can't tell which follows a comma param_assignment { } | parameter_port_declarationFront param_assignment { } ; portsStarE: // IEEE: .* + list_of_ports + list_of_port_declarations + empty /* empty */ { } // // .* expanded from module_declaration // // '(' ')' handled by list_of_ports:portE | '(' yP_DOTSTAR ')' { } | '(' {VARRESET_LIST("");} list_of_portsE ')' { VARRESET_NONLIST(""); } ; list_of_portsE: // IEEE: list_of_ports + list_of_port_declarations portE { } | list_of_portsE ',' portE { } ; portE: // ==IEEE: [ port ] // // Though not type for interfaces, we factor out the port direction and type // // so we can simply handle it in one place // // // IEEE: interface_port_header port_identifier { unpacked_dimension } // // Expanded interface_port_header // // We use instantCb here because the non-port form looks just like a module instantiation /* empty */ { } | portDirNetE id/*interface*/ idAny/*port*/ variable_dimensionListE sigAttrListE { VARDTYPE($2); VARIO("interface"); VARDONE($2, $3, $4, ""); PINNUMINC(); PARSEP->instantCb($2, $2, $3, $4); PARSEP->endcellCb($2,""); } | portDirNetE yINTERFACE idAny/*port*/ variable_dimensionListE sigAttrListE { VARDTYPE($2); VARIO("interface"); VARDONE($2, $3, $4, ""); PINNUMINC(); } | portDirNetE id/*interface*/ '.' idAny/*modport*/ idAny/*port*/ variable_dimensionListE sigAttrListE { VARDTYPE($2+"."+$4); VARIO("interface"); VARDONE($2, $5, $6, ""); PINNUMINC(); PARSEP->instantCb($2, $2, $5, $6); PARSEP->endcellCb($2,""); } | portDirNetE yINTERFACE '.' idAny/*modport*/ idAny/*port*/ variable_dimensionListE sigAttrListE { VARDTYPE($2+"."+$4); VARIO("interface"); VARDONE($2, $5, $6, ""); PINNUMINC(); } // // // IEEE: ansi_port_declaration, with [port_direction] removed // // IEEE: [ net_port_header | interface_port_header ] port_identifier { unpacked_dimension } [ '=' constant_expression ] // // IEEE: [ net_port_header | variable_port_header ] '.' port_identifier '(' [ expression ] ')' // // IEEE: [ variable_port_header ] port_identifier { variable_dimension } [ '=' constant_expression ] // // Substitute net_port_header = [ port_direction ] net_port_type // // Substitute variable_port_header = [ port_direction ] variable_port_type // // Substitute net_port_type = [ net_type ] data_type_or_implicit // // Substitute variable_port_type = var_data_type // // [ [ port_direction ] net_port_type | interface_port_header ] port_identifier { unpacked_dimension } // // [ [ port_direction ] var_data_type ] port_identifier variable_dimensionListE [ '=' constant_expression ] // // [ [ port_direction ] net_port_type | [ port_direction ] var_data_type ] '.' port_identifier '(' [ expression ] ')' // // // Remove optional '[...] id' is in portAssignment // // Remove optional '[port_direction]' is in port // // net_port_type | interface_port_header port_identifier { unpacked_dimension } // // net_port_type | interface_port_header port_identifier { unpacked_dimension } // // var_data_type port_identifier variable_dimensionListE [ '=' constExpr ] // // net_port_type | [ port_direction ] var_data_type '.' port_identifier '(' [ expr ] ')' // // Expand implicit_type // // // IEEE-2012: Since a net_type_identifier is a data_type, it falls into // // the rules here without change. // // // variable_dimensionListE instead of rangeListE to avoid conflicts // // // Note implicit rules looks just line declaring additional followon port // // No VARDECL("port") for implicit, as we don't want to declare variables for them | portDirNetE var_data_type '.' portSig '(' portAssignExprE ')' sigAttrListE { VARDTYPE($2); VARDONE($4, $4, "", ""); PINNUMINC(); } | portDirNetE signing '.' portSig '(' portAssignExprE ')' sigAttrListE { VARDTYPE($2); VARDONE($4, $4, "", ""); PINNUMINC(); } | portDirNetE signingE variable_dimensionList '.' portSig '(' portAssignExprE ')' sigAttrListE { VARDTYPE(SPACED($2,$3)); VARDONE($5, $5, "", ""); PINNUMINC(); } | portDirNetE yINTERCONNECT signingE variable_dimensionListE '.' portSig '(' portAssignExprE ')' sigAttrListE { VARDTYPE(SPACED(SPACED($2,$3),$4)); VARDONE($6, $6, "", ""); PINNUMINC(); } | portDirNetE /*implicit*/ '.' portSig '(' portAssignExprE ')' sigAttrListE { /*VARDTYPE-same*/ VARDONE($3, $3, "", ""); PINNUMINC(); } // | portDirNetE var_data_type portSig variable_dimensionListE sigAttrListE { VARDTYPE($2); VARDONE($3, $3, $4, ""); PINNUMINC(); } | portDirNetE signing portSig variable_dimensionListE sigAttrListE { VARDTYPE($2); VARDONE($3, $3, $4, ""); PINNUMINC(); } | portDirNetE signingE variable_dimensionList portSig variable_dimensionListE sigAttrListE { VARDTYPE(SPACED($2,$3)); VARDONE($4, $4, $5, ""); PINNUMINC(); } | portDirNetE yINTERCONNECT signingE variable_dimensionList portSig variable_dimensionListE sigAttrListE { VARDTYPE(SPACED(SPACED($2,$3),$4)); VARDONE($5, $5, $6, ""); PINNUMINC(); } | portDirNetE /*implicit*/ portSig variable_dimensionListE sigAttrListE { /*VARDTYPE-same*/ VARDONE($2, $2, $3, ""); PINNUMINC(); } // | portDirNetE var_data_type portSig variable_dimensionListE sigAttrListE '=' constExpr { VARDTYPE($2); VARDONE($3, $3, $4, $7); PINNUMINC(); } | portDirNetE signing portSig variable_dimensionListE sigAttrListE '=' constExpr { VARDTYPE($2); VARDONE($3, $3, $4, $7); PINNUMINC(); } | portDirNetE signingE variable_dimensionList portSig variable_dimensionListE sigAttrListE '=' constExpr { VARDTYPE(SPACED($2,$3)); VARDONE($4, $4, $5, $8); PINNUMINC(); } | portDirNetE yINTERCONNECT signingE variable_dimensionList portSig variable_dimensionListE sigAttrListE '=' constExpr { VARDTYPE(SPACED(SPACED($2,$3),$4)); VARDONE($5, $5, $6, $9); PINNUMINC(); } | portDirNetE /*implicit*/ portSig variable_dimensionListE sigAttrListE '=' constExpr { /*VARDTYPE-same*/ VARDONE($2, $2, $3, $6); PINNUMINC(); } // | '{' list_of_portsE '}' { } ; portDirNetE: // IEEE: part of port, optional net type and/or direction /* empty */ { } // // Per spec, if direction given default the nettype. // // The higher level rule may override this VARDTYPE with one later in the parse. | port_direction { VARDTYPE(""/*default_nettype*/); } | port_direction net_type { VARDTYPE(""/*default_nettype*/); } // net_type calls VARNET | net_type { } // net_type calls VARNET ; port_declNetE: // IEEE: part of port_declaration, optional net type /* empty */ { } | net_type { } // net_type calls VARNET ; portAssignExprE: // IEEE: part of port, optional expression /* empty */ { } | expr { } ; portSig: id/*port*/ { $$=$1; $$=$1; } | idSVKwd { $$=$1; $$=$1; } ; //********************************************************************** // Interface headers interface_declaration: // IEEE: interface_declaration + interface_nonansi_header + interface_ansi_header: // // timeunits_delcarationE is instead in interface_item intFront importsAndParametersE portsStarE ';' interface_itemListE yENDINTERFACE endLabelE { PARSEP->endinterfaceCb($6, $6); PARSEP->symPopScope(VAstType::INTERFACE); } | yEXTERN intFront importsAndParametersE portsStarE ';' { } ; intFront: yINTERFACE lifetimeE idAny/*new_interface*/ { PARSEP->symPushNew(VAstType::INTERFACE,$3); PARSEP->interfaceCb($1,$1,$3); } ; interface_itemListE: /* empty */ { } | interface_itemList { } ; interface_itemList: interface_item { } | interface_itemList interface_item { } ; interface_item: // IEEE: interface_item + non_port_interface_item port_declaration ';' { } // // IEEE: non_port_interface_item | generate_region { } | interface_or_generate_item { } | program_declaration { } // // IEEE 1800-2017: modport_item // // See instead old 2012 position in interface_or_generate_item | interface_declaration { } | timeunits_declaration { } // // See note in interface_or_generate item | module_common_item { } ; interface_or_generate_item: // ==IEEE: interface_or_generate_item // // module_common_item in interface_item, as otherwise duplicated // // with module_or_generate_item:module_common_item // // IEEE 1800-2017 removes modport_declaration here // // but for 2012 compatibility we retain it modport_declaration { } | extern_tf_declaration { } ; //********************************************************************** // Program headers anonymous_program: // ==IEEE: anonymous_program // // See the spec - this doesn't change the scope, items still go up "top" yPROGRAM ';' anonymous_program_itemListE yENDPROGRAM { } ; anonymous_program_itemListE: // IEEE: { anonymous_program_item } /* empty */ { } | anonymous_program_itemList { } ; anonymous_program_itemList: // IEEE: { anonymous_program_item } anonymous_program_item { } | anonymous_program_itemList anonymous_program_item { } ; anonymous_program_item: // ==IEEE: anonymous_program_item task_declaration { } | function_declaration { } | class_declaration { } | covergroup_declaration { } // // class_constructor_declaration is part of function_declaration | ';' { } ; program_declaration: // IEEE: program_declaration + program_nonansi_header + program_ansi_header: // // timeunits_delcarationE is instead in program_item pgmFront importsAndParametersE portsStarE ';' program_itemListE yENDPROGRAM endLabelE { PARSEP->endprogramCb($6,$6); PARSEP->symPopScope(VAstType::PROGRAM); } | yEXTERN pgmFront importsAndParametersE portsStarE ';' { PARSEP->symPopScope(VAstType::PROGRAM); } ; pgmFront: yPROGRAM lifetimeE idAny/*new_program*/ { PARSEP->symPushNew(VAstType::PROGRAM,$3); PARSEP->programCb($1,$1, $3); } ; program_itemListE: // ==IEEE: [{ program_item }] /* empty */ { } | program_itemList { } ; program_itemList: // ==IEEE: { program_item } program_item { } | program_itemList program_item { } ; program_item: // ==IEEE: program_item port_declaration ';' { } | non_port_program_item { } ; non_port_program_item: // ==IEEE: non_port_program_item continuous_assign { } | module_or_generate_item_declaration { } | initial_construct { } | final_construct { } | concurrent_assertion_item { } | timeunits_declaration { } | program_generate_item { } ; program_generate_item: // ==IEEE: program_generate_item loop_generate_construct { } | conditional_generate_construct { } | generate_region { } | elaboration_system_task { } ; extern_tf_declaration: // ==IEEE: extern_tf_declaration yEXTERN task_prototype ';' { } | yEXTERN function_prototype ';' { } | yEXTERN yFORKJOIN task_prototype ';' { } ; modport_declaration: // ==IEEE: modport_declaration yMODPORT modport_itemList ';' { } ; modport_itemList: // IEEE: part of modport_declaration modport_item { } | modport_itemList ',' modport_item { } ; modport_item: // ==IEEE: modport_item modport_idFront '(' {VARRESET_LIST("");} modportPortsDeclList ')' { VARRESET_NONLIST(""); PARSEP->endmodportCb($1, "endmodport"); PARSEP->symPopScope(VAstType::MODPORT); } ; modport_idFront: id/*new-modport*/ { PARSEP->symPushNew(VAstType::MODPORT,$1); PARSEP->modportCb($1,"modport",$1); } ; modportPortsDeclList: modportPortsDecl { } | modportPortsDeclList ',' modportPortsDecl { } ; // IEEE: modport_ports_declaration + modport_simple_ports_declaration // + (modport_tf_ports_declaration+import_export) + modport_clocking_declaration // We've expanded the lists each take to instead just have standalone ID ports. // We track the type as with the V2k series of defines, then create as each ID is seen. modportPortsDecl: // // IEEE: modport_simple_ports_declaration port_direction modportSimplePort { } // // IEEE: modport_clocking_declaration | yCLOCKING idAny/*clocking_identifier*/ { } | yIMPORT modport_tf_port { } | yEXPORT modport_tf_port { } // Continuations of above after a comma. // // IEEE: modport_simple_ports_declaration | modportSimplePort { } ; modportSimplePort: // IEEE: modport_simple_port or modport_tf_port, depending what keyword was earlier // // Note 'init' field is used to say what to connect to id { VARDONE($1,$1,"",$1); PINNUMINC(); } | '.' idAny '(' ')' { VARDONE($1,$2,"",""); PINNUMINC(); } | '.' idAny '(' expr ')' { VARDONE($1,$2,"",$4); PINNUMINC(); } ; modport_tf_port: // ==IEEE: modport_tf_port id/*tf_identifier*/ { } | method_prototype { } ; //************************************************ // Variable Declarations genvar_declaration: // ==IEEE: genvar_declaration yGENVAR list_of_genvar_identifiers ';' { } ; list_of_genvar_identifiers: // IEEE: list_of_genvar_identifiers (for declaration) genvar_identifierDecl { } | list_of_genvar_identifiers ',' genvar_identifierDecl { } ; genvar_identifierDecl: // IEEE: genvar_identifier (for declaration) id/*new-genvar_identifier*/ sigAttrListE { VARRESET_NONLIST("genvar"); VARDONE($1, $1, "", ""); } ; local_parameter_declaration: // IEEE: local_parameter_declaration // // See notes in parameter_declaration local_parameter_declarationFront list_of_param_assignments { } ; parameter_declaration: // IEEE: parameter_declaration // // IEEE: yPARAMETER yTYPE list_of_type_assignments ';' // // Instead of list_of_type_assignments // // we use list_of_param_assignments because for port handling // // it already must accept types, so simpler to have code only one place parameter_declarationFront list_of_param_assignments { } ; local_parameter_declarationFront: // IEEE: local_parameter_declaration w/o assignment varLParamReset implicit_typeE { VARRESET(); VARDECL("localparam"); VARDTYPE($2); } | varLParamReset data_type { VARRESET(); VARDECL("localparam"); VARDTYPE($2); } | varLParamReset yTYPE { VARRESET(); VARDECL("localparam"); VARDTYPE($2); } ; parameter_declarationFront: // IEEE: parameter_declaration w/o assignment varGParamReset implicit_typeE { VARRESET(); VARDECL("parameter"); VARDTYPE($2); } | varGParamReset data_type { VARRESET(); VARDECL("parameter"); VARDTYPE($2); } | varGParamReset yTYPE { VARRESET(); VARDECL("parameter"); VARDTYPE($2); } ; parameter_port_declarationFront: // IEEE: parameter_port_declaration w/o assignment // // IEEE: parameter_declaration (minus assignment) parameter_declarationFront { } | local_parameter_declarationFront { /*NEED_S09(CURLINE(),"port localparams");*/ } // | data_type { VARDTYPE($1); } | yTYPE { VARDTYPE($1); } ; net_declaration: // IEEE: net_declaration - excluding implict net_declarationFront netSigList ';' { } ; net_declarationFront: // IEEE: beginning of net_declaration net_declRESET net_type strengthSpecE net_scalaredE net_dataType { VARDTYPE(SPACED($4,$5)); } | net_declRESET yINTERCONNECT signingE rangeListE { VARNET($2); VARDTYPE(SPACED($3,$4)); } ; net_declRESET: /* empty */ { VARRESET_NONLIST("net"); } ; net_scalaredE: /* empty */ { $$=""; } | ySCALARED { $$=$1; $$=$1; } | yVECTORED { $$=$1; $$=$1; } ; net_dataType: // // If there's a SV data type there shouldn't be a delay on this wire // // Otherwise #(...) can't be determined to be a delay or parameters // // Submit this as a footnote to the committee var_data_type { $$=$1; $$=$1; } | signingE rangeList delayE { $$=$1; $$=SPACED($1,$2); } | signing delayE { $$=$1; $$=$1; } | /*implicit*/ delayE { $$=$1; $$=""; } ; net_type: // ==IEEE: net_type ySUPPLY0 { VARNET($1); } | ySUPPLY1 { VARNET($1); } | yTRI { VARNET($1); } | yTRI0 { VARNET($1); } | yTRI1 { VARNET($1); } | yTRIAND { VARNET($1); } | yTRIOR { VARNET($1); } | yTRIREG { VARNET($1); } | yWAND { VARNET($1); } | yWIRE { VARNET($1); } | yWOR { VARNET($1); } ; varGParamReset: yPARAMETER { VARRESET_NONLIST($1); } ; varLParamReset: yLOCALPARAM { VARRESET_NONLIST($1); } ; port_direction: // ==IEEE: port_direction + tf_port_direction // // IEEE 19.8 just "input" FIRST forces type to wire - we'll ignore that here yINPUT { VARIO($1); } | yOUTPUT { VARIO($1); } | yINOUT { VARIO($1); } | yREF { VARIO($1); } | yCONST__REF yREF { VARIO($1); } ; port_directionReset: // IEEE: port_direction that starts a port_declaraiton // // Used only for declarations outside the port list yINPUT { VARRESET_NONLIST(""); VARIO($1); } | yOUTPUT { VARRESET_NONLIST(""); VARIO($1); } | yINOUT { VARRESET_NONLIST(""); VARIO($1); } | yREF { VARRESET_NONLIST(""); VARIO($1); } | yCONST__REF yREF { VARRESET_NONLIST(""); VARIO($1); } ; port_declaration: // ==IEEE: port_declaration // // Used inside block; followed by ';' // // SIMILAR to tf_port_declaration // // // IEEE: inout_declaration // // IEEE: input_declaration // // IEEE: output_declaration // // IEEE: ref_declaration port_directionReset port_declNetE var_data_type { VARDTYPE($3); } list_of_variable_decl_assignments { } | port_directionReset port_declNetE signingE rangeList { VARDTYPE(SPACED($3,$4)); } list_of_variable_decl_assignments { } | port_directionReset port_declNetE signing { VARDTYPE($3); } list_of_variable_decl_assignments { } | port_directionReset port_declNetE /*implicit*/ { VARDTYPE("");/*default_nettype*/} list_of_variable_decl_assignments { } // // IEEE: interface_declaration // // Looks just like variable declaration unless has a period // // See etcInst ; tf_port_declaration: // ==IEEE: tf_port_declaration // // Used inside function; followed by ';' // // SIMILAR to port_declaration // port_directionReset var_data_type { VARDTYPE($2); } list_of_tf_variable_identifiers ';' { } | port_directionReset implicit_typeE { VARDTYPE($2); } list_of_tf_variable_identifiers ';' { } ; integer_atom_type: // ==IEEE: integer_atom_type yBYTE { $$=$1; $$=$1; } | ySHORTINT { $$=$1; $$=$1; } | yINT { $$=$1; $$=$1; } | yLONGINT { $$=$1; $$=$1; } | yINTEGER { $$=$1; $$=$1; } | yTIME { $$=$1; $$=$1; } ; integer_vector_type: // ==IEEE: integer_atom_type yBIT { $$=$1; $$=$1; } | yLOGIC { $$=$1; $$=$1; } | yREG { $$=$1; $$=$1; } ; non_integer_type: // ==IEEE: non_integer_type ySHORTREAL { $$=$1; $$=$1; } | yREAL { $$=$1; $$=$1; } | yREALTIME { $$=$1; $$=$1; } ; signingE: // IEEE: signing - plus empty /*empty*/ { $$=""; } | signing { $$=$1; $$=$1; } ; signing: // ==IEEE: signing ySIGNED { $$=$1; $$=$1; } | yUNSIGNED { $$=$1; $$=$1; } ; //************************************************ // Data Types casting_type: // IEEE: casting_type simple_type { $$=$1; $$=$1; } // // IEEE: constant_primary // // In expr:cast this is expanded to just "expr" // // // IEEE: signing | ySIGNED { $$=$1; $$=$1; } | yUNSIGNED { $$=$1; $$=$1; } | ySTRING { $$=$1; $$=$1; } | yCONST__ETC/*then `*/ { $$=$1; $$=$1; } ; simple_type: // ==IEEE: simple_type // // IEEE: integer_type integer_atom_type { $$=$1; $$=$1; } | integer_vector_type { $$=$1; $$=$1; } | non_integer_type { $$=$1; $$=$1; } // // IEEE: ps_type_identifier // // IEEE: ps_parameter_identifier (presumably a PARAMETER TYPE) | package_scopeIdFollowsE yaID__aTYPE { $$=$1; $$=$1+$2; } // // { generate_block_identifer ... } '.' // // Need to determine if generate_block_identifier can be lex-detected ; data_typeVar: // IEEE: data_type + virtual_interface_declaration data_type { $$=$1; $$=$1; } // // IEEE-2009: virtual_interface_declaration // // IEEE-2012: part of data_type | yVIRTUAL__INTERFACE yINTERFACE id/*interface*/ parameter_value_assignmentE '.' id/*modport*/ { $$=$1; $$=SPACED($1,SPACED($2,$3)); } | yVIRTUAL__anyID id/*interface*/ parameter_value_assignmentE '.' id/*modport*/ { $$=$1; $$=SPACED($1,$2); } ; data_type: // ==IEEE: data_type, excluding class_type etc references integer_vector_type signingE rangeListE { $$=$1; $$=SPACED($1,SPACED($2,$3)); } | integer_atom_type signingE { $$=$1; $$=SPACED($1,$2); } | non_integer_type { $$=$1; $$=$1; } | ySTRUCT packedSigningE '{' { PARSEP->symPushNewAnon(VAstType::STRUCT); } /*cont*/ struct_union_memberList '}' packed_dimensionListE { $$=$1; $$=$1; PARSEP->symPopScope(VAstType::STRUCT); } | yUNION taggedE packedSigningE '{' { PARSEP->symPushNewAnon(VAstType::UNION); } /*cont*/ struct_union_memberList '}' packed_dimensionListE { $$=$1; $$=$1; PARSEP->symPopScope(VAstType::UNION); } | enumDecl { $$=$1; $$=$1; } | ySTRING { $$=$1; $$=$1; } | yCHANDLE { $$=$1; $$=$1; } // // Rules overlap virtual_interface_declaration // // Parameters here are SV2009 // // IEEE has ['.' modport] but that will conflict with port // // declarations which decode '.' modport themselves, so // // instead see data_typeVar | yVIRTUAL__INTERFACE yINTERFACE id/*interface*/ parameter_value_assignmentE { $$=$1; $$=SPACED($1,SPACED($2,$3)); } | yVIRTUAL__anyID id/*interface*/ parameter_value_assignmentE { $$=$1; $$=SPACED($1,$2); } // // // IEEE: [ class_scope | package_scope ] type_identifier { packed_dimension } // // See data_type // // IEEE: class_type // // See data_type | yEVENT { $$=$1; $$=$1; } | type_reference { $$=$1; $$=$1; } // //---------------------- // // REFERENCES // // // IEEE: [ class_scope | package_scope ] type_identifier { packed_dimension } // // IEEE: class_type // // IEEE: ps_covergroup_identifier // // Don't distinguish between types and classes so all these combined | package_scopeIdFollowsE class_typeOneList packed_dimensionListE { $$=$1; $$=$1+$2+$3; } ; // IEEE: struct_union - not needed, expanded in data_type data_type_or_void: // ==IEEE: data_type_or_void data_type { $$=$1; $$=$1; } | yVOID { $$=$1; $$=$1; } ; var_data_type: // ==IEEE: var_data_type data_type { $$=$1; $$=$1; } | yVAR data_type { $$=$1; $$=$1; } | yVAR implicit_typeE { $$=$1; $$=$1; } ; type_reference: // ==IEEE: type_reference yTYPE '(' exprOrDataType ')' { $$=$1; $$="type("+$3+")"; } ; struct_union_memberList: // IEEE: { struct_union_member } struct_union_member { } | struct_union_memberList struct_union_member { } ; struct_union_member: // ==IEEE: struct_union_member random_qualifierE data_type_or_void { VARS_PUSH(); // Structs can be recursive, or under a parameter typs VARRESET_NONLIST("member"); VARDTYPE(SPACED($1,$2)); } /*cont*/ list_of_variable_decl_assignments ';' { VARS_POP(); } ; list_of_variable_decl_assignments: // ==IEEE: list_of_variable_decl_assignments variable_decl_assignment { } | list_of_variable_decl_assignments ',' variable_decl_assignment { } ; variable_decl_assignment: // ==IEEE: variable_decl_assignment id variable_dimensionListE sigAttrListE { VARDONE($1, $1, $2, ""); } | id variable_dimensionListE sigAttrListE '=' variable_declExpr { VARDONE($1, $1, $2, $5); } | idSVKwd { } // // // IEEE: "dynamic_array_variable_identifier '[' ']' [ '=' dynamic_array_new ]" // // Matches above with variable_dimensionE = "[]" // // IEEE: "class_variable_identifier [ '=' class_new ]" // // variable_dimensionE must be empty // // Pushed into variable_declExpr:dynamic_array_new // // // IEEE: "[ covergroup_variable_identifier ] '=' class_new // // Pushed into variable_declExpr:class_new | '=' class_new { } ; list_of_tf_variable_identifiers: // ==IEEE: list_of_tf_variable_identifiers tf_variable_identifier { } | list_of_tf_variable_identifiers ',' tf_variable_identifier { } ; tf_variable_identifier: // IEEE: part of list_of_tf_variable_identifiers id variable_dimensionListE sigAttrListE { VARDONE($1, $1, $2, ""); } | id variable_dimensionListE sigAttrListE '=' expr { VARDONE($1, $1, $2, $5); } ; variable_declExpr: // IEEE: part of variable_decl_assignment - rhs of expr expr { $$=$1; $$=$1; } | dynamic_array_new { $$=$1; $$=$1; } | class_new { $$=$1; $$=$1; } ; variable_dimensionListE: // IEEE: variable_dimension + empty /*empty*/ { $$=""; } | variable_dimensionList { $$=$1; $$=$1; } ; variable_dimensionList: // IEEE: variable_dimension + empty variable_dimension { $$=$1; $$=$1; } | variable_dimensionList variable_dimension { $$=$1; $$=$1+$2; } ; variable_dimension: // ==IEEE: variable_dimension // // IEEE: unsized_dimension '[' ']' { $$=$1; $$=""; } // // IEEE: unpacked_dimension | anyrange { $$=$1; $$=$1; } // // IEEE: unpacked_dimension (if const_expr) // // IEEE: associative_dimension (if data_type) // // Can't tell which until see if expr is data type or not | '[' exprOrDataType ']' { $$=$1; $$="["+$2+"]"; } | yP_BRASTAR ']' { $$=$1; $$="[*]"; } | '[' '*' ']' { $$=$1; $$="[*]"; } // // IEEE: queue_dimension // // '[' '$' ']' -- $ is part of expr // // '[' '$' ':' expr ']' -- anyrange:expr:$ ; random_qualifierE: // IEEE: random_qualifier + empty /*empty*/ { $$=""; } | random_qualifier { $$=$1; $$=$1; } ; random_qualifier: // ==IEEE: random_qualifier yRAND { $$=$1; $$=$1; } | yRANDC { $$=$1; $$=$1; } ; taggedE: /*empty*/ { } | yTAGGED { } ; packedSigningE: /*empty*/ { } | yPACKED signingE { } ; //************************************************ // enum // IEEE: part of data_type enumDecl: yENUM enum_base_typeE '{' enum_nameList '}' rangeListE { $$=$2; } ; enum_base_typeE: // IEEE: enum_base_type /* empty */ { $$="enum"; } // // Not in spec, but obviously "enum [1:0]" should work // // implicit_type expanded, without empty | signingE rangeList { $$=$1; $$=$1+$2; } | signing { $$=$1; $$=$1; } // | integer_atom_type signingE { $$=$1; $$=SPACED($1,$2); } | integer_vector_type signingE regrangeE { $$=$1; $$=SPACED($1,SPACED($2,$3)); } // // below can be idAny or yaID__aTYPE // // IEEE requires a type, though no shift conflict if idAny // // IEEE: type_identifier [ packed_dimension ] // // however other simulators allow [ class_scope | package_scope ] type_identifier | idAny regrangeE { $$=$1; $$=SPACED($1,$2); } | package_scopeIdFollows idAny rangeListE { $$=$1; $$ = $1+$2+$3; } ; enum_nameList: enum_name_declaration { } | enum_nameList ',' enum_name_declaration { } ; enum_name_declaration: // ==IEEE: enum_name_declaration idAny/*enum_identifier*/ enumNameRangeE enumNameStartE { } ; enumNameRangeE: // IEEE: second part of enum_name_declaration /* empty */ { } | '[' intnumAsConst ']' { } | '[' intnumAsConst ':' intnumAsConst ']' { } ; enumNameStartE: // IEEE: third part of enum_name_declaration /* empty */ { } | '=' constExpr { } ; intnumAsConst: yaINTNUM { } ; //************************************************ // Typedef data_declaration: // ==IEEE: data_declaration // // VARRESET can't be called here - conflicts data_declarationVar { } | type_declaration { } | package_import_declaration { } // // IEEE 2005: virtual_interface_declaration // // IEEE 2009 removed this // // "yVIRTUAL yID yID" looks just like a data_declaration // // Therefore the virtual_interface_declaration term isn't used // // 1800-2009: | net_type_declaration { } ; class_property: // ==IEEE: class_property, which is {property_qualifier} data_declaration memberQualResetListE data_declarationVarClass { } | memberQualResetListE type_declaration { } | memberQualResetListE package_import_declaration { } // // IEEE: virtual_interface_declaration // // "yVIRTUAL yID yID" looks just like a data_declaration // // Therefore the virtual_interface_declaration term isn't used ; data_declarationVar: // IEEE: part of data_declaration // // The first declaration has complications between assuming what's the type vs ID declaring data_declarationVarFront list_of_variable_decl_assignments ';' { } ; data_declarationVarClass: // IEEE: part of data_declaration (for class_property) // // The first declaration has complications between assuming what's the type vs ID declaring data_declarationVarFrontClass list_of_variable_decl_assignments ';' { } ; data_declarationVarFront: // IEEE: part of data_declaration // // implicit_type expanded into /*empty*/ or "signingE rangeList" constE yVAR lifetimeE data_type { VARRESET(); VARDECL("var"); VARDTYPE(SPACED($1,$4)); } | constE yVAR lifetimeE { VARRESET(); VARDECL("var"); VARDTYPE($1); } | constE yVAR lifetimeE signingE rangeList { VARRESET(); VARDECL("var"); VARDTYPE(SPACED($1,SPACED($4,$5))); } // // // Expanded: "constE lifetimeE data_type" | /**/ data_typeVar { VARRESET(); VARDECL("var"); VARDTYPE($1); } | /**/ lifetime data_typeVar { VARRESET(); VARDECL("var"); VARDTYPE($2); } | yCONST__ETC lifetimeE data_typeVar { VARRESET(); VARDECL("var"); VARDTYPE(SPACED($1,$3)); } // // = class_new is in variable_decl_assignment // // // IEEE: virtual_interface_declaration // // data_type includes VIRTUAL_INTERFACE, so added to data_typeVar ; data_declarationVarFrontClass: // IEEE: part of data_declaration (for class_property) // // VARRESET called before this rule // // yCONST is removed, added to memberQual rules // // implicit_type expanded into /*empty*/ or "signingE rangeList" yVAR lifetimeE data_type { VARDECL("var"); VARDTYPE(SPACED(GRAMMARP->m_var.m_dtype, $3)); } | yVAR lifetimeE { VARDECL("var"); VARDTYPE(GRAMMARP->m_var.m_dtype); } | yVAR lifetimeE signingE rangeList { VARDECL("var"); VARDTYPE(SPACED(GRAMMARP->m_var.m_dtype, SPACED($3, $4))); } // // // Expanded: "constE lifetimeE data_type" | /**/ data_typeVar { VARDECL("var"); VARDTYPE(SPACED(GRAMMARP->m_var.m_dtype, $1)); } // // lifetime is removed, added to memberQual rules to avoid conflict // // yCONST is removed, added to memberQual rules to avoid conflict // // = class_new is in variable_decl_assignment ; net_type_declaration: // IEEE: net_type_declaration yNETTYPE data_type idAny/*net_type_identifier*/ ';' { PARSEP->syms().replaceInsert(VAstType::TYPE, $3); } // // package_scope part of data_type | yNETTYPE data_type idAny yWITH__ETC package_scopeIdFollowsE id/*tf_identifier*/ ';' { PARSEP->syms().replaceInsert(VAstType::TYPE, $3); } | yNETTYPE package_scopeIdFollowsE id/*net_type_identifier*/ idAny/*net_type_identifier*/ ';' { PARSEP->syms().replaceInsert(VAstType::TYPE, $4); } ; constE: // IEEE: part of data_declaration /* empty */ { $$ = ""; } | yCONST__ETC { $$ = $1; } ; implicit_typeE: // IEEE: part of *data_type_or_implicit // // Also expanded in data_declaration /* empty */ { $$ = ""; } | signingE rangeList { $$ = SPACED($1,$2); } | signing { $$ = $1; } ; assertion_variable_declaration: // IEEE: assertion_variable_declaration // // IEEE: var_data_type expanded var_data_type list_of_variable_decl_assignments ';' { } ; type_declaration: // ==IEEE: type_declaration // // Use idAny, as we can redeclare a typedef on an existing typedef yTYPEDEF data_type idAny variable_dimensionListE ';' { VARDONETYPEDEF($1,$3,$2,$4); } | yTYPEDEF id/*interface*/ bit_selectE '.' idAny/*type*/ idAny/*type*/ ';' { VARDONETYPEDEF($1,$6,$2+$3+"."+$5,""); } // // Combines into above "data_type id" rule | yTYPEDEF id ';' { VARDONETYPEDEF($1,$2,"",""); } | yTYPEDEF yENUM idAny ';' { PARSEP->syms().replaceInsert(VAstType::ENUM, $3); } | yTYPEDEF ySTRUCT idAny ';' { PARSEP->syms().replaceInsert(VAstType::STRUCT, $3); } | yTYPEDEF yUNION idAny ';' { PARSEP->syms().replaceInsert(VAstType::UNION, $3); } | yTYPEDEF yCLASS idAny ';' { PARSEP->syms().replaceInsert(VAstType::CLASS, $3); } | yTYPEDEF yINTERFACE yCLASS idAny ';' { PARSEP->syms().replaceInsert(VAstType::CLASS, $3); } ; //************************************************ // Module Items module_itemListE: // IEEE: Part of module_declaration /* empty */ { } | module_itemList { } ; module_itemList: // IEEE: Part of module_declaration module_item { } | module_itemList module_item { } ; module_item: // ==IEEE: module_item port_declaration ';' { } | non_port_module_item { } ; non_port_module_item: // ==IEEE: non_port_module_item generate_region { } | module_or_generate_item { } | specify_block { } | specparam_declaration { } | program_declaration { } | module_declaration { } | interface_declaration { } | timeunits_declaration { } ; module_or_generate_item: // ==IEEE: module_or_generate_item // // IEEE: parameter_override yDEFPARAM list_of_defparam_assignments ';' { } // // IEEE: gate_instantiation + udp_instantiation + module_instantiation // // not here, see etcInst in module_common_item // // We joined udp & module definitions, so this goes here | combinational_body { } // // This module_common_item shared with interface_or_generate_item:module_common_item | module_common_item { } ; module_common_item: // ==IEEE: module_common_item module_or_generate_item_declaration { } // // IEEE: interface_instantiation // // + IEEE: program_instantiation // // + module_instantiation from module_or_generate_item | etcInst { } | assertion_item { } | bind_directive { } | continuous_assign { } // // IEEE: net_alias | yALIAS variable_lvalue aliasEqList ';' { } | initial_construct { } | final_construct { } // // IEEE: always_construct | yALWAYS stmtBlock { } | loop_generate_construct { } | conditional_generate_construct { } | elaboration_system_task { } // | error ';' { } ; continuous_assign: // IEEE: continuous_assign yASSIGN strengthSpecE delayE assignList ';' { } ; initial_construct: // IEEE: initial_construct yINITIAL stmtBlock { } ; final_construct: // IEEE: final_construct yFINAL stmtBlock { } ; module_or_generate_item_declaration: // ==IEEE: module_or_generate_item_declaration package_or_generate_item_declaration { } | genvar_declaration { } | clocking_declaration { } | yDEFAULT yCLOCKING idAny/*new-clocking_identifier*/ ';' { } | yDEFAULT yDISABLE yIFF expr/*expression_or_dist*/ ';' { } ; aliasEqList: // IEEE: part of net_alias '=' variable_lvalue { } | aliasEqList '=' variable_lvalue { } ; bind_directive: // ==IEEE: bind_directive + bind_target_scope // // ';' - Note IEEE grammar is wrong, includes extra ';' - it's already in module_instantiation // // We merged the rules - id may be a bind_target_instance or module_identifier or interface_identifier yBIND bind_target_instance bind_instantiation { } | yBIND bind_target_instance ':' bind_target_instance_list bind_instantiation { } ; bind_target_instance_list: // ==IEEE: bind_target_instance_list bind_target_instance { } | bind_target_instance_list ',' bind_target_instance { } ; bind_target_instance: // ==IEEE: bind_target_instance hierarchical_identifierBit { } ; bind_instantiation: // ==IEEE: bind_instantiation // // IEEE: program_instantiation // // IEEE: + module_instantiation // // IEEE: + interface_instantiation etcInst { } ; //************************************************ // Generates // // Way down in generate_item is speced a difference between module, // interface and checker generates. modules and interfaces are almost // identical (minus DEFPARAMs) so we overlap them. Checkers are too // different, so we copy all rules for checkers. generate_region: // ==IEEE: generate_region yGENERATE ~c~genItemList yENDGENERATE { } | yGENERATE yENDGENERATE { } ; c_generate_region: // IEEE: generate_region (for checkers) BISONPRE_COPY(generate_region,{s/~c~/c_/g}) // {copied} ; generate_block: // IEEE: generate_block // // Either a single item, or a begin-end block ~c~generate_item { } | ~c~genItemBegin { } ; c_generate_block: // IEEE: generate_block (for checkers) BISONPRE_COPY(generate_block,{s/~c~/c_/g}) // {copied} ; genItemBegin: // IEEE: part of generate_block yBEGIN ~c~genItemList yEND { } | yBEGIN yEND { } | id ':' yBEGIN ~c~genItemList yEND endLabelE { } | id ':' yBEGIN yEND endLabelE { } | yBEGIN ':' idAny ~c~genItemList yEND endLabelE { } | yBEGIN ':' idAny yEND endLabelE { } ; c_genItemBegin: // IEEE: part of generate_block (for checkers) BISONPRE_COPY(genItemBegin,{s/~c~/c_/g}) // {copied} ; genItemOrBegin: // Not in IEEE, but our begin isn't under generate_item ~c~generate_item { } | ~c~genItemBegin { } ; c_genItemOrBegin: // (for checkers) BISONPRE_COPY(genItemOrBegin,{s/~c~/c_/g}) // {copied} ; genItemList: ~c~genItemOrBegin { } | ~c~genItemList ~c~genItemOrBegin { } ; c_genItemList: // (for checkers) BISONPRE_COPY(genItemList,{s/~c~/c_/g}) // {copied} ; generate_item: // IEEE: module_or_interface_or_generate_item // // Only legal when in a generate under a module (or interface under a module) module_or_generate_item { } // // Only legal when in a generate under an interface | interface_or_generate_item { } // // IEEE: checker_or_generate_item // // Only legal when in a generate under a checker // // so below in c_generate_item ; c_generate_item: // IEEE: generate_item (for checkers) checker_or_generate_item { } ; conditional_generate_construct: // ==IEEE: conditional_generate_construct // // IEEE: case_generate_construct yCASE '(' expr ')' yENDCASE { } | yCASE '(' expr ')' ~c~case_generate_itemList yENDCASE { } // // IEEE: if_generate_construct | yIF '(' expr ')' ~c~generate_block %prec prLOWER_THAN_ELSE { } | yIF '(' expr ')' ~c~generate_block yELSE ~c~generate_block { } ; c_conditional_generate_construct: // IEEE: conditional_generate_construct (for checkers) BISONPRE_COPY(conditional_generate_construct,{s/~c~/c_/g}) // {copied} ; loop_generate_construct: // ==IEEE: loop_generate_construct yFOR '(' genvar_initialization ';' expr ';' genvar_iteration ')' ~c~generate_block { } ; c_loop_generate_construct: // IEEE: loop_generate_construct (for checkers) BISONPRE_COPY(loop_generate_construct,{s/~c~/c_/g}) // {copied} ; genvar_initialization: // ==IEEE: genvar_initalization id '=' constExpr { } | yGENVAR genvar_identifierDecl '=' constExpr { } ; genvar_iteration: // ==IEEE: genvar_iteration // // IEEE: assignment_operator plus IDs | id '=' expr { } | id yP_PLUSEQ expr { } | id yP_MINUSEQ expr { } | id yP_TIMESEQ expr { } | id yP_DIVEQ expr { } | id yP_MODEQ expr { } | id yP_ANDEQ expr { } | id yP_OREQ expr { } | id yP_XOREQ expr { } | id yP_SLEFTEQ expr { } | id yP_SRIGHTEQ expr { } | id yP_SSRIGHTEQ expr { } // // inc_or_dec_operator | yP_PLUSPLUS id { } | yP_MINUSMINUS id { } | id yP_PLUSPLUS { } | id yP_MINUSMINUS { } ; case_generate_itemList: // IEEE: { case_generate_item } ~c~case_generate_item { } | ~c~case_generate_itemList ~c~case_generate_item { } ; c_case_generate_itemList: // IEEE: { case_generate_item } (for checkers) BISONPRE_COPY(case_generate_itemList,{s/~c~/c_/g}) // {copied} ; case_generate_item: // ==IEEE: case_generate_item caseCondList ':' ~c~generate_block { } | yDEFAULT ':' ~c~generate_block { } | yDEFAULT ~c~generate_block { } ; c_case_generate_item: // IEEE: case_generate_item (for checkers) BISONPRE_COPY(case_generate_item,{s/~c~/c_/g}) // {copied} ; //************************************************ // Assignments and register declarations assignList: assignOne { } | assignList ',' assignOne { } ; assignOne: variable_lvalue '=' expr { PARSEP->contassignCb($2,"assign",$1,$3); } ; delay_or_event_controlE: // IEEE: delay_or_event_control plus empty /* empty */ { } | delay_control { } /* ignored */ | event_control { } /* ignored */ | yREPEAT '(' expr ')' event_control { } /* ignored */ ; delayE: /* empty */ { } | delay_control { } /* ignored */ ; delay_control: // ==IEEE: delay_control '#' delay_value { } /* ignored */ | '#' '(' minTypMax ')' { } /* ignored */ | '#' '(' minTypMax ',' minTypMax ')' { } /* ignored */ | '#' '(' minTypMax ',' minTypMax ',' minTypMax ')' { } /* ignored */ ; delay_value: // ==IEEE:delay_value // // IEEE: ps_identifier ps_id_etc { } | yaINTNUM { } | yaFLOATNUM { } | yaTIMENUM { } ; delayExpr: expr { } ; minTypMax: // IEEE: mintypmax_expression and constant_mintypmax_expression delayExpr { } | delayExpr ':' delayExpr ':' delayExpr { } ; netSigList: // IEEE: list_of_port_identifiers netSig { } | netSigList ',' netSig { } ; netSig: // IEEE: net_decl_assignment - one element from list_of_port_identifiers netId sigAttrListE { VARDONE($1, $1, "", ""); } | netId sigAttrListE '=' expr { VARDONE($1, $1, "", $4); } | netId variable_dimensionList sigAttrListE { VARDONE($1, $1, $2, ""); } ; netId: id/*new-net*/ { $$=$1; $$=$1; } | idSVKwd { $$=$1; $$=$1; } ; sigAttrListE: /* empty */ { } ; rangeListE: // IEEE: [{packed_dimension}] /* empty */ { $$=""; } | rangeList { $$=$1; $$ = $1; } ; rangeList: // IEEE: {packed_dimension} anyrange { $$=$1; $$ = $1; } | rangeList anyrange { $$=$1; $$ = $1+$2; } ; regrangeE: /* empty */ { $$=""; } | anyrange { $$=$1; $$=$1; } ; bit_selectE: // IEEE: constant_bit_select (IEEE included empty) /* empty */ { $$ = ""; } | '[' constExpr ']' { $$=$1; $$ = "["+$2+"]"; } ; // IEEE: select // Merged into more general idArray anyrange: '[' constExpr ':' constExpr ']' { $$=$1; $$ = "["+$2+":"+$4+"]"; } ; packed_dimensionListE: // IEEE: [{ packed_dimension }] /* empty */ { $$=""; } | packed_dimensionList { $$=$1; $$=$1; } ; packed_dimensionList: // IEEE: { packed_dimension } packed_dimension { $$=$1; $$=$1; } | packed_dimensionList packed_dimension { $$=$1; $$=$1+$2; } ; packed_dimension: // ==IEEE: packed_dimension anyrange { $$=$1; $$=$1; } | '[' ']' { $$="[]"; } ; //************************************************ // Parameters param_assignment: // ==IEEE: param_assignment // // IEEE: constant_param_expression // // param_expression: '$' is in expr id/*new-parameter*/ variable_dimensionListE sigAttrListE '=' exprOrDataTypeOrMinTypMax { $$=$1; VARDONE($1, $1, $2, $5); } // // only legal in port list; throws error if not set | id/*new-parameter*/ variable_dimensionListE sigAttrListE { $$=$1; VARDONE($1, $1, $2, ""); NEED_S09($1,"optional parameter defaults"); } ; list_of_param_assignments: // ==IEEE: list_of_param_assignments param_assignment { } | list_of_param_assignments ',' param_assignment { } ; list_of_defparam_assignments: // ==IEEE: list_of_defparam_assignments defparam_assignment { } | list_of_defparam_assignments ',' defparam_assignment { } ; defparam_assignment: // ==IEEE: defparam_assignment hierarchical_identifier/*parameter*/ '=' expr { PARSEP->defparamCb($2,"defparam",$1,$3); } ; //************************************************ // Instances // We don't know identifier types, so this matches all module,udp,etc instantiation // module_id [#(params)] name (pins) [, name ...] ; // module_instantiation // gate (strong0) [#(delay)] [name] (pins) [, (pins)...] ; // gate_instantiation // program_id [#(params}] name ; // program_instantiation // interface_id [#(params}] name ; // interface_instantiation // checker_id name (pins) ; // checker_instantiation etcInst: // IEEE: module_instantiation + gate_instantiation + udp_instantiation instName { INSTPREP($1,1,0); } strengthSpecE parameter_value_assignmentE { INSTPREP($1,0,1); } instnameList ';' { INSTDONE(); } // // IEEE: interface_identifier' .' modport_identifier list_of_interface_identifiers | instName { INSTPREP($1,1,0); } '.' id {INSTPREP($1,0,0);} mpInstnameList ';' { INSTDONE(); } ; instName: gateKwd { $$=$1; $$=$1; } // // id is-a: interface_identifier // // or program_identifier // // or udp_identifier // // or module_identifier | id { $$=$1; $$=$1; } ; mpInstnameList: // Similar to instnameList, but for modport instantiations which have no parenthesis mpInstnameParen { } | mpInstnameList ',' mpInstnameParen { } ; mpInstnameParen: // Similar to instnameParen, but for modport instantiations which have no parenthesis mpInstname { PARSEP->endcellCb($1,""); } ; mpInstname: // Similar to instname, but for modport instantiations which have no parenthesis // // id is-a: interface_port_identifier (interface.modport) id instRangeListE { PARSEP->instantCb($1, GRAMMARP->m_cellMod, $1, $2); } ; instnameList: instnameParen { } | instnameList ',' instnameParen { } ; instnameParen: instname cellpinList ')' { PARSEP->endcellCb($3,""); } ; instname: // // id is-a: hierarchical_instance (interface) // // or instance_identifier (module) // // or instance_identifier (program) // // or udp_instance (udp) id instRangeListE '(' { PARSEP->instantCb($1, GRAMMARP->m_cellMod, $1, $2); PINPARAMS(); } | instRangeListE '(' { PARSEP->instantCb($2, GRAMMARP->m_cellMod, "", $1); PINPARAMS(); } // UDP ; instRangeListE: /* empty */ { $$ = ""; } | instRangeList { $$=$1; $$ = $1; } ; instRangeList: instRange { $$=$1; $$ = $1; } | instRangeList instRange { $$=$1; $$ = $1+$2; } ; instRange: '[' constExpr ']' { $$=$1; $$ = "["+$2+"]"; } | '[' constExpr ':' constExpr ']' { $$=$1; $$ = "["+$2+":"+$4+"]"; } ; cellpinList: { VARRESET_LIST(""); } cellpinItList { VARRESET_NONLIST(""); GRAMMARP->m_withinPin = false; } ; cellpinItList: // IEEE: list_of_port_connections + list_of_parameter_assignmente { GRAMMARP->m_portNextNetName.clear(); } cellpinItemE { } | cellpinItList ',' cellpinItemE { } ; cellpinItemE: // IEEE: named_port_connection + named_parameter_assignment + empty /* empty: ',,' is legal */ { PINNUMINC(); } /*PINDONE(yylval.fl,"",""); <- No, as then () implies a pin*/ | yP_DOTSTAR { PINDONE($1,"*","*");PINNUMINC(); } | '.' idSVKwd { PINDONE($1,$2,$2); PINNUMINC(); } | '.' idAny { PINDONE($1,$2,$2); PINNUMINC(); } | '.' idAny '(' ')' { PINDONE($1,$2,""); PINNUMINC(); } // // mintypmax is expanded here, as it might be a UDP or gate primitive // // For checkers, this needs to not just expr, but include events + properties | '.' idAny '(' pev_expr ')' { PINDONE($1,$2,$4); PINNUMINC(); } | '.' idAny '(' pev_expr ':' expr ')' { PINDONE($1,$2,$4); PINNUMINC(); } | '.' idAny '(' pev_expr ':' expr ':' expr ')' { PINDONE($1,$2,$4); PINNUMINC(); } // // For parameters | '.' idAny '(' data_type ')' { PINDONE($1,$2,$4); PINNUMINC(); } // // For parameters | data_type { PINDONE($1,"",$1); PINNUMINC(); } // | expr { PINDONE($1,"",$1); PINNUMINC(); } | expr ':' expr { PINDONE($1,"",$1); PINNUMINC(); } | expr ':' expr ':' expr { PINDONE($1,"",$1); PINNUMINC(); } ; //************************************************ // EventControl lists event_control: // ==IEEE: event_control '@' '(' event_expression ')' { } | '@' '*' { } | '@' '(' '*' ')' { } // // IEEE: hierarchical_event_identifier | '@' idClassSel/*event_id or ps_or_hierarchical_sequence_identifier*/ { } // // IEEE: ps_or_hierarchical_sequence_identifier // // sequence_instance without parens matches idClassSel above. // // Ambiguity: "'@' sequence (-for-sequence" versus expr:delay_or_event_controlE "'@' id (-for-expr // // For now we avoid this, as it's very unlikely someone would mix // // 1995 delay with a sequence with parameters. // // Alternatively split this out of event_control, and delay_or_event_controlE // // and anywhere delay_or_event_controlE is called allow two expressions ; event_expression: // IEEE: event_expression - split over several // // ',' rules aren't valid in port lists - ev_expr is there. // // Also eliminates left recursion to appease conflicts ev_expr { } | event_expression ',' ev_expr %prec yOR { } /* Verilog 2001 */ ; senitemEdge: // IEEE: part of event_expression // // Also called by pev_expr yPOSEDGE expr { $$=$1; $$=$1+" "+$2; } | yPOSEDGE expr yIFF expr { $$=$1; $$=$1+" "+$2+" iff "+$4; } | yNEGEDGE expr { $$=$1; $$=$1+" "+$2; } | yNEGEDGE expr yIFF expr { $$=$1; $$=$1+" "+$2+" iff "+$4; } | yEDGE expr { $$=$1; $$=$1+" "+$2; NEED_S09($1,"edge"); } | yEDGE expr yIFF expr { $$=$1; $$=$1+" "+$2+" iff "+$4; NEED_S09($1,"edge"); } ; //************************************************ // Statements stmtBlock: // IEEE: statement + seq_block + par_block stmt { } ; seq_block: // ==IEEE: seq_block // // IEEE doesn't allow declarations in unnamed blocks, but several simulators do. seq_blockFront blockDeclStmtList yEND endLabelE { PARSEP->symPopScope(VAstType::BLOCK); } | seq_blockFront /**/ yEND endLabelE { PARSEP->symPopScope(VAstType::BLOCK); } ; par_block: // ==IEEE: par_block par_blockFront blockDeclStmtList yJOIN endLabelE { PARSEP->symPopScope(VAstType::FORK); } | par_blockFront /**/ yJOIN endLabelE { PARSEP->symPopScope(VAstType::FORK); } ; seq_blockFront: // IEEE: part of seq_block yBEGIN { PARSEP->symPushNewAnon(VAstType::BLOCK); } | yBEGIN ':' idAny/*new-block_identifier*/ { PARSEP->symPushNew(VAstType::BLOCK,$1); } ; par_blockFront: // IEEE: part of par_block yFORK { PARSEP->symPushNewAnon(VAstType::FORK); } | yFORK ':' idAny/*new-block_identifier*/ { PARSEP->symPushNew(VAstType::FORK,$1); } ; blockDeclStmtList: // IEEE: { block_item_declaration } { statement or null } // // The spec seems to suggest a empty declaration isn't ok, but most simulators take it block_item_declarationList { } | block_item_declarationList stmtList { } | stmtList { } ; block_item_declarationList: // IEEE: [ block_item_declaration ] block_item_declaration { } | block_item_declarationList block_item_declaration { } ; block_item_declaration: // ==IEEE: block_item_declaration data_declaration { } | local_parameter_declaration ';' { } | parameter_declaration ';' { } | overload_declaration { } | let_declaration { } ; stmtList: stmtBlock { } | stmtList stmtBlock { } ; stmt: // IEEE: statement_or_null == function_statement_or_null statement_item { } // // S05 block creation rule | id/*block_identifier*/ ':' statement_item { } // // from _or_null | ';' { } ; statement_item: // IEEE: statement_item // // IEEE: operator_assignment foperator_assignment ';' { } // // // IEEE: blocking_assignment // // 1800-2009 restricts LHS of assignment to new to not have a range // // This is ignored to avoid conflicts | fexprLvalue '=' class_new ';' { } | fexprLvalue '=' dynamic_array_new ';' { } // // // IEEE: nonblocking_assignment | fexprLvalue yP_LTE delay_or_event_controlE expr ';' { } // // // IEEE: procedural_continuous_assignment | yASSIGN expr '=' delay_or_event_controlE expr ';' { } | yDEASSIGN variable_lvalue ';' { } | yFORCE expr '=' expr ';' { } | yRELEASE variable_lvalue ';' { } // // // IEEE: case_statement | unique_priorityE caseStart caseAttrE case_itemListE yENDCASE { } | unique_priorityE caseStart caseAttrE yMATCHES case_patternListE yENDCASE { } | unique_priorityE caseStart caseAttrE yINSIDE case_insideListE yENDCASE { } // // // IEEE: conditional_statement | unique_priorityE yIF '(' expr ')' stmtBlock %prec prLOWER_THAN_ELSE { } | unique_priorityE yIF '(' expr ')' stmtBlock yELSE stmtBlock { } // | finc_or_dec_expression ';' { } // // IEEE: inc_or_dec_expression // // Below under expr // // // IEEE: subroutine_call_statement | yVOID yP_TICK '(' function_subroutine_callNoMethod ')' ';' { } | yVOID yP_TICK '(' expr '.' function_subroutine_callNoMethod ')' ';' { } // // Expr included here to resolve our not knowing what is a method call // // Expr here must result in a subroutine_call | task_subroutine_callNoMethod ';' { } | fexpr '.' array_methodNoRoot ';' { } | fexpr '.' task_subroutine_callNoMethod ';' { } | fexprScope ';' { } // // Not here in IEEE; from class_constructor_declaration // // Because we've joined class_constructor_declaration into generic functions // // Way over-permissive; // // IEEE: [ ySUPER '.' yNEW [ '(' list_of_arguments ')' ] ';' ] | fexpr '.' class_new ';' { } // // // IEEE: disable_statement | yDISABLE hierarchical_identifier/*task_or_block*/ ';' { } | yDISABLE yFORK ';' { } // // IEEE: event_trigger | yP_MINUSGT hierarchical_identifier/*event*/ ';' { } | yP_MINUSGTGT delay_or_event_controlE hierarchical_identifier/*event*/ ';' { } // // IEEE: loop_statement | yFOREVER stmtBlock { } | yREPEAT '(' expr ')' stmtBlock { } | yWHILE '(' expr ')' stmtBlock { } // // for's first ';' is in for_initalization | yFOR '(' for_initialization expr ';' for_stepE ')' stmtBlock { } | yFOR '(' for_initialization ';' for_stepE ')' stmtBlock { } | yDO stmtBlock yWHILE '(' expr ')' ';' { } // // IEEE says array_identifier here, but dotted accepted in VMM and 1800-2009 | yFOREACH '(' idClassForeach/*array_id[loop_variables]*/ ')' stmt { } // // // IEEE: jump_statement | yRETURN ';' { } | yRETURN expr ';' { } | yBREAK ';' { } | yCONTINUE ';' { } // | par_block { } // // IEEE: procedural_timing_control_statement + procedural_timing_control | delay_control stmtBlock { } | event_control stmtBlock { } | cycle_delay stmtBlock { } // | seq_block { } // // // IEEE: wait_statement | yWAIT '(' expr ')' stmtBlock { } | yWAIT yFORK ';' { } | yWAIT_ORDER '(' hierarchical_identifierList ')' action_block { } // // // IEEE: procedural_assertion_statement | procedural_assertion_statement { } // // // IEEE: clocking_drive ';' // // clockvar_expression made to fexprLvalue to prevent reduce conflict // // Note LTE in this context is highest precedence, so first on left wins | fexprLvalue yP_LTE cycle_delay expr ';' { } // | randsequence_statement { } // // // IEEE: randcase_statement | yRANDCASE case_itemList yENDCASE { } // | expect_property_statement { } // | error ';' { } ; operator_assignment: // IEEE: operator_assignment ~f~exprLvalue '=' delay_or_event_controlE expr { } | ~f~exprLvalue yP_PLUSEQ expr { } | ~f~exprLvalue yP_MINUSEQ expr { } | ~f~exprLvalue yP_TIMESEQ expr { } | ~f~exprLvalue yP_DIVEQ expr { } | ~f~exprLvalue yP_MODEQ expr { } | ~f~exprLvalue yP_ANDEQ expr { } | ~f~exprLvalue yP_OREQ expr { } | ~f~exprLvalue yP_XOREQ expr { } | ~f~exprLvalue yP_SLEFTEQ expr { } | ~f~exprLvalue yP_SRIGHTEQ expr { } | ~f~exprLvalue yP_SSRIGHTEQ expr { } ; foperator_assignment: // IEEE: operator_assignment (for first part of expression) BISONPRE_COPY(operator_assignment,{s/~f~/f/g}) // {copied} ; inc_or_dec_expression: // ==IEEE: inc_or_dec_expression // // Need fexprScope instead of variable_lvalue to prevent conflict ~l~exprScope yP_PLUSPLUS { $$=$1; $$ = $1+$2; } | ~l~exprScope yP_MINUSMINUS { $$=$1; $$ = $1+$2; } // // Need expr instead of variable_lvalue to prevent conflict | yP_PLUSPLUS expr { $$=$1; $$ = $1+$2; } | yP_MINUSMINUS expr { $$=$1; $$ = $1+$2; } ; finc_or_dec_expression: // IEEE: inc_or_dec_expression (for first part of expression) BISONPRE_COPY(inc_or_dec_expression,{s/~l~/f/g}) // {copied} ; sinc_or_dec_expression: // IEEE: inc_or_dec_expression (for sequence_expression) BISONPRE_COPY(inc_or_dec_expression,{s/~l~/s/g}) // {copied} ; pinc_or_dec_expression: // IEEE: inc_or_dec_expression (for property_expression) BISONPRE_COPY(inc_or_dec_expression,{s/~l~/p/g}) // {copied} ; ev_inc_or_dec_expression: // IEEE: inc_or_dec_expression (for ev_expr) BISONPRE_COPY(inc_or_dec_expression,{s/~l~/ev_/g}) // {copied} ; pev_inc_or_dec_expression: // IEEE: inc_or_dec_expression (for pev_expr) BISONPRE_COPY(inc_or_dec_expression,{s/~l~/pev_/g}) // {copied} ; class_new: // ==IEEE: class_new // // Special precence so (...) doesn't match expr yNEW__ETC { $$=$1; $$ = $1; } | yNEW__ETC expr { $$=$1; $$ = $1+" "+$2; } // // Grammer abiguity; we assume "new (x)" the () are a argument, not expr | yNEW__PAREN '(' list_of_argumentsE ')' { $$=$1; $$ = $1+"("+$3+")"; } ; dynamic_array_new: // ==IEEE: dynamic_array_new yNEW__ETC '[' expr ']' { $$=$1; $$=$1+"["+$3+"]"; } | yNEW__ETC '[' expr ']' '(' expr ')' { $$=$1; $$=$1+"["+$3+"]("+$6+")"; } ; //************************************************ // Case/If unique_priorityE: // IEEE: unique_priority + empty /*empty*/ { } | yPRIORITY { } | yUNIQUE { } | yUNIQUE0 { NEED_S09($1, "unique0"); } ; action_block: // ==IEEE: action_block stmt %prec prLOWER_THAN_ELSE { } | stmt yELSE stmt { } | yELSE stmt { } ; caseStart: // IEEE: part of case_statement yCASE '(' expr ')' { } | yCASEX '(' expr ')' { } | yCASEZ '(' expr ')' { } ; caseAttrE: /*empty*/ { } ; case_patternListE: // IEEE: case_pattern_item // &&& is part of expr so aliases to case_itemList case_itemListE { } ; case_itemListE: // IEEE: [ { case_item } ] /* empty */ { } | case_itemList { } ; case_insideListE: // IEEE: [ { case_inside_item } ] /* empty */ { } | case_inside_itemList { } ; case_itemList: // IEEE: { case_item + ... } caseCondList ':' stmtBlock { } | yDEFAULT ':' stmtBlock { } | yDEFAULT stmtBlock { } | case_itemList caseCondList ':' stmtBlock { } | case_itemList yDEFAULT stmtBlock { } | case_itemList yDEFAULT ':' stmtBlock { } ; case_inside_itemList: // IEEE: { case_inside_item + open_range_list ... } open_range_list ':' stmtBlock { } | yDEFAULT ':' stmtBlock { } | yDEFAULT stmtBlock { } | case_inside_itemList open_range_list ':' stmtBlock { } | case_inside_itemList yDEFAULT stmtBlock { } | case_inside_itemList yDEFAULT ':' stmtBlock { } ; open_range_list: // ==IEEE: open_range_list + open_value_range open_value_range { } | open_range_list ',' open_value_range { } ; open_value_range: // ==IEEE: open_value_range value_range { } ; value_range: // ==IEEE: value_range expr { } | '[' expr ':' expr ']' { } ; covergroup_value_range: // ==IEEE-2012: covergroup_value_range cgexpr { } | '[' cgexpr ':' cgexpr ']' { } ; caseCondList: // IEEE: part of case_item expr { } | caseCondList ',' expr { } ; patternNoExpr: // IEEE: pattern **Excluding Expr* '.' id/*variable*/ { $$=$1; $$="."+$2; } | yP_DOTSTAR { $$=$1; $$=".*"; } // // IEEE: "expr" excluded; expand in callers // // "yTAGGED id [expr]" Already part of expr | yTAGGED id/*member_identifier*/ patternNoExpr { $$=$1; $$=" tagged "+$2+" "+$3; } // // "yP_TICKBRA patternList '}'" part of expr under assignment_pattern ; patternList: // IEEE: part of pattern patternOne { $$=$1; $$=$1; } | patternList ',' patternOne { $$=$1; $$=$1+","+$3; } ; patternOne: // IEEE: part of pattern expr { $$=$1; $$=$1; } | expr '{' argsExprList '}' { $$=$1; $$=$1; } | patternNoExpr { $$=$1; $$=$1; } ; patternMemberList: // IEEE: part of pattern and assignment_pattern patternKey ':' expr { $$=$1; $$=$1+" : "+$2; } | patternKey ':' patternNoExpr { $$=$1; $$=$1+" : "+$2; } | patternMemberList ',' patternKey ':' expr { $$=$1; $$=$1+","+$3+":"+$4; } | patternMemberList ',' patternKey ':' patternNoExpr { $$=$1; $$=$1+","+$3+":"+$4; } ; patternKey: // IEEE: merge structure_pattern_key, array_pattern_key, assignment_pattern_key // // IEEE: structure_pattern_key // // id/*member*/ is part of constExpr below constExpr { $$=$1; $$=$1; } // // IEEE: assignment_pattern_key | yDEFAULT { $$=$1; $$=$1; } | simple_type { $$=$1; $$=$1; } // // simple_type reference looks like constExpr ; assignment_pattern: // ==IEEE: assignment_pattern // This doesn't match the text of the spec. I think a : is missing, or example code needed // yP_TICKBRA constExpr exprList '}' { $$="'{"+$2+" "+$3"}"; } // // "'{ const_expression }" is same as patternList with one entry // // From patternNoExpr // // also IEEE: "''{' expression { ',' expression } '}'" // // matches since patternList includes expr yP_TICKBRA patternList '}' { $$=$1; $$="'{"+$2+"}"; } // // From patternNoExpr // // also IEEE "''{' structure_pattern_key ':' ... // // also IEEE "''{' array_pattern_key ':' ... | yP_TICKBRA patternMemberList '}' { $$=$1; $$="'{"+$2+"}"; } // // IEEE: Not in grammar, but in VMM | yP_TICKBRA '}' { $$=$1; $$="'{}"; } ; // "datatype id = x {, id = x }" | "yaId = x {, id=x}" is legal for_initialization: // ==IEEE: for_initialization + for_variable_declaration + extra terminating ";" // // IEEE: for_variable_declaration for_initializationItemList ';' { } // // IEEE: 1800-2017 empty initialization | ';' { } ; for_initializationItemList: // IEEE: [for_variable_declaration...] for_initializationItem { } | for_initializationItemList ',' for_initializationItem { } ; for_initializationItem: // IEEE: variable_assignment + for_variable_declaration // // IEEE: for_variable_declaration data_type idAny/*new*/ '=' expr { VARDTYPE($1); } // // IEEE-2012: | yVAR data_type idAny/*new*/ '=' expr { VARDTYPE($1); } // // IEEE: variable_assignment | variable_lvalue '=' expr { } ; for_stepE: // IEEE: for_step + empty /* empty */ { } | for_step { } ; for_step: // IEEE: for_step for_step_assignment { } | for_step ',' for_step_assignment { } ; for_step_assignment: // ==IEEE: for_step_assignment operator_assignment { } // | inc_or_dec_expression { } // // IEEE: subroutine_call | function_subroutine_callNoMethod { } // // method_call:array_method requires a '.' | expr '.' array_methodNoRoot { } | exprScope { } ; loop_variables: // ==IEEE: loop_variables id { $$=$1; $$=$1; } | loop_variables ',' id { $$=$1; $$=$1+","+$3; } ; //************************************************ // Functions/tasks funcRef: // IEEE: part of tf_call // // package_scope/hierarchical_... is part of expr, so just need ID // // making-a id-is-a // // ----------------- ------------------ // // tf_call tf_identifier expr (list_of_arguments) // // method_call(post .) function_identifier expr (list_of_arguments) // // property_instance property_identifier property_actual_arg // // sequence_instance sequence_identifier sequence_actual_arg // // let_expression let_identifier let_actual_arg // id '(' pev_list_of_argumentsE ')' { $$=$1; $$=$1+"("+$3+")"; } | package_scopeIdFollows id '(' pev_list_of_argumentsE ')' { $$=$2; $$=$1+$2+"("+$4+")"; } | class_scope_id '(' pev_list_of_argumentsE ')' { $$=$1; $$=$1+"("+$3+")"; } ; task_subroutine_callNoMethod: // function_subroutine_callNoMethod (as task) // // IEEE: tf_call funcRef { $$=$1; $$=$1; } | funcRef yWITH__PAREN '(' expr ')' { $$=$1; $$=$1+" "+$2+$3+$4+$5; } | system_t_call { $$=$1; $$=$1; } // // IEEE: method_call requires a "." so is in expr // // IEEE: ['std::'] not needed, as normal std package resolution will find it // // IEEE: randomize_call // // We implement randomize as a normal funcRef, since randomize isn't a keyword // // Note yNULL is already part of expressions, so they come for free | funcRef yWITH__CUR constraint_block { $$=$1; $$=$1+" with..."; } ; function_subroutine_callNoMethod: // IEEE: function_subroutine_call (as function) // // IEEE: tf_call funcRef { $$=$1; $$=$1; } | funcRef yWITH__PAREN '(' expr ')' { $$=$1; $$=$1+" "+$2+$3+$4+$5; } | system_f_call { $$=$1; $$=$1; } // // IEEE: method_call requires a "." so is in expr // // IEEE: ['std::'] not needed, as normal std package resolution will find it // // IEEE: randomize_call // // We implement randomize as a normal funcRef, since randomize isn't a keyword // // Note yNULL is already part of expressions, so they come for free | funcRef yWITH__CUR constraint_block { $$=$1; $$=$1+" with..."; } ; system_t_call: // IEEE: system_tf_call (as task) system_f_call { $$=$1; $$ = $1; } ; system_f_call: // IEEE: system_tf_call (as func) ygenSYSCALL parenE { $$=$1; $$ = $1; } // // Allow list of data_type to support "x,,,y" | ygenSYSCALL '(' exprOrDataTypeList ')' { $$=$1; $$ = $1+"("+$3+")"; } // // Standard doesn't explicity list system calls // // But these match elaboration calls in 1800-2009 | yD_FATAL parenE { $$=$1; $$ = $1; } | yD_FATAL '(' exprOrDataTypeList ')' { $$=$1; $$ = $1+"("+$3+")"; } | yD_ERROR parenE { $$=$1; $$ = $1; } | yD_ERROR '(' exprOrDataTypeList ')' { $$=$1; $$ = $1+"("+$3+")"; } | yD_WARNING parenE { $$=$1; $$ = $1; } | yD_WARNING '(' exprOrDataTypeList ')' { $$=$1; $$ = $1+"("+$3+")"; } | yD_INFO parenE { $$=$1; $$ = $1; } | yD_INFO '(' exprOrDataTypeList ')' { $$=$1; $$ = $1+"("+$3+")"; } ; elaboration_system_task: // IEEE: elaboration_system_task (1800-2009) // // $fatal first argument is exit number, must be constant yD_FATAL parenE ';' { $$=$1; $$ = $1; NEED_S09($1,"elaboration system tasks"); } | yD_FATAL '(' exprOrDataTypeList ')' ';' { $$=$1; $$ = $1+"("+$3+")"; NEED_S09($1,"elaboration system tasks"); } | yD_ERROR parenE ';' { $$=$1; $$ = $1; NEED_S09($1,"elaboration system tasks"); } | yD_ERROR '(' exprOrDataTypeList ')' ';' { $$=$1; $$ = $1+"("+$3+")"; NEED_S09($1,"elaboration system tasks"); } | yD_WARNING parenE ';' { $$=$1; $$ = $1; NEED_S09($1,"elaboration system tasks"); } | yD_WARNING '(' exprOrDataTypeList ')' ';' {$$=$1; $$ = $1+"("+$3+")"; NEED_S09($1,"elaboration system tasks"); } | yD_INFO parenE ';' { $$=$1; $$ = $1; NEED_S09($1,"elaboration system tasks"); } | yD_INFO '(' exprOrDataTypeList ')' ';' { $$=$1; $$ = $1+"("+$3+")"; NEED_S09($1,"elaboration system tasks"); } ; property_actual_arg: // ==IEEE: property_actual_arg // // IEEE: property_expr // // IEEE: sequence_actual_arg pev_expr { $$=$1; $$=$1; } // // IEEE: sequence_expr // // property_expr already includes sequence_expr ; task: yTASK__ETC { $$=$1; } | yTASK__aPUREV { $$=$1; } ; task_declaration: // IEEE: task_declaration yTASK__ETC lifetimeE taskId tfGuts yENDTASK endLabelE { PARSEP->endtaskfuncCb($5,$5); PARSEP->symPopScope(VAstType::TASK); } | yTASK__aPUREV lifetimeE taskId tfGutsPureV { PARSEP->endtaskfuncCb($1,"endtask"); PARSEP->symPopScope(VAstType::TASK); } ; task_prototype: // ==IEEE: task_prototype // // IEEE: has '(' tf_port_list ')' // // However the () should be optional for OVA task taskId '(' tf_port_listE ')' { PARSEP->symPopScope(VAstType::TASK); PARSEP->endtaskfuncCb($1,"endtask"); } | task taskId { PARSEP->symPopScope(VAstType::TASK); PARSEP->endtaskfuncCb($1,"endtask"); } ; function: yFUNCTION__ETC { $$=$1; } | yFUNCTION__aPUREV { $$=$1; } ; function_declaration: // IEEE: function_declaration + function_body_declaration yFUNCTION__ETC lifetimeE funcId tfGuts yENDFUNCTION endLabelE { PARSEP->endtaskfuncCb($5,$5); PARSEP->symPopScope(VAstType::FUNCTION); } | yFUNCTION__ETC lifetimeE funcIdNew tfGuts yENDFUNCTION endLabelE { PARSEP->endtaskfuncCb($5,$5); PARSEP->symPopScope(VAstType::FUNCTION); } | yFUNCTION__aPUREV lifetimeE funcId tfGutsPureV { PARSEP->endtaskfuncCb($1,"endfunction"); PARSEP->symPopScope(VAstType::FUNCTION); } | yFUNCTION__aPUREV lifetimeE funcIdNew tfGutsPureV { PARSEP->endtaskfuncCb($1,"endfunction"); PARSEP->symPopScope(VAstType::FUNCTION); } ; function_prototype: // IEEE: function_prototype // // IEEE: has '(' tf_port_list ')' // // However the () should be optional for OVA function funcId '(' tf_port_listE ')' { PARSEP->symPopScope(VAstType::FUNCTION); PARSEP->endtaskfuncCb($1,"endfunction"); } | function funcId { PARSEP->symPopScope(VAstType::FUNCTION); PARSEP->endtaskfuncCb($1,"endfunction"); } ; class_constructor_prototype: // ==IEEE: class_constructor_prototype function funcIdNew '(' tf_port_listE ')' ';' { PARSEP->symPopScope(VAstType::FUNCTION); PARSEP->endtaskfuncCb($1,"endfunction"); } | function funcIdNew ';' { PARSEP->symPopScope(VAstType::FUNCTION); PARSEP->endtaskfuncCb($1,"endfunction"); } ; method_prototype: task_prototype { } | function_prototype { } ; lifetimeE: // IEEE: [lifetime] /* empty */ { } | lifetime { } ; lifetime: // ==IEEE: lifetime // // Note lifetime used by members is instead under memberQual ySTATIC__ETC { } | yAUTOMATIC { } ; taskId: tfIdScoped { PARSEP->symPushNewUnder(VAstType::TASK, $1, $1); PARSEP->taskCb($1,"task",$1); } ; funcId: // IEEE: function_data_type_or_implicit + part of function_body_declaration // // IEEE: function_data_type_or_implicit must be expanded here to prevent conflict // // function_data_type expanded here to prevent conflicts with implicit_type:empty vs data_type:ID /**/ tfIdScoped { PARSEP->symPushNewUnder(VAstType::FUNCTION, $1, $1); PARSEP->functionCb($1,"function",$1,""); } | signingE rangeList tfIdScoped { PARSEP->symPushNewUnder(VAstType::FUNCTION, $3, $3); PARSEP->functionCb($3,"function",$3,SPACED($1,$2)); } | signing tfIdScoped { PARSEP->symPushNewUnder(VAstType::FUNCTION, $2, $2); PARSEP->functionCb($2,"function",$2,$1); } | yVOID tfIdScoped { PARSEP->symPushNewUnder(VAstType::FUNCTION, $2, $2); PARSEP->functionCb($2,"function",$2,$1); } | data_type tfIdScoped { PARSEP->symPushNewUnder(VAstType::FUNCTION, $2, $2); PARSEP->functionCb($2,"function",$2,$1); } ; funcIdNew: // IEEE: from class_constructor_declaration yNEW__ETC { PARSEP->symPushNewUnder(VAstType::FUNCTION, "new", NULL); PARSEP->functionCb($1,"function","new",""); } | yNEW__PAREN { PARSEP->symPushNewUnder(VAstType::FUNCTION, "new", NULL); PARSEP->functionCb($1,"function","new",""); } | class_scopeWithoutId yNEW__PAREN { PARSEP->symPushNewUnder(VAstType::FUNCTION, "new", $1); PARSEP->functionCb($2,"function","new",""); } ; tfIdScoped: // IEEE: part of function_body_declaration/task_body_declaration // // IEEE: [ interface_identifier '.' | class_scope ] function_identifier id { $$=$1; $$=NULL; $$ = $1; } | id/*interface_identifier*/ '.' id { $$=$1; $$=NULL; $$ = $1+"."+$2; } | class_scope_id { $$=$1; $$=$1; $$ = $1; } ; tfGuts: '(' tf_port_listE ')' ';' tfBodyE { } | ';' tfBodyE { } ; tfGutsPureV: '(' tf_port_listE ')' ';' { } | ';' { } ; tfBodyE: // IEEE: part of function_body_declaration/task_body_declaration /* empty */ { } | tf_item_declarationList { } | tf_item_declarationList stmtList { } | stmtList { } ; function_data_type: // IEEE: function_data_type yVOID { $$ = $1; } | data_type { $$ = $1; } ; tf_item_declarationList: tf_item_declaration { } | tf_item_declarationList tf_item_declaration { } ; tf_item_declaration: // ==IEEE: tf_item_declaration block_item_declaration { } | tf_port_declaration { } ; tf_port_listE: // IEEE: tf_port_list + empty // // Empty covered by tf_port_item { VARRESET_LIST(""); VARIO("input"); } tf_port_listList { VARRESET_NONLIST(""); } ; tf_port_listList: // IEEE: part of tf_port_list tf_port_item { } | tf_port_listList ',' tf_port_item { } ; tf_port_item: // ==IEEE: tf_port_item // // We split tf_port_item into the type and assignment as don't know what follows a comma /* empty */ { PINNUMINC(); } // For example a ",," port | tf_port_itemFront tf_port_itemAssignment { PINNUMINC(); } | tf_port_itemAssignment { PINNUMINC(); } ; tf_port_itemFront: // IEEE: part of tf_port_item, which has the data type data_type { VARDTYPE($1); } | signingE rangeList { VARDTYPE(SPACED($1,$2)); } | signing { VARDTYPE($1); } | yVAR data_type { VARDTYPE($2); } | yVAR implicit_typeE { VARDTYPE($2); } // | tf_port_itemDir /*implicit*/ { VARDTYPE(""); /*default_nettype-see spec*/ } | tf_port_itemDir data_type { VARDTYPE($2); } | tf_port_itemDir signingE rangeList { VARDTYPE(SPACED($2,$3)); } | tf_port_itemDir signing { VARDTYPE($2); } | tf_port_itemDir yVAR data_type { VARDTYPE($3); } | tf_port_itemDir yVAR implicit_typeE { VARDTYPE($3); } ; tf_port_itemDir: // IEEE: part of tf_port_item, direction port_direction { } // port_direction sets VARIO ; tf_port_itemAssignment: // IEEE: part of tf_port_item, which has assignment id variable_dimensionListE sigAttrListE { VARDONE($1, $1, $2, ""); } | id variable_dimensionListE sigAttrListE '=' expr { VARDONE($1, $1, $2, $5); } ; parenE: /* empty */ { } | '(' ')' { } ; // method_call: // ==IEEE: method_call + method_call_body // // IEEE: method_call_root '.' method_identifier [ '(' list_of_arguments ')' ] // // "method_call_root '.' method_identifier" looks just like "expr '.' id" // // "method_call_root '.' method_identifier (...)" looks just like "expr '.' tf_call" // // IEEE: built_in_method_call // // method_call_root not needed, part of expr resolution // // What's left is below array_methodNoRoot array_methodNoRoot: // ==IEEE: built_in_method_call without root // // method_call_root not needed, part of expr resolution array_method_nameNoId method_callWithE { $$=$1; $$=$1+$2; } | array_method_nameNoId '(' list_of_argumentsE ')' method_callWithE { $$=$1; $$=$1+$2+$3+$4+$5; } // // "method_call_root '.' randomize_call" matches function_subroutine_call:randomize_call ; method_callWithE: // // Code duplicated elsewhere /* empty */ { $$=""; } | yWITH__PAREN '(' expr ')' { $$=$1; $$=$1+$2+$3+$4; } ; array_method_nameNoId: // IEEE: array_method_name minus method_identifier yUNIQUE { $$=$1; $$=$1; } | yAND { $$=$1; $$=$1; } | yOR { $$=$1; $$=$1; } | yXOR { $$=$1; $$=$1; } ; dpi_import_export: // ==IEEE: dpi_import_export yIMPORT yaSTRING dpi_tf_import_propertyE dpi_importLabelE function_prototype ';' { } | yIMPORT yaSTRING dpi_tf_import_propertyE dpi_importLabelE task_prototype ';' { } | yEXPORT yaSTRING dpi_importLabelE function idAny ';' { } | yEXPORT yaSTRING dpi_importLabelE task idAny ';' { } ; dpi_importLabelE: // IEEE: part of dpi_import_export /* empty */ { } | idAny/*c_identifier*/ '=' { } ; dpi_tf_import_propertyE: // IEEE: [ dpi_function_import_property + dpi_task_import_property ] /* empty */ { } | yCONTEXT { } | yPURE { } ; overload_declaration: // ==IEEE: overload_declaration // // OLD: Overloads deprecated in IEEE 1800-2017 yBIND overload_operator function data_type idAny/*new-function_identifier*/ '(' overload_proto_formals ')' ';' { } ; overload_operator: // ==IEEE: overload_operator "+" { $$="+"; } | yP_PLUSPLUS { $$="++"; } | "-" { $$="-"; } | yP_MINUSMINUS { $$="--"; } | "*" { $$="*"; } | yP_POW { $$="**"; } | "/" { $$="/"; } | "%" { $$="%"; } | yP_EQUAL { $$="=="; } | yP_NOTEQUAL { $$="!="; } | "<" { $$="<"; } | yP_LTE { $$="<="; } | ">" { $$=">"; } | yP_GTE { $$=">="; } | "=" { $$="="; } ; overload_proto_formals: // ==IEEE: overload_proto_formals data_type { } | overload_proto_formals ',' data_type { } ; //************************************************ // Expressions // // ~l~ means this is the (l)eft hand side of any operator // it will get replaced by "", "f" or "s"equence // ~r~ means this is a (r)ight hand later expansion in the same statement, // not under parenthesis for <= disambiguation // it will get replaced by "", or "f" // ~p~ means this is a (p)arenthetized expression // it will get replaced by "", or "s"equence constExpr: expr { $$=$1; $$ = $1; } ; expr: // IEEE: part of expression/constant_expression/primary // *SEE BELOW* // IEEE: primary/constant_primary // // // IEEE: unary_operator primary '+' ~r~expr %prec prUNARYARITH { $$=$1; $$ = $1+$2; } | '-' ~r~expr %prec prUNARYARITH { $$=$1; $$ = $1+$2; } | '!' ~r~expr %prec prNEGATION { $$=$1; $$ = $1+$2; } | '&' ~r~expr %prec prREDUCTION { $$=$1; $$ = $1+$2; } | '~' ~r~expr %prec prNEGATION { $$=$1; $$ = $1+$2; } | '|' ~r~expr %prec prREDUCTION { $$=$1; $$ = $1+$2; } | '^' ~r~expr %prec prREDUCTION { $$=$1; $$ = $1+$2; } | yP_NAND ~r~expr %prec prREDUCTION { $$=$1; $$ = $1+$2; } | yP_NOR ~r~expr %prec prREDUCTION { $$=$1; $$ = $1+$2; } | yP_XNOR ~r~expr %prec prREDUCTION { $$=$1; $$ = $1+$2; } // // // IEEE: inc_or_dec_expression | ~l~inc_or_dec_expression { $$=$1; $$ = $1; } // // // IEEE: '(' operator_assignment ')' // // Need exprScope of variable_lvalue to prevent conflict | '(' ~p~exprScope '=' expr ')' { $$=$1; $$ = "("+$2+$3+$4+")"; } | '(' ~p~exprScope yP_PLUSEQ expr ')' { $$=$1; $$ = "("+$2+$3+$4+")"; } | '(' ~p~exprScope yP_MINUSEQ expr ')' { $$=$1; $$ = "("+$2+$3+$4+")"; } | '(' ~p~exprScope yP_TIMESEQ expr ')' { $$=$1; $$ = "("+$2+$3+$4+")"; } | '(' ~p~exprScope yP_DIVEQ expr ')' { $$=$1; $$ = "("+$2+$3+$4+")"; } | '(' ~p~exprScope yP_MODEQ expr ')' { $$=$1; $$ = "("+$2+$3+$4+")"; } | '(' ~p~exprScope yP_ANDEQ expr ')' { $$=$1; $$ = "("+$2+$3+$4+")"; } | '(' ~p~exprScope yP_OREQ expr ')' { $$=$1; $$ = "("+$2+$3+$4+")"; } | '(' ~p~exprScope yP_XOREQ expr ')' { $$=$1; $$ = "("+$2+$3+$4+")"; } | '(' ~p~exprScope yP_SLEFTEQ expr ')' { $$=$1; $$ = "("+$2+$3+$4+")"; } | '(' ~p~exprScope yP_SRIGHTEQ expr ')' { $$=$1; $$ = "("+$2+$3+$4+")"; } | '(' ~p~exprScope yP_SSRIGHTEQ expr ')' { $$=$1; $$ = "("+$2+$3+$4+")"; } // // // IEEE: expression binary_operator expression | ~l~expr '+' ~r~expr { $$=$1; $$ = $1+$2+$3; } | ~l~expr '-' ~r~expr { $$=$1; $$ = $1+$2+$3; } | ~l~expr '*' ~r~expr { $$=$1; $$ = $1+$2+$3; } | ~l~expr '/' ~r~expr { $$=$1; $$ = $1+$2+$3; } | ~l~expr '%' ~r~expr { $$=$1; $$ = $1+$2+$3; } | ~l~expr yP_EQUAL ~r~expr { $$=$1; $$ = $1+$2+$3; } | ~l~expr yP_NOTEQUAL ~r~expr { $$=$1; $$ = $1+$2+$3; } | ~l~expr yP_CASEEQUAL ~r~expr { $$=$1; $$ = $1+$2+$3; } | ~l~expr yP_CASENOTEQUAL ~r~expr { $$=$1; $$ = $1+$2+$3; } | ~l~expr yP_WILDEQUAL ~r~expr { $$=$1; $$ = $1+$2+$3; } | ~l~expr yP_WILDNOTEQUAL ~r~expr { $$=$1; $$ = $1+$2+$3; } | ~l~expr yP_ANDAND ~r~expr { $$=$1; $$ = $1+$2+$3; } | ~l~expr yP_OROR ~r~expr { $$=$1; $$ = $1+$2+$3; } | ~l~expr yP_POW ~r~expr { $$=$1; $$ = $1+$2+$3; } | ~l~expr '<' ~r~expr { $$=$1; $$ = $1+$2+$3; } | ~l~expr '>' ~r~expr { $$=$1; $$ = $1+$2+$3; } | ~l~expr yP_GTE ~r~expr { $$=$1; $$ = $1+$2+$3; } | ~l~expr '&' ~r~expr { $$=$1; $$ = $1+$2+$3; } | ~l~expr '|' ~r~expr { $$=$1; $$ = $1+$2+$3; } | ~l~expr '^' ~r~expr { $$=$1; $$ = $1+$2+$3; } | ~l~expr yP_XNOR ~r~expr { $$=$1; $$ = $1+$2+$3; } | ~l~expr yP_NOR ~r~expr { $$=$1; $$ = $1+$2+$3; } | ~l~expr yP_NAND ~r~expr { $$=$1; $$ = $1+$2+$3; } | ~l~expr yP_SLEFT ~r~expr { $$=$1; $$ = $1+$2+$3; } | ~l~expr yP_SRIGHT ~r~expr { $$=$1; $$ = $1+$2+$3; } | ~l~expr yP_SSRIGHT ~r~expr { $$=$1; $$ = $1+$2+$3; } | ~l~expr yP_LTMINUSGT ~r~expr { $$=$1; $$ = $1+$2+$3; } // // // IEEE: expr yP_MINUSGT expr (1800-2009) // // Conflicts with constraint_expression:"expr yP_MINUSGT constraint_set" // // To duplicating expr for constraints, just allow the more general form // // Later Ast processing must ignore constraint terms where inappropriate | ~l~expr yP_MINUSGT constraint_set { $$=$1; $$ = $1+$2+$3; } // // // <= is special, as we need to disambiguate it with <= assignment // // We copy all of expr to fexpr and rename this token to a fake one. | ~l~expr yP_LTE~f__IGNORE~ ~r~expr { $$=$1; $$ = $1+$2+$3; } // // // IEEE: conditional_expression | ~l~expr '?' ~r~expr ':' ~r~expr { $$=$1; $$ = $1+"?"+$3+":"+$5; } // // // IEEE: inside_expression | ~l~expr yINSIDE '{' open_range_list '}' { $$=$1; $$ = $1+" inside {"+$3+"}"; } // // // IEEE: tagged_union_expression | yTAGGED id/*member*/ %prec prTAGGED { $$=$1; $$ = " tagged "+$1; } | yTAGGED id/*member*/ %prec prTAGGED expr { $$=$1; $$ = " tagged "+$1+" "+$2; } // //======================// IEEE: primary/constant_primary // // // IEEE: primary_literal (minus string, which is handled specially) | yaINTNUM { $$=$1; $$ = $1; } | yaFLOATNUM { $$=$1; $$ = $1; } | yaTIMENUM { $$=$1; $$ = $1; } | strAsInt~noStr__IGNORE~ { $$=$1; $$ = $1; } // // // IEEE: "... hierarchical_identifier select" see below // // // IEEE: empty_queue (IEEE 1800-2017 empty_unpacked_array_concatenation) | '{' '}' // // // IEEE: concatenation/constant_concatenation // // Part of exprOkLvalue below // // // IEEE: multiple_concatenation/constant_multiple_concatenation | '{' constExpr '{' cateList '}' '}' { $$=$1; $$ = "{"+$2+"{"+$4+"}}"; } // // IEEE: multiple_concatenation/constant_multiple_concatenation+ range_expression (1800-2009) | '{' constExpr '{' cateList '}' '}' '[' expr ']' { $$=$1; $$ = "{"+$2+"{"+$4+"}}["+$8+"]"; NEED_S09($6,"{}[]"); } | '{' constExpr '{' cateList '}' '}' '[' expr ':' expr ']' { $$=$1; $$ = "{"+$2+"{"+$4+"}}["+$8+$9+$10+"]"; NEED_S09($6,"{}[]"); } | '{' constExpr '{' cateList '}' '}' '[' expr yP_PLUSCOLON expr ']' { $$=$1; $$ = "{"+$2+"{"+$4+"}}["+$8+$9+$10+"]"; NEED_S09($6,"{}[]"); } | '{' constExpr '{' cateList '}' '}' '[' expr yP_MINUSCOLON expr ']' { $$=$1; $$ = "{"+$2+"{"+$4+"}}["+$8+$9+$10+"]"; NEED_S09($6,"{}[]"); } // | function_subroutine_callNoMethod { $$ = $1; } // // method_call | ~l~expr '.' function_subroutine_callNoMethod { $$=$1; $$=$1+"."+$3; } // // method_call:array_method requires a '.' | ~l~expr '.' array_methodNoRoot { $$=$1; $$ = $1+"."+$3; } // // // IEEE: let_expression // // see funcRef // // // IEEE: '(' mintypmax_expression ')' | ~noPar__IGNORE~'(' expr ')' { $$=$1; $$ = "("+$2+")"; } | ~noPar__IGNORE~'(' expr ':' expr ':' expr ')' { $$=$1; $$ = "("+$2+":"+$4+":"+$5+")"; } // // PSL rule | '_' '(' statePushVlg expr statePop ')' { $$=$1; $$ = "_("+$4+")"; } // Arbitrary Verilog inside PSL // // // IEEE: cast/constant_cast | casting_type yP_TICK '(' expr ')' { $$=$1; $$ = $1+"'("+$4+")"; } // // Spec only allows primary with addition of a type reference // // We'll be more general, and later assert LHS was a type. | ~l~expr yP_TICK '(' expr ')' { $$=$1; $$ = $1+"'("+$4+")"; } // // // IEEE: assignment_pattern_expression // // IEEE: streaming_concatenation // // See exprOkLvalue // // // IEEE: sequence_method_call // // Indistinguishable from function_subroutine_call:method_call // | '$' { $$=$1; $$ = "$"; } | yNULL { $$=$1; $$ = $1; } // // IEEE: yTHIS // // See exprScope // //---------------------- // // // Part of expr that may also be used as lvalue | ~l~exprOkLvalue { $$=$1; $$ = $1; } // //---------------------- // // // IEEE: cond_predicate - here to avoid reduce problems // // Note expr includes cond_pattern | ~l~expr yP_ANDANDAND ~r~expr { $$=$1; $$ = $1 + "&&&" + $3; } // // // IEEE: cond_pattern - here to avoid reduce problems // // "expr yMATCHES pattern" // // IEEE: pattern - expanded here to avoid conflicts | ~l~expr yMATCHES patternNoExpr { $$=$1; $$ = $1 + " matches " + $3; } | ~l~expr yMATCHES ~r~expr { $$=$1; $$ = $1 + " matches " + $3; } // // // IEEE: expression_or_dist - here to avoid reduce problems // // "expr yDIST '{' dist_list '}'" | ~l~expr yDIST '{' dist_list '}' { $$=$1; $$ = $1 + " dist " + $3+"..."+$5; } ; fexpr: // For use as first part of statement (disambiguates <=) BISONPRE_COPY(expr,{s/~l~/f/g; s/~r~/f/g; s/~f__IGNORE~/__IGNORE/g;}) // {copied} ; ev_expr: // IEEE: event_expression // // for yOR/, see event_expression // // // IEEE: [ edge_identifier ] expression [ yIFF expression ] // // expr alone see below senitemEdge { } | ev_expr yIFF expr { } // // // IEEE: sequence_instance [ yIFF expression ] // // seq_inst is in expr, so matches senitem rule above // // // IEEE: event_expression yOR event_expression | ev_expr yOR ev_expr { } // // IEEE: event_expression ',' event_expression // // See real event_expression rule // //--------------------- // // IEEE: expr | BISONPRE_COPY(expr,{s/~l~/ev_/g; s/~r~/ev_/g; s/~p~/ev_/g; s/~noPar__IGNORE~/yP_PAR__IGNORE /g;}) // {copied} // // // IEEE: '(' event_expression ')' // // expr:'(' x ')' conflicts with event_expression:'(' event_expression ')' // // so we use a special expression class | '(' event_expression ')' { $$=$1; $$ = "(...)"; } // // IEEE: From normal expr: '(' expr ':' expr ':' expr ')' // // But must avoid conflict | '(' event_expression ':' expr ':' expr ')' { $$=$1; $$ = "(...)"; } ; //sexpr: See elsewhere //pexpr: See elsewhere exprOkLvalue: // expression that's also OK to use as a variable_lvalue ~l~exprScope { $$=$1; $$ = $1; } // // IEEE: concatenation/constant_concatenation | '{' cateList '}' { $$=$1; $$ = "{"+$2+"}"; } // // IEEE: concatenation/constant_concatenation+ constant_range_expression (1800-2009) | '{' cateList '}' '[' expr ']' { $$=$1; $$ = "{"+$2+"}["+$5+"]"; NEED_S09($4,"{}[]"); } | '{' cateList '}' '[' expr ':' expr ']' { $$=$1; $$ = "{"+$2+"}["+$5+$6+$7+"]"; NEED_S09($4,"{}[]"); } | '{' cateList '}' '[' expr yP_PLUSCOLON expr ']' { $$=$1; $$ = "{"+$2+"}["+$5+$6+$7+"]"; NEED_S09($4,"{}[]"); } | '{' cateList '}' '[' expr yP_MINUSCOLON expr ']' { $$=$1; $$ = "{"+$2+"}["+$5+$6+$7+"]"; NEED_S09($4,"{}[]"); } // // IEEE: assignment_pattern_expression // // IEEE: [ assignment_pattern_expression_type ] == [ ps_type_id /ps_paremeter_id/data_type] // // We allow more here than the spec requires | ~l~exprScope assignment_pattern { $$=$1; $$=$1+$2; } | data_type assignment_pattern { $$=$1; $$=$1+$2; } | assignment_pattern { $$=$1; $$=$1; } // | streaming_concatenation { $$=$1; $$ = $1; } ; fexprOkLvalue: // exprOkLValue, For use as first part of statement (disambiguates <=) BISONPRE_COPY(exprOkLvalue,{s/~l~/f/g}) // {copied} ; sexprOkLvalue: // exprOkLValue, For use by sequence_expr BISONPRE_COPY(exprOkLvalue,{s/~l~/s/g}) // {copied} ; pexprOkLvalue: // exprOkLValue, For use by property_expr BISONPRE_COPY(exprOkLvalue,{s/~l~/p/g}) // {copied} ; ev_exprOkLvalue: // exprOkLValue, For use by ev_expr BISONPRE_COPY(exprOkLvalue,{s/~l~/ev_/g}) // {copied} ; pev_exprOkLvalue: // exprOkLValue, For use by ev_expr BISONPRE_COPY(exprOkLvalue,{s/~l~/pev_/g}) // {copied} ; exprLvalue: // expression that should be a variable_lvalue ~f~exprOkLvalue { $$=$1; $$ = $1; } ; fexprLvalue: // For use as first part of statement (disambiguates <=) BISONPRE_COPY(exprLvalue,{s/~f~/f/g}) // {copied} ; exprScope: // scope and variable for use to inside an expression // // Here we've split method_call_root | implicit_class_handle | class_scope | package_scope // // from the object being called and let expr's "." deal with resolving it. // // (note method_call_root was simplified to require a primary in 1800-2009) // // // IEEE: [ implicit_class_handle . | class_scope | package_scope ] hierarchical_identifier select // // Or method_call_body without parenthesis // // See also varRefClassBit, which is the non-expr version of most of this yTHIS { $$=$1; $$ = $1; } | idArrayed { $$=$1; $$ = $1; } | package_scopeIdFollows idArrayed { $$=$1; $$ = $1+$2; } | class_scopeIdFollows idArrayed { $$=$1; $$ = $1+$2; } | ~l~expr '.' idArrayed { $$=$1; $$ = $1+"."+$3; PORTNET($1, $$); } // // expr below must be a "yTHIS" | ~l~expr '.' ySUPER { $$=$1; $$ = $1+"."+$3; } // // Part of implicit_class_handle | ySUPER { $$=$1; $$ = $1; } ; fexprScope: // exprScope, For use as first part of statement (disambiguates <=) BISONPRE_COPY(exprScope,{s/~l~/f/g}) // {copied} ; sexprScope: // exprScope, For use by sequence_expr BISONPRE_COPY(exprScope,{s/~l~/s/g}) // {copied} ; pexprScope: // exprScope, For use by property_expr BISONPRE_COPY(exprScope,{s/~l~/p/g}) // {copied} ; ev_exprScope: // exprScope, For use by ev_expr BISONPRE_COPY(exprScope,{s/~l~/ev_/g}) // {copied} ; pev_exprScope: // exprScope, For use by ev_expr BISONPRE_COPY(exprScope,{s/~l~/pev_/g}) // {copied} ; // Generic expressions exprOrDataType: // expr | data_type: combined to prevent conflicts expr { $$=$1; $$ = $1; } // // data_type includes id that overlaps expr, so special flavor | data_type { $$=$1; $$ = $1; } // // not in spec, but needed for $past(sig,1,,@(posedge clk)) | event_control { $$ = "event_control"; } ; exprOrDataTypeOrMinTypMax: // exprOrDataType or mintypmax_expression expr { $$=$1; $$ = $1; } | expr ':' expr ':' expr { $$=$1; $$ = $1+$2+$3+$4+$5; } // // data_type includes id that overlaps expr, so special flavor | data_type { $$=$1; $$ = $1; } // // not in spec, but needed for $past(sig,1,,@(posedge clk)) | event_control { $$ = "event_control"; } ; cateList: // // Not just 'expr' to prevent conflict via stream_concOrExprOrType stream_expression { $$=$1; $$ = $1; PIN_CONCAT_APPEND($1); } | cateList ',' stream_expression { $$=$1; $$ = $1+","+$3; PIN_CONCAT_APPEND($3); } ; exprOrDataTypeList: exprOrDataType { $$=$1; $$ = $1; } | exprOrDataTypeList ',' exprOrDataType { $$=$1; $$ = $1+","+$3; } | exprOrDataTypeList ',' { $$=$1; $$ = $1+","; } // Verilog::Parser only: ,, is ok ; list_of_argumentsE: // IEEE: [list_of_arguments] // // See comments under funcRef argsDottedList { $$=$1; $$=$1; } | argsExprListE { $$=$1; $$=$1; } | argsExprListE ',' argsDottedList { $$=$1; $$=$1+","+$3; } ; pev_list_of_argumentsE: // IEEE: [list_of_arguments] - pev_expr at bottom // // See comments under funcRef pev_argsDottedList { $$=$1; $$=$1; } | pev_argsExprListE { $$=$1; $$=$1; } | pev_argsExprListE ',' pev_argsDottedList { $$=$1; $$=$1+","+$3; } ; argsExprList: // IEEE: part of list_of_arguments (used where ,, isn't legal) expr { $$=$1; $$ = $1; } | argsExprList ',' expr { $$=$1; $$ = $1+","+$3; } ; argsExprListE: // IEEE: part of list_of_arguments argsExprOneE { $$=$1; $$ = $1; } | argsExprListE ',' argsExprOneE { $$=$1; $$ = $1+","+$3; } ; pev_argsExprListE: // IEEE: part of list_of_arguments - pev_expr at bottom pev_argsExprOneE { $$=$1; $$ = $1; } | pev_argsExprListE ',' pev_argsExprOneE { $$=$1; $$ = $1+","+$3; } ; argsExprOneE: // IEEE: part of list_of_arguments /*empty*/ { $$ = ""; } // ,, is legal in list_of_arguments | expr { $$=$1; $$ = $1; } ; pev_argsExprOneE: // IEEE: part of list_of_arguments - pev_expr at bottom /*empty*/ { $$ = ""; } // ,, is legal in list_of_arguments | pev_expr { $$=$1; $$ = $1; } ; argsDottedList: // IEEE: part of list_of_arguments argsDotted { $$=$1; $$=$1; } | argsDottedList ',' argsDotted { $$=$1; $$=$1+","+$3; } ; pev_argsDottedList: // IEEE: part of list_of_arguments - pev_expr at bottom pev_argsDotted { $$=$1; $$=$1; } | pev_argsDottedList ',' pev_argsDotted { $$=$1; $$=$1+","+$3; } ; argsDotted: // IEEE: part of list_of_arguments '.' idAny '(' ')' { $$=$1; $$=$1+$2+$3+$4; } | '.' idAny '(' expr ')' { $$=$1; $$=$1+$2+$3+$4+$5; } ; pev_argsDotted: // IEEE: part of list_of_arguments - pev_expr at bottom '.' idAny '(' ')' { $$=$1; $$=$1+$2+$3+$4; } | '.' idAny '(' pev_expr ')' { $$=$1; $$=$1+$2+$3+$4+$5; } ; streaming_concatenation: // ==IEEE: streaming_concatenation // // Need to disambiguate {<< expr-{ ... expr-} stream_concat } // // From {<< stream-{ ... stream-} } // // Likewise simple_type's idScoped from constExpr's idScope // // Thus we allow always any two operations. Sorry // // IEEE: "'{' yP_SL/R stream_concatenation '}'" // // IEEE: "'{' yP_SL/R simple_type stream_concatenation '}'" // // IEEE: "'{' yP_SL/R constExpr stream_concatenation '}'" '{' yP_SLEFT stream_concOrExprOrType '}' { $$=$1; $$="{<<"+$3+"}"; } | '{' yP_SRIGHT stream_concOrExprOrType '}' { $$=$1; $$="{>>"+$3+"}"; } | '{' yP_SLEFT stream_concOrExprOrType stream_concatenation '}' { $$=$1; $$="{<<"+$3+" "+$4+"}"; } | '{' yP_SRIGHT stream_concOrExprOrType stream_concatenation '}' { $$=$1; $$="{>>"+$3+" "+$4+"}"; } ; stream_concOrExprOrType: // IEEE: stream_concatenation | slice_size:simple_type | slice_size:constExpr cateList { $$=$1; $$=$1; } | simple_type { $$=$1; $$=$1; } // // stream_concatenation found via cateList:stream_expr:'{-normal-concat' // // simple_typeRef found via cateList:stream_expr:expr:id // // constant_expression found via cateList:stream_expr:expr ; stream_concatenation: // ==IEEE: stream_concatenation '{' stream_expressionList '}' { $$=$1; $$="{"+$2+"}"; } ; stream_expressionList: // IEEE: part of stream_concatenation stream_expression { $$=$1; $$=$1; } | stream_expressionList ',' stream_expression { $$=$1; $$=$1+","+$3; } ; stream_expression: // ==IEEE: stream_expression // // IEEE: array_range_expression expanded below expr { $$=$1; $$=$1; } | expr yWITH__BRA '[' expr ']' { $$=$1; $$=$1; } | expr yWITH__BRA '[' expr ':' expr ']' { $$=$1; $$=$1; } | expr yWITH__BRA '[' expr yP_PLUSCOLON expr ']' { $$=$1; $$=$1; } | expr yWITH__BRA '[' expr yP_MINUSCOLON expr ']' { $$=$1; $$=$1; } ; //************************************************ // Gate declarations // We can't tell between UDPs and modules as they aren't declared yet. // For simplicity, assume everything is a module, perhaps nameless, // and deal with it later. // IEEE: cmos_switchtype + enable_gatetype + mos_switchtype // + n_input_gatetype + n_output_gatetype + pass_en_switchtype // + pass_switchtype gateKwd: ygenGATE { $$=$1; INSTPREP($1,0,0); } | yAND { $$=$1; INSTPREP($1,0,0); } | yBUF { $$=$1; INSTPREP($1,0,0); } | yNAND { $$=$1; INSTPREP($1,0,0); } | yNOR { $$=$1; INSTPREP($1,0,0); } | yNOT { $$=$1; INSTPREP($1,0,0); } | yOR { $$=$1; INSTPREP($1,0,0); } | yXNOR { $$=$1; INSTPREP($1,0,0); } | yXOR { $$=$1; INSTPREP($1,0,0); } ; // This list is also hardcoded in VParseLex.l strength: // IEEE: strength0+strength1 - plus HIGHZ/SMALL/MEDIUM/LARGE ygenSTRENGTH { } | ySUPPLY0 { } | ySUPPLY1 { } ; strengthSpecE: // IEEE: drive_strength + pullup_strength + pulldown_strength + charge_strength - plus empty /* empty */ { } | strengthSpec { } ; strengthSpec: // IEEE: drive_strength + pullup_strength + pulldown_strength + charge_strength - plus empty yP_PAR__STRENGTH strength ')' { } | yP_PAR__STRENGTH strength ',' strength ')' { } ; //************************************************ // Tables combinational_body: // IEEE: combinational_body + sequential_body yTABLE tableJunkList yENDTABLE { } ; tableJunkList: tableJunk { } /* ignored */ | tableJunkList tableJunk { } /* ignored */ ; tableJunk: BISONPRE_NOT(yTABLE,yENDTABLE) { } | yTABLE tableJunk yENDTABLE { } | error {} ; //************************************************ // Specify specify_block: // ==IEEE: specify_block ySPECIFY specifyJunkList yENDSPECIFY { } | ySPECIFY yENDSPECIFY { } ; specifyJunkList: specifyJunk { } /* ignored */ | specifyJunkList specifyJunk { } /* ignored */ ; specifyJunk: BISONPRE_NOT(ySPECIFY,yENDSPECIFY) { } | ySPECIFY specifyJunk yENDSPECIFY { } | error {} ; specparam_declaration: // ==IEEE: specparam_declaration ySPECPARAM junkToSemiList ';' { } ; junkToSemiList: junkToSemi { } /* ignored */ | junkToSemiList junkToSemi { } /* ignored */ ; junkToSemi: BISONPRE_NOT(';',yENDSPECIFY,yENDMODULE) { } | error {} ; //************************************************ // IDs id: yaID__ETC { $$=$1; $$=$1; } ; idAny: // Any kind of identifier yaID__aPACKAGE { $$=$1; $$=$1; } | yaID__aTYPE { $$=$1; $$=$1; } | yaID__ETC { $$=$1; $$=$1; } ; idSVKwd: // Warn about non-forward compatible Verilog 2001 code // // yBIT, yBYTE won't work here as causes conflicts yDO { $$=$1; $$=$1; ERRSVKWD($1,$$); } | yFINAL { $$=$1; $$=$1; ERRSVKWD($1,$$); } ; variable_lvalue: // IEEE: variable_lvalue or net_lvalue // // Note many variable_lvalue's must use exprOkLvalue when arbitrary expressions may also exist idClassSel { $$=$1; $$ = $1; } | '{' variable_lvalueConcList '}' { $$=$1; $$ = $1+$2+$3; } // // IEEE: [ assignment_pattern_expression_type ] assignment_pattern_variable_lvalue // // We allow more assignment_pattern_expression_types then strictly required | data_type yP_TICKBRA variable_lvalueList '}' { $$=$1; $$ = $1+" "+$2+$3+$4; } | idClassSel yP_TICKBRA variable_lvalueList '}' { $$=$1; $$ = $1+" "+$2+$3+$4; } | /**/ yP_TICKBRA variable_lvalueList '}' { $$=$1; $$ = $1+$2+$3; } | streaming_concatenation { $$=$1; $$ = $1; } ; variable_lvalueConcList: // IEEE: part of variable_lvalue: '{' variable_lvalue { ',' variable_lvalue } '}' variable_lvalue { $$=$1; $$ = $1; } | variable_lvalueConcList ',' variable_lvalue { $$=$1; $$ = $1+","+$3; } ; variable_lvalueList: // IEEE: part of variable_lvalue: variable_lvalue { ',' variable_lvalue } variable_lvalue { $$=$1; $$ = $1; } | variable_lvalueList ',' variable_lvalue { $$=$1; $$ = $1+","+$3; } ; idClassSel: // Misc Ref to dotted, and/or arrayed, and/or bit-ranged variable idDotted { $$=$1; $$ = $1; } // // IEEE: [ implicit_class_handle . | package_scope ] hierarchical_variable_identifier select | yTHIS '.' idDotted { $$=$1; $$ = "this."+$3; } | ySUPER '.' idDotted { $$=$1; $$ = "super."+$3; } | yTHIS '.' ySUPER '.' idDotted { $$=$1; $$ = "this.super."+$3; } // // Expanded: package_scope idDotted | class_scopeIdFollows idDotted { $$=$1; $$ = $1+$2; } | package_scopeIdFollows idDotted { $$=$1; $$ = $1+$2; } ; idClassForeach: // Misc Ref to dotted, and/or arrayed, no bit range for foreach statement // // We can't just use the more general idClassSel // // because ,'s are allowed in the []'s idDottedForeach { $$=$1; $$ = $1; } // // IEEE: [ implicit_class_handle . | package_scope ] hierarchical_variable_identifier select | yTHIS '.' idDottedForeach { $$=$1; $$ = "this."+$3; } | ySUPER '.' idDottedForeach { $$=$1; $$ = "super."+$3; } | yTHIS '.' ySUPER '.' idDottedForeach { $$=$1; $$ = "this.super."+$3; } // // Expanded: package_scope idDotted | class_scopeIdFollows idDottedForeach { $$=$1; $$ = $1+$2; } | package_scopeIdFollows idDottedForeach { $$=$1; $$ = $1+$2; } ; hierarchical_identifierList: // IEEE: part of wait_statement hierarchical_identifier { } | hierarchical_identifierList ',' hierarchical_identifier { } ; hierarchical_identifierBit: // IEEE: "hierarchical_identifier bit_select" // // Not in grammar but "this." believed legal here idClassSel { } ; hierarchical_identifier: // IEEE: hierarchical_identifier, including extra bit_select // // +hierarchical_parameter_identifier // // Not in grammar but "this." believed legal here idClassSel { $$=$1; $$ = $1; } ; idDotted: yD_ROOT '.' idDottedMore { $$=$1; $$ = $1+"."+$3; } | idDottedMore { $$=$1; $$ = $1; } ; idDottedForeach: yD_ROOT '.' idDottedForeachMore { $$=$1; $$ = $1+"."+$3; } | idDottedForeachMore { $$=$1; $$ = $1; } ; idDottedMore: idArrayed { $$=$1; $$ = $1; } | idDottedMore '.' idArrayed { $$=$1; $$ = $1+"."+$3; } ; idDottedForeachMore: idForeach { $$=$1; $$ = $1; } | idDottedForeachMore '.' idForeach { $$=$1; $$ = $1+"."+$3; } ; // Single component of dotted path, maybe [#]. // Due to lookahead constraints, we can't know if [:] or [+:] are valid (last dotted part), // we'll assume so and cleanup later. // id below includes: // enum_identifier idArrayed: // IEEE: id + select id { $$=$1; $$ = $1; PORTNET($1, $1);} // // IEEE: part_select_range/constant_part_select_range | idArrayed '[' expr ']' { $$=$1; $$ = $1+"["+$3+"]"; PORTRANGE($3, $3);} | idArrayed '[' constExpr ':' constExpr ']' { $$=$1; $$ = $1+"["+$3+":"+$5+"]"; PORTRANGE($3, $5);} // // IEEE: indexed_range/constant_indexed_range | idArrayed '[' expr yP_PLUSCOLON constExpr ']' { $$=$1; $$ = $1+"["+$3+"+:"+$5+"]"; } | idArrayed '[' expr yP_MINUSCOLON constExpr ']' { $$=$1; $$ = $1+"["+$3+"-:"+$5+"]"; } ; idForeach: // IEEE: id + select + [loop_variables] // // Merge of foreach and idArrayed to prevent conflict id { $$=$1; $$ = $1; } // // IEEE: part_select_range/constant_part_select_range | idForeach '[' expr ']' { $$=$1; $$ = $1+"["+$3+"]"; } | idForeach '[' constExpr ':' constExpr ']' { $$=$1; $$ = $1+"["+$3+":"+$5+"]"; } // // IEEE: indexed_range/constant_indexed_range | idForeach '[' expr yP_PLUSCOLON constExpr ']' { $$=$1; $$ = $1+"["+$3+"+:"+$5+"]"; } | idForeach '[' expr yP_MINUSCOLON constExpr ']' { $$=$1; $$ = $1+"["+$3+"-:"+$5+"]"; } // // IEEE: part of foreach: [ loop_variables ] | idForeach '[' expr ',' loop_variables ']' { $$=$1; $$ = $1+"["+$3+","+$5+"]"; } ; strAsInt: yaSTRING { $$=$1; $$ = $1; } ; endLabelE: /* empty */ { } | ':' idAny { } | ':' yNEW__ETC { } ; //************************************************ // Clocking clocking_declaration: // IEEE: clocking_declaration clockingFront clocking_event ';' clocking_itemListE yENDCLOCKING endLabelE { PARSEP->symPopScope(VAstType::CLOCKING); } // // global clocking below - we allow item list, though not in grammar ; clockingFront: // IEEE: part of class_declaration yCLOCKING { PARSEP->symPushNewAnon(VAstType::CLOCKING); } | yCLOCKING idAny/*clocking_identifier*/ { PARSEP->symPushNew(VAstType::CLOCKING,$2); } | yDEFAULT yCLOCKING { PARSEP->symPushNewAnon(VAstType::CLOCKING); } | yDEFAULT yCLOCKING idAny/*clocking_identifier*/ { PARSEP->symPushNew(VAstType::CLOCKING,$3); } | yGLOBAL__CLOCKING yCLOCKING { PARSEP->symPushNewAnon(VAstType::CLOCKING); } | yGLOBAL__CLOCKING yCLOCKING idAny/*clocking_identifier*/ { PARSEP->symPushNew(VAstType::CLOCKING,$3); } ; clocking_event: // ==IEEE: clocking_event '@' id { } | '@' '(' event_expression ')' { } ; clocking_itemListE: /* empty */ { } | clocking_itemList { } ; clocking_itemList: // IEEE: [ clocking_item ] clocking_item { } | clocking_itemList clocking_item { } ; clocking_item: // ==IEEE: clocking_item yDEFAULT default_skew ';' { } | clocking_direction list_of_clocking_decl_assign ';' { } | assertion_item_declaration { } ; default_skew: // ==IEEE: default_skew yINPUT clocking_skew { } | yOUTPUT clocking_skew { } | yINPUT clocking_skew yOUTPUT clocking_skew { } ; clocking_direction: // ==IEEE: clocking_direction yINPUT clocking_skewE { } | yOUTPUT clocking_skewE { } | yINPUT clocking_skewE yOUTPUT clocking_skewE { } | yINOUT { } ; list_of_clocking_decl_assign: // ==IEEE: list_of_clocking_decl_assign clocking_decl_assign { } | list_of_clocking_decl_assign ',' clocking_decl_assign { } ; clocking_decl_assign: // ==IEEE: clocking_decl_assign idAny/*new-signal_identifier*/ { } | idAny/*new-signal_identifier*/ '=' expr { } ; clocking_skewE: // IEEE: [clocking_skew] /* empty */ { } | clocking_skew { } ; clocking_skew: // ==IEEE: clocking_skew yPOSEDGE { } | yPOSEDGE delay_control { } | yNEGEDGE { } | yNEGEDGE delay_control { } | yEDGE { NEED_S09($1,"edge"); } | yEDGE delay_control { NEED_S09($1,"edge"); } | delay_control { } ; cycle_delay: // ==IEEE: cycle_delay yP_POUNDPOUND yaINTNUM { } | yP_POUNDPOUND id { } | yP_POUNDPOUND '(' expr ')' { } ; //************************************************ // Asserts assertion_item_declaration: // ==IEEE: assertion_item_declaration property_declaration { } | sequence_declaration { } | let_declaration { } ; assertion_item: // ==IEEE: assertion_item concurrent_assertion_item { } | deferred_immediate_assertion_item { } ; deferred_immediate_assertion_item: // ==IEEE: deferred_immediate_assertion_item deferred_immediate_assertion_statement { } | id/*block_identifier*/ ':' deferred_immediate_assertion_statement { } ; procedural_assertion_statement: // ==IEEE: procedural_assertion_statement concurrent_assertion_statement { } | immediate_assertion_statement { } // // IEEE: checker_instantiation // // Unlike modules, checkers are the only "id id (...)" form in statements. | checker_instantiation { } ; immediate_assertion_statement: // ==IEEE: immediate_assertion_statement simple_immediate_assertion_statement { } | deferred_immediate_assertion_statement { } ; simple_immediate_assertion_statement: // ==IEEE: simple_immediate_assertion_statement // // IEEE: simple_immediate_assert_statement yASSERT '(' expr ')' action_block { } // // IEEE: simple_immediate_assume_statement | yASSUME '(' expr ')' action_block { } // // IEEE: simple_immediate_cover_statement | yCOVER '(' expr ')' stmt { } ; final_zero: // IEEE: part of deferred_immediate_assertion_statement '#' yaINTNUM { } // yaINTNUM is always a '0' // // 1800-2012: | yFINAL { } ; deferred_immediate_assertion_statement: // ==IEEE: deferred_immediate_assertion_statement // // IEEE: deferred_immediate_assert_statement yASSERT final_zero '(' expr ')' action_block { } // // IEEE: deferred_immediate_assume_statement | yASSUME final_zero '(' expr ')' action_block { } // // IEEE: deferred_immediate_cover_statement | yCOVER final_zero '(' expr ')' stmt { } ; expect_property_statement: // ==IEEE: expect_property_statement yEXPECT '(' property_spec ')' action_block { } ; concurrent_assertion_item: // IEEE: concurrent_assertion_item concurrent_assertion_statement { } | id/*block_identifier*/ ':' concurrent_assertion_statement { } // // IEEE: checker_instantiation // // identical to module_instantiation; see etcInst ; concurrent_assertion_statement: // ==IEEE: concurrent_assertion_statement // // IEEE: assert_property_statement yASSERT yPROPERTY '(' property_spec ')' action_block { } // // IEEE: assume_property_statement | yASSUME yPROPERTY '(' property_spec ')' action_block { } // // IEEE: cover_property_statement | yCOVER yPROPERTY '(' property_spec ')' stmtBlock { } // // IEEE: cover_sequence_statement | yCOVER ySEQUENCE '(' sexpr ')' stmt { } // // IEEE: yCOVER ySEQUENCE '(' clocking_event sexpr ')' stmt // // sexpr already includes "clocking_event sexpr" | yCOVER ySEQUENCE '(' clocking_event yDISABLE yIFF '(' expr/*expression_or_dist*/ ')' sexpr ')' stmt { } | yCOVER ySEQUENCE '(' yDISABLE yIFF '(' expr/*expression_or_dist*/ ')' sexpr ')' stmt { } // // IEEE: restrict_property_statement | yRESTRICT yPROPERTY '(' property_spec ')' ';' { } ; property_declaration: // ==IEEE: property_declaration property_declarationFront property_port_listE ';' property_declarationBody yENDPROPERTY endLabelE { PARSEP->symPopScope(VAstType::PROPERTY); } ; property_declarationFront: // IEEE: part of property_declaration yPROPERTY idAny/*property_identifier*/ { PARSEP->symPushNew(VAstType::PROPERTY,$2); } ; property_port_listE: // IEEE: [ ( [ property_port_list ] ) ] /* empty */ { } | '(' {VARRESET_LIST(""); VARIO("input"); } property_port_list ')' { VARRESET_NONLIST(""); } ; property_port_list: // ==IEEE: property_port_list property_port_item { } | property_port_list ',' property_port_item { } ; property_port_item: // IEEE: property_port_item/sequence_port_item // // Merged in sequence_port_item // // IEEE: property_lvar_port_direction ::= yINPUT // // prop IEEE: [ yLOCAL [ yINPUT ] ] property_formal_type // // id {variable_dimension} [ '=' property_actual_arg ] // // seq IEEE: [ yLOCAL [ sequence_lvar_port_direction ] ] sequence_formal_type // // id {variable_dimension} [ '=' sequence_actual_arg ] property_port_itemFront property_port_itemAssignment { } ; property_port_itemFront: // IEEE: part of property_port_item/sequence_port_item // property_port_itemDirE property_formal_typeNoDt { VARDTYPE($2); } // // data_type_or_implicit | property_port_itemDirE data_type { VARDTYPE($2); } | property_port_itemDirE yVAR data_type { VARDTYPE($3); } | property_port_itemDirE yVAR implicit_typeE { VARDTYPE($3); } | property_port_itemDirE signingE rangeList { VARDTYPE(SPACED($2,$3)); } | property_port_itemDirE /*implicit*/ { /*VARDTYPE-same*/ } ; property_port_itemAssignment: // IEEE: part of property_port_item/sequence_port_item/checker_port_direction portSig variable_dimensionListE { VARDONE($1, $1, $2, ""); PINNUMINC(); } | portSig variable_dimensionListE '=' property_actual_arg { VARDONE($1, $1, $2, $4); PINNUMINC(); } ; property_port_itemDirE: /* empty */ { } | yLOCAL__ETC { } | yLOCAL__ETC port_direction { } ; property_declarationBody: // IEEE: part of property_declaration assertion_variable_declarationList property_statement_spec { } // // IEEE-2012: Incorectly hasyCOVER ySEQUENCE then property_spec here. // // Fixed in IEEE 1800-2017 | property_statement_spec { } ; assertion_variable_declarationList: // IEEE: part of assertion_variable_declaration assertion_variable_declaration { } | assertion_variable_declarationList assertion_variable_declaration { } ; sequence_declaration: // ==IEEE: sequence_declaration sequence_declarationFront sequence_port_listE ';' sequence_declarationBody yENDSEQUENCE endLabelE { PARSEP->symPopScope(VAstType::SEQUENCE); } ; sequence_declarationFront: // IEEE: part of sequence_declaration ySEQUENCE idAny/*new_sequence*/ { PARSEP->symPushNew(VAstType::SEQUENCE,$2); } ; sequence_port_listE: // IEEE: [ ( [ sequence_port_list ] ) ] // // IEEE: sequence_lvar_port_direction ::= yINPUT | yINOUT | yOUTPUT // // IEEE: [ yLOCAL [ sequence_lvar_port_direction ] ] sequence_formal_type // // id {variable_dimension} [ '=' sequence_actual_arg ] // // All this is almost identically the same as a property. // // Difference is only yINOUT/yOUTPUT (which might be added to 1800-2012) // // and yPROPERTY. So save some work. property_port_listE { } ; property_formal_typeNoDt: // IEEE: property_formal_type (w/o implicit) sequence_formal_typeNoDt { $$ = $1; } | yPROPERTY { $$ = "property"; } ; sequence_formal_typeNoDt: // ==IEEE: sequence_formal_type (w/o data_type_or_implicit) // // IEEE: data_type_or_implicit // // implicit expanded where used ySEQUENCE { $$ = "sequence"; } // // IEEE-2009: yEVENT // // already part of data_type. Removed in 1800-2012. | yUNTYPED { $$ = "untyped"; } ; sequence_declarationBody: // IEEE: part of sequence_declaration // // 1800-2012 makes ';' optional assertion_variable_declarationList sexpr { } | assertion_variable_declarationList sexpr ';' { } | sexpr { } | sexpr ';' { } ; property_spec: // IEEE: property_spec // // IEEE: [clocking_event ] [ yDISABLE yIFF '(' expression_or_dist ')' ] property_expr // // matches property_spec: "clocking_event property_expr" so we put it there yDISABLE yIFF '(' expr ')' pexpr { } | pexpr { } ; property_statement_spec: // ==IEEE: property_statement_spec // // IEEE: [ clocking_event ] [ yDISABLE yIFF '(' expression_or_dist ')' ] property_statement property_statement { } | yDISABLE yIFF '(' expr/*expression_or_dist*/ ')' property_statement { } // // IEEE: clocking_event property_statement // // IEEE: clocking_event yDISABLE yIFF '(' expr/*expression_or_dist*/ ')' property_statement // // Both overlap pexpr:"clocking_event pexpr" the difference is // // property_statement:property_statementCaseIf so replicate it | clocking_event property_statementCaseIf { } | clocking_event yDISABLE yIFF '(' expr/*expression_or_dist*/ ')' property_statementCaseIf { } ; property_statement: // ==IEEE: property_statement // // Doesn't make sense to have "pexpr ;" in pexpr rule itself, so we split out case/if pexpr ';' { } // // Note this term replicated in property_statement_spec // // If committee adds terms, they may need to be there too. | property_statementCaseIf { } ; property_statementCaseIf: // IEEE: property_statement - minus pexpr yCASE '(' expr/*expression_or_dist*/ ')' property_case_itemList yENDCASE { } | yCASE '(' expr/*expression_or_dist*/ ')' yENDCASE { } | yIF '(' expr/*expression_or_dist*/ ')' pexpr %prec prLOWER_THAN_ELSE { } | yIF '(' expr/*expression_or_dist*/ ')' pexpr yELSE pexpr { } ; property_case_itemList: // IEEE: {property_case_item} property_case_item { } | property_case_itemList ',' property_case_item { } ; property_case_item: // ==IEEE: property_case_item // // IEEE: expression_or_dist { ',' expression_or_dist } ':' property_statement // // IEEE 1800-2012 changed from property_statement to property_expr // // IEEE 1800-2017 changed to require the semicolon caseCondList ':' pexpr { } | caseCondList ':' pexpr ';' { } | yDEFAULT pexpr { } | yDEFAULT ':' pexpr ';' { } ; pev_expr: // IEEE: property_actual_arg | expr // // which expands to pexpr | event_expression // // Used in port and function calls, when we can't know yet if something // // is a function/sequence/property or instance/checker pin. // // // '(' pev_expr ')' // // Already in pexpr // // IEEE: event_expression ',' event_expression // // ','s are legal in event_expressions, but parens required to avoid conflict with port-sep-, // // IEEE: event_expression yOR event_expression // // Already in pexpr - needs removal there // // IEEE: event_expression yIFF expr // // Already in pexpr - needs removal there // senitemEdge { $$=$1; } // //============= pexpr rules copied for pev_expr | BISONPRE_COPY_ONCE(pexpr,{s/~o~p/pev_/g; }) // {copied} // //============= sexpr rules copied for pev_expr | BISONPRE_COPY_ONCE(sexpr,{s/~p~s/pev_/g; }) // {copied} // //============= expr rules copied for pev_expr | BISONPRE_COPY_ONCE(expr,{s/~l~/pev_/g; s/~p~/pev_/g; s/~noPar__IGNORE~/yP_PAR__IGNORE /g; }) // {copied} ; pexpr: // IEEE: property_expr (The name pexpr is important as regexps just add an "p" to expr.) // // // IEEE: sequence_expr // // Expanded below // // // IEEE: '(' pexpr ')' // // Expanded below // yNOT pexpr %prec prNEGATION { } | ySTRONG '(' sexpr ')' { } | yWEAK '(' sexpr ')' { } // // IEEE: pexpr yOR pexpr // // IEEE: pexpr yAND pexpr // // Under ~p~sexpr and/or ~p~sexpr // // // IEEE: "sequence_expr yP_ORMINUSGT pexpr" // // Instead we use pexpr to prevent conflicts | ~o~pexpr yP_ORMINUSGT pexpr { } | ~o~pexpr yP_OREQGT pexpr { } // // // IEEE-2009: property_statement // // IEEE-2012: yIF and yCASE | property_statementCaseIf { } // | ~o~pexpr/*sexpr*/ yP_POUNDMINUSPD pexpr { } | ~o~pexpr/*sexpr*/ yP_POUNDEQPD pexpr { } | yNEXTTIME pexpr { } | yS_NEXTTIME pexpr { } | yNEXTTIME '[' expr/*const*/ ']' pexpr %prec yNEXTTIME { } | yS_NEXTTIME '[' expr/*const*/ ']' pexpr %prec yS_NEXTTIME { } | yALWAYS pexpr { } | yALWAYS '[' cycle_delay_const_range_expression ']' pexpr %prec yALWAYS { } | yS_ALWAYS '[' constant_range ']' pexpr %prec yS_ALWAYS { } | yS_EVENTUALLY pexpr { } | yEVENTUALLY '[' constant_range ']' pexpr %prec yEVENTUALLY { } | yS_EVENTUALLY '[' cycle_delay_const_range_expression ']' pexpr %prec yS_EVENTUALLY { } | ~o~pexpr yUNTIL pexpr { } | ~o~pexpr yS_UNTIL pexpr { } | ~o~pexpr yUNTIL_WITH pexpr { } | ~o~pexpr yS_UNTIL_WITH pexpr { } | ~o~pexpr yIMPLIES pexpr { } // // yIFF also used by event_expression | ~o~pexpr yIFF ~o~pexpr { } | yACCEPT_ON '(' expr/*expression_or_dist*/ ')' pexpr %prec yACCEPT_ON { } | yREJECT_ON '(' expr/*expression_or_dist*/ ')' pexpr %prec yREJECT_ON { } | ySYNC_ACCEPT_ON '(' expr/*expression_or_dist*/ ')' pexpr %prec ySYNC_ACCEPT_ON { } | ySYNC_REJECT_ON '(' expr/*expression_or_dist*/ ')' pexpr %prec ySYNC_REJECT_ON { } // // // IEEE: "property_instance" // // Looks just like a function/method call // // // Note "clocking_event pexpr" overlaps property_statement_spec: clocking_event property_statement // // // Include property_specDisable to match property_spec rule | clocking_event yDISABLE yIFF '(' expr ')' pexpr %prec prSEQ_CLOCKING { } // //============= sexpr rules copied for property_expr | BISONPRE_COPY_ONCE(sexpr,{s/~p~s/p/g; }) // {copied} // //============= expr rules copied for property_expr | BISONPRE_COPY_ONCE(expr,{s/~l~/p/g; s/~p~/p/g; s/~noPar__IGNORE~/yP_PAR__IGNORE /g; }) // {copied} ; sexpr: // ==IEEE: sequence_expr (The name sexpr is important as regexps just add an "s" to expr.) // // ********* RULES COPIED IN sequence_exprProp // // For precedence, see IEEE 17.7.1 // // // IEEE: "cycle_delay_range sequence_expr { cycle_delay_range sequence_expr }" // // IEEE: "sequence_expr cycle_delay_range sequence_expr { cycle_delay_range sequence_expr }" // // Both rules basically mean we can repeat sequences, so make it simpler: cycle_delay_range sexpr %prec yP_POUNDPOUND { } | ~p~sexpr cycle_delay_range sexpr %prec prPOUNDPOUND_MULTI { } // // // IEEE: expression_or_dist [ boolean_abbrev ] // // Note expression_or_dist includes "expr"! // // sexpr/*sexpression_or_dist*/ --- Hardcoded below | ~p~sexpr/*sexpression_or_dist*/ boolean_abbrev { } // // // IEEE: "sequence_instance [ sequence_abbrev ]" // // version without sequence_abbrev looks just like normal function call // // version w/sequence_abbrev matches above; expression_or_dist:expr:func boolean_abbrev:sequence_abbrev // // // IEEE: '(' expression_or_dist {',' sequence_match_item } ')' [ boolean_abbrev ] // // IEEE: '(' sexpr {',' sequence_match_item } ')' [ sequence_abbrev ] // // As sequence_expr includes expression_or_dist, and boolean_abbrev includes sequence_abbrev: // // '(' sequence_expr {',' sequence_match_item } ')' [ boolean_abbrev ] // // "'(' sexpr ')' boolean_abbrev" matches "[sexpr:'(' expr ')'] boolean_abbrev" so we can simply drop it | '(' ~p~sexpr ')' { $$=$1; $$=$1+$2+$3; } | '(' ~p~sexpr ',' sequence_match_itemList ')' { } // // // AND/OR are between pexprs OR sexprs | ~p~sexpr yAND ~p~sexpr { $$=$1; $$=$1+$2+$3; } | ~p~sexpr yOR ~p~sexpr { $$=$1; $$=$1+$2+$3; } // // Intersect always has an sexpr rhs | ~p~sexpr yINTERSECT sexpr { $$=$1; $$=$1+$2+$3; } // | yFIRST_MATCH '(' sexpr ')' { } | yFIRST_MATCH '(' sexpr ',' sequence_match_itemList ')' { } | ~p~sexpr/*sexpression_or_dist*/ yTHROUGHOUT sexpr { } // // Below pexpr's are really sequence_expr, but avoid conflict // // IEEE: sexpr yWITHIN sexpr | ~p~sexpr yWITHIN sexpr { $$=$1; $$=$1+$2+$3; } // // Note concurrent_assertion had duplicate rule for below | clocking_event ~p~sexpr %prec prSEQ_CLOCKING { } // //============= expr rules copied for sequence_expr | BISONPRE_COPY_ONCE(expr,{s/~l~/s/g; s/~p~/s/g; s/~noPar__IGNORE~/yP_PAR__IGNORE /g; }) // {copied} ; cycle_delay_range: // IEEE: ==cycle_delay_range // // These three terms in 1800-2005 ONLY yP_POUNDPOUND yaINTNUM { } | yP_POUNDPOUND id { } | yP_POUNDPOUND '(' constExpr ')' { } // // In 1800-2009 ONLY: // // IEEE: yP_POUNDPOUND constant_primary // // UNSUP: This causes a big grammer ambiguity // // as ()'s mismatch between primary and the following statement // // the sv-ac committee has been asked to clarify (Mantis 1901) | yP_POUNDPOUND '[' cycle_delay_const_range_expression ']' { } | yP_POUNDPOUND yP_BRASTAR ']' { } | yP_POUNDPOUND yP_BRAPLUSKET { } ; sequence_match_itemList: // IEEE: [sequence_match_item] part of sequence_expr sequence_match_item { } | sequence_match_itemList ',' sequence_match_item { } ; sequence_match_item: // ==IEEE: sequence_match_item // // IEEE says: operator_assignment // // IEEE says: inc_or_dec_expression // // IEEE says: subroutine_call // // This is the same list as... for_step_assignment { } ; boolean_abbrev: // ==IEEE: boolean_abbrev // // IEEE: consecutive_repetition yP_BRASTAR const_or_range_expression ']' { } | yP_BRASTAR ']' { } | yP_BRAPLUSKET { } // // IEEE: non_consecutive_repetition | yP_BRAEQ const_or_range_expression ']' { } // // IEEE: goto_repetition | yP_BRAMINUSGT const_or_range_expression ']' { } ; const_or_range_expression: // ==IEEE: const_or_range_expression constExpr { } | cycle_delay_const_range_expression { } ; constant_range: // ==IEEE: constant_range constExpr ':' constExpr { } ; cycle_delay_const_range_expression: // ==IEEE: cycle_delay_const_range_expression // // Note '$' is part of constExpr constExpr ':' constExpr { } ; //************************************************ // Let let_declaration: // ==IEEE: let_declaration let_declarationFront let_port_listE '=' expr ';' { PARSEP->symPopScope(VAstType::LET); } ; let_declarationFront: // IEEE: part of let_declaration yLET idAny/*let_identifier*/ { PARSEP->symPushNew(VAstType::LET,$2); } ; let_port_listE: // ==IEEE: let_port_list /* empty */ // // IEEE: let_port_list // // No significant difference from task ports | '(' tf_port_listE ')' { VARRESET_NONLIST(""); } ; //************************************************ // Covergroup covergroup_declaration: // ==IEEE: covergroup_declaration covergroup_declarationFront coverage_eventE ';' coverage_spec_or_optionListE yENDGROUP endLabelE { PARSEP->endgroupCb($5,$5); PARSEP->symPopScope(VAstType::COVERGROUP); } | covergroup_declarationFront '(' tf_port_listE ')' coverage_eventE ';' coverage_spec_or_optionListE yENDGROUP endLabelE { PARSEP->endgroupCb($8,$8); PARSEP->symPopScope(VAstType::COVERGROUP); } ; covergroup_declarationFront: // IEEE: part of covergroup_declaration yCOVERGROUP idAny { PARSEP->symPushNew(VAstType::COVERGROUP,$2); PARSEP->covergroupCb($1,$1,$2); } ; cgexpr: // IEEE-2012: covergroup_expression, before that just expression expr { $$=$1; $$ = $1; } ; coverage_spec_or_optionListE: // IEEE: [{coverage_spec_or_option}] /* empty */ { } | coverage_spec_or_optionList { } ; coverage_spec_or_optionList: // IEEE: {coverage_spec_or_option} coverage_spec_or_option { } | coverage_spec_or_optionList coverage_spec_or_option { } ; coverage_spec_or_option: // ==IEEE: coverage_spec_or_option // // IEEE: coverage_spec cover_point { } | cover_cross { } | coverage_option ';' { } | error { } ; coverage_option: // ==IEEE: coverage_option // // option/type_option aren't really keywords id/*yOPTION | yTYPE_OPTION*/ '.' idAny/*member_identifier*/ '=' expr { } ; cover_point: // ==IEEE: cover_point /**/ yCOVERPOINT expr iffE bins_or_empty { } // // IEEE-2012: class_scope before an ID | /**/ /**/ /**/ id ':' yCOVERPOINT expr iffE bins_or_empty { } | class_scope_id ':' yCOVERPOINT expr iffE bins_or_empty { } | class_scope_id id data_type id ':' yCOVERPOINT expr iffE bins_or_empty { } | class_scope_id id /**/ id ':' yCOVERPOINT expr iffE bins_or_empty { } | /**/ id /**/ id ':' yCOVERPOINT expr iffE bins_or_empty { } // // IEEE-2012: | bins_or_empty { } ; iffE: // IEEE: part of cover_point, others /* empty */ { } | yIFF '(' expr ')' { } ; bins_or_empty: // ==IEEE: bins_or_empty '{' bins_or_optionsList '}' { } | '{' '}' { } | ';' { } ; bins_or_optionsList: // IEEE: { bins_or_options ';' } bins_or_options ';' { } | bins_or_optionsList bins_or_options ';' { } ; bins_or_options: // ==IEEE: bins_or_options // // Superset of IEEE - we allow []'s in more places coverage_option { } // // Can't use wildcardE as results in conflicts | /**/ bins_keyword id/*bin_identifier*/ bins_orBraE '=' '{' open_range_list '}' iffE { } | yWILDCARD bins_keyword id/*bin_identifier*/ bins_orBraE '=' '{' open_range_list '}' iffE { } | /**/ bins_keyword id/*bin_identifier*/ bins_orBraE '=' '{' open_range_list '}' yWITH__CUR '{' cgexpr ')' iffE { } | yWILDCARD bins_keyword id/*bin_identifier*/ bins_orBraE '=' '{' open_range_list '}' yWITH__CUR '{' cgexpr ')' iffE { } // // // cgexpr part of trans_list // | /**/ bins_keyword id/*bin_identifier*/ bins_orBraE '=' trans_list iffE { } | yWILDCARD bins_keyword id/*bin_identifier*/ bins_orBraE '=' trans_list iffE { } // | bins_keyword id/*bin_identifier*/ bins_orBraE '=' yDEFAULT iffE { } // | bins_keyword id/*bin_identifier*/ bins_orBraE '=' yDEFAULT ySEQUENCE iffE { } ; bins_orBraE: // IEEE: part of bins_or_options: /* empty */ { } | '[' ']' { } | '[' cgexpr ']' { } ; bins_keyword: // ==IEEE: bins_keyword yBINS { } | yILLEGAL_BINS { } | yIGNORE_BINS { } ; covergroup_range_list: // ==IEEE: covergroup_range_list covergroup_value_range { } | covergroup_range_list ',' covergroup_value_range { } ; trans_list: // ==IEEE: trans_list '(' trans_set ')' { } | trans_list ',' '(' trans_set ')' { } ; trans_set: // ==IEEE: trans_set trans_range_list { } // // Note the { => } in the grammer, this is really a list | trans_set yP_EQGT trans_range_list { } ; trans_range_list: // ==IEEE: trans_range_list trans_item { } | trans_item yP_BRASTAR repeat_range ']' { } | trans_item yP_BRAMINUSGT repeat_range ']' { } | trans_item yP_BRAEQ repeat_range ']' { } ; trans_item: // ==IEEE: range_list covergroup_range_list { } ; repeat_range: // ==IEEE: repeat_range cgexpr { } | cgexpr ':' cgexpr { } ; cover_cross: // ==IEEE: cover_cross id/*cover_point_identifier*/ ':' yCROSS list_of_cross_items iffE cross_body { } | /**/ yCROSS list_of_cross_items iffE cross_body { } ; list_of_cross_items: // ==IEEE: list_of_cross_items cross_item ',' cross_item { } | cross_item ',' cross_item ',' cross_itemList { } ; cross_itemList: // IEEE: part of list_of_cross_items cross_item | cross_itemList ',' cross_item { } ; cross_item: // ==IEEE: cross_item idAny/*cover_point_identifier or variable_identifier*/ { } ; cross_body: // ==IEEE: cross_body '{' '}' { } // // IEEE-2012: No semicolon here, mistake in spec | '{' cross_body_itemSemiList '}' { } | ';' { } ; cross_body_itemSemiList: // IEEE: part of cross_body cross_body_item ';' { } | cross_body_itemSemiList cross_body_item ';' { } ; cross_body_item: // ==IEEE: cross_body_item // // IEEE: our semicolon is in the list bins_selection_or_option { } | function_declaration { } ; bins_selection_or_option: // ==IEEE: bins_selection_or_option coverage_option { } | bins_selection { } ; bins_selection: // ==IEEE: bins_selection bins_keyword idAny/*new-bin_identifier*/ '=' select_expression iffE { } ; select_expression: // ==IEEE: select_expression // // IEEE: select_condition expanded here yBINSOF '(' bins_expression ')' { } | yBINSOF '(' bins_expression ')' yINTERSECT '{' covergroup_range_list '}' { } | yWITH__PAREN '(' cgexpr ')' { } // // IEEE-2012: Need clarification as to precedence //UNSUP yWITH__PAREN '(' cgexpr ')' yMATCHES cgexpr { } | '!' yBINSOF '(' bins_expression ')' { } | '!' yBINSOF '(' bins_expression ')' yINTERSECT '{' covergroup_range_list '}' { } | '!' yWITH__PAREN '(' cgexpr ')' { } // // IEEE-2012: Need clarification as to precedence //UNSUP '!' yWITH__PAREN '(' cgexpr ')' yMATCHES cgexpr { } | select_expression yP_ANDAND select_expression { } | select_expression yP_OROR select_expression { } | '(' select_expression ')' { } // // IEEE-2012: cross_identifier // // Part of covergroup_expression - generic identifier // // IEEE-2012: Need clarification as to precedence //UNSUP covergroup_expression [ yMATCHES covergroup_expression ] ; bins_expression: // ==IEEE: bins_expression // // "cover_point_identifier" and "variable_identifier" look identical id/*variable_identifier or cover_point_identifier*/ { } | id/*cover_point_identifier*/ '.' idAny/*bins_identifier*/ { } ; coverage_eventE: // IEEE: [ coverage_event ] /* empty */ { } | clocking_event { } | yWITH__ETC function idAny/*"sample"*/ '(' tf_port_listE ')' { } | yP_ATAT '(' block_event_expression ')' { } ; block_event_expression: // ==IEEE: block_event_expression block_event_expressionTerm { } | block_event_expression yOR block_event_expressionTerm { } ; block_event_expressionTerm: // IEEE: part of block_event_expression yBEGIN hierarchical_btf_identifier { } | yEND hierarchical_btf_identifier { } ; hierarchical_btf_identifier: // ==IEEE: hierarchical_btf_identifier // // hierarchical_tf_identifier + hierarchical_block_identifier hierarchical_identifier/*tf_or_block*/ { } // // method_identifier | hierarchical_identifier class_scope_id { } | hierarchical_identifier id { } ; //********************************************************************** // Randsequence randsequence_statement: // ==IEEE: randsequence_statement yRANDSEQUENCE '(' ')' productionList yENDSEQUENCE { } | yRANDSEQUENCE '(' id/*production_identifier*/ ')' productionList yENDSEQUENCE { } ; productionList: // IEEE: production+ production { } | productionList production { } ; production: // ==IEEE: production productionFront ':' rs_ruleList ';' { } ; productionFront: // IEEE: part of production function_data_type id/*production_identifier*/ { } | /**/ id/*production_identifier*/ { } | function_data_type id/*production_identifier*/ '(' tf_port_listE ')' { } | /**/ id/*production_identifier*/ '(' tf_port_listE ')' { } ; rs_ruleList: // IEEE: rs_rule+ part of production rs_rule { } | rs_ruleList '|' rs_rule { } ; rs_rule: // ==IEEE: rs_rule rs_production_list { } | rs_production_list yP_COLONEQ weight_specification { } | rs_production_list yP_COLONEQ weight_specification rs_code_block { } ; rs_production_list: // ==IEEE: rs_production_list rs_prodList { } | yRAND yJOIN /**/ production_item production_itemList { } | yRAND yJOIN '(' expr ')' production_item production_itemList { } ; weight_specification: // ==IEEE: weight_specification yaINTNUM { } | idClassSel/*ps_identifier*/ { } | '(' expr ')' { } ; rs_code_block: // ==IEEE: rs_code_block '{' '}' { } | '{' rs_code_blockItemList '}' { } ; rs_code_blockItemList: // IEEE: part of rs_code_block rs_code_blockItem { } | rs_code_blockItemList rs_code_blockItem { } ; rs_code_blockItem: // IEEE: part of rs_code_block data_declaration { } | stmt { } ; rs_prodList: // IEEE: rs_prod+ rs_prod { } | rs_prodList rs_prod { } ; rs_prod: // ==IEEE: rs_prod production_item { } | rs_code_block { } // // IEEE: rs_if_else | yIF '(' expr ')' production_item %prec prLOWER_THAN_ELSE { } | yIF '(' expr ')' production_item yELSE production_item { } // // IEEE: rs_repeat | yREPEAT '(' expr ')' production_item { } // // IEEE: rs_case | yCASE '(' expr ')' rs_case_itemList yENDCASE { } ; production_itemList: // IEEE: production_item+ production_item { } | production_itemList production_item { } ; production_item: // ==IEEE: production_item id/*production_identifier*/ { } | id/*production_identifier*/ '(' list_of_argumentsE ')' { } ; rs_case_itemList: // IEEE: rs_case_item+ rs_case_item { } | rs_case_itemList rs_case_item { } ; rs_case_item: // ==IEEE: rs_case_item caseCondList ':' production_item ';' { } | yDEFAULT production_item ';' { } | yDEFAULT ':' production_item ';' { } ; //********************************************************************** // Checker checker_declaration: // ==IEEE: part of checker_declaration checkerFront checker_port_listE ';' checker_or_generate_itemListE yENDCHECKER endLabelE { PARSEP->symPopScope(VAstType::CHECKER); } ; checkerFront: // IEEE: part of checker_declaration yCHECKER idAny/*checker_identifier*/ { PARSEP->symPushNew(VAstType::CHECKER, $2); } ; checker_port_listE: // IEEE: [ ( [ checker_port_list ] ) ] // // checker_port_item is basically the same as property_port_item, minus yLOCAL:: // // Want to bet 1800-2012 adds local to checkers? property_port_listE { } ; checker_or_generate_itemListE: // IEEE: [{ checker_or_generate_itemList }] /* empty */ { } | checker_or_generate_itemList { } ; checker_or_generate_itemList: // IEEE: { checker_or_generate_itemList } checker_or_generate_item { } | checker_or_generate_itemList checker_or_generate_item { } ; checker_or_generate_item: // ==IEEE: checker_or_generate_item checker_or_generate_item_declaration { } | initial_construct { } // // IEEE: checker_construct | yALWAYS stmtBlock { } | final_construct { } | assertion_item { } | continuous_assign { } | checker_generate_item { } ; checker_or_generate_item_declaration: // ==IEEE: checker_or_generate_item_declaration data_declaration { } | yRAND data_declaration { } | function_declaration { } | checker_declaration { } | assertion_item_declaration { } | covergroup_declaration { } | overload_declaration { } | genvar_declaration { } | clocking_declaration { } | yDEFAULT yCLOCKING id/*clocking_identifier*/ ';' { } | yDEFAULT yDISABLE yIFF expr/*expression_or_dist*/ ';' { } | ';' { } ; checker_generate_item: // ==IEEE: checker_generate_item // // Specialized for checker so need "c_" prefixes here c_loop_generate_construct { } | c_conditional_generate_construct { } | c_generate_region { } // | elaboration_system_task { } ; checker_instantiation: // // Only used for procedural_assertion_item's // // Version in concurrent_assertion_item looks like etcInst // // Thus instead of *_checker_port_connection we can use etcInst's cellpinList id/*checker_identifier*/ id '(' cellpinList ')' ';' { } ; //********************************************************************** // Class class_declaration: // ==IEEE: part of class_declaration // // IEEE-2012: using this also for interface_class_declaration // // The classExtendsE rule relys on classFront having the // // new class scope correct via classFront classFront parameter_port_listE classExtendsE classImplementsE ';' class_itemListE yENDCLASS endLabelE { PARSEP->endclassCb($7,$7); PARSEP->symPopScope(VAstType::CLASS); } ; classFront: // IEEE: part of class_declaration classVirtualE yCLASS lifetimeE idAny/*class_identifier*/ { PARSEP->symPushNew(VAstType::CLASS, $4); PARSEP->classCb($2,$2,$4,$1); } // // IEEE: part of interface_class_declaration | yINTERFACE yCLASS lifetimeE idAny/*class_identifier*/ { PARSEP->symPushNew(VAstType::CLASS, $4); PARSEP->classCb($2,$2,$4,$1); } ; classVirtualE: /* empty */ { $$=""; } | yVIRTUAL__CLASS { $$=$1; $$=$1; } ; classExtendsE: // IEEE: part of class_declaration // // The classExtendsE rule relys on classFront having the // // new class scope correct via classFront /* empty */ { } | yEXTENDS class_typeWithoutId { PARSEP->syms().import($1,$2,$2,"*"); } | yEXTENDS class_typeWithoutId '(' list_of_argumentsE ')' { PARSEP->syms().import($1,$2,$2,"*"); } ; classImplementsE: // IEEE: part of class_declaration // // All 1800-2012 /* empty */ { } | yIMPLEMENTS classImplementsList { PARSEP->syms().import($1,$2,$2,"*"); } ; classImplementsList: // IEEE: part of class_declaration // // All 1800-2012 class_typeWithoutId { } | classImplementsList ',' class_typeWithoutId { } ; //========= // Package scoping - to traverse the symbol table properly, the final identifer // must be included in the rules below. // Each of these must end with {symsPackageDone | symsClassDone} ps_id_etc: // package_scope + general id package_scopeIdFollowsE id { $$=$1; $$=$1+$2; } ; class_scope_id: // class_scope + id etc class_scopeIdFollows id { $$=$1; $$=$1; $$=$1+$2; } ; //=== Below rules assume special scoping per above class_typeWithoutId: // as with class_typeWithoutId but allow yaID__aTYPE // // and we thus don't need to resolve it in specified package package_scopeIdFollowsE class_typeOneList { $$=$2; $$=$2; $$=$1+$2; } ; class_scopeWithoutId: // class_type standalone without following id // // and we thus don't need to resolve it in specified package class_scopeIdFollows { $$=$1; $$=$1; $$=$1; PARSEP->symTableNextId(NULL); } ; class_scopeIdFollows: // IEEE: class_scope + type // // IEEE: "class_type yP_COLONCOLON" // // IMPORTANT: The lexer will parse the following ID to be in the found package // // But class_type:'::' conflicts with class_scope:'::' so expand here package_scopeIdFollowsE class_typeOneListColonIdFollows { $$=$2; $$=$2; $$=$1+$2; } ; class_typeOneListColonIdFollows: // IEEE: class_type :: but allow yaID__aTYPE class_typeOneList yP_COLONCOLON { $$=$1; $$=$1; $$=$1+$2; PARSEP->symTableNextId($1); } ; class_typeOneList: // IEEE: class_type: "id [ parameter_value_assignment ]" but allow yaID__aTYPE // // If you follow the rules down, class_type is really a list via ps_class_identifier // // Must propagate scp up for next id class_typeOne { $$=$1; $$=$1; $$=$1; } | class_typeOneListColonIdFollows class_typeOne { $$=$1; $$=$2; $$=$1+$2; } ; class_typeOne: // IEEE: class_type: "id [ parameter_value_assignment ]" but allow yaID__aTYPE // // If you follow the rules down, class_type is really a list via ps_class_identifier // // Not listed in IEEE, but see bug627 any parameter type maybe a class yaID__aTYPE parameter_value_assignmentE { $$=$1; $$=$1; $$=$1; } ; package_scopeIdFollowsE: // IEEE: [package_scope] // // IMPORTANT: The lexer will parse the following ID to be in the found package /* empty */ { $$=""; } | package_scopeIdFollows { $$=$1; $$=$1; } ; package_scopeIdFollows: // IEEE: package_scope // // IMPORTANT: The lexer will parse the following ID to be in the found package // // class_qualifier := [ yLOCAL '::' ] [ implicit_class_handle '.' | class_scope ] // //vv mid rule action needed otherwise we might not have NextId in time to parse the id token yD_UNIT { PARSEP->symTableNextId(PARSEP->syms().netlistSymp()); } /*cont*/ yP_COLONCOLON { $$=$1; $$=$1+$3; } | yaID__aPACKAGE { PARSEP->symTableNextId($1); } /*cont*/ yP_COLONCOLON { $$=$1; $$=$1+$3; } | yLOCAL__COLONCOLON { PARSEP->symTableNextId($1); } /*cont*/ yP_COLONCOLON { $$=$1; $$=$1+$3; } ; //^^^========= class_itemListE: /* empty */ { } | class_itemList { } ; class_itemList: class_item { } | class_itemList class_item { } ; class_item: // ==IEEE: class_item class_property { } | class_method { } | class_constraint { } // | class_declaration { } | timeunits_declaration { } | covergroup_declaration { } | local_parameter_declaration ';' { } // 1800-2009 | parameter_declaration ';' { } // 1800-2009 | ';' { } // | error ';' { } ; class_method: // ==IEEE: class_method memberQualResetListE task_declaration { } | memberQualResetListE function_declaration { } // // 1800-2009 adds yPURE yVIRTUAL, already in memberQualResetListE | yEXTERN memberQualResetListE method_prototype ';' { } // // IEEE: "method_qualifierE class_constructor_declaration" // // part of function_declaration | yEXTERN memberQualResetListE class_constructor_prototype { } ; // IEEE: class_constructor_prototype // See function_declaration class_item_qualifier: // IEEE: class_item_qualifier minus ySTATIC // // IMPORTANT: yPROTECTED | yLOCAL is in a lex rule yPROTECTED { $$=$1; $$=$1; } | yLOCAL__ETC { $$=$1; $$=$1; } | ySTATIC__ETC { $$=$1; $$=$1; } ; memberQualResetListE: // Called from class_property for all qualifiers before yVAR // // Also before method declarations, to prevent grammar conflict // // Thus both types of qualifiers (method/property) are here /*empty*/ { VARRESET(); VARDTYPE(""); } | memberQualList { VARRESET(); VARDTYPE($1); } ; memberQualList: memberQualOne { $$=$1; $$=$1; } | memberQualList memberQualOne { $$=$1; $$=SPACED($1,$2); } ; memberQualOne: // IEEE: property_qualifier + method_qualifier // // Part of method_qualifier and property_qualifier class_item_qualifier { $$=$1; $$=$1; } // // Part of method_qualifier only | yVIRTUAL__ETC { $$=$1; $$=$1; } // // IMPORTANT: lexer looks for yPURE yVIRTUAL | yPURE yVIRTUAL__ETC { $$=$1; $$=$1+" "+$2; } // // Part of property_qualifier only | random_qualifier { $$=$1; $$=$1; } // // Part of lifetime, but here as ySTATIC can be in different positions | yAUTOMATIC { $$=$1; $$=$1; } // // Part of data_declaration, but not in data_declarationVarFrontClass | yCONST__ETC { $$=$1; $$=$1; } ; //********************************************************************** // Constraints class_constraint: // ==IEEE: class_constraint // // IEEE: constraint_declaration constraintStaticE yCONSTRAINT idAny constraint_block { } // // IEEE: constraint_prototype + constraint_prototype_qualifier | constraintStaticE yCONSTRAINT idAny ';' { } | yEXTERN constraintStaticE yCONSTRAINT idAny ';' { } | yPURE constraintStaticE yCONSTRAINT idAny ';' { } ; constraint_block: // ==IEEE: constraint_block '{' constraint_block_itemList '}' { } ; constraint_block_itemList: // IEEE: { constraint_block_item } constraint_block_item { } | constraint_block_itemList constraint_block_item { } ; constraint_block_item: // ==IEEE: constraint_block_item ySOLVE solve_before_list yBEFORE solve_before_list ';' { } | constraint_expression { } ; solve_before_list: // ==IEEE: solve_before_list constraint_primary { } | solve_before_list ',' constraint_primary { } ; constraint_primary: // ==IEEE: constraint_primary // // exprScope more general than: [ implicit_class_handle '.' | class_scope ] hierarchical_identifier select exprScope { } ; constraint_expressionList: // ==IEEE: { constraint_expression } constraint_expression { $$=$1; } | constraint_expressionList constraint_expression { $$=$1+" "+$2; } ; constraint_expression: // ==IEEE: constraint_expression expr/*expression_or_dist*/ ';' { $$=$1; } // // 1800-2012: | ySOFT expr/*expression_or_dist*/ ';' { $$="soft "+$1; } // // 1800-2012: // // IEEE: uniqueness_constraint ';' | yUNIQUE '{' open_range_list '}' { $$="unique {...}"; } // // IEEE: expr yP_MINUSGT constraint_set // // Conflicts with expr:"expr yP_MINUSGT expr"; rule moved there // | yIF '(' expr ')' constraint_set %prec prLOWER_THAN_ELSE { $$=$1; } | yIF '(' expr ')' constraint_set yELSE constraint_set { $$=$1;} // // IEEE says array_identifier here, but dotted accepted in VMM + 1800-2009 | yFOREACH '(' idClassForeach/*array_id[loop_variables]*/ ')' constraint_set { $$=$1; } // // soft is 1800-2012 | yDISABLE ySOFT expr/*constraint_primary*/ ';' { $$="disable soft "+$1; } ; constraint_set: // ==IEEE: constraint_set constraint_expression { $$=$1; } | '{' constraint_expressionList '}' { $$=$1+$2+$3; } ; dist_list: // ==IEEE: dist_list dist_item { } | dist_list ',' dist_item { } ; dist_item: // ==IEEE: dist_item + dist_weight value_range { } | value_range yP_COLONEQ expr { } | value_range yP_COLONDIV expr { } ; extern_constraint_declaration: // ==IEEE: extern_constraint_declaration constraintStaticE yCONSTRAINT class_scope_id constraint_block { } ; constraintStaticE: // IEEE: part of extern_constraint_declaration /* empty */ { } | ySTATIC__CONSTRAINT { } ; //********************************************************************** %% int VParseGrammar::parse() { s_grammarp = this; return VParseBisonparse(); } void VParseGrammar::debug(int level) { VParseBisondebug = level; } const char* VParseGrammar::tokenName(int token) { #if YYDEBUG || YYERROR_VERBOSE if (token >= 255) { switch (token) { /*BISONPRE_TOKEN_NAMES*/ default: return yytname[token-255]; } } else { static char ch[2]; ch[0]=token; ch[1]='\0'; return ch; } #else return ""; #endif } //YACC = /kits/sources/bison-2.4.1/src/bison --report=lookahead // --report=lookahead // --report=itemset // --graph // // Local Variables: // compile-command: "cd .. ; make -j 8 && make test" // End: Verilog-Perl-3.482/Parser/Parser.pm0000644000177100017500000003654414553624343017067 0ustar wsnyderwsnyder# Verilog - Verilog Perl Interface # See copyright, etc in below POD section. ###################################################################### package Verilog::Parser; use Carp; use Verilog::Getopt; use Verilog::Language; use Verilog::Std; require DynaLoader; use base qw(DynaLoader); use strict; use vars qw($VERSION $Debug); $VERSION = '3.482'; #$Debug sets the default value for debug. You're better off with the object method though. our @_Callback_Names = qw( attribute endparse keyword number operator preproc string symbol ); ###################################################################### #### Configuration Section bootstrap Verilog::Parser; #In Parser.xs: # sub _new (class, sigparser) # sub _open (class) # sub _debug (class, level) # sub _prologe (class, flag) # sub _callback_master_enable # sub _use_cb (class, name, flag) # sub parse (class) # sub eof (class) # sub filename (class, [setit]) # sub lineno (class, [setit]) # sub unreadback (class, [setit]) # sub unreadbackCat (class, add) ###################################################################### #### Constructors sub new { my $class = shift; $class = ref $class if ref $class; my $self = {_sigparser=>0, symbol_table=>[], # .xs will init further for us use_vars => 1, use_unreadback => 1, # Backward compatibility use_protected => 1, # Backward compatibility use_pinselects => 0, # Backward compatibility use_std => undef, # Undef = silent #use_cb_{callback-name} => 0/1 # #_debug # Don't set, use debug() accessor to change level @_}; bless $self, $class; # Sets $self->{_cthis} $self->_new($self, # Options go here $self->{symbol_table}, $self->{_sigparser}, $self->{use_unreadback}, $self->{use_protected}, $self->{use_pinselects}, # Undocumented as for use in SigParser only ); $self->{use_cb_contassign} = $self->{use_vars} if !exists $self->{use_cb_contassign}; $self->{use_cb_defparam} = $self->{use_vars} if !exists $self->{use_cb_defparam}; $self->{use_cb_pin} = $self->{use_vars} if !exists $self->{use_cb_pin}; $self->{use_cb_port} = $self->{use_vars} if !exists $self->{use_cb_port}; $self->{use_cb_var} = $self->{use_vars} if !exists $self->{use_cb_var}; foreach my $key (keys %{$self}) { if ($key =~ /^use_cb_(.*)/) { $self->_use_cb($1, $self->{$key}); } } $self->language(Verilog::Language::language_standard()); $self->debug($Debug) if $Debug; return $self; } sub DESTROY { my $self = shift; $self->_DESTROY; } ###################################################################### #### Accessors sub callback_names { my @out = sort @_Callback_Names; return @out; } sub debug { my $self = shift; my $level = shift; if (defined $level) { $self->{_debug} = $level; $self->_debug($level); } return $self->{_debug}; } sub fileline { my $self = shift; return ($self->filename||"").":".($self->lineno||""); } sub line { return lineno(@_); } # Old, now undocumented ####################################################################### #### Methods sub reset { my $self = shift; $self->std; } sub std { my $self = shift; my $quiet = !defined $self->{use_std} && $self->{_sigparser}; if (!$self->{symbol_table}[2]->{std} # Not in the symbol table yet && ($self->{use_std} || $quiet) ) { print "Including std::\n" if $self->{_debug}; my $olddbg = $self->debug; if ($quiet) { print "Disabling debug during std:: loading\n" if $self->{_debug}; $self->debug(0); $self->_callback_master_enable(0); # //verilog-perl callbacks off } $self->eof; #Flush user code before callback disable $self->parse(Verilog::Std::std); $self->eof; if ($quiet) { $self->_callback_master_enable(1); # //verilog-perl callbacks on $self->debug($olddbg); } } } sub parse_file { # Read a file and parse @_ == 2 or croak 'usage: $parser->parse_file($filename)'; my $self = shift; my $filename = shift; my $fh = new IO::File; $fh->open($filename) or croak "%Error: $! $filename"; $self->reset(); $self->filename($filename); $self->lineno(1); while (defined(my $line = $fh->getline())) { $self->parse($line); } $self->eof; $fh->close; return $self; } sub parse_preproc_file { # Read a preprocess file and parse @_ == 2 or croak 'usage: $parser->parse_file(Verilog::Preproc_object_ref)'; my $self = shift; my $pp = shift; ref($pp) or croak "%Error: not passed a Verilog::Preproc object"; $self->reset(); # Chunk size of ~32K determined experimentally with t/49_largeish.t while (defined(my $text = $pp->getall(31*1024))) { $self->parse($text); } $self->eof; return $self; } ###################################################################### #### Called by the parser sub error { my ($self,$text,$token)=@_; my $fileline = $self->filename.":".$self->lineno; croak("%Error: $fileline: $text\n" ."Stopped"); } sub attribute { # Default Internal callback my $self = shift; # Parser invoked my $token = shift; # What token was parsed $self->unreadbackCat($token); } sub comment { # Default Internal callback my $self = shift; # Parser invoked my $token = shift; # What token was parsed $self->unreadbackCat($token); } sub string { # Default Internal callback my $self = shift; # Parser invoked my $token = shift; # What token was parsed $self->unreadbackCat($token); } sub keyword { # Default Internal callback my $self = shift; # Parser invoked my $token = shift; # What token was parsed $self->unreadbackCat($token); } sub symbol { # Default Internal callback my $self = shift; # Parser invoked my $token = shift; # What token was parsed $self->unreadbackCat($token); } sub operator { # Default Internal callback my $self = shift; # Parser invoked my $token = shift; # What token was parsed $self->unreadbackCat($token); } sub preproc { # Default Internal callback my $self = shift; # Parser invoked my $token = shift; # What token was parsed if (Verilog::Language::is_keyword($token)) { $self->keyword($token); # Do this for backward compatibility with Version 2.* } else { $self->symbol($token); # Do this for backward compatibility with Version 2.* } } sub number { # Default Internal callback my $self = shift; # Parser invoked my $token = shift; # What token was parsed $self->unreadbackCat($token); } sub sysfunc { # Default Internal callback - note the default action my $self = shift; # Parser invoked my $token = shift; # What token was parsed $self->symbol($token); # Do this for backward compatibility with Version 2.* } sub endparse { # Default Internal callback my $self = shift; # Parser invoked my $token = shift; # What token was parsed $self->unreadbackCat($token); } ###################################################################### #### Package return 1; __END__ =pod =head1 NAME Verilog::Parser - Parse Verilog language files =head1 SYNOPSIS use Verilog::Parser; my $parser = new Verilog::Parser; $string = $parser->unreadback(); $line = $parser->lineno(); $parser->parse($text) $parser->parse_file($filename) =head1 DESCRIPTION Verilog::Parser will tokenize a Verilog file when the parse() method is called and invoke various callback methods. This is useful for extracting information and editing files while retaining all context. For netlist like extractions, see L. See the "Which Package" section of L if you are unsure which parsing package to use for a new application. Note the parser allows some constructs that are syntax errors according to the specification (for example "foo.bar(1)++".) This is done when the parser can't easily detect these cases. It's up to the consumer of the parser to filter out such errors if it cares. =head1 METHODS =over 4 =item $parser = Verilog::Parser->new (args...) Create a new Parser. Adding "symbol_table => []" will use the specified symbol table for this parse, and modify the array reference to include those symbols detected by this parse. As the SystemVerilog language requires packages and typedefs to exist before they are referenced, you must pass the same symbol_table to subsequent parses that are for the same compilation scope. The internals of this symbol_table should be considered opaque, as it will change between package versions, and must not be modified by user code. Adding "use_cb_{callback-name} => 0" will disable the specified callback. By default, all callbacks will be called; disabling callbacks can greatly speed up the parser as a large percentage of time is spent calling between C and Perl to invoke the callbacks. When using this feature, use_unreadback=>0 should be used too, as since whole tokens are skipped, skipping whitespace shouldn't matter either. Adding "use_protected => 0" will disable callbacks on `protected and "`pragma protect protected" regions, which may improve performance. Adding "use_std => 1" will add parsing of the SystemVerilog built-in std:: package, or "use_std => 0" will disable it. If unspecified it is silently included (no callbacks will be involved) when suspected to be necessary. Adding "use_unreadback => 0" will disable later use of the unreadback method, which may improve performance. Adding "use_vars => 0" will disable contassign, defparam, pin, var and port callbacks to Verilog::SigParser. This can greatly speed parsing when variable and interconnect information is not required. =item $parser->callback_names() Return an array of callback function names. This may be used to automatically create callbacks for all functions, or to test for different callback functionality between versions of Verilog-Perl. =item $parser->eof() Indicate the end of the input stream. All incomplete tokens will be parsed and all remaining callbacks completed. =item $parser->filename($set) Return (if $set is undefined) or set current filename. =item $parser->lineno($set) Return (if $set is undefined) or set current line number. =item $parser->parse($string) Parse the $string as verilog text. Can be called multiple times. Note not all callbacks may be invoked until the eof method is called. =item $parser->parse_file($filename); This method can be called to parse text from a file. The argument can be a filename or an already opened file handle. The return value from parse_file() is a reference to the parser object. =item $parser->parse_preproc_file($preproc); This method can be called to parse preprocessed text from a predeclared Verilog::Preproc object. =item $parser->unreadback($string) Return any input string from the file that has not been sent to the callback. This will include whitespace and tokens which did not have a callback. (For example comments, if there is no comment callback.) This is useful for recording the entire contents of the input, for preprocessors, pretty-printers, and such. With the optional argument, set the text to be returned with the next unreadback call. See also unreadbackCat, which is much faster. To use this option, "use_unreadback => 1" must have been passed to the constructor. =item $parser->unreadbackCat($text) Add text to be returned with the next unreadback call. This is much faster than using "$parser->unreadback($parser->unreadback . $text)". =back =head1 CALLBACKS In order to make the parser do anything interesting, you must make a subclass where you override one or more of the following callback methods as appropriate. =over 4 =item $self->attribute($token) This method is called when any text in (* *) are recognized. The first argument, $token, is the contents of the attribute including the delimiters. =item $self->comment($token) This method is called when any text in // or /**/ comments are recognized. The first argument, $token, is the contents of the comment including the comment delimiters. =item $self->endparse($token) This method is called when the file has been completely parsed, at the End-Of-File of the parsed file. It is useful for writing clean up routines. =item $self->keyword($token) This method is called when any Verilog keyword is recognized. The first argument, $token, is the keyword. =item $self->number($token) This method is called when any number is recognized. The first argument, $token, is the number. The Verilog::Language::number_value function may be useful for converting a Verilog value to a Perl integer. =item $self->operator($token) This method is called when any symbolic operator (+, -, etc) is recognized. The first argument, $token, is the operator. =item $self->preproc($token) This method is called when any Verilog preprocessor `command is recognized. Most of these are handled by the preprocessor, however any unrecognized `defines are passed through. For backward compatibility, if not defined this function will call the symbol callback. =item $self->string($token) This method is called when any text in double quotes are recognized, or on the text of protected regions. The first argument, $token, is the contents of the string including the quotes. =item $self->symbol($token) This method is called when any Verilog symbol is recognized. A symbol is considered a non-keyword bare-word. The first argument, $token, is the symbol. =item $self->sysfunc($token) This method is called when any Verilog $syscall is recognized. The first argument, $token, is the symbol. For backward compatibility, if not defined this function will call the symbol callback. =back =head1 EXAMPLE Here's a simple example which will print every symbol in a verilog file. package MyParser; use Verilog::Parser; @ISA = qw(Verilog::Parser); # parse, parse_file, etc are inherited from Verilog::Parser sub new { my $class = shift; #print "Class $class\n"; my $self = $class->SUPER::new(); bless $self, $class; return $self; } sub symbol { my $self = shift; my $token = shift; $self->{symbols}{$token}++; } sub report { my $self = shift; foreach my $sym (sort keys %{$self->{symbols}}) { printf "Symbol %-30s occurs %4d times\n", $sym, $self->{symbols}{$sym}; } } package main; my $parser = MyParser->new(); $parser->parse_file(shift); $parser->report(); =head1 BUGS This is being distributed as a baseline for future contributions. Don't expect a lot, the Parser is still naive, and there are many awkward cases that aren't covered. The parser currently assumes the string it is passed ends on a newline boundary. It should be changed to allow arbitrary chunks. Cell instantiations without any arguments are not supported, an empty set of parenthesis are required. (Use "cell cell();", not "cell cell;".) =head1 DISTRIBUTION Verilog-Perl is part of the L free Verilog EDA software tool suite. The latest version is available from CPAN and from L. Copyright 2000-2024 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. =head1 AUTHORS Wilson Snyder =head1 SEE ALSO L, L, L, L, L, L, L, L L =cut Verilog-Perl-3.482/Parser/SigParser.pm0000644000177100017500000003325514553624343017526 0ustar wsnyderwsnyder# Verilog::SigParser.pm -- Verilog signal parsing # See copyright, etc in below POD section. ###################################################################### package Verilog::SigParser; require 5.000; use strict; use vars qw($VERSION $Debug); use Carp; use Verilog::Parser; use base qw(Verilog::Parser); ###################################################################### #### Configuration Section $VERSION = '3.482'; our @_Callback_Names = qw( attribute class contassign covergroup defparam endcell endclass endgroup endinterface endmodport endmodule endpackage endprogram endtaskfunc function import instant interface modport module package parampin pin pinselects port program task var ); ####################################################################### # parse, parse_file, etc are inherited from Verilog::Parser sub new { my $class = shift; my $self = $class->SUPER::new(_sigparser => 1, use_unreadback => 0, use_protected => 0, use_pinselects => 0, @_); bless $self, $class; $self->debug($Debug) if $Debug; $self->{metacomment} = {} unless defined $self->{metacomment}; return $self; } sub metacomment { my $self = shift; return $self->{metacomment}; } ####################################################################### # Accessors sub callback_names { my @out = sort @_Callback_Names; return @out; } ####################################################################### # Parser callbacks - backward compatibility sub comment { my $self = shift; my $text = shift; # Includes comment delimiters if ($text =~ m!^(/.)\s* ([\$A-Za-z]\w*)\s+ (\w+) !x) { my ($delim, $category, $name) = ($1, $2, $3); if ($self->{metacomment}->{$category}) { print "GotaMeta $category $name\n" if ($Debug); if ($delim eq "/*") { $text =~ s!\s*\*/$!!; } else { $text =~ s!\s+$!!; } $text =~ s!^/.\s*!!; $self->attribute( $text ); } } $self->SUPER::comment($text); } ####################################################################### # Null callbacks # The my's aren't needed since we do nothing, but are useful if the # user copies them from here to their program. sub contassign { my $self = shift; my $lhs = shift; my $rhs = shift; } sub class { my $self = shift; my $keyword = shift; my $name = shift; my $virtual = shift; } sub covergroup { my $self = shift; my $keyword = shift; my $name = shift; } sub defparam { my $self = shift; my $lhs = shift; my $rhs = shift; } sub endclass { my $self = shift; } sub endcell { my $self = shift; } sub endgroup { my $self = shift; } sub endinterface { my $self = shift; } sub endmodport { my $self = shift; } sub endtaskfunc { my $self = shift; } sub endmodule { my $self = shift; } sub endpackage { my $self = shift; } sub endprogram { my $self = shift; } sub function { my $self = shift; my $keyword = shift; my $name = shift; my $data_type = shift; } sub import { my $self = shift; my $module = shift; my $name = shift; } sub instant { my $self = shift; my $module = shift; my $cell = shift; my $range = shift; } sub interface { my $self = shift; my $keyword = shift; my $name = shift; } sub modport { my $self = shift; my $keyword = shift; my $name = shift; } sub module { my $self = shift; my $keyword = shift; my $name = shift; shift; # Ignored my $in_celldefine = shift; } sub pin { my $self = shift; my $name = shift; my $conn = shift; my $number = shift; } sub pinselects { my $self = shift; my $name = shift; my $conns = shift; my $number = shift; } sub package { my $self = shift; my $kwd = shift; my $name = shift; } sub parampin { my $self = shift; my $name = shift; my $conn = shift; my $number = shift; } sub port { my $self = shift; my $name = shift; my $objof = shift; my $direction = shift; my $data_type = shift; my $array = shift; my $pinnum = shift; } sub program { my $self = shift; my $kwd = shift; my $name = shift; } sub task { my $self = shift; my $keyword = shift; my $name = shift; } sub var { my $self = shift; my $keyword = shift; my $name = shift; my $objof = shift; my $net_type = shift; my $data_type = shift; my $array = shift; my $value = shift; } ###################################################################### ### Package return 1; __END__ =pod =head1 NAME Verilog::SigParser - Signal Parsing for Verilog language files =head1 SYNOPSIS use Verilog::Preproc; use Verilog::SigParser; my $pp = Verilog::Preproc->new(keep_comments=>0,); my $parser = new Verilog::SigParser; $parser->parse_preproc_file($pp); # The below described callbacks are then invoked =head1 DESCRIPTION Verilog::SigParser builds upon the Verilog::Parser module to provide callbacks for when a signal is declared, a module instantiated, or a module defined. See the "Which Package" section of L if you are unsure which parsing package to use for a new application. For a higher level interface to this package, see L. =head1 METHODS The method interface to Verilog::SigParser is described in the Verilog::Parser module which this package inherits. You will probably want to use the preprocessing option of Verilog::Parser with this package. =head1 CALLBACKS In order to make the parser do anything interesting, you must make a subclass where you override one or more of the following methods as appropriate. Note Verilog::Parser callbacks also are invoked when SigParser is parsing. =over 4 =item $self->attribute($text) Scanned an attribute or meta-comment. The parser inspects the first word of each comment line (C to end of line) or comment block (Cattribute( meta_text )> if the first word has a true value in hash C<$self->metacomment>. =item $self->class($token, $name, $virtual) This method is called at a class. =item $self->covergroup($token, $name) This method is called at a covergroup. =item $self->contassign($token, $lhs, $rhs) This method is called at a continuous "assign" keyword, with the left and right hand part of the assignment. Note that "wire" initializations are not considered assignments; those are received via the var callback's value parameter. =item $self->defparam($token, $lhs, $rhs) This method is called at a "defparam" keyword, with the left and right hand part of the assignment. =item $self->endcell($token) This method is called at the end of defining a cell. It is useful for writing clean up routines. =item $self->endgroup($token) This method is called at the end of defining a covergroup. It is useful for writing clean up routines. =item $self->endinterface($token) This method is called at a endinterface keyword. It is useful for writing clean up routines. =item $self->endclass($token) This method is called at a endclass keyword. It is useful for writing clean up routines. =item $self->endtaskfunc($token) This method is called at a endfunction or endtask keyword. It is useful for writing clean up routines. =item $self->endmodport($token) This method is called at a endmodport keyword. It is useful for writing clean up routines. =item $self->endmodule($token) This method is called at a endmodule keyword. It is useful for writing clean up routines. =item $self->endpackage($token) This method is called at a endpackage keyword. It is useful for writing clean up routines. =item $self->endprogram($token) This method is called at a endprogram keyword. It is useful for writing clean up routines. =item $self->function($keyword, $name, $data-type) This method is called when a function is defined. Type is the output size or typename, plus "signed", for example "", "[3:0]", "integer", or "signed [2:0]". =item $self->import($package, $id) This method is called when an import is defined. =item $self->instant($module, $cell, $range) This method is called when a instantiation is defined. The first parameter is the name of the module being instantiated. The second parameter is the name of the cell, which may be "" for primitives. The third is the range if the cell was arrayed. Prior to version 3.000, the name of the parameters were also included in this callback. This has been replaced with the parampin callback. =item $self->interface($keyword, $name) This method is called when an interface is defined. =item $self->modport($keyword, $name) This method is called when an interface modport is defined. =item $self->module($keyword, $name, ignored, $in_celldefine) This method is called when a module is defined. =item $self->package($keyword, $name) This method is called when a package is defined. =item $self->parampin($name, $connection, $index) This method is called when a parameter is connected to an instantiation, IE the "#(...)" syntax. It is also used for UDP delays (Three calls for "#(delay0,delay1,delay2)"), as the parser does not know if the instantiation is for an UDP versus a module. =item $self->pin($name, $connection, $index) This method is called when a pin on an instant is defined and "use_pinselects" is not set (the default, see pinselects() below. If a pin name was not provided and the connection is by position, name will be '' or undef. If you do not need the pin nor var nor port callbacks, consider the "$self->new (... use_vars=>0 ...)" option to accelerate parsing. =item $self->pinselects($name, $connections, $index) If "$self->new (... use_pinselects=>1 ...)" is used this function is called instead of "$self->pin (...)". The difference is that the second parameter ("$connections") is a Perl hash that contains all connected nets in the case of concatenations including the MSB and LSB bounds used at these locations. =item $self->port($name, $objof, $direction, $data_type, $array, $pinnum) This method is called when a module port is defined. It may be called twice on a port if the 1995 style is used; the first call is made at the port header, the second call at the input/output declaration. The first argument $name, is the name of the port. $objof is what the port is an object of ('module', 'function', etc). $direction is the port direction ('input', 'output', 'inout', 'ref', 'const ref', or 'interface'). $data_type is the data type ('reg', 'user_type_t', 'signed [31:0]', etc, or for interfaces the "{interface_id}.{modport_name}"). $array is the arraying of the port ('[1:0][2:0]', '', etc). $pinnum is set to the pin number for ANSI style declarations, and 0 for Verilog 1995 declarations made outside the port list. If you do not need the pin nor var nor port callbacks, consider the "$self->new (... use_vars=>0 ...)" option to accelerate parsing. =item $self->program($keyword, $name) This method is called when a program is defined. =item $self->signal_decl($keyword, $signame, $vector, $mem, $signed, $value) This method is no longer used, see $self->var. =item $self->task($keyword, $name) This method is called when a task is defined. =item $self->var($kwd, $name, $objof, $nettype, $data_type, $array, $value) This method is called when a variable or net is defined. The first argument $kwd is how it was declared ('port', 'var', 'genvar', 'parameter', 'localparam', 'typedef') or if applicable a net type ('supply0', 'wire', etc). $name is the name of the variable. $objof is what the variable is an object of ('module', 'function', etc). $nettype is the net type if any was defined ('', 'supply0', 'wire', 'tri', etc). $data_type is the data type ('user_type_t', '[31:0] signed', etc). $array is the arraying of the variable which is the text AFTER the variable name ('[1:0][2:0]', '', etc). $value is what the variable was assigned to ('', or expression). Note typedefs are included here, because "parameter type" is both a variable and a type declaration. If you do not need the pin nor var nor port callbacks, consider the "$self->new (... use_vars=>0 ...)" option to accelerate parsing. Below are some example declarations and the callbacks: reg [4:0] vect = 5'b10100; # VAR 'var' 'vect' 'module' '' 'reg [4:0]' '' '5'b10100' wire (weak0, weak1) value = pullval; # VAR 'net' 'value' 'module' 'wire' '' '' 'pullval' reg [1:0] mem [12:2]; # VAR 'var' 'mem' 'module' '' 'reg [1:0]' '[12:2]' '' int n[1:2][1:3] = '{'{0,1,2}, '{3{4}}}; # verilog/parser_sv.v:121: VAR 'var' 'n' 'module' '' 'int' '[1:2][1:3]' ''{'{0,1,2},'{3}}' module ( output logic [SZ-1:0] o_sized ); # VAR 'port' 'o_sized' 'module' '' 'logic [SZ-1:0]' '' '' struct packed signed { bit [7:0] m_b; }; # VAR 'member' 'm_b' 'struct' '' 'bit [7:0]' '' '' =back =head1 BUGS This is being distributed as a baseline for future contributions. Don't expect a lot, the Parser is still naive, and there are many awkward cases that aren't covered. Note the SigParser is focused on extracting signal information. It does NOT extract enough information to derive general interconnect; for example the contents of 'assign' statements are not parsed. =head1 DISTRIBUTION Verilog-Perl is part of the L free Verilog EDA software tool suite. The latest version is available from CPAN and from L. Copyright 2000-2024 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. =head1 AUTHORS Wilson Snyder =head1 SEE ALSO L, L, L, L, L =cut Verilog-Perl-3.482/Parser/VParse.cpp0000644000177100017500000001061014553624300017154 0ustar wsnyderwsnyder// -*- C++ -*- //************************************************************************* // // Copyright 2000-2024 by Wilson Snyder. This program is free software; // you can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. // // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // //************************************************************************* /// \file /// \brief Verilog::Parse: Internal implementation of default preprocessor /// /// Authors: Wilson Snyder /// /// Code available from: https://www.veripool.org/verilog-perl /// //************************************************************************* #include #include #include #include #include #include #include #include #include "VParse.h" #include "VParseLex.h" #include "VParseGrammar.h" #include "VSymTable.h" VParseGrammar* VParseGrammar::s_grammarp = NULL; //************************************************************************* VParse::VParse(VFileLine* filelinep, av* symsp, bool sigParser, bool useUnreadbackFlag, bool useProtected, bool usePinselects) : m_syms(filelinep, symsp) { m_inFilelinep = filelinep; m_sigParser = sigParser; m_useUnreadback = useUnreadbackFlag; m_useProtected = useProtected; m_usePinselects = usePinselects; m_debug = 0; m_lexp = new VParseLex(this); m_grammarp = new VParseGrammar(this); m_eof = false; m_anonNum = 0; m_symTableNextId = NULL; m_callbackMasterEna = true; } VParse::~VParse() { if (m_lexp) { delete m_lexp; m_lexp = NULL; } if (m_grammarp) { delete m_grammarp; m_grammarp = NULL; } } void VParse::debug(int level) { m_debug = level; if (level>5) m_grammarp->debug(level); if (level>5) m_lexp->debug(level); } VFileLine* VParse::inFilelinep() const { return m_inFilelinep; } bool VParse::inCellDefine() const { return m_lexp->m_inCellDefine; } void VParse::language(const char* valuep) { m_lexp->language(valuep); } void VParse::parse(const string& text) { if (debug()>=10) { cout<<"VParse::parse: '"< max_chunk) chunk = max_chunk; m_buffers.push_back(string(text.data()+pos, chunk)); pos += chunk; } } void VParse::setEof() { m_eof = true; if (debug()) { cout<<"VParse::setEof: for "<<(void*)(this)<restart(); if (sigParser()) { // Use the bison parser m_grammarp->parse(); } else { fakeBison(); } // End of parsing callback endparseCb(inFilelinep(),""); if (debug()) { cout<<"VParse::setEof: DONE\n"; } } void VParse::fakeBison() { // Verilog::Parser and we don't care about the syntax, so just Lex. VParseBisonYYSType yylval; while (int tok = lexToBison(&yylval)) { if (tok) {} // Prevent unused on some GCCs } } int VParse::lexToBison(VParseBisonYYSType* yylvalp) { return m_lexp->lexToBison(yylvalp); } size_t VParse::inputToLex(char* buf, size_t max_size) { size_t got = 0; while (got < max_size // Haven't got enough && !m_buffers.empty()) { // And something buffered string front = m_buffers.front(); m_buffers.pop_front(); size_t len = front.length(); if (len > (max_size-got)) { // Front string too big string remainder = front.substr(max_size-got); front = front.substr(0, max_size-got); m_buffers.push_front(remainder); // Put back remainder for next time len = (max_size-got); } strncpy(buf+got, front.c_str(), len); got += len; } if (debug()>=9) { string out = string(buf,got); cout<<" inputToLex got="< #* #* Code available from: https://www.veripool.org/ #* #********************************************************************* #* #* Copyright 2000-2024 by Wilson Snyder. This program is free software; #* you can redistribute it and/or modify it under the terms of either the GNU #* Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. #* #* This program is distributed in the hope that it will be useful, #* but WITHOUT ANY WARRANTY; without even the implied warranty of #* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the #* GNU General Public License for more details. #* #* You should have received a copy of the Perl Artistic License #* along with this module; see the file COPYING. If not, see #* www.cpan.org #* #*********************************************************************** #* Note with C++ XS libraries, the CLASS parameter is implied... #***********************************************************************/ /* Mine: */ #include "VParse.h" #include "VSymTable.h" #include "VAst.h" #include #include /* Perl */ extern "C" { # include "EXTERN.h" # include "perl.h" # include "XSUB.h" } #ifdef open # undef open /* Perl 64 bit on solaris has a nasty hack that redefines open */ #endif // This is a global constant pointer initialized to its own address to // produce a unique address to distinguish hashes (pointers to // struct VParseHashElem) from the strings (character pointers) used by // callbackgen in its variadic parameters for VParserXs::call(). static void *hasharray_param = &hasharray_param; class VFileLineParseXs; #//********************************************************************** #// Parseressor derived classes, so we can override the callbacks to call perl. class VParserXs : public VParse { public: SV* m_self; // Class called from (the hash, not SV pointing to the hash) VFileLine* m_cbFilelinep; ///< Last callback's starting point deque m_filelineps; // CALLBACKGEN_H_MEMBERS // CALLBACKGEN_GENERATED_BEGIN - GENERATED AUTOMATICALLY by callbackgen struct { // Bit packed to help the cache bool m_useCb_attribute:1; bool m_useCb_class:1; bool m_useCb_comment:1; bool m_useCb_contassign:1; bool m_useCb_covergroup:1; bool m_useCb_defparam:1; bool m_useCb_endcell:1; bool m_useCb_endclass:1; bool m_useCb_endgroup:1; bool m_useCb_endinterface:1; bool m_useCb_endmodport:1; bool m_useCb_endmodule:1; bool m_useCb_endpackage:1; bool m_useCb_endparse:1; bool m_useCb_endprogram:1; bool m_useCb_endtaskfunc:1; bool m_useCb_function:1; bool m_useCb_import:1; bool m_useCb_instant:1; bool m_useCb_interface:1; bool m_useCb_keyword:1; bool m_useCb_modport:1; bool m_useCb_module:1; bool m_useCb_number:1; bool m_useCb_operator:1; bool m_useCb_package:1; bool m_useCb_parampin:1; bool m_useCb_pin:1; bool m_useCb_pinselects:1; bool m_useCb_port:1; bool m_useCb_preproc:1; bool m_useCb_program:1; bool m_useCb_string:1; bool m_useCb_symbol:1; bool m_useCb_sysfunc:1; bool m_useCb_task:1; bool m_useCb_var:1; }; // CALLBACKGEN_GENERATED_END - GENERATED AUTOMATICALLY by callbackgen VFileLine* cbFilelinep() const { return m_cbFilelinep; } void cbFileline(VFileLine* filelinep) { m_cbFilelinep = filelinep; } VParserXs(VFileLine* filelinep, av* symsp, bool sigparser, bool useUnreadback, bool useProtected, bool usePinselects) : VParse(filelinep, symsp, sigparser, useUnreadback, useProtected, usePinselects) , m_cbFilelinep(filelinep) { set_cb_use(); } virtual ~VParserXs(); // CALLBACKGEN_CB_USE // CALLBACKGEN_GENERATED_BEGIN - GENERATED AUTOMATICALLY by callbackgen void set_cb_use() { m_useCb_attribute = true; m_useCb_class = true; m_useCb_comment = true; m_useCb_contassign = true; m_useCb_covergroup = true; m_useCb_defparam = true; m_useCb_endcell = true; m_useCb_endclass = true; m_useCb_endgroup = true; m_useCb_endinterface = true; m_useCb_endmodport = true; m_useCb_endmodule = true; m_useCb_endpackage = true; m_useCb_endparse = true; m_useCb_endprogram = true; m_useCb_endtaskfunc = true; m_useCb_function = true; m_useCb_import = true; m_useCb_instant = true; m_useCb_interface = true; m_useCb_keyword = true; m_useCb_modport = true; m_useCb_module = true; m_useCb_number = true; m_useCb_operator = true; m_useCb_package = true; m_useCb_parampin = true; m_useCb_pin = true; m_useCb_pinselects = true; m_useCb_port = true; m_useCb_preproc = true; m_useCb_program = true; m_useCb_string = true; m_useCb_symbol = true; m_useCb_sysfunc = true; m_useCb_task = true; m_useCb_var = true; } // CALLBACKGEN_GENERATED_END - GENERATED AUTOMATICALLY by callbackgen // CALLBACKGEN_H_VIRTUAL // CALLBACKGEN_GENERATED_BEGIN - GENERATED AUTOMATICALLY by callbackgen // Verilog::Parser Callback methods virtual void attributeCb(VFileLine* fl, const string& text); virtual void commentCb(VFileLine* fl, const string& text); virtual void endparseCb(VFileLine* fl, const string& text); virtual void keywordCb(VFileLine* fl, const string& text); virtual void numberCb(VFileLine* fl, const string& text); virtual void operatorCb(VFileLine* fl, const string& text); virtual void preprocCb(VFileLine* fl, const string& text); virtual void stringCb(VFileLine* fl, const string& text); virtual void symbolCb(VFileLine* fl, const string& text); virtual void sysfuncCb(VFileLine* fl, const string& text); // Verilog::SigParser Callback methods virtual void classCb(VFileLine* fl, const string& kwd, const string& name, const string& virt); virtual void contassignCb(VFileLine* fl, const string& kwd, const string& lhs, const string& rhs); virtual void covergroupCb(VFileLine* fl, const string& kwd, const string& name); virtual void defparamCb(VFileLine* fl, const string& kwd, const string& lhs, const string& rhs); virtual void endcellCb(VFileLine* fl, const string& kwd); virtual void endclassCb(VFileLine* fl, const string& kwd); virtual void endgroupCb(VFileLine* fl, const string& kwd); virtual void endinterfaceCb(VFileLine* fl, const string& kwd); virtual void endmodportCb(VFileLine* fl, const string& kwd); virtual void endmoduleCb(VFileLine* fl, const string& kwd); virtual void endpackageCb(VFileLine* fl, const string& kwd); virtual void endprogramCb(VFileLine* fl, const string& kwd); virtual void endtaskfuncCb(VFileLine* fl, const string& kwd); virtual void functionCb(VFileLine* fl, const string& kwd, const string& name, const string& data_type); virtual void importCb(VFileLine* fl, const string& package, const string& id); virtual void instantCb(VFileLine* fl, const string& mod, const string& cell, const string& range); virtual void interfaceCb(VFileLine* fl, const string& kwd, const string& name); virtual void modportCb(VFileLine* fl, const string& kwd, const string& name); virtual void moduleCb(VFileLine* fl, const string& kwd, const string& name, bool, bool celldefine); virtual void packageCb(VFileLine* fl, const string& kwd, const string& name); virtual void parampinCb(VFileLine* fl, const string& name, const string& conn, int index); virtual void pinCb(VFileLine* fl, const string& name, const string& conn, int index); virtual void pinselectsCb(VFileLine* fl, const string& name, unsigned int arraycnt2, unsigned int elemcnt2, const VParseHashElem* conns2, int index); virtual void portCb(VFileLine* fl, const string& name, const string& objof, const string& direction, const string& data_type , const string& array, int index); virtual void programCb(VFileLine* fl, const string& kwd, const string& name); virtual void taskCb(VFileLine* fl, const string& kwd, const string& name); virtual void varCb(VFileLine* fl, const string& kwd, const string& name, const string& objof, const string& net , const string& data_type, const string& array, const string& value); // CALLBACKGEN_GENERATED_END - GENERATED AUTOMATICALLY by callbackgen void useCbEna(const char* name, bool flag); void call(string* rtnStrp, int params, const char* method, ...); }; class VFileLineParseXs : public VFileLine { VParserXs* m_vParserp; // Parser handling the errors public: VFileLineParseXs(VParserXs* pp) : VFileLine(true), m_vParserp(pp) { if (pp) pushFl(); } virtual ~VFileLineParseXs() { } virtual VFileLine* create(const string& filename, int lineno) { VFileLineParseXs* filelp = new VFileLineParseXs(m_vParserp); filelp->init(filename, lineno); return filelp; } virtual void error(const string& msg); // Report a error at given location void setParser(VParserXs* pp) { m_vParserp=pp; pushFl(); // The very first construction used pp=NULL, as pp wasn't created yet so make it now } // Record the structure so we can delete it later void pushFl() { m_vParserp->m_filelineps.push_back(this); } }; #//********************************************************************** #// Overrides error handling virtual functions to invoke callbacks void VFileLineParseXs::error(const string& msg) { static string holdmsg; holdmsg = msg; m_vParserp->cbFileline(this); // Call always, not just if callbacks enabled m_vParserp->call(NULL, 1,"error",holdmsg.c_str()); } #//********************************************************************** #// Overrides of virtual functions to invoke callbacks #include "Parser_callbackgen.cpp" #//********************************************************************** #// VParserXs functions VParserXs::~VParserXs() { for (deque::iterator it=m_filelineps.begin(); it!=m_filelineps.end(); ++it) { delete *it; } } #//********************************************************************** #// General callback invoker void VParserXs::call( string* rtnStrp, /* If non-null, load return value here */ int params, /* Number of parameters */ const char* method, /* Name of method to call */ ...) /* Arguments to pass to method's @_ */ { // Call $perlself->method (passedparam1, parsedparam2) if (debug()) cout << "CALLBACK "< */ XPUSHs(sv_2mortal(selfsv)); while (params--) { char* textp = va_arg(ap, char *); if (textp == hasharray_param) { // First hasharray param defines number of array elements unsigned int arrcnt = va_arg(ap, unsigned int); AV* av = newAV(); av_extend(av, arrcnt); // Second hasharray param defines how many keys are within one hash unsigned int elemcnt = va_arg(ap, unsigned int); // Followed by the hash array pointer... const VParseHashElem* arrp = va_arg(ap, const VParseHashElem*); // [arrcnt][elemcnt] for (unsigned int i = 0; i < arrcnt; i++) { HV* hv = newHV(); const VParseHashElem* elemp = arrp + elemcnt*i; for (unsigned int j = 0; j < elemcnt; j++) { if (!elemp[j].keyp) continue; SV* sv; switch (elemp[j].val_type) { case VParseHashElem::ELEM_INT: sv = newSViv(elemp[j].val_int); break; case VParseHashElem::ELEM_STR: default: sv = newSVpv(elemp[j].val_str.c_str(), 0); break; } hv_store(hv, elemp[j].keyp, strlen(elemp[j].keyp), sv, 0); } av_store(av, i, newRV_noinc((SV*)hv)); elemp++; } XPUSHs(sv_2mortal(newRV_noinc((SV*)av))); } else if (textp) { // Non hasharray_param, so is text XPUSHs(sv_2mortal(newSVpv(textp, 0))); } else { XPUSHs(&PL_sv_undef); } } PUTBACK; /* make local stack pointer global */ if (rtnStrp) { int rtnCount = perl_call_method((char*)method, G_SCALAR); SPAGAIN; /* refresh stack pointer */ if (rtnCount > 0) { SV* sv = POPs; //printf("RTN %ld %d %s\n", SvTYPE(sv),SvTRUE(sv),SvPV_nolen(sv)); #ifdef SvPV_nolen // Perl 5.6 and later *rtnStrp = SvPV_nolen(sv); #else *rtnStrp = SvPV(sv,PL_na); #endif } PUTBACK; } else { perl_call_method((char*)method, G_DISCARD | G_VOID); } FREETMPS; /* free that return value */ LEAVE; /* ...and the XPUSHed "mortal" args.*/ } va_end(ap); } #//********************************************************************** MODULE = Verilog::Parser PACKAGE = Verilog::Parser #//********************************************************************** #// self->_new (class, sigparser) static VParserXs * VParserXs::_new(SV* SELF, AV* symsp, bool sigparser, bool useUnreadback, bool useProtected, bool usePinselects) PROTOTYPE: $$$$ CODE: { if (CLASS) {} /* Prevent unused warning */ if (!SvROK(SELF)) { warn("${Package}::$func_name() -- SELF is not a hash reference"); } VFileLineParseXs* filelinep = new VFileLineParseXs(NULL/*ok,for initial*/); VParserXs* parserp = new VParserXs(filelinep, symsp, sigparser, useUnreadback, useProtected, usePinselects); filelinep->setParser(parserp); parserp->m_self = SvRV(SELF); RETVAL = parserp; } OUTPUT: RETVAL #//********************************************************************** #// self->_DESTROY() void VParserXs::_DESTROY() PROTOTYPE: $ CODE: { delete THIS; } #//********************************************************************** #// self->debug(level) void VParserXs::_debug(level) int level PROTOTYPE: $$ CODE: { THIS->debug(level); VAstEnt::debug(level); } #//********************************************************************** #// self->_callback_master_enable(flag) #// Turn off callbacks during std:: parsing void VParserXs::_callback_master_enable(flag) bool flag PROTOTYPE: $$ CODE: { THIS->callbackMasterEna(flag); } #//********************************************************************** #// self->_use_cb(name,flag) #// Turn off specified callback void VParserXs::_use_cb(const char* name, bool flag) PROTOTYPE: $$$ CODE: { THIS->useCbEna(name,flag); } #//********************************************************************** #// self->eof() void VParserXs::eof() PROTOTYPE: $ CODE: { THIS->setEof(); } #//********************************************************************** #// self->filename([setit]) SV* VParserXs::filename(const char* flagp="") PROTOTYPE: $;$ CODE: { if (!THIS) XSRETURN_UNDEF; if (items > 1) { THIS->inFileline(flagp, THIS->inFilelinep()->lineno()); THIS->cbFileline(THIS->inFilelinep()); } string ret = THIS->cbFilelinep()->filename(); RETVAL = newSVpv(ret.c_str(), ret.length()); } OUTPUT: RETVAL #//********************************************************************** #// self->language() void VParserXs::language(valuep) const char* valuep PROTOTYPE: $$ CODE: { if (items > 1) { THIS->language(valuep); } } #//********************************************************************** #// self->lineno([setit]) int VParserXs::lineno(int flag=0) PROTOTYPE: $;$ CODE: { if (!THIS) XSRETURN_UNDEF; if (items > 1) { THIS->inFileline(THIS->inFilelinep()->filename(), flag); THIS->cbFileline(THIS->inFilelinep()); } RETVAL = (THIS->cbFilelinep()->lineno()); } OUTPUT: RETVAL #//********************************************************************** #// self->parse() void VParserXs::parse(const char* textp) PROTOTYPE: $$ CODE: { THIS->parse(textp); } #//********************************************************************** #// self->selftest() void VParserXs::selftest() PROTOTYPE: $ CODE: { VSymStack::selftest(); assert(VParse::isKeyword("wire",strlen("wire"))); assert(!VParse::isKeyword("wire99",strlen("wide99"))); } #//********************************************************************** #// self->unreadback() SV* VParserXs::unreadback(const char* flagp="") PROTOTYPE: $;$ CODE: { if (!THIS) XSRETURN_UNDEF; // Set RETVAL to a SV before we replace with the new value, and c_str may change string ret = THIS->unreadback(); RETVAL = newSVpv(ret.c_str(), ret.length()); if (items > 1) { THIS->unreadback(flagp); } } OUTPUT: RETVAL #//********************************************************************** #// self->unreadbackCat() void VParserXs::unreadbackCat(SV* textsvp) PROTOTYPE: $$ CODE: { if (!THIS) XSRETURN_UNDEF; STRLEN textlen; const char* textp = SvPV(textsvp, textlen); THIS->unreadbackCat(textp, textlen); } Verilog-Perl-3.482/Parser/VSymTable.h0000644000177100017500000001023314553624300017270 0ustar wsnyderwsnyder// -*- C++ -*- //************************************************************************* // // Copyright 2009-2024 by Wilson Snyder. This program is free software; // you can redistribute it and/or modify it under the terms of either the // GNU Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // //************************************************************************* /// \file /// \brief Verilog::Parse: Symbol table accessing /// /// Authors: Wilson Snyder /// /// Code available from: https://www.veripool.org/verilog-perl /// //************************************************************************* #ifndef _VSYMTABLE_H_ #define _VSYMTABLE_H_ 1 #include "VFileLine.h" #include "VAst.h" #include #include using namespace std; //###################################################################### // List of symbol tables class VSymStack { typedef vector SymStack; SymStack m_sympStack; // Stack of symbol tables VAstEnt* m_currentSymp; // Current symbol table public: // CONSTRUCTORS VSymStack(VFileLine* fl, struct av* symp); // Pass in top-level symbol table array ~VSymStack() {} // ACCESSORS VAstEnt* currentSymp() const { return m_currentSymp; } VAstEnt* netlistSymp() const { return m_sympStack.front(); } // METHODS /// Insert a new entry, and return the new entry VAstEnt* replaceInsert(VAstType type, const string& name) { return m_currentSymp->replaceInsert(type,name); } /// Insert an entry if it doesn't exist VAstEnt* findInsert(VAstType type, const string& name) { return m_currentSymp->findInsert(type,name); } /// Return type of current lookup VAstType curType() { return m_currentSymp->type(); } void showUpward() { cout<<"SymTable Stack:\n"; for (SymStack::reverse_iterator it=m_sympStack.rbegin(); it!=m_sympStack.rend(); ++it) { VAstEnt* symp = *it; cout<<"\t"<ascii()<parentp()) { cout<<"\t"<ascii()<findSym VAstEnt* findEntUpward(const string& name) { for (VAstEnt* symp=currentSymp(); symp; symp=symp->parentp()) { if (VAstEnt* subp = symp->findSym(name)) { return subp; } } return NULL; } VAstType findTypeUpward(const string& name) { if (VAstEnt* subp = findEntUpward(name)) { return subp->type(); } else { return VAstType::NOT_FOUND; } } /// Return what this object is a member of, ignoring blocks string objofUpward() { for (VAstEnt* symp=currentSymp(); symp; symp=symp->parentp()) { if (!symp->typeIgnoreObjof()) { return symp->type().ascii(); } } assert(0); // Should have been a NETLIST if nothing else return ""; // Asserts maybe NOPed } /// Push current scope down to a new scope void pushScope(VAstEnt* symp) { m_sympStack.push_back(symp); m_currentSymp = symp; } /// Pop current scope up to a previous scope void popScope(VFileLine* fl) { m_sympStack.pop_back(); // Must always have one remaining - it's globals. Thus this is after the pop. if (m_sympStack.empty()) { fl->error("symbol stack underflow"); return; } m_currentSymp = m_sympStack.back(); } /// Import from package::id_or_star to this void import(VFileLine* fl, const string& pkg, const string& id_or_star) { import(fl, pkg, findEntUpward(pkg), id_or_star); } void import(VFileLine* fl, const string& pkg, VAstEnt* entp, const string& id_or_star) { if (!entp) { // Internal problem, because we earlier found pkg to label it an ID__aPACKAGE fl->error("Internal: Import package not found: "+pkg); return; } m_currentSymp->import(entp, id_or_star); } static void selftest(); }; #endif // guard Verilog-Perl-3.482/Parser/bisonpre0000755000177100017500000004041714553624343017036 0ustar wsnyderwsnyder#!/usr/bin/perl -w # See copyright, etc in below POD section. ###################################################################### require 5.006_001; use Getopt::Long; use IO::File; use Pod::Usage; use strict; use vars qw($Debug $VERSION); $VERSION = '3.482'; our $Self; #====================================================================== # main our $Opt_Debug; our $Opt_Definitions; our $Opt_File_Prefix; our $Opt_Name_Prefix; our $Opt_Output; our $Opt_Token_Table; our $Opt_Verbose; our $Opt_Yacc = "bison"; our $Opt_Input; autoflush STDOUT 1; autoflush STDERR 1; Getopt::Long::config("no_auto_abbrev"); if (! GetOptions ( # Local options "help" => \&usage, "version" => sub { print "Version $VERSION\n"; exit(0); }, "yacc=s" => \$Opt_Yacc, # Passed to Bison "t|debug" => sub { $Opt_Debug = 1; }, "b|file-prefix=s" => \$Opt_File_Prefix, "d" => \$Opt_Definitions, "k|token-table" => \$Opt_Token_Table, "o=s" => \$Opt_Output, "p|name-prefix=s" => \$Opt_Name_Prefix, "v|verbose" => \$Opt_Verbose, "<>" => \¶meter, )) { die "%Error: Bad usage, try 'bisonpre --help'\n"; } $Opt_Input or die "bisonpre: %Error: input file not specified\n"; $Opt_Output or die "bisonpre: %Error: --o option is required\n"; process(); #---------------------------------------------------------------------- sub usage { print "Version $VERSION\n"; pod2usage(-verbose=>2, -exitval=>2, -output=>\*STDOUT, -noperldoc=>1); exit(1); } sub parameter { my $param = shift; if (!defined $Opt_Input) { $Opt_Input = $param; } else { die "bisonpre: %Error: Unknown parameter: $param\n"; } } ####################################################################### sub process { remove_outputs(); $Self->{bison_version} = bison_version_check(); my $supports_report = ($Self->{bison_version} >= 2.3); clean_input($Opt_Input, tmp_prefix().".y"); # Run bison my $command = ($Opt_Yacc .($Opt_Debug?" -t":"") .($Opt_Definitions?" -d":"") .($Opt_Token_Table?" -k":"") .($Opt_Verbose?" -v":"") .(($Opt_Verbose && $supports_report)?" --report=itemset --report=lookahead":"") # -p required for GLR parsers; they write to -p basename, not -o .($Opt_Name_Prefix?" -p $Opt_Name_Prefix":"") ." -b ".tmp_prefix() ." -o ".tmp_prefix().".c" ." ".tmp_prefix().".y" ); print " $command\n"; system $command; my $status = $?; if ($status != 0) { remove_outputs(); my $v = bison_version_check(); die "bisonpre: %Error: $Opt_Yacc version $v run failed due to errors\n"; } clean_output(tmp_prefix().".output",output_prefix().".output", 1,0); warning_check(output_prefix().".output"); clean_output(tmp_prefix().".c", output_prefix().".c", 0,1); clean_output(tmp_prefix().".h", output_prefix().".h", 0,1); remove_tmp(); } sub tmp_prefix { return output_prefix()."_pretmp"; } sub output_prefix { my $o; if ($Opt_Output) { (my $o = $Opt_Output) =~ s!\.[^.]*$!!; return $o; } else { return $Opt_File_Prefix.".tab"; } } sub remove_tmp { unlink(tmp_prefix().".c"); # Ok if errors unlink(tmp_prefix().".h"); # Ok if errors unlink(tmp_prefix().".output"); # Ok if errors } sub remove_outputs { remove_tmp(); unlink(output_prefix().".c"); # Ok if errors unlink(output_prefix().".h"); # Ok if errors # We don't remove .output file, as it's useful for debugging errors } sub bison_version_check { my $v = `$Opt_Yacc --version`; if ($v && $v =~ /([0-9]+\.[0-9]+)/) { my $v = $1; ($v >= 1.875) or die "bisonpre: %Error: '$Opt_Yacc' is version $v; version 1.875 or newer is required\n"; return $v; } else { die "bisonpre: %Error: '$Opt_Yacc' is not installed, or not working\n"; } } sub clean_output { my $filename = shift; my $outname = shift || $filename; my $is_output = shift; my $is_c = shift; print " edit $filename $outname\n"; my $fh = IO::File->new("<$filename") or die "%Error: $! $filename\n"; my @lines = $fh->getlines; $fh->close; (my $basename = tmp_prefix().".") =~ s!.*/!!; $basename = quotemeta($basename); (my $newbase = $Opt_Input) =~ s!.*/!!; $newbase =~ s/\.y/./; if ($is_output) { my %state_line; my $l=0; foreach my $line (@lines) { $l++; # We add a colon so it's easy to search for the definition $state_line{$1} = $l if $line =~ s/^state (\d+)\s*$/state $1:/; } my @out; foreach my $line (@lines) { if ($line =~ /^State (\d+) (conflicts)/) { chomp $line; $line .= " // line $state_line{$1}" if $state_line{$1}; $line .= "\n"; } push @out, $line; } @lines = @out; @out = (); } if ($is_c) { my %token_values; my $in_en=0; foreach my $line (@lines) { $in_en=1 if $line =~ /enum\s+yytokentype/; $in_en=0 if $line =~ /;/; $token_values{$2} = $1 if $in_en && $line =~ /\b(\S+) = (\d+)/; } my @out; foreach my $line (@lines) { if ($line =~ /BISONPRE_TOKEN_NAMES/) { push @out, $line; foreach my $tv (sort keys %token_values) { push @out, sprintf("\tcase %d: return \"%s\";\n", $tv, $token_values{$tv}); } next; } push @out, $line; } @lines = @out; @out = (); } $fh = IO::File->new(">$outname") or die "%Error: $! writing $outname\n"; foreach my $line (@lines) { # Fix filename refs $line =~ s!$basename!$newbase!g; # Fix bison 2.3 and GCC 4.2.1 $line =~ s!\(YY_\("!(YY_((char*)"!g; # Fix bison 2.3 glr-parser warning about yyerrorloc.YYTYPE::yydummy uninit $line =~ s!(YYLTYPE yyerrloc;)!$1 yyerrloc.yydummy=0;/*bisonpre*/!g; $fh->write($line); } $fh->close; } sub warning_check { my $filename = shift; my $fh = IO::File->new("<$filename") or die "%Error: $! $filename\n"; while (defined(my $line = $fh->getline)) { if ($line =~ /(conflicts|warning:|^useless)/i) { die "%Error: $filename:$.: $line\n"; } } $fh->close; } ####################################################################### sub clean_input { my $filename = shift; my $outname = shift || $filename; # Can == filename if desired print " edit $filename $outname\n"; $Self->{filename} = $filename; my $fh = IO::File->new("<$filename") or die "%Error: $! $filename\n"; my @lines = $fh->getlines; $fh->close; # Find "%tokens:" # Find "rule:" and replace with just "rule:" my %types; my %rules; $Self->{rules} = \%rules; my %tokens; my $last_rule; my $section = 1; { my @linesin = @lines; @lines=(); my $l=0; foreach my $line (@linesin) { $l++; # ^/ to prevent comments from matching $line =~ m!^[a-zA-Z0-9_<>]+:[^/]*[a-zA-Z]! and die "%Error: $filename:$l: Move text on rule line to next line: $line\n"; if ($line =~ /^%%/) { $section++; if ($section==2) { $last_rule = undef; } } elsif ($line =~ s/^([a-zA-Z0-9_]+)<(\S*)>:/$1:/) { !$rules{$1}{name} or die "%Error: $filename:$l: Redeclaring '$1': $line\n"; $types{$2}{$1} = 1; $rules{$1}{name} = $1; $rules{$1}{type} = $2; !$last_rule or die "%Error: $filename:$l: Unterminated previous rule\n"; $last_rule = $1; } elsif ($line =~ /^([a-zA-Z0-9_]+):/) { !$rules{$1}{name} or die "%Error: $filename:$l: Redeclaring '$1': $line\n"; $rules{$1}{name} = $1; $rules{$1}{type} = ""; !$last_rule or die "%Error: $filename:$l: Unterminated previous rule\n"; $last_rule = $1; } push @lines, $line; # Now clean the line and extract some more info (my $cline = $line) =~ s/\/\/.*$/\n/; (my $rline = $line) =~ s/\/\/.*$/\n/; if ($cline =~ /^\s*;/) { $last_rule or die "%Error: $filename:$l: Stray semicolon\n"; $last_rule = undef; } elsif ($last_rule) { $rules{$last_rule}{rules_and_productions} .= $cline; } if ($cline =~ /^%token\s*<(\S+)>\s*(\S+)/) { !$tokens{$2} or die "%Error: $filename:$l: Redeclaring '$2': $line\n"; $tokens{$2} = $1; } foreach my $tok (split /[^a-zA-Z0-9_]+/, $cline) { if ($last_rule && $tok=~/^[a-zA-Z]/) { #print "TT $last_rule $tok\n"; $rules{$last_rule}{subrules}{$tok} = 1; $rules{$tok}{parentrules}{$last_rule} = 1; } } } } #use Data::Dumper; print Dumper(\%rules); # Replace BISONPRE_VERSION(ver,,...) with expanded list { my @linesin = @lines; @lines=(); my $l=0; foreach my $line (@linesin) { $l++; if ($line =~ /BISONPRE_VERSION/) { # 1 3 4 ($line =~ /BISONPRE_VERSION\((\S+)\s*,\s*((\S+)\s*,)?\s*([^\),]+)\)\s*$/) or die "%Error: $filename:$l: Bad form of BISONPRE_VERSION: $line\n"; my $ver=$1; my $ver_max=$3; my $cmd=$4; if ($Self->{bison_version} >= $1 && (!$ver_max || $Self->{bison_version} <= $ver_max)) { $line = $cmd."\n"; } else { $line = "//NOP: $line"; } } push @lines, $line; } } # Replace BISONPRE_NOT(type,...) with expanded list { my @linesin = @lines; @lines=(); my $l=0; foreach my $line (@linesin) { $l++; if ($line =~ /BISONPRE_NOT/) { ($line =~ s/BISONPRE_NOT\((\S+)\)\s*(\{[^}]+})\s*$//) or die "%Error: $filename:$l: Bad form of BISONPRE_NOT: $line\n"; my $endtok = $1; my $action = $2; my @endtoks = split(/,/, $endtok); map { $tokens{$_} or die "%Error: $filename:$l: Can't find definition for token: $_\n" } @endtoks; # Push it all onto one line to avoid error messages changing my $bar = ""; tok: foreach my $tok (sort keys %tokens) { foreach (@endtoks) { next tok if $tok eq $_; } if ($endtok ne $tok) { $line .= "\t$bar $tok $action"; $bar = "|"; } } $line .= "\n"; } push @lines, $line; } } # Replace BISONPRE_COPY(type,{code}) { my @linesin = @lines; @lines=(); my $l=0; foreach my $line (@linesin) { $l++; if ($line =~ /BISONPRE_COPY/) { $line = _bisonpre_copy($line,$l,0); } push @lines, $line; } } # Replace ~[x]~ - must be after BISONPRE_COPY expansion { my @linesin = @lines; @lines=(); my $l=0; foreach my $line (@linesin) { $l++; $line =~ s/~[a-zA-Z0-9_]+~//g; push @lines, $line; } } # Find "BISONPRE_TYPES" { my @linesin = @lines; @lines=(); my $l=0; my $needmore = 0; foreach my $line (@linesin) { $l++; if ($line =~ m!//BISONPRE_TYPES!) { push @lines, $line; foreach my $type (sort keys %types) { next if !$type; my $line = "%type<$type>\t"; foreach my $rule (sort keys %{$types{$type}}) { $line.=" ".$rule; } $line .= "\n"; push @lines, $line; $needmore++ } } elsif ($needmore) { # Bison doesn't have a #line directive, so we need somewhere to insert into $line =~ s!^\s*//.*$!!; ($line =~ m/^\s*$/) or die "%Error: $filename:$l: Need $needmore more blank lines to insure line numbers are constant\n"; $needmore--; } else { push @lines, $line; } } } $fh = IO::File->new(">$outname") or die "%Error: $! writing $outname\n"; foreach my $line (@lines) { $fh->write($line); } $fh->close; } sub _bisonpre_copy { my $text = shift; my $l = shift; my $depth = shift; while ($text =~ /BISONPRE_COPY/) { ($text =~ s/BISONPRE_COPY(_ONCE)?\((\S+)\s*,\s*\{([^}]*)}\s*\)/{HERE}/) or die "%Error: $Self->{filename}:$l: Bad form of BISONPRE_NOT: $text\n"; my $once = $1; my $rule = $2; my $code = $3; $Self->{rules}{$rule} or die "%Error: $Self->{filename}:$l: Can't find definition for rule: $rule\n"; if ($depth > 0 && $once) { # _ONCE means don't inherit $text =~ s/\|[ \t]+{HERE}//; # Don't OR in nothing $text =~ s/{HERE}//; } else { # Push it all onto one line to avoid error messages changing my $insert = $Self->{rules}{$rule}{rules_and_productions}; $insert =~ s/^\S+://g; # Strip rule name # Recurse so BISONPRE under B #print "COPY $l code $code\n"; #print "COPY $l in $insert\n"; $_=$insert; eval("$code; \$_;"); $insert = $_; #print "COPY $l out $insert\n"; while ($insert =~ s/[ \t\n]+\n/\n/go) {} while ($insert =~ s/\n/ /go) {} # Optional - preserve line numbering $text =~ s/{HERE}/$insert/; } $depth++; } return $text; } ####################################################################### __END__ =pod =head1 NAME bisonpre - Bison wrapper with pre and post processing =head1 SYNOPSIS bisonpre --yacc bison --debug --verbose --defines X.h -k $< -pX -o X.c =head1 DESCRIPTION Bisonpre is a wrapper for the Bison YACC replacement. Input to Bison is preprocessed with substitution as described below under EXTENSIONS. Output from Bison is checked for additional errors, and corrected to work around various compile warnings. =head1 EXTENSIONS =over 4 =item //BISONPRE_TYPES This is expanded into %type declarations. =item ~[a-z]+~ Any text matching ~[a-z]+~ is removed. This allows optional text to be used only when the rule containing the ~~ is used in a BISONPRE_COPY. =item rule_label: This allows the label declaring a rule to also specify the type of the rule. The type will be inserted where /*BISONPRE_TYPES*/ is encountered. =item BISONPRE_COPY(rule, {code}) Copy the rules and productions from the specified rule, filter through the Perl code provided in the {} and insert here into the output file. =item BISONPRE_COPY_ONCE(rule, {code}) As with BISONPRE_COPY, but if called from underneath another BISONPRE_COPY rule, ignore it. =item BISONPRE_NOT(token[, token...]) Create a rule that matches every token except for those specified. =item BISONPRE_VERSION(ver, cmd) If the bison version is >= the specified version, include the given command. =back =head1 ARGUMENTS =over 4 =item -b file-prefix =item --file-prefix=file-prefix Passed to bison. Specify a prefix to use for all bison output file names. The names are chosen as if the input file were named file-prefix.c. =item -d Passed to bison. Write an extra output file containing macro definitions for the token type names defined in the grammar and the semantic value type YYSTYPE, as well as a few extern variable declarations. If the parser output file is named name.c then this file is named name.h. This output file is essential if you wish to put the definition of yylex in a separate source file, because yylex needs to be able to refer to token type codes and the variable yylval. =item --help Displays this message and program version and exits. =item -k =item --token-table Passed to bison. This switch causes the name.tab.c output to include a list of token names in order by their token numbers; this is defined in the array yytname. Also generated are #defines for YYNTOKENS, YYNNTS, YYNRULES, and YYNSTATES. =item -t =item --debug Passed to bison. In the parser file, define the macro YYDEBUG to 1 if it is not already defined, so that the debugging facilities are compiled. =item -v =item --verbose Passed to bison. Write an extra output file containing verbose descriptions of the parser states and what is done for each type of look-ahead token in that state. This file also describes all the conflicts, both those resolved by operator precedence and the unresolved ones. The file's name is made by removing .tab.c or .c from the parser output file name, and adding .output instead. Therefore, if the input file is foo.y, then the parser file is called foo.tab.c by default. As a consequence, the verbose output file is called foo.output. =item --version Print the version number and exit. =item --yacc Specify the name of the bison executable, defaults to "bison." =back =head1 DISTRIBUTION This is part of the L free Verilog EDA software tool suite. The latest version is available from CPAN and from L. Copyright 2008-2024 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. =head1 AUTHORS Wilson Snyder =head1 SEE ALSO C =cut ###################################################################### ### Local Variables: ### compile-command: "./bisonpre " ### End: Verilog-Perl-3.482/Parser/Makefile.PL0000644000177100017500000001165414553624300017233 0ustar wsnyderwsnyder# DESCRIPTION: Perl ExtUtils: Type 'perl Makefile.PL' to create a Makefile for this package # # Copyright 2000-2024 by Wilson Snyder. This program is free software; # you can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. use ExtUtils::MakeMaker; use Config; sub MY::postamble { my $out; #print Config::myconfig(); if ($Config{osname} !~ /cygwin/i && $Config{archname} !~ /cygwin/i && $Config{osname} !~ /darwin/i && $Config{archname} !~ /darwin/i) { # Cygwin: Don't change LD, it breaks # Sun: Requires g++ LD # Linux: Either way $out .= "LD = g++\n"; } # Note OPTIMIZE is passed from upper makefile, so this code needed there too. my $optimize = $Config{optimize}; $optimize =~ s/(^| )-O2( |$)/\1-O\2/g; # pass hardening flags $optimize .= " $ENV{CFLAGS} $ENV{CPPFLAGS}"; $out .= "OPTIMIZE = $optimize\n"; if ($Config{osname} =~ /cygwin/i || $Config{archname} =~ /cygwin/i) { # Cygwin ExtUtils::MakeMaker ignores our LIBS declaration and says # "No library found for -lstdc++". Force it. $out .= "LDLOADLIBS += -lstdc++\n"; # Cygwin: High optimization causes g++ "out of memory" $out .= "OPTIMIZE += -O\n"; } if ($Config{osname} =~ /darwin/i || $Config{archname} =~ /darwin/i) { # MakeMaker wants to create bundles on MacOSX rather than dylibs. We override DLEXT and LDDLFLAGS generated by MakeMaker in this case $out .= "DLEXT = dylib\n"; if ($^V eq '5.12.4') { $out .= sprintf("LDDLFLAGS = -dynamiclib -lstdc++ -L/System/Library/Perl/5.12/%s/CORE -lperl -L/usr/local/lib\n",$Config{archname}); } elsif ($^V eq '5.18.2') { $out .= sprintf("LDDLFLAGS = -dynamiclib -lstdc++ -L/System/Library/Perl/5.18/%s/CORE -lperl -L/usr/local/lib\n",$Config{archname}); } elsif ($^V < 'v5.26.3') { $out .= sprintf("LDDLFLAGS = -dynamiclib -lstdc++ -L/System/Library/Perl/%vd/%s/CORE -lperl -lgcc_eh -L/usr/local/lib\n",$^V,$Config{archname}); } } # The ../Makefile.PL will override these if make is called from there! $out .= "CCFLAGS += -Wall -Wno-unused -Wno-sign-compare -Werror\n" if $ENV{VERILATOR_AUTHOR_SITE}; $out .= "CCFLAGS += $ENV{VERILOGPERL_CCFLAGS}\n" if defined $ENV{VERILOGPERL_CCFLAGS}; $out .= "OPTIMIZE += -Wno-unused\n" if $ENV{VERILATOR_AUTHOR_SITE}; # Makefile has another -Wall $out .= "OPTIMIZE += $ENV{VERILOGPERL_CCFLAGS}\n" if defined $ENV{VERILOGPERL_CCFLAGS}; $out .= "CCFLAGS += -I\$(PPSRC)\n"; my $cmt = $ENV{VERILOGPERL_FLEX_DEBUG} ? "" : "#"; $out .= "${cmt}CFLAGS += -DFLEX_DEBUG\n"; $out .= "LEXFLAGS += -d\n"; $out .= ' CC = $(OBJCACHE) g++ LEX = flex YACC = bison PPSRC = ../Preproc FLEXFIX = $(PPSRC)/flexfix TOOLHASH = $(PPSRC)/toolhash XSUBPPFIX = $(PPSRC)/xsubppfix VPATH += . $(PPSRC) VHEADERS = VParseLex.h VParseGrammar.h VParse.h VFileLine.h VParseBison.h \ VSymTable.h VAst.h Parser_callbackgen.cpp VParseLex.o: VParseLex.cpp $(VHEADERS) VParseGrammar.o: VParseGrammar.cpp $(VHEADERS) VParseBison.o: VParseBison.cpp $(VHEADERS) VParse.o: VParse.cpp $(VHEADERS) VFileLine.o: VFileLine.cpp $(VHEADERS) VAst.o: VAst.cpp $(VHEADERS) VSymTable.o: VSymTable.cpp $(VHEADERS) VFileLine.o: $(PPSRC)/VFileLine.cpp $(CCCMD) $(CCCDLFLAGS) "-I$(PERL_INC)" $(PASTHRU_DEFINE) $(DEFINE) $< VParseLex_pretmp.cpp: VParseLex.l -$(LEX) --version $(PERL) $(TOOLHASH) --verbose --in $< --out $@ --cmd $(LEX) $(LEXFLAGS) -o$@ $< VParseLex.cpp: $(FLEXFIX) VParseLex_pretmp.cpp $(PERL) $(FLEXFIX) VParseLex < VParseLex_pretmp.cpp > $@ VParseBison.h: VParseBison.cpp VParseBison.cpp: VParseBison.y bisonpre -$(RM_RF) VParseBison.c VParseBison.cpp -${YACC} --version | head -1 @echo "Note: toolhash ignores VParseBison.output; remove gen/ if you want to debug the grammar" @echo "Note: If the next command fails, you probably need to install Bison 1.875 or newer" $(PERL) $(TOOLHASH) --verbose --name bisonpre --vercmd bison --skip-cmd 1 \ --in VParseBison.y bisonpre \ --out VParseBison.c VParseBison.h \ --cmd $(PERL) bisonpre --yacc ${YACC} --debug --verbose --d -p VParseBison -k VParseBison.y -o VParseBison.c mv VParseBison.c VParseBison.cpp Parser_callbackgen.cpp: callbackgen $(PERL) callbackgen Parser_cleaned.cpp: Parser.c $(VHEADERS) $(PERL) $(XSUBPPFIX) < Parser.c > Parser_cleaned.cpp clean:: -$(RM_RF) test *.d *.o *.output *.pre.* *_pretmp.* -$(RM_RF) VParseLex*.cpp VParseBison.h VParseBison.cpp Parser_cleaned.* -$(RM_RF) Parser_callbackgen.cpp '; return $out; } # Grr; some flags cause warnings in g++ (my $ccflags = $Config{ccflags}) =~ s/ *-Wdeclaration-after-statement//; WriteMakefile( NAME => "Verilog::Parser", LIBS => '-lstdc++', VERSION_FROM => 'Parser.pm', XSOPT => '-C++', CCFLAGS => $ccflags, OBJECT => 'VFileLine.o VParseLex.o VParse.o VParseBison.o VSymTable.o VAst.o ', MYEXTLIB => 'Parser_cleaned.o', ); Verilog-Perl-3.482/Parser/VAst.h0000644000177100017500000001117614553624300016306 0ustar wsnyderwsnyder// -*- C++ -*- //************************************************************************* // // Copyright 2009-2024 by Wilson Snyder. This program is free software; // you can redistribute it and/or modify it under the terms of either the // GNU Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // //************************************************************************* /// \file /// \brief Verilog::Parse: Symbol table accessing /// /// Authors: Wilson Snyder /// /// Code available from: https://www.veripool.org/verilog-perl /// //************************************************************************* #ifndef _VAST_H_ #define _VAST_H_ 1 #include #include #include using namespace std; // We don't include perl.h as it gets upset when merged with bison // code. So just grab a minimal set. struct av; struct hv; //###################################################################### // Enumeration that indicates what type of symbol is in the symbol tree. // We may later change to use a different object for each type class VAstType { public: enum en { NOT_FOUND = 0, NETLIST = 1, // Top of structure, created by Parser.pm:sub new{} AN_ERROR = 2, // Consistency error in internal tables (ERROR alone is a #define on some systems) UNKNOWN = 3, // Things that need scope, but don't know type yet // BLOCK, CHECKER, CLASS, // For yaID__CLASS CLOCKING, COVERGROUP, // For yaID__COVERGROUP ENUM, FORK, FUNCTION, INTERFACE, LET, MODPORT, MODULE, PACKAGE, // For yaID__PACKAGE PROGRAM, PROPERTY, SEQUENCE, STRUCT, TASK, TYPE, // For yaID__TYPE UNION, _MAX }; enum en m_e; inline VAstType() {}; inline VAstType(en _e) : m_e(_e) {}; explicit inline VAstType(int _e) : m_e(static_cast(_e)) {}; operator en() const { return m_e; }; const char* ascii() const { static const char* names[] = { "NOT_FOUND", "netlist", "error", "unknown", "block", "checker", "class", "clocking", "covergroup", "enum", "fork", "function", "interface", "let", "modport", "module", "package", "program", "property", "sequence", "struct", "task", "type", "union", "_MAX" }; return names[m_e]; } }; inline bool operator== (VAstType lhs, VAstType rhs) { return (lhs.m_e == rhs.m_e); } inline bool operator== (VAstType lhs, VAstType::en rhs) { return (lhs.m_e == rhs); } inline bool operator== (VAstType::en lhs, VAstType rhs) { return (lhs == rhs.m_e); } //###################################################################### // Single symbol table class VAstEnt { private: // MEMBERS // NOT ALLOWED - this class really has this==AV* // STATIC MEMBERS static int s_debug; public: static void debug(int flag) { s_debug=flag; } static int debug() { return s_debug; } private: // CREATORS VAstEnt() { assert(0); } // Not made by users, it's an AV* ~VAstEnt() { assert(0); } // Not made by users, it's an AV* av* newAVEnt(VAstType type); static void initAVEnt(struct av* avp, VAstType type, struct av* parentp); // ACCESSORS inline struct av* castAVp() { return (struct av*)(this); } inline VAstEnt* avToSymEnt(struct av* avp) { return (VAstEnt*)(avp); } /// $self->[2]: For current entry, the hash of symbols under it struct hv* subhash(); /// Insert into current table void replaceInsert(VAstEnt* newentp, const string& name); public: // ACCESSORS /// $self->[0]: For current entry, the node type VAstType type(); /// $self->[1]: For current entry, what node it is under or NULL if netlist VAstEnt* parentp(); /// type() indicates we shouldn't report this as a containing object bool typeIgnoreObjof() { VAstType t=type(); return t==VAstType::BLOCK || t==VAstType::FORK; } /// Info on current node, for debug string ascii(const string& name=""); // METHODS /// Return internal pointer for given name or null VAstEnt* findSym(const string& name); /// Find or create a symbol under current entry VAstEnt* findInsert(VAstType type, const string& name); /// Replace or create a symbol entry under current entry VAstEnt* replaceInsert(VAstType type, const string& name); /// Insert into current table from another imported package's table void import(VAstEnt* fromEntp, const string& id_or_star); protected: friend class VSymStack; void initNetlist(VFileLine* fl); }; #endif // guard Verilog-Perl-3.482/Parser/VParseLex.h0000644000177100017500000001073114553624300017276 0ustar wsnyderwsnyder// -*- C++ -*- //************************************************************************* // // Copyright 2000-2024 by Wilson Snyder. This program is free software; // you can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. // // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // //************************************************************************* /// \file /// \brief Verilog::Parse: Internal header for lex interfacing /// /// Authors: Wilson Snyder /// /// Code available from: https://www.veripool.org/verilog-perl /// /// This header provides the interface between the lex proper VParseLex.l/.cpp /// and the class implementation file VParse.cpp /// It is not intended for user applications. /// //************************************************************************* #ifndef _VPARSELEX_H_ // Guard #define _VPARSELEX_H_ 1 #include "VFileLine.h" #include "VParseGrammar.h" //====================================================================== // Externs created by flex // We add a prefix so that other lexers/flexers in the same program won't collide. #ifndef yy_create_buffer # define yy_create_buffer VParseLex_create_buffer # define yy_delete_buffer VParseLex_delete_buffer # define yy_scan_buffer VParseLex_scan_buffer # define yy_scan_string VParseLex_scan_string # define yy_scan_bytes VParseLex_scan_bytes # define yy_flex_debug VParseLex_flex_debug # define yy_init_buffer VParseLex_init_buffer # define yy_flush_buffer VParseLex_flush_buffer # define yy_load_buffer_state VParseLex_load_buffer_state # define yy_switch_to_buffer VParseLex_switch_to_buffer # define yyin VParseLexin # define yyleng VParseLexleng # define yylex VParseLexlex # define yyout VParseLexout # define yyrestart VParseLexrestart # define yytext VParseLextext #endif #ifndef YY_BUFFER_STATE struct yy_buffer_state; typedef struct yy_buffer_state *YY_BUFFER_STATE; # define YY_BUF_SIZE 16384 #endif extern int yylex(); extern void yyrestart(FILE*); YY_BUFFER_STATE yy_create_buffer (FILE *file, int size); YY_BUFFER_STATE yy_scan_bytes(const char *bytes, int len); void yy_switch_to_buffer(YY_BUFFER_STATE new_buffer); void yy_delete_buffer(YY_BUFFER_STATE b); class VParse; //====================================================================== /// Class entry for each lexer state class VParseLex { public: // Used only by VParseLex.cpp and VParse.cpp VParse* m_parsep; ///< Current parser bool m_inCellDefine; ///< In a `celldefine int m_prevLexToken; ///< previous parsed token (for lexer) bool m_ahead; ///< aheadToken is valid int m_aheadToken; ///< Token we read ahead VParseBisonYYSType m_aheadVal; ///< aheadToken's value int m_pvstate; ///< "pure virtual" detection // Parse state YY_BUFFER_STATE m_yyState; ///< flex input state // State to lexer static VParseLex* s_currentLexp; ///< Current lexing point static VParseBisonYYSType* s_yylvalp; int prevLexToken() { return m_prevLexToken; } // Parser -> lexer communication // CONSTRUCTORS VParseLex(VParse* parsep) { m_parsep = parsep; m_inCellDefine = false; m_prevLexToken = 0; m_ahead = false; m_pvstate = 0; m_yyState = yy_create_buffer(NULL, YY_BUF_SIZE); s_currentLexp = this; yyrestart(NULL); debug(0); } ~VParseLex() { yy_delete_buffer(m_yyState); s_currentLexp = NULL; } void restart() { yyrestart(NULL); } // Internal Utilities static bool symEscapeless(const char* textp, size_t leng) { // Are \ escapes needed to print this symbol? if (leng<1) return false; // Probably not a valid identifier, but better than a core dump... if (!isalpha(textp[0]) && textp[0] != '_') return false; const char* cp = textp; for (size_t tleng=leng; tleng; tleng--, cp++) { if (!isalnum(*cp) && *cp != '_') return false; } if (VParse::isKeyword(textp, leng)) return false; return true; } /// Called by VParse.cpp to inform lexer void unputString(const char* textp); void unputString(const char* textp, size_t length); void debug(int level); void language(const char* value); int lexToBison(VParseBisonYYSType* yylvalp); private: void unused(); int yylexReadTok(); int lexToken(VParseBisonYYSType* yylvalp); }; #endif // Guard Verilog-Perl-3.482/Parser/gen/0000755000177100017500000000000014553624441016031 5ustar wsnyderwsnyderVerilog-Perl-3.482/Parser/gen/bisonpre-10000644000177100017500003073105014553624372017747 0ustar wsnyderwsnyder/* A Bison parser, made by GNU Bison 3.8.2. */ /* Bison implementation for Yacc-like parsers in C Copyright (C) 1984, 1989-1990, 2000-2015, 2018-2021 Free Software Foundation, Inc. This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program. If not, see . */ /* As a special exception, you may create a larger work that contains part or all of the Bison parser skeleton and distribute that work under terms of your choice, so long as that work isn't itself a parser generator using the skeleton or a modified version thereof as a parser skeleton. Alternatively, if you modify or redistribute the parser skeleton itself, you may (at your option) remove this special exception, which will cause the skeleton and the resulting Bison output files to be licensed under the GNU General Public License without this special exception. This special exception was added by the Free Software Foundation in version 2.2 of Bison. */ /* C LALR(1) parser skeleton written by Richard Stallman, by simplifying the original so-called "semantic" parser. */ /* DO NOT RELY ON FEATURES THAT ARE NOT DOCUMENTED in the manual, especially those whose name start with YY_ or yy_. They are private implementation details that can be changed or removed. */ /* All symbols defined below should begin with yy or YY, to avoid infringing on user name space. This should be done even for local variables, as they might otherwise be expanded by user macros. There are some unavoidable exceptions within include files to define necessary library symbols; they are noted "INFRINGES ON USER NAME SPACE" below. */ /* Identify Bison output, and Bison version. */ #define YYBISON 30802 /* Bison version string. */ #define YYBISON_VERSION "3.8.2" /* Skeleton name. */ #define YYSKELETON_NAME "yacc.c" /* Pure parsers. */ #define YYPURE 1 /* Push parsers. */ #define YYPUSH 0 /* Pull parsers. */ #define YYPULL 1 /* Substitute the variable and function names. */ #define yyparse VParseBisonparse #define yylex VParseBisonlex #define yyerror VParseBisonerror #define yydebug VParseBisondebug #define yynerrs VParseBisonnerrs /* First part of user prologue. */ #line 24 "VParseBison.y" #include #include #include #include #include #include #include #include #include #include #include #include "VParse.h" #include "VParseGrammar.h" #define YYERROR_VERBOSE 1 #define YYINITDEPTH 5000 // Large as the stack won't grow, since YYSTYPE_IS_TRIVIAL isn't defined #define YYMAXDEPTH 5000 // See VParseGrammar.h for the C++ interface to this parser // Include that instead of VParseBison.h //************************************************************************* #define GRAMMARP VParseGrammar::staticGrammarp() #define PARSEP VParseGrammar::staticParsep() #define NEWSTRING(text) (string((text))) #define SPACED(a,b) ((a)+(((a)=="" || (b)=="")?"":" ")+(b)) #define VARS_PUSH() { GRAMMARP->m_varStack.push_back(GRAMMARP->m_var); } #define VARS_POP() { GRAMMARP->m_var = GRAMMARP->m_varStack.back(); GRAMMARP->m_varStack.pop_back(); } #define VARRESET_LIST(decl) { GRAMMARP->pinNum(1); VARRESET(); VARDECL(decl); } // Start of pinlist #define VARRESET_NONLIST(decl) { GRAMMARP->pinNum(0); VARRESET(); VARDECL(decl); } // Not in a pinlist #define VARRESET() { VARDECL(""); VARIO(""); VARNET(""); VARDTYPE(""); } // Start of one variable decl // VARDECL("") indicates inside a port list or IO list and we shouldn't declare the variable #define VARDECL(type) \ { GRAMMARP->m_var.m_decl = (type); } // genvar, parameter, localparam #define VARIO(type) \ { GRAMMARP->m_var.m_io = (type); } // input, output, inout, ref, const ref #define VARNET(type) \ { GRAMMARP->m_var.m_net = (type); } // supply*,wire,tri #define VARDTYPE(type) \ { GRAMMARP->m_var.m_dtype = (type); } // "signed", "int", etc #define PINNUMINC() { GRAMMARP->pinNumInc(); } #define INSTPREP(cellmod,cellparam,withinInst) { GRAMMARP->pinNum(1); GRAMMARP->m_cellMod=(cellmod); GRAMMARP->m_cellParam=(cellparam); GRAMMARP->m_withinInst = 1; } #define INSTDONE() { GRAMMARP->m_withinInst = 0; } enum net_idx {NI_NETNAME = 0, NI_MSB, NI_LSB}; static void VARDONE(VFileLine * fl, const string& name, const string& array, const string& value) { if (GRAMMARP->m_var.m_io != "" && GRAMMARP->m_var.m_decl == "") GRAMMARP->m_var.m_decl = "port"; if (GRAMMARP->m_var.m_decl != "") { PARSEP->varCb(fl, GRAMMARP->m_var.m_decl, name, PARSEP->symObjofUpward(), GRAMMARP->m_var.m_net, GRAMMARP->m_var.m_dtype, array, value); } if (GRAMMARP->m_var.m_io != "" || GRAMMARP->pinNum()) { PARSEP->portCb(fl, name, PARSEP->symObjofUpward(), GRAMMARP->m_var.m_io, GRAMMARP->m_var.m_dtype, array, GRAMMARP->pinNum()); } if (GRAMMARP->m_var.m_dtype == "type") { PARSEP->syms().replaceInsert(VAstType::TYPE, name); } } static void VARDONETYPEDEF(VFileLine* fl, const string& name, const string& type, const string& array) { VARRESET(); VARDECL("typedef"); VARDTYPE(type); VARDONE(fl,name,array,""); // TYPE shouldn't override a more specific node type, as often is forward reference PARSEP->syms().replaceInsert(VAstType::TYPE, name); } static void parse_net_constants(VFileLine* fl, VParseHashElem nets[][3]) { VParseHashElem (*net)[3] = &nets[0]; VParseHashElem* nhp = net[0]; std::deque::iterator it = GRAMMARP->m_portStack.begin(); while (it != GRAMMARP->m_portStack.end()) { // Default net name is simply the complete token const char* netnamep = it->m_name.c_str(); size_t delim = it->m_name.find_first_of("'"); if (it->m_name[0] != '\\' && it->m_msb.empty() && delim != string::npos && it->m_name[delim] == '\'') { // Handle sized integer constants (e.g., 7'b0) specifically but ignore replications (e.g., {4{w}}) if (delim != 0 && netnamep[0] != '{') { // Handle the first part that indicates the width for sized constants (guaranteed to be a decimal) char* endp; errno = 0; long l = strtol(netnamep, &endp, 10); if ((errno == ERANGE && l == LONG_MAX) || l > INT_MAX || l <= 0) { fl->error((string)"Unexpected length in size of integer constant: \""+netnamep+"\"."); return; } // Skip whitespace while (endp < netnamep + delim && isspace(*endp)) { endp++; } if (endp != netnamep + delim) { fl->error((string)"Could not convert size of integer constant: \""+netnamep+"\"."); return; } int count = l; // Skip characters up to the delimiter ' to determine new netnamep netnamep += delim; // Test for legal base specifiers: // d, D, h, H, o, O , b, or B for the decimal, hexadecimal, octal, and binary bases, respectively char base = netnamep[1]; // 's' indicates a signed constant, is followed by the actual base; currently ignored if (base == 's' || base == 'S') { base = netnamep[2]; } if (strchr("dDhHoObB", base) == NULL) { fl->error((string)"Base specifier \""+base+"\" is not valid in integer constant \""+it->m_name.c_str()+"\"."); return; } // These assignments could be prettified with C++11 nhp[NI_MSB].keyp = "msb"; nhp[NI_MSB].val_type = VParseHashElem::ELEM_INT; nhp[NI_MSB].val_int = count - 1; nhp[NI_LSB].keyp = "lsb"; nhp[NI_LSB].val_type = VParseHashElem::ELEM_INT; nhp[NI_LSB].val_int = 0; } else { // fl->error increases the error count which would create regressions for no good reasons. // There is no ->warn or similar though but we could print, e.g., to stderr in these cases //fl->error((string)"Neither unsized integer constant nor replications are not fully supported in nets (\""+netnamep+"\")."); //fprintf(stderr, "Neither unsized integer constant nor replications are not fully supported in nets (\"%s\").\n", netnamep); } } else { // Ordinary net names might have a range attached or not. // If it does then parse its bounds into proper integers. const char *msbstr = it->m_msb.c_str(); if (msbstr[0] != '\0') { { // Parse NI_MSB char* endp; errno = 0; long l = strtol(msbstr, &endp, 10); // Test for range within int, and proper parsing if ((errno == ERANGE && l == LONG_MAX) || l > INT_MAX || l < 0 || (endp && l == 0 && errno == ERANGE)) { fl->error((string)"Unexpected length in msb specification of \""+netnamep+"\" (endp="+endp+", errno="+strerror(errno)+")."); return; } nhp[NI_MSB].keyp = "msb"; nhp[NI_MSB].val_type = VParseHashElem::ELEM_INT; nhp[NI_MSB].val_int = (int)l; } { // Parse NI_LSB char* endp; errno = 0; long l = strtol(it->m_lsb.c_str(), &endp, 10); if ((errno == ERANGE && l == LONG_MAX) || l > INT_MAX || l < 0 || (endp && l == 0 && errno == ERANGE)) { fl->error((string)"Unexpected length in lsb specification of \""+netnamep+"\"."); return; } nhp[NI_LSB].keyp = "lsb"; nhp[NI_LSB].val_type = VParseHashElem::ELEM_INT; nhp[NI_LSB].val_int = (int)l; } } else { nhp[NI_MSB].keyp = NULL; nhp[NI_LSB].keyp = NULL; } } nhp[NI_NETNAME].keyp = "netname"; nhp[NI_NETNAME].val_type = VParseHashElem::ELEM_STR; nhp[NI_NETNAME].val_str = netnamep; *it++; nhp += 3; // We operate on three elements in each iteration } } static void PINDONE(VFileLine* fl, const string& name, const string& expr) { if (GRAMMARP->m_cellParam) { // Stack them until we create the instance itself GRAMMARP->m_pinStack.push_back(VParseGPin(fl, name, expr, GRAMMARP->pinNum())); } else { PARSEP->pinCb(fl, name, expr, GRAMMARP->pinNum()); if (PARSEP->usePinSelects()) { if (GRAMMARP->m_portStack.empty()) { string netname; if (GRAMMARP->m_portNextNetName.empty()) { netname = expr; } else { netname = GRAMMARP->m_portNextNetName; } size_t elem_cnt = GRAMMARP->m_portNextNetMsb.empty() ? 1 : 3; VParseHashElem nets[elem_cnt]; // These assignments could be prettified with C++11 nets[NI_NETNAME].keyp = "netname"; nets[NI_NETNAME].val_type = VParseHashElem::ELEM_STR; nets[NI_NETNAME].val_str = netname; if (elem_cnt > 1) { nets[NI_MSB].keyp = "msb"; nets[NI_MSB].val_type = VParseHashElem::ELEM_STR; nets[NI_MSB].val_str = GRAMMARP->m_portNextNetMsb; nets[NI_LSB].keyp = "lsb"; nets[NI_LSB].val_type = VParseHashElem::ELEM_STR; nets[NI_LSB].val_str = GRAMMARP->m_portNextNetLsb; } PARSEP->pinselectsCb(fl, name, 1, elem_cnt, &nets[0], GRAMMARP->pinNum()); } else { // Connection with multiple pins was parsed completely. // There might be one net left in the pipe... if (GRAMMARP->m_portNextNetValid) { GRAMMARP->m_portStack.push_front(VParseNet(GRAMMARP->m_portNextNetName, GRAMMARP->m_portNextNetMsb, GRAMMARP->m_portNextNetLsb)); } unsigned int arraycnt = GRAMMARP->m_portStack.size(); VParseHashElem nets[arraycnt][3]; parse_net_constants(fl, nets); PARSEP->pinselectsCb(fl, name, arraycnt, 3, &nets[0][0], GRAMMARP->pinNum()); } // Clear all pin-related fields GRAMMARP->m_portNextNetValid = false; GRAMMARP->m_portNextNetName.clear(); GRAMMARP->m_portStack.clear(); GRAMMARP->m_portNextNetMsb.clear(); GRAMMARP->m_portNextNetLsb.clear(); } } } static void PINPARAMS() { // Throw out all the "pins" we found before we could do instanceCb while (!GRAMMARP->m_pinStack.empty()) { VParseGPin& pinr = GRAMMARP->m_pinStack.front(); PARSEP->parampinCb(pinr.m_fl, pinr.m_name, pinr.m_conn, pinr.m_number); GRAMMARP->m_pinStack.pop_front(); } GRAMMARP->m_withinPin = true; } static void PORTNET(VFileLine* fl, const string& name) { if (!GRAMMARP->m_withinInst) { return; } GRAMMARP->m_portNextNetValid = true; GRAMMARP->m_portNextNetName = name; GRAMMARP->m_portNextNetMsb.clear(); GRAMMARP->m_portNextNetLsb.clear(); } static void PORTRANGE(const string& msb, const string& lsb) { if (!GRAMMARP->m_withinInst) { return; } GRAMMARP->m_portNextNetMsb = msb; GRAMMARP->m_portNextNetLsb = lsb; } static void PIN_CONCAT_APPEND(const string& expr) { if (!GRAMMARP->m_withinPin) { return; } if (!GRAMMARP->m_portNextNetValid) { // Only while not within a valid net term the expression is part // of a replication constant. If that's detected ignore the // previous expression (that is actually just the contained // concatenation) in favor of the full replication expression. if (expr[0] == '{') { if (expr.find_first_of("{", 1) != string::npos) { // fprintf(stderr, "%d: ignoring \"%s\" in favor of \"%s\".\n", __LINE__, GRAMMARP->m_portStack.front().m_name.c_str(), expr.c_str()); GRAMMARP->m_portStack.pop_front(); GRAMMARP->m_portStack.push_front(VParseNet(expr)); } } else { GRAMMARP->m_portStack.push_front(VParseNet(expr)); } } else { GRAMMARP->m_portStack.push_front(VParseNet(GRAMMARP->m_portNextNetName, GRAMMARP->m_portNextNetMsb, GRAMMARP->m_portNextNetLsb)); } GRAMMARP->m_portNextNetValid = false; } /* Yacc */ static int VParseBisonlex(VParseBisonYYSType* yylvalp) { return PARSEP->lexToBison(yylvalp); } static void VParseBisonerror(const char *s) { VParseGrammar::bisonError(s); } static void ERRSVKWD(VFileLine* fileline, const string& tokname) { static int toldonce = 0; fileline->error((string)"Unexpected \""+tokname+"\": \""+tokname+"\" is a SystemVerilog keyword misused as an identifier."); if (!toldonce++) fileline->error("Modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language."); } static void NEED_S09(VFileLine*, const string&) { //Let lint tools worry about it //fileline->error((string)"Advanced feature: \""+tokname+"\" is a 1800-2009 construct, but used under --language 1800-2005 or earlier."); } // gcc-11 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98753 #if defined(__GNUC__) && __GNUC__ == 11 #pragma GCC diagnostic ignored "-Wfree-nonheap-object" #endif #line 387 "VParseBison.c" # ifndef YY_CAST # ifdef __cplusplus # define YY_CAST(Type, Val) static_cast (Val) # define YY_REINTERPRET_CAST(Type, Val) reinterpret_cast (Val) # else # define YY_CAST(Type, Val) ((Type) (Val)) # define YY_REINTERPRET_CAST(Type, Val) ((Type) (Val)) # endif # endif # ifndef YY_NULLPTR # if defined __cplusplus # if 201103L <= __cplusplus # define YY_NULLPTR nullptr # else # define YY_NULLPTR 0 # endif # else # define YY_NULLPTR ((void*)0) # endif # endif #include "VParseBison.h" /* Symbol kind. */ enum yysymbol_kind_t { YYSYMBOL_YYEMPTY = -2, YYSYMBOL_YYEOF = 0, /* "end of file" */ YYSYMBOL_YYerror = 1, /* error */ YYSYMBOL_YYUNDEF = 2, /* "invalid token" */ YYSYMBOL_yaFLOATNUM = 3, /* "FLOATING-POINT NUMBER" */ YYSYMBOL_yaID__ETC = 4, /* "IDENTIFIER" */ YYSYMBOL_yaID__LEX = 5, /* "IDENTIFIER-in-lex" */ YYSYMBOL_yaID__aPACKAGE = 6, /* "PACKAGE-IDENTIFIER" */ YYSYMBOL_yaID__aTYPE = 7, /* "TYPE-IDENTIFIER" */ YYSYMBOL_yaINTNUM = 8, /* "INTEGER NUMBER" */ YYSYMBOL_yaTIMENUM = 9, /* "TIME NUMBER" */ YYSYMBOL_yaSTRING = 10, /* "STRING" */ YYSYMBOL_yaSTRING__IGNORE = 11, /* "STRING-ignored" */ YYSYMBOL_yaTIMINGSPEC = 12, /* "TIMING SPEC ELEMENT" */ YYSYMBOL_ygenGATE = 13, /* "GATE keyword" */ YYSYMBOL_ygenCONFIGKEYWORD = 14, /* "CONFIG keyword (cell/use/design/etc)" */ YYSYMBOL_ygenOPERATOR = 15, /* "OPERATOR" */ YYSYMBOL_ygenSTRENGTH = 16, /* "STRENGTH keyword (strong1/etc)" */ YYSYMBOL_ygenSYSCALL = 17, /* "SYSCALL" */ YYSYMBOL_18_ = 18, /* '!' */ YYSYMBOL_19_ = 19, /* '#' */ YYSYMBOL_20_ = 20, /* '%' */ YYSYMBOL_21_ = 21, /* '&' */ YYSYMBOL_22_ = 22, /* '(' */ YYSYMBOL_23_ = 23, /* ')' */ YYSYMBOL_24_ = 24, /* '*' */ YYSYMBOL_25_ = 25, /* '+' */ YYSYMBOL_26_ = 26, /* ',' */ YYSYMBOL_27_ = 27, /* '-' */ YYSYMBOL_28_ = 28, /* '.' */ YYSYMBOL_29_ = 29, /* '/' */ YYSYMBOL_30_ = 30, /* ':' */ YYSYMBOL_31_ = 31, /* ';' */ YYSYMBOL_32_ = 32, /* '<' */ YYSYMBOL_33_ = 33, /* '=' */ YYSYMBOL_34_ = 34, /* '>' */ YYSYMBOL_35_ = 35, /* '?' */ YYSYMBOL_36_ = 36, /* '@' */ YYSYMBOL_37_ = 37, /* '[' */ YYSYMBOL_38_ = 38, /* ']' */ YYSYMBOL_39_ = 39, /* '^' */ YYSYMBOL_40_ = 40, /* '{' */ YYSYMBOL_41_ = 41, /* '|' */ YYSYMBOL_42_ = 42, /* '}' */ YYSYMBOL_43_ = 43, /* '~' */ YYSYMBOL_yACCEPT_ON = 44, /* "accept_on" */ YYSYMBOL_yALIAS = 45, /* "alias" */ YYSYMBOL_yALWAYS = 46, /* "always" */ YYSYMBOL_yAND = 47, /* "and" */ YYSYMBOL_yASSERT = 48, /* "assert" */ YYSYMBOL_yASSIGN = 49, /* "assign" */ YYSYMBOL_yASSUME = 50, /* "assume" */ YYSYMBOL_yAUTOMATIC = 51, /* "automatic" */ YYSYMBOL_yBEFORE = 52, /* "before" */ YYSYMBOL_yBEGIN = 53, /* "begin" */ YYSYMBOL_yBIND = 54, /* "bind" */ YYSYMBOL_yBINS = 55, /* "bins" */ YYSYMBOL_yBINSOF = 56, /* "binsof" */ YYSYMBOL_yBIT = 57, /* "bit" */ YYSYMBOL_yBREAK = 58, /* "break" */ YYSYMBOL_yBUF = 59, /* "buf" */ YYSYMBOL_yBYTE = 60, /* "byte" */ YYSYMBOL_yCASE = 61, /* "case" */ YYSYMBOL_yCASEX = 62, /* "casex" */ YYSYMBOL_yCASEZ = 63, /* "casez" */ YYSYMBOL_yCHANDLE = 64, /* "chandle" */ YYSYMBOL_yCHECKER = 65, /* "checker" */ YYSYMBOL_yCLASS = 66, /* "class" */ YYSYMBOL_yCLOCK = 67, /* "clock" */ YYSYMBOL_yCLOCKING = 68, /* "clocking" */ YYSYMBOL_yCONSTRAINT = 69, /* "constraint" */ YYSYMBOL_yCONST__ETC = 70, /* "const" */ YYSYMBOL_yCONST__LEX = 71, /* "const-in-lex" */ YYSYMBOL_yCONST__LOCAL = 72, /* "const-then-local" */ YYSYMBOL_yCONST__REF = 73, /* "const-then-ref" */ YYSYMBOL_yCONTEXT = 74, /* "context" */ YYSYMBOL_yCONTINUE = 75, /* "continue" */ YYSYMBOL_yCOVER = 76, /* "cover" */ YYSYMBOL_yCOVERGROUP = 77, /* "covergroup" */ YYSYMBOL_yCOVERPOINT = 78, /* "coverpoint" */ YYSYMBOL_yCROSS = 79, /* "cross" */ YYSYMBOL_yDEASSIGN = 80, /* "deassign" */ YYSYMBOL_yDEFAULT = 81, /* "default" */ YYSYMBOL_yDEFPARAM = 82, /* "defparam" */ YYSYMBOL_yDISABLE = 83, /* "disable" */ YYSYMBOL_yDIST = 84, /* "dist" */ YYSYMBOL_yDO = 85, /* "do" */ YYSYMBOL_yEDGE = 86, /* "edge" */ YYSYMBOL_yELSE = 87, /* "else" */ YYSYMBOL_yEND = 88, /* "end" */ YYSYMBOL_yENDCASE = 89, /* "endcase" */ YYSYMBOL_yENDCHECKER = 90, /* "endchecker" */ YYSYMBOL_yENDCLASS = 91, /* "endclass" */ YYSYMBOL_yENDCLOCKING = 92, /* "endclocking" */ YYSYMBOL_yENDFUNCTION = 93, /* "endfunction" */ YYSYMBOL_yENDGENERATE = 94, /* "endgenerate" */ YYSYMBOL_yENDGROUP = 95, /* "endgroup" */ YYSYMBOL_yENDINTERFACE = 96, /* "endinterface" */ YYSYMBOL_yENDMODULE = 97, /* "endmodule" */ YYSYMBOL_yENDPACKAGE = 98, /* "endpackage" */ YYSYMBOL_yENDPROGRAM = 99, /* "endprogram" */ YYSYMBOL_yENDPROPERTY = 100, /* "endproperty" */ YYSYMBOL_yENDSEQUENCE = 101, /* "endsequence" */ YYSYMBOL_yENDSPECIFY = 102, /* "endspecify" */ YYSYMBOL_yENDTABLE = 103, /* "endtable" */ YYSYMBOL_yENDTASK = 104, /* "endtask" */ YYSYMBOL_yENUM = 105, /* "enum" */ YYSYMBOL_yEVENT = 106, /* "event" */ YYSYMBOL_yEVENTUALLY = 107, /* "eventually" */ YYSYMBOL_yEXPECT = 108, /* "expect" */ YYSYMBOL_yEXPORT = 109, /* "export" */ YYSYMBOL_yEXTENDS = 110, /* "extends" */ YYSYMBOL_yEXTERN = 111, /* "extern" */ YYSYMBOL_yFINAL = 112, /* "final" */ YYSYMBOL_yFIRST_MATCH = 113, /* "first_match" */ YYSYMBOL_yFOR = 114, /* "for" */ YYSYMBOL_yFORCE = 115, /* "force" */ YYSYMBOL_yFOREACH = 116, /* "foreach" */ YYSYMBOL_yFOREVER = 117, /* "forever" */ YYSYMBOL_yFORK = 118, /* "fork" */ YYSYMBOL_yFORKJOIN = 119, /* "forkjoin" */ YYSYMBOL_yFUNCTION__ETC = 120, /* "function" */ YYSYMBOL_yFUNCTION__LEX = 121, /* "function-in-lex" */ YYSYMBOL_yFUNCTION__aPUREV = 122, /* "function-is-pure-virtual" */ YYSYMBOL_yGENERATE = 123, /* "generate" */ YYSYMBOL_yGENVAR = 124, /* "genvar" */ YYSYMBOL_yGLOBAL__CLOCKING = 125, /* "global-then-clocking" */ YYSYMBOL_yGLOBAL__LEX = 126, /* "global-in-lex" */ YYSYMBOL_yIF = 127, /* "if" */ YYSYMBOL_yIFF = 128, /* "iff" */ YYSYMBOL_yIGNORE_BINS = 129, /* "ignore_bins" */ YYSYMBOL_yILLEGAL_BINS = 130, /* "illegal_bins" */ YYSYMBOL_yIMPLEMENTS = 131, /* "implements" */ YYSYMBOL_yIMPLIES = 132, /* "implies" */ YYSYMBOL_yIMPORT = 133, /* "import" */ YYSYMBOL_yINITIAL = 134, /* "initial" */ YYSYMBOL_yINOUT = 135, /* "inout" */ YYSYMBOL_yINPUT = 136, /* "input" */ YYSYMBOL_yINSIDE = 137, /* "inside" */ YYSYMBOL_yINT = 138, /* "int" */ YYSYMBOL_yINTEGER = 139, /* "integer" */ YYSYMBOL_yINTERCONNECT = 140, /* "interconnect" */ YYSYMBOL_yINTERFACE = 141, /* "interface" */ YYSYMBOL_yINTERSECT = 142, /* "intersect" */ YYSYMBOL_yJOIN = 143, /* "join" */ YYSYMBOL_yLET = 144, /* "let" */ YYSYMBOL_yLOCALPARAM = 145, /* "localparam" */ YYSYMBOL_yLOCAL__COLONCOLON = 146, /* "local-then-::" */ YYSYMBOL_yLOCAL__ETC = 147, /* "local" */ YYSYMBOL_yLOCAL__LEX = 148, /* "local-in-lex" */ YYSYMBOL_yLOGIC = 149, /* "logic" */ YYSYMBOL_yLONGINT = 150, /* "longint" */ YYSYMBOL_yMATCHES = 151, /* "matches" */ YYSYMBOL_yMODPORT = 152, /* "modport" */ YYSYMBOL_yMODULE = 153, /* "module" */ YYSYMBOL_yNAND = 154, /* "nand" */ YYSYMBOL_yNEGEDGE = 155, /* "negedge" */ YYSYMBOL_yNETTYPE = 156, /* "nettype" */ YYSYMBOL_yNEW__ETC = 157, /* "new" */ YYSYMBOL_yNEW__LEX = 158, /* "new-in-lex" */ YYSYMBOL_yNEW__PAREN = 159, /* "new-then-paren" */ YYSYMBOL_yNEXTTIME = 160, /* "nexttime" */ YYSYMBOL_yNOR = 161, /* "nor" */ YYSYMBOL_yNOT = 162, /* "not" */ YYSYMBOL_yNULL = 163, /* "null" */ YYSYMBOL_yOR = 164, /* "or" */ YYSYMBOL_yOUTPUT = 165, /* "output" */ YYSYMBOL_yPACKAGE = 166, /* "package" */ YYSYMBOL_yPACKED = 167, /* "packed" */ YYSYMBOL_yPARAMETER = 168, /* "parameter" */ YYSYMBOL_yPOSEDGE = 169, /* "posedge" */ YYSYMBOL_yPRIORITY = 170, /* "priority" */ YYSYMBOL_yPROGRAM = 171, /* "program" */ YYSYMBOL_yPROPERTY = 172, /* "property" */ YYSYMBOL_yPROTECTED = 173, /* "protected" */ YYSYMBOL_yPURE = 174, /* "pure" */ YYSYMBOL_yRAND = 175, /* "rand" */ YYSYMBOL_yRANDC = 176, /* "randc" */ YYSYMBOL_yRANDCASE = 177, /* "randcase" */ YYSYMBOL_yRANDSEQUENCE = 178, /* "randsequence" */ YYSYMBOL_yREAL = 179, /* "real" */ YYSYMBOL_yREALTIME = 180, /* "realtime" */ YYSYMBOL_yREF = 181, /* "ref" */ YYSYMBOL_yREG = 182, /* "reg" */ YYSYMBOL_yREJECT_ON = 183, /* "reject_on" */ YYSYMBOL_yRELEASE = 184, /* "release" */ YYSYMBOL_yREPEAT = 185, /* "repeat" */ YYSYMBOL_yRESTRICT = 186, /* "restrict" */ YYSYMBOL_yRETURN = 187, /* "return" */ YYSYMBOL_ySCALARED = 188, /* "scalared" */ YYSYMBOL_ySEQUENCE = 189, /* "sequence" */ YYSYMBOL_ySHORTINT = 190, /* "shortint" */ YYSYMBOL_ySHORTREAL = 191, /* "shortreal" */ YYSYMBOL_ySIGNED = 192, /* "signed" */ YYSYMBOL_ySOFT = 193, /* "soft" */ YYSYMBOL_ySOLVE = 194, /* "solve" */ YYSYMBOL_ySPECIFY = 195, /* "specify" */ YYSYMBOL_ySPECPARAM = 196, /* "specparam" */ YYSYMBOL_ySTATIC__CONSTRAINT = 197, /* "static-then-constraint" */ YYSYMBOL_ySTATIC__ETC = 198, /* "static" */ YYSYMBOL_ySTATIC__LEX = 199, /* "static-in-lex" */ YYSYMBOL_ySTRING = 200, /* "string" */ YYSYMBOL_ySTRONG = 201, /* "strong" */ YYSYMBOL_ySTRUCT = 202, /* "struct" */ YYSYMBOL_ySUPER = 203, /* "super" */ YYSYMBOL_ySUPPLY0 = 204, /* "supply0" */ YYSYMBOL_ySUPPLY1 = 205, /* "supply1" */ YYSYMBOL_ySYNC_ACCEPT_ON = 206, /* "sync_accept_on" */ YYSYMBOL_ySYNC_REJECT_ON = 207, /* "sync_reject_on" */ YYSYMBOL_yS_ALWAYS = 208, /* "s_always" */ YYSYMBOL_yS_EVENTUALLY = 209, /* "s_eventually" */ YYSYMBOL_yS_NEXTTIME = 210, /* "s_nexttime" */ YYSYMBOL_yS_UNTIL = 211, /* "s_until" */ YYSYMBOL_yS_UNTIL_WITH = 212, /* "s_until_with" */ YYSYMBOL_yTABLE = 213, /* "table" */ YYSYMBOL_yTAGGED = 214, /* "tagged" */ YYSYMBOL_yTASK__ETC = 215, /* "task" */ YYSYMBOL_yTASK__LEX = 216, /* "task-in-lex" */ YYSYMBOL_yTASK__aPUREV = 217, /* "task-is-pure-virtual" */ YYSYMBOL_yTHIS = 218, /* "this" */ YYSYMBOL_yTHROUGHOUT = 219, /* "throughout" */ YYSYMBOL_yTIME = 220, /* "time" */ YYSYMBOL_yTIMEPRECISION = 221, /* "timeprecision" */ YYSYMBOL_yTIMEUNIT = 222, /* "timeunit" */ YYSYMBOL_yTRI = 223, /* "tri" */ YYSYMBOL_yTRI0 = 224, /* "tri0" */ YYSYMBOL_yTRI1 = 225, /* "tri1" */ YYSYMBOL_yTRIAND = 226, /* "triand" */ YYSYMBOL_yTRIOR = 227, /* "trior" */ YYSYMBOL_yTRIREG = 228, /* "trireg" */ YYSYMBOL_yTYPE = 229, /* "type" */ YYSYMBOL_yTYPEDEF = 230, /* "typedef" */ YYSYMBOL_yUNION = 231, /* "union" */ YYSYMBOL_yUNIQUE = 232, /* "unique" */ YYSYMBOL_yUNIQUE0 = 233, /* "unique0" */ YYSYMBOL_yUNSIGNED = 234, /* "unsigned" */ YYSYMBOL_yUNTIL = 235, /* "until" */ YYSYMBOL_yUNTIL_WITH = 236, /* "until_with" */ YYSYMBOL_yUNTYPED = 237, /* "untyped" */ YYSYMBOL_yVAR = 238, /* "var" */ YYSYMBOL_yVECTORED = 239, /* "vectored" */ YYSYMBOL_yVIRTUAL__CLASS = 240, /* "virtual-then-class" */ YYSYMBOL_yVIRTUAL__ETC = 241, /* "virtual" */ YYSYMBOL_yVIRTUAL__INTERFACE = 242, /* "virtual-then-interface" */ YYSYMBOL_yVIRTUAL__LEX = 243, /* "virtual-in-lex" */ YYSYMBOL_yVIRTUAL__anyID = 244, /* "virtual-then-identifier" */ YYSYMBOL_yVOID = 245, /* "void" */ YYSYMBOL_yWAIT = 246, /* "wait" */ YYSYMBOL_yWAIT_ORDER = 247, /* "wait_order" */ YYSYMBOL_yWAND = 248, /* "wand" */ YYSYMBOL_yWEAK = 249, /* "weak" */ YYSYMBOL_yWHILE = 250, /* "while" */ YYSYMBOL_yWILDCARD = 251, /* "wildcard" */ YYSYMBOL_yWIRE = 252, /* "wire" */ YYSYMBOL_yWITHIN = 253, /* "within" */ YYSYMBOL_yWITH__BRA = 254, /* "with-then-[" */ YYSYMBOL_yWITH__CUR = 255, /* "with-then-{" */ YYSYMBOL_yWITH__ETC = 256, /* "with" */ YYSYMBOL_yWITH__LEX = 257, /* "with-in-lex" */ YYSYMBOL_yWITH__PAREN = 258, /* "with-then-(" */ YYSYMBOL_yWOR = 259, /* "wor" */ YYSYMBOL_yXNOR = 260, /* "xnor" */ YYSYMBOL_yXOR = 261, /* "xor" */ YYSYMBOL_yD_ERROR = 262, /* "$error" */ YYSYMBOL_yD_FATAL = 263, /* "$fatal" */ YYSYMBOL_yD_INFO = 264, /* "$info" */ YYSYMBOL_yD_ROOT = 265, /* "$root" */ YYSYMBOL_yD_UNIT = 266, /* "$unit" */ YYSYMBOL_yD_WARNING = 267, /* "$warning" */ YYSYMBOL_yP_TICK = 268, /* "'" */ YYSYMBOL_yP_TICKBRA = 269, /* "'{" */ YYSYMBOL_yP_OROR = 270, /* "||" */ YYSYMBOL_yP_ANDAND = 271, /* "&&" */ YYSYMBOL_yP_NOR = 272, /* "~|" */ YYSYMBOL_yP_XNOR = 273, /* "^~" */ YYSYMBOL_yP_NAND = 274, /* "~&" */ YYSYMBOL_yP_EQUAL = 275, /* "==" */ YYSYMBOL_yP_NOTEQUAL = 276, /* "!=" */ YYSYMBOL_yP_CASEEQUAL = 277, /* "===" */ YYSYMBOL_yP_CASENOTEQUAL = 278, /* "!==" */ YYSYMBOL_yP_WILDEQUAL = 279, /* "==?" */ YYSYMBOL_yP_WILDNOTEQUAL = 280, /* "!=?" */ YYSYMBOL_yP_GTE = 281, /* ">=" */ YYSYMBOL_yP_LTE = 282, /* "<=" */ YYSYMBOL_yP_LTE__IGNORE = 283, /* "<=-ignored" */ YYSYMBOL_yP_SLEFT = 284, /* "<<" */ YYSYMBOL_yP_SRIGHT = 285, /* ">>" */ YYSYMBOL_yP_SSRIGHT = 286, /* ">>>" */ YYSYMBOL_yP_POW = 287, /* "**" */ YYSYMBOL_yP_PAR__IGNORE = 288, /* "(-ignored" */ YYSYMBOL_yP_PAR__STRENGTH = 289, /* "(-for-strength" */ YYSYMBOL_yP_LTMINUSGT = 290, /* "<->" */ YYSYMBOL_yP_PLUSCOLON = 291, /* "+:" */ YYSYMBOL_yP_MINUSCOLON = 292, /* "-:" */ YYSYMBOL_yP_MINUSGT = 293, /* "->" */ YYSYMBOL_yP_MINUSGTGT = 294, /* "->>" */ YYSYMBOL_yP_EQGT = 295, /* "=>" */ YYSYMBOL_yP_ASTGT = 296, /* "*>" */ YYSYMBOL_yP_ANDANDAND = 297, /* "&&&" */ YYSYMBOL_yP_POUNDPOUND = 298, /* "##" */ YYSYMBOL_yP_POUNDMINUSPD = 299, /* "#-#" */ YYSYMBOL_yP_POUNDEQPD = 300, /* "#=#" */ YYSYMBOL_yP_DOTSTAR = 301, /* ".*" */ YYSYMBOL_yP_ATAT = 302, /* "@@" */ YYSYMBOL_yP_COLONCOLON = 303, /* "::" */ YYSYMBOL_yP_COLONEQ = 304, /* ":=" */ YYSYMBOL_yP_COLONDIV = 305, /* ":/" */ YYSYMBOL_yP_ORMINUSGT = 306, /* "|->" */ YYSYMBOL_yP_OREQGT = 307, /* "|=>" */ YYSYMBOL_yP_BRASTAR = 308, /* "[*" */ YYSYMBOL_yP_BRAEQ = 309, /* "[=" */ YYSYMBOL_yP_BRAMINUSGT = 310, /* "[->" */ YYSYMBOL_yP_BRAPLUSKET = 311, /* "[+]" */ YYSYMBOL_yP_PLUSPLUS = 312, /* "++" */ YYSYMBOL_yP_MINUSMINUS = 313, /* "--" */ YYSYMBOL_yP_PLUSEQ = 314, /* "+=" */ YYSYMBOL_yP_MINUSEQ = 315, /* "-=" */ YYSYMBOL_yP_TIMESEQ = 316, /* "*=" */ YYSYMBOL_yP_DIVEQ = 317, /* "/=" */ YYSYMBOL_yP_MODEQ = 318, /* "%=" */ YYSYMBOL_yP_ANDEQ = 319, /* "&=" */ YYSYMBOL_yP_OREQ = 320, /* "|=" */ YYSYMBOL_yP_XOREQ = 321, /* "^=" */ YYSYMBOL_yP_SLEFTEQ = 322, /* "<<=" */ YYSYMBOL_yP_SRIGHTEQ = 323, /* ">>=" */ YYSYMBOL_yP_SSRIGHTEQ = 324, /* ">>>=" */ YYSYMBOL_prUNARYARITH = 325, /* prUNARYARITH */ YYSYMBOL_prREDUCTION = 326, /* prREDUCTION */ YYSYMBOL_prNEGATION = 327, /* prNEGATION */ YYSYMBOL_prEVENTBEGIN = 328, /* prEVENTBEGIN */ YYSYMBOL_prTAGGED = 329, /* prTAGGED */ YYSYMBOL_prSEQ_CLOCKING = 330, /* prSEQ_CLOCKING */ YYSYMBOL_prPOUNDPOUND_MULTI = 331, /* prPOUNDPOUND_MULTI */ YYSYMBOL_prLOWER_THAN_ELSE = 332, /* prLOWER_THAN_ELSE */ YYSYMBOL_333_ = 333, /* "+" */ YYSYMBOL_334_ = 334, /* "-" */ YYSYMBOL_335_ = 335, /* "*" */ YYSYMBOL_336_ = 336, /* "/" */ YYSYMBOL_337_ = 337, /* "%" */ YYSYMBOL_338_ = 338, /* "<" */ YYSYMBOL_339_ = 339, /* ">" */ YYSYMBOL_340_ = 340, /* "=" */ YYSYMBOL_341___ = 341, /* '_' */ YYSYMBOL_342_ = 342, /* '$' */ YYSYMBOL_YYACCEPT = 343, /* $accept */ YYSYMBOL_statePushVlg = 344, /* statePushVlg */ YYSYMBOL_statePop = 345, /* statePop */ YYSYMBOL_source_text = 346, /* source_text */ YYSYMBOL_descriptionList = 347, /* descriptionList */ YYSYMBOL_description = 348, /* description */ YYSYMBOL_timeunits_declaration = 349, /* timeunits_declaration */ YYSYMBOL_package_declaration = 350, /* package_declaration */ YYSYMBOL_packageFront = 351, /* packageFront */ YYSYMBOL_package_itemListE = 352, /* package_itemListE */ YYSYMBOL_package_itemList = 353, /* package_itemList */ YYSYMBOL_package_item = 354, /* package_item */ YYSYMBOL_package_or_generate_item_declaration = 355, /* package_or_generate_item_declaration */ YYSYMBOL_package_import_declarationList = 356, /* package_import_declarationList */ YYSYMBOL_package_import_declaration = 357, /* package_import_declaration */ YYSYMBOL_package_import_itemList = 358, /* package_import_itemList */ YYSYMBOL_package_import_item = 359, /* package_import_item */ YYSYMBOL_package_import_itemObj = 360, /* package_import_itemObj */ YYSYMBOL_package_export_declaration = 361, /* package_export_declaration */ YYSYMBOL_module_declaration = 362, /* module_declaration */ YYSYMBOL_modFront = 363, /* modFront */ YYSYMBOL_importsAndParametersE = 364, /* importsAndParametersE */ YYSYMBOL_parameter_value_assignmentE = 365, /* parameter_value_assignmentE */ YYSYMBOL_parameter_port_listE = 366, /* parameter_port_listE */ YYSYMBOL_367_1 = 367, /* $@1 */ YYSYMBOL_paramPortDeclOrArgList = 368, /* paramPortDeclOrArgList */ YYSYMBOL_paramPortDeclOrArg = 369, /* paramPortDeclOrArg */ YYSYMBOL_portsStarE = 370, /* portsStarE */ YYSYMBOL_371_2 = 371, /* $@2 */ YYSYMBOL_list_of_portsE = 372, /* list_of_portsE */ YYSYMBOL_portE = 373, /* portE */ YYSYMBOL_portDirNetE = 374, /* portDirNetE */ YYSYMBOL_port_declNetE = 375, /* port_declNetE */ YYSYMBOL_portAssignExprE = 376, /* portAssignExprE */ YYSYMBOL_portSig = 377, /* portSig */ YYSYMBOL_interface_declaration = 378, /* interface_declaration */ YYSYMBOL_intFront = 379, /* intFront */ YYSYMBOL_interface_itemListE = 380, /* interface_itemListE */ YYSYMBOL_interface_itemList = 381, /* interface_itemList */ YYSYMBOL_interface_item = 382, /* interface_item */ YYSYMBOL_interface_or_generate_item = 383, /* interface_or_generate_item */ YYSYMBOL_anonymous_program = 384, /* anonymous_program */ YYSYMBOL_anonymous_program_itemListE = 385, /* anonymous_program_itemListE */ YYSYMBOL_anonymous_program_itemList = 386, /* anonymous_program_itemList */ YYSYMBOL_anonymous_program_item = 387, /* anonymous_program_item */ YYSYMBOL_program_declaration = 388, /* program_declaration */ YYSYMBOL_pgmFront = 389, /* pgmFront */ YYSYMBOL_program_itemListE = 390, /* program_itemListE */ YYSYMBOL_program_itemList = 391, /* program_itemList */ YYSYMBOL_program_item = 392, /* program_item */ YYSYMBOL_non_port_program_item = 393, /* non_port_program_item */ YYSYMBOL_program_generate_item = 394, /* program_generate_item */ YYSYMBOL_extern_tf_declaration = 395, /* extern_tf_declaration */ YYSYMBOL_modport_declaration = 396, /* modport_declaration */ YYSYMBOL_modport_itemList = 397, /* modport_itemList */ YYSYMBOL_modport_item = 398, /* modport_item */ YYSYMBOL_399_3 = 399, /* $@3 */ YYSYMBOL_modport_idFront = 400, /* modport_idFront */ YYSYMBOL_modportPortsDeclList = 401, /* modportPortsDeclList */ YYSYMBOL_modportPortsDecl = 402, /* modportPortsDecl */ YYSYMBOL_modportSimplePort = 403, /* modportSimplePort */ YYSYMBOL_modport_tf_port = 404, /* modport_tf_port */ YYSYMBOL_genvar_declaration = 405, /* genvar_declaration */ YYSYMBOL_list_of_genvar_identifiers = 406, /* list_of_genvar_identifiers */ YYSYMBOL_genvar_identifierDecl = 407, /* genvar_identifierDecl */ YYSYMBOL_local_parameter_declaration = 408, /* local_parameter_declaration */ YYSYMBOL_parameter_declaration = 409, /* parameter_declaration */ YYSYMBOL_local_parameter_declarationFront = 410, /* local_parameter_declarationFront */ YYSYMBOL_parameter_declarationFront = 411, /* parameter_declarationFront */ YYSYMBOL_parameter_port_declarationFront = 412, /* parameter_port_declarationFront */ YYSYMBOL_net_declaration = 413, /* net_declaration */ YYSYMBOL_net_declarationFront = 414, /* net_declarationFront */ YYSYMBOL_net_declRESET = 415, /* net_declRESET */ YYSYMBOL_net_scalaredE = 416, /* net_scalaredE */ YYSYMBOL_net_dataType = 417, /* net_dataType */ YYSYMBOL_net_type = 418, /* net_type */ YYSYMBOL_varGParamReset = 419, /* varGParamReset */ YYSYMBOL_varLParamReset = 420, /* varLParamReset */ YYSYMBOL_port_direction = 421, /* port_direction */ YYSYMBOL_port_directionReset = 422, /* port_directionReset */ YYSYMBOL_port_declaration = 423, /* port_declaration */ YYSYMBOL_424_4 = 424, /* $@4 */ YYSYMBOL_425_5 = 425, /* $@5 */ YYSYMBOL_426_6 = 426, /* $@6 */ YYSYMBOL_427_7 = 427, /* $@7 */ YYSYMBOL_tf_port_declaration = 428, /* tf_port_declaration */ YYSYMBOL_429_8 = 429, /* $@8 */ YYSYMBOL_430_9 = 430, /* $@9 */ YYSYMBOL_integer_atom_type = 431, /* integer_atom_type */ YYSYMBOL_integer_vector_type = 432, /* integer_vector_type */ YYSYMBOL_non_integer_type = 433, /* non_integer_type */ YYSYMBOL_signingE = 434, /* signingE */ YYSYMBOL_signing = 435, /* signing */ YYSYMBOL_casting_type = 436, /* casting_type */ YYSYMBOL_simple_type = 437, /* simple_type */ YYSYMBOL_data_typeVar = 438, /* data_typeVar */ YYSYMBOL_data_type = 439, /* data_type */ YYSYMBOL_440_10 = 440, /* $@10 */ YYSYMBOL_441_11 = 441, /* $@11 */ YYSYMBOL_data_type_or_void = 442, /* data_type_or_void */ YYSYMBOL_var_data_type = 443, /* var_data_type */ YYSYMBOL_type_reference = 444, /* type_reference */ YYSYMBOL_struct_union_memberList = 445, /* struct_union_memberList */ YYSYMBOL_struct_union_member = 446, /* struct_union_member */ YYSYMBOL_447_12 = 447, /* $@12 */ YYSYMBOL_list_of_variable_decl_assignments = 448, /* list_of_variable_decl_assignments */ YYSYMBOL_variable_decl_assignment = 449, /* variable_decl_assignment */ YYSYMBOL_list_of_tf_variable_identifiers = 450, /* list_of_tf_variable_identifiers */ YYSYMBOL_tf_variable_identifier = 451, /* tf_variable_identifier */ YYSYMBOL_variable_declExpr = 452, /* variable_declExpr */ YYSYMBOL_variable_dimensionListE = 453, /* variable_dimensionListE */ YYSYMBOL_variable_dimensionList = 454, /* variable_dimensionList */ YYSYMBOL_variable_dimension = 455, /* variable_dimension */ YYSYMBOL_random_qualifierE = 456, /* random_qualifierE */ YYSYMBOL_random_qualifier = 457, /* random_qualifier */ YYSYMBOL_taggedE = 458, /* taggedE */ YYSYMBOL_packedSigningE = 459, /* packedSigningE */ YYSYMBOL_enumDecl = 460, /* enumDecl */ YYSYMBOL_enum_base_typeE = 461, /* enum_base_typeE */ YYSYMBOL_enum_nameList = 462, /* enum_nameList */ YYSYMBOL_enum_name_declaration = 463, /* enum_name_declaration */ YYSYMBOL_enumNameRangeE = 464, /* enumNameRangeE */ YYSYMBOL_enumNameStartE = 465, /* enumNameStartE */ YYSYMBOL_intnumAsConst = 466, /* intnumAsConst */ YYSYMBOL_data_declaration = 467, /* data_declaration */ YYSYMBOL_class_property = 468, /* class_property */ YYSYMBOL_data_declarationVar = 469, /* data_declarationVar */ YYSYMBOL_data_declarationVarClass = 470, /* data_declarationVarClass */ YYSYMBOL_data_declarationVarFront = 471, /* data_declarationVarFront */ YYSYMBOL_data_declarationVarFrontClass = 472, /* data_declarationVarFrontClass */ YYSYMBOL_net_type_declaration = 473, /* net_type_declaration */ YYSYMBOL_constE = 474, /* constE */ YYSYMBOL_implicit_typeE = 475, /* implicit_typeE */ YYSYMBOL_assertion_variable_declaration = 476, /* assertion_variable_declaration */ YYSYMBOL_type_declaration = 477, /* type_declaration */ YYSYMBOL_module_itemListE = 478, /* module_itemListE */ YYSYMBOL_module_itemList = 479, /* module_itemList */ YYSYMBOL_module_item = 480, /* module_item */ YYSYMBOL_non_port_module_item = 481, /* non_port_module_item */ YYSYMBOL_module_or_generate_item = 482, /* module_or_generate_item */ YYSYMBOL_module_common_item = 483, /* module_common_item */ YYSYMBOL_continuous_assign = 484, /* continuous_assign */ YYSYMBOL_initial_construct = 485, /* initial_construct */ YYSYMBOL_final_construct = 486, /* final_construct */ YYSYMBOL_module_or_generate_item_declaration = 487, /* module_or_generate_item_declaration */ YYSYMBOL_aliasEqList = 488, /* aliasEqList */ YYSYMBOL_bind_directive = 489, /* bind_directive */ YYSYMBOL_bind_target_instance_list = 490, /* bind_target_instance_list */ YYSYMBOL_bind_target_instance = 491, /* bind_target_instance */ YYSYMBOL_bind_instantiation = 492, /* bind_instantiation */ YYSYMBOL_generate_region = 493, /* generate_region */ YYSYMBOL_c_generate_region = 494, /* c_generate_region */ YYSYMBOL_generate_block = 495, /* generate_block */ YYSYMBOL_c_generate_block = 496, /* c_generate_block */ YYSYMBOL_genItemBegin = 497, /* genItemBegin */ YYSYMBOL_c_genItemBegin = 498, /* c_genItemBegin */ YYSYMBOL_genItemOrBegin = 499, /* genItemOrBegin */ YYSYMBOL_c_genItemOrBegin = 500, /* c_genItemOrBegin */ YYSYMBOL_genItemList = 501, /* genItemList */ YYSYMBOL_c_genItemList = 502, /* c_genItemList */ YYSYMBOL_generate_item = 503, /* generate_item */ YYSYMBOL_c_generate_item = 504, /* c_generate_item */ YYSYMBOL_conditional_generate_construct = 505, /* conditional_generate_construct */ YYSYMBOL_c_conditional_generate_construct = 506, /* c_conditional_generate_construct */ YYSYMBOL_loop_generate_construct = 507, /* loop_generate_construct */ YYSYMBOL_c_loop_generate_construct = 508, /* c_loop_generate_construct */ YYSYMBOL_genvar_initialization = 509, /* genvar_initialization */ YYSYMBOL_genvar_iteration = 510, /* genvar_iteration */ YYSYMBOL_case_generate_itemList = 511, /* case_generate_itemList */ YYSYMBOL_c_case_generate_itemList = 512, /* c_case_generate_itemList */ YYSYMBOL_case_generate_item = 513, /* case_generate_item */ YYSYMBOL_c_case_generate_item = 514, /* c_case_generate_item */ YYSYMBOL_assignList = 515, /* assignList */ YYSYMBOL_assignOne = 516, /* assignOne */ YYSYMBOL_delay_or_event_controlE = 517, /* delay_or_event_controlE */ YYSYMBOL_delayE = 518, /* delayE */ YYSYMBOL_delay_control = 519, /* delay_control */ YYSYMBOL_delay_value = 520, /* delay_value */ YYSYMBOL_delayExpr = 521, /* delayExpr */ YYSYMBOL_minTypMax = 522, /* minTypMax */ YYSYMBOL_netSigList = 523, /* netSigList */ YYSYMBOL_netSig = 524, /* netSig */ YYSYMBOL_netId = 525, /* netId */ YYSYMBOL_sigAttrListE = 526, /* sigAttrListE */ YYSYMBOL_rangeListE = 527, /* rangeListE */ YYSYMBOL_rangeList = 528, /* rangeList */ YYSYMBOL_regrangeE = 529, /* regrangeE */ YYSYMBOL_bit_selectE = 530, /* bit_selectE */ YYSYMBOL_anyrange = 531, /* anyrange */ YYSYMBOL_packed_dimensionListE = 532, /* packed_dimensionListE */ YYSYMBOL_packed_dimensionList = 533, /* packed_dimensionList */ YYSYMBOL_packed_dimension = 534, /* packed_dimension */ YYSYMBOL_param_assignment = 535, /* param_assignment */ YYSYMBOL_list_of_param_assignments = 536, /* list_of_param_assignments */ YYSYMBOL_list_of_defparam_assignments = 537, /* list_of_defparam_assignments */ YYSYMBOL_defparam_assignment = 538, /* defparam_assignment */ YYSYMBOL_etcInst = 539, /* etcInst */ YYSYMBOL_540_13 = 540, /* $@13 */ YYSYMBOL_541_14 = 541, /* $@14 */ YYSYMBOL_542_15 = 542, /* $@15 */ YYSYMBOL_543_16 = 543, /* $@16 */ YYSYMBOL_instName = 544, /* instName */ YYSYMBOL_mpInstnameList = 545, /* mpInstnameList */ YYSYMBOL_mpInstnameParen = 546, /* mpInstnameParen */ YYSYMBOL_mpInstname = 547, /* mpInstname */ YYSYMBOL_instnameList = 548, /* instnameList */ YYSYMBOL_instnameParen = 549, /* instnameParen */ YYSYMBOL_instname = 550, /* instname */ YYSYMBOL_instRangeListE = 551, /* instRangeListE */ YYSYMBOL_instRangeList = 552, /* instRangeList */ YYSYMBOL_instRange = 553, /* instRange */ YYSYMBOL_cellpinList = 554, /* cellpinList */ YYSYMBOL_555_17 = 555, /* $@17 */ YYSYMBOL_cellpinItList = 556, /* cellpinItList */ YYSYMBOL_557_18 = 557, /* $@18 */ YYSYMBOL_cellpinItemE = 558, /* cellpinItemE */ YYSYMBOL_event_control = 559, /* event_control */ YYSYMBOL_event_expression = 560, /* event_expression */ YYSYMBOL_senitemEdge = 561, /* senitemEdge */ YYSYMBOL_stmtBlock = 562, /* stmtBlock */ YYSYMBOL_seq_block = 563, /* seq_block */ YYSYMBOL_par_block = 564, /* par_block */ YYSYMBOL_seq_blockFront = 565, /* seq_blockFront */ YYSYMBOL_par_blockFront = 566, /* par_blockFront */ YYSYMBOL_blockDeclStmtList = 567, /* blockDeclStmtList */ YYSYMBOL_block_item_declarationList = 568, /* block_item_declarationList */ YYSYMBOL_block_item_declaration = 569, /* block_item_declaration */ YYSYMBOL_stmtList = 570, /* stmtList */ YYSYMBOL_stmt = 571, /* stmt */ YYSYMBOL_statement_item = 572, /* statement_item */ YYSYMBOL_operator_assignment = 573, /* operator_assignment */ YYSYMBOL_foperator_assignment = 574, /* foperator_assignment */ YYSYMBOL_inc_or_dec_expression = 575, /* inc_or_dec_expression */ YYSYMBOL_finc_or_dec_expression = 576, /* finc_or_dec_expression */ YYSYMBOL_sinc_or_dec_expression = 577, /* sinc_or_dec_expression */ YYSYMBOL_pinc_or_dec_expression = 578, /* pinc_or_dec_expression */ YYSYMBOL_ev_inc_or_dec_expression = 579, /* ev_inc_or_dec_expression */ YYSYMBOL_pev_inc_or_dec_expression = 580, /* pev_inc_or_dec_expression */ YYSYMBOL_class_new = 581, /* class_new */ YYSYMBOL_dynamic_array_new = 582, /* dynamic_array_new */ YYSYMBOL_unique_priorityE = 583, /* unique_priorityE */ YYSYMBOL_action_block = 584, /* action_block */ YYSYMBOL_caseStart = 585, /* caseStart */ YYSYMBOL_caseAttrE = 586, /* caseAttrE */ YYSYMBOL_case_patternListE = 587, /* case_patternListE */ YYSYMBOL_case_itemListE = 588, /* case_itemListE */ YYSYMBOL_case_insideListE = 589, /* case_insideListE */ YYSYMBOL_case_itemList = 590, /* case_itemList */ YYSYMBOL_case_inside_itemList = 591, /* case_inside_itemList */ YYSYMBOL_open_range_list = 592, /* open_range_list */ YYSYMBOL_open_value_range = 593, /* open_value_range */ YYSYMBOL_value_range = 594, /* value_range */ YYSYMBOL_covergroup_value_range = 595, /* covergroup_value_range */ YYSYMBOL_caseCondList = 596, /* caseCondList */ YYSYMBOL_patternNoExpr = 597, /* patternNoExpr */ YYSYMBOL_patternList = 598, /* patternList */ YYSYMBOL_patternOne = 599, /* patternOne */ YYSYMBOL_patternMemberList = 600, /* patternMemberList */ YYSYMBOL_patternKey = 601, /* patternKey */ YYSYMBOL_assignment_pattern = 602, /* assignment_pattern */ YYSYMBOL_for_initialization = 603, /* for_initialization */ YYSYMBOL_for_initializationItemList = 604, /* for_initializationItemList */ YYSYMBOL_for_initializationItem = 605, /* for_initializationItem */ YYSYMBOL_for_stepE = 606, /* for_stepE */ YYSYMBOL_for_step = 607, /* for_step */ YYSYMBOL_for_step_assignment = 608, /* for_step_assignment */ YYSYMBOL_loop_variables = 609, /* loop_variables */ YYSYMBOL_funcRef = 610, /* funcRef */ YYSYMBOL_task_subroutine_callNoMethod = 611, /* task_subroutine_callNoMethod */ YYSYMBOL_function_subroutine_callNoMethod = 612, /* function_subroutine_callNoMethod */ YYSYMBOL_system_t_call = 613, /* system_t_call */ YYSYMBOL_system_f_call = 614, /* system_f_call */ YYSYMBOL_elaboration_system_task = 615, /* elaboration_system_task */ YYSYMBOL_property_actual_arg = 616, /* property_actual_arg */ YYSYMBOL_task = 617, /* task */ YYSYMBOL_task_declaration = 618, /* task_declaration */ YYSYMBOL_task_prototype = 619, /* task_prototype */ YYSYMBOL_function = 620, /* function */ YYSYMBOL_function_declaration = 621, /* function_declaration */ YYSYMBOL_function_prototype = 622, /* function_prototype */ YYSYMBOL_class_constructor_prototype = 623, /* class_constructor_prototype */ YYSYMBOL_method_prototype = 624, /* method_prototype */ YYSYMBOL_lifetimeE = 625, /* lifetimeE */ YYSYMBOL_lifetime = 626, /* lifetime */ YYSYMBOL_taskId = 627, /* taskId */ YYSYMBOL_funcId = 628, /* funcId */ YYSYMBOL_funcIdNew = 629, /* funcIdNew */ YYSYMBOL_tfIdScoped = 630, /* tfIdScoped */ YYSYMBOL_tfGuts = 631, /* tfGuts */ YYSYMBOL_tfGutsPureV = 632, /* tfGutsPureV */ YYSYMBOL_tfBodyE = 633, /* tfBodyE */ YYSYMBOL_function_data_type = 634, /* function_data_type */ YYSYMBOL_tf_item_declarationList = 635, /* tf_item_declarationList */ YYSYMBOL_tf_item_declaration = 636, /* tf_item_declaration */ YYSYMBOL_tf_port_listE = 637, /* tf_port_listE */ YYSYMBOL_638_19 = 638, /* $@19 */ YYSYMBOL_tf_port_listList = 639, /* tf_port_listList */ YYSYMBOL_tf_port_item = 640, /* tf_port_item */ YYSYMBOL_tf_port_itemFront = 641, /* tf_port_itemFront */ YYSYMBOL_tf_port_itemDir = 642, /* tf_port_itemDir */ YYSYMBOL_tf_port_itemAssignment = 643, /* tf_port_itemAssignment */ YYSYMBOL_parenE = 644, /* parenE */ YYSYMBOL_array_methodNoRoot = 645, /* array_methodNoRoot */ YYSYMBOL_method_callWithE = 646, /* method_callWithE */ YYSYMBOL_array_method_nameNoId = 647, /* array_method_nameNoId */ YYSYMBOL_dpi_import_export = 648, /* dpi_import_export */ YYSYMBOL_dpi_importLabelE = 649, /* dpi_importLabelE */ YYSYMBOL_dpi_tf_import_propertyE = 650, /* dpi_tf_import_propertyE */ YYSYMBOL_overload_declaration = 651, /* overload_declaration */ YYSYMBOL_overload_operator = 652, /* overload_operator */ YYSYMBOL_overload_proto_formals = 653, /* overload_proto_formals */ YYSYMBOL_constExpr = 654, /* constExpr */ YYSYMBOL_expr = 655, /* expr */ YYSYMBOL_fexpr = 656, /* fexpr */ YYSYMBOL_ev_expr = 657, /* ev_expr */ YYSYMBOL_exprOkLvalue = 658, /* exprOkLvalue */ YYSYMBOL_fexprOkLvalue = 659, /* fexprOkLvalue */ YYSYMBOL_sexprOkLvalue = 660, /* sexprOkLvalue */ YYSYMBOL_pexprOkLvalue = 661, /* pexprOkLvalue */ YYSYMBOL_ev_exprOkLvalue = 662, /* ev_exprOkLvalue */ YYSYMBOL_pev_exprOkLvalue = 663, /* pev_exprOkLvalue */ YYSYMBOL_exprLvalue = 664, /* exprLvalue */ YYSYMBOL_fexprLvalue = 665, /* fexprLvalue */ YYSYMBOL_exprScope = 666, /* exprScope */ YYSYMBOL_fexprScope = 667, /* fexprScope */ YYSYMBOL_sexprScope = 668, /* sexprScope */ YYSYMBOL_pexprScope = 669, /* pexprScope */ YYSYMBOL_ev_exprScope = 670, /* ev_exprScope */ YYSYMBOL_pev_exprScope = 671, /* pev_exprScope */ YYSYMBOL_exprOrDataType = 672, /* exprOrDataType */ YYSYMBOL_exprOrDataTypeOrMinTypMax = 673, /* exprOrDataTypeOrMinTypMax */ YYSYMBOL_cateList = 674, /* cateList */ YYSYMBOL_exprOrDataTypeList = 675, /* exprOrDataTypeList */ YYSYMBOL_list_of_argumentsE = 676, /* list_of_argumentsE */ YYSYMBOL_pev_list_of_argumentsE = 677, /* pev_list_of_argumentsE */ YYSYMBOL_argsExprList = 678, /* argsExprList */ YYSYMBOL_argsExprListE = 679, /* argsExprListE */ YYSYMBOL_pev_argsExprListE = 680, /* pev_argsExprListE */ YYSYMBOL_argsExprOneE = 681, /* argsExprOneE */ YYSYMBOL_pev_argsExprOneE = 682, /* pev_argsExprOneE */ YYSYMBOL_argsDottedList = 683, /* argsDottedList */ YYSYMBOL_pev_argsDottedList = 684, /* pev_argsDottedList */ YYSYMBOL_argsDotted = 685, /* argsDotted */ YYSYMBOL_pev_argsDotted = 686, /* pev_argsDotted */ YYSYMBOL_streaming_concatenation = 687, /* streaming_concatenation */ YYSYMBOL_stream_concOrExprOrType = 688, /* stream_concOrExprOrType */ YYSYMBOL_stream_concatenation = 689, /* stream_concatenation */ YYSYMBOL_stream_expressionList = 690, /* stream_expressionList */ YYSYMBOL_stream_expression = 691, /* stream_expression */ YYSYMBOL_gateKwd = 692, /* gateKwd */ YYSYMBOL_strength = 693, /* strength */ YYSYMBOL_strengthSpecE = 694, /* strengthSpecE */ YYSYMBOL_strengthSpec = 695, /* strengthSpec */ YYSYMBOL_combinational_body = 696, /* combinational_body */ YYSYMBOL_tableJunkList = 697, /* tableJunkList */ YYSYMBOL_tableJunk = 698, /* tableJunk */ YYSYMBOL_specify_block = 699, /* specify_block */ YYSYMBOL_specifyJunkList = 700, /* specifyJunkList */ YYSYMBOL_specifyJunk = 701, /* specifyJunk */ YYSYMBOL_specparam_declaration = 702, /* specparam_declaration */ YYSYMBOL_junkToSemiList = 703, /* junkToSemiList */ YYSYMBOL_junkToSemi = 704, /* junkToSemi */ YYSYMBOL_id = 705, /* id */ YYSYMBOL_idAny = 706, /* idAny */ YYSYMBOL_idSVKwd = 707, /* idSVKwd */ YYSYMBOL_variable_lvalue = 708, /* variable_lvalue */ YYSYMBOL_variable_lvalueConcList = 709, /* variable_lvalueConcList */ YYSYMBOL_variable_lvalueList = 710, /* variable_lvalueList */ YYSYMBOL_idClassSel = 711, /* idClassSel */ YYSYMBOL_idClassForeach = 712, /* idClassForeach */ YYSYMBOL_hierarchical_identifierList = 713, /* hierarchical_identifierList */ YYSYMBOL_hierarchical_identifierBit = 714, /* hierarchical_identifierBit */ YYSYMBOL_hierarchical_identifier = 715, /* hierarchical_identifier */ YYSYMBOL_idDotted = 716, /* idDotted */ YYSYMBOL_idDottedForeach = 717, /* idDottedForeach */ YYSYMBOL_idDottedMore = 718, /* idDottedMore */ YYSYMBOL_idDottedForeachMore = 719, /* idDottedForeachMore */ YYSYMBOL_idArrayed = 720, /* idArrayed */ YYSYMBOL_idForeach = 721, /* idForeach */ YYSYMBOL_strAsInt = 722, /* strAsInt */ YYSYMBOL_endLabelE = 723, /* endLabelE */ YYSYMBOL_clocking_declaration = 724, /* clocking_declaration */ YYSYMBOL_clockingFront = 725, /* clockingFront */ YYSYMBOL_clocking_event = 726, /* clocking_event */ YYSYMBOL_clocking_itemListE = 727, /* clocking_itemListE */ YYSYMBOL_clocking_itemList = 728, /* clocking_itemList */ YYSYMBOL_clocking_item = 729, /* clocking_item */ YYSYMBOL_default_skew = 730, /* default_skew */ YYSYMBOL_clocking_direction = 731, /* clocking_direction */ YYSYMBOL_list_of_clocking_decl_assign = 732, /* list_of_clocking_decl_assign */ YYSYMBOL_clocking_decl_assign = 733, /* clocking_decl_assign */ YYSYMBOL_clocking_skewE = 734, /* clocking_skewE */ YYSYMBOL_clocking_skew = 735, /* clocking_skew */ YYSYMBOL_cycle_delay = 736, /* cycle_delay */ YYSYMBOL_assertion_item_declaration = 737, /* assertion_item_declaration */ YYSYMBOL_assertion_item = 738, /* assertion_item */ YYSYMBOL_deferred_immediate_assertion_item = 739, /* deferred_immediate_assertion_item */ YYSYMBOL_procedural_assertion_statement = 740, /* procedural_assertion_statement */ YYSYMBOL_immediate_assertion_statement = 741, /* immediate_assertion_statement */ YYSYMBOL_simple_immediate_assertion_statement = 742, /* simple_immediate_assertion_statement */ YYSYMBOL_final_zero = 743, /* final_zero */ YYSYMBOL_deferred_immediate_assertion_statement = 744, /* deferred_immediate_assertion_statement */ YYSYMBOL_expect_property_statement = 745, /* expect_property_statement */ YYSYMBOL_concurrent_assertion_item = 746, /* concurrent_assertion_item */ YYSYMBOL_concurrent_assertion_statement = 747, /* concurrent_assertion_statement */ YYSYMBOL_property_declaration = 748, /* property_declaration */ YYSYMBOL_property_declarationFront = 749, /* property_declarationFront */ YYSYMBOL_property_port_listE = 750, /* property_port_listE */ YYSYMBOL_751_20 = 751, /* $@20 */ YYSYMBOL_property_port_list = 752, /* property_port_list */ YYSYMBOL_property_port_item = 753, /* property_port_item */ YYSYMBOL_property_port_itemFront = 754, /* property_port_itemFront */ YYSYMBOL_property_port_itemAssignment = 755, /* property_port_itemAssignment */ YYSYMBOL_property_port_itemDirE = 756, /* property_port_itemDirE */ YYSYMBOL_property_declarationBody = 757, /* property_declarationBody */ YYSYMBOL_assertion_variable_declarationList = 758, /* assertion_variable_declarationList */ YYSYMBOL_sequence_declaration = 759, /* sequence_declaration */ YYSYMBOL_sequence_declarationFront = 760, /* sequence_declarationFront */ YYSYMBOL_sequence_port_listE = 761, /* sequence_port_listE */ YYSYMBOL_property_formal_typeNoDt = 762, /* property_formal_typeNoDt */ YYSYMBOL_sequence_formal_typeNoDt = 763, /* sequence_formal_typeNoDt */ YYSYMBOL_sequence_declarationBody = 764, /* sequence_declarationBody */ YYSYMBOL_property_spec = 765, /* property_spec */ YYSYMBOL_property_statement_spec = 766, /* property_statement_spec */ YYSYMBOL_property_statement = 767, /* property_statement */ YYSYMBOL_property_statementCaseIf = 768, /* property_statementCaseIf */ YYSYMBOL_property_case_itemList = 769, /* property_case_itemList */ YYSYMBOL_property_case_item = 770, /* property_case_item */ YYSYMBOL_pev_expr = 771, /* pev_expr */ YYSYMBOL_pexpr = 772, /* pexpr */ YYSYMBOL_sexpr = 773, /* sexpr */ YYSYMBOL_cycle_delay_range = 774, /* cycle_delay_range */ YYSYMBOL_sequence_match_itemList = 775, /* sequence_match_itemList */ YYSYMBOL_sequence_match_item = 776, /* sequence_match_item */ YYSYMBOL_boolean_abbrev = 777, /* boolean_abbrev */ YYSYMBOL_const_or_range_expression = 778, /* const_or_range_expression */ YYSYMBOL_constant_range = 779, /* constant_range */ YYSYMBOL_cycle_delay_const_range_expression = 780, /* cycle_delay_const_range_expression */ YYSYMBOL_let_declaration = 781, /* let_declaration */ YYSYMBOL_let_declarationFront = 782, /* let_declarationFront */ YYSYMBOL_let_port_listE = 783, /* let_port_listE */ YYSYMBOL_covergroup_declaration = 784, /* covergroup_declaration */ YYSYMBOL_covergroup_declarationFront = 785, /* covergroup_declarationFront */ YYSYMBOL_cgexpr = 786, /* cgexpr */ YYSYMBOL_coverage_spec_or_optionListE = 787, /* coverage_spec_or_optionListE */ YYSYMBOL_coverage_spec_or_optionList = 788, /* coverage_spec_or_optionList */ YYSYMBOL_coverage_spec_or_option = 789, /* coverage_spec_or_option */ YYSYMBOL_coverage_option = 790, /* coverage_option */ YYSYMBOL_cover_point = 791, /* cover_point */ YYSYMBOL_iffE = 792, /* iffE */ YYSYMBOL_bins_or_empty = 793, /* bins_or_empty */ YYSYMBOL_bins_or_optionsList = 794, /* bins_or_optionsList */ YYSYMBOL_bins_or_options = 795, /* bins_or_options */ YYSYMBOL_bins_orBraE = 796, /* bins_orBraE */ YYSYMBOL_bins_keyword = 797, /* bins_keyword */ YYSYMBOL_covergroup_range_list = 798, /* covergroup_range_list */ YYSYMBOL_trans_list = 799, /* trans_list */ YYSYMBOL_trans_set = 800, /* trans_set */ YYSYMBOL_trans_range_list = 801, /* trans_range_list */ YYSYMBOL_trans_item = 802, /* trans_item */ YYSYMBOL_repeat_range = 803, /* repeat_range */ YYSYMBOL_cover_cross = 804, /* cover_cross */ YYSYMBOL_list_of_cross_items = 805, /* list_of_cross_items */ YYSYMBOL_cross_itemList = 806, /* cross_itemList */ YYSYMBOL_cross_item = 807, /* cross_item */ YYSYMBOL_cross_body = 808, /* cross_body */ YYSYMBOL_cross_body_itemSemiList = 809, /* cross_body_itemSemiList */ YYSYMBOL_cross_body_item = 810, /* cross_body_item */ YYSYMBOL_bins_selection_or_option = 811, /* bins_selection_or_option */ YYSYMBOL_bins_selection = 812, /* bins_selection */ YYSYMBOL_select_expression = 813, /* select_expression */ YYSYMBOL_bins_expression = 814, /* bins_expression */ YYSYMBOL_coverage_eventE = 815, /* coverage_eventE */ YYSYMBOL_block_event_expression = 816, /* block_event_expression */ YYSYMBOL_block_event_expressionTerm = 817, /* block_event_expressionTerm */ YYSYMBOL_hierarchical_btf_identifier = 818, /* hierarchical_btf_identifier */ YYSYMBOL_randsequence_statement = 819, /* randsequence_statement */ YYSYMBOL_productionList = 820, /* productionList */ YYSYMBOL_production = 821, /* production */ YYSYMBOL_productionFront = 822, /* productionFront */ YYSYMBOL_rs_ruleList = 823, /* rs_ruleList */ YYSYMBOL_rs_rule = 824, /* rs_rule */ YYSYMBOL_rs_production_list = 825, /* rs_production_list */ YYSYMBOL_weight_specification = 826, /* weight_specification */ YYSYMBOL_rs_code_block = 827, /* rs_code_block */ YYSYMBOL_rs_code_blockItemList = 828, /* rs_code_blockItemList */ YYSYMBOL_rs_code_blockItem = 829, /* rs_code_blockItem */ YYSYMBOL_rs_prodList = 830, /* rs_prodList */ YYSYMBOL_rs_prod = 831, /* rs_prod */ YYSYMBOL_production_itemList = 832, /* production_itemList */ YYSYMBOL_production_item = 833, /* production_item */ YYSYMBOL_rs_case_itemList = 834, /* rs_case_itemList */ YYSYMBOL_rs_case_item = 835, /* rs_case_item */ YYSYMBOL_checker_declaration = 836, /* checker_declaration */ YYSYMBOL_checkerFront = 837, /* checkerFront */ YYSYMBOL_checker_port_listE = 838, /* checker_port_listE */ YYSYMBOL_checker_or_generate_itemListE = 839, /* checker_or_generate_itemListE */ YYSYMBOL_checker_or_generate_itemList = 840, /* checker_or_generate_itemList */ YYSYMBOL_checker_or_generate_item = 841, /* checker_or_generate_item */ YYSYMBOL_checker_or_generate_item_declaration = 842, /* checker_or_generate_item_declaration */ YYSYMBOL_checker_generate_item = 843, /* checker_generate_item */ YYSYMBOL_checker_instantiation = 844, /* checker_instantiation */ YYSYMBOL_class_declaration = 845, /* class_declaration */ YYSYMBOL_classFront = 846, /* classFront */ YYSYMBOL_classVirtualE = 847, /* classVirtualE */ YYSYMBOL_classExtendsE = 848, /* classExtendsE */ YYSYMBOL_classImplementsE = 849, /* classImplementsE */ YYSYMBOL_classImplementsList = 850, /* classImplementsList */ YYSYMBOL_ps_id_etc = 851, /* ps_id_etc */ YYSYMBOL_class_scope_id = 852, /* class_scope_id */ YYSYMBOL_class_typeWithoutId = 853, /* class_typeWithoutId */ YYSYMBOL_class_scopeWithoutId = 854, /* class_scopeWithoutId */ YYSYMBOL_class_scopeIdFollows = 855, /* class_scopeIdFollows */ YYSYMBOL_class_typeOneListColonIdFollows = 856, /* class_typeOneListColonIdFollows */ YYSYMBOL_class_typeOneList = 857, /* class_typeOneList */ YYSYMBOL_class_typeOne = 858, /* class_typeOne */ YYSYMBOL_package_scopeIdFollowsE = 859, /* package_scopeIdFollowsE */ YYSYMBOL_package_scopeIdFollows = 860, /* package_scopeIdFollows */ YYSYMBOL_861_21 = 861, /* $@21 */ YYSYMBOL_862_22 = 862, /* $@22 */ YYSYMBOL_863_23 = 863, /* $@23 */ YYSYMBOL_class_itemListE = 864, /* class_itemListE */ YYSYMBOL_class_itemList = 865, /* class_itemList */ YYSYMBOL_class_item = 866, /* class_item */ YYSYMBOL_class_method = 867, /* class_method */ YYSYMBOL_class_item_qualifier = 868, /* class_item_qualifier */ YYSYMBOL_memberQualResetListE = 869, /* memberQualResetListE */ YYSYMBOL_memberQualList = 870, /* memberQualList */ YYSYMBOL_memberQualOne = 871, /* memberQualOne */ YYSYMBOL_class_constraint = 872, /* class_constraint */ YYSYMBOL_constraint_block = 873, /* constraint_block */ YYSYMBOL_constraint_block_itemList = 874, /* constraint_block_itemList */ YYSYMBOL_constraint_block_item = 875, /* constraint_block_item */ YYSYMBOL_solve_before_list = 876, /* solve_before_list */ YYSYMBOL_constraint_primary = 877, /* constraint_primary */ YYSYMBOL_constraint_expressionList = 878, /* constraint_expressionList */ YYSYMBOL_constraint_expression = 879, /* constraint_expression */ YYSYMBOL_constraint_set = 880, /* constraint_set */ YYSYMBOL_dist_list = 881, /* dist_list */ YYSYMBOL_dist_item = 882, /* dist_item */ YYSYMBOL_extern_constraint_declaration = 883, /* extern_constraint_declaration */ YYSYMBOL_constraintStaticE = 884 /* constraintStaticE */ }; typedef enum yysymbol_kind_t yysymbol_kind_t; #ifdef short # undef short #endif /* On compilers that do not define __PTRDIFF_MAX__ etc., make sure and (if available) are included so that the code can choose integer types of a good width. */ #ifndef __PTRDIFF_MAX__ # include /* INFRINGES ON USER NAME SPACE */ # if defined __STDC_VERSION__ && 199901 <= __STDC_VERSION__ # include /* INFRINGES ON USER NAME SPACE */ # define YY_STDINT_H # endif #endif /* Narrow types that promote to a signed type and that can represent a signed or unsigned integer of at least N bits. In tables they can save space and decrease cache pressure. Promoting to a signed type helps avoid bugs in integer arithmetic. */ #ifdef __INT_LEAST8_MAX__ typedef __INT_LEAST8_TYPE__ yytype_int8; #elif defined YY_STDINT_H typedef int_least8_t yytype_int8; #else typedef signed char yytype_int8; #endif #ifdef __INT_LEAST16_MAX__ typedef __INT_LEAST16_TYPE__ yytype_int16; #elif defined YY_STDINT_H typedef int_least16_t yytype_int16; #else typedef short yytype_int16; #endif /* Work around bug in HP-UX 11.23, which defines these macros incorrectly for preprocessor constants. This workaround can likely be removed in 2023, as HPE has promised support for HP-UX 11.23 (aka HP-UX 11i v2) only through the end of 2022; see Table 2 of . */ #ifdef __hpux # undef UINT_LEAST8_MAX # undef UINT_LEAST16_MAX # define UINT_LEAST8_MAX 255 # define UINT_LEAST16_MAX 65535 #endif #if defined __UINT_LEAST8_MAX__ && __UINT_LEAST8_MAX__ <= __INT_MAX__ typedef __UINT_LEAST8_TYPE__ yytype_uint8; #elif (!defined __UINT_LEAST8_MAX__ && defined YY_STDINT_H \ && UINT_LEAST8_MAX <= INT_MAX) typedef uint_least8_t yytype_uint8; #elif !defined __UINT_LEAST8_MAX__ && UCHAR_MAX <= INT_MAX typedef unsigned char yytype_uint8; #else typedef short yytype_uint8; #endif #if defined __UINT_LEAST16_MAX__ && __UINT_LEAST16_MAX__ <= __INT_MAX__ typedef __UINT_LEAST16_TYPE__ yytype_uint16; #elif (!defined __UINT_LEAST16_MAX__ && defined YY_STDINT_H \ && UINT_LEAST16_MAX <= INT_MAX) typedef uint_least16_t yytype_uint16; #elif !defined __UINT_LEAST16_MAX__ && USHRT_MAX <= INT_MAX typedef unsigned short yytype_uint16; #else typedef int yytype_uint16; #endif #ifndef YYPTRDIFF_T # if defined __PTRDIFF_TYPE__ && defined __PTRDIFF_MAX__ # define YYPTRDIFF_T __PTRDIFF_TYPE__ # define YYPTRDIFF_MAXIMUM __PTRDIFF_MAX__ # elif defined PTRDIFF_MAX # ifndef ptrdiff_t # include /* INFRINGES ON USER NAME SPACE */ # endif # define YYPTRDIFF_T ptrdiff_t # define YYPTRDIFF_MAXIMUM PTRDIFF_MAX # else # define YYPTRDIFF_T long # define YYPTRDIFF_MAXIMUM LONG_MAX # endif #endif #ifndef YYSIZE_T # ifdef __SIZE_TYPE__ # define YYSIZE_T __SIZE_TYPE__ # elif defined size_t # define YYSIZE_T size_t # elif defined __STDC_VERSION__ && 199901 <= __STDC_VERSION__ # include /* INFRINGES ON USER NAME SPACE */ # define YYSIZE_T size_t # else # define YYSIZE_T unsigned # endif #endif #define YYSIZE_MAXIMUM \ YY_CAST (YYPTRDIFF_T, \ (YYPTRDIFF_MAXIMUM < YY_CAST (YYSIZE_T, -1) \ ? YYPTRDIFF_MAXIMUM \ : YY_CAST (YYSIZE_T, -1))) #define YYSIZEOF(X) YY_CAST (YYPTRDIFF_T, sizeof (X)) /* Stored state numbers (used for stacks). */ typedef yytype_int16 yy_state_t; /* State numbers in computations. */ typedef int yy_state_fast_t; #ifndef YY_ # if defined YYENABLE_NLS && YYENABLE_NLS # if ENABLE_NLS # include /* INFRINGES ON USER NAME SPACE */ # define YY_(Msgid) dgettext ("bison-runtime", Msgid) # endif # endif # ifndef YY_ # define YY_(Msgid) Msgid # endif #endif #ifndef YY_ATTRIBUTE_PURE # if defined __GNUC__ && 2 < __GNUC__ + (96 <= __GNUC_MINOR__) # define YY_ATTRIBUTE_PURE __attribute__ ((__pure__)) # else # define YY_ATTRIBUTE_PURE # endif #endif #ifndef YY_ATTRIBUTE_UNUSED # if defined __GNUC__ && 2 < __GNUC__ + (7 <= __GNUC_MINOR__) # define YY_ATTRIBUTE_UNUSED __attribute__ ((__unused__)) # else # define YY_ATTRIBUTE_UNUSED # endif #endif /* Suppress unused-variable warnings by "using" E. */ #if ! defined lint || defined __GNUC__ # define YY_USE(E) ((void) (E)) #else # define YY_USE(E) /* empty */ #endif /* Suppress an incorrect diagnostic about yylval being uninitialized. */ #if defined __GNUC__ && ! defined __ICC && 406 <= __GNUC__ * 100 + __GNUC_MINOR__ # if __GNUC__ * 100 + __GNUC_MINOR__ < 407 # define YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN \ _Pragma ("GCC diagnostic push") \ _Pragma ("GCC diagnostic ignored \"-Wuninitialized\"") # else # define YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN \ _Pragma ("GCC diagnostic push") \ _Pragma ("GCC diagnostic ignored \"-Wuninitialized\"") \ _Pragma ("GCC diagnostic ignored \"-Wmaybe-uninitialized\"") # endif # define YY_IGNORE_MAYBE_UNINITIALIZED_END \ _Pragma ("GCC diagnostic pop") #else # define YY_INITIAL_VALUE(Value) Value #endif #ifndef YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN # define YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN # define YY_IGNORE_MAYBE_UNINITIALIZED_END #endif #ifndef YY_INITIAL_VALUE # define YY_INITIAL_VALUE(Value) /* Nothing. */ #endif #if defined __cplusplus && defined __GNUC__ && ! defined __ICC && 6 <= __GNUC__ # define YY_IGNORE_USELESS_CAST_BEGIN \ _Pragma ("GCC diagnostic push") \ _Pragma ("GCC diagnostic ignored \"-Wuseless-cast\"") # define YY_IGNORE_USELESS_CAST_END \ _Pragma ("GCC diagnostic pop") #endif #ifndef YY_IGNORE_USELESS_CAST_BEGIN # define YY_IGNORE_USELESS_CAST_BEGIN # define YY_IGNORE_USELESS_CAST_END #endif #define YY_ASSERT(E) ((void) (0 && (E))) #if !defined yyoverflow /* The parser invokes alloca or malloc; define the necessary symbols. */ # ifdef YYSTACK_USE_ALLOCA # if YYSTACK_USE_ALLOCA # ifdef __GNUC__ # define YYSTACK_ALLOC __builtin_alloca # elif defined __BUILTIN_VA_ARG_INCR # include /* INFRINGES ON USER NAME SPACE */ # elif defined _AIX # define YYSTACK_ALLOC __alloca # elif defined _MSC_VER # include /* INFRINGES ON USER NAME SPACE */ # define alloca _alloca # else # define YYSTACK_ALLOC alloca # if ! defined _ALLOCA_H && ! defined EXIT_SUCCESS # include /* INFRINGES ON USER NAME SPACE */ /* Use EXIT_SUCCESS as a witness for stdlib.h. */ # ifndef EXIT_SUCCESS # define EXIT_SUCCESS 0 # endif # endif # endif # endif # endif # ifdef YYSTACK_ALLOC /* Pacify GCC's 'empty if-body' warning. */ # define YYSTACK_FREE(Ptr) do { /* empty */; } while (0) # ifndef YYSTACK_ALLOC_MAXIMUM /* The OS might guarantee only one guard page at the bottom of the stack, and a page size can be as small as 4096 bytes. So we cannot safely invoke alloca (N) if N exceeds 4096. Use a slightly smaller number to allow for a few compiler-allocated temporary stack slots. */ # define YYSTACK_ALLOC_MAXIMUM 4032 /* reasonable circa 2006 */ # endif # else # define YYSTACK_ALLOC YYMALLOC # define YYSTACK_FREE YYFREE # ifndef YYSTACK_ALLOC_MAXIMUM # define YYSTACK_ALLOC_MAXIMUM YYSIZE_MAXIMUM # endif # if (defined __cplusplus && ! defined EXIT_SUCCESS \ && ! ((defined YYMALLOC || defined malloc) \ && (defined YYFREE || defined free))) # include /* INFRINGES ON USER NAME SPACE */ # ifndef EXIT_SUCCESS # define EXIT_SUCCESS 0 # endif # endif # ifndef YYMALLOC # define YYMALLOC malloc # if ! defined malloc && ! defined EXIT_SUCCESS void *malloc (YYSIZE_T); /* INFRINGES ON USER NAME SPACE */ # endif # endif # ifndef YYFREE # define YYFREE free # if ! defined free && ! defined EXIT_SUCCESS void free (void *); /* INFRINGES ON USER NAME SPACE */ # endif # endif # endif #endif /* !defined yyoverflow */ #if (! defined yyoverflow \ && (! defined __cplusplus \ || (defined YYSTYPE_IS_TRIVIAL && YYSTYPE_IS_TRIVIAL))) /* A type that is properly aligned for any stack member. */ union yyalloc { yy_state_t yyss_alloc; YYSTYPE yyvs_alloc; }; /* The size of the maximum gap between one aligned stack and the next. */ # define YYSTACK_GAP_MAXIMUM (YYSIZEOF (union yyalloc) - 1) /* The size of an array large to enough to hold all stacks, each with N elements. */ # define YYSTACK_BYTES(N) \ ((N) * (YYSIZEOF (yy_state_t) + YYSIZEOF (YYSTYPE)) \ + YYSTACK_GAP_MAXIMUM) # define YYCOPY_NEEDED 1 /* Relocate STACK from its old location to the new one. The local variables YYSIZE and YYSTACKSIZE give the old and new number of elements in the stack, and YYPTR gives the new location of the stack. Advance YYPTR to a properly aligned location for the next stack. */ # define YYSTACK_RELOCATE(Stack_alloc, Stack) \ do \ { \ YYPTRDIFF_T yynewbytes; \ YYCOPY (&yyptr->Stack_alloc, Stack, yysize); \ Stack = &yyptr->Stack_alloc; \ yynewbytes = yystacksize * YYSIZEOF (*Stack) + YYSTACK_GAP_MAXIMUM; \ yyptr += yynewbytes / YYSIZEOF (*yyptr); \ } \ while (0) #endif #if defined YYCOPY_NEEDED && YYCOPY_NEEDED /* Copy COUNT objects from SRC to DST. The source and destination do not overlap. */ # ifndef YYCOPY # if defined __GNUC__ && 1 < __GNUC__ # define YYCOPY(Dst, Src, Count) \ __builtin_memcpy (Dst, Src, YY_CAST (YYSIZE_T, (Count)) * sizeof (*(Src))) # else # define YYCOPY(Dst, Src, Count) \ do \ { \ YYPTRDIFF_T yyi; \ for (yyi = 0; yyi < (Count); yyi++) \ (Dst)[yyi] = (Src)[yyi]; \ } \ while (0) # endif # endif #endif /* !YYCOPY_NEEDED */ /* YYFINAL -- State number of the termination state. */ #define YYFINAL 213 /* YYLAST -- Last index in YYTABLE. */ #define YYLAST 80112 /* YYNTOKENS -- Number of terminals. */ #define YYNTOKENS 343 /* YYNNTS -- Number of nonterminals. */ #define YYNNTS 542 /* YYNRULES -- Number of rules. */ #define YYNRULES 3131 /* YYNSTATES -- Number of states. */ #define YYNSTATES 5451 /* YYMAXUTOK -- Last valid token kind. */ #define YYMAXUTOK 569 /* YYTRANSLATE(TOKEN-NUM) -- Symbol number corresponding to TOKEN-NUM as returned by yylex, with out-of-bounds checking. */ #define YYTRANSLATE(YYX) \ (0 <= (YYX) && (YYX) <= YYMAXUTOK \ ? YY_CAST (yysymbol_kind_t, yytranslate[YYX]) \ : YYSYMBOL_YYUNDEF) /* YYTRANSLATE[TOKEN-NUM] -- Symbol number corresponding to TOKEN-NUM as returned by yylex. */ static const yytype_int16 yytranslate[] = { 0, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 18, 2, 19, 342, 20, 21, 2, 22, 23, 24, 25, 26, 27, 28, 29, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 30, 31, 32, 33, 34, 35, 36, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 37, 2, 38, 39, 341, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 40, 41, 42, 43, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214, 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228, 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242, 243, 244, 245, 246, 247, 248, 249, 250, 251, 252, 253, 254, 255, 256, 257, 258, 259, 260, 261, 262, 263, 264, 265, 266, 267, 268, 269, 270, 271, 272, 273, 274, 275, 276, 277, 278, 279, 280, 281, 282, 283, 284, 285, 286, 287, 288, 289, 290, 291, 292, 293, 294, 295, 296, 297, 298, 299, 300, 301, 302, 303, 304, 305, 306, 307, 308, 309, 310, 311, 312, 313, 314, 315, 316, 317, 318, 319, 320, 321, 322, 323, 324, 325, 326, 327, 328, 329, 330, 331, 332, 333, 334, 335, 336, 337, 338, 339, 340 }; #if YYDEBUG /* YYRLINE[YYN] -- Source line where rule number YYN was defined. */ static const yytype_int16 yyrline[] = { 0, 800, 800, 803, 810, 812, 816, 817, 821, 823, 824, 825, 826, 827, 829, 833, 834, 835, 842, 849, 855, 856, 860, 861, 865, 866, 867, 868, 872, 873, 874, 875, 876, 877, 878, 879, 881, 882, 883, 884, 885, 886, 890, 891, 895, 899, 900, 904, 910, 911, 915, 916, 925, 930, 937, 944, 945, 949, 950, 952, 956, 957, 962, 962, 967, 968, 973, 974, 978, 981, 982, 982, 986, 987, 997, 998, 1001, 1003, 1006, 1036, 1038, 1040, 1042, 1044, 1047, 1049, 1051, 1053, 1055, 1058, 1060, 1062, 1064, 1066, 1069, 1073, 1076, 1077, 1078, 1082, 1083, 1087, 1088, 1092, 1093, 1101, 1105, 1109, 1115, 1116, 1120, 1121, 1125, 1127, 1128, 1129, 1132, 1133, 1135, 1143, 1144, 1152, 1156, 1157, 1161, 1162, 1166, 1167, 1168, 1169, 1171, 1176, 1180, 1185, 1192, 1193, 1197, 1198, 1202, 1203, 1207, 1208, 1209, 1210, 1211, 1212, 1213, 1217, 1218, 1219, 1220, 1224, 1225, 1226, 1230, 1234, 1235, 1239, 1239, 1246, 1252, 1253, 1262, 1264, 1265, 1266, 1269, 1274, 1275, 1276, 1280, 1281, 1288, 1292, 1293, 1297, 1302, 1310, 1314, 1315, 1316, 1320, 1321, 1322, 1327, 1328, 1330, 1331, 1335, 1339, 1340, 1344, 1348, 1349, 1350, 1357, 1358, 1359, 1360, 1364, 1365, 1366, 1367, 1368, 1369, 1370, 1371, 1372, 1373, 1374, 1378, 1382, 1387, 1388, 1389, 1390, 1391, 1396, 1397, 1398, 1399, 1400, 1411, 1411, 1412, 1412, 1413, 1413, 1414, 1414, 1424, 1424, 1425, 1425, 1429, 1430, 1431, 1432, 1433, 1434, 1438, 1439, 1440, 1444, 1445, 1446, 1450, 1451, 1455, 1456, 1463, 1468, 1469, 1470, 1471, 1476, 1477, 1478, 1481, 1487, 1490, 1492, 1497, 1498, 1499, 1500, 1500, 1503, 1503, 1506, 1507, 1508, 1514, 1516, 1523, 1524, 1533, 1539, 1540, 1544, 1545, 1546, 1550, 1554, 1555, 1560, 1559, 1567, 1568, 1572, 1574, 1576, 1586, 1590, 1591, 1595, 1597, 1602, 1603, 1604, 1608, 1609, 1613, 1614, 1619, 1621, 1625, 1626, 1627, 1634, 1635, 1639, 1640, 1644, 1645, 1649, 1650, 1658, 1662, 1665, 1666, 1668, 1669, 1674, 1675, 1680, 1681, 1685, 1689, 1690, 1691, 1695, 1696, 1700, 1708, 1709, 1710, 1716, 1720, 1721, 1722, 1730, 1735, 1740, 1741, 1742, 1745, 1746, 1747, 1758, 1759, 1760, 1763, 1770, 1773, 1775, 1780, 1781, 1786, 1787, 1788, 1793, 1798, 1800, 1803, 1804, 1805, 1806, 1807, 1808, 1815, 1816, 1820, 1821, 1825, 1826, 1830, 1831, 1832, 1833, 1834, 1835, 1836, 1837, 1842, 1846, 1848, 1852, 1856, 1857, 1858, 1859, 1861, 1862, 1863, 1865, 1866, 1867, 1868, 1870, 1874, 1878, 1882, 1886, 1887, 1888, 1889, 1890, 1894, 1895, 1901, 1902, 1906, 1907, 1911, 1918, 1930, 1931, 1935, 1935, 1940, 1941, 1945, 1945, 1949, 1950, 1951, 1952, 1953, 1954, 1958, 1958, 1958, 1958, 1958, 1958, 1962, 1963, 1967, 1967, 1971, 1972, 1976, 1976, 1981, 1983, 1990, 1995, 1996, 1998, 1999, 2003, 2003, 2003, 2003, 2007, 2012, 2016, 2017, 2020, 2022, 2023, 2024, 2025, 2026, 2027, 2028, 2029, 2030, 2031, 2032, 2033, 2035, 2036, 2037, 2038, 2042, 2043, 2047, 2047, 2051, 2052, 2053, 2057, 2057, 2057, 2064, 2065, 2069, 2073, 2074, 2075, 2076, 2080, 2081, 2085, 2086, 2087, 2088, 2093, 2094, 2095, 2096, 2100, 2104, 2105, 2109, 2110, 2114, 2115, 2116, 2120, 2121, 2125, 2129, 2130, 2134, 2135, 2139, 2140, 2144, 2145, 2152, 2156, 2157, 2161, 2162, 2166, 2167, 2176, 2179, 2184, 2185, 2189, 2190, 2194, 2207, 2207, 2207, 2210, 2210, 2210, 2215, 2220, 2224, 2225, 2229, 2234, 2238, 2239, 2243, 2251, 2252, 2256, 2257, 2261, 2262, 2266, 2267, 2271, 2271, 2275, 2275, 2276, 2280, 2281, 2282, 2283, 2284, 2287, 2288, 2289, 2291, 2293, 2295, 2296, 2297, 2304, 2305, 2306, 2308, 2321, 2322, 2327, 2328, 2329, 2330, 2331, 2332, 2339, 2344, 2345, 2349, 2350, 2354, 2355, 2359, 2360, 2365, 2366, 2367, 2371, 2372, 2376, 2377, 2378, 2379, 2380, 2384, 2385, 2389, 2391, 2393, 2398, 2403, 2404, 2407, 2410, 2411, 2412, 2413, 2416, 2417, 2418, 2421, 2422, 2424, 2429, 2430, 2433, 2434, 2435, 2436, 2441, 2444, 2445, 2447, 2448, 2450, 2451, 2452, 2454, 2456, 2458, 2460, 2463, 2464, 2465, 2466, 2468, 2470, 2471, 2472, 2474, 2477, 2478, 2479, 2482, 2487, 2489, 2492, 2494, 2496, 2500, 2501, 2502, 2503, 2504, 2505, 2506, 2507, 2508, 2509, 2510, 2511, 2515, 2515, 2515, 2515, 2515, 2515, 2515, 2515, 2515, 2515, 2515, 2515, 2520, 2521, 2523, 2524, 2528, 2528, 2528, 2528, 2532, 2532, 2532, 2532, 2536, 2536, 2536, 2536, 2540, 2540, 2540, 2540, 2544, 2544, 2544, 2544, 2549, 2550, 2552, 2556, 2557, 2564, 2565, 2566, 2567, 2571, 2572, 2573, 2577, 2578, 2579, 2583, 2588, 2592, 2593, 2597, 2598, 2602, 2603, 2604, 2605, 2606, 2607, 2611, 2612, 2613, 2614, 2615, 2616, 2620, 2621, 2625, 2629, 2630, 2634, 2635, 2639, 2640, 2644, 2645, 2648, 2653, 2654, 2658, 2659, 2660, 2664, 2665, 2666, 2667, 2673, 2675, 2676, 2687, 2691, 2693, 2699, 2701, 2705, 2706, 2711, 2713, 2715, 2719, 2720, 2724, 2725, 2729, 2731, 2733, 2735, 2736, 2740, 2741, 2757, 2758, 2759, 2764, 2765, 2766, 2772, 2777, 2778, 2779, 2785, 2789, 2793, 2795, 2798, 2799, 2800, 2801, 2802, 2803, 2804, 2805, 2810, 2811, 2812, 2813, 2814, 2815, 2816, 2817, 2823, 2829, 2830, 2834, 2837, 2845, 2846, 2850, 2851, 2855, 2858, 2861, 2864, 2872, 2873, 2877, 2878, 2882, 2883, 2887, 2888, 2893, 2894, 2898, 2906, 2909, 2912, 2915, 2918, 2924, 2927, 2930, 2937, 2938, 2939, 2943, 2944, 2948, 2949, 2953, 2954, 2955, 2956, 2960, 2961, 2965, 2966, 2970, 2971, 2976, 2976, 2981, 2982, 2987, 2988, 2989, 2993, 2994, 2995, 2996, 2997, 2999, 3000, 3001, 3002, 3003, 3004, 3008, 3012, 3014, 3019, 3020, 3033, 3034, 3040, 3041, 3045, 3046, 3047, 3048, 3052, 3053, 3054, 3055, 3059, 3060, 3064, 3065, 3066, 3071, 3076, 3077, 3078, 3079, 3080, 3081, 3082, 3083, 3084, 3085, 3086, 3087, 3088, 3089, 3090, 3094, 3095, 3110, 3117, 3118, 3119, 3120, 3121, 3122, 3123, 3124, 3125, 3126, 3129, 3133, 3134, 3135, 3136, 3137, 3138, 3139, 3140, 3141, 3142, 3143, 3144, 3147, 3148, 3149, 3150, 3151, 3152, 3153, 3154, 3155, 3156, 3157, 3158, 3159, 3160, 3161, 3162, 3163, 3164, 3165, 3166, 3167, 3168, 3169, 3170, 3171, 3172, 3173, 3179, 3183, 3186, 3189, 3192, 3193, 3198, 3199, 3200, 3201, 3206, 3212, 3214, 3216, 3218, 3220, 3223, 3225, 3227, 3233, 3234, 3236, 3239, 3242, 3251, 3252, 3259, 3265, 3270, 3271, 3275, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3279, 3287, 3288, 3294, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3300, 3305, 3308, 3315, 3317, 3319, 3320, 3321, 3322, 3326, 3327, 3328, 3330, 3334, 3334, 3334, 3334, 3334, 3334, 3334, 3334, 3334, 3334, 3338, 3338, 3338, 3338, 3338, 3338, 3338, 3338, 3338, 3338, 3342, 3342, 3342, 3342, 3342, 3342, 3342, 3342, 3342, 3342, 3346, 3346, 3346, 3346, 3346, 3346, 3346, 3346, 3346, 3346, 3350, 3350, 3350, 3350, 3350, 3350, 3350, 3350, 3350, 3350, 3354, 3358, 3369, 3370, 3371, 3372, 3373, 3375, 3377, 3381, 3381, 3381, 3381, 3381, 3381, 3381, 3385, 3385, 3385, 3385, 3385, 3385, 3385, 3389, 3389, 3389, 3389, 3389, 3389, 3389, 3393, 3393, 3393, 3393, 3393, 3393, 3393, 3397, 3397, 3397, 3397, 3397, 3397, 3397, 3402, 3404, 3406, 3410, 3411, 3413, 3415, 3421, 3422, 3426, 3427, 3428, 3433, 3434, 3435, 3440, 3441, 3442, 3446, 3447, 3451, 3452, 3456, 3457, 3461, 3462, 3466, 3467, 3471, 3472, 3476, 3477, 3481, 3482, 3486, 3487, 3498, 3499, 3500, 3501, 3505, 3506, 3513, 3517, 3518, 3523, 3524, 3525, 3526, 3527, 3541, 3542, 3543, 3544, 3545, 3546, 3547, 3548, 3549, 3554, 3555, 3556, 3560, 3561, 3565, 3566, 3573, 3577, 3578, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3582, 3583, 3584, 3591, 3592, 3596, 3597, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 3601, 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3789, 3793, 3794, 3795, 3799, 3800, 3801, 3805, 3806, 3807, 3808, 3812, 3813, 3817, 3818, 3822, 3823, 3827, 3828, 3829, 3830, 3831, 3832, 3833, 3837, 3838, 3839, 3846, 3847, 3848, 3852, 3853, 3857, 3858, 3862, 3863, 3866, 3870, 3871, 3876, 3878, 3880, 3884, 3886, 3891, 3893, 3895, 3899, 3903, 3904, 3911, 3913, 3915, 3917, 3920, 3921, 3923, 3927, 3933, 3938, 3939, 3939, 3944, 3945, 3955, 3960, 3962, 3963, 3964, 3965, 3966, 3970, 3971, 3976, 3977, 3978, 3982, 3985, 3989, 3990, 3994, 4000, 4011, 4015, 4016, 4022, 4025, 4030, 4031, 4032, 4033, 4039, 4040, 4045, 4046, 4051, 4052, 4057, 4060, 4064, 4065, 4066, 4067, 4071, 4072, 4079, 4080, 4081, 4082, 4099, 4102, 4102, 4102, 4102, 4102, 4102, 4102, 4102, 4102, 4102, 4102, 4102, 4102, 4102, 4102, 4102, 4102, 4102, 4102, 4102, 4102, 4102, 4102, 4102, 4102, 4102, 4102, 4102, 4102, 4105, 4105, 4105, 4105, 4105, 4105, 4105, 4105, 4105, 4105, 4105, 4105, 4105, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4108, 4119, 4120, 4121, 4128, 4129, 4133, 4135, 4136, 4137, 4138, 4139, 4140, 4141, 4142, 4143, 4144, 4145, 4146, 4147, 4148, 4149, 4150, 4151, 4153, 4154, 4155, 4156, 4157, 4165, 4168, 4168, 4168, 4168, 4168, 4168, 4168, 4168, 4168, 4168, 4168, 4168, 4168, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4171, 4182, 4183, 4188, 4199, 4200, 4203, 4204, 4206, 4208, 4209, 4210, 4213, 4215, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4218, 4223, 4224, 4225, 4231, 4232, 4233, 4237, 4238, 4246, 4251, 4252, 4253, 4255, 4257, 4261, 4262, 4267, 4272, 4279, 4284, 4288, 4292, 4300, 4304, 4311, 4317, 4321, 4322, 4326, 4327, 4332, 4333, 4334, 4335, 4340, 4344, 4346, 4347, 4348, 4349, 4350, 4352, 4356, 4357, 4361, 4362, 4363, 4367, 4368, 4373, 4375, 4376, 4377, 4378, 4382, 4383, 4385, 4387, 4391, 4392, 4393, 4397, 4398, 4399, 4403, 4404, 4408, 4409, 4413, 4415, 4419, 4420, 4421, 4422, 4426, 4430, 4431, 4435, 4436, 4440, 4441, 4445, 4446, 4450, 4454, 4456, 4457, 4461, 4462, 4467, 4468, 4472, 4473, 4477, 4482, 4483, 4484, 4487, 4488, 4489, 4492, 4493, 4494, 4503, 4504, 4508, 4509, 4510, 4511, 4515, 4516, 4520, 4521, 4526, 4528, 4529, 4536, 4537, 4541, 4542, 4546, 4550, 4551, 4552, 4553, 4557, 4558, 4562, 4563, 4564, 4568, 4569, 4570, 4574, 4575, 4576, 4580, 4581, 4585, 4586, 4590, 4591, 4595, 4596, 4600, 4601, 4603, 4604, 4606, 4608, 4612, 4613, 4617, 4618, 4622, 4623, 4627, 4628, 4629, 4636, 4642, 4649, 4653, 4654, 4658, 4659, 4663, 4664, 4666, 4667, 4668, 4669, 4670, 4674, 4675, 4676, 4677, 4678, 4679, 4680, 4681, 4682, 4683, 4684, 4685, 4690, 4691, 4692, 4694, 4701, 4711, 4718, 4722, 4728, 4729, 4735, 4736, 4737, 4742, 4743, 4748, 4749, 4758, 4762, 4769, 4774, 4781, 4785, 4791, 4792, 4798, 4804, 4805, 4812, 4812, 4814, 4814, 4816, 4816, 4823, 4824, 4828, 4829, 4833, 4834, 4835, 4837, 4838, 4839, 4840, 4841, 4842, 4844, 4848, 4849, 4851, 4854, 4862, 4863, 4864, 4870, 4871, 4875, 4876, 4881, 4883, 4885, 4887, 4889, 4891, 4899, 4901, 4902, 4903, 4907, 4911, 4912, 4916, 4917, 4921, 4922, 4927, 4931, 4932, 4936, 4938, 4941, 4945, 4946, 4948, 4950, 4954, 4955, 4959, 4960, 4964, 4965, 4966, 4970, 4974, 4975 }; #endif /** Accessing symbol of state STATE. */ #define YY_ACCESSING_SYMBOL(State) YY_CAST (yysymbol_kind_t, yystos[State]) #if YYDEBUG || 1 /* The user-facing name of the symbol whose (internal) number is YYSYMBOL. No bounds checking. */ static const char *yysymbol_name (yysymbol_kind_t yysymbol) YY_ATTRIBUTE_UNUSED; /* YYTNAME[SYMBOL-NUM] -- String name of the symbol SYMBOL-NUM. First, the terminals, then, starting at YYNTOKENS, nonterminals. */ static const char *const yytname[] = { "\"end of file\"", "error", "\"invalid token\"", "\"FLOATING-POINT NUMBER\"", "\"IDENTIFIER\"", "\"IDENTIFIER-in-lex\"", "\"PACKAGE-IDENTIFIER\"", "\"TYPE-IDENTIFIER\"", "\"INTEGER NUMBER\"", "\"TIME NUMBER\"", "\"STRING\"", "\"STRING-ignored\"", "\"TIMING SPEC ELEMENT\"", "\"GATE keyword\"", "\"CONFIG keyword (cell/use/design/etc)\"", "\"OPERATOR\"", "\"STRENGTH keyword (strong1/etc)\"", "\"SYSCALL\"", "'!'", "'#'", "'%'", "'&'", "'('", "')'", "'*'", "'+'", "','", "'-'", "'.'", "'/'", "':'", "';'", "'<'", "'='", "'>'", "'?'", "'@'", "'['", "']'", "'^'", "'{'", "'|'", "'}'", "'~'", "\"accept_on\"", "\"alias\"", "\"always\"", "\"and\"", "\"assert\"", "\"assign\"", "\"assume\"", "\"automatic\"", "\"before\"", "\"begin\"", "\"bind\"", "\"bins\"", "\"binsof\"", "\"bit\"", "\"break\"", "\"buf\"", "\"byte\"", "\"case\"", "\"casex\"", "\"casez\"", "\"chandle\"", "\"checker\"", "\"class\"", "\"clock\"", "\"clocking\"", "\"constraint\"", "\"const\"", "\"const-in-lex\"", "\"const-then-local\"", "\"const-then-ref\"", "\"context\"", "\"continue\"", "\"cover\"", "\"covergroup\"", "\"coverpoint\"", "\"cross\"", "\"deassign\"", "\"default\"", "\"defparam\"", "\"disable\"", "\"dist\"", "\"do\"", "\"edge\"", "\"else\"", "\"end\"", "\"endcase\"", "\"endchecker\"", "\"endclass\"", "\"endclocking\"", "\"endfunction\"", "\"endgenerate\"", "\"endgroup\"", "\"endinterface\"", "\"endmodule\"", "\"endpackage\"", "\"endprogram\"", "\"endproperty\"", "\"endsequence\"", "\"endspecify\"", "\"endtable\"", "\"endtask\"", "\"enum\"", "\"event\"", "\"eventually\"", "\"expect\"", "\"export\"", "\"extends\"", "\"extern\"", "\"final\"", "\"first_match\"", "\"for\"", "\"force\"", "\"foreach\"", "\"forever\"", "\"fork\"", "\"forkjoin\"", "\"function\"", "\"function-in-lex\"", "\"function-is-pure-virtual\"", "\"generate\"", "\"genvar\"", "\"global-then-clocking\"", "\"global-in-lex\"", "\"if\"", "\"iff\"", "\"ignore_bins\"", "\"illegal_bins\"", "\"implements\"", "\"implies\"", "\"import\"", "\"initial\"", "\"inout\"", "\"input\"", "\"inside\"", "\"int\"", "\"integer\"", "\"interconnect\"", "\"interface\"", "\"intersect\"", "\"join\"", "\"let\"", "\"localparam\"", "\"local-then-::\"", "\"local\"", "\"local-in-lex\"", "\"logic\"", "\"longint\"", "\"matches\"", "\"modport\"", "\"module\"", "\"nand\"", "\"negedge\"", "\"nettype\"", "\"new\"", "\"new-in-lex\"", "\"new-then-paren\"", "\"nexttime\"", "\"nor\"", "\"not\"", "\"null\"", "\"or\"", "\"output\"", "\"package\"", "\"packed\"", "\"parameter\"", "\"posedge\"", "\"priority\"", "\"program\"", "\"property\"", "\"protected\"", "\"pure\"", "\"rand\"", "\"randc\"", "\"randcase\"", "\"randsequence\"", "\"real\"", "\"realtime\"", "\"ref\"", "\"reg\"", "\"reject_on\"", "\"release\"", "\"repeat\"", "\"restrict\"", "\"return\"", "\"scalared\"", "\"sequence\"", "\"shortint\"", "\"shortreal\"", "\"signed\"", "\"soft\"", "\"solve\"", "\"specify\"", "\"specparam\"", "\"static-then-constraint\"", "\"static\"", "\"static-in-lex\"", "\"string\"", "\"strong\"", "\"struct\"", "\"super\"", "\"supply0\"", "\"supply1\"", "\"sync_accept_on\"", "\"sync_reject_on\"", "\"s_always\"", "\"s_eventually\"", "\"s_nexttime\"", "\"s_until\"", "\"s_until_with\"", "\"table\"", "\"tagged\"", "\"task\"", "\"task-in-lex\"", "\"task-is-pure-virtual\"", "\"this\"", "\"throughout\"", "\"time\"", "\"timeprecision\"", "\"timeunit\"", "\"tri\"", "\"tri0\"", "\"tri1\"", "\"triand\"", "\"trior\"", "\"trireg\"", "\"type\"", "\"typedef\"", "\"union\"", "\"unique\"", "\"unique0\"", "\"unsigned\"", "\"until\"", "\"until_with\"", "\"untyped\"", "\"var\"", "\"vectored\"", "\"virtual-then-class\"", "\"virtual\"", "\"virtual-then-interface\"", "\"virtual-in-lex\"", "\"virtual-then-identifier\"", "\"void\"", "\"wait\"", "\"wait_order\"", "\"wand\"", "\"weak\"", "\"while\"", "\"wildcard\"", "\"wire\"", "\"within\"", "\"with-then-[\"", "\"with-then-{\"", "\"with\"", "\"with-in-lex\"", "\"with-then-(\"", "\"wor\"", "\"xnor\"", "\"xor\"", "\"$error\"", "\"$fatal\"", "\"$info\"", "\"$root\"", "\"$unit\"", "\"$warning\"", "\"'\"", "\"'{\"", "\"||\"", "\"&&\"", "\"~|\"", "\"^~\"", "\"~&\"", "\"==\"", "\"!=\"", "\"===\"", "\"!==\"", "\"==?\"", "\"!=?\"", "\">=\"", "\"<=\"", "\"<=-ignored\"", "\"<<\"", "\">>\"", "\">>>\"", "\"**\"", "\"(-ignored\"", "\"(-for-strength\"", "\"<->\"", "\"+:\"", "\"-:\"", "\"->\"", "\"->>\"", "\"=>\"", "\"*>\"", "\"&&&\"", "\"##\"", "\"#-#\"", "\"#=#\"", "\".*\"", "\"@@\"", "\"::\"", "\":=\"", "\":/\"", "\"|->\"", "\"|=>\"", "\"[*\"", "\"[=\"", "\"[->\"", "\"[+]\"", "\"++\"", "\"--\"", "\"+=\"", "\"-=\"", "\"*=\"", "\"/=\"", "\"%=\"", "\"&=\"", "\"|=\"", "\"^=\"", "\"<<=\"", "\">>=\"", "\">>>=\"", "prUNARYARITH", "prREDUCTION", "prNEGATION", "prEVENTBEGIN", "prTAGGED", "prSEQ_CLOCKING", "prPOUNDPOUND_MULTI", "prLOWER_THAN_ELSE", "\"+\"", "\"-\"", "\"*\"", "\"/\"", "\"%\"", "\"<\"", "\">\"", "\"=\"", "'_'", "'$'", "$accept", "statePushVlg", "statePop", "source_text", "descriptionList", "description", "timeunits_declaration", "package_declaration", "packageFront", "package_itemListE", "package_itemList", "package_item", "package_or_generate_item_declaration", "package_import_declarationList", "package_import_declaration", "package_import_itemList", "package_import_item", "package_import_itemObj", "package_export_declaration", "module_declaration", "modFront", "importsAndParametersE", "parameter_value_assignmentE", "parameter_port_listE", "$@1", "paramPortDeclOrArgList", "paramPortDeclOrArg", "portsStarE", "$@2", "list_of_portsE", "portE", "portDirNetE", "port_declNetE", "portAssignExprE", "portSig", "interface_declaration", "intFront", "interface_itemListE", "interface_itemList", "interface_item", "interface_or_generate_item", "anonymous_program", "anonymous_program_itemListE", "anonymous_program_itemList", "anonymous_program_item", "program_declaration", "pgmFront", "program_itemListE", "program_itemList", "program_item", "non_port_program_item", "program_generate_item", "extern_tf_declaration", "modport_declaration", "modport_itemList", "modport_item", "$@3", "modport_idFront", "modportPortsDeclList", "modportPortsDecl", "modportSimplePort", "modport_tf_port", "genvar_declaration", "list_of_genvar_identifiers", "genvar_identifierDecl", "local_parameter_declaration", "parameter_declaration", "local_parameter_declarationFront", "parameter_declarationFront", "parameter_port_declarationFront", "net_declaration", "net_declarationFront", "net_declRESET", "net_scalaredE", "net_dataType", "net_type", "varGParamReset", "varLParamReset", "port_direction", "port_directionReset", "port_declaration", "$@4", "$@5", "$@6", "$@7", "tf_port_declaration", "$@8", "$@9", "integer_atom_type", "integer_vector_type", "non_integer_type", "signingE", "signing", "casting_type", "simple_type", "data_typeVar", "data_type", "$@10", "$@11", "data_type_or_void", "var_data_type", "type_reference", "struct_union_memberList", "struct_union_member", "$@12", "list_of_variable_decl_assignments", "variable_decl_assignment", "list_of_tf_variable_identifiers", "tf_variable_identifier", "variable_declExpr", "variable_dimensionListE", "variable_dimensionList", "variable_dimension", "random_qualifierE", "random_qualifier", "taggedE", "packedSigningE", "enumDecl", "enum_base_typeE", "enum_nameList", "enum_name_declaration", "enumNameRangeE", "enumNameStartE", "intnumAsConst", "data_declaration", "class_property", "data_declarationVar", "data_declarationVarClass", "data_declarationVarFront", "data_declarationVarFrontClass", "net_type_declaration", "constE", "implicit_typeE", "assertion_variable_declaration", "type_declaration", "module_itemListE", "module_itemList", "module_item", "non_port_module_item", "module_or_generate_item", "module_common_item", "continuous_assign", "initial_construct", "final_construct", "module_or_generate_item_declaration", "aliasEqList", "bind_directive", "bind_target_instance_list", "bind_target_instance", "bind_instantiation", "generate_region", "c_generate_region", "generate_block", "c_generate_block", "genItemBegin", "c_genItemBegin", "genItemOrBegin", "c_genItemOrBegin", "genItemList", "c_genItemList", "generate_item", "c_generate_item", "conditional_generate_construct", "c_conditional_generate_construct", "loop_generate_construct", "c_loop_generate_construct", "genvar_initialization", "genvar_iteration", "case_generate_itemList", "c_case_generate_itemList", "case_generate_item", "c_case_generate_item", "assignList", "assignOne", "delay_or_event_controlE", "delayE", "delay_control", "delay_value", "delayExpr", "minTypMax", "netSigList", "netSig", "netId", "sigAttrListE", "rangeListE", "rangeList", "regrangeE", "bit_selectE", "anyrange", "packed_dimensionListE", "packed_dimensionList", "packed_dimension", "param_assignment", "list_of_param_assignments", "list_of_defparam_assignments", "defparam_assignment", "etcInst", "$@13", "$@14", "$@15", "$@16", "instName", "mpInstnameList", "mpInstnameParen", "mpInstname", "instnameList", "instnameParen", "instname", "instRangeListE", "instRangeList", "instRange", "cellpinList", "$@17", "cellpinItList", "$@18", "cellpinItemE", "event_control", "event_expression", "senitemEdge", "stmtBlock", "seq_block", "par_block", "seq_blockFront", "par_blockFront", "blockDeclStmtList", "block_item_declarationList", "block_item_declaration", "stmtList", "stmt", "statement_item", "operator_assignment", "foperator_assignment", "inc_or_dec_expression", "finc_or_dec_expression", "sinc_or_dec_expression", "pinc_or_dec_expression", "ev_inc_or_dec_expression", "pev_inc_or_dec_expression", "class_new", "dynamic_array_new", "unique_priorityE", "action_block", "caseStart", "caseAttrE", "case_patternListE", "case_itemListE", "case_insideListE", "case_itemList", "case_inside_itemList", "open_range_list", "open_value_range", "value_range", "covergroup_value_range", "caseCondList", "patternNoExpr", "patternList", "patternOne", "patternMemberList", "patternKey", "assignment_pattern", "for_initialization", "for_initializationItemList", "for_initializationItem", "for_stepE", "for_step", "for_step_assignment", "loop_variables", "funcRef", "task_subroutine_callNoMethod", "function_subroutine_callNoMethod", "system_t_call", "system_f_call", "elaboration_system_task", "property_actual_arg", "task", "task_declaration", "task_prototype", "function", "function_declaration", "function_prototype", "class_constructor_prototype", "method_prototype", "lifetimeE", "lifetime", "taskId", "funcId", "funcIdNew", "tfIdScoped", "tfGuts", "tfGutsPureV", "tfBodyE", "function_data_type", "tf_item_declarationList", "tf_item_declaration", "tf_port_listE", "$@19", "tf_port_listList", "tf_port_item", "tf_port_itemFront", "tf_port_itemDir", "tf_port_itemAssignment", "parenE", "array_methodNoRoot", "method_callWithE", "array_method_nameNoId", "dpi_import_export", "dpi_importLabelE", "dpi_tf_import_propertyE", "overload_declaration", "overload_operator", "overload_proto_formals", "constExpr", "expr", "fexpr", "ev_expr", "exprOkLvalue", "fexprOkLvalue", "sexprOkLvalue", "pexprOkLvalue", "ev_exprOkLvalue", "pev_exprOkLvalue", "exprLvalue", "fexprLvalue", "exprScope", "fexprScope", "sexprScope", "pexprScope", "ev_exprScope", "pev_exprScope", "exprOrDataType", "exprOrDataTypeOrMinTypMax", "cateList", "exprOrDataTypeList", "list_of_argumentsE", "pev_list_of_argumentsE", "argsExprList", "argsExprListE", "pev_argsExprListE", "argsExprOneE", "pev_argsExprOneE", "argsDottedList", "pev_argsDottedList", "argsDotted", "pev_argsDotted", "streaming_concatenation", "stream_concOrExprOrType", "stream_concatenation", "stream_expressionList", "stream_expression", "gateKwd", "strength", "strengthSpecE", "strengthSpec", "combinational_body", "tableJunkList", "tableJunk", "specify_block", "specifyJunkList", "specifyJunk", "specparam_declaration", "junkToSemiList", "junkToSemi", "id", "idAny", "idSVKwd", "variable_lvalue", "variable_lvalueConcList", "variable_lvalueList", "idClassSel", "idClassForeach", "hierarchical_identifierList", "hierarchical_identifierBit", "hierarchical_identifier", "idDotted", "idDottedForeach", "idDottedMore", "idDottedForeachMore", "idArrayed", "idForeach", "strAsInt", "endLabelE", "clocking_declaration", "clockingFront", "clocking_event", "clocking_itemListE", "clocking_itemList", "clocking_item", "default_skew", "clocking_direction", "list_of_clocking_decl_assign", "clocking_decl_assign", "clocking_skewE", "clocking_skew", "cycle_delay", "assertion_item_declaration", "assertion_item", "deferred_immediate_assertion_item", "procedural_assertion_statement", "immediate_assertion_statement", "simple_immediate_assertion_statement", "final_zero", "deferred_immediate_assertion_statement", "expect_property_statement", "concurrent_assertion_item", "concurrent_assertion_statement", "property_declaration", "property_declarationFront", "property_port_listE", "$@20", "property_port_list", "property_port_item", "property_port_itemFront", "property_port_itemAssignment", "property_port_itemDirE", "property_declarationBody", "assertion_variable_declarationList", "sequence_declaration", "sequence_declarationFront", "sequence_port_listE", "property_formal_typeNoDt", "sequence_formal_typeNoDt", "sequence_declarationBody", "property_spec", "property_statement_spec", "property_statement", "property_statementCaseIf", "property_case_itemList", "property_case_item", "pev_expr", "pexpr", "sexpr", "cycle_delay_range", "sequence_match_itemList", "sequence_match_item", "boolean_abbrev", "const_or_range_expression", "constant_range", "cycle_delay_const_range_expression", "let_declaration", "let_declarationFront", "let_port_listE", "covergroup_declaration", "covergroup_declarationFront", "cgexpr", "coverage_spec_or_optionListE", "coverage_spec_or_optionList", "coverage_spec_or_option", "coverage_option", "cover_point", "iffE", "bins_or_empty", "bins_or_optionsList", "bins_or_options", "bins_orBraE", "bins_keyword", "covergroup_range_list", "trans_list", "trans_set", "trans_range_list", "trans_item", "repeat_range", "cover_cross", "list_of_cross_items", "cross_itemList", "cross_item", "cross_body", "cross_body_itemSemiList", "cross_body_item", "bins_selection_or_option", "bins_selection", "select_expression", "bins_expression", "coverage_eventE", "block_event_expression", "block_event_expressionTerm", "hierarchical_btf_identifier", "randsequence_statement", "productionList", "production", "productionFront", "rs_ruleList", "rs_rule", "rs_production_list", "weight_specification", "rs_code_block", "rs_code_blockItemList", "rs_code_blockItem", "rs_prodList", "rs_prod", "production_itemList", "production_item", "rs_case_itemList", "rs_case_item", "checker_declaration", "checkerFront", "checker_port_listE", "checker_or_generate_itemListE", "checker_or_generate_itemList", "checker_or_generate_item", "checker_or_generate_item_declaration", "checker_generate_item", "checker_instantiation", "class_declaration", "classFront", "classVirtualE", "classExtendsE", "classImplementsE", "classImplementsList", "ps_id_etc", "class_scope_id", "class_typeWithoutId", "class_scopeWithoutId", "class_scopeIdFollows", "class_typeOneListColonIdFollows", "class_typeOneList", "class_typeOne", "package_scopeIdFollowsE", "package_scopeIdFollows", "$@21", "$@22", "$@23", "class_itemListE", "class_itemList", "class_item", "class_method", "class_item_qualifier", "memberQualResetListE", "memberQualList", "memberQualOne", "class_constraint", "constraint_block", "constraint_block_itemList", "constraint_block_item", "solve_before_list", "constraint_primary", "constraint_expressionList", "constraint_expression", "constraint_set", "dist_list", "dist_item", "extern_constraint_declaration", "constraintStaticE", YY_NULLPTR }; static const char * yysymbol_name (yysymbol_kind_t yysymbol) { return yytname[yysymbol]; } #endif #define YYPACT_NINF (-4562) #define yypact_value_is_default(Yyn) \ ((Yyn) == YYPACT_NINF) #define YYTABLE_NINF (-3131) #define yytable_value_is_error(Yyn) \ 0 /* YYPACT[STATE-NUM] -- Index in YYTABLE of the portion describing STATE-NUM. */ static const int yypact[] = { 75361, -4562, -4562, -4562, -4562, 1894, -4562, -4562, -4562, 1890, 455, 1890, 5649, -4562, 1213, 904, 226, 226, 819, -4562, -4562, 621, 1890, -4562, -4562, -4562, -4562, 226, 26244, 226, -4562, 688, 1890, -4562, -4562, -4562, 1890, -4562, -4562, -4562, -4562, -4562, 111, 226, 226, -4562, 335, 443, 315, 11855, 487, -4562, 242, 798, -4562, 857, 75610, -4562, -4562, -4562, 79343, -4562, -4562, -4562, -4562, -4562, 240, -4562, 240, -4562, -4562, 240, 838, 872, 798, 798, -4562, 681, 3287, 26249, 27760, 684, 684, -4562, -4562, -4562, -4562, -4562, -4562, -4562, 679, -4562, 692, -4562, -4562, -4562, -4562, 39134, -4562, -4562, -4562, -4562, 918, -4562, 918, -4562, 949, -4562, 247, -4562, 918, -4562, 971, 1018, 1103, -4562, -4562, 1060, 834, -4562, 1134, 1199, 1247, -4562, -4562, -4562, -4562, -4562, -4562, -4562, -4562, -4562, -4562, -4562, -4562, -4562, -4562, -4562, 2474, 1375, -4562, -4562, -4562, -4562, 1268, 1308, 191, 1103, 191, -4562, -4562, -4562, -4562, 39134, -4562, -4562, 1062, -4562, -4562, 684, 684, 1335, 1339, 1396, 1335, 1890, 1174, 1890, 1214, 1173, -4562, 226, 226, 240, 240, 240, 11543, 11543, 415, 1176, 226, 1890, -4562, 1257, 1890, 1436, 798, 1890, 1056, 1890, 1187, 1890, -4562, -4562, 684, 1567, 301, 301, 1635, 1587, 47451, 1890, 5649, 1610, 968, 538, 1890, 1547, -4562, 111, 798, 1682, 1406, -4562, -4562, 2364, 1650, 1693, 1636, 79546, -4562, 1738, 1736, 240, -4562, 1762, -4562, 1762, 1762, -4562, -4562, -4562, 1766, 156, 1766, -4562, -4562, 1433, -4562, 156, -4562, -4562, 684, -4562, -4562, -4562, -4562, -4562, -4562, -4562, -4562, -4562, -4562, -4562, 1522, 315, 1335, 1833, -4562, -4562, 315, -4562, -4562, -4562, -4562, 1335, 1532, 1600, -4562, 156, -4562, 226, -4562, -4562, 1789, -4562, 1857, -4562, 1892, -4562, 354, 1375, 1911, -4562, 1883, -4562, 1918, 1870, 226, 1682, 1103, 137, -4562, 200, -4562, 191, 248, 798, -4562, 1482, -4562, -4562, -4562, -4562, -4562, -4562, -4562, -4562, -4562, -4562, 1956, -4562, -4562, -4562, -4562, 26244, 798, 50721, -4562, 1103, 1703, -4562, -4562, -4562, 1335, 50721, 1335, -4562, 1890, -4562, -4562, 1335, 1342, 929, 1977, 1990, 1736, -4562, 1762, 1762, 1762, -4562, -4562, 301, 1335, 297, 301, 1055, 1055, -4562, 2005, -4562, 1879, 798, 1103, 1096, 1096, -4562, -4562, 1890, -4562, 1890, -4562, -4562, -4562, 798, 1682, 151, 1890, 2014, -4562, 1952, 1187, -4562, -4562, -4562, -4562, -4562, -4562, -4562, -4562, 1055, -4562, 798, 1096, -4562, 2053, -4562, -4562, -4562, -4562, -4562, 2045, 50721, 50721, 50721, 50721, 50721, 1595, 50721, 41500, 50721, 50721, -4562, -4562, -4562, 1828, -4562, 798, -4562, -4562, 2085, 2088, 2089, 2092, 41007, 50721, 50721, 50721, 50721, 50721, 2094, -4562, 715, 1353, 279, 1856, -4562, 1787, -4562, -4562, -4562, 919, -4562, -4562, 71306, -4562, 787, 2096, -4562, 2099, 1308, -4562, 2103, 798, 2123, 798, 2098, 1653, 1890, 2100, 2101, 156, -4562, 50721, 2106, 2097, 1682, 1116, 2108, -4562, 2109, -4562, 2115, -4562, -4562, 1840, 2125, 2126, 2127, 798, 41783, 2128, -4562, 156, -4562, -4562, 681, -4562, 156, 2132, 1335, 458, 222, -4562, 1335, -4562, 1335, 47669, 2139, -4562, 679, -4562, -4562, 79846, 2021, 6920, 29149, 2150, 28231, 50721, 2154, 11860, -4562, 1890, 299, 2395, 78706, 200, 2049, 1890, -4562, -4562, 47887, -4562, -4562, -4562, 2141, -4562, 2142, -4562, 2155, -4562, 1268, 2682, -4562, 1522, 2171, 1890, 1308, 1787, 2170, 50986, -4562, 2172, 71306, -4562, 700, -4562, 2164, -4562, -4562, -4562, -4562, -4562, -4562, 1890, 1890, -4562, 2179, -4562, 2186, 2188, 2190, -4562, 365, -4562, -4562, -4562, 17712, 2110, 2129, 798, -4562, -4562, -4562, -4562, -4562, -4562, 929, -4562, 1682, -4562, -4562, 200, 2192, -4562, -4562, -4562, 1249, 2111, -4562, 2193, 43963, -4562, 214, 214, 30755, 1188, 214, 214, 11153, -4562, -4562, 214, -4562, 50721, 50721, 2185, 54407, 846, -4562, 214, 214, 47669, 43963, -4562, 43963, -4562, 43963, -4562, 43963, -4562, 798, -4562, -4562, 798, -4562, 2205, -4562, 899, -4562, 931, 2206, -4562, 54435, 214, 214, 214, 214, 214, -4562, 2215, -4562, 2142, 2218, 50721, 50721, 50721, 50721, 50721, 2930, 50721, 50721, 50721, 50721, 50721, 50721, 2202, 2208, 44181, 2224, 50721, 50721, 50721, 50721, 50721, 50721, 50721, 50721, 50721, 50721, 50721, 50721, 50721, 50721, 50721, 50721, 50721, 50721, 40514, 50721, -4562, -4562, -4562, -4562, 16785, 16785, 2228, 1308, 609, 2230, 1308, -4562, -4562, 2223, -4562, -4562, 2225, 2217, 1890, -4562, 2229, -4562, -4562, -4562, -4562, -4562, -4562, 798, 798, 1147, -4562, -4562, 38234, 2235, 6837, 71680, 72208, 76206, -4562, 2221, -4562, 55181, 2222, -4562, 2233, -4562, -4562, -4562, 50721, -4562, -4562, -4562, -4562, 1259, -4562, -4562, 29750, 71306, 44399, -4562, 2243, 1335, -4562, 1414, 1746, -4562, 681, 79667, -4562, -4562, -4562, 50721, 50721, 40239, 50721, 50721, 50721, 42001, 50721, 50721, 2239, 13157, 2241, 2149, 2242, 2259, 2260, 32876, 40239, -4562, 2263, 2264, -4562, 2265, 2266, 2252, 36475, 36841, 798, -4562, 79846, 2268, 50721, 50721, 50721, 2269, 353, 50721, 50721, 2270, -4562, 2044, 1787, 679, -4562, -4562, -4562, -4562, -4562, 1094, -4562, 1308, -4562, 37170, 2194, 6920, -4562, -4562, 2214, 12448, 41225, 798, 798, -4562, -4562, -4562, 50721, 50721, 41225, 50721, 50721, 50721, 42219, 50721, 50721, 2288, -4562, -4562, 798, -4562, 50721, 50721, 50721, 2293, 50721, 50721, 2295, -4562, 2050, 1787, -4562, -4562, -4562, -4562, 1170, -4562, 1308, -4562, 41225, 29149, 2219, 17337, 41225, 798, 798, -4562, 2143, -4562, -4562, -4562, -4562, 28803, -4562, 1335, 2319, -4562, 2299, -4562, 798, 14721, -4562, 156, 55209, 194, -4562, -4562, -4562, 11860, 11860, 11860, 11860, 11860, 11860, 42437, 11860, 11860, 50721, 50721, -4562, 50721, -4562, 798, -4562, 11860, 11860, 11860, 2318, 50721, 50721, 2320, -4562, 2073, 1787, 1881, -4562, -4562, -4562, -4562, 54501, -4562, 1297, -4562, 1308, -4562, 798, 798, 2325, 1482, 1482, 250, -4562, -4562, -4562, 1046, 50721, 1890, 958, 2258, 2808, -4562, 2323, -4562, -4562, -4562, 352, -4562, 35883, 638, 1522, 710, 2333, 1890, 923, 963, 35883, 2334, 76882, 798, 2289, 2350, 35883, 79774, 2204, 2352, 2355, 2356, 2357, -4562, -4562, -4562, -4562, -4562, -4562, -4562, -4562, -4562, -4562, -4562, 2353, -4562, 2349, -4562, -4562, -4562, -4562, -4562, -4562, -4562, -4562, 2297, 78934, -4562, -4562, -4562, 2367, 1103, 200, 2359, -4562, -4562, -4562, 15061, -4562, 191, 1482, -4562, 1682, 798, 2370, 50721, -4562, 50721, 50721, 50721, 1890, 1335, 2386, 2362, 2366, 2369, -4562, -4562, -4562, -4562, -4562, 2380, 2374, -4562, -4562, -4562, 50939, 1125, 50939, 50721, 50939, 50939, -4562, 50939, 42655, 50939, 50939, 610, 50721, 1139, 2377, 2378, 219, 2227, 2379, 739, 17865, 2305, 35883, 2389, 2390, 50721, 2391, 35883, 2384, -4562, -4562, -4562, -4562, -4562, 48105, 2393, -4562, 17865, 2396, 48323, -4562, 798, -4562, -4562, -4562, 2151, 308, 2399, 2402, 50939, 50939, 50939, 1482, 641, 1141, 50721, 50721, 2405, -4562, 2397, 2398, 22514, -4562, 2162, 1787, -4562, 35883, 35883, -4562, -4562, -4562, 22048, 22361, -4562, 14489, -4562, -4562, 2401, 2403, 1227, -4562, 285, 2416, -4562, -4562, 2417, -4562, 18219, -4562, -4562, 71334, 1099, 1704, 249, -4562, 955, 1308, -4562, 35883, -4562, -4562, -4562, -4562, -4562, -4562, -4562, -4562, -4562, 798, 798, 2109, 2109, -4562, 2394, 301, 2418, 18522, 2422, -4562, 798, -4562, -4562, -4562, 504, -4562, 12048, -4562, 2109, -4562, -4562, -4562, 1897, -4562, 50721, 50721, 50721, 50721, 50721, 50721, 50721, 50721, 50721, 50721, 50721, 50721, 50721, 2410, 1904, 2189, 55243, 2428, 1936, 1962, 50721, 2419, 50721, 2421, 26775, 1912, 1917, 1930, 1943, -4562, 42873, 44181, -4562, 48541, -4562, 44181, 50721, 50721, 50721, -4562, 50721, 305, 2184, 305, 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50721, -4562, -4562, -4562, 50721, -4562, 798, 50721, -4562, 3223, 3227, 3231, 2985, -4562, 35883, 53950, -4562, 70632, 70903, 70931, 767, 1829, 47233, -4562, 3168, 798, -4562, -4562, -4562, 70961, 70989, 71260, 71035, -4562, -4562, -4562, -4562, -4562, -4562, -4562, -4562, -4562, -4562, 50721, -4562, -4562, 3238, 3241, 3242, 1890, 3127, -4562, -4562, 35883, -4562, -4562, -4562, 798, 3235, 798, -4562, -4562, 798, 798, -4562, -4562, -4562, -4562, 3244, 2456, 3131, -4562, -4562, 3228, -4562, 3246, -4562, 3247, -4562, 798, 2456, -4562, 3239, 50067, -4562, -4562, -4562, 50067, 1751, 1755, -4562, -4562 }; /* YYDEFACT[STATE-NUM] -- Default reduction number in state STATE-NUM. Performed when YYTABLE does not specify something else to do. Zero means the default is an error. */ static const yytype_int16 yydefact[] = { 0, 14, 3066, 41, 841, 3062, 240, 234, 271, 0, 838, 0, 246, 274, 0, 0, 838, 838, 0, 236, 238, 838, 0, 211, 3068, 241, 237, 838, 3062, 838, 210, 838, 0, 244, 245, 242, 0, 235, 243, 3131, 840, 270, 315, 838, 838, 239, 0, 0, 0, 3062, 313, 3045, 0, 0, 3064, 0, 0, 6, 27, 11, 191, 12, 24, 336, 26, 8, 60, 9, 60, 25, 10, 60, 0, 0, 0, 0, 28, 0, 0, 246, 246, 246, 246, 264, 346, 259, 275, 269, 29, 334, 0, 337, 0, 335, 13, 30, 31, 3062, 33, 39, 40, 2428, 2460, 2429, 2460, 2430, 2871, 38, 2956, 32, 2460, 35, 60, 0, 0, 3063, 34, 0, 0, 2334, 0, 0, 0, 917, 918, 922, 920, 914, 910, 912, 909, 911, 913, 915, 916, 919, 921, 923, 0, 0, 2374, 2364, 414, 2350, 2367, 2370, 0, 0, 3063, 2337, 2335, 2336, 3011, 3062, 839, 2875, 2335, 248, 249, 246, 246, 0, 247, 0, 518, 0, 0, 903, 0, 0, 45, 838, 838, 60, 60, 60, 246, 246, 905, 0, 838, 0, 2870, 0, 0, 0, 0, 0, 0, 0, 122, 0, 2459, 2482, 246, 0, 3062, 3062, 0, 0, 3062, 0, 246, 0, 315, 313, 0, 520, 314, 315, 0, 57, 0, 1, 7, 0, 0, 0, 0, 191, 22, 0, 0, 60, 42, 68, 55, 68, 68, 36, 37, 531, 176, 300, 177, 2338, 2339, 0, 506, 513, 511, 512, 246, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 1341, 183, 0, 360, 182, 181, 180, 179, 178, 263, 247, 514, 0, 0, 287, 300, 291, 838, 347, 2461, 0, 2483, 0, 868, 0, 868, 0, 0, 0, 2957, 0, 3012, 0, 3046, 838, 57, 0, 523, 3059, 3062, 3067, 0, 0, 0, 1329, 3062, 1330, 1331, 1332, 1333, 1334, 1335, 1336, 1337, 410, 415, 536, 542, 543, 826, 827, 3062, 0, 3062, 2354, 3057, 0, 2355, 348, 321, 518, 3062, 319, 516, 0, 323, 519, 514, 0, 0, 0, 0, 0, 51, 68, 68, 68, 848, 849, 3062, 0, 247, 3062, 0, 0, 843, 851, 853, 0, 3056, 0, 0, 0, 906, 907, 903, 44, 0, 107, 3069, 54, 0, 57, 0, 0, 0, 130, 0, 123, 124, 126, 127, 129, 128, 133, 316, 265, 0, 842, 0, 0, 17, 0, 15, 984, 983, 985, 2385, 889, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 254, 1002, 251, 270, 1243, 0, 1237, 252, 889, 889, 889, 889, 3062, 3062, 3062, 3062, 3062, 3062, 0, 1001, 246, 246, 264, 0, 250, 1280, 1281, 937, 1183, 796, 993, 798, 1279, 1003, 1175, 0, 1184, 2374, 1238, 986, 0, 0, 0, 3063, 0, 518, 0, 0, 0, 300, 364, 3062, 0, 0, 57, 3062, 273, 3065, 2386, 23, 62, 43, 56, 70, 0, 0, 0, 0, 3062, 0, 513, 301, 302, 305, 0, 188, 513, 508, 514, 0, 192, 1342, 359, 262, 515, 711, 0, 292, 0, 341, 513, 344, 2474, 3062, 3062, 0, 872, 3062, 0, 3062, 2396, 0, 0, 0, 356, 3062, 3049, 0, 3061, 3060, 3062, 3058, 527, 276, 524, 525, 0, 2352, 0, 2351, 2366, 0, 412, 1341, 0, 0, 2371, 0, 0, 926, 322, 0, 926, 517, 0, 325, 328, 324, 49, 47, 48, 820, 821, 0, 0, 904, 0, 46, 0, 0, 0, 846, 3062, 845, 847, 868, 0, 0, 0, 0, 850, 3054, 868, 857, 830, 831, 0, 3043, 57, 273, 353, 3062, 0, 19, 121, 125, 309, 0, 823, 0, 3062, 801, 929, 930, 0, 1175, 927, 928, 3062, 578, 580, 933, 987, 3062, 3062, 0, 1324, 0, 1286, 932, 931, 981, 3062, 805, 3062, 803, 3062, 809, 3062, 807, 0, 770, 766, 0, 754, 250, 760, 0, 756, 0, 0, 765, 758, 935, 936, 934, 689, 690, 2, 0, 1182, 0, 0, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 0, 0, 3062, 0, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 687, 688, 1181, 282, 1305, 1305, 2374, 1240, 57, 2374, 1239, 368, 365, 0, 366, 367, 0, 0, 0, 267, 272, 501, 500, 502, 559, 59, 499, 0, 0, 0, 18, 61, 3062, 0, 95, 0, 0, 191, 532, 0, 304, 926, 0, 307, 530, 303, 507, 510, 3062, 190, 1338, 1339, 1340, 0, 193, 194, 493, 712, 1303, 288, 289, 0, 343, 2475, 0, 2463, 0, 2471, 2733, 2732, 2734, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 0, 3062, 0, 0, 0, 0, 0, 3062, 3062, 2751, 0, 0, 1264, 0, 0, 0, 3062, 3062, 0, 1258, 358, 0, 3062, 3062, 3062, 0, 0, 3062, 3062, 0, 2750, 0, 279, 0, 2479, 2686, 1213, 2742, 2752, 1205, 1214, 1259, 2735, 3062, 0, 3062, 2478, 2494, 2639, 0, 3062, 0, 3063, 2827, 2826, 2828, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 0, 2845, 1257, 0, 1251, 3062, 3062, 3062, 0, 3062, 3062, 0, 2844, 0, 279, 2780, 1203, 2836, 2846, 1195, 1204, 1252, 2829, 3062, 3062, 0, 2490, 3062, 0, 3063, 2872, 0, 214, 212, 213, 215, 246, 886, 0, 247, 875, 869, 870, 0, 246, 874, 300, 0, 2956, 1149, 1148, 1150, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 1167, 3062, 1271, 0, 1265, 3062, 3062, 3062, 0, 3062, 3062, 0, 1166, 0, 0, 0, 1089, 1102, 1223, 1158, 581, 1168, 1215, 1224, 1266, 1151, 0, 3063, 0, 3062, 3062, 0, 2960, 2884, 2897, 0, 3062, 0, 0, 0, 0, 2879, 0, 2881, 2892, 2882, 0, 3035, 0, 0, 1341, 0, 0, 2390, 0, 0, 0, 0, 356, 0, 0, 0, 0, 356, 0, 889, 889, 889, 889, 3031, 3024, 3022, 3018, 3020, 3038, 3037, 3036, 3039, 3026, 3030, 0, 3032, 0, 3028, 3021, 2432, 2433, 2431, 2449, 3029, 3027, 0, 356, 3015, 3017, 3023, 3047, 0, 3062, 0, 3042, 528, 526, 3062, 3129, 0, 3062, 411, 57, 0, 0, 3062, 2375, 3062, 3062, 3062, 0, 514, 0, 331, 0, 0, 50, 53, 106, 132, 844, 0, 0, 1065, 1064, 1066, 3062, 3062, 3062, 3062, 3062, 3062, 612, 3062, 3062, 3062, 3062, 0, 3062, 0, 594, 0, 838, 0, 0, 0, 3062, 3062, 0, 0, 0, 3062, 0, 0, 596, 219, 217, 1083, 218, 717, 3062, 0, 220, 3062, 0, 3062, 1250, 0, 1244, 718, 719, 0, 0, 0, 0, 3062, 3062, 3062, 3062, 489, 0, 3062, 3062, 0, 1082, 0, 0, 246, 867, 0, 259, 603, 0, 0, 608, 653, 649, 0, 0, 866, 0, 589, 610, 0, 1018, 0, 1193, 796, 0, 1074, 794, 798, 855, 0, 864, 606, 0, 1084, 0, 1185, 1194, 2374, 1245, 1067, 0, 657, 2436, 2438, 2439, 661, 2435, 607, 659, 2437, 0, 3063, 2386, 2386, 852, 0, 3062, 0, 246, 0, 272, 0, 355, 311, 312, 309, 283, 3062, 310, 2386, 16, 890, 1288, 0, 996, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 0, 0, 1320, 1324, 1319, 0, 0, 3062, 0, 3062, 1176, 982, 0, 0, 0, 0, 753, 981, 3062, 768, 3062, 769, 3062, 3062, 3062, 3062, 799, 3062, 954, 967, 952, 950, 951, 896, 897, 1242, 895, 898, 994, 995, 893, 1241, 3063, 953, 964, 965, 0, 969, 968, 3062, 3062, 1005, 1006, 3062, 962, 961, 971, 970, 972, 955, 956, 957, 958, 959, 960, 966, 978, 973, 974, 975, 963, 976, 3062, 0, 0, 0, 3062, 0, 0, 3122, 977, 1004, 2610, 2609, 2611, 3062, 3062, 3062, 3062, 3062, 0, 3062, 3062, 3062, 3062, 0, 3062, 0, 0, 3062, 3062, 2628, 0, 0, 1278, 0, 0, 0, 3062, 3062, 0, 1272, 0, 3062, 3062, 3062, 0, 3062, 3062, 0, 2627, 0, 0, 2510, 2563, 1233, 2619, 2629, 1225, 0, 1295, 1301, 1294, 1309, 1234, 1273, 2612, 3062, 2516, 1306, 3062, 0, 3063, 0, 1305, 369, 362, 521, 0, 309, 0, 0, 561, 3053, 261, 2388, 2387, 187, 0, 64, 185, 184, 0, 186, 66, 69, 95, 0, 72, 246, 98, 96, 0, 3062, 0, 0, 0, 3062, 0, 0, 0, 0, 0, 0, 0, 383, 403, 381, 382, 380, 404, 99, 0, 0, 0, 372, 375, 377, 386, 391, 393, 394, 387, 390, 376, 397, 396, 388, 398, 385, 378, 379, 543, 405, 389, 0, 0, 117, 116, 0, 0, 110, 114, 115, 120, 119, 0, 118, 113, 0, 0, 0, 145, 0, 191, 136, 139, 146, 0, 140, 142, 143, 141, 149, 148, 147, 150, 0, 144, 308, 306, 3062, 509, 1343, 0, 189, 0, 493, 279, 195, 198, 494, 0, 1304, 0, 1292, 1299, 1291, 1307, 3062, 345, 2476, 2462, 2474, 300, 103, 104, 2465, 2485, 2486, 2487, 358, 0, 2467, 2466, 2484, 2678, 2679, 0, 1205, 3062, 2639, 0, 2676, 2677, 2682, 2736, 0, 0, 2681, 2680, 3062, 3062, 2646, 3062, 0, 3062, 3062, 3062, 3062, 2642, 2634, 3062, 3062, 3062, 3062, 3062, 3062, 2649, 3062, 2643, 2730, 280, 281, 3062, 2684, 2685, 2683, 3062, 2851, 3062, 3062, 0, 2856, 2852, 701, 702, 2, 0, 1212, 0, 699, 700, 1211, 0, 2639, 2675, 2386, 2480, 2477, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 2498, 3062, 3062, 3062, 3062, 3062, 3062, 0, 3062, 3062, 0, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 0, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 2862, 3062, 2665, 0, 2663, 1261, 1260, 2772, 2773, 1195, 0, 2770, 2771, 2776, 2830, 0, 0, 2775, 2774, 3062, 2824, 2778, 2779, 2777, 3062, 697, 698, 2, 0, 1202, 695, 696, 1201, 2769, 2488, 2386, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 2491, 3062, 3062, 3062, 3062, 3062, 3062, 0, 0, 3062, 3062, 3062, 3062, 3062, 0, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 2759, 2757, 1254, 1253, 216, 878, 879, 876, 872, 873, 246, 0, 247, 881, 513, 2869, 0, 1094, 1095, 0, 1215, 1092, 1093, 1098, 1152, 0, 0, 1097, 1096, 587, 585, 583, 1146, 1100, 1101, 1099, 3062, 705, 706, 2, 0, 1222, 2397, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 0, 3062, 0, 3062, 3062, 0, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 703, 704, 1221, 1268, 1267, 868, 2365, 2964, 2962, 2963, 2959, 0, 2896, 2912, 2914, 2913, 0, 0, 2900, 0, 0, 0, 2893, 2934, 2893, 0, 0, 0, 0, 2386, 2880, 2883, 0, 3062, 0, 3019, 0, 2444, 0, 0, 493, 0, 0, 3062, 2391, 0, 0, 0, 2392, 0, 402, 0, 356, 419, 439, 442, 356, 438, 0, 446, 0, 173, 513, 2394, 3062, 401, 3025, 0, 3062, 0, 3062, 0, 3062, 0, 3062, 0, 0, 0, 2386, 3016, 1303, 3055, 3050, 3051, 0, 3062, 3062, 3106, 3109, 2353, 413, 537, 540, 3062, 0, 0, 0, 0, 326, 317, 333, 0, 3062, 327, 902, 901, 0, 662, 1018, 1010, 1084, 1185, 3062, 495, 1011, 0, 1175, 1008, 1009, 1014, 1068, 0, 0, 1013, 1012, 3062, 0, 3062, 0, 647, 221, 648, 3062, 3062, 3062, 0, 2345, 0, 2340, 0, 0, 0, 3062, 3062, 0, 3062, 638, 0, 0, 3062, 0, 751, 0, 0, 3062, 645, 0, 1062, 0, 3062, 0, 3062, 3062, 1016, 1017, 1015, 0, 0, 3062, 490, 491, 2425, 3062, 2426, 693, 694, 2, 604, 605, 230, 232, 0, 1192, 650, 651, 2386, 0, 0, 601, 0, 2386, 0, 609, 613, 626, 0, 0, 0, 0, 726, 0, 0, 629, 0, 865, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 0, 0, 3062, 0, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 489, 489, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 632, 691, 692, 1191, 0, 0, 652, 1247, 1246, 828, 829, 0, 825, 900, 833, 899, 0, 523, 284, 278, 277, 285, 822, 802, 1290, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 579, 577, 3062, 1315, 0, 1316, 0, 0, 3062, 1287, 3062, 806, 804, 810, 808, 755, 757, 758, 0, 762, 761, 1297, 0, 3, 0, 0, 1303, 0, 891, 0, 3062, 3062, 3126, 747, 0, 3124, 0, 744, 746, 0, 1324, 3062, 3113, 3062, 3062, 3062, 0, 3062, 3115, 2555, 2556, 1225, 0, 2553, 2554, 0, 2559, 2613, 0, 0, 2558, 2557, 3062, 3062, 2523, 3062, 3062, 3062, 2519, 2511, 3062, 3062, 3062, 3062, 3062, 3062, 2526, 3062, 2520, 2607, 3062, 2561, 2562, 2560, 3062, 709, 710, 2, 0, 1232, 707, 708, 1231, 789, 1305, 0, 0, 2552, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 0, 3062, 3062, 0, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 0, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 3062, 2542, 2540, 1275, 1274, 791, 0, 0, 309, 260, 58, 560, 564, 63, 3062, 67, 0, 71, 95, 0, 246, 0, 300, 0, 247, 0, 103, 97, 399, 0, 395, 3062, 2392, 0, 0, 533, 0, 0, 0, 417, 0, 445, 444, 437, 440, 0, 436, 543, 3062, 2005, 1989, 1990, 1991, 1992, 1993, 1994, 1997, 1995, 1996, 1998, 2000, 1999, 2001, 2002, 2003, 1679, 1680, 1681, 1682, 1683, 1684, 1685, 1686, 1687, 1688, 1689, 1690, 1691, 1692, 1693, 1694, 1695, 1696, 1697, 1698, 1699, 1700, 1701, 1702, 1703, 1704, 1710, 1711, 1712, 1713, 1714, 1715, 1716, 1717, 1718, 1719, 1720, 1721, 1722, 1723, 1724, 1725, 1726, 1727, 1728, 1729, 1730, 1731, 1732, 1733, 1734, 1735, 1736, 1737, 1738, 1739, 1740, 1741, 1742, 1743, 1744, 1745, 1746, 1747, 1748, 1749, 1750, 1751, 1758, 1759, 1760, 1761, 1762, 1763, 1764, 1765, 1766, 1767, 1768, 1769, 1770, 1771, 1772, 1773, 1676, 1774, 1775, 1776, 1777, 1778, 1779, 1780, 1781, 1782, 1783, 1784, 1785, 1786, 1787, 1788, 1789, 1790, 1791, 1792, 1793, 1794, 1795, 1796, 1797, 1798, 1799, 1800, 1801, 1802, 1803, 1804, 1805, 1806, 1807, 1808, 1809, 1810, 1811, 1812, 1813, 1814, 1815, 1816, 1817, 1818, 1819, 1820, 1821, 1822, 1823, 1824, 1825, 1826, 1827, 1828, 1829, 1830, 1831, 1832, 1833, 1834, 1835, 1836, 1837, 1838, 1839, 1840, 1841, 1842, 1843, 1844, 1845, 1903, 1904, 1905, 1906, 1907, 1908, 1909, 1910, 1911, 1912, 1913, 1914, 1915, 1916, 1917, 1918, 1919, 1920, 1921, 1922, 0, 1923, 1924, 1925, 1926, 1927, 1928, 1929, 1930, 1931, 1932, 1933, 1934, 1935, 1936, 1937, 1938, 1939, 1940, 1941, 1942, 1943, 1944, 1945, 1946, 1947, 1948, 1949, 1950, 1951, 1952, 1953, 1954, 1955, 1956, 1957, 1958, 1959, 1960, 1961, 1962, 1963, 1964, 1965, 1966, 1967, 1968, 1969, 1970, 1971, 1972, 1973, 1974, 1975, 1976, 1977, 1978, 1979, 1980, 1981, 1982, 1983, 1984, 1985, 1986, 1987, 1988, 1752, 1753, 1754, 1755, 1756, 1757, 1896, 1897, 1880, 1846, 1875, 1901, 1874, 1863, 1876, 1855, 1856, 1899, 1900, 1864, 1865, 1866, 1890, 1892, 1894, 1889, 1881, 1882, 1867, 1883, 1868, 1870, 1871, 1862, 1849, 1847, 1888, 1887, 1886, 1861, 1850, 1857, 1859, 1858, 1879, 1878, 1854, 1851, 1852, 1853, 1885, 1872, 1884, 1869, 1898, 1860, 1873, 1848, 1877, 1902, 1891, 1893, 1895, 1709, 1707, 1706, 1705, 1708, 0, 1677, 2333, 2318, 2319, 2320, 2321, 2322, 2323, 2326, 2324, 2325, 2327, 2329, 2328, 2330, 2331, 2332, 2009, 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018, 2019, 2020, 2021, 2022, 2023, 2024, 2025, 2026, 2027, 2028, 2029, 2030, 2031, 2032, 2033, 2039, 2040, 2041, 2042, 2043, 2044, 2045, 2046, 2047, 2048, 2049, 2050, 2051, 2052, 2053, 2054, 2055, 2056, 2057, 2058, 2059, 2060, 2061, 2062, 2063, 2064, 2065, 2066, 2067, 2068, 2069, 2070, 2071, 2072, 2073, 2074, 2075, 2076, 2077, 2078, 2079, 2080, 2087, 2088, 2089, 2090, 2091, 2092, 2093, 2094, 2095, 2096, 2097, 2098, 2099, 2100, 2101, 2102, 2103, 2104, 2105, 2106, 2107, 2108, 2109, 2110, 2111, 2112, 2113, 2114, 2115, 2116, 2117, 2118, 2119, 2120, 2121, 2122, 2123, 2124, 2125, 2126, 2127, 2128, 2129, 2130, 2131, 2132, 2133, 2134, 2135, 2136, 2137, 2138, 2139, 2140, 2141, 2142, 2143, 2144, 2145, 2146, 2147, 2148, 2149, 2150, 2151, 2152, 2153, 2154, 2155, 2156, 2157, 2158, 2159, 2160, 2161, 2162, 2163, 2164, 2165, 2166, 2167, 2168, 2169, 2170, 2171, 2172, 2173, 2231, 2232, 2233, 2234, 2235, 2236, 2237, 2238, 2239, 2240, 2241, 2242, 2243, 2244, 2245, 2246, 2247, 2248, 2249, 2250, 2251, 2252, 2253, 2254, 2255, 2256, 2257, 2258, 2259, 2260, 2261, 2262, 2263, 2264, 2265, 2266, 2267, 2268, 2269, 2270, 2271, 2272, 2273, 2274, 2275, 2276, 2277, 2278, 2279, 2280, 2281, 2282, 2283, 2284, 2285, 2286, 2287, 2288, 2289, 2290, 2291, 2292, 2293, 2294, 2295, 2296, 2297, 2298, 2299, 2300, 2301, 2302, 2303, 2304, 2305, 2306, 2307, 2308, 2309, 2310, 2311, 2312, 2313, 2314, 2315, 2316, 2317, 2081, 2082, 2083, 2084, 2085, 2086, 2224, 2225, 2208, 2174, 2203, 2229, 2202, 2191, 2204, 2183, 2184, 2227, 2228, 2192, 2193, 2194, 2218, 2220, 2222, 2217, 2209, 2210, 2195, 2211, 2196, 2198, 2199, 2190, 2177, 2175, 2216, 2215, 2214, 2189, 2178, 2185, 2187, 2186, 2207, 2206, 2182, 2179, 2180, 2181, 2213, 2200, 2212, 2197, 2226, 2188, 2201, 2176, 2205, 2230, 2219, 2221, 2223, 2038, 2036, 2035, 2034, 2037, 0, 2007, 1674, 1658, 1659, 1660, 1661, 1662, 1663, 1666, 1664, 1665, 1667, 1669, 1668, 1670, 1671, 1672, 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2985, 2979, 628, 296, 625, 743, 741, 0, 0, 0, 0, 1228, 1229, 1230, 2623, 0, 0, 3062, 513, 91, 80, 79, 0, 168, 0, 715, 3062, 2738, 3062, 3062, 3062, 2832, 3062, 3062, 3062, 1154, 3062, 3062, 2893, 3062, 2916, 2920, 2926, 0, 0, 0, 0, 2901, 0, 0, 0, 0, 0, 3062, 0, 0, 2944, 2889, 0, 3062, 456, 460, 461, 462, 463, 464, 465, 466, 467, 468, 469, 470, 471, 0, 3062, 1070, 3062, 3062, 788, 3062, 0, 0, 2982, 3001, 0, 3004, 0, 2980, 990, 991, 992, 3062, 2615, 3062, 3062, 570, 3062, 513, 92, 81, 455, 169, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2902, 0, 3062, 2922, 2924, 2923, 3062, 2918, 0, 3062, 2953, 2954, 0, 0, 2952, 2951, 0, 0, 834, 0, 0, 0, 0, 0, 3062, 3005, 2997, 0, 3002, 2999, 2986, 0, 0, 0, 0, 82, 2739, 2740, 2741, 2833, 2834, 2835, 1155, 1156, 1157, 3062, 750, 2927, 0, 0, 0, 0, 2945, 2947, 2456, 0, 1071, 1072, 1073, 0, 0, 0, 3000, 3006, 0, 0, 2616, 2617, 2618, 571, 0, 2893, 2948, 2950, 2955, 0, 2455, 0, 3008, 0, 2998, 2983, 2893, 2903, 0, 3062, 3009, 3007, 2904, 3062, 0, 0, 2946, 2949 }; /* YYPGOTO[NTERM-NUM]. */ static const int yypgoto[] = { -4562, -1319, -3754, -4562, -4562, 3219, -615, -4562, -4562, -4562, -4562, 176, 760, -4562, -10, 3268, 2947, -4562, -4562, -565, 3269, 1395, 23, 162, -4562, -4562, 1106, 842, -4562, 1973, 1113, -4562, -4562, -4513, -1270, -484, 68, -4562, -4562, 1908, -606, -4562, -4562, -4562, 2917, -452, 69, -4562, -4562, 1906, -4562, -4562, -4562, -4562, -4562, -659, -4562, -4562, -4562, -1714, -1481, -1476, -296, -4562, -1928, -500, -479, -627, -622, -4562, -4562, -4562, -4562, -4562, -4562, 22, -4562, -4562, -494, -529, -561, -4562, -4562, -4562, -4562, -4562, -4562, -4562, 1768, 12805, 15900, 108, 31, 30252, -269, -80, 8909, -4562, -4562, -4562, -708, -4562, 1996, -1037, -4562, -784, 2813, -375, -1358, -4562, -215, -230, -458, -4562, -1745, -4562, 3101, -4562, -4562, -4562, 2315, -4562, -4562, -282, -45, -4562, -4562, -4562, -4562, -4562, -4562, -4562, 9, -28, -253, -4562, -4562, 1978, -4562, -562, -577, -305, -249, -168, -587, -4562, 598, -4562, -186, 2800, -555, -4562, -4561, -4360, -4267, -4016, -2150, -1744, -2141, -1734, -4259, -3997, -584, -4562, -574, -4562, 1123, -1669, -4562, -4562, -1422, -1196, -4562, -1188, -1916, -1349, -697, 2328, -4071, -4061, -4562, 2869, -4562, -398, -164, -157, 3020, -4562, -2, -1942, -4562, 2830, -391, 3273, -4562, -579, 48, -4562, -4562, -4562, -4562, -4562, -4562, -1240, -4562, -4562, -1233, -4562, -2281, -4562, -812, -3581, -4562, -4562, -4562, -546, 278, -413, -586, 639, -4562, -4562, -4562, -4562, 2276, -4562, -966, -955, -3240, 1380, -4562, -4562, -3166, 643, -4562, -4562, -4562, -4562, -1287, 1398, -4562, -3535, -4562, -4562, -4562, -898, -4562, 2326, -4562, -1937, -424, -1166, -1807, -1860, -388, -4562, 2200, -4562, 2199, 24161, -4562, -4562, -833, -1249, -4562, -4098, -4562, -483, 1453, 25393, -4562, 1416, -127, -4562, 3056, -150, -523, -124, -187, -498, -4562, -753, 183, 8, -96, 1783, -170, -46, 340, 423, -205, -4562, -4562, 2298, -277, -4562, -4562, 1744, -4562, -4562, 2539, 18, -1427, -901, -4562, -4562, 3045, -4562, -462, -4562, -4562, 341, 19574, 920, 1078, -2993, 1065, -4562, -4562, -4562, -4562, -4562, -4562, -369, 1101, 2612, 2658, 2537, 2160, -126, -4562, -178, -475, -1782, -519, -4562, -4562, -4562, 185, 1304, 187, 1314, 201, 1320, 29021, 2835, 2273, -4562, -1144, -4562, 2017, -370, -4562, -4562, -4562, -2883, -4562, -4562, -2158, -4562, -4562, 564, -5, 207, -71, -945, -4562, -1521, 7, 1374, -4562, -4562, -986, -9, -3546, 3142, -781, 10687, -782, 33880, 511, -242, -4562, -97, -4562, -4562, -693, -4562, -4562, -4562, -1444, -4014, -4391, 1478, -304, -106, -4562, -4562, -4562, -4562, 339, 471, -4562, -571, -286, -4562, -4562, 1295, -4562, -4562, 2019, -4562, -4562, -4562, -4562, 2949, -4562, -4562, -4562, -4562, -4562, -4562, -2449, 2651, -992, -431, -4562, -1361, -1190, 6119, -374, 33625, -3257, -975, 3432, 406, -1314, -1305, -525, -4562, -4562, -176, -4562, -3830, 32, -4562, 2536, -905, -4562, -1715, -3403, -4562, 1711, -630, -1712, -3551, -1378, -1732, -1724, -4562, -3190, -4562, -42, -4562, -3433, -1058, -4562, -1049, -4562, -4562, -4021, -1899, 2607, -4562, 1732, 2558, -4562, -771, -4085, -4562, -4562, -1646, -4562, -4562, -1775, -4562, -1633, -4562, -1466, -1945, -3836, -4562, -1903, -82, -4562, -4562, -4562, -4562, -346, -4562, -4562, -4562, -152, -4562, -4562, -4562, -4562, -4562, -4562, 272, -946, -4562, 14636, 81, -33, 401, 6853, 4549, -4562, -4562, -4562, -4562, -4562, -88, -4562, -4562, -72, -4562, -90, -4562, -626, -4562, 1677, -673, -671, -4562, -871, -1490, -3135, -303, -4562, -1741 }; /* YYDEFGOTO[NTERM-NUM]. */ static const yytype_int16 yydefgoto[] = { 0, 1182, 3787, 55, 56, 57, 58, 59, 60, 218, 219, 61, 1344, 223, 63, 179, 170, 542, 64, 65, 66, 225, 511, 226, 704, 1316, 1317, 467, 706, 1325, 1326, 1327, 3200, 4742, 1432, 67, 68, 1377, 1378, 1379, 2206, 69, 371, 372, 373, 70, 71, 1391, 1392, 1393, 1394, 1395, 1382, 1383, 3208, 3209, 4392, 3210, 4779, 4780, 4781, 5009, 1348, 1784, 1785, 72, 73, 74, 75, 1320, 76, 77, 78, 728, 1413, 1328, 79, 80, 1329, 1349, 1350, 4389, 4772, 4388, 3950, 1074, 3679, 3680, 423, 424, 425, 256, 264, 426, 427, 84, 530, 579, 1307, 1999, 785, 86, 1135, 1136, 3762, 267, 268, 4252, 4253, 3231, 473, 474, 475, 1137, 1138, 209, 195, 87, 163, 537, 538, 999, 1827, 1825, 88, 3567, 89, 4154, 90, 4155, 91, 92, 259, 786, 93, 1351, 1352, 1353, 1354, 2207, 1356, 1357, 1358, 1359, 1360, 3927, 1361, 524, 138, 308, 1362, 954, 4769, 4551, 2208, 1778, 2209, 1779, 2210, 1780, 2211, 1781, 1363, 955, 1364, 956, 3525, 5068, 4760, 4535, 4761, 4536, 4104, 4105, 1892, 1418, 1078, 697, 3599, 3600, 237, 238, 239, 480, 486, 487, 329, 455, 476, 516, 517, 518, 231, 232, 2199, 2200, 1365, 526, 3586, 527, 3587, 310, 4171, 4172, 4173, 4164, 4165, 4166, 4167, 4168, 4169, 1309, 1310, 2176, 2177, 3909, 1079, 895, 896, 1080, 1081, 1082, 1083, 1084, 1910, 1911, 1085, 1086, 1087, 1088, 3985, 1089, 430, 1090, 832, 787, 897, 1282, 490, 3233, 1091, 4619, 1923, 3692, 4677, 4265, 4674, 4266, 4675, 2052, 2053, 2054, 5045, 1874, 2031, 620, 621, 622, 623, 431, 3639, 3640, 3641, 4632, 4633, 3987, 5099, 432, 1094, 433, 1096, 434, 1366, 4397, 1126, 95, 4574, 1128, 96, 4576, 4577, 5010, 153, 97, 381, 1992, 348, 349, 560, 567, 1098, 4235, 1099, 1100, 498, 499, 858, 859, 860, 861, 862, 584, 1197, 2044, 1198, 98, 333, 359, 99, 139, 3589, 3258, 535, 1102, 900, 436, 1103, 835, 790, 901, 1285, 3991, 1104, 437, 1105, 836, 791, 902, 1286, 1142, 3222, 600, 1143, 1422, 1287, 2038, 1423, 1288, 1424, 1289, 1425, 1290, 1426, 1291, 439, 1163, 2020, 3777, 601, 311, 725, 483, 484, 1367, 3198, 3199, 1368, 2542, 2543, 1369, 2869, 2870, 440, 1747, 1434, 3625, 3624, 3626, 1862, 3648, 3671, 142, 1731, 143, 3649, 144, 3650, 441, 3651, 442, 702, 1371, 962, 1448, 4134, 4135, 4136, 4561, 4137, 4572, 4573, 4566, 4567, 1110, 100, 1372, 965, 1111, 1112, 1113, 1763, 1114, 1115, 967, 1116, 101, 102, 274, 495, 736, 737, 738, 1435, 739, 796, 797, 103, 104, 276, 1442, 1443, 842, 3634, 798, 799, 1449, 4435, 4436, 1297, 3635, 1596, 802, 3993, 3994, 1565, 3342, 3263, 3343, 105, 106, 278, 107, 108, 5046, 919, 920, 921, 922, 923, 3499, 924, 1743, 1744, 4088, 1745, 5047, 4840, 5048, 5049, 5050, 5288, 925, 1748, 4846, 1749, 4093, 4514, 4515, 4516, 4517, 5195, 5369, 284, 911, 912, 1732, 1118, 4237, 4238, 4239, 4938, 4939, 4940, 5246, 4941, 5108, 5109, 4942, 4943, 5327, 4944, 5381, 5382, 109, 110, 286, 971, 972, 1783, 974, 975, 1119, 111, 112, 113, 509, 979, 1806, 698, 443, 976, 352, 444, 290, 291, 292, 445, 446, 212, 118, 183, 3570, 3571, 3572, 3573, 3574, 3575, 3576, 3577, 3578, 984, 1810, 1811, 3582, 3583, 2057, 1237, 1238, 2050, 2051, 116, 117 }; /* YYTABLE[YYPACT[STATE-NUM]] -- What to do in state STATE-NUM. If positive, shift that token. If negative, reduce the rule whose number is the opposite. If YYTABLE_NINF, syntax error. */ static const yytype_int16 yytable[] = { 140, 1498, 501, 375, 326, 854, 241, 356, 1184, 479, 1742, 283, 141, 3659, 376, 315, 717, 272, 154, 270, 1417, 717, 3551, 2025, 154, 154, 588, 619, 3493, 154, 1073, 1419, 1807, 3500, 1117, 154, 3531, 154, 377, 154, 374, 2048, 3529, 162, 207, 959, 1127, 1864, 211, 3738, 3741, 154, 154, 3761, 493, 2068, 224, 2187, 224, 1071, 3939, 224, 3937, 3566, 3334, 800, 3225, 3579, 4094, 233, 233, 1129, 240, 322, 438, 716, 1093, 1318, 1890, 710, 1072, 719, 1319, 174, 175, 269, 3292, 1861, 3986, 262, 1281, 1281, 1343, 1375, 1390, 732, 4090, 1101, 1996, 485, 254, 384, 1380, 4042, 1877, 2113, 4225, 4226, 4552, 4600, 257, 257, 1812, 525, 320, 4634, 4770, 1912, 1912, 4568, 161, 4601, 1400, 843, 4771, 1402, 3807, 4553, 1913, 1913, 1170, 1385, 1171, 312, 1172, 1403, 1173, 318, 1406, 321, 3232, 140, 1345, 140, 1927, 1355, 618, 1384, 1396, 3413, 382, 382, 4652, 1386, 1401, 3259, 988, 504, 1301, 327, 3271, 973, 330, 224, 224, 224, 4024, 540, 4878, 4879, 3272, 350, 350, 4861, 513, 4281, 3280, 3377, 1159, 154, 154, 366, 573, 368, 3278, 375, 309, 555, 154, 263, 265, 350, 350, 471, 3986, 119, 376, 4996, 3947, 176, 177, 2042, 951, 963, 181, 457, 2, 345, 345, 547, 184, 949, 189, 464, 191, 119, 152, 119, 155, 164, 377, 968, 374, 1346, 1376, 5294, 196, 197, 319, 182, 280, 119, 3487, 162, 459, 5138, 220, 688, 4990, 192, 4992, 1429, 641, 193, -786, 1296, 1296, -786, 5183, 3942, 471, 4052, 119, 5364, 327, 1347, 1381, 4507, 952, 221, 3790, 3990, 1209, 327, 3453, 961, 4450, 323, 324, 279, 4, 3366, 1513, 1734, 287, 503, 1013, 4, 194, 154, 1978, 1007, 3498, 280, 344, 344, 520, 522, 1125, 515, 140, 140, 140, 398, 140, 4474, 154, 554, 235, 556, 557, 119, 379, 2, -3062, 119, 141, 2, 1691, -257, 161, 140, 3598, 1322, 5054, 3949, -792, 721, 119, -257, 958, -257, 330, 4498, 536, 236, 4080, 1160, 1160, 327, 1883, 969, 149, 641, 150, 151, 3498, 200, 350, 953, 350, 350, 327, 5052, 198, 714, 24, 1691, 564, 2201, 481, 4163, 909, 3598, 181, 191, 119, 119, 119, 2058, 571, 1487, 3443, 361, 1503, 1903, 800, 3990, 1893, 119, 641, 2, 331, 222, 334, 1488, 502, 119, 564, 119, 957, 3498, 1756, 210, 3944, 465, 2194, 910, 362, 572, 1489, 364, 4810, 140, 367, 462, 369, 5367, 378, 795, 840, 964, 325, 604, 1397, 593, 241, 574, 447, 448, 726, 450, 451, 452, 1735, 3513, 3498, 40, 1162, 1162, 270, 968, 968, 968, 40, 970, 1884, 5295, 1567, 606, 608, 610, 612, 39, 5153, 319, 1573, 2043, 5154, 678, 514, 681, 1891, 24, 5158, 1093, 330, 24, 351, 351, 281, 521, 199, 1093, 494, 4811, 122, -357, 1661, 1093, 1398, 727, 950, 5291, 472, 233, 54, 1597, 351, 351, 1643, 510, 240, 3736, 722, 5146, 959, 4145, 429, 327, 692, 415, 651, 536, 5191, 536, 269, -254, 5192, 357, 415, 4770, 3646, 313, 863, 314, 282, 4663, 4559, 4771, 5062, 918, 960, 281, 5063, 119, 4, 3704, 5356, 1006, 959, 24, 1535, 122, 1077, 515, 5072, 4552, 415, 312, 5184, 472, 5193, 5066, 5067, 5184, 319, 4560, 3498, 4363, 856, 263, 265, 672, 673, 539, 4553, 4634, 471, 543, 1924, 1399, 149, 1925, 150, 151, 1995, -257, 1703, 282, 350, 1093, 1944, 536, 1107, 1066, 1093, 1124, 1117, 1117, 1764, 1979, 1980, 54, 4324, 519, 334, 54, 570, 4652, 1073, 1456, 309, 651, 1117, 575, 1428, 4272, 4640, 1295, 1295, 3678, 1404, 1071, 1071, 4590, 235, 1703, 544, 358, 545, 4733, 668, 1944, 1130, 1093, 1093, 3627, 94, 1071, 1093, 1093, 733, 1093, 1072, 1072, 1720, 855, 1174, -3112, 651, 1175, 1961, 236, -3112, 351, 1093, 351, 351, 2190, 1072, 1101, 1101, 1013, 664, 4837, 1803, 1093, 458, 1760, 5261, 54, 1849, 951, 963, -3112, 1579, 1101, 5229, -258, 3646, -247, 949, 4838, 5299, 5300, 1840, 3701, 1656, -258, 5230, -258, 968, 40, 94, 3986, 685, 1760, 531, 1281, 1013, 1490, 723, 724, 1491, 4621, 534, 951, 963, 3895, 5299, 5300, 4, 4639, 4641, 4629, 949, 398, 3739, 1133, 1134, 4161, 5218, 119, 4839, 119, 968, 180, 561, 952, 1013, 512, 3853, -357, 1311, 1312, 961, 1668, 1649, 233, 795, 208, 1370, 1370, 1405, 840, 5345, 4162, 325, 1281, 4659, 908, 266, 840, 270, 119, 1281, 980, 1419, 190, 512, 580, 1761, 952, 5194, 3904, 996, 4349, 4770, 1760, 961, 327, 4770, 1433, 5204, 990, 4771, 1343, 4770, 4, 4771, 598, 997, 840, 840, -255, 4771, 840, 4440, 429, 1761, 958, 208, 1000, 1001, -255, 624, -255, 1760, 1415, 62, 1856, 969, 1375, 235, 1479, 235, 3827, 283, 1506, 953, 119, 1380, 1492, 3826, 119, 3834, 1390, 926, 568, 269, 1481, 1762, 2171, 3840, 958, 3835, 1345, 619, 4472, 1355, 236, 2035, 236, 3662, 689, 969, 5416, 678, 681, 1814, 1385, 119, 257, 953, 1400, 119, 581, 1402, 472, 1762, 957, 534, 1506, 1296, 1583, 62, 1384, 1403, 40, 62, 1406, 1761, 1386, 5095, 166, 1891, 351, 3990, 178, 4775, 1396, 964, 1823, 5083, 3524, 1414, 1401, 1742, 3986, 678, 681, 1846, 5305, 4552, 957, 5084, 1440, 4552, 1093, 3206, 1761, 415, 327, 534, 863, 970, 213, 1133, 1134, 4552, 429, 1648, 4553, 1296, 1801, 964, 4553, 1346, 229, 5074, 1296, 1167, 1737, 3778, 3207, 157, -258, 1674, 4553, 3986, 5115, 1765, 429, 257, 429, 40, 429, 1168, 429, 970, 5116, 1654, 950, 1376, 672, 673, 1306, 1790, 3672, 1347, 678, 681, 230, 140, 140, 3676, 157, 1314, 618, 1741, 1769, 3623, 1752, 3914, 918, 1730, 1730, 158, 3921, 3923, 1757, 3642, 1107, 2167, 1176, 1381, 950, 1770, 2180, 271, 1107, 119, 1782, 1786, 1769, 3861, 1107, 3863, 1812, 273, 1177, 1760, 3869, 1805, 3684, 636, 1738, 1739, 158, 638, 639, 1770, 640, 641, 642, 3685, 1178, 4618, 119, 4618, 4622, 119, 1793, 1795, 1797, 1799, 960, 4932, 1653, 4618, 277, 149, 1179, 150, 151, 1813, 676, 966, 62, 140, 140, 4643, -255, 1816, 1982, 1750, 2023, 1751, 4933, 221, 4854, 4855, 141, 636, 327, 4858, 4859, 638, 639, 4770, 640, 641, 642, 929, 4618, 931, 119, 4771, 4122, 1167, 1815, 3990, 5205, 5206, 5207, 5208, 5209, 5210, 5211, 5212, 5213, 5214, 5215, 5216, 5217, 3256, 140, 140, 1107, 1990, 1772, 934, 636, 1107, 1761, 154, 638, 1077, 1077, 1730, 641, 642, 4932, 140, 171, 1773, 3986, 1881, 313, 119, 314, 968, 3990, 1077, 4934, 415, 27, 119, 140, 119, 1897, 4102, 289, 4933, 4107, 968, 1419, 4110, 468, 469, 1730, 2075, 1107, 1107, 172, 4724, 558, 1107, 1107, 382, 1107, 1904, 119, 288, 4847, 559, 1397, 1736, 4125, 1455, 3264, 968, 119, 1107, 1769, 3494, 3268, 1167, 672, 673, 1737, 1983, 4935, 257, 1107, 968, 3920, 3275, 1737, 289, 676, 1770, 4936, 3362, 678, 681, 4848, 565, 693, 4851, 350, 2, 350, 694, 695, 1994, 566, 693, 293, 4934, 2, -1236, 694, 695, 194, 1996, 294, 696, 3306, 1768, 119, 944, 1398, 544, 119, 545, 1836, 1295, 1895, 1167, 149, 3305, 150, 151, 1578, 854, 3311, 1760, 345, 3314, 1851, 295, 1896, 235, 3922, 3437, 3986, 929, 1167, 931, 5296, 1013, 4382, 634, 1738, 1739, 635, 966, 966, 551, 552, 553, 1738, 1739, 3617, 3802, 4552, 4936, 398, 3346, 236, 926, 3563, 651, 2045, 934, 4837, 1295, 336, 914, 840, 336, 539, 337, 1295, 4553, 360, 3363, 915, 665, 666, 667, 668, 5181, 5042, 1667, 3236, 370, 166, 3990, 1146, 235, 167, 1399, 1686, 1013, 296, 3389, 1688, 1689, 1686, 1690, 1691, 1692, 1688, 344, 168, 3385, 1691, 1692, 3388, 651, 3391, 3392, 3393, 929, 3594, 931, 236, 1167, 1761, 1387, -3044, 1388, 3595, 3785, 3224, 3420, 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0, 0, 0, 0, 2, -3062, 0, 0, 0, 0, 18, 0, 0, 0, 0, 19, 20, 0, 216, 0, 0, 22, 23, 24, 0, 0, 25, 26, 0, 0, 0, 0, 0, 28, 0, -246, 0, 0, 0, 0, 0, 0, 0, 0, 0, 30, 0, 0, 217, 32, 0, 0, 0, 0, 0, 6, 33, 34, 7, 35, 0, 0, 8, 0, 0, 0, 36, 37, 38, 0, 0, 0, 0, 0, 39, 40, 0, 41, 0, 42, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 43, 0, 44, 0, 0, 45, 46, 47, 0, 0, 0, 12, 13, 0, 48, 49, 50, 0, 0, 2, -3062, 0, 0, -356, 0, 51, 0, 52, 0, 53, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 19, 20, 0, 0, 0, 0, 0, 54, 24, 0, 0, 25, 26, 0, 0, 0, 0, 0, 0, 0, 4, 0, 0, 0, 0, 0, 6, 0, 0, 7, 2, -3062, 0, 8, 1436, 0, 0, 0, 0, 10, 0, 33, 34, 0, 35, 0, 0, 2, -3062, 0, 0, 1437, 37, 38, 157, 0, 0, 0, 0, 0, 0, -246, 41, 0, 42, 0, 0, 0, 0, 0, 0, 0, 0, 0, 12, 13, 0, 0, -246, 0, 0, 6, 45, 0, 7, 0, 0, 0, 8, 0, 0, 48, 0, 50, 0, 0, 158, 0, 6, 1438, 1439, 7, 222, 0, 185, 8, 186, 19, 20, 0, 0, 0, 0, 0, 0, 24, 0, 0, 25, 26, 0, 0, 0, 0, 0, 28, 0, 0, 54, 12, 13, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 12, 13, 33, 34, 0, 35, 0, 0, 0, 0, 0, 0, 0, 37, 38, 0, 19, 20, 0, 0, 0, 40, 0, 41, 24, 42, 0, 25, 26, 0, 0, 0, 0, 19, 20, 0, 0, 0, 0, 0, 0, 24, 0, 45, 25, 26, 0, 0, 0, 0, 0, 0, 48, 49, 50, 0, 0, 33, 34, 0, 35, 0, 0, 0, 0, 52, 0, 53, 37, 38, 157, 0, 0, 0, 33, 34, 0, 35, 41, 0, 42, 0, 0, 0, 0, 37, 38, 157, 0, 54, 0, 0, 0, 0, 0, 41, 0, 42, 45, 0, 0, 0, 0, 0, 0, 0, 0, 48, 0, 50, 0, 0, 158, 0, 0, 45, 772, 0, 0, 0, 185, 0, 186, 0, 48, 0, 50, 0, 0, 158, 0, 0, 0, 0, 0, 0, 0, 185, 0, 186, 0, 0, 0, 0, 54, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 54 }; static const yytype_int16 yycheck[] = { 5, 785, 279, 190, 161, 499, 77, 177, 634, 239, 915, 108, 5, 1873, 190, 139, 474, 97, 10, 90, 728, 479, 1804, 1167, 16, 17, 395, 415, 1740, 21, 559, 728, 978, 1748, 559, 27, 1780, 29, 190, 31, 190, 1207, 1776, 12, 49, 507, 569, 1033, 53, 1965, 1966, 43, 44, 1995, 269, 1245, 66, 1327, 68, 559, 2210, 71, 2203, 1808, 1554, 496, 1415, 1808, 3501, 74, 75, 569, 77, 153, 200, 473, 559, 704, 1064, 470, 559, 479, 704, 15, 15, 90, 1513, 1032, 3254, 80, 676, 677, 707, 708, 709, 493, 3499, 559, 1135, 256, 78, 197, 708, 3360, 1049, 1295, 3652, 3653, 4124, 4180, 79, 80, 983, 299, 147, 4213, 4383, 1083, 1084, 4133, 12, 4182, 709, 497, 4383, 709, 2063, 4124, 1083, 1084, 605, 708, 607, 138, 609, 709, 611, 146, 709, 148, 1427, 146, 707, 148, 1099, 707, 415, 708, 709, 1639, 196, 197, 4237, 708, 709, 1460, 526, 281, 677, 161, 1474, 507, 164, 173, 174, 175, 3301, 331, 4559, 4560, 1475, 176, 177, 4533, 37, 3756, 1495, 1604, 591, 171, 172, 186, 31, 188, 1489, 372, 138, 344, 180, 81, 82, 196, 197, 37, 3360, 4, 372, 4758, 3081, 16, 17, 22, 507, 507, 21, 210, 6, 176, 177, 333, 27, 507, 29, 223, 31, 4, 9, 4, 11, 12, 372, 507, 372, 707, 708, 56, 43, 44, 147, 22, 36, 4, 1722, 202, 211, 23, 60, 452, 4751, 32, 4753, 735, 28, 36, 23, 676, 677, 26, 23, 2407, 37, 3386, 4, 23, 256, 707, 708, 4087, 507, 19, 2042, 3254, 650, 265, 1691, 507, 4020, 159, 160, 22, 51, 1590, 28, 23, 112, 280, 19, 51, 167, 271, 31, 558, 128, 36, 176, 177, 295, 296, 565, 291, 295, 296, 297, 36, 299, 4049, 288, 343, 85, 345, 346, 4, 194, 6, 7, 4, 299, 6, 28, 30, 202, 316, 28, 704, 26, 3198, 31, 481, 4, 40, 507, 42, 324, 4077, 326, 112, 3461, 596, 597, 331, 22, 507, 4, 28, 6, 7, 128, 22, 343, 507, 345, 346, 344, 189, 9, 471, 146, 28, 353, 1335, 242, 37, 53, 28, 171, 172, 4, 4, 4, 1230, 365, 8, 1681, 180, 795, 1073, 797, 3360, 1065, 4, 28, 6, 165, 133, 167, 22, 22, 4, 383, 4, 507, 128, 30, 141, 2542, 223, 1331, 88, 181, 366, 37, 184, 26, 398, 187, 219, 189, 23, 191, 496, 497, 507, 37, 408, 709, 398, 477, 256, 201, 202, 188, 204, 205, 206, 164, 1764, 128, 198, 596, 597, 491, 707, 708, 709, 198, 507, 118, 258, 802, 411, 412, 413, 414, 197, 4995, 354, 810, 258, 4999, 444, 303, 446, 185, 146, 5005, 928, 448, 146, 176, 177, 256, 203, 9, 936, 271, 89, 265, 238, 871, 942, 709, 239, 507, 255, 308, 470, 266, 841, 196, 197, 844, 288, 477, 1963, 16, 4988, 938, 241, 200, 481, 457, 269, 268, 485, 18, 487, 491, 268, 22, 74, 269, 4758, 265, 120, 499, 122, 302, 4251, 136, 4758, 4860, 506, 507, 256, 4864, 4, 51, 1934, 255, 555, 972, 146, 268, 265, 559, 517, 4876, 4533, 269, 524, 295, 308, 56, 312, 313, 295, 445, 165, 128, 28, 499, 423, 424, 312, 313, 328, 4533, 4635, 37, 332, 255, 709, 4, 258, 6, 7, 42, 268, 268, 302, 555, 1034, 268, 555, 559, 298, 1039, 562, 1083, 1084, 930, 312, 313, 266, 3821, 293, 359, 266, 361, 4654, 1099, 749, 524, 268, 1099, 368, 733, 3712, 203, 676, 677, 1900, 709, 1083, 1084, 4166, 85, 268, 215, 174, 217, 4345, 287, 268, 571, 1078, 1079, 269, 0, 1099, 1083, 1084, 494, 1086, 1083, 1084, 287, 499, 613, 26, 268, 616, 287, 112, 31, 343, 1099, 345, 346, 1327, 1099, 1083, 1084, 19, 282, 22, 972, 1110, 19, 19, 5143, 266, 22, 938, 938, 52, 814, 1099, 26, 30, 265, 37, 938, 40, 270, 271, 1015, 1934, 863, 40, 38, 42, 938, 198, 56, 3821, 449, 19, 317, 1245, 19, 308, 204, 205, 311, 4200, 325, 972, 972, 2159, 270, 271, 51, 4219, 4220, 4210, 972, 36, 1965, 175, 176, 26, 5073, 4, 81, 4, 972, 66, 348, 938, 19, 290, 2119, 238, 699, 700, 938, 875, 855, 704, 797, 214, 707, 708, 709, 802, 5267, 52, 37, 1295, 4245, 504, 33, 810, 785, 4, 1302, 510, 1415, 31, 319, 381, 112, 972, 258, 42, 26, 3862, 4995, 19, 972, 733, 4999, 738, 33, 528, 4995, 1352, 5005, 51, 4999, 400, 42, 840, 841, 30, 5005, 844, 4005, 471, 112, 938, 214, 546, 547, 40, 415, 42, 19, 728, 0, 22, 938, 1378, 85, 770, 85, 2081, 865, 797, 938, 4, 1378, 778, 2079, 4, 2090, 1392, 506, 356, 785, 772, 172, 1302, 2103, 972, 2091, 1352, 1176, 4046, 1352, 112, 1180, 112, 23, 454, 972, 30, 803, 804, 986, 1378, 4, 772, 972, 1392, 4, 384, 1392, 308, 172, 938, 471, 841, 1245, 820, 56, 1378, 1392, 198, 60, 1392, 112, 1378, 4922, 6, 185, 555, 3821, 10, 28, 1392, 938, 997, 4905, 124, 728, 1392, 1743, 4005, 845, 846, 1020, 5203, 4860, 972, 4907, 739, 4864, 1332, 1373, 112, 269, 855, 513, 860, 938, 0, 175, 176, 4876, 583, 853, 4860, 1295, 962, 972, 4864, 1352, 31, 4884, 1302, 26, 55, 2018, 1373, 192, 268, 883, 4876, 4046, 31, 172, 605, 853, 607, 198, 609, 42, 611, 972, 41, 861, 938, 1378, 312, 313, 690, 943, 1885, 1352, 906, 907, 31, 909, 910, 1892, 192, 701, 1178, 915, 172, 1857, 918, 2184, 920, 909, 910, 234, 2189, 2190, 926, 1867, 928, 1298, 26, 1378, 972, 189, 1320, 238, 936, 4, 938, 939, 172, 2126, 942, 2128, 1810, 22, 42, 19, 2133, 977, 1911, 20, 129, 130, 234, 24, 25, 189, 27, 28, 29, 1911, 26, 4198, 4, 4200, 4201, 4, 945, 946, 947, 948, 972, 40, 861, 4210, 22, 4, 42, 6, 7, 985, 22, 507, 219, 985, 986, 4222, 268, 989, 30, 28, 1165, 30, 61, 19, 4526, 4527, 986, 20, 997, 4531, 4532, 24, 25, 5267, 27, 28, 29, 48, 4245, 50, 4, 5267, 53, 26, 988, 4005, 312, 313, 314, 315, 316, 317, 318, 319, 320, 321, 322, 323, 324, 42, 1032, 1033, 1034, 1126, 68, 76, 20, 1039, 112, 1028, 24, 1083, 1084, 1033, 28, 29, 40, 1049, 141, 83, 4213, 1053, 120, 4, 122, 1338, 4046, 1099, 127, 269, 153, 4, 1064, 4, 1066, 3511, 7, 61, 3514, 1352, 1764, 3517, 227, 228, 1064, 1250, 1078, 1079, 171, 4333, 22, 1083, 1084, 1126, 1086, 1073, 4, 66, 4518, 31, 1392, 42, 3538, 749, 1465, 1378, 4, 1099, 172, 42, 1471, 26, 312, 313, 55, 1107, 175, 1073, 1110, 1392, 28, 1482, 55, 7, 22, 189, 185, 42, 1120, 1121, 4520, 22, 3, 4523, 1126, 6, 1128, 8, 9, 1131, 31, 3, 69, 127, 6, 33, 8, 9, 167, 2173, 303, 22, 1527, 933, 4, 186, 1392, 215, 4, 217, 22, 1245, 8, 26, 4, 1526, 6, 7, 814, 1650, 1531, 19, 1128, 1534, 22, 28, 22, 85, 28, 42, 4333, 48, 26, 50, 5192, 19, 53, 255, 129, 130, 258, 707, 708, 338, 339, 340, 129, 130, 42, 2057, 5203, 185, 36, 1564, 112, 920, 1808, 268, 1200, 76, 22, 1295, 26, 31, 1298, 26, 996, 31, 1302, 5203, 31, 1582, 40, 284, 285, 286, 287, 5044, 40, 875, 1432, 31, 6, 4213, 33, 85, 10, 1392, 20, 19, 28, 1616, 24, 25, 20, 27, 28, 29, 24, 1128, 24, 1612, 28, 29, 1615, 268, 1617, 1618, 1619, 48, 30, 50, 112, 26, 112, 48, 66, 50, 38, 26, 1414, 1656, 4, 4426, 287, 146, 1268, 77, 1392, 42, 1641, 1965, 1966, 931, 146, 42, 934, 76, 28, 5112, 22, 5299, 5300, 76, 268, 23, 1440, 68, 26, 4526, 4527, 61, 62, 63, 4531, 4532, 86, 1299, 1300, 28, 251, 1924, 83, 287, 4541, 4542, 1308, 157, 251, 186, 120, 1808, 122, 157, 172, 159, 1701, 1776, 1320, 20, 1792, 1780, 1794, 24, 1796, 1327, 1798, 28, 29, 1331, 1332, 141, 1808, 1335, 30, 991, 1338, 993, 994, 995, 26, 185, 38, 4333, 30, 1335, 1065, 26, 37, 4, 1352, 6, 7, 4, 1329, 6, 7, 127, 5185, 5186, 5187, 1327, 26, 42, 1020, 155, 269, 1025, 303, 24, 3304, 1465, 1374, 1031, 1349, 37, 1378, 1471, 42, 169, 4617, 4924, 40, 26, 282, 266, 30, 186, 1482, 1911, 1392, 1786, 1872, 186, 266, 26, 40, 26, 42, 42, 26, 1126, 104, 1128, 30, 215, 5239, 217, 110, 312, 313, 42, 938, 42, 1911, 1414, 314, 315, 316, 317, 318, 319, 320, 321, 322, 323, 324, 175, 176, 1428, 240, 1911, 1526, 1913, 85, 1911, 4426, 1531, 1327, 40, 1534, 1440, 269, 1809, 1373, 1373, 972, 1927, 26, 26, 4850, 1439, 1911, 3387, 1934, 1729, 23, 5284, 1248, 26, 269, 112, 26, 30, 42, 42, 68, 31, 26, 71, 1564, 5298, 4635, 1439, 1776, 1776, 268, 26, 1780, 1780, 303, 30, 268, 1776, 42, 312, 313, 1780, 1582, 4, 73, 6, 5325, 1776, 5327, 287, 5329, 1780, 120, 1653, 122, 287, 1982, 312, 313, 314, 315, 316, 317, 318, 319, 320, 321, 322, 323, 324, 1306, 1800, 1612, 26, 303, 1615, 1178, 1617, 1618, 1619, 26, 2110, 26, 3463, 1776, 22, 5359, 26, 1780, 42, 5363, 1776, 26, 5366, 31, 1780, 42, 2126, 42, 2128, 5379, 1641, 192, 42, 2133, 5384, 135, 136, 42, 2179, 33, 20, 1943, 31, 2179, 24, 25, 303, 27, 28, 29, 268, 40, 269, 928, 173, 174, 175, 1230, 5402, 119, 120, 936, 122, 141, 31, 165, 5416, 942, 5418, 287, 37, 5421, 5422, 234, 31, 1776, 26, 1250, 269, 1780, 269, 181, 3524, 40, 26, 4, 1776, 6, 5438, 4, 1780, 3533, 42, 40, 1776, 312, 313, 4, 1780, 6, 42, 8, 29, 22, 31, 24, 4, 268, 6, 7, 26, 5058, 26, 1420, 146, 22, 26, 31, 1808, 1122, 1123, 312, 313, 312, 313, 26, 42, 42, 4635, 30, 28, 1650, 42, 1649, 4, 1776, 1139, 1653, 26, 1780, 55, 1012, 1808, 1014, 5061, 1016, 1017, 1652, 1019, 26, 1021, 1022, 31, 30, 42, 215, 1776, 217, 26, 1034, 1780, 4915, 66, 26, 1039, 2110, 26, 1650, 2205, 1652, 31, 203, 42, 1409, 42, 157, 37, 159, 4932, 42, 1776, 2126, 42, 2128, 1780, 55, 218, 19, 2133, 3619, 1061, 1062, 1063, 2205, 2082, 303, 26, 26, 4, 2087, 6, 31, 66, 1078, 1079, 120, 26, 122, 2096, 26, 31, 1086, 1731, 42, 129, 130, 4, 1776, 6, 7, 98, 1780, 42, 33, 1743, 42, 1745, 146, 6, 26, 2132, 26, 26, 265, 266, 1110, 26, 31, 1757, 146, 28, 31, 4922, 2131, 1650, 42, 22, 42, 2136, 26, 120, 2139, 122, 1772, 0, 23, 1775, 1776, 26, 129, 130, 1780, 3713, 26, 26, 42, 12, 26, 26, 31, 22, 3529, 30, 3937, 2179, 269, 26, 2165, 26, 42, 5197, 31, 28, 42, 203, 20, 78, 79, 268, 24, 25, 1464, 27, 28, 29, 1338, 203, 289, 3557, 218, 26, 1474, 3557, 49, 30, 3560, 31, 287, 26, 1352, 56, 218, 3571, 31, 60, 1488, 3571, 3576, 312, 313, 314, 315, 316, 317, 318, 319, 320, 321, 322, 323, 324, 26, 26, 79, 80, 1378, 31, 31, 1857, 1858, 146, 26, 308, 309, 310, 30, 265, 266, 1867, 33, 1869, 97, 1911, 1872, 5108, 26, 37, 1876, 265, 266, 31, 3224, 2002, 26, 26, 26, 1885, 26, 31, 31, 31, 26, 31, 1892, 31, 4170, 31, 5442, 1885, 4174, 4, 5446, 6, 7, 4, 1892, 6, 1560, 1561, 1562, 23, 33, 1911, 26, 1913, 119, 120, 203, 122, 4, 31, 6, 7, 2203, 304, 305, 23, 153, 1927, 26, 2210, 33, 218, 23, 3865, 4922, 26, 141, 1012, 22, 1014, 23, 1016, 1017, 26, 1019, 23, 1021, 1022, 26, 176, 177, 81, 869, 870, 31, 872, 873, 874, 23, 876, 877, 26, 1750, 2188, 176, 177, 171, 3904, 885, 886, 887, 23, 1561, 1562, 26, 202, 1332, 2187, 265, 266, 559, 40, 1982, 42, 1772, 110, 1061, 1062, 1063, 28, 2082, 282, 219, 23, 23, 2087, 26, 26, 1995, 1787, 23, 5186, 5187, 26, 2096, 135, 136, 40, 1731, 42, 215, 303, 217, 23, 144, 33, 26, 23, 2110, 24, 26, 1505, 33, 314, 315, 316, 317, 318, 319, 320, 321, 322, 323, 324, 2126, 165, 2128, 23, 28, 2131, 26, 2133, 172, 159, 2136, 146, 23, 2139, 23, 26, 31, 26, 268, 33, 23, 23, 99, 26, 26, 189, 2060, 269, 23, 23, 1852, 26, 26, 9, 284, 285, 286, 287, 22, 2165, 215, 1792, 217, 1794, 31, 1796, 33, 1798, 1012, 1871, 1014, 33, 1016, 1017, 315, 1019, 23, 1021, 1022, 26, 23, 23, 23, 26, 26, 26, 23, 268, 203, 26, 269, 23, 23, 23, 26, 26, 26, 3627, 22, 3629, 1598, 22, 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-1, -1, -1, -1, 179, 180, -1, 182, -1, -1, -1, -1, -1, -1, 189, 190, 191, -1, -1, -1, -1, -1, 197, 198, -1, 200, -1, 202, -1, -1, -1, -1, -1, -1, 6, 7, -1, -1, -1, -1, 215, -1, 217, -1, -1, 220, 221, 222, -1, -1, -1, -1, -1, -1, 229, 230, 231, -1, -1, 31, -1, -1, -1, 238, -1, 240, -1, 242, -1, 244, -1, -1, -1, -1, -1, -1, -1, -1, -1, 51, -1, -1, 54, -1, -1, 57, -1, -1, 60, -1, -1, 266, 64, 65, 66, -1, -1, 69, 70, -1, -1, -1, -1, -1, -1, 77, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 98, -1, -1, -1, -1, -1, -1, 105, 106, -1, -1, 109, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 120, -1, 122, -1, -1, -1, -1, 6, 7, -1, -1, -1, -1, 133, -1, -1, -1, -1, 138, 139, -1, 141, -1, -1, 144, 145, 146, -1, -1, 149, 150, -1, -1, -1, -1, -1, 156, -1, 37, -1, -1, -1, -1, -1, -1, -1, -1, -1, 168, -1, -1, 171, 172, -1, -1, -1, -1, -1, 57, 179, 180, 60, 182, -1, -1, 64, -1, -1, -1, 189, 190, 191, -1, -1, -1, -1, -1, 197, 198, -1, 200, -1, 202, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 215, -1, 217, -1, -1, 220, 221, 222, -1, -1, -1, 105, 106, -1, 229, 230, 231, -1, -1, 6, 7, -1, -1, 238, -1, 240, -1, 242, -1, 244, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 138, 139, -1, -1, -1, -1, -1, 266, 146, -1, -1, 149, 150, -1, -1, -1, -1, -1, -1, -1, 51, -1, -1, -1, -1, -1, 57, -1, -1, 60, 6, 7, -1, 64, 172, -1, -1, -1, -1, 70, -1, 179, 180, -1, 182, -1, -1, 6, 7, -1, -1, 189, 190, 191, 192, -1, -1, -1, -1, -1, -1, 37, 200, -1, 202, -1, -1, -1, -1, -1, -1, -1, -1, -1, 105, 106, -1, -1, 37, -1, -1, 57, 220, -1, 60, -1, -1, -1, 64, -1, -1, 229, -1, 231, -1, -1, 234, -1, 57, 237, 238, 60, 133, -1, 242, 64, 244, 138, 139, -1, -1, -1, -1, -1, -1, 146, -1, -1, 149, 150, -1, -1, -1, -1, -1, 156, -1, -1, 266, 105, 106, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 105, 106, 179, 180, -1, 182, -1, -1, -1, -1, -1, -1, -1, 190, 191, -1, 138, 139, -1, -1, -1, 198, -1, 200, 146, 202, -1, 149, 150, -1, -1, -1, -1, 138, 139, -1, -1, -1, -1, -1, -1, 146, -1, 220, 149, 150, -1, -1, -1, -1, -1, -1, 229, 230, 231, -1, -1, 179, 180, -1, 182, -1, -1, -1, -1, 242, -1, 244, 190, 191, 192, -1, -1, -1, 179, 180, -1, 182, 200, -1, 202, -1, -1, -1, -1, 190, 191, 192, -1, 266, -1, -1, -1, -1, -1, 200, -1, 202, 220, -1, -1, -1, -1, -1, -1, -1, -1, 229, -1, 231, -1, -1, 234, -1, -1, 220, 238, -1, -1, -1, 242, -1, 244, -1, 229, -1, 231, -1, -1, 234, -1, -1, -1, -1, -1, -1, -1, 242, -1, 244, -1, -1, -1, -1, 266, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 266 }; /* YYSTOS[STATE-NUM] -- The symbol kind of the accessing symbol of state STATE-NUM. */ static const yytype_int16 yystos[] = { 0, 1, 6, 31, 51, 54, 57, 60, 64, 65, 70, 77, 105, 106, 109, 111, 120, 122, 133, 138, 139, 141, 144, 145, 146, 149, 150, 153, 156, 166, 168, 171, 172, 179, 180, 182, 189, 190, 191, 197, 198, 200, 202, 215, 217, 220, 221, 222, 229, 230, 231, 240, 242, 244, 266, 346, 347, 348, 349, 350, 351, 354, 355, 357, 361, 362, 363, 378, 379, 384, 388, 389, 408, 409, 410, 411, 413, 414, 415, 419, 420, 431, 432, 433, 438, 439, 444, 460, 467, 469, 471, 473, 474, 477, 489, 618, 621, 626, 648, 651, 737, 748, 749, 759, 760, 781, 782, 784, 785, 836, 837, 845, 846, 847, 859, 860, 883, 884, 862, 4, 203, 218, 265, 275, 276, 281, 282, 287, 312, 313, 333, 334, 335, 336, 337, 338, 339, 340, 491, 652, 705, 711, 714, 716, 718, 720, 855, 859, 860, 4, 6, 7, 706, 625, 626, 706, 6, 192, 234, 431, 432, 434, 435, 461, 706, 860, 6, 10, 24, 358, 359, 141, 171, 363, 379, 389, 625, 625, 10, 358, 66, 625, 706, 863, 625, 242, 244, 439, 859, 625, 31, 625, 706, 706, 167, 459, 625, 625, 9, 9, 22, 66, 105, 141, 202, 231, 439, 705, 214, 458, 141, 705, 861, 0, 348, 54, 141, 171, 352, 353, 354, 19, 133, 356, 357, 364, 366, 364, 364, 31, 31, 535, 536, 705, 536, 85, 112, 523, 524, 525, 705, 707, 140, 204, 205, 223, 224, 225, 226, 227, 228, 248, 252, 259, 418, 229, 434, 435, 439, 475, 229, 439, 475, 434, 435, 434, 33, 448, 449, 705, 707, 238, 438, 22, 750, 750, 761, 22, 783, 22, 36, 256, 302, 726, 815, 750, 838, 366, 66, 7, 856, 857, 858, 69, 303, 28, 28, 28, 13, 30, 47, 59, 154, 161, 162, 164, 260, 261, 492, 539, 544, 692, 705, 120, 122, 620, 28, 37, 716, 856, 857, 716, 438, 434, 434, 37, 528, 531, 40, 529, 531, 706, 303, 649, 706, 303, 26, 31, 364, 364, 364, 157, 159, 245, 434, 435, 439, 628, 629, 630, 705, 852, 854, 855, 859, 628, 629, 74, 174, 650, 31, 625, 706, 303, 706, 141, 705, 706, 705, 706, 31, 385, 386, 387, 618, 621, 784, 845, 706, 434, 40, 627, 630, 855, 627, 31, 29, 31, 3, 8, 9, 10, 17, 18, 21, 22, 25, 27, 36, 39, 40, 41, 43, 70, 163, 192, 200, 203, 214, 218, 234, 262, 263, 264, 267, 269, 272, 273, 274, 312, 313, 341, 342, 431, 432, 433, 436, 437, 439, 559, 575, 602, 610, 612, 614, 655, 658, 666, 672, 687, 705, 720, 722, 852, 855, 859, 860, 706, 706, 66, 706, 706, 706, 31, 37, 530, 459, 705, 19, 365, 303, 98, 354, 22, 357, 366, 22, 370, 370, 370, 26, 37, 308, 453, 454, 455, 531, 26, 31, 454, 526, 434, 289, 694, 695, 528, 527, 528, 157, 159, 581, 26, 31, 453, 625, 751, 31, 31, 637, 638, 33, 637, 22, 705, 620, 22, 31, 31, 110, 848, 625, 365, 858, 37, 303, 531, 532, 533, 534, 852, 716, 203, 716, 718, 490, 491, 540, 542, 439, 720, 439, 654, 655, 529, 654, 655, 531, 462, 463, 706, 527, 24, 360, 706, 215, 217, 617, 620, 33, 24, 359, 370, 370, 370, 630, 528, 630, 630, 22, 31, 631, 631, 28, 159, 705, 22, 31, 632, 632, 649, 706, 705, 365, 31, 256, 706, 31, 99, 387, 440, 631, 632, 9, 22, 644, 655, 655, 655, 666, 655, 655, 22, 24, 711, 655, 42, 284, 285, 654, 655, 674, 691, 655, 655, 705, 22, 644, 22, 644, 22, 644, 22, 644, 28, 42, 81, 214, 301, 437, 597, 598, 599, 600, 601, 654, 655, 655, 655, 655, 655, 655, 22, 268, 602, 255, 258, 20, 21, 24, 25, 27, 28, 29, 32, 34, 35, 39, 41, 84, 137, 151, 268, 270, 271, 272, 273, 274, 275, 276, 277, 278, 279, 280, 281, 282, 284, 285, 286, 287, 290, 293, 297, 312, 313, 602, 23, 22, 22, 705, 720, 7, 705, 720, 31, 31, 706, 31, 31, 453, 654, 28, 40, 365, 3, 8, 9, 22, 520, 851, 859, 28, 30, 723, 23, 367, 301, 371, 31, 31, 31, 535, 24, 38, 655, 672, 38, 526, 455, 524, 526, 33, 527, 16, 204, 205, 693, 188, 239, 416, 655, 22, 449, 526, 434, 439, 147, 752, 753, 754, 756, 3, 8, 9, 18, 21, 22, 25, 27, 39, 40, 41, 43, 44, 46, 61, 83, 107, 113, 127, 160, 162, 163, 183, 201, 203, 206, 207, 208, 209, 210, 214, 218, 238, 249, 272, 273, 274, 288, 298, 312, 313, 341, 342, 436, 439, 443, 476, 578, 602, 612, 661, 669, 687, 720, 722, 726, 757, 758, 766, 767, 768, 772, 774, 855, 860, 3, 8, 9, 18, 21, 22, 25, 27, 39, 40, 41, 43, 113, 163, 203, 214, 218, 272, 273, 274, 288, 312, 313, 341, 342, 436, 439, 577, 602, 612, 660, 668, 687, 720, 722, 726, 758, 764, 773, 774, 855, 860, 23, 73, 135, 136, 165, 181, 238, 421, 434, 435, 439, 639, 640, 641, 642, 643, 705, 655, 23, 3, 8, 9, 18, 21, 22, 25, 27, 39, 40, 41, 43, 86, 155, 163, 169, 203, 214, 218, 272, 273, 274, 288, 312, 313, 341, 342, 436, 439, 560, 561, 579, 602, 612, 657, 662, 670, 687, 720, 722, 855, 860, 706, 53, 88, 816, 817, 1, 31, 40, 78, 79, 705, 787, 788, 789, 790, 791, 793, 804, 852, 31, 46, 48, 49, 50, 61, 68, 76, 81, 112, 114, 123, 124, 125, 127, 134, 175, 186, 262, 263, 264, 267, 405, 467, 484, 485, 486, 494, 506, 508, 615, 621, 651, 705, 724, 725, 737, 738, 739, 744, 746, 747, 784, 836, 839, 840, 841, 842, 843, 853, 859, 131, 849, 706, 38, 534, 40, 873, 28, 26, 492, 694, 28, 706, 30, 38, 291, 292, 30, 26, 42, 37, 464, 706, 706, 31, 31, 31, 31, 630, 637, 1, 3, 8, 9, 18, 19, 21, 22, 25, 27, 31, 39, 40, 41, 43, 48, 49, 50, 53, 58, 70, 73, 75, 76, 80, 83, 85, 108, 114, 115, 116, 117, 118, 135, 136, 163, 165, 170, 177, 178, 181, 184, 185, 187, 203, 214, 218, 232, 233, 245, 246, 247, 250, 272, 273, 274, 293, 294, 298, 312, 313, 341, 342, 408, 409, 422, 428, 436, 439, 467, 519, 559, 562, 563, 564, 565, 566, 569, 570, 571, 572, 574, 576, 583, 602, 610, 611, 612, 613, 614, 633, 635, 636, 651, 656, 659, 665, 667, 687, 705, 720, 722, 736, 740, 741, 742, 744, 745, 747, 781, 819, 844, 855, 860, 93, 93, 705, 637, 617, 619, 620, 622, 365, 859, 31, 175, 176, 445, 446, 456, 457, 104, 31, 23, 672, 675, 23, 30, 33, 314, 315, 316, 317, 318, 319, 320, 321, 322, 323, 324, 24, 560, 437, 655, 674, 688, 688, 40, 254, 26, 42, 655, 675, 675, 675, 675, 705, 705, 26, 42, 26, 42, 30, 40, 344, 22, 873, 22, 655, 655, 655, 655, 655, 47, 164, 203, 232, 261, 612, 645, 647, 720, 860, 655, 655, 655, 655, 655, 655, 40, 40, 597, 655, 22, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 40, 83, 116, 127, 193, 232, 655, 879, 880, 655, 3, 8, 9, 18, 21, 22, 25, 27, 28, 39, 40, 41, 43, 44, 46, 107, 113, 160, 162, 163, 183, 201, 203, 206, 207, 208, 209, 210, 214, 218, 249, 272, 273, 274, 288, 312, 313, 341, 342, 436, 439, 561, 580, 602, 612, 663, 671, 677, 680, 682, 684, 686, 687, 720, 722, 726, 768, 771, 774, 855, 860, 677, 22, 31, 31, 38, 706, 441, 28, 554, 555, 705, 705, 157, 706, 229, 368, 369, 410, 411, 412, 439, 535, 23, 40, 372, 373, 374, 418, 421, 1, 45, 46, 61, 81, 82, 109, 114, 123, 127, 195, 196, 213, 349, 355, 362, 378, 388, 405, 422, 423, 478, 479, 480, 481, 482, 483, 484, 485, 486, 487, 489, 493, 505, 507, 539, 615, 696, 699, 702, 705, 724, 738, 111, 152, 349, 378, 380, 381, 382, 383, 388, 395, 396, 423, 483, 493, 48, 50, 76, 349, 390, 391, 392, 393, 394, 423, 484, 485, 486, 487, 493, 505, 507, 615, 705, 746, 38, 38, 33, 655, 23, 26, 417, 434, 435, 439, 443, 518, 519, 28, 655, 676, 679, 681, 683, 685, 33, 528, 421, 23, 26, 377, 705, 707, 755, 172, 189, 237, 238, 434, 439, 762, 763, 655, 655, 439, 669, 726, 768, 772, 655, 655, 655, 42, 654, 674, 655, 655, 22, 37, 772, 22, 128, 37, 22, 22, 37, 772, 772, 22, 22, 22, 22, 37, 37, 772, 37, 772, 705, 439, 475, 22, 655, 655, 655, 22, 8, 22, 37, 308, 311, 705, 655, 655, 22, 268, 602, 448, 312, 313, 602, 83, 768, 772, 100, 476, 766, 20, 21, 24, 25, 27, 28, 29, 31, 32, 34, 35, 39, 41, 47, 84, 128, 132, 137, 142, 151, 164, 211, 212, 219, 235, 236, 253, 268, 270, 271, 272, 273, 274, 275, 276, 277, 278, 279, 280, 281, 282, 284, 285, 286, 287, 290, 293, 297, 299, 300, 306, 307, 308, 309, 310, 311, 774, 777, 439, 773, 720, 720, 655, 655, 668, 773, 655, 655, 655, 42, 654, 674, 655, 655, 22, 705, 655, 655, 655, 22, 655, 655, 22, 268, 602, 312, 313, 602, 773, 773, 101, 20, 21, 24, 25, 27, 28, 29, 31, 32, 34, 35, 39, 41, 47, 84, 137, 142, 151, 164, 219, 253, 268, 270, 271, 272, 273, 274, 275, 276, 277, 278, 279, 280, 281, 282, 284, 285, 286, 287, 290, 293, 297, 774, 777, 773, 720, 720, 181, 439, 475, 528, 26, 643, 238, 434, 435, 439, 453, 31, 815, 657, 657, 560, 670, 657, 657, 657, 42, 654, 674, 657, 657, 655, 655, 655, 705, 657, 657, 657, 22, 655, 655, 22, 268, 602, 23, 26, 20, 21, 24, 25, 27, 28, 29, 32, 34, 35, 39, 41, 84, 128, 137, 151, 164, 268, 270, 271, 272, 273, 274, 275, 276, 277, 278, 279, 280, 281, 282, 284, 285, 286, 287, 290, 293, 297, 312, 313, 602, 720, 720, 22, 711, 715, 818, 818, 23, 164, 42, 55, 129, 130, 251, 705, 790, 794, 795, 797, 655, 706, 805, 807, 28, 30, 705, 95, 789, 31, 30, 705, 439, 562, 19, 112, 172, 743, 694, 172, 743, 22, 706, 172, 189, 743, 68, 83, 562, 22, 53, 94, 498, 500, 502, 504, 705, 841, 406, 407, 705, 68, 22, 562, 467, 172, 22, 644, 22, 644, 22, 644, 22, 644, 30, 726, 90, 841, 22, 857, 850, 853, 31, 194, 874, 875, 879, 716, 491, 365, 705, 22, 654, 654, 654, 654, 463, 527, 8, 466, 33, 465, 31, 31, 23, 31, 576, 656, 659, 667, 22, 520, 656, 655, 666, 656, 656, 656, 42, 654, 674, 656, 656, 22, 655, 22, 30, 31, 181, 31, 22, 40, 269, 439, 687, 708, 711, 118, 715, 562, 22, 22, 655, 22, 562, 30, 81, 590, 596, 655, 22, 708, 22, 31, 655, 705, 268, 22, 118, 22, 22, 656, 656, 656, 715, 185, 517, 519, 559, 8, 22, 705, 655, 655, 22, 31, 31, 443, 475, 268, 602, 562, 562, 88, 567, 568, 569, 570, 143, 567, 562, 31, 31, 61, 62, 63, 127, 585, 255, 258, 31, 570, 636, 20, 21, 24, 25, 27, 28, 29, 32, 34, 35, 39, 41, 84, 137, 151, 268, 270, 271, 272, 273, 274, 275, 276, 277, 278, 279, 280, 281, 283, 284, 285, 286, 287, 290, 293, 297, 33, 282, 314, 315, 316, 317, 318, 319, 320, 321, 322, 323, 324, 31, 312, 313, 602, 30, 705, 562, 720, 720, 723, 723, 23, 627, 31, 628, 31, 705, 42, 446, 245, 439, 442, 723, 23, 26, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 23, 23, 40, 42, 689, 42, 689, 674, 37, 691, 37, 23, 23, 23, 23, 597, 599, 655, 601, 597, 655, 655, 678, 655, 655, 655, 22, 258, 646, 705, 30, 37, 594, 655, 881, 882, 592, 593, 594, 655, 655, 878, 879, 193, 22, 22, 655, 40, 31, 655, 655, 671, 771, 655, 655, 706, 655, 42, 654, 674, 655, 655, 22, 37, 772, 37, 22, 37, 772, 772, 22, 22, 22, 22, 37, 37, 772, 37, 772, 705, 22, 655, 655, 655, 22, 655, 655, 22, 268, 602, 312, 313, 602, 23, 26, 26, 83, 771, 20, 21, 24, 25, 27, 28, 29, 32, 34, 35, 39, 41, 47, 84, 128, 132, 137, 142, 151, 164, 211, 212, 219, 235, 236, 253, 268, 270, 271, 272, 273, 274, 275, 276, 277, 278, 279, 280, 281, 282, 284, 285, 286, 287, 290, 293, 297, 299, 300, 306, 307, 774, 777, 773, 720, 720, 23, 677, 706, 445, 705, 23, 556, 557, 23, 26, 535, 372, 23, 26, 28, 140, 141, 377, 434, 435, 443, 705, 418, 31, 708, 562, 22, 68, 83, 537, 538, 715, 22, 53, 94, 111, 383, 482, 497, 499, 501, 503, 705, 22, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214, 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228, 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242, 243, 244, 245, 246, 247, 248, 249, 250, 251, 252, 253, 254, 255, 256, 257, 258, 259, 260, 261, 262, 263, 264, 265, 266, 267, 268, 269, 270, 271, 272, 273, 274, 275, 276, 277, 278, 279, 280, 281, 282, 283, 284, 285, 286, 287, 288, 289, 290, 291, 292, 293, 294, 295, 296, 297, 298, 299, 300, 301, 302, 303, 304, 305, 306, 307, 308, 309, 310, 311, 312, 313, 314, 315, 316, 317, 318, 319, 320, 321, 322, 323, 324, 325, 326, 327, 328, 329, 700, 701, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 98, 99, 100, 101, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214, 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228, 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242, 243, 244, 245, 246, 247, 248, 249, 250, 251, 252, 253, 254, 255, 256, 257, 258, 259, 260, 261, 262, 263, 264, 265, 266, 267, 268, 269, 270, 271, 272, 273, 274, 275, 276, 277, 278, 279, 280, 281, 282, 283, 284, 285, 286, 287, 288, 289, 290, 291, 292, 293, 294, 295, 296, 297, 298, 299, 300, 301, 302, 303, 304, 305, 306, 307, 308, 309, 310, 311, 312, 313, 314, 315, 316, 317, 318, 319, 320, 321, 322, 323, 324, 325, 326, 327, 328, 329, 703, 704, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214, 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228, 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242, 243, 244, 245, 246, 247, 248, 249, 250, 251, 252, 253, 254, 255, 256, 257, 258, 259, 260, 261, 262, 263, 264, 265, 266, 267, 268, 269, 270, 271, 272, 273, 274, 275, 276, 277, 278, 279, 280, 281, 282, 283, 284, 285, 286, 287, 288, 289, 290, 291, 292, 293, 294, 295, 296, 297, 298, 299, 300, 301, 302, 303, 304, 305, 306, 307, 308, 309, 310, 311, 312, 313, 314, 315, 316, 317, 318, 319, 320, 321, 322, 323, 324, 325, 326, 327, 328, 329, 697, 698, 375, 418, 31, 97, 480, 119, 619, 622, 397, 398, 400, 705, 96, 382, 31, 99, 392, 31, 30, 439, 559, 655, 673, 693, 528, 518, 706, 23, 26, 26, 157, 452, 581, 582, 655, 753, 453, 439, 475, 528, 33, 314, 315, 316, 317, 318, 319, 320, 321, 322, 323, 324, 83, 23, 26, 40, 42, 655, 654, 780, 655, 22, 654, 779, 773, 655, 655, 655, 773, 655, 655, 779, 780, 655, 655, 773, 655, 654, 780, 38, 344, 22, 31, 128, 723, 655, 655, 655, 655, 655, 203, 612, 645, 720, 655, 655, 655, 655, 655, 655, 772, 40, 772, 772, 40, 773, 597, 655, 772, 772, 772, 773, 772, 772, 773, 22, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 880, 655, 772, 772, 772, 772, 38, 654, 778, 780, 778, 778, 773, 33, 314, 315, 316, 317, 318, 319, 320, 321, 322, 323, 324, 23, 26, 40, 42, 773, 655, 655, 344, 22, 31, 723, 655, 655, 655, 655, 655, 203, 612, 645, 720, 655, 655, 655, 655, 655, 655, 773, 40, 40, 773, 597, 655, 773, 773, 773, 22, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 880, 655, 773, 640, 439, 475, 528, 526, 31, 23, 30, 33, 314, 315, 316, 317, 318, 319, 320, 321, 322, 323, 324, 40, 42, 128, 128, 128, 655, 655, 344, 22, 657, 657, 657, 657, 657, 657, 203, 612, 645, 720, 657, 657, 657, 657, 657, 657, 40, 655, 40, 214, 597, 657, 657, 22, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 880, 657, 637, 705, 852, 817, 797, 42, 795, 31, 705, 128, 792, 792, 26, 706, 78, 79, 30, 723, 78, 439, 705, 8, 22, 22, 518, 22, 22, 655, 22, 22, 22, 4, 705, 706, 128, 124, 509, 705, 30, 88, 502, 94, 500, 30, 26, 31, 526, 706, 655, 22, 675, 31, 675, 31, 675, 31, 675, 31, 744, 747, 31, 723, 676, 26, 1, 31, 51, 70, 111, 147, 173, 174, 198, 241, 349, 408, 409, 457, 468, 784, 845, 864, 865, 866, 867, 868, 869, 870, 871, 872, 884, 655, 666, 876, 877, 42, 875, 541, 543, 439, 653, 38, 38, 38, 38, 30, 38, 654, 31, 28, 521, 522, 655, 23, 30, 33, 314, 315, 316, 317, 318, 319, 320, 321, 322, 323, 324, 40, 42, 655, 33, 655, 706, 655, 708, 709, 708, 710, 269, 31, 269, 31, 31, 250, 83, 765, 772, 31, 238, 439, 603, 604, 605, 708, 33, 203, 218, 265, 705, 712, 717, 719, 721, 855, 860, 706, 30, 562, 81, 89, 596, 26, 30, 23, 705, 31, 655, 31, 655, 22, 655, 31, 713, 715, 655, 31, 22, 715, 655, 344, 429, 430, 22, 723, 88, 569, 570, 723, 143, 22, 22, 22, 22, 586, 873, 22, 656, 656, 656, 656, 656, 203, 581, 611, 612, 645, 720, 656, 656, 656, 656, 656, 656, 40, 40, 214, 597, 656, 22, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 880, 656, 517, 581, 582, 517, 736, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 572, 705, 22, 31, 22, 22, 31, 532, 447, 672, 30, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 690, 691, 42, 42, 42, 655, 655, 30, 26, 42, 345, 23, 23, 676, 22, 655, 655, 304, 305, 26, 42, 26, 42, 23, 42, 879, 655, 712, 655, 31, 592, 33, 314, 315, 316, 317, 318, 319, 320, 321, 322, 323, 324, 23, 26, 22, 40, 42, 655, 780, 779, 773, 655, 655, 773, 655, 655, 779, 780, 655, 655, 773, 655, 344, 22, 682, 684, 686, 128, 655, 655, 655, 655, 655, 203, 612, 645, 720, 655, 655, 655, 655, 655, 655, 771, 40, 771, 772, 40, 773, 597, 655, 771, 772, 772, 773, 772, 772, 773, 22, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 880, 655, 772, 772, 772, 772, 773, 23, 31, 42, 26, 28, 301, 439, 558, 655, 369, 42, 373, 377, 434, 28, 706, 453, 454, 28, 377, 28, 377, 28, 706, 33, 488, 655, 706, 128, 26, 31, 33, 509, 30, 88, 501, 94, 499, 30, 655, 701, 102, 701, 31, 704, 698, 103, 698, 427, 434, 435, 443, 723, 619, 31, 31, 26, 31, 22, 723, 723, 30, 23, 518, 22, 681, 683, 685, 37, 33, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 128, 573, 575, 608, 612, 655, 658, 664, 666, 775, 776, 674, 37, 23, 30, 38, 23, 655, 30, 38, 23, 26, 23, 38, 23, 23, 23, 23, 38, 38, 38, 23, 23, 30, 23, 38, 655, 655, 22, 30, 881, 592, 655, 38, 38, 38, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 775, 674, 37, 23, 26, 23, 30, 655, 655, 30, 881, 592, 655, 33, 787, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 674, 37, 655, 655, 655, 23, 30, 655, 655, 30, 881, 592, 705, 655, 23, 705, 31, 37, 796, 22, 793, 31, 40, 808, 807, 33, 655, 805, 78, 655, 705, 30, 765, 655, 515, 516, 708, 765, 655, 23, 765, 83, 726, 773, 655, 31, 655, 407, 31, 33, 706, 88, 53, 407, 23, 765, 23, 23, 23, 23, 81, 135, 136, 165, 727, 728, 729, 731, 737, 23, 853, 31, 174, 869, 884, 241, 884, 31, 31, 91, 866, 238, 357, 438, 470, 472, 477, 618, 621, 871, 69, 26, 52, 37, 548, 549, 550, 551, 552, 553, 705, 545, 546, 547, 705, 23, 26, 466, 633, 645, 30, 23, 26, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 674, 37, 23, 517, 23, 23, 26, 42, 26, 42, 710, 710, 22, 128, 23, 439, 706, 31, 655, 26, 31, 33, 655, 28, 28, 28, 23, 28, 37, 717, 717, 562, 30, 562, 30, 655, 562, 245, 439, 634, 705, 820, 821, 822, 23, 23, 612, 655, 23, 23, 26, 23, 655, 31, 23, 655, 450, 451, 705, 450, 655, 723, 723, 655, 655, 655, 655, 137, 151, 588, 590, 655, 31, 31, 31, 30, 881, 592, 705, 655, 655, 31, 31, 655, 655, 554, 637, 637, 448, 655, 26, 42, 42, 30, 38, 291, 292, 30, 38, 291, 292, 597, 655, 655, 23, 23, 655, 30, 655, 655, 882, 593, 31, 23, 23, 42, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 775, 23, 771, 674, 37, 23, 38, 38, 23, 26, 38, 23, 23, 23, 23, 38, 38, 38, 23, 23, 30, 655, 655, 22, 30, 881, 592, 655, 532, 558, 706, 707, 30, 22, 453, 454, 706, 453, 526, 28, 377, 377, 453, 377, 453, 706, 453, 708, 31, 33, 23, 31, 655, 538, 655, 31, 706, 88, 53, 23, 102, 103, 448, 528, 426, 424, 31, 398, 399, 655, 23, 655, 655, 616, 771, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 22, 28, 33, 314, 315, 316, 317, 318, 319, 320, 321, 322, 323, 324, 23, 26, 42, 655, 772, 654, 772, 81, 89, 596, 769, 770, 23, 654, 772, 775, 772, 772, 772, 772, 772, 772, 772, 772, 655, 345, 23, 655, 655, 42, 42, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 42, 655, 775, 655, 345, 23, 655, 42, 42, 23, 655, 95, 30, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 42, 655, 655, 345, 23, 657, 42, 42, 23, 796, 38, 655, 786, 33, 655, 42, 621, 790, 797, 809, 810, 811, 812, 26, 655, 792, 792, 655, 792, 30, 78, 23, 23, 26, 31, 33, 23, 23, 81, 89, 512, 514, 596, 23, 128, 83, 23, 23, 31, 33, 655, 654, 88, 502, 88, 502, 496, 498, 504, 23, 31, 31, 31, 31, 136, 165, 730, 86, 155, 169, 519, 734, 735, 734, 92, 729, 706, 732, 733, 619, 620, 622, 623, 624, 69, 69, 723, 625, 448, 706, 877, 876, 654, 26, 31, 554, 22, 553, 551, 26, 31, 551, 31, 439, 38, 521, 522, 30, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 42, 655, 87, 571, 584, 655, 584, 571, 708, 708, 42, 42, 655, 22, 584, 706, 33, 606, 607, 608, 31, 605, 655, 31, 717, 203, 717, 719, 571, 721, 654, 655, 562, 562, 705, 22, 101, 821, 30, 820, 562, 23, 28, 562, 584, 715, 562, 23, 345, 26, 31, 453, 31, 23, 23, 23, 23, 23, 81, 589, 591, 592, 587, 588, 89, 23, 656, 42, 42, 23, 31, 31, 23, 23, 23, 31, 23, 691, 37, 655, 655, 655, 655, 655, 655, 646, 23, 655, 880, 880, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 42, 655, 772, 772, 772, 775, 772, 772, 772, 772, 772, 772, 772, 655, 345, 23, 655, 655, 42, 42, 23, 22, 655, 376, 655, 28, 377, 706, 526, 33, 377, 453, 22, 526, 22, 526, 706, 526, 708, 81, 89, 511, 513, 596, 31, 655, 88, 501, 88, 501, 495, 497, 503, 425, 448, 448, 28, 68, 109, 133, 401, 402, 403, 421, 705, 30, 23, 38, 655, 645, 517, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 776, 42, 30, 38, 291, 292, 30, 772, 30, 26, 89, 767, 23, 87, 30, 23, 23, 42, 30, 38, 291, 292, 23, 30, 23, 723, 655, 42, 30, 38, 291, 292, 30, 23, 33, 38, 22, 40, 81, 799, 23, 706, 42, 810, 31, 806, 807, 793, 808, 792, 793, 78, 655, 584, 584, 516, 655, 584, 584, 30, 496, 89, 514, 30, 562, 22, 128, 571, 571, 654, 31, 723, 88, 723, 88, 87, 31, 735, 735, 31, 519, 519, 519, 165, 723, 33, 26, 31, 629, 31, 706, 706, 434, 439, 31, 31, 873, 31, 30, 38, 549, 23, 22, 546, 30, 23, 26, 655, 42, 30, 38, 291, 292, 571, 87, 31, 23, 655, 33, 655, 23, 26, 606, 28, 30, 26, 38, 291, 292, 22, 637, 40, 61, 127, 175, 185, 705, 823, 824, 825, 827, 830, 831, 833, 101, 31, 612, 559, 23, 451, 526, 562, 30, 562, 89, 81, 592, 30, 89, 31, 655, 38, 38, 38, 38, 38, 38, 38, 87, 42, 30, 38, 291, 292, 23, 30, 23, 23, 23, 439, 771, 30, 23, 377, 453, 453, 654, 22, 526, 376, 33, 376, 33, 453, 30, 495, 89, 513, 30, 31, 723, 88, 723, 88, 87, 448, 706, 706, 404, 624, 705, 404, 23, 26, 403, 655, 22, 23, 655, 37, 655, 655, 655, 772, 772, 770, 772, 655, 768, 772, 37, 655, 655, 655, 655, 23, 37, 655, 655, 655, 655, 40, 799, 37, 595, 786, 798, 800, 801, 802, 592, 189, 792, 26, 792, 33, 31, 26, 793, 655, 792, 496, 496, 655, 22, 312, 313, 510, 705, 723, 723, 496, 165, 734, 655, 733, 22, 31, 31, 31, 528, 654, 521, 522, 23, 37, 655, 655, 655, 571, 31, 23, 655, 562, 608, 23, 717, 654, 609, 705, 654, 654, 637, 23, 42, 467, 571, 828, 829, 22, 22, 143, 22, 22, 31, 41, 304, 831, 23, 33, 87, 562, 30, 562, 30, 562, 30, 38, 291, 292, 880, 37, 655, 655, 655, 655, 772, 23, 23, 30, 655, 526, 22, 526, 526, 376, 33, 23, 654, 23, 654, 526, 495, 495, 510, 723, 723, 495, 22, 402, 655, 655, 38, 38, 38, 31, 31, 23, 655, 38, 38, 38, 23, 655, 38, 38, 38, 23, 592, 792, 786, 26, 23, 295, 308, 309, 310, 42, 792, 22, 18, 22, 56, 258, 813, 807, 792, 793, 23, 655, 705, 705, 23, 33, 312, 313, 314, 315, 316, 317, 318, 319, 320, 321, 322, 323, 324, 735, 637, 38, 23, 655, 38, 38, 38, 772, 562, 38, 26, 38, 38, 38, 23, 42, 829, 655, 655, 22, 833, 655, 676, 824, 8, 22, 711, 826, 31, 655, 562, 562, 562, 655, 655, 655, 655, 38, 38, 38, 23, 655, 376, 33, 23, 654, 526, 526, 23, 23, 655, 23, 30, 38, 291, 292, 30, 38, 291, 292, 30, 38, 291, 292, 42, 30, 595, 801, 786, 803, 803, 803, 255, 792, 800, 56, 258, 813, 22, 22, 270, 271, 792, 793, 773, 23, 496, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 23, 30, 38, 291, 292, 705, 23, 23, 655, 832, 833, 23, 23, 655, 827, 38, 38, 38, 30, 38, 291, 292, 23, 30, 23, 654, 526, 495, 23, 655, 655, 655, 655, 655, 655, 655, 655, 655, 255, 792, 786, 30, 38, 38, 38, 40, 23, 22, 22, 23, 705, 814, 786, 813, 813, 23, 773, 31, 655, 655, 655, 81, 596, 834, 835, 833, 23, 833, 833, 23, 655, 655, 655, 655, 526, 38, 38, 38, 38, 38, 38, 38, 38, 38, 40, 38, 786, 786, 814, 786, 28, 23, 23, 571, 23, 38, 38, 38, 30, 833, 30, 89, 835, 87, 833, 38, 38, 38, 23, 786, 23, 23, 23, 706, 142, 571, 833, 31, 833, 833, 832, 23, 792, 142, 40, 31, 31, 792, 40, 798, 798, 42, 42 }; /* YYR1[RULE-NUM] -- Symbol kind of the left-hand side of rule RULE-NUM. */ static const yytype_int16 yyr1[] = { 0, 343, 344, 345, 346, 346, 347, 347, 348, 348, 348, 348, 348, 348, 348, 349, 349, 349, 350, 351, 352, 352, 353, 353, 354, 354, 354, 354, 355, 355, 355, 355, 355, 355, 355, 355, 355, 355, 355, 355, 355, 355, 356, 356, 357, 358, 358, 359, 360, 360, 361, 361, 362, 362, 363, 364, 364, 365, 365, 365, 366, 366, 367, 366, 368, 368, 369, 369, 370, 370, 371, 370, 372, 372, 373, 373, 373, 373, 373, 373, 373, 373, 373, 373, 373, 373, 373, 373, 373, 373, 373, 373, 373, 373, 373, 374, 374, 374, 374, 375, 375, 376, 376, 377, 377, 378, 378, 379, 380, 380, 381, 381, 382, 382, 382, 382, 382, 382, 382, 383, 383, 384, 385, 385, 386, 386, 387, 387, 387, 387, 387, 388, 388, 389, 390, 390, 391, 391, 392, 392, 393, 393, 393, 393, 393, 393, 393, 394, 394, 394, 394, 395, 395, 395, 396, 397, 397, 399, 398, 400, 401, 401, 402, 402, 402, 402, 402, 403, 403, 403, 404, 404, 405, 406, 406, 407, 408, 409, 410, 410, 410, 411, 411, 411, 412, 412, 412, 412, 413, 414, 414, 415, 416, 416, 416, 417, 417, 417, 417, 418, 418, 418, 418, 418, 418, 418, 418, 418, 418, 418, 419, 420, 421, 421, 421, 421, 421, 422, 422, 422, 422, 422, 424, 423, 425, 423, 426, 423, 427, 423, 429, 428, 430, 428, 431, 431, 431, 431, 431, 431, 432, 432, 432, 433, 433, 433, 434, 434, 435, 435, 436, 436, 436, 436, 436, 437, 437, 437, 437, 438, 438, 438, 439, 439, 439, 440, 439, 441, 439, 439, 439, 439, 439, 439, 439, 439, 439, 442, 442, 443, 443, 443, 444, 445, 445, 447, 446, 448, 448, 449, 449, 449, 449, 450, 450, 451, 451, 452, 452, 452, 453, 453, 454, 454, 455, 455, 455, 455, 455, 456, 456, 457, 457, 458, 458, 459, 459, 460, 461, 461, 461, 461, 461, 461, 461, 462, 462, 463, 464, 464, 464, 465, 465, 466, 467, 467, 467, 467, 468, 468, 468, 469, 470, 471, 471, 471, 471, 471, 471, 472, 472, 472, 472, 473, 473, 473, 474, 474, 475, 475, 475, 476, 477, 477, 477, 477, 477, 477, 477, 477, 478, 478, 479, 479, 480, 480, 481, 481, 481, 481, 481, 481, 481, 481, 482, 482, 482, 483, 483, 483, 483, 483, 483, 483, 483, 483, 483, 483, 483, 483, 484, 485, 486, 487, 487, 487, 487, 487, 488, 488, 489, 489, 490, 490, 491, 492, 493, 493, 494, 494, 495, 495, 496, 496, 497, 497, 497, 497, 497, 497, 498, 498, 498, 498, 498, 498, 499, 499, 500, 500, 501, 501, 502, 502, 503, 503, 504, 505, 505, 505, 505, 506, 506, 506, 506, 507, 508, 509, 509, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 511, 511, 512, 512, 513, 513, 513, 514, 514, 514, 515, 515, 516, 517, 517, 517, 517, 518, 518, 519, 519, 519, 519, 520, 520, 520, 520, 521, 522, 522, 523, 523, 524, 524, 524, 525, 525, 526, 527, 527, 528, 528, 529, 529, 530, 530, 531, 532, 532, 533, 533, 534, 534, 535, 535, 536, 536, 537, 537, 538, 540, 541, 539, 542, 543, 539, 544, 544, 545, 545, 546, 547, 548, 548, 549, 550, 550, 551, 551, 552, 552, 553, 553, 555, 554, 557, 556, 556, 558, 558, 558, 558, 558, 558, 558, 558, 558, 558, 558, 558, 558, 559, 559, 559, 559, 560, 560, 561, 561, 561, 561, 561, 561, 562, 563, 563, 564, 564, 565, 565, 566, 566, 567, 567, 567, 568, 568, 569, 569, 569, 569, 569, 570, 570, 571, 571, 571, 572, 572, 572, 572, 572, 572, 572, 572, 572, 572, 572, 572, 572, 572, 572, 572, 572, 572, 572, 572, 572, 572, 572, 572, 572, 572, 572, 572, 572, 572, 572, 572, 572, 572, 572, 572, 572, 572, 572, 572, 572, 572, 572, 572, 572, 572, 572, 572, 572, 572, 573, 573, 573, 573, 573, 573, 573, 573, 573, 573, 573, 573, 574, 574, 574, 574, 574, 574, 574, 574, 574, 574, 574, 574, 575, 575, 575, 575, 576, 576, 576, 576, 577, 577, 577, 577, 578, 578, 578, 578, 579, 579, 579, 579, 580, 580, 580, 580, 581, 581, 581, 582, 582, 583, 583, 583, 583, 584, 584, 584, 585, 585, 585, 586, 587, 588, 588, 589, 589, 590, 590, 590, 590, 590, 590, 591, 591, 591, 591, 591, 591, 592, 592, 593, 594, 594, 595, 595, 596, 596, 597, 597, 597, 598, 598, 599, 599, 599, 600, 600, 600, 600, 601, 601, 601, 602, 602, 602, 603, 603, 604, 604, 605, 605, 605, 606, 606, 607, 607, 608, 608, 608, 608, 608, 609, 609, 610, 610, 610, 611, 611, 611, 611, 612, 612, 612, 612, 613, 614, 614, 614, 614, 614, 614, 614, 614, 614, 614, 615, 615, 615, 615, 615, 615, 615, 615, 616, 617, 617, 618, 618, 619, 619, 620, 620, 621, 621, 621, 621, 622, 622, 623, 623, 624, 624, 625, 625, 626, 626, 627, 628, 628, 628, 628, 628, 629, 629, 629, 630, 630, 630, 631, 631, 632, 632, 633, 633, 633, 633, 634, 634, 635, 635, 636, 636, 638, 637, 639, 639, 640, 640, 640, 641, 641, 641, 641, 641, 641, 641, 641, 641, 641, 641, 642, 643, 643, 644, 644, 645, 645, 646, 646, 647, 647, 647, 647, 648, 648, 648, 648, 649, 649, 650, 650, 650, 651, 652, 652, 652, 652, 652, 652, 652, 652, 652, 652, 652, 652, 652, 652, 652, 653, 653, 654, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 655, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 656, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 657, 658, 658, 658, 658, 658, 658, 658, 658, 658, 658, 659, 659, 659, 659, 659, 659, 659, 659, 659, 659, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 661, 661, 661, 661, 661, 661, 661, 661, 661, 661, 662, 662, 662, 662, 662, 662, 662, 662, 662, 662, 663, 663, 663, 663, 663, 663, 663, 663, 663, 663, 664, 665, 666, 666, 666, 666, 666, 666, 666, 667, 667, 667, 667, 667, 667, 667, 668, 668, 668, 668, 668, 668, 668, 669, 669, 669, 669, 669, 669, 669, 670, 670, 670, 670, 670, 670, 670, 671, 671, 671, 671, 671, 671, 671, 672, 672, 672, 673, 673, 673, 673, 674, 674, 675, 675, 675, 676, 676, 676, 677, 677, 677, 678, 678, 679, 679, 680, 680, 681, 681, 682, 682, 683, 683, 684, 684, 685, 685, 686, 686, 687, 687, 687, 687, 688, 688, 689, 690, 690, 691, 691, 691, 691, 691, 692, 692, 692, 692, 692, 692, 692, 692, 692, 693, 693, 693, 694, 694, 695, 695, 696, 697, 697, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 699, 699, 700, 700, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 702, 703, 703, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 705, 706, 706, 706, 707, 707, 708, 708, 708, 708, 708, 708, 709, 709, 710, 710, 711, 711, 711, 711, 711, 711, 712, 712, 712, 712, 712, 712, 713, 713, 714, 715, 716, 716, 717, 717, 718, 718, 719, 719, 720, 720, 720, 720, 720, 721, 721, 721, 721, 721, 721, 722, 723, 723, 723, 724, 725, 725, 725, 725, 725, 725, 726, 726, 727, 727, 728, 728, 729, 729, 729, 730, 730, 730, 731, 731, 731, 731, 732, 732, 733, 733, 734, 734, 735, 735, 735, 735, 735, 735, 735, 736, 736, 736, 737, 737, 737, 738, 738, 739, 739, 740, 740, 740, 741, 741, 742, 742, 742, 743, 743, 744, 744, 744, 745, 746, 746, 747, 747, 747, 747, 747, 747, 747, 748, 749, 750, 751, 750, 752, 752, 753, 754, 754, 754, 754, 754, 754, 755, 755, 756, 756, 756, 757, 757, 758, 758, 759, 760, 761, 762, 762, 763, 763, 764, 764, 764, 764, 765, 765, 766, 766, 766, 766, 767, 767, 768, 768, 768, 768, 769, 769, 770, 770, 770, 770, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 771, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 772, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 773, 774, 774, 774, 774, 774, 774, 775, 775, 776, 777, 777, 777, 777, 777, 778, 778, 779, 780, 781, 782, 783, 783, 784, 784, 785, 786, 787, 787, 788, 788, 789, 789, 789, 789, 790, 791, 791, 791, 791, 791, 791, 791, 792, 792, 793, 793, 793, 794, 794, 795, 795, 795, 795, 795, 795, 795, 795, 795, 796, 796, 796, 797, 797, 797, 798, 798, 799, 799, 800, 800, 801, 801, 801, 801, 802, 803, 803, 804, 804, 805, 805, 806, 806, 807, 808, 808, 808, 809, 809, 810, 810, 811, 811, 812, 813, 813, 813, 813, 813, 813, 813, 813, 813, 814, 814, 815, 815, 815, 815, 816, 816, 817, 817, 818, 818, 818, 819, 819, 820, 820, 821, 822, 822, 822, 822, 823, 823, 824, 824, 824, 825, 825, 825, 826, 826, 826, 827, 827, 828, 828, 829, 829, 830, 830, 831, 831, 831, 831, 831, 831, 832, 832, 833, 833, 834, 834, 835, 835, 835, 836, 837, 838, 839, 839, 840, 840, 841, 841, 841, 841, 841, 841, 841, 842, 842, 842, 842, 842, 842, 842, 842, 842, 842, 842, 842, 843, 843, 843, 843, 844, 845, 846, 846, 847, 847, 848, 848, 848, 849, 849, 850, 850, 851, 852, 853, 854, 855, 856, 857, 857, 858, 859, 859, 861, 860, 862, 860, 863, 860, 864, 864, 865, 865, 866, 866, 866, 866, 866, 866, 866, 866, 866, 866, 867, 867, 867, 867, 868, 868, 868, 869, 869, 870, 870, 871, 871, 871, 871, 871, 871, 872, 872, 872, 872, 873, 874, 874, 875, 875, 876, 876, 877, 878, 878, 879, 879, 879, 879, 879, 879, 879, 880, 880, 881, 881, 882, 882, 882, 883, 884, 884 }; /* YYR2[RULE-NUM] -- Number of symbols on the right-hand side of rule RULE-NUM. */ static const yytype_int8 yyr2[] = { 0, 2, 0, 0, 0, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1, 3, 5, 3, 4, 4, 0, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 1, 1, 1, 1, 1, 2, 3, 1, 3, 3, 1, 1, 5, 3, 7, 5, 3, 1, 2, 0, 4, 2, 0, 3, 0, 5, 1, 3, 1, 2, 0, 3, 0, 4, 1, 3, 0, 5, 5, 7, 7, 8, 8, 9, 10, 7, 5, 5, 6, 7, 4, 7, 7, 8, 9, 6, 3, 0, 1, 2, 1, 0, 1, 0, 1, 1, 1, 7, 5, 3, 0, 1, 1, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 4, 0, 1, 1, 2, 1, 1, 1, 1, 1, 7, 5, 3, 0, 1, 1, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 3, 3, 4, 3, 1, 3, 0, 5, 1, 1, 3, 2, 2, 2, 2, 1, 1, 4, 5, 1, 1, 3, 1, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 3, 5, 4, 0, 0, 1, 1, 1, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, 0, 5, 0, 6, 0, 5, 0, 4, 0, 5, 0, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 1, 6, 5, 3, 2, 1, 0, 7, 0, 8, 1, 1, 1, 4, 3, 1, 1, 3, 1, 1, 1, 2, 2, 4, 1, 2, 0, 5, 1, 3, 3, 5, 1, 2, 1, 3, 3, 5, 1, 1, 1, 0, 1, 1, 2, 2, 1, 3, 2, 3, 0, 1, 1, 1, 0, 1, 0, 2, 6, 0, 2, 1, 2, 3, 2, 3, 1, 3, 3, 0, 3, 5, 0, 2, 1, 1, 1, 1, 1, 2, 2, 2, 3, 3, 4, 3, 5, 1, 2, 3, 3, 2, 4, 1, 4, 7, 5, 0, 1, 0, 2, 1, 3, 5, 7, 3, 4, 4, 4, 4, 5, 0, 1, 1, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 4, 1, 1, 2, 1, 1, 1, 2, 5, 2, 2, 1, 1, 1, 4, 5, 2, 3, 3, 5, 1, 3, 1, 1, 3, 2, 3, 2, 1, 1, 1, 1, 3, 2, 6, 5, 6, 5, 3, 2, 6, 5, 6, 5, 1, 1, 1, 1, 1, 2, 1, 2, 1, 1, 1, 5, 6, 5, 7, 5, 6, 5, 7, 9, 9, 3, 4, 0, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 1, 2, 1, 2, 3, 3, 2, 3, 3, 2, 1, 3, 3, 0, 1, 1, 5, 0, 1, 2, 4, 6, 8, 1, 1, 1, 1, 1, 1, 5, 1, 3, 2, 4, 3, 1, 1, 0, 0, 1, 1, 2, 0, 1, 0, 3, 5, 0, 1, 1, 2, 1, 2, 5, 3, 1, 3, 1, 3, 3, 0, 0, 7, 0, 0, 7, 1, 1, 1, 3, 1, 2, 1, 3, 3, 3, 2, 0, 1, 1, 2, 3, 5, 0, 2, 0, 2, 3, 0, 1, 2, 2, 4, 5, 7, 9, 5, 1, 1, 3, 5, 4, 2, 4, 2, 1, 3, 2, 4, 2, 4, 2, 4, 1, 4, 3, 4, 3, 1, 3, 1, 3, 1, 2, 1, 1, 2, 1, 2, 2, 1, 1, 1, 2, 1, 3, 1, 2, 4, 4, 5, 6, 3, 5, 3, 5, 6, 6, 6, 8, 2, 6, 8, 2, 4, 4, 2, 4, 3, 3, 3, 4, 2, 5, 5, 8, 7, 7, 5, 2, 3, 2, 2, 1, 2, 2, 2, 1, 5, 3, 5, 1, 5, 1, 3, 1, 2, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 2, 4, 4, 7, 0, 1, 1, 1, 1, 3, 2, 4, 4, 4, 0, 1, 0, 1, 0, 1, 3, 3, 2, 4, 3, 4, 3, 3, 2, 4, 3, 4, 1, 3, 1, 1, 5, 1, 5, 1, 3, 2, 1, 3, 1, 3, 1, 4, 1, 3, 3, 5, 5, 1, 1, 1, 3, 3, 2, 2, 1, 1, 3, 4, 5, 3, 0, 1, 1, 3, 1, 1, 1, 3, 1, 1, 3, 4, 5, 4, 1, 5, 1, 3, 1, 5, 1, 3, 1, 2, 4, 2, 4, 2, 4, 2, 4, 2, 4, 3, 5, 3, 5, 3, 5, 3, 5, 1, 1, 1, 6, 4, 5, 2, 1, 1, 6, 6, 4, 4, 5, 2, 6, 3, 1, 1, 0, 1, 1, 1, 1, 1, 3, 2, 2, 2, 1, 1, 2, 1, 3, 1, 5, 2, 4, 1, 0, 1, 2, 1, 1, 1, 1, 2, 1, 1, 0, 2, 1, 3, 0, 2, 1, 1, 2, 1, 2, 2, 1, 2, 3, 2, 3, 3, 1, 3, 5, 0, 2, 2, 5, 0, 4, 1, 1, 1, 1, 6, 6, 6, 6, 0, 2, 0, 1, 1, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 3, 1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 5, 5, 2, 3, 1, 1, 1, 1, 2, 6, 9, 11, 11, 11, 1, 3, 3, 3, 7, 6, 5, 5, 1, 1, 1, 3, 3, 3, 5, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 5, 5, 2, 3, 1, 1, 1, 1, 2, 6, 9, 11, 11, 11, 1, 3, 3, 3, 7, 6, 5, 5, 1, 1, 1, 3, 3, 3, 5, 1, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 5, 5, 2, 3, 1, 1, 1, 1, 2, 6, 9, 11, 11, 11, 1, 3, 3, 4, 8, 6, 5, 5, 1, 1, 1, 3, 3, 3, 5, 3, 7, 1, 3, 6, 8, 8, 8, 2, 2, 1, 1, 1, 3, 6, 8, 8, 8, 2, 2, 1, 1, 1, 3, 6, 8, 8, 8, 2, 2, 1, 1, 1, 3, 6, 8, 8, 8, 2, 2, 1, 1, 1, 3, 6, 8, 8, 8, 2, 2, 1, 1, 1, 3, 6, 8, 8, 8, 2, 2, 1, 1, 1, 1, 1, 1, 2, 2, 3, 3, 1, 1, 1, 2, 2, 3, 3, 1, 1, 1, 2, 2, 3, 3, 1, 1, 1, 2, 2, 3, 3, 1, 1, 1, 2, 2, 3, 3, 1, 1, 1, 2, 2, 3, 3, 1, 1, 1, 1, 1, 5, 1, 1, 1, 3, 1, 3, 2, 1, 1, 3, 1, 1, 3, 1, 3, 1, 3, 1, 3, 0, 1, 0, 1, 1, 3, 1, 3, 4, 5, 4, 5, 4, 4, 5, 5, 1, 1, 3, 1, 3, 1, 5, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 3, 5, 3, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 3, 1, 3, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 3, 1, 3, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 3, 4, 4, 3, 1, 1, 3, 1, 3, 1, 3, 3, 5, 2, 2, 1, 3, 3, 5, 2, 2, 1, 3, 1, 1, 3, 1, 3, 1, 1, 3, 1, 3, 1, 4, 6, 6, 6, 1, 4, 6, 6, 6, 6, 1, 0, 2, 2, 6, 1, 2, 2, 3, 2, 3, 2, 4, 0, 1, 1, 2, 3, 3, 1, 2, 2, 4, 2, 2, 4, 1, 1, 3, 1, 3, 0, 1, 1, 2, 1, 2, 1, 2, 1, 2, 2, 4, 1, 1, 1, 1, 1, 1, 3, 1, 1, 1, 1, 1, 5, 5, 5, 2, 1, 6, 6, 6, 5, 1, 3, 6, 6, 6, 6, 12, 11, 6, 6, 2, 0, 0, 4, 1, 3, 2, 2, 2, 3, 3, 3, 1, 2, 4, 0, 1, 2, 2, 1, 1, 2, 6, 2, 1, 1, 1, 1, 1, 2, 3, 1, 2, 6, 1, 1, 6, 2, 7, 2, 1, 6, 5, 5, 7, 1, 3, 3, 4, 2, 4, 1, 2, 4, 4, 3, 3, 1, 3, 3, 2, 2, 5, 5, 2, 5, 5, 2, 5, 5, 3, 3, 3, 3, 3, 3, 5, 5, 5, 5, 7, 2, 3, 2, 3, 5, 3, 3, 3, 4, 6, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 5, 5, 2, 3, 1, 1, 1, 1, 2, 6, 9, 11, 11, 11, 1, 3, 3, 4, 8, 6, 5, 5, 1, 1, 1, 3, 3, 3, 5, 2, 4, 4, 3, 3, 1, 3, 3, 2, 2, 5, 5, 2, 5, 5, 2, 5, 5, 3, 3, 3, 3, 3, 3, 5, 5, 5, 5, 7, 2, 3, 2, 3, 5, 3, 3, 3, 4, 6, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 5, 5, 2, 3, 1, 1, 1, 1, 2, 6, 9, 11, 11, 11, 1, 3, 3, 4, 8, 6, 5, 5, 1, 1, 1, 3, 3, 3, 5, 2, 3, 2, 3, 5, 3, 3, 3, 4, 6, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 5, 5, 2, 3, 1, 1, 1, 1, 2, 6, 9, 11, 11, 11, 1, 3, 3, 4, 8, 6, 5, 5, 1, 1, 1, 3, 3, 3, 5, 2, 2, 4, 4, 3, 2, 1, 3, 1, 3, 2, 1, 3, 3, 1, 1, 3, 3, 5, 2, 0, 3, 6, 9, 2, 1, 0, 1, 1, 2, 1, 1, 2, 1, 5, 4, 6, 6, 9, 8, 7, 1, 0, 4, 3, 2, 1, 2, 3, 1, 8, 9, 12, 13, 6, 7, 6, 7, 0, 2, 3, 1, 1, 1, 1, 3, 3, 5, 1, 3, 1, 4, 4, 4, 1, 1, 3, 6, 4, 3, 5, 1, 3, 1, 2, 3, 1, 2, 3, 1, 1, 1, 1, 5, 4, 8, 4, 5, 9, 5, 3, 3, 3, 1, 3, 0, 1, 6, 4, 1, 3, 2, 2, 1, 2, 2, 5, 6, 1, 2, 4, 2, 1, 5, 4, 1, 3, 1, 3, 4, 1, 4, 7, 1, 1, 3, 2, 3, 1, 2, 1, 1, 1, 2, 1, 1, 5, 7, 5, 6, 1, 2, 1, 4, 1, 2, 4, 3, 4, 6, 2, 1, 0, 1, 1, 2, 1, 1, 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1, 4, 5, 1, 1, 1, 1, 1, 6, 8, 4, 4, 0, 1, 0, 2, 5, 0, 2, 1, 3, 2, 2, 2, 1, 2, 2, 1, 2, 2, 0, 1, 0, 3, 0, 3, 0, 3, 0, 1, 1, 2, 1, 1, 1, 1, 1, 1, 2, 2, 1, 2, 2, 2, 4, 3, 1, 1, 1, 0, 1, 1, 2, 1, 1, 2, 1, 1, 1, 4, 4, 5, 5, 3, 1, 2, 5, 1, 1, 3, 1, 1, 2, 2, 3, 4, 5, 7, 5, 4, 1, 3, 1, 3, 1, 3, 3, 4, 0, 1 }; enum { YYENOMEM = -2 }; #define yyerrok (yyerrstatus = 0) #define yyclearin (yychar = YYEMPTY) #define YYACCEPT goto yyacceptlab #define YYABORT goto yyabortlab #define YYERROR goto yyerrorlab #define YYNOMEM goto yyexhaustedlab #define YYRECOVERING() (!!yyerrstatus) #define YYBACKUP(Token, Value) \ do \ if (yychar == YYEMPTY) \ { \ yychar = (Token); \ yylval = (Value); \ YYPOPSTACK (yylen); \ yystate = *yyssp; \ goto yybackup; \ } \ else \ { \ yyerror (YY_((char*)"syntax error: cannot back up")); \ YYERROR; \ } \ while (0) /* Backward compatibility with an undocumented macro. Use YYerror or YYUNDEF. */ #define YYERRCODE YYUNDEF /* Enable debugging if requested. */ #if YYDEBUG # ifndef YYFPRINTF # include /* INFRINGES ON USER NAME SPACE */ # define YYFPRINTF fprintf # endif # define YYDPRINTF(Args) \ do { \ if (yydebug) \ YYFPRINTF Args; \ } while (0) # define YY_SYMBOL_PRINT(Title, Kind, Value, Location) \ do { \ if (yydebug) \ { \ YYFPRINTF (stderr, "%s ", Title); \ yy_symbol_print (stderr, \ Kind, Value); \ YYFPRINTF (stderr, "\n"); \ } \ } while (0) /*-----------------------------------. | Print this symbol's value on YYO. | `-----------------------------------*/ static void yy_symbol_value_print (FILE *yyo, yysymbol_kind_t yykind, YYSTYPE const * const yyvaluep) { FILE *yyoutput = yyo; YY_USE (yyoutput); if (!yyvaluep) return; YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN YY_USE (yykind); YY_IGNORE_MAYBE_UNINITIALIZED_END } /*---------------------------. | Print this symbol on YYO. | `---------------------------*/ static void yy_symbol_print (FILE *yyo, yysymbol_kind_t yykind, YYSTYPE const * const yyvaluep) { YYFPRINTF (yyo, "%s %s (", yykind < YYNTOKENS ? "token" : "nterm", yysymbol_name (yykind)); yy_symbol_value_print (yyo, yykind, yyvaluep); YYFPRINTF (yyo, ")"); } /*------------------------------------------------------------------. | yy_stack_print -- Print the state stack from its BOTTOM up to its | | TOP (included). | `------------------------------------------------------------------*/ static void yy_stack_print (yy_state_t *yybottom, yy_state_t *yytop) { YYFPRINTF (stderr, "Stack now"); for (; yybottom <= yytop; yybottom++) { int yybot = *yybottom; YYFPRINTF (stderr, " %d", yybot); } YYFPRINTF (stderr, "\n"); } # define YY_STACK_PRINT(Bottom, Top) \ do { \ if (yydebug) \ yy_stack_print ((Bottom), (Top)); \ } while (0) /*------------------------------------------------. | Report that the YYRULE is going to be reduced. | `------------------------------------------------*/ static void yy_reduce_print (yy_state_t *yyssp, YYSTYPE *yyvsp, int yyrule) { int yylno = yyrline[yyrule]; int yynrhs = yyr2[yyrule]; int yyi; YYFPRINTF (stderr, "Reducing stack by rule %d (line %d):\n", yyrule - 1, yylno); /* The symbols being reduced. */ for (yyi = 0; yyi < yynrhs; yyi++) { YYFPRINTF (stderr, " $%d = ", yyi + 1); yy_symbol_print (stderr, YY_ACCESSING_SYMBOL (+yyssp[yyi + 1 - yynrhs]), &yyvsp[(yyi + 1) - (yynrhs)]); YYFPRINTF (stderr, "\n"); } } # define YY_REDUCE_PRINT(Rule) \ do { \ if (yydebug) \ yy_reduce_print (yyssp, yyvsp, Rule); \ } while (0) /* Nonzero means print parse trace. It is left uninitialized so that multiple parsers can coexist. */ int yydebug; #else /* !YYDEBUG */ # define YYDPRINTF(Args) ((void) 0) # define YY_SYMBOL_PRINT(Title, Kind, Value, Location) # define YY_STACK_PRINT(Bottom, Top) # define YY_REDUCE_PRINT(Rule) #endif /* !YYDEBUG */ /* YYINITDEPTH -- initial size of the parser's stacks. */ #ifndef YYINITDEPTH # define YYINITDEPTH 200 #endif /* YYMAXDEPTH -- maximum size the stacks can grow to (effective only if the built-in stack extension method is used). Do not make this value too large; the results are undefined if YYSTACK_ALLOC_MAXIMUM < YYSTACK_BYTES (YYMAXDEPTH) evaluated with infinite-precision integer arithmetic. */ #ifndef YYMAXDEPTH # define YYMAXDEPTH 10000 #endif /*-----------------------------------------------. | Release the memory associated to this symbol. | `-----------------------------------------------*/ static void yydestruct (const char *yymsg, yysymbol_kind_t yykind, YYSTYPE *yyvaluep) { YY_USE (yyvaluep); if (!yymsg) yymsg = "Deleting"; YY_SYMBOL_PRINT (yymsg, yykind, yyvaluep, yylocationp); YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN YY_USE (yykind); YY_IGNORE_MAYBE_UNINITIALIZED_END } /*----------. | yyparse. | `----------*/ int yyparse (void) { /* Lookahead token kind. */ int yychar; /* The semantic value of the lookahead symbol. */ /* Default value used for initialization, for pacifying older GCCs or non-GCC compilers. */ YY_INITIAL_VALUE (static YYSTYPE yyval_default;) YYSTYPE yylval YY_INITIAL_VALUE (= yyval_default); /* Number of syntax errors so far. */ int yynerrs = 0; yy_state_fast_t yystate = 0; /* Number of tokens to shift before error messages enabled. */ int yyerrstatus = 0; /* Refer to the stacks through separate pointers, to allow yyoverflow to reallocate them elsewhere. */ /* Their size. */ YYPTRDIFF_T yystacksize = YYINITDEPTH; /* The state stack: array, bottom, top. */ yy_state_t yyssa[YYINITDEPTH]; yy_state_t *yyss = yyssa; yy_state_t *yyssp = yyss; /* The semantic value stack: array, bottom, top. */ YYSTYPE yyvsa[YYINITDEPTH]; YYSTYPE *yyvs = yyvsa; YYSTYPE *yyvsp = yyvs; int yyn; /* The return value of yyparse. */ int yyresult; /* Lookahead symbol kind. */ yysymbol_kind_t yytoken = YYSYMBOL_YYEMPTY; /* The variables used to return semantic value and location from the action routines. */ YYSTYPE yyval; #define YYPOPSTACK(N) (yyvsp -= (N), yyssp -= (N)) /* The number of symbols on the RHS of the reduced rule. Keep to zero when no symbol should be popped. */ int yylen = 0; YYDPRINTF ((stderr, "Starting parse\n")); yychar = YYEMPTY; /* Cause a token to be read. */ goto yysetstate; /*------------------------------------------------------------. | yynewstate -- push a new state, which is found in yystate. | `------------------------------------------------------------*/ yynewstate: /* In all cases, when you get here, the value and location stacks have just been pushed. So pushing a state here evens the stacks. */ yyssp++; /*--------------------------------------------------------------------. | yysetstate -- set current state (the top of the stack) to yystate. | `--------------------------------------------------------------------*/ yysetstate: YYDPRINTF ((stderr, "Entering state %d\n", yystate)); YY_ASSERT (0 <= yystate && yystate < YYNSTATES); YY_IGNORE_USELESS_CAST_BEGIN *yyssp = YY_CAST (yy_state_t, yystate); YY_IGNORE_USELESS_CAST_END YY_STACK_PRINT (yyss, yyssp); if (yyss + yystacksize - 1 <= yyssp) #if !defined yyoverflow && !defined YYSTACK_RELOCATE YYNOMEM; #else { /* Get the current used size of the three stacks, in elements. */ YYPTRDIFF_T yysize = yyssp - yyss + 1; # if defined yyoverflow { /* Give user a chance to reallocate the stack. Use copies of these so that the &'s don't force the real ones into memory. */ yy_state_t *yyss1 = yyss; YYSTYPE *yyvs1 = yyvs; /* Each stack pointer address is followed by the size of the data in use in that stack, in bytes. This used to be a conditional around just the two extra args, but that might be undefined if yyoverflow is a macro. */ yyoverflow (YY_((char*)"memory exhausted"), &yyss1, yysize * YYSIZEOF (*yyssp), &yyvs1, yysize * YYSIZEOF (*yyvsp), &yystacksize); yyss = yyss1; yyvs = yyvs1; } # else /* defined YYSTACK_RELOCATE */ /* Extend the stack our own way. */ if (YYMAXDEPTH <= yystacksize) YYNOMEM; yystacksize *= 2; if (YYMAXDEPTH < yystacksize) yystacksize = YYMAXDEPTH; { yy_state_t *yyss1 = yyss; union yyalloc *yyptr = YY_CAST (union yyalloc *, YYSTACK_ALLOC (YY_CAST (YYSIZE_T, YYSTACK_BYTES (yystacksize)))); if (! yyptr) YYNOMEM; YYSTACK_RELOCATE (yyss_alloc, yyss); YYSTACK_RELOCATE (yyvs_alloc, yyvs); # undef YYSTACK_RELOCATE if (yyss1 != yyssa) YYSTACK_FREE (yyss1); } # endif yyssp = yyss + yysize - 1; yyvsp = yyvs + yysize - 1; YY_IGNORE_USELESS_CAST_BEGIN YYDPRINTF ((stderr, "Stack size increased to %ld\n", YY_CAST (long, yystacksize))); YY_IGNORE_USELESS_CAST_END if (yyss + yystacksize - 1 <= yyssp) YYABORT; } #endif /* !defined yyoverflow && !defined YYSTACK_RELOCATE */ if (yystate == YYFINAL) YYACCEPT; goto yybackup; /*-----------. | yybackup. | `-----------*/ yybackup: /* Do appropriate processing given the current state. Read a lookahead token if we need one and don't already have one. */ /* First try to decide what to do without reference to lookahead token. */ yyn = yypact[yystate]; if (yypact_value_is_default (yyn)) goto yydefault; /* Not known => get a lookahead token if don't already have one. */ /* YYCHAR is either empty, or end-of-input, or a valid lookahead. */ if (yychar == YYEMPTY) { YYDPRINTF ((stderr, "Reading a token\n")); yychar = yylex (&yylval); } if (yychar <= YYEOF) { yychar = YYEOF; yytoken = YYSYMBOL_YYEOF; YYDPRINTF ((stderr, "Now at end of input.\n")); } else if (yychar == YYerror) { /* The scanner already issued an error message, process directly to error recovery. But do not keep the error token as lookahead, it is too special and may lead us to an endless loop in error recovery. */ yychar = YYUNDEF; yytoken = YYSYMBOL_YYerror; goto yyerrlab1; } else { yytoken = YYTRANSLATE (yychar); YY_SYMBOL_PRINT ("Next token is", yytoken, &yylval, &yylloc); } /* If the proper action on seeing token YYTOKEN is to reduce or to detect an error, take that action. */ yyn += yytoken; if (yyn < 0 || YYLAST < yyn || yycheck[yyn] != yytoken) goto yydefault; yyn = yytable[yyn]; if (yyn <= 0) { if (yytable_value_is_error (yyn)) goto yyerrlab; yyn = -yyn; goto yyreduce; } /* Count tokens shifted since error; after three, turn off error status. */ if (yyerrstatus) yyerrstatus--; /* Shift the lookahead token. */ YY_SYMBOL_PRINT ("Shifting", yytoken, &yylval, &yylloc); yystate = yyn; YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN *++yyvsp = yylval; YY_IGNORE_MAYBE_UNINITIALIZED_END /* Discard the shifted token. */ yychar = YYEMPTY; goto yynewstate; /*-----------------------------------------------------------. | yydefault -- do the default action for the current state. | `-----------------------------------------------------------*/ yydefault: yyn = yydefact[yystate]; if (yyn == 0) goto yyerrlab; goto yyreduce; /*-----------------------------. | yyreduce -- do a reduction. | `-----------------------------*/ yyreduce: /* yyn is the number of a rule to reduce with. */ yylen = yyr2[yyn]; /* If YYLEN is nonzero, implement the default value of the action: '$$ = $1'. Otherwise, the following line sets YYVAL to garbage. This behavior is undocumented and Bison users should not rely upon it. Assigning to YYVAL unconditionally makes the parser a bit smaller, and it avoids a GCC warning that YYVAL may be used uninitialized. */ yyval = yyvsp[1-yylen]; YY_REDUCE_PRINT (yyn); switch (yyn) { case 2: /* statePushVlg: %empty */ #line 800 "VParseBison.y" { } #line 21226 "VParseBison.c" break; case 3: /* statePop: %empty */ #line 803 "VParseBison.y" { } #line 21232 "VParseBison.c" break; case 4: /* source_text: %empty */ #line 810 "VParseBison.y" { } #line 21238 "VParseBison.c" break; case 5: /* source_text: descriptionList */ #line 812 "VParseBison.y" { } #line 21244 "VParseBison.c" break; case 6: /* descriptionList: description */ #line 816 "VParseBison.y" { } #line 21250 "VParseBison.c" break; case 7: /* descriptionList: descriptionList description */ #line 817 "VParseBison.y" { } #line 21256 "VParseBison.c" break; case 8: /* description: module_declaration */ #line 821 "VParseBison.y" { } #line 21262 "VParseBison.c" break; case 9: /* description: interface_declaration */ #line 823 "VParseBison.y" { } #line 21268 "VParseBison.c" break; case 10: /* description: program_declaration */ #line 824 "VParseBison.y" { } #line 21274 "VParseBison.c" break; case 11: /* description: package_declaration */ #line 825 "VParseBison.y" { } #line 21280 "VParseBison.c" break; case 12: /* description: package_item */ #line 826 "VParseBison.y" { } #line 21286 "VParseBison.c" break; case 13: /* description: bind_directive */ #line 827 "VParseBison.y" { } #line 21292 "VParseBison.c" break; case 14: /* description: error */ #line 829 "VParseBison.y" { } #line 21298 "VParseBison.c" break; case 15: /* timeunits_declaration: "timeunit" "TIME NUMBER" ';' */ #line 833 "VParseBison.y" { } #line 21304 "VParseBison.c" break; case 16: /* timeunits_declaration: "timeunit" "TIME NUMBER" '/' "TIME NUMBER" ';' */ #line 834 "VParseBison.y" { NEED_S09((yyvsp[-4].fl),"timeunit /"); } #line 21310 "VParseBison.c" break; case 17: /* timeunits_declaration: "timeprecision" "TIME NUMBER" ';' */ #line 835 "VParseBison.y" { } #line 21316 "VParseBison.c" break; case 18: /* package_declaration: packageFront package_itemListE "endpackage" endLabelE */ #line 843 "VParseBison.y" { PARSEP->endpackageCb((yyvsp[-1].fl),(yyvsp[-1].str)); PARSEP->symPopScope(VAstType::PACKAGE); } #line 21323 "VParseBison.c" break; case 19: /* packageFront: "package" lifetimeE idAny ';' */ #line 850 "VParseBison.y" { PARSEP->symPushNew(VAstType::PACKAGE, (yyvsp[-1].str)); PARSEP->packageCb((yyvsp[-3].fl),(yyvsp[-3].str), (yyvsp[-1].str)); } #line 21330 "VParseBison.c" break; case 20: /* package_itemListE: %empty */ #line 855 "VParseBison.y" { } #line 21336 "VParseBison.c" break; case 21: /* package_itemListE: package_itemList */ #line 856 "VParseBison.y" { } #line 21342 "VParseBison.c" break; case 22: /* package_itemList: package_item */ #line 860 "VParseBison.y" { } #line 21348 "VParseBison.c" break; case 23: /* package_itemList: package_itemList package_item */ #line 861 "VParseBison.y" { } #line 21354 "VParseBison.c" break; case 24: /* package_item: package_or_generate_item_declaration */ #line 865 "VParseBison.y" { } #line 21360 "VParseBison.c" break; case 25: /* package_item: anonymous_program */ #line 866 "VParseBison.y" { } #line 21366 "VParseBison.c" break; case 26: /* package_item: package_export_declaration */ #line 867 "VParseBison.y" { } #line 21372 "VParseBison.c" break; case 27: /* package_item: timeunits_declaration */ #line 868 "VParseBison.y" { } #line 21378 "VParseBison.c" break; case 28: /* package_or_generate_item_declaration: net_declaration */ #line 872 "VParseBison.y" { } #line 21384 "VParseBison.c" break; case 29: /* package_or_generate_item_declaration: data_declaration */ #line 873 "VParseBison.y" { } #line 21390 "VParseBison.c" break; case 30: /* package_or_generate_item_declaration: task_declaration */ #line 874 "VParseBison.y" { } #line 21396 "VParseBison.c" break; case 31: /* package_or_generate_item_declaration: function_declaration */ #line 875 "VParseBison.y" { } #line 21402 "VParseBison.c" break; case 32: /* package_or_generate_item_declaration: checker_declaration */ #line 876 "VParseBison.y" { } #line 21408 "VParseBison.c" break; case 33: /* package_or_generate_item_declaration: dpi_import_export */ #line 877 "VParseBison.y" { } #line 21414 "VParseBison.c" break; case 34: /* package_or_generate_item_declaration: extern_constraint_declaration */ #line 878 "VParseBison.y" { } #line 21420 "VParseBison.c" break; case 35: /* package_or_generate_item_declaration: class_declaration */ #line 879 "VParseBison.y" { } #line 21426 "VParseBison.c" break; case 36: /* package_or_generate_item_declaration: local_parameter_declaration ';' */ #line 881 "VParseBison.y" { } #line 21432 "VParseBison.c" break; case 37: /* package_or_generate_item_declaration: parameter_declaration ';' */ #line 882 "VParseBison.y" { } #line 21438 "VParseBison.c" break; case 38: /* package_or_generate_item_declaration: covergroup_declaration */ #line 883 "VParseBison.y" { } #line 21444 "VParseBison.c" break; case 39: /* package_or_generate_item_declaration: overload_declaration */ #line 884 "VParseBison.y" { } #line 21450 "VParseBison.c" break; case 40: /* package_or_generate_item_declaration: assertion_item_declaration */ #line 885 "VParseBison.y" { } #line 21456 "VParseBison.c" break; case 41: /* package_or_generate_item_declaration: ';' */ #line 886 "VParseBison.y" { } #line 21462 "VParseBison.c" break; case 42: /* package_import_declarationList: package_import_declaration */ #line 890 "VParseBison.y" { } #line 21468 "VParseBison.c" break; case 43: /* package_import_declarationList: package_import_declarationList package_import_declaration */ #line 891 "VParseBison.y" { } #line 21474 "VParseBison.c" break; case 44: /* package_import_declaration: "import" package_import_itemList ';' */ #line 895 "VParseBison.y" { } #line 21480 "VParseBison.c" break; case 45: /* package_import_itemList: package_import_item */ #line 899 "VParseBison.y" { } #line 21486 "VParseBison.c" break; case 46: /* package_import_itemList: package_import_itemList ',' package_import_item */ #line 900 "VParseBison.y" { } #line 21492 "VParseBison.c" break; case 47: /* package_import_item: "PACKAGE-IDENTIFIER" "::" package_import_itemObj */ #line 905 "VParseBison.y" { PARSEP->syms().import((yyvsp[-2].fl),(yyvsp[-2].str),(yyvsp[0].str)); PARSEP->importCb((yyvsp[-2].fl),(yyvsp[-2].str),(yyvsp[0].str)); } #line 21499 "VParseBison.c" break; case 48: /* package_import_itemObj: idAny */ #line 910 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 21505 "VParseBison.c" break; case 49: /* package_import_itemObj: '*' */ #line 911 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 21511 "VParseBison.c" break; case 50: /* package_export_declaration: "export" '*' "::" '*' ';' */ #line 915 "VParseBison.y" { } #line 21517 "VParseBison.c" break; case 51: /* package_export_declaration: "export" package_import_itemList ';' */ #line 916 "VParseBison.y" { } #line 21523 "VParseBison.c" break; case 52: /* module_declaration: modFront importsAndParametersE portsStarE ';' module_itemListE "endmodule" endLabelE */ #line 927 "VParseBison.y" { PARSEP->endmoduleCb((yyvsp[-1].fl),(yyvsp[-1].str)); PARSEP->symPopScope(VAstType::MODULE); } #line 21530 "VParseBison.c" break; case 53: /* module_declaration: "extern" modFront importsAndParametersE portsStarE ';' */ #line 931 "VParseBison.y" { PARSEP->symPopScope(VAstType::MODULE); } #line 21536 "VParseBison.c" break; case 54: /* modFront: "module" lifetimeE idAny */ #line 938 "VParseBison.y" { PARSEP->symPushNew(VAstType::MODULE, (yyvsp[0].str)); PARSEP->moduleCb((yyvsp[-2].fl),(yyvsp[-2].str),(yyvsp[0].str),false,PARSEP->inCellDefine()); } #line 21543 "VParseBison.c" break; case 55: /* importsAndParametersE: parameter_port_listE */ #line 944 "VParseBison.y" { } #line 21549 "VParseBison.c" break; case 56: /* importsAndParametersE: package_import_declarationList parameter_port_listE */ #line 945 "VParseBison.y" { } #line 21555 "VParseBison.c" break; case 57: /* parameter_value_assignmentE: %empty */ #line 949 "VParseBison.y" { } #line 21561 "VParseBison.c" break; case 58: /* parameter_value_assignmentE: '#' '(' cellpinList ')' */ #line 950 "VParseBison.y" { } #line 21567 "VParseBison.c" break; case 59: /* parameter_value_assignmentE: '#' delay_value */ #line 952 "VParseBison.y" { } #line 21573 "VParseBison.c" break; case 60: /* parameter_port_listE: %empty */ #line 956 "VParseBison.y" { } #line 21579 "VParseBison.c" break; case 61: /* parameter_port_listE: '#' '(' ')' */ #line 957 "VParseBison.y" { } #line 21585 "VParseBison.c" break; case 62: /* $@1: %empty */ #line 962 "VParseBison.y" {VARRESET_LIST("parameter");} #line 21591 "VParseBison.c" break; case 63: /* parameter_port_listE: '#' '(' $@1 paramPortDeclOrArgList ')' */ #line 962 "VParseBison.y" { VARRESET_NONLIST(""); } #line 21597 "VParseBison.c" break; case 64: /* paramPortDeclOrArgList: paramPortDeclOrArg */ #line 967 "VParseBison.y" { } #line 21603 "VParseBison.c" break; case 65: /* paramPortDeclOrArgList: paramPortDeclOrArgList ',' paramPortDeclOrArg */ #line 968 "VParseBison.y" { } #line 21609 "VParseBison.c" break; case 66: /* paramPortDeclOrArg: param_assignment */ #line 973 "VParseBison.y" { } #line 21615 "VParseBison.c" break; case 67: /* paramPortDeclOrArg: parameter_port_declarationFront param_assignment */ #line 974 "VParseBison.y" { } #line 21621 "VParseBison.c" break; case 68: /* portsStarE: %empty */ #line 978 "VParseBison.y" { } #line 21627 "VParseBison.c" break; case 69: /* portsStarE: '(' ".*" ')' */ #line 981 "VParseBison.y" { } #line 21633 "VParseBison.c" break; case 70: /* $@2: %empty */ #line 982 "VParseBison.y" {VARRESET_LIST("");} #line 21639 "VParseBison.c" break; case 71: /* portsStarE: '(' $@2 list_of_portsE ')' */ #line 982 "VParseBison.y" { VARRESET_NONLIST(""); } #line 21645 "VParseBison.c" break; case 72: /* list_of_portsE: portE */ #line 986 "VParseBison.y" { } #line 21651 "VParseBison.c" break; case 73: /* list_of_portsE: list_of_portsE ',' portE */ #line 987 "VParseBison.y" { } #line 21657 "VParseBison.c" break; case 74: /* portE: %empty */ #line 997 "VParseBison.y" { } #line 21663 "VParseBison.c" break; case 75: /* portE: portDirNetE id idAny variable_dimensionListE sigAttrListE */ #line 999 "VParseBison.y" { VARDTYPE((yyvsp[-3].str)); VARIO("interface"); VARDONE((yyvsp[-3].fl), (yyvsp[-2].str), (yyvsp[-1].str), ""); PINNUMINC(); PARSEP->instantCb((yyvsp[-3].fl), (yyvsp[-3].str), (yyvsp[-2].str), (yyvsp[-1].str)); PARSEP->endcellCb((yyvsp[-3].fl),""); } #line 21670 "VParseBison.c" break; case 76: /* portE: portDirNetE "interface" idAny variable_dimensionListE sigAttrListE */ #line 1002 "VParseBison.y" { VARDTYPE((yyvsp[-3].str)); VARIO("interface"); VARDONE((yyvsp[-3].fl), (yyvsp[-2].str), (yyvsp[-1].str), ""); PINNUMINC(); } #line 21676 "VParseBison.c" break; case 77: /* portE: portDirNetE id '.' idAny idAny variable_dimensionListE sigAttrListE */ #line 1004 "VParseBison.y" { VARDTYPE((yyvsp[-5].str)+"."+(yyvsp[-3].str)); VARIO("interface"); VARDONE((yyvsp[-5].fl), (yyvsp[-2].str), (yyvsp[-1].str), ""); PINNUMINC(); PARSEP->instantCb((yyvsp[-5].fl), (yyvsp[-5].str), (yyvsp[-2].str), (yyvsp[-1].str)); PARSEP->endcellCb((yyvsp[-5].fl),""); } #line 21683 "VParseBison.c" break; case 78: /* portE: portDirNetE "interface" '.' idAny idAny variable_dimensionListE sigAttrListE */ #line 1007 "VParseBison.y" { VARDTYPE((yyvsp[-5].str)+"."+(yyvsp[-3].str)); VARIO("interface"); VARDONE((yyvsp[-5].fl), (yyvsp[-2].str), (yyvsp[-1].str), ""); PINNUMINC(); } #line 21689 "VParseBison.c" break; case 79: /* portE: portDirNetE var_data_type '.' portSig '(' portAssignExprE ')' sigAttrListE */ #line 1037 "VParseBison.y" { VARDTYPE((yyvsp[-6].str)); VARDONE((yyvsp[-4].fl), (yyvsp[-4].str), "", ""); PINNUMINC(); } #line 21695 "VParseBison.c" break; case 80: /* portE: portDirNetE signing '.' portSig '(' portAssignExprE ')' sigAttrListE */ #line 1039 "VParseBison.y" { VARDTYPE((yyvsp[-6].str)); VARDONE((yyvsp[-4].fl), (yyvsp[-4].str), "", ""); PINNUMINC(); } #line 21701 "VParseBison.c" break; case 81: /* portE: portDirNetE signingE variable_dimensionList '.' portSig '(' portAssignExprE ')' sigAttrListE */ #line 1041 "VParseBison.y" { VARDTYPE(SPACED((yyvsp[-7].str),(yyvsp[-6].str))); VARDONE((yyvsp[-4].fl), (yyvsp[-4].str), "", ""); PINNUMINC(); } #line 21707 "VParseBison.c" break; case 82: /* portE: portDirNetE "interconnect" signingE variable_dimensionListE '.' portSig '(' portAssignExprE ')' sigAttrListE */ #line 1043 "VParseBison.y" { VARDTYPE(SPACED(SPACED((yyvsp[-8].str),(yyvsp[-7].str)),(yyvsp[-6].str))); VARDONE((yyvsp[-4].fl), (yyvsp[-4].str), "", ""); PINNUMINC(); } #line 21713 "VParseBison.c" break; case 83: /* portE: portDirNetE '.' portSig '(' portAssignExprE ')' sigAttrListE */ #line 1045 "VParseBison.y" { /*VARDTYPE-same*/ VARDONE((yyvsp[-4].fl), (yyvsp[-4].str), "", ""); PINNUMINC(); } #line 21719 "VParseBison.c" break; case 84: /* portE: portDirNetE var_data_type portSig variable_dimensionListE sigAttrListE */ #line 1048 "VParseBison.y" { VARDTYPE((yyvsp[-3].str)); VARDONE((yyvsp[-2].fl), (yyvsp[-2].str), (yyvsp[-1].str), ""); PINNUMINC(); } #line 21725 "VParseBison.c" break; case 85: /* portE: portDirNetE signing portSig variable_dimensionListE sigAttrListE */ #line 1050 "VParseBison.y" { VARDTYPE((yyvsp[-3].str)); VARDONE((yyvsp[-2].fl), (yyvsp[-2].str), (yyvsp[-1].str), ""); PINNUMINC(); } #line 21731 "VParseBison.c" break; case 86: /* portE: portDirNetE signingE variable_dimensionList portSig variable_dimensionListE sigAttrListE */ #line 1052 "VParseBison.y" { VARDTYPE(SPACED((yyvsp[-4].str),(yyvsp[-3].str))); VARDONE((yyvsp[-2].fl), (yyvsp[-2].str), (yyvsp[-1].str), ""); PINNUMINC(); } #line 21737 "VParseBison.c" break; case 87: /* portE: portDirNetE "interconnect" signingE variable_dimensionList portSig variable_dimensionListE sigAttrListE */ #line 1054 "VParseBison.y" { VARDTYPE(SPACED(SPACED((yyvsp[-5].str),(yyvsp[-4].str)),(yyvsp[-3].str))); VARDONE((yyvsp[-2].fl), (yyvsp[-2].str), (yyvsp[-1].str), ""); PINNUMINC(); } #line 21743 "VParseBison.c" break; case 88: /* portE: portDirNetE portSig variable_dimensionListE sigAttrListE */ #line 1056 "VParseBison.y" { /*VARDTYPE-same*/ VARDONE((yyvsp[-2].fl), (yyvsp[-2].str), (yyvsp[-1].str), ""); PINNUMINC(); } #line 21749 "VParseBison.c" break; case 89: /* portE: portDirNetE var_data_type portSig variable_dimensionListE sigAttrListE '=' constExpr */ #line 1059 "VParseBison.y" { VARDTYPE((yyvsp[-5].str)); VARDONE((yyvsp[-4].fl), (yyvsp[-4].str), (yyvsp[-3].str), (yyvsp[0].str)); PINNUMINC(); } #line 21755 "VParseBison.c" break; case 90: /* portE: portDirNetE signing portSig variable_dimensionListE sigAttrListE '=' constExpr */ #line 1061 "VParseBison.y" { VARDTYPE((yyvsp[-5].str)); VARDONE((yyvsp[-4].fl), (yyvsp[-4].str), (yyvsp[-3].str), (yyvsp[0].str)); PINNUMINC(); } #line 21761 "VParseBison.c" break; case 91: /* portE: portDirNetE signingE variable_dimensionList portSig variable_dimensionListE sigAttrListE '=' constExpr */ #line 1063 "VParseBison.y" { VARDTYPE(SPACED((yyvsp[-6].str),(yyvsp[-5].str))); VARDONE((yyvsp[-4].fl), (yyvsp[-4].str), (yyvsp[-3].str), (yyvsp[0].str)); PINNUMINC(); } #line 21767 "VParseBison.c" break; case 92: /* portE: portDirNetE "interconnect" signingE variable_dimensionList portSig variable_dimensionListE sigAttrListE '=' constExpr */ #line 1065 "VParseBison.y" { VARDTYPE(SPACED(SPACED((yyvsp[-7].str),(yyvsp[-6].str)),(yyvsp[-5].str))); VARDONE((yyvsp[-4].fl), (yyvsp[-4].str), (yyvsp[-3].str), (yyvsp[0].str)); PINNUMINC(); } #line 21773 "VParseBison.c" break; case 93: /* portE: portDirNetE portSig variable_dimensionListE sigAttrListE '=' constExpr */ #line 1067 "VParseBison.y" { /*VARDTYPE-same*/ VARDONE((yyvsp[-4].fl), (yyvsp[-4].str), (yyvsp[-3].str), (yyvsp[0].str)); PINNUMINC(); } #line 21779 "VParseBison.c" break; case 94: /* portE: '{' list_of_portsE '}' */ #line 1069 "VParseBison.y" { } #line 21785 "VParseBison.c" break; case 95: /* portDirNetE: %empty */ #line 1073 "VParseBison.y" { } #line 21791 "VParseBison.c" break; case 96: /* portDirNetE: port_direction */ #line 1076 "VParseBison.y" { VARDTYPE(""/*default_nettype*/); } #line 21797 "VParseBison.c" break; case 97: /* portDirNetE: port_direction net_type */ #line 1077 "VParseBison.y" { VARDTYPE(""/*default_nettype*/); } #line 21803 "VParseBison.c" break; case 98: /* portDirNetE: net_type */ #line 1078 "VParseBison.y" { } #line 21809 "VParseBison.c" break; case 99: /* port_declNetE: %empty */ #line 1082 "VParseBison.y" { } #line 21815 "VParseBison.c" break; case 100: /* port_declNetE: net_type */ #line 1083 "VParseBison.y" { } #line 21821 "VParseBison.c" break; case 101: /* portAssignExprE: %empty */ #line 1087 "VParseBison.y" { } #line 21827 "VParseBison.c" break; case 102: /* portAssignExprE: expr */ #line 1088 "VParseBison.y" { } #line 21833 "VParseBison.c" break; case 103: /* portSig: id */ #line 1092 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 21839 "VParseBison.c" break; case 104: /* portSig: idSVKwd */ #line 1093 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 21845 "VParseBison.c" break; case 105: /* interface_declaration: intFront importsAndParametersE portsStarE ';' interface_itemListE "endinterface" endLabelE */ #line 1103 "VParseBison.y" { PARSEP->endinterfaceCb((yyvsp[-1].fl), (yyvsp[-1].str)); PARSEP->symPopScope(VAstType::INTERFACE); } #line 21852 "VParseBison.c" break; case 106: /* interface_declaration: "extern" intFront importsAndParametersE portsStarE ';' */ #line 1105 "VParseBison.y" { } #line 21858 "VParseBison.c" break; case 107: /* intFront: "interface" lifetimeE idAny */ #line 1110 "VParseBison.y" { PARSEP->symPushNew(VAstType::INTERFACE,(yyvsp[0].str)); PARSEP->interfaceCb((yyvsp[-2].fl),(yyvsp[-2].str),(yyvsp[0].str)); } #line 21865 "VParseBison.c" break; case 108: /* interface_itemListE: %empty */ #line 1115 "VParseBison.y" { } #line 21871 "VParseBison.c" break; case 109: /* interface_itemListE: interface_itemList */ #line 1116 "VParseBison.y" { } #line 21877 "VParseBison.c" break; case 110: /* interface_itemList: interface_item */ #line 1120 "VParseBison.y" { } #line 21883 "VParseBison.c" break; case 111: /* interface_itemList: interface_itemList interface_item */ #line 1121 "VParseBison.y" { } #line 21889 "VParseBison.c" break; case 112: /* interface_item: port_declaration ';' */ #line 1125 "VParseBison.y" { } #line 21895 "VParseBison.c" break; case 113: /* interface_item: generate_region */ #line 1127 "VParseBison.y" { } #line 21901 "VParseBison.c" break; case 114: /* interface_item: interface_or_generate_item */ #line 1128 "VParseBison.y" { } #line 21907 "VParseBison.c" break; case 115: /* interface_item: program_declaration */ #line 1129 "VParseBison.y" { } #line 21913 "VParseBison.c" break; case 116: /* interface_item: interface_declaration */ #line 1132 "VParseBison.y" { } #line 21919 "VParseBison.c" break; case 117: /* interface_item: timeunits_declaration */ #line 1133 "VParseBison.y" { } #line 21925 "VParseBison.c" break; case 118: /* interface_item: module_common_item */ #line 1135 "VParseBison.y" { } #line 21931 "VParseBison.c" break; case 119: /* interface_or_generate_item: modport_declaration */ #line 1143 "VParseBison.y" { } #line 21937 "VParseBison.c" break; case 120: /* interface_or_generate_item: extern_tf_declaration */ #line 1144 "VParseBison.y" { } #line 21943 "VParseBison.c" break; case 121: /* anonymous_program: "program" ';' anonymous_program_itemListE "endprogram" */ #line 1152 "VParseBison.y" { } #line 21949 "VParseBison.c" break; case 122: /* anonymous_program_itemListE: %empty */ #line 1156 "VParseBison.y" { } #line 21955 "VParseBison.c" break; case 123: /* anonymous_program_itemListE: anonymous_program_itemList */ #line 1157 "VParseBison.y" { } #line 21961 "VParseBison.c" break; case 124: /* anonymous_program_itemList: anonymous_program_item */ #line 1161 "VParseBison.y" { } #line 21967 "VParseBison.c" break; case 125: /* anonymous_program_itemList: anonymous_program_itemList anonymous_program_item */ #line 1162 "VParseBison.y" { } #line 21973 "VParseBison.c" break; case 126: /* anonymous_program_item: task_declaration */ #line 1166 "VParseBison.y" { } #line 21979 "VParseBison.c" break; case 127: /* anonymous_program_item: function_declaration */ #line 1167 "VParseBison.y" { } #line 21985 "VParseBison.c" break; case 128: /* anonymous_program_item: class_declaration */ #line 1168 "VParseBison.y" { } #line 21991 "VParseBison.c" break; case 129: /* anonymous_program_item: covergroup_declaration */ #line 1169 "VParseBison.y" { } #line 21997 "VParseBison.c" break; case 130: /* anonymous_program_item: ';' */ #line 1171 "VParseBison.y" { } #line 22003 "VParseBison.c" break; case 131: /* program_declaration: pgmFront importsAndParametersE portsStarE ';' program_itemListE "endprogram" endLabelE */ #line 1178 "VParseBison.y" { PARSEP->endprogramCb((yyvsp[-1].fl),(yyvsp[-1].str)); PARSEP->symPopScope(VAstType::PROGRAM); } #line 22010 "VParseBison.c" break; case 132: /* program_declaration: "extern" pgmFront importsAndParametersE portsStarE ';' */ #line 1181 "VParseBison.y" { PARSEP->symPopScope(VAstType::PROGRAM); } #line 22016 "VParseBison.c" break; case 133: /* pgmFront: "program" lifetimeE idAny */ #line 1186 "VParseBison.y" { PARSEP->symPushNew(VAstType::PROGRAM,(yyvsp[0].str)); PARSEP->programCb((yyvsp[-2].fl),(yyvsp[-2].str), (yyvsp[0].str)); } #line 22024 "VParseBison.c" break; case 134: /* program_itemListE: %empty */ #line 1192 "VParseBison.y" { } #line 22030 "VParseBison.c" break; case 135: /* program_itemListE: program_itemList */ #line 1193 "VParseBison.y" { } #line 22036 "VParseBison.c" break; case 136: /* program_itemList: program_item */ #line 1197 "VParseBison.y" { } #line 22042 "VParseBison.c" break; case 137: /* program_itemList: program_itemList program_item */ #line 1198 "VParseBison.y" { } #line 22048 "VParseBison.c" break; case 138: /* program_item: port_declaration ';' */ #line 1202 "VParseBison.y" { } #line 22054 "VParseBison.c" break; case 139: /* program_item: non_port_program_item */ #line 1203 "VParseBison.y" { } #line 22060 "VParseBison.c" break; case 140: /* non_port_program_item: continuous_assign */ #line 1207 "VParseBison.y" { } #line 22066 "VParseBison.c" break; case 141: /* non_port_program_item: module_or_generate_item_declaration */ #line 1208 "VParseBison.y" { } #line 22072 "VParseBison.c" break; case 142: /* non_port_program_item: initial_construct */ #line 1209 "VParseBison.y" { } #line 22078 "VParseBison.c" break; case 143: /* non_port_program_item: final_construct */ #line 1210 "VParseBison.y" { } #line 22084 "VParseBison.c" break; case 144: /* non_port_program_item: concurrent_assertion_item */ #line 1211 "VParseBison.y" { } #line 22090 "VParseBison.c" break; case 145: /* non_port_program_item: timeunits_declaration */ #line 1212 "VParseBison.y" { } #line 22096 "VParseBison.c" break; case 146: /* non_port_program_item: program_generate_item */ #line 1213 "VParseBison.y" { } #line 22102 "VParseBison.c" break; case 147: /* program_generate_item: loop_generate_construct */ #line 1217 "VParseBison.y" { } #line 22108 "VParseBison.c" break; case 148: /* program_generate_item: conditional_generate_construct */ #line 1218 "VParseBison.y" { } #line 22114 "VParseBison.c" break; case 149: /* program_generate_item: generate_region */ #line 1219 "VParseBison.y" { } #line 22120 "VParseBison.c" break; case 150: /* program_generate_item: elaboration_system_task */ #line 1220 "VParseBison.y" { } #line 22126 "VParseBison.c" break; case 151: /* extern_tf_declaration: "extern" task_prototype ';' */ #line 1224 "VParseBison.y" { } #line 22132 "VParseBison.c" break; case 152: /* extern_tf_declaration: "extern" function_prototype ';' */ #line 1225 "VParseBison.y" { } #line 22138 "VParseBison.c" break; case 153: /* extern_tf_declaration: "extern" "forkjoin" task_prototype ';' */ #line 1226 "VParseBison.y" { } #line 22144 "VParseBison.c" break; case 154: /* modport_declaration: "modport" modport_itemList ';' */ #line 1230 "VParseBison.y" { } #line 22150 "VParseBison.c" break; case 155: /* modport_itemList: modport_item */ #line 1234 "VParseBison.y" { } #line 22156 "VParseBison.c" break; case 156: /* modport_itemList: modport_itemList ',' modport_item */ #line 1235 "VParseBison.y" { } #line 22162 "VParseBison.c" break; case 157: /* $@3: %empty */ #line 1239 "VParseBison.y" {VARRESET_LIST("");} #line 22168 "VParseBison.c" break; case 158: /* modport_item: modport_idFront '(' $@3 modportPortsDeclList ')' */ #line 1240 "VParseBison.y" { VARRESET_NONLIST(""); PARSEP->endmodportCb((yyvsp[-4].fl), "endmodport"); PARSEP->symPopScope(VAstType::MODPORT); } #line 22176 "VParseBison.c" break; case 159: /* modport_idFront: id */ #line 1247 "VParseBison.y" { PARSEP->symPushNew(VAstType::MODPORT,(yyvsp[0].str)); PARSEP->modportCb((yyvsp[0].fl),"modport",(yyvsp[0].str)); } #line 22183 "VParseBison.c" break; case 160: /* modportPortsDeclList: modportPortsDecl */ #line 1252 "VParseBison.y" { } #line 22189 "VParseBison.c" break; case 161: /* modportPortsDeclList: modportPortsDeclList ',' modportPortsDecl */ #line 1253 "VParseBison.y" { } #line 22195 "VParseBison.c" break; case 162: /* modportPortsDecl: port_direction modportSimplePort */ #line 1262 "VParseBison.y" { } #line 22201 "VParseBison.c" break; case 163: /* modportPortsDecl: "clocking" idAny */ #line 1264 "VParseBison.y" { } #line 22207 "VParseBison.c" break; case 164: /* modportPortsDecl: "import" modport_tf_port */ #line 1265 "VParseBison.y" { } #line 22213 "VParseBison.c" break; case 165: /* modportPortsDecl: "export" modport_tf_port */ #line 1266 "VParseBison.y" { } #line 22219 "VParseBison.c" break; case 166: /* modportPortsDecl: modportSimplePort */ #line 1269 "VParseBison.y" { } #line 22225 "VParseBison.c" break; case 167: /* modportSimplePort: id */ #line 1274 "VParseBison.y" { VARDONE((yyvsp[0].fl),(yyvsp[0].str),"",(yyvsp[0].str)); PINNUMINC(); } #line 22231 "VParseBison.c" break; case 168: /* modportSimplePort: '.' idAny '(' ')' */ #line 1275 "VParseBison.y" { VARDONE((yyvsp[-3].fl),(yyvsp[-2].str),"",""); PINNUMINC(); } #line 22237 "VParseBison.c" break; case 169: /* modportSimplePort: '.' idAny '(' expr ')' */ #line 1276 "VParseBison.y" { VARDONE((yyvsp[-4].fl),(yyvsp[-3].str),"",(yyvsp[-1].str)); PINNUMINC(); } #line 22243 "VParseBison.c" break; case 170: /* modport_tf_port: id */ #line 1280 "VParseBison.y" { } #line 22249 "VParseBison.c" break; case 171: /* modport_tf_port: method_prototype */ #line 1281 "VParseBison.y" { } #line 22255 "VParseBison.c" break; case 172: /* genvar_declaration: "genvar" list_of_genvar_identifiers ';' */ #line 1288 "VParseBison.y" { } #line 22261 "VParseBison.c" break; case 173: /* list_of_genvar_identifiers: genvar_identifierDecl */ #line 1292 "VParseBison.y" { } #line 22267 "VParseBison.c" break; case 174: /* list_of_genvar_identifiers: list_of_genvar_identifiers ',' genvar_identifierDecl */ #line 1293 "VParseBison.y" { } #line 22273 "VParseBison.c" break; case 175: /* genvar_identifierDecl: id sigAttrListE */ #line 1297 "VParseBison.y" { VARRESET_NONLIST("genvar"); VARDONE((yyvsp[-1].fl), (yyvsp[-1].str), "", ""); } #line 22279 "VParseBison.c" break; case 176: /* local_parameter_declaration: local_parameter_declarationFront list_of_param_assignments */ #line 1302 "VParseBison.y" { } #line 22285 "VParseBison.c" break; case 177: /* parameter_declaration: parameter_declarationFront list_of_param_assignments */ #line 1310 "VParseBison.y" { } #line 22291 "VParseBison.c" break; case 178: /* local_parameter_declarationFront: varLParamReset implicit_typeE */ #line 1314 "VParseBison.y" { VARRESET(); VARDECL("localparam"); VARDTYPE((yyvsp[0].str)); } #line 22297 "VParseBison.c" break; case 179: /* local_parameter_declarationFront: varLParamReset data_type */ #line 1315 "VParseBison.y" { VARRESET(); VARDECL("localparam"); VARDTYPE((yyvsp[0].str)); } #line 22303 "VParseBison.c" break; case 180: /* local_parameter_declarationFront: varLParamReset "type" */ #line 1316 "VParseBison.y" { VARRESET(); VARDECL("localparam"); VARDTYPE((yyvsp[0].str)); } #line 22309 "VParseBison.c" break; case 181: /* parameter_declarationFront: varGParamReset implicit_typeE */ #line 1320 "VParseBison.y" { VARRESET(); VARDECL("parameter"); VARDTYPE((yyvsp[0].str)); } #line 22315 "VParseBison.c" break; case 182: /* parameter_declarationFront: varGParamReset data_type */ #line 1321 "VParseBison.y" { VARRESET(); VARDECL("parameter"); VARDTYPE((yyvsp[0].str)); } #line 22321 "VParseBison.c" break; case 183: /* parameter_declarationFront: varGParamReset "type" */ #line 1322 "VParseBison.y" { VARRESET(); VARDECL("parameter"); VARDTYPE((yyvsp[0].str)); } #line 22327 "VParseBison.c" break; case 184: /* parameter_port_declarationFront: parameter_declarationFront */ #line 1327 "VParseBison.y" { } #line 22333 "VParseBison.c" break; case 185: /* parameter_port_declarationFront: local_parameter_declarationFront */ #line 1328 "VParseBison.y" { /*NEED_S09(CURLINE(),"port localparams");*/ } #line 22339 "VParseBison.c" break; case 186: /* parameter_port_declarationFront: data_type */ #line 1330 "VParseBison.y" { VARDTYPE((yyvsp[0].str)); } #line 22345 "VParseBison.c" break; case 187: /* parameter_port_declarationFront: "type" */ #line 1331 "VParseBison.y" { VARDTYPE((yyvsp[0].str)); } #line 22351 "VParseBison.c" break; case 188: /* net_declaration: net_declarationFront netSigList ';' */ #line 1335 "VParseBison.y" { } #line 22357 "VParseBison.c" break; case 189: /* net_declarationFront: net_declRESET net_type strengthSpecE net_scalaredE net_dataType */ #line 1339 "VParseBison.y" { VARDTYPE(SPACED((yyvsp[-1].str),(yyvsp[0].str))); } #line 22363 "VParseBison.c" break; case 190: /* net_declarationFront: net_declRESET "interconnect" signingE rangeListE */ #line 1340 "VParseBison.y" { VARNET((yyvsp[-2].str)); VARDTYPE(SPACED((yyvsp[-1].str),(yyvsp[0].str))); } #line 22369 "VParseBison.c" break; case 191: /* net_declRESET: %empty */ #line 1344 "VParseBison.y" { VARRESET_NONLIST("net"); } #line 22375 "VParseBison.c" break; case 192: /* net_scalaredE: %empty */ #line 1348 "VParseBison.y" { (yyval.str)=""; } #line 22381 "VParseBison.c" break; case 193: /* net_scalaredE: "scalared" */ #line 1349 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 22387 "VParseBison.c" break; case 194: /* net_scalaredE: "vectored" */ #line 1350 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 22393 "VParseBison.c" break; case 195: /* net_dataType: var_data_type */ #line 1357 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 22399 "VParseBison.c" break; case 196: /* net_dataType: signingE rangeList delayE */ #line 1358 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str)=SPACED((yyvsp[-2].str),(yyvsp[-1].str)); } #line 22405 "VParseBison.c" break; case 197: /* net_dataType: signing delayE */ #line 1359 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str)=(yyvsp[-1].str); } #line 22411 "VParseBison.c" break; case 198: /* net_dataType: delayE */ #line 1360 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=""; } #line 22417 "VParseBison.c" break; case 199: /* net_type: "supply0" */ #line 1364 "VParseBison.y" { VARNET((yyvsp[0].str)); } #line 22423 "VParseBison.c" break; case 200: /* net_type: "supply1" */ #line 1365 "VParseBison.y" { VARNET((yyvsp[0].str)); } #line 22429 "VParseBison.c" break; case 201: /* net_type: "tri" */ #line 1366 "VParseBison.y" { VARNET((yyvsp[0].str)); } #line 22435 "VParseBison.c" break; case 202: /* net_type: "tri0" */ #line 1367 "VParseBison.y" { VARNET((yyvsp[0].str)); } #line 22441 "VParseBison.c" break; case 203: /* net_type: "tri1" */ #line 1368 "VParseBison.y" { VARNET((yyvsp[0].str)); } #line 22447 "VParseBison.c" break; case 204: /* net_type: "triand" */ #line 1369 "VParseBison.y" { VARNET((yyvsp[0].str)); } #line 22453 "VParseBison.c" break; case 205: /* net_type: "trior" */ #line 1370 "VParseBison.y" { VARNET((yyvsp[0].str)); } #line 22459 "VParseBison.c" break; case 206: /* net_type: "trireg" */ #line 1371 "VParseBison.y" { VARNET((yyvsp[0].str)); } #line 22465 "VParseBison.c" break; case 207: /* net_type: "wand" */ #line 1372 "VParseBison.y" { VARNET((yyvsp[0].str)); } #line 22471 "VParseBison.c" break; case 208: /* net_type: "wire" */ #line 1373 "VParseBison.y" { VARNET((yyvsp[0].str)); } #line 22477 "VParseBison.c" break; case 209: /* net_type: "wor" */ #line 1374 "VParseBison.y" { VARNET((yyvsp[0].str)); } #line 22483 "VParseBison.c" break; case 210: /* varGParamReset: "parameter" */ #line 1378 "VParseBison.y" { VARRESET_NONLIST((yyvsp[0].str)); } #line 22489 "VParseBison.c" break; case 211: /* varLParamReset: "localparam" */ #line 1382 "VParseBison.y" { VARRESET_NONLIST((yyvsp[0].str)); } #line 22495 "VParseBison.c" break; case 212: /* port_direction: "input" */ #line 1387 "VParseBison.y" { VARIO((yyvsp[0].str)); } #line 22501 "VParseBison.c" break; case 213: /* port_direction: "output" */ #line 1388 "VParseBison.y" { VARIO((yyvsp[0].str)); } #line 22507 "VParseBison.c" break; case 214: /* port_direction: "inout" */ #line 1389 "VParseBison.y" { VARIO((yyvsp[0].str)); } #line 22513 "VParseBison.c" break; case 215: /* port_direction: "ref" */ #line 1390 "VParseBison.y" { VARIO((yyvsp[0].str)); } #line 22519 "VParseBison.c" break; case 216: /* port_direction: "const-then-ref" "ref" */ #line 1391 "VParseBison.y" { VARIO((yyvsp[-1].str)); } #line 22525 "VParseBison.c" break; case 217: /* port_directionReset: "input" */ #line 1396 "VParseBison.y" { VARRESET_NONLIST(""); VARIO((yyvsp[0].str)); } #line 22531 "VParseBison.c" break; case 218: /* port_directionReset: "output" */ #line 1397 "VParseBison.y" { VARRESET_NONLIST(""); VARIO((yyvsp[0].str)); } #line 22537 "VParseBison.c" break; case 219: /* port_directionReset: "inout" */ #line 1398 "VParseBison.y" { VARRESET_NONLIST(""); VARIO((yyvsp[0].str)); } #line 22543 "VParseBison.c" break; case 220: /* port_directionReset: "ref" */ #line 1399 "VParseBison.y" { VARRESET_NONLIST(""); VARIO((yyvsp[0].str)); } #line 22549 "VParseBison.c" break; case 221: /* port_directionReset: "const-then-ref" "ref" */ #line 1400 "VParseBison.y" { VARRESET_NONLIST(""); VARIO((yyvsp[-1].str)); } #line 22555 "VParseBison.c" break; case 222: /* $@4: %empty */ #line 1411 "VParseBison.y" { VARDTYPE((yyvsp[0].str)); } #line 22561 "VParseBison.c" break; case 223: /* port_declaration: port_directionReset port_declNetE var_data_type $@4 list_of_variable_decl_assignments */ #line 1411 "VParseBison.y" { } #line 22567 "VParseBison.c" break; case 224: /* $@5: %empty */ #line 1412 "VParseBison.y" { VARDTYPE(SPACED((yyvsp[-1].str),(yyvsp[0].str))); } #line 22573 "VParseBison.c" break; case 225: /* port_declaration: port_directionReset port_declNetE signingE rangeList $@5 list_of_variable_decl_assignments */ #line 1412 "VParseBison.y" { } #line 22579 "VParseBison.c" break; case 226: /* $@6: %empty */ #line 1413 "VParseBison.y" { VARDTYPE((yyvsp[0].str)); } #line 22585 "VParseBison.c" break; case 227: /* port_declaration: port_directionReset port_declNetE signing $@6 list_of_variable_decl_assignments */ #line 1413 "VParseBison.y" { } #line 22591 "VParseBison.c" break; case 228: /* $@7: %empty */ #line 1414 "VParseBison.y" { VARDTYPE("");/*default_nettype*/} #line 22597 "VParseBison.c" break; case 229: /* port_declaration: port_directionReset port_declNetE $@7 list_of_variable_decl_assignments */ #line 1414 "VParseBison.y" { } #line 22603 "VParseBison.c" break; case 230: /* $@8: %empty */ #line 1424 "VParseBison.y" { VARDTYPE((yyvsp[0].str)); } #line 22609 "VParseBison.c" break; case 231: /* tf_port_declaration: port_directionReset var_data_type $@8 list_of_tf_variable_identifiers ';' */ #line 1424 "VParseBison.y" { } #line 22615 "VParseBison.c" break; case 232: /* $@9: %empty */ #line 1425 "VParseBison.y" { VARDTYPE((yyvsp[0].str)); } #line 22621 "VParseBison.c" break; case 233: /* tf_port_declaration: port_directionReset implicit_typeE $@9 list_of_tf_variable_identifiers ';' */ #line 1425 "VParseBison.y" { } #line 22627 "VParseBison.c" break; case 234: /* integer_atom_type: "byte" */ #line 1429 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 22633 "VParseBison.c" break; case 235: /* integer_atom_type: "shortint" */ #line 1430 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 22639 "VParseBison.c" break; case 236: /* integer_atom_type: "int" */ #line 1431 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 22645 "VParseBison.c" break; case 237: /* integer_atom_type: "longint" */ #line 1432 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 22651 "VParseBison.c" break; case 238: /* integer_atom_type: "integer" */ #line 1433 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 22657 "VParseBison.c" break; case 239: /* integer_atom_type: "time" */ #line 1434 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 22663 "VParseBison.c" break; case 240: /* integer_vector_type: "bit" */ #line 1438 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 22669 "VParseBison.c" break; case 241: /* integer_vector_type: "logic" */ #line 1439 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 22675 "VParseBison.c" break; case 242: /* integer_vector_type: "reg" */ #line 1440 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 22681 "VParseBison.c" break; case 243: /* non_integer_type: "shortreal" */ #line 1444 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 22687 "VParseBison.c" break; case 244: /* non_integer_type: "real" */ #line 1445 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 22693 "VParseBison.c" break; case 245: /* non_integer_type: "realtime" */ #line 1446 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 22699 "VParseBison.c" break; case 246: /* signingE: %empty */ #line 1450 "VParseBison.y" { (yyval.str)=""; } #line 22705 "VParseBison.c" break; case 247: /* signingE: signing */ #line 1451 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 22711 "VParseBison.c" break; case 248: /* signing: "signed" */ #line 1455 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 22717 "VParseBison.c" break; case 249: /* signing: "unsigned" */ #line 1456 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 22723 "VParseBison.c" break; case 250: /* casting_type: simple_type */ #line 1463 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 22729 "VParseBison.c" break; case 251: /* casting_type: "signed" */ #line 1468 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 22735 "VParseBison.c" break; case 252: /* casting_type: "unsigned" */ #line 1469 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 22741 "VParseBison.c" break; case 253: /* casting_type: "string" */ #line 1470 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 22747 "VParseBison.c" break; case 254: /* casting_type: "const" */ #line 1471 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 22753 "VParseBison.c" break; case 255: /* simple_type: integer_atom_type */ #line 1476 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 22759 "VParseBison.c" break; case 256: /* simple_type: integer_vector_type */ #line 1477 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 22765 "VParseBison.c" break; case 257: /* simple_type: non_integer_type */ #line 1478 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 22771 "VParseBison.c" break; case 258: /* simple_type: package_scopeIdFollowsE "TYPE-IDENTIFIER" */ #line 1481 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str)=(yyvsp[-1].str)+(yyvsp[0].str); } #line 22777 "VParseBison.c" break; case 259: /* data_typeVar: data_type */ #line 1487 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 22783 "VParseBison.c" break; case 260: /* data_typeVar: "virtual-then-interface" "interface" id parameter_value_assignmentE '.' id */ #line 1491 "VParseBison.y" { (yyval.fl)=(yyvsp[-5].fl); (yyval.str)=SPACED((yyvsp[-5].str),SPACED((yyvsp[-4].str),(yyvsp[-3].str))); } #line 22789 "VParseBison.c" break; case 261: /* data_typeVar: "virtual-then-identifier" id parameter_value_assignmentE '.' id */ #line 1493 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str)=SPACED((yyvsp[-4].str),(yyvsp[-3].str)); } #line 22795 "VParseBison.c" break; case 262: /* data_type: integer_vector_type signingE rangeListE */ #line 1497 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str)=SPACED((yyvsp[-2].str),SPACED((yyvsp[-1].str),(yyvsp[0].str))); } #line 22801 "VParseBison.c" break; case 263: /* data_type: integer_atom_type signingE */ #line 1498 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str)=SPACED((yyvsp[-1].str),(yyvsp[0].str)); } #line 22807 "VParseBison.c" break; case 264: /* data_type: non_integer_type */ #line 1499 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 22813 "VParseBison.c" break; case 265: /* $@10: %empty */ #line 1500 "VParseBison.y" { PARSEP->symPushNewAnon(VAstType::STRUCT); } #line 22819 "VParseBison.c" break; case 266: /* data_type: "struct" packedSigningE '{' $@10 struct_union_memberList '}' packed_dimensionListE */ #line 1502 "VParseBison.y" { (yyval.fl)=(yyvsp[-6].fl); (yyval.str)=(yyvsp[-6].str); PARSEP->symPopScope(VAstType::STRUCT); } #line 22825 "VParseBison.c" break; case 267: /* $@11: %empty */ #line 1503 "VParseBison.y" { PARSEP->symPushNewAnon(VAstType::UNION); } #line 22831 "VParseBison.c" break; case 268: /* data_type: "union" taggedE packedSigningE '{' $@11 struct_union_memberList '}' packed_dimensionListE */ #line 1505 "VParseBison.y" { (yyval.fl)=(yyvsp[-7].fl); (yyval.str)=(yyvsp[-7].str); PARSEP->symPopScope(VAstType::UNION); } #line 22837 "VParseBison.c" break; case 269: /* data_type: enumDecl */ #line 1506 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 22843 "VParseBison.c" break; case 270: /* data_type: "string" */ #line 1507 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 22849 "VParseBison.c" break; case 271: /* data_type: "chandle" */ #line 1508 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 22855 "VParseBison.c" break; case 272: /* data_type: "virtual-then-interface" "interface" id parameter_value_assignmentE */ #line 1515 "VParseBison.y" { (yyval.fl)=(yyvsp[-3].fl); (yyval.str)=SPACED((yyvsp[-3].str),SPACED((yyvsp[-2].str),(yyvsp[-1].str))); } #line 22861 "VParseBison.c" break; case 273: /* data_type: "virtual-then-identifier" id parameter_value_assignmentE */ #line 1517 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str)=SPACED((yyvsp[-2].str),(yyvsp[-1].str)); } #line 22867 "VParseBison.c" break; case 274: /* data_type: "event" */ #line 1523 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 22873 "VParseBison.c" break; case 275: /* data_type: type_reference */ #line 1524 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 22879 "VParseBison.c" break; case 276: /* data_type: package_scopeIdFollowsE class_typeOneList packed_dimensionListE */ #line 1533 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str)=(yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 22885 "VParseBison.c" break; case 277: /* data_type_or_void: data_type */ #line 1539 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 22891 "VParseBison.c" break; case 278: /* data_type_or_void: "void" */ #line 1540 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 22897 "VParseBison.c" break; case 279: /* var_data_type: data_type */ #line 1544 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 22903 "VParseBison.c" break; case 280: /* var_data_type: "var" data_type */ #line 1545 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str)=(yyvsp[-1].str); } #line 22909 "VParseBison.c" break; case 281: /* var_data_type: "var" implicit_typeE */ #line 1546 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str)=(yyvsp[-1].str); } #line 22915 "VParseBison.c" break; case 282: /* type_reference: "type" '(' exprOrDataType ')' */ #line 1550 "VParseBison.y" { (yyval.fl)=(yyvsp[-3].fl); (yyval.str)="type("+(yyvsp[-1].str)+")"; } #line 22921 "VParseBison.c" break; case 283: /* struct_union_memberList: struct_union_member */ #line 1554 "VParseBison.y" { } #line 22927 "VParseBison.c" break; case 284: /* struct_union_memberList: struct_union_memberList struct_union_member */ #line 1555 "VParseBison.y" { } #line 22933 "VParseBison.c" break; case 285: /* $@12: %empty */ #line 1560 "VParseBison.y" { VARS_PUSH(); // Structs can be recursive, or under a parameter typs VARRESET_NONLIST("member"); VARDTYPE(SPACED((yyvsp[-1].str),(yyvsp[0].str))); } #line 22940 "VParseBison.c" break; case 286: /* struct_union_member: random_qualifierE data_type_or_void $@12 list_of_variable_decl_assignments ';' */ #line 1563 "VParseBison.y" { VARS_POP(); } #line 22946 "VParseBison.c" break; case 287: /* list_of_variable_decl_assignments: variable_decl_assignment */ #line 1567 "VParseBison.y" { } #line 22952 "VParseBison.c" break; case 288: /* list_of_variable_decl_assignments: list_of_variable_decl_assignments ',' variable_decl_assignment */ #line 1568 "VParseBison.y" { } #line 22958 "VParseBison.c" break; case 289: /* variable_decl_assignment: id variable_dimensionListE sigAttrListE */ #line 1573 "VParseBison.y" { VARDONE((yyvsp[-2].fl), (yyvsp[-2].str), (yyvsp[-1].str), ""); } #line 22964 "VParseBison.c" break; case 290: /* variable_decl_assignment: id variable_dimensionListE sigAttrListE '=' variable_declExpr */ #line 1575 "VParseBison.y" { VARDONE((yyvsp[-4].fl), (yyvsp[-4].str), (yyvsp[-3].str), (yyvsp[0].str)); } #line 22970 "VParseBison.c" break; case 291: /* variable_decl_assignment: idSVKwd */ #line 1576 "VParseBison.y" { } #line 22976 "VParseBison.c" break; case 292: /* variable_decl_assignment: '=' class_new */ #line 1586 "VParseBison.y" { } #line 22982 "VParseBison.c" break; case 293: /* list_of_tf_variable_identifiers: tf_variable_identifier */ #line 1590 "VParseBison.y" { } #line 22988 "VParseBison.c" break; case 294: /* list_of_tf_variable_identifiers: list_of_tf_variable_identifiers ',' tf_variable_identifier */ #line 1591 "VParseBison.y" { } #line 22994 "VParseBison.c" break; case 295: /* tf_variable_identifier: id variable_dimensionListE sigAttrListE */ #line 1596 "VParseBison.y" { VARDONE((yyvsp[-2].fl), (yyvsp[-2].str), (yyvsp[-1].str), ""); } #line 23000 "VParseBison.c" break; case 296: /* tf_variable_identifier: id variable_dimensionListE sigAttrListE '=' expr */ #line 1598 "VParseBison.y" { VARDONE((yyvsp[-4].fl), (yyvsp[-4].str), (yyvsp[-3].str), (yyvsp[0].str)); } #line 23006 "VParseBison.c" break; case 297: /* variable_declExpr: expr */ #line 1602 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 23012 "VParseBison.c" break; case 298: /* variable_declExpr: dynamic_array_new */ #line 1603 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 23018 "VParseBison.c" break; case 299: /* variable_declExpr: class_new */ #line 1604 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 23024 "VParseBison.c" break; case 300: /* variable_dimensionListE: %empty */ #line 1608 "VParseBison.y" { (yyval.str)=""; } #line 23030 "VParseBison.c" break; case 301: /* variable_dimensionListE: variable_dimensionList */ #line 1609 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 23036 "VParseBison.c" break; case 302: /* variable_dimensionList: variable_dimension */ #line 1613 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 23042 "VParseBison.c" break; case 303: /* variable_dimensionList: variable_dimensionList variable_dimension */ #line 1614 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str)=(yyvsp[-1].str)+(yyvsp[0].str); } #line 23048 "VParseBison.c" break; case 304: /* variable_dimension: '[' ']' */ #line 1619 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str)=""; } #line 23054 "VParseBison.c" break; case 305: /* variable_dimension: anyrange */ #line 1621 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 23060 "VParseBison.c" break; case 306: /* variable_dimension: '[' exprOrDataType ']' */ #line 1625 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str)="["+(yyvsp[-1].str)+"]"; } #line 23066 "VParseBison.c" break; case 307: /* variable_dimension: "[*" ']' */ #line 1626 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str)="[*]"; } #line 23072 "VParseBison.c" break; case 308: /* variable_dimension: '[' '*' ']' */ #line 1627 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str)="[*]"; } #line 23078 "VParseBison.c" break; case 309: /* random_qualifierE: %empty */ #line 1634 "VParseBison.y" { (yyval.str)=""; } #line 23084 "VParseBison.c" break; case 310: /* random_qualifierE: random_qualifier */ #line 1635 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 23090 "VParseBison.c" break; case 311: /* random_qualifier: "rand" */ #line 1639 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 23096 "VParseBison.c" break; case 312: /* random_qualifier: "randc" */ #line 1640 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 23102 "VParseBison.c" break; case 313: /* taggedE: %empty */ #line 1644 "VParseBison.y" { } #line 23108 "VParseBison.c" break; case 314: /* taggedE: "tagged" */ #line 1645 "VParseBison.y" { } #line 23114 "VParseBison.c" break; case 315: /* packedSigningE: %empty */ #line 1649 "VParseBison.y" { } #line 23120 "VParseBison.c" break; case 316: /* packedSigningE: "packed" signingE */ #line 1650 "VParseBison.y" { } #line 23126 "VParseBison.c" break; case 317: /* enumDecl: "enum" enum_base_typeE '{' enum_nameList '}' rangeListE */ #line 1658 "VParseBison.y" { (yyval.str)=(yyvsp[-4].str); } #line 23132 "VParseBison.c" break; case 318: /* enum_base_typeE: %empty */ #line 1662 "VParseBison.y" { (yyval.str)="enum"; } #line 23138 "VParseBison.c" break; case 319: /* enum_base_typeE: signingE rangeList */ #line 1665 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str)=(yyvsp[-1].str)+(yyvsp[0].str); } #line 23144 "VParseBison.c" break; case 320: /* enum_base_typeE: signing */ #line 1666 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 23150 "VParseBison.c" break; case 321: /* enum_base_typeE: integer_atom_type signingE */ #line 1668 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str)=SPACED((yyvsp[-1].str),(yyvsp[0].str)); } #line 23156 "VParseBison.c" break; case 322: /* enum_base_typeE: integer_vector_type signingE regrangeE */ #line 1669 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str)=SPACED((yyvsp[-2].str),SPACED((yyvsp[-1].str),(yyvsp[0].str))); } #line 23162 "VParseBison.c" break; case 323: /* enum_base_typeE: idAny regrangeE */ #line 1674 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str)=SPACED((yyvsp[-1].str),(yyvsp[0].str)); } #line 23168 "VParseBison.c" break; case 324: /* enum_base_typeE: package_scopeIdFollows idAny rangeListE */ #line 1676 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 23174 "VParseBison.c" break; case 325: /* enum_nameList: enum_name_declaration */ #line 1680 "VParseBison.y" { } #line 23180 "VParseBison.c" break; case 326: /* enum_nameList: enum_nameList ',' enum_name_declaration */ #line 1681 "VParseBison.y" { } #line 23186 "VParseBison.c" break; case 327: /* enum_name_declaration: idAny enumNameRangeE enumNameStartE */ #line 1685 "VParseBison.y" { } #line 23192 "VParseBison.c" break; case 328: /* enumNameRangeE: %empty */ #line 1689 "VParseBison.y" { } #line 23198 "VParseBison.c" break; case 329: /* enumNameRangeE: '[' intnumAsConst ']' */ #line 1690 "VParseBison.y" { } #line 23204 "VParseBison.c" break; case 330: /* enumNameRangeE: '[' intnumAsConst ':' intnumAsConst ']' */ #line 1691 "VParseBison.y" { } #line 23210 "VParseBison.c" break; case 331: /* enumNameStartE: %empty */ #line 1695 "VParseBison.y" { } #line 23216 "VParseBison.c" break; case 332: /* enumNameStartE: '=' constExpr */ #line 1696 "VParseBison.y" { } #line 23222 "VParseBison.c" break; case 333: /* intnumAsConst: "INTEGER NUMBER" */ #line 1700 "VParseBison.y" { } #line 23228 "VParseBison.c" break; case 334: /* data_declaration: data_declarationVar */ #line 1708 "VParseBison.y" { } #line 23234 "VParseBison.c" break; case 335: /* data_declaration: type_declaration */ #line 1709 "VParseBison.y" { } #line 23240 "VParseBison.c" break; case 336: /* data_declaration: package_import_declaration */ #line 1710 "VParseBison.y" { } #line 23246 "VParseBison.c" break; case 337: /* data_declaration: net_type_declaration */ #line 1716 "VParseBison.y" { } #line 23252 "VParseBison.c" break; case 338: /* class_property: memberQualResetListE data_declarationVarClass */ #line 1720 "VParseBison.y" { } #line 23258 "VParseBison.c" break; case 339: /* class_property: memberQualResetListE type_declaration */ #line 1721 "VParseBison.y" { } #line 23264 "VParseBison.c" break; case 340: /* class_property: memberQualResetListE package_import_declaration */ #line 1722 "VParseBison.y" { } #line 23270 "VParseBison.c" break; case 341: /* data_declarationVar: data_declarationVarFront list_of_variable_decl_assignments ';' */ #line 1730 "VParseBison.y" { } #line 23276 "VParseBison.c" break; case 342: /* data_declarationVarClass: data_declarationVarFrontClass list_of_variable_decl_assignments ';' */ #line 1735 "VParseBison.y" { } #line 23282 "VParseBison.c" break; case 343: /* data_declarationVarFront: constE "var" lifetimeE data_type */ #line 1740 "VParseBison.y" { VARRESET(); VARDECL("var"); VARDTYPE(SPACED((yyvsp[-3].str),(yyvsp[0].str))); } #line 23288 "VParseBison.c" break; case 344: /* data_declarationVarFront: constE "var" lifetimeE */ #line 1741 "VParseBison.y" { VARRESET(); VARDECL("var"); VARDTYPE((yyvsp[-2].str)); } #line 23294 "VParseBison.c" break; case 345: /* data_declarationVarFront: constE "var" lifetimeE signingE rangeList */ #line 1742 "VParseBison.y" { VARRESET(); VARDECL("var"); VARDTYPE(SPACED((yyvsp[-4].str),SPACED((yyvsp[-1].str),(yyvsp[0].str)))); } #line 23300 "VParseBison.c" break; case 346: /* data_declarationVarFront: data_typeVar */ #line 1745 "VParseBison.y" { VARRESET(); VARDECL("var"); VARDTYPE((yyvsp[0].str)); } #line 23306 "VParseBison.c" break; case 347: /* data_declarationVarFront: lifetime data_typeVar */ #line 1746 "VParseBison.y" { VARRESET(); VARDECL("var"); VARDTYPE((yyvsp[0].str)); } #line 23312 "VParseBison.c" break; case 348: /* data_declarationVarFront: "const" lifetimeE data_typeVar */ #line 1747 "VParseBison.y" { VARRESET(); VARDECL("var"); VARDTYPE(SPACED((yyvsp[-2].str),(yyvsp[0].str))); } #line 23318 "VParseBison.c" break; case 349: /* data_declarationVarFrontClass: "var" lifetimeE data_type */ #line 1758 "VParseBison.y" { VARDECL("var"); VARDTYPE(SPACED(GRAMMARP->m_var.m_dtype, (yyvsp[0].str))); } #line 23324 "VParseBison.c" break; case 350: /* data_declarationVarFrontClass: "var" lifetimeE */ #line 1759 "VParseBison.y" { VARDECL("var"); VARDTYPE(GRAMMARP->m_var.m_dtype); } #line 23330 "VParseBison.c" break; case 351: /* data_declarationVarFrontClass: "var" lifetimeE signingE rangeList */ #line 1760 "VParseBison.y" { VARDECL("var"); VARDTYPE(SPACED(GRAMMARP->m_var.m_dtype, SPACED((yyvsp[-1].str), (yyvsp[0].str)))); } #line 23336 "VParseBison.c" break; case 352: /* data_declarationVarFrontClass: data_typeVar */ #line 1763 "VParseBison.y" { VARDECL("var"); VARDTYPE(SPACED(GRAMMARP->m_var.m_dtype, (yyvsp[0].str))); } #line 23342 "VParseBison.c" break; case 353: /* net_type_declaration: "nettype" data_type idAny ';' */ #line 1771 "VParseBison.y" { PARSEP->syms().replaceInsert(VAstType::TYPE, (yyvsp[-1].str)); } #line 23348 "VParseBison.c" break; case 354: /* net_type_declaration: "nettype" data_type idAny "with" package_scopeIdFollowsE id ';' */ #line 1774 "VParseBison.y" { PARSEP->syms().replaceInsert(VAstType::TYPE, (yyvsp[-4].str)); } #line 23354 "VParseBison.c" break; case 355: /* net_type_declaration: "nettype" package_scopeIdFollowsE id idAny ';' */ #line 1776 "VParseBison.y" { PARSEP->syms().replaceInsert(VAstType::TYPE, (yyvsp[-1].str)); } #line 23360 "VParseBison.c" break; case 356: /* constE: %empty */ #line 1780 "VParseBison.y" { (yyval.str) = ""; } #line 23366 "VParseBison.c" break; case 357: /* constE: "const" */ #line 1781 "VParseBison.y" { (yyval.str) = (yyvsp[0].str); } #line 23372 "VParseBison.c" break; case 358: /* implicit_typeE: %empty */ #line 1786 "VParseBison.y" { (yyval.str) = ""; } #line 23378 "VParseBison.c" break; case 359: /* implicit_typeE: signingE rangeList */ #line 1787 "VParseBison.y" { (yyval.str) = SPACED((yyvsp[-1].str),(yyvsp[0].str)); } #line 23384 "VParseBison.c" break; case 360: /* implicit_typeE: signing */ #line 1788 "VParseBison.y" { (yyval.str) = (yyvsp[0].str); } #line 23390 "VParseBison.c" break; case 361: /* assertion_variable_declaration: var_data_type list_of_variable_decl_assignments ';' */ #line 1793 "VParseBison.y" { } #line 23396 "VParseBison.c" break; case 362: /* type_declaration: "typedef" data_type idAny variable_dimensionListE ';' */ #line 1799 "VParseBison.y" { VARDONETYPEDEF((yyvsp[-4].fl),(yyvsp[-2].str),(yyvsp[-3].str),(yyvsp[-1].str)); } #line 23402 "VParseBison.c" break; case 363: /* type_declaration: "typedef" id bit_selectE '.' idAny idAny ';' */ #line 1801 "VParseBison.y" { VARDONETYPEDEF((yyvsp[-6].fl),(yyvsp[-1].str),(yyvsp[-5].str)+(yyvsp[-4].str)+"."+(yyvsp[-2].str),""); } #line 23408 "VParseBison.c" break; case 364: /* type_declaration: "typedef" id ';' */ #line 1803 "VParseBison.y" { VARDONETYPEDEF((yyvsp[-2].fl),(yyvsp[-1].str),"",""); } #line 23414 "VParseBison.c" break; case 365: /* type_declaration: "typedef" "enum" idAny ';' */ #line 1804 "VParseBison.y" { PARSEP->syms().replaceInsert(VAstType::ENUM, (yyvsp[-1].str)); } #line 23420 "VParseBison.c" break; case 366: /* type_declaration: "typedef" "struct" idAny ';' */ #line 1805 "VParseBison.y" { PARSEP->syms().replaceInsert(VAstType::STRUCT, (yyvsp[-1].str)); } #line 23426 "VParseBison.c" break; case 367: /* type_declaration: "typedef" "union" idAny ';' */ #line 1806 "VParseBison.y" { PARSEP->syms().replaceInsert(VAstType::UNION, (yyvsp[-1].str)); } #line 23432 "VParseBison.c" break; case 368: /* type_declaration: "typedef" "class" idAny ';' */ #line 1807 "VParseBison.y" { PARSEP->syms().replaceInsert(VAstType::CLASS, (yyvsp[-1].str)); } #line 23438 "VParseBison.c" break; case 369: /* type_declaration: "typedef" "interface" "class" idAny ';' */ #line 1808 "VParseBison.y" { PARSEP->syms().replaceInsert(VAstType::CLASS, (yyvsp[-2].str)); } #line 23444 "VParseBison.c" break; case 370: /* module_itemListE: %empty */ #line 1815 "VParseBison.y" { } #line 23450 "VParseBison.c" break; case 371: /* module_itemListE: module_itemList */ #line 1816 "VParseBison.y" { } #line 23456 "VParseBison.c" break; case 372: /* module_itemList: module_item */ #line 1820 "VParseBison.y" { } #line 23462 "VParseBison.c" break; case 373: /* module_itemList: module_itemList module_item */ #line 1821 "VParseBison.y" { } #line 23468 "VParseBison.c" break; case 374: /* module_item: port_declaration ';' */ #line 1825 "VParseBison.y" { } #line 23474 "VParseBison.c" break; case 375: /* module_item: non_port_module_item */ #line 1826 "VParseBison.y" { } #line 23480 "VParseBison.c" break; case 376: /* non_port_module_item: generate_region */ #line 1830 "VParseBison.y" { } #line 23486 "VParseBison.c" break; case 377: /* non_port_module_item: module_or_generate_item */ #line 1831 "VParseBison.y" { } #line 23492 "VParseBison.c" break; case 378: /* non_port_module_item: specify_block */ #line 1832 "VParseBison.y" { } #line 23498 "VParseBison.c" break; case 379: /* non_port_module_item: specparam_declaration */ #line 1833 "VParseBison.y" { } #line 23504 "VParseBison.c" break; case 380: /* non_port_module_item: program_declaration */ #line 1834 "VParseBison.y" { } #line 23510 "VParseBison.c" break; case 381: /* non_port_module_item: module_declaration */ #line 1835 "VParseBison.y" { } #line 23516 "VParseBison.c" break; case 382: /* non_port_module_item: interface_declaration */ #line 1836 "VParseBison.y" { } #line 23522 "VParseBison.c" break; case 383: /* non_port_module_item: timeunits_declaration */ #line 1837 "VParseBison.y" { } #line 23528 "VParseBison.c" break; case 384: /* module_or_generate_item: "defparam" list_of_defparam_assignments ';' */ #line 1842 "VParseBison.y" { } #line 23534 "VParseBison.c" break; case 385: /* module_or_generate_item: combinational_body */ #line 1846 "VParseBison.y" { } #line 23540 "VParseBison.c" break; case 386: /* module_or_generate_item: module_common_item */ #line 1848 "VParseBison.y" { } #line 23546 "VParseBison.c" break; case 387: /* module_common_item: module_or_generate_item_declaration */ #line 1852 "VParseBison.y" { } #line 23552 "VParseBison.c" break; case 388: /* module_common_item: etcInst */ #line 1856 "VParseBison.y" { } #line 23558 "VParseBison.c" break; case 389: /* module_common_item: assertion_item */ #line 1857 "VParseBison.y" { } #line 23564 "VParseBison.c" break; case 390: /* module_common_item: bind_directive */ #line 1858 "VParseBison.y" { } #line 23570 "VParseBison.c" break; case 391: /* module_common_item: continuous_assign */ #line 1859 "VParseBison.y" { } #line 23576 "VParseBison.c" break; case 392: /* module_common_item: "alias" variable_lvalue aliasEqList ';' */ #line 1861 "VParseBison.y" { } #line 23582 "VParseBison.c" break; case 393: /* module_common_item: initial_construct */ #line 1862 "VParseBison.y" { } #line 23588 "VParseBison.c" break; case 394: /* module_common_item: final_construct */ #line 1863 "VParseBison.y" { } #line 23594 "VParseBison.c" break; case 395: /* module_common_item: "always" stmtBlock */ #line 1865 "VParseBison.y" { } #line 23600 "VParseBison.c" break; case 396: /* module_common_item: loop_generate_construct */ #line 1866 "VParseBison.y" { } #line 23606 "VParseBison.c" break; case 397: /* module_common_item: conditional_generate_construct */ #line 1867 "VParseBison.y" { } #line 23612 "VParseBison.c" break; case 398: /* module_common_item: elaboration_system_task */ #line 1868 "VParseBison.y" { } #line 23618 "VParseBison.c" break; case 399: /* module_common_item: error ';' */ #line 1870 "VParseBison.y" { } #line 23624 "VParseBison.c" break; case 400: /* continuous_assign: "assign" strengthSpecE delayE assignList ';' */ #line 1874 "VParseBison.y" { } #line 23630 "VParseBison.c" break; case 401: /* initial_construct: "initial" stmtBlock */ #line 1878 "VParseBison.y" { } #line 23636 "VParseBison.c" break; case 402: /* final_construct: "final" stmtBlock */ #line 1882 "VParseBison.y" { } #line 23642 "VParseBison.c" break; case 403: /* module_or_generate_item_declaration: package_or_generate_item_declaration */ #line 1886 "VParseBison.y" { } #line 23648 "VParseBison.c" break; case 404: /* module_or_generate_item_declaration: genvar_declaration */ #line 1887 "VParseBison.y" { } #line 23654 "VParseBison.c" break; case 405: /* module_or_generate_item_declaration: clocking_declaration */ #line 1888 "VParseBison.y" { } #line 23660 "VParseBison.c" break; case 406: /* module_or_generate_item_declaration: "default" "clocking" idAny ';' */ #line 1889 "VParseBison.y" { } #line 23666 "VParseBison.c" break; case 407: /* module_or_generate_item_declaration: "default" "disable" "iff" expr ';' */ #line 1890 "VParseBison.y" { } #line 23672 "VParseBison.c" break; case 408: /* aliasEqList: '=' variable_lvalue */ #line 1894 "VParseBison.y" { } #line 23678 "VParseBison.c" break; case 409: /* aliasEqList: aliasEqList '=' variable_lvalue */ #line 1895 "VParseBison.y" { } #line 23684 "VParseBison.c" break; case 410: /* bind_directive: "bind" bind_target_instance bind_instantiation */ #line 1901 "VParseBison.y" { } #line 23690 "VParseBison.c" break; case 411: /* bind_directive: "bind" bind_target_instance ':' bind_target_instance_list bind_instantiation */ #line 1902 "VParseBison.y" { } #line 23696 "VParseBison.c" break; case 412: /* bind_target_instance_list: bind_target_instance */ #line 1906 "VParseBison.y" { } #line 23702 "VParseBison.c" break; case 413: /* bind_target_instance_list: bind_target_instance_list ',' bind_target_instance */ #line 1907 "VParseBison.y" { } #line 23708 "VParseBison.c" break; case 414: /* bind_target_instance: hierarchical_identifierBit */ #line 1911 "VParseBison.y" { } #line 23714 "VParseBison.c" break; case 415: /* bind_instantiation: etcInst */ #line 1918 "VParseBison.y" { } #line 23720 "VParseBison.c" break; case 416: /* generate_region: "generate" genItemList "endgenerate" */ #line 1930 "VParseBison.y" { } #line 23726 "VParseBison.c" break; case 417: /* generate_region: "generate" "endgenerate" */ #line 1931 "VParseBison.y" { } #line 23732 "VParseBison.c" break; case 418: /* c_generate_region: "generate" c_genItemList "endgenerate" */ #line 1935 "VParseBison.y" { } #line 23738 "VParseBison.c" break; case 419: /* c_generate_region: "generate" "endgenerate" */ #line 1935 "VParseBison.y" { } #line 23744 "VParseBison.c" break; case 420: /* generate_block: generate_item */ #line 1940 "VParseBison.y" { } #line 23750 "VParseBison.c" break; case 421: /* generate_block: genItemBegin */ #line 1941 "VParseBison.y" { } #line 23756 "VParseBison.c" break; case 422: /* c_generate_block: c_generate_item */ #line 1945 "VParseBison.y" { } #line 23762 "VParseBison.c" break; case 423: /* c_generate_block: c_genItemBegin */ #line 1945 "VParseBison.y" { } #line 23768 "VParseBison.c" break; case 424: /* genItemBegin: "begin" genItemList "end" */ #line 1949 "VParseBison.y" { } #line 23774 "VParseBison.c" break; case 425: /* genItemBegin: "begin" "end" */ #line 1950 "VParseBison.y" { } #line 23780 "VParseBison.c" break; case 426: /* genItemBegin: id ':' "begin" genItemList "end" endLabelE */ #line 1951 "VParseBison.y" { } #line 23786 "VParseBison.c" break; case 427: /* genItemBegin: id ':' "begin" "end" endLabelE */ #line 1952 "VParseBison.y" { } #line 23792 "VParseBison.c" break; case 428: /* genItemBegin: "begin" ':' idAny genItemList "end" endLabelE */ #line 1953 "VParseBison.y" { } #line 23798 "VParseBison.c" break; case 429: /* genItemBegin: "begin" ':' idAny "end" endLabelE */ #line 1954 "VParseBison.y" { } #line 23804 "VParseBison.c" break; case 430: /* c_genItemBegin: "begin" c_genItemList "end" */ #line 1958 "VParseBison.y" { } #line 23810 "VParseBison.c" break; case 431: /* c_genItemBegin: "begin" "end" */ #line 1958 "VParseBison.y" { } #line 23816 "VParseBison.c" break; case 432: /* c_genItemBegin: id ':' "begin" c_genItemList "end" endLabelE */ #line 1958 "VParseBison.y" { } #line 23822 "VParseBison.c" break; case 433: /* c_genItemBegin: id ':' "begin" "end" endLabelE */ #line 1958 "VParseBison.y" { } #line 23828 "VParseBison.c" break; case 434: /* c_genItemBegin: "begin" ':' idAny c_genItemList "end" endLabelE */ #line 1958 "VParseBison.y" { } #line 23834 "VParseBison.c" break; case 435: /* c_genItemBegin: "begin" ':' idAny "end" endLabelE */ #line 1958 "VParseBison.y" { } #line 23840 "VParseBison.c" break; case 436: /* genItemOrBegin: generate_item */ #line 1962 "VParseBison.y" { } #line 23846 "VParseBison.c" break; case 437: /* genItemOrBegin: genItemBegin */ #line 1963 "VParseBison.y" { } #line 23852 "VParseBison.c" break; case 438: /* c_genItemOrBegin: c_generate_item */ #line 1967 "VParseBison.y" { } #line 23858 "VParseBison.c" break; case 439: /* c_genItemOrBegin: c_genItemBegin */ #line 1967 "VParseBison.y" { } #line 23864 "VParseBison.c" break; case 440: /* genItemList: genItemOrBegin */ #line 1971 "VParseBison.y" { } #line 23870 "VParseBison.c" break; case 441: /* genItemList: genItemList genItemOrBegin */ #line 1972 "VParseBison.y" { } #line 23876 "VParseBison.c" break; case 442: /* c_genItemList: c_genItemOrBegin */ #line 1976 "VParseBison.y" { } #line 23882 "VParseBison.c" break; case 443: /* c_genItemList: c_genItemList c_genItemOrBegin */ #line 1976 "VParseBison.y" { } #line 23888 "VParseBison.c" break; case 444: /* generate_item: module_or_generate_item */ #line 1981 "VParseBison.y" { } #line 23894 "VParseBison.c" break; case 445: /* generate_item: interface_or_generate_item */ #line 1983 "VParseBison.y" { } #line 23900 "VParseBison.c" break; case 446: /* c_generate_item: checker_or_generate_item */ #line 1990 "VParseBison.y" { } #line 23906 "VParseBison.c" break; case 447: /* conditional_generate_construct: "case" '(' expr ')' "endcase" */ #line 1995 "VParseBison.y" { } #line 23912 "VParseBison.c" break; case 448: /* conditional_generate_construct: "case" '(' expr ')' case_generate_itemList "endcase" */ #line 1996 "VParseBison.y" { } #line 23918 "VParseBison.c" break; case 449: /* conditional_generate_construct: "if" '(' expr ')' generate_block */ #line 1998 "VParseBison.y" { } #line 23924 "VParseBison.c" break; case 450: /* conditional_generate_construct: "if" '(' expr ')' generate_block "else" generate_block */ #line 1999 "VParseBison.y" { } #line 23930 "VParseBison.c" break; case 451: /* c_conditional_generate_construct: "case" '(' expr ')' "endcase" */ #line 2003 "VParseBison.y" { } #line 23936 "VParseBison.c" break; case 452: /* c_conditional_generate_construct: "case" '(' expr ')' c_case_generate_itemList "endcase" */ #line 2003 "VParseBison.y" { } #line 23942 "VParseBison.c" break; case 453: /* c_conditional_generate_construct: "if" '(' expr ')' c_generate_block */ #line 2003 "VParseBison.y" { } #line 23948 "VParseBison.c" break; case 454: /* c_conditional_generate_construct: "if" '(' expr ')' c_generate_block "else" c_generate_block */ #line 2003 "VParseBison.y" { } #line 23954 "VParseBison.c" break; case 455: /* loop_generate_construct: "for" '(' genvar_initialization ';' expr ';' genvar_iteration ')' generate_block */ #line 2008 "VParseBison.y" { } #line 23960 "VParseBison.c" break; case 456: /* c_loop_generate_construct: "for" '(' genvar_initialization ';' expr ';' genvar_iteration ')' c_generate_block */ #line 2012 "VParseBison.y" { } #line 23966 "VParseBison.c" break; case 457: /* genvar_initialization: id '=' constExpr */ #line 2016 "VParseBison.y" { } #line 23972 "VParseBison.c" break; case 458: /* genvar_initialization: "genvar" genvar_identifierDecl '=' constExpr */ #line 2017 "VParseBison.y" { } #line 23978 "VParseBison.c" break; case 460: /* genvar_iteration: id '=' expr */ #line 2022 "VParseBison.y" { } #line 23984 "VParseBison.c" break; case 461: /* genvar_iteration: id "+=" expr */ #line 2023 "VParseBison.y" { } #line 23990 "VParseBison.c" break; case 462: /* genvar_iteration: id "-=" expr */ #line 2024 "VParseBison.y" { } #line 23996 "VParseBison.c" break; case 463: /* genvar_iteration: id "*=" expr */ #line 2025 "VParseBison.y" { } #line 24002 "VParseBison.c" break; case 464: /* genvar_iteration: id "/=" expr */ #line 2026 "VParseBison.y" { } #line 24008 "VParseBison.c" break; case 465: /* genvar_iteration: id "%=" expr */ #line 2027 "VParseBison.y" { } #line 24014 "VParseBison.c" break; case 466: /* genvar_iteration: id "&=" expr */ #line 2028 "VParseBison.y" { } #line 24020 "VParseBison.c" break; case 467: /* genvar_iteration: id "|=" expr */ #line 2029 "VParseBison.y" { } #line 24026 "VParseBison.c" break; case 468: /* genvar_iteration: id "^=" expr */ #line 2030 "VParseBison.y" { } #line 24032 "VParseBison.c" break; case 469: /* genvar_iteration: id "<<=" expr */ #line 2031 "VParseBison.y" { } #line 24038 "VParseBison.c" break; case 470: /* genvar_iteration: id ">>=" expr */ #line 2032 "VParseBison.y" { } #line 24044 "VParseBison.c" break; case 471: /* genvar_iteration: id ">>>=" expr */ #line 2033 "VParseBison.y" { } #line 24050 "VParseBison.c" break; case 472: /* genvar_iteration: "++" id */ #line 2035 "VParseBison.y" { } #line 24056 "VParseBison.c" break; case 473: /* genvar_iteration: "--" id */ #line 2036 "VParseBison.y" { } #line 24062 "VParseBison.c" break; case 474: /* genvar_iteration: id "++" */ #line 2037 "VParseBison.y" { } #line 24068 "VParseBison.c" break; case 475: /* genvar_iteration: id "--" */ #line 2038 "VParseBison.y" { } #line 24074 "VParseBison.c" break; case 476: /* case_generate_itemList: case_generate_item */ #line 2042 "VParseBison.y" { } #line 24080 "VParseBison.c" break; case 477: /* case_generate_itemList: case_generate_itemList case_generate_item */ #line 2043 "VParseBison.y" { } #line 24086 "VParseBison.c" break; case 478: /* c_case_generate_itemList: c_case_generate_item */ #line 2047 "VParseBison.y" { } #line 24092 "VParseBison.c" break; case 479: /* c_case_generate_itemList: c_case_generate_itemList c_case_generate_item */ #line 2047 "VParseBison.y" { } #line 24098 "VParseBison.c" break; case 480: /* case_generate_item: caseCondList ':' generate_block */ #line 2051 "VParseBison.y" { } #line 24104 "VParseBison.c" break; case 481: /* case_generate_item: "default" ':' generate_block */ #line 2052 "VParseBison.y" { } #line 24110 "VParseBison.c" break; case 482: /* case_generate_item: "default" generate_block */ #line 2053 "VParseBison.y" { } #line 24116 "VParseBison.c" break; case 483: /* c_case_generate_item: caseCondList ':' c_generate_block */ #line 2057 "VParseBison.y" { } #line 24122 "VParseBison.c" break; case 484: /* c_case_generate_item: "default" ':' c_generate_block */ #line 2057 "VParseBison.y" { } #line 24128 "VParseBison.c" break; case 485: /* c_case_generate_item: "default" c_generate_block */ #line 2057 "VParseBison.y" { } #line 24134 "VParseBison.c" break; case 486: /* assignList: assignOne */ #line 2064 "VParseBison.y" { } #line 24140 "VParseBison.c" break; case 487: /* assignList: assignList ',' assignOne */ #line 2065 "VParseBison.y" { } #line 24146 "VParseBison.c" break; case 488: /* assignOne: variable_lvalue '=' expr */ #line 2069 "VParseBison.y" { PARSEP->contassignCb((yyvsp[-1].fl),"assign",(yyvsp[-2].str),(yyvsp[0].str)); } #line 24152 "VParseBison.c" break; case 489: /* delay_or_event_controlE: %empty */ #line 2073 "VParseBison.y" { } #line 24158 "VParseBison.c" break; case 490: /* delay_or_event_controlE: delay_control */ #line 2074 "VParseBison.y" { } #line 24164 "VParseBison.c" break; case 491: /* delay_or_event_controlE: event_control */ #line 2075 "VParseBison.y" { } #line 24170 "VParseBison.c" break; case 492: /* delay_or_event_controlE: "repeat" '(' expr ')' event_control */ #line 2076 "VParseBison.y" { } #line 24176 "VParseBison.c" break; case 493: /* delayE: %empty */ #line 2080 "VParseBison.y" { } #line 24182 "VParseBison.c" break; case 494: /* delayE: delay_control */ #line 2081 "VParseBison.y" { } #line 24188 "VParseBison.c" break; case 495: /* delay_control: '#' delay_value */ #line 2085 "VParseBison.y" { } #line 24194 "VParseBison.c" break; case 496: /* delay_control: '#' '(' minTypMax ')' */ #line 2086 "VParseBison.y" { } #line 24200 "VParseBison.c" break; case 497: /* delay_control: '#' '(' minTypMax ',' minTypMax ')' */ #line 2087 "VParseBison.y" { } #line 24206 "VParseBison.c" break; case 498: /* delay_control: '#' '(' minTypMax ',' minTypMax ',' minTypMax ')' */ #line 2088 "VParseBison.y" { } #line 24212 "VParseBison.c" break; case 499: /* delay_value: ps_id_etc */ #line 2093 "VParseBison.y" { } #line 24218 "VParseBison.c" break; case 500: /* delay_value: "INTEGER NUMBER" */ #line 2094 "VParseBison.y" { } #line 24224 "VParseBison.c" break; case 501: /* delay_value: "FLOATING-POINT NUMBER" */ #line 2095 "VParseBison.y" { } #line 24230 "VParseBison.c" break; case 502: /* delay_value: "TIME NUMBER" */ #line 2096 "VParseBison.y" { } #line 24236 "VParseBison.c" break; case 503: /* delayExpr: expr */ #line 2100 "VParseBison.y" { } #line 24242 "VParseBison.c" break; case 504: /* minTypMax: delayExpr */ #line 2104 "VParseBison.y" { } #line 24248 "VParseBison.c" break; case 505: /* minTypMax: delayExpr ':' delayExpr ':' delayExpr */ #line 2105 "VParseBison.y" { } #line 24254 "VParseBison.c" break; case 506: /* netSigList: netSig */ #line 2109 "VParseBison.y" { } #line 24260 "VParseBison.c" break; case 507: /* netSigList: netSigList ',' netSig */ #line 2110 "VParseBison.y" { } #line 24266 "VParseBison.c" break; case 508: /* netSig: netId sigAttrListE */ #line 2114 "VParseBison.y" { VARDONE((yyvsp[-1].fl), (yyvsp[-1].str), "", ""); } #line 24272 "VParseBison.c" break; case 509: /* netSig: netId sigAttrListE '=' expr */ #line 2115 "VParseBison.y" { VARDONE((yyvsp[-3].fl), (yyvsp[-3].str), "", (yyvsp[0].str)); } #line 24278 "VParseBison.c" break; case 510: /* netSig: netId variable_dimensionList sigAttrListE */ #line 2116 "VParseBison.y" { VARDONE((yyvsp[-2].fl), (yyvsp[-2].str), (yyvsp[-1].str), ""); } #line 24284 "VParseBison.c" break; case 511: /* netId: id */ #line 2120 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 24290 "VParseBison.c" break; case 512: /* netId: idSVKwd */ #line 2121 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 24296 "VParseBison.c" break; case 513: /* sigAttrListE: %empty */ #line 2125 "VParseBison.y" { } #line 24302 "VParseBison.c" break; case 514: /* rangeListE: %empty */ #line 2129 "VParseBison.y" { (yyval.str)=""; } #line 24308 "VParseBison.c" break; case 515: /* rangeListE: rangeList */ #line 2130 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 24314 "VParseBison.c" break; case 516: /* rangeList: anyrange */ #line 2134 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 24320 "VParseBison.c" break; case 517: /* rangeList: rangeList anyrange */ #line 2135 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 24326 "VParseBison.c" break; case 518: /* regrangeE: %empty */ #line 2139 "VParseBison.y" { (yyval.str)=""; } #line 24332 "VParseBison.c" break; case 519: /* regrangeE: anyrange */ #line 2140 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 24338 "VParseBison.c" break; case 520: /* bit_selectE: %empty */ #line 2144 "VParseBison.y" { (yyval.str) = ""; } #line 24344 "VParseBison.c" break; case 521: /* bit_selectE: '[' constExpr ']' */ #line 2145 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = "["+(yyvsp[-1].str)+"]"; } #line 24350 "VParseBison.c" break; case 522: /* anyrange: '[' constExpr ':' constExpr ']' */ #line 2152 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "["+(yyvsp[-3].str)+":"+(yyvsp[-1].str)+"]"; } #line 24356 "VParseBison.c" break; case 523: /* packed_dimensionListE: %empty */ #line 2156 "VParseBison.y" { (yyval.str)=""; } #line 24362 "VParseBison.c" break; case 524: /* packed_dimensionListE: packed_dimensionList */ #line 2157 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 24368 "VParseBison.c" break; case 525: /* packed_dimensionList: packed_dimension */ #line 2161 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 24374 "VParseBison.c" break; case 526: /* packed_dimensionList: packed_dimensionList packed_dimension */ #line 2162 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str)=(yyvsp[-1].str)+(yyvsp[0].str); } #line 24380 "VParseBison.c" break; case 527: /* packed_dimension: anyrange */ #line 2166 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 24386 "VParseBison.c" break; case 528: /* packed_dimension: '[' ']' */ #line 2167 "VParseBison.y" { (yyval.str)="[]"; } #line 24392 "VParseBison.c" break; case 529: /* param_assignment: id variable_dimensionListE sigAttrListE '=' exprOrDataTypeOrMinTypMax */ #line 2177 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); VARDONE((yyvsp[-4].fl), (yyvsp[-4].str), (yyvsp[-3].str), (yyvsp[0].str)); } #line 24398 "VParseBison.c" break; case 530: /* param_assignment: id variable_dimensionListE sigAttrListE */ #line 2180 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); VARDONE((yyvsp[-2].fl), (yyvsp[-2].str), (yyvsp[-1].str), ""); NEED_S09((yyvsp[-2].fl),"optional parameter defaults"); } #line 24404 "VParseBison.c" break; case 531: /* list_of_param_assignments: param_assignment */ #line 2184 "VParseBison.y" { } #line 24410 "VParseBison.c" break; case 532: /* list_of_param_assignments: list_of_param_assignments ',' param_assignment */ #line 2185 "VParseBison.y" { } #line 24416 "VParseBison.c" break; case 533: /* list_of_defparam_assignments: defparam_assignment */ #line 2189 "VParseBison.y" { } #line 24422 "VParseBison.c" break; case 534: /* list_of_defparam_assignments: list_of_defparam_assignments ',' defparam_assignment */ #line 2190 "VParseBison.y" { } #line 24428 "VParseBison.c" break; case 535: /* defparam_assignment: hierarchical_identifier '=' expr */ #line 2194 "VParseBison.y" { PARSEP->defparamCb((yyvsp[-1].fl),"defparam",(yyvsp[-2].str),(yyvsp[0].str)); } #line 24434 "VParseBison.c" break; case 536: /* $@13: %empty */ #line 2207 "VParseBison.y" { INSTPREP((yyvsp[0].str),1,0); } #line 24440 "VParseBison.c" break; case 537: /* $@14: %empty */ #line 2207 "VParseBison.y" { INSTPREP((yyvsp[-3].str),0,1); } #line 24446 "VParseBison.c" break; case 538: /* etcInst: instName $@13 strengthSpecE parameter_value_assignmentE $@14 instnameList ';' */ #line 2208 "VParseBison.y" { INSTDONE(); } #line 24452 "VParseBison.c" break; case 539: /* $@15: %empty */ #line 2210 "VParseBison.y" { INSTPREP((yyvsp[0].str),1,0); } #line 24458 "VParseBison.c" break; case 540: /* $@16: %empty */ #line 2210 "VParseBison.y" {INSTPREP((yyvsp[-3].str),0,0);} #line 24464 "VParseBison.c" break; case 541: /* etcInst: instName $@15 '.' id $@16 mpInstnameList ';' */ #line 2211 "VParseBison.y" { INSTDONE(); } #line 24470 "VParseBison.c" break; case 542: /* instName: gateKwd */ #line 2215 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 24476 "VParseBison.c" break; case 543: /* instName: id */ #line 2220 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 24482 "VParseBison.c" break; case 544: /* mpInstnameList: mpInstnameParen */ #line 2224 "VParseBison.y" { } #line 24488 "VParseBison.c" break; case 545: /* mpInstnameList: mpInstnameList ',' mpInstnameParen */ #line 2225 "VParseBison.y" { } #line 24494 "VParseBison.c" break; case 546: /* mpInstnameParen: mpInstname */ #line 2229 "VParseBison.y" { PARSEP->endcellCb((yyvsp[0].fl),""); } #line 24500 "VParseBison.c" break; case 547: /* mpInstname: id instRangeListE */ #line 2234 "VParseBison.y" { PARSEP->instantCb((yyvsp[-1].fl), GRAMMARP->m_cellMod, (yyvsp[-1].str), (yyvsp[0].str)); } #line 24506 "VParseBison.c" break; case 548: /* instnameList: instnameParen */ #line 2238 "VParseBison.y" { } #line 24512 "VParseBison.c" break; case 549: /* instnameList: instnameList ',' instnameParen */ #line 2239 "VParseBison.y" { } #line 24518 "VParseBison.c" break; case 550: /* instnameParen: instname cellpinList ')' */ #line 2243 "VParseBison.y" { PARSEP->endcellCb((yyvsp[0].fl),""); } #line 24524 "VParseBison.c" break; case 551: /* instname: id instRangeListE '(' */ #line 2251 "VParseBison.y" { PARSEP->instantCb((yyvsp[-2].fl), GRAMMARP->m_cellMod, (yyvsp[-2].str), (yyvsp[-1].str)); PINPARAMS(); } #line 24530 "VParseBison.c" break; case 552: /* instname: instRangeListE '(' */ #line 2252 "VParseBison.y" { PARSEP->instantCb((yyvsp[0].fl), GRAMMARP->m_cellMod, "", (yyvsp[-1].str)); PINPARAMS(); } #line 24536 "VParseBison.c" break; case 553: /* instRangeListE: %empty */ #line 2256 "VParseBison.y" { (yyval.str) = ""; } #line 24542 "VParseBison.c" break; case 554: /* instRangeListE: instRangeList */ #line 2257 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 24548 "VParseBison.c" break; case 555: /* instRangeList: instRange */ #line 2261 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 24554 "VParseBison.c" break; case 556: /* instRangeList: instRangeList instRange */ #line 2262 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 24560 "VParseBison.c" break; case 557: /* instRange: '[' constExpr ']' */ #line 2266 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = "["+(yyvsp[-1].str)+"]"; } #line 24566 "VParseBison.c" break; case 558: /* instRange: '[' constExpr ':' constExpr ']' */ #line 2267 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "["+(yyvsp[-3].str)+":"+(yyvsp[-1].str)+"]"; } #line 24572 "VParseBison.c" break; case 559: /* $@17: %empty */ #line 2271 "VParseBison.y" { VARRESET_LIST(""); } #line 24578 "VParseBison.c" break; case 560: /* cellpinList: $@17 cellpinItList */ #line 2271 "VParseBison.y" { VARRESET_NONLIST(""); GRAMMARP->m_withinPin = false; } #line 24584 "VParseBison.c" break; case 561: /* $@18: %empty */ #line 2275 "VParseBison.y" { GRAMMARP->m_portNextNetName.clear(); } #line 24590 "VParseBison.c" break; case 562: /* cellpinItList: $@18 cellpinItemE */ #line 2275 "VParseBison.y" { } #line 24596 "VParseBison.c" break; case 563: /* cellpinItList: cellpinItList ',' cellpinItemE */ #line 2276 "VParseBison.y" { } #line 24602 "VParseBison.c" break; case 564: /* cellpinItemE: %empty */ #line 2280 "VParseBison.y" { PINNUMINC(); } #line 24608 "VParseBison.c" break; case 565: /* cellpinItemE: ".*" */ #line 2281 "VParseBison.y" { PINDONE((yyvsp[0].fl),"*","*");PINNUMINC(); } #line 24614 "VParseBison.c" break; case 566: /* cellpinItemE: '.' idSVKwd */ #line 2282 "VParseBison.y" { PINDONE((yyvsp[-1].fl),(yyvsp[0].str),(yyvsp[0].str)); PINNUMINC(); } #line 24620 "VParseBison.c" break; case 567: /* cellpinItemE: '.' idAny */ #line 2283 "VParseBison.y" { PINDONE((yyvsp[-1].fl),(yyvsp[0].str),(yyvsp[0].str)); PINNUMINC(); } #line 24626 "VParseBison.c" break; case 568: /* cellpinItemE: '.' idAny '(' ')' */ #line 2284 "VParseBison.y" { PINDONE((yyvsp[-3].fl),(yyvsp[-2].str),""); PINNUMINC(); } #line 24632 "VParseBison.c" break; case 569: /* cellpinItemE: '.' idAny '(' pev_expr ')' */ #line 2287 "VParseBison.y" { PINDONE((yyvsp[-4].fl),(yyvsp[-3].str),(yyvsp[-1].str)); PINNUMINC(); } #line 24638 "VParseBison.c" break; case 570: /* cellpinItemE: '.' idAny '(' pev_expr ':' expr ')' */ #line 2288 "VParseBison.y" { PINDONE((yyvsp[-6].fl),(yyvsp[-5].str),(yyvsp[-3].str)); PINNUMINC(); } #line 24644 "VParseBison.c" break; case 571: /* cellpinItemE: '.' idAny '(' pev_expr ':' expr ':' expr ')' */ #line 2289 "VParseBison.y" { PINDONE((yyvsp[-8].fl),(yyvsp[-7].str),(yyvsp[-5].str)); PINNUMINC(); } #line 24650 "VParseBison.c" break; case 572: /* cellpinItemE: '.' idAny '(' data_type ')' */ #line 2291 "VParseBison.y" { PINDONE((yyvsp[-4].fl),(yyvsp[-3].str),(yyvsp[-1].str)); PINNUMINC(); } #line 24656 "VParseBison.c" break; case 573: /* cellpinItemE: data_type */ #line 2293 "VParseBison.y" { PINDONE((yyvsp[0].fl),"",(yyvsp[0].str)); PINNUMINC(); } #line 24662 "VParseBison.c" break; case 574: /* cellpinItemE: expr */ #line 2295 "VParseBison.y" { PINDONE((yyvsp[0].fl),"",(yyvsp[0].str)); PINNUMINC(); } #line 24668 "VParseBison.c" break; case 575: /* cellpinItemE: expr ':' expr */ #line 2296 "VParseBison.y" { PINDONE((yyvsp[-2].fl),"",(yyvsp[-2].str)); PINNUMINC(); } #line 24674 "VParseBison.c" break; case 576: /* cellpinItemE: expr ':' expr ':' expr */ #line 2297 "VParseBison.y" { PINDONE((yyvsp[-4].fl),"",(yyvsp[-4].str)); PINNUMINC(); } #line 24680 "VParseBison.c" break; case 577: /* event_control: '@' '(' event_expression ')' */ #line 2304 "VParseBison.y" { } #line 24686 "VParseBison.c" break; case 578: /* event_control: '@' '*' */ #line 2305 "VParseBison.y" { } #line 24692 "VParseBison.c" break; case 579: /* event_control: '@' '(' '*' ')' */ #line 2306 "VParseBison.y" { } #line 24698 "VParseBison.c" break; case 580: /* event_control: '@' idClassSel */ #line 2308 "VParseBison.y" { } #line 24704 "VParseBison.c" break; case 581: /* event_expression: ev_expr */ #line 2321 "VParseBison.y" { } #line 24710 "VParseBison.c" break; case 582: /* event_expression: event_expression ',' ev_expr */ #line 2322 "VParseBison.y" { } #line 24716 "VParseBison.c" break; case 583: /* senitemEdge: "posedge" expr */ #line 2327 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str)=(yyvsp[-1].str)+" "+(yyvsp[0].str); } #line 24722 "VParseBison.c" break; case 584: /* senitemEdge: "posedge" expr "iff" expr */ #line 2328 "VParseBison.y" { (yyval.fl)=(yyvsp[-3].fl); (yyval.str)=(yyvsp[-3].str)+" "+(yyvsp[-2].str)+" iff "+(yyvsp[0].str); } #line 24728 "VParseBison.c" break; case 585: /* senitemEdge: "negedge" expr */ #line 2329 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str)=(yyvsp[-1].str)+" "+(yyvsp[0].str); } #line 24734 "VParseBison.c" break; case 586: /* senitemEdge: "negedge" expr "iff" expr */ #line 2330 "VParseBison.y" { (yyval.fl)=(yyvsp[-3].fl); (yyval.str)=(yyvsp[-3].str)+" "+(yyvsp[-2].str)+" iff "+(yyvsp[0].str); } #line 24740 "VParseBison.c" break; case 587: /* senitemEdge: "edge" expr */ #line 2331 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str)=(yyvsp[-1].str)+" "+(yyvsp[0].str); NEED_S09((yyvsp[-1].fl),"edge"); } #line 24746 "VParseBison.c" break; case 588: /* senitemEdge: "edge" expr "iff" expr */ #line 2332 "VParseBison.y" { (yyval.fl)=(yyvsp[-3].fl); (yyval.str)=(yyvsp[-3].str)+" "+(yyvsp[-2].str)+" iff "+(yyvsp[0].str); NEED_S09((yyvsp[-3].fl),"edge"); } #line 24752 "VParseBison.c" break; case 589: /* stmtBlock: stmt */ #line 2339 "VParseBison.y" { } #line 24758 "VParseBison.c" break; case 590: /* seq_block: seq_blockFront blockDeclStmtList "end" endLabelE */ #line 2344 "VParseBison.y" { PARSEP->symPopScope(VAstType::BLOCK); } #line 24764 "VParseBison.c" break; case 591: /* seq_block: seq_blockFront "end" endLabelE */ #line 2345 "VParseBison.y" { PARSEP->symPopScope(VAstType::BLOCK); } #line 24770 "VParseBison.c" break; case 592: /* par_block: par_blockFront blockDeclStmtList "join" endLabelE */ #line 2349 "VParseBison.y" { PARSEP->symPopScope(VAstType::FORK); } #line 24776 "VParseBison.c" break; case 593: /* par_block: par_blockFront "join" endLabelE */ #line 2350 "VParseBison.y" { PARSEP->symPopScope(VAstType::FORK); } #line 24782 "VParseBison.c" break; case 594: /* seq_blockFront: "begin" */ #line 2354 "VParseBison.y" { PARSEP->symPushNewAnon(VAstType::BLOCK); } #line 24788 "VParseBison.c" break; case 595: /* seq_blockFront: "begin" ':' idAny */ #line 2355 "VParseBison.y" { PARSEP->symPushNew(VAstType::BLOCK,(yyvsp[-2].str)); } #line 24794 "VParseBison.c" break; case 596: /* par_blockFront: "fork" */ #line 2359 "VParseBison.y" { PARSEP->symPushNewAnon(VAstType::FORK); } #line 24800 "VParseBison.c" break; case 597: /* par_blockFront: "fork" ':' idAny */ #line 2360 "VParseBison.y" { PARSEP->symPushNew(VAstType::FORK,(yyvsp[-2].str)); } #line 24806 "VParseBison.c" break; case 598: /* blockDeclStmtList: block_item_declarationList */ #line 2365 "VParseBison.y" { } #line 24812 "VParseBison.c" break; case 599: /* blockDeclStmtList: block_item_declarationList stmtList */ #line 2366 "VParseBison.y" { } #line 24818 "VParseBison.c" break; case 600: /* blockDeclStmtList: stmtList */ #line 2367 "VParseBison.y" { } #line 24824 "VParseBison.c" break; case 601: /* block_item_declarationList: block_item_declaration */ #line 2371 "VParseBison.y" { } #line 24830 "VParseBison.c" break; case 602: /* block_item_declarationList: block_item_declarationList block_item_declaration */ #line 2372 "VParseBison.y" { } #line 24836 "VParseBison.c" break; case 603: /* block_item_declaration: data_declaration */ #line 2376 "VParseBison.y" { } #line 24842 "VParseBison.c" break; case 604: /* block_item_declaration: local_parameter_declaration ';' */ #line 2377 "VParseBison.y" { } #line 24848 "VParseBison.c" break; case 605: /* block_item_declaration: parameter_declaration ';' */ #line 2378 "VParseBison.y" { } #line 24854 "VParseBison.c" break; case 606: /* block_item_declaration: overload_declaration */ #line 2379 "VParseBison.y" { } #line 24860 "VParseBison.c" break; case 607: /* block_item_declaration: let_declaration */ #line 2380 "VParseBison.y" { } #line 24866 "VParseBison.c" break; case 608: /* stmtList: stmtBlock */ #line 2384 "VParseBison.y" { } #line 24872 "VParseBison.c" break; case 609: /* stmtList: stmtList stmtBlock */ #line 2385 "VParseBison.y" { } #line 24878 "VParseBison.c" break; case 610: /* stmt: statement_item */ #line 2389 "VParseBison.y" { } #line 24884 "VParseBison.c" break; case 611: /* stmt: id ':' statement_item */ #line 2391 "VParseBison.y" { } #line 24890 "VParseBison.c" break; case 612: /* stmt: ';' */ #line 2393 "VParseBison.y" { } #line 24896 "VParseBison.c" break; case 613: /* statement_item: foperator_assignment ';' */ #line 2398 "VParseBison.y" { } #line 24902 "VParseBison.c" break; case 614: /* statement_item: fexprLvalue '=' class_new ';' */ #line 2403 "VParseBison.y" { } #line 24908 "VParseBison.c" break; case 615: /* statement_item: fexprLvalue '=' dynamic_array_new ';' */ #line 2404 "VParseBison.y" { } #line 24914 "VParseBison.c" break; case 616: /* statement_item: fexprLvalue "<=" delay_or_event_controlE expr ';' */ #line 2407 "VParseBison.y" { } #line 24920 "VParseBison.c" break; case 617: /* statement_item: "assign" expr '=' delay_or_event_controlE expr ';' */ #line 2410 "VParseBison.y" { } #line 24926 "VParseBison.c" break; case 618: /* statement_item: "deassign" variable_lvalue ';' */ #line 2411 "VParseBison.y" { } #line 24932 "VParseBison.c" break; case 619: /* statement_item: "force" expr '=' expr ';' */ #line 2412 "VParseBison.y" { } #line 24938 "VParseBison.c" break; case 620: /* statement_item: "release" variable_lvalue ';' */ #line 2413 "VParseBison.y" { } #line 24944 "VParseBison.c" break; case 621: /* statement_item: unique_priorityE caseStart caseAttrE case_itemListE "endcase" */ #line 2416 "VParseBison.y" { } #line 24950 "VParseBison.c" break; case 622: /* statement_item: unique_priorityE caseStart caseAttrE "matches" case_patternListE "endcase" */ #line 2417 "VParseBison.y" { } #line 24956 "VParseBison.c" break; case 623: /* statement_item: unique_priorityE caseStart caseAttrE "inside" case_insideListE "endcase" */ #line 2418 "VParseBison.y" { } #line 24962 "VParseBison.c" break; case 624: /* statement_item: unique_priorityE "if" '(' expr ')' stmtBlock */ #line 2421 "VParseBison.y" { } #line 24968 "VParseBison.c" break; case 625: /* statement_item: unique_priorityE "if" '(' expr ')' stmtBlock "else" stmtBlock */ #line 2422 "VParseBison.y" { } #line 24974 "VParseBison.c" break; case 626: /* statement_item: finc_or_dec_expression ';' */ #line 2424 "VParseBison.y" { } #line 24980 "VParseBison.c" break; case 627: /* statement_item: "void" "'" '(' function_subroutine_callNoMethod ')' ';' */ #line 2429 "VParseBison.y" { } #line 24986 "VParseBison.c" break; case 628: /* statement_item: "void" "'" '(' expr '.' function_subroutine_callNoMethod ')' ';' */ #line 2430 "VParseBison.y" { } #line 24992 "VParseBison.c" break; case 629: /* statement_item: task_subroutine_callNoMethod ';' */ #line 2433 "VParseBison.y" { } #line 24998 "VParseBison.c" break; case 630: /* statement_item: fexpr '.' array_methodNoRoot ';' */ #line 2434 "VParseBison.y" { } #line 25004 "VParseBison.c" break; case 631: /* statement_item: fexpr '.' task_subroutine_callNoMethod ';' */ #line 2435 "VParseBison.y" { } #line 25010 "VParseBison.c" break; case 632: /* statement_item: fexprScope ';' */ #line 2436 "VParseBison.y" { } #line 25016 "VParseBison.c" break; case 633: /* statement_item: fexpr '.' class_new ';' */ #line 2441 "VParseBison.y" { } #line 25022 "VParseBison.c" break; case 634: /* statement_item: "disable" hierarchical_identifier ';' */ #line 2444 "VParseBison.y" { } #line 25028 "VParseBison.c" break; case 635: /* statement_item: "disable" "fork" ';' */ #line 2445 "VParseBison.y" { } #line 25034 "VParseBison.c" break; case 636: /* statement_item: "->" hierarchical_identifier ';' */ #line 2447 "VParseBison.y" { } #line 25040 "VParseBison.c" break; case 637: /* statement_item: "->>" delay_or_event_controlE hierarchical_identifier ';' */ #line 2448 "VParseBison.y" { } #line 25046 "VParseBison.c" break; case 638: /* statement_item: "forever" stmtBlock */ #line 2450 "VParseBison.y" { } #line 25052 "VParseBison.c" break; case 639: /* statement_item: "repeat" '(' expr ')' stmtBlock */ #line 2451 "VParseBison.y" { } #line 25058 "VParseBison.c" break; case 640: /* statement_item: "while" '(' expr ')' stmtBlock */ #line 2452 "VParseBison.y" { } #line 25064 "VParseBison.c" break; case 641: /* statement_item: "for" '(' for_initialization expr ';' for_stepE ')' stmtBlock */ #line 2455 "VParseBison.y" { } #line 25070 "VParseBison.c" break; case 642: /* statement_item: "for" '(' for_initialization ';' for_stepE ')' stmtBlock */ #line 2457 "VParseBison.y" { } #line 25076 "VParseBison.c" break; case 643: /* statement_item: "do" stmtBlock "while" '(' expr ')' ';' */ #line 2458 "VParseBison.y" { } #line 25082 "VParseBison.c" break; case 644: /* statement_item: "foreach" '(' idClassForeach ')' stmt */ #line 2460 "VParseBison.y" { } #line 25088 "VParseBison.c" break; case 645: /* statement_item: "return" ';' */ #line 2463 "VParseBison.y" { } #line 25094 "VParseBison.c" break; case 646: /* statement_item: "return" expr ';' */ #line 2464 "VParseBison.y" { } #line 25100 "VParseBison.c" break; case 647: /* statement_item: "break" ';' */ #line 2465 "VParseBison.y" { } #line 25106 "VParseBison.c" break; case 648: /* statement_item: "continue" ';' */ #line 2466 "VParseBison.y" { } #line 25112 "VParseBison.c" break; case 649: /* statement_item: par_block */ #line 2468 "VParseBison.y" { } #line 25118 "VParseBison.c" break; case 650: /* statement_item: delay_control stmtBlock */ #line 2470 "VParseBison.y" { } #line 25124 "VParseBison.c" break; case 651: /* statement_item: event_control stmtBlock */ #line 2471 "VParseBison.y" { } #line 25130 "VParseBison.c" break; case 652: /* statement_item: cycle_delay stmtBlock */ #line 2472 "VParseBison.y" { } #line 25136 "VParseBison.c" break; case 653: /* statement_item: seq_block */ #line 2474 "VParseBison.y" { } #line 25142 "VParseBison.c" break; case 654: /* statement_item: "wait" '(' expr ')' stmtBlock */ #line 2477 "VParseBison.y" { } #line 25148 "VParseBison.c" break; case 655: /* statement_item: "wait" "fork" ';' */ #line 2478 "VParseBison.y" { } #line 25154 "VParseBison.c" break; case 656: /* statement_item: "wait_order" '(' hierarchical_identifierList ')' action_block */ #line 2479 "VParseBison.y" { } #line 25160 "VParseBison.c" break; case 657: /* statement_item: procedural_assertion_statement */ #line 2482 "VParseBison.y" { } #line 25166 "VParseBison.c" break; case 658: /* statement_item: fexprLvalue "<=" cycle_delay expr ';' */ #line 2487 "VParseBison.y" { } #line 25172 "VParseBison.c" break; case 659: /* statement_item: randsequence_statement */ #line 2489 "VParseBison.y" { } #line 25178 "VParseBison.c" break; case 660: /* statement_item: "randcase" case_itemList "endcase" */ #line 2492 "VParseBison.y" { } #line 25184 "VParseBison.c" break; case 661: /* statement_item: expect_property_statement */ #line 2494 "VParseBison.y" { } #line 25190 "VParseBison.c" break; case 662: /* statement_item: error ';' */ #line 2496 "VParseBison.y" { } #line 25196 "VParseBison.c" break; case 663: /* operator_assignment: exprLvalue '=' delay_or_event_controlE expr */ #line 2500 "VParseBison.y" { } #line 25202 "VParseBison.c" break; case 664: /* operator_assignment: exprLvalue "+=" expr */ #line 2501 "VParseBison.y" { } #line 25208 "VParseBison.c" break; case 665: /* operator_assignment: exprLvalue "-=" expr */ #line 2502 "VParseBison.y" { } #line 25214 "VParseBison.c" break; case 666: /* operator_assignment: exprLvalue "*=" expr */ #line 2503 "VParseBison.y" { } #line 25220 "VParseBison.c" break; case 667: /* operator_assignment: exprLvalue "/=" expr */ #line 2504 "VParseBison.y" { } #line 25226 "VParseBison.c" break; case 668: /* operator_assignment: exprLvalue "%=" expr */ #line 2505 "VParseBison.y" { } #line 25232 "VParseBison.c" break; case 669: /* operator_assignment: exprLvalue "&=" expr */ #line 2506 "VParseBison.y" { } #line 25238 "VParseBison.c" break; case 670: /* operator_assignment: exprLvalue "|=" expr */ #line 2507 "VParseBison.y" { } #line 25244 "VParseBison.c" break; case 671: /* operator_assignment: exprLvalue "^=" expr */ #line 2508 "VParseBison.y" { } #line 25250 "VParseBison.c" break; case 672: /* operator_assignment: exprLvalue "<<=" expr */ #line 2509 "VParseBison.y" { } #line 25256 "VParseBison.c" break; case 673: /* operator_assignment: exprLvalue ">>=" expr */ #line 2510 "VParseBison.y" { } #line 25262 "VParseBison.c" break; case 674: /* operator_assignment: exprLvalue ">>>=" expr */ #line 2511 "VParseBison.y" { } #line 25268 "VParseBison.c" break; case 675: /* foperator_assignment: fexprLvalue '=' delay_or_event_controlE expr */ #line 2515 "VParseBison.y" { } #line 25274 "VParseBison.c" break; case 676: /* foperator_assignment: fexprLvalue "+=" expr */ #line 2515 "VParseBison.y" { } #line 25280 "VParseBison.c" break; case 677: /* foperator_assignment: fexprLvalue "-=" expr */ #line 2515 "VParseBison.y" { } #line 25286 "VParseBison.c" break; case 678: /* foperator_assignment: fexprLvalue "*=" expr */ #line 2515 "VParseBison.y" { } #line 25292 "VParseBison.c" break; case 679: /* foperator_assignment: fexprLvalue "/=" expr */ #line 2515 "VParseBison.y" { } #line 25298 "VParseBison.c" break; case 680: /* foperator_assignment: fexprLvalue "%=" expr */ #line 2515 "VParseBison.y" { } #line 25304 "VParseBison.c" break; case 681: /* foperator_assignment: fexprLvalue "&=" expr */ #line 2515 "VParseBison.y" { } #line 25310 "VParseBison.c" break; case 682: /* foperator_assignment: fexprLvalue "|=" expr */ #line 2515 "VParseBison.y" { } #line 25316 "VParseBison.c" break; case 683: /* foperator_assignment: fexprLvalue "^=" expr */ #line 2515 "VParseBison.y" { } #line 25322 "VParseBison.c" break; case 684: /* foperator_assignment: fexprLvalue "<<=" expr */ #line 2515 "VParseBison.y" { } #line 25328 "VParseBison.c" break; case 685: /* foperator_assignment: fexprLvalue ">>=" expr */ #line 2515 "VParseBison.y" { } #line 25334 "VParseBison.c" break; case 686: /* foperator_assignment: fexprLvalue ">>>=" expr */ #line 2515 "VParseBison.y" { } #line 25340 "VParseBison.c" break; case 687: /* inc_or_dec_expression: exprScope "++" */ #line 2520 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 25346 "VParseBison.c" break; case 688: /* inc_or_dec_expression: exprScope "--" */ #line 2521 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 25352 "VParseBison.c" break; case 689: /* inc_or_dec_expression: "++" expr */ #line 2523 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 25358 "VParseBison.c" break; case 690: /* inc_or_dec_expression: "--" expr */ #line 2524 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 25364 "VParseBison.c" break; case 691: /* finc_or_dec_expression: fexprScope "++" */ #line 2528 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 25370 "VParseBison.c" break; case 692: /* finc_or_dec_expression: fexprScope "--" */ #line 2528 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 25376 "VParseBison.c" break; case 693: /* finc_or_dec_expression: "++" expr */ #line 2528 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 25382 "VParseBison.c" break; case 694: /* finc_or_dec_expression: "--" expr */ #line 2528 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 25388 "VParseBison.c" break; case 695: /* sinc_or_dec_expression: sexprScope "++" */ #line 2532 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 25394 "VParseBison.c" break; case 696: /* sinc_or_dec_expression: sexprScope "--" */ #line 2532 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 25400 "VParseBison.c" break; case 697: /* sinc_or_dec_expression: "++" expr */ #line 2532 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 25406 "VParseBison.c" break; case 698: /* sinc_or_dec_expression: "--" expr */ #line 2532 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 25412 "VParseBison.c" break; case 699: /* pinc_or_dec_expression: pexprScope "++" */ #line 2536 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 25418 "VParseBison.c" break; case 700: /* pinc_or_dec_expression: pexprScope "--" */ #line 2536 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 25424 "VParseBison.c" break; case 701: /* pinc_or_dec_expression: "++" expr */ #line 2536 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 25430 "VParseBison.c" break; case 702: /* pinc_or_dec_expression: "--" expr */ #line 2536 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 25436 "VParseBison.c" break; case 703: /* ev_inc_or_dec_expression: ev_exprScope "++" */ #line 2540 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 25442 "VParseBison.c" break; case 704: /* ev_inc_or_dec_expression: ev_exprScope "--" */ #line 2540 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 25448 "VParseBison.c" break; case 705: /* ev_inc_or_dec_expression: "++" expr */ #line 2540 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 25454 "VParseBison.c" break; case 706: /* ev_inc_or_dec_expression: "--" expr */ #line 2540 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 25460 "VParseBison.c" break; case 707: /* pev_inc_or_dec_expression: pev_exprScope "++" */ #line 2544 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 25466 "VParseBison.c" break; case 708: /* pev_inc_or_dec_expression: pev_exprScope "--" */ #line 2544 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 25472 "VParseBison.c" break; case 709: /* pev_inc_or_dec_expression: "++" expr */ #line 2544 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 25478 "VParseBison.c" break; case 710: /* pev_inc_or_dec_expression: "--" expr */ #line 2544 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 25484 "VParseBison.c" break; case 711: /* class_new: "new" */ #line 2549 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 25490 "VParseBison.c" break; case 712: /* class_new: "new" expr */ #line 2550 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+" "+(yyvsp[0].str); } #line 25496 "VParseBison.c" break; case 713: /* class_new: "new-then-paren" '(' list_of_argumentsE ')' */ #line 2552 "VParseBison.y" { (yyval.fl)=(yyvsp[-3].fl); (yyval.str) = (yyvsp[-3].str)+"("+(yyvsp[-1].str)+")"; } #line 25502 "VParseBison.c" break; case 714: /* dynamic_array_new: "new" '[' expr ']' */ #line 2556 "VParseBison.y" { (yyval.fl)=(yyvsp[-3].fl); (yyval.str)=(yyvsp[-3].str)+"["+(yyvsp[-1].str)+"]"; } #line 25508 "VParseBison.c" break; case 715: /* dynamic_array_new: "new" '[' expr ']' '(' expr ')' */ #line 2557 "VParseBison.y" { (yyval.fl)=(yyvsp[-6].fl); (yyval.str)=(yyvsp[-6].str)+"["+(yyvsp[-4].str)+"]("+(yyvsp[-1].str)+")"; } #line 25514 "VParseBison.c" break; case 716: /* unique_priorityE: %empty */ #line 2564 "VParseBison.y" { } #line 25520 "VParseBison.c" break; case 717: /* unique_priorityE: "priority" */ #line 2565 "VParseBison.y" { } #line 25526 "VParseBison.c" break; case 718: /* unique_priorityE: "unique" */ #line 2566 "VParseBison.y" { } #line 25532 "VParseBison.c" break; case 719: /* unique_priorityE: "unique0" */ #line 2567 "VParseBison.y" { NEED_S09((yyvsp[0].fl), "unique0"); } #line 25538 "VParseBison.c" break; case 720: /* action_block: stmt */ #line 2571 "VParseBison.y" { } #line 25544 "VParseBison.c" break; case 721: /* action_block: stmt "else" stmt */ #line 2572 "VParseBison.y" { } #line 25550 "VParseBison.c" break; case 722: /* action_block: "else" stmt */ #line 2573 "VParseBison.y" { } #line 25556 "VParseBison.c" break; case 723: /* caseStart: "case" '(' expr ')' */ #line 2577 "VParseBison.y" { } #line 25562 "VParseBison.c" break; case 724: /* caseStart: "casex" '(' expr ')' */ #line 2578 "VParseBison.y" { } #line 25568 "VParseBison.c" break; case 725: /* caseStart: "casez" '(' expr ')' */ #line 2579 "VParseBison.y" { } #line 25574 "VParseBison.c" break; case 726: /* caseAttrE: %empty */ #line 2583 "VParseBison.y" { } #line 25580 "VParseBison.c" break; case 727: /* case_patternListE: case_itemListE */ #line 2588 "VParseBison.y" { } #line 25586 "VParseBison.c" break; case 728: /* case_itemListE: %empty */ #line 2592 "VParseBison.y" { } #line 25592 "VParseBison.c" break; case 729: /* case_itemListE: case_itemList */ #line 2593 "VParseBison.y" { } #line 25598 "VParseBison.c" break; case 730: /* case_insideListE: %empty */ #line 2597 "VParseBison.y" { } #line 25604 "VParseBison.c" break; case 731: /* case_insideListE: case_inside_itemList */ #line 2598 "VParseBison.y" { } #line 25610 "VParseBison.c" break; case 732: /* case_itemList: caseCondList ':' stmtBlock */ #line 2602 "VParseBison.y" { } #line 25616 "VParseBison.c" break; case 733: /* case_itemList: "default" ':' stmtBlock */ #line 2603 "VParseBison.y" { } #line 25622 "VParseBison.c" break; case 734: /* case_itemList: "default" stmtBlock */ #line 2604 "VParseBison.y" { } #line 25628 "VParseBison.c" break; case 735: /* case_itemList: case_itemList caseCondList ':' stmtBlock */ #line 2605 "VParseBison.y" { } #line 25634 "VParseBison.c" break; case 736: /* case_itemList: case_itemList "default" stmtBlock */ #line 2606 "VParseBison.y" { } #line 25640 "VParseBison.c" break; case 737: /* case_itemList: case_itemList "default" ':' stmtBlock */ #line 2607 "VParseBison.y" { } #line 25646 "VParseBison.c" break; case 738: /* case_inside_itemList: open_range_list ':' stmtBlock */ #line 2611 "VParseBison.y" { } #line 25652 "VParseBison.c" break; case 739: /* case_inside_itemList: "default" ':' stmtBlock */ #line 2612 "VParseBison.y" { } #line 25658 "VParseBison.c" break; case 740: /* case_inside_itemList: "default" stmtBlock */ #line 2613 "VParseBison.y" { } #line 25664 "VParseBison.c" break; case 741: /* case_inside_itemList: case_inside_itemList open_range_list ':' stmtBlock */ #line 2614 "VParseBison.y" { } #line 25670 "VParseBison.c" break; case 742: /* case_inside_itemList: case_inside_itemList "default" stmtBlock */ #line 2615 "VParseBison.y" { } #line 25676 "VParseBison.c" break; case 743: /* case_inside_itemList: case_inside_itemList "default" ':' stmtBlock */ #line 2616 "VParseBison.y" { } #line 25682 "VParseBison.c" break; case 744: /* open_range_list: open_value_range */ #line 2620 "VParseBison.y" { } #line 25688 "VParseBison.c" break; case 745: /* open_range_list: open_range_list ',' open_value_range */ #line 2621 "VParseBison.y" { } #line 25694 "VParseBison.c" break; case 746: /* open_value_range: value_range */ #line 2625 "VParseBison.y" { } #line 25700 "VParseBison.c" break; case 747: /* value_range: expr */ #line 2629 "VParseBison.y" { } #line 25706 "VParseBison.c" break; case 748: /* value_range: '[' expr ':' expr ']' */ #line 2630 "VParseBison.y" { } #line 25712 "VParseBison.c" break; case 749: /* covergroup_value_range: cgexpr */ #line 2634 "VParseBison.y" { } #line 25718 "VParseBison.c" break; case 750: /* covergroup_value_range: '[' cgexpr ':' cgexpr ']' */ #line 2635 "VParseBison.y" { } #line 25724 "VParseBison.c" break; case 751: /* caseCondList: expr */ #line 2639 "VParseBison.y" { } #line 25730 "VParseBison.c" break; case 752: /* caseCondList: caseCondList ',' expr */ #line 2640 "VParseBison.y" { } #line 25736 "VParseBison.c" break; case 753: /* patternNoExpr: '.' id */ #line 2644 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str)="."+(yyvsp[0].str); } #line 25742 "VParseBison.c" break; case 754: /* patternNoExpr: ".*" */ #line 2645 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=".*"; } #line 25748 "VParseBison.c" break; case 755: /* patternNoExpr: "tagged" id patternNoExpr */ #line 2648 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str)=" tagged "+(yyvsp[-1].str)+" "+(yyvsp[0].str); } #line 25754 "VParseBison.c" break; case 756: /* patternList: patternOne */ #line 2653 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 25760 "VParseBison.c" break; case 757: /* patternList: patternList ',' patternOne */ #line 2654 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str)=(yyvsp[-2].str)+","+(yyvsp[0].str); } #line 25766 "VParseBison.c" break; case 758: /* patternOne: expr */ #line 2658 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 25772 "VParseBison.c" break; case 759: /* patternOne: expr '{' argsExprList '}' */ #line 2659 "VParseBison.y" { (yyval.fl)=(yyvsp[-3].fl); (yyval.str)=(yyvsp[-3].str); } #line 25778 "VParseBison.c" break; case 760: /* patternOne: patternNoExpr */ #line 2660 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 25784 "VParseBison.c" break; case 761: /* patternMemberList: patternKey ':' expr */ #line 2664 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str)=(yyvsp[-2].str)+" : "+(yyvsp[-1].str); } #line 25790 "VParseBison.c" break; case 762: /* patternMemberList: patternKey ':' patternNoExpr */ #line 2665 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str)=(yyvsp[-2].str)+" : "+(yyvsp[-1].str); } #line 25796 "VParseBison.c" break; case 763: /* patternMemberList: patternMemberList ',' patternKey ':' expr */ #line 2666 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str)=(yyvsp[-4].str)+","+(yyvsp[-2].str)+":"+(yyvsp[-1].str); } #line 25802 "VParseBison.c" break; case 764: /* patternMemberList: patternMemberList ',' patternKey ':' patternNoExpr */ #line 2667 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str)=(yyvsp[-4].str)+","+(yyvsp[-2].str)+":"+(yyvsp[-1].str); } #line 25808 "VParseBison.c" break; case 765: /* patternKey: constExpr */ #line 2673 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 25814 "VParseBison.c" break; case 766: /* patternKey: "default" */ #line 2675 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 25820 "VParseBison.c" break; case 767: /* patternKey: simple_type */ #line 2676 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 25826 "VParseBison.c" break; case 768: /* assignment_pattern: "'{" patternList '}' */ #line 2687 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str)="'{"+(yyvsp[-1].str)+"}"; } #line 25832 "VParseBison.c" break; case 769: /* assignment_pattern: "'{" patternMemberList '}' */ #line 2691 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str)="'{"+(yyvsp[-1].str)+"}"; } #line 25838 "VParseBison.c" break; case 770: /* assignment_pattern: "'{" '}' */ #line 2693 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str)="'{}"; } #line 25844 "VParseBison.c" break; case 771: /* for_initialization: for_initializationItemList ';' */ #line 2699 "VParseBison.y" { } #line 25850 "VParseBison.c" break; case 772: /* for_initialization: ';' */ #line 2701 "VParseBison.y" { } #line 25856 "VParseBison.c" break; case 773: /* for_initializationItemList: for_initializationItem */ #line 2705 "VParseBison.y" { } #line 25862 "VParseBison.c" break; case 774: /* for_initializationItemList: for_initializationItemList ',' for_initializationItem */ #line 2706 "VParseBison.y" { } #line 25868 "VParseBison.c" break; case 775: /* for_initializationItem: data_type idAny '=' expr */ #line 2711 "VParseBison.y" { VARDTYPE((yyvsp[-3].str)); } #line 25874 "VParseBison.c" break; case 776: /* for_initializationItem: "var" data_type idAny '=' expr */ #line 2713 "VParseBison.y" { VARDTYPE((yyvsp[-4].str)); } #line 25880 "VParseBison.c" break; case 777: /* for_initializationItem: variable_lvalue '=' expr */ #line 2715 "VParseBison.y" { } #line 25886 "VParseBison.c" break; case 778: /* for_stepE: %empty */ #line 2719 "VParseBison.y" { } #line 25892 "VParseBison.c" break; case 779: /* for_stepE: for_step */ #line 2720 "VParseBison.y" { } #line 25898 "VParseBison.c" break; case 780: /* for_step: for_step_assignment */ #line 2724 "VParseBison.y" { } #line 25904 "VParseBison.c" break; case 781: /* for_step: for_step ',' for_step_assignment */ #line 2725 "VParseBison.y" { } #line 25910 "VParseBison.c" break; case 782: /* for_step_assignment: operator_assignment */ #line 2729 "VParseBison.y" { } #line 25916 "VParseBison.c" break; case 783: /* for_step_assignment: inc_or_dec_expression */ #line 2731 "VParseBison.y" { } #line 25922 "VParseBison.c" break; case 784: /* for_step_assignment: function_subroutine_callNoMethod */ #line 2733 "VParseBison.y" { } #line 25928 "VParseBison.c" break; case 785: /* for_step_assignment: expr '.' array_methodNoRoot */ #line 2735 "VParseBison.y" { } #line 25934 "VParseBison.c" break; case 786: /* for_step_assignment: exprScope */ #line 2736 "VParseBison.y" { } #line 25940 "VParseBison.c" break; case 787: /* loop_variables: id */ #line 2740 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 25946 "VParseBison.c" break; case 788: /* loop_variables: loop_variables ',' id */ #line 2741 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str)=(yyvsp[-2].str)+","+(yyvsp[0].str); } #line 25952 "VParseBison.c" break; case 789: /* funcRef: id '(' pev_list_of_argumentsE ')' */ #line 2757 "VParseBison.y" { (yyval.fl)=(yyvsp[-3].fl); (yyval.str)=(yyvsp[-3].str)+"("+(yyvsp[-1].str)+")"; } #line 25958 "VParseBison.c" break; case 790: /* funcRef: package_scopeIdFollows id '(' pev_list_of_argumentsE ')' */ #line 2758 "VParseBison.y" { (yyval.fl)=(yyvsp[-3].fl); (yyval.str)=(yyvsp[-4].str)+(yyvsp[-3].str)+"("+(yyvsp[-1].str)+")"; } #line 25964 "VParseBison.c" break; case 791: /* funcRef: class_scope_id '(' pev_list_of_argumentsE ')' */ #line 2759 "VParseBison.y" { (yyval.fl)=(yyvsp[-3].fl); (yyval.str)=(yyvsp[-3].str)+"("+(yyvsp[-1].str)+")"; } #line 25970 "VParseBison.c" break; case 792: /* task_subroutine_callNoMethod: funcRef */ #line 2764 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 25976 "VParseBison.c" break; case 793: /* task_subroutine_callNoMethod: funcRef "with-then-(" '(' expr ')' */ #line 2765 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str)=(yyvsp[-4].str)+" "+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 25982 "VParseBison.c" break; case 794: /* task_subroutine_callNoMethod: system_t_call */ #line 2766 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 25988 "VParseBison.c" break; case 795: /* task_subroutine_callNoMethod: funcRef "with-then-{" constraint_block */ #line 2772 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str)=(yyvsp[-2].str)+" with..."; } #line 25994 "VParseBison.c" break; case 796: /* function_subroutine_callNoMethod: funcRef */ #line 2777 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 26000 "VParseBison.c" break; case 797: /* function_subroutine_callNoMethod: funcRef "with-then-(" '(' expr ')' */ #line 2778 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str)=(yyvsp[-4].str)+" "+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 26006 "VParseBison.c" break; case 798: /* function_subroutine_callNoMethod: system_f_call */ #line 2779 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 26012 "VParseBison.c" break; case 799: /* function_subroutine_callNoMethod: funcRef "with-then-{" constraint_block */ #line 2785 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str)=(yyvsp[-2].str)+" with..."; } #line 26018 "VParseBison.c" break; case 800: /* system_t_call: system_f_call */ #line 2789 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 26024 "VParseBison.c" break; case 801: /* system_f_call: "SYSCALL" parenE */ #line 2793 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str); } #line 26030 "VParseBison.c" break; case 802: /* system_f_call: "SYSCALL" '(' exprOrDataTypeList ')' */ #line 2795 "VParseBison.y" { (yyval.fl)=(yyvsp[-3].fl); (yyval.str) = (yyvsp[-3].str)+"("+(yyvsp[-1].str)+")"; } #line 26036 "VParseBison.c" break; case 803: /* system_f_call: "$fatal" parenE */ #line 2798 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str); } #line 26042 "VParseBison.c" break; case 804: /* system_f_call: "$fatal" '(' exprOrDataTypeList ')' */ #line 2799 "VParseBison.y" { (yyval.fl)=(yyvsp[-3].fl); (yyval.str) = (yyvsp[-3].str)+"("+(yyvsp[-1].str)+")"; } #line 26048 "VParseBison.c" break; case 805: /* system_f_call: "$error" parenE */ #line 2800 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str); } #line 26054 "VParseBison.c" break; case 806: /* system_f_call: "$error" '(' exprOrDataTypeList ')' */ #line 2801 "VParseBison.y" { (yyval.fl)=(yyvsp[-3].fl); (yyval.str) = (yyvsp[-3].str)+"("+(yyvsp[-1].str)+")"; } #line 26060 "VParseBison.c" break; case 807: /* system_f_call: "$warning" parenE */ #line 2802 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str); } #line 26066 "VParseBison.c" break; case 808: /* system_f_call: "$warning" '(' exprOrDataTypeList ')' */ #line 2803 "VParseBison.y" { (yyval.fl)=(yyvsp[-3].fl); (yyval.str) = (yyvsp[-3].str)+"("+(yyvsp[-1].str)+")"; } #line 26072 "VParseBison.c" break; case 809: /* system_f_call: "$info" parenE */ #line 2804 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str); } #line 26078 "VParseBison.c" break; case 810: /* system_f_call: "$info" '(' exprOrDataTypeList ')' */ #line 2805 "VParseBison.y" { (yyval.fl)=(yyvsp[-3].fl); (yyval.str) = (yyvsp[-3].str)+"("+(yyvsp[-1].str)+")"; } #line 26084 "VParseBison.c" break; case 811: /* elaboration_system_task: "$fatal" parenE ';' */ #line 2810 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str); NEED_S09((yyvsp[-2].fl),"elaboration system tasks"); } #line 26090 "VParseBison.c" break; case 812: /* elaboration_system_task: "$fatal" '(' exprOrDataTypeList ')' ';' */ #line 2811 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = (yyvsp[-4].str)+"("+(yyvsp[-2].str)+")"; NEED_S09((yyvsp[-4].fl),"elaboration system tasks"); } #line 26096 "VParseBison.c" break; case 813: /* elaboration_system_task: "$error" parenE ';' */ #line 2812 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str); NEED_S09((yyvsp[-2].fl),"elaboration system tasks"); } #line 26102 "VParseBison.c" break; case 814: /* elaboration_system_task: "$error" '(' exprOrDataTypeList ')' ';' */ #line 2813 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = (yyvsp[-4].str)+"("+(yyvsp[-2].str)+")"; NEED_S09((yyvsp[-4].fl),"elaboration system tasks"); } #line 26108 "VParseBison.c" break; case 815: /* elaboration_system_task: "$warning" parenE ';' */ #line 2814 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str); NEED_S09((yyvsp[-2].fl),"elaboration system tasks"); } #line 26114 "VParseBison.c" break; case 816: /* elaboration_system_task: "$warning" '(' exprOrDataTypeList ')' ';' */ #line 2815 "VParseBison.y" {(yyval.fl)=(yyvsp[-4].fl); (yyval.str) = (yyvsp[-4].str)+"("+(yyvsp[-2].str)+")"; NEED_S09((yyvsp[-4].fl),"elaboration system tasks"); } #line 26120 "VParseBison.c" break; case 817: /* elaboration_system_task: "$info" parenE ';' */ #line 2816 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str); NEED_S09((yyvsp[-2].fl),"elaboration system tasks"); } #line 26126 "VParseBison.c" break; case 818: /* elaboration_system_task: "$info" '(' exprOrDataTypeList ')' ';' */ #line 2817 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = (yyvsp[-4].str)+"("+(yyvsp[-2].str)+")"; NEED_S09((yyvsp[-4].fl),"elaboration system tasks"); } #line 26132 "VParseBison.c" break; case 819: /* property_actual_arg: pev_expr */ #line 2823 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 26138 "VParseBison.c" break; case 820: /* task: "task" */ #line 2829 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); } #line 26144 "VParseBison.c" break; case 821: /* task: "task-is-pure-virtual" */ #line 2830 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); } #line 26150 "VParseBison.c" break; case 822: /* task_declaration: "task" lifetimeE taskId tfGuts "endtask" endLabelE */ #line 2835 "VParseBison.y" { PARSEP->endtaskfuncCb((yyvsp[-1].fl),(yyvsp[-1].str)); PARSEP->symPopScope(VAstType::TASK); } #line 26157 "VParseBison.c" break; case 823: /* task_declaration: "task-is-pure-virtual" lifetimeE taskId tfGutsPureV */ #line 2838 "VParseBison.y" { PARSEP->endtaskfuncCb((yyvsp[-3].fl),"endtask"); PARSEP->symPopScope(VAstType::TASK); } #line 26164 "VParseBison.c" break; case 824: /* task_prototype: task taskId '(' tf_port_listE ')' */ #line 2845 "VParseBison.y" { PARSEP->symPopScope(VAstType::TASK); PARSEP->endtaskfuncCb((yyvsp[-4].fl),"endtask"); } #line 26170 "VParseBison.c" break; case 825: /* task_prototype: task taskId */ #line 2846 "VParseBison.y" { PARSEP->symPopScope(VAstType::TASK); PARSEP->endtaskfuncCb((yyvsp[-1].fl),"endtask"); } #line 26176 "VParseBison.c" break; case 826: /* function: "function" */ #line 2850 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); } #line 26182 "VParseBison.c" break; case 827: /* function: "function-is-pure-virtual" */ #line 2851 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); } #line 26188 "VParseBison.c" break; case 828: /* function_declaration: "function" lifetimeE funcId tfGuts "endfunction" endLabelE */ #line 2856 "VParseBison.y" { PARSEP->endtaskfuncCb((yyvsp[-1].fl),(yyvsp[-1].str)); PARSEP->symPopScope(VAstType::FUNCTION); } #line 26195 "VParseBison.c" break; case 829: /* function_declaration: "function" lifetimeE funcIdNew tfGuts "endfunction" endLabelE */ #line 2859 "VParseBison.y" { PARSEP->endtaskfuncCb((yyvsp[-1].fl),(yyvsp[-1].str)); PARSEP->symPopScope(VAstType::FUNCTION); } #line 26202 "VParseBison.c" break; case 830: /* function_declaration: "function-is-pure-virtual" lifetimeE funcId tfGutsPureV */ #line 2862 "VParseBison.y" { PARSEP->endtaskfuncCb((yyvsp[-3].fl),"endfunction"); PARSEP->symPopScope(VAstType::FUNCTION); } #line 26209 "VParseBison.c" break; case 831: /* function_declaration: "function-is-pure-virtual" lifetimeE funcIdNew tfGutsPureV */ #line 2865 "VParseBison.y" { PARSEP->endtaskfuncCb((yyvsp[-3].fl),"endfunction"); PARSEP->symPopScope(VAstType::FUNCTION); } #line 26216 "VParseBison.c" break; case 832: /* function_prototype: function funcId '(' tf_port_listE ')' */ #line 2872 "VParseBison.y" { PARSEP->symPopScope(VAstType::FUNCTION); PARSEP->endtaskfuncCb((yyvsp[-4].fl),"endfunction"); } #line 26222 "VParseBison.c" break; case 833: /* function_prototype: function funcId */ #line 2873 "VParseBison.y" { PARSEP->symPopScope(VAstType::FUNCTION); PARSEP->endtaskfuncCb((yyvsp[-1].fl),"endfunction"); } #line 26228 "VParseBison.c" break; case 834: /* class_constructor_prototype: function funcIdNew '(' tf_port_listE ')' ';' */ #line 2877 "VParseBison.y" { PARSEP->symPopScope(VAstType::FUNCTION); PARSEP->endtaskfuncCb((yyvsp[-5].fl),"endfunction"); } #line 26234 "VParseBison.c" break; case 835: /* class_constructor_prototype: function funcIdNew ';' */ #line 2878 "VParseBison.y" { PARSEP->symPopScope(VAstType::FUNCTION); PARSEP->endtaskfuncCb((yyvsp[-2].fl),"endfunction"); } #line 26240 "VParseBison.c" break; case 836: /* method_prototype: task_prototype */ #line 2882 "VParseBison.y" { } #line 26246 "VParseBison.c" break; case 837: /* method_prototype: function_prototype */ #line 2883 "VParseBison.y" { } #line 26252 "VParseBison.c" break; case 838: /* lifetimeE: %empty */ #line 2887 "VParseBison.y" { } #line 26258 "VParseBison.c" break; case 839: /* lifetimeE: lifetime */ #line 2888 "VParseBison.y" { } #line 26264 "VParseBison.c" break; case 840: /* lifetime: "static" */ #line 2893 "VParseBison.y" { } #line 26270 "VParseBison.c" break; case 841: /* lifetime: "automatic" */ #line 2894 "VParseBison.y" { } #line 26276 "VParseBison.c" break; case 842: /* taskId: tfIdScoped */ #line 2899 "VParseBison.y" { PARSEP->symPushNewUnder(VAstType::TASK, (yyvsp[0].str), (yyvsp[0].scp)); PARSEP->taskCb((yyvsp[0].fl),"task",(yyvsp[0].str)); } #line 26283 "VParseBison.c" break; case 843: /* funcId: tfIdScoped */ #line 2907 "VParseBison.y" { PARSEP->symPushNewUnder(VAstType::FUNCTION, (yyvsp[0].str), (yyvsp[0].scp)); PARSEP->functionCb((yyvsp[0].fl),"function",(yyvsp[0].str),""); } #line 26290 "VParseBison.c" break; case 844: /* funcId: signingE rangeList tfIdScoped */ #line 2910 "VParseBison.y" { PARSEP->symPushNewUnder(VAstType::FUNCTION, (yyvsp[0].str), (yyvsp[0].scp)); PARSEP->functionCb((yyvsp[0].fl),"function",(yyvsp[0].str),SPACED((yyvsp[-2].str),(yyvsp[-1].str))); } #line 26297 "VParseBison.c" break; case 845: /* funcId: signing tfIdScoped */ #line 2913 "VParseBison.y" { PARSEP->symPushNewUnder(VAstType::FUNCTION, (yyvsp[0].str), (yyvsp[0].scp)); PARSEP->functionCb((yyvsp[0].fl),"function",(yyvsp[0].str),(yyvsp[-1].str)); } #line 26304 "VParseBison.c" break; case 846: /* funcId: "void" tfIdScoped */ #line 2916 "VParseBison.y" { PARSEP->symPushNewUnder(VAstType::FUNCTION, (yyvsp[0].str), (yyvsp[0].scp)); PARSEP->functionCb((yyvsp[0].fl),"function",(yyvsp[0].str),(yyvsp[-1].str)); } #line 26311 "VParseBison.c" break; case 847: /* funcId: data_type tfIdScoped */ #line 2919 "VParseBison.y" { PARSEP->symPushNewUnder(VAstType::FUNCTION, (yyvsp[0].str), (yyvsp[0].scp)); PARSEP->functionCb((yyvsp[0].fl),"function",(yyvsp[0].str),(yyvsp[-1].str)); } #line 26318 "VParseBison.c" break; case 848: /* funcIdNew: "new" */ #line 2925 "VParseBison.y" { PARSEP->symPushNewUnder(VAstType::FUNCTION, "new", NULL); PARSEP->functionCb((yyvsp[0].fl),"function","new",""); } #line 26325 "VParseBison.c" break; case 849: /* funcIdNew: "new-then-paren" */ #line 2928 "VParseBison.y" { PARSEP->symPushNewUnder(VAstType::FUNCTION, "new", NULL); PARSEP->functionCb((yyvsp[0].fl),"function","new",""); } #line 26332 "VParseBison.c" break; case 850: /* funcIdNew: class_scopeWithoutId "new-then-paren" */ #line 2931 "VParseBison.y" { PARSEP->symPushNewUnder(VAstType::FUNCTION, "new", (yyvsp[-1].scp)); PARSEP->functionCb((yyvsp[0].fl),"function","new",""); } #line 26339 "VParseBison.c" break; case 851: /* tfIdScoped: id */ #line 2937 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.scp)=NULL; (yyval.str) = (yyvsp[0].str); } #line 26345 "VParseBison.c" break; case 852: /* tfIdScoped: id '.' id */ #line 2938 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.scp)=NULL; (yyval.str) = (yyvsp[-2].str)+"."+(yyvsp[-1].str); } #line 26351 "VParseBison.c" break; case 853: /* tfIdScoped: class_scope_id */ #line 2939 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.scp)=(yyvsp[0].scp); (yyval.str) = (yyvsp[0].str); } #line 26357 "VParseBison.c" break; case 854: /* tfGuts: '(' tf_port_listE ')' ';' tfBodyE */ #line 2943 "VParseBison.y" { } #line 26363 "VParseBison.c" break; case 855: /* tfGuts: ';' tfBodyE */ #line 2944 "VParseBison.y" { } #line 26369 "VParseBison.c" break; case 856: /* tfGutsPureV: '(' tf_port_listE ')' ';' */ #line 2948 "VParseBison.y" { } #line 26375 "VParseBison.c" break; case 857: /* tfGutsPureV: ';' */ #line 2949 "VParseBison.y" { } #line 26381 "VParseBison.c" break; case 858: /* tfBodyE: %empty */ #line 2953 "VParseBison.y" { } #line 26387 "VParseBison.c" break; case 859: /* tfBodyE: tf_item_declarationList */ #line 2954 "VParseBison.y" { } #line 26393 "VParseBison.c" break; case 860: /* tfBodyE: tf_item_declarationList stmtList */ #line 2955 "VParseBison.y" { } #line 26399 "VParseBison.c" break; case 861: /* tfBodyE: stmtList */ #line 2956 "VParseBison.y" { } #line 26405 "VParseBison.c" break; case 862: /* function_data_type: "void" */ #line 2960 "VParseBison.y" { (yyval.str) = (yyvsp[0].str); } #line 26411 "VParseBison.c" break; case 863: /* function_data_type: data_type */ #line 2961 "VParseBison.y" { (yyval.str) = (yyvsp[0].str); } #line 26417 "VParseBison.c" break; case 864: /* tf_item_declarationList: tf_item_declaration */ #line 2965 "VParseBison.y" { } #line 26423 "VParseBison.c" break; case 865: /* tf_item_declarationList: tf_item_declarationList tf_item_declaration */ #line 2966 "VParseBison.y" { } #line 26429 "VParseBison.c" break; case 866: /* tf_item_declaration: block_item_declaration */ #line 2970 "VParseBison.y" { } #line 26435 "VParseBison.c" break; case 867: /* tf_item_declaration: tf_port_declaration */ #line 2971 "VParseBison.y" { } #line 26441 "VParseBison.c" break; case 868: /* $@19: %empty */ #line 2976 "VParseBison.y" { VARRESET_LIST(""); VARIO("input"); } #line 26447 "VParseBison.c" break; case 869: /* tf_port_listE: $@19 tf_port_listList */ #line 2977 "VParseBison.y" { VARRESET_NONLIST(""); } #line 26453 "VParseBison.c" break; case 870: /* tf_port_listList: tf_port_item */ #line 2981 "VParseBison.y" { } #line 26459 "VParseBison.c" break; case 871: /* tf_port_listList: tf_port_listList ',' tf_port_item */ #line 2982 "VParseBison.y" { } #line 26465 "VParseBison.c" break; case 872: /* tf_port_item: %empty */ #line 2987 "VParseBison.y" { PINNUMINC(); } #line 26471 "VParseBison.c" break; case 873: /* tf_port_item: tf_port_itemFront tf_port_itemAssignment */ #line 2988 "VParseBison.y" { PINNUMINC(); } #line 26477 "VParseBison.c" break; case 874: /* tf_port_item: tf_port_itemAssignment */ #line 2989 "VParseBison.y" { PINNUMINC(); } #line 26483 "VParseBison.c" break; case 875: /* tf_port_itemFront: data_type */ #line 2993 "VParseBison.y" { VARDTYPE((yyvsp[0].str)); } #line 26489 "VParseBison.c" break; case 876: /* tf_port_itemFront: signingE rangeList */ #line 2994 "VParseBison.y" { VARDTYPE(SPACED((yyvsp[-1].str),(yyvsp[0].str))); } #line 26495 "VParseBison.c" break; case 877: /* tf_port_itemFront: signing */ #line 2995 "VParseBison.y" { VARDTYPE((yyvsp[0].str)); } #line 26501 "VParseBison.c" break; case 878: /* tf_port_itemFront: "var" data_type */ #line 2996 "VParseBison.y" { VARDTYPE((yyvsp[0].str)); } #line 26507 "VParseBison.c" break; case 879: /* tf_port_itemFront: "var" implicit_typeE */ #line 2997 "VParseBison.y" { VARDTYPE((yyvsp[0].str)); } #line 26513 "VParseBison.c" break; case 880: /* tf_port_itemFront: tf_port_itemDir */ #line 2999 "VParseBison.y" { VARDTYPE(""); /*default_nettype-see spec*/ } #line 26519 "VParseBison.c" break; case 881: /* tf_port_itemFront: tf_port_itemDir data_type */ #line 3000 "VParseBison.y" { VARDTYPE((yyvsp[0].str)); } #line 26525 "VParseBison.c" break; case 882: /* tf_port_itemFront: tf_port_itemDir signingE rangeList */ #line 3001 "VParseBison.y" { VARDTYPE(SPACED((yyvsp[-1].str),(yyvsp[0].str))); } #line 26531 "VParseBison.c" break; case 883: /* tf_port_itemFront: tf_port_itemDir signing */ #line 3002 "VParseBison.y" { VARDTYPE((yyvsp[0].str)); } #line 26537 "VParseBison.c" break; case 884: /* tf_port_itemFront: tf_port_itemDir "var" data_type */ #line 3003 "VParseBison.y" { VARDTYPE((yyvsp[0].str)); } #line 26543 "VParseBison.c" break; case 885: /* tf_port_itemFront: tf_port_itemDir "var" implicit_typeE */ #line 3004 "VParseBison.y" { VARDTYPE((yyvsp[0].str)); } #line 26549 "VParseBison.c" break; case 886: /* tf_port_itemDir: port_direction */ #line 3008 "VParseBison.y" { } #line 26555 "VParseBison.c" break; case 887: /* tf_port_itemAssignment: id variable_dimensionListE sigAttrListE */ #line 3013 "VParseBison.y" { VARDONE((yyvsp[-2].fl), (yyvsp[-2].str), (yyvsp[-1].str), ""); } #line 26561 "VParseBison.c" break; case 888: /* tf_port_itemAssignment: id variable_dimensionListE sigAttrListE '=' expr */ #line 3015 "VParseBison.y" { VARDONE((yyvsp[-4].fl), (yyvsp[-4].str), (yyvsp[-3].str), (yyvsp[0].str)); } #line 26567 "VParseBison.c" break; case 889: /* parenE: %empty */ #line 3019 "VParseBison.y" { } #line 26573 "VParseBison.c" break; case 890: /* parenE: '(' ')' */ #line 3020 "VParseBison.y" { } #line 26579 "VParseBison.c" break; case 891: /* array_methodNoRoot: array_method_nameNoId method_callWithE */ #line 3033 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str)=(yyvsp[-1].str)+(yyvsp[0].str); } #line 26585 "VParseBison.c" break; case 892: /* array_methodNoRoot: array_method_nameNoId '(' list_of_argumentsE ')' method_callWithE */ #line 3034 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str)=(yyvsp[-4].str)+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 26591 "VParseBison.c" break; case 893: /* method_callWithE: %empty */ #line 3040 "VParseBison.y" { (yyval.str)=""; } #line 26597 "VParseBison.c" break; case 894: /* method_callWithE: "with-then-(" '(' expr ')' */ #line 3041 "VParseBison.y" { (yyval.fl)=(yyvsp[-3].fl); (yyval.str)=(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 26603 "VParseBison.c" break; case 895: /* array_method_nameNoId: "unique" */ #line 3045 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 26609 "VParseBison.c" break; case 896: /* array_method_nameNoId: "and" */ #line 3046 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 26615 "VParseBison.c" break; case 897: /* array_method_nameNoId: "or" */ #line 3047 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 26621 "VParseBison.c" break; case 898: /* array_method_nameNoId: "xor" */ #line 3048 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 26627 "VParseBison.c" break; case 899: /* dpi_import_export: "import" "STRING" dpi_tf_import_propertyE dpi_importLabelE function_prototype ';' */ #line 3052 "VParseBison.y" { } #line 26633 "VParseBison.c" break; case 900: /* dpi_import_export: "import" "STRING" dpi_tf_import_propertyE dpi_importLabelE task_prototype ';' */ #line 3053 "VParseBison.y" { } #line 26639 "VParseBison.c" break; case 901: /* dpi_import_export: "export" "STRING" dpi_importLabelE function idAny ';' */ #line 3054 "VParseBison.y" { } #line 26645 "VParseBison.c" break; case 902: /* dpi_import_export: "export" "STRING" dpi_importLabelE task idAny ';' */ #line 3055 "VParseBison.y" { } #line 26651 "VParseBison.c" break; case 903: /* dpi_importLabelE: %empty */ #line 3059 "VParseBison.y" { } #line 26657 "VParseBison.c" break; case 904: /* dpi_importLabelE: idAny '=' */ #line 3060 "VParseBison.y" { } #line 26663 "VParseBison.c" break; case 905: /* dpi_tf_import_propertyE: %empty */ #line 3064 "VParseBison.y" { } #line 26669 "VParseBison.c" break; case 906: /* dpi_tf_import_propertyE: "context" */ #line 3065 "VParseBison.y" { } #line 26675 "VParseBison.c" break; case 907: /* dpi_tf_import_propertyE: "pure" */ #line 3066 "VParseBison.y" { } #line 26681 "VParseBison.c" break; case 908: /* overload_declaration: "bind" overload_operator function data_type idAny '(' overload_proto_formals ')' ';' */ #line 3072 "VParseBison.y" { } #line 26687 "VParseBison.c" break; case 909: /* overload_operator: "+" */ #line 3076 "VParseBison.y" { (yyval.str)="+"; } #line 26693 "VParseBison.c" break; case 910: /* overload_operator: "++" */ #line 3077 "VParseBison.y" { (yyval.str)="++"; } #line 26699 "VParseBison.c" break; case 911: /* overload_operator: "-" */ #line 3078 "VParseBison.y" { (yyval.str)="-"; } #line 26705 "VParseBison.c" break; case 912: /* overload_operator: "--" */ #line 3079 "VParseBison.y" { (yyval.str)="--"; } #line 26711 "VParseBison.c" break; case 913: /* overload_operator: "*" */ #line 3080 "VParseBison.y" { (yyval.str)="*"; } #line 26717 "VParseBison.c" break; case 914: /* overload_operator: "**" */ #line 3081 "VParseBison.y" { (yyval.str)="**"; } #line 26723 "VParseBison.c" break; case 915: /* overload_operator: "/" */ #line 3082 "VParseBison.y" { (yyval.str)="/"; } #line 26729 "VParseBison.c" break; case 916: /* overload_operator: "%" */ #line 3083 "VParseBison.y" { (yyval.str)="%"; } #line 26735 "VParseBison.c" break; case 917: /* overload_operator: "==" */ #line 3084 "VParseBison.y" { (yyval.str)="=="; } #line 26741 "VParseBison.c" break; case 918: /* overload_operator: "!=" */ #line 3085 "VParseBison.y" { (yyval.str)="!="; } #line 26747 "VParseBison.c" break; case 919: /* overload_operator: "<" */ #line 3086 "VParseBison.y" { (yyval.str)="<"; } #line 26753 "VParseBison.c" break; case 920: /* overload_operator: "<=" */ #line 3087 "VParseBison.y" { (yyval.str)="<="; } #line 26759 "VParseBison.c" break; case 921: /* overload_operator: ">" */ #line 3088 "VParseBison.y" { (yyval.str)=">"; } #line 26765 "VParseBison.c" break; case 922: /* overload_operator: ">=" */ #line 3089 "VParseBison.y" { (yyval.str)=">="; } #line 26771 "VParseBison.c" break; case 923: /* overload_operator: "=" */ #line 3090 "VParseBison.y" { (yyval.str)="="; } #line 26777 "VParseBison.c" break; case 924: /* overload_proto_formals: data_type */ #line 3094 "VParseBison.y" { } #line 26783 "VParseBison.c" break; case 925: /* overload_proto_formals: overload_proto_formals ',' data_type */ #line 3095 "VParseBison.y" { } #line 26789 "VParseBison.c" break; case 926: /* constExpr: expr */ #line 3110 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 26795 "VParseBison.c" break; case 927: /* expr: '+' expr */ #line 3117 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 26801 "VParseBison.c" break; case 928: /* expr: '-' expr */ #line 3118 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 26807 "VParseBison.c" break; case 929: /* expr: '!' expr */ #line 3119 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 26813 "VParseBison.c" break; case 930: /* expr: '&' expr */ #line 3120 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 26819 "VParseBison.c" break; case 931: /* expr: '~' expr */ #line 3121 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 26825 "VParseBison.c" break; case 932: /* expr: '|' expr */ #line 3122 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 26831 "VParseBison.c" break; case 933: /* expr: '^' expr */ #line 3123 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 26837 "VParseBison.c" break; case 934: /* expr: "~&" expr */ #line 3124 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 26843 "VParseBison.c" break; case 935: /* expr: "~|" expr */ #line 3125 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 26849 "VParseBison.c" break; case 936: /* expr: "^~" expr */ #line 3126 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 26855 "VParseBison.c" break; case 937: /* expr: inc_or_dec_expression */ #line 3129 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 26861 "VParseBison.c" break; case 938: /* expr: '(' exprScope '=' expr ')' */ #line 3133 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 26867 "VParseBison.c" break; case 939: /* expr: '(' exprScope "+=" expr ')' */ #line 3134 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 26873 "VParseBison.c" break; case 940: /* expr: '(' exprScope "-=" expr ')' */ #line 3135 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 26879 "VParseBison.c" break; case 941: /* expr: '(' exprScope "*=" expr ')' */ #line 3136 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 26885 "VParseBison.c" break; case 942: /* expr: '(' exprScope "/=" expr ')' */ #line 3137 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 26891 "VParseBison.c" break; case 943: /* expr: '(' exprScope "%=" expr ')' */ #line 3138 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 26897 "VParseBison.c" break; case 944: /* expr: '(' exprScope "&=" expr ')' */ #line 3139 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 26903 "VParseBison.c" break; case 945: /* expr: '(' exprScope "|=" expr ')' */ #line 3140 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 26909 "VParseBison.c" break; case 946: /* expr: '(' exprScope "^=" expr ')' */ #line 3141 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 26915 "VParseBison.c" break; case 947: /* expr: '(' exprScope "<<=" expr ')' */ #line 3142 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 26921 "VParseBison.c" break; case 948: /* expr: '(' exprScope ">>=" expr ')' */ #line 3143 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 26927 "VParseBison.c" break; case 949: /* expr: '(' exprScope ">>>=" expr ')' */ #line 3144 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 26933 "VParseBison.c" break; case 950: /* expr: expr '+' expr */ #line 3147 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 26939 "VParseBison.c" break; case 951: /* expr: expr '-' expr */ #line 3148 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 26945 "VParseBison.c" break; case 952: /* expr: expr '*' expr */ #line 3149 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 26951 "VParseBison.c" break; case 953: /* expr: expr '/' expr */ #line 3150 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 26957 "VParseBison.c" break; case 954: /* expr: expr '%' expr */ #line 3151 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 26963 "VParseBison.c" break; case 955: /* expr: expr "==" expr */ #line 3152 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 26969 "VParseBison.c" break; case 956: /* expr: expr "!=" expr */ #line 3153 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 26975 "VParseBison.c" break; case 957: /* expr: expr "===" expr */ #line 3154 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 26981 "VParseBison.c" break; case 958: /* expr: expr "!==" expr */ #line 3155 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 26987 "VParseBison.c" break; case 959: /* expr: expr "==?" expr */ #line 3156 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 26993 "VParseBison.c" break; case 960: /* expr: expr "!=?" expr */ #line 3157 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 26999 "VParseBison.c" break; case 961: /* expr: expr "&&" expr */ #line 3158 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 27005 "VParseBison.c" break; case 962: /* expr: expr "||" expr */ #line 3159 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 27011 "VParseBison.c" break; case 963: /* expr: expr "**" expr */ #line 3160 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 27017 "VParseBison.c" break; case 964: /* expr: expr '<' expr */ #line 3161 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 27023 "VParseBison.c" break; case 965: /* expr: expr '>' expr */ #line 3162 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 27029 "VParseBison.c" break; case 966: /* expr: expr ">=" expr */ #line 3163 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 27035 "VParseBison.c" break; case 967: /* expr: expr '&' expr */ #line 3164 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 27041 "VParseBison.c" break; case 968: /* expr: expr '|' expr */ #line 3165 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 27047 "VParseBison.c" break; case 969: /* expr: expr '^' expr */ #line 3166 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 27053 "VParseBison.c" break; case 970: /* expr: expr "^~" expr */ #line 3167 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 27059 "VParseBison.c" break; case 971: /* expr: expr "~|" expr */ #line 3168 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 27065 "VParseBison.c" break; case 972: /* expr: expr "~&" expr */ #line 3169 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 27071 "VParseBison.c" break; case 973: /* expr: expr "<<" expr */ #line 3170 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 27077 "VParseBison.c" break; case 974: /* expr: expr ">>" expr */ #line 3171 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 27083 "VParseBison.c" break; case 975: /* expr: expr ">>>" expr */ #line 3172 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 27089 "VParseBison.c" break; case 976: /* expr: expr "<->" expr */ #line 3173 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 27095 "VParseBison.c" break; case 977: /* expr: expr "->" constraint_set */ #line 3179 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 27101 "VParseBison.c" break; case 978: /* expr: expr "<=" expr */ #line 3183 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 27107 "VParseBison.c" break; case 979: /* expr: expr '?' expr ':' expr */ #line 3186 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = (yyvsp[-4].str)+"?"+(yyvsp[-2].str)+":"+(yyvsp[0].str); } #line 27113 "VParseBison.c" break; case 980: /* expr: expr "inside" '{' open_range_list '}' */ #line 3189 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = (yyvsp[-4].str)+" inside {"+(yyvsp[-2].str)+"}"; } #line 27119 "VParseBison.c" break; case 981: /* expr: "tagged" id */ #line 3192 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = " tagged "+(yyvsp[-1].str); } #line 27125 "VParseBison.c" break; case 982: /* expr: "tagged" id expr */ #line 3193 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = " tagged "+(yyvsp[-2].str)+" "+(yyvsp[-1].str); } #line 27131 "VParseBison.c" break; case 983: /* expr: "INTEGER NUMBER" */ #line 3198 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 27137 "VParseBison.c" break; case 984: /* expr: "FLOATING-POINT NUMBER" */ #line 3199 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 27143 "VParseBison.c" break; case 985: /* expr: "TIME NUMBER" */ #line 3200 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 27149 "VParseBison.c" break; case 986: /* expr: strAsInt */ #line 3201 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 27155 "VParseBison.c" break; case 988: /* expr: '{' constExpr '{' cateList '}' '}' */ #line 3212 "VParseBison.y" { (yyval.fl)=(yyvsp[-5].fl); (yyval.str) = "{"+(yyvsp[-4].str)+"{"+(yyvsp[-2].str)+"}}"; } #line 27161 "VParseBison.c" break; case 989: /* expr: '{' constExpr '{' cateList '}' '}' '[' expr ']' */ #line 3215 "VParseBison.y" { (yyval.fl)=(yyvsp[-8].fl); (yyval.str) = "{"+(yyvsp[-7].str)+"{"+(yyvsp[-5].str)+"}}["+(yyvsp[-1].str)+"]"; NEED_S09((yyvsp[-3].fl),"{}[]"); } #line 27167 "VParseBison.c" break; case 990: /* expr: '{' constExpr '{' cateList '}' '}' '[' expr ':' expr ']' */ #line 3217 "VParseBison.y" { (yyval.fl)=(yyvsp[-10].fl); (yyval.str) = "{"+(yyvsp[-9].str)+"{"+(yyvsp[-7].str)+"}}["+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+"]"; NEED_S09((yyvsp[-5].fl),"{}[]"); } #line 27173 "VParseBison.c" break; case 991: /* expr: '{' constExpr '{' cateList '}' '}' '[' expr "+:" expr ']' */ #line 3219 "VParseBison.y" { (yyval.fl)=(yyvsp[-10].fl); (yyval.str) = "{"+(yyvsp[-9].str)+"{"+(yyvsp[-7].str)+"}}["+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+"]"; NEED_S09((yyvsp[-5].fl),"{}[]"); } #line 27179 "VParseBison.c" break; case 992: /* expr: '{' constExpr '{' cateList '}' '}' '[' expr "-:" expr ']' */ #line 3221 "VParseBison.y" { (yyval.fl)=(yyvsp[-10].fl); (yyval.str) = "{"+(yyvsp[-9].str)+"{"+(yyvsp[-7].str)+"}}["+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+"]"; NEED_S09((yyvsp[-5].fl),"{}[]"); } #line 27185 "VParseBison.c" break; case 993: /* expr: function_subroutine_callNoMethod */ #line 3223 "VParseBison.y" { (yyval.str) = (yyvsp[0].str); } #line 27191 "VParseBison.c" break; case 994: /* expr: expr '.' function_subroutine_callNoMethod */ #line 3225 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str)=(yyvsp[-2].str)+"."+(yyvsp[0].str); } #line 27197 "VParseBison.c" break; case 995: /* expr: expr '.' array_methodNoRoot */ #line 3227 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+"."+(yyvsp[0].str); } #line 27203 "VParseBison.c" break; case 996: /* expr: '(' expr ')' */ #line 3233 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = "("+(yyvsp[-1].str)+")"; } #line 27209 "VParseBison.c" break; case 997: /* expr: '(' expr ':' expr ':' expr ')' */ #line 3234 "VParseBison.y" { (yyval.fl)=(yyvsp[-6].fl); (yyval.str) = "("+(yyvsp[-5].str)+":"+(yyvsp[-3].str)+":"+(yyvsp[-2].str)+")"; } #line 27215 "VParseBison.c" break; case 998: /* expr: '_' '(' statePushVlg expr statePop ')' */ #line 3236 "VParseBison.y" { (yyval.fl)=(yyvsp[-5].fl); (yyval.str) = "_("+(yyvsp[-2].str)+")"; } #line 27221 "VParseBison.c" break; case 999: /* expr: casting_type "'" '(' expr ')' */ #line 3239 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = (yyvsp[-4].str)+"'("+(yyvsp[-1].str)+")"; } #line 27227 "VParseBison.c" break; case 1000: /* expr: expr "'" '(' expr ')' */ #line 3242 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = (yyvsp[-4].str)+"'("+(yyvsp[-1].str)+")"; } #line 27233 "VParseBison.c" break; case 1001: /* expr: '$' */ #line 3251 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = "$"; } #line 27239 "VParseBison.c" break; case 1002: /* expr: "null" */ #line 3252 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 27245 "VParseBison.c" break; case 1003: /* expr: exprOkLvalue */ #line 3259 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 27251 "VParseBison.c" break; case 1004: /* expr: expr "&&&" expr */ #line 3265 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str) + "&&&" + (yyvsp[0].str); } #line 27257 "VParseBison.c" break; case 1005: /* expr: expr "matches" patternNoExpr */ #line 3270 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str) + " matches " + (yyvsp[0].str); } #line 27263 "VParseBison.c" break; case 1006: /* expr: expr "matches" expr */ #line 3271 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str) + " matches " + (yyvsp[0].str); } #line 27269 "VParseBison.c" break; case 1007: /* expr: expr "dist" '{' dist_list '}' */ #line 3275 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = (yyvsp[-4].str) + " dist " + (yyvsp[-2].str)+"..."+(yyvsp[0].str); } #line 27275 "VParseBison.c" break; case 1008: /* fexpr: '+' fexpr */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 27281 "VParseBison.c" break; case 1009: /* fexpr: '-' fexpr */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 27287 "VParseBison.c" break; case 1010: /* fexpr: '!' fexpr */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 27293 "VParseBison.c" break; case 1011: /* fexpr: '&' fexpr */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 27299 "VParseBison.c" break; case 1012: /* fexpr: '~' fexpr */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 27305 "VParseBison.c" break; case 1013: /* fexpr: '|' fexpr */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 27311 "VParseBison.c" break; case 1014: /* fexpr: '^' fexpr */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 27317 "VParseBison.c" break; case 1015: /* fexpr: "~&" fexpr */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 27323 "VParseBison.c" break; case 1016: /* fexpr: "~|" fexpr */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 27329 "VParseBison.c" break; case 1017: /* fexpr: "^~" fexpr */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 27335 "VParseBison.c" break; case 1018: /* fexpr: finc_or_dec_expression */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 27341 "VParseBison.c" break; case 1019: /* fexpr: '(' exprScope '=' expr ')' */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 27347 "VParseBison.c" break; case 1020: /* fexpr: '(' exprScope "+=" expr ')' */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 27353 "VParseBison.c" break; case 1021: /* fexpr: '(' exprScope "-=" expr ')' */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 27359 "VParseBison.c" break; case 1022: /* fexpr: '(' exprScope "*=" expr ')' */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 27365 "VParseBison.c" break; case 1023: /* fexpr: '(' exprScope "/=" expr ')' */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 27371 "VParseBison.c" break; case 1024: /* fexpr: '(' exprScope "%=" expr ')' */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 27377 "VParseBison.c" break; case 1025: /* fexpr: '(' exprScope "&=" expr ')' */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 27383 "VParseBison.c" break; case 1026: /* fexpr: '(' exprScope "|=" expr ')' */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 27389 "VParseBison.c" break; case 1027: /* fexpr: '(' exprScope "^=" expr ')' */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 27395 "VParseBison.c" break; case 1028: /* fexpr: '(' exprScope "<<=" expr ')' */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 27401 "VParseBison.c" break; case 1029: /* fexpr: '(' exprScope ">>=" expr ')' */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 27407 "VParseBison.c" break; case 1030: /* fexpr: '(' exprScope ">>>=" expr ')' */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 27413 "VParseBison.c" break; case 1031: /* fexpr: fexpr '+' fexpr */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 27419 "VParseBison.c" break; case 1032: /* fexpr: fexpr '-' fexpr */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 27425 "VParseBison.c" break; case 1033: /* fexpr: fexpr '*' fexpr */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 27431 "VParseBison.c" break; case 1034: /* fexpr: fexpr '/' fexpr */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 27437 "VParseBison.c" break; case 1035: /* fexpr: fexpr '%' fexpr */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 27443 "VParseBison.c" break; case 1036: /* fexpr: fexpr "==" fexpr */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 27449 "VParseBison.c" break; case 1037: /* fexpr: fexpr "!=" fexpr */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 27455 "VParseBison.c" break; case 1038: /* fexpr: fexpr "===" fexpr */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 27461 "VParseBison.c" break; case 1039: /* fexpr: fexpr "!==" fexpr */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 27467 "VParseBison.c" break; case 1040: /* fexpr: fexpr "==?" fexpr */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 27473 "VParseBison.c" break; case 1041: /* fexpr: fexpr "!=?" fexpr */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 27479 "VParseBison.c" break; case 1042: /* fexpr: fexpr "&&" fexpr */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 27485 "VParseBison.c" break; case 1043: /* fexpr: fexpr "||" fexpr */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 27491 "VParseBison.c" break; case 1044: /* fexpr: fexpr "**" fexpr */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 27497 "VParseBison.c" break; case 1045: /* fexpr: fexpr '<' fexpr */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 27503 "VParseBison.c" break; case 1046: /* fexpr: fexpr '>' fexpr */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 27509 "VParseBison.c" break; case 1047: /* fexpr: fexpr ">=" fexpr */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 27515 "VParseBison.c" break; case 1048: /* fexpr: fexpr '&' fexpr */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 27521 "VParseBison.c" break; case 1049: /* fexpr: fexpr '|' fexpr */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 27527 "VParseBison.c" break; case 1050: /* fexpr: fexpr '^' fexpr */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 27533 "VParseBison.c" break; case 1051: /* fexpr: fexpr "^~" fexpr */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 27539 "VParseBison.c" break; case 1052: /* fexpr: fexpr "~|" fexpr */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 27545 "VParseBison.c" break; case 1053: /* fexpr: fexpr "~&" fexpr */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 27551 "VParseBison.c" break; case 1054: /* fexpr: fexpr "<<" fexpr */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 27557 "VParseBison.c" break; case 1055: /* fexpr: fexpr ">>" fexpr */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 27563 "VParseBison.c" break; case 1056: /* fexpr: fexpr ">>>" fexpr */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 27569 "VParseBison.c" break; case 1057: /* fexpr: fexpr "<->" fexpr */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 27575 "VParseBison.c" break; case 1058: /* fexpr: fexpr "->" constraint_set */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 27581 "VParseBison.c" break; case 1059: /* fexpr: fexpr "<=-ignored" fexpr */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 27587 "VParseBison.c" break; case 1060: /* fexpr: fexpr '?' fexpr ':' fexpr */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = (yyvsp[-4].str)+"?"+(yyvsp[-2].str)+":"+(yyvsp[0].str); } #line 27593 "VParseBison.c" break; case 1061: /* fexpr: fexpr "inside" '{' open_range_list '}' */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = (yyvsp[-4].str)+" inside {"+(yyvsp[-2].str)+"}"; } #line 27599 "VParseBison.c" break; case 1062: /* fexpr: "tagged" id */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = " tagged "+(yyvsp[-1].str); } #line 27605 "VParseBison.c" break; case 1063: /* fexpr: "tagged" id expr */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = " tagged "+(yyvsp[-2].str)+" "+(yyvsp[-1].str); } #line 27611 "VParseBison.c" break; case 1064: /* fexpr: "INTEGER NUMBER" */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 27617 "VParseBison.c" break; case 1065: /* fexpr: "FLOATING-POINT NUMBER" */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 27623 "VParseBison.c" break; case 1066: /* fexpr: "TIME NUMBER" */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 27629 "VParseBison.c" break; case 1067: /* fexpr: strAsInt */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 27635 "VParseBison.c" break; case 1069: /* fexpr: '{' constExpr '{' cateList '}' '}' */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-5].fl); (yyval.str) = "{"+(yyvsp[-4].str)+"{"+(yyvsp[-2].str)+"}}"; } #line 27641 "VParseBison.c" break; case 1070: /* fexpr: '{' constExpr '{' cateList '}' '}' '[' expr ']' */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-8].fl); (yyval.str) = "{"+(yyvsp[-7].str)+"{"+(yyvsp[-5].str)+"}}["+(yyvsp[-1].str)+"]"; NEED_S09((yyvsp[-3].fl),"{}[]"); } #line 27647 "VParseBison.c" break; case 1071: /* fexpr: '{' constExpr '{' cateList '}' '}' '[' expr ':' expr ']' */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-10].fl); (yyval.str) = "{"+(yyvsp[-9].str)+"{"+(yyvsp[-7].str)+"}}["+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+"]"; NEED_S09((yyvsp[-5].fl),"{}[]"); } #line 27653 "VParseBison.c" break; case 1072: /* fexpr: '{' constExpr '{' cateList '}' '}' '[' expr "+:" expr ']' */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-10].fl); (yyval.str) = "{"+(yyvsp[-9].str)+"{"+(yyvsp[-7].str)+"}}["+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+"]"; NEED_S09((yyvsp[-5].fl),"{}[]"); } #line 27659 "VParseBison.c" break; case 1073: /* fexpr: '{' constExpr '{' cateList '}' '}' '[' expr "-:" expr ']' */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-10].fl); (yyval.str) = "{"+(yyvsp[-9].str)+"{"+(yyvsp[-7].str)+"}}["+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+"]"; NEED_S09((yyvsp[-5].fl),"{}[]"); } #line 27665 "VParseBison.c" break; case 1074: /* fexpr: function_subroutine_callNoMethod */ #line 3279 "VParseBison.y" { (yyval.str) = (yyvsp[0].str); } #line 27671 "VParseBison.c" break; case 1075: /* fexpr: fexpr '.' function_subroutine_callNoMethod */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str)=(yyvsp[-2].str)+"."+(yyvsp[0].str); } #line 27677 "VParseBison.c" break; case 1076: /* fexpr: fexpr '.' array_methodNoRoot */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+"."+(yyvsp[0].str); } #line 27683 "VParseBison.c" break; case 1077: /* fexpr: '(' expr ')' */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = "("+(yyvsp[-1].str)+")"; } #line 27689 "VParseBison.c" break; case 1078: /* fexpr: '(' expr ':' expr ':' expr ')' */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-6].fl); (yyval.str) = "("+(yyvsp[-5].str)+":"+(yyvsp[-3].str)+":"+(yyvsp[-2].str)+")"; } #line 27695 "VParseBison.c" break; case 1079: /* fexpr: '_' '(' statePushVlg expr statePop ')' */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-5].fl); (yyval.str) = "_("+(yyvsp[-2].str)+")"; } #line 27701 "VParseBison.c" break; case 1080: /* fexpr: casting_type "'" '(' expr ')' */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = (yyvsp[-4].str)+"'("+(yyvsp[-1].str)+")"; } #line 27707 "VParseBison.c" break; case 1081: /* fexpr: fexpr "'" '(' expr ')' */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = (yyvsp[-4].str)+"'("+(yyvsp[-1].str)+")"; } #line 27713 "VParseBison.c" break; case 1082: /* fexpr: '$' */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = "$"; } #line 27719 "VParseBison.c" break; case 1083: /* fexpr: "null" */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 27725 "VParseBison.c" break; case 1084: /* fexpr: fexprOkLvalue */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 27731 "VParseBison.c" break; case 1085: /* fexpr: fexpr "&&&" fexpr */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str) + "&&&" + (yyvsp[0].str); } #line 27737 "VParseBison.c" break; case 1086: /* fexpr: fexpr "matches" patternNoExpr */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str) + " matches " + (yyvsp[0].str); } #line 27743 "VParseBison.c" break; case 1087: /* fexpr: fexpr "matches" fexpr */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str) + " matches " + (yyvsp[0].str); } #line 27749 "VParseBison.c" break; case 1088: /* fexpr: fexpr "dist" '{' dist_list '}' */ #line 3279 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = (yyvsp[-4].str) + " dist " + (yyvsp[-2].str)+"..."+(yyvsp[0].str); } #line 27755 "VParseBison.c" break; case 1089: /* ev_expr: senitemEdge */ #line 3287 "VParseBison.y" { } #line 27761 "VParseBison.c" break; case 1090: /* ev_expr: ev_expr "iff" expr */ #line 3288 "VParseBison.y" { } #line 27767 "VParseBison.c" break; case 1091: /* ev_expr: ev_expr "or" ev_expr */ #line 3294 "VParseBison.y" { } #line 27773 "VParseBison.c" break; case 1092: /* ev_expr: '+' ev_expr */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 27779 "VParseBison.c" break; case 1093: /* ev_expr: '-' ev_expr */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 27785 "VParseBison.c" break; case 1094: /* ev_expr: '!' ev_expr */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 27791 "VParseBison.c" break; case 1095: /* ev_expr: '&' ev_expr */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 27797 "VParseBison.c" break; case 1096: /* ev_expr: '~' ev_expr */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 27803 "VParseBison.c" break; case 1097: /* ev_expr: '|' ev_expr */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 27809 "VParseBison.c" break; case 1098: /* ev_expr: '^' ev_expr */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 27815 "VParseBison.c" break; case 1099: /* ev_expr: "~&" ev_expr */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 27821 "VParseBison.c" break; case 1100: /* ev_expr: "~|" ev_expr */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 27827 "VParseBison.c" break; case 1101: /* ev_expr: "^~" ev_expr */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 27833 "VParseBison.c" break; case 1102: /* ev_expr: ev_inc_or_dec_expression */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 27839 "VParseBison.c" break; case 1103: /* ev_expr: '(' ev_exprScope '=' expr ')' */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 27845 "VParseBison.c" break; case 1104: /* ev_expr: '(' ev_exprScope "+=" expr ')' */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 27851 "VParseBison.c" break; case 1105: /* ev_expr: '(' ev_exprScope "-=" expr ')' */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 27857 "VParseBison.c" break; case 1106: /* ev_expr: '(' ev_exprScope "*=" expr ')' */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 27863 "VParseBison.c" break; case 1107: /* ev_expr: '(' ev_exprScope "/=" expr ')' */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 27869 "VParseBison.c" break; case 1108: /* ev_expr: '(' ev_exprScope "%=" expr ')' */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 27875 "VParseBison.c" break; case 1109: /* ev_expr: '(' ev_exprScope "&=" expr ')' */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 27881 "VParseBison.c" break; case 1110: /* ev_expr: '(' ev_exprScope "|=" expr ')' */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 27887 "VParseBison.c" break; case 1111: /* ev_expr: '(' ev_exprScope "^=" expr ')' */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 27893 "VParseBison.c" break; case 1112: /* ev_expr: '(' ev_exprScope "<<=" expr ')' */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 27899 "VParseBison.c" break; case 1113: /* ev_expr: '(' ev_exprScope ">>=" expr ')' */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 27905 "VParseBison.c" break; case 1114: /* ev_expr: '(' ev_exprScope ">>>=" expr ')' */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 27911 "VParseBison.c" break; case 1115: /* ev_expr: ev_expr '+' ev_expr */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 27917 "VParseBison.c" break; case 1116: /* ev_expr: ev_expr '-' ev_expr */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 27923 "VParseBison.c" break; case 1117: /* ev_expr: ev_expr '*' ev_expr */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 27929 "VParseBison.c" break; case 1118: /* ev_expr: ev_expr '/' ev_expr */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 27935 "VParseBison.c" break; case 1119: /* ev_expr: ev_expr '%' ev_expr */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 27941 "VParseBison.c" break; case 1120: /* ev_expr: ev_expr "==" ev_expr */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 27947 "VParseBison.c" break; case 1121: /* ev_expr: ev_expr "!=" ev_expr */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 27953 "VParseBison.c" break; case 1122: /* ev_expr: ev_expr "===" ev_expr */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 27959 "VParseBison.c" break; case 1123: /* ev_expr: ev_expr "!==" ev_expr */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 27965 "VParseBison.c" break; case 1124: /* ev_expr: ev_expr "==?" ev_expr */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 27971 "VParseBison.c" break; case 1125: /* ev_expr: ev_expr "!=?" ev_expr */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 27977 "VParseBison.c" break; case 1126: /* ev_expr: ev_expr "&&" ev_expr */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 27983 "VParseBison.c" break; case 1127: /* ev_expr: ev_expr "||" ev_expr */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 27989 "VParseBison.c" break; case 1128: /* ev_expr: ev_expr "**" ev_expr */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 27995 "VParseBison.c" break; case 1129: /* ev_expr: ev_expr '<' ev_expr */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 28001 "VParseBison.c" break; case 1130: /* ev_expr: ev_expr '>' ev_expr */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 28007 "VParseBison.c" break; case 1131: /* ev_expr: ev_expr ">=" ev_expr */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 28013 "VParseBison.c" break; case 1132: /* ev_expr: ev_expr '&' ev_expr */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 28019 "VParseBison.c" break; case 1133: /* ev_expr: ev_expr '|' ev_expr */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 28025 "VParseBison.c" break; case 1134: /* ev_expr: ev_expr '^' ev_expr */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 28031 "VParseBison.c" break; case 1135: /* ev_expr: ev_expr "^~" ev_expr */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 28037 "VParseBison.c" break; case 1136: /* ev_expr: ev_expr "~|" ev_expr */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 28043 "VParseBison.c" break; case 1137: /* ev_expr: ev_expr "~&" ev_expr */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 28049 "VParseBison.c" break; case 1138: /* ev_expr: ev_expr "<<" ev_expr */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 28055 "VParseBison.c" break; case 1139: /* ev_expr: ev_expr ">>" ev_expr */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 28061 "VParseBison.c" break; case 1140: /* ev_expr: ev_expr ">>>" ev_expr */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 28067 "VParseBison.c" break; case 1141: /* ev_expr: ev_expr "<->" ev_expr */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 28073 "VParseBison.c" break; case 1142: /* ev_expr: ev_expr "->" constraint_set */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 28079 "VParseBison.c" break; case 1143: /* ev_expr: ev_expr "<=" ev_expr */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 28085 "VParseBison.c" break; case 1144: /* ev_expr: ev_expr '?' ev_expr ':' ev_expr */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = (yyvsp[-4].str)+"?"+(yyvsp[-2].str)+":"+(yyvsp[0].str); } #line 28091 "VParseBison.c" break; case 1145: /* ev_expr: ev_expr "inside" '{' open_range_list '}' */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = (yyvsp[-4].str)+" inside {"+(yyvsp[-2].str)+"}"; } #line 28097 "VParseBison.c" break; case 1146: /* ev_expr: "tagged" id */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = " tagged "+(yyvsp[-1].str); } #line 28103 "VParseBison.c" break; case 1147: /* ev_expr: "tagged" id expr */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = " tagged "+(yyvsp[-2].str)+" "+(yyvsp[-1].str); } #line 28109 "VParseBison.c" break; case 1148: /* ev_expr: "INTEGER NUMBER" */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 28115 "VParseBison.c" break; case 1149: /* ev_expr: "FLOATING-POINT NUMBER" */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 28121 "VParseBison.c" break; case 1150: /* ev_expr: "TIME NUMBER" */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 28127 "VParseBison.c" break; case 1151: /* ev_expr: strAsInt */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 28133 "VParseBison.c" break; case 1153: /* ev_expr: '{' constExpr '{' cateList '}' '}' */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-5].fl); (yyval.str) = "{"+(yyvsp[-4].str)+"{"+(yyvsp[-2].str)+"}}"; } #line 28139 "VParseBison.c" break; case 1154: /* ev_expr: '{' constExpr '{' cateList '}' '}' '[' expr ']' */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-8].fl); (yyval.str) = "{"+(yyvsp[-7].str)+"{"+(yyvsp[-5].str)+"}}["+(yyvsp[-1].str)+"]"; NEED_S09((yyvsp[-3].fl),"{}[]"); } #line 28145 "VParseBison.c" break; case 1155: /* ev_expr: '{' constExpr '{' cateList '}' '}' '[' expr ':' expr ']' */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-10].fl); (yyval.str) = "{"+(yyvsp[-9].str)+"{"+(yyvsp[-7].str)+"}}["+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+"]"; NEED_S09((yyvsp[-5].fl),"{}[]"); } #line 28151 "VParseBison.c" break; case 1156: /* ev_expr: '{' constExpr '{' cateList '}' '}' '[' expr "+:" expr ']' */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-10].fl); (yyval.str) = "{"+(yyvsp[-9].str)+"{"+(yyvsp[-7].str)+"}}["+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+"]"; NEED_S09((yyvsp[-5].fl),"{}[]"); } #line 28157 "VParseBison.c" break; case 1157: /* ev_expr: '{' constExpr '{' cateList '}' '}' '[' expr "-:" expr ']' */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-10].fl); (yyval.str) = "{"+(yyvsp[-9].str)+"{"+(yyvsp[-7].str)+"}}["+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+"]"; NEED_S09((yyvsp[-5].fl),"{}[]"); } #line 28163 "VParseBison.c" break; case 1158: /* ev_expr: function_subroutine_callNoMethod */ #line 3300 "VParseBison.y" { (yyval.str) = (yyvsp[0].str); } #line 28169 "VParseBison.c" break; case 1159: /* ev_expr: ev_expr '.' function_subroutine_callNoMethod */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str)=(yyvsp[-2].str)+"."+(yyvsp[0].str); } #line 28175 "VParseBison.c" break; case 1160: /* ev_expr: ev_expr '.' array_methodNoRoot */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+"."+(yyvsp[0].str); } #line 28181 "VParseBison.c" break; case 1161: /* ev_expr: "(-ignored" '(' expr ')' */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-3].fl); (yyval.str) = "("+(yyvsp[-2].str)+")"; } #line 28187 "VParseBison.c" break; case 1162: /* ev_expr: "(-ignored" '(' expr ':' expr ':' expr ')' */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-7].fl); (yyval.str) = "("+(yyvsp[-6].str)+":"+(yyvsp[-4].str)+":"+(yyvsp[-3].str)+")"; } #line 28193 "VParseBison.c" break; case 1163: /* ev_expr: '_' '(' statePushVlg expr statePop ')' */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-5].fl); (yyval.str) = "_("+(yyvsp[-2].str)+")"; } #line 28199 "VParseBison.c" break; case 1164: /* ev_expr: casting_type "'" '(' expr ')' */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = (yyvsp[-4].str)+"'("+(yyvsp[-1].str)+")"; } #line 28205 "VParseBison.c" break; case 1165: /* ev_expr: ev_expr "'" '(' expr ')' */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = (yyvsp[-4].str)+"'("+(yyvsp[-1].str)+")"; } #line 28211 "VParseBison.c" break; case 1166: /* ev_expr: '$' */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = "$"; } #line 28217 "VParseBison.c" break; case 1167: /* ev_expr: "null" */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 28223 "VParseBison.c" break; case 1168: /* ev_expr: ev_exprOkLvalue */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 28229 "VParseBison.c" break; case 1169: /* ev_expr: ev_expr "&&&" ev_expr */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str) + "&&&" + (yyvsp[0].str); } #line 28235 "VParseBison.c" break; case 1170: /* ev_expr: ev_expr "matches" patternNoExpr */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str) + " matches " + (yyvsp[0].str); } #line 28241 "VParseBison.c" break; case 1171: /* ev_expr: ev_expr "matches" ev_expr */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str) + " matches " + (yyvsp[0].str); } #line 28247 "VParseBison.c" break; case 1172: /* ev_expr: ev_expr "dist" '{' dist_list '}' */ #line 3300 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = (yyvsp[-4].str) + " dist " + (yyvsp[-2].str)+"..."+(yyvsp[0].str); } #line 28253 "VParseBison.c" break; case 1173: /* ev_expr: '(' event_expression ')' */ #line 3305 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = "(...)"; } #line 28259 "VParseBison.c" break; case 1174: /* ev_expr: '(' event_expression ':' expr ':' expr ')' */ #line 3308 "VParseBison.y" { (yyval.fl)=(yyvsp[-6].fl); (yyval.str) = "(...)"; } #line 28265 "VParseBison.c" break; case 1175: /* exprOkLvalue: exprScope */ #line 3315 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 28271 "VParseBison.c" break; case 1176: /* exprOkLvalue: '{' cateList '}' */ #line 3317 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = "{"+(yyvsp[-1].str)+"}"; } #line 28277 "VParseBison.c" break; case 1177: /* exprOkLvalue: '{' cateList '}' '[' expr ']' */ #line 3319 "VParseBison.y" { (yyval.fl)=(yyvsp[-5].fl); (yyval.str) = "{"+(yyvsp[-4].str)+"}["+(yyvsp[-1].str)+"]"; NEED_S09((yyvsp[-2].fl),"{}[]"); } #line 28283 "VParseBison.c" break; case 1178: /* exprOkLvalue: '{' cateList '}' '[' expr ':' expr ']' */ #line 3320 "VParseBison.y" { (yyval.fl)=(yyvsp[-7].fl); (yyval.str) = "{"+(yyvsp[-6].str)+"}["+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+"]"; NEED_S09((yyvsp[-4].fl),"{}[]"); } #line 28289 "VParseBison.c" break; case 1179: /* exprOkLvalue: '{' cateList '}' '[' expr "+:" expr ']' */ #line 3321 "VParseBison.y" { (yyval.fl)=(yyvsp[-7].fl); (yyval.str) = "{"+(yyvsp[-6].str)+"}["+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+"]"; NEED_S09((yyvsp[-4].fl),"{}[]"); } #line 28295 "VParseBison.c" break; case 1180: /* exprOkLvalue: '{' cateList '}' '[' expr "-:" expr ']' */ #line 3322 "VParseBison.y" { (yyval.fl)=(yyvsp[-7].fl); (yyval.str) = "{"+(yyvsp[-6].str)+"}["+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+"]"; NEED_S09((yyvsp[-4].fl),"{}[]"); } #line 28301 "VParseBison.c" break; case 1181: /* exprOkLvalue: exprScope assignment_pattern */ #line 3326 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str)=(yyvsp[-1].str)+(yyvsp[0].str); } #line 28307 "VParseBison.c" break; case 1182: /* exprOkLvalue: data_type assignment_pattern */ #line 3327 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str)=(yyvsp[-1].str)+(yyvsp[0].str); } #line 28313 "VParseBison.c" break; case 1183: /* exprOkLvalue: assignment_pattern */ #line 3328 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 28319 "VParseBison.c" break; case 1184: /* exprOkLvalue: streaming_concatenation */ #line 3330 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 28325 "VParseBison.c" break; case 1185: /* fexprOkLvalue: fexprScope */ #line 3334 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 28331 "VParseBison.c" break; case 1186: /* fexprOkLvalue: '{' cateList '}' */ #line 3334 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = "{"+(yyvsp[-1].str)+"}"; } #line 28337 "VParseBison.c" break; case 1187: /* fexprOkLvalue: '{' cateList '}' '[' expr ']' */ #line 3334 "VParseBison.y" { (yyval.fl)=(yyvsp[-5].fl); (yyval.str) = "{"+(yyvsp[-4].str)+"}["+(yyvsp[-1].str)+"]"; NEED_S09((yyvsp[-2].fl),"{}[]"); } #line 28343 "VParseBison.c" break; case 1188: /* fexprOkLvalue: '{' cateList '}' '[' expr ':' expr ']' */ #line 3334 "VParseBison.y" { (yyval.fl)=(yyvsp[-7].fl); (yyval.str) = "{"+(yyvsp[-6].str)+"}["+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+"]"; NEED_S09((yyvsp[-4].fl),"{}[]"); } #line 28349 "VParseBison.c" break; case 1189: /* fexprOkLvalue: '{' cateList '}' '[' expr "+:" expr ']' */ #line 3334 "VParseBison.y" { (yyval.fl)=(yyvsp[-7].fl); (yyval.str) = "{"+(yyvsp[-6].str)+"}["+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+"]"; NEED_S09((yyvsp[-4].fl),"{}[]"); } #line 28355 "VParseBison.c" break; case 1190: /* fexprOkLvalue: '{' cateList '}' '[' expr "-:" expr ']' */ #line 3334 "VParseBison.y" { (yyval.fl)=(yyvsp[-7].fl); (yyval.str) = "{"+(yyvsp[-6].str)+"}["+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+"]"; NEED_S09((yyvsp[-4].fl),"{}[]"); } #line 28361 "VParseBison.c" break; case 1191: /* fexprOkLvalue: fexprScope assignment_pattern */ #line 3334 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str)=(yyvsp[-1].str)+(yyvsp[0].str); } #line 28367 "VParseBison.c" break; case 1192: /* fexprOkLvalue: data_type assignment_pattern */ #line 3334 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str)=(yyvsp[-1].str)+(yyvsp[0].str); } #line 28373 "VParseBison.c" break; case 1193: /* fexprOkLvalue: assignment_pattern */ #line 3334 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 28379 "VParseBison.c" break; case 1194: /* fexprOkLvalue: streaming_concatenation */ #line 3334 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 28385 "VParseBison.c" break; case 1195: /* sexprOkLvalue: sexprScope */ #line 3338 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 28391 "VParseBison.c" break; case 1196: /* sexprOkLvalue: '{' cateList '}' */ #line 3338 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = "{"+(yyvsp[-1].str)+"}"; } #line 28397 "VParseBison.c" break; case 1197: /* sexprOkLvalue: '{' cateList '}' '[' expr ']' */ #line 3338 "VParseBison.y" { (yyval.fl)=(yyvsp[-5].fl); (yyval.str) = "{"+(yyvsp[-4].str)+"}["+(yyvsp[-1].str)+"]"; NEED_S09((yyvsp[-2].fl),"{}[]"); } #line 28403 "VParseBison.c" break; case 1198: /* sexprOkLvalue: '{' cateList '}' '[' expr ':' expr ']' */ #line 3338 "VParseBison.y" { (yyval.fl)=(yyvsp[-7].fl); (yyval.str) = "{"+(yyvsp[-6].str)+"}["+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+"]"; NEED_S09((yyvsp[-4].fl),"{}[]"); } #line 28409 "VParseBison.c" break; case 1199: /* sexprOkLvalue: '{' cateList '}' '[' expr "+:" expr ']' */ #line 3338 "VParseBison.y" { (yyval.fl)=(yyvsp[-7].fl); (yyval.str) = "{"+(yyvsp[-6].str)+"}["+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+"]"; NEED_S09((yyvsp[-4].fl),"{}[]"); } #line 28415 "VParseBison.c" break; case 1200: /* sexprOkLvalue: '{' cateList '}' '[' expr "-:" expr ']' */ #line 3338 "VParseBison.y" { (yyval.fl)=(yyvsp[-7].fl); (yyval.str) = "{"+(yyvsp[-6].str)+"}["+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+"]"; NEED_S09((yyvsp[-4].fl),"{}[]"); } #line 28421 "VParseBison.c" break; case 1201: /* sexprOkLvalue: sexprScope assignment_pattern */ #line 3338 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str)=(yyvsp[-1].str)+(yyvsp[0].str); } #line 28427 "VParseBison.c" break; case 1202: /* sexprOkLvalue: data_type assignment_pattern */ #line 3338 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str)=(yyvsp[-1].str)+(yyvsp[0].str); } #line 28433 "VParseBison.c" break; case 1203: /* sexprOkLvalue: assignment_pattern */ #line 3338 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 28439 "VParseBison.c" break; case 1204: /* sexprOkLvalue: streaming_concatenation */ #line 3338 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 28445 "VParseBison.c" break; case 1205: /* pexprOkLvalue: pexprScope */ #line 3342 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 28451 "VParseBison.c" break; case 1206: /* pexprOkLvalue: '{' cateList '}' */ #line 3342 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = "{"+(yyvsp[-1].str)+"}"; } #line 28457 "VParseBison.c" break; case 1207: /* pexprOkLvalue: '{' cateList '}' '[' expr ']' */ #line 3342 "VParseBison.y" { (yyval.fl)=(yyvsp[-5].fl); (yyval.str) = "{"+(yyvsp[-4].str)+"}["+(yyvsp[-1].str)+"]"; NEED_S09((yyvsp[-2].fl),"{}[]"); } #line 28463 "VParseBison.c" break; case 1208: /* pexprOkLvalue: '{' cateList '}' '[' expr ':' expr ']' */ #line 3342 "VParseBison.y" { (yyval.fl)=(yyvsp[-7].fl); (yyval.str) = "{"+(yyvsp[-6].str)+"}["+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+"]"; NEED_S09((yyvsp[-4].fl),"{}[]"); } #line 28469 "VParseBison.c" break; case 1209: /* pexprOkLvalue: '{' cateList '}' '[' expr "+:" expr ']' */ #line 3342 "VParseBison.y" { (yyval.fl)=(yyvsp[-7].fl); (yyval.str) = "{"+(yyvsp[-6].str)+"}["+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+"]"; NEED_S09((yyvsp[-4].fl),"{}[]"); } #line 28475 "VParseBison.c" break; case 1210: /* pexprOkLvalue: '{' cateList '}' '[' expr "-:" expr ']' */ #line 3342 "VParseBison.y" { (yyval.fl)=(yyvsp[-7].fl); (yyval.str) = "{"+(yyvsp[-6].str)+"}["+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+"]"; NEED_S09((yyvsp[-4].fl),"{}[]"); } #line 28481 "VParseBison.c" break; case 1211: /* pexprOkLvalue: pexprScope assignment_pattern */ #line 3342 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str)=(yyvsp[-1].str)+(yyvsp[0].str); } #line 28487 "VParseBison.c" break; case 1212: /* pexprOkLvalue: data_type assignment_pattern */ #line 3342 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str)=(yyvsp[-1].str)+(yyvsp[0].str); } #line 28493 "VParseBison.c" break; case 1213: /* pexprOkLvalue: assignment_pattern */ #line 3342 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 28499 "VParseBison.c" break; case 1214: /* pexprOkLvalue: streaming_concatenation */ #line 3342 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 28505 "VParseBison.c" break; case 1215: /* ev_exprOkLvalue: ev_exprScope */ #line 3346 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 28511 "VParseBison.c" break; case 1216: /* ev_exprOkLvalue: '{' cateList '}' */ #line 3346 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = "{"+(yyvsp[-1].str)+"}"; } #line 28517 "VParseBison.c" break; case 1217: /* ev_exprOkLvalue: '{' cateList '}' '[' expr ']' */ #line 3346 "VParseBison.y" { (yyval.fl)=(yyvsp[-5].fl); (yyval.str) = "{"+(yyvsp[-4].str)+"}["+(yyvsp[-1].str)+"]"; NEED_S09((yyvsp[-2].fl),"{}[]"); } #line 28523 "VParseBison.c" break; case 1218: /* ev_exprOkLvalue: '{' cateList '}' '[' expr ':' expr ']' */ #line 3346 "VParseBison.y" { (yyval.fl)=(yyvsp[-7].fl); (yyval.str) = "{"+(yyvsp[-6].str)+"}["+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+"]"; NEED_S09((yyvsp[-4].fl),"{}[]"); } #line 28529 "VParseBison.c" break; case 1219: /* ev_exprOkLvalue: '{' cateList '}' '[' expr "+:" expr ']' */ #line 3346 "VParseBison.y" { (yyval.fl)=(yyvsp[-7].fl); (yyval.str) = "{"+(yyvsp[-6].str)+"}["+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+"]"; NEED_S09((yyvsp[-4].fl),"{}[]"); } #line 28535 "VParseBison.c" break; case 1220: /* ev_exprOkLvalue: '{' cateList '}' '[' expr "-:" expr ']' */ #line 3346 "VParseBison.y" { (yyval.fl)=(yyvsp[-7].fl); (yyval.str) = "{"+(yyvsp[-6].str)+"}["+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+"]"; NEED_S09((yyvsp[-4].fl),"{}[]"); } #line 28541 "VParseBison.c" break; case 1221: /* ev_exprOkLvalue: ev_exprScope assignment_pattern */ #line 3346 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str)=(yyvsp[-1].str)+(yyvsp[0].str); } #line 28547 "VParseBison.c" break; case 1222: /* ev_exprOkLvalue: data_type assignment_pattern */ #line 3346 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str)=(yyvsp[-1].str)+(yyvsp[0].str); } #line 28553 "VParseBison.c" break; case 1223: /* ev_exprOkLvalue: assignment_pattern */ #line 3346 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 28559 "VParseBison.c" break; case 1224: /* ev_exprOkLvalue: streaming_concatenation */ #line 3346 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 28565 "VParseBison.c" break; case 1225: /* pev_exprOkLvalue: pev_exprScope */ #line 3350 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 28571 "VParseBison.c" break; case 1226: /* pev_exprOkLvalue: '{' cateList '}' */ #line 3350 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = "{"+(yyvsp[-1].str)+"}"; } #line 28577 "VParseBison.c" break; case 1227: /* pev_exprOkLvalue: '{' cateList '}' '[' expr ']' */ #line 3350 "VParseBison.y" { (yyval.fl)=(yyvsp[-5].fl); (yyval.str) = "{"+(yyvsp[-4].str)+"}["+(yyvsp[-1].str)+"]"; NEED_S09((yyvsp[-2].fl),"{}[]"); } #line 28583 "VParseBison.c" break; case 1228: /* pev_exprOkLvalue: '{' cateList '}' '[' expr ':' expr ']' */ #line 3350 "VParseBison.y" { (yyval.fl)=(yyvsp[-7].fl); (yyval.str) = "{"+(yyvsp[-6].str)+"}["+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+"]"; NEED_S09((yyvsp[-4].fl),"{}[]"); } #line 28589 "VParseBison.c" break; case 1229: /* pev_exprOkLvalue: '{' cateList '}' '[' expr "+:" expr ']' */ #line 3350 "VParseBison.y" { (yyval.fl)=(yyvsp[-7].fl); (yyval.str) = "{"+(yyvsp[-6].str)+"}["+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+"]"; NEED_S09((yyvsp[-4].fl),"{}[]"); } #line 28595 "VParseBison.c" break; case 1230: /* pev_exprOkLvalue: '{' cateList '}' '[' expr "-:" expr ']' */ #line 3350 "VParseBison.y" { (yyval.fl)=(yyvsp[-7].fl); (yyval.str) = "{"+(yyvsp[-6].str)+"}["+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+"]"; NEED_S09((yyvsp[-4].fl),"{}[]"); } #line 28601 "VParseBison.c" break; case 1231: /* pev_exprOkLvalue: pev_exprScope assignment_pattern */ #line 3350 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str)=(yyvsp[-1].str)+(yyvsp[0].str); } #line 28607 "VParseBison.c" break; case 1232: /* pev_exprOkLvalue: data_type assignment_pattern */ #line 3350 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str)=(yyvsp[-1].str)+(yyvsp[0].str); } #line 28613 "VParseBison.c" break; case 1233: /* pev_exprOkLvalue: assignment_pattern */ #line 3350 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 28619 "VParseBison.c" break; case 1234: /* pev_exprOkLvalue: streaming_concatenation */ #line 3350 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 28625 "VParseBison.c" break; case 1235: /* exprLvalue: exprOkLvalue */ #line 3354 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 28631 "VParseBison.c" break; case 1236: /* fexprLvalue: fexprOkLvalue */ #line 3358 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 28637 "VParseBison.c" break; case 1237: /* exprScope: "this" */ #line 3369 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 28643 "VParseBison.c" break; case 1238: /* exprScope: idArrayed */ #line 3370 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 28649 "VParseBison.c" break; case 1239: /* exprScope: package_scopeIdFollows idArrayed */ #line 3371 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 28655 "VParseBison.c" break; case 1240: /* exprScope: class_scopeIdFollows idArrayed */ #line 3372 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 28661 "VParseBison.c" break; case 1241: /* exprScope: expr '.' idArrayed */ #line 3373 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+"."+(yyvsp[0].str); PORTNET((yyvsp[-2].fl), (yyval.str)); } #line 28667 "VParseBison.c" break; case 1242: /* exprScope: expr '.' "super" */ #line 3375 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+"."+(yyvsp[0].str); } #line 28673 "VParseBison.c" break; case 1243: /* exprScope: "super" */ #line 3377 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 28679 "VParseBison.c" break; case 1244: /* fexprScope: "this" */ #line 3381 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 28685 "VParseBison.c" break; case 1245: /* fexprScope: idArrayed */ #line 3381 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 28691 "VParseBison.c" break; case 1246: /* fexprScope: package_scopeIdFollows idArrayed */ #line 3381 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 28697 "VParseBison.c" break; case 1247: /* fexprScope: class_scopeIdFollows idArrayed */ #line 3381 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 28703 "VParseBison.c" break; case 1248: /* fexprScope: fexpr '.' idArrayed */ #line 3381 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+"."+(yyvsp[0].str); PORTNET((yyvsp[-2].fl), (yyval.str)); } #line 28709 "VParseBison.c" break; case 1249: /* fexprScope: fexpr '.' "super" */ #line 3381 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+"."+(yyvsp[0].str); } #line 28715 "VParseBison.c" break; case 1250: /* fexprScope: "super" */ #line 3381 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 28721 "VParseBison.c" break; case 1251: /* sexprScope: "this" */ #line 3385 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 28727 "VParseBison.c" break; case 1252: /* sexprScope: idArrayed */ #line 3385 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 28733 "VParseBison.c" break; case 1253: /* sexprScope: package_scopeIdFollows idArrayed */ #line 3385 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 28739 "VParseBison.c" break; case 1254: /* sexprScope: class_scopeIdFollows idArrayed */ #line 3385 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 28745 "VParseBison.c" break; case 1255: /* sexprScope: sexpr '.' idArrayed */ #line 3385 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+"."+(yyvsp[0].str); PORTNET((yyvsp[-2].fl), (yyval.str)); } #line 28751 "VParseBison.c" break; case 1256: /* sexprScope: sexpr '.' "super" */ #line 3385 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+"."+(yyvsp[0].str); } #line 28757 "VParseBison.c" break; case 1257: /* sexprScope: "super" */ #line 3385 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 28763 "VParseBison.c" break; case 1258: /* pexprScope: "this" */ #line 3389 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 28769 "VParseBison.c" break; case 1259: /* pexprScope: idArrayed */ #line 3389 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 28775 "VParseBison.c" break; case 1260: /* pexprScope: package_scopeIdFollows idArrayed */ #line 3389 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 28781 "VParseBison.c" break; case 1261: /* pexprScope: class_scopeIdFollows idArrayed */ #line 3389 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 28787 "VParseBison.c" break; case 1262: /* pexprScope: pexpr '.' idArrayed */ #line 3389 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+"."+(yyvsp[0].str); PORTNET((yyvsp[-2].fl), (yyval.str)); } #line 28793 "VParseBison.c" break; case 1263: /* pexprScope: pexpr '.' "super" */ #line 3389 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+"."+(yyvsp[0].str); } #line 28799 "VParseBison.c" break; case 1264: /* pexprScope: "super" */ #line 3389 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 28805 "VParseBison.c" break; case 1265: /* ev_exprScope: "this" */ #line 3393 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 28811 "VParseBison.c" break; case 1266: /* ev_exprScope: idArrayed */ #line 3393 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 28817 "VParseBison.c" break; case 1267: /* ev_exprScope: package_scopeIdFollows idArrayed */ #line 3393 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 28823 "VParseBison.c" break; case 1268: /* ev_exprScope: class_scopeIdFollows idArrayed */ #line 3393 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 28829 "VParseBison.c" break; case 1269: /* ev_exprScope: ev_expr '.' idArrayed */ #line 3393 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+"."+(yyvsp[0].str); PORTNET((yyvsp[-2].fl), (yyval.str)); } #line 28835 "VParseBison.c" break; case 1270: /* ev_exprScope: ev_expr '.' "super" */ #line 3393 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+"."+(yyvsp[0].str); } #line 28841 "VParseBison.c" break; case 1271: /* ev_exprScope: "super" */ #line 3393 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 28847 "VParseBison.c" break; case 1272: /* pev_exprScope: "this" */ #line 3397 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 28853 "VParseBison.c" break; case 1273: /* pev_exprScope: idArrayed */ #line 3397 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 28859 "VParseBison.c" break; case 1274: /* pev_exprScope: package_scopeIdFollows idArrayed */ #line 3397 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 28865 "VParseBison.c" break; case 1275: /* pev_exprScope: class_scopeIdFollows idArrayed */ #line 3397 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 28871 "VParseBison.c" break; case 1276: /* pev_exprScope: pev_expr '.' idArrayed */ #line 3397 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+"."+(yyvsp[0].str); PORTNET((yyvsp[-2].fl), (yyval.str)); } #line 28877 "VParseBison.c" break; case 1277: /* pev_exprScope: pev_expr '.' "super" */ #line 3397 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+"."+(yyvsp[0].str); } #line 28883 "VParseBison.c" break; case 1278: /* pev_exprScope: "super" */ #line 3397 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 28889 "VParseBison.c" break; case 1279: /* exprOrDataType: expr */ #line 3402 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 28895 "VParseBison.c" break; case 1280: /* exprOrDataType: data_type */ #line 3404 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 28901 "VParseBison.c" break; case 1281: /* exprOrDataType: event_control */ #line 3406 "VParseBison.y" { (yyval.str) = "event_control"; } #line 28907 "VParseBison.c" break; case 1282: /* exprOrDataTypeOrMinTypMax: expr */ #line 3410 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 28913 "VParseBison.c" break; case 1283: /* exprOrDataTypeOrMinTypMax: expr ':' expr ':' expr */ #line 3411 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = (yyvsp[-4].str)+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 28919 "VParseBison.c" break; case 1284: /* exprOrDataTypeOrMinTypMax: data_type */ #line 3413 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 28925 "VParseBison.c" break; case 1285: /* exprOrDataTypeOrMinTypMax: event_control */ #line 3415 "VParseBison.y" { (yyval.str) = "event_control"; } #line 28931 "VParseBison.c" break; case 1286: /* cateList: stream_expression */ #line 3421 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); PIN_CONCAT_APPEND((yyvsp[0].str)); } #line 28937 "VParseBison.c" break; case 1287: /* cateList: cateList ',' stream_expression */ #line 3422 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+","+(yyvsp[0].str); PIN_CONCAT_APPEND((yyvsp[0].str)); } #line 28943 "VParseBison.c" break; case 1288: /* exprOrDataTypeList: exprOrDataType */ #line 3426 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 28949 "VParseBison.c" break; case 1289: /* exprOrDataTypeList: exprOrDataTypeList ',' exprOrDataType */ #line 3427 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+","+(yyvsp[0].str); } #line 28955 "VParseBison.c" break; case 1290: /* exprOrDataTypeList: exprOrDataTypeList ',' */ #line 3428 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+","; } #line 28961 "VParseBison.c" break; case 1291: /* list_of_argumentsE: argsDottedList */ #line 3433 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 28967 "VParseBison.c" break; case 1292: /* list_of_argumentsE: argsExprListE */ #line 3434 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 28973 "VParseBison.c" break; case 1293: /* list_of_argumentsE: argsExprListE ',' argsDottedList */ #line 3435 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str)=(yyvsp[-2].str)+","+(yyvsp[0].str); } #line 28979 "VParseBison.c" break; case 1294: /* pev_list_of_argumentsE: pev_argsDottedList */ #line 3440 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 28985 "VParseBison.c" break; case 1295: /* pev_list_of_argumentsE: pev_argsExprListE */ #line 3441 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 28991 "VParseBison.c" break; case 1296: /* pev_list_of_argumentsE: pev_argsExprListE ',' pev_argsDottedList */ #line 3442 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str)=(yyvsp[-2].str)+","+(yyvsp[0].str); } #line 28997 "VParseBison.c" break; case 1297: /* argsExprList: expr */ #line 3446 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 29003 "VParseBison.c" break; case 1298: /* argsExprList: argsExprList ',' expr */ #line 3447 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+","+(yyvsp[0].str); } #line 29009 "VParseBison.c" break; case 1299: /* argsExprListE: argsExprOneE */ #line 3451 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 29015 "VParseBison.c" break; case 1300: /* argsExprListE: argsExprListE ',' argsExprOneE */ #line 3452 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+","+(yyvsp[0].str); } #line 29021 "VParseBison.c" break; case 1301: /* pev_argsExprListE: pev_argsExprOneE */ #line 3456 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 29027 "VParseBison.c" break; case 1302: /* pev_argsExprListE: pev_argsExprListE ',' pev_argsExprOneE */ #line 3457 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+","+(yyvsp[0].str); } #line 29033 "VParseBison.c" break; case 1303: /* argsExprOneE: %empty */ #line 3461 "VParseBison.y" { (yyval.str) = ""; } #line 29039 "VParseBison.c" break; case 1304: /* argsExprOneE: expr */ #line 3462 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 29045 "VParseBison.c" break; case 1305: /* pev_argsExprOneE: %empty */ #line 3466 "VParseBison.y" { (yyval.str) = ""; } #line 29051 "VParseBison.c" break; case 1306: /* pev_argsExprOneE: pev_expr */ #line 3467 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 29057 "VParseBison.c" break; case 1307: /* argsDottedList: argsDotted */ #line 3471 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 29063 "VParseBison.c" break; case 1308: /* argsDottedList: argsDottedList ',' argsDotted */ #line 3472 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str)=(yyvsp[-2].str)+","+(yyvsp[0].str); } #line 29069 "VParseBison.c" break; case 1309: /* pev_argsDottedList: pev_argsDotted */ #line 3476 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 29075 "VParseBison.c" break; case 1310: /* pev_argsDottedList: pev_argsDottedList ',' pev_argsDotted */ #line 3477 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str)=(yyvsp[-2].str)+","+(yyvsp[0].str); } #line 29081 "VParseBison.c" break; case 1311: /* argsDotted: '.' idAny '(' ')' */ #line 3481 "VParseBison.y" { (yyval.fl)=(yyvsp[-3].fl); (yyval.str)=(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 29087 "VParseBison.c" break; case 1312: /* argsDotted: '.' idAny '(' expr ')' */ #line 3482 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str)=(yyvsp[-4].str)+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 29093 "VParseBison.c" break; case 1313: /* pev_argsDotted: '.' idAny '(' ')' */ #line 3486 "VParseBison.y" { (yyval.fl)=(yyvsp[-3].fl); (yyval.str)=(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 29099 "VParseBison.c" break; case 1314: /* pev_argsDotted: '.' idAny '(' pev_expr ')' */ #line 3487 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str)=(yyvsp[-4].str)+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 29105 "VParseBison.c" break; case 1315: /* streaming_concatenation: '{' "<<" stream_concOrExprOrType '}' */ #line 3498 "VParseBison.y" { (yyval.fl)=(yyvsp[-3].fl); (yyval.str)="{<<"+(yyvsp[-1].str)+"}"; } #line 29111 "VParseBison.c" break; case 1316: /* streaming_concatenation: '{' ">>" stream_concOrExprOrType '}' */ #line 3499 "VParseBison.y" { (yyval.fl)=(yyvsp[-3].fl); (yyval.str)="{>>"+(yyvsp[-1].str)+"}"; } #line 29117 "VParseBison.c" break; case 1317: /* streaming_concatenation: '{' "<<" stream_concOrExprOrType stream_concatenation '}' */ #line 3500 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str)="{<<"+(yyvsp[-2].str)+" "+(yyvsp[-1].str)+"}"; } #line 29123 "VParseBison.c" break; case 1318: /* streaming_concatenation: '{' ">>" stream_concOrExprOrType stream_concatenation '}' */ #line 3501 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str)="{>>"+(yyvsp[-2].str)+" "+(yyvsp[-1].str)+"}"; } #line 29129 "VParseBison.c" break; case 1319: /* stream_concOrExprOrType: cateList */ #line 3505 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 29135 "VParseBison.c" break; case 1320: /* stream_concOrExprOrType: simple_type */ #line 3506 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 29141 "VParseBison.c" break; case 1321: /* stream_concatenation: '{' stream_expressionList '}' */ #line 3513 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str)="{"+(yyvsp[-1].str)+"}"; } #line 29147 "VParseBison.c" break; case 1322: /* stream_expressionList: stream_expression */ #line 3517 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 29153 "VParseBison.c" break; case 1323: /* stream_expressionList: stream_expressionList ',' stream_expression */ #line 3518 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str)=(yyvsp[-2].str)+","+(yyvsp[0].str); } #line 29159 "VParseBison.c" break; case 1324: /* stream_expression: expr */ #line 3523 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 29165 "VParseBison.c" break; case 1325: /* stream_expression: expr "with-then-[" '[' expr ']' */ #line 3524 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str)=(yyvsp[-4].str); } #line 29171 "VParseBison.c" break; case 1326: /* stream_expression: expr "with-then-[" '[' expr ':' expr ']' */ #line 3525 "VParseBison.y" { (yyval.fl)=(yyvsp[-6].fl); (yyval.str)=(yyvsp[-6].str); } #line 29177 "VParseBison.c" break; case 1327: /* stream_expression: expr "with-then-[" '[' expr "+:" expr ']' */ #line 3526 "VParseBison.y" { (yyval.fl)=(yyvsp[-6].fl); (yyval.str)=(yyvsp[-6].str); } #line 29183 "VParseBison.c" break; case 1328: /* stream_expression: expr "with-then-[" '[' expr "-:" expr ']' */ #line 3527 "VParseBison.y" { (yyval.fl)=(yyvsp[-6].fl); (yyval.str)=(yyvsp[-6].str); } #line 29189 "VParseBison.c" break; case 1329: /* gateKwd: "GATE keyword" */ #line 3541 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); INSTPREP((yyvsp[0].str),0,0); } #line 29195 "VParseBison.c" break; case 1330: /* gateKwd: "and" */ #line 3542 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); INSTPREP((yyvsp[0].str),0,0); } #line 29201 "VParseBison.c" break; case 1331: /* gateKwd: "buf" */ #line 3543 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); INSTPREP((yyvsp[0].str),0,0); } #line 29207 "VParseBison.c" break; case 1332: /* gateKwd: "nand" */ #line 3544 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); INSTPREP((yyvsp[0].str),0,0); } #line 29213 "VParseBison.c" break; case 1333: /* gateKwd: "nor" */ #line 3545 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); INSTPREP((yyvsp[0].str),0,0); } #line 29219 "VParseBison.c" break; case 1334: /* gateKwd: "not" */ #line 3546 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); INSTPREP((yyvsp[0].str),0,0); } #line 29225 "VParseBison.c" break; case 1335: /* gateKwd: "or" */ #line 3547 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); INSTPREP((yyvsp[0].str),0,0); } #line 29231 "VParseBison.c" break; case 1336: /* gateKwd: "xnor" */ #line 3548 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); INSTPREP((yyvsp[0].str),0,0); } #line 29237 "VParseBison.c" break; case 1337: /* gateKwd: "xor" */ #line 3549 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); INSTPREP((yyvsp[0].str),0,0); } #line 29243 "VParseBison.c" break; case 1338: /* strength: "STRENGTH keyword (strong1/etc)" */ #line 3554 "VParseBison.y" { } #line 29249 "VParseBison.c" break; case 1339: /* strength: "supply0" */ #line 3555 "VParseBison.y" { } #line 29255 "VParseBison.c" break; case 1340: /* strength: "supply1" */ #line 3556 "VParseBison.y" { } #line 29261 "VParseBison.c" break; case 1341: /* strengthSpecE: %empty */ #line 3560 "VParseBison.y" { } #line 29267 "VParseBison.c" break; case 1342: /* strengthSpecE: strengthSpec */ #line 3561 "VParseBison.y" { } #line 29273 "VParseBison.c" break; case 1343: /* strengthSpec: "(-for-strength" strength ')' */ #line 3565 "VParseBison.y" { } #line 29279 "VParseBison.c" break; case 1344: /* strengthSpec: "(-for-strength" strength ',' strength ')' */ #line 3566 "VParseBison.y" { } #line 29285 "VParseBison.c" break; case 1345: /* combinational_body: "table" tableJunkList "endtable" */ #line 3573 "VParseBison.y" { } #line 29291 "VParseBison.c" break; case 1346: /* tableJunkList: tableJunk */ #line 3577 "VParseBison.y" { } #line 29297 "VParseBison.c" break; case 1347: /* tableJunkList: tableJunkList tableJunk */ #line 3578 "VParseBison.y" { } #line 29303 "VParseBison.c" break; case 1348: /* tableJunk: '!' */ #line 3582 "VParseBison.y" { } #line 29309 "VParseBison.c" break; case 1349: /* tableJunk: '#' */ #line 3582 "VParseBison.y" { } #line 29315 "VParseBison.c" break; case 1350: /* tableJunk: '%' */ #line 3582 "VParseBison.y" { } #line 29321 "VParseBison.c" break; case 1351: /* tableJunk: '&' */ #line 3582 "VParseBison.y" { } #line 29327 "VParseBison.c" break; case 1352: /* tableJunk: '(' */ #line 3582 "VParseBison.y" { } #line 29333 "VParseBison.c" break; case 1353: /* tableJunk: ')' */ #line 3582 "VParseBison.y" { } #line 29339 "VParseBison.c" break; case 1354: /* tableJunk: '*' */ #line 3582 "VParseBison.y" { } #line 29345 "VParseBison.c" break; case 1355: /* tableJunk: '+' */ #line 3582 "VParseBison.y" { } #line 29351 "VParseBison.c" break; case 1356: /* tableJunk: ',' */ #line 3582 "VParseBison.y" { } #line 29357 "VParseBison.c" break; case 1357: /* tableJunk: '-' */ #line 3582 "VParseBison.y" { } #line 29363 "VParseBison.c" break; case 1358: /* tableJunk: '.' */ #line 3582 "VParseBison.y" { } #line 29369 "VParseBison.c" break; case 1359: /* tableJunk: '/' */ #line 3582 "VParseBison.y" { } #line 29375 "VParseBison.c" break; case 1360: /* tableJunk: ':' */ #line 3582 "VParseBison.y" { } #line 29381 "VParseBison.c" break; case 1361: /* tableJunk: ';' */ #line 3582 "VParseBison.y" { } #line 29387 "VParseBison.c" break; case 1362: /* tableJunk: '<' */ #line 3582 "VParseBison.y" { } #line 29393 "VParseBison.c" break; case 1363: /* tableJunk: '=' */ #line 3582 "VParseBison.y" { } #line 29399 "VParseBison.c" break; case 1364: /* tableJunk: '>' */ #line 3582 "VParseBison.y" { } #line 29405 "VParseBison.c" break; case 1365: /* tableJunk: '?' */ #line 3582 "VParseBison.y" { } #line 29411 "VParseBison.c" break; case 1366: /* tableJunk: '@' */ #line 3582 "VParseBison.y" { } #line 29417 "VParseBison.c" break; case 1367: /* tableJunk: '[' */ #line 3582 "VParseBison.y" { } #line 29423 "VParseBison.c" break; case 1368: /* tableJunk: ']' */ #line 3582 "VParseBison.y" { } #line 29429 "VParseBison.c" break; case 1369: /* tableJunk: '^' */ #line 3582 "VParseBison.y" { } #line 29435 "VParseBison.c" break; case 1370: /* tableJunk: '{' */ #line 3582 "VParseBison.y" { } #line 29441 "VParseBison.c" break; case 1371: /* tableJunk: '|' */ #line 3582 "VParseBison.y" { } #line 29447 "VParseBison.c" break; case 1372: /* tableJunk: '}' */ #line 3582 "VParseBison.y" { } #line 29453 "VParseBison.c" break; case 1373: /* tableJunk: '~' */ #line 3582 "VParseBison.y" { } #line 29459 "VParseBison.c" break; case 1374: /* tableJunk: prEVENTBEGIN */ #line 3582 "VParseBison.y" { } #line 29465 "VParseBison.c" break; case 1375: /* tableJunk: prNEGATION */ #line 3582 "VParseBison.y" { } #line 29471 "VParseBison.c" break; case 1376: /* tableJunk: prREDUCTION */ #line 3582 "VParseBison.y" { } #line 29477 "VParseBison.c" break; case 1377: /* tableJunk: prTAGGED */ #line 3582 "VParseBison.y" { } #line 29483 "VParseBison.c" break; case 1378: /* tableJunk: prUNARYARITH */ #line 3582 "VParseBison.y" { } #line 29489 "VParseBison.c" break; case 1379: /* tableJunk: "accept_on" */ #line 3582 "VParseBison.y" { } #line 29495 "VParseBison.c" break; case 1380: /* tableJunk: "alias" */ #line 3582 "VParseBison.y" { } #line 29501 "VParseBison.c" break; case 1381: /* tableJunk: "always" */ #line 3582 "VParseBison.y" { } #line 29507 "VParseBison.c" break; case 1382: /* tableJunk: "and" */ #line 3582 "VParseBison.y" { } #line 29513 "VParseBison.c" break; case 1383: /* tableJunk: "assert" */ #line 3582 "VParseBison.y" { } #line 29519 "VParseBison.c" break; case 1384: /* tableJunk: "assign" */ #line 3582 "VParseBison.y" { } #line 29525 "VParseBison.c" break; case 1385: /* tableJunk: "assume" */ #line 3582 "VParseBison.y" { } #line 29531 "VParseBison.c" break; case 1386: /* tableJunk: "automatic" */ #line 3582 "VParseBison.y" { } #line 29537 "VParseBison.c" break; case 1387: /* tableJunk: "before" */ #line 3582 "VParseBison.y" { } #line 29543 "VParseBison.c" break; case 1388: /* tableJunk: "begin" */ #line 3582 "VParseBison.y" { } #line 29549 "VParseBison.c" break; case 1389: /* tableJunk: "bind" */ #line 3582 "VParseBison.y" { } #line 29555 "VParseBison.c" break; case 1390: /* tableJunk: "bins" */ #line 3582 "VParseBison.y" { } #line 29561 "VParseBison.c" break; case 1391: /* tableJunk: "binsof" */ #line 3582 "VParseBison.y" { } #line 29567 "VParseBison.c" break; case 1392: /* tableJunk: "bit" */ #line 3582 "VParseBison.y" { } #line 29573 "VParseBison.c" break; case 1393: /* tableJunk: "break" */ #line 3582 "VParseBison.y" { } #line 29579 "VParseBison.c" break; case 1394: /* tableJunk: "buf" */ #line 3582 "VParseBison.y" { } #line 29585 "VParseBison.c" break; case 1395: /* tableJunk: "byte" */ #line 3582 "VParseBison.y" { } #line 29591 "VParseBison.c" break; case 1396: /* tableJunk: "case" */ #line 3582 "VParseBison.y" { } #line 29597 "VParseBison.c" break; case 1397: /* tableJunk: "casex" */ #line 3582 "VParseBison.y" { } #line 29603 "VParseBison.c" break; case 1398: /* tableJunk: "casez" */ #line 3582 "VParseBison.y" { } #line 29609 "VParseBison.c" break; case 1399: /* tableJunk: "chandle" */ #line 3582 "VParseBison.y" { } #line 29615 "VParseBison.c" break; case 1400: /* tableJunk: "checker" */ #line 3582 "VParseBison.y" { } #line 29621 "VParseBison.c" break; case 1401: /* tableJunk: "class" */ #line 3582 "VParseBison.y" { } #line 29627 "VParseBison.c" break; case 1402: /* tableJunk: "clock" */ #line 3582 "VParseBison.y" { } #line 29633 "VParseBison.c" break; case 1403: /* tableJunk: "clocking" */ #line 3582 "VParseBison.y" { } #line 29639 "VParseBison.c" break; case 1404: /* tableJunk: "constraint" */ #line 3582 "VParseBison.y" { } #line 29645 "VParseBison.c" break; case 1405: /* tableJunk: "const" */ #line 3582 "VParseBison.y" { } #line 29651 "VParseBison.c" break; case 1406: /* tableJunk: "const-in-lex" */ #line 3582 "VParseBison.y" { } #line 29657 "VParseBison.c" break; case 1407: /* tableJunk: "const-then-local" */ #line 3582 "VParseBison.y" { } #line 29663 "VParseBison.c" break; case 1408: /* tableJunk: "const-then-ref" */ #line 3582 "VParseBison.y" { } #line 29669 "VParseBison.c" break; case 1409: /* tableJunk: "context" */ #line 3582 "VParseBison.y" { } #line 29675 "VParseBison.c" break; case 1410: /* tableJunk: "continue" */ #line 3582 "VParseBison.y" { } #line 29681 "VParseBison.c" break; case 1411: /* tableJunk: "cover" */ #line 3582 "VParseBison.y" { } #line 29687 "VParseBison.c" break; case 1412: /* tableJunk: "covergroup" */ #line 3582 "VParseBison.y" { } #line 29693 "VParseBison.c" break; case 1413: /* tableJunk: "coverpoint" */ #line 3582 "VParseBison.y" { } #line 29699 "VParseBison.c" break; case 1414: /* tableJunk: "cross" */ #line 3582 "VParseBison.y" { } #line 29705 "VParseBison.c" break; case 1415: /* tableJunk: "deassign" */ #line 3582 "VParseBison.y" { } #line 29711 "VParseBison.c" break; case 1416: /* tableJunk: "default" */ #line 3582 "VParseBison.y" { } #line 29717 "VParseBison.c" break; case 1417: /* tableJunk: "defparam" */ #line 3582 "VParseBison.y" { } #line 29723 "VParseBison.c" break; case 1418: /* tableJunk: "disable" */ #line 3582 "VParseBison.y" { } #line 29729 "VParseBison.c" break; case 1419: /* tableJunk: "dist" */ #line 3582 "VParseBison.y" { } #line 29735 "VParseBison.c" break; case 1420: /* tableJunk: "do" */ #line 3582 "VParseBison.y" { } #line 29741 "VParseBison.c" break; case 1421: /* tableJunk: "$error" */ #line 3582 "VParseBison.y" { } #line 29747 "VParseBison.c" break; case 1422: /* tableJunk: "$fatal" */ #line 3582 "VParseBison.y" { } #line 29753 "VParseBison.c" break; case 1423: /* tableJunk: "$info" */ #line 3582 "VParseBison.y" { } #line 29759 "VParseBison.c" break; case 1424: /* tableJunk: "$root" */ #line 3582 "VParseBison.y" { } #line 29765 "VParseBison.c" break; case 1425: /* tableJunk: "$unit" */ #line 3582 "VParseBison.y" { } #line 29771 "VParseBison.c" break; case 1426: /* tableJunk: "$warning" */ #line 3582 "VParseBison.y" { } #line 29777 "VParseBison.c" break; case 1427: /* tableJunk: "edge" */ #line 3582 "VParseBison.y" { } #line 29783 "VParseBison.c" break; case 1428: /* tableJunk: "else" */ #line 3582 "VParseBison.y" { } #line 29789 "VParseBison.c" break; case 1429: /* tableJunk: "end" */ #line 3582 "VParseBison.y" { } #line 29795 "VParseBison.c" break; case 1430: /* tableJunk: "endcase" */ #line 3582 "VParseBison.y" { } #line 29801 "VParseBison.c" break; case 1431: /* tableJunk: "endchecker" */ #line 3582 "VParseBison.y" { } #line 29807 "VParseBison.c" break; case 1432: /* tableJunk: "endclass" */ #line 3582 "VParseBison.y" { } #line 29813 "VParseBison.c" break; case 1433: /* tableJunk: "endclocking" */ #line 3582 "VParseBison.y" { } #line 29819 "VParseBison.c" break; case 1434: /* tableJunk: "endfunction" */ #line 3582 "VParseBison.y" { } #line 29825 "VParseBison.c" break; case 1435: /* tableJunk: "endgenerate" */ #line 3582 "VParseBison.y" { } #line 29831 "VParseBison.c" break; case 1436: /* tableJunk: "endgroup" */ #line 3582 "VParseBison.y" { } #line 29837 "VParseBison.c" break; case 1437: /* tableJunk: "endinterface" */ #line 3582 "VParseBison.y" { } #line 29843 "VParseBison.c" break; case 1438: /* tableJunk: "endmodule" */ #line 3582 "VParseBison.y" { } #line 29849 "VParseBison.c" break; case 1439: /* tableJunk: "endpackage" */ #line 3582 "VParseBison.y" { } #line 29855 "VParseBison.c" break; case 1440: /* tableJunk: "endprogram" */ #line 3582 "VParseBison.y" { } #line 29861 "VParseBison.c" break; case 1441: /* tableJunk: "endproperty" */ #line 3582 "VParseBison.y" { } #line 29867 "VParseBison.c" break; case 1442: /* tableJunk: "endsequence" */ #line 3582 "VParseBison.y" { } #line 29873 "VParseBison.c" break; case 1443: /* tableJunk: "endspecify" */ #line 3582 "VParseBison.y" { } #line 29879 "VParseBison.c" break; case 1444: /* tableJunk: "endtask" */ #line 3582 "VParseBison.y" { } #line 29885 "VParseBison.c" break; case 1445: /* tableJunk: "enum" */ #line 3582 "VParseBison.y" { } #line 29891 "VParseBison.c" break; case 1446: /* tableJunk: "event" */ #line 3582 "VParseBison.y" { } #line 29897 "VParseBison.c" break; case 1447: /* tableJunk: "eventually" */ #line 3582 "VParseBison.y" { } #line 29903 "VParseBison.c" break; case 1448: /* tableJunk: "expect" */ #line 3582 "VParseBison.y" { } #line 29909 "VParseBison.c" break; case 1449: /* tableJunk: "export" */ #line 3582 "VParseBison.y" { } #line 29915 "VParseBison.c" break; case 1450: /* tableJunk: "extends" */ #line 3582 "VParseBison.y" { } #line 29921 "VParseBison.c" break; case 1451: /* tableJunk: "extern" */ #line 3582 "VParseBison.y" { } #line 29927 "VParseBison.c" break; case 1452: /* tableJunk: "final" */ #line 3582 "VParseBison.y" { } #line 29933 "VParseBison.c" break; case 1453: /* tableJunk: "first_match" */ #line 3582 "VParseBison.y" { } #line 29939 "VParseBison.c" break; case 1454: /* tableJunk: "for" */ #line 3582 "VParseBison.y" { } #line 29945 "VParseBison.c" break; case 1455: /* tableJunk: "force" */ #line 3582 "VParseBison.y" { } #line 29951 "VParseBison.c" break; case 1456: /* tableJunk: "foreach" */ #line 3582 "VParseBison.y" { } #line 29957 "VParseBison.c" break; case 1457: /* tableJunk: "forever" */ #line 3582 "VParseBison.y" { } #line 29963 "VParseBison.c" break; case 1458: /* tableJunk: "fork" */ #line 3582 "VParseBison.y" { } #line 29969 "VParseBison.c" break; case 1459: /* tableJunk: "forkjoin" */ #line 3582 "VParseBison.y" { } #line 29975 "VParseBison.c" break; case 1460: /* tableJunk: "function" */ #line 3582 "VParseBison.y" { } #line 29981 "VParseBison.c" break; case 1461: /* tableJunk: "function-in-lex" */ #line 3582 "VParseBison.y" { } #line 29987 "VParseBison.c" break; case 1462: /* tableJunk: "function-is-pure-virtual" */ #line 3582 "VParseBison.y" { } #line 29993 "VParseBison.c" break; case 1463: /* tableJunk: "generate" */ #line 3582 "VParseBison.y" { } #line 29999 "VParseBison.c" break; case 1464: /* tableJunk: "genvar" */ #line 3582 "VParseBison.y" { } #line 30005 "VParseBison.c" break; case 1465: /* tableJunk: "global-then-clocking" */ #line 3582 "VParseBison.y" { } #line 30011 "VParseBison.c" break; case 1466: /* tableJunk: "global-in-lex" */ #line 3582 "VParseBison.y" { } #line 30017 "VParseBison.c" break; case 1467: /* tableJunk: "if" */ #line 3582 "VParseBison.y" { } #line 30023 "VParseBison.c" break; case 1468: /* tableJunk: "iff" */ #line 3582 "VParseBison.y" { } #line 30029 "VParseBison.c" break; case 1469: /* tableJunk: "ignore_bins" */ #line 3582 "VParseBison.y" { } #line 30035 "VParseBison.c" break; case 1470: /* tableJunk: "illegal_bins" */ #line 3582 "VParseBison.y" { } #line 30041 "VParseBison.c" break; case 1471: /* tableJunk: "implements" */ #line 3582 "VParseBison.y" { } #line 30047 "VParseBison.c" break; case 1472: /* tableJunk: "implies" */ #line 3582 "VParseBison.y" { } #line 30053 "VParseBison.c" break; case 1473: /* tableJunk: "import" */ #line 3582 "VParseBison.y" { } #line 30059 "VParseBison.c" break; case 1474: /* tableJunk: "initial" */ #line 3582 "VParseBison.y" { } #line 30065 "VParseBison.c" break; case 1475: /* tableJunk: "inout" */ #line 3582 "VParseBison.y" { } #line 30071 "VParseBison.c" break; case 1476: /* tableJunk: "input" */ #line 3582 "VParseBison.y" { } #line 30077 "VParseBison.c" break; case 1477: /* tableJunk: "inside" */ #line 3582 "VParseBison.y" { } #line 30083 "VParseBison.c" break; case 1478: /* tableJunk: "int" */ #line 3582 "VParseBison.y" { } #line 30089 "VParseBison.c" break; case 1479: /* tableJunk: "integer" */ #line 3582 "VParseBison.y" { } #line 30095 "VParseBison.c" break; case 1480: /* tableJunk: "interconnect" */ #line 3582 "VParseBison.y" { } #line 30101 "VParseBison.c" break; case 1481: /* tableJunk: "interface" */ #line 3582 "VParseBison.y" { } #line 30107 "VParseBison.c" break; case 1482: /* tableJunk: "intersect" */ #line 3582 "VParseBison.y" { } #line 30113 "VParseBison.c" break; case 1483: /* tableJunk: "join" */ #line 3582 "VParseBison.y" { } #line 30119 "VParseBison.c" break; case 1484: /* tableJunk: "let" */ #line 3582 "VParseBison.y" { } #line 30125 "VParseBison.c" break; case 1485: /* tableJunk: "localparam" */ #line 3582 "VParseBison.y" { } #line 30131 "VParseBison.c" break; case 1486: /* tableJunk: "local-then-::" */ #line 3582 "VParseBison.y" { } #line 30137 "VParseBison.c" break; case 1487: /* tableJunk: "local" */ #line 3582 "VParseBison.y" { } #line 30143 "VParseBison.c" break; case 1488: /* tableJunk: "local-in-lex" */ #line 3582 "VParseBison.y" { } #line 30149 "VParseBison.c" break; case 1489: /* tableJunk: "logic" */ #line 3582 "VParseBison.y" { } #line 30155 "VParseBison.c" break; case 1490: /* tableJunk: "longint" */ #line 3582 "VParseBison.y" { } #line 30161 "VParseBison.c" break; case 1491: /* tableJunk: "matches" */ #line 3582 "VParseBison.y" { } #line 30167 "VParseBison.c" break; case 1492: /* tableJunk: "modport" */ #line 3582 "VParseBison.y" { } #line 30173 "VParseBison.c" break; case 1493: /* tableJunk: "module" */ #line 3582 "VParseBison.y" { } #line 30179 "VParseBison.c" break; case 1494: /* tableJunk: "nand" */ #line 3582 "VParseBison.y" { } #line 30185 "VParseBison.c" break; case 1495: /* tableJunk: "negedge" */ #line 3582 "VParseBison.y" { } #line 30191 "VParseBison.c" break; case 1496: /* tableJunk: "nettype" */ #line 3582 "VParseBison.y" { } #line 30197 "VParseBison.c" break; case 1497: /* tableJunk: "new" */ #line 3582 "VParseBison.y" { } #line 30203 "VParseBison.c" break; case 1498: /* tableJunk: "new-in-lex" */ #line 3582 "VParseBison.y" { } #line 30209 "VParseBison.c" break; case 1499: /* tableJunk: "new-then-paren" */ #line 3582 "VParseBison.y" { } #line 30215 "VParseBison.c" break; case 1500: /* tableJunk: "nexttime" */ #line 3582 "VParseBison.y" { } #line 30221 "VParseBison.c" break; case 1501: /* tableJunk: "nor" */ #line 3582 "VParseBison.y" { } #line 30227 "VParseBison.c" break; case 1502: /* tableJunk: "not" */ #line 3582 "VParseBison.y" { } #line 30233 "VParseBison.c" break; case 1503: /* tableJunk: "null" */ #line 3582 "VParseBison.y" { } #line 30239 "VParseBison.c" break; case 1504: /* tableJunk: "or" */ #line 3582 "VParseBison.y" { } #line 30245 "VParseBison.c" break; case 1505: /* tableJunk: "output" */ #line 3582 "VParseBison.y" { } #line 30251 "VParseBison.c" break; case 1506: /* tableJunk: "package" */ #line 3582 "VParseBison.y" { } #line 30257 "VParseBison.c" break; case 1507: /* tableJunk: "packed" */ #line 3582 "VParseBison.y" { } #line 30263 "VParseBison.c" break; case 1508: /* tableJunk: "parameter" */ #line 3582 "VParseBison.y" { } #line 30269 "VParseBison.c" break; case 1509: /* tableJunk: "posedge" */ #line 3582 "VParseBison.y" { } #line 30275 "VParseBison.c" break; case 1510: /* tableJunk: "priority" */ #line 3582 "VParseBison.y" { } #line 30281 "VParseBison.c" break; case 1511: /* tableJunk: "program" */ #line 3582 "VParseBison.y" { } #line 30287 "VParseBison.c" break; case 1512: /* tableJunk: "property" */ #line 3582 "VParseBison.y" { } #line 30293 "VParseBison.c" break; case 1513: /* tableJunk: "protected" */ #line 3582 "VParseBison.y" { } #line 30299 "VParseBison.c" break; case 1514: /* tableJunk: "pure" */ #line 3582 "VParseBison.y" { } #line 30305 "VParseBison.c" break; case 1515: /* tableJunk: "&&" */ #line 3582 "VParseBison.y" { } #line 30311 "VParseBison.c" break; case 1516: /* tableJunk: "&&&" */ #line 3582 "VParseBison.y" { } #line 30317 "VParseBison.c" break; case 1517: /* tableJunk: "&=" */ #line 3582 "VParseBison.y" { } #line 30323 "VParseBison.c" break; case 1518: /* tableJunk: "*>" */ #line 3582 "VParseBison.y" { } #line 30329 "VParseBison.c" break; case 1519: /* tableJunk: "@@" */ #line 3582 "VParseBison.y" { } #line 30335 "VParseBison.c" break; case 1520: /* tableJunk: "[=" */ #line 3582 "VParseBison.y" { } #line 30341 "VParseBison.c" break; case 1521: /* tableJunk: "[->" */ #line 3582 "VParseBison.y" { } #line 30347 "VParseBison.c" break; case 1522: /* tableJunk: "[+]" */ #line 3582 "VParseBison.y" { } #line 30353 "VParseBison.c" break; case 1523: /* tableJunk: "[*" */ #line 3582 "VParseBison.y" { } #line 30359 "VParseBison.c" break; case 1524: /* tableJunk: "===" */ #line 3582 "VParseBison.y" { } #line 30365 "VParseBison.c" break; case 1525: /* tableJunk: "!==" */ #line 3582 "VParseBison.y" { } #line 30371 "VParseBison.c" break; case 1526: /* tableJunk: "::" */ #line 3582 "VParseBison.y" { } #line 30377 "VParseBison.c" break; case 1527: /* tableJunk: ":/" */ #line 3582 "VParseBison.y" { } #line 30383 "VParseBison.c" break; case 1528: /* tableJunk: ":=" */ #line 3582 "VParseBison.y" { } #line 30389 "VParseBison.c" break; case 1529: /* tableJunk: "/=" */ #line 3582 "VParseBison.y" { } #line 30395 "VParseBison.c" break; case 1530: /* tableJunk: ".*" */ #line 3582 "VParseBison.y" { } #line 30401 "VParseBison.c" break; case 1531: /* tableJunk: "=>" */ #line 3582 "VParseBison.y" { } #line 30407 "VParseBison.c" break; case 1532: /* tableJunk: "==" */ #line 3582 "VParseBison.y" { } #line 30413 "VParseBison.c" break; case 1533: /* tableJunk: ">=" */ #line 3582 "VParseBison.y" { } #line 30419 "VParseBison.c" break; case 1534: /* tableJunk: "<=" */ #line 3582 "VParseBison.y" { } #line 30425 "VParseBison.c" break; case 1535: /* tableJunk: "<=-ignored" */ #line 3582 "VParseBison.y" { } #line 30431 "VParseBison.c" break; case 1536: /* tableJunk: "<->" */ #line 3582 "VParseBison.y" { } #line 30437 "VParseBison.c" break; case 1537: /* tableJunk: "-:" */ #line 3582 "VParseBison.y" { } #line 30443 "VParseBison.c" break; case 1538: /* tableJunk: "-=" */ #line 3582 "VParseBison.y" { } #line 30449 "VParseBison.c" break; case 1539: /* tableJunk: "->" */ #line 3582 "VParseBison.y" { } #line 30455 "VParseBison.c" break; case 1540: /* tableJunk: "->>" */ #line 3582 "VParseBison.y" { } #line 30461 "VParseBison.c" break; case 1541: /* tableJunk: "--" */ #line 3582 "VParseBison.y" { } #line 30467 "VParseBison.c" break; case 1542: /* tableJunk: "%=" */ #line 3582 "VParseBison.y" { } #line 30473 "VParseBison.c" break; case 1543: /* tableJunk: "~&" */ #line 3582 "VParseBison.y" { } #line 30479 "VParseBison.c" break; case 1544: /* tableJunk: "~|" */ #line 3582 "VParseBison.y" { } #line 30485 "VParseBison.c" break; case 1545: /* tableJunk: "!=" */ #line 3582 "VParseBison.y" { } #line 30491 "VParseBison.c" break; case 1546: /* tableJunk: "|=" */ #line 3582 "VParseBison.y" { } #line 30497 "VParseBison.c" break; case 1547: /* tableJunk: "|=>" */ #line 3582 "VParseBison.y" { } #line 30503 "VParseBison.c" break; case 1548: /* tableJunk: "|->" */ #line 3582 "VParseBison.y" { } #line 30509 "VParseBison.c" break; case 1549: /* tableJunk: "||" */ #line 3582 "VParseBison.y" { } #line 30515 "VParseBison.c" break; case 1550: /* tableJunk: "(-ignored" */ #line 3582 "VParseBison.y" { } #line 30521 "VParseBison.c" break; case 1551: /* tableJunk: "(-for-strength" */ #line 3582 "VParseBison.y" { } #line 30527 "VParseBison.c" break; case 1552: /* tableJunk: "+:" */ #line 3582 "VParseBison.y" { } #line 30533 "VParseBison.c" break; case 1553: /* tableJunk: "+=" */ #line 3582 "VParseBison.y" { } #line 30539 "VParseBison.c" break; case 1554: /* tableJunk: "++" */ #line 3582 "VParseBison.y" { } #line 30545 "VParseBison.c" break; case 1555: /* tableJunk: "#=#" */ #line 3582 "VParseBison.y" { } #line 30551 "VParseBison.c" break; case 1556: /* tableJunk: "#-#" */ #line 3582 "VParseBison.y" { } #line 30557 "VParseBison.c" break; case 1557: /* tableJunk: "##" */ #line 3582 "VParseBison.y" { } #line 30563 "VParseBison.c" break; case 1558: /* tableJunk: "**" */ #line 3582 "VParseBison.y" { } #line 30569 "VParseBison.c" break; case 1559: /* tableJunk: "<<" */ #line 3582 "VParseBison.y" { } #line 30575 "VParseBison.c" break; case 1560: /* tableJunk: "<<=" */ #line 3582 "VParseBison.y" { } #line 30581 "VParseBison.c" break; case 1561: /* tableJunk: ">>" */ #line 3582 "VParseBison.y" { } #line 30587 "VParseBison.c" break; case 1562: /* tableJunk: ">>=" */ #line 3582 "VParseBison.y" { } #line 30593 "VParseBison.c" break; case 1563: /* tableJunk: ">>>" */ #line 3582 "VParseBison.y" { } #line 30599 "VParseBison.c" break; case 1564: /* tableJunk: ">>>=" */ #line 3582 "VParseBison.y" { } #line 30605 "VParseBison.c" break; case 1565: /* tableJunk: "'" */ #line 3582 "VParseBison.y" { } #line 30611 "VParseBison.c" break; case 1566: /* tableJunk: "'{" */ #line 3582 "VParseBison.y" { } #line 30617 "VParseBison.c" break; case 1567: /* tableJunk: "*=" */ #line 3582 "VParseBison.y" { } #line 30623 "VParseBison.c" break; case 1568: /* tableJunk: "==?" */ #line 3582 "VParseBison.y" { } #line 30629 "VParseBison.c" break; case 1569: /* tableJunk: "!=?" */ #line 3582 "VParseBison.y" { } #line 30635 "VParseBison.c" break; case 1570: /* tableJunk: "^~" */ #line 3582 "VParseBison.y" { } #line 30641 "VParseBison.c" break; case 1571: /* tableJunk: "^=" */ #line 3582 "VParseBison.y" { } #line 30647 "VParseBison.c" break; case 1572: /* tableJunk: "rand" */ #line 3582 "VParseBison.y" { } #line 30653 "VParseBison.c" break; case 1573: /* tableJunk: "randc" */ #line 3582 "VParseBison.y" { } #line 30659 "VParseBison.c" break; case 1574: /* tableJunk: "randcase" */ #line 3582 "VParseBison.y" { } #line 30665 "VParseBison.c" break; case 1575: /* tableJunk: "randsequence" */ #line 3582 "VParseBison.y" { } #line 30671 "VParseBison.c" break; case 1576: /* tableJunk: "real" */ #line 3582 "VParseBison.y" { } #line 30677 "VParseBison.c" break; case 1577: /* tableJunk: "realtime" */ #line 3582 "VParseBison.y" { } #line 30683 "VParseBison.c" break; case 1578: /* tableJunk: "ref" */ #line 3582 "VParseBison.y" { } #line 30689 "VParseBison.c" break; case 1579: /* tableJunk: "reg" */ #line 3582 "VParseBison.y" { } #line 30695 "VParseBison.c" break; case 1580: /* tableJunk: "reject_on" */ #line 3582 "VParseBison.y" { } #line 30701 "VParseBison.c" break; case 1581: /* tableJunk: "release" */ #line 3582 "VParseBison.y" { } #line 30707 "VParseBison.c" break; case 1582: /* tableJunk: "repeat" */ #line 3582 "VParseBison.y" { } #line 30713 "VParseBison.c" break; case 1583: /* tableJunk: "restrict" */ #line 3582 "VParseBison.y" { } #line 30719 "VParseBison.c" break; case 1584: /* tableJunk: "return" */ #line 3582 "VParseBison.y" { } #line 30725 "VParseBison.c" break; case 1585: /* tableJunk: "scalared" */ #line 3582 "VParseBison.y" { } #line 30731 "VParseBison.c" break; case 1586: /* tableJunk: "sequence" */ #line 3582 "VParseBison.y" { } #line 30737 "VParseBison.c" break; case 1587: /* tableJunk: "shortint" */ #line 3582 "VParseBison.y" { } #line 30743 "VParseBison.c" break; case 1588: /* tableJunk: "shortreal" */ #line 3582 "VParseBison.y" { } #line 30749 "VParseBison.c" break; case 1589: /* tableJunk: "signed" */ #line 3582 "VParseBison.y" { } #line 30755 "VParseBison.c" break; case 1590: /* tableJunk: "soft" */ #line 3582 "VParseBison.y" { } #line 30761 "VParseBison.c" break; case 1591: /* tableJunk: "solve" */ #line 3582 "VParseBison.y" { } #line 30767 "VParseBison.c" break; case 1592: /* tableJunk: "specify" */ #line 3582 "VParseBison.y" { } #line 30773 "VParseBison.c" break; case 1593: /* tableJunk: "specparam" */ #line 3582 "VParseBison.y" { } #line 30779 "VParseBison.c" break; case 1594: /* tableJunk: "static-then-constraint" */ #line 3582 "VParseBison.y" { } #line 30785 "VParseBison.c" break; case 1595: /* tableJunk: "static" */ #line 3582 "VParseBison.y" { } #line 30791 "VParseBison.c" break; case 1596: /* tableJunk: "static-in-lex" */ #line 3582 "VParseBison.y" { } #line 30797 "VParseBison.c" break; case 1597: /* tableJunk: "string" */ #line 3582 "VParseBison.y" { } #line 30803 "VParseBison.c" break; case 1598: /* tableJunk: "strong" */ #line 3582 "VParseBison.y" { } #line 30809 "VParseBison.c" break; case 1599: /* tableJunk: "struct" */ #line 3582 "VParseBison.y" { } #line 30815 "VParseBison.c" break; case 1600: /* tableJunk: "super" */ #line 3582 "VParseBison.y" { } #line 30821 "VParseBison.c" break; case 1601: /* tableJunk: "supply0" */ #line 3582 "VParseBison.y" { } #line 30827 "VParseBison.c" break; case 1602: /* tableJunk: "supply1" */ #line 3582 "VParseBison.y" { } #line 30833 "VParseBison.c" break; case 1603: /* tableJunk: "sync_accept_on" */ #line 3582 "VParseBison.y" { } #line 30839 "VParseBison.c" break; case 1604: /* tableJunk: "sync_reject_on" */ #line 3582 "VParseBison.y" { } #line 30845 "VParseBison.c" break; case 1605: /* tableJunk: "s_always" */ #line 3582 "VParseBison.y" { } #line 30851 "VParseBison.c" break; case 1606: /* tableJunk: "s_eventually" */ #line 3582 "VParseBison.y" { } #line 30857 "VParseBison.c" break; case 1607: /* tableJunk: "s_nexttime" */ #line 3582 "VParseBison.y" { } #line 30863 "VParseBison.c" break; case 1608: /* tableJunk: "s_until" */ #line 3582 "VParseBison.y" { } #line 30869 "VParseBison.c" break; case 1609: /* tableJunk: "s_until_with" */ #line 3582 "VParseBison.y" { } #line 30875 "VParseBison.c" break; case 1610: /* tableJunk: "tagged" */ #line 3582 "VParseBison.y" { } #line 30881 "VParseBison.c" break; case 1611: /* tableJunk: "task" */ #line 3582 "VParseBison.y" { } #line 30887 "VParseBison.c" break; case 1612: /* tableJunk: "task-in-lex" */ #line 3582 "VParseBison.y" { } #line 30893 "VParseBison.c" break; case 1613: /* tableJunk: "task-is-pure-virtual" */ #line 3582 "VParseBison.y" { } #line 30899 "VParseBison.c" break; case 1614: /* tableJunk: "this" */ #line 3582 "VParseBison.y" { } #line 30905 "VParseBison.c" break; case 1615: /* tableJunk: "throughout" */ #line 3582 "VParseBison.y" { } #line 30911 "VParseBison.c" break; case 1616: /* tableJunk: "time" */ #line 3582 "VParseBison.y" { } #line 30917 "VParseBison.c" break; case 1617: /* tableJunk: "timeprecision" */ #line 3582 "VParseBison.y" { } #line 30923 "VParseBison.c" break; case 1618: /* tableJunk: "timeunit" */ #line 3582 "VParseBison.y" { } #line 30929 "VParseBison.c" break; case 1619: /* tableJunk: "tri" */ #line 3582 "VParseBison.y" { } #line 30935 "VParseBison.c" break; case 1620: /* tableJunk: "tri0" */ #line 3582 "VParseBison.y" { } #line 30941 "VParseBison.c" break; case 1621: /* tableJunk: "tri1" */ #line 3582 "VParseBison.y" { } #line 30947 "VParseBison.c" break; case 1622: /* tableJunk: "triand" */ #line 3582 "VParseBison.y" { } #line 30953 "VParseBison.c" break; case 1623: /* tableJunk: "trior" */ #line 3582 "VParseBison.y" { } #line 30959 "VParseBison.c" break; case 1624: /* tableJunk: "trireg" */ #line 3582 "VParseBison.y" { } #line 30965 "VParseBison.c" break; case 1625: /* tableJunk: "type" */ #line 3582 "VParseBison.y" { } #line 30971 "VParseBison.c" break; case 1626: /* tableJunk: "typedef" */ #line 3582 "VParseBison.y" { } #line 30977 "VParseBison.c" break; case 1627: /* tableJunk: "union" */ #line 3582 "VParseBison.y" { } #line 30983 "VParseBison.c" break; case 1628: /* tableJunk: "unique" */ #line 3582 "VParseBison.y" { } #line 30989 "VParseBison.c" break; case 1629: /* tableJunk: "unique0" */ #line 3582 "VParseBison.y" { } #line 30995 "VParseBison.c" break; case 1630: /* tableJunk: "unsigned" */ #line 3582 "VParseBison.y" { } #line 31001 "VParseBison.c" break; case 1631: /* tableJunk: "until" */ #line 3582 "VParseBison.y" { } #line 31007 "VParseBison.c" break; case 1632: /* tableJunk: "until_with" */ #line 3582 "VParseBison.y" { } #line 31013 "VParseBison.c" break; case 1633: /* tableJunk: "untyped" */ #line 3582 "VParseBison.y" { } #line 31019 "VParseBison.c" break; case 1634: /* tableJunk: "var" */ #line 3582 "VParseBison.y" { } #line 31025 "VParseBison.c" break; case 1635: /* tableJunk: "vectored" */ #line 3582 "VParseBison.y" { } #line 31031 "VParseBison.c" break; case 1636: /* tableJunk: "virtual-then-class" */ #line 3582 "VParseBison.y" { } #line 31037 "VParseBison.c" break; case 1637: /* tableJunk: "virtual" */ #line 3582 "VParseBison.y" { } #line 31043 "VParseBison.c" break; case 1638: /* tableJunk: "virtual-then-interface" */ #line 3582 "VParseBison.y" { } #line 31049 "VParseBison.c" break; case 1639: /* tableJunk: "virtual-in-lex" */ #line 3582 "VParseBison.y" { } #line 31055 "VParseBison.c" break; case 1640: /* tableJunk: "virtual-then-identifier" */ #line 3582 "VParseBison.y" { } #line 31061 "VParseBison.c" break; case 1641: /* tableJunk: "void" */ #line 3582 "VParseBison.y" { } #line 31067 "VParseBison.c" break; case 1642: /* tableJunk: "wait" */ #line 3582 "VParseBison.y" { } #line 31073 "VParseBison.c" break; case 1643: /* tableJunk: "wait_order" */ #line 3582 "VParseBison.y" { } #line 31079 "VParseBison.c" break; case 1644: /* tableJunk: "wand" */ #line 3582 "VParseBison.y" { } #line 31085 "VParseBison.c" break; case 1645: /* tableJunk: "weak" */ #line 3582 "VParseBison.y" { } #line 31091 "VParseBison.c" break; case 1646: /* tableJunk: "while" */ #line 3582 "VParseBison.y" { } #line 31097 "VParseBison.c" break; case 1647: /* tableJunk: "wildcard" */ #line 3582 "VParseBison.y" { } #line 31103 "VParseBison.c" break; case 1648: /* tableJunk: "wire" */ #line 3582 "VParseBison.y" { } #line 31109 "VParseBison.c" break; case 1649: /* tableJunk: "within" */ #line 3582 "VParseBison.y" { } #line 31115 "VParseBison.c" break; case 1650: /* tableJunk: "with-then-[" */ #line 3582 "VParseBison.y" { } #line 31121 "VParseBison.c" break; case 1651: /* tableJunk: "with-then-{" */ #line 3582 "VParseBison.y" { } #line 31127 "VParseBison.c" break; case 1652: /* tableJunk: "with" */ #line 3582 "VParseBison.y" { } #line 31133 "VParseBison.c" break; case 1653: /* tableJunk: "with-in-lex" */ #line 3582 "VParseBison.y" { } #line 31139 "VParseBison.c" break; case 1654: /* tableJunk: "with-then-(" */ #line 3582 "VParseBison.y" { } #line 31145 "VParseBison.c" break; case 1655: /* tableJunk: "wor" */ #line 3582 "VParseBison.y" { } #line 31151 "VParseBison.c" break; case 1656: /* tableJunk: "xnor" */ #line 3582 "VParseBison.y" { } #line 31157 "VParseBison.c" break; case 1657: /* tableJunk: "xor" */ #line 3582 "VParseBison.y" { } #line 31163 "VParseBison.c" break; case 1658: /* tableJunk: "FLOATING-POINT NUMBER" */ #line 3582 "VParseBison.y" { } #line 31169 "VParseBison.c" break; case 1659: /* tableJunk: "IDENTIFIER" */ #line 3582 "VParseBison.y" { } #line 31175 "VParseBison.c" break; case 1660: /* tableJunk: "IDENTIFIER-in-lex" */ #line 3582 "VParseBison.y" { } #line 31181 "VParseBison.c" break; case 1661: /* tableJunk: "PACKAGE-IDENTIFIER" */ #line 3582 "VParseBison.y" { } #line 31187 "VParseBison.c" break; case 1662: /* tableJunk: "TYPE-IDENTIFIER" */ #line 3582 "VParseBison.y" { } #line 31193 "VParseBison.c" break; case 1663: /* tableJunk: "INTEGER NUMBER" */ #line 3582 "VParseBison.y" { } #line 31199 "VParseBison.c" break; case 1664: /* tableJunk: "STRING" */ #line 3582 "VParseBison.y" { } #line 31205 "VParseBison.c" break; case 1665: /* tableJunk: "STRING-ignored" */ #line 3582 "VParseBison.y" { } #line 31211 "VParseBison.c" break; case 1666: /* tableJunk: "TIME NUMBER" */ #line 3582 "VParseBison.y" { } #line 31217 "VParseBison.c" break; case 1667: /* tableJunk: "TIMING SPEC ELEMENT" */ #line 3582 "VParseBison.y" { } #line 31223 "VParseBison.c" break; case 1668: /* tableJunk: "CONFIG keyword (cell/use/design/etc)" */ #line 3582 "VParseBison.y" { } #line 31229 "VParseBison.c" break; case 1669: /* tableJunk: "GATE keyword" */ #line 3582 "VParseBison.y" { } #line 31235 "VParseBison.c" break; case 1670: /* tableJunk: "OPERATOR" */ #line 3582 "VParseBison.y" { } #line 31241 "VParseBison.c" break; case 1671: /* tableJunk: "STRENGTH keyword (strong1/etc)" */ #line 3582 "VParseBison.y" { } #line 31247 "VParseBison.c" break; case 1672: /* tableJunk: "SYSCALL" */ #line 3582 "VParseBison.y" { } #line 31253 "VParseBison.c" break; case 1673: /* tableJunk: "table" tableJunk "endtable" */ #line 3583 "VParseBison.y" { } #line 31259 "VParseBison.c" break; case 1674: /* tableJunk: error */ #line 3584 "VParseBison.y" {} #line 31265 "VParseBison.c" break; case 1675: /* specify_block: "specify" specifyJunkList "endspecify" */ #line 3591 "VParseBison.y" { } #line 31271 "VParseBison.c" break; case 1676: /* specify_block: "specify" "endspecify" */ #line 3592 "VParseBison.y" { } #line 31277 "VParseBison.c" break; case 1677: /* specifyJunkList: specifyJunk */ #line 3596 "VParseBison.y" { } #line 31283 "VParseBison.c" break; case 1678: /* specifyJunkList: specifyJunkList specifyJunk */ #line 3597 "VParseBison.y" { } #line 31289 "VParseBison.c" break; case 1679: /* specifyJunk: '!' */ #line 3601 "VParseBison.y" { } #line 31295 "VParseBison.c" break; case 1680: /* specifyJunk: '#' */ #line 3601 "VParseBison.y" { } #line 31301 "VParseBison.c" break; case 1681: /* specifyJunk: '%' */ #line 3601 "VParseBison.y" { } #line 31307 "VParseBison.c" break; case 1682: /* specifyJunk: '&' */ #line 3601 "VParseBison.y" { } #line 31313 "VParseBison.c" break; case 1683: /* specifyJunk: '(' */ #line 3601 "VParseBison.y" { } #line 31319 "VParseBison.c" break; case 1684: /* specifyJunk: ')' */ #line 3601 "VParseBison.y" { } #line 31325 "VParseBison.c" break; case 1685: /* specifyJunk: '*' */ #line 3601 "VParseBison.y" { } #line 31331 "VParseBison.c" break; case 1686: /* specifyJunk: '+' */ #line 3601 "VParseBison.y" { } #line 31337 "VParseBison.c" break; case 1687: /* specifyJunk: ',' */ #line 3601 "VParseBison.y" { } #line 31343 "VParseBison.c" break; case 1688: /* specifyJunk: '-' */ #line 3601 "VParseBison.y" { } #line 31349 "VParseBison.c" break; case 1689: /* specifyJunk: '.' */ #line 3601 "VParseBison.y" { } #line 31355 "VParseBison.c" break; case 1690: /* specifyJunk: '/' */ #line 3601 "VParseBison.y" { } #line 31361 "VParseBison.c" break; case 1691: /* specifyJunk: ':' */ #line 3601 "VParseBison.y" { } #line 31367 "VParseBison.c" break; case 1692: /* specifyJunk: ';' */ #line 3601 "VParseBison.y" { } #line 31373 "VParseBison.c" break; case 1693: /* specifyJunk: '<' */ #line 3601 "VParseBison.y" { } #line 31379 "VParseBison.c" break; case 1694: /* specifyJunk: '=' */ #line 3601 "VParseBison.y" { } #line 31385 "VParseBison.c" break; case 1695: /* specifyJunk: '>' */ #line 3601 "VParseBison.y" { } #line 31391 "VParseBison.c" break; case 1696: /* specifyJunk: '?' */ #line 3601 "VParseBison.y" { } #line 31397 "VParseBison.c" break; case 1697: /* specifyJunk: '@' */ #line 3601 "VParseBison.y" { } #line 31403 "VParseBison.c" break; case 1698: /* specifyJunk: '[' */ #line 3601 "VParseBison.y" { } #line 31409 "VParseBison.c" break; case 1699: /* specifyJunk: ']' */ #line 3601 "VParseBison.y" { } #line 31415 "VParseBison.c" break; case 1700: /* specifyJunk: '^' */ #line 3601 "VParseBison.y" { } #line 31421 "VParseBison.c" break; case 1701: /* specifyJunk: '{' */ #line 3601 "VParseBison.y" { } #line 31427 "VParseBison.c" break; case 1702: /* specifyJunk: '|' */ #line 3601 "VParseBison.y" { } #line 31433 "VParseBison.c" break; case 1703: /* specifyJunk: '}' */ #line 3601 "VParseBison.y" { } #line 31439 "VParseBison.c" break; case 1704: /* specifyJunk: '~' */ #line 3601 "VParseBison.y" { } #line 31445 "VParseBison.c" break; case 1705: /* specifyJunk: prEVENTBEGIN */ #line 3601 "VParseBison.y" { } #line 31451 "VParseBison.c" break; case 1706: /* specifyJunk: prNEGATION */ #line 3601 "VParseBison.y" { } #line 31457 "VParseBison.c" break; case 1707: /* specifyJunk: prREDUCTION */ #line 3601 "VParseBison.y" { } #line 31463 "VParseBison.c" break; case 1708: /* specifyJunk: prTAGGED */ #line 3601 "VParseBison.y" { } #line 31469 "VParseBison.c" break; case 1709: /* specifyJunk: prUNARYARITH */ #line 3601 "VParseBison.y" { } #line 31475 "VParseBison.c" break; case 1710: /* specifyJunk: "accept_on" */ #line 3601 "VParseBison.y" { } #line 31481 "VParseBison.c" break; case 1711: /* specifyJunk: "alias" */ #line 3601 "VParseBison.y" { } #line 31487 "VParseBison.c" break; case 1712: /* specifyJunk: "always" */ #line 3601 "VParseBison.y" { } #line 31493 "VParseBison.c" break; case 1713: /* specifyJunk: "and" */ #line 3601 "VParseBison.y" { } #line 31499 "VParseBison.c" break; case 1714: /* specifyJunk: "assert" */ #line 3601 "VParseBison.y" { } #line 31505 "VParseBison.c" break; case 1715: /* specifyJunk: "assign" */ #line 3601 "VParseBison.y" { } #line 31511 "VParseBison.c" break; case 1716: /* specifyJunk: "assume" */ #line 3601 "VParseBison.y" { } #line 31517 "VParseBison.c" break; case 1717: /* specifyJunk: "automatic" */ #line 3601 "VParseBison.y" { } #line 31523 "VParseBison.c" break; case 1718: /* specifyJunk: "before" */ #line 3601 "VParseBison.y" { } #line 31529 "VParseBison.c" break; case 1719: /* specifyJunk: "begin" */ #line 3601 "VParseBison.y" { } #line 31535 "VParseBison.c" break; case 1720: /* specifyJunk: "bind" */ #line 3601 "VParseBison.y" { } #line 31541 "VParseBison.c" break; case 1721: /* specifyJunk: "bins" */ #line 3601 "VParseBison.y" { } #line 31547 "VParseBison.c" break; case 1722: /* specifyJunk: "binsof" */ #line 3601 "VParseBison.y" { } #line 31553 "VParseBison.c" break; case 1723: /* specifyJunk: "bit" */ #line 3601 "VParseBison.y" { } #line 31559 "VParseBison.c" break; case 1724: /* specifyJunk: "break" */ #line 3601 "VParseBison.y" { } #line 31565 "VParseBison.c" break; case 1725: /* specifyJunk: "buf" */ #line 3601 "VParseBison.y" { } #line 31571 "VParseBison.c" break; case 1726: /* specifyJunk: "byte" */ #line 3601 "VParseBison.y" { } #line 31577 "VParseBison.c" break; case 1727: /* specifyJunk: "case" */ #line 3601 "VParseBison.y" { } #line 31583 "VParseBison.c" break; case 1728: /* specifyJunk: "casex" */ #line 3601 "VParseBison.y" { } #line 31589 "VParseBison.c" break; case 1729: /* specifyJunk: "casez" */ #line 3601 "VParseBison.y" { } #line 31595 "VParseBison.c" break; case 1730: /* specifyJunk: "chandle" */ #line 3601 "VParseBison.y" { } #line 31601 "VParseBison.c" break; case 1731: /* specifyJunk: "checker" */ #line 3601 "VParseBison.y" { } #line 31607 "VParseBison.c" break; case 1732: /* specifyJunk: "class" */ #line 3601 "VParseBison.y" { } #line 31613 "VParseBison.c" break; case 1733: /* specifyJunk: "clock" */ #line 3601 "VParseBison.y" { } #line 31619 "VParseBison.c" break; case 1734: /* specifyJunk: "clocking" */ #line 3601 "VParseBison.y" { } #line 31625 "VParseBison.c" break; case 1735: /* specifyJunk: "constraint" */ #line 3601 "VParseBison.y" { } #line 31631 "VParseBison.c" break; case 1736: /* specifyJunk: "const" */ #line 3601 "VParseBison.y" { } #line 31637 "VParseBison.c" break; case 1737: /* specifyJunk: "const-in-lex" */ #line 3601 "VParseBison.y" { } #line 31643 "VParseBison.c" break; case 1738: /* specifyJunk: "const-then-local" */ #line 3601 "VParseBison.y" { } #line 31649 "VParseBison.c" break; case 1739: /* specifyJunk: "const-then-ref" */ #line 3601 "VParseBison.y" { } #line 31655 "VParseBison.c" break; case 1740: /* specifyJunk: "context" */ #line 3601 "VParseBison.y" { } #line 31661 "VParseBison.c" break; case 1741: /* specifyJunk: "continue" */ #line 3601 "VParseBison.y" { } #line 31667 "VParseBison.c" break; case 1742: /* specifyJunk: "cover" */ #line 3601 "VParseBison.y" { } #line 31673 "VParseBison.c" break; case 1743: /* specifyJunk: "covergroup" */ #line 3601 "VParseBison.y" { } #line 31679 "VParseBison.c" break; case 1744: /* specifyJunk: "coverpoint" */ #line 3601 "VParseBison.y" { } #line 31685 "VParseBison.c" break; case 1745: /* specifyJunk: "cross" */ #line 3601 "VParseBison.y" { } #line 31691 "VParseBison.c" break; case 1746: /* specifyJunk: "deassign" */ #line 3601 "VParseBison.y" { } #line 31697 "VParseBison.c" break; case 1747: /* specifyJunk: "default" */ #line 3601 "VParseBison.y" { } #line 31703 "VParseBison.c" break; case 1748: /* specifyJunk: "defparam" */ #line 3601 "VParseBison.y" { } #line 31709 "VParseBison.c" break; case 1749: /* specifyJunk: "disable" */ #line 3601 "VParseBison.y" { } #line 31715 "VParseBison.c" break; case 1750: /* specifyJunk: "dist" */ #line 3601 "VParseBison.y" { } #line 31721 "VParseBison.c" break; case 1751: /* specifyJunk: "do" */ #line 3601 "VParseBison.y" { } #line 31727 "VParseBison.c" break; case 1752: /* specifyJunk: "$error" */ #line 3601 "VParseBison.y" { } #line 31733 "VParseBison.c" break; case 1753: /* specifyJunk: "$fatal" */ #line 3601 "VParseBison.y" { } #line 31739 "VParseBison.c" break; case 1754: /* specifyJunk: "$info" */ #line 3601 "VParseBison.y" { } #line 31745 "VParseBison.c" break; case 1755: /* specifyJunk: "$root" */ #line 3601 "VParseBison.y" { } #line 31751 "VParseBison.c" break; case 1756: /* specifyJunk: "$unit" */ #line 3601 "VParseBison.y" { } #line 31757 "VParseBison.c" break; case 1757: /* specifyJunk: "$warning" */ #line 3601 "VParseBison.y" { } #line 31763 "VParseBison.c" break; case 1758: /* specifyJunk: "edge" */ #line 3601 "VParseBison.y" { } #line 31769 "VParseBison.c" break; case 1759: /* specifyJunk: "else" */ #line 3601 "VParseBison.y" { } #line 31775 "VParseBison.c" break; case 1760: /* specifyJunk: "end" */ #line 3601 "VParseBison.y" { } #line 31781 "VParseBison.c" break; case 1761: /* specifyJunk: "endcase" */ #line 3601 "VParseBison.y" { } #line 31787 "VParseBison.c" break; case 1762: /* specifyJunk: "endchecker" */ #line 3601 "VParseBison.y" { } #line 31793 "VParseBison.c" break; case 1763: /* specifyJunk: "endclass" */ #line 3601 "VParseBison.y" { } #line 31799 "VParseBison.c" break; case 1764: /* specifyJunk: "endclocking" */ #line 3601 "VParseBison.y" { } #line 31805 "VParseBison.c" break; case 1765: /* specifyJunk: "endfunction" */ #line 3601 "VParseBison.y" { } #line 31811 "VParseBison.c" break; case 1766: /* specifyJunk: "endgenerate" */ #line 3601 "VParseBison.y" { } #line 31817 "VParseBison.c" break; case 1767: /* specifyJunk: "endgroup" */ #line 3601 "VParseBison.y" { } #line 31823 "VParseBison.c" break; case 1768: /* specifyJunk: "endinterface" */ #line 3601 "VParseBison.y" { } #line 31829 "VParseBison.c" break; case 1769: /* specifyJunk: "endmodule" */ #line 3601 "VParseBison.y" { } #line 31835 "VParseBison.c" break; case 1770: /* specifyJunk: "endpackage" */ #line 3601 "VParseBison.y" { } #line 31841 "VParseBison.c" break; case 1771: /* specifyJunk: "endprogram" */ #line 3601 "VParseBison.y" { } #line 31847 "VParseBison.c" break; case 1772: /* specifyJunk: "endproperty" */ #line 3601 "VParseBison.y" { } #line 31853 "VParseBison.c" break; case 1773: /* specifyJunk: "endsequence" */ #line 3601 "VParseBison.y" { } #line 31859 "VParseBison.c" break; case 1774: /* specifyJunk: "endtable" */ #line 3601 "VParseBison.y" { } #line 31865 "VParseBison.c" break; case 1775: /* specifyJunk: "endtask" */ #line 3601 "VParseBison.y" { } #line 31871 "VParseBison.c" break; case 1776: /* specifyJunk: "enum" */ #line 3601 "VParseBison.y" { } #line 31877 "VParseBison.c" break; case 1777: /* specifyJunk: "event" */ #line 3601 "VParseBison.y" { } #line 31883 "VParseBison.c" break; case 1778: /* specifyJunk: "eventually" */ #line 3601 "VParseBison.y" { } #line 31889 "VParseBison.c" break; case 1779: /* specifyJunk: "expect" */ #line 3601 "VParseBison.y" { } #line 31895 "VParseBison.c" break; case 1780: /* specifyJunk: "export" */ #line 3601 "VParseBison.y" { } #line 31901 "VParseBison.c" break; case 1781: /* specifyJunk: "extends" */ #line 3601 "VParseBison.y" { } #line 31907 "VParseBison.c" break; case 1782: /* specifyJunk: "extern" */ #line 3601 "VParseBison.y" { } #line 31913 "VParseBison.c" break; case 1783: /* specifyJunk: "final" */ #line 3601 "VParseBison.y" { } #line 31919 "VParseBison.c" break; case 1784: /* specifyJunk: "first_match" */ #line 3601 "VParseBison.y" { } #line 31925 "VParseBison.c" break; case 1785: /* specifyJunk: "for" */ #line 3601 "VParseBison.y" { } #line 31931 "VParseBison.c" break; case 1786: /* specifyJunk: "force" */ #line 3601 "VParseBison.y" { } #line 31937 "VParseBison.c" break; case 1787: /* specifyJunk: "foreach" */ #line 3601 "VParseBison.y" { } #line 31943 "VParseBison.c" break; case 1788: /* specifyJunk: "forever" */ #line 3601 "VParseBison.y" { } #line 31949 "VParseBison.c" break; case 1789: /* specifyJunk: "fork" */ #line 3601 "VParseBison.y" { } #line 31955 "VParseBison.c" break; case 1790: /* specifyJunk: "forkjoin" */ #line 3601 "VParseBison.y" { } #line 31961 "VParseBison.c" break; case 1791: /* specifyJunk: "function" */ #line 3601 "VParseBison.y" { } #line 31967 "VParseBison.c" break; case 1792: /* specifyJunk: "function-in-lex" */ #line 3601 "VParseBison.y" { } #line 31973 "VParseBison.c" break; case 1793: /* specifyJunk: "function-is-pure-virtual" */ #line 3601 "VParseBison.y" { } #line 31979 "VParseBison.c" break; case 1794: /* specifyJunk: "generate" */ #line 3601 "VParseBison.y" { } #line 31985 "VParseBison.c" break; case 1795: /* specifyJunk: "genvar" */ #line 3601 "VParseBison.y" { } #line 31991 "VParseBison.c" break; case 1796: /* specifyJunk: "global-then-clocking" */ #line 3601 "VParseBison.y" { } #line 31997 "VParseBison.c" break; case 1797: /* specifyJunk: "global-in-lex" */ #line 3601 "VParseBison.y" { } #line 32003 "VParseBison.c" break; case 1798: /* specifyJunk: "if" */ #line 3601 "VParseBison.y" { } #line 32009 "VParseBison.c" break; case 1799: /* specifyJunk: "iff" */ #line 3601 "VParseBison.y" { } #line 32015 "VParseBison.c" break; case 1800: /* specifyJunk: "ignore_bins" */ #line 3601 "VParseBison.y" { } #line 32021 "VParseBison.c" break; case 1801: /* specifyJunk: "illegal_bins" */ #line 3601 "VParseBison.y" { } #line 32027 "VParseBison.c" break; case 1802: /* specifyJunk: "implements" */ #line 3601 "VParseBison.y" { } #line 32033 "VParseBison.c" break; case 1803: /* specifyJunk: "implies" */ #line 3601 "VParseBison.y" { } #line 32039 "VParseBison.c" break; case 1804: /* specifyJunk: "import" */ #line 3601 "VParseBison.y" { } #line 32045 "VParseBison.c" break; case 1805: /* specifyJunk: "initial" */ #line 3601 "VParseBison.y" { } #line 32051 "VParseBison.c" break; case 1806: /* specifyJunk: "inout" */ #line 3601 "VParseBison.y" { } #line 32057 "VParseBison.c" break; case 1807: /* specifyJunk: "input" */ #line 3601 "VParseBison.y" { } #line 32063 "VParseBison.c" break; case 1808: /* specifyJunk: "inside" */ #line 3601 "VParseBison.y" { } #line 32069 "VParseBison.c" break; case 1809: /* specifyJunk: "int" */ #line 3601 "VParseBison.y" { } #line 32075 "VParseBison.c" break; case 1810: /* specifyJunk: "integer" */ #line 3601 "VParseBison.y" { } #line 32081 "VParseBison.c" break; case 1811: /* specifyJunk: "interconnect" */ #line 3601 "VParseBison.y" { } #line 32087 "VParseBison.c" break; case 1812: /* specifyJunk: "interface" */ #line 3601 "VParseBison.y" { } #line 32093 "VParseBison.c" break; case 1813: /* specifyJunk: "intersect" */ #line 3601 "VParseBison.y" { } #line 32099 "VParseBison.c" break; case 1814: /* specifyJunk: "join" */ #line 3601 "VParseBison.y" { } #line 32105 "VParseBison.c" break; case 1815: /* specifyJunk: "let" */ #line 3601 "VParseBison.y" { } #line 32111 "VParseBison.c" break; case 1816: /* specifyJunk: "localparam" */ #line 3601 "VParseBison.y" { } #line 32117 "VParseBison.c" break; case 1817: /* specifyJunk: "local-then-::" */ #line 3601 "VParseBison.y" { } #line 32123 "VParseBison.c" break; case 1818: /* specifyJunk: "local" */ #line 3601 "VParseBison.y" { } #line 32129 "VParseBison.c" break; case 1819: /* specifyJunk: "local-in-lex" */ #line 3601 "VParseBison.y" { } #line 32135 "VParseBison.c" break; case 1820: /* specifyJunk: "logic" */ #line 3601 "VParseBison.y" { } #line 32141 "VParseBison.c" break; case 1821: /* specifyJunk: "longint" */ #line 3601 "VParseBison.y" { } #line 32147 "VParseBison.c" break; case 1822: /* specifyJunk: "matches" */ #line 3601 "VParseBison.y" { } #line 32153 "VParseBison.c" break; case 1823: /* specifyJunk: "modport" */ #line 3601 "VParseBison.y" { } #line 32159 "VParseBison.c" break; case 1824: /* specifyJunk: "module" */ #line 3601 "VParseBison.y" { } #line 32165 "VParseBison.c" break; case 1825: /* specifyJunk: "nand" */ #line 3601 "VParseBison.y" { } #line 32171 "VParseBison.c" break; case 1826: /* specifyJunk: "negedge" */ #line 3601 "VParseBison.y" { } #line 32177 "VParseBison.c" break; case 1827: /* specifyJunk: "nettype" */ #line 3601 "VParseBison.y" { } #line 32183 "VParseBison.c" break; case 1828: /* specifyJunk: "new" */ #line 3601 "VParseBison.y" { } #line 32189 "VParseBison.c" break; case 1829: /* specifyJunk: "new-in-lex" */ #line 3601 "VParseBison.y" { } #line 32195 "VParseBison.c" break; case 1830: /* specifyJunk: "new-then-paren" */ #line 3601 "VParseBison.y" { } #line 32201 "VParseBison.c" break; case 1831: /* specifyJunk: "nexttime" */ #line 3601 "VParseBison.y" { } #line 32207 "VParseBison.c" break; case 1832: /* specifyJunk: "nor" */ #line 3601 "VParseBison.y" { } #line 32213 "VParseBison.c" break; case 1833: /* specifyJunk: "not" */ #line 3601 "VParseBison.y" { } #line 32219 "VParseBison.c" break; case 1834: /* specifyJunk: "null" */ #line 3601 "VParseBison.y" { } #line 32225 "VParseBison.c" break; case 1835: /* specifyJunk: "or" */ #line 3601 "VParseBison.y" { } #line 32231 "VParseBison.c" break; case 1836: /* specifyJunk: "output" */ #line 3601 "VParseBison.y" { } #line 32237 "VParseBison.c" break; case 1837: /* specifyJunk: "package" */ #line 3601 "VParseBison.y" { } #line 32243 "VParseBison.c" break; case 1838: /* specifyJunk: "packed" */ #line 3601 "VParseBison.y" { } #line 32249 "VParseBison.c" break; case 1839: /* specifyJunk: "parameter" */ #line 3601 "VParseBison.y" { } #line 32255 "VParseBison.c" break; case 1840: /* specifyJunk: "posedge" */ #line 3601 "VParseBison.y" { } #line 32261 "VParseBison.c" break; case 1841: /* specifyJunk: "priority" */ #line 3601 "VParseBison.y" { } #line 32267 "VParseBison.c" break; case 1842: /* specifyJunk: "program" */ #line 3601 "VParseBison.y" { } #line 32273 "VParseBison.c" break; case 1843: /* specifyJunk: "property" */ #line 3601 "VParseBison.y" { } #line 32279 "VParseBison.c" break; case 1844: /* specifyJunk: "protected" */ #line 3601 "VParseBison.y" { } #line 32285 "VParseBison.c" break; case 1845: /* specifyJunk: "pure" */ #line 3601 "VParseBison.y" { } #line 32291 "VParseBison.c" break; case 1846: /* specifyJunk: "&&" */ #line 3601 "VParseBison.y" { } #line 32297 "VParseBison.c" break; case 1847: /* specifyJunk: "&&&" */ #line 3601 "VParseBison.y" { } #line 32303 "VParseBison.c" break; case 1848: /* specifyJunk: "&=" */ #line 3601 "VParseBison.y" { } #line 32309 "VParseBison.c" break; case 1849: /* specifyJunk: "*>" */ #line 3601 "VParseBison.y" { } #line 32315 "VParseBison.c" break; case 1850: /* specifyJunk: "@@" */ #line 3601 "VParseBison.y" { } #line 32321 "VParseBison.c" break; case 1851: /* specifyJunk: "[=" */ #line 3601 "VParseBison.y" { } #line 32327 "VParseBison.c" break; case 1852: /* specifyJunk: "[->" */ #line 3601 "VParseBison.y" { } #line 32333 "VParseBison.c" break; case 1853: /* specifyJunk: "[+]" */ #line 3601 "VParseBison.y" { } #line 32339 "VParseBison.c" break; case 1854: /* specifyJunk: "[*" */ #line 3601 "VParseBison.y" { } #line 32345 "VParseBison.c" break; case 1855: /* specifyJunk: "===" */ #line 3601 "VParseBison.y" { } #line 32351 "VParseBison.c" break; case 1856: /* specifyJunk: "!==" */ #line 3601 "VParseBison.y" { } #line 32357 "VParseBison.c" break; case 1857: /* specifyJunk: "::" */ #line 3601 "VParseBison.y" { } #line 32363 "VParseBison.c" break; case 1858: /* specifyJunk: ":/" */ #line 3601 "VParseBison.y" { } #line 32369 "VParseBison.c" break; case 1859: /* specifyJunk: ":=" */ #line 3601 "VParseBison.y" { } #line 32375 "VParseBison.c" break; case 1860: /* specifyJunk: "/=" */ #line 3601 "VParseBison.y" { } #line 32381 "VParseBison.c" break; case 1861: /* specifyJunk: ".*" */ #line 3601 "VParseBison.y" { } #line 32387 "VParseBison.c" break; case 1862: /* specifyJunk: "=>" */ #line 3601 "VParseBison.y" { } #line 32393 "VParseBison.c" break; case 1863: /* specifyJunk: "==" */ #line 3601 "VParseBison.y" { } #line 32399 "VParseBison.c" break; case 1864: /* specifyJunk: ">=" */ #line 3601 "VParseBison.y" { } #line 32405 "VParseBison.c" break; case 1865: /* specifyJunk: "<=" */ #line 3601 "VParseBison.y" { } #line 32411 "VParseBison.c" break; case 1866: /* specifyJunk: "<=-ignored" */ #line 3601 "VParseBison.y" { } #line 32417 "VParseBison.c" break; case 1867: /* specifyJunk: "<->" */ #line 3601 "VParseBison.y" { } #line 32423 "VParseBison.c" break; case 1868: /* specifyJunk: "-:" */ #line 3601 "VParseBison.y" { } #line 32429 "VParseBison.c" break; case 1869: /* specifyJunk: "-=" */ #line 3601 "VParseBison.y" { } #line 32435 "VParseBison.c" break; case 1870: /* specifyJunk: "->" */ #line 3601 "VParseBison.y" { } #line 32441 "VParseBison.c" break; case 1871: /* specifyJunk: "->>" */ #line 3601 "VParseBison.y" { } #line 32447 "VParseBison.c" break; case 1872: /* specifyJunk: "--" */ #line 3601 "VParseBison.y" { } #line 32453 "VParseBison.c" break; case 1873: /* specifyJunk: "%=" */ #line 3601 "VParseBison.y" { } #line 32459 "VParseBison.c" break; case 1874: /* specifyJunk: "~&" */ #line 3601 "VParseBison.y" { } #line 32465 "VParseBison.c" break; case 1875: /* specifyJunk: "~|" */ #line 3601 "VParseBison.y" { } #line 32471 "VParseBison.c" break; case 1876: /* specifyJunk: "!=" */ #line 3601 "VParseBison.y" { } #line 32477 "VParseBison.c" break; case 1877: /* specifyJunk: "|=" */ #line 3601 "VParseBison.y" { } #line 32483 "VParseBison.c" break; case 1878: /* specifyJunk: "|=>" */ #line 3601 "VParseBison.y" { } #line 32489 "VParseBison.c" break; case 1879: /* specifyJunk: "|->" */ #line 3601 "VParseBison.y" { } #line 32495 "VParseBison.c" break; case 1880: /* specifyJunk: "||" */ #line 3601 "VParseBison.y" { } #line 32501 "VParseBison.c" break; case 1881: /* specifyJunk: "(-ignored" */ #line 3601 "VParseBison.y" { } #line 32507 "VParseBison.c" break; case 1882: /* specifyJunk: "(-for-strength" */ #line 3601 "VParseBison.y" { } #line 32513 "VParseBison.c" break; case 1883: /* specifyJunk: "+:" */ #line 3601 "VParseBison.y" { } #line 32519 "VParseBison.c" break; case 1884: /* specifyJunk: "+=" */ #line 3601 "VParseBison.y" { } #line 32525 "VParseBison.c" break; case 1885: /* specifyJunk: "++" */ #line 3601 "VParseBison.y" { } #line 32531 "VParseBison.c" break; case 1886: /* specifyJunk: "#=#" */ #line 3601 "VParseBison.y" { } #line 32537 "VParseBison.c" break; case 1887: /* specifyJunk: "#-#" */ #line 3601 "VParseBison.y" { } #line 32543 "VParseBison.c" break; case 1888: /* specifyJunk: "##" */ #line 3601 "VParseBison.y" { } #line 32549 "VParseBison.c" break; case 1889: /* specifyJunk: "**" */ #line 3601 "VParseBison.y" { } #line 32555 "VParseBison.c" break; case 1890: /* specifyJunk: "<<" */ #line 3601 "VParseBison.y" { } #line 32561 "VParseBison.c" break; case 1891: /* specifyJunk: "<<=" */ #line 3601 "VParseBison.y" { } #line 32567 "VParseBison.c" break; case 1892: /* specifyJunk: ">>" */ #line 3601 "VParseBison.y" { } #line 32573 "VParseBison.c" break; case 1893: /* specifyJunk: ">>=" */ #line 3601 "VParseBison.y" { } #line 32579 "VParseBison.c" break; case 1894: /* specifyJunk: ">>>" */ #line 3601 "VParseBison.y" { } #line 32585 "VParseBison.c" break; case 1895: /* specifyJunk: ">>>=" */ #line 3601 "VParseBison.y" { } #line 32591 "VParseBison.c" break; case 1896: /* specifyJunk: "'" */ #line 3601 "VParseBison.y" { } #line 32597 "VParseBison.c" break; case 1897: /* specifyJunk: "'{" */ #line 3601 "VParseBison.y" { } #line 32603 "VParseBison.c" break; case 1898: /* specifyJunk: "*=" */ #line 3601 "VParseBison.y" { } #line 32609 "VParseBison.c" break; case 1899: /* specifyJunk: "==?" */ #line 3601 "VParseBison.y" { } #line 32615 "VParseBison.c" break; case 1900: /* specifyJunk: "!=?" */ #line 3601 "VParseBison.y" { } #line 32621 "VParseBison.c" break; case 1901: /* specifyJunk: "^~" */ #line 3601 "VParseBison.y" { } #line 32627 "VParseBison.c" break; case 1902: /* specifyJunk: "^=" */ #line 3601 "VParseBison.y" { } #line 32633 "VParseBison.c" break; case 1903: /* specifyJunk: "rand" */ #line 3601 "VParseBison.y" { } #line 32639 "VParseBison.c" break; case 1904: /* specifyJunk: "randc" */ #line 3601 "VParseBison.y" { } #line 32645 "VParseBison.c" break; case 1905: /* specifyJunk: "randcase" */ #line 3601 "VParseBison.y" { } #line 32651 "VParseBison.c" break; case 1906: /* specifyJunk: "randsequence" */ #line 3601 "VParseBison.y" { } #line 32657 "VParseBison.c" break; case 1907: /* specifyJunk: "real" */ #line 3601 "VParseBison.y" { } #line 32663 "VParseBison.c" break; case 1908: /* specifyJunk: "realtime" */ #line 3601 "VParseBison.y" { } #line 32669 "VParseBison.c" break; case 1909: /* specifyJunk: "ref" */ #line 3601 "VParseBison.y" { } #line 32675 "VParseBison.c" break; case 1910: /* specifyJunk: "reg" */ #line 3601 "VParseBison.y" { } #line 32681 "VParseBison.c" break; case 1911: /* specifyJunk: "reject_on" */ #line 3601 "VParseBison.y" { } #line 32687 "VParseBison.c" break; case 1912: /* specifyJunk: "release" */ #line 3601 "VParseBison.y" { } #line 32693 "VParseBison.c" break; case 1913: /* specifyJunk: "repeat" */ #line 3601 "VParseBison.y" { } #line 32699 "VParseBison.c" break; case 1914: /* specifyJunk: "restrict" */ #line 3601 "VParseBison.y" { } #line 32705 "VParseBison.c" break; case 1915: /* specifyJunk: "return" */ #line 3601 "VParseBison.y" { } #line 32711 "VParseBison.c" break; case 1916: /* specifyJunk: "scalared" */ #line 3601 "VParseBison.y" { } #line 32717 "VParseBison.c" break; case 1917: /* specifyJunk: "sequence" */ #line 3601 "VParseBison.y" { } #line 32723 "VParseBison.c" break; case 1918: /* specifyJunk: "shortint" */ #line 3601 "VParseBison.y" { } #line 32729 "VParseBison.c" break; case 1919: /* specifyJunk: "shortreal" */ #line 3601 "VParseBison.y" { } #line 32735 "VParseBison.c" break; case 1920: /* specifyJunk: "signed" */ #line 3601 "VParseBison.y" { } #line 32741 "VParseBison.c" break; case 1921: /* specifyJunk: "soft" */ #line 3601 "VParseBison.y" { } #line 32747 "VParseBison.c" break; case 1922: /* specifyJunk: "solve" */ #line 3601 "VParseBison.y" { } #line 32753 "VParseBison.c" break; case 1923: /* specifyJunk: "specparam" */ #line 3601 "VParseBison.y" { } #line 32759 "VParseBison.c" break; case 1924: /* specifyJunk: "static-then-constraint" */ #line 3601 "VParseBison.y" { } #line 32765 "VParseBison.c" break; case 1925: /* specifyJunk: "static" */ #line 3601 "VParseBison.y" { } #line 32771 "VParseBison.c" break; case 1926: /* specifyJunk: "static-in-lex" */ #line 3601 "VParseBison.y" { } #line 32777 "VParseBison.c" break; case 1927: /* specifyJunk: "string" */ #line 3601 "VParseBison.y" { } #line 32783 "VParseBison.c" break; case 1928: /* specifyJunk: "strong" */ #line 3601 "VParseBison.y" { } #line 32789 "VParseBison.c" break; case 1929: /* specifyJunk: "struct" */ #line 3601 "VParseBison.y" { } #line 32795 "VParseBison.c" break; case 1930: /* specifyJunk: "super" */ #line 3601 "VParseBison.y" { } #line 32801 "VParseBison.c" break; case 1931: /* specifyJunk: "supply0" */ #line 3601 "VParseBison.y" { } #line 32807 "VParseBison.c" break; case 1932: /* specifyJunk: "supply1" */ #line 3601 "VParseBison.y" { } #line 32813 "VParseBison.c" break; case 1933: /* specifyJunk: "sync_accept_on" */ #line 3601 "VParseBison.y" { } #line 32819 "VParseBison.c" break; case 1934: /* specifyJunk: "sync_reject_on" */ #line 3601 "VParseBison.y" { } #line 32825 "VParseBison.c" break; case 1935: /* specifyJunk: "s_always" */ #line 3601 "VParseBison.y" { } #line 32831 "VParseBison.c" break; case 1936: /* specifyJunk: "s_eventually" */ #line 3601 "VParseBison.y" { } #line 32837 "VParseBison.c" break; case 1937: /* specifyJunk: "s_nexttime" */ #line 3601 "VParseBison.y" { } #line 32843 "VParseBison.c" break; case 1938: /* specifyJunk: "s_until" */ #line 3601 "VParseBison.y" { } #line 32849 "VParseBison.c" break; case 1939: /* specifyJunk: "s_until_with" */ #line 3601 "VParseBison.y" { } #line 32855 "VParseBison.c" break; case 1940: /* specifyJunk: "table" */ #line 3601 "VParseBison.y" { } #line 32861 "VParseBison.c" break; case 1941: /* specifyJunk: "tagged" */ #line 3601 "VParseBison.y" { } #line 32867 "VParseBison.c" break; case 1942: /* specifyJunk: "task" */ #line 3601 "VParseBison.y" { } #line 32873 "VParseBison.c" break; case 1943: /* specifyJunk: "task-in-lex" */ #line 3601 "VParseBison.y" { } #line 32879 "VParseBison.c" break; case 1944: /* specifyJunk: "task-is-pure-virtual" */ #line 3601 "VParseBison.y" { } #line 32885 "VParseBison.c" break; case 1945: /* specifyJunk: "this" */ #line 3601 "VParseBison.y" { } #line 32891 "VParseBison.c" break; case 1946: /* specifyJunk: "throughout" */ #line 3601 "VParseBison.y" { } #line 32897 "VParseBison.c" break; case 1947: /* specifyJunk: "time" */ #line 3601 "VParseBison.y" { } #line 32903 "VParseBison.c" break; case 1948: /* specifyJunk: "timeprecision" */ #line 3601 "VParseBison.y" { } #line 32909 "VParseBison.c" break; case 1949: /* specifyJunk: "timeunit" */ #line 3601 "VParseBison.y" { } #line 32915 "VParseBison.c" break; case 1950: /* specifyJunk: "tri" */ #line 3601 "VParseBison.y" { } #line 32921 "VParseBison.c" break; case 1951: /* specifyJunk: "tri0" */ #line 3601 "VParseBison.y" { } #line 32927 "VParseBison.c" break; case 1952: /* specifyJunk: "tri1" */ #line 3601 "VParseBison.y" { } #line 32933 "VParseBison.c" break; case 1953: /* specifyJunk: "triand" */ #line 3601 "VParseBison.y" { } #line 32939 "VParseBison.c" break; case 1954: /* specifyJunk: "trior" */ #line 3601 "VParseBison.y" { } #line 32945 "VParseBison.c" break; case 1955: /* specifyJunk: "trireg" */ #line 3601 "VParseBison.y" { } #line 32951 "VParseBison.c" break; case 1956: /* specifyJunk: "type" */ #line 3601 "VParseBison.y" { } #line 32957 "VParseBison.c" break; case 1957: /* specifyJunk: "typedef" */ #line 3601 "VParseBison.y" { } #line 32963 "VParseBison.c" break; case 1958: /* specifyJunk: "union" */ #line 3601 "VParseBison.y" { } #line 32969 "VParseBison.c" break; case 1959: /* specifyJunk: "unique" */ #line 3601 "VParseBison.y" { } #line 32975 "VParseBison.c" break; case 1960: /* specifyJunk: "unique0" */ #line 3601 "VParseBison.y" { } #line 32981 "VParseBison.c" break; case 1961: /* specifyJunk: "unsigned" */ #line 3601 "VParseBison.y" { } #line 32987 "VParseBison.c" break; case 1962: /* specifyJunk: "until" */ #line 3601 "VParseBison.y" { } #line 32993 "VParseBison.c" break; case 1963: /* specifyJunk: "until_with" */ #line 3601 "VParseBison.y" { } #line 32999 "VParseBison.c" break; case 1964: /* specifyJunk: "untyped" */ #line 3601 "VParseBison.y" { } #line 33005 "VParseBison.c" break; case 1965: /* specifyJunk: "var" */ #line 3601 "VParseBison.y" { } #line 33011 "VParseBison.c" break; case 1966: /* specifyJunk: "vectored" */ #line 3601 "VParseBison.y" { } #line 33017 "VParseBison.c" break; case 1967: /* specifyJunk: "virtual-then-class" */ #line 3601 "VParseBison.y" { } #line 33023 "VParseBison.c" break; case 1968: /* specifyJunk: "virtual" */ #line 3601 "VParseBison.y" { } #line 33029 "VParseBison.c" break; case 1969: /* specifyJunk: "virtual-then-interface" */ #line 3601 "VParseBison.y" { } #line 33035 "VParseBison.c" break; case 1970: /* specifyJunk: "virtual-in-lex" */ #line 3601 "VParseBison.y" { } #line 33041 "VParseBison.c" break; case 1971: /* specifyJunk: "virtual-then-identifier" */ #line 3601 "VParseBison.y" { } #line 33047 "VParseBison.c" break; case 1972: /* specifyJunk: "void" */ #line 3601 "VParseBison.y" { } #line 33053 "VParseBison.c" break; case 1973: /* specifyJunk: "wait" */ #line 3601 "VParseBison.y" { } #line 33059 "VParseBison.c" break; case 1974: /* specifyJunk: "wait_order" */ #line 3601 "VParseBison.y" { } #line 33065 "VParseBison.c" break; case 1975: /* specifyJunk: "wand" */ #line 3601 "VParseBison.y" { } #line 33071 "VParseBison.c" break; case 1976: /* specifyJunk: "weak" */ #line 3601 "VParseBison.y" { } #line 33077 "VParseBison.c" break; case 1977: /* specifyJunk: "while" */ #line 3601 "VParseBison.y" { } #line 33083 "VParseBison.c" break; case 1978: /* specifyJunk: "wildcard" */ #line 3601 "VParseBison.y" { } #line 33089 "VParseBison.c" break; case 1979: /* specifyJunk: "wire" */ #line 3601 "VParseBison.y" { } #line 33095 "VParseBison.c" break; case 1980: /* specifyJunk: "within" */ #line 3601 "VParseBison.y" { } #line 33101 "VParseBison.c" break; case 1981: /* specifyJunk: "with-then-[" */ #line 3601 "VParseBison.y" { } #line 33107 "VParseBison.c" break; case 1982: /* specifyJunk: "with-then-{" */ #line 3601 "VParseBison.y" { } #line 33113 "VParseBison.c" break; case 1983: /* specifyJunk: "with" */ #line 3601 "VParseBison.y" { } #line 33119 "VParseBison.c" break; case 1984: /* specifyJunk: "with-in-lex" */ #line 3601 "VParseBison.y" { } #line 33125 "VParseBison.c" break; case 1985: /* specifyJunk: "with-then-(" */ #line 3601 "VParseBison.y" { } #line 33131 "VParseBison.c" break; case 1986: /* specifyJunk: "wor" */ #line 3601 "VParseBison.y" { } #line 33137 "VParseBison.c" break; case 1987: /* specifyJunk: "xnor" */ #line 3601 "VParseBison.y" { } #line 33143 "VParseBison.c" break; case 1988: /* specifyJunk: "xor" */ #line 3601 "VParseBison.y" { } #line 33149 "VParseBison.c" break; case 1989: /* specifyJunk: "FLOATING-POINT NUMBER" */ #line 3601 "VParseBison.y" { } #line 33155 "VParseBison.c" break; case 1990: /* specifyJunk: "IDENTIFIER" */ #line 3601 "VParseBison.y" { } #line 33161 "VParseBison.c" break; case 1991: /* specifyJunk: "IDENTIFIER-in-lex" */ #line 3601 "VParseBison.y" { } #line 33167 "VParseBison.c" break; case 1992: /* specifyJunk: "PACKAGE-IDENTIFIER" */ #line 3601 "VParseBison.y" { } #line 33173 "VParseBison.c" break; case 1993: /* specifyJunk: "TYPE-IDENTIFIER" */ #line 3601 "VParseBison.y" { } #line 33179 "VParseBison.c" break; case 1994: /* specifyJunk: "INTEGER NUMBER" */ #line 3601 "VParseBison.y" { } #line 33185 "VParseBison.c" break; case 1995: /* specifyJunk: "STRING" */ #line 3601 "VParseBison.y" { } #line 33191 "VParseBison.c" break; case 1996: /* specifyJunk: "STRING-ignored" */ #line 3601 "VParseBison.y" { } #line 33197 "VParseBison.c" break; case 1997: /* specifyJunk: "TIME NUMBER" */ #line 3601 "VParseBison.y" { } #line 33203 "VParseBison.c" break; case 1998: /* specifyJunk: "TIMING SPEC ELEMENT" */ #line 3601 "VParseBison.y" { } #line 33209 "VParseBison.c" break; case 1999: /* specifyJunk: "CONFIG keyword (cell/use/design/etc)" */ #line 3601 "VParseBison.y" { } #line 33215 "VParseBison.c" break; case 2000: /* specifyJunk: "GATE keyword" */ #line 3601 "VParseBison.y" { } #line 33221 "VParseBison.c" break; case 2001: /* specifyJunk: "OPERATOR" */ #line 3601 "VParseBison.y" { } #line 33227 "VParseBison.c" break; case 2002: /* specifyJunk: "STRENGTH keyword (strong1/etc)" */ #line 3601 "VParseBison.y" { } #line 33233 "VParseBison.c" break; case 2003: /* specifyJunk: "SYSCALL" */ #line 3601 "VParseBison.y" { } #line 33239 "VParseBison.c" break; case 2004: /* specifyJunk: "specify" specifyJunk "endspecify" */ #line 3602 "VParseBison.y" { } #line 33245 "VParseBison.c" break; case 2005: /* specifyJunk: error */ #line 3603 "VParseBison.y" {} #line 33251 "VParseBison.c" break; case 2006: /* specparam_declaration: "specparam" junkToSemiList ';' */ #line 3607 "VParseBison.y" { } #line 33257 "VParseBison.c" break; case 2007: /* junkToSemiList: junkToSemi */ #line 3611 "VParseBison.y" { } #line 33263 "VParseBison.c" break; case 2008: /* junkToSemiList: junkToSemiList junkToSemi */ #line 3612 "VParseBison.y" { } #line 33269 "VParseBison.c" break; case 2009: /* junkToSemi: '!' */ #line 3616 "VParseBison.y" { } #line 33275 "VParseBison.c" break; case 2010: /* junkToSemi: '#' */ #line 3616 "VParseBison.y" { } #line 33281 "VParseBison.c" break; case 2011: /* junkToSemi: '%' */ #line 3616 "VParseBison.y" { } #line 33287 "VParseBison.c" break; case 2012: /* junkToSemi: '&' */ #line 3616 "VParseBison.y" { } #line 33293 "VParseBison.c" break; case 2013: /* junkToSemi: '(' */ #line 3616 "VParseBison.y" { } #line 33299 "VParseBison.c" break; case 2014: /* junkToSemi: ')' */ #line 3616 "VParseBison.y" { } #line 33305 "VParseBison.c" break; case 2015: /* junkToSemi: '*' */ #line 3616 "VParseBison.y" { } #line 33311 "VParseBison.c" break; case 2016: /* junkToSemi: '+' */ #line 3616 "VParseBison.y" { } #line 33317 "VParseBison.c" break; case 2017: /* junkToSemi: ',' */ #line 3616 "VParseBison.y" { } #line 33323 "VParseBison.c" break; case 2018: /* junkToSemi: '-' */ #line 3616 "VParseBison.y" { } #line 33329 "VParseBison.c" break; case 2019: /* junkToSemi: '.' */ #line 3616 "VParseBison.y" { } #line 33335 "VParseBison.c" break; case 2020: /* junkToSemi: '/' */ #line 3616 "VParseBison.y" { } #line 33341 "VParseBison.c" break; case 2021: /* junkToSemi: ':' */ #line 3616 "VParseBison.y" { } #line 33347 "VParseBison.c" break; case 2022: /* junkToSemi: '<' */ #line 3616 "VParseBison.y" { } #line 33353 "VParseBison.c" break; case 2023: /* junkToSemi: '=' */ #line 3616 "VParseBison.y" { } #line 33359 "VParseBison.c" break; case 2024: /* junkToSemi: '>' */ #line 3616 "VParseBison.y" { } #line 33365 "VParseBison.c" break; case 2025: /* junkToSemi: '?' */ #line 3616 "VParseBison.y" { } #line 33371 "VParseBison.c" break; case 2026: /* junkToSemi: '@' */ #line 3616 "VParseBison.y" { } #line 33377 "VParseBison.c" break; case 2027: /* junkToSemi: '[' */ #line 3616 "VParseBison.y" { } #line 33383 "VParseBison.c" break; case 2028: /* junkToSemi: ']' */ #line 3616 "VParseBison.y" { } #line 33389 "VParseBison.c" break; case 2029: /* junkToSemi: '^' */ #line 3616 "VParseBison.y" { } #line 33395 "VParseBison.c" break; case 2030: /* junkToSemi: '{' */ #line 3616 "VParseBison.y" { } #line 33401 "VParseBison.c" break; case 2031: /* junkToSemi: '|' */ #line 3616 "VParseBison.y" { } #line 33407 "VParseBison.c" break; case 2032: /* junkToSemi: '}' */ #line 3616 "VParseBison.y" { } #line 33413 "VParseBison.c" break; case 2033: /* junkToSemi: '~' */ #line 3616 "VParseBison.y" { } #line 33419 "VParseBison.c" break; case 2034: /* junkToSemi: prEVENTBEGIN */ #line 3616 "VParseBison.y" { } #line 33425 "VParseBison.c" break; case 2035: /* junkToSemi: prNEGATION */ #line 3616 "VParseBison.y" { } #line 33431 "VParseBison.c" break; case 2036: /* junkToSemi: prREDUCTION */ #line 3616 "VParseBison.y" { } #line 33437 "VParseBison.c" break; case 2037: /* junkToSemi: prTAGGED */ #line 3616 "VParseBison.y" { } #line 33443 "VParseBison.c" break; case 2038: /* junkToSemi: prUNARYARITH */ #line 3616 "VParseBison.y" { } #line 33449 "VParseBison.c" break; case 2039: /* junkToSemi: "accept_on" */ #line 3616 "VParseBison.y" { } #line 33455 "VParseBison.c" break; case 2040: /* junkToSemi: "alias" */ #line 3616 "VParseBison.y" { } #line 33461 "VParseBison.c" break; case 2041: /* junkToSemi: "always" */ #line 3616 "VParseBison.y" { } #line 33467 "VParseBison.c" break; case 2042: /* junkToSemi: "and" */ #line 3616 "VParseBison.y" { } #line 33473 "VParseBison.c" break; case 2043: /* junkToSemi: "assert" */ #line 3616 "VParseBison.y" { } #line 33479 "VParseBison.c" break; case 2044: /* junkToSemi: "assign" */ #line 3616 "VParseBison.y" { } #line 33485 "VParseBison.c" break; case 2045: /* junkToSemi: "assume" */ #line 3616 "VParseBison.y" { } #line 33491 "VParseBison.c" break; case 2046: /* junkToSemi: "automatic" */ #line 3616 "VParseBison.y" { } #line 33497 "VParseBison.c" break; case 2047: /* junkToSemi: "before" */ #line 3616 "VParseBison.y" { } #line 33503 "VParseBison.c" break; case 2048: /* junkToSemi: "begin" */ #line 3616 "VParseBison.y" { } #line 33509 "VParseBison.c" break; case 2049: /* junkToSemi: "bind" */ #line 3616 "VParseBison.y" { } #line 33515 "VParseBison.c" break; case 2050: /* junkToSemi: "bins" */ #line 3616 "VParseBison.y" { } #line 33521 "VParseBison.c" break; case 2051: /* junkToSemi: "binsof" */ #line 3616 "VParseBison.y" { } #line 33527 "VParseBison.c" break; case 2052: /* junkToSemi: "bit" */ #line 3616 "VParseBison.y" { } #line 33533 "VParseBison.c" break; case 2053: /* junkToSemi: "break" */ #line 3616 "VParseBison.y" { } #line 33539 "VParseBison.c" break; case 2054: /* junkToSemi: "buf" */ #line 3616 "VParseBison.y" { } #line 33545 "VParseBison.c" break; case 2055: /* junkToSemi: "byte" */ #line 3616 "VParseBison.y" { } #line 33551 "VParseBison.c" break; case 2056: /* junkToSemi: "case" */ #line 3616 "VParseBison.y" { } #line 33557 "VParseBison.c" break; case 2057: /* junkToSemi: "casex" */ #line 3616 "VParseBison.y" { } #line 33563 "VParseBison.c" break; case 2058: /* junkToSemi: "casez" */ #line 3616 "VParseBison.y" { } #line 33569 "VParseBison.c" break; case 2059: /* junkToSemi: "chandle" */ #line 3616 "VParseBison.y" { } #line 33575 "VParseBison.c" break; case 2060: /* junkToSemi: "checker" */ #line 3616 "VParseBison.y" { } #line 33581 "VParseBison.c" break; case 2061: /* junkToSemi: "class" */ #line 3616 "VParseBison.y" { } #line 33587 "VParseBison.c" break; case 2062: /* junkToSemi: "clock" */ #line 3616 "VParseBison.y" { } #line 33593 "VParseBison.c" break; case 2063: /* junkToSemi: "clocking" */ #line 3616 "VParseBison.y" { } #line 33599 "VParseBison.c" break; case 2064: /* junkToSemi: "constraint" */ #line 3616 "VParseBison.y" { } #line 33605 "VParseBison.c" break; case 2065: /* junkToSemi: "const" */ #line 3616 "VParseBison.y" { } #line 33611 "VParseBison.c" break; case 2066: /* junkToSemi: "const-in-lex" */ #line 3616 "VParseBison.y" { } #line 33617 "VParseBison.c" break; case 2067: /* junkToSemi: "const-then-local" */ #line 3616 "VParseBison.y" { } #line 33623 "VParseBison.c" break; case 2068: /* junkToSemi: "const-then-ref" */ #line 3616 "VParseBison.y" { } #line 33629 "VParseBison.c" break; case 2069: /* junkToSemi: "context" */ #line 3616 "VParseBison.y" { } #line 33635 "VParseBison.c" break; case 2070: /* junkToSemi: "continue" */ #line 3616 "VParseBison.y" { } #line 33641 "VParseBison.c" break; case 2071: /* junkToSemi: "cover" */ #line 3616 "VParseBison.y" { } #line 33647 "VParseBison.c" break; case 2072: /* junkToSemi: "covergroup" */ #line 3616 "VParseBison.y" { } #line 33653 "VParseBison.c" break; case 2073: /* junkToSemi: "coverpoint" */ #line 3616 "VParseBison.y" { } #line 33659 "VParseBison.c" break; case 2074: /* junkToSemi: "cross" */ #line 3616 "VParseBison.y" { } #line 33665 "VParseBison.c" break; case 2075: /* junkToSemi: "deassign" */ #line 3616 "VParseBison.y" { } #line 33671 "VParseBison.c" break; case 2076: /* junkToSemi: "default" */ #line 3616 "VParseBison.y" { } #line 33677 "VParseBison.c" break; case 2077: /* junkToSemi: "defparam" */ #line 3616 "VParseBison.y" { } #line 33683 "VParseBison.c" break; case 2078: /* junkToSemi: "disable" */ #line 3616 "VParseBison.y" { } #line 33689 "VParseBison.c" break; case 2079: /* junkToSemi: "dist" */ #line 3616 "VParseBison.y" { } #line 33695 "VParseBison.c" break; case 2080: /* junkToSemi: "do" */ #line 3616 "VParseBison.y" { } #line 33701 "VParseBison.c" break; case 2081: /* junkToSemi: "$error" */ #line 3616 "VParseBison.y" { } #line 33707 "VParseBison.c" break; case 2082: /* junkToSemi: "$fatal" */ #line 3616 "VParseBison.y" { } #line 33713 "VParseBison.c" break; case 2083: /* junkToSemi: "$info" */ #line 3616 "VParseBison.y" { } #line 33719 "VParseBison.c" break; case 2084: /* junkToSemi: "$root" */ #line 3616 "VParseBison.y" { } #line 33725 "VParseBison.c" break; case 2085: /* junkToSemi: "$unit" */ #line 3616 "VParseBison.y" { } #line 33731 "VParseBison.c" break; case 2086: /* junkToSemi: "$warning" */ #line 3616 "VParseBison.y" { } #line 33737 "VParseBison.c" break; case 2087: /* junkToSemi: "edge" */ #line 3616 "VParseBison.y" { } #line 33743 "VParseBison.c" break; case 2088: /* junkToSemi: "else" */ #line 3616 "VParseBison.y" { } #line 33749 "VParseBison.c" break; case 2089: /* junkToSemi: "end" */ #line 3616 "VParseBison.y" { } #line 33755 "VParseBison.c" break; case 2090: /* junkToSemi: "endcase" */ #line 3616 "VParseBison.y" { } #line 33761 "VParseBison.c" break; case 2091: /* junkToSemi: "endchecker" */ #line 3616 "VParseBison.y" { } #line 33767 "VParseBison.c" break; case 2092: /* junkToSemi: "endclass" */ #line 3616 "VParseBison.y" { } #line 33773 "VParseBison.c" break; case 2093: /* junkToSemi: "endclocking" */ #line 3616 "VParseBison.y" { } #line 33779 "VParseBison.c" break; case 2094: /* junkToSemi: "endfunction" */ #line 3616 "VParseBison.y" { } #line 33785 "VParseBison.c" break; case 2095: /* junkToSemi: "endgenerate" */ #line 3616 "VParseBison.y" { } #line 33791 "VParseBison.c" break; case 2096: /* junkToSemi: "endgroup" */ #line 3616 "VParseBison.y" { } #line 33797 "VParseBison.c" break; case 2097: /* junkToSemi: "endinterface" */ #line 3616 "VParseBison.y" { } #line 33803 "VParseBison.c" break; case 2098: /* junkToSemi: "endpackage" */ #line 3616 "VParseBison.y" { } #line 33809 "VParseBison.c" break; case 2099: /* junkToSemi: "endprogram" */ #line 3616 "VParseBison.y" { } #line 33815 "VParseBison.c" break; case 2100: /* junkToSemi: "endproperty" */ #line 3616 "VParseBison.y" { } #line 33821 "VParseBison.c" break; case 2101: /* junkToSemi: "endsequence" */ #line 3616 "VParseBison.y" { } #line 33827 "VParseBison.c" break; case 2102: /* junkToSemi: "endtable" */ #line 3616 "VParseBison.y" { } #line 33833 "VParseBison.c" break; case 2103: /* junkToSemi: "endtask" */ #line 3616 "VParseBison.y" { } #line 33839 "VParseBison.c" break; case 2104: /* junkToSemi: "enum" */ #line 3616 "VParseBison.y" { } #line 33845 "VParseBison.c" break; case 2105: /* junkToSemi: "event" */ #line 3616 "VParseBison.y" { } #line 33851 "VParseBison.c" break; case 2106: /* junkToSemi: "eventually" */ #line 3616 "VParseBison.y" { } #line 33857 "VParseBison.c" break; case 2107: /* junkToSemi: "expect" */ #line 3616 "VParseBison.y" { } #line 33863 "VParseBison.c" break; case 2108: /* junkToSemi: "export" */ #line 3616 "VParseBison.y" { } #line 33869 "VParseBison.c" break; case 2109: /* junkToSemi: "extends" */ #line 3616 "VParseBison.y" { } #line 33875 "VParseBison.c" break; case 2110: /* junkToSemi: "extern" */ #line 3616 "VParseBison.y" { } #line 33881 "VParseBison.c" break; case 2111: /* junkToSemi: "final" */ #line 3616 "VParseBison.y" { } #line 33887 "VParseBison.c" break; case 2112: /* junkToSemi: "first_match" */ #line 3616 "VParseBison.y" { } #line 33893 "VParseBison.c" break; case 2113: /* junkToSemi: "for" */ #line 3616 "VParseBison.y" { } #line 33899 "VParseBison.c" break; case 2114: /* junkToSemi: "force" */ #line 3616 "VParseBison.y" { } #line 33905 "VParseBison.c" break; case 2115: /* junkToSemi: "foreach" */ #line 3616 "VParseBison.y" { } #line 33911 "VParseBison.c" break; case 2116: /* junkToSemi: "forever" */ #line 3616 "VParseBison.y" { } #line 33917 "VParseBison.c" break; case 2117: /* junkToSemi: "fork" */ #line 3616 "VParseBison.y" { } #line 33923 "VParseBison.c" break; case 2118: /* junkToSemi: "forkjoin" */ #line 3616 "VParseBison.y" { } #line 33929 "VParseBison.c" break; case 2119: /* junkToSemi: "function" */ #line 3616 "VParseBison.y" { } #line 33935 "VParseBison.c" break; case 2120: /* junkToSemi: "function-in-lex" */ #line 3616 "VParseBison.y" { } #line 33941 "VParseBison.c" break; case 2121: /* junkToSemi: "function-is-pure-virtual" */ #line 3616 "VParseBison.y" { } #line 33947 "VParseBison.c" break; case 2122: /* junkToSemi: "generate" */ #line 3616 "VParseBison.y" { } #line 33953 "VParseBison.c" break; case 2123: /* junkToSemi: "genvar" */ #line 3616 "VParseBison.y" { } #line 33959 "VParseBison.c" break; case 2124: /* junkToSemi: "global-then-clocking" */ #line 3616 "VParseBison.y" { } #line 33965 "VParseBison.c" break; case 2125: /* junkToSemi: "global-in-lex" */ #line 3616 "VParseBison.y" { } #line 33971 "VParseBison.c" break; case 2126: /* junkToSemi: "if" */ #line 3616 "VParseBison.y" { } #line 33977 "VParseBison.c" break; case 2127: /* junkToSemi: "iff" */ #line 3616 "VParseBison.y" { } #line 33983 "VParseBison.c" break; case 2128: /* junkToSemi: "ignore_bins" */ #line 3616 "VParseBison.y" { } #line 33989 "VParseBison.c" break; case 2129: /* junkToSemi: "illegal_bins" */ #line 3616 "VParseBison.y" { } #line 33995 "VParseBison.c" break; case 2130: /* junkToSemi: "implements" */ #line 3616 "VParseBison.y" { } #line 34001 "VParseBison.c" break; case 2131: /* junkToSemi: "implies" */ #line 3616 "VParseBison.y" { } #line 34007 "VParseBison.c" break; case 2132: /* junkToSemi: "import" */ #line 3616 "VParseBison.y" { } #line 34013 "VParseBison.c" break; case 2133: /* junkToSemi: "initial" */ #line 3616 "VParseBison.y" { } #line 34019 "VParseBison.c" break; case 2134: /* junkToSemi: "inout" */ #line 3616 "VParseBison.y" { } #line 34025 "VParseBison.c" break; case 2135: /* junkToSemi: "input" */ #line 3616 "VParseBison.y" { } #line 34031 "VParseBison.c" break; case 2136: /* junkToSemi: "inside" */ #line 3616 "VParseBison.y" { } #line 34037 "VParseBison.c" break; case 2137: /* junkToSemi: "int" */ #line 3616 "VParseBison.y" { } #line 34043 "VParseBison.c" break; case 2138: /* junkToSemi: "integer" */ #line 3616 "VParseBison.y" { } #line 34049 "VParseBison.c" break; case 2139: /* junkToSemi: "interconnect" */ #line 3616 "VParseBison.y" { } #line 34055 "VParseBison.c" break; case 2140: /* junkToSemi: "interface" */ #line 3616 "VParseBison.y" { } #line 34061 "VParseBison.c" break; case 2141: /* junkToSemi: "intersect" */ #line 3616 "VParseBison.y" { } #line 34067 "VParseBison.c" break; case 2142: /* junkToSemi: "join" */ #line 3616 "VParseBison.y" { } #line 34073 "VParseBison.c" break; case 2143: /* junkToSemi: "let" */ #line 3616 "VParseBison.y" { } #line 34079 "VParseBison.c" break; case 2144: /* junkToSemi: "localparam" */ #line 3616 "VParseBison.y" { } #line 34085 "VParseBison.c" break; case 2145: /* junkToSemi: "local-then-::" */ #line 3616 "VParseBison.y" { } #line 34091 "VParseBison.c" break; case 2146: /* junkToSemi: "local" */ #line 3616 "VParseBison.y" { } #line 34097 "VParseBison.c" break; case 2147: /* junkToSemi: "local-in-lex" */ #line 3616 "VParseBison.y" { } #line 34103 "VParseBison.c" break; case 2148: /* junkToSemi: "logic" */ #line 3616 "VParseBison.y" { } #line 34109 "VParseBison.c" break; case 2149: /* junkToSemi: "longint" */ #line 3616 "VParseBison.y" { } #line 34115 "VParseBison.c" break; case 2150: /* junkToSemi: "matches" */ #line 3616 "VParseBison.y" { } #line 34121 "VParseBison.c" break; case 2151: /* junkToSemi: "modport" */ #line 3616 "VParseBison.y" { } #line 34127 "VParseBison.c" break; case 2152: /* junkToSemi: "module" */ #line 3616 "VParseBison.y" { } #line 34133 "VParseBison.c" break; case 2153: /* junkToSemi: "nand" */ #line 3616 "VParseBison.y" { } #line 34139 "VParseBison.c" break; case 2154: /* junkToSemi: "negedge" */ #line 3616 "VParseBison.y" { } #line 34145 "VParseBison.c" break; case 2155: /* junkToSemi: "nettype" */ #line 3616 "VParseBison.y" { } #line 34151 "VParseBison.c" break; case 2156: /* junkToSemi: "new" */ #line 3616 "VParseBison.y" { } #line 34157 "VParseBison.c" break; case 2157: /* junkToSemi: "new-in-lex" */ #line 3616 "VParseBison.y" { } #line 34163 "VParseBison.c" break; case 2158: /* junkToSemi: "new-then-paren" */ #line 3616 "VParseBison.y" { } #line 34169 "VParseBison.c" break; case 2159: /* junkToSemi: "nexttime" */ #line 3616 "VParseBison.y" { } #line 34175 "VParseBison.c" break; case 2160: /* junkToSemi: "nor" */ #line 3616 "VParseBison.y" { } #line 34181 "VParseBison.c" break; case 2161: /* junkToSemi: "not" */ #line 3616 "VParseBison.y" { } #line 34187 "VParseBison.c" break; case 2162: /* junkToSemi: "null" */ #line 3616 "VParseBison.y" { } #line 34193 "VParseBison.c" break; case 2163: /* junkToSemi: "or" */ #line 3616 "VParseBison.y" { } #line 34199 "VParseBison.c" break; case 2164: /* junkToSemi: "output" */ #line 3616 "VParseBison.y" { } #line 34205 "VParseBison.c" break; case 2165: /* junkToSemi: "package" */ #line 3616 "VParseBison.y" { } #line 34211 "VParseBison.c" break; case 2166: /* junkToSemi: "packed" */ #line 3616 "VParseBison.y" { } #line 34217 "VParseBison.c" break; case 2167: /* junkToSemi: "parameter" */ #line 3616 "VParseBison.y" { } #line 34223 "VParseBison.c" break; case 2168: /* junkToSemi: "posedge" */ #line 3616 "VParseBison.y" { } #line 34229 "VParseBison.c" break; case 2169: /* junkToSemi: "priority" */ #line 3616 "VParseBison.y" { } #line 34235 "VParseBison.c" break; case 2170: /* junkToSemi: "program" */ #line 3616 "VParseBison.y" { } #line 34241 "VParseBison.c" break; case 2171: /* junkToSemi: "property" */ #line 3616 "VParseBison.y" { } #line 34247 "VParseBison.c" break; case 2172: /* junkToSemi: "protected" */ #line 3616 "VParseBison.y" { } #line 34253 "VParseBison.c" break; case 2173: /* junkToSemi: "pure" */ #line 3616 "VParseBison.y" { } #line 34259 "VParseBison.c" break; case 2174: /* junkToSemi: "&&" */ #line 3616 "VParseBison.y" { } #line 34265 "VParseBison.c" break; case 2175: /* junkToSemi: "&&&" */ #line 3616 "VParseBison.y" { } #line 34271 "VParseBison.c" break; case 2176: /* junkToSemi: "&=" */ #line 3616 "VParseBison.y" { } #line 34277 "VParseBison.c" break; case 2177: /* junkToSemi: "*>" */ #line 3616 "VParseBison.y" { } #line 34283 "VParseBison.c" break; case 2178: /* junkToSemi: "@@" */ #line 3616 "VParseBison.y" { } #line 34289 "VParseBison.c" break; case 2179: /* junkToSemi: "[=" */ #line 3616 "VParseBison.y" { } #line 34295 "VParseBison.c" break; case 2180: /* junkToSemi: "[->" */ #line 3616 "VParseBison.y" { } #line 34301 "VParseBison.c" break; case 2181: /* junkToSemi: "[+]" */ #line 3616 "VParseBison.y" { } #line 34307 "VParseBison.c" break; case 2182: /* junkToSemi: "[*" */ #line 3616 "VParseBison.y" { } #line 34313 "VParseBison.c" break; case 2183: /* junkToSemi: "===" */ #line 3616 "VParseBison.y" { } #line 34319 "VParseBison.c" break; case 2184: /* junkToSemi: "!==" */ #line 3616 "VParseBison.y" { } #line 34325 "VParseBison.c" break; case 2185: /* junkToSemi: "::" */ #line 3616 "VParseBison.y" { } #line 34331 "VParseBison.c" break; case 2186: /* junkToSemi: ":/" */ #line 3616 "VParseBison.y" { } #line 34337 "VParseBison.c" break; case 2187: /* junkToSemi: ":=" */ #line 3616 "VParseBison.y" { } #line 34343 "VParseBison.c" break; case 2188: /* junkToSemi: "/=" */ #line 3616 "VParseBison.y" { } #line 34349 "VParseBison.c" break; case 2189: /* junkToSemi: ".*" */ #line 3616 "VParseBison.y" { } #line 34355 "VParseBison.c" break; case 2190: /* junkToSemi: "=>" */ #line 3616 "VParseBison.y" { } #line 34361 "VParseBison.c" break; case 2191: /* junkToSemi: "==" */ #line 3616 "VParseBison.y" { } #line 34367 "VParseBison.c" break; case 2192: /* junkToSemi: ">=" */ #line 3616 "VParseBison.y" { } #line 34373 "VParseBison.c" break; case 2193: /* junkToSemi: "<=" */ #line 3616 "VParseBison.y" { } #line 34379 "VParseBison.c" break; case 2194: /* junkToSemi: "<=-ignored" */ #line 3616 "VParseBison.y" { } #line 34385 "VParseBison.c" break; case 2195: /* junkToSemi: "<->" */ #line 3616 "VParseBison.y" { } #line 34391 "VParseBison.c" break; case 2196: /* junkToSemi: "-:" */ #line 3616 "VParseBison.y" { } #line 34397 "VParseBison.c" break; case 2197: /* junkToSemi: "-=" */ #line 3616 "VParseBison.y" { } #line 34403 "VParseBison.c" break; case 2198: /* junkToSemi: "->" */ #line 3616 "VParseBison.y" { } #line 34409 "VParseBison.c" break; case 2199: /* junkToSemi: "->>" */ #line 3616 "VParseBison.y" { } #line 34415 "VParseBison.c" break; case 2200: /* junkToSemi: "--" */ #line 3616 "VParseBison.y" { } #line 34421 "VParseBison.c" break; case 2201: /* junkToSemi: "%=" */ #line 3616 "VParseBison.y" { } #line 34427 "VParseBison.c" break; case 2202: /* junkToSemi: "~&" */ #line 3616 "VParseBison.y" { } #line 34433 "VParseBison.c" break; case 2203: /* junkToSemi: "~|" */ #line 3616 "VParseBison.y" { } #line 34439 "VParseBison.c" break; case 2204: /* junkToSemi: "!=" */ #line 3616 "VParseBison.y" { } #line 34445 "VParseBison.c" break; case 2205: /* junkToSemi: "|=" */ #line 3616 "VParseBison.y" { } #line 34451 "VParseBison.c" break; case 2206: /* junkToSemi: "|=>" */ #line 3616 "VParseBison.y" { } #line 34457 "VParseBison.c" break; case 2207: /* junkToSemi: "|->" */ #line 3616 "VParseBison.y" { } #line 34463 "VParseBison.c" break; case 2208: /* junkToSemi: "||" */ #line 3616 "VParseBison.y" { } #line 34469 "VParseBison.c" break; case 2209: /* junkToSemi: "(-ignored" */ #line 3616 "VParseBison.y" { } #line 34475 "VParseBison.c" break; case 2210: /* junkToSemi: "(-for-strength" */ #line 3616 "VParseBison.y" { } #line 34481 "VParseBison.c" break; case 2211: /* junkToSemi: "+:" */ #line 3616 "VParseBison.y" { } #line 34487 "VParseBison.c" break; case 2212: /* junkToSemi: "+=" */ #line 3616 "VParseBison.y" { } #line 34493 "VParseBison.c" break; case 2213: /* junkToSemi: "++" */ #line 3616 "VParseBison.y" { } #line 34499 "VParseBison.c" break; case 2214: /* junkToSemi: "#=#" */ #line 3616 "VParseBison.y" { } #line 34505 "VParseBison.c" break; case 2215: /* junkToSemi: "#-#" */ #line 3616 "VParseBison.y" { } #line 34511 "VParseBison.c" break; case 2216: /* junkToSemi: "##" */ #line 3616 "VParseBison.y" { } #line 34517 "VParseBison.c" break; case 2217: /* junkToSemi: "**" */ #line 3616 "VParseBison.y" { } #line 34523 "VParseBison.c" break; case 2218: /* junkToSemi: "<<" */ #line 3616 "VParseBison.y" { } #line 34529 "VParseBison.c" break; case 2219: /* junkToSemi: "<<=" */ #line 3616 "VParseBison.y" { } #line 34535 "VParseBison.c" break; case 2220: /* junkToSemi: ">>" */ #line 3616 "VParseBison.y" { } #line 34541 "VParseBison.c" break; case 2221: /* junkToSemi: ">>=" */ #line 3616 "VParseBison.y" { } #line 34547 "VParseBison.c" break; case 2222: /* junkToSemi: ">>>" */ #line 3616 "VParseBison.y" { } #line 34553 "VParseBison.c" break; case 2223: /* junkToSemi: ">>>=" */ #line 3616 "VParseBison.y" { } #line 34559 "VParseBison.c" break; case 2224: /* junkToSemi: "'" */ #line 3616 "VParseBison.y" { } #line 34565 "VParseBison.c" break; case 2225: /* junkToSemi: "'{" */ #line 3616 "VParseBison.y" { } #line 34571 "VParseBison.c" break; case 2226: /* junkToSemi: "*=" */ #line 3616 "VParseBison.y" { } #line 34577 "VParseBison.c" break; case 2227: /* junkToSemi: "==?" */ #line 3616 "VParseBison.y" { } #line 34583 "VParseBison.c" break; case 2228: /* junkToSemi: "!=?" */ #line 3616 "VParseBison.y" { } #line 34589 "VParseBison.c" break; case 2229: /* junkToSemi: "^~" */ #line 3616 "VParseBison.y" { } #line 34595 "VParseBison.c" break; case 2230: /* junkToSemi: "^=" */ #line 3616 "VParseBison.y" { } #line 34601 "VParseBison.c" break; case 2231: /* junkToSemi: "rand" */ #line 3616 "VParseBison.y" { } #line 34607 "VParseBison.c" break; case 2232: /* junkToSemi: "randc" */ #line 3616 "VParseBison.y" { } #line 34613 "VParseBison.c" break; case 2233: /* junkToSemi: "randcase" */ #line 3616 "VParseBison.y" { } #line 34619 "VParseBison.c" break; case 2234: /* junkToSemi: "randsequence" */ #line 3616 "VParseBison.y" { } #line 34625 "VParseBison.c" break; case 2235: /* junkToSemi: "real" */ #line 3616 "VParseBison.y" { } #line 34631 "VParseBison.c" break; case 2236: /* junkToSemi: "realtime" */ #line 3616 "VParseBison.y" { } #line 34637 "VParseBison.c" break; case 2237: /* junkToSemi: "ref" */ #line 3616 "VParseBison.y" { } #line 34643 "VParseBison.c" break; case 2238: /* junkToSemi: "reg" */ #line 3616 "VParseBison.y" { } #line 34649 "VParseBison.c" break; case 2239: /* junkToSemi: "reject_on" */ #line 3616 "VParseBison.y" { } #line 34655 "VParseBison.c" break; case 2240: /* junkToSemi: "release" */ #line 3616 "VParseBison.y" { } #line 34661 "VParseBison.c" break; case 2241: /* junkToSemi: "repeat" */ #line 3616 "VParseBison.y" { } #line 34667 "VParseBison.c" break; case 2242: /* junkToSemi: "restrict" */ #line 3616 "VParseBison.y" { } #line 34673 "VParseBison.c" break; case 2243: /* junkToSemi: "return" */ #line 3616 "VParseBison.y" { } #line 34679 "VParseBison.c" break; case 2244: /* junkToSemi: "scalared" */ #line 3616 "VParseBison.y" { } #line 34685 "VParseBison.c" break; case 2245: /* junkToSemi: "sequence" */ #line 3616 "VParseBison.y" { } #line 34691 "VParseBison.c" break; case 2246: /* junkToSemi: "shortint" */ #line 3616 "VParseBison.y" { } #line 34697 "VParseBison.c" break; case 2247: /* junkToSemi: "shortreal" */ #line 3616 "VParseBison.y" { } #line 34703 "VParseBison.c" break; case 2248: /* junkToSemi: "signed" */ #line 3616 "VParseBison.y" { } #line 34709 "VParseBison.c" break; case 2249: /* junkToSemi: "soft" */ #line 3616 "VParseBison.y" { } #line 34715 "VParseBison.c" break; case 2250: /* junkToSemi: "solve" */ #line 3616 "VParseBison.y" { } #line 34721 "VParseBison.c" break; case 2251: /* junkToSemi: "specify" */ #line 3616 "VParseBison.y" { } #line 34727 "VParseBison.c" break; case 2252: /* junkToSemi: "specparam" */ #line 3616 "VParseBison.y" { } #line 34733 "VParseBison.c" break; case 2253: /* junkToSemi: "static-then-constraint" */ #line 3616 "VParseBison.y" { } #line 34739 "VParseBison.c" break; case 2254: /* junkToSemi: "static" */ #line 3616 "VParseBison.y" { } #line 34745 "VParseBison.c" break; case 2255: /* junkToSemi: "static-in-lex" */ #line 3616 "VParseBison.y" { } #line 34751 "VParseBison.c" break; case 2256: /* junkToSemi: "string" */ #line 3616 "VParseBison.y" { } #line 34757 "VParseBison.c" break; case 2257: /* junkToSemi: "strong" */ #line 3616 "VParseBison.y" { } #line 34763 "VParseBison.c" break; case 2258: /* junkToSemi: "struct" */ #line 3616 "VParseBison.y" { } #line 34769 "VParseBison.c" break; case 2259: /* junkToSemi: "super" */ #line 3616 "VParseBison.y" { } #line 34775 "VParseBison.c" break; case 2260: /* junkToSemi: "supply0" */ #line 3616 "VParseBison.y" { } #line 34781 "VParseBison.c" break; case 2261: /* junkToSemi: "supply1" */ #line 3616 "VParseBison.y" { } #line 34787 "VParseBison.c" break; case 2262: /* junkToSemi: "sync_accept_on" */ #line 3616 "VParseBison.y" { } #line 34793 "VParseBison.c" break; case 2263: /* junkToSemi: "sync_reject_on" */ #line 3616 "VParseBison.y" { } #line 34799 "VParseBison.c" break; case 2264: /* junkToSemi: "s_always" */ #line 3616 "VParseBison.y" { } #line 34805 "VParseBison.c" break; case 2265: /* junkToSemi: "s_eventually" */ #line 3616 "VParseBison.y" { } #line 34811 "VParseBison.c" break; case 2266: /* junkToSemi: "s_nexttime" */ #line 3616 "VParseBison.y" { } #line 34817 "VParseBison.c" break; case 2267: /* junkToSemi: "s_until" */ #line 3616 "VParseBison.y" { } #line 34823 "VParseBison.c" break; case 2268: /* junkToSemi: "s_until_with" */ #line 3616 "VParseBison.y" { } #line 34829 "VParseBison.c" break; case 2269: /* junkToSemi: "table" */ #line 3616 "VParseBison.y" { } #line 34835 "VParseBison.c" break; case 2270: /* junkToSemi: "tagged" */ #line 3616 "VParseBison.y" { } #line 34841 "VParseBison.c" break; case 2271: /* junkToSemi: "task" */ #line 3616 "VParseBison.y" { } #line 34847 "VParseBison.c" break; case 2272: /* junkToSemi: "task-in-lex" */ #line 3616 "VParseBison.y" { } #line 34853 "VParseBison.c" break; case 2273: /* junkToSemi: "task-is-pure-virtual" */ #line 3616 "VParseBison.y" { } #line 34859 "VParseBison.c" break; case 2274: /* junkToSemi: "this" */ #line 3616 "VParseBison.y" { } #line 34865 "VParseBison.c" break; case 2275: /* junkToSemi: "throughout" */ #line 3616 "VParseBison.y" { } #line 34871 "VParseBison.c" break; case 2276: /* junkToSemi: "time" */ #line 3616 "VParseBison.y" { } #line 34877 "VParseBison.c" break; case 2277: /* junkToSemi: "timeprecision" */ #line 3616 "VParseBison.y" { } #line 34883 "VParseBison.c" break; case 2278: /* junkToSemi: "timeunit" */ #line 3616 "VParseBison.y" { } #line 34889 "VParseBison.c" break; case 2279: /* junkToSemi: "tri" */ #line 3616 "VParseBison.y" { } #line 34895 "VParseBison.c" break; case 2280: /* junkToSemi: "tri0" */ #line 3616 "VParseBison.y" { } #line 34901 "VParseBison.c" break; case 2281: /* junkToSemi: "tri1" */ #line 3616 "VParseBison.y" { } #line 34907 "VParseBison.c" break; case 2282: /* junkToSemi: "triand" */ #line 3616 "VParseBison.y" { } #line 34913 "VParseBison.c" break; case 2283: /* junkToSemi: "trior" */ #line 3616 "VParseBison.y" { } #line 34919 "VParseBison.c" break; case 2284: /* junkToSemi: "trireg" */ #line 3616 "VParseBison.y" { } #line 34925 "VParseBison.c" break; case 2285: /* junkToSemi: "type" */ #line 3616 "VParseBison.y" { } #line 34931 "VParseBison.c" break; case 2286: /* junkToSemi: "typedef" */ #line 3616 "VParseBison.y" { } #line 34937 "VParseBison.c" break; case 2287: /* junkToSemi: "union" */ #line 3616 "VParseBison.y" { } #line 34943 "VParseBison.c" break; case 2288: /* junkToSemi: "unique" */ #line 3616 "VParseBison.y" { } #line 34949 "VParseBison.c" break; case 2289: /* junkToSemi: "unique0" */ #line 3616 "VParseBison.y" { } #line 34955 "VParseBison.c" break; case 2290: /* junkToSemi: "unsigned" */ #line 3616 "VParseBison.y" { } #line 34961 "VParseBison.c" break; case 2291: /* junkToSemi: "until" */ #line 3616 "VParseBison.y" { } #line 34967 "VParseBison.c" break; case 2292: /* junkToSemi: "until_with" */ #line 3616 "VParseBison.y" { } #line 34973 "VParseBison.c" break; case 2293: /* junkToSemi: "untyped" */ #line 3616 "VParseBison.y" { } #line 34979 "VParseBison.c" break; case 2294: /* junkToSemi: "var" */ #line 3616 "VParseBison.y" { } #line 34985 "VParseBison.c" break; case 2295: /* junkToSemi: "vectored" */ #line 3616 "VParseBison.y" { } #line 34991 "VParseBison.c" break; case 2296: /* junkToSemi: "virtual-then-class" */ #line 3616 "VParseBison.y" { } #line 34997 "VParseBison.c" break; case 2297: /* junkToSemi: "virtual" */ #line 3616 "VParseBison.y" { } #line 35003 "VParseBison.c" break; case 2298: /* junkToSemi: "virtual-then-interface" */ #line 3616 "VParseBison.y" { } #line 35009 "VParseBison.c" break; case 2299: /* junkToSemi: "virtual-in-lex" */ #line 3616 "VParseBison.y" { } #line 35015 "VParseBison.c" break; case 2300: /* junkToSemi: "virtual-then-identifier" */ #line 3616 "VParseBison.y" { } #line 35021 "VParseBison.c" break; case 2301: /* junkToSemi: "void" */ #line 3616 "VParseBison.y" { } #line 35027 "VParseBison.c" break; case 2302: /* junkToSemi: "wait" */ #line 3616 "VParseBison.y" { } #line 35033 "VParseBison.c" break; case 2303: /* junkToSemi: "wait_order" */ #line 3616 "VParseBison.y" { } #line 35039 "VParseBison.c" break; case 2304: /* junkToSemi: "wand" */ #line 3616 "VParseBison.y" { } #line 35045 "VParseBison.c" break; case 2305: /* junkToSemi: "weak" */ #line 3616 "VParseBison.y" { } #line 35051 "VParseBison.c" break; case 2306: /* junkToSemi: "while" */ #line 3616 "VParseBison.y" { } #line 35057 "VParseBison.c" break; case 2307: /* junkToSemi: "wildcard" */ #line 3616 "VParseBison.y" { } #line 35063 "VParseBison.c" break; case 2308: /* junkToSemi: "wire" */ #line 3616 "VParseBison.y" { } #line 35069 "VParseBison.c" break; case 2309: /* junkToSemi: "within" */ #line 3616 "VParseBison.y" { } #line 35075 "VParseBison.c" break; case 2310: /* junkToSemi: "with-then-[" */ #line 3616 "VParseBison.y" { } #line 35081 "VParseBison.c" break; case 2311: /* junkToSemi: "with-then-{" */ #line 3616 "VParseBison.y" { } #line 35087 "VParseBison.c" break; case 2312: /* junkToSemi: "with" */ #line 3616 "VParseBison.y" { } #line 35093 "VParseBison.c" break; case 2313: /* junkToSemi: "with-in-lex" */ #line 3616 "VParseBison.y" { } #line 35099 "VParseBison.c" break; case 2314: /* junkToSemi: "with-then-(" */ #line 3616 "VParseBison.y" { } #line 35105 "VParseBison.c" break; case 2315: /* junkToSemi: "wor" */ #line 3616 "VParseBison.y" { } #line 35111 "VParseBison.c" break; case 2316: /* junkToSemi: "xnor" */ #line 3616 "VParseBison.y" { } #line 35117 "VParseBison.c" break; case 2317: /* junkToSemi: "xor" */ #line 3616 "VParseBison.y" { } #line 35123 "VParseBison.c" break; case 2318: /* junkToSemi: "FLOATING-POINT NUMBER" */ #line 3616 "VParseBison.y" { } #line 35129 "VParseBison.c" break; case 2319: /* junkToSemi: "IDENTIFIER" */ #line 3616 "VParseBison.y" { } #line 35135 "VParseBison.c" break; case 2320: /* junkToSemi: "IDENTIFIER-in-lex" */ #line 3616 "VParseBison.y" { } #line 35141 "VParseBison.c" break; case 2321: /* junkToSemi: "PACKAGE-IDENTIFIER" */ #line 3616 "VParseBison.y" { } #line 35147 "VParseBison.c" break; case 2322: /* junkToSemi: "TYPE-IDENTIFIER" */ #line 3616 "VParseBison.y" { } #line 35153 "VParseBison.c" break; case 2323: /* junkToSemi: "INTEGER NUMBER" */ #line 3616 "VParseBison.y" { } #line 35159 "VParseBison.c" break; case 2324: /* junkToSemi: "STRING" */ #line 3616 "VParseBison.y" { } #line 35165 "VParseBison.c" break; case 2325: /* junkToSemi: "STRING-ignored" */ #line 3616 "VParseBison.y" { } #line 35171 "VParseBison.c" break; case 2326: /* junkToSemi: "TIME NUMBER" */ #line 3616 "VParseBison.y" { } #line 35177 "VParseBison.c" break; case 2327: /* junkToSemi: "TIMING SPEC ELEMENT" */ #line 3616 "VParseBison.y" { } #line 35183 "VParseBison.c" break; case 2328: /* junkToSemi: "CONFIG keyword (cell/use/design/etc)" */ #line 3616 "VParseBison.y" { } #line 35189 "VParseBison.c" break; case 2329: /* junkToSemi: "GATE keyword" */ #line 3616 "VParseBison.y" { } #line 35195 "VParseBison.c" break; case 2330: /* junkToSemi: "OPERATOR" */ #line 3616 "VParseBison.y" { } #line 35201 "VParseBison.c" break; case 2331: /* junkToSemi: "STRENGTH keyword (strong1/etc)" */ #line 3616 "VParseBison.y" { } #line 35207 "VParseBison.c" break; case 2332: /* junkToSemi: "SYSCALL" */ #line 3616 "VParseBison.y" { } #line 35213 "VParseBison.c" break; case 2333: /* junkToSemi: error */ #line 3617 "VParseBison.y" {} #line 35219 "VParseBison.c" break; case 2334: /* id: "IDENTIFIER" */ #line 3624 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 35225 "VParseBison.c" break; case 2335: /* idAny: "PACKAGE-IDENTIFIER" */ #line 3628 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 35231 "VParseBison.c" break; case 2336: /* idAny: "TYPE-IDENTIFIER" */ #line 3629 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 35237 "VParseBison.c" break; case 2337: /* idAny: "IDENTIFIER" */ #line 3630 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 35243 "VParseBison.c" break; case 2338: /* idSVKwd: "do" */ #line 3635 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); ERRSVKWD((yyvsp[0].fl),(yyval.str)); } #line 35249 "VParseBison.c" break; case 2339: /* idSVKwd: "final" */ #line 3636 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); ERRSVKWD((yyvsp[0].fl),(yyval.str)); } #line 35255 "VParseBison.c" break; case 2340: /* variable_lvalue: idClassSel */ #line 3641 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 35261 "VParseBison.c" break; case 2341: /* variable_lvalue: '{' variable_lvalueConcList '}' */ #line 3642 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 35267 "VParseBison.c" break; case 2342: /* variable_lvalue: data_type "'{" variable_lvalueList '}' */ #line 3645 "VParseBison.y" { (yyval.fl)=(yyvsp[-3].fl); (yyval.str) = (yyvsp[-3].str)+" "+(yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 35273 "VParseBison.c" break; case 2343: /* variable_lvalue: idClassSel "'{" variable_lvalueList '}' */ #line 3646 "VParseBison.y" { (yyval.fl)=(yyvsp[-3].fl); (yyval.str) = (yyvsp[-3].str)+" "+(yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 35279 "VParseBison.c" break; case 2344: /* variable_lvalue: "'{" variable_lvalueList '}' */ #line 3647 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 35285 "VParseBison.c" break; case 2345: /* variable_lvalue: streaming_concatenation */ #line 3648 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 35291 "VParseBison.c" break; case 2346: /* variable_lvalueConcList: variable_lvalue */ #line 3652 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 35297 "VParseBison.c" break; case 2347: /* variable_lvalueConcList: variable_lvalueConcList ',' variable_lvalue */ #line 3653 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+","+(yyvsp[0].str); } #line 35303 "VParseBison.c" break; case 2348: /* variable_lvalueList: variable_lvalue */ #line 3657 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 35309 "VParseBison.c" break; case 2349: /* variable_lvalueList: variable_lvalueList ',' variable_lvalue */ #line 3658 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+","+(yyvsp[0].str); } #line 35315 "VParseBison.c" break; case 2350: /* idClassSel: idDotted */ #line 3662 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 35321 "VParseBison.c" break; case 2351: /* idClassSel: "this" '.' idDotted */ #line 3664 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = "this."+(yyvsp[0].str); } #line 35327 "VParseBison.c" break; case 2352: /* idClassSel: "super" '.' idDotted */ #line 3665 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = "super."+(yyvsp[0].str); } #line 35333 "VParseBison.c" break; case 2353: /* idClassSel: "this" '.' "super" '.' idDotted */ #line 3666 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "this.super."+(yyvsp[-2].str); } #line 35339 "VParseBison.c" break; case 2354: /* idClassSel: class_scopeIdFollows idDotted */ #line 3668 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 35345 "VParseBison.c" break; case 2355: /* idClassSel: package_scopeIdFollows idDotted */ #line 3669 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 35351 "VParseBison.c" break; case 2356: /* idClassForeach: idDottedForeach */ #line 3675 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 35357 "VParseBison.c" break; case 2357: /* idClassForeach: "this" '.' idDottedForeach */ #line 3677 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = "this."+(yyvsp[0].str); } #line 35363 "VParseBison.c" break; case 2358: /* idClassForeach: "super" '.' idDottedForeach */ #line 3678 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = "super."+(yyvsp[0].str); } #line 35369 "VParseBison.c" break; case 2359: /* idClassForeach: "this" '.' "super" '.' idDottedForeach */ #line 3679 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "this.super."+(yyvsp[-2].str); } #line 35375 "VParseBison.c" break; case 2360: /* idClassForeach: class_scopeIdFollows idDottedForeach */ #line 3681 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 35381 "VParseBison.c" break; case 2361: /* idClassForeach: package_scopeIdFollows idDottedForeach */ #line 3682 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 35387 "VParseBison.c" break; case 2362: /* hierarchical_identifierList: hierarchical_identifier */ #line 3686 "VParseBison.y" { } #line 35393 "VParseBison.c" break; case 2363: /* hierarchical_identifierList: hierarchical_identifierList ',' hierarchical_identifier */ #line 3687 "VParseBison.y" { } #line 35399 "VParseBison.c" break; case 2364: /* hierarchical_identifierBit: idClassSel */ #line 3692 "VParseBison.y" { } #line 35405 "VParseBison.c" break; case 2365: /* hierarchical_identifier: idClassSel */ #line 3698 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 35411 "VParseBison.c" break; case 2366: /* idDotted: "$root" '.' idDottedMore */ #line 3702 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+"."+(yyvsp[0].str); } #line 35417 "VParseBison.c" break; case 2367: /* idDotted: idDottedMore */ #line 3703 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 35423 "VParseBison.c" break; case 2368: /* idDottedForeach: "$root" '.' idDottedForeachMore */ #line 3707 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+"."+(yyvsp[0].str); } #line 35429 "VParseBison.c" break; case 2369: /* idDottedForeach: idDottedForeachMore */ #line 3708 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 35435 "VParseBison.c" break; case 2370: /* idDottedMore: idArrayed */ #line 3712 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 35441 "VParseBison.c" break; case 2371: /* idDottedMore: idDottedMore '.' idArrayed */ #line 3713 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+"."+(yyvsp[0].str); } #line 35447 "VParseBison.c" break; case 2372: /* idDottedForeachMore: idForeach */ #line 3717 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 35453 "VParseBison.c" break; case 2373: /* idDottedForeachMore: idDottedForeachMore '.' idForeach */ #line 3718 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+"."+(yyvsp[0].str); } #line 35459 "VParseBison.c" break; case 2374: /* idArrayed: id */ #line 3727 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); PORTNET((yyvsp[0].fl), (yyvsp[0].str));} #line 35465 "VParseBison.c" break; case 2375: /* idArrayed: idArrayed '[' expr ']' */ #line 3729 "VParseBison.y" { (yyval.fl)=(yyvsp[-3].fl); (yyval.str) = (yyvsp[-3].str)+"["+(yyvsp[-1].str)+"]"; PORTRANGE((yyvsp[-1].str), (yyvsp[-1].str));} #line 35471 "VParseBison.c" break; case 2376: /* idArrayed: idArrayed '[' constExpr ':' constExpr ']' */ #line 3730 "VParseBison.y" { (yyval.fl)=(yyvsp[-5].fl); (yyval.str) = (yyvsp[-5].str)+"["+(yyvsp[-3].str)+":"+(yyvsp[-1].str)+"]"; PORTRANGE((yyvsp[-3].str), (yyvsp[-1].str));} #line 35477 "VParseBison.c" break; case 2377: /* idArrayed: idArrayed '[' expr "+:" constExpr ']' */ #line 3732 "VParseBison.y" { (yyval.fl)=(yyvsp[-5].fl); (yyval.str) = (yyvsp[-5].str)+"["+(yyvsp[-3].str)+"+:"+(yyvsp[-1].str)+"]"; } #line 35483 "VParseBison.c" break; case 2378: /* idArrayed: idArrayed '[' expr "-:" constExpr ']' */ #line 3733 "VParseBison.y" { (yyval.fl)=(yyvsp[-5].fl); (yyval.str) = (yyvsp[-5].str)+"["+(yyvsp[-3].str)+"-:"+(yyvsp[-1].str)+"]"; } #line 35489 "VParseBison.c" break; case 2379: /* idForeach: id */ #line 3738 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 35495 "VParseBison.c" break; case 2380: /* idForeach: idForeach '[' expr ']' */ #line 3740 "VParseBison.y" { (yyval.fl)=(yyvsp[-3].fl); (yyval.str) = (yyvsp[-3].str)+"["+(yyvsp[-1].str)+"]"; } #line 35501 "VParseBison.c" break; case 2381: /* idForeach: idForeach '[' constExpr ':' constExpr ']' */ #line 3741 "VParseBison.y" { (yyval.fl)=(yyvsp[-5].fl); (yyval.str) = (yyvsp[-5].str)+"["+(yyvsp[-3].str)+":"+(yyvsp[-1].str)+"]"; } #line 35507 "VParseBison.c" break; case 2382: /* idForeach: idForeach '[' expr "+:" constExpr ']' */ #line 3743 "VParseBison.y" { (yyval.fl)=(yyvsp[-5].fl); (yyval.str) = (yyvsp[-5].str)+"["+(yyvsp[-3].str)+"+:"+(yyvsp[-1].str)+"]"; } #line 35513 "VParseBison.c" break; case 2383: /* idForeach: idForeach '[' expr "-:" constExpr ']' */ #line 3744 "VParseBison.y" { (yyval.fl)=(yyvsp[-5].fl); (yyval.str) = (yyvsp[-5].str)+"["+(yyvsp[-3].str)+"-:"+(yyvsp[-1].str)+"]"; } #line 35519 "VParseBison.c" break; case 2384: /* idForeach: idForeach '[' expr ',' loop_variables ']' */ #line 3746 "VParseBison.y" { (yyval.fl)=(yyvsp[-5].fl); (yyval.str) = (yyvsp[-5].str)+"["+(yyvsp[-3].str)+","+(yyvsp[-1].str)+"]"; } #line 35525 "VParseBison.c" break; case 2385: /* strAsInt: "STRING" */ #line 3750 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 35531 "VParseBison.c" break; case 2386: /* endLabelE: %empty */ #line 3754 "VParseBison.y" { } #line 35537 "VParseBison.c" break; case 2387: /* endLabelE: ':' idAny */ #line 3755 "VParseBison.y" { } #line 35543 "VParseBison.c" break; case 2388: /* endLabelE: ':' "new" */ #line 3756 "VParseBison.y" { } #line 35549 "VParseBison.c" break; case 2389: /* clocking_declaration: clockingFront clocking_event ';' clocking_itemListE "endclocking" endLabelE */ #line 3764 "VParseBison.y" { PARSEP->symPopScope(VAstType::CLOCKING); } #line 35555 "VParseBison.c" break; case 2390: /* clockingFront: "clocking" */ #line 3769 "VParseBison.y" { PARSEP->symPushNewAnon(VAstType::CLOCKING); } #line 35561 "VParseBison.c" break; case 2391: /* clockingFront: "clocking" idAny */ #line 3770 "VParseBison.y" { PARSEP->symPushNew(VAstType::CLOCKING,(yyvsp[0].str)); } #line 35567 "VParseBison.c" break; case 2392: /* clockingFront: "default" "clocking" */ #line 3771 "VParseBison.y" { PARSEP->symPushNewAnon(VAstType::CLOCKING); } #line 35573 "VParseBison.c" break; case 2393: /* clockingFront: "default" "clocking" idAny */ #line 3772 "VParseBison.y" { PARSEP->symPushNew(VAstType::CLOCKING,(yyvsp[0].str)); } #line 35579 "VParseBison.c" break; case 2394: /* clockingFront: "global-then-clocking" "clocking" */ #line 3773 "VParseBison.y" { PARSEP->symPushNewAnon(VAstType::CLOCKING); } #line 35585 "VParseBison.c" break; case 2395: /* clockingFront: "global-then-clocking" "clocking" idAny */ #line 3774 "VParseBison.y" { PARSEP->symPushNew(VAstType::CLOCKING,(yyvsp[0].str)); } #line 35591 "VParseBison.c" break; case 2396: /* clocking_event: '@' id */ #line 3778 "VParseBison.y" { } #line 35597 "VParseBison.c" break; case 2397: /* clocking_event: '@' '(' event_expression ')' */ #line 3779 "VParseBison.y" { } #line 35603 "VParseBison.c" break; case 2398: /* clocking_itemListE: %empty */ #line 3783 "VParseBison.y" { } #line 35609 "VParseBison.c" break; case 2399: /* clocking_itemListE: clocking_itemList */ #line 3784 "VParseBison.y" { } #line 35615 "VParseBison.c" break; case 2400: /* clocking_itemList: clocking_item */ #line 3788 "VParseBison.y" { } #line 35621 "VParseBison.c" break; case 2401: /* clocking_itemList: clocking_itemList clocking_item */ #line 3789 "VParseBison.y" { } #line 35627 "VParseBison.c" break; case 2402: /* clocking_item: "default" default_skew ';' */ #line 3793 "VParseBison.y" { } #line 35633 "VParseBison.c" break; case 2403: /* clocking_item: clocking_direction list_of_clocking_decl_assign ';' */ #line 3794 "VParseBison.y" { } #line 35639 "VParseBison.c" break; case 2404: /* clocking_item: assertion_item_declaration */ #line 3795 "VParseBison.y" { } #line 35645 "VParseBison.c" break; case 2405: /* default_skew: "input" clocking_skew */ #line 3799 "VParseBison.y" { } #line 35651 "VParseBison.c" break; case 2406: /* default_skew: "output" clocking_skew */ #line 3800 "VParseBison.y" { } #line 35657 "VParseBison.c" break; case 2407: /* default_skew: "input" clocking_skew "output" clocking_skew */ #line 3801 "VParseBison.y" { } #line 35663 "VParseBison.c" break; case 2408: /* clocking_direction: "input" clocking_skewE */ #line 3805 "VParseBison.y" { } #line 35669 "VParseBison.c" break; case 2409: /* clocking_direction: "output" clocking_skewE */ #line 3806 "VParseBison.y" { } #line 35675 "VParseBison.c" break; case 2410: /* clocking_direction: "input" clocking_skewE "output" clocking_skewE */ #line 3807 "VParseBison.y" { } #line 35681 "VParseBison.c" break; case 2411: /* clocking_direction: "inout" */ #line 3808 "VParseBison.y" { } #line 35687 "VParseBison.c" break; case 2412: /* list_of_clocking_decl_assign: clocking_decl_assign */ #line 3812 "VParseBison.y" { } #line 35693 "VParseBison.c" break; case 2413: /* list_of_clocking_decl_assign: list_of_clocking_decl_assign ',' clocking_decl_assign */ #line 3813 "VParseBison.y" { } #line 35699 "VParseBison.c" break; case 2414: /* clocking_decl_assign: idAny */ #line 3817 "VParseBison.y" { } #line 35705 "VParseBison.c" break; case 2415: /* clocking_decl_assign: idAny '=' expr */ #line 3818 "VParseBison.y" { } #line 35711 "VParseBison.c" break; case 2416: /* clocking_skewE: %empty */ #line 3822 "VParseBison.y" { } #line 35717 "VParseBison.c" break; case 2417: /* clocking_skewE: clocking_skew */ #line 3823 "VParseBison.y" { } #line 35723 "VParseBison.c" break; case 2418: /* clocking_skew: "posedge" */ #line 3827 "VParseBison.y" { } #line 35729 "VParseBison.c" break; case 2419: /* clocking_skew: "posedge" delay_control */ #line 3828 "VParseBison.y" { } #line 35735 "VParseBison.c" break; case 2420: /* clocking_skew: "negedge" */ #line 3829 "VParseBison.y" { } #line 35741 "VParseBison.c" break; case 2421: /* clocking_skew: "negedge" delay_control */ #line 3830 "VParseBison.y" { } #line 35747 "VParseBison.c" break; case 2422: /* clocking_skew: "edge" */ #line 3831 "VParseBison.y" { NEED_S09((yyvsp[0].fl),"edge"); } #line 35753 "VParseBison.c" break; case 2423: /* clocking_skew: "edge" delay_control */ #line 3832 "VParseBison.y" { NEED_S09((yyvsp[-1].fl),"edge"); } #line 35759 "VParseBison.c" break; case 2424: /* clocking_skew: delay_control */ #line 3833 "VParseBison.y" { } #line 35765 "VParseBison.c" break; case 2425: /* cycle_delay: "##" "INTEGER NUMBER" */ #line 3837 "VParseBison.y" { } #line 35771 "VParseBison.c" break; case 2426: /* cycle_delay: "##" id */ #line 3838 "VParseBison.y" { } #line 35777 "VParseBison.c" break; case 2427: /* cycle_delay: "##" '(' expr ')' */ #line 3839 "VParseBison.y" { } #line 35783 "VParseBison.c" break; case 2428: /* assertion_item_declaration: property_declaration */ #line 3846 "VParseBison.y" { } #line 35789 "VParseBison.c" break; case 2429: /* assertion_item_declaration: sequence_declaration */ #line 3847 "VParseBison.y" { } #line 35795 "VParseBison.c" break; case 2430: /* assertion_item_declaration: let_declaration */ #line 3848 "VParseBison.y" { } #line 35801 "VParseBison.c" break; case 2431: /* assertion_item: concurrent_assertion_item */ #line 3852 "VParseBison.y" { } #line 35807 "VParseBison.c" break; case 2432: /* assertion_item: deferred_immediate_assertion_item */ #line 3853 "VParseBison.y" { } #line 35813 "VParseBison.c" break; case 2433: /* deferred_immediate_assertion_item: deferred_immediate_assertion_statement */ #line 3857 "VParseBison.y" { } #line 35819 "VParseBison.c" break; case 2434: /* deferred_immediate_assertion_item: id ':' deferred_immediate_assertion_statement */ #line 3858 "VParseBison.y" { } #line 35825 "VParseBison.c" break; case 2435: /* procedural_assertion_statement: concurrent_assertion_statement */ #line 3862 "VParseBison.y" { } #line 35831 "VParseBison.c" break; case 2436: /* procedural_assertion_statement: immediate_assertion_statement */ #line 3863 "VParseBison.y" { } #line 35837 "VParseBison.c" break; case 2437: /* procedural_assertion_statement: checker_instantiation */ #line 3866 "VParseBison.y" { } #line 35843 "VParseBison.c" break; case 2438: /* immediate_assertion_statement: simple_immediate_assertion_statement */ #line 3870 "VParseBison.y" { } #line 35849 "VParseBison.c" break; case 2439: /* immediate_assertion_statement: deferred_immediate_assertion_statement */ #line 3871 "VParseBison.y" { } #line 35855 "VParseBison.c" break; case 2440: /* simple_immediate_assertion_statement: "assert" '(' expr ')' action_block */ #line 3876 "VParseBison.y" { } #line 35861 "VParseBison.c" break; case 2441: /* simple_immediate_assertion_statement: "assume" '(' expr ')' action_block */ #line 3878 "VParseBison.y" { } #line 35867 "VParseBison.c" break; case 2442: /* simple_immediate_assertion_statement: "cover" '(' expr ')' stmt */ #line 3880 "VParseBison.y" { } #line 35873 "VParseBison.c" break; case 2443: /* final_zero: '#' "INTEGER NUMBER" */ #line 3884 "VParseBison.y" { } #line 35879 "VParseBison.c" break; case 2444: /* final_zero: "final" */ #line 3886 "VParseBison.y" { } #line 35885 "VParseBison.c" break; case 2445: /* deferred_immediate_assertion_statement: "assert" final_zero '(' expr ')' action_block */ #line 3891 "VParseBison.y" { } #line 35891 "VParseBison.c" break; case 2446: /* deferred_immediate_assertion_statement: "assume" final_zero '(' expr ')' action_block */ #line 3893 "VParseBison.y" { } #line 35897 "VParseBison.c" break; case 2447: /* deferred_immediate_assertion_statement: "cover" final_zero '(' expr ')' stmt */ #line 3895 "VParseBison.y" { } #line 35903 "VParseBison.c" break; case 2448: /* expect_property_statement: "expect" '(' property_spec ')' action_block */ #line 3899 "VParseBison.y" { } #line 35909 "VParseBison.c" break; case 2449: /* concurrent_assertion_item: concurrent_assertion_statement */ #line 3903 "VParseBison.y" { } #line 35915 "VParseBison.c" break; case 2450: /* concurrent_assertion_item: id ':' concurrent_assertion_statement */ #line 3904 "VParseBison.y" { } #line 35921 "VParseBison.c" break; case 2451: /* concurrent_assertion_statement: "assert" "property" '(' property_spec ')' action_block */ #line 3911 "VParseBison.y" { } #line 35927 "VParseBison.c" break; case 2452: /* concurrent_assertion_statement: "assume" "property" '(' property_spec ')' action_block */ #line 3913 "VParseBison.y" { } #line 35933 "VParseBison.c" break; case 2453: /* concurrent_assertion_statement: "cover" "property" '(' property_spec ')' stmtBlock */ #line 3915 "VParseBison.y" { } #line 35939 "VParseBison.c" break; case 2454: /* concurrent_assertion_statement: "cover" "sequence" '(' sexpr ')' stmt */ #line 3917 "VParseBison.y" { } #line 35945 "VParseBison.c" break; case 2455: /* concurrent_assertion_statement: "cover" "sequence" '(' clocking_event "disable" "iff" '(' expr ')' sexpr ')' stmt */ #line 3920 "VParseBison.y" { } #line 35951 "VParseBison.c" break; case 2456: /* concurrent_assertion_statement: "cover" "sequence" '(' "disable" "iff" '(' expr ')' sexpr ')' stmt */ #line 3921 "VParseBison.y" { } #line 35957 "VParseBison.c" break; case 2457: /* concurrent_assertion_statement: "restrict" "property" '(' property_spec ')' ';' */ #line 3923 "VParseBison.y" { } #line 35963 "VParseBison.c" break; case 2458: /* property_declaration: property_declarationFront property_port_listE ';' property_declarationBody "endproperty" endLabelE */ #line 3929 "VParseBison.y" { PARSEP->symPopScope(VAstType::PROPERTY); } #line 35969 "VParseBison.c" break; case 2459: /* property_declarationFront: "property" idAny */ #line 3934 "VParseBison.y" { PARSEP->symPushNew(VAstType::PROPERTY,(yyvsp[0].str)); } #line 35975 "VParseBison.c" break; case 2460: /* property_port_listE: %empty */ #line 3938 "VParseBison.y" { } #line 35981 "VParseBison.c" break; case 2461: /* $@20: %empty */ #line 3939 "VParseBison.y" {VARRESET_LIST(""); VARIO("input"); } #line 35987 "VParseBison.c" break; case 2462: /* property_port_listE: '(' $@20 property_port_list ')' */ #line 3940 "VParseBison.y" { VARRESET_NONLIST(""); } #line 35993 "VParseBison.c" break; case 2463: /* property_port_list: property_port_item */ #line 3944 "VParseBison.y" { } #line 35999 "VParseBison.c" break; case 2464: /* property_port_list: property_port_list ',' property_port_item */ #line 3945 "VParseBison.y" { } #line 36005 "VParseBison.c" break; case 2465: /* property_port_item: property_port_itemFront property_port_itemAssignment */ #line 3955 "VParseBison.y" { } #line 36011 "VParseBison.c" break; case 2466: /* property_port_itemFront: property_port_itemDirE property_formal_typeNoDt */ #line 3960 "VParseBison.y" { VARDTYPE((yyvsp[0].str)); } #line 36017 "VParseBison.c" break; case 2467: /* property_port_itemFront: property_port_itemDirE data_type */ #line 3962 "VParseBison.y" { VARDTYPE((yyvsp[0].str)); } #line 36023 "VParseBison.c" break; case 2468: /* property_port_itemFront: property_port_itemDirE "var" data_type */ #line 3963 "VParseBison.y" { VARDTYPE((yyvsp[0].str)); } #line 36029 "VParseBison.c" break; case 2469: /* property_port_itemFront: property_port_itemDirE "var" implicit_typeE */ #line 3964 "VParseBison.y" { VARDTYPE((yyvsp[0].str)); } #line 36035 "VParseBison.c" break; case 2470: /* property_port_itemFront: property_port_itemDirE signingE rangeList */ #line 3965 "VParseBison.y" { VARDTYPE(SPACED((yyvsp[-1].str),(yyvsp[0].str))); } #line 36041 "VParseBison.c" break; case 2471: /* property_port_itemFront: property_port_itemDirE */ #line 3966 "VParseBison.y" { /*VARDTYPE-same*/ } #line 36047 "VParseBison.c" break; case 2472: /* property_port_itemAssignment: portSig variable_dimensionListE */ #line 3970 "VParseBison.y" { VARDONE((yyvsp[-1].fl), (yyvsp[-1].str), (yyvsp[0].str), ""); PINNUMINC(); } #line 36053 "VParseBison.c" break; case 2473: /* property_port_itemAssignment: portSig variable_dimensionListE '=' property_actual_arg */ #line 3972 "VParseBison.y" { VARDONE((yyvsp[-3].fl), (yyvsp[-3].str), (yyvsp[-2].str), (yyvsp[0].str)); PINNUMINC(); } #line 36059 "VParseBison.c" break; case 2474: /* property_port_itemDirE: %empty */ #line 3976 "VParseBison.y" { } #line 36065 "VParseBison.c" break; case 2475: /* property_port_itemDirE: "local" */ #line 3977 "VParseBison.y" { } #line 36071 "VParseBison.c" break; case 2476: /* property_port_itemDirE: "local" port_direction */ #line 3978 "VParseBison.y" { } #line 36077 "VParseBison.c" break; case 2477: /* property_declarationBody: assertion_variable_declarationList property_statement_spec */ #line 3982 "VParseBison.y" { } #line 36083 "VParseBison.c" break; case 2478: /* property_declarationBody: property_statement_spec */ #line 3985 "VParseBison.y" { } #line 36089 "VParseBison.c" break; case 2479: /* assertion_variable_declarationList: assertion_variable_declaration */ #line 3989 "VParseBison.y" { } #line 36095 "VParseBison.c" break; case 2480: /* assertion_variable_declarationList: assertion_variable_declarationList assertion_variable_declaration */ #line 3990 "VParseBison.y" { } #line 36101 "VParseBison.c" break; case 2481: /* sequence_declaration: sequence_declarationFront sequence_port_listE ';' sequence_declarationBody "endsequence" endLabelE */ #line 3996 "VParseBison.y" { PARSEP->symPopScope(VAstType::SEQUENCE); } #line 36107 "VParseBison.c" break; case 2482: /* sequence_declarationFront: "sequence" idAny */ #line 4001 "VParseBison.y" { PARSEP->symPushNew(VAstType::SEQUENCE,(yyvsp[0].str)); } #line 36113 "VParseBison.c" break; case 2483: /* sequence_port_listE: property_port_listE */ #line 4011 "VParseBison.y" { } #line 36119 "VParseBison.c" break; case 2484: /* property_formal_typeNoDt: sequence_formal_typeNoDt */ #line 4015 "VParseBison.y" { (yyval.str) = (yyvsp[0].str); } #line 36125 "VParseBison.c" break; case 2485: /* property_formal_typeNoDt: "property" */ #line 4016 "VParseBison.y" { (yyval.str) = "property"; } #line 36131 "VParseBison.c" break; case 2486: /* sequence_formal_typeNoDt: "sequence" */ #line 4022 "VParseBison.y" { (yyval.str) = "sequence"; } #line 36137 "VParseBison.c" break; case 2487: /* sequence_formal_typeNoDt: "untyped" */ #line 4025 "VParseBison.y" { (yyval.str) = "untyped"; } #line 36143 "VParseBison.c" break; case 2488: /* sequence_declarationBody: assertion_variable_declarationList sexpr */ #line 4030 "VParseBison.y" { } #line 36149 "VParseBison.c" break; case 2489: /* sequence_declarationBody: assertion_variable_declarationList sexpr ';' */ #line 4031 "VParseBison.y" { } #line 36155 "VParseBison.c" break; case 2490: /* sequence_declarationBody: sexpr */ #line 4032 "VParseBison.y" { } #line 36161 "VParseBison.c" break; case 2491: /* sequence_declarationBody: sexpr ';' */ #line 4033 "VParseBison.y" { } #line 36167 "VParseBison.c" break; case 2492: /* property_spec: "disable" "iff" '(' expr ')' pexpr */ #line 4039 "VParseBison.y" { } #line 36173 "VParseBison.c" break; case 2493: /* property_spec: pexpr */ #line 4040 "VParseBison.y" { } #line 36179 "VParseBison.c" break; case 2494: /* property_statement_spec: property_statement */ #line 4045 "VParseBison.y" { } #line 36185 "VParseBison.c" break; case 2495: /* property_statement_spec: "disable" "iff" '(' expr ')' property_statement */ #line 4046 "VParseBison.y" { } #line 36191 "VParseBison.c" break; case 2496: /* property_statement_spec: clocking_event property_statementCaseIf */ #line 4051 "VParseBison.y" { } #line 36197 "VParseBison.c" break; case 2497: /* property_statement_spec: clocking_event "disable" "iff" '(' expr ')' property_statementCaseIf */ #line 4052 "VParseBison.y" { } #line 36203 "VParseBison.c" break; case 2498: /* property_statement: pexpr ';' */ #line 4057 "VParseBison.y" { } #line 36209 "VParseBison.c" break; case 2499: /* property_statement: property_statementCaseIf */ #line 4060 "VParseBison.y" { } #line 36215 "VParseBison.c" break; case 2500: /* property_statementCaseIf: "case" '(' expr ')' property_case_itemList "endcase" */ #line 4064 "VParseBison.y" { } #line 36221 "VParseBison.c" break; case 2501: /* property_statementCaseIf: "case" '(' expr ')' "endcase" */ #line 4065 "VParseBison.y" { } #line 36227 "VParseBison.c" break; case 2502: /* property_statementCaseIf: "if" '(' expr ')' pexpr */ #line 4066 "VParseBison.y" { } #line 36233 "VParseBison.c" break; case 2503: /* property_statementCaseIf: "if" '(' expr ')' pexpr "else" pexpr */ #line 4067 "VParseBison.y" { } #line 36239 "VParseBison.c" break; case 2504: /* property_case_itemList: property_case_item */ #line 4071 "VParseBison.y" { } #line 36245 "VParseBison.c" break; case 2505: /* property_case_itemList: property_case_itemList ',' property_case_item */ #line 4072 "VParseBison.y" { } #line 36251 "VParseBison.c" break; case 2506: /* property_case_item: caseCondList ':' pexpr */ #line 4079 "VParseBison.y" { } #line 36257 "VParseBison.c" break; case 2507: /* property_case_item: caseCondList ':' pexpr ';' */ #line 4080 "VParseBison.y" { } #line 36263 "VParseBison.c" break; case 2508: /* property_case_item: "default" pexpr */ #line 4081 "VParseBison.y" { } #line 36269 "VParseBison.c" break; case 2509: /* property_case_item: "default" ':' pexpr ';' */ #line 4082 "VParseBison.y" { } #line 36275 "VParseBison.c" break; case 2510: /* pev_expr: senitemEdge */ #line 4099 "VParseBison.y" { (yyval.str)=(yyvsp[0].str); } #line 36281 "VParseBison.c" break; case 2511: /* pev_expr: "not" pexpr */ #line 4102 "VParseBison.y" { } #line 36287 "VParseBison.c" break; case 2512: /* pev_expr: "strong" '(' sexpr ')' */ #line 4102 "VParseBison.y" { } #line 36293 "VParseBison.c" break; case 2513: /* pev_expr: "weak" '(' sexpr ')' */ #line 4102 "VParseBison.y" { } #line 36299 "VParseBison.c" break; case 2514: /* pev_expr: pev_expr "|->" pexpr */ #line 4102 "VParseBison.y" { } #line 36305 "VParseBison.c" break; case 2515: /* pev_expr: pev_expr "|=>" pexpr */ #line 4102 "VParseBison.y" { } #line 36311 "VParseBison.c" break; case 2516: /* pev_expr: property_statementCaseIf */ #line 4102 "VParseBison.y" { } #line 36317 "VParseBison.c" break; case 2517: /* pev_expr: pev_expr "#-#" pexpr */ #line 4102 "VParseBison.y" { } #line 36323 "VParseBison.c" break; case 2518: /* pev_expr: pev_expr "#=#" pexpr */ #line 4102 "VParseBison.y" { } #line 36329 "VParseBison.c" break; case 2519: /* pev_expr: "nexttime" pexpr */ #line 4102 "VParseBison.y" { } #line 36335 "VParseBison.c" break; case 2520: /* pev_expr: "s_nexttime" pexpr */ #line 4102 "VParseBison.y" { } #line 36341 "VParseBison.c" break; case 2521: /* pev_expr: "nexttime" '[' expr ']' pexpr */ #line 4102 "VParseBison.y" { } #line 36347 "VParseBison.c" break; case 2522: /* pev_expr: "s_nexttime" '[' expr ']' pexpr */ #line 4102 "VParseBison.y" { } #line 36353 "VParseBison.c" break; case 2523: /* pev_expr: "always" pexpr */ #line 4102 "VParseBison.y" { } #line 36359 "VParseBison.c" break; case 2524: /* pev_expr: "always" '[' cycle_delay_const_range_expression ']' pexpr */ #line 4102 "VParseBison.y" { } #line 36365 "VParseBison.c" break; case 2525: /* pev_expr: "s_always" '[' constant_range ']' pexpr */ #line 4102 "VParseBison.y" { } #line 36371 "VParseBison.c" break; case 2526: /* pev_expr: "s_eventually" pexpr */ #line 4102 "VParseBison.y" { } #line 36377 "VParseBison.c" break; case 2527: /* pev_expr: "eventually" '[' constant_range ']' pexpr */ #line 4102 "VParseBison.y" { } #line 36383 "VParseBison.c" break; case 2528: /* pev_expr: "s_eventually" '[' cycle_delay_const_range_expression ']' pexpr */ #line 4102 "VParseBison.y" { } #line 36389 "VParseBison.c" break; case 2529: /* pev_expr: pev_expr "until" pexpr */ #line 4102 "VParseBison.y" { } #line 36395 "VParseBison.c" break; case 2530: /* pev_expr: pev_expr "s_until" pexpr */ #line 4102 "VParseBison.y" { } #line 36401 "VParseBison.c" break; case 2531: /* pev_expr: pev_expr "until_with" pexpr */ #line 4102 "VParseBison.y" { } #line 36407 "VParseBison.c" break; case 2532: /* pev_expr: pev_expr "s_until_with" pexpr */ #line 4102 "VParseBison.y" { } #line 36413 "VParseBison.c" break; case 2533: /* pev_expr: pev_expr "implies" pexpr */ #line 4102 "VParseBison.y" { } #line 36419 "VParseBison.c" break; case 2534: /* pev_expr: pev_expr "iff" pev_expr */ #line 4102 "VParseBison.y" { } #line 36425 "VParseBison.c" break; case 2535: /* pev_expr: "accept_on" '(' expr ')' pexpr */ #line 4102 "VParseBison.y" { } #line 36431 "VParseBison.c" break; case 2536: /* pev_expr: "reject_on" '(' expr ')' pexpr */ #line 4102 "VParseBison.y" { } #line 36437 "VParseBison.c" break; case 2537: /* pev_expr: "sync_accept_on" '(' expr ')' pexpr */ #line 4102 "VParseBison.y" { } #line 36443 "VParseBison.c" break; case 2538: /* pev_expr: "sync_reject_on" '(' expr ')' pexpr */ #line 4102 "VParseBison.y" { } #line 36449 "VParseBison.c" break; case 2539: /* pev_expr: clocking_event "disable" "iff" '(' expr ')' pexpr */ #line 4102 "VParseBison.y" { } #line 36455 "VParseBison.c" break; case 2540: /* pev_expr: cycle_delay_range sexpr */ #line 4105 "VParseBison.y" { } #line 36461 "VParseBison.c" break; case 2541: /* pev_expr: pev_expr cycle_delay_range sexpr */ #line 4105 "VParseBison.y" { } #line 36467 "VParseBison.c" break; case 2542: /* pev_expr: pev_expr boolean_abbrev */ #line 4105 "VParseBison.y" { } #line 36473 "VParseBison.c" break; case 2543: /* pev_expr: '(' pev_expr ')' */ #line 4105 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str)=(yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 36479 "VParseBison.c" break; case 2544: /* pev_expr: '(' pev_expr ',' sequence_match_itemList ')' */ #line 4105 "VParseBison.y" { } #line 36485 "VParseBison.c" break; case 2545: /* pev_expr: pev_expr "and" pev_expr */ #line 4105 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str)=(yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 36491 "VParseBison.c" break; case 2546: /* pev_expr: pev_expr "or" pev_expr */ #line 4105 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str)=(yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 36497 "VParseBison.c" break; case 2547: /* pev_expr: pev_expr "intersect" sexpr */ #line 4105 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str)=(yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 36503 "VParseBison.c" break; case 2548: /* pev_expr: "first_match" '(' sexpr ')' */ #line 4105 "VParseBison.y" { } #line 36509 "VParseBison.c" break; case 2549: /* pev_expr: "first_match" '(' sexpr ',' sequence_match_itemList ')' */ #line 4105 "VParseBison.y" { } #line 36515 "VParseBison.c" break; case 2550: /* pev_expr: pev_expr "throughout" sexpr */ #line 4105 "VParseBison.y" { } #line 36521 "VParseBison.c" break; case 2551: /* pev_expr: pev_expr "within" sexpr */ #line 4105 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str)=(yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 36527 "VParseBison.c" break; case 2552: /* pev_expr: clocking_event pev_expr */ #line 4105 "VParseBison.y" { } #line 36533 "VParseBison.c" break; case 2553: /* pev_expr: '+' expr */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 36539 "VParseBison.c" break; case 2554: /* pev_expr: '-' expr */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 36545 "VParseBison.c" break; case 2555: /* pev_expr: '!' expr */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 36551 "VParseBison.c" break; case 2556: /* pev_expr: '&' expr */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 36557 "VParseBison.c" break; case 2557: /* pev_expr: '~' expr */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 36563 "VParseBison.c" break; case 2558: /* pev_expr: '|' expr */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 36569 "VParseBison.c" break; case 2559: /* pev_expr: '^' expr */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 36575 "VParseBison.c" break; case 2560: /* pev_expr: "~&" expr */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 36581 "VParseBison.c" break; case 2561: /* pev_expr: "~|" expr */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 36587 "VParseBison.c" break; case 2562: /* pev_expr: "^~" expr */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 36593 "VParseBison.c" break; case 2563: /* pev_expr: pev_inc_or_dec_expression */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 36599 "VParseBison.c" break; case 2564: /* pev_expr: '(' pev_exprScope '=' expr ')' */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 36605 "VParseBison.c" break; case 2565: /* pev_expr: '(' pev_exprScope "+=" expr ')' */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 36611 "VParseBison.c" break; case 2566: /* pev_expr: '(' pev_exprScope "-=" expr ')' */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 36617 "VParseBison.c" break; case 2567: /* pev_expr: '(' pev_exprScope "*=" expr ')' */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 36623 "VParseBison.c" break; case 2568: /* pev_expr: '(' pev_exprScope "/=" expr ')' */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 36629 "VParseBison.c" break; case 2569: /* pev_expr: '(' pev_exprScope "%=" expr ')' */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 36635 "VParseBison.c" break; case 2570: /* pev_expr: '(' pev_exprScope "&=" expr ')' */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 36641 "VParseBison.c" break; case 2571: /* pev_expr: '(' pev_exprScope "|=" expr ')' */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 36647 "VParseBison.c" break; case 2572: /* pev_expr: '(' pev_exprScope "^=" expr ')' */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 36653 "VParseBison.c" break; case 2573: /* pev_expr: '(' pev_exprScope "<<=" expr ')' */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 36659 "VParseBison.c" break; case 2574: /* pev_expr: '(' pev_exprScope ">>=" expr ')' */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 36665 "VParseBison.c" break; case 2575: /* pev_expr: '(' pev_exprScope ">>>=" expr ')' */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 36671 "VParseBison.c" break; case 2576: /* pev_expr: pev_expr '+' expr */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 36677 "VParseBison.c" break; case 2577: /* pev_expr: pev_expr '-' expr */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 36683 "VParseBison.c" break; case 2578: /* pev_expr: pev_expr '*' expr */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 36689 "VParseBison.c" break; case 2579: /* pev_expr: pev_expr '/' expr */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 36695 "VParseBison.c" break; case 2580: /* pev_expr: pev_expr '%' expr */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 36701 "VParseBison.c" break; case 2581: /* pev_expr: pev_expr "==" expr */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 36707 "VParseBison.c" break; case 2582: /* pev_expr: pev_expr "!=" expr */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 36713 "VParseBison.c" break; case 2583: /* pev_expr: pev_expr "===" expr */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 36719 "VParseBison.c" break; case 2584: /* pev_expr: pev_expr "!==" expr */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 36725 "VParseBison.c" break; case 2585: /* pev_expr: pev_expr "==?" expr */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 36731 "VParseBison.c" break; case 2586: /* pev_expr: pev_expr "!=?" expr */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 36737 "VParseBison.c" break; case 2587: /* pev_expr: pev_expr "&&" expr */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 36743 "VParseBison.c" break; case 2588: /* pev_expr: pev_expr "||" expr */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 36749 "VParseBison.c" break; case 2589: /* pev_expr: pev_expr "**" expr */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 36755 "VParseBison.c" break; case 2590: /* pev_expr: pev_expr '<' expr */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 36761 "VParseBison.c" break; case 2591: /* pev_expr: pev_expr '>' expr */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 36767 "VParseBison.c" break; case 2592: /* pev_expr: pev_expr ">=" expr */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 36773 "VParseBison.c" break; case 2593: /* pev_expr: pev_expr '&' expr */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 36779 "VParseBison.c" break; case 2594: /* pev_expr: pev_expr '|' expr */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 36785 "VParseBison.c" break; case 2595: /* pev_expr: pev_expr '^' expr */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 36791 "VParseBison.c" break; case 2596: /* pev_expr: pev_expr "^~" expr */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 36797 "VParseBison.c" break; case 2597: /* pev_expr: pev_expr "~|" expr */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 36803 "VParseBison.c" break; case 2598: /* pev_expr: pev_expr "~&" expr */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 36809 "VParseBison.c" break; case 2599: /* pev_expr: pev_expr "<<" expr */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 36815 "VParseBison.c" break; case 2600: /* pev_expr: pev_expr ">>" expr */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 36821 "VParseBison.c" break; case 2601: /* pev_expr: pev_expr ">>>" expr */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 36827 "VParseBison.c" break; case 2602: /* pev_expr: pev_expr "<->" expr */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 36833 "VParseBison.c" break; case 2603: /* pev_expr: pev_expr "->" constraint_set */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 36839 "VParseBison.c" break; case 2604: /* pev_expr: pev_expr "<=" expr */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 36845 "VParseBison.c" break; case 2605: /* pev_expr: pev_expr '?' expr ':' expr */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = (yyvsp[-4].str)+"?"+(yyvsp[-2].str)+":"+(yyvsp[0].str); } #line 36851 "VParseBison.c" break; case 2606: /* pev_expr: pev_expr "inside" '{' open_range_list '}' */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = (yyvsp[-4].str)+" inside {"+(yyvsp[-2].str)+"}"; } #line 36857 "VParseBison.c" break; case 2607: /* pev_expr: "tagged" id */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = " tagged "+(yyvsp[-1].str); } #line 36863 "VParseBison.c" break; case 2608: /* pev_expr: "tagged" id expr */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = " tagged "+(yyvsp[-2].str)+" "+(yyvsp[-1].str); } #line 36869 "VParseBison.c" break; case 2609: /* pev_expr: "INTEGER NUMBER" */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 36875 "VParseBison.c" break; case 2610: /* pev_expr: "FLOATING-POINT NUMBER" */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 36881 "VParseBison.c" break; case 2611: /* pev_expr: "TIME NUMBER" */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 36887 "VParseBison.c" break; case 2612: /* pev_expr: strAsInt */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 36893 "VParseBison.c" break; case 2614: /* pev_expr: '{' constExpr '{' cateList '}' '}' */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-5].fl); (yyval.str) = "{"+(yyvsp[-4].str)+"{"+(yyvsp[-2].str)+"}}"; } #line 36899 "VParseBison.c" break; case 2615: /* pev_expr: '{' constExpr '{' cateList '}' '}' '[' expr ']' */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-8].fl); (yyval.str) = "{"+(yyvsp[-7].str)+"{"+(yyvsp[-5].str)+"}}["+(yyvsp[-1].str)+"]"; NEED_S09((yyvsp[-3].fl),"{}[]"); } #line 36905 "VParseBison.c" break; case 2616: /* pev_expr: '{' constExpr '{' cateList '}' '}' '[' expr ':' expr ']' */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-10].fl); (yyval.str) = "{"+(yyvsp[-9].str)+"{"+(yyvsp[-7].str)+"}}["+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+"]"; NEED_S09((yyvsp[-5].fl),"{}[]"); } #line 36911 "VParseBison.c" break; case 2617: /* pev_expr: '{' constExpr '{' cateList '}' '}' '[' expr "+:" expr ']' */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-10].fl); (yyval.str) = "{"+(yyvsp[-9].str)+"{"+(yyvsp[-7].str)+"}}["+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+"]"; NEED_S09((yyvsp[-5].fl),"{}[]"); } #line 36917 "VParseBison.c" break; case 2618: /* pev_expr: '{' constExpr '{' cateList '}' '}' '[' expr "-:" expr ']' */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-10].fl); (yyval.str) = "{"+(yyvsp[-9].str)+"{"+(yyvsp[-7].str)+"}}["+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+"]"; NEED_S09((yyvsp[-5].fl),"{}[]"); } #line 36923 "VParseBison.c" break; case 2619: /* pev_expr: function_subroutine_callNoMethod */ #line 4108 "VParseBison.y" { (yyval.str) = (yyvsp[0].str); } #line 36929 "VParseBison.c" break; case 2620: /* pev_expr: pev_expr '.' function_subroutine_callNoMethod */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str)=(yyvsp[-2].str)+"."+(yyvsp[0].str); } #line 36935 "VParseBison.c" break; case 2621: /* pev_expr: pev_expr '.' array_methodNoRoot */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+"."+(yyvsp[0].str); } #line 36941 "VParseBison.c" break; case 2622: /* pev_expr: "(-ignored" '(' expr ')' */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-3].fl); (yyval.str) = "("+(yyvsp[-2].str)+")"; } #line 36947 "VParseBison.c" break; case 2623: /* pev_expr: "(-ignored" '(' expr ':' expr ':' expr ')' */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-7].fl); (yyval.str) = "("+(yyvsp[-6].str)+":"+(yyvsp[-4].str)+":"+(yyvsp[-3].str)+")"; } #line 36953 "VParseBison.c" break; case 2624: /* pev_expr: '_' '(' statePushVlg expr statePop ')' */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-5].fl); (yyval.str) = "_("+(yyvsp[-2].str)+")"; } #line 36959 "VParseBison.c" break; case 2625: /* pev_expr: casting_type "'" '(' expr ')' */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = (yyvsp[-4].str)+"'("+(yyvsp[-1].str)+")"; } #line 36965 "VParseBison.c" break; case 2626: /* pev_expr: pev_expr "'" '(' expr ')' */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = (yyvsp[-4].str)+"'("+(yyvsp[-1].str)+")"; } #line 36971 "VParseBison.c" break; case 2627: /* pev_expr: '$' */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = "$"; } #line 36977 "VParseBison.c" break; case 2628: /* pev_expr: "null" */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 36983 "VParseBison.c" break; case 2629: /* pev_expr: pev_exprOkLvalue */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 36989 "VParseBison.c" break; case 2630: /* pev_expr: pev_expr "&&&" expr */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str) + "&&&" + (yyvsp[0].str); } #line 36995 "VParseBison.c" break; case 2631: /* pev_expr: pev_expr "matches" patternNoExpr */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str) + " matches " + (yyvsp[0].str); } #line 37001 "VParseBison.c" break; case 2632: /* pev_expr: pev_expr "matches" expr */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str) + " matches " + (yyvsp[0].str); } #line 37007 "VParseBison.c" break; case 2633: /* pev_expr: pev_expr "dist" '{' dist_list '}' */ #line 4108 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = (yyvsp[-4].str) + " dist " + (yyvsp[-2].str)+"..."+(yyvsp[0].str); } #line 37013 "VParseBison.c" break; case 2634: /* pexpr: "not" pexpr */ #line 4119 "VParseBison.y" { } #line 37019 "VParseBison.c" break; case 2635: /* pexpr: "strong" '(' sexpr ')' */ #line 4120 "VParseBison.y" { } #line 37025 "VParseBison.c" break; case 2636: /* pexpr: "weak" '(' sexpr ')' */ #line 4121 "VParseBison.y" { } #line 37031 "VParseBison.c" break; case 2637: /* pexpr: pexpr "|->" pexpr */ #line 4128 "VParseBison.y" { } #line 37037 "VParseBison.c" break; case 2638: /* pexpr: pexpr "|=>" pexpr */ #line 4129 "VParseBison.y" { } #line 37043 "VParseBison.c" break; case 2639: /* pexpr: property_statementCaseIf */ #line 4133 "VParseBison.y" { } #line 37049 "VParseBison.c" break; case 2640: /* pexpr: pexpr "#-#" pexpr */ #line 4135 "VParseBison.y" { } #line 37055 "VParseBison.c" break; case 2641: /* pexpr: pexpr "#=#" pexpr */ #line 4136 "VParseBison.y" { } #line 37061 "VParseBison.c" break; case 2642: /* pexpr: "nexttime" pexpr */ #line 4137 "VParseBison.y" { } #line 37067 "VParseBison.c" break; case 2643: /* pexpr: "s_nexttime" pexpr */ #line 4138 "VParseBison.y" { } #line 37073 "VParseBison.c" break; case 2644: /* pexpr: "nexttime" '[' expr ']' pexpr */ #line 4139 "VParseBison.y" { } #line 37079 "VParseBison.c" break; case 2645: /* pexpr: "s_nexttime" '[' expr ']' pexpr */ #line 4140 "VParseBison.y" { } #line 37085 "VParseBison.c" break; case 2646: /* pexpr: "always" pexpr */ #line 4141 "VParseBison.y" { } #line 37091 "VParseBison.c" break; case 2647: /* pexpr: "always" '[' cycle_delay_const_range_expression ']' pexpr */ #line 4142 "VParseBison.y" { } #line 37097 "VParseBison.c" break; case 2648: /* pexpr: "s_always" '[' constant_range ']' pexpr */ #line 4143 "VParseBison.y" { } #line 37103 "VParseBison.c" break; case 2649: /* pexpr: "s_eventually" pexpr */ #line 4144 "VParseBison.y" { } #line 37109 "VParseBison.c" break; case 2650: /* pexpr: "eventually" '[' constant_range ']' pexpr */ #line 4145 "VParseBison.y" { } #line 37115 "VParseBison.c" break; case 2651: /* pexpr: "s_eventually" '[' cycle_delay_const_range_expression ']' pexpr */ #line 4146 "VParseBison.y" { } #line 37121 "VParseBison.c" break; case 2652: /* pexpr: pexpr "until" pexpr */ #line 4147 "VParseBison.y" { } #line 37127 "VParseBison.c" break; case 2653: /* pexpr: pexpr "s_until" pexpr */ #line 4148 "VParseBison.y" { } #line 37133 "VParseBison.c" break; case 2654: /* pexpr: pexpr "until_with" pexpr */ #line 4149 "VParseBison.y" { } #line 37139 "VParseBison.c" break; case 2655: /* pexpr: pexpr "s_until_with" pexpr */ #line 4150 "VParseBison.y" { } #line 37145 "VParseBison.c" break; case 2656: /* pexpr: pexpr "implies" pexpr */ #line 4151 "VParseBison.y" { } #line 37151 "VParseBison.c" break; case 2657: /* pexpr: pexpr "iff" pexpr */ #line 4153 "VParseBison.y" { } #line 37157 "VParseBison.c" break; case 2658: /* pexpr: "accept_on" '(' expr ')' pexpr */ #line 4154 "VParseBison.y" { } #line 37163 "VParseBison.c" break; case 2659: /* pexpr: "reject_on" '(' expr ')' pexpr */ #line 4155 "VParseBison.y" { } #line 37169 "VParseBison.c" break; case 2660: /* pexpr: "sync_accept_on" '(' expr ')' pexpr */ #line 4156 "VParseBison.y" { } #line 37175 "VParseBison.c" break; case 2661: /* pexpr: "sync_reject_on" '(' expr ')' pexpr */ #line 4157 "VParseBison.y" { } #line 37181 "VParseBison.c" break; case 2662: /* pexpr: clocking_event "disable" "iff" '(' expr ')' pexpr */ #line 4165 "VParseBison.y" { } #line 37187 "VParseBison.c" break; case 2663: /* pexpr: cycle_delay_range sexpr */ #line 4168 "VParseBison.y" { } #line 37193 "VParseBison.c" break; case 2664: /* pexpr: pexpr cycle_delay_range sexpr */ #line 4168 "VParseBison.y" { } #line 37199 "VParseBison.c" break; case 2665: /* pexpr: pexpr boolean_abbrev */ #line 4168 "VParseBison.y" { } #line 37205 "VParseBison.c" break; case 2666: /* pexpr: '(' pexpr ')' */ #line 4168 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str)=(yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 37211 "VParseBison.c" break; case 2667: /* pexpr: '(' pexpr ',' sequence_match_itemList ')' */ #line 4168 "VParseBison.y" { } #line 37217 "VParseBison.c" break; case 2668: /* pexpr: pexpr "and" pexpr */ #line 4168 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str)=(yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 37223 "VParseBison.c" break; case 2669: /* pexpr: pexpr "or" pexpr */ #line 4168 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str)=(yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 37229 "VParseBison.c" break; case 2670: /* pexpr: pexpr "intersect" sexpr */ #line 4168 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str)=(yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 37235 "VParseBison.c" break; case 2671: /* pexpr: "first_match" '(' sexpr ')' */ #line 4168 "VParseBison.y" { } #line 37241 "VParseBison.c" break; case 2672: /* pexpr: "first_match" '(' sexpr ',' sequence_match_itemList ')' */ #line 4168 "VParseBison.y" { } #line 37247 "VParseBison.c" break; case 2673: /* pexpr: pexpr "throughout" sexpr */ #line 4168 "VParseBison.y" { } #line 37253 "VParseBison.c" break; case 2674: /* pexpr: pexpr "within" sexpr */ #line 4168 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str)=(yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 37259 "VParseBison.c" break; case 2675: /* pexpr: clocking_event pexpr */ #line 4168 "VParseBison.y" { } #line 37265 "VParseBison.c" break; case 2676: /* pexpr: '+' expr */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 37271 "VParseBison.c" break; case 2677: /* pexpr: '-' expr */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 37277 "VParseBison.c" break; case 2678: /* pexpr: '!' expr */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 37283 "VParseBison.c" break; case 2679: /* pexpr: '&' expr */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 37289 "VParseBison.c" break; case 2680: /* pexpr: '~' expr */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 37295 "VParseBison.c" break; case 2681: /* pexpr: '|' expr */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 37301 "VParseBison.c" break; case 2682: /* pexpr: '^' expr */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 37307 "VParseBison.c" break; case 2683: /* pexpr: "~&" expr */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 37313 "VParseBison.c" break; case 2684: /* pexpr: "~|" expr */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 37319 "VParseBison.c" break; case 2685: /* pexpr: "^~" expr */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 37325 "VParseBison.c" break; case 2686: /* pexpr: pinc_or_dec_expression */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 37331 "VParseBison.c" break; case 2687: /* pexpr: '(' pexprScope '=' expr ')' */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 37337 "VParseBison.c" break; case 2688: /* pexpr: '(' pexprScope "+=" expr ')' */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 37343 "VParseBison.c" break; case 2689: /* pexpr: '(' pexprScope "-=" expr ')' */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 37349 "VParseBison.c" break; case 2690: /* pexpr: '(' pexprScope "*=" expr ')' */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 37355 "VParseBison.c" break; case 2691: /* pexpr: '(' pexprScope "/=" expr ')' */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 37361 "VParseBison.c" break; case 2692: /* pexpr: '(' pexprScope "%=" expr ')' */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 37367 "VParseBison.c" break; case 2693: /* pexpr: '(' pexprScope "&=" expr ')' */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 37373 "VParseBison.c" break; case 2694: /* pexpr: '(' pexprScope "|=" expr ')' */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 37379 "VParseBison.c" break; case 2695: /* pexpr: '(' pexprScope "^=" expr ')' */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 37385 "VParseBison.c" break; case 2696: /* pexpr: '(' pexprScope "<<=" expr ')' */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 37391 "VParseBison.c" break; case 2697: /* pexpr: '(' pexprScope ">>=" expr ')' */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 37397 "VParseBison.c" break; case 2698: /* pexpr: '(' pexprScope ">>>=" expr ')' */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 37403 "VParseBison.c" break; case 2699: /* pexpr: pexpr '+' expr */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 37409 "VParseBison.c" break; case 2700: /* pexpr: pexpr '-' expr */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 37415 "VParseBison.c" break; case 2701: /* pexpr: pexpr '*' expr */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 37421 "VParseBison.c" break; case 2702: /* pexpr: pexpr '/' expr */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 37427 "VParseBison.c" break; case 2703: /* pexpr: pexpr '%' expr */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 37433 "VParseBison.c" break; case 2704: /* pexpr: pexpr "==" expr */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 37439 "VParseBison.c" break; case 2705: /* pexpr: pexpr "!=" expr */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 37445 "VParseBison.c" break; case 2706: /* pexpr: pexpr "===" expr */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 37451 "VParseBison.c" break; case 2707: /* pexpr: pexpr "!==" expr */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 37457 "VParseBison.c" break; case 2708: /* pexpr: pexpr "==?" expr */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 37463 "VParseBison.c" break; case 2709: /* pexpr: pexpr "!=?" expr */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 37469 "VParseBison.c" break; case 2710: /* pexpr: pexpr "&&" expr */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 37475 "VParseBison.c" break; case 2711: /* pexpr: pexpr "||" expr */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 37481 "VParseBison.c" break; case 2712: /* pexpr: pexpr "**" expr */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 37487 "VParseBison.c" break; case 2713: /* pexpr: pexpr '<' expr */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 37493 "VParseBison.c" break; case 2714: /* pexpr: pexpr '>' expr */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 37499 "VParseBison.c" break; case 2715: /* pexpr: pexpr ">=" expr */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 37505 "VParseBison.c" break; case 2716: /* pexpr: pexpr '&' expr */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 37511 "VParseBison.c" break; case 2717: /* pexpr: pexpr '|' expr */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 37517 "VParseBison.c" break; case 2718: /* pexpr: pexpr '^' expr */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 37523 "VParseBison.c" break; case 2719: /* pexpr: pexpr "^~" expr */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 37529 "VParseBison.c" break; case 2720: /* pexpr: pexpr "~|" expr */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 37535 "VParseBison.c" break; case 2721: /* pexpr: pexpr "~&" expr */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 37541 "VParseBison.c" break; case 2722: /* pexpr: pexpr "<<" expr */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 37547 "VParseBison.c" break; case 2723: /* pexpr: pexpr ">>" expr */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 37553 "VParseBison.c" break; case 2724: /* pexpr: pexpr ">>>" expr */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 37559 "VParseBison.c" break; case 2725: /* pexpr: pexpr "<->" expr */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 37565 "VParseBison.c" break; case 2726: /* pexpr: pexpr "->" constraint_set */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 37571 "VParseBison.c" break; case 2727: /* pexpr: pexpr "<=" expr */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 37577 "VParseBison.c" break; case 2728: /* pexpr: pexpr '?' expr ':' expr */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = (yyvsp[-4].str)+"?"+(yyvsp[-2].str)+":"+(yyvsp[0].str); } #line 37583 "VParseBison.c" break; case 2729: /* pexpr: pexpr "inside" '{' open_range_list '}' */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = (yyvsp[-4].str)+" inside {"+(yyvsp[-2].str)+"}"; } #line 37589 "VParseBison.c" break; case 2730: /* pexpr: "tagged" id */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = " tagged "+(yyvsp[-1].str); } #line 37595 "VParseBison.c" break; case 2731: /* pexpr: "tagged" id expr */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = " tagged "+(yyvsp[-2].str)+" "+(yyvsp[-1].str); } #line 37601 "VParseBison.c" break; case 2732: /* pexpr: "INTEGER NUMBER" */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 37607 "VParseBison.c" break; case 2733: /* pexpr: "FLOATING-POINT NUMBER" */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 37613 "VParseBison.c" break; case 2734: /* pexpr: "TIME NUMBER" */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 37619 "VParseBison.c" break; case 2735: /* pexpr: strAsInt */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 37625 "VParseBison.c" break; case 2737: /* pexpr: '{' constExpr '{' cateList '}' '}' */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-5].fl); (yyval.str) = "{"+(yyvsp[-4].str)+"{"+(yyvsp[-2].str)+"}}"; } #line 37631 "VParseBison.c" break; case 2738: /* pexpr: '{' constExpr '{' cateList '}' '}' '[' expr ']' */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-8].fl); (yyval.str) = "{"+(yyvsp[-7].str)+"{"+(yyvsp[-5].str)+"}}["+(yyvsp[-1].str)+"]"; NEED_S09((yyvsp[-3].fl),"{}[]"); } #line 37637 "VParseBison.c" break; case 2739: /* pexpr: '{' constExpr '{' cateList '}' '}' '[' expr ':' expr ']' */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-10].fl); (yyval.str) = "{"+(yyvsp[-9].str)+"{"+(yyvsp[-7].str)+"}}["+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+"]"; NEED_S09((yyvsp[-5].fl),"{}[]"); } #line 37643 "VParseBison.c" break; case 2740: /* pexpr: '{' constExpr '{' cateList '}' '}' '[' expr "+:" expr ']' */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-10].fl); (yyval.str) = "{"+(yyvsp[-9].str)+"{"+(yyvsp[-7].str)+"}}["+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+"]"; NEED_S09((yyvsp[-5].fl),"{}[]"); } #line 37649 "VParseBison.c" break; case 2741: /* pexpr: '{' constExpr '{' cateList '}' '}' '[' expr "-:" expr ']' */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-10].fl); (yyval.str) = "{"+(yyvsp[-9].str)+"{"+(yyvsp[-7].str)+"}}["+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+"]"; NEED_S09((yyvsp[-5].fl),"{}[]"); } #line 37655 "VParseBison.c" break; case 2742: /* pexpr: function_subroutine_callNoMethod */ #line 4171 "VParseBison.y" { (yyval.str) = (yyvsp[0].str); } #line 37661 "VParseBison.c" break; case 2743: /* pexpr: pexpr '.' function_subroutine_callNoMethod */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str)=(yyvsp[-2].str)+"."+(yyvsp[0].str); } #line 37667 "VParseBison.c" break; case 2744: /* pexpr: pexpr '.' array_methodNoRoot */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+"."+(yyvsp[0].str); } #line 37673 "VParseBison.c" break; case 2745: /* pexpr: "(-ignored" '(' expr ')' */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-3].fl); (yyval.str) = "("+(yyvsp[-2].str)+")"; } #line 37679 "VParseBison.c" break; case 2746: /* pexpr: "(-ignored" '(' expr ':' expr ':' expr ')' */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-7].fl); (yyval.str) = "("+(yyvsp[-6].str)+":"+(yyvsp[-4].str)+":"+(yyvsp[-3].str)+")"; } #line 37685 "VParseBison.c" break; case 2747: /* pexpr: '_' '(' statePushVlg expr statePop ')' */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-5].fl); (yyval.str) = "_("+(yyvsp[-2].str)+")"; } #line 37691 "VParseBison.c" break; case 2748: /* pexpr: casting_type "'" '(' expr ')' */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = (yyvsp[-4].str)+"'("+(yyvsp[-1].str)+")"; } #line 37697 "VParseBison.c" break; case 2749: /* pexpr: pexpr "'" '(' expr ')' */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = (yyvsp[-4].str)+"'("+(yyvsp[-1].str)+")"; } #line 37703 "VParseBison.c" break; case 2750: /* pexpr: '$' */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = "$"; } #line 37709 "VParseBison.c" break; case 2751: /* pexpr: "null" */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 37715 "VParseBison.c" break; case 2752: /* pexpr: pexprOkLvalue */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 37721 "VParseBison.c" break; case 2753: /* pexpr: pexpr "&&&" expr */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str) + "&&&" + (yyvsp[0].str); } #line 37727 "VParseBison.c" break; case 2754: /* pexpr: pexpr "matches" patternNoExpr */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str) + " matches " + (yyvsp[0].str); } #line 37733 "VParseBison.c" break; case 2755: /* pexpr: pexpr "matches" expr */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str) + " matches " + (yyvsp[0].str); } #line 37739 "VParseBison.c" break; case 2756: /* pexpr: pexpr "dist" '{' dist_list '}' */ #line 4171 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = (yyvsp[-4].str) + " dist " + (yyvsp[-2].str)+"..."+(yyvsp[0].str); } #line 37745 "VParseBison.c" break; case 2757: /* sexpr: cycle_delay_range sexpr */ #line 4182 "VParseBison.y" { } #line 37751 "VParseBison.c" break; case 2758: /* sexpr: sexpr cycle_delay_range sexpr */ #line 4183 "VParseBison.y" { } #line 37757 "VParseBison.c" break; case 2759: /* sexpr: sexpr boolean_abbrev */ #line 4188 "VParseBison.y" { } #line 37763 "VParseBison.c" break; case 2760: /* sexpr: '(' sexpr ')' */ #line 4199 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str)=(yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 37769 "VParseBison.c" break; case 2761: /* sexpr: '(' sexpr ',' sequence_match_itemList ')' */ #line 4200 "VParseBison.y" { } #line 37775 "VParseBison.c" break; case 2762: /* sexpr: sexpr "and" sexpr */ #line 4203 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str)=(yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 37781 "VParseBison.c" break; case 2763: /* sexpr: sexpr "or" sexpr */ #line 4204 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str)=(yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 37787 "VParseBison.c" break; case 2764: /* sexpr: sexpr "intersect" sexpr */ #line 4206 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str)=(yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 37793 "VParseBison.c" break; case 2765: /* sexpr: "first_match" '(' sexpr ')' */ #line 4208 "VParseBison.y" { } #line 37799 "VParseBison.c" break; case 2766: /* sexpr: "first_match" '(' sexpr ',' sequence_match_itemList ')' */ #line 4209 "VParseBison.y" { } #line 37805 "VParseBison.c" break; case 2767: /* sexpr: sexpr "throughout" sexpr */ #line 4210 "VParseBison.y" { } #line 37811 "VParseBison.c" break; case 2768: /* sexpr: sexpr "within" sexpr */ #line 4213 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str)=(yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 37817 "VParseBison.c" break; case 2769: /* sexpr: clocking_event sexpr */ #line 4215 "VParseBison.y" { } #line 37823 "VParseBison.c" break; case 2770: /* sexpr: '+' expr */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 37829 "VParseBison.c" break; case 2771: /* sexpr: '-' expr */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 37835 "VParseBison.c" break; case 2772: /* sexpr: '!' expr */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 37841 "VParseBison.c" break; case 2773: /* sexpr: '&' expr */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 37847 "VParseBison.c" break; case 2774: /* sexpr: '~' expr */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 37853 "VParseBison.c" break; case 2775: /* sexpr: '|' expr */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 37859 "VParseBison.c" break; case 2776: /* sexpr: '^' expr */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 37865 "VParseBison.c" break; case 2777: /* sexpr: "~&" expr */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 37871 "VParseBison.c" break; case 2778: /* sexpr: "~|" expr */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 37877 "VParseBison.c" break; case 2779: /* sexpr: "^~" expr */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = (yyvsp[-1].str)+(yyvsp[0].str); } #line 37883 "VParseBison.c" break; case 2780: /* sexpr: sinc_or_dec_expression */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 37889 "VParseBison.c" break; case 2781: /* sexpr: '(' sexprScope '=' expr ')' */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 37895 "VParseBison.c" break; case 2782: /* sexpr: '(' sexprScope "+=" expr ')' */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 37901 "VParseBison.c" break; case 2783: /* sexpr: '(' sexprScope "-=" expr ')' */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 37907 "VParseBison.c" break; case 2784: /* sexpr: '(' sexprScope "*=" expr ')' */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 37913 "VParseBison.c" break; case 2785: /* sexpr: '(' sexprScope "/=" expr ')' */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 37919 "VParseBison.c" break; case 2786: /* sexpr: '(' sexprScope "%=" expr ')' */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 37925 "VParseBison.c" break; case 2787: /* sexpr: '(' sexprScope "&=" expr ')' */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 37931 "VParseBison.c" break; case 2788: /* sexpr: '(' sexprScope "|=" expr ')' */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 37937 "VParseBison.c" break; case 2789: /* sexpr: '(' sexprScope "^=" expr ')' */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 37943 "VParseBison.c" break; case 2790: /* sexpr: '(' sexprScope "<<=" expr ')' */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 37949 "VParseBison.c" break; case 2791: /* sexpr: '(' sexprScope ">>=" expr ')' */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 37955 "VParseBison.c" break; case 2792: /* sexpr: '(' sexprScope ">>>=" expr ')' */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = "("+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+")"; } #line 37961 "VParseBison.c" break; case 2793: /* sexpr: sexpr '+' expr */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 37967 "VParseBison.c" break; case 2794: /* sexpr: sexpr '-' expr */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 37973 "VParseBison.c" break; case 2795: /* sexpr: sexpr '*' expr */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 37979 "VParseBison.c" break; case 2796: /* sexpr: sexpr '/' expr */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 37985 "VParseBison.c" break; case 2797: /* sexpr: sexpr '%' expr */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 37991 "VParseBison.c" break; case 2798: /* sexpr: sexpr "==" expr */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 37997 "VParseBison.c" break; case 2799: /* sexpr: sexpr "!=" expr */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 38003 "VParseBison.c" break; case 2800: /* sexpr: sexpr "===" expr */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 38009 "VParseBison.c" break; case 2801: /* sexpr: sexpr "!==" expr */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 38015 "VParseBison.c" break; case 2802: /* sexpr: sexpr "==?" expr */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 38021 "VParseBison.c" break; case 2803: /* sexpr: sexpr "!=?" expr */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 38027 "VParseBison.c" break; case 2804: /* sexpr: sexpr "&&" expr */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 38033 "VParseBison.c" break; case 2805: /* sexpr: sexpr "||" expr */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 38039 "VParseBison.c" break; case 2806: /* sexpr: sexpr "**" expr */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 38045 "VParseBison.c" break; case 2807: /* sexpr: sexpr '<' expr */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 38051 "VParseBison.c" break; case 2808: /* sexpr: sexpr '>' expr */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 38057 "VParseBison.c" break; case 2809: /* sexpr: sexpr ">=" expr */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 38063 "VParseBison.c" break; case 2810: /* sexpr: sexpr '&' expr */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 38069 "VParseBison.c" break; case 2811: /* sexpr: sexpr '|' expr */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 38075 "VParseBison.c" break; case 2812: /* sexpr: sexpr '^' expr */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 38081 "VParseBison.c" break; case 2813: /* sexpr: sexpr "^~" expr */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 38087 "VParseBison.c" break; case 2814: /* sexpr: sexpr "~|" expr */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 38093 "VParseBison.c" break; case 2815: /* sexpr: sexpr "~&" expr */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 38099 "VParseBison.c" break; case 2816: /* sexpr: sexpr "<<" expr */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 38105 "VParseBison.c" break; case 2817: /* sexpr: sexpr ">>" expr */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 38111 "VParseBison.c" break; case 2818: /* sexpr: sexpr ">>>" expr */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 38117 "VParseBison.c" break; case 2819: /* sexpr: sexpr "<->" expr */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 38123 "VParseBison.c" break; case 2820: /* sexpr: sexpr "->" constraint_set */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 38129 "VParseBison.c" break; case 2821: /* sexpr: sexpr "<=" expr */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 38135 "VParseBison.c" break; case 2822: /* sexpr: sexpr '?' expr ':' expr */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = (yyvsp[-4].str)+"?"+(yyvsp[-2].str)+":"+(yyvsp[0].str); } #line 38141 "VParseBison.c" break; case 2823: /* sexpr: sexpr "inside" '{' open_range_list '}' */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = (yyvsp[-4].str)+" inside {"+(yyvsp[-2].str)+"}"; } #line 38147 "VParseBison.c" break; case 2824: /* sexpr: "tagged" id */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str) = " tagged "+(yyvsp[-1].str); } #line 38153 "VParseBison.c" break; case 2825: /* sexpr: "tagged" id expr */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = " tagged "+(yyvsp[-2].str)+" "+(yyvsp[-1].str); } #line 38159 "VParseBison.c" break; case 2826: /* sexpr: "INTEGER NUMBER" */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 38165 "VParseBison.c" break; case 2827: /* sexpr: "FLOATING-POINT NUMBER" */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 38171 "VParseBison.c" break; case 2828: /* sexpr: "TIME NUMBER" */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 38177 "VParseBison.c" break; case 2829: /* sexpr: strAsInt */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 38183 "VParseBison.c" break; case 2831: /* sexpr: '{' constExpr '{' cateList '}' '}' */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-5].fl); (yyval.str) = "{"+(yyvsp[-4].str)+"{"+(yyvsp[-2].str)+"}}"; } #line 38189 "VParseBison.c" break; case 2832: /* sexpr: '{' constExpr '{' cateList '}' '}' '[' expr ']' */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-8].fl); (yyval.str) = "{"+(yyvsp[-7].str)+"{"+(yyvsp[-5].str)+"}}["+(yyvsp[-1].str)+"]"; NEED_S09((yyvsp[-3].fl),"{}[]"); } #line 38195 "VParseBison.c" break; case 2833: /* sexpr: '{' constExpr '{' cateList '}' '}' '[' expr ':' expr ']' */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-10].fl); (yyval.str) = "{"+(yyvsp[-9].str)+"{"+(yyvsp[-7].str)+"}}["+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+"]"; NEED_S09((yyvsp[-5].fl),"{}[]"); } #line 38201 "VParseBison.c" break; case 2834: /* sexpr: '{' constExpr '{' cateList '}' '}' '[' expr "+:" expr ']' */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-10].fl); (yyval.str) = "{"+(yyvsp[-9].str)+"{"+(yyvsp[-7].str)+"}}["+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+"]"; NEED_S09((yyvsp[-5].fl),"{}[]"); } #line 38207 "VParseBison.c" break; case 2835: /* sexpr: '{' constExpr '{' cateList '}' '}' '[' expr "-:" expr ']' */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-10].fl); (yyval.str) = "{"+(yyvsp[-9].str)+"{"+(yyvsp[-7].str)+"}}["+(yyvsp[-3].str)+(yyvsp[-2].str)+(yyvsp[-1].str)+"]"; NEED_S09((yyvsp[-5].fl),"{}[]"); } #line 38213 "VParseBison.c" break; case 2836: /* sexpr: function_subroutine_callNoMethod */ #line 4218 "VParseBison.y" { (yyval.str) = (yyvsp[0].str); } #line 38219 "VParseBison.c" break; case 2837: /* sexpr: sexpr '.' function_subroutine_callNoMethod */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str)=(yyvsp[-2].str)+"."+(yyvsp[0].str); } #line 38225 "VParseBison.c" break; case 2838: /* sexpr: sexpr '.' array_methodNoRoot */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str)+"."+(yyvsp[0].str); } #line 38231 "VParseBison.c" break; case 2839: /* sexpr: "(-ignored" '(' expr ')' */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-3].fl); (yyval.str) = "("+(yyvsp[-2].str)+")"; } #line 38237 "VParseBison.c" break; case 2840: /* sexpr: "(-ignored" '(' expr ':' expr ':' expr ')' */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-7].fl); (yyval.str) = "("+(yyvsp[-6].str)+":"+(yyvsp[-4].str)+":"+(yyvsp[-3].str)+")"; } #line 38243 "VParseBison.c" break; case 2841: /* sexpr: '_' '(' statePushVlg expr statePop ')' */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-5].fl); (yyval.str) = "_("+(yyvsp[-2].str)+")"; } #line 38249 "VParseBison.c" break; case 2842: /* sexpr: casting_type "'" '(' expr ')' */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = (yyvsp[-4].str)+"'("+(yyvsp[-1].str)+")"; } #line 38255 "VParseBison.c" break; case 2843: /* sexpr: sexpr "'" '(' expr ')' */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = (yyvsp[-4].str)+"'("+(yyvsp[-1].str)+")"; } #line 38261 "VParseBison.c" break; case 2844: /* sexpr: '$' */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = "$"; } #line 38267 "VParseBison.c" break; case 2845: /* sexpr: "null" */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 38273 "VParseBison.c" break; case 2846: /* sexpr: sexprOkLvalue */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 38279 "VParseBison.c" break; case 2847: /* sexpr: sexpr "&&&" expr */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str) + "&&&" + (yyvsp[0].str); } #line 38285 "VParseBison.c" break; case 2848: /* sexpr: sexpr "matches" patternNoExpr */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str) + " matches " + (yyvsp[0].str); } #line 38291 "VParseBison.c" break; case 2849: /* sexpr: sexpr "matches" expr */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str) = (yyvsp[-2].str) + " matches " + (yyvsp[0].str); } #line 38297 "VParseBison.c" break; case 2850: /* sexpr: sexpr "dist" '{' dist_list '}' */ #line 4218 "VParseBison.y" { (yyval.fl)=(yyvsp[-4].fl); (yyval.str) = (yyvsp[-4].str) + " dist " + (yyvsp[-2].str)+"..."+(yyvsp[0].str); } #line 38303 "VParseBison.c" break; case 2851: /* cycle_delay_range: "##" "INTEGER NUMBER" */ #line 4223 "VParseBison.y" { } #line 38309 "VParseBison.c" break; case 2852: /* cycle_delay_range: "##" id */ #line 4224 "VParseBison.y" { } #line 38315 "VParseBison.c" break; case 2853: /* cycle_delay_range: "##" '(' constExpr ')' */ #line 4225 "VParseBison.y" { } #line 38321 "VParseBison.c" break; case 2854: /* cycle_delay_range: "##" '[' cycle_delay_const_range_expression ']' */ #line 4231 "VParseBison.y" { } #line 38327 "VParseBison.c" break; case 2855: /* cycle_delay_range: "##" "[*" ']' */ #line 4232 "VParseBison.y" { } #line 38333 "VParseBison.c" break; case 2856: /* cycle_delay_range: "##" "[+]" */ #line 4233 "VParseBison.y" { } #line 38339 "VParseBison.c" break; case 2857: /* sequence_match_itemList: sequence_match_item */ #line 4237 "VParseBison.y" { } #line 38345 "VParseBison.c" break; case 2858: /* sequence_match_itemList: sequence_match_itemList ',' sequence_match_item */ #line 4238 "VParseBison.y" { } #line 38351 "VParseBison.c" break; case 2859: /* sequence_match_item: for_step_assignment */ #line 4246 "VParseBison.y" { } #line 38357 "VParseBison.c" break; case 2860: /* boolean_abbrev: "[*" const_or_range_expression ']' */ #line 4251 "VParseBison.y" { } #line 38363 "VParseBison.c" break; case 2861: /* boolean_abbrev: "[*" ']' */ #line 4252 "VParseBison.y" { } #line 38369 "VParseBison.c" break; case 2862: /* boolean_abbrev: "[+]" */ #line 4253 "VParseBison.y" { } #line 38375 "VParseBison.c" break; case 2863: /* boolean_abbrev: "[=" const_or_range_expression ']' */ #line 4255 "VParseBison.y" { } #line 38381 "VParseBison.c" break; case 2864: /* boolean_abbrev: "[->" const_or_range_expression ']' */ #line 4257 "VParseBison.y" { } #line 38387 "VParseBison.c" break; case 2865: /* const_or_range_expression: constExpr */ #line 4261 "VParseBison.y" { } #line 38393 "VParseBison.c" break; case 2866: /* const_or_range_expression: cycle_delay_const_range_expression */ #line 4262 "VParseBison.y" { } #line 38399 "VParseBison.c" break; case 2867: /* constant_range: constExpr ':' constExpr */ #line 4267 "VParseBison.y" { } #line 38405 "VParseBison.c" break; case 2868: /* cycle_delay_const_range_expression: constExpr ':' constExpr */ #line 4272 "VParseBison.y" { } #line 38411 "VParseBison.c" break; case 2869: /* let_declaration: let_declarationFront let_port_listE '=' expr ';' */ #line 4280 "VParseBison.y" { PARSEP->symPopScope(VAstType::LET); } #line 38417 "VParseBison.c" break; case 2870: /* let_declarationFront: "let" idAny */ #line 4285 "VParseBison.y" { PARSEP->symPushNew(VAstType::LET,(yyvsp[0].str)); } #line 38423 "VParseBison.c" break; case 2872: /* let_port_listE: '(' tf_port_listE ')' */ #line 4293 "VParseBison.y" { VARRESET_NONLIST(""); } #line 38429 "VParseBison.c" break; case 2873: /* covergroup_declaration: covergroup_declarationFront coverage_eventE ';' coverage_spec_or_optionListE "endgroup" endLabelE */ #line 4302 "VParseBison.y" { PARSEP->endgroupCb((yyvsp[-1].fl),(yyvsp[-1].str)); PARSEP->symPopScope(VAstType::COVERGROUP); } #line 38436 "VParseBison.c" break; case 2874: /* covergroup_declaration: covergroup_declarationFront '(' tf_port_listE ')' coverage_eventE ';' coverage_spec_or_optionListE "endgroup" endLabelE */ #line 4306 "VParseBison.y" { PARSEP->endgroupCb((yyvsp[-1].fl),(yyvsp[-1].str)); PARSEP->symPopScope(VAstType::COVERGROUP); } #line 38443 "VParseBison.c" break; case 2875: /* covergroup_declarationFront: "covergroup" idAny */ #line 4312 "VParseBison.y" { PARSEP->symPushNew(VAstType::COVERGROUP,(yyvsp[0].str)); PARSEP->covergroupCb((yyvsp[-1].fl),(yyvsp[-1].str),(yyvsp[0].str)); } #line 38450 "VParseBison.c" break; case 2876: /* cgexpr: expr */ #line 4317 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str) = (yyvsp[0].str); } #line 38456 "VParseBison.c" break; case 2877: /* coverage_spec_or_optionListE: %empty */ #line 4321 "VParseBison.y" { } #line 38462 "VParseBison.c" break; case 2878: /* coverage_spec_or_optionListE: coverage_spec_or_optionList */ #line 4322 "VParseBison.y" { } #line 38468 "VParseBison.c" break; case 2879: /* coverage_spec_or_optionList: coverage_spec_or_option */ #line 4326 "VParseBison.y" { } #line 38474 "VParseBison.c" break; case 2880: /* coverage_spec_or_optionList: coverage_spec_or_optionList coverage_spec_or_option */ #line 4327 "VParseBison.y" { } #line 38480 "VParseBison.c" break; case 2881: /* coverage_spec_or_option: cover_point */ #line 4332 "VParseBison.y" { } #line 38486 "VParseBison.c" break; case 2882: /* coverage_spec_or_option: cover_cross */ #line 4333 "VParseBison.y" { } #line 38492 "VParseBison.c" break; case 2883: /* coverage_spec_or_option: coverage_option ';' */ #line 4334 "VParseBison.y" { } #line 38498 "VParseBison.c" break; case 2884: /* coverage_spec_or_option: error */ #line 4335 "VParseBison.y" { } #line 38504 "VParseBison.c" break; case 2885: /* coverage_option: id '.' idAny '=' expr */ #line 4340 "VParseBison.y" { } #line 38510 "VParseBison.c" break; case 2886: /* cover_point: "coverpoint" expr iffE bins_or_empty */ #line 4344 "VParseBison.y" { } #line 38516 "VParseBison.c" break; case 2887: /* cover_point: id ':' "coverpoint" expr iffE bins_or_empty */ #line 4346 "VParseBison.y" { } #line 38522 "VParseBison.c" break; case 2888: /* cover_point: class_scope_id ':' "coverpoint" expr iffE bins_or_empty */ #line 4347 "VParseBison.y" { } #line 38528 "VParseBison.c" break; case 2889: /* cover_point: class_scope_id id data_type id ':' "coverpoint" expr iffE bins_or_empty */ #line 4348 "VParseBison.y" { } #line 38534 "VParseBison.c" break; case 2890: /* cover_point: class_scope_id id id ':' "coverpoint" expr iffE bins_or_empty */ #line 4349 "VParseBison.y" { } #line 38540 "VParseBison.c" break; case 2891: /* cover_point: id id ':' "coverpoint" expr iffE bins_or_empty */ #line 4350 "VParseBison.y" { } #line 38546 "VParseBison.c" break; case 2892: /* cover_point: bins_or_empty */ #line 4352 "VParseBison.y" { } #line 38552 "VParseBison.c" break; case 2893: /* iffE: %empty */ #line 4356 "VParseBison.y" { } #line 38558 "VParseBison.c" break; case 2894: /* iffE: "iff" '(' expr ')' */ #line 4357 "VParseBison.y" { } #line 38564 "VParseBison.c" break; case 2895: /* bins_or_empty: '{' bins_or_optionsList '}' */ #line 4361 "VParseBison.y" { } #line 38570 "VParseBison.c" break; case 2896: /* bins_or_empty: '{' '}' */ #line 4362 "VParseBison.y" { } #line 38576 "VParseBison.c" break; case 2897: /* bins_or_empty: ';' */ #line 4363 "VParseBison.y" { } #line 38582 "VParseBison.c" break; case 2898: /* bins_or_optionsList: bins_or_options ';' */ #line 4367 "VParseBison.y" { } #line 38588 "VParseBison.c" break; case 2899: /* bins_or_optionsList: bins_or_optionsList bins_or_options ';' */ #line 4368 "VParseBison.y" { } #line 38594 "VParseBison.c" break; case 2900: /* bins_or_options: coverage_option */ #line 4373 "VParseBison.y" { } #line 38600 "VParseBison.c" break; case 2901: /* bins_or_options: bins_keyword id bins_orBraE '=' '{' open_range_list '}' iffE */ #line 4375 "VParseBison.y" { } #line 38606 "VParseBison.c" break; case 2902: /* bins_or_options: "wildcard" bins_keyword id bins_orBraE '=' '{' open_range_list '}' iffE */ #line 4376 "VParseBison.y" { } #line 38612 "VParseBison.c" break; case 2903: /* bins_or_options: bins_keyword id bins_orBraE '=' '{' open_range_list '}' "with-then-{" '{' cgexpr ')' iffE */ #line 4377 "VParseBison.y" { } #line 38618 "VParseBison.c" break; case 2904: /* bins_or_options: "wildcard" bins_keyword id bins_orBraE '=' '{' open_range_list '}' "with-then-{" '{' cgexpr ')' iffE */ #line 4378 "VParseBison.y" { } #line 38624 "VParseBison.c" break; case 2905: /* bins_or_options: bins_keyword id bins_orBraE '=' trans_list iffE */ #line 4382 "VParseBison.y" { } #line 38630 "VParseBison.c" break; case 2906: /* bins_or_options: "wildcard" bins_keyword id bins_orBraE '=' trans_list iffE */ #line 4383 "VParseBison.y" { } #line 38636 "VParseBison.c" break; case 2907: /* bins_or_options: bins_keyword id bins_orBraE '=' "default" iffE */ #line 4385 "VParseBison.y" { } #line 38642 "VParseBison.c" break; case 2908: /* bins_or_options: bins_keyword id bins_orBraE '=' "default" "sequence" iffE */ #line 4387 "VParseBison.y" { } #line 38648 "VParseBison.c" break; case 2909: /* bins_orBraE: %empty */ #line 4391 "VParseBison.y" { } #line 38654 "VParseBison.c" break; case 2910: /* bins_orBraE: '[' ']' */ #line 4392 "VParseBison.y" { } #line 38660 "VParseBison.c" break; case 2911: /* bins_orBraE: '[' cgexpr ']' */ #line 4393 "VParseBison.y" { } #line 38666 "VParseBison.c" break; case 2912: /* bins_keyword: "bins" */ #line 4397 "VParseBison.y" { } #line 38672 "VParseBison.c" break; case 2913: /* bins_keyword: "illegal_bins" */ #line 4398 "VParseBison.y" { } #line 38678 "VParseBison.c" break; case 2914: /* bins_keyword: "ignore_bins" */ #line 4399 "VParseBison.y" { } #line 38684 "VParseBison.c" break; case 2915: /* covergroup_range_list: covergroup_value_range */ #line 4403 "VParseBison.y" { } #line 38690 "VParseBison.c" break; case 2916: /* covergroup_range_list: covergroup_range_list ',' covergroup_value_range */ #line 4404 "VParseBison.y" { } #line 38696 "VParseBison.c" break; case 2917: /* trans_list: '(' trans_set ')' */ #line 4408 "VParseBison.y" { } #line 38702 "VParseBison.c" break; case 2918: /* trans_list: trans_list ',' '(' trans_set ')' */ #line 4409 "VParseBison.y" { } #line 38708 "VParseBison.c" break; case 2919: /* trans_set: trans_range_list */ #line 4413 "VParseBison.y" { } #line 38714 "VParseBison.c" break; case 2920: /* trans_set: trans_set "=>" trans_range_list */ #line 4415 "VParseBison.y" { } #line 38720 "VParseBison.c" break; case 2921: /* trans_range_list: trans_item */ #line 4419 "VParseBison.y" { } #line 38726 "VParseBison.c" break; case 2922: /* trans_range_list: trans_item "[*" repeat_range ']' */ #line 4420 "VParseBison.y" { } #line 38732 "VParseBison.c" break; case 2923: /* trans_range_list: trans_item "[->" repeat_range ']' */ #line 4421 "VParseBison.y" { } #line 38738 "VParseBison.c" break; case 2924: /* trans_range_list: trans_item "[=" repeat_range ']' */ #line 4422 "VParseBison.y" { } #line 38744 "VParseBison.c" break; case 2925: /* trans_item: covergroup_range_list */ #line 4426 "VParseBison.y" { } #line 38750 "VParseBison.c" break; case 2926: /* repeat_range: cgexpr */ #line 4430 "VParseBison.y" { } #line 38756 "VParseBison.c" break; case 2927: /* repeat_range: cgexpr ':' cgexpr */ #line 4431 "VParseBison.y" { } #line 38762 "VParseBison.c" break; case 2928: /* cover_cross: id ':' "cross" list_of_cross_items iffE cross_body */ #line 4435 "VParseBison.y" { } #line 38768 "VParseBison.c" break; case 2929: /* cover_cross: "cross" list_of_cross_items iffE cross_body */ #line 4436 "VParseBison.y" { } #line 38774 "VParseBison.c" break; case 2930: /* list_of_cross_items: cross_item ',' cross_item */ #line 4440 "VParseBison.y" { } #line 38780 "VParseBison.c" break; case 2931: /* list_of_cross_items: cross_item ',' cross_item ',' cross_itemList */ #line 4441 "VParseBison.y" { } #line 38786 "VParseBison.c" break; case 2933: /* cross_itemList: cross_itemList ',' cross_item */ #line 4446 "VParseBison.y" { } #line 38792 "VParseBison.c" break; case 2934: /* cross_item: idAny */ #line 4450 "VParseBison.y" { } #line 38798 "VParseBison.c" break; case 2935: /* cross_body: '{' '}' */ #line 4454 "VParseBison.y" { } #line 38804 "VParseBison.c" break; case 2936: /* cross_body: '{' cross_body_itemSemiList '}' */ #line 4456 "VParseBison.y" { } #line 38810 "VParseBison.c" break; case 2937: /* cross_body: ';' */ #line 4457 "VParseBison.y" { } #line 38816 "VParseBison.c" break; case 2938: /* cross_body_itemSemiList: cross_body_item ';' */ #line 4461 "VParseBison.y" { } #line 38822 "VParseBison.c" break; case 2939: /* cross_body_itemSemiList: cross_body_itemSemiList cross_body_item ';' */ #line 4462 "VParseBison.y" { } #line 38828 "VParseBison.c" break; case 2940: /* cross_body_item: bins_selection_or_option */ #line 4467 "VParseBison.y" { } #line 38834 "VParseBison.c" break; case 2941: /* cross_body_item: function_declaration */ #line 4468 "VParseBison.y" { } #line 38840 "VParseBison.c" break; case 2942: /* bins_selection_or_option: coverage_option */ #line 4472 "VParseBison.y" { } #line 38846 "VParseBison.c" break; case 2943: /* bins_selection_or_option: bins_selection */ #line 4473 "VParseBison.y" { } #line 38852 "VParseBison.c" break; case 2944: /* bins_selection: bins_keyword idAny '=' select_expression iffE */ #line 4477 "VParseBison.y" { } #line 38858 "VParseBison.c" break; case 2945: /* select_expression: "binsof" '(' bins_expression ')' */ #line 4482 "VParseBison.y" { } #line 38864 "VParseBison.c" break; case 2946: /* select_expression: "binsof" '(' bins_expression ')' "intersect" '{' covergroup_range_list '}' */ #line 4483 "VParseBison.y" { } #line 38870 "VParseBison.c" break; case 2947: /* select_expression: "with-then-(" '(' cgexpr ')' */ #line 4484 "VParseBison.y" { } #line 38876 "VParseBison.c" break; case 2948: /* select_expression: '!' "binsof" '(' bins_expression ')' */ #line 4487 "VParseBison.y" { } #line 38882 "VParseBison.c" break; case 2949: /* select_expression: '!' "binsof" '(' bins_expression ')' "intersect" '{' covergroup_range_list '}' */ #line 4488 "VParseBison.y" { } #line 38888 "VParseBison.c" break; case 2950: /* select_expression: '!' "with-then-(" '(' cgexpr ')' */ #line 4489 "VParseBison.y" { } #line 38894 "VParseBison.c" break; case 2951: /* select_expression: select_expression "&&" select_expression */ #line 4492 "VParseBison.y" { } #line 38900 "VParseBison.c" break; case 2952: /* select_expression: select_expression "||" select_expression */ #line 4493 "VParseBison.y" { } #line 38906 "VParseBison.c" break; case 2953: /* select_expression: '(' select_expression ')' */ #line 4494 "VParseBison.y" { } #line 38912 "VParseBison.c" break; case 2954: /* bins_expression: id */ #line 4503 "VParseBison.y" { } #line 38918 "VParseBison.c" break; case 2955: /* bins_expression: id '.' idAny */ #line 4504 "VParseBison.y" { } #line 38924 "VParseBison.c" break; case 2956: /* coverage_eventE: %empty */ #line 4508 "VParseBison.y" { } #line 38930 "VParseBison.c" break; case 2957: /* coverage_eventE: clocking_event */ #line 4509 "VParseBison.y" { } #line 38936 "VParseBison.c" break; case 2958: /* coverage_eventE: "with" function idAny '(' tf_port_listE ')' */ #line 4510 "VParseBison.y" { } #line 38942 "VParseBison.c" break; case 2959: /* coverage_eventE: "@@" '(' block_event_expression ')' */ #line 4511 "VParseBison.y" { } #line 38948 "VParseBison.c" break; case 2960: /* block_event_expression: block_event_expressionTerm */ #line 4515 "VParseBison.y" { } #line 38954 "VParseBison.c" break; case 2961: /* block_event_expression: block_event_expression "or" block_event_expressionTerm */ #line 4516 "VParseBison.y" { } #line 38960 "VParseBison.c" break; case 2962: /* block_event_expressionTerm: "begin" hierarchical_btf_identifier */ #line 4520 "VParseBison.y" { } #line 38966 "VParseBison.c" break; case 2963: /* block_event_expressionTerm: "end" hierarchical_btf_identifier */ #line 4521 "VParseBison.y" { } #line 38972 "VParseBison.c" break; case 2964: /* hierarchical_btf_identifier: hierarchical_identifier */ #line 4526 "VParseBison.y" { } #line 38978 "VParseBison.c" break; case 2965: /* hierarchical_btf_identifier: hierarchical_identifier class_scope_id */ #line 4528 "VParseBison.y" { } #line 38984 "VParseBison.c" break; case 2966: /* hierarchical_btf_identifier: hierarchical_identifier id */ #line 4529 "VParseBison.y" { } #line 38990 "VParseBison.c" break; case 2967: /* randsequence_statement: "randsequence" '(' ')' productionList "endsequence" */ #line 4536 "VParseBison.y" { } #line 38996 "VParseBison.c" break; case 2968: /* randsequence_statement: "randsequence" '(' id ')' productionList "endsequence" */ #line 4537 "VParseBison.y" { } #line 39002 "VParseBison.c" break; case 2969: /* productionList: production */ #line 4541 "VParseBison.y" { } #line 39008 "VParseBison.c" break; case 2970: /* productionList: productionList production */ #line 4542 "VParseBison.y" { } #line 39014 "VParseBison.c" break; case 2971: /* production: productionFront ':' rs_ruleList ';' */ #line 4546 "VParseBison.y" { } #line 39020 "VParseBison.c" break; case 2972: /* productionFront: function_data_type id */ #line 4550 "VParseBison.y" { } #line 39026 "VParseBison.c" break; case 2973: /* productionFront: id */ #line 4551 "VParseBison.y" { } #line 39032 "VParseBison.c" break; case 2974: /* productionFront: function_data_type id '(' tf_port_listE ')' */ #line 4552 "VParseBison.y" { } #line 39038 "VParseBison.c" break; case 2975: /* productionFront: id '(' tf_port_listE ')' */ #line 4553 "VParseBison.y" { } #line 39044 "VParseBison.c" break; case 2976: /* rs_ruleList: rs_rule */ #line 4557 "VParseBison.y" { } #line 39050 "VParseBison.c" break; case 2977: /* rs_ruleList: rs_ruleList '|' rs_rule */ #line 4558 "VParseBison.y" { } #line 39056 "VParseBison.c" break; case 2978: /* rs_rule: rs_production_list */ #line 4562 "VParseBison.y" { } #line 39062 "VParseBison.c" break; case 2979: /* rs_rule: rs_production_list ":=" weight_specification */ #line 4563 "VParseBison.y" { } #line 39068 "VParseBison.c" break; case 2980: /* rs_rule: rs_production_list ":=" weight_specification rs_code_block */ #line 4564 "VParseBison.y" { } #line 39074 "VParseBison.c" break; case 2981: /* rs_production_list: rs_prodList */ #line 4568 "VParseBison.y" { } #line 39080 "VParseBison.c" break; case 2982: /* rs_production_list: "rand" "join" production_item production_itemList */ #line 4569 "VParseBison.y" { } #line 39086 "VParseBison.c" break; case 2983: /* rs_production_list: "rand" "join" '(' expr ')' production_item production_itemList */ #line 4570 "VParseBison.y" { } #line 39092 "VParseBison.c" break; case 2984: /* weight_specification: "INTEGER NUMBER" */ #line 4574 "VParseBison.y" { } #line 39098 "VParseBison.c" break; case 2985: /* weight_specification: idClassSel */ #line 4575 "VParseBison.y" { } #line 39104 "VParseBison.c" break; case 2986: /* weight_specification: '(' expr ')' */ #line 4576 "VParseBison.y" { } #line 39110 "VParseBison.c" break; case 2987: /* rs_code_block: '{' '}' */ #line 4580 "VParseBison.y" { } #line 39116 "VParseBison.c" break; case 2988: /* rs_code_block: '{' rs_code_blockItemList '}' */ #line 4581 "VParseBison.y" { } #line 39122 "VParseBison.c" break; case 2989: /* rs_code_blockItemList: rs_code_blockItem */ #line 4585 "VParseBison.y" { } #line 39128 "VParseBison.c" break; case 2990: /* rs_code_blockItemList: rs_code_blockItemList rs_code_blockItem */ #line 4586 "VParseBison.y" { } #line 39134 "VParseBison.c" break; case 2991: /* rs_code_blockItem: data_declaration */ #line 4590 "VParseBison.y" { } #line 39140 "VParseBison.c" break; case 2992: /* rs_code_blockItem: stmt */ #line 4591 "VParseBison.y" { } #line 39146 "VParseBison.c" break; case 2993: /* rs_prodList: rs_prod */ #line 4595 "VParseBison.y" { } #line 39152 "VParseBison.c" break; case 2994: /* rs_prodList: rs_prodList rs_prod */ #line 4596 "VParseBison.y" { } #line 39158 "VParseBison.c" break; case 2995: /* rs_prod: production_item */ #line 4600 "VParseBison.y" { } #line 39164 "VParseBison.c" break; case 2996: /* rs_prod: rs_code_block */ #line 4601 "VParseBison.y" { } #line 39170 "VParseBison.c" break; case 2997: /* rs_prod: "if" '(' expr ')' production_item */ #line 4603 "VParseBison.y" { } #line 39176 "VParseBison.c" break; case 2998: /* rs_prod: "if" '(' expr ')' production_item "else" production_item */ #line 4604 "VParseBison.y" { } #line 39182 "VParseBison.c" break; case 2999: /* rs_prod: "repeat" '(' expr ')' production_item */ #line 4606 "VParseBison.y" { } #line 39188 "VParseBison.c" break; case 3000: /* rs_prod: "case" '(' expr ')' rs_case_itemList "endcase" */ #line 4608 "VParseBison.y" { } #line 39194 "VParseBison.c" break; case 3001: /* production_itemList: production_item */ #line 4612 "VParseBison.y" { } #line 39200 "VParseBison.c" break; case 3002: /* production_itemList: production_itemList production_item */ #line 4613 "VParseBison.y" { } #line 39206 "VParseBison.c" break; case 3003: /* production_item: id */ #line 4617 "VParseBison.y" { } #line 39212 "VParseBison.c" break; case 3004: /* production_item: id '(' list_of_argumentsE ')' */ #line 4618 "VParseBison.y" { } #line 39218 "VParseBison.c" break; case 3005: /* rs_case_itemList: rs_case_item */ #line 4622 "VParseBison.y" { } #line 39224 "VParseBison.c" break; case 3006: /* rs_case_itemList: rs_case_itemList rs_case_item */ #line 4623 "VParseBison.y" { } #line 39230 "VParseBison.c" break; case 3007: /* rs_case_item: caseCondList ':' production_item ';' */ #line 4627 "VParseBison.y" { } #line 39236 "VParseBison.c" break; case 3008: /* rs_case_item: "default" production_item ';' */ #line 4628 "VParseBison.y" { } #line 39242 "VParseBison.c" break; case 3009: /* rs_case_item: "default" ':' production_item ';' */ #line 4629 "VParseBison.y" { } #line 39248 "VParseBison.c" break; case 3010: /* checker_declaration: checkerFront checker_port_listE ';' checker_or_generate_itemListE "endchecker" endLabelE */ #line 4638 "VParseBison.y" { PARSEP->symPopScope(VAstType::CHECKER); } #line 39254 "VParseBison.c" break; case 3011: /* checkerFront: "checker" idAny */ #line 4643 "VParseBison.y" { PARSEP->symPushNew(VAstType::CHECKER, (yyvsp[0].str)); } #line 39260 "VParseBison.c" break; case 3012: /* checker_port_listE: property_port_listE */ #line 4649 "VParseBison.y" { } #line 39266 "VParseBison.c" break; case 3013: /* checker_or_generate_itemListE: %empty */ #line 4653 "VParseBison.y" { } #line 39272 "VParseBison.c" break; case 3014: /* checker_or_generate_itemListE: checker_or_generate_itemList */ #line 4654 "VParseBison.y" { } #line 39278 "VParseBison.c" break; case 3015: /* checker_or_generate_itemList: checker_or_generate_item */ #line 4658 "VParseBison.y" { } #line 39284 "VParseBison.c" break; case 3016: /* checker_or_generate_itemList: checker_or_generate_itemList checker_or_generate_item */ #line 4659 "VParseBison.y" { } #line 39290 "VParseBison.c" break; case 3017: /* checker_or_generate_item: checker_or_generate_item_declaration */ #line 4663 "VParseBison.y" { } #line 39296 "VParseBison.c" break; case 3018: /* checker_or_generate_item: initial_construct */ #line 4664 "VParseBison.y" { } #line 39302 "VParseBison.c" break; case 3019: /* checker_or_generate_item: "always" stmtBlock */ #line 4666 "VParseBison.y" { } #line 39308 "VParseBison.c" break; case 3020: /* checker_or_generate_item: final_construct */ #line 4667 "VParseBison.y" { } #line 39314 "VParseBison.c" break; case 3021: /* checker_or_generate_item: assertion_item */ #line 4668 "VParseBison.y" { } #line 39320 "VParseBison.c" break; case 3022: /* checker_or_generate_item: continuous_assign */ #line 4669 "VParseBison.y" { } #line 39326 "VParseBison.c" break; case 3023: /* checker_or_generate_item: checker_generate_item */ #line 4670 "VParseBison.y" { } #line 39332 "VParseBison.c" break; case 3024: /* checker_or_generate_item_declaration: data_declaration */ #line 4674 "VParseBison.y" { } #line 39338 "VParseBison.c" break; case 3025: /* checker_or_generate_item_declaration: "rand" data_declaration */ #line 4675 "VParseBison.y" { } #line 39344 "VParseBison.c" break; case 3026: /* checker_or_generate_item_declaration: function_declaration */ #line 4676 "VParseBison.y" { } #line 39350 "VParseBison.c" break; case 3027: /* checker_or_generate_item_declaration: checker_declaration */ #line 4677 "VParseBison.y" { } #line 39356 "VParseBison.c" break; case 3028: /* checker_or_generate_item_declaration: assertion_item_declaration */ #line 4678 "VParseBison.y" { } #line 39362 "VParseBison.c" break; case 3029: /* checker_or_generate_item_declaration: covergroup_declaration */ #line 4679 "VParseBison.y" { } #line 39368 "VParseBison.c" break; case 3030: /* checker_or_generate_item_declaration: overload_declaration */ #line 4680 "VParseBison.y" { } #line 39374 "VParseBison.c" break; case 3031: /* checker_or_generate_item_declaration: genvar_declaration */ #line 4681 "VParseBison.y" { } #line 39380 "VParseBison.c" break; case 3032: /* checker_or_generate_item_declaration: clocking_declaration */ #line 4682 "VParseBison.y" { } #line 39386 "VParseBison.c" break; case 3033: /* checker_or_generate_item_declaration: "default" "clocking" id ';' */ #line 4683 "VParseBison.y" { } #line 39392 "VParseBison.c" break; case 3034: /* checker_or_generate_item_declaration: "default" "disable" "iff" expr ';' */ #line 4684 "VParseBison.y" { } #line 39398 "VParseBison.c" break; case 3035: /* checker_or_generate_item_declaration: ';' */ #line 4685 "VParseBison.y" { } #line 39404 "VParseBison.c" break; case 3036: /* checker_generate_item: c_loop_generate_construct */ #line 4690 "VParseBison.y" { } #line 39410 "VParseBison.c" break; case 3037: /* checker_generate_item: c_conditional_generate_construct */ #line 4691 "VParseBison.y" { } #line 39416 "VParseBison.c" break; case 3038: /* checker_generate_item: c_generate_region */ #line 4692 "VParseBison.y" { } #line 39422 "VParseBison.c" break; case 3039: /* checker_generate_item: elaboration_system_task */ #line 4694 "VParseBison.y" { } #line 39428 "VParseBison.c" break; case 3040: /* checker_instantiation: id id '(' cellpinList ')' ';' */ #line 4701 "VParseBison.y" { } #line 39434 "VParseBison.c" break; case 3041: /* class_declaration: classFront parameter_port_listE classExtendsE classImplementsE ';' class_itemListE "endclass" endLabelE */ #line 4713 "VParseBison.y" { PARSEP->endclassCb((yyvsp[-1].fl),(yyvsp[-1].str)); PARSEP->symPopScope(VAstType::CLASS); } #line 39441 "VParseBison.c" break; case 3042: /* classFront: classVirtualE "class" lifetimeE idAny */ #line 4719 "VParseBison.y" { PARSEP->symPushNew(VAstType::CLASS, (yyvsp[0].str)); PARSEP->classCb((yyvsp[-2].fl),(yyvsp[-2].str),(yyvsp[0].str),(yyvsp[-3].str)); } #line 39448 "VParseBison.c" break; case 3043: /* classFront: "interface" "class" lifetimeE idAny */ #line 4723 "VParseBison.y" { PARSEP->symPushNew(VAstType::CLASS, (yyvsp[0].str)); PARSEP->classCb((yyvsp[-2].fl),(yyvsp[-2].str),(yyvsp[0].str),(yyvsp[-3].str)); } #line 39455 "VParseBison.c" break; case 3044: /* classVirtualE: %empty */ #line 4728 "VParseBison.y" { (yyval.str)=""; } #line 39461 "VParseBison.c" break; case 3045: /* classVirtualE: "virtual-then-class" */ #line 4729 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 39467 "VParseBison.c" break; case 3046: /* classExtendsE: %empty */ #line 4735 "VParseBison.y" { } #line 39473 "VParseBison.c" break; case 3047: /* classExtendsE: "extends" class_typeWithoutId */ #line 4736 "VParseBison.y" { PARSEP->syms().import((yyvsp[-1].fl),(yyvsp[0].str),(yyvsp[0].scp),"*"); } #line 39479 "VParseBison.c" break; case 3048: /* classExtendsE: "extends" class_typeWithoutId '(' list_of_argumentsE ')' */ #line 4737 "VParseBison.y" { PARSEP->syms().import((yyvsp[-4].fl),(yyvsp[-3].str),(yyvsp[-3].scp),"*"); } #line 39485 "VParseBison.c" break; case 3049: /* classImplementsE: %empty */ #line 4742 "VParseBison.y" { } #line 39491 "VParseBison.c" break; case 3050: /* classImplementsE: "implements" classImplementsList */ #line 4743 "VParseBison.y" { PARSEP->syms().import((yyvsp[-1].fl),(yyvsp[0].str),(yyvsp[0].scp),"*"); } #line 39497 "VParseBison.c" break; case 3051: /* classImplementsList: class_typeWithoutId */ #line 4748 "VParseBison.y" { } #line 39503 "VParseBison.c" break; case 3052: /* classImplementsList: classImplementsList ',' class_typeWithoutId */ #line 4749 "VParseBison.y" { } #line 39509 "VParseBison.c" break; case 3053: /* ps_id_etc: package_scopeIdFollowsE id */ #line 4758 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str)=(yyvsp[-1].str)+(yyvsp[0].str); } #line 39515 "VParseBison.c" break; case 3054: /* class_scope_id: class_scopeIdFollows id */ #line 4762 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.scp)=(yyvsp[-1].scp); (yyval.str)=(yyvsp[-1].str)+(yyvsp[0].str); } #line 39521 "VParseBison.c" break; case 3055: /* class_typeWithoutId: package_scopeIdFollowsE class_typeOneList */ #line 4769 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.scp)=(yyvsp[0].scp); (yyval.str)=(yyvsp[-1].str)+(yyvsp[0].str); } #line 39527 "VParseBison.c" break; case 3056: /* class_scopeWithoutId: class_scopeIdFollows */ #line 4774 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.scp)=(yyvsp[0].scp); (yyval.str)=(yyvsp[0].str); PARSEP->symTableNextId(NULL); } #line 39533 "VParseBison.c" break; case 3057: /* class_scopeIdFollows: package_scopeIdFollowsE class_typeOneListColonIdFollows */ #line 4781 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.scp)=(yyvsp[0].scp); (yyval.str)=(yyvsp[-1].str)+(yyvsp[0].str); } #line 39539 "VParseBison.c" break; case 3058: /* class_typeOneListColonIdFollows: class_typeOneList "::" */ #line 4785 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.scp)=(yyvsp[-1].scp); (yyval.str)=(yyvsp[-1].str)+(yyvsp[0].str); PARSEP->symTableNextId((yyvsp[-1].scp)); } #line 39545 "VParseBison.c" break; case 3059: /* class_typeOneList: class_typeOne */ #line 4791 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.scp)=(yyvsp[0].scp); (yyval.str)=(yyvsp[0].str); } #line 39551 "VParseBison.c" break; case 3060: /* class_typeOneList: class_typeOneListColonIdFollows class_typeOne */ #line 4792 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.scp)=(yyvsp[0].scp); (yyval.str)=(yyvsp[-1].str)+(yyvsp[0].str); } #line 39557 "VParseBison.c" break; case 3061: /* class_typeOne: "TYPE-IDENTIFIER" parameter_value_assignmentE */ #line 4799 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.scp)=(yyvsp[-1].scp); (yyval.str)=(yyvsp[-1].str); } #line 39563 "VParseBison.c" break; case 3062: /* package_scopeIdFollowsE: %empty */ #line 4804 "VParseBison.y" { (yyval.str)=""; } #line 39569 "VParseBison.c" break; case 3063: /* package_scopeIdFollowsE: package_scopeIdFollows */ #line 4805 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 39575 "VParseBison.c" break; case 3064: /* $@21: %empty */ #line 4812 "VParseBison.y" { PARSEP->symTableNextId(PARSEP->syms().netlistSymp()); } #line 39581 "VParseBison.c" break; case 3065: /* package_scopeIdFollows: "$unit" $@21 "::" */ #line 4813 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str)=(yyvsp[-2].str)+(yyvsp[0].str); } #line 39587 "VParseBison.c" break; case 3066: /* $@22: %empty */ #line 4814 "VParseBison.y" { PARSEP->symTableNextId((yyvsp[0].scp)); } #line 39593 "VParseBison.c" break; case 3067: /* package_scopeIdFollows: "PACKAGE-IDENTIFIER" $@22 "::" */ #line 4815 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str)=(yyvsp[-2].str)+(yyvsp[0].str); } #line 39599 "VParseBison.c" break; case 3068: /* $@23: %empty */ #line 4816 "VParseBison.y" { PARSEP->symTableNextId((yyvsp[0].scp)); } #line 39605 "VParseBison.c" break; case 3069: /* package_scopeIdFollows: "local-then-::" $@23 "::" */ #line 4817 "VParseBison.y" { (yyval.fl)=(yyvsp[-2].fl); (yyval.str)=(yyvsp[-2].str)+(yyvsp[0].str); } #line 39611 "VParseBison.c" break; case 3070: /* class_itemListE: %empty */ #line 4823 "VParseBison.y" { } #line 39617 "VParseBison.c" break; case 3071: /* class_itemListE: class_itemList */ #line 4824 "VParseBison.y" { } #line 39623 "VParseBison.c" break; case 3072: /* class_itemList: class_item */ #line 4828 "VParseBison.y" { } #line 39629 "VParseBison.c" break; case 3073: /* class_itemList: class_itemList class_item */ #line 4829 "VParseBison.y" { } #line 39635 "VParseBison.c" break; case 3074: /* class_item: class_property */ #line 4833 "VParseBison.y" { } #line 39641 "VParseBison.c" break; case 3075: /* class_item: class_method */ #line 4834 "VParseBison.y" { } #line 39647 "VParseBison.c" break; case 3076: /* class_item: class_constraint */ #line 4835 "VParseBison.y" { } #line 39653 "VParseBison.c" break; case 3077: /* class_item: class_declaration */ #line 4837 "VParseBison.y" { } #line 39659 "VParseBison.c" break; case 3078: /* class_item: timeunits_declaration */ #line 4838 "VParseBison.y" { } #line 39665 "VParseBison.c" break; case 3079: /* class_item: covergroup_declaration */ #line 4839 "VParseBison.y" { } #line 39671 "VParseBison.c" break; case 3080: /* class_item: local_parameter_declaration ';' */ #line 4840 "VParseBison.y" { } #line 39677 "VParseBison.c" break; case 3081: /* class_item: parameter_declaration ';' */ #line 4841 "VParseBison.y" { } #line 39683 "VParseBison.c" break; case 3082: /* class_item: ';' */ #line 4842 "VParseBison.y" { } #line 39689 "VParseBison.c" break; case 3083: /* class_item: error ';' */ #line 4844 "VParseBison.y" { } #line 39695 "VParseBison.c" break; case 3084: /* class_method: memberQualResetListE task_declaration */ #line 4848 "VParseBison.y" { } #line 39701 "VParseBison.c" break; case 3085: /* class_method: memberQualResetListE function_declaration */ #line 4849 "VParseBison.y" { } #line 39707 "VParseBison.c" break; case 3086: /* class_method: "extern" memberQualResetListE method_prototype ';' */ #line 4851 "VParseBison.y" { } #line 39713 "VParseBison.c" break; case 3087: /* class_method: "extern" memberQualResetListE class_constructor_prototype */ #line 4854 "VParseBison.y" { } #line 39719 "VParseBison.c" break; case 3088: /* class_item_qualifier: "protected" */ #line 4862 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 39725 "VParseBison.c" break; case 3089: /* class_item_qualifier: "local" */ #line 4863 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 39731 "VParseBison.c" break; case 3090: /* class_item_qualifier: "static" */ #line 4864 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 39737 "VParseBison.c" break; case 3091: /* memberQualResetListE: %empty */ #line 4870 "VParseBison.y" { VARRESET(); VARDTYPE(""); } #line 39743 "VParseBison.c" break; case 3092: /* memberQualResetListE: memberQualList */ #line 4871 "VParseBison.y" { VARRESET(); VARDTYPE((yyvsp[0].str)); } #line 39749 "VParseBison.c" break; case 3093: /* memberQualList: memberQualOne */ #line 4875 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 39755 "VParseBison.c" break; case 3094: /* memberQualList: memberQualList memberQualOne */ #line 4876 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str)=SPACED((yyvsp[-1].str),(yyvsp[0].str)); } #line 39761 "VParseBison.c" break; case 3095: /* memberQualOne: class_item_qualifier */ #line 4881 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 39767 "VParseBison.c" break; case 3096: /* memberQualOne: "virtual" */ #line 4883 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 39773 "VParseBison.c" break; case 3097: /* memberQualOne: "pure" "virtual" */ #line 4885 "VParseBison.y" { (yyval.fl)=(yyvsp[-1].fl); (yyval.str)=(yyvsp[-1].str)+" "+(yyvsp[0].str); } #line 39779 "VParseBison.c" break; case 3098: /* memberQualOne: random_qualifier */ #line 4887 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 39785 "VParseBison.c" break; case 3099: /* memberQualOne: "automatic" */ #line 4889 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 39791 "VParseBison.c" break; case 3100: /* memberQualOne: "const" */ #line 4891 "VParseBison.y" { (yyval.fl)=(yyvsp[0].fl); (yyval.str)=(yyvsp[0].str); } #line 39797 "VParseBison.c" break; case 3101: /* class_constraint: constraintStaticE "constraint" idAny constraint_block */ #line 4899 "VParseBison.y" { } #line 39803 "VParseBison.c" break; case 3102: /* class_constraint: constraintStaticE "constraint" idAny ';' */ #line 4901 "VParseBison.y" { } #line 39809 "VParseBison.c" break; case 3103: /* class_constraint: "extern" constraintStaticE "constraint" idAny ';' */ #line 4902 "VParseBison.y" { } #line 39815 "VParseBison.c" break; case 3104: /* class_constraint: "pure" constraintStaticE "constraint" idAny ';' */ #line 4903 "VParseBison.y" { } #line 39821 "VParseBison.c" break; case 3105: /* constraint_block: '{' constraint_block_itemList '}' */ #line 4907 "VParseBison.y" { } #line 39827 "VParseBison.c" break; case 3106: /* constraint_block_itemList: constraint_block_item */ #line 4911 "VParseBison.y" { } #line 39833 "VParseBison.c" break; case 3107: /* constraint_block_itemList: constraint_block_itemList constraint_block_item */ #line 4912 "VParseBison.y" { } #line 39839 "VParseBison.c" break; case 3108: /* constraint_block_item: "solve" solve_before_list "before" solve_before_list ';' */ #line 4916 "VParseBison.y" { } #line 39845 "VParseBison.c" break; case 3109: /* constraint_block_item: constraint_expression */ #line 4917 "VParseBison.y" { } #line 39851 "VParseBison.c" break; case 3110: /* solve_before_list: constraint_primary */ #line 4921 "VParseBison.y" { } #line 39857 "VParseBison.c" break; case 3111: /* solve_before_list: solve_before_list ',' constraint_primary */ #line 4922 "VParseBison.y" { } #line 39863 "VParseBison.c" break; case 3112: /* constraint_primary: exprScope */ #line 4927 "VParseBison.y" { } #line 39869 "VParseBison.c" break; case 3113: /* constraint_expressionList: constraint_expression */ #line 4931 "VParseBison.y" { (yyval.str)=(yyvsp[0].str); } #line 39875 "VParseBison.c" break; case 3114: /* constraint_expressionList: constraint_expressionList constraint_expression */ #line 4932 "VParseBison.y" { (yyval.str)=(yyvsp[-1].str)+" "+(yyvsp[0].str); } #line 39881 "VParseBison.c" break; case 3115: /* constraint_expression: expr ';' */ #line 4936 "VParseBison.y" { (yyval.str)=(yyvsp[-1].str); } #line 39887 "VParseBison.c" break; case 3116: /* constraint_expression: "soft" expr ';' */ #line 4938 "VParseBison.y" { (yyval.str)="soft "+(yyvsp[-2].str); } #line 39893 "VParseBison.c" break; case 3117: /* constraint_expression: "unique" '{' open_range_list '}' */ #line 4941 "VParseBison.y" { (yyval.str)="unique {...}"; } #line 39899 "VParseBison.c" break; case 3118: /* constraint_expression: "if" '(' expr ')' constraint_set */ #line 4945 "VParseBison.y" { (yyval.str)=(yyvsp[-4].str); } #line 39905 "VParseBison.c" break; case 3119: /* constraint_expression: "if" '(' expr ')' constraint_set "else" constraint_set */ #line 4946 "VParseBison.y" { (yyval.str)=(yyvsp[-6].str);} #line 39911 "VParseBison.c" break; case 3120: /* constraint_expression: "foreach" '(' idClassForeach ')' constraint_set */ #line 4948 "VParseBison.y" { (yyval.str)=(yyvsp[-4].str); } #line 39917 "VParseBison.c" break; case 3121: /* constraint_expression: "disable" "soft" expr ';' */ #line 4950 "VParseBison.y" { (yyval.str)="disable soft "+(yyvsp[-3].str); } #line 39923 "VParseBison.c" break; case 3122: /* constraint_set: constraint_expression */ #line 4954 "VParseBison.y" { (yyval.str)=(yyvsp[0].str); } #line 39929 "VParseBison.c" break; case 3123: /* constraint_set: '{' constraint_expressionList '}' */ #line 4955 "VParseBison.y" { (yyval.str)=(yyvsp[-2].str)+(yyvsp[-1].str)+(yyvsp[0].str); } #line 39935 "VParseBison.c" break; case 3124: /* dist_list: dist_item */ #line 4959 "VParseBison.y" { } #line 39941 "VParseBison.c" break; case 3125: /* dist_list: dist_list ',' dist_item */ #line 4960 "VParseBison.y" { } #line 39947 "VParseBison.c" break; case 3126: /* dist_item: value_range */ #line 4964 "VParseBison.y" { } #line 39953 "VParseBison.c" break; case 3127: /* dist_item: value_range ":=" expr */ #line 4965 "VParseBison.y" { } #line 39959 "VParseBison.c" break; case 3128: /* dist_item: value_range ":/" expr */ #line 4966 "VParseBison.y" { } #line 39965 "VParseBison.c" break; case 3129: /* extern_constraint_declaration: constraintStaticE "constraint" class_scope_id constraint_block */ #line 4970 "VParseBison.y" { } #line 39971 "VParseBison.c" break; case 3130: /* constraintStaticE: %empty */ #line 4974 "VParseBison.y" { } #line 39977 "VParseBison.c" break; case 3131: /* constraintStaticE: "static-then-constraint" */ #line 4975 "VParseBison.y" { } #line 39983 "VParseBison.c" break; #line 39987 "VParseBison.c" default: break; } /* User semantic actions sometimes alter yychar, and that requires that yytoken be updated with the new translation. We take the approach of translating immediately before every use of yytoken. One alternative is translating here after every semantic action, but that translation would be missed if the semantic action invokes YYABORT, YYACCEPT, or YYERROR immediately after altering yychar or if it invokes YYBACKUP. In the case of YYABORT or YYACCEPT, an incorrect destructor might then be invoked immediately. In the case of YYERROR or YYBACKUP, subsequent parser actions might lead to an incorrect destructor call or verbose syntax error message before the lookahead is translated. */ YY_SYMBOL_PRINT ("-> $$ =", YY_CAST (yysymbol_kind_t, yyr1[yyn]), &yyval, &yyloc); YYPOPSTACK (yylen); yylen = 0; *++yyvsp = yyval; /* Now 'shift' the result of the reduction. Determine what state that goes to, based on the state we popped back to and the rule number reduced by. */ { const int yylhs = yyr1[yyn] - YYNTOKENS; const int yyi = yypgoto[yylhs] + *yyssp; yystate = (0 <= yyi && yyi <= YYLAST && yycheck[yyi] == *yyssp ? yytable[yyi] : yydefgoto[yylhs]); } goto yynewstate; /*--------------------------------------. | yyerrlab -- here on detecting error. | `--------------------------------------*/ yyerrlab: /* Make sure we have latest lookahead translation. See comments at user semantic actions for why this is necessary. */ yytoken = yychar == YYEMPTY ? YYSYMBOL_YYEMPTY : YYTRANSLATE (yychar); /* If not already recovering from an error, report this error. */ if (!yyerrstatus) { ++yynerrs; yyerror (YY_((char*)"syntax error")); } if (yyerrstatus == 3) { /* If just tried and failed to reuse lookahead token after an error, discard it. */ if (yychar <= YYEOF) { /* Return failure if at end of input. */ if (yychar == YYEOF) YYABORT; } else { yydestruct ("Error: discarding", yytoken, &yylval); yychar = YYEMPTY; } } /* Else will try to reuse lookahead token after shifting the error token. */ goto yyerrlab1; /*---------------------------------------------------. | yyerrorlab -- error raised explicitly by YYERROR. | `---------------------------------------------------*/ yyerrorlab: /* Pacify compilers when the user code never invokes YYERROR and the label yyerrorlab therefore never appears in user code. */ if (0) YYERROR; ++yynerrs; /* Do not reclaim the symbols of the rule whose action triggered this YYERROR. */ YYPOPSTACK (yylen); yylen = 0; YY_STACK_PRINT (yyss, yyssp); yystate = *yyssp; goto yyerrlab1; /*-------------------------------------------------------------. | yyerrlab1 -- common code for both syntax error and YYERROR. | `-------------------------------------------------------------*/ yyerrlab1: yyerrstatus = 3; /* Each real token shifted decrements this. */ /* Pop stack until we find a state that shifts the error token. */ for (;;) { yyn = yypact[yystate]; if (!yypact_value_is_default (yyn)) { yyn += YYSYMBOL_YYerror; if (0 <= yyn && yyn <= YYLAST && yycheck[yyn] == YYSYMBOL_YYerror) { yyn = yytable[yyn]; if (0 < yyn) break; } } /* Pop the current state because it cannot handle the error token. */ if (yyssp == yyss) YYABORT; yydestruct ("Error: popping", YY_ACCESSING_SYMBOL (yystate), yyvsp); YYPOPSTACK (1); yystate = *yyssp; YY_STACK_PRINT (yyss, yyssp); } YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN *++yyvsp = yylval; YY_IGNORE_MAYBE_UNINITIALIZED_END /* Shift the error token. */ YY_SYMBOL_PRINT ("Shifting", YY_ACCESSING_SYMBOL (yyn), yyvsp, yylsp); yystate = yyn; goto yynewstate; /*-------------------------------------. | yyacceptlab -- YYACCEPT comes here. | `-------------------------------------*/ yyacceptlab: yyresult = 0; goto yyreturnlab; /*-----------------------------------. | yyabortlab -- YYABORT comes here. | `-----------------------------------*/ yyabortlab: yyresult = 1; goto yyreturnlab; /*-----------------------------------------------------------. | yyexhaustedlab -- YYNOMEM (memory exhaustion) comes here. | `-----------------------------------------------------------*/ yyexhaustedlab: yyerror (YY_((char*)"memory exhausted")); yyresult = 2; goto yyreturnlab; /*----------------------------------------------------------. | yyreturnlab -- parsing is finished, clean up and return. | `----------------------------------------------------------*/ yyreturnlab: if (yychar != YYEMPTY) { /* Make sure we have latest lookahead translation. See comments at user semantic actions for why this is necessary. */ yytoken = YYTRANSLATE (yychar); yydestruct ("Cleanup: discarding lookahead", yytoken, &yylval); } /* Do not reclaim the symbols of the rule whose action triggered this YYABORT or YYACCEPT. */ YYPOPSTACK (yylen); YY_STACK_PRINT (yyss, yyssp); while (yyssp != yyss) { yydestruct ("Cleanup: popping", YY_ACCESSING_SYMBOL (+*yyssp), yyvsp); YYPOPSTACK (1); } #ifndef yyoverflow if (yyss != yyssa) YYSTACK_FREE (yyss); #endif return yyresult; } #line 4979 "VParseBison.y" int VParseGrammar::parse() { s_grammarp = this; return VParseBisonparse(); } void VParseGrammar::debug(int level) { VParseBisondebug = level; } const char* VParseGrammar::tokenName(int token) { #if YYDEBUG || YYERROR_VERBOSE if (token >= 255) { switch (token) { /*BISONPRE_TOKEN_NAMES*/ default: return yytname[token-255]; } } else { static char ch[2]; ch[0]=token; ch[1]='\0'; return ch; } #else return ""; #endif } //YACC = /kits/sources/bison-2.4.1/src/bison --report=lookahead // --report=lookahead // --report=itemset // --graph // // Local Variables: // compile-command: "cd .. ; make -j 8 && make test" // End: Verilog-Perl-3.482/Parser/gen/flex-10000644000177100017500000062467214553624373017075 0ustar wsnyderwsnyder#line 2 "VParseLex_pretmp.cpp" #line 4 "VParseLex_pretmp.cpp" #define YY_INT_ALIGNED long int /* A lexical scanner generated by flex */ /* %not-for-header */ /* %if-c-only */ /* %if-not-reentrant */ #define yy_create_buffer VParseLex_create_buffer #define yy_delete_buffer VParseLex_delete_buffer #define yy_scan_buffer VParseLex_scan_buffer #define yy_scan_string VParseLex_scan_string #define yy_scan_bytes VParseLex_scan_bytes #define yy_init_buffer VParseLex_init_buffer #define yy_flush_buffer VParseLex_flush_buffer #define yy_load_buffer_state VParseLex_load_buffer_state #define yy_switch_to_buffer VParseLex_switch_to_buffer #define yypush_buffer_state VParseLexpush_buffer_state #define yypop_buffer_state VParseLexpop_buffer_state #define yyensure_buffer_stack VParseLexensure_buffer_stack #define yy_flex_debug VParseLex_flex_debug #define yyin VParseLexin #define yyleng VParseLexleng #define yylex VParseLexlex #define yylineno VParseLexlineno #define yyout VParseLexout #define yyrestart VParseLexrestart #define yytext VParseLextext #define yywrap VParseLexwrap #define yyalloc VParseLexalloc #define yyrealloc VParseLexrealloc #define yyfree VParseLexfree /* %endif */ /* %endif */ /* %ok-for-header */ #define FLEX_SCANNER #define YY_FLEX_MAJOR_VERSION 2 #define YY_FLEX_MINOR_VERSION 6 #define YY_FLEX_SUBMINOR_VERSION 4 #if YY_FLEX_SUBMINOR_VERSION > 0 #define FLEX_BETA #endif /* %if-c++-only */ /* %endif */ /* %if-c-only */ #ifdef yy_create_buffer #define VParseLex_create_buffer_ALREADY_DEFINED #else #define yy_create_buffer VParseLex_create_buffer #endif #ifdef yy_delete_buffer #define VParseLex_delete_buffer_ALREADY_DEFINED #else #define yy_delete_buffer VParseLex_delete_buffer #endif #ifdef yy_scan_buffer #define VParseLex_scan_buffer_ALREADY_DEFINED #else #define yy_scan_buffer VParseLex_scan_buffer #endif #ifdef yy_scan_string #define VParseLex_scan_string_ALREADY_DEFINED #else #define yy_scan_string VParseLex_scan_string #endif #ifdef yy_scan_bytes #define VParseLex_scan_bytes_ALREADY_DEFINED #else #define yy_scan_bytes VParseLex_scan_bytes #endif #ifdef yy_init_buffer #define VParseLex_init_buffer_ALREADY_DEFINED #else #define yy_init_buffer VParseLex_init_buffer #endif #ifdef yy_flush_buffer #define VParseLex_flush_buffer_ALREADY_DEFINED #else #define yy_flush_buffer VParseLex_flush_buffer #endif #ifdef yy_load_buffer_state #define VParseLex_load_buffer_state_ALREADY_DEFINED #else #define yy_load_buffer_state VParseLex_load_buffer_state #endif #ifdef yy_switch_to_buffer #define VParseLex_switch_to_buffer_ALREADY_DEFINED #else #define yy_switch_to_buffer VParseLex_switch_to_buffer #endif #ifdef yypush_buffer_state #define VParseLexpush_buffer_state_ALREADY_DEFINED #else #define yypush_buffer_state VParseLexpush_buffer_state #endif #ifdef yypop_buffer_state #define VParseLexpop_buffer_state_ALREADY_DEFINED #else #define yypop_buffer_state VParseLexpop_buffer_state #endif #ifdef yyensure_buffer_stack #define VParseLexensure_buffer_stack_ALREADY_DEFINED #else #define yyensure_buffer_stack VParseLexensure_buffer_stack #endif #ifdef yylex #define VParseLexlex_ALREADY_DEFINED #else #define yylex VParseLexlex #endif #ifdef yyrestart #define VParseLexrestart_ALREADY_DEFINED #else #define yyrestart VParseLexrestart #endif #ifdef yylex_init #define VParseLexlex_init_ALREADY_DEFINED #else #define yylex_init VParseLexlex_init #endif #ifdef yylex_init_extra #define VParseLexlex_init_extra_ALREADY_DEFINED #else #define yylex_init_extra VParseLexlex_init_extra #endif #ifdef yylex_destroy #define VParseLexlex_destroy_ALREADY_DEFINED #else #define yylex_destroy VParseLexlex_destroy #endif #ifdef yyget_debug #define VParseLexget_debug_ALREADY_DEFINED #else #define yyget_debug VParseLexget_debug #endif #ifdef yyset_debug #define VParseLexset_debug_ALREADY_DEFINED #else #define yyset_debug VParseLexset_debug #endif #ifdef yyget_extra #define VParseLexget_extra_ALREADY_DEFINED #else #define yyget_extra VParseLexget_extra #endif #ifdef yyset_extra #define VParseLexset_extra_ALREADY_DEFINED #else #define yyset_extra VParseLexset_extra #endif #ifdef yyget_in #define VParseLexget_in_ALREADY_DEFINED #else #define yyget_in VParseLexget_in #endif #ifdef yyset_in #define VParseLexset_in_ALREADY_DEFINED #else #define yyset_in VParseLexset_in #endif #ifdef yyget_out #define VParseLexget_out_ALREADY_DEFINED #else #define yyget_out VParseLexget_out #endif #ifdef yyset_out #define VParseLexset_out_ALREADY_DEFINED #else #define yyset_out VParseLexset_out #endif #ifdef yyget_leng #define VParseLexget_leng_ALREADY_DEFINED #else #define yyget_leng VParseLexget_leng #endif #ifdef yyget_text #define VParseLexget_text_ALREADY_DEFINED #else #define yyget_text VParseLexget_text #endif #ifdef yyget_lineno #define VParseLexget_lineno_ALREADY_DEFINED #else #define yyget_lineno VParseLexget_lineno #endif #ifdef yyset_lineno #define VParseLexset_lineno_ALREADY_DEFINED #else #define yyset_lineno VParseLexset_lineno #endif #ifdef yywrap #define VParseLexwrap_ALREADY_DEFINED #else #define yywrap VParseLexwrap #endif /* %endif */ #ifdef yyalloc #define VParseLexalloc_ALREADY_DEFINED #else #define yyalloc VParseLexalloc #endif #ifdef yyrealloc #define VParseLexrealloc_ALREADY_DEFINED #else #define yyrealloc VParseLexrealloc #endif #ifdef yyfree #define VParseLexfree_ALREADY_DEFINED #else #define yyfree VParseLexfree #endif /* %if-c-only */ #ifdef yytext #define VParseLextext_ALREADY_DEFINED #else #define yytext VParseLextext #endif #ifdef yyleng #define VParseLexleng_ALREADY_DEFINED #else #define yyleng VParseLexleng #endif #ifdef yyin #define VParseLexin_ALREADY_DEFINED #else #define yyin VParseLexin #endif #ifdef yyout #define VParseLexout_ALREADY_DEFINED #else #define yyout VParseLexout #endif #ifdef yy_flex_debug #define VParseLex_flex_debug_ALREADY_DEFINED #else #define yy_flex_debug VParseLex_flex_debug #endif #ifdef yylineno #define VParseLexlineno_ALREADY_DEFINED #else #define yylineno VParseLexlineno #endif /* %endif */ /* First, we deal with platform-specific or compiler-specific issues. */ /* begin standard C headers. */ /* %if-c-only */ #include #include #include #include /* %endif */ /* %if-tables-serialization */ /* %endif */ /* end standard C headers. */ /* %if-c-or-c++ */ /* flex integer type definitions */ #ifndef FLEXINT_H #define FLEXINT_H /* C99 systems have . Non-C99 systems may or may not. */ #if defined (__STDC_VERSION__) && __STDC_VERSION__ >= 199901L /* C99 says to define __STDC_LIMIT_MACROS before including stdint.h, * if you want the limit (max/min) macros for int types. */ #ifndef __STDC_LIMIT_MACROS #define __STDC_LIMIT_MACROS 1 #endif #include typedef int8_t flex_int8_t; typedef uint8_t flex_uint8_t; typedef int16_t flex_int16_t; typedef uint16_t flex_uint16_t; typedef int32_t flex_int32_t; typedef uint32_t flex_uint32_t; #else typedef signed char flex_int8_t; typedef short int flex_int16_t; typedef int flex_int32_t; typedef unsigned char flex_uint8_t; typedef unsigned short int flex_uint16_t; typedef unsigned int flex_uint32_t; /* Limits of integral types. */ #ifndef INT8_MIN #define INT8_MIN (-128) #endif #ifndef INT16_MIN #define INT16_MIN (-32767-1) #endif #ifndef INT32_MIN #define INT32_MIN (-2147483647-1) #endif #ifndef INT8_MAX #define INT8_MAX (127) #endif #ifndef INT16_MAX #define INT16_MAX (32767) #endif #ifndef INT32_MAX #define INT32_MAX (2147483647) #endif #ifndef UINT8_MAX #define UINT8_MAX (255U) #endif #ifndef UINT16_MAX #define UINT16_MAX (65535U) #endif #ifndef UINT32_MAX #define UINT32_MAX (4294967295U) #endif #ifndef SIZE_MAX #define SIZE_MAX (~(size_t)0) #endif #endif /* ! C99 */ #endif /* ! FLEXINT_H */ /* %endif */ /* begin standard C++ headers. */ /* %if-c++-only */ /* %endif */ /* TODO: this is always defined, so inline it */ #define yyconst const #if defined(__GNUC__) && __GNUC__ >= 3 #define yynoreturn __attribute__((__noreturn__)) #else #define yynoreturn #endif /* %not-for-header */ /* Returned upon end-of-file. */ #define YY_NULL 0 /* %ok-for-header */ /* %not-for-header */ /* Promotes a possibly negative, possibly signed char to an * integer in range [0..255] for use as an array index. */ #define YY_SC_TO_UI(c) ((YY_CHAR) (c)) /* %ok-for-header */ /* %if-reentrant */ /* %endif */ /* %if-not-reentrant */ /* %endif */ /* Enter a start condition. This macro really ought to take a parameter, * but we do it the disgusting crufty way forced on us by the ()-less * definition of BEGIN. */ #define BEGIN (yy_start) = 1 + 2 * /* Translate the current start state into a value that can be later handed * to BEGIN to return to the state. The YYSTATE alias is for lex * compatibility. */ #define YY_START (((yy_start) - 1) / 2) #define YYSTATE YY_START /* Action number for EOF rule of a given start state. */ #define YY_STATE_EOF(state) (YY_END_OF_BUFFER + state + 1) /* Special action meaning "start processing a new file". */ #define YY_NEW_FILE yyrestart( yyin ) #define YY_END_OF_BUFFER_CHAR 0 /* Size of default input buffer. */ #ifndef YY_BUF_SIZE #ifdef __ia64__ /* On IA-64, the buffer size is 16k, not 8k. * Moreover, YY_BUF_SIZE is 2*YY_READ_BUF_SIZE in the general case. * Ditto for the __ia64__ case accordingly. */ #define YY_BUF_SIZE 32768 #else #define YY_BUF_SIZE 16384 #endif /* __ia64__ */ #endif /* The state buf must be large enough to hold one state per character in the main buffer. */ #define YY_STATE_BUF_SIZE ((YY_BUF_SIZE + 2) * sizeof(yy_state_type)) #ifndef YY_TYPEDEF_YY_BUFFER_STATE #define YY_TYPEDEF_YY_BUFFER_STATE typedef struct yy_buffer_state *YY_BUFFER_STATE; #endif #ifndef YY_TYPEDEF_YY_SIZE_T #define YY_TYPEDEF_YY_SIZE_T typedef size_t yy_size_t; #endif /* %if-not-reentrant */ extern int yyleng; /* %endif */ /* %if-c-only */ /* %if-not-reentrant */ extern FILE *yyin, *yyout; /* %endif */ /* %endif */ #define EOB_ACT_CONTINUE_SCAN 0 #define EOB_ACT_END_OF_FILE 1 #define EOB_ACT_LAST_MATCH 2 #define YY_LESS_LINENO(n) #define YY_LINENO_REWIND_TO(ptr) /* Return all but the first "n" matched characters back to the input stream. */ #define yyless(n) \ do \ { \ /* Undo effects of setting up yytext. */ \ int yyless_macro_arg = (n); \ YY_LESS_LINENO(yyless_macro_arg);\ *yy_cp = (yy_hold_char); \ YY_RESTORE_YY_MORE_OFFSET \ (yy_c_buf_p) = yy_cp = yy_bp + yyless_macro_arg - YY_MORE_ADJ; \ YY_DO_BEFORE_ACTION; /* set up yytext again */ \ } \ while ( 0 ) #define unput(c) yyunput( c, (yytext_ptr) ) #ifndef YY_STRUCT_YY_BUFFER_STATE #define YY_STRUCT_YY_BUFFER_STATE struct yy_buffer_state { /* %if-c-only */ FILE *yy_input_file; /* %endif */ /* %if-c++-only */ /* %endif */ char *yy_ch_buf; /* input buffer */ char *yy_buf_pos; /* current position in input buffer */ /* Size of input buffer in bytes, not including room for EOB * characters. */ int yy_buf_size; /* Number of characters read into yy_ch_buf, not including EOB * characters. */ int yy_n_chars; /* Whether we "own" the buffer - i.e., we know we created it, * and can realloc() it to grow it, and should free() it to * delete it. */ int yy_is_our_buffer; /* Whether this is an "interactive" input source; if so, and * if we're using stdio for input, then we want to use getc() * instead of fread(), to make sure we stop fetching input after * each newline. */ int yy_is_interactive; /* Whether we're considered to be at the beginning of a line. * If so, '^' rules will be active on the next match, otherwise * not. */ int yy_at_bol; int yy_bs_lineno; /**< The line count. */ int yy_bs_column; /**< The column count. */ /* Whether to try to fill the input buffer when we reach the * end of it. */ int yy_fill_buffer; int yy_buffer_status; #define YY_BUFFER_NEW 0 #define YY_BUFFER_NORMAL 1 /* When an EOF's been seen but there's still some text to process * then we mark the buffer as YY_EOF_PENDING, to indicate that we * shouldn't try reading from the input source any more. We might * still have a bunch of tokens to match, though, because of * possible backing-up. * * When we actually see the EOF, we change the status to "new" * (via yyrestart()), so that the user can continue scanning by * just pointing yyin at a new input file. */ #define YY_BUFFER_EOF_PENDING 2 }; #endif /* !YY_STRUCT_YY_BUFFER_STATE */ /* %if-c-only Standard (non-C++) definition */ /* %not-for-header */ /* %if-not-reentrant */ /* Stack of input buffers. */ static size_t yy_buffer_stack_top = 0; /**< index of top of stack. */ static size_t yy_buffer_stack_max = 0; /**< capacity of stack. */ static YY_BUFFER_STATE * yy_buffer_stack = NULL; /**< Stack as an array. */ /* %endif */ /* %ok-for-header */ /* %endif */ /* We provide macros for accessing buffer states in case in the * future we want to put the buffer states in a more general * "scanner state". * * Returns the top of the stack, or NULL. */ #define YY_CURRENT_BUFFER ( (yy_buffer_stack) \ ? (yy_buffer_stack)[(yy_buffer_stack_top)] \ : NULL) /* Same as previous macro, but useful when we know that the buffer stack is not * NULL or when we need an lvalue. For internal use only. */ #define YY_CURRENT_BUFFER_LVALUE (yy_buffer_stack)[(yy_buffer_stack_top)] /* %if-c-only Standard (non-C++) definition */ /* %if-not-reentrant */ /* %not-for-header */ /* yy_hold_char holds the character lost when yytext is formed. */ static char yy_hold_char; static int yy_n_chars; /* number of characters read into yy_ch_buf */ int yyleng; /* Points to current character in buffer. */ static char *yy_c_buf_p = NULL; static int yy_init = 0; /* whether we need to initialize */ static int yy_start = 0; /* start state number */ /* Flag which is used to allow yywrap()'s to do buffer switches * instead of setting up a fresh yyin. A bit of a hack ... */ static int yy_did_buffer_switch_on_eof; /* %ok-for-header */ /* %endif */ void yyrestart ( FILE *input_file ); void yy_switch_to_buffer ( YY_BUFFER_STATE new_buffer ); YY_BUFFER_STATE yy_create_buffer ( FILE *file, int size ); void yy_delete_buffer ( YY_BUFFER_STATE b ); void yy_flush_buffer ( YY_BUFFER_STATE b ); void yypush_buffer_state ( YY_BUFFER_STATE new_buffer ); void yypop_buffer_state ( void ); static void yyensure_buffer_stack ( void ); static void yy_load_buffer_state ( void ); static void yy_init_buffer ( YY_BUFFER_STATE b, FILE *file ); #define YY_FLUSH_BUFFER yy_flush_buffer( YY_CURRENT_BUFFER ) YY_BUFFER_STATE yy_scan_buffer ( char *base, yy_size_t size ); YY_BUFFER_STATE yy_scan_string ( const char *yy_str ); YY_BUFFER_STATE yy_scan_bytes ( const char *bytes, int len ); /* %endif */ void *yyalloc ( yy_size_t ); void *yyrealloc ( void *, yy_size_t ); void yyfree ( void * ); #define yy_new_buffer yy_create_buffer #define yy_set_interactive(is_interactive) \ { \ if ( ! YY_CURRENT_BUFFER ){ \ yyensure_buffer_stack (); \ YY_CURRENT_BUFFER_LVALUE = \ yy_create_buffer( yyin, YY_BUF_SIZE ); \ } \ YY_CURRENT_BUFFER_LVALUE->yy_is_interactive = is_interactive; \ } #define yy_set_bol(at_bol) \ { \ if ( ! YY_CURRENT_BUFFER ){\ yyensure_buffer_stack (); \ YY_CURRENT_BUFFER_LVALUE = \ yy_create_buffer( yyin, YY_BUF_SIZE ); \ } \ YY_CURRENT_BUFFER_LVALUE->yy_at_bol = at_bol; \ } #define YY_AT_BOL() (YY_CURRENT_BUFFER_LVALUE->yy_at_bol) /* %% [1.0] yytext/yyin/yyout/yy_state_type/yylineno etc. def's & init go here */ /* Begin user sect3 */ #define FLEX_DEBUG typedef flex_uint8_t YY_CHAR; FILE *yyin = NULL, *yyout = NULL; typedef int yy_state_type; extern int yylineno; int yylineno = 1; extern char *yytext; #ifdef yytext_ptr #undef yytext_ptr #endif #define yytext_ptr yytext /* %% [1.5] DFA */ /* %if-c-only Standard (non-C++) definition */ static yy_state_type yy_get_previous_state ( void ); static yy_state_type yy_try_NUL_trans ( yy_state_type current_state ); static int yy_get_next_buffer ( void ); static void yynoreturn yy_fatal_error ( const char* msg ); /* %endif */ /* Done after the current pattern has been matched and before the * corresponding action - sets up yytext. */ #define YY_DO_BEFORE_ACTION \ (yytext_ptr) = yy_bp; \ /* %% [2.0] code to fiddle yytext and yyleng for yymore() goes here \ */\ (yytext_ptr) -= (yy_more_len); \ yyleng = (int) (yy_cp - (yytext_ptr)); \ (yy_hold_char) = *yy_cp; \ *yy_cp = '\0'; \ /* %% [3.0] code to copy yytext_ptr to yytext[] goes here, if %array \ */\ (yy_c_buf_p) = yy_cp; /* %% [4.0] data tables for the DFA and the user's section 1 definitions go here */ #define YY_NUM_RULES 422 #define YY_END_OF_BUFFER 423 /* This struct is not used in this scanner, but its presence is necessary. */ struct yy_trans_info { flex_int32_t yy_verify; flex_int32_t yy_nxt; }; static const flex_int32_t yy_accept[2079] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 423, 1, 420, 2, 3, 2, 261, 345, 262, 263, 264, 265, 420, 266, 267, 268, 269, 270, 271, 272, 273, 347, 274, 275, 276, 277, 278, 279, 280, 343, 281, 420, 282, 283, 420, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 259, 284, 260, 285, 268, 269, 271, 272, 276, 278, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 261, 262, 263, 264, 265, 310, 268, 269, 271, 273, 274, 276, 277, 278, 280, 281, 283, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 284, 276, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 356, 351, 356, 354, 355, 356, 371, 368, 371, 371, 370, 361, 358, 357, 360, 366, 362, 366, 366, 366, 421, 2, 3, 2, 293, 0, 344, 258, 286, 346, 346, 0, 0, 302, 300, 419, 418, 0, 0, 0, 347, 0, 347, 0, 0, 0, 0, 350, 0, 290, 288, 292, 301, 289, 291, 343, 342, 296, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 32, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 44, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 287, 298, 297, 299, 306, 307, 308, 309, 290, 291, 343, 343, 343, 343, 343, 343, 32, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 293, 329, 258, 258, 258, 258, 258, 258, 320, 321, 311, 318, 314, 316, 315, 317, 300, 319, 0, 331, 332, 290, 292, 291, 330, 0, 336, 0, 0, 337, 323, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 159, 343, 343, 343, 343, 32, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 0, 322, 0, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 351, 0, 355, 353, 352, 353, 368, 0, 369, 370, 357, 357, 359, 360, 0, 367, 0, 0, 295, 258, 303, 346, 346, 0, 0, 0, 372, 0, 418, 418, 418, 0, 0, 346, 346, 346, 346, 348, 0, 349, 350, 0, 294, 341, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 343, 5, 343, 343, 8, 343, 343, 343, 343, 343, 343, 343, 18, 343, 27, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 42, 43, 343, 343, 343, 343, 343, 343, 343, 343, 51, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 62, 343, 343, 343, 343, 343, 343, 73, 343, 75, 304, 305, 343, 343, 343, 343, 18, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 126, 343, 313, 258, 258, 258, 258, 258, 258, 328, 333, 304, 324, 312, 325, 305, 0, 339, 338, 343, 343, 343, 343, 343, 144, 343, 343, 343, 343, 343, 343, 343, 343, 343, 18, 343, 343, 343, 343, 343, 27, 177, 343, 343, 343, 343, 182, 343, 343, 343, 343, 343, 343, 192, 343, 343, 343, 343, 343, 343, 205, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 224, 343, 343, 343, 343, 343, 334, 335, 340, 343, 343, 18, 343, 343, 343, 237, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 182, 343, 343, 0, 0, 0, 0, 0, 372, 372, 418, 346, 346, 346, 346, 346, 0, 0, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 343, 343, 343, 343, 9, 78, 343, 343, 343, 343, 16, 17, 343, 343, 343, 343, 343, 343, 343, 343, 343, 30, 343, 343, 343, 343, 343, 343, 37, 343, 343, 343, 343, 40, 343, 83, 343, 343, 343, 86, 343, 343, 343, 343, 49, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 60, 61, 100, 63, 64, 343, 343, 343, 343, 69, 70, 343, 343, 72, 74, 343, 117, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 258, 258, 258, 258, 258, 258, 326, 327, 343, 343, 343, 343, 343, 141, 142, 343, 146, 343, 343, 343, 343, 343, 343, 343, 158, 343, 343, 343, 343, 343, 168, 343, 343, 343, 343, 343, 343, 30, 343, 343, 343, 343, 343, 37, 343, 343, 343, 343, 343, 193, 343, 343, 343, 343, 343, 200, 201, 343, 343, 343, 343, 343, 343, 343, 343, 343, 216, 343, 61, 220, 343, 343, 343, 226, 69, 343, 229, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 253, 343, 343, 343, 257, 0, 0, 0, 418, 0, 348, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 343, 343, 7, 343, 10, 11, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 26, 28, 343, 343, 343, 343, 34, 35, 343, 81, 343, 343, 343, 343, 343, 343, 343, 343, 343, 87, 88, 343, 343, 91, 343, 343, 343, 92, 93, 94, 343, 97, 343, 343, 343, 343, 59, 343, 343, 66, 343, 343, 103, 104, 71, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 127, 258, 258, 130, 131, 132, 258, 134, 343, 343, 343, 343, 343, 145, 343, 148, 343, 150, 343, 343, 154, 157, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 173, 343, 343, 343, 343, 343, 343, 343, 343, 343, 187, 188, 343, 343, 343, 343, 343, 343, 343, 343, 343, 202, 343, 343, 343, 343, 210, 343, 343, 343, 214, 343, 343, 343, 343, 343, 222, 343, 343, 343, 343, 343, 343, 343, 343, 26, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 250, 343, 343, 343, 343, 0, 0, 0, 418, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 0, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 4, 6, 76, 77, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 79, 80, 343, 343, 343, 82, 39, 343, 84, 85, 45, 343, 343, 343, 343, 90, 343, 343, 53, 343, 343, 343, 343, 343, 343, 343, 65, 67, 343, 343, 118, 119, 343, 343, 343, 108, 109, 121, 343, 343, 343, 343, 343, 343, 343, 343, 115, 343, 128, 129, 258, 4, 138, 139, 140, 143, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 169, 170, 343, 172, 343, 343, 343, 343, 343, 180, 181, 343, 343, 343, 343, 343, 343, 343, 343, 195, 343, 343, 343, 343, 343, 343, 206, 343, 343, 343, 211, 212, 213, 215, 343, 343, 343, 343, 223, 343, 343, 343, 230, 343, 343, 343, 343, 235, 343, 343, 343, 343, 343, 343, 343, 343, 246, 343, 343, 223, 343, 343, 343, 343, 343, 0, 0, 0, 418, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 388, 0, 0, 389, 0, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 343, 13, 343, 15, 19, 343, 343, 343, 343, 343, 25, 29, 343, 33, 36, 343, 41, 343, 47, 343, 343, 343, 52, 343, 343, 55, 343, 98, 99, 57, 58, 101, 102, 343, 343, 343, 343, 343, 122, 343, 124, 125, 343, 343, 343, 343, 343, 258, 343, 147, 343, 343, 152, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 171, 343, 175, 343, 343, 343, 343, 343, 343, 343, 189, 190, 191, 194, 343, 197, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 221, 225, 343, 343, 343, 232, 343, 343, 236, 343, 343, 343, 343, 343, 343, 244, 343, 343, 249, 343, 252, 343, 343, 256, 0, 0, 0, 418, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 0, 416, 416, 416, 416, 416, 416, 398, 399, 416, 416, 416, 416, 12, 14, 343, 343, 343, 343, 24, 31, 343, 343, 343, 89, 50, 95, 96, 54, 343, 68, 343, 343, 343, 107, 123, 343, 343, 343, 343, 116, 133, 343, 343, 343, 149, 343, 153, 343, 343, 160, 343, 162, 343, 343, 343, 343, 343, 343, 176, 343, 343, 343, 343, 185, 343, 196, 198, 343, 203, 343, 207, 208, 343, 343, 343, 219, 343, 228, 343, 343, 343, 238, 343, 240, 241, 343, 343, 343, 343, 343, 343, 343, 343, 0, 0, 0, 418, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 398, 398, 398, 416, 416, 416, 403, 416, 416, 343, 21, 343, 343, 343, 46, 48, 56, 105, 120, 343, 343, 343, 343, 343, 343, 136, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 343, 183, 184, 186, 199, 343, 209, 343, 343, 343, 231, 343, 343, 239, 343, 343, 343, 343, 343, 343, 343, 343, 0, 0, 0, 418, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 398, 400, 416, 416, 416, 416, 343, 343, 23, 343, 343, 110, 343, 343, 343, 343, 343, 151, 155, 156, 343, 343, 164, 165, 343, 343, 343, 343, 343, 343, 217, 343, 227, 233, 234, 343, 243, 343, 343, 343, 251, 254, 343, 0, 0, 0, 418, 373, 416, 416, 375, 416, 416, 416, 416, 416, 416, 416, 416, 386, 416, 416, 416, 416, 416, 416, 416, 396, 398, 416, 416, 416, 405, 20, 343, 38, 106, 343, 343, 343, 135, 343, 161, 343, 166, 167, 174, 178, 343, 343, 343, 343, 343, 343, 343, 343, 0, 0, 0, 418, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 398, 416, 416, 416, 405, 405, 22, 343, 343, 343, 137, 163, 179, 204, 343, 242, 245, 343, 343, 255, 0, 0, 0, 418, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 415, 416, 416, 390, 416, 416, 416, 416, 416, 398, 416, 416, 416, 343, 343, 114, 218, 343, 343, 0, 363, 0, 418, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 385, 416, 416, 416, 416, 416, 416, 398, 416, 416, 416, 343, 343, 343, 247, 248, 0, 0, 418, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 398, 416, 416, 416, 111, 343, 343, 0, 0, 418, 416, 0, 0, 416, 416, 416, 416, 380, 381, 382, 416, 416, 416, 416, 416, 416, 416, 416, 398, 0, 416, 402, 404, 343, 343, 0, 0, 418, 416, 0, 416, 377, 416, 416, 416, 416, 416, 416, 416, 416, 416, 416, 398, 0, 401, 343, 343, 0, 0, 418, 416, 0, 0, 416, 377, 416, 416, 416, 384, 387, 416, 416, 393, 394, 416, 398, 0, 343, 113, 0, 0, 418, 416, 0, 0, 416, 416, 416, 383, 416, 392, 416, 398, 0, 112, 0, 0, 418, 416, 0, 0, 376, 416, 416, 391, 395, 398, 0, 0, 0, 418, 416, 0, 0, 376, 376, 416, 416, 398, 0, 0, 0, 418, 374, 0, 0, 0, 416, 416, 398, 0, 0, 0, 418, 0, 0, 0, 416, 379, 398, 0, 0, 0, 418, 0, 0, 0, 0, 0, 416, 398, 0, 0, 0, 418, 0, 0, 0, 0, 0, 0, 0, 0, 378, 398, 0, 0, 0, 418, 406, 407, 0, 409, 410, 411, 412, 413, 414, 378, 378, 398, 0, 0, 0, 418, 0, 398, 0, 0, 0, 418, 0, 398, 0, 0, 0, 418, 0, 398, 0, 0, 364, 418, 0, 398, 0, 365, 418, 0, 397, 397, 417, 0, 0, 0, 408, 0 } ; static const YY_CHAR yy_ec[256] = { 0, 1, 1, 1, 1, 1, 1, 1, 1, 2, 3, 1, 4, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 40, 40, 41, 39, 42, 43, 42, 42, 42, 42, 42, 42, 43, 42, 42, 42, 44, 42, 42, 42, 42, 45, 42, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 } ; static const YY_CHAR yy_meta[82] = { 0, 1, 2, 3, 4, 4, 2, 1, 1, 1, 5, 1, 1, 1, 1, 1, 6, 7, 1, 7, 1, 6, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 9, 1, 10, 10, 10, 11, 11, 11, 10, 1, 12, 1, 1, 13, 1, 10, 10, 10, 10, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 10, 11, 10, 1, 1, 1, 1 } ; static const flex_int32_t yy_base[2108] = { 0, 0, 0, 0, 0, 66, 0, 3247, 3246, 132, 0, 156, 175, 198, 217, 240, 259, 282, 301, 375, 0, 456, 0, 537, 0, 618, 0, 0, 0, 3317, 3320, 3320, 85, 3320, 90, 3281, 3307, 3320, 0, 3320, 3302, 678, 3297, 3320, 3276, 3320, 3320, 3275, 3320, 82, 754, 3320, 3320, 70, 71, 73, 3320, 3320, 0, 3320, 0, 3320, 3229, 736, 47, 41, 47, 28, 92, 53, 3249, 58, 3242, 3255, 94, 107, 58, 110, 648, 170, 131, 3250, 651, 69, 3320, 3226, 3320, 128, 116, 3272, 122, 3287, 183, 187, 183, 294, 138, 651, 3246, 104, 224, 674, 254, 675, 110, 192, 3266, 3291, 694, 3264, 102, 3220, 243, 726, 781, 267, 309, 230, 272, 313, 3259, 823, 204, 302, 774, 785, 709, 790, 742, 803, 3230, 804, 693, 817, 810, 832, 842, 835, 842, 863, 865, 693, 752, 872, 882, 855, 157, 892, 887, 902, 908, 744, 862, 911, 923, 926, 781, 3320, 3320, 292, 3320, 0, 296, 3320, 3320, 322, 3280, 0, 3320, 3320, 316, 0, 3320, 3320, 3273, 0, 653, 3320, 989, 3320, 997, 3258, 3284, 3320, 0, 3279, 3320, 830, 974, 1003, 3320, 3320, 3320, 1016, 1010, 1082, 1030, 0, 708, 1068, 3220, 3219, 3218, 3217, 3215, 3215, 3320, 3320, 3249, 3320, 3320, 3320, 0, 3277, 3320, 0, 267, 3226, 3225, 737, 687, 3215, 3219, 3212, 639, 3221, 3204, 3215, 3200, 3218, 3202, 3213, 3213, 3199, 3202, 311, 3197, 3208, 3195, 3209, 3207, 3193, 3196, 3202, 0, 944, 3199, 3189, 3203, 3201, 3200, 3189, 3195, 3186, 806, 0, 3180, 3181, 3183, 3178, 3187, 3183, 3181, 972, 3180, 3179, 3173, 3189, 3188, 3183, 3169, 3170, 190, 3172, 820, 3181, 676, 3182, 3173, 3163, 3162, 3164, 3160, 3320, 3320, 3320, 3320, 3320, 3320, 3320, 3320, 3194, 3191, 3155, 3162, 3159, 974, 3168, 3157, 3156, 1008, 3167, 3165, 821, 3155, 3151, 3158, 3145, 3158, 3153, 924, 3320, 3143, 3159, 3145, 3143, 3143, 3155, 3320, 3320, 3320, 3320, 3320, 3320, 3320, 3320, 3170, 3320, 0, 3320, 3320, 788, 948, 1001, 3320, 1112, 3320, 1041, 3169, 3320, 3320, 738, 3134, 984, 699, 3147, 3131, 3149, 819, 911, 3134, 3129, 0, 850, 898, 969, 3129, 1006, 3132, 3133, 3128, 1095, 3134, 1011, 918, 3138, 98, 3129, 47, 1004, 1003, 3126, 1093, 3122, 3123, 3125, 1034, 3120, 1100, 1013, 3122, 3118, 1007, 3115, 3114, 3122, 1055, 1100, 3145, 3144, 3143, 3124, 1088, 1112, 3121, 3110, 3108, 3103, 1114, 1116, 1126, 1123, 3108, 1125, 3120, 3104, 1139, 1142, 1067, 3320, 1097, 0, 3320, 3320, 1198, 3320, 1199, 3320, 0, 1160, 1191, 3320, 0, 1216, 0, 3105, 3100, 3320, 0, 3320, 1140, 1221, 1226, 1231, 1237, 0, 0, 0, 1242, 3099, 1209, 1227, 1248, 1253, 1255, 299, 1288, 1276, 1339, 3320, 3111, 3320, 3320, 3112, 3094, 3106, 3100, 1151, 3092, 783, 3094, 3097, 3094, 1220, 3089, 1035, 1155, 3090, 3092, 3103, 0, 3094, 3093, 3092, 3095, 3080, 3079, 826, 3096, 3091, 3090, 1266, 3080, 1278, 3090, 3084, 3071, 3069, 3068, 3083, 3073, 3079, 3067, 3075, 3062, 3078, 3076, 3061, 0, 3070, 3062, 3076, 3057, 3070, 3061, 3061, 3057, 3059, 0, 3065, 3064, 3053, 3052, 3065, 3053, 3052, 3060, 3047, 3045, 3048, 3048, 3053, 3043, 1273, 3036, 3035, 3050, 3042, 3040, 3046, 0, 3032, 0, 3320, 3320, 3034, 3036, 3041, 3037, 1317, 1124, 3030, 1211, 3024, 1222, 3042, 3034, 870, 3018, 3026, 3030, 0, 3020, 3320, 3019, 3016, 3029, 3019, 3024, 3014, 3320, 3320, 3047, 3320, 3320, 3320, 3046, 1344, 3320, 3320, 3028, 3027, 1271, 3012, 1156, 0, 3025, 3020, 3010, 3004, 3019, 1251, 3016, 3001, 1217, 1336, 3006, 1221, 3013, 3016, 2997, 1323, 0, 3000, 3009, 2998, 1264, 3007, 2997, 3009, 3000, 3001, 3004, 1193, 0, 2994, 2994, 1290, 1315, 2999, 2999, 0, 2981, 2980, 1309, 2978, 2979, 1338, 1324, 2991, 2978, 2981, 2990, 2989, 1291, 0, 2973, 2988, 2971, 2986, 2981, 3320, 3320, 3320, 2983, 2984, 1351, 2972, 2983, 1336, 0, 2964, 2978, 2962, 2969, 2958, 2974, 2964, 1353, 2974, 1329, 972, 2965, 1351, 2970, 2954, 2953, 1421, 1425, 2954, 2967, 2969, 0, 0, 2968, 0, 0, 1368, 1430, 1437, 1418, 2952, 2962, 2951, 2956, 2952, 2962, 2961, 2960, 2958, 1391, 2958, 2949, 2952, 2953, 2931, 2949, 2932, 2938, 2931, 2943, 2929, 2933, 2942, 2930, 2940, 2919, 2936, 2928, 2935, 1367, 0, 2921, 2918, 2937, 2935, 0, 0, 2935, 2914, 2919, 2915, 2916, 2930, 2910, 2924, 2906, 0, 2907, 2900, 2916, 2904, 2903, 2915, 0, 2916, 2905, 2898, 2906, 0, 2913, 0, 2910, 2894, 2901, 0, 2909, 2903, 1424, 2892, 2890, 2908, 2907, 2888, 2887, 2891, 2903, 2891, 1178, 2888, 2889, 2895, 0, 0, 2890, 0, 0, 2884, 2879, 2891, 2880, 0, 0, 1426, 2889, 0, 0, 2880, 0, 2883, 2884, 1368, 2885, 2871, 2887, 2873, 2877, 2864, 2883, 2874, 2881, 2869, 2855, 2852, 2849, 2845, 2842, 2843, 2831, 2833, 2806, 2784, 2783, 2788, 3320, 3320, 2782, 2772, 2778, 2779, 2773, 0, 2775, 2778, 0, 2773, 2757, 2764, 2752, 1134, 2751, 2748, 0, 1398, 1272, 2752, 1399, 1396, 0, 2754, 2732, 1282, 2737, 2728, 163, 2737, 2716, 2720, 2708, 2721, 1396, 2725, 2711, 2715, 2708, 2705, 2697, 0, 1320, 2693, 2692, 2701, 2698, 0, 1399, 2683, 2695, 2677, 2689, 2682, 2674, 2673, 2654, 2664, 0, 2632, 1356, 2646, 2633, 2623, 2612, 0, 2633, 2628, 2619, 2609, 2612, 1407, 2602, 2618, 2607, 2595, 2611, 2595, 2587, 2566, 2546, 2548, 2553, 2567, 2544, 2551, 2546, 1433, 1411, 1414, 2536, 0, 2559, 2543, 2551, 2550, 1475, 1485, 2544, 2550, 2540, 2549, 2531, 2526, 2548, 2536, 2536, 2541, 2527, 2530, 2528, 1472, 2537, 2523, 2525, 2521, 2533, 2532, 2521, 2528, 2510, 2511, 2512, 2510, 2509, 2513, 0, 1458, 0, 0, 68, 218, 235, 299, 703, 744, 804, 840, 896, 1464, 0, 0, 969, 1073, 1462, 1102, 0, 0, 1159, 0, 1230, 1337, 1360, 1399, 1464, 1389, 1406, 1417, 1411, 0, 0, 1422, 1422, 0, 1430, 1421, 1422, 0, 0, 1434, 1426, 0, 1461, 1467, 1462, 1445, 0, 1465, 1468, 0, 1466, 1457, 0, 0, 0, 1475, 1470, 1464, 1465, 1466, 1480, 1464, 1480, 1468, 1483, 1474, 1470, 1472, 1475, 1469, 1474, 1493, 1491, 1482, 0, 1479, 1486, 0, 0, 0, 1490, 0, 1481, 1481, 1497, 1498, 1498, 0, 1493, 0, 1497, 1489, 1484, 1495, 1503, 0, 1510, 1497, 1493, 1511, 1506, 1499, 1497, 1498, 1516, 1508, 0, 1524, 1521, 1511, 1522, 1527, 1509, 1525, 1525, 1531, 1517, 0, 1520, 1530, 1518, 1530, 1534, 1530, 1539, 1523, 1539, 1542, 1541, 1533, 1534, 1540, 0, 1547, 1544, 1532, 0, 1549, 1547, 1537, 1542, 1552, 0, 1554, 1559, 1546, 1561, 1549, 1544, 1560, 1561, 1546, 1556, 1564, 1561, 1551, 1563, 1572, 1560, 1555, 1567, 1570, 1577, 1574, 1581, 1576, 1569, 1580, 1568, 1578, 1569, 1575, 1576, 1585, 1567, 1593, 1588, 1582, 1597, 1585, 1593, 1595, 1589, 1587, 1599, 1599, 1654, 1605, 1610, 1597, 1597, 1599, 1600, 1615, 1614, 1613, 1618, 1615, 1618, 0, 0, 0, 0, 1615, 1603, 1623, 1620, 1621, 1624, 1607, 1616, 1627, 1619, 1621, 1615, 1619, 0, 0, 1623, 1618, 1622, 0, 0, 1633, 0, 0, 0, 1619, 1635, 1632, 1619, 0, 1630, 1639, 0, 1639, 1641, 1622, 1630, 1678, 1680, 1682, 0, 0, 1650, 1636, 0, 0, 1651, 1653, 1639, 0, 0, 0, 1655, 1658, 1642, 1638, 1663, 1662, 1646, 1653, 0, 1663, 0, 0, 1655, 1671, 0, 0, 0, 0, 1666, 1658, 1672, 1654, 1654, 1658, 1662, 1659, 1676, 1659, 1676, 1671, 1676, 1663, 0, 0, 1666, 0, 1673, 1679, 1679, 1690, 1678, 0, 0, 1690, 1688, 1680, 1680, 1676, 1678, 1678, 1694, 0, 1680, 1688, 1682, 1683, 1685, 1688, 0, 1703, 1693, 1703, 0, 0, 0, 0, 1701, 1705, 1702, 1706, 0, 1701, 1696, 1697, 0, 1717, 1699, 1715, 1718, 0, 1701, 1708, 1723, 1720, 1699, 1705, 1706, 1715, 1757, 1727, 1726, 1761, 1710, 1730, 1730, 1721, 1732, 1725, 1724, 1739, 1740, 1724, 1727, 1733, 1739, 1726, 1734, 1743, 1750, 1725, 1739, 1732, 1754, 0, 1802, 1806, 3320, 1811, 1743, 1753, 1746, 1751, 1756, 1766, 1821, 1753, 1778, 1766, 1760, 1779, 1767, 0, 1769, 0, 0, 1763, 1772, 1776, 1777, 1782, 0, 0, 1774, 0, 0, 1785, 0, 1785, 0, 1769, 1778, 1788, 0, 1823, 1792, 0, 1796, 0, 0, 0, 0, 0, 0, 1794, 1790, 1791, 1783, 1797, 0, 1798, 0, 0, 1786, 1804, 1781, 1804, 1804, 1802, 1807, 0, 1804, 1803, 0, 1809, 1800, 1807, 1798, 1807, 1804, 1803, 1821, 1805, 1819, 1820, 0, 1825, 0, 1813, 1826, 1830, 1827, 1828, 1807, 1819, 0, 0, 0, 0, 1809, 0, 1810, 1831, 1832, 1817, 1834, 1820, 1840, 1827, 1840, 1824, 0, 0, 1841, 1842, 1832, 0, 1837, 1837, 0, 1845, 1836, 1832, 1834, 1833, 1846, 1857, 1854, 1848, 0, 1850, 0, 1846, 1847, 0, 1861, 1843, 1913, 1918, 1864, 1869, 1869, 1866, 1877, 1862, 1879, 1863, 1857, 1877, 1877, 1861, 1932, 1880, 1883, 1883, 1884, 1876, 1873, 1941, 1888, 1890, 1886, 1880, 1888, 0, 0, 1892, 1897, 1883, 1899, 0, 0, 1885, 1889, 1903, 0, 0, 0, 0, 0, 1896, 0, 1907, 1904, 1911, 0, 0, 1912, 1900, 1903, 1911, 0, 0, 1902, 1912, 1918, 0, 1906, 0, 1900, 1908, 0, 1914, 0, 1918, 1918, 1925, 1909, 1914, 1909, 0, 1921, 1929, 1927, 1913, 0, 1929, 0, 0, 1931, 0, 1931, 0, 0, 1925, 1917, 1930, 0, 1935, 0, 1927, 1937, 1931, 0, 1930, 0, 0, 1944, 1933, 1924, 1943, 1944, 1930, 1931, 1938, 2005, 1948, 2010, 2015, 1934, 1941, 1937, 1953, 1967, 1968, 1957, 1959, 1960, 1971, 1974, 1973, 1961, 1981, 1983, 1964, 1979, 1982, 2032, 2037, 2039, 1985, 1993, 1990, 0, 1997, 1992, 1983, 0, 1990, 1975, 1989, 0, 0, 0, 0, 0, 1982, 1990, 2001, 2000, 1994, 1994, 0, 1988, 1989, 1994, 1991, 1998, 2012, 2009, 2002, 1996, 2014, 2015, 2005, 2011, 0, 0, 0, 0, 2007, 0, 2002, 2004, 2006, 0, 2007, 2002, 0, 2016, 2024, 2021, 2016, 2030, 2026, 2016, 2031, 2086, 2035, 2024, 2025, 2039, 2041, 2023, 2042, 2043, 2044, 2032, 2046, 2037, 2036, 2037, 2050, 2038, 2056, 2059, 2039, 2055, 2044, 2061, 2060, 2112, 0, 2047, 2048, 2064, 2120, 2058, 2054, 0, 2072, 2073, 0, 2074, 2081, 2069, 2080, 2080, 0, 0, 0, 2077, 2082, 0, 0, 2061, 2082, 2080, 2070, 2076, 2088, 0, 2083, 0, 0, 0, 2081, 0, 2074, 2075, 2076, 0, 0, 2094, 2080, 2079, 2085, 2086, 0, 2104, 2089, 0, 2102, 2086, 2098, 2109, 2091, 2090, 2107, 2103, 0, 2093, 2094, 2110, 2115, 2112, 2119, 2099, 0, 2166, 2116, 2108, 2122, 2175, 0, 2119, 0, 0, 2113, 2116, 2127, 0, 2125, 0, 2129, 0, 0, 0, 0, 2116, 2131, 2122, 2113, 2131, 2141, 2142, 2122, 2128, 2139, 2125, 2126, 2125, 2130, 2148, 2130, 2133, 2148, 2133, 2148, 2136, 2142, 2142, 2153, 2156, 2140, 2141, 2156, 2158, 2211, 2152, 2166, 2147, 2216, 2222, 0, 2159, 2158, 2174, 0, 0, 0, 0, 2165, 0, 0, 2165, 2166, 0, 2162, 2179, 2179, 2180, 2182, 2184, 2164, 2165, 2186, 2183, 2192, 2180, 2190, 2190, 2196, 0, 2193, 2181, 0, 2180, 2196, 2188, 2202, 2200, 2251, 2205, 2194, 2196, 2204, 2206, 0, 0, 2198, 2199, 2209, 3320, 2212, 2214, 2215, 2200, 2221, 2205, 2215, 2204, 2204, 2216, 2208, 2226, 2207, 0, 2215, 2215, 2217, 2231, 2212, 2235, 2281, 2223, 2232, 2218, 2235, 2235, 2219, 0, 0, 2239, 2223, 2224, 2225, 2295, 2227, 2243, 2250, 2231, 2245, 2235, 2241, 2236, 2246, 2254, 2242, 2260, 2249, 2251, 2260, 2314, 2261, 2251, 2252, 0, 2252, 2268, 2254, 2324, 2329, 2261, 2330, 2314, 2279, 2338, 2271, 2276, 0, 0, 0, 2283, 2276, 2277, 2284, 2286, 2295, 2282, 2285, 2353, 2358, 2286, 0, 0, 2305, 2300, 2364, 2369, 2374, 2298, 2347, 2317, 2380, 2312, 2327, 2317, 2319, 2320, 2335, 2336, 2323, 2324, 2335, 2391, 2341, 0, 2344, 2328, 2398, 2336, 2349, 2342, 2380, 2387, 2354, 2410, 2344, 2364, 2348, 0, 0, 2348, 2350, 0, 0, 2348, 2417, 2365, 2353, 0, 2361, 2373, 2371, 2374, 2405, 2410, 2431, 2378, 2366, 0, 2369, 0, 2384, 2436, 2382, 0, 2388, 2394, 2385, 2375, 2429, 2430, 2451, 2385, 2380, 0, 0, 2447, 2393, 2409, 2393, 2396, 2392, 2440, 2441, 2461, 2465, 2410, 2416, 2468, 2424, 2409, 2408, 2428, 0, 2448, 2458, 2459, 2411, 2428, 2479, 2418, 2417, 2421, 2421, 2458, 2468, 2469, 2435, 0, 2490, 2428, 2432, 2428, 2431, 2474, 2479, 2476, 2480, 2480, 2509, 2503, 2444, 2445, 2461, 2453, 2512, 2513, 2514, 2515, 2516, 2517, 2518, 2519, 2529, 2523, 2458, 2474, 2482, 2466, 3320, 3320, 2473, 3320, 3320, 3320, 3320, 3320, 3320, 2534, 2538, 2536, 2489, 2493, 2477, 2493, 2484, 2546, 2498, 2482, 2498, 2501, 2502, 2552, 2487, 2504, 2506, 2491, 2497, 2559, 2509, 2511, 3320, 2511, 2503, 2565, 2516, 3320, 2517, 2516, 2569, 3320, 0, 2515, 2518, 2569, 3320, 3320, 2623, 2636, 2649, 2658, 2667, 2680, 2686, 2692, 2705, 2711, 2724, 2730, 2736, 2745, 2757, 2769, 2782, 2789, 2802, 2811, 2824, 2836, 2843, 2856, 2869, 2882, 2894, 2905, 2918 } ; static const flex_int32_t yy_def[2108] = { 0, 2079, 2079, 2078, 3, 3, 5, 5, 5, 5, 9, 9, 9, 9, 9, 9, 9, 9, 9, 2078, 19, 2078, 21, 2078, 23, 2078, 25, 2080, 2080, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2081, 2078, 2082, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2083, 2078, 2084, 2078, 2078, 2085, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2078, 2078, 2082, 2078, 2078, 41, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2078, 2078, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 136, 2083, 2083, 2083, 2083, 136, 2078, 2078, 2078, 2078, 2086, 2087, 2078, 2078, 2078, 2078, 2088, 2078, 2078, 2089, 2090, 2078, 2078, 2078, 2091, 2078, 2078, 2078, 2078, 2078, 2078, 2081, 2078, 2092, 2078, 2078, 2093, 2078, 2094, 2078, 2078, 2078, 2095, 2078, 2078, 2078, 50, 2096, 50, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2083, 2084, 2078, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2078, 2078, 2092, 2092, 2092, 2092, 2092, 2092, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2097, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2078, 2078, 2078, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2078, 2078, 2086, 2078, 2078, 2078, 2078, 2078, 2078, 2088, 2089, 2089, 2078, 2090, 2078, 2091, 2078, 2078, 2078, 2092, 2078, 2093, 2093, 2094, 2094, 2094, 2098, 2099, 2095, 2095, 2095, 195, 195, 441, 2100, 2100, 195, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2078, 2078, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2078, 2092, 2092, 2092, 2092, 2092, 2092, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2078, 2078, 2078, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2078, 2078, 2078, 2078, 2078, 2098, 2099, 2095, 441, 441, 440, 2100, 2100, 2101, 2078, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2092, 2092, 2092, 2092, 2092, 2092, 2078, 2078, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2078, 2078, 2078, 2095, 2078, 2078, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2092, 2092, 2092, 2092, 2092, 2092, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2078, 2078, 2078, 2095, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2102, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2092, 2092, 2092, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2078, 2078, 2078, 2095, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2102, 2102, 2078, 2102, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2092, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2078, 2078, 2078, 2095, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2078, 2085, 2085, 2085, 2085, 2085, 2085, 2103, 2085, 2085, 2085, 2085, 2085, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2092, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2078, 2078, 2078, 2095, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2103, 2103, 2103, 2085, 2085, 2085, 2085, 2085, 2085, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2078, 2078, 2078, 2095, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2103, 2085, 2085, 2085, 2085, 2085, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2078, 2078, 2078, 2095, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2103, 2085, 2085, 2085, 2104, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2078, 2078, 2078, 2095, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2103, 2085, 2085, 2085, 2104, 2104, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2083, 2078, 2078, 2078, 2095, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2103, 2085, 2085, 2085, 2083, 2083, 2083, 2083, 2083, 2083, 2078, 2078, 2078, 2095, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2103, 2085, 2085, 2085, 2083, 2083, 2083, 2083, 2083, 2078, 2078, 2095, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2103, 2085, 2085, 2085, 2083, 2083, 2083, 2078, 2078, 2095, 2085, 2078, 2078, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2103, 2078, 2085, 2085, 2085, 2083, 2083, 2078, 2078, 2095, 2085, 2078, 2085, 2105, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2103, 2078, 2085, 2083, 2083, 2078, 2078, 2095, 2085, 2078, 2078, 2085, 2105, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2103, 2078, 2083, 2083, 2078, 2078, 2095, 2085, 2078, 2078, 2085, 2085, 2085, 2085, 2085, 2085, 2085, 2103, 2078, 2083, 2078, 2078, 2095, 2085, 2078, 2078, 2106, 2085, 2085, 2085, 2085, 2103, 2078, 2078, 2078, 2095, 2085, 2078, 2078, 2106, 2106, 2085, 2085, 2103, 2078, 2078, 2078, 2095, 2085, 2078, 2078, 2078, 2085, 2085, 2103, 2078, 2078, 2078, 2095, 2078, 2078, 2078, 2085, 2085, 2103, 2078, 2078, 2078, 2095, 2078, 2078, 2078, 2078, 2078, 2085, 2103, 2078, 2078, 2078, 2095, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2107, 2103, 2078, 2078, 2078, 2095, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2107, 2107, 2103, 2078, 2078, 2078, 2095, 2078, 2103, 2078, 2078, 2078, 2095, 2078, 2103, 2078, 2078, 2078, 2095, 2078, 2103, 2078, 2078, 2078, 2095, 2078, 2103, 2078, 2078, 2095, 2078, 2103, 2078, 2095, 2078, 2078, 2078, 2078, 0, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078 } ; static const flex_int32_t yy_nxt[3402] = { 0, 31, 32, 33, 32, 34, 32, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 51, 52, 53, 54, 55, 56, 57, 58, 58, 58, 58, 58, 58, 58, 59, 60, 61, 62, 58, 63, 64, 65, 66, 67, 68, 69, 58, 70, 71, 72, 58, 73, 74, 75, 76, 77, 58, 78, 79, 80, 58, 81, 82, 83, 58, 58, 84, 85, 86, 87, 88, 89, 235, 90, 91, 178, 236, 178, 178, 178, 178, 179, 178, 180, 178, 231, 192, 233, 92, 606, 93, 193, 206, 207, 208, 209, 210, 211, 228, 234, 229, 232, 185, 244, 501, 230, 94, 241, 95, 96, 97, 245, 98, 242, 99, 255, 1129, 100, 256, 101, 287, 102, 281, 282, 103, 319, 104, 106, 284, 107, 108, 109, 110, 111, 248, 237, 112, 113, 249, 114, 190, 115, 289, 238, 496, 239, 191, 251, 250, 299, 257, 252, 116, 240, 117, 118, 119, 300, 120, 253, 604, 254, 258, 307, 259, 285, 121, 260, 308, 122, 261, 272, 123, 124, 125, 126, 127, 128, 142, 273, 129, 130, 296, 131, 132, 133, 236, 134, 274, 135, 136, 137, 138, 139, 140, 286, 143, 142, 144, 141, 145, 298, 146, 1034, 147, 291, 207, 148, 395, 149, 210, 292, 267, 150, 151, 143, 152, 144, 153, 145, 142, 146, 268, 147, 938, 269, 148, 340, 149, 270, 271, 519, 150, 151, 228, 152, 229, 153, 143, 142, 144, 230, 145, 293, 146, 307, 154, 287, 520, 148, 308, 155, 331, 207, 309, 150, 156, 143, 152, 144, 153, 145, 142, 146, 247, 154, 321, 190, 148, 1130, 155, 192, 301, 214, 150, 156, 193, 152, 302, 153, 143, 142, 144, 409, 145, 410, 146, 413, 154, 414, 327, 148, 1131, 155, 257, 332, 209, 150, 156, 143, 152, 144, 153, 145, 142, 146, 258, 154, 259, 453, 148, 260, 155, 415, 304, 416, 150, 156, 328, 152, 420, 153, 143, 142, 144, 421, 145, 454, 146, 329, 154, 2078, 330, 148, 233, 155, 210, 333, 294, 150, 156, 143, 152, 144, 153, 145, 234, 146, 295, 154, 1132, 476, 148, 341, 155, 229, 477, 2078, 150, 156, 342, 152, 293, 153, 157, 157, 158, 157, 159, 157, 157, 160, 157, 157, 157, 157, 157, 157, 157, 157, 157, 157, 157, 157, 157, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 157, 157, 157, 157, 157, 157, 157, 161, 161, 161, 161, 161, 161, 161, 157, 162, 157, 157, 161, 157, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 157, 157, 157, 157, 163, 163, 164, 163, 165, 163, 163, 163, 163, 163, 163, 163, 163, 163, 163, 166, 163, 163, 163, 163, 163, 167, 167, 167, 167, 167, 167, 167, 167, 167, 167, 163, 163, 163, 163, 163, 163, 163, 167, 167, 167, 167, 167, 167, 167, 163, 163, 163, 163, 167, 163, 167, 167, 167, 167, 167, 167, 167, 167, 167, 167, 167, 167, 167, 167, 167, 167, 167, 167, 167, 167, 167, 167, 167, 167, 167, 167, 163, 163, 163, 163, 168, 168, 169, 168, 168, 168, 168, 168, 168, 168, 168, 168, 168, 168, 168, 170, 168, 168, 168, 168, 168, 171, 171, 171, 171, 171, 171, 171, 171, 171, 171, 168, 168, 168, 168, 168, 168, 168, 171, 171, 171, 171, 171, 171, 171, 168, 168, 168, 168, 171, 168, 171, 171, 171, 171, 171, 171, 171, 171, 171, 171, 171, 171, 171, 171, 171, 171, 171, 171, 171, 171, 171, 171, 171, 171, 171, 171, 168, 168, 168, 168, 172, 172, 173, 172, 172, 172, 172, 172, 172, 172, 172, 172, 172, 172, 172, 172, 172, 172, 172, 172, 174, 175, 175, 175, 175, 175, 175, 175, 175, 175, 175, 172, 172, 172, 172, 172, 172, 172, 175, 175, 175, 175, 175, 175, 175, 172, 172, 172, 172, 175, 176, 175, 175, 175, 175, 175, 175, 175, 175, 175, 175, 175, 175, 175, 175, 175, 175, 175, 175, 175, 175, 175, 175, 175, 175, 175, 175, 172, 172, 172, 172, 186, 186, 262, 276, 263, 464, 237, 277, 465, 425, 278, 279, 388, 264, 238, 265, 297, 280, 187, 266, 426, 187, 188, 186, 240, 447, 251, 447, 389, 267, 252, 187, 187, 187, 305, 306, 525, 187, 253, 268, 303, 526, 269, 322, 187, 364, 270, 271, 188, 249, 312, 313, 459, 186, 314, 186, 194, 194, 288, 365, 194, 323, 460, 315, 574, 296, 316, 195, 317, 351, 575, 390, 283, 1133, 196, 352, 197, 197, 197, 197, 197, 197, 197, 197, 197, 197, 331, 207, 216, 217, 218, 219, 220, 457, 400, 198, 221, 458, 570, 222, 324, 223, 355, 224, 199, 225, 226, 227, 356, 1134, 198, 200, 571, 289, 242, 401, 325, 326, 201, 202, 402, 203, 562, 563, 204, 335, 205, 335, 335, 335, 343, 400, 430, 430, 344, 679, 430, 233, 680, 336, 337, 294, 338, 345, 347, 237, 232, 408, 348, 234, 346, 349, 401, 238, 350, 353, 247, 402, 339, 1135, 357, 358, 368, 240, 301, 354, 359, 360, 361, 251, 363, 579, 522, 366, 258, 498, 259, 499, 703, 369, 523, 253, 370, 303, 371, 580, 262, 378, 372, 367, 498, 546, 499, 704, 379, 380, 267, 264, 373, 265, 1136, 374, 306, 266, 274, 585, 268, 382, 375, 269, 237, 381, 308, 376, 377, 383, 309, 386, 238, 275, 393, 277, 586, 384, 278, 387, 391, 403, 394, 385, 354, 280, 308, 738, 233, 341, 309, 229, 294, 247, 783, 392, 342, 397, 293, 348, 234, 301, 349, 357, 358, 350, 1137, 363, 251, 359, 396, 361, 398, 427, 371, 553, 262, 386, 399, 587, 253, 404, 303, 588, 278, 387, 492, 264, 367, 265, 581, 280, 251, 266, 357, 358, 407, 451, 582, 564, 359, 405, 406, 602, 253, 178, 303, 178, 178, 178, 186, 186, 367, 178, 179, 178, 180, 178, 486, 432, 433, 432, 434, 432, 487, 488, 194, 194, 187, 489, 194, 187, 438, 186, 438, 438, 438, 440, 507, 1140, 476, 187, 187, 187, 508, 477, 881, 187, 589, 509, 565, 566, 590, 510, 187, 573, 472, 567, 538, 567, 567, 567, 882, 186, 436, 186, 446, 446, 446, 446, 446, 446, 446, 446, 446, 446, 542, 592, 607, 599, 547, 624, 486, 600, 608, 541, 609, 620, 487, 488, 601, 550, 543, 489, 446, 440, 621, 439, 441, 441, 616, 690, 441, 568, 199, 199, 199, 199, 199, 199, 199, 199, 199, 199, 409, 691, 410, 617, 442, 442, 442, 442, 442, 442, 442, 442, 442, 442, 335, 628, 335, 335, 335, 442, 526, 442, 443, 442, 656, 444, 445, 442, 336, 337, 615, 338, 442, 1141, 442, 443, 443, 443, 442, 442, 578, 444, 430, 430, 635, 507, 430, 339, 444, 542, 611, 508, 445, 519, 1144, 486, 509, 442, 619, 442, 510, 487, 488, 629, 612, 596, 597, 636, 507, 529, 520, 630, 496, 611, 508, 616, 2078, 642, 644, 509, 773, 2078, 645, 510, 586, 650, 643, 612, 604, 641, 1018, 646, 648, 542, 1019, 550, 651, 774, 647, 486, 496, 413, 415, 657, 416, 487, 488, 420, 676, 596, 654, 801, 421, 655, 677, 1145, 604, 641, 658, 692, 658, 658, 658, 2078, 2078, 693, 802, 2078, 432, 433, 432, 434, 432, 432, 433, 432, 434, 432, 968, 432, 433, 432, 434, 432, 438, 969, 438, 438, 438, 665, 2078, 2078, 666, 667, 2078, 668, 668, 668, 668, 668, 836, 668, 665, 665, 665, 728, 776, 442, 666, 705, 2078, 2078, 684, 436, 777, 666, 685, 819, 436, 667, 442, 442, 442, 659, 436, 779, 2078, 820, 812, 686, 687, 780, 688, 2078, 1146, 755, 756, 2078, 448, 448, 448, 448, 448, 448, 448, 448, 448, 448, 769, 439, 446, 446, 446, 446, 446, 446, 446, 446, 446, 446, 708, 808, 809, 709, 829, 757, 448, 798, 985, 670, 710, 697, 715, 711, 716, 778, 712, 713, 446, 758, 717, 1023, 759, 799, 670, 200, 567, 1030, 567, 567, 567, 1031, 201, 202, 737, 203, 839, 858, 204, 859, 205, 448, 448, 448, 448, 448, 448, 448, 448, 448, 448, 771, 1047, 840, 709, 772, 1048, 715, 847, 824, 852, 710, 841, 784, 711, 825, 842, 712, 713, 448, 813, 750, 568, 709, 814, 858, 815, 880, 850, 870, 710, 1147, 828, 816, 749, 867, 817, 713, 709, 814, 851, 815, 2078, 850, 884, 710, 1148, 828, 816, 878, 930, 817, 713, 1065, 413, 851, 657, 658, 1066, 658, 658, 658, 668, 668, 984, 892, 668, 892, 2078, 2078, 2078, 902, 924, 2078, 925, 903, 955, 956, 978, 979, 930, 1025, 1027, 1053, 944, 978, 979, 1149, 904, 930, 1152, 1022, 1153, 934, 984, 1040, 1076, 1092, 1026, 1054, 1022, 1079, 944, 984, 1112, 1154, 1112, 1112, 1112, 957, 1127, 1128, 1155, 1093, 1142, 1143, 1150, 1151, 1156, 1157, 1158, 1159, 659, 1160, 1161, 1162, 958, 893, 893, 893, 893, 893, 893, 893, 893, 893, 893, 893, 893, 893, 893, 893, 893, 893, 893, 893, 893, 1138, 1163, 1164, 1165, 1166, 1167, 1168, 1169, 893, 1170, 1171, 1172, 1173, 1174, 1175, 1176, 1177, 1139, 893, 1178, 1179, 1180, 1181, 1182, 1183, 1184, 1185, 1186, 1187, 1188, 1189, 1190, 1191, 1192, 1193, 1194, 1195, 1196, 1197, 1198, 1199, 1200, 1201, 1202, 1203, 1205, 1207, 1208, 1209, 1136, 1211, 1212, 1213, 1204, 1214, 1210, 1215, 1216, 1217, 1206, 1218, 1219, 1220, 1221, 1222, 1223, 1225, 1184, 1227, 1228, 1229, 1230, 1231, 1232, 1233, 1234, 1235, 1236, 1224, 1226, 1237, 1238, 1239, 1240, 1242, 1243, 1244, 1245, 1246, 1247, 1248, 1249, 1241, 1250, 1251, 1252, 1253, 1254, 1255, 1256, 1257, 1258, 1259, 1260, 1261, 1262, 1263, 1264, 1265, 1266, 1267, 1268, 1269, 1271, 1272, 1273, 1274, 1275, 1276, 1277, 1223, 1278, 1279, 1280, 1281, 1282, 1283, 1284, 1285, 1270, 1286, 1287, 1288, 1224, 1289, 1290, 1291, 1292, 1293, 1295, 1296, 1295, 1297, 1295, 1298, 1299, 1300, 1301, 1302, 1303, 1304, 1305, 1306, 1307, 1308, 1309, 1310, 1311, 1312, 1313, 1314, 1315, 1316, 1317, 1318, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327, 1328, 1329, 1330, 1331, 1332, 1333, 1334, 1335, 1336, 1337, 1338, 1339, 1340, 1341, 1342, 1343, 1344, 1345, 1346, 1347, 1348, 1349, 1350, 1351, 1352, 1353, 1354, 1355, 1356, 1357, 1358, 1359, 1360, 1361, 1362, 1363, 1364, 1365, 1366, 1367, 1368, 1369, 1370, 1371, 1373, 1374, 1375, 1376, 1377, 1378, 1379, 1380, 1372, 1381, 1382, 1383, 1384, 1385, 1386, 1387, 1388, 1389, 1390, 1391, 1392, 1393, 1394, 1395, 1396, 1397, 1398, 1399, 1400, 1401, 1402, 1403, 1404, 1405, 1406, 1407, 1408, 1409, 1410, 1411, 1412, 1413, 1414, 1415, 1337, 1338, 1416, 1417, 1418, 1419, 1420, 1421, 1422, 1423, 1424, 1425, 1426, 1427, 1428, 1429, 1430, 1431, 1432, 1433, 1434, 1435, 1436, 1437, 1438, 1439, 1296, 1441, 1440, 1295, 1296, 1295, 1297, 1295, 1295, 1296, 1295, 1297, 1295, 1442, 1443, 1444, 1445, 1446, 1447, 1448, 1447, 1447, 1447, 1449, 1450, 1451, 1452, 1453, 1454, 1455, 1456, 1457, 1458, 1459, 1460, 1461, 1462, 1463, 1464, 1465, 1466, 1467, 1468, 1469, 1470, 1471, 1472, 1473, 1474, 1475, 1476, 1477, 1478, 1479, 1480, 1481, 1482, 1485, 1486, 1483, 1487, 1488, 1489, 1490, 1491, 1484, 1492, 1493, 1494, 1495, 1496, 1497, 1498, 1499, 1500, 1501, 1502, 1503, 1504, 1505, 1506, 1507, 1508, 1509, 1510, 1511, 1512, 1513, 1514, 1515, 1516, 1517, 1518, 1519, 1520, 1521, 1522, 1523, 1524, 1525, 1526, 1527, 1528, 1529, 1530, 1531, 1532, 1533, 1534, 1535, 1536, 1538, 1536, 1536, 1536, 1537, 1539, 1537, 1537, 1537, 1540, 1541, 1542, 1543, 1544, 1545, 1546, 1547, 1548, 1549, 1296, 1550, 1440, 1551, 1552, 1553, 1554, 1555, 1557, 1559, 1557, 1447, 1557, 1560, 1562, 1563, 1564, 1565, 1566, 1567, 1561, 1568, 1569, 1570, 1571, 1572, 1573, 1574, 1575, 1576, 1577, 1578, 1579, 1580, 1581, 1582, 1583, 1584, 1585, 1586, 1587, 1588, 1589, 1590, 1591, 1592, 1593, 1594, 1595, 1596, 1597, 1598, 1599, 1600, 1601, 1602, 1603, 1604, 1605, 1606, 1607, 1608, 1609, 1610, 1611, 1612, 1613, 1614, 1615, 1617, 1620, 1621, 1616, 1558, 1616, 1616, 1616, 1536, 1622, 1536, 1536, 1536, 1537, 1623, 1537, 1537, 1537, 1624, 1627, 1628, 1629, 1630, 1631, 1632, 1633, 1634, 1635, 1625, 1636, 1637, 1638, 1639, 2078, 1626, 1557, 1641, 1557, 1447, 1557, 2078, 1642, 1643, 1644, 1645, 1646, 1647, 1648, 1649, 1650, 1651, 1652, 1653, 1654, 1655, 1656, 1657, 1658, 1659, 1660, 1661, 1662, 1663, 1664, 1665, 1666, 1667, 1668, 1669, 1670, 1671, 1672, 1673, 1618, 1674, 1675, 1676, 1677, 1619, 1678, 1679, 1680, 1681, 1682, 1616, 1684, 1616, 1616, 1616, 1685, 1686, 1687, 1688, 1689, 1690, 1691, 1692, 1693, 1694, 1695, 1558, 1696, 1697, 1698, 1640, 1699, 1700, 1701, 1702, 1703, 1705, 1706, 1707, 2078, 1709, 1710, 1704, 1711, 1712, 1713, 1712, 1712, 1712, 1714, 1715, 1716, 1717, 1718, 1719, 1720, 1721, 1722, 1723, 1724, 1725, 1726, 1727, 1728, 1729, 1730, 1731, 1732, 1733, 1734, 1735, 1736, 1737, 1738, 1739, 1683, 1740, 1741, 1742, 1743, 1744, 1745, 1746, 1747, 1748, 1749, 1750, 1751, 1752, 1753, 1754, 1755, 1756, 2078, 1758, 1759, 1760, 1763, 1764, 1762, 1708, 1762, 1712, 1762, 1765, 1766, 1767, 1768, 1769, 1770, 1771, 1772, 1773, 1774, 1775, 1776, 1777, 1778, 1779, 1780, 1781, 1782, 1783, 1784, 1785, 1786, 1790, 1791, 1792, 1793, 1794, 1795, 1796, 1797, 1798, 1799, 1800, 1787, 2078, 1802, 1803, 1804, 1788, 2078, 1805, 1806, 1762, 1789, 1762, 1712, 1762, 1807, 1808, 1809, 1810, 1811, 1812, 1813, 1814, 1757, 1815, 1816, 1817, 1818, 1819, 1820, 1821, 1822, 1823, 1824, 1825, 1826, 1827, 1828, 1829, 1830, 1831, 1832, 2078, 1834, 1835, 1836, 1837, 1838, 1839, 1840, 1841, 1842, 1843, 1801, 1844, 1845, 1846, 1847, 1848, 1849, 1850, 1851, 1852, 1853, 1854, 1855, 1856, 1857, 1858, 1859, 1860, 1861, 2078, 1863, 1864, 1865, 1866, 1867, 1868, 1869, 1870, 1871, 1872, 1873, 1875, 1876, 1877, 1873, 1878, 1874, 1879, 1833, 1880, 1881, 1882, 1883, 1884, 1885, 1886, 1887, 1888, 1889, 1890, 1892, 1890, 1891, 1890, 1893, 1894, 1895, 1896, 1897, 1898, 1900, 1898, 1898, 1898, 1899, 1873, 1899, 1899, 1899, 1873, 1901, 1874, 1902, 1903, 1904, 1903, 1903, 1903, 1905, 1906, 1907, 1908, 1909, 1910, 1911, 1862, 1912, 1913, 1890, 1916, 1890, 1891, 1890, 1891, 1917, 1891, 1891, 1891, 1918, 1919, 1922, 1919, 1919, 1919, 1898, 1923, 1898, 1898, 1898, 1899, 1924, 1899, 1899, 1899, 1925, 1903, 1927, 1903, 1903, 1903, 1928, 1929, 1930, 1931, 1932, 1933, 1934, 1935, 1936, 2078, 1938, 1939, 1940, 1919, 1942, 1919, 1919, 1919, 1943, 1914, 1944, 1945, 1946, 1947, 1915, 2078, 1948, 2078, 2078, 2078, 1949, 1950, 1951, 1952, 1953, 2078, 1955, 1956, 1920, 1957, 1921, 1958, 1959, 1960, 1961, 1962, 1963, 1964, 1963, 1963, 1963, 1965, 1966, 1967, 2078, 1969, 1970, 1971, 1972, 1973, 1937, 1974, 1975, 1978, 1979, 2078, 1977, 1941, 1977, 1963, 1977, 1981, 1982, 1983, 1984, 1985, 1986, 1987, 1988, 2078, 1977, 1989, 1977, 1963, 1977, 1990, 2078, 1992, 1954, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2078, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2078, 1968, 2013, 2014, 2015, 2016, 2017, 2018, 2020, 2022, 2024, 2019, 2021, 2078, 2023, 2027, 2025, 1980, 2025, 2025, 2025, 2028, 2029, 1991, 2030, 2031, 2032, 2034, 2035, 2036, 2037, 2038, 2039, 2078, 2043, 2044, 2041, 2033, 2041, 2025, 2041, 2045, 2046, 2047, 2078, 2041, 2078, 2041, 2025, 2041, 2049, 2001, 2050, 2051, 2052, 2053, 2078, 2055, 2056, 2057, 2058, 2059, 2078, 2061, 2012, 2062, 2063, 2064, 2065, 2078, 2067, 2068, 2069, 2070, 2026, 2078, 2072, 2073, 2074, 2078, 2075, 2076, 2077, 1126, 1125, 1124, 1123, 1122, 1121, 1120, 1119, 1118, 1117, 1116, 1115, 1114, 1113, 2048, 1111, 2042, 1110, 1109, 1108, 1107, 1106, 2054, 1105, 1104, 1103, 1102, 1101, 1100, 1099, 1098, 1097, 1096, 1095, 1094, 1091, 1090, 2066, 1089, 1088, 1087, 1086, 2071, 1085, 1084, 2060, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 177, 177, 177, 177, 177, 177, 177, 177, 177, 177, 177, 177, 177, 182, 182, 182, 182, 182, 182, 182, 182, 182, 182, 182, 1083, 182, 184, 1082, 1081, 1080, 1079, 184, 184, 1078, 184, 212, 1077, 1075, 212, 1074, 212, 212, 1073, 212, 213, 1072, 1071, 1070, 213, 213, 213, 213, 213, 213, 213, 213, 213, 215, 1069, 215, 215, 1068, 215, 411, 1067, 411, 411, 1064, 411, 412, 412, 412, 412, 412, 412, 412, 412, 412, 412, 412, 412, 412, 418, 1063, 418, 418, 1062, 418, 419, 419, 1061, 419, 419, 419, 419, 419, 419, 419, 419, 419, 419, 422, 1060, 422, 422, 1059, 422, 424, 1058, 424, 424, 1057, 424, 428, 1056, 1055, 428, 1052, 428, 428, 1051, 428, 431, 431, 1050, 1049, 1046, 1045, 431, 431, 431, 1044, 1043, 431, 435, 435, 435, 1042, 1041, 1039, 1038, 1037, 435, 435, 435, 435, 437, 437, 1036, 437, 437, 437, 437, 437, 437, 437, 437, 437, 437, 448, 448, 1035, 1033, 1032, 1029, 448, 561, 561, 561, 561, 561, 1028, 561, 561, 561, 561, 561, 561, 561, 662, 1024, 1021, 662, 1020, 662, 662, 1017, 662, 663, 1016, 1015, 1014, 663, 663, 663, 663, 663, 663, 663, 663, 663, 669, 669, 1013, 1012, 1011, 1010, 669, 669, 669, 1009, 1008, 669, 893, 893, 1007, 1006, 1005, 1004, 893, 1294, 1294, 1294, 1294, 1294, 1294, 1294, 1294, 1294, 1294, 1294, 1294, 1294, 1556, 1556, 1003, 1556, 1556, 1556, 1556, 1556, 1556, 1556, 1556, 1556, 1556, 1761, 1761, 1002, 1761, 1761, 1761, 1761, 1761, 1761, 1761, 1761, 1761, 1761, 1926, 1001, 1926, 1000, 999, 998, 1926, 997, 1926, 1926, 1976, 1976, 996, 1976, 1976, 1976, 1976, 1976, 1976, 1976, 1976, 1976, 1976, 2040, 2040, 995, 2040, 2040, 2040, 2040, 2040, 2040, 2040, 2040, 2040, 2040, 994, 993, 992, 991, 990, 989, 988, 987, 986, 985, 983, 982, 981, 980, 977, 976, 975, 974, 973, 972, 971, 970, 967, 966, 965, 964, 963, 962, 961, 960, 959, 954, 953, 952, 951, 950, 949, 948, 947, 946, 945, 944, 943, 942, 941, 940, 939, 938, 937, 936, 935, 934, 933, 932, 931, 930, 929, 928, 927, 926, 923, 922, 921, 920, 919, 918, 917, 916, 915, 914, 913, 912, 911, 910, 909, 908, 907, 906, 905, 901, 900, 899, 898, 897, 896, 895, 894, 449, 891, 890, 889, 888, 887, 886, 885, 883, 879, 877, 876, 875, 874, 873, 872, 871, 869, 868, 866, 865, 864, 863, 862, 861, 860, 857, 856, 855, 854, 853, 849, 848, 846, 845, 844, 843, 838, 837, 835, 834, 833, 832, 831, 830, 828, 827, 826, 823, 822, 821, 818, 811, 810, 807, 806, 805, 804, 803, 800, 797, 796, 795, 794, 793, 792, 791, 790, 789, 788, 787, 786, 785, 784, 782, 781, 778, 775, 770, 769, 768, 767, 766, 765, 764, 763, 762, 761, 760, 754, 753, 752, 751, 750, 749, 748, 747, 746, 745, 744, 743, 742, 741, 740, 739, 738, 737, 736, 735, 734, 733, 732, 731, 730, 729, 728, 727, 726, 725, 724, 723, 722, 721, 720, 719, 718, 714, 707, 706, 705, 702, 701, 700, 699, 698, 697, 696, 695, 694, 689, 683, 682, 681, 678, 675, 674, 673, 672, 671, 664, 661, 660, 653, 652, 649, 640, 639, 638, 637, 634, 633, 632, 631, 627, 626, 625, 623, 622, 618, 615, 614, 613, 610, 605, 603, 598, 595, 594, 593, 591, 584, 583, 578, 577, 576, 572, 569, 560, 559, 558, 557, 556, 555, 554, 552, 551, 550, 549, 548, 547, 545, 544, 541, 540, 539, 537, 536, 535, 534, 533, 532, 531, 530, 529, 528, 527, 524, 521, 518, 517, 516, 515, 514, 513, 512, 511, 506, 505, 504, 503, 502, 501, 500, 497, 496, 495, 494, 493, 492, 491, 490, 485, 484, 483, 482, 481, 480, 479, 478, 475, 474, 473, 472, 471, 470, 469, 468, 467, 466, 463, 462, 461, 456, 455, 452, 451, 449, 450, 449, 449, 449, 449, 429, 183, 427, 423, 417, 362, 334, 320, 318, 311, 310, 298, 290, 288, 283, 275, 247, 246, 243, 214, 191, 190, 189, 185, 183, 181, 2078, 105, 105, 29, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078 } ; static const flex_int32_t yy_chk[3402] = { 0, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 5, 5, 67, 5, 5, 32, 67, 32, 32, 32, 34, 34, 34, 34, 34, 65, 49, 66, 5, 368, 5, 49, 53, 53, 54, 54, 55, 55, 64, 66, 64, 65, 110, 71, 368, 64, 5, 69, 5, 5, 5, 71, 5, 69, 5, 76, 926, 5, 76, 5, 88, 5, 83, 83, 5, 110, 5, 9, 87, 9, 9, 9, 9, 9, 74, 68, 9, 9, 74, 9, 88, 9, 90, 68, 366, 68, 90, 75, 74, 99, 77, 75, 9, 68, 9, 9, 9, 99, 9, 75, 366, 75, 77, 104, 77, 87, 9, 77, 104, 9, 77, 80, 9, 9, 9, 9, 9, 9, 11, 80, 9, 9, 96, 9, 9, 9, 96, 9, 80, 9, 9, 9, 9, 9, 9, 87, 11, 12, 11, 9, 11, 146, 11, 824, 11, 92, 92, 11, 146, 11, 93, 93, 79, 11, 11, 12, 11, 12, 11, 12, 13, 12, 79, 12, 824, 79, 12, 122, 12, 79, 79, 272, 12, 12, 94, 12, 94, 12, 13, 14, 13, 94, 13, 94, 13, 105, 13, 112, 272, 13, 105, 13, 117, 117, 105, 13, 13, 14, 13, 14, 13, 14, 15, 14, 100, 14, 112, 112, 14, 927, 14, 115, 100, 122, 14, 14, 115, 14, 100, 14, 15, 16, 15, 159, 15, 159, 15, 162, 15, 162, 115, 15, 928, 15, 102, 118, 118, 15, 15, 16, 15, 16, 15, 16, 17, 16, 102, 16, 102, 216, 16, 102, 16, 165, 102, 165, 16, 16, 116, 16, 170, 16, 17, 18, 17, 170, 17, 216, 17, 116, 17, 445, 116, 17, 95, 17, 119, 119, 95, 17, 17, 18, 17, 18, 17, 18, 95, 18, 95, 18, 929, 235, 18, 123, 18, 123, 235, 445, 18, 18, 123, 18, 123, 18, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 41, 41, 78, 82, 78, 224, 97, 82, 224, 176, 82, 82, 141, 78, 97, 78, 97, 82, 41, 78, 176, 41, 41, 41, 97, 198, 101, 198, 141, 103, 101, 41, 41, 41, 103, 103, 276, 41, 101, 103, 101, 276, 103, 113, 41, 132, 103, 103, 41, 132, 108, 108, 220, 41, 108, 41, 50, 50, 113, 132, 50, 113, 220, 108, 344, 126, 108, 50, 108, 126, 344, 142, 141, 930, 50, 126, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 142, 142, 63, 63, 63, 63, 63, 219, 151, 50, 63, 219, 341, 63, 114, 63, 128, 63, 50, 63, 63, 63, 128, 931, 50, 50, 341, 114, 128, 151, 114, 114, 50, 50, 151, 50, 331, 331, 50, 121, 50, 121, 121, 121, 124, 156, 187, 187, 124, 459, 187, 125, 459, 121, 121, 125, 121, 124, 125, 127, 124, 156, 125, 125, 124, 125, 156, 127, 125, 127, 131, 156, 121, 932, 129, 129, 134, 127, 131, 127, 129, 129, 129, 133, 131, 348, 274, 133, 134, 254, 134, 254, 477, 134, 274, 133, 134, 133, 135, 348, 135, 137, 135, 133, 303, 303, 303, 477, 137, 137, 136, 135, 136, 135, 933, 136, 136, 135, 137, 353, 136, 138, 136, 136, 145, 137, 138, 136, 136, 139, 138, 140, 145, 139, 145, 140, 353, 139, 140, 140, 143, 152, 145, 139, 145, 140, 152, 547, 144, 143, 152, 143, 144, 148, 547, 144, 143, 148, 143, 144, 144, 148, 144, 147, 147, 144, 934, 148, 149, 147, 147, 147, 149, 310, 150, 310, 150, 153, 150, 354, 149, 153, 149, 354, 153, 153, 364, 150, 149, 150, 349, 153, 155, 150, 154, 154, 155, 332, 349, 332, 154, 154, 154, 364, 155, 178, 155, 178, 178, 178, 188, 188, 155, 180, 180, 180, 180, 180, 245, 189, 189, 189, 189, 189, 245, 245, 194, 194, 188, 245, 194, 188, 193, 188, 193, 193, 193, 194, 263, 938, 296, 188, 188, 188, 263, 296, 651, 188, 355, 263, 333, 333, 355, 263, 188, 343, 343, 337, 296, 337, 337, 337, 651, 188, 189, 188, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 300, 357, 369, 363, 370, 382, 300, 363, 369, 357, 370, 379, 300, 300, 363, 382, 300, 300, 196, 199, 379, 193, 195, 195, 376, 465, 195, 337, 199, 199, 199, 199, 199, 199, 199, 199, 199, 199, 410, 465, 410, 376, 195, 195, 195, 195, 195, 195, 195, 195, 195, 195, 335, 386, 335, 335, 335, 195, 386, 195, 195, 195, 408, 195, 195, 195, 335, 335, 408, 335, 195, 939, 195, 195, 195, 195, 195, 195, 392, 195, 430, 430, 392, 372, 430, 335, 195, 361, 372, 372, 195, 378, 941, 361, 372, 195, 378, 195, 372, 361, 361, 387, 372, 361, 361, 393, 399, 387, 378, 387, 398, 399, 399, 401, 419, 399, 400, 399, 540, 419, 400, 399, 393, 403, 399, 399, 398, 398, 809, 400, 401, 406, 809, 403, 403, 540, 400, 406, 407, 414, 416, 414, 416, 406, 406, 420, 457, 406, 406, 574, 420, 407, 457, 944, 407, 407, 423, 466, 423, 423, 423, 431, 431, 466, 574, 431, 432, 432, 432, 432, 432, 433, 433, 433, 433, 433, 748, 434, 434, 434, 434, 434, 438, 748, 438, 438, 438, 440, 442, 442, 440, 440, 442, 443, 443, 444, 444, 443, 603, 444, 440, 440, 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688, 687, 686, 685, 684, 683, 682, 681, 679, 678, 677, 676, 675, 674, 673, 672, 671, 664, 661, 660, 659, 656, 655, 654, 652, 649, 647, 646, 645, 644, 643, 642, 641, 638, 637, 635, 634, 630, 629, 628, 627, 626, 623, 622, 621, 620, 619, 616, 615, 613, 612, 610, 609, 606, 605, 602, 601, 600, 599, 598, 597, 595, 594, 593, 590, 589, 588, 586, 583, 582, 580, 579, 578, 577, 576, 573, 571, 570, 566, 562, 559, 558, 557, 556, 555, 554, 552, 550, 549, 548, 546, 545, 543, 541, 538, 537, 536, 535, 531, 529, 528, 527, 526, 525, 524, 522, 521, 520, 519, 518, 517, 516, 515, 514, 513, 512, 511, 510, 509, 507, 506, 505, 504, 503, 502, 501, 500, 499, 497, 496, 495, 494, 493, 492, 491, 490, 489, 488, 487, 486, 485, 484, 482, 480, 479, 478, 476, 475, 474, 473, 472, 471, 469, 468, 467, 464, 462, 461, 460, 458, 456, 455, 454, 453, 450, 439, 426, 425, 405, 404, 402, 397, 396, 395, 394, 391, 390, 389, 388, 385, 384, 383, 381, 380, 377, 375, 374, 373, 371, 367, 365, 362, 360, 359, 358, 356, 351, 350, 347, 346, 345, 342, 338, 326, 317, 316, 315, 314, 313, 312, 309, 308, 307, 306, 305, 304, 302, 301, 299, 298, 297, 295, 294, 293, 292, 291, 282, 281, 280, 279, 278, 277, 275, 273, 271, 270, 269, 268, 267, 266, 265, 264, 262, 261, 260, 259, 258, 257, 256, 253, 252, 251, 250, 249, 248, 247, 246, 243, 242, 241, 240, 239, 238, 237, 236, 234, 233, 232, 231, 230, 229, 228, 227, 226, 225, 223, 222, 221, 218, 217, 213, 208, 205, 204, 203, 202, 201, 200, 185, 182, 181, 174, 166, 130, 120, 111, 109, 107, 106, 98, 91, 89, 85, 81, 73, 72, 70, 62, 47, 44, 42, 40, 36, 35, 29, 8, 7, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078, 2078 } ; static yy_state_type yy_last_accepting_state; static char *yy_last_accepting_cpos; extern int yy_flex_debug; int yy_flex_debug = 1; static const flex_int32_t yy_rule_linenum[422] = { 0, 115, 119, 120, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214, 215, 216, 217, 218, 219, 220, 221, 222, 223, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 243, 244, 245, 246, 247, 248, 249, 250, 251, 252, 258, 264, 265, 266, 267, 268, 269, 271, 272, 273, 274, 275, 276, 277, 278, 279, 280, 281, 282, 283, 284, 285, 286, 287, 288, 289, 290, 291, 292, 293, 294, 295, 296, 297, 298, 299, 300, 301, 302, 303, 304, 305, 306, 307, 308, 309, 310, 311, 312, 313, 314, 315, 316, 317, 318, 319, 320, 321, 322, 323, 324, 325, 326, 327, 328, 329, 330, 331, 332, 333, 334, 335, 336, 337, 338, 339, 340, 341, 342, 343, 344, 345, 346, 347, 348, 349, 350, 351, 352, 353, 354, 355, 356, 357, 358, 359, 360, 361, 362, 363, 364, 365, 366, 367, 373, 374, 375, 376, 377, 378, 379, 380, 381, 382, 383, 384, 385, 386, 387, 388, 389, 390, 391, 392, 393, 394, 395, 401, 402, 403, 404, 412, 419, 420, 423, 424, 425, 426, 427, 428, 429, 430, 431, 432, 433, 434, 435, 436, 437, 438, 439, 440, 441, 442, 443, 444, 445, 446, 447, 455, 456, 457, 458, 459, 460, 461, 462, 463, 464, 465, 466, 467, 468, 469, 470, 471, 472, 477, 478, 479, 480, 481, 482, 487, 488, 489, 490, 491, 492, 493, 494, 495, 496, 497, 498, 499, 500, 501, 502, 503, 504, 505, 506, 507, 508, 509, 510, 511, 512, 514, 515, 516, 517, 522, 528, 536, 544, 545, 547, 549, 564, 567, 570, 573, 581, 582, 583, 584, 586, 587, 591, 592, 593, 594, 595, 601, 602, 603, 604, 606, 607, 613, 614, 615, 616, 624, 630, 631, 632, 633, 634, 635, 636, 637, 638, 639, 640, 641, 642, 643, 644, 645, 646, 647, 648, 649, 650, 651, 652, 653, 654, 655, 656, 657, 658, 659, 660, 661, 662, 665, 666, 667, 668, 669, 670, 671, 672, 673, 674, 681, 684, 686, 687, 688, 692 } ; /* The intent behind this definition is that it'll catch * any uses of REJECT which flex missed. */ #define REJECT reject_used_but_not_detected static int yy_more_flag = 0; static int yy_more_len = 0; #define yymore() ((yy_more_flag) = 1) #define YY_MORE_ADJ (yy_more_len) #define YY_RESTORE_YY_MORE_OFFSET char *yytext; #line 1 "VParseLex.l" #line 6 "VParseLex.l" /************************************************************************** * DESCRIPTION: Verilog Parser Lexer * * This file is part of Verilog-Perl. * * Author: Wilson Snyder * * Code available from: https://www.veripool.org/verilog-perl * ************************************************************************** * * Copyright 2000-2024 by Wilson Snyder. This program is free software; * you can redistribute it and/or modify it under the terms of either the * GNU Lesser General Public License Version 3 or the Perl Artistic License * Version 2.0. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * ************************************************************************** * Do not use Flex in C++ mode. It has bugs with yyunput() which result in * lost characters. *************************************************************************/ #include "VParseLex.h" #include #include #include #include #include "VParseGrammar.h" #include "VParseBison.h" #define YY_SKIP_YYWRAP #define STATE_VERILOG_RECENT S23 // State name for most recent Verilog Version // Flex 2.5.35 has compile warning in ECHO, so we'll default our own rule #define ECHO yyerrorf("Missing VParseLex.l rule: ECHO rule invoked in state %d: %s", YY_START, yytext); VParseLex* VParseLex::s_currentLexp = NULL; // Current lexing point VParseBisonYYSType* VParseLex::s_yylvalp = NULL; // LValue for current bison object #define LEXP (VParseLex::s_currentLexp) #define LPARSEP (LEXP->m_parsep) #define NEXTLINE() { LPARSEP->inFilelineInc(); } #define LINECHECKS(textp,len) { const char* cp=textp; for (int n=len; n; --n) if (cp[n]=='\n') NEXTLINE(); } #define LINECHECK() LINECHECKS(yytext,yyleng) #define FL { VParseLex::s_yylvalp->fl = LPARSEP->inFilelinep(); } // lval.fileline not used yet; here for Verilator parser compatibility #define VALTEXTS(strg) VParseLex::s_yylvalp->str = strg #define VALTEXT VALTEXTS(string(yytext,yyleng)) #define CALLBACKS(whichCb,strg) {LPARSEP->whichCb(VParseLex::s_yylvalp->fl, strg); } #define CALLBACK(whichCb) CALLBACKS(whichCb,string(yytext,yyleng)) #define YY_INPUT(buf,result,max_size) \ result = LPARSEP->inputToLex(buf,max_size); int yywrap() { return LPARSEP->eofToLex(); } #define StashPrefix LPARSEP->unreadbackCat(yytext,yyleng) void yyerror(char* errmsg) { LPARSEP->inFilelinep()->error(errmsg); } void yyerrorf(const char* format, ...) { char msg[1024]; va_list ap; va_start(ap,format); vsprintf(msg,format,ap); va_end(ap); yyerror(msg); } /**********************************************************************/ #line 2361 "VParseLex_pretmp.cpp" #line 100 "VParseLex.l" /* identifier */ /* escaped identifier */ /* verilog numbers, constructed to not match the ' that begins a '( or '{ */ #line 2367 "VParseLex_pretmp.cpp" #define INITIAL 0 #define V95 1 #define V01 2 #define V05 3 #define S05 4 #define S09 5 #define S12 6 #define S17 7 #define S23 8 #define STRING 9 #define ATTRMODE 10 #define CMTMODE 11 #define PROTMODE 12 #define DUMMY_TO_AVOID_WARNING 13 #ifndef YY_NO_UNISTD_H /* Special case for "unistd.h", since it is non-ANSI. We include it way * down here because we want the user's section 1 to have been scanned first. * The user has a chance to override it with an option. */ /* %if-c-only */ #include /* %endif */ /* %if-c++-only */ /* %endif */ #endif #ifndef YY_EXTRA_TYPE #define YY_EXTRA_TYPE void * #endif /* %if-c-only Reentrant structure and macros (non-C++). */ /* %if-reentrant */ /* %if-c-only */ static int yy_init_globals ( void ); /* %endif */ /* %if-reentrant */ /* %endif */ /* %endif End reentrant structures and macros. */ /* Accessor methods to globals. These are made visible to non-reentrant scanners for convenience. */ int yylex_destroy ( void ); int yyget_debug ( void ); void yyset_debug ( int debug_flag ); YY_EXTRA_TYPE yyget_extra ( void ); void yyset_extra ( YY_EXTRA_TYPE user_defined ); FILE *yyget_in ( void ); void yyset_in ( FILE * _in_str ); FILE *yyget_out ( void ); void yyset_out ( FILE * _out_str ); int yyget_leng ( void ); char *yyget_text ( void ); int yyget_lineno ( void ); void yyset_lineno ( int _line_number ); /* %if-bison-bridge */ /* %endif */ /* Macros after this point can all be overridden by user definitions in * section 1. */ #ifndef YY_SKIP_YYWRAP #ifdef __cplusplus extern "C" int yywrap ( void ); #else extern int yywrap ( void ); #endif #endif /* %not-for-header */ #ifndef YY_NO_UNPUT static void yyunput ( int c, char *buf_ptr ); #endif /* %ok-for-header */ /* %endif */ #ifndef yytext_ptr static void yy_flex_strncpy ( char *, const char *, int ); #endif #ifdef YY_NEED_STRLEN static int yy_flex_strlen ( const char * ); #endif #ifndef YY_NO_INPUT /* %if-c-only Standard (non-C++) definition */ /* %not-for-header */ #ifdef __cplusplus static int yyinput ( void ); #else static int input ( void ); #endif /* %ok-for-header */ /* %endif */ #endif /* %if-c-only */ static int yy_start_stack_ptr = 0; static int yy_start_stack_depth = 0; static int *yy_start_stack = NULL; static void yy_push_state ( int _new_state ); static void yy_pop_state ( void ); static int yy_top_state ( void ); /* %endif */ /* Amount of stuff to slurp up with each read. */ #ifndef YY_READ_BUF_SIZE #ifdef __ia64__ /* On IA-64, the buffer size is 16k, not 8k */ #define YY_READ_BUF_SIZE 16384 #else #define YY_READ_BUF_SIZE 8192 #endif /* __ia64__ */ #endif /* Copy whatever the last rule matched to the standard output. */ #ifndef ECHO /* %if-c-only Standard (non-C++) definition */ /* This used to be an fputs(), but since the string might contain NUL's, * we now use fwrite(). */ #define ECHO do { if (fwrite( yytext, (size_t) yyleng, 1, yyout )) {} } while (0) /* %endif */ /* %if-c++-only C++ definition */ /* %endif */ #endif /* Gets input and stuffs it into "buf". number of characters read, or YY_NULL, * is returned in "result". */ #ifndef YY_INPUT #define YY_INPUT(buf,result,max_size) \ /* %% [5.0] fread()/read() definition of YY_INPUT goes here unless we're doing C++ \ */\ if ( YY_CURRENT_BUFFER_LVALUE->yy_is_interactive ) \ { \ int c = '*'; \ int n; \ for ( n = 0; n < max_size && \ (c = getc( yyin )) != EOF && c != '\n'; ++n ) \ buf[n] = (char) c; \ if ( c == '\n' ) \ buf[n++] = (char) c; \ if ( c == EOF && ferror( yyin ) ) \ YY_FATAL_ERROR( "input in flex scanner failed" ); \ result = n; \ } \ else \ { \ errno=0; \ while ( (result = (int) fread(buf, 1, (yy_size_t) max_size, yyin)) == 0 && ferror(yyin)) \ { \ if( errno != EINTR) \ { \ YY_FATAL_ERROR( "input in flex scanner failed" ); \ break; \ } \ errno=0; \ clearerr(yyin); \ } \ }\ \ /* %if-c++-only C++ definition \ */\ /* %endif */ #endif /* No semi-colon after return; correct usage is to write "yyterminate();" - * we don't want an extra ';' after the "return" because that will cause * some compilers to complain about unreachable statements. */ #ifndef yyterminate #define yyterminate() return YY_NULL #endif /* Number of entries by which start-condition stack grows. */ #ifndef YY_START_STACK_INCR #define YY_START_STACK_INCR 25 #endif /* Report a fatal error. */ #ifndef YY_FATAL_ERROR /* %if-c-only */ #define YY_FATAL_ERROR(msg) yy_fatal_error( msg ) /* %endif */ /* %if-c++-only */ /* %endif */ #endif /* %if-tables-serialization structures and prototypes */ /* %not-for-header */ /* %ok-for-header */ /* %not-for-header */ /* %tables-yydmap generated elements */ /* %endif */ /* end tables serialization structures and prototypes */ /* %ok-for-header */ /* Default declaration of generated scanner - a define so the user can * easily add parameters. */ #ifndef YY_DECL #define YY_DECL_IS_OURS 1 /* %if-c-only Standard (non-C++) definition */ extern int yylex (void); #define YY_DECL int yylex (void) /* %endif */ /* %if-c++-only C++ definition */ /* %endif */ #endif /* !YY_DECL */ /* Code executed at the beginning of each rule, after yytext and yyleng * have been set up. */ #ifndef YY_USER_ACTION #define YY_USER_ACTION #endif /* Code executed at the end of each rule. */ #ifndef YY_BREAK #define YY_BREAK /*LINTED*/break; #endif /* %% [6.0] YY_RULE_SETUP definition goes here */ #define YY_RULE_SETUP \ YY_USER_ACTION /* %not-for-header */ /** The main scanner function which does all the work. */ YY_DECL { yy_state_type yy_current_state; char *yy_cp, *yy_bp; int yy_act; if ( !(yy_init) ) { (yy_init) = 1; #ifdef YY_USER_INIT YY_USER_INIT; #endif if ( ! (yy_start) ) (yy_start) = 1; /* first start state */ if ( ! yyin ) /* %if-c-only */ yyin = stdin; /* %endif */ /* %if-c++-only */ /* %endif */ if ( ! yyout ) /* %if-c-only */ yyout = stdout; /* %endif */ /* %if-c++-only */ /* %endif */ if ( ! YY_CURRENT_BUFFER ) { yyensure_buffer_stack (); YY_CURRENT_BUFFER_LVALUE = yy_create_buffer( yyin, YY_BUF_SIZE ); } yy_load_buffer_state( ); } { /* %% [7.0] user's declarations go here */ #line 113 "VParseLex.l" #line 2673 "VParseLex_pretmp.cpp" while ( /*CONSTCOND*/1 ) /* loops until end-of-file is reached */ { /* %% [8.0] yymore()-related code goes here */ (yy_more_len) = 0; if ( (yy_more_flag) ) { (yy_more_len) = (int) ((yy_c_buf_p) - (yytext_ptr)); (yy_more_flag) = 0; } yy_cp = (yy_c_buf_p); /* Support of yytext. */ *yy_cp = (yy_hold_char); /* yy_bp points to the position in yy_ch_buf of the start of * the current run. */ yy_bp = yy_cp; /* %% [9.0] code to set up and find next match goes here */ yy_current_state = (yy_start); yy_match: do { YY_CHAR yy_c = yy_ec[YY_SC_TO_UI(*yy_cp)] ; if ( yy_accept[yy_current_state] ) { (yy_last_accepting_state) = yy_current_state; (yy_last_accepting_cpos) = yy_cp; } while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) { yy_current_state = (int) yy_def[yy_current_state]; if ( yy_current_state >= 2079 ) yy_c = yy_meta[yy_c]; } yy_current_state = yy_nxt[yy_base[yy_current_state] + yy_c]; ++yy_cp; } while ( yy_base[yy_current_state] != 3320 ); yy_find_action: /* %% [10.0] code to find the action number goes here */ yy_act = yy_accept[yy_current_state]; if ( yy_act == 0 ) { /* have to back up */ yy_cp = (yy_last_accepting_cpos); yy_current_state = (yy_last_accepting_state); yy_act = yy_accept[yy_current_state]; } YY_DO_BEFORE_ACTION; /* %% [11.0] code for yylineno update goes here */ do_action: /* This label is used only to access EOF actions. */ /* %% [12.0] debug code goes here */ if ( yy_flex_debug ) { if ( yy_act == 0 ) fprintf( stderr, "--scanner backing up\n" ); else if ( yy_act < 422 ) fprintf( stderr, "--accepting rule at line %ld (\"%s\")\n", (long)yy_rule_linenum[yy_act], yytext ); else if ( yy_act == 422 ) fprintf( stderr, "--accepting default rule (\"%s\")\n", yytext ); else if ( yy_act == 423 ) fprintf( stderr, "--(end of buffer or a NUL)\n" ); else fprintf( stderr, "--EOF (start condition %d)\n", YY_START ); } switch ( yy_act ) { /* beginning of action switch */ /* %% [13.0] actions go here */ case 0: /* must back up */ /* undo the effects of YY_DO_BEFORE_ACTION */ *yy_cp = (yy_hold_char); yy_cp = (yy_last_accepting_cpos); yy_current_state = (yy_last_accepting_state); goto yy_find_action; case 1: /* rule 1 can match eol */ YY_RULE_SETUP #line 115 "VParseLex.l" {BEGIN STATE_VERILOG_RECENT; yyless(0); } YY_BREAK /* Verilog 1995 */ case 2: YY_RULE_SETUP #line 119 "VParseLex.l" { StashPrefix; } /* otherwise ignore white-space */ YY_BREAK case 3: /* rule 3 can match eol */ YY_RULE_SETUP #line 120 "VParseLex.l" { StashPrefix; NEXTLINE(); } /* Count line numbers */ YY_BREAK /* Keywords */ case 4: YY_RULE_SETUP #line 122 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yALWAYS; } YY_BREAK case 5: YY_RULE_SETUP #line 123 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yAND; } YY_BREAK case 6: YY_RULE_SETUP #line 124 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yASSIGN; } YY_BREAK case 7: YY_RULE_SETUP #line 125 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yBEGIN; } YY_BREAK case 8: YY_RULE_SETUP #line 126 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yBUF; } YY_BREAK case 9: YY_RULE_SETUP #line 127 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yCASE; } YY_BREAK case 10: YY_RULE_SETUP #line 128 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yCASEX; } YY_BREAK case 11: YY_RULE_SETUP #line 129 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yCASEZ; } YY_BREAK case 12: YY_RULE_SETUP #line 130 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yDEASSIGN; } YY_BREAK case 13: YY_RULE_SETUP #line 131 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yDEFAULT; } YY_BREAK case 14: YY_RULE_SETUP #line 132 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yDEFPARAM; } YY_BREAK case 15: YY_RULE_SETUP #line 133 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yDISABLE; } YY_BREAK case 16: YY_RULE_SETUP #line 134 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yEDGE; } YY_BREAK case 17: YY_RULE_SETUP #line 135 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yELSE; } YY_BREAK case 18: YY_RULE_SETUP #line 136 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yEND; } YY_BREAK case 19: YY_RULE_SETUP #line 137 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yENDCASE; } YY_BREAK case 20: YY_RULE_SETUP #line 138 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yENDFUNCTION; } YY_BREAK case 21: YY_RULE_SETUP #line 139 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yENDMODULE; } YY_BREAK case 22: YY_RULE_SETUP #line 140 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yENDMODULE; } YY_BREAK case 23: YY_RULE_SETUP #line 141 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yENDSPECIFY; } YY_BREAK case 24: YY_RULE_SETUP #line 142 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yENDTABLE; } YY_BREAK case 25: YY_RULE_SETUP #line 143 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yENDTASK; } YY_BREAK case 26: YY_RULE_SETUP #line 144 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yEVENT; } YY_BREAK case 27: YY_RULE_SETUP #line 145 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yFOR; } YY_BREAK case 28: YY_RULE_SETUP #line 146 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yFORCE; } YY_BREAK case 29: YY_RULE_SETUP #line 147 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yFOREVER; } YY_BREAK case 30: YY_RULE_SETUP #line 148 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yFORK; } YY_BREAK case 31: YY_RULE_SETUP #line 149 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yFUNCTION__LEX; } YY_BREAK case 32: YY_RULE_SETUP #line 150 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yIF; } YY_BREAK case 33: YY_RULE_SETUP #line 151 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yINITIAL; } YY_BREAK case 34: YY_RULE_SETUP #line 152 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yINOUT; } YY_BREAK case 35: YY_RULE_SETUP #line 153 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yINPUT; } YY_BREAK case 36: YY_RULE_SETUP #line 154 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yINTEGER; } YY_BREAK case 37: YY_RULE_SETUP #line 155 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yJOIN; } YY_BREAK case 38: YY_RULE_SETUP #line 156 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yMODULE; } YY_BREAK case 39: YY_RULE_SETUP #line 157 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yMODULE; } YY_BREAK case 40: YY_RULE_SETUP #line 158 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yNAND; } YY_BREAK case 41: YY_RULE_SETUP #line 159 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yNEGEDGE; } YY_BREAK case 42: YY_RULE_SETUP #line 160 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yNOR; } YY_BREAK case 43: YY_RULE_SETUP #line 161 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yNOT; } YY_BREAK case 44: YY_RULE_SETUP #line 162 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yOR; } YY_BREAK case 45: YY_RULE_SETUP #line 163 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yOUTPUT; } YY_BREAK case 46: YY_RULE_SETUP #line 164 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yPARAMETER; } YY_BREAK case 47: YY_RULE_SETUP #line 165 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yPOSEDGE; } YY_BREAK case 48: YY_RULE_SETUP #line 166 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yMODULE; } YY_BREAK case 49: YY_RULE_SETUP #line 167 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yREAL; } YY_BREAK case 50: YY_RULE_SETUP #line 168 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yREALTIME; } YY_BREAK case 51: YY_RULE_SETUP #line 169 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yREG; } YY_BREAK case 52: YY_RULE_SETUP #line 170 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yRELEASE; } YY_BREAK case 53: YY_RULE_SETUP #line 171 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yREPEAT; } YY_BREAK case 54: YY_RULE_SETUP #line 172 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return ySCALARED; } YY_BREAK case 55: YY_RULE_SETUP #line 173 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return ySPECIFY; } YY_BREAK case 56: YY_RULE_SETUP #line 174 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return ySPECPARAM; } YY_BREAK case 57: YY_RULE_SETUP #line 175 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return ySUPPLY0; } YY_BREAK case 58: YY_RULE_SETUP #line 176 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return ySUPPLY1; } YY_BREAK case 59: YY_RULE_SETUP #line 177 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yTABLE; } YY_BREAK case 60: YY_RULE_SETUP #line 178 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yTASK__LEX; } YY_BREAK case 61: YY_RULE_SETUP #line 179 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yTIME; } YY_BREAK case 62: YY_RULE_SETUP #line 180 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yTRI; } YY_BREAK case 63: YY_RULE_SETUP #line 181 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yTRI0; } YY_BREAK case 64: YY_RULE_SETUP #line 182 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yTRI1; } YY_BREAK case 65: YY_RULE_SETUP #line 183 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yTRIAND; } YY_BREAK case 66: YY_RULE_SETUP #line 184 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yTRIOR; } YY_BREAK case 67: YY_RULE_SETUP #line 185 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yTRIREG; } YY_BREAK case 68: YY_RULE_SETUP #line 186 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yVECTORED; } YY_BREAK case 69: YY_RULE_SETUP #line 187 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yWAIT; } YY_BREAK case 70: YY_RULE_SETUP #line 188 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yWAND; } YY_BREAK case 71: YY_RULE_SETUP #line 189 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yWHILE; } YY_BREAK case 72: YY_RULE_SETUP #line 190 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yWIRE; } YY_BREAK case 73: YY_RULE_SETUP #line 191 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yWOR; } YY_BREAK case 74: YY_RULE_SETUP #line 192 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yXNOR; } YY_BREAK case 75: YY_RULE_SETUP #line 193 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yXOR; } YY_BREAK /* Types Verilator doesn't support but we do generically here */ case 76: YY_RULE_SETUP #line 195 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return ygenGATE; } YY_BREAK case 77: YY_RULE_SETUP #line 196 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return ygenGATE; } YY_BREAK case 78: YY_RULE_SETUP #line 197 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return ygenGATE; } YY_BREAK case 79: YY_RULE_SETUP #line 198 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return ygenSTRENGTH; } YY_BREAK case 80: YY_RULE_SETUP #line 199 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return ygenSTRENGTH; } YY_BREAK case 81: YY_RULE_SETUP #line 200 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return ygenSTRENGTH; } YY_BREAK case 82: YY_RULE_SETUP #line 201 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return ygenSTRENGTH; } YY_BREAK case 83: YY_RULE_SETUP #line 202 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return ygenGATE; } YY_BREAK case 84: YY_RULE_SETUP #line 203 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return ygenGATE; } YY_BREAK case 85: YY_RULE_SETUP #line 204 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return ygenGATE; } YY_BREAK case 86: YY_RULE_SETUP #line 205 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return ygenGATE; } YY_BREAK case 87: YY_RULE_SETUP #line 206 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return ygenSTRENGTH; } YY_BREAK case 88: YY_RULE_SETUP #line 207 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return ygenSTRENGTH; } YY_BREAK case 89: YY_RULE_SETUP #line 208 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return ygenGATE; } YY_BREAK case 90: YY_RULE_SETUP #line 209 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return ygenGATE; } YY_BREAK case 91: YY_RULE_SETUP #line 210 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return ygenGATE; } YY_BREAK case 92: YY_RULE_SETUP #line 211 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return ygenGATE; } YY_BREAK case 93: YY_RULE_SETUP #line 212 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return ygenGATE; } YY_BREAK case 94: YY_RULE_SETUP #line 213 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return ygenGATE; } YY_BREAK case 95: YY_RULE_SETUP #line 214 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return ygenGATE; } YY_BREAK case 96: YY_RULE_SETUP #line 215 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return ygenGATE; } YY_BREAK case 97: YY_RULE_SETUP #line 216 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return ygenSTRENGTH; } YY_BREAK case 98: YY_RULE_SETUP #line 217 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return ygenSTRENGTH; } YY_BREAK case 99: YY_RULE_SETUP #line 218 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return ygenSTRENGTH; } YY_BREAK case 100: YY_RULE_SETUP #line 219 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return ygenGATE; } YY_BREAK case 101: YY_RULE_SETUP #line 220 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return ygenGATE; } YY_BREAK case 102: YY_RULE_SETUP #line 221 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return ygenGATE; } YY_BREAK case 103: YY_RULE_SETUP #line 222 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return ygenSTRENGTH; } YY_BREAK case 104: YY_RULE_SETUP #line 223 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return ygenSTRENGTH; } YY_BREAK /* Generic unsupported warnings */ /* Verilog 2001 */ /* Keywords*/ case 105: YY_RULE_SETUP #line 230 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yAUTOMATIC; } YY_BREAK case 106: YY_RULE_SETUP #line 231 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yENDGENERATE; } YY_BREAK case 107: YY_RULE_SETUP #line 232 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yGENERATE; } YY_BREAK case 108: YY_RULE_SETUP #line 233 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yGENVAR; } YY_BREAK case 109: YY_RULE_SETUP #line 234 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yaTIMINGSPEC; } YY_BREAK case 110: YY_RULE_SETUP #line 235 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yLOCALPARAM; } YY_BREAK case 111: YY_RULE_SETUP #line 236 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yaTIMINGSPEC; } YY_BREAK case 112: YY_RULE_SETUP #line 237 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yaTIMINGSPEC; } YY_BREAK case 113: YY_RULE_SETUP #line 238 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yaTIMINGSPEC; } YY_BREAK case 114: YY_RULE_SETUP #line 239 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yaTIMINGSPEC; } YY_BREAK case 115: YY_RULE_SETUP #line 240 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return ySIGNED; } YY_BREAK case 116: YY_RULE_SETUP #line 241 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yUNSIGNED; } YY_BREAK /* Generic unsupported keywords */ case 117: YY_RULE_SETUP #line 243 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return ygenCONFIGKEYWORD; } YY_BREAK case 118: YY_RULE_SETUP #line 244 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return ygenCONFIGKEYWORD; } YY_BREAK case 119: YY_RULE_SETUP #line 245 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return ygenCONFIGKEYWORD; } YY_BREAK case 120: YY_RULE_SETUP #line 246 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return ygenCONFIGKEYWORD; } YY_BREAK case 121: YY_RULE_SETUP #line 247 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return ygenCONFIGKEYWORD; } YY_BREAK case 122: YY_RULE_SETUP #line 248 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return ygenCONFIGKEYWORD; } YY_BREAK case 123: YY_RULE_SETUP #line 249 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return ygenCONFIGKEYWORD; } YY_BREAK case 124: YY_RULE_SETUP #line 250 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return ygenCONFIGKEYWORD; } YY_BREAK case 125: YY_RULE_SETUP #line 251 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return ygenCONFIGKEYWORD; } YY_BREAK case 126: YY_RULE_SETUP #line 252 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return ygenCONFIGKEYWORD; } YY_BREAK /* Verilog 2005 */ /* Keywords */ case 127: YY_RULE_SETUP #line 258 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yWIRE; } YY_BREAK /* System Verilog 2005 */ /* System Tasks */ case 128: YY_RULE_SETUP #line 264 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yD_ERROR; } YY_BREAK case 129: YY_RULE_SETUP #line 265 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yD_FATAL; } YY_BREAK case 130: YY_RULE_SETUP #line 266 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yD_INFO; } YY_BREAK case 131: YY_RULE_SETUP #line 267 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yD_ROOT; } YY_BREAK case 132: YY_RULE_SETUP #line 268 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yD_UNIT; } YY_BREAK case 133: YY_RULE_SETUP #line 269 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yD_WARNING; } YY_BREAK /* Keywords */ case 134: YY_RULE_SETUP #line 271 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yALIAS; } YY_BREAK case 135: YY_RULE_SETUP #line 272 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yALWAYS; } YY_BREAK case 136: YY_RULE_SETUP #line 273 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yALWAYS; } YY_BREAK case 137: YY_RULE_SETUP #line 274 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yALWAYS; } YY_BREAK case 138: YY_RULE_SETUP #line 275 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yASSERT; } YY_BREAK case 139: YY_RULE_SETUP #line 276 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yASSUME; } YY_BREAK case 140: YY_RULE_SETUP #line 277 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yBEFORE; } YY_BREAK case 141: YY_RULE_SETUP #line 278 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yBIND; } YY_BREAK case 142: YY_RULE_SETUP #line 279 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yBINS; } YY_BREAK case 143: YY_RULE_SETUP #line 280 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yBINSOF; } YY_BREAK case 144: YY_RULE_SETUP #line 281 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yBIT; } YY_BREAK case 145: YY_RULE_SETUP #line 282 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yBREAK; } YY_BREAK case 146: YY_RULE_SETUP #line 283 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yBYTE; } YY_BREAK case 147: YY_RULE_SETUP #line 284 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yCHANDLE; } YY_BREAK case 148: YY_RULE_SETUP #line 285 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yCLASS; } YY_BREAK case 149: YY_RULE_SETUP #line 286 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yCLOCKING; } YY_BREAK case 150: YY_RULE_SETUP #line 287 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yCONST__LEX; } YY_BREAK case 151: YY_RULE_SETUP #line 288 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yCONSTRAINT; } YY_BREAK case 152: YY_RULE_SETUP #line 289 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yCONTEXT; } YY_BREAK case 153: YY_RULE_SETUP #line 290 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yCONTINUE; } YY_BREAK case 154: YY_RULE_SETUP #line 291 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yCOVER; } YY_BREAK case 155: YY_RULE_SETUP #line 292 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yCOVERGROUP; } YY_BREAK case 156: YY_RULE_SETUP #line 293 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yCOVERPOINT; } YY_BREAK case 157: YY_RULE_SETUP #line 294 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yCROSS; } YY_BREAK case 158: YY_RULE_SETUP #line 295 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yDIST; } YY_BREAK case 159: YY_RULE_SETUP #line 296 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yDO; } YY_BREAK case 160: YY_RULE_SETUP #line 297 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yENDCLASS; } YY_BREAK case 161: YY_RULE_SETUP #line 298 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yENDCLOCKING; } YY_BREAK case 162: YY_RULE_SETUP #line 299 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yENDGROUP; } YY_BREAK case 163: YY_RULE_SETUP #line 300 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yENDINTERFACE; } YY_BREAK case 164: YY_RULE_SETUP #line 301 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yENDPACKAGE; } YY_BREAK case 165: YY_RULE_SETUP #line 302 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yENDPROGRAM; } YY_BREAK case 166: YY_RULE_SETUP #line 303 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yENDPROPERTY; } YY_BREAK case 167: YY_RULE_SETUP #line 304 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yENDSEQUENCE; } YY_BREAK case 168: YY_RULE_SETUP #line 305 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yENUM; } YY_BREAK case 169: YY_RULE_SETUP #line 306 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yEXPECT; } YY_BREAK case 170: YY_RULE_SETUP #line 307 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yEXPORT; } YY_BREAK case 171: YY_RULE_SETUP #line 308 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yEXTENDS; } YY_BREAK case 172: YY_RULE_SETUP #line 309 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yEXTERN; } YY_BREAK case 173: YY_RULE_SETUP #line 310 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yFINAL; } YY_BREAK case 174: YY_RULE_SETUP #line 311 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yFIRST_MATCH; } YY_BREAK case 175: YY_RULE_SETUP #line 312 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yFOREACH; } YY_BREAK case 176: YY_RULE_SETUP #line 313 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yFORKJOIN; } YY_BREAK case 177: YY_RULE_SETUP #line 314 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yIFF; } YY_BREAK case 178: YY_RULE_SETUP #line 315 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yIGNORE_BINS; } YY_BREAK case 179: YY_RULE_SETUP #line 316 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yILLEGAL_BINS; } YY_BREAK case 180: YY_RULE_SETUP #line 317 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yIMPORT; } YY_BREAK case 181: YY_RULE_SETUP #line 318 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yINSIDE; } YY_BREAK case 182: YY_RULE_SETUP #line 319 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yINT; } YY_BREAK case 183: YY_RULE_SETUP #line 320 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yINTERFACE; } YY_BREAK case 184: YY_RULE_SETUP #line 321 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yINTERSECT; } YY_BREAK case 185: YY_RULE_SETUP #line 322 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yJOIN; } YY_BREAK case 186: YY_RULE_SETUP #line 323 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yJOIN; } YY_BREAK case 187: YY_RULE_SETUP #line 324 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yLOCAL__LEX; } YY_BREAK case 188: YY_RULE_SETUP #line 325 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yLOGIC; } YY_BREAK case 189: YY_RULE_SETUP #line 326 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yLONGINT; } YY_BREAK case 190: YY_RULE_SETUP #line 327 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yMATCHES; } YY_BREAK case 191: YY_RULE_SETUP #line 328 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yMODPORT; } YY_BREAK case 192: YY_RULE_SETUP #line 329 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yNEW__LEX; } YY_BREAK case 193: YY_RULE_SETUP #line 330 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yNULL; } YY_BREAK case 194: YY_RULE_SETUP #line 331 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yPACKAGE; } YY_BREAK case 195: YY_RULE_SETUP #line 332 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yPACKED; } YY_BREAK case 196: YY_RULE_SETUP #line 333 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yPRIORITY; } YY_BREAK case 197: YY_RULE_SETUP #line 334 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yPROGRAM; } YY_BREAK case 198: YY_RULE_SETUP #line 335 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yPROPERTY; } YY_BREAK case 199: YY_RULE_SETUP #line 336 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yPROTECTED; } YY_BREAK case 200: YY_RULE_SETUP #line 337 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yPURE; } YY_BREAK case 201: YY_RULE_SETUP #line 338 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yRAND; } YY_BREAK case 202: YY_RULE_SETUP #line 339 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yRANDC; } YY_BREAK case 203: YY_RULE_SETUP #line 340 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yRANDCASE; } YY_BREAK case 204: YY_RULE_SETUP #line 341 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yRANDSEQUENCE; } YY_BREAK case 205: YY_RULE_SETUP #line 342 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yREF; } YY_BREAK case 206: YY_RULE_SETUP #line 343 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yRETURN; } YY_BREAK case 207: YY_RULE_SETUP #line 344 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return ySEQUENCE; } YY_BREAK case 208: YY_RULE_SETUP #line 345 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return ySHORTINT; } YY_BREAK case 209: YY_RULE_SETUP #line 346 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return ySHORTREAL; } YY_BREAK case 210: YY_RULE_SETUP #line 347 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return ySOLVE; } YY_BREAK case 211: YY_RULE_SETUP #line 348 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return ySTATIC__LEX; } YY_BREAK case 212: YY_RULE_SETUP #line 349 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return ySTRING; } YY_BREAK case 213: YY_RULE_SETUP #line 350 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return ySTRUCT; } YY_BREAK case 214: YY_RULE_SETUP #line 351 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return ySUPER; } YY_BREAK case 215: YY_RULE_SETUP #line 352 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yTAGGED; } YY_BREAK case 216: YY_RULE_SETUP #line 353 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yTHIS; } YY_BREAK case 217: YY_RULE_SETUP #line 354 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yTHROUGHOUT; } YY_BREAK case 218: YY_RULE_SETUP #line 355 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yTIMEPRECISION; } YY_BREAK case 219: YY_RULE_SETUP #line 356 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yTIMEUNIT; } YY_BREAK case 220: YY_RULE_SETUP #line 357 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yTYPE; } YY_BREAK case 221: YY_RULE_SETUP #line 358 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yTYPEDEF; } YY_BREAK case 222: YY_RULE_SETUP #line 359 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yUNION; } YY_BREAK case 223: YY_RULE_SETUP #line 360 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yUNIQUE; } YY_BREAK case 224: YY_RULE_SETUP #line 361 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yVAR; } YY_BREAK case 225: YY_RULE_SETUP #line 362 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yVIRTUAL__LEX; } YY_BREAK case 226: YY_RULE_SETUP #line 363 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yVOID; } YY_BREAK case 227: YY_RULE_SETUP #line 364 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yWAIT_ORDER; } YY_BREAK case 228: YY_RULE_SETUP #line 365 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yWILDCARD; } YY_BREAK case 229: YY_RULE_SETUP #line 366 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yWITH__LEX; } YY_BREAK case 230: YY_RULE_SETUP #line 367 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yWITHIN; } YY_BREAK /* System Verilog 2009 */ /* Keywords */ case 231: YY_RULE_SETUP #line 373 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yACCEPT_ON; } YY_BREAK case 232: YY_RULE_SETUP #line 374 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yCHECKER; } YY_BREAK case 233: YY_RULE_SETUP #line 375 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yENDCHECKER; } YY_BREAK case 234: YY_RULE_SETUP #line 376 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yEVENTUALLY; } YY_BREAK case 235: YY_RULE_SETUP #line 377 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yGLOBAL__LEX; } YY_BREAK case 236: YY_RULE_SETUP #line 378 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yIMPLIES; } YY_BREAK case 237: YY_RULE_SETUP #line 379 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yLET; } YY_BREAK case 238: YY_RULE_SETUP #line 380 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yNEXTTIME; } YY_BREAK case 239: YY_RULE_SETUP #line 381 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yREJECT_ON; } YY_BREAK case 240: YY_RULE_SETUP #line 382 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yRESTRICT; } YY_BREAK case 241: YY_RULE_SETUP #line 383 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yS_ALWAYS; } YY_BREAK case 242: YY_RULE_SETUP #line 384 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yS_EVENTUALLY; } YY_BREAK case 243: YY_RULE_SETUP #line 385 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yS_NEXTTIME; } YY_BREAK case 244: YY_RULE_SETUP #line 386 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yS_UNTIL; } YY_BREAK case 245: YY_RULE_SETUP #line 387 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yS_UNTIL_WITH; } YY_BREAK case 246: YY_RULE_SETUP #line 388 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return ySTRONG; } YY_BREAK case 247: YY_RULE_SETUP #line 389 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return ySYNC_ACCEPT_ON; } YY_BREAK case 248: YY_RULE_SETUP #line 390 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return ySYNC_REJECT_ON; } YY_BREAK case 249: YY_RULE_SETUP #line 391 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yUNIQUE0; } YY_BREAK case 250: YY_RULE_SETUP #line 392 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yUNTIL; } YY_BREAK case 251: YY_RULE_SETUP #line 393 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yUNTIL_WITH; } YY_BREAK case 252: YY_RULE_SETUP #line 394 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yUNTYPED; } YY_BREAK case 253: YY_RULE_SETUP #line 395 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yWEAK; } YY_BREAK /* System Verilog 2012 */ /* Keywords */ case 254: YY_RULE_SETUP #line 401 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yIMPLEMENTS; } YY_BREAK case 255: YY_RULE_SETUP #line 402 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yINTERCONNECT; } YY_BREAK case 256: YY_RULE_SETUP #line 403 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return yNETTYPE; } YY_BREAK case 257: YY_RULE_SETUP #line 404 "VParseLex.l" { FL; VALTEXT; CALLBACK(keywordCb); return ySOFT; } YY_BREAK /* System Verilog 2017 */ /* No new keywords */ /* Default PLI rule */ case 258: YY_RULE_SETUP #line 412 "VParseLex.l" { FL; VALTEXT; CALLBACK(sysfuncCb); return ygenSYSCALL; } YY_BREAK /************************************************************************/ /* Single character operator thingies */ case 259: YY_RULE_SETUP #line 419 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yytext[0]; } YY_BREAK case 260: YY_RULE_SETUP #line 420 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yytext[0]; } YY_BREAK case 261: YY_RULE_SETUP #line 423 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yytext[0]; } YY_BREAK case 262: YY_RULE_SETUP #line 424 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yytext[0]; } YY_BREAK case 263: YY_RULE_SETUP #line 425 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yytext[0]; } YY_BREAK case 264: YY_RULE_SETUP #line 426 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yytext[0]; } YY_BREAK case 265: YY_RULE_SETUP #line 427 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yytext[0]; } YY_BREAK case 266: YY_RULE_SETUP #line 428 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yytext[0]; } YY_BREAK case 267: YY_RULE_SETUP #line 429 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yytext[0]; } YY_BREAK case 268: YY_RULE_SETUP #line 430 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yytext[0]; } YY_BREAK case 269: YY_RULE_SETUP #line 431 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yytext[0]; } YY_BREAK case 270: YY_RULE_SETUP #line 432 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yytext[0]; } YY_BREAK case 271: YY_RULE_SETUP #line 433 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yytext[0]; } YY_BREAK case 272: YY_RULE_SETUP #line 434 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yytext[0]; } YY_BREAK case 273: YY_RULE_SETUP #line 435 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yytext[0]; } YY_BREAK case 274: YY_RULE_SETUP #line 436 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yytext[0]; } YY_BREAK case 275: YY_RULE_SETUP #line 437 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yytext[0]; } YY_BREAK case 276: YY_RULE_SETUP #line 438 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yytext[0]; } YY_BREAK case 277: YY_RULE_SETUP #line 439 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yytext[0]; } YY_BREAK case 278: YY_RULE_SETUP #line 440 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yytext[0]; } YY_BREAK case 279: YY_RULE_SETUP #line 441 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yytext[0]; } YY_BREAK case 280: YY_RULE_SETUP #line 442 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yytext[0]; } YY_BREAK case 281: YY_RULE_SETUP #line 443 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yytext[0]; } YY_BREAK case 282: YY_RULE_SETUP #line 444 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yytext[0]; } YY_BREAK case 283: YY_RULE_SETUP #line 445 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yytext[0]; } YY_BREAK case 284: YY_RULE_SETUP #line 446 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yytext[0]; } YY_BREAK case 285: YY_RULE_SETUP #line 447 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yytext[0]; } YY_BREAK /************************************************************************/ /* Operators and multi-character symbols */ /* Verilog 1995 Operators */ case 286: YY_RULE_SETUP #line 455 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yP_ANDAND; } YY_BREAK case 287: YY_RULE_SETUP #line 456 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yP_OROR; } YY_BREAK case 288: YY_RULE_SETUP #line 457 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yP_LTE; } YY_BREAK case 289: YY_RULE_SETUP #line 458 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yP_GTE; } YY_BREAK case 290: YY_RULE_SETUP #line 459 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yP_SLEFT; } YY_BREAK case 291: YY_RULE_SETUP #line 460 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yP_SRIGHT; } YY_BREAK case 292: YY_RULE_SETUP #line 461 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yP_EQUAL; } YY_BREAK case 293: YY_RULE_SETUP #line 462 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yP_NOTEQUAL; } YY_BREAK case 294: YY_RULE_SETUP #line 463 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yP_CASEEQUAL; } YY_BREAK case 295: YY_RULE_SETUP #line 464 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yP_CASENOTEQUAL; } YY_BREAK case 296: YY_RULE_SETUP #line 465 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yP_XNOR; } YY_BREAK case 297: YY_RULE_SETUP #line 466 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yP_XNOR; } YY_BREAK case 298: YY_RULE_SETUP #line 467 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yP_NAND; } YY_BREAK case 299: YY_RULE_SETUP #line 468 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yP_NOR; } YY_BREAK case 300: YY_RULE_SETUP #line 469 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yP_MINUSGT; } YY_BREAK case 301: YY_RULE_SETUP #line 470 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yP_EQGT; } YY_BREAK case 302: YY_RULE_SETUP #line 471 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yP_ASTGT; } YY_BREAK case 303: YY_RULE_SETUP #line 472 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yP_ANDANDAND; } YY_BREAK /* Verilog 2001 Operators */ case 304: YY_RULE_SETUP #line 477 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yP_SLEFT; } YY_BREAK case 305: YY_RULE_SETUP #line 478 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yP_SSRIGHT; } YY_BREAK case 306: YY_RULE_SETUP #line 479 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yP_POW; } YY_BREAK case 307: YY_RULE_SETUP #line 480 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yP_PLUSCOLON; } YY_BREAK case 308: YY_RULE_SETUP #line 481 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yP_MINUSCOLON; } YY_BREAK case 309: YY_RULE_SETUP #line 482 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yP_DOTSTAR; } YY_BREAK /* SystemVerilog 2005 Operators */ case 310: YY_RULE_SETUP #line 487 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yP_TICK; } YY_BREAK case 311: YY_RULE_SETUP #line 488 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yP_TICKBRA; } YY_BREAK case 312: YY_RULE_SETUP #line 489 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yP_WILDEQUAL; } YY_BREAK case 313: YY_RULE_SETUP #line 490 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yP_WILDNOTEQUAL; } YY_BREAK case 314: YY_RULE_SETUP #line 491 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yP_PLUSPLUS; } YY_BREAK case 315: YY_RULE_SETUP #line 492 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yP_MINUSMINUS; } YY_BREAK case 316: YY_RULE_SETUP #line 493 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yP_PLUSEQ; } YY_BREAK case 317: YY_RULE_SETUP #line 494 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yP_MINUSEQ; } YY_BREAK case 318: YY_RULE_SETUP #line 495 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yP_TIMESEQ; } YY_BREAK case 319: YY_RULE_SETUP #line 496 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yP_DIVEQ; } YY_BREAK case 320: YY_RULE_SETUP #line 497 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yP_MODEQ; } YY_BREAK case 321: YY_RULE_SETUP #line 498 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yP_ANDEQ; } YY_BREAK case 322: YY_RULE_SETUP #line 499 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yP_OREQ; } YY_BREAK case 323: YY_RULE_SETUP #line 500 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yP_XOREQ; } YY_BREAK case 324: YY_RULE_SETUP #line 501 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yP_SLEFTEQ; } YY_BREAK case 325: YY_RULE_SETUP #line 502 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yP_SRIGHTEQ; } YY_BREAK case 326: YY_RULE_SETUP #line 503 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yP_SLEFTEQ; } YY_BREAK case 327: YY_RULE_SETUP #line 504 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yP_SSRIGHTEQ; } YY_BREAK case 328: YY_RULE_SETUP #line 505 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yP_MINUSGTGT; } YY_BREAK case 329: YY_RULE_SETUP #line 506 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yP_POUNDPOUND; } YY_BREAK case 330: YY_RULE_SETUP #line 507 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yP_ATAT; } YY_BREAK case 331: YY_RULE_SETUP #line 508 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yP_COLONCOLON; } YY_BREAK case 332: YY_RULE_SETUP #line 509 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yP_COLONEQ; } YY_BREAK case 333: /* rule 333 can match eol */ YY_RULE_SETUP #line 510 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yP_COLONDIV; } /* : then comment is not ":/" */ YY_BREAK case 334: YY_RULE_SETUP #line 511 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yP_ORMINUSGT; } YY_BREAK case 335: YY_RULE_SETUP #line 512 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yP_OREQGT; } YY_BREAK /* Some simulators allow whitespace here. Grr */ case 336: YY_RULE_SETUP #line 514 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yP_BRASTAR; } YY_BREAK case 337: YY_RULE_SETUP #line 515 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yP_BRAEQ; } YY_BREAK case 338: YY_RULE_SETUP #line 516 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yP_BRAMINUSGT; } YY_BREAK case 339: YY_RULE_SETUP #line 517 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yP_BRAPLUSKET; } YY_BREAK /* SystemVerilog 2009 Operators */ case 340: YY_RULE_SETUP #line 522 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return yP_LTMINUSGT; } YY_BREAK /* Identifiers and numbers */ /* Consume a following space, as we're going to add one to the symbol, we'd like to avoid inserting an extra */ case 341: YY_RULE_SETUP #line 528 "VParseLex.l" { if (VParseLex::symEscapeless(yytext+1,yyleng-1-1)) { string sym = string(yytext+1,yyleng-1-1); FL; CALLBACKS(symbolCb, sym); VALTEXTS(sym); unput(' '); } else { string sym = string(yytext,yyleng-1) + ' '; FL; CALLBACKS(symbolCb, sym); VALTEXTS(sym); } return yaID__LEX; } YY_BREAK case 342: YY_RULE_SETUP #line 536 "VParseLex.l" { if (VParseLex::symEscapeless(yytext+1,yyleng-1)) { string sym = string(yytext+1,yyleng-1); FL; CALLBACKS(symbolCb, sym); VALTEXTS(sym); } else { string sym = string(yytext,yyleng) + ' '; FL; CALLBACKS(symbolCb, sym); VALTEXTS(sym); } return yaID__LEX; } YY_BREAK case 343: YY_RULE_SETUP #line 544 "VParseLex.l" { FL; VALTEXT; CALLBACK(symbolCb); return yaID__LEX; } YY_BREAK case 344: /* rule 344 can match eol */ YY_RULE_SETUP #line 545 "VParseLex.l" { FL; VALTEXT; CALLBACK(stringCb); return yaSTRING; } YY_BREAK case 345: YY_RULE_SETUP #line 547 "VParseLex.l" { yy_push_state(STRING); yymore(); } YY_BREAK case 346: /* rule 346 can match eol */ YY_RULE_SETUP #line 549 "VParseLex.l" { /* "# 1'b0" is a delay value so must lex as "#" "1" "'b0" */ if (LEXP->prevLexToken()=='#') { int shortlen = 0; while (isdigit(yytext[shortlen])) shortlen++; if (shortlen) { // Return is stuff before ' VALTEXTS(string(yytext,shortlen)); // Push rest for later parse LEXP->unputString(yytext+shortlen, yyleng-shortlen); FL; LINECHECKS(yytext,shortlen); CALLBACKS(numberCb,string(yytext,shortlen)); return yaINTNUM; } } FL; VALTEXT; LINECHECK(); CALLBACK(numberCb); return yaINTNUM; } YY_BREAK case 347: YY_RULE_SETUP #line 564 "VParseLex.l" { FL; VALTEXT; CALLBACK(numberCb); return yaINTNUM; } YY_BREAK case 348: YY_RULE_SETUP #line 567 "VParseLex.l" { FL; VALTEXT; CALLBACK(numberCb); return yaFLOATNUM; } YY_BREAK case 349: YY_RULE_SETUP #line 570 "VParseLex.l" { FL; VALTEXT; CALLBACK(numberCb); return yaFLOATNUM; } YY_BREAK case 350: YY_RULE_SETUP #line 573 "VParseLex.l" { FL; VALTEXT; CALLBACK(numberCb); return yaTIMENUM; } YY_BREAK /************************************************************************/ /* STRINGS */ case YY_STATE_EOF(STRING): #line 580 "VParseLex.l" { yyerrorf("EOF in unterminated string"); yyleng = 0; yy_pop_state(); } YY_BREAK case 351: /* rule 351 can match eol */ YY_RULE_SETUP #line 581 "VParseLex.l" { yyerrorf("Unterminated string"); NEXTLINE(); } YY_BREAK case 352: /* rule 352 can match eol */ YY_RULE_SETUP #line 582 "VParseLex.l" { yymore(); NEXTLINE(); } YY_BREAK case 353: YY_RULE_SETUP #line 583 "VParseLex.l" { yymore(); } YY_BREAK case 354: YY_RULE_SETUP #line 584 "VParseLex.l" { yy_pop_state(); FL; VALTEXT; CALLBACK(stringCb); return yaSTRING; } YY_BREAK case 355: YY_RULE_SETUP #line 586 "VParseLex.l" { yymore(); } YY_BREAK case 356: YY_RULE_SETUP #line 587 "VParseLex.l" { yymore(); } YY_BREAK /************************************************************************/ /* Multi-line COMMENTS */ case 357: YY_RULE_SETUP #line 591 "VParseLex.l" { yymore(); } YY_BREAK case 358: /* rule 358 can match eol */ YY_RULE_SETUP #line 592 "VParseLex.l" { yymore(); NEXTLINE(); } YY_BREAK case 359: YY_RULE_SETUP #line 593 "VParseLex.l" { VALTEXT; CALLBACK(commentCb); yy_pop_state(); } /* No FL; it's at comment begin */ YY_BREAK case 360: YY_RULE_SETUP #line 594 "VParseLex.l" { yymore(); } YY_BREAK case 361: YY_RULE_SETUP #line 595 "VParseLex.l" { yymore(); } YY_BREAK case YY_STATE_EOF(CMTMODE): #line 596 "VParseLex.l" { yyerrorf("EOF in '/* ... */' block comment"); yyleng = 0; yy_pop_state(); } YY_BREAK /************************************************************************/ /* Protected */ case 362: /* rule 362 can match eol */ YY_RULE_SETUP #line 601 "VParseLex.l" { if (LPARSEP->useProtected()) yymore(); NEXTLINE(); } YY_BREAK case 363: YY_RULE_SETUP #line 602 "VParseLex.l" { FL; VALTEXT; CALLBACK(preprocCb); yy_pop_state(); } YY_BREAK case 364: YY_RULE_SETUP #line 603 "VParseLex.l" { FL; VALTEXT; CALLBACK(preprocCb); yy_pop_state(); } YY_BREAK case 365: YY_RULE_SETUP #line 604 "VParseLex.l" { FL; VALTEXT; CALLBACK(preprocCb); yy_pop_state(); } YY_BREAK case 366: YY_RULE_SETUP #line 606 "VParseLex.l" { if (LPARSEP->useProtected()) yymore(); } YY_BREAK case 367: YY_RULE_SETUP #line 607 "VParseLex.l" { if (LPARSEP->useProtected()) yymore(); } YY_BREAK case YY_STATE_EOF(PROTMODE): #line 608 "VParseLex.l" { yyerrorf("EOF in `protected"); yyleng = 0; yy_pop_state(); } YY_BREAK /************************************************************************/ /* Attributes */ case 368: /* rule 368 can match eol */ YY_RULE_SETUP #line 613 "VParseLex.l" { yymore(); NEXTLINE(); } YY_BREAK case 369: YY_RULE_SETUP #line 614 "VParseLex.l" { FL; VALTEXT; CALLBACK(attributeCb); yy_pop_state(); } YY_BREAK case 370: YY_RULE_SETUP #line 615 "VParseLex.l" { yymore(); } YY_BREAK case 371: YY_RULE_SETUP #line 616 "VParseLex.l" { yymore(); } YY_BREAK case YY_STATE_EOF(ATTRMODE): #line 617 "VParseLex.l" { yyerrorf("EOF in (*"); yyleng = 0; yy_pop_state(); } YY_BREAK /************************************************************************/ /* Attributes */ /* Note simulators vary in support for "(* /_*something*_/ foo*)" where _ doesn't exist */ case 372: /* rule 372 can match eol */ YY_RULE_SETUP #line 624 "VParseLex.l" { yymore(); yy_push_state(ATTRMODE); } /* Doesn't match (*), but (* attr_spec */ YY_BREAK /************************************************************************/ /* Preprocessor */ case 373: YY_RULE_SETUP #line 630 "VParseLex.l" { FL; VALTEXT; CALLBACK(preprocCb); } // Verilog-XL compatibility YY_BREAK case 374: YY_RULE_SETUP #line 631 "VParseLex.l" { FL; VALTEXT; CALLBACK(preprocCb); } // Verilog-XL compatibility YY_BREAK case 375: YY_RULE_SETUP #line 632 "VParseLex.l" { FL; VALTEXT; CALLBACK(preprocCb); LEXP->m_inCellDefine=true; } YY_BREAK case 376: YY_RULE_SETUP #line 633 "VParseLex.l" { FL; VALTEXT; CALLBACK(preprocCb); } // Verilog spec - delays only YY_BREAK case 377: YY_RULE_SETUP #line 634 "VParseLex.l" { FL; VALTEXT; CALLBACK(preprocCb); } // Verilog 2001 YY_BREAK case 378: YY_RULE_SETUP #line 635 "VParseLex.l" { FL; VALTEXT; CALLBACK(preprocCb); } // Verilog 2009 YY_BREAK case 379: YY_RULE_SETUP #line 636 "VParseLex.l" { FL; VALTEXT; CALLBACK(preprocCb); } // Verilog spec - delays only YY_BREAK case 380: YY_RULE_SETUP #line 637 "VParseLex.l" { FL; VALTEXT; CALLBACK(preprocCb); } // Verilog spec - delays only YY_BREAK case 381: YY_RULE_SETUP #line 638 "VParseLex.l" { FL; VALTEXT; CALLBACK(preprocCb); } // Verilog spec - delays only YY_BREAK case 382: YY_RULE_SETUP #line 639 "VParseLex.l" { FL; VALTEXT; CALLBACK(preprocCb); } // Verilog spec - delays only YY_BREAK case 383: YY_RULE_SETUP #line 640 "VParseLex.l" { FL; VALTEXT; CALLBACK(preprocCb); } // Verilog-XL compatibility YY_BREAK case 384: YY_RULE_SETUP #line 641 "VParseLex.l" { FL; VALTEXT; CALLBACK(preprocCb); } // Verilog-XL compatibility YY_BREAK case 385: YY_RULE_SETUP #line 642 "VParseLex.l" { FL; VALTEXT; CALLBACK(preprocCb); LEXP->m_inCellDefine=false; } YY_BREAK case 386: YY_RULE_SETUP #line 643 "VParseLex.l" { FL; VALTEXT; CALLBACK(preprocCb); } YY_BREAK case 387: YY_RULE_SETUP #line 644 "VParseLex.l" { FL; VALTEXT; CALLBACK(preprocCb); } // Verilog-XL compatibility YY_BREAK case 388: YY_RULE_SETUP #line 645 "VParseLex.l" { FL; VALTEXT; CALLBACK(preprocCb); } YY_BREAK case 389: /* rule 389 can match eol */ YY_RULE_SETUP #line 646 "VParseLex.l" { LPARSEP->inLineDirective(yytext); FL; VALTEXT; CALLBACK(preprocCb); } YY_BREAK case 390: YY_RULE_SETUP #line 647 "VParseLex.l" { FL; VALTEXT; CALLBACK(preprocCb); } // Verilog-XL compatibility YY_BREAK case 391: YY_RULE_SETUP #line 648 "VParseLex.l" { FL; VALTEXT; CALLBACK(preprocCb); } // Verilog-XL compatibility YY_BREAK case 392: YY_RULE_SETUP #line 649 "VParseLex.l" { FL; VALTEXT; CALLBACK(preprocCb); } // Verilog-XL compatibility YY_BREAK case 393: YY_RULE_SETUP #line 650 "VParseLex.l" { FL; VALTEXT; CALLBACK(preprocCb); } // Verilog-XL compatibility YY_BREAK case 394: YY_RULE_SETUP #line 651 "VParseLex.l" { FL; VALTEXT; CALLBACK(preprocCb); } // Verilog-XL compatibility YY_BREAK case 395: YY_RULE_SETUP #line 652 "VParseLex.l" { FL; VALTEXT; CALLBACK(preprocCb); } // Verilog-XL compatibility YY_BREAK case 396: YY_RULE_SETUP #line 653 "VParseLex.l" { FL; VALTEXT; CALLBACK(preprocCb); } YY_BREAK case 397: YY_RULE_SETUP #line 654 "VParseLex.l" { FL; VALTEXT; CALLBACK(preprocCb); yy_push_state(PROTMODE); } YY_BREAK case 398: YY_RULE_SETUP #line 655 "VParseLex.l" { FL; VALTEXT; CALLBACK(preprocCb); } // Verilog 2005 YY_BREAK case 399: YY_RULE_SETUP #line 656 "VParseLex.l" { FL; VALTEXT; CALLBACK(preprocCb); } YY_BREAK case 400: YY_RULE_SETUP #line 657 "VParseLex.l" { FL; VALTEXT; CALLBACK(preprocCb); yy_push_state(PROTMODE); } YY_BREAK case 401: YY_RULE_SETUP #line 658 "VParseLex.l" { FL; VALTEXT; CALLBACK(preprocCb); } // Verilog-XL compatibility YY_BREAK case 402: YY_RULE_SETUP #line 659 "VParseLex.l" { FL; VALTEXT; CALLBACK(preprocCb); } // Verilog-XL compatibility YY_BREAK case 403: YY_RULE_SETUP #line 660 "VParseLex.l" { FL; VALTEXT; CALLBACK(preprocCb); } YY_BREAK case 404: YY_RULE_SETUP #line 661 "VParseLex.l" { FL; VALTEXT; CALLBACK(preprocCb); } // Verilog-XL compatibility YY_BREAK case 405: YY_RULE_SETUP #line 662 "VParseLex.l" { FL; VALTEXT; CALLBACK(preprocCb); } YY_BREAK /* See also setLanguage below */ case 406: YY_RULE_SETUP #line 665 "VParseLex.l" { yy_push_state(V95); CALLBACK(preprocCb); } YY_BREAK case 407: YY_RULE_SETUP #line 666 "VParseLex.l" { yy_push_state(V01); CALLBACK(preprocCb); } YY_BREAK case 408: YY_RULE_SETUP #line 667 "VParseLex.l" { yy_push_state(V01); CALLBACK(preprocCb); } YY_BREAK case 409: YY_RULE_SETUP #line 668 "VParseLex.l" { yy_push_state(V05); CALLBACK(preprocCb); } YY_BREAK case 410: YY_RULE_SETUP #line 669 "VParseLex.l" { yy_push_state(S05); CALLBACK(preprocCb); } YY_BREAK case 411: YY_RULE_SETUP #line 670 "VParseLex.l" { yy_push_state(S09); CALLBACK(preprocCb); } YY_BREAK case 412: YY_RULE_SETUP #line 671 "VParseLex.l" { yy_push_state(S12); CALLBACK(preprocCb); } YY_BREAK case 413: YY_RULE_SETUP #line 672 "VParseLex.l" { yy_push_state(S17); CALLBACK(preprocCb); } YY_BREAK case 414: YY_RULE_SETUP #line 673 "VParseLex.l" { yy_push_state(S23); CALLBACK(preprocCb); } YY_BREAK case 415: YY_RULE_SETUP #line 674 "VParseLex.l" { yy_pop_state(); CALLBACK(preprocCb); } YY_BREAK /************************************************************************/ /* Default rules - leave last */ case 416: YY_RULE_SETUP #line 681 "VParseLex.l" { FL; VALTEXT; if (LPARSEP->sigParser()) { yyerrorf("Define or directive not defined: %s",yytext); } else { CALLBACK(preprocCb); } } YY_BREAK case 417: YY_RULE_SETUP #line 684 "VParseLex.l" { FL; CALLBACK(preprocCb); yy_push_state(PROTMODE); } YY_BREAK case 418: YY_RULE_SETUP #line 686 "VParseLex.l" { FL; VALTEXT; CALLBACK(commentCb); } /* throw away single line comments */ YY_BREAK case 419: YY_RULE_SETUP #line 687 "VParseLex.l" { FL; yy_push_state(CMTMODE); yymore(); } /* FL; marks start for COMMENT callback */ YY_BREAK case 420: YY_RULE_SETUP #line 688 "VParseLex.l" { FL; VALTEXT; CALLBACK(operatorCb); return ygenOPERATOR; } /* return single char ops. */ YY_BREAK /* Catch all - absolutely last */ case 421: /* rule 421 can match eol */ YY_RULE_SETUP #line 692 "VParseLex.l" { yyerrorf("Missing VParseLex.l rule: Default rule invoked in state %d: %s", YY_START, yytext); } YY_BREAK case 422: YY_RULE_SETUP #line 693 "VParseLex.l" ECHO; YY_BREAK #line 5024 "VParseLex_pretmp.cpp" case YY_STATE_EOF(INITIAL): case YY_STATE_EOF(V95): case YY_STATE_EOF(V01): case YY_STATE_EOF(V05): case YY_STATE_EOF(S05): case YY_STATE_EOF(S09): case YY_STATE_EOF(S12): case YY_STATE_EOF(S17): case YY_STATE_EOF(S23): case YY_STATE_EOF(DUMMY_TO_AVOID_WARNING): yyterminate(); case YY_END_OF_BUFFER: { /* Amount of text matched not including the EOB char. */ int yy_amount_of_matched_text = (int) (yy_cp - (yytext_ptr)) - 1; /* Undo the effects of YY_DO_BEFORE_ACTION. */ *yy_cp = (yy_hold_char); YY_RESTORE_YY_MORE_OFFSET if ( YY_CURRENT_BUFFER_LVALUE->yy_buffer_status == YY_BUFFER_NEW ) { /* We're scanning a new file or input source. It's * possible that this happened because the user * just pointed yyin at a new source and called * yylex(). If so, then we have to assure * consistency between YY_CURRENT_BUFFER and our * globals. Here is the right place to do so, because * this is the first action (other than possibly a * back-up) that will match for the new input source. */ (yy_n_chars) = YY_CURRENT_BUFFER_LVALUE->yy_n_chars; /* %if-c-only */ YY_CURRENT_BUFFER_LVALUE->yy_input_file = yyin; /* %endif */ /* %if-c++-only */ /* %endif */ YY_CURRENT_BUFFER_LVALUE->yy_buffer_status = YY_BUFFER_NORMAL; } /* Note that here we test for yy_c_buf_p "<=" to the position * of the first EOB in the buffer, since yy_c_buf_p will * already have been incremented past the NUL character * (since all states make transitions on EOB to the * end-of-buffer state). Contrast this with the test * in input(). */ if ( (yy_c_buf_p) <= &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)] ) { /* This was really a NUL. */ yy_state_type yy_next_state; (yy_c_buf_p) = (yytext_ptr) + yy_amount_of_matched_text; yy_current_state = yy_get_previous_state( ); /* Okay, we're now positioned to make the NUL * transition. We couldn't have * yy_get_previous_state() go ahead and do it * for us because it doesn't know how to deal * with the possibility of jamming (and we don't * want to build jamming into it because then it * will run more slowly). */ yy_next_state = yy_try_NUL_trans( yy_current_state ); yy_bp = (yytext_ptr) + YY_MORE_ADJ; if ( yy_next_state ) { /* Consume the NUL. */ yy_cp = ++(yy_c_buf_p); yy_current_state = yy_next_state; goto yy_match; } else { /* %% [14.0] code to do back-up for compressed tables and set up yy_cp goes here */ yy_cp = (yy_c_buf_p); goto yy_find_action; } } else switch ( yy_get_next_buffer( ) ) { case EOB_ACT_END_OF_FILE: { (yy_did_buffer_switch_on_eof) = 0; if ( yywrap( ) ) { /* Note: because we've taken care in * yy_get_next_buffer() to have set up * yytext, we can now set up * yy_c_buf_p so that if some total * hoser (like flex itself) wants to * call the scanner after we return the * YY_NULL, it'll still work - another * YY_NULL will get returned. */ (yy_c_buf_p) = (yytext_ptr) + YY_MORE_ADJ; yy_act = YY_STATE_EOF(YY_START); goto do_action; } else { if ( ! (yy_did_buffer_switch_on_eof) ) YY_NEW_FILE; } break; } case EOB_ACT_CONTINUE_SCAN: (yy_c_buf_p) = (yytext_ptr) + yy_amount_of_matched_text; yy_current_state = yy_get_previous_state( ); yy_cp = (yy_c_buf_p); yy_bp = (yytext_ptr) + YY_MORE_ADJ; goto yy_match; case EOB_ACT_LAST_MATCH: (yy_c_buf_p) = &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)]; yy_current_state = yy_get_previous_state( ); yy_cp = (yy_c_buf_p); yy_bp = (yytext_ptr) + YY_MORE_ADJ; goto yy_find_action; } break; } default: YY_FATAL_ERROR( "fatal flex scanner internal error--no action found" ); } /* end of action switch */ } /* end of scanning one token */ } /* end of user's declarations */ } /* end of yylex */ /* %ok-for-header */ /* %if-c++-only */ /* %not-for-header */ /* %ok-for-header */ /* %endif */ /* yy_get_next_buffer - try to read in a new buffer * * Returns a code representing an action: * EOB_ACT_LAST_MATCH - * EOB_ACT_CONTINUE_SCAN - continue scanning from current position * EOB_ACT_END_OF_FILE - end of file */ /* %if-c-only */ static int yy_get_next_buffer (void) /* %endif */ /* %if-c++-only */ /* %endif */ { char *dest = YY_CURRENT_BUFFER_LVALUE->yy_ch_buf; char *source = (yytext_ptr); int number_to_move, i; int ret_val; if ( (yy_c_buf_p) > &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars) + 1] ) YY_FATAL_ERROR( "fatal flex scanner internal error--end of buffer missed" ); if ( YY_CURRENT_BUFFER_LVALUE->yy_fill_buffer == 0 ) { /* Don't try to fill the buffer, so this is an EOF. */ if ( (yy_c_buf_p) - (yytext_ptr) - YY_MORE_ADJ == 1 ) { /* We matched a single character, the EOB, so * treat this as a final EOF. */ return EOB_ACT_END_OF_FILE; } else { /* We matched some text prior to the EOB, first * process it. */ return EOB_ACT_LAST_MATCH; } } /* Try to read more data. */ /* First move last chars to start of buffer. */ number_to_move = (int) ((yy_c_buf_p) - (yytext_ptr) - 1); for ( i = 0; i < number_to_move; ++i ) *(dest++) = *(source++); if ( YY_CURRENT_BUFFER_LVALUE->yy_buffer_status == YY_BUFFER_EOF_PENDING ) /* don't do the read, it's not guaranteed to return an EOF, * just force an EOF */ YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars) = 0; else { int num_to_read = YY_CURRENT_BUFFER_LVALUE->yy_buf_size - number_to_move - 1; while ( num_to_read <= 0 ) { /* Not enough room in the buffer - grow it. */ /* just a shorter name for the current buffer */ YY_BUFFER_STATE b = YY_CURRENT_BUFFER_LVALUE; int yy_c_buf_p_offset = (int) ((yy_c_buf_p) - b->yy_ch_buf); if ( b->yy_is_our_buffer ) { int new_size = b->yy_buf_size * 2; if ( new_size <= 0 ) b->yy_buf_size += b->yy_buf_size / 8; else b->yy_buf_size *= 2; b->yy_ch_buf = (char *) /* Include room in for 2 EOB chars. */ yyrealloc( (void *) b->yy_ch_buf, (yy_size_t) (b->yy_buf_size + 2) ); } else /* Can't grow it, we don't own it. */ b->yy_ch_buf = NULL; if ( ! b->yy_ch_buf ) YY_FATAL_ERROR( "fatal error - scanner input buffer overflow" ); (yy_c_buf_p) = &b->yy_ch_buf[yy_c_buf_p_offset]; num_to_read = YY_CURRENT_BUFFER_LVALUE->yy_buf_size - number_to_move - 1; } if ( num_to_read > YY_READ_BUF_SIZE ) num_to_read = YY_READ_BUF_SIZE; /* Read in more data. */ YY_INPUT( (&YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[number_to_move]), (yy_n_chars), num_to_read ); YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars); } if ( (yy_n_chars) == 0 ) { if ( number_to_move == YY_MORE_ADJ ) { ret_val = EOB_ACT_END_OF_FILE; yyrestart( yyin ); } else { ret_val = EOB_ACT_LAST_MATCH; YY_CURRENT_BUFFER_LVALUE->yy_buffer_status = YY_BUFFER_EOF_PENDING; } } else ret_val = EOB_ACT_CONTINUE_SCAN; if (((yy_n_chars) + number_to_move) > YY_CURRENT_BUFFER_LVALUE->yy_buf_size) { /* Extend the array by 50%, plus the number we really need. */ int new_size = (yy_n_chars) + number_to_move + ((yy_n_chars) >> 1); YY_CURRENT_BUFFER_LVALUE->yy_ch_buf = (char *) yyrealloc( (void *) YY_CURRENT_BUFFER_LVALUE->yy_ch_buf, (yy_size_t) new_size ); if ( ! YY_CURRENT_BUFFER_LVALUE->yy_ch_buf ) YY_FATAL_ERROR( "out of dynamic memory in yy_get_next_buffer()" ); /* "- 2" to take care of EOB's */ YY_CURRENT_BUFFER_LVALUE->yy_buf_size = (int) (new_size - 2); } (yy_n_chars) += number_to_move; YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)] = YY_END_OF_BUFFER_CHAR; YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars) + 1] = YY_END_OF_BUFFER_CHAR; (yytext_ptr) = &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[0]; return ret_val; } /* yy_get_previous_state - get the state just before the EOB char was reached */ /* %if-c-only */ /* %not-for-header */ static yy_state_type yy_get_previous_state (void) /* %endif */ /* %if-c++-only */ /* %endif */ { yy_state_type yy_current_state; char *yy_cp; /* %% [15.0] code to get the start state into yy_current_state goes here */ yy_current_state = (yy_start); for ( yy_cp = (yytext_ptr) + YY_MORE_ADJ; yy_cp < (yy_c_buf_p); ++yy_cp ) { /* %% [16.0] code to find the next state goes here */ YY_CHAR yy_c = (*yy_cp ? yy_ec[YY_SC_TO_UI(*yy_cp)] : 1); if ( yy_accept[yy_current_state] ) { (yy_last_accepting_state) = yy_current_state; (yy_last_accepting_cpos) = yy_cp; } while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) { yy_current_state = (int) yy_def[yy_current_state]; if ( yy_current_state >= 2079 ) yy_c = yy_meta[yy_c]; } yy_current_state = yy_nxt[yy_base[yy_current_state] + yy_c]; } return yy_current_state; } /* yy_try_NUL_trans - try to make a transition on the NUL character * * synopsis * next_state = yy_try_NUL_trans( current_state ); */ /* %if-c-only */ static yy_state_type yy_try_NUL_trans (yy_state_type yy_current_state ) /* %endif */ /* %if-c++-only */ /* %endif */ { int yy_is_jam; /* %% [17.0] code to find the next state, and perhaps do backing up, goes here */ char *yy_cp = (yy_c_buf_p); YY_CHAR yy_c = 1; if ( yy_accept[yy_current_state] ) { (yy_last_accepting_state) = yy_current_state; (yy_last_accepting_cpos) = yy_cp; } while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) { yy_current_state = (int) yy_def[yy_current_state]; if ( yy_current_state >= 2079 ) yy_c = yy_meta[yy_c]; } yy_current_state = yy_nxt[yy_base[yy_current_state] + yy_c]; yy_is_jam = (yy_current_state == 2078); return yy_is_jam ? 0 : yy_current_state; } #ifndef YY_NO_UNPUT /* %if-c-only */ static void yyunput (int c, char * yy_bp ) /* %endif */ /* %if-c++-only */ /* %endif */ { char *yy_cp; yy_cp = (yy_c_buf_p); /* undo effects of setting up yytext */ *yy_cp = (yy_hold_char); if ( yy_cp < YY_CURRENT_BUFFER_LVALUE->yy_ch_buf + 2 ) { /* need to shift things up to make room */ /* +2 for EOB chars. */ int number_to_move = (yy_n_chars) + 2; char *dest = &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[ YY_CURRENT_BUFFER_LVALUE->yy_buf_size + 2]; char *source = &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[number_to_move]; while ( source > YY_CURRENT_BUFFER_LVALUE->yy_ch_buf ) *--dest = *--source; yy_cp += (int) (dest - source); yy_bp += (int) (dest - source); YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars) = (int) YY_CURRENT_BUFFER_LVALUE->yy_buf_size; if ( yy_cp < YY_CURRENT_BUFFER_LVALUE->yy_ch_buf + 2 ) YY_FATAL_ERROR( "flex scanner push-back overflow" ); } *--yy_cp = (char) c; /* %% [18.0] update yylineno here */ (yytext_ptr) = yy_bp; (yy_hold_char) = *yy_cp; (yy_c_buf_p) = yy_cp; } /* %if-c-only */ /* %endif */ #endif /* %if-c-only */ #ifndef YY_NO_INPUT #ifdef __cplusplus static int yyinput (void) #else static int input (void) #endif /* %endif */ /* %if-c++-only */ /* %endif */ { int c; *(yy_c_buf_p) = (yy_hold_char); if ( *(yy_c_buf_p) == YY_END_OF_BUFFER_CHAR ) { /* yy_c_buf_p now points to the character we want to return. * If this occurs *before* the EOB characters, then it's a * valid NUL; if not, then we've hit the end of the buffer. */ if ( (yy_c_buf_p) < &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)] ) /* This was really a NUL. */ *(yy_c_buf_p) = '\0'; else { /* need more input */ int offset = (int) ((yy_c_buf_p) - (yytext_ptr)); ++(yy_c_buf_p); switch ( yy_get_next_buffer( ) ) { case EOB_ACT_LAST_MATCH: /* This happens because yy_g_n_b() * sees that we've accumulated a * token and flags that we need to * try matching the token before * proceeding. But for input(), * there's no matching to consider. * So convert the EOB_ACT_LAST_MATCH * to EOB_ACT_END_OF_FILE. */ /* Reset buffer status. */ yyrestart( yyin ); /*FALLTHROUGH*/ case EOB_ACT_END_OF_FILE: { if ( yywrap( ) ) return 0; if ( ! (yy_did_buffer_switch_on_eof) ) YY_NEW_FILE; #ifdef __cplusplus return yyinput(); #else return input(); #endif } case EOB_ACT_CONTINUE_SCAN: (yy_c_buf_p) = (yytext_ptr) + offset; break; } } } c = *(unsigned char *) (yy_c_buf_p); /* cast for 8-bit char's */ *(yy_c_buf_p) = '\0'; /* preserve yytext */ (yy_hold_char) = *++(yy_c_buf_p); /* %% [19.0] update BOL and yylineno */ return c; } /* %if-c-only */ #endif /* ifndef YY_NO_INPUT */ /* %endif */ /** Immediately switch to a different input stream. * @param input_file A readable stream. * * @note This function does not reset the start condition to @c INITIAL . */ /* %if-c-only */ void yyrestart (FILE * input_file ) /* %endif */ /* %if-c++-only */ /* %endif */ { if ( ! YY_CURRENT_BUFFER ){ yyensure_buffer_stack (); YY_CURRENT_BUFFER_LVALUE = yy_create_buffer( yyin, YY_BUF_SIZE ); } yy_init_buffer( YY_CURRENT_BUFFER, input_file ); yy_load_buffer_state( ); } /* %if-c++-only */ /* %endif */ /** Switch to a different input buffer. * @param new_buffer The new input buffer. * */ /* %if-c-only */ void yy_switch_to_buffer (YY_BUFFER_STATE new_buffer ) /* %endif */ /* %if-c++-only */ /* %endif */ { /* TODO. We should be able to replace this entire function body * with * yypop_buffer_state(); * yypush_buffer_state(new_buffer); */ yyensure_buffer_stack (); if ( YY_CURRENT_BUFFER == new_buffer ) return; if ( YY_CURRENT_BUFFER ) { /* Flush out information for old buffer. */ *(yy_c_buf_p) = (yy_hold_char); YY_CURRENT_BUFFER_LVALUE->yy_buf_pos = (yy_c_buf_p); YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars); } YY_CURRENT_BUFFER_LVALUE = new_buffer; yy_load_buffer_state( ); /* We don't actually know whether we did this switch during * EOF (yywrap()) processing, but the only time this flag * is looked at is after yywrap() is called, so it's safe * to go ahead and always set it. */ (yy_did_buffer_switch_on_eof) = 1; } /* %if-c-only */ static void yy_load_buffer_state (void) /* %endif */ /* %if-c++-only */ /* %endif */ { (yy_n_chars) = YY_CURRENT_BUFFER_LVALUE->yy_n_chars; (yytext_ptr) = (yy_c_buf_p) = YY_CURRENT_BUFFER_LVALUE->yy_buf_pos; /* %if-c-only */ yyin = YY_CURRENT_BUFFER_LVALUE->yy_input_file; /* %endif */ /* %if-c++-only */ /* %endif */ (yy_hold_char) = *(yy_c_buf_p); } /** Allocate and initialize an input buffer state. * @param file A readable stream. * @param size The character buffer size in bytes. When in doubt, use @c YY_BUF_SIZE. * * @return the allocated buffer state. */ /* %if-c-only */ YY_BUFFER_STATE yy_create_buffer (FILE * file, int size ) /* %endif */ /* %if-c++-only */ /* %endif */ { YY_BUFFER_STATE b; b = (YY_BUFFER_STATE) yyalloc( sizeof( struct yy_buffer_state ) ); if ( ! b ) YY_FATAL_ERROR( "out of dynamic memory in yy_create_buffer()" ); b->yy_buf_size = size; /* yy_ch_buf has to be 2 characters longer than the size given because * we need to put in 2 end-of-buffer characters. */ b->yy_ch_buf = (char *) yyalloc( (yy_size_t) (b->yy_buf_size + 2) ); if ( ! b->yy_ch_buf ) YY_FATAL_ERROR( "out of dynamic memory in yy_create_buffer()" ); b->yy_is_our_buffer = 1; yy_init_buffer( b, file ); return b; } /* %if-c++-only */ /* %endif */ /** Destroy the buffer. * @param b a buffer created with yy_create_buffer() * */ /* %if-c-only */ void yy_delete_buffer (YY_BUFFER_STATE b ) /* %endif */ /* %if-c++-only */ /* %endif */ { if ( ! b ) return; if ( b == YY_CURRENT_BUFFER ) /* Not sure if we should pop here. */ YY_CURRENT_BUFFER_LVALUE = (YY_BUFFER_STATE) 0; if ( b->yy_is_our_buffer ) yyfree( (void *) b->yy_ch_buf ); yyfree( (void *) b ); } /* Initializes or reinitializes a buffer. * This function is sometimes called more than once on the same buffer, * such as during a yyrestart() or at EOF. */ /* %if-c-only */ static void yy_init_buffer (YY_BUFFER_STATE b, FILE * file ) /* %endif */ /* %if-c++-only */ /* %endif */ { int oerrno = errno; yy_flush_buffer( b ); /* %if-c-only */ b->yy_input_file = file; /* %endif */ /* %if-c++-only */ /* %endif */ b->yy_fill_buffer = 1; /* If b is the current buffer, then yy_init_buffer was _probably_ * called from yyrestart() or through yy_get_next_buffer. * In that case, we don't want to reset the lineno or column. */ if (b != YY_CURRENT_BUFFER){ b->yy_bs_lineno = 1; b->yy_bs_column = 0; } /* %if-c-only */ b->yy_is_interactive = file ? (isatty( fileno(file) ) > 0) : 0; /* %endif */ /* %if-c++-only */ /* %endif */ errno = oerrno; } /** Discard all buffered characters. On the next scan, YY_INPUT will be called. * @param b the buffer state to be flushed, usually @c YY_CURRENT_BUFFER. * */ /* %if-c-only */ void yy_flush_buffer (YY_BUFFER_STATE b ) /* %endif */ /* %if-c++-only */ /* %endif */ { if ( ! b ) return; b->yy_n_chars = 0; /* We always need two end-of-buffer characters. The first causes * a transition to the end-of-buffer state. The second causes * a jam in that state. */ b->yy_ch_buf[0] = YY_END_OF_BUFFER_CHAR; b->yy_ch_buf[1] = YY_END_OF_BUFFER_CHAR; b->yy_buf_pos = &b->yy_ch_buf[0]; b->yy_at_bol = 1; b->yy_buffer_status = YY_BUFFER_NEW; if ( b == YY_CURRENT_BUFFER ) yy_load_buffer_state( ); } /* %if-c-or-c++ */ /** Pushes the new state onto the stack. The new state becomes * the current state. This function will allocate the stack * if necessary. * @param new_buffer The new state. * */ /* %if-c-only */ void yypush_buffer_state (YY_BUFFER_STATE new_buffer ) /* %endif */ /* %if-c++-only */ /* %endif */ { if (new_buffer == NULL) return; yyensure_buffer_stack(); /* This block is copied from yy_switch_to_buffer. */ if ( YY_CURRENT_BUFFER ) { /* Flush out information for old buffer. */ *(yy_c_buf_p) = (yy_hold_char); YY_CURRENT_BUFFER_LVALUE->yy_buf_pos = (yy_c_buf_p); YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars); } /* Only push if top exists. Otherwise, replace top. */ if (YY_CURRENT_BUFFER) (yy_buffer_stack_top)++; YY_CURRENT_BUFFER_LVALUE = new_buffer; /* copied from yy_switch_to_buffer. */ yy_load_buffer_state( ); (yy_did_buffer_switch_on_eof) = 1; } /* %endif */ /* %if-c-or-c++ */ /** Removes and deletes the top of the stack, if present. * The next element becomes the new top. * */ /* %if-c-only */ void yypop_buffer_state (void) /* %endif */ /* %if-c++-only */ /* %endif */ { if (!YY_CURRENT_BUFFER) return; yy_delete_buffer(YY_CURRENT_BUFFER ); YY_CURRENT_BUFFER_LVALUE = NULL; if ((yy_buffer_stack_top) > 0) --(yy_buffer_stack_top); if (YY_CURRENT_BUFFER) { yy_load_buffer_state( ); (yy_did_buffer_switch_on_eof) = 1; } } /* %endif */ /* %if-c-or-c++ */ /* Allocates the stack if it does not exist. * Guarantees space for at least one push. */ /* %if-c-only */ static void yyensure_buffer_stack (void) /* %endif */ /* %if-c++-only */ /* %endif */ { yy_size_t num_to_alloc; if (!(yy_buffer_stack)) { /* First allocation is just for 2 elements, since we don't know if this * scanner will even need a stack. We use 2 instead of 1 to avoid an * immediate realloc on the next call. */ num_to_alloc = 1; /* After all that talk, this was set to 1 anyways... */ (yy_buffer_stack) = (struct yy_buffer_state**)yyalloc (num_to_alloc * sizeof(struct yy_buffer_state*) ); if ( ! (yy_buffer_stack) ) YY_FATAL_ERROR( "out of dynamic memory in yyensure_buffer_stack()" ); memset((yy_buffer_stack), 0, num_to_alloc * sizeof(struct yy_buffer_state*)); (yy_buffer_stack_max) = num_to_alloc; (yy_buffer_stack_top) = 0; return; } if ((yy_buffer_stack_top) >= ((yy_buffer_stack_max)) - 1){ /* Increase the buffer to prepare for a possible push. */ yy_size_t grow_size = 8 /* arbitrary grow size */; num_to_alloc = (yy_buffer_stack_max) + grow_size; (yy_buffer_stack) = (struct yy_buffer_state**)yyrealloc ((yy_buffer_stack), num_to_alloc * sizeof(struct yy_buffer_state*) ); if ( ! (yy_buffer_stack) ) YY_FATAL_ERROR( "out of dynamic memory in yyensure_buffer_stack()" ); /* zero only the new slots.*/ memset((yy_buffer_stack) + (yy_buffer_stack_max), 0, grow_size * sizeof(struct yy_buffer_state*)); (yy_buffer_stack_max) = num_to_alloc; } } /* %endif */ /* %if-c-only */ /** Setup the input buffer state to scan directly from a user-specified character buffer. * @param base the character buffer * @param size the size in bytes of the character buffer * * @return the newly allocated buffer state object. */ YY_BUFFER_STATE yy_scan_buffer (char * base, yy_size_t size ) { YY_BUFFER_STATE b; if ( size < 2 || base[size-2] != YY_END_OF_BUFFER_CHAR || base[size-1] != YY_END_OF_BUFFER_CHAR ) /* They forgot to leave room for the EOB's. */ return NULL; b = (YY_BUFFER_STATE) yyalloc( sizeof( struct yy_buffer_state ) ); if ( ! b ) YY_FATAL_ERROR( "out of dynamic memory in yy_scan_buffer()" ); b->yy_buf_size = (int) (size - 2); /* "- 2" to take care of EOB's */ b->yy_buf_pos = b->yy_ch_buf = base; b->yy_is_our_buffer = 0; b->yy_input_file = NULL; b->yy_n_chars = b->yy_buf_size; b->yy_is_interactive = 0; b->yy_at_bol = 1; b->yy_fill_buffer = 0; b->yy_buffer_status = YY_BUFFER_NEW; yy_switch_to_buffer( b ); return b; } /* %endif */ /* %if-c-only */ /** Setup the input buffer state to scan a string. The next call to yylex() will * scan from a @e copy of @a str. * @param yystr a NUL-terminated string to scan * * @return the newly allocated buffer state object. * @note If you want to scan bytes that may contain NUL values, then use * yy_scan_bytes() instead. */ YY_BUFFER_STATE yy_scan_string (const char * yystr ) { return yy_scan_bytes( yystr, (int) strlen(yystr) ); } /* %endif */ /* %if-c-only */ /** Setup the input buffer state to scan the given bytes. The next call to yylex() will * scan from a @e copy of @a bytes. * @param yybytes the byte buffer to scan * @param _yybytes_len the number of bytes in the buffer pointed to by @a bytes. * * @return the newly allocated buffer state object. */ YY_BUFFER_STATE yy_scan_bytes (const char * yybytes, int _yybytes_len ) { YY_BUFFER_STATE b; char *buf; yy_size_t n; int i; /* Get memory for full buffer, including space for trailing EOB's. */ n = (yy_size_t) (_yybytes_len + 2); buf = (char *) yyalloc( n ); if ( ! buf ) YY_FATAL_ERROR( "out of dynamic memory in yy_scan_bytes()" ); for ( i = 0; i < _yybytes_len; ++i ) buf[i] = yybytes[i]; buf[_yybytes_len] = buf[_yybytes_len+1] = YY_END_OF_BUFFER_CHAR; b = yy_scan_buffer( buf, n ); if ( ! b ) YY_FATAL_ERROR( "bad buffer in yy_scan_bytes()" ); /* It's okay to grow etc. this buffer, and we should throw it * away when we're done. */ b->yy_is_our_buffer = 1; return b; } /* %endif */ /* %if-c-only */ static void yy_push_state (int _new_state ) /* %endif */ /* %if-c++-only */ /* %endif */ { if ( (yy_start_stack_ptr) >= (yy_start_stack_depth) ) { yy_size_t new_size; (yy_start_stack_depth) += YY_START_STACK_INCR; new_size = (yy_size_t) (yy_start_stack_depth) * sizeof( int ); if ( ! (yy_start_stack) ) (yy_start_stack) = (int *) yyalloc( new_size ); else (yy_start_stack) = (int *) yyrealloc( (void *) (yy_start_stack), new_size ); if ( ! (yy_start_stack) ) YY_FATAL_ERROR( "out of memory expanding start-condition stack" ); } (yy_start_stack)[(yy_start_stack_ptr)++] = YY_START; BEGIN(_new_state); } /* %if-c-only */ static void yy_pop_state (void) /* %endif */ /* %if-c++-only */ /* %endif */ { if ( --(yy_start_stack_ptr) < 0 ) YY_FATAL_ERROR( "start-condition stack underflow" ); BEGIN((yy_start_stack)[(yy_start_stack_ptr)]); } /* %if-c-only */ static int yy_top_state (void) /* %endif */ /* %if-c++-only */ /* %endif */ { return (yy_start_stack)[(yy_start_stack_ptr) - 1]; } #ifndef YY_EXIT_FAILURE #define YY_EXIT_FAILURE 2 #endif /* %if-c-only */ static void yynoreturn yy_fatal_error (const char* msg ) { fprintf( stderr, "%s\n", msg ); exit( YY_EXIT_FAILURE ); } /* %endif */ /* %if-c++-only */ /* %endif */ /* Redefine yyless() so it works in section 3 code. */ #undef yyless #define yyless(n) \ do \ { \ /* Undo effects of setting up yytext. */ \ int yyless_macro_arg = (n); \ YY_LESS_LINENO(yyless_macro_arg);\ yytext[yyleng] = (yy_hold_char); \ (yy_c_buf_p) = yytext + yyless_macro_arg; \ (yy_hold_char) = *(yy_c_buf_p); \ *(yy_c_buf_p) = '\0'; \ yyleng = yyless_macro_arg; \ } \ while ( 0 ) /* Accessor methods (get/set functions) to struct members. */ /* %if-c-only */ /* %if-reentrant */ /* %endif */ /** Get the current line number. * */ int yyget_lineno (void) { return yylineno; } /** Get the input stream. * */ FILE *yyget_in (void) { return yyin; } /** Get the output stream. * */ FILE *yyget_out (void) { return yyout; } /** Get the length of the current token. * */ int yyget_leng (void) { return yyleng; } /** Get the current token. * */ char *yyget_text (void) { return yytext; } /* %if-reentrant */ /* %endif */ /** Set the current line number. * @param _line_number line number * */ void yyset_lineno (int _line_number ) { yylineno = _line_number; } /** Set the input stream. This does not discard the current * input buffer. * @param _in_str A readable stream. * * @see yy_switch_to_buffer */ void yyset_in (FILE * _in_str ) { yyin = _in_str ; } void yyset_out (FILE * _out_str ) { yyout = _out_str ; } int yyget_debug (void) { return yy_flex_debug; } void yyset_debug (int _bdebug ) { yy_flex_debug = _bdebug ; } /* %endif */ /* %if-reentrant */ /* %if-bison-bridge */ /* %endif */ /* %endif if-c-only */ /* %if-c-only */ static int yy_init_globals (void) { /* Initialization is the same as for the non-reentrant scanner. * This function is called from yylex_destroy(), so don't allocate here. */ (yy_buffer_stack) = NULL; (yy_buffer_stack_top) = 0; (yy_buffer_stack_max) = 0; (yy_c_buf_p) = NULL; (yy_init) = 0; (yy_start) = 0; (yy_start_stack_ptr) = 0; (yy_start_stack_depth) = 0; (yy_start_stack) = NULL; /* Defined in main.c */ #ifdef YY_STDINIT yyin = stdin; yyout = stdout; #else yyin = NULL; yyout = NULL; #endif /* For future reference: Set errno on error, since we are called by * yylex_init() */ return 0; } /* %endif */ /* %if-c-only SNIP! this currently causes conflicts with the c++ scanner */ /* yylex_destroy is for both reentrant and non-reentrant scanners. */ int yylex_destroy (void) { /* Pop the buffer stack, destroying each element. */ while(YY_CURRENT_BUFFER){ yy_delete_buffer( YY_CURRENT_BUFFER ); YY_CURRENT_BUFFER_LVALUE = NULL; yypop_buffer_state(); } /* Destroy the stack itself. */ yyfree((yy_buffer_stack) ); (yy_buffer_stack) = NULL; /* Destroy the start condition stack. */ yyfree( (yy_start_stack) ); (yy_start_stack) = NULL; /* Reset the globals. This is important in a non-reentrant scanner so the next time * yylex() is called, initialization will occur. */ yy_init_globals( ); /* %if-reentrant */ /* %endif */ return 0; } /* %endif */ /* * Internal utility routines. */ #ifndef yytext_ptr static void yy_flex_strncpy (char* s1, const char * s2, int n ) { int i; for ( i = 0; i < n; ++i ) s1[i] = s2[i]; } #endif #ifdef YY_NEED_STRLEN static int yy_flex_strlen (const char * s ) { int n; for ( n = 0; s[n]; ++n ) ; return n; } #endif void *yyalloc (yy_size_t size ) { return malloc(size); } void *yyrealloc (void * ptr, yy_size_t size ) { /* The cast to (char *) in the following accommodates both * implementations that use char* generic pointers, and those * that use void* generic pointers. It works with the latter * because both ANSI C and C++ allow castless assignment from * any pointer type to void*, and deal with argument conversions * as though doing an assignment. */ return realloc(ptr, size); } void yyfree (void * ptr ) { free( (char *) ptr ); /* see yyrealloc() for (char *) cast */ } /* %if-tables-serialization definitions */ /* %define-yytables The name for this specific scanner's tables. */ #define YYTABLES_NAME "yytables" /* %endif */ /* %ok-for-header */ #line 693 "VParseLex.l" void VParseLex::unputString(const char* textp) { s_currentLexp = this; // Add characters to input stream in back-to-front order const char* cp; for (cp = textp; *cp; cp++); for (cp--; cp >= textp; cp--) { unput(*cp); } } void VParseLex::unputString(const char* textp, size_t length) { s_currentLexp = this; // Add characters to input stream in back-to-front order const char* cp = textp; for (cp += length - 1; length--; cp--) { unput(*cp); } } void VParseLex::unused() { if (0) { // Prevent unused warnings yy_top_state(); } } int VParseLex::yylexReadTok() { // Call yylex() remembering last non-whitespace token int token = yylex(); m_prevLexToken = token; // Save so can find '#' to parse following number return token; } int VParseLex::lexToken(VParseBisonYYSType* yylvalp) { // Fetch next token from prefetch or real lexer s_currentLexp = this; int token; if (m_ahead) { // We prefetched an extra token, give it back m_ahead = false; token = m_aheadToken; *yylvalp = m_aheadVal; } else { // Parse new token s_yylvalp = yylvalp; // Read by yylex() token = yylexReadTok(); } // If a paren, read another if (token == '(' || token == yCONST__LEX || token == yGLOBAL__LEX || token == yLOCAL__LEX || token == yNEW__LEX || token == ySTATIC__LEX || token == yVIRTUAL__LEX || token == yWITH__LEX // Never put yID_* here; below symbol table resolution would break ) { #ifdef FLEX_DEBUG if (yy_flex_debug) { cout<<" lexToken: reading ahead to find possible strength"<str = "global"; } // Avoid 2009 "global" conflicting with old code when we can } else if (token == yLOCAL__LEX) { if (nexttok == yP_COLONCOLON) token = yLOCAL__COLONCOLON; else token = yLOCAL__ETC; } else if (token == yNEW__LEX) { if (nexttok == '(') token = yNEW__PAREN; else token = yNEW__ETC; } else if (token == ySTATIC__LEX) { if (nexttok == yCONSTRAINT) token = ySTATIC__CONSTRAINT; else token = ySTATIC__ETC; } else if (token == yVIRTUAL__LEX) { if (nexttok == yCLASS) token = yVIRTUAL__CLASS; else if (nexttok == yINTERFACE) token = yVIRTUAL__INTERFACE; else if (nexttok == yaID__ETC || nexttok == yaID__LEX) // || nexttok == yaID__aINTERFACE // but we may not know interfaces yet. token = yVIRTUAL__anyID; else token = yVIRTUAL__ETC; } else if (token == yWITH__LEX) { if (nexttok == '(') token = yWITH__PAREN; else if (nexttok == '[') token = yWITH__BRA; else if (nexttok == '{') token = yWITH__CUR; else token = yWITH__ETC; } // If add to above "else if", also add to "if (token" further above } // Non-lookahead conversions // If a function/task convert token based on earlier detection of yPURE yVIRTUAL switch (token) { case yPURE: m_pvstate = 1; // found pure break; case yVIRTUAL__ETC: if (m_pvstate == 1) m_pvstate = 2; // found pure virtual else m_pvstate = 0; break; case yFUNCTION__LEX: token = (m_pvstate==2) ? yFUNCTION__aPUREV : yFUNCTION__ETC; m_pvstate = 0; break; case yTASK__LEX: token = (m_pvstate==2) ? yTASK__aPUREV : yTASK__ETC; m_pvstate = 0; break; case ';': // Just to be safe m_pvstate = 0; break; default: if (m_pvstate == 1) m_pvstate = 0; break; } // If an id, change the type based on symbol table // Note above sometimes converts yGLOBAL to a yaID__LEX s_yylvalp->scp = NULL; if (token == yaID__LEX) { VAstEnt* scp; if (VAstEnt* look_underp = LPARSEP->symTableNextId()) { if (yy_flex_debug) { cout<<" lexToken: next id lookup forced under "<str<<"\""<findSym(s_yylvalp->str); // "consume" it. Must set again if want another token under temp scope LPARSEP->symTableNextId(NULL); } else { scp = LPARSEP->syms().findEntUpward(s_yylvalp->str); } if (scp) { s_yylvalp->scp = scp; switch (scp->type()) { case VAstType::PACKAGE: token = yaID__aPACKAGE; break; case VAstType::CLASS: token = yaID__aTYPE; break; case VAstType::COVERGROUP: token = yaID__aTYPE; break; case VAstType::TYPE: token = yaID__aTYPE; break; default: token = yaID__ETC; break; } } else { // Not found token = yaID__ETC; } } return token; } int VParseLex::lexToBison(VParseBisonYYSType* yylvalp) { int tok = lexToken(yylvalp); if (yy_flex_debug || LPARSEP->debug()>=6) { // When debugging flex OR bison string shortstr = yylvalp->str; if (shortstr.length()>20) shortstr = string(shortstr,20)+"..."; cout<<" lexToBison TOKEN="<scp) cout<<" scp="<scp->ascii(); cout<. */ /* As a special exception, you may create a larger work that contains part or all of the Bison parser skeleton and distribute that work under terms of your choice, so long as that work isn't itself a parser generator using the skeleton or a modified version thereof as a parser skeleton. Alternatively, if you modify or redistribute the parser skeleton itself, you may (at your option) remove this special exception, which will cause the skeleton and the resulting Bison output files to be licensed under the GNU General Public License without this special exception. This special exception was added by the Free Software Foundation in version 2.2 of Bison. */ /* DO NOT RELY ON FEATURES THAT ARE NOT DOCUMENTED in the manual, especially those whose name start with YY_ or yy_. They are private implementation details that can be changed or removed. */ #ifndef YY_VPARSEBISON_VPARSEBISON_PRETMP_H_INCLUDED # define YY_VPARSEBISON_VPARSEBISON_PRETMP_H_INCLUDED /* Debug traces. */ #ifndef YYDEBUG # define YYDEBUG 1 #endif #if YYDEBUG extern int VParseBisondebug; #endif /* Token kinds. */ #ifndef YYTOKENTYPE # define YYTOKENTYPE enum yytokentype { YYEMPTY = -2, YYEOF = 0, /* "end of file" */ YYerror = 256, /* error */ YYUNDEF = 257, /* "invalid token" */ yaFLOATNUM = 258, /* "FLOATING-POINT NUMBER" */ yaID__ETC = 259, /* "IDENTIFIER" */ yaID__LEX = 260, /* "IDENTIFIER-in-lex" */ yaID__aPACKAGE = 261, /* "PACKAGE-IDENTIFIER" */ yaID__aTYPE = 262, /* "TYPE-IDENTIFIER" */ yaINTNUM = 263, /* "INTEGER NUMBER" */ yaTIMENUM = 264, /* "TIME NUMBER" */ yaSTRING = 265, /* "STRING" */ yaSTRING__IGNORE = 266, /* "STRING-ignored" */ yaTIMINGSPEC = 267, /* "TIMING SPEC ELEMENT" */ ygenGATE = 268, /* "GATE keyword" */ ygenCONFIGKEYWORD = 269, /* "CONFIG keyword (cell/use/design/etc)" */ ygenOPERATOR = 270, /* "OPERATOR" */ ygenSTRENGTH = 271, /* "STRENGTH keyword (strong1/etc)" */ ygenSYSCALL = 272, /* "SYSCALL" */ yACCEPT_ON = 273, /* "accept_on" */ yALIAS = 274, /* "alias" */ yALWAYS = 275, /* "always" */ yAND = 276, /* "and" */ yASSERT = 277, /* "assert" */ yASSIGN = 278, /* "assign" */ yASSUME = 279, /* "assume" */ yAUTOMATIC = 280, /* "automatic" */ yBEFORE = 281, /* "before" */ yBEGIN = 282, /* "begin" */ yBIND = 283, /* "bind" */ yBINS = 284, /* "bins" */ yBINSOF = 285, /* "binsof" */ yBIT = 286, /* "bit" */ yBREAK = 287, /* "break" */ yBUF = 288, /* "buf" */ yBYTE = 289, /* "byte" */ yCASE = 290, /* "case" */ yCASEX = 291, /* "casex" */ yCASEZ = 292, /* "casez" */ yCHANDLE = 293, /* "chandle" */ yCHECKER = 294, /* "checker" */ yCLASS = 295, /* "class" */ yCLOCK = 296, /* "clock" */ yCLOCKING = 297, /* "clocking" */ yCONSTRAINT = 298, /* "constraint" */ yCONST__ETC = 299, /* "const" */ yCONST__LEX = 300, /* "const-in-lex" */ yCONST__LOCAL = 301, /* "const-then-local" */ yCONST__REF = 302, /* "const-then-ref" */ yCONTEXT = 303, /* "context" */ yCONTINUE = 304, /* "continue" */ yCOVER = 305, /* "cover" */ yCOVERGROUP = 306, /* "covergroup" */ yCOVERPOINT = 307, /* "coverpoint" */ yCROSS = 308, /* "cross" */ yDEASSIGN = 309, /* "deassign" */ yDEFAULT = 310, /* "default" */ yDEFPARAM = 311, /* "defparam" */ yDISABLE = 312, /* "disable" */ yDIST = 313, /* "dist" */ yDO = 314, /* "do" */ yEDGE = 315, /* "edge" */ yELSE = 316, /* "else" */ yEND = 317, /* "end" */ yENDCASE = 318, /* "endcase" */ yENDCHECKER = 319, /* "endchecker" */ yENDCLASS = 320, /* "endclass" */ yENDCLOCKING = 321, /* "endclocking" */ yENDFUNCTION = 322, /* "endfunction" */ yENDGENERATE = 323, /* "endgenerate" */ yENDGROUP = 324, /* "endgroup" */ yENDINTERFACE = 325, /* "endinterface" */ yENDMODULE = 326, /* "endmodule" */ yENDPACKAGE = 327, /* "endpackage" */ yENDPROGRAM = 328, /* "endprogram" */ yENDPROPERTY = 329, /* "endproperty" */ yENDSEQUENCE = 330, /* "endsequence" */ yENDSPECIFY = 331, /* "endspecify" */ yENDTABLE = 332, /* "endtable" */ yENDTASK = 333, /* "endtask" */ yENUM = 334, /* "enum" */ yEVENT = 335, /* "event" */ yEVENTUALLY = 336, /* "eventually" */ yEXPECT = 337, /* "expect" */ yEXPORT = 338, /* "export" */ yEXTENDS = 339, /* "extends" */ yEXTERN = 340, /* "extern" */ yFINAL = 341, /* "final" */ yFIRST_MATCH = 342, /* "first_match" */ yFOR = 343, /* "for" */ yFORCE = 344, /* "force" */ yFOREACH = 345, /* "foreach" */ yFOREVER = 346, /* "forever" */ yFORK = 347, /* "fork" */ yFORKJOIN = 348, /* "forkjoin" */ yFUNCTION__ETC = 349, /* "function" */ yFUNCTION__LEX = 350, /* "function-in-lex" */ yFUNCTION__aPUREV = 351, /* "function-is-pure-virtual" */ yGENERATE = 352, /* "generate" */ yGENVAR = 353, /* "genvar" */ yGLOBAL__CLOCKING = 354, /* "global-then-clocking" */ yGLOBAL__LEX = 355, /* "global-in-lex" */ yIF = 356, /* "if" */ yIFF = 357, /* "iff" */ yIGNORE_BINS = 358, /* "ignore_bins" */ yILLEGAL_BINS = 359, /* "illegal_bins" */ yIMPLEMENTS = 360, /* "implements" */ yIMPLIES = 361, /* "implies" */ yIMPORT = 362, /* "import" */ yINITIAL = 363, /* "initial" */ yINOUT = 364, /* "inout" */ yINPUT = 365, /* "input" */ yINSIDE = 366, /* "inside" */ yINT = 367, /* "int" */ yINTEGER = 368, /* "integer" */ yINTERCONNECT = 369, /* "interconnect" */ yINTERFACE = 370, /* "interface" */ yINTERSECT = 371, /* "intersect" */ yJOIN = 372, /* "join" */ yLET = 373, /* "let" */ yLOCALPARAM = 374, /* "localparam" */ yLOCAL__COLONCOLON = 375, /* "local-then-::" */ yLOCAL__ETC = 376, /* "local" */ yLOCAL__LEX = 377, /* "local-in-lex" */ yLOGIC = 378, /* "logic" */ yLONGINT = 379, /* "longint" */ yMATCHES = 380, /* "matches" */ yMODPORT = 381, /* "modport" */ yMODULE = 382, /* "module" */ yNAND = 383, /* "nand" */ yNEGEDGE = 384, /* "negedge" */ yNETTYPE = 385, /* "nettype" */ yNEW__ETC = 386, /* "new" */ yNEW__LEX = 387, /* "new-in-lex" */ yNEW__PAREN = 388, /* "new-then-paren" */ yNEXTTIME = 389, /* "nexttime" */ yNOR = 390, /* "nor" */ yNOT = 391, /* "not" */ yNULL = 392, /* "null" */ yOR = 393, /* "or" */ yOUTPUT = 394, /* "output" */ yPACKAGE = 395, /* "package" */ yPACKED = 396, /* "packed" */ yPARAMETER = 397, /* "parameter" */ yPOSEDGE = 398, /* "posedge" */ yPRIORITY = 399, /* "priority" */ yPROGRAM = 400, /* "program" */ yPROPERTY = 401, /* "property" */ yPROTECTED = 402, /* "protected" */ yPURE = 403, /* "pure" */ yRAND = 404, /* "rand" */ yRANDC = 405, /* "randc" */ yRANDCASE = 406, /* "randcase" */ yRANDSEQUENCE = 407, /* "randsequence" */ yREAL = 408, /* "real" */ yREALTIME = 409, /* "realtime" */ yREF = 410, /* "ref" */ yREG = 411, /* "reg" */ yREJECT_ON = 412, /* "reject_on" */ yRELEASE = 413, /* "release" */ yREPEAT = 414, /* "repeat" */ yRESTRICT = 415, /* "restrict" */ yRETURN = 416, /* "return" */ ySCALARED = 417, /* "scalared" */ ySEQUENCE = 418, /* "sequence" */ ySHORTINT = 419, /* "shortint" */ ySHORTREAL = 420, /* "shortreal" */ ySIGNED = 421, /* "signed" */ ySOFT = 422, /* "soft" */ ySOLVE = 423, /* "solve" */ ySPECIFY = 424, /* "specify" */ ySPECPARAM = 425, /* "specparam" */ ySTATIC__CONSTRAINT = 426, /* "static-then-constraint" */ ySTATIC__ETC = 427, /* "static" */ ySTATIC__LEX = 428, /* "static-in-lex" */ ySTRING = 429, /* "string" */ ySTRONG = 430, /* "strong" */ ySTRUCT = 431, /* "struct" */ ySUPER = 432, /* "super" */ ySUPPLY0 = 433, /* "supply0" */ ySUPPLY1 = 434, /* "supply1" */ ySYNC_ACCEPT_ON = 435, /* "sync_accept_on" */ ySYNC_REJECT_ON = 436, /* "sync_reject_on" */ yS_ALWAYS = 437, /* "s_always" */ yS_EVENTUALLY = 438, /* "s_eventually" */ yS_NEXTTIME = 439, /* "s_nexttime" */ yS_UNTIL = 440, /* "s_until" */ yS_UNTIL_WITH = 441, /* "s_until_with" */ yTABLE = 442, /* "table" */ yTAGGED = 443, /* "tagged" */ yTASK__ETC = 444, /* "task" */ yTASK__LEX = 445, /* "task-in-lex" */ yTASK__aPUREV = 446, /* "task-is-pure-virtual" */ yTHIS = 447, /* "this" */ yTHROUGHOUT = 448, /* "throughout" */ yTIME = 449, /* "time" */ yTIMEPRECISION = 450, /* "timeprecision" */ yTIMEUNIT = 451, /* "timeunit" */ yTRI = 452, /* "tri" */ yTRI0 = 453, /* "tri0" */ yTRI1 = 454, /* "tri1" */ yTRIAND = 455, /* "triand" */ yTRIOR = 456, /* "trior" */ yTRIREG = 457, /* "trireg" */ yTYPE = 458, /* "type" */ yTYPEDEF = 459, /* "typedef" */ yUNION = 460, /* "union" */ yUNIQUE = 461, /* "unique" */ yUNIQUE0 = 462, /* "unique0" */ yUNSIGNED = 463, /* "unsigned" */ yUNTIL = 464, /* "until" */ yUNTIL_WITH = 465, /* "until_with" */ yUNTYPED = 466, /* "untyped" */ yVAR = 467, /* "var" */ yVECTORED = 468, /* "vectored" */ yVIRTUAL__CLASS = 469, /* "virtual-then-class" */ yVIRTUAL__ETC = 470, /* "virtual" */ yVIRTUAL__INTERFACE = 471, /* "virtual-then-interface" */ yVIRTUAL__LEX = 472, /* "virtual-in-lex" */ yVIRTUAL__anyID = 473, /* "virtual-then-identifier" */ yVOID = 474, /* "void" */ yWAIT = 475, /* "wait" */ yWAIT_ORDER = 476, /* "wait_order" */ yWAND = 477, /* "wand" */ yWEAK = 478, /* "weak" */ yWHILE = 479, /* "while" */ yWILDCARD = 480, /* "wildcard" */ yWIRE = 481, /* "wire" */ yWITHIN = 482, /* "within" */ yWITH__BRA = 483, /* "with-then-[" */ yWITH__CUR = 484, /* "with-then-{" */ yWITH__ETC = 485, /* "with" */ yWITH__LEX = 486, /* "with-in-lex" */ yWITH__PAREN = 487, /* "with-then-(" */ yWOR = 488, /* "wor" */ yXNOR = 489, /* "xnor" */ yXOR = 490, /* "xor" */ yD_ERROR = 491, /* "$error" */ yD_FATAL = 492, /* "$fatal" */ yD_INFO = 493, /* "$info" */ yD_ROOT = 494, /* "$root" */ yD_UNIT = 495, /* "$unit" */ yD_WARNING = 496, /* "$warning" */ yP_TICK = 497, /* "'" */ yP_TICKBRA = 498, /* "'{" */ yP_OROR = 499, /* "||" */ yP_ANDAND = 500, /* "&&" */ yP_NOR = 501, /* "~|" */ yP_XNOR = 502, /* "^~" */ yP_NAND = 503, /* "~&" */ yP_EQUAL = 504, /* "==" */ yP_NOTEQUAL = 505, /* "!=" */ yP_CASEEQUAL = 506, /* "===" */ yP_CASENOTEQUAL = 507, /* "!==" */ yP_WILDEQUAL = 508, /* "==?" */ yP_WILDNOTEQUAL = 509, /* "!=?" */ yP_GTE = 510, /* ">=" */ yP_LTE = 511, /* "<=" */ yP_LTE__IGNORE = 512, /* "<=-ignored" */ yP_SLEFT = 513, /* "<<" */ yP_SRIGHT = 514, /* ">>" */ yP_SSRIGHT = 515, /* ">>>" */ yP_POW = 516, /* "**" */ yP_PAR__IGNORE = 517, /* "(-ignored" */ yP_PAR__STRENGTH = 518, /* "(-for-strength" */ yP_LTMINUSGT = 519, /* "<->" */ yP_PLUSCOLON = 520, /* "+:" */ yP_MINUSCOLON = 521, /* "-:" */ yP_MINUSGT = 522, /* "->" */ yP_MINUSGTGT = 523, /* "->>" */ yP_EQGT = 524, /* "=>" */ yP_ASTGT = 525, /* "*>" */ yP_ANDANDAND = 526, /* "&&&" */ yP_POUNDPOUND = 527, /* "##" */ yP_POUNDMINUSPD = 528, /* "#-#" */ yP_POUNDEQPD = 529, /* "#=#" */ yP_DOTSTAR = 530, /* ".*" */ yP_ATAT = 531, /* "@@" */ yP_COLONCOLON = 532, /* "::" */ yP_COLONEQ = 533, /* ":=" */ yP_COLONDIV = 534, /* ":/" */ yP_ORMINUSGT = 535, /* "|->" */ yP_OREQGT = 536, /* "|=>" */ yP_BRASTAR = 537, /* "[*" */ yP_BRAEQ = 538, /* "[=" */ yP_BRAMINUSGT = 539, /* "[->" */ yP_BRAPLUSKET = 540, /* "[+]" */ yP_PLUSPLUS = 541, /* "++" */ yP_MINUSMINUS = 542, /* "--" */ yP_PLUSEQ = 543, /* "+=" */ yP_MINUSEQ = 544, /* "-=" */ yP_TIMESEQ = 545, /* "*=" */ yP_DIVEQ = 546, /* "/=" */ yP_MODEQ = 547, /* "%=" */ yP_ANDEQ = 548, /* "&=" */ yP_OREQ = 549, /* "|=" */ yP_XOREQ = 550, /* "^=" */ yP_SLEFTEQ = 551, /* "<<=" */ yP_SRIGHTEQ = 552, /* ">>=" */ yP_SSRIGHTEQ = 553, /* ">>>=" */ prUNARYARITH = 554, /* prUNARYARITH */ prREDUCTION = 555, /* prREDUCTION */ prNEGATION = 556, /* prNEGATION */ prEVENTBEGIN = 557, /* prEVENTBEGIN */ prTAGGED = 558, /* prTAGGED */ prSEQ_CLOCKING = 559, /* prSEQ_CLOCKING */ prPOUNDPOUND_MULTI = 560, /* prPOUNDPOUND_MULTI */ prLOWER_THAN_ELSE = 561 /* prLOWER_THAN_ELSE */ }; typedef enum yytokentype yytoken_kind_t; #endif /* Value type. */ int VParseBisonparse (void); #endif /* !YY_VPARSEBISON_VPARSEBISON_PRETMP_H_INCLUDED */ Verilog-Perl-3.482/Parser/gen/flex-00000644000177100017500000000003314553624373017047 0ustar wsnyderwsnyderlMvEfF8bMEB/+mrIdsLqYBpfq0wVerilog-Perl-3.482/Parser/gen/bisonpre-s0000644000177100017500000000047414553624372020045 0ustar wsnyderwsnyder edit VParseBison.y VParseBison_pretmp.y bison -t -d -k -v --report=itemset --report=lookahead -p VParseBison -b VParseBison_pretmp -o VParseBison_pretmp.c VParseBison_pretmp.y edit VParseBison_pretmp.output VParseBison.output edit VParseBison_pretmp.c VParseBison.c edit VParseBison_pretmp.h VParseBison.h Verilog-Perl-3.482/Parser/VParseLex.l0000644000177100017500000012503214553624300017303 0ustar wsnyderwsnyder%option align interactive %option stack %option noc++ %option prefix="VParseLex" %{ /************************************************************************** * DESCRIPTION: Verilog Parser Lexer * * This file is part of Verilog-Perl. * * Author: Wilson Snyder * * Code available from: https://www.veripool.org/verilog-perl * ************************************************************************** * * Copyright 2000-2024 by Wilson Snyder. This program is free software; * you can redistribute it and/or modify it under the terms of either the * GNU Lesser General Public License Version 3 or the Perl Artistic License * Version 2.0. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * ************************************************************************** * Do not use Flex in C++ mode. It has bugs with yyunput() which result in * lost characters. *************************************************************************/ #include "VParseLex.h" #include #include #include #include #include "VParseGrammar.h" #include "VParseBison.h" #define YY_SKIP_YYWRAP #define STATE_VERILOG_RECENT S23 // State name for most recent Verilog Version // Flex 2.5.35 has compile warning in ECHO, so we'll default our own rule #define ECHO yyerrorf("Missing VParseLex.l rule: ECHO rule invoked in state %d: %s", YY_START, yytext); VParseLex* VParseLex::s_currentLexp = NULL; // Current lexing point VParseBisonYYSType* VParseLex::s_yylvalp = NULL; // LValue for current bison object #define LEXP (VParseLex::s_currentLexp) #define LPARSEP (LEXP->m_parsep) #define NEXTLINE() { LPARSEP->inFilelineInc(); } #define LINECHECKS(textp,len) { const char* cp=textp; for (int n=len; n; --n) if (cp[n]=='\n') NEXTLINE(); } #define LINECHECK() LINECHECKS(yytext,yyleng) #define FL { VParseLex::s_yylvalp->fl = LPARSEP->inFilelinep(); } // lval.fileline not used yet; here for Verilator parser compatibility #define VALTEXTS(strg) VParseLex::s_yylvalp->str = strg #define VALTEXT VALTEXTS(string(yytext,yyleng)) #define CALLBACKS(whichCb,strg) {LPARSEP->whichCb(VParseLex::s_yylvalp->fl, strg); } #define CALLBACK(whichCb) CALLBACKS(whichCb,string(yytext,yyleng)) #define YY_INPUT(buf,result,max_size) \ result = LPARSEP->inputToLex(buf,max_size); int yywrap() { return LPARSEP->eofToLex(); } #define StashPrefix LPARSEP->unreadbackCat(yytext,yyleng) void yyerror(char* errmsg) { LPARSEP->inFilelinep()->error(errmsg); } void yyerrorf(const char* format, ...) { char msg[1024]; va_list ap; va_start(ap,format); vsprintf(msg,format,ap); va_end(ap); yyerror(msg); } /**********************************************************************/ %} %s V95 V01 V05 S05 S09 S12 S17 S23 %s STRING ATTRMODE %s CMTMODE PROTMODE %s DUMMY_TO_AVOID_WARNING space [ ] ws [ \t\f\r]+ crnl [\r]*[\n] /* identifier */ id [a-zA-Z_][a-zA-Z0-9_$]* /* escaped identifier */ escid \\[^ \t\f\r\n]+ word [a-zA-Z0-9_]+ /* verilog numbers, constructed to not match the ' that begins a '( or '{ */ vnum1 [0-9]*?[''][sS]?[bcodhBCODH][ \t\n]*[A-Fa-f0-9xXzZ_?]* vnum2 [0-9]*?[''][sS]?[01xXzZ] vnum3 [0-9][_0-9]*[ \t\n]*[''][Ss]?[bcodhBCODH]?[ \t\n]*[A-Fa-f0-9xXzZ_?]+ vnum4 [0-9][_0-9]*[ \t\n]*[''][sS]?[bcodhBCODH] vnum5 [0-9][_0-9]*[ \t\n]*[''][sS] vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} %% .|\n {BEGIN STATE_VERILOG_RECENT; yyless(0); } /* Verilog 1995 */ { {ws} { StashPrefix; } /* otherwise ignore white-space */ {crnl} { StashPrefix; NEXTLINE(); } /* Count line numbers */ /* Keywords */ "always" { FL; VALTEXT; CALLBACK(keywordCb); return yALWAYS; } "and" { FL; VALTEXT; CALLBACK(keywordCb); return yAND; } "assign" { FL; VALTEXT; CALLBACK(keywordCb); return yASSIGN; } "begin" { FL; VALTEXT; CALLBACK(keywordCb); return yBEGIN; } "buf" { FL; VALTEXT; CALLBACK(keywordCb); return yBUF; } "case" { FL; VALTEXT; CALLBACK(keywordCb); return yCASE; } "casex" { FL; VALTEXT; CALLBACK(keywordCb); return yCASEX; } "casez" { FL; VALTEXT; CALLBACK(keywordCb); return yCASEZ; } "deassign" { FL; VALTEXT; CALLBACK(keywordCb); return yDEASSIGN; } "default" { FL; VALTEXT; CALLBACK(keywordCb); return yDEFAULT; } "defparam" { FL; VALTEXT; CALLBACK(keywordCb); return yDEFPARAM; } "disable" { FL; VALTEXT; CALLBACK(keywordCb); return yDISABLE; } "edge" { FL; VALTEXT; CALLBACK(keywordCb); return yEDGE; } "else" { FL; VALTEXT; CALLBACK(keywordCb); return yELSE; } "end" { FL; VALTEXT; CALLBACK(keywordCb); return yEND; } "endcase" { FL; VALTEXT; CALLBACK(keywordCb); return yENDCASE; } "endfunction" { FL; VALTEXT; CALLBACK(keywordCb); return yENDFUNCTION; } "endmodule" { FL; VALTEXT; CALLBACK(keywordCb); return yENDMODULE; } "endprimitive" { FL; VALTEXT; CALLBACK(keywordCb); return yENDMODULE; } "endspecify" { FL; VALTEXT; CALLBACK(keywordCb); return yENDSPECIFY; } "endtable" { FL; VALTEXT; CALLBACK(keywordCb); return yENDTABLE; } "endtask" { FL; VALTEXT; CALLBACK(keywordCb); return yENDTASK; } "event" { FL; VALTEXT; CALLBACK(keywordCb); return yEVENT; } "for" { FL; VALTEXT; CALLBACK(keywordCb); return yFOR; } "force" { FL; VALTEXT; CALLBACK(keywordCb); return yFORCE; } "forever" { FL; VALTEXT; CALLBACK(keywordCb); return yFOREVER; } "fork" { FL; VALTEXT; CALLBACK(keywordCb); return yFORK; } "function" { FL; VALTEXT; CALLBACK(keywordCb); return yFUNCTION__LEX; } "if" { FL; VALTEXT; CALLBACK(keywordCb); return yIF; } "initial" { FL; VALTEXT; CALLBACK(keywordCb); return yINITIAL; } "inout" { FL; VALTEXT; CALLBACK(keywordCb); return yINOUT; } "input" { FL; VALTEXT; CALLBACK(keywordCb); return yINPUT; } "integer" { FL; VALTEXT; CALLBACK(keywordCb); return yINTEGER; } "join" { FL; VALTEXT; CALLBACK(keywordCb); return yJOIN; } "macromodule" { FL; VALTEXT; CALLBACK(keywordCb); return yMODULE; } "module" { FL; VALTEXT; CALLBACK(keywordCb); return yMODULE; } "nand" { FL; VALTEXT; CALLBACK(keywordCb); return yNAND; } "negedge" { FL; VALTEXT; CALLBACK(keywordCb); return yNEGEDGE; } "nor" { FL; VALTEXT; CALLBACK(keywordCb); return yNOR; } "not" { FL; VALTEXT; CALLBACK(keywordCb); return yNOT; } "or" { FL; VALTEXT; CALLBACK(keywordCb); return yOR; } "output" { FL; VALTEXT; CALLBACK(keywordCb); return yOUTPUT; } "parameter" { FL; VALTEXT; CALLBACK(keywordCb); return yPARAMETER; } "posedge" { FL; VALTEXT; CALLBACK(keywordCb); return yPOSEDGE; } "primitive" { FL; VALTEXT; CALLBACK(keywordCb); return yMODULE; } "real" { FL; VALTEXT; CALLBACK(keywordCb); return yREAL; } "realtime" { FL; VALTEXT; CALLBACK(keywordCb); return yREALTIME; } "reg" { FL; VALTEXT; CALLBACK(keywordCb); return yREG; } "release" { FL; VALTEXT; CALLBACK(keywordCb); return yRELEASE; } "repeat" { FL; VALTEXT; CALLBACK(keywordCb); return yREPEAT; } "scalared" { FL; VALTEXT; CALLBACK(keywordCb); return ySCALARED; } "specify" { FL; VALTEXT; CALLBACK(keywordCb); return ySPECIFY; } "specparam" { FL; VALTEXT; CALLBACK(keywordCb); return ySPECPARAM; } "supply0" { FL; VALTEXT; CALLBACK(keywordCb); return ySUPPLY0; } "supply1" { FL; VALTEXT; CALLBACK(keywordCb); return ySUPPLY1; } "table" { FL; VALTEXT; CALLBACK(keywordCb); return yTABLE; } "task" { FL; VALTEXT; CALLBACK(keywordCb); return yTASK__LEX; } "time" { FL; VALTEXT; CALLBACK(keywordCb); return yTIME; } "tri" { FL; VALTEXT; CALLBACK(keywordCb); return yTRI; } "tri0" { FL; VALTEXT; CALLBACK(keywordCb); return yTRI0; } "tri1" { FL; VALTEXT; CALLBACK(keywordCb); return yTRI1; } "triand" { FL; VALTEXT; CALLBACK(keywordCb); return yTRIAND; } "trior" { FL; VALTEXT; CALLBACK(keywordCb); return yTRIOR; } "trireg" { FL; VALTEXT; CALLBACK(keywordCb); return yTRIREG; } "vectored" { FL; VALTEXT; CALLBACK(keywordCb); return yVECTORED; } "wait" { FL; VALTEXT; CALLBACK(keywordCb); return yWAIT; } "wand" { FL; VALTEXT; CALLBACK(keywordCb); return yWAND; } "while" { FL; VALTEXT; CALLBACK(keywordCb); return yWHILE; } "wire" { FL; VALTEXT; CALLBACK(keywordCb); return yWIRE; } "wor" { FL; VALTEXT; CALLBACK(keywordCb); return yWOR; } "xnor" { FL; VALTEXT; CALLBACK(keywordCb); return yXNOR; } "xor" { FL; VALTEXT; CALLBACK(keywordCb); return yXOR; } /* Types Verilator doesn't support but we do generically here */ "bufif0" { FL; VALTEXT; CALLBACK(keywordCb); return ygenGATE; } "bufif1" { FL; VALTEXT; CALLBACK(keywordCb); return ygenGATE; } "cmos" { FL; VALTEXT; CALLBACK(keywordCb); return ygenGATE; } "highz0" { FL; VALTEXT; CALLBACK(keywordCb); return ygenSTRENGTH; } "highz1" { FL; VALTEXT; CALLBACK(keywordCb); return ygenSTRENGTH; } "large" { FL; VALTEXT; CALLBACK(keywordCb); return ygenSTRENGTH; } "medium" { FL; VALTEXT; CALLBACK(keywordCb); return ygenSTRENGTH; } "nmos" { FL; VALTEXT; CALLBACK(keywordCb); return ygenGATE; } "notif0" { FL; VALTEXT; CALLBACK(keywordCb); return ygenGATE; } "notif1" { FL; VALTEXT; CALLBACK(keywordCb); return ygenGATE; } "pmos" { FL; VALTEXT; CALLBACK(keywordCb); return ygenGATE; } "pull0" { FL; VALTEXT; CALLBACK(keywordCb); return ygenSTRENGTH; } "pull1" { FL; VALTEXT; CALLBACK(keywordCb); return ygenSTRENGTH; } "pulldown" { FL; VALTEXT; CALLBACK(keywordCb); return ygenGATE; } "pullup" { FL; VALTEXT; CALLBACK(keywordCb); return ygenGATE; } "rcmos" { FL; VALTEXT; CALLBACK(keywordCb); return ygenGATE; } "rnmos" { FL; VALTEXT; CALLBACK(keywordCb); return ygenGATE; } "rpmos" { FL; VALTEXT; CALLBACK(keywordCb); return ygenGATE; } "rtran" { FL; VALTEXT; CALLBACK(keywordCb); return ygenGATE; } "rtranif0" { FL; VALTEXT; CALLBACK(keywordCb); return ygenGATE; } "rtranif1" { FL; VALTEXT; CALLBACK(keywordCb); return ygenGATE; } "small" { FL; VALTEXT; CALLBACK(keywordCb); return ygenSTRENGTH; } "strong0" { FL; VALTEXT; CALLBACK(keywordCb); return ygenSTRENGTH; } "strong1" { FL; VALTEXT; CALLBACK(keywordCb); return ygenSTRENGTH; } "tran" { FL; VALTEXT; CALLBACK(keywordCb); return ygenGATE; } "tranif0" { FL; VALTEXT; CALLBACK(keywordCb); return ygenGATE; } "tranif1" { FL; VALTEXT; CALLBACK(keywordCb); return ygenGATE; } "weak0" { FL; VALTEXT; CALLBACK(keywordCb); return ygenSTRENGTH; } "weak1" { FL; VALTEXT; CALLBACK(keywordCb); return ygenSTRENGTH; } /* Generic unsupported warnings */ } /* Verilog 2001 */ { /* Keywords*/ "automatic" { FL; VALTEXT; CALLBACK(keywordCb); return yAUTOMATIC; } "endgenerate" { FL; VALTEXT; CALLBACK(keywordCb); return yENDGENERATE; } "generate" { FL; VALTEXT; CALLBACK(keywordCb); return yGENERATE; } "genvar" { FL; VALTEXT; CALLBACK(keywordCb); return yGENVAR; } "ifnone" { FL; VALTEXT; CALLBACK(keywordCb); return yaTIMINGSPEC; } "localparam" { FL; VALTEXT; CALLBACK(keywordCb); return yLOCALPARAM; } "noshowcancelled" { FL; VALTEXT; CALLBACK(keywordCb); return yaTIMINGSPEC; } "pulsestyle_ondetect" { FL; VALTEXT; CALLBACK(keywordCb); return yaTIMINGSPEC; } "pulsestyle_onevent" { FL; VALTEXT; CALLBACK(keywordCb); return yaTIMINGSPEC; } "showcancelled" { FL; VALTEXT; CALLBACK(keywordCb); return yaTIMINGSPEC; } "signed" { FL; VALTEXT; CALLBACK(keywordCb); return ySIGNED; } "unsigned" { FL; VALTEXT; CALLBACK(keywordCb); return yUNSIGNED; } /* Generic unsupported keywords */ "cell" { FL; VALTEXT; CALLBACK(keywordCb); return ygenCONFIGKEYWORD; } "config" { FL; VALTEXT; CALLBACK(keywordCb); return ygenCONFIGKEYWORD; } "design" { FL; VALTEXT; CALLBACK(keywordCb); return ygenCONFIGKEYWORD; } "endconfig" { FL; VALTEXT; CALLBACK(keywordCb); return ygenCONFIGKEYWORD; } "incdir" { FL; VALTEXT; CALLBACK(keywordCb); return ygenCONFIGKEYWORD; } "include" { FL; VALTEXT; CALLBACK(keywordCb); return ygenCONFIGKEYWORD; } "instance" { FL; VALTEXT; CALLBACK(keywordCb); return ygenCONFIGKEYWORD; } "liblist" { FL; VALTEXT; CALLBACK(keywordCb); return ygenCONFIGKEYWORD; } "library" { FL; VALTEXT; CALLBACK(keywordCb); return ygenCONFIGKEYWORD; } "use" { FL; VALTEXT; CALLBACK(keywordCb); return ygenCONFIGKEYWORD; } } /* Verilog 2005 */ { /* Keywords */ "uwire" { FL; VALTEXT; CALLBACK(keywordCb); return yWIRE; } } /* System Verilog 2005 */ { /* System Tasks */ "$error" { FL; VALTEXT; CALLBACK(keywordCb); return yD_ERROR; } "$fatal" { FL; VALTEXT; CALLBACK(keywordCb); return yD_FATAL; } "$info" { FL; VALTEXT; CALLBACK(keywordCb); return yD_INFO; } "$root" { FL; VALTEXT; CALLBACK(keywordCb); return yD_ROOT; } "$unit" { FL; VALTEXT; CALLBACK(keywordCb); return yD_UNIT; } "$warning" { FL; VALTEXT; CALLBACK(keywordCb); return yD_WARNING; } /* Keywords */ "alias" { FL; VALTEXT; CALLBACK(keywordCb); return yALIAS; } "always_comb" { FL; VALTEXT; CALLBACK(keywordCb); return yALWAYS; } "always_ff" { FL; VALTEXT; CALLBACK(keywordCb); return yALWAYS; } "always_latch" { FL; VALTEXT; CALLBACK(keywordCb); return yALWAYS; } "assert" { FL; VALTEXT; CALLBACK(keywordCb); return yASSERT; } "assume" { FL; VALTEXT; CALLBACK(keywordCb); return yASSUME; } "before" { FL; VALTEXT; CALLBACK(keywordCb); return yBEFORE; } "bind" { FL; VALTEXT; CALLBACK(keywordCb); return yBIND; } "bins" { FL; VALTEXT; CALLBACK(keywordCb); return yBINS; } "binsof" { FL; VALTEXT; CALLBACK(keywordCb); return yBINSOF; } "bit" { FL; VALTEXT; CALLBACK(keywordCb); return yBIT; } "break" { FL; VALTEXT; CALLBACK(keywordCb); return yBREAK; } "byte" { FL; VALTEXT; CALLBACK(keywordCb); return yBYTE; } "chandle" { FL; VALTEXT; CALLBACK(keywordCb); return yCHANDLE; } "class" { FL; VALTEXT; CALLBACK(keywordCb); return yCLASS; } "clocking" { FL; VALTEXT; CALLBACK(keywordCb); return yCLOCKING; } "const" { FL; VALTEXT; CALLBACK(keywordCb); return yCONST__LEX; } "constraint" { FL; VALTEXT; CALLBACK(keywordCb); return yCONSTRAINT; } "context" { FL; VALTEXT; CALLBACK(keywordCb); return yCONTEXT; } "continue" { FL; VALTEXT; CALLBACK(keywordCb); return yCONTINUE; } "cover" { FL; VALTEXT; CALLBACK(keywordCb); return yCOVER; } "covergroup" { FL; VALTEXT; CALLBACK(keywordCb); return yCOVERGROUP; } "coverpoint" { FL; VALTEXT; CALLBACK(keywordCb); return yCOVERPOINT; } "cross" { FL; VALTEXT; CALLBACK(keywordCb); return yCROSS; } "dist" { FL; VALTEXT; CALLBACK(keywordCb); return yDIST; } "do" { FL; VALTEXT; CALLBACK(keywordCb); return yDO; } "endclass" { FL; VALTEXT; CALLBACK(keywordCb); return yENDCLASS; } "endclocking" { FL; VALTEXT; CALLBACK(keywordCb); return yENDCLOCKING; } "endgroup" { FL; VALTEXT; CALLBACK(keywordCb); return yENDGROUP; } "endinterface" { FL; VALTEXT; CALLBACK(keywordCb); return yENDINTERFACE; } "endpackage" { FL; VALTEXT; CALLBACK(keywordCb); return yENDPACKAGE; } "endprogram" { FL; VALTEXT; CALLBACK(keywordCb); return yENDPROGRAM; } "endproperty" { FL; VALTEXT; CALLBACK(keywordCb); return yENDPROPERTY; } "endsequence" { FL; VALTEXT; CALLBACK(keywordCb); return yENDSEQUENCE; } "enum" { FL; VALTEXT; CALLBACK(keywordCb); return yENUM; } "expect" { FL; VALTEXT; CALLBACK(keywordCb); return yEXPECT; } "export" { FL; VALTEXT; CALLBACK(keywordCb); return yEXPORT; } "extends" { FL; VALTEXT; CALLBACK(keywordCb); return yEXTENDS; } "extern" { FL; VALTEXT; CALLBACK(keywordCb); return yEXTERN; } "final" { FL; VALTEXT; CALLBACK(keywordCb); return yFINAL; } "first_match" { FL; VALTEXT; CALLBACK(keywordCb); return yFIRST_MATCH; } "foreach" { FL; VALTEXT; CALLBACK(keywordCb); return yFOREACH; } "forkjoin" { FL; VALTEXT; CALLBACK(keywordCb); return yFORKJOIN; } "iff" { FL; VALTEXT; CALLBACK(keywordCb); return yIFF; } "ignore_bins" { FL; VALTEXT; CALLBACK(keywordCb); return yIGNORE_BINS; } "illegal_bins" { FL; VALTEXT; CALLBACK(keywordCb); return yILLEGAL_BINS; } "import" { FL; VALTEXT; CALLBACK(keywordCb); return yIMPORT; } "inside" { FL; VALTEXT; CALLBACK(keywordCb); return yINSIDE; } "int" { FL; VALTEXT; CALLBACK(keywordCb); return yINT; } "interface" { FL; VALTEXT; CALLBACK(keywordCb); return yINTERFACE; } "intersect" { FL; VALTEXT; CALLBACK(keywordCb); return yINTERSECT; } "join_any" { FL; VALTEXT; CALLBACK(keywordCb); return yJOIN; } "join_none" { FL; VALTEXT; CALLBACK(keywordCb); return yJOIN; } "local" { FL; VALTEXT; CALLBACK(keywordCb); return yLOCAL__LEX; } "logic" { FL; VALTEXT; CALLBACK(keywordCb); return yLOGIC; } "longint" { FL; VALTEXT; CALLBACK(keywordCb); return yLONGINT; } "matches" { FL; VALTEXT; CALLBACK(keywordCb); return yMATCHES; } "modport" { FL; VALTEXT; CALLBACK(keywordCb); return yMODPORT; } "new" { FL; VALTEXT; CALLBACK(keywordCb); return yNEW__LEX; } "null" { FL; VALTEXT; CALLBACK(keywordCb); return yNULL; } "package" { FL; VALTEXT; CALLBACK(keywordCb); return yPACKAGE; } "packed" { FL; VALTEXT; CALLBACK(keywordCb); return yPACKED; } "priority" { FL; VALTEXT; CALLBACK(keywordCb); return yPRIORITY; } "program" { FL; VALTEXT; CALLBACK(keywordCb); return yPROGRAM; } "property" { FL; VALTEXT; CALLBACK(keywordCb); return yPROPERTY; } "protected" { FL; VALTEXT; CALLBACK(keywordCb); return yPROTECTED; } "pure" { FL; VALTEXT; CALLBACK(keywordCb); return yPURE; } "rand" { FL; VALTEXT; CALLBACK(keywordCb); return yRAND; } "randc" { FL; VALTEXT; CALLBACK(keywordCb); return yRANDC; } "randcase" { FL; VALTEXT; CALLBACK(keywordCb); return yRANDCASE; } "randsequence" { FL; VALTEXT; CALLBACK(keywordCb); return yRANDSEQUENCE; } "ref" { FL; VALTEXT; CALLBACK(keywordCb); return yREF; } "return" { FL; VALTEXT; CALLBACK(keywordCb); return yRETURN; } "sequence" { FL; VALTEXT; CALLBACK(keywordCb); return ySEQUENCE; } "shortint" { FL; VALTEXT; CALLBACK(keywordCb); return ySHORTINT; } "shortreal" { FL; VALTEXT; CALLBACK(keywordCb); return ySHORTREAL; } "solve" { FL; VALTEXT; CALLBACK(keywordCb); return ySOLVE; } "static" { FL; VALTEXT; CALLBACK(keywordCb); return ySTATIC__LEX; } "string" { FL; VALTEXT; CALLBACK(keywordCb); return ySTRING; } "struct" { FL; VALTEXT; CALLBACK(keywordCb); return ySTRUCT; } "super" { FL; VALTEXT; CALLBACK(keywordCb); return ySUPER; } "tagged" { FL; VALTEXT; CALLBACK(keywordCb); return yTAGGED; } "this" { FL; VALTEXT; CALLBACK(keywordCb); return yTHIS; } "throughout" { FL; VALTEXT; CALLBACK(keywordCb); return yTHROUGHOUT; } "timeprecision" { FL; VALTEXT; CALLBACK(keywordCb); return yTIMEPRECISION; } "timeunit" { FL; VALTEXT; CALLBACK(keywordCb); return yTIMEUNIT; } "type" { FL; VALTEXT; CALLBACK(keywordCb); return yTYPE; } "typedef" { FL; VALTEXT; CALLBACK(keywordCb); return yTYPEDEF; } "union" { FL; VALTEXT; CALLBACK(keywordCb); return yUNION; } "unique" { FL; VALTEXT; CALLBACK(keywordCb); return yUNIQUE; } "var" { FL; VALTEXT; CALLBACK(keywordCb); return yVAR; } "virtual" { FL; VALTEXT; CALLBACK(keywordCb); return yVIRTUAL__LEX; } "void" { FL; VALTEXT; CALLBACK(keywordCb); return yVOID; } "wait_order" { FL; VALTEXT; CALLBACK(keywordCb); return yWAIT_ORDER; } "wildcard" { FL; VALTEXT; CALLBACK(keywordCb); return yWILDCARD; } "with" { FL; VALTEXT; CALLBACK(keywordCb); return yWITH__LEX; } "within" { FL; VALTEXT; CALLBACK(keywordCb); return yWITHIN; } } /* System Verilog 2009 */ { /* Keywords */ "accept_on" { FL; VALTEXT; CALLBACK(keywordCb); return yACCEPT_ON; } "checker" { FL; VALTEXT; CALLBACK(keywordCb); return yCHECKER; } "endchecker" { FL; VALTEXT; CALLBACK(keywordCb); return yENDCHECKER; } "eventually" { FL; VALTEXT; CALLBACK(keywordCb); return yEVENTUALLY; } "global" { FL; VALTEXT; CALLBACK(keywordCb); return yGLOBAL__LEX; } "implies" { FL; VALTEXT; CALLBACK(keywordCb); return yIMPLIES; } "let" { FL; VALTEXT; CALLBACK(keywordCb); return yLET; } "nexttime" { FL; VALTEXT; CALLBACK(keywordCb); return yNEXTTIME; } "reject_on" { FL; VALTEXT; CALLBACK(keywordCb); return yREJECT_ON; } "restrict" { FL; VALTEXT; CALLBACK(keywordCb); return yRESTRICT; } "s_always" { FL; VALTEXT; CALLBACK(keywordCb); return yS_ALWAYS; } "s_eventually" { FL; VALTEXT; CALLBACK(keywordCb); return yS_EVENTUALLY; } "s_nexttime" { FL; VALTEXT; CALLBACK(keywordCb); return yS_NEXTTIME; } "s_until" { FL; VALTEXT; CALLBACK(keywordCb); return yS_UNTIL; } "s_until_with" { FL; VALTEXT; CALLBACK(keywordCb); return yS_UNTIL_WITH; } "strong" { FL; VALTEXT; CALLBACK(keywordCb); return ySTRONG; } "sync_accept_on" { FL; VALTEXT; CALLBACK(keywordCb); return ySYNC_ACCEPT_ON; } "sync_reject_on" { FL; VALTEXT; CALLBACK(keywordCb); return ySYNC_REJECT_ON; } "unique0" { FL; VALTEXT; CALLBACK(keywordCb); return yUNIQUE0; } "until" { FL; VALTEXT; CALLBACK(keywordCb); return yUNTIL; } "until_with" { FL; VALTEXT; CALLBACK(keywordCb); return yUNTIL_WITH; } "untyped" { FL; VALTEXT; CALLBACK(keywordCb); return yUNTYPED; } "weak" { FL; VALTEXT; CALLBACK(keywordCb); return yWEAK; } } /* System Verilog 2012 */ { /* Keywords */ "implements" { FL; VALTEXT; CALLBACK(keywordCb); return yIMPLEMENTS; } "interconnect" { FL; VALTEXT; CALLBACK(keywordCb); return yINTERCONNECT; } "nettype" { FL; VALTEXT; CALLBACK(keywordCb); return yNETTYPE; } "soft" { FL; VALTEXT; CALLBACK(keywordCb); return ySOFT; } } /* System Verilog 2017 */ /* No new keywords */ /* Default PLI rule */ { "$"[a-zA-Z_$][a-zA-Z0-9_$]* { FL; VALTEXT; CALLBACK(sysfuncCb); return ygenSYSCALL; } } /************************************************************************/ /* Single character operator thingies */ { "{" { FL; VALTEXT; CALLBACK(operatorCb); return yytext[0]; } "}" { FL; VALTEXT; CALLBACK(operatorCb); return yytext[0]; } } { "!" { FL; VALTEXT; CALLBACK(operatorCb); return yytext[0]; } "#" { FL; VALTEXT; CALLBACK(operatorCb); return yytext[0]; } "$" { FL; VALTEXT; CALLBACK(operatorCb); return yytext[0]; } "%" { FL; VALTEXT; CALLBACK(operatorCb); return yytext[0]; } "&" { FL; VALTEXT; CALLBACK(operatorCb); return yytext[0]; } "(" { FL; VALTEXT; CALLBACK(operatorCb); return yytext[0]; } ")" { FL; VALTEXT; CALLBACK(operatorCb); return yytext[0]; } "*" { FL; VALTEXT; CALLBACK(operatorCb); return yytext[0]; } "+" { FL; VALTEXT; CALLBACK(operatorCb); return yytext[0]; } "," { FL; VALTEXT; CALLBACK(operatorCb); return yytext[0]; } "-" { FL; VALTEXT; CALLBACK(operatorCb); return yytext[0]; } "." { FL; VALTEXT; CALLBACK(operatorCb); return yytext[0]; } "/" { FL; VALTEXT; CALLBACK(operatorCb); return yytext[0]; } ":" { FL; VALTEXT; CALLBACK(operatorCb); return yytext[0]; } ";" { FL; VALTEXT; CALLBACK(operatorCb); return yytext[0]; } "<" { FL; VALTEXT; CALLBACK(operatorCb); return yytext[0]; } "=" { FL; VALTEXT; CALLBACK(operatorCb); return yytext[0]; } ">" { FL; VALTEXT; CALLBACK(operatorCb); return yytext[0]; } "?" { FL; VALTEXT; CALLBACK(operatorCb); return yytext[0]; } "@" { FL; VALTEXT; CALLBACK(operatorCb); return yytext[0]; } "[" { FL; VALTEXT; CALLBACK(operatorCb); return yytext[0]; } "]" { FL; VALTEXT; CALLBACK(operatorCb); return yytext[0]; } "^" { FL; VALTEXT; CALLBACK(operatorCb); return yytext[0]; } "|" { FL; VALTEXT; CALLBACK(operatorCb); return yytext[0]; } "~" { FL; VALTEXT; CALLBACK(operatorCb); return yytext[0]; } } /************************************************************************/ /* Operators and multi-character symbols */ /* Verilog 1995 Operators */ { "&&" { FL; VALTEXT; CALLBACK(operatorCb); return yP_ANDAND; } "||" { FL; VALTEXT; CALLBACK(operatorCb); return yP_OROR; } "<=" { FL; VALTEXT; CALLBACK(operatorCb); return yP_LTE; } ">=" { FL; VALTEXT; CALLBACK(operatorCb); return yP_GTE; } "<<" { FL; VALTEXT; CALLBACK(operatorCb); return yP_SLEFT; } ">>" { FL; VALTEXT; CALLBACK(operatorCb); return yP_SRIGHT; } "==" { FL; VALTEXT; CALLBACK(operatorCb); return yP_EQUAL; } "!=" { FL; VALTEXT; CALLBACK(operatorCb); return yP_NOTEQUAL; } "===" { FL; VALTEXT; CALLBACK(operatorCb); return yP_CASEEQUAL; } "!==" { FL; VALTEXT; CALLBACK(operatorCb); return yP_CASENOTEQUAL; } "^~" { FL; VALTEXT; CALLBACK(operatorCb); return yP_XNOR; } "~^" { FL; VALTEXT; CALLBACK(operatorCb); return yP_XNOR; } "~&" { FL; VALTEXT; CALLBACK(operatorCb); return yP_NAND; } "~|" { FL; VALTEXT; CALLBACK(operatorCb); return yP_NOR; } "->" { FL; VALTEXT; CALLBACK(operatorCb); return yP_MINUSGT; } "=>" { FL; VALTEXT; CALLBACK(operatorCb); return yP_EQGT; } "*>" { FL; VALTEXT; CALLBACK(operatorCb); return yP_ASTGT; } "&&&" { FL; VALTEXT; CALLBACK(operatorCb); return yP_ANDANDAND; } } /* Verilog 2001 Operators */ { "<<<" { FL; VALTEXT; CALLBACK(operatorCb); return yP_SLEFT; } ">>>" { FL; VALTEXT; CALLBACK(operatorCb); return yP_SSRIGHT; } "**" { FL; VALTEXT; CALLBACK(operatorCb); return yP_POW; } "+:" { FL; VALTEXT; CALLBACK(operatorCb); return yP_PLUSCOLON; } "-:" { FL; VALTEXT; CALLBACK(operatorCb); return yP_MINUSCOLON; } ".*" { FL; VALTEXT; CALLBACK(operatorCb); return yP_DOTSTAR; } } /* SystemVerilog 2005 Operators */ { "'" { FL; VALTEXT; CALLBACK(operatorCb); return yP_TICK; } "'{" { FL; VALTEXT; CALLBACK(operatorCb); return yP_TICKBRA; } "==?" { FL; VALTEXT; CALLBACK(operatorCb); return yP_WILDEQUAL; } "!=?" { FL; VALTEXT; CALLBACK(operatorCb); return yP_WILDNOTEQUAL; } "++" { FL; VALTEXT; CALLBACK(operatorCb); return yP_PLUSPLUS; } "--" { FL; VALTEXT; CALLBACK(operatorCb); return yP_MINUSMINUS; } "+=" { FL; VALTEXT; CALLBACK(operatorCb); return yP_PLUSEQ; } "-=" { FL; VALTEXT; CALLBACK(operatorCb); return yP_MINUSEQ; } "*=" { FL; VALTEXT; CALLBACK(operatorCb); return yP_TIMESEQ; } "/=" { FL; VALTEXT; CALLBACK(operatorCb); return yP_DIVEQ; } "%=" { FL; VALTEXT; CALLBACK(operatorCb); return yP_MODEQ; } "&=" { FL; VALTEXT; CALLBACK(operatorCb); return yP_ANDEQ; } "|=" { FL; VALTEXT; CALLBACK(operatorCb); return yP_OREQ; } "^=" { FL; VALTEXT; CALLBACK(operatorCb); return yP_XOREQ; } "<<=" { FL; VALTEXT; CALLBACK(operatorCb); return yP_SLEFTEQ; } ">>=" { FL; VALTEXT; CALLBACK(operatorCb); return yP_SRIGHTEQ; } "<<<=" { FL; VALTEXT; CALLBACK(operatorCb); return yP_SLEFTEQ; } ">>>=" { FL; VALTEXT; CALLBACK(operatorCb); return yP_SSRIGHTEQ; } "->>" { FL; VALTEXT; CALLBACK(operatorCb); return yP_MINUSGTGT; } "##" { FL; VALTEXT; CALLBACK(operatorCb); return yP_POUNDPOUND; } "@@" { FL; VALTEXT; CALLBACK(operatorCb); return yP_ATAT; } "::" { FL; VALTEXT; CALLBACK(operatorCb); return yP_COLONCOLON; } ":=" { FL; VALTEXT; CALLBACK(operatorCb); return yP_COLONEQ; } ":/"[^\/\*] { FL; VALTEXT; CALLBACK(operatorCb); return yP_COLONDIV; } /* : then comment is not ":/" */ "|->" { FL; VALTEXT; CALLBACK(operatorCb); return yP_ORMINUSGT; } "|=>" { FL; VALTEXT; CALLBACK(operatorCb); return yP_OREQGT; } /* Some simulators allow whitespace here. Grr */ "["{ws}*"*" { FL; VALTEXT; CALLBACK(operatorCb); return yP_BRASTAR; } "["{ws}*"=" { FL; VALTEXT; CALLBACK(operatorCb); return yP_BRAEQ; } "["{ws}*"->" { FL; VALTEXT; CALLBACK(operatorCb); return yP_BRAMINUSGT; } "["{ws}*"+"{ws}*"]" { FL; VALTEXT; CALLBACK(operatorCb); return yP_BRAPLUSKET; } } /* SystemVerilog 2009 Operators */ { "<->" { FL; VALTEXT; CALLBACK(operatorCb); return yP_LTMINUSGT; } } /* Identifiers and numbers */ { /* Consume a following space, as we're going to add one to the symbol, we'd like to avoid inserting an extra */ {escid}{space} { if (VParseLex::symEscapeless(yytext+1,yyleng-1-1)) { string sym = string(yytext+1,yyleng-1-1); FL; CALLBACKS(symbolCb, sym); VALTEXTS(sym); unput(' '); } else { string sym = string(yytext,yyleng-1) + ' '; FL; CALLBACKS(symbolCb, sym); VALTEXTS(sym); } return yaID__LEX; } {escid} { if (VParseLex::symEscapeless(yytext+1,yyleng-1)) { string sym = string(yytext+1,yyleng-1); FL; CALLBACKS(symbolCb, sym); VALTEXTS(sym); } else { string sym = string(yytext,yyleng) + ' '; FL; CALLBACKS(symbolCb, sym); VALTEXTS(sym); } return yaID__LEX; } {id} { FL; VALTEXT; CALLBACK(symbolCb); return yaID__LEX; } \"[^\"\\]*\" { FL; VALTEXT; CALLBACK(stringCb); return yaSTRING; } \" { yy_push_state(STRING); yymore(); } {vnum} { /* "# 1'b0" is a delay value so must lex as "#" "1" "'b0" */ if (LEXP->prevLexToken()=='#') { int shortlen = 0; while (isdigit(yytext[shortlen])) shortlen++; if (shortlen) { // Return is stuff before ' VALTEXTS(string(yytext,shortlen)); // Push rest for later parse LEXP->unputString(yytext+shortlen, yyleng-shortlen); FL; LINECHECKS(yytext,shortlen); CALLBACKS(numberCb,string(yytext,shortlen)); return yaINTNUM; } } FL; VALTEXT; LINECHECK(); CALLBACK(numberCb); return yaINTNUM; } [0-9][_0-9]* { FL; VALTEXT; CALLBACK(numberCb); return yaINTNUM; } [0-9][_0-9]*(\.[_0-9]+)([eE][-+]?[_0-9]+)? { FL; VALTEXT; CALLBACK(numberCb); return yaFLOATNUM; } [0-9][_0-9]*(\.[_0-9]+)?([eE][-+]?[_0-9]+) { FL; VALTEXT; CALLBACK(numberCb); return yaFLOATNUM; } [0-9][_0-9]*(\.[_0-9]+)?(fs|ps|ns|us|ms|s|step) { FL; VALTEXT; CALLBACK(numberCb); return yaTIMENUM; } } /************************************************************************/ /* STRINGS */ <> { yyerrorf("EOF in unterminated string"); yyleng = 0; yy_pop_state(); } {crnl} { yyerrorf("Unterminated string"); NEXTLINE(); } \\{crnl} { yymore(); NEXTLINE(); } \\. { yymore(); } \" { yy_pop_state(); FL; VALTEXT; CALLBACK(stringCb); return yaSTRING; } {word} { yymore(); } . { yymore(); } /************************************************************************/ /* Multi-line COMMENTS */ "*"+[^*/\n]* { yymore(); } \n { yymore(); NEXTLINE(); } "*"+"/" { VALTEXT; CALLBACK(commentCb); yy_pop_state(); } /* No FL; it's at comment begin */ {word} { yymore(); } . { yymore(); } <> { yyerrorf("EOF in '/* ... */' block comment"); yyleng = 0; yy_pop_state(); } /************************************************************************/ /* Protected */ \n { if (LPARSEP->useProtected()) yymore(); NEXTLINE(); } "`endprotected" { FL; VALTEXT; CALLBACK(preprocCb); yy_pop_state(); } "`pragma"{ws}+"protect"{ws}+"end_protected" { FL; VALTEXT; CALLBACK(preprocCb); yy_pop_state(); } "//"{ws}*"pragma"{ws}+"protect"{ws}+"end_protected" { FL; VALTEXT; CALLBACK(preprocCb); yy_pop_state(); } . { if (LPARSEP->useProtected()) yymore(); } {word} { if (LPARSEP->useProtected()) yymore(); } <> { yyerrorf("EOF in `protected"); yyleng = 0; yy_pop_state(); } /************************************************************************/ /* Attributes */ {crnl} { yymore(); NEXTLINE(); } "*)" { FL; VALTEXT; CALLBACK(attributeCb); yy_pop_state(); } {word} { yymore(); } . { yymore(); } <> { yyerrorf("EOF in (*"); yyleng = 0; yy_pop_state(); } /************************************************************************/ /* Attributes */ /* Note simulators vary in support for "(* /_*something*_/ foo*)" where _ doesn't exist */ { "(*"({ws}|{crnl})*({id}|{escid}) { yymore(); yy_push_state(ATTRMODE); } /* Doesn't match (*), but (* attr_spec */ } /************************************************************************/ /* Preprocessor */ { "`accelerate" { FL; VALTEXT; CALLBACK(preprocCb); } // Verilog-XL compatibility "`autoexpand_vectornets" { FL; VALTEXT; CALLBACK(preprocCb); } // Verilog-XL compatibility "`celldefine" { FL; VALTEXT; CALLBACK(preprocCb); LEXP->m_inCellDefine=true; } "`default_decay_time"{ws}+[^\n\r]* { FL; VALTEXT; CALLBACK(preprocCb); } // Verilog spec - delays only "`default_nettype"{ws}+[a-zA-Z0-9]* { FL; VALTEXT; CALLBACK(preprocCb); } // Verilog 2001 "`default_trireg_strength"{ws}+[^\n\r]* { FL; VALTEXT; CALLBACK(preprocCb); } // Verilog 2009 "`delay_mode_distributed" { FL; VALTEXT; CALLBACK(preprocCb); } // Verilog spec - delays only "`delay_mode_path" { FL; VALTEXT; CALLBACK(preprocCb); } // Verilog spec - delays only "`delay_mode_unit" { FL; VALTEXT; CALLBACK(preprocCb); } // Verilog spec - delays only "`delay_mode_zero" { FL; VALTEXT; CALLBACK(preprocCb); } // Verilog spec - delays only "`disable_portfaults" { FL; VALTEXT; CALLBACK(preprocCb); } // Verilog-XL compatibility "`enable_portfaults" { FL; VALTEXT; CALLBACK(preprocCb); } // Verilog-XL compatibility "`endcelldefine" { FL; VALTEXT; CALLBACK(preprocCb); LEXP->m_inCellDefine=false; } "`endprotect" { FL; VALTEXT; CALLBACK(preprocCb); } "`expand_vectornets" { FL; VALTEXT; CALLBACK(preprocCb); } // Verilog-XL compatibility "`inline" { FL; VALTEXT; CALLBACK(preprocCb); } "`line"{ws}+[^\n\r]*{crnl} { LPARSEP->inLineDirective(yytext); FL; VALTEXT; CALLBACK(preprocCb); } "`noaccelerate" { FL; VALTEXT; CALLBACK(preprocCb); } // Verilog-XL compatibility "`noexpand_vectornets" { FL; VALTEXT; CALLBACK(preprocCb); } // Verilog-XL compatibility "`noremove_gatenames" { FL; VALTEXT; CALLBACK(preprocCb); } // Verilog-XL compatibility "`noremove_netnames" { FL; VALTEXT; CALLBACK(preprocCb); } // Verilog-XL compatibility "`nosuppress_faults" { FL; VALTEXT; CALLBACK(preprocCb); } // Verilog-XL compatibility "`nounconnected_drive" { FL; VALTEXT; CALLBACK(preprocCb); } // Verilog-XL compatibility "`portcoerce" { FL; VALTEXT; CALLBACK(preprocCb); } "`pragma"{ws}+"protect"{ws}+"begin_protected" { FL; VALTEXT; CALLBACK(preprocCb); yy_push_state(PROTMODE); } "`pragma"{ws}+[^\n\r]* { FL; VALTEXT; CALLBACK(preprocCb); } // Verilog 2005 "`protect" { FL; VALTEXT; CALLBACK(preprocCb); } "`protected" { FL; VALTEXT; CALLBACK(preprocCb); yy_push_state(PROTMODE); } "`remove_gatenames" { FL; VALTEXT; CALLBACK(preprocCb); } // Verilog-XL compatibility "`remove_netnames" { FL; VALTEXT; CALLBACK(preprocCb); } // Verilog-XL compatibility "`resetall" { FL; VALTEXT; CALLBACK(preprocCb); } "`suppress_faults" { FL; VALTEXT; CALLBACK(preprocCb); } // Verilog-XL compatibility "`timescale"{ws}+[^\n\r]* { FL; VALTEXT; CALLBACK(preprocCb); } /* See also setLanguage below */ "`begin_keywords"[ \t]*\"1364-1995\" { yy_push_state(V95); CALLBACK(preprocCb); } "`begin_keywords"[ \t]*\"1364-2001\" { yy_push_state(V01); CALLBACK(preprocCb); } "`begin_keywords"[ \t]*\"1364-2001-noconfig\" { yy_push_state(V01); CALLBACK(preprocCb); } "`begin_keywords"[ \t]*\"1364-2005\" { yy_push_state(V05); CALLBACK(preprocCb); } "`begin_keywords"[ \t]*\"1800-2005\" { yy_push_state(S05); CALLBACK(preprocCb); } "`begin_keywords"[ \t]*\"1800-2009\" { yy_push_state(S09); CALLBACK(preprocCb); } "`begin_keywords"[ \t]*\"1800-2012\" { yy_push_state(S12); CALLBACK(preprocCb); } "`begin_keywords"[ \t]*\"1800-2017\" { yy_push_state(S17); CALLBACK(preprocCb); } "`begin_keywords"[ \t]*\"1800-2023\" { yy_push_state(S23); CALLBACK(preprocCb); } "`end_keywords" { yy_pop_state(); CALLBACK(preprocCb); } } /************************************************************************/ /* Default rules - leave last */ { "`"[a-zA-Z_0-9]+ { FL; VALTEXT; if (LPARSEP->sigParser()) { yyerrorf("Define or directive not defined: %s",yytext); } else { CALLBACK(preprocCb); } } "//"{ws}*"pragma"{ws}+"protect"{ws}+"begin_protected" { FL; CALLBACK(preprocCb); yy_push_state(PROTMODE); } "//"[^\n]* { FL; VALTEXT; CALLBACK(commentCb); } /* throw away single line comments */ "/*" { FL; yy_push_state(CMTMODE); yymore(); } /* FL; marks start for COMMENT callback */ . { FL; VALTEXT; CALLBACK(operatorCb); return ygenOPERATOR; } /* return single char ops. */ } /* Catch all - absolutely last */ <*>.|\n { yyerrorf("Missing VParseLex.l rule: Default rule invoked in state %d: %s", YY_START, yytext); } %% void VParseLex::unputString(const char* textp) { s_currentLexp = this; // Add characters to input stream in back-to-front order const char* cp; for (cp = textp; *cp; cp++); for (cp--; cp >= textp; cp--) { unput(*cp); } } void VParseLex::unputString(const char* textp, size_t length) { s_currentLexp = this; // Add characters to input stream in back-to-front order const char* cp = textp; for (cp += length - 1; length--; cp--) { unput(*cp); } } void VParseLex::unused() { if (0) { // Prevent unused warnings yy_top_state(); } } int VParseLex::yylexReadTok() { // Call yylex() remembering last non-whitespace token int token = yylex(); m_prevLexToken = token; // Save so can find '#' to parse following number return token; } int VParseLex::lexToken(VParseBisonYYSType* yylvalp) { // Fetch next token from prefetch or real lexer s_currentLexp = this; int token; if (m_ahead) { // We prefetched an extra token, give it back m_ahead = false; token = m_aheadToken; *yylvalp = m_aheadVal; } else { // Parse new token s_yylvalp = yylvalp; // Read by yylex() token = yylexReadTok(); } // If a paren, read another if (token == '(' || token == yCONST__LEX || token == yGLOBAL__LEX || token == yLOCAL__LEX || token == yNEW__LEX || token == ySTATIC__LEX || token == yVIRTUAL__LEX || token == yWITH__LEX // Never put yID_* here; below symbol table resolution would break ) { #ifdef FLEX_DEBUG if (yy_flex_debug) { cout<<" lexToken: reading ahead to find possible strength"<str = "global"; } // Avoid 2009 "global" conflicting with old code when we can } else if (token == yLOCAL__LEX) { if (nexttok == yP_COLONCOLON) token = yLOCAL__COLONCOLON; else token = yLOCAL__ETC; } else if (token == yNEW__LEX) { if (nexttok == '(') token = yNEW__PAREN; else token = yNEW__ETC; } else if (token == ySTATIC__LEX) { if (nexttok == yCONSTRAINT) token = ySTATIC__CONSTRAINT; else token = ySTATIC__ETC; } else if (token == yVIRTUAL__LEX) { if (nexttok == yCLASS) token = yVIRTUAL__CLASS; else if (nexttok == yINTERFACE) token = yVIRTUAL__INTERFACE; else if (nexttok == yaID__ETC || nexttok == yaID__LEX) // || nexttok == yaID__aINTERFACE // but we may not know interfaces yet. token = yVIRTUAL__anyID; else token = yVIRTUAL__ETC; } else if (token == yWITH__LEX) { if (nexttok == '(') token = yWITH__PAREN; else if (nexttok == '[') token = yWITH__BRA; else if (nexttok == '{') token = yWITH__CUR; else token = yWITH__ETC; } // If add to above "else if", also add to "if (token" further above } // Non-lookahead conversions // If a function/task convert token based on earlier detection of yPURE yVIRTUAL switch (token) { case yPURE: m_pvstate = 1; // found pure break; case yVIRTUAL__ETC: if (m_pvstate == 1) m_pvstate = 2; // found pure virtual else m_pvstate = 0; break; case yFUNCTION__LEX: token = (m_pvstate==2) ? yFUNCTION__aPUREV : yFUNCTION__ETC; m_pvstate = 0; break; case yTASK__LEX: token = (m_pvstate==2) ? yTASK__aPUREV : yTASK__ETC; m_pvstate = 0; break; case ';': // Just to be safe m_pvstate = 0; break; default: if (m_pvstate == 1) m_pvstate = 0; break; } // If an id, change the type based on symbol table // Note above sometimes converts yGLOBAL to a yaID__LEX s_yylvalp->scp = NULL; if (token == yaID__LEX) { VAstEnt* scp; if (VAstEnt* look_underp = LPARSEP->symTableNextId()) { if (yy_flex_debug) { cout<<" lexToken: next id lookup forced under "<str<<"\""<findSym(s_yylvalp->str); // "consume" it. Must set again if want another token under temp scope LPARSEP->symTableNextId(NULL); } else { scp = LPARSEP->syms().findEntUpward(s_yylvalp->str); } if (scp) { s_yylvalp->scp = scp; switch (scp->type()) { case VAstType::PACKAGE: token = yaID__aPACKAGE; break; case VAstType::CLASS: token = yaID__aTYPE; break; case VAstType::COVERGROUP: token = yaID__aTYPE; break; case VAstType::TYPE: token = yaID__aTYPE; break; default: token = yaID__ETC; break; } } else { // Not found token = yaID__ETC; } } return token; } int VParseLex::lexToBison(VParseBisonYYSType* yylvalp) { int tok = lexToken(yylvalp); if (yy_flex_debug || LPARSEP->debug()>=6) { // When debugging flex OR bison string shortstr = yylvalp->str; if (shortstr.length()>20) shortstr = string(shortstr,20)+"..."; cout<<" lexToBison TOKEN="<scp) cout<<" scp="<scp->ascii(); cout<{_netname} = $netname; $self->{_msb} = $msb; $self->{_lsb} = $lsb; return $self; } ## Standard accessors sub netname { # ($self, $new) = @_; $_[0]->{_netname} = $_[1] if (@_ == 2); return $_[0]->{_netname}; } sub lsb { # ($self, $new) = @_; $_[0]->{_lsb} = $_[1] if (@_ == 2); return $_[0]->{_lsb}; } sub msb { # ($self, $new) = @_; $_[0]->{_msb} = $_[1] if (@_ == 2); return $_[0]->{_msb}; } ## Member functions sub bracketed_msb_lsb { my $self = shift; my $out = ""; # Handle sized constant numbers (e.g., 7'b0) distinctively # but leave unsized constants (msb/lsb undefined) alone. if ($self->netname =~ /^'/) { $out .= $self->msb + 1 if defined($self->msb); $out .= $self->netname; } else { $out .= $self->netname; if (defined($self->msb)) { if ($self->msb == $self->lsb) { $out .= "[".$self->msb."]"; } else { $out .= "[".$self->msb.":".$self->lsb."]"; } } } return $out; } ###################################################################### #### Package return 1; __END__ =pod =head1 NAME Verilog::Netlist::PinSelection - Nets attached to a Verilog Cell's Pins =head1 DESCRIPTION Verilog::Netlist::PinSelection objects are used by Verilog::Netlist::Pin to define ranges of nets attached to the respective pin of a cell. =head1 ACCESSORS =over 4 =item $self->netname Name of the respective net, or, if use_pinselects is disabled, the string representation of the whole pin value. In the case of a sized constant only the part following the ' is stored while the width is encoded in the msb and lsb fields. =item $self->lsb Least significant bit of the underlying net within the selection. =item $self->msb Most significant bit of the underlying net within the selection. =back =head1 MEMBER FUNCTIONS =over 4 =item $self->bracketed_msb_lsb Returns the common string representation of a vectored net, e.g. netA[15:8]. =back =head1 DISTRIBUTION Verilog-Perl is part of the L free Verilog EDA software tool suite. The latest version is available from CPAN and from L. Copyright 2000-2024 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. =head1 AUTHORS Stefan Tauner Wilson Snyder # =head1 SEE ALSO # L, # L # L =cut Verilog-Perl-3.482/Netlist/Net.pm0000644000177100017500000002762214553624343016544 0ustar wsnyderwsnyder# Verilog - Verilog Perl Interface # See copyright, etc in below POD section. ###################################################################### package Verilog::Netlist::Net; use Verilog::Netlist; use Verilog::Netlist::Subclass; use vars qw($VERSION @ISA); use strict; @ISA = qw(Verilog::Netlist::Net::Struct Verilog::Netlist::Subclass); $VERSION = '3.482'; my %_Type_Widths = ( 'bit' => 1, 'byte' => 8, 'genvar' => 32, 'integer' => 32, 'localparam'=> 32, 'logic' => 1, 'longint' => 64, 'parameter' => 32, 'reg' => 1, 'shortint' => 16, 'supply0' => 1, 'supply1' => 1, 'tri' => 1, 'tri0' => 1, 'tri1' => 1, 'triand' => 1, 'trior' => 1, 'trireg' => 1, 'wand' => 1, 'wire' => 1, 'wor' => 1, ); my %_Type_Accessors = ( 'genvar' => 'decl_type', 'localparam'=> 'decl_type', 'parameter' => 'decl_type', 'var' => 'decl_type', # Not in old version, but for completeness #'port' => 'decl_type', # Internals - Look at Port (input/output/inout/ref) #'net' => 'decl_type', # Internals - Look at net_type (wire/tri/...) # 'supply0' => 'net_type', 'supply1' => 'net_type', 'tri' => 'net_type', 'tri0' => 'net_type', 'tri1' => 'net_type', 'triand' => 'net_type', 'trior' => 'net_type', 'trireg' => 'net_type', 'wand' => 'net_type', 'wire' => 'net_type', 'wor' => 'net_type', # 'bit' => 'data_type', 'byte' => 'data_type', 'chandle' => 'data_type', 'event' => 'data_type', 'int' => 'data_type', 'integer' => 'data_type', 'logic' => 'data_type', 'longint' => 'data_type', 'real' => 'data_type', 'realtime' => 'data_type', 'reg' => 'data_type', 'shortint' => 'data_type', 'shortreal' => 'data_type', 'string' => 'data_type', 'time' => 'data_type', ); ###################################################################### structs('_new_base', 'Verilog::Netlist::Net::Struct' =>[name => '$', #' # Name of the net filename => '$', #' # Filename this came from lineno => '$', #' # Linenumber this came from userdata => '%', # User information attributes => '%', #' # Misc attributes for systemperl or other processors # data_type => '$', #' # SystemVerilog Type (logic/integer/reg [3:0] etc) decl_type => '$', #' # Declaration type (parameter/genvar/port/net etc) net_type => '$', #' # Net type (wire/tri/supply0 etc) comment => '$', #' # Comment provided by user array => '$', #' # Vector module => '$', #' # Module, Program or Interface entity belongs to signed => '$', #' # True if signed value => '$', #' # For parameters, the value of the parameter # below only after links() port => '$', #' # Reference to port connected to msb => '$', #' # MSB of signal (if known) lsb => '$', #' # LSB of signal (if known) stored_lsb => '$', #' # Bit number of signal stored in bit 0 (generally lsb) _used_in => '$', #' # Driver count onto signal _used_out => '$', #' # Receiver count on signal _used_inout => '$', #' # Bidirect count on signal # SystemPerl only: below only after autos() simple_type => '$', #' # True if is uint (as opposed to sc_signal) sp_traced => '$', #' # Created by SP_TRACED sp_autocreated => '$', #' # Created by /*AUTOSIGNAL*/ ]); sub new { my $class = shift; my %params = @_; my $self = $class->_new_base(%params); $self->type($params{type}) if $params{type}; # Backward compatibility return $self; } sub delete { my $self = shift; my $h = $self->module->_nets; delete $h->{$self->name}; return undef; } ###################################################################### sub logger { return $_[0]->netlist->logger; } sub netlist { return $_[0]->module->netlist; } sub _used_in_inc { $_[0]->_used_in(1+($_[0]->_used_in()||0)); } sub _used_out_inc { $_[0]->_used_out(1+($_[0]->_used_out()||0)); } sub _used_inout_inc { $_[0]->_used_inout(1+($_[0]->_used_inout()||0)); } sub _used_in_dec { return if !$_[0]->_used_in(); $_[0]->_used_in(-1+$_[0]->_used_in()); } sub _used_out_dec { return if !$_[0]->_used_out(); $_[0]->_used_out(-1+$_[0]->_used_out()); } sub _used_inout_dec { return if !$_[0]->_used_inout(); $_[0]->_used_inout(-1+$_[0]->_used_inout()); } sub stored_lsb { defined $_[0]->SUPER::stored_lsb ? $_[0]->SUPER::stored_lsb : $_[0]->lsb; } sub width { my $self = shift; # Return bit width (if known) my $dt = $self->data_type; $dt="" if $dt eq "signed"; if (defined $self->msb && defined $self->lsb) { return (abs($self->msb - $self->lsb) + 1); } elsif (my $width = $_Type_Widths{$dt || $self->net_type || $self->decl_type}) { return $width; } return undef; } sub type { my $self = shift; my $flag = shift; if (defined $flag) { if (my $acc = $_Type_Accessors{$flag}) { if ($acc eq 'decl_type') { $self->decl_type($flag); } elsif ($acc eq 'net_type') { $self->net_type($flag); } else { $self->data_type($flag); } } else { $self->data_type($flag); } } my $dt = $self->data_type; $dt="" if $dt && $dt eq "signed"; return $dt || $self->net_type || $self->decl_type; } ###################################################################### sub _link {} sub lint { my $self = shift; # Sequential logic may gen/use a signal, so we have to be a little sloppy if (0&&$self->_used_inout() && $self->_used_out() && !$self->array()) { # if an array, different outputs might hit different bits $self->warn("Signal is used as both a inout and output: ",$self->name(), "\n"); $self->dump_drivers(8); } elsif ($self->_used_out()) { if ($self->_used_out()>1 # if an array, different outputs might hit different bits && !$self->array() # if vector, warn only if # of usages is higher than # of bits in vector && (abs($self->msb() - $self->lsb()) + 1) < $self->_used_out()) { $self->warn("Signal has multiple drivers (", $self->_used_out(),"): ",$self->name(), "\n"); $self->dump_drivers(8); } } if (0&&$self->_used_in() && !$self->_used_out()) { $self->warn("Signal has no drivers: ",$self->name(), "\n"); } if (0&&$self->_used_out() && !$self->_used_in() && $self->name() !~ /unused/) { $self->dump(5); $self->port->dump(10) if $self->port; $self->warn("Signal is not used (or needs signal declaration): ",$self->name(), "\n"); flush STDOUT; flush STDERR; } } ###################################################################### ## Outputters sub _decls { my $self = shift; my $out = $self->net_type || $self->decl_type; if ($self->port) { $out = "input" if $self->port->direction eq "in"; $out = "output" if $self->port->direction eq "out"; $out = "inout" if $self->port->direction eq "inout"; } return $out; } sub verilog_text { my $self = shift; my @out; foreach my $decl ($self->_decls) { push @out, $decl; push @out, " ".$self->data_type if $self->data_type; push @out, " ".$self->name; push @out, " ".$self->array if $self->array; push @out, " = ".$self->value if defined $self->value && $self->value ne ''; push @out, ";"; push @out, " ".$self->comment if defined $self->comment && $self->comment ne ''; } return (wantarray ? @out : join('',@out)); } sub dump { my $self = shift; my $indent = shift||0; print " "x$indent,"Net:",$self->name() ," ",($self->_used_in() ? "I":""),($self->_used_out() ? "O":""), ," DeclT:",$self->decl_type||'' ," NetT:",$self->net_type||'' ," DataT:",$self->data_type||'' ," Array:",$self->array()||''; print " ",($self->msb).":".($self->lsb) if defined $self->msb; print " Value:",$self->value if defined $self->value && $self->value ne ''; print "\n"; } sub dump_drivers { my $self = shift; my $indent = shift||0; print " "x$indent,"Net:",$self->name,"\n"; if (my $port = $self->port) { print " "x$indent," Port: ",$port->name," ",$port->direction,"\n"; } foreach my $cell ($self->module->cells_sorted) { foreach my $pin ($cell->pins_sorted) { foreach my $net ($pin->nets) { next unless defined $net->{net}; if ($pin->port && $net->{net} == $self) { print " "x$indent," Pin: ",$cell->name,".",$pin->name ," ",$pin->port->direction,"\n"; } elsif ($self->name eq $net->{net}->name) { warn "%Warning: Internal net name duplicate: ".$cell->name." ".$self->name."\n" .$self->comment." ".$net->{net}->comment."\n" ."$self ".$net->{net}->name."\n"; } } } } flush STDERR; flush STDOUT; } ###################################################################### #### Package return 1; __END__ =pod =head1 NAME Verilog::Netlist::Net - Net for a Verilog Module =head1 SYNOPSIS use Verilog::Netlist; ... my $net = $module->find_net('signalname'); print $net->name; =head1 DESCRIPTION A Verilog::Netlist::Net object is created by Verilog::Netlist::Module for every signal and input/output declaration, and parameter in the current module. =head1 ACCESSORS See also Verilog::Netlist::Subclass for additional accessors and methods. =over 4 =item $self->array Any array (vector) declaration for the net. This is for Verilog 2001 multidimensional signals; for the width of a signal, use msb/lsb/width. For newer applications use data_type() as it supports SystemVerilog types. =item $self->comment Returns any comments following the definition. keep_comments=>1 must be passed to Verilog::Netlist::new for comments to be retained. =item $self->data_type The data type of the net. This may be a data type keyword ("integer", "logic", etc), user defined type from a type def, a range ("[11:0]", "signed [1:0]" or "" for an implicit wire. =item $self->decl_type How the net was declared. A declaration keyword ("genvar", "localparam", "parameter", "var") or "port" if only as a port - and see the port method, or "net" - and see the net_type method. =item $self->module Reference to the Verilog::Netlist::Module or Verilog::Netlist::Interface the net is under. =item $self->lsb The least significant bit number of the net. =item $self->msb The most significant bit number of the net. =item $self->name The name of the net. =item $self->net_type The net type, if one applies. Always a net type keyword ('supply0', 'supply1', 'tri', 'tri0', 'tri1', 'triand', 'trior', 'trireg', 'wand', 'wire', 'wor'). =item $self->type The type function is provided for backward compatibility to Verilog-Perl versions before 3.200. Applications should change to use data_type() and/or decl_type() instead. The type function returns an agglomeration of data_type, net_type and decl_type that worked ok in Verilog, but does not work with SystemVerilog. Calls to type() will be converted to calls to data_type, decl_type or net_type in a way that attempts to maintain backward compatibility, however compatibility is not always possible. =item $self->value If the net's type is 'parameter', the value from the parameter's declaration. =item $self->width The width of the net in bits. =back =head1 MEMBER FUNCTIONS See also Verilog::Netlist::Subclass for additional accessors and methods. =over 4 =item $self->lint Checks the net for errors. Normally called by Verilog::Netlist::lint. =item $self->dump Prints debugging information for this net. =item $self->dump_drivers Prints debugging information for this net, and all pins driving the net. =back =head1 DISTRIBUTION Verilog-Perl is part of the L free Verilog EDA software tool suite. The latest version is available from CPAN and from L. Copyright 2000-2024 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. =head1 AUTHORS Wilson Snyder =head1 SEE ALSO L, L L =cut Verilog-Perl-3.482/Netlist/Module.pm0000644000177100017500000003614414553624343017242 0ustar wsnyderwsnyder# Verilog - Verilog Perl Interface # See copyright, etc in below POD section. ###################################################################### package Verilog::Netlist::Module; use Verilog::Netlist; use Verilog::Netlist::ContAssign; use Verilog::Netlist::Defparam; use Verilog::Netlist::Port; use Verilog::Netlist::Net; use Verilog::Netlist::Cell; use Verilog::Netlist::Pin; use Verilog::Netlist::Subclass; use vars qw($VERSION @ISA); use strict; @ISA = qw(Verilog::Netlist::Module::Struct Verilog::Netlist::Subclass); $VERSION = '3.482'; structs('new', 'Verilog::Netlist::Module::Struct' =>[name => '$', #' # Name of the module filename => '$', #' # Filename this came from lineno => '$', #' # Linenumber this came from netlist => '$', #' # Netlist is a member of keyword => '$', #' # Type of module userdata => '%', # User information attributes => '%', #' # Misc attributes for systemperl or other processors # attrs => '@', # list of "category name[ =](.*)" strings comment => '$', #' # Comment provided by user _ports => '%', # hash of Verilog::Netlist::Ports _portsordered=> '@', # list of Verilog::Netlist::Ports as ordered in list of ports _nets => '%', # hash of Verilog::Netlist::Nets _cells => '%', # hash of Verilog::Netlist::Cells _celldecls => '%', # hash of declared cells (for autocell only) _cellarray => '%', # hash of declared cell widths (for autocell only) _cellnum => '$', # Number of next unnamed cell _level => '$', # Depth in hierarchy (if calculated) _statements => '%', # hash of Verilog::Netlist::ContAssigns _stmtnum => '$', # Number of next unnamed statement is_top => '$', #' # Module is at top of hier (not a child) is_libcell => '$', #' # Module is a library cell # SystemPerl: _autocovers => '%', #' # Hash of covers found in code _autosignal => '$', #' # Module has /*AUTOSIGNAL*/ in it _autosubcells=> '$', #' # Module has /*AUTOSUBCELL_DECL*/ in it _autotrace => '%', #' # Module has /*AUTOTRACE*/ in it _autoinoutmod=> '$', #' # Module has /*AUTOINOUT_MODULE*/ in it _pintemplates=> '@', #' # Module SP_TEMPLATEs _ctor => '$', #' # Module has SC_CTOR in it _code_symbols=> '$', #' # Hash ref of symbols found in raw code _covergroups => '%', #' # Hash of covergroups found in code lesswarn => '$', #' # True if some warnings should be disabled ]); sub delete { my $self = shift; foreach my $oref ($self->nets) { $oref->delete; } foreach my $oref ($self->ports) { $oref->delete; } foreach my $oref ($self->cells) { $oref->delete; } foreach my $oref ($self->statements) { $oref->delete; } my $h = $self->netlist->{_modules}; delete $h->{$self->name}; return undef; } ###################################################################### sub logger { return $_[0]->netlist->logger; } sub modulename_from_filename { my $filename = shift; (my $module = $filename) =~ s/.*\///; $module =~ s/\.[a-z]+$//; return $module; } sub find_port { my $self = shift; my $search = shift; return $self->_ports->{$search} || $self->_ports->{"\\".$search." "}; } sub find_port_by_index { my $self = shift; my $myindex = shift; # @{$self->_portsordered}[$myindex-1] returns the name of # the port in the module at this index. Then, this is # used to find the port reference via the port hash my $name = @{$self->_portsordered}[$myindex-1]; return undef if !$name; return $self->_ports->{$name}; } sub find_cell { my $self = shift; my $search = shift; return $self->_cells->{$search} || $self->_cells->{"\\".$search." "}; } sub find_net { my $self = shift; my $search = shift; my $rtn = $self->_nets->{$search}||""; #print "FINDNET ",$self->name, " SS $search $rtn\n"; return $self->_nets->{$search} || $self->_nets->{"\\".$search." "}; } sub attrs_sorted { return (sort {$a cmp $b} @{$_[0]->attrs}); } sub nets { return (values %{$_[0]->_nets}); } sub nets_sorted { return (sort {$a->name() cmp $b->name()} (values %{$_[0]->_nets})); } sub ports { return (values %{$_[0]->_ports}); } sub ports_sorted { return (sort {$a->name() cmp $b->name()} (values %{$_[0]->_ports})); } sub ports_ordered { my $self = shift; return map {$self->_ports->{$_}} @{$self->_portsordered}; } sub cells { return (values %{$_[0]->_cells}); } sub cells_sorted { return (sort {$a->name() cmp $b->name()} (values %{$_[0]->_cells})); } sub statements { return (values %{$_[0]->_statements}); } sub statements_sorted { return (sort {$a->name() cmp $b->name()} (values %{$_[0]->_statements})); } sub nets_and_ports_sorted { my $self = shift; my @list = ($self->nets, $self->ports,); my @outlist; my $last = ""; # Eliminate duplicates foreach my $e (sort {$a->name() cmp $b->name()} (@list)) { next if $e eq $last; push @outlist, $e; $last = $e; } return (@outlist); } sub new_net { my $self = shift; my %params = @_; # Create a new net under this my $netref; if (defined($params{msb})) { my $data_type; $data_type = "[".($params{msb}); $data_type .= ":".($params{lsb}) if defined $params{lsb}; $data_type .= "]"; $netref = new Verilog::Netlist::Net(decl_type=>'net', net_type => 'wire', data_type => $data_type, %params, module => $self); } else { $netref = new Verilog::Netlist::Net(decl_type => 'net', net_type => 'wire', %params, module => $self); } $self->_nets($netref->name(), $netref); return $netref; } sub new_attr { my $self = shift; my $clean_text = shift; push @{$self->attrs}, $clean_text; } sub new_port { my $self = shift; # @_ params # Create a new port under this module my $portref = new Verilog::Netlist::Port(@_, module=>$self,); $self->_ports($portref->name(), $portref); return $portref; } sub new_cell { my $self = shift; my %params = @_; # name=>, filename=>, lineno=>, submodname=>, params=> # Create a new cell under this module if (!defined $params{name} || $params{name} eq '') { # Blank instance name; invent a new one; use the next instance number in this module t$ $self->_cellnum(($self->_cellnum||0) + 1); $params{name} = '__unnamed_instance_' . $self->_cellnum; } if (my $preexist = $self->find_cell($params{name})) { $self->_cellnum(($self->_cellnum||0) + 1); $params{name} .= '__duplicate_' . $self->_cellnum; } # Create a new cell; pass the potentially modified options my $cellref = new Verilog::Netlist::Cell(%params, module=>$self,); # Add the new cell to the hash of cells in this module $self->_cells($params{name}, $cellref); return $cellref; } sub new_contassign { my $self = shift; my %params = @_; # name=>, filename=>, lineno=>, keyword=> etc # Create a new statement under this module if (!defined $params{name} || $params{name} eq '') { # Blank instance name; invent a new one; use the next instance number in this module t$ $self->_stmtnum(($self->_stmtnum||0) + 1); $params{name} = '__unnamed_statement_' . $self->_stmtnum; } # Create a new object; pass the potentially modified options my $newref = new Verilog::Netlist::ContAssign(%params, module=>$self,); # Add the new object to the hash of statements in this module $self->_statements($params{name}, $newref); return $newref; } sub new_defparam { my $self = shift; my %params = @_; # name=>, filename=>, lineno=>, keyword=> etc # Create a new statement under this module if (!defined $params{name} || $params{name} eq '') { # Blank instance name; invent a new one; use the next instance number in this module t$ $self->_stmtnum(($self->_stmtnum||0) + 1); $params{name} = '__unnamed_statement_' . $self->_stmtnum; } # Create a new object; pass the potentially modified options my $newref = new Verilog::Netlist::Defparam(%params, module=>$self,); # Add the new object to the hash of statements in this module $self->_statements($params{name}, $newref); return $newref; } sub level { my $self = shift; my $level = $self->_level; return $level if defined $level; $self->_level(1); # Set before recurse in case there's circular module refs foreach my $cell ($self->cells) { if ($cell->submod) { my $celllevel = $cell->submod->level; $self->_level($celllevel+1) if $celllevel >= $self->_level; } } return $self->_level; } sub link { my $self = shift; # Ports create nets, so link ports before nets foreach my $portref ($self->ports) { $portref->_link(); } foreach my $netref ($self->nets) { $netref->_link(); } foreach my $cellref ($self->cells) { $cellref->_link(); } } sub lint { my $self = shift; if ($self->netlist->{use_vars}) { foreach my $portref ($self->ports) { $portref->lint(); } foreach my $netref ($self->nets) { $netref->lint(); } } foreach my $cellref ($self->cells) { $cellref->lint(); } foreach my $oref ($self->statements) { $oref->lint(); } } sub verilog_text { my $self = shift; my @out = ($self->keyword||'module')." ".$self->name." (\n"; my $indent = " "; # Port list my $comma=""; push @out, $indent; foreach my $portref ($self->ports_sorted) { push @out, $comma, $portref->verilog_text; $comma = ", "; } push @out, ");\n"; # Signal list foreach my $netref ($self->nets_sorted) { push @out, $indent, $netref->verilog_text, "\n"; } # Cell list foreach my $cellref ($self->cells_sorted) { push @out, $indent, $cellref->verilog_text, "\n"; } foreach my $oref ($self->statements_sorted) { push @out, $indent, $oref->verilog_text, "\n"; } push @out, "end".($self->keyword||'module')."\n"; return (wantarray ? @out : join('',@out)); } sub dump { my $self = shift; my $indent = shift||0; my $norecurse = shift; print " "x$indent,"Module:",$self->name()," Kwd:",($self->keyword||'')," File:",$self->filename(),"\n"; if (!$norecurse) { foreach my $portref ($self->ports_sorted) { $portref->dump($indent+2); } foreach my $netref ($self->nets_sorted) { $netref->dump($indent+2); } foreach my $cellref ($self->cells_sorted) { $cellref->dump($indent+2); } foreach my $cellref ($self->statements_sorted) { $cellref->dump($indent+2); } } } ###################################################################### #### Package return 1; __END__ =pod =head1 NAME Verilog::Netlist::Module - Module within a Verilog Netlist =head1 SYNOPSIS use Verilog::Netlist; ... my $module = $netlist->find_module('modname'); my $cell = $self->find_cell('name') my $port = $self->find_port('name') my $net = $self->find_net('name') =head1 DESCRIPTION A Verilog::Netlist::Module object is created by Verilog::Netlist for every module, macromodule, primitive or program in the design. =head1 ACCESSORS See also Verilog::Netlist::Subclass for additional accessors and methods. =over 4 =item $self->cells Returns list of references to Verilog::Netlist::Cell in the module. =item $self->cells_sorted Returns list of name sorted references to Verilog::Netlist::Cell in the module. =item $self->comment Returns any comments following the definition. keep_comments=>1 must be passed to Verilog::Netlist::new for comments to be retained. =item $self->find_port_by_index Returns the port name associated with the given index. Indexes start at 1 (pin numbers are traditionally counted from pin 1..pin N, not starting at zero. This was probably an unfortunate choice, sorry.) =item $self->is_top Returns true if the module has no cells referencing it (is at the top of the hierarchy.) =item $self->keyword Returns the keyword used to declare the module ("module", "macromodule", "primitive" or "program".) It might at first not seem obvious that programs are considered modules, but in most cases they contain the same type of objects so can be handled identically. =item $self->name The name of the module. =item $self->netlist Reference to the Verilog::Netlist the module is under. =item $self->nets Returns list of references to Verilog::Netlist::Net in the module. =item $self->nets_sorted Returns list of name sorted references to Verilog::Netlist::Net in the module. =item $self->nets_and_ports_sorted Returns list of name sorted references to Verilog::Netlist::Net and Verilog::Netlist::Port in the module. =item $self->ports Returns list of references to Verilog::Netlist::Port in the module. =item $self->ports_ordered Returns list of references to Verilog::Netlist::Port in the module sorted by pin number. =item $self->ports_sorted Returns list of references to Verilog::Netlist::Port in the module sorted by name. =item $self->statements Returns list of references to Verilog::Netlist::ContAssign in the module. Other statement types (Always, etc) may also be added to this list in the future. =item $self->statements_sorted Returns list of name sorted references to Verilog::Netlist::ContAssign in the module. Other statement types (Always, etc) may also be added to this list in the future. =back =head1 MEMBER FUNCTIONS See also Verilog::Netlist::Subclass for additional accessors and methods. =over 4 =item $self->find_cell(I) Returns Verilog::Netlist::Cell matching given name. =item $self->find_port(I) Returns Verilog::Netlist::Port matching given name. =item $self->find_net(I) Returns Verilog::Netlist::Net matching given name. =item $self->is_libcell Returns if module declared inside a `celldefine. =item $self->level Returns the reverse depth of this module with respect to other modules. Leaf modules (modules with no cells) will be level 1. Modules which instantiate cells of level 1 will be level 2 modules and so forth. See also Netlist's modules_sorted_level. =item $self->lint Checks the module for errors. =item $self->link Creates interconnections between this module and other modules. =item $self->modulename_from_filename Uses a rough algorithm (drop the extension) to convert a filename to the module that is expected to be inside it. =item $self->new_cell Creates a new Verilog::Netlist::Cell. =item $self->new_port Creates a new Verilog::Netlist::Port. =item $self->new_net Creates a new Verilog::Netlist::Net. =item $self->dump Prints debugging information for this module. =item $self->verilog_text Returns verilog code which represents this module. Returned as an array that must be joined together to form the final text string. The netlist must be already ->link'ed for this to work correctly. =back =head1 DISTRIBUTION Verilog-Perl is part of the L free Verilog EDA software tool suite. The latest version is available from CPAN and from L. Copyright 2000-2024 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. =head1 AUTHORS Wilson Snyder =head1 SEE ALSO L, L L =cut Verilog-Perl-3.482/Netlist/Port.pm0000644000177100017500000001301314553624343016727 0ustar wsnyderwsnyder# Verilog - Verilog Perl Interface # See copyright, etc in below POD section. ###################################################################### package Verilog::Netlist::Port; use Verilog::Netlist; use Verilog::Netlist::Subclass; use vars qw($VERSION @ISA); use strict; @ISA = qw(Verilog::Netlist::Port::Struct Verilog::Netlist::Subclass); $VERSION = '3.482'; structs('_new_base', 'Verilog::Netlist::Port::Struct' =>[name => '$', #' # Name of the port filename => '$', #' # Filename this came from lineno => '$', #' # Linenumber this came from userdata => '%', # User information attributes => '%', #' # Misc attributes for systemperl or other processors # direction => '$', #' # Direction (in/out/inout) data_type => '$', #' # SystemVerilog Type (logic/integer etc) comment => '$', #' # Comment provided by user array => '$', #' # Vectorization module => '$', #' # Module entity belongs to # below only after links() net => '$', #' # Net port connects # below only after autos() sp_autocreated => '$', #' # Created by /*AUTOINOUT*/ ]); sub new { my $class = shift; my %params = (@_); $params{data_type} = $params{type} if defined $params{type}; # Backward compatibility if ($params{direction}) { # Correct common mistakes; plus the parser itself needs this conversion $params{direction} = 'in' if $params{direction} eq 'input'; $params{direction} = 'out' if $params{direction} eq 'output'; } return $class->_new_base(%params); } sub delete { my $self = shift; my $h = $self->module->_ports; delete $h->{$self->name}; return undef; } ###################################################################### sub netlist { return $_[0]->module->netlist; } sub logger { return $_[0]->netlist->logger; } sub type { # Backward compatibility only my $self=shift; if ($#_ >= 0) { $self->data_type(@_); } return ($self->data_type || ($self->net && $self->net->type))||''; } sub _link { my $self = shift; if (!$self->net) { my $net = $self->module->find_net($self->name); if (!$net) { my $msb; my $lsb; if (defined $self->data_type) { $self->data_type =~ /\[([^:]+)(:(.*))?\]$/; $msb = $1; $lsb = defined($3) ? $3 : $1; } $net = $self->module->new_net (name=>$self->name, filename=>$self->filename, lineno=>$self->lineno, decl_type=>"port", net_type=>"wire", data_type=>$self->data_type, array=>$self->array, comment=>undef, msb=>$msb, lsb=>$lsb, ); $net->attributes($self->attributes); # Copy attributes across } if ($net && $net->port && $net->port != $self) { $self->error("Port redeclares existing port: ",$self->name,"\n"); } $self->net($net); $self->net->port($self); # A input to the module is actually a "source" or thus "out" of the net. $self->net->_used_in_inc() if ($self->direction() eq 'out'); $self->net->_used_out_inc() if ($self->direction() eq 'in'); $self->net->_used_inout_inc() if ($self->direction() eq 'inout'); } } sub lint {} sub verilog_text { my $self = shift; return $self->name; } sub dump { my $self = shift; my $indent = shift||0; print " "x$indent,"Port:",$self->name()," Dir:",$self->direction() ," DataT:",$self->data_type()," Array:",$self->array()||"","\n"; } ###################################################################### #### Package return 1; __END__ =pod =head1 NAME Verilog::Netlist::Port - Port for a Verilog Module =head1 SYNOPSIS use Verilog::Netlist; ... my $port = $module->find_port('pinname'); print $port->name; =head1 DESCRIPTION A Verilog::Netlist::Port object is created by Verilog::Netlist::Module for every port connection in the module. =head1 ACCESSORS See also Verilog::Netlist::Subclass for additional accessors and methods. =over 4 =item $self->array Any array declaration for the port. This only applies to Verilog 1995 style ports which can declare port bits independently from the signal declarations. When using Verilog 2001 style ports, see the matching net declaration's data_type, msb and lsb methods instead, for example C<$module->find_net($port->name)->data_type>. =item $self->comment Returns any comments following the definition. keep_comments=>1 must be passed to Verilog::Netlist::new for comments to be retained. =item $self->data_type The SystemVerilog data type of the port. =item $self->direction The direction of the port: "in", "out", or "inout". =item $self->module Reference to the Verilog::Netlist::Module the port is in. =item $self->name The name of the port. =item $self->net Reference to the Verilog::Netlist::Net the port connects to. Only valid after the netlist is linked. =item $self->type Approximately an alias of data_type for backward compatibility. Do not use for new applications. =back =head1 MEMBER FUNCTIONS See also Verilog::Netlist::Subclass for additional accessors and methods. =over 4 =item $self->dump Prints debugging information for this port. =back =head1 DISTRIBUTION Verilog-Perl is part of the L free Verilog EDA software tool suite. The latest version is available from CPAN and from L. Copyright 2000-2024 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. =head1 AUTHORS Wilson Snyder =head1 SEE ALSO L, L L =cut Verilog-Perl-3.482/Netlist/ContAssign.pm0000644000177100017500000000631514553624343020062 0ustar wsnyderwsnyder# Verilog - Verilog Perl Interface # See copyright, etc in below POD section. ###################################################################### package Verilog::Netlist::ContAssign; use Verilog::Netlist; use Verilog::Netlist::Subclass; use vars qw($VERSION @ISA); use strict; @ISA = qw(Verilog::Netlist::ContAssign::Struct Verilog::Netlist::Subclass); $VERSION = '3.482'; structs('new', 'Verilog::Netlist::ContAssign::Struct' =>[name => '$', #' # Unique ID keyword => '$', #' # Keyword name filename => '$', #' # Filename this came from lineno => '$', #' # Linenumber this came from userdata => '%', # User information attributes => '%', #' # Misc attributes for systemperl or other processors # lhs => '$', #' # Left hand side of assignment rhs => '$', #' # Right hand side of assignment module => '$', #' # Module reference ]); sub delete { my $self = shift; my $h = $self->module->_statements; delete $h->{$self->name}; return undef; } ###################################################################### #### Methods sub logger { my $self = shift; return $self->netlist->logger; } sub netlist { my $self = shift; return $self->module->netlist; } sub lint {} sub link {} sub verilog_text { my $self = shift; my @out = ($self->keyword," ",$self->lhs," = ",$self->rhs,";"); return (wantarray ? @out : join('',@out)); } sub dump { my $self = shift; my $indent = shift||0; print " "x$indent,"ContAssign:",$self->keyword," lhs:",$self->lhs," rhs:",$self->rhs; print "\n"; } ###################################################################### #### Package return 1; __END__ =pod =head1 NAME Verilog::Netlist::ContAssign - ContAssign assignment =head1 SYNOPSIS use Verilog::Netlist; ... foreach my $cont ($module->statements) print $cont->name; =head1 DESCRIPTION A Verilog::Netlist::ContAssign object is created by Verilog::Netlist for every continuous assignment statement in the current module. =head1 ACCESSORS See also Verilog::Netlist::Subclass for additional accessors and methods. =over 4 =item $self->keyword Keyword used to declare the assignment. Currently "assign" is the only supported value. =item $self->lhs Left hand side of the assignment. =item $self->module Pointer to the module the cell is in. =item $self->netlist Reference to the Verilog::Netlist the cell is under. =item $self->rhs Right hand side of the assignment. =back =head1 MEMBER FUNCTIONS See also Verilog::Netlist::Subclass for additional accessors and methods. =over 4 =item $self->dump Prints debugging information for this cell. =back =head1 DISTRIBUTION Verilog-Perl is part of the L free Verilog EDA software tool suite. The latest version is available from CPAN and from L. Copyright 2000-2024 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. =head1 AUTHORS Wilson Snyder =head1 SEE ALSO L, L L =cut Verilog-Perl-3.482/Netlist/Defparam.pm0000644000177100017500000000625214553624343017531 0ustar wsnyderwsnyder# Verilog - Verilog Perl Interface # See copyright, etc in below POD section. ###################################################################### package Verilog::Netlist::Defparam; use Verilog::Netlist; use Verilog::Netlist::Subclass; use vars qw($VERSION @ISA); use strict; @ISA = qw(Verilog::Netlist::Defparam::Struct Verilog::Netlist::Subclass); $VERSION = '3.482'; structs('new', 'Verilog::Netlist::Defparam::Struct' =>[name => '$', #' # Unique ID keyword => '$', #' # Keyword name filename => '$', #' # Filename this came from lineno => '$', #' # Linenumber this came from userdata => '%', # User information attributes => '%', #' # Misc attributes for systemperl or other processors # lhs => '$', #' # Left hand side of assignment rhs => '$', #' # Right hand side of assignment module => '$', #' # Module reference ]); sub delete { my $self = shift; my $h = $self->module->_statements; delete $h->{$self->name}; return undef; } ###################################################################### #### Methods sub logger { my $self = shift; return $self->netlist->logger; } sub netlist { my $self = shift; return $self->module->netlist; } sub lint {} sub link {} sub verilog_text { my $self = shift; my @out = ($self->keyword," ",$self->lhs," = ",$self->rhs,";"); return (wantarray ? @out : join('',@out)); } sub dump { my $self = shift; my $indent = shift||0; print " "x$indent,"Defparam:",$self->keyword," lhs:",$self->lhs," rhs:",$self->rhs; print "\n"; } ###################################################################### #### Package return 1; __END__ =pod =head1 NAME Verilog::Netlist::Defparam - Defparam assignment =head1 SYNOPSIS use Verilog::Netlist; ... foreach my $cont ($module->statements) print $cont->name; =head1 DESCRIPTION A Verilog::Netlist::Defparam object is created by Verilog::Netlist for every defparam in the current module. =head1 ACCESSORS See also Verilog::Netlist::Subclass for additional accessors and methods. =over 4 =item $self->keyword Keyword used to declare the assignment. Currently "defparam" is the only supported value. =item $self->lhs Left hand side of the assignment. =item $self->module Pointer to the module the cell is in. =item $self->netlist Reference to the Verilog::Netlist the cell is under. =item $self->rhs Right hand side of the assignment. =back =head1 MEMBER FUNCTIONS See also Verilog::Netlist::Subclass for additional accessors and methods. =over 4 =item $self->dump Prints debugging information for this cell. =back =head1 DISTRIBUTION Verilog-Perl is part of the L free Verilog EDA software tool suite. The latest version is available from CPAN and from L. Copyright 2000-2024 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. =head1 AUTHORS Wilson Snyder =head1 SEE ALSO L, L L =cut Verilog-Perl-3.482/Netlist/File.pm0000644000177100017500000003744514553624343016701 0ustar wsnyderwsnyder# Verilog - Verilog Perl Interface # See copyright, etc in below POD section. ###################################################################### package Verilog::Netlist::File; use Carp; use Verilog::Netlist; use Verilog::Netlist::Subclass; use vars qw($VERSION @ISA); use strict; @ISA = qw(Verilog::Netlist::File::Struct Verilog::Netlist::Subclass); $VERSION = '3.482'; structs('new', 'Verilog::Netlist::File::Struct' =>[name => '$', #' # Filename this came from basename => '$', #' # Basename of the file netlist => '$', #' # Netlist is a member of userdata => '%', # User information attributes => '%', #' # Misc attributes for systemperl or other processors comment => '$', #' # Comment provided by user is_libcell => '$', #' # True if is a library cell preproc => '$', #' # Preprocessor object # For special procedures _interfaces => '%', # For autosubcell_include _modules => '%', # For autosubcell_include ]); ###################################################################### ###################################################################### #### Read class package Verilog::Netlist::File::Parser; use Verilog::SigParser; use Verilog::Preproc; use base qw(Verilog::SigParser); use strict; sub new { my $class = shift; my %params = (preproc => "Verilog::Preproc", @_); # filename=> my $preproc_class = $params{preproc}; delete $params{preproc}; # Remove as preproc doesn't need passing down to Preprocessor # A new file; make new information $params{fileref} or die "%Error: No fileref parameter?"; $params{netlist} = $params{fileref}->netlist; my $parser = $class->SUPER::new (%params, modref=>undef, # Module being parsed now cellref=>undef, # Cell being parsed now _cmtref=>undef, # Object to attach comments to # Must parse all files in same compilation unit with # same symbol_table, or a package won't exist for link() symbol_table => $params{netlist}->{symbol_table}, ); my @opt; push @opt, (options=>$params{netlist}{options}) if $params{netlist}{options}; my $meta = $params{metacomment}; if ($meta) { die "%Error: 'metacomment' arg of Netlist or read_file() must be a hash," unless (ref($meta) eq 'HASH'); push @opt, metacomments=>[ grep({ $meta->{$_} } keys %$meta) ]; push @opt, keep_comments=>($params{netlist}{keep_comments} || 1); } elsif ($params{netlist}{keep_comments}) { push @opt, keep_comments=>$params{netlist}{keep_comments}; } else { push @opt, keep_comments=>0; } push @opt, keep_whitespace=>1; # So we don't loose newlines push @opt, include_open_nonfatal=>1 if $params{netlist}{include_open_nonfatal}; push @opt, synthesis=>1 if $params{netlist}{synthesis}; my $preproc = $preproc_class->new(@opt, parent => $params{fileref}); $params{fileref}->preproc($preproc); $preproc->open($params{filename}); $parser->parse_preproc_file($preproc); return $parser; } sub contassign { my $self = shift; my $keyword = shift; my $lhs = shift; my $rhs = shift; print " ContAssign $keyword $lhs\n" if $Verilog::Netlist::Debug; my $modref = $self->{modref}; if (!$modref) { return $self->error("CONTASSIGN outside of module definition", $lhs); } $modref->new_contassign (filename=>$self->filename, lineno=>$self->lineno, keyword=>$keyword, lhs=>$lhs, rhs=>$rhs); } sub defparam { my $self = shift; my $keyword = shift; my $lhs = shift; my $rhs = shift; print " Defparam $keyword $lhs\n" if $Verilog::Netlist::Debug; my $modref = $self->{modref}; if (!$modref) { return $self->error("DEFPARAM outside of module definition", $lhs); } $modref->new_defparam (filename=>$self->filename, lineno=>$self->lineno, keyword=>$keyword, lhs=>$lhs, rhs=>$rhs); } sub interface { my $self = shift; my $keyword = shift; my $name = shift; my $fileref = $self->{fileref}; my $netlist = $self->{netlist}; print "Interface $name\n" if $Verilog::Netlist::Debug; $self->{modref} = $netlist->new_interface (name=>$name, filename=>$self->filename, lineno=>$self->lineno); $fileref->_interfaces($name, $self->{modref}); $self->{_cmtpre} = undef; $self->{_cmtref} = $self->{modref}; } sub modport { my $self = shift; my $keyword = shift; my $name = shift; print " Modport $name\n" if $Verilog::Netlist::Debug; my $modref = $self->{modref}; if (!$modref) { return $self->error("MODPORT outside of interface definition", $name); } $self->{_modportref} = $modref->new_modport (name=>$name, filename=>$self->filename, lineno=>$self->lineno); $self->{_cmtpre} = undef; $self->{_cmtref} = $self->{modref}; } sub module { my $self = shift; my $keyword = shift; my $name = shift; my $orderref = shift; my $in_celldefine = shift; my $fileref = $self->{fileref}; my $netlist = $self->{netlist}; print "Module $name\n" if $Verilog::Netlist::Debug; $self->{modref} = $netlist->new_module (name=>$name, keyword=>$keyword, is_libcell=>($fileref->is_libcell() || $in_celldefine), filename=>$self->filename, lineno=>$self->lineno); $fileref->_modules($name, $self->{modref}); $self->{_cmtpre} = undef; $self->{_cmtref} = $self->{modref}; } sub program { my $self = shift; $self->module(@_); } sub endinterface { my $self = shift; $self->endmodule(@_); } sub endmodport { my $self = shift; $self->{_cmtpre} = undef; $self->{_cmtref} = $self->{modref}; $self->{_modportref} = undef; } sub endmodule { my $self = shift; $self->{_cmtpre} = undef; $self->{_cmtref} = undef; # Assume all module comments are inside the module, not after $self->{modref} = undef; } sub endprogram { my $self = shift; $self->endmodule(@_); } sub attribute { my $self = shift; my $text = shift||''; my $modref = $self->{modref}; my ($category, $name, $eql, $rest); if ($text =~ m!^([\$A-Za-z]\w*)\s+ (\w+) (\s*=\s*)? (.*) !x) { ($category, $name, $eql, $rest) = ($1, $2, ($3 || ""), $4); if ($eql ne "") { $eql = "="; } my $cleaned = ($category ." ". $name . $eql . $rest); if ($Verilog::Netlist::Debug) { printf +("%d: Attribute '%s'\n", $self->lineno, $cleaned); } # Treat as module-level if attribute appears before any declarations. if ($modref) { my $attr = $modref->new_attr($cleaned); } } } sub port { my $self = shift; my $name = shift; my $objof = shift; my $direction = shift; my $type = shift; my $array = shift; my $pinnum = shift; return if !($objof eq 'module' || $objof eq 'interface' || $objof eq 'modport'); my $underref = $self->{_modportref} || $self->{modref}; if ($pinnum) { # Else a "input" etc outside the "(...)"s $underref->_portsordered($pinnum-1, $name); # -1 because [0] has first pin } if ($direction) { # Else just a pin number without declaration my $port = $underref->new_port (name=>$name, filename=>$self->filename, lineno=>$self->lineno, direction=>$direction, data_type=>$type, array=>$array, comment=>undef,); } } sub var { my $self = shift; #use Data::Dumper; print " DEBUG: var callback: ",Dumper(\@_); my $decl_type = shift; my $name = shift; my $objof = shift; my $net_type = shift; my $data_type = shift; my $array = shift; my $value = shift; print " Sig $name dt=$decl_type nt=$net_type d=$data_type\n" if $Verilog::Netlist::Debug; return if !($objof eq 'module' || $objof eq 'interface' || $objof eq 'modport' || $objof eq 'netlist'); my $msb; my $lsb; if ($data_type && $data_type =~ /\[(.*):(.*)\]/) { $msb = $1; $lsb = $2; } elsif ($data_type && $data_type =~ /\[(.*)\]/) { $msb = $lsb = $1; } my $underref = $self->{_modportref} || $self->{modref}; if ($objof eq 'netlist') { $underref = $self->{netlist}->new_root_module (filename=>$self->filename, lineno=>$self->lineno); } if (!$underref) { return $self->error("Signal declaration outside of module definition", $name); } my $signed = ($data_type =~ /signed/); my $net = $underref->find_net($name); $net or $net = $underref->new_net (name=>$name, filename=>$self->filename, lineno=>$self->lineno, simple_type=>1, data_type=>$data_type, array=>$array, comment=>$self->{_cmtpre}, msb=>$msb, lsb=>$lsb, net_type=>$net_type, decl_type=>$decl_type, signed=>$signed, value=>$value, ); $net->data_type($data_type); # If it was declared earlier as in/out etc $net->net_type($net_type) if $net_type; # (from a single non-typed input/output stmt), remark the type now $self->{_cmtpre} = undef; $self->{_cmtref} = $net; } sub instant { my $self = shift; my $submodname = shift; my $instname = shift; my $range = shift; print " Cell $instname\n" if $Verilog::Netlist::Debug; my $modref = $self->{modref}; if (!$modref) { return $self->error("CELL outside of module definition", $instname); } $self->{cellref} = $modref->new_cell (name=>$instname, filename=>$self->filename, lineno=>$self->lineno, submodname=>$submodname, range=>$range,); $self->{_cmtpre} = undef; $self->{_cmtref} = $self->{cellref}; } sub endcell { my $self = shift; $self->{_cmtpre} = undef; $self->{_cmtref} = $self->{cellref}; # Comments after cell decl go to the cell } sub parampin { my $self = shift; my $pin = shift; my $conn = shift; my $number = shift; my $prev = $self->{cellref}->params(); $prev .= ", " if $prev; $prev .= ($pin ? ".$pin($conn)" : $conn); $self->{cellref}->params($prev); } sub pin { my $self = shift; if (!$self->{use_pinselects}) { $self->pinselects(@_); } } sub pinselects { my $self = shift; my $pin = shift; my $nets = shift; my $number = shift; my $hasnamedports = (($pin||'') ne ''); $pin = "pin".$number if !$hasnamedports; my $net_cnt = scalar($nets); print " Pin $pin $number (connected to $net_cnt nets) \n" if $Verilog::Netlist::Debug; my $cellref = $self->{cellref}; if (!$cellref) { return $self->error("PIN outside of cell definition", $pin); } my %params = ( name => $pin, portname => $pin, portnumber => $number, pinnamed => $hasnamedports, filename => $self->filename, lineno => $self->lineno, ); if ($self->{use_pinselects}) { $params{pinselects} = $nets; } else { $params{netname} = $nets; } my $pinref = $cellref->new_pin(%params); # If any pin uses call-by-name, then all are assumed to use call-by-name $cellref->byorder(1) if !$hasnamedports; $self->{_cmtpre} = undef; $self->{_cmtref} = $pinref; } sub keyword { # OVERRIDE Verilog::Parse calls when keyword occurs # Note we use_cb_keyword only if comments are parsed! my $self = shift; # Parser invoked $self->{_cmtpre} = undef; $self->{_cmtref} = undef; } sub comment { my $self = shift; # OVERRIDE Verilog::Parse calls when comment occurs my $text = shift; # Includes comment delimiters if ($self->{_cmtref}) { my $old = $self->{_cmtref}->comment(); $old = (defined $old) ? $old."\n".$text : $text; $self->{_cmtref}->comment($old); } elsif ($self->{modref}) { my $old = $self->{_cmtpre}; $old = (defined $old) ? $old."\n".$text : $text; $self->{_cmtpre} = $old; } } # sub operator { ... Disabled by new(use_cmt_operator => 0) # sub number { ... Disabled by new(use_cmt_number => 0) # sub string { ... Disabled by new(use_cmt_string => 0) # sub symbol { ... Disabled by new(use_cmt_symbol => 0) sub error { my $self = shift; my $text = shift; my $fileref = $self->{fileref}; # Call Verilog::Netlist::Subclass's error reporting, it will track # errors $fileref->error($self, "$text\n"); } sub warn { my $self = shift; my $text = shift; my $fileref = $self->{fileref}; $fileref->warn($self, "$text\n"); } package Verilog::Netlist::File; ###################################################################### ###################################################################### #### Functions sub delete { my $self = shift; $self->netlist(undef); # Break circular $self->preproc(undef); # Break circular } sub logger { my $self = shift; return $self->netlist->logger; } sub read { my %params = (lookup_type=>'module', @_); # netlist=>, filename=>, per-file options my $filename = $params{filename} or croak "%Error: ".__PACKAGE__."::read_file (filename=>) parameter required, stopped"; my $netlist = $params{netlist} or croak("Call Verilog::Netlist::read_file instead,"); my $filepath = $netlist->resolve_filename($filename, $params{lookup_type}); if (!$filepath) { if ($params{error_self}) { $params{error_self}->error("Cannot find $filename\n"); } elsif (!defined $params{error_self}) { die "%Error: Cannot find $filename\n"; } # 0=suppress error return undef; } print __PACKAGE__."::read_file $filepath\n" if $Verilog::Netlist::Debug; my $fileref = $netlist->new_file(name=>$filepath, is_libcell=>$params{is_libcell}||0, ); my $keep_cmt = ($params{keep_comments} || $netlist->{keep_comments}); my $parser_class = ($params{parser} || $netlist->{parser}); my $parser = $parser_class->new ( fileref => $fileref, filename => $filepath, # for ->read metacomment => ($params{metacomment} || $netlist->{metacomment}), keep_comments => $keep_cmt, use_vars => ($params{use_vars} || $netlist->{use_vars}), use_pinselects => ($params{use_pinselects} || $netlist->{use_pinselects}), use_protected => 0, preproc => ($params{preproc} || $netlist->{preproc}), # Callbacks we need; disable unused for speed use_cb_attribute => 1, use_cb_comment => $keep_cmt, use_cb_keyword => $keep_cmt, use_cb_number => 0, use_cb_operator => 0, use_cb_string => 0, use_cb_symbol => 0, ); return $fileref; } sub link { # For backward compatibility for SystemC child class, call _link $_[0]->_link(@_); } sub _link { } sub dump { my $self = shift; my $indent = shift||0; print " "x$indent,"File:",$self->name(),"\n"; } ###################################################################### #### Package return 1; __END__ =pod =head1 NAME Verilog::Netlist::File - File containing Verilog code =head1 SYNOPSIS use Verilog::Netlist; my $nl = new Verilog::Netlist; my $fileref = $nl->read_file(filename=>'filename'); =head1 DESCRIPTION Verilog::Netlist::File allows Verilog::Netlist objects to be read and written in Verilog format. =head1 ACCESSORS See also Verilog::Netlist::Subclass for additional accessors and methods. =over 4 =item $self->basename The filename of the file with any path and . suffix stripped off. =item $self->name The filename of the file. =item $self->preproc The Verilog::Preproc object this file is using. =back =head1 MEMBER FUNCTIONS See also Verilog::Netlist::Subclass for additional accessors and methods. =over 4 =item $self->read Generally called as $netlist->read_file. Pass a hash of parameters. Reads the filename=> parameter, parsing all instantiations, ports, and signals, and creating Verilog::Netlist::Module structures. =item $self->dump Prints debugging information for this file. =back =head1 DISTRIBUTION Verilog-Perl is part of the L free Verilog EDA software tool suite. The latest version is available from CPAN and from L. Copyright 2000-2024 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. =head1 AUTHORS Wilson Snyder =head1 SEE ALSO L, L L =cut Verilog-Perl-3.482/Netlist/Logger.pm0000644000177100017500000001024614553624343017227 0ustar wsnyderwsnyder# Verilog - Verilog Perl Interface # See copyright, etc in below POD section. ###################################################################### package Verilog::Netlist::Logger; require Exporter; use vars qw($VERSION); use strict; $VERSION = '3.482'; # We don't use Verilog::Netlist::Subclass, as this is called from it! ###################################################################### #### Constructors sub new { my $class = shift; my $self = { _warnings => 0, _errors => 0, _error_unlink_files => {}, @_ }; bless $self, $class; return $self; } ###################################################################### #### Accessors sub errors { my $self = shift; $self->{_errors} = shift if $#_>=0; return $self->{_errors}; } sub warnings { my $self = shift; $self->{_warnings} = shift if $#_>=0; return $self->{_warnings}; } ###################################################################### #### Error Handling sub info { my $self = shift; my $objref = shift; CORE::warn "-Info: ".$objref->fileline.": ".join('',@_); } sub warn { my $self = shift; my $objref = shift; CORE::warn "%Warning: ".$objref->fileline.": ".join('',@_); $self->warnings($self->warnings+1); } sub error { my $self = shift; my $objref = shift; CORE::warn "%Error: ".$objref->fileline.": ".join('',@_); $self->errors($self->errors+1); } sub exit_if_error { my $self = shift; my %params = @_; my $allow = $params{allow} || ""; if ($self->errors || ($self->warnings && $allow !~ /warning/)) { CORE::warn "Exiting due to errors\n"; exit(10); } return ($self->errors + $self->warnings); } sub unlink_if_error { my $self = shift; $self->{_error_unlink_files}{$_[0]} = 1; } sub error_unlink { my $self = shift; foreach my $file (keys %{$self->{_error_unlink_files}}) { unlink $file; delete $self->{_error_unlink_files}{$file}; } } sub DESTROY { my $self = shift; my $has_err = $? || $self->errors || $self->warnings; if ($has_err) { $self->error_unlink; } } ###################################################################### #### Package return 1; __END__ =pod =head1 NAME Verilog::Netlist::Logger - Error collection and reporting =head1 SYNOPSIS use Verilog::Netlist::Logger; ... my $self = Verilog::Netlist::Logger->new(); $self->info("We're here\n"); $self->warn("Things look bad\n"); $self->error("Things are even worse\n"); $self->exit_if_error(); =head1 DESCRIPTION The Verilog::Netlist::Logger is used to report all errors detected by Verilog::Netlist::* structures. By default, Verilog::Netlist creates a new Logger object, and passes it down to all contained objects. Users may create their own logger objects to catch or otherwise handle error messages. =head1 MEMBER FUNCTIONS =over 4 =item $self->error(object, I) Print an error about the object in a standard format. The object must have a fileline method. =item $self->exit_if_error([allow=>'warning']) Exits the program if any errors were detected. Optionally specify allow=>'warning' to ignore warnings. =item $self->info(I) Print an informational about the object in a standard format. The object must have a fileline method. =item $self->lineno() The line number the entity was created on. =item $self->unlink_if_error(I) Requests the given file be deleted if any errors are detected when the Logger object is destroyed. Used for temporary files. =item $self->warn(I) Print a warning about the object in a standard format. The object must have a fileline method. =back =head1 DISTRIBUTION Verilog-Perl is part of the L free Verilog EDA software tool suite. The latest version is available from CPAN and from L. Copyright 2000-2024 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. =head1 AUTHORS Wilson Snyder =head1 SEE ALSO L, L, L =cut Verilog-Perl-3.482/Netlist/Interface.pm0000644000177100017500000002355414553624343017716 0ustar wsnyderwsnyder# Verilog - Verilog Perl Interface # See copyright, etc in below POD section. ###################################################################### package Verilog::Netlist::Interface; use Verilog::Netlist; use Verilog::Netlist::ModPort; use Verilog::Netlist::Net; use Verilog::Netlist::Pin; use Verilog::Netlist::Subclass; use vars qw($VERSION @ISA); use strict; @ISA = qw(Verilog::Netlist::Interface::Struct Verilog::Netlist::Subclass); $VERSION = '3.482'; structs('new', 'Verilog::Netlist::Interface::Struct' =>[name => '$', #' # Name of the module filename => '$', #' # Filename this came from lineno => '$', #' # Linenumber this came from netlist => '$', #' # Netlist is a member of userdata => '%', # User information attributes => '%', #' # Misc attributes for systemperl or other processors # comment => '$', #' # Comment provided by user _cells => '%', # hash of Verilog::Netlist::Cells _modports => '%', # hash of Verilog::Netlist::ModPorts _ports => '%', # hash of Verilog::Netlist::Ports _portsordered=> '@', # list of Verilog::Netlist::Ports as ordered in list of ports _nets => '%', # hash of Verilog::Netlist::Nets _level => '$', # Depth in hierarchy (if calculated) ]); sub delete { my $self = shift; foreach my $oref ($self->nets) { $oref->delete; } foreach my $oref ($self->ports) { $oref->delete; } foreach my $oref ($self->modports) { $oref->delete; } foreach my $oref ($self->cells) { $oref->delete; } my $h = $self->netlist->{_interfaces}; delete $h->{$self->name}; return undef; } ###################################################################### sub is_top {} # Ignored, for module compatibility sub keyword { return 'interface'; } sub logger { return $_[0]->netlist->logger; } sub find_modport { my $self = shift; my $search = shift; return $self->_modports->{$search} || $self->_modports->{"\\".$search." "}; } sub find_port { my $self = shift; my $search = shift; return $self->_ports->{$search} || $self->_ports->{"\\".$search." "}; } sub find_port_by_index { my $self = shift; my $myindex = shift; # @{$self->_portsordered}[$myindex-1] returns the name of # the port in the module at this index. Then, this is # used to find the port reference via the port hash return $self->_ports->{@{$self->_portsordered}[$myindex-1]}; } sub find_cell { my $self = shift; my $search = shift; return $self->_cells->{$search} || $self->_cells->{"\\".$search." "}; } sub find_net { my $self = shift; my $search = shift; my $rtn = $self->_nets->{$search}||""; #print "FINDNET ",$self->name, " SS $search $rtn\n"; return $self->_nets->{$search} || $self->_nets->{"\\".$search." "}; } sub attrs_sorted { return (sort {$a cmp $b} @{$_[0]->attrs}); } sub cells { return (values %{$_[0]->_cells}); } sub cells_sorted { return (sort {$a->name() cmp $b->name()} (values %{$_[0]->_cells})); } sub modports { return (values %{$_[0]->_modports}); } sub modports_sorted { return (sort {$a->name() cmp $b->name()} (values %{$_[0]->_modports})); } sub nets { return (values %{$_[0]->_nets}); } sub nets_sorted { return (sort {$a->name() cmp $b->name()} (values %{$_[0]->_nets})); } sub ports { return (values %{$_[0]->_ports}); } sub ports_sorted { return (sort {$a->name() cmp $b->name()} (values %{$_[0]->_ports})); } sub ports_ordered { my $self = shift; return map {$self->_ports->{$_}} @{$self->_portsordered}; } sub nets_and_ports_sorted { return Verilog::Netlist::Module::nets_and_ports_sorted(@_); } sub new_net { my $self = shift; # @_ params # Create a new net under this my $netref = new Verilog::Netlist::Net(direction=>'net', data_type=>'wire', @_, module=>$self, ); $self->_nets($netref->name(), $netref); return $netref; } sub new_attr { my $self = shift; my $clean_text = shift; push @{$self->attrs}, $clean_text; } sub new_modport { my $self = shift; # @_ params my $oref = new Verilog::Netlist::ModPort(@_, module=>$self,); $self->_modports($oref->name(), $oref); return $oref; } sub new_port { my $self = shift; # @_ params # Create a new port under this module my $portref = new Verilog::Netlist::Port(@_, module=>$self,); $self->_ports($portref->name(), $portref); return $portref; } sub new_cell { return Verilog::Netlist::Module::new_cell(@_); } sub level { my $self = shift; my $level = $self->_level; return $level if defined $level; $self->_level(2); # Interfaces are never up "top" foreach my $cell ($self->cells) { if ($cell->submod) { my $celllevel = $cell->submod->level; $self->_level($celllevel+1) if $celllevel >= $self->_level; } } return $self->_level; } sub link { my $self = shift; # Ports create nets, so link ports before nets foreach my $portref ($self->ports) { $portref->_link(); } foreach my $netref ($self->nets) { $netref->_link(); } foreach my $oref ($self->modports) { $oref->_link(); } foreach my $cellref ($self->cells) { $cellref->_link(); } } sub lint { my $self = shift; if ($self->netlist->{use_vars}) { foreach my $portref ($self->ports) { $portref->lint(); } foreach my $netref ($self->nets) { $netref->lint(); } } foreach my $cellref ($self->cells) { $cellref->lint(); } } sub verilog_text { my $self = shift; my @out = "interface ".$self->name." (\n"; my $indent = " "; # Port list my $comma=""; push @out, $indent; foreach my $portref ($self->ports_sorted) { push @out, $comma, $portref->verilog_text; $comma = ", "; } push @out, ");\n"; foreach my $netref ($self->nets_sorted) { push @out, $indent, $netref->verilog_text, "\n"; } foreach my $oref ($self->modports_sorted) { push @out, $indent, $oref->verilog_text, "\n"; } foreach my $cellref ($self->cells_sorted) { push @out, $indent, $cellref->verilog_text, "\n"; } push @out, "endinterface\n"; return (wantarray ? @out : join('',@out)); } sub dump { my $self = shift; my $indent = shift||0; my $norecurse = shift; print " "x$indent,"Interface:",$self->name()," File:",$self->filename(),"\n"; if (!$norecurse) { foreach my $portref ($self->ports_sorted) { $portref->dump($indent+2); } foreach my $netref ($self->nets_sorted) { $netref->dump($indent+2); } foreach my $oref ($self->modports_sorted) { $oref->dump($indent+2); } foreach my $cellref ($self->cells_sorted) { $cellref->dump($indent+2); } } } ###################################################################### #### Package return 1; __END__ =pod =head1 NAME Verilog::Netlist::Interface - Interface within a Verilog Netlist =head1 SYNOPSIS use Verilog::Netlist; ... my $interface = $netlist->find_interface('name'); my $cell = $self->find_cell('name') my $port = $self->find_port('name') my $net = $self->find_net('name') =head1 DESCRIPTION A Verilog::Netlist::Interface object is created by Verilog::Netlist for every interface in the design. =head1 ACCESSORS See also Verilog::Netlist::Subclass for additional accessors and methods. =over 4 =item $self->comment Returns any comments following the definition. keep_comments=>1 must be passed to Verilog::Netlist::new for comments to be retained. =item $self->find_port_by_index Returns the port name associated with the given index. =item $self->modports Returns list of references to Verilog::Netlist::ModPort in the interface. =item $self->modports_sorted Returns list of references to Verilog::Netlist::ModPort in the interface sorted by name. =item $self->name The name of the interface. =item $self->netlist Reference to the Verilog::Netlist the interface is under. =item $self->nets Returns list of references to Verilog::Netlist::Net in the interface. =item $self->nets_sorted Returns list of name sorted references to Verilog::Netlist::Net in the interface. =item $self->nets_and_ports_sorted Returns list of name sorted references to Verilog::Netlist::Net and Verilog::Netlist::Port in the interface. =item $self->ports Returns list of references to Verilog::Netlist::Port in the interface. =item $self->ports_ordered Returns list of references to Verilog::Netlist::Port in the interface sorted by pin number. =item $self->ports_sorted Returns list of references to Verilog::Netlist::Port in the interface sorted by name. =back =head1 MEMBER FUNCTIONS See also Verilog::Netlist::Subclass for additional accessors and methods. =over 4 =item $self->find_net(I) Returns Verilog::Netlist::Net matching given name. =item $self->level Returns the reverse depth of this interface with respect to other modules and interfaces. See also Netlist's modules_sorted_level. =item $self->lint Checks the interface for errors. =item $self->link Creates interconnections between this interface and other interfaces. =item $self->new_net Creates a new Verilog::Netlist::Net. =item $self->dump Prints debugging information for this interface. =item $self->verilog_text Returns verilog code which represents this interface. Returned as an array that must be joined together to form the final text string. The netlist must be already ->link'ed for this to work correctly. =back =head1 DISTRIBUTION Verilog-Perl is part of the L free Verilog EDA software tool suite. The latest version is available from CPAN and from L. Copyright 2000-2024 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. =head1 AUTHORS Wilson Snyder =head1 SEE ALSO L, L L =cut Verilog-Perl-3.482/Netlist/ModPort.pm0000644000177100017500000001564114553624343017400 0ustar wsnyderwsnyder# Verilog - Verilog Perl Modport # See copyright, etc in below POD section. ###################################################################### package Verilog::Netlist::ModPort; use Verilog::Netlist; use Verilog::Netlist::Net; use Verilog::Netlist::Subclass; use vars qw($VERSION @ISA); use strict; @ISA = qw(Verilog::Netlist::ModPort::Struct Verilog::Netlist::Subclass); $VERSION = '3.482'; structs('new', 'Verilog::Netlist::ModPort::Struct' =>[name => '$', #' # Name of the module filename => '$', #' # Filename this came from lineno => '$', #' # Linenumber this came from module => '$', #' # Interface is a member of userdata => '%', # User information attributes => '%', #' # Misc attributes for systemperl or other processors # comment => '$', #' # Comment provided by user _ports => '%', # hash of Verilog::Netlist::Ports _portsordered=> '@', # list of Verilog::Netlist::Ports as ordered in list of ports _nets => '%', # hash of Verilog::Netlist::Nets ]); sub delete { my $self = shift; foreach my $oref ($self->nets) { $oref->delete; } foreach my $oref ($self->ports) { $oref->delete; } my $h = $self->module->{_modports}; delete $h->{$self->name}; return undef; } ###################################################################### sub netlist { return $_[0]->module->netlist; } sub is_top {} # Ignored, for module compatibility sub keyword { return 'modport'; } sub logger { return $_[0]->netlist->logger; } sub find_net { my $self = shift; my $search = shift; my $rtn = $self->_nets->{$search}||""; #print "FINDNET ",$self->name, " SS $search $rtn\n"; return $self->_nets->{$search} || $self->_nets->{"\\".$search." "}; } sub find_port { my $self = shift; my $search = shift; return $self->_ports->{$search} || $self->_ports->{"\\".$search." "}; } sub find_port_by_index { my $self = shift; my $myindex = shift; # @{$self->_portsordered}[$myindex-1] returns the name of # the port in the module at this index. Then, this is # used to find the port reference via the port hash return $self->_ports->{@{$self->_portsordered}[$myindex-1]}; } sub attrs_sorted { return (sort {$a cmp $b} @{$_[0]->attrs}); } sub nets { return (values %{$_[0]->_nets}); } sub nets_sorted { return (sort {$a->name() cmp $b->name()} (values %{$_[0]->_nets})); } sub ports { return (values %{$_[0]->_ports}); } sub ports_sorted { return (sort {$a->name() cmp $b->name()} (values %{$_[0]->_ports})); } sub ports_ordered { my $self = shift; return map {$self->_ports->{$_}} @{$self->_portsordered}; } sub nets_and_ports_sorted { return Verilog::Netlist::Module::nets_and_ports_sorted(@_); } sub new_attr { my $self = shift; my $clean_text = shift; push @{$self->attrs}, $clean_text; } sub new_net { my $self = shift; # @_ params # Create a new net under this my $netref = new Verilog::Netlist::Net(direction=>'net', data_type=>'wire', @_, module=>$self, ); $self->_nets($netref->name(), $netref); return $netref; } sub new_port { my $self = shift; # @_ params # Create a new port under this module my $portref = new Verilog::Netlist::Port(@_, module=>$self,); $self->_ports($portref->name(), $portref); return $portref; } sub _link { my $self = shift; # Ports create nets, so link ports before nets foreach my $oref ($self->ports) { $oref->_link(); } } sub lint { my $self = shift; if ($self->netlist->{use_vars}) { foreach my $oref ($self->ports) { $oref->lint(); } } } sub verilog_text { my $self = shift; my @out = "modport ".$self->name." (\n"; my $indent = " "; # Port list my $comma=""; push @out, $indent; foreach my $oref ($self->ports_sorted) { push @out, $comma, $oref->verilog_text; $comma = ", "; } push @out, ");\n"; push @out, "endmodport\n"; return (wantarray ? @out : join('',@out)); } sub dump { my $self = shift; my $indent = shift||0; my $norecurse = shift; print " "x$indent,"ModPort:",$self->name()," File:",$self->filename(),"\n"; if (!$norecurse) { foreach my $oref ($self->ports_sorted) { $oref->dump($indent+2); } } } ###################################################################### #### Package return 1; __END__ =pod =head1 NAME Verilog::Netlist::ModPort - ModPort within a Verilog Interface =head1 SYNOPSIS use Verilog::Netlist; ... my $interface = $netlist->find_interface('name'); my $modport = $interface->find_modport('name') =head1 DESCRIPTION A Verilog::Netlist::ModPort object is created by Verilog::Netlist::Interface for every modport under the interface. =head1 METHODS See also Verilog::Netlist::Subclass for additional accessors and methods. =over 4 =item $self->comment Returns any comments following the definition. keep_comments=>1 must be passed to Verilog::Netlist::new for comments to be retained. =item $self->dump Prints debugging information for this modport. =item $self->find_port(I) Returns Verilog::Netlist::Net matching given name. =item $self->find_port_by_index Returns the port name associated with the given index. =item $self->module Returns Verilog::Netlist::Interface the ModPort belongs to. =item $self->lint Checks the modport for errors. =item $self->name The name of the modport. =item $self->netlist Reference to the Verilog::Netlist the modport is under. =item $self->nets Returns list of references to Verilog::Netlist::Net in the interface. =item $self->nets_sorted Returns list of name sorted references to Verilog::Netlist::Net in the interface. =item $self->nets_and_ports_sorted Returns list of name sorted references to Verilog::Netlist::Net and Verilog::Netlist::Port in the modport. =item $self->ports Returns list of references to Verilog::Netlist::Port in the modport. =item $self->ports_ordered Returns list of references to Verilog::Netlist::Port in the modport sorted by pin number. =item $self->ports_sorted Returns list of references to Verilog::Netlist::Port in the modport sorted by name. =item $self->verilog_text Returns verilog code which represents this modport. Returned as an array that must be joined together to form the final text string. The netlist must be already ->link'ed for this to work correctly. =back =head1 DISTRIBUTION Verilog-Perl is part of the L free Verilog EDA software tool suite. The latest version is available from CPAN and from L. Copyright 2000-2024 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. =head1 AUTHORS Wilson Snyder =head1 SEE ALSO L, L L L =cut Verilog-Perl-3.482/Netlist/Cell.pm0000644000177100017500000001730714553624343016674 0ustar wsnyderwsnyder# Verilog - Verilog Perl Interface # See copyright, etc in below POD section. ###################################################################### package Verilog::Netlist::Cell; use Verilog::Netlist; use Verilog::Netlist::Subclass; use vars qw($VERSION @ISA); use strict; @ISA = qw(Verilog::Netlist::Cell::Struct Verilog::Netlist::Subclass); $VERSION = '3.482'; structs('new', 'Verilog::Netlist::Cell::Struct' =>[name => '$', #' # Instantiation name filename => '$', #' # Filename this came from lineno => '$', #' # Linenumber this came from userdata => '%', # User information attributes => '%', #' # Misc attributes for systemperl or other processors # comment => '$', #' # Comment provided by user submodname => '$', #' # Which module it instantiates module => '$', #' # Module reference params => '$', #' # Textual description of parameters range => '$', #' # Range of ranged instance _pins => '%', # List of Verilog::Netlist::Pins byorder => '$', # True if Cell call uses order based pins # after link(): submod => '$', #' # Sub Module reference gateprim => '$', #' # Primitive (and/buf/cmos etc), but not UDPs # system perl _autoinst => '$', #' # Marked with AUTOINST tag ]); sub delete { my $self = shift; foreach my $pinref ($self->pins_sorted) { $pinref->delete; } my $h = $self->module->_cells; delete $h->{$self->name}; return undef; } ###################################################################### #### Methods sub logger { my $self = shift; return $self->netlist->logger; } sub netlist { my $self = shift; return $self->module->netlist; } sub _link_guts { my $self = shift; # This function is HOT, keep simple if (!$self->submod) { if (my $name = $self->submodname) { my $netlist = $self->netlist; my $sm = $netlist->find_module_or_interface_for_cell($name); if (!$sm) { my $name2 = $netlist->remove_defines($name); $sm = $netlist->find_module_or_interface_for_cell($name2) if $name ne $name2; } if ($sm) { $self->submod($sm); $sm->is_top(0); } } } } sub _link { my $self = shift; # This function is HOT, keep simple $self->_link_guts(); if (!$self->submod && Verilog::Language::is_gateprim($self->submodname)) { $self->gateprim(1); } if (!$self->submod() && !$self->gateprim && !$self->module->is_libcell() && $self->netlist->{link_read} && !$self->netlist->{_missing_submod}{$self->submodname} ) { print " Link_Read ",$self->submodname,"\n" if $Verilog::Netlist::Debug; # Try 1: Direct filename $self->netlist->read_file(filename=>$self->submodname, error_self=>0); $self->_link_guts(); # # Try 2: Libraries if (!$self->submod()) { $self->netlist->read_libraries(); $self->_link_guts(); } # Try 3: Bitch about missing file if (!$self->submod()) { $self->netlist->read_file(filename=>$self->submodname, error_self=>($self->netlist->{link_read_nonfatal} ? 0:$self)); } # Still missing if (!$self->submod()) { # Don't link this file again - speeds up if many common gate-ish missing primitives $self->netlist->{_missing_submod}{$self->submodname} = 1; } # Note if got it the new_module will add it to the _need_link list } # Link pins after module resolved, so don't do it multiple times if not found foreach my $pinref ($self->pins) { $pinref->_link(); } } sub lint { my $self = shift; if (!$self->submod() && !$self->gateprim && !$self->netlist->{link_read_nonfatal}) { $self->error($self,"Module/Program/Interface reference not found: ",$self->submodname(),,"\n"); } if ($self->netlist->{use_vars}) { foreach my $pinref ($self->pins) { $pinref->lint(); } } } sub verilog_text { my $self = shift; my @out = $self->submodname; if ($self->params) { push @out, " #(".$self->params.")"; } push @out, " ".$self->name; if ($self->range) { push @out, " ".$self->range; } push @out, " ("; my $comma=""; foreach my $pinref ($self->pins_sorted) { push @out, $comma if $comma; $comma=", "; push @out, $pinref->verilog_text; } push @out, ");"; return (wantarray ? @out : join('',@out)); } sub dump { my $self = shift; my $indent = shift||0; my $norecurse = shift; print " "x$indent,"Cell:",$self->name()," is-a:",$self->submodname(); print " ".$self->params if (($self->params||"") ne ""); print "\n"; if ($self->submod()) { $self->submod->dump($indent+10, 'norecurse'); } if (!$norecurse) { foreach my $pinref ($self->pins_sorted) { $pinref->dump($indent+2); } } } ###################################################################### #### Pins sub new_pin { my $self = shift; # @_ params # Create a new pin under this cell push @_, (cell=>$self); my $pinref = new Verilog::Netlist::Pin(@_); $self->_pins($pinref->name(), $pinref); return $pinref; } sub find_pin { my $self = shift; my $name = shift; return $self->_pins($name) || $self->_pins("\\".$name." "); } sub pins { return (values %{$_[0]->_pins}); } sub pins_sorted { return (sort {$a->name() cmp $b->name()} (values %{$_[0]->_pins})); } ###################################################################### #### Package return 1; __END__ =pod =head1 NAME Verilog::Netlist::Cell - Instantiated cell within a Verilog Netlist =head1 SYNOPSIS use Verilog::Netlist; ... my $cell = $module->find_cell('cellname'); print $cell->name; =head1 DESCRIPTION A Verilog::Netlist::Cell object is created by Verilog::Netlist for every instantiation in the current module. =head1 ACCESSORS See also Verilog::Netlist::Subclass for additional accessors and methods. =over 4 =item $self->comment Returns any comments following the definition. keep_comments=>1 must be passed to Verilog::Netlist::new for comments to be retained. =item $self->delete Delete the cell from the module it's under. =item $self->gateprim True if the cell is a gate primitive instantiation (buf/cmos/etc), but not a UDP. =item $self->module Pointer to the module the cell is in. =item $self->name The instantiation name of the cell. =item $self->netlist Reference to the Verilog::Netlist the cell is under. =item $self->pins List of Verilog::Netlist::Pin connections for the cell. =item $self->pins_sorted List of name sorted Verilog::Netlist::Pin connections for the cell. =item $self->range The range for the cell (e.g. "[1:0]") or false (i.e. undef or "") if not ranged. =item $self->submod Reference to the Verilog::Netlist::Module the cell instantiates. Only valid after the design is linked. =item $self->submodname The module name the cell instantiates (under the cell). =back =head1 MEMBER FUNCTIONS See also Verilog::Netlist::Subclass for additional accessors and methods. =over 4 =item $self->lint Checks the cell for errors. Normally called by Verilog::Netlist::lint. =item $self->new_pin Creates a new Verilog::Netlist::Pin connection for this cell. =item $self->pins_sorted Returns all Verilog::Netlist::Pin connections for this cell. =item $self->dump Prints debugging information for this cell. =back =head1 DISTRIBUTION Verilog-Perl is part of the L free Verilog EDA software tool suite. The latest version is available from CPAN and from L. Copyright 2000-2024 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. =head1 AUTHORS Wilson Snyder =head1 SEE ALSO L, L L =cut Verilog-Perl-3.482/Netlist/Subclass.pm0000644000177100017500000002117414553624343017571 0ustar wsnyderwsnyder# Verilog - Verilog Perl Interface # See copyright, etc in below POD section. ###################################################################### package Verilog::Netlist::Subclass; use Scalar::Util qw(weaken); use Carp; use Verilog::Netlist::Logger; require Exporter; use base qw(Exporter); use vars qw($VERSION @EXPORT); use strict; $VERSION = '3.482'; @EXPORT = qw(structs); # Maybe in the future. For now all users of this must do it themselves #struct ('Verilog::Netlist::Subclass' # =>[name => '$', #' # Name of the element # filename => '$', #' # Filename this came from # lineno => '$', #' # Linenumber this came from # logger => '%', # Logger object, or undef # userdata => '%', # User information # ]); ###################################################################### #### Member functions sub fileline { my $self = shift; return ($self->filename||"").":".($self->lineno||""); } ###################################################################### #### Error Handling our $_Subclass_Logger_Warned; sub logger { my $self = shift; # This provides forward compatibility to derived classes written before # Verilog-Perl 3.041. At some point this function will be removed; all # new derived classes should provide an override for this function. if (!$_Subclass_Logger_Warned) { warn "-Info: Object class missing logger method, update the package?: ".ref($self)."\n"; $_Subclass_Logger_Warned = Verilog::Netlist::Logger->new(); } return $_Subclass_Logger_Warned; } sub errors { my $self = shift; return $self->logger->errors; } sub warnings { my $self = shift; return $self->logger->warnings; } # Methods sub info { my $self = shift; my $objref = $self; $objref = shift if ref $_[0]; # Optional reference to object $self->logger->info($objref,@_); } sub warn { my $self = shift; my $objref = $self; $objref = shift if ref $_[0]; # Optional reference to object $self->logger->warn($objref,@_); } sub error { my $self = shift; my $objref = $self; $objref = shift if ref $_[0]; # Optional reference to object $self->logger->error($objref,@_); } sub exit_if_error { my $self = shift; return $self->logger->exit_if_error(@_); } sub unlink_if_error { my $self = shift; # Not documented; Depreciated in Verilog-Perl 3.041. # Applications should call the logger object's unlink_if_error directly. return $self->logger->unlink_if_error(@_); } ###################################################################### ###################################################################### ###################################################################### # # Prior to perl 5.6, Class::Struct's new didn't bless the arguments, # or allow parameter initialization! Later versions didn't support weak # references. # This code is thus from Class::Struct, copyright under the Artistic license sub structs { my $func = shift; my $baseclass = $_[0]; # Determine parameter list structure, one of: # struct (class => [ element-list ]) my ($class, @decls); my $base_type = ref $_[1]; if ($base_type eq 'ARRAY') { $class = shift; @decls = @{shift()}; confess "structs usage error" if @_; } else { confess "structs usage error"; } confess "structs usage error" if @decls % 2 == 1; # Create constructor. croak "function 'new' already defined in package $class" if do { no strict 'refs'; defined &{$class . "::new"} }; my @methods = (); my %refs = (); my %arrays = (); my %hashes = (); my %types; my $got_class = 0; my $out = ''; $out .= "{\n package $class;\n use Carp;\n"; $out .= " use Scalar::Util qw(weaken);\n\n"; $out .= " sub new {\n"; $out .= " my (\$class, \%init) = \@_;\n"; $out .= " \$class = __PACKAGE__ unless \@_;\n"; my $cnt = 0; my ($cmt, $elem); if ($base_type eq 'ARRAY') { $out .= " my(\$r) = [];\n"; } for (my $idx=0; $idx < @decls; $idx+=2) { my $name = $decls[$idx]; my $type = $decls[$idx+1]; $types{$name} = $type; push (@methods, $name); if ($base_type eq 'ARRAY') { $elem = "[$cnt]"; ++$cnt; $cmt = " # $name"; } if ($type =~ /^\*(.)/) { $refs{$name}++; $type = $1; } my $init = "defined(\$init{'$name'}) ? \$init{'$name'} :"; if ($type eq '@') { $out .= " croak 'Initializer for $name must be array reference'\n"; $out .= " if defined(\$init{'$name'}) && ref(\$init{'$name'}) ne 'ARRAY';\n"; $out .= " \$r->$elem = $init [];$cmt\n"; $arrays{$name}++; } elsif ($type eq '%') { $out .= " croak 'Initializer for $name must be hash reference'\n"; $out .= " if defined(\$init{'$name'}) && ref(\$init{'$name'}) ne 'HASH';\n"; $out .= " \$r->$elem = $init {};$cmt\n"; $hashes{$name}++; } elsif ($type eq '$') { $out .= " \$r->$elem = $init undef;$cmt\n"; } else{ croak "'$type' is not a valid struct element type"; } } $out .= " bless \$r, \$class;\n }\n"; # Create accessor methods. my ($pre, $pst, $sel); $cnt = 0; foreach my $name (@methods) { my $type = $types{$name}; if (do { no strict 'refs'; defined &{$class . "::$name"} }) { warnings::warnif("function '$name' already defined, overrides struct accessor method"); } else { $pre = $pst = $cmt = $sel = ''; if (defined $refs{$name}) { $pre = "\\("; $pst = ")"; $cmt = " # returns ref"; } $out .= " sub $name {$cmt\n my \$r = shift;\n"; if ($base_type eq 'ARRAY') { $elem = "[$cnt]"; ++$cnt; } if (defined $arrays{$name}) { $out .= " my \$i;\n"; $out .= " \@_ ? (\$i = shift) : return \$r->$elem;\n"; $out .= " if (ref(\$i) eq 'ARRAY' && !\@_) { \$r->$elem = \$i; return \$r }\n"; $sel = "->[\$i]"; } elsif (defined $hashes{$name}) { $out .= " my \$i;\n"; $out .= " \@_ ? (\$i = shift) : return \$r->$elem;\n"; $out .= " if (ref(\$i) eq 'HASH' && !\@_) { \$r->$elem = \$i; return \$r }\n"; $sel = "->{\$i}"; } $out .= " croak 'Too many args to $name' if \@_ > 1;\n"; $out .= " \@_ ? ($pre\$r->$elem$sel = shift$pst) : $pre\$r->$elem$sel$pst;\n"; $out .= " }\n"; } } #print $out; $out .= "}\n1;\n"; my $result = eval $out; carp $@ if $@; # Create top class (my $overclass = $baseclass) =~ s/::Struct$//; { #print \"NEW \",join(' ',\@_),\"\\n\"; eval " package $overclass; sub ${func} { my \$class = shift; my \$self = new $baseclass(\@_); bless \$self, \$class; }"; } } ###################################################################### #### Package return 1; __END__ =pod =head1 NAME Verilog::Netlist::Subclass - Common routines for all classes =head1 SYNOPSIS package Verilog::Netlist::Something; use Verilog::Netlist::Subclass; use base qw(Verilog::Netlist::Subclass); ... $self->info("We're here\n"); $self->warn("Things look bad\n"); $self->error("Things are even worse\n"); $self->exit_if_error(); =head1 DESCRIPTION The Verilog::Netlist::Subclass is used as a base class for all Verilog::Netlist::* structures. It is mainly used so that $self->warn() and $self->error() will produce consistent results. =head1 MEMBER FUNCTIONS =over 4 =item $self->error(I) Print an error in a standard format. =item $self->errors() Return number of errors detected. =item $self->exit_if_error() Exits the program if any errors were detected. =item $self->filename() The filename number the entity was created in. =item $self->info(I) Print a informational in a standard format. =item $self->lineno() The line number the entity was created on. =item $self->logger() The class to report errors using, generally a Verilog::Netlist::Logger object. =item $self->userdata(I) =item $self->userdata(I, I) Sets (with two arguments) or retrieves the specified key from an opaque hash. This may be used to store application data on the specified node. =item $self->warn(I) Print a warning in a standard format. =item $self->warnings() Return number of warnings detected. =back =head1 DISTRIBUTION Verilog-Perl is part of the L free Verilog EDA software tool suite. The latest version is available from CPAN and from L. Copyright 2000-2024 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. =head1 AUTHORS Wilson Snyder =head1 SEE ALSO L, L =cut Verilog-Perl-3.482/Netlist/Pin.pm0000644000177100017500000002446514553624343016546 0ustar wsnyderwsnyder# Verilog - Verilog Perl Interface # See copyright, etc in below POD section. ###################################################################### package Verilog::Netlist::Pin; use Verilog::Netlist; use Verilog::Netlist::Port; use Verilog::Netlist::Net; use Verilog::Netlist::Cell; use Verilog::Netlist::Module; use Verilog::Netlist::Pin; use Verilog::Netlist::PinSelection; use Verilog::Netlist::Subclass; use vars qw($VERSION @ISA); use strict; @ISA = qw(Verilog::Netlist::Pin::Struct Verilog::Netlist::Subclass); $VERSION = '3.482'; structs('_new_base', 'Verilog::Netlist::Pin::Struct' =>[name => '$', #' # Pin connection filename => '$', #' # Filename this came from lineno => '$', #' # Linenumber this came from userdata => '%', # User information attributes => '%', #' # Misc attributes for systemperl or other processors # comment => '$', #' # Comment provided by user _pinselects => '$', #' # Arrayref to Verilog::Netlist::PinSelections portname => '$', #' # Port connection name portnumber => '$', #' # Position of name in call pinnamed => '$', #' # True if name assigned cell => '$', #' # Cell reference # below only after link() _nets => '$', #' # Arrayref to references to connected nets port => '$', #' # Port connection reference # SystemPerl: below only after autos() sp_autocreated => '$', #' # Created by auto() # below by accessor computation #module #submod ]); sub new { my $class = shift; my %params = (@_); if (defined $params{netname}) { # handle legacy constructor parameter "netname" $params{_pinselects} = [new Verilog::Netlist::PinSelection($params{netname})]; delete $params{netname}; } elsif (defined $params{pinselects}) { # remap pinselects to _pinselects foreach my $pinselect (@{$params{pinselects}}) { push @{$params{_pinselects}}, new Verilog::Netlist::PinSelection($pinselect->{netname}, $pinselect->{msb}, $pinselect->{lsb}); } delete $params{pinselects}; } return $class->_new_base(%params); } sub delete { my $self = shift; if ($self->nets && $self->port) { foreach my $net ($self->nets) { next unless $net->{net}; my $dir = $self->port->direction; if ($dir eq 'in') { $net->{net}->_used_in_dec(); } elsif ($dir eq 'out') { $net->{net}->_used_out_dec(); } elsif ($dir eq 'inout') { $net->{net}->_used_inout_dec(); } } } my $h = $self->cell->_pins; delete $h->{$self->name}; return undef; } ###################################################################### #### Methods # Legacy accessors sub netname { return undef if !defined($_[0]->_pinselects); return @{$_[0]->_pinselects}[0]->{_netname}; } sub net { my $nets = $_[0]->_nets; return undef if !defined($nets); return undef if !@{$nets}[0]; return @{$nets}[0]->{net}; } # Standard accessors sub nets { return [] if !defined($_[0]->_nets); return (@{$_[0]->_nets}); } sub nets_sorted { return [] if !defined($_[0]->_nets); return (sort {$a->name cmp $b->name} (@{$_[0]->_nets})); } sub pinselects { return [] if !defined($_[0]->_pinselects); return @{$_[0]->_pinselects}; } sub logger { return $_[0]->netlist->logger; } sub module { return $_[0]->cell->module; } sub submod { return $_[0]->cell->submod; } sub netlist { return $_[0]->cell->module->netlist; } sub _link { my $self = shift; # Note this routine is HOT my $change; if (!$self->_nets) { if ($self->_pinselects) { my @nets = (); foreach my $pinselect (@{$self->_pinselects}) { my $net = $self->module->find_net($pinselect->netname); next if (!defined($net)); my ($msb, $lsb); # if the parsed description includes a range, use that, # else use the complete range of the underlying net. if (defined($pinselect->msb)) { $msb = $pinselect->msb; $lsb = $pinselect->lsb; } else { $msb = $net->msb; $lsb = $net->lsb; } push(@nets, {net => $net, msb => $msb, lsb => $lsb}); } $self->_nets(\@nets); $change = 1; } } if (!$self->port) { if (my $submod = $self->submod) { my $portname = $self->portname; if ($portname && !$self->cell->byorder ) { $self->port($submod->find_port($portname)); $change = 1; } else { $self->port($submod->find_port_by_index($self->portnumber)); # changing name from pin# to actual port name $self->name($self->port->name) if $self->port; $change = 1; } } } if ($change && $self->_nets && $self->port) { my $dir = $self->port->direction; foreach my $net ($self->nets) { next unless $net->{net}; if ($dir eq 'in') { $net->{net}->_used_in_inc(); } elsif ($dir eq 'out') { $net->{net}->_used_out_inc(); } elsif ($dir eq 'inout') { $net->{net}->_used_inout_inc(); } } } } sub type_match { my $self = shift; # We could check for specific types being OK, but nearly everything, # reg/trireg/wire/wand etc/tri/ supply0|1 etc # is allowed to connect with everything else, and we're not a lint tool... # So, not: return $self->net->data_type eq $self->port->data_type; return 1; } sub lint { my $self = shift; if (!$self->port && $self->submod) { $self->error($self,"Port not found in ",$self->submod->keyword," ",$self->submod->name,": ",$self->portname,"\n"); } if ($self->port && $self->nets) { if (!$self->type_match) { my $nettype = $self->net->data_type; my $porttype = $self->port->data_type; $self->error("Port pin data type '$porttype' != Net data type '$nettype': " ,$self->name,"\n"); } foreach my $net ($self->nets) { next unless $net->{net} && $net->{net}->port; my $portdir = $self->port->direction; my $netdir = $net->{net}->port->direction; if (($netdir eq "in" && $portdir eq "out") #Legal: ($netdir eq "in" && $portdir eq "inout") #Legal: ($netdir eq "out" && $portdir eq "inout") ) { $self->error("Port is ${portdir}put from submodule, but ${netdir}put from this module: " ,$self->name,"\n"); #$self->cell->module->netlist->dump; } } } } sub verilog_text { my $self = shift; my $inst; if ($self->port) { # Even if it was by position, after linking we can write it as if it's by name. $inst = ".".$self->port->name."("; } elsif ($self->pinnamed) { $inst = ".".$self->name."("; } else { # not by name, and unlinked $inst = ".".$self->portname."("; } my $net_cnt = $self->pinselects; if ($net_cnt >= 2) { $inst .= "{"; my $comma = ""; foreach my $pinselect (reverse($self->pinselects)) { $inst .= $comma; $inst .= $pinselect->bracketed_msb_lsb; $comma = ","; } $inst .= "}"; } elsif ($net_cnt == 1) { my @tmp = $self->pinselects; $inst .= $tmp[0]->bracketed_msb_lsb; } $inst .= ")"; return $inst; } sub dump { my $self = shift; my $indent = shift||0; my $net_cnt = $self->pinselects; my $out = " "x$indent."Pin:".$self->name; $out .= ($net_cnt > 1) ? " Nets:" : " Net:"; my $comma = ""; foreach my $pinselect (reverse($self->pinselects)) { $out .= $comma; $out .= $pinselect->bracketed_msb_lsb; $comma = ","; } print "$out\n"; if ($self->port) { $self->port->dump($indent+10, 'norecurse'); } foreach my $net ($self->nets) { next unless $net->{net}; $net->{net}->dump($indent+10, 'norecurse'); } } ###################################################################### #### Package return 1; __END__ =pod =head1 NAME Verilog::Netlist::Pin - Pin on a Verilog Cell =head1 SYNOPSIS use Verilog::Netlist; ... my $pin = $cell->find_pin('pinname'); print $pin->name; =head1 DESCRIPTION A Verilog::Netlist::Pin object is created by Verilog::Netlist::Cell for for each pin connection on a cell. A Pin connects a net in the current design to a port on the instantiated cell's module. =head1 ACCESSORS See also Verilog::Netlist::Subclass for additional accessors and methods. =over 4 =item $self->cell Reference to the Verilog::Netlist::Cell the pin is under. =item $self->comment Returns any comments following the definition. keep_comments=>1 must be passed to Verilog::Netlist::new for comments to be retained. =item $self->delete Delete the pin from the cell it's under. =item $self->module Reference to the Verilog::Netlist::Module the pin is in. =item $self->name The name of the pin. May have extra characters to make vectors connect, generally portname is a more readable version. There may be multiple pins with the same portname, only one pin has a given name. =item $self->net Reference to the Verilog::Netlist::Net the pin connects to. Only valid after a link. This function is deprecated; use nets or nets_sorted instead. =item $self->nets Array of hashes the pin connects to. Each hash contains a msb, lsb, and net (a Verilog::Netlist::Net). Only valid after a link. =item $self->nets_sorted Array of sorted hashes the pin connects to. Each hash contains a msb, lsb, and net (a Verilog::Netlist::Net). Only valid after a link. =item $self->netlist Reference to the Verilog::Netlist the pin is in. =item $self->netname The net name the pin connects to. This function is deprecated; use pinselects instead. =item $self->pinselects The net names the pins connect to, as an array of Verilog::Netlist::PinSelection elements. =item $self->portname The name of the port connected to. =item $self->port Reference to the Verilog::Netlist::Port the pin connects to. Only valid after a link. =back =head1 MEMBER FUNCTIONS See also Verilog::Netlist::Subclass for additional accessors and methods. =over 4 =item $self->lint Checks the pin for errors. Normally called by Verilog::Netlist::lint. =item $self->dump Prints debugging information for this pin. =back =head1 DISTRIBUTION Verilog-Perl is part of the L free Verilog EDA software tool suite. The latest version is available from CPAN and from L. Copyright 2000-2024 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. =head1 AUTHORS Wilson Snyder =head1 SEE ALSO L, L, L, L =cut Verilog-Perl-3.482/Getopt.pm0000644000177100017500000005406114553624343015633 0ustar wsnyderwsnyder# See copyright, etc in below POD section. ###################################################################### package Verilog::Getopt; require 5.000; require Exporter; use strict; use vars qw($VERSION $Debug %Skip_Basenames); use Carp; use IO::File; use File::Basename; use File::Spec; use Cwd; ###################################################################### #### Configuration Section $VERSION = '3.482'; # Basenames we should ignore when recursing directories, # Because they contain large files of no relevance foreach ( '.', '..', 'CVS', '.svn', '.snapshot', 'blib', ) { $Skip_Basenames{$_} = 1; } ####################################################################### ####################################################################### ####################################################################### sub new { @_ >= 1 or croak 'usage: Verilog::Getopt->new ({options})'; my $class = shift; # Class (Getopt Element) $class ||= "Verilog::Getopt"; my $self = {defines => {}, incdir => ['.', ], includes => {}, module_dir => ['.', ], libext => ['.v', ], library => [ ], gcc_style => 1, vcs_style => 1, filename_expansion => 0, fileline => 'Command_Line', unparsed => [], define_warnings => 1, depend_files => {}, @_ }; bless $self, $class; return $self; } ####################################################################### # Option parsing sub _filedir { my $self = shift; my $path = shift; $path =~ s![/\\][^/\\]*$!! # ~~== my @dirs = File::Spec->splitdir( $path ); or $path = "."; return "." if $path eq ''; return $path } sub parameter_file { my $self = shift; my $filename = shift; my $relative = shift; print "*parameter_file $filename\n" if $Debug; my $optdir = "."; if ($relative) { $optdir = $self->_filedir($filename); } my $fh = IO::File->new("<$filename") or die "%Error: ".$self->fileline().": $! $filename\n"; my $hold_fileline = $self->fileline(); while (my $line = $fh->getline()) { chomp $line; $line =~ s/(?:^|\s)\/\/.*$//; next if $line =~ /^\s*$/; $self->fileline("$filename:$."); my @p = (split /\s+/,"$line "); $self->_parameter_parse($optdir, @p); } $fh->close(); $self->fileline($hold_fileline); } sub parameter { my $self = shift; # Parse VCS like parameters, and perform standard setup based on it # Return list of leftover parameters @{$self->{unparsed}} = (); $self->_parameter_parse('.', @_); return @{$self->{unparsed}}; } sub _parameter_parse { my $self = shift; my $optdir = shift; # Internal: Parse list of VCS like parameters, and perform standard setup based on it foreach my $oparam (@_) { my $param = "$oparam"; # Must quote to convert Getopt to string, bug298 next if ($param =~ /^\s*$/); print " parameter($param)\n" if $Debug; ### GCC & VCS style if ($param eq '-F' || $param eq '-f') { $self->{_parameter_next} = $param; } ### VCS style elsif (($param eq '-v' || $param eq '-y') && $self->{vcs_style}) { $self->{_parameter_next} = $param; } elsif ($param =~ /^\+libext\+(.*)$/ && $self->{vcs_style}) { my $ext = $1; foreach (split /\+/, $ext) { $self->libext($_); } } elsif ($param =~ /^\+incdir\+(.*)$/ && $self->{vcs_style}) { $self->incdir($self->_parse_file_arg($optdir, $1)); } elsif ($param =~ /^\+define\+(.*)$/ && $self->{vcs_style}) { foreach my $tok (split("\\+", $1)) { my ($a, $b) = $tok =~ m/^([^=]*)=?(.*)$/; $self->define($a,$b,undef,1); } } # Ignored elsif ($param =~ /^\+librescan$/ && $self->{vcs_style}) { } ### GCC style elsif (($param =~ /^-D([^=]*)=(.*)$/ || $param =~ /^-D([^=]*)()$/) && $self->{gcc_style}) { $self->define($1,$2,undef,1); } elsif (($param =~ /^-U([^=]*)$/) && $self->{gcc_style}) { $self->undef($1); } elsif ($param =~ /^-I(.*)$/ && $self->{gcc_style}) { $self->incdir($self->_parse_file_arg($optdir, $1)); } # Second parameters elsif ($self->{_parameter_next}) { my $pn = $self->{_parameter_next}; $self->{_parameter_next} = undef; if ($pn eq '-F') { $self->parameter_file($self->_parse_file_arg($optdir,$param), 1); } elsif ($pn eq '-f') { $self->parameter_file($self->_parse_file_arg($optdir,$param), 0); } elsif ($pn eq '-v') { $self->library($self->_parse_file_arg($optdir,$param)); } elsif ($pn eq '-y') { $self->module_dir($self->_parse_file_arg($optdir,$param)); } else { die "%Error: ".$self->fileline().": Bad internal next param ".$pn; } } else { # Unknown. if ($self->{filename_expansion} && $param !~ /^-.*$/ # Presume not a file && $optdir ne '.') { # If it is a filename, we should ensure it is # relative to $optdir. We assume anything without a leading '-' # is a file, bug 444. my $fn = $self->_parse_file_arg($optdir,$param); if (-e $fn) { push @{$self->{unparsed}}, "$fn"; } else { push @{$self->{unparsed}}, "$param"; } } else { push @{$self->{unparsed}}, "$param"; } } } } sub _parse_file_arg { my $self = shift; my $optdir = shift; my $relfilename = shift; # Parse filename on option line, expanding relative paths in -F's my $filename = $self->file_substitute($relfilename); if ($optdir ne "." && ! File::Spec->file_name_is_absolute($filename)) { $filename = File::Spec->catfile($optdir,$filename); } return $filename; } ####################################################################### # Accessors sub fileline { my $self = shift; if (@_) { $self->{fileline} = shift; } return ($self->{fileline}); } sub incdir { my $self = shift; if (@_) { my $token = shift; print "incdir $token\n" if $Debug; if (ref($token) && ref($token) eq 'ARRAY') { @{$self->{incdir}} = @{$token}; } else { push @{$self->{incdir}}, $self->file_abs($token); } $self->file_path_cache_flush(); } return (wantarray ? @{$self->{incdir}} : $self->{incdir}); } sub libext { my $self = shift; if (@_) { my $token = shift; print "libext $token\n" if $Debug; if (ref($token) && ref($token) eq 'ARRAY') { @{$self->{libext}} = @{$token}; } else { push @{$self->{libext}}, $token; } $self->file_path_cache_flush(); } return (wantarray ? @{$self->{libext}} : $self->{libext}); } sub library { my $self = shift; if (@_) { my $token = shift; print "library $token\n" if $Debug; if (ref($token) && ref($token) eq 'ARRAY') { @{$self->{library}} = @{$token}; } else { push @{$self->{library}}, $self->file_abs($token); } } return (wantarray ? @{$self->{library}} : $self->{library}); } sub module_dir { my $self = shift; if (@_) { my $token = shift; print "module_dir $token\n" if $Debug; if (ref($token) && ref($token) eq 'ARRAY') { @{$self->{module_dir}} = @{$token}; } else { push @{$self->{module_dir}}, $self->file_abs($token); } $self->file_path_cache_flush(); } return (wantarray ? @{$self->{module_dir}} : $self->{module_dir}); } sub depend_files { my $self = shift; if (@_) { #@_ may be Getopt::Long::Parameters which aren't arrays, will stringify if (ref($_[0]) && ref($_[0]) eq 'ARRAY') { $self->{depend_files} = {}; foreach my $fn (@{$_[0]}) { $self->{depend_files}{$fn} = 1; } } else { foreach my $fn (@_) { print "depend_files $fn\n" if $Debug; $self->{depend_files}{$fn} = 1; } } } my @list = (sort (keys %{$self->{depend_files}})); return (wantarray ? @list : \@list); } sub get_parameters { my $self = shift; my %args = (gcc_stlyle => $self->{gcc_style},); # Defines my @params = (); foreach my $def ($self->define_names_sorted) { my $defvalue = $self->defvalue($def); $defvalue = "=".($defvalue||"") if (defined $defvalue && $defvalue ne ""); if ($args{gcc_style}) { push @params, "-D${def}${defvalue}"; } else { push @params, "+define+${def}${defvalue}"; } } # Put all libexts on one line, else NC-Verilog will bitch my $exts=""; foreach my $ext ($self->libext()) { $exts = "+libext" if !$exts; $exts .= "+$ext"; } push @params, $exts if $exts; # Includes... foreach my $dir ($self->incdir()) { if ($args{gcc_style}) { push @params, "-I${dir}"; } else { push @params, "+incdir+${dir}"; } } foreach my $dir ($self->module_dir()) { push @params, "-y", $dir; } foreach my $dir ($self->library()) { push @params, "-v", $dir; } return (@params); } sub write_parameters_file { my $self = shift; my $filename = shift; # Write get_parameters to a file my $fh = IO::File->new(">$filename") or croak "%Error: $! writing $filename,"; my @opts = $self->get_parameters(); print $fh join("\n",@opts); $fh->close; } sub includes { my $self = shift; if (@_) { my $from_filename = shift; my $inc_filename = shift; $self->{includes}{$from_filename}{$inc_filename} = 1; } return $self->{includes}; } ####################################################################### # Utility functions sub remove_duplicates { my $self = ref $_[0] && shift; # return list in same order, with any duplicates removed my @rtn; my %hit; foreach (@_) { push @rtn, $_ unless $hit{$_}++; } return @rtn; } sub file_skip_special { my $self = shift; my $filename = shift; $filename =~ s!.*[/\\]!!; return $Skip_Basenames{$filename}; } sub file_abs { my $self = shift; my $filename = shift; # return absolute filename # If the user doesn't want this absolutification, they can just # make their own derived class and override this function. # # We don't absolutify files that don't have any path, # as file_path() will probably be used to resolve them. return $filename; return $filename if ("" eq dirname($filename)); return $filename if File::Spec->file_name_is_absolute($filename); # Cwd::abspath() requires files to exist. Too annoying... $filename = File::Spec->canonpath(File::Spec->catdir(Cwd::getcwd(),$filename)); return $filename; } sub file_substitute { my $self = shift; my $filename = shift; my $out = $filename; while ($filename =~ /\$([A-Za-z_0-9]+)\b/g) { my $var = $1; $out =~ s/\$$var\b/$ENV{$var}/g if defined $ENV{$var}; } while ($filename =~ /\$\{([A-Za-z_0-9]+)\}/g) { my $var = $1; $out =~ s/\$\{$var\}/$ENV{$var}/g if defined $ENV{$var}; } $out =~ s!^~!$ENV{HOME}/!; return $out; } sub file_path_cache_flush { my $self = shift; # Clear out a file_path cache, needed if the incdir/module_dirs change $self->{_file_path_cache} = {}; } sub file_path { my $self = shift; my $filename = shift; my $lookup_type = shift || 'all'; # return path to given filename using library directories & files, or undef # locations are cached, because -r can be a very slow operation defined $filename or carp "%Error: Undefined filename,"; return $self->{_file_path_cache}{$filename} if defined $self->{_file_path_cache}{$filename}; if (-r $filename && !-d $filename) { $self->{_file_path_cache}{$filename} = $filename; $self->depend_files($filename); return $filename; } # Try expanding environment $filename = $self->file_substitute($filename); if (-r $filename && !-d $filename) { $self->{_file_path_cache}{$filename} = $filename; $self->depend_files($filename); return $filename; } # What paths to use? my @dirlist; if ($lookup_type eq 'module') { @dirlist = $self->module_dir(); } elsif ($lookup_type eq 'include') { @dirlist = $self->incdir(); } else { # all # Might be more obvious if -y had priority, but we'll remain back compatible @dirlist = ($self->incdir(), $self->module_dir()); } # Expand any envvars in incdir/moduledir @dirlist = map {$self->file_substitute($_)} @dirlist; # Check each search path # We use both the incdir and moduledir. This isn't strictly correct, # but it's fairly silly to have to specify both all of the time. my %checked_dir = (); my %checked_file = (); foreach my $dir (@dirlist) { next if $checked_dir{$dir}; $checked_dir{$dir}=1; # -r can be quite slow # Check each postfix added to the file foreach my $postfix ("", @{$self->{libext}}) { my $found = "$dir/$filename$postfix"; next if $checked_file{$found}; $checked_file{$found}=1; # -r can be quite slow if (-r $found && !-d $found) { $self->{_file_path_cache}{$filename} = $found; $self->depend_files($found); return $found; } } } return $filename; # Let whoever needs it discover it doesn't exist } sub libext_matches { my $self = shift; my $filename = shift; return undef if !$filename; foreach my $postfix (@{$self->{libext}}) { my $re = quotemeta($postfix) . "\$"; return $filename if ($filename =~ /$re/); } return undef; } sub map_directories { my $self = shift; my $func = shift; # Execute map function on all directories listed in self. { my @newdir = $self->incdir(); @newdir = map {&{$func}} @newdir; $self->incdir(\@newdir); } { my @newdir = $self->module_dir(); @newdir = map {&{$func}} @newdir; $self->module_dir(\@newdir); } } ####################################################################### # Getopt functions sub define_names_sorted { my $self = shift; return (sort (keys %{$self->{defines}})); } sub defcmdline { my $self = shift; my $token = shift; my $val = $self->{defines}{$token}; if (ref $val) { return $val->[2]; } else { return undef; } } sub defparams { my $self = shift; my $token = shift; my $val = $self->{defines}{$token}; if (!defined $val) { return undef; } elsif (ref $val && defined $val->[1]) { return $val->[1]; # Has parameters hash, return param list or undef } else { return 0; } } sub defvalue { my $self = shift; my $token = shift; my $val = $self->{defines}{$token}; (defined $val) or carp "%Warning: ".$self->fileline().": No definition for $token,"; if (ref $val) { return $val->[0]; # Has parameters, return just value } else { return $val; } } sub defvalue_nowarn { my $self = shift; my $token = shift; my $val = $self->{defines}{$token}; if (ref $val) { return $val->[0]; # Has parameters, return just value } else { return $val; } } sub define { my $self = shift; if (@_) { my $token = shift; my $value = shift; my $params = shift; my $cmdline = shift; print "Define $token ".($params||'')."= $value\n" if $Debug; my $oldval = $self->{defines}{$token}; my $oldparams; if (ref $oldval eq 'ARRAY') { ($oldval, $oldparams) = @{$oldval}; } if (defined $oldval && (($oldval ne $value) || (($oldparams||'') ne ($params||''))) && $self->{define_warnings}) { warn "%Warning: ".$self->fileline().": Redefining `$token" # Don't make errors too long or have strange chars .((length($oldval)<40 && $oldval =~ /^[^\n\r\f]$/ && length($value)<40 && $value =~ /^[^\n\r\f]$/) ? "to '$value', was '$oldval'\n" : "\n"); } if ($params || $cmdline) { $self->{defines}{$token} = [$value, $params, $cmdline]; } else { $self->{defines}{$token} = $value; } } } sub undef { my $self = shift; my $token = shift; my $oldval = $self->{defines}{$token}; # We no longer warn about undefing something that doesn't exist, as other compilers don't #(defined $oldval or !$self->{define_warnings}) # or carp "%Warning: ".$self->fileline().": No definition to undef for $token,"; delete $self->{defines}{$token}; } sub undefineall { my $self = shift; foreach my $def (keys %{$self->{defines}}) { if (!$self->defcmdline($def)) { delete $self->{defines}{$def}; } } } sub remove_defines { my $self = shift; my $sym = shift; my $val = "x"; while (defined $val) { last if $sym eq $val; (my $xsym = $sym) =~ s/^\`//; $val = $self->defvalue_nowarn($xsym); #Undef if not found $sym = $val if defined $val; } return $sym; } ###################################################################### ### Package return 1; __END__ =pod =head1 NAME Verilog::Getopt - Get Verilog command line options =head1 SYNOPSIS use Verilog::Getopt; my $opt = new Verilog::Getopt; $opt->parameter (qw( +incdir+standard_include_directory )); @ARGV = $opt->parameter(@ARGV); ... print "Path to foo.v is ", $opt->file_path('foo.v'); =head1 DESCRIPTION Verilog::Getopt provides standardized handling of options similar to Verilog/VCS and cc/GCC. =head1 OPTIONS The new() constructor accepts the following options: =over 4 =item filename_expansion=>1 Enable converting filenames to relative filenames when possible. This option is needed when the -F option will be used. If flags are passed through Getopt which should otherwise not be expanded (e.g. "--out myfile.v") having this option set may undesirably expand myfile.v to an absolute filename. =item gcc_style=>0 Disable parsing of GCC-like parameters. =item vcs_style=>0 Disable parsing of VCS-like parameters. =back =head1 METHODS =over 4 =item $opt = Verilog::Getopt->new ( I ) Create a new Getopt. See OPTIONS above. =item $self->file_path(I, [I]) Returns a new path to the filename, using the library directories and search paths to resolve the file. Optional lookup_type is 'module', 'include', or 'all', to use only module_dirs, incdirs, or both for the lookup. =item $self->get_parameters() Returns a list of parameters that when passed through $self->parameter() should result in the same state. Often this is used to form command lines for downstream programs that also use Verilog::Getopt. =item $self->parameter(\@params) Parses any recognized parameters in the referenced array, removing the standard parameters from any previous parameters() call, and returning a array with all unparsed parameters. The below list shows the VCS-like parameters that are supported, and the functions that are called: +libext+I+I... libext (I) +incdir+I incdir (I) +define+I=I define (I,I) +define+I define (I,undef) +librescan Ignored -F I Parse parameters in file relatively -f I Parse parameters in file -v I library (I) -y I module_dir (I) all others Put in returned list The below list shows the GCC-like parameters that are supported, and the functions that are called: -DI=I define (I,I) -DI define (I,undef) -UI undefine (I) -II incdir (I) -F I Parse parameters in file relatively -f I Parse parameters in file all others Put in returned list =item $self->write_parameters_file(I) Write the output from get_parameters to the specified file. =back =head1 ACCESSORS =over 4 =item $self->define($token, $value) This method is called when a define is recognized. The default behavior loads a hash that is used to fulfill define references. This function may also be called outside parsing to predefine values. An optional third argument specifies parameters to the define, and a fourth argument if true indicates the define was set on the command line and should not be removed by `undefineall. =item $self->define_names_sorted Return sorted list of all define names that currently exist. =item $self->defparams($token) This method returns the parameter list of the define. This will be defined, but false, if the define does not have arguments. =item $self->defvalue($token) This method returns the value of a given define, or prints a warning. =item $self->defvalue_nowarn($token) This method returns the value of a given define, or undef. =item $self->depend_files() Returns reference to list of filenames referenced with file_path, useful for creating dependency lists. With argument, adds that file. With list reference argument, sets the list to the argument. =item $self->file_abs($filename) Using the incdir and libext lists, convert the specified module or filename ("foo") to a absolute filename ("include/dir/foo.v"). =item $self->file_skip_special($filename) Return true if the filename is one that generally should be ignored when recursing directories, such as for example, ".", "CVS", and ".svn". =item $self->file_substitute($filename) Removes existing environment variables from the provided filename. Any undefined variables are not substituted nor cause errors. =item $self->incdir Returns reference to list of include directories. With argument, adds that directory. =item $self->includes Returns reference to hash of files that included some file, and for each hash value a list of files included. Only relevant after Verilog::Netlist processing. With two arguments, adds an include for the given referencing filename to the given include filename. =item $self->libext Returns reference to list of library extensions. With argument, adds that extension. =item $self->libext_matches(I) Returns true if the passed filename matches the libext. =item $self->library Returns reference to list of libraries. With argument, adds that library. =item $self->module_dir Returns reference to list of module directories. With argument, adds that directory. =item $self->remove_defines($token) Return string with any definitions in the token removed. =item $self->undef($token) Deletes a hash element that is used to fulfill define references. This function may also be called outside parsing to erase a predefined value. =item $self->undefineall Deletes all non-command line definitions, for implementing `undefineall. =back =head1 DISTRIBUTION Verilog-Perl is part of the L free Verilog EDA software tool suite. The latest version is available from CPAN and from L. Copyright 2000-2024 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. =head1 AUTHORS Wilson Snyder =head1 SEE ALSO L, L =cut Verilog-Perl-3.482/Language.pm0000644000177100017500000005235714553624343016122 0ustar wsnyderwsnyder# See copyright, etc in below POD section. ###################################################################### =pod =head1 NAME Verilog::Language - Verilog language utilities =head1 SYNOPSIS use Verilog::Language; $result = Verilog::Language::is_keyword("wire"); # true $result = Verilog::Language::is_compdirect("`notundef"); # false $result = Verilog::Language::number_value("4'b111"); # 8 $result = Verilog::Language::number_bits("32'h1b"); # 32 $result = Verilog::Language::number_signed("1'sh1"); # 1 @vec = Verilog::Language::split_bus("[31,5:4]"); # 31, 5, 4 @vec = Verilog::Language::split_bus_nocomma("[31:29]"); # 31, 30, 29 $result = Verilog::Language::strip_comments("a/*b*/c"); # ac =head1 DESCRIPTION Verilog::Language provides general utilities for using the Verilog Language, such as parsing numbers or determining what keywords exist. General functions will be added as needed. =head1 FUNCTIONS =over 4 =item Verilog::Language::is_keyword($symbol_string) Return true if the given symbol string is a Verilog reserved keyword. Value indicates the language standard as per the `begin_keywords macro, '1364-1995', '1364-2001', '1364-2005', '1800-2005', '1800-2009', '1800-2012', '1800-2017', '1800-2023', or 'VAMS'. =item Verilog::Language::is_compdirect($symbol_string) Return true if the given symbol string is a Verilog compiler directive. =item Verilog::Language::is_gateprim($symbol_string) Return true if the given symbol is a built in gate primitive; for example "buf", "xor", etc. =item Verilog::Language::language_keywords($year) Returns a hash for keywords for given language standard year, where the value of the hash is the standard in which it was defined. =item Verilog::Language::language_standard($year) Sets the language standard to indicate what are keywords. If undef, all standards apply. The year is indicates the language standard as per the `begin_keywords macro, '1364-1995', '1364-2001', '1364-2005', '1800-2005' '1800-2009', '1800-2012', '1800-2017', or '1800-2023'. =item Verilog::Language::language_maximum Returns the greatest language currently standardized, presently '1800-2023'. =item Verilog::Language::number_bigint($number_string) Return the numeric value of a Verilog value stored as a Math::BigInt, or undef if incorrectly formed. You must 'use Math::BigInt' yourself before calling this function. Note bigints do not have an exact size, so NOT of a Math::BigInt may return a different value than verilog. See also number_value and number_bitvector. =item Verilog::Language::number_bits($number_string) Return the number of bits in a value string, or undef if incorrectly formed, _or_ not specified. =item Verilog::Language::number_bitvector($number_string) Return the numeric value of a Verilog value stored as a Bit::Vector, or undef if incorrectly formed. You must 'use Bit::Vector' yourself before calling this function. The size of the Vector will be that returned by number_bits. =item Verilog::Language::number_signed($number_string) Return true if the Verilog value is signed, else undef. =item Verilog::Language::number_value($number_string) Return the numeric value of a Verilog value, or undef if incorrectly formed. It ignores any signed Verilog attributes, but is is returned as a perl signed integer, so it may fail for over 31 bit values. See also number_bigint and number_bitvector. =item Verilog::Language::split_bus($bus) Return a list of expanded arrays. When passed a string like "foo[5:1:2,10:9]", it will return a array with ("foo[5]", "foo[3]", ...). It correctly handles connectivity expansion also, so that "x[1:0] = y[3:0]" will get intuitive results. =item Verilog::Language::split_bus_nocomma($bus) As with split_bus, but faster. Only supports simple decimal colon separated array specifications, such as "foo[3:0]". =item Verilog::Language::strip_comments($text) Return text with any // or /**/ comments stripped, correctly handing quoted strings. Newlines will be preserved in this process. =back =head1 DISTRIBUTION Verilog-Perl is part of the L free Verilog EDA software tool suite. The latest version is available from CPAN and from L. Copyright 2000-2024 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. =head1 AUTHORS Wilson Snyder =head1 SEE ALSO L, L L, L, L And the LVerilog-Mode package for Emacs. =cut ###################################################################### package Verilog::Language; require 5.000; require Exporter; use strict; use vars qw($VERSION %Keyword %Keywords %Compdirect $Standard %Gateprim); use Carp; ###################################################################### #### Configuration Section $VERSION = '3.482'; ###################################################################### #### Internal Variables foreach my $kwd (qw( always and assign begin buf bufif0 bufif1 case casex casez cmos deassign default defparam disable else end endcase endfunction endmodule endprimitive endspecify endtable endtask event for force forever fork function highz0 highz1 if initial inout input integer join large macromodule medium module nand negedge nmos nor not notif0 notif1 or output parameter pmos posedge primitive pull0 pull1 pulldown pullup rcmos real realtime reg release repeat rnmos rpmos rtran rtranif0 rtranif1 scalared small specify strength strong0 strong1 supply0 supply1 table task time tran tranif0 tranif1 tri tri0 tri1 triand trior trireg vectored wait wand weak0 weak1 while wire wor xnor xor )) { $Keywords{'1364-1995'}{$kwd} = '1364-1995'; } foreach my $kwd (qw( automatic cell config design edge endconfig endgenerate generate genvar ifnone incdir include instance liblist library localparam noshowcancelled pulsestyle_ondetect pulsestyle_onevent showcancelled signed specparam unsigned use )) { $Keywords{'1364-2001'}{$kwd} = '1364-2001'; } foreach my $kwd (qw( uwire )) { $Keywords{'1364-2005'}{$kwd} = '1364-2005'; } foreach my $kwd (qw( alias always_comb always_ff always_latch assert assume before bind bins binsof bit break byte chandle class clocking const constraint context continue cover covergroup coverpoint cross dist do endclass endclocking endgroup endinterface endpackage endprogram endproperty endsequence enum expect export extends extern final first_match foreach forkjoin iff ignore_bins illegal_bins import inside int interface intersect join_any join_none local logic longint matches modport new null package packed priority program property protected pure rand randc randcase randsequence ref return sequence shortint shortreal solve static string struct super tagged this throughout timeprecision timeunit type typedef union unique var virtual void wait_order wildcard with within )) { $Keywords{'1800-2005'}{$kwd} = '1800-2005'; } foreach my $kwd (qw( accept_on checker endchecker eventually global implies let nexttime reject_on restrict s_always s_eventually s_nexttime s_until s_until_with strong sync_accept_on sync_reject_on unique0 until until_with untyped weak )) { $Keywords{'1800-2009'}{$kwd} = '1800-2009'; } foreach my $kwd (qw( implements nettype interconnect soft )) { $Keywords{'1800-2012'}{$kwd} = '1800-2012'; } foreach my $kwd (qw( )) { $Keywords{'1800-2017'}{$kwd} = '1800-2017'; } foreach my $kwd (qw( )) { $Keywords{'1800-2023'}{$kwd} = '1800-2023'; } foreach my $kwd (qw( above abs absdelay abstol ac_stim access acos acosh aliasparam analog analysis asin asinh assert atan atan2 atanh branch ceil connect connectmodule connectrules continuous cos cosh cross ddt ddt_nature ddx discipline discrete domain driver_update endconnectrules enddiscipline endnature endparamset exclude exp final_step flicker_noise floor flow from ground hypot idt idt_nature idtmod inf initial_step laplace_nd laplace_np laplace_zd laplace_zp last_crossing limexp ln log max merged min nature net_resolution noise_table paramset potential pow resolveto sin sinh slew split sqrt string tan tanh timer transition units white_noise wreal zi_nd zi_np zi_zd zi_zp )) { $Keywords{'VAMS'}{$kwd} = 'VAMS'; } foreach my $kwd ( # Speced "`celldefine", "`define", # Preprocessor "`else", # Preprocessor "`endcelldefine", "`endif", # Preprocessor "`ifdef", # Preprocessor "`include", # Preprocessor "`nounconnected_drive", "`resetall", "`timescale", "`unconnected_drive", "`undef", # Preprocessor "`undefineall", # Preprocessor # Commercial Extensions "`accelerate", # Verilog-XL compatibility "`autoexpand_vectornets", # Verilog-XL compatibility "`default_decay_time", # Verilog spec - delays only "`default_trireg_strength", # Verilog spec "`delay_mode_distributed", # Verilog spec - delays only "`delay_mode_path", # Verilog spec - delays only "`delay_mode_unit", # Verilog spec - delays only "`delay_mode_zero", # Verilog spec - delays only "`disable_portfaults", # Verilog-XL compatibility "`enable_portfaults", # Verilog-XL compatibility "`endprotect", # Many tools - pre encryption "`endprotected", # Many tools - post encryption "`expand_vectornets", # Verilog-XL compatibility "`noaccelerate", # Verilog-XL compatibility "`noexpand_vectornets", # Verilog-XL compatibility "`noremove_gatenames", # Verilog-XL compatibility "`noremove_netnames", # Verilog-XL compatibility "`nosuppress_faults", # Verilog-XL compatibility "`nounconnected_drive", # Verilog-XL compatibility "`portcoerce", # Verilog-XL compatibility "`protect", # Many tools - pre encryption "`protected", # Many tools - post encryption "`remove_gatenames", # Verilog-XL compatibility "`remove_netnames", # Verilog-XL compatibility "`suppress_faults", # Verilog-XL compatibility ) { $Keywords{$kwd}{'1364-1995'} = $Compdirect{$kwd} = '1364-1995'; } foreach my $kwd ( "`default_nettype", "`elsif", "`undef", "`ifndef", "`file", "`line", ) { $Keywords{$kwd}{'1364-2001'} = $Compdirect{$kwd} = '1364-2001'; } foreach my $kwd ( "`pragma", ) { $Keywords{$kwd}{'1364-2005'} = $Compdirect{$kwd} = '1364-2005'; } foreach my $kwd ( "`default_discipline", "`default_transition", ) { $Keywords{$kwd}{'1364-2005'} = $Compdirect{$kwd} = '1364-2005'; } language_standard(language_maximum()); # Default standard foreach my $kwd (qw( and buf bufif0 bufif1 cmos nand nmos nor not notif0 notif1 or pmos pulldown pullup rcmos rnmos rpmos rtran rtranif0 rtranif1 tran tranif0 tranif1 xnor xor )) { $Gateprim{$kwd} = '1364-1995'; } ###################################################################### #### Keyword utilities sub language_maximum { return "1800-2023"; } sub _language_kwd_hash { my $standard = shift; my @subsets; if ($standard eq '1995' || $standard eq '1364-1995') { $Standard = '1364-1995'; @subsets = ('1364-1995'); } elsif ($standard eq '2001' || $standard eq '1364-2001' || $standard eq '1364-2001-noconfig') { $Standard = '1364-2001'; @subsets = ('1364-2001', '1364-1995'); } elsif ($standard eq '1364-2005') { $Standard = '1364-2005'; @subsets = ('1364-2005', '1364-2001', '1364-1995'); } elsif ($standard eq 'sv31' || $standard eq '1800-2005') { $Standard = '1800-2005'; @subsets = ('1800-2005', '1364-2005', '1364-2001', '1364-1995'); } elsif ($standard eq '1800-2009') { $Standard = '1800-2009'; @subsets = ('1800-2009', '1800-2005', '1364-2005', '1364-2001', '1364-1995'); } elsif ($standard eq '1800-2012') { $Standard = '1800-2012'; @subsets = ('1800-2012', '1800-2009', '1800-2005', '1364-2005', '1364-2001', '1364-1995'); } elsif ($standard eq '1800-2017') { $Standard = '1800-2017'; @subsets = ('1800-2017', '1800-2012', '1800-2009', '1800-2005', '1364-2005', '1364-2001', '1364-1995'); } elsif ($standard eq 'latest' || $standard eq '1800-2023') { $Standard = '1800-2023'; @subsets = ('1800-2023', '1800-2017', '1800-2012', '1800-2009', '1800-2005', '1364-2005', '1364-2001', '1364-1995'); } elsif ($standard =~ /^V?AMS/) { $Standard = 'VAMS'; @subsets = ('VAMS', '1364-2005', '1364-2001', '1364-1995'); } else { croak "%Error: Verilog::Language::language_standard passed bad value: $standard,"; } # Update keyword list to present language # (We presume the language_standard rarely changes, so it's faster to compute the list.) my %keywords = (); foreach my $ss (@subsets) { foreach my $kwd (%{$Keywords{$ss}}) { $keywords{$kwd} = $ss; } } return %keywords; } sub language_standard { my $standard = shift; if (defined $standard) { %Keyword = _language_kwd_hash($standard); } return $Standard; } sub language_keywords { my $standard = shift || $Standard; return _language_kwd_hash($standard); } sub is_keyword { my $symbol = shift; return ($Keyword{$symbol}); } sub is_compdirect { my $symbol = shift; return ($Compdirect{$symbol}); } sub is_gateprim { my $symbol = shift; return ($Gateprim{$symbol}); } ###################################################################### #### String utilities sub strip_comments { return $_[0] if $_[0] !~ m!/!s; # Fast path my $text = shift; # Spec says that // has no special meaning inside /**/ my $quote; my $olcmt; my $cmt; my $out = ""; while ($text =~ m!(.*?)(//|/\*|\*/|\n|\"|$)!sg) { $out .= $1 if !$olcmt && !$cmt; my $t = $2; if ($2 eq '"') { $out .= $t; $quote = ! $quote; } elsif (!$quote && !$olcmt && $t eq '/*') { $cmt = 1; } elsif (!$quote && !$cmt && $t eq '//') { $olcmt = 1; } elsif ($cmt && $t eq '*/') { $cmt = 0; } elsif ($t eq "\n") { $olcmt = 0; $out .= $t; } else { $out .= $t if !$olcmt && !$cmt; } } return $out; } ###################################################################### #### Numeric utilities sub number_bits { my $number = shift; if ($number =~ /^\s*([0-9]+)\s*\'/i) { return $1; } return undef; } sub number_signed { my $number = shift; if ($number =~ /\'\s*s/i) { return 1; } return undef; } sub number_value { my $number = shift; $number =~ s/[_ ]//g; if ($number =~ /\'s?h([0-9a-f]+)$/i) { return (hex ($1)); } elsif ($number =~ /\'s?o([0-9a-f]+)$/i) { return (oct ($1)); } elsif ($number =~ /\'s?b([0-1]+)$/i) { my $val = 0; $number = $1; foreach my $bit (split(//, $number)) { $val = ($val<<1) | ($bit=='1'?1:0); } return ($val); } elsif ($number =~ /\'s?d?([0-9]+)$/i || $number =~ /^(-?[0-9]+)$/i) { return ($1); } return undef; } sub number_bigint { my $number = shift; $number =~ s/[_ ]//g; if ($number =~ /\'s?h([0-9a-f]+)$/i) { return (Math::BigInt->new("0x".$1)); } elsif ($number =~ /\'s?o([0-9a-f]+)$/i) { my $digits = $1; my $vec = Math::BigInt->new(); my $len = length($digits); my $bit = 0; for (my $index=$len-1; $index>=0; $index--, $bit+=3) { my $digit = substr($digits,$index,1); my $val = Math::BigInt->new($digit); $val = $val->blsft($bit,2); $vec->bior($val); } return ($vec); } elsif ($number =~ /\'s?b([0-1]+)$/i) { return (Math::BigInt->new("0b".$1)); } elsif ($number =~ /\'s?d?0*([0-9]+)$/i || $number =~ /^0*([0-9]+)$/i) { return (Math::BigInt->new($1)); } return undef; } sub number_bitvector { my $number = shift; $number =~ s/[_ ]//g; my $bits = number_bits($number) || 32; if ($number =~ /\'s?h([0-9a-f]+)$/i) { return (Bit::Vector->new_Hex($bits,$1)); } elsif ($number =~ /\'s?o([0-9a-f]+)$/i) { my $digits = $1; my $vec = Bit::Vector->new($bits); my $len = length($digits); my $bit = 0; for (my $index=$len-1; $index>=0; $index--, $bit+=3) { my $digit = substr($digits,$index,1); $vec->Bit_On($bit+2) if ($digit & 4); $vec->Bit_On($bit+1) if ($digit & 2); $vec->Bit_On($bit+0) if ($digit & 1); } return ($vec); } elsif ($number =~ /\'s?b([0-1]+)$/i) { return (Bit::Vector->new_Bin($bits,$1)); } elsif ($number =~ /\'s?d?([0-9]+)$/i || $number =~ /^([0-9]+)$/i) { return (Bit::Vector->new_Dec($bits,$1)); } return undef; } ###################################################################### #### Signal utilities sub split_bus { my $bus = shift; if ($bus !~ /\[/) { # Fast case: No bussing return $bus; } elsif ($bus =~ /^([^\[]+\[)([0-9]+):([0-9]+)(\][^\]]*)$/) { # Middle speed case: Simple max:min my $bit; my @vec = (); if ($2 >= $3) { for ($bit = $2; $bit >= $3; $bit --) { push @vec, $1 . $bit . $4; } } else { for ($bit = $2; $bit <= $3; $bit ++) { push @vec, $1 . $bit . $4; } } return @vec; } else { # Complex case: x:y:z,p,... etc # Do full parsing my @pretext = (); # [brnum] my @expanded = (); # [brnum][bitoccurance] my $inbra = 0; my $brnum = 0; my ($beg,$end,$step); foreach (split (/([:\]\[,])/, $bus)) { if (/^\[/) { $inbra = 1; $pretext[$brnum] .= $_; } if (!$inbra) { # Not in bracket, just remember text $pretext[$brnum] .= $_; next; } if (/[\],]/) { if (defined $beg) { # End of bus piece #print "Got seg $beg $end $step\n"; my $bit; if ($beg >= $end) { for ($bit = $beg; $bit >= $end; $bit -= $step) { push @{$expanded[$brnum]}, $bit; } } else { for ($bit = $beg; $bit <= $end; $bit += $step) { push @{$expanded[$brnum]}, $bit; } } } $beg = undef; # Now what? if (/^\]/) { $inbra = 0; $brnum++; $pretext[$brnum] .= $_; } elsif (/,/) { $inbra = 1; } } elsif (/:/) { $inbra++; } else { if ($inbra == 1) { # Begin value $beg = $end = number_value($_); # [2'b11:2'b00] is legal $step = 1; } elsif ($inbra == 2) { # End value $end = number_value($_); # [2'b11:2'b00] is legal } elsif ($inbra == 3) { # Middle value $step = number_value($_); # [2'b11:2'b00] is legal } # Else ignore extra colons } } # Determine max size of any bracket expansion array my $br; my $max_size = $#{$expanded[0]}; for ($br=1; $br<$brnum; $br++) { my $len = $#{$expanded[$br]}; if ($len < 0) { push @{$expanded[$br]}, ""; $len = 0; } $max_size = $len if $max_size < $len; } my $i; my @vec = (); for ($i=0; $i<=$max_size; $i++) { $bus = ""; for ($br=0; $br<$brnum; $br++) { #print "i $i br $br >", $pretext[$br],"<\n"; $bus .= $pretext[$br] . $expanded[$br][$i % (1+$#{$expanded[$br]})]; } $bus .= $pretext[$br]; # Trailing stuff push @vec, $bus; } return @vec; } } sub split_bus_nocomma { # Faster version of split_bus my $bus = shift; if ($bus !~ /:/) { # Fast case: No bussing return $bus; } elsif ($bus =~ /^([^\[]+\[)([0-9]+):([0-9]+)(\][^\]]*)$/) { # Middle speed case: Simple max:min my $bit; my @vec = (); if ($2 >= $3) { for ($bit = $2; $bit >= $3; $bit --) { push @vec, $1 . $bit . $4; } } else { for ($bit = $2; $bit <= $3; $bit ++) { push @vec, $1 . $bit . $4; } } return @vec; } else { # Complex case: x:y etc # Do full parsing my @pretext = (); # [brnum] my @expanded = (); # [brnum][bitoccurance] my $inbra = 0; my $brnum = 0; my ($beg,$end); foreach (split (/([:\]\[])/, $bus)) { if (/^\[/) { $inbra = 1; $pretext[$brnum] .= $_; } if (!$inbra) { # Not in bracket, just remember text $pretext[$brnum] .= $_; next; } if (/[\]]/) { if (defined $beg) { # End of bus piece #print "Got seg $beg $end\n"; my $bit; if ($beg >= $end) { for ($bit = $beg; $bit >= $end; $bit--) { push @{$expanded[$brnum]}, $bit; } } else { for ($bit = $beg; $bit <= $end; $bit++) { push @{$expanded[$brnum]}, $bit; } } } $beg = undef; # Now what? if (/^\]/) { $inbra = 0; $brnum++; $pretext[$brnum] .= $_; } } elsif (/:/) { $inbra++; } else { if ($inbra == 1) { # Begin value $beg = $end = $_; } elsif ($inbra == 2) { # End value $end = $_; } # Else ignore extra colons } } # Determine max size of any bracket expansion array my $br; my $max_size = $#{$expanded[0]}; for ($br=1; $br<$brnum; $br++) { my $len = $#{$expanded[$br]}; if ($len < 0) { push @{$expanded[$br]}, ""; $len = 0; } $max_size = $len if $max_size < $len; } my $i; my @vec = (); for ($i=0; $i<=$max_size; $i++) { $bus = ""; for ($br=0; $br<$brnum; $br++) { #print "i $i br $br >", $pretext[$br],"<\n"; $bus .= $pretext[$br] . $expanded[$br][$i % (1+$#{$expanded[$br]})]; } $bus .= $pretext[$br]; # Trailing stuff push @vec, $bus; } return @vec; } } ###################################################################### #### Package return 1; Verilog-Perl-3.482/Netlist.pm0000644000177100017500000004647314553624343016023 0ustar wsnyderwsnyder# Verilog - Verilog Perl Interface # See copyright, etc in below POD section. ###################################################################### package Verilog::Netlist; use Carp; use IO::File; use Verilog::Netlist::File; use Verilog::Netlist::Interface; use Verilog::Netlist::Module; use Verilog::Netlist::Subclass; use base qw(Verilog::Netlist::Subclass); use strict; use vars qw($Debug $Verbose $VERSION); $VERSION = '3.482'; ###################################################################### #### Error Handling # Netlist file & line numbers don't apply sub logger { return $_[0]->{logger}; } sub filename { return 'Verilog::Netlist'; } sub lineno { return ''; } ###################################################################### #### Creation sub new { my $class = shift; my $self = {_interfaces => {}, _modules => {}, _files => {}, implicit_wires_ok => 1, link_read => 1, logger => Verilog::Netlist::Logger->new, options => undef, # Usually pointer to Verilog::Getopt symbol_table => [], # Symbol table for Verilog::Parser preproc => 'Verilog::Preproc', parser => 'Verilog::Netlist::File::Parser', remove_defines_without_tick => 0, # Overriden in SystemC::Netlist #include_open_nonfatal => 0, #keep_comments => 0, #synthesis => 0, #use_pinselects => 0, use_vars => 1, _libraries_done => {}, _need_link => [], # Objects we need to ->link @_}; bless $self, $class; return $self; } sub delete { my $self = shift; # Break circular references to netlist foreach my $subref ($self->modules) { $subref->delete; } foreach my $subref ($self->interfaces) { $subref->delete; } foreach my $subref ($self->files) { $subref->delete; } $self->{_modules} = {}; $self->{_interfaces} = {}; $self->{_files} = {}; $self->{_need_link} = {}; } ###################################################################### #### Functions sub link { my $self = shift; while (defined(my $subref = pop @{$self->{_need_link}})) { $subref->link(); } # The above should have gotten everything, but a child class # may rely on old behavior or have added classes outside our # universe, so be nice and do it the old way too. $self->{_relink} = 1; while ($self->{_relink}) { $self->{_relink} = 0; foreach my $subref ($self->modules) { $subref->link(); } foreach my $subref ($self->interfaces) { $subref->link(); } foreach my $subref ($self->files) { $subref->_link(); } } } sub lint { my $self = shift; foreach my $subref ($self->modules_sorted) { next if $subref->is_libcell(); $subref->lint(); } foreach my $subref ($self->interfaces_sorted) { $subref->link(); } } sub verilog_text { my $self = shift; my @out; foreach my $subref ($self->interfaces_sorted) { push @out, $subref->verilog_text, "\n"; } foreach my $subref ($self->modules_sorted) { push @out, $subref->verilog_text, "\n"; } return (wantarray ? @out : join('',@out)); } sub dump { my $self = shift; foreach my $subref ($self->interfaces_sorted) { $subref->dump(); } foreach my $subref ($self->modules_sorted) { $subref->dump(); } } ###################################################################### #### Module access sub new_module { my $self = shift; # @_ params # Can't have 'new Verilog::Netlist::Module' do this, # as not allowed to override Class::Struct's new() my $modref = new Verilog::Netlist::Module (netlist=>$self, keyword=>'module', is_top=>1, @_); $self->{_modules}{$modref->name} = $modref; push @{$self->{_need_link}}, $modref; return $modref; } sub new_root_module { my $self = shift; $self->{_modules}{'$root'} ||= $self->new_module(keyword=>'root_module', name=>'$root', @_); return $self->{_modules}{'$root'}; } sub defvalue_nowarn { my $self = shift; my $sym = shift; # Look up the value of a define, letting the user pick the accessor class if (my $opt=$self->{options}) { return $opt->defvalue_nowarn($sym); } return undef; } sub remove_defines { my $self = shift; my $sym = shift; # This function is HOT my $xsym = $sym; # We only remove defines one level deep, for historical reasons. # We optionally don't require a ` as SystemC also uses this function and doesn't use `. if ($self->{remove_defines_without_tick} || $xsym =~ /^\`/) { $xsym =~ s/^\`//; my $val = $self->defvalue_nowarn($xsym); #Undef if not found return $val if defined $val; } return $sym; } sub find_module_or_interface_for_cell { # ($self,$name) Are arguments, hardcoded below # Hot function, used only by Verilog::Netlist::Cell linking # Doesn't need to remove defines, as that's already done by caller return $_[0]->{_modules}{$_[1]} || $_[0]->{_interfaces}{$_[1]}; } sub find_module { my $self = shift; my $search = shift; # Return module maching name my $mod = $self->{_modules}{$search}; return $mod if $mod; # Allow FOO_CELL to be a #define to choose what instantiation is really used my $rsearch = $self->remove_defines($search); if ($rsearch ne $search) { return $self->find_module($rsearch); } return undef; } sub modules { my $self = shift; # Return all modules return (values %{$self->{_modules}}); } sub modules_sorted { my $self = shift; # Return all modules return (sort {$a->name cmp $b->name} (values %{$self->{_modules}})); } sub modules_sorted_level { my $self = shift; # Return all modules return (sort {$a->level <=> $b->level || $a->name cmp $b->name} (values %{$self->{_modules}})); } sub top_modules_sorted { my $self = shift; return grep ($_->is_top && !$_->is_libcell, $self->modules_sorted); } ###################################################################### #### Interface access sub new_interface { my $self = shift; # @_ params # Can't have 'new Verilog::Netlist::Interface' do this, # as not allowed to override Class::Struct's new() my $modref = new Verilog::Netlist::Interface (netlist=>$self, @_); $self->{_interfaces}{$modref->name} = $modref; push @{$self->{_need_link}}, $modref; return $modref; } sub find_interface { my $self = shift; my $search = shift; # Return interface maching name my $mod = $self->{_interfaces}{$search}; return $mod if $mod; # Allow FOO_CELL to be a #define to choose what instantiation is really used my $rsearch = $self->remove_defines($search); if ($rsearch ne $search) { return $self->find_interface($rsearch); } return undef; } sub interfaces { my $self = shift; # Return all interfaces return (values %{$self->{_interfaces}}); } sub interfaces_sorted { my $self = shift; # Return all interfaces return (sort {$a->name cmp $b->name} (values %{$self->{_interfaces}})); } ###################################################################### #### Files access sub resolve_filename { my $self = shift; my $filename = shift; my $lookup_type = shift; if ($self->{options}) { $filename = $self->remove_defines($filename); $filename = $self->{options}->file_path($filename, $lookup_type); } if (!-r $filename || -d $filename) { return undef; } $self->dependency_in($filename); return $filename; } sub new_file { my $self = shift; # @_ params # Can't have 'new Verilog::Netlist::File' do this, # as not allowed to override Class::Struct's new() my $fileref = new Verilog::Netlist::File (netlist=>$self, @_); defined $fileref->name or carp "%Error: No name=> specified, stopped"; $self->{_files}{$fileref->name} = $fileref; $fileref->basename(Verilog::Netlist::Module::modulename_from_filename($fileref->name)); push @{$self->{_need_link}}, $fileref; return $fileref; } sub find_file { my $self = shift; my $search = shift; # Return file maching name return $self->{_files}{$search}; } sub files { my $self = shift; ref $self or die; # Return all files return (sort {$a->name() cmp $b->name()} (values %{$self->{_files}})); } sub files_sorted { return files(@_); } sub read_file { my $self = shift; my $fileref = $self->read_verilog_file(@_); return $fileref; } sub read_verilog_file { my $self = shift; my $fileref = Verilog::Netlist::File::read (netlist=>$self, @_); return $fileref; } sub read_libraries { my $self = shift; if ($self->{options}) { my @files = $self->{options}->library(); foreach my $file (@files) { if (!$self->{_libraries_done}{$file}) { $self->{_libraries_done}{$file} = 1; $self->read_file(filename=>$file, is_libcell=>1, ); ## $self->dump(); } } } } ###################################################################### #### Dependencies sub dependency_in { my $self = shift; my $filename = shift; $self->{_depend_in}{$filename} = 1; } sub dependency_out { my $self = shift; my $filename = shift; $self->{_depend_out}{$filename} = 1; } sub dependency_write { my $self = shift; my $filename = shift; my $fh = IO::File->new(">$filename") or die "%Error: $! writing $filename\n"; print $fh "$filename"; foreach my $dout (sort (keys %{$self->{_depend_out}})) { print $fh " $dout"; } print $fh " :"; foreach my $din (sort (keys %{$self->{_depend_in}})) { print $fh " $din"; } print $fh "\n"; $fh->close(); } ###################################################################### #### Package return 1; __END__ =pod =head1 NAME Verilog::Netlist - Verilog Netlist =head1 SYNOPSIS use Verilog::Netlist; # Setup options so files can be found use Verilog::Getopt; my $opt = new Verilog::Getopt; $opt->parameter( "+incdir+verilog", "-y","verilog", ); # Prepare netlist my $nl = new Verilog::Netlist(options => $opt,); foreach my $file ('testnetlist.v') { $nl->read_file(filename=>$file); } # Read in any sub-modules $nl->link(); #$nl->lint(); # Optional, see docs; probably not wanted $nl->exit_if_error(); foreach my $mod ($nl->top_modules_sorted) { show_hier($mod, " ", "", ""); } sub show_hier { my $mod = shift; my $indent = shift; my $hier = shift; my $cellname = shift; if (!$cellname) {$hier = $mod->name;} #top modules get the design name else {$hier .= ".$cellname";} #append the cellname printf("%-45s %s\n", $indent."Module ".$mod->name,$hier); foreach my $sig ($mod->ports_sorted) { printf($indent." %sput %s\n", $sig->direction, $sig->name); } foreach my $cell ($mod->cells_sorted) { printf($indent. " Cell %s\n", $cell->name); foreach my $pin ($cell->pins_sorted) { printf($indent." .%s(%s)\n", $pin->name, $pin->netname); } show_hier($cell->submod, $indent." ", $hier, $cell->name) if $cell->submod; } } =head1 DESCRIPTION Verilog::Netlist reads and holds interconnect information about a whole design database. See the "Which Package" section of L if you are unsure which parsing package to use for a new application. A Verilog::Netlist is composed of files, which contain the text read from each file. A file may contain modules, which are individual blocks that can be instantiated (designs, in Synopsys terminology.) Modules have ports, which are the interconnection between nets in that module and the outside world. Modules also have nets, (aka signals), which interconnect the logic inside that module. Modules can also instantiate other modules. The instantiation of a module is a Cell. Cells have pins that interconnect the referenced module's pin to a net in the module doing the instantiation. Each of these types, files, modules, ports, nets, cells and pins have a class. For example Verilog::Netlist::Cell has the list of Verilog::Netlist::Pin(s) that interconnect that cell. =head1 FUNCTIONS See also Verilog::Netlist::Subclass for additional accessors and methods. =over 4 =item $netlist->lint Error checks the entire netlist structure. Currently there are only two checks, that modules are bound to instantiations (which is also checked by $netlist->link), and that signals aren't multiply driven. Note that as there is no elaboration you may get false errors about multiple drivers from generate statements that are mutually exclusive. For this reason and the few lint checks you may not want to use this method. Alternatively to avoid pin interconnect checks, set the $netlist->new (...use_vars=>0...) option. =item $netlist->link() Resolves references between the different modules. If link_read=>1 is passed when netlist->new is called (it is by default), undefined modules will be searched for using the Verilog::Getopt package, passed by a reference in the creation of the netlist. To suppress errors in any missing references, set link_read_nonfatal=>1 also. =item $netlist->new Creates a new netlist structure. Pass optional parameters by name, with the following parameters: =over 8 =item implicit_wires_ok => $true_or_false Indicates whether to allow undeclared wires to be used. =item include_open_nonfatal => $true_or_false Indicates that include files that do not exist should be ignored. =item keep_comments => $true_or_false Indicates that comment fields should be preserved and on net declarations into the Vtest::Netlist::Net structures. Otherwise all comments are stripped for speed. =item link_read => $true_or_false Indicates whether or not the parser should automatically search for undefined modules through the "options" object. =item link_read_nonfatal => $true_or_false Indicates that modules that referenced but not found should be ignored, rather than causing an error message. =item logger => object Specify a message handler object to be used for error handling, this class should be a Verilog::Netlist::Logger object, or derived from one. If unspecified, a Verilog::Netlist::Logger local to this netlist will be used. =item options => $opt_object An optional pointer to a Verilog::Getopt object, to be used for locating files. =item parser => $package_name The name of the parser class. Defaults to "Verilog::Netlist::File::Parser". =item preproc => $package_name The name of the preprocessor class. Defaults to "Verilog::Preproc". =item synthesis => $true_or_false With synthesis set, define SYNTHESIS, and ignore text between "ambit", "pragma", "synopsys" or "synthesis" translate_off and translate_on meta comments. Note using metacomments is discouraged as they have led to silicon bugs (versus ifdef SYNTHESIS); see L. =item use_pinselects => $true_or_false Indicates that bit selects should be parsed and interpreted. False for backward compatibility, but true recommended in new applications. =item use_vars => $true_or_false Indicates that signals, variables, and pin interconnect information is needed; set by default. If clear do not read it, nor report lint related pin warnings, which can greatly improve performance. =back =item $netlist->dump Prints debugging information for the entire netlist structure. =back =head1 INTERFACE FUNCTIONS =over 4 =item $netlist->find_interface($name) Returns Verilog::Netlist::Interface matching given name. =item $netlist->interfaces Returns list of Verilog::Netlist::Interface. =item $netlist->interfaces_sorted Returns name sorted list of Verilog::Netlist::Interface. =item $netlist->new_interface Creates a new Verilog::Netlist::Interface. =back =head1 MODULE FUNCTIONS =over 4 =item $netlist->find_module($name) Returns Verilog::Netlist::Module matching given name. =item $netlist->modules Returns list of Verilog::Netlist::Module. =item $netlist->modules_sorted Returns name sorted list of Verilog::Netlist::Module. =item $netlist->modules_sorted_level Returns level sorted list of Verilog::Netlist::Module. Leaf modules will be first, the top most module will be last. =item $netlist->new_module Creates a new Verilog::Netlist::Module. =item $netlist->new_root_module Creates a new Verilog::Netlist::Module for $root, if one doesn't already exist. =item $netlist->top_modules_sorted Returns name sorted list of Verilog::Netlist::Module, only for those modules which have no children and are not unused library cells. =back =head1 FILE FUNCTIONS =over 4 =item $netlist->dependency_write(I) Writes a dependency file for make, listing all input and output files. =item $netlist->defvalue_nowarn(I) Return the value of the specified define or undef. =item $netlist->dependency_in(I) Adds an additional input dependency for dependency_write. =item $netlist->dependency_out(I) Adds an additional output dependency for dependency_write. =item $netlist->delete Delete the netlist, reclaim memory. Unfortunately netlists will not disappear simply with normal garbage collection from leaving of scope due to complications with reference counting and weaking Class::Struct structures; solutions welcome. =item $netlist->files Returns list of Verilog::Netlist::File. =item $netlist->files_sorted Returns a name sorted list of Verilog::Netlist::File. =item $netlist->find_file($name) Returns Verilog::Netlist::File matching given name. =item $netlist->read_file( filename=>$name) Reads the given Verilog file, and returns a Verilog::Netlist::File reference. Generally called as $netlist->read_file. Pass a hash of parameters. Reads the filename=> parameter, parsing all instantiations, ports, and signals, and creating Verilog::Netlist::Module structures. =item $netlist->read_libraries() Read any libraries specified in the options=> argument passed with the netlist constructor. Automatically invoked when netlist linking results in a module that wasn't found, and thus might be inside the libraries. =item $netlist->remove_defines(I) Expand any `defines in the string and return the results. Undefined defines will remain in the returned string. =item $netlist->resolve_filename(I, [I]) Convert a module name to a filename. Optional lookup_type is 'module', 'include', or 'all', to use only module_dirs, incdirs, or both for the lookup. Return undef if not found. =item $self->verilog_text Returns verilog code which represents the netlist. The netlist must be already ->link'ed for this to work correctly. =back =head1 BUGS Cell instantiations without any arguments are not supported, a empty set of parenthesis are required. (Use "cell cell();", not "cell cell;".) Order based pin interconnect is not supported, use name based connections. =head1 DISTRIBUTION Verilog-Perl is part of the L free Verilog EDA software tool suite. The latest version is available from CPAN and from L. Copyright 2000-2024 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. =head1 AUTHORS Wilson Snyder =head1 SEE ALSO L, L, L, L, L, L, L, L, L, L, L, L And the LVerilog-Mode package for Emacs. =cut Verilog-Perl-3.482/.gitignore0000644000177100017500000000017413234726611016013 0ustar wsnyderwsnyderREADME blib Makefile pm_to_blib *.c *.bs *.old *.tmp .vpassert .vpm .git .svn simv signals.vrename test_dir MYMETA.* nodist Verilog-Perl-3.482/Preproc/0000755000177100017500000000000014553624441015436 5ustar wsnyderwsnyderVerilog-Perl-3.482/Preproc/VPreLex.l0000644000177100017500000005674714553624300017155 0ustar wsnyderwsnyder%option noyywrap align interactive %option stack %option noc++ %option prefix="VPreLex" %{ /****************************************************************************** * DESCRIPTION: Verilog Preprocessor Lexer * * This file is part of Verilog-Perl. * * Author: Wilson Snyder * * Code available from: https://www.veripool.org/verilog-perl * ****************************************************************************** * * Copyright 2000-2024 by Wilson Snyder. This program is free software; * you can redistribute it and/or modify it under the terms of either the GNU * Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * ***************************************************************************** * Do not use Flex in C++ mode. It has bugs with yyunput() which result in * lost characters. *****************************************************************************/ #include "VPreProc.h" #include "VPreLex.h" #include #include #include #include // Flex 2.5.35 has compile warning in ECHO, so we'll default our own rule #define ECHO yyerrorf("Missing VPreLex.l rule: ECHO rule invoked in state %d: %s", YY_START, yytext); VPreLex* VPreLex::s_currentLexp = NULL; // Current lexing point #define LEXP VPreLex::s_currentLexp #define linenoInc() { LEXP->linenoInc(); } static bool pedantic() { return LEXP->m_pedantic; } static bool keepWhitespace() { return LEXP->m_keepWhitespace; } static void appendDefValue(const char* t, size_t l) { LEXP->appendDefValue(t,l); } void yyerror(char* msg) { LEXP->curFilelinep()->error(msg); } #define YY_INPUT(buf,result,max_size) \ result = LEXP->inputToLex(buf,max_size); // Accessors, because flex keeps changing the type of yyleng char* yyourtext() { return yytext; } size_t yyourleng() { return (size_t)yyleng; } void yyourtext(const char* textp, size_t size) { yytext=(char*)textp; yyleng=size; } void yyerrorf(const char* format, ...) { char msg[1024]; va_list ap; va_start(ap,format); vsprintf(msg,format,ap); va_end(ap); yyerror(msg); } static bool isWhitespace(const std::string& str) { for (std::string::const_iterator pos = str.begin(); pos != str.end(); ++pos) { if (!isspace(*pos)) return false; } return true; } /**********************************************************************/ %} %x CMTMODE %x STRMODE %x DEFFPAR %x DEFFORM %x DEFVAL %x DEFCMT %x STRIFY %x ARGMODE %x INCMODE %x PRTMODE %x OFFMODE /* drop: Drop Ctrl-Z - can't pass thru or may EOF the output too soon */ ws [ \t\f\r] wsn [ \t\f] crnl [\r]*[\n] quote [\"] tickquote [`][\"] /* Where we use symb/symbdef, we must also look for a `` join */ /* Note in the preprocessor \ESCaped is *not* always special; mantis1537/bug441 */ backslash [\\] symb ([a-zA-Z_][a-zA-Z0-9_$]*|\\[^ \t\f\r\n]+) symbdef ([a-zA-Z_][a-zA-Z0-9_$]*|\\[^ \t\f\r\n`]+) word [a-zA-Z0-9_]+ drop [\032] bom [\357\273\277] /* Case insensitive; unfortunately ?i: isn't in flex 2.5.4 which is popular */ ambit [Aa][Mm][Bb][Ii][Tt] pragma [Pp][Rr][Aa][Gg][Mm][Aa] synopsys [Ss][Yy][Nn][Oo][Pp][Ss][Yy][Ss] synthesis [Ss][Yy][Nn][Tt][Hh][Ee][Ss][Ii][Ss] pragma_tools ({ambit}|{pragma}|{synopsys}|{synthesis}) translate_off [Tt][Rr][Aa][Nn][Ss][Ll][Aa][Tt][Ee]_[Oo][Ff][Ff] translate_on [Tt][Rr][Aa][Nn][Ss][Ll][Aa][Tt][Ee]_[Oo][Nn] prag_trans_off ({ws}*{pragma_tools}{ws}+{translate_off}{ws}*) prag_trans_on ({ws}*{pragma_tools}{ws}+{translate_on}{ws}*) /**************************************************************/ %% {bom} { } ^{ws}*"`line"{ws}+.*{crnl} { LEXP->lineDirective(yytext); return(VP_LINE); } /* Special directives we recognize */ "`define" { return(VP_DEFINE); } "`else" { return(VP_ELSE); } "`elsif" { return(VP_ELSIF); } "`endif" { return(VP_ENDIF); } "`ifdef" { return(VP_IFDEF); } "`ifndef" { return(VP_IFNDEF); } "`include" { return(VP_INCLUDE); } "`undef" { return(VP_UNDEF); } "`undefineall" { return(VP_UNDEFINEALL); } "`error" { if (!pedantic()) return (VP_ERROR); else return(VP_DEFREF); } "`__FILE__" { static string rtnfile; rtnfile = '"'; rtnfile += LEXP->curFilelinep()->filename(); rtnfile += '"'; yytext=(char*)rtnfile.c_str(); yyleng = rtnfile.length(); return (VP_STRING); } "`__LINE__" { static char buf[10]; sprintf(buf, "%d",LEXP->curFilelinep()->lineno()); yytext = buf; yyleng = strlen(yytext); return (VP_TEXT); } /* Pass-through strings */ {quote} { yy_push_state(STRMODE); yymore(); } <> { linenoInc(); yyerrorf("EOF in unterminated string"); yyleng=0; yyterminate(); } {crnl} { linenoInc(); yyerrorf("Unterminated string"); BEGIN(INITIAL); } {word} { yymore(); } [^\"\\] { yymore(); } {backslash}{crnl} { linenoInc(); yymore(); } {backslash}. { yymore(); } {quote} { yy_pop_state(); if (LEXP->m_parenLevel || LEXP->m_defQuote) { LEXP->m_defQuote=false; appendDefValue(yytext,yyleng); yyleng=0; } else return (VP_STRING); } /* Stringification */ {tickquote} { yy_push_state(STRIFY); return VP_STRIFY; } <> { linenoInc(); yyerrorf("EOF in unterminated '\""); yyleng=0; yyterminate(); } "`\\`\"" { return VP_BACKQUOTE; } {quote} { yy_push_state(STRMODE); yymore(); } {tickquote} { yy_pop_state(); return VP_STRIFY; } {symbdef} { return (VP_SYMBOL); } {symbdef}`` { yyleng-=2; return (VP_SYMBOL_JOIN); } "`"{symbdef} { return (VP_DEFREF); } "`"{symbdef}`` { yyleng-=2; return (VP_DEFREF_JOIN); } `` { yyleng-=2; return (VP_JOIN); } {crnl} { linenoInc(); yytext=(char*)"\n"; yyleng=1; return(VP_WHITE); } {wsn}+ { return (VP_WHITE); } {drop} { } [\r] { } . { return (VP_TEXT); } /* Protected blocks */ "`protected" { yy_push_state(PRTMODE); yymore(); } "`pragma"{wsn}+"protect"{wsn}+"begin_protected" { yy_push_state(PRTMODE); yymore(); } "//"{ws}*"pragma"{ws}+"protect"{ws}+"begin_protected" { yy_push_state(PRTMODE); yymore(); } <> { linenoInc(); yyerrorf("EOF in `protected"); yyleng=0; yyterminate(); } {crnl} { linenoInc(); return VP_TEXT; } . { yymore(); } "`endprotected" { yy_pop_state(); return VP_TEXT; } "`pragma"{wsn}+"protect"{wsn}+"end_protected" { yy_pop_state(); return VP_TEXT; } "//"{ws}*"pragma"{ws}+"protect"{ws}+"end_protected" { yy_pop_state(); return VP_TEXT; } /* Pass-through include <> filenames */ <> { linenoInc(); yyerrorf("EOF in unterminated include filename"); yyleng=0; yyterminate(); } {crnl} { linenoInc(); yyerrorf("Unterminated include filename"); BEGIN(INITIAL); } [^\>\\] { yymore(); } {backslash}. { yymore(); } [\>] { yy_pop_state(); return VP_STRING; } /* Reading definition formal parenthesis (or not) to begin formal arguments */ /* Note '(' must IMMEDIATELY follow definition name */ [(] { appendDefValue("(",1); LEXP->m_formalLevel=1; BEGIN(DEFFORM); } {crnl} { yy_pop_state(); unput('\n'); yyleng=0; return VP_DEFFORM; } /* DEFVAL will later grab the return */ <> { yy_pop_state(); return VP_DEFFORM; } /* empty formals */ . { yy_pop_state(); unput(yytext[yyleng-1]); yyleng=0; return VP_DEFFORM; } /* empty formals */ /* Reading definition formals (declaration of a define) */ [(] { appendDefValue(yytext,yyleng); yyleng=0; ++LEXP->m_formalLevel; } [)] { appendDefValue(yytext,yyleng); yyleng=0; if ((--LEXP->m_formalLevel)==0) { yy_pop_state(); return VP_DEFFORM; } } "/*" { yy_push_state(CMTMODE); yymore(); } "//"[^\n\r]* { return (VP_COMMENT);} {drop} { } <> { linenoInc(); yy_pop_state(); yyerrorf("Unterminated ( in define formal arguments."); yyleng=0; return VP_DEFFORM; } {crnl} { linenoInc(); appendDefValue((char*)"\n",1); } /* Include return so can maintain output line count */ [\\]{crnl} { linenoInc(); appendDefValue((char*)"\\\n",2); } /* Include return so can maintain output line count */ {quote} { LEXP->m_defQuote=true; yy_push_state(STRMODE); yymore(); } /* Legal only in default values */ "`\\`\"" { appendDefValue(yytext,yyleng); } /* Maybe illegal, otherwise in default value */ {tickquote} { appendDefValue(yytext,yyleng); } /* Maybe illegal, otherwise in default value */ [{\[] { LEXP->m_formalLevel++; appendDefValue(yytext,yyleng); } [}\]] { LEXP->m_formalLevel--; appendDefValue(yytext,yyleng); } [^\/\*\n\r\\(){}\[\]\"]+ | [\\][^\n\r] | . { appendDefValue(yytext,yyleng); } /* Reading definition value (declaration of a define's text) */ "/*" { LEXP->m_defCmtSlash=false; yy_push_state(DEFCMT); yymore(); } /* Special comment parser */ "//"[^\n\r]*[\\]{crnl} { linenoInc(); appendDefValue((char*)"\n",1); } /* Spec says // not part of define value */ "//"[^\n\r]* { return (VP_COMMENT);} {drop} { } <> { linenoInc(); yy_pop_state(); yytext=(char*)"\n"; yyleng=1; return (VP_DEFVALUE); } /* Technically illegal, but people complained */ {crnl} { linenoInc(); yy_pop_state(); yytext=(char*)"\n"; yyleng=1; return (VP_DEFVALUE); } [\\]{crnl} { linenoInc(); appendDefValue((char*)"\\\n",2); } /* Return, AND \ is part of define value */ {quote} { LEXP->m_defQuote=true; yy_push_state(STRMODE); yymore(); } [^\/\*\n\r\\\"]+ | [\\][^\n\r] | . { appendDefValue(yytext,yyleng); } /* Comments inside define values - if embedded get added to define value per spec */ /* - if no \{crnl} ending then the comment belongs to the next line, as a non-embedded comment */ /* - if all but (say) 3rd line is missing \ then it's indeterminate */ "*/" { yy_pop_state(); appendDefValue(yytext,yyleng); } [\\]{crnl} { linenoInc(); LEXP->m_defCmtSlash=true; appendDefValue(yytext,yyleng-2); appendDefValue((char*)"\n",1); } /* Return but not \ */ {crnl} { linenoInc(); yymore(); if (LEXP->m_defCmtSlash) yyerrorf("One line of /* ... */ is missing \\ before newline"); BEGIN(CMTMODE); } {word} { yymore(); } . { yymore(); } <> { yyerrorf("EOF in '/* ... */' block comment\n"); yyleng=0; yyterminate(); } /* Define arguments (use of a define) */ "/*" { yy_push_state(CMTMODE); yymore(); } "//"[^\n\r]* { return (VP_COMMENT);} {drop} { } <> { yyerrorf("EOF in define argument list\n"); yyleng = 0; yyterminate(); } {crnl} { linenoInc(); yytext=(char*)"\n"; yyleng=1; return(VP_WHITE); } {quote} { yy_push_state(STRMODE); yymore(); } "`\\`\"" { appendDefValue(yytext,yyleng); } /* Literal text */ {tickquote} { yy_push_state(STRIFY); return(VP_STRIFY); } [{\[] { LEXP->m_parenLevel++; appendDefValue(yytext,yyleng); } [}\]] { LEXP->m_parenLevel--; appendDefValue(yytext,yyleng); } [(] { LEXP->m_parenLevel++; // Note paren level 0 means before "(" of starting args // Level 1 means "," between arguments // Level 2+ means one argument's internal () if (LEXP->m_parenLevel == 1) { // Starting ( if (!isWhitespace(LEXP->m_defValue)) { yyerrorf("Illegal text before '(' that starts define arguments: '%s'", LEXP->m_defValue.c_str()); } } if (LEXP->m_parenLevel>1) { appendDefValue(yytext,yyleng); } else { return (VP_TEXT); }} [)] { LEXP->m_parenLevel--; if (LEXP->m_parenLevel>0) { appendDefValue(yytext,yyleng); } else { yy_pop_state(); return (VP_DEFARG); }} [,] { if (LEXP->m_parenLevel>1) { appendDefValue(yytext,yyleng); } else { yy_pop_state(); return (VP_DEFARG); }} "`"{symbdef} { appendDefValue(yytext,yyleng); } /* defref in defref - outer macro expands first */ "`"{symbdef}`` { appendDefValue(yytext,yyleng); } /* defref in defref - outer macro expands first */ `` { appendDefValue(yytext,yyleng); } /* defref in defref - outer macro expands first */ [^\/\*\n\r\\(,){}\[\]\"`]+ | . { appendDefValue(yytext,yyleng); } /* Translate offs. Note final newline not included */ (("//"{prag_trans_off}[^\n\r]*)|("/*"{prag_trans_off}"*/")) { if (LEXP->m_synthesis) { yy_push_state(OFFMODE); } return(VP_COMMENT); } (("//"{prag_trans_on}[^\n\r]*)|("/*"{prag_trans_on}"*/")) { if (LEXP->m_synthesis) { yy_pop_state(); } return(VP_COMMENT); } {crnl} { linenoInc(); yymore(); } /* Need to end the / / */ {word} { } . { } <> { yyerrorf("EOF in '/*synthesis translate_off*/' region\n"); yyleng=0; yyterminate(); } /* One line comments. Note final newline not included */ "//"[^\n\r]* { return (VP_COMMENT); } /* C-style comments. */ /**** See also DEFCMT */ "/*" { yy_push_state(CMTMODE); yymore(); } "*/" { yy_pop_state(); return(VP_COMMENT); } {crnl} { linenoInc(); yymore(); } {word} { yymore(); } . { yymore(); } <> { yyerrorf("EOF in '/* ... */' block comment\n"); yyleng=0; yyterminate(); } /* Define calls */ /* symbdef prevents normal lex rules from making `\`"foo a symbol {`"foo} instead of a BACKQUOTE */ "`"{symbdef} { return (VP_DEFREF); } "`"{symbdef}`` { yyleng-=2; return (VP_DEFREF_JOIN); } `` { yyleng-=2; return (VP_JOIN); } /* Generics */ <> { yyterminate(); } /* A "normal" EOF */ {crnl} { linenoInc(); yytext=(char*)"\n"; yyleng=1; return(VP_WHITE); } {symb} { return (VP_SYMBOL); } {symb}`` { yyleng-=2; return (VP_SYMBOL_JOIN); } `` { yyleng-=2; return (VP_JOIN); } [\r] { } {wsn}+ { if (!keepWhitespace()) { yytext=(char*)" "; yyleng=1; } return VP_WHITE; } {drop} { } . { return (VP_TEXT); } <*>.|\n { yymore(); } /* Prevent hitting ECHO; */ %% void VPreLex::pushStateDefArg(int level) { // Enter define substitution argument state yy_push_state(ARGMODE); m_parenLevel = level; m_defValue = ""; } void VPreLex::pushStateDefForm() { // Enter define formal arguments state yy_push_state(DEFFPAR); // First is an optional ( to begin args m_parenLevel = 0; m_defValue = ""; } void VPreLex::pushStateDefValue() { // Enter define value state yy_push_state(DEFVAL); m_parenLevel = 0; m_defValue = ""; } void VPreLex::pushStateIncFilename() { // Enter include <> filename state yy_push_state(INCMODE); yymore(); } void VPreLex::debug(int level) { #ifdef FLEX_DEBUG yy_flex_debug=level; #endif } int VPreLex::debug() { #ifdef FLEX_DEBUG return yy_flex_debug; #else return 0; #endif } int VPreLex::lex() { VPreLex::s_currentLexp = this; // Tell parser where to get/put data m_tokFilelinep = curFilelinep(); // Remember token start location, may be updated by the lexer later return yylex(); } size_t VPreLex::inputToLex(char* buf, size_t max_size) { // We need a custom YY_INPUT because we can't use flex buffers. // Flex buffers are limited to 2GB, and we can't chop into 2G pieces // because buffers can't end in the middle of tokens. // Note if we switched streams here (which we don't) "buf" would be // become a stale invalid pointer. // VPreStream* streamp = curStreamp(); if (debug()>=10) { cout<<"- pp:inputToLex ITL s="< max_size) { yyerrorf("Output buffer too small for a `line"); } else { got = forceOut.length(); strncpy(buf, forceOut.c_str(), got); } } else { if (streamp->m_eof) { if (debug()) cout<<"- EOF\n"; } got = 0; // 0=EOF/EOS - although got was already 0. if (again) goto again; } } if (debug()>=10) { cout<<"- pp::inputToLex got="<m_eof) return ""; // Don't delete the final "EOF" stream bool exited_file = curStreamp()->m_file; if (!exited_file) { // Midpoint of stream, just change buffers delete curStreamp(); m_streampStack.pop(); // Must work as size>1; EOF is entry 0 againr = true; return ""; } // Multiple steps because we need FLEX to see ending \n and EOS to end // any illegal states, like an unterminated `protected region else if (!curStreamp()->m_termState) { // First shutdown phase for a file // Terminate all files with a newline. This prevents problems if // the user had a define without a terminating newline, // otherwise the resumed file's next line would get tacked on. // Also makes it likely the `line that changes files comes out // immediately. curStreamp()->m_termState = 1; return "\n"; // Exit old file } else if (curStreamp()->m_termState == 1) { // Now the EOF - can't be sent with other characters curStreamp()->m_termState = 2; return ""; // End of file } else if (curStreamp()->m_termState == 2) { // Now ending `line curStreamp()->m_termState = 3; return curFilelinep()->lineDirectiveStrg(2); // Exit old file } else { // Final shutdown phase for a stream, we can finally change the // current fileline to the new stream curStreamp()->m_termState = 0; VFileLine* filelinep = curFilelinep(); delete curStreamp(); m_streampStack.pop(); // Must work as size>1; EOF is entry 0 if (curStreamp()->m_eof) { // EOF doesn't have a "real" fileline, but a linenumber of 0 from init time // Inherit whatever we last parsed so it's more obvious. curFilelinep(filelinep); } // The caller parser remembered the start location for the text we are parsing, // but we've discovered there was a file switch along the way, so update it. m_tokFilelinep = curFilelinep(); // if (curStreamp()->m_eof) { return ""; } else { return curFilelinep()->lineDirectiveStrg(0); // Reenter resumed file } } } void VPreLex::initFirstBuffer(VFileLine* filelinep) { // Called from constructor to make first buffer // yy_create_buffer also sets yy_fill_buffer=1 so reads from YY_INPUT VPreStream* streamp = new VPreStream(filelinep, this); streamp->m_eof = true; m_streampStack.push(streamp); // m_bufferState = yy_create_buffer(NULL, YY_BUF_SIZE); yy_switch_to_buffer(m_bufferState); yyrestart(NULL); } void VPreLex::scanNewFile(VFileLine* filelinep) { // Called on new open file. scanBytesBack will be called next. if (streamDepth() > VPreProc::DEFINE_RECURSION_LEVEL_MAX) { // The recursive `include in VPreProcImp should trigger first yyerrorf("Recursive `define or other nested inclusion"); curStreamp()->m_eof = true; // Fake it to stop recursion } else { VPreStream* streamp = new VPreStream(filelinep, this); m_tokFilelinep = curFilelinep(); streamp->m_file = true; scanSwitchStream(streamp); } } void VPreLex::scanBytes(const string& str) { // Note buffers also appended in ::scanBytesBack // Not "m_buffers.push_front(string(strp,len))" as we need a `define // to take effect immediately, in the middle of the current buffer // Also we don't use scan_bytes that would set yy_fill_buffer // which would force Flex to bypass our YY_INPUT routine. if (streamDepth() > VPreProc::DEFINE_RECURSION_LEVEL_MAX) { // More streams if recursive `define with complex insertion // More buffers mostly if something internal goes funky yyerrorf("Recursive `define or other nested inclusion"); curStreamp()->m_eof = true; // Fake it to stop recursion } else { VPreStream* streamp = new VPreStream(curFilelinep(), this); streamp->m_buffers.push_front(str); scanSwitchStream(streamp); } } void VPreLex::scanSwitchStream(VPreStream* streamp) { curStreamp()->m_buffers.push_front(currentUnreadChars()); m_streampStack.push(streamp); yyrestart(NULL); } void VPreLex::scanBytesBack(const string& str) { // Initial creation, that will pull from YY_INPUT==inputToLex // Note buffers also appended in ::scanBytes if (curStreamp()->m_eof) yyerrorf("scanBytesBack without being under scanNewFile"); curStreamp()->m_buffers.push_back(str); } string VPreLex::currentUnreadChars() { // WARNING - Peeking at internals if (!currentBuffer()) return ""; ssize_t left = (yy_n_chars - (yy_c_buf_p - currentBuffer()->yy_ch_buf)); if (left > 0) { // left may be -1 at EOS *(yy_c_buf_p) = (yy_hold_char); return string(yy_c_buf_p, left); } else { return ""; } } YY_BUFFER_STATE VPreLex::currentBuffer() { return YY_CURRENT_BUFFER; } int VPreLex::currentStartState() { return YY_START; } void VPreLex::dumpSummary() { cout<<"- pp::dumpSummary curBuf="<<(void*)(currentBuffer()); #ifdef FLEX_DEBUG // Else peeking at internals may cause portability issues ssize_t left = (yy_n_chars - (yy_c_buf_p -currentBuffer()->yy_ch_buf)); cout<<" left="< tmpstack = LEXP->m_streampStack; while (!tmpstack.empty()) { VPreStream* streamp = tmpstack.top(); cout<<"- bufferStack["<<(void*)(streamp)<<"]: " <<" at="<m_curFilelinep <<" nBuf="<m_buffers.size() <<" size0="<<(streamp->m_buffers.empty() ? 0 : streamp->m_buffers.front().length()) <<(streamp->m_eof?" [EOF]":"") <<(streamp->m_file?" [FILE]":""); cout< #include #include using namespace std; #include "VFileLine.h" /// Generic opaque pointer to VPreProcImp implementation class. struct VPreProcOpaque { virtual ~VPreProcOpaque() {} }; class VDefine; //********************************************************************** // VPreProc /// Verilog Preprocessor. //// /// This defines a preprocessor. Functions are virtual so users can override them. /// After creating, call openFile(), then getline() in a loop. The class will to the rest... class VPreProc { public: VPreProc(); void configure(VFileLine* filelinep); virtual ~VPreProc(); // STATE private: int m_keepComments; int m_keepWhitespace; bool m_lineDirectives; bool m_pedantic; bool m_synthesis; public: // CONSTANTS enum MiscConsts { DEFINE_RECURSION_LEVEL_MAX = 1000, // How many `def substitutions before an error INCLUDE_DEPTH_MAX = 500, // How many `includes deep before an error STREAM_DEPTH_LEVEL_MAX = 2000, // How many streams deep (sometimes `def deep) before an error // // Set more than DEFINE_RECURSION_LEVEL_MAX or INCLUDE_DEPTH_MAX NEWLINES_VS_TICKLINE = 20 // Use `line in place of this many newlines }; // ACCESSORS /// Insert given file into this point in input stream void openFile(string filename, VFileLine* filelinep=NULL); void debug(int level); ///< Set debugging level string getall(size_t approx_chunk); ///< Return all lines, or at least approx_chunk bytes. (Null if done.) string getline(); ///< Return next line/lines. (Null if done.) bool isEof(); ///< Return true on EOF. void insertUnreadback(string text); VFileLine* fileline(); ///< File/Line number for last getline call // The default behavior is to pass all unknown `defines right through. // This lets the user determine how to report the errors. It also nicely // allows `celldefine and such to remain in the output stream. // CONTROL METHODS // These options control how the parsing proceeds int keepComments() { return m_keepComments; } void keepComments(int flag) { m_keepComments=flag; } // Return comments, 0=no, 1=yes, 2=callback int keepWhitespace() { return m_keepWhitespace; } void keepWhitespace(int flag) { m_keepWhitespace=flag; } // Return extra whitespace bool lineDirectives() { return m_lineDirectives; } void lineDirectives(bool flag) { m_lineDirectives=flag; } // Insert `line directives bool pedantic() { return m_pedantic; } void pedantic(bool flag) { m_pedantic=flag; } // Obey standard; Don't substitute `error bool synthesis() { return m_synthesis; } void synthesis(bool flag) { m_synthesis=flag; } // Ignore translate off // CALLBACK METHODS // This probably will want to be overridden for given child users of this class. virtual void comment(string cmt) = 0; ///< Comment detected (if keepComments==2) virtual void include(string filename) = 0; ///< Request a include file be processed virtual void define(string name, string value, string params) = 0; ///< `define without any parameters virtual void undef(string name) = 0; ///< Remove a definition virtual void undefineall() = 0; ///< Remove all non-command-line definitions virtual bool defExists(string name) = 0; ///< Return true if define exists virtual string defParams(string name) = 0; ///< Return parameter list if define exists virtual string defValue(string name) = 0; ///< Return value of given define (should exist) virtual string defSubstitute(string substitute) = 0; ///< Return value to substitute for given post-parameter value // UTILITIES void error(string msg) { fileline()->error(msg); } ///< Report a error void fatal(string msg) { fileline()->fatal(msg); } ///< Report a fatal error private: VPreProcOpaque* m_opaquep; ///< Pointer to parser's implementation data. }; #endif // Guard Verilog-Perl-3.482/Preproc/typemap0000644000177100017500000000154213422450702017031 0ustar wsnyderwsnyderTYPEMAP const char * T_PV VPreProcXs * O_CTHIS OUTPUT # The variable is stored into a pre-blessed $self->{_cthis} O_CTHIS // SELF->{_cthis} = THIS if( sv_isobject(SELF) && (SvTYPE(SvRV(SELF)) == SVt_PVHV) ) { SV **svp = hv_fetch((HV*)SvRV(SELF), \"_cthis\", 6, 1); sv_setiv(*svp, PTR2IV( $var )); XSRETURN_UNDEF; } else { warn( \"${Package}::$func_name() -- $var is not a Verilog::Preproc object\" ); XSRETURN_UNDEF; } INPUT O_CTHIS $var = NULL; if( sv_isobject($arg) && (SvTYPE(SvRV( $arg )) == SVt_PVHV) ) { SV **svp = hv_fetch((HV*)SvRV(( $arg )), \"_cthis\", 6, 0); $var = NULL; if (svp) { $var = INT2PTR($type,SvIV( *svp )); } } if (!$var || !dynamic_cast($var)) { warn( \"${Package}::$func_name() -- $var is not a Verilog::Preproc object\" ); XSRETURN_UNDEF; } Verilog-Perl-3.482/Preproc/toolhash0000755000177100017500000001621014553624300017177 0ustar wsnyderwsnyder#!/usr/bin/perl -w use Digest::SHA; use File::Copy qw(copy); # Core module use IO::File; use strict; our $Debug; # We don't use getopt, as want multiple in/outs and stop at first command my @opt_name; my @opt_in; # We allow empty opt_in and opt_out so we can cache --version checks. my @opt_out; my @opt_cmd; my @opt_vercmd; my $Opt_Gen = "gen"; my $Opt_Verbose; my $opt_skip_cmd = 0; my $in_cmd; my $list = \@opt_in; while (defined(my $param=shift @ARGV)) { if ($in_cmd) { push @opt_cmd, $param; } elsif ($param =~ /^-?-debug/) { $Debug=1; } elsif ($param =~ /^-?-cmd/) { $in_cmd = 1; } elsif ($param =~ /^-?-in/) { $list = \@opt_in; } elsif ($param =~ /^-?-name/) { $list = \@opt_name; } elsif ($param =~ /^-?-skip-cmd/) { $opt_skip_cmd = shift @ARGV; } elsif ($param =~ /^-?-out/) { $list = \@opt_out; } elsif ($param =~ /^-?-verbose/) { $Opt_Verbose=1; } elsif ($param =~ /^-?-gen/) { $Opt_Gen = shift @ARGV; } elsif ($param =~ /^-?-vercmd/) { $list = \@opt_vercmd; } elsif ($param =~ /^-/) { die "%Error: Unexpected argument: $param,"; } else { push @$list, $param; } } $opt_name[0] ||= $opt_cmd[0]; $opt_vercmd[0] ||= $opt_cmd[0]; $Opt_Verbose = 1 if $Debug; mkdir $Opt_Gen, 0777; # Hash of command, including this program args my $digest = Digest::SHA->new(1); { my $str = 'toolhash_1.0'; $str .= '----'.join(' ',@opt_in); $str .= '----'.join(' ',@opt_out); $str .= '----'; my $i = $opt_skip_cmd; foreach (@opt_cmd) { next if ($i-- > 0); $str.=' '.$_; } $str .= '----'; print "toolhash: Hashing $str\n" if $Debug; $digest->add($str); } foreach my $fn (@opt_in) { print "toolhash: Hashing $fn\n" if $Debug; my $fh = IO::File->new("<$fn") or die "toolhash: %Error: $! reading $fn\n"; $digest->addfile($fh); $fh->close; } my $arcfn = $Opt_Gen."/".$opt_name[0]; my $hash = $digest->b64digest; # Cache hit? If so, fill as we go remove_out(); my $hit = restore($hash, 1); if ($hit) { print "toolhash: Cache hit running $opt_name[0]\n" if $Opt_Verbose; exit(0); } else { print "toolhash: Cache miss running $opt_name[0]\n" if $Opt_Verbose; } remove_named(); my $out = run_cmd(); encache($hash, $out); remove_out(); $hit = restore($hash, 0); exit(0) if $hit; die "toolhash: %Error: encaching failed, didn't hit second time\n"; ####################################################################### sub restore { my $hash = shift; my $pass1 = shift; if ($pass1 && $ENV{TOOLHASH_RECACHE}) { print "toolhash: TOOLHASH_RECACHE set, missing\n" if $Debug; return 0; } # Returns hit my $hit = 1; my $fh = IO::File->new("<${arcfn}-0"); if (!$fh) { print "toolhash: Cache hash empty $arcfn\n" if $Debug; return 0; } my $line = $fh->getline; chomp $line; print "toolhash: Cache hash test $arcfn $line ".$hash."\n" if $Debug; if ($line ne $hash) { print "toolhash: Cache hash miss\n" if $Debug; return 0; } my $n = 1; foreach my $fn (@opt_out) { my $digout = "${arcfn}-${n}"; if (-r $digout) { print "toolhash: Cache hit $digout for $fn\n" if $Debug; # Restore, assuming all hits. copy($digout, $fn) or die "toolhash: %Error: $! on 'cp $digout $fn'\n"; } else { print "toolhash: Cache miss $digout for $fn\n" if $Debug; $hit = 0; last; } $n++; } if ($hit) { print "toolhash: Cache hit\n" if $Debug; if (my $fh = IO::File->new("<${arcfn}-s")) { # Dump stdout print join('',$fh->getlines); $fh->close; } } return $hit; } sub run_cmd { remove_out(); my $cmd = join(' ',@opt_cmd); # We can't use system() as we need the output and fork() isn't portable # without pulling in yet another package, so punt on spaces foreach (@opt_cmd) { if (/ /) { die "%Error: unsupported: spaces in command: '$cmd',"; } } print "\t$cmd\n" if $Debug||1; my $out = `$cmd`; my $status = $?; print $out; if ($status) { remove_out(); # See if bison/gcc/flex --version works my $vcmd = "$opt_vercmd[0] --version"; print "\t$vcmd\n" if $Debug; `$vcmd`; if ($?) { die "\n%Error: '$opt_cmd[0]' must be installed to build\n"; } exit $status >> 8; } return $out; } sub encache { my $hash = shift; my $out = shift; print "toolhash: Encache ".$hash."\n" if $Debug; my $fh = IO::File->new(">${arcfn}-0") or die "toolhash: %Error: $! ${arcfn}-0\n"; $fh->print($hash); $fh->close; if ($out ne "") { $fh = IO::File->new(">${arcfn}-s") or die "toolhash: %Error: $! ${arcfn}-s\n"; $fh->print($out); $fh->close; } my $n = 1; foreach my $fn (@opt_out) { my $digout = "${arcfn}-${n}"; copy($fn, $digout) or die "toolhash: %Error: $! on 'cp $fn $digout'\n"; $n++; } } sub remove_out { unlink for (@opt_out); # Ok if error } sub remove_named { unlink for (glob $Opt_Gen."/$opt_name[0]-*"); # Ok if error } ####################################################################### __END__ =pod =head1 NAME toolhash - Generate and hash files to avoid installation of build tools =head1 SYNOPSIS toolhash --in foo.c --out foo.o --cmd gcc -c -o foo.o foo.c =head1 DESCRIPTION Toolhash is used to install Verilog-Perl and other tools. It stores a hash of generated files (aka the cons make utility) for distribution to avoid building those files from scratch. The hash isn't stored as part of the filename, so that the MANIFEST can remain constant. =head1 ARGUMENTS =over 4 =item --cmd command args... Command and arguments to run. All further arguments are passed to the command. =item --gen ARG Specify location of generated file cache, defaults to "gen". =item --in filenames... Input filenames. =item --name Prefix for output files, or defaults to first --cmd argument. =item --verbose Print hit/miss messages. =item --skip-cmd Disable hashing first num-arg components of the command. This is used to avoid commands like "/usr/bin/perl ...." from hash missing when the Perl version and thus the path changes. =item --out filenames... Output filenames. =item --vercmd command Command to run to get --version. =back =head1 ENVIRONMENT =over 4 =item TOOLHASH_RECACHE Write the cache, but do not read from it. =back =head1 DISTRIBUTION This is part of the L free Verilog EDA software tool suite. The latest version is available from CPAN and from L. Copyright 2010-2024 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. =head1 AUTHORS Wilson Snyder =head1 SEE ALSO C =cut ###################################################################### ### Local Variables: ### compile-command: "echo 'void i() {}' > foo.c; ./toolhash toolhash --debug --in foo.c --out foo.o --cmd gcc -c -o foo.o foo.c ; ls -la foo.* gen/* ; rm foo.*" ### End: Verilog-Perl-3.482/Preproc/Preproc.pm0000644000177100017500000003245314553624343017416 0ustar wsnyderwsnyder# Verilog - Verilog Perl Interface # See copyright, etc in below POD section. ###################################################################### package Verilog::Preproc; use Carp; use Verilog::Getopt; require DynaLoader; use base qw(DynaLoader); use strict; use vars qw($VERSION); $VERSION = '3.482'; ###################################################################### #### Configuration Section bootstrap Verilog::Preproc; #In Preproc.xs: # sub _new (class, keepcmt, linedir, pedantic, synthesis) # sub _open (class) # sub getall (class) # sub getline (class) # sub eof (class) # sub filename (class) # sub lineno (class) # sub unreadback (class, text) ###################################################################### #### Accessors sub new { my $class = shift; $class = ref $class if ref $class; my $self = {keep_comments=>1, keep_whitespace=>1, line_directives=>1, ieee_predefined=>1, pedantic=>0, synthesis=>0, options=>Verilog::Getopt->new(), # If the user didn't give one, still work! parent => undef, #include_open_nonfatal=>0, @_}; bless $self, $class; # Sets $self->{_cthis} $self->{keep_comments} = 2 if ($self->{keep_comments} eq 'sub'); $self->{keep_comments} = 3 if ($self->{keep_comments} eq 'expand'); #TBD $self->_new($self, $self->{keep_comments}, $self->{keep_whitespace}, $self->{line_directives}, $self->{pedantic}, $self->{synthesis}, ); if ($self->{synthesis}) { # Fourth argument 1 for cmdline - no `undefineall effect $self->define('SYNTHESIS',1,undef,1); } if ($self->{ieee_predefined}) { $self->define('SV_COV_START', 0,undef,1); $self->define('SV_COV_STOP', 1,undef,1); $self->define('SV_COV_RESET', 2,undef,1); $self->define('SV_COV_CHECK', 3,undef,1); $self->define('SV_COV_MODULE', 10,undef,1); $self->define('SV_COV_HIER', 11,undef,1); $self->define('SV_COV_ASSERTION', 20,undef,1); $self->define('SV_COV_FSM_STATE', 21,undef,1); $self->define('SV_COV_STATEMENT', 22,undef,1); $self->define('SV_COV_TOGGLE', 23,undef,1); $self->define('SV_COV_OVERFLOW', -2,undef,1); $self->define('SV_COV_ERROR', -1,undef,1); $self->define('SV_COV_NOCOV', 0,undef,1); $self->define('SV_COV_OK', 1,undef,1); $self->define('SV_COV_PARTIAL', 2,undef,1); } #use Data::Dumper; print Dumper($self); return $self; } sub DESTROY { my $self = shift; $self->_DESTROY; } sub STORABLE_freeze { my ($self, $cloning) = @_; # Prevent crash on Storable::store then retrieve delete $self->{_cthis}; return; } sub open { my $self = shift; my %params = ( # filename => # open_nonfatal => 0, ); if ($#_ > 0) { %params=(@_); } else { $params{filename}=shift; } # We allow either open(name) or open(filename=>name); # Allow user to put `defined names on the command line instead of filenames, # then convert them properly. my $filename = $params{filename}; $filename = $self->remove_defines($filename); printf ("Perl open $filename\n") if $self->{debug}; $filename = $self->{options}->file_path($filename); printf ("Perl openfp $filename\n") if $self->{debug}; if (!-r $filename) { if (!$params{open_nonfatal}) { $self->error("Cannot open $filename"); } return undef; } else { $self->_open($filename); } return $self; } sub debug { my $self = shift; my $level = shift; $self->{debug} = $level; $self->_debug($level); } sub parent { my $self = shift; return $self->{parent}; } ###################################################################### #### Utilities sub remove_defines { my $self = shift; my $sym = shift; my $val = "x"; while (defined $val) { last if $sym eq $val; (my $xsym = $sym) =~ s/^\`//; $val = $self->{options}->defvalue_nowarn($xsym); #Undef if not found $sym = $val if defined $val; } return $sym; } sub fileline { my $self = shift; return ($self->filename||"").":".($self->lineno||""); } ###################################################################### #### Called by the parser sub error { my ($self,$text,$token)=@_; my $fileline = $self->filename.":".$self->lineno; croak ("%Error: $fileline: $text\n" ."Stopped"); } sub comment {} sub def_substitute { my ($self, $out) = @_; return $out; } sub include { my ($self,$filename)=@_; print "INCLUDE $filename\n" if $self->{debug}; $self->{options}->includes($self->filename, $filename); $self->open(filename => $filename, open_nonfatal => $self->{include_open_nonfatal}, ); } # Note rather than overriding these, a derived Verilog::Getopt class can # accomplish the same thing. sub undef { my $self = shift; $self->{options}->undef(@_); } sub undefineall { my $self = shift; $self->{options}->undefineall(@_); } sub define { my $self = shift; #print "DEFINE @_\n"; $self->{options}->fileline($self->filename.":".$self->lineno); $self->{options}->define(@_); } sub def_params { # Return define parameters my $self = shift; my $val = $self->{options}->defparams(@_); #printf "DEFPARAMS @_ -> %s\n", $val if $self->{debug}; $val = "" if !defined $val; return $val; } sub def_value { # Return value my $self = shift; #printf "DEFVALUE @_ -> %s\n", $self->{options}->defvalue_nowarn(@_); return $self->{options}->defvalue(@_); } ###################################################################### #### Package return 1; __END__ =pod =head1 NAME Verilog::Preproc - Preprocess Verilog files =head1 SYNOPSIS use Verilog::Getopt; my $vp = Verilog::Preproc->new(I); $vp->open(filename=>"verilog_file.v"); my $line = $vp->getline(); =head1 EXAMPLE # This is a complete verilog pre-parser! # For a command line version, see vppreproc use Verilog::Getopt; use Verilog::Preproc; my $opt = new Verilog::Getopt; @ARGV = $opt->parameter(@ARGV); my $vp = Verilog::Preproc->new(options=>$opt,); $vp->open(filename=>"verilog_file.v"); while (defined (my $line = $vp->getline())) { print $line; } =head1 DESCRIPTION Verilog::Preproc reads Verilog files, and preprocesses them according to the SystemVerilog 2009 (1800-2009) specification. Programs can be easily converted from reading a IO::File into reading preprocessed output from Verilog::Preproc. See the "Which Package" section of L if you are unsure which parsing package to use for a new application. =head1 MEMBER FUNCTIONS =over 4 =item $self->eof() Returns true at the end of the file. =item $self->filename() Returns the filename of the most recently returned getline(). May not match the filename passed on the command line, as `line directives are honored. =item $self->getall() Return the entire translated text up to the final EOF, similar to calling join('',$self->getline) but significantly faster. With optional argument, returns approximately that number of characters. Returns undef at EOF. =item $self->getline() Return the next line of text. Returns undef at EOF. (Just like IO::File->getline().) =item $self->lineno() Returns the line number of the last getline(). Note that the line number may change several times between getline(), for example when traversing multiple include files. =item $self->parent() Returns a reference to the Verilog::Netlist::File which created this object, if any. =item $self->new(I) Creates a new preprocessor. See the PARAMETERS section for the options that may be passed to new. =item $self->open(filename=>I) Opens the specified file. If filename ends in .gz, decompress while reading. If called before a file is completely parsed, the new file will be parsed completely before returning to the previously open file. (As if it was an include file.) Open may also be called without named parameters, in which case the only argument is the filename. =item $self->unreadback(I) Insert text into the input stream at the given point. The text will not be parsed, just returned to the application. This lets comment() callbacks insert special code into the output stream. =back =head1 PARAMETERS The following named parameters may be passed to the new constructor. =over 4 =item ieee_predefines=>0 With ieee_predefines false, disable defining SV_COV_START and other IEEE mandated definitions. =item include_open_nonfatal=>1 With include_open_nonfatal set to one, ignore any include files that do not exist. =item keep_comments=>0 With keep_comments set to zero, strip all comments. When set to one (the default), insert comments in output streams. When set to 'sub', call the comment() function so that meta-comments can be processed outside of the output stream. Note that some programs use meta-comments to embed useful information (synthesis and lint), so strip with caution if feeding to tools other than your own. Defaults to 1. =item keep_whitespace=>0 With keep_whitespace set to zero, compress all whitespace to a single space or newline. When set to one (the default), retain whitespace. Defaults to 1. =item line_directives=>0 With line_directives set to zero, suppress "`line" comments which indicate filename and line number changes. Use the lineno() and filename() methods instead to retrieve this information. Defaults true. =item options=>Verilog::Getopt object Specifies the object to be used for resolving filenames and defines. Other classes may be used, as long as their interface matches that of Getopt. =item pedantic=>1 With pedantic set, rigorously obey the Verilog pedantic. This used to disable the `__FILE__ and `__LINE__ features but no longer does as they were added to the 1800-2009 standard. It remains to disable `error and may disable other future features that are not specified in the language standard. Defaults false. =item synthesis=>1 With synthesis set, define SYNTHESIS, and ignore text between "ambit", "pragma", "synopsys" or "synthesis" translate_off and translate_on meta comments. Note using metacomments is discouraged as they have led to silicon bugs (versus ifdef SYNTHESIS); see L. =back =head1 CALLBACKS Default callbacks are implemented that are suitable for most applications. Derived classes may override these callbacks as needed. =over 4 =item $self->comment(I) Called with each comment, when keep_comments=>'sub' is used. Defaults to do nothing. =item $self->undef(I) Called with each `undef. Defaults to use options object. =item $self->undefineall() Called with each `undefineall. Defaults to use options object. =item $self->define(I, I, I) Called with each `define. Defaults to use options object. =item $self->def_params(I) Called to determine if the define exists and the parameters it expects. Return undef if the define doesn't exist, 0 if the define exists with no arguments, or argument list with leading parenthesis if the define has arguments. Defaults to use options object's defparams method. =item $self->def_substitute(I) Called to determine what string to insert for a define substitution. Called with the value of the define after parameters have been expanded computed per the SystemVerilog spec. Generally this function would just return the same string as it is passed, but this can be overridden to allow customized preprocessing. =item $self->def_value(I) Called to return value to substitute for specified define. Defaults to use options object. =item $self->error(I) Called on errors, with the error message as an argument. Defaults to die. =item $self->include(I) Specifies a include file has been found. Defaults to call $self->open after resolving the filename with the options parameter. =back =head1 COMPLIANCE The preprocessor supports the constructs defined in the SystemVerilog 2017 standard (IEEE 1800-2017), which is a superset of Verilog 1995 (IEEE 1364-1995), Verilog 2001 (IEEE 1364-2001), Verilog 2005 (IEEE 1364-2005) SystemVerilog 2005 (IEEE 1800-2005), SystemVerilog 2009 (IEEE 1800-2009), and SystemVerilog 2012 (IEEE 1800-2012). Verilog::Preproc adds the `error macro (unless the pedantic parameter is set.): =over 4 =item `__FILE__ The __FILE__ define expands to the current filename as a string, like C++'s __FILE__. This was incorporated into to the 1800-2009 standard (but supported by Verilog-Perl since 2004!) =item `__LINE__ The __LINE__ define expands to the current filename as a string, like C++'s __LINE__. This was incorporated into to the 1800-2009 standard (but supported by Verilog-Perl since 2004!) =item `error I<"string"> `error will be reported whenever it is encountered. (Like C++ #error.) These are useful for error macros, similar to assert() in C++. =back =head1 DISTRIBUTION Verilog-Perl is part of the L free Verilog EDA software tool suite. The latest version is available from CPAN and from L. Copyright 2000-2024 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. =head1 AUTHORS Wilson Snyder =head1 SEE ALSO L, L, L L This package is layered on a C++ interface which may be found in the kit. =cut Verilog-Perl-3.482/Preproc/Preproc.xs0000644000177100017500000002472414553624300017427 0ustar wsnyderwsnyder#/* Verilog.xs -- Verilog Booter -*- C++ -*- #********************************************************************* #* #* DESCRIPTION: Verilog::Preproc Perl XS interface #* #* Author: Wilson Snyder #* #* Code available from: https://www.veripool.org/ #* #********************************************************************* #* #* Copyright 2000-2024 by Wilson Snyder. This program is free software; #* you can redistribute it and/or modify it under the terms of either the GNU #* Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. #* #* This program is distributed in the hope that it will be useful, #* but WITHOUT ANY WARRANTY; without even the implied warranty of #* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the #* GNU General Public License for more details. #* #* You should have received a copy of the Perl Artistic License #* along with this module; see the file COPYING. If not, see #* www.cpan.org #* #*********************************************************************** #* Note with C++ XS libraries, the CLASS parameter is implied... #***********************************************************************/ /* Mine: */ #include "VPreProc.h" #include /* Perl */ extern "C" { # include "EXTERN.h" # include "perl.h" # include "XSUB.h" } #ifdef open # undef open /* Perl 64 bit on solaris has a nasty hack that redefines open */ #endif class VFileLineXs; #//********************************************************************** #// Preprocessor derived classes, so we can override the callbacks to call perl. class VPreProcXs : public VPreProc { public: SV* m_self; // Class called from (the hash, not SV pointing to the hash) deque m_filelineps; VPreProcXs() : VPreProc() {} virtual ~VPreProcXs(); // Callback methods virtual void comment(string filename); // Comment for keepComments=>sub virtual void include(string filename); // Request a include file be processed virtual void define(string name, string value, string params); // `define with parameters virtual void undef(string name); // Remove a definition virtual void undefineall(); // Remove all non-command-line definitions virtual bool defExists(string name); // Return true if define exists virtual string defParams(string name); // Return parameter list if define exists virtual string defValue(string name); // Return value of given define (should exist) virtual string defSubstitute(string substitute); // Return value to substitute for given post-parameter value void call(string* rtnStrp, int params, const char* method, ...); void unreadback(char* text); }; class VFileLineXs : public VFileLine { VPreProcXs* m_vPreprocp; // Parser handling the errors public: VFileLineXs(VPreProcXs* pp) : VFileLine(true), m_vPreprocp(pp) { if (pp) pushFl(); } virtual ~VFileLineXs() { } virtual VFileLine* create(const string& filename, int lineno) { VFileLineXs* filelp = new VFileLineXs(m_vPreprocp); filelp->init(filename, lineno); return filelp; } virtual void error(const string& msg); // Report a error at given location void setPreproc(VPreProcXs* pp) { m_vPreprocp=pp; pushFl(); // The very first construction used pp=NULL, as pp wasn't created yet so make it now } // Record the structure so we can delete it later void pushFl() { m_vPreprocp->m_filelineps.push_back(this); } }; #//********************************************************************** #// Overrides error handling virtual functions to invoke callbacks void VFileLineXs::error(const string& msg) { static string holdmsg; holdmsg = msg; m_vPreprocp->call(NULL, 1,"error",holdmsg.c_str()); } #//********************************************************************** #// VPreProcXs functions VPreProcXs::~VPreProcXs() { for (deque::iterator it=m_filelineps.begin(); it!=m_filelineps.end(); ++it) { delete *it; } } #//********************************************************************** #// Overrides of virtual functions to invoke callbacks void VPreProcXs::comment(string cmt) { static string holdcmt; holdcmt = cmt; call(NULL, 1,"comment",holdcmt.c_str()); } void VPreProcXs::include(string filename) { static string holdfilename; holdfilename = filename; call(NULL, 1,"include",holdfilename.c_str()); } void VPreProcXs::undef(string define) { static string holddefine; holddefine = define; call(NULL, 1,"undef", holddefine.c_str()); } void VPreProcXs::undefineall() { call(NULL, 0,"undefineall"); } void VPreProcXs::define(string define, string value, string params) { static string holddefine; holddefine = define; static string holdvalue; holdvalue = value; static string holdparams; holdparams = params; // 4th argument is cmdline; always undef from here call(NULL, 3,"define", holddefine.c_str(), holdvalue.c_str(), holdparams.c_str()); } bool VPreProcXs::defExists(string define) { return defParams(define)!=""; } string VPreProcXs::defParams(string define) { static string holddefine; holddefine = define; string paramStr; call(¶mStr, 1,"def_params", holddefine.c_str()); return paramStr; } string VPreProcXs::defValue(string define) { static string holddefine; holddefine = define; string valueStr; call(&valueStr, 1,"def_value", holddefine.c_str()); return valueStr; } string VPreProcXs::defSubstitute(string subs) { static string holdsubs; holdsubs = subs; string outStr; call(&outStr, 1, "def_substitute", holdsubs.c_str()); return outStr; } void VPreProcXs::call( string* rtnStrp, /* If non-null, load return value here */ int params, /* Number of parameters. Negative frees the parameters */ const char* method, /* Name of method to call */ ...) /* Arguments to pass to method's @_ */ { // Call $perlself->method (passedparam1, parsedparam2) va_list ap; va_start(ap, method); { dSP; /* Initialize stack pointer */ ENTER; /* everything created after here */ SAVETMPS; /* ...is a temporary variable. */ PUSHMARK(SP); /* remember the stack pointer */ SV* selfsv = newRV_inc(m_self); /* $self-> */ XPUSHs(sv_2mortal(selfsv)); while (params--) { char* text = va_arg(ap, char *); SV* sv; if (text) { sv = sv_2mortal(newSVpv(text, 0)); } else { sv = &PL_sv_undef; } XPUSHs(sv); /* token */ } PUTBACK; /* make local stack pointer global */ if (rtnStrp) { int rtnCount = perl_call_method((char*)method, G_SCALAR); SPAGAIN; /* refresh stack pointer */ if (rtnCount > 0) { SV* sv = POPs; //printf("RTN %ld %d %s\n", SvTYPE(sv),SvTRUE(sv),SvPV_nolen(sv)); #ifdef SvPV_nolen // Perl 5.6 and later *rtnStrp = SvPV_nolen(sv); #else *rtnStrp = SvPV(sv,PL_na); #endif } PUTBACK; } else { perl_call_method((char*)method, G_DISCARD | G_VOID); } FREETMPS; /* free that return value */ LEAVE; /* ...and the XPUSHed "mortal" args.*/ } va_end(ap); } #//********************************************************************** MODULE = Verilog::Preproc PACKAGE = Verilog::Preproc #//********************************************************************** #// self->_new(class, keepcmt, keepwhite, linedir, pedantic, synthesis) static VPreProcXs * VPreProcXs::_new(SELF, keepcmt, keepwhite, linedir, pedantic, synthesis) SV *SELF int keepcmt int keepwhite int linedir int pedantic int synthesis PROTOTYPE: $$$$$$ CODE: { if (CLASS) {} /* Prevent unused warning */ if (!SvROK(SELF)) { warn("${Package}::$func_name() -- SELF is not a hash reference"); } VFileLineXs* filelinep = new VFileLineXs(NULL/*ok,for initial*/); VPreProcXs* preprocp = new VPreProcXs(); filelinep->setPreproc(preprocp); preprocp->m_self = SvRV(SELF); preprocp->keepComments(keepcmt); preprocp->keepWhitespace(keepwhite); preprocp->lineDirectives(linedir); preprocp->pedantic(pedantic); preprocp->synthesis(synthesis); preprocp->configure(filelinep); RETVAL = preprocp; } OUTPUT: RETVAL #//********************************************************************** #// self->_DESTROY() void VPreProcXs::_DESTROY() PROTOTYPE: $ CODE: { delete THIS; } #//********************************************************************** #// self->debug() void VPreProcXs::_debug(level) int level PROTOTYPE: $$ CODE: { THIS->debug(level); } #//********************************************************************** #// self->lineno() int VPreProcXs::lineno() PROTOTYPE: $ CODE: { if (!THIS) XSRETURN_UNDEF; RETVAL = (THIS->fileline()->lineno()); } OUTPUT: RETVAL #//********************************************************************** #// self->filename() SV* VPreProcXs::filename() PROTOTYPE: $ CODE: { if (!THIS) XSRETURN_UNDEF; string ret = THIS->fileline()->filename(); RETVAL = newSVpv(ret.c_str(), ret.length()); } OUTPUT: RETVAL #//********************************************************************** #// self->unreadback() void VPreProcXs::unreadback(text) char* text PROTOTYPE: $$ CODE: { if (!THIS) XSRETURN_UNDEF; THIS->insertUnreadback((string)text); } #//********************************************************************** #// self->getall() SV* VPreProcXs::getall(approx_chunk=0) size_t approx_chunk PROTOTYPE: $;$ CODE: { static string holdline; if (!THIS || THIS->isEof()) XSRETURN_UNDEF; string lastline = THIS->getall(approx_chunk); holdline = lastline; /* Stash it so c_str() doesn't disappear immediately */ if (holdline=="" && THIS->isEof()) XSRETURN_UNDEF; RETVAL = newSVpv(lastline.c_str(), lastline.length()); } OUTPUT: RETVAL #//********************************************************************** #// self->getline() SV* VPreProcXs::getline() PROTOTYPE: $ CODE: { static string holdline; if (!THIS || THIS->isEof()) XSRETURN_UNDEF; string lastline = THIS->getline(); holdline = lastline; /* Stash it so c_str() doesn't disappear immediately */ if (holdline=="" && THIS->isEof()) XSRETURN_UNDEF; RETVAL = newSVpv(lastline.c_str(), lastline.length()); } OUTPUT: RETVAL #//********************************************************************** #// self->eof() int VPreProcXs::eof() PROTOTYPE: $ CODE: { RETVAL = THIS->isEof(); } OUTPUT: RETVAL #//********************************************************************** #// self->_open(filename) int VPreProcXs::_open(filename) const char *filename PROTOTYPE: $$ CODE: { if (!THIS) XSRETURN_UNDEF; THIS->openFile(filename); RETVAL = 1; } OUTPUT: RETVAL Verilog-Perl-3.482/Preproc/VFileLine.h0000644000177100017500000000634514553624300017426 0ustar wsnyderwsnyder// -*- C++ -*- //************************************************************************* // // Copyright 2000-2024 by Wilson Snyder. This program is free software; // you can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. // // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // //************************************************************************* /// \file /// \brief Verilog::Preproc: Error handling /// /// Authors: Wilson Snyder /// /// Code available from: https://www.veripool.org/verilog-perl /// //************************************************************************* #ifndef _VFILELINE_H_ #define _VFILELINE_H_ 1 #include #include #include using namespace std; //============================================================================ // VFileLine /// User information and error reporting functions //// /// Users can override this class to implement their own error handling class VFileLine { private: int m_lineno; ///< Line number in file string m_filename; ///< File name static int s_numErrors; ///< Number of errors detected protected: VFileLine(int called_only_for_default) {init("",0);} public: // CONSTRUCTORS /// Create a new fileline, for a new file and/or line number. /// Member functions, so that if a user provides another class, a change in the /// filename/linenumber will create a new element using the derived class. virtual VFileLine* create(const string& filename, int lineno) = 0; /// Create with same filename, new line number; just calls create(fn,ln) virtual VFileLine* create(int lineno) { return create(filename(), lineno); } virtual void init(const string& filename, int lineno); virtual ~VFileLine() {} // ACCESSORS int lineno() const { return m_lineno; } ///< Return line number void linenoIncInPlace() { m_lineno++; } ///< Increment line IN PLACE; normally use create() instead const string filename() const { return m_filename; } ///< Return filename const string filebasename() const; ///< Filename with any directory stripped string lineDirectiveStrg(int enter_exit_level) const; // METHODS virtual void fatal(const string& msg); ///< Report a fatal error at given location virtual void error(const string& msg); ///< Report a error at given location VFileLine* lineDirective(const char* textp, int& enterExitRef); // STATIC METHODS static int numErrors() { return s_numErrors; } ///< Return total errors detected // Internal methods -- special use static const char* itoa(int i); ///< Internal: Not reentrant! - for fatalSrc() only }; ostream& operator<<(ostream& os, VFileLine* fileline); /// Use this instead of fatal() to mention the source code line. #define fatalSrc(msg) fatal((string)"Internal Error: "+__FILE__+":"+VFileLine::itoa(__LINE__)+": "+(msg)) template< class T> std::string cvtToStr(const T& t) { ostringstream os; os< #include #include #include #include #include #include #include #include #include #include #include #include #if defined(_WIN32) && !defined(__MINGW32__) && !defined(__CYGWIN__) # include #else # include #endif #include "VPreProc.h" #include "VPreLex.h" //#undef yyFlexLexer //#define yyFlexLexer xxFlexLexer //#include //************************************************************************* class VPreDefRef { // One for each pending define substitution string m_name; // Define last name being defined string m_params; // Define parameter list for next expansion string m_nextarg; // String being built for next argument int m_parenLevel; // Parenthesis counting inside def args (for PARENT not child) vector m_args; // List of define arguments public: string name() const { return m_name; } string params() const { return m_params; } string nextarg() const { return m_nextarg; } void nextarg(const string& value) { m_nextarg = value; } int parenLevel() const { return m_parenLevel; } void parenLevel(int value) { m_parenLevel = value; } vector& args() { return m_args; } VPreDefRef(const string& name, const string& params) : m_name(name), m_params(params), m_parenLevel(0) {} ~VPreDefRef() {} }; //************************************************************************* /// Data for parsing on/off class VPreIfEntry { // One for each pending ifdef/ifndef bool m_on; // Current parse for this ifdef level is "on" bool m_everOn; // Some if term in elsif tree has been on public: bool on() const { return m_on; } bool everOn() const { return m_everOn; } VPreIfEntry(bool on, bool everOn) : m_on(on), m_everOn(everOn || on) {} // Note everOn includes new state ~VPreIfEntry() {} }; //************************************************************************* /// Data for a preprocessor instantiation. class VPreProcImp : public VPreProcOpaque { public: typedef list StrList; VPreProc* m_preprocp; ///< Object we're holding data for int m_debug; ///< Debugging level VPreLex* m_lexp; ///< Current lexer state (NULL = closed) enum ProcState { ps_TOP, ps_DEFNAME_UNDEF, ps_DEFNAME_DEFINE, ps_DEFNAME_IFDEF, ps_DEFNAME_IFNDEF, ps_DEFNAME_ELSIF, ps_DEFFORM, ps_DEFVALUE, ps_DEFPAREN, ps_DEFARG, ps_INCNAME, ps_ERRORNAME, ps_JOIN, ps_STRIFY }; static const char* procStateName(ProcState s) { static const char* states[] = {"ps_TOP", "ps_DEFNAME_UNDEF", "ps_DEFNAME_DEFINE", "ps_DEFNAME_IFDEF", "ps_DEFNAME_IFNDEF", "ps_DEFNAME_ELSIF", "ps_DEFFORM", "ps_DEFVALUE", "ps_DEFPAREN", "ps_DEFARG", "ps_INCNAME", "ps_ERRORNAME", "ps_JOIN", "ps_STRIFY" }; return states[s]; }; stack m_states; ///< Current state of parser int m_off; ///< If non-zero, ifdef level is turned off, don't dump text string m_lastSym; ///< Last symbol name found. string m_formals; ///< Last formals found // For getRawToken/ `line insertion string m_lineCmt; ///< Line comment(s) to be returned bool m_lineCmtNl; ///< Newline needed before inserting lineCmt int m_lineAdd; ///< Empty lines to return to maintain line count bool m_rawAtBol; ///< Last rawToken left us at beginning of line // For getFinalToken bool m_finAhead; ///< Have read a token ahead int m_finToken; ///< Last token read string m_finBuf; ///< Last yytext read bool m_finAtBol; ///< Last getFinalToken left us at beginning of line VFileLine* m_finFilelinep; ///< Location of last returned token (internal only) // For stringification string m_strify; ///< Text to be stringified // For defines stack m_defRefs; // Pending definine substitution stack m_ifdefStack; ///< Stack of true/false emitting evaluations unsigned m_defDepth; ///< How many `defines deep bool m_defPutJoin; ///< Insert `` after substitution // For `` join stack m_joinStack; ///< Text on lhs of join // For getline() string m_lineChars; ///< Characters left for next line VPreProcImp() { m_debug = 0; m_states.push(ps_TOP); m_off = 0; m_lineChars = ""; m_lastSym = ""; m_lineAdd = 0; m_lineCmtNl = false; m_rawAtBol = true; m_finAhead = false; m_finAtBol = true; m_defDepth = 0; m_defPutJoin = false; m_finToken = 0; m_finFilelinep = NULL; m_lexp = NULL; m_preprocp = NULL; } void configure(VFileLine* filelinep, VPreProc* preprocp) { // configure() separate from constructor to avoid calling abstract functions m_preprocp = preprocp; m_finFilelinep = filelinep->create(1); // Create lexer m_lexp = new VPreLex(this, filelinep); m_lexp->m_keepComments = m_preprocp->keepComments(); m_lexp->m_keepWhitespace = m_preprocp->keepWhitespace(); m_lexp->m_pedantic = m_preprocp->pedantic(); m_lexp->m_synthesis = m_preprocp->synthesis(); m_lexp->debug(debug()>=10 ? debug() : 0); // See also VPreProc::debug() method } ~VPreProcImp() { if (m_lexp) { delete m_lexp; m_lexp = NULL; } } const char* tokenName(int tok); void debugToken(int tok, const char* cmtp); void parseTop(); void parseUndef(); string getparseline(bool stop_at_eol, size_t approx_chunk); bool isEof() const { return m_lexp->curStreamp()->m_eof; } bool readWholefile(const string& filename, StrList& outl); void openFile(string filename, VFileLine* filelinep); void insertUnreadback(const string& text) { m_lineCmt += text; } void insertUnreadbackAtBol(const string& text); void addLineComment(int enter_exit_level); private: void error(string msg) { m_lexp->m_tokFilelinep->error(msg); } void fatal(string msg) { m_lexp->m_tokFilelinep->fatal(msg); } int debug() const { return m_debug; } void endOfOneFile(); string defineSubst(VPreDefRef* refp); string trimWhitespace(const string& strg, bool trailing); void unputString(const string& strg); void unputDefrefString(const string& strg); void parsingOn() { m_off--; if (m_off<0) fatalSrc("Underflow of parsing cmds"); // addLineComment no longer needed; getFinalToken will correct. } void parsingOff() { m_off++; } int getRawToken(); int getStateToken(string& buf); int getFinalToken(string& buf); ProcState state() const { return m_states.top(); } bool stateIsDefname() const { return state()==ps_DEFNAME_UNDEF || state()==ps_DEFNAME_DEFINE || state()==ps_DEFNAME_IFDEF || state()==ps_DEFNAME_IFNDEF || state()==ps_DEFNAME_ELSIF; } void statePush(ProcState state) { m_states.push(state); } void statePop() { m_states.pop(); if (m_states.empty()) { error("InternalError: Pop of parser state with nothing on stack"); m_states.push(ps_TOP); } } void stateChange(ProcState state) { statePop(); statePush(state); } }; //************************************************************************* // Creation VPreProc::VPreProc() { VPreProcImp* idatap = new VPreProcImp(); m_opaquep = idatap; // Below overridden by configure() m_keepComments = true; m_keepWhitespace = true; m_lineDirectives = true; m_pedantic = false; m_synthesis = false; } void VPreProc::configure(VFileLine* filelinep) { VPreProcImp* idatap = static_cast(m_opaquep); idatap->configure(filelinep, this); } VPreProc::~VPreProc() { if (m_opaquep) { delete m_opaquep; m_opaquep = NULL; } } //************************************************************************* // VPreProc Methods. Just call the implementation functions. void VPreProc::comment(string cmt) { } void VPreProc::openFile(string filename, VFileLine* filelinep) { VPreProcImp* idatap = static_cast(m_opaquep); idatap->openFile(filename,filelinep); } string VPreProc::getline() { VPreProcImp* idatap = static_cast(m_opaquep); return idatap->getparseline(true,0); } string VPreProc::getall(size_t approx_chunk) { VPreProcImp* idatap = static_cast(m_opaquep); return idatap->getparseline(false,approx_chunk); } void VPreProc::debug(int level) { VPreProcImp* idatap = static_cast(m_opaquep); idatap->m_debug = level; // To see "accepting rule" debug, Makefile.PL must be changed to enable flex debug // export VERILOGPERL_FLEX_DEBUG=1 idatap->m_lexp->debug(level>=10 ? level : 0); } bool VPreProc::isEof() { VPreProcImp* idatap = static_cast(m_opaquep); return idatap->isEof(); } VFileLine* VPreProc::fileline() { VPreProcImp* idatap = static_cast(m_opaquep); return idatap->m_lexp->m_tokFilelinep; } void VPreProc::insertUnreadback(string text) { VPreProcImp* idatap = static_cast(m_opaquep); return idatap->insertUnreadback(text); } //********************************************************************** // Parser Utilities const char* VPreProcImp::tokenName(int tok) { switch (tok) { case VP_BACKQUOTE : return("BACKQUOTE"); case VP_COMMENT : return("COMMENT"); case VP_DEFARG : return("DEFARG"); case VP_DEFFORM : return("DEFFORM"); case VP_DEFINE : return("DEFINE"); case VP_DEFREF : return("DEFREF"); case VP_DEFREF_JOIN : return("DEFREF_JOIN"); case VP_DEFVALUE : return("DEFVALUE"); case VP_ELSE : return("ELSE"); case VP_ELSIF : return("ELSIF"); case VP_ENDIF : return("ENDIF"); case VP_EOF : return("EOF"); case VP_ERROR : return("ERROR"); case VP_IFDEF : return("IFDEF"); case VP_IFNDEF : return("IFNDEF"); case VP_JOIN : return("JOIN"); case VP_INCLUDE : return("INCLUDE"); case VP_LINE : return("LINE"); case VP_PSL : return("PSL"); case VP_STRIFY : return("STRIFY"); case VP_STRING : return("STRING"); case VP_SYMBOL : return("SYMBOL"); case VP_SYMBOL_JOIN : return("SYMBOL_JOIN"); case VP_TEXT : return("TEXT"); case VP_UNDEF : return("UNDEF"); case VP_UNDEFINEALL : return("UNDEFINEALL"); case VP_WHITE : return("WHITE"); default: return("?"); } } void VPreProcImp::unputString(const string& strg) { // Note: The preliminary call in ::openFile bypasses this function // We used to just m_lexp->unputString(strg.c_str()); // However this can lead to "flex scanner push-back overflow" // so instead we scan from a temporary buffer, then on EOF return. // This is also faster than the old scheme, amazingly. if (m_lexp->m_bufferState!=m_lexp->currentBuffer()) { fatalSrc("bufferStack missing current buffer; will return incorrectly"); // Hard to debug lost text as won't know till much later } m_lexp->scanBytes(strg); } void VPreProcImp::unputDefrefString(const string& strg) { int multiline = 0; for (size_t i=0; icurStreamp()->m_ignNewlines += multiline; // Must be after unput - applies to new stream } string VPreProcImp::trimWhitespace(const string& strg, bool trailing) { // Remove leading whitespace string out = strg; string::size_type leadspace = 0; while (out.length() > leadspace && isspace(out[leadspace])) leadspace++; if (leadspace) out.erase(0,leadspace); // Remove trailing whitespace if (trailing) { string::size_type trailspace = 0; while (out.length() > trailspace && isspace(out[out.length()-1-trailspace])) trailspace++; // Don't remove \{space_or_newline} if (trailspace && out.length() > trailspace && out[out.length()-1-trailspace]=='\\') trailspace--; if (trailspace) out.erase(out.length()-trailspace,trailspace); } return out; } string VPreProcImp::defineSubst(VPreDefRef* refp) { // Substitute out defines in a define reference. // (We also need to call here on non-param defines to handle `") // We could push the define text back into the lexer, but that's slow // and would make recursive definitions and parameter handling nasty. // // Note we parse the definition parameters and value here. If a // parametrized define is used many, many times, we could cache the // parsed result. if (debug()>=5) { cout<<"defineSubstIn `"<name()<<" "<params()<args().size(); i++) { cout<<"defineArg["<args()[i]<<"'"<defValue(refp->name()); if (debug()>=5) cout<<"defineValue '"< argValueByName; { // Parse argument list into map unsigned numArgs=0; string argName; int paren = 1; // (), {} and [] can use same counter, as must be matched pair per spec string token; bool quote = false; bool haveDefault = false; // Note there's a leading ( and trailing ), so parens==1 is the base parsing level string params = refp->params(); // Must keep str in scope to get pointer const char* cp=params.c_str(); if (*cp == '(') cp++; for (; *cp; cp++) { //if (debug()>=5) cout <<" Parse Paren="<args().size() > numArgs) { // A call `def( a ) must be equivelent to `def(a ), so trimWhitespace // At one point we didn't trim trailing whitespace, but this confuses `" string arg = trimWhitespace(refp->args()[numArgs], true); if (arg != "") valueDef = arg; } else if (!haveDefault) { error("Define missing argument '"+argName+"' for: "+refp->name()+"\n"); return " `"+refp->name()+" "; } numArgs++; } argValueByName[argName] = valueDef; // Prepare for next argName = ""; token = ""; haveDefault = false; continue; } else if (*cp=='=') { haveDefault = true; argName = token; token = ""; continue; } } if (cp[0]=='\\' && cp[1]) { token += cp[0]; // \{any} Put out literal next character token += cp[1]; cp++; continue; } if (!quote) { if (*cp=='(' || *cp=='{' || *cp=='[') paren++; else if (*cp==')' || *cp=='}' || *cp==']') paren--; } if (*cp=='"') quote=!quote; if (*cp) token += *cp; } if (refp->args().size() > numArgs // `define X() is ok to call with nothing && !(refp->args().size()==1 && numArgs==0 && trimWhitespace(refp->args()[0],false)=="")) { error("Define passed too many arguments: "+refp->name()+"\n"); return " `"+refp->name()+" "; } } string out = ""; { // Parse substitution define using arguments string argName; bool quote = false; bool backslashesc = false; // In \.....{space} block // Note we go through the loop once more at the NULL end-of-string for (const char* cp=value.c_str(); (*cp) || argName!=""; cp=(*cp?cp+1:cp)) { //cout << "CH "<<*cp<<" an "<::iterator iter = argValueByName.find(argName); if (iter != argValueByName.end()) { // Substitute string subst = iter->second; if (subst == "") { // Normally `` is removed later, but with no token after, we're otherwise // stuck, so remove proceeding `` if (out.size()>=2 && out.substr(out.size()-2) == "``") { out = out.substr(0, out.size()-2); } } else { out += subst; } } else { out += argName; } argName = ""; } if (!quote) { // Check for `` only after we've detected end-of-argname if (cp[0]=='`' && cp[1]=='`') { if (backslashesc) { // Don't put out the ``, we're forming an escape which will not expand further later } else { out += "``"; // `` must get removed later, as `FOO```BAR must pre-expand FOO and BAR // See also removal in empty substitutes above } cp++; continue; } else if (cp[0]=='`' && cp[1]=='"') { out += "`\""; // `" means to put out a " without enabling quote mode (sort of) // however we must expand any macro calls inside it first. // So keep it `", so we don't enter quote mode. cp++; continue; } else if (cp[0]=='`' && cp[1]=='\\' && cp[2]=='`' && cp[3]=='"') { out += "`\\`\""; // `\`" means to put out a backslash quote // Leave it literal until we parse the VP_STRIFY string cp+=3; continue; } else if (cp[0]=='`' && cp[1]=='\\') { out += '\\'; // `\ means to put out a backslash cp++; continue; } else if (cp[0]=='\\' && cp[1]=='\n') { // We kept the \\n when we lexed because we don't want whitespace // trimming to mis-drop the final \\n // At replacement time we need the standard newline. out += "\n"; // \\n newline cp++; continue; } } if (cp[0]=='\\' && cp[1]=='\"') { out += cp[0]; // \{any} Put out literal next character out += cp[1]; cp++; continue; } else if (cp[0]=='\\') { // Normally \{any} would put out literal next character // Instead we allow "`define A(nm) \nm" to expand, per proposed mantis1537 out += cp[0]; continue; } if (*cp=='"') quote=!quote; if (*cp) out += *cp; } } if (debug()>=5) cout<<"defineSubstOut '"<3 && 0==filename.compare(filename.length()-3, 3, ".gz")) { string cmd = "gunzip -c "+filename; if ((fp = popen(cmd.c_str(), "r")) == NULL) { return false; } fd = fileno(fp); } else { fd = open(filename.c_str(), O_RDONLY); if (fd<0) return false; } while (!eof) { ssize_t todo = INFILTER_IPC_BUFSIZ; errno = 0; ssize_t got = read(fd, buf, todo); if (got>0) { outl.push_back(string(buf, got)); } else if (errno == EINTR || errno == EAGAIN #ifdef EWOULDBLOCK || errno == EWOULDBLOCK #endif ) { } else { eof = true; break; } } if (fp) { pclose(fp); fp=NULL; } else close(fd); return true; } void VPreProcImp::openFile(string filename, VFileLine* filelinep) { // Open a new file, possibly overriding the current one which is active. // Read a list with the whole file. StrList wholefile; bool ok = readWholefile(filename, wholefile/*ref*/); if (!ok) { error("File not found: "+filename+"\n"); return; } if (!m_preprocp->isEof()) { // IE not the first file. // We allow the same include file twice, because occasionally it pops // up, with guards preventing a real recursion. if (m_lexp->m_streampStack.size()>VPreProc::INCLUDE_DEPTH_MAX) { error("Recursive inclusion of file: "+filename); return; } // There's already a file active. Push it to work on the new one. addLineComment(0); } // Create new stream structure m_lexp->scanNewFile(m_preprocp->fileline()->create(filename, 1)); addLineComment(1); // Enter // Filter all DOS CR's en-mass. This avoids bugs with lexing CRs in the wrong places. // This will also strip them from strings, but strings aren't supposed to be multi-line without a "\" for (StrList::iterator it=wholefile.begin(); it!=wholefile.end(); ++it) { // We don't end-loop at \0 as we allow and strip mid-string '\0's (for now). bool strip = false; const char* sp = it->data(); const char* ep = sp + it->length(); // Only process if needed, as saves extra string allocations for (const char* cp=sp; cplength()); for (const char* cp=sp; cpscanBytesBack(*it); // Reclaim memory; the push saved the string contents for us *it = ""; } } void VPreProcImp::insertUnreadbackAtBol(const string& text) { // Insert insuring we're at the beginning of line, for `line // We don't always add a leading newline, as it may result in extra unreadback(newlines). if (m_lineCmt == "") { m_lineCmtNl = true; } else if (m_lineCmt[m_lineCmt.length()-1]!='\n') { insertUnreadback("\n"); } insertUnreadback(text); } void VPreProcImp::addLineComment(int enter_exit_level) { if (m_preprocp->lineDirectives()) { insertUnreadbackAtBol(m_lexp->curFilelinep()->lineDirectiveStrg(enter_exit_level)); } } int VPreProcImp::getRawToken() { // Get a token from the file, whatever it may be. while (1) { next_tok: if (m_lineAdd) { m_lineAdd--; m_rawAtBol = true; yyourtext("\n",1); if (debug()>=5) debugToken(VP_WHITE, "LNA"); return (VP_WHITE); } if (m_lineCmt!="") { // We have some `line directive or other processed data to return to the user. static string rtncmt; // Keep the c string till next call rtncmt = m_lineCmt; if (m_lineCmtNl) { if (!m_rawAtBol) rtncmt = "\n"+rtncmt; m_lineCmtNl = false; } yyourtext(rtncmt.c_str(), rtncmt.length()); m_lineCmt = ""; if (yyourleng()) m_rawAtBol = (yyourtext()[yyourleng()-1]=='\n'); if (state()==ps_DEFVALUE) { VPreLex::s_currentLexp->appendDefValue(yyourtext(),yyourleng()); goto next_tok; } else { if (debug()>=5) debugToken(VP_TEXT, "LCM"); return (VP_TEXT); } } if (isEof()) return (VP_EOF); // Snarf next token from the file int tok = m_lexp->lex(); if (debug()>=5) debugToken(tok, "RAW"); // A EOF on an include, so we can print `line and detect mis-matched "s if (tok==VP_EOF) { goto next_tok; // find the EOF, after adding needed lines } if (yyourleng()) m_rawAtBol = (yyourtext()[yyourleng()-1]=='\n'); return tok; } } void VPreProcImp::debugToken(int tok, const char* cmtp) { if (debug()>=5) { string buf = string(yyourtext(), yyourleng()); string::size_type pos; while ((pos=buf.find("\n")) != string::npos) { buf.replace(pos, 1, "\\n"); } while ((pos=buf.find("\r")) != string::npos) { buf.replace(pos, 1, "\\r"); } fprintf(stderr, "%d: %s %s %s(%d) dr%d: <%d>%-10s: %s\n", m_lexp->m_tokFilelinep->lineno(), cmtp, m_off?"of":"on", procStateName(state()), (int)m_states.size(), (int)m_defRefs.size(), m_lexp->currentStartState(), tokenName(tok), buf.c_str()); } } // Sorry, we're not using bison/yacc. It doesn't handle returning white space // in the middle of parsing other tokens. int VPreProcImp::getStateToken(string& buf) { // Return the next state-determined token while (1) { next_tok: if (isEof()) { buf = string(yyourtext(), yyourleng()); return VP_EOF; } int tok = getRawToken(); // Most states emit white space and comments between tokens. (Unless collecting a string) if (tok==VP_WHITE && state() !=ps_STRIFY) { buf = string(yyourtext(), yyourleng()); return (tok); } if (tok==VP_BACKQUOTE && state() !=ps_STRIFY) { tok = VP_TEXT; } if (tok==VP_COMMENT) { if (!m_off) { if (m_lexp->m_keepComments == KEEPCMT_SUB || m_lexp->m_keepComments == KEEPCMT_EXP) { string rtn; rtn.assign(yyourtext(),yyourleng()); m_preprocp->comment(rtn); // Need to insure "foo/**/bar" becomes two tokens insertUnreadback(" "); } else if (m_lexp->m_keepComments) { buf = string(yyourtext(), yyourleng()); return (tok); } else { // Need to insure "foo/**/bar" becomes two tokens insertUnreadback(" "); } } // We're off or processed the comment specially. If there are newlines // in it, we also return the newlines as TEXT so that the linenumber // count is maintained for downstream tools for (size_t len=0; len<(size_t)yyourleng(); len++) { if (yyourtext()[len]=='\n') m_lineAdd++; } goto next_tok; } if (tok==VP_LINE) { addLineComment(m_lexp->m_enterExit); goto next_tok; } if (tok==VP_DEFREF_JOIN) { // Here's something fun and unspecified as yet: // The existance of non-existance of a base define changes `` expansion // `define QA_b zzz // `define Q1 `QA``_b // 1Q1 -> zzz // `define QA a // `Q1 -> a_b // Note parenthesis make this unambiguous // `define Q1 `QA()``_b // -> a_b // This may be a side effect of how `UNDEFINED remains as `UNDEFINED, // but it screws up our method here. So hardcode it. string name(yyourtext()+1,yyourleng()-1); if (m_preprocp->defExists(name)) { // JOIN(DEFREF) // Put back the `` and process the defref if (debug()>=5) cout<<"```: define "<=5) cout<<"TOKEN now DEFREF\n"; tok = VP_DEFREF; } else { // DEFREF(JOIN) if (debug()>=5) cout<<"```: define "< string doesn't include the ``, so can just grab next and continue string out(yyourtext(),yyourleng()); if (debug()>=5) cout<<"`` LHS:"<defExists(m_lastSym); if (debug()>=5) cout<<"Ifdef "<defExists(m_lastSym); if (debug()>=5) cout<<"Elsif "<=5) cout<<"Undef "<undef(m_lastSym); } statePop(); goto next_tok; } else if (state()==ps_DEFNAME_DEFINE) { // m_lastSym already set. stateChange(ps_DEFFORM); m_lexp->pushStateDefForm(); goto next_tok; } else fatalSrc("Bad case\n"); goto next_tok; } else if (tok==VP_TEXT) { // IE, something like comment between define and symbol if (!m_off) { buf = string(yyourtext(), yyourleng()); return tok; } else goto next_tok; } else if (tok==VP_DEFREF) { // IE, `ifdef `MACRO(x): Substitue and come back here when state pops. break; } else { error((string)"Expecting define name. Found: "+tokenName(tok)+"\n"); goto next_tok; } } case ps_DEFFORM: { if (tok==VP_DEFFORM) { m_formals = m_lexp->m_defValue; if (debug()>=5) cout<<"DefFormals='"<pushStateDefValue(); goto next_tok; } else if (tok==VP_TEXT) { // IE, something like comment in formals if (!m_off) { buf = string(yyourtext(), yyourleng()); return tok; } else goto next_tok; } else { error((string)"Expecting define formal arguments. Found: "+tokenName(tok)+"\n"); goto next_tok; } } case ps_DEFVALUE: { static string newlines; newlines = "\n"; // Always start with trailing return if (tok == VP_DEFVALUE) { if (debug()>=5) cout<<"DefValue='"<m_defValue) <<"' formals='"<m_defValue; // Remove returns // Not removing returns in values has two problems, // 1. we need to correct line numbers with `line after each substitution // 2. Substituting in " .... " with embedded returns requires \ escape. // This is very difficult in the presence of `", so we keep the \ before the newline. for (size_t i=0; i=5) cout<<"Define "<define(m_lastSym, value, formals); } } else { string msg = string("Bad define text, unexpected ")+tokenName(tok)+"\n"; fatalSrc(msg); } statePop(); // DEFVALUE is terminated by a return, but lex can't return both tokens. // Thus, we emit a return here. buf = newlines; return(VP_WHITE); } case ps_DEFPAREN: { if (tok==VP_TEXT && yyourleng()==1 && yyourtext()[0]=='(') { stateChange(ps_DEFARG); goto next_tok; } else { if (m_defRefs.empty()) fatalSrc("Shouldn't be in DEFPAREN w/o active defref"); VPreDefRef* refp = &(m_defRefs.top()); error((string)"Expecting ( to begin argument list for define reference `"+refp->name()+"\n"); statePop(); goto next_tok; } } case ps_DEFARG: { if (m_defRefs.empty()) fatalSrc("Shouldn't be in DEFARG w/o active defref"); VPreDefRef* refp = &(m_defRefs.top()); refp->nextarg(refp->nextarg()+m_lexp->m_defValue); m_lexp->m_defValue=""; if (debug()>=5) cout<<"defarg++ "<nextarg()<args().push_back(refp->nextarg()); stateChange(ps_DEFARG); m_lexp->pushStateDefArg(1); refp->nextarg(""); goto next_tok; } else if (tok==VP_DEFARG && yyourleng()==1 && yyourtext()[0]==')') { // Substitute in and prepare for next action // Similar code in non-parenthesized define (Search for END_OF_DEFARG) refp->args().push_back(refp->nextarg()); string out; if (!m_off) { out = defineSubst(refp); out = m_preprocp->defSubstitute(out); } m_defRefs.pop(); refp=NULL; if (m_defRefs.empty()) { statePop(); if (state() == ps_JOIN) { // Handle {left}```FOO(ARG) where `FOO(ARG) might be empty if (m_joinStack.empty()) fatalSrc("`` join stack empty, but in a ``"); string lhs = m_joinStack.top(); m_joinStack.pop(); out = lhs+out; if (debug()>=5) cout<<"``-end-defarg Out:"<m_parenLevel = 0; } else { // Finished a defref inside a upper defref // Can't subst now, or // `define a(ign) x,y // foo(`a(ign),`b) would break because a contains comma refp = &(m_defRefs.top()); // We popped, so new top refp->nextarg(refp->nextarg()+m_lexp->m_defValue+out); m_lexp->m_defValue=""; m_lexp->m_parenLevel = refp->parenLevel(); statePop(); // Will go to ps_DEFARG, as we're under another define } goto next_tok; } else if (tok==VP_DEFREF) { // Expand it, then state will come back here // Value of building argument is data before the lower defref // we'll append it when we push the argument. break; } else if (tok==VP_SYMBOL || tok==VP_STRING || tok==VP_TEXT || tok==VP_WHITE || tok==VP_PSL) { string rtn; rtn.assign(yyourtext(),yyourleng()); refp->nextarg(refp->nextarg()+rtn); goto next_tok; } else if (tok==VP_STRIFY) { // We must expand stringinfication, when done will return to this state statePush(ps_STRIFY); goto next_tok; } else { error((string)"Expecting ) or , to end argument list for define reference. Found: "+tokenName(tok)); statePop(); goto next_tok; } } case ps_INCNAME: { if (tok==VP_STRING) { statePop(); m_lastSym.assign(yyourtext(),yyourleng()); if (debug()>=5) cout<<"Include "<include(m_lastSym); goto next_tok; } else if (tok==VP_TEXT && yyourleng()==1 && yyourtext()[0]=='<') { // include stateChange(ps_INCNAME); // Still m_lexp->pushStateIncFilename(); goto next_tok; } else if (tok==VP_DEFREF || tok==VP_STRIFY) { // Expand it, then state will come back here break; } else { statePop(); error((string)"Expecting include filename. Found: "+tokenName(tok)+"\n"); goto next_tok; } } case ps_ERRORNAME: { if (tok==VP_STRING) { if (!m_off) { m_lastSym.assign(yyourtext(),yyourleng()); error(m_lastSym); } statePop(); goto next_tok; } else { error((string)"Expecting `error string. Found: "+tokenName(tok)+"\n"); statePop(); goto next_tok; } } case ps_JOIN: { if (tok==VP_SYMBOL || tok==VP_TEXT) { if (m_joinStack.empty()) fatalSrc("`` join stack empty, but in a ``"); string lhs = m_joinStack.top(); m_joinStack.pop(); if (debug()>=5) cout<<"`` LHS:"<=5) cout<<"`` RHS:"<=5) cout<<"`` Out:"<=5) cout<<"Else "<<(enable?" ON":" OFF")<=5) cout<<"Endif "<=5) cout<<"DefRef "< VPreProc::DEFINE_RECURSION_LEVEL_MAX) { error("Recursive `define substitution: `"+name); goto next_tok; } // Substitute string params = m_preprocp->defParams(name); if (params=="") { // Not found, return original string as-is m_defDepth = 0; if (debug()>=5) cout<<"Defref `"< not_defined"<defSubstitute(out); if (m_defRefs.empty()) { // Just output the substitution if (state() == ps_JOIN) { // Handle {left}```FOO where `FOO might be empty if (m_joinStack.empty()) fatalSrc("`` join stack empty, but in a ``"); string lhs = m_joinStack.top(); m_joinStack.pop(); out = lhs+out; if (debug()>=5) cout<<"``-end-defref Out:"<nextarg(refp->nextarg()+m_lexp->m_defValue+out); m_lexp->m_defValue=""; } goto next_tok; } else { // Found, with parameters if (debug()>=5) cout<<"Defref `"< parametrized"<m_parenLevel); m_defRefs.push(VPreDefRef(name, params)); statePush(ps_DEFPAREN); m_lexp->pushStateDefArg(0); goto next_tok; } fatalSrc("Bad case\n"); } case VP_ERROR: { statePush(ps_ERRORNAME); goto next_tok; } case VP_EOF: if (!m_ifdefStack.empty()) { error("`ifdef not terminated at EOF\n"); } buf = string(yyourtext(), yyourleng()); return tok; case VP_UNDEFINEALL: if (!m_off) { if (debug()>=5) cout<<"Undefineall "<undefineall(); } goto next_tok; case VP_STRIFY: // We must expand macros in the body of the stringification // Then, when done, form a final string to return // (it could be used as a include filename, for example, so need the string token) statePush(ps_STRIFY); goto next_tok; case VP_SYMBOL: case VP_STRING: case VP_PSL: case VP_TEXT: { m_defDepth = 0; if (!m_off) { buf = string(yyourtext(), yyourleng()); return tok; } else goto next_tok; } case VP_WHITE: // Handled at top of loop case VP_COMMENT: // Handled at top of loop case VP_DEFFORM: // Handled by state=ps_DEFFORM; case VP_DEFVALUE: // Handled by state=ps_DEFVALUE; default: fatalSrc((string)"Internal error: Unexpected token "+tokenName(tok)+"\n"); break; } buf = string(yyourtext(), yyourleng()); return tok; } } int VPreProcImp::getFinalToken(string& buf) { // Return the next user-visible token in the input stream. // Includes and such are handled here, and are never seen by the caller. if (!m_finAhead) { m_finAhead = true; m_finToken = getStateToken(m_finBuf); } int tok = m_finToken; buf = m_finBuf; if (0 && debug()>=5) { string bufcln = VPreLex::cleanDbgStrg(buf); fprintf(stderr,"%d: FIN: %-10s: %s\n", m_lexp->m_tokFilelinep->lineno(), tokenName(tok), bufcln.c_str()); } // Track `line const char* bufp = buf.c_str(); while (*bufp == '\n') bufp++; if ((tok == VP_TEXT || tok == VP_LINE) && 0==strncmp(bufp,"`line ",6)) { int enter; m_finFilelinep = m_finFilelinep->lineDirective(bufp, enter/*ref*/); } else { if (m_finAtBol && !(tok==VP_TEXT && buf=="\n") && m_preprocp->lineDirectives()) { if (int outBehind = m_lexp->m_tokFilelinep->lineno() - m_finFilelinep->lineno()) { if (debug()>=5) fprintf(stderr,"%d: FIN: readjust, fin at %d request at %d\n", m_lexp->m_tokFilelinep->lineno(), m_finFilelinep->lineno(), m_lexp->m_tokFilelinep->lineno()); m_finFilelinep = m_finFilelinep->create(m_lexp->m_tokFilelinep->filename(),m_lexp->m_tokFilelinep->lineno()); if (outBehind > 0 && outBehind <= (int)VPreProc::NEWLINES_VS_TICKLINE) { // Output stream is behind, send newlines to get back in sync // (Most likely because we're completing a disabled `endif) if (m_preprocp->keepWhitespace()) { buf = string(outBehind,'\n'); return VP_TEXT; } } else { // Need to backup, use `line buf = m_finFilelinep->lineDirectiveStrg(0); return VP_LINE; } } } // Track newlines in prep for next token for (string::iterator cp=buf.begin(); cp!=buf.end(); ++cp) { if (*cp == '\n') { m_finAtBol = true; m_finFilelinep->linenoIncInPlace(); // Increment in place to avoid new/delete calls. It's private data. } else { m_finAtBol = false; } } } m_finAhead = false; // Consumed the token return tok; } string VPreProcImp::getparseline(bool stop_at_eol, size_t approx_chunk) { // Get a single line from the parse stream. Buffer unreturned text until the newline. if (isEof()) return ""; while (1) { const char* rtnp = NULL; bool gotEof = false; while ((stop_at_eol ? (NULL==(rtnp=strchr(m_lineChars.c_str(),'\n'))) : (approx_chunk==0 || (m_lineChars.length() < approx_chunk))) && !gotEof) { string buf; int tok = getFinalToken(buf/*ref*/); if (debug()>=5) { string bufcln = VPreLex::cleanDbgStrg(buf); fprintf(stderr,"%d: GETFETC: %-10s: %s\n", m_lexp->m_tokFilelinep->lineno(), tokenName(tok), bufcln.c_str()); } if (tok==VP_EOF) { // Add a final newline, if the user forgot the final \n. if (m_lineChars != "" && m_lineChars[m_lineChars.length()-1] != '\n') { m_lineChars.append("\n"); } gotEof = true; } else if (tok==VP_PSL) { m_lineChars.append(" psl "); } else { m_lineChars.append(buf); } } // Make new string with data up to the newline. size_t len = stop_at_eol ? (rtnp-m_lineChars.c_str()+1) : m_lineChars.length(); string theLine(m_lineChars, 0, len); m_lineChars = m_lineChars.erase(0,len); // Remove returned characters if (!m_preprocp->keepWhitespace() && !gotEof) { const char* cp=theLine.c_str(); for (; *cp && (isspace(*cp) || *cp=='\n'); cp++) {} if (!*cp) continue; } if (debug()>=4) { string lncln = VPreLex::cleanDbgStrg(theLine); fprintf(stderr,"%d: GETLINE: %s\n", m_lexp->m_tokFilelinep->lineno(), lncln.c_str()); } return theLine; } } Verilog-Perl-3.482/Preproc/flexfix0000755000177100017500000000342714553624300017031 0ustar wsnyderwsnyder#!/usr/bin/perl -w ###################################################################### # # Copyright 2002-2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # ###################################################################### # DESCRIPTION: Edits flex output to get around various broken flex issues. my $Opt_Prefix = $ARGV[0] or die "%Error: No prefix specified,"; foreach my $line () { # Fix flex 2.6.0 warning $line =~ s/ number_to_move == YY_MORE_ADJ / (int)number_to_move == (int)YY_MORE_ADJ /; # Fix flex 2.5.4 namespace omission $line =~ s/^class istream;/\#include \nusing namespace std;\n/; # Fix flex 2.5.31 redefinition $line =~ s!(\#define\s+yyFlexLexer\s+yyFlexLexer)!//flexfix: $1!g; # Fix flex 2.5.1 yytext_ptr undef $line =~ s!(\#undef\s+yytext_ptr)!//flexfix: $1!g; # Fix flex 2.5.4 and GCC 4.1.0 warn_unused_result $line =~ s!\(void\) *fwrite\((.*)\)!if (fwrite($1)) {}!g; # Fix flex 2.5.33 and GCC 4.1.2 "warning: comparison between signed and unsigned integer expressions" in YY_INPUT $line =~ s!for \( n = 0; n < max_size && !for ( n = 0; ((size_t)n < (size_t)max_size) && !g; # Fix flex 2.5.4 and GCC 4.0.2 under FLEX_DEBUG $line =~ s!--accepting rule at line %d !--accepting rule at line %ld !g; # Fix compiler warning filenames $line =~ s!(#line \d+ ".*)_pretmp!$1!; print "$line"; } Verilog-Perl-3.482/Preproc/.gitignore0000644000177100017500000000015213234726611017421 0ustar wsnyderwsnyderblib gen Makefile pm_to_blib VPreLex*.cpp *.def *.dll *.exp *.o *.c *.bs *.xsc *.output *.old *_cleaned.* Verilog-Perl-3.482/Preproc/VPreLex.h0000644000177100017500000001740714553624300017137 0ustar wsnyderwsnyder// -*- C++ -*- //************************************************************************* // // Copyright 2000-2024 by Wilson Snyder. This program is free software; // you can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. // // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // //************************************************************************* /// \file /// \brief Verilog::Preproc: Internal header for lex interfacing /// /// Authors: Wilson Snyder /// /// Code available from: https://www.veripool.org/verilog-perl /// /// This header provides the interface between the lex proper VPreLex.l/.cpp /// and the class implementation file VPreProc.cpp /// It is not intended for user applications. /// //************************************************************************* #ifndef _VPREPROCLEX_H_ // Guard #define _VPREPROCLEX_H_ 1 #include #include #include "VFileLine.h" class VPreLex; class VPreProcImp; //====================================================================== // Token codes // If changing, see VPreProc.cpp's VPreProcImp::tokenName() #define VP_EOF 0 #define VP_INCLUDE 256 #define VP_IFDEF 257 #define VP_IFNDEF 258 #define VP_ENDIF 259 #define VP_UNDEF 260 #define VP_DEFINE 261 #define VP_ELSE 262 #define VP_ELSIF 263 #define VP_LINE 264 #define VP_UNDEFINEALL 265 #define VP_SYMBOL 300 #define VP_STRING 301 #define VP_DEFVALUE 302 #define VP_COMMENT 303 #define VP_TEXT 304 #define VP_WHITE 305 #define VP_DEFREF 306 #define VP_DEFARG 307 #define VP_ERROR 308 #define VP_DEFFORM 309 #define VP_STRIFY 310 #define VP_BACKQUOTE 311 #define VP_SYMBOL_JOIN 312 #define VP_DEFREF_JOIN 313 #define VP_JOIN 314 #define VP_PSL 350 //====================================================================== // Externs created by flex // We add a prefix so that other lexers/flexers in the same program won't collide. #ifndef yy_create_buffer # define yy_create_buffer VPreLex_create_buffer # define yy_delete_buffer VPreLex_delete_buffer # define yy_scan_buffer VPreLex_scan_buffer # define yy_scan_string VPreLex_scan_string # define yy_scan_bytes VPreLex_scan_bytes # define yy_flex_debug VPreLex_flex_debug # define yy_init_buffer VPreLex_init_buffer # define yy_flush_buffer VPreLex_flush_buffer # define yy_load_buffer_state VPreLex_load_buffer_state # define yy_switch_to_buffer VPreLex_switch_to_buffer # define yyin VPreLexin # define yyleng VPreLexleng # define yylex VPreLexlex # define yyout VPreLexout # define yyrestart VPreLexrestart # define yytext VPreLextext #endif #ifndef yyourleng # define yyourleng VPreLexourleng # define yyourtext VPreLexourtext #endif #ifndef YY_BUFFER_STATE struct yy_buffer_state; typedef struct yy_buffer_state *YY_BUFFER_STATE; # define YY_BUF_SIZE 16384 #endif extern int yylex(); extern void yyrestart(FILE*); // Accessors, because flex keeps changing the type of yyleng extern char* yyourtext(); extern size_t yyourleng(); extern void yyourtext(const char* textp, size_t size); // Must call with static YY_BUFFER_STATE yy_create_buffer(FILE *file, int size); void yy_switch_to_buffer(YY_BUFFER_STATE new_buffer); void yy_delete_buffer(YY_BUFFER_STATE b); //====================================================================== #define KEEPCMT_SUB 2 #define KEEPCMT_EXP 3 //====================================================================== // Entry for each file processed; a stack of entries included class VPreStream { public: VFileLine* m_curFilelinep; // Current processing point (see also m_tokFilelinep) VPreLex* m_lexp; // Lexer, for resource tracking deque m_buffers; // Buffer of characters to process int m_ignNewlines; // Ignore multiline newlines bool m_eof; // "EOF" buffer bool m_file; // Buffer is start of new file int m_termState; // Termination fsm VPreStream(VFileLine* fl, VPreLex* lexp) : m_curFilelinep(fl), m_lexp(lexp), m_ignNewlines(0), m_eof(false), m_file(false), m_termState(0) { lexStreamDepthAdd(1); } ~VPreStream() { lexStreamDepthAdd(-1); } private: void lexStreamDepthAdd(int delta); }; //====================================================================== // Class entry for each per-lexer state class VPreLex { public: // Used only by VPreLex.cpp and VPreProc.cpp VPreProcImp* m_preimpp; // Preprocessor lexor belongs to stack m_streampStack; // Stack of processing files int m_streamDepth; // Depth of stream processing YY_BUFFER_STATE m_bufferState; // Flex state VFileLine* m_tokFilelinep; // Starting position of current token // State to lexer static VPreLex* s_currentLexp; ///< Current lexing point int m_keepComments; ///< Emit comments in output text int m_keepWhitespace; ///< Emit all whitespace in output text bool m_pedantic; ///< Obey standard; don't Substitute `error bool m_synthesis; ///< Remove translate_offs // State from lexer int m_formalLevel; ///< Parenthesis counting inside def formals int m_parenLevel; ///< Parenthesis counting inside def args bool m_defCmtSlash; ///< /*...*/ comment in define had \ ending bool m_defQuote; ///< Definition value inside quote string m_defValue; ///< Definition value being built. int m_enterExit; ///< For VL_LINE, the enter/exit level // CONSTRUCTORS VPreLex(VPreProcImp* preimpp, VFileLine* filelinep) { m_preimpp = preimpp; m_streamDepth = 0; m_keepComments = 0; m_keepWhitespace = 1; m_pedantic = false; m_synthesis = false; m_formalLevel = 0; m_parenLevel = 0; m_defQuote = false; m_defCmtSlash = false; m_tokFilelinep = filelinep; m_enterExit = 0; initFirstBuffer(filelinep); } ~VPreLex() { while (!m_streampStack.empty()) { delete m_streampStack.top(); m_streampStack.pop(); } yy_delete_buffer(m_bufferState); m_bufferState=NULL; } /// Called by VPreLex.l from lexer VPreStream* curStreamp() { return m_streampStack.top(); } // Can't be empty, "EOF" is on top VFileLine* curFilelinep() { return curStreamp()->m_curFilelinep; } void curFilelinep(VFileLine* fl) { curStreamp()->m_curFilelinep = fl; } void appendDefValue(const char* textp, size_t len) { m_defValue.append(textp,len); } void lineDirective(const char* textp) { curFilelinep(curFilelinep()->lineDirective(textp, m_enterExit/*ref*/)); } void linenoInc() { if (curStreamp()->m_ignNewlines) curStreamp()->m_ignNewlines--; else curFilelinep(curFilelinep()->create(curFilelinep()->lineno()+1)); } /// Called by VPreProc.cpp to inform lexer void pushStateDefArg(int level); void pushStateDefForm(); void pushStateDefValue(); void pushStateIncFilename(); void scanNewFile(VFileLine* filelinep); void scanBytes(const string& str); void scanBytesBack(const string& str); size_t inputToLex(char* buf, size_t max_size); /// Called by VPreProc.cpp to get data from lexer YY_BUFFER_STATE currentBuffer(); int lex(); int currentStartState(); void dumpSummary(); void dumpStack(); void unused(); // Called by VPreStream void streamDepthAdd(int delta) { m_streamDepth += delta; } int streamDepth() const { return m_streamDepth; } /// Utility static int debug(); static void debug(int level); static string cleanDbgStrg(const string& in); private: string currentUnreadChars(); string endOfStream(bool& againr); void initFirstBuffer(VFileLine* filelinep); void scanSwitchStream(VPreStream* streamp); }; inline void VPreStream::lexStreamDepthAdd(int delta) { m_lexp->streamDepthAdd(delta); } #endif // Guard Verilog-Perl-3.482/Preproc/Makefile.PL0000644000177100017500000000745414553624300017414 0ustar wsnyderwsnyder# DESCRIPTION: Perl ExtUtils: Type 'perl Makefile.PL' to create a Makefile for this package # # Copyright 2000-2024 by Wilson Snyder. This program is free software; # you can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. use ExtUtils::MakeMaker; use Config; sub MY::postamble { my $out; #print Config::myconfig(); if ($Config{osname} !~ /cygwin/i && $Config{archname} !~ /cygwin/i && $Config{osname} !~ /darwin/i && $Config{archname} !~ /darwin/i) { # Cygwin: Don't change LD, it breaks # Sun: Requires g++ LD # Linux: Either way $out .= "LD = g++\n"; } # Note OPTIMIZE is passed from upper makefile, so this code needed there too. my $optimize = $Config{optimize}; $optimize =~ s/(^| )-O2( |$)/\1-O\2/g; # pass hardening flags $optimize .= " $ENV{CFLAGS} $ENV{CPPFLAGS}"; $out .= "OPTIMIZE = $optimize\n"; if ($Config{osname} =~ /cygwin/i || $Config{archname} =~ /cygwin/i) { # Cygwin ExtUtils::MakeMaker ignores our LIBS declaration and says # "No library found for -lstdc++". Force it. $out .= "LDLOADLIBS += -lstdc++\n"; # Cygwin: High optimization causes g++ "out of memory" $out .= "OPTIMIZE += -O\n"; } if ($Config{osname} =~ /darwin/i || $Config{archname} =~ /darwin/i) { # MakeMaker wants to create bundles on MacOSX rather than dylibs. We override DLEXT and LDDLFLAGS generated by MakeMaker in this case $out .= "DLEXT = dylib\n"; if ($^V eq '5.12.4') { $out .= sprintf("LDDLFLAGS = -dynamiclib -lstdc++ -L/System/Library/Perl/5.12/%s/CORE -lperl -L/usr/local/lib\n",$Config{archname}); } elsif ($^V eq '5.18.2') { $out .= sprintf("LDDLFLAGS = -dynamiclib -lstdc++ -L/System/Library/Perl/5.18/%s/CORE -lperl -L/usr/local/lib\n",$Config{archname}); } elsif ($^V < 'v5.26.3') { $out .= sprintf("LDDLFLAGS = -dynamiclib -lstdc++ -L/System/Library/Perl/%vd/%s/CORE -lperl -lgcc_eh -L/usr/local/lib\n",$^V,$Config{archname}); } } $out .= "CCFLAGS += -Wall -Wno-unused -Wno-sign-compare -Werror\n" if $ENV{VERILATOR_AUTHOR_SITE}; #$out .= "CCFLAGS += -O0 -ggdb\n" if $ENV{VERILATOR_AUTHOR_SITE}; print "%Warning: -O0 --gdb on, also FLEX -d on"; $out .= "CCFLAGS += $ENV{VERILOGPERL_CCFLAGS}\n" if defined $ENV{VERILOGPERL_CCFLAGS}; $out .= "OPTIMIZE += -Wno-unused\n" if $ENV{VERILATOR_AUTHOR_SITE}; # Makefile has another -Wall $out .= "OPTIMIZE += $ENV{VERILOGPERL_CCFLAGS}\n" if defined $ENV{VERILOGPERL_CCFLAGS}; $out .= "CCFLAGS += -I\$(PPSRC)\n"; my $cmt = $ENV{VERILOGPERL_FLEX_DEBUG} ? "" : "#"; $out .= "${cmt}CFLAGS += -DFLEX_DEBUG\n"; $out .= "${cmt}LEXFLAGS += -d\n"; $out .= ' CC = $(OBJCACHE) g++ LEX = flex YACC = bison PPSRC = ../Preproc FLEXFIX = $(PPSRC)/flexfix TOOLHASH = $(PPSRC)/toolhash XSUBPPFIX = $(PPSRC)/xsubppfix VPATH += . $(PPSRC) VPreLex.o: VPreLex.h VPreProc.h VFileLine.h VPreProc.o: VPreLex.h VPreProc.h VFileLine.h VFileLine.o: VFileLine.h VPreLex_pretmp.cpp: VPreLex.l -$(LEX) --version $(PERL) $(TOOLHASH) --verbose --in $< --out $@ --cmd $(LEX) $(LEXFLAGS) -o$@ $< VPreLex.cpp: $(FLEXFIX) VPreLex_pretmp.cpp $(PERL) $(FLEXFIX) VPreLex < VPreLex_pretmp.cpp > $@ Preproc_cleaned.cpp: Preproc.c $(PERL) $(XSUBPPFIX) < Preproc.c > Preproc_cleaned.cpp clean:: -$(RM_RF) test *.d *.o *.output -$(RM_RF) VPreLex*.cpp Preproc_cleaned.* -$(RM_RF) VPreprocLex* '; return $out; } # Grr; some flags cause warnings in g++ (my $ccflags = $Config{ccflags}) =~ s/ *-Wdeclaration-after-statement//; WriteMakefile( NAME => "Verilog::Preproc", LIBS => '-lstdc++', VERSION_FROM => 'Preproc.pm', XSOPT => '-C++', CCFLAGS => $ccflags, OBJECT => 'VFileLine.o VPreProc.o VPreLex.o', MYEXTLIB => 'Preproc_cleaned.o', ); Verilog-Perl-3.482/Preproc/VFileLine.cpp0000644000177100017500000000653014553624300017755 0ustar wsnyderwsnyder// -*- C++ -*- //************************************************************************* // // Copyright 2000-2024 by Wilson Snyder. This program is free software; // you can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. // // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // //************************************************************************* /// \file /// \brief Verilog::Preproc: Error handling implementation /// /// Authors: Wilson Snyder /// /// Code available from: https://www.veripool.org/verilog-perl /// //************************************************************************* #include #include #include "VFileLine.h" int VFileLine::s_numErrors = 0; ///< Number of errors detected //============================================================================ void VFileLine::init(const string& filename, int lineno) { m_filename = filename; m_lineno = lineno; } const string VFileLine::filebasename() const { string name = filename(); string::size_type slash; if ((slash = name.rfind("/")) != string::npos) { name.erase(0,slash+1); } return name; } void VFileLine::fatal(const string& msg) { error(msg); error("Fatal Error detected"); abort(); } void VFileLine::error(const string& msg) { VFileLine::s_numErrors++; if (msg[msg.length()-1] != '\n') { fprintf(stderr, "%%Error: %s", msg.c_str()); } else { fprintf(stderr, "%%Error: %s\n", msg.c_str()); // Append newline, as user omitted it. } } const char* VFileLine::itoa(int i) { static char buf[100]; sprintf(buf,"%d",i); return buf; } string VFileLine::lineDirectiveStrg(int enterExit) const { char numbuf[20]; sprintf(numbuf, "%d", lineno()); char levelbuf[20]; sprintf(levelbuf, "%d", enterExit); return ((string)"`line "+numbuf+" \""+filename()+"\" "+levelbuf+"\n"); } VFileLine* VFileLine::lineDirective(const char* textp, int& enterExitRef) { // Handle `line directive // Skip `line while (*textp && isspace(*textp)) textp++; while (*textp && !isspace(*textp)) textp++; while (*textp && (isspace(*textp) || *textp=='"')) textp++; // Grab linenumber int lineno = this->lineno(); const char *ln = textp; while (*textp && !isspace(*textp)) textp++; if (isdigit(*ln)) { lineno = atoi(ln); } while (*textp && (isspace(*textp) || *textp=='"')) textp++; // Grab filename string filename = this->filename(); const char* fn = textp; while (*textp && !(isspace(*textp) || *textp=='"')) textp++; if (textp != fn) { string strfn = fn; strfn = strfn.substr(0, textp-fn); filename = strfn; } // Grab level while (*textp && (isspace(*textp) || *textp=='"')) textp++; if (isdigit(*textp)) enterExitRef = atoi(textp); else enterExitRef = 0; return create(filename,lineno); } //====================================================================== // Global scope ostream& operator<<(ostream& os, VFileLine* flp) { if (flp->filename()!="") { os <filename()<<":"<lineno()<<": "< 0 #define FLEX_BETA #endif #ifdef yy_create_buffer #define VPreLex_create_buffer_ALREADY_DEFINED #else #define yy_create_buffer VPreLex_create_buffer #endif #ifdef yy_delete_buffer #define VPreLex_delete_buffer_ALREADY_DEFINED #else #define yy_delete_buffer VPreLex_delete_buffer #endif #ifdef yy_scan_buffer #define VPreLex_scan_buffer_ALREADY_DEFINED #else #define yy_scan_buffer VPreLex_scan_buffer #endif #ifdef yy_scan_string #define VPreLex_scan_string_ALREADY_DEFINED #else #define yy_scan_string VPreLex_scan_string #endif #ifdef yy_scan_bytes #define VPreLex_scan_bytes_ALREADY_DEFINED #else #define yy_scan_bytes VPreLex_scan_bytes #endif #ifdef yy_init_buffer #define VPreLex_init_buffer_ALREADY_DEFINED #else #define yy_init_buffer VPreLex_init_buffer #endif #ifdef yy_flush_buffer #define VPreLex_flush_buffer_ALREADY_DEFINED #else #define yy_flush_buffer VPreLex_flush_buffer #endif #ifdef yy_load_buffer_state #define VPreLex_load_buffer_state_ALREADY_DEFINED #else #define yy_load_buffer_state VPreLex_load_buffer_state #endif #ifdef yy_switch_to_buffer #define VPreLex_switch_to_buffer_ALREADY_DEFINED #else #define yy_switch_to_buffer VPreLex_switch_to_buffer #endif #ifdef yypush_buffer_state #define VPreLexpush_buffer_state_ALREADY_DEFINED #else #define yypush_buffer_state VPreLexpush_buffer_state #endif #ifdef yypop_buffer_state #define VPreLexpop_buffer_state_ALREADY_DEFINED #else #define yypop_buffer_state VPreLexpop_buffer_state #endif #ifdef yyensure_buffer_stack #define VPreLexensure_buffer_stack_ALREADY_DEFINED #else #define yyensure_buffer_stack VPreLexensure_buffer_stack #endif #ifdef yylex #define VPreLexlex_ALREADY_DEFINED #else #define yylex VPreLexlex #endif #ifdef yyrestart #define VPreLexrestart_ALREADY_DEFINED #else #define yyrestart VPreLexrestart #endif #ifdef yylex_init #define VPreLexlex_init_ALREADY_DEFINED #else #define yylex_init VPreLexlex_init #endif #ifdef yylex_init_extra #define VPreLexlex_init_extra_ALREADY_DEFINED #else #define yylex_init_extra VPreLexlex_init_extra #endif #ifdef yylex_destroy #define VPreLexlex_destroy_ALREADY_DEFINED #else #define yylex_destroy VPreLexlex_destroy #endif #ifdef yyget_debug #define VPreLexget_debug_ALREADY_DEFINED #else #define yyget_debug VPreLexget_debug #endif #ifdef yyset_debug #define VPreLexset_debug_ALREADY_DEFINED #else #define yyset_debug VPreLexset_debug #endif #ifdef yyget_extra #define VPreLexget_extra_ALREADY_DEFINED #else #define yyget_extra VPreLexget_extra #endif #ifdef yyset_extra #define VPreLexset_extra_ALREADY_DEFINED #else #define yyset_extra VPreLexset_extra #endif #ifdef yyget_in #define VPreLexget_in_ALREADY_DEFINED #else #define yyget_in VPreLexget_in #endif #ifdef yyset_in #define VPreLexset_in_ALREADY_DEFINED #else #define yyset_in VPreLexset_in #endif #ifdef yyget_out #define VPreLexget_out_ALREADY_DEFINED #else #define yyget_out VPreLexget_out #endif #ifdef yyset_out #define VPreLexset_out_ALREADY_DEFINED #else #define yyset_out VPreLexset_out #endif #ifdef yyget_leng #define VPreLexget_leng_ALREADY_DEFINED #else #define yyget_leng VPreLexget_leng #endif #ifdef yyget_text #define VPreLexget_text_ALREADY_DEFINED #else #define yyget_text VPreLexget_text #endif #ifdef yyget_lineno #define VPreLexget_lineno_ALREADY_DEFINED #else #define yyget_lineno VPreLexget_lineno #endif #ifdef yyset_lineno #define VPreLexset_lineno_ALREADY_DEFINED #else #define yyset_lineno VPreLexset_lineno #endif #ifdef yywrap #define VPreLexwrap_ALREADY_DEFINED #else #define yywrap VPreLexwrap #endif #ifdef yyalloc #define VPreLexalloc_ALREADY_DEFINED #else #define yyalloc VPreLexalloc #endif #ifdef yyrealloc #define VPreLexrealloc_ALREADY_DEFINED #else #define yyrealloc VPreLexrealloc #endif #ifdef yyfree #define VPreLexfree_ALREADY_DEFINED #else #define yyfree VPreLexfree #endif #ifdef yytext #define VPreLextext_ALREADY_DEFINED #else #define yytext VPreLextext #endif #ifdef yyleng #define VPreLexleng_ALREADY_DEFINED #else #define yyleng VPreLexleng #endif #ifdef yyin #define VPreLexin_ALREADY_DEFINED #else #define yyin VPreLexin #endif #ifdef yyout #define VPreLexout_ALREADY_DEFINED #else #define yyout VPreLexout #endif #ifdef yy_flex_debug #define VPreLex_flex_debug_ALREADY_DEFINED #else #define yy_flex_debug VPreLex_flex_debug #endif #ifdef yylineno #define VPreLexlineno_ALREADY_DEFINED #else #define yylineno VPreLexlineno #endif /* First, we deal with platform-specific or compiler-specific issues. */ /* begin standard C headers. */ #include #include #include #include /* end standard C headers. */ /* flex integer type definitions */ #ifndef FLEXINT_H #define FLEXINT_H /* C99 systems have . Non-C99 systems may or may not. */ #if defined (__STDC_VERSION__) && __STDC_VERSION__ >= 199901L /* C99 says to define __STDC_LIMIT_MACROS before including stdint.h, * if you want the limit (max/min) macros for int types. */ #ifndef __STDC_LIMIT_MACROS #define __STDC_LIMIT_MACROS 1 #endif #include typedef int8_t flex_int8_t; typedef uint8_t flex_uint8_t; typedef int16_t flex_int16_t; typedef uint16_t flex_uint16_t; typedef int32_t flex_int32_t; typedef uint32_t flex_uint32_t; #else typedef signed char flex_int8_t; typedef short int flex_int16_t; typedef int flex_int32_t; typedef unsigned char flex_uint8_t; typedef unsigned short int flex_uint16_t; typedef unsigned int flex_uint32_t; /* Limits of integral types. */ #ifndef INT8_MIN #define INT8_MIN (-128) #endif #ifndef INT16_MIN #define INT16_MIN (-32767-1) #endif #ifndef INT32_MIN #define INT32_MIN (-2147483647-1) #endif #ifndef INT8_MAX #define INT8_MAX (127) #endif #ifndef INT16_MAX #define INT16_MAX (32767) #endif #ifndef INT32_MAX #define INT32_MAX (2147483647) #endif #ifndef UINT8_MAX #define UINT8_MAX (255U) #endif #ifndef UINT16_MAX #define UINT16_MAX (65535U) #endif #ifndef UINT32_MAX #define UINT32_MAX (4294967295U) #endif #ifndef SIZE_MAX #define SIZE_MAX (~(size_t)0) #endif #endif /* ! C99 */ #endif /* ! FLEXINT_H */ /* begin standard C++ headers. */ /* TODO: this is always defined, so inline it */ #define yyconst const #if defined(__GNUC__) && __GNUC__ >= 3 #define yynoreturn __attribute__((__noreturn__)) #else #define yynoreturn #endif /* Returned upon end-of-file. */ #define YY_NULL 0 /* Promotes a possibly negative, possibly signed char to an * integer in range [0..255] for use as an array index. */ #define YY_SC_TO_UI(c) ((YY_CHAR) (c)) /* Enter a start condition. This macro really ought to take a parameter, * but we do it the disgusting crufty way forced on us by the ()-less * definition of BEGIN. */ #define BEGIN (yy_start) = 1 + 2 * /* Translate the current start state into a value that can be later handed * to BEGIN to return to the state. The YYSTATE alias is for lex * compatibility. */ #define YY_START (((yy_start) - 1) / 2) #define YYSTATE YY_START /* Action number for EOF rule of a given start state. */ #define YY_STATE_EOF(state) (YY_END_OF_BUFFER + state + 1) /* Special action meaning "start processing a new file". */ #define YY_NEW_FILE yyrestart( yyin ) #define YY_END_OF_BUFFER_CHAR 0 /* Size of default input buffer. */ #ifndef YY_BUF_SIZE #ifdef __ia64__ /* On IA-64, the buffer size is 16k, not 8k. * Moreover, YY_BUF_SIZE is 2*YY_READ_BUF_SIZE in the general case. * Ditto for the __ia64__ case accordingly. */ #define YY_BUF_SIZE 32768 #else #define YY_BUF_SIZE 16384 #endif /* __ia64__ */ #endif /* The state buf must be large enough to hold one state per character in the main buffer. */ #define YY_STATE_BUF_SIZE ((YY_BUF_SIZE + 2) * sizeof(yy_state_type)) #ifndef YY_TYPEDEF_YY_BUFFER_STATE #define YY_TYPEDEF_YY_BUFFER_STATE typedef struct yy_buffer_state *YY_BUFFER_STATE; #endif #ifndef YY_TYPEDEF_YY_SIZE_T #define YY_TYPEDEF_YY_SIZE_T typedef size_t yy_size_t; #endif extern int yyleng; extern FILE *yyin, *yyout; #define EOB_ACT_CONTINUE_SCAN 0 #define EOB_ACT_END_OF_FILE 1 #define EOB_ACT_LAST_MATCH 2 #define YY_LESS_LINENO(n) #define YY_LINENO_REWIND_TO(ptr) /* Return all but the first "n" matched characters back to the input stream. */ #define yyless(n) \ do \ { \ /* Undo effects of setting up yytext. */ \ int yyless_macro_arg = (n); \ YY_LESS_LINENO(yyless_macro_arg);\ *yy_cp = (yy_hold_char); \ YY_RESTORE_YY_MORE_OFFSET \ (yy_c_buf_p) = yy_cp = yy_bp + yyless_macro_arg - YY_MORE_ADJ; \ YY_DO_BEFORE_ACTION; /* set up yytext again */ \ } \ while ( 0 ) #define unput(c) yyunput( c, (yytext_ptr) ) #ifndef YY_STRUCT_YY_BUFFER_STATE #define YY_STRUCT_YY_BUFFER_STATE struct yy_buffer_state { FILE *yy_input_file; char *yy_ch_buf; /* input buffer */ char *yy_buf_pos; /* current position in input buffer */ /* Size of input buffer in bytes, not including room for EOB * characters. */ int yy_buf_size; /* Number of characters read into yy_ch_buf, not including EOB * characters. */ int yy_n_chars; /* Whether we "own" the buffer - i.e., we know we created it, * and can realloc() it to grow it, and should free() it to * delete it. */ int yy_is_our_buffer; /* Whether this is an "interactive" input source; if so, and * if we're using stdio for input, then we want to use getc() * instead of fread(), to make sure we stop fetching input after * each newline. */ int yy_is_interactive; /* Whether we're considered to be at the beginning of a line. * If so, '^' rules will be active on the next match, otherwise * not. */ int yy_at_bol; int yy_bs_lineno; /**< The line count. */ int yy_bs_column; /**< The column count. */ /* Whether to try to fill the input buffer when we reach the * end of it. */ int yy_fill_buffer; int yy_buffer_status; #define YY_BUFFER_NEW 0 #define YY_BUFFER_NORMAL 1 /* When an EOF's been seen but there's still some text to process * then we mark the buffer as YY_EOF_PENDING, to indicate that we * shouldn't try reading from the input source any more. We might * still have a bunch of tokens to match, though, because of * possible backing-up. * * When we actually see the EOF, we change the status to "new" * (via yyrestart()), so that the user can continue scanning by * just pointing yyin at a new input file. */ #define YY_BUFFER_EOF_PENDING 2 }; #endif /* !YY_STRUCT_YY_BUFFER_STATE */ /* Stack of input buffers. */ static size_t yy_buffer_stack_top = 0; /**< index of top of stack. */ static size_t yy_buffer_stack_max = 0; /**< capacity of stack. */ static YY_BUFFER_STATE * yy_buffer_stack = NULL; /**< Stack as an array. */ /* We provide macros for accessing buffer states in case in the * future we want to put the buffer states in a more general * "scanner state". * * Returns the top of the stack, or NULL. */ #define YY_CURRENT_BUFFER ( (yy_buffer_stack) \ ? (yy_buffer_stack)[(yy_buffer_stack_top)] \ : NULL) /* Same as previous macro, but useful when we know that the buffer stack is not * NULL or when we need an lvalue. For internal use only. */ #define YY_CURRENT_BUFFER_LVALUE (yy_buffer_stack)[(yy_buffer_stack_top)] /* yy_hold_char holds the character lost when yytext is formed. */ static char yy_hold_char; static int yy_n_chars; /* number of characters read into yy_ch_buf */ int yyleng; /* Points to current character in buffer. */ static char *yy_c_buf_p = NULL; static int yy_init = 0; /* whether we need to initialize */ static int yy_start = 0; /* start state number */ /* Flag which is used to allow yywrap()'s to do buffer switches * instead of setting up a fresh yyin. A bit of a hack ... */ static int yy_did_buffer_switch_on_eof; void yyrestart ( FILE *input_file ); void yy_switch_to_buffer ( YY_BUFFER_STATE new_buffer ); YY_BUFFER_STATE yy_create_buffer ( FILE *file, int size ); void yy_delete_buffer ( YY_BUFFER_STATE b ); void yy_flush_buffer ( YY_BUFFER_STATE b ); void yypush_buffer_state ( YY_BUFFER_STATE new_buffer ); void yypop_buffer_state ( void ); static void yyensure_buffer_stack ( void ); static void yy_load_buffer_state ( void ); static void yy_init_buffer ( YY_BUFFER_STATE b, FILE *file ); #define YY_FLUSH_BUFFER yy_flush_buffer( YY_CURRENT_BUFFER ) YY_BUFFER_STATE yy_scan_buffer ( char *base, yy_size_t size ); YY_BUFFER_STATE yy_scan_string ( const char *yy_str ); YY_BUFFER_STATE yy_scan_bytes ( const char *bytes, int len ); void *yyalloc ( yy_size_t ); void *yyrealloc ( void *, yy_size_t ); void yyfree ( void * ); #define yy_new_buffer yy_create_buffer #define yy_set_interactive(is_interactive) \ { \ if ( ! YY_CURRENT_BUFFER ){ \ yyensure_buffer_stack (); \ YY_CURRENT_BUFFER_LVALUE = \ yy_create_buffer( yyin, YY_BUF_SIZE ); \ } \ YY_CURRENT_BUFFER_LVALUE->yy_is_interactive = is_interactive; \ } #define yy_set_bol(at_bol) \ { \ if ( ! YY_CURRENT_BUFFER ){\ yyensure_buffer_stack (); \ YY_CURRENT_BUFFER_LVALUE = \ yy_create_buffer( yyin, YY_BUF_SIZE ); \ } \ YY_CURRENT_BUFFER_LVALUE->yy_at_bol = at_bol; \ } #define YY_AT_BOL() (YY_CURRENT_BUFFER_LVALUE->yy_at_bol) /* Begin user sect3 */ #define VPreLexwrap() (/*CONSTCOND*/1) #define YY_SKIP_YYWRAP typedef flex_uint8_t YY_CHAR; FILE *yyin = NULL, *yyout = NULL; typedef int yy_state_type; extern int yylineno; int yylineno = 1; extern char *yytext; #ifdef yytext_ptr #undef yytext_ptr #endif #define yytext_ptr yytext static yy_state_type yy_get_previous_state ( void ); static yy_state_type yy_try_NUL_trans ( yy_state_type current_state ); static int yy_get_next_buffer ( void ); static void yynoreturn yy_fatal_error ( const char* msg ); /* Done after the current pattern has been matched and before the * corresponding action - sets up yytext. */ #define YY_DO_BEFORE_ACTION \ (yytext_ptr) = yy_bp; \ (yytext_ptr) -= (yy_more_len); \ yyleng = (int) (yy_cp - (yytext_ptr)); \ (yy_hold_char) = *yy_cp; \ *yy_cp = '\0'; \ (yy_c_buf_p) = yy_cp; #define YY_NUM_RULES 121 #define YY_END_OF_BUFFER 122 /* This struct is not used in this scanner, but its presence is necessary. */ struct yy_trans_info { flex_int32_t yy_verify; flex_int32_t yy_nxt; }; static const flex_int32_t yy_accept[692] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 122, 119, 117, 112, 116, 118, 15, 119, 113, 119, 119, 1, 117, 116, 119, 108, 106, 108, 108, 107, 18, 16, 18, 21, 17, 120, 50, 49, 50, 48, 63, 56, 65, 55, 58, 51, 52, 65, 65, 61, 65, 62, 63, 73, 70, 75, 69, 72, 75, 75, 75, 80, 78, 80, 80, 79, 80, 35, 32, 31, 34, 33, 24, 26, 35, 35, 32, 34, 35, 96, 84, 97, 83, 85, 90, 91, 97, 92, 97, 88, 89, 97, 45, 44, 45, 47, 120, 40, 39, 40, 40, 40, 102, 100, 102, 102, 101, 117, 112, 0, 104, 103, 113, 0, 113, 22, 109, 0, 109, 111, 109, 109, 109, 109, 109, 117, 0, 0, 0, 109, 106, 0, 105, 107, 16, 0, 17, 20, 19, 20, 49, 0, 63, 56, 0, 53, 54, 64, 57, 0, 60, 0, 73, 70, 0, 66, 68, 74, 71, 0, 78, 0, 76, 79, 77, 0, 32, 31, 0, 26, 0, 26, 25, 28, 0, 28, 30, 32, 0, 28, 96, 84, 0, 81, 82, 87, 93, 0, 95, 44, 0, 46, 39, 0, 0, 0, 0, 100, 0, 0, 0, 101, 0, 0, 0, 0, 103, 103, 0, 103, 103, 103, 103, 114, 113, 109, 0, 109, 109, 109, 109, 109, 109, 109, 109, 109, 109, 0, 109, 0, 54, 0, 68, 68, 27, 28, 0, 28, 0, 28, 28, 82, 93, 0, 93, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 103, 103, 103, 103, 113, 110, 109, 109, 109, 109, 109, 109, 109, 109, 109, 109, 109, 109, 0, 109, 59, 67, 0, 29, 23, 28, 28, 28, 94, 86, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 103, 103, 103, 103, 109, 109, 109, 4, 109, 109, 109, 109, 109, 109, 109, 109, 109, 0, 109, 28, 28, 28, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 103, 103, 103, 103, 103, 109, 109, 109, 5, 6, 12, 7, 109, 109, 109, 109, 10, 0, 0, 28, 28, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 103, 103, 103, 103, 103, 109, 109, 3, 8, 109, 109, 109, 109, 0, 0, 2, 0, 28, 28, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 103, 0, 103, 103, 103, 109, 109, 9, 0, 109, 109, 0, 28, 28, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 103, 0, 103, 103, 103, 0, 13, 14, 0, 109, 109, 13, 14, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 103, 0, 103, 103, 0, 0, 36, 109, 0, 0, 0, 0, 0, 0, 0, 0, 0, 103, 0, 103, 0, 0, 109, 0, 0, 0, 0, 0, 0, 103, 0, 103, 0, 0, 11, 0, 0, 0, 0, 0, 0, 103, 0, 103, 0, 0, 0, 41, 0, 0, 0, 0, 103, 0, 103, 0, 0, 0, 0, 0, 0, 0, 103, 0, 103, 0, 0, 0, 0, 0, 0, 0, 103, 0, 103, 0, 0, 0, 0, 0, 0, 0, 103, 0, 103, 0, 0, 0, 0, 0, 0, 0, 103, 0, 103, 0, 0, 0, 0, 0, 0, 0, 103, 0, 103, 0, 0, 0, 0, 0, 0, 0, 103, 0, 103, 0, 0, 0, 0, 0, 99, 0, 98, 98, 103, 0, 0, 0, 0, 0, 0, 99, 99, 99, 0, 0, 98, 98, 98, 98, 98, 103, 0, 0, 0, 0, 99, 98, 103, 0, 0, 0, 0, 103, 0, 0, 0, 0, 103, 0, 0, 0, 0, 103, 0, 0, 0, 0, 103, 0, 0, 0, 0, 103, 0, 0, 0, 0, 103, 0, 0, 0, 42, 103, 0, 0, 43, 103, 0, 37, 38, 38, 0 } ; static const YY_CHAR yy_ec[256] = { 0, 1, 1, 1, 1, 1, 1, 1, 1, 2, 3, 1, 2, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 5, 1, 1, 1, 1, 1, 2, 1, 6, 1, 7, 1, 1, 1, 8, 9, 10, 1, 11, 1, 1, 12, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 1, 1, 1, 1, 14, 1, 1, 15, 16, 17, 17, 18, 19, 20, 21, 22, 17, 17, 23, 24, 25, 26, 27, 17, 28, 29, 30, 17, 17, 17, 17, 31, 17, 32, 33, 34, 1, 35, 36, 37, 38, 39, 40, 41, 42, 43, 21, 44, 17, 17, 45, 46, 47, 48, 49, 17, 50, 51, 52, 53, 17, 17, 17, 31, 17, 32, 1, 34, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 54, 1, 1, 1, 54, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 54, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 } ; static const YY_CHAR yy_meta[55] = { 0, 1, 2, 3, 4, 1, 5, 6, 7, 7, 8, 9, 8, 10, 1, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 7, 5, 7, 11, 12, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 1 } ; static const flex_int32_t yy_base[736] = { 0, 0, 54, 108, 162, 216, 270, 12, 14, 322, 356, 36, 67, 392, 446, 500, 554, 606, 640, 71, 88, 40, 91, 676, 730, 1773, 1774, 1770, 1774, 20, 1774, 1774, 9, 1735, 0, 779, 1774, 45, 94, 827, 1774, 1774, 22, 1758, 0, 1774, 1774, 24, 1774, 0, 26, 1774, 1774, 34, 1774, 0, 1774, 47, 0, 1774, 1774, 1774, 1774, 68, 1774, 79, 1774, 93, 0, 1774, 102, 0, 1774, 1774, 113, 125, 1774, 1774, 128, 1757, 0, 130, 1774, 1766, 1774, 132, 1774, 1774, 1731, 0, 118, 141, 144, 146, 0, 1774, 134, 0, 1774, 1774, 1774, 1774, 1774, 145, 1774, 1774, 150, 1774, 1774, 146, 1774, 0, 1774, 1774, 155, 1754, 4, 1774, 1774, 157, 175, 0, 1763, 1774, 185, 284, 570, 1728, 1727, 1726, 1774, 1725, 0, 157, 1774, 48, 154, 161, 57, 164, 203, 208, 1715, 211, 193, 1774, 228, 1774, 0, 1774, 230, 0, 1774, 1774, 232, 1774, 237, 0, 1774, 239, 1774, 0, 1774, 1774, 242, 1774, 1723, 0, 1774, 250, 1774, 1725, 1774, 1774, 252, 1774, 254, 1774, 0, 1774, 256, 1755, 1774, 258, 1720, 1719, 1718, 1774, 1717, 1716, 228, 1774, 264, 287, 249, 0, 1774, 291, 1774, 0, 1774, 1715, 1714, 1774, 1774, 293, 1774, 1774, 304, 263, 1702, 1698, 1774, 306, 576, 741, 0, 744, 160, 255, 1716, 1742, 745, 750, 294, 288, 171, 313, 1774, 1709, 1708, 1707, 1706, 334, 278, 286, 279, 251, 303, 306, 335, 308, 1697, 300, 348, 0, 1734, 1706, 372, 1774, 1702, 1701, 1700, 1729, 350, 331, 0, 1698, 1697, 1696, 1725, 378, 1680, 1689, 1691, 798, 361, 359, 1696, 802, 367, 380, 1695, 394, 396, 387, 390, 387, 1694, 388, 425, 427, 414, 455, 1688, 1774, 399, 440, 429, 430, 431, 433, 338, 341, 432, 447, 436, 381, 1676, 404, 1774, 1774, 416, 1774, 1774, 462, 463, 450, 1774, 1774, 1685, 1672, 1677, 477, 479, 470, 480, 482, 495, 499, 502, 498, 509, 511, 502, 514, 531, 580, 572, 627, 215, 505, 534, 1683, 495, 502, 533, 535, 553, 293, 546, 560, 537, 1677, 624, 516, 568, 628, 1674, 1666, 1669, 611, 586, 611, 612, 615, 641, 623, 645, 665, 1693, 672, 675, 671, 678, 698, 751, 702, 519, 765, 618, 681, 621, 1677, 1676, 1666, 1654, 669, 625, 407, 664, 660, 485, 722, 740, 762, 1632, 1607, 1617, 731, 762, 761, 1632, 786, 794, 794, 1627, 664, 807, 795, 785, 800, 810, 809, 1626, 813, 711, 846, 837, 851, 850, 838, 842, 1610, 1600, 686, 755, 812, 834, 881, 887, 1774, 891, 861, 863, 1598, 1572, 1621, 803, 842, 853, 868, 898, 886, 874, 887, 904, 1591, 878, 908, 896, 884, 896, 901, 913, 916, 591, 915, 920, 891, 895, 1581, 718, 900, 904, 944, 914, 916, 951, 1575, 930, 955, 1584, 910, 956, 1574, 913, 926, 933, 945, 1573, 940, 968, 959, 943, 969, 970, 973, 986, 1557, 1556, 1532, 942, 944, 1545, 1544, 992, 1536, 1524, 955, 966, 975, 971, 972, 980, 989, 977, 981, 989, 1014, 997, 1011, 703, 1523, 1514, 1512, 991, 1493, 1490, 1493, 1015, 1002, 1022, 1010, 1017, 1014, 1041, 1021, 996, 1492, 1487, 1011, 1487, 1493, 1481, 1023, 1024, 1021, 1050, 1026, 1053, 1479, 1489, 1493, 1472, 1483, 1481, 1029, 1031, 1040, 1063, 1046, 1069, 1480, 1481, 1470, 1774, 1471, 1051, 1052, 1061, 1074, 1066, 345, 1470, 1452, 1464, 1450, 1069, 1072, 1060, 1088, 1063, 1079, 1430, 1477, 1426, 1475, 1064, 1065, 1081, 1096, 1084, 1117, 1122, 807, 1125, 137, 1089, 1095, 1423, 1100, 1422, 1130, 1137, 1414, 1140, 1407, 1418, 1397, 1097, 1124, 1107, 1116, 1390, 1387, 1382, 1388, 1112, 1117, 1127, 1143, 1129, 1145, 1375, 1373, 1376, 1376, 1126, 1127, 1134, 1159, 1135, 1152, 1366, 1362, 1227, 1212, 1157, 1162, 1180, 1185, 1189, 1166, 1213, 1224, 1209, 1207, 1190, 1244, 1251, 1193, 1200, 1201, 1240, 1247, 1204, 1205, 1246, 1208, 1179, 1214, 1199, 1197, 1198, 1774, 1774, 1175, 1196, 1194, 1195, 1190, 871, 1191, 1192, 1187, 1197, 1182, 1189, 1184, 1192, 1193, 1176, 1179, 1188, 1188, 1174, 1194, 1184, 1184, 1170, 1180, 1195, 1181, 1167, 1176, 1118, 1211, 961, 801, 383, 1774, 1212, 228, 169, 1774, 1214, 61, 1774, 27, 1774, 1774, 1263, 1275, 1287, 1299, 1311, 1323, 1335, 1347, 1359, 1371, 1383, 1395, 1402, 1414, 1422, 1425, 1427, 1438, 1450, 1462, 1474, 1486, 1489, 1495, 1507, 1514, 1526, 1533, 1545, 1548, 1559, 1566, 1578, 1589, 1601, 1608, 1620, 1632, 1639, 1651, 1663, 1675, 1687, 1699 } ; static const flex_int32_t yy_def[736] = { 0, 692, 692, 693, 693, 694, 694, 695, 695, 696, 696, 697, 697, 698, 698, 699, 699, 700, 700, 701, 701, 702, 702, 703, 703, 691, 691, 691, 691, 691, 691, 691, 691, 704, 705, 706, 691, 691, 691, 706, 691, 691, 691, 691, 707, 691, 691, 691, 691, 708, 709, 691, 691, 691, 691, 710, 691, 691, 710, 691, 691, 691, 691, 691, 691, 711, 691, 710, 712, 691, 691, 712, 691, 691, 691, 713, 691, 691, 691, 691, 714, 691, 691, 691, 691, 691, 691, 691, 715, 716, 717, 691, 691, 717, 718, 691, 691, 718, 691, 691, 691, 691, 691, 691, 691, 691, 719, 691, 691, 691, 691, 720, 691, 691, 691, 691, 691, 691, 691, 691, 691, 721, 691, 691, 691, 691, 722, 704, 691, 705, 691, 723, 724, 723, 691, 723, 723, 723, 723, 723, 691, 691, 691, 691, 723, 691, 691, 691, 707, 691, 691, 708, 691, 691, 691, 691, 691, 710, 691, 691, 691, 725, 691, 691, 691, 691, 691, 712, 691, 691, 691, 726, 691, 691, 691, 691, 691, 691, 714, 691, 691, 691, 691, 691, 715, 691, 716, 691, 727, 728, 727, 691, 691, 691, 727, 718, 691, 691, 691, 729, 691, 730, 731, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 721, 691, 691, 691, 691, 722, 722, 691, 722, 722, 722, 722, 691, 705, 723, 691, 724, 723, 723, 723, 723, 723, 723, 723, 723, 723, 691, 723, 691, 725, 691, 726, 726, 691, 727, 691, 728, 691, 727, 727, 729, 730, 691, 731, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 722, 722, 722, 722, 705, 691, 723, 723, 723, 723, 723, 723, 723, 723, 723, 723, 723, 723, 691, 723, 691, 691, 691, 691, 691, 727, 727, 727, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 722, 722, 722, 722, 723, 723, 723, 723, 723, 723, 723, 723, 723, 723, 723, 723, 723, 691, 723, 727, 727, 727, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 722, 722, 722, 722, 722, 723, 723, 723, 723, 723, 723, 723, 723, 723, 723, 723, 723, 691, 732, 727, 727, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 722, 722, 722, 722, 722, 723, 723, 723, 723, 723, 723, 723, 723, 732, 732, 691, 732, 727, 727, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 722, 691, 722, 722, 722, 723, 723, 723, 691, 723, 723, 732, 727, 727, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 722, 691, 722, 722, 722, 691, 723, 723, 691, 723, 723, 727, 727, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 722, 691, 722, 722, 691, 691, 723, 723, 691, 691, 691, 691, 691, 691, 691, 691, 691, 722, 691, 722, 691, 691, 723, 691, 691, 691, 691, 691, 691, 722, 691, 722, 691, 691, 723, 691, 691, 691, 691, 691, 691, 722, 691, 722, 691, 691, 691, 691, 691, 691, 691, 691, 722, 691, 722, 691, 691, 691, 691, 691, 691, 691, 722, 691, 722, 691, 691, 691, 691, 691, 691, 691, 722, 691, 722, 691, 691, 691, 691, 691, 691, 691, 722, 691, 722, 691, 691, 691, 691, 691, 691, 691, 722, 691, 722, 691, 691, 691, 691, 691, 691, 691, 722, 691, 722, 691, 691, 691, 691, 691, 691, 691, 722, 691, 722, 691, 691, 691, 691, 691, 733, 691, 734, 735, 722, 691, 691, 691, 691, 691, 691, 733, 733, 733, 691, 691, 734, 734, 735, 735, 735, 722, 691, 691, 691, 691, 691, 691, 722, 691, 691, 691, 691, 722, 691, 691, 691, 691, 722, 691, 691, 691, 691, 722, 691, 691, 691, 691, 722, 691, 691, 691, 691, 722, 691, 691, 691, 691, 722, 691, 691, 691, 691, 722, 691, 691, 691, 722, 691, 691, 722, 691, 0, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691 } ; static const flex_int32_t yy_nxt[1829] = { 0, 26, 27, 28, 29, 30, 31, 26, 26, 26, 26, 26, 32, 26, 26, 52, 53, 52, 53, 125, 54, 126, 54, 123, 124, 145, 146, 149, 150, 153, 154, 691, 26, 34, 26, 691, 35, 155, 156, 69, 70, 71, 72, 113, 114, 210, 73, 140, 74, 141, 158, 159, 115, 211, 36, 26, 37, 28, 38, 30, 31, 26, 26, 26, 26, 26, 32, 26, 26, 75, 69, 70, 71, 72, 108, 109, 116, 73, 160, 74, 161, 142, 163, 164, 231, 110, 26, 34, 26, 234, 39, 108, 109, 231, 113, 114, 141, 123, 143, 165, 75, 690, 110, 115, 111, 168, 169, 240, 36, 40, 40, 41, 42, 40, 40, 40, 40, 40, 43, 40, 40, 111, 40, 170, 187, 171, 166, 116, 173, 174, 142, 175, 176, 179, 180, 182, 183, 196, 197, 577, 40, 40, 40, 192, 40, 141, 141, 182, 193, 204, 205, 189, 187, 190, 191, 198, 200, 199, 207, 208, 212, 213, 40, 40, 40, 41, 42, 40, 40, 40, 40, 40, 43, 40, 40, 691, 40, 142, 587, 189, 142, 190, 191, 202, 273, 214, 203, 215, 123, 124, 231, 194, 233, 231, 40, 40, 40, 231, 40, 235, 231, 236, 282, 238, 237, 140, 273, 141, 239, 688, 141, 241, 141, 141, 123, 143, 40, 45, 45, 46, 47, 45, 48, 45, 45, 45, 45, 45, 45, 231, 45, 145, 146, 149, 150, 153, 244, 243, 370, 142, 155, 156, 158, 159, 142, 163, 164, 142, 45, 50, 45, 231, 45, 168, 169, 173, 174, 175, 176, 179, 180, 182, 183, 254, 251, 261, 192, 261, 141, 687, 45, 45, 45, 46, 47, 45, 48, 45, 45, 45, 45, 45, 45, 274, 45, 251, 217, 231, 217, 141, 182, 193, 691, 255, 196, 197, 204, 205, 691, 218, 142, 291, 45, 50, 45, 274, 45, 207, 208, 212, 213, 219, 262, 220, 231, 231, 281, 691, 280, 290, 288, 218, 231, 142, 45, 56, 57, 58, 59, 231, 60, 61, 62, 219, 63, 220, 231, 289, 281, 231, 280, 281, 231, 292, 231, 294, 378, 299, 297, 691, 293, 153, 244, 286, 64, 65, 66, 287, 67, 56, 57, 58, 59, 283, 60, 61, 62, 251, 63, 305, 231, 231, 295, 306, 231, 301, 302, 231, 307, 337, 261, 338, 261, 296, 563, 313, 251, 314, 64, 65, 66, 316, 67, 76, 76, 77, 78, 76, 76, 76, 76, 76, 79, 76, 76, 248, 76, 313, 317, 314, 319, 320, 321, 316, 322, 323, 323, 231, 691, 301, 302, 330, 342, 685, 76, 81, 76, 262, 76, 691, 317, 691, 319, 320, 321, 231, 322, 323, 325, 328, 231, 326, 327, 231, 416, 344, 76, 76, 76, 77, 78, 76, 76, 76, 76, 76, 79, 76, 76, 691, 76, 328, 331, 326, 327, 231, 231, 231, 231, 231, 327, 333, 231, 332, 334, 335, 231, 339, 76, 81, 76, 336, 76, 231, 345, 346, 251, 383, 341, 383, 340, 347, 329, 351, 352, 353, 354, 355, 251, 251, 76, 82, 83, 84, 85, 86, 87, 82, 82, 82, 82, 82, 82, 82, 82, 351, 352, 353, 354, 355, 356, 357, 358, 691, 359, 361, 362, 363, 360, 362, 371, 231, 82, 89, 82, 691, 90, 373, 231, 384, 409, 231, 356, 357, 374, 358, 359, 361, 362, 363, 360, 364, 251, 365, 82, 82, 91, 84, 92, 86, 87, 82, 82, 82, 82, 82, 82, 82, 82, 231, 231, 231, 222, 231, 223, 365, 691, 376, 265, 381, 265, 372, 231, 375, 691, 224, 82, 89, 82, 231, 93, 266, 379, 385, 377, 691, 231, 225, 367, 226, 366, 380, 368, 267, 251, 268, 390, 224, 82, 95, 96, 97, 98, 266, 99, 100, 101, 102, 103, 227, 367, 226, 475, 366, 368, 267, 383, 268, 383, 390, 383, 691, 383, 389, 393, 394, 411, 391, 104, 101, 105, 392, 106, 95, 96, 97, 98, 366, 99, 100, 101, 102, 103, 397, 231, 389, 393, 231, 394, 391, 231, 231, 413, 392, 251, 415, 436, 395, 436, 398, 369, 396, 104, 101, 105, 397, 106, 117, 117, 118, 119, 117, 117, 117, 117, 117, 117, 117, 120, 395, 117, 398, 399, 396, 401, 402, 231, 403, 402, 412, 231, 404, 691, 417, 418, 231, 691, 691, 117, 117, 117, 414, 117, 444, 399, 445, 401, 231, 402, 403, 452, 405, 231, 404, 420, 421, 422, 451, 406, 408, 117, 117, 117, 118, 119, 117, 117, 117, 117, 117, 117, 117, 120, 269, 117, 269, 217, 222, 217, 223, 406, 408, 223, 518, 223, 691, 270, 452, 423, 218, 224, 428, 117, 117, 117, 276, 117, 481, 271, 691, 272, 219, 225, 220, 226, 407, 251, 277, 270, 278, 424, 218, 224, 428, 117, 130, 429, 276, 430, 407, 271, 231, 272, 219, 227, 220, 226, 407, 251, 279, 265, 278, 265, 438, 269, 461, 269, 461, 429, 575, 430, 410, 132, 266, 133, 134, 432, 270, 433, 135, 136, 434, 397, 137, 437, 267, 438, 268, 138, 271, 439, 272, 139, 130, 440, 266, 441, 440, 432, 270, 433, 691, 684, 434, 397, 585, 437, 267, 231, 268, 691, 271, 439, 272, 691, 691, 440, 428, 441, 443, 132, 406, 133, 134, 453, 406, 446, 135, 136, 447, 231, 137, 144, 449, 231, 691, 138, 450, 231, 428, 139, 454, 462, 406, 421, 455, 463, 448, 446, 420, 421, 422, 447, 420, 421, 422, 456, 251, 457, 251, 464, 432, 464, 465, 462, 466, 436, 469, 436, 463, 445, 439, 445, 470, 471, 444, 439, 445, 445, 691, 445, 657, 477, 432, 478, 465, 479, 231, 466, 469, 480, 231, 460, 439, 467, 470, 231, 471, 472, 491, 231, 482, 494, 473, 476, 483, 474, 421, 455, 484, 251, 485, 251, 486, 495, 486, 467, 461, 464, 461, 464, 491, 397, 691, 494, 473, 476, 496, 474, 498, 478, 500, 478, 691, 691, 477, 495, 478, 231, 488, 231, 506, 505, 510, 397, 489, 492, 499, 478, 496, 478, 498, 501, 500, 486, 428, 486, 511, 406, 512, 691, 432, 513, 473, 514, 510, 397, 489, 492, 499, 439, 515, 517, 683, 501, 691, 474, 428, 691, 511, 406, 512, 502, 432, 513, 473, 514, 231, 397, 516, 525, 428, 439, 515, 517, 503, 521, 526, 474, 432, 406, 507, 527, 439, 530, 691, 529, 231, 537, 538, 539, 516, 525, 428, 691, 541, 533, 691, 548, 526, 549, 432, 406, 550, 527, 439, 528, 691, 529, 552, 537, 538, 539, 691, 558, 559, 560, 541, 691, 540, 548, 562, 549, 691, 568, 550, 551, 569, 528, 561, 570, 552, 691, 572, 578, 579, 558, 559, 560, 580, 691, 540, 582, 562, 691, 542, 568, 588, 551, 569, 553, 561, 570, 589, 581, 572, 578, 579, 571, 583, 691, 584, 580, 600, 584, 582, 584, 586, 691, 586, 588, 573, 583, 602, 584, 591, 589, 581, 608, 584, 571, 584, 586, 609, 586, 600, 610, 691, 612, 691, 601, 618, 619, 620, 622, 602, 691, 603, 681, 628, 608, 628, 611, 691, 631, 609, 632, 629, 593, 610, 691, 612, 601, 618, 619, 594, 620, 622, 621, 691, 691, 596, 633, 691, 633, 611, 691, 636, 613, 637, 634, 639, 628, 637, 628, 631, 623, 632, 691, 691, 629, 621, 631, 633, 632, 633, 636, 639, 637, 637, 639, 634, 637, 640, 647, 691, 691, 680, 691, 679, 678, 676, 675, 674, 652, 673, 671, 670, 667, 669, 662, 668, 666, 665, 677, 672, 664, 663, 661, 660, 659, 658, 656, 655, 654, 653, 651, 650, 649, 648, 691, 691, 646, 686, 689, 691, 645, 644, 643, 642, 641, 627, 626, 682, 33, 33, 33, 33, 33, 33, 33, 33, 33, 33, 33, 33, 44, 44, 44, 44, 44, 44, 44, 44, 44, 44, 44, 44, 49, 49, 49, 49, 49, 49, 49, 49, 49, 49, 49, 49, 51, 51, 51, 51, 51, 51, 51, 51, 51, 51, 51, 51, 55, 55, 55, 55, 55, 55, 55, 55, 55, 55, 55, 55, 68, 68, 68, 68, 68, 68, 68, 68, 68, 68, 68, 68, 80, 80, 80, 80, 80, 80, 80, 80, 80, 80, 80, 80, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 94, 94, 94, 94, 94, 94, 94, 94, 94, 94, 94, 94, 107, 107, 107, 107, 107, 107, 107, 107, 107, 107, 107, 107, 112, 112, 112, 112, 112, 112, 112, 112, 112, 112, 112, 112, 121, 121, 121, 121, 121, 121, 121, 121, 121, 121, 121, 121, 127, 625, 624, 617, 127, 127, 127, 129, 616, 615, 614, 129, 129, 129, 129, 129, 129, 129, 129, 131, 607, 606, 605, 604, 599, 131, 131, 148, 148, 151, 151, 152, 152, 152, 152, 152, 152, 152, 152, 152, 152, 152, 152, 157, 157, 598, 597, 595, 157, 592, 590, 157, 157, 157, 157, 162, 162, 162, 162, 162, 162, 162, 162, 162, 162, 162, 162, 167, 167, 577, 576, 575, 167, 167, 574, 167, 167, 167, 167, 172, 172, 172, 172, 172, 172, 172, 172, 172, 172, 172, 172, 178, 178, 184, 567, 566, 565, 184, 184, 184, 186, 564, 557, 556, 186, 186, 186, 186, 186, 186, 186, 188, 555, 554, 547, 546, 545, 188, 188, 195, 195, 231, 544, 543, 195, 536, 535, 534, 195, 195, 201, 532, 531, 524, 523, 522, 201, 201, 206, 206, 231, 206, 206, 206, 206, 206, 206, 206, 206, 206, 216, 216, 221, 221, 520, 221, 221, 221, 221, 221, 221, 221, 221, 221, 230, 519, 509, 508, 230, 230, 230, 232, 251, 251, 504, 232, 232, 232, 232, 232, 232, 232, 245, 245, 231, 231, 245, 245, 245, 245, 245, 245, 245, 245, 247, 247, 497, 493, 247, 247, 247, 247, 247, 247, 247, 247, 250, 490, 487, 231, 250, 250, 250, 252, 468, 460, 459, 252, 252, 252, 252, 252, 252, 252, 252, 256, 256, 458, 231, 256, 256, 256, 256, 256, 256, 256, 256, 257, 231, 442, 435, 257, 257, 257, 259, 431, 427, 426, 259, 259, 259, 259, 259, 259, 259, 259, 419, 419, 419, 419, 419, 419, 419, 419, 419, 419, 419, 419, 630, 630, 425, 630, 630, 630, 630, 630, 630, 630, 630, 630, 635, 635, 231, 635, 635, 635, 635, 635, 635, 635, 635, 635, 638, 638, 231, 638, 638, 638, 638, 638, 638, 638, 638, 638, 231, 231, 400, 388, 387, 386, 382, 231, 350, 349, 348, 343, 284, 324, 318, 315, 312, 311, 310, 309, 258, 308, 258, 304, 251, 303, 251, 248, 300, 298, 231, 285, 231, 284, 691, 275, 264, 263, 260, 258, 253, 251, 185, 249, 185, 181, 248, 246, 242, 231, 229, 228, 128, 122, 209, 185, 181, 177, 147, 128, 122, 691, 25, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691 } ; static const flex_int32_t yy_chk[1829] = { 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 7, 7, 8, 8, 32, 7, 32, 8, 29, 29, 42, 42, 47, 47, 50, 50, 689, 1, 1, 1, 0, 1, 53, 53, 11, 11, 11, 11, 21, 21, 116, 11, 37, 11, 37, 57, 57, 21, 116, 1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 11, 12, 12, 12, 12, 19, 19, 21, 12, 63, 12, 63, 37, 65, 65, 135, 19, 2, 2, 2, 135, 2, 20, 20, 138, 22, 22, 38, 38, 38, 67, 12, 687, 20, 22, 19, 70, 70, 138, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 20, 3, 74, 90, 74, 67, 22, 75, 75, 38, 78, 78, 81, 81, 85, 85, 96, 96, 577, 3, 3, 3, 91, 3, 91, 92, 92, 92, 109, 109, 90, 93, 90, 90, 103, 106, 103, 114, 114, 119, 119, 3, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 226, 4, 91, 577, 93, 92, 93, 93, 106, 218, 120, 106, 120, 124, 124, 136, 93, 133, 133, 4, 4, 4, 137, 4, 136, 139, 136, 226, 137, 136, 140, 218, 140, 137, 684, 141, 139, 141, 143, 143, 143, 4, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 144, 5, 146, 146, 150, 150, 154, 154, 144, 330, 140, 156, 156, 159, 159, 141, 164, 164, 143, 5, 5, 5, 330, 5, 169, 169, 174, 174, 176, 176, 180, 180, 183, 183, 190, 190, 209, 192, 209, 192, 683, 5, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 219, 6, 194, 125, 237, 125, 193, 193, 193, 225, 194, 197, 197, 205, 205, 224, 125, 192, 237, 6, 6, 6, 219, 6, 208, 208, 213, 213, 125, 209, 125, 234, 236, 225, 227, 224, 236, 234, 125, 235, 193, 6, 9, 9, 9, 9, 339, 9, 9, 9, 125, 9, 125, 243, 235, 225, 238, 224, 227, 239, 238, 241, 239, 339, 243, 241, 553, 238, 244, 244, 233, 9, 9, 9, 233, 9, 10, 10, 10, 10, 227, 10, 10, 10, 255, 10, 254, 233, 240, 240, 254, 292, 248, 248, 293, 255, 292, 261, 293, 261, 240, 553, 266, 254, 267, 10, 10, 10, 270, 10, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 248, 13, 266, 271, 267, 273, 274, 275, 270, 276, 277, 279, 297, 282, 302, 302, 286, 297, 680, 13, 13, 13, 261, 13, 280, 271, 281, 273, 274, 275, 286, 276, 277, 279, 282, 299, 280, 281, 379, 379, 299, 13, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 283, 14, 282, 287, 280, 281, 288, 289, 290, 294, 291, 283, 289, 296, 288, 289, 290, 287, 294, 14, 14, 14, 291, 14, 295, 305, 306, 307, 382, 296, 382, 295, 307, 283, 313, 314, 315, 316, 317, 305, 306, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 313, 314, 315, 316, 317, 318, 319, 320, 368, 321, 322, 323, 324, 321, 325, 331, 334, 15, 15, 15, 326, 15, 334, 335, 345, 368, 331, 318, 319, 335, 320, 321, 322, 323, 324, 321, 325, 345, 326, 15, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 336, 332, 337, 126, 342, 126, 326, 328, 337, 214, 342, 214, 332, 340, 336, 327, 126, 16, 16, 16, 338, 16, 214, 340, 346, 338, 446, 341, 126, 328, 126, 327, 341, 328, 214, 346, 214, 352, 126, 16, 17, 17, 17, 17, 214, 17, 17, 17, 17, 17, 126, 328, 126, 446, 327, 328, 214, 344, 214, 344, 352, 347, 329, 347, 351, 354, 355, 370, 353, 17, 17, 17, 353, 17, 18, 18, 18, 18, 329, 18, 18, 18, 18, 18, 357, 370, 351, 354, 372, 355, 353, 344, 378, 372, 353, 347, 378, 397, 356, 397, 358, 329, 356, 18, 18, 18, 357, 18, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 356, 23, 358, 359, 356, 361, 362, 381, 363, 364, 371, 380, 363, 365, 380, 381, 377, 367, 502, 23, 23, 23, 377, 23, 406, 359, 406, 361, 371, 362, 363, 452, 364, 415, 363, 383, 383, 383, 415, 365, 367, 23, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 215, 24, 215, 217, 222, 217, 222, 365, 367, 223, 502, 223, 366, 215, 416, 384, 217, 222, 389, 24, 24, 24, 223, 24, 452, 215, 369, 215, 217, 222, 217, 222, 366, 384, 223, 215, 223, 385, 217, 222, 389, 24, 35, 390, 223, 391, 369, 215, 416, 215, 217, 222, 217, 222, 366, 385, 223, 265, 223, 265, 400, 269, 428, 269, 428, 390, 575, 391, 369, 35, 265, 35, 35, 393, 269, 394, 35, 35, 395, 398, 35, 399, 265, 400, 265, 35, 269, 401, 269, 35, 39, 402, 265, 403, 405, 393, 269, 394, 408, 679, 395, 398, 575, 399, 265, 417, 265, 407, 269, 401, 269, 410, 409, 402, 429, 403, 405, 39, 407, 39, 39, 417, 410, 408, 39, 39, 409, 418, 39, 39, 411, 411, 652, 39, 412, 412, 429, 39, 418, 430, 407, 419, 419, 431, 410, 408, 420, 420, 420, 409, 422, 422, 422, 423, 423, 424, 424, 432, 433, 432, 434, 430, 435, 436, 438, 436, 431, 439, 440, 439, 441, 442, 444, 443, 444, 445, 447, 445, 652, 448, 433, 448, 434, 449, 449, 435, 438, 450, 450, 460, 440, 436, 441, 453, 442, 443, 463, 454, 453, 466, 444, 447, 454, 445, 455, 455, 456, 456, 457, 457, 458, 467, 458, 436, 461, 464, 461, 464, 463, 468, 473, 466, 444, 447, 469, 445, 471, 472, 474, 472, 475, 476, 477, 467, 477, 482, 460, 483, 483, 482, 489, 468, 461, 464, 473, 478, 469, 478, 471, 476, 474, 486, 490, 486, 491, 475, 492, 518, 493, 494, 477, 495, 489, 496, 461, 464, 473, 497, 498, 500, 678, 476, 501, 478, 490, 499, 491, 475, 492, 477, 493, 494, 477, 495, 506, 496, 499, 510, 511, 497, 498, 500, 478, 506, 512, 478, 513, 501, 486, 514, 515, 518, 516, 517, 521, 525, 526, 527, 499, 510, 511, 528, 529, 521, 530, 537, 512, 538, 513, 501, 539, 514, 515, 516, 540, 517, 541, 525, 526, 527, 542, 548, 549, 550, 529, 551, 528, 537, 552, 538, 563, 558, 539, 540, 559, 516, 551, 560, 541, 561, 562, 568, 569, 548, 549, 550, 570, 571, 528, 572, 552, 581, 530, 558, 578, 540, 559, 542, 551, 560, 579, 571, 562, 568, 569, 561, 573, 593, 573, 570, 590, 574, 572, 574, 576, 591, 576, 578, 563, 583, 592, 583, 581, 579, 571, 598, 584, 561, 584, 586, 599, 586, 590, 600, 601, 602, 603, 591, 608, 609, 610, 612, 592, 613, 593, 676, 618, 598, 618, 601, 611, 619, 599, 619, 618, 583, 600, 623, 602, 591, 608, 609, 584, 610, 612, 611, 647, 662, 586, 620, 640, 620, 601, 657, 621, 603, 621, 620, 622, 628, 622, 628, 631, 613, 631, 667, 672, 628, 611, 632, 633, 632, 633, 636, 637, 636, 637, 639, 633, 639, 623, 640, 677, 682, 675, 686, 674, 673, 671, 670, 669, 647, 668, 666, 665, 662, 664, 657, 663, 661, 660, 672, 667, 659, 658, 656, 655, 654, 653, 651, 650, 649, 648, 644, 643, 642, 641, 638, 635, 634, 682, 686, 630, 629, 627, 626, 625, 624, 617, 616, 677, 692, 692, 692, 692, 692, 692, 692, 692, 692, 692, 692, 692, 693, 693, 693, 693, 693, 693, 693, 693, 693, 693, 693, 693, 694, 694, 694, 694, 694, 694, 694, 694, 694, 694, 694, 694, 695, 695, 695, 695, 695, 695, 695, 695, 695, 695, 695, 695, 696, 696, 696, 696, 696, 696, 696, 696, 696, 696, 696, 696, 697, 697, 697, 697, 697, 697, 697, 697, 697, 697, 697, 697, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 698, 699, 699, 699, 699, 699, 699, 699, 699, 699, 699, 699, 699, 700, 700, 700, 700, 700, 700, 700, 700, 700, 700, 700, 700, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 701, 702, 702, 702, 702, 702, 702, 702, 702, 702, 702, 702, 702, 703, 703, 703, 703, 703, 703, 703, 703, 703, 703, 703, 703, 704, 615, 614, 607, 704, 704, 704, 705, 606, 605, 604, 705, 705, 705, 705, 705, 705, 705, 705, 706, 597, 596, 595, 594, 589, 706, 706, 707, 707, 708, 708, 709, 709, 709, 709, 709, 709, 709, 709, 709, 709, 709, 709, 710, 710, 588, 587, 585, 710, 582, 580, 710, 710, 710, 710, 711, 711, 711, 711, 711, 711, 711, 711, 711, 711, 711, 711, 712, 712, 567, 566, 565, 712, 712, 564, 712, 712, 712, 712, 713, 713, 713, 713, 713, 713, 713, 713, 713, 713, 713, 713, 714, 714, 715, 557, 556, 555, 715, 715, 715, 716, 554, 547, 545, 716, 716, 716, 716, 716, 716, 716, 717, 544, 543, 536, 535, 534, 717, 717, 718, 718, 533, 532, 531, 718, 524, 523, 522, 718, 718, 719, 520, 519, 509, 508, 507, 719, 719, 720, 720, 505, 720, 720, 720, 720, 720, 720, 720, 720, 720, 721, 721, 722, 722, 504, 722, 722, 722, 722, 722, 722, 722, 722, 722, 723, 503, 488, 487, 723, 723, 723, 724, 485, 484, 481, 724, 724, 724, 724, 724, 724, 724, 725, 725, 480, 479, 725, 725, 725, 725, 725, 725, 725, 725, 726, 726, 470, 465, 726, 726, 726, 726, 726, 726, 726, 726, 727, 462, 459, 451, 727, 727, 727, 728, 437, 427, 426, 728, 728, 728, 728, 728, 728, 728, 728, 729, 729, 425, 414, 729, 729, 729, 729, 729, 729, 729, 729, 730, 413, 404, 396, 730, 730, 730, 731, 392, 388, 387, 731, 731, 731, 731, 731, 731, 731, 731, 732, 732, 732, 732, 732, 732, 732, 732, 732, 732, 732, 732, 733, 733, 386, 733, 733, 733, 733, 733, 733, 733, 733, 733, 734, 734, 376, 734, 734, 734, 734, 734, 734, 734, 734, 734, 735, 735, 375, 735, 735, 735, 735, 735, 735, 735, 735, 735, 374, 373, 360, 350, 349, 348, 343, 333, 312, 311, 310, 298, 284, 278, 272, 268, 264, 263, 262, 260, 259, 258, 257, 253, 252, 251, 250, 247, 246, 242, 232, 231, 230, 229, 221, 220, 211, 210, 202, 201, 189, 188, 186, 185, 184, 181, 171, 166, 142, 131, 129, 128, 127, 122, 115, 88, 83, 79, 43, 33, 27, 25, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691, 691 } ; static yy_state_type yy_last_accepting_state; static char *yy_last_accepting_cpos; extern int yy_flex_debug; int yy_flex_debug = 0; /* The intent behind this definition is that it'll catch * any uses of REJECT which flex missed. */ #define REJECT reject_used_but_not_detected static int yy_more_flag = 0; static int yy_more_len = 0; #define yymore() ((yy_more_flag) = 1) #define YY_MORE_ADJ (yy_more_len) #define YY_RESTORE_YY_MORE_OFFSET char *yytext; #line 1 "VPreLex.l" #line 6 "VPreLex.l" /****************************************************************************** * DESCRIPTION: Verilog Preprocessor Lexer * * This file is part of Verilog-Perl. * * Author: Wilson Snyder * * Code available from: https://www.veripool.org/verilog-perl * ****************************************************************************** * * Copyright 2000-2024 by Wilson Snyder. This program is free software; * you can redistribute it and/or modify it under the terms of either the GNU * Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * ***************************************************************************** * Do not use Flex in C++ mode. It has bugs with yyunput() which result in * lost characters. *****************************************************************************/ #include "VPreProc.h" #include "VPreLex.h" #include #include #include #include // Flex 2.5.35 has compile warning in ECHO, so we'll default our own rule #define ECHO yyerrorf("Missing VPreLex.l rule: ECHO rule invoked in state %d: %s", YY_START, yytext); VPreLex* VPreLex::s_currentLexp = NULL; // Current lexing point #define LEXP VPreLex::s_currentLexp #define linenoInc() { LEXP->linenoInc(); } static bool pedantic() { return LEXP->m_pedantic; } static bool keepWhitespace() { return LEXP->m_keepWhitespace; } static void appendDefValue(const char* t, size_t l) { LEXP->appendDefValue(t,l); } void yyerror(char* msg) { LEXP->curFilelinep()->error(msg); } #define YY_INPUT(buf,result,max_size) \ result = LEXP->inputToLex(buf,max_size); // Accessors, because flex keeps changing the type of yyleng char* yyourtext() { return yytext; } size_t yyourleng() { return (size_t)yyleng; } void yyourtext(const char* textp, size_t size) { yytext=(char*)textp; yyleng=size; } void yyerrorf(const char* format, ...) { char msg[1024]; va_list ap; va_start(ap,format); vsprintf(msg,format,ap); va_end(ap); yyerror(msg); } static bool isWhitespace(const std::string& str) { for (std::string::const_iterator pos = str.begin(); pos != str.end(); ++pos) { if (!isspace(*pos)) return false; } return true; } /**********************************************************************/ #line 1421 "VPreLex_pretmp.cpp" /* drop: Drop Ctrl-Z - can't pass thru or may EOF the output too soon */ /* Where we use symb/symbdef, we must also look for a `` join */ /* Note in the preprocessor \ESCaped is *not* always special; mantis1537/bug441 */ /* Case insensitive; unfortunately ?i: isn't in flex 2.5.4 which is popular */ #line 119 "VPreLex.l" /**************************************************************/ #line 1429 "VPreLex_pretmp.cpp" #define INITIAL 0 #define CMTMODE 1 #define STRMODE 2 #define DEFFPAR 3 #define DEFFORM 4 #define DEFVAL 5 #define DEFCMT 6 #define STRIFY 7 #define ARGMODE 8 #define INCMODE 9 #define PRTMODE 10 #define OFFMODE 11 #ifndef YY_NO_UNISTD_H /* Special case for "unistd.h", since it is non-ANSI. We include it way * down here because we want the user's section 1 to have been scanned first. * The user has a chance to override it with an option. */ #include #endif #ifndef YY_EXTRA_TYPE #define YY_EXTRA_TYPE void * #endif static int yy_init_globals ( void ); /* Accessor methods to globals. These are made visible to non-reentrant scanners for convenience. */ int yylex_destroy ( void ); int yyget_debug ( void ); void yyset_debug ( int debug_flag ); YY_EXTRA_TYPE yyget_extra ( void ); void yyset_extra ( YY_EXTRA_TYPE user_defined ); FILE *yyget_in ( void ); void yyset_in ( FILE * _in_str ); FILE *yyget_out ( void ); void yyset_out ( FILE * _out_str ); int yyget_leng ( void ); char *yyget_text ( void ); int yyget_lineno ( void ); void yyset_lineno ( int _line_number ); /* Macros after this point can all be overridden by user definitions in * section 1. */ #ifndef YY_SKIP_YYWRAP #ifdef __cplusplus extern "C" int yywrap ( void ); #else extern int yywrap ( void ); #endif #endif #ifndef YY_NO_UNPUT static void yyunput ( int c, char *buf_ptr ); #endif #ifndef yytext_ptr static void yy_flex_strncpy ( char *, const char *, int ); #endif #ifdef YY_NEED_STRLEN static int yy_flex_strlen ( const char * ); #endif #ifndef YY_NO_INPUT #ifdef __cplusplus static int yyinput ( void ); #else static int input ( void ); #endif #endif static int yy_start_stack_ptr = 0; static int yy_start_stack_depth = 0; static int *yy_start_stack = NULL; static void yy_push_state ( int _new_state ); static void yy_pop_state ( void ); static int yy_top_state ( void ); /* Amount of stuff to slurp up with each read. */ #ifndef YY_READ_BUF_SIZE #ifdef __ia64__ /* On IA-64, the buffer size is 16k, not 8k */ #define YY_READ_BUF_SIZE 16384 #else #define YY_READ_BUF_SIZE 8192 #endif /* __ia64__ */ #endif /* Copy whatever the last rule matched to the standard output. */ #ifndef ECHO /* This used to be an fputs(), but since the string might contain NUL's, * we now use fwrite(). */ #define ECHO do { if (fwrite( yytext, (size_t) yyleng, 1, yyout )) {} } while (0) #endif /* Gets input and stuffs it into "buf". number of characters read, or YY_NULL, * is returned in "result". */ #ifndef YY_INPUT #define YY_INPUT(buf,result,max_size) \ if ( YY_CURRENT_BUFFER_LVALUE->yy_is_interactive ) \ { \ int c = '*'; \ int n; \ for ( n = 0; n < max_size && \ (c = getc( yyin )) != EOF && c != '\n'; ++n ) \ buf[n] = (char) c; \ if ( c == '\n' ) \ buf[n++] = (char) c; \ if ( c == EOF && ferror( yyin ) ) \ YY_FATAL_ERROR( "input in flex scanner failed" ); \ result = n; \ } \ else \ { \ errno=0; \ while ( (result = (int) fread(buf, 1, (yy_size_t) max_size, yyin)) == 0 && ferror(yyin)) \ { \ if( errno != EINTR) \ { \ YY_FATAL_ERROR( "input in flex scanner failed" ); \ break; \ } \ errno=0; \ clearerr(yyin); \ } \ }\ \ #endif /* No semi-colon after return; correct usage is to write "yyterminate();" - * we don't want an extra ';' after the "return" because that will cause * some compilers to complain about unreachable statements. */ #ifndef yyterminate #define yyterminate() return YY_NULL #endif /* Number of entries by which start-condition stack grows. */ #ifndef YY_START_STACK_INCR #define YY_START_STACK_INCR 25 #endif /* Report a fatal error. */ #ifndef YY_FATAL_ERROR #define YY_FATAL_ERROR(msg) yy_fatal_error( msg ) #endif /* end tables serialization structures and prototypes */ /* Default declaration of generated scanner - a define so the user can * easily add parameters. */ #ifndef YY_DECL #define YY_DECL_IS_OURS 1 extern int yylex (void); #define YY_DECL int yylex (void) #endif /* !YY_DECL */ /* Code executed at the beginning of each rule, after yytext and yyleng * have been set up. */ #ifndef YY_USER_ACTION #define YY_USER_ACTION #endif /* Code executed at the end of each rule. */ #ifndef YY_BREAK #define YY_BREAK /*LINTED*/break; #endif #define YY_RULE_SETUP \ if ( yyleng > 0 ) \ YY_CURRENT_BUFFER_LVALUE->yy_at_bol = \ (yytext[yyleng - 1] == '\n'); \ YY_USER_ACTION /** The main scanner function which does all the work. */ YY_DECL { yy_state_type yy_current_state; char *yy_cp, *yy_bp; int yy_act; if ( !(yy_init) ) { (yy_init) = 1; #ifdef YY_USER_INIT YY_USER_INIT; #endif if ( ! (yy_start) ) (yy_start) = 1; /* first start state */ if ( ! yyin ) yyin = stdin; if ( ! yyout ) yyout = stdout; if ( ! YY_CURRENT_BUFFER ) { yyensure_buffer_stack (); YY_CURRENT_BUFFER_LVALUE = yy_create_buffer( yyin, YY_BUF_SIZE ); } yy_load_buffer_state( ); } { #line 120 "VPreLex.l" #line 1673 "VPreLex_pretmp.cpp" while ( /*CONSTCOND*/1 ) /* loops until end-of-file is reached */ { (yy_more_len) = 0; if ( (yy_more_flag) ) { (yy_more_len) = (int) ((yy_c_buf_p) - (yytext_ptr)); (yy_more_flag) = 0; } yy_cp = (yy_c_buf_p); /* Support of yytext. */ *yy_cp = (yy_hold_char); /* yy_bp points to the position in yy_ch_buf of the start of * the current run. */ yy_bp = yy_cp; yy_current_state = (yy_start); yy_current_state += YY_AT_BOL(); yy_match: do { YY_CHAR yy_c = yy_ec[YY_SC_TO_UI(*yy_cp)] ; if ( yy_accept[yy_current_state] ) { (yy_last_accepting_state) = yy_current_state; (yy_last_accepting_cpos) = yy_cp; } while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) { yy_current_state = (int) yy_def[yy_current_state]; if ( yy_current_state >= 692 ) yy_c = yy_meta[yy_c]; } yy_current_state = yy_nxt[yy_base[yy_current_state] + yy_c]; ++yy_cp; } while ( yy_base[yy_current_state] != 1774 ); yy_find_action: yy_act = yy_accept[yy_current_state]; if ( yy_act == 0 ) { /* have to back up */ yy_cp = (yy_last_accepting_cpos); yy_current_state = (yy_last_accepting_state); yy_act = yy_accept[yy_current_state]; } YY_DO_BEFORE_ACTION; do_action: /* This label is used only to access EOF actions. */ switch ( yy_act ) { /* beginning of action switch */ case 0: /* must back up */ /* undo the effects of YY_DO_BEFORE_ACTION */ *yy_cp = (yy_hold_char); yy_cp = (yy_last_accepting_cpos); yy_current_state = (yy_last_accepting_state); goto yy_find_action; case 1: YY_RULE_SETUP #line 122 "VPreLex.l" { } YY_BREAK case 2: /* rule 2 can match eol */ YY_RULE_SETUP #line 123 "VPreLex.l" { LEXP->lineDirective(yytext); return(VP_LINE); } YY_BREAK /* Special directives we recognize */ case 3: YY_RULE_SETUP #line 127 "VPreLex.l" { return(VP_DEFINE); } YY_BREAK case 4: YY_RULE_SETUP #line 128 "VPreLex.l" { return(VP_ELSE); } YY_BREAK case 5: YY_RULE_SETUP #line 129 "VPreLex.l" { return(VP_ELSIF); } YY_BREAK case 6: YY_RULE_SETUP #line 130 "VPreLex.l" { return(VP_ENDIF); } YY_BREAK case 7: YY_RULE_SETUP #line 131 "VPreLex.l" { return(VP_IFDEF); } YY_BREAK case 8: YY_RULE_SETUP #line 132 "VPreLex.l" { return(VP_IFNDEF); } YY_BREAK case 9: YY_RULE_SETUP #line 133 "VPreLex.l" { return(VP_INCLUDE); } YY_BREAK case 10: YY_RULE_SETUP #line 134 "VPreLex.l" { return(VP_UNDEF); } YY_BREAK case 11: YY_RULE_SETUP #line 135 "VPreLex.l" { return(VP_UNDEFINEALL); } YY_BREAK case 12: YY_RULE_SETUP #line 136 "VPreLex.l" { if (!pedantic()) return (VP_ERROR); else return(VP_DEFREF); } YY_BREAK case 13: YY_RULE_SETUP #line 137 "VPreLex.l" { static string rtnfile; rtnfile = '"'; rtnfile += LEXP->curFilelinep()->filename(); rtnfile += '"'; yytext=(char*)rtnfile.c_str(); yyleng = rtnfile.length(); return (VP_STRING); } YY_BREAK case 14: YY_RULE_SETUP #line 141 "VPreLex.l" { static char buf[10]; sprintf(buf, "%d",LEXP->curFilelinep()->lineno()); yytext = buf; yyleng = strlen(yytext); return (VP_TEXT); } YY_BREAK /* Pass-through strings */ case 15: YY_RULE_SETUP #line 147 "VPreLex.l" { yy_push_state(STRMODE); yymore(); } YY_BREAK case YY_STATE_EOF(STRMODE): #line 148 "VPreLex.l" { linenoInc(); yyerrorf("EOF in unterminated string"); yyleng=0; yyterminate(); } YY_BREAK case 16: /* rule 16 can match eol */ YY_RULE_SETUP #line 149 "VPreLex.l" { linenoInc(); yyerrorf("Unterminated string"); BEGIN(INITIAL); } YY_BREAK case 17: YY_RULE_SETUP #line 150 "VPreLex.l" { yymore(); } YY_BREAK case 18: /* rule 18 can match eol */ YY_RULE_SETUP #line 151 "VPreLex.l" { yymore(); } YY_BREAK case 19: /* rule 19 can match eol */ YY_RULE_SETUP #line 152 "VPreLex.l" { linenoInc(); yymore(); } YY_BREAK case 20: YY_RULE_SETUP #line 153 "VPreLex.l" { yymore(); } YY_BREAK case 21: YY_RULE_SETUP #line 154 "VPreLex.l" { yy_pop_state(); if (LEXP->m_parenLevel || LEXP->m_defQuote) { LEXP->m_defQuote=false; appendDefValue(yytext,yyleng); yyleng=0; } else return (VP_STRING); } YY_BREAK /* Stringification */ case 22: YY_RULE_SETUP #line 159 "VPreLex.l" { yy_push_state(STRIFY); return VP_STRIFY; } YY_BREAK case YY_STATE_EOF(STRIFY): #line 160 "VPreLex.l" { linenoInc(); yyerrorf("EOF in unterminated '\""); yyleng=0; yyterminate(); } YY_BREAK case 23: YY_RULE_SETUP #line 161 "VPreLex.l" { return VP_BACKQUOTE; } YY_BREAK case 24: YY_RULE_SETUP #line 162 "VPreLex.l" { yy_push_state(STRMODE); yymore(); } YY_BREAK case 25: YY_RULE_SETUP #line 163 "VPreLex.l" { yy_pop_state(); return VP_STRIFY; } YY_BREAK case 26: YY_RULE_SETUP #line 164 "VPreLex.l" { return (VP_SYMBOL); } YY_BREAK case 27: YY_RULE_SETUP #line 165 "VPreLex.l" { yyleng-=2; return (VP_SYMBOL_JOIN); } YY_BREAK case 28: YY_RULE_SETUP #line 166 "VPreLex.l" { return (VP_DEFREF); } YY_BREAK case 29: YY_RULE_SETUP #line 167 "VPreLex.l" { yyleng-=2; return (VP_DEFREF_JOIN); } YY_BREAK case 30: YY_RULE_SETUP #line 168 "VPreLex.l" { yyleng-=2; return (VP_JOIN); } YY_BREAK case 31: /* rule 31 can match eol */ YY_RULE_SETUP #line 169 "VPreLex.l" { linenoInc(); yytext=(char*)"\n"; yyleng=1; return(VP_WHITE); } YY_BREAK case 32: YY_RULE_SETUP #line 170 "VPreLex.l" { return (VP_WHITE); } YY_BREAK case 33: YY_RULE_SETUP #line 171 "VPreLex.l" { } YY_BREAK case 34: YY_RULE_SETUP #line 172 "VPreLex.l" { } YY_BREAK case 35: YY_RULE_SETUP #line 173 "VPreLex.l" { return (VP_TEXT); } YY_BREAK /* Protected blocks */ case 36: YY_RULE_SETUP #line 176 "VPreLex.l" { yy_push_state(PRTMODE); yymore(); } YY_BREAK case 37: YY_RULE_SETUP #line 177 "VPreLex.l" { yy_push_state(PRTMODE); yymore(); } YY_BREAK case 38: YY_RULE_SETUP #line 178 "VPreLex.l" { yy_push_state(PRTMODE); yymore(); } YY_BREAK case YY_STATE_EOF(PRTMODE): #line 179 "VPreLex.l" { linenoInc(); yyerrorf("EOF in `protected"); yyleng=0; yyterminate(); } YY_BREAK case 39: /* rule 39 can match eol */ YY_RULE_SETUP #line 180 "VPreLex.l" { linenoInc(); return VP_TEXT; } YY_BREAK case 40: YY_RULE_SETUP #line 181 "VPreLex.l" { yymore(); } YY_BREAK case 41: YY_RULE_SETUP #line 182 "VPreLex.l" { yy_pop_state(); return VP_TEXT; } YY_BREAK case 42: YY_RULE_SETUP #line 183 "VPreLex.l" { yy_pop_state(); return VP_TEXT; } YY_BREAK case 43: YY_RULE_SETUP #line 184 "VPreLex.l" { yy_pop_state(); return VP_TEXT; } YY_BREAK /* Pass-through include <> filenames */ case YY_STATE_EOF(INCMODE): #line 187 "VPreLex.l" { linenoInc(); yyerrorf("EOF in unterminated include filename"); yyleng=0; yyterminate(); } YY_BREAK case 44: /* rule 44 can match eol */ YY_RULE_SETUP #line 188 "VPreLex.l" { linenoInc(); yyerrorf("Unterminated include filename"); BEGIN(INITIAL); } YY_BREAK case 45: /* rule 45 can match eol */ YY_RULE_SETUP #line 189 "VPreLex.l" { yymore(); } YY_BREAK case 46: YY_RULE_SETUP #line 190 "VPreLex.l" { yymore(); } YY_BREAK case 47: YY_RULE_SETUP #line 191 "VPreLex.l" { yy_pop_state(); return VP_STRING; } YY_BREAK /* Reading definition formal parenthesis (or not) to begin formal arguments */ /* Note '(' must IMMEDIATELY follow definition name */ case 48: YY_RULE_SETUP #line 195 "VPreLex.l" { appendDefValue("(",1); LEXP->m_formalLevel=1; BEGIN(DEFFORM); } YY_BREAK case 49: /* rule 49 can match eol */ YY_RULE_SETUP #line 196 "VPreLex.l" { yy_pop_state(); unput('\n'); yyleng=0; return VP_DEFFORM; } /* DEFVAL will later grab the return */ YY_BREAK case YY_STATE_EOF(DEFFPAR): #line 197 "VPreLex.l" { yy_pop_state(); return VP_DEFFORM; } /* empty formals */ YY_BREAK case 50: YY_RULE_SETUP #line 198 "VPreLex.l" { yy_pop_state(); unput(yytext[yyleng-1]); yyleng=0; return VP_DEFFORM; } /* empty formals */ YY_BREAK /* Reading definition formals (declaration of a define) */ case 51: YY_RULE_SETUP #line 201 "VPreLex.l" { appendDefValue(yytext,yyleng); yyleng=0; ++LEXP->m_formalLevel; } YY_BREAK case 52: YY_RULE_SETUP #line 202 "VPreLex.l" { appendDefValue(yytext,yyleng); yyleng=0; if ((--LEXP->m_formalLevel)==0) { yy_pop_state(); return VP_DEFFORM; } } YY_BREAK case 53: YY_RULE_SETUP #line 203 "VPreLex.l" { yy_push_state(CMTMODE); yymore(); } YY_BREAK case 54: YY_RULE_SETUP #line 204 "VPreLex.l" { return (VP_COMMENT);} YY_BREAK case 55: YY_RULE_SETUP #line 205 "VPreLex.l" { } YY_BREAK case YY_STATE_EOF(DEFFORM): #line 206 "VPreLex.l" { linenoInc(); yy_pop_state(); yyerrorf("Unterminated ( in define formal arguments."); yyleng=0; return VP_DEFFORM; } YY_BREAK case 56: /* rule 56 can match eol */ YY_RULE_SETUP #line 207 "VPreLex.l" { linenoInc(); appendDefValue((char*)"\n",1); } /* Include return so can maintain output line count */ YY_BREAK case 57: /* rule 57 can match eol */ YY_RULE_SETUP #line 208 "VPreLex.l" { linenoInc(); appendDefValue((char*)"\\\n",2); } /* Include return so can maintain output line count */ YY_BREAK case 58: YY_RULE_SETUP #line 209 "VPreLex.l" { LEXP->m_defQuote=true; yy_push_state(STRMODE); yymore(); } /* Legal only in default values */ YY_BREAK case 59: YY_RULE_SETUP #line 210 "VPreLex.l" { appendDefValue(yytext,yyleng); } /* Maybe illegal, otherwise in default value */ YY_BREAK case 60: YY_RULE_SETUP #line 211 "VPreLex.l" { appendDefValue(yytext,yyleng); } /* Maybe illegal, otherwise in default value */ YY_BREAK case 61: YY_RULE_SETUP #line 212 "VPreLex.l" { LEXP->m_formalLevel++; appendDefValue(yytext,yyleng); } YY_BREAK case 62: YY_RULE_SETUP #line 213 "VPreLex.l" { LEXP->m_formalLevel--; appendDefValue(yytext,yyleng); } YY_BREAK case 63: #line 215 "VPreLex.l" case 64: #line 216 "VPreLex.l" case 65: YY_RULE_SETUP #line 216 "VPreLex.l" { appendDefValue(yytext,yyleng); } YY_BREAK /* Reading definition value (declaration of a define's text) */ case 66: YY_RULE_SETUP #line 219 "VPreLex.l" { LEXP->m_defCmtSlash=false; yy_push_state(DEFCMT); yymore(); } /* Special comment parser */ YY_BREAK case 67: /* rule 67 can match eol */ YY_RULE_SETUP #line 220 "VPreLex.l" { linenoInc(); appendDefValue((char*)"\n",1); } /* Spec says // not part of define value */ YY_BREAK case 68: YY_RULE_SETUP #line 221 "VPreLex.l" { return (VP_COMMENT);} YY_BREAK case 69: YY_RULE_SETUP #line 222 "VPreLex.l" { } YY_BREAK case YY_STATE_EOF(DEFVAL): #line 223 "VPreLex.l" { linenoInc(); yy_pop_state(); yytext=(char*)"\n"; yyleng=1; return (VP_DEFVALUE); } /* Technically illegal, but people complained */ YY_BREAK case 70: /* rule 70 can match eol */ YY_RULE_SETUP #line 224 "VPreLex.l" { linenoInc(); yy_pop_state(); yytext=(char*)"\n"; yyleng=1; return (VP_DEFVALUE); } YY_BREAK case 71: /* rule 71 can match eol */ YY_RULE_SETUP #line 225 "VPreLex.l" { linenoInc(); appendDefValue((char*)"\\\n",2); } /* Return, AND \ is part of define value */ YY_BREAK case 72: YY_RULE_SETUP #line 226 "VPreLex.l" { LEXP->m_defQuote=true; yy_push_state(STRMODE); yymore(); } YY_BREAK case 73: #line 228 "VPreLex.l" case 74: #line 229 "VPreLex.l" case 75: YY_RULE_SETUP #line 229 "VPreLex.l" { appendDefValue(yytext,yyleng); } YY_BREAK /* Comments inside define values - if embedded get added to define value per spec */ /* - if no \{crnl} ending then the comment belongs to the next line, as a non-embedded comment */ /* - if all but (say) 3rd line is missing \ then it's indeterminate */ case 76: YY_RULE_SETUP #line 234 "VPreLex.l" { yy_pop_state(); appendDefValue(yytext,yyleng); } YY_BREAK case 77: /* rule 77 can match eol */ YY_RULE_SETUP #line 235 "VPreLex.l" { linenoInc(); LEXP->m_defCmtSlash=true; appendDefValue(yytext,yyleng-2); appendDefValue((char*)"\n",1); } /* Return but not \ */ YY_BREAK case 78: /* rule 78 can match eol */ YY_RULE_SETUP #line 237 "VPreLex.l" { linenoInc(); yymore(); if (LEXP->m_defCmtSlash) yyerrorf("One line of /* ... */ is missing \\ before newline"); BEGIN(CMTMODE); } YY_BREAK case 79: YY_RULE_SETUP #line 239 "VPreLex.l" { yymore(); } YY_BREAK case 80: YY_RULE_SETUP #line 240 "VPreLex.l" { yymore(); } YY_BREAK case YY_STATE_EOF(DEFCMT): #line 241 "VPreLex.l" { yyerrorf("EOF in '/* ... */' block comment\n"); yyleng=0; yyterminate(); } YY_BREAK /* Define arguments (use of a define) */ case 81: YY_RULE_SETUP #line 244 "VPreLex.l" { yy_push_state(CMTMODE); yymore(); } YY_BREAK case 82: YY_RULE_SETUP #line 245 "VPreLex.l" { return (VP_COMMENT);} YY_BREAK case 83: YY_RULE_SETUP #line 246 "VPreLex.l" { } YY_BREAK case YY_STATE_EOF(ARGMODE): #line 247 "VPreLex.l" { yyerrorf("EOF in define argument list\n"); yyleng = 0; yyterminate(); } YY_BREAK case 84: /* rule 84 can match eol */ YY_RULE_SETUP #line 248 "VPreLex.l" { linenoInc(); yytext=(char*)"\n"; yyleng=1; return(VP_WHITE); } YY_BREAK case 85: YY_RULE_SETUP #line 249 "VPreLex.l" { yy_push_state(STRMODE); yymore(); } YY_BREAK case 86: YY_RULE_SETUP #line 250 "VPreLex.l" { appendDefValue(yytext,yyleng); } /* Literal text */ YY_BREAK case 87: YY_RULE_SETUP #line 251 "VPreLex.l" { yy_push_state(STRIFY); return(VP_STRIFY); } YY_BREAK case 88: YY_RULE_SETUP #line 252 "VPreLex.l" { LEXP->m_parenLevel++; appendDefValue(yytext,yyleng); } YY_BREAK case 89: YY_RULE_SETUP #line 253 "VPreLex.l" { LEXP->m_parenLevel--; appendDefValue(yytext,yyleng); } YY_BREAK case 90: YY_RULE_SETUP #line 254 "VPreLex.l" { LEXP->m_parenLevel++; // Note paren level 0 means before "(" of starting args // Level 1 means "," between arguments // Level 2+ means one argument's internal () if (LEXP->m_parenLevel == 1) { // Starting ( if (!isWhitespace(LEXP->m_defValue)) { yyerrorf("Illegal text before '(' that starts define arguments: '%s'", LEXP->m_defValue.c_str()); } } if (LEXP->m_parenLevel>1) { appendDefValue(yytext,yyleng); } else { return (VP_TEXT); }} YY_BREAK case 91: YY_RULE_SETUP #line 269 "VPreLex.l" { LEXP->m_parenLevel--; if (LEXP->m_parenLevel>0) { appendDefValue(yytext,yyleng); } else { yy_pop_state(); return (VP_DEFARG); }} YY_BREAK case 92: YY_RULE_SETUP #line 275 "VPreLex.l" { if (LEXP->m_parenLevel>1) { appendDefValue(yytext,yyleng); } else { yy_pop_state(); return (VP_DEFARG); }} YY_BREAK case 93: YY_RULE_SETUP #line 280 "VPreLex.l" { appendDefValue(yytext,yyleng); } /* defref in defref - outer macro expands first */ YY_BREAK case 94: YY_RULE_SETUP #line 281 "VPreLex.l" { appendDefValue(yytext,yyleng); } /* defref in defref - outer macro expands first */ YY_BREAK case 95: YY_RULE_SETUP #line 282 "VPreLex.l" { appendDefValue(yytext,yyleng); } /* defref in defref - outer macro expands first */ YY_BREAK case 96: #line 284 "VPreLex.l" case 97: YY_RULE_SETUP #line 284 "VPreLex.l" { appendDefValue(yytext,yyleng); } YY_BREAK /* Translate offs. Note final newline not included */ case 98: YY_RULE_SETUP #line 287 "VPreLex.l" { if (LEXP->m_synthesis) { yy_push_state(OFFMODE); } return(VP_COMMENT); } YY_BREAK case 99: YY_RULE_SETUP #line 290 "VPreLex.l" { if (LEXP->m_synthesis) { yy_pop_state(); } return(VP_COMMENT); } YY_BREAK case 100: /* rule 100 can match eol */ YY_RULE_SETUP #line 293 "VPreLex.l" { linenoInc(); yymore(); } /* Need to end the / / */ YY_BREAK case 101: YY_RULE_SETUP #line 294 "VPreLex.l" { } YY_BREAK case 102: YY_RULE_SETUP #line 295 "VPreLex.l" { } YY_BREAK case YY_STATE_EOF(OFFMODE): #line 296 "VPreLex.l" { yyerrorf("EOF in '/*synthesis translate_off*/' region\n"); yyleng=0; yyterminate(); } YY_BREAK /* One line comments. Note final newline not included */ case 103: YY_RULE_SETUP #line 299 "VPreLex.l" { return (VP_COMMENT); } YY_BREAK /* C-style comments. */ /**** See also DEFCMT */ case 104: YY_RULE_SETUP #line 303 "VPreLex.l" { yy_push_state(CMTMODE); yymore(); } YY_BREAK case 105: YY_RULE_SETUP #line 304 "VPreLex.l" { yy_pop_state(); return(VP_COMMENT); } YY_BREAK case 106: /* rule 106 can match eol */ YY_RULE_SETUP #line 305 "VPreLex.l" { linenoInc(); yymore(); } YY_BREAK case 107: YY_RULE_SETUP #line 306 "VPreLex.l" { yymore(); } YY_BREAK case 108: YY_RULE_SETUP #line 307 "VPreLex.l" { yymore(); } YY_BREAK case YY_STATE_EOF(CMTMODE): #line 308 "VPreLex.l" { yyerrorf("EOF in '/* ... */' block comment\n"); yyleng=0; yyterminate(); } YY_BREAK /* Define calls */ /* symbdef prevents normal lex rules from making `\`"foo a symbol {`"foo} instead of a BACKQUOTE */ case 109: YY_RULE_SETUP #line 312 "VPreLex.l" { return (VP_DEFREF); } YY_BREAK case 110: YY_RULE_SETUP #line 313 "VPreLex.l" { yyleng-=2; return (VP_DEFREF_JOIN); } YY_BREAK case 111: YY_RULE_SETUP #line 314 "VPreLex.l" { yyleng-=2; return (VP_JOIN); } YY_BREAK /* Generics */ case YY_STATE_EOF(INITIAL): #line 317 "VPreLex.l" { yyterminate(); } /* A "normal" EOF */ YY_BREAK case 112: /* rule 112 can match eol */ YY_RULE_SETUP #line 318 "VPreLex.l" { linenoInc(); yytext=(char*)"\n"; yyleng=1; return(VP_WHITE); } YY_BREAK case 113: YY_RULE_SETUP #line 319 "VPreLex.l" { return (VP_SYMBOL); } YY_BREAK case 114: YY_RULE_SETUP #line 320 "VPreLex.l" { yyleng-=2; return (VP_SYMBOL_JOIN); } YY_BREAK case 115: YY_RULE_SETUP #line 321 "VPreLex.l" { yyleng-=2; return (VP_JOIN); } YY_BREAK case 116: YY_RULE_SETUP #line 322 "VPreLex.l" { } YY_BREAK case 117: YY_RULE_SETUP #line 323 "VPreLex.l" { if (!keepWhitespace()) { yytext=(char*)" "; yyleng=1; } return VP_WHITE; } YY_BREAK case 118: YY_RULE_SETUP #line 324 "VPreLex.l" { } YY_BREAK case 119: YY_RULE_SETUP #line 325 "VPreLex.l" { return (VP_TEXT); } YY_BREAK case 120: /* rule 120 can match eol */ YY_RULE_SETUP #line 327 "VPreLex.l" { yymore(); } /* Prevent hitting ECHO; */ YY_BREAK case 121: YY_RULE_SETUP #line 328 "VPreLex.l" ECHO; YY_BREAK #line 2454 "VPreLex_pretmp.cpp" case YY_END_OF_BUFFER: { /* Amount of text matched not including the EOB char. */ int yy_amount_of_matched_text = (int) (yy_cp - (yytext_ptr)) - 1; /* Undo the effects of YY_DO_BEFORE_ACTION. */ *yy_cp = (yy_hold_char); YY_RESTORE_YY_MORE_OFFSET if ( YY_CURRENT_BUFFER_LVALUE->yy_buffer_status == YY_BUFFER_NEW ) { /* We're scanning a new file or input source. It's * possible that this happened because the user * just pointed yyin at a new source and called * yylex(). If so, then we have to assure * consistency between YY_CURRENT_BUFFER and our * globals. Here is the right place to do so, because * this is the first action (other than possibly a * back-up) that will match for the new input source. */ (yy_n_chars) = YY_CURRENT_BUFFER_LVALUE->yy_n_chars; YY_CURRENT_BUFFER_LVALUE->yy_input_file = yyin; YY_CURRENT_BUFFER_LVALUE->yy_buffer_status = YY_BUFFER_NORMAL; } /* Note that here we test for yy_c_buf_p "<=" to the position * of the first EOB in the buffer, since yy_c_buf_p will * already have been incremented past the NUL character * (since all states make transitions on EOB to the * end-of-buffer state). Contrast this with the test * in input(). */ if ( (yy_c_buf_p) <= &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)] ) { /* This was really a NUL. */ yy_state_type yy_next_state; (yy_c_buf_p) = (yytext_ptr) + yy_amount_of_matched_text; yy_current_state = yy_get_previous_state( ); /* Okay, we're now positioned to make the NUL * transition. We couldn't have * yy_get_previous_state() go ahead and do it * for us because it doesn't know how to deal * with the possibility of jamming (and we don't * want to build jamming into it because then it * will run more slowly). */ yy_next_state = yy_try_NUL_trans( yy_current_state ); yy_bp = (yytext_ptr) + YY_MORE_ADJ; if ( yy_next_state ) { /* Consume the NUL. */ yy_cp = ++(yy_c_buf_p); yy_current_state = yy_next_state; goto yy_match; } else { yy_cp = (yy_c_buf_p); goto yy_find_action; } } else switch ( yy_get_next_buffer( ) ) { case EOB_ACT_END_OF_FILE: { (yy_did_buffer_switch_on_eof) = 0; if ( yywrap( ) ) { /* Note: because we've taken care in * yy_get_next_buffer() to have set up * yytext, we can now set up * yy_c_buf_p so that if some total * hoser (like flex itself) wants to * call the scanner after we return the * YY_NULL, it'll still work - another * YY_NULL will get returned. */ (yy_c_buf_p) = (yytext_ptr) + YY_MORE_ADJ; yy_act = YY_STATE_EOF(YY_START); goto do_action; } else { if ( ! (yy_did_buffer_switch_on_eof) ) YY_NEW_FILE; } break; } case EOB_ACT_CONTINUE_SCAN: (yy_c_buf_p) = (yytext_ptr) + yy_amount_of_matched_text; yy_current_state = yy_get_previous_state( ); yy_cp = (yy_c_buf_p); yy_bp = (yytext_ptr) + YY_MORE_ADJ; goto yy_match; case EOB_ACT_LAST_MATCH: (yy_c_buf_p) = &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)]; yy_current_state = yy_get_previous_state( ); yy_cp = (yy_c_buf_p); yy_bp = (yytext_ptr) + YY_MORE_ADJ; goto yy_find_action; } break; } default: YY_FATAL_ERROR( "fatal flex scanner internal error--no action found" ); } /* end of action switch */ } /* end of scanning one token */ } /* end of user's declarations */ } /* end of yylex */ /* yy_get_next_buffer - try to read in a new buffer * * Returns a code representing an action: * EOB_ACT_LAST_MATCH - * EOB_ACT_CONTINUE_SCAN - continue scanning from current position * EOB_ACT_END_OF_FILE - end of file */ static int yy_get_next_buffer (void) { char *dest = YY_CURRENT_BUFFER_LVALUE->yy_ch_buf; char *source = (yytext_ptr); int number_to_move, i; int ret_val; if ( (yy_c_buf_p) > &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars) + 1] ) YY_FATAL_ERROR( "fatal flex scanner internal error--end of buffer missed" ); if ( YY_CURRENT_BUFFER_LVALUE->yy_fill_buffer == 0 ) { /* Don't try to fill the buffer, so this is an EOF. */ if ( (yy_c_buf_p) - (yytext_ptr) - YY_MORE_ADJ == 1 ) { /* We matched a single character, the EOB, so * treat this as a final EOF. */ return EOB_ACT_END_OF_FILE; } else { /* We matched some text prior to the EOB, first * process it. */ return EOB_ACT_LAST_MATCH; } } /* Try to read more data. */ /* First move last chars to start of buffer. */ number_to_move = (int) ((yy_c_buf_p) - (yytext_ptr) - 1); for ( i = 0; i < number_to_move; ++i ) *(dest++) = *(source++); if ( YY_CURRENT_BUFFER_LVALUE->yy_buffer_status == YY_BUFFER_EOF_PENDING ) /* don't do the read, it's not guaranteed to return an EOF, * just force an EOF */ YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars) = 0; else { int num_to_read = YY_CURRENT_BUFFER_LVALUE->yy_buf_size - number_to_move - 1; while ( num_to_read <= 0 ) { /* Not enough room in the buffer - grow it. */ /* just a shorter name for the current buffer */ YY_BUFFER_STATE b = YY_CURRENT_BUFFER_LVALUE; int yy_c_buf_p_offset = (int) ((yy_c_buf_p) - b->yy_ch_buf); if ( b->yy_is_our_buffer ) { int new_size = b->yy_buf_size * 2; if ( new_size <= 0 ) b->yy_buf_size += b->yy_buf_size / 8; else b->yy_buf_size *= 2; b->yy_ch_buf = (char *) /* Include room in for 2 EOB chars. */ yyrealloc( (void *) b->yy_ch_buf, (yy_size_t) (b->yy_buf_size + 2) ); } else /* Can't grow it, we don't own it. */ b->yy_ch_buf = NULL; if ( ! b->yy_ch_buf ) YY_FATAL_ERROR( "fatal error - scanner input buffer overflow" ); (yy_c_buf_p) = &b->yy_ch_buf[yy_c_buf_p_offset]; num_to_read = YY_CURRENT_BUFFER_LVALUE->yy_buf_size - number_to_move - 1; } if ( num_to_read > YY_READ_BUF_SIZE ) num_to_read = YY_READ_BUF_SIZE; /* Read in more data. */ YY_INPUT( (&YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[number_to_move]), (yy_n_chars), num_to_read ); YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars); } if ( (yy_n_chars) == 0 ) { if ( number_to_move == YY_MORE_ADJ ) { ret_val = EOB_ACT_END_OF_FILE; yyrestart( yyin ); } else { ret_val = EOB_ACT_LAST_MATCH; YY_CURRENT_BUFFER_LVALUE->yy_buffer_status = YY_BUFFER_EOF_PENDING; } } else ret_val = EOB_ACT_CONTINUE_SCAN; if (((yy_n_chars) + number_to_move) > YY_CURRENT_BUFFER_LVALUE->yy_buf_size) { /* Extend the array by 50%, plus the number we really need. */ int new_size = (yy_n_chars) + number_to_move + ((yy_n_chars) >> 1); YY_CURRENT_BUFFER_LVALUE->yy_ch_buf = (char *) yyrealloc( (void *) YY_CURRENT_BUFFER_LVALUE->yy_ch_buf, (yy_size_t) new_size ); if ( ! YY_CURRENT_BUFFER_LVALUE->yy_ch_buf ) YY_FATAL_ERROR( "out of dynamic memory in yy_get_next_buffer()" ); /* "- 2" to take care of EOB's */ YY_CURRENT_BUFFER_LVALUE->yy_buf_size = (int) (new_size - 2); } (yy_n_chars) += number_to_move; YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)] = YY_END_OF_BUFFER_CHAR; YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars) + 1] = YY_END_OF_BUFFER_CHAR; (yytext_ptr) = &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[0]; return ret_val; } /* yy_get_previous_state - get the state just before the EOB char was reached */ static yy_state_type yy_get_previous_state (void) { yy_state_type yy_current_state; char *yy_cp; yy_current_state = (yy_start); yy_current_state += YY_AT_BOL(); for ( yy_cp = (yytext_ptr) + YY_MORE_ADJ; yy_cp < (yy_c_buf_p); ++yy_cp ) { YY_CHAR yy_c = (*yy_cp ? yy_ec[YY_SC_TO_UI(*yy_cp)] : 1); if ( yy_accept[yy_current_state] ) { (yy_last_accepting_state) = yy_current_state; (yy_last_accepting_cpos) = yy_cp; } while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) { yy_current_state = (int) yy_def[yy_current_state]; if ( yy_current_state >= 692 ) yy_c = yy_meta[yy_c]; } yy_current_state = yy_nxt[yy_base[yy_current_state] + yy_c]; } return yy_current_state; } /* yy_try_NUL_trans - try to make a transition on the NUL character * * synopsis * next_state = yy_try_NUL_trans( current_state ); */ static yy_state_type yy_try_NUL_trans (yy_state_type yy_current_state ) { int yy_is_jam; char *yy_cp = (yy_c_buf_p); YY_CHAR yy_c = 1; if ( yy_accept[yy_current_state] ) { (yy_last_accepting_state) = yy_current_state; (yy_last_accepting_cpos) = yy_cp; } while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) { yy_current_state = (int) yy_def[yy_current_state]; if ( yy_current_state >= 692 ) yy_c = yy_meta[yy_c]; } yy_current_state = yy_nxt[yy_base[yy_current_state] + yy_c]; yy_is_jam = (yy_current_state == 691); return yy_is_jam ? 0 : yy_current_state; } #ifndef YY_NO_UNPUT static void yyunput (int c, char * yy_bp ) { char *yy_cp; yy_cp = (yy_c_buf_p); /* undo effects of setting up yytext */ *yy_cp = (yy_hold_char); if ( yy_cp < YY_CURRENT_BUFFER_LVALUE->yy_ch_buf + 2 ) { /* need to shift things up to make room */ /* +2 for EOB chars. */ int number_to_move = (yy_n_chars) + 2; char *dest = &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[ YY_CURRENT_BUFFER_LVALUE->yy_buf_size + 2]; char *source = &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[number_to_move]; while ( source > YY_CURRENT_BUFFER_LVALUE->yy_ch_buf ) *--dest = *--source; yy_cp += (int) (dest - source); yy_bp += (int) (dest - source); YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars) = (int) YY_CURRENT_BUFFER_LVALUE->yy_buf_size; if ( yy_cp < YY_CURRENT_BUFFER_LVALUE->yy_ch_buf + 2 ) YY_FATAL_ERROR( "flex scanner push-back overflow" ); } *--yy_cp = (char) c; (yytext_ptr) = yy_bp; (yy_hold_char) = *yy_cp; (yy_c_buf_p) = yy_cp; } #endif #ifndef YY_NO_INPUT #ifdef __cplusplus static int yyinput (void) #else static int input (void) #endif { int c; *(yy_c_buf_p) = (yy_hold_char); if ( *(yy_c_buf_p) == YY_END_OF_BUFFER_CHAR ) { /* yy_c_buf_p now points to the character we want to return. * If this occurs *before* the EOB characters, then it's a * valid NUL; if not, then we've hit the end of the buffer. */ if ( (yy_c_buf_p) < &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)] ) /* This was really a NUL. */ *(yy_c_buf_p) = '\0'; else { /* need more input */ int offset = (int) ((yy_c_buf_p) - (yytext_ptr)); ++(yy_c_buf_p); switch ( yy_get_next_buffer( ) ) { case EOB_ACT_LAST_MATCH: /* This happens because yy_g_n_b() * sees that we've accumulated a * token and flags that we need to * try matching the token before * proceeding. But for input(), * there's no matching to consider. * So convert the EOB_ACT_LAST_MATCH * to EOB_ACT_END_OF_FILE. */ /* Reset buffer status. */ yyrestart( yyin ); /*FALLTHROUGH*/ case EOB_ACT_END_OF_FILE: { if ( yywrap( ) ) return 0; if ( ! (yy_did_buffer_switch_on_eof) ) YY_NEW_FILE; #ifdef __cplusplus return yyinput(); #else return input(); #endif } case EOB_ACT_CONTINUE_SCAN: (yy_c_buf_p) = (yytext_ptr) + offset; break; } } } c = *(unsigned char *) (yy_c_buf_p); /* cast for 8-bit char's */ *(yy_c_buf_p) = '\0'; /* preserve yytext */ (yy_hold_char) = *++(yy_c_buf_p); YY_CURRENT_BUFFER_LVALUE->yy_at_bol = (c == '\n'); return c; } #endif /* ifndef YY_NO_INPUT */ /** Immediately switch to a different input stream. * @param input_file A readable stream. * * @note This function does not reset the start condition to @c INITIAL . */ void yyrestart (FILE * input_file ) { if ( ! YY_CURRENT_BUFFER ){ yyensure_buffer_stack (); YY_CURRENT_BUFFER_LVALUE = yy_create_buffer( yyin, YY_BUF_SIZE ); } yy_init_buffer( YY_CURRENT_BUFFER, input_file ); yy_load_buffer_state( ); } /** Switch to a different input buffer. * @param new_buffer The new input buffer. * */ void yy_switch_to_buffer (YY_BUFFER_STATE new_buffer ) { /* TODO. We should be able to replace this entire function body * with * yypop_buffer_state(); * yypush_buffer_state(new_buffer); */ yyensure_buffer_stack (); if ( YY_CURRENT_BUFFER == new_buffer ) return; if ( YY_CURRENT_BUFFER ) { /* Flush out information for old buffer. */ *(yy_c_buf_p) = (yy_hold_char); YY_CURRENT_BUFFER_LVALUE->yy_buf_pos = (yy_c_buf_p); YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars); } YY_CURRENT_BUFFER_LVALUE = new_buffer; yy_load_buffer_state( ); /* We don't actually know whether we did this switch during * EOF (yywrap()) processing, but the only time this flag * is looked at is after yywrap() is called, so it's safe * to go ahead and always set it. */ (yy_did_buffer_switch_on_eof) = 1; } static void yy_load_buffer_state (void) { (yy_n_chars) = YY_CURRENT_BUFFER_LVALUE->yy_n_chars; (yytext_ptr) = (yy_c_buf_p) = YY_CURRENT_BUFFER_LVALUE->yy_buf_pos; yyin = YY_CURRENT_BUFFER_LVALUE->yy_input_file; (yy_hold_char) = *(yy_c_buf_p); } /** Allocate and initialize an input buffer state. * @param file A readable stream. * @param size The character buffer size in bytes. When in doubt, use @c YY_BUF_SIZE. * * @return the allocated buffer state. */ YY_BUFFER_STATE yy_create_buffer (FILE * file, int size ) { YY_BUFFER_STATE b; b = (YY_BUFFER_STATE) yyalloc( sizeof( struct yy_buffer_state ) ); if ( ! b ) YY_FATAL_ERROR( "out of dynamic memory in yy_create_buffer()" ); b->yy_buf_size = size; /* yy_ch_buf has to be 2 characters longer than the size given because * we need to put in 2 end-of-buffer characters. */ b->yy_ch_buf = (char *) yyalloc( (yy_size_t) (b->yy_buf_size + 2) ); if ( ! b->yy_ch_buf ) YY_FATAL_ERROR( "out of dynamic memory in yy_create_buffer()" ); b->yy_is_our_buffer = 1; yy_init_buffer( b, file ); return b; } /** Destroy the buffer. * @param b a buffer created with yy_create_buffer() * */ void yy_delete_buffer (YY_BUFFER_STATE b ) { if ( ! b ) return; if ( b == YY_CURRENT_BUFFER ) /* Not sure if we should pop here. */ YY_CURRENT_BUFFER_LVALUE = (YY_BUFFER_STATE) 0; if ( b->yy_is_our_buffer ) yyfree( (void *) b->yy_ch_buf ); yyfree( (void *) b ); } /* Initializes or reinitializes a buffer. * This function is sometimes called more than once on the same buffer, * such as during a yyrestart() or at EOF. */ static void yy_init_buffer (YY_BUFFER_STATE b, FILE * file ) { int oerrno = errno; yy_flush_buffer( b ); b->yy_input_file = file; b->yy_fill_buffer = 1; /* If b is the current buffer, then yy_init_buffer was _probably_ * called from yyrestart() or through yy_get_next_buffer. * In that case, we don't want to reset the lineno or column. */ if (b != YY_CURRENT_BUFFER){ b->yy_bs_lineno = 1; b->yy_bs_column = 0; } b->yy_is_interactive = file ? (isatty( fileno(file) ) > 0) : 0; errno = oerrno; } /** Discard all buffered characters. On the next scan, YY_INPUT will be called. * @param b the buffer state to be flushed, usually @c YY_CURRENT_BUFFER. * */ void yy_flush_buffer (YY_BUFFER_STATE b ) { if ( ! b ) return; b->yy_n_chars = 0; /* We always need two end-of-buffer characters. The first causes * a transition to the end-of-buffer state. The second causes * a jam in that state. */ b->yy_ch_buf[0] = YY_END_OF_BUFFER_CHAR; b->yy_ch_buf[1] = YY_END_OF_BUFFER_CHAR; b->yy_buf_pos = &b->yy_ch_buf[0]; b->yy_at_bol = 1; b->yy_buffer_status = YY_BUFFER_NEW; if ( b == YY_CURRENT_BUFFER ) yy_load_buffer_state( ); } /** Pushes the new state onto the stack. The new state becomes * the current state. This function will allocate the stack * if necessary. * @param new_buffer The new state. * */ void yypush_buffer_state (YY_BUFFER_STATE new_buffer ) { if (new_buffer == NULL) return; yyensure_buffer_stack(); /* This block is copied from yy_switch_to_buffer. */ if ( YY_CURRENT_BUFFER ) { /* Flush out information for old buffer. */ *(yy_c_buf_p) = (yy_hold_char); YY_CURRENT_BUFFER_LVALUE->yy_buf_pos = (yy_c_buf_p); YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars); } /* Only push if top exists. Otherwise, replace top. */ if (YY_CURRENT_BUFFER) (yy_buffer_stack_top)++; YY_CURRENT_BUFFER_LVALUE = new_buffer; /* copied from yy_switch_to_buffer. */ yy_load_buffer_state( ); (yy_did_buffer_switch_on_eof) = 1; } /** Removes and deletes the top of the stack, if present. * The next element becomes the new top. * */ void yypop_buffer_state (void) { if (!YY_CURRENT_BUFFER) return; yy_delete_buffer(YY_CURRENT_BUFFER ); YY_CURRENT_BUFFER_LVALUE = NULL; if ((yy_buffer_stack_top) > 0) --(yy_buffer_stack_top); if (YY_CURRENT_BUFFER) { yy_load_buffer_state( ); (yy_did_buffer_switch_on_eof) = 1; } } /* Allocates the stack if it does not exist. * Guarantees space for at least one push. */ static void yyensure_buffer_stack (void) { yy_size_t num_to_alloc; if (!(yy_buffer_stack)) { /* First allocation is just for 2 elements, since we don't know if this * scanner will even need a stack. We use 2 instead of 1 to avoid an * immediate realloc on the next call. */ num_to_alloc = 1; /* After all that talk, this was set to 1 anyways... */ (yy_buffer_stack) = (struct yy_buffer_state**)yyalloc (num_to_alloc * sizeof(struct yy_buffer_state*) ); if ( ! (yy_buffer_stack) ) YY_FATAL_ERROR( "out of dynamic memory in yyensure_buffer_stack()" ); memset((yy_buffer_stack), 0, num_to_alloc * sizeof(struct yy_buffer_state*)); (yy_buffer_stack_max) = num_to_alloc; (yy_buffer_stack_top) = 0; return; } if ((yy_buffer_stack_top) >= ((yy_buffer_stack_max)) - 1){ /* Increase the buffer to prepare for a possible push. */ yy_size_t grow_size = 8 /* arbitrary grow size */; num_to_alloc = (yy_buffer_stack_max) + grow_size; (yy_buffer_stack) = (struct yy_buffer_state**)yyrealloc ((yy_buffer_stack), num_to_alloc * sizeof(struct yy_buffer_state*) ); if ( ! (yy_buffer_stack) ) YY_FATAL_ERROR( "out of dynamic memory in yyensure_buffer_stack()" ); /* zero only the new slots.*/ memset((yy_buffer_stack) + (yy_buffer_stack_max), 0, grow_size * sizeof(struct yy_buffer_state*)); (yy_buffer_stack_max) = num_to_alloc; } } /** Setup the input buffer state to scan directly from a user-specified character buffer. * @param base the character buffer * @param size the size in bytes of the character buffer * * @return the newly allocated buffer state object. */ YY_BUFFER_STATE yy_scan_buffer (char * base, yy_size_t size ) { YY_BUFFER_STATE b; if ( size < 2 || base[size-2] != YY_END_OF_BUFFER_CHAR || base[size-1] != YY_END_OF_BUFFER_CHAR ) /* They forgot to leave room for the EOB's. */ return NULL; b = (YY_BUFFER_STATE) yyalloc( sizeof( struct yy_buffer_state ) ); if ( ! b ) YY_FATAL_ERROR( "out of dynamic memory in yy_scan_buffer()" ); b->yy_buf_size = (int) (size - 2); /* "- 2" to take care of EOB's */ b->yy_buf_pos = b->yy_ch_buf = base; b->yy_is_our_buffer = 0; b->yy_input_file = NULL; b->yy_n_chars = b->yy_buf_size; b->yy_is_interactive = 0; b->yy_at_bol = 1; b->yy_fill_buffer = 0; b->yy_buffer_status = YY_BUFFER_NEW; yy_switch_to_buffer( b ); return b; } /** Setup the input buffer state to scan a string. The next call to yylex() will * scan from a @e copy of @a str. * @param yystr a NUL-terminated string to scan * * @return the newly allocated buffer state object. * @note If you want to scan bytes that may contain NUL values, then use * yy_scan_bytes() instead. */ YY_BUFFER_STATE yy_scan_string (const char * yystr ) { return yy_scan_bytes( yystr, (int) strlen(yystr) ); } /** Setup the input buffer state to scan the given bytes. The next call to yylex() will * scan from a @e copy of @a bytes. * @param yybytes the byte buffer to scan * @param _yybytes_len the number of bytes in the buffer pointed to by @a bytes. * * @return the newly allocated buffer state object. */ YY_BUFFER_STATE yy_scan_bytes (const char * yybytes, int _yybytes_len ) { YY_BUFFER_STATE b; char *buf; yy_size_t n; int i; /* Get memory for full buffer, including space for trailing EOB's. */ n = (yy_size_t) (_yybytes_len + 2); buf = (char *) yyalloc( n ); if ( ! buf ) YY_FATAL_ERROR( "out of dynamic memory in yy_scan_bytes()" ); for ( i = 0; i < _yybytes_len; ++i ) buf[i] = yybytes[i]; buf[_yybytes_len] = buf[_yybytes_len+1] = YY_END_OF_BUFFER_CHAR; b = yy_scan_buffer( buf, n ); if ( ! b ) YY_FATAL_ERROR( "bad buffer in yy_scan_bytes()" ); /* It's okay to grow etc. this buffer, and we should throw it * away when we're done. */ b->yy_is_our_buffer = 1; return b; } static void yy_push_state (int _new_state ) { if ( (yy_start_stack_ptr) >= (yy_start_stack_depth) ) { yy_size_t new_size; (yy_start_stack_depth) += YY_START_STACK_INCR; new_size = (yy_size_t) (yy_start_stack_depth) * sizeof( int ); if ( ! (yy_start_stack) ) (yy_start_stack) = (int *) yyalloc( new_size ); else (yy_start_stack) = (int *) yyrealloc( (void *) (yy_start_stack), new_size ); if ( ! (yy_start_stack) ) YY_FATAL_ERROR( "out of memory expanding start-condition stack" ); } (yy_start_stack)[(yy_start_stack_ptr)++] = YY_START; BEGIN(_new_state); } static void yy_pop_state (void) { if ( --(yy_start_stack_ptr) < 0 ) YY_FATAL_ERROR( "start-condition stack underflow" ); BEGIN((yy_start_stack)[(yy_start_stack_ptr)]); } static int yy_top_state (void) { return (yy_start_stack)[(yy_start_stack_ptr) - 1]; } #ifndef YY_EXIT_FAILURE #define YY_EXIT_FAILURE 2 #endif static void yynoreturn yy_fatal_error (const char* msg ) { fprintf( stderr, "%s\n", msg ); exit( YY_EXIT_FAILURE ); } /* Redefine yyless() so it works in section 3 code. */ #undef yyless #define yyless(n) \ do \ { \ /* Undo effects of setting up yytext. */ \ int yyless_macro_arg = (n); \ YY_LESS_LINENO(yyless_macro_arg);\ yytext[yyleng] = (yy_hold_char); \ (yy_c_buf_p) = yytext + yyless_macro_arg; \ (yy_hold_char) = *(yy_c_buf_p); \ *(yy_c_buf_p) = '\0'; \ yyleng = yyless_macro_arg; \ } \ while ( 0 ) /* Accessor methods (get/set functions) to struct members. */ /** Get the current line number. * */ int yyget_lineno (void) { return yylineno; } /** Get the input stream. * */ FILE *yyget_in (void) { return yyin; } /** Get the output stream. * */ FILE *yyget_out (void) { return yyout; } /** Get the length of the current token. * */ int yyget_leng (void) { return yyleng; } /** Get the current token. * */ char *yyget_text (void) { return yytext; } /** Set the current line number. * @param _line_number line number * */ void yyset_lineno (int _line_number ) { yylineno = _line_number; } /** Set the input stream. This does not discard the current * input buffer. * @param _in_str A readable stream. * * @see yy_switch_to_buffer */ void yyset_in (FILE * _in_str ) { yyin = _in_str ; } void yyset_out (FILE * _out_str ) { yyout = _out_str ; } int yyget_debug (void) { return yy_flex_debug; } void yyset_debug (int _bdebug ) { yy_flex_debug = _bdebug ; } static int yy_init_globals (void) { /* Initialization is the same as for the non-reentrant scanner. * This function is called from yylex_destroy(), so don't allocate here. */ (yy_buffer_stack) = NULL; (yy_buffer_stack_top) = 0; (yy_buffer_stack_max) = 0; (yy_c_buf_p) = NULL; (yy_init) = 0; (yy_start) = 0; (yy_start_stack_ptr) = 0; (yy_start_stack_depth) = 0; (yy_start_stack) = NULL; /* Defined in main.c */ #ifdef YY_STDINIT yyin = stdin; yyout = stdout; #else yyin = NULL; yyout = NULL; #endif /* For future reference: Set errno on error, since we are called by * yylex_init() */ return 0; } /* yylex_destroy is for both reentrant and non-reentrant scanners. */ int yylex_destroy (void) { /* Pop the buffer stack, destroying each element. */ while(YY_CURRENT_BUFFER){ yy_delete_buffer( YY_CURRENT_BUFFER ); YY_CURRENT_BUFFER_LVALUE = NULL; yypop_buffer_state(); } /* Destroy the stack itself. */ yyfree((yy_buffer_stack) ); (yy_buffer_stack) = NULL; /* Destroy the start condition stack. */ yyfree( (yy_start_stack) ); (yy_start_stack) = NULL; /* Reset the globals. This is important in a non-reentrant scanner so the next time * yylex() is called, initialization will occur. */ yy_init_globals( ); return 0; } /* * Internal utility routines. */ #ifndef yytext_ptr static void yy_flex_strncpy (char* s1, const char * s2, int n ) { int i; for ( i = 0; i < n; ++i ) s1[i] = s2[i]; } #endif #ifdef YY_NEED_STRLEN static int yy_flex_strlen (const char * s ) { int n; for ( n = 0; s[n]; ++n ) ; return n; } #endif void *yyalloc (yy_size_t size ) { return malloc(size); } void *yyrealloc (void * ptr, yy_size_t size ) { /* The cast to (char *) in the following accommodates both * implementations that use char* generic pointers, and those * that use void* generic pointers. It works with the latter * because both ANSI C and C++ allow castless assignment from * any pointer type to void*, and deal with argument conversions * as though doing an assignment. */ return realloc(ptr, size); } void yyfree (void * ptr ) { free( (char *) ptr ); /* see yyrealloc() for (char *) cast */ } #define YYTABLES_NAME "yytables" #line 328 "VPreLex.l" void VPreLex::pushStateDefArg(int level) { // Enter define substitution argument state yy_push_state(ARGMODE); m_parenLevel = level; m_defValue = ""; } void VPreLex::pushStateDefForm() { // Enter define formal arguments state yy_push_state(DEFFPAR); // First is an optional ( to begin args m_parenLevel = 0; m_defValue = ""; } void VPreLex::pushStateDefValue() { // Enter define value state yy_push_state(DEFVAL); m_parenLevel = 0; m_defValue = ""; } void VPreLex::pushStateIncFilename() { // Enter include <> filename state yy_push_state(INCMODE); yymore(); } void VPreLex::debug(int level) { #ifdef FLEX_DEBUG yy_flex_debug=level; #endif } int VPreLex::debug() { #ifdef FLEX_DEBUG return yy_flex_debug; #else return 0; #endif } int VPreLex::lex() { VPreLex::s_currentLexp = this; // Tell parser where to get/put data m_tokFilelinep = curFilelinep(); // Remember token start location, may be updated by the lexer later return yylex(); } size_t VPreLex::inputToLex(char* buf, size_t max_size) { // We need a custom YY_INPUT because we can't use flex buffers. // Flex buffers are limited to 2GB, and we can't chop into 2G pieces // because buffers can't end in the middle of tokens. // Note if we switched streams here (which we don't) "buf" would be // become a stale invalid pointer. // VPreStream* streamp = curStreamp(); if (debug()>=10) { cout<<"- pp:inputToLex ITL s="< max_size) { yyerrorf("Output buffer too small for a `line"); } else { got = forceOut.length(); strncpy(buf, forceOut.c_str(), got); } } else { if (streamp->m_eof) { if (debug()) cout<<"- EOF\n"; } got = 0; // 0=EOF/EOS - although got was already 0. if (again) goto again; } } if (debug()>=10) { cout<<"- pp::inputToLex got="<m_eof) return ""; // Don't delete the final "EOF" stream bool exited_file = curStreamp()->m_file; if (!exited_file) { // Midpoint of stream, just change buffers delete curStreamp(); m_streampStack.pop(); // Must work as size>1; EOF is entry 0 againr = true; return ""; } // Multiple steps because we need FLEX to see ending \n and EOS to end // any illegal states, like an unterminated `protected region else if (!curStreamp()->m_termState) { // First shutdown phase for a file // Terminate all files with a newline. This prevents problems if // the user had a define without a terminating newline, // otherwise the resumed file's next line would get tacked on. // Also makes it likely the `line that changes files comes out // immediately. curStreamp()->m_termState = 1; return "\n"; // Exit old file } else if (curStreamp()->m_termState == 1) { // Now the EOF - can't be sent with other characters curStreamp()->m_termState = 2; return ""; // End of file } else if (curStreamp()->m_termState == 2) { // Now ending `line curStreamp()->m_termState = 3; return curFilelinep()->lineDirectiveStrg(2); // Exit old file } else { // Final shutdown phase for a stream, we can finally change the // current fileline to the new stream curStreamp()->m_termState = 0; VFileLine* filelinep = curFilelinep(); delete curStreamp(); m_streampStack.pop(); // Must work as size>1; EOF is entry 0 if (curStreamp()->m_eof) { // EOF doesn't have a "real" fileline, but a linenumber of 0 from init time // Inherit whatever we last parsed so it's more obvious. curFilelinep(filelinep); } // The caller parser remembered the start location for the text we are parsing, // but we've discovered there was a file switch along the way, so update it. m_tokFilelinep = curFilelinep(); // if (curStreamp()->m_eof) { return ""; } else { return curFilelinep()->lineDirectiveStrg(0); // Reenter resumed file } } } void VPreLex::initFirstBuffer(VFileLine* filelinep) { // Called from constructor to make first buffer // yy_create_buffer also sets yy_fill_buffer=1 so reads from YY_INPUT VPreStream* streamp = new VPreStream(filelinep, this); streamp->m_eof = true; m_streampStack.push(streamp); // m_bufferState = yy_create_buffer(NULL, YY_BUF_SIZE); yy_switch_to_buffer(m_bufferState); yyrestart(NULL); } void VPreLex::scanNewFile(VFileLine* filelinep) { // Called on new open file. scanBytesBack will be called next. if (streamDepth() > VPreProc::DEFINE_RECURSION_LEVEL_MAX) { // The recursive `include in VPreProcImp should trigger first yyerrorf("Recursive `define or other nested inclusion"); curStreamp()->m_eof = true; // Fake it to stop recursion } else { VPreStream* streamp = new VPreStream(filelinep, this); m_tokFilelinep = curFilelinep(); streamp->m_file = true; scanSwitchStream(streamp); } } void VPreLex::scanBytes(const string& str) { // Note buffers also appended in ::scanBytesBack // Not "m_buffers.push_front(string(strp,len))" as we need a `define // to take effect immediately, in the middle of the current buffer // Also we don't use scan_bytes that would set yy_fill_buffer // which would force Flex to bypass our YY_INPUT routine. if (streamDepth() > VPreProc::DEFINE_RECURSION_LEVEL_MAX) { // More streams if recursive `define with complex insertion // More buffers mostly if something internal goes funky yyerrorf("Recursive `define or other nested inclusion"); curStreamp()->m_eof = true; // Fake it to stop recursion } else { VPreStream* streamp = new VPreStream(curFilelinep(), this); streamp->m_buffers.push_front(str); scanSwitchStream(streamp); } } void VPreLex::scanSwitchStream(VPreStream* streamp) { curStreamp()->m_buffers.push_front(currentUnreadChars()); m_streampStack.push(streamp); yyrestart(NULL); } void VPreLex::scanBytesBack(const string& str) { // Initial creation, that will pull from YY_INPUT==inputToLex // Note buffers also appended in ::scanBytes if (curStreamp()->m_eof) yyerrorf("scanBytesBack without being under scanNewFile"); curStreamp()->m_buffers.push_back(str); } string VPreLex::currentUnreadChars() { // WARNING - Peeking at internals if (!currentBuffer()) return ""; ssize_t left = (yy_n_chars - (yy_c_buf_p - currentBuffer()->yy_ch_buf)); if (left > 0) { // left may be -1 at EOS *(yy_c_buf_p) = (yy_hold_char); return string(yy_c_buf_p, left); } else { return ""; } } YY_BUFFER_STATE VPreLex::currentBuffer() { return YY_CURRENT_BUFFER; } int VPreLex::currentStartState() { return YY_START; } void VPreLex::dumpSummary() { cout<<"- pp::dumpSummary curBuf="<<(void*)(currentBuffer()); #ifdef FLEX_DEBUG // Else peeking at internals may cause portability issues ssize_t left = (yy_n_chars - (yy_c_buf_p -currentBuffer()->yy_ch_buf)); cout<<" left="< tmpstack = LEXP->m_streampStack; while (!tmpstack.empty()) { VPreStream* streamp = tmpstack.top(); cout<<"- bufferStack["<<(void*)(streamp)<<"]: " <<" at="<m_curFilelinep <<" nBuf="<m_buffers.size() <<" size0="<<(streamp->m_buffers.empty() ? 0 : streamp->m_buffers.front().length()) <<(streamp->m_eof?" [EOF]":"") <<(streamp->m_file?" [FILE]":""); cout<) { # Fix xsubpp 1.9508 and GCC 4.2.1 warning # "warning: deprecated conversion from string constant to ‘char*’" $line =~ s/^(\s*)(?:const\s*|)char\*\s*file\s*=\s*__FILE__;/${1}char* file = (char*)__FILE__;/; if ($line =~ /newXSproto/) { $line =~ s/([(,]\s*)"/$1(char*)"/g; } # print "$line"; } Verilog-Perl-3.482/verilog/0000755000177100017500000000000014553624441015473 5ustar wsnyderwsnyderVerilog-Perl-3.482/verilog/parser_bugs.v0000644000177100017500000003137213536545407020210 0ustar wsnyderwsnyder// Not legal: // end : ADDRESS_TEST_BLOCK // See 9.8.1 // `define at EOF with no newline module bug26141 (); wire [0:3] b; wire a = b[2]; endmodule module bug26940 (); (* attribute *) assign q = {1'b0,a} +{1'b0,b}; adder u_add (.q(q),.a(d),.b(d)); initial begin # 1; q=0; if (q!=0) $stop; end endmodule module bug26968 (); reg [4:0] vect = 5'b10100; wire [4:0] tmp = { vect[0], vect[1], vect[2], vect[3], vect[4] }; initial begin #1 $display("vect=%b, tmp=%b", vect, tmp); end endmodule module bug26969 (input [31:0] ad, output [15:0] regff, input [31:0] read); bufif0 ad_drv [31:0] (ad, {16'b0, regff}, read); endmodule module bug26970; parameter A = 2'b1, B = 3'b0; parameter x = {B,B,B,A,A,B}; endmodule module bug26997; MUX_REG_8x8 PAGE_REG_B3 ( .CLK (CLK), /* .IN (DATA_RES[31:24]), .OUT (PAGE[31:24]), .EN_IN (EN_B3), .EN_OUT (PAGE_SEL), */ .TC (), .TD (), .TQ ()); endmodule module bug27013; submod u1(0); submod u2(1); endmodule module bug27036; reg [2:0] a_fifo_cam_indices[3:0], lt_fifo_cam_indices[5:0]; wire [2:0] db0_a_fifo_cam_indices = a_fifo_cam_indices[0]; endmodule module bug27037; reg mem[12:2]; reg [7:0] i; endmodule module bug27039; integer i; endmodule module bug27045( input clk, input reset, input [7:0] d, output reg [7:0] q ); parameter REG_DELAY = 0; always @(posedge clk or posedge reset) q <= #(REG_DELAY*2) d; endmodule module bug27062 (input D, output Q); p(Q, D); endmodule `timescale 1ns/1ns module bug27066; integer i; time t; realtime rt; function integer toint; input integer y; input [15:0] x; toint = x|y; endfunction endmodule module bug27067; initial $monitor( "%T %b %b %b", $time, clk1, clko1, clko2 ); initial forever @( negedge clk1 ) dclk1ff <= #50 ~ dclk1ff; endmodule module bug27072( output reg sum, input wire ci); endmodule `resetall module spec; specify specparam Tac = 0.1, Tcs = 0.2; if ( !B & !M ) ( posedge CLK => ( Q[0] : 1'bx )) = ( Tac, Tcs ); $width (negedge CLK &&& EN, Tac, 0, notif_clk); ( in1 => q ) = (3, 4); ( in1 +=> q ) = Tac; ( a, b, c *> q1, q2) = 10; ( s +*> q ) = Tcs; endspecify endmodule module bugevent; event e; initial ->e; always @ (e && e) $write("Legal\n"); endmodule module bugio (input [31:0] a, a2, output [15:0] o, o2, input ibit); endmodule module buglocal; always #(cyclehalf) begin clk <= ~clk; end always @(*) begin end initial force flag = 0; initial #(delta+0.5) CLRN <= 1; assign (weak0,weak1) VDD=1'b0; assign (weak0,weak1) VSS=1'b1; wire [71:0] #1 xxout = xxin; initial #1000_000 $finish; initial $display($time,,"Double commas are stupid"); initial for (counter[3:0] = 4'h0; counter[3:0] < limit[3:0]; counter[3:0] = counter[3:0] + 4'h1) $write(); always @(posedge(clk && !xclk) or negedge(clk && xclk) or reset) $write(); nmos # (PullTime, PullTime, 0) (PT,PU,1'b1); pulldown (strong0) pullinst (r); defparam x.y.z.PAR = 1; cdrv #5.0 clk(clk); initial PI = 3.1415926535_8979323846; always val = @ eventid 1'h1; always dly = # (2:3:4) 5'h6 ; wire \33escapeneeded = 1'b1; wire \33escapenewlineend = 1'b1; wire \noescapenewlineend = 1'b1; wire \noescapespaceend = 1'b1; endmodule module v2kparam #(parameter WIDTH = 1, parameter LENGTH = 1, LENGTH2 = 1) (output [WIDTH-1:0] myout, input [LENGTH-1:0] myin, myinb ); assign myout = myin ^ myinb ^ $callemptyparens(); endmodule module foreqn (in); input [1:0] in; reg a,b; reg [1:0] c; always for ({a,c[0]} = in; a < 1'b1; {b,c[1]} = in) begin end always for ({a,c[in]} = 0; a < 1'b1; {b,c[in]} = 2'b10) begin end endmodule module colonslash; always @* case (cond&4'b1110) 'h0://Error t = 7; 'h2:/*Another comment*/ t = 6; 'h4: t = 5; endcase endmodule module enums; enum {red, yellow, green} light; enum integer {IDLE, XX='x, S1='b01, S2='b10} state, next; enum {bronze=3, silver, gold} medal; enum { add=10, sub[5], jmp[6:8] } E1; typedef enum {NOPE, YUP} boolean; enum logic [1:0] {IDLE, DIR} STATE, NSTATE; endmodule module invec ( output logic novec, output logic [7:0] range, output logic [1:0] [7:0] arrayAndRange, output logic [2:0] [1:0] [7:0] arrayAndArrayAndRange, output reg signed novec2 ); endmodule module bug34575; wire a,b,c,d; assign #(0,0) a = 1; assign #(0:1:2) b = 1; assign #(0:1:2,0:1:2) c = 1; assign #(0:1:2,0) d = 1; endmodule module bug34649 (name); output reg name = 0; endmodule module bug34649b ( output reg name = 0 ); endmodule module bug10; initial begin x += 1; x -= 1; x /= 1; x *= 1; x |= 1; x ^= 1; x <<= 1; x >>= 1; x <<<= 1; x >>>= 1; y = x++; // Part of expression y = ++x; y = x--; y = --x; x++; // Statement ++x; x--; --x; end endmodule module bug33; integer i; initial begin unique case (i) endcase priority case (i) endcase if (i) begin end else begin end end endmodule module bug16; timeunit 0.1ns; timeprecision 1ns; endmodule parameter bug39 = 0; `default_nettype none `pragma foo = bar `default_nettype wire module bug64; parameter integer a=1,b=2; parameter real c=3.0; parameter realtime d=4.0; parameter time e=5.0; endmodule module bug166; assign {{o1,o2},o3,o4,{o5,o6}} = {{i1,i2},i3,i4,{i5,i6}}; endmodule module coverage20090318; task atask; begin end endtask endmodule module svsig; function int count (input logic [3:0] d); automatic int count = d[0]+d[1]+d[2]+d[3]; for (int i=0; i<4; i++) begin if (d[i]) count++; end return (count); endfunction task automatic autoconst; const int CONS = 8; $display("CONS=%x\n", CONS); $display("Another stmt\n"); endtask endmodule module bug_empty_func_param; //function int intfunc(int a=0, b=1); // return a+b; //endfunction always_comb begin foo = funccall(); foo = intfunc(a, b); foo = intfunc(a, .b(b)); foo = intfunc(.b(b), .a(a)); end endmodule module dotted_funcs; initial ram.dotTask(addr[31:0],ramdata); // Call task initial zz = ram.a.dotFunc(foo); // Call function endmodule module var_only_in_block; initial begin : named integer only_a_var_in_blk; end endmodule module v2k_vec_no_vec ( input [2:0] VEC, VEC2, // No direction, no port, no data type; inherits input NOVEC, // No direction, no data type; use `default_nettype input ARY [1:0], NOARY2, // Array doesn't inherit logic STILL_IN, // No direction, data type; inherits direction input logic TYPED // Logic type ); task t (input [2:0] FVEC, FVEC2, input NOVEC); begin end endtask endmodule module bugfor; initial for (a=0;a;) begin end endmodule module bug85 #(parameter type T_DATA = byte) (data); input T_DATA data; sub #(.T_DATA( T_DATA )) sub (.data(data)); endmodule module bugmodportcomma (,a,); input a; endmodule module bug168; initial $display("\nWarning! This is a\ string with a line\ continuation\ at time %0d PS", $time); endmodule module bug183 #(parameter NUM = 9 , WIDTH = 8 ) ( input logic [NUM-1:0][WIDTH-1:0] a , output logic [WIDTH-1:0] sum ); localparam NLOG = (NUM <= 2) ? 1 : (NUM <= 1024) ? 10 : 0; typedef logic [WIDTH-1:0] val_t; val_t [NLOG:0][NUM-1:0] tree; endmodule module bug192; covergroup cg192 @(posedge cclk); count_tag_busy: coverpoint countones_tag_busy { bins count[] = {[0:DEPTH]}; } endgroup: cg192 cg192 cover_ts = new(); // also bug361 endmodule function bit func_implied_in (bit i); g_bit = ~i; endfunction module sparam; specparam delay = 10; endmodule // bug221 sequence stable_before_s(sig, clks_before, clk, rst=1'b0); @(clk) !rst throughout(##1 $stable(sig)[*clks_before-1]); endsequence : stable_before_s property stable_window(sample, sig, clks_before, clks_after, clk=$default_clk ,rst=1'b0); @(clk) disable iff(rst) ## clks_before sample |-> stable_before_s(sig, clks_before, clk, rst).ended ##1 ($stable(sig)[*clks_after]); endproperty : stable_window property never(prop, clk=$default_clk , rst=1'b0); @(clk) disable iff(rst) not(prop); endproperty : never property recur_triggers(trig, n, cond, clk=$default_clk , rst=1'b0); @(clk) disable iff (rst) not ( !cond throughout (trig ##1 trig[->(n-1)]) ); endproperty : recur_triggers property data_transfer( start_ev, start_data, end_ev, end_data, clk=$default_clk ,rst=1'b0); logic [$bits(start_data)-1:0] local_data; @(clk) disable iff (rst) (start_ev, local_data = start_data) ##0 (end_ev or (!end_ev ##1 (!start_ev throughout end_ev[->1]))) |-> (local_data == end_data); endproperty : data_transfer module bug228; wire net1, net2, net3; nmos #(0:1:10, 0:1:10, 0:1:10) u (net1, net2, net3); endmodule module bug262 ( Y, {A1, A2} , B ); output Y; input A1, A2, B; endmodule wire \wire = bug282_must_keep_escape; module bug403_bug404; // Simulators vary as to if "(* /* */ )" is legal or not (* attr *) wire foo; always @ (*) begin end always @ (* ) begin end endmodule /* multi line bug459*/ module bug422; generate endgenerate endmodule module bug461; generate genvar g; // bug461 begin : topgen genvar g2; genvar g1; for (g=0; g<100; g++) begin end for (g=0; g<100; g++) begin end end for (g=0; g<100; g++) begin end endgenerate endmodule module bug507; integer x = 32'd 6; endmodule // bug_msg_887; bind path.to.example_mod example_mod_fcov uexample_mod_fcov (.*); package bug586_pkg; parameter B = 10; endpackage module non_bug586; // Verilator only input logic [bug586_pkg::B : 0] bvar; endmodule // bug_641 import "DPI-C" function bit mydpi_bug641(input a_dpi_input); // .f() in function call module fbug; initial a = f(, 1); initial a = f(.s(1), .j(2)); initial a = f(.s(), .j()); initial a = f(2); initial a = f(); endmodule parameter bug671 = 5 : 10 : 20 ; module bug256; always @(posedge clk) begin myreg1 <= # 100 7'd0; myreg1 <= # 100 'b0; myreg1 <= # 100'b0; // [#] [100] ['b0] myreg1 <= 100'b0; end endmodule module msg1491(A,B); output A; trireg (small) A; output trireg B; endmodule module msg2540 (output signed foo); endmodule module prot(); `protected I!#r#e6<_Q{{E2+]I3<[3s)1@D|'E''i!O?]jD>Jo_![Cl) #nj1]p,3^1~,="E@QZB\T)eU\pC#C|7=\$J$##A[@-@{Qk] `endprotected endmodule module prot2(); `pragma protect begin_protected `pragma protect encrypt_agent = "Whatever agent" `pragma protect encrypt_agent_info = "1.2.3" `pragma protect data_method = "aes128-cbc" `pragma protect key_keyowner = "Someone" `pragma protect key_keyname = "somekey", key_method = "rsa" `pragma protect key_block encoding = (enctype = "base64") wefjosdfjklajklasjkl `pragma protect data_block encoding = (enctype = "base64", bytes = 1059) I!#r#e6<_Q{{E2+]I3<[3s)1@D|'E''i!O?]jD>Jo_![Cl) #nj1]p,3^1~,="E@QZB\T)eU\pC#C|7=\$J$##A[@-@{Qk] `pragma protect end_protected `pragma reset protect endmodule module prot3(); //pragma protect begin_protected //pragma protect key_keyowner=Cadence Design Systems. //pragma protect key_keyname=CDS_KEY //pragma protect key_method=RC5 //pragma protect key_block zzZzZ/4ZzzZZZzzz4zZzZzZZZZzZzZ/Zz+33zZ2zz/zzzzzzzzZZZzZ4z+ZZZZz1 Z1ZzzzZZzZZzz9ZZZZ37zzZzZzZzzz9ZZzzZzZz9Zz64+z8Z7ZzZZZzzzzZZZzZz zzZzZZZzZ0463zzzzzZzZ6z00z4zZzzZZzzZzzzZZ8zzz09ZzZZZZZ== //pragma protect end_key_block //pragma protect digest_block ZzZZzzZ9ZZZZz2ZzzzZz/Zzzz8Z= //pragma protect end_digest_block //pragma protect data_block ZZZ8zZzz6ZZ/zZZ5zZZzzz3ZzzzZzZZZ6ZzZzZZZZZz1zzZZZZ7ZZZZz3Zzz+9zz 4zzz+8zZzzzzZzZZzzzZzz1Z7ZzZz+zZz8ZZZZzZ6ZzzZzZZzzZZzzZzzZzZzZzZ ZzzzzZ0zZz1ZzzZzzZzZzz== //pragma protect end_data_block //pragma protect digest_block Z4Z6zZzZ3Z7ZZ6zzZZZZzzzzZZZ= //pragma protect end_digest_block //pragma protect end_protected endmodule module bug1340; parameter B= 8 'b 1 ; endmodule module msg2931; nettype int net1_t; net1_t mynet1; nettype int net2_t with resolvefunc; net2_t mynet2; nettype net_t net3_t; net3_t mynet3; endmodule module bug1505; sub i_suba (); sub i_subb[1:2] (); sub i_subc[1:2][3:4][5:6] (); endmodule Verilog-Perl-3.482/verilog/v_hier_inc.vh0000644000177100017500000000042614030463163020131 0ustar wsnyderwsnyder// DESCRIPTION: Verilog-Perl: Example Verilog for testing package // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2000-2012 by Wilson Snyder. `ifndef V_HIER_INC_VH `define V_HIER_INC_VH // Guard `define hsub v_hier_sub `endif // Guard Verilog-Perl-3.482/verilog/inc_nonl.v0000644000177100017500000000011613234726611017454 0ustar wsnyderwsnyder// The lack of a newline on the next line is intentional blah-no-newline-here>Verilog-Perl-3.482/verilog/v_gate.v0000644000177100017500000000023013234726611017117 0ustar wsnyderwsnydermodule buffer ( output Z, input A); buf u_buf(Z, A); endmodule module gate ( output Z, input A); buffer u_buf(Z, A); endmodule Verilog-Perl-3.482/verilog/t_86_vhier_tick_sub.v0000644000177100017500000000031713234726611021520 0ustar wsnyderwsnyder// DESCRIPTION: Verilog::Preproc: Example source code // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2000-2012 by Wilson Snyder. module t_86_vhier_tick_sub; endmodule Verilog-Perl-3.482/verilog/inc2.v0000644000177100017500000000035113234726611016511 0ustar wsnyderwsnyder// DESCRIPTION: Verilog::Preproc: Example source code // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2000-2012 by Wilson Snyder. At file `__FILE__ line `__LINE__ `include Verilog-Perl-3.482/verilog/inc1.v0000644000177100017500000004662714030463163016523 0ustar wsnyderwsnyder// DESCRIPTION: Verilog::Preproc: Example source code // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2000-2012 by Wilson Snyder. text. //=========================================================================== // Includes //=========================================================================== // Defines `define DEF_A3 `define DEF_A1 // DEF_A0 set by command line wire [3:0] q = { `ifdef DEF_A3 1'b1 `else 1'b0 `endif , `ifdef DEF_A2 1'b1 `else 1'b0 `endif , `ifdef DEF_A1 1'b1 `else 1'b0 `endif , `ifdef DEF_A0 1'b1 `else 1'b0 `endif }; text. `define FOOBAR foo /*this */ bar /* this too */ `define FOOBAR2 foobar2 // but not `FOOBAR `FOOBAR2 `define MULTILINE first part \ second part \ third part `define MOREMULTILINE {\ a,\ b,\ c} /*******COMMENT*****/ `MULTILINE `MOREMULTILINE Line_Preproc_Check `__LINE__ //=========================================================================== `define syn_negedge_reset_l or negedge reset_l `define DEEP deep `define DEEPER `DEEP `DEEP `DEEPER `define nosubst NOT_SUBSTITUTED `define WITHTICK "`nosubst" "Inside: `nosubst" `WITHTICK `define withparam(a, b) a b LLZZ a b `withparam(x,y) `withparam(`withparam(p,q),`withparam ( r , s )) `withparam(firstline , comma","line) `define withquote(a, bar) a bar LLZZ "a" bar `withquote( x , y) // Simulators disagree here; some substitute "a" others do not `define noparam (a,b) `noparam(a,b) `define msg(x,y) `"x: `\`"y`\`"`" $display(`msg(left side, right side)) `define foo(f) f``_suffix `foo(bar) more `define zap(which) \ $c("Zap(\"",which,"\");"); `zap(bug1); `zap("bug2"); /* Define inside comment: `DEEPER and `WITHTICK */ // More commentary: `zap(bug1); `zap("bug2"); //====================================================================== // display passthru `define ls left_side `define rs right_side `define noarg na `define thru(x) x `define thruthru `ls `rs // Doesn't expand `define msg(x,y) `"x: `\`"y`\`"`" initial begin //$display(`msg( \`, \`)); // Illegal $display(`msg(pre `thru(thrupre `thru(thrumid) thrupost) post,right side)); $display(`msg(left side,right side)); $display(`msg( left side , right side )); $display(`msg( `ls , `rs )); $display(`msg( `noarg , `rs )); $display(`msg( prep ( midp1 `ls midp2 ( outp ) ) , `rs )); $display(`msg(`noarg,`noarg`noarg)); $display(`msg( `thruthru , `thruthru )); // Results vary between simulators $display(`msg(`thru(),)); // Empty $display(`msg(`thru(left side),`thru(right side))); $display(`msg( `thru( left side ) , `thru( right side ) )); $display(`"standalone`"); // Unspecified when the stringification has multiple lines `define twoline first \ second $display(`msg(twoline, `twoline)); //$display(`msg(left side, \ right side \ )); // Not sure \{space} is legal. $write("*-* All Finished *-*\n"); $finish; end endmodule //====================================================================== // rt.cpan.org bug34429 `define ADD_UP(a,c) \ wire tmp_``a = a; \ wire tmp_``c = tmp_``a + 1; \ assign c = tmp_``c ; module add1 ( input wire d1, output wire o1); `ADD_UP(d1,o1) // expansion is OK endmodule module add2 ( input wire d2, output wire o2); `ADD_UP( d2 , o2 ) // expansion is bad endmodule `define check(mod, width, flopname, gate, path) \ generate for (i=0; i<(width); i=i+1) begin \ psl cover { path.d[i] & ~path.q[i] & !path.cond & (gate)} report `"fondNoRise: mod.flopname`"; \ psl cover { ~path.d[i] & path.q[i] & !path.cond & (gate)} report `"fondNoFall: mod.flopname`"; \ end endgenerate // parameterized macro with arguments that are macros `define MK m5k.f `define MF `MK .ctl `define CK_fr (`MF.alive & `MF.alive_m1) `check(m5kc_fcl, 3, _ctl_mvldx_m1, `CK_fr, `MF._ctl_mvldx_m1) // ignorecmt //====================================================================== // Quotes are legal in protected blocks. Grr. module prot(); `protected I!#r#e6<_Q{{E2+]I3<[3s)1@D|'E''i!O?]jD>Jo_![Cl) #nj1]p,3^1~,="E@QZB\T)eU\pC#C|7=\$J$##A[@-@{Qk] `endprotected endmodule module prot2(); `pragma protect begin_protected `pragma protect encrypt_agent = "Whatever agent" `pragma protect encrypt_agent_info = "1.2.3" `pragma protect data_method = "aes128-cbc" `pragma protect key_keyowner = "Someone" `pragma protect key_keyname = "somekey", key_method = "rsa" `pragma protect key_block encoding = (enctype = "base64") wefjosdfjklajklasjkl `pragma protect data_block encoding = (enctype = "base64", bytes = 1059) I!#r#e6<_Q{{E2+]I3<[3s)1@D|'E''i!O?]jD>Jo_![Cl) #nj1]p,3^1~,="E@QZB\T)eU\pC#C|7=\$J$##A[@-@{Qk] `pragma protect end_protected `pragma reset protect endmodule module prot3(); //pragma protect begin_protected //pragma protect key_keyowner=Cadence Design Systems. //pragma protect key_keyname=CDS_KEY //pragma protect key_method=RC5 //pragma protect key_block zzZzZ/4ZzzZZZzzz4zZzZzZZZZzZzZ/Zz+33zZ2zz/zzzzzzzzZZZzZ4z+ZZZZz1 Z1ZzzzZZzZZzz9ZZZZ37zzZzZzZzzz9ZZzzZzZz9Zz64+z8Z7ZzZZZzzzzZZZzZz zzZzZZZzZ0463zzzzzZzZ6z00z4zZzzZZzzZzzzZZ8zzz09ZzZZZZZ== //pragma protect end_key_block //pragma protect digest_block ZzZZzzZ9ZZZZz2ZzzzZz/Zzzz8Z= //pragma protect end_digest_block //pragma protect data_block ZZZ8zZzz6ZZ/zZZ5zZZzzz3ZzzzZzZZZ6ZzZzZZZZZz1zzZZZZ7ZZZZz3Zzz+9zz 4zzz+8zZzzzzZzZZzzzZzz1Z7ZzZz+zZz8ZZZZzZ6ZzzZzZZzzZZzzZzzZzZzZzZ ZzzzzZ0zZz1ZzzZzzZzZzz== //pragma protect end_data_block //pragma protect digest_block Z4Z6zZzZ3Z7ZZ6zzZZZZzzzzZZZ= //pragma protect end_digest_block //pragma protect end_protected endmodule //====================================================================== // macro call with define that has comma `define REG_H 6 `define REG_L 7 `define _H regs[`REG_H] `define _L regs[`REG_L] `define _HL {`_H, `_L} `define EX_WRITE(ad, da) begin addr <= (ad); wdata <= (da); wr <= 1; end `define EX_READ(ad) begin addr <= (ad); rd <= 1; end `EX_READ((`_HL + 1)) and `EX_WRITE((`_HL), rdata) `EX_READ(`_HL + 1) `EX_WRITE(`_HL, rdata) more //====================================================================== // include of parameterized file `define INCNAME "t_preproc_inc4.vh" `include `INCNAME `ifndef T_PREPROC_INC4 `error "No Inc4" `endif `undef T_PREPROC_INC4 `ifdef NOT_DEFINED_INC `include NOT_DEFINED_INC `endif //====================================================================== // macro call with , in {} `define xxerror(logfile, msg) $blah(logfile,msg) `xxerror("ab,cd","e,f"); `xxerror(this.logfile, vec); `xxerror(this.logfile, vec[1,2,3]); `xxerror(this.logfile, {blah.name(), " is not foo"}); //====================================================================== // pragma/default net type `pragma foo = 1 `default_nettype none `default_nettype uwire //====================================================================== // Ifdef `define EMPTY_TRUE `ifndef EMPTY_TRUE `error "Empty is still true" `endif Line_Preproc_Check `__LINE__ //====================================================================== // bug84 `define ARGPAR(a, // Hello, comments MIGHT not be legal /*more,,)cmts*/ b // But newlines ARE legal... who speced THAT? ) (a,b) `ARGPAR(p,q) `ARGPAR( //Here x, y //Too ) Line_Preproc_Check `__LINE__ //====================================================================== // defines split arguments `define BEGIN begin `define END end `define BEGINEND `BEGIN`END `define quoteit(x) `"x`" `BEGIN`END // 2001 spec doesn't require two tokens, so "beginend" ok `BEGINEND // 2001 spec doesn't require two tokens, so "beginend" ok `quoteit(`BEGIN`END) // No space "beginend" //====================================================================== // bug106 `define \esc`def got_escaped `ifdef \esc`def `\esc`def `endif Not a \`define //====================================================================== // misparsed comma in submacro `define sb bee `define appease_emacs_paren_matcher ( `define sa(l) x,y) `define sfoo(q,r) q--r `sfoo(`sa(el),`sb) submacro has comma paren //====================================================================== // bug191 `define bug191(bits) $display("bits %d %d", $bits(foo), bits); `bug191(10) //====================================================================== // 1800-2009 `define UDALL `ifndef PREDEF_COMMAND_LINE `error "Test setup error, PREDEF_COMMAND_LINE pre-missing" `endif `undefineall `ifdef UDALL `error "undefineall failed" `endif `ifndef PREDEF_COMMAND_LINE `error "Deleted too much, no PREDEF_COMMAND_LINE" `endif //====================================================================== // bug202 `define FC_INV3(out, in) \ `ifdef DC \ cell \inv_``out <$typeof(out)> (.a(), .o()); \ /* multi-line comment \ multi-line comment */ \ `else \ `ifdef MACRO_ATTRIBUTE \ (* macro_attribute = `"INV (out``,in``)`" *) \ `endif \ assign out = ~in ; \ `endif `FC_INV3(a3,b3) `define /* multi \ line1*/ \ bug202( i /*multi \ line2*/ \ ) \ /* multi \ line 3*/ \ def i \ `bug202(foo) //====================================================================== `define CMT1 // verilator NOT IN DEFINE `define CMT2 /* verilator PART OF DEFINE */ `define CMT3 /* verilator NOT PART OF DEFINE */ `define CMT4 /* verilator PART \ OF DEFINE */ `define CMT5 // CMT NOT \ also in // BUT TEXT IS \ also3 // CMT NOT 1 `CMT1 (nodef) 2 `CMT2 (hasdef) 3 `CMT3 (nodef) 4 `CMT4 (nodef) 5 `CMT5 (nodef) `define NL HAS a NEW \ LINE `NL //====================================================================== `define msg_fatal(log, msg) \ do \ /* synopsys translate_off */ \ `ifdef NEVER \ `error "WTF" \ `else \ if (start(`__FILE__, `__LINE__)) begin \ `endif \ message(msg); \ end \ /* synopsys translate_on */ \ while(0) `define msg_scen_(cl) cl``_scen `define MSG_MACRO_TO_STRING(x) `"x`" EXP: clxx_scen `msg_scen_(clxx) EXP: clxx_scen `MSG_MACRO_TO_STRING(`msg_scen_(clxx)) `define mf(clx) `msg_fatal(this.log, {"Blah-", `MSG_MACRO_TO_STRING(`msg_scen_(clx)), " end"}); EXP: do if (start("verilog/inc1.v", 25)) begin message({"Blah-", "clx_scen", " end"}); end while(0); `mf(clx) //====================================================================== `define makedefine(name) \ `define def_``name This is name \ `define def_``name``_2 This is name``_2 \ `makedefine(fooed) `ifndef def_fooed `error "No def_fooed" `endif //`ifndef def_fooed_2 `error "No def_fooed_2" `endif EXP: This is fooed `def_fooed EXP: This is fooed_2 `def_fooed_2 //====================================================================== `define NOPARAM() np `NOPARAM() `NOPARAM( ) //====================================================================== // It's unclear if the spec allows this; is text_macro_idenitfier before or after substitution? `define NODS_DEFINED `define NODS_INDIRECT(x) x `ifndef `NODS_INDIRECT(NODS_DEFINED) `error "Indirect failed" `endif `ifdef `NODS_INDIRECT(NODS_UNDEFINED) `error "Indirect2 failed" `endif //====================================================================== // Metaprogramming `define REPEAT_0(d) `define REPEAT_1(d) d `define REPEAT_2(d) `REPEAT_1(d)d `define REPEAT_3(d) `REPEAT_2(d)d `define REPEAT_4(d) `REPEAT_3(d)d `define CONCAT(a, b) a``b `define REPEATC(n, d) `CONCAT(`REPEAT_, n)(d) `define REPEATT(n, d) `REPEAT_``n(d) `REPEATC(3, hello3 ) `REPEATT(4, hello4 ) //====================================================================== // Include from stringification `undef T_PREPROC_INC4 `define NODS_CONC_VH(m) `"m.vh`" `include `NODS_CONC_VH(t_preproc_inc4) `ifndef T_PREPROC_INC4 `error_here `endif //====================================================================== // Defines doing defines // Note the newline on the end - required to form the end of a define `define DEFINEIT(d) d \ `define _DEFIF_Z_0 1 `define DEFIF_NZ(d,n) `undef d `ifndef _DEFIF_Z_``n `DEFINEIT(`define d 1) `endif `DEFIF_NZ(TEMP,1) `ifndef TEMP `error "bad1" `endif `DEFIF_NZ(TEMP,0) `ifdef TEMP `error "bad0" `endif Line_Preproc_Check `__LINE__ //====================================================================== // Quoted multiline - track line numbers, and insure \\n gets propagated `define MULQUOTE "FOO \ BAR " `define MULQUOTE2(mq) `MULQUOTE mq `MULQUOTE Line_Preproc_Check `__LINE__ `MULQUOTE2("arg_line1 \ arg_line2") Line_Preproc_Check `__LINE__ //====================================================================== // bug283 `define A a `define B b `define C c // EXP: abc `define C5 `A``b```C `C5 `undef A `undef B `undef C `define XTYPE sonet `define XJOIN(__arg1, __arg2) __arg1``__arg2 `define XACTION `XJOIN(`XTYPE, _frame) EXP: sonet_frame `XACTION // `define XFRAME frame `define XACTION2 `XJOIN(sonet_, `XFRAME) EXP: sonet_frame `XACTION2 // This result varies between simulators `define sonet_frame other_frame `define XACTION3 `XTYPE``_frame EXP: sonet_frame `XACTION3 // The existance of non-existance of a base define can make a difference `define QA_b zzz `define Q1 `QA``_b EXP: module zzz ; endmodule module `Q1 ; endmodule module `Q1 ; endmodule `define QA a EXP: module a_b ; endmodule module `Q1 ; endmodule module `Q1 ; endmodule //====================================================================== // bug311 integer/*NEED_SPACE*/foo; //====================================================================== synth_test: // synopsys translate_off synthesis_turned_off // synthesis translate_on EXP: on //====================================================================== // bug441 module t; //----- // case provided // note this does NOT escape as suggested in the mail `define LEX_CAT(lexem1, lexem2) lexem1``lexem2 `define LEX_ESC(name) \name \ initial begin : `LEX_ESC( `LEX_CAT(a[0],_assignment) ) $write("GOT%%m='%m' EXP='%s'\n", "t.\\`LEX_CAT(a[0],_assignment) "); end //----- // SHOULD(simulator-dependant): Backslash doesn't prevent arguments from // substituting and the \ staying in the expansion // Note space after name is important so when substitute it has ending whitespace `define ESC_CAT(name,name2) \name``_assignment_``name2 \ initial begin : `ESC_CAT( a[0],a[1] ) $write("GOT%%m='%m' EXP='%s'\n", "t.\\a[0]_assignment_a[1] "); end `undef ESC_CAT //----- `define CAT(a,b) a``b `define ESC(name) \`CAT(name,suffix) // RULE: Ignoring backslash does NOT allow an additional expansion level // (Because ESC gets expanded then the \ has it's normal escape meaning) initial begin : `ESC(pp) $write("GOT%%m='%m' EXP='%s'\n", "t.\\`CAT(pp,suffix) "); end `undef CAT `undef ESC //----- `define CAT(a,b) a``b `define ESC(name) \name \ // Similar to above; \ does not allow expansion after substitution initial begin : `ESC( `CAT(ff,bb) ) $write("GOT%%m='%m' EXP='%s'\n", "t.\\`CAT(ff,bb) "); end `undef CAT `undef ESC //----- `define ESC(name) \name \ // MUST: Unknown macro with backslash escape stays as escaped symbol name initial begin : `ESC( `zzz ) $write("GOT%%m='%m' EXP='%s'\n", "t.\\`zzz "); end `undef ESC //----- `define FOO bar `define ESC(name) \name \ // SHOULD(simulator-dependant): Known macro with backslash escape expands initial begin : `ESC( `FOO ) $write("GOT%%m='%m' OTHER_EXP='%s'\n OUR_EXP='%s'", "t.bar ","t.\\`FOO "); end // SHOULD(simulator-dependant): Prefix breaks the above initial begin : `ESC( xx`FOO ) $write("GOT%%m='%m' EXP='%s'\n", "t.\\xx`FOO "); end `undef FOO `undef ESC //----- // MUST: Unknown macro not under call with backslash escape doesn't expand `undef UNKNOWN initial begin : \`UNKNOWN $write("GOT%%m='%m' EXP='%s'\n", "t.\\`UNKNOWN "); end //----- // MUST: Unknown macro not under call doesn't expand `define DEF_NO_EXPAND error_dont_expand initial begin : \`DEF_NO_EXPAND $write("GOT%%m='%m' EXP='%s'\n", "t.\\`DEF_NO_EXPAND "); end `undef DEF_NO_EXPAND //----- // bug441 derivative // SHOULD(simulator-dependant): Quotes doesn't prevent arguments from expanding (like backslashes above) `define STR(name) "foo name baz" initial $write("GOT='%s' EXP='%s'\n", `STR(bar), "foo bar baz"); `undef STR //----- // RULE: Because there are quotes after substituting STR, the `A does NOT expand `define STR(name) "foo name baz" `define A(name) boo name hiss initial $write("GOT='%s' EXP='%s'\n", `STR(`A(bar)), "foo `A(bar) baz"); `undef A `undef STR //---- // bug845 `define SLASHED "1//2.3" initial $write("Slashed=`%s'\n", `SLASHED); //---- // bug915 `define BUG915(a,b,c) \ $display("%s%s",a,`"b``c``\n`") initial `BUG915("a1",b2,c3); endmodule //====================================================================== //bug1225 `define X_ITEM(SUB,UNIT) `X_STRING(SUB``UNIT) `define X_STRING(A) `"A`" $display(`X_ITEM(RAM,0)); $display(`X_ITEM(CPU,)); `define EMPTY `define EMPTYP(foo) `define SOME some `define SOMEP(foo) foo `define XXE_FAMILY XXE_```EMPTY XXE_FAMILY = `XXE_FAMILY `define XXE_```EMPTY `ifdef XXE_ $display("XXE_ is defined"); `endif `define XYE_FAMILY XYE_```EMPTYP(foo) XYE_FAMILY = `XYE_FAMILY `define XYE_```EMPTYP(foo) `ifdef XYE_ $display("XYE_ is defined"); `endif `define XXS_FAMILY XXS_```SOME XXS_FAMILY = `XXS_FAMILY `define XXS_```SOME `ifdef XXS_some $display("XXS_some is defined"); `endif `define XYS_FAMILY XYS_```SOMEP(foo) XYS_FAMILY = `XYS_FAMILY `define XYS_```SOMEP(foo) `ifdef XYS_foo $display("XYS_foo is defined"); `endif //==== `ifdef NEVER `define NXE_FAMILY NXE_```EMPTY NXE_FAMILY = `NXE_FAMILY `define NXE_```EMPTY `ifdef NXE_ $display("NXE_ is defined"); `endif `define NYE_FAMILY NYE_```EMPTYP(foo) NYE_FAMILY = `NYE_FAMILY `define NYE_```EMPTYP(foo) `ifdef NYE_ $display("NYE_ is defined"); `endif `define NXS_FAMILY NXS_```SOME NXS_FAMILY = `NXS_FAMILY `define NXS_```SOME `ifdef NXS_some $display("NXS_some is defined"); `endif `define NYS_FAMILY NYS_```SOMEP(foo) NYS_FAMILY = `NYS_FAMILY `define NYS_```SOMEP(foo) `ifdef NYS_foo $display("NYS_foo is defined"); `endif `include `EMPTY `endif // NEVER //bug1227 `define INSTANCE(NAME) (.mySig (myInterface.``NAME), `INSTANCE(pa5) //====================================================================== // Stringify bug `define hack(GRP) `dbg_hdl(UVM_LOW, (`"Functional coverage enabled: GRP`")); `hack(paramgrp) `define dbg_hdl(LVL, MSG) $display ("DEBUG : %s [%m]", $sformatf MSG) `define svfcov_new(GRP) \ initial do begin `dbg_hdl(UVM_LOW, (`"Functional coverage enabled: GRP`")); end while(0) `define simple_svfcov_clk(LBL, CLK, RST, ARG) \ covergroup LBL @(posedge CLK); \ c: coverpoint ARG iff ((RST) === 1'b1); endgroup \ LBL u_``LBL; `svfcov_new(u_``LBL) module pcc2_cfg; generate `simple_svfcov_clk(a, b, c, d); endgenerate endmodule //====================================================================== // Verilog-Perl bug1668 `define stringify(text) `"text`" `stringify(`NOT_DEFINED_STR) //====================================================================== // IEEE mandated predefines `undefineall // undefineall should have no effect on these predef `SV_COV_START 0 predef `SV_COV_STOP 1 predef `SV_COV_RESET 2 predef `SV_COV_CHECK 3 predef `SV_COV_MODULE 10 predef `SV_COV_HIER 11 predef `SV_COV_ASSERTION 20 predef `SV_COV_FSM_STATE 21 predef `SV_COV_STATEMENT 22 predef `SV_COV_TOGGLE 23 predef `SV_COV_OVERFLOW -2 predef `SV_COV_ERROR -1 predef `SV_COV_NOCOV 0 predef `SV_COV_OK 1 predef `SV_COV_PARTIAL 2 Verilog-Perl-3.482/verilog/v_sv_pgm.v0000644000177100017500000000034113234726611017475 0ustar wsnyderwsnyder// DESCRIPTION: Verilog-Perl: Example Verilog for testing package // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2009-2012 by Wilson Snyder. program v_sv_pgm; int in_pgm; endprogram Verilog-Perl-3.482/verilog/pli.v0000644000177100017500000000207313234726611016445 0ustar wsnyderwsnyder// DESCRIPTION: Example pli file for vpassert program // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2000-2012 by Wilson Snyder. `timescale 1ns/1ns module pli; // A module called PLI is required, to contain the error counts // This is required with the vpassert --nostop option, which this example uses // By default (--stop), this file isn't needed at all integer errors; initial errors = 0; integer warnings; initial warnings = 0; // Normally this would be 0 at startup, then become 1 after reset deasserts // This prevents false assertion checks during reset integer message_on; initial message_on = 1; always @ (errors or warnings) begin `ifdef OPTIONAL_EXIT_ON_WARNING if (errors!=0 || warnings!=0) begin $uinfo (0, "Errors/warnings found, exiting!\n"); $finish; end `else if (errors!=0) begin $uinfo (0, "Errors found, exiting!\n"); $finish; end else if (warnings!=0) begin $uinfo (0, {"Warnings found, ","consider stopping!\n"}); end `endif end endmodule Verilog-Perl-3.482/verilog/parser_sv09.v0000644000177100017500000000247213264012701020030 0ustar wsnyderwsnyder// 1800-2009 mantis1769 module mantis1769 #(N=1); if (N < 1) $error("Bad N value %d", N); endmodule // 1800-2009 mantis1134 module mantis1134_decoder #(BITS = 3, localparam OUT_BITS = 1 << BITS) (input [BITS-1:0] A, output reg [OUT_BITS-1:0] Y); assign Y = 1 << A; endmodule // 1800-2009 mantis907 module mantis907_default_parameter #(REQUIRED); endmodule module mantis1619_default_input (input integer deflt = 10); endmodule module global_anal; // Don't be anal about "global" in old code integer global = 1; global clocking z @(posedge clk); // But still get it right endclocking endmodule module bug400; assert property ( @(posedge clk) disable iff (rst || $past (rst,1,,@(posedge clk)) || $isunknown(rst)) "assert 0"); endmodule // dobbie package pkga; endpackage package pkgb; endpackage module impbegin import pkga::*; import pkgb::*; (input foobar); endmodule // msg2546 module def_cov_point; logic [7:0] data; logic [7:0] addr; covergroup c; ADDRESS : coverpoint addr { bins low[] = {[0:10]}; bins med[] = {[11:20]}; } endgroup // Can't handle this due to package parsing yaID__ETC //covergroup d; // d : coverpoint data { // bins low[] = {[0:10]}; // bins med[] = {[11:20]}; // } //endgroup endmodule Verilog-Perl-3.482/verilog/v_comments.v0000644000177100017500000000145513234726611020036 0ustar wsnyderwsnyder`define ThirtyTwo 32 module v_comments ( a, // Pragma for a b, // pragma for b c, d, d1, d2, d3 ); input a; // comment for a inout [10:0] b; output [0:10] c; // comment for c output [ ((2*`ThirtyTwo) - 1) : 0 ] d; output [ `ThirtyTwo : 0 ] d1; output [ ( MATH - 1 ): 0 ] d2; output [ `ThirtyTwo - 1: 0 ] d3; reg d; reg [11:0] e; // Comment for e endmodule // 'Third' below must attach to 'b' becase there's no ) or , after b. module v_bug917 // modcmt (input wire a, // a-First output wire m // m-Second , output wire b // b-Third ); // Third endmodule module v_bug917p (input wire a, // a-First output wire b); // b-Secondparen // Third endmodule Verilog-Perl-3.482/verilog/v_hier_top.v0000644000177100017500000000173514030463163020016 0ustar wsnyderwsnyder// DESCRIPTION: Verilog-Perl: Example Verilog for testing package // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2000-2012 by Wilson Snyder. `include "v_hier_inc.vh" module v_hier_top (/*AUTOARG*/ // Inputs clk ); input clk; /* pragma jsc_clk */ defparam sub.FROM_DEFPARAM = 2; `hsub sub (/*AUTOINST*/ // Outputs .qvec (qvec[3:0]), // Inputs .avec ({avec[3],avec[2:0]}), .clk (1'b0)); missing missing (); v_recursive #(.DEPTH(3)) recursive (); // Width checks, bug65 wire WC_w1; wire [0:0] WC_w1b; wire [2:0] WC_w3; wire [-1:2] WC_w4; localparam WC_p32=0; localparam [0:0] WC_p1=0; localparam [2:0] WC_p3=0; localparam [-1:2] WC_p4=0; localparam integer WC_pint=0; // Assignments wire asn_clk; assign asn_clk = clk; endmodule localparam GLOBAL_PARAM = 1; // Local Variables: // eval:(verilog-read-defines) // End: Verilog-Perl-3.482/verilog/parser_vectors.v0000644000177100017500000000214013234726611020715 0ustar wsnyderwsnyder/* This file contains some instantiations of an unknown module that use bit vectors. */ module top(i,o); input [31:0] i; output [31:0] o; wire [3:0] somebus, someotherbus; wire somenet_1,somenet_2,somenet_3; wire [29:0] somewidebus; parameter SOMEPARAM = 10; assign somewidebus=i[31:2]; assign o[1]=somenet_1; assign o[2]=somenet_2; assign o[0]=1'b0; assign o[3]=someotherbus[2]; assign o[28:4]=25'b0; assign o[31]=~somenet_1; mod instmod_1 ( .a(somebus), .y(somenet_1) ); mod instmod_2 ( .a(somebus), .y(someotherbus[2]) ); mod instmod_3 ( .a(somewidebus[24:21]), .y(somenet_2) ); mod instmod_4 ( .a(i[31:27]), .y(o[29]) ); mod instmod_5 ( .a({somenet_1,3'b101,someotherbus[2],somewidebus[2:1]}), .y(o[30]) ); mod instmod_6 ( .a({somenet_1,3'b101,{someotherbus[2],someotherbus[2]},somewidebus[2:1]}), .y(o[30]) ); mod instmod_7 ( .a(somebus[{SOMEPARAM_3[1],SOMEPARAM_3[0]}]), .y(someotherbus[2]) ); endmodule Verilog-Perl-3.482/verilog/v_hier_subprim.v0000644000177100017500000000106513234726611020676 0ustar wsnyderwsnyder// DESCRIPTION: Verilog-Perl: Example Verilog for testing package // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2000-2012 by Wilson Snyder. // surefire lint_off UDPUNS primitive v_hier_prim (/*AUTOARG*/ // Outputs q, // Inputs a ); output q; input a; table 0 : 1; 1 : 0; endtable endprimitive `celldefine module bug27070(); `define W 4 parameter TAP = `W'b1001; endmodule `endcelldefine `celldefine module bug893(); reg r; initial r <=#1 '0; endmodule `endcelldefine Verilog-Perl-3.482/verilog/parser_sv17.v0000644000177100017500000000023114020733063020020 0ustar wsnyderwsnyder// 1800-2017 module sv17; integer i; initial begin for (i=0;;) break; for (;i!=0;) begin end for (;;++i) break; end endmodule Verilog-Perl-3.482/verilog/t_80_foo.f0000644000177100017500000000005513234726611017254 0ustar wsnyderwsnyderverilog/t_80_foo.v -F verilog/t_80_bar/bar.f Verilog-Perl-3.482/verilog/test.v0000644000177100017500000000074214030463163016634 0ustar wsnyderwsnyder// DESCRIPTION: Verilog-Perl: Example Verilog for testing package // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2000-2012 by Wilson Snyder. // ENCRYPT_ME module example (/*AUTOARG*/ // Outputs z, // Inputs a, b ); // See https://www.veripool.org // for what AUTOARG and friends can do for you! /*Comment // test*/ // input a; input b; output z; wire result = a|b; wire z = result; endmodule Verilog-Perl-3.482/verilog/t_80_bar/0000755000177100017500000000000014553624441017071 5ustar wsnyderwsnyderVerilog-Perl-3.482/verilog/t_80_bar/bar.f0000644000177100017500000000000613234726611017775 0ustar wsnyderwsnyderbar.v Verilog-Perl-3.482/verilog/t_80_bar/bar.v0000644000177100017500000000042713234726611020024 0ustar wsnyderwsnyder// DESCRIPTION: Verilog::Preproc: Example source code // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012-2012 by Wilson Snyder. // // Test -F option in vppreproc. module bar(output wire y, input wire x); assign y = x; endmodule // bar Verilog-Perl-3.482/verilog/v_hier_sub.v0000644000177100017500000000163013234726611020004 0ustar wsnyderwsnyder// DESCRIPTION: Verilog-Perl: Example Verilog for testing package // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2000-2012 by Wilson Snyder. module v_hier_sub (/*AUTOARG*/ input clk, input [3:0] avec, // Comment for v_hier_sub, avec output [3:0] qvec /* Comment for v_hier_sub, qvec */ ); parameter FROM_DEFPARAM = 1; supply1 a1; v_hier_subsub #( .IGNORED('sh20) ) \subsub0 ( // Outputs .q (qvec[0]), // Inputs .a (a1)); // Comment for subsub cell generate genvar K, K_UNUSED; for (K=0; K<1; K=K+1) begin : genloop // By pin position, inside generate v_hier_subsub subsub2 (qvec[2], 1'b0); end endgenerate function foo; (* attribute *) /* synopsys metacommenttest */ input not_part_of_pinlist; foo = not_part_of_pinlist; endfunction endmodule Verilog-Perl-3.482/verilog/t_86_vhier_tick.v0000644000177100017500000000043413234726611020647 0ustar wsnyderwsnyder// DESCRIPTION: Verilog::Preproc: Example source code // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2000-2012 by Wilson Snyder. module t_86_vhier_tick; `define t_86_vhier_tick_sub FOOBAR_NOT_FOUND t_86_vhier_tick_sub sub (); endmodule Verilog-Perl-3.482/verilog/v_v2k.v0000644000177100017500000000113013234726611016701 0ustar wsnyderwsnyder// DESCRIPTION: Verilog-Perl: Example Verilog for testing package // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2006-2012 by Wilson Snyder. module v_v2k #(parameter WIDTH = 16) ( input clk, input rst, input [WIDTH:0] sig1, output reg [WIDTH:0] sig2 ); always @(clk) begin if (rst) begin sig2 <= #1 0; end else begin sig2 <= #1 sig1; end end // Multidim, bug1206 wire [1:2] [3:4] netmd; v_v2k_sub sub (.net1 (netmd[1])); endmodule module v_v2k_sub ( input [3:4] net1 ); endmodule Verilog-Perl-3.482/verilog/t_preproc_inc3.vh0000644000177100017500000000070213234726611020737 0ustar wsnyderwsnyder`line 2 "inc3_a_filename_from_line_directive" 0 // DESCRIPTION: Verilog::Preproc: Example source code // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2000-2012 by Wilson Snyder. `ifndef _EXAMPLE_INC2_V_ `define _EXAMPLE_INC2_V_ 1 `define _EMPTY // FOO At file `__FILE__ line `__LINE__ `else `error "INC2 File already included once" `endif // guard `ifdef not_defined `include "NotToBeInced.v" `endif Verilog-Perl-3.482/verilog/v_hier_noport.v0000644000177100017500000000036613422450702020533 0ustar wsnyderwsnyder// DESCRIPTION: Verilog-Perl: Example Verilog for testing package // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2000-2012 by Wilson Snyder. module v_hier_noport; parameter P; reg internal; endmodule Verilog-Perl-3.482/verilog/t_preproc_inc4.vh0000644000177100017500000000030013234726611020732 0ustar wsnyderwsnyder// DESCRIPTION: Verilog::Preproc: Example source code // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2000-2012 by Wilson Snyder. `define T_PREPROC_INC4 Verilog-Perl-3.482/verilog/v_sv_mod.v0000644000177100017500000000072713234726611017501 0ustar wsnyderwsnyder// DESCRIPTION: Verilog-Perl: Example Verilog for testing package // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2009-2012 by Wilson Snyder. `include "v_sv_pkg" interface sv_if_ported (input clk); endinterface module v_sv_mod (v_sv_intf intf, input clk); // Import types import v_sv_pkg::*; // Internal interface (unconnected) sv_if_ported if_ported(.clk(clk)); // Grab a program v_sv_pgm pgm(); endmodule Verilog-Perl-3.482/verilog/v_sv_intf.v0000644000177100017500000000062713234726611017661 0ustar wsnyderwsnyder// DESCRIPTION: Verilog-Perl: Example Verilog for testing package // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2009-2012 by Wilson Snyder. `include "v_sv_pkg.v" interface v_sv_intf; v_sv_pkg::byte_t byte_port; v_sv_intf2 subintf(.*); endinterface interface v_sv_intf2; v_sv_pkg::byte_t byte_port; modport Master(input data, output addr); endinterface Verilog-Perl-3.482/verilog/inc_def09.v0000644000177100017500000000341413234726611017421 0ustar wsnyderwsnyder// DESCRIPTION: Verilog-Perl: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2009 by Wilson Snyder. `undefineall // Definitions as speced // Note there are trailing spaces, which spec doesn't show properly `define D(x,y) initial $display("start", x , y, "end"); '`D( "msg1" , "msg2" )' 'initial $display("start", "msg1" , "msg2" , "end");' '`D( " msg1", )' 'initial $display("start", " msg1" , , "end");' '`D(, "msg2 ")' 'initial $display("start", , "msg2 ", "end");' '`D(,)' 'initial $display("start", , , "end");' '`D( , )' 'initial $display("start", , , "end");' //`D("msg1") // ILLEGAL: only one argument //`D() // ILLEGAL: only one empty argument //`D(,,) // ILLEGAL: more actual than formal arguments // Defaults: `define MACRO1(a=5,b="B",c) $display(a,,b,,c); '`MACRO1 ( , 2, 3 )' '$display(5,,2,,3);' '`MACRO1 ( 1 , , 3 )' '$display(1 ,,"B",,3 );' '`MACRO1 ( , 2, )' '$display(5,,2,,);' //`MACRO1 ( 1 ) // ILLEGAL: b and c omitted, no default for c `define MACRO2(a=5, b, c="C") $display(a,,b,,c); '`MACRO2 (1, , 3)' '$display(5,,,,"C");' '`MACRO2 (, 2, )' '$display(5,,2,,"C");' '`MACRO2 (, 2)' '$display(5,,2,,"C");' `define MACRO3(a=5, b=0, c="C") $display(a,,b,,c); '`MACRO3 ( 1 )' '$display(1 ,,0,,"C");' '`MACRO3 ( )' '$display(5,,0,,"C");' //`MACRO3 // ILLEGAL: parentheses required `define DTOP(a,b) a + b '`DTOP( `DTOP(b,1), `DTOP(42,a) )' 'b + 1 + 42 + a' // Local tests `define MACROQUOTE(a="==)",b="((((",c=() ) 'a b c' `MACROQUOTE(); '"==)" "((((" () '; // Also check our line counting doesn't go bad `define MACROPAREN(a=(6), b=(eq=al), c) 'a b c' `MACROPAREN( ,, ZOT) HERE-`__LINE__ - Line71 //====================================================================== Verilog-Perl-3.482/verilog/v_hier_top2.v0000644000177100017500000000104513422450702020071 0ustar wsnyderwsnyder// DESCRIPTION: Verilog-Perl: Example Verilog for testing package // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2000-2012 by Wilson Snyder. module v_hier_top2 (/*AUTOARG*/ // Inputs clk ); input clk; v_hier_noport noport (); v_hier_noport #(.P(1)) noportp (); //bug1393 v_hier_noport #(.P(1)) noporta[1:0] (); inout [2:0] iosig/* synthesis useioff = 1 //*synthesis fpga_attr = "BLAH=ON"//* synthesis fpga_pin = "A22"*/;/* synthesis aftersemi*/ // NetListName=F12_IO endmodule Verilog-Perl-3.482/verilog/parser_sv.v0000644000177100017500000002273314035374034017670 0ustar wsnyderwsnyderpackage mypackage; bit [7:0] pkg_addr; bit [7:0] pkg_data; endpackage module times (); time x; initial x = 33ns; // Note no space endmodule : times interface itf #(parameter num_of_cli = 0); logic blabla; logic [7:0] addr, data[9]; modport Master(input data, date_delayed, output addr); endinterface : itf module test ( itf whole_int, itf.test modported_int, input logic clk, rst, input logic d_in, output logic d_out ); import mypackage::*; logic d_int; logic [7:0] data_, bork[2]; assign d_int = d_in + pkg_data; assign modported_int.data = data_; always_ff @(posedge clk or negedge rst) begin if (~rst) d_out <= '0; else d_out <= d_int; end property p1; @(posedge clk) disable iff(!rst) $rose(d_int) |-> ##1 d_int; endproperty //a1: assert property(p1) else $warning("\nProperty violated\n"); c1: cover property(p1) $display("\np1_cover\n"); endmodule : test // Different ways of declaring pins/vars module line49_diff_pins1 ( input in_nw, // Input, no type input [1:0] in_vec[2:0], // Input, implicit input in_nvec, // Isn't vectorized output logic out_logic, // Output and var output out_also_logic // "logic" sticks ); endmodule module line49_diff_pins2 (in2_nw, in2_vec, out2reg); input in2_nw; input [1:0] in2_vec [2:0]; output reg out2_reg; input signed in2_signed; var var1_imp; var [1:0] var1_imp_vec [2:0]; var reg var1_imp_reg; var logic var1_imp_logic; endmodule program automatic first_prog; int i; endprogram // Importing package imp_test_pkg; typedef logic [7:0] byte_t; typedef logic [15:0] word_t; function afunc(integer w); afunc=0; endfunction endpackage module imp_test_mod; import imp_test_pkg::byte_t; byte_t some_byte; endmodule module imp_test_mod2; import imp_test_pkg::*; word_t some_word; endmodule module imp_test_mod3 ( input imp_test_pkg::word_t wordin ); localparam FROM_FUNC = imp_test_pkg::afunc(1); endmodule module var_unnamed_block; initial begin integer var_in_unnamed; end endmodule module cell_with_typeparam; addr #(.PARAMTYPE(integer)) acell (); endmodule module arrayed_wire; wire [3:0][7:0] n2; endmodule task empty_task; // sv design book endtask task empty_task2; // sv design book integer i; endtask task check_casts; typedef integer integer_t; sum = a + integer '(3); sum = a + integer_t '(3); sum = a + 10'(3); endtask module comma_assign; int n[1:2][1:3] = '{'{0,1,2}, '{3{4}}}; endmodule task typed_pattern; typedef int triple [1:3]; $mydisplay(triple'{0,1,2}); endtask virtual class VclassWCopy; extern function new(); virtual function VclassWCopy copy(input VclassWCopy src=null); endfunction endclass : VclassWCopy function VclassWCopy::new(); endfunction : new typedef class FwdClass; function bit [3:0] FwdClass::ffunc (bit [3:0] in); ffunc = in; endfunction : ffunc function VclassWCopy VclassWCopy::copy (input VclassWCopy to); dst = new(); endfunction : copy task foreach_memref; bit [0:52] [7:0] mem; // It's *not* legal according to the grammar to have dotted/package ids here foreach (mem[i]) $write("i=%x ", mem[i]); $display; endtask typedef class PreTypedefedClass; class PreTypedefedClass; extern function new(); endclass typedef class PreTypedefedClass; class NewInNew; function new; s_self = new; endfunction : new endclass // std package class TryStd; semaphore s1; std::semaphore s2; mailbox #(integer) m1; std::mailbox m2; process p1; std::process p2; endclass module cg_test1; covergroup counter1 @ (posedge cyc); cyc_bined : coverpoint cyc { bins zero = {0}; bins low = {1,5}; bins mid = {[5:$]}; } value_and_toggle: cross cyc_value, toggle; endgroup endmodule task randomize_dotted(); int vbl; assert(vbl.randomize()); endtask module prop_parens; LABEL: cover property (@(posedge clk) ((foo[3:0] == 4'h0) & bar)); endmodule class this_dot_tests; task ass; this.super.foo = this.bar; endtask endclass module sized_out #( parameter SZ = 4 ) ( output logic [SZ-1:0] o_sized ); endmodule class solve_size; rand byte arrayed[]; rand bit b; // The dot below doesn't seem legal according to grammar, but // the intent makes sense, and it appears in the VMM constraint solve_a_b { solve arrayed.size before b; } endclass class vmm_stuff; task examples; void'(this.a.funccall(x)); this.a.taskcall(); super.new(name2); endtask extern static local function bit foo1(); extern virtual protected function void foo2(); protected static string foo3; extern function bit foo4(); static local bit foo5[string]; endclass class vmm_cl_func_colon; typedef enum int unsigned {FIRM} restart_e; function void do_all(vmm_cl_func_colon::restart_e kind = vmm_cl_func_colon::FIRM); endfunction extern function int uses_class_type(); endclass class vmm_cl_subenv; extern protected virtual task do_reset(vmm_cl_func_colon::restart_e kind = vmm_cl_func_colon::FIRM); endclass task empty_comma; extracomma1(,); extracomma2("a",); extracomma3("a",,"c"); extracomma4(,"b"); endtask task vmm_more; file_is_a_string(`__FILE__,`__LINE__); foreach(this.text[i]) begin $display("%s\n", this.text[i]); end // Not part of 1800-2005 grammar, but likely in 1800-2009 queue = '{}; -> this.item_taken; endtask // Extern Functions/tasks when defined must scope to the class they're in to get appropriate types function int vmm_cl_func_colon::uses_class_type(restart_e note_uses_class_type); var restart_e also_uses_class_type; endfunction module hidden_checks; typedef int T; sub (.T(123)); // Different T task hidden; typedef bit T; // Different T endtask endmodule typedef struct packed signed { rand int m_a; bit [7:0] m_b; } t_bug91; t_bug91 v_bug91; module bug98(interfacex x_if); h inst_h(.push(x_if.pop)); endmodule module bugas; initial begin ASSERT_CHK: assert (0) else $error("%m -- not allowed %d", 0); end endmodule typedef enum [2:0] { ENUM_RANGED_VALUE } enum_ranged_t; typedef struct packed { logic val; } t_bug202_struct; typedef union packed { logic val; } t_bug202_union; class ln288; extern virtual function string extvirtstr; extern virtual task extvirttask; endclass class cl_to_init; extern function new(); extern static function cl_to_init init(); endclass function cl_to_init cl_to_init::init(); endfunction function cl_to_init::new(); endfunction cl_to_init cl_inited = cl_to_init::init(); // pure virtual functions have no endfunction. virtual class pure_virt_func_class; pure virtual function string pure_virt_func(); pure virtual task pure_virt_task(); endclass class extend_base; typedef enum { EN_A, EN_B } base_enum; virtual function extend_base create(); return null; endfunction endclass class extended extends extend_base; typedef base_enum be_t; // type must come from base class virtual function int create (); // Must override base's create be_t mye; endfunction endclass task rand_with_ln320(); if (!randomize(v) with { v > 0 && v < maxval; }) begin end if (randomize(null)) begin end endtask task apply_request(data_req, input bit randomize = 1); if (randomize == 1) begin data_req.randomize(); // Generic method, not std::randomize end endtask task foreach_class_scope_ln330; foreach (extended::some_array[i,j]) begin end endtask module clkif_334; always @(posedge top.clk iff !top.clken_l) begin end endmodule module gen_ln338; generate case (P) 32'b0: initial begin end default: initial begin end endcase endgenerate endmodule module par_packed; parameter logic [31:0] P1 [3:0] = '{ 1, 2, 3, 4 } ; // unpacked array wire struct packed { logic ecc; logic [7:0] data; } memsig; endmodule module not_a_bug315; typedef int supply_net_t; input int i; input imp_test_pkg::byte_t i; input supply_net_t bug316; endmodule module bins_bracket; parameter N = 2; covergroup cg_debitor @(posedge eclk); count: coverpoint count iff (erst_n) { // 'std' overrides std:: package, which confuses VP //bins std[] = { [0:N] }; } endgroup endmodule virtual class ovm_void; endclass virtual class ovm_port_base #(type IF=ovm_void) extends ovm_void; endclass virtual class uvm_build_phase #(type BASE=ovm_void) extends BASE; static const string type_name = "uvm_build_phase"; endclass class bug627sub; endclass class bug627 #(type TYPE=bug627sub); typedef TYPE types_t[$]; static function types_t f(); $display("%s", { TYPE::type_name }); return types; endfunction endclass interface if_bug777; wire a; modport master (input a); modport slave (output a); endinterface module bug777 (clk, ifport); input clk; if_bug777 ifport (); if_bug777.mp ifportmp; //if_bug777.mp ifportmp (); // Not legal // Currently unsupported, parens required so VP knows is instance //if_bug777 ifport; endmodule module bug778 (); virtual if_bug777.master bar; endmodule class cls778; virtual if_bug777.master bar; endclass : cls778; module bug810 #( /*parameter*/ int unsigned DW = 32); endmodule interface test_if (input clk); endinterface module bug815 ( test_if bad[2]); endmodule module bug868 (ifmp); if_bug777.master ifmp; endmodule module bug_param_struct #(int ROWS = 2, type data_t = struct packed { logic [ROWS-1:0] row_id; }) (input data_t d); endmodule Verilog-Perl-3.482/verilog/v_sv_pkg.v0000644000177100017500000000045313234726611017477 0ustar wsnyderwsnyder// DESCRIPTION: Verilog-Perl: Example Verilog for testing package // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2009-2012 by Wilson Snyder. `ifndef _V_SV_PKG_ `define _V_SV_PKG_ package v_sv_pkg; typedef logic [7:0] byte_t; endpackage `endif // guard Verilog-Perl-3.482/verilog/v_hier_subsub.v0000644000177100017500000000167113234726611020523 0ustar wsnyderwsnyder// DESCRIPTION: Verilog-Perl: Example Verilog for testing package // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2000-2012 by Wilson Snyder. module v_hier_subsub (/*AUTOARG*/ // Outputs q, // Inputs a ); parameter IGNORED = 0; input signed a; output q; wire q = a; // Test protected `pragma protect begin_protected `pragma protect encrypt_agent = "Whatever agent" `pragma protect encrypt_agent_info = "1.2.3" `pragma protect data_method = "aes128-cbc" `pragma protect key_keyowner = "Someone" `pragma protect key_keyname = "somekey", key_method = "rsa" `pragma protect key_block encoding = (enctype = "base64") wefjosdfjklajklasjkl `pragma protect data_block encoding = (enctype = "base64", bytes = 1059) I!#r#e6<_Q{{E2+]I3<[3s)1@D|'E''i!O?]jD>Jo_![Cl) #nj1]p,3^1~,="E@QZB\T)eU\pC#C|7=\$J$##A[@-@{Qk] `pragma protect end_protected `pragma reset protect //" endmodule Verilog-Perl-3.482/verilog/inc_ifdef.v0000644000177100017500000000134313234726611017566 0ustar wsnyderwsnyder// DESCRIPTION: Verilog::Preproc: Example source code // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2000-2012 by Wilson Snyder. `define EMPTY_TRUE `ifndef EMPTY_TRUE `error "Empty is still true" `endif `define A `ifdef A $display("1A"); `ifdef C $display("%Error: 2C"); `elsif A $display("2A"); `ifdef C $display("%Error: 3C"); `elsif B $display("%Error: 3B"); `else $display("3AELSE"); `endif `else $display("%Error: 2ELSE"); `endif `elsif B $display("%Error: 1B"); `ifdef A $display("%Error: noC"); `elsif A $display("%Error: noB"); `else $display("%Error: noELSE"); `endif `elsif C $display("%Error: 1C"); `else $display("%Error: 1ELSE"); `endif Verilog-Perl-3.482/verilog/test.vrename0000644000177100017500000000066014553624300020025 0ustar wsnyderwsnyder# DESCRIPTION: vrename: For test.pl testing of vrename # # Copyright 2000-2024 by Wilson Snyder. This program is free software; # you can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. ###################################################################### sigren "a" "or_term_1" sigren "b" "or_term_2" sigren "z" "ored_output" Verilog-Perl-3.482/verilog/example.v0000644000177100017500000000710013234726611017310 0ustar wsnyderwsnyder// DESCRIPTION: Example top verilog file for vpassert program // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2000-2012 by Wilson Snyder. `timescale 1ns/1ns module example; pli pli (); // Put on highest level of your design integer i; `define ten 10 reg \escaped[10] ; initial begin $uinfo (0, "Welcome to a VPASSERTed file\n"); // $uinfo (1, "Printed only at debug level %0d\n",1); $uinfo (9, "Printed only at debug level %0d\n",9); // \escaped[10] = 1'b1; $uassert (\escaped[10] , "Escaped not 1\n"); $uassert_info (\escaped[10] , "Escaped not 1\n"); // i=0; $uassert (1==1, "Why doesn't 1==1??\n"); $uassert (10==`ten, "Why doesn't 10==10??\n"); $uassert (/*comm ent*/1==1, //comment /*com ent*/"Why doesn't 1==1??\n"/*com ent*/ ); // i=3'b100; $uassert_amone(\i [2:0], "amone ok\n"); i=3'b010; $uassert_amone(i[2:0], "amone ok\n"); i=3'b001; $uassert_amone(i[2:0], "amone ok\n"); i=3'b000; $uassert_amone(i[2:0], "amone ok\n"); //i=3'b011; $uassert_amone(i[2:0], "amone error expected\n"); //i=3'b110; $uassert_amone(i[2:0], "amone error expected\n"); // i=2'b10; $uassert_onehot(i[1:0], "onehot ok\n"); i=2'b01; $uassert_onehot(i[1:0], "onehot ok\n"); i=2'b10; $uassert_onehot(i[1],i[0], "onehot ok\n"); i=2'b10; $uassert_onehot({i[1],i[0]}, "onehot ok\n"); //i=2'b11; $uassert_onehot(i[2:0], "onehot error expected\n"); //i=2'b00; $uassert_onehot(i[2:0], "onehot error expected\n"); end // Test assertions within case statements initial begin i=3'b100; casez (i) 3'b100: ; 3'b000: $stop; 3'b010: $uerror("Why?\n"); default: $stop; endcase if ($time > 1000) $stop; end // Example of request/grant handshake reg clk; reg bus_req; // Request a transaction, single cycle pulse reg bus_ack; // Acknowledged transaction, single cycle pulse reg [31:0] bus_data; initial begin // Reset signals bus_req = 1'b0; bus_ack = 1'b0; bus_data = 1'b0; // Assert a request @ (posedge clk) ; bus_req = 1'b1; bus_data = 32'hfeed; // Wait for ack @ (posedge clk) ; bus_req = 1'b0; // Send ack @ (posedge clk) ; bus_ack = 1'b1; // Next request could be here @ (posedge clk) ; bus_ack = 1'b0; end always @ (posedge clk) begin $uassert_req_ack (bus_req, bus_ack /*COMMENT*/, bus_data); end // Overall control loop initial clk = 1'b0; initial forever begin #1; i = i + 1; clk = !clk; if (i==20) $uwarn (0, "Don't know what to do next!\n"); if (i==22) $uerror (0, "Guess I'll error out!\n"); end // Moved clock asserts always @* begin if (i==19) $uwarn_clk (clk,"Called at next edge (1 of 2)\n"); if (i==18) $ucover_clk (clk,"example_cover_label"); $ucover_foreach_clk(clk, "foreach_label", "27:3,1,0", (i[$ui])); end // Meta coverage disables initial begin // vp_coverage_off if (0) begin end // cover off'ed // vp_coverage_on end // Ifdef based disables initial begin `ifndef NEVER `ifdef SYNTHESIS if (1) begin end // cover on `elsif SYNTHESIS if (1) begin end // cover on `else if (1) begin end // cover off'ed `endif `ifndef SYNTHESIS if (1) begin end // cover off'ed `else if (1) begin end // cover on `endif `endif end endmodule Verilog-Perl-3.482/verilog/pinorder.v0000644000177100017500000000165513234726611017510 0ustar wsnyderwsnyder// DESCRIPTION: Verilog-Perl: Example Verilog for testing package // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2003 by Wilson Snyder. module pinorder4(); wire b_i; wire d_o; wire [7:0] a_i; wire [31:0] IPCD_const = 32'h1; assign a_i = 0; assign b_i = 0; foo foo1( .y(b_i), .x(a_i), .abcconst(3'h0), .noconnect(), .def(IPCD_const)); foo foo3( b_i, a_i, 3'h0, , IPCD_const); foo2 foo2( b_i, a_i[0], d_o); endmodule module foo2(/*AUTOARG*/ // Outputs x, // Inputs z, y ); input z; input y; output x; reg x; always @(z or y) x = z & y; endmodule module foo (/*AUTOARG*/ // Inputs y, x, abcconst, noconnect, def ); input y; input x; input [2:0] abcconst; input signed [3:0] noconnect; input [31:0] def; endmodule module bug278 ( output wire ow, inout wire iow, input wire iw); endmodule Verilog-Perl-3.482/verilog/v_recursive.v0000644000177100017500000000025313234726611020213 0ustar wsnyderwsnydermodule v_recursive (); parameter DEPTH = 1; generate if (DEPTH > 1) begin : rec v_recursive #(.DEPTH(DEPTH-1)) recurse (); end endgenerate endmodule Verilog-Perl-3.482/verilog/t_80_foo.v0000644000177100017500000000047313234726611017300 0ustar wsnyderwsnyder// DESCRIPTION: Verilog::Preproc: Example source code // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012-2012 by Wilson Snyder. // // Test -F option in vppreproc. // This is the top level module. module foo(output wire y, input wire x); bar i_bar(y, x); endmodule // foo Verilog-Perl-3.482/.clang-format0000644000177100017500000000613214035374034016374 0ustar wsnyderwsnyder--- Language: Cpp # BasedOnStyle: LLVM AccessModifierOffset: -4 AlignAfterOpenBracket: Align AlignConsecutiveAssignments: false AlignConsecutiveDeclarations: false AlignEscapedNewlines: DontAlign AlignOperands: true AlignTrailingComments: false AllowAllParametersOfDeclarationOnNextLine: true AllowShortBlocksOnASingleLine: true AllowShortCaseLabelsOnASingleLine: true AllowShortFunctionsOnASingleLine: All AllowShortIfStatementsOnASingleLine: true AllowShortLoopsOnASingleLine: true AlwaysBreakAfterDefinitionReturnType: None AlwaysBreakAfterReturnType: None AlwaysBreakBeforeMultilineStrings: false AlwaysBreakTemplateDeclarations: false BinPackArguments: true BinPackParameters: true BraceWrapping: AfterClass: false AfterControlStatement: false AfterEnum: false AfterFunction: false AfterNamespace: false AfterObjCDeclaration: false AfterStruct: false AfterUnion: false AfterExternBlock: false BeforeCatch: false BeforeElse: false IndentBraces: false SplitEmptyFunction: true SplitEmptyRecord: true SplitEmptyNamespace: true BreakBeforeBinaryOperators: All BreakBeforeBraces: Attach BreakBeforeInheritanceComma: false BreakBeforeTernaryOperators: true BreakConstructorInitializersBeforeComma: false BreakConstructorInitializers: BeforeComma BreakAfterJavaFieldAnnotations: false BreakStringLiterals: true ColumnLimit: 99 CommentPragmas: '^ IWYU pragma:' CompactNamespaces: false ConstructorInitializerAllOnOneLineOrOnePerLine: false ConstructorInitializerIndentWidth: 4 ContinuationIndentWidth: 4 Cpp11BracedListStyle: true DerivePointerAlignment: false DisableFormat: false ExperimentalAutoDetectBinPacking: false FixNamespaceComments: true ForEachMacros: - foreach - Q_FOREACH - BOOST_FOREACH IncludeBlocks: Preserve IncludeCategories: - Regex: '^"(llvm|llvm-c|clang|clang-c)/' Priority: 2 - Regex: '^(<|"(gtest|gmock|isl|json)/)' Priority: 3 - Regex: '.*' Priority: 1 IncludeIsMainRegex: '(Test)?$' IndentCaseLabels: false IndentPPDirectives: None IndentWidth: 4 IndentWrappedFunctionNames: false JavaScriptQuotes: Leave JavaScriptWrapImports: true KeepEmptyLinesAtTheStartOfBlocks: true MacroBlockBegin: '' MacroBlockEnd: '' MaxEmptyLinesToKeep: 1 NamespaceIndentation: None ObjCBlockIndentWidth: 2 ObjCSpaceAfterProperty: false ObjCSpaceBeforeProtocolList: true PenaltyBreakAssignment: 2 PenaltyBreakBeforeFirstCallParameter: 19 PenaltyBreakComment: 300 PenaltyBreakFirstLessLess: 120 PenaltyBreakString: 1000 PenaltyExcessCharacter: 1000000 PenaltyReturnTypeOnItsOwnLine: 60 PointerAlignment: Left ReflowComments: true SortIncludes: false SortUsingDeclarations: true SpaceAfterCStyleCast: false SpaceAfterTemplateKeyword: true SpaceBeforeAssignmentOperators: true SpaceBeforeParens: ControlStatements SpaceInEmptyParentheses: false SpacesBeforeTrailingComments: 2 SpacesInAngles: false SpacesInContainerLiterals: true SpacesInCStyleCastParentheses: false SpacesInParentheses: false SpacesInSquareBrackets: false Standard: Cpp03 TabWidth: 8 UseTab: Never ... Verilog-Perl-3.482/t/0000755000177100017500000000000014553624441014267 5ustar wsnyderwsnyderVerilog-Perl-3.482/t/35_sigparser_ps.out0000644000177100017500000023034314035374034020030 0ustar wsnyderwsnyderverilog/v_hier_subprim.v:001: COMMENT '// DESCRIPTION: Verilog-Perl: Example Verilog for testing package' verilog/v_hier_subprim.v:002: COMMENT '//' verilog/v_hier_subprim.v:003: COMMENT '// This file ONLY is placed into the Public Domain, for any use,' verilog/v_hier_subprim.v:004: COMMENT '// without warranty, 2000-2012 by Wilson Snyder.' verilog/v_hier_subprim.v:006: COMMENT '// surefire lint_off UDPUNS' verilog/v_hier_subprim.v:008: MODULE 'primitive' 'v_hier_prim' undef '0' verilog/v_hier_subprim.v:008: COMMENT '/*AUTOARG*/' verilog/v_hier_subprim.v:009: COMMENT '// Outputs' verilog/v_hier_subprim.v:010: PORT 'q' 'module' '' '' '' '1' verilog/v_hier_subprim.v:011: COMMENT '// Inputs' verilog/v_hier_subprim.v:012: PORT 'a' 'module' '' '' '' '2' verilog/v_hier_subprim.v:014: VAR 'port' 'q' 'module' '' '' '' '' verilog/v_hier_subprim.v:014: PORT 'q' 'module' 'output' '' '' '0' verilog/v_hier_subprim.v:015: VAR 'port' 'a' 'module' '' '' '' '' verilog/v_hier_subprim.v:015: PORT 'a' 'module' 'input' '' '' '0' verilog/v_hier_subprim.v:022: ENDMODULE 'endprimitive' verilog/v_hier_subprim.v:025: MODULE 'module' 'bug27070' undef '1' verilog/v_hier_subprim.v:027: VAR 'parameter' 'TAP' 'module' '' '' '' '4'b1001' verilog/v_hier_subprim.v:028: ENDMODULE 'endmodule' verilog/v_hier_subprim.v:032: MODULE 'module' 'bug893' undef '1' verilog/v_hier_subprim.v:033: VAR 'var' 'r' 'module' '' 'reg' '' '' verilog/v_hier_subprim.v:035: ENDMODULE 'endmodule' verilog/v_hier_sub.v:001: COMMENT '// DESCRIPTION: Verilog-Perl: Example Verilog for testing package' verilog/v_hier_sub.v:002: COMMENT '//' verilog/v_hier_sub.v:003: COMMENT '// This file ONLY is placed into the Public Domain, for any use,' verilog/v_hier_sub.v:004: COMMENT '// without warranty, 2000-2012 by Wilson Snyder.' verilog/v_hier_sub.v:006: MODULE 'module' 'v_hier_sub' undef '0' verilog/v_hier_sub.v:006: COMMENT '/*AUTOARG*/' verilog/v_hier_sub.v:007: VAR 'port' 'clk' 'module' '' '' '' '' verilog/v_hier_sub.v:007: PORT 'clk' 'module' 'input' '' '' '1' verilog/v_hier_sub.v:008: VAR 'port' 'avec' 'module' '' '[3:0]' '' '' verilog/v_hier_sub.v:008: PORT 'avec' 'module' 'input' '[3:0]' '' '2' verilog/v_hier_sub.v:008: COMMENT '// Comment for v_hier_sub, avec' verilog/v_hier_sub.v:009: COMMENT '/* Comment for v_hier_sub, qvec */' verilog/v_hier_sub.v:009: VAR 'port' 'qvec' 'module' '' '[3:0]' '' '' verilog/v_hier_sub.v:009: PORT 'qvec' 'module' 'output' '[3:0]' '' '3' verilog/v_hier_sub.v:012: VAR 'parameter' 'FROM_DEFPARAM' 'module' '' '' '' '1' verilog/v_hier_sub.v:014: VAR 'net' 'a1' 'module' 'supply1' '' '' '' verilog/v_hier_sub.v:020: COMMENT '// Outputs' verilog/v_hier_sub.v:019: INSTANT 'v_hier_subsub' 'subsub0' '' verilog/v_hier_sub.v:017: PARAMPIN 'IGNORED' ''sh20' '1' verilog/v_hier_sub.v:021: PIN 'q' 'qvec[0]' '1' verilog/v_hier_sub.v:021: PINSELECTS 'q' '[{'lsb' => '0','msb' => '0','netname' => 'qvec'}]' '1' verilog/v_hier_sub.v:022: COMMENT '// Inputs' verilog/v_hier_sub.v:023: PIN 'a' 'a1' '2' verilog/v_hier_sub.v:023: PINSELECTS 'a' '[{'netname' => 'a1'}]' '2' verilog/v_hier_sub.v:023: ENDCELL '' verilog/v_hier_sub.v:023: COMMENT '// Comment for subsub cell' verilog/v_hier_sub.v:027: VAR 'genvar' 'K' 'module' '' '' '' '' verilog/v_hier_sub.v:027: VAR 'genvar' 'K_UNUSED' 'module' '' '' '' '' verilog/v_hier_sub.v:029: COMMENT '// By pin position, inside generate' verilog/v_hier_sub.v:030: INSTANT 'v_hier_subsub' 'subsub2' '' verilog/v_hier_sub.v:030: PIN '' 'qvec[2]' '1' verilog/v_hier_sub.v:030: PINSELECTS '' '[{'lsb' => '2','msb' => '2','netname' => 'qvec'}]' '1' verilog/v_hier_sub.v:030: PIN '' '1'b0' '2' verilog/v_hier_sub.v:030: PINSELECTS '' '[{'netname' => '1\'b0'}]' '2' verilog/v_hier_sub.v:030: ENDCELL '' verilog/v_hier_sub.v:034: FUNCTION 'function' 'foo' '' verilog/v_hier_sub.v:035: ATTRIBUTE '(* attribute *)' verilog/v_hier_sub.v:036: COMMENT '/* synopsys metacommenttest */' verilog/v_hier_sub.v:037: VAR 'port' 'not_part_of_pinlist' 'function' '' '' '' '' verilog/v_hier_sub.v:037: PORT 'not_part_of_pinlist' 'function' 'input' '' '' '0' verilog/v_hier_sub.v:039: ENDTASKFUNC 'endfunction' verilog/v_hier_sub.v:041: ENDMODULE 'endmodule' verilog/parser_bugs.v:001: COMMENT '// Not legal:' verilog/parser_bugs.v:002: COMMENT '// end : ADDRESS_TEST_BLOCK // See 9.8.1' verilog/parser_bugs.v:003: COMMENT '// `define at EOF with no newline' verilog/parser_bugs.v:005: MODULE 'module' 'bug26141' undef '0' verilog/parser_bugs.v:006: VAR 'net' 'b' 'module' 'wire' '[0:3]' '' '' verilog/parser_bugs.v:007: VAR 'net' 'a' 'module' 'wire' '' '' 'b[2]' verilog/parser_bugs.v:008: ENDMODULE 'endmodule' verilog/parser_bugs.v:010: MODULE 'module' 'bug26940' undef '0' verilog/parser_bugs.v:011: ATTRIBUTE '(* attribute *)' verilog/parser_bugs.v:012: CONTASSIGN 'assign' 'q' '{1'b0,a}+{1'b0,b}' verilog/parser_bugs.v:014: INSTANT 'adder' 'u_add' '' verilog/parser_bugs.v:014: PIN 'q' 'q' '1' verilog/parser_bugs.v:014: PINSELECTS 'q' '[{'netname' => 'q'}]' '1' verilog/parser_bugs.v:014: PIN 'a' 'd' '2' verilog/parser_bugs.v:014: PINSELECTS 'a' '[{'netname' => 'd'}]' '2' verilog/parser_bugs.v:014: PIN 'b' 'd' '3' verilog/parser_bugs.v:014: PINSELECTS 'b' '[{'netname' => 'd'}]' '3' verilog/parser_bugs.v:014: ENDCELL '' verilog/parser_bugs.v:020: ENDMODULE 'endmodule' verilog/parser_bugs.v:022: MODULE 'module' 'bug26968' undef '0' verilog/parser_bugs.v:023: VAR 'var' 'vect' 'module' '' 'reg [4:0]' '' '5'b10100' verilog/parser_bugs.v:024: VAR 'net' 'tmp' 'module' 'wire' '[4:0]' '' '{vect[0],vect[1],vect[2],vect[3],vect[4]}' verilog/parser_bugs.v:028: ENDMODULE 'endmodule' verilog/parser_bugs.v:030: MODULE 'module' 'bug26969' undef '0' verilog/parser_bugs.v:030: VAR 'port' 'ad' 'module' '' '[31:0]' '' '' verilog/parser_bugs.v:030: PORT 'ad' 'module' 'input' '[31:0]' '' '1' verilog/parser_bugs.v:030: VAR 'port' 'regff' 'module' '' '[15:0]' '' '' verilog/parser_bugs.v:030: PORT 'regff' 'module' 'output' '[15:0]' '' '2' verilog/parser_bugs.v:030: VAR 'port' 'read' 'module' '' '[31:0]' '' '' verilog/parser_bugs.v:030: PORT 'read' 'module' 'input' '[31:0]' '' '3' verilog/parser_bugs.v:031: INSTANT 'bufif0' 'ad_drv' '[31:0]' verilog/parser_bugs.v:031: PIN '' 'ad' '1' verilog/parser_bugs.v:031: PINSELECTS '' '[{'netname' => 'ad'}]' '1' verilog/parser_bugs.v:031: PIN '' '{16'b0,regff}' '2' verilog/parser_bugs.v:031: PINSELECTS '' '[{'netname' => 'regff'},{'lsb' => 0,'msb' => 15,'netname' => '\'b0'}]' '2' verilog/parser_bugs.v:031: PIN '' 'read' '3' verilog/parser_bugs.v:031: PINSELECTS '' '[{'netname' => 'read'}]' '3' verilog/parser_bugs.v:031: ENDCELL '' verilog/parser_bugs.v:032: ENDMODULE 'endmodule' verilog/parser_bugs.v:034: MODULE 'module' 'bug26970' undef '0' verilog/parser_bugs.v:035: VAR 'parameter' 'A' 'module' '' '' '' '2'b1' verilog/parser_bugs.v:035: VAR 'parameter' 'B' 'module' '' '' '' '3'b0' verilog/parser_bugs.v:036: VAR 'parameter' 'x' 'module' '' '' '' '{B,B,B,A,A,B}' verilog/parser_bugs.v:037: ENDMODULE 'endmodule' verilog/parser_bugs.v:039: MODULE 'module' 'bug26997' undef '0' verilog/parser_bugs.v:040: INSTANT 'MUX_REG_8x8' 'PAGE_REG_B3' '' verilog/parser_bugs.v:041: PIN 'CLK' 'CLK' '1' verilog/parser_bugs.v:041: PINSELECTS 'CLK' '[{'netname' => 'CLK'}]' '1' verilog/parser_bugs.v:042: COMMENT '/* .IN (DATA_RES[31:24]), .OUT (PAGE[31:24]), .EN_IN (EN_B3), .EN_OUT (PAGE_SEL), */' verilog/parser_bugs.v:048: PIN 'TC' '' '2' verilog/parser_bugs.v:048: PINSELECTS 'TC' '[{'netname' => ''}]' '2' verilog/parser_bugs.v:049: PIN 'TD' '' '3' verilog/parser_bugs.v:049: PINSELECTS 'TD' '[{'netname' => ''}]' '3' verilog/parser_bugs.v:050: PIN 'TQ' '' '4' verilog/parser_bugs.v:050: PINSELECTS 'TQ' '[{'netname' => ''}]' '4' verilog/parser_bugs.v:050: ENDCELL '' verilog/parser_bugs.v:051: ENDMODULE 'endmodule' verilog/parser_bugs.v:053: MODULE 'module' 'bug27013' undef '0' verilog/parser_bugs.v:054: INSTANT 'submod' 'u1' '' verilog/parser_bugs.v:054: PIN '' '0' '1' verilog/parser_bugs.v:054: PINSELECTS '' '[{'netname' => '0'}]' '1' verilog/parser_bugs.v:054: ENDCELL '' verilog/parser_bugs.v:055: INSTANT 'submod' 'u2' '' verilog/parser_bugs.v:055: PIN '' '1' '1' verilog/parser_bugs.v:055: PINSELECTS '' '[{'netname' => '1'}]' '1' verilog/parser_bugs.v:055: ENDCELL '' verilog/parser_bugs.v:056: ENDMODULE 'endmodule' verilog/parser_bugs.v:058: MODULE 'module' 'bug27036' undef '0' verilog/parser_bugs.v:059: VAR 'var' 'a_fifo_cam_indices' 'module' '' 'reg [2:0]' '[3:0]' '' verilog/parser_bugs.v:059: VAR 'var' 'lt_fifo_cam_indices' 'module' '' 'reg [2:0]' '[5:0]' '' verilog/parser_bugs.v:060: VAR 'net' 'db0_a_fifo_cam_indices' 'module' 'wire' '[2:0]' '' 'a_fifo_cam_indices[0]' verilog/parser_bugs.v:061: ENDMODULE 'endmodule' verilog/parser_bugs.v:063: MODULE 'module' 'bug27037' undef '0' verilog/parser_bugs.v:064: VAR 'var' 'mem' 'module' '' 'reg' '[12:2]' '' verilog/parser_bugs.v:065: VAR 'var' 'i' 'module' '' 'reg [7:0]' '' '' verilog/parser_bugs.v:066: ENDMODULE 'endmodule' verilog/parser_bugs.v:068: MODULE 'module' 'bug27039' undef '0' verilog/parser_bugs.v:069: VAR 'var' 'i' 'module' '' 'integer' '' '' verilog/parser_bugs.v:070: ENDMODULE 'endmodule' verilog/parser_bugs.v:072: MODULE 'module' 'bug27045' undef '0' verilog/parser_bugs.v:073: VAR 'port' 'clk' 'module' '' '' '' '' verilog/parser_bugs.v:073: PORT 'clk' 'module' 'input' '' '' '1' verilog/parser_bugs.v:073: VAR 'port' 'reset' 'module' '' '' '' '' verilog/parser_bugs.v:073: PORT 'reset' 'module' 'input' '' '' '2' verilog/parser_bugs.v:074: VAR 'port' 'd' 'module' '' '[7:0]' '' '' verilog/parser_bugs.v:074: PORT 'd' 'module' 'input' '[7:0]' '' '3' verilog/parser_bugs.v:075: VAR 'port' 'q' 'module' '' 'reg [7:0]' '' '' verilog/parser_bugs.v:075: PORT 'q' 'module' 'output' 'reg [7:0]' '' '4' verilog/parser_bugs.v:076: VAR 'parameter' 'REG_DELAY' 'module' '' '' '' '0' verilog/parser_bugs.v:079: ENDMODULE 'endmodule' verilog/parser_bugs.v:081: MODULE 'module' 'bug27062' undef '0' verilog/parser_bugs.v:081: VAR 'port' 'D' 'module' '' '' '' '' verilog/parser_bugs.v:081: PORT 'D' 'module' 'input' '' '' '1' verilog/parser_bugs.v:081: VAR 'port' 'Q' 'module' '' '' '' '' verilog/parser_bugs.v:081: PORT 'Q' 'module' 'output' '' '' '2' verilog/parser_bugs.v:082: INSTANT 'p' '' '' verilog/parser_bugs.v:082: PIN '' 'Q' '1' verilog/parser_bugs.v:082: PINSELECTS '' '[{'netname' => 'Q'}]' '1' verilog/parser_bugs.v:082: PIN '' 'D' '2' verilog/parser_bugs.v:082: PINSELECTS '' '[{'netname' => 'D'}]' '2' verilog/parser_bugs.v:082: ENDCELL '' verilog/parser_bugs.v:083: ENDMODULE 'endmodule' verilog/parser_bugs.v:087: MODULE 'module' 'bug27066' undef '0' verilog/parser_bugs.v:088: VAR 'var' 'i' 'module' '' 'integer' '' '' verilog/parser_bugs.v:089: VAR 'var' 't' 'module' '' 'time' '' '' verilog/parser_bugs.v:090: VAR 'var' 'rt' 'module' '' 'realtime' '' '' verilog/parser_bugs.v:091: FUNCTION 'function' 'toint' 'integer' verilog/parser_bugs.v:092: VAR 'port' 'y' 'function' '' 'integer' '' '' verilog/parser_bugs.v:092: PORT 'y' 'function' 'input' 'integer' '' '0' verilog/parser_bugs.v:093: VAR 'port' 'x' 'function' '' '[15:0]' '' '' verilog/parser_bugs.v:093: PORT 'x' 'function' 'input' '[15:0]' '' '0' verilog/parser_bugs.v:095: ENDTASKFUNC 'endfunction' verilog/parser_bugs.v:096: ENDMODULE 'endmodule' verilog/parser_bugs.v:098: MODULE 'module' 'bug27067' undef '0' verilog/parser_bugs.v:101: ENDMODULE 'endmodule' verilog/parser_bugs.v:103: MODULE 'module' 'bug27072' undef '0' verilog/parser_bugs.v:104: VAR 'port' 'sum' 'module' '' 'reg' '' '' verilog/parser_bugs.v:104: PORT 'sum' 'module' 'output' 'reg' '' '1' verilog/parser_bugs.v:105: VAR 'port' 'ci' 'module' 'wire' '' '' '' verilog/parser_bugs.v:105: PORT 'ci' 'module' 'input' '' '' '2' verilog/parser_bugs.v:106: ENDMODULE 'endmodule' verilog/parser_bugs.v:109: MODULE 'module' 'spec' undef '0' verilog/parser_bugs.v:122: ENDMODULE 'endmodule' verilog/parser_bugs.v:124: MODULE 'module' 'bugevent' undef '0' verilog/parser_bugs.v:125: VAR 'var' 'e' 'module' '' 'event' '' '' verilog/parser_bugs.v:128: ENDMODULE 'endmodule' verilog/parser_bugs.v:130: MODULE 'module' 'bugio' undef '0' verilog/parser_bugs.v:130: VAR 'port' 'a' 'module' '' '[31:0]' '' '' verilog/parser_bugs.v:130: PORT 'a' 'module' 'input' '[31:0]' '' '1' verilog/parser_bugs.v:130: VAR 'port' 'a2' 'module' '' '[31:0]' '' '' verilog/parser_bugs.v:130: PORT 'a2' 'module' 'input' '[31:0]' '' '2' verilog/parser_bugs.v:130: VAR 'port' 'o' 'module' '' '[15:0]' '' '' verilog/parser_bugs.v:130: PORT 'o' 'module' 'output' '[15:0]' '' '3' verilog/parser_bugs.v:130: VAR 'port' 'o2' 'module' '' '[15:0]' '' '' verilog/parser_bugs.v:130: PORT 'o2' 'module' 'output' '[15:0]' '' '4' verilog/parser_bugs.v:130: VAR 'port' 'ibit' 'module' '' '' '' '' verilog/parser_bugs.v:130: PORT 'ibit' 'module' 'input' '' '' '5' verilog/parser_bugs.v:131: ENDMODULE 'endmodule' verilog/parser_bugs.v:133: MODULE 'module' 'buglocal' undef '0' verilog/parser_bugs.v:140: CONTASSIGN 'assign' 'VDD' '1'b0' verilog/parser_bugs.v:141: CONTASSIGN 'assign' 'VSS' '1'b1' verilog/parser_bugs.v:142: VAR 'net' 'xxout' 'module' 'wire' '[71:0]' '' 'xxin' verilog/parser_bugs.v:149: INSTANT 'nmos' '' '' verilog/parser_bugs.v:149: PARAMPIN '' 'PullTime' '1' verilog/parser_bugs.v:149: PARAMPIN '' 'PullTime' '2' verilog/parser_bugs.v:149: PARAMPIN '' '0' '3' verilog/parser_bugs.v:149: PIN '' 'PT' '1' verilog/parser_bugs.v:149: PINSELECTS '' '[{'netname' => 'PT'}]' '1' verilog/parser_bugs.v:149: PIN '' 'PU' '2' verilog/parser_bugs.v:149: PINSELECTS '' '[{'netname' => 'PU'}]' '2' verilog/parser_bugs.v:149: PIN '' '1'b1' '3' verilog/parser_bugs.v:149: PINSELECTS '' '[{'netname' => '1\'b1'}]' '3' verilog/parser_bugs.v:149: ENDCELL '' verilog/parser_bugs.v:150: INSTANT 'pulldown' 'pullinst' '' verilog/parser_bugs.v:150: PIN '' 'r' '1' verilog/parser_bugs.v:150: PINSELECTS '' '[{'netname' => 'r'}]' '1' verilog/parser_bugs.v:150: ENDCELL '' verilog/parser_bugs.v:152: DEFPARAM 'defparam' 'x.y.z.PAR' '1' verilog/parser_bugs.v:154: INSTANT 'cdrv' 'clk' '' verilog/parser_bugs.v:154: PIN '' 'clk' '1' verilog/parser_bugs.v:154: PINSELECTS '' '[{'netname' => 'clk'}]' '1' verilog/parser_bugs.v:154: ENDCELL '' verilog/parser_bugs.v:162: VAR 'net' '\33escapeneeded ' 'module' 'wire' '' '' '1'b1' verilog/parser_bugs.v:163: VAR 'net' '\33escapenewlineend ' 'module' 'wire' '' '' '1'b1' verilog/parser_bugs.v:165: VAR 'net' 'noescapenewlineend' 'module' 'wire' '' '' '1'b1' verilog/parser_bugs.v:167: VAR 'net' 'noescapespaceend' 'module' 'wire' '' '' '1'b1' verilog/parser_bugs.v:169: ENDMODULE 'endmodule' verilog/parser_bugs.v:171: MODULE 'module' 'v2kparam' undef '0' verilog/parser_bugs.v:172: VAR 'parameter' 'WIDTH' 'module' '' '' '' '1' verilog/parser_bugs.v:173: VAR 'parameter' 'LENGTH' 'module' '' '' '' '1' verilog/parser_bugs.v:173: VAR 'parameter' 'LENGTH2' 'module' '' '' '' '1' verilog/parser_bugs.v:174: VAR 'port' 'myout' 'module' '' '[WIDTH-1:0]' '' '' verilog/parser_bugs.v:174: PORT 'myout' 'module' 'output' '[WIDTH-1:0]' '' '1' verilog/parser_bugs.v:175: VAR 'port' 'myin' 'module' '' '[LENGTH-1:0]' '' '' verilog/parser_bugs.v:175: PORT 'myin' 'module' 'input' '[LENGTH-1:0]' '' '2' verilog/parser_bugs.v:175: VAR 'port' 'myinb' 'module' '' '[LENGTH-1:0]' '' '' verilog/parser_bugs.v:175: PORT 'myinb' 'module' 'input' '[LENGTH-1:0]' '' '3' verilog/parser_bugs.v:177: CONTASSIGN 'assign' 'myout' 'myin^myinb^$callemptyparens' verilog/parser_bugs.v:178: ENDMODULE 'endmodule' verilog/parser_bugs.v:180: MODULE 'module' 'foreqn' undef '0' verilog/parser_bugs.v:180: PORT 'in' 'module' '' '' '' '1' verilog/parser_bugs.v:181: VAR 'port' 'in' 'module' '' '[1:0]' '' '' verilog/parser_bugs.v:181: PORT 'in' 'module' 'input' '[1:0]' '' '0' verilog/parser_bugs.v:182: VAR 'var' 'a' 'module' '' 'reg' '' '' verilog/parser_bugs.v:182: VAR 'var' 'b' 'module' '' 'reg' '' '' verilog/parser_bugs.v:183: VAR 'var' 'c' 'module' '' 'reg [1:0]' '' '' verilog/parser_bugs.v:188: ENDMODULE 'endmodule' verilog/parser_bugs.v:190: MODULE 'module' 'colonslash' undef '0' verilog/parser_bugs.v:193: COMMENT '//Error' verilog/parser_bugs.v:195: COMMENT '/*Another comment*/' verilog/parser_bugs.v:199: ENDMODULE 'endmodule' verilog/parser_bugs.v:201: MODULE 'module' 'enums' undef '0' verilog/parser_bugs.v:202: VAR 'var' 'light' 'module' '' 'enum' '' '' verilog/parser_bugs.v:203: VAR 'var' 'state' 'module' '' 'integer' '' '' verilog/parser_bugs.v:203: VAR 'var' 'next' 'module' '' 'integer' '' '' verilog/parser_bugs.v:204: VAR 'var' 'medal' 'module' '' 'enum' '' '' verilog/parser_bugs.v:205: VAR 'var' 'E1' 'module' '' 'enum' '' '' verilog/parser_bugs.v:206: VAR 'typedef' 'boolean' 'module' '' 'enum' '' '' verilog/parser_bugs.v:207: VAR 'var' 'STATE' 'module' '' 'logic [1:0]' '' '' verilog/parser_bugs.v:207: VAR 'var' 'NSTATE' 'module' '' 'logic [1:0]' '' '' verilog/parser_bugs.v:208: ENDMODULE 'endmodule' verilog/parser_bugs.v:210: MODULE 'module' 'invec' undef '0' verilog/parser_bugs.v:211: VAR 'port' 'novec' 'module' '' 'logic' '' '' verilog/parser_bugs.v:211: PORT 'novec' 'module' 'output' 'logic' '' '1' verilog/parser_bugs.v:212: VAR 'port' 'range' 'module' '' 'logic [7:0]' '' '' verilog/parser_bugs.v:212: PORT 'range' 'module' 'output' 'logic [7:0]' '' '2' verilog/parser_bugs.v:213: VAR 'port' 'arrayAndRange' 'module' '' 'logic [1:0][7:0]' '' '' verilog/parser_bugs.v:213: PORT 'arrayAndRange' 'module' 'output' 'logic [1:0][7:0]' '' '3' verilog/parser_bugs.v:214: VAR 'port' 'arrayAndArrayAndRange' 'module' '' 'logic [2:0][1:0][7:0]' '' '' verilog/parser_bugs.v:214: PORT 'arrayAndArrayAndRange' 'module' 'output' 'logic [2:0][1:0][7:0]' '' '4' verilog/parser_bugs.v:215: VAR 'port' 'novec2' 'module' '' 'reg signed' '' '' verilog/parser_bugs.v:215: PORT 'novec2' 'module' 'output' 'reg signed' '' '5' verilog/parser_bugs.v:217: ENDMODULE 'endmodule' verilog/parser_bugs.v:219: MODULE 'module' 'bug34575' undef '0' verilog/parser_bugs.v:220: VAR 'net' 'a' 'module' 'wire' '' '' '' verilog/parser_bugs.v:220: VAR 'net' 'b' 'module' 'wire' '' '' '' verilog/parser_bugs.v:220: VAR 'net' 'c' 'module' 'wire' '' '' '' verilog/parser_bugs.v:220: VAR 'net' 'd' 'module' 'wire' '' '' '' verilog/parser_bugs.v:221: CONTASSIGN 'assign' 'a' '1' verilog/parser_bugs.v:222: CONTASSIGN 'assign' 'b' '1' verilog/parser_bugs.v:223: CONTASSIGN 'assign' 'c' '1' verilog/parser_bugs.v:224: CONTASSIGN 'assign' 'd' '1' verilog/parser_bugs.v:225: ENDMODULE 'endmodule' verilog/parser_bugs.v:227: MODULE 'module' 'bug34649' undef '0' verilog/parser_bugs.v:227: PORT 'name' 'module' '' '' '' '1' verilog/parser_bugs.v:228: VAR 'port' 'name' 'module' '' 'reg' '' '0' verilog/parser_bugs.v:228: PORT 'name' 'module' 'output' 'reg' '' '0' verilog/parser_bugs.v:229: ENDMODULE 'endmodule' verilog/parser_bugs.v:230: MODULE 'module' 'bug34649b' undef '0' verilog/parser_bugs.v:231: VAR 'port' 'name' 'module' '' 'reg' '' '0' verilog/parser_bugs.v:231: PORT 'name' 'module' 'output' 'reg' '' '1' verilog/parser_bugs.v:233: ENDMODULE 'endmodule' verilog/parser_bugs.v:234: MODULE 'module' 'bug10' undef '0' verilog/parser_bugs.v:246: COMMENT '// Part of expression' verilog/parser_bugs.v:250: COMMENT '// Statement' verilog/parser_bugs.v:255: ENDMODULE 'endmodule' verilog/parser_bugs.v:257: MODULE 'module' 'bug33' undef '0' verilog/parser_bugs.v:258: VAR 'var' 'i' 'module' '' 'integer' '' '' verilog/parser_bugs.v:266: ENDMODULE 'endmodule' verilog/parser_bugs.v:268: MODULE 'module' 'bug16' undef '0' verilog/parser_bugs.v:271: ENDMODULE 'endmodule' verilog/parser_bugs.v:273: VAR 'parameter' 'bug39' 'netlist' '' '' '' '0' verilog/parser_bugs.v:279: MODULE 'module' 'bug64' undef '0' verilog/parser_bugs.v:280: VAR 'parameter' 'a' 'module' '' 'integer' '' '1' verilog/parser_bugs.v:280: VAR 'parameter' 'b' 'module' '' 'integer' '' '2' verilog/parser_bugs.v:281: VAR 'parameter' 'c' 'module' '' 'real' '' '3.0' verilog/parser_bugs.v:282: VAR 'parameter' 'd' 'module' '' 'realtime' '' '4.0' verilog/parser_bugs.v:283: VAR 'parameter' 'e' 'module' '' 'time' '' '5.0' verilog/parser_bugs.v:284: ENDMODULE 'endmodule' verilog/parser_bugs.v:286: MODULE 'module' 'bug166' undef '0' verilog/parser_bugs.v:287: CONTASSIGN 'assign' '{{o1,o2},o3,o4,{o5,o6}}' '{{i1,i2},i3,i4,{i5,i6}}' verilog/parser_bugs.v:288: ENDMODULE 'endmodule' verilog/parser_bugs.v:290: MODULE 'module' 'coverage20090318' undef '0' verilog/parser_bugs.v:291: TASK 'task' 'atask' verilog/parser_bugs.v:293: ENDTASKFUNC 'endtask' verilog/parser_bugs.v:294: ENDMODULE 'endmodule' verilog/parser_bugs.v:296: MODULE 'module' 'svsig' undef '0' verilog/parser_bugs.v:297: FUNCTION 'function' 'count' 'int' verilog/parser_bugs.v:297: VAR 'port' 'd' 'function' '' 'logic [3:0]' '' '' verilog/parser_bugs.v:297: PORT 'd' 'function' 'input' 'logic [3:0]' '' '1' verilog/parser_bugs.v:298: VAR 'var' 'count' 'function' '' 'int' '' 'd[0]+d[1]+d[2]+d[3]' verilog/parser_bugs.v:303: ENDTASKFUNC 'endfunction' verilog/parser_bugs.v:304: TASK 'task' 'autoconst' verilog/parser_bugs.v:305: VAR 'var' 'CONS' 'task' '' 'const int' '' '8' verilog/parser_bugs.v:308: ENDTASKFUNC 'endtask' verilog/parser_bugs.v:309: ENDMODULE 'endmodule' verilog/parser_bugs.v:311: MODULE 'module' 'bug_empty_func_param' undef '0' verilog/parser_bugs.v:312: COMMENT '//function int intfunc(int a=0, b=1);' verilog/parser_bugs.v:313: COMMENT '// return a+b;' verilog/parser_bugs.v:314: COMMENT '//endfunction' verilog/parser_bugs.v:321: ENDMODULE 'endmodule' verilog/parser_bugs.v:323: MODULE 'module' 'dotted_funcs' undef '0' verilog/parser_bugs.v:324: COMMENT '// Call task' verilog/parser_bugs.v:325: COMMENT '// Call function' verilog/parser_bugs.v:326: ENDMODULE 'endmodule' verilog/parser_bugs.v:328: MODULE 'module' 'var_only_in_block' undef '0' verilog/parser_bugs.v:330: VAR 'var' 'only_a_var_in_blk' 'module' '' 'integer' '' '' verilog/parser_bugs.v:332: ENDMODULE 'endmodule' verilog/parser_bugs.v:334: MODULE 'module' 'v2k_vec_no_vec' undef '0' verilog/parser_bugs.v:335: VAR 'port' 'VEC' 'module' '' '[2:0]' '' '' verilog/parser_bugs.v:335: PORT 'VEC' 'module' 'input' '[2:0]' '' '1' verilog/parser_bugs.v:336: VAR 'port' 'VEC2' 'module' '' '[2:0]' '' '' verilog/parser_bugs.v:336: PORT 'VEC2' 'module' 'input' '[2:0]' '' '2' verilog/parser_bugs.v:336: COMMENT '// No direction, no port, no data type; inherits' verilog/parser_bugs.v:337: VAR 'port' 'NOVEC' 'module' '' '' '' '' verilog/parser_bugs.v:337: PORT 'NOVEC' 'module' 'input' '' '' '3' verilog/parser_bugs.v:337: COMMENT '// No direction, no data type; use `default_nettype' verilog/parser_bugs.v:338: VAR 'port' 'ARY' 'module' '' '' '[1:0]' '' verilog/parser_bugs.v:338: PORT 'ARY' 'module' 'input' '' '[1:0]' '4' verilog/parser_bugs.v:339: VAR 'port' 'NOARY2' 'module' '' '' '' '' verilog/parser_bugs.v:339: PORT 'NOARY2' 'module' 'input' '' '' '5' verilog/parser_bugs.v:339: COMMENT '// Array doesn't inherit' verilog/parser_bugs.v:340: VAR 'port' 'STILL_IN' 'module' '' 'logic' '' '' verilog/parser_bugs.v:340: PORT 'STILL_IN' 'module' 'input' 'logic' '' '6' verilog/parser_bugs.v:340: COMMENT '// No direction, data type; inherits direction' verilog/parser_bugs.v:341: COMMENT '// Logic type' verilog/parser_bugs.v:341: VAR 'port' 'TYPED' 'module' '' 'logic' '' '' verilog/parser_bugs.v:341: PORT 'TYPED' 'module' 'input' 'logic' '' '7' verilog/parser_bugs.v:343: TASK 'task' 't' verilog/parser_bugs.v:343: VAR 'port' 'FVEC' 'task' '' '[2:0]' '' '' verilog/parser_bugs.v:343: PORT 'FVEC' 'task' 'input' '[2:0]' '' '1' verilog/parser_bugs.v:343: VAR 'port' 'FVEC2' 'task' '' '[2:0]' '' '' verilog/parser_bugs.v:343: PORT 'FVEC2' 'task' 'input' '[2:0]' '' '2' verilog/parser_bugs.v:344: VAR 'port' 'NOVEC' 'task' '' '' '' '' verilog/parser_bugs.v:344: PORT 'NOVEC' 'task' 'input' '' '' '3' verilog/parser_bugs.v:346: ENDTASKFUNC 'endtask' verilog/parser_bugs.v:347: ENDMODULE 'endmodule' verilog/parser_bugs.v:349: MODULE 'module' 'bugfor' undef '0' verilog/parser_bugs.v:351: ENDMODULE 'endmodule' verilog/parser_bugs.v:353: MODULE 'module' 'bug85' undef '0' verilog/parser_bugs.v:353: VAR 'parameter' 'T_DATA' 'module' '' 'type' '' 'byte' verilog/parser_bugs.v:354: PORT 'data' 'module' '' '' '' '1' verilog/parser_bugs.v:355: VAR 'port' 'data' 'module' '' 'T_DATA' '' '' verilog/parser_bugs.v:355: PORT 'data' 'module' 'input' 'T_DATA' '' '0' verilog/parser_bugs.v:357: INSTANT 'sub' 'sub' '' verilog/parser_bugs.v:356: PARAMPIN 'T_DATA' 'T_DATA' '1' verilog/parser_bugs.v:357: PIN 'data' 'data' '1' verilog/parser_bugs.v:357: PINSELECTS 'data' '[{'netname' => 'data'}]' '1' verilog/parser_bugs.v:357: ENDCELL '' verilog/parser_bugs.v:358: ENDMODULE 'endmodule' verilog/parser_bugs.v:360: MODULE 'module' 'bugmodportcomma' undef '0' verilog/parser_bugs.v:360: PORT 'a' 'module' '' '' '' '1' verilog/parser_bugs.v:361: VAR 'port' 'a' 'module' '' '' '' '' verilog/parser_bugs.v:361: PORT 'a' 'module' 'input' '' '' '0' verilog/parser_bugs.v:362: ENDMODULE 'endmodule' verilog/parser_bugs.v:364: MODULE 'module' 'bug168' undef '0' verilog/parser_bugs.v:369: ENDMODULE 'endmodule' verilog/parser_bugs.v:371: MODULE 'module' 'bug183' undef '0' verilog/parser_bugs.v:372: VAR 'parameter' 'NUM' 'module' '' '' '' '9' verilog/parser_bugs.v:373: VAR 'parameter' 'WIDTH' 'module' '' '' '' '8' verilog/parser_bugs.v:374: VAR 'port' 'a' 'module' '' 'logic [NUM-1:0][WIDTH-1:0]' '' '' verilog/parser_bugs.v:374: PORT 'a' 'module' 'input' 'logic [NUM-1:0][WIDTH-1:0]' '' '1' verilog/parser_bugs.v:375: VAR 'port' 'sum' 'module' '' 'logic [WIDTH-1:0]' '' '' verilog/parser_bugs.v:375: PORT 'sum' 'module' 'output' 'logic [WIDTH-1:0]' '' '2' verilog/parser_bugs.v:377: VAR 'localparam' 'NLOG' 'module' '' '' '' '(NUM<=2)?1:(NUM<=1024)?10:0' verilog/parser_bugs.v:381: VAR 'typedef' 'val_t' 'module' '' 'logic [WIDTH-1:0]' '' '' verilog/parser_bugs.v:382: VAR 'var' 'tree' 'module' '' 'val_t[NLOG:0][NUM-1:0]' '' '' verilog/parser_bugs.v:383: ENDMODULE 'endmodule' verilog/parser_bugs.v:385: MODULE 'module' 'bug192' undef '0' verilog/parser_bugs.v:386: COVERGROUP 'covergroup' 'cg192' verilog/parser_bugs.v:390: ENDGROUP 'endgroup' verilog/parser_bugs.v:391: VAR 'var' 'cover_ts' 'module' '' 'cg192' '' 'new()' verilog/parser_bugs.v:391: COMMENT '// also bug361' verilog/parser_bugs.v:392: ENDMODULE 'endmodule' verilog/parser_bugs.v:394: FUNCTION 'function' 'func_implied_in' 'bit' verilog/parser_bugs.v:394: VAR 'port' 'i' 'function' '' 'bit' '' '' verilog/parser_bugs.v:394: PORT 'i' 'function' 'input' 'bit' '' '1' verilog/parser_bugs.v:394: ENDTASKFUNC 'endfunction' verilog/parser_bugs.v:396: MODULE 'module' 'sparam' undef '0' verilog/parser_bugs.v:400: COMMENT '// bug221' verilog/parser_bugs.v:398: ENDMODULE 'endmodule' verilog/parser_bugs.v:401: VAR 'port' 'sig' 'sequence' '' '' '' '' verilog/parser_bugs.v:401: PORT 'sig' 'sequence' 'input' '' '' '1' verilog/parser_bugs.v:401: VAR 'port' 'clks_before' 'sequence' '' '' '' '' verilog/parser_bugs.v:401: PORT 'clks_before' 'sequence' 'input' '' '' '2' verilog/parser_bugs.v:401: VAR 'port' 'clk' 'sequence' '' '' '' '' verilog/parser_bugs.v:401: PORT 'clk' 'sequence' 'input' '' '' '3' verilog/parser_bugs.v:401: VAR 'port' 'rst' 'sequence' '' '' '' '1'b0' verilog/parser_bugs.v:401: PORT 'rst' 'sequence' 'input' '' '' '4' verilog/parser_bugs.v:405: VAR 'port' 'sample' 'property' '' '' '' '' verilog/parser_bugs.v:405: PORT 'sample' 'property' 'input' '' '' '1' verilog/parser_bugs.v:405: VAR 'port' 'sig' 'property' '' '' '' '' verilog/parser_bugs.v:405: PORT 'sig' 'property' 'input' '' '' '2' verilog/parser_bugs.v:405: VAR 'port' 'clks_before' 'property' '' '' '' '' verilog/parser_bugs.v:405: PORT 'clks_before' 'property' 'input' '' '' '3' verilog/parser_bugs.v:405: VAR 'port' 'clks_after' 'property' '' '' '' '' verilog/parser_bugs.v:405: PORT 'clks_after' 'property' 'input' '' '' '4' verilog/parser_bugs.v:405: VAR 'port' 'clk' 'property' '' '' '' '$default_clk' verilog/parser_bugs.v:405: PORT 'clk' 'property' 'input' '' '' '5' verilog/parser_bugs.v:405: VAR 'port' 'rst' 'property' '' '' '' '1'b0' verilog/parser_bugs.v:405: PORT 'rst' 'property' 'input' '' '' '6' verilog/parser_bugs.v:411: VAR 'port' 'prop' 'property' '' '' '' '' verilog/parser_bugs.v:411: PORT 'prop' 'property' 'input' '' '' '1' verilog/parser_bugs.v:411: VAR 'port' 'clk' 'property' '' '' '' '$default_clk' verilog/parser_bugs.v:411: PORT 'clk' 'property' 'input' '' '' '2' verilog/parser_bugs.v:411: VAR 'port' 'rst' 'property' '' '' '' '1'b0' verilog/parser_bugs.v:411: PORT 'rst' 'property' 'input' '' '' '3' verilog/parser_bugs.v:415: VAR 'port' 'trig' 'property' '' '' '' '' verilog/parser_bugs.v:415: PORT 'trig' 'property' 'input' '' '' '1' verilog/parser_bugs.v:415: VAR 'port' 'n' 'property' '' '' '' '' verilog/parser_bugs.v:415: PORT 'n' 'property' 'input' '' '' '2' verilog/parser_bugs.v:415: VAR 'port' 'cond' 'property' '' '' '' '' verilog/parser_bugs.v:415: PORT 'cond' 'property' 'input' '' '' '3' verilog/parser_bugs.v:415: VAR 'port' 'clk' 'property' '' '' '' '$default_clk' verilog/parser_bugs.v:415: PORT 'clk' 'property' 'input' '' '' '4' verilog/parser_bugs.v:415: VAR 'port' 'rst' 'property' '' '' '' '1'b0' verilog/parser_bugs.v:415: PORT 'rst' 'property' 'input' '' '' '5' verilog/parser_bugs.v:421: VAR 'port' 'start_ev' 'property' '' '' '' '' verilog/parser_bugs.v:421: PORT 'start_ev' 'property' 'input' '' '' '1' verilog/parser_bugs.v:421: VAR 'port' 'start_data' 'property' '' '' '' '' verilog/parser_bugs.v:421: PORT 'start_data' 'property' 'input' '' '' '2' verilog/parser_bugs.v:421: VAR 'port' 'end_ev' 'property' '' '' '' '' verilog/parser_bugs.v:421: PORT 'end_ev' 'property' 'input' '' '' '3' verilog/parser_bugs.v:421: VAR 'port' 'end_data' 'property' '' '' '' '' verilog/parser_bugs.v:421: PORT 'end_data' 'property' 'input' '' '' '4' verilog/parser_bugs.v:421: VAR 'port' 'clk' 'property' '' '' '' '$default_clk' verilog/parser_bugs.v:421: PORT 'clk' 'property' 'input' '' '' '5' verilog/parser_bugs.v:421: VAR 'port' 'rst' 'property' '' '' '' '1'b0' verilog/parser_bugs.v:421: PORT 'rst' 'property' 'input' '' '' '6' verilog/parser_bugs.v:429: MODULE 'module' 'bug228' undef '0' verilog/parser_bugs.v:430: VAR 'net' 'net1' 'module' 'wire' '' '' '' verilog/parser_bugs.v:430: VAR 'net' 'net2' 'module' 'wire' '' '' '' verilog/parser_bugs.v:430: VAR 'net' 'net3' 'module' 'wire' '' '' '' verilog/parser_bugs.v:431: INSTANT 'nmos' 'u' '' verilog/parser_bugs.v:431: PARAMPIN '' '0' '1' verilog/parser_bugs.v:431: PARAMPIN '' '0' '2' verilog/parser_bugs.v:431: PARAMPIN '' '0' '3' verilog/parser_bugs.v:431: PIN '' 'net1' '1' verilog/parser_bugs.v:431: PINSELECTS '' '[{'netname' => 'net1'}]' '1' verilog/parser_bugs.v:431: PIN '' 'net2' '2' verilog/parser_bugs.v:431: PINSELECTS '' '[{'netname' => 'net2'}]' '2' verilog/parser_bugs.v:431: PIN '' 'net3' '3' verilog/parser_bugs.v:431: PINSELECTS '' '[{'netname' => 'net3'}]' '3' verilog/parser_bugs.v:431: ENDCELL '' verilog/parser_bugs.v:432: ENDMODULE 'endmodule' verilog/parser_bugs.v:434: MODULE 'module' 'bug262' undef '0' verilog/parser_bugs.v:434: PORT 'Y' 'module' '' '' '' '1' verilog/parser_bugs.v:434: PORT 'A1' 'module' '' '' '' '2' verilog/parser_bugs.v:434: PORT 'A2' 'module' '' '' '' '3' verilog/parser_bugs.v:434: PORT 'B' 'module' '' '' '' '4' verilog/parser_bugs.v:435: VAR 'port' 'Y' 'module' '' '' '' '' verilog/parser_bugs.v:435: PORT 'Y' 'module' 'output' '' '' '0' verilog/parser_bugs.v:436: VAR 'port' 'A1' 'module' '' '' '' '' verilog/parser_bugs.v:436: PORT 'A1' 'module' 'input' '' '' '0' verilog/parser_bugs.v:436: VAR 'port' 'A2' 'module' '' '' '' '' verilog/parser_bugs.v:436: PORT 'A2' 'module' 'input' '' '' '0' verilog/parser_bugs.v:436: VAR 'port' 'B' 'module' '' '' '' '' verilog/parser_bugs.v:436: PORT 'B' 'module' 'input' '' '' '0' verilog/parser_bugs.v:437: ENDMODULE 'endmodule' verilog/parser_bugs.v:439: VAR 'net' '\wire ' 'netlist' 'wire' '' '' 'bug282_must_keep_escape' verilog/parser_bugs.v:441: MODULE 'module' 'bug403_bug404' undef '0' verilog/parser_bugs.v:442: COMMENT '// Simulators vary as to if "(* /* */ )" is legal or not' verilog/parser_bugs.v:443: ATTRIBUTE '(* attr *)' verilog/parser_bugs.v:443: VAR 'net' 'foo' 'module' 'wire' '' '' '' verilog/parser_bugs.v:449: COMMENT '/* multi line bug459*/' verilog/parser_bugs.v:447: ENDMODULE 'endmodule' verilog/parser_bugs.v:453: MODULE 'module' 'bug422' undef '0' verilog/parser_bugs.v:456: ENDMODULE 'endmodule' verilog/parser_bugs.v:458: MODULE 'module' 'bug461' undef '0' verilog/parser_bugs.v:460: VAR 'genvar' 'g' 'module' '' '' '' '' verilog/parser_bugs.v:460: COMMENT '// bug461' verilog/parser_bugs.v:462: VAR 'genvar' 'g2' 'module' '' '' '' '' verilog/parser_bugs.v:463: VAR 'genvar' 'g1' 'module' '' '' '' '' verilog/parser_bugs.v:469: ENDMODULE 'endmodule' verilog/parser_bugs.v:471: MODULE 'module' 'bug507' undef '0' verilog/parser_bugs.v:472: VAR 'var' 'x' 'module' '' 'integer' '' '32'd 6' verilog/parser_bugs.v:476: COMMENT '// bug_msg_887;' verilog/parser_bugs.v:474: ENDMODULE 'endmodule' verilog/parser_bugs.v:477: INSTANT 'example_mod_fcov' 'uexample_mod_fcov' '' verilog/parser_bugs.v:477: PIN '*' '*' '1' verilog/parser_bugs.v:477: PINSELECTS '*' '[{'netname' => '*'}]' '1' verilog/parser_bugs.v:477: ENDCELL '' verilog/parser_bugs.v:479: PACKAGE 'package' 'bug586_pkg' verilog/parser_bugs.v:480: VAR 'parameter' 'B' 'package' '' '' '' '10' verilog/parser_bugs.v:481: ENDPACKAGE 'endpackage' verilog/parser_bugs.v:482: MODULE 'module' 'non_bug586' undef '0' verilog/parser_bugs.v:482: COMMENT '// Verilator only' verilog/parser_bugs.v:483: VAR 'port' 'bvar' 'module' '' 'logic [bug586_pkg::B:0]' '' '' verilog/parser_bugs.v:483: PORT 'bvar' 'module' 'input' 'logic [bug586_pkg::B:0]' '' '0' verilog/parser_bugs.v:486: COMMENT '// bug_641' verilog/parser_bugs.v:484: ENDMODULE 'endmodule' verilog/parser_bugs.v:487: FUNCTION 'function' 'mydpi_bug641' 'bit' verilog/parser_bugs.v:487: VAR 'port' 'a_dpi_input' 'function' '' '' '' '' verilog/parser_bugs.v:487: PORT 'a_dpi_input' 'function' 'input' '' '' '1' verilog/parser_bugs.v:487: ENDTASKFUNC 'endfunction' verilog/parser_bugs.v:489: COMMENT '// .f() in function call' verilog/parser_bugs.v:490: MODULE 'module' 'fbug' undef '0' verilog/parser_bugs.v:496: ENDMODULE 'endmodule' verilog/parser_bugs.v:498: VAR 'parameter' 'bug671' 'netlist' '' '' '' '5:10:20' verilog/parser_bugs.v:500: MODULE 'module' 'bug256' undef '0' verilog/parser_bugs.v:504: COMMENT '// [#] [100] ['b0]' verilog/parser_bugs.v:507: ENDMODULE 'endmodule' verilog/parser_bugs.v:509: MODULE 'module' 'msg1491' undef '0' verilog/parser_bugs.v:509: PORT 'A' 'module' '' '' '' '1' verilog/parser_bugs.v:509: PORT 'B' 'module' '' '' '' '2' verilog/parser_bugs.v:510: VAR 'port' 'A' 'module' '' '' '' '' verilog/parser_bugs.v:510: PORT 'A' 'module' 'output' '' '' '0' verilog/parser_bugs.v:511: VAR 'net' 'A' 'module' 'trireg' '' '' '' verilog/parser_bugs.v:512: VAR 'port' 'B' 'module' 'trireg' '' '' '' verilog/parser_bugs.v:512: PORT 'B' 'module' 'output' '' '' '0' verilog/parser_bugs.v:513: ENDMODULE 'endmodule' verilog/parser_bugs.v:515: MODULE 'module' 'msg2540' undef '0' verilog/parser_bugs.v:516: VAR 'port' 'foo' 'module' '' 'signed' '' '' verilog/parser_bugs.v:516: PORT 'foo' 'module' 'output' 'signed' '' '1' verilog/parser_bugs.v:517: ENDMODULE 'endmodule' verilog/parser_bugs.v:519: MODULE 'module' 'prot' undef '0' verilog/parser_bugs.v:524: ENDMODULE 'endmodule' verilog/parser_bugs.v:526: MODULE 'module' 'prot2' undef '0' verilog/parser_bugs.v:540: ENDMODULE 'endmodule' verilog/parser_bugs.v:542: MODULE 'module' 'prot3' undef '0' verilog/parser_bugs.v:564: ENDMODULE 'endmodule' verilog/parser_bugs.v:566: MODULE 'module' 'bug1340' undef '0' verilog/parser_bugs.v:567: VAR 'parameter' 'B' 'module' '' '' '' '8 'b 1' verilog/parser_bugs.v:572: ENDMODULE 'endmodule' verilog/parser_bugs.v:574: MODULE 'module' 'msg2931' undef '0' verilog/parser_bugs.v:576: VAR 'var' 'mynet1' 'module' '' 'net1_t' '' '' verilog/parser_bugs.v:578: VAR 'var' 'mynet2' 'module' '' 'net2_t' '' '' verilog/parser_bugs.v:580: VAR 'var' 'mynet3' 'module' '' 'net3_t' '' '' verilog/parser_bugs.v:581: ENDMODULE 'endmodule' verilog/parser_bugs.v:583: MODULE 'module' 'bug1505' undef '0' verilog/parser_bugs.v:584: INSTANT 'sub' 'i_suba' '' verilog/parser_bugs.v:584: ENDCELL '' verilog/parser_bugs.v:585: INSTANT 'sub' 'i_subb' '[1:2]' verilog/parser_bugs.v:585: ENDCELL '' verilog/parser_bugs.v:586: INSTANT 'sub' 'i_subc' '[1:2][3:4][5:6]' verilog/parser_bugs.v:586: ENDCELL '' verilog/parser_bugs.v:587: ENDMODULE 'endmodule' verilog/pinorder.v:001: COMMENT '// DESCRIPTION: Verilog-Perl: Example Verilog for testing package' verilog/pinorder.v:002: COMMENT '//' verilog/pinorder.v:003: COMMENT '// This file ONLY is placed into the Public Domain, for any use,' verilog/pinorder.v:004: COMMENT '// without warranty, 2003 by Wilson Snyder.' verilog/pinorder.v:006: MODULE 'module' 'pinorder4' undef '0' verilog/pinorder.v:007: VAR 'net' 'b_i' 'module' 'wire' '' '' '' verilog/pinorder.v:008: VAR 'net' 'd_o' 'module' 'wire' '' '' '' verilog/pinorder.v:009: VAR 'net' 'a_i' 'module' 'wire' '[7:0]' '' '' verilog/pinorder.v:010: VAR 'net' 'IPCD_const' 'module' 'wire' '[31:0]' '' '32'h1' verilog/pinorder.v:012: CONTASSIGN 'assign' 'a_i' '0' verilog/pinorder.v:013: CONTASSIGN 'assign' 'b_i' '0' verilog/pinorder.v:015: INSTANT 'foo' 'foo1' '' verilog/pinorder.v:015: PIN 'y' 'b_i' '1' verilog/pinorder.v:015: PINSELECTS 'y' '[{'netname' => 'b_i'}]' '1' verilog/pinorder.v:015: PIN 'x' 'a_i' '2' verilog/pinorder.v:015: PINSELECTS 'x' '[{'netname' => 'a_i'}]' '2' verilog/pinorder.v:015: PIN 'abcconst' '3'h0' '3' verilog/pinorder.v:015: PINSELECTS 'abcconst' '[{'netname' => '3\'h0'}]' '3' verilog/pinorder.v:015: PIN 'noconnect' '' '4' verilog/pinorder.v:015: PINSELECTS 'noconnect' '[{'netname' => ''}]' '4' verilog/pinorder.v:016: PIN 'def' 'IPCD_const' '5' verilog/pinorder.v:016: PINSELECTS 'def' '[{'netname' => 'IPCD_const'}]' '5' verilog/pinorder.v:016: ENDCELL '' verilog/pinorder.v:017: INSTANT 'foo' 'foo3' '' verilog/pinorder.v:017: PIN '' 'b_i' '1' verilog/pinorder.v:017: PINSELECTS '' '[{'netname' => 'b_i'}]' '1' verilog/pinorder.v:017: PIN '' 'a_i' '2' verilog/pinorder.v:017: PINSELECTS '' '[{'netname' => 'a_i'}]' '2' verilog/pinorder.v:017: PIN '' '3'h0' '3' verilog/pinorder.v:017: PINSELECTS '' '[{'netname' => '3\'h0'}]' '3' verilog/pinorder.v:017: PIN '' 'IPCD_const' '5' verilog/pinorder.v:017: PINSELECTS '' '[{'netname' => 'IPCD_const'}]' '5' verilog/pinorder.v:017: ENDCELL '' verilog/pinorder.v:018: INSTANT 'foo2' 'foo2' '' verilog/pinorder.v:018: PIN '' 'b_i' '1' verilog/pinorder.v:018: PINSELECTS '' '[{'netname' => 'b_i'}]' '1' verilog/pinorder.v:018: PIN '' 'a_i[0]' '2' verilog/pinorder.v:018: PINSELECTS '' '[{'lsb' => '0','msb' => '0','netname' => 'a_i'}]' '2' verilog/pinorder.v:018: PIN '' 'd_o' '3' verilog/pinorder.v:018: PINSELECTS '' '[{'netname' => 'd_o'}]' '3' verilog/pinorder.v:018: ENDCELL '' verilog/pinorder.v:020: ENDMODULE 'endmodule' verilog/pinorder.v:022: MODULE 'module' 'foo2' undef '0' verilog/pinorder.v:022: COMMENT '/*AUTOARG*/' verilog/pinorder.v:023: COMMENT '// Outputs' verilog/pinorder.v:024: PORT 'x' 'module' '' '' '' '1' verilog/pinorder.v:025: COMMENT '// Inputs' verilog/pinorder.v:026: PORT 'z' 'module' '' '' '' '2' verilog/pinorder.v:026: PORT 'y' 'module' '' '' '' '3' verilog/pinorder.v:028: VAR 'port' 'z' 'module' '' '' '' '' verilog/pinorder.v:028: PORT 'z' 'module' 'input' '' '' '0' verilog/pinorder.v:029: VAR 'port' 'y' 'module' '' '' '' '' verilog/pinorder.v:029: PORT 'y' 'module' 'input' '' '' '0' verilog/pinorder.v:030: VAR 'port' 'x' 'module' '' '' '' '' verilog/pinorder.v:030: PORT 'x' 'module' 'output' '' '' '0' verilog/pinorder.v:031: VAR 'var' 'x' 'module' '' 'reg' '' '' verilog/pinorder.v:033: ENDMODULE 'endmodule' verilog/pinorder.v:035: MODULE 'module' 'foo' undef '0' verilog/pinorder.v:035: COMMENT '/*AUTOARG*/' verilog/pinorder.v:036: COMMENT '// Inputs' verilog/pinorder.v:037: PORT 'y' 'module' '' '' '' '1' verilog/pinorder.v:037: PORT 'x' 'module' '' '' '' '2' verilog/pinorder.v:037: PORT 'abcconst' 'module' '' '' '' '3' verilog/pinorder.v:037: PORT 'noconnect' 'module' '' '' '' '4' verilog/pinorder.v:037: PORT 'def' 'module' '' '' '' '5' verilog/pinorder.v:039: VAR 'port' 'y' 'module' '' '' '' '' verilog/pinorder.v:039: PORT 'y' 'module' 'input' '' '' '0' verilog/pinorder.v:040: VAR 'port' 'x' 'module' '' '' '' '' verilog/pinorder.v:040: PORT 'x' 'module' 'input' '' '' '0' verilog/pinorder.v:041: VAR 'port' 'abcconst' 'module' '' '[2:0]' '' '' verilog/pinorder.v:041: PORT 'abcconst' 'module' 'input' '[2:0]' '' '0' verilog/pinorder.v:042: VAR 'port' 'noconnect' 'module' '' 'signed [3:0]' '' '' verilog/pinorder.v:042: PORT 'noconnect' 'module' 'input' 'signed [3:0]' '' '0' verilog/pinorder.v:043: VAR 'port' 'def' 'module' '' '[31:0]' '' '' verilog/pinorder.v:043: PORT 'def' 'module' 'input' '[31:0]' '' '0' verilog/pinorder.v:044: ENDMODULE 'endmodule' verilog/pinorder.v:046: MODULE 'module' 'bug278' undef '0' verilog/pinorder.v:048: VAR 'port' 'ow' 'module' 'wire' '' '' '' verilog/pinorder.v:048: PORT 'ow' 'module' 'output' '' '' '1' verilog/pinorder.v:049: VAR 'port' 'iow' 'module' 'wire' '' '' '' verilog/pinorder.v:049: PORT 'iow' 'module' 'inout' '' '' '2' verilog/pinorder.v:050: VAR 'port' 'iw' 'module' 'wire' '' '' '' verilog/pinorder.v:050: PORT 'iw' 'module' 'input' '' '' '3' verilog/pinorder.v:051: ENDMODULE 'endmodule' verilog/parser_sv.v:001: PACKAGE 'package' 'mypackage' verilog/parser_sv.v:002: VAR 'var' 'pkg_addr' 'package' '' 'bit [7:0]' '' '' verilog/parser_sv.v:003: VAR 'var' 'pkg_data' 'package' '' 'bit [7:0]' '' '' verilog/parser_sv.v:004: ENDPACKAGE 'endpackage' verilog/parser_sv.v:006: MODULE 'module' 'times' undef '0' verilog/parser_sv.v:007: VAR 'var' 'x' 'module' '' 'time' '' '' verilog/parser_sv.v:008: COMMENT '// Note no space' verilog/parser_sv.v:009: ENDMODULE 'endmodule' verilog/parser_sv.v:011: INTERFACE 'interface' 'itf' verilog/parser_sv.v:011: VAR 'parameter' 'num_of_cli' 'interface' '' '' '' '0' verilog/parser_sv.v:012: VAR 'var' 'blabla' 'interface' '' 'logic' '' '' verilog/parser_sv.v:013: VAR 'var' 'addr' 'interface' '' 'logic [7:0]' '' '' verilog/parser_sv.v:013: VAR 'var' 'data' 'interface' '' 'logic [7:0]' '[9]' '' verilog/parser_sv.v:014: MODPORT 'modport' 'Master' verilog/parser_sv.v:014: VAR 'port' 'data' 'modport' '' '' '' 'data' verilog/parser_sv.v:014: PORT 'data' 'modport' 'input' '' '' '1' verilog/parser_sv.v:014: VAR 'port' 'date_delayed' 'modport' '' '' '' 'date_delayed' verilog/parser_sv.v:014: PORT 'date_delayed' 'modport' 'input' '' '' '2' verilog/parser_sv.v:014: VAR 'port' 'addr' 'modport' '' '' '' 'addr' verilog/parser_sv.v:014: PORT 'addr' 'modport' 'output' '' '' '3' verilog/parser_sv.v:014: ENDMODPORT 'endmodport' verilog/parser_sv.v:015: ENDINTERFACE 'endinterface' verilog/parser_sv.v:017: MODULE 'module' 'test' undef '0' verilog/parser_sv.v:018: VAR 'port' 'whole_int' 'module' '' 'itf' '' '' verilog/parser_sv.v:018: PORT 'whole_int' 'module' 'interface' 'itf' '' '1' verilog/parser_sv.v:018: INSTANT 'itf' 'whole_int' '' verilog/parser_sv.v:018: ENDCELL '' verilog/parser_sv.v:019: VAR 'port' 'modported_int' 'module' '' 'itf.test' '' '' verilog/parser_sv.v:019: PORT 'modported_int' 'module' 'interface' 'itf.test' '' '2' verilog/parser_sv.v:019: INSTANT 'itf' 'modported_int' '' verilog/parser_sv.v:019: ENDCELL '' verilog/parser_sv.v:020: VAR 'port' 'clk' 'module' '' 'logic' '' '' verilog/parser_sv.v:020: PORT 'clk' 'module' 'input' 'logic' '' '3' verilog/parser_sv.v:020: VAR 'port' 'rst' 'module' '' 'logic' '' '' verilog/parser_sv.v:020: PORT 'rst' 'module' 'input' 'logic' '' '4' verilog/parser_sv.v:021: VAR 'port' 'd_in' 'module' '' 'logic' '' '' verilog/parser_sv.v:021: PORT 'd_in' 'module' 'input' 'logic' '' '5' verilog/parser_sv.v:022: VAR 'port' 'd_out' 'module' '' 'logic' '' '' verilog/parser_sv.v:022: PORT 'd_out' 'module' 'output' 'logic' '' '6' verilog/parser_sv.v:025: IMPORT 'mypackage' '*' verilog/parser_sv.v:027: VAR 'var' 'd_int' 'module' '' 'logic' '' '' verilog/parser_sv.v:028: VAR 'var' 'data_' 'module' '' 'logic [7:0]' '' '' verilog/parser_sv.v:028: VAR 'var' 'bork' 'module' '' 'logic [7:0]' '[2]' '' verilog/parser_sv.v:029: CONTASSIGN 'assign' 'd_int' 'd_in+pkg_data' verilog/parser_sv.v:031: CONTASSIGN 'assign' 'modported_int.data' 'data_' verilog/parser_sv.v:044: COMMENT '//a1: assert property(p1) else $warning("\nProperty violated\n");' verilog/parser_sv.v:046: ENDMODULE 'endmodule' verilog/parser_sv.v:048: COMMENT '// Different ways of declaring pins/vars' verilog/parser_sv.v:049: MODULE 'module' 'line49_diff_pins1' undef '0' verilog/parser_sv.v:050: VAR 'port' 'in_nw' 'module' '' '' '' '' verilog/parser_sv.v:050: PORT 'in_nw' 'module' 'input' '' '' '1' verilog/parser_sv.v:050: COMMENT '// Input, no type' verilog/parser_sv.v:051: VAR 'port' 'in_vec' 'module' '' '[1:0]' '[2:0]' '' verilog/parser_sv.v:051: PORT 'in_vec' 'module' 'input' '[1:0]' '[2:0]' '2' verilog/parser_sv.v:051: COMMENT '// Input, implicit' verilog/parser_sv.v:052: VAR 'port' 'in_nvec' 'module' '' '' '' '' verilog/parser_sv.v:052: PORT 'in_nvec' 'module' 'input' '' '' '3' verilog/parser_sv.v:052: COMMENT '// Isn't vectorized' verilog/parser_sv.v:053: VAR 'port' 'out_logic' 'module' '' 'logic' '' '' verilog/parser_sv.v:053: PORT 'out_logic' 'module' 'output' 'logic' '' '4' verilog/parser_sv.v:053: COMMENT '// Output and var' verilog/parser_sv.v:054: COMMENT '// "logic" sticks' verilog/parser_sv.v:054: VAR 'port' 'out_also_logic' 'module' '' '' '' '' verilog/parser_sv.v:054: PORT 'out_also_logic' 'module' 'output' '' '' '5' verilog/parser_sv.v:056: ENDMODULE 'endmodule' verilog/parser_sv.v:057: MODULE 'module' 'line49_diff_pins2' undef '0' verilog/parser_sv.v:057: PORT 'in2_nw' 'module' '' '' '' '1' verilog/parser_sv.v:057: PORT 'in2_vec' 'module' '' '' '' '2' verilog/parser_sv.v:057: PORT 'out2reg' 'module' '' '' '' '3' verilog/parser_sv.v:059: VAR 'port' 'in2_nw' 'module' '' '' '' '' verilog/parser_sv.v:059: PORT 'in2_nw' 'module' 'input' '' '' '0' verilog/parser_sv.v:060: VAR 'port' 'in2_vec' 'module' '' '[1:0]' '[2:0]' '' verilog/parser_sv.v:060: PORT 'in2_vec' 'module' 'input' '[1:0]' '[2:0]' '0' verilog/parser_sv.v:061: VAR 'port' 'out2_reg' 'module' '' 'reg' '' '' verilog/parser_sv.v:061: PORT 'out2_reg' 'module' 'output' 'reg' '' '0' verilog/parser_sv.v:062: VAR 'port' 'in2_signed' 'module' '' 'signed' '' '' verilog/parser_sv.v:062: PORT 'in2_signed' 'module' 'input' 'signed' '' '0' verilog/parser_sv.v:064: VAR 'var' 'var1_imp' 'module' '' '' '' '' verilog/parser_sv.v:065: VAR 'var' 'var1_imp_vec' 'module' '' '[1:0]' '[2:0]' '' verilog/parser_sv.v:066: VAR 'var' 'var1_imp_reg' 'module' '' 'reg' '' '' verilog/parser_sv.v:067: VAR 'var' 'var1_imp_logic' 'module' '' 'logic' '' '' verilog/parser_sv.v:068: ENDMODULE 'endmodule' verilog/parser_sv.v:070: PROGRAM 'program' 'first_prog' verilog/parser_sv.v:071: VAR 'var' 'i' 'program' '' 'int' '' '' verilog/parser_sv.v:074: COMMENT '// Importing' verilog/parser_sv.v:072: ENDPROGRAM 'endprogram' verilog/parser_sv.v:075: PACKAGE 'package' 'imp_test_pkg' verilog/parser_sv.v:076: VAR 'typedef' 'byte_t' 'package' '' 'logic [7:0]' '' '' verilog/parser_sv.v:077: VAR 'typedef' 'word_t' 'package' '' 'logic [15:0]' '' '' verilog/parser_sv.v:078: FUNCTION 'function' 'afunc' '' verilog/parser_sv.v:078: VAR 'port' 'w' 'function' '' 'integer' '' '' verilog/parser_sv.v:078: PORT 'w' 'function' 'input' 'integer' '' '1' verilog/parser_sv.v:078: ENDTASKFUNC 'endfunction' verilog/parser_sv.v:079: ENDPACKAGE 'endpackage' verilog/parser_sv.v:080: MODULE 'module' 'imp_test_mod' undef '0' verilog/parser_sv.v:081: IMPORT 'imp_test_pkg' 'byte_t' verilog/parser_sv.v:082: VAR 'var' 'some_byte' 'module' '' 'byte_t' '' '' verilog/parser_sv.v:083: ENDMODULE 'endmodule' verilog/parser_sv.v:084: MODULE 'module' 'imp_test_mod2' undef '0' verilog/parser_sv.v:085: IMPORT 'imp_test_pkg' '*' verilog/parser_sv.v:086: VAR 'var' 'some_word' 'module' '' 'word_t' '' '' verilog/parser_sv.v:087: ENDMODULE 'endmodule' verilog/parser_sv.v:088: MODULE 'module' 'imp_test_mod3' undef '0' verilog/parser_sv.v:089: VAR 'port' 'wordin' 'module' '' 'imp_test_pkg::word_t' '' '' verilog/parser_sv.v:089: PORT 'wordin' 'module' 'input' 'imp_test_pkg::word_t' '' '1' verilog/parser_sv.v:090: VAR 'localparam' 'FROM_FUNC' 'module' '' '' '' 'imp_test_pkg::afunc(1)' verilog/parser_sv.v:091: ENDMODULE 'endmodule' verilog/parser_sv.v:093: MODULE 'module' 'var_unnamed_block' undef '0' verilog/parser_sv.v:095: VAR 'var' 'var_in_unnamed' 'module' '' 'integer' '' '' verilog/parser_sv.v:097: ENDMODULE 'endmodule' verilog/parser_sv.v:099: MODULE 'module' 'cell_with_typeparam' undef '0' verilog/parser_sv.v:100: INSTANT 'addr' 'acell' '' verilog/parser_sv.v:100: PARAMPIN 'PARAMTYPE' 'integer' '1' verilog/parser_sv.v:100: ENDCELL '' verilog/parser_sv.v:101: ENDMODULE 'endmodule' verilog/parser_sv.v:103: MODULE 'module' 'arrayed_wire' undef '0' verilog/parser_sv.v:104: VAR 'net' 'n2' 'module' 'wire' '[3:0][7:0]' '' '' verilog/parser_sv.v:105: ENDMODULE 'endmodule' verilog/parser_sv.v:107: TASK 'task' 'empty_task' verilog/parser_sv.v:107: COMMENT '// sv design book' verilog/parser_sv.v:108: ENDTASKFUNC 'endtask' verilog/parser_sv.v:109: TASK 'task' 'empty_task2' verilog/parser_sv.v:109: COMMENT '// sv design book' verilog/parser_sv.v:110: VAR 'var' 'i' 'task' '' 'integer' '' '' verilog/parser_sv.v:111: ENDTASKFUNC 'endtask' verilog/parser_sv.v:113: TASK 'task' 'check_casts' verilog/parser_sv.v:114: VAR 'typedef' 'integer_t' 'task' '' 'integer' '' '' verilog/parser_sv.v:118: ENDTASKFUNC 'endtask' verilog/parser_sv.v:120: MODULE 'module' 'comma_assign' undef '0' verilog/parser_sv.v:121: VAR 'var' 'n' 'module' '' 'int' '[1:2][1:3]' ''{'{0,1,2},'{3}}' verilog/parser_sv.v:122: ENDMODULE 'endmodule' verilog/parser_sv.v:124: TASK 'task' 'typed_pattern' verilog/parser_sv.v:125: VAR 'typedef' 'triple' 'task' '' 'int' '[1:3]' '' verilog/parser_sv.v:127: ENDTASKFUNC 'endtask' verilog/parser_sv.v:129: CLASS 'class' 'VclassWCopy' 'virtual' verilog/parser_sv.v:130: FUNCTION 'function' 'new' '' verilog/parser_sv.v:130: ENDTASKFUNC 'endfunction' verilog/parser_sv.v:131: FUNCTION 'function' 'copy' 'VclassWCopy' verilog/parser_sv.v:131: VAR 'port' 'src' 'function' '' 'VclassWCopy' '' 'null' verilog/parser_sv.v:131: PORT 'src' 'function' 'input' 'VclassWCopy' '' '1' verilog/parser_sv.v:132: ENDTASKFUNC 'endfunction' verilog/parser_sv.v:133: ENDCLASS 'endclass' verilog/parser_sv.v:134: FUNCTION 'function' 'new' '' verilog/parser_sv.v:135: ENDTASKFUNC 'endfunction' verilog/parser_sv.v:138: FUNCTION 'function' 'FwdClass::ffunc' 'bit [3:0]' verilog/parser_sv.v:138: VAR 'port' 'in' 'function' '' 'bit [3:0]' '' '' verilog/parser_sv.v:138: PORT 'in' 'function' 'input' 'bit [3:0]' '' '1' verilog/parser_sv.v:140: ENDTASKFUNC 'endfunction' verilog/parser_sv.v:142: FUNCTION 'function' 'VclassWCopy::copy' 'VclassWCopy' verilog/parser_sv.v:143: VAR 'port' 'to' 'function' '' 'VclassWCopy' '' '' verilog/parser_sv.v:143: PORT 'to' 'function' 'input' 'VclassWCopy' '' '1' verilog/parser_sv.v:145: ENDTASKFUNC 'endfunction' verilog/parser_sv.v:147: TASK 'task' 'foreach_memref' verilog/parser_sv.v:148: VAR 'var' 'mem' 'task' '' 'bit [0:52][7:0]' '' '' verilog/parser_sv.v:149: COMMENT '// It's *not* legal according to the grammar to have dotted/package ids here' verilog/parser_sv.v:151: ENDTASKFUNC 'endtask' verilog/parser_sv.v:154: CLASS 'class' 'PreTypedefedClass' '' verilog/parser_sv.v:155: FUNCTION 'function' 'new' '' verilog/parser_sv.v:155: ENDTASKFUNC 'endfunction' verilog/parser_sv.v:156: ENDCLASS 'endclass' verilog/parser_sv.v:159: CLASS 'class' 'NewInNew' '' verilog/parser_sv.v:160: FUNCTION 'function' 'new' '' verilog/parser_sv.v:162: ENDTASKFUNC 'endfunction' verilog/parser_sv.v:165: COMMENT '// std package' verilog/parser_sv.v:163: ENDCLASS 'endclass' verilog/parser_sv.v:166: CLASS 'class' 'TryStd' '' verilog/parser_sv.v:167: VAR 'var' 's1' 'class' '' 'semaphore' '' '' verilog/parser_sv.v:168: VAR 'var' 's2' 'class' '' 'std::semaphore' '' '' verilog/parser_sv.v:169: PIN '' 'integer' '1' verilog/parser_sv.v:169: PINSELECTS '' '[{'netname' => 'integer'}]' '1' verilog/parser_sv.v:169: VAR 'var' 'm1' 'class' '' 'mailbox' '' '' verilog/parser_sv.v:170: VAR 'var' 'm2' 'class' '' 'std::mailbox' '' '' verilog/parser_sv.v:171: VAR 'var' 'p1' 'class' '' 'process' '' '' verilog/parser_sv.v:172: VAR 'var' 'p2' 'class' '' 'std::process' '' '' verilog/parser_sv.v:173: ENDCLASS 'endclass' verilog/parser_sv.v:175: MODULE 'module' 'cg_test1' undef '0' verilog/parser_sv.v:176: COVERGROUP 'covergroup' 'counter1' verilog/parser_sv.v:184: ENDGROUP 'endgroup' verilog/parser_sv.v:185: ENDMODULE 'endmodule' verilog/parser_sv.v:187: TASK 'task' 'randomize_dotted' verilog/parser_sv.v:188: VAR 'var' 'vbl' 'task' '' 'int' '' '' verilog/parser_sv.v:190: ENDTASKFUNC 'endtask' verilog/parser_sv.v:192: MODULE 'module' 'prop_parens' undef '0' verilog/parser_sv.v:194: ENDMODULE 'endmodule' verilog/parser_sv.v:196: CLASS 'class' 'this_dot_tests' '' verilog/parser_sv.v:197: TASK 'task' 'ass' verilog/parser_sv.v:199: ENDTASKFUNC 'endtask' verilog/parser_sv.v:200: ENDCLASS 'endclass' verilog/parser_sv.v:202: MODULE 'module' 'sized_out' undef '0' verilog/parser_sv.v:203: VAR 'parameter' 'SZ' 'module' '' '' '' '4' verilog/parser_sv.v:204: VAR 'port' 'o_sized' 'module' '' 'logic [SZ-1:0]' '' '' verilog/parser_sv.v:204: PORT 'o_sized' 'module' 'output' 'logic [SZ-1:0]' '' '1' verilog/parser_sv.v:205: ENDMODULE 'endmodule' verilog/parser_sv.v:207: CLASS 'class' 'solve_size' '' verilog/parser_sv.v:208: VAR 'var' 'arrayed' 'class' '' 'rand byte' '' '' verilog/parser_sv.v:209: VAR 'var' 'b' 'class' '' 'rand bit' '' '' verilog/parser_sv.v:210: COMMENT '// The dot below doesn't seem legal according to grammar, but' verilog/parser_sv.v:211: COMMENT '// the intent makes sense, and it appears in the VMM' verilog/parser_sv.v:213: ENDCLASS 'endclass' verilog/parser_sv.v:215: CLASS 'class' 'vmm_stuff' '' verilog/parser_sv.v:216: TASK 'task' 'examples' verilog/parser_sv.v:220: ENDTASKFUNC 'endtask' verilog/parser_sv.v:221: FUNCTION 'function' 'foo1' 'bit' verilog/parser_sv.v:221: ENDTASKFUNC 'endfunction' verilog/parser_sv.v:222: FUNCTION 'function' 'foo2' 'void' verilog/parser_sv.v:222: ENDTASKFUNC 'endfunction' verilog/parser_sv.v:223: VAR 'var' 'foo3' 'class' '' 'protected static string' '' '' verilog/parser_sv.v:224: FUNCTION 'function' 'foo4' 'bit' verilog/parser_sv.v:224: ENDTASKFUNC 'endfunction' verilog/parser_sv.v:225: VAR 'var' 'foo5' 'class' '' 'static local bit' '[string]' '' verilog/parser_sv.v:226: ENDCLASS 'endclass' verilog/parser_sv.v:228: CLASS 'class' 'vmm_cl_func_colon' '' verilog/parser_sv.v:229: VAR 'typedef' 'restart_e' 'class' '' 'int unsigned' '' '' verilog/parser_sv.v:230: FUNCTION 'function' 'do_all' 'void' verilog/parser_sv.v:230: VAR 'port' 'kind' 'function' '' 'vmm_cl_func_colon::restart_e' '' 'vmm_cl_func_colon::FIRM' verilog/parser_sv.v:230: PORT 'kind' 'function' 'input' 'vmm_cl_func_colon::restart_e' '' '1' verilog/parser_sv.v:231: ENDTASKFUNC 'endfunction' verilog/parser_sv.v:232: FUNCTION 'function' 'uses_class_type' 'int' verilog/parser_sv.v:232: ENDTASKFUNC 'endfunction' verilog/parser_sv.v:233: ENDCLASS 'endclass' verilog/parser_sv.v:235: CLASS 'class' 'vmm_cl_subenv' '' verilog/parser_sv.v:236: TASK 'task' 'do_reset' verilog/parser_sv.v:236: VAR 'port' 'kind' 'task' '' 'vmm_cl_func_colon::restart_e' '' 'vmm_cl_func_colon::FIRM' verilog/parser_sv.v:236: PORT 'kind' 'task' 'input' 'vmm_cl_func_colon::restart_e' '' '1' verilog/parser_sv.v:236: ENDTASKFUNC 'endtask' verilog/parser_sv.v:237: ENDCLASS 'endclass' verilog/parser_sv.v:239: TASK 'task' 'empty_comma' verilog/parser_sv.v:244: ENDTASKFUNC 'endtask' verilog/parser_sv.v:246: TASK 'task' 'vmm_more' verilog/parser_sv.v:249: COMMENT '// Not part of 1800-2005 grammar, but likely in 1800-2009' verilog/parser_sv.v:254: COMMENT '// Extern Functions/tasks when defined must scope to the class they're in to get appropriate types' verilog/parser_sv.v:252: ENDTASKFUNC 'endtask' verilog/parser_sv.v:255: FUNCTION 'function' 'vmm_cl_func_colon::uses_class_type' 'int' verilog/parser_sv.v:255: VAR 'port' 'note_uses_class_type' 'function' '' 'restart_e' '' '' verilog/parser_sv.v:255: PORT 'note_uses_class_type' 'function' 'input' 'restart_e' '' '1' verilog/parser_sv.v:256: VAR 'var' 'also_uses_class_type' 'function' '' 'restart_e' '' '' verilog/parser_sv.v:257: ENDTASKFUNC 'endfunction' verilog/parser_sv.v:259: MODULE 'module' 'hidden_checks' undef '0' verilog/parser_sv.v:260: VAR 'typedef' 'T' 'module' '' 'int' '' '' verilog/parser_sv.v:261: INSTANT 'sub' '' '' verilog/parser_sv.v:261: PIN 'T' '123' '1' verilog/parser_sv.v:261: PINSELECTS 'T' '[{'netname' => '123'}]' '1' verilog/parser_sv.v:261: ENDCELL '' verilog/parser_sv.v:261: COMMENT '// Different T' verilog/parser_sv.v:262: TASK 'task' 'hidden' verilog/parser_sv.v:263: VAR 'typedef' 'T' 'task' '' 'bit' '' '' verilog/parser_sv.v:263: COMMENT '// Different T' verilog/parser_sv.v:264: ENDTASKFUNC 'endtask' verilog/parser_sv.v:265: ENDMODULE 'endmodule' verilog/parser_sv.v:268: VAR 'member' 'm_a' 'struct' '' 'rand int' '' '' verilog/parser_sv.v:269: VAR 'member' 'm_b' 'struct' '' 'bit [7:0]' '' '' verilog/parser_sv.v:267: VAR 'typedef' 't_bug91' 'netlist' '' 'struct' '' '' verilog/parser_sv.v:271: VAR 'var' 'v_bug91' 'netlist' '' 't_bug91' '' '' verilog/parser_sv.v:273: MODULE 'module' 'bug98' undef '0' verilog/parser_sv.v:273: VAR 'port' 'x_if' 'module' '' 'interfacex' '' '' verilog/parser_sv.v:273: PORT 'x_if' 'module' 'interface' 'interfacex' '' '1' verilog/parser_sv.v:273: INSTANT 'interfacex' 'x_if' '' verilog/parser_sv.v:273: ENDCELL '' verilog/parser_sv.v:274: INSTANT 'h' 'inst_h' '' verilog/parser_sv.v:274: PIN 'push' 'x_if.pop' '1' verilog/parser_sv.v:274: PINSELECTS 'push' '[{'netname' => 'x_if.pop'}]' '1' verilog/parser_sv.v:274: ENDCELL '' verilog/parser_sv.v:275: ENDMODULE 'endmodule' verilog/parser_sv.v:277: MODULE 'module' 'bugas' undef '0' verilog/parser_sv.v:281: ENDMODULE 'endmodule' verilog/parser_sv.v:283: VAR 'typedef' 'enum_ranged_t' 'netlist' '' '[2:0]' '' '' verilog/parser_sv.v:285: VAR 'member' 'val' 'struct' '' 'logic' '' '' verilog/parser_sv.v:285: VAR 'typedef' 't_bug202_struct' 'netlist' '' 'struct' '' '' verilog/parser_sv.v:286: VAR 'member' 'val' 'union' '' 'logic' '' '' verilog/parser_sv.v:286: VAR 'typedef' 't_bug202_union' 'netlist' '' 'union' '' '' verilog/parser_sv.v:288: CLASS 'class' 'ln288' '' verilog/parser_sv.v:289: FUNCTION 'function' 'extvirtstr' 'string' verilog/parser_sv.v:289: ENDTASKFUNC 'endfunction' verilog/parser_sv.v:290: TASK 'task' 'extvirttask' verilog/parser_sv.v:290: ENDTASKFUNC 'endtask' verilog/parser_sv.v:291: ENDCLASS 'endclass' verilog/parser_sv.v:293: CLASS 'class' 'cl_to_init' '' verilog/parser_sv.v:294: FUNCTION 'function' 'new' '' verilog/parser_sv.v:294: ENDTASKFUNC 'endfunction' verilog/parser_sv.v:295: FUNCTION 'function' 'init' 'cl_to_init' verilog/parser_sv.v:295: ENDTASKFUNC 'endfunction' verilog/parser_sv.v:296: ENDCLASS 'endclass' verilog/parser_sv.v:297: FUNCTION 'function' 'cl_to_init::init' 'cl_to_init' verilog/parser_sv.v:298: ENDTASKFUNC 'endfunction' verilog/parser_sv.v:299: FUNCTION 'function' 'new' '' verilog/parser_sv.v:300: ENDTASKFUNC 'endfunction' verilog/parser_sv.v:301: VAR 'var' 'cl_inited' 'netlist' '' 'cl_to_init' '' 'cl_to_init::init()' verilog/parser_sv.v:303: COMMENT '// pure virtual functions have no endfunction.' verilog/parser_sv.v:304: CLASS 'class' 'pure_virt_func_class' 'virtual' verilog/parser_sv.v:305: FUNCTION 'function' 'pure_virt_func' 'string' verilog/parser_sv.v:305: ENDTASKFUNC 'endfunction' verilog/parser_sv.v:306: TASK 'task' 'pure_virt_task' verilog/parser_sv.v:306: ENDTASKFUNC 'endtask' verilog/parser_sv.v:307: ENDCLASS 'endclass' verilog/parser_sv.v:309: CLASS 'class' 'extend_base' '' verilog/parser_sv.v:310: VAR 'typedef' 'base_enum' 'class' '' 'enum' '' '' verilog/parser_sv.v:311: FUNCTION 'function' 'create' 'extend_base' verilog/parser_sv.v:311: ENDTASKFUNC 'endfunction' verilog/parser_sv.v:312: ENDCLASS 'endclass' verilog/parser_sv.v:313: CLASS 'class' 'extended' '' verilog/parser_sv.v:314: VAR 'typedef' 'be_t' 'class' '' 'base_enum' '' '' verilog/parser_sv.v:314: COMMENT '// type must come from base class' verilog/parser_sv.v:315: FUNCTION 'function' 'create' 'int' verilog/parser_sv.v:315: COMMENT '// Must override base's create' verilog/parser_sv.v:316: VAR 'var' 'mye' 'function' '' 'be_t' '' '' verilog/parser_sv.v:317: ENDTASKFUNC 'endfunction' verilog/parser_sv.v:318: ENDCLASS 'endclass' verilog/parser_sv.v:320: TASK 'task' 'rand_with_ln320' verilog/parser_sv.v:323: ENDTASKFUNC 'endtask' verilog/parser_sv.v:324: TASK 'task' 'apply_request' verilog/parser_sv.v:324: VAR 'port' 'data_req' 'task' '' '' '' '' verilog/parser_sv.v:324: PORT 'data_req' 'task' 'input' '' '' '1' verilog/parser_sv.v:324: VAR 'port' 'randomize' 'task' '' 'bit' '' '1' verilog/parser_sv.v:324: PORT 'randomize' 'task' 'input' 'bit' '' '2' verilog/parser_sv.v:326: COMMENT '// Generic method, not std::randomize' verilog/parser_sv.v:328: ENDTASKFUNC 'endtask' verilog/parser_sv.v:330: TASK 'task' 'foreach_class_scope_ln330' verilog/parser_sv.v:332: ENDTASKFUNC 'endtask' verilog/parser_sv.v:334: MODULE 'module' 'clkif_334' undef '0' verilog/parser_sv.v:336: ENDMODULE 'endmodule' verilog/parser_sv.v:338: MODULE 'module' 'gen_ln338' undef '0' verilog/parser_sv.v:345: ENDMODULE 'endmodule' verilog/parser_sv.v:347: MODULE 'module' 'par_packed' undef '0' verilog/parser_sv.v:348: VAR 'parameter' 'P1' 'module' '' 'logic [31:0]' '[3:0]' ''{1,2,3,4}' verilog/parser_sv.v:348: COMMENT '// unpacked array' verilog/parser_sv.v:349: VAR 'member' 'ecc' 'struct' '' 'logic' '' '' verilog/parser_sv.v:349: VAR 'member' 'data' 'struct' '' 'logic [7:0]' '' '' verilog/parser_sv.v:349: VAR 'net' 'memsig' 'module' 'wire' 'struct' '' '' verilog/parser_sv.v:350: ENDMODULE 'endmodule' verilog/parser_sv.v:352: MODULE 'module' 'not_a_bug315' undef '0' verilog/parser_sv.v:353: VAR 'typedef' 'supply_net_t' 'module' '' 'int' '' '' verilog/parser_sv.v:354: VAR 'port' 'i' 'module' '' 'int' '' '' verilog/parser_sv.v:354: PORT 'i' 'module' 'input' 'int' '' '0' verilog/parser_sv.v:355: VAR 'port' 'i' 'module' '' 'imp_test_pkg::byte_t' '' '' verilog/parser_sv.v:355: PORT 'i' 'module' 'input' 'imp_test_pkg::byte_t' '' '0' verilog/parser_sv.v:356: VAR 'port' 'bug316' 'module' '' 'supply_net_t' '' '' verilog/parser_sv.v:356: PORT 'bug316' 'module' 'input' 'supply_net_t' '' '0' verilog/parser_sv.v:357: ENDMODULE 'endmodule' verilog/parser_sv.v:359: MODULE 'module' 'bins_bracket' undef '0' verilog/parser_sv.v:360: VAR 'parameter' 'N' 'module' '' '' '' '2' verilog/parser_sv.v:361: COVERGROUP 'covergroup' 'cg_debitor' verilog/parser_sv.v:363: COMMENT '// 'std' overrides std:: package, which confuses VP' verilog/parser_sv.v:364: COMMENT '//bins std[] = { [0:N] };' verilog/parser_sv.v:366: ENDGROUP 'endgroup' verilog/parser_sv.v:367: ENDMODULE 'endmodule' verilog/parser_sv.v:369: CLASS 'class' 'ovm_void' 'virtual' verilog/parser_sv.v:370: ENDCLASS 'endclass' verilog/parser_sv.v:371: CLASS 'class' 'ovm_port_base' 'virtual' verilog/parser_sv.v:371: VAR 'parameter' 'IF' 'class' '' 'type' '' 'ovm_void' verilog/parser_sv.v:371: PORT 'IF' 'class' '' 'type' '' '1' verilog/parser_sv.v:372: ENDCLASS 'endclass' verilog/parser_sv.v:373: CLASS 'class' 'uvm_build_phase' 'virtual' verilog/parser_sv.v:373: VAR 'parameter' 'BASE' 'class' '' 'type' '' 'ovm_void' verilog/parser_sv.v:373: PORT 'BASE' 'class' '' 'type' '' '1' verilog/parser_sv.v:374: VAR 'var' 'type_name' 'class' '' 'static const string' '' '"uvm_build_phase"' verilog/parser_sv.v:375: ENDCLASS 'endclass' verilog/parser_sv.v:377: CLASS 'class' 'bug627sub' '' verilog/parser_sv.v:378: ENDCLASS 'endclass' verilog/parser_sv.v:379: CLASS 'class' 'bug627' '' verilog/parser_sv.v:379: VAR 'parameter' 'TYPE' 'class' '' 'type' '' 'bug627sub' verilog/parser_sv.v:379: PORT 'TYPE' 'class' '' 'type' '' '1' verilog/parser_sv.v:380: VAR 'typedef' 'types_t' 'class' '' 'TYPE' '[$]' '' verilog/parser_sv.v:381: FUNCTION 'function' 'f' 'types_t' verilog/parser_sv.v:384: ENDTASKFUNC 'endfunction' verilog/parser_sv.v:385: ENDCLASS 'endclass' verilog/parser_sv.v:387: INTERFACE 'interface' 'if_bug777' verilog/parser_sv.v:388: VAR 'net' 'a' 'interface' 'wire' '' '' '' verilog/parser_sv.v:389: MODPORT 'modport' 'master' verilog/parser_sv.v:389: VAR 'port' 'a' 'modport' '' '' '' 'a' verilog/parser_sv.v:389: PORT 'a' 'modport' 'input' '' '' '1' verilog/parser_sv.v:389: ENDMODPORT 'endmodport' verilog/parser_sv.v:390: MODPORT 'modport' 'slave' verilog/parser_sv.v:390: VAR 'port' 'a' 'modport' '' '' '' 'a' verilog/parser_sv.v:390: PORT 'a' 'modport' 'output' '' '' '1' verilog/parser_sv.v:390: ENDMODPORT 'endmodport' verilog/parser_sv.v:391: ENDINTERFACE 'endinterface' verilog/parser_sv.v:392: MODULE 'module' 'bug777' undef '0' verilog/parser_sv.v:392: PORT 'clk' 'module' '' '' '' '1' verilog/parser_sv.v:392: PORT 'ifport' 'module' '' '' '' '2' verilog/parser_sv.v:393: VAR 'port' 'clk' 'module' '' '' '' '' verilog/parser_sv.v:393: PORT 'clk' 'module' 'input' '' '' '0' verilog/parser_sv.v:394: INSTANT 'if_bug777' 'ifport' '' verilog/parser_sv.v:394: ENDCELL '' verilog/parser_sv.v:395: INSTANT 'if_bug777' 'ifportmp' '' verilog/parser_sv.v:395: ENDCELL '' verilog/parser_sv.v:396: COMMENT '//if_bug777.mp ifportmp (); // Not legal' verilog/parser_sv.v:397: COMMENT '// Currently unsupported, parens required so VP knows is instance' verilog/parser_sv.v:398: COMMENT '//if_bug777 ifport;' verilog/parser_sv.v:399: ENDMODULE 'endmodule' verilog/parser_sv.v:400: MODULE 'module' 'bug778' undef '0' verilog/parser_sv.v:401: VAR 'var' 'bar' 'module' '' 'virtual if_bug777' '' '' verilog/parser_sv.v:402: ENDMODULE 'endmodule' verilog/parser_sv.v:403: CLASS 'class' 'cls778' '' verilog/parser_sv.v:404: VAR 'var' 'bar' 'class' '' 'virtual if_bug777' '' '' verilog/parser_sv.v:405: ENDCLASS 'endclass' verilog/parser_sv.v:407: MODULE 'module' 'bug810' undef '0' verilog/parser_sv.v:408: COMMENT '/*parameter*/' verilog/parser_sv.v:408: VAR 'parameter' 'DW' 'module' '' 'int unsigned' '' '32' verilog/parser_sv.v:408: PORT 'DW' 'module' '' 'int unsigned' '' '1' verilog/parser_sv.v:409: ENDMODULE 'endmodule' verilog/parser_sv.v:410: INTERFACE 'interface' 'test_if' verilog/parser_sv.v:410: VAR 'port' 'clk' 'interface' '' '' '' '' verilog/parser_sv.v:410: PORT 'clk' 'interface' 'input' '' '' '1' verilog/parser_sv.v:411: ENDINTERFACE 'endinterface' verilog/parser_sv.v:413: MODULE 'module' 'bug815' undef '0' verilog/parser_sv.v:414: VAR 'port' 'bad' 'module' '' 'test_if' '[2]' '' verilog/parser_sv.v:414: PORT 'bad' 'module' 'interface' 'test_if' '[2]' '1' verilog/parser_sv.v:414: INSTANT 'test_if' 'bad' '[2]' verilog/parser_sv.v:414: ENDCELL '' verilog/parser_sv.v:415: ENDMODULE 'endmodule' verilog/parser_sv.v:417: MODULE 'module' 'bug868' undef '0' verilog/parser_sv.v:417: PORT 'ifmp' 'module' '' '' '' '1' verilog/parser_sv.v:418: INSTANT 'if_bug777' 'ifmp' '' verilog/parser_sv.v:418: ENDCELL '' verilog/parser_sv.v:419: ENDMODULE 'endmodule' verilog/parser_sv.v:421: MODULE 'module' 'bug_param_struct' undef '0' verilog/parser_sv.v:422: VAR 'parameter' 'ROWS' 'module' '' 'int' '' '2' verilog/parser_sv.v:422: PORT 'ROWS' 'module' '' 'int' '' '1' verilog/parser_sv.v:423: VAR 'member' 'row_id' 'struct' '' 'logic [ROWS-1:0]' '' '' verilog/parser_sv.v:423: VAR 'parameter' 'data_t' 'module' '' 'type' '' 'struct' verilog/parser_sv.v:424: VAR 'port' 'd' 'module' '' 'data_t' '' '' verilog/parser_sv.v:424: PORT 'd' 'module' 'input' 'data_t' '' '1' verilog/parser_sv.v:425: ENDMODULE 'endmodule' verilog/parser_sv09.v:001: COMMENT '// 1800-2009 mantis1769' verilog/parser_sv09.v:002: MODULE 'module' 'mantis1769' undef '0' verilog/parser_sv09.v:002: VAR 'parameter' 'N' 'module' '' '' '' '1' verilog/parser_sv09.v:002: PORT 'N' 'module' '' '' '' '1' verilog/parser_sv09.v:005: COMMENT '// 1800-2009 mantis1134' verilog/parser_sv09.v:004: ENDMODULE 'endmodule' verilog/parser_sv09.v:006: MODULE 'module' 'mantis1134_decoder' undef '0' verilog/parser_sv09.v:007: VAR 'parameter' 'BITS' 'module' '' '' '' '3' verilog/parser_sv09.v:007: PORT 'BITS' 'module' '' '' '' '1' verilog/parser_sv09.v:007: VAR 'localparam' 'OUT_BITS' 'module' '' '' '' '1< 'somebus'}]' '1' verilog/parser_vectors.v:023: PIN 'y' 'somenet_1' '2' verilog/parser_vectors.v:023: PINSELECTS 'y' '[{'netname' => 'somenet_1'}]' '2' verilog/parser_vectors.v:024: ENDCELL '' verilog/parser_vectors.v:026: INSTANT 'mod' 'instmod_2' '' verilog/parser_vectors.v:027: PIN 'a' 'somebus' '1' verilog/parser_vectors.v:027: PINSELECTS 'a' '[{'netname' => 'somebus'}]' '1' verilog/parser_vectors.v:028: PIN 'y' 'someotherbus[2]' '2' verilog/parser_vectors.v:028: PINSELECTS 'y' '[{'lsb' => '2','msb' => '2','netname' => 'someotherbus'}]' '2' verilog/parser_vectors.v:029: ENDCELL '' verilog/parser_vectors.v:031: INSTANT 'mod' 'instmod_3' '' verilog/parser_vectors.v:032: PIN 'a' 'somewidebus[24:21]' '1' verilog/parser_vectors.v:032: PINSELECTS 'a' '[{'lsb' => '21','msb' => '24','netname' => 'somewidebus'}]' '1' verilog/parser_vectors.v:033: PIN 'y' 'somenet_2' '2' verilog/parser_vectors.v:033: PINSELECTS 'y' '[{'netname' => 'somenet_2'}]' '2' verilog/parser_vectors.v:034: ENDCELL '' verilog/parser_vectors.v:036: INSTANT 'mod' 'instmod_4' '' verilog/parser_vectors.v:037: PIN 'a' 'i[31:27]' '1' verilog/parser_vectors.v:037: PINSELECTS 'a' '[{'lsb' => '27','msb' => '31','netname' => 'i'}]' '1' verilog/parser_vectors.v:038: PIN 'y' 'o[29]' '2' verilog/parser_vectors.v:038: PINSELECTS 'y' '[{'lsb' => '29','msb' => '29','netname' => 'o'}]' '2' verilog/parser_vectors.v:039: ENDCELL '' verilog/parser_vectors.v:041: INSTANT 'mod' 'instmod_5' '' verilog/parser_vectors.v:042: PIN 'a' '{somenet_1,3'b101,someotherbus[2],somewidebus[2:1]}' '1' verilog/parser_vectors.v:042: PINSELECTS 'a' '[{'lsb' => 1,'msb' => 2,'netname' => 'somewidebus'},{'lsb' => 2,'msb' => 2,'netname' => 'someotherbus'},{'lsb' => 0,'msb' => 2,'netname' => '\'b101'},{'netname' => 'somenet_1'}]' '1' verilog/parser_vectors.v:043: PIN 'y' 'o[30]' '2' verilog/parser_vectors.v:043: PINSELECTS 'y' '[{'lsb' => '30','msb' => '30','netname' => 'o'}]' '2' verilog/parser_vectors.v:044: ENDCELL '' verilog/parser_vectors.v:046: INSTANT 'mod' 'instmod_6' '' verilog/parser_vectors.v:047: PIN 'a' '{somenet_1,3'b101,{someotherbus[2],someotherbus[2]},somewidebus[2:1]}' '1' verilog/parser_vectors.v:047: PINSELECTS 'a' '[{'lsb' => 1,'msb' => 2,'netname' => 'somewidebus'},{'lsb' => 2,'msb' => 2,'netname' => 'someotherbus'},{'lsb' => 2,'msb' => 2,'netname' => 'someotherbus'},{'lsb' => 0,'msb' => 2,'netname' => '\'b101'},{'netname' => 'somenet_1'}]' '1' verilog/parser_vectors.v:048: PIN 'y' 'o[30]' '2' verilog/parser_vectors.v:048: PINSELECTS 'y' '[{'lsb' => '30','msb' => '30','netname' => 'o'}]' '2' verilog/parser_vectors.v:049: ENDCELL '' verilog/parser_vectors.v:051: INSTANT 'mod' 'instmod_7' '' verilog/parser_vectors.v:052: PIN 'a' 'somebus[{SOMEPARAM_3[1],SOMEPARAM_3[0]}]' '1' verilog/parser_vectors.v:052: PINSELECTS 'a' '[{'lsb' => 0,'msb' => 0,'netname' => 'SOMEPARAM_3'},{'lsb' => 1,'msb' => 1,'netname' => 'SOMEPARAM_3'}]' '1' verilog/parser_vectors.v:053: PIN 'y' 'someotherbus[2]' '2' verilog/parser_vectors.v:053: PINSELECTS 'y' '[{'lsb' => '2','msb' => '2','netname' => 'someotherbus'}]' '2' verilog/parser_vectors.v:054: ENDCELL '' verilog/parser_vectors.v:056: ENDMODULE 'endmodule' Verilog-Perl-3.482/t/85_vhier_modfiles.out0000644000177100017500000000015013741600317020321 0ustar wsnyderwsnyder verilog/v_hier_top.v verilog/v_hier_sub.v verilog/v_recursive.v verilog/v_hier_subsub.v Verilog-Perl-3.482/t/41_example.out0000644000177100017500000001176713453243564016774 0ustar wsnyderwsnyderChecking example in Netlist.pm Module $root $root Module v_hier_top v_hier_top input clk Cell missing Cell recursive Module v_recursive v_hier_top.recursive Cell recurse Cell sub .avec({avec[3],avec[2:0]}) .clk(1'b0) .qvec(qvec[3:0]) Module v_hier_sub v_hier_top.sub input avec input clk output qvec Cell subsub0 .a(a1) .q(qvec[0]) Module v_hier_subsub v_hier_top.sub.subsub0 input a output q Cell subsub2 .a(1'b0) .q(qvec[2]) Module v_hier_subsub v_hier_top.sub.subsub2 input a output q Module v_hier_top2 v_hier_top2 input clk inoutput iosig Cell noport Module v_hier_noport v_hier_top2.noport Cell noporta Module v_hier_noport v_hier_top2.noporta Cell noportp Module v_hier_noport v_hier_top2.noportp Dump Module:$root Kwd:root_module File:verilog/v_hier_top.v Net:GLOBAL_PARAM DeclT:localparam NetT: DataT: Array: Value:1 Module:v_hier_noport Kwd:module File:verilog/v_hier_noport.v Net:P DeclT:parameter NetT: DataT: Array: Net:internal DeclT:var NetT: DataT:reg Array: Module:v_hier_sub Kwd:module File:verilog/v_hier_sub.v Port:avec Dir:in DataT:[3:0] Array: Port:clk Dir:in DataT: Array: Port:qvec Dir:out DataT:[3:0] Array: Net:FROM_DEFPARAM DeclT:parameter NetT: DataT: Array: Value:1 Net:K DeclT:genvar NetT: DataT: Array: Net:K_UNUSED DeclT:genvar NetT: DataT: Array: Net:a1 I DeclT:net NetT:supply1 DataT: Array: Net:avec O DeclT:port NetT: DataT:[3:0] Array: 3:0 Net:clk O DeclT:port NetT: DataT: Array: Net:qvec I DeclT:port NetT: DataT:[3:0] Array: 3:0 Cell:subsub0 is-a:v_hier_subsub .IGNORED('sh20) Module:v_hier_subsub Kwd:module File:verilog/v_hier_subsub.v Pin:a Net:a1 Port:a Dir:in DataT:signed Array: Net:a1 I DeclT:net NetT:supply1 DataT: Array: Pin:q Net:qvec[0] Port:q Dir:out DataT: Array: Cell:subsub2 is-a:v_hier_subsub Module:v_hier_subsub Kwd:module File:verilog/v_hier_subsub.v Pin:a Net:1'b0 Port:a Dir:in DataT:signed Array: Pin:q Net:qvec[2] Port:q Dir:out DataT: Array: Module:v_hier_subsub Kwd:module File:verilog/v_hier_subsub.v Port:a Dir:in DataT:signed Array: Port:q Dir:out DataT: Array: Net:IGNORED DeclT:parameter NetT: DataT: Array: Value:0 Net:a O DeclT:port NetT: DataT:signed Array: Net:q I DeclT:port NetT:wire DataT: Array: Module:v_hier_top Kwd:module File:verilog/v_hier_top.v Port:clk Dir:in DataT: Array: Net:WC_p1 DeclT:localparam NetT: DataT:[0:0] Array: 0:0 Value:0 Net:WC_p3 DeclT:localparam NetT: DataT:[2:0] Array: 2:0 Value:0 Net:WC_p32 DeclT:localparam NetT: DataT: Array: Value:0 Net:WC_p4 DeclT:localparam NetT: DataT:[-1:2] Array: -1:2 Value:0 Net:WC_pint DeclT:localparam NetT: DataT:integer Array: Value:0 Net:WC_w1 DeclT:net NetT:wire DataT: Array: Net:WC_w1b DeclT:net NetT:wire DataT:[0:0] Array: 0:0 Net:WC_w3 DeclT:net NetT:wire DataT:[2:0] Array: 2:0 Net:WC_w4 DeclT:net NetT:wire DataT:[-1:2] Array: -1:2 Net:asn_clk DeclT:net NetT:wire DataT: Array: Net:clk O DeclT:port NetT: DataT: Array: Cell:missing is-a:missing Cell:recursive is-a:v_recursive .DEPTH(3) Module:v_recursive Kwd:module File:verilog/v_recursive.v Cell:sub is-a:v_hier_sub Module:v_hier_sub Kwd:module File:verilog/v_hier_sub.v Pin:avec Net:{avec[3],avec[2:0]} Port:avec Dir:in DataT:[3:0] Array: Pin:clk Net:1'b0 Port:clk Dir:in DataT: Array: Pin:qvec Net:qvec[3:0] Port:qvec Dir:out DataT:[3:0] Array: Defparam:defparam lhs:sub.FROM_DEFPARAM rhs:2 ContAssign:assign lhs:asn_clk rhs:clk Module:v_hier_top2 Kwd:module File:verilog/v_hier_top2.v Port:clk Dir:in DataT: Array: Port:iosig Dir:inout DataT:[2:0] Array: Net:clk O DeclT:port NetT: DataT: Array: Net:iosig DeclT:port NetT: DataT:[2:0] Array: 2:0 Cell:noport is-a:v_hier_noport Module:v_hier_noport Kwd:module File:verilog/v_hier_noport.v Cell:noporta is-a:v_hier_noport .P(1) Module:v_hier_noport Kwd:module File:verilog/v_hier_noport.v Cell:noportp is-a:v_hier_noport .P(1) Module:v_hier_noport Kwd:module File:verilog/v_hier_noport.v Module:v_recursive Kwd:module File:verilog/v_recursive.v Net:DEPTH DeclT:parameter NetT: DataT: Array: Value:1 Cell:recurse is-a:v_recursive .DEPTH(DEPTH-1) Module:v_recursive Kwd:module File:verilog/v_recursive.v Verilog-Perl-3.482/t/51_vrename_kwd_list.out0000644000177100017500000000234413462302176020661 0ustar wsnyderwsnyder# Generated by vrename on Wed May 1 06:55:43 2019 # # Files read for this analysis: vfile "t/51_vrename_kwd.v" # # Original Signal Name Name to change to # -------------------- ----------------- # sigren "$display" "$display" sigren "\do " "\do " sigren "\esc[ape]_2esc " "\esc[ape]_2esc " sigren "\esc[ape]_2esc_nospace " "\esc[ape]_2esc_nospace " sigren "\esc[ape]_2ext " "\esc[ape]_2ext " sigren "\esc[ape]_2ext_nospace " "\esc[ape]_2ext_nospace " sigren "\esc[ape]_2non " "\esc[ape]_2non " sigren "\esc[ape]_2non_nospace " "\esc[ape]_2non_nospace " sigren "do" "\do " sigren "ext_2esc" "ext_2esc" sigren "ext_2esc_nospace" "ext_2esc_nospace" sigren "ext_2ext" "ext_2ext" sigren "ext_2ext_nospace" "ext_2ext_nospace" sigren "ext_2non" "ext_2non" sigren "ext_2non_nospace" "ext_2non_nospace" sigren "non_2esc" "non_2esc" sigren "non_2esc_nospace" "non_2esc_nospace" sigren "non_2ext" "non_2ext" sigren "non_2ext_nospace" "non_2ext_nospace" sigren "non_2non" "non_2non" sigren "non_2non_nospace" "non_2non_nospace" sigren "vrename_kwd" "vrename_kwd" # # Use M-x compile in emacs to automatically perform the changes: ## Local Variables: *** ## compile-command: "./vrename -change t/51_vrename_kwd.v " *** ## End: *** Verilog-Perl-3.482/t/85_vhier_skiplist.dat0000644000177100017500000000004113234726611020324 0ustar wsnyderwsnyderv_hier_nonexistent v_hier_subsub Verilog-Perl-3.482/t/56_editfiles.v0000755000177100017500000000073413462162621016742 0ustar wsnyderwsnyder// DESCRIPTION: Verilog::Preproc: Example source code // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2007-2012 by Wilson Snyder. `celldefine a_front_matter; module a; wire inside_module_a; /* // double cmt */ endmodule b_front_matter; `ifdef B_HAS_X module b; `elsif module b (input x); `endif wire inside_module_b; // synopsys translate_off wire in_translate_off; // synopsys translate_on endmodule `endcelldefine Verilog-Perl-3.482/t/04_critic.t0000755000177100017500000000155414553624300016236 0ustar wsnyderwsnyder#!/usr/bin/perl -w # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package # # Copyright 2000-2024 by Wilson Snyder. This program is free software; # you can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. use strict; use Test; use warnings; if (!$ENV{VERILATOR_AUTHOR_SITE} || $ENV{HARNESS_NO_CRITIC}) { plan tests => 1; skip("author only test (harmless)",1); } else { eval "use Test::Perl::Critic;"; if ($@) { plan tests => 1; skip("Test::Perl::Critic not installed so ignoring check (harmless)",1); } else { #-profile => "t/04_critic.rc" Test::Perl::Critic->import( -verbose=>9, -exclude=>['ProhibitExplicitReturnUndef', 'ProhibitNoStrict', 'ProhibitStringyEval'], ); all_critic_ok(); } } Verilog-Perl-3.482/t/30_preproc.t0000755000177100017500000000574014553624300016433 0ustar wsnyderwsnyder#!/usr/bin/perl -w # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package # # Copyright 2000-2024 by Wilson Snyder. This program is free software; # you can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. use IO::File; use strict; use Test::More; BEGIN { plan tests => 1+6*3 } BEGIN { require "./t/test_utils.pl"; } ####################################################################### package MyPreproc; use Verilog::Preproc; use base qw(Verilog::Preproc); sub comment { print $::OUTTO $_[0]->filename,":",$_[0]->lineno,": COMMENT: $_[1]\n"; $_[0]->unreadback(' /*CMT*/ '); } sub def_substitute { my ($self,$out) = @_; # Only do this for some tests, as it makes the output look strange if ($self->{_test_def_substitute} && $out !~ /^".*"$/ # And don't corrupt `include test && $out !~ /\.v/ # Nor things that look like filenames && $out !~ /NODS/){ return "DS_".$out; # Must use _ as need identifier character } else { return $out; } } package main; ####################################################################### sub prep { my $opt = new Verilog::Getopt; $opt->parameter (qw( +incdir+verilog +define+PREDEF_COMMAND_LINE )); return $opt; } use Verilog::Getopt; ok(1, "use Verilog::Getopt"); use Verilog::Preproc; ok(1, "use Verilog::Preproc"); test ('', keep_comments=>1, line_directives=>0, _no_line_numbering=>1); # Makes "diff" cleaner test ('_on', keep_comments=>1,); test ('_syn', keep_comments=>1, keep_whitespace=>1, synthesis=>1); test ('_nows', keep_comments=>0, keep_whitespace=>0, synthesis=>1); test ('_sub', keep_comments=>'sub', _test_def_substitute=>1); test_getall (); sub test { my $id = shift; my @args = @_; my $opt = prep(); my $pp = new MyPreproc (options=>$opt, @args); ok(1, "new${id}"); #$pp->debug(9); $pp->open("inc1.v"); $pp->open("inc2.v"); $pp->open("inc_ifdef.v"); $pp->open("inc_nonl.v"); $pp->open("inc_def09.v"); my $fhout = IO::File->new(">test_dir/inc${id}.out"); $::OUTTO = $fhout; while (defined(my $line = $pp->getline())) { if ($pp->{_no_line_numbering}) { print $fhout $pp->filename.": ".$line; } else { print $fhout $pp->filename.":".$pp->lineno.": ".$line; } } $fhout->close(); ok(1, "parsed${id}"); ok(files_identical("test_dir/inc${id}.out", "t/30_preproc${id}.out"), "diff${id}"); } sub test_getall { my $id = shift; my @args = @_; my $a; my $acalls = 0; { my $pp = new MyPreproc (options=>prep(), @args); $pp->open("inc1.v"); while (defined(my $line = $pp->getline)) { $a .= $line; $acalls++; } } my $b; my $bcalls = 0; { my $pp = new MyPreproc (options=>prep(), @args); $pp->open("inc1.v"); while (defined(my $all = $pp->getall)) { $b .= $all; $bcalls++; } } is($a, $b); ok($acalls > $bcalls, "getall does same callbacks"); } Verilog-Perl-3.482/t/41_example.t0000755000177100017500000000425614553624300016417 0ustar wsnyderwsnyder#!/usr/bin/perl -w # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package # # Copyright 2000-2024 by Wilson Snyder. This program is free software; # you can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. use strict; use Test::More; BEGIN { plan tests => 3 } BEGIN { require "./t/test_utils.pl"; } #$Verilog::Netlist::Debug = 1; use Verilog::Netlist; ok(1, "use"); { local *STDOUT; open(STDOUT, ">", "test_dir/41_example.dmp"); print "Checking example in Netlist.pm\n"; use Verilog::Netlist; # Setup options so files can be found use Verilog::Getopt; my $opt = new Verilog::Getopt; $opt->parameter( "+incdir+verilog", "-y","verilog", ); # Prepare netlist my $nl = new Verilog::Netlist(options => $opt, link_read_nonfatal=>1, ); foreach my $file ('verilog/v_hier_top.v', 'verilog/v_hier_top2.v') { $nl->read_file(filename=>$file); } # Read in any sub-modules $nl->link(); #$nl->lint(); # Optional, see docs; probably not wanted $nl->exit_if_error(); my %recursing; # Prevent recursion; not in example foreach my $mod ($nl->top_modules_sorted) { show_hier($mod, " ", "", ""); } sub show_hier { my $mod = shift; my $indent = shift; my $hier = shift; my $cellname = shift; return if $recursing{$mod->name}++; # Not in example if (!$cellname) {$hier = $mod->name;} #top modules get the design name else {$hier .= ".$cellname";} #append the cellname printf ("%-45s %s\n", $indent."Module ".$mod->name,$hier); foreach my $sig ($mod->ports_sorted) { printf ($indent." %sput %s\n", $sig->direction, $sig->name); } foreach my $cell ($mod->cells_sorted) { printf ($indent. " Cell %s\n", $cell->name); foreach my $pin ($cell->pins_sorted) { printf($indent." .%s(%s)\n", $pin->name, $pin->netname); } show_hier($cell->submod, $indent." ", $hier, $cell->name) if $cell->submod; } --$recursing{$mod->name}; # Not in example } print "Dump\n"; $nl->dump; } ok(files_identical("test_dir/41_example.dmp", "t/41_example.out")); ok(1, "done"); Verilog-Perl-3.482/t/35_sigparser.t0000755000177100017500000000742214553624300016764 0ustar wsnyderwsnyder#!/usr/bin/perl -w # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package # # Copyright 2000-2024 by Wilson Snyder. This program is free software; # you can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. use strict; use Test::More; use Data::Dumper; $Data::Dumper::Indent = 1; BEGIN { plan tests => 6 } BEGIN { require "./t/test_utils.pl"; } our %_TestCoverage; our %_TestCallbacks; ###################################################################### package MyParser; use Verilog::SigParser; use strict; use base qw(Verilog::SigParser); BEGIN { # Make functions like this: # sub attribute { $_[0]->_common('module', @_); } foreach my $cb (Verilog::SigParser::callback_names(), 'comment') { $_TestCallbacks{$cb} = 1; my $func = ' sub __CB__ { $_[0]->_common("__CB__", @_); } '; $func =~ s/__CB__/$cb/g; eval($func); } } sub _serialize { my $in = shift; if (ref($in)) { my $dd = Data::Dumper->new([$in], [qw(in)]); $dd->Reset->Indent(0)->Terse(1)->Sortkeys(1); return $dd->Dump; } else { return $in; } } sub _common { my $self = shift; my $what = shift; my $call_self = shift; my @args = @_; $_TestCoverage{$what}++; my $args=""; foreach (@args) { if (defined $_) { $args .= " \'"._serialize($_)."\'"; } else { $args .= " undef"; } } $self->{dump_fh}->printf("%s:%03d: %s %s\n", $self->filename, $self->lineno, uc $what, $args); } sub error { my ($self,$text,$token)=@_; my $fileline = $self->filename.":".$self->lineno; warn ("%Warning: $fileline: $text\n"); } ###################################################################### package main; use Verilog::SigParser; use Verilog::Preproc; ok(1, "use"); read_tests("test_dir/35.dmp", []); ok(1, "read"); # Did we read the right stuff? ok(files_identical("test_dir/35.dmp", "t/35_sigparser.out"), "diff"); read_tests("test_dir/35_ps.dmp", [use_pinselects => 1]); ok(1, "read-pinselects"); # Did we read the right stuff? ok(files_identical("test_dir/35_ps.dmp", "t/35_sigparser_ps.out"), "diff"); # Did we cover everything? my $err; foreach my $cb (sort keys %_TestCallbacks) { if (!$_TestCoverage{$cb}) { $err=1; warn "%Warning: No test coverage for callback: $cb\n"; } } ok (!$err, "coverage"); ###################################################################### # Use our class and dump to a file sub read_tests { my $dump_filename = shift; my $option_ref = shift; my $dump_fh = new IO::File($dump_filename,"w") or die "%Error: $! $dump_filename,"; read_test($dump_fh, $option_ref, "/dev/null"); # Empty files should be ok read_test($dump_fh, $option_ref, "verilog/v_hier_subprim.v"); read_test($dump_fh, $option_ref, "verilog/v_hier_sub.v"); read_test($dump_fh, $option_ref, "verilog/parser_bugs.v"); read_test($dump_fh, $option_ref, "verilog/pinorder.v"); read_test($dump_fh, $option_ref, "verilog/parser_sv.v"); read_test($dump_fh, $option_ref, "verilog/parser_sv09.v"); read_test($dump_fh, $option_ref, "verilog/parser_sv17.v"); read_test($dump_fh, $option_ref, "verilog/parser_vectors.v"); $dump_fh->close(); } sub read_test { my $dump_fh = shift; my $option_ref = shift; my $filename = shift; my $pp = Verilog::Preproc->new(keep_comments=>1,); my $parser = new MyParser (dump_fh => $dump_fh, metacomment=>{synopsys=>1}, @$option_ref); if ($ENV{VERILOG_TEST_DEBUG}) { # For example, VERILOG_TEST_DEBUG=9 $parser->debug($ENV{VERILOG_TEST_DEBUG}); } # Preprocess $pp->open($filename); $parser->parse_preproc_file($pp); print Dumper($parser->{symbol_table}) if ($parser->debug()); } Verilog-Perl-3.482/t/43_storable.t0000755000177100017500000000153414553624300016575 0ustar wsnyderwsnyder#!/usr/bin/perl -w # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package # # Copyright 2000-2024 by Wilson Snyder. This program is free software; # you can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. BEGIN { require "./t/test_utils.pl"; } use strict; use Test; use warnings; $SIG{__WARN__} = sub {}; eval "use Storable;"; if ($@) { plan tests => 1; skip("Storable not installed so ignoring check (harmless)",1); } else { plan tests => 4; eval "use Verilog::Netlist;"; ok(1); if (1) { my $nl = new Verilog::Netlist; $nl->read_file(filename=>"verilog/v_hier_subsub.v"); ok(1); Storable::store($nl, "test_dir/netlist.db"); ok(1); } if (1) { my $nl = retrieve("test_dir/netlist.db"); ok(1); } } Verilog-Perl-3.482/t/32_noinc.v0000644000177100017500000000030413234726611016062 0ustar wsnyderwsnyder// DESCRIPTION: Verilog::Preproc: Example source code // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2007-2012 by Wilson Snyder. text. `include "notfound" Verilog-Perl-3.482/t/30_preproc_syn.out0000644000177100017500000011617514030463163017670 0ustar wsnyderwsnyderverilog/inc_nonl.v:1: `line 1 "verilog/inc1.v" 1 verilog/inc_nonl.v:1: `line 1 "verilog/inc1.v" 0 verilog/inc_nonl.v:1: `line 1 "verilog/inc2.v" 1 verilog/inc_nonl.v:1: `line 1 "verilog/inc2.v" 0 verilog/inc_nonl.v:1: `line 1 "verilog/inc_ifdef.v" 1 verilog/inc_nonl.v:1: `line 1 "verilog/inc_ifdef.v" 0 verilog/inc_nonl.v:1: `line 1 "verilog/inc_nonl.v" 1 verilog/inc_nonl.v:1: `line 1 "verilog/inc_nonl.v" 0 verilog/inc_nonl.v:1: `line 1 "verilog/inc_def09.v" 1 verilog/inc_def09.v:1: // DESCRIPTION: Verilog-Perl: Verilog Test module verilog/inc_def09.v:2: // verilog/inc_def09.v:3: // This file ONLY is placed into the Public Domain, for any use, verilog/inc_def09.v:4: // without warranty, 2009 by Wilson Snyder. verilog/inc_def09.v:5: verilog/inc_def09.v:6: verilog/inc_def09.v:7: verilog/inc_def09.v:8: // Definitions as speced verilog/inc_def09.v:9: // Note there are trailing spaces, which spec doesn't show properly verilog/inc_def09.v:10: verilog/inc_def09.v:11: 'initial $display("start", "msg1" , "msg2", "end");' verilog/inc_def09.v:12: 'initial $display("start", "msg1" , "msg2" , "end");' verilog/inc_def09.v:13: 'initial $display("start", " msg1" , , "end");' verilog/inc_def09.v:14: 'initial $display("start", " msg1" , , "end");' verilog/inc_def09.v:15: 'initial $display("start", , "msg2 ", "end");' verilog/inc_def09.v:16: 'initial $display("start", , "msg2 ", "end");' verilog/inc_def09.v:17: 'initial $display("start", , , "end");' verilog/inc_def09.v:18: 'initial $display("start", , , "end");' verilog/inc_def09.v:19: 'initial $display("start", , , "end");' verilog/inc_def09.v:20: 'initial $display("start", , , "end");' verilog/inc_def09.v:21: //`D("msg1") // ILLEGAL: only one argument verilog/inc_def09.v:22: //`D() // ILLEGAL: only one empty argument verilog/inc_def09.v:23: //`D(,,) // ILLEGAL: more actual than formal arguments verilog/inc_def09.v:24: verilog/inc_def09.v:25: // Defaults: verilog/inc_def09.v:26: verilog/inc_def09.v:27: '$display(5,,2,,3);' verilog/inc_def09.v:28: '$display(5,,2,,3);' verilog/inc_def09.v:29: '$display(1,,"B",,3);' verilog/inc_def09.v:30: '$display(1 ,,"B",,3 );' verilog/inc_def09.v:31: '$display(5,,2,,);' verilog/inc_def09.v:32: '$display(5,,2,,);' verilog/inc_def09.v:33: //`MACRO1 ( 1 ) // ILLEGAL: b and c omitted, no default for c verilog/inc_def09.v:34: verilog/inc_def09.v:35: verilog/inc_def09.v:36: '$display(1,,,,3);' verilog/inc_def09.v:37: '$display(5,,,,"C");' verilog/inc_def09.v:38: '$display(5,,2,,"C");' verilog/inc_def09.v:39: '$display(5,,2,,"C");' verilog/inc_def09.v:40: '$display(5,,2,,"C");' verilog/inc_def09.v:41: '$display(5,,2,,"C");' verilog/inc_def09.v:42: verilog/inc_def09.v:43: verilog/inc_def09.v:44: '$display(1,,0,,"C");' verilog/inc_def09.v:45: '$display(1 ,,0,,"C");' verilog/inc_def09.v:46: '$display(5,,0,,"C");' verilog/inc_def09.v:47: '$display(5,,0,,"C");' verilog/inc_def09.v:48: //`MACRO3 // ILLEGAL: parentheses required verilog/inc_def09.v:49: verilog/inc_def09.v:50: verilog/inc_def09.v:51: 'b + 1 + 42 + a' verilog/inc_def09.v:52: 'b + 1 + 42 + a' verilog/inc_def09.v:53: verilog/inc_def09.v:54: // Local tests verilog/inc_def09.v:55: verilog/inc_def09.v:56: '"==)" "((((" () '; verilog/inc_def09.v:57: '"==)" "((((" () '; verilog/inc_def09.v:58: verilog/inc_def09.v:59: // Also check our line counting doesn't go bad verilog/inc_def09.v:62: verilog/inc_def09.v:62: verilog/inc_def09.v:62: verilog/inc_def09.v:63: verilog/inc_def09.v:64: verilog/inc_def09.v:65: verilog/inc_def09.v:66: verilog/inc_def09.v:67: verilog/inc_def09.v:68: verilog/inc_def09.v:69: verilog/inc_def09.v:70: '(6) (eq=al) ZOT' verilog/inc_def09.v:71: HERE-71 - Line71 verilog/inc_def09.v:72: verilog/inc_def09.v:73: //====================================================================== verilog/inc_def09.v:74: verilog/inc_def09.v:75: `line 75 "verilog/inc_def09.v" 2 verilog/inc_nonl.v:1: `line 1 "verilog/inc_nonl.v" 0 verilog/inc_nonl.v:1: // The lack of a newline on the next line is intentional verilog/inc_nonl.v:2: blah-no-newline-here> verilog/inc_nonl.v:3: `line 3 "verilog/inc_nonl.v" 2 verilog/inc_ifdef.v:1: `line 1 "verilog/inc_ifdef.v" 0 verilog/inc_ifdef.v:1: // DESCRIPTION: Verilog::Preproc: Example source code verilog/inc_ifdef.v:2: // This file ONLY is placed into the Public Domain, for any use, verilog/inc_ifdef.v:3: // without warranty, 2000-2012 by Wilson Snyder. verilog/inc_ifdef.v:4: verilog/inc_ifdef.v:5: verilog/inc_ifdef.v:6: verilog/inc_ifdef.v:7: verilog/inc_ifdef.v:8: verilog/inc_ifdef.v:9: verilog/inc_ifdef.v:10: verilog/inc_ifdef.v:11: verilog/inc_ifdef.v:12: $display("1A"); verilog/inc_ifdef.v:13: verilog/inc_ifdef.v:14: verilog/inc_ifdef.v:15: verilog/inc_ifdef.v:16: $display("2A"); verilog/inc_ifdef.v:17: verilog/inc_ifdef.v:18: verilog/inc_ifdef.v:19: verilog/inc_ifdef.v:20: verilog/inc_ifdef.v:21: verilog/inc_ifdef.v:22: $display("3AELSE"); verilog/inc_ifdef.v:23: verilog/inc_ifdef.v:24: verilog/inc_ifdef.v:25: verilog/inc_ifdef.v:26: verilog/inc_ifdef.v:27: verilog/inc_ifdef.v:28: verilog/inc_ifdef.v:29: verilog/inc_ifdef.v:30: verilog/inc_ifdef.v:31: verilog/inc_ifdef.v:32: verilog/inc_ifdef.v:33: verilog/inc_ifdef.v:34: verilog/inc_ifdef.v:35: verilog/inc_ifdef.v:36: verilog/inc_ifdef.v:37: verilog/inc_ifdef.v:38: verilog/inc_ifdef.v:39: verilog/inc_ifdef.v:40: verilog/inc_ifdef.v:41: verilog/inc_ifdef.v:42: `line 42 "verilog/inc_ifdef.v" 2 verilog/inc2.v:1: `line 1 "verilog/inc2.v" 0 verilog/inc2.v:1: // DESCRIPTION: Verilog::Preproc: Example source code verilog/inc2.v:2: // This file ONLY is placed into the Public Domain, for any use, verilog/inc2.v:3: // without warranty, 2000-2012 by Wilson Snyder. verilog/inc2.v:4: At file "verilog/inc2.v" line 4 verilog/inc2.v:5: verilog/inc2.v:5: `line 5 "verilog/inc2.v" 0 verilog/inc2.v:5: `line 1 "verilog/t_preproc_inc3.vh" 1 verilog/t_preproc_inc3.vh:1: `line 2 "inc3_a_filename_from_line_directive" 0 inc3_a_filename_from_line_directive:2: // DESCRIPTION: Verilog::Preproc: Example source code inc3_a_filename_from_line_directive:3: // This file ONLY is placed into the Public Domain, for any use, inc3_a_filename_from_line_directive:4: // without warranty, 2000-2012 by Wilson Snyder. inc3_a_filename_from_line_directive:5: inc3_a_filename_from_line_directive:6: inc3_a_filename_from_line_directive:7: inc3_a_filename_from_line_directive:8: inc3_a_filename_from_line_directive:9: // FOO inc3_a_filename_from_line_directive:10: At file "inc3_a_filename_from_line_directive" line 10 inc3_a_filename_from_line_directive:11: inc3_a_filename_from_line_directive:12: inc3_a_filename_from_line_directive:13: // guard inc3_a_filename_from_line_directive:14: inc3_a_filename_from_line_directive:15: inc3_a_filename_from_line_directive:16: inc3_a_filename_from_line_directive:17: inc3_a_filename_from_line_directive:18: inc3_a_filename_from_line_directive:19: `line 19 "inc3_a_filename_from_line_directive" 2 verilog/inc2.v:5: `line 5 "verilog/inc2.v" 0 verilog/inc2.v:5: verilog/inc2.v:6: verilog/inc2.v:7: `line 7 "verilog/inc2.v" 2 verilog/inc1.v:1: `line 1 "verilog/inc1.v" 0 verilog/inc1.v:1: // DESCRIPTION: Verilog::Preproc: Example source code verilog/inc1.v:2: // This file ONLY is placed into the Public Domain, for any use, verilog/inc1.v:3: // without warranty, 2000-2012 by Wilson Snyder. verilog/inc1.v:4: text. verilog/inc1.v:5: verilog/inc1.v:6: //=========================================================================== verilog/inc1.v:7: // Includes verilog/inc1.v:8: verilog/inc1.v:9: //=========================================================================== verilog/inc1.v:10: // Defines verilog/inc1.v:11: verilog/inc1.v:12: verilog/inc1.v:13: verilog/inc1.v:14: // DEF_A0 set by command line verilog/inc1.v:15: wire [3:0] q = { verilog/inc1.v:16: 1'b1 , verilog/inc1.v:17: 1'b0 , verilog/inc1.v:18: 1'b1 , verilog/inc1.v:19: 1'b0 verilog/inc1.v:20: }; verilog/inc1.v:21: verilog/inc1.v:22: text. verilog/inc1.v:23: verilog/inc1.v:24: verilog/inc1.v:25: // but not verilog/inc1.v:26: foo /*this */ bar /* this too */ verilog/inc1.v:27: foobar2 verilog/inc1.v:28: verilog/inc1.v:29: verilog/inc1.v:29: verilog/inc1.v:29: verilog/inc1.v:32: verilog/inc1.v:33: verilog/inc1.v:33: verilog/inc1.v:33: verilog/inc1.v:33: verilog/inc1.v:37: verilog/inc1.v:38: /*******COMMENT*****/ verilog/inc1.v:39: first part verilog/inc1.v:39: `line 39 "verilog/inc1.v" 0 verilog/inc1.v:39: second part verilog/inc1.v:39: `line 39 "verilog/inc1.v" 0 verilog/inc1.v:39: third part verilog/inc1.v:40: { verilog/inc1.v:40: `line 40 "verilog/inc1.v" 0 verilog/inc1.v:40: a, verilog/inc1.v:40: `line 40 "verilog/inc1.v" 0 verilog/inc1.v:40: b, verilog/inc1.v:40: `line 40 "verilog/inc1.v" 0 verilog/inc1.v:40: c} verilog/inc1.v:41: Line_Preproc_Check 41 verilog/inc1.v:42: verilog/inc1.v:43: //=========================================================================== verilog/inc1.v:44: verilog/inc1.v:45: verilog/inc1.v:46: verilog/inc1.v:47: verilog/inc1.v:48: verilog/inc1.v:49: deep deep verilog/inc1.v:50: verilog/inc1.v:51: verilog/inc1.v:52: verilog/inc1.v:53: "Inside: `nosubst" verilog/inc1.v:54: "`nosubst" verilog/inc1.v:55: verilog/inc1.v:56: verilog/inc1.v:57: x y LLZZ x y verilog/inc1.v:58: p q LLZZ p q r s LLZZ r s LLZZ p q LLZZ p q r s LLZZ r s verilog/inc1.v:59: verilog/inc1.v:60: verilog/inc1.v:61: verilog/inc1.v:62: firstline comma","line LLZZ firstline comma","line verilog/inc1.v:63: verilog/inc1.v:64: verilog/inc1.v:65: x y LLZZ "x" y // Simulators disagree here; some substitute "a" others do not verilog/inc1.v:66: verilog/inc1.v:67: verilog/inc1.v:68: (a,b)(a,b) verilog/inc1.v:69: verilog/inc1.v:70: verilog/inc1.v:71: $display("left side: \"right side\"") verilog/inc1.v:72: verilog/inc1.v:73: verilog/inc1.v:74: bar_suffix more verilog/inc1.v:75: verilog/inc1.v:76: verilog/inc1.v:76: verilog/inc1.v:78: verilog/inc1.v:78: `line 78 "verilog/inc1.v" 0 verilog/inc1.v:78: $c("Zap(\"",bug1,"\");");; verilog/inc1.v:79: verilog/inc1.v:79: `line 79 "verilog/inc1.v" 0 verilog/inc1.v:79: $c("Zap(\"","bug2","\");");; verilog/inc1.v:80: verilog/inc1.v:81: /* Define inside comment: `DEEPER and `WITHTICK */ verilog/inc1.v:82: // More commentary: `zap(bug1); `zap("bug2"); verilog/inc1.v:83: verilog/inc1.v:84: //====================================================================== verilog/inc1.v:85: // display passthru verilog/inc1.v:86: verilog/inc1.v:87: verilog/inc1.v:88: verilog/inc1.v:89: verilog/inc1.v:90: verilog/inc1.v:91: // Doesn't expand verilog/inc1.v:92: verilog/inc1.v:93: initial begin verilog/inc1.v:94: //$display(`msg( \`, \`)); // Illegal verilog/inc1.v:95: $display("pre thrupre thrumid thrupost post: \"right side\""); verilog/inc1.v:96: $display("left side: \"right side\""); verilog/inc1.v:97: $display("left side: \"right side\""); verilog/inc1.v:98: $display("left_side: \"right_side\""); verilog/inc1.v:99: $display("na: \"right_side\""); verilog/inc1.v:100: $display("prep ( midp1 left_side midp2 ( outp ) ): \"right_side\""); verilog/inc1.v:101: $display("na: \"nana\""); verilog/inc1.v:102: $display("left_side right_side: \"left_side right_side\""); // Results vary between simulators verilog/inc1.v:103: $display(": \"\""); // Empty verilog/inc1.v:104: $display("left side: \"right side\""); verilog/inc1.v:105: $display("left side: \"right side\""); verilog/inc1.v:106: $display("standalone"); verilog/inc1.v:107: verilog/inc1.v:108: // Unspecified when the stringification has multiple lines verilog/inc1.v:109: verilog/inc1.v:109: verilog/inc1.v:111: $display("twoline: \"first second\""); verilog/inc1.v:112: //$display(`msg(left side, \ right side \ )); // Not sure \{space} is legal. verilog/inc1.v:113: $write("*-* All Finished *-*\n"); verilog/inc1.v:114: $finish; verilog/inc1.v:115: end verilog/inc1.v:116: endmodule verilog/inc1.v:117: verilog/inc1.v:118: //====================================================================== verilog/inc1.v:119: // rt.cpan.org bug34429 verilog/inc1.v:120: verilog/inc1.v:121: verilog/inc1.v:121: verilog/inc1.v:121: verilog/inc1.v:121: verilog/inc1.v:125: verilog/inc1.v:126: module add1 ( input wire d1, output wire o1); verilog/inc1.v:127: verilog/inc1.v:127: `line 127 "verilog/inc1.v" 0 verilog/inc1.v:127: wire tmp_d1 = d1; verilog/inc1.v:127: `line 127 "verilog/inc1.v" 0 verilog/inc1.v:127: wire tmp_o1 = tmp_d1 + 1; verilog/inc1.v:127: `line 127 "verilog/inc1.v" 0 verilog/inc1.v:127: assign o1 = tmp_o1 ; // expansion is OK verilog/inc1.v:128: endmodule verilog/inc1.v:129: module add2 ( input wire d2, output wire o2); verilog/inc1.v:130: verilog/inc1.v:130: `line 130 "verilog/inc1.v" 0 verilog/inc1.v:130: wire tmp_d2 = d2; verilog/inc1.v:130: `line 130 "verilog/inc1.v" 0 verilog/inc1.v:130: wire tmp_o2 = tmp_d2 + 1; verilog/inc1.v:130: `line 130 "verilog/inc1.v" 0 verilog/inc1.v:130: assign o2 = tmp_o2 ; // expansion is bad verilog/inc1.v:131: endmodule verilog/inc1.v:132: verilog/inc1.v:133: verilog/inc1.v:133: verilog/inc1.v:133: verilog/inc1.v:133: verilog/inc1.v:133: verilog/inc1.v:138: verilog/inc1.v:139: // parameterized macro with arguments that are macros verilog/inc1.v:140: verilog/inc1.v:141: verilog/inc1.v:142: verilog/inc1.v:143: verilog/inc1.v:144: verilog/inc1.v:144: `line 144 "verilog/inc1.v" 0 verilog/inc1.v:144: generate for (i=0; i<(3); i=i+1) begin verilog/inc1.v:144: `line 144 "verilog/inc1.v" 0 verilog/inc1.v:144: psl cover { m5k.f .ctl._ctl_mvldx_m1.d[i] & ~m5k.f .ctl._ctl_mvldx_m1.q[i] & !m5k.f .ctl._ctl_mvldx_m1.cond & ((m5k.f .ctl.alive & m5k.f .ctl.alive_m1))} report "fondNoRise: m5kc_fcl._ctl_mvldx_m1"; verilog/inc1.v:144: `line 144 "verilog/inc1.v" 0 verilog/inc1.v:144: psl cover { ~m5k.f .ctl._ctl_mvldx_m1.d[i] & m5k.f .ctl._ctl_mvldx_m1.q[i] & !m5k.f .ctl._ctl_mvldx_m1.cond & ((m5k.f .ctl.alive & m5k.f .ctl.alive_m1))} report "fondNoFall: m5kc_fcl._ctl_mvldx_m1"; verilog/inc1.v:144: `line 144 "verilog/inc1.v" 0 verilog/inc1.v:144: end endgenerate // ignorecmt verilog/inc1.v:145: verilog/inc1.v:146: //====================================================================== verilog/inc1.v:147: // Quotes are legal in protected blocks. Grr. verilog/inc1.v:148: module prot(); verilog/inc1.v:149: `protected verilog/inc1.v:150: I!#r#e6<_Q{{E2+]I3<[3s)1@D|'E''i!O?]jD>Jo_![Cl) verilog/inc1.v:151: #nj1]p,3^1~,="E@QZB\T)eU\pC#C|7=\$J$##A[@-@{Qk] verilog/inc1.v:152: `endprotected verilog/inc1.v:153: endmodule verilog/inc1.v:154: verilog/inc1.v:155: module prot2(); verilog/inc1.v:156: `pragma protect begin_protected verilog/inc1.v:157: `pragma protect encrypt_agent = "Whatever agent" verilog/inc1.v:158: `pragma protect encrypt_agent_info = "1.2.3" verilog/inc1.v:159: `pragma protect data_method = "aes128-cbc" verilog/inc1.v:160: `pragma protect key_keyowner = "Someone" verilog/inc1.v:161: `pragma protect key_keyname = "somekey", key_method = "rsa" verilog/inc1.v:162: `pragma protect key_block encoding = (enctype = "base64") verilog/inc1.v:163: wefjosdfjklajklasjkl verilog/inc1.v:164: `pragma protect data_block encoding = (enctype = "base64", bytes = 1059) verilog/inc1.v:165: I!#r#e6<_Q{{E2+]I3<[3s)1@D|'E''i!O?]jD>Jo_![Cl) verilog/inc1.v:166: #nj1]p,3^1~,="E@QZB\T)eU\pC#C|7=\$J$##A[@-@{Qk] verilog/inc1.v:167: `pragma protect end_protected verilog/inc1.v:168: `pragma reset protect verilog/inc1.v:169: endmodule verilog/inc1.v:170: verilog/inc1.v:171: module prot3(); verilog/inc1.v:172: //pragma protect begin_protected verilog/inc1.v:173: //pragma protect key_keyowner=Cadence Design Systems. verilog/inc1.v:174: //pragma protect key_keyname=CDS_KEY verilog/inc1.v:175: //pragma protect key_method=RC5 verilog/inc1.v:176: //pragma protect key_block verilog/inc1.v:177: zzZzZ/4ZzzZZZzzz4zZzZzZZZZzZzZ/Zz+33zZ2zz/zzzzzzzzZZZzZ4z+ZZZZz1 verilog/inc1.v:178: Z1ZzzzZZzZZzz9ZZZZ37zzZzZzZzzz9ZZzzZzZz9Zz64+z8Z7ZzZZZzzzzZZZzZz verilog/inc1.v:179: zzZzZZZzZ0463zzzzzZzZ6z00z4zZzzZZzzZzzzZZ8zzz09ZzZZZZZ== verilog/inc1.v:180: //pragma protect end_key_block verilog/inc1.v:181: //pragma protect digest_block verilog/inc1.v:182: ZzZZzzZ9ZZZZz2ZzzzZz/Zzzz8Z= verilog/inc1.v:183: //pragma protect end_digest_block verilog/inc1.v:184: //pragma protect data_block verilog/inc1.v:185: ZZZ8zZzz6ZZ/zZZ5zZZzzz3ZzzzZzZZZ6ZzZzZZZZZz1zzZZZZ7ZZZZz3Zzz+9zz verilog/inc1.v:186: 4zzz+8zZzzzzZzZZzzzZzz1Z7ZzZz+zZz8ZZZZzZ6ZzzZzZZzzZZzzZzzZzZzZzZ verilog/inc1.v:187: ZzzzzZ0zZz1ZzzZzzZzZzz== verilog/inc1.v:188: //pragma protect end_data_block verilog/inc1.v:189: //pragma protect digest_block verilog/inc1.v:190: Z4Z6zZzZ3Z7ZZ6zzZZZZzzzzZZZ= verilog/inc1.v:191: //pragma protect end_digest_block verilog/inc1.v:192: //pragma protect end_protected verilog/inc1.v:193: endmodule verilog/inc1.v:194: verilog/inc1.v:195: //====================================================================== verilog/inc1.v:196: // macro call with define that has comma verilog/inc1.v:197: verilog/inc1.v:198: verilog/inc1.v:199: verilog/inc1.v:200: verilog/inc1.v:201: verilog/inc1.v:202: verilog/inc1.v:203: verilog/inc1.v:204: verilog/inc1.v:205: begin addr <= (({regs[6], regs[7]} + 1)); rd <= 1; end and begin addr <= (({regs[6], regs[7]})); wdata <= (rdata); wr <= 1; end verilog/inc1.v:206: begin addr <= ({regs[6], regs[7]} + 1); rd <= 1; end verilog/inc1.v:207: begin addr <= ({regs[6], regs[7]}); wdata <= (rdata); wr <= 1; end more verilog/inc1.v:208: verilog/inc1.v:209: //====================================================================== verilog/inc1.v:210: // include of parameterized file verilog/inc1.v:211: verilog/inc1.v:212: verilog/inc1.v:212: `line 212 "verilog/inc1.v" 0 verilog/inc1.v:212: `line 1 "verilog/t_preproc_inc4.vh" 1 verilog/t_preproc_inc4.vh:1: // DESCRIPTION: Verilog::Preproc: Example source code verilog/t_preproc_inc4.vh:2: `line 2 "verilog/t_preproc_inc4.vh" 0 verilog/t_preproc_inc4.vh:2: // This file ONLY is placed into the Public Domain, for any use, verilog/t_preproc_inc4.vh:3: // without warranty, 2000-2012 by Wilson Snyder. verilog/t_preproc_inc4.vh:4: verilog/t_preproc_inc4.vh:5: verilog/t_preproc_inc4.vh:6: verilog/t_preproc_inc4.vh:7: `line 7 "verilog/t_preproc_inc4.vh" 2 verilog/inc1.v:212: `line 212 "verilog/inc1.v" 0 verilog/inc1.v:212: verilog/inc1.v:213: verilog/inc1.v:214: verilog/inc1.v:215: verilog/inc1.v:216: verilog/inc1.v:217: verilog/inc1.v:218: verilog/inc1.v:219: verilog/inc1.v:220: verilog/inc1.v:221: verilog/inc1.v:222: //====================================================================== verilog/inc1.v:223: // macro call with , in {} verilog/inc1.v:224: verilog/inc1.v:225: verilog/inc1.v:226: $blah("ab,cd","e,f"); verilog/inc1.v:227: $blah(this.logfile,vec); verilog/inc1.v:228: $blah(this.logfile,vec[1,2,3]); verilog/inc1.v:229: $blah(this.logfile,{blah.name(), " is not foo"}); verilog/inc1.v:230: verilog/inc1.v:231: //====================================================================== verilog/inc1.v:232: // pragma/default net type verilog/inc1.v:233: verilog/inc1.v:234: `pragma foo = 1 verilog/inc1.v:235: `default_nettype none verilog/inc1.v:236: `default_nettype uwire verilog/inc1.v:237: verilog/inc1.v:238: //====================================================================== verilog/inc1.v:239: // Ifdef verilog/inc1.v:240: verilog/inc1.v:241: verilog/inc1.v:242: verilog/inc1.v:243: verilog/inc1.v:244: verilog/inc1.v:245: Line_Preproc_Check 245 verilog/inc1.v:246: verilog/inc1.v:247: //====================================================================== verilog/inc1.v:248: // bug84 verilog/inc1.v:249: verilog/inc1.v:252: // Hello, comments MIGHT not be legal/*more,,)cmts*/// But newlines ARE legal... who speced THAT? verilog/inc1.v:252: verilog/inc1.v:252: verilog/inc1.v:253: (p,q) verilog/inc1.v:254: //Here verilog/inc1.v:255: verilog/inc1.v:256: //Too verilog/inc1.v:257: (x,y) verilog/inc1.v:258: Line_Preproc_Check 258 verilog/inc1.v:259: verilog/inc1.v:260: //====================================================================== verilog/inc1.v:261: // defines split arguments verilog/inc1.v:262: verilog/inc1.v:263: verilog/inc1.v:264: verilog/inc1.v:265: verilog/inc1.v:266: verilog/inc1.v:267: beginend // 2001 spec doesn't require two tokens, so "beginend" ok verilog/inc1.v:268: beginend // 2001 spec doesn't require two tokens, so "beginend" ok verilog/inc1.v:269: "beginend" // No space "beginend" verilog/inc1.v:270: verilog/inc1.v:271: //====================================================================== verilog/inc1.v:272: // bug106 verilog/inc1.v:273: verilog/inc1.v:274: verilog/inc1.v:275: `\esc`def verilog/inc1.v:276: verilog/inc1.v:277: Not a \`define verilog/inc1.v:278: verilog/inc1.v:279: //====================================================================== verilog/inc1.v:280: // misparsed comma in submacro verilog/inc1.v:281: verilog/inc1.v:282: verilog/inc1.v:283: verilog/inc1.v:284: verilog/inc1.v:285: x,y)--bee submacro has comma paren verilog/inc1.v:286: verilog/inc1.v:287: //====================================================================== verilog/inc1.v:288: // bug191 verilog/inc1.v:289: verilog/inc1.v:290: $display("10 %d %d", $bits(foo), 10); verilog/inc1.v:291: verilog/inc1.v:292: //====================================================================== verilog/inc1.v:293: // 1800-2009 verilog/inc1.v:294: verilog/inc1.v:295: verilog/inc1.v:296: verilog/inc1.v:297: verilog/inc1.v:298: verilog/inc1.v:299: verilog/inc1.v:300: //====================================================================== verilog/inc1.v:301: // bug202 verilog/inc1.v:302: verilog/inc1.v:302: verilog/inc1.v:302: verilog/inc1.v:302: verilog/inc1.v:302: verilog/inc1.v:302: verilog/inc1.v:302: verilog/inc1.v:302: verilog/inc1.v:302: verilog/inc1.v:302: verilog/inc1.v:302: verilog/inc1.v:313: verilog/inc1.v:314: verilog/inc1.v:314: `line 314 "verilog/inc1.v" 0 verilog/inc1.v:314: verilog/inc1.v:314: `line 314 "verilog/inc1.v" 0 verilog/inc1.v:314: verilog/inc1.v:314: `line 314 "verilog/inc1.v" 0 verilog/inc1.v:314: verilog/inc1.v:314: `line 314 "verilog/inc1.v" 0 verilog/inc1.v:314: verilog/inc1.v:314: `line 314 "verilog/inc1.v" 0 verilog/inc1.v:314: verilog/inc1.v:314: `line 314 "verilog/inc1.v" 0 verilog/inc1.v:314: verilog/inc1.v:314: `line 314 "verilog/inc1.v" 0 verilog/inc1.v:314: verilog/inc1.v:314: `line 314 "verilog/inc1.v" 0 verilog/inc1.v:314: verilog/inc1.v:314: `line 314 "verilog/inc1.v" 0 verilog/inc1.v:314: assign a3 = ~b3 ; verilog/inc1.v:314: `line 314 "verilog/inc1.v" 0 verilog/inc1.v:314: verilog/inc1.v:315: verilog/inc1.v:316: /* multi \ verilog/inc1.v:317: line1*/ \ verilog/inc1.v:318: /*multi \ verilog/inc1.v:320: line2*/ verilog/inc1.v:320: verilog/inc1.v:320: verilog/inc1.v:320: verilog/inc1.v:320: verilog/inc1.v:320: verilog/inc1.v:325: verilog/inc1.v:325: `line 325 "verilog/inc1.v" 0 verilog/inc1.v:325: /* multi verilog/inc1.v:325: line 3*/ verilog/inc1.v:325: `line 325 "verilog/inc1.v" 0 verilog/inc1.v:325: def i verilog/inc1.v:325: `line 325 "verilog/inc1.v" 0 verilog/inc1.v:325: verilog/inc1.v:326: verilog/inc1.v:327: //====================================================================== verilog/inc1.v:328: verilog/inc1.v:329: // verilator NOT IN DEFINE verilog/inc1.v:330: verilog/inc1.v:331: /* verilator NOT PART verilog/inc1.v:332: OF DEFINE */ verilog/inc1.v:333: verilog/inc1.v:333: verilog/inc1.v:337: // CMT NOT verilog/inc1.v:337: verilog/inc1.v:337: verilog/inc1.v:338: verilog/inc1.v:339: 1 (nodef) verilog/inc1.v:340: 2 /* verilator PART OF DEFINE */ (hasdef) verilog/inc1.v:341: 3 (nodef) verilog/inc1.v:342: 4 /* verilator PART verilog/inc1.v:342: OF DEFINE */ (nodef) verilog/inc1.v:343: `line 343 "verilog/inc1.v" 0 verilog/inc1.v:343: 5 also in verilog/inc1.v:343: `line 343 "verilog/inc1.v" 0 verilog/inc1.v:343: also3 (nodef) verilog/inc1.v:344: verilog/inc1.v:344: verilog/inc1.v:346: HAS a NEW verilog/inc1.v:346: `line 346 "verilog/inc1.v" 0 verilog/inc1.v:346: LINE verilog/inc1.v:347: verilog/inc1.v:348: //====================================================================== verilog/inc1.v:349: verilog/inc1.v:350: verilog/inc1.v:350: verilog/inc1.v:350: verilog/inc1.v:350: verilog/inc1.v:350: verilog/inc1.v:350: verilog/inc1.v:350: verilog/inc1.v:350: verilog/inc1.v:350: verilog/inc1.v:350: verilog/inc1.v:350: verilog/inc1.v:350: verilog/inc1.v:362: verilog/inc1.v:363: verilog/inc1.v:364: verilog/inc1.v:365: verilog/inc1.v:366: EXP: clxx_scen verilog/inc1.v:367: clxx_scen verilog/inc1.v:368: EXP: clxx_scen verilog/inc1.v:369: "clxx_scen" verilog/inc1.v:370: verilog/inc1.v:371: EXP: do if (start("verilog/inc1.v", 25)) begin message({"Blah-", "clx_scen", " end"}); end while(0); verilog/inc1.v:372: verilog/inc1.v:372: `line 372 "verilog/inc1.v" 0 verilog/inc1.v:372: do verilog/inc1.v:372: `line 372 "verilog/inc1.v" 0 verilog/inc1.v:372: /* synopsys translate_off *//* synopsys translate_on */ verilog/inc1.v:372: `line 372 "verilog/inc1.v" 0 verilog/inc1.v:372: while(0); verilog/inc1.v:373: verilog/inc1.v:374: //====================================================================== verilog/inc1.v:375: verilog/inc1.v:376: verilog/inc1.v:376: verilog/inc1.v:376: verilog/inc1.v:376: verilog/inc1.v:380: verilog/inc1.v:380: `line 380 "verilog/inc1.v" 0 verilog/inc1.v:380: verilog/inc1.v:380: `line 380 "verilog/inc1.v" 0 verilog/inc1.v:380: verilog/inc1.v:380: `line 380 "verilog/inc1.v" 0 verilog/inc1.v:380: verilog/inc1.v:381: verilog/inc1.v:382: //`ifndef def_fooed_2 `error "No def_fooed_2" `endif verilog/inc1.v:383: EXP: This is fooed verilog/inc1.v:384: This is fooed verilog/inc1.v:385: EXP: This is fooed_2 verilog/inc1.v:386: This is fooed_2 verilog/inc1.v:387: verilog/inc1.v:388: //====================================================================== verilog/inc1.v:389: verilog/inc1.v:390: np verilog/inc1.v:391: np verilog/inc1.v:392: //====================================================================== verilog/inc1.v:393: // It's unclear if the spec allows this; is text_macro_idenitfier before or after substitution? verilog/inc1.v:394: verilog/inc1.v:395: verilog/inc1.v:396: verilog/inc1.v:397: verilog/inc1.v:398: verilog/inc1.v:399: verilog/inc1.v:400: verilog/inc1.v:401: verilog/inc1.v:402: //====================================================================== verilog/inc1.v:403: // Metaprogramming verilog/inc1.v:404: verilog/inc1.v:405: verilog/inc1.v:406: verilog/inc1.v:407: verilog/inc1.v:408: verilog/inc1.v:409: verilog/inc1.v:410: verilog/inc1.v:411: verilog/inc1.v:412: verilog/inc1.v:413: verilog/inc1.v:414: hello3hello3hello3 verilog/inc1.v:415: hello4hello4hello4hello4 verilog/inc1.v:416: //====================================================================== verilog/inc1.v:417: // Include from stringification verilog/inc1.v:418: verilog/inc1.v:419: verilog/inc1.v:420: verilog/inc1.v:420: `line 420 "verilog/inc1.v" 0 verilog/inc1.v:420: `line 1 "verilog/t_preproc_inc4.vh" 1 verilog/t_preproc_inc4.vh:1: // DESCRIPTION: Verilog::Preproc: Example source code verilog/t_preproc_inc4.vh:2: `line 2 "verilog/t_preproc_inc4.vh" 0 verilog/t_preproc_inc4.vh:2: // This file ONLY is placed into the Public Domain, for any use, verilog/t_preproc_inc4.vh:3: // without warranty, 2000-2012 by Wilson Snyder. verilog/t_preproc_inc4.vh:4: verilog/t_preproc_inc4.vh:5: verilog/t_preproc_inc4.vh:6: verilog/t_preproc_inc4.vh:7: `line 7 "verilog/t_preproc_inc4.vh" 2 verilog/inc1.v:420: `line 420 "verilog/inc1.v" 0 verilog/inc1.v:420: verilog/inc1.v:421: verilog/inc1.v:422: //====================================================================== verilog/inc1.v:423: // Defines doing defines verilog/inc1.v:424: // Note the newline on the end - required to form the end of a define verilog/inc1.v:425: verilog/inc1.v:425: verilog/inc1.v:427: verilog/inc1.v:428: verilog/inc1.v:429: verilog/inc1.v:429: `line 429 "verilog/inc1.v" 0 verilog/inc1.v:429: verilog/inc1.v:430: verilog/inc1.v:431: verilog/inc1.v:432: verilog/inc1.v:433: Line_Preproc_Check 433 verilog/inc1.v:434: //====================================================================== verilog/inc1.v:435: // Quoted multiline - track line numbers, and insure \\n gets propagated verilog/inc1.v:436: verilog/inc1.v:436: verilog/inc1.v:438: verilog/inc1.v:439: Line_Preproc_Check 439 verilog/inc1.v:441: verilog/inc1.v:441: "FOO \ verilog/inc1.v:441: BAR " "arg_line1 \ verilog/inc1.v:441: arg_line2" "FOO \ verilog/inc1.v:441: BAR " verilog/inc1.v:442: `line 442 "verilog/inc1.v" 0 verilog/inc1.v:442: Line_Preproc_Check 442 verilog/inc1.v:443: //====================================================================== verilog/inc1.v:444: // bug283 verilog/inc1.v:445: verilog/inc1.v:446: verilog/inc1.v:447: verilog/inc1.v:448: verilog/inc1.v:449: // EXP: abc verilog/inc1.v:450: verilog/inc1.v:451: abc verilog/inc1.v:452: verilog/inc1.v:453: verilog/inc1.v:454: verilog/inc1.v:455: verilog/inc1.v:456: verilog/inc1.v:457: verilog/inc1.v:458: verilog/inc1.v:459: EXP: sonet_frame verilog/inc1.v:460: sonet_frame verilog/inc1.v:461: // verilog/inc1.v:462: verilog/inc1.v:463: verilog/inc1.v:464: EXP: sonet_frame verilog/inc1.v:465: sonet_frame verilog/inc1.v:466: // This result varies between simulators verilog/inc1.v:467: verilog/inc1.v:468: verilog/inc1.v:469: EXP: sonet_frame verilog/inc1.v:470: sonet_frame verilog/inc1.v:471: verilog/inc1.v:472: // The existance of non-existance of a base define can make a difference verilog/inc1.v:473: verilog/inc1.v:474: verilog/inc1.v:475: EXP: module zzz ; endmodule verilog/inc1.v:476: module zzz ; endmodule verilog/inc1.v:477: module zzz ; endmodule verilog/inc1.v:478: verilog/inc1.v:479: verilog/inc1.v:480: EXP: module a_b ; endmodule verilog/inc1.v:481: module a_b ; endmodule verilog/inc1.v:482: module a_b ; endmodule verilog/inc1.v:483: verilog/inc1.v:484: //====================================================================== verilog/inc1.v:485: // bug311 verilog/inc1.v:486: integer/*NEED_SPACE*/foo; verilog/inc1.v:487: //====================================================================== verilog/inc1.v:488: synth_test: verilog/inc1.v:489: // synopsys translate_off verilog/inc1.v:491: // synthesis translate_on verilog/inc1.v:492: verilog/inc1.v:492: EXP: on verilog/inc1.v:493: //====================================================================== verilog/inc1.v:494: // bug441 verilog/inc1.v:495: module t; verilog/inc1.v:496: //----- verilog/inc1.v:497: // case provided verilog/inc1.v:498: // note this does NOT escape as suggested in the mail verilog/inc1.v:499: verilog/inc1.v:500: verilog/inc1.v:500: verilog/inc1.v:502: initial begin : \`LEX_CAT(a[0],_assignment) verilog/inc1.v:502: `line 502 "verilog/inc1.v" 0 verilog/inc1.v:502: $write("GOT%%m='%m' EXP='%s'\n", "t.\\`LEX_CAT(a[0],_assignment) "); end verilog/inc1.v:503: //----- verilog/inc1.v:504: // SHOULD(simulator-dependant): Backslash doesn't prevent arguments from verilog/inc1.v:505: // substituting and the \ staying in the expansion verilog/inc1.v:506: // Note space after name is important so when substitute it has ending whitespace verilog/inc1.v:507: verilog/inc1.v:507: verilog/inc1.v:509: initial begin : \a[0]_assignment_a[1] verilog/inc1.v:509: `line 509 "verilog/inc1.v" 0 verilog/inc1.v:509: $write("GOT%%m='%m' EXP='%s'\n", "t.\\a[0]_assignment_a[1] "); end verilog/inc1.v:510: verilog/inc1.v:511: //----- verilog/inc1.v:512: verilog/inc1.v:513: verilog/inc1.v:514: // RULE: Ignoring backslash does NOT allow an additional expansion level verilog/inc1.v:515: // (Because ESC gets expanded then the \ has it's normal escape meaning) verilog/inc1.v:516: initial begin : \`CAT(pp,suffix) $write("GOT%%m='%m' EXP='%s'\n", "t.\\`CAT(pp,suffix) "); end verilog/inc1.v:517: verilog/inc1.v:518: //----- verilog/inc1.v:519: verilog/inc1.v:520: verilog/inc1.v:520: verilog/inc1.v:522: // Similar to above; \ does not allow expansion after substitution verilog/inc1.v:523: initial begin : \`CAT(ff,bb) verilog/inc1.v:523: `line 523 "verilog/inc1.v" 0 verilog/inc1.v:523: $write("GOT%%m='%m' EXP='%s'\n", "t.\\`CAT(ff,bb) "); end verilog/inc1.v:524: verilog/inc1.v:525: //----- verilog/inc1.v:526: verilog/inc1.v:526: verilog/inc1.v:528: // MUST: Unknown macro with backslash escape stays as escaped symbol name verilog/inc1.v:529: initial begin : \`zzz verilog/inc1.v:529: `line 529 "verilog/inc1.v" 0 verilog/inc1.v:529: $write("GOT%%m='%m' EXP='%s'\n", "t.\\`zzz "); end verilog/inc1.v:530: verilog/inc1.v:531: //----- verilog/inc1.v:532: verilog/inc1.v:533: verilog/inc1.v:533: verilog/inc1.v:535: // SHOULD(simulator-dependant): Known macro with backslash escape expands verilog/inc1.v:536: initial begin : \`FOO verilog/inc1.v:536: `line 536 "verilog/inc1.v" 0 verilog/inc1.v:536: $write("GOT%%m='%m' OTHER_EXP='%s'\n OUR_EXP='%s'", "t.bar ","t.\\`FOO "); end verilog/inc1.v:537: // SHOULD(simulator-dependant): Prefix breaks the above verilog/inc1.v:538: initial begin : \xx`FOO verilog/inc1.v:538: `line 538 "verilog/inc1.v" 0 verilog/inc1.v:538: $write("GOT%%m='%m' EXP='%s'\n", "t.\\xx`FOO "); end verilog/inc1.v:539: verilog/inc1.v:540: //----- verilog/inc1.v:541: // MUST: Unknown macro not under call with backslash escape doesn't expand verilog/inc1.v:542: verilog/inc1.v:543: initial begin : \`UNKNOWN $write("GOT%%m='%m' EXP='%s'\n", "t.\\`UNKNOWN "); end verilog/inc1.v:544: //----- verilog/inc1.v:545: // MUST: Unknown macro not under call doesn't expand verilog/inc1.v:546: verilog/inc1.v:547: initial begin : \`DEF_NO_EXPAND $write("GOT%%m='%m' EXP='%s'\n", "t.\\`DEF_NO_EXPAND "); end verilog/inc1.v:548: verilog/inc1.v:549: //----- verilog/inc1.v:550: // bug441 derivative verilog/inc1.v:551: // SHOULD(simulator-dependant): Quotes doesn't prevent arguments from expanding (like backslashes above) verilog/inc1.v:552: verilog/inc1.v:553: initial $write("GOT='%s' EXP='%s'\n", "foo bar baz", "foo bar baz"); verilog/inc1.v:554: verilog/inc1.v:555: //----- verilog/inc1.v:556: // RULE: Because there are quotes after substituting STR, the `A does NOT expand verilog/inc1.v:557: verilog/inc1.v:558: verilog/inc1.v:559: initial $write("GOT='%s' EXP='%s'\n", "foo `A(bar) baz", "foo `A(bar) baz"); verilog/inc1.v:560: verilog/inc1.v:561: //---- verilog/inc1.v:562: // bug845 verilog/inc1.v:563: verilog/inc1.v:564: initial $write("Slashed=`%s'\n", "1//2.3"); verilog/inc1.v:565: //---- verilog/inc1.v:566: // bug915 verilog/inc1.v:567: verilog/inc1.v:567: verilog/inc1.v:569: initial verilog/inc1.v:569: `line 569 "verilog/inc1.v" 0 verilog/inc1.v:569: $display("%s%s","a1","b2c3\n"); verilog/inc1.v:570: endmodule verilog/inc1.v:571: verilog/inc1.v:572: //====================================================================== verilog/inc1.v:573: //bug1225 verilog/inc1.v:574: verilog/inc1.v:575: verilog/inc1.v:576: verilog/inc1.v:577: $display("RAM0"); verilog/inc1.v:578: $display("CPU"); verilog/inc1.v:579: verilog/inc1.v:580: verilog/inc1.v:581: verilog/inc1.v:582: verilog/inc1.v:583: verilog/inc1.v:584: verilog/inc1.v:585: verilog/inc1.v:586: XXE_FAMILY = XXE_ verilog/inc1.v:587: verilog/inc1.v:588: verilog/inc1.v:589: $display("XXE_ is defined"); verilog/inc1.v:590: verilog/inc1.v:591: verilog/inc1.v:592: verilog/inc1.v:593: XYE_FAMILY = XYE_ verilog/inc1.v:594: verilog/inc1.v:595: verilog/inc1.v:596: $display("XYE_ is defined"); verilog/inc1.v:597: verilog/inc1.v:598: verilog/inc1.v:599: verilog/inc1.v:600: XXS_FAMILY = XXS_some verilog/inc1.v:601: verilog/inc1.v:602: verilog/inc1.v:603: $display("XXS_some is defined"); verilog/inc1.v:604: verilog/inc1.v:605: verilog/inc1.v:606: verilog/inc1.v:607: XYS_FAMILY = XYS_foo verilog/inc1.v:608: verilog/inc1.v:609: verilog/inc1.v:610: $display("XYS_foo is defined"); verilog/inc1.v:611: verilog/inc1.v:612: verilog/inc1.v:613: //==== verilog/inc1.v:614: verilog/inc1.v:615: verilog/inc1.v:616: verilog/inc1.v:617: verilog/inc1.v:618: verilog/inc1.v:619: verilog/inc1.v:620: verilog/inc1.v:621: verilog/inc1.v:622: verilog/inc1.v:623: verilog/inc1.v:624: verilog/inc1.v:625: verilog/inc1.v:626: verilog/inc1.v:627: verilog/inc1.v:628: verilog/inc1.v:629: verilog/inc1.v:630: verilog/inc1.v:631: verilog/inc1.v:632: verilog/inc1.v:633: verilog/inc1.v:634: verilog/inc1.v:635: verilog/inc1.v:636: verilog/inc1.v:637: verilog/inc1.v:638: verilog/inc1.v:639: verilog/inc1.v:640: verilog/inc1.v:641: verilog/inc1.v:642: verilog/inc1.v:643: verilog/inc1.v:644: verilog/inc1.v:645: verilog/inc1.v:646: // NEVER verilog/inc1.v:647: verilog/inc1.v:648: //bug1227 verilog/inc1.v:649: verilog/inc1.v:650: (.mySig (myInterface.pa5), verilog/inc1.v:651: verilog/inc1.v:652: //====================================================================== verilog/inc1.v:653: // Stringify bug verilog/inc1.v:654: verilog/inc1.v:655: verilog/inc1.v:656: `dbg_hdl(UVM_LOW, ("Functional coverage enabled: paramgrp")); verilog/inc1.v:657: verilog/inc1.v:658: verilog/inc1.v:659: verilog/inc1.v:659: verilog/inc1.v:661: verilog/inc1.v:661: verilog/inc1.v:661: verilog/inc1.v:661: verilog/inc1.v:665: verilog/inc1.v:666: module pcc2_cfg; verilog/inc1.v:667: generate verilog/inc1.v:668: verilog/inc1.v:668: `line 668 "verilog/inc1.v" 0 verilog/inc1.v:668: covergroup a @(posedge b); verilog/inc1.v:668: `line 668 "verilog/inc1.v" 0 verilog/inc1.v:668: c: coverpoint d iff ((c) === 1'b1); endgroup verilog/inc1.v:668: `line 668 "verilog/inc1.v" 0 verilog/inc1.v:668: a u_a; verilog/inc1.v:668: `line 668 "verilog/inc1.v" 0 verilog/inc1.v:668: initial do begin $display ("DEBUG : %s [%m]", $sformatf ("Functional coverage enabled: u_a")); end while(0); verilog/inc1.v:669: endgenerate verilog/inc1.v:670: endmodule verilog/inc1.v:671: verilog/inc1.v:672: //====================================================================== verilog/inc1.v:673: // Verilog-Perl bug1668 verilog/inc1.v:674: verilog/inc1.v:675: "`NOT_DEFINED_STR" verilog/inc1.v:676: verilog/inc1.v:677: //====================================================================== verilog/inc1.v:678: // IEEE mandated predefines verilog/inc1.v:679: // undefineall should have no effect on these verilog/inc1.v:680: predef 0 0 verilog/inc1.v:681: predef 1 1 verilog/inc1.v:682: predef 2 2 verilog/inc1.v:683: predef 3 3 verilog/inc1.v:684: predef 10 10 verilog/inc1.v:685: predef 11 11 verilog/inc1.v:686: predef 20 20 verilog/inc1.v:687: predef 21 21 verilog/inc1.v:688: predef 22 22 verilog/inc1.v:689: predef 23 23 verilog/inc1.v:690: predef -2 -2 verilog/inc1.v:691: predef -1 -1 verilog/inc1.v:692: predef 0 0 verilog/inc1.v:693: predef 1 1 verilog/inc1.v:694: predef 2 2 verilog/inc1.v:695: verilog/inc1.v:696: `line 696 "verilog/inc1.v" 2 Verilog-Perl-3.482/t/85_vhier_xml.out0000644000177100017500000000232614030463163017324 0ustar wsnyderwsnyder verilog/v_hier_top.v verilog/v_hier_sub.v verilog/v_recursive.v verilog/v_hier_subsub.v verilog/v_hier_inc.vh verilog/v_hier_sub.v verilog/v_hier_subsub.v verilog/v_hier_top.v verilog/v_recursive.v Verilog-Perl-3.482/t/60_vpassert.out0000644000177100017500000004162713234726611017203 0ustar wsnyderwsnyder/* Generated by vpassert; File:"verilog/example.v" */ `line 1 "verilog/example.v" 0 // DESCRIPTION: Example top verilog file for vpassert program // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2000-2012 by Wilson Snyder. `timescale 1ns/1ns module example;/*vpassert*/integer __message; initial __message = 5;reg _assertreqack1_busy_r; initial _assertreqack1_busy_r = 0;reg _assertreqack1_data0_r; initial _assertreqack1_data0_r = 0;reg _ucoverclk10; initial _ucoverclk10 = 0;reg _ucoverclk11; initial _ucoverclk11 = 0;reg _ucoverclk12; initial _ucoverclk12 = 0;reg _ucoverclk13; initial _ucoverclk13 = 0;reg _ucoverclk14; initial _ucoverclk14 = 0;reg _ucoverclk15; initial _ucoverclk15 = 0;reg _ucoverclk16; initial _ucoverclk16 = 0;reg _ucoverclk17; initial _ucoverclk17 = 0; reg _ucoverclk18; initial _ucoverclk18 = 0;reg _ucoverclk19; initial _ucoverclk19 = 0;reg _ucoverclk20; initial _ucoverclk20 = 0;reg _ucoverclk21; initial _ucoverclk21 = 0;reg _ucoverclk22; initial _ucoverclk22 = 0;reg _ucoverclk23; initial _ucoverclk23 = 0;reg _ucoverclk24; initial _ucoverclk24 = 0;reg _ucoverclk25; initial _ucoverclk25 = 0;reg _ucoverclk26; initial _ucoverclk26 = 0;reg _ucoverclk27; initial _ucoverclk27 = 0;reg _ucoverclk28; initial _ucoverclk28 = 0; reg _ucoverclk29; initial _ucoverclk29 = 0;reg _ucoverclk3; initial _ucoverclk3 = 0;reg _ucoverclk30; initial _ucoverclk30 = 0;reg _ucoverclk4; initial _ucoverclk4 = 0;reg _ucoverclk5; initial _ucoverclk5 = 0;reg _ucoverclk6; initial _ucoverclk6 = 0;reg _ucoverclk7; initial _ucoverclk7 = 0;reg _ucoverclk8; initial _ucoverclk8 = 0;reg _ucoverclk9; initial _ucoverclk9 = 0;reg _umessageclk2; initial _umessageclk2 = 0; `line 7 "verilog/example.v" 0 pli pli (); // Put on highest level of your design integer i; `define ten 10 reg \escaped[10] ; initial begin /*VCS coverage off*/ /*vpassert*/begin /*verilator coverage_block_off*/begin $callInfo ("Welcome to a VPASSERTed file\n"); end end /*vpassert*/ /*VCS coverage on*/ `line 18 "verilog/example.v" 0 // /*VCS coverage off*/ /*vpassert*/begin /*verilator coverage_block_off*/if ((__message >= (1))) begin $callInfo ("Printed only at debug level %0d\n", 1); end end /*vpassert*/ /*VCS coverage on*/ `line 20 "verilog/example.v" 0 /*VCS coverage off*/ /*vpassert*/begin /*verilator coverage_block_off*/if ((__message >= (9))) begin $callInfo ("Printed only at debug level %0d\n", 9); end end /*vpassert*/ /*VCS coverage on*/ `line 21 "verilog/example.v" 0 // \escaped[10] = 1'b1; /*VCS coverage off*/ /*vpassert*/begin /*verilator coverage_block_off*/if (!(\escaped[10] ) && (`__message_on)) begin $callError ("Escaped not 1\n%%E: In %m\n"); end end /*vpassert*/ /*VCS coverage on*/ `line 24 "verilog/example.v" 0 /*VCS coverage off*/ /*vpassert*/begin /*verilator coverage_block_off*/if (!(\escaped[10] ) && (`__message_on)) begin $callInfo ("Escaped not 1\n"); end end /*vpassert*/ /*VCS coverage on*/ `line 25 "verilog/example.v" 0 // i=0; /*VCS coverage off*/ /*vpassert*/begin /*verilator coverage_block_off*/if (!(1==1) && (`__message_on)) begin $callError ("Why doesn't 1==1??\n%%E: In %m\n"); end end /*vpassert*/ /*VCS coverage on*/ `line 28 "verilog/example.v" 0 /*VCS coverage off*/ /*vpassert*/begin /*verilator coverage_block_off*/if (!(10==`ten) && (`__message_on)) begin $callError ("Why doesn't 10==10??\n%%E: In %m\n"); end end /*vpassert*/ /*VCS coverage on*/ `line 36 "verilog/example.v" 0 /*VCS coverage off*/ /*vpassert*/begin /*verilator coverage_block_off*/if (!(1==1) && (`__message_on)) begin $callError ("Why doesn't 1==1??\n%%E: In %m\n"); end end /*vpassert*/ /*VCS coverage on*/ `line 36 "verilog/example.v" 0 // i=3'b100; if ((({i [2:0]}) & (({i [2:0]}) - 3'b1)) !== 3'b0 && `__message_on) /*VCS coverage off*/ /*vpassert*/begin /*verilator coverage_block_off*/if (`__message_on) begin $callError ("MULTIPLE ACTIVE %b --> amone ok\n\n%%E: In %m\n", ({i [2:0]})); end end /*vpassert*/ /*VCS coverage on*/ `line 38 "verilog/example.v" 0 i=3'b010; if ((({i[2:0]}) & (({i[2:0]}) - 3'b1)) !== 3'b0 && `__message_on) /*VCS coverage off*/ /*vpassert*/begin /*verilator coverage_block_off*/if (`__message_on) begin $callError ("MULTIPLE ACTIVE %b --> amone ok\n\n%%E: In %m\n", ({i[2:0]})); end end /*vpassert*/ /*VCS coverage on*/ `line 39 "verilog/example.v" 0 i=3'b001; if ((({i[2:0]}) & (({i[2:0]}) - 3'b1)) !== 3'b0 && `__message_on) /*VCS coverage off*/ /*vpassert*/begin /*verilator coverage_block_off*/if (`__message_on) begin $callError ("MULTIPLE ACTIVE %b --> amone ok\n\n%%E: In %m\n", ({i[2:0]})); end end /*vpassert*/ /*VCS coverage on*/ `line 40 "verilog/example.v" 0 i=3'b000; if ((({i[2:0]}) & (({i[2:0]}) - 3'b1)) !== 3'b0 && `__message_on) /*VCS coverage off*/ /*vpassert*/begin /*verilator coverage_block_off*/if (`__message_on) begin $callError ("MULTIPLE ACTIVE %b --> amone ok\n\n%%E: In %m\n", ({i[2:0]})); end end /*vpassert*/ /*VCS coverage on*/ `line 41 "verilog/example.v" 0 //i=3'b011; $uassert_amone(i[2:0], "amone error expected\n"); //i=3'b110; $uassert_amone(i[2:0], "amone error expected\n"); // i=2'b10; if ((({i[1:0]}) & (({i[1:0]}) - 2'b1)) !== 2'b0 && `__message_on) /*VCS coverage off*/ /*vpassert*/begin /*verilator coverage_block_off*/if (`__message_on) begin $callError ("MULTIPLE ACTIVE %b --> onehot ok\n\n%%E: In %m\n", ({i[1:0]})); end end /*vpassert*/ /*VCS coverage on*/ `line 45 "verilog/example.v" 0 if (({i[1:0]}) === 2'b0 && `__message_on) /*VCS coverage off*/ /*vpassert*/begin /*verilator coverage_block_off*/if (`__message_on) begin $callError ("NONE ACTIVE %b --> onehot ok\n\n%%E: In %m\n", ({i[1:0]})); end end /*vpassert*/ /*VCS coverage on*/ `line 45 "verilog/example.v" 0 i=2'b01; if ((({i[1:0]}) & (({i[1:0]}) - 2'b1)) !== 2'b0 && `__message_on) /*VCS coverage off*/ /*vpassert*/begin /*verilator coverage_block_off*/if (`__message_on) begin $callError ("MULTIPLE ACTIVE %b --> onehot ok\n\n%%E: In %m\n", ({i[1:0]})); end end /*vpassert*/ /*VCS coverage on*/ `line 46 "verilog/example.v" 0 if (({i[1:0]}) === 2'b0 && `__message_on) /*VCS coverage off*/ /*vpassert*/begin /*verilator coverage_block_off*/if (`__message_on) begin $callError ("NONE ACTIVE %b --> onehot ok\n\n%%E: In %m\n", ({i[1:0]})); end end /*vpassert*/ /*VCS coverage on*/ `line 46 "verilog/example.v" 0 i=2'b10; if ((({i[1],i[0]}) & (({i[1],i[0]}) - 2'b1)) !== 2'b0 && `__message_on) /*VCS coverage off*/ /*vpassert*/begin /*verilator coverage_block_off*/if (`__message_on) begin $callError ("MULTIPLE ACTIVE %b --> onehot ok\n\n%%E: In %m\n", ({i[1],i[0]})); end end /*vpassert*/ /*VCS coverage on*/ `line 47 "verilog/example.v" 0 if (({i[1],i[0]}) === 2'b0 && `__message_on) /*VCS coverage off*/ /*vpassert*/begin /*verilator coverage_block_off*/if (`__message_on) begin $callError ("NONE ACTIVE %b --> onehot ok\n\n%%E: In %m\n", ({i[1],i[0]})); end end /*vpassert*/ /*VCS coverage on*/ `line 47 "verilog/example.v" 0 i=2'b10; if ((({{i[1],i[0]}}) & (({{i[1],i[0]}}) - 2'b1)) !== 2'b0 && `__message_on) /*VCS coverage off*/ /*vpassert*/begin /*verilator coverage_block_off*/if (`__message_on) begin $callError ("MULTIPLE ACTIVE %b --> onehot ok\n\n%%E: In %m\n", ({{i[1],i[0]}})); end end /*vpassert*/ /*VCS coverage on*/ `line 48 "verilog/example.v" 0 if (({{i[1],i[0]}}) === 2'b0 && `__message_on) /*VCS coverage off*/ /*vpassert*/begin /*verilator coverage_block_off*/if (`__message_on) begin $callError ("NONE ACTIVE %b --> onehot ok\n\n%%E: In %m\n", ({{i[1],i[0]}})); end end /*vpassert*/ /*VCS coverage on*/ `line 48 "verilog/example.v" 0 //i=2'b11; $uassert_onehot(i[2:0], "onehot error expected\n"); //i=2'b00; $uassert_onehot(i[2:0], "onehot error expected\n"); end // Test assertions within case statements initial begin i=3'b100; casez (i) 3'b100: ; 3'b000: $stop; 3'b010: /*VCS coverage off*/ /*vpassert*/begin /*verilator coverage_block_off*/if (`__message_on) begin $callError ("Why?\n%%E: In %m\n"); end end /*vpassert*/ /*VCS coverage on*/ `line 59 "verilog/example.v" 0 default: $stop; endcase if ($time > 1000) $stop; end // Example of request/grant handshake reg clk; reg bus_req; // Request a transaction, single cycle pulse reg bus_ack; // Acknowledged transaction, single cycle pulse reg [31:0] bus_data; initial begin // Reset signals bus_req = 1'b0; bus_ack = 1'b0; bus_data = 1'b0; // Assert a request @ (posedge clk) ; bus_req = 1'b1; bus_data = 32'hfeed; // Wait for ack @ (posedge clk) ; bus_req = 1'b0; // Send ack @ (posedge clk) ; bus_ack = 1'b1; // Next request could be here @ (posedge clk) ; bus_ack = 1'b0; end always @ (posedge clk) begin `line 93 "verilog/example.v" 0 /*VCS coverage off*/ /*vpassert*/begin /*verilator coverage_block_off*/ `line 93 "verilog/example.v" 0 if (`__message_on) begin casez({(_assertreqack1_busy_r),(bus_req),(bus_ack)}) 3'b000: ; 3'b010: _assertreqack1_busy_r<=1'b1; 3'b011: begin if (`__message_on) begin $callError ("Unexpected bus_req coincident with bus_ack\n%%E: In %m\n"); end end 3'b001: begin if (`__message_on) begin $callError ("Unexpected bus_ack with no request pending\n%%E: In %m\n"); end end 3'b100: ; 3'b11?: begin if (`__message_on) begin $callError ("Unexpected bus_req with request already pending\n%%E: In %m\n"); end end 3'b101: _assertreqack1_busy_r<=1'b0;endcase if ((bus_req)||(_assertreqack1_busy_r)) begin if ((_assertreqack1_busy_r)) begin if (_assertreqack1_data0_r != ^(bus_data)) begin if (`__message_on) begin $callError ("Unexpected transition of bus_data during transaction\n%%E: In %m\n"); end end end _assertreqack1_data0_r <= ^(bus_data); end end end /*vpassert*/ /*VCS coverage on*/ `line 93 "verilog/example.v" 0 end // Overall control loop initial clk = 1'b0; initial forever begin #1; i = i + 1; clk = !clk; if (i==20) /*VCS coverage off*/ /*vpassert*/begin /*verilator coverage_block_off*/if (`__message_on) begin $callWarn ("Don't know what to do next!\n%%W: In %m\n"); end end /*vpassert*/ /*VCS coverage on*/ `line 102 "verilog/example.v" 0 if (i==22) /*VCS coverage off*/ /*vpassert*/begin /*verilator coverage_block_off*/if (`__message_on) begin $callError ("Guess I'll error out!\n%%E: In %m\n"); end end /*vpassert*/ /*VCS coverage on*/ `line 103 "verilog/example.v" 0 end // Moved clock asserts always @* begin/*vpassert*/ _ucoverclk30=1'b0; /*vpassert*//*vpassert*/ _ucoverclk29=1'b0; /*vpassert*//*vpassert*/ _ucoverclk28=1'b0; /*vpassert*//*vpassert*/ _ucoverclk27=1'b0; /*vpassert*//*vpassert*/ _ucoverclk26=1'b0; /*vpassert*//*vpassert*/ _ucoverclk25=1'b0; /*vpassert*//*vpassert*/ _ucoverclk24=1'b0; /*vpassert*//*vpassert*/ _ucoverclk23=1'b0; /*vpassert*//*vpassert*/ _ucoverclk22=1'b0; /*vpassert*//*vpassert*/ _ucoverclk21=1'b0; /*vpassert*//*vpassert*/ _ucoverclk20=1'b0; /*vpassert*//*vpassert*/ _ucoverclk19=1'b0; /*vpassert*//*vpassert*/ _ucoverclk18=1'b0; /*vpassert*//*vpassert*/ _ucoverclk17=1'b0; /*vpassert*//*vpassert*/ _ucoverclk16=1'b0; /*vpassert*//*vpassert*/ _ucoverclk15=1'b0; /*vpassert*//*vpassert*/ _ucoverclk14=1'b0; /*vpassert*//*vpassert*/ _ucoverclk13=1'b0; /*vpassert*//*vpassert*/ _ucoverclk12=1'b0; /*vpassert*//*vpassert*/ _ucoverclk11=1'b0; /*vpassert*//*vpassert*/ _ucoverclk10=1'b0; /*vpassert*//*vpassert*/ _ucoverclk9=1'b0; /*vpassert*//*vpassert*/ _ucoverclk8=1'b0; /*vpassert*//*vpassert*/ _ucoverclk7=1'b0; /*vpassert*//*vpassert*/ _ucoverclk6=1'b0; /*vpassert*//*vpassert*/ _ucoverclk5=1'b0; /*vpassert*//*vpassert*/ _ucoverclk4=1'b0; /*vpassert*//*vpassert*/ _ucoverclk3=1'b0; /*vpassert*//*vpassert*/ _umessageclk2=1'b0; /*vpassert*/ if (i==19) /*vpassert*/_umessageclk2=1'b1;/*vpassert*/ if (i==18) /*vpassert*/_ucoverclk3=1'b1;/*vpassert*/ /*vpassert*/_ucoverclk4=( (i[(27)]));/*vpassert*//*vpassert*/_ucoverclk5=( (i[(26)]));/*vpassert*//*vpassert*/_ucoverclk6=( (i[(25)]));/*vpassert*//*vpassert*/_ucoverclk7=( (i[(24)]));/*vpassert*//*vpassert*/_ucoverclk8=( (i[(23)]));/*vpassert*//*vpassert*/_ucoverclk9=( (i[(22)]));/*vpassert*//*vpassert*/_ucoverclk10=( (i[(21)]));/*vpassert*//*vpassert*/_ucoverclk11=( (i[(20)]));/*vpassert*//*vpassert*/_ucoverclk12=( (i[(19)]));/*vpassert*//*vpassert*/_ucoverclk13=( (i[(18)]));/*vpassert*//*vpassert*/_ucoverclk14=( (i[(17)]));/*vpassert*//*vpassert*/_ucoverclk15=( (i[(16)]));/*vpassert*//*vpassert*/_ucoverclk16=( (i[(15)]));/*vpassert*//*vpassert*/_ucoverclk17=( (i[(14)]));/*vpassert*//*vpassert*/_ucoverclk18=( (i[(13)]));/*vpassert*//*vpassert*/_ucoverclk19=( (i[(12)]));/*vpassert*//*vpassert*/_ucoverclk20=( (i[(11)]));/*vpassert*//*vpassert*/_ucoverclk21=( (i[(10)]));/*vpassert*//*vpassert*/_ucoverclk22=( (i[(9)]));/*vpassert*//*vpassert*/_ucoverclk23=( (i[(8)]));/*vpassert*//*vpassert*/_ucoverclk24=( (i[(7)]));/*vpassert*//*vpassert*/_ucoverclk25=( (i[(6)]));/*vpassert*//*vpassert*/_ucoverclk26=( (i[(5)]));/*vpassert*//*vpassert*/_ucoverclk27=( (i[(4)]));/*vpassert*//*vpassert*/_ucoverclk28=( (i[(3)]));/*vpassert*//*vpassert*/_ucoverclk29=( (i[(1)]));/*vpassert*//*vpassert*/_ucoverclk30=( (i[(0)]));/*vpassert*/ end // Meta coverage disables initial begin // vp_coverage_off `line 114 "verilog/example.v" 0 /*VCS coverage off*/ /*verilator coverage_off*/ /*vpassert*/ `line 115 "verilog/example.v" 0 if (0) begin end // cover off'ed // vp_coverage_on `line 116 "verilog/example.v" 0 /*vpassert*/ /*verilator coverage_on*/ /*VCS coverage on*/ `line 117 "verilog/example.v" 0 end // Ifdef based disables initial begin `ifndef NEVER `ifdef SYNTHESIS if (1) begin end // cover on `elsif SYNTHESIS if (1) begin end // cover on `else if (1) begin end // cover off'ed `endif `ifndef SYNTHESIS if (1) begin end // cover off'ed `else if (1) begin end // cover on `endif `endif end `line 135 "verilog/example.v" 0 always @ (posedge clk) if (_umessageclk2) /*VCS coverage off*/ /*vpassert*/begin /*verilator coverage_block_off*/if (`__message_on) begin $callWarn ("Called at next edge (1 of 2)\n%%W: In %m\n"); end end /*vpassert*/ /*VCS coverage on*/ `line 109 "verilog/example.v" 0 example_cover_label: cover property (@(posedge clk) (_ucoverclk3)); foreach_label__27: cover property (@(posedge clk) (_ucoverclk4)); `line 110 "verilog/example.v" 0 foreach_label__26: cover property (@(posedge clk) (_ucoverclk5)); `line 110 "verilog/example.v" 0 foreach_label__25: cover property (@(posedge clk) (_ucoverclk6)); `line 110 "verilog/example.v" 0 foreach_label__24: cover property (@(posedge clk) (_ucoverclk7)); `line 110 "verilog/example.v" 0 foreach_label__23: cover property (@(posedge clk) (_ucoverclk8)); `line 110 "verilog/example.v" 0 foreach_label__22: cover property (@(posedge clk) (_ucoverclk9)); `line 110 "verilog/example.v" 0 foreach_label__21: cover property (@(posedge clk) (_ucoverclk10)); `line 110 "verilog/example.v" 0 foreach_label__20: cover property (@(posedge clk) (_ucoverclk11)); `line 110 "verilog/example.v" 0 foreach_label__19: cover property (@(posedge clk) (_ucoverclk12)); `line 110 "verilog/example.v" 0 foreach_label__18: cover property (@(posedge clk) (_ucoverclk13)); `line 110 "verilog/example.v" 0 foreach_label__17: cover property (@(posedge clk) (_ucoverclk14)); `line 110 "verilog/example.v" 0 foreach_label__16: cover property (@(posedge clk) (_ucoverclk15)); `line 110 "verilog/example.v" 0 foreach_label__15: cover property (@(posedge clk) (_ucoverclk16)); `line 110 "verilog/example.v" 0 foreach_label__14: cover property (@(posedge clk) (_ucoverclk17)); `line 110 "verilog/example.v" 0 foreach_label__13: cover property (@(posedge clk) (_ucoverclk18)); `line 110 "verilog/example.v" 0 foreach_label__12: cover property (@(posedge clk) (_ucoverclk19)); `line 110 "verilog/example.v" 0 foreach_label__11: cover property (@(posedge clk) (_ucoverclk20)); `line 110 "verilog/example.v" 0 foreach_label__10: cover property (@(posedge clk) (_ucoverclk21)); `line 110 "verilog/example.v" 0 foreach_label__9: cover property (@(posedge clk) (_ucoverclk22)); `line 110 "verilog/example.v" 0 foreach_label__8: cover property (@(posedge clk) (_ucoverclk23)); `line 110 "verilog/example.v" 0 foreach_label__7: cover property (@(posedge clk) (_ucoverclk24)); `line 110 "verilog/example.v" 0 foreach_label__6: cover property (@(posedge clk) (_ucoverclk25)); `line 110 "verilog/example.v" 0 foreach_label__5: cover property (@(posedge clk) (_ucoverclk26)); `line 110 "verilog/example.v" 0 foreach_label__4: cover property (@(posedge clk) (_ucoverclk27)); `line 110 "verilog/example.v" 0 foreach_label__3: cover property (@(posedge clk) (_ucoverclk28)); `line 110 "verilog/example.v" 0 foreach_label__1: cover property (@(posedge clk) (_ucoverclk29)); `line 110 "verilog/example.v" 0 foreach_label__0: cover property (@(posedge clk) (_ucoverclk30)); `line 136 "verilog/example.v" 0 endmodule `line 139 "verilog/example.v" 0 Verilog-Perl-3.482/t/42_dumpcheck_1v.out0000644000177100017500000000422713422450702017672 0ustar wsnyderwsnyderroot_module $root ( ); localparam GLOBAL_PARAM = 1; // Local Variables: // eval:(verilog-read-defines) // End: endroot_module module v_bug917 ( a, b, m); input a; // a-First output b; // b-Third // Third output m; // m-Second endmodule module v_bug917p ( a, b); input a; // a-First output b; // b-Secondparen // Third endmodule module v_comments ( a, b, c, d, d1, d2, d3); input a; // comment for a inout [10:0] b; output [0:10] c; // comment for c output reg d; output [32:0] d1; output [(MATH-1):0] d2; output [32-1:0] d3; var reg [11:0] e; // Comment for e endmodule module v_hier_noport ( ); parameter P; var reg internal; endmodule module v_hier_sub ( avec, clk, qvec); parameter FROM_DEFPARAM = 1; genvar K; genvar K_UNUSED; supply1 a1; // Outputs input [3:0] avec; // Comment for v_hier_sub, avec input clk; output [3:0] qvec; /* Comment for v_hier_sub, qvec */ v_hier_subsub #(.IGNORED('sh20)) subsub0 (.a(a1), .q(qvec[0])); v_hier_subsub subsub2 (.a(1'b0), .q(qvec[2])); endmodule module v_hier_subsub ( a, q); parameter IGNORED = 0; input signed a; output q; // Test protected //" endmodule module v_hier_top ( clk); localparam [0:0] WC_p1 = 0; localparam [2:0] WC_p3 = 0; localparam WC_p32 = 0; localparam [-1:2] WC_p4 = 0; localparam integer WC_pint = 0; // Assignments wire WC_w1; wire [0:0] WC_w1b; wire [2:0] WC_w3; wire [-1:2] WC_w4; wire asn_clk; input clk; /* pragma jsc_clk */ missing missing (); v_recursive #(.DEPTH(3)) recursive (); v_hier_sub sub (.avec({avec[3],avec[2:0]}), .clk(1'b0), .qvec(qvec[3:0])); defparam sub.FROM_DEFPARAM = 2; assign asn_clk = clk; endmodule module v_hier_top2 ( clk, iosig); input clk; inout [2:0] iosig; /* synthesis useioff = 1 //*synthesis fpga_attr = "BLAH=ON"//* synthesis fpga_pin = "A22"*/ /* synthesis aftersemi*/ // NetListName=F12_IO v_hier_noport noport (); v_hier_noport #(.P(1)) noporta [1:0] (); v_hier_noport #(.P(1)) noportp (); endmodule module v_recursive ( ); parameter DEPTH = 1; v_recursive #(.DEPTH(DEPTH-1)) recurse (); endmodule Verilog-Perl-3.482/t/58_vsplitmodule.t0000755000177100017500000000131314553624300017512 0ustar wsnyderwsnyder#!/usr/bin/perl -w # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package # # Copyright 2000-2024 by Wilson Snyder. This program is free software; # you can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. use strict; use Test::More; BEGIN { plan tests => 2 } BEGIN { require "./t/test_utils.pl"; } $ENV{HARNESS_ACTIVE} = 1; # vsplitmodule checks this and doesn't die print "Checking vsplitmodule...\n"; { # -List my $out = "test_dir/a.v"; unlink $out; run_system ("${PERL} ./vsplitmodule"); ok(1, "vsplitmodule"); ok(-r $out, "vsplitmodule output"); unlink $out; } Verilog-Perl-3.482/t/85_vhier_forest.out0000644000177100017500000000020313741600317020020 0ustar wsnyderwsnyder v_hier_top v_hier_top |--recursive v_recursive \--sub v_hier_sub |--subsub0 v_hier_subsub \--subsub2 v_hier_subsub Verilog-Perl-3.482/t/80_vppreproc_defines.out0000644000177100017500000000063213741600370021036 0ustar wsnyderwsnyder`define SV_COV_ASSERTION 20 `define SV_COV_CHECK 3 `define SV_COV_ERROR -1 `define SV_COV_FSM_STATE 21 `define SV_COV_HIER 11 `define SV_COV_MODULE 10 `define SV_COV_NOCOV 0 `define SV_COV_OK 1 `define SV_COV_OVERFLOW -2 `define SV_COV_PARTIAL 2 `define SV_COV_RESET 2 `define SV_COV_START 0 `define SV_COV_STATEMENT 22 `define SV_COV_STOP 1 `define SV_COV_TOGGLE 23 `define _EMPTY `define _EXAMPLE_INC2_V_ 1 Verilog-Perl-3.482/t/10_keywords.t0000755000177100017500000000365014553624300016624 0ustar wsnyderwsnyder#!/usr/bin/perl -w # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package # # Copyright 2000-2024 by Wilson Snyder. This program is free software; # you can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. use strict; use Test::More; BEGIN { plan tests => 27 } BEGIN { require "./t/test_utils.pl"; } use Verilog::Language; ok(1); ok (Verilog::Language::is_keyword("input")); ok (!Verilog::Language::is_keyword("not_input")); ok (Verilog::Language::is_compdirect("`define")); is (Verilog::Language::language_standard(), '1800-2023'); is (Verilog::Language::language_standard('1800-2023'), '1800-2023'); is (Verilog::Language::language_standard('1800-2017'), '1800-2017'); is (Verilog::Language::language_standard('1800-2012'), '1800-2012'); is (Verilog::Language::language_standard('1800-2009'), '1800-2009'); ok (Verilog::Language::is_keyword("checker")); is (Verilog::Language::language_standard('1800-2005'), '1800-2005'); ok (!Verilog::Language::is_keyword("checker")); ok (Verilog::Language::is_keyword("do")); is (Verilog::Language::language_standard('1364-2005'), '1364-2005'); ok (Verilog::Language::is_keyword("uwire")); is (Verilog::Language::language_standard(2001), '1364-2001'); ok (!Verilog::Language::is_keyword("uwire")); ok (Verilog::Language::is_keyword("generate")); is (Verilog::Language::language_standard(1995), '1364-1995'); ok (!Verilog::Language::is_keyword("generate")); is (Verilog::Language::language_maximum(), '1800-2023', 'language_maximum'); is (Verilog::Language::strip_comments("he/**/l/**/lo"), "hello"); is (Verilog::Language::strip_comments("he//xx/*\nllo"), "he\nllo"); is (Verilog::Language::strip_comments("he/*xx//..*/llo"), "hello"); is (Verilog::Language::strip_comments("he\"//llo\""), "he\"//llo\""); ok ( Verilog::Language::is_gateprim("buf")); ok (!Verilog::Language::is_gateprim("else")); Verilog-Perl-3.482/t/34_parser.t0000755000177100017500000000515014553624300016254 0ustar wsnyderwsnyder#!/usr/bin/perl -w # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package # # Copyright 2000-2024 by Wilson Snyder. This program is free software; # you can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. use strict; use Test::More; use Data::Dumper; $Data::Dumper::Indent = 1; #Debug BEGIN { plan tests => 7 } BEGIN { require "./t/test_utils.pl"; } our %_TestCoverage; ###################################################################### package MyParser; use Verilog::Parser; use strict; use base qw(Verilog::Parser); BEGIN { # Make functions like this: # sub attribute { $_[0]->_common('attribute', @_); } foreach my $cb (Verilog::Parser::callback_names()) { my $func = ' sub __CB__ { $_[0]->_common("__CB__", @_); } '; $func =~ s/__CB__/$cb/g; eval($func); } } sub _common { my $self = shift; my $what = shift; my $call_self = shift; my @args = @_; my $urb = $self->unreadback; $_TestCoverage{$what}++; my $args=""; foreach (@args) { $args .= defined $_ ? " '$_'" : " undef"; } if ($urb && $urb ne '') { $self->{dump_fh}->printf("%s:%03d: unreadback '%s'\n", $self->filename, $self->lineno, $urb); $self->unreadback(''); } $self->{dump_fh}->printf("%s:%03d: %s%s\n", $self->filename, $self->lineno, uc $what, $args); } ###################################################################### package main; use Verilog::Parser; use Verilog::Preproc; ok(1, "use"); # Use our class and dump to a file my $dump_fh = new IO::File(">test_dir/34.dmp") or die "%Error: $! test_dir/34.dmp,"; my $p = new Verilog::Parser; ok($p, "new"); $p->selftest(); ok(1, "selftest"); $p->lineno(100); $p->filename("XXX"); is($p->lineno, 100); read_test("verilog/v_hier_subprim.v", $dump_fh); read_test("verilog/v_hier_sub.v", $dump_fh); read_test("verilog/example.v", $dump_fh); ok(1); $dump_fh->close(); # Did we read the right stuff? ok(files_identical("test_dir/34.dmp", "t/34_parser.out"), "diff"); # Did we cover everything? my $err; foreach my $cb (Verilog::Parser::callback_names()) { if (!$_TestCoverage{$cb}) { $err=1; warn "%Warning: No test coverage for callback: $cb\n"; } } ok (!$err, "coverage"); ###################################################################### sub read_test { my $filename = shift; my $dump_fh = shift; my $pp = Verilog::Preproc->new(keep_comments=>0,); my $parser = new MyParser (dump_fh => $dump_fh); # Preprocess $pp->open($filename); $parser->parse_preproc_file($pp); } Verilog-Perl-3.482/t/85_vhier_resolvefiles.out0000644000177100017500000000002513234726611021225 0ustar wsnyderwsnyderverilog/v_hier_top.v Verilog-Perl-3.482/t/12_splitbus.t0000755000177100017500000000214114553624300016616 0ustar wsnyderwsnyder#!/usr/bin/perl -w # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package # # Copyright 2000-2024 by Wilson Snyder. This program is free software; # you can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. use strict; use Test::More; BEGIN { plan tests => 5 } BEGIN { require "./t/test_utils.pl"; } use Verilog::Language; ok(1, "use"); array_ck (['none', ], Verilog::Language::split_bus ("none")); array_ck (['ff[1]', 'ff[2]', ], Verilog::Language::split_bus ("ff[1:2]")); array_ck (['ff[5]e', 'ff[3]e', 'ff[1]e', 'ff[4]e', ], Verilog::Language::split_bus ("ff[5:1:2,4]e")); array_ck (['ff[3] bar [10] end', 'ff[2] bar [9] end', 'ff[1] bar [8] end', 'ff[3] bar [7] end', 'ff[2] bar [6] end', 'ff[1] bar [5] end', 'ff[3] bar [4] end', 'ff[2] bar [3] end', ], Verilog::Language::split_bus ("ff[3:1] bar [4'ha:3] end")); sub array_ck { my $checkref = shift; my @got = @_; is_deeply(\@got, $checkref); } Verilog-Perl-3.482/t/85_vhier_inpfiles.out0000644000177100017500000000017014030463163020330 0ustar wsnyderwsnyder verilog/v_hier_inc.vh verilog/v_hier_sub.v verilog/v_hier_subsub.v verilog/v_hier_top.v verilog/v_recursive.v Verilog-Perl-3.482/t/05_yaml.t0000755000177100017500000000120514553624300015715 0ustar wsnyderwsnyder#!/usr/bin/perl -w # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package # # Copyright 2010-2024 by Wilson Snyder. This program is free software; # you can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. use strict; use Test; use warnings; if (!$ENV{VERILATOR_AUTHOR_SITE}) { plan tests => 1; skip("author only test (harmless)",1); } else { eval "use Test::YAML::Meta;"; if ($@) { plan tests => 1; skip("Test::YAML::Meta not installed so ignoring check (harmless)",1); } else { meta_yaml_ok(); } } Verilog-Perl-3.482/t/34_parser.out0000644000177100017500000011363013234726611016623 0ustar wsnyderwsnyderverilog/v_hier_subprim.v:001: PREPROC '`line 1 "verilog/v_hier_subprim.v" 1 ' verilog/v_hier_subprim.v:008: unreadback ' ' verilog/v_hier_subprim.v:008: KEYWORD 'primitive' verilog/v_hier_subprim.v:008: unreadback ' ' verilog/v_hier_subprim.v:008: SYMBOL 'v_hier_prim' verilog/v_hier_subprim.v:008: unreadback ' ' verilog/v_hier_subprim.v:008: OPERATOR '(' verilog/v_hier_subprim.v:010: unreadback ' ' verilog/v_hier_subprim.v:010: SYMBOL 'q' verilog/v_hier_subprim.v:010: OPERATOR ',' verilog/v_hier_subprim.v:012: unreadback ' ' verilog/v_hier_subprim.v:012: SYMBOL 'a' verilog/v_hier_subprim.v:013: unreadback ' ' verilog/v_hier_subprim.v:013: OPERATOR ')' verilog/v_hier_subprim.v:013: OPERATOR ';' verilog/v_hier_subprim.v:014: unreadback ' ' verilog/v_hier_subprim.v:014: KEYWORD 'output' verilog/v_hier_subprim.v:014: unreadback ' ' verilog/v_hier_subprim.v:014: SYMBOL 'q' verilog/v_hier_subprim.v:014: OPERATOR ';' verilog/v_hier_subprim.v:015: unreadback ' ' verilog/v_hier_subprim.v:015: KEYWORD 'input' verilog/v_hier_subprim.v:015: unreadback ' ' verilog/v_hier_subprim.v:015: SYMBOL 'a' verilog/v_hier_subprim.v:015: OPERATOR ';' verilog/v_hier_subprim.v:017: unreadback ' ' verilog/v_hier_subprim.v:017: KEYWORD 'table' verilog/v_hier_subprim.v:018: unreadback ' ' verilog/v_hier_subprim.v:018: NUMBER '0' verilog/v_hier_subprim.v:018: unreadback ' ' verilog/v_hier_subprim.v:018: OPERATOR ':' verilog/v_hier_subprim.v:018: unreadback ' ' verilog/v_hier_subprim.v:018: NUMBER '1' verilog/v_hier_subprim.v:018: OPERATOR ';' verilog/v_hier_subprim.v:019: unreadback ' ' verilog/v_hier_subprim.v:019: NUMBER '1' verilog/v_hier_subprim.v:019: unreadback ' ' verilog/v_hier_subprim.v:019: OPERATOR ':' verilog/v_hier_subprim.v:019: unreadback ' ' verilog/v_hier_subprim.v:019: NUMBER '0' verilog/v_hier_subprim.v:019: OPERATOR ';' verilog/v_hier_subprim.v:020: unreadback ' ' verilog/v_hier_subprim.v:020: KEYWORD 'endtable' verilog/v_hier_subprim.v:022: unreadback ' ' verilog/v_hier_subprim.v:022: KEYWORD 'endprimitive' verilog/v_hier_subprim.v:024: unreadback ' ' verilog/v_hier_subprim.v:024: PREPROC '`celldefine' verilog/v_hier_subprim.v:025: unreadback ' ' verilog/v_hier_subprim.v:025: KEYWORD 'module' verilog/v_hier_subprim.v:025: unreadback ' ' verilog/v_hier_subprim.v:025: SYMBOL 'bug27070' verilog/v_hier_subprim.v:025: OPERATOR '(' verilog/v_hier_subprim.v:025: OPERATOR ')' verilog/v_hier_subprim.v:025: OPERATOR ';' verilog/v_hier_subprim.v:027: unreadback ' ' verilog/v_hier_subprim.v:027: KEYWORD 'parameter' verilog/v_hier_subprim.v:027: unreadback ' ' verilog/v_hier_subprim.v:027: SYMBOL 'TAP' verilog/v_hier_subprim.v:027: unreadback ' ' verilog/v_hier_subprim.v:027: OPERATOR '=' verilog/v_hier_subprim.v:027: unreadback ' ' verilog/v_hier_subprim.v:027: NUMBER '4'b1001' verilog/v_hier_subprim.v:027: OPERATOR ';' verilog/v_hier_subprim.v:028: unreadback ' ' verilog/v_hier_subprim.v:028: KEYWORD 'endmodule' verilog/v_hier_subprim.v:029: unreadback ' ' verilog/v_hier_subprim.v:029: PREPROC '`endcelldefine' verilog/v_hier_subprim.v:031: unreadback ' ' verilog/v_hier_subprim.v:031: PREPROC '`celldefine' verilog/v_hier_subprim.v:032: unreadback ' ' verilog/v_hier_subprim.v:032: KEYWORD 'module' verilog/v_hier_subprim.v:032: unreadback ' ' verilog/v_hier_subprim.v:032: SYMBOL 'bug893' verilog/v_hier_subprim.v:032: OPERATOR '(' verilog/v_hier_subprim.v:032: OPERATOR ')' verilog/v_hier_subprim.v:032: OPERATOR ';' verilog/v_hier_subprim.v:033: unreadback ' ' verilog/v_hier_subprim.v:033: KEYWORD 'reg' verilog/v_hier_subprim.v:033: unreadback ' ' verilog/v_hier_subprim.v:033: SYMBOL 'r' verilog/v_hier_subprim.v:033: OPERATOR ';' verilog/v_hier_subprim.v:034: unreadback ' ' verilog/v_hier_subprim.v:034: KEYWORD 'initial' verilog/v_hier_subprim.v:034: unreadback ' ' verilog/v_hier_subprim.v:034: SYMBOL 'r' verilog/v_hier_subprim.v:034: unreadback ' ' verilog/v_hier_subprim.v:034: OPERATOR '<=' verilog/v_hier_subprim.v:034: OPERATOR '#' verilog/v_hier_subprim.v:034: NUMBER '1' verilog/v_hier_subprim.v:034: unreadback ' ' verilog/v_hier_subprim.v:034: NUMBER ''0' verilog/v_hier_subprim.v:034: OPERATOR ';' verilog/v_hier_subprim.v:035: unreadback ' ' verilog/v_hier_subprim.v:035: KEYWORD 'endmodule' verilog/v_hier_subprim.v:036: unreadback ' ' verilog/v_hier_subprim.v:036: PREPROC '`endcelldefine' verilog/v_hier_subprim.v:038: unreadback ' ' verilog/v_hier_subprim.v:038: PREPROC '`line 38 "verilog/v_hier_subprim.v" 2 ' verilog/v_hier_subprim.v:038: ENDPARSE '' verilog/v_hier_sub.v:001: PREPROC '`line 1 "verilog/v_hier_sub.v" 1 ' verilog/v_hier_sub.v:006: unreadback ' ' verilog/v_hier_sub.v:006: KEYWORD 'module' verilog/v_hier_sub.v:006: unreadback ' ' verilog/v_hier_sub.v:006: SYMBOL 'v_hier_sub' verilog/v_hier_sub.v:006: unreadback ' ' verilog/v_hier_sub.v:006: OPERATOR '(' verilog/v_hier_sub.v:007: unreadback ' ' verilog/v_hier_sub.v:007: KEYWORD 'input' verilog/v_hier_sub.v:007: unreadback ' ' verilog/v_hier_sub.v:007: SYMBOL 'clk' verilog/v_hier_sub.v:007: OPERATOR ',' verilog/v_hier_sub.v:008: unreadback ' ' verilog/v_hier_sub.v:008: KEYWORD 'input' verilog/v_hier_sub.v:008: unreadback ' ' verilog/v_hier_sub.v:008: OPERATOR '[' verilog/v_hier_sub.v:008: NUMBER '3' verilog/v_hier_sub.v:008: OPERATOR ':' verilog/v_hier_sub.v:008: NUMBER '0' verilog/v_hier_sub.v:008: OPERATOR ']' verilog/v_hier_sub.v:008: unreadback ' ' verilog/v_hier_sub.v:008: SYMBOL 'avec' verilog/v_hier_sub.v:008: OPERATOR ',' verilog/v_hier_sub.v:009: unreadback ' ' verilog/v_hier_sub.v:009: KEYWORD 'output' verilog/v_hier_sub.v:009: unreadback ' ' verilog/v_hier_sub.v:009: OPERATOR '[' verilog/v_hier_sub.v:009: NUMBER '3' verilog/v_hier_sub.v:009: OPERATOR ':' verilog/v_hier_sub.v:009: NUMBER '0' verilog/v_hier_sub.v:009: OPERATOR ']' verilog/v_hier_sub.v:009: unreadback ' ' verilog/v_hier_sub.v:009: SYMBOL 'qvec' verilog/v_hier_sub.v:010: unreadback ' ' verilog/v_hier_sub.v:010: OPERATOR ')' verilog/v_hier_sub.v:010: OPERATOR ';' verilog/v_hier_sub.v:012: unreadback ' ' verilog/v_hier_sub.v:012: KEYWORD 'parameter' verilog/v_hier_sub.v:012: unreadback ' ' verilog/v_hier_sub.v:012: SYMBOL 'FROM_DEFPARAM' verilog/v_hier_sub.v:012: unreadback ' ' verilog/v_hier_sub.v:012: OPERATOR '=' verilog/v_hier_sub.v:012: unreadback ' ' verilog/v_hier_sub.v:012: NUMBER '1' verilog/v_hier_sub.v:012: OPERATOR ';' verilog/v_hier_sub.v:014: unreadback ' ' verilog/v_hier_sub.v:014: KEYWORD 'supply1' verilog/v_hier_sub.v:014: unreadback ' ' verilog/v_hier_sub.v:014: SYMBOL 'a1' verilog/v_hier_sub.v:014: OPERATOR ';' verilog/v_hier_sub.v:016: unreadback ' ' verilog/v_hier_sub.v:016: SYMBOL 'v_hier_subsub' verilog/v_hier_sub.v:016: unreadback ' ' verilog/v_hier_sub.v:016: OPERATOR '#' verilog/v_hier_sub.v:016: OPERATOR '(' verilog/v_hier_sub.v:017: unreadback ' ' verilog/v_hier_sub.v:017: OPERATOR '.' verilog/v_hier_sub.v:017: SYMBOL 'IGNORED' verilog/v_hier_sub.v:017: OPERATOR '(' verilog/v_hier_sub.v:017: NUMBER ''sh20' verilog/v_hier_sub.v:017: OPERATOR ')' verilog/v_hier_sub.v:018: unreadback ' ' verilog/v_hier_sub.v:018: OPERATOR ')' verilog/v_hier_sub.v:019: unreadback ' ' verilog/v_hier_sub.v:019: SYMBOL 'subsub0' verilog/v_hier_sub.v:019: unreadback ' ' verilog/v_hier_sub.v:019: OPERATOR '(' verilog/v_hier_sub.v:021: unreadback ' ' verilog/v_hier_sub.v:021: OPERATOR '.' verilog/v_hier_sub.v:021: SYMBOL 'q' verilog/v_hier_sub.v:021: unreadback ' ' verilog/v_hier_sub.v:021: OPERATOR '(' verilog/v_hier_sub.v:021: SYMBOL 'qvec' verilog/v_hier_sub.v:021: OPERATOR '[' verilog/v_hier_sub.v:021: NUMBER '0' verilog/v_hier_sub.v:021: OPERATOR ']' verilog/v_hier_sub.v:021: OPERATOR ')' verilog/v_hier_sub.v:021: OPERATOR ',' verilog/v_hier_sub.v:023: unreadback ' ' verilog/v_hier_sub.v:023: OPERATOR '.' verilog/v_hier_sub.v:023: SYMBOL 'a' verilog/v_hier_sub.v:023: unreadback ' ' verilog/v_hier_sub.v:023: OPERATOR '(' verilog/v_hier_sub.v:023: SYMBOL 'a1' verilog/v_hier_sub.v:023: OPERATOR ')' verilog/v_hier_sub.v:023: OPERATOR ')' verilog/v_hier_sub.v:023: OPERATOR ';' verilog/v_hier_sub.v:026: unreadback ' ' verilog/v_hier_sub.v:026: KEYWORD 'generate' verilog/v_hier_sub.v:027: unreadback ' ' verilog/v_hier_sub.v:027: KEYWORD 'genvar' verilog/v_hier_sub.v:027: unreadback ' ' verilog/v_hier_sub.v:027: SYMBOL 'K' verilog/v_hier_sub.v:027: OPERATOR ',' verilog/v_hier_sub.v:027: unreadback ' ' verilog/v_hier_sub.v:027: SYMBOL 'K_UNUSED' verilog/v_hier_sub.v:027: OPERATOR ';' verilog/v_hier_sub.v:028: unreadback ' ' verilog/v_hier_sub.v:028: KEYWORD 'for' verilog/v_hier_sub.v:028: unreadback ' ' verilog/v_hier_sub.v:028: OPERATOR '(' verilog/v_hier_sub.v:028: SYMBOL 'K' verilog/v_hier_sub.v:028: OPERATOR '=' verilog/v_hier_sub.v:028: NUMBER '0' verilog/v_hier_sub.v:028: OPERATOR ';' verilog/v_hier_sub.v:028: unreadback ' ' verilog/v_hier_sub.v:028: SYMBOL 'K' verilog/v_hier_sub.v:028: OPERATOR '<' verilog/v_hier_sub.v:028: NUMBER '1' verilog/v_hier_sub.v:028: OPERATOR ';' verilog/v_hier_sub.v:028: unreadback ' ' verilog/v_hier_sub.v:028: SYMBOL 'K' verilog/v_hier_sub.v:028: OPERATOR '=' verilog/v_hier_sub.v:028: SYMBOL 'K' verilog/v_hier_sub.v:028: OPERATOR '+' verilog/v_hier_sub.v:028: NUMBER '1' verilog/v_hier_sub.v:028: OPERATOR ')' verilog/v_hier_sub.v:028: unreadback ' ' verilog/v_hier_sub.v:028: KEYWORD 'begin' verilog/v_hier_sub.v:028: unreadback ' ' verilog/v_hier_sub.v:028: OPERATOR ':' verilog/v_hier_sub.v:028: unreadback ' ' verilog/v_hier_sub.v:028: SYMBOL 'genloop' verilog/v_hier_sub.v:030: unreadback ' ' verilog/v_hier_sub.v:030: SYMBOL 'v_hier_subsub' verilog/v_hier_sub.v:030: unreadback ' ' verilog/v_hier_sub.v:030: SYMBOL 'subsub2' verilog/v_hier_sub.v:030: unreadback ' ' verilog/v_hier_sub.v:030: OPERATOR '(' verilog/v_hier_sub.v:030: SYMBOL 'qvec' verilog/v_hier_sub.v:030: OPERATOR '[' verilog/v_hier_sub.v:030: NUMBER '2' verilog/v_hier_sub.v:030: OPERATOR ']' verilog/v_hier_sub.v:030: OPERATOR ',' verilog/v_hier_sub.v:030: unreadback ' ' verilog/v_hier_sub.v:030: NUMBER '1'b0' verilog/v_hier_sub.v:030: OPERATOR ')' verilog/v_hier_sub.v:030: OPERATOR ';' verilog/v_hier_sub.v:031: unreadback ' ' verilog/v_hier_sub.v:031: KEYWORD 'end' verilog/v_hier_sub.v:032: unreadback ' ' verilog/v_hier_sub.v:032: KEYWORD 'endgenerate' verilog/v_hier_sub.v:034: unreadback ' ' verilog/v_hier_sub.v:034: KEYWORD 'function' verilog/v_hier_sub.v:034: unreadback ' ' verilog/v_hier_sub.v:034: SYMBOL 'foo' verilog/v_hier_sub.v:034: OPERATOR ';' verilog/v_hier_sub.v:035: unreadback ' ' verilog/v_hier_sub.v:035: ATTRIBUTE '(* attribute *)' verilog/v_hier_sub.v:037: unreadback ' ' verilog/v_hier_sub.v:037: KEYWORD 'input' verilog/v_hier_sub.v:037: unreadback ' ' verilog/v_hier_sub.v:037: SYMBOL 'not_part_of_pinlist' verilog/v_hier_sub.v:037: OPERATOR ';' verilog/v_hier_sub.v:038: unreadback ' ' verilog/v_hier_sub.v:038: SYMBOL 'foo' verilog/v_hier_sub.v:038: unreadback ' ' verilog/v_hier_sub.v:038: OPERATOR '=' verilog/v_hier_sub.v:038: unreadback ' ' verilog/v_hier_sub.v:038: SYMBOL 'not_part_of_pinlist' verilog/v_hier_sub.v:038: OPERATOR ';' verilog/v_hier_sub.v:039: unreadback ' ' verilog/v_hier_sub.v:039: KEYWORD 'endfunction' verilog/v_hier_sub.v:041: unreadback ' ' verilog/v_hier_sub.v:041: KEYWORD 'endmodule' verilog/v_hier_sub.v:043: unreadback ' ' verilog/v_hier_sub.v:043: PREPROC '`line 43 "verilog/v_hier_sub.v" 2 ' verilog/v_hier_sub.v:043: ENDPARSE '' verilog/example.v:001: PREPROC '`line 1 "verilog/example.v" 1 ' verilog/example.v:005: unreadback ' ' verilog/example.v:005: PREPROC '`timescale 1ns/1ns' verilog/example.v:007: unreadback ' ' verilog/example.v:007: KEYWORD 'module' verilog/example.v:007: unreadback ' ' verilog/example.v:007: SYMBOL 'example' verilog/example.v:007: OPERATOR ';' verilog/example.v:009: unreadback ' ' verilog/example.v:009: SYMBOL 'pli' verilog/example.v:009: unreadback ' ' verilog/example.v:009: SYMBOL 'pli' verilog/example.v:009: unreadback ' ' verilog/example.v:009: OPERATOR '(' verilog/example.v:009: OPERATOR ')' verilog/example.v:009: OPERATOR ';' verilog/example.v:011: unreadback ' ' verilog/example.v:011: KEYWORD 'integer' verilog/example.v:011: unreadback ' ' verilog/example.v:011: SYMBOL 'i' verilog/example.v:011: OPERATOR ';' verilog/example.v:015: unreadback ' ' verilog/example.v:015: KEYWORD 'reg' verilog/example.v:015: unreadback ' ' verilog/example.v:015: SYMBOL '\escaped[10] ' verilog/example.v:015: OPERATOR ';' verilog/example.v:017: unreadback ' ' verilog/example.v:017: KEYWORD 'initial' verilog/example.v:017: unreadback ' ' verilog/example.v:017: KEYWORD 'begin' verilog/example.v:018: unreadback ' ' verilog/example.v:018: SYMBOL '$uinfo' verilog/example.v:018: unreadback ' ' verilog/example.v:018: OPERATOR '(' verilog/example.v:018: NUMBER '0' verilog/example.v:018: OPERATOR ',' verilog/example.v:018: unreadback ' ' verilog/example.v:018: STRING '"Welcome to a VPASSERTed file\n"' verilog/example.v:018: OPERATOR ')' verilog/example.v:018: OPERATOR ';' verilog/example.v:020: unreadback ' ' verilog/example.v:020: SYMBOL '$uinfo' verilog/example.v:020: unreadback ' ' verilog/example.v:020: OPERATOR '(' verilog/example.v:020: NUMBER '1' verilog/example.v:020: OPERATOR ',' verilog/example.v:020: unreadback ' ' verilog/example.v:020: STRING '"Printed only at debug level %0d\n"' verilog/example.v:020: OPERATOR ',' verilog/example.v:020: NUMBER '1' verilog/example.v:020: OPERATOR ')' verilog/example.v:020: OPERATOR ';' verilog/example.v:021: unreadback ' ' verilog/example.v:021: SYMBOL '$uinfo' verilog/example.v:021: unreadback ' ' verilog/example.v:021: OPERATOR '(' verilog/example.v:021: NUMBER '9' verilog/example.v:021: OPERATOR ',' verilog/example.v:021: unreadback ' ' verilog/example.v:021: STRING '"Printed only at debug level %0d\n"' verilog/example.v:021: OPERATOR ',' verilog/example.v:021: NUMBER '9' verilog/example.v:021: OPERATOR ')' verilog/example.v:021: OPERATOR ';' verilog/example.v:023: unreadback ' ' verilog/example.v:023: SYMBOL '\escaped[10] ' verilog/example.v:023: OPERATOR '=' verilog/example.v:023: unreadback ' ' verilog/example.v:023: NUMBER '1'b1' verilog/example.v:023: OPERATOR ';' verilog/example.v:024: unreadback ' ' verilog/example.v:024: SYMBOL '$uassert' verilog/example.v:024: unreadback ' ' verilog/example.v:024: OPERATOR '(' verilog/example.v:024: SYMBOL '\escaped[10] ' verilog/example.v:024: OPERATOR ',' verilog/example.v:024: unreadback ' ' verilog/example.v:024: STRING '"Escaped not 1\n"' verilog/example.v:024: OPERATOR ')' verilog/example.v:024: OPERATOR ';' verilog/example.v:025: unreadback ' ' verilog/example.v:025: SYMBOL '$uassert_info' verilog/example.v:025: unreadback ' ' verilog/example.v:025: OPERATOR '(' verilog/example.v:025: SYMBOL '\escaped[10] ' verilog/example.v:025: OPERATOR ',' verilog/example.v:025: unreadback ' ' verilog/example.v:025: STRING '"Escaped not 1\n"' verilog/example.v:025: OPERATOR ')' verilog/example.v:025: OPERATOR ';' verilog/example.v:027: unreadback ' ' verilog/example.v:027: SYMBOL 'i' verilog/example.v:027: OPERATOR '=' verilog/example.v:027: NUMBER '0' verilog/example.v:027: OPERATOR ';' verilog/example.v:028: unreadback ' ' verilog/example.v:028: SYMBOL '$uassert' verilog/example.v:028: unreadback ' ' verilog/example.v:028: OPERATOR '(' verilog/example.v:028: NUMBER '1' verilog/example.v:028: OPERATOR '==' verilog/example.v:028: NUMBER '1' verilog/example.v:028: OPERATOR ',' verilog/example.v:028: unreadback ' ' verilog/example.v:028: STRING '"Why doesn't 1==1??\n"' verilog/example.v:028: OPERATOR ')' verilog/example.v:028: OPERATOR ';' verilog/example.v:029: unreadback ' ' verilog/example.v:029: SYMBOL '$uassert' verilog/example.v:029: unreadback ' ' verilog/example.v:029: OPERATOR '(' verilog/example.v:029: NUMBER '10' verilog/example.v:029: OPERATOR '==' verilog/example.v:029: NUMBER '10' verilog/example.v:029: OPERATOR ',' verilog/example.v:029: unreadback ' ' verilog/example.v:029: STRING '"Why doesn't 10==10??\n"' verilog/example.v:029: OPERATOR ')' verilog/example.v:029: OPERATOR ';' verilog/example.v:030: unreadback ' ' verilog/example.v:030: SYMBOL '$uassert' verilog/example.v:030: unreadback ' ' verilog/example.v:030: OPERATOR '(' verilog/example.v:030: unreadback ' ' verilog/example.v:030: PREPROC '`line 30 "verilog/example.v" 0 ' verilog/example.v:030: unreadback ' ' verilog/example.v:030: NUMBER '1' verilog/example.v:030: OPERATOR '==' verilog/example.v:030: NUMBER '1' verilog/example.v:030: OPERATOR ',' verilog/example.v:033: unreadback ' ' verilog/example.v:033: PREPROC '`line 33 "verilog/example.v" 0 ' verilog/example.v:033: unreadback ' ' verilog/example.v:033: STRING '"Why doesn't 1==1??\n"' verilog/example.v:036: unreadback ' ' verilog/example.v:036: OPERATOR ')' verilog/example.v:036: OPERATOR ';' verilog/example.v:038: unreadback ' ' verilog/example.v:038: SYMBOL 'i' verilog/example.v:038: OPERATOR '=' verilog/example.v:038: NUMBER '3'b100' verilog/example.v:038: OPERATOR ';' verilog/example.v:038: unreadback ' ' verilog/example.v:038: SYMBOL '$uassert_amone' verilog/example.v:038: OPERATOR '(' verilog/example.v:038: SYMBOL 'i' verilog/example.v:038: unreadback ' ' verilog/example.v:038: OPERATOR '[' verilog/example.v:038: NUMBER '2' verilog/example.v:038: OPERATOR ':' verilog/example.v:038: NUMBER '0' verilog/example.v:038: OPERATOR ']' verilog/example.v:038: OPERATOR ',' verilog/example.v:038: unreadback ' ' verilog/example.v:038: STRING '"amone ok\n"' verilog/example.v:038: OPERATOR ')' verilog/example.v:038: OPERATOR ';' verilog/example.v:039: unreadback ' ' verilog/example.v:039: SYMBOL 'i' verilog/example.v:039: OPERATOR '=' verilog/example.v:039: NUMBER '3'b010' verilog/example.v:039: OPERATOR ';' verilog/example.v:039: unreadback ' ' verilog/example.v:039: SYMBOL '$uassert_amone' verilog/example.v:039: OPERATOR '(' verilog/example.v:039: SYMBOL 'i' verilog/example.v:039: OPERATOR '[' verilog/example.v:039: NUMBER '2' verilog/example.v:039: OPERATOR ':' verilog/example.v:039: NUMBER '0' verilog/example.v:039: OPERATOR ']' verilog/example.v:039: OPERATOR ',' verilog/example.v:039: unreadback ' ' verilog/example.v:039: STRING '"amone ok\n"' verilog/example.v:039: OPERATOR ')' verilog/example.v:039: OPERATOR ';' verilog/example.v:040: unreadback ' ' verilog/example.v:040: SYMBOL 'i' verilog/example.v:040: OPERATOR '=' verilog/example.v:040: NUMBER '3'b001' verilog/example.v:040: OPERATOR ';' verilog/example.v:040: unreadback ' ' verilog/example.v:040: SYMBOL '$uassert_amone' verilog/example.v:040: OPERATOR '(' verilog/example.v:040: SYMBOL 'i' verilog/example.v:040: OPERATOR '[' verilog/example.v:040: NUMBER '2' verilog/example.v:040: OPERATOR ':' verilog/example.v:040: NUMBER '0' verilog/example.v:040: OPERATOR ']' verilog/example.v:040: OPERATOR ',' verilog/example.v:040: unreadback ' ' verilog/example.v:040: STRING '"amone ok\n"' verilog/example.v:040: OPERATOR ')' verilog/example.v:040: OPERATOR ';' verilog/example.v:041: unreadback ' ' verilog/example.v:041: SYMBOL 'i' verilog/example.v:041: OPERATOR '=' verilog/example.v:041: NUMBER '3'b000' verilog/example.v:041: OPERATOR ';' verilog/example.v:041: unreadback ' ' verilog/example.v:041: SYMBOL '$uassert_amone' verilog/example.v:041: OPERATOR '(' verilog/example.v:041: SYMBOL 'i' verilog/example.v:041: OPERATOR '[' verilog/example.v:041: NUMBER '2' verilog/example.v:041: OPERATOR ':' verilog/example.v:041: NUMBER '0' verilog/example.v:041: OPERATOR ']' verilog/example.v:041: OPERATOR ',' verilog/example.v:041: unreadback ' ' verilog/example.v:041: STRING '"amone ok\n"' verilog/example.v:041: OPERATOR ')' verilog/example.v:041: OPERATOR ';' verilog/example.v:045: unreadback ' ' verilog/example.v:045: SYMBOL 'i' verilog/example.v:045: OPERATOR '=' verilog/example.v:045: NUMBER '2'b10' verilog/example.v:045: OPERATOR ';' verilog/example.v:045: unreadback ' ' verilog/example.v:045: SYMBOL '$uassert_onehot' verilog/example.v:045: OPERATOR '(' verilog/example.v:045: SYMBOL 'i' verilog/example.v:045: OPERATOR '[' verilog/example.v:045: NUMBER '1' verilog/example.v:045: OPERATOR ':' verilog/example.v:045: NUMBER '0' verilog/example.v:045: OPERATOR ']' verilog/example.v:045: OPERATOR ',' verilog/example.v:045: unreadback ' ' verilog/example.v:045: STRING '"onehot ok\n"' verilog/example.v:045: OPERATOR ')' verilog/example.v:045: OPERATOR ';' verilog/example.v:046: unreadback ' ' verilog/example.v:046: SYMBOL 'i' verilog/example.v:046: OPERATOR '=' verilog/example.v:046: NUMBER '2'b01' verilog/example.v:046: OPERATOR ';' verilog/example.v:046: unreadback ' ' verilog/example.v:046: SYMBOL '$uassert_onehot' verilog/example.v:046: OPERATOR '(' verilog/example.v:046: SYMBOL 'i' verilog/example.v:046: OPERATOR '[' verilog/example.v:046: NUMBER '1' verilog/example.v:046: OPERATOR ':' verilog/example.v:046: NUMBER '0' verilog/example.v:046: OPERATOR ']' verilog/example.v:046: OPERATOR ',' verilog/example.v:046: unreadback ' ' verilog/example.v:046: STRING '"onehot ok\n"' verilog/example.v:046: OPERATOR ')' verilog/example.v:046: OPERATOR ';' verilog/example.v:047: unreadback ' ' verilog/example.v:047: SYMBOL 'i' verilog/example.v:047: OPERATOR '=' verilog/example.v:047: NUMBER '2'b10' verilog/example.v:047: OPERATOR ';' verilog/example.v:047: unreadback ' ' verilog/example.v:047: SYMBOL '$uassert_onehot' verilog/example.v:047: OPERATOR '(' verilog/example.v:047: SYMBOL 'i' verilog/example.v:047: OPERATOR '[' verilog/example.v:047: NUMBER '1' verilog/example.v:047: OPERATOR ']' verilog/example.v:047: OPERATOR ',' verilog/example.v:047: SYMBOL 'i' verilog/example.v:047: OPERATOR '[' verilog/example.v:047: NUMBER '0' verilog/example.v:047: OPERATOR ']' verilog/example.v:047: OPERATOR ',' verilog/example.v:047: unreadback ' ' verilog/example.v:047: STRING '"onehot ok\n"' verilog/example.v:047: OPERATOR ')' verilog/example.v:047: OPERATOR ';' verilog/example.v:048: unreadback ' ' verilog/example.v:048: SYMBOL 'i' verilog/example.v:048: OPERATOR '=' verilog/example.v:048: NUMBER '2'b10' verilog/example.v:048: OPERATOR ';' verilog/example.v:048: unreadback ' ' verilog/example.v:048: SYMBOL '$uassert_onehot' verilog/example.v:048: OPERATOR '(' verilog/example.v:048: OPERATOR '{' verilog/example.v:048: SYMBOL 'i' verilog/example.v:048: OPERATOR '[' verilog/example.v:048: NUMBER '1' verilog/example.v:048: OPERATOR ']' verilog/example.v:048: OPERATOR ',' verilog/example.v:048: SYMBOL 'i' verilog/example.v:048: OPERATOR '[' verilog/example.v:048: NUMBER '0' verilog/example.v:048: OPERATOR ']' verilog/example.v:048: OPERATOR '}' verilog/example.v:048: OPERATOR ',' verilog/example.v:048: unreadback ' ' verilog/example.v:048: STRING '"onehot ok\n"' verilog/example.v:048: OPERATOR ')' verilog/example.v:048: OPERATOR ';' verilog/example.v:051: unreadback ' ' verilog/example.v:051: KEYWORD 'end' verilog/example.v:054: unreadback ' ' verilog/example.v:054: KEYWORD 'initial' verilog/example.v:054: unreadback ' ' verilog/example.v:054: KEYWORD 'begin' verilog/example.v:055: unreadback ' ' verilog/example.v:055: SYMBOL 'i' verilog/example.v:055: OPERATOR '=' verilog/example.v:055: NUMBER '3'b100' verilog/example.v:055: OPERATOR ';' verilog/example.v:056: unreadback ' ' verilog/example.v:056: KEYWORD 'casez' verilog/example.v:056: unreadback ' ' verilog/example.v:056: OPERATOR '(' verilog/example.v:056: SYMBOL 'i' verilog/example.v:056: OPERATOR ')' verilog/example.v:057: unreadback ' ' verilog/example.v:057: NUMBER '3'b100' verilog/example.v:057: OPERATOR ':' verilog/example.v:057: unreadback ' ' verilog/example.v:057: OPERATOR ';' verilog/example.v:058: unreadback ' ' verilog/example.v:058: NUMBER '3'b000' verilog/example.v:058: OPERATOR ':' verilog/example.v:058: unreadback ' ' verilog/example.v:058: SYMBOL '$stop' verilog/example.v:058: OPERATOR ';' verilog/example.v:059: unreadback ' ' verilog/example.v:059: NUMBER '3'b010' verilog/example.v:059: OPERATOR ':' verilog/example.v:059: unreadback ' ' verilog/example.v:059: SYMBOL '$uerror' verilog/example.v:059: OPERATOR '(' verilog/example.v:059: STRING '"Why?\n"' verilog/example.v:059: OPERATOR ')' verilog/example.v:059: OPERATOR ';' verilog/example.v:060: unreadback ' ' verilog/example.v:060: KEYWORD 'default' verilog/example.v:060: OPERATOR ':' verilog/example.v:060: unreadback ' ' verilog/example.v:060: SYMBOL '$stop' verilog/example.v:060: OPERATOR ';' verilog/example.v:061: unreadback ' ' verilog/example.v:061: KEYWORD 'endcase' verilog/example.v:062: unreadback ' ' verilog/example.v:062: KEYWORD 'if' verilog/example.v:062: unreadback ' ' verilog/example.v:062: OPERATOR '(' verilog/example.v:062: SYMBOL '$time' verilog/example.v:062: unreadback ' ' verilog/example.v:062: OPERATOR '>' verilog/example.v:062: unreadback ' ' verilog/example.v:062: NUMBER '1000' verilog/example.v:062: OPERATOR ')' verilog/example.v:062: unreadback ' ' verilog/example.v:062: SYMBOL '$stop' verilog/example.v:062: OPERATOR ';' verilog/example.v:063: unreadback ' ' verilog/example.v:063: KEYWORD 'end' verilog/example.v:066: unreadback ' ' verilog/example.v:066: KEYWORD 'reg' verilog/example.v:066: unreadback ' ' verilog/example.v:066: SYMBOL 'clk' verilog/example.v:066: OPERATOR ';' verilog/example.v:067: unreadback ' ' verilog/example.v:067: KEYWORD 'reg' verilog/example.v:067: unreadback ' ' verilog/example.v:067: SYMBOL 'bus_req' verilog/example.v:067: OPERATOR ';' verilog/example.v:068: unreadback ' ' verilog/example.v:068: KEYWORD 'reg' verilog/example.v:068: unreadback ' ' verilog/example.v:068: SYMBOL 'bus_ack' verilog/example.v:068: OPERATOR ';' verilog/example.v:069: unreadback ' ' verilog/example.v:069: KEYWORD 'reg' verilog/example.v:069: unreadback ' ' verilog/example.v:069: OPERATOR '[' verilog/example.v:069: NUMBER '31' verilog/example.v:069: OPERATOR ':' verilog/example.v:069: NUMBER '0' verilog/example.v:069: OPERATOR ']' verilog/example.v:069: unreadback ' ' verilog/example.v:069: SYMBOL 'bus_data' verilog/example.v:069: OPERATOR ';' verilog/example.v:071: unreadback ' ' verilog/example.v:071: KEYWORD 'initial' verilog/example.v:071: unreadback ' ' verilog/example.v:071: KEYWORD 'begin' verilog/example.v:073: unreadback ' ' verilog/example.v:073: SYMBOL 'bus_req' verilog/example.v:073: unreadback ' ' verilog/example.v:073: OPERATOR '=' verilog/example.v:073: unreadback ' ' verilog/example.v:073: NUMBER '1'b0' verilog/example.v:073: OPERATOR ';' verilog/example.v:074: unreadback ' ' verilog/example.v:074: SYMBOL 'bus_ack' verilog/example.v:074: unreadback ' ' verilog/example.v:074: OPERATOR '=' verilog/example.v:074: unreadback ' ' verilog/example.v:074: NUMBER '1'b0' verilog/example.v:074: OPERATOR ';' verilog/example.v:075: unreadback ' ' verilog/example.v:075: SYMBOL 'bus_data' verilog/example.v:075: unreadback ' ' verilog/example.v:075: OPERATOR '=' verilog/example.v:075: unreadback ' ' verilog/example.v:075: NUMBER '1'b0' verilog/example.v:075: OPERATOR ';' verilog/example.v:077: unreadback ' ' verilog/example.v:077: OPERATOR '@' verilog/example.v:077: unreadback ' ' verilog/example.v:077: OPERATOR '(' verilog/example.v:077: KEYWORD 'posedge' verilog/example.v:077: unreadback ' ' verilog/example.v:077: SYMBOL 'clk' verilog/example.v:077: OPERATOR ')' verilog/example.v:077: unreadback ' ' verilog/example.v:077: OPERATOR ';' verilog/example.v:078: unreadback ' ' verilog/example.v:078: SYMBOL 'bus_req' verilog/example.v:078: unreadback ' ' verilog/example.v:078: OPERATOR '=' verilog/example.v:078: unreadback ' ' verilog/example.v:078: NUMBER '1'b1' verilog/example.v:078: OPERATOR ';' verilog/example.v:079: unreadback ' ' verilog/example.v:079: SYMBOL 'bus_data' verilog/example.v:079: unreadback ' ' verilog/example.v:079: OPERATOR '=' verilog/example.v:079: unreadback ' ' verilog/example.v:079: NUMBER '32'hfeed' verilog/example.v:079: OPERATOR ';' verilog/example.v:081: unreadback ' ' verilog/example.v:081: OPERATOR '@' verilog/example.v:081: unreadback ' ' verilog/example.v:081: OPERATOR '(' verilog/example.v:081: KEYWORD 'posedge' verilog/example.v:081: unreadback ' ' verilog/example.v:081: SYMBOL 'clk' verilog/example.v:081: OPERATOR ')' verilog/example.v:081: unreadback ' ' verilog/example.v:081: OPERATOR ';' verilog/example.v:082: unreadback ' ' verilog/example.v:082: SYMBOL 'bus_req' verilog/example.v:082: unreadback ' ' verilog/example.v:082: OPERATOR '=' verilog/example.v:082: unreadback ' ' verilog/example.v:082: NUMBER '1'b0' verilog/example.v:082: OPERATOR ';' verilog/example.v:084: unreadback ' ' verilog/example.v:084: OPERATOR '@' verilog/example.v:084: unreadback ' ' verilog/example.v:084: OPERATOR '(' verilog/example.v:084: KEYWORD 'posedge' verilog/example.v:084: unreadback ' ' verilog/example.v:084: SYMBOL 'clk' verilog/example.v:084: OPERATOR ')' verilog/example.v:084: unreadback ' ' verilog/example.v:084: OPERATOR ';' verilog/example.v:085: unreadback ' ' verilog/example.v:085: SYMBOL 'bus_ack' verilog/example.v:085: unreadback ' ' verilog/example.v:085: OPERATOR '=' verilog/example.v:085: unreadback ' ' verilog/example.v:085: NUMBER '1'b1' verilog/example.v:085: OPERATOR ';' verilog/example.v:087: unreadback ' ' verilog/example.v:087: OPERATOR '@' verilog/example.v:087: unreadback ' ' verilog/example.v:087: OPERATOR '(' verilog/example.v:087: KEYWORD 'posedge' verilog/example.v:087: unreadback ' ' verilog/example.v:087: SYMBOL 'clk' verilog/example.v:087: OPERATOR ')' verilog/example.v:087: unreadback ' ' verilog/example.v:087: OPERATOR ';' verilog/example.v:088: unreadback ' ' verilog/example.v:088: SYMBOL 'bus_ack' verilog/example.v:088: unreadback ' ' verilog/example.v:088: OPERATOR '=' verilog/example.v:088: unreadback ' ' verilog/example.v:088: NUMBER '1'b0' verilog/example.v:088: OPERATOR ';' verilog/example.v:089: unreadback ' ' verilog/example.v:089: KEYWORD 'end' verilog/example.v:090: unreadback ' ' verilog/example.v:090: KEYWORD 'always' verilog/example.v:090: unreadback ' ' verilog/example.v:090: OPERATOR '@' verilog/example.v:090: unreadback ' ' verilog/example.v:090: OPERATOR '(' verilog/example.v:090: KEYWORD 'posedge' verilog/example.v:090: unreadback ' ' verilog/example.v:090: SYMBOL 'clk' verilog/example.v:090: OPERATOR ')' verilog/example.v:090: unreadback ' ' verilog/example.v:090: KEYWORD 'begin' verilog/example.v:091: unreadback ' ' verilog/example.v:091: SYMBOL '$uassert_req_ack' verilog/example.v:091: unreadback ' ' verilog/example.v:091: OPERATOR '(' verilog/example.v:091: SYMBOL 'bus_req' verilog/example.v:091: OPERATOR ',' verilog/example.v:092: unreadback ' ' verilog/example.v:092: SYMBOL 'bus_ack' verilog/example.v:092: unreadback ' ' verilog/example.v:092: OPERATOR ',' verilog/example.v:093: unreadback ' ' verilog/example.v:093: SYMBOL 'bus_data' verilog/example.v:093: OPERATOR ')' verilog/example.v:093: OPERATOR ';' verilog/example.v:094: unreadback ' ' verilog/example.v:094: KEYWORD 'end' verilog/example.v:097: unreadback ' ' verilog/example.v:097: KEYWORD 'initial' verilog/example.v:097: unreadback ' ' verilog/example.v:097: SYMBOL 'clk' verilog/example.v:097: unreadback ' ' verilog/example.v:097: OPERATOR '=' verilog/example.v:097: unreadback ' ' verilog/example.v:097: NUMBER '1'b0' verilog/example.v:097: OPERATOR ';' verilog/example.v:098: unreadback ' ' verilog/example.v:098: KEYWORD 'initial' verilog/example.v:098: unreadback ' ' verilog/example.v:098: KEYWORD 'forever' verilog/example.v:098: unreadback ' ' verilog/example.v:098: KEYWORD 'begin' verilog/example.v:099: unreadback ' ' verilog/example.v:099: OPERATOR '#' verilog/example.v:099: NUMBER '1' verilog/example.v:099: OPERATOR ';' verilog/example.v:100: unreadback ' ' verilog/example.v:100: SYMBOL 'i' verilog/example.v:100: unreadback ' ' verilog/example.v:100: OPERATOR '=' verilog/example.v:100: unreadback ' ' verilog/example.v:100: SYMBOL 'i' verilog/example.v:100: unreadback ' ' verilog/example.v:100: OPERATOR '+' verilog/example.v:100: unreadback ' ' verilog/example.v:100: NUMBER '1' verilog/example.v:100: OPERATOR ';' verilog/example.v:101: unreadback ' ' verilog/example.v:101: SYMBOL 'clk' verilog/example.v:101: unreadback ' ' verilog/example.v:101: OPERATOR '=' verilog/example.v:101: unreadback ' ' verilog/example.v:101: OPERATOR '!' verilog/example.v:101: SYMBOL 'clk' verilog/example.v:101: OPERATOR ';' verilog/example.v:102: unreadback ' ' verilog/example.v:102: KEYWORD 'if' verilog/example.v:102: unreadback ' ' verilog/example.v:102: OPERATOR '(' verilog/example.v:102: SYMBOL 'i' verilog/example.v:102: OPERATOR '==' verilog/example.v:102: NUMBER '20' verilog/example.v:102: OPERATOR ')' verilog/example.v:102: unreadback ' ' verilog/example.v:102: SYMBOL '$uwarn' verilog/example.v:102: unreadback ' ' verilog/example.v:102: OPERATOR '(' verilog/example.v:102: NUMBER '0' verilog/example.v:102: OPERATOR ',' verilog/example.v:102: unreadback ' ' verilog/example.v:102: STRING '"Don't know what to do next!\n"' verilog/example.v:102: OPERATOR ')' verilog/example.v:102: OPERATOR ';' verilog/example.v:103: unreadback ' ' verilog/example.v:103: KEYWORD 'if' verilog/example.v:103: unreadback ' ' verilog/example.v:103: OPERATOR '(' verilog/example.v:103: SYMBOL 'i' verilog/example.v:103: OPERATOR '==' verilog/example.v:103: NUMBER '22' verilog/example.v:103: OPERATOR ')' verilog/example.v:103: unreadback ' ' verilog/example.v:103: SYMBOL '$uerror' verilog/example.v:103: unreadback ' ' verilog/example.v:103: OPERATOR '(' verilog/example.v:103: NUMBER '0' verilog/example.v:103: OPERATOR ',' verilog/example.v:103: unreadback ' ' verilog/example.v:103: STRING '"Guess I'll error out!\n"' verilog/example.v:103: OPERATOR ')' verilog/example.v:103: OPERATOR ';' verilog/example.v:104: unreadback ' ' verilog/example.v:104: KEYWORD 'end' verilog/example.v:107: unreadback ' ' verilog/example.v:107: KEYWORD 'always' verilog/example.v:107: unreadback ' ' verilog/example.v:107: OPERATOR '@' verilog/example.v:107: OPERATOR '*' verilog/example.v:107: unreadback ' ' verilog/example.v:107: KEYWORD 'begin' verilog/example.v:108: unreadback ' ' verilog/example.v:108: KEYWORD 'if' verilog/example.v:108: unreadback ' ' verilog/example.v:108: OPERATOR '(' verilog/example.v:108: SYMBOL 'i' verilog/example.v:108: OPERATOR '==' verilog/example.v:108: NUMBER '19' verilog/example.v:108: OPERATOR ')' verilog/example.v:108: unreadback ' ' verilog/example.v:108: SYMBOL '$uwarn_clk' verilog/example.v:108: unreadback ' ' verilog/example.v:108: OPERATOR '(' verilog/example.v:108: SYMBOL 'clk' verilog/example.v:108: OPERATOR ',' verilog/example.v:108: STRING '"Called at next edge (1 of 2)\n"' verilog/example.v:108: OPERATOR ')' verilog/example.v:108: OPERATOR ';' verilog/example.v:109: unreadback ' ' verilog/example.v:109: KEYWORD 'if' verilog/example.v:109: unreadback ' ' verilog/example.v:109: OPERATOR '(' verilog/example.v:109: SYMBOL 'i' verilog/example.v:109: OPERATOR '==' verilog/example.v:109: NUMBER '18' verilog/example.v:109: OPERATOR ')' verilog/example.v:109: unreadback ' ' verilog/example.v:109: SYMBOL '$ucover_clk' verilog/example.v:109: unreadback ' ' verilog/example.v:109: OPERATOR '(' verilog/example.v:109: SYMBOL 'clk' verilog/example.v:109: OPERATOR ',' verilog/example.v:109: STRING '"example_cover_label"' verilog/example.v:109: OPERATOR ')' verilog/example.v:109: OPERATOR ';' verilog/example.v:110: unreadback ' ' verilog/example.v:110: SYMBOL '$ucover_foreach_clk' verilog/example.v:110: OPERATOR '(' verilog/example.v:110: SYMBOL 'clk' verilog/example.v:110: OPERATOR ',' verilog/example.v:110: unreadback ' ' verilog/example.v:110: STRING '"foreach_label"' verilog/example.v:110: OPERATOR ',' verilog/example.v:110: unreadback ' ' verilog/example.v:110: STRING '"27:3,1,0"' verilog/example.v:110: OPERATOR ',' verilog/example.v:110: unreadback ' ' verilog/example.v:110: OPERATOR '(' verilog/example.v:110: SYMBOL 'i' verilog/example.v:110: OPERATOR '[' verilog/example.v:110: SYMBOL '$ui' verilog/example.v:110: OPERATOR ']' verilog/example.v:110: OPERATOR ')' verilog/example.v:110: OPERATOR ')' verilog/example.v:110: OPERATOR ';' verilog/example.v:111: unreadback ' ' verilog/example.v:111: KEYWORD 'end' verilog/example.v:114: unreadback ' ' verilog/example.v:114: KEYWORD 'initial' verilog/example.v:114: unreadback ' ' verilog/example.v:114: KEYWORD 'begin' verilog/example.v:116: unreadback ' ' verilog/example.v:116: KEYWORD 'if' verilog/example.v:116: unreadback ' ' verilog/example.v:116: OPERATOR '(' verilog/example.v:116: NUMBER '0' verilog/example.v:116: OPERATOR ')' verilog/example.v:116: unreadback ' ' verilog/example.v:116: KEYWORD 'begin' verilog/example.v:116: unreadback ' ' verilog/example.v:116: KEYWORD 'end' verilog/example.v:118: unreadback ' ' verilog/example.v:118: KEYWORD 'end' verilog/example.v:121: unreadback ' ' verilog/example.v:121: KEYWORD 'initial' verilog/example.v:121: unreadback ' ' verilog/example.v:121: KEYWORD 'begin' verilog/example.v:128: unreadback ' ' verilog/example.v:128: KEYWORD 'if' verilog/example.v:128: unreadback ' ' verilog/example.v:128: OPERATOR '(' verilog/example.v:128: NUMBER '1' verilog/example.v:128: OPERATOR ')' verilog/example.v:128: unreadback ' ' verilog/example.v:128: KEYWORD 'begin' verilog/example.v:128: unreadback ' ' verilog/example.v:128: KEYWORD 'end' verilog/example.v:131: unreadback ' ' verilog/example.v:131: KEYWORD 'if' verilog/example.v:131: unreadback ' ' verilog/example.v:131: OPERATOR '(' verilog/example.v:131: NUMBER '1' verilog/example.v:131: OPERATOR ')' verilog/example.v:131: unreadback ' ' verilog/example.v:131: KEYWORD 'begin' verilog/example.v:131: unreadback ' ' verilog/example.v:131: KEYWORD 'end' verilog/example.v:136: unreadback ' ' verilog/example.v:136: KEYWORD 'end' verilog/example.v:138: unreadback ' ' verilog/example.v:138: KEYWORD 'endmodule' verilog/example.v:140: unreadback ' ' verilog/example.v:140: PREPROC '`line 140 "verilog/example.v" 2 ' verilog/example.v:140: ENDPARSE '' Verilog-Perl-3.482/t/51_vrename_kwd.v0000755000177100017500000000203013462302176017257 0ustar wsnyderwsnyder// DESCRIPTION: Verilog-Perl: Example Verilog for testing package // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2010-2012 by Wilson Snyder. module 51_vrename_kwd; // Keyword wire do; wire \do ; // Non escapes wire non_2non; wire non_2non_nospace ; wire non_2ext; wire non_2ext_nospace ; wire non_2esc; wire non_2esc_nospace ; // Extra unnecessary escapes // Note we cannot legally remove spaces if replacing with non-escaped name wire \ext_2non ; wire \ext_2non_nospace ; wire \ext_2ext ; wire \ext_2ext_nospace ; wire \ext_2esc ; wire \ext_2esc_nospace ; // Necessary escapes wire \esc[ape]_2non ; wire \esc[ape]_2non_nospace ; wire \esc[ape]_2ext ; wire \esc[ape]_2ext_nospace ; wire \esc[ape]_2esc ; wire \esc[ape]_2esc_nospace ; // Strings initial $display("foo"); initial $display("foo.foo"); initial $display("baz_foo"); initial $display("foo_baz"); endmodule Verilog-Perl-3.482/t/30_preproc_sub.out0000644000177100017500000013774714030463163017660 0ustar wsnyderwsnyderverilog/inc_nonl.v:1: `line 1 "verilog/inc1.v" 1 verilog/inc_nonl.v:1: `line 1 "verilog/inc1.v" 0 verilog/inc_nonl.v:1: `line 1 "verilog/inc2.v" 1 verilog/inc_nonl.v:1: `line 1 "verilog/inc2.v" 0 verilog/inc_nonl.v:1: `line 1 "verilog/inc_ifdef.v" 1 verilog/inc_nonl.v:1: `line 1 "verilog/inc_ifdef.v" 0 verilog/inc_nonl.v:1: `line 1 "verilog/inc_nonl.v" 1 verilog/inc_nonl.v:1: `line 1 "verilog/inc_nonl.v" 0 verilog/inc_nonl.v:1: `line 1 "verilog/inc_def09.v" 1 verilog/inc_def09.v:1: COMMENT: // DESCRIPTION: Verilog-Perl: Verilog Test module verilog/inc_def09.v:1: /*CMT*/ verilog/inc_def09.v:2: COMMENT: // verilog/inc_def09.v:2: /*CMT*/ verilog/inc_def09.v:3: COMMENT: // This file ONLY is placed into the Public Domain, for any use, verilog/inc_def09.v:3: /*CMT*/ verilog/inc_def09.v:4: COMMENT: // without warranty, 2009 by Wilson Snyder. verilog/inc_def09.v:4: /*CMT*/ verilog/inc_def09.v:5: verilog/inc_def09.v:6: verilog/inc_def09.v:7: verilog/inc_def09.v:8: COMMENT: // Definitions as speced verilog/inc_def09.v:8: /*CMT*/ verilog/inc_def09.v:9: COMMENT: // Note there are trailing spaces, which spec doesn't show properly verilog/inc_def09.v:9: /*CMT*/ verilog/inc_def09.v:10: verilog/inc_def09.v:11: 'DS_initial $display("start", "msg1" , "msg2", "end");' verilog/inc_def09.v:12: 'initial $display("start", "msg1" , "msg2" , "end");' verilog/inc_def09.v:13: 'DS_initial $display("start", " msg1" , , "end");' verilog/inc_def09.v:14: 'initial $display("start", " msg1" , , "end");' verilog/inc_def09.v:15: 'DS_initial $display("start", , "msg2 ", "end");' verilog/inc_def09.v:16: 'initial $display("start", , "msg2 ", "end");' verilog/inc_def09.v:17: 'DS_initial $display("start", , , "end");' verilog/inc_def09.v:18: 'initial $display("start", , , "end");' verilog/inc_def09.v:19: 'DS_initial $display("start", , , "end");' verilog/inc_def09.v:20: 'initial $display("start", , , "end");' verilog/inc_def09.v:21: COMMENT: //`D("msg1") // ILLEGAL: only one argument verilog/inc_def09.v:21: /*CMT*/ verilog/inc_def09.v:22: COMMENT: //`D() // ILLEGAL: only one empty argument verilog/inc_def09.v:22: /*CMT*/ verilog/inc_def09.v:23: COMMENT: //`D(,,) // ILLEGAL: more actual than formal arguments verilog/inc_def09.v:23: /*CMT*/ verilog/inc_def09.v:24: verilog/inc_def09.v:25: COMMENT: // Defaults: verilog/inc_def09.v:25: /*CMT*/ verilog/inc_def09.v:26: verilog/inc_def09.v:27: 'DS_$display(5,,2,,3);' verilog/inc_def09.v:28: '$display(5,,2,,3);' verilog/inc_def09.v:29: 'DS_$display(1,,"B",,3);' verilog/inc_def09.v:30: '$display(1 ,,"B",,3 );' verilog/inc_def09.v:31: 'DS_$display(5,,2,,);' verilog/inc_def09.v:32: '$display(5,,2,,);' verilog/inc_def09.v:33: COMMENT: //`MACRO1 ( 1 ) // ILLEGAL: b and c omitted, no default for c verilog/inc_def09.v:33: /*CMT*/ verilog/inc_def09.v:34: verilog/inc_def09.v:35: verilog/inc_def09.v:36: 'DS_$display(1,,,,3);' verilog/inc_def09.v:37: '$display(5,,,,"C");' verilog/inc_def09.v:38: 'DS_$display(5,,2,,"C");' verilog/inc_def09.v:39: '$display(5,,2,,"C");' verilog/inc_def09.v:40: 'DS_$display(5,,2,,"C");' verilog/inc_def09.v:41: '$display(5,,2,,"C");' verilog/inc_def09.v:42: verilog/inc_def09.v:43: verilog/inc_def09.v:44: 'DS_$display(1,,0,,"C");' verilog/inc_def09.v:45: '$display(1 ,,0,,"C");' verilog/inc_def09.v:46: 'DS_$display(5,,0,,"C");' verilog/inc_def09.v:47: '$display(5,,0,,"C");' verilog/inc_def09.v:48: COMMENT: //`MACRO3 // ILLEGAL: parentheses required verilog/inc_def09.v:48: /*CMT*/ verilog/inc_def09.v:49: verilog/inc_def09.v:50: verilog/inc_def09.v:51: 'DS_DS_b + 1 + DS_42 + a' verilog/inc_def09.v:52: 'b + 1 + 42 + a' verilog/inc_def09.v:53: verilog/inc_def09.v:54: COMMENT: // Local tests verilog/inc_def09.v:54: /*CMT*/ verilog/inc_def09.v:55: verilog/inc_def09.v:56: DS_'"==)" "((((" () '; verilog/inc_def09.v:57: '"==)" "((((" () '; verilog/inc_def09.v:58: verilog/inc_def09.v:59: COMMENT: // Also check our line counting doesn't go bad verilog/inc_def09.v:59: /*CMT*/ verilog/inc_def09.v:62: verilog/inc_def09.v:62: verilog/inc_def09.v:62: verilog/inc_def09.v:63: verilog/inc_def09.v:64: verilog/inc_def09.v:65: verilog/inc_def09.v:66: verilog/inc_def09.v:67: verilog/inc_def09.v:68: verilog/inc_def09.v:69: verilog/inc_def09.v:70: DS_'(6) (eq=al) ZOT' verilog/inc_def09.v:71: HERE-71 - Line71 verilog/inc_def09.v:72: verilog/inc_def09.v:73: COMMENT: //====================================================================== verilog/inc_def09.v:73: /*CMT*/ verilog/inc_def09.v:74: verilog/inc_def09.v:75: `line 75 "verilog/inc_def09.v" 2 verilog/inc_nonl.v:1: `line 1 "verilog/inc_nonl.v" 0 verilog/inc_nonl.v:1: COMMENT: // The lack of a newline on the next line is intentional verilog/inc_nonl.v:1: /*CMT*/ verilog/inc_nonl.v:2: blah-no-newline-here> verilog/inc_nonl.v:3: `line 3 "verilog/inc_nonl.v" 2 verilog/inc_ifdef.v:1: `line 1 "verilog/inc_ifdef.v" 0 verilog/inc_ifdef.v:1: COMMENT: // DESCRIPTION: Verilog::Preproc: Example source code verilog/inc_ifdef.v:1: /*CMT*/ verilog/inc_ifdef.v:2: COMMENT: // This file ONLY is placed into the Public Domain, for any use, verilog/inc_ifdef.v:2: /*CMT*/ verilog/inc_ifdef.v:3: COMMENT: // without warranty, 2000-2012 by Wilson Snyder. verilog/inc_ifdef.v:3: /*CMT*/ verilog/inc_ifdef.v:4: verilog/inc_ifdef.v:5: verilog/inc_ifdef.v:6: verilog/inc_ifdef.v:7: verilog/inc_ifdef.v:8: verilog/inc_ifdef.v:9: verilog/inc_ifdef.v:10: verilog/inc_ifdef.v:11: verilog/inc_ifdef.v:12: $display("1A"); verilog/inc_ifdef.v:13: verilog/inc_ifdef.v:14: verilog/inc_ifdef.v:15: verilog/inc_ifdef.v:16: $display("2A"); verilog/inc_ifdef.v:17: verilog/inc_ifdef.v:18: verilog/inc_ifdef.v:19: verilog/inc_ifdef.v:20: verilog/inc_ifdef.v:21: verilog/inc_ifdef.v:22: $display("3AELSE"); verilog/inc_ifdef.v:23: verilog/inc_ifdef.v:24: verilog/inc_ifdef.v:25: verilog/inc_ifdef.v:26: verilog/inc_ifdef.v:27: verilog/inc_ifdef.v:28: verilog/inc_ifdef.v:29: verilog/inc_ifdef.v:30: verilog/inc_ifdef.v:31: verilog/inc_ifdef.v:32: verilog/inc_ifdef.v:33: verilog/inc_ifdef.v:34: verilog/inc_ifdef.v:35: verilog/inc_ifdef.v:36: verilog/inc_ifdef.v:37: verilog/inc_ifdef.v:38: verilog/inc_ifdef.v:39: verilog/inc_ifdef.v:40: verilog/inc_ifdef.v:41: verilog/inc_ifdef.v:42: `line 42 "verilog/inc_ifdef.v" 2 verilog/inc2.v:1: `line 1 "verilog/inc2.v" 0 verilog/inc2.v:1: COMMENT: // DESCRIPTION: Verilog::Preproc: Example source code verilog/inc2.v:1: /*CMT*/ verilog/inc2.v:2: COMMENT: // This file ONLY is placed into the Public Domain, for any use, verilog/inc2.v:2: /*CMT*/ verilog/inc2.v:3: COMMENT: // without warranty, 2000-2012 by Wilson Snyder. verilog/inc2.v:3: /*CMT*/ verilog/inc2.v:4: At file "verilog/inc2.v" line 4 verilog/inc2.v:5: verilog/inc2.v:5: `line 5 "verilog/inc2.v" 0 verilog/inc2.v:5: `line 1 "verilog/t_preproc_inc3.vh" 1 verilog/t_preproc_inc3.vh:1: `line 2 "inc3_a_filename_from_line_directive" 0 inc3_a_filename_from_line_directive:2: COMMENT: // DESCRIPTION: Verilog::Preproc: Example source code inc3_a_filename_from_line_directive:2: /*CMT*/ inc3_a_filename_from_line_directive:3: COMMENT: // This file ONLY is placed into the Public Domain, for any use, inc3_a_filename_from_line_directive:3: /*CMT*/ inc3_a_filename_from_line_directive:4: COMMENT: // without warranty, 2000-2012 by Wilson Snyder. inc3_a_filename_from_line_directive:4: /*CMT*/ inc3_a_filename_from_line_directive:5: inc3_a_filename_from_line_directive:6: inc3_a_filename_from_line_directive:7: inc3_a_filename_from_line_directive:8: inc3_a_filename_from_line_directive:9: COMMENT: // FOO inc3_a_filename_from_line_directive:9: /*CMT*/ inc3_a_filename_from_line_directive:10: At file "inc3_a_filename_from_line_directive" line 10 inc3_a_filename_from_line_directive:11: inc3_a_filename_from_line_directive:12: inc3_a_filename_from_line_directive:13: COMMENT: // guard inc3_a_filename_from_line_directive:13: /*CMT*/ inc3_a_filename_from_line_directive:14: inc3_a_filename_from_line_directive:15: inc3_a_filename_from_line_directive:16: inc3_a_filename_from_line_directive:17: inc3_a_filename_from_line_directive:18: inc3_a_filename_from_line_directive:19: `line 19 "inc3_a_filename_from_line_directive" 2 verilog/inc2.v:5: `line 5 "verilog/inc2.v" 0 verilog/inc2.v:5: verilog/inc2.v:6: verilog/inc2.v:7: `line 7 "verilog/inc2.v" 2 verilog/inc1.v:1: `line 1 "verilog/inc1.v" 0 verilog/inc1.v:1: COMMENT: // DESCRIPTION: Verilog::Preproc: Example source code verilog/inc1.v:1: /*CMT*/ verilog/inc1.v:2: COMMENT: // This file ONLY is placed into the Public Domain, for any use, verilog/inc1.v:2: /*CMT*/ verilog/inc1.v:3: COMMENT: // without warranty, 2000-2012 by Wilson Snyder. verilog/inc1.v:3: /*CMT*/ verilog/inc1.v:4: text. verilog/inc1.v:5: verilog/inc1.v:6: COMMENT: //=========================================================================== verilog/inc1.v:6: /*CMT*/ verilog/inc1.v:7: COMMENT: // Includes verilog/inc1.v:7: /*CMT*/ verilog/inc1.v:8: verilog/inc1.v:9: COMMENT: //=========================================================================== verilog/inc1.v:9: /*CMT*/ verilog/inc1.v:10: COMMENT: // Defines verilog/inc1.v:10: /*CMT*/ verilog/inc1.v:11: verilog/inc1.v:12: verilog/inc1.v:13: verilog/inc1.v:14: COMMENT: // DEF_A0 set by command line verilog/inc1.v:14: /*CMT*/ verilog/inc1.v:15: wire [3:0] q = { verilog/inc1.v:16: 1'b1 , verilog/inc1.v:17: 1'b0 , verilog/inc1.v:18: 1'b1 , verilog/inc1.v:19: 1'b0 verilog/inc1.v:20: }; verilog/inc1.v:21: verilog/inc1.v:22: text. verilog/inc1.v:23: verilog/inc1.v:24: verilog/inc1.v:25: COMMENT: // but not verilog/inc1.v:25: verilog/inc1.v:26: COMMENT: /*this */ verilog/inc1.v:26: COMMENT: /* this too */ verilog/inc1.v:26: DS_foo /*CMT*/ bar /*CMT*/ verilog/inc1.v:27: COMMENT: /*CMT*/ verilog/inc1.v:27: DS_foobar2 /*CMT*/ verilog/inc1.v:28: verilog/inc1.v:29: verilog/inc1.v:29: verilog/inc1.v:29: verilog/inc1.v:32: verilog/inc1.v:33: verilog/inc1.v:33: verilog/inc1.v:33: verilog/inc1.v:33: verilog/inc1.v:37: verilog/inc1.v:38: COMMENT: /*******COMMENT*****/ verilog/inc1.v:38: /*CMT*/ verilog/inc1.v:39: DS_first part verilog/inc1.v:39: `line 39 "verilog/inc1.v" 0 verilog/inc1.v:39: second part verilog/inc1.v:39: `line 39 "verilog/inc1.v" 0 verilog/inc1.v:39: third part verilog/inc1.v:40: DS_{ verilog/inc1.v:40: `line 40 "verilog/inc1.v" 0 verilog/inc1.v:40: a, verilog/inc1.v:40: `line 40 "verilog/inc1.v" 0 verilog/inc1.v:40: b, verilog/inc1.v:40: `line 40 "verilog/inc1.v" 0 verilog/inc1.v:40: c} verilog/inc1.v:41: Line_Preproc_Check 41 verilog/inc1.v:42: verilog/inc1.v:43: COMMENT: //=========================================================================== verilog/inc1.v:43: /*CMT*/ verilog/inc1.v:44: verilog/inc1.v:45: verilog/inc1.v:46: verilog/inc1.v:47: verilog/inc1.v:48: verilog/inc1.v:49: DS_DS_deep DS_deep verilog/inc1.v:50: verilog/inc1.v:51: verilog/inc1.v:52: verilog/inc1.v:53: "Inside: `nosubst" verilog/inc1.v:54: "`nosubst" verilog/inc1.v:55: verilog/inc1.v:56: verilog/inc1.v:57: DS_x y LLZZ x y verilog/inc1.v:58: DS_DS_p q LLZZ p q DS_r s LLZZ r s LLZZ DS_p q LLZZ p q DS_r s LLZZ r s verilog/inc1.v:59: verilog/inc1.v:60: verilog/inc1.v:61: verilog/inc1.v:62: DS_firstline comma","line LLZZ firstline comma","line verilog/inc1.v:63: verilog/inc1.v:64: verilog/inc1.v:65: COMMENT: // Simulators disagree here; some substitute "a" others do not verilog/inc1.v:65: DS_x y LLZZ "x" y /*CMT*/ verilog/inc1.v:66: verilog/inc1.v:67: verilog/inc1.v:68: DS_(a,b)(a,b) verilog/inc1.v:69: verilog/inc1.v:70: verilog/inc1.v:71: $display(DS_"left side: \"right side\"") verilog/inc1.v:72: verilog/inc1.v:73: verilog/inc1.v:74: DS_bar_suffix more verilog/inc1.v:75: verilog/inc1.v:76: verilog/inc1.v:76: verilog/inc1.v:78: DS_ verilog/inc1.v:78: `line 78 "verilog/inc1.v" 0 verilog/inc1.v:78: $c("Zap(\"",bug1,"\");");; verilog/inc1.v:79: DS_ verilog/inc1.v:79: `line 79 "verilog/inc1.v" 0 verilog/inc1.v:79: $c("Zap(\"","bug2","\");");; verilog/inc1.v:80: verilog/inc1.v:81: COMMENT: /* Define inside comment: `DEEPER and `WITHTICK */ verilog/inc1.v:81: /*CMT*/ verilog/inc1.v:82: COMMENT: // More commentary: `zap(bug1); `zap("bug2"); verilog/inc1.v:82: /*CMT*/ verilog/inc1.v:83: verilog/inc1.v:84: COMMENT: //====================================================================== verilog/inc1.v:84: /*CMT*/ verilog/inc1.v:85: COMMENT: // display passthru verilog/inc1.v:85: /*CMT*/ verilog/inc1.v:86: verilog/inc1.v:87: verilog/inc1.v:88: verilog/inc1.v:89: verilog/inc1.v:90: verilog/inc1.v:91: COMMENT: // Doesn't expand verilog/inc1.v:91: verilog/inc1.v:92: verilog/inc1.v:93: initial begin verilog/inc1.v:94: COMMENT: //$display(`msg( \`, \`)); // Illegal verilog/inc1.v:94: /*CMT*/ verilog/inc1.v:95: $display(DS_"pre DS_thrupre DS_thrumid thrupost post: \"right side\""); verilog/inc1.v:96: $display(DS_"left side: \"right side\""); verilog/inc1.v:97: $display(DS_"left side: \"right side\""); verilog/inc1.v:98: $display(DS_"DS_left_side: \"DS_right_side\""); verilog/inc1.v:99: $display(DS_"DS_na: \"DS_right_side\""); verilog/inc1.v:100: $display(DS_"prep ( midp1 DS_left_side midp2 ( outp ) ): \"DS_right_side\""); verilog/inc1.v:101: $display(DS_"DS_na: \"DS_naDS_na\""); verilog/inc1.v:102: COMMENT: // Results vary between simulators verilog/inc1.v:102: $display(DS_"DS_DS_left_side DS_right_side /*CMT*/: \"DS_DS_left_side DS_right_side /*CMT*/\""); /*CMT*/ verilog/inc1.v:103: COMMENT: // Empty verilog/inc1.v:103: $display(DS_"DS_: \"\""); /*CMT*/ verilog/inc1.v:104: $display(DS_"DS_left side: \"DS_right side\""); verilog/inc1.v:105: $display(DS_"DS_left side: \"DS_right side\""); verilog/inc1.v:106: $display("standalone"); verilog/inc1.v:107: verilog/inc1.v:108: COMMENT: // Unspecified when the stringification has multiple lines verilog/inc1.v:108: /*CMT*/ verilog/inc1.v:109: verilog/inc1.v:109: verilog/inc1.v:111: $display(DS_"twoline: \"DS_first second\""); verilog/inc1.v:112: COMMENT: //$display(`msg(left side, \ right side \ )); // Not sure \{space} is legal. verilog/inc1.v:112: /*CMT*/ verilog/inc1.v:113: $write("*-* All Finished *-*\n"); verilog/inc1.v:114: $finish; verilog/inc1.v:115: end verilog/inc1.v:116: endmodule verilog/inc1.v:117: verilog/inc1.v:118: COMMENT: //====================================================================== verilog/inc1.v:118: /*CMT*/ verilog/inc1.v:119: COMMENT: // rt.cpan.org bug34429 verilog/inc1.v:119: /*CMT*/ verilog/inc1.v:120: verilog/inc1.v:121: verilog/inc1.v:121: verilog/inc1.v:121: verilog/inc1.v:121: verilog/inc1.v:125: verilog/inc1.v:126: module add1 ( input wire d1, output wire o1); verilog/inc1.v:127: DS_ verilog/inc1.v:127: `line 127 "verilog/inc1.v" 0 verilog/inc1.v:127: wire tmp_d1 = d1; verilog/inc1.v:127: `line 127 "verilog/inc1.v" 0 verilog/inc1.v:127: wire tmp_o1 = tmp_d1 + 1; verilog/inc1.v:127: `line 127 "verilog/inc1.v" 0 verilog/inc1.v:127: COMMENT: // expansion is OK verilog/inc1.v:127: assign o1 = tmp_o1 ; /*CMT*/ verilog/inc1.v:128: endmodule verilog/inc1.v:129: module add2 ( input wire d2, output wire o2); verilog/inc1.v:130: DS_ verilog/inc1.v:130: `line 130 "verilog/inc1.v" 0 verilog/inc1.v:130: wire tmp_d2 = d2; verilog/inc1.v:130: `line 130 "verilog/inc1.v" 0 verilog/inc1.v:130: wire tmp_o2 = tmp_d2 + 1; verilog/inc1.v:130: `line 130 "verilog/inc1.v" 0 verilog/inc1.v:130: COMMENT: // expansion is bad verilog/inc1.v:130: assign o2 = tmp_o2 ; /*CMT*/ verilog/inc1.v:131: endmodule verilog/inc1.v:132: verilog/inc1.v:133: verilog/inc1.v:133: verilog/inc1.v:133: verilog/inc1.v:133: verilog/inc1.v:133: verilog/inc1.v:138: verilog/inc1.v:139: COMMENT: // parameterized macro with arguments that are macros verilog/inc1.v:139: /*CMT*/ verilog/inc1.v:140: verilog/inc1.v:141: verilog/inc1.v:142: verilog/inc1.v:143: verilog/inc1.v:144: DS_ verilog/inc1.v:144: `line 144 "verilog/inc1.v" 0 verilog/inc1.v:144: generate for (i=0; i<(3); i=i+1) begin verilog/inc1.v:144: `line 144 "verilog/inc1.v" 0 verilog/inc1.v:144: psl cover { DS_DS_m5k.f .ctl._ctl_mvldx_m1.d[i] & ~DS_DS_m5k.f .ctl._ctl_mvldx_m1.q[i] & !DS_DS_m5k.f .ctl._ctl_mvldx_m1.cond & (DS_(DS_DS_m5k.f .ctl.alive & DS_DS_m5k.f .ctl.alive_m1))} report "fondNoRise: m5kc_fcl._ctl_mvldx_m1"; verilog/inc1.v:144: `line 144 "verilog/inc1.v" 0 verilog/inc1.v:144: psl cover { ~DS_DS_m5k.f .ctl._ctl_mvldx_m1.d[i] & DS_DS_m5k.f .ctl._ctl_mvldx_m1.q[i] & !DS_DS_m5k.f .ctl._ctl_mvldx_m1.cond & (DS_(DS_DS_m5k.f .ctl.alive & DS_DS_m5k.f .ctl.alive_m1))} report "fondNoFall: m5kc_fcl._ctl_mvldx_m1"; verilog/inc1.v:144: `line 144 "verilog/inc1.v" 0 verilog/inc1.v:144: COMMENT: // ignorecmt verilog/inc1.v:144: end endgenerate /*CMT*/ verilog/inc1.v:145: verilog/inc1.v:146: COMMENT: //====================================================================== verilog/inc1.v:146: /*CMT*/ verilog/inc1.v:147: COMMENT: // Quotes are legal in protected blocks. Grr. verilog/inc1.v:147: /*CMT*/ verilog/inc1.v:148: module prot(); verilog/inc1.v:149: `protected verilog/inc1.v:150: I!#r#e6<_Q{{E2+]I3<[3s)1@D|'E''i!O?]jD>Jo_![Cl) verilog/inc1.v:151: #nj1]p,3^1~,="E@QZB\T)eU\pC#C|7=\$J$##A[@-@{Qk] verilog/inc1.v:152: `endprotected verilog/inc1.v:153: endmodule verilog/inc1.v:154: verilog/inc1.v:155: module prot2(); verilog/inc1.v:156: `pragma protect begin_protected verilog/inc1.v:157: `pragma protect encrypt_agent = "Whatever agent" verilog/inc1.v:158: `pragma protect encrypt_agent_info = "1.2.3" verilog/inc1.v:159: `pragma protect data_method = "aes128-cbc" verilog/inc1.v:160: `pragma protect key_keyowner = "Someone" verilog/inc1.v:161: `pragma protect key_keyname = "somekey", key_method = "rsa" verilog/inc1.v:162: `pragma protect key_block encoding = (enctype = "base64") verilog/inc1.v:163: wefjosdfjklajklasjkl verilog/inc1.v:164: `pragma protect data_block encoding = (enctype = "base64", bytes = 1059) verilog/inc1.v:165: I!#r#e6<_Q{{E2+]I3<[3s)1@D|'E''i!O?]jD>Jo_![Cl) verilog/inc1.v:166: #nj1]p,3^1~,="E@QZB\T)eU\pC#C|7=\$J$##A[@-@{Qk] verilog/inc1.v:167: `pragma protect end_protected verilog/inc1.v:168: `pragma reset protect verilog/inc1.v:169: endmodule verilog/inc1.v:170: verilog/inc1.v:171: module prot3(); verilog/inc1.v:172: //pragma protect begin_protected verilog/inc1.v:173: //pragma protect key_keyowner=Cadence Design Systems. verilog/inc1.v:174: //pragma protect key_keyname=CDS_KEY verilog/inc1.v:175: //pragma protect key_method=RC5 verilog/inc1.v:176: //pragma protect key_block verilog/inc1.v:177: zzZzZ/4ZzzZZZzzz4zZzZzZZZZzZzZ/Zz+33zZ2zz/zzzzzzzzZZZzZ4z+ZZZZz1 verilog/inc1.v:178: Z1ZzzzZZzZZzz9ZZZZ37zzZzZzZzzz9ZZzzZzZz9Zz64+z8Z7ZzZZZzzzzZZZzZz verilog/inc1.v:179: zzZzZZZzZ0463zzzzzZzZ6z00z4zZzzZZzzZzzzZZ8zzz09ZzZZZZZ== verilog/inc1.v:180: //pragma protect end_key_block verilog/inc1.v:181: //pragma protect digest_block verilog/inc1.v:182: ZzZZzzZ9ZZZZz2ZzzzZz/Zzzz8Z= verilog/inc1.v:183: //pragma protect end_digest_block verilog/inc1.v:184: //pragma protect data_block verilog/inc1.v:185: ZZZ8zZzz6ZZ/zZZ5zZZzzz3ZzzzZzZZZ6ZzZzZZZZZz1zzZZZZ7ZZZZz3Zzz+9zz verilog/inc1.v:186: 4zzz+8zZzzzzZzZZzzzZzz1Z7ZzZz+zZz8ZZZZzZ6ZzzZzZZzzZZzzZzzZzZzZzZ verilog/inc1.v:187: ZzzzzZ0zZz1ZzzZzzZzZzz== verilog/inc1.v:188: //pragma protect end_data_block verilog/inc1.v:189: //pragma protect digest_block verilog/inc1.v:190: Z4Z6zZzZ3Z7ZZ6zzZZZZzzzzZZZ= verilog/inc1.v:191: //pragma protect end_digest_block verilog/inc1.v:192: //pragma protect end_protected verilog/inc1.v:193: endmodule verilog/inc1.v:194: verilog/inc1.v:195: COMMENT: //====================================================================== verilog/inc1.v:195: /*CMT*/ verilog/inc1.v:196: COMMENT: // macro call with define that has comma verilog/inc1.v:196: /*CMT*/ verilog/inc1.v:197: verilog/inc1.v:198: verilog/inc1.v:199: verilog/inc1.v:200: verilog/inc1.v:201: verilog/inc1.v:202: verilog/inc1.v:203: verilog/inc1.v:204: verilog/inc1.v:205: DS_begin addr <= ((DS_{DS_regs[DS_6], DS_regs[DS_7]} + 1)); rd <= 1; end and DS_begin addr <= ((DS_{DS_regs[DS_6], DS_regs[DS_7]})); wdata <= (rdata); wr <= 1; end verilog/inc1.v:206: DS_begin addr <= (DS_{DS_regs[DS_6], DS_regs[DS_7]} + 1); rd <= 1; end verilog/inc1.v:207: DS_begin addr <= (DS_{DS_regs[DS_6], DS_regs[DS_7]}); wdata <= (rdata); wr <= 1; end more verilog/inc1.v:208: verilog/inc1.v:209: COMMENT: //====================================================================== verilog/inc1.v:209: /*CMT*/ verilog/inc1.v:210: COMMENT: // include of parameterized file verilog/inc1.v:210: /*CMT*/ verilog/inc1.v:211: verilog/inc1.v:212: verilog/inc1.v:212: `line 212 "verilog/inc1.v" 0 verilog/inc1.v:212: `line 1 "verilog/t_preproc_inc4.vh" 1 verilog/t_preproc_inc4.vh:1: COMMENT: // DESCRIPTION: Verilog::Preproc: Example source code verilog/t_preproc_inc4.vh:1: /*CMT*/ verilog/t_preproc_inc4.vh:2: COMMENT: // This file ONLY is placed into the Public Domain, for any use, verilog/t_preproc_inc4.vh:2: `line 2 "verilog/t_preproc_inc4.vh" 0 verilog/t_preproc_inc4.vh:2: /*CMT*/ verilog/t_preproc_inc4.vh:3: COMMENT: // without warranty, 2000-2012 by Wilson Snyder. verilog/t_preproc_inc4.vh:3: /*CMT*/ verilog/t_preproc_inc4.vh:4: verilog/t_preproc_inc4.vh:5: verilog/t_preproc_inc4.vh:6: verilog/t_preproc_inc4.vh:7: `line 7 "verilog/t_preproc_inc4.vh" 2 verilog/inc1.v:212: `line 212 "verilog/inc1.v" 0 verilog/inc1.v:212: verilog/inc1.v:213: verilog/inc1.v:214: verilog/inc1.v:215: verilog/inc1.v:216: verilog/inc1.v:217: verilog/inc1.v:218: verilog/inc1.v:219: verilog/inc1.v:220: verilog/inc1.v:221: verilog/inc1.v:222: COMMENT: //====================================================================== verilog/inc1.v:222: /*CMT*/ verilog/inc1.v:223: COMMENT: // macro call with , in {} verilog/inc1.v:223: /*CMT*/ verilog/inc1.v:224: verilog/inc1.v:225: verilog/inc1.v:226: DS_$blah("ab,cd","e,f"); verilog/inc1.v:227: DS_$blah(this.logfile,vec); verilog/inc1.v:228: DS_$blah(this.logfile,vec[1,2,3]); verilog/inc1.v:229: DS_$blah(this.logfile,{blah.name(), " is not foo"}); verilog/inc1.v:230: verilog/inc1.v:231: COMMENT: //====================================================================== verilog/inc1.v:231: /*CMT*/ verilog/inc1.v:232: COMMENT: // pragma/default net type verilog/inc1.v:232: /*CMT*/ verilog/inc1.v:233: verilog/inc1.v:234: `pragma foo = 1 verilog/inc1.v:235: `default_nettype none verilog/inc1.v:236: `default_nettype uwire verilog/inc1.v:237: verilog/inc1.v:238: COMMENT: //====================================================================== verilog/inc1.v:238: /*CMT*/ verilog/inc1.v:239: COMMENT: // Ifdef verilog/inc1.v:239: /*CMT*/ verilog/inc1.v:240: verilog/inc1.v:241: verilog/inc1.v:242: verilog/inc1.v:243: verilog/inc1.v:244: verilog/inc1.v:245: Line_Preproc_Check 245 verilog/inc1.v:246: verilog/inc1.v:247: COMMENT: //====================================================================== verilog/inc1.v:247: /*CMT*/ verilog/inc1.v:248: COMMENT: // bug84 verilog/inc1.v:248: /*CMT*/ verilog/inc1.v:249: verilog/inc1.v:250: COMMENT: // Hello, comments MIGHT not be legal verilog/inc1.v:250: COMMENT: /*more,,)cmts*/ verilog/inc1.v:251: COMMENT: // But newlines ARE legal... who speced THAT? verilog/inc1.v:252: /*CMT*/ /*CMT*/ /*CMT*/ verilog/inc1.v:252: verilog/inc1.v:252: verilog/inc1.v:253: DS_(p,q) verilog/inc1.v:254: COMMENT: //Here verilog/inc1.v:254: verilog/inc1.v:255: verilog/inc1.v:256: COMMENT: //Too verilog/inc1.v:256: verilog/inc1.v:257: COMMENT: /*CMT*/ verilog/inc1.v:257: COMMENT: /*CMT*/ verilog/inc1.v:257: DS_( /*CMT*/ x,y /*CMT*/ ) verilog/inc1.v:258: Line_Preproc_Check 258 verilog/inc1.v:259: verilog/inc1.v:260: COMMENT: //====================================================================== verilog/inc1.v:260: /*CMT*/ verilog/inc1.v:261: COMMENT: // defines split arguments verilog/inc1.v:261: /*CMT*/ verilog/inc1.v:262: verilog/inc1.v:263: verilog/inc1.v:264: verilog/inc1.v:265: verilog/inc1.v:266: verilog/inc1.v:267: COMMENT: // 2001 spec doesn't require two tokens, so "beginend" ok verilog/inc1.v:267: DS_beginDS_end /*CMT*/ verilog/inc1.v:268: COMMENT: // 2001 spec doesn't require two tokens, so "beginend" ok verilog/inc1.v:268: DS_DS_beginDS_end /*CMT*/ verilog/inc1.v:269: COMMENT: // No space "beginend" verilog/inc1.v:269: DS_"DS_beginDS_end" /*CMT*/ verilog/inc1.v:270: verilog/inc1.v:271: COMMENT: //====================================================================== verilog/inc1.v:271: /*CMT*/ verilog/inc1.v:272: COMMENT: // bug106 verilog/inc1.v:272: /*CMT*/ verilog/inc1.v:273: verilog/inc1.v:274: verilog/inc1.v:275: `\esc`def verilog/inc1.v:276: verilog/inc1.v:277: Not a \`define verilog/inc1.v:278: verilog/inc1.v:279: COMMENT: //====================================================================== verilog/inc1.v:279: /*CMT*/ verilog/inc1.v:280: COMMENT: // misparsed comma in submacro verilog/inc1.v:280: /*CMT*/ verilog/inc1.v:281: verilog/inc1.v:282: verilog/inc1.v:283: verilog/inc1.v:284: verilog/inc1.v:285: DS_DS_x,y)--DS_bee submacro has comma paren verilog/inc1.v:286: verilog/inc1.v:287: COMMENT: //====================================================================== verilog/inc1.v:287: /*CMT*/ verilog/inc1.v:288: COMMENT: // bug191 verilog/inc1.v:288: /*CMT*/ verilog/inc1.v:289: verilog/inc1.v:290: DS_$display("10 %d %d", $bits(foo), 10); verilog/inc1.v:291: verilog/inc1.v:292: COMMENT: //====================================================================== verilog/inc1.v:292: /*CMT*/ verilog/inc1.v:293: COMMENT: // 1800-2009 verilog/inc1.v:293: /*CMT*/ verilog/inc1.v:294: verilog/inc1.v:295: verilog/inc1.v:296: verilog/inc1.v:297: verilog/inc1.v:298: verilog/inc1.v:299: verilog/inc1.v:300: COMMENT: //====================================================================== verilog/inc1.v:300: /*CMT*/ verilog/inc1.v:301: COMMENT: // bug202 verilog/inc1.v:301: /*CMT*/ verilog/inc1.v:302: verilog/inc1.v:302: verilog/inc1.v:302: verilog/inc1.v:302: verilog/inc1.v:302: verilog/inc1.v:302: verilog/inc1.v:302: verilog/inc1.v:302: verilog/inc1.v:302: verilog/inc1.v:302: verilog/inc1.v:302: verilog/inc1.v:313: verilog/inc1.v:314: DS_ verilog/inc1.v:314: `line 314 "verilog/inc1.v" 0 verilog/inc1.v:314: verilog/inc1.v:314: `line 314 "verilog/inc1.v" 0 verilog/inc1.v:314: verilog/inc1.v:314: `line 314 "verilog/inc1.v" 0 verilog/inc1.v:314: verilog/inc1.v:314: `line 314 "verilog/inc1.v" 0 verilog/inc1.v:314: verilog/inc1.v:314: `line 314 "verilog/inc1.v" 0 verilog/inc1.v:314: verilog/inc1.v:314: `line 314 "verilog/inc1.v" 0 verilog/inc1.v:314: verilog/inc1.v:314: `line 314 "verilog/inc1.v" 0 verilog/inc1.v:314: verilog/inc1.v:314: `line 314 "verilog/inc1.v" 0 verilog/inc1.v:314: verilog/inc1.v:314: `line 314 "verilog/inc1.v" 0 verilog/inc1.v:314: assign a3 = ~b3 ; verilog/inc1.v:314: `line 314 "verilog/inc1.v" 0 verilog/inc1.v:314: verilog/inc1.v:315: verilog/inc1.v:316: COMMENT: /* multi \ line1*/ verilog/inc1.v:316: verilog/inc1.v:316: `line 316 "verilog/inc1.v" 0 verilog/inc1.v:317: /*CMT*/ \ verilog/inc1.v:318: verilog/inc1.v:318: COMMENT: /*multi \ line2*/ verilog/inc1.v:318: verilog/inc1.v:318: `line 318 "verilog/inc1.v" 0 verilog/inc1.v:320: /*CMT*/ verilog/inc1.v:320: verilog/inc1.v:320: verilog/inc1.v:320: verilog/inc1.v:320: verilog/inc1.v:320: verilog/inc1.v:325: verilog/inc1.v:325: DS_ verilog/inc1.v:325: `line 325 "verilog/inc1.v" 0 verilog/inc1.v:325: COMMENT: /* multi line 3*/ verilog/inc1.v:325: verilog/inc1.v:325: `line 325 "verilog/inc1.v" 0 verilog/inc1.v:325: /*CMT*/ verilog/inc1.v:325: `line 325 "verilog/inc1.v" 0 verilog/inc1.v:325: def i verilog/inc1.v:325: `line 325 "verilog/inc1.v" 0 verilog/inc1.v:325: verilog/inc1.v:326: verilog/inc1.v:327: COMMENT: //====================================================================== verilog/inc1.v:327: /*CMT*/ verilog/inc1.v:328: verilog/inc1.v:329: COMMENT: // verilator NOT IN DEFINE verilog/inc1.v:329: verilog/inc1.v:330: verilog/inc1.v:331: COMMENT: /* verilator NOT PART OF DEFINE */ verilog/inc1.v:331: verilog/inc1.v:332: verilog/inc1.v:333: verilog/inc1.v:333: verilog/inc1.v:335: COMMENT: // CMT NOT verilog/inc1.v:337: verilog/inc1.v:337: verilog/inc1.v:337: verilog/inc1.v:338: verilog/inc1.v:339: COMMENT: /*CMT*/ verilog/inc1.v:339: 1 DS_ /*CMT*/ (nodef) verilog/inc1.v:340: COMMENT: /* verilator PART OF DEFINE */ verilog/inc1.v:340: 2 DS_ /*CMT*/ (hasdef) verilog/inc1.v:341: COMMENT: /*CMT*/ verilog/inc1.v:341: 3 DS_ /*CMT*/ (nodef) verilog/inc1.v:342: COMMENT: /* verilator PART OF DEFINE */ verilog/inc1.v:342: 4 DS_ verilog/inc1.v:342: `line 342 "verilog/inc1.v" 0 verilog/inc1.v:342: /*CMT*/ (nodef) verilog/inc1.v:343: 5 DS_also in verilog/inc1.v:343: `line 343 "verilog/inc1.v" 0 verilog/inc1.v:343: COMMENT: /*CMT*/ verilog/inc1.v:343: also3 /*CMT*/ (nodef) verilog/inc1.v:344: verilog/inc1.v:344: verilog/inc1.v:346: DS_HAS a NEW verilog/inc1.v:346: `line 346 "verilog/inc1.v" 0 verilog/inc1.v:346: LINE verilog/inc1.v:347: verilog/inc1.v:348: COMMENT: //====================================================================== verilog/inc1.v:348: /*CMT*/ verilog/inc1.v:349: verilog/inc1.v:350: verilog/inc1.v:350: verilog/inc1.v:350: verilog/inc1.v:350: verilog/inc1.v:350: verilog/inc1.v:350: verilog/inc1.v:350: verilog/inc1.v:350: verilog/inc1.v:350: verilog/inc1.v:350: verilog/inc1.v:350: verilog/inc1.v:350: verilog/inc1.v:362: verilog/inc1.v:363: verilog/inc1.v:364: verilog/inc1.v:365: verilog/inc1.v:366: EXP: clxx_scen verilog/inc1.v:367: DS_clxx_scen verilog/inc1.v:368: EXP: clxx_scen verilog/inc1.v:369: DS_"DS_clxx_scen" verilog/inc1.v:370: verilog/inc1.v:371: EXP: do if (start("verilog/inc1.v", 25)) begin message({"Blah-", "clx_scen", " end"}); end while(0); verilog/inc1.v:372: DS_DS_ verilog/inc1.v:372: `line 372 "verilog/inc1.v" 0 verilog/inc1.v:372: do verilog/inc1.v:372: `line 372 "verilog/inc1.v" 0 verilog/inc1.v:372: COMMENT: /* synopsys translate_off */ verilog/inc1.v:372: /*CMT*/ verilog/inc1.v:372: `line 372 "verilog/inc1.v" 0 verilog/inc1.v:372: verilog/inc1.v:372: `line 372 "verilog/inc1.v" 0 verilog/inc1.v:372: verilog/inc1.v:372: `line 372 "verilog/inc1.v" 0 verilog/inc1.v:372: verilog/inc1.v:372: `line 372 "verilog/inc1.v" 0 verilog/inc1.v:372: if (start("verilog/inc1.v", 372)) begin verilog/inc1.v:372: `line 372 "verilog/inc1.v" 0 verilog/inc1.v:372: verilog/inc1.v:372: `line 372 "verilog/inc1.v" 0 verilog/inc1.v:372: message({"Blah-", DS_"DS_clx_scen", " end"}); verilog/inc1.v:372: `line 372 "verilog/inc1.v" 0 verilog/inc1.v:372: end verilog/inc1.v:372: `line 372 "verilog/inc1.v" 0 verilog/inc1.v:372: COMMENT: /* synopsys translate_on */ verilog/inc1.v:372: /*CMT*/ verilog/inc1.v:372: `line 372 "verilog/inc1.v" 0 verilog/inc1.v:372: while(0); verilog/inc1.v:373: verilog/inc1.v:374: COMMENT: //====================================================================== verilog/inc1.v:374: /*CMT*/ verilog/inc1.v:375: verilog/inc1.v:376: verilog/inc1.v:376: verilog/inc1.v:376: verilog/inc1.v:376: verilog/inc1.v:380: DS_ verilog/inc1.v:380: `line 380 "verilog/inc1.v" 0 verilog/inc1.v:380: verilog/inc1.v:380: `line 380 "verilog/inc1.v" 0 verilog/inc1.v:380: verilog/inc1.v:380: `line 380 "verilog/inc1.v" 0 verilog/inc1.v:380: verilog/inc1.v:381: verilog/inc1.v:382: COMMENT: //`ifndef def_fooed_2 `error "No def_fooed_2" `endif verilog/inc1.v:382: /*CMT*/ verilog/inc1.v:383: EXP: This is fooed verilog/inc1.v:384: DS_This is fooed verilog/inc1.v:385: EXP: This is fooed_2 verilog/inc1.v:386: DS_This is fooed_2 verilog/inc1.v:387: verilog/inc1.v:388: COMMENT: //====================================================================== verilog/inc1.v:388: /*CMT*/ verilog/inc1.v:389: verilog/inc1.v:390: DS_np verilog/inc1.v:391: DS_np verilog/inc1.v:392: COMMENT: //====================================================================== verilog/inc1.v:392: /*CMT*/ verilog/inc1.v:393: COMMENT: // It's unclear if the spec allows this; is text_macro_idenitfier before or after substitution? verilog/inc1.v:393: /*CMT*/ verilog/inc1.v:394: verilog/inc1.v:395: verilog/inc1.v:396: verilog/inc1.v:397: verilog/inc1.v:398: verilog/inc1.v:399: verilog/inc1.v:400: verilog/inc1.v:401: verilog/inc1.v:402: COMMENT: //====================================================================== verilog/inc1.v:402: /*CMT*/ verilog/inc1.v:403: COMMENT: // Metaprogramming verilog/inc1.v:403: /*CMT*/ verilog/inc1.v:404: verilog/inc1.v:405: verilog/inc1.v:406: verilog/inc1.v:407: verilog/inc1.v:408: verilog/inc1.v:409: verilog/inc1.v:410: verilog/inc1.v:411: verilog/inc1.v:412: verilog/inc1.v:413: verilog/inc1.v:414: DS_DS_DS_DS_DS_hello3hello3hello3 verilog/inc1.v:415: DS_DS_DS_DS_DS_hello4hello4hello4hello4 verilog/inc1.v:416: COMMENT: //====================================================================== verilog/inc1.v:416: /*CMT*/ verilog/inc1.v:417: COMMENT: // Include from stringification verilog/inc1.v:417: /*CMT*/ verilog/inc1.v:418: verilog/inc1.v:419: verilog/inc1.v:420: verilog/inc1.v:420: `line 420 "verilog/inc1.v" 0 verilog/inc1.v:420: `line 1 "verilog/t_preproc_inc4.vh" 1 verilog/t_preproc_inc4.vh:1: COMMENT: // DESCRIPTION: Verilog::Preproc: Example source code verilog/t_preproc_inc4.vh:1: /*CMT*/ verilog/t_preproc_inc4.vh:2: COMMENT: // This file ONLY is placed into the Public Domain, for any use, verilog/t_preproc_inc4.vh:2: `line 2 "verilog/t_preproc_inc4.vh" 0 verilog/t_preproc_inc4.vh:2: /*CMT*/ verilog/t_preproc_inc4.vh:3: COMMENT: // without warranty, 2000-2012 by Wilson Snyder. verilog/t_preproc_inc4.vh:3: /*CMT*/ verilog/t_preproc_inc4.vh:4: verilog/t_preproc_inc4.vh:5: verilog/t_preproc_inc4.vh:6: verilog/t_preproc_inc4.vh:7: `line 7 "verilog/t_preproc_inc4.vh" 2 verilog/inc1.v:420: `line 420 "verilog/inc1.v" 0 verilog/inc1.v:420: verilog/inc1.v:421: verilog/inc1.v:422: COMMENT: //====================================================================== verilog/inc1.v:422: /*CMT*/ verilog/inc1.v:423: COMMENT: // Defines doing defines verilog/inc1.v:423: /*CMT*/ verilog/inc1.v:424: COMMENT: // Note the newline on the end - required to form the end of a define verilog/inc1.v:424: /*CMT*/ verilog/inc1.v:425: verilog/inc1.v:425: verilog/inc1.v:427: verilog/inc1.v:428: verilog/inc1.v:429: DS_ DS_ verilog/inc1.v:429: `line 429 "verilog/inc1.v" 0 verilog/inc1.v:429: verilog/inc1.v:430: verilog/inc1.v:431: DS_ verilog/inc1.v:432: verilog/inc1.v:433: Line_Preproc_Check 433 verilog/inc1.v:434: COMMENT: //====================================================================== verilog/inc1.v:434: /*CMT*/ verilog/inc1.v:435: COMMENT: // Quoted multiline - track line numbers, and insure \\n gets propagated verilog/inc1.v:435: /*CMT*/ verilog/inc1.v:436: verilog/inc1.v:436: verilog/inc1.v:438: verilog/inc1.v:439: Line_Preproc_Check 439 verilog/inc1.v:441: verilog/inc1.v:441: DS_DS_"FOO \ verilog/inc1.v:441: BAR " "arg_line1 \ verilog/inc1.v:441: arg_line2" DS_"FOO \ verilog/inc1.v:441: BAR " verilog/inc1.v:442: `line 442 "verilog/inc1.v" 0 verilog/inc1.v:442: Line_Preproc_Check 442 verilog/inc1.v:443: COMMENT: //====================================================================== verilog/inc1.v:443: /*CMT*/ verilog/inc1.v:444: COMMENT: // bug283 verilog/inc1.v:444: /*CMT*/ verilog/inc1.v:445: verilog/inc1.v:446: verilog/inc1.v:447: verilog/inc1.v:448: verilog/inc1.v:449: COMMENT: // EXP: abc verilog/inc1.v:449: /*CMT*/ verilog/inc1.v:450: verilog/inc1.v:451: DS_DS_abDS_c verilog/inc1.v:452: verilog/inc1.v:453: verilog/inc1.v:454: verilog/inc1.v:455: verilog/inc1.v:456: verilog/inc1.v:457: verilog/inc1.v:458: verilog/inc1.v:459: EXP: sonet_frame verilog/inc1.v:460: DS_DS_DS_sonet_frame verilog/inc1.v:461: COMMENT: // verilog/inc1.v:461: /*CMT*/ verilog/inc1.v:462: verilog/inc1.v:463: verilog/inc1.v:464: EXP: sonet_frame verilog/inc1.v:465: DS_DS_sonet_DS_frame verilog/inc1.v:466: COMMENT: // This result varies between simulators verilog/inc1.v:466: /*CMT*/ verilog/inc1.v:467: verilog/inc1.v:468: verilog/inc1.v:469: EXP: sonet_frame verilog/inc1.v:470: DS_DS_sonet_frame verilog/inc1.v:471: verilog/inc1.v:472: COMMENT: // The existance of non-existance of a base define can make a difference verilog/inc1.v:472: /*CMT*/ verilog/inc1.v:473: verilog/inc1.v:474: verilog/inc1.v:475: EXP: module zzz ; endmodule verilog/inc1.v:476: module DS_DS_zzz ; endmodule verilog/inc1.v:477: module DS_DS_zzz ; endmodule verilog/inc1.v:478: verilog/inc1.v:479: verilog/inc1.v:480: EXP: module a_b ; endmodule verilog/inc1.v:481: module DS_DS_a_b ; endmodule verilog/inc1.v:482: module DS_DS_a_b ; endmodule verilog/inc1.v:483: verilog/inc1.v:484: COMMENT: //====================================================================== verilog/inc1.v:484: /*CMT*/ verilog/inc1.v:485: COMMENT: // bug311 verilog/inc1.v:485: /*CMT*/ verilog/inc1.v:486: COMMENT: /*NEED_SPACE*/ verilog/inc1.v:486: integer /*CMT*/ foo; verilog/inc1.v:487: COMMENT: //====================================================================== verilog/inc1.v:487: /*CMT*/ verilog/inc1.v:488: synth_test: verilog/inc1.v:489: COMMENT: // synopsys translate_off verilog/inc1.v:489: /*CMT*/ verilog/inc1.v:490: synthesis_turned_off verilog/inc1.v:491: COMMENT: // synthesis translate_on verilog/inc1.v:491: /*CMT*/ verilog/inc1.v:492: EXP: on verilog/inc1.v:493: COMMENT: //====================================================================== verilog/inc1.v:493: /*CMT*/ verilog/inc1.v:494: COMMENT: // bug441 verilog/inc1.v:494: /*CMT*/ verilog/inc1.v:495: module t; verilog/inc1.v:496: COMMENT: //----- verilog/inc1.v:496: /*CMT*/ verilog/inc1.v:497: COMMENT: // case provided verilog/inc1.v:497: /*CMT*/ verilog/inc1.v:498: COMMENT: // note this does NOT escape as suggested in the mail verilog/inc1.v:498: /*CMT*/ verilog/inc1.v:499: verilog/inc1.v:500: verilog/inc1.v:500: verilog/inc1.v:502: initial begin : DS_\`LEX_CAT(a[0],_assignment) verilog/inc1.v:502: `line 502 "verilog/inc1.v" 0 verilog/inc1.v:502: $write("GOT%%m='%m' EXP='%s'\n", "t.\\`LEX_CAT(a[0],_assignment) "); end verilog/inc1.v:503: COMMENT: //----- verilog/inc1.v:503: /*CMT*/ verilog/inc1.v:504: COMMENT: // SHOULD(simulator-dependant): Backslash doesn't prevent arguments from verilog/inc1.v:504: /*CMT*/ verilog/inc1.v:505: COMMENT: // substituting and the \ staying in the expansion verilog/inc1.v:505: /*CMT*/ verilog/inc1.v:506: COMMENT: // Note space after name is important so when substitute it has ending whitespace verilog/inc1.v:506: /*CMT*/ verilog/inc1.v:507: verilog/inc1.v:507: verilog/inc1.v:509: initial begin : DS_\a[0]_assignment_a[1] verilog/inc1.v:509: `line 509 "verilog/inc1.v" 0 verilog/inc1.v:509: $write("GOT%%m='%m' EXP='%s'\n", "t.\\a[0]_assignment_a[1] "); end verilog/inc1.v:510: verilog/inc1.v:511: COMMENT: //----- verilog/inc1.v:511: /*CMT*/ verilog/inc1.v:512: verilog/inc1.v:513: verilog/inc1.v:514: COMMENT: // RULE: Ignoring backslash does NOT allow an additional expansion level verilog/inc1.v:514: /*CMT*/ verilog/inc1.v:515: COMMENT: // (Because ESC gets expanded then the \ has it's normal escape meaning) verilog/inc1.v:515: /*CMT*/ verilog/inc1.v:516: initial begin : DS_\`CAT(pp,suffix) $write("GOT%%m='%m' EXP='%s'\n", "t.\\`CAT(pp,suffix) "); end verilog/inc1.v:517: verilog/inc1.v:518: COMMENT: //----- verilog/inc1.v:518: /*CMT*/ verilog/inc1.v:519: verilog/inc1.v:520: verilog/inc1.v:520: verilog/inc1.v:522: COMMENT: // Similar to above; \ does not allow expansion after substitution verilog/inc1.v:522: /*CMT*/ verilog/inc1.v:523: initial begin : DS_\`CAT(ff,bb) verilog/inc1.v:523: `line 523 "verilog/inc1.v" 0 verilog/inc1.v:523: $write("GOT%%m='%m' EXP='%s'\n", "t.\\`CAT(ff,bb) "); end verilog/inc1.v:524: verilog/inc1.v:525: COMMENT: //----- verilog/inc1.v:525: /*CMT*/ verilog/inc1.v:526: verilog/inc1.v:526: verilog/inc1.v:528: COMMENT: // MUST: Unknown macro with backslash escape stays as escaped symbol name verilog/inc1.v:528: /*CMT*/ verilog/inc1.v:529: initial begin : DS_\`zzz verilog/inc1.v:529: `line 529 "verilog/inc1.v" 0 verilog/inc1.v:529: $write("GOT%%m='%m' EXP='%s'\n", "t.\\`zzz "); end verilog/inc1.v:530: verilog/inc1.v:531: COMMENT: //----- verilog/inc1.v:531: /*CMT*/ verilog/inc1.v:532: verilog/inc1.v:533: verilog/inc1.v:533: verilog/inc1.v:535: COMMENT: // SHOULD(simulator-dependant): Known macro with backslash escape expands verilog/inc1.v:535: /*CMT*/ verilog/inc1.v:536: initial begin : DS_\`FOO verilog/inc1.v:536: `line 536 "verilog/inc1.v" 0 verilog/inc1.v:536: $write("GOT%%m='%m' OTHER_EXP='%s'\n OUR_EXP='%s'", "t.bar ","t.\\`FOO "); end verilog/inc1.v:537: COMMENT: // SHOULD(simulator-dependant): Prefix breaks the above verilog/inc1.v:537: /*CMT*/ verilog/inc1.v:538: initial begin : DS_\xx`FOO verilog/inc1.v:538: `line 538 "verilog/inc1.v" 0 verilog/inc1.v:538: $write("GOT%%m='%m' EXP='%s'\n", "t.\\xx`FOO "); end verilog/inc1.v:539: verilog/inc1.v:540: COMMENT: //----- verilog/inc1.v:540: /*CMT*/ verilog/inc1.v:541: COMMENT: // MUST: Unknown macro not under call with backslash escape doesn't expand verilog/inc1.v:541: /*CMT*/ verilog/inc1.v:542: verilog/inc1.v:543: initial begin : \`UNKNOWN $write("GOT%%m='%m' EXP='%s'\n", "t.\\`UNKNOWN "); end verilog/inc1.v:544: COMMENT: //----- verilog/inc1.v:544: /*CMT*/ verilog/inc1.v:545: COMMENT: // MUST: Unknown macro not under call doesn't expand verilog/inc1.v:545: /*CMT*/ verilog/inc1.v:546: verilog/inc1.v:547: initial begin : \`DEF_NO_EXPAND $write("GOT%%m='%m' EXP='%s'\n", "t.\\`DEF_NO_EXPAND "); end verilog/inc1.v:548: verilog/inc1.v:549: COMMENT: //----- verilog/inc1.v:549: /*CMT*/ verilog/inc1.v:550: COMMENT: // bug441 derivative verilog/inc1.v:550: /*CMT*/ verilog/inc1.v:551: COMMENT: // SHOULD(simulator-dependant): Quotes doesn't prevent arguments from expanding (like backslashes above) verilog/inc1.v:551: /*CMT*/ verilog/inc1.v:552: verilog/inc1.v:553: initial $write("GOT='%s' EXP='%s'\n", "foo bar baz", "foo bar baz"); verilog/inc1.v:554: verilog/inc1.v:555: COMMENT: //----- verilog/inc1.v:555: /*CMT*/ verilog/inc1.v:556: COMMENT: // RULE: Because there are quotes after substituting STR, the `A does NOT expand verilog/inc1.v:556: /*CMT*/ verilog/inc1.v:557: verilog/inc1.v:558: verilog/inc1.v:559: initial $write("GOT='%s' EXP='%s'\n", "foo `A(bar) baz", "foo `A(bar) baz"); verilog/inc1.v:560: verilog/inc1.v:561: COMMENT: //---- verilog/inc1.v:561: /*CMT*/ verilog/inc1.v:562: COMMENT: // bug845 verilog/inc1.v:562: /*CMT*/ verilog/inc1.v:563: verilog/inc1.v:564: initial $write("Slashed=`%s'\n", "1//2.3"); verilog/inc1.v:565: COMMENT: //---- verilog/inc1.v:565: /*CMT*/ verilog/inc1.v:566: COMMENT: // bug915 verilog/inc1.v:566: /*CMT*/ verilog/inc1.v:567: verilog/inc1.v:567: verilog/inc1.v:569: initial DS_ verilog/inc1.v:569: `line 569 "verilog/inc1.v" 0 verilog/inc1.v:569: $display("%s%s","a1","b2c3\n"); verilog/inc1.v:570: endmodule verilog/inc1.v:571: verilog/inc1.v:572: COMMENT: //====================================================================== verilog/inc1.v:572: /*CMT*/ verilog/inc1.v:573: COMMENT: //bug1225 verilog/inc1.v:573: /*CMT*/ verilog/inc1.v:574: verilog/inc1.v:575: verilog/inc1.v:576: verilog/inc1.v:577: $display(DS_DS_"RAM0"); verilog/inc1.v:578: $display(DS_DS_"CPU"); verilog/inc1.v:579: verilog/inc1.v:580: verilog/inc1.v:581: verilog/inc1.v:582: verilog/inc1.v:583: verilog/inc1.v:584: verilog/inc1.v:585: verilog/inc1.v:586: XXE_FAMILY = DS_XXE_DS_ verilog/inc1.v:587: verilog/inc1.v:588: verilog/inc1.v:589: verilog/inc1.v:590: verilog/inc1.v:591: verilog/inc1.v:592: verilog/inc1.v:593: XYE_FAMILY = DS_XYE_DS_ verilog/inc1.v:594: verilog/inc1.v:595: verilog/inc1.v:596: verilog/inc1.v:597: verilog/inc1.v:598: verilog/inc1.v:599: verilog/inc1.v:600: XXS_FAMILY = DS_XXS_DS_some verilog/inc1.v:601: verilog/inc1.v:602: verilog/inc1.v:603: verilog/inc1.v:604: verilog/inc1.v:605: verilog/inc1.v:606: verilog/inc1.v:607: XYS_FAMILY = DS_XYS_DS_foo verilog/inc1.v:608: verilog/inc1.v:609: verilog/inc1.v:610: verilog/inc1.v:611: verilog/inc1.v:612: verilog/inc1.v:613: COMMENT: //==== verilog/inc1.v:613: /*CMT*/ verilog/inc1.v:614: verilog/inc1.v:615: verilog/inc1.v:616: verilog/inc1.v:617: verilog/inc1.v:618: verilog/inc1.v:619: verilog/inc1.v:620: verilog/inc1.v:621: verilog/inc1.v:622: verilog/inc1.v:623: verilog/inc1.v:624: verilog/inc1.v:625: verilog/inc1.v:626: verilog/inc1.v:627: verilog/inc1.v:628: verilog/inc1.v:629: verilog/inc1.v:630: verilog/inc1.v:631: verilog/inc1.v:632: verilog/inc1.v:633: verilog/inc1.v:634: verilog/inc1.v:635: verilog/inc1.v:636: verilog/inc1.v:637: verilog/inc1.v:638: verilog/inc1.v:639: verilog/inc1.v:640: verilog/inc1.v:641: verilog/inc1.v:642: verilog/inc1.v:643: verilog/inc1.v:644: verilog/inc1.v:645: verilog/inc1.v:646: COMMENT: // NEVER verilog/inc1.v:646: /*CMT*/ verilog/inc1.v:647: verilog/inc1.v:648: COMMENT: //bug1227 verilog/inc1.v:648: /*CMT*/ verilog/inc1.v:649: verilog/inc1.v:650: DS_(.mySig (myInterface.pa5), verilog/inc1.v:651: verilog/inc1.v:652: COMMENT: //====================================================================== verilog/inc1.v:652: /*CMT*/ verilog/inc1.v:653: COMMENT: // Stringify bug verilog/inc1.v:653: /*CMT*/ verilog/inc1.v:654: verilog/inc1.v:655: verilog/inc1.v:656: DS_`dbg_hdl(UVM_LOW, ("Functional coverage enabled: paramgrp")); verilog/inc1.v:657: verilog/inc1.v:658: verilog/inc1.v:659: verilog/inc1.v:659: verilog/inc1.v:661: verilog/inc1.v:661: verilog/inc1.v:661: verilog/inc1.v:661: verilog/inc1.v:665: verilog/inc1.v:666: module pcc2_cfg; verilog/inc1.v:667: generate verilog/inc1.v:668: DS_ verilog/inc1.v:668: `line 668 "verilog/inc1.v" 0 verilog/inc1.v:668: covergroup a @(posedge b); verilog/inc1.v:668: `line 668 "verilog/inc1.v" 0 verilog/inc1.v:668: c: coverpoint d iff ((c) === 1'b1); endgroup verilog/inc1.v:668: `line 668 "verilog/inc1.v" 0 verilog/inc1.v:668: a u_a; DS_ verilog/inc1.v:668: `line 668 "verilog/inc1.v" 0 verilog/inc1.v:668: initial do begin DS_$display ("DEBUG : %s [%m]", $sformatf ("Functional coverage enabled: u_a")); end while(0); verilog/inc1.v:669: endgenerate verilog/inc1.v:670: endmodule verilog/inc1.v:671: verilog/inc1.v:672: COMMENT: //====================================================================== verilog/inc1.v:672: /*CMT*/ verilog/inc1.v:673: COMMENT: // Verilog-Perl bug1668 verilog/inc1.v:673: /*CMT*/ verilog/inc1.v:674: verilog/inc1.v:675: DS_"`NOT_DEFINED_STR" verilog/inc1.v:676: verilog/inc1.v:677: COMMENT: //====================================================================== verilog/inc1.v:677: /*CMT*/ verilog/inc1.v:678: COMMENT: // IEEE mandated predefines verilog/inc1.v:678: /*CMT*/ verilog/inc1.v:679: COMMENT: // undefineall should have no effect on these verilog/inc1.v:679: /*CMT*/ verilog/inc1.v:680: predef DS_0 0 verilog/inc1.v:681: predef DS_1 1 verilog/inc1.v:682: predef DS_2 2 verilog/inc1.v:683: predef DS_3 3 verilog/inc1.v:684: predef DS_10 10 verilog/inc1.v:685: predef DS_11 11 verilog/inc1.v:686: predef DS_20 20 verilog/inc1.v:687: predef DS_21 21 verilog/inc1.v:688: predef DS_22 22 verilog/inc1.v:689: predef DS_23 23 verilog/inc1.v:690: predef DS_-2 -2 verilog/inc1.v:691: predef DS_-1 -1 verilog/inc1.v:692: predef DS_0 0 verilog/inc1.v:693: predef DS_1 1 verilog/inc1.v:694: predef DS_2 2 verilog/inc1.v:695: verilog/inc1.v:696: `line 696 "verilog/inc1.v" 2 Verilog-Perl-3.482/t/56_editfiles.t0000755000177100017500000000274414553624300016742 0ustar wsnyderwsnyder#!/usr/bin/perl -w # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package # # Copyright 2007-2024 by Wilson Snyder. This program is free software; # you can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. use strict; use Test::More; use File::Copy; BEGIN { plan tests => 9 } BEGIN { require "./t/test_utils.pl"; } BEGIN { use Verilog::EditFiles; } ok(1); { #Editing my $split = Verilog::EditFiles->new(); ok(1, "new"); my $edfile = "test_dir/56_editfiles.v"; $split->edit_file (filename => "t/56_editfiles.v", write_filename => $edfile, cb=>sub { my $wholefile = shift; $wholefile =~ s%inside_module%replaced_inside_module%mg; return $wholefile; }); ok(1, "edit_file"); ok(files_identical($edfile, "t/56_editfiles_edit.out"), "diff"); } { unlink (glob("test_dir/editout/*.v")); my $split = Verilog::EditFiles->new (program => "56_editfiles.t", outdir => "test_dir/editout", translate_synthesis => 1, lint_header => "// lint_checking HEADER\n", celldefine => 1, ); $split->read_and_split(glob("t/56_editfiles.v")); ok(1, "read_and_split"); $split->write_files(); ok(1, "write_files"); ok(files_identical("test_dir/editout/a.v", "t/56_editfiles_a.out"), "diff"); ok(files_identical("test_dir/editout/b.v", "t/56_editfiles_b.out"), "diff"); $split->write_lint(); ok(1, "write_lint"); } Verilog-Perl-3.482/t/60_vpassert.t0000755000177100017500000001135214553624300016627 0ustar wsnyderwsnyder#!/usr/bin/perl -w # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package # # Copyright 2000-2024 by Wilson Snyder. This program is free software; # you can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. use IO::File; use strict; use Test::More; BEGIN { plan tests => 6 } BEGIN { require "./t/test_utils.pl"; } print "Checking vpassert...\n"; # Preprocess the files mkdir "test_dir/.vpassert", 0777; mkdir "test_dir/.vpassertcall", 0777; system ("/bin/rm -rf test_dir/verilog"); symlink ("../verilog", "test_dir/verilog"); # So `line files are found; ok if fails run_system ("${PERL} ./vpassert --minimum --nostop --date --axiom --verilator --vcs --synthcov" ." -o test_dir/.vpassert -y verilog/"); ok(1, "vpassert ran"); ok(-r 'test_dir/.vpassert/pli.v', "pli.v created"); ok(compare('lines', [glob("test_dir/.vpassert/*.v")]), "lines output"); ok(compare('diff', [glob("test_dir/.vpassert/*.v")]), "diff output"); # Preprocess with custom outputters run_system ("${PERL} ./vpassert --date --verilator --vcs" .q{ --call-error '$callError'} .q{ --call-info '$callInfo'} .q{ --call-warn '$callWarn'} ." -o test_dir/.vpassertcall -y verilog/"); ok(files_identical("test_dir/.vpassertcall/example.v", "t/60_vpassert.out"), "diff"); # Build the model unlink "simv"; chdir 'test_dir'; SKIP: { skip("author only test (harmless)",1) if (!$ENV{VERILATOR_AUTHOR_SITE}); if ($ENV{VCS_HOME} && -r "$ENV{VCS_HOME}/bin/vcs") { run_system (# We use VCS, insert your simulator here "$ENV{VCS_HOME}/bin/vcs" # check line coverage ." -cm line+assert" # vpassert optionally uses SystemVerilog coverage for $ucover_clk ." -sverilog" # vpassert uses `pli to point to the hierarchy of the pli module ." +define+pli=pli" # vpassert uses `__message_on to point to the message on variable ." +define+__message_on=pli.message_on" # vpassert --minimum uses `__message_minimum to optimize away some messages ." +define+__message_minimum=1" # Read files from .vpassert BEFORE reading from other directories ." +librescan +libext+.v -y .vpassert" # Finally, read the needed top level file ." .vpassert/example.v" ); # Execute the model (VCS is a compiled simulator) run_system ("./simv"); unlink ("./simv"); ok(1, "vcs sim"); } elsif ($ENV{NC_ROOT} && -d "$ENV{NC_ROOT}/tools") { run_system ("ncverilog" ." -q" # vpassert optionally uses SystemVerilog coverage for $ucover_clk ." +sv" # vpassert uses `pli to point to the hierarchy of the pli module ." +define+pli=pli" # vpassert uses `__message_on to point to the message on variable ." +define+__message_on=pli.message_on" # vpassert --minimum uses `__message_minimum to optimize away some messages ." +define+__message_minimum=1" # Read files from .vpassert BEFORE reading from other directories ." +librescan +libext+.v -y .vpassert" # Finally, read the needed top level file ." .vpassert/example.v" ); ok(1, "ncv sim"); } else { warn "\n"; warn "*** You do not seem to have VCS or NC-Verilog installed, not running rest of test.\n"; warn "*** (If you do not license VCS/NC-Verilog, ignore this warning).\n"; skip("No simulator found",1); } } chdir '..'; sub lines_in { my $filename = shift; my $fh = IO::File->new($filename) or die "%Error: $! $filename"; my @lines = $fh->getlines(); @lines = grep (!/\`line/, @lines); return $#lines; } sub compare { my $mode = shift; my $files = shift; my $ok = 1; file: foreach my $file (@{$files}) { $file =~ s!.*/!!; # SPECIAL FILES we processed! next if $file eq 'example.v'; next if $file eq 'pli.v'; my $fn1 = "verilog/$file"; my $fn2 = "test_dir/.vpassert/$file"; if ($mode eq 'lines') { my $orig_lines = lines_in($fn1); my $new_lines = lines_in($fn2); if ($orig_lines!=$new_lines) { $ok=0; print "%Error: "; } print "Line count: $file: $orig_lines =? $new_lines\n"; } elsif ($mode eq 'diff') { my $f1 = IO::File->new ($fn1) or die "%Error: $! $fn1,"; my $f2 = IO::File->new ($fn2) or die "%Error: $! $fn2,"; my @l1 = $f1->getlines(); my @l2 = $f2->getlines(); @l1 = grep (!/`line/, @l1); @l2 = grep (!/`line/, @l2); my $nl = $#l1; $nl = $#l2 if ($#l2 > $nl); for (my $l=0; $l<=$nl; $l++) { next if $l2[$l] =~ /vpassert/; if (($l1[$l]||"") ne ($l2[$l]||"")) { warn ("%Warning: Line ".($l+1)." mismatches; diff $fn1 $fn2\n" ."F1: ".($l1[$l]||"*EOF*\n") ."F2: ".($l2[$l]||"*EOF*\n")); $ok = 0; next file; } } } else { die; } } return $ok; } Verilog-Perl-3.482/t/42_dumpcheck_2.out0000644000177100017500000000735013234726611017513 0ustar wsnyderwsnyderModule:bug278 Kwd:module File:verilog/pinorder.v Port:iow Dir:inout DataT: Array: Port:iw Dir:in DataT: Array: Port:ow Dir:out DataT: Array: Net:iow DeclT:port NetT:wire DataT: Array: Net:iw O DeclT:port NetT:wire DataT: Array: Net:ow I DeclT:port NetT:wire DataT: Array: Module:foo Kwd:module File:verilog/pinorder.v Port:abcconst Dir:in DataT:[2:0] Array: Port:def Dir:in DataT:[31:0] Array: Port:noconnect Dir:in DataT:signed [3:0] Array: Port:x Dir:in DataT: Array: Port:y Dir:in DataT: Array: Net:abcconst O DeclT:port NetT: DataT:[2:0] Array: 2:0 Net:def O DeclT:port NetT: DataT:[31:0] Array: 31:0 Net:noconnect O DeclT:port NetT: DataT:signed [3:0] Array: 3:0 Net:x O DeclT:port NetT: DataT: Array: Net:y O DeclT:port NetT: DataT: Array: Module:foo2 Kwd:module File:verilog/pinorder.v Port:x Dir:out DataT: Array: Port:y Dir:in DataT: Array: Port:z Dir:in DataT: Array: Net:x I DeclT:port NetT: DataT:reg Array: Net:y O DeclT:port NetT: DataT: Array: Net:z O DeclT:port NetT: DataT: Array: Module:pinorder4 Kwd:module File:verilog/pinorder.v Net:IPCD_const I DeclT:net NetT:wire DataT:[31:0] Array: 31:0 Value:32'h1 Net:a_i I DeclT:net NetT:wire DataT:[7:0] Array: 7:0 Net:b_i IO DeclT:net NetT:wire DataT: Array: Net:d_o I DeclT:net NetT:wire DataT: Array: Cell:foo1 is-a:foo Module:foo Kwd:module File:verilog/pinorder.v Pin:abcconst Net:3'h0 Port:abcconst Dir:in DataT:[2:0] Array: Pin:def Net:IPCD_const Port:def Dir:in DataT:[31:0] Array: Net:IPCD_const I DeclT:net NetT:wire DataT:[31:0] Array: 31:0 Value:32'h1 Pin:noconnect Net: Port:noconnect Dir:in DataT:signed [3:0] Array: Pin:x Net:a_i Port:x Dir:in DataT: Array: Net:a_i I DeclT:net NetT:wire DataT:[7:0] Array: 7:0 Pin:y Net:b_i Port:y Dir:in DataT: Array: Net:b_i IO DeclT:net NetT:wire DataT: Array: Cell:foo2 is-a:foo2 Module:foo2 Kwd:module File:verilog/pinorder.v Pin:x Net:b_i Port:x Dir:out DataT: Array: Net:b_i IO DeclT:net NetT:wire DataT: Array: Pin:y Net:d_o Port:y Dir:in DataT: Array: Net:d_o I DeclT:net NetT:wire DataT: Array: Pin:z Net:a_i[0] Port:z Dir:in DataT: Array: Cell:foo3 is-a:foo Module:foo Kwd:module File:verilog/pinorder.v Pin:abcconst Net:3'h0 Port:abcconst Dir:in DataT:[2:0] Array: Pin:def Net:IPCD_const Port:def Dir:in DataT:[31:0] Array: Net:IPCD_const I DeclT:net NetT:wire DataT:[31:0] Array: 31:0 Value:32'h1 Pin:x Net:a_i Port:x Dir:in DataT: Array: Net:a_i I DeclT:net NetT:wire DataT:[7:0] Array: 7:0 Pin:y Net:b_i Port:y Dir:in DataT: Array: Net:b_i IO DeclT:net NetT:wire DataT: Array: ContAssign:assign lhs:a_i rhs:0 ContAssign:assign lhs:b_i rhs:0 #### Commentary: verilog/pinorder.v:0049: iow cmt="" verilog/pinorder.v:0050: iw cmt="" verilog/pinorder.v:0048: ow cmt="" verilog/pinorder.v:0041: abcconst cmt="" verilog/pinorder.v:0043: def cmt="" verilog/pinorder.v:0042: noconnect cmt="" verilog/pinorder.v:0040: x cmt="" verilog/pinorder.v:0039: y cmt="" verilog/pinorder.v:0030: x cmt="" verilog/pinorder.v:0029: y cmt="" verilog/pinorder.v:0028: z cmt="" verilog/pinorder.v:0010: IPCD_const cmt="" verilog/pinorder.v:0009: a_i cmt="" verilog/pinorder.v:0007: b_i cmt="" verilog/pinorder.v:0008: d_o cmt="" Verilog-Perl-3.482/t/30_preproc_nows.out0000644000177100017500000004307214030463163020040 0ustar wsnyderwsnyderverilog/inc_nonl.v:1: `line 1 "verilog/inc1.v" 1 verilog/inc_nonl.v:1: `line 1 "verilog/inc1.v" 0 verilog/inc_nonl.v:1: `line 1 "verilog/inc2.v" 1 verilog/inc_nonl.v:1: `line 1 "verilog/inc2.v" 0 verilog/inc_nonl.v:1: `line 1 "verilog/inc_ifdef.v" 1 verilog/inc_nonl.v:1: `line 1 "verilog/inc_ifdef.v" 0 verilog/inc_nonl.v:1: `line 1 "verilog/inc_nonl.v" 1 verilog/inc_nonl.v:1: `line 1 "verilog/inc_nonl.v" 0 verilog/inc_nonl.v:1: `line 1 "verilog/inc_def09.v" 1 verilog/inc_def09.v:11: 'initial $display("start", "msg1" , "msg2", "end");' verilog/inc_def09.v:12: 'initial $display("start", "msg1" , "msg2" , "end");' verilog/inc_def09.v:13: 'initial $display("start", " msg1" , , "end");' verilog/inc_def09.v:14: 'initial $display("start", " msg1" , , "end");' verilog/inc_def09.v:15: 'initial $display("start", , "msg2 ", "end");' verilog/inc_def09.v:16: 'initial $display("start", , "msg2 ", "end");' verilog/inc_def09.v:17: 'initial $display("start", , , "end");' verilog/inc_def09.v:18: 'initial $display("start", , , "end");' verilog/inc_def09.v:19: 'initial $display("start", , , "end");' verilog/inc_def09.v:20: 'initial $display("start", , , "end");' verilog/inc_def09.v:27: '$display(5,,2,,3);' verilog/inc_def09.v:28: '$display(5,,2,,3);' verilog/inc_def09.v:29: '$display(1,,"B",,3);' verilog/inc_def09.v:30: '$display(1 ,,"B",,3 );' verilog/inc_def09.v:31: '$display(5,,2,,);' verilog/inc_def09.v:32: '$display(5,,2,,);' verilog/inc_def09.v:36: '$display(1,,,,3);' verilog/inc_def09.v:37: '$display(5,,,,"C");' verilog/inc_def09.v:38: '$display(5,,2,,"C");' verilog/inc_def09.v:39: '$display(5,,2,,"C");' verilog/inc_def09.v:40: '$display(5,,2,,"C");' verilog/inc_def09.v:41: '$display(5,,2,,"C");' verilog/inc_def09.v:44: '$display(1,,0,,"C");' verilog/inc_def09.v:45: '$display(1 ,,0,,"C");' verilog/inc_def09.v:46: '$display(5,,0,,"C");' verilog/inc_def09.v:47: '$display(5,,0,,"C");' verilog/inc_def09.v:51: 'b + 1 + 42 + a' verilog/inc_def09.v:52: 'b + 1 + 42 + a' verilog/inc_def09.v:56: '"==)" "((((" () '; verilog/inc_def09.v:57: '"==)" "((((" () '; verilog/inc_def09.v:70: '(6) (eq=al) ZOT' verilog/inc_def09.v:71: HERE-71 - Line71 verilog/inc_def09.v:75: `line 75 "verilog/inc_def09.v" 2 verilog/inc_nonl.v:1: `line 1 "verilog/inc_nonl.v" 0 verilog/inc_nonl.v:2: blah-no-newline-here> verilog/inc_nonl.v:3: `line 3 "verilog/inc_nonl.v" 2 verilog/inc_ifdef.v:1: `line 1 "verilog/inc_ifdef.v" 0 verilog/inc_ifdef.v:12: $display("1A"); verilog/inc_ifdef.v:16: $display("2A"); verilog/inc_ifdef.v:22: $display("3AELSE"); verilog/inc_ifdef.v:42: `line 42 "verilog/inc_ifdef.v" 2 verilog/inc2.v:1: `line 1 "verilog/inc2.v" 0 verilog/inc2.v:4: At file "verilog/inc2.v" line 4 verilog/inc2.v:5: `line 5 "verilog/inc2.v" 0 verilog/inc2.v:5: `line 1 "verilog/t_preproc_inc3.vh" 1 verilog/t_preproc_inc3.vh:1: `line 2 "inc3_a_filename_from_line_directive" 0 inc3_a_filename_from_line_directive:10: At file "inc3_a_filename_from_line_directive" line 10 inc3_a_filename_from_line_directive:19: `line 19 "inc3_a_filename_from_line_directive" 2 verilog/inc2.v:5: `line 5 "verilog/inc2.v" 0 verilog/inc2.v:7: `line 7 "verilog/inc2.v" 2 verilog/inc1.v:1: `line 1 "verilog/inc1.v" 0 verilog/inc1.v:4: text. verilog/inc1.v:15: wire [3:0] q = { verilog/inc1.v:16: 1'b1 , verilog/inc1.v:17: 1'b0 , verilog/inc1.v:18: 1'b1 , verilog/inc1.v:19: 1'b0 verilog/inc1.v:20: }; verilog/inc1.v:22: text. verilog/inc1.v:26: foo bar verilog/inc1.v:27: foobar2 verilog/inc1.v:39: first part verilog/inc1.v:39: `line 39 "verilog/inc1.v" 0 verilog/inc1.v:39: second part verilog/inc1.v:39: `line 39 "verilog/inc1.v" 0 verilog/inc1.v:39: third part verilog/inc1.v:40: { verilog/inc1.v:40: `line 40 "verilog/inc1.v" 0 verilog/inc1.v:40: a, verilog/inc1.v:40: `line 40 "verilog/inc1.v" 0 verilog/inc1.v:40: b, verilog/inc1.v:40: `line 40 "verilog/inc1.v" 0 verilog/inc1.v:40: c} verilog/inc1.v:41: Line_Preproc_Check 41 verilog/inc1.v:49: deep deep verilog/inc1.v:53: "Inside: `nosubst" verilog/inc1.v:54: "`nosubst" verilog/inc1.v:57: x y LLZZ x y verilog/inc1.v:58: p q LLZZ p q r s LLZZ r s LLZZ p q LLZZ p q r s LLZZ r s verilog/inc1.v:62: firstline comma","line LLZZ firstline comma","line verilog/inc1.v:65: x y LLZZ "x" y verilog/inc1.v:68: (a,b)(a,b) verilog/inc1.v:71: $display("left side: \"right side\"") verilog/inc1.v:74: bar_suffix more verilog/inc1.v:78: `line 78 "verilog/inc1.v" 0 verilog/inc1.v:78: $c("Zap(\"",bug1,"\");");; verilog/inc1.v:79: `line 79 "verilog/inc1.v" 0 verilog/inc1.v:79: $c("Zap(\"","bug2","\");");; verilog/inc1.v:93: initial begin verilog/inc1.v:95: $display("pre thrupre thrumid thrupost post: \"right side\""); verilog/inc1.v:96: $display("left side: \"right side\""); verilog/inc1.v:97: $display("left side: \"right side\""); verilog/inc1.v:98: $display("left_side: \"right_side\""); verilog/inc1.v:99: $display("na: \"right_side\""); verilog/inc1.v:100: $display("prep ( midp1 left_side midp2 ( outp ) ): \"right_side\""); verilog/inc1.v:101: $display("na: \"nana\""); verilog/inc1.v:102: $display("left_side right_side: \"left_side right_side\""); verilog/inc1.v:103: $display(": \"\""); verilog/inc1.v:104: $display("left side: \"right side\""); verilog/inc1.v:105: $display("left side: \"right side\""); verilog/inc1.v:106: $display("standalone"); verilog/inc1.v:111: $display("twoline: \"first second\""); verilog/inc1.v:113: $write("*-* All Finished *-*\n"); verilog/inc1.v:114: $finish; verilog/inc1.v:115: end verilog/inc1.v:116: endmodule verilog/inc1.v:126: module add1 ( input wire d1, output wire o1); verilog/inc1.v:127: `line 127 "verilog/inc1.v" 0 verilog/inc1.v:127: wire tmp_d1 = d1; verilog/inc1.v:127: `line 127 "verilog/inc1.v" 0 verilog/inc1.v:127: wire tmp_o1 = tmp_d1 + 1; verilog/inc1.v:127: `line 127 "verilog/inc1.v" 0 verilog/inc1.v:127: assign o1 = tmp_o1 ; verilog/inc1.v:128: endmodule verilog/inc1.v:129: module add2 ( input wire d2, output wire o2); verilog/inc1.v:130: `line 130 "verilog/inc1.v" 0 verilog/inc1.v:130: wire tmp_d2 = d2; verilog/inc1.v:130: `line 130 "verilog/inc1.v" 0 verilog/inc1.v:130: wire tmp_o2 = tmp_d2 + 1; verilog/inc1.v:130: `line 130 "verilog/inc1.v" 0 verilog/inc1.v:130: assign o2 = tmp_o2 ; verilog/inc1.v:131: endmodule verilog/inc1.v:144: `line 144 "verilog/inc1.v" 0 verilog/inc1.v:144: generate for (i=0; i<(3); i=i+1) begin verilog/inc1.v:144: `line 144 "verilog/inc1.v" 0 verilog/inc1.v:144: psl cover { m5k.f .ctl._ctl_mvldx_m1.d[i] & ~m5k.f .ctl._ctl_mvldx_m1.q[i] & !m5k.f .ctl._ctl_mvldx_m1.cond & ((m5k.f .ctl.alive & m5k.f .ctl.alive_m1))} report "fondNoRise: m5kc_fcl._ctl_mvldx_m1"; verilog/inc1.v:144: `line 144 "verilog/inc1.v" 0 verilog/inc1.v:144: psl cover { ~m5k.f .ctl._ctl_mvldx_m1.d[i] & m5k.f .ctl._ctl_mvldx_m1.q[i] & !m5k.f .ctl._ctl_mvldx_m1.cond & ((m5k.f .ctl.alive & m5k.f .ctl.alive_m1))} report "fondNoFall: m5kc_fcl._ctl_mvldx_m1"; verilog/inc1.v:144: `line 144 "verilog/inc1.v" 0 verilog/inc1.v:144: end endgenerate verilog/inc1.v:148: module prot(); verilog/inc1.v:149: `protected verilog/inc1.v:150: I!#r#e6<_Q{{E2+]I3<[3s)1@D|'E''i!O?]jD>Jo_![Cl) verilog/inc1.v:151: #nj1]p,3^1~,="E@QZB\T)eU\pC#C|7=\$J$##A[@-@{Qk] verilog/inc1.v:152: `endprotected verilog/inc1.v:153: endmodule verilog/inc1.v:155: module prot2(); verilog/inc1.v:156: `pragma protect begin_protected verilog/inc1.v:157: `pragma protect encrypt_agent = "Whatever agent" verilog/inc1.v:158: `pragma protect encrypt_agent_info = "1.2.3" verilog/inc1.v:159: `pragma protect data_method = "aes128-cbc" verilog/inc1.v:160: `pragma protect key_keyowner = "Someone" verilog/inc1.v:161: `pragma protect key_keyname = "somekey", key_method = "rsa" verilog/inc1.v:162: `pragma protect key_block encoding = (enctype = "base64") verilog/inc1.v:163: wefjosdfjklajklasjkl verilog/inc1.v:164: `pragma protect data_block encoding = (enctype = "base64", bytes = 1059) verilog/inc1.v:165: I!#r#e6<_Q{{E2+]I3<[3s)1@D|'E''i!O?]jD>Jo_![Cl) verilog/inc1.v:166: #nj1]p,3^1~,="E@QZB\T)eU\pC#C|7=\$J$##A[@-@{Qk] verilog/inc1.v:167: `pragma protect end_protected verilog/inc1.v:168: `pragma reset protect verilog/inc1.v:169: endmodule verilog/inc1.v:171: module prot3(); verilog/inc1.v:172: //pragma protect begin_protected verilog/inc1.v:173: //pragma protect key_keyowner=Cadence Design Systems. verilog/inc1.v:174: //pragma protect key_keyname=CDS_KEY verilog/inc1.v:175: //pragma protect key_method=RC5 verilog/inc1.v:176: //pragma protect key_block verilog/inc1.v:177: zzZzZ/4ZzzZZZzzz4zZzZzZZZZzZzZ/Zz+33zZ2zz/zzzzzzzzZZZzZ4z+ZZZZz1 verilog/inc1.v:178: Z1ZzzzZZzZZzz9ZZZZ37zzZzZzZzzz9ZZzzZzZz9Zz64+z8Z7ZzZZZzzzzZZZzZz verilog/inc1.v:179: zzZzZZZzZ0463zzzzzZzZ6z00z4zZzzZZzzZzzzZZ8zzz09ZzZZZZZ== verilog/inc1.v:180: //pragma protect end_key_block verilog/inc1.v:181: //pragma protect digest_block verilog/inc1.v:182: ZzZZzzZ9ZZZZz2ZzzzZz/Zzzz8Z= verilog/inc1.v:183: //pragma protect end_digest_block verilog/inc1.v:184: //pragma protect data_block verilog/inc1.v:185: ZZZ8zZzz6ZZ/zZZ5zZZzzz3ZzzzZzZZZ6ZzZzZZZZZz1zzZZZZ7ZZZZz3Zzz+9zz verilog/inc1.v:186: 4zzz+8zZzzzzZzZZzzzZzz1Z7ZzZz+zZz8ZZZZzZ6ZzzZzZZzzZZzzZzzZzZzZzZ verilog/inc1.v:187: ZzzzzZ0zZz1ZzzZzzZzZzz== verilog/inc1.v:188: //pragma protect end_data_block verilog/inc1.v:189: //pragma protect digest_block verilog/inc1.v:190: Z4Z6zZzZ3Z7ZZ6zzZZZZzzzzZZZ= verilog/inc1.v:191: //pragma protect end_digest_block verilog/inc1.v:192: //pragma protect end_protected verilog/inc1.v:193: endmodule verilog/inc1.v:205: begin addr <= (({regs[6], regs[7]} + 1)); rd <= 1; end and begin addr <= (({regs[6], regs[7]})); wdata <= (rdata); wr <= 1; end verilog/inc1.v:206: begin addr <= ({regs[6], regs[7]} + 1); rd <= 1; end verilog/inc1.v:207: begin addr <= ({regs[6], regs[7]}); wdata <= (rdata); wr <= 1; end more verilog/inc1.v:212: `line 212 "verilog/inc1.v" 0 verilog/inc1.v:212: `line 1 "verilog/t_preproc_inc4.vh" 1 verilog/t_preproc_inc4.vh:2: `line 2 "verilog/t_preproc_inc4.vh" 0 verilog/t_preproc_inc4.vh:7: `line 7 "verilog/t_preproc_inc4.vh" 2 verilog/inc1.v:212: `line 212 "verilog/inc1.v" 0 verilog/inc1.v:226: $blah("ab,cd","e,f"); verilog/inc1.v:227: $blah(this.logfile,vec); verilog/inc1.v:228: $blah(this.logfile,vec[1,2,3]); verilog/inc1.v:229: $blah(this.logfile,{blah.name(), " is not foo"}); verilog/inc1.v:234: `pragma foo = 1 verilog/inc1.v:235: `default_nettype none verilog/inc1.v:236: `default_nettype uwire verilog/inc1.v:245: Line_Preproc_Check 245 verilog/inc1.v:253: (p,q) verilog/inc1.v:257: (x,y) verilog/inc1.v:258: Line_Preproc_Check 258 verilog/inc1.v:267: beginend verilog/inc1.v:268: beginend verilog/inc1.v:269: "beginend" verilog/inc1.v:275: `\esc`def verilog/inc1.v:277: Not a \`define verilog/inc1.v:285: x,y)--bee submacro has comma paren verilog/inc1.v:290: $display("10 %d %d", $bits(foo), 10); verilog/inc1.v:314: `line 314 "verilog/inc1.v" 0 verilog/inc1.v:314: `line 314 "verilog/inc1.v" 0 verilog/inc1.v:314: `line 314 "verilog/inc1.v" 0 verilog/inc1.v:314: `line 314 "verilog/inc1.v" 0 verilog/inc1.v:314: `line 314 "verilog/inc1.v" 0 verilog/inc1.v:314: `line 314 "verilog/inc1.v" 0 verilog/inc1.v:314: `line 314 "verilog/inc1.v" 0 verilog/inc1.v:314: `line 314 "verilog/inc1.v" 0 verilog/inc1.v:314: `line 314 "verilog/inc1.v" 0 verilog/inc1.v:314: assign a3 = ~b3 ; verilog/inc1.v:314: `line 314 "verilog/inc1.v" 0 verilog/inc1.v:316: `line 316 "verilog/inc1.v" 0 verilog/inc1.v:317: \ verilog/inc1.v:318: `line 318 "verilog/inc1.v" 0 verilog/inc1.v:325: `line 325 "verilog/inc1.v" 0 verilog/inc1.v:325: `line 325 "verilog/inc1.v" 0 verilog/inc1.v:325: `line 325 "verilog/inc1.v" 0 verilog/inc1.v:325: def i verilog/inc1.v:325: `line 325 "verilog/inc1.v" 0 verilog/inc1.v:339: 1 (nodef) verilog/inc1.v:340: 2 (hasdef) verilog/inc1.v:341: 3 (nodef) verilog/inc1.v:342: 4 verilog/inc1.v:342: `line 342 "verilog/inc1.v" 0 verilog/inc1.v:342: (nodef) verilog/inc1.v:343: 5 also in verilog/inc1.v:343: `line 343 "verilog/inc1.v" 0 verilog/inc1.v:343: also3 (nodef) verilog/inc1.v:346: HAS a NEW verilog/inc1.v:346: `line 346 "verilog/inc1.v" 0 verilog/inc1.v:346: LINE verilog/inc1.v:366: EXP: clxx_scen verilog/inc1.v:367: clxx_scen verilog/inc1.v:368: EXP: clxx_scen verilog/inc1.v:369: "clxx_scen" verilog/inc1.v:371: EXP: do if (start("verilog/inc1.v", 25)) begin message({"Blah-", "clx_scen", " end"}); end while(0); verilog/inc1.v:372: `line 372 "verilog/inc1.v" 0 verilog/inc1.v:372: do verilog/inc1.v:372: `line 372 "verilog/inc1.v" 0 verilog/inc1.v:372: `line 372 "verilog/inc1.v" 0 verilog/inc1.v:372: while(0); verilog/inc1.v:380: `line 380 "verilog/inc1.v" 0 verilog/inc1.v:380: `line 380 "verilog/inc1.v" 0 verilog/inc1.v:380: `line 380 "verilog/inc1.v" 0 verilog/inc1.v:383: EXP: This is fooed verilog/inc1.v:384: This is fooed verilog/inc1.v:385: EXP: This is fooed_2 verilog/inc1.v:386: This is fooed_2 verilog/inc1.v:390: np verilog/inc1.v:391: np verilog/inc1.v:414: hello3hello3hello3 verilog/inc1.v:415: hello4hello4hello4hello4 verilog/inc1.v:420: `line 420 "verilog/inc1.v" 0 verilog/inc1.v:420: `line 1 "verilog/t_preproc_inc4.vh" 1 verilog/t_preproc_inc4.vh:2: `line 2 "verilog/t_preproc_inc4.vh" 0 verilog/t_preproc_inc4.vh:7: `line 7 "verilog/t_preproc_inc4.vh" 2 verilog/inc1.v:420: `line 420 "verilog/inc1.v" 0 verilog/inc1.v:429: `line 429 "verilog/inc1.v" 0 verilog/inc1.v:433: Line_Preproc_Check 433 verilog/inc1.v:439: Line_Preproc_Check 439 verilog/inc1.v:441: "FOO \ verilog/inc1.v:441: BAR " "arg_line1 \ verilog/inc1.v:441: arg_line2" "FOO \ verilog/inc1.v:441: BAR " verilog/inc1.v:442: `line 442 "verilog/inc1.v" 0 verilog/inc1.v:442: Line_Preproc_Check 442 verilog/inc1.v:451: abc verilog/inc1.v:459: EXP: sonet_frame verilog/inc1.v:460: sonet_frame verilog/inc1.v:464: EXP: sonet_frame verilog/inc1.v:465: sonet_frame verilog/inc1.v:469: EXP: sonet_frame verilog/inc1.v:470: sonet_frame verilog/inc1.v:475: EXP: module zzz ; endmodule verilog/inc1.v:476: module zzz ; endmodule verilog/inc1.v:477: module zzz ; endmodule verilog/inc1.v:480: EXP: module a_b ; endmodule verilog/inc1.v:481: module a_b ; endmodule verilog/inc1.v:482: module a_b ; endmodule verilog/inc1.v:486: integer foo; verilog/inc1.v:488: synth_test: verilog/inc1.v:489: `line 489 "verilog/inc1.v" 0 verilog/inc1.v:492: EXP: on verilog/inc1.v:495: module t; verilog/inc1.v:502: initial begin : \`LEX_CAT(a[0],_assignment) verilog/inc1.v:502: `line 502 "verilog/inc1.v" 0 verilog/inc1.v:502: $write("GOT%%m='%m' EXP='%s'\n", "t.\\`LEX_CAT(a[0],_assignment) "); end verilog/inc1.v:509: initial begin : \a[0]_assignment_a[1] verilog/inc1.v:509: `line 509 "verilog/inc1.v" 0 verilog/inc1.v:509: $write("GOT%%m='%m' EXP='%s'\n", "t.\\a[0]_assignment_a[1] "); end verilog/inc1.v:516: initial begin : \`CAT(pp,suffix) $write("GOT%%m='%m' EXP='%s'\n", "t.\\`CAT(pp,suffix) "); end verilog/inc1.v:523: initial begin : \`CAT(ff,bb) verilog/inc1.v:523: `line 523 "verilog/inc1.v" 0 verilog/inc1.v:523: $write("GOT%%m='%m' EXP='%s'\n", "t.\\`CAT(ff,bb) "); end verilog/inc1.v:529: initial begin : \`zzz verilog/inc1.v:529: `line 529 "verilog/inc1.v" 0 verilog/inc1.v:529: $write("GOT%%m='%m' EXP='%s'\n", "t.\\`zzz "); end verilog/inc1.v:536: initial begin : \`FOO verilog/inc1.v:536: `line 536 "verilog/inc1.v" 0 verilog/inc1.v:536: $write("GOT%%m='%m' OTHER_EXP='%s'\n OUR_EXP='%s'", "t.bar ","t.\\`FOO "); end verilog/inc1.v:538: initial begin : \xx`FOO verilog/inc1.v:538: `line 538 "verilog/inc1.v" 0 verilog/inc1.v:538: $write("GOT%%m='%m' EXP='%s'\n", "t.\\xx`FOO "); end verilog/inc1.v:543: initial begin : \`UNKNOWN $write("GOT%%m='%m' EXP='%s'\n", "t.\\`UNKNOWN "); end verilog/inc1.v:547: initial begin : \`DEF_NO_EXPAND $write("GOT%%m='%m' EXP='%s'\n", "t.\\`DEF_NO_EXPAND "); end verilog/inc1.v:553: initial $write("GOT='%s' EXP='%s'\n", "foo bar baz", "foo bar baz"); verilog/inc1.v:559: initial $write("GOT='%s' EXP='%s'\n", "foo `A(bar) baz", "foo `A(bar) baz"); verilog/inc1.v:564: initial $write("Slashed=`%s'\n", "1//2.3"); verilog/inc1.v:569: initial verilog/inc1.v:569: `line 569 "verilog/inc1.v" 0 verilog/inc1.v:569: $display("%s%s","a1","b2c3\n"); verilog/inc1.v:570: endmodule verilog/inc1.v:577: $display("RAM0"); verilog/inc1.v:578: $display("CPU"); verilog/inc1.v:586: XXE_FAMILY = XXE_ verilog/inc1.v:589: $display("XXE_ is defined"); verilog/inc1.v:593: XYE_FAMILY = XYE_ verilog/inc1.v:596: $display("XYE_ is defined"); verilog/inc1.v:600: XXS_FAMILY = XXS_some verilog/inc1.v:603: $display("XXS_some is defined"); verilog/inc1.v:607: XYS_FAMILY = XYS_foo verilog/inc1.v:610: $display("XYS_foo is defined"); verilog/inc1.v:650: (.mySig (myInterface.pa5), verilog/inc1.v:656: `dbg_hdl(UVM_LOW, ("Functional coverage enabled: paramgrp")); verilog/inc1.v:666: module pcc2_cfg; verilog/inc1.v:667: generate verilog/inc1.v:668: `line 668 "verilog/inc1.v" 0 verilog/inc1.v:668: covergroup a @(posedge b); verilog/inc1.v:668: `line 668 "verilog/inc1.v" 0 verilog/inc1.v:668: c: coverpoint d iff ((c) === 1'b1); endgroup verilog/inc1.v:668: `line 668 "verilog/inc1.v" 0 verilog/inc1.v:668: a u_a; verilog/inc1.v:668: `line 668 "verilog/inc1.v" 0 verilog/inc1.v:668: initial do begin $display ("DEBUG : %s [%m]", $sformatf ("Functional coverage enabled: u_a")); end while(0); verilog/inc1.v:669: endgenerate verilog/inc1.v:670: endmodule verilog/inc1.v:675: "`NOT_DEFINED_STR" verilog/inc1.v:680: predef 0 0 verilog/inc1.v:681: predef 1 1 verilog/inc1.v:682: predef 2 2 verilog/inc1.v:683: predef 3 3 verilog/inc1.v:684: predef 10 10 verilog/inc1.v:685: predef 11 11 verilog/inc1.v:686: predef 20 20 verilog/inc1.v:687: predef 21 21 verilog/inc1.v:688: predef 22 22 verilog/inc1.v:689: predef 23 23 verilog/inc1.v:690: predef -2 -2 verilog/inc1.v:691: predef -1 -1 verilog/inc1.v:692: predef 0 0 verilog/inc1.v:693: predef 1 1 verilog/inc1.v:694: predef 2 2 verilog/inc1.v:696: `line 696 "verilog/inc1.v" 2 Verilog-Perl-3.482/t/46_link.t0000755000177100017500000000174714553624300015730 0ustar wsnyderwsnyder#!/usr/bin/perl -w # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package # # Copyright 2000-2024 by Wilson Snyder. This program is free software; # you can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. use strict; use Test::More; BEGIN { plan tests => 2 } BEGIN { require "./t/test_utils.pl"; } #$Verilog::Netlist::Debug = 1; use Verilog::Netlist; use Verilog::Getopt; ok(1, "use"); { # Setup options so files can be found my $opt = new Verilog::Getopt; $opt->parameter( "+incdir+verilog", "-y","verilog", ); # Prepare netlist my $nl = new Verilog::Netlist (options => $opt, ); foreach my $file ('verilog/v_gate.v') { $nl->read_file (filename=>$file); } # Read in any sub-modules $nl->read_libraries(); $nl->link(); $nl->lint(); $nl->exit_if_error(); print "Dump\n"; $nl->dump; } ok(1, "done"); Verilog-Perl-3.482/t/86_vhier_tick.t0000755000177100017500000000107214553624300017115 0ustar wsnyderwsnyder#!/usr/bin/perl -w # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package # # Copyright 2000-2024 by Wilson Snyder. This program is free software; # you can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. use IO::File; use strict; use Test::More; BEGIN { plan tests => 2 } BEGIN { require "./t/test_utils.pl"; } # bug300 my $cmd = "${PERL} ./vhier --input-files -y verilog t_86_vhier_tick.v"; my $out = `$cmd`; is($?,0,$cmd); like($out, qr//, $cmd); Verilog-Perl-3.482/t/32_noinc.t0000755000177100017500000000200114553624300016054 0ustar wsnyderwsnyder#!/usr/bin/perl -w # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package # # Copyright 2000-2024 by Wilson Snyder. This program is free software; # you can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. use IO::File; use strict; use Test::More; BEGIN { plan tests => 7 } BEGIN { require "./t/test_utils.pl"; } ####################################################################### use Verilog::Getopt; use Verilog::Preproc; ok(1, "use"); # Check we get error eval { check(); }; like ($@, qr/32_noinc.v:\d+: Cannot open notfound/); check(include_open_nonfatal=>1); ok (1); # Check no error sub check { my @opts = (@_); my $opt = new Verilog::Getopt; my $pp = new Verilog::Preproc (options=>$opt, @opts); ok(1, "new"); #$pp->debug(9); $pp->open("t/32_noinc.v"); ok(1, "open"); while (defined(my $line = $pp->getline())) { #print "LINE: $line"; } } Verilog-Perl-3.482/t/16_std.t0000755000177100017500000000107314553624300015552 0ustar wsnyderwsnyder#!/usr/bin/perl -w # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package # # Copyright 2009-2024 by Wilson Snyder. This program is free software; # you can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. use strict; use Test::More; BEGIN { plan tests => 3 } BEGIN { require "./t/test_utils.pl"; } use Verilog::Std; ok(1, "use"); like (Verilog::Std::std(), qr/endpackage/); # Make sure data sticks around like (Verilog::Std::std(), qr/endpackage/); Verilog-Perl-3.482/t/56_editfiles_b.out0000644000177100017500000000042413302063476017577 0ustar wsnyderwsnyder// Created by 56_editfiles.t from 56_editfiles.v b_front_matter; `celldefine // lint_checking HEADER `ifdef B_HAS_X module b; `elsif module b (input x); `endif wire inside_module_b; `ifndef SYNTHESIS wire in_translate_off; `endif //SYNTHESIS endmodule `endcelldefine Verilog-Perl-3.482/t/85_vhier_includes.out0000644000177100017500000000005114030463163020323 0ustar wsnyderwsnyder verilog/v_hier_top.v v_hier_inc.vh Verilog-Perl-3.482/t/44_create.out0000644000177100017500000000014313234726611016565 0ustar wsnyderwsnydermodule a ( x, y); input [2:0] x; output [2:0] y; b i_b (.w(y[2:0]), .z(x)); endmodule Verilog-Perl-3.482/t/80_vppreproc_cmped.out0000644000177100017500000000057413741600370020516 0ustar wsnyderwsnyder`line 1 "verilog/inc2.v" 1 At file "verilog/inc2.v" line 4 `line 5 "verilog/inc2.v" 0 `line 1 "verilog/t_preproc_inc3.vh" 1 `line 2 "inc3_a_filename_from_line_directive" 0 At file "inc3_a_filename_from_line_directive" line 10 `line 19 "inc3_a_filename_from_line_directive" 2 `line 5 "verilog/inc2.v" 0 `line 7 "verilog/inc2.v" 2 Verilog-Perl-3.482/t/14_numbers.t0000755000177100017500000000547314553624300016441 0ustar wsnyderwsnyder#!/usr/bin/perl -w # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package # # Copyright 2000-2024 by Wilson Snyder. This program is free software; # you can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. use strict; use Test::More; BEGIN { plan tests => 32 } BEGIN { require "./t/test_utils.pl"; } use Verilog::Language; ok(1, "use"); is (Verilog::Language::number_value("5'h13"), 19); is (Verilog::Language::number_value("5'd13"), 13); is (Verilog::Language::number_value("5'o13"), 11); is (Verilog::Language::number_value("5'B11"), 3); is (Verilog::Language::number_value("5 'B 11"), 3); is (Verilog::Language::number_value("'b10"), 2); is (Verilog::Language::number_value("2'sb10"), 2); is (Verilog::Language::number_bits("8'b10"), 8); is (Verilog::Language::number_bits("8 'b 10"), 8); is (Verilog::Language::number_signed("8 'sb 1"), 1); ok (!defined Verilog::Language::number_bits("'b10")); print " Bit::Vector\n"; eval "use Bit::Vector"; SKIP: { if ($@) { skip("Bit::Vector not installed (harmless)",5*2); } try_bitvector("5823", 32, "000016bf"); try_bitvector("80'h47cb_40d7_b50f_0147_1a85", 80, "47cb40d7b50f01471a85"); try_bitvector("83'o227525534413441101057616251", 83, "097aad721721208bf1ca9"); try_bitvector("70'b1011010111111001010111111111111001110000011000101110010100110101101101", 70, "2d7e57ff9c18b94d6d"); try_bitvector("90'd46548__4046747316__6145438700", 90, "003d9b368496d10ab0043ec"); } print " Math::BigInt\n"; eval "use Math::BigInts"; SKIP: { if ($@) { skip("Math::BigInt not installed (harmless)",5*2); } try_bigint("5823", 4, "0x16bf"); try_bigint("80'h47cb_40d7_b50f_0147_1a85", 24, "0x47cb40d7b50f01471a85"); try_bigint("83'o227525534413441101057616251", 24, "0x97aad721721208bf1ca9"); try_bigint("70'b1011010111111001010111111111111001110000011000101110010100110101101101", 21, "0x2d7e57ff9c18b94d6d"); try_bigint("90'd46548__4046747316__6145438700", 25, "0x3d9b368496d10ab0043ec"); } sub try_bitvector { my $text = shift; my $expbits = shift; my $expvalue = shift; my $got = Verilog::Language::number_bitvector($text); my $gotbits = $got->Size; my $gotvalue = lc $got->to_Hex; print " $text -> got $gotbits $gotvalue =? exp $expbits exp $expvalue\n"; is ($gotbits, $expbits, "number of bits"); is ($gotvalue, $expvalue, "value"); } sub try_bigint { my $text = shift; my $expbits = shift; my $expvalue = shift; my $got = Verilog::Language::number_bigint($text); my $gotbits = $got->length; my $gotvalue = lc $got->as_hex; print " $text -> got $gotbits $gotvalue =? exp $expbits exp $expvalue\n"; is ($gotbits, $expbits, "number of bits"); is ($gotvalue, $expvalue, "value"); } Verilog-Perl-3.482/t/20_getopt.t0000755000177100017500000000537014553624300016261 0ustar wsnyderwsnyder#!/usr/bin/perl -w # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package # # Copyright 2000-2024 by Wilson Snyder. This program is free software; # you can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. use strict; use Test::More; use Cwd; BEGIN { plan tests => 15 } BEGIN { require "./t/test_utils.pl"; } use Verilog::Getopt; ok(1, "use"); $Verilog::Getopt::Debug = 1; my $opt = new Verilog::Getopt; ok(1, "new"); $ENV{DOT} = "."; is($opt->file_substitute('Fred/$DOT/$NOT_SET_IN_ENV/$DOT'), 'Fred/./$NOT_SET_IN_ENV/.'); my @param = qw ( +libext+t +incdir+t +define+foo=bar +define+foo2 +define+foo3=3+foo4 -v libdir -y moddir -Dbaz=bar -Iincdir2 -f $DOT/t/20_getopt.opt -F $DOT/t/20_getopt.opt passthru ); my @left = $opt->parameter(@param); print join(" ",@left),"\n"; is ($#left, 0); # passthru ok ($opt->defvalue('read_opt_file')); my $fp = $opt->file_path('20_getopt.t'); print "fp $fp\n"; ok (($fp eq (Cwd::abs_path("t")."/20_getopt.t")) || ($fp eq "t/20_getopt.t")); my @out = $opt->get_parameters(); print "OUT: ",(join(" ",@out)),"\n"; is ($#out, 19); { my $opt2 = new Verilog::Getopt (); my @left2 = $opt2->parameter(@out); print "LEFT: ",join(" ",@left2),"\n"; my @out2 = $opt->get_parameters(); print "LEFT: ",join(" ",@out2),"\n"; is_deeply(\@out2, [qw(+define+baz=bar +define+foo=bar +define+foo2 +define+foo3=3 +define+foo4 +define+read_opt_file=1 +libext+.v+t +incdir+. +incdir+t +incdir+incdir2 -y . -y moddir -y y_library_path -y t/y_library_path -v libdir)]); } { my $opt2 = new Verilog::Getopt (gcc_style=>1, vcs_style=>0); my @left2 = $opt2->parameter(@param); print "LEFT: ",join(" ",@left2),"\n"; is_deeply(\@left2, [qw(+libext+t +incdir+t +define+foo=bar +define+foo2 +define+foo3=3+foo4 -v libdir -y moddir -y y_library_path -y y_library_path passthru)]); } { my $opt2 = new Verilog::Getopt (gcc_style=>0, vcs_style=>1); my @left2 = $opt2->parameter(@param); print "LEFT: ",join(" ",@left2),"\n"; is_deeply(\@left2, [qw(-Dbaz=bar -Iincdir2 -Dread_opt_file=1 -Dread_opt_file=1 passthru)]); } { my $opt2 = new Verilog::Getopt (gcc_style=>0, vcs_style=>1); { local $SIG{__WARN__} = sub {}, my @left2 = $opt2->parameter("+define+foo=bar", "+define+foo=baz"); } my @out2 = $opt2->get_parameters(); is_deeply($out2[0], qw(+define+foo=baz)); } $opt->map_directories(sub{s![a-z]!x!; $_}); ok(1); ok($opt->file_skip_special(".svn")); ok(!$opt->file_skip_special("svn")); ok($opt->file_skip_special("foo/bar/baz/CVS")); Verilog-Perl-3.482/t/44_create.t0000755000177100017500000000275714553624300016236 0ustar wsnyderwsnyder#!/usr/bin/perl -w # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package # # Copyright 2000-2024 by Wilson Snyder. This program is free software; # you can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. use strict; use Test::More; BEGIN { plan tests => 3 } BEGIN { require "./t/test_utils.pl"; } #$Verilog::Netlist::Debug = 1; use Verilog::Netlist; use Verilog::Getopt; ok(1, "use"); { my $opt = new Verilog::Getopt; $opt->parameter( "+incdir+verilog", "-y","verilog", ); # Prepare netlist my $nl = new Verilog::Netlist (options => $opt, link_read_nonfatal=>1, ); my @fl = (filename=>'44_create.t', lineno=>0); my $moda = $nl->new_module (name=>'a', @fl); { my $x = $moda->new_port (name=>'x', @fl, direction=>'input', data_type=>'[2:0]',); my $y = $moda->new_port (name=>'y', @fl, direction=>'output', data_type=>'[2:0]',); my $b = $moda->new_cell (name=>'i_b', submodname=>'b', @fl); { $b->new_pin(name=>'z', portname=>'z', pinnamed=>1, netname=>'x', @fl); $b->new_pin(name=>'w', portname=>'w', pinnamed=>1, pinselects=>[{netname=>'y', msb=>2, lsb=>0}], @fl); } } $nl->link; my $fh = IO::File->new('test_dir/44_create.dmp', "w") or die "%Error: $! creating dump file,"; print $fh $nl->verilog_text; $fh->close; ok(files_identical("test_dir/44_create.dmp", "t/44_create.out")); } ok(1, "done"); Verilog-Perl-3.482/t/56_editfiles_a.out0000644000177100017500000000062313302063476017577 0ustar wsnyderwsnyder// Created by 56_editfiles.t from 56_editfiles.v // Created by 56_editfiles.t from 56_editfiles.v // DESCRIPTION: Verilog::Preproc: Example source code // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2007-2012 by Wilson Snyder. a_front_matter; `celldefine // lint_checking HEADER module a; wire inside_module_a; /* // double cmt */ endmodule `endcelldefine Verilog-Perl-3.482/t/87_vhier_unicode.t0000755000177100017500000000273114553624300017615 0ustar wsnyderwsnyder#!/usr/bin/perl -w # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package # # Copyright 2000-2024 by Wilson Snyder. This program is free software; # you can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. use IO::File; use strict; use Test::More; BEGIN { plan tests => 3 } BEGIN { require "./t/test_utils.pl"; } { my $fh = IO::File->new(">test_dir/unicode.v"); $fh->print(chr(0xEF).chr(0xBB).chr(0xBF)); # BOM $fh->print("// Bom\n"); $fh->print("module t;\n"); $fh->print(" // Chinese " .chr(0xe8).chr(0xaf).chr(0x84).chr(0xe8).chr(0xae).chr(0xba) # Comment ."\n"); $fh->print(" initial begin\n"); $fh->print(" \$write(\"Hello " .chr(0xe4).chr(0xb8).chr(0x96).chr(0xe7).chr(0x95).chr(0x8c) # World ."\\n\");\n"); $fh->print(" \$write(\"*-* All Finished *-*\\n\");\n"); $fh->print(" end\n"); $fh->print("endmodule\n"); $fh->close; } ok(1); { my $out = "test_dir/unicode_vppreproc.out"; my $cmd = "${PERL} ./vppreproc -y verilog test_dir/unicode.v > $out"; run_system($cmd); ok(-r $out, "vppreproc outputted from: $cmd"); } { my $out = "test_dir/unicode_vhier.out"; my $cmd = "${PERL} ./vhier --input-files --nomissing -y verilog test_dir/unicode.v -o $out"; run_system($cmd); ok(-r $out, "vhier outputted from: $cmd"); } Verilog-Perl-3.482/t/85_vhier_skiplist.out0000644000177100017500000000010713741600320020355 0ustar wsnyderwsnyder v_hier_top v_hier_top |--recursive v_recursive \--sub v_hier_sub Verilog-Perl-3.482/t/51_vrename_kwd_chg2.out0000644000177100017500000000216413462302176020531 0ustar wsnyderwsnyder// DESCRIPTION: Verilog-Perl: Example Verilog for testing package // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2010-2012 by Wilson Snyder. module 51_vrename_kwd; // Keyword wire do; wire \do ; // Non escapes wire chg_non_2non; wire chg_non_2non_nospace ; wire \chg_non_2ext ; wire \chg_non_2ext_nospace ; wire \chg_non[ape]_2esc ; wire \chg_non[ape]_2esc_nospace ; // Extra unnecessary escapes // Note we cannot legally remove spaces if replacing with non-escaped name wire chg_ext_2non ; wire chg_ext_2non_nospace ; wire \chg_ext_2ext ; wire \chg_ext_2ext_nospace ; wire \chg_ext[ape]_2esc ; wire \chg_ext[ape]_2esc_nospace ; // Necessary escapes wire chg_escape_2non ; wire chg_escape_2non_nospace ; wire \chg_escape_2ext ; wire \chg_escape_2ext_nospace ; wire \chg_esc[ape]_2esc ; wire \chg_esc[ape]_2esc_nospace ; // Strings initial $display("bar"); initial $display("bar.bar"); initial $display("baz_foo"); initial $display("foo_baz"); endmodule Verilog-Perl-3.482/t/02_help.t0000755000177100017500000000164314553624300015706 0ustar wsnyderwsnyder#!/usr/bin/perl -w # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package # # Copyright 2007-2024 by Wilson Snyder. This program is free software; # you can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. use strict; use Test::More; BEGIN { require "./t/test_utils.pl"; } my @execs = glob ("blib/script/[a-z]*"); plan tests => (3 * ($#execs+1)); foreach my $exe (@execs) { print "Doc test of: $exe\n"; ok (-e $exe, "exe exists: $exe"); SKIP: { skip("vsplitmodule is only example (harmless)",2) if ($exe =~ /vsplitmodule/); my $cmd = "$PERL $exe --help 2>&1"; my $help = `$cmd`; like ($help, qr/--version/, "help result for: $cmd"); $cmd = "$PERL $exe --version 2>&1"; $help = `$cmd`; like ($help, qr/Version.*[0-9]/, "version result for: $cmd"); } } Verilog-Perl-3.482/t/85_vhier_topmodule.out0000644000177100017500000000006413741600317020533 0ustar wsnyderwsnyder verilog/v_hier_sub.v verilog/v_hier_subsub.v Verilog-Perl-3.482/t/42_dumpcheck_1_ps.out0000644000177100017500000001662213422450702020210 0ustar wsnyderwsnyderModule:$root Kwd:root_module File:verilog/v_hier_top.v Net:GLOBAL_PARAM DeclT:localparam NetT: DataT: Array: Value:1 Module:v_bug917 Kwd:module File:verilog/v_comments.v Port:a Dir:in DataT: Array: Port:b Dir:out DataT: Array: Port:m Dir:out DataT: Array: Net:a O DeclT:port NetT:wire DataT: Array: Net:b I DeclT:port NetT:wire DataT: Array: Net:m I DeclT:port NetT:wire DataT: Array: Module:v_bug917p Kwd:module File:verilog/v_comments.v Port:a Dir:in DataT: Array: Port:b Dir:out DataT: Array: Net:a O DeclT:port NetT:wire DataT: Array: Net:b I DeclT:port NetT:wire DataT: Array: Module:v_comments Kwd:module File:verilog/v_comments.v Port:a Dir:in DataT: Array: Port:b Dir:inout DataT:[10:0] Array: Port:c Dir:out DataT:[0:10] Array: Port:d Dir:out DataT:[((2*32)-1):0] Array: Port:d1 Dir:out DataT:[32:0] Array: Port:d2 Dir:out DataT:[(MATH-1):0] Array: Port:d3 Dir:out DataT:[32-1:0] Array: Net:a O DeclT:port NetT: DataT: Array: Net:b DeclT:port NetT: DataT:[10:0] Array: 10:0 Net:c I DeclT:port NetT: DataT:[0:10] Array: 0:10 Net:d I DeclT:port NetT: DataT:reg Array: ((2*32)-1):0 Net:d1 I DeclT:port NetT: DataT:[32:0] Array: 32:0 Net:d2 I DeclT:port NetT: DataT:[(MATH-1):0] Array: (MATH-1):0 Net:d3 I DeclT:port NetT: DataT:[32-1:0] Array: 32-1:0 Net:e DeclT:var NetT: DataT:reg [11:0] Array: 11:0 Module:v_hier_noport Kwd:module File:verilog/v_hier_noport.v Net:P DeclT:parameter NetT: DataT: Array: Net:internal DeclT:var NetT: DataT:reg Array: Module:v_hier_sub Kwd:module File:verilog/v_hier_sub.v Port:avec Dir:in DataT:[3:0] Array: Port:clk Dir:in DataT: Array: Port:qvec Dir:out DataT:[3:0] Array: Net:FROM_DEFPARAM DeclT:parameter NetT: DataT: Array: Value:1 Net:K DeclT:genvar NetT: DataT: Array: Net:K_UNUSED DeclT:genvar NetT: DataT: Array: Net:a1 I DeclT:net NetT:supply1 DataT: Array: Net:avec O DeclT:port NetT: DataT:[3:0] Array: 3:0 Net:clk O DeclT:port NetT: DataT: Array: Net:qvec IO DeclT:port NetT: DataT:[3:0] Array: 3:0 Cell:subsub0 is-a:v_hier_subsub .IGNORED('sh20) Module:v_hier_subsub Kwd:module File:verilog/v_hier_subsub.v Pin:a Net:a1 Port:a Dir:in DataT:signed Array: Net:a1 I DeclT:net NetT:supply1 DataT: Array: Pin:q Net:qvec[0] Port:q Dir:out DataT: Array: Net:qvec IO DeclT:port NetT: DataT:[3:0] Array: 3:0 Cell:subsub2 is-a:v_hier_subsub Module:v_hier_subsub Kwd:module File:verilog/v_hier_subsub.v Pin:a Net:1'b0 Port:a Dir:in DataT:signed Array: Pin:q Net:qvec[2] Port:q Dir:out DataT: Array: Net:qvec IO DeclT:port NetT: DataT:[3:0] Array: 3:0 Module:v_hier_subsub Kwd:module File:verilog/v_hier_subsub.v Port:a Dir:in DataT:signed Array: Port:q Dir:out DataT: Array: Net:IGNORED DeclT:parameter NetT: DataT: Array: Value:0 Net:a O DeclT:port NetT: DataT:signed Array: Net:q I DeclT:port NetT:wire DataT: Array: Module:v_hier_top Kwd:module File:verilog/v_hier_top.v Port:clk Dir:in DataT: Array: Net:WC_p1 DeclT:localparam NetT: DataT:[0:0] Array: 0:0 Value:0 Net:WC_p3 DeclT:localparam NetT: DataT:[2:0] Array: 2:0 Value:0 Net:WC_p32 DeclT:localparam NetT: DataT: Array: Value:0 Net:WC_p4 DeclT:localparam NetT: DataT:[-1:2] Array: -1:2 Value:0 Net:WC_pint DeclT:localparam NetT: DataT:integer Array: Value:0 Net:WC_w1 DeclT:net NetT:wire DataT: Array: Net:WC_w1b DeclT:net NetT:wire DataT:[0:0] Array: 0:0 Net:WC_w3 DeclT:net NetT:wire DataT:[2:0] Array: 2:0 Net:WC_w4 DeclT:net NetT:wire DataT:[-1:2] Array: -1:2 Net:asn_clk DeclT:net NetT:wire DataT: Array: Net:clk O DeclT:port NetT: DataT: Array: Cell:missing is-a:missing Cell:recursive is-a:v_recursive .DEPTH(3) Module:v_recursive Kwd:module File:verilog/v_recursive.v Cell:sub is-a:v_hier_sub Module:v_hier_sub Kwd:module File:verilog/v_hier_sub.v Pin:avec Nets:avec[3],avec[2:0] Port:avec Dir:in DataT:[3:0] Array: Pin:clk Net:1'b0 Port:clk Dir:in DataT: Array: Pin:qvec Net:qvec[3:0] Port:qvec Dir:out DataT:[3:0] Array: Defparam:defparam lhs:sub.FROM_DEFPARAM rhs:2 ContAssign:assign lhs:asn_clk rhs:clk Module:v_hier_top2 Kwd:module File:verilog/v_hier_top2.v Port:clk Dir:in DataT: Array: Port:iosig Dir:inout DataT:[2:0] Array: Net:clk O DeclT:port NetT: DataT: Array: Net:iosig DeclT:port NetT: DataT:[2:0] Array: 2:0 Cell:noport is-a:v_hier_noport Module:v_hier_noport Kwd:module File:verilog/v_hier_noport.v Cell:noporta is-a:v_hier_noport .P(1) Module:v_hier_noport Kwd:module File:verilog/v_hier_noport.v Cell:noportp is-a:v_hier_noport .P(1) Module:v_hier_noport Kwd:module File:verilog/v_hier_noport.v Module:v_recursive Kwd:module File:verilog/v_recursive.v Net:DEPTH DeclT:parameter NetT: DataT: Array: Value:1 Cell:recurse is-a:v_recursive .DEPTH(DEPTH-1) Module:v_recursive Kwd:module File:verilog/v_recursive.v #### Commentary: verilog/v_hier_top.v:0042: GLOBAL_PARAM cmt="// Local Variables:\n// eval:(verilog-read-defines)\n// End:" verilog/v_comments.v:0022: a cmt="// a-First" verilog/v_comments.v:0025: b cmt="// b-Third\n// Third" verilog/v_comments.v:0023: m cmt="// m-Second" verilog/v_comments.v:0031: a cmt="// a-First" verilog/v_comments.v:0032: b cmt="// b-Secondparen\n// Third" verilog/v_comments.v:0007: a cmt="// comment for a" verilog/v_comments.v:0008: b cmt="" verilog/v_comments.v:0009: c cmt="// comment for c" verilog/v_comments.v:0010: d cmt="" verilog/v_comments.v:0011: d1 cmt="" verilog/v_comments.v:0012: d2 cmt="" verilog/v_comments.v:0013: d3 cmt="" verilog/v_comments.v:0016: e cmt="// Comment for e" verilog/v_hier_noport.v:0006: P cmt="" verilog/v_hier_noport.v:0007: internal cmt="" verilog/v_hier_sub.v:0012: FROM_DEFPARAM cmt="" verilog/v_hier_sub.v:0027: K cmt="" verilog/v_hier_sub.v:0027: K_UNUSED cmt="" verilog/v_hier_sub.v:0014: a1 cmt="// Outputs" verilog/v_hier_sub.v:0008: avec cmt="// Comment for v_hier_sub, avec" verilog/v_hier_sub.v:0007: clk cmt="" verilog/v_hier_sub.v:0009: qvec cmt="/* Comment for v_hier_sub, qvec */" verilog/v_hier_subsub.v:0011: IGNORED cmt="" verilog/v_hier_subsub.v:0012: a cmt="" verilog/v_hier_subsub.v:0013: q cmt="// Test protected\n//"" verilog/v_hier_top.v:0031: WC_p1 cmt="" verilog/v_hier_top.v:0032: WC_p3 cmt="" verilog/v_hier_top.v:0030: WC_p32 cmt="" verilog/v_hier_top.v:0033: WC_p4 cmt="" verilog/v_hier_top.v:0034: WC_pint cmt="// Assignments" verilog/v_hier_top.v:0026: WC_w1 cmt="" verilog/v_hier_top.v:0027: WC_w1b cmt="" verilog/v_hier_top.v:0028: WC_w3 cmt="" verilog/v_hier_top.v:0029: WC_w4 cmt="" verilog/v_hier_top.v:0037: asn_clk cmt="" verilog/v_hier_top.v:0011: clk cmt="/* pragma jsc_clk */" verilog/v_hier_top2.v:0009: clk cmt="" verilog/v_hier_top2.v:0018: iosig cmt="/* synthesis useioff = 1 //*synthesis fpga_attr = "BLAH=ON"//* synthesis fpga_pin = "A22"*/\n/* synthesis aftersemi*/\n// NetListName=F12_IO" verilog/v_recursive.v:0002: DEPTH cmt="" Verilog-Perl-3.482/t/test_utils.pl0000644000177100017500000000504314553624300017017 0ustar wsnyderwsnyder# DESCRIPTION: Perl ExtUtils: Common routines required by package tests # # Copyright 2000-2024 by Wilson Snyder. This program is free software; # you can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. use IO::File; use File::Copy; use strict; use vars qw($PERL); $PERL = "$^X -Iblib/arch -Iblib/lib -IPreproc/blib/arch -IPreproc/blib/lib"; mkdir 'test_dir',0777; unlink "test_dir/verilog"; # Symlink made in vpassert test will mess up others if (!$ENV{HARNESS_ACTIVE}) { use lib '.'; use lib '..'; use lib "blib/lib"; use lib "blib/arch"; use lib "Preproc/blib/lib"; use lib "Preproc/blib/arch"; } sub run_system { # Run a system command, check errors my $command = shift; print "\t$command\n"; system "$command"; my $status = $?; ($status == 0) or die "%Error: Command Failed $command, $status, stopped"; } sub run_system_no_die { # Run a system command, check errors my $command = shift; print "\t$command\n"; system "$command"; return $?; } sub wholefile { my $file = shift; my $fh = IO::File->new ($file) or die "%Error: $! $file"; my $wholefile = join('',$fh->getlines()); $fh->close(); return $wholefile; } sub files_identical { my $fn1 = shift; # got my $fn2 = shift; # expected my $f1 = IO::File->new ($fn1) or die "%Error: $! $fn1,"; my $f2 = IO::File->new ($fn2) or die "%Error: $! $fn2,"; my @l1 = $f1->getlines(); my @l2 = $f2->getlines(); my $nl = $#l1; $nl = $#l2 if ($#l2 > $nl); for (my $l=0; $l<=$nl; $l++) { $l1[$l] =~ s/\r\n/\n/g if defined $l1[$l]; # Cleanup if on Windows $l2[$l] =~ s/\r\n/\n/g if defined $l2[$l]; if (($l1[$l]||"") ne ($l2[$l]||"")) { next if ($l1[$l]||"") =~ /Generated by vrename on/; warn ("%Warning: Line ".($l+1)." mismatches; $fn1 $fn2\n" ."GOT: ".($l1[$l]||"*EOF*\n") ."EXP: ".($l2[$l]||"*EOF*\n")); if ($ENV{HARNESS_UPDATE_GOLDEN}) { # Update golden files with current warn "%Warning: HARNESS_UPDATE_GOLDEN set: cp $fn1 $fn2\n"; copy($fn1,$fn2); } else { warn "To update reference: HARNESS_UPDATE_GOLDEN=1 ".join(" ",$0,@ARGV)."\n"; } return 0; } } return 1; } sub get_memory_usage { # Return memory usage. Return 0 if the system doesn't look quite right. my $fh = IO::File->new("getline || ""; my @stats = split /\s+/, $stat; return ($stats[0]||0)*4096; # vmsize } 1; Verilog-Perl-3.482/t/30_preproc.out0000644000177100017500000007754014030463163017001 0ustar wsnyderwsnyderverilog/inc_def09.v: // DESCRIPTION: Verilog-Perl: Verilog Test module verilog/inc_def09.v: // verilog/inc_def09.v: // This file ONLY is placed into the Public Domain, for any use, verilog/inc_def09.v: // without warranty, 2009 by Wilson Snyder. verilog/inc_def09.v: verilog/inc_def09.v: verilog/inc_def09.v: verilog/inc_def09.v: // Definitions as speced verilog/inc_def09.v: // Note there are trailing spaces, which spec doesn't show properly verilog/inc_def09.v: verilog/inc_def09.v: 'initial $display("start", "msg1" , "msg2", "end");' verilog/inc_def09.v: 'initial $display("start", "msg1" , "msg2" , "end");' verilog/inc_def09.v: 'initial $display("start", " msg1" , , "end");' verilog/inc_def09.v: 'initial $display("start", " msg1" , , "end");' verilog/inc_def09.v: 'initial $display("start", , "msg2 ", "end");' verilog/inc_def09.v: 'initial $display("start", , "msg2 ", "end");' verilog/inc_def09.v: 'initial $display("start", , , "end");' verilog/inc_def09.v: 'initial $display("start", , , "end");' verilog/inc_def09.v: 'initial $display("start", , , "end");' verilog/inc_def09.v: 'initial $display("start", , , "end");' verilog/inc_def09.v: //`D("msg1") // ILLEGAL: only one argument verilog/inc_def09.v: //`D() // ILLEGAL: only one empty argument verilog/inc_def09.v: //`D(,,) // ILLEGAL: more actual than formal arguments verilog/inc_def09.v: verilog/inc_def09.v: // Defaults: verilog/inc_def09.v: verilog/inc_def09.v: '$display(5,,2,,3);' verilog/inc_def09.v: '$display(5,,2,,3);' verilog/inc_def09.v: '$display(1,,"B",,3);' verilog/inc_def09.v: '$display(1 ,,"B",,3 );' verilog/inc_def09.v: '$display(5,,2,,);' verilog/inc_def09.v: '$display(5,,2,,);' verilog/inc_def09.v: //`MACRO1 ( 1 ) // ILLEGAL: b and c omitted, no default for c verilog/inc_def09.v: verilog/inc_def09.v: verilog/inc_def09.v: '$display(1,,,,3);' verilog/inc_def09.v: '$display(5,,,,"C");' verilog/inc_def09.v: '$display(5,,2,,"C");' verilog/inc_def09.v: '$display(5,,2,,"C");' verilog/inc_def09.v: '$display(5,,2,,"C");' verilog/inc_def09.v: '$display(5,,2,,"C");' verilog/inc_def09.v: verilog/inc_def09.v: verilog/inc_def09.v: '$display(1,,0,,"C");' verilog/inc_def09.v: '$display(1 ,,0,,"C");' verilog/inc_def09.v: '$display(5,,0,,"C");' verilog/inc_def09.v: '$display(5,,0,,"C");' verilog/inc_def09.v: //`MACRO3 // ILLEGAL: parentheses required verilog/inc_def09.v: verilog/inc_def09.v: verilog/inc_def09.v: 'b + 1 + 42 + a' verilog/inc_def09.v: 'b + 1 + 42 + a' verilog/inc_def09.v: verilog/inc_def09.v: // Local tests verilog/inc_def09.v: verilog/inc_def09.v: '"==)" "((((" () '; verilog/inc_def09.v: '"==)" "((((" () '; verilog/inc_def09.v: verilog/inc_def09.v: // Also check our line counting doesn't go bad verilog/inc_def09.v: verilog/inc_def09.v: verilog/inc_def09.v: verilog/inc_def09.v: verilog/inc_def09.v: verilog/inc_def09.v: verilog/inc_def09.v: verilog/inc_def09.v: verilog/inc_def09.v: verilog/inc_def09.v: verilog/inc_def09.v: '(6) (eq=al) ZOT' verilog/inc_def09.v: HERE-71 - Line71 verilog/inc_def09.v: verilog/inc_def09.v: //====================================================================== verilog/inc_def09.v: verilog/inc_nonl.v: // The lack of a newline on the next line is intentional verilog/inc_nonl.v: blah-no-newline-here> verilog/inc_ifdef.v: // DESCRIPTION: Verilog::Preproc: Example source code verilog/inc_ifdef.v: // This file ONLY is placed into the Public Domain, for any use, verilog/inc_ifdef.v: // without warranty, 2000-2012 by Wilson Snyder. verilog/inc_ifdef.v: verilog/inc_ifdef.v: verilog/inc_ifdef.v: verilog/inc_ifdef.v: verilog/inc_ifdef.v: verilog/inc_ifdef.v: verilog/inc_ifdef.v: verilog/inc_ifdef.v: verilog/inc_ifdef.v: $display("1A"); verilog/inc_ifdef.v: verilog/inc_ifdef.v: verilog/inc_ifdef.v: verilog/inc_ifdef.v: $display("2A"); verilog/inc_ifdef.v: verilog/inc_ifdef.v: verilog/inc_ifdef.v: verilog/inc_ifdef.v: verilog/inc_ifdef.v: verilog/inc_ifdef.v: $display("3AELSE"); verilog/inc_ifdef.v: verilog/inc_ifdef.v: verilog/inc_ifdef.v: verilog/inc_ifdef.v: verilog/inc_ifdef.v: verilog/inc_ifdef.v: verilog/inc_ifdef.v: verilog/inc_ifdef.v: verilog/inc_ifdef.v: verilog/inc_ifdef.v: verilog/inc_ifdef.v: verilog/inc_ifdef.v: verilog/inc_ifdef.v: verilog/inc_ifdef.v: verilog/inc_ifdef.v: verilog/inc_ifdef.v: verilog/inc_ifdef.v: verilog/inc_ifdef.v: verilog/inc_ifdef.v: verilog/inc2.v: // DESCRIPTION: Verilog::Preproc: Example source code verilog/inc2.v: // This file ONLY is placed into the Public Domain, for any use, verilog/inc2.v: // without warranty, 2000-2012 by Wilson Snyder. verilog/inc2.v: At file "verilog/inc2.v" line 4 inc3_a_filename_from_line_directive: // DESCRIPTION: Verilog::Preproc: Example source code inc3_a_filename_from_line_directive: // This file ONLY is placed into the Public Domain, for any use, inc3_a_filename_from_line_directive: // without warranty, 2000-2012 by Wilson Snyder. inc3_a_filename_from_line_directive: inc3_a_filename_from_line_directive: inc3_a_filename_from_line_directive: inc3_a_filename_from_line_directive: inc3_a_filename_from_line_directive: // FOO inc3_a_filename_from_line_directive: At file "inc3_a_filename_from_line_directive" line 10 inc3_a_filename_from_line_directive: inc3_a_filename_from_line_directive: inc3_a_filename_from_line_directive: // guard inc3_a_filename_from_line_directive: inc3_a_filename_from_line_directive: inc3_a_filename_from_line_directive: inc3_a_filename_from_line_directive: inc3_a_filename_from_line_directive: verilog/inc2.v: verilog/inc2.v: verilog/inc1.v: // DESCRIPTION: Verilog::Preproc: Example source code verilog/inc1.v: // This file ONLY is placed into the Public Domain, for any use, verilog/inc1.v: // without warranty, 2000-2012 by Wilson Snyder. verilog/inc1.v: text. verilog/inc1.v: verilog/inc1.v: //=========================================================================== verilog/inc1.v: // Includes verilog/inc1.v: verilog/inc1.v: //=========================================================================== verilog/inc1.v: // Defines verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: // DEF_A0 set by command line verilog/inc1.v: wire [3:0] q = { verilog/inc1.v: 1'b1 , verilog/inc1.v: 1'b0 , verilog/inc1.v: 1'b1 , verilog/inc1.v: 1'b0 verilog/inc1.v: }; verilog/inc1.v: verilog/inc1.v: text. verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: // but not verilog/inc1.v: foo /*this */ bar /* this too */ verilog/inc1.v: foobar2 verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: /*******COMMENT*****/ verilog/inc1.v: first part verilog/inc1.v: second part verilog/inc1.v: third part verilog/inc1.v: { verilog/inc1.v: a, verilog/inc1.v: b, verilog/inc1.v: c} verilog/inc1.v: Line_Preproc_Check 41 verilog/inc1.v: verilog/inc1.v: //=========================================================================== verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: deep deep verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: "Inside: `nosubst" verilog/inc1.v: "`nosubst" verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: x y LLZZ x y verilog/inc1.v: p q LLZZ p q r s LLZZ r s LLZZ p q LLZZ p q r s LLZZ r s verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: firstline comma","line LLZZ firstline comma","line verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: x y LLZZ "x" y // Simulators disagree here; some substitute "a" others do not verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: (a,b)(a,b) verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: $display("left side: \"right side\"") verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: bar_suffix more verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: $c("Zap(\"",bug1,"\");");; verilog/inc1.v: verilog/inc1.v: $c("Zap(\"","bug2","\");");; verilog/inc1.v: verilog/inc1.v: /* Define inside comment: `DEEPER and `WITHTICK */ verilog/inc1.v: // More commentary: `zap(bug1); `zap("bug2"); verilog/inc1.v: verilog/inc1.v: //====================================================================== verilog/inc1.v: // display passthru verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: // Doesn't expand verilog/inc1.v: verilog/inc1.v: initial begin verilog/inc1.v: //$display(`msg( \`, \`)); // Illegal verilog/inc1.v: $display("pre thrupre thrumid thrupost post: \"right side\""); verilog/inc1.v: $display("left side: \"right side\""); verilog/inc1.v: $display("left side: \"right side\""); verilog/inc1.v: $display("left_side: \"right_side\""); verilog/inc1.v: $display("na: \"right_side\""); verilog/inc1.v: $display("prep ( midp1 left_side midp2 ( outp ) ): \"right_side\""); verilog/inc1.v: $display("na: \"nana\""); verilog/inc1.v: $display("left_side right_side: \"left_side right_side\""); // Results vary between simulators verilog/inc1.v: $display(": \"\""); // Empty verilog/inc1.v: $display("left side: \"right side\""); verilog/inc1.v: $display("left side: \"right side\""); verilog/inc1.v: $display("standalone"); verilog/inc1.v: verilog/inc1.v: // Unspecified when the stringification has multiple lines verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: $display("twoline: \"first second\""); verilog/inc1.v: //$display(`msg(left side, \ right side \ )); // Not sure \{space} is legal. verilog/inc1.v: $write("*-* All Finished *-*\n"); verilog/inc1.v: $finish; verilog/inc1.v: end verilog/inc1.v: endmodule verilog/inc1.v: verilog/inc1.v: //====================================================================== verilog/inc1.v: // rt.cpan.org bug34429 verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: module add1 ( input wire d1, output wire o1); verilog/inc1.v: verilog/inc1.v: wire tmp_d1 = d1; verilog/inc1.v: wire tmp_o1 = tmp_d1 + 1; verilog/inc1.v: assign o1 = tmp_o1 ; // expansion is OK verilog/inc1.v: endmodule verilog/inc1.v: module add2 ( input wire d2, output wire o2); verilog/inc1.v: verilog/inc1.v: wire tmp_d2 = d2; verilog/inc1.v: wire tmp_o2 = tmp_d2 + 1; verilog/inc1.v: assign o2 = tmp_o2 ; // expansion is bad verilog/inc1.v: endmodule verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: // parameterized macro with arguments that are macros verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: generate for (i=0; i<(3); i=i+1) begin verilog/inc1.v: psl cover { m5k.f .ctl._ctl_mvldx_m1.d[i] & ~m5k.f .ctl._ctl_mvldx_m1.q[i] & !m5k.f .ctl._ctl_mvldx_m1.cond & ((m5k.f .ctl.alive & m5k.f .ctl.alive_m1))} report "fondNoRise: m5kc_fcl._ctl_mvldx_m1"; verilog/inc1.v: psl cover { ~m5k.f .ctl._ctl_mvldx_m1.d[i] & m5k.f .ctl._ctl_mvldx_m1.q[i] & !m5k.f .ctl._ctl_mvldx_m1.cond & ((m5k.f .ctl.alive & m5k.f .ctl.alive_m1))} report "fondNoFall: m5kc_fcl._ctl_mvldx_m1"; verilog/inc1.v: end endgenerate // ignorecmt verilog/inc1.v: verilog/inc1.v: //====================================================================== verilog/inc1.v: // Quotes are legal in protected blocks. Grr. verilog/inc1.v: module prot(); verilog/inc1.v: `protected verilog/inc1.v: I!#r#e6<_Q{{E2+]I3<[3s)1@D|'E''i!O?]jD>Jo_![Cl) verilog/inc1.v: #nj1]p,3^1~,="E@QZB\T)eU\pC#C|7=\$J$##A[@-@{Qk] verilog/inc1.v: `endprotected verilog/inc1.v: endmodule verilog/inc1.v: verilog/inc1.v: module prot2(); verilog/inc1.v: `pragma protect begin_protected verilog/inc1.v: `pragma protect encrypt_agent = "Whatever agent" verilog/inc1.v: `pragma protect encrypt_agent_info = "1.2.3" verilog/inc1.v: `pragma protect data_method = "aes128-cbc" verilog/inc1.v: `pragma protect key_keyowner = "Someone" verilog/inc1.v: `pragma protect key_keyname = "somekey", key_method = "rsa" verilog/inc1.v: `pragma protect key_block encoding = (enctype = "base64") verilog/inc1.v: wefjosdfjklajklasjkl verilog/inc1.v: `pragma protect data_block encoding = (enctype = "base64", bytes = 1059) verilog/inc1.v: I!#r#e6<_Q{{E2+]I3<[3s)1@D|'E''i!O?]jD>Jo_![Cl) verilog/inc1.v: #nj1]p,3^1~,="E@QZB\T)eU\pC#C|7=\$J$##A[@-@{Qk] verilog/inc1.v: `pragma protect end_protected verilog/inc1.v: `pragma reset protect verilog/inc1.v: endmodule verilog/inc1.v: verilog/inc1.v: module prot3(); verilog/inc1.v: //pragma protect begin_protected verilog/inc1.v: //pragma protect key_keyowner=Cadence Design Systems. verilog/inc1.v: //pragma protect key_keyname=CDS_KEY verilog/inc1.v: //pragma protect key_method=RC5 verilog/inc1.v: //pragma protect key_block verilog/inc1.v: zzZzZ/4ZzzZZZzzz4zZzZzZZZZzZzZ/Zz+33zZ2zz/zzzzzzzzZZZzZ4z+ZZZZz1 verilog/inc1.v: Z1ZzzzZZzZZzz9ZZZZ37zzZzZzZzzz9ZZzzZzZz9Zz64+z8Z7ZzZZZzzzzZZZzZz verilog/inc1.v: zzZzZZZzZ0463zzzzzZzZ6z00z4zZzzZZzzZzzzZZ8zzz09ZzZZZZZ== verilog/inc1.v: //pragma protect end_key_block verilog/inc1.v: //pragma protect digest_block verilog/inc1.v: ZzZZzzZ9ZZZZz2ZzzzZz/Zzzz8Z= verilog/inc1.v: //pragma protect end_digest_block verilog/inc1.v: //pragma protect data_block verilog/inc1.v: ZZZ8zZzz6ZZ/zZZ5zZZzzz3ZzzzZzZZZ6ZzZzZZZZZz1zzZZZZ7ZZZZz3Zzz+9zz verilog/inc1.v: 4zzz+8zZzzzzZzZZzzzZzz1Z7ZzZz+zZz8ZZZZzZ6ZzzZzZZzzZZzzZzzZzZzZzZ verilog/inc1.v: ZzzzzZ0zZz1ZzzZzzZzZzz== verilog/inc1.v: //pragma protect end_data_block verilog/inc1.v: //pragma protect digest_block verilog/inc1.v: Z4Z6zZzZ3Z7ZZ6zzZZZZzzzzZZZ= verilog/inc1.v: //pragma protect end_digest_block verilog/inc1.v: //pragma protect end_protected verilog/inc1.v: endmodule verilog/inc1.v: verilog/inc1.v: //====================================================================== verilog/inc1.v: // macro call with define that has comma verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: begin addr <= (({regs[6], regs[7]} + 1)); rd <= 1; end and begin addr <= (({regs[6], regs[7]})); wdata <= (rdata); wr <= 1; end verilog/inc1.v: begin addr <= ({regs[6], regs[7]} + 1); rd <= 1; end verilog/inc1.v: begin addr <= ({regs[6], regs[7]}); wdata <= (rdata); wr <= 1; end more verilog/inc1.v: verilog/inc1.v: //====================================================================== verilog/inc1.v: // include of parameterized file verilog/inc1.v: verilog/t_preproc_inc4.vh: // DESCRIPTION: Verilog::Preproc: Example source code verilog/t_preproc_inc4.vh: // This file ONLY is placed into the Public Domain, for any use, verilog/t_preproc_inc4.vh: // without warranty, 2000-2012 by Wilson Snyder. verilog/t_preproc_inc4.vh: verilog/t_preproc_inc4.vh: verilog/t_preproc_inc4.vh: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: //====================================================================== verilog/inc1.v: // macro call with , in {} verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: $blah("ab,cd","e,f"); verilog/inc1.v: $blah(this.logfile,vec); verilog/inc1.v: $blah(this.logfile,vec[1,2,3]); verilog/inc1.v: $blah(this.logfile,{blah.name(), " is not foo"}); verilog/inc1.v: verilog/inc1.v: //====================================================================== verilog/inc1.v: // pragma/default net type verilog/inc1.v: verilog/inc1.v: `pragma foo = 1 verilog/inc1.v: `default_nettype none verilog/inc1.v: `default_nettype uwire verilog/inc1.v: verilog/inc1.v: //====================================================================== verilog/inc1.v: // Ifdef verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: Line_Preproc_Check 245 verilog/inc1.v: verilog/inc1.v: //====================================================================== verilog/inc1.v: // bug84 verilog/inc1.v: verilog/inc1.v: // Hello, comments MIGHT not be legal/*more,,)cmts*/// But newlines ARE legal... who speced THAT? verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: (p,q) verilog/inc1.v: //Here verilog/inc1.v: verilog/inc1.v: //Too verilog/inc1.v: (x,y) verilog/inc1.v: Line_Preproc_Check 258 verilog/inc1.v: verilog/inc1.v: //====================================================================== verilog/inc1.v: // defines split arguments verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: beginend // 2001 spec doesn't require two tokens, so "beginend" ok verilog/inc1.v: beginend // 2001 spec doesn't require two tokens, so "beginend" ok verilog/inc1.v: "beginend" // No space "beginend" verilog/inc1.v: verilog/inc1.v: //====================================================================== verilog/inc1.v: // bug106 verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: `\esc`def verilog/inc1.v: verilog/inc1.v: Not a \`define verilog/inc1.v: verilog/inc1.v: //====================================================================== verilog/inc1.v: // misparsed comma in submacro verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: x,y)--bee submacro has comma paren verilog/inc1.v: verilog/inc1.v: //====================================================================== verilog/inc1.v: // bug191 verilog/inc1.v: verilog/inc1.v: $display("10 %d %d", $bits(foo), 10); verilog/inc1.v: verilog/inc1.v: //====================================================================== verilog/inc1.v: // 1800-2009 verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: //====================================================================== verilog/inc1.v: // bug202 verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: assign a3 = ~b3 ; verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: /* multi \ verilog/inc1.v: line1*/ \ verilog/inc1.v: /*multi \ verilog/inc1.v: line2*/ verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: /* multi verilog/inc1.v: line 3*/ verilog/inc1.v: def i verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: //====================================================================== verilog/inc1.v: verilog/inc1.v: // verilator NOT IN DEFINE verilog/inc1.v: verilog/inc1.v: /* verilator NOT PART verilog/inc1.v: OF DEFINE */ verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: // CMT NOT verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: 1 (nodef) verilog/inc1.v: 2 /* verilator PART OF DEFINE */ (hasdef) verilog/inc1.v: 3 (nodef) verilog/inc1.v: 4 /* verilator PART verilog/inc1.v: OF DEFINE */ (nodef) verilog/inc1.v: 5 also in verilog/inc1.v: also3 (nodef) verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: HAS a NEW verilog/inc1.v: LINE verilog/inc1.v: verilog/inc1.v: //====================================================================== verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: EXP: clxx_scen verilog/inc1.v: clxx_scen verilog/inc1.v: EXP: clxx_scen verilog/inc1.v: "clxx_scen" verilog/inc1.v: verilog/inc1.v: EXP: do if (start("verilog/inc1.v", 25)) begin message({"Blah-", "clx_scen", " end"}); end while(0); verilog/inc1.v: verilog/inc1.v: do verilog/inc1.v: /* synopsys translate_off */ verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: if (start("verilog/inc1.v", 372)) begin verilog/inc1.v: verilog/inc1.v: message({"Blah-", "clx_scen", " end"}); verilog/inc1.v: end verilog/inc1.v: /* synopsys translate_on */ verilog/inc1.v: while(0); verilog/inc1.v: verilog/inc1.v: //====================================================================== verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: //`ifndef def_fooed_2 `error "No def_fooed_2" `endif verilog/inc1.v: EXP: This is fooed verilog/inc1.v: This is fooed verilog/inc1.v: EXP: This is fooed_2 verilog/inc1.v: This is fooed_2 verilog/inc1.v: verilog/inc1.v: //====================================================================== verilog/inc1.v: verilog/inc1.v: np verilog/inc1.v: np verilog/inc1.v: //====================================================================== verilog/inc1.v: // It's unclear if the spec allows this; is text_macro_idenitfier before or after substitution? verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: //====================================================================== verilog/inc1.v: // Metaprogramming verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: hello3hello3hello3 verilog/inc1.v: hello4hello4hello4hello4 verilog/inc1.v: //====================================================================== verilog/inc1.v: // Include from stringification verilog/inc1.v: verilog/inc1.v: verilog/t_preproc_inc4.vh: // DESCRIPTION: Verilog::Preproc: Example source code verilog/t_preproc_inc4.vh: // This file ONLY is placed into the Public Domain, for any use, verilog/t_preproc_inc4.vh: // without warranty, 2000-2012 by Wilson Snyder. verilog/t_preproc_inc4.vh: verilog/t_preproc_inc4.vh: verilog/t_preproc_inc4.vh: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: //====================================================================== verilog/inc1.v: // Defines doing defines verilog/inc1.v: // Note the newline on the end - required to form the end of a define verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: Line_Preproc_Check 433 verilog/inc1.v: //====================================================================== verilog/inc1.v: // Quoted multiline - track line numbers, and insure \\n gets propagated verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: Line_Preproc_Check 439 verilog/inc1.v: "FOO \ verilog/inc1.v: BAR " "arg_line1 \ verilog/inc1.v: arg_line2" "FOO \ verilog/inc1.v: BAR " verilog/inc1.v: Line_Preproc_Check 442 verilog/inc1.v: //====================================================================== verilog/inc1.v: // bug283 verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: // EXP: abc verilog/inc1.v: verilog/inc1.v: abc verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: EXP: sonet_frame verilog/inc1.v: sonet_frame verilog/inc1.v: // verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: EXP: sonet_frame verilog/inc1.v: sonet_frame verilog/inc1.v: // This result varies between simulators verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: EXP: sonet_frame verilog/inc1.v: sonet_frame verilog/inc1.v: verilog/inc1.v: // The existance of non-existance of a base define can make a difference verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: EXP: module zzz ; endmodule verilog/inc1.v: module zzz ; endmodule verilog/inc1.v: module zzz ; endmodule verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: EXP: module a_b ; endmodule verilog/inc1.v: module a_b ; endmodule verilog/inc1.v: module a_b ; endmodule verilog/inc1.v: verilog/inc1.v: //====================================================================== verilog/inc1.v: // bug311 verilog/inc1.v: integer/*NEED_SPACE*/foo; verilog/inc1.v: //====================================================================== verilog/inc1.v: synth_test: verilog/inc1.v: // synopsys translate_off verilog/inc1.v: synthesis_turned_off verilog/inc1.v: // synthesis translate_on verilog/inc1.v: EXP: on verilog/inc1.v: //====================================================================== verilog/inc1.v: // bug441 verilog/inc1.v: module t; verilog/inc1.v: //----- verilog/inc1.v: // case provided verilog/inc1.v: // note this does NOT escape as suggested in the mail verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: initial begin : \`LEX_CAT(a[0],_assignment) verilog/inc1.v: $write("GOT%%m='%m' EXP='%s'\n", "t.\\`LEX_CAT(a[0],_assignment) "); end verilog/inc1.v: //----- verilog/inc1.v: // SHOULD(simulator-dependant): Backslash doesn't prevent arguments from verilog/inc1.v: // substituting and the \ staying in the expansion verilog/inc1.v: // Note space after name is important so when substitute it has ending whitespace verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: initial begin : \a[0]_assignment_a[1] verilog/inc1.v: $write("GOT%%m='%m' EXP='%s'\n", "t.\\a[0]_assignment_a[1] "); end verilog/inc1.v: verilog/inc1.v: //----- verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: // RULE: Ignoring backslash does NOT allow an additional expansion level verilog/inc1.v: // (Because ESC gets expanded then the \ has it's normal escape meaning) verilog/inc1.v: initial begin : \`CAT(pp,suffix) $write("GOT%%m='%m' EXP='%s'\n", "t.\\`CAT(pp,suffix) "); end verilog/inc1.v: verilog/inc1.v: //----- verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: // Similar to above; \ does not allow expansion after substitution verilog/inc1.v: initial begin : \`CAT(ff,bb) verilog/inc1.v: $write("GOT%%m='%m' EXP='%s'\n", "t.\\`CAT(ff,bb) "); end verilog/inc1.v: verilog/inc1.v: //----- verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: // MUST: Unknown macro with backslash escape stays as escaped symbol name verilog/inc1.v: initial begin : \`zzz verilog/inc1.v: $write("GOT%%m='%m' EXP='%s'\n", "t.\\`zzz "); end verilog/inc1.v: verilog/inc1.v: //----- verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: // SHOULD(simulator-dependant): Known macro with backslash escape expands verilog/inc1.v: initial begin : \`FOO verilog/inc1.v: $write("GOT%%m='%m' OTHER_EXP='%s'\n OUR_EXP='%s'", "t.bar ","t.\\`FOO "); end verilog/inc1.v: // SHOULD(simulator-dependant): Prefix breaks the above verilog/inc1.v: initial begin : \xx`FOO verilog/inc1.v: $write("GOT%%m='%m' EXP='%s'\n", "t.\\xx`FOO "); end verilog/inc1.v: verilog/inc1.v: //----- verilog/inc1.v: // MUST: Unknown macro not under call with backslash escape doesn't expand verilog/inc1.v: verilog/inc1.v: initial begin : \`UNKNOWN $write("GOT%%m='%m' EXP='%s'\n", "t.\\`UNKNOWN "); end verilog/inc1.v: //----- verilog/inc1.v: // MUST: Unknown macro not under call doesn't expand verilog/inc1.v: verilog/inc1.v: initial begin : \`DEF_NO_EXPAND $write("GOT%%m='%m' EXP='%s'\n", "t.\\`DEF_NO_EXPAND "); end verilog/inc1.v: verilog/inc1.v: //----- verilog/inc1.v: // bug441 derivative verilog/inc1.v: // SHOULD(simulator-dependant): Quotes doesn't prevent arguments from expanding (like backslashes above) verilog/inc1.v: verilog/inc1.v: initial $write("GOT='%s' EXP='%s'\n", "foo bar baz", "foo bar baz"); verilog/inc1.v: verilog/inc1.v: //----- verilog/inc1.v: // RULE: Because there are quotes after substituting STR, the `A does NOT expand verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: initial $write("GOT='%s' EXP='%s'\n", "foo `A(bar) baz", "foo `A(bar) baz"); verilog/inc1.v: verilog/inc1.v: //---- verilog/inc1.v: // bug845 verilog/inc1.v: verilog/inc1.v: initial $write("Slashed=`%s'\n", "1//2.3"); verilog/inc1.v: //---- verilog/inc1.v: // bug915 verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: initial verilog/inc1.v: $display("%s%s","a1","b2c3\n"); verilog/inc1.v: endmodule verilog/inc1.v: verilog/inc1.v: //====================================================================== verilog/inc1.v: //bug1225 verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: $display("RAM0"); verilog/inc1.v: $display("CPU"); verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: XXE_FAMILY = XXE_ verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: $display("XXE_ is defined"); verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: XYE_FAMILY = XYE_ verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: $display("XYE_ is defined"); verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: XXS_FAMILY = XXS_some verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: $display("XXS_some is defined"); verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: XYS_FAMILY = XYS_foo verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: $display("XYS_foo is defined"); verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: //==== verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: // NEVER verilog/inc1.v: verilog/inc1.v: //bug1227 verilog/inc1.v: verilog/inc1.v: (.mySig (myInterface.pa5), verilog/inc1.v: verilog/inc1.v: //====================================================================== verilog/inc1.v: // Stringify bug verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: `dbg_hdl(UVM_LOW, ("Functional coverage enabled: paramgrp")); verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: verilog/inc1.v: module pcc2_cfg; verilog/inc1.v: generate verilog/inc1.v: verilog/inc1.v: covergroup a @(posedge b); verilog/inc1.v: c: coverpoint d iff ((c) === 1'b1); endgroup verilog/inc1.v: a u_a; verilog/inc1.v: initial do begin $display ("DEBUG : %s [%m]", $sformatf ("Functional coverage enabled: u_a")); end while(0); verilog/inc1.v: endgenerate verilog/inc1.v: endmodule verilog/inc1.v: verilog/inc1.v: //====================================================================== verilog/inc1.v: // Verilog-Perl bug1668 verilog/inc1.v: verilog/inc1.v: "`NOT_DEFINED_STR" verilog/inc1.v: verilog/inc1.v: //====================================================================== verilog/inc1.v: // IEEE mandated predefines verilog/inc1.v: // undefineall should have no effect on these verilog/inc1.v: predef 0 0 verilog/inc1.v: predef 1 1 verilog/inc1.v: predef 2 2 verilog/inc1.v: predef 3 3 verilog/inc1.v: predef 10 10 verilog/inc1.v: predef 11 11 verilog/inc1.v: predef 20 20 verilog/inc1.v: predef 21 21 verilog/inc1.v: predef 22 22 verilog/inc1.v: predef 23 23 verilog/inc1.v: predef -2 -2 verilog/inc1.v: predef -1 -1 verilog/inc1.v: predef 0 0 verilog/inc1.v: predef 1 1 verilog/inc1.v: predef 2 2 verilog/inc1.v: Verilog-Perl-3.482/t/51_vrename_kwd.t0000755000177100017500000000263514553624300017266 0ustar wsnyderwsnyder#!/usr/bin/perl -w # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package # # Copyright 2000-2024 by Wilson Snyder. This program is free software; # you can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. use strict; use Test::More; BEGIN { plan tests => 6 } BEGIN { require "./t/test_utils.pl"; } print "Checking vrename...\n"; my $changefile = "test_dir/51_vrename_kwd_list.vrename"; { # -List my $cmd = "${PERL} ./vrename -changefile=$changefile -list --changelang --language 1364-1995 t/51_vrename_kwd.v"; run_system ($cmd); ok(1, "vrename list"); ok(files_identical($changefile, "t/51_vrename_kwd_list.out"), "diff"); } { # Try renaming - no change mkdir 'test_dir/t', 0777; my $cmd = ("${PERL} ./vrename -change --changefile=$changefile" ." -o test_dir t/51_vrename_kwd.v"); run_system ($cmd); ok(1, "vrename change same"); ok(files_identical("test_dir/t/51_vrename_kwd.v", "t/51_vrename_kwd_chg.out"), "diff"); } { # Try renaming - with change mkdir 'test_dir/t', 0777; my $cmd = ("${PERL} ./vrename -change --changefile=t/51_vrename_kwd_chg2.vrename" ." -o test_dir t/51_vrename_kwd.v"); run_system ($cmd); ok(1, "vrename change"); ok(files_identical("test_dir/t/51_vrename_kwd.v", "t/51_vrename_kwd_chg2.out"), "diff"); } Verilog-Perl-3.482/t/42_dumpcheck_2v.out0000644000177100017500000000124213234726611017673 0ustar wsnyderwsnydermodule bug278 ( iow, iw, ow); inout iow; input iw; output ow; endmodule module foo ( abcconst, def, noconnect, x, y); input [2:0] abcconst; input [31:0] def; input signed [3:0] noconnect; input x; input y; endmodule module foo2 ( x, y, z); output reg x; input y; input z; endmodule module pinorder4 ( ); wire [31:0] IPCD_const = 32'h1; wire [7:0] a_i; wire b_i; wire d_o; foo foo1 (.abcconst(3'h0), .def(IPCD_const), .noconnect(), .x(a_i), .y(b_i)); foo2 foo2 (.x(b_i), .y(d_o), .z(a_i[0])); foo foo3 (.abcconst(3'h0), .def(IPCD_const), .x(a_i), .y(b_i)); assign a_i = 0; assign b_i = 0; endmodule Verilog-Perl-3.482/t/42_dumpcheck_sv.out0000644000177100017500000000257013234726611020001 0ustar wsnyderwsnyderInterface:sv_if_ported File:verilog/v_sv_mod.v Port:clk Dir:in DataT: Array: Net:clk O DeclT:port NetT: DataT: Array: Interface:v_sv_intf File:verilog/v_sv_intf.v Net:byte_port DeclT:var NetT: DataT:v_sv_pkg::byte_t Array: Cell:subintf is-a:v_sv_intf2 Interface:v_sv_intf2 File:verilog/v_sv_intf.v Pin:* Net:* Interface:v_sv_intf2 File:verilog/v_sv_intf.v Net:byte_port DeclT:var NetT: DataT:v_sv_pkg::byte_t Array: ModPort:Master File:verilog/v_sv_intf.v Port:addr Dir:out DataT: Array: Port:data Dir:in DataT: Array: Module:v_sv_mod Kwd:module File:verilog/v_sv_mod.v Port:clk Dir:in DataT: Array: Port:intf Dir:interface DataT:v_sv_intf Array: Net:clk IO DeclT:port NetT: DataT: Array: Net:intf DeclT:port NetT: DataT:v_sv_intf Array: Cell:if_ported is-a:sv_if_ported Interface:sv_if_ported File:verilog/v_sv_mod.v Pin:clk Net:clk Port:clk Dir:in DataT: Array: Net:clk IO DeclT:port NetT: DataT: Array: Cell:intf is-a:v_sv_intf Interface:v_sv_intf File:verilog/v_sv_intf.v Cell:pgm is-a:v_sv_pgm Module:v_sv_pgm Kwd:program File:verilog/v_sv_pgm.v Module:v_sv_pgm Kwd:program File:verilog/v_sv_pgm.v #### Commentary: verilog/v_sv_mod.v:0010: clk cmt="// Import types" verilog/v_sv_mod.v:0010: intf cmt="" Verilog-Perl-3.482/t/80_vppreproc_simple.out0000644000177100017500000000013213741600370020705 0ustar wsnyderwsnyderAt file "verilog/inc2.v" line 4 At file "inc3_a_filename_from_line_directive" line 10 Verilog-Perl-3.482/t/51_vrename_kwd_chg2.vrename0000644000177100017500000000220213462302176021350 0ustar wsnyderwsnyder# DESCRIPTION: Verilog-Perl: Example Verilog for testing package # This file ONLY is placed into the Public Domain, for any use, # without warranty, 2010-2015 by Wilson Snyder. # # Original Signal Name Name to change to # -------------------- ----------------- # sigren "foo" "bar" sigren "\esc[ape]_2esc " "\chg_esc[ape]_2esc " sigren "\esc[ape]_2esc_nospace " "\chg_esc[ape]_2esc_nospace " sigren "\esc[ape]_2non " "chg_escape_2non" sigren "\esc[ape]_2non_nospace " "chg_escape_2non_nospace" sigren "\esc[ape]_2ext " "\chg_escape_2ext " sigren "\esc[ape]_2ext_nospace " "\chg_escape_2ext_nospace " sigren "non_2esc" "\chg_non[ape]_2esc " sigren "non_2esc_nospace" "\chg_non[ape]_2esc_nospace " sigren "non_2non" "chg_non_2non" sigren "non_2non_nospace" "chg_non_2non_nospace" sigren "non_2ext" "\chg_non_2ext " sigren "non_2ext_nospace" "\chg_non_2ext_nospace " sigren "ext_2esc" "\chg_ext[ape]_2esc " sigren "ext_2esc_nospace" "\chg_ext[ape]_2esc_nospace " sigren "ext_2non" "chg_ext_2non" sigren "ext_2non_nospace" "chg_ext_2non_nospace" sigren "ext_2ext" "\chg_ext_2ext " sigren "ext_2ext_nospace" "\chg_ext_2ext_nospace " Verilog-Perl-3.482/t/03_spaces.t0000755000177100017500000000216114553624300016231 0ustar wsnyderwsnyder#!/usr/bin/perl -w # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package # # Copyright 2007-2024 by Wilson Snyder. This program is free software; # you can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. use strict; use Test; BEGIN { require "./t/test_utils.pl"; } eval { use ExtUtils::Manifest; }; my $manifest = ExtUtils::Manifest::maniread(); plan tests => (1 + (keys %{$manifest})); ok(1); foreach my $filename (sort keys %{$manifest}) { if (!$ENV{VERILATOR_AUTHOR_SITE}) { skip("author only test (harmless)",1); next; } if ($filename =~ /README/) { # May not even exist skip("File doesn't need check (harmless)",1); next; } print "Space test of: $filename\n"; my $wholefile = wholefile($filename); if ($wholefile && $wholefile !~ /[ \t]+\n/ && $wholefile !~ /^[ \t]*[ ]+\t/) { ok(1); } elsif ($filename =~ m!\.out! || $filename =~ m!/gen/!) { skip("File doesn't need check (harmless)",1); } else { warn "%Error: $filename: Bad indentation\n"; ok(0); } } Verilog-Perl-3.482/t/20_getopt.opt0000644000177100017500000000015413234726611016613 0ustar wsnyderwsnyder// DESCRIPTION: Perl ExtUtils: Option file for testing Verilog::Getopt -Dread_opt_file=1 -y y_library_path Verilog-Perl-3.482/t/49_largeish.t0000755000177100017500000000720614553624300016570 0ustar wsnyderwsnyder#!/usr/bin/perl -w # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package # # Copyright 2000-2024 by Wilson Snyder. This program is free software; # you can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. use strict; use Test::More; use Time::HiRes qw(gettimeofday tv_interval); use Data::Dumper; $Data::Dumper::Indent = 1; BEGIN { plan tests => 4 } BEGIN { require "./t/test_utils.pl"; } use Verilog::SigParser; use Verilog::Preproc; use Verilog::Getopt; use Verilog::Netlist; use POSIX qw(); ###################################################################### our $nets = 10*1000; our $Opt_Sym_Size = 30; our $Opt_Spaced_Out = 0; # Lots of stuff that preprocessor can rip out our $Opt_Dir = $ENV{HARNESS_TEST_DIR}||"test_dir"; # Move to scratch disk for very large tests prep("${Opt_Dir}/largeish_1.v",1); prep("${Opt_Dir}/largeish_2.v",1+($nets/10)); prep("${Opt_Dir}/largeish_3.v",1+$nets); per_net_test('sigparser', 100000); per_net_test('netlist', 100000); unlink(glob("${Opt_Dir}/largeish_*")); # Fat, so don't keep around ###################################################################### sub prep { my $filename = shift; my $count = shift; my $fh = IO::File->new(">$filename"); print $fh "module largeish;\n"; my $wirefmt = " wire n%0".($Opt_Sym_Size-1)."d;\n"; # Each net is constant sized for (my $i=0; $i<$count; $i++) { printf $fh $wirefmt, $i; print $fh " "x1023,"\n" if $Opt_Spaced_Out; } print $fh "endmodule\n"; printf "Wrote $filename: %6.3f MB\n", (-s $filename)/1024/1024; } sub per_net_test { my $pack = shift; my $limit = shift; my (@mem, @time, @size, @names, @secPerB); $names[1] = "${Opt_Dir}/largeish_1.v"; $names[2] = "${Opt_Dir}/largeish_2.v"; $names[3] = "${Opt_Dir}/largeish_3.v"; $mem[0] = get_memory_usage(); $time[0] = [gettimeofday]; for (my $i=1; $i<4; $i++) { read_test($pack, $names[$i]); $size[$i] = -s $names[$i]; $mem[$i] = get_memory_usage(); $time[$i] = [gettimeofday]; } for (my $i=2; $i<4; $i++) { my $deltamem = $mem[$i]-$mem[0]; my $deltatime = tv_interval($time[$i-1],$time[$i]); my $mpn = $deltamem / $size[$i]; $secPerB[$i] = $deltatime / ($size[$i]/1024/1024); printf "For $pack $names[$i]: File %1.3f MB, %1.3f s, %1.3f MB, Alloced %1.3f MB, %1.1f Alloc/FileB %1.1f s/MB\n" , $size[$i]/1024/1024, $deltatime, $mem[$i]/1024/1024, $deltamem/1024/1024, $mpn, $secPerB[$i]; } ok(1, "run complete"); my $slope = $secPerB[3] / ($secPerB[2]||1); SKIP: { if ($slope > 0.5 && $slope < 2) { ok(1, "complexity"); } else { if (!$ENV{VERILATOR_AUTHOR_SITE} || $ENV{HARNESS_FAST}) { # It's somewhat sensitive unless there's a lot of loops, # and lots of loops is too slow for users to deal with. skip("waived, author only test",1); } else { warn "%Warning: ",$slope," non O(n) based on input file size, slope=$slope\n"; ok(0, "complexity"); } } } } sub read_test { my $pack = shift; my $filename = shift; if ($pack eq 'sigparser') { my $go = Verilog::Getopt->new(); my $pp = Verilog::Preproc->new(keep_comments=>1); my $parser = Verilog::SigParser->new(); #my $parser = Verilog::Parser->new(); #$pp->debug(99); $pp->open($filename); ##Preproc_Only_Test: while (defined($pp->getline())) {} $parser->parse_preproc_file($pp); $pp->open($filename); while (defined($pp->getline())) {} } elsif ($pack eq 'netlist') { my $nl = Verilog::Netlist->new(); $nl->read_file(filename=>$filename); $nl->delete; } else { die; } } Verilog-Perl-3.482/t/36_sigmany.t0000755000177100017500000000770414553624300016440 0ustar wsnyderwsnyder#!/usr/bin/perl -w # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package # # Copyright 2000-2024 by Wilson Snyder. This program is free software; # you can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. ###################################################################### # VERILOG_TEST_FILES="$V4/test_regress/t/t_case*.v" VERILOG_TEST_DEBUGIF=1 t/36_sigmany.t # (delete-matching-lines "^#\\|^ok \\|^1\\.\\.\\|^not ok") use strict; use Test; # Not Test::More due to skip usage use Data::Dumper; $Data::Dumper::Indent = 1; BEGIN { plan tests => 3 } BEGIN { require "./t/test_utils.pl"; } our $Any_Error; our $Got_Eof_Module; ###################################################################### package MyParser; use Verilog::SigParser; use strict; use base qw(Verilog::SigParser); sub module { my ($self,$kwd,$name)=@_; $Got_Eof_Module = 1 if $name eq '_GOT_EOF_MODULE'; } sub error { my ($self,$text,$token)=@_; my $fileline = $self->filename.":".$self->lineno; if ($text !~ /\`math/) { if (!$ENV{VERILOG_TEST_SILENT}) { warn ("%Warning: $fileline: $text\n"); $self->{_errored} = 1; $::Any_Error = 1; } else { warn ("-Silent-Warning: $fileline: $text\n"); } # Try to print source line if (my $fh=IO::File->new("<".$self->filename)) { my @lines = $fh->getlines; my $line = $lines[$self->lineno-1] || ""; $line =~ s/^\s+//; warn ("\t".$line) if $line; $fh->close(); } } } ###################################################################### package main; use Verilog::SigParser; use Verilog::Preproc; use Verilog::Getopt; ok(1); my @files; if ($ENV{VERILOG_TEST_FILES}) { ok(1); @files = split(/:/,$ENV{VERILOG_TEST_FILES}); @files = map {glob $_} @files; } else { skip("VERILOG_TEST_FILES not set (harmless)",1); # export VERILOG_TEST_FILES="$V4/test_regress/t/t_case*.v" @files = glob("verilog/*.v"); @files = grep {!m!/inc!} @files; } check_series(@files); ###################################################################### sub check_series { my @files = @_; $Any_Error = 0; foreach my $file (@files) { read_test($file); } ok(!$Any_Error); } sub read_test { my $filename = shift; my $parser = one_parse($filename, 0); if ($ENV{VERILOG_TEST_DEBUGIF} && $parser->{_errored}) { print "======== REPARSING w/debug\n"; one_parse($filename, 9); } } sub one_parse { my $filename = shift; my $debug = shift; $Got_Eof_Module = undef; print "="x70,"\n"; print "read $filename\n"; my $opt = new Verilog::Getopt; # Used to do this so we can read pre-vpassert'ed files, # but now we require a `include std_defines in all sources # even though a lint run may not indicate it's needed # (since lint runs pre-vpassert.) # $opt->define('__message_on',"1'b0"); if ($filename =~ m!(.*)/!) { # Allow includes in same dir as the test my $fdir = $1; $opt->incdir($fdir); $opt->module_dir ($fdir); } my $pp = Verilog::Preproc->new(keep_comments=>0, include_open_nonfatal=>0, options=>$opt); my $parser = new MyParser(); # Suck in std:: before enabling debug dumps $parser->std; $parser->debug($debug || $ENV{VERILOG_TEST_DEBUG}); $pp->open($filename); if ($ENV{VERILOG_TEST_KEYWORDS}) { $parser->parse("`begin_keywords \"1364-2001\" "); } $parser->reset; # Similar to $parser->parse_preproc_file($pp); # but we want to stuff a module before the EOF while (defined(my $line = $pp->getline())) { $parser->parse ($line); } $parser->parse("module _GOT_EOF_MODULE; endmodule\n"); $parser->eof; if (!$Any_Error && !$Got_Eof_Module) { warn "%Warning: $filename: Never parsed fake module at EOF\n"; $parser->{_errored} = 1; $::Any_Error = 1; } print Dumper($parser->{symbol_table}) if $parser->debug; return $parser; } Verilog-Perl-3.482/t/42_dumpcheck_v2kv.out0000644000177100017500000000043313234726611020235 0ustar wsnyderwsnydermodule v_v2k ( clk, rst, sig1, sig2); parameter WIDTH = 16; input clk; wire [1:2][3:4] netmd; input rst; input [WIDTH:0] sig1; output reg [WIDTH:0] sig2; v_v2k_sub sub (.net1(netmd[1])); endmodule module v_v2k_sub ( net1); input [3:4] net1; endmodule Verilog-Perl-3.482/t/48_leak.t0000755000177100017500000000520314553624300015700 0ustar wsnyderwsnyder#!/usr/bin/perl -w # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package # # Copyright 2000-2024 by Wilson Snyder. This program is free software; # you can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. use strict; use Test; # Test::More leaks itself! use Data::Dumper; $Data::Dumper::Indent = 1; BEGIN { eval "use Devel::Leak;"; } # Optional BEGIN { plan tests => 2 } BEGIN { require "./t/test_utils.pl"; } use Verilog::SigParser; use Verilog::Preproc; use Verilog::Getopt; use Verilog::Netlist; use POSIX qw(); ###################################################################### my $mem = get_memory_usage(); my $loops = 50; # At least 10 my $mem_end; my $mem_mid; my $handle; for (my $i=0; $i<$loops; $i++) { test(); my $newmem = get_memory_usage(); my $delta = $newmem - $mem; printf "$i: Memory %6.3f MB Alloced %6.3f MB\n" , $newmem/1024/1024, $delta/1024/1024 if $delta; $mem_mid = $newmem if $i==int($loops/2)-1; $mem_end = $newmem if $i==$loops-1; # The Devel checks must complete before $mem_mid is sampled, as they use memory if (0 && $Devel::Leak::VERSION) { Devel::Leak::NoteSV($handle) if $i==int($loops/2)-4; Devel::Leak::CheckSV($handle) if $i==int($loops/2)-3; #warn "EXITING" if $i==int($loops/2)-3; #POSIX::_exit(10) if $i==int($loops/2)-3; } $mem = $newmem; } ok(1); if ($mem == 0) { skip("get_memory_usage isn't supported",1); } elsif ($mem_end <= $mem_mid) { ok(1); } else { warn "%Warning: Leaked ",int(($mem_end-$mem_mid)/($loops/2))," bytes per parse\n"; if (!$ENV{VERILATOR_AUTHOR_SITE} || $ENV{HARNESS_FAST}) { # It's somewhat sensitive unless there's a lot of loops, # and lots of loops is too slow for users to deal with. skip("leaked, but author only test",1); } else { ok(0); } } ###################################################################### sub test { read_test("verilog/v_hier_sub.v"); read_test("verilog/parser_bugs.v"); read_test("verilog/pinorder.v"); read_test("verilog/parser_sv.v"); } sub read_test { my $filename = shift; my $go = Verilog::Getopt->new(); my $pp = Verilog::Preproc->new(keep_comments=>1); my $parser = Verilog::SigParser->new(); #my $parser = Verilog::Parser->new(); $pp->open($filename); ##Preproc_Only_Test: while (defined($pp->getline())) {} $parser->parse_preproc_file($pp); my $nl = Verilog::Netlist->new(); $nl->read_file(filename=>"verilog/v_hier_sub.v"); $nl->delete; #print Dumper($nl); use Devel::Peek; print "\nPEEK: \n";Dump(\$nl); } Verilog-Perl-3.482/t/35_sigparser.out0000644000177100017500000021667214035374034017337 0ustar wsnyderwsnyderverilog/v_hier_subprim.v:001: COMMENT '// DESCRIPTION: Verilog-Perl: Example Verilog for testing package' verilog/v_hier_subprim.v:002: COMMENT '//' verilog/v_hier_subprim.v:003: COMMENT '// This file ONLY is placed into the Public Domain, for any use,' verilog/v_hier_subprim.v:004: COMMENT '// without warranty, 2000-2012 by Wilson Snyder.' verilog/v_hier_subprim.v:006: COMMENT '// surefire lint_off UDPUNS' verilog/v_hier_subprim.v:008: MODULE 'primitive' 'v_hier_prim' undef '0' verilog/v_hier_subprim.v:008: COMMENT '/*AUTOARG*/' verilog/v_hier_subprim.v:009: COMMENT '// Outputs' verilog/v_hier_subprim.v:010: PORT 'q' 'module' '' '' '' '1' verilog/v_hier_subprim.v:011: COMMENT '// Inputs' verilog/v_hier_subprim.v:012: PORT 'a' 'module' '' '' '' '2' verilog/v_hier_subprim.v:014: VAR 'port' 'q' 'module' '' '' '' '' verilog/v_hier_subprim.v:014: PORT 'q' 'module' 'output' '' '' '0' verilog/v_hier_subprim.v:015: VAR 'port' 'a' 'module' '' '' '' '' verilog/v_hier_subprim.v:015: PORT 'a' 'module' 'input' '' '' '0' verilog/v_hier_subprim.v:022: ENDMODULE 'endprimitive' verilog/v_hier_subprim.v:025: MODULE 'module' 'bug27070' undef '1' verilog/v_hier_subprim.v:027: VAR 'parameter' 'TAP' 'module' '' '' '' '4'b1001' verilog/v_hier_subprim.v:028: ENDMODULE 'endmodule' verilog/v_hier_subprim.v:032: MODULE 'module' 'bug893' undef '1' verilog/v_hier_subprim.v:033: VAR 'var' 'r' 'module' '' 'reg' '' '' verilog/v_hier_subprim.v:035: ENDMODULE 'endmodule' verilog/v_hier_sub.v:001: COMMENT '// DESCRIPTION: Verilog-Perl: Example Verilog for testing package' verilog/v_hier_sub.v:002: COMMENT '//' verilog/v_hier_sub.v:003: COMMENT '// This file ONLY is placed into the Public Domain, for any use,' verilog/v_hier_sub.v:004: COMMENT '// without warranty, 2000-2012 by Wilson Snyder.' verilog/v_hier_sub.v:006: MODULE 'module' 'v_hier_sub' undef '0' verilog/v_hier_sub.v:006: COMMENT '/*AUTOARG*/' verilog/v_hier_sub.v:007: VAR 'port' 'clk' 'module' '' '' '' '' verilog/v_hier_sub.v:007: PORT 'clk' 'module' 'input' '' '' '1' verilog/v_hier_sub.v:008: VAR 'port' 'avec' 'module' '' '[3:0]' '' '' verilog/v_hier_sub.v:008: PORT 'avec' 'module' 'input' '[3:0]' '' '2' verilog/v_hier_sub.v:008: COMMENT '// Comment for v_hier_sub, avec' verilog/v_hier_sub.v:009: COMMENT '/* Comment for v_hier_sub, qvec */' verilog/v_hier_sub.v:009: VAR 'port' 'qvec' 'module' '' '[3:0]' '' '' verilog/v_hier_sub.v:009: PORT 'qvec' 'module' 'output' '[3:0]' '' '3' verilog/v_hier_sub.v:012: VAR 'parameter' 'FROM_DEFPARAM' 'module' '' '' '' '1' verilog/v_hier_sub.v:014: VAR 'net' 'a1' 'module' 'supply1' '' '' '' verilog/v_hier_sub.v:020: COMMENT '// Outputs' verilog/v_hier_sub.v:019: INSTANT 'v_hier_subsub' 'subsub0' '' verilog/v_hier_sub.v:017: PARAMPIN 'IGNORED' ''sh20' '1' verilog/v_hier_sub.v:021: PIN 'q' 'qvec[0]' '1' verilog/v_hier_sub.v:022: COMMENT '// Inputs' verilog/v_hier_sub.v:023: PIN 'a' 'a1' '2' verilog/v_hier_sub.v:023: ENDCELL '' verilog/v_hier_sub.v:023: COMMENT '// Comment for subsub cell' verilog/v_hier_sub.v:027: VAR 'genvar' 'K' 'module' '' '' '' '' verilog/v_hier_sub.v:027: VAR 'genvar' 'K_UNUSED' 'module' '' '' '' '' verilog/v_hier_sub.v:029: COMMENT '// By pin position, inside generate' verilog/v_hier_sub.v:030: INSTANT 'v_hier_subsub' 'subsub2' '' verilog/v_hier_sub.v:030: PIN '' 'qvec[2]' '1' verilog/v_hier_sub.v:030: PIN '' '1'b0' '2' verilog/v_hier_sub.v:030: ENDCELL '' verilog/v_hier_sub.v:034: FUNCTION 'function' 'foo' '' verilog/v_hier_sub.v:035: ATTRIBUTE '(* attribute *)' verilog/v_hier_sub.v:036: COMMENT '/* synopsys metacommenttest */' verilog/v_hier_sub.v:037: VAR 'port' 'not_part_of_pinlist' 'function' '' '' '' '' verilog/v_hier_sub.v:037: PORT 'not_part_of_pinlist' 'function' 'input' '' '' '0' verilog/v_hier_sub.v:039: ENDTASKFUNC 'endfunction' verilog/v_hier_sub.v:041: ENDMODULE 'endmodule' verilog/parser_bugs.v:001: COMMENT '// Not legal:' verilog/parser_bugs.v:002: COMMENT '// end : ADDRESS_TEST_BLOCK // See 9.8.1' verilog/parser_bugs.v:003: COMMENT '// `define at EOF with no newline' verilog/parser_bugs.v:005: MODULE 'module' 'bug26141' undef '0' verilog/parser_bugs.v:006: VAR 'net' 'b' 'module' 'wire' '[0:3]' '' '' verilog/parser_bugs.v:007: VAR 'net' 'a' 'module' 'wire' '' '' 'b[2]' verilog/parser_bugs.v:008: ENDMODULE 'endmodule' verilog/parser_bugs.v:010: MODULE 'module' 'bug26940' undef '0' verilog/parser_bugs.v:011: ATTRIBUTE '(* attribute *)' verilog/parser_bugs.v:012: CONTASSIGN 'assign' 'q' '{1'b0,a}+{1'b0,b}' verilog/parser_bugs.v:014: INSTANT 'adder' 'u_add' '' verilog/parser_bugs.v:014: PIN 'q' 'q' '1' verilog/parser_bugs.v:014: PIN 'a' 'd' '2' verilog/parser_bugs.v:014: PIN 'b' 'd' '3' verilog/parser_bugs.v:014: ENDCELL '' verilog/parser_bugs.v:020: ENDMODULE 'endmodule' verilog/parser_bugs.v:022: MODULE 'module' 'bug26968' undef '0' verilog/parser_bugs.v:023: VAR 'var' 'vect' 'module' '' 'reg [4:0]' '' '5'b10100' verilog/parser_bugs.v:024: VAR 'net' 'tmp' 'module' 'wire' '[4:0]' '' '{vect[0],vect[1],vect[2],vect[3],vect[4]}' verilog/parser_bugs.v:028: ENDMODULE 'endmodule' verilog/parser_bugs.v:030: MODULE 'module' 'bug26969' undef '0' verilog/parser_bugs.v:030: VAR 'port' 'ad' 'module' '' '[31:0]' '' '' verilog/parser_bugs.v:030: PORT 'ad' 'module' 'input' '[31:0]' '' '1' verilog/parser_bugs.v:030: VAR 'port' 'regff' 'module' '' '[15:0]' '' '' verilog/parser_bugs.v:030: PORT 'regff' 'module' 'output' '[15:0]' '' '2' verilog/parser_bugs.v:030: VAR 'port' 'read' 'module' '' '[31:0]' '' '' verilog/parser_bugs.v:030: PORT 'read' 'module' 'input' '[31:0]' '' '3' verilog/parser_bugs.v:031: INSTANT 'bufif0' 'ad_drv' '[31:0]' verilog/parser_bugs.v:031: PIN '' 'ad' '1' verilog/parser_bugs.v:031: PIN '' '{16'b0,regff}' '2' verilog/parser_bugs.v:031: PIN '' 'read' '3' verilog/parser_bugs.v:031: ENDCELL '' verilog/parser_bugs.v:032: ENDMODULE 'endmodule' verilog/parser_bugs.v:034: MODULE 'module' 'bug26970' undef '0' verilog/parser_bugs.v:035: VAR 'parameter' 'A' 'module' '' '' '' '2'b1' verilog/parser_bugs.v:035: VAR 'parameter' 'B' 'module' '' '' '' '3'b0' verilog/parser_bugs.v:036: VAR 'parameter' 'x' 'module' '' '' '' '{B,B,B,A,A,B}' verilog/parser_bugs.v:037: ENDMODULE 'endmodule' verilog/parser_bugs.v:039: MODULE 'module' 'bug26997' undef '0' verilog/parser_bugs.v:040: INSTANT 'MUX_REG_8x8' 'PAGE_REG_B3' '' verilog/parser_bugs.v:041: PIN 'CLK' 'CLK' '1' verilog/parser_bugs.v:042: COMMENT '/* .IN (DATA_RES[31:24]), .OUT (PAGE[31:24]), .EN_IN (EN_B3), .EN_OUT (PAGE_SEL), */' verilog/parser_bugs.v:048: PIN 'TC' '' '2' verilog/parser_bugs.v:049: PIN 'TD' '' '3' verilog/parser_bugs.v:050: PIN 'TQ' '' '4' verilog/parser_bugs.v:050: ENDCELL '' verilog/parser_bugs.v:051: ENDMODULE 'endmodule' verilog/parser_bugs.v:053: MODULE 'module' 'bug27013' undef '0' verilog/parser_bugs.v:054: INSTANT 'submod' 'u1' '' verilog/parser_bugs.v:054: PIN '' '0' '1' verilog/parser_bugs.v:054: ENDCELL '' verilog/parser_bugs.v:055: INSTANT 'submod' 'u2' '' verilog/parser_bugs.v:055: PIN '' '1' '1' verilog/parser_bugs.v:055: ENDCELL '' verilog/parser_bugs.v:056: ENDMODULE 'endmodule' verilog/parser_bugs.v:058: MODULE 'module' 'bug27036' undef '0' verilog/parser_bugs.v:059: VAR 'var' 'a_fifo_cam_indices' 'module' '' 'reg [2:0]' '[3:0]' '' verilog/parser_bugs.v:059: VAR 'var' 'lt_fifo_cam_indices' 'module' '' 'reg [2:0]' '[5:0]' '' verilog/parser_bugs.v:060: VAR 'net' 'db0_a_fifo_cam_indices' 'module' 'wire' '[2:0]' '' 'a_fifo_cam_indices[0]' verilog/parser_bugs.v:061: ENDMODULE 'endmodule' verilog/parser_bugs.v:063: MODULE 'module' 'bug27037' undef '0' verilog/parser_bugs.v:064: VAR 'var' 'mem' 'module' '' 'reg' '[12:2]' '' verilog/parser_bugs.v:065: VAR 'var' 'i' 'module' '' 'reg [7:0]' '' '' verilog/parser_bugs.v:066: ENDMODULE 'endmodule' verilog/parser_bugs.v:068: MODULE 'module' 'bug27039' undef '0' verilog/parser_bugs.v:069: VAR 'var' 'i' 'module' '' 'integer' '' '' verilog/parser_bugs.v:070: ENDMODULE 'endmodule' verilog/parser_bugs.v:072: MODULE 'module' 'bug27045' undef '0' verilog/parser_bugs.v:073: VAR 'port' 'clk' 'module' '' '' '' '' verilog/parser_bugs.v:073: PORT 'clk' 'module' 'input' '' '' '1' verilog/parser_bugs.v:073: VAR 'port' 'reset' 'module' '' '' '' '' verilog/parser_bugs.v:073: PORT 'reset' 'module' 'input' '' '' '2' verilog/parser_bugs.v:074: VAR 'port' 'd' 'module' '' '[7:0]' '' '' verilog/parser_bugs.v:074: PORT 'd' 'module' 'input' '[7:0]' '' '3' verilog/parser_bugs.v:075: VAR 'port' 'q' 'module' '' 'reg [7:0]' '' '' verilog/parser_bugs.v:075: PORT 'q' 'module' 'output' 'reg [7:0]' '' '4' verilog/parser_bugs.v:076: VAR 'parameter' 'REG_DELAY' 'module' '' '' '' '0' verilog/parser_bugs.v:079: ENDMODULE 'endmodule' verilog/parser_bugs.v:081: MODULE 'module' 'bug27062' undef '0' verilog/parser_bugs.v:081: VAR 'port' 'D' 'module' '' '' '' '' verilog/parser_bugs.v:081: PORT 'D' 'module' 'input' '' '' '1' verilog/parser_bugs.v:081: VAR 'port' 'Q' 'module' '' '' '' '' verilog/parser_bugs.v:081: PORT 'Q' 'module' 'output' '' '' '2' verilog/parser_bugs.v:082: INSTANT 'p' '' '' verilog/parser_bugs.v:082: PIN '' 'Q' '1' verilog/parser_bugs.v:082: PIN '' 'D' '2' verilog/parser_bugs.v:082: ENDCELL '' verilog/parser_bugs.v:083: ENDMODULE 'endmodule' verilog/parser_bugs.v:087: MODULE 'module' 'bug27066' undef '0' verilog/parser_bugs.v:088: VAR 'var' 'i' 'module' '' 'integer' '' '' verilog/parser_bugs.v:089: VAR 'var' 't' 'module' '' 'time' '' '' verilog/parser_bugs.v:090: VAR 'var' 'rt' 'module' '' 'realtime' '' '' verilog/parser_bugs.v:091: FUNCTION 'function' 'toint' 'integer' verilog/parser_bugs.v:092: VAR 'port' 'y' 'function' '' 'integer' '' '' verilog/parser_bugs.v:092: PORT 'y' 'function' 'input' 'integer' '' '0' verilog/parser_bugs.v:093: VAR 'port' 'x' 'function' '' '[15:0]' '' '' verilog/parser_bugs.v:093: PORT 'x' 'function' 'input' '[15:0]' '' '0' verilog/parser_bugs.v:095: ENDTASKFUNC 'endfunction' verilog/parser_bugs.v:096: ENDMODULE 'endmodule' verilog/parser_bugs.v:098: MODULE 'module' 'bug27067' undef '0' verilog/parser_bugs.v:101: ENDMODULE 'endmodule' verilog/parser_bugs.v:103: MODULE 'module' 'bug27072' undef '0' verilog/parser_bugs.v:104: VAR 'port' 'sum' 'module' '' 'reg' '' '' verilog/parser_bugs.v:104: PORT 'sum' 'module' 'output' 'reg' '' '1' verilog/parser_bugs.v:105: VAR 'port' 'ci' 'module' 'wire' '' '' '' verilog/parser_bugs.v:105: PORT 'ci' 'module' 'input' '' '' '2' verilog/parser_bugs.v:106: ENDMODULE 'endmodule' verilog/parser_bugs.v:109: MODULE 'module' 'spec' undef '0' verilog/parser_bugs.v:122: ENDMODULE 'endmodule' verilog/parser_bugs.v:124: MODULE 'module' 'bugevent' undef '0' verilog/parser_bugs.v:125: VAR 'var' 'e' 'module' '' 'event' '' '' verilog/parser_bugs.v:128: ENDMODULE 'endmodule' verilog/parser_bugs.v:130: MODULE 'module' 'bugio' undef '0' verilog/parser_bugs.v:130: VAR 'port' 'a' 'module' '' '[31:0]' '' '' verilog/parser_bugs.v:130: PORT 'a' 'module' 'input' '[31:0]' '' '1' verilog/parser_bugs.v:130: VAR 'port' 'a2' 'module' '' '[31:0]' '' '' verilog/parser_bugs.v:130: PORT 'a2' 'module' 'input' '[31:0]' '' '2' verilog/parser_bugs.v:130: VAR 'port' 'o' 'module' '' '[15:0]' '' '' verilog/parser_bugs.v:130: PORT 'o' 'module' 'output' '[15:0]' '' '3' verilog/parser_bugs.v:130: VAR 'port' 'o2' 'module' '' '[15:0]' '' '' verilog/parser_bugs.v:130: PORT 'o2' 'module' 'output' '[15:0]' '' '4' verilog/parser_bugs.v:130: VAR 'port' 'ibit' 'module' '' '' '' '' verilog/parser_bugs.v:130: PORT 'ibit' 'module' 'input' '' '' '5' verilog/parser_bugs.v:131: ENDMODULE 'endmodule' verilog/parser_bugs.v:133: MODULE 'module' 'buglocal' undef '0' verilog/parser_bugs.v:140: CONTASSIGN 'assign' 'VDD' '1'b0' verilog/parser_bugs.v:141: CONTASSIGN 'assign' 'VSS' '1'b1' verilog/parser_bugs.v:142: VAR 'net' 'xxout' 'module' 'wire' '[71:0]' '' 'xxin' verilog/parser_bugs.v:149: INSTANT 'nmos' '' '' verilog/parser_bugs.v:149: PARAMPIN '' 'PullTime' '1' verilog/parser_bugs.v:149: PARAMPIN '' 'PullTime' '2' verilog/parser_bugs.v:149: PARAMPIN '' '0' '3' verilog/parser_bugs.v:149: PIN '' 'PT' '1' verilog/parser_bugs.v:149: PIN '' 'PU' '2' verilog/parser_bugs.v:149: PIN '' '1'b1' '3' verilog/parser_bugs.v:149: ENDCELL '' verilog/parser_bugs.v:150: INSTANT 'pulldown' 'pullinst' '' verilog/parser_bugs.v:150: PIN '' 'r' '1' verilog/parser_bugs.v:150: ENDCELL '' verilog/parser_bugs.v:152: DEFPARAM 'defparam' 'x.y.z.PAR' '1' verilog/parser_bugs.v:154: INSTANT 'cdrv' 'clk' '' verilog/parser_bugs.v:154: PIN '' 'clk' '1' verilog/parser_bugs.v:154: ENDCELL '' verilog/parser_bugs.v:162: VAR 'net' '\33escapeneeded ' 'module' 'wire' '' '' '1'b1' verilog/parser_bugs.v:163: VAR 'net' '\33escapenewlineend ' 'module' 'wire' '' '' '1'b1' verilog/parser_bugs.v:165: VAR 'net' 'noescapenewlineend' 'module' 'wire' '' '' '1'b1' verilog/parser_bugs.v:167: VAR 'net' 'noescapespaceend' 'module' 'wire' '' '' '1'b1' verilog/parser_bugs.v:169: ENDMODULE 'endmodule' verilog/parser_bugs.v:171: MODULE 'module' 'v2kparam' undef '0' verilog/parser_bugs.v:172: VAR 'parameter' 'WIDTH' 'module' '' '' '' '1' verilog/parser_bugs.v:173: VAR 'parameter' 'LENGTH' 'module' '' '' '' '1' verilog/parser_bugs.v:173: VAR 'parameter' 'LENGTH2' 'module' '' '' '' '1' verilog/parser_bugs.v:174: VAR 'port' 'myout' 'module' '' '[WIDTH-1:0]' '' '' verilog/parser_bugs.v:174: PORT 'myout' 'module' 'output' '[WIDTH-1:0]' '' '1' verilog/parser_bugs.v:175: VAR 'port' 'myin' 'module' '' '[LENGTH-1:0]' '' '' verilog/parser_bugs.v:175: PORT 'myin' 'module' 'input' '[LENGTH-1:0]' '' '2' verilog/parser_bugs.v:175: VAR 'port' 'myinb' 'module' '' '[LENGTH-1:0]' '' '' verilog/parser_bugs.v:175: PORT 'myinb' 'module' 'input' '[LENGTH-1:0]' '' '3' verilog/parser_bugs.v:177: CONTASSIGN 'assign' 'myout' 'myin^myinb^$callemptyparens' verilog/parser_bugs.v:178: ENDMODULE 'endmodule' verilog/parser_bugs.v:180: MODULE 'module' 'foreqn' undef '0' verilog/parser_bugs.v:180: PORT 'in' 'module' '' '' '' '1' verilog/parser_bugs.v:181: VAR 'port' 'in' 'module' '' '[1:0]' '' '' verilog/parser_bugs.v:181: PORT 'in' 'module' 'input' '[1:0]' '' '0' verilog/parser_bugs.v:182: VAR 'var' 'a' 'module' '' 'reg' '' '' verilog/parser_bugs.v:182: VAR 'var' 'b' 'module' '' 'reg' '' '' verilog/parser_bugs.v:183: VAR 'var' 'c' 'module' '' 'reg [1:0]' '' '' verilog/parser_bugs.v:188: ENDMODULE 'endmodule' verilog/parser_bugs.v:190: MODULE 'module' 'colonslash' undef '0' verilog/parser_bugs.v:193: COMMENT '//Error' verilog/parser_bugs.v:195: COMMENT '/*Another comment*/' verilog/parser_bugs.v:199: ENDMODULE 'endmodule' verilog/parser_bugs.v:201: MODULE 'module' 'enums' undef '0' verilog/parser_bugs.v:202: VAR 'var' 'light' 'module' '' 'enum' '' '' verilog/parser_bugs.v:203: VAR 'var' 'state' 'module' '' 'integer' '' '' verilog/parser_bugs.v:203: VAR 'var' 'next' 'module' '' 'integer' '' '' verilog/parser_bugs.v:204: VAR 'var' 'medal' 'module' '' 'enum' '' '' verilog/parser_bugs.v:205: VAR 'var' 'E1' 'module' '' 'enum' '' '' verilog/parser_bugs.v:206: VAR 'typedef' 'boolean' 'module' '' 'enum' '' '' verilog/parser_bugs.v:207: VAR 'var' 'STATE' 'module' '' 'logic [1:0]' '' '' verilog/parser_bugs.v:207: VAR 'var' 'NSTATE' 'module' '' 'logic [1:0]' '' '' verilog/parser_bugs.v:208: ENDMODULE 'endmodule' verilog/parser_bugs.v:210: MODULE 'module' 'invec' undef '0' verilog/parser_bugs.v:211: VAR 'port' 'novec' 'module' '' 'logic' '' '' verilog/parser_bugs.v:211: PORT 'novec' 'module' 'output' 'logic' '' '1' verilog/parser_bugs.v:212: VAR 'port' 'range' 'module' '' 'logic [7:0]' '' '' verilog/parser_bugs.v:212: PORT 'range' 'module' 'output' 'logic [7:0]' '' '2' verilog/parser_bugs.v:213: VAR 'port' 'arrayAndRange' 'module' '' 'logic [1:0][7:0]' '' '' verilog/parser_bugs.v:213: PORT 'arrayAndRange' 'module' 'output' 'logic [1:0][7:0]' '' '3' verilog/parser_bugs.v:214: VAR 'port' 'arrayAndArrayAndRange' 'module' '' 'logic [2:0][1:0][7:0]' '' '' verilog/parser_bugs.v:214: PORT 'arrayAndArrayAndRange' 'module' 'output' 'logic [2:0][1:0][7:0]' '' '4' verilog/parser_bugs.v:215: VAR 'port' 'novec2' 'module' '' 'reg signed' '' '' verilog/parser_bugs.v:215: PORT 'novec2' 'module' 'output' 'reg signed' '' '5' verilog/parser_bugs.v:217: ENDMODULE 'endmodule' verilog/parser_bugs.v:219: MODULE 'module' 'bug34575' undef '0' verilog/parser_bugs.v:220: VAR 'net' 'a' 'module' 'wire' '' '' '' verilog/parser_bugs.v:220: VAR 'net' 'b' 'module' 'wire' '' '' '' verilog/parser_bugs.v:220: VAR 'net' 'c' 'module' 'wire' '' '' '' verilog/parser_bugs.v:220: VAR 'net' 'd' 'module' 'wire' '' '' '' verilog/parser_bugs.v:221: CONTASSIGN 'assign' 'a' '1' verilog/parser_bugs.v:222: CONTASSIGN 'assign' 'b' '1' verilog/parser_bugs.v:223: CONTASSIGN 'assign' 'c' '1' verilog/parser_bugs.v:224: CONTASSIGN 'assign' 'd' '1' verilog/parser_bugs.v:225: ENDMODULE 'endmodule' verilog/parser_bugs.v:227: MODULE 'module' 'bug34649' undef '0' verilog/parser_bugs.v:227: PORT 'name' 'module' '' '' '' '1' verilog/parser_bugs.v:228: VAR 'port' 'name' 'module' '' 'reg' '' '0' verilog/parser_bugs.v:228: PORT 'name' 'module' 'output' 'reg' '' '0' verilog/parser_bugs.v:229: ENDMODULE 'endmodule' verilog/parser_bugs.v:230: MODULE 'module' 'bug34649b' undef '0' verilog/parser_bugs.v:231: VAR 'port' 'name' 'module' '' 'reg' '' '0' verilog/parser_bugs.v:231: PORT 'name' 'module' 'output' 'reg' '' '1' verilog/parser_bugs.v:233: ENDMODULE 'endmodule' verilog/parser_bugs.v:234: MODULE 'module' 'bug10' undef '0' verilog/parser_bugs.v:246: COMMENT '// Part of expression' verilog/parser_bugs.v:250: COMMENT '// Statement' verilog/parser_bugs.v:255: ENDMODULE 'endmodule' verilog/parser_bugs.v:257: MODULE 'module' 'bug33' undef '0' verilog/parser_bugs.v:258: VAR 'var' 'i' 'module' '' 'integer' '' '' verilog/parser_bugs.v:266: ENDMODULE 'endmodule' verilog/parser_bugs.v:268: MODULE 'module' 'bug16' undef '0' verilog/parser_bugs.v:271: ENDMODULE 'endmodule' verilog/parser_bugs.v:273: VAR 'parameter' 'bug39' 'netlist' '' '' '' '0' verilog/parser_bugs.v:279: MODULE 'module' 'bug64' undef '0' verilog/parser_bugs.v:280: VAR 'parameter' 'a' 'module' '' 'integer' '' '1' verilog/parser_bugs.v:280: VAR 'parameter' 'b' 'module' '' 'integer' '' '2' verilog/parser_bugs.v:281: VAR 'parameter' 'c' 'module' '' 'real' '' '3.0' verilog/parser_bugs.v:282: VAR 'parameter' 'd' 'module' '' 'realtime' '' '4.0' verilog/parser_bugs.v:283: VAR 'parameter' 'e' 'module' '' 'time' '' '5.0' verilog/parser_bugs.v:284: ENDMODULE 'endmodule' verilog/parser_bugs.v:286: MODULE 'module' 'bug166' undef '0' verilog/parser_bugs.v:287: CONTASSIGN 'assign' '{{o1,o2},o3,o4,{o5,o6}}' '{{i1,i2},i3,i4,{i5,i6}}' verilog/parser_bugs.v:288: ENDMODULE 'endmodule' verilog/parser_bugs.v:290: MODULE 'module' 'coverage20090318' undef '0' verilog/parser_bugs.v:291: TASK 'task' 'atask' verilog/parser_bugs.v:293: ENDTASKFUNC 'endtask' verilog/parser_bugs.v:294: ENDMODULE 'endmodule' verilog/parser_bugs.v:296: MODULE 'module' 'svsig' undef '0' verilog/parser_bugs.v:297: FUNCTION 'function' 'count' 'int' verilog/parser_bugs.v:297: VAR 'port' 'd' 'function' '' 'logic [3:0]' '' '' verilog/parser_bugs.v:297: PORT 'd' 'function' 'input' 'logic [3:0]' '' '1' verilog/parser_bugs.v:298: VAR 'var' 'count' 'function' '' 'int' '' 'd[0]+d[1]+d[2]+d[3]' verilog/parser_bugs.v:303: ENDTASKFUNC 'endfunction' verilog/parser_bugs.v:304: TASK 'task' 'autoconst' verilog/parser_bugs.v:305: VAR 'var' 'CONS' 'task' '' 'const int' '' '8' verilog/parser_bugs.v:308: ENDTASKFUNC 'endtask' verilog/parser_bugs.v:309: ENDMODULE 'endmodule' verilog/parser_bugs.v:311: MODULE 'module' 'bug_empty_func_param' undef '0' verilog/parser_bugs.v:312: COMMENT '//function int intfunc(int a=0, b=1);' verilog/parser_bugs.v:313: COMMENT '// return a+b;' verilog/parser_bugs.v:314: COMMENT '//endfunction' verilog/parser_bugs.v:321: ENDMODULE 'endmodule' verilog/parser_bugs.v:323: MODULE 'module' 'dotted_funcs' undef '0' verilog/parser_bugs.v:324: COMMENT '// Call task' verilog/parser_bugs.v:325: COMMENT '// Call function' verilog/parser_bugs.v:326: ENDMODULE 'endmodule' verilog/parser_bugs.v:328: MODULE 'module' 'var_only_in_block' undef '0' verilog/parser_bugs.v:330: VAR 'var' 'only_a_var_in_blk' 'module' '' 'integer' '' '' verilog/parser_bugs.v:332: ENDMODULE 'endmodule' verilog/parser_bugs.v:334: MODULE 'module' 'v2k_vec_no_vec' undef '0' verilog/parser_bugs.v:335: VAR 'port' 'VEC' 'module' '' '[2:0]' '' '' verilog/parser_bugs.v:335: PORT 'VEC' 'module' 'input' '[2:0]' '' '1' verilog/parser_bugs.v:336: VAR 'port' 'VEC2' 'module' '' '[2:0]' '' '' verilog/parser_bugs.v:336: PORT 'VEC2' 'module' 'input' '[2:0]' '' '2' verilog/parser_bugs.v:336: COMMENT '// No direction, no port, no data type; inherits' verilog/parser_bugs.v:337: VAR 'port' 'NOVEC' 'module' '' '' '' '' verilog/parser_bugs.v:337: PORT 'NOVEC' 'module' 'input' '' '' '3' verilog/parser_bugs.v:337: COMMENT '// No direction, no data type; use `default_nettype' verilog/parser_bugs.v:338: VAR 'port' 'ARY' 'module' '' '' '[1:0]' '' verilog/parser_bugs.v:338: PORT 'ARY' 'module' 'input' '' '[1:0]' '4' verilog/parser_bugs.v:339: VAR 'port' 'NOARY2' 'module' '' '' '' '' verilog/parser_bugs.v:339: PORT 'NOARY2' 'module' 'input' '' '' '5' verilog/parser_bugs.v:339: COMMENT '// Array doesn't inherit' verilog/parser_bugs.v:340: VAR 'port' 'STILL_IN' 'module' '' 'logic' '' '' verilog/parser_bugs.v:340: PORT 'STILL_IN' 'module' 'input' 'logic' '' '6' verilog/parser_bugs.v:340: COMMENT '// No direction, data type; inherits direction' verilog/parser_bugs.v:341: COMMENT '// Logic type' verilog/parser_bugs.v:341: VAR 'port' 'TYPED' 'module' '' 'logic' '' '' verilog/parser_bugs.v:341: PORT 'TYPED' 'module' 'input' 'logic' '' '7' verilog/parser_bugs.v:343: TASK 'task' 't' verilog/parser_bugs.v:343: VAR 'port' 'FVEC' 'task' '' '[2:0]' '' '' verilog/parser_bugs.v:343: PORT 'FVEC' 'task' 'input' '[2:0]' '' '1' verilog/parser_bugs.v:343: VAR 'port' 'FVEC2' 'task' '' '[2:0]' '' '' verilog/parser_bugs.v:343: PORT 'FVEC2' 'task' 'input' '[2:0]' '' '2' verilog/parser_bugs.v:344: VAR 'port' 'NOVEC' 'task' '' '' '' '' verilog/parser_bugs.v:344: PORT 'NOVEC' 'task' 'input' '' '' '3' verilog/parser_bugs.v:346: ENDTASKFUNC 'endtask' verilog/parser_bugs.v:347: ENDMODULE 'endmodule' verilog/parser_bugs.v:349: MODULE 'module' 'bugfor' undef '0' verilog/parser_bugs.v:351: ENDMODULE 'endmodule' verilog/parser_bugs.v:353: MODULE 'module' 'bug85' undef '0' verilog/parser_bugs.v:353: VAR 'parameter' 'T_DATA' 'module' '' 'type' '' 'byte' verilog/parser_bugs.v:354: PORT 'data' 'module' '' '' '' '1' verilog/parser_bugs.v:355: VAR 'port' 'data' 'module' '' 'T_DATA' '' '' verilog/parser_bugs.v:355: PORT 'data' 'module' 'input' 'T_DATA' '' '0' verilog/parser_bugs.v:357: INSTANT 'sub' 'sub' '' verilog/parser_bugs.v:356: PARAMPIN 'T_DATA' 'T_DATA' '1' verilog/parser_bugs.v:357: PIN 'data' 'data' '1' verilog/parser_bugs.v:357: ENDCELL '' verilog/parser_bugs.v:358: ENDMODULE 'endmodule' verilog/parser_bugs.v:360: MODULE 'module' 'bugmodportcomma' undef '0' verilog/parser_bugs.v:360: PORT 'a' 'module' '' '' '' '1' verilog/parser_bugs.v:361: VAR 'port' 'a' 'module' '' '' '' '' verilog/parser_bugs.v:361: PORT 'a' 'module' 'input' '' '' '0' verilog/parser_bugs.v:362: ENDMODULE 'endmodule' verilog/parser_bugs.v:364: MODULE 'module' 'bug168' undef '0' verilog/parser_bugs.v:369: ENDMODULE 'endmodule' verilog/parser_bugs.v:371: MODULE 'module' 'bug183' undef '0' verilog/parser_bugs.v:372: VAR 'parameter' 'NUM' 'module' '' '' '' '9' verilog/parser_bugs.v:373: VAR 'parameter' 'WIDTH' 'module' '' '' '' '8' verilog/parser_bugs.v:374: VAR 'port' 'a' 'module' '' 'logic [NUM-1:0][WIDTH-1:0]' '' '' verilog/parser_bugs.v:374: PORT 'a' 'module' 'input' 'logic [NUM-1:0][WIDTH-1:0]' '' '1' verilog/parser_bugs.v:375: VAR 'port' 'sum' 'module' '' 'logic [WIDTH-1:0]' '' '' verilog/parser_bugs.v:375: PORT 'sum' 'module' 'output' 'logic [WIDTH-1:0]' '' '2' verilog/parser_bugs.v:377: VAR 'localparam' 'NLOG' 'module' '' '' '' '(NUM<=2)?1:(NUM<=1024)?10:0' verilog/parser_bugs.v:381: VAR 'typedef' 'val_t' 'module' '' 'logic [WIDTH-1:0]' '' '' verilog/parser_bugs.v:382: VAR 'var' 'tree' 'module' '' 'val_t[NLOG:0][NUM-1:0]' '' '' verilog/parser_bugs.v:383: ENDMODULE 'endmodule' verilog/parser_bugs.v:385: MODULE 'module' 'bug192' undef '0' verilog/parser_bugs.v:386: COVERGROUP 'covergroup' 'cg192' verilog/parser_bugs.v:390: ENDGROUP 'endgroup' verilog/parser_bugs.v:391: VAR 'var' 'cover_ts' 'module' '' 'cg192' '' 'new()' verilog/parser_bugs.v:391: COMMENT '// also bug361' verilog/parser_bugs.v:392: ENDMODULE 'endmodule' verilog/parser_bugs.v:394: FUNCTION 'function' 'func_implied_in' 'bit' verilog/parser_bugs.v:394: VAR 'port' 'i' 'function' '' 'bit' '' '' verilog/parser_bugs.v:394: PORT 'i' 'function' 'input' 'bit' '' '1' verilog/parser_bugs.v:394: ENDTASKFUNC 'endfunction' verilog/parser_bugs.v:396: MODULE 'module' 'sparam' undef '0' verilog/parser_bugs.v:400: COMMENT '// bug221' verilog/parser_bugs.v:398: ENDMODULE 'endmodule' verilog/parser_bugs.v:401: VAR 'port' 'sig' 'sequence' '' '' '' '' verilog/parser_bugs.v:401: PORT 'sig' 'sequence' 'input' '' '' '1' verilog/parser_bugs.v:401: VAR 'port' 'clks_before' 'sequence' '' '' '' '' verilog/parser_bugs.v:401: PORT 'clks_before' 'sequence' 'input' '' '' '2' verilog/parser_bugs.v:401: VAR 'port' 'clk' 'sequence' '' '' '' '' verilog/parser_bugs.v:401: PORT 'clk' 'sequence' 'input' '' '' '3' verilog/parser_bugs.v:401: VAR 'port' 'rst' 'sequence' '' '' '' '1'b0' verilog/parser_bugs.v:401: PORT 'rst' 'sequence' 'input' '' '' '4' verilog/parser_bugs.v:405: VAR 'port' 'sample' 'property' '' '' '' '' verilog/parser_bugs.v:405: PORT 'sample' 'property' 'input' '' '' '1' verilog/parser_bugs.v:405: VAR 'port' 'sig' 'property' '' '' '' '' verilog/parser_bugs.v:405: PORT 'sig' 'property' 'input' '' '' '2' verilog/parser_bugs.v:405: VAR 'port' 'clks_before' 'property' '' '' '' '' verilog/parser_bugs.v:405: PORT 'clks_before' 'property' 'input' '' '' '3' verilog/parser_bugs.v:405: VAR 'port' 'clks_after' 'property' '' '' '' '' verilog/parser_bugs.v:405: PORT 'clks_after' 'property' 'input' '' '' '4' verilog/parser_bugs.v:405: VAR 'port' 'clk' 'property' '' '' '' '$default_clk' verilog/parser_bugs.v:405: PORT 'clk' 'property' 'input' '' '' '5' verilog/parser_bugs.v:405: VAR 'port' 'rst' 'property' '' '' '' '1'b0' verilog/parser_bugs.v:405: PORT 'rst' 'property' 'input' '' '' '6' verilog/parser_bugs.v:411: VAR 'port' 'prop' 'property' '' '' '' '' verilog/parser_bugs.v:411: PORT 'prop' 'property' 'input' '' '' '1' verilog/parser_bugs.v:411: VAR 'port' 'clk' 'property' '' '' '' '$default_clk' verilog/parser_bugs.v:411: PORT 'clk' 'property' 'input' '' '' '2' verilog/parser_bugs.v:411: VAR 'port' 'rst' 'property' '' '' '' '1'b0' verilog/parser_bugs.v:411: PORT 'rst' 'property' 'input' '' '' '3' verilog/parser_bugs.v:415: VAR 'port' 'trig' 'property' '' '' '' '' verilog/parser_bugs.v:415: PORT 'trig' 'property' 'input' '' '' '1' verilog/parser_bugs.v:415: VAR 'port' 'n' 'property' '' '' '' '' verilog/parser_bugs.v:415: PORT 'n' 'property' 'input' '' '' '2' verilog/parser_bugs.v:415: VAR 'port' 'cond' 'property' '' '' '' '' verilog/parser_bugs.v:415: PORT 'cond' 'property' 'input' '' '' '3' verilog/parser_bugs.v:415: VAR 'port' 'clk' 'property' '' '' '' '$default_clk' verilog/parser_bugs.v:415: PORT 'clk' 'property' 'input' '' '' '4' verilog/parser_bugs.v:415: VAR 'port' 'rst' 'property' '' '' '' '1'b0' verilog/parser_bugs.v:415: PORT 'rst' 'property' 'input' '' '' '5' verilog/parser_bugs.v:421: VAR 'port' 'start_ev' 'property' '' '' '' '' verilog/parser_bugs.v:421: PORT 'start_ev' 'property' 'input' '' '' '1' verilog/parser_bugs.v:421: VAR 'port' 'start_data' 'property' '' '' '' '' verilog/parser_bugs.v:421: PORT 'start_data' 'property' 'input' '' '' '2' verilog/parser_bugs.v:421: VAR 'port' 'end_ev' 'property' '' '' '' '' verilog/parser_bugs.v:421: PORT 'end_ev' 'property' 'input' '' '' '3' verilog/parser_bugs.v:421: VAR 'port' 'end_data' 'property' '' '' '' '' verilog/parser_bugs.v:421: PORT 'end_data' 'property' 'input' '' '' '4' verilog/parser_bugs.v:421: VAR 'port' 'clk' 'property' '' '' '' '$default_clk' verilog/parser_bugs.v:421: PORT 'clk' 'property' 'input' '' '' '5' verilog/parser_bugs.v:421: VAR 'port' 'rst' 'property' '' '' '' '1'b0' verilog/parser_bugs.v:421: PORT 'rst' 'property' 'input' '' '' '6' verilog/parser_bugs.v:429: MODULE 'module' 'bug228' undef '0' verilog/parser_bugs.v:430: VAR 'net' 'net1' 'module' 'wire' '' '' '' verilog/parser_bugs.v:430: VAR 'net' 'net2' 'module' 'wire' '' '' '' verilog/parser_bugs.v:430: VAR 'net' 'net3' 'module' 'wire' '' '' '' verilog/parser_bugs.v:431: INSTANT 'nmos' 'u' '' verilog/parser_bugs.v:431: PARAMPIN '' '0' '1' verilog/parser_bugs.v:431: PARAMPIN '' '0' '2' verilog/parser_bugs.v:431: PARAMPIN '' '0' '3' verilog/parser_bugs.v:431: PIN '' 'net1' '1' verilog/parser_bugs.v:431: PIN '' 'net2' '2' verilog/parser_bugs.v:431: PIN '' 'net3' '3' verilog/parser_bugs.v:431: ENDCELL '' verilog/parser_bugs.v:432: ENDMODULE 'endmodule' verilog/parser_bugs.v:434: MODULE 'module' 'bug262' undef '0' verilog/parser_bugs.v:434: PORT 'Y' 'module' '' '' '' '1' verilog/parser_bugs.v:434: PORT 'A1' 'module' '' '' '' '2' verilog/parser_bugs.v:434: PORT 'A2' 'module' '' '' '' '3' verilog/parser_bugs.v:434: PORT 'B' 'module' '' '' '' '4' verilog/parser_bugs.v:435: VAR 'port' 'Y' 'module' '' '' '' '' verilog/parser_bugs.v:435: PORT 'Y' 'module' 'output' '' '' '0' verilog/parser_bugs.v:436: VAR 'port' 'A1' 'module' '' '' '' '' verilog/parser_bugs.v:436: PORT 'A1' 'module' 'input' '' '' '0' verilog/parser_bugs.v:436: VAR 'port' 'A2' 'module' '' '' '' '' verilog/parser_bugs.v:436: PORT 'A2' 'module' 'input' '' '' '0' verilog/parser_bugs.v:436: VAR 'port' 'B' 'module' '' '' '' '' verilog/parser_bugs.v:436: PORT 'B' 'module' 'input' '' '' '0' verilog/parser_bugs.v:437: ENDMODULE 'endmodule' verilog/parser_bugs.v:439: VAR 'net' '\wire ' 'netlist' 'wire' '' '' 'bug282_must_keep_escape' verilog/parser_bugs.v:441: MODULE 'module' 'bug403_bug404' undef '0' verilog/parser_bugs.v:442: COMMENT '// Simulators vary as to if "(* /* */ )" is legal or not' verilog/parser_bugs.v:443: ATTRIBUTE '(* attr *)' verilog/parser_bugs.v:443: VAR 'net' 'foo' 'module' 'wire' '' '' '' verilog/parser_bugs.v:449: COMMENT '/* multi line bug459*/' verilog/parser_bugs.v:447: ENDMODULE 'endmodule' verilog/parser_bugs.v:453: MODULE 'module' 'bug422' undef '0' verilog/parser_bugs.v:456: ENDMODULE 'endmodule' verilog/parser_bugs.v:458: MODULE 'module' 'bug461' undef '0' verilog/parser_bugs.v:460: VAR 'genvar' 'g' 'module' '' '' '' '' verilog/parser_bugs.v:460: COMMENT '// bug461' verilog/parser_bugs.v:462: VAR 'genvar' 'g2' 'module' '' '' '' '' verilog/parser_bugs.v:463: VAR 'genvar' 'g1' 'module' '' '' '' '' verilog/parser_bugs.v:469: ENDMODULE 'endmodule' verilog/parser_bugs.v:471: MODULE 'module' 'bug507' undef '0' verilog/parser_bugs.v:472: VAR 'var' 'x' 'module' '' 'integer' '' '32'd 6' verilog/parser_bugs.v:476: COMMENT '// bug_msg_887;' verilog/parser_bugs.v:474: ENDMODULE 'endmodule' verilog/parser_bugs.v:477: INSTANT 'example_mod_fcov' 'uexample_mod_fcov' '' verilog/parser_bugs.v:477: PIN '*' '*' '1' verilog/parser_bugs.v:477: ENDCELL '' verilog/parser_bugs.v:479: PACKAGE 'package' 'bug586_pkg' verilog/parser_bugs.v:480: VAR 'parameter' 'B' 'package' '' '' '' '10' verilog/parser_bugs.v:481: ENDPACKAGE 'endpackage' verilog/parser_bugs.v:482: MODULE 'module' 'non_bug586' undef '0' verilog/parser_bugs.v:482: COMMENT '// Verilator only' verilog/parser_bugs.v:483: VAR 'port' 'bvar' 'module' '' 'logic [bug586_pkg::B:0]' '' '' verilog/parser_bugs.v:483: PORT 'bvar' 'module' 'input' 'logic [bug586_pkg::B:0]' '' '0' verilog/parser_bugs.v:486: COMMENT '// bug_641' verilog/parser_bugs.v:484: ENDMODULE 'endmodule' verilog/parser_bugs.v:487: FUNCTION 'function' 'mydpi_bug641' 'bit' verilog/parser_bugs.v:487: VAR 'port' 'a_dpi_input' 'function' '' '' '' '' verilog/parser_bugs.v:487: PORT 'a_dpi_input' 'function' 'input' '' '' '1' verilog/parser_bugs.v:487: ENDTASKFUNC 'endfunction' verilog/parser_bugs.v:489: COMMENT '// .f() in function call' verilog/parser_bugs.v:490: MODULE 'module' 'fbug' undef '0' verilog/parser_bugs.v:496: ENDMODULE 'endmodule' verilog/parser_bugs.v:498: VAR 'parameter' 'bug671' 'netlist' '' '' '' '5:10:20' verilog/parser_bugs.v:500: MODULE 'module' 'bug256' undef '0' verilog/parser_bugs.v:504: COMMENT '// [#] [100] ['b0]' verilog/parser_bugs.v:507: ENDMODULE 'endmodule' verilog/parser_bugs.v:509: MODULE 'module' 'msg1491' undef '0' verilog/parser_bugs.v:509: PORT 'A' 'module' '' '' '' '1' verilog/parser_bugs.v:509: PORT 'B' 'module' '' '' '' '2' verilog/parser_bugs.v:510: VAR 'port' 'A' 'module' '' '' '' '' verilog/parser_bugs.v:510: PORT 'A' 'module' 'output' '' '' '0' verilog/parser_bugs.v:511: VAR 'net' 'A' 'module' 'trireg' '' '' '' verilog/parser_bugs.v:512: VAR 'port' 'B' 'module' 'trireg' '' '' '' verilog/parser_bugs.v:512: PORT 'B' 'module' 'output' '' '' '0' verilog/parser_bugs.v:513: ENDMODULE 'endmodule' verilog/parser_bugs.v:515: MODULE 'module' 'msg2540' undef '0' verilog/parser_bugs.v:516: VAR 'port' 'foo' 'module' '' 'signed' '' '' verilog/parser_bugs.v:516: PORT 'foo' 'module' 'output' 'signed' '' '1' verilog/parser_bugs.v:517: ENDMODULE 'endmodule' verilog/parser_bugs.v:519: MODULE 'module' 'prot' undef '0' verilog/parser_bugs.v:524: ENDMODULE 'endmodule' verilog/parser_bugs.v:526: MODULE 'module' 'prot2' undef '0' verilog/parser_bugs.v:540: ENDMODULE 'endmodule' verilog/parser_bugs.v:542: MODULE 'module' 'prot3' undef '0' verilog/parser_bugs.v:564: ENDMODULE 'endmodule' verilog/parser_bugs.v:566: MODULE 'module' 'bug1340' undef '0' verilog/parser_bugs.v:567: VAR 'parameter' 'B' 'module' '' '' '' '8 'b 1' verilog/parser_bugs.v:572: ENDMODULE 'endmodule' verilog/parser_bugs.v:574: MODULE 'module' 'msg2931' undef '0' verilog/parser_bugs.v:576: VAR 'var' 'mynet1' 'module' '' 'net1_t' '' '' verilog/parser_bugs.v:578: VAR 'var' 'mynet2' 'module' '' 'net2_t' '' '' verilog/parser_bugs.v:580: VAR 'var' 'mynet3' 'module' '' 'net3_t' '' '' verilog/parser_bugs.v:581: ENDMODULE 'endmodule' verilog/parser_bugs.v:583: MODULE 'module' 'bug1505' undef '0' verilog/parser_bugs.v:584: INSTANT 'sub' 'i_suba' '' verilog/parser_bugs.v:584: ENDCELL '' verilog/parser_bugs.v:585: INSTANT 'sub' 'i_subb' '[1:2]' verilog/parser_bugs.v:585: ENDCELL '' verilog/parser_bugs.v:586: INSTANT 'sub' 'i_subc' '[1:2][3:4][5:6]' verilog/parser_bugs.v:586: ENDCELL '' verilog/parser_bugs.v:587: ENDMODULE 'endmodule' verilog/pinorder.v:001: COMMENT '// DESCRIPTION: Verilog-Perl: Example Verilog for testing package' verilog/pinorder.v:002: COMMENT '//' verilog/pinorder.v:003: COMMENT '// This file ONLY is placed into the Public Domain, for any use,' verilog/pinorder.v:004: COMMENT '// without warranty, 2003 by Wilson Snyder.' verilog/pinorder.v:006: MODULE 'module' 'pinorder4' undef '0' verilog/pinorder.v:007: VAR 'net' 'b_i' 'module' 'wire' '' '' '' verilog/pinorder.v:008: VAR 'net' 'd_o' 'module' 'wire' '' '' '' verilog/pinorder.v:009: VAR 'net' 'a_i' 'module' 'wire' '[7:0]' '' '' verilog/pinorder.v:010: VAR 'net' 'IPCD_const' 'module' 'wire' '[31:0]' '' '32'h1' verilog/pinorder.v:012: CONTASSIGN 'assign' 'a_i' '0' verilog/pinorder.v:013: CONTASSIGN 'assign' 'b_i' '0' verilog/pinorder.v:015: INSTANT 'foo' 'foo1' '' verilog/pinorder.v:015: PIN 'y' 'b_i' '1' verilog/pinorder.v:015: PIN 'x' 'a_i' '2' verilog/pinorder.v:015: PIN 'abcconst' '3'h0' '3' verilog/pinorder.v:015: PIN 'noconnect' '' '4' verilog/pinorder.v:016: PIN 'def' 'IPCD_const' '5' verilog/pinorder.v:016: ENDCELL '' verilog/pinorder.v:017: INSTANT 'foo' 'foo3' '' verilog/pinorder.v:017: PIN '' 'b_i' '1' verilog/pinorder.v:017: PIN '' 'a_i' '2' verilog/pinorder.v:017: PIN '' '3'h0' '3' verilog/pinorder.v:017: PIN '' 'IPCD_const' '5' verilog/pinorder.v:017: ENDCELL '' verilog/pinorder.v:018: INSTANT 'foo2' 'foo2' '' verilog/pinorder.v:018: PIN '' 'b_i' '1' verilog/pinorder.v:018: PIN '' 'a_i[0]' '2' verilog/pinorder.v:018: PIN '' 'd_o' '3' verilog/pinorder.v:018: ENDCELL '' verilog/pinorder.v:020: ENDMODULE 'endmodule' verilog/pinorder.v:022: MODULE 'module' 'foo2' undef '0' verilog/pinorder.v:022: COMMENT '/*AUTOARG*/' verilog/pinorder.v:023: COMMENT '// Outputs' verilog/pinorder.v:024: PORT 'x' 'module' '' '' '' '1' verilog/pinorder.v:025: COMMENT '// Inputs' verilog/pinorder.v:026: PORT 'z' 'module' '' '' '' '2' verilog/pinorder.v:026: PORT 'y' 'module' '' '' '' '3' verilog/pinorder.v:028: VAR 'port' 'z' 'module' '' '' '' '' verilog/pinorder.v:028: PORT 'z' 'module' 'input' '' '' '0' verilog/pinorder.v:029: VAR 'port' 'y' 'module' '' '' '' '' verilog/pinorder.v:029: PORT 'y' 'module' 'input' '' '' '0' verilog/pinorder.v:030: VAR 'port' 'x' 'module' '' '' '' '' verilog/pinorder.v:030: PORT 'x' 'module' 'output' '' '' '0' verilog/pinorder.v:031: VAR 'var' 'x' 'module' '' 'reg' '' '' verilog/pinorder.v:033: ENDMODULE 'endmodule' verilog/pinorder.v:035: MODULE 'module' 'foo' undef '0' verilog/pinorder.v:035: COMMENT '/*AUTOARG*/' verilog/pinorder.v:036: COMMENT '// Inputs' verilog/pinorder.v:037: PORT 'y' 'module' '' '' '' '1' verilog/pinorder.v:037: PORT 'x' 'module' '' '' '' '2' verilog/pinorder.v:037: PORT 'abcconst' 'module' '' '' '' '3' verilog/pinorder.v:037: PORT 'noconnect' 'module' '' '' '' '4' verilog/pinorder.v:037: PORT 'def' 'module' '' '' '' '5' verilog/pinorder.v:039: VAR 'port' 'y' 'module' '' '' '' '' verilog/pinorder.v:039: PORT 'y' 'module' 'input' '' '' '0' verilog/pinorder.v:040: VAR 'port' 'x' 'module' '' '' '' '' verilog/pinorder.v:040: PORT 'x' 'module' 'input' '' '' '0' verilog/pinorder.v:041: VAR 'port' 'abcconst' 'module' '' '[2:0]' '' '' verilog/pinorder.v:041: PORT 'abcconst' 'module' 'input' '[2:0]' '' '0' verilog/pinorder.v:042: VAR 'port' 'noconnect' 'module' '' 'signed [3:0]' '' '' verilog/pinorder.v:042: PORT 'noconnect' 'module' 'input' 'signed [3:0]' '' '0' verilog/pinorder.v:043: VAR 'port' 'def' 'module' '' '[31:0]' '' '' verilog/pinorder.v:043: PORT 'def' 'module' 'input' '[31:0]' '' '0' verilog/pinorder.v:044: ENDMODULE 'endmodule' verilog/pinorder.v:046: MODULE 'module' 'bug278' undef '0' verilog/pinorder.v:048: VAR 'port' 'ow' 'module' 'wire' '' '' '' verilog/pinorder.v:048: PORT 'ow' 'module' 'output' '' '' '1' verilog/pinorder.v:049: VAR 'port' 'iow' 'module' 'wire' '' '' '' verilog/pinorder.v:049: PORT 'iow' 'module' 'inout' '' '' '2' verilog/pinorder.v:050: VAR 'port' 'iw' 'module' 'wire' '' '' '' verilog/pinorder.v:050: PORT 'iw' 'module' 'input' '' '' '3' verilog/pinorder.v:051: ENDMODULE 'endmodule' verilog/parser_sv.v:001: PACKAGE 'package' 'mypackage' verilog/parser_sv.v:002: VAR 'var' 'pkg_addr' 'package' '' 'bit [7:0]' '' '' verilog/parser_sv.v:003: VAR 'var' 'pkg_data' 'package' '' 'bit [7:0]' '' '' verilog/parser_sv.v:004: ENDPACKAGE 'endpackage' verilog/parser_sv.v:006: MODULE 'module' 'times' undef '0' verilog/parser_sv.v:007: VAR 'var' 'x' 'module' '' 'time' '' '' verilog/parser_sv.v:008: COMMENT '// Note no space' verilog/parser_sv.v:009: ENDMODULE 'endmodule' verilog/parser_sv.v:011: INTERFACE 'interface' 'itf' verilog/parser_sv.v:011: VAR 'parameter' 'num_of_cli' 'interface' '' '' '' '0' verilog/parser_sv.v:012: VAR 'var' 'blabla' 'interface' '' 'logic' '' '' verilog/parser_sv.v:013: VAR 'var' 'addr' 'interface' '' 'logic [7:0]' '' '' verilog/parser_sv.v:013: VAR 'var' 'data' 'interface' '' 'logic [7:0]' '[9]' '' verilog/parser_sv.v:014: MODPORT 'modport' 'Master' verilog/parser_sv.v:014: VAR 'port' 'data' 'modport' '' '' '' 'data' verilog/parser_sv.v:014: PORT 'data' 'modport' 'input' '' '' '1' verilog/parser_sv.v:014: VAR 'port' 'date_delayed' 'modport' '' '' '' 'date_delayed' verilog/parser_sv.v:014: PORT 'date_delayed' 'modport' 'input' '' '' '2' verilog/parser_sv.v:014: VAR 'port' 'addr' 'modport' '' '' '' 'addr' verilog/parser_sv.v:014: PORT 'addr' 'modport' 'output' '' '' '3' verilog/parser_sv.v:014: ENDMODPORT 'endmodport' verilog/parser_sv.v:015: ENDINTERFACE 'endinterface' verilog/parser_sv.v:017: MODULE 'module' 'test' undef '0' verilog/parser_sv.v:018: VAR 'port' 'whole_int' 'module' '' 'itf' '' '' verilog/parser_sv.v:018: PORT 'whole_int' 'module' 'interface' 'itf' '' '1' verilog/parser_sv.v:018: INSTANT 'itf' 'whole_int' '' verilog/parser_sv.v:018: ENDCELL '' verilog/parser_sv.v:019: VAR 'port' 'modported_int' 'module' '' 'itf.test' '' '' verilog/parser_sv.v:019: PORT 'modported_int' 'module' 'interface' 'itf.test' '' '2' verilog/parser_sv.v:019: INSTANT 'itf' 'modported_int' '' verilog/parser_sv.v:019: ENDCELL '' verilog/parser_sv.v:020: VAR 'port' 'clk' 'module' '' 'logic' '' '' verilog/parser_sv.v:020: PORT 'clk' 'module' 'input' 'logic' '' '3' verilog/parser_sv.v:020: VAR 'port' 'rst' 'module' '' 'logic' '' '' verilog/parser_sv.v:020: PORT 'rst' 'module' 'input' 'logic' '' '4' verilog/parser_sv.v:021: VAR 'port' 'd_in' 'module' '' 'logic' '' '' verilog/parser_sv.v:021: PORT 'd_in' 'module' 'input' 'logic' '' '5' verilog/parser_sv.v:022: VAR 'port' 'd_out' 'module' '' 'logic' '' '' verilog/parser_sv.v:022: PORT 'd_out' 'module' 'output' 'logic' '' '6' verilog/parser_sv.v:025: IMPORT 'mypackage' '*' verilog/parser_sv.v:027: VAR 'var' 'd_int' 'module' '' 'logic' '' '' verilog/parser_sv.v:028: VAR 'var' 'data_' 'module' '' 'logic [7:0]' '' '' verilog/parser_sv.v:028: VAR 'var' 'bork' 'module' '' 'logic [7:0]' '[2]' '' verilog/parser_sv.v:029: CONTASSIGN 'assign' 'd_int' 'd_in+pkg_data' verilog/parser_sv.v:031: CONTASSIGN 'assign' 'modported_int.data' 'data_' verilog/parser_sv.v:044: COMMENT '//a1: assert property(p1) else $warning("\nProperty violated\n");' verilog/parser_sv.v:046: ENDMODULE 'endmodule' verilog/parser_sv.v:048: COMMENT '// Different ways of declaring pins/vars' verilog/parser_sv.v:049: MODULE 'module' 'line49_diff_pins1' undef '0' verilog/parser_sv.v:050: VAR 'port' 'in_nw' 'module' '' '' '' '' verilog/parser_sv.v:050: PORT 'in_nw' 'module' 'input' '' '' '1' verilog/parser_sv.v:050: COMMENT '// Input, no type' verilog/parser_sv.v:051: VAR 'port' 'in_vec' 'module' '' '[1:0]' '[2:0]' '' verilog/parser_sv.v:051: PORT 'in_vec' 'module' 'input' '[1:0]' '[2:0]' '2' verilog/parser_sv.v:051: COMMENT '// Input, implicit' verilog/parser_sv.v:052: VAR 'port' 'in_nvec' 'module' '' '' '' '' verilog/parser_sv.v:052: PORT 'in_nvec' 'module' 'input' '' '' '3' verilog/parser_sv.v:052: COMMENT '// Isn't vectorized' verilog/parser_sv.v:053: VAR 'port' 'out_logic' 'module' '' 'logic' '' '' verilog/parser_sv.v:053: PORT 'out_logic' 'module' 'output' 'logic' '' '4' verilog/parser_sv.v:053: COMMENT '// Output and var' verilog/parser_sv.v:054: COMMENT '// "logic" sticks' verilog/parser_sv.v:054: VAR 'port' 'out_also_logic' 'module' '' '' '' '' verilog/parser_sv.v:054: PORT 'out_also_logic' 'module' 'output' '' '' '5' verilog/parser_sv.v:056: ENDMODULE 'endmodule' verilog/parser_sv.v:057: MODULE 'module' 'line49_diff_pins2' undef '0' verilog/parser_sv.v:057: PORT 'in2_nw' 'module' '' '' '' '1' verilog/parser_sv.v:057: PORT 'in2_vec' 'module' '' '' '' '2' verilog/parser_sv.v:057: PORT 'out2reg' 'module' '' '' '' '3' verilog/parser_sv.v:059: VAR 'port' 'in2_nw' 'module' '' '' '' '' verilog/parser_sv.v:059: PORT 'in2_nw' 'module' 'input' '' '' '0' verilog/parser_sv.v:060: VAR 'port' 'in2_vec' 'module' '' '[1:0]' '[2:0]' '' verilog/parser_sv.v:060: PORT 'in2_vec' 'module' 'input' '[1:0]' '[2:0]' '0' verilog/parser_sv.v:061: VAR 'port' 'out2_reg' 'module' '' 'reg' '' '' verilog/parser_sv.v:061: PORT 'out2_reg' 'module' 'output' 'reg' '' '0' verilog/parser_sv.v:062: VAR 'port' 'in2_signed' 'module' '' 'signed' '' '' verilog/parser_sv.v:062: PORT 'in2_signed' 'module' 'input' 'signed' '' '0' verilog/parser_sv.v:064: VAR 'var' 'var1_imp' 'module' '' '' '' '' verilog/parser_sv.v:065: VAR 'var' 'var1_imp_vec' 'module' '' '[1:0]' '[2:0]' '' verilog/parser_sv.v:066: VAR 'var' 'var1_imp_reg' 'module' '' 'reg' '' '' verilog/parser_sv.v:067: VAR 'var' 'var1_imp_logic' 'module' '' 'logic' '' '' verilog/parser_sv.v:068: ENDMODULE 'endmodule' verilog/parser_sv.v:070: PROGRAM 'program' 'first_prog' verilog/parser_sv.v:071: VAR 'var' 'i' 'program' '' 'int' '' '' verilog/parser_sv.v:074: COMMENT '// Importing' verilog/parser_sv.v:072: ENDPROGRAM 'endprogram' verilog/parser_sv.v:075: PACKAGE 'package' 'imp_test_pkg' verilog/parser_sv.v:076: VAR 'typedef' 'byte_t' 'package' '' 'logic [7:0]' '' '' verilog/parser_sv.v:077: VAR 'typedef' 'word_t' 'package' '' 'logic [15:0]' '' '' verilog/parser_sv.v:078: FUNCTION 'function' 'afunc' '' verilog/parser_sv.v:078: VAR 'port' 'w' 'function' '' 'integer' '' '' verilog/parser_sv.v:078: PORT 'w' 'function' 'input' 'integer' '' '1' verilog/parser_sv.v:078: ENDTASKFUNC 'endfunction' verilog/parser_sv.v:079: ENDPACKAGE 'endpackage' verilog/parser_sv.v:080: MODULE 'module' 'imp_test_mod' undef '0' verilog/parser_sv.v:081: IMPORT 'imp_test_pkg' 'byte_t' verilog/parser_sv.v:082: VAR 'var' 'some_byte' 'module' '' 'byte_t' '' '' verilog/parser_sv.v:083: ENDMODULE 'endmodule' verilog/parser_sv.v:084: MODULE 'module' 'imp_test_mod2' undef '0' verilog/parser_sv.v:085: IMPORT 'imp_test_pkg' '*' verilog/parser_sv.v:086: VAR 'var' 'some_word' 'module' '' 'word_t' '' '' verilog/parser_sv.v:087: ENDMODULE 'endmodule' verilog/parser_sv.v:088: MODULE 'module' 'imp_test_mod3' undef '0' verilog/parser_sv.v:089: VAR 'port' 'wordin' 'module' '' 'imp_test_pkg::word_t' '' '' verilog/parser_sv.v:089: PORT 'wordin' 'module' 'input' 'imp_test_pkg::word_t' '' '1' verilog/parser_sv.v:090: VAR 'localparam' 'FROM_FUNC' 'module' '' '' '' 'imp_test_pkg::afunc(1)' verilog/parser_sv.v:091: ENDMODULE 'endmodule' verilog/parser_sv.v:093: MODULE 'module' 'var_unnamed_block' undef '0' verilog/parser_sv.v:095: VAR 'var' 'var_in_unnamed' 'module' '' 'integer' '' '' verilog/parser_sv.v:097: ENDMODULE 'endmodule' verilog/parser_sv.v:099: MODULE 'module' 'cell_with_typeparam' undef '0' verilog/parser_sv.v:100: INSTANT 'addr' 'acell' '' verilog/parser_sv.v:100: PARAMPIN 'PARAMTYPE' 'integer' '1' verilog/parser_sv.v:100: ENDCELL '' verilog/parser_sv.v:101: ENDMODULE 'endmodule' verilog/parser_sv.v:103: MODULE 'module' 'arrayed_wire' undef '0' verilog/parser_sv.v:104: VAR 'net' 'n2' 'module' 'wire' '[3:0][7:0]' '' '' verilog/parser_sv.v:105: ENDMODULE 'endmodule' verilog/parser_sv.v:107: TASK 'task' 'empty_task' verilog/parser_sv.v:107: COMMENT '// sv design book' verilog/parser_sv.v:108: ENDTASKFUNC 'endtask' verilog/parser_sv.v:109: TASK 'task' 'empty_task2' verilog/parser_sv.v:109: COMMENT '// sv design book' verilog/parser_sv.v:110: VAR 'var' 'i' 'task' '' 'integer' '' '' verilog/parser_sv.v:111: ENDTASKFUNC 'endtask' verilog/parser_sv.v:113: TASK 'task' 'check_casts' verilog/parser_sv.v:114: VAR 'typedef' 'integer_t' 'task' '' 'integer' '' '' verilog/parser_sv.v:118: ENDTASKFUNC 'endtask' verilog/parser_sv.v:120: MODULE 'module' 'comma_assign' undef '0' verilog/parser_sv.v:121: VAR 'var' 'n' 'module' '' 'int' '[1:2][1:3]' ''{'{0,1,2},'{3}}' verilog/parser_sv.v:122: ENDMODULE 'endmodule' verilog/parser_sv.v:124: TASK 'task' 'typed_pattern' verilog/parser_sv.v:125: VAR 'typedef' 'triple' 'task' '' 'int' '[1:3]' '' verilog/parser_sv.v:127: ENDTASKFUNC 'endtask' verilog/parser_sv.v:129: CLASS 'class' 'VclassWCopy' 'virtual' verilog/parser_sv.v:130: FUNCTION 'function' 'new' '' verilog/parser_sv.v:130: ENDTASKFUNC 'endfunction' verilog/parser_sv.v:131: FUNCTION 'function' 'copy' 'VclassWCopy' verilog/parser_sv.v:131: VAR 'port' 'src' 'function' '' 'VclassWCopy' '' 'null' verilog/parser_sv.v:131: PORT 'src' 'function' 'input' 'VclassWCopy' '' '1' verilog/parser_sv.v:132: ENDTASKFUNC 'endfunction' verilog/parser_sv.v:133: ENDCLASS 'endclass' verilog/parser_sv.v:134: FUNCTION 'function' 'new' '' verilog/parser_sv.v:135: ENDTASKFUNC 'endfunction' verilog/parser_sv.v:138: FUNCTION 'function' 'FwdClass::ffunc' 'bit [3:0]' verilog/parser_sv.v:138: VAR 'port' 'in' 'function' '' 'bit [3:0]' '' '' verilog/parser_sv.v:138: PORT 'in' 'function' 'input' 'bit [3:0]' '' '1' verilog/parser_sv.v:140: ENDTASKFUNC 'endfunction' verilog/parser_sv.v:142: FUNCTION 'function' 'VclassWCopy::copy' 'VclassWCopy' verilog/parser_sv.v:143: VAR 'port' 'to' 'function' '' 'VclassWCopy' '' '' verilog/parser_sv.v:143: PORT 'to' 'function' 'input' 'VclassWCopy' '' '1' verilog/parser_sv.v:145: ENDTASKFUNC 'endfunction' verilog/parser_sv.v:147: TASK 'task' 'foreach_memref' verilog/parser_sv.v:148: VAR 'var' 'mem' 'task' '' 'bit [0:52][7:0]' '' '' verilog/parser_sv.v:149: COMMENT '// It's *not* legal according to the grammar to have dotted/package ids here' verilog/parser_sv.v:151: ENDTASKFUNC 'endtask' verilog/parser_sv.v:154: CLASS 'class' 'PreTypedefedClass' '' verilog/parser_sv.v:155: FUNCTION 'function' 'new' '' verilog/parser_sv.v:155: ENDTASKFUNC 'endfunction' verilog/parser_sv.v:156: ENDCLASS 'endclass' verilog/parser_sv.v:159: CLASS 'class' 'NewInNew' '' verilog/parser_sv.v:160: FUNCTION 'function' 'new' '' verilog/parser_sv.v:162: ENDTASKFUNC 'endfunction' verilog/parser_sv.v:165: COMMENT '// std package' verilog/parser_sv.v:163: ENDCLASS 'endclass' verilog/parser_sv.v:166: CLASS 'class' 'TryStd' '' verilog/parser_sv.v:167: VAR 'var' 's1' 'class' '' 'semaphore' '' '' verilog/parser_sv.v:168: VAR 'var' 's2' 'class' '' 'std::semaphore' '' '' verilog/parser_sv.v:169: PIN '' 'integer' '1' verilog/parser_sv.v:169: VAR 'var' 'm1' 'class' '' 'mailbox' '' '' verilog/parser_sv.v:170: VAR 'var' 'm2' 'class' '' 'std::mailbox' '' '' verilog/parser_sv.v:171: VAR 'var' 'p1' 'class' '' 'process' '' '' verilog/parser_sv.v:172: VAR 'var' 'p2' 'class' '' 'std::process' '' '' verilog/parser_sv.v:173: ENDCLASS 'endclass' verilog/parser_sv.v:175: MODULE 'module' 'cg_test1' undef '0' verilog/parser_sv.v:176: COVERGROUP 'covergroup' 'counter1' verilog/parser_sv.v:184: ENDGROUP 'endgroup' verilog/parser_sv.v:185: ENDMODULE 'endmodule' verilog/parser_sv.v:187: TASK 'task' 'randomize_dotted' verilog/parser_sv.v:188: VAR 'var' 'vbl' 'task' '' 'int' '' '' verilog/parser_sv.v:190: ENDTASKFUNC 'endtask' verilog/parser_sv.v:192: MODULE 'module' 'prop_parens' undef '0' verilog/parser_sv.v:194: ENDMODULE 'endmodule' verilog/parser_sv.v:196: CLASS 'class' 'this_dot_tests' '' verilog/parser_sv.v:197: TASK 'task' 'ass' verilog/parser_sv.v:199: ENDTASKFUNC 'endtask' verilog/parser_sv.v:200: ENDCLASS 'endclass' verilog/parser_sv.v:202: MODULE 'module' 'sized_out' undef '0' verilog/parser_sv.v:203: VAR 'parameter' 'SZ' 'module' '' '' '' '4' verilog/parser_sv.v:204: VAR 'port' 'o_sized' 'module' '' 'logic [SZ-1:0]' '' '' verilog/parser_sv.v:204: PORT 'o_sized' 'module' 'output' 'logic [SZ-1:0]' '' '1' verilog/parser_sv.v:205: ENDMODULE 'endmodule' verilog/parser_sv.v:207: CLASS 'class' 'solve_size' '' verilog/parser_sv.v:208: VAR 'var' 'arrayed' 'class' '' 'rand byte' '' '' verilog/parser_sv.v:209: VAR 'var' 'b' 'class' '' 'rand bit' '' '' verilog/parser_sv.v:210: COMMENT '// The dot below doesn't seem legal according to grammar, but' verilog/parser_sv.v:211: COMMENT '// the intent makes sense, and it appears in the VMM' verilog/parser_sv.v:213: ENDCLASS 'endclass' verilog/parser_sv.v:215: CLASS 'class' 'vmm_stuff' '' verilog/parser_sv.v:216: TASK 'task' 'examples' verilog/parser_sv.v:220: ENDTASKFUNC 'endtask' verilog/parser_sv.v:221: FUNCTION 'function' 'foo1' 'bit' verilog/parser_sv.v:221: ENDTASKFUNC 'endfunction' verilog/parser_sv.v:222: FUNCTION 'function' 'foo2' 'void' verilog/parser_sv.v:222: ENDTASKFUNC 'endfunction' verilog/parser_sv.v:223: VAR 'var' 'foo3' 'class' '' 'protected static string' '' '' verilog/parser_sv.v:224: FUNCTION 'function' 'foo4' 'bit' verilog/parser_sv.v:224: ENDTASKFUNC 'endfunction' verilog/parser_sv.v:225: VAR 'var' 'foo5' 'class' '' 'static local bit' '[string]' '' verilog/parser_sv.v:226: ENDCLASS 'endclass' verilog/parser_sv.v:228: CLASS 'class' 'vmm_cl_func_colon' '' verilog/parser_sv.v:229: VAR 'typedef' 'restart_e' 'class' '' 'int unsigned' '' '' verilog/parser_sv.v:230: FUNCTION 'function' 'do_all' 'void' verilog/parser_sv.v:230: VAR 'port' 'kind' 'function' '' 'vmm_cl_func_colon::restart_e' '' 'vmm_cl_func_colon::FIRM' verilog/parser_sv.v:230: PORT 'kind' 'function' 'input' 'vmm_cl_func_colon::restart_e' '' '1' verilog/parser_sv.v:231: ENDTASKFUNC 'endfunction' verilog/parser_sv.v:232: FUNCTION 'function' 'uses_class_type' 'int' verilog/parser_sv.v:232: ENDTASKFUNC 'endfunction' verilog/parser_sv.v:233: ENDCLASS 'endclass' verilog/parser_sv.v:235: CLASS 'class' 'vmm_cl_subenv' '' verilog/parser_sv.v:236: TASK 'task' 'do_reset' verilog/parser_sv.v:236: VAR 'port' 'kind' 'task' '' 'vmm_cl_func_colon::restart_e' '' 'vmm_cl_func_colon::FIRM' verilog/parser_sv.v:236: PORT 'kind' 'task' 'input' 'vmm_cl_func_colon::restart_e' '' '1' verilog/parser_sv.v:236: ENDTASKFUNC 'endtask' verilog/parser_sv.v:237: ENDCLASS 'endclass' verilog/parser_sv.v:239: TASK 'task' 'empty_comma' verilog/parser_sv.v:244: ENDTASKFUNC 'endtask' verilog/parser_sv.v:246: TASK 'task' 'vmm_more' verilog/parser_sv.v:249: COMMENT '// Not part of 1800-2005 grammar, but likely in 1800-2009' verilog/parser_sv.v:254: COMMENT '// Extern Functions/tasks when defined must scope to the class they're in to get appropriate types' verilog/parser_sv.v:252: ENDTASKFUNC 'endtask' verilog/parser_sv.v:255: FUNCTION 'function' 'vmm_cl_func_colon::uses_class_type' 'int' verilog/parser_sv.v:255: VAR 'port' 'note_uses_class_type' 'function' '' 'restart_e' '' '' verilog/parser_sv.v:255: PORT 'note_uses_class_type' 'function' 'input' 'restart_e' '' '1' verilog/parser_sv.v:256: VAR 'var' 'also_uses_class_type' 'function' '' 'restart_e' '' '' verilog/parser_sv.v:257: ENDTASKFUNC 'endfunction' verilog/parser_sv.v:259: MODULE 'module' 'hidden_checks' undef '0' verilog/parser_sv.v:260: VAR 'typedef' 'T' 'module' '' 'int' '' '' verilog/parser_sv.v:261: INSTANT 'sub' '' '' verilog/parser_sv.v:261: PIN 'T' '123' '1' verilog/parser_sv.v:261: ENDCELL '' verilog/parser_sv.v:261: COMMENT '// Different T' verilog/parser_sv.v:262: TASK 'task' 'hidden' verilog/parser_sv.v:263: VAR 'typedef' 'T' 'task' '' 'bit' '' '' verilog/parser_sv.v:263: COMMENT '// Different T' verilog/parser_sv.v:264: ENDTASKFUNC 'endtask' verilog/parser_sv.v:265: ENDMODULE 'endmodule' verilog/parser_sv.v:268: VAR 'member' 'm_a' 'struct' '' 'rand int' '' '' verilog/parser_sv.v:269: VAR 'member' 'm_b' 'struct' '' 'bit [7:0]' '' '' verilog/parser_sv.v:267: VAR 'typedef' 't_bug91' 'netlist' '' 'struct' '' '' verilog/parser_sv.v:271: VAR 'var' 'v_bug91' 'netlist' '' 't_bug91' '' '' verilog/parser_sv.v:273: MODULE 'module' 'bug98' undef '0' verilog/parser_sv.v:273: VAR 'port' 'x_if' 'module' '' 'interfacex' '' '' verilog/parser_sv.v:273: PORT 'x_if' 'module' 'interface' 'interfacex' '' '1' verilog/parser_sv.v:273: INSTANT 'interfacex' 'x_if' '' verilog/parser_sv.v:273: ENDCELL '' verilog/parser_sv.v:274: INSTANT 'h' 'inst_h' '' verilog/parser_sv.v:274: PIN 'push' 'x_if.pop' '1' verilog/parser_sv.v:274: ENDCELL '' verilog/parser_sv.v:275: ENDMODULE 'endmodule' verilog/parser_sv.v:277: MODULE 'module' 'bugas' undef '0' verilog/parser_sv.v:281: ENDMODULE 'endmodule' verilog/parser_sv.v:283: VAR 'typedef' 'enum_ranged_t' 'netlist' '' '[2:0]' '' '' verilog/parser_sv.v:285: VAR 'member' 'val' 'struct' '' 'logic' '' '' verilog/parser_sv.v:285: VAR 'typedef' 't_bug202_struct' 'netlist' '' 'struct' '' '' verilog/parser_sv.v:286: VAR 'member' 'val' 'union' '' 'logic' '' '' verilog/parser_sv.v:286: VAR 'typedef' 't_bug202_union' 'netlist' '' 'union' '' '' verilog/parser_sv.v:288: CLASS 'class' 'ln288' '' verilog/parser_sv.v:289: FUNCTION 'function' 'extvirtstr' 'string' verilog/parser_sv.v:289: ENDTASKFUNC 'endfunction' verilog/parser_sv.v:290: TASK 'task' 'extvirttask' verilog/parser_sv.v:290: ENDTASKFUNC 'endtask' verilog/parser_sv.v:291: ENDCLASS 'endclass' verilog/parser_sv.v:293: CLASS 'class' 'cl_to_init' '' verilog/parser_sv.v:294: FUNCTION 'function' 'new' '' verilog/parser_sv.v:294: ENDTASKFUNC 'endfunction' verilog/parser_sv.v:295: FUNCTION 'function' 'init' 'cl_to_init' verilog/parser_sv.v:295: ENDTASKFUNC 'endfunction' verilog/parser_sv.v:296: ENDCLASS 'endclass' verilog/parser_sv.v:297: FUNCTION 'function' 'cl_to_init::init' 'cl_to_init' verilog/parser_sv.v:298: ENDTASKFUNC 'endfunction' verilog/parser_sv.v:299: FUNCTION 'function' 'new' '' verilog/parser_sv.v:300: ENDTASKFUNC 'endfunction' verilog/parser_sv.v:301: VAR 'var' 'cl_inited' 'netlist' '' 'cl_to_init' '' 'cl_to_init::init()' verilog/parser_sv.v:303: COMMENT '// pure virtual functions have no endfunction.' verilog/parser_sv.v:304: CLASS 'class' 'pure_virt_func_class' 'virtual' verilog/parser_sv.v:305: FUNCTION 'function' 'pure_virt_func' 'string' verilog/parser_sv.v:305: ENDTASKFUNC 'endfunction' verilog/parser_sv.v:306: TASK 'task' 'pure_virt_task' verilog/parser_sv.v:306: ENDTASKFUNC 'endtask' verilog/parser_sv.v:307: ENDCLASS 'endclass' verilog/parser_sv.v:309: CLASS 'class' 'extend_base' '' verilog/parser_sv.v:310: VAR 'typedef' 'base_enum' 'class' '' 'enum' '' '' verilog/parser_sv.v:311: FUNCTION 'function' 'create' 'extend_base' verilog/parser_sv.v:311: ENDTASKFUNC 'endfunction' verilog/parser_sv.v:312: ENDCLASS 'endclass' verilog/parser_sv.v:313: CLASS 'class' 'extended' '' verilog/parser_sv.v:314: VAR 'typedef' 'be_t' 'class' '' 'base_enum' '' '' verilog/parser_sv.v:314: COMMENT '// type must come from base class' verilog/parser_sv.v:315: FUNCTION 'function' 'create' 'int' verilog/parser_sv.v:315: COMMENT '// Must override base's create' verilog/parser_sv.v:316: VAR 'var' 'mye' 'function' '' 'be_t' '' '' verilog/parser_sv.v:317: ENDTASKFUNC 'endfunction' verilog/parser_sv.v:318: ENDCLASS 'endclass' verilog/parser_sv.v:320: TASK 'task' 'rand_with_ln320' verilog/parser_sv.v:323: ENDTASKFUNC 'endtask' verilog/parser_sv.v:324: TASK 'task' 'apply_request' verilog/parser_sv.v:324: VAR 'port' 'data_req' 'task' '' '' '' '' verilog/parser_sv.v:324: PORT 'data_req' 'task' 'input' '' '' '1' verilog/parser_sv.v:324: VAR 'port' 'randomize' 'task' '' 'bit' '' '1' verilog/parser_sv.v:324: PORT 'randomize' 'task' 'input' 'bit' '' '2' verilog/parser_sv.v:326: COMMENT '// Generic method, not std::randomize' verilog/parser_sv.v:328: ENDTASKFUNC 'endtask' verilog/parser_sv.v:330: TASK 'task' 'foreach_class_scope_ln330' verilog/parser_sv.v:332: ENDTASKFUNC 'endtask' verilog/parser_sv.v:334: MODULE 'module' 'clkif_334' undef '0' verilog/parser_sv.v:336: ENDMODULE 'endmodule' verilog/parser_sv.v:338: MODULE 'module' 'gen_ln338' undef '0' verilog/parser_sv.v:345: ENDMODULE 'endmodule' verilog/parser_sv.v:347: MODULE 'module' 'par_packed' undef '0' verilog/parser_sv.v:348: VAR 'parameter' 'P1' 'module' '' 'logic [31:0]' '[3:0]' ''{1,2,3,4}' verilog/parser_sv.v:348: COMMENT '// unpacked array' verilog/parser_sv.v:349: VAR 'member' 'ecc' 'struct' '' 'logic' '' '' verilog/parser_sv.v:349: VAR 'member' 'data' 'struct' '' 'logic [7:0]' '' '' verilog/parser_sv.v:349: VAR 'net' 'memsig' 'module' 'wire' 'struct' '' '' verilog/parser_sv.v:350: ENDMODULE 'endmodule' verilog/parser_sv.v:352: MODULE 'module' 'not_a_bug315' undef '0' verilog/parser_sv.v:353: VAR 'typedef' 'supply_net_t' 'module' '' 'int' '' '' verilog/parser_sv.v:354: VAR 'port' 'i' 'module' '' 'int' '' '' verilog/parser_sv.v:354: PORT 'i' 'module' 'input' 'int' '' '0' verilog/parser_sv.v:355: VAR 'port' 'i' 'module' '' 'imp_test_pkg::byte_t' '' '' verilog/parser_sv.v:355: PORT 'i' 'module' 'input' 'imp_test_pkg::byte_t' '' '0' verilog/parser_sv.v:356: VAR 'port' 'bug316' 'module' '' 'supply_net_t' '' '' verilog/parser_sv.v:356: PORT 'bug316' 'module' 'input' 'supply_net_t' '' '0' verilog/parser_sv.v:357: ENDMODULE 'endmodule' verilog/parser_sv.v:359: MODULE 'module' 'bins_bracket' undef '0' verilog/parser_sv.v:360: VAR 'parameter' 'N' 'module' '' '' '' '2' verilog/parser_sv.v:361: COVERGROUP 'covergroup' 'cg_debitor' verilog/parser_sv.v:363: COMMENT '// 'std' overrides std:: package, which confuses VP' verilog/parser_sv.v:364: COMMENT '//bins std[] = { [0:N] };' verilog/parser_sv.v:366: ENDGROUP 'endgroup' verilog/parser_sv.v:367: ENDMODULE 'endmodule' verilog/parser_sv.v:369: CLASS 'class' 'ovm_void' 'virtual' verilog/parser_sv.v:370: ENDCLASS 'endclass' verilog/parser_sv.v:371: CLASS 'class' 'ovm_port_base' 'virtual' verilog/parser_sv.v:371: VAR 'parameter' 'IF' 'class' '' 'type' '' 'ovm_void' verilog/parser_sv.v:371: PORT 'IF' 'class' '' 'type' '' '1' verilog/parser_sv.v:372: ENDCLASS 'endclass' verilog/parser_sv.v:373: CLASS 'class' 'uvm_build_phase' 'virtual' verilog/parser_sv.v:373: VAR 'parameter' 'BASE' 'class' '' 'type' '' 'ovm_void' verilog/parser_sv.v:373: PORT 'BASE' 'class' '' 'type' '' '1' verilog/parser_sv.v:374: VAR 'var' 'type_name' 'class' '' 'static const string' '' '"uvm_build_phase"' verilog/parser_sv.v:375: ENDCLASS 'endclass' verilog/parser_sv.v:377: CLASS 'class' 'bug627sub' '' verilog/parser_sv.v:378: ENDCLASS 'endclass' verilog/parser_sv.v:379: CLASS 'class' 'bug627' '' verilog/parser_sv.v:379: VAR 'parameter' 'TYPE' 'class' '' 'type' '' 'bug627sub' verilog/parser_sv.v:379: PORT 'TYPE' 'class' '' 'type' '' '1' verilog/parser_sv.v:380: VAR 'typedef' 'types_t' 'class' '' 'TYPE' '[$]' '' verilog/parser_sv.v:381: FUNCTION 'function' 'f' 'types_t' verilog/parser_sv.v:384: ENDTASKFUNC 'endfunction' verilog/parser_sv.v:385: ENDCLASS 'endclass' verilog/parser_sv.v:387: INTERFACE 'interface' 'if_bug777' verilog/parser_sv.v:388: VAR 'net' 'a' 'interface' 'wire' '' '' '' verilog/parser_sv.v:389: MODPORT 'modport' 'master' verilog/parser_sv.v:389: VAR 'port' 'a' 'modport' '' '' '' 'a' verilog/parser_sv.v:389: PORT 'a' 'modport' 'input' '' '' '1' verilog/parser_sv.v:389: ENDMODPORT 'endmodport' verilog/parser_sv.v:390: MODPORT 'modport' 'slave' verilog/parser_sv.v:390: VAR 'port' 'a' 'modport' '' '' '' 'a' verilog/parser_sv.v:390: PORT 'a' 'modport' 'output' '' '' '1' verilog/parser_sv.v:390: ENDMODPORT 'endmodport' verilog/parser_sv.v:391: ENDINTERFACE 'endinterface' verilog/parser_sv.v:392: MODULE 'module' 'bug777' undef '0' verilog/parser_sv.v:392: PORT 'clk' 'module' '' '' '' '1' verilog/parser_sv.v:392: PORT 'ifport' 'module' '' '' '' '2' verilog/parser_sv.v:393: VAR 'port' 'clk' 'module' '' '' '' '' verilog/parser_sv.v:393: PORT 'clk' 'module' 'input' '' '' '0' verilog/parser_sv.v:394: INSTANT 'if_bug777' 'ifport' '' verilog/parser_sv.v:394: ENDCELL '' verilog/parser_sv.v:395: INSTANT 'if_bug777' 'ifportmp' '' verilog/parser_sv.v:395: ENDCELL '' verilog/parser_sv.v:396: COMMENT '//if_bug777.mp ifportmp (); // Not legal' verilog/parser_sv.v:397: COMMENT '// Currently unsupported, parens required so VP knows is instance' verilog/parser_sv.v:398: COMMENT '//if_bug777 ifport;' verilog/parser_sv.v:399: ENDMODULE 'endmodule' verilog/parser_sv.v:400: MODULE 'module' 'bug778' undef '0' verilog/parser_sv.v:401: VAR 'var' 'bar' 'module' '' 'virtual if_bug777' '' '' verilog/parser_sv.v:402: ENDMODULE 'endmodule' verilog/parser_sv.v:403: CLASS 'class' 'cls778' '' verilog/parser_sv.v:404: VAR 'var' 'bar' 'class' '' 'virtual if_bug777' '' '' verilog/parser_sv.v:405: ENDCLASS 'endclass' verilog/parser_sv.v:407: MODULE 'module' 'bug810' undef '0' verilog/parser_sv.v:408: COMMENT '/*parameter*/' verilog/parser_sv.v:408: VAR 'parameter' 'DW' 'module' '' 'int unsigned' '' '32' verilog/parser_sv.v:408: PORT 'DW' 'module' '' 'int unsigned' '' '1' verilog/parser_sv.v:409: ENDMODULE 'endmodule' verilog/parser_sv.v:410: INTERFACE 'interface' 'test_if' verilog/parser_sv.v:410: VAR 'port' 'clk' 'interface' '' '' '' '' verilog/parser_sv.v:410: PORT 'clk' 'interface' 'input' '' '' '1' verilog/parser_sv.v:411: ENDINTERFACE 'endinterface' verilog/parser_sv.v:413: MODULE 'module' 'bug815' undef '0' verilog/parser_sv.v:414: VAR 'port' 'bad' 'module' '' 'test_if' '[2]' '' verilog/parser_sv.v:414: PORT 'bad' 'module' 'interface' 'test_if' '[2]' '1' verilog/parser_sv.v:414: INSTANT 'test_if' 'bad' '[2]' verilog/parser_sv.v:414: ENDCELL '' verilog/parser_sv.v:415: ENDMODULE 'endmodule' verilog/parser_sv.v:417: MODULE 'module' 'bug868' undef '0' verilog/parser_sv.v:417: PORT 'ifmp' 'module' '' '' '' '1' verilog/parser_sv.v:418: INSTANT 'if_bug777' 'ifmp' '' verilog/parser_sv.v:418: ENDCELL '' verilog/parser_sv.v:419: ENDMODULE 'endmodule' verilog/parser_sv.v:421: MODULE 'module' 'bug_param_struct' undef '0' verilog/parser_sv.v:422: VAR 'parameter' 'ROWS' 'module' '' 'int' '' '2' verilog/parser_sv.v:422: PORT 'ROWS' 'module' '' 'int' '' '1' verilog/parser_sv.v:423: VAR 'member' 'row_id' 'struct' '' 'logic [ROWS-1:0]' '' '' verilog/parser_sv.v:423: VAR 'parameter' 'data_t' 'module' '' 'type' '' 'struct' verilog/parser_sv.v:424: VAR 'port' 'd' 'module' '' 'data_t' '' '' verilog/parser_sv.v:424: PORT 'd' 'module' 'input' 'data_t' '' '1' verilog/parser_sv.v:425: ENDMODULE 'endmodule' verilog/parser_sv09.v:001: COMMENT '// 1800-2009 mantis1769' verilog/parser_sv09.v:002: MODULE 'module' 'mantis1769' undef '0' verilog/parser_sv09.v:002: VAR 'parameter' 'N' 'module' '' '' '' '1' verilog/parser_sv09.v:002: PORT 'N' 'module' '' '' '' '1' verilog/parser_sv09.v:005: COMMENT '// 1800-2009 mantis1134' verilog/parser_sv09.v:004: ENDMODULE 'endmodule' verilog/parser_sv09.v:006: MODULE 'module' 'mantis1134_decoder' undef '0' verilog/parser_sv09.v:007: VAR 'parameter' 'BITS' 'module' '' '' '' '3' verilog/parser_sv09.v:007: PORT 'BITS' 'module' '' '' '' '1' verilog/parser_sv09.v:007: VAR 'localparam' 'OUT_BITS' 'module' '' '' '' '1< 4 } BEGIN { require "./t/test_utils.pl"; } ####################################################################### use Verilog::Getopt; use Verilog::Preproc; ok(1, "use"); # Check we get error SKIP: { if (`which gzip` !~ m!^/! || `which gunzip` !~ m!^/!) { skip("no gzip installed (harmless)",3); } system("gzip t/32_noinc.v -c > test_dir/33_gzip.v.gz"); ok (-r "test_dir/33_gzip.v.gz", "gzip test creation"); my $opt = new Verilog::Getopt; my $pp = new Verilog::Preproc (options=>$opt, include_open_nonfatal=>1,); $pp->open("test_dir/33_gzip.v.gz"); ok(1, "open"); my $hit; while (defined(my $line = $pp->getline())) { #print "TEXT $line"; $hit = 1 if $line =~ /text/; } ok ($hit, "decompress found text"); } Verilog-Perl-3.482/t/40_netlist.t0000755000177100017500000000451314553624300016441 0ustar wsnyderwsnyder#!/usr/bin/perl -w # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package # # Copyright 2000-2024 by Wilson Snyder. This program is free software; # you can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. use strict; use Test::More; BEGIN { plan tests => 17 } BEGIN { require "./t/test_utils.pl"; } #$Verilog::Netlist::Debug = 1; use Verilog::Netlist; ok(1, "use"); ##*** See also 41_example.t # Setup options so files can be found use Verilog::Getopt; my $opt = new Verilog::Getopt; $opt->parameter( "+incdir+verilog", "-y","verilog", ); # Prepare netlist my $nl = new Verilog::Netlist (options => $opt, keep_comments => 1, link_read_nonfatal=>1, ); foreach my $file ('verilog/v_hier_top.v', 'verilog/v_hier_top2.v', 'verilog/v_sv_mod.v' ) { $nl->read_file (filename=>$file); } # Read in any sub-modules $nl->link(); $nl->lint(); # Optional, see docs; probably not wanted $nl->exit_if_error(); print "Level tests\n"; is($nl->find_module("v_hier_top")->level, 3); is($nl->find_module("v_hier_sub")->level, 2); is($nl->find_module("v_hier_subsub")->level, 1); my @mods = map {$_->name} $nl->modules_sorted_level; is_deeply (\@mods, ['$root', 'v_hier_noport', 'v_hier_subsub', 'v_sv_pgm', 'v_hier_sub', 'v_hier_top2', 'v_recursive', 'v_hier_top', 'v_sv_mod']); # Width checks { my $mod = $nl->find_module("v_hier_top"); is (_width_of($mod,"WC_w1"), 1); is (_width_of($mod,"WC_w1b"), 1); is (_width_of($mod,"WC_w3"), 3); is (_width_of($mod,"WC_w4"), 4); is (_width_of($mod,"WC_p32"), 32); is (_width_of($mod,"WC_p1"), 1); is (_width_of($mod,"WC_p3"), 3); is (_width_of($mod,"WC_p4"), 4); is (_width_of($mod,"WC_pint"), 32); } # Port accessors { my $mod = $nl->find_module("v_hier_sub"); my @o = $mod->ports_sorted; ok ($#o == 2 && $o[0]->name eq 'avec'); @o = $mod->ports_ordered; ok ($#o == 2 && $o[0]->name eq 'clk'); } ok(1); sub _width_of { my $mod = shift; my $name = shift; if (!$mod) { warn "%Warning: No module found,"; return; } my $sig = $mod->find_net($name); if (!$sig) { warn "%Warning: No signal '$name' found,"; return; } return $sig->width; } Verilog-Perl-3.482/t/30_preproc_on.out0000644000177100017500000011746214030463163017473 0ustar wsnyderwsnyderverilog/inc_nonl.v:1: `line 1 "verilog/inc1.v" 1 verilog/inc_nonl.v:1: `line 1 "verilog/inc1.v" 0 verilog/inc_nonl.v:1: `line 1 "verilog/inc2.v" 1 verilog/inc_nonl.v:1: `line 1 "verilog/inc2.v" 0 verilog/inc_nonl.v:1: `line 1 "verilog/inc_ifdef.v" 1 verilog/inc_nonl.v:1: `line 1 "verilog/inc_ifdef.v" 0 verilog/inc_nonl.v:1: `line 1 "verilog/inc_nonl.v" 1 verilog/inc_nonl.v:1: `line 1 "verilog/inc_nonl.v" 0 verilog/inc_nonl.v:1: `line 1 "verilog/inc_def09.v" 1 verilog/inc_def09.v:1: // DESCRIPTION: Verilog-Perl: Verilog Test module verilog/inc_def09.v:2: // verilog/inc_def09.v:3: // This file ONLY is placed into the Public Domain, for any use, verilog/inc_def09.v:4: // without warranty, 2009 by Wilson Snyder. verilog/inc_def09.v:5: verilog/inc_def09.v:6: verilog/inc_def09.v:7: verilog/inc_def09.v:8: // Definitions as speced verilog/inc_def09.v:9: // Note there are trailing spaces, which spec doesn't show properly verilog/inc_def09.v:10: verilog/inc_def09.v:11: 'initial $display("start", "msg1" , "msg2", "end");' verilog/inc_def09.v:12: 'initial $display("start", "msg1" , "msg2" , "end");' verilog/inc_def09.v:13: 'initial $display("start", " msg1" , , "end");' verilog/inc_def09.v:14: 'initial $display("start", " msg1" , , "end");' verilog/inc_def09.v:15: 'initial $display("start", , "msg2 ", "end");' verilog/inc_def09.v:16: 'initial $display("start", , "msg2 ", "end");' verilog/inc_def09.v:17: 'initial $display("start", , , "end");' verilog/inc_def09.v:18: 'initial $display("start", , , "end");' verilog/inc_def09.v:19: 'initial $display("start", , , "end");' verilog/inc_def09.v:20: 'initial $display("start", , , "end");' verilog/inc_def09.v:21: //`D("msg1") // ILLEGAL: only one argument verilog/inc_def09.v:22: //`D() // ILLEGAL: only one empty argument verilog/inc_def09.v:23: //`D(,,) // ILLEGAL: more actual than formal arguments verilog/inc_def09.v:24: verilog/inc_def09.v:25: // Defaults: verilog/inc_def09.v:26: verilog/inc_def09.v:27: '$display(5,,2,,3);' verilog/inc_def09.v:28: '$display(5,,2,,3);' verilog/inc_def09.v:29: '$display(1,,"B",,3);' verilog/inc_def09.v:30: '$display(1 ,,"B",,3 );' verilog/inc_def09.v:31: '$display(5,,2,,);' verilog/inc_def09.v:32: '$display(5,,2,,);' verilog/inc_def09.v:33: //`MACRO1 ( 1 ) // ILLEGAL: b and c omitted, no default for c verilog/inc_def09.v:34: verilog/inc_def09.v:35: verilog/inc_def09.v:36: '$display(1,,,,3);' verilog/inc_def09.v:37: '$display(5,,,,"C");' verilog/inc_def09.v:38: '$display(5,,2,,"C");' verilog/inc_def09.v:39: '$display(5,,2,,"C");' verilog/inc_def09.v:40: '$display(5,,2,,"C");' verilog/inc_def09.v:41: '$display(5,,2,,"C");' verilog/inc_def09.v:42: verilog/inc_def09.v:43: verilog/inc_def09.v:44: '$display(1,,0,,"C");' verilog/inc_def09.v:45: '$display(1 ,,0,,"C");' verilog/inc_def09.v:46: '$display(5,,0,,"C");' verilog/inc_def09.v:47: '$display(5,,0,,"C");' verilog/inc_def09.v:48: //`MACRO3 // ILLEGAL: parentheses required verilog/inc_def09.v:49: verilog/inc_def09.v:50: verilog/inc_def09.v:51: 'b + 1 + 42 + a' verilog/inc_def09.v:52: 'b + 1 + 42 + a' verilog/inc_def09.v:53: verilog/inc_def09.v:54: // Local tests verilog/inc_def09.v:55: verilog/inc_def09.v:56: '"==)" "((((" () '; verilog/inc_def09.v:57: '"==)" "((((" () '; verilog/inc_def09.v:58: verilog/inc_def09.v:59: // Also check our line counting doesn't go bad verilog/inc_def09.v:62: verilog/inc_def09.v:62: verilog/inc_def09.v:62: verilog/inc_def09.v:63: verilog/inc_def09.v:64: verilog/inc_def09.v:65: verilog/inc_def09.v:66: verilog/inc_def09.v:67: verilog/inc_def09.v:68: verilog/inc_def09.v:69: verilog/inc_def09.v:70: '(6) (eq=al) ZOT' verilog/inc_def09.v:71: HERE-71 - Line71 verilog/inc_def09.v:72: verilog/inc_def09.v:73: //====================================================================== verilog/inc_def09.v:74: verilog/inc_def09.v:75: `line 75 "verilog/inc_def09.v" 2 verilog/inc_nonl.v:1: `line 1 "verilog/inc_nonl.v" 0 verilog/inc_nonl.v:1: // The lack of a newline on the next line is intentional verilog/inc_nonl.v:2: blah-no-newline-here> verilog/inc_nonl.v:3: `line 3 "verilog/inc_nonl.v" 2 verilog/inc_ifdef.v:1: `line 1 "verilog/inc_ifdef.v" 0 verilog/inc_ifdef.v:1: // DESCRIPTION: Verilog::Preproc: Example source code verilog/inc_ifdef.v:2: // This file ONLY is placed into the Public Domain, for any use, verilog/inc_ifdef.v:3: // without warranty, 2000-2012 by Wilson Snyder. verilog/inc_ifdef.v:4: verilog/inc_ifdef.v:5: verilog/inc_ifdef.v:6: verilog/inc_ifdef.v:7: verilog/inc_ifdef.v:8: verilog/inc_ifdef.v:9: verilog/inc_ifdef.v:10: verilog/inc_ifdef.v:11: verilog/inc_ifdef.v:12: $display("1A"); verilog/inc_ifdef.v:13: verilog/inc_ifdef.v:14: verilog/inc_ifdef.v:15: verilog/inc_ifdef.v:16: $display("2A"); verilog/inc_ifdef.v:17: verilog/inc_ifdef.v:18: verilog/inc_ifdef.v:19: verilog/inc_ifdef.v:20: verilog/inc_ifdef.v:21: verilog/inc_ifdef.v:22: $display("3AELSE"); verilog/inc_ifdef.v:23: verilog/inc_ifdef.v:24: verilog/inc_ifdef.v:25: verilog/inc_ifdef.v:26: verilog/inc_ifdef.v:27: verilog/inc_ifdef.v:28: verilog/inc_ifdef.v:29: verilog/inc_ifdef.v:30: verilog/inc_ifdef.v:31: verilog/inc_ifdef.v:32: verilog/inc_ifdef.v:33: verilog/inc_ifdef.v:34: verilog/inc_ifdef.v:35: verilog/inc_ifdef.v:36: verilog/inc_ifdef.v:37: verilog/inc_ifdef.v:38: verilog/inc_ifdef.v:39: verilog/inc_ifdef.v:40: verilog/inc_ifdef.v:41: verilog/inc_ifdef.v:42: `line 42 "verilog/inc_ifdef.v" 2 verilog/inc2.v:1: `line 1 "verilog/inc2.v" 0 verilog/inc2.v:1: // DESCRIPTION: Verilog::Preproc: Example source code verilog/inc2.v:2: // This file ONLY is placed into the Public Domain, for any use, verilog/inc2.v:3: // without warranty, 2000-2012 by Wilson Snyder. verilog/inc2.v:4: At file "verilog/inc2.v" line 4 verilog/inc2.v:5: verilog/inc2.v:5: `line 5 "verilog/inc2.v" 0 verilog/inc2.v:5: `line 1 "verilog/t_preproc_inc3.vh" 1 verilog/t_preproc_inc3.vh:1: `line 2 "inc3_a_filename_from_line_directive" 0 inc3_a_filename_from_line_directive:2: // DESCRIPTION: Verilog::Preproc: Example source code inc3_a_filename_from_line_directive:3: // This file ONLY is placed into the Public Domain, for any use, inc3_a_filename_from_line_directive:4: // without warranty, 2000-2012 by Wilson Snyder. inc3_a_filename_from_line_directive:5: inc3_a_filename_from_line_directive:6: inc3_a_filename_from_line_directive:7: inc3_a_filename_from_line_directive:8: inc3_a_filename_from_line_directive:9: // FOO inc3_a_filename_from_line_directive:10: At file "inc3_a_filename_from_line_directive" line 10 inc3_a_filename_from_line_directive:11: inc3_a_filename_from_line_directive:12: inc3_a_filename_from_line_directive:13: // guard inc3_a_filename_from_line_directive:14: inc3_a_filename_from_line_directive:15: inc3_a_filename_from_line_directive:16: inc3_a_filename_from_line_directive:17: inc3_a_filename_from_line_directive:18: inc3_a_filename_from_line_directive:19: `line 19 "inc3_a_filename_from_line_directive" 2 verilog/inc2.v:5: `line 5 "verilog/inc2.v" 0 verilog/inc2.v:5: verilog/inc2.v:6: verilog/inc2.v:7: `line 7 "verilog/inc2.v" 2 verilog/inc1.v:1: `line 1 "verilog/inc1.v" 0 verilog/inc1.v:1: // DESCRIPTION: Verilog::Preproc: Example source code verilog/inc1.v:2: // This file ONLY is placed into the Public Domain, for any use, verilog/inc1.v:3: // without warranty, 2000-2012 by Wilson Snyder. verilog/inc1.v:4: text. verilog/inc1.v:5: verilog/inc1.v:6: //=========================================================================== verilog/inc1.v:7: // Includes verilog/inc1.v:8: verilog/inc1.v:9: //=========================================================================== verilog/inc1.v:10: // Defines verilog/inc1.v:11: verilog/inc1.v:12: verilog/inc1.v:13: verilog/inc1.v:14: // DEF_A0 set by command line verilog/inc1.v:15: wire [3:0] q = { verilog/inc1.v:16: 1'b1 , verilog/inc1.v:17: 1'b0 , verilog/inc1.v:18: 1'b1 , verilog/inc1.v:19: 1'b0 verilog/inc1.v:20: }; verilog/inc1.v:21: verilog/inc1.v:22: text. verilog/inc1.v:23: verilog/inc1.v:24: verilog/inc1.v:25: // but not verilog/inc1.v:26: foo /*this */ bar /* this too */ verilog/inc1.v:27: foobar2 verilog/inc1.v:28: verilog/inc1.v:29: verilog/inc1.v:29: verilog/inc1.v:29: verilog/inc1.v:32: verilog/inc1.v:33: verilog/inc1.v:33: verilog/inc1.v:33: verilog/inc1.v:33: verilog/inc1.v:37: verilog/inc1.v:38: /*******COMMENT*****/ verilog/inc1.v:39: first part verilog/inc1.v:39: `line 39 "verilog/inc1.v" 0 verilog/inc1.v:39: second part verilog/inc1.v:39: `line 39 "verilog/inc1.v" 0 verilog/inc1.v:39: third part verilog/inc1.v:40: { verilog/inc1.v:40: `line 40 "verilog/inc1.v" 0 verilog/inc1.v:40: a, verilog/inc1.v:40: `line 40 "verilog/inc1.v" 0 verilog/inc1.v:40: b, verilog/inc1.v:40: `line 40 "verilog/inc1.v" 0 verilog/inc1.v:40: c} verilog/inc1.v:41: Line_Preproc_Check 41 verilog/inc1.v:42: verilog/inc1.v:43: //=========================================================================== verilog/inc1.v:44: verilog/inc1.v:45: verilog/inc1.v:46: verilog/inc1.v:47: verilog/inc1.v:48: verilog/inc1.v:49: deep deep verilog/inc1.v:50: verilog/inc1.v:51: verilog/inc1.v:52: verilog/inc1.v:53: "Inside: `nosubst" verilog/inc1.v:54: "`nosubst" verilog/inc1.v:55: verilog/inc1.v:56: verilog/inc1.v:57: x y LLZZ x y verilog/inc1.v:58: p q LLZZ p q r s LLZZ r s LLZZ p q LLZZ p q r s LLZZ r s verilog/inc1.v:59: verilog/inc1.v:60: verilog/inc1.v:61: verilog/inc1.v:62: firstline comma","line LLZZ firstline comma","line verilog/inc1.v:63: verilog/inc1.v:64: verilog/inc1.v:65: x y LLZZ "x" y // Simulators disagree here; some substitute "a" others do not verilog/inc1.v:66: verilog/inc1.v:67: verilog/inc1.v:68: (a,b)(a,b) verilog/inc1.v:69: verilog/inc1.v:70: verilog/inc1.v:71: $display("left side: \"right side\"") verilog/inc1.v:72: verilog/inc1.v:73: verilog/inc1.v:74: bar_suffix more verilog/inc1.v:75: verilog/inc1.v:76: verilog/inc1.v:76: verilog/inc1.v:78: verilog/inc1.v:78: `line 78 "verilog/inc1.v" 0 verilog/inc1.v:78: $c("Zap(\"",bug1,"\");");; verilog/inc1.v:79: verilog/inc1.v:79: `line 79 "verilog/inc1.v" 0 verilog/inc1.v:79: $c("Zap(\"","bug2","\");");; verilog/inc1.v:80: verilog/inc1.v:81: /* Define inside comment: `DEEPER and `WITHTICK */ verilog/inc1.v:82: // More commentary: `zap(bug1); `zap("bug2"); verilog/inc1.v:83: verilog/inc1.v:84: //====================================================================== verilog/inc1.v:85: // display passthru verilog/inc1.v:86: verilog/inc1.v:87: verilog/inc1.v:88: verilog/inc1.v:89: verilog/inc1.v:90: verilog/inc1.v:91: // Doesn't expand verilog/inc1.v:92: verilog/inc1.v:93: initial begin verilog/inc1.v:94: //$display(`msg( \`, \`)); // Illegal verilog/inc1.v:95: $display("pre thrupre thrumid thrupost post: \"right side\""); verilog/inc1.v:96: $display("left side: \"right side\""); verilog/inc1.v:97: $display("left side: \"right side\""); verilog/inc1.v:98: $display("left_side: \"right_side\""); verilog/inc1.v:99: $display("na: \"right_side\""); verilog/inc1.v:100: $display("prep ( midp1 left_side midp2 ( outp ) ): \"right_side\""); verilog/inc1.v:101: $display("na: \"nana\""); verilog/inc1.v:102: $display("left_side right_side: \"left_side right_side\""); // Results vary between simulators verilog/inc1.v:103: $display(": \"\""); // Empty verilog/inc1.v:104: $display("left side: \"right side\""); verilog/inc1.v:105: $display("left side: \"right side\""); verilog/inc1.v:106: $display("standalone"); verilog/inc1.v:107: verilog/inc1.v:108: // Unspecified when the stringification has multiple lines verilog/inc1.v:109: verilog/inc1.v:109: verilog/inc1.v:111: $display("twoline: \"first second\""); verilog/inc1.v:112: //$display(`msg(left side, \ right side \ )); // Not sure \{space} is legal. verilog/inc1.v:113: $write("*-* All Finished *-*\n"); verilog/inc1.v:114: $finish; verilog/inc1.v:115: end verilog/inc1.v:116: endmodule verilog/inc1.v:117: verilog/inc1.v:118: //====================================================================== verilog/inc1.v:119: // rt.cpan.org bug34429 verilog/inc1.v:120: verilog/inc1.v:121: verilog/inc1.v:121: verilog/inc1.v:121: verilog/inc1.v:121: verilog/inc1.v:125: verilog/inc1.v:126: module add1 ( input wire d1, output wire o1); verilog/inc1.v:127: verilog/inc1.v:127: `line 127 "verilog/inc1.v" 0 verilog/inc1.v:127: wire tmp_d1 = d1; verilog/inc1.v:127: `line 127 "verilog/inc1.v" 0 verilog/inc1.v:127: wire tmp_o1 = tmp_d1 + 1; verilog/inc1.v:127: `line 127 "verilog/inc1.v" 0 verilog/inc1.v:127: assign o1 = tmp_o1 ; // expansion is OK verilog/inc1.v:128: endmodule verilog/inc1.v:129: module add2 ( input wire d2, output wire o2); verilog/inc1.v:130: verilog/inc1.v:130: `line 130 "verilog/inc1.v" 0 verilog/inc1.v:130: wire tmp_d2 = d2; verilog/inc1.v:130: `line 130 "verilog/inc1.v" 0 verilog/inc1.v:130: wire tmp_o2 = tmp_d2 + 1; verilog/inc1.v:130: `line 130 "verilog/inc1.v" 0 verilog/inc1.v:130: assign o2 = tmp_o2 ; // expansion is bad verilog/inc1.v:131: endmodule verilog/inc1.v:132: verilog/inc1.v:133: verilog/inc1.v:133: verilog/inc1.v:133: verilog/inc1.v:133: verilog/inc1.v:133: verilog/inc1.v:138: verilog/inc1.v:139: // parameterized macro with arguments that are macros verilog/inc1.v:140: verilog/inc1.v:141: verilog/inc1.v:142: verilog/inc1.v:143: verilog/inc1.v:144: verilog/inc1.v:144: `line 144 "verilog/inc1.v" 0 verilog/inc1.v:144: generate for (i=0; i<(3); i=i+1) begin verilog/inc1.v:144: `line 144 "verilog/inc1.v" 0 verilog/inc1.v:144: psl cover { m5k.f .ctl._ctl_mvldx_m1.d[i] & ~m5k.f .ctl._ctl_mvldx_m1.q[i] & !m5k.f .ctl._ctl_mvldx_m1.cond & ((m5k.f .ctl.alive & m5k.f .ctl.alive_m1))} report "fondNoRise: m5kc_fcl._ctl_mvldx_m1"; verilog/inc1.v:144: `line 144 "verilog/inc1.v" 0 verilog/inc1.v:144: psl cover { ~m5k.f .ctl._ctl_mvldx_m1.d[i] & m5k.f .ctl._ctl_mvldx_m1.q[i] & !m5k.f .ctl._ctl_mvldx_m1.cond & ((m5k.f .ctl.alive & m5k.f .ctl.alive_m1))} report "fondNoFall: m5kc_fcl._ctl_mvldx_m1"; verilog/inc1.v:144: `line 144 "verilog/inc1.v" 0 verilog/inc1.v:144: end endgenerate // ignorecmt verilog/inc1.v:145: verilog/inc1.v:146: //====================================================================== verilog/inc1.v:147: // Quotes are legal in protected blocks. Grr. verilog/inc1.v:148: module prot(); verilog/inc1.v:149: `protected verilog/inc1.v:150: I!#r#e6<_Q{{E2+]I3<[3s)1@D|'E''i!O?]jD>Jo_![Cl) verilog/inc1.v:151: #nj1]p,3^1~,="E@QZB\T)eU\pC#C|7=\$J$##A[@-@{Qk] verilog/inc1.v:152: `endprotected verilog/inc1.v:153: endmodule verilog/inc1.v:154: verilog/inc1.v:155: module prot2(); verilog/inc1.v:156: `pragma protect begin_protected verilog/inc1.v:157: `pragma protect encrypt_agent = "Whatever agent" verilog/inc1.v:158: `pragma protect encrypt_agent_info = "1.2.3" verilog/inc1.v:159: `pragma protect data_method = "aes128-cbc" verilog/inc1.v:160: `pragma protect key_keyowner = "Someone" verilog/inc1.v:161: `pragma protect key_keyname = "somekey", key_method = "rsa" verilog/inc1.v:162: `pragma protect key_block encoding = (enctype = "base64") verilog/inc1.v:163: wefjosdfjklajklasjkl verilog/inc1.v:164: `pragma protect data_block encoding = (enctype = "base64", bytes = 1059) verilog/inc1.v:165: I!#r#e6<_Q{{E2+]I3<[3s)1@D|'E''i!O?]jD>Jo_![Cl) verilog/inc1.v:166: #nj1]p,3^1~,="E@QZB\T)eU\pC#C|7=\$J$##A[@-@{Qk] verilog/inc1.v:167: `pragma protect end_protected verilog/inc1.v:168: `pragma reset protect verilog/inc1.v:169: endmodule verilog/inc1.v:170: verilog/inc1.v:171: module prot3(); verilog/inc1.v:172: //pragma protect begin_protected verilog/inc1.v:173: //pragma protect key_keyowner=Cadence Design Systems. verilog/inc1.v:174: //pragma protect key_keyname=CDS_KEY verilog/inc1.v:175: //pragma protect key_method=RC5 verilog/inc1.v:176: //pragma protect key_block verilog/inc1.v:177: zzZzZ/4ZzzZZZzzz4zZzZzZZZZzZzZ/Zz+33zZ2zz/zzzzzzzzZZZzZ4z+ZZZZz1 verilog/inc1.v:178: Z1ZzzzZZzZZzz9ZZZZ37zzZzZzZzzz9ZZzzZzZz9Zz64+z8Z7ZzZZZzzzzZZZzZz verilog/inc1.v:179: zzZzZZZzZ0463zzzzzZzZ6z00z4zZzzZZzzZzzzZZ8zzz09ZzZZZZZ== verilog/inc1.v:180: //pragma protect end_key_block verilog/inc1.v:181: //pragma protect digest_block verilog/inc1.v:182: ZzZZzzZ9ZZZZz2ZzzzZz/Zzzz8Z= verilog/inc1.v:183: //pragma protect end_digest_block verilog/inc1.v:184: //pragma protect data_block verilog/inc1.v:185: ZZZ8zZzz6ZZ/zZZ5zZZzzz3ZzzzZzZZZ6ZzZzZZZZZz1zzZZZZ7ZZZZz3Zzz+9zz verilog/inc1.v:186: 4zzz+8zZzzzzZzZZzzzZzz1Z7ZzZz+zZz8ZZZZzZ6ZzzZzZZzzZZzzZzzZzZzZzZ verilog/inc1.v:187: ZzzzzZ0zZz1ZzzZzzZzZzz== verilog/inc1.v:188: //pragma protect end_data_block verilog/inc1.v:189: //pragma protect digest_block verilog/inc1.v:190: Z4Z6zZzZ3Z7ZZ6zzZZZZzzzzZZZ= verilog/inc1.v:191: //pragma protect end_digest_block verilog/inc1.v:192: //pragma protect end_protected verilog/inc1.v:193: endmodule verilog/inc1.v:194: verilog/inc1.v:195: //====================================================================== verilog/inc1.v:196: // macro call with define that has comma verilog/inc1.v:197: verilog/inc1.v:198: verilog/inc1.v:199: verilog/inc1.v:200: verilog/inc1.v:201: verilog/inc1.v:202: verilog/inc1.v:203: verilog/inc1.v:204: verilog/inc1.v:205: begin addr <= (({regs[6], regs[7]} + 1)); rd <= 1; end and begin addr <= (({regs[6], regs[7]})); wdata <= (rdata); wr <= 1; end verilog/inc1.v:206: begin addr <= ({regs[6], regs[7]} + 1); rd <= 1; end verilog/inc1.v:207: begin addr <= ({regs[6], regs[7]}); wdata <= (rdata); wr <= 1; end more verilog/inc1.v:208: verilog/inc1.v:209: //====================================================================== verilog/inc1.v:210: // include of parameterized file verilog/inc1.v:211: verilog/inc1.v:212: verilog/inc1.v:212: `line 212 "verilog/inc1.v" 0 verilog/inc1.v:212: `line 1 "verilog/t_preproc_inc4.vh" 1 verilog/t_preproc_inc4.vh:1: // DESCRIPTION: Verilog::Preproc: Example source code verilog/t_preproc_inc4.vh:2: `line 2 "verilog/t_preproc_inc4.vh" 0 verilog/t_preproc_inc4.vh:2: // This file ONLY is placed into the Public Domain, for any use, verilog/t_preproc_inc4.vh:3: // without warranty, 2000-2012 by Wilson Snyder. verilog/t_preproc_inc4.vh:4: verilog/t_preproc_inc4.vh:5: verilog/t_preproc_inc4.vh:6: verilog/t_preproc_inc4.vh:7: `line 7 "verilog/t_preproc_inc4.vh" 2 verilog/inc1.v:212: `line 212 "verilog/inc1.v" 0 verilog/inc1.v:212: verilog/inc1.v:213: verilog/inc1.v:214: verilog/inc1.v:215: verilog/inc1.v:216: verilog/inc1.v:217: verilog/inc1.v:218: verilog/inc1.v:219: verilog/inc1.v:220: verilog/inc1.v:221: verilog/inc1.v:222: //====================================================================== verilog/inc1.v:223: // macro call with , in {} verilog/inc1.v:224: verilog/inc1.v:225: verilog/inc1.v:226: $blah("ab,cd","e,f"); verilog/inc1.v:227: $blah(this.logfile,vec); verilog/inc1.v:228: $blah(this.logfile,vec[1,2,3]); verilog/inc1.v:229: $blah(this.logfile,{blah.name(), " is not foo"}); verilog/inc1.v:230: verilog/inc1.v:231: //====================================================================== verilog/inc1.v:232: // pragma/default net type verilog/inc1.v:233: verilog/inc1.v:234: `pragma foo = 1 verilog/inc1.v:235: `default_nettype none verilog/inc1.v:236: `default_nettype uwire verilog/inc1.v:237: verilog/inc1.v:238: //====================================================================== verilog/inc1.v:239: // Ifdef verilog/inc1.v:240: verilog/inc1.v:241: verilog/inc1.v:242: verilog/inc1.v:243: verilog/inc1.v:244: verilog/inc1.v:245: Line_Preproc_Check 245 verilog/inc1.v:246: verilog/inc1.v:247: //====================================================================== verilog/inc1.v:248: // bug84 verilog/inc1.v:249: verilog/inc1.v:252: // Hello, comments MIGHT not be legal/*more,,)cmts*/// But newlines ARE legal... who speced THAT? verilog/inc1.v:252: verilog/inc1.v:252: verilog/inc1.v:253: (p,q) verilog/inc1.v:254: //Here verilog/inc1.v:255: verilog/inc1.v:256: //Too verilog/inc1.v:257: (x,y) verilog/inc1.v:258: Line_Preproc_Check 258 verilog/inc1.v:259: verilog/inc1.v:260: //====================================================================== verilog/inc1.v:261: // defines split arguments verilog/inc1.v:262: verilog/inc1.v:263: verilog/inc1.v:264: verilog/inc1.v:265: verilog/inc1.v:266: verilog/inc1.v:267: beginend // 2001 spec doesn't require two tokens, so "beginend" ok verilog/inc1.v:268: beginend // 2001 spec doesn't require two tokens, so "beginend" ok verilog/inc1.v:269: "beginend" // No space "beginend" verilog/inc1.v:270: verilog/inc1.v:271: //====================================================================== verilog/inc1.v:272: // bug106 verilog/inc1.v:273: verilog/inc1.v:274: verilog/inc1.v:275: `\esc`def verilog/inc1.v:276: verilog/inc1.v:277: Not a \`define verilog/inc1.v:278: verilog/inc1.v:279: //====================================================================== verilog/inc1.v:280: // misparsed comma in submacro verilog/inc1.v:281: verilog/inc1.v:282: verilog/inc1.v:283: verilog/inc1.v:284: verilog/inc1.v:285: x,y)--bee submacro has comma paren verilog/inc1.v:286: verilog/inc1.v:287: //====================================================================== verilog/inc1.v:288: // bug191 verilog/inc1.v:289: verilog/inc1.v:290: $display("10 %d %d", $bits(foo), 10); verilog/inc1.v:291: verilog/inc1.v:292: //====================================================================== verilog/inc1.v:293: // 1800-2009 verilog/inc1.v:294: verilog/inc1.v:295: verilog/inc1.v:296: verilog/inc1.v:297: verilog/inc1.v:298: verilog/inc1.v:299: verilog/inc1.v:300: //====================================================================== verilog/inc1.v:301: // bug202 verilog/inc1.v:302: verilog/inc1.v:302: verilog/inc1.v:302: verilog/inc1.v:302: verilog/inc1.v:302: verilog/inc1.v:302: verilog/inc1.v:302: verilog/inc1.v:302: verilog/inc1.v:302: verilog/inc1.v:302: verilog/inc1.v:302: verilog/inc1.v:313: verilog/inc1.v:314: verilog/inc1.v:314: `line 314 "verilog/inc1.v" 0 verilog/inc1.v:314: verilog/inc1.v:314: `line 314 "verilog/inc1.v" 0 verilog/inc1.v:314: verilog/inc1.v:314: `line 314 "verilog/inc1.v" 0 verilog/inc1.v:314: verilog/inc1.v:314: `line 314 "verilog/inc1.v" 0 verilog/inc1.v:314: verilog/inc1.v:314: `line 314 "verilog/inc1.v" 0 verilog/inc1.v:314: verilog/inc1.v:314: `line 314 "verilog/inc1.v" 0 verilog/inc1.v:314: verilog/inc1.v:314: `line 314 "verilog/inc1.v" 0 verilog/inc1.v:314: verilog/inc1.v:314: `line 314 "verilog/inc1.v" 0 verilog/inc1.v:314: verilog/inc1.v:314: `line 314 "verilog/inc1.v" 0 verilog/inc1.v:314: assign a3 = ~b3 ; verilog/inc1.v:314: `line 314 "verilog/inc1.v" 0 verilog/inc1.v:314: verilog/inc1.v:315: verilog/inc1.v:316: /* multi \ verilog/inc1.v:317: line1*/ \ verilog/inc1.v:318: /*multi \ verilog/inc1.v:320: line2*/ verilog/inc1.v:320: verilog/inc1.v:320: verilog/inc1.v:320: verilog/inc1.v:320: verilog/inc1.v:320: verilog/inc1.v:325: verilog/inc1.v:325: `line 325 "verilog/inc1.v" 0 verilog/inc1.v:325: /* multi verilog/inc1.v:325: line 3*/ verilog/inc1.v:325: `line 325 "verilog/inc1.v" 0 verilog/inc1.v:325: def i verilog/inc1.v:325: `line 325 "verilog/inc1.v" 0 verilog/inc1.v:325: verilog/inc1.v:326: verilog/inc1.v:327: //====================================================================== verilog/inc1.v:328: verilog/inc1.v:329: // verilator NOT IN DEFINE verilog/inc1.v:330: verilog/inc1.v:331: /* verilator NOT PART verilog/inc1.v:332: OF DEFINE */ verilog/inc1.v:333: verilog/inc1.v:333: verilog/inc1.v:337: // CMT NOT verilog/inc1.v:337: verilog/inc1.v:337: verilog/inc1.v:338: verilog/inc1.v:339: 1 (nodef) verilog/inc1.v:340: 2 /* verilator PART OF DEFINE */ (hasdef) verilog/inc1.v:341: 3 (nodef) verilog/inc1.v:342: 4 /* verilator PART verilog/inc1.v:342: OF DEFINE */ (nodef) verilog/inc1.v:343: `line 343 "verilog/inc1.v" 0 verilog/inc1.v:343: 5 also in verilog/inc1.v:343: `line 343 "verilog/inc1.v" 0 verilog/inc1.v:343: also3 (nodef) verilog/inc1.v:344: verilog/inc1.v:344: verilog/inc1.v:346: HAS a NEW verilog/inc1.v:346: `line 346 "verilog/inc1.v" 0 verilog/inc1.v:346: LINE verilog/inc1.v:347: verilog/inc1.v:348: //====================================================================== verilog/inc1.v:349: verilog/inc1.v:350: verilog/inc1.v:350: verilog/inc1.v:350: verilog/inc1.v:350: verilog/inc1.v:350: verilog/inc1.v:350: verilog/inc1.v:350: verilog/inc1.v:350: verilog/inc1.v:350: verilog/inc1.v:350: verilog/inc1.v:350: verilog/inc1.v:350: verilog/inc1.v:362: verilog/inc1.v:363: verilog/inc1.v:364: verilog/inc1.v:365: verilog/inc1.v:366: EXP: clxx_scen verilog/inc1.v:367: clxx_scen verilog/inc1.v:368: EXP: clxx_scen verilog/inc1.v:369: "clxx_scen" verilog/inc1.v:370: verilog/inc1.v:371: EXP: do if (start("verilog/inc1.v", 25)) begin message({"Blah-", "clx_scen", " end"}); end while(0); verilog/inc1.v:372: verilog/inc1.v:372: `line 372 "verilog/inc1.v" 0 verilog/inc1.v:372: do verilog/inc1.v:372: `line 372 "verilog/inc1.v" 0 verilog/inc1.v:372: /* synopsys translate_off */ verilog/inc1.v:372: `line 372 "verilog/inc1.v" 0 verilog/inc1.v:372: verilog/inc1.v:372: `line 372 "verilog/inc1.v" 0 verilog/inc1.v:372: verilog/inc1.v:372: `line 372 "verilog/inc1.v" 0 verilog/inc1.v:372: verilog/inc1.v:372: `line 372 "verilog/inc1.v" 0 verilog/inc1.v:372: if (start("verilog/inc1.v", 372)) begin verilog/inc1.v:372: `line 372 "verilog/inc1.v" 0 verilog/inc1.v:372: verilog/inc1.v:372: `line 372 "verilog/inc1.v" 0 verilog/inc1.v:372: message({"Blah-", "clx_scen", " end"}); verilog/inc1.v:372: `line 372 "verilog/inc1.v" 0 verilog/inc1.v:372: end verilog/inc1.v:372: `line 372 "verilog/inc1.v" 0 verilog/inc1.v:372: /* synopsys translate_on */ verilog/inc1.v:372: `line 372 "verilog/inc1.v" 0 verilog/inc1.v:372: while(0); verilog/inc1.v:373: verilog/inc1.v:374: //====================================================================== verilog/inc1.v:375: verilog/inc1.v:376: verilog/inc1.v:376: verilog/inc1.v:376: verilog/inc1.v:376: verilog/inc1.v:380: verilog/inc1.v:380: `line 380 "verilog/inc1.v" 0 verilog/inc1.v:380: verilog/inc1.v:380: `line 380 "verilog/inc1.v" 0 verilog/inc1.v:380: verilog/inc1.v:380: `line 380 "verilog/inc1.v" 0 verilog/inc1.v:380: verilog/inc1.v:381: verilog/inc1.v:382: //`ifndef def_fooed_2 `error "No def_fooed_2" `endif verilog/inc1.v:383: EXP: This is fooed verilog/inc1.v:384: This is fooed verilog/inc1.v:385: EXP: This is fooed_2 verilog/inc1.v:386: This is fooed_2 verilog/inc1.v:387: verilog/inc1.v:388: //====================================================================== verilog/inc1.v:389: verilog/inc1.v:390: np verilog/inc1.v:391: np verilog/inc1.v:392: //====================================================================== verilog/inc1.v:393: // It's unclear if the spec allows this; is text_macro_idenitfier before or after substitution? verilog/inc1.v:394: verilog/inc1.v:395: verilog/inc1.v:396: verilog/inc1.v:397: verilog/inc1.v:398: verilog/inc1.v:399: verilog/inc1.v:400: verilog/inc1.v:401: verilog/inc1.v:402: //====================================================================== verilog/inc1.v:403: // Metaprogramming verilog/inc1.v:404: verilog/inc1.v:405: verilog/inc1.v:406: verilog/inc1.v:407: verilog/inc1.v:408: verilog/inc1.v:409: verilog/inc1.v:410: verilog/inc1.v:411: verilog/inc1.v:412: verilog/inc1.v:413: verilog/inc1.v:414: hello3hello3hello3 verilog/inc1.v:415: hello4hello4hello4hello4 verilog/inc1.v:416: //====================================================================== verilog/inc1.v:417: // Include from stringification verilog/inc1.v:418: verilog/inc1.v:419: verilog/inc1.v:420: verilog/inc1.v:420: `line 420 "verilog/inc1.v" 0 verilog/inc1.v:420: `line 1 "verilog/t_preproc_inc4.vh" 1 verilog/t_preproc_inc4.vh:1: // DESCRIPTION: Verilog::Preproc: Example source code verilog/t_preproc_inc4.vh:2: `line 2 "verilog/t_preproc_inc4.vh" 0 verilog/t_preproc_inc4.vh:2: // This file ONLY is placed into the Public Domain, for any use, verilog/t_preproc_inc4.vh:3: // without warranty, 2000-2012 by Wilson Snyder. verilog/t_preproc_inc4.vh:4: verilog/t_preproc_inc4.vh:5: verilog/t_preproc_inc4.vh:6: verilog/t_preproc_inc4.vh:7: `line 7 "verilog/t_preproc_inc4.vh" 2 verilog/inc1.v:420: `line 420 "verilog/inc1.v" 0 verilog/inc1.v:420: verilog/inc1.v:421: verilog/inc1.v:422: //====================================================================== verilog/inc1.v:423: // Defines doing defines verilog/inc1.v:424: // Note the newline on the end - required to form the end of a define verilog/inc1.v:425: verilog/inc1.v:425: verilog/inc1.v:427: verilog/inc1.v:428: verilog/inc1.v:429: verilog/inc1.v:429: `line 429 "verilog/inc1.v" 0 verilog/inc1.v:429: verilog/inc1.v:430: verilog/inc1.v:431: verilog/inc1.v:432: verilog/inc1.v:433: Line_Preproc_Check 433 verilog/inc1.v:434: //====================================================================== verilog/inc1.v:435: // Quoted multiline - track line numbers, and insure \\n gets propagated verilog/inc1.v:436: verilog/inc1.v:436: verilog/inc1.v:438: verilog/inc1.v:439: Line_Preproc_Check 439 verilog/inc1.v:441: verilog/inc1.v:441: "FOO \ verilog/inc1.v:441: BAR " "arg_line1 \ verilog/inc1.v:441: arg_line2" "FOO \ verilog/inc1.v:441: BAR " verilog/inc1.v:442: `line 442 "verilog/inc1.v" 0 verilog/inc1.v:442: Line_Preproc_Check 442 verilog/inc1.v:443: //====================================================================== verilog/inc1.v:444: // bug283 verilog/inc1.v:445: verilog/inc1.v:446: verilog/inc1.v:447: verilog/inc1.v:448: verilog/inc1.v:449: // EXP: abc verilog/inc1.v:450: verilog/inc1.v:451: abc verilog/inc1.v:452: verilog/inc1.v:453: verilog/inc1.v:454: verilog/inc1.v:455: verilog/inc1.v:456: verilog/inc1.v:457: verilog/inc1.v:458: verilog/inc1.v:459: EXP: sonet_frame verilog/inc1.v:460: sonet_frame verilog/inc1.v:461: // verilog/inc1.v:462: verilog/inc1.v:463: verilog/inc1.v:464: EXP: sonet_frame verilog/inc1.v:465: sonet_frame verilog/inc1.v:466: // This result varies between simulators verilog/inc1.v:467: verilog/inc1.v:468: verilog/inc1.v:469: EXP: sonet_frame verilog/inc1.v:470: sonet_frame verilog/inc1.v:471: verilog/inc1.v:472: // The existance of non-existance of a base define can make a difference verilog/inc1.v:473: verilog/inc1.v:474: verilog/inc1.v:475: EXP: module zzz ; endmodule verilog/inc1.v:476: module zzz ; endmodule verilog/inc1.v:477: module zzz ; endmodule verilog/inc1.v:478: verilog/inc1.v:479: verilog/inc1.v:480: EXP: module a_b ; endmodule verilog/inc1.v:481: module a_b ; endmodule verilog/inc1.v:482: module a_b ; endmodule verilog/inc1.v:483: verilog/inc1.v:484: //====================================================================== verilog/inc1.v:485: // bug311 verilog/inc1.v:486: integer/*NEED_SPACE*/foo; verilog/inc1.v:487: //====================================================================== verilog/inc1.v:488: synth_test: verilog/inc1.v:489: // synopsys translate_off verilog/inc1.v:490: synthesis_turned_off verilog/inc1.v:491: // synthesis translate_on verilog/inc1.v:492: EXP: on verilog/inc1.v:493: //====================================================================== verilog/inc1.v:494: // bug441 verilog/inc1.v:495: module t; verilog/inc1.v:496: //----- verilog/inc1.v:497: // case provided verilog/inc1.v:498: // note this does NOT escape as suggested in the mail verilog/inc1.v:499: verilog/inc1.v:500: verilog/inc1.v:500: verilog/inc1.v:502: initial begin : \`LEX_CAT(a[0],_assignment) verilog/inc1.v:502: `line 502 "verilog/inc1.v" 0 verilog/inc1.v:502: $write("GOT%%m='%m' EXP='%s'\n", "t.\\`LEX_CAT(a[0],_assignment) "); end verilog/inc1.v:503: //----- verilog/inc1.v:504: // SHOULD(simulator-dependant): Backslash doesn't prevent arguments from verilog/inc1.v:505: // substituting and the \ staying in the expansion verilog/inc1.v:506: // Note space after name is important so when substitute it has ending whitespace verilog/inc1.v:507: verilog/inc1.v:507: verilog/inc1.v:509: initial begin : \a[0]_assignment_a[1] verilog/inc1.v:509: `line 509 "verilog/inc1.v" 0 verilog/inc1.v:509: $write("GOT%%m='%m' EXP='%s'\n", "t.\\a[0]_assignment_a[1] "); end verilog/inc1.v:510: verilog/inc1.v:511: //----- verilog/inc1.v:512: verilog/inc1.v:513: verilog/inc1.v:514: // RULE: Ignoring backslash does NOT allow an additional expansion level verilog/inc1.v:515: // (Because ESC gets expanded then the \ has it's normal escape meaning) verilog/inc1.v:516: initial begin : \`CAT(pp,suffix) $write("GOT%%m='%m' EXP='%s'\n", "t.\\`CAT(pp,suffix) "); end verilog/inc1.v:517: verilog/inc1.v:518: //----- verilog/inc1.v:519: verilog/inc1.v:520: verilog/inc1.v:520: verilog/inc1.v:522: // Similar to above; \ does not allow expansion after substitution verilog/inc1.v:523: initial begin : \`CAT(ff,bb) verilog/inc1.v:523: `line 523 "verilog/inc1.v" 0 verilog/inc1.v:523: $write("GOT%%m='%m' EXP='%s'\n", "t.\\`CAT(ff,bb) "); end verilog/inc1.v:524: verilog/inc1.v:525: //----- verilog/inc1.v:526: verilog/inc1.v:526: verilog/inc1.v:528: // MUST: Unknown macro with backslash escape stays as escaped symbol name verilog/inc1.v:529: initial begin : \`zzz verilog/inc1.v:529: `line 529 "verilog/inc1.v" 0 verilog/inc1.v:529: $write("GOT%%m='%m' EXP='%s'\n", "t.\\`zzz "); end verilog/inc1.v:530: verilog/inc1.v:531: //----- verilog/inc1.v:532: verilog/inc1.v:533: verilog/inc1.v:533: verilog/inc1.v:535: // SHOULD(simulator-dependant): Known macro with backslash escape expands verilog/inc1.v:536: initial begin : \`FOO verilog/inc1.v:536: `line 536 "verilog/inc1.v" 0 verilog/inc1.v:536: $write("GOT%%m='%m' OTHER_EXP='%s'\n OUR_EXP='%s'", "t.bar ","t.\\`FOO "); end verilog/inc1.v:537: // SHOULD(simulator-dependant): Prefix breaks the above verilog/inc1.v:538: initial begin : \xx`FOO verilog/inc1.v:538: `line 538 "verilog/inc1.v" 0 verilog/inc1.v:538: $write("GOT%%m='%m' EXP='%s'\n", "t.\\xx`FOO "); end verilog/inc1.v:539: verilog/inc1.v:540: //----- verilog/inc1.v:541: // MUST: Unknown macro not under call with backslash escape doesn't expand verilog/inc1.v:542: verilog/inc1.v:543: initial begin : \`UNKNOWN $write("GOT%%m='%m' EXP='%s'\n", "t.\\`UNKNOWN "); end verilog/inc1.v:544: //----- verilog/inc1.v:545: // MUST: Unknown macro not under call doesn't expand verilog/inc1.v:546: verilog/inc1.v:547: initial begin : \`DEF_NO_EXPAND $write("GOT%%m='%m' EXP='%s'\n", "t.\\`DEF_NO_EXPAND "); end verilog/inc1.v:548: verilog/inc1.v:549: //----- verilog/inc1.v:550: // bug441 derivative verilog/inc1.v:551: // SHOULD(simulator-dependant): Quotes doesn't prevent arguments from expanding (like backslashes above) verilog/inc1.v:552: verilog/inc1.v:553: initial $write("GOT='%s' EXP='%s'\n", "foo bar baz", "foo bar baz"); verilog/inc1.v:554: verilog/inc1.v:555: //----- verilog/inc1.v:556: // RULE: Because there are quotes after substituting STR, the `A does NOT expand verilog/inc1.v:557: verilog/inc1.v:558: verilog/inc1.v:559: initial $write("GOT='%s' EXP='%s'\n", "foo `A(bar) baz", "foo `A(bar) baz"); verilog/inc1.v:560: verilog/inc1.v:561: //---- verilog/inc1.v:562: // bug845 verilog/inc1.v:563: verilog/inc1.v:564: initial $write("Slashed=`%s'\n", "1//2.3"); verilog/inc1.v:565: //---- verilog/inc1.v:566: // bug915 verilog/inc1.v:567: verilog/inc1.v:567: verilog/inc1.v:569: initial verilog/inc1.v:569: `line 569 "verilog/inc1.v" 0 verilog/inc1.v:569: $display("%s%s","a1","b2c3\n"); verilog/inc1.v:570: endmodule verilog/inc1.v:571: verilog/inc1.v:572: //====================================================================== verilog/inc1.v:573: //bug1225 verilog/inc1.v:574: verilog/inc1.v:575: verilog/inc1.v:576: verilog/inc1.v:577: $display("RAM0"); verilog/inc1.v:578: $display("CPU"); verilog/inc1.v:579: verilog/inc1.v:580: verilog/inc1.v:581: verilog/inc1.v:582: verilog/inc1.v:583: verilog/inc1.v:584: verilog/inc1.v:585: verilog/inc1.v:586: XXE_FAMILY = XXE_ verilog/inc1.v:587: verilog/inc1.v:588: verilog/inc1.v:589: $display("XXE_ is defined"); verilog/inc1.v:590: verilog/inc1.v:591: verilog/inc1.v:592: verilog/inc1.v:593: XYE_FAMILY = XYE_ verilog/inc1.v:594: verilog/inc1.v:595: verilog/inc1.v:596: $display("XYE_ is defined"); verilog/inc1.v:597: verilog/inc1.v:598: verilog/inc1.v:599: verilog/inc1.v:600: XXS_FAMILY = XXS_some verilog/inc1.v:601: verilog/inc1.v:602: verilog/inc1.v:603: $display("XXS_some is defined"); verilog/inc1.v:604: verilog/inc1.v:605: verilog/inc1.v:606: verilog/inc1.v:607: XYS_FAMILY = XYS_foo verilog/inc1.v:608: verilog/inc1.v:609: verilog/inc1.v:610: $display("XYS_foo is defined"); verilog/inc1.v:611: verilog/inc1.v:612: verilog/inc1.v:613: //==== verilog/inc1.v:614: verilog/inc1.v:615: verilog/inc1.v:616: verilog/inc1.v:617: verilog/inc1.v:618: verilog/inc1.v:619: verilog/inc1.v:620: verilog/inc1.v:621: verilog/inc1.v:622: verilog/inc1.v:623: verilog/inc1.v:624: verilog/inc1.v:625: verilog/inc1.v:626: verilog/inc1.v:627: verilog/inc1.v:628: verilog/inc1.v:629: verilog/inc1.v:630: verilog/inc1.v:631: verilog/inc1.v:632: verilog/inc1.v:633: verilog/inc1.v:634: verilog/inc1.v:635: verilog/inc1.v:636: verilog/inc1.v:637: verilog/inc1.v:638: verilog/inc1.v:639: verilog/inc1.v:640: verilog/inc1.v:641: verilog/inc1.v:642: verilog/inc1.v:643: verilog/inc1.v:644: verilog/inc1.v:645: verilog/inc1.v:646: // NEVER verilog/inc1.v:647: verilog/inc1.v:648: //bug1227 verilog/inc1.v:649: verilog/inc1.v:650: (.mySig (myInterface.pa5), verilog/inc1.v:651: verilog/inc1.v:652: //====================================================================== verilog/inc1.v:653: // Stringify bug verilog/inc1.v:654: verilog/inc1.v:655: verilog/inc1.v:656: `dbg_hdl(UVM_LOW, ("Functional coverage enabled: paramgrp")); verilog/inc1.v:657: verilog/inc1.v:658: verilog/inc1.v:659: verilog/inc1.v:659: verilog/inc1.v:661: verilog/inc1.v:661: verilog/inc1.v:661: verilog/inc1.v:661: verilog/inc1.v:665: verilog/inc1.v:666: module pcc2_cfg; verilog/inc1.v:667: generate verilog/inc1.v:668: verilog/inc1.v:668: `line 668 "verilog/inc1.v" 0 verilog/inc1.v:668: covergroup a @(posedge b); verilog/inc1.v:668: `line 668 "verilog/inc1.v" 0 verilog/inc1.v:668: c: coverpoint d iff ((c) === 1'b1); endgroup verilog/inc1.v:668: `line 668 "verilog/inc1.v" 0 verilog/inc1.v:668: a u_a; verilog/inc1.v:668: `line 668 "verilog/inc1.v" 0 verilog/inc1.v:668: initial do begin $display ("DEBUG : %s [%m]", $sformatf ("Functional coverage enabled: u_a")); end while(0); verilog/inc1.v:669: endgenerate verilog/inc1.v:670: endmodule verilog/inc1.v:671: verilog/inc1.v:672: //====================================================================== verilog/inc1.v:673: // Verilog-Perl bug1668 verilog/inc1.v:674: verilog/inc1.v:675: "`NOT_DEFINED_STR" verilog/inc1.v:676: verilog/inc1.v:677: //====================================================================== verilog/inc1.v:678: // IEEE mandated predefines verilog/inc1.v:679: // undefineall should have no effect on these verilog/inc1.v:680: predef 0 0 verilog/inc1.v:681: predef 1 1 verilog/inc1.v:682: predef 2 2 verilog/inc1.v:683: predef 3 3 verilog/inc1.v:684: predef 10 10 verilog/inc1.v:685: predef 11 11 verilog/inc1.v:686: predef 20 20 verilog/inc1.v:687: predef 21 21 verilog/inc1.v:688: predef 22 22 verilog/inc1.v:689: predef 23 23 verilog/inc1.v:690: predef -2 -2 verilog/inc1.v:691: predef -1 -1 verilog/inc1.v:692: predef 0 0 verilog/inc1.v:693: predef 1 1 verilog/inc1.v:694: predef 2 2 verilog/inc1.v:695: verilog/inc1.v:696: `line 696 "verilog/inc1.v" 2 Verilog-Perl-3.482/t/50_vrename.out0000644000177100017500000000106713462165726016771 0ustar wsnyderwsnyder# Generated by vrename on Thu Jul 5 09:01:51 2007 # # Files read for this analysis: vfile "verilog/test.v" # # Original Signal Name Name to change to # -------------------- ----------------- # sigren "a" "a" #verilog/test.v sigren "b" "b" #verilog/test.v sigren "example" "example" #verilog/test.v sigren "result" "result" #verilog/test.v sigren "z" "z" #verilog/test.v # # Use M-x compile in emacs to automatically perform the changes: ## Local Variables: *** ## compile-command: "./vrename -change verilog/test.v " *** ## End: *** Verilog-Perl-3.482/t/56_editfiles_edit.out0000644000177100017500000000075613310275003020301 0ustar wsnyderwsnyder// DESCRIPTION: Verilog::Preproc: Example source code // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2007-2012 by Wilson Snyder. `celldefine a_front_matter; module a; wire replaced_inside_module_a; /* // double cmt */ endmodule b_front_matter; `ifdef B_HAS_X module b; `elsif module b (input x); `endif wire replaced_inside_module_b; // synopsys translate_off wire in_translate_off; // synopsys translate_on endmodule `endcelldefine Verilog-Perl-3.482/t/42_dumpcheck_1v_ps.out0000644000177100017500000000422713422450702020374 0ustar wsnyderwsnyderroot_module $root ( ); localparam GLOBAL_PARAM = 1; // Local Variables: // eval:(verilog-read-defines) // End: endroot_module module v_bug917 ( a, b, m); input a; // a-First output b; // b-Third // Third output m; // m-Second endmodule module v_bug917p ( a, b); input a; // a-First output b; // b-Secondparen // Third endmodule module v_comments ( a, b, c, d, d1, d2, d3); input a; // comment for a inout [10:0] b; output [0:10] c; // comment for c output reg d; output [32:0] d1; output [(MATH-1):0] d2; output [32-1:0] d3; var reg [11:0] e; // Comment for e endmodule module v_hier_noport ( ); parameter P; var reg internal; endmodule module v_hier_sub ( avec, clk, qvec); parameter FROM_DEFPARAM = 1; genvar K; genvar K_UNUSED; supply1 a1; // Outputs input [3:0] avec; // Comment for v_hier_sub, avec input clk; output [3:0] qvec; /* Comment for v_hier_sub, qvec */ v_hier_subsub #(.IGNORED('sh20)) subsub0 (.a(a1), .q(qvec[0])); v_hier_subsub subsub2 (.a(1'b0), .q(qvec[2])); endmodule module v_hier_subsub ( a, q); parameter IGNORED = 0; input signed a; output q; // Test protected //" endmodule module v_hier_top ( clk); localparam [0:0] WC_p1 = 0; localparam [2:0] WC_p3 = 0; localparam WC_p32 = 0; localparam [-1:2] WC_p4 = 0; localparam integer WC_pint = 0; // Assignments wire WC_w1; wire [0:0] WC_w1b; wire [2:0] WC_w3; wire [-1:2] WC_w4; wire asn_clk; input clk; /* pragma jsc_clk */ missing missing (); v_recursive #(.DEPTH(3)) recursive (); v_hier_sub sub (.avec({avec[3],avec[2:0]}), .clk(1'b0), .qvec(qvec[3:0])); defparam sub.FROM_DEFPARAM = 2; assign asn_clk = clk; endmodule module v_hier_top2 ( clk, iosig); input clk; inout [2:0] iosig; /* synthesis useioff = 1 //*synthesis fpga_attr = "BLAH=ON"//* synthesis fpga_pin = "A22"*/ /* synthesis aftersemi*/ // NetListName=F12_IO v_hier_noport noport (); v_hier_noport #(.P(1)) noporta [1:0] (); v_hier_noport #(.P(1)) noportp (); endmodule module v_recursive ( ); parameter DEPTH = 1; v_recursive #(.DEPTH(DEPTH-1)) recurse (); endmodule Verilog-Perl-3.482/t/42_dumpcheck_1.out0000644000177100017500000001640213422450702017502 0ustar wsnyderwsnyderModule:$root Kwd:root_module File:verilog/v_hier_top.v Net:GLOBAL_PARAM DeclT:localparam NetT: DataT: Array: Value:1 Module:v_bug917 Kwd:module File:verilog/v_comments.v Port:a Dir:in DataT: Array: Port:b Dir:out DataT: Array: Port:m Dir:out DataT: Array: Net:a O DeclT:port NetT:wire DataT: Array: Net:b I DeclT:port NetT:wire DataT: Array: Net:m I DeclT:port NetT:wire DataT: Array: Module:v_bug917p Kwd:module File:verilog/v_comments.v Port:a Dir:in DataT: Array: Port:b Dir:out DataT: Array: Net:a O DeclT:port NetT:wire DataT: Array: Net:b I DeclT:port NetT:wire DataT: Array: Module:v_comments Kwd:module File:verilog/v_comments.v Port:a Dir:in DataT: Array: Port:b Dir:inout DataT:[10:0] Array: Port:c Dir:out DataT:[0:10] Array: Port:d Dir:out DataT:[((2*32)-1):0] Array: Port:d1 Dir:out DataT:[32:0] Array: Port:d2 Dir:out DataT:[(MATH-1):0] Array: Port:d3 Dir:out DataT:[32-1:0] Array: Net:a O DeclT:port NetT: DataT: Array: Net:b DeclT:port NetT: DataT:[10:0] Array: 10:0 Net:c I DeclT:port NetT: DataT:[0:10] Array: 0:10 Net:d I DeclT:port NetT: DataT:reg Array: ((2*32)-1):0 Net:d1 I DeclT:port NetT: DataT:[32:0] Array: 32:0 Net:d2 I DeclT:port NetT: DataT:[(MATH-1):0] Array: (MATH-1):0 Net:d3 I DeclT:port NetT: DataT:[32-1:0] Array: 32-1:0 Net:e DeclT:var NetT: DataT:reg [11:0] Array: 11:0 Module:v_hier_noport Kwd:module File:verilog/v_hier_noport.v Net:P DeclT:parameter NetT: DataT: Array: Net:internal DeclT:var NetT: DataT:reg Array: Module:v_hier_sub Kwd:module File:verilog/v_hier_sub.v Port:avec Dir:in DataT:[3:0] Array: Port:clk Dir:in DataT: Array: Port:qvec Dir:out DataT:[3:0] Array: Net:FROM_DEFPARAM DeclT:parameter NetT: DataT: Array: Value:1 Net:K DeclT:genvar NetT: DataT: Array: Net:K_UNUSED DeclT:genvar NetT: DataT: Array: Net:a1 I DeclT:net NetT:supply1 DataT: Array: Net:avec O DeclT:port NetT: DataT:[3:0] Array: 3:0 Net:clk O DeclT:port NetT: DataT: Array: Net:qvec I DeclT:port NetT: DataT:[3:0] Array: 3:0 Cell:subsub0 is-a:v_hier_subsub .IGNORED('sh20) Module:v_hier_subsub Kwd:module File:verilog/v_hier_subsub.v Pin:a Net:a1 Port:a Dir:in DataT:signed Array: Net:a1 I DeclT:net NetT:supply1 DataT: Array: Pin:q Net:qvec[0] Port:q Dir:out DataT: Array: Cell:subsub2 is-a:v_hier_subsub Module:v_hier_subsub Kwd:module File:verilog/v_hier_subsub.v Pin:a Net:1'b0 Port:a Dir:in DataT:signed Array: Pin:q Net:qvec[2] Port:q Dir:out DataT: Array: Module:v_hier_subsub Kwd:module File:verilog/v_hier_subsub.v Port:a Dir:in DataT:signed Array: Port:q Dir:out DataT: Array: Net:IGNORED DeclT:parameter NetT: DataT: Array: Value:0 Net:a O DeclT:port NetT: DataT:signed Array: Net:q I DeclT:port NetT:wire DataT: Array: Module:v_hier_top Kwd:module File:verilog/v_hier_top.v Port:clk Dir:in DataT: Array: Net:WC_p1 DeclT:localparam NetT: DataT:[0:0] Array: 0:0 Value:0 Net:WC_p3 DeclT:localparam NetT: DataT:[2:0] Array: 2:0 Value:0 Net:WC_p32 DeclT:localparam NetT: DataT: Array: Value:0 Net:WC_p4 DeclT:localparam NetT: DataT:[-1:2] Array: -1:2 Value:0 Net:WC_pint DeclT:localparam NetT: DataT:integer Array: Value:0 Net:WC_w1 DeclT:net NetT:wire DataT: Array: Net:WC_w1b DeclT:net NetT:wire DataT:[0:0] Array: 0:0 Net:WC_w3 DeclT:net NetT:wire DataT:[2:0] Array: 2:0 Net:WC_w4 DeclT:net NetT:wire DataT:[-1:2] Array: -1:2 Net:asn_clk DeclT:net NetT:wire DataT: Array: Net:clk O DeclT:port NetT: DataT: Array: Cell:missing is-a:missing Cell:recursive is-a:v_recursive .DEPTH(3) Module:v_recursive Kwd:module File:verilog/v_recursive.v Cell:sub is-a:v_hier_sub Module:v_hier_sub Kwd:module File:verilog/v_hier_sub.v Pin:avec Net:{avec[3],avec[2:0]} Port:avec Dir:in DataT:[3:0] Array: Pin:clk Net:1'b0 Port:clk Dir:in DataT: Array: Pin:qvec Net:qvec[3:0] Port:qvec Dir:out DataT:[3:0] Array: Defparam:defparam lhs:sub.FROM_DEFPARAM rhs:2 ContAssign:assign lhs:asn_clk rhs:clk Module:v_hier_top2 Kwd:module File:verilog/v_hier_top2.v Port:clk Dir:in DataT: Array: Port:iosig Dir:inout DataT:[2:0] Array: Net:clk O DeclT:port NetT: DataT: Array: Net:iosig DeclT:port NetT: DataT:[2:0] Array: 2:0 Cell:noport is-a:v_hier_noport Module:v_hier_noport Kwd:module File:verilog/v_hier_noport.v Cell:noporta is-a:v_hier_noport .P(1) Module:v_hier_noport Kwd:module File:verilog/v_hier_noport.v Cell:noportp is-a:v_hier_noport .P(1) Module:v_hier_noport Kwd:module File:verilog/v_hier_noport.v Module:v_recursive Kwd:module File:verilog/v_recursive.v Net:DEPTH DeclT:parameter NetT: DataT: Array: Value:1 Cell:recurse is-a:v_recursive .DEPTH(DEPTH-1) Module:v_recursive Kwd:module File:verilog/v_recursive.v #### Commentary: verilog/v_hier_top.v:0042: GLOBAL_PARAM cmt="// Local Variables:\n// eval:(verilog-read-defines)\n// End:" verilog/v_comments.v:0022: a cmt="// a-First" verilog/v_comments.v:0025: b cmt="// b-Third\n// Third" verilog/v_comments.v:0023: m cmt="// m-Second" verilog/v_comments.v:0031: a cmt="// a-First" verilog/v_comments.v:0032: b cmt="// b-Secondparen\n// Third" verilog/v_comments.v:0007: a cmt="// comment for a" verilog/v_comments.v:0008: b cmt="" verilog/v_comments.v:0009: c cmt="// comment for c" verilog/v_comments.v:0010: d cmt="" verilog/v_comments.v:0011: d1 cmt="" verilog/v_comments.v:0012: d2 cmt="" verilog/v_comments.v:0013: d3 cmt="" verilog/v_comments.v:0016: e cmt="// Comment for e" verilog/v_hier_noport.v:0006: P cmt="" verilog/v_hier_noport.v:0007: internal cmt="" verilog/v_hier_sub.v:0012: FROM_DEFPARAM cmt="" verilog/v_hier_sub.v:0027: K cmt="" verilog/v_hier_sub.v:0027: K_UNUSED cmt="" verilog/v_hier_sub.v:0014: a1 cmt="// Outputs" verilog/v_hier_sub.v:0008: avec cmt="// Comment for v_hier_sub, avec" verilog/v_hier_sub.v:0007: clk cmt="" verilog/v_hier_sub.v:0009: qvec cmt="/* Comment for v_hier_sub, qvec */" verilog/v_hier_subsub.v:0011: IGNORED cmt="" verilog/v_hier_subsub.v:0012: a cmt="" verilog/v_hier_subsub.v:0013: q cmt="// Test protected\n//"" verilog/v_hier_top.v:0031: WC_p1 cmt="" verilog/v_hier_top.v:0032: WC_p3 cmt="" verilog/v_hier_top.v:0030: WC_p32 cmt="" verilog/v_hier_top.v:0033: WC_p4 cmt="" verilog/v_hier_top.v:0034: WC_pint cmt="// Assignments" verilog/v_hier_top.v:0026: WC_w1 cmt="" verilog/v_hier_top.v:0027: WC_w1b cmt="" verilog/v_hier_top.v:0028: WC_w3 cmt="" verilog/v_hier_top.v:0029: WC_w4 cmt="" verilog/v_hier_top.v:0037: asn_clk cmt="" verilog/v_hier_top.v:0011: clk cmt="/* pragma jsc_clk */" verilog/v_hier_top2.v:0009: clk cmt="" verilog/v_hier_top2.v:0018: iosig cmt="/* synthesis useioff = 1 //*synthesis fpga_attr = "BLAH=ON"//* synthesis fpga_pin = "A22"*/\n/* synthesis aftersemi*/\n// NetListName=F12_IO" verilog/v_recursive.v:0002: DEPTH cmt="" Verilog-Perl-3.482/t/00_pod.t0000755000177100017500000000101014553624300015522 0ustar wsnyderwsnyder#!/usr/bin/perl -w # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package # # Copyright 2000-2024 by Wilson Snyder. This program is free software; # you can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. use strict; use Test; eval "use Test::Pod 1.00"; if ($@) { print "1..1\n"; print "ok 1 # skip Test::Pod not installed so ignoring Pod check (harmless)"; } else { all_pod_files_ok(); } Verilog-Perl-3.482/t/80_vppreproc_none.out0000644000177100017500000000131413741600370020356 0ustar wsnyderwsnyder`line 1 "verilog/inc2.v" 1 // DESCRIPTION: Verilog::Preproc: Example source code // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2000-2012 by Wilson Snyder. At file "verilog/inc2.v" line 4 `line 5 "verilog/inc2.v" 0 `line 1 "verilog/t_preproc_inc3.vh" 1 `line 2 "inc3_a_filename_from_line_directive" 0 // DESCRIPTION: Verilog::Preproc: Example source code // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2000-2012 by Wilson Snyder. // FOO At file "inc3_a_filename_from_line_directive" line 10 // guard `line 19 "inc3_a_filename_from_line_directive" 2 `line 5 "verilog/inc2.v" 0 `line 7 "verilog/inc2.v" 2 Verilog-Perl-3.482/t/42_dumpcheck.t0000755000177100017500000000710414553624300016723 0ustar wsnyderwsnyder#!/usr/bin/perl -w # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package # # Copyright 2000-2024 by Wilson Snyder. This program is free software; # you can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. use strict; use Test::More; BEGIN { plan tests => 17 } BEGIN { require "./t/test_utils.pl"; } #$Verilog::SigParser::Debug = $Verilog::Parser::Debug = 1; use Verilog::Netlist; ok(1, "use"); check ('test_dir/42.dmp', ['verilog/v_hier_top.v', 'verilog/v_hier_top2.v', 'verilog/v_comments.v'], [link_read_nonfatal=>1, keep_comments => 1,]); ok(1); ok(files_identical("test_dir/42.dmp", "t/42_dumpcheck_1.out")); ok(files_identical("test_dir/42.dmp.v", "t/42_dumpcheck_1v.out")); check ('test_dir/42_ps.dmp', ['verilog/v_hier_top.v', 'verilog/v_hier_top2.v', 'verilog/v_comments.v'], [link_read_nonfatal=>1, keep_comments => 1, use_pinselects => 1]); ok(1); ok(files_identical("test_dir/42_ps.dmp", "t/42_dumpcheck_1_ps.out")); ok(files_identical("test_dir/42_ps.dmp.v", "t/42_dumpcheck_1v_ps.out")); my $n2 = check ('test_dir/42_n2.dmp', ['verilog/pinorder.v'], [link_read_nonfatal=>1, keep_comments => 1,]); ok(1); ok(files_identical("test_dir/42_n2.dmp", "t/42_dumpcheck_2.out")); ok(files_identical("test_dir/42_n2.dmp.v", "t/42_dumpcheck_2v.out")); check ('test_dir/42_v2k.dmp', ['verilog/v_v2k.v'], [link_read_nonfatal=>1, keep_comments => 1,]); ok(1); ok(files_identical("test_dir/42_v2k.dmp", "t/42_dumpcheck_v2k.out")); ok(files_identical("test_dir/42_v2k.dmp.v", "t/42_dumpcheck_v2kv.out")); print "Edit tests\n"; $n2->find_module("pinorder4")->find_cell("foo3")->delete; $n2->find_module("pinorder4")->find_cell("foo1")->find_pin("x")->delete; $n2->find_module("pinorder4")->find_cell("foo1")->find_pin("def")->delete; $n2->find_module("pinorder4")->find_net("IPCD_const")->delete; $n2->find_module("foo2")->delete; vwrite($n2, "test_dir/42.ed.v"); ok(1); ok(files_identical("test_dir/42.ed.v", "t/42_dumpcheck_2e.out")); check ('test_dir/42_sv.dmp', ['verilog/v_sv_mod.v'], [link_read_nonfatal=>0, keep_comments => 1,]); ok(1); ok(files_identical("test_dir/42_sv.dmp", "t/42_dumpcheck_sv.out")); sub check { my $outfilename = shift; my $files = shift; my $nl_opts = shift; # Setup options so files can be found use Verilog::Getopt; my $opt = new Verilog::Getopt; $opt->parameter( "+incdir+verilog", "-y","verilog", ); my $nl = new Verilog::Netlist (options => $opt, link_read_nonfatal=>1, keep_comments => 1, @{$nl_opts}); foreach my $file (@{$files}) { $nl->read_file (filename=>$file); } # Read in any sub-modules $nl->link(); $nl->lint(); $nl->exit_if_error(); print "Dump\n"; { open (SAVEOUT, ">&STDOUT") or die "%Error: Can't dup stdout,"; if (0) { print SAVEOUT "To prevent used only once"; } open (STDOUT, ">$outfilename") or die "%Error: $! $outfilename,"; $nl->dump; print STDOUT "#### Commentary:\n"; foreach my $mod ($nl->modules_sorted) { foreach my $net ($mod->nets_sorted) { my $cmt = $net->comment||''; $cmt =~ s/\n/\\n/g; $cmt = qq{"$cmt"}; printf STDOUT "%s:%04d: %s cmt=%s\n" , $net->filename, $net->lineno, $net->name, $cmt; } } close(STDOUT); open (STDOUT, ">&SAVEOUT"); } vwrite($nl, $outfilename.".v"); return $nl; } sub vwrite { my $nl = shift; my $filename = shift; my $fh = IO::File->new($filename,"w") or die "%Error: $! writing $filename,"; print $fh $nl->verilog_text; $fh->close; } Verilog-Perl-3.482/t/42_dumpcheck_2e.out0000644000177100017500000000072213234726611017654 0ustar wsnyderwsnydermodule bug278 ( iow, iw, ow); inout iow; input iw; output ow; endmodule module foo ( abcconst, def, noconnect, x, y); input [2:0] abcconst; input [31:0] def; input signed [3:0] noconnect; input x; input y; endmodule module pinorder4 ( ); wire [7:0] a_i; wire b_i; wire d_o; foo foo1 (.abcconst(3'h0), .noconnect(), .y(b_i)); foo2 foo2 (.x(b_i), .y(d_o), .z(a_i[0])); assign a_i = 0; assign b_i = 0; endmodule Verilog-Perl-3.482/t/42_dumpcheck_v2k.out0000644000177100017500000000222413234726611020047 0ustar wsnyderwsnyderModule:v_v2k Kwd:module File:verilog/v_v2k.v Port:clk Dir:in DataT: Array: Port:rst Dir:in DataT: Array: Port:sig1 Dir:in DataT:[WIDTH:0] Array: Port:sig2 Dir:out DataT:reg [WIDTH:0] Array: Net:WIDTH DeclT:parameter NetT: DataT: Array: Value:16 Net:clk O DeclT:port NetT: DataT: Array: Net:netmd DeclT:net NetT:wire DataT:[1:2][3:4] Array: 1:2][3:4 Net:rst O DeclT:port NetT: DataT: Array: Net:sig1 O DeclT:port NetT: DataT:[WIDTH:0] Array: WIDTH:0 Net:sig2 I DeclT:port NetT: DataT:reg [WIDTH:0] Array: WIDTH:0 Cell:sub is-a:v_v2k_sub Module:v_v2k_sub Kwd:module File:verilog/v_v2k.v Pin:net1 Net:netmd[1] Port:net1 Dir:in DataT:[3:4] Array: Module:v_v2k_sub Kwd:module File:verilog/v_v2k.v Port:net1 Dir:in DataT:[3:4] Array: Net:net1 O DeclT:port NetT: DataT:[3:4] Array: 3:4 #### Commentary: verilog/v_v2k.v:0006: WIDTH cmt="" verilog/v_v2k.v:0007: clk cmt="" verilog/v_v2k.v:0023: netmd cmt="" verilog/v_v2k.v:0008: rst cmt="" verilog/v_v2k.v:0009: sig1 cmt="" verilog/v_v2k.v:0010: sig2 cmt="" verilog/v_v2k.v:0030: net1 cmt="" Verilog-Perl-3.482/t/01_manifest.t0000755000177100017500000000155014553624300016560 0ustar wsnyderwsnyder#!/usr/bin/perl -w # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package # # Copyright 2007-2024 by Wilson Snyder. This program is free software; # you can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. use strict; use Test; BEGIN { plan tests => 1 } if (!$ENV{VERILATOR_AUTHOR_SITE}) { skip("author only test (harmless)",1); } else { eval { use ExtUtils::Manifest; }; $ExtUtils::Manifest::Quiet = 1; my ($missing, $extra) = ExtUtils::Manifest::fullcheck(); my $bad; foreach my $file (@{$missing}) { next if $file eq "README"; warn "%Warning: MANIFEST listed file not found: $file\n"; $bad = 1; } foreach my $file (@{$extra}) { warn "%Warning: MANIFEST maybe missing: $file\n"; $bad = 1; } ok (!$bad); } Verilog-Perl-3.482/t/50_vrename.t0000755000177100017500000000266214553624300016420 0ustar wsnyderwsnyder#!/usr/bin/perl -w # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package # # Copyright 2000-2024 by Wilson Snyder. This program is free software; # you can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. use strict; use Test::More; BEGIN { plan tests => 6 } BEGIN { require "./t/test_utils.pl"; } print "Checking vrename...\n"; { # -List my $changefile = "test_dir/signals.vrename"; unlink $changefile; my $cmd = "${PERL} ./vrename -changefile=$changefile -list -xref verilog/test.v"; run_system ($cmd); ok(1, "vrename list"); ok(files_identical($changefile, "t/50_vrename.out"), "diff"); unlink $changefile; } { # Try renaming mkdir 'test_dir/verilog', 0777; my $cmd = ("${PERL} ./vrename -change --changefile verilog/test.vrename" ." -o test_dir verilog/test.v"); run_system ($cmd); ok(1, "vrename change"); ok(-r 'test_dir/verilog/test.v', "diff"); } { # Crypt my $changefile = "test_dir/signals.vrename"; my $cmd = ("${PERL} ./vrename -changefile=$changefile -list --crypt" ." -o test_dir verilog/test.v"); run_system ($cmd); $cmd = ("${PERL} ./vrename -changefile=$changefile -change --crypt" ." -o test_dir verilog/test.v"); run_system ($cmd); ok(1, "vrename crypt"); ok(-r 'test_dir/verilog/test.v', "output exists"); } Verilog-Perl-3.482/t/51_vrename_kwd_chg.out0000644000177100017500000000203213462302176020441 0ustar wsnyderwsnyder// DESCRIPTION: Verilog-Perl: Example Verilog for testing package // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2010-2012 by Wilson Snyder. module 51_vrename_kwd; // Keyword wire \do ; wire \do ; // Non escapes wire non_2non; wire non_2non_nospace ; wire non_2ext; wire non_2ext_nospace ; wire non_2esc; wire non_2esc_nospace ; // Extra unnecessary escapes // Note we cannot legally remove spaces if replacing with non-escaped name wire \ext_2non ; wire \ext_2non_nospace ; wire \ext_2ext ; wire \ext_2ext_nospace ; wire \ext_2esc ; wire \ext_2esc_nospace ; // Necessary escapes wire \esc[ape]_2non ; wire \esc[ape]_2non_nospace ; wire \esc[ape]_2ext ; wire \esc[ape]_2ext_nospace ; wire \esc[ape]_2esc ; wire \esc[ape]_2esc_nospace ; // Strings initial $display("foo"); initial $display("foo.foo"); initial $display("baz_foo"); initial $display("foo_baz"); endmodule Verilog-Perl-3.482/t/80_vppreproc_rel_file.out0000644000177100017500000000264613741600371021212 0ustar wsnyderwsnyder`line 1 "verilog/t_80_foo.v" 1 // DESCRIPTION: Verilog::Preproc: Example source code // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012-2012 by Wilson Snyder. // // Test -F option in vppreproc. // This is the top level module. module foo(output wire y, input wire x); bar i_bar(y, x); endmodule // foo `line 12 "verilog/t_80_foo.v" 2 `line 1 "verilog/t_80_bar/bar.v" 1 // DESCRIPTION: Verilog::Preproc: Example source code // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012-2012 by Wilson Snyder. // // Test -F option in vppreproc. module bar(output wire y, input wire x); assign y = x; endmodule // bar `line 11 "verilog/t_80_bar/bar.v" 2 `line 1 "verilog/inc2.v" 1 // DESCRIPTION: Verilog::Preproc: Example source code // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2000-2012 by Wilson Snyder. At file "verilog/inc2.v" line 4 `line 5 "verilog/inc2.v" 0 `line 1 "verilog/t_preproc_inc3.vh" 1 `line 2 "inc3_a_filename_from_line_directive" 0 // DESCRIPTION: Verilog::Preproc: Example source code // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2000-2012 by Wilson Snyder. // FOO At file "inc3_a_filename_from_line_directive" line 10 // guard `line 19 "inc3_a_filename_from_line_directive" 2 `line 5 "verilog/inc2.v" 0 `line 7 "verilog/inc2.v" 2 Verilog-Perl-3.482/t/80_vppreproc.t0000755000177100017500000000251314553624300017001 0ustar wsnyderwsnyder#!/usr/bin/perl -w # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package # # Copyright 2000-2024 by Wilson Snyder. This program is free software; # you can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. use IO::File; use strict; use Test::More; BEGIN { plan tests => 15 } BEGIN { require "./t/test_utils.pl"; } print "Checking vppreproc...\n"; vppreproc ("t/80_vppreproc_none.out", "test_dir/vppreproc_none.v", ""); vppreproc ("t/80_vppreproc_cmped.out", "test_dir/vppreproc_cmped.v", "--nocomment --pedantic"); vppreproc ("t/80_vppreproc_simple.out", "test_dir/vppreproc_simple.v", "--simple"); vppreproc ("t/80_vppreproc_defines.out", "test_dir/vppreproc_defines.v", "--dump-defines"); vppreproc ("t/80_vppreproc_rel_file.out", "test_dir/vppreproc_rel_file.v", "-f verilog/t_80_foo.f"); sub vppreproc { my $checkname = shift; my $out = shift; my $flags = shift; my $cmd = "${PERL} ./vppreproc ${flags} -y verilog inc2.v > $out"; if (0 == run_system_no_die ($cmd)) { pass("run command"); ok(-r $out, "vppreproc output from: $cmd"); ok(files_identical ($out, $checkname), "diff"); } else { fail ("run command"); fail ("no output file created"); fail ("no output file to compare"); } } Verilog-Perl-3.482/t/85_vhier_cells.out0000644000177100017500000000012413741600304017616 0ustar wsnyderwsnyder v_hier_top v_recursive v_hier_sub v_hier_subsub v_hier_subsub Verilog-Perl-3.482/t/85_vhier.t0000755000177100017500000000337314553624300016110 0ustar wsnyderwsnyder#!/usr/bin/perl -w # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package # # Copyright 2000-2024 by Wilson Snyder. This program is free software; # you can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. use IO::File; use strict; use Test::More; BEGIN { plan tests => 19 } BEGIN { require "./t/test_utils.pl"; } print "Checking vhier...\n"; vhier ("t/85_vhier_cells.out", "--cells"); vhier ("t/85_vhier_includes.out", "--includes"); vhier ("t/85_vhier_inpfiles.out", "--input-files"); vhier ("t/85_vhier_resolvefiles.out","--resolve-files"); vhier ("t/85_vhier_modfiles.out", "--module-files --language 2001"); vhier ("t/85_vhier_topmodule.out", "--module-files --top-module v_hier_sub"); vhier ("t/85_vhier_forest.out", "--forest --instance"); vhier ("t/85_vhier_skiplist.out", "--forest --instance --skiplist t/85_vhier_skiplist.dat"); vhier ("t/85_vhier_xml.out", "--xml --cells --includes --input-files --module-files --missing-modules"); check_valid_xml("test_dir/vhier.out"); sub vhier { my $checkname = shift; my $flags = shift; my $out = "test_dir/vhier.out"; my $cmd = "${PERL} ./vhier ${flags} --nomissing -y verilog v_hier_top.v -o $out"; run_system ($cmd); ok(-r $out, "vhier outputted from: $cmd"); #run_system ("/bin/cp $out $checkname"); ok(files_identical ($out, $checkname), "vhier file compare"); } sub check_valid_xml { my $filename = shift; SKIP: { if ((eval("use XML::Simple; 1;")||0) == 1) { my $xs = new XML::Simple('ForceArray' => [qw(entry)],); ok ($xs->XMLin($filename), "Validate XML"); } else { skip("author only XML test (harmless)",1); } } } Verilog-Perl-3.482/vsplitmodule0000755000177100017500000000641113422450702016472 0ustar wsnyderwsnyder#!/usr/bin/perl -w # See copyright, etc in below POD section. ###################################################################### use lib 'blib/lib'; use Verilog::EditFiles; use FindBin qw($RealBin $RealScript $Script); use strict; #====================================================================== # When editing, delete this section up to the next #==== die <new (# Verilog::EditFiles will use the below program name in its comments program => $Script, # Name of the directory to write the output modules to. # I like to put all generated files under a dir named "gen" # so it is obvious the files are generated. # (But for the Verilog-Perl internal tests, this needs to be test_dir) outdir => "test_dir", #"gen", # If true, add "`celldefine" before every module statement. #celldefine => 1, # For the write_lint method, the name of the linter to use. #lint_command => 'vlint --brief', # If defined, add the provided text before every module statement. # Generally used to insert lint off pragmas. #lint_header => "// lint_checking MY_RULES OFF\n", # If defined, add the provided text before every module statement. # Generally used to insert lint off pragmas. #include_header => "`include \"my_defines.v\"\n", # If defined, add the provided text before every module statement. # Generally used to insert lint off pragmas. #timescale_header => "`include \"my_timescale.v\"\n", # If set, remove any `timescales. #timescale_removal => 1, # If 1, replace any synopsys translate on/offs with "`ifdef SYNTHESIS" and # "`endif"s. If set to a string, use that string instead of "SYNTHESIS". translate_synthesis => 'SYNTHESIS', # The suffix to add to convert a module name into a filename. Defaults to #v_suffix => '.v', # If set, show what files are being read and written verbose => 1, ); # Remove all existing files under the output. You might not want to do # this if there are files you want to keep from there unlink(glob("$split->{outdir}/*.v")); # Read specified libraries and split them $split->read_and_split(glob("t/*.v")); # And write them out $split->write_files(); # And create a lint file $split->write_lint(); # If a file needs 'manual' search and replaces, we can do that too. $split->edit_file (# The filename to be edited filename=>"$split->{outdir}/a.v", # Callback subroutine that takes file contents as a string # and returns the new file contents cb=>sub { my $wholefile = shift; # Globally search and comment out any lines with "pulldown PULLDOWN" # See "man perlre" for examples. # The %mg here means to match multiple lines (you can put # \n in the regexp), and to do it globally $wholefile =~ s%(pulldown PULLDOWN;)%//vsplitmodule: $1%mg; return $wholefile; }); Verilog-Perl-3.482/Makefile.PL0000755000177100017500000001251214553624300015774 0ustar wsnyderwsnyder# DESCRIPTION: Perl ExtUtils: Type 'perl Makefile.PL' to create a Makefile for this package # # Copyright 2000-2024 by Wilson Snyder. This program is free software; # you can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. require 5.005; use ExtUtils::MakeMaker; use Carp; use Config; sub MY::postamble { my $out=""; # Note OPTIMIZE is passed from upper makefile, so this code needed there too. # -O2 optimization seems unreasonably slow on nearly every platform. I give up. my $optimize = $Config{optimize}; $optimize =~ s/(^| )-O2( |$)/\1-O\2/g; # pass hardening flags $optimize .= " $ENV{CFLAGS} $ENV{CPPFLAGS}"; $out .= "OPTIMIZE = $optimize\n"; if ($Config{osname} =~ /cygwin/i || $Config{archname} =~ /cygwin/i) { # Cygwin ExtUtils::MakeMaker ignores our LIBS declaration and says # "No library found for -lstdc++". Force it. $out .= "LDLOADLIBS += -lstdc++\n"; # Cygwin: High optimization causes g++ "out of memory" $out .= "OPTIMIZE += -O\n"; } if ($Config{osname} =~ /darwin/i || $Config{archname} =~ /darwin/i) { # MakeMaker wants to create bundles on MacOSX rather than dylibs. We override DLEXT and LDDLFLAGS generated by MakeMaker in this case $out .= "DLEXT = dylib\n"; if ($^V eq '5.16.2') { $out .= sprintf("LDDLFLAGS = -dynamiclib -lstdc++ -L/System/Library/Perl/5.16.2/%s/CORE -lperl -L/usr/local/lib\n",$Config{archname}); } elsif ($^V eq '5.12.4') { $out .= sprintf("LDDLFLAGS = -dynamiclib -lstdc++ -L/System/Library/Perl/5.12/%s/CORE -lperl -L/usr/local/lib\n",$Config{archname}); } elsif ($^V eq '5.18.2') { $out .= sprintf("LDDLFLAGS = -dynamiclib -lstdc++ -L/System/Library/Perl/5.18/%s/CORE -lperl -L/usr/local/lib\n",$Config{archname}); } elsif ($^V < 'v5.26.3') { $out .= sprintf("LDDLFLAGS = -dynamiclib -lstdc++ -L/System/Library/Perl/%vd/%s/CORE -lperl -lgcc_eh -L/usr/local/lib\n",$^V,$Config{archname}); } } $out .= "CCFLAGS += -Wall -Wno-unused -Wno-sign-compare -Werror\n" if $ENV{VERILATOR_AUTHOR_SITE}; $out .= "CCFLAGS += $ENV{VERILOGPERL_CCFLAGS}\n" if defined $ENV{VERILOGPERL_CCFLAGS}; $out .= "OPTIMIZE += -Wno-unused\n" if $ENV{VERILATOR_AUTHOR_SITE}; # Makefile has another -Wall #$out .= "OPTIMIZE += -O0 -ggdb\n" if $ENV{VERILATOR_AUTHOR_SITE}; print "%Warning: -O0 --gdb on, also FLEX -d on\n"; $out .= "OPTIMIZE += $ENV{VERILOGPERL_CCFLAGS}\n" if defined $ENV{VERILOGPERL_CCFLAGS}; $out .= ' all:: README README: README.pod -$(RM_RF) $@ pod2text --loose $< > $@ clean:: -$(RM_RF) simv .vpassert test_dir *.tmp dist: maintainer-copy distcheck README ## Maintainer use: preexist: svnorcvs nexists $(DISTNAME)_$(VERSION_SYM) test -s README tag: svnorcvs tag $(DISTNAME)_$(VERSION_SYM) maintainer-diff: svnorcvs diff $(DISTNAME)_$(VERSION_SYM) maintainer-dist: preexist dist tag svnorcvs release $(DISTVNAME).tar.gz maintainer-copy: maintainer-clean:: distclean -$(RM_RF) README Makefile MANIFEST.bak $(MAKEFILE_OLD) */gen ## cppcheck CPPCHECK = cppcheck CPPCHECK_FLAGS = --enable=all --inline-suppr CPPCHECK_CPP = $(wildcard */*.cpp) CPPCHECK_DEP = $(subst .cpp,.cppcheck,$(CPPCHECK_CPP)) cppcheck: $(CPPCHECK_DEP) %.cppcheck: %.cpp $(CPPCHECK) $(CPPCHECK_FLAGS) $< '; return $out; } my $fail; local $! = undef; my $have_gen = -d "Preproc/gen"; `flex --version`; if ($?) { if ($have_gen) { warn "\n-Note: 'flex' must be installed to build from sources\n"; } else { $fail=1; warn "\n%Error: 'flex' must be installed to build\n\n"; } } `bison --version`; if ($?) { if ($have_gen) { warn "\n-Note: 'bison' must be installed to build from sources\n"; } else { $fail=1; warn "\n%Error: 'bison' must be installed to build\n\n"; } } `g++ --version`; if ($?) { $fail=1; warn "\n%Error: 'gcc/g++' must be installed to build\n"; } if ($fail) { if ($ENV{AUTOMATED_TESTING}) { exit(0); } else { die "%Error: Exiting due to above missing dependencies.\n"; } } if (!-r "README" && !-r "Makefile") { warn "-Note: If building from 'git' sources (not from a CPAN tar file),\n" ."-Note: ignore any 'files are missing' below for */gen/ and README:\n"; } WriteMakefile( DISTNAME => 'Verilog-Perl', NAME => 'Verilog::Language', AUTHOR => 'Wilson Snyder ', ABSTRACT => 'Verilog language utilities and parsing', VERSION_FROM => 'Language.pm', NO_META => 1, #OPTIMIZE => '-ggdb', PREREQ_PM => { 'Pod::Usage' => 1.34, 'Data::Dumper' => 1, 'warnings' => 1, #---- Below are really BUILD_REQUIRES, but only newer perls understand that 'Digest::SHA' => 0, 'Test' => 1, 'Test::More' => 0, 'Time::HiRes' => 1, #'Test::Pod' => 1, # Required only for author tests #'Test::Perl::Critic' => 1, # Required only for author tests }, PMLIBDIRS => ['lib', 'Parser', 'Preproc', 'Netlist',], EXE_FILES => [qw( vrename vpassert vppreproc vhier vsplitmodule )], 'clean' => {FILES => qw (test_dir signals.vrename .vpassert simv ),}, 'dist' => {COMPRESS => 'gzip -9f', SUFFIX => '.gz', DIST_DEFAULT => 'README all tardist', }, ); my $mkv = `make --version`; if ($? || $mkv !~ /GNU Make/i) { warn "-Important: Now type 'gmake MAKE=gmake' as this package requires GNU Make\n"; } 1; Verilog-Perl-3.482/vhier0000755000177100017500000004110014553624343015064 0ustar wsnyderwsnyder#!/usr/bin/perl -w # See copyright, etc in below POD section. ###################################################################### require 5.005; use FindBin qw($RealBin); use lib "$RealBin/blib/arch"; use lib "$RealBin/blib/lib"; use lib "$RealBin"; use Getopt::Long; use IO::File; use Pod::Usage; use Verilog::Netlist; use Verilog::Getopt; use strict; use vars qw($Debug $VERSION); $VERSION = '3.482'; ###################################################################### # main $Debug = 0; my $opt_output_filename = undef; my @opt_files; autoflush STDOUT 1; autoflush STDERR 1; # Option parsing my $Opt = new Verilog::Getopt(filename_expansion=>1); my $Opt_Cells; my $Opt_Modules; my $Opt_ModFiles; my $Opt_Includes; my $Opt_InFiles; my $Opt_Missing = 1; my $Opt_Missing_Modules; my $Opt_TopModule; my $Opt_ResolveFiles; my $Opt_Synthesis; my $Opt_Instance; my $Opt_Forest; my $opt_skiplist; my @Opt_Skiplist_Names; my $Opt_Xml; Getopt::Long::config("no_auto_abbrev","pass_through"); GetOptions("debug" => \&debug); # Snarf --debug ASAP, before parse -f files @ARGV = $Opt->parameter(@ARGV); Getopt::Long::config("no_auto_abbrev","no_pass_through"); if (! GetOptions ( "help" => \&usage, "debug" => \&debug, "o=s" => \$opt_output_filename, "cells!" => \$Opt_Cells, "module-files!" => \$Opt_ModFiles, "modules!" => \$Opt_Modules, "includes!" => \$Opt_Includes, "input-files!" => \$Opt_InFiles, "resolve-files!" => \$Opt_ResolveFiles, "skiplist=s" => \$opt_skiplist, "sv!" => sub { shift; Verilog::Language::language_standard("1800-2023"); }, "language=s" => sub { shift; Verilog::Language::language_standard(shift); }, "missing!" => \$Opt_Missing, "missing-modules!" => \$Opt_Missing_Modules, "synthesis!" => \$Opt_Synthesis, "top-module=s" => \$Opt_TopModule, "version" => sub { print "Version $VERSION\n"; exit(0); }, "forest" => \$Opt_Forest, "instance" => \$Opt_Instance, "xml!" => \$Opt_Xml, "<>" => \¶meter, )) { die "%Error: Bad usage, try 'vhier --help'\n"; } if (!@opt_files) { die "%Error: vhier: No input filenames specified.\n"; } { my $fh = IO::File->new; if ($opt_output_filename) { $fh->open(">$opt_output_filename") or die "%Error: $! $opt_output_filename\n"; } else { $fh->open(">-") or die; } read_skiplist($opt_skiplist) if $opt_skiplist; vhier($fh, @opt_files); $fh->close; } exit(0); ###################################################################### sub usage { print "Version $VERSION\n"; pod2usage(-verbose=>2, -exitval=>2, -output=>\*STDOUT, -noperldoc=>1); exit(1); } sub debug { $Debug = 1; } sub parameter { my $param = shift; if ($param =~ /^--?/) { die "%Error: vhier: Unknown parameter: $param\n"; } else { push @opt_files, "$param"; # Must quote to convert Getopt to string, bug298 } } ###################################################################### #### Creation sub vhier { my $fh = shift; my @files = @_; my $nl = new Verilog::Netlist(options => $Opt, keep_comments => 0, use_vars => 0, link_read_nonfatal => !$Opt_Missing, synthesis => $Opt_Synthesis, ); $fh->print("\n") if $Opt_Xml; if ($Opt_ResolveFiles) { $nl->read_libraries(); $fh->print(" \n") if $Opt_Xml; foreach my $file (@files) { if (my $resolved = $nl->resolve_filename($file, "all")) { $fh->print( "$resolved\n") if !$Opt_Xml; $fh->print( " $resolved\n") if $Opt_Xml; } } $fh->print(" \n") if $Opt_Xml; return; } foreach my $file (@files) { print " Reading $file\n" if $Debug; $nl->read_file(filename=>$file); } # Read in any sub-modules $nl->link(); $nl->lint(); # Simplified as use_vars => 0 $nl->exit_if_error(); if ($Opt_TopModule) { my $topmod = $nl->find_module($Opt_TopModule) or die "%Error: --top-module '$Opt_TopModule' was not found.\n"; $topmod->is_top(1); # We could just pass this to all of the following routines, # but each would need a different edit. Instead, just edit the netlist # to contain only the specified tree. my %marked_modules; _mod_mark_recurse($nl, $topmod, \%marked_modules); foreach my $mod ($nl->modules_sorted) { if (!$marked_modules{$mod->name}) { $mod->delete; } } } if ($Opt_Cells || $Opt_Forest) { $fh->print(" \n") if $Opt_Xml; foreach my $mod ($nl->modules_sorted) { if ($mod->is_top) { my %recursing; show_hier($fh, \%recursing, $mod, undef, " ", $mod->name); } } $fh->print(" \n") if $Opt_Xml; } if ($Opt_Modules) { show_module_names($nl, $fh); } if ($Opt_ModFiles) { show_mod_files($nl, $fh); } if ($Opt_InFiles) { $fh->print(" \n") if $Opt_Xml; foreach my $filename ($Opt->depend_files) { $fh->print(" $filename\n") if !$Opt_Xml; $fh->print(" $filename\n") if $Opt_Xml; } $fh->print(" \n") if $Opt_Xml; } if ($Opt_Includes) { $fh->print(" \n") if $Opt_Xml; foreach my $filename (sort keys %{$Opt->includes}) { $fh->print(" $filename\n") if !$Opt_Xml; $fh->printf(" \n", $Opt->file_path($filename)) if $Opt_Xml; foreach my $incname (sort keys %{$Opt->{includes}{$filename}}) { $fh->print(" $incname\n") if !$Opt_Xml; $fh->printf(" \n", $Opt->file_path($incname)) if $Opt_Xml; } $fh->print(" \n") if $Opt_Xml; } $fh->print(" \n") if $Opt_Xml; } if ($Opt_Missing_Modules) { show_missing_module_names($nl,$fh); } $fh->print("\n") if $Opt_Xml; } sub show_module_names { my $nl = shift; my $fh = shift; $fh->print(" \n") if $Opt_Xml; foreach my $mod ($nl->modules_sorted) { $fh->printf(" %s\n", $mod->name) if !$Opt_Xml; $fh->printf(" \n", $mod->name) if $Opt_Xml; } $fh->print(" \n") if $Opt_Xml; } sub show_missing_module_names { my $nl = shift; my $fh = shift; my %miss_names; foreach my $mod ($nl->modules) { foreach my $cell ($mod->cells_sorted) { if (!$cell->submod && !$cell->gateprim) { $miss_names{$cell->submodname} = 1; } } } $fh->print(" \n") if $Opt_Xml; foreach my $key (sort (keys %miss_names)) { $fh->printf(" %s\n",$key) if !$Opt_Xml; $fh->printf(" \n",$key) if $Opt_Xml; } $fh->print(" \n") if $Opt_Xml; } sub show_mod_files { my $nl = shift; my $fh = shift; # We'll attach a level attribute to each module indicating its maximum depth foreach my $mod ($nl->modules, $nl->interfaces) { $mod->attributes("_vhier_level", 0); } # Recurse the tree and determine level foreach my $mod ($nl->modules, $nl->interfaces) { if ($mod->is_top) { my %recursing; _mod_files_recurse($mod, 1, \%recursing); } } # Make sort key based on numeric level my %keys; foreach my $mod ($nl->modules) { # No interfaces, it's --module-files implying modules only my $key = sprintf("%03d_%s", $mod->attributes("_vhier_level"), $mod->name); $keys{$key} = $mod; } my @files; my %files; # Uniquify the array foreach my $key (sort {$b cmp $a} (keys %keys)) { my $mod = $keys{$key}; my $filename = $mod->filename; if (!$files{$filename}) { $files{$filename} = 1; push @files, [" "x($mod->attributes("_vhier_level")), $filename]; } } $fh->print(" \n") if $Opt_Xml; foreach my $filespace (reverse @files) { $fh->printf(" %s%s\n",$filespace->[0],$filespace->[1]) if !$Opt_Xml; $fh->printf(" %s%s\n",$filespace->[0],$filespace->[1]) if $Opt_Xml; } $fh->print(" \n") if $Opt_Xml; } sub _mod_mark_recurse { my $nl = shift; my $mod = shift; my $marked = shift; return if $marked->{$mod->name}++; foreach my $cell ($mod->cells_sorted) { if ($cell->submod) { _mod_mark_recurse($nl, $cell->submod, $marked); } } } sub _mod_files_recurse { my $mod = shift; my $level = shift; my $recursing = shift; my $name = $mod->name; return if $recursing->{$name}; ++$recursing->{$name}; if (($mod->attributes("_vhier_level")||0) < $level) { $mod->attributes("_vhier_level", $level); } foreach my $cell ($mod->cells_sorted) { if ($cell->submod) { _mod_files_recurse($cell->submod, $level+1, $recursing); } } --$recursing->{$name}; } sub show_hier { my $fh = shift; my $recursing = shift; my $mod = shift; my $parcell = shift; my $indent = shift; my $hier = shift; my $submodname = shift; # print the design hierarchy starting at mod (recursive) my $name = $mod->name; # check if mod name has match in regex list to skip if (grep { $name =~ $_ } @Opt_Skiplist_Names) { print "Debug: Skipping module $name" if $Debug; return; } return if $recursing->{$name}; ++$recursing->{$name}; printf "%-38s %s\n", $indent."Module ".$name,$hier if $Debug; my $instance = $parcell ? $parcell->name : $name; # print the mod instance $fh->printf("%s\n", $indent, ($parcell ? $parcell->name : $name), $name, $hier, $Opt->file_path($mod->filename)) if $Opt_Xml; $fh->printf("%s%s %s\n", $indent, $instance, $name) if !$Opt_Xml && $Opt_Instance; $fh->printf("%s%s\n", $indent, $name) if !$Opt_Xml && !$Opt_Instance; # print the design hierarchy of each cell in mod my $i = 0; my $suffix; my @cellCount = $mod->cells_sorted; # Returns list of name sorted references to Verilog::Netlist::Cell in the module $fh->printf("\t\t%d cells_sorted for %s\n", $#cellCount+1, $name) if $Debug; my @subMods = grep($_->submod, $mod->cells_sorted); # list of submods of the current mod $fh->printf("\t\t%d submods in cells_sorted.\t", $#subMods+1) if $Debug; $fh->printf("\t\tsubmods=%s\n", join(',',map($_->name, @subMods))) if $Debug; foreach my $cell ($mod->cells_sorted) { if ($cell->submod) { # Reference to the Verilog::Netlist::Module the cell instantiates # true if the cell refers to a defined module # set the suffix characters used to indent lower level of hierarchy if ($Opt_Forest) { if ($i < $#subMods) { $suffix = "|--"; # indent chars for not last cell in the module } else { $suffix = "\\--"; # tweak indent chars for last cell in the module } $indent =~ tr/-\\/ /; # clear out higher-level indent chars } else { $suffix = " "; # simple indenting with spaces } show_hier($fh, $recursing, $cell->submod, $cell, $indent.$suffix, $hier.".".$cell->name); $i++; } } $fh->printf("%s\n", $indent) if $Opt_Xml; --$recursing->{$name}; } sub read_skiplist { my $filename = shift; my $fh = IO::File->new("<$filename") or die "%Error: $! $filename,"; while (<$fh>) { chomp; push @Opt_Skiplist_Names, $_; } $fh->close; if ($Debug) { print "Debug: skiplist:\n"; foreach (@Opt_Skiplist_Names) { print "\t$_\n"; } } } ###################################################################### ###################################################################### ###################################################################### __END__ =pod =head1 NAME vhier - Return all files in a verilog hierarchy using Verilog::Netlist =head1 SYNOPSIS vhier --help vhier [verilog_options] [-o filename] [verilog_files.v...] =head1 DESCRIPTION Vhier reads the Verilog files passed on the command line and outputs a tree of all of the filenames, modules, and cells referenced by that file. =head1 VERILOG ARGUMENTS The following arguments are compatible with GCC, VCS and most Verilog programs. =over 4 =item +define+I+I =item -DI=I Defines the given preprocessor symbol. =item -F I Read the specified file, and act as if all text inside it was specified as command line parameters. Any relative paths are relative to the directory containing the specified file. =item -f I Read the specified file, and act as if all text inside it was specified as command line parameters. Any relative paths are relative to the current directory. =item +incdir+I =item -II Add the directory to the list of directories that should be searched for include directories or libraries. =item +libext+I+I... Specify the extensions that should be used for finding modules. If for example module I is referenced, look in I.I. =item -sv Specifies SystemVerilog language features should be enabled; equivalent to "--language 1800-2023". This option is selected by default, it exists for compatibility with other simulators. =item -y I Add the directory to the list of directories that should be searched for include directories or libraries. =back =head1 VHIER ARGUMENTS =over 4 =item --help Displays this message and program version and exits. =item --o I Use the given filename for output instead of stdout. =item --cells Show the module name of all cells in top-down order. =item --forest Show "ASCII-art" hierarchy tree of all cells (like ps --forest) =item --input-files Show all input filenames. Copying all of these files should result in only those files needed to represent the entire design. =item --includes Show each source filename that includes another filename. The included filename will be as specified in the original source filename, so it may be necessary to resolve it into an absolute path for further processing. =item --instance With --cells or --forest, show module instance names. =item --language <1364-1995|1364-2001|1364-2005|1800-2005|1800-2009|1800-2012|1800-2017|1800-2023> Set the language standard for the files. This determines which tokens are signals versus keywords, such as the ever-common "do" (data-out signal, versus a do-while loop keyword). =item --resolve-files Show resolved filenames passed on the command line. This will convert raw module and filenames without paths to include the library search path directory. Output filenames will be in the same order as passed on the command line. Unlike --input-files or --module-files, hierarchy is not traversed. =item --module-files Show all module filenames in top-down order. Child modules will always appear as low as possible, so that reversing the list will allow bottom-up processing of modules. Unlike input-files, header files are not included. =item --modules Show all module names. =item --no-missing Do not complain about references to missing modules. =item --missing-modules With --nomissing, show all modules that are not found. =item --skiplist I Given file contains a list of regular expressions, one per line. If a module name in the design hierarchy matches one of these expressions, skip showing that module and any sub-hierarchy. =item --synthesis Define SYNTHESIS, and ignore text between "ambit", "pragma", "synopsys" or "synthesis" translate_off and translate_on meta comments. Note using metacomments is discouraged as they have led to silicon bugs (versus ifdef SYNTHESIS); see L. =item --top-module I Start the report at the specified module name, ignoring all modules that are not the one specified with --top-module or below, and report an error if the --top-module specified does not exist. Without this option vhier will report all modules, starting at the module(s) that have no children below them. Note this option will not change the result of the --input-files list, as the files needed to parse any design are independent of which modules are used. =item --version Displays program version and exits. =item --xml Create output in XML format. =back =head1 DISTRIBUTION Verilog-Perl is part of the L free Verilog EDA software tool suite. The latest version is available from CPAN and from L. Copyright 2005-2024 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. =head1 AUTHORS Wilson Snyder =head1 SEE ALSO L, L, L, L =cut ###################################################################### Verilog-Perl-3.482/MANIFEST0000644000177100017500000000700214035374034015147 0ustar wsnyderwsnyder.clang-format .gitignore Changes COPYING EditFiles.pm Getopt.pm Language.pm Makefile.PL MANIFEST This list of files MANIFEST.SKIP META.yml Netlist.pm Netlist/Cell.pm Netlist/ContAssign.pm Netlist/Defparam.pm Netlist/File.pm Netlist/Interface.pm Netlist/Logger.pm Netlist/ModPort.pm Netlist/Module.pm Netlist/Net.pm Netlist/Pin.pm Netlist/PinSelection.pm Netlist/Port.pm Netlist/Subclass.pm Parser/.gitignore Parser/bisonpre Parser/callbackgen Parser/gen/bisonpre-0 Parser/gen/bisonpre-1 Parser/gen/bisonpre-2 Parser/gen/bisonpre-s Parser/gen/flex-0 Parser/gen/flex-1 Parser/Makefile.PL Parser/Parser.pm Parser/Parser.xs Parser/SigParser.pm Parser/typemap Parser/VAst.cpp Parser/VAst.h Parser/VParse.cpp Parser/VParse.h Parser/VParseBison.y Parser/VParseGrammar.h Parser/VParseLex.h Parser/VParseLex.l Parser/VSymTable.cpp Parser/VSymTable.h Preproc/.gitignore Preproc/flexfix Preproc/gen/flex-0 Preproc/gen/flex-1 Preproc/Makefile.PL Preproc/Preproc.pm Preproc/Preproc.xs Preproc/toolhash Preproc/typemap Preproc/VFileLine.cpp Preproc/VFileLine.h Preproc/VPreLex.h Preproc/VPreLex.l Preproc/VPreProc.cpp Preproc/VPreProc.h Preproc/xsubppfix README README.pod Std.pm t/00_pod.t t/01_manifest.t t/02_help.t t/03_spaces.t t/04_critic.t t/05_yaml.t t/10_keywords.t t/12_splitbus.t t/14_numbers.t t/16_std.t t/20_getopt.opt t/20_getopt.t t/30_preproc.out t/30_preproc.t t/30_preproc_nows.out t/30_preproc_on.out t/30_preproc_sub.out t/30_preproc_syn.out t/32_noinc.t t/32_noinc.v t/33_gzip.t t/34_parser.out t/34_parser.t t/35_sigparser.out t/35_sigparser.t t/35_sigparser_ps.out t/36_sigmany.t t/40_netlist.t t/41_example.out t/41_example.t t/42_dumpcheck.t t/42_dumpcheck_1.out t/42_dumpcheck_1_ps.out t/42_dumpcheck_1v.out t/42_dumpcheck_1v_ps.out t/42_dumpcheck_2.out t/42_dumpcheck_2e.out t/42_dumpcheck_2v.out t/42_dumpcheck_sv.out t/42_dumpcheck_v2k.out t/42_dumpcheck_v2kv.out t/43_storable.t t/44_create.out t/44_create.t t/46_link.t t/48_leak.t t/49_largeish.t t/50_vrename.out t/50_vrename.t t/51_vrename_kwd.t t/51_vrename_kwd.v t/51_vrename_kwd_chg.out t/51_vrename_kwd_chg2.out t/51_vrename_kwd_chg2.vrename t/51_vrename_kwd_list.out t/56_editfiles.t t/56_editfiles.v t/56_editfiles_a.out t/56_editfiles_b.out t/56_editfiles_edit.out t/58_vsplitmodule.t t/60_vpassert.out t/60_vpassert.t t/80_vppreproc.t t/80_vppreproc_cmped.out t/80_vppreproc_defines.out t/80_vppreproc_none.out t/80_vppreproc_rel_file.out t/80_vppreproc_simple.out t/85_vhier.t t/85_vhier_cells.out t/85_vhier_forest.out t/85_vhier_includes.out t/85_vhier_inpfiles.out t/85_vhier_modfiles.out t/85_vhier_resolvefiles.out t/85_vhier_skiplist.dat t/85_vhier_skiplist.out t/85_vhier_topmodule.out t/85_vhier_xml.out t/86_vhier_tick.t t/87_vhier_unicode.t t/test_utils.pl verilog/example.v verilog/inc1.v verilog/inc2.v verilog/inc_def09.v verilog/inc_ifdef.v verilog/inc_nonl.v verilog/parser_bugs.v verilog/parser_sv.v verilog/parser_sv09.v verilog/parser_sv17.v verilog/parser_vectors.v verilog/pinorder.v verilog/pli.v verilog/t_80_bar/bar.f verilog/t_80_bar/bar.v verilog/t_80_foo.f verilog/t_80_foo.v verilog/t_86_vhier_tick.v verilog/t_86_vhier_tick_sub.v verilog/t_preproc_inc3.vh verilog/t_preproc_inc4.vh verilog/test.v verilog/test.vrename verilog/v_comments.v verilog/v_gate.v verilog/v_hier_inc.vh verilog/v_hier_noport.v verilog/v_hier_sub.v verilog/v_hier_subprim.v verilog/v_hier_subsub.v verilog/v_hier_top.v verilog/v_hier_top2.v verilog/v_recursive.v verilog/v_sv_intf.v verilog/v_sv_mod.v verilog/v_sv_pgm.v verilog/v_sv_pkg.v verilog/v_v2k.v vhier vpassert vppreproc vrename vsplitmodule Verilog-Perl-3.482/vpassert0000755000177100017500000014413714553624343015634 0ustar wsnyderwsnyder#!/usr/bin/perl -w # See copyright, etc in below POD section. ###################################################################### require 5.005; use FindBin qw($RealBin); use lib "$RealBin/blib/arch"; use lib "$RealBin/blib/lib"; use lib "$RealBin"; use File::Copy; use FindBin qw($RealBin); use Getopt::Long; use IO::Dir; use IO::File; use POSIX qw(); use Pod::Usage; use strict "vars"; use Verilog::Parser; use Verilog::Getopt; use vars qw ($VERSION $Debug $Opt %Vpassert_Conversions $Vpassert_Conversions_Regexp $Opt_Synthcov $Opt_Vericov @Endmodule_Inserts $Last_Parser $Last_Module $Last_Task $ReqAck_Num $Vericov_Enabled $Got_Change @Sendout %Insure_Symbols %Files %Files_Read %File_Dest ); $VERSION = '3.482'; ###################################################################### # configuration # Hash with key of macro to convert and value of the function to call when it occurs # Avoid having a token that is a substring of a standard function, for example # $wr would be bad (beginning of $write). That would slow down the parsing. %Vpassert_Conversions = (## U versions, to avoid conflicts with SystemVerilog '$uassert' => \&ins_uassert, '$uassert_amone' => sub {shift; uassert_hot(0,@_); }, # atmost one hot '$uassert_onehot' => sub {shift; uassert_hot(1,@_); }, '$uassert_req_ack' => \&ins_uassert_req_ack, '$uassert_info' => \&ins_uassert_info, '$ucheck_ilevel' => \&ins_ucheck_ilevel, '$uerror' => \&ins_uerror, #'$ui' => # Used inside ucover_foreach_clk '$uinfo' => \&ins_uinfo, '$uwarn' => \&ins_uwarn, #'$uassert_clk' => sub {shift; my $clk=shift; my $cond=shift; umessage_clk('%%E', $cond,$clk,@_); }, # May be confusing, try without '$uerror_clk' => sub {shift; umessage_clk('%%E', 0, @_); }, '$uwarn_clk' => sub {shift; umessage_clk('%%W', 0, @_); }, '$ucover_clk' => sub {shift; ucover_clk(@_); }, '$ucover_foreach_clk' => sub {shift; ucover_foreach_clk(@_); }, ); ###################################################################### # main $Debug = 0; my $output_dirname = ".vpassert/"; my $Opt_Quiet = 0; # Don't blab about what files are being worked on my $Opt_Axiom; # Athdl my $Opt_AllFiles = 0; # Preprocess all files my $Opt_Call_Error; my $Opt_Call_Info; my $Opt_Call_Warn; my $Opt_Date = 0; # Check dates my $Opt_NoPli = 0; # Delete all pli calls $Opt_Vericov = 0; # Add vericov on/off comments (messes up line # counts) my $Opt_RealIntent; # RealIntent my $Opt_Stop = 1; # Put $stop in error messages my $Opt_Verilator; # Verilator my $Opt_Vcs; # Vcs my $Last_ArgsDiffer; # Last run's Opt_* mismatch my $Opt_Minimum; # Include `__message_minimum my @Opt_Exclude; my $Opt_Timeformat_Units = undef; my $Opt_Timeformat_Precision = 0; my $Opt_Line; my $Total_Files = 0; my @files = (); my @instance_tests_list = (); my $Prog_Mtime = 0; # Time program last changed, so we bag cache on change (-r "$RealBin/vpassert") or die "%Error: Where'd the vpassert source code go?"; $Prog_Mtime = (stat("$RealBin/vpassert"))[9]; autoflush STDOUT 1; Getopt::Long::config("no_auto_abbrev","pass_through"); GetOptions("debug" => \&debug); # Snarf --debug ASAP, before parse -f files $Opt = new Verilog::Getopt(); @ARGV = $Opt->parameter(@ARGV); # Strip -y, +incdir+, etc Getopt::Long::config("no_auto_abbrev","no_pass_through"); if (! GetOptions ( # When add flags, update _switch_line also as appropriate "-o=s" => \$output_dirname, "allfiles!" => \$Opt_AllFiles, "axiom!" => \$Opt_Axiom, "call-error=s" => \$Opt_Call_Error, "call-info=s" => \$Opt_Call_Info, "call-warn=s" => \$Opt_Call_Warn, "date!" => \$Opt_Date, "debug" => \&debug, "exclude=s" => sub {shift; push @Opt_Exclude, shift;}, "help" => \&usage, "language=s" => sub { shift; Verilog::Language::language_standard(shift); }, "line!" => \$Opt_Line, "minimum!" => \$Opt_Minimum, "nopli!" => \$Opt_NoPli, "realintent!" => \$Opt_RealIntent, "quiet!" => \$Opt_Quiet, "stop!" => \$Opt_Stop, "synthcov!" => \$Opt_Synthcov, "timeformat-precision=s" => \$Opt_Timeformat_Precision, "timeformat-units=s" => \$Opt_Timeformat_Units, "vericov!" => \$Opt_Vericov, "verilator!" => \$Opt_Verilator, "version" => sub { print "Version $VERSION\n"; exit(0); }, "vcs!" => \$Opt_Vcs, "<>" => \¶meter, )) { die "%Error: Bad usage, try 'vpassert --help'\n"; } sub _switch_line { # If any of these flags change, we must regenerate output my $sw = ""; $sw .= " --axiom" if $Opt_Axiom; $sw .= " --call-error=$Opt_Call_Error" if $Opt_Call_Error; $sw .= " --call-info=$Opt_Call_Info" if $Opt_Call_Info; $sw .= " --call-warn=$Opt_Call_Warn" if $Opt_Call_Warn; $sw .= " --line" if $Opt_Line; $sw .= " --minimum=$Opt_Minimum" if defined $Opt_Minimum; $sw .= " --nopli" if $Opt_NoPli; $sw .= " --realintent" if $Opt_RealIntent; $sw .= " --stop" if $Opt_Stop; $sw .= " --synthcov" if $Opt_Synthcov; $sw .= " --timeformat-precision=$Opt_Timeformat_Precision" if $Opt_Timeformat_Precision; $sw .= " --timeformat-units=$Opt_Timeformat_Units" if $Opt_Timeformat_Units; $sw .= " --vericov" if $Opt_Vericov; $sw .= " --verilator" if $Opt_Verilator; $sw .= " --vcs" if $Opt_Vcs; return $sw; } if (!defined $Opt_Line) { $Opt_Line = $Opt_Verilator || Verilog::Language::is_compdirect("`line"); # uses language_standard() } push @files, ($Opt->incdir(), $Opt->library(), $Opt->module_dir()); @files = $Opt->remove_duplicates(@files); (@files) or die "%Error: No directories or files specified for processing, try --help\n"; if ($#files >= 0) { (!-f $output_dirname) or die "%Error: $output_dirname already exists as a file, should be a directory.\n"; vpassert_recursive_prelude($output_dirname); file: foreach my $file (@files) { next if $file eq $output_dirname; foreach my $exclude (@Opt_Exclude) { next file if $file =~ /^$exclude/; } vpassert_recursive($file, $output_dirname); } vpassert_recursive_postlude($output_dirname); } print "\tVPASSERT generated $Total_Files new file(s)\n"; exit(0); ###################################################################### sub usage { print "Version $VERSION\n"; print "\nThe following tokens are converted:\n"; foreach my $tok (sort keys %Vpassert_Conversions ) { print "\tToken $tok\n"; } print "\n"; pod2usage(-verbose=>2, -exitval=>2, -output=>\*STDOUT, -noperldoc=>1); exit(1); } sub debug { $Debug = 1; $Verilog::Parser::Debug = 1; $Opt_Quiet = 0; } sub parameter { my $param = shift; (-r $param) or die "%Error: Can't open $param"; push @files, "$param"; # Must quote to convert Getopt to string, bug298 } ###################################################################### ###################################################################### ###################################################################### ###################################################################### ###################################################################### ###################################################################### # Functions that transform the tokens # Note -I is specially detected below sub ins_uinfo { shift; sendout(message(get_lineinfo(), 1, '-I', 1, "", @_)); } sub ins_uwarn { shift; sendout(message(get_lineinfo(), 1, '%%W', 1, "", @_)); } sub ins_uerror { shift; sendout(message(get_lineinfo(), 1, '%%E', 1, "", @_)); } sub ins_uassert { shift; my $cond = shift; my @params = @_; sendout(message(get_lineinfo(), 1, '%%E', $cond, "", 0, @params)); } sub ins_uassert_info { shift; my $cond = shift; my @params = @_; # Lower case -i indicates it's a assert vs. a info sendout(message(get_lineinfo(), 1, "-i", $cond, "", 0, @params)); } sub check_signame { my $sig = shift; return undef if !$sig; return $1 if ($sig =~ /^\s*([a-zA-Z_\$][a-z0-9A-Z_\$]*)\s*$/); return undef; } sub ins_uassert_req_ack { shift; my @params = @_; # Check parameters my $req = check_signame(shift @params); my $ack = check_signame(shift @params); ($req && $ack) or die "%Error: ".$Last_Parser->fileline.": Format of \$uassert_req_ack boggled.\n"; @params = map { my $ipar = $_; $ipar = check_signame($ipar); ($ipar) or die "%Error: ".$Last_Parser->fileline.": Parameter $ipar isn't a signal\n"; $ipar; } @params; # Form new variables $ReqAck_Num or die "%Error: ".$Last_Parser->fileline.": \$uassert_req_ack can't find module statement\n"; my $busy = "_assertreqack${ReqAck_Num}_busy_r"; $Insure_Symbols{$Last_Module}{$busy} = ['reg', 0]; # Make this symbol exist if doesn't # We make a parity across all data signals, as we don't have the width # of the original signal, and I'm too lazy to add code to find it out. my @dholds = (); for (my $n=0; $n<=$#params; $n++) { my $dhold = "_assertreqack${ReqAck_Num}_data${n}_r"; push @dholds, $dhold; $Insure_Symbols{$Last_Module}{$dhold} = ['reg', 0]; } # Output it sendout(message_header()); push @Sendout, [$Last_Parser->lineno, ""]; # Make sure message_header newlines leave us in right place sendout("if (`__message_on) begin "); # Need to wait till after reset, so FSM doesn't start sendout("casez({($busy),($req),($ack)}) "); sendout(" 3'b000: ;"); sendout(" 3'b010: $busy<=1'b1;"); sendout(" 3'b011: "); ins_uerror(0,"\"Unexpected $req coincident with $ack\\n\""); sendout(" 3'b001: "); ins_uerror(0,"\"Unexpected $ack with no request pending\\n\""); sendout(" 3'b100: ;"); sendout(" 3'b11?: "); ins_uerror(0,"\"Unexpected $req with request already pending\\n\""); sendout(" 3'b101: $busy<=1'b0;"); sendout("endcase "); if ($#params>=0) { sendout(" if (($req)||($busy)) begin"); sendout(" if (($busy)) begin"); for (my $n=0; $n<=$#params; $n++) { sendout(" if ($dholds[$n] != ^($params[$n])) "); ins_uerror(0,"\"Unexpected transition of $params[$n] during transaction\\n\""); } sendout(" end"); # Save state of signals for (my $n=0; $n<=$#params; $n++) { sendout(" $dholds[$n] <= ^($params[$n]);"); } sendout(" end "); } sendout(" end "); sendout(message_trailer()); $ReqAck_Num++; } sub ins_ucheck_ilevel { shift; # $ucheck_ilevel my $level = shift; my $chk = "/*vpassert*/if ((`__message_on) && "; $chk .= ' && (`__message_minimum >= (' . $level . '))' if $Opt_Minimum; $chk = $chk . '(__message >= (' . $level . ')))'; sendout($chk); } sub uassert_hot { my $check_nohot = shift; my @params = @_; my $text = ""; my ($elem,$i,$ptemp,$plist,$pnone); my $len = 0; my @cl = (); while ($elem = shift @params){ $elem =~ s/^\s*//; if ($elem =~ /^\"/){ # beginning quote $elem =~ s/\"//g; $text .= $elem; last; }else{ foreach my $subel (split ',', $elem) { $len = $len + bitwidth($subel); } push @cl, $elem; }; } # We use === so that x's will properly cause error messages my $vec = "({".join(",",@cl)."})"; sendout("if (($vec & ($vec - ${len}'b1)) !== ${len}'b0 && `__message_on) "); ins_uerror(0,"\"MULTIPLE ACTIVE %b --> $text\\n\"",$vec); if ($check_nohot==1){ sendout("if ($vec === ${len}'b0 && `__message_on) "); ins_uerror(0,"\"NONE ACTIVE %b --> $text\\n\"",$vec); } } sub umessage_clk { my $char = shift; my $cond = shift; my $clk = shift; my @params = @_; $params[0] = convert_concat_string($params[0]); ($params[0] =~ /^\s*\"/) or die "%Error: ".$Last_Parser->fileline.": Non-string \$message second argument: $params[0]\n"; $ReqAck_Num or die "%Error: ".$Last_Parser->fileline.": \$uassert_req_ack can't find module statement\n"; my $sig = "_umessageclk${ReqAck_Num}"; $Insure_Symbols{$Last_Module}{$sig} = ['reg', 0]; # Make this symbol exist if doesn't $ReqAck_Num++; if ($cond eq '0') { sendout("/*vpassert*/$sig=1'b1;/*vpassert*/"); } else { sendout("/*vpassert*/$sig=!($cond);/*vpassert*/"); } _insert_always_begin('assert', "/*vpassert*/ $sig=1'b0; /*vpassert*/"); my $bot = (" always @ (posedge $clk) if ($sig) " .message(get_lineinfo(), 1, $char, 1, "", @_) ." "); push @Endmodule_Inserts, [0, $bot]; } sub ucover_foreach_clk { my $clk = shift; my $label = shift; my $range = shift; my $expr = shift; $#_==-1 or die "%Error: ".$Last_Parser->fileline.": Extra arguments to \$ucover_foreach_clk: $_[0]\n"; # We require quotes around the label so synthesis tools won't gripe if not wrapping in vpassert # (Otherwise it would look like a system call with a variable of the name of the label.) ($label =~ s/^\s*\"([a-zA-Z][a-zA-Z0-9_]+)\"\s*$/$1/) or die "%Error: ".$Last_Parser->fileline.": Non-string label \$ucover_clk second argument: $label\n"; ($range =~ s/^\s*\"\s*(\d[0-9,:]+)\s*\"\s*$/$1/) or die "%Error: ".$Last_Parser->fileline.": Can't parse msb:lsb in \$ucover_foreach_clk: $range\n"; my @values = _convert_foreach_comma($range); foreach my $i (@values) { my $nexpr = $expr; $nexpr =~ s/\$ui\b/($i)/g or die "%Error: ".$Last_Parser->fileline.": No \$ui in \$ucover_foreach_clk expression: $expr\n"; _ucover_clk_guts($clk, $label."__".$i, "(${nexpr})"); } } sub ucover_clk { my $clk = shift; my $label = shift; $#_==-1 or die "%Error: ".$Last_Parser->fileline.": Extra arguments to \$ucover_clk: $_[0]\n"; # We require quotes around the label so synthesis tools won't gripe if not wrapping in vpassert # (Otherwise it would look like a system call with a variable of the name of the label.) ($label =~ s/^\s*\"([a-zA-Z][a-zA-Z0-9_]+)\"\s*$/$1/) or die "%Error: ".$Last_Parser->fileline.": Non-string label \$ucover_clk second argument: $label\n"; _ucover_clk_guts($clk,$label, "1'b1"); } sub _ucover_clk_guts { my $clk = shift; my $label = shift; my $expr = shift; $ReqAck_Num or die "%Error: ".$Last_Parser->fileline.": \$ucover_clk can't find module statement\n"; my $sig = "_ucoverclk${ReqAck_Num}"; $Insure_Symbols{$Last_Module}{$sig} = ['reg', 0]; # Make this symbol exist if doesn't $ReqAck_Num++; sendout("/*vpassert*/$sig=${expr};/*vpassert*/"); _insert_always_begin('cover', "/*vpassert*/ $sig=1'b0; /*vpassert*/"); # Note correct `line is required to see correct cover point push @Endmodule_Inserts, [$Last_Parser->lineno," $label: cover property (@(posedge $clk) ($sig));\n"]; } sub _insert_always_begin { my $for_assert = shift; my $text = shift; my $beginl; for (my $l = $#Sendout; $l>=0; $l--) { my $tok = $Sendout[$l][1]; #print "HUNT $l: ".($beginl||"").": $tok\n"; # Fortunately all comments must be a single array entry $tok =~ s!//.*?\n!!go; $tok =~ s!/\*.*?\*/$!!go; if ($tok =~ /\bbegin\b/) { $beginl = $l; } if ($tok =~ /\b(if|initial|final)\b/) { $beginl = undef; } if ($tok =~ /\bposedge\b/) { if ($for_assert ne 'cover') { die "%Error: ".$Last_Parser->fileline.": \$uerror_clk is under a posedge clk, use \$uerror instead\n"; } } if ($tok =~ /\balways\b/) { last if !defined $beginl; # And die below my $insert = $text; $Sendout[$beginl][1] =~ s/(\bbegin\b)/$1$insert/; return; } } die "%Error: ".$Last_Parser->fileline.": \$uerror_clk is not somewhere under an 'always begin' block\n"; } sub get_lineinfo { # Align the lineinfo so that right hand sides are aligned my $message_filename = $Last_Parser->filename; $message_filename =~ s/^.*\///g; my $lineinfo = substr($message_filename, 0, 17); # Don't make too long $lineinfo = $lineinfo . sprintf(":%04d:", $Last_Parser->lineno ); $lineinfo = sprintf("%-21s", $lineinfo); } use vars qw($Msg_Header_Level); sub coverage_off { my $subcall = shift; my $out = ""; if (!$Msg_Header_Level) { $out .= "/*summit modcovoff -bpen*/\n" if $Vericov_Enabled; $out .= "/*ri userpass BE on*/\n" if $Opt_RealIntent; $out .= "/*VCS coverage off*/\n" if $Opt_Vcs; $out .= "/*ax_line_coverage_off*/\n" if $Opt_Axiom; $out .= "/*verilator coverage_off*/\n" if $Opt_Verilator && !$subcall; $out = "\n".$out if $out; $out .= "/*vpassert*/"; $Got_Change = 1; } $Msg_Header_Level++; return $out; } sub coverage_on { my $subcall = shift; my $out = ""; if ((--$Msg_Header_Level)==0) { $out .= "/*verilator coverage_on*/\n" if $Opt_Verilator && !$subcall; $out .= "/*VCS coverage on*/\n" if $Opt_Vcs; $out .= "/*ax_line_coverage_on*/\n" if $Opt_Axiom; $out .= "/*ri userpass BE off*/\n" if $Opt_RealIntent; $out .= "/*summit modcovon -bpen*/\n" if $Vericov_Enabled; $out = "\n".$out if $out; $out = '/*vpassert*/'.$out; } return $out; } sub message_header { my $off = coverage_off(1); my $out = $off; $out .= "begin "; $out .= "/*verilator coverage_block_off*/" if ($Opt_Verilator && $off); return $out; } sub message_trailer { my $out = 'end '; $out .= coverage_on(1); return $out; } sub message { my $lineinfo = shift; my $show_id = shift; my $char = shift; my $cond = shift; my $otherargs = shift; my @params = @_; # Level, printf string, args if ($params[0] =~ /^\s*\"/) { # No digit in first parameter # Push new parameter [0] as a 0. unshift @params, '0'; } $params[1] = convert_concat_string($params[1]); unless ($char =~ /^-I/i) { if ($params[1] =~ s/\s*\"\s*$//) { # For a well-formed message, $params[1] now ends in "\\n". $params[1] .= "\\n" if $params[1] !~ /\\n$/; $params[1] = $params[1]."${char}: In %m\\n\""; } } ($params[0] =~ /^\s*[0-9]/) or die "%Error: ".$Last_Parser->fileline.": Non-numeric \$message first argument: $params[0]\n"; ($params[1] =~ /^\s*\"/) or die "%Error: ".$Last_Parser->fileline.": Non-string \$message second argument: $params[1]\n"; my $out = message_header(); # These long lines without breaks are intentional; I want to preserve line numbers my $is_warn = (($char eq '%%E') || ($char eq '%%W') || ($char eq "-i")); if ($cond ne "1") { # Conditional code, for $uassert # Note this will only work in RTL code! $out .= "if (!($cond) && (`__message_on)) "; } elsif ($params[0] =~ /^\s*0\s*$/) { # Always enabled if ($is_warn) { $out .= "if (`__message_on) "; } } else { # Complex test $Insure_Symbols{$Last_Module}{__message} = ['integer',5]; # Make this symbol exist if doesn't my $chk = 'if ((__message >= (' . $params[0] . '))'; $chk .= ' && (`__message_minimum >= (' . $params[0] . '))' if $Opt_Minimum; $chk .= " && (`__message_on) " if $is_warn; $chk .= ') '; $out .= $chk; } my $task; my $call; if (($char eq '-I') || ($char eq '-i')) { if ($Opt_Call_Info) { $call = $Opt_Call_Info; } } elsif ($char eq '%%E') { if ($Opt_Call_Error) { $call = $Opt_Call_Error; } else { $task = ($Opt_Stop ? '$stop;' : "`pli.errors = `pli.errors+1;"); } } elsif ($char eq '%%W') { if ($Opt_Call_Error) { $call = $Opt_Call_Warn; } else { $task = ($Opt_Stop ? '$stop;' : "`pli.warnings = `pli.warnings+1;"); } } else { die "%Error: Unknown message character class '$char'\n"; } { # if's body $out .= "begin"; $out .= " \$timeformat($Opt_Timeformat_Units, $Opt_Timeformat_Precision,\"\",20);" if defined $Opt_Timeformat_Units; $out .= " \$write (\"[%0t] ${char}:${lineinfo} " if !$call; $out .= " ${call} (\"" if $call; my $par = $params[1]; $par =~ s/^\s*\"//; $out .= "$par"; $out .= ",\$time" if !$call; $out .= $otherargs; for my $parn (2 .. $#params) { my $p = $params[$parn]; $out .= ", $p"; print "MESSAGE $char, Parameter $p\n" if ($Debug); } $out .= ');'; $out .= $task if $task; $out .= ' end '; } $out .= message_trailer(); return $out; } ###################################################################### sub _convert_foreach_comma { my $in = shift; # Similar to Verilog::Language::split_bus my @out; $in =~ s/\s+//g; while ($in =~ s!,?(((\d+):(\d+))|(\d+))!!) { if (defined $3 && defined $4) { if ($3<$4) { foreach (my $i=$3; $i<=$4; $i++) { push @out, $i; } } else { foreach (my $i=$3; $i>=$4; $i--) { push @out, $i; } } } elsif (defined $5) { push @out, $5; } } $in eq "" or die "%Error: ".$Last_Parser->fileline.": Strange range expression: $in\n"; return @out; } sub convert_concat_string { my $string = shift; # Convert {"string"} or {"str","in","g"} to just "string" # Beware embedded quotes "\"" return $string if ($string !~ /^\s*\{\s*(\".*)\s*\}\s*$/); my $in = $1; my $out = ""; my $quote; my $slash; for (my $i=0; $ilineno, $string]; $Got_Change = 1; } ###################################################################### ###################################################################### ###################################################################### ###################################################################### sub form_conversions_regexp { # Create $Vpassert_Conversions_Regexp, a regexp that matches any of the conversions # This regexp will allow us to quickly look at the file and ignore it if no matches my $re = ''; my $last_tok = "\$ignore"; foreach my $tok (sort (keys %Vpassert_Conversions)) { ($tok =~ s/^\$//) or die "%Error: Vpassert_Conversion $tok doesn't have leading \$\n"; if (substr ($tok, 0, length($last_tok)) eq $last_tok) { #print "Suppress $tok $last_tok\n" if $Debug; } else { $re .= "|" if $re; $re .= '\$'.$tok; $last_tok = $tok; } } if ($Opt_NoPli) { $re .= "|" if $re; $re .= '\$'; } if ($Opt_Synthcov) { $re .= "|" if $re; $re .= 'SYNTHESIS'; } $re = "(".$re.")"; $re = "\$NEVER_MATCH_ANYTHING" if $re eq '\$()'; #print "CV REGEXP $re\n" if $Debug; $Vpassert_Conversions_Regexp = qr/$re/; } sub vpassert_process { # Read all signals in this filename # Return TRUE if the file changed my $filename = shift; my $outname = shift; $Got_Change = shift; # True if should always write output, not only if have change if ($outname =~ /[\/\\]$/) { # Directory, not file, so append filename my $basename = $filename; $basename =~ s/.*[\/\\]//g; $outname .= $basename; } print "vpassert_process ($filename, $outname, $Got_Change)\n" if ($Debug); ($filename ne $outname) or die "%Error: $filename: Would overwrite self."; @Sendout = (); $Msg_Header_Level = 0; @instance_tests_list = (); # Set up parsing my $parser = new Verilog::Vpassert::Parser; $parser->filename($filename); $parser->lineno(1); $Last_Parser = $parser; # Open file for reading and parse it my $fh = IO::File->new("<$filename") or die "%Error: $! $filename."; if (!$Got_Change) { while (<$fh>) { goto diff if (/$Vpassert_Conversions_Regexp/); } print "$filename: No dollars, not processing\n" if ($Debug); return; diff: $fh->seek(0,0); $. = 1; } while (my $line = $fh->getline() ) { $parser->parse($line); } $parser->eof; push @Sendout, [$Last_Parser->lineno, $parser->unreadback()]; $parser->unreadback(''); $fh->close; # Hack the output text to add in the messages variable foreach my $mod (sort keys %Insure_Symbols) { my $insert=""; my $n=0; # Some compilers choke if lines get too long; foreach my $sym (sort keys %{$Insure_Symbols{$mod}}) { #if ! $module_symbols{$sym} # For now always put it in my $type = $Insure_Symbols{$mod}{$sym}[0]; my $value = $Insure_Symbols{$mod}{$sym}[1]; $insert .= "$type $sym; initial $sym = $value;"; if (++$n > 10) { $insert .= "\n"; $n=0; } } if ($insert) { my $hit; for (my $l = $#Sendout; $l>=0; $l--) { my $tok = $Sendout[$l][1]; if ($tok =~ m%/\*vpassert beginmodule $mod\*/%) { my $lineno = $Sendout[$l][0]; if ($Opt_Line) { $insert .= "\n`line ".$lineno." \"".$Last_Parser->filename."\" 0\n"; } $tok =~ s%/\*vpassert beginmodule $mod\*/%/*vpassert*/$insert%g or die; # Must exist, found above! $Sendout[$l][1] = $tok; $hit = 1; # Don't exit the loop, keep looking for more. # It's possible there's a `ifdef with multiple "module x" headers } } $hit or die "vpassert %Error: $filename: Couldn't find symbol insertion point in $mod\n"; } } $#Endmodule_Inserts < 0 or die "vpassert %Error: $filename: Couldn't find endmodule\n"; # Put out the processed file print "Got_Change? $Got_Change $outname\n" if ($Debug); if ($Got_Change) { my $date = localtime; $fh->open(">$outname") or die "%Error: Can't write $outname."; my $curline = -1; my $needline = 1; # No newline so line counts not affected print $fh "/* Generated by vpassert; File:\"$filename\" */"; my @out; foreach my $outref (@Sendout) { #print "CL $curline WL $outref->[0] TT $outref->[1]\n"; if ($outref->[0]) { $needline = $outref->[0]; } if ($curline != $needline) { push @out, "\n`line $needline \"$filename\" 0\n" if $Opt_Line; $curline = $needline; } push @out, $outref->[1]; $curline++ while ($outref->[1] =~ /\n/g); } my $out = join('',@out); # Simplify redundant `lines to save space $out =~ s%(\`line[^\n]*)\n[ \t\n]*(\`line[^\n]*\n)%$2%mg; $out =~ s%\n+(\n\`line[^\n]*)%$1%mg; print $fh $out; $fh->close; if (defined $Files{$filename}{mtime}) { utime $Files{$filename}{mtime}, $Files{$filename}{mtime}, $outname; } } return $Got_Change; } #---------------------------------------------------------------------- sub bitwidth { # Take a string like "{foo[5:0],bar} and return bit width (7 in this case) my $statement = shift; my $bits = 0; foreach my $sig (split /,\{\]/, $statement) { if ($sig =~ /[a-z].* \[ (-?[0-9]+) : (-?[0-9]+) \]/x) { $bits += ($1 - $2) + 1; } elsif ($sig =~ /[a-z]/) { $bits ++; } } return $bits; } #---------------------------------------------------------------------- #---------------------------------------------------------------------- #---------------------------------------------------------------------- sub vpassert_db_read_file { # Read when the unprocessed files were last known to not need processing my $filename = shift; my $fh = IO::File->new("<$filename") or return; # no error if fails while (my $line = $fh->getline) { chomp $line; if ($line =~ /^switch\s*(.*$)/) { my $old = $1; my $now = _switch_line(); $old =~ s/\s+//g; $now =~ s/\s+//g; $Last_ArgsDiffer = ($old ne $now); } else { my ($tt_cmd, $tt_file, $tt_mtime, $tt_size) = split(/\t/,$line); $tt_cmd .= ""; # Warning removal $Files_Read{$tt_file}{mtime} = $tt_mtime; $Files_Read{$tt_file}{size} = $tt_size; } } $fh->close; } sub vpassert_db_write_file { # Save which unprocessed files did not need processing my $filename = shift; my $fh = IO::File->new(">$filename") or die "%Error: $! $filename.\n"; $fh->print("switch\t"._switch_line()."\n"); foreach my $file (sort (keys %Files)) { next if !$Files{$file}{mtime}; $fh->print("unproc\t$file\t$Files{$file}{mtime}\t$Files{$file}{size}\n"); } $fh->close; } #---------------------------------------------------------------------- sub vpassert_recursive_prelude { # What to do before processing any files my $destdir = shift; $destdir .= "/" if ($destdir !~ /[\\\/]$/); %Files = (); %Files_Read = (); vpassert_db_read_file("${destdir}/.vpassert_skipped_times"); form_conversions_regexp(); if (! -d $destdir) { mkdir($destdir,0777) or die "%Error: Can't mkdir $destdir\n"; } # Don't include directory in time saving, as path may change dep how run my $dest_mtime = $Files_Read{"vpassert"}{mtime} || 0; if (!$Opt_Date || ($Prog_Mtime > $dest_mtime) || $Last_ArgsDiffer) { # Flush the whole read cache %Files_Read = (); print "\t VPASSERT (or overall flags) changed... Two minutes...\n"; print "\t Mtime = $Prog_Mtime\n" if $Debug; } #print "FF $Opt_Date, $Prog_Mtime, $dest_mtime, $Opt_Vericov, $Last_Vericov\n"; $Files{"vpassert"}{mtime} = $Prog_Mtime; $Files{"vpassert"}{size} = 1; } sub vpassert_recursive_postlude { my $destdir = shift; $destdir .= "/" if ($destdir !~ /[\\\/]$/); # What to do after processing all files # Check for deletions foreach my $srcfile (sort keys %Files_Read) { if ($Files_Read{$srcfile}{mtime} && !$Files{$srcfile}{mtime}) { (my $basefile = $srcfile) =~ s/.*\///; my $destfile = "$destdir$basefile"; # A file with the same basename may now be in a different dir, # and already processed, so don't delete it. if (!$File_Dest{$destfile}) { print "\t vpassert: Deleted? $srcfile\n" if !$Opt_Quiet; unlink $destfile; } } } vpassert_db_write_file("${destdir}/.vpassert_skipped_times"); } sub vpassert_recursive { # Recursively process this directory or file argument my $srcdir = shift; my $destdir = shift; print "Recursing $srcdir $destdir\n" if ($Debug); if (-d $srcdir) { $srcdir .= "/" if ($srcdir !~ /[\\\/]$/); $destdir .= "/" if ($destdir !~ /[\\\/]$/); my $dh = new IO::Dir $srcdir or die "%Error: Could not directory $srcdir.\n"; while (defined (my $basefile = $dh->read)) { my $srcfile = $srcdir . $basefile; if ($Opt->libext_matches($srcfile)) { next if -d $srcfile; vpassert_process_one($srcfile, $destdir); } } $dh->close(); } else { # Plain file vpassert_process_one($srcdir, $destdir, 1); } } use vars (qw(%file_directory)); sub vpassert_process_one { # Process one file, keeping cache consistent my $srcfile = shift; my $destdir = shift; (my $basefile = $srcfile) =~ s!.*[/\\]!!; my $destfile = "$destdir$basefile"; $File_Dest{$destfile} = 1; my @stat = (stat($srcfile)); my $src_mtime = $stat[9] || 0; my $src_size = $stat[7] || 0; my $dest_mtime = $Files_Read{$srcfile}{mtime} || 0; # Mark times #print "BCK $basefile $src_mtime, $dest_mtime\n"; $Files{$srcfile}{mtime} = $src_mtime; $Files{$srcfile}{size} = $src_size; if ($src_mtime != $dest_mtime || $src_size != $Files_Read{$srcfile}{size}) { my $no_output = 0; unlink $destfile; $Total_Files++; if (! vpassert_process ($srcfile, $destfile, $Opt_AllFiles)) { # Didn't need to do processing $no_output = 1; print "nooutput: vpassert_process ($srcfile, $destfile,0 )\n" if ($Debug); nochange_copy($srcfile,$destfile); } else { # Make sure didn't clobber another directory's file print "madenew: vpassert_process ($srcfile, $destfile,0 )\n" if ($Debug); if ($file_directory{$destfile}) { my $old = $file_directory{$destfile}; die "%Error: Two files with same basename: $srcfile, $old\n"; # This warning is to prevent search order dependence in the # verilog search path. It also makes sure we don't clobber # one file with another by the same name in the .vpassert directory } } if (!$Opt_Quiet) { print " VPASSERT'ing file ($Total_Files) $srcfile ", ($dest_mtime ? "(Changed)":"(New)"), ($no_output ? " (no-output)" : ""),"\n"; } } $file_directory{$destfile} = $srcfile; } sub nochange_copy { my $srcfile = shift; my $dstfile = shift; my $fhw = IO::File->new(">$dstfile"); my $fhr = IO::File->new("<$srcfile"); if (!$fhr) { warn "%Warning: $! $srcfile\n"; return; } $fhw->print("`line 1 \"$srcfile\" 0\n") if $Opt_Line; # Unfortunately File::Copy::copy overwrites our line statement. my $eof; my $chunk = POSIX::BUFSIZ; # On 5.8.8 this isn't a number but text $chunk = 8*1024 if $chunk !~ /^\d+$/; while (!$eof) { my $data = ''; $!=undef; my $rv = $fhr->sysread($data, $chunk, 0); #print "RRV=$rv b=$!\n" if $Debug; $eof = 1 if !$rv || (!$fhr || ($! && $! != POSIX::EWOULDBLOCK)); $fhw->print($data); } } ###################################################################### ###################################################################### ###################################################################### ###################################################################### # Parser functions called by Verilog::Parser package Verilog::Vpassert::Parser; ## no critic require Exporter; use Verilog::Parser; use base qw(Verilog::Parser); BEGIN { # Symbols to alias to global scope use vars qw(@GLOBALS); @GLOBALS = qw ( $Debug @Sendout $Last_Task $Last_Module $Opt_Vericov $Opt_Synthcov $ReqAck_Num $Vericov_Enabled %Vpassert_Conversions %Insure_Symbols @Endmodule_Inserts ); foreach (@GLOBALS) { my ($type,$sym) = /^(.)(.*)$/; *{"$sym"} = \${"::$sym"} if ($type eq "\$"); *{"$sym"} = \%{"::$sym"} if ($type eq "%"); *{"$sym"} = \@{"::$sym"} if ($type eq "@"); } } use strict; use vars (@GLOBALS, qw ( $Last_Keyword $Last_Lineno $Last_Prekwd @Last_Symbols @Last_Number_Ops $Need_Vpassert_Symbols @Params $Param_Num $Parens $PreLevel @PreCovOff $In_Message )); use Verilog::Parser; sub new { my $class = shift; my $self = $class->SUPER::new(); bless $self, $class; # State of the parser # These could be put under the class, but this is faster and we only parse # one file at a time @Endmodule_Inserts = (); $Last_Keyword = ""; $Last_Lineno = 0; $Last_Prekwd = 0; @Last_Symbols = (); @Last_Number_Ops = (); $Last_Task = ""; $Last_Module = ""; $Vericov_Enabled = $Opt_Vericov; $Need_Vpassert_Symbols = 0; $Param_Num = 0; $Parens = 0; $PreLevel = 0; @PreCovOff = (); $In_Message = 0; #%module_symbols = (); %Insure_Symbols = (); @Params = (); return $self; } sub keyword { # Callback from parser when a keyword occurs my ($parser, $token) = @_; my $since = $parser->unreadback(); $parser->unreadback(''); $Last_Keyword = $token; @Last_Symbols = (); @Last_Number_Ops = (); if ($Opt_Vericov && (($token eq "case") || ($token eq "casex") || ($token eq "casez"))) { push @Sendout, [$Last_Lineno, $since]; push @Sendout, [$Last_Lineno, "\n/*summit implicit off*/\n"] if $Vericov_Enabled; push @Sendout, [$Last_Lineno, $token]; } elsif ($Opt_Vericov && ($token eq "endcase")) { push @Sendout, [$Last_Lineno, $since . $token]; push @Sendout, [$Last_Lineno, "\n/*summit implicit on*/\n"] if $Vericov_Enabled; } elsif ($token eq "endmodule") { if ($#Endmodule_Inserts >= 0) { push @Sendout, @Endmodule_Inserts; @Endmodule_Inserts = (); } push @Sendout, [$Last_Lineno, $since . $token]; } else { push @Sendout, [$Last_Lineno, $since . $token]; } $Last_Lineno = $parser->lineno; } sub symbol { # Callback from parser when a symbol occurs my ($parser, $token) = @_; my $since = $parser->unreadback(); $parser->unreadback(''); if ($In_Message) { $Params[$Param_Num] .= $since . $token; } else { if ($Vpassert_Conversions {$token} || ($Opt_NoPli && $token =~ /^\$/ && $Parens==0)) { push @Sendout, [$Last_Lineno, $since]; print "Callback SYMBOL $token\n" if ($Debug); $In_Message = 1; $Param_Num = 1; @Params = (); $Params[0] = $token; } else { # Actually a keyword; we check for that too push @Sendout, [$Last_Lineno, $since . $token]; } } if ($Last_Keyword eq "task") { $Last_Task = $token; $Last_Keyword = ""; $Parens = 0; } if ($Last_Keyword eq "module") { $Last_Module = $token; $Last_Keyword = ""; $Need_Vpassert_Symbols = 1; $ReqAck_Num = 1; $Parens = 0; } if ($Last_Prekwd) { if ($Last_Prekwd eq "`ifdef" || $Last_Prekwd eq "`elsif" || $Last_Prekwd eq "`ifndef") { if ($token eq "SYNTHESIS") { my $ndef = ($Last_Prekwd eq "`ifndef"); $PreCovOff[$PreLevel] = $ndef; if ($PreCovOff[$PreLevel] && $Opt_Synthcov) { push @Sendout, [0, ::coverage_off(0)]; } } else { $PreCovOff[$PreLevel] = 0; } } $Last_Prekwd = 0; } push @Last_Symbols, $token; $Last_Lineno = $parser->lineno; } sub number { # Callback from parser when a number occurs my ($parser, $token) = @_; my $since = $parser->unreadback(); $parser->unreadback(''); if ($In_Message) { print "Callback NUMBER $token\n" if ($Debug); $Params[$Param_Num] .= $since . $token; } else { push @Sendout, [$Last_Lineno, $since . $token]; } push @Last_Number_Ops, $token; $Last_Lineno = $parser->lineno; } sub operator { # Callback from parser when a operator occurs my ($parser, $token) = @_; my $since = $parser->unreadback(); $parser->unreadback(''); if ($In_Message) { print "Callback OPERATOR $token ($Parens, $Param_Num)\n" if ($Debug); if (($token eq ',') && ($Parens==1)) { # Top level comma $Params[$Param_Num] .= $since; $Param_Num ++; } elsif (($token eq ';' && ($Parens==0))) { # Final statement close if ($In_Message) { if ($Opt_NoPli) { # "" doesn't work, as need semi for "if (1) $x()" # ";" doesn't work, as need empty for "begin $x() end" ::sendout("begin end "); for (my $p=0; $p<=$#Params; $p++) { while ($Params[$p]=~/\n/g) { ::sendout("\n"); } } } elsif (defined $Vpassert_Conversions {$Params[0]}) { #print " CALLPRE ",join(':',@Params),"\n" if $Debug; my $nl = ""; for (my $p=0; $p<=$#Params; $p++) { while ($Params[$p]=~/\n/g) { $nl .= "\n"; } $Params[$p] = Verilog::Language::strip_comments($Params[$p]); $Params[$p]=~ s/\n//g; } my $func = $Vpassert_Conversions {$Params[0]}; print " CALL ",join(':',@Params),"\n" if $Debug; &$func(@Params); ::sendout($nl) if $nl; # Adjust for \n's in params } else { ::sendout(""); } } $In_Message=0; } elsif (($token eq ')' || $token eq '}') && ($Parens==1)) { # Final paren $Params[$Param_Num] .= $since; } elsif ($token eq ')' || $token eq '}') { # Other paren $Params[$Param_Num] .= $since . $token; } elsif ($token eq '(' || $token eq '{') { if ($Parens!=0) { $Params[$Param_Num] .= $since . $token; } } else { $Params[$Param_Num] .= $since . $token; } } elsif ($Need_Vpassert_Symbols && ($token eq ';')) { $Need_Vpassert_Symbols = 0; # Squeeze it after module (..); push @Sendout, [$Last_Lineno, $since . $token . '/*vpassert beginmodule '.$Last_Module.'*/']; } else { push @Sendout, [$Last_Lineno, $since . $token]; } # Track parens if ($token eq '(' || $token eq '{') { $Parens++; } elsif ($token eq ')' || $token eq '}') { $Parens--; } push @Last_Number_Ops, $token; $Last_Lineno = $parser->lineno; } sub string { # Callback from parser when a string occurs my ($parser, $token) = @_; my $since = $parser->unreadback(); $parser->unreadback(''); if ($In_Message) { print "Callback STRING $token\n" if ($Debug); $Params[$Param_Num] .= $since . $token; } else { push @Sendout, [$Last_Lineno, $since . $token]; if (($Last_Keyword eq "`include") && ($token =~ /\//)) { print STDERR "%Warning: ".$parser->fileline.": `include has directory," . " remove and add +incdir+ to input.vc\n"; } } $Last_Lineno = $parser->lineno; } sub comment { # Callback from parser when a comment # *** To speed things up, this is only invoked when doing vericov my ($parser, $token) = @_; if (!$Opt_Vericov && $token !~ /_coverage_/) { $parser->unreadback($parser->unreadback() . $token); return; } my $since = $parser->unreadback(); $parser->unreadback(''); if ($Opt_Vericov) { if ($token =~ /summit\s+modcovon/ || $token =~ /simtech\s+modcovon/) { $Vericov_Enabled = 1; } elsif ($token =~ /summit\s+modcovoff/ || $token =~ /simtech\s+modcovoff/) { $Vericov_Enabled = 0; } } push @Sendout, [$Last_Lineno, $since . $token]; if ($token =~ /\b(cn|vp)_coverage_(off|on)/) { if ($2 eq 'off') { push @Sendout, [0, ::coverage_off(0)]; } else { push @Sendout, [0, ::coverage_on(0)]; } } $Last_Lineno = $parser->lineno; } sub preproc { my ($self, $token) = @_; if (Verilog::Language::is_compdirect($token)) { my $since = $self->unreadback(); $self->unreadback(''); # Close previous endif if ($Opt_Synthcov) { # Else accelerate if ($token eq "`elsif" || $token eq "`else" || $token eq "`endif") { if ($PreCovOff[$PreLevel] && $Opt_Synthcov) { push @Sendout, [0, ::coverage_on(0)]; } $PreLevel--; } } # Current token push @Sendout, [$Last_Lineno, $since . $token]; # Begin new endif if ($Opt_Synthcov) { # Else accelerate if ($token eq "`ifdef" || $token eq "`ifndef" || $token eq "`elsif") { $PreLevel++; $Last_Prekwd = $token; } elsif ($token eq "`else") { $PreLevel++; $PreCovOff[$PreLevel] = !$PreCovOff[$PreLevel]; if ($PreCovOff[$PreLevel] && $Opt_Synthcov) { push @Sendout, [0, ::coverage_off(0)]; } } } $Last_Lineno = $self->lineno; } else { $self->symbol($token); } } package main; ###################################################################### ###################################################################### ###################################################################### __END__ =pod =head1 NAME vpassert - Preprocess Verilog code assertions =head1 SYNOPSIS B [ B<--help> ] [ B<--date> ] [ B<--quiet> ] [ -y B ] [ B ] =head1 DESCRIPTION Vpassert will read the specified Verilog files and preprocess special PLI assertions. The files are written to the directory named .vpassert unless another name is given with B<-o>. If a directory is passed, all files in that directory will be preprocessed. =head1 ARGUMENTS Standard VCS and GCC-like parameters are used to specify the files to be preprocessed: +libext+I+I... Specify extensions to be processed -f I Parse parameters in file -v I Parse the library file (I) -y I Parse all files in the directory (I) -II Parse all files in the directory (I) +incdir+I Parse all files in the directory (I) To prevent recursion and allow reuse of the input.vc being passed to the simulator, if the output directory is requested to be preprocessed, that directory is simply ignored. =over 4 =item --allfiles Preprocess and write out files that do not have any macros that need expanding. By default, files that do not need processing are not written out. This option may speed up simulator compile times; the file will always be found in the preprocessed directory, saving the compiler from having to search a large number of -v directories to find it. =item --axiom Special Axiom ATHDL enables/disables added around unreachable code. =item --call-error When $uerror (or $uassert etc.) wants to display a message, call the specified function instead of $display and $stop. =item --call-info When $uinfo wants to display a message, call the specified function instead of $display. =item --call-warn When $uwarn (or $uwarn_clk etc.) wants to display a message, call the specified function instead of $display and $stop. =item --date Check file dates and sizes versus the last run of vpassert and don't process if the given source file has not changed. =item --exclude Exclude processing any files which begin with the specified prefix. =item --help Displays this message and program version and exits. =item --language <1364-1995|1364-2001|1364-2005|1800-2005|1800-2009|1800-2012|1800-2017|1800-2023> Set the language standard for the files. This determines which tokens are signals versus keywords, such as the ever-common "do" (data-out signal, versus a do-while loop keyword). =item --minimum Include `__message_minimum in the $uinfo test, so that by defining __message_minimum=1 some uinfos may be optimized away at compile time. =item --noline Do not emit `line directives. If not specified they will be used under --language 1364-2001 and later. =item --nopli Delete all 'simple' PLI calls. PLI function calls inside parenthesis will not be changed, and thus may still need to be manually ifdef'ed out. Useful for reducing the amount of `ifdef's required to feed non-PLI competent synthesis programs. =item --nostop By default, $error and $warn insert a $stop statement. With --nostop, this is replaced by incrementing a variable, which may then be used to conditionally halt simulation. =item --o I Use the given filename for output instead of the input name .vpassert. If the name ends in a / it is used as a output directory with the default name. =item --quiet Suppress messages about what files are being preprocessed. =item --realintent Special RealIntent enable/disables added around unreachable code. =item --synthcov When "ifdef SYNTHESIS" is seen, disable coverage. Resume on the `else or `endif. This does NOT follow child defines, for example: `ifdef SYNTHSIS `define MYSYNTH `endif `ifdef MYSYNTH // This will not be coveraged-off =item --timeformat-units I If specified, include Verilog $timeformat calls before all messages. Use the provided argument as the units. Units is in powers of 10, so -9 indicates to use nanoseconds. =item --timeformat-precision I When using --timeformat-units, use this as the precision value, the number of digits after the decimal point. Defaults to zero. =item --vericov Special Vericov enable/disables added around unreachable code. =item --verilator Special Verilator translations enabled. =item --version Displays program version and exits. =item --vcs Special Synopsys VCS enables/disables added around unreachable code. =back =head1 FUNCTIONS These Verilog pseudo-pli calls are expanded: =over 4 =item /*vp_coverage_off*/ Disable coverage for all tools starting at this point. Does not need to be on a unique line. =item /*vp_coverage_on*/ Re-enable coverage after a vp_coverage_off. Does not need to be on a unique line. =item $uassert(I, "message", [I...] ) Report a $uerror if the given case is FALSE. (Like assert() in C.) =item $uassert_amone(I, [I...], "message", [I...] ) Report a $uerror if more than one signal is asserted, or any are X. (None asserted is ok.) The error message will include a binary display of the signal values. =item $uassert_info(I, "message", [I...] ) Report a $uinfo if the given case is FALSE. (Like assert() in C.) =item $uassert_onehot(I, [I...], "message", [I...] ) Report a $uerror if other than one signal is asserted, or any are X. The error message will include a binary display of the signal values. =item $uassert_req_ack(I, I, [I,...] ) Check for a single cycle request pulse, followed by a single cycle acknowledgment pulse. Do not allow any of the data signals to change between the request and acknowledgment. =item $ucheck_ilevel(I ) Return true if the __message level is greater or equal to the given level, and that global messages are turned on. =item $ucover_clk(I, I