qflow-1.1.23/0000755000175000001440000000000012624543605011445 5ustar timusersqflow-1.1.23/configure.in0000664000175000001440000001205612606477746014000 0ustar timusers#!/bin/sh AC_INIT(VERSION,, eda-dev@opencircuitdesign.com) AC_PREREQ(2.60) AC_CONFIG_SRCDIR([Makefile.in]) # Determine the host and build type. # =========================================================================== AC_CANONICAL_HOST PACKAGE=qflow VERSION=`cat ./VERSION | cut -d. -f1-2` REVISION=`cat ./VERSION | cut -d. -f3` AC_SUBST(VERSION) AC_SUBST(REVISION) AC_ARG_PROGRAM # Required programs # =========================================================================== AC_PROG_CC AC_PROG_CPP AC_ISC_POSIX if test "x$U" != "x"; then AC_MSG_ERROR(Compiler not ANSI compliant) fi AC_PROG_INSTALL AC_PROG_RANLIB AC_CHECK_PROG(AUTOCONF, autoconf, autoconf, :) AC_CHECK_PROG(CP, cp, cp, :) AC_CHECK_PROG(RM, rm, rm, :) AC_LANG_C AC_HEADER_STDC AC_CHECK_FUNCS(setenv putenv) # Options # ========================================= dnl Path to Tcl/Tk AC_ARG_WITH(tclsh, [ --with-tclsh=DIR path to tclsh], [ if test -d "$withval"; then TCLSH_DIR=$withval elif test -f "$withval"; then # Path includes "/tclsh"; remove it TCLSH_DIR=${withval%/tclsh} else TCLSH_DIR=${PATH} fi AC_PATH_PROG(TCLSH_PATH, tclsh, tclsh, $TCLSH_DIR) ], [ AC_PATH_PROG(TCLSH_PATH, tclsh, tclsh, )]) AC_DEFINE_UNQUOTED(TCLSH_PATH, "$TCLSH_PATH") dnl Path to Magic 8.0 AC_ARG_WITH(magic, [ --with-magic=DIR path to magic-8.0], [ if test -d "$withval"; then QFLOW_MAGIC_DIR=$withval elif test -f "$withval"; then # Path includes "/magic"; remove it QFLOW_MAGIC_DIR=${withval%/magic} else QFLOW_MAGIC_DIR=${PATH} fi AC_PATH_PROG(QFLOW_MAGIC_PATH, magic, , $QFLOW_MAGIC_DIR) ], [ AC_PATH_PROG(QFLOW_MAGIC_PATH, magic, , )]) AC_DEFINE_UNQUOTED(QFLOW_MAGIC_PATH, "$QFLOW_MAGIC_PATH") dnl Path to Qrouter AC_ARG_WITH(qrouter, [ --with-qrouter=DIR path to qrouter], [ if test -d "$withval"; then QFLOW_QROUTER_DIR=$withval elif test -f "$withval"; then # Path includes "/qrouter"; remove it QFLOW_QROUTER_DIR=${withval%/qrouter} else QFLOW_QROUTER_DIR=${PATH} fi AC_PATH_PROG(QFLOW_QROUTER_PATH, qrouter, , $QFLOW_QROUTER_DIR) ], [ AC_PATH_PROG(QFLOW_QROUTER_PATH, qrouter, , )]) AC_DEFINE_UNQUOTED(QFLOW_QROUTER_PATH, "$QFLOW_QROUTER_PATH") dnl Path to GrayWolf AC_ARG_WITH(graywolf, [ --with-graywolf=DIR path to graywolf], [ if test -d "$withval"; then QFLOW_GRAYWOLF_DIR=$withval elif test -f "$withval"; then # Path includes "/graywolf"; remove it QFLOW_GRAYWOLF_DIR=${withval%/graywolf} else QFLOW_GRAYWOLF_DIR=${PATH} fi AC_PATH_PROG(QFLOW_GRAYWOLF_PATH, graywolf, , $QFLOW_GRAYWOLF_DIR) ], [ AC_PATH_PROG(QFLOW_GRAYWOLF_PATH, graywolf, , )]) AC_DEFINE_UNQUOTED(QFLOW_GRAYWOLF_PATH, "$QFLOW_GRAYWOLF_PATH") dnl Path to yosys AC_ARG_WITH(yosys, [ --with-yosys=DIR path to yosys], [ if test -d "$withval"; then QFLOW_YOSYS_DIR=$withval elif test -f "$withval"; then # Path includes "/yosys"; remove it QFLOW_YOSYS_DIR=${withval%/yosys} else QFLOW_YOSYS_DIR=${PATH} fi AC_PATH_PROG(QFLOW_YOSYS_PATH, yosys, , $QFLOW_YOSYS_DIR) ], [ AC_PATH_PROG(QFLOW_YOSYS_PATH, yosys, , )]) AC_DEFINE_UNQUOTED(QFLOW_YOSYS_PATH, "$QFLOW_YOSYS_PATH") dnl Expand the prefix variable if test "x$prefix" = xNONE ; then prefix=$ac_default_prefix fi dnl Target library location AC_ARG_WITH(libdir, [ --with-libdir=DIR path to qflow runtime files], [ QFLOW_LIB_DIR=$withval ], [ QFLOW_LIB_DIR=${prefix}/share/qflow ]) AC_ARG_WITH(bindir, [ --with-bindir=DIR path to qflow launch script], [ QFLOW_BIN_DIR=$withval ], [ QFLOW_BIN_DIR=${prefix}/bin ]) dnl AC_SUBST(QFLOW_YOSYS_PATH) dnl AC_SUBST(QFLOW_GRAYWOLF_PATH) dnl AC_SUBST(QFLOW_QROUTER_PATH) dnl AC_SUBST(QFLOW_MAGIC_PATH) AC_SUBST(QFLOW_BIN_DIR) AC_SUBST(QFLOW_LIB_DIR) AC_SUBST(TCLSH_PATH) AC_SUBST(CFLAGS) AC_SUBST(LDFLAGS) AC_SUBST(LD) AC_SUBST(STDLIBS) if test "x${ac_cv_path_QFLOW_YOSYS_PATH}" == "x"; then HAVE_YOSYS=0 else HAVE_YOSYS=1 fi AC_SUBST(HAVE_YOSYS) AC_OUTPUT(Makefile scripts/Makefile src/Makefile tech/Makefile tech/osu050/Makefile tech/osu035/Makefile tech/osu018/Makefile) echo "" echo "Configuration results:" echo "----------------------------------------------------" echo "" if test "x${ac_cv_path_QFLOW_YOSYS_PATH}" == "x"; then echo "ERROR: yosys not found. Use --with-yosys=" else echo "Using yosys verilog synthesis tool at: ${ac_cv_path_QFLOW_YOSYS_PATH}" fi if test "x${ac_cv_path_QFLOW_GRAYWOLF_PATH}" == "x"; then echo "ERROR: GrayWolf not found. Use --with-graywolf=" else echo "Using graywolf placement tool at: ${ac_cv_path_QFLOW_GRAYWOLF_PATH}" fi if test "x${ac_cv_path_QFLOW_QROUTER_PATH}" == "x"; then echo "ERROR: qrouter not found. Use --with-qrouter=" else echo "Using qrouter detail route tool at: ${ac_cv_path_QFLOW_QROUTER_PATH}" fi if test "x${ac_cv_path_QFLOW_MAGIC_PATH}" == "x"; then echo "WARNING: Magic 8.0 not found. Use --with-magic=" else echo "Using Magic layout tool at: ${ac_cv_path_QFLOW_MAGIC_PATH}" fi echo "----------------------------------------------------" qflow-1.1.23/Makefile.in0000644000175000001440000000103512526236535013513 0ustar timusers# # qflow project main Makefile # SHELL = /bin/sh EXEEXT = @EXEEXT@ TARGETS = src scripts tech all: $(TARGETS) @for target in $(TARGETS); do\ (cd $$target ; $(MAKE) all) ;\ done install: @for target in $(TARGETS); do\ (cd $$target ; $(MAKE) install) ;\ done clean: @for target in $(TARGETS); do\ (cd $$target ; $(MAKE) clean) ;\ done distclean: @for target in $(TARGETS); do\ (cd $$target ; $(MAKE) distclean) ;\ done uninstall: @for target in $(TARGETS); do\ (cd $$target ; $(MAKE) uninstall) ;\ done qflow-1.1.23/VERSION0000644000175000001440000000000712624543602012507 0ustar timusers1.1.23 qflow-1.1.23/config.log0000664000175000001440000002706612614150373013425 0ustar timusersThis file contains any messages produced by compilers while running configure, to aid debugging if configure makes a mistake. It was created by configure, which was generated by GNU Autoconf 2.69. Invocation command line was $ ./configure ## --------- ## ## Platform. ## ## --------- ## hostname = stravinsky uname -m = x86_64 uname -r = 3.18.3-201.fc21.x86_64 uname -s = Linux uname -v = #1 SMP Mon Jan 19 15:59:31 UTC 2015 /usr/bin/uname -p = x86_64 /bin/uname -X = unknown /bin/arch = x86_64 /usr/bin/arch -k = unknown /usr/convex/getsysinfo = unknown /usr/bin/hostinfo = unknown /bin/machine = unknown /usr/bin/oslevel = unknown /bin/universe = unknown PATH: . PATH: /bin PATH: /sbin PATH: /usr/bin PATH: /usr/sbin PATH: /usr/local/bin ## ----------- ## ## Core tests. ## ## ----------- ## configure:2016: checking build system type configure:2030: result: x86_64-unknown-linux-gnu configure:2050: checking host system type configure:2063: result: x86_64-unknown-linux-gnu configure:2151: checking for gcc configure:2167: found /bin/gcc configure:2178: result: gcc configure:2407: checking for C compiler version configure:2416: gcc --version >&5 gcc (GCC) 4.9.2 20141101 (Red Hat 4.9.2-1) Copyright (C) 2014 Free Software Foundation, Inc. This is free software; see the source for copying conditions. There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. configure:2427: $? = 0 configure:2416: gcc -v >&5 Using built-in specs. COLLECT_GCC=gcc COLLECT_LTO_WRAPPER=/usr/libexec/gcc/x86_64-redhat-linux/4.9.2/lto-wrapper Target: x86_64-redhat-linux Configured with: ../configure --prefix=/usr --mandir=/usr/share/man --infodir=/usr/share/info --with-bugurl=http://bugzilla.redhat.com/bugzilla --enable-bootstrap --enable-shared --enable-threads=posix --enable-checking=release --enable-multilib --with-system-zlib --enable-__cxa_atexit --disable-libunwind-exceptions --enable-gnu-unique-object --enable-linker-build-id --with-linker-hash-style=gnu --enable-languages=c,c++,objc,obj-c++,fortran,ada,go,lto --enable-plugin --enable-initfini-array --disable-libgcj --with-isl=/builddir/build/BUILD/gcc-4.9.2-20141101/obj-x86_64-redhat-linux/isl-install --with-cloog=/builddir/build/BUILD/gcc-4.9.2-20141101/obj-x86_64-redhat-linux/cloog-install --enable-gnu-indirect-function --with-tune=generic --with-arch_32=i686 --build=x86_64-redhat-linux Thread model: posix gcc version 4.9.2 20141101 (Red Hat 4.9.2-1) (GCC) configure:2427: $? = 0 configure:2416: gcc -V >&5 gcc: error: unrecognized command line option '-V' gcc: fatal error: no input files compilation terminated. configure:2427: $? = 4 configure:2416: gcc -qversion >&5 gcc: error: unrecognized command line option '-qversion' gcc: fatal error: no input files compilation terminated. configure:2427: $? = 4 configure:2447: checking whether the C compiler works configure:2469: gcc conftest.c >&5 configure:2473: $? = 0 configure:2521: result: yes configure:2524: checking for C compiler default output file name configure:2526: result: a.out configure:2532: checking for suffix of executables configure:2539: gcc -o conftest conftest.c >&5 configure:2543: $? = 0 configure:2565: result: configure:2587: checking whether we are cross compiling configure:2595: gcc -o conftest conftest.c >&5 configure:2599: $? = 0 configure:2606: ./conftest configure:2610: $? = 0 configure:2625: result: no configure:2630: checking for suffix of object files configure:2652: gcc -c conftest.c >&5 configure:2656: $? = 0 configure:2677: result: o configure:2681: checking whether we are using the GNU C compiler configure:2700: gcc -c conftest.c >&5 configure:2700: $? = 0 configure:2709: result: yes configure:2718: checking whether gcc accepts -g configure:2738: gcc -c -g conftest.c >&5 configure:2738: $? = 0 configure:2779: result: yes configure:2796: checking for gcc option to accept ISO C89 configure:2859: gcc -c -g -O2 conftest.c >&5 configure:2859: $? = 0 configure:2872: result: none needed configure:2897: checking how to run the C preprocessor configure:2928: gcc -E conftest.c configure:2928: $? = 0 configure:2942: gcc -E conftest.c conftest.c:9:28: fatal error: ac_nonexistent.h: No such file or directory #include ^ compilation terminated. configure:2942: $? = 1 configure: failed program was: | /* confdefs.h */ | #define PACKAGE_NAME "" | #define PACKAGE_TARNAME "" | #define PACKAGE_VERSION "" | #define PACKAGE_STRING "" | #define PACKAGE_BUGREPORT "" | #define PACKAGE_URL "" | /* end confdefs.h. */ | #include configure:2967: result: gcc -E configure:2987: gcc -E conftest.c configure:2987: $? = 0 configure:3001: gcc -E conftest.c conftest.c:9:28: fatal error: ac_nonexistent.h: No such file or directory #include ^ compilation terminated. configure:3001: $? = 1 configure: failed program was: | /* confdefs.h */ | #define PACKAGE_NAME "" | #define PACKAGE_TARNAME "" | #define PACKAGE_VERSION "" | #define PACKAGE_STRING "" | #define PACKAGE_BUGREPORT "" | #define PACKAGE_URL "" | /* end confdefs.h. */ | #include configure:3030: checking for library containing strerror configure:3061: gcc -o conftest -g -O2 conftest.c >&5 configure:3061: $? = 0 configure:3078: result: none required configure:3103: checking for a BSD-compatible install configure:3171: result: /bin/install -c configure:3225: checking for ranlib configure:3241: found /bin/ranlib configure:3252: result: ranlib configure:3276: checking for autoconf configure:3292: found /bin/autoconf configure:3304: result: autoconf configure:3314: checking for cp configure:3330: found /bin/cp configure:3342: result: cp configure:3352: checking for rm configure:3368: found /bin/rm configure:3380: result: rm configure:3396: checking for grep that handles long lines and -e configure:3454: result: /bin/grep configure:3459: checking for egrep configure:3521: result: /bin/grep -E configure:3526: checking for ANSI C header files configure:3546: gcc -c -g -O2 conftest.c >&5 configure:3546: $? = 0 configure:3619: gcc -o conftest -g -O2 conftest.c >&5 configure:3619: $? = 0 configure:3619: ./conftest configure:3619: $? = 0 configure:3630: result: yes configure:3641: checking for setenv configure:3641: gcc -o conftest -g -O2 conftest.c >&5 configure:3641: $? = 0 configure:3641: result: yes configure:3641: checking for putenv configure:3641: gcc -o conftest -g -O2 conftest.c >&5 configure:3641: $? = 0 configure:3641: result: yes configure:3713: checking for tclsh configure:3731: found /bin/tclsh configure:3744: result: /bin/tclsh configure:3817: checking for magic configure:3835: found /usr/local/bin/magic configure:3847: result: /usr/local/bin/magic configure:3920: checking for qrouter configure:3938: found /usr/local/bin/qrouter configure:3950: result: /usr/local/bin/qrouter configure:4023: checking for graywolf configure:4041: found /usr/local/bin/graywolf configure:4053: result: /usr/local/bin/graywolf configure:4126: checking for yosys configure:4144: found /usr/local/bin/yosys configure:4156: result: /usr/local/bin/yosys configure:4373: creating ./config.status ## ---------------------- ## ## Running config.status. ## ## ---------------------- ## This file was extended by config.status, which was generated by GNU Autoconf 2.69. Invocation command line was CONFIG_FILES = CONFIG_HEADERS = CONFIG_LINKS = CONFIG_COMMANDS = $ ./config.status on stravinsky config.status:757: creating Makefile config.status:757: creating scripts/Makefile config.status:757: creating src/Makefile config.status:757: creating tech/Makefile config.status:757: creating tech/osu050/Makefile config.status:757: creating tech/osu035/Makefile config.status:757: creating tech/osu018/Makefile ## ---------------- ## ## Cache variables. ## ## ---------------- ## ac_cv_build=x86_64-unknown-linux-gnu ac_cv_c_compiler_gnu=yes ac_cv_env_CC_set= ac_cv_env_CC_value= ac_cv_env_CFLAGS_set= ac_cv_env_CFLAGS_value= ac_cv_env_CPPFLAGS_set= ac_cv_env_CPPFLAGS_value= ac_cv_env_CPP_set= ac_cv_env_CPP_value= ac_cv_env_LDFLAGS_set= ac_cv_env_LDFLAGS_value= ac_cv_env_LIBS_set= ac_cv_env_LIBS_value= ac_cv_env_build_alias_set= ac_cv_env_build_alias_value= ac_cv_env_host_alias_set= ac_cv_env_host_alias_value= ac_cv_env_target_alias_set= ac_cv_env_target_alias_value= ac_cv_func_putenv=yes ac_cv_func_setenv=yes ac_cv_header_stdc=yes ac_cv_host=x86_64-unknown-linux-gnu ac_cv_objext=o ac_cv_path_EGREP='/bin/grep -E' ac_cv_path_GREP=/bin/grep ac_cv_path_QFLOW_GRAYWOLF_PATH=/usr/local/bin/graywolf ac_cv_path_QFLOW_MAGIC_PATH=/usr/local/bin/magic ac_cv_path_QFLOW_QROUTER_PATH=/usr/local/bin/qrouter ac_cv_path_QFLOW_YOSYS_PATH=/usr/local/bin/yosys ac_cv_path_TCLSH_PATH=/bin/tclsh ac_cv_path_install='/bin/install -c' ac_cv_prog_AUTOCONF=autoconf ac_cv_prog_CP=cp ac_cv_prog_CPP='gcc -E' ac_cv_prog_RM=rm ac_cv_prog_ac_ct_CC=gcc ac_cv_prog_ac_ct_RANLIB=ranlib ac_cv_prog_cc_c89= ac_cv_prog_cc_g=yes ac_cv_search_strerror='none required' ## ----------------- ## ## Output variables. ## ## ----------------- ## AUTOCONF='autoconf' CC='gcc' CFLAGS='-g -O2' CP='cp' CPP='gcc -E' CPPFLAGS='' DEFS='-DPACKAGE_NAME=\"\" -DPACKAGE_TARNAME=\"\" -DPACKAGE_VERSION=\"\" -DPACKAGE_STRING=\"\" -DPACKAGE_BUGREPORT=\"\" -DPACKAGE_URL=\"\" -DSTDC_HEADERS=1 -DHAVE_SETENV=1 -DHAVE_PUTENV=1 -DTCLSH_PATH=\"/bin/tclsh\" -DQFLOW_MAGIC_PATH=\"/usr/local/bin/magic\" -DQFLOW_QROUTER_PATH=\"/usr/local/bin/qrouter\" -DQFLOW_GRAYWOLF_PATH=\"/usr/local/bin/graywolf\" -DQFLOW_YOSYS_PATH=\"/usr/local/bin/yosys\"' ECHO_C='' ECHO_N='-n' ECHO_T='' EGREP='/bin/grep -E' EXEEXT='' GREP='/bin/grep' HAVE_YOSYS='1' INSTALL_DATA='${INSTALL} -m 644' INSTALL_PROGRAM='${INSTALL}' INSTALL_SCRIPT='${INSTALL}' LD='' LDFLAGS='' LIBOBJS='' LIBS='' LTLIBOBJS='' OBJEXT='o' PACKAGE_BUGREPORT='' PACKAGE_NAME='' PACKAGE_STRING='' PACKAGE_TARNAME='' PACKAGE_URL='' PACKAGE_VERSION='' PATH_SEPARATOR=':' QFLOW_BIN_DIR='/usr/local/bin' QFLOW_GRAYWOLF_PATH='/usr/local/bin/graywolf' QFLOW_LIB_DIR='/usr/local/share/qflow' QFLOW_MAGIC_PATH='/usr/local/bin/magic' QFLOW_QROUTER_PATH='/usr/local/bin/qrouter' QFLOW_YOSYS_PATH='/usr/local/bin/yosys' RANLIB='ranlib' REVISION='14' RM='rm' SHELL='/bin/sh' STDLIBS='' TCLSH_PATH='/bin/tclsh' VERSION='1.1' ac_ct_CC='gcc' bindir='${exec_prefix}/bin' build='x86_64-unknown-linux-gnu' build_alias='' build_cpu='x86_64' build_os='linux-gnu' build_vendor='unknown' datadir='${datarootdir}' datarootdir='${prefix}/share' docdir='${datarootdir}/doc/${PACKAGE}' dvidir='${docdir}' exec_prefix='${prefix}' host='x86_64-unknown-linux-gnu' host_alias='' host_cpu='x86_64' host_os='linux-gnu' host_vendor='unknown' htmldir='${docdir}' includedir='${prefix}/include' infodir='${datarootdir}/info' libdir='${exec_prefix}/lib' libexecdir='${exec_prefix}/libexec' localedir='${datarootdir}/locale' localstatedir='${prefix}/var' mandir='${datarootdir}/man' oldincludedir='/usr/include' pdfdir='${docdir}' prefix='/usr/local' program_transform_name='s,x,x,' psdir='${docdir}' sbindir='${exec_prefix}/sbin' sharedstatedir='${prefix}/com' sysconfdir='${prefix}/etc' target_alias='' ## ----------- ## ## confdefs.h. ## ## ----------- ## /* confdefs.h */ #define PACKAGE_NAME "" #define PACKAGE_TARNAME "" #define PACKAGE_VERSION "" #define PACKAGE_STRING "" #define PACKAGE_BUGREPORT "" #define PACKAGE_URL "" #define STDC_HEADERS 1 #define HAVE_SETENV 1 #define HAVE_PUTENV 1 #define TCLSH_PATH "/bin/tclsh" #define QFLOW_MAGIC_PATH "/usr/local/bin/magic" #define QFLOW_QROUTER_PATH "/usr/local/bin/qrouter" #define QFLOW_GRAYWOLF_PATH "/usr/local/bin/graywolf" #define QFLOW_YOSYS_PATH "/usr/local/bin/yosys" configure: exit 0 qflow-1.1.23/src/0000755000175000001440000000000012614150373012227 5ustar timusersqflow-1.1.23/src/Makefile.in0000664000175000001440000000420512554724076014311 0ustar timusers# # qflow project source compile makefile # # Main compiler arguments CFLAGS = @CFLAGS@ DEFS = @DEFS@ LIBS = @LIBS@ LDFLAGS = @LDFLAGS@ INSTALL = @INSTALL@ QFLOW_LIB_DIR = @QFLOW_LIB_DIR@ QFLOW_GRAYWOLF_PATH = @QFLOW_GRAYWOLF_PATH@ QFLOW_QROUTER_PATH = @QFLOW_QROUTER_PATH@ QFLOW_ABC_PATH = @QFLOW_ABC_PATH@ QFLOW_ODIN_PATH = @QFLOW_ODIN_PATH@ QFLOW_MAGIC_PATH = @QFLOW_MAGIC_PATH@ QFLOW_YOSYS_PATH = @QFLOW_YOSYS_PATH@ HAVE_ABC = @HAVE_ABC@ HAVE_YOSYS = @HAVE_YOSYS@ HAVE_ODIN_II = @HAVE_ODIN_II@ OBJECTS = blif2BSpice.o blif2Verilog.o blifFanout.o vesta.o HASHLIB = hash.o LIBERTYLIB = readliberty.o SOURCES := $(patsubst %.o,%.c,$(OBJECTS)) TARGETS := $(patsubst %.o,%$(EXEEXT),$(OBJECTS)) BININSTALL = ${QFLOW_LIB_DIR}/bin all: $(TARGETS) blif2BSpice$(EXEEXT): blif2BSpice.o $(CC) $(LDFLAGS) blif2BSpice.o -o $@ $(LIBS) blifFanout$(EXEEXT): blifFanout.o $(HASHLIB) $(LIBERTYLIB) $(CC) $(LDFLAGS) blifFanout.o $(HASHLIB) $(LIBERTYLIB) \ $(DEPENDS) -o $@ $(LIBS) -lm blif2Verilog$(EXEEXT): blif2Verilog.o $(CC) $(LDFLAGS) blif2Verilog.o -o $@ $(LIBS) vesta$(EXEEXT): vesta.o $(HASHLIB) $(CC) $(LDFLAGS) vesta.o $(HASHLIB) -o $@ $(LIBS) install: $(TARGETS) @echo "Installing verilog and BDNET file format handlers" $(INSTALL) -d $(DESTDIR)${BININSTALL} @for target in $(TARGETS); do \ $(INSTALL) $$target $(DESTDIR)${BININSTALL} ;\ done @echo "Installing links to graywolf, qrouter, odin_ii, and abc" (cd $(DESTDIR)${BININSTALL}; $(RM) -f graywolf; ln -s $(QFLOW_GRAYWOLF_PATH) graywolf) (cd $(DESTDIR)${BININSTALL}; $(RM) -f qrouter; ln -s $(QFLOW_QROUTER_PATH) qrouter) @if test "${HAVE_ABC}" = "1"; then \ (cd $(DESTDIR)${BININSTALL}; $(RM) -f abc; ln -s $(QFLOW_ABC_PATH) abc); \ fi (cd $(DESTDIR)${BININSTALL}; $(RM) -f magic; ln -s $(QFLOW_MAGIC_PATH) magic) @if test "${HAVE_YOSYS}" = "1"; then \ (cd $(DESTDIR)${BININSTALL}; $(RM) -f yosys; ln -s $(QFLOW_YOSYS_PATH) yosys); \ fi uninstall: $(RM) -rf ${BININSTALL} clean: $(RM) -f $(OBJECTS) $(HASHLIB) $(LIBERTYLIB) $(RM) -f $(TARGETS) veryclean: $(RM) -f $(OBJECTS) $(HASHLIB) $(LIBERTYLIB) $(RM) -f $(TARGETS) .c.o: $(CC) $(CFLAGS) $(CPPFLAGS) $(DEFS) -c $< -o $@ qflow-1.1.23/src/hash.h0000644000175000001440000000356512526236535013343 0ustar timusers#ifndef _HASH_H #define _HASH_H #define OBJHASHSIZE 997 struct hashlist { char *name; void *ptr; struct hashlist *next; }; extern void InitializeHashTable(struct hashlist **tab); extern int RecurseHashTable(struct hashlist **hashtab, int (*func)(struct hashlist *elem)); extern int RecurseHashTableValue(struct hashlist **hashtab, int (*func)(struct hashlist *elem, int), int); extern struct nlist *RecurseHashTablePointer(struct hashlist **hashtab, struct nlist *(*func)(struct hashlist *elem, void *), void *pointer); extern int CountHashTableEntries(struct hashlist *p); extern int CountHashTableBinsUsed(struct hashlist *p); extern void HashDelete(char *name, struct hashlist **hashtab); extern void HashIntDelete(char *name, int value, struct hashlist **hashtab); /* these functions return a pointer to a hash list element */ extern struct hashlist *HashInstall(char *name, struct hashlist **hashtab); extern struct hashlist *HashPtrInstall(char *name, void *ptr, struct hashlist **hashtab); extern struct hashlist *HashIntPtrInstall(char *name, int value, void *ptr, struct hashlist **hashtab); /* these functions return the ->ptr field of a struct hashlist */ extern void *HashLookup(char *s, struct hashlist **hashtab); extern void *HashIntLookup(char *s, int i, struct hashlist **hashtab); extern void *HashFirst(struct hashlist **hashtab); extern void *HashNext(struct hashlist **hashtab); extern unsigned long hashnocase(char *s); extern unsigned long hash(char *s); extern int (*matchfunc)(char *, char *); /* matchintfunc() compares based on the name and the first */ /* entry of the pointer value, which is cast as an integer */ extern int (*matchintfunc)(char *, char *, int, int); extern unsigned long (*hashfunc)(char *); /* the matching functions themselves */ extern int match(char *s1, char *s2); extern int matchnocase(char *s1, char *s2); #endif /* _HASH_H */ qflow-1.1.23/src/blif2Verilog.c0000664000175000001440000004176412535603240014735 0ustar timusers// blif2Verilog // // Revision 0, 2006-11-11: First release by R. Timothy Edwards. // Revision 1, 2009-07-13: Minor cleanups by Philipp Klaus Krause. // Revision 2, 2011-11-7: Added flag "-c" to maintain character case // Revision 3, 2013-10-09: Changed input format from BDNET to BLIF // // This program is written in ISO C99. #include #include #include #include #include #include #define EXIT_SUCCESS 0 #define EXIT_FAILURE 1 #define EXIT_HELP 2 #define TRUE 1 #define FALSE 0 #define NMOS 1 #define PMOS 0 #define LengthOfLine 16384 #define LengthOfNodeName 512 /* getopt stuff */ extern int optind, getopt(); extern char *optarg; #define INPUT 0 #define OUTPUT 1 struct Vect { struct Vect *next; char *name; char direction; /* INPUT or OUTPUT */ int Max; }; void ReadNetlistAndConvert(FILE *, FILE *, int, int); void CleanupString(char text[]); void ToLowerCase( char *text); float getnumber(char *strpntbegin); int loc_getline( char s[], int lim, FILE *fp); void helpmessage(); int ParseNumber( char *test); struct Vect *VectorAlloc(void); char *VddNet = NULL; char *GndNet = NULL; int main ( int argc, char *argv[]) { FILE *NET1 = NULL, *NET2, *OUT; struct Resistor *ResistorData; int i,AllMatched,NetsEqual,ImplicitPower,MaintainCase; char *Net1name = NULL; VddNet = strdup("VDD"); GndNet = strdup("VSS"); ImplicitPower=TRUE; MaintainCase=FALSE; while( (i = getopt( argc, argv, "pchHv:g:" )) != EOF ) { switch( i ) { case 'p': ImplicitPower=FALSE; break; case 'c': MaintainCase=TRUE; break; case 'h': case 'H': helpmessage(); break; case 'v': free(VddNet); VddNet = strdup(optarg); break; case 'g': free(GndNet); GndNet = strdup(optarg); break; default: fprintf(stderr,"\nbad switch %d\n", i ); helpmessage(); break; } } if( optind < argc ) { Net1name = strdup(argv[optind]); optind++; } else { fprintf(stderr,"Couldn't find a filename as input\n"); exit(EXIT_FAILURE); } optind++; if (Net1name) NET1=fopen(Net1name,"r"); if (NET1 == NULL ) { fprintf(stderr,"Couldn't open %s for read\n",Net1name); exit(EXIT_FAILURE); } OUT=stdout; ReadNetlistAndConvert(NET1,OUT,ImplicitPower,MaintainCase); return 0; } struct GateList { struct GateList *next; char *gatename; int gatecount; }; /*--------------------------------------------------------------*/ /*C *Alloc - Allocates memory for linked list elements */ /* */ /* ARGS: RETURNS: 1 to OS SIDE EFFECTS: \*--------------------------------------------------------------*/ void ReadNetlistAndConvert(FILE *NETFILE, FILE *OUT, int ImplicitPower, int MaintainCase) { struct Vect *Vector, *VectorPresent; struct GateList *glist; struct GateList *gl; int i, Found, NumberOfInputs, NumberOfOutputs; int First, VectorIndex, ItIsAnInput, ItIsAnOutput, PrintIt; char line[LengthOfLine]; char *Weirdpnt, *lptr; char *allinputs = NULL; char *alloutputs = NULL; char **InputNodes; char **OutputNodes; char InputName[LengthOfNodeName]; char OutputName[LengthOfNodeName]; char MainSubcktName[LengthOfNodeName]; char InstanceName[LengthOfNodeName]; char InstancePortName[LengthOfNodeName]; char InstancePortWire[LengthOfNodeName]; char dum[LengthOfNodeName]; glist = NULL; NumberOfOutputs = 0; NumberOfInputs = 0; InputNodes = (char **)malloc(sizeof(char *)); OutputNodes = (char **)malloc(sizeof(char *)); /* Read in line by line */ First = TRUE; Vector = VectorAlloc(); Vector->next = NULL; while (loc_getline(line, sizeof(line), NETFILE) > 0) { lptr = line; while (isspace(*lptr)) lptr++; if (strstr(lptr, ".model") != NULL) { if (sscanf(lptr, ".model %s", MainSubcktName) == 1) { CleanupString(MainSubcktName); fprintf(OUT, "module %s (", MainSubcktName); if (ImplicitPower) fprintf(OUT, " %s, %s, ", GndNet, VddNet); } } if (strstr(lptr, ".inputs") != NULL) { allinputs = (char *)malloc(1); allinputs[0] = '\0'; while (!isspace(*lptr)) lptr++; while (isspace(*lptr)) lptr++; while (1) { if (sscanf(lptr, "%s", InputName) == 1) { PrintIt = TRUE; CleanupString(InputName); InputNodes[NumberOfInputs] = strdup(InputName); if ((Weirdpnt = strchr(InputName,'[')) != NULL) { PrintIt = FALSE; VectorIndex = ParseNumber(Weirdpnt); // This one needs to cut off [..] VectorPresent = Vector; Found = FALSE; while (VectorPresent->next != NULL && !Found) { if (strcmp(VectorPresent->name, InputName) == 0) { VectorPresent->Max = (VectorPresent->Max > VectorIndex) ? VectorPresent->Max : VectorIndex; Found = TRUE; } VectorPresent = VectorPresent->next; } if (!Found) { VectorPresent->name = strdup(InputName); VectorPresent->direction = INPUT; VectorPresent->Max = VectorIndex; VectorPresent->next = VectorAlloc(); VectorPresent->next->next = NULL; } } if (PrintIt || !Found) { // Should print vectors in module statement if (First) { fprintf(OUT, "%s", InputName); First = FALSE; } else fprintf(OUT, ", %s", InputName); } if (PrintIt) { //Should not print vectors now allinputs = (char *)realloc(allinputs, strlen(allinputs) + strlen(InputName) + 9); strcat(allinputs, "input "); strcat(allinputs, InputName); strcat(allinputs, ";\n"); } NumberOfInputs++; InputNodes = (char **)realloc(InputNodes, (NumberOfInputs + 1) * sizeof(char *)); while (!isspace(*lptr)) lptr++; while (isspace(*lptr)) lptr++; if (*lptr == '\\') { if (loc_getline(line, sizeof(line), NETFILE) <= 1) break; else { lptr = line; while (isspace(*lptr)) lptr++; } } if (*lptr == '\n' || *lptr == '\0') break; } else break; } } if (strstr(lptr, ".outputs") != NULL) { alloutputs = (char *)malloc(1); alloutputs[0] = '\0'; while (!isspace(*lptr)) lptr++; while (isspace(*lptr)) lptr++; while (1) { if (sscanf(lptr, "%s", OutputName) == 1) { PrintIt = TRUE; CleanupString(OutputName); OutputNodes[NumberOfOutputs] = strdup(OutputName); if ((Weirdpnt = strchr(OutputName,'[')) != NULL) { PrintIt = FALSE; VectorIndex = ParseNumber(Weirdpnt); // This one needs to cut off [..] VectorPresent = Vector; Found = FALSE; while (VectorPresent->next != NULL && !Found) { if (strcmp(VectorPresent->name, OutputName) == 0) { VectorPresent->Max = (VectorPresent->Max > VectorIndex) ? VectorPresent->Max : VectorIndex; Found = TRUE; } VectorPresent = VectorPresent->next; } if (!Found) { VectorPresent->name = strdup(OutputName); VectorPresent->direction = OUTPUT; VectorPresent->Max = VectorIndex; VectorPresent->next = VectorAlloc(); VectorPresent->next->next = NULL; } } if (PrintIt || !Found) { if (First) { fprintf(OUT, "%s", OutputName); First = FALSE; } else fprintf(OUT, ", %s", OutputName); } if (PrintIt) { alloutputs = (char *)realloc(alloutputs, strlen(alloutputs) + strlen(OutputName) + 10); strcat(alloutputs, "output "); strcat(alloutputs, OutputName); strcat(alloutputs, ";\n"); } NumberOfOutputs++; OutputNodes = (char **)realloc(OutputNodes, (NumberOfOutputs + 1) * sizeof(char *)); while (!isspace(*lptr)) lptr++; while (isspace(*lptr)) lptr++; if (*lptr == '\\') { if (loc_getline(line, sizeof(line), NETFILE) <= 1) break; else { lptr = line; while (isspace(*lptr)) lptr++; } } if (*lptr == '\n' || *lptr == '\0') break; } else break; } fprintf(OUT,");\n\n"); if (ImplicitPower) fprintf(OUT, "input %s, %s;\n", GndNet, VddNet); if (allinputs) fprintf(OUT, "%s", allinputs); if (alloutputs) fprintf(OUT, "%s", alloutputs); VectorPresent = Vector; while (VectorPresent->next != NULL) { fprintf(OUT, "%s [%d:0] %s;\n", (VectorPresent->direction == INPUT) ? "input" : "output", VectorPresent->Max, VectorPresent->name); VectorPresent = VectorPresent->next; } fprintf(OUT, "\n"); if (!ImplicitPower) { fprintf(OUT, "wire %s = 1'b1;\n", VddNet); fprintf(OUT, "wire %s = 1'b0;\n", GndNet); fprintf(OUT, "\n"); } } if (strstr(lptr, ".end") != NULL) { fprintf(OUT, "endmodule\n"); } if (strstr(lptr,".gate") != NULL || strstr(lptr, ".subckt") != NULL) { if (sscanf(lptr, ".%*s %s", InstanceName) == 1) { CleanupString(InstanceName); if (!MaintainCase) ToLowerCase(InstanceName); for (gl = glist; gl; gl = gl->next) { if (!strcmp(gl->gatename, InstanceName)) { gl->gatecount++; break; } } if (gl == NULL) { gl = (struct GateList *)malloc(sizeof(struct GateList)); gl->gatename = strdup(InstanceName); gl->gatecount = 1; gl->next = glist; glist = gl; } fprintf(OUT, "\t%s %s_%d ( ", gl->gatename, gl->gatename, gl->gatecount); First = TRUE; if (ImplicitPower) fprintf(OUT, ".%s(%s), .%s(%s), ", GndNet, GndNet, VddNet, VddNet); while (!isspace(*lptr)) lptr++; while (isspace(*lptr)) lptr++; while (!isspace(*lptr)) lptr++; while (isspace(*lptr)) lptr++; while (1) { char *eptr; eptr = strchr(lptr, '='); if (eptr == NULL) break; *eptr = '\0'; if (sscanf(lptr, "%s", InstancePortName) != 1) break; lptr = eptr + 1; if (sscanf(lptr, "%s", InstancePortWire) != 1) break; CleanupString(InstancePortName); CleanupString(InstancePortWire); ItIsAnInput = FALSE; ItIsAnOutput = FALSE; for (i = 0; i < NumberOfInputs; i++) { if (!strcmp(InstancePortWire, InputNodes[i])) { ItIsAnInput = TRUE; strcpy(InstancePortWire, InputNodes[i]); Weirdpnt = strchr(InstancePortWire, ']'); if(Weirdpnt != NULL) *(Weirdpnt + 1) = '\0'; } } for (i = 0; i < NumberOfOutputs; i++) { if (!strcmp(InstancePortWire, OutputNodes[i])) { ItIsAnOutput = TRUE; strcpy(InstancePortWire, OutputNodes[i]); Weirdpnt = strchr(InstancePortWire, ']'); if (Weirdpnt != NULL) *(Weirdpnt + 1) = '\0'; } } if (!ItIsAnInput && !ItIsAnOutput) { if ((Weirdpnt = strchr(InstancePortWire,'[')) != NULL) { *Weirdpnt = '_'; if ((Weirdpnt = strchr(InstancePortWire,']')) != NULL) *Weirdpnt = '_'; } while ((Weirdpnt = strchr(InstancePortWire, '$')) != NULL) { *Weirdpnt = '_'; Weirdpnt++; } } if (InstancePortWire[0] <= '9' && InstancePortWire[0] >= '0') { strcpy(dum, "N_"); strcat(dum, InstancePortWire); strcpy(InstancePortWire, dum); } if (First) { fprintf(OUT, ".%s(%s)", InstancePortName, InstancePortWire); First = FALSE; } else fprintf(OUT, ", .%s(%s)", InstancePortName, InstancePortWire); while (!isspace(*lptr)) lptr++; while (isspace(*lptr)) lptr++; if (*lptr == '\\') { if (loc_getline(line, sizeof(line), NETFILE) <= 1) break; lptr = line; } else if (*lptr == '\n') break; } fprintf(OUT, " );\n"); } } } } int ParseNumber( char *text) { char *begin, *end; // Assumes *text is a '[' begin=(text+1); end=strchr(begin,']'); *end='\0'; *text='\0'; return atoi(begin); } void ToLowerCase( char *text) { int i=0; while( text[i] != '\0' ) { text[i]=tolower(text[i]); i++; } } void CleanupString(char text[LengthOfNodeName]) { int i; char *CitationPnt, *Weirdpnt; CitationPnt=strchr(text,'"'); if( CitationPnt != NULL) { i=0; while( CitationPnt[i+1] != '"' ) { CitationPnt[i]=CitationPnt[i+1]; i+=1; } CitationPnt[i]='\0'; } // Convert angle brackets to square brackets if they // occur at the end of a name; otherwise, convert // them to underscores while ((Weirdpnt = strchr(text,'<')) != NULL) { char *eptr; eptr = strchr(Weirdpnt, '>'); if (eptr == NULL) { *Weirdpnt = '_'; } else { if (*(eptr + 1) == '\0') { *Weirdpnt = '['; *eptr = ']'; } else { *Weirdpnt = '_'; *eptr = '_'; } } } // Disallow characters '.' and ':' in node names while ((Weirdpnt=strchr(text,'.')) != NULL) *Weirdpnt='_'; while ((Weirdpnt=strchr(text,':')) != NULL) *Weirdpnt='_'; } /*--------------------------------------------------------------*/ /*C getnumber - gets number pointed by strpntbegin */ /* */ /* ARGS: strpntbegin - number expected after '=' */ /* RETURNS: 1 to OS SIDE EFFECTS: \*--------------------------------------------------------------*/ float getnumber(char *strpntbegin) { int i; char *strpnt,magn1,magn2; float number; strpnt=strpntbegin; strpnt=strchr(strpntbegin,'='); if(strpnt == NULL) { fprintf(stderr,"Error: getnumber: Didn't find '=' in string " "%s\n",strpntbegin); return DBL_MAX; } strpnt=strpnt+1; if(sscanf(strpnt,"%f%c%c",&number,&magn1, &magn2)!=3) { if(sscanf(strpnt,"%f%c",&number,&magn1)!=2) { fprintf(stderr,"Error: getnumber : Couldn't read number in " "%s %s\n",strpntbegin,strpnt); return DBL_MAX; } } /*if(*strpntbegin =='m') */ switch( magn1 ) { case 'f': number *= 1e-15; break; case 'p': number *= 1e-12; break; case 'n': number *= 1e-9; break; case 'u': number *= 1e-6; break; case 'm': if(magn2='e') number *= 1e6; else number *= 1e-3; break; case 'k': number *= 1e3; break; case 'g': number *= 1e9; break; case ' ': default: return number; } return number; } /*--------------------------------------------------------------*/ /*C loc_getline: read a line, return length */ /* */ /* ARGS: RETURNS: 1 to OS SIDE EFFECTS: \*--------------------------------------------------------------*/ int loc_getline( char s[], int lim, FILE *fp) { int c, i; i=0; while(--lim > 0 && (c=getc(fp)) != EOF && c != '\n') s[i++] = c; if (c == '\n'); s[i++] = c; s[i] = '\0'; if ( c == EOF ) i=0; return i; } struct Vect *VectorAlloc(void) { return (struct Vect *) malloc(sizeof(struct Vect)); } /*--------------------------------------------------------------*/ /*C helpmessage - tell user how to use the program */ /* */ /* ARGS: RETURNS: 1 to OS SIDE EFFECTS: \*--------------------------------------------------------------*/ void helpmessage() { fprintf(stderr,"blif2Verilog [-options] netlist \n"); fprintf(stderr,"\n"); fprintf(stderr,"blif2Verilog converts a netlist in blif format \n"); fprintf(stderr,"to Verilog format. Output on stdout\n"); fprintf(stderr,"\n"); fprintf(stderr,"option, -h this message\n"); fprintf(stderr,"option, -p means: don't add power nodes to instances\n"); fprintf(stderr," only nodes present in the .gate statement used\n"); exit( EXIT_HELP ); } /* helpmessage() */ qflow-1.1.23/src/Makefile0000664000175000001440000000500212614150373013666 0ustar timusers# # qflow project source compile makefile # # Main compiler arguments CFLAGS = -g -O2 DEFS = -DPACKAGE_NAME=\"\" -DPACKAGE_TARNAME=\"\" -DPACKAGE_VERSION=\"\" -DPACKAGE_STRING=\"\" -DPACKAGE_BUGREPORT=\"\" -DPACKAGE_URL=\"\" -DSTDC_HEADERS=1 -DHAVE_SETENV=1 -DHAVE_PUTENV=1 -DTCLSH_PATH=\"/bin/tclsh\" -DQFLOW_MAGIC_PATH=\"/usr/local/bin/magic\" -DQFLOW_QROUTER_PATH=\"/usr/local/bin/qrouter\" -DQFLOW_GRAYWOLF_PATH=\"/usr/local/bin/graywolf\" -DQFLOW_YOSYS_PATH=\"/usr/local/bin/yosys\" LIBS = LDFLAGS = INSTALL = /bin/install -c QFLOW_LIB_DIR = /usr/local/share/qflow QFLOW_GRAYWOLF_PATH = /usr/local/bin/graywolf QFLOW_QROUTER_PATH = /usr/local/bin/qrouter QFLOW_ABC_PATH = @QFLOW_ABC_PATH@ QFLOW_ODIN_PATH = @QFLOW_ODIN_PATH@ QFLOW_MAGIC_PATH = /usr/local/bin/magic QFLOW_YOSYS_PATH = /usr/local/bin/yosys HAVE_ABC = @HAVE_ABC@ HAVE_YOSYS = 1 HAVE_ODIN_II = @HAVE_ODIN_II@ OBJECTS = blif2BSpice.o blif2Verilog.o blifFanout.o vesta.o HASHLIB = hash.o LIBERTYLIB = readliberty.o SOURCES := $(patsubst %.o,%.c,$(OBJECTS)) TARGETS := $(patsubst %.o,%$(EXEEXT),$(OBJECTS)) BININSTALL = ${QFLOW_LIB_DIR}/bin all: $(TARGETS) blif2BSpice$(EXEEXT): blif2BSpice.o $(CC) $(LDFLAGS) blif2BSpice.o -o $@ $(LIBS) blifFanout$(EXEEXT): blifFanout.o $(HASHLIB) $(LIBERTYLIB) $(CC) $(LDFLAGS) blifFanout.o $(HASHLIB) $(LIBERTYLIB) \ $(DEPENDS) -o $@ $(LIBS) -lm blif2Verilog$(EXEEXT): blif2Verilog.o $(CC) $(LDFLAGS) blif2Verilog.o -o $@ $(LIBS) vesta$(EXEEXT): vesta.o $(HASHLIB) $(CC) $(LDFLAGS) vesta.o $(HASHLIB) -o $@ $(LIBS) install: $(TARGETS) @echo "Installing verilog and BDNET file format handlers" $(INSTALL) -d $(DESTDIR)${BININSTALL} @for target in $(TARGETS); do \ $(INSTALL) $$target $(DESTDIR)${BININSTALL} ;\ done @echo "Installing links to graywolf, qrouter, odin_ii, and abc" (cd $(DESTDIR)${BININSTALL}; $(RM) -f graywolf; ln -s $(QFLOW_GRAYWOLF_PATH) graywolf) (cd $(DESTDIR)${BININSTALL}; $(RM) -f qrouter; ln -s $(QFLOW_QROUTER_PATH) qrouter) @if test "${HAVE_ABC}" = "1"; then \ (cd $(DESTDIR)${BININSTALL}; $(RM) -f abc; ln -s $(QFLOW_ABC_PATH) abc); \ fi (cd $(DESTDIR)${BININSTALL}; $(RM) -f magic; ln -s $(QFLOW_MAGIC_PATH) magic) @if test "${HAVE_YOSYS}" = "1"; then \ (cd $(DESTDIR)${BININSTALL}; $(RM) -f yosys; ln -s $(QFLOW_YOSYS_PATH) yosys); \ fi uninstall: $(RM) -rf ${BININSTALL} clean: $(RM) -f $(OBJECTS) $(HASHLIB) $(LIBERTYLIB) $(RM) -f $(TARGETS) veryclean: $(RM) -f $(OBJECTS) $(HASHLIB) $(LIBERTYLIB) $(RM) -f $(TARGETS) .c.o: $(CC) $(CFLAGS) $(CPPFLAGS) $(DEFS) -c $< -o $@ qflow-1.1.23/src/vesta.c0000664000175000001440000033355212533350457013537 0ustar timusers/*--------------------------------------------------------------*/ /* vesta.c --- */ /* */ /* This file reads two files: (1) A verilog netlist file */ /* of a circuit (structural verilog, that is, gate-level */ /* information only), and (2) a liberty format file */ /* containing timing information for the standard cell */ /* macros instantiated in the verilog netlist. In */ /* addition, it may take an optional third file containing */ /* information about the resistance and capacitance of the */ /* wiring (see below). */ /* */ /* Options are supplied as command-line arguments: */ /* */ /* -d Wiring delays (see below) */ /* -p Clock period, in ps */ /* -l Output load, in fF */ /* -v set verbose mode */ /* -V report version number */ /* -e exhaustive search */ /* */ /* Currently the only output this tool generates is a */ /* list of paths with negative slack. If no paths have */ /* negative slack, then the 20 paths with the smallest */ /* positive slack are output, following a "success" */ /* message. If no clock period is supplied, then the */ /* clock period is set to equal the delay of the longest */ /* delay path, and the 20 paths with the smallest positive */ /* slack are output, following a statement indicated the */ /* computed minimum clock period. */ /*--------------------------------------------------------------*/ /*--------------------------------------------------------------*/ /* Wiring delay file: */ /* For qflow, the wiring delay is generated by the tool */ /* "def2delays". The file format is as follows: */ /* */ /* */ /* [] */ /* */ /* ... */ /* */ /* */ /* Optional value is in fF */ /* Values are in ps */ /*--------------------------------------------------------------*/ #include #include #include #include #include #include #include // Temporary, for fabs() #include "hash.h" // For net hash table #define LIB_LINE_MAX 65535 int fileCurrentLine; // Analysis types --- note that maximum flop-to-flop delay // requires calculating minimum clock skew time, and vice // versa, so it is necessary that these have TRUE/FALSE // values. #define MINIMUM_TIME 0 #define MAXIMUM_TIME 1 // Multiple-use definition #define UNKNOWN -1 // Sections of liberty file #define INIT 0 #define LIBBLOCK 1 #define CELLDEF 2 #define PINDEF 3 #define FLOPDEF 4 #define LATCHDEF 5 #define TIMING 6 // Sections of verilog file #define MODULE 0 #define IOLIST 1 #define GATELIST 2 #define INSTANCE 3 #define INSTPIN 4 #define PINCONN 5 // Pin types (these are masks---e.g., a pin can be an INPUT and a CLOCK) #define INPUT 0x01 // The default #define OUTPUT 0x02 #define DFFCLK 0x04 #define DFFIN 0x08 // Flop input #define DFFOUT 0x10 // Flop output #define DFFSET 0x20 // Flop set (preset) #define DFFRST 0x40 // Flop reset (clear) #define LATCHIN 0x80 // Latch input #define LATCHEN 0x100 // Latch enable #define LATCHOUT 0x200 // Latch output // Timing type (for tables) #define TIMING_PROP_TRANS 0 #define TIMING_HOLD 1 #define TIMING_SETUP 2 #define TIMING_SET_RESET 3 #define TIMING_RECOVERY 4 #define TIMING_REMOVAL 5 #define TIMING_TRISTATE 6 // A few short-hand definitions #define DFF_ALL_IN (DFFCLK | DFFIN | DFFSET | DFFRST) #define LATCH_ALL_IN (LATCHIN | LATCHEN) #define DFF_IN_NOT_CLK (DFFIN | DFFSET | DFFRST) #define LATCH_IN_NOT_EN (LATCHIN) #define REGISTER_IN (DFF_ALL_IN | LATCH_ALL_IN) #define REG_IN_NOT_CLK (DFF_IN_NOT_CLK | LATCH_IN_NOT_EN) #define IOMASK 0x03 #define DFFMASK 0x7c #define LATCHMASK 0x180 // Pin sense #define SENSE_UNKNOWN 0 // Sense unknown #define SENSE_NONE 1 // Non-unate #define SENSE_POSITIVE 2 // Positive-unate #define SENSE_NEGATIVE 3 // Negative-unate // Signal transition direction #define EDGE_UNKNOWN 0 #define RISING 1 #define FALLING 2 #define EITHER 3 // Function translation #define GROUPBEGIN 1 #define GROUPEND 2 #define SIGNAL 3 #define OPERATOR 4 #define XOPERATOR 5 #define SEPARATOR 6 // Net types #define NET 0x00 // Ordinary net (default) #define CLOCK 0x01 // Clock net (path start) #define OUTTERM 0x02 // Module output #define ASYNC 0x04 // Asynchronous set/reset #define TERMINAL 0x08 // DFF input (path terminal) #define LATCHTERM 0x10 // Latch input (dependent path terminal) #define ENABLE 0x20 // Latch enable (path start) // Cell types #define GATE 0x00 // Combinatorial gate (default) #define DFF 0x01 // Flip-flop (shared bit field) #define CLK_SENSE_MASK 0x02 // Clock edge mask (0=positive, 1=negative) #define RST_MASK 0x04 // Reset mask (0=no reset, 1=reset) #define RST_SENSE_MASK 0x08 // Reset edge mask (0=positive, 1=negative) #define SET_MASK 0x10 // Set mask (0=no set, 1=set) #define SET_SENSE_MASK 0x20 // Set edge mask (0=positive, 1=negative) #define LATCH 0x40 // Latch type #define EN_SENSE_MASK 0x80 // Latch enable edge mask (0=positive, 1=negative) // Some names for cell types based on masks #define DFFCP 0x01 // Pos clock #define DFFCN 0x03 // Neg clock #define DFFCPRP 0x05 // Pos clock, Pos reset #define DFFCNRP 0x07 // Neg clock, Pos reset #define DFFCPRN 0x0d // Pos clock, Neg reset #define DFFCNRN 0x0f // Neg clock, Neg reset #define DFFCPSP 0x11 // Pos clock, Pos set #define DFFCNSP 0x13 // Neg clock, Pos set #define DFFCPRPSP 0x15 // Pos clock, Pos reset, Pos set #define DFFCNRPSP 0x17 // Neg clock, Pos reset, Pos set #define DFFCPRNSP 0x1d // Pos clock, Neg reset, Pos set #define DFFCNRNSP 0x1f // Neg clock, Neg reset, Pos set #define DFFCPSN 0x31 // Pos clock, Neg set #define DFFCNSN 0x33 // Neg clock, Neg set #define DFFCPRPSN 0x35 // Pos clock, Pos reset, Neg set #define DFFCNRPSN 0x37 // Neg clock, Pos reset, Neg set #define DFFCPRNSN 0x3d // Pos clock, Neg reset, Neg set #define DFFCNRNSN 0x3f // Neg clock, Neg reset, Neg set /*--------------------------------------------------------------*/ /* Liberty file database */ /*--------------------------------------------------------------*/ // Types of array // Array type 1: Propagation time #define OUTPUT_CAP 0 #define TRANSITION_TIME 1 // Array type 2: Setup, hold, recovery, removal times #define RELATED_TIME 2 #define CONSTRAINED_TIME 3 typedef struct _lutable *lutableptr; typedef struct _lutable { char *name; char invert; // 0 if times x caps, 1 if caps x times int var1; // Type of array in index1 int var2; // Type of array in index2 int size1; // Number of entries in time array int size2; // Number of entries in cap (or constrained timing) array union { double *times; // Time array (units ps) double *rel; // Related pin transition time array (units ps) } idx1; union { double *caps; // Cap array (units fF) double *cons; // Constrained pin transition time array (units ps) } idx2; double *values; // Matrix of values (used locally, not for templates) lutableptr next; } lutable; typedef struct _pin *pinptr; typedef struct _cell *cellptr; typedef struct _pin { char *name; short type; double capr; // Capacitance for rising input double capf; // Capacitance for falling input (optional) short sense; // Sense (positive-unate, negative-unate, non-unate) lutable *propdelr; // Reference table for rising output prop delay relative to driver lutable *propdelf; // Reference table for falling output prop delay relative to driver lutable *transr; // Reference table for transition rise time lutable *transf; // Reference table for transition fall time cellptr refcell; // Pointer back to parent cell pinptr next; } pin; typedef struct _cell { short type; char *name; char *function; pin *pins; /* List of input pins with timing info */ double area; double maxtrans; /* Maximum transition time */ double maxcap; /* Maximum allowable load */ cellptr next; } cell; /*--------------------------------------------------------------*/ /* Verilog netlist database */ /*--------------------------------------------------------------*/ typedef struct _net *netptr; typedef struct _connect *connptr; typedef struct _delaydata *ddataptr; typedef struct _net { char *name; connptr driver; short type; int fanout; connptr *receivers; double loadr; /* Total load capacitance for rising input */ double loadf; /* Total load capacitance for falling input */ netptr next; } net; typedef struct _instance *instptr; typedef struct _connect { double metric; /* Delay metric at connection */ instptr refinst; pinptr refpin; netptr refnet; ddataptr tag; /* Tag value for checking for loops and endpoints */ double *prvector; /* Prop delay rising (at load condition) vector */ double *pfvector; /* Prop delay falling (at load condition) vector */ double *trvector; /* Transition time rising (at load condition) vector */ double *tfvector; /* Transition time falling (at load condition) vector */ connptr next; } connect; typedef struct _instance { char *name; cellptr refcell; connptr in_connects; connptr out_connects; instptr next; } instance; // Linked list of delays (backtrace to source) typedef struct _btdata *btptr; typedef struct _btdata { double delay; /* Propagation delay to this point */ double trans; /* Transition time at this point */ short dir; /* Edge direction at this point */ connptr receiver; /* Receiver connection at end of path */ int refcnt; /* Reference counter for backtrace data */ btptr next; /* Path of propagation */ } btdata; // Linked list of backtrace records typedef struct _delaydata { double delay; /* Total delay, including setup and clock skew */ double trans; /* Transition time at destination, used to find setup */ btptr backtrace; ddataptr next; } delaydata; // Linked list of connection pointers // (Much like delaydata, but without all the timing information) typedef struct _connlist *connlistptr; typedef struct _connlist { connptr connection; connlistptr next; } connlist; /* Global variables */ unsigned char verbose; /* Level of debug output generated */ unsigned char exhaustive; /* Exhaustive search mode */ /*--------------------------------------------------------------*/ /* Grab a token from the input */ /* Return the token, or NULL if we have reached end-of-file. */ /*--------------------------------------------------------------*/ char * advancetoken(FILE *flib, char delimiter) { static char token[LIB_LINE_MAX]; static char line[LIB_LINE_MAX]; static char *linepos = NULL; char *lineptr = linepos; char *lptr, *tptr; char *result; int commentblock, concat, nest; commentblock = 0; concat = 0; nest = 0; while (1) { /* Keep processing until we get a token or hit EOF */ if (lineptr != NULL && *lineptr == '/' && *(lineptr + 1) == '*') { commentblock = 1; } if (commentblock == 1) { if ((lptr = strstr(lineptr, "*/")) != NULL) { lineptr = lptr + 2; commentblock = 0; } else lineptr = NULL; } if (lineptr == NULL || *lineptr == '\n' || *lineptr == '\0') { result = fgets(line, LIB_LINE_MAX, flib); fileCurrentLine++; if (result == NULL) return NULL; /* Keep pulling stuff in if the line ends with a continuation character */ lptr = line; while (*lptr != '\n' && *lptr != '\0') { if (*lptr == '\\') { // To be considered a line continuation marker, there must be // only whitespace or newline between the backslash and the // end of the string. char *eptr = lptr + 1; while (isspace(*eptr)) eptr++; if (*eptr == '\0') { result = fgets(lptr, LIB_LINE_MAX - (lptr - line), flib); fileCurrentLine++; if (result == NULL) break; } else lptr++; } else lptr++; } if (result == NULL) return NULL; lineptr = line; } if (commentblock == 1) continue; while (isspace(*lineptr)) lineptr++; if (concat == 0) tptr = token; // Find the next token and return just the token. Update linepos // to the position just beyond the token. All delimiters like // parentheses, quotes, etc., are returned as single tokens // If delimiter is declared, then we stop when we reach the // delimiter character, and return all the text preceding it // as the token. If delimiter is 0, then we look for standard // delimiters, and separate them out and return them as tokens // if found. while (1) { if (*lineptr == '\n' || *lineptr == '\0') break; if (*lineptr == '/' && *(lineptr + 1) == '*') break; if (delimiter != 0 && *lineptr == delimiter) { if (nest > 0) nest--; else break; } // Watch for nested delimiters! if (delimiter == '}' && *lineptr == '{') nest++; if (delimiter == ')' && *lineptr == '(') nest++; if (delimiter == 0) if (*lineptr == ' ' || *lineptr == '\t') break; if (delimiter == 0) { if (*lineptr == '(' || *lineptr == ')') { if (tptr == token) *tptr++ = *lineptr++; break; } if (*lineptr == '{' || *lineptr == '}') { if (tptr == token) *tptr++ = *lineptr++; break; } if (*lineptr == '\"' || *lineptr == ':' || *lineptr == ';') { if (tptr == token) *tptr++ = *lineptr++; break; } } *tptr++ = *lineptr++; } *tptr = '\0'; if ((delimiter != 0) && (*lineptr != delimiter)) concat = 1; else if ((delimiter != 0) && (*lineptr == delimiter)) break; else if (tptr > token) break; } if (delimiter != 0) lineptr++; while (isspace(*lineptr)) lineptr++; linepos = lineptr; // Final: Remove trailing whitespace tptr = token + strlen(token) - 1; while (isspace(*tptr)) { *tptr = '\0'; tptr--; } return token; } /*--------------------------------------------------------------*/ /* Parse a pin name. Check if the cell has a pin of that name, */ /* and if not, add the pin to the cell, giving it default */ /* values. The pin name may contain quotes, parentheses, or */ /* negations ("!" or "'"); these should be ignored. */ /*--------------------------------------------------------------*/ pinptr parse_pin(cellptr newcell, char *token, short sense_predef) { pinptr newpin, lastpin; char *pinname, *sptr; // Advance to first legal pin name character pinname = token; while (isspace(*pinname) || (*pinname == '\'') || (*pinname == '\"') || (*pinname == '!') || (*pinname == '(') || (*pinname == ')')) pinname++; sptr = pinname; while (*sptr != '\0') { if (isspace(*sptr) || (*sptr == '\'') || (*sptr == '\"') || (*sptr == '!') || (*sptr == '(') || (*sptr == ')')) { *sptr = '\0'; break; } sptr++; } // Check if pin was already defined lastpin = NULL; newpin = newcell->pins; while (newpin) { lastpin = newpin; if (!strcmp(newpin->name, pinname)) return newpin; newpin = newpin->next; } // Pin was not defined, so create a new one and add it to the cell // at the end of the cell's pin list. newpin = (pin *)malloc(sizeof(pin)); newpin->name = strdup(pinname); newpin->next = NULL; if (lastpin != NULL) lastpin->next = newpin; else newcell->pins = newpin; newpin->type = INPUT; // The default; modified later, if not an input newpin->capr = 0.0; newpin->capf = 0.0; newpin->sense = sense_predef; // Again, modified later if not true. newpin->propdelr = NULL; newpin->propdelf = NULL; newpin->transr = NULL; newpin->transf = NULL; newpin->refcell = newcell; // Create link back to cell return newpin; } /*--------------------------------------------------------------*/ /* Create a new net record */ /*--------------------------------------------------------------*/ netptr create_net(netptr *netlist) { netptr newnet; newnet = (netptr)malloc(sizeof(net)); newnet->name = NULL; newnet->next = *netlist; *netlist = newnet; newnet->driver = NULL; newnet->fanout = 0; newnet->receivers = NULL; newnet->loadr = 0.0; newnet->loadf = 0.0; newnet->type = NET; return newnet; } /*----------------------------------------------------------------------*/ /* Interpolate or extrapolate a vector from a time vs. capacitance */ /* lookup table. */ /*----------------------------------------------------------------------*/ double *table_collapse(lutableptr tableptr, double load) { double *vector; double cfrac, vlow, vhigh; int i, j; vector = (double *)malloc(tableptr->size1 * sizeof(double)); // If the table is 1-dimensional, then just return a copy of the table. if (tableptr->size2 <= 1) { for (i = 0; i < tableptr->size1; i++) { *(vector + i) = *(tableptr->values + i); } return vector; } // Find cap load index entries bounding "load", or the two nearest // entries, if extrapolating if (load < tableptr->idx2.caps[0]) j = 1; else if (load >= tableptr->idx2.caps[tableptr->size2 - 1]) j = tableptr->size2 - 1; else { for (j = 0; j < tableptr->size2; j++) if (tableptr->idx2.caps[j] > load) break; } cfrac = (load - tableptr->idx2.caps[j - 1]) / (tableptr->idx2.caps[j] - tableptr->idx2.caps[j - 1]); for (i = 0; i < tableptr->size1; i++) { // Interpolate value at cap load for each transition value vlow = *(tableptr->values + i * tableptr->size1 + (j - 1)); vhigh = *(tableptr->values + i * tableptr->size1 + j); *(vector + i) = vlow + (vhigh - vlow) * cfrac; } return vector; } /*----------------------------------------------------------------------*/ /* Interpolate/extrapolate a delay or transition value from a vector of */ /* values at a known output load. The original full 2D table contains */ /* the transition time index values. */ /*----------------------------------------------------------------------*/ double vector_get_value(lutableptr tableptr, double *vector, double trans) { int i; double tfrac, vlow, vhigh, value; // Find time index entries bounding "trans", or the two nearest // entries, if extrapolating if (trans < tableptr->idx1.times[0]) i = 1; else if (trans >= tableptr->idx1.times[tableptr->size1 - 1]) i = tableptr->size1 - 1; else { for (i = 0; i < tableptr->size1; i++) if (tableptr->idx1.times[i] > trans) break; } // Compute transition time as a fraction of the nearest table indexes // for transition times tfrac = (trans - tableptr->idx1.times[i - 1]) / (tableptr->idx1.times[i] - tableptr->idx1.times[i - 1]); // Interpolate value vlow = *(vector + (i - 1)); vhigh = *(vector + i); value = vlow + (vhigh - vlow) * tfrac; return value; } /*----------------------------------------------------------------------*/ /* Interpolate or extrapolate a value from a related time vs. */ /* constrained time lookup table. */ /*----------------------------------------------------------------------*/ double binomial_get_value(lutableptr tableptr, double rtrans, double ctrans) { int i, j; double rfrac, cfrac, vlow, vhigh, valuel, valueh, value; /* Tables have been arranged such that idx1 is related time, */ /* idx2 is constrained time */ // Find time index entries bounding "rtrans", or the two nearest // entries, if extrapolating if (rtrans < tableptr->idx1.rel[0]) i = 1; else if (rtrans >= tableptr->idx1.rel[tableptr->size1 - 1]) i = tableptr->size1 - 1; else { for (i = 0; i < tableptr->size1; i++) if (tableptr->idx1.rel[i] > rtrans) break; } // Compute transition time as a fraction of the nearest table indexes // for transition times rfrac = (rtrans - tableptr->idx1.rel[i - 1]) / (tableptr->idx1.rel[i] - tableptr->idx1.rel[i - 1]); // 1-dimensional computation, if this table is 1-dimensional if (tableptr->size2 == 0) { vlow = *(tableptr->values + (i - 1)); vhigh = *(tableptr->values + i); value = vlow + (vhigh - vlow) * rfrac; return value; } // Find cons index entries bounding "ctrans", or the two nearest // entries, if extrapolating if (ctrans < tableptr->idx2.cons[0]) j = 1; else if (ctrans >= tableptr->idx2.cons[tableptr->size2 - 1]) j = tableptr->size2 - 1; else { for (j = 0; j < tableptr->size2; j++) if (tableptr->idx2.cons[j] > ctrans) break; } // Compute cons transition as a fraction of the nearest table indexes for cons cfrac = (ctrans - tableptr->idx2.cons[j - 1]) / (tableptr->idx2.cons[j] - tableptr->idx2.cons[j - 1]); // Interpolate value at cons lower bound vlow = *(tableptr->values + (i - 1) * tableptr->size1 + (j - 1)); vhigh = *(tableptr->values + i * tableptr->size1 + (j - 1)); valuel = vlow + (vhigh - vlow) * rfrac; // Interpolate value at cons upper bound vlow = *(tableptr->values + (i - 1) * tableptr->size1 + j); vhigh = *(tableptr->values + i * tableptr->size1 + j); valueh = vlow + (vhigh - vlow) * rfrac; // Final interpolation (binomial interpolation) value = valuel + (valueh - valuel) * cfrac; return value; } /*----------------------------------------------------------------------*/ /* Determine how the sense of a signal changes going from a gate's */ /* input to its output. If the gate's input pin is positive unate */ /* relative to the gate output, then the signal sense remains the same. */ /* If it is negative unate, then the signal sense inverts. If it is */ /* non-unate, then the signal sense becomes non-unate, and we calculate */ /* timing for both edges from that point forward, always accepting the */ /* maximum time. */ /*----------------------------------------------------------------------*/ short calc_dir(pinptr testpin, short dir) { short outdir; outdir = UNKNOWN; if (testpin == NULL) return dir; switch(dir) { case RISING: if (testpin->sense == SENSE_POSITIVE) outdir = RISING; /* rising input, rising output */ else if (testpin->sense = SENSE_NEGATIVE) outdir = FALLING; /* rising input, falling output */ else outdir = EITHER; /* output can be rising or falling */ break; case FALLING: if (testpin->sense == SENSE_POSITIVE) outdir = FALLING; /* falling input, falling output */ else if (testpin->sense = SENSE_NEGATIVE) outdir = RISING; /* falling input, rising output */ else outdir = EITHER; /* output can be rising or falling */ break; case EITHER: outdir = EITHER; /* output can be rising or falling */ break; } return outdir; } /*----------------------------------------------------------------------*/ /* Calculate the propagation delay from "testpin" to the output */ /* of the gate to which "testpin" is an input. */ /* */ /* "sense" is a pointer to the sense at the input. SENSE_POSITIVE */ /* indicates a rising edge at the pin, SENSE_NEGATIVE indicates a */ /* falling edge at the pin. "sense" is updated to indicate if the */ /* output transition is rising, falling, or unknown (SENSE_NONE). */ /* */ /* "loadnet" is a pointer to the net connected to the cell instance's */ /* output pin. Load values will be taken from this net, depending on */ /* the sense of the output. */ /* */ /* "testpin" is the pin receiving the input signal, and the pin record */ /* containing the relevant timing tables. */ /*----------------------------------------------------------------------*/ double calc_prop_delay(double trans, connptr testconn, short sense, char minmax) { pinptr testpin; double propdelayr, propdelayf; propdelayr = 0.0; propdelayf = 0.0; testpin = testconn->refpin; if (testpin == NULL) return 0.0; if (sense != SENSE_NEGATIVE) { if (testconn->prvector) propdelayr = vector_get_value(testpin->propdelr, testconn->prvector, trans); if (sense == SENSE_POSITIVE) return propdelayr; } if (sense != SENSE_POSITIVE) { if (testconn->pfvector) propdelayf = vector_get_value(testpin->propdelf, testconn->pfvector, trans); if (sense == SENSE_NEGATIVE) return propdelayf; } if (minmax == MAXIMUM_TIME) return (propdelayr > propdelayf) ? propdelayr : propdelayf; else return (propdelayr < propdelayf) ? propdelayr : propdelayf; } /*----------------------------------------------------------------------*/ /* Calculate the transition time from "testpin" to the output */ /* of the gate to which "testpin" is an input. This is equivalent to */ /* the propagation delay calculation routine above, apart from using */ /* the lookup tables for transition time instead of propagation delay. */ /*----------------------------------------------------------------------*/ double calc_transition(double trans, connptr testconn, short sense, char minmax) { pinptr testpin; double transr, transf; testpin = testconn->refpin; if (testpin == NULL) return 0.0; transr = 0.0; transf = 0.0; if (sense != SENSE_NEGATIVE) { if (testconn->trvector) transr = vector_get_value(testpin->transr, testconn->trvector, trans); if (sense == SENSE_POSITIVE) return transr; } if (sense != SENSE_POSITIVE) { if (testconn->tfvector) transf = vector_get_value(testpin->transf, testconn->tfvector, trans); if (sense == SENSE_NEGATIVE) return transf; } if (minmax == MAXIMUM_TIME) return (transr > transf) ? transr : transf; else return (transr < transf) ? transr : transf; } /*----------------------------------------------------------------------*/ /* Calculate the hold time for a flop input "testpin" relative to the */ /* flop clock, where "trans" is the transition time of the signal at */ /* "testpin", and "clktrans" is the transition time of the clock */ /* signal at the clock pin. "sense" is the sense of the input signal */ /* at "testpin". */ /*----------------------------------------------------------------------*/ double calc_hold_time(double trans, pinptr testpin, double clktrans, short sense, char minmax) { double holdr, holdf; if (testpin == NULL) return 0.0; holdr = 0.0; holdf = 0.0; if (sense != SENSE_NEGATIVE) { if (testpin->transr) holdr = binomial_get_value(testpin->transr, trans, clktrans); if (sense == SENSE_POSITIVE) return holdr; } if (sense != SENSE_POSITIVE) { if (testpin->transf) holdf = binomial_get_value(testpin->transf, trans, clktrans); if (sense == SENSE_NEGATIVE) return holdf; } if (minmax == MAXIMUM_TIME) return (holdr > holdf) ? holdr : holdf; else return (holdr < holdf) ? holdr : holdf; } /*----------------------------------------------------------------------*/ /* Calculate the setup time for a flop input "testpin" relative to the */ /* flop clock, where "trans" is the transition time of the signal at */ /* "testpin", and "clktrans" is the transition time of the clock */ /* signal at the clock pin. "sense" is the sense of the input signal */ /* at "testpin". */ /*----------------------------------------------------------------------*/ double calc_setup_time(double trans, pinptr testpin, double clktrans, short sense, char minmax) { double setupr, setupf; if (testpin == NULL) return 0.0; setupr = 0.0; setupf = 0.0; if (sense != SENSE_NEGATIVE) { if (testpin->propdelr) setupr = binomial_get_value(testpin->propdelr, trans, clktrans); if (sense == SENSE_POSITIVE) return setupr; } if (sense != SENSE_POSITIVE) { if (testpin->propdelf) setupf = binomial_get_value(testpin->propdelf, trans, clktrans); if (sense == SENSE_NEGATIVE) return setupf; } if (minmax == MAXIMUM_TIME) return (setupr > setupf) ? setupr : setupf; else return (setupr < setupf) ? setupr : setupf; } /*--------------------------------------------------------------*/ /* Find the path from a clock back to all inputs or flop */ /* outputs. This list will be used to find nodes that are */ /* common to other clocks. */ /*--------------------------------------------------------------*/ void find_clock_source(connptr testlink, btptr *clocklist, short dir) { netptr clknet; connptr driver, iinput; instptr iupstream; btptr newclock; short newdir; /* Add this connection record to clocklist */ newclock = (btptr)malloc(sizeof(btdata)); newclock->delay = 0.0; newclock->trans = 0.0; newclock->dir = dir; newclock->refcnt = 1; newclock->receiver = testlink; newclock->next = *clocklist; *clocklist = newclock; clknet = testlink->refnet; driver = clknet->driver; if (driver == NULL) return; /* Reached a module input */ iupstream = driver->refinst; if (iupstream == NULL) return; /* Not supposed to happen? */ if (driver->refpin->type & DFFOUT) return; /* Reached a flop output */ if (driver->refpin->type & LATCHOUT) return; /* Reached a latch output */ for (iinput = iupstream->in_connects; iinput; iinput = iinput->next) { newdir = calc_dir(iinput->refpin, dir); find_clock_source(iinput, clocklist, newdir); } } /*--------------------------------------------------------------*/ /* Find a net that is common to both "clocklist" and */ /* "clock2list". If one exists, return a pointer to the */ /* connection. */ /*--------------------------------------------------------------*/ netptr find_common_clock(btptr clocklist, btptr clock2list) { btptr srch1ptr, srch2ptr; for (srch1ptr = clocklist; srch1ptr; srch1ptr = srch1ptr->next) for (srch2ptr = clock2list; srch2ptr; srch2ptr = srch2ptr->next) if (srch1ptr->receiver->refnet == srch2ptr->receiver->refnet) return srch1ptr->receiver->refnet; return NULL; } /*--------------------------------------------------------------*/ /* Determine the delay to a clock pin from the farthest point */ /* back in the network, either to an input pin or the output of */ /* another flop (e.g., a ripple counter). If there is more */ /* than one such source (which can happen with, say, a gated */ /* clock, because this routine will not differentiate between */ /* the clock signal and the gating signal), then all sources */ /* recorded (it is only necessary to find a common root of all */ /* other related clocks downstream). */ /* */ /* This is a recursive routine, continuing to find all delays */ /* through the circuit until it reaches "terminal". The */ /* "delaylist" linked list is not modified by this routine. */ /*--------------------------------------------------------------*/ void find_clock_delay(int dir, double delay, double trans, connptr receiver, btptr clocklist, connptr terminal, char minmax) { pinptr testpin; netptr loadnet; cellptr testcell; instptr testinst; btptr testbtdata, newbtdata; double newdelayr, newdelayf, newtransr, newtransf; short outdir; int i; testpin = receiver->refpin; // Stop when receiver matches terminal. if (receiver != terminal) { testinst = receiver->refinst; testcell = (testpin) ? testpin->refcell : NULL; // Don't follow signal through any DFF pins if (testcell && (testcell->type & DFF)) return; // Compute delay from gate input to output outdir = calc_dir(testpin, dir); if (outdir & RISING) { newdelayr = delay + calc_prop_delay(trans, receiver, RISING, minmax); newtransr = calc_transition(trans, receiver, RISING, minmax); } if (outdir & FALLING) { newdelayf = delay + calc_prop_delay(trans, receiver, FALLING, minmax); newtransf = calc_transition(trans, receiver, FALLING, minmax); } loadnet = (testinst) ? testinst->out_connects->refnet : NULL; if (loadnet != NULL) { for (i = 0; i < loadnet->fanout; i++) { if (outdir & RISING) find_clock_delay(RISING, newdelayr, newtransr, loadnet->receivers[i], clocklist, terminal, minmax); if (outdir & FALLING) find_clock_delay(FALLING, newdelayf, newtransf, loadnet->receivers[i], clocklist, terminal, minmax); } } } else { /* Determine if receiver is in clocklist */ for (testbtdata = clocklist; testbtdata; testbtdata = testbtdata->next) { if (testbtdata->receiver == receiver) { /* Is delay greater than that already recorded? If so, replace it */ if (minmax == MAXIMUM_TIME) { if (delay > testbtdata->delay) { testbtdata->delay = delay; testbtdata->trans = trans; testbtdata->dir = dir; } } else { if (delay < testbtdata->delay) { testbtdata->delay = delay; testbtdata->trans = trans; testbtdata->dir = dir; } } break; } } } } /*--------------------------------------------------------------*/ /* Determine the delay from input to output through a gate */ /* */ /* This is a recursive routine, continuing to find all delays */ /* through the circuit until it reaches a terminal or flop */ /* input. It is similar to find_clock_delay, but stops on all */ /* terminal points found in the path, rather than stopping on */ /* a specific connection. */ /* */ /* Also unlike find_clock_delay, the routine keeps a running */ /* record of the path followed from the source, as a character */ /* string. When a terminal is found, the path and delay are */ /* saved and added to "delaylist". After the recursive search, */ /* "delaylist" contains a list of all paths starting from the */ /* original connection "receiver" and ending on a clock or an */ /* output pin. Where multiple paths exist between source and */ /* destination, only the path with the longest delay is kept. */ /* */ /* Return the number of new paths recorded. */ /*--------------------------------------------------------------*/ int find_path_delay(int dir, double delay, double trans, connptr receiver, btptr backtrace, ddataptr *delaylist, char minmax) { pinptr testpin; netptr loadnet; cellptr testcell; instptr testinst; btptr newbtdata, freebt, testbt; ddataptr testddata, newddata; double newdelayr, newdelayf, newtransr, newtransf; short outdir; char replace; int i, numpaths; numpaths = 0; testpin = receiver->refpin; // Prevent exhaustive search by stopping on a metric. Note that the // nonlinear table-based delay data requires an exhaustive search; // generally, the tables can be assumed to be monotonic, in which case // we can stop if the delay is less than the greatest delay recorded // at this point AND the transition time is less than the transition // time recorded along with that delay. A more relaxed metric is to // use the delay plus the transition time, and an even more relaxed // metric is to use only the delay. Any relaxing of the metric // implies that the final result may not be the absolute maximum delay, // although it will typically vary by less than an average gate delay. if (!exhaustive) { if (minmax == MAXIMUM_TIME) { if (delay <= receiver->metric) return numpaths; } else { if (delay >= receiver->metric) return numpaths; } } // Check for a logic loop, and truncate the path to avoid infinite // looping in the path search. if (receiver->tag == (ddataptr)(-1)) return numpaths; else if (receiver->tag == NULL) receiver->tag = (ddataptr)(-1); // Record this position and delay/transition information newbtdata = (btptr)malloc(sizeof(btdata)); newbtdata->delay = delay; newbtdata->trans = trans; newbtdata->dir = dir; newbtdata->receiver = receiver; newbtdata->refcnt = 1; newbtdata->next = backtrace; // Stop when we hit a module output pin or any flop/latch input. // We must allow the routine to pass through the 1st register clock (on the first // time through, backtrace is NULL). if ((backtrace == NULL) || (testpin && ((testpin->type & REGISTER_IN) == 0))) { testinst = receiver->refinst; testcell = (testpin) ? testpin->refcell : NULL; // Compute delay from gate input to output outdir = calc_dir(testpin, dir); if (outdir & RISING) { newdelayr = delay + calc_prop_delay(trans, receiver, RISING, minmax); newtransr = calc_transition(trans, receiver, RISING, minmax); } if (outdir & FALLING) { newdelayf = delay + calc_prop_delay(trans, receiver, FALLING, minmax); newtransf = calc_transition(trans, receiver, FALLING, minmax); } loadnet = (testinst) ? testinst->out_connects->refnet : receiver->refnet; for (i = 0; i < loadnet->fanout; i++) { if (outdir & RISING) numpaths += find_path_delay(RISING, newdelayr, newtransr, loadnet->receivers[i], newbtdata, delaylist, minmax); if (outdir & FALLING) numpaths += find_path_delay(FALLING, newdelayf, newtransf, loadnet->receivers[i], newbtdata, delaylist, minmax); } receiver->tag = NULL; } else { /* Is receiver already in delaylist? */ if ((receiver->tag != (ddataptr)(-1)) && (receiver->tag != NULL)) { /* Position in delaylist is recorded in tag field */ testddata = receiver->tag; if (testddata->backtrace->receiver == receiver) { replace = 0; if (minmax == MAXIMUM_TIME) { /* Is delay greater than that already recorded? If so, replace it */ if (delay > testddata->backtrace->delay) replace = 1; } else { /* Is delay less than that already recorded? If so, replace it */ if (delay < testddata->backtrace->delay) replace = 1; } if (replace) { /* Remove the existing path record and replace it */ while (testddata->backtrace != NULL) { freebt = testddata->backtrace; testddata->backtrace = testddata->backtrace->next; freebt->refcnt--; if (freebt->refcnt <= 0) free(freebt); } testddata->backtrace = newbtdata; /* Increment the refcounts along the backtrace */ for (testbt = newbtdata; testbt; testbt = testbt->next) testbt->refcnt++; } } else fprintf(stderr, "ERROR: Bad endpoint tag!\n"); } else testddata = NULL; // If we have found a propagation path from source to dest, // record it in delaylist. if (testddata == NULL) { numpaths++; newddata = (ddataptr)malloc(sizeof(delaydata)); newddata->delay = 0.0; newddata->trans = 0.0; newddata->backtrace = newbtdata; newddata->next = *delaylist; *delaylist = newddata; /* Mark the receiver as having been visited */ receiver->tag = *delaylist; /* Increment the refcounts along the backtrace */ for (testbt = newbtdata; testbt; testbt = testbt->next) testbt->refcnt++; } } receiver->metric = delay; newbtdata->refcnt--; if (newbtdata->refcnt <= 0) free(newbtdata); return numpaths; } /*--------------------------------------------------------------*/ /* Search the list "clocklist" for all points that are module */ /* inputs or flop outputs, and compute the worst-case */ /* transition time downstream at testlink. */ /* */ /* Return a pointer to the ddataptr entry that contains the */ /* worst-case transition time. */ /*--------------------------------------------------------------*/ btptr find_clock_transition(btptr clocklist, connptr testlink, short dir, char minmax) { btptr testclock, testlinkptr, resetclock; connptr testconn; double tdriver; // Find out where testlink is in clocklist, and save the position. for (testclock = clocklist; testclock; testclock = testclock->next) { if (testclock->receiver == testlink) { testlinkptr = testclock; break; } } if (testclock == NULL) return NULL; // Error---testlink wasn't in clocklist! for (testclock = clocklist; testclock; testclock = testclock->next) { testconn = testclock->receiver; tdriver = 0.0; // to-do: set to default input transition time find_clock_delay(testlinkptr->dir, 0.0, tdriver, testconn, clocklist, testlink, minmax); } // Return the linkptr containing the recorded transition time from // source to destination clock pins return testlinkptr; } /*--------------------------------------------------------------*/ /* Given an instance record, find the pin of the instance that */ /* is the clock, if the instance is a flop. If the instance is */ /* not a flop, return NULL. */ /*--------------------------------------------------------------*/ connptr find_register_clock(instptr testinst) { connptr testconn; for (testconn = testinst->in_connects; testconn; testconn = testconn->next) if (testconn->refpin && (testconn->refpin->type & DFFCLK)) return testconn; return NULL; } /*--------------------------------------------------------------*/ /* Given an edge direction (RISING or FALLING) at a source net, */ /* and given a destination net, find the sense of the signal */ /* when it arrives at the destination net. */ /*--------------------------------------------------------------*/ short find_edge_dir(short dir, netptr sourcenet, netptr destnet) { int i; short outdir, rdir; connptr testconn, nextconn; instptr testinst; netptr nextnet; for (i = 0; i < sourcenet->fanout; i++) { testconn = sourcenet->receivers[i]; testinst = testconn->refinst; if (testinst == NULL) continue; if (testconn->refpin == NULL) continue; if ((testconn->refpin->type & REGISTER_IN) != 0) continue; nextconn = testinst->out_connects; nextnet = nextconn->refnet; outdir = calc_dir(testconn->refpin, dir); if (nextnet == destnet) return outdir; rdir = find_edge_dir(outdir, nextnet, destnet); if (rdir != 0) return rdir; } return 0; } /*--------------------------------------------------------------*/ /* Search all paths from the clocked data outputs of */ /* "clockedlist" to either output pins or data inputs of other */ /* flops. */ /* */ /* Return a master list of all backtraces in "masterlist". */ /* */ /* Return value is the number of paths recorded in masterlist. */ /* */ /* If minmax == MAXIMUM_TIME, return the maximum delay. */ /* If minmax == MINIMUM_TIME, return the minimum delay. */ /*--------------------------------------------------------------*/ int find_clock_to_term_paths(connlistptr clockedlist, ddataptr *masterlist, netptr netlist, char minmax) { netptr commonclock, testnet; connptr testconn, thisconn; connlistptr testlink; pinptr testpin; cellptr testcell; instptr testinst; btptr clocklist, clock2list, backtrace, freebt; btptr selectedsource, selecteddest; ddataptr delaylist, testddata; ddataptr freeddata; short srcdir, destdir; // Signal direction in/out double tdriver, setupdelay, holddelay; char clk_sense_inv, clk_invert; int numpaths, n, i; delaylist = NULL; clocklist = NULL; clock2list = NULL; numpaths = 0; for (testlink = clockedlist; testlink; testlink = testlink->next) { // Remove all tags and reset delay metrics before each run for (testnet = netlist; testnet; testnet = testnet->next) { for (i = 0; i < testnet->fanout; i++) { testconn = testnet->receivers[i]; testconn->tag = NULL; if (minmax == MAXIMUM_TIME) testconn->metric = -1.0; else testconn->metric = 1E50; } } thisconn = testlink->connection; testpin = thisconn->refpin; if (testpin) { testcell = testpin->refcell; // Sense is positive for rising edge-triggered flops, negative for // falling edge-triggered flops srcdir = (testcell->type & CLK_SENSE_MASK) ? FALLING : RISING; // Find the sources of the clock at the path start find_clock_source(thisconn, &clocklist, srcdir); // Find the clock source with the worst-case transition time at testlink // (Note: For maximum path delay, find minimum clock transistion, and vice versa) selectedsource = find_clock_transition(clocklist, thisconn, srcdir, ~minmax); if (selectedsource == NULL) tdriver = 0.0; else tdriver = selectedsource->trans; // Report on paths and their maximum delays if (verbose > 0) fprintf(stdout, "Paths starting at flop \"%s\" clock:\n\n", thisconn->refinst->name); } else { // Connection is an input pin; must calculate both rising and falling edges. srcdir = EITHER; tdriver = 0.0; // To-do: use designated input transition time // Report on paths and their maximum delays if (verbose > 0) fprintf(stdout, "Paths starting at input pin \"%s\"\n\n", thisconn->refnet->name); } if (verbose > 0) fflush(stdout); // Find all paths from "thisconn" to output or a flop input, and compute delay n = find_path_delay(srcdir, 0.0, tdriver, thisconn, NULL, &delaylist, minmax); numpaths += n; if (verbose > 0) fprintf(stdout, "%d paths traced (%d total).\n\n", n, numpaths); for (testddata = delaylist; testddata; testddata = testddata->next) { // Copy last backtrace delay to testddata. testddata->delay = testddata->backtrace->delay; testddata->trans = testddata->backtrace->trans; testinst = testddata->backtrace->receiver->refinst; if (testinst != NULL) { // Find the sources of the clock at the path end destdir = (testinst->refcell->type & CLK_SENSE_MASK) ? FALLING : RISING; testconn = find_register_clock(testinst); find_clock_source(testconn, &clock2list, destdir); selecteddest = find_clock_transition(clock2list, testconn, destdir, ~minmax); // Find the connection that is common to both clocks commonclock = find_common_clock(clocklist, clock2list); if (commonclock == NULL) { // Warn about asynchronous clock sources if (verbose > 0) { fflush(stdout); fprintf(stderr, "Independent clock nets \"%s\" and \"%s\"" " drive related gates!\n", testconn->refnet->name, thisconn->refnet->name); } clk_invert = -1; } else { // Add or subtract difference in arrival times between source and // destination clocks if (selecteddest != NULL && selectedsource != NULL) { testddata->delay += selecteddest->delay; testddata->delay -= selectedsource->delay; /* Check if the clock signal arrives at both flops with the */ /* same edge type (both rising or both falling). */ clk_invert = (find_edge_dir(RISING, commonclock, selectedsource->receiver->refnet) == find_edge_dir(RISING, commonclock, selecteddest->receiver->refnet)) ? 0 : 1; } if (minmax == MAXIMUM_TIME) { // Add setup time for destination clocks setupdelay = calc_setup_time(testddata->trans, testddata->backtrace->receiver->refpin, selecteddest->trans, testddata->backtrace->dir, minmax); testddata->delay += setupdelay; } else { // Subtract hold time for destination clocks holddelay = calc_hold_time(testddata->trans, testddata->backtrace->receiver->refpin, selecteddest->trans, testddata->backtrace->dir, minmax); testddata->delay -= holddelay; } if (verbose > 0) fprintf(stdout, "Path terminated on flop \"%s\" input with max delay %g ps\n", testconn->refinst->name, testddata->delay); for (backtrace = testddata->backtrace; backtrace->next; backtrace = backtrace->next) { if (verbose > 0) fprintf(stdout, " %g (%s) %s/%s -> %s/%s\n", backtrace->delay, backtrace->receiver->refnet->name, backtrace->receiver->refnet->driver->refinst->name, backtrace->receiver->refnet->driver->refpin->name, backtrace->receiver->refinst->name, backtrace->receiver->refpin->name); } if (verbose > 0) fprintf(stdout, " 000.000 (%s) %s/%s -> %s/%s\n", backtrace->receiver->refnet->name, backtrace->receiver->refinst->name, backtrace->receiver->refpin->name, backtrace->receiver->refinst->name, backtrace->receiver->refinst->out_connects->refpin->name); if (selecteddest != NULL && selectedsource != NULL) { if (verbose > 0) { if (selectedsource->receiver->refnet != selecteddest->receiver->refnet) { fprintf(stdout, " %g %s to %s clock skew\n", selecteddest->delay - selectedsource->delay, selectedsource->receiver->refnet->name, selecteddest->receiver->refnet->name); } } /* Check if the flops have the same clock sense */ /* (both are clock rising edge or both are clock falling edge type) */ if ((testinst->refcell->type & CLK_SENSE_MASK) != (backtrace->receiver->refinst->refcell->type & CLK_SENSE_MASK)) clk_sense_inv = 1; else clk_sense_inv = 0; /* If the two flops don't clock at the same time, then issue a */ /* warning that the slack time loses half a clock period. */ if ((verbose > 0) && (clk_invert != -1) && (clk_sense_inv != clk_invert)) { fprintf(stdout, " Clocks are inverted relative to one another,\n"); fprintf(stdout, " implying a maximum propagation delay of 1/2 period.\n"); } } if (selecteddest != NULL && selectedsource != NULL) { if (verbose > 0) { if (minmax == MAXIMUM_TIME) fprintf(stdout, " %g setup time at destination\n", setupdelay); else fprintf(stdout, " %g hold time at destination\n", holddelay); } } if (verbose > 0) fprintf(stdout, "\n"); } } else if (verbose > 0) { fprintf(stdout, "Path terminated on output \"%s\" with max delay %g ps\n", testddata->backtrace->receiver->refnet->name, testddata->delay); backtrace = testddata->backtrace; fprintf(stdout, " %g (%s) %s/%s -> [output pin]\n", backtrace->delay, backtrace->receiver->refnet->name, backtrace->receiver->refnet->driver->refinst->name, backtrace->receiver->refnet->driver->refpin->name); for (backtrace = backtrace->next; backtrace->next; backtrace = backtrace->next) { fprintf(stdout, " %g (%s) %s/%s -> %s/%s\n", backtrace->delay, backtrace->receiver->refnet->name, backtrace->receiver->refnet->driver->refinst->name, backtrace->receiver->refnet->driver->refpin->name, backtrace->receiver->refinst->name, backtrace->receiver->refpin->name); } fprintf(stdout, " 000.000 (%s) %s/%s -> %s/%s\n\n", backtrace->receiver->refnet->name, backtrace->receiver->refinst->name, backtrace->receiver->refpin->name, backtrace->receiver->refinst->name, backtrace->receiver->refinst->out_connects->refpin->name); } // Clean up clock2list while (clock2list != NULL) { freebt = clock2list; clock2list = clock2list->next; free(freebt); } } // Link delaylist data to the beginning of masterlist, and null out // delaylist for the next set of paths. if (delaylist) { for (testddata = delaylist; testddata->next; testddata = testddata->next); testddata->next = *masterlist; *masterlist = delaylist; delaylist = NULL; } // Free up clocklist while (clocklist != NULL) { freebt = clocklist; clocklist = clocklist->next; free(freebt); } } return numpaths; } /*--------------------------------------------------------------*/ /* Parse a table variable type from a liberty format file */ /*--------------------------------------------------------------*/ int get_table_type(char *token) { if (!strcasecmp(token, "input_net_transition")) return TRANSITION_TIME; else if (!strcasecmp(token, "total_output_net_capacitance")) return OUTPUT_CAP; else if (!strcasecmp(token, "related_pin_transition")) return RELATED_TIME; else if (!strcasecmp(token, "constrained_pin_transition")) return CONSTRAINED_TIME; else return UNKNOWN; } /*--------------------------------------------------------------*/ /* Read a liberty format file and collect information about */ /* the timing properties of each standard cell. */ /*--------------------------------------------------------------*/ void libertyRead(FILE *flib, lutable **tablelist, cell **celllist) { char *token; char *libname = NULL; int section = INIT; double time_unit = 1.0; // Time unit multiplier, to get ps double cap_unit = 1.0; // Capacitive unit multiplier, to get fF pinptr testpin; lutable *tableptr; int i, j; double gval; char *iptr; short timing_type, sense_type; lutable *newtable, *reftable; cell *newcell, *lastcell; pin *newpin; lastcell = NULL; timing_type = UNKNOWN; /* Read tokens off of the line */ token = advancetoken(flib, 0); while (token != NULL) { switch (section) { case INIT: if (!strcasecmp(token, "library")) { token = advancetoken(flib, 0); if (strcmp(token, "(")) fprintf(stderr, "Library not followed by name\n"); else token = advancetoken(flib, ')'); fprintf(stderr, "Parsing library \"%s\"\n", token); libname = strdup(token); token = advancetoken(flib, 0); if (strcmp(token, "{")) { fprintf(stderr, "Did not find opening brace " "on library block\n"); exit(1); } section = LIBBLOCK; } else fprintf(stderr, "Unknown input \"%s\", looking for " "\"library\"\n", token); break; case LIBBLOCK: // Here we check for the main blocks, again not rigorously. . . if (!strcasecmp(token, "}")) { fprintf(stdout, "End of library at line %d\n", fileCurrentLine); section = INIT; // End of library block } else if (!strcasecmp(token, "delay_model")) { token = advancetoken(flib, 0); if (strcmp(token, ":")) fprintf(stderr, "Input missing colon\n"); token = advancetoken(flib, ';'); if (strcasecmp(token, "table_lookup")) { fprintf(stderr, "Sorry, only know how to " "handle table lookup!\n"); exit(1); } } else if (!strcasecmp(token, "lu_table_template") || !strcasecmp(token, "power_lut_template")) { // Read in template information; newtable = (lutable *)malloc(sizeof(lutable)); newtable->name = NULL; newtable->invert = 0; newtable->var1 = UNKNOWN; newtable->var2 = UNKNOWN; newtable->size1 = 0; newtable->size2 = 0; newtable->idx1.times = NULL; newtable->idx2.caps = NULL; newtable->values = NULL; newtable->next = *tablelist; *tablelist = newtable; token = advancetoken(flib, 0); if (strcmp(token, "(")) fprintf(stderr, "Input missing open parens\n"); else token = advancetoken(flib, ')'); newtable->name = strdup(token); while (*token != '}') { token = advancetoken(flib, 0); if (!strcasecmp(token, "variable_1")) { token = advancetoken(flib, 0); token = advancetoken(flib, ';'); newtable->var1 = get_table_type(token); if (newtable->var1 == OUTPUT_CAP || newtable->var1 == CONSTRAINED_TIME) newtable->invert = 1; } else if (!strcasecmp(token, "variable_2")) { token = advancetoken(flib, 0); token = advancetoken(flib, ';'); newtable->var2 = get_table_type(token); if (newtable->var2 == TRANSITION_TIME || newtable->var2 == RELATED_TIME) newtable->invert = 1; } else if (!strcasecmp(token, "index_1")) { token = advancetoken(flib, 0); // Open parens token = advancetoken(flib, 0); // Quote if (!strcmp(token, "\"")) token = advancetoken(flib, '\"'); if (newtable->invert == 1) { // Count entries iptr = token; newtable->size2 = 1; while ((iptr = strchr(iptr, ',')) != NULL) { iptr++; newtable->size2++; } newtable->idx2.caps = (double *)malloc(newtable->size2 * sizeof(double)); newtable->size2 = 0; iptr = token; sscanf(iptr, "%lg", &newtable->idx2.caps[0]); if (newtable->var2 == OUTPUT_CAP) newtable->idx2.caps[0] *= cap_unit; else newtable->idx2.caps[0] *= time_unit; while ((iptr = strchr(iptr, ',')) != NULL) { iptr++; newtable->size2++; sscanf(iptr, "%lg", &newtable->idx2.caps[newtable->size2]); if (newtable->var2 == OUTPUT_CAP) newtable->idx2.caps[newtable->size2] *= cap_unit; else newtable->idx2.cons[newtable->size2] *= time_unit; } newtable->size2++; } else { // newtable->invert = 0 // Count entries iptr = token; newtable->size1 = 1; while ((iptr = strchr(iptr, ',')) != NULL) { iptr++; newtable->size1++; } newtable->idx1.times = (double *)malloc(newtable->size1 * sizeof(double)); newtable->size1 = 0; iptr = token; sscanf(iptr, "%lg", &newtable->idx1.times[0]); newtable->idx1.times[0] *= time_unit; while ((iptr = strchr(iptr, ',')) != NULL) { iptr++; newtable->size1++; sscanf(iptr, "%lg", &newtable->idx1.times[newtable->size1]); newtable->idx1.times[newtable->size1] *= time_unit; } newtable->size1++; } token = advancetoken(flib, ';'); // EOL semicolon } else if (!strcasecmp(token, "index_2")) { token = advancetoken(flib, 0); // Open parens token = advancetoken(flib, 0); // Quote if (!strcmp(token, "\"")) token = advancetoken(flib, '\"'); if (newtable->invert == 0) { // Count entries iptr = token; newtable->size2 = 1; while ((iptr = strchr(iptr, ',')) != NULL) { iptr++; newtable->size2++; } newtable->idx2.caps = (double *)malloc(newtable->size2 * sizeof(double)); newtable->size2 = 0; iptr = token; sscanf(iptr, "%lg", &newtable->idx2.caps[0]); if (newtable->var2 == OUTPUT_CAP) newtable->idx2.caps[0] *= cap_unit; else newtable->idx2.cons[0] *= time_unit; while ((iptr = strchr(iptr, ',')) != NULL) { iptr++; newtable->size2++; sscanf(iptr, "%lg", &newtable->idx2.caps[newtable->size2]); if (newtable->var2 == OUTPUT_CAP) newtable->idx2.caps[newtable->size2] *= cap_unit; else newtable->idx2.cons[newtable->size2] *= time_unit; } newtable->size2++; } else { // newtable->invert == 1 // Count entries iptr = token; newtable->size1 = 1; while ((iptr = strchr(iptr, ',')) != NULL) { iptr++; newtable->size1++; } newtable->idx1.times = (double *)malloc(newtable->size1 * sizeof(double)); newtable->size1 = 0; iptr = token; sscanf(iptr, "%lg", &newtable->idx1.times[0]); newtable->idx1.times[0] *= time_unit; while ((iptr = strchr(iptr, ',')) != NULL) { iptr++; newtable->size1++; sscanf(iptr, "%lg", &newtable->idx1.times[newtable->size1]); newtable->idx1.times[newtable->size1] *= time_unit; } newtable->size1++; } token = advancetoken(flib, ';'); // EOL semicolon } } } else if (!strcasecmp(token, "cell")) { newcell = (cell *)malloc(sizeof(cell)); newcell->next = NULL; if (lastcell != NULL) lastcell->next = newcell; else *celllist = newcell; lastcell = newcell; token = advancetoken(flib, 0); // Open parens if (!strcmp(token, "(")) token = advancetoken(flib, ')'); // Cellname newcell->name = strdup(token); token = advancetoken(flib, 0); // Find start of block if (strcmp(token, "{")) fprintf(stderr, "Error: failed to find start of block\n"); newcell->type = GATE; // Default type newcell->function = NULL; newcell->pins = NULL; newcell->area = 1.0; newcell->maxtrans = 0.0; newcell->maxcap = 0.0; section = CELLDEF; } else if (!strcasecmp(token, "time_unit")) { char *metric; token = advancetoken(flib, 0); if (token == NULL) break; if (!strcmp(token, ":")) { token = advancetoken(flib, 0); if (token == NULL) break; } if (!strcmp(token, "\"")) { token = advancetoken(flib, '\"'); if (token == NULL) break; } time_unit = strtod(token, &metric); if (*metric != '\0') { if (!strcmp(metric, "ns")) time_unit *= 1E3; else if (!strcmp(metric, "us")) time_unit *= 1E6; else if (!strcmp(metric, "fs")) time_unit *= 1E-3; else if (strcmp(metric, "ps")) fprintf(stderr, "Don't understand time units \"%s\"\n", token); } else { token = advancetoken(flib, 0); if (token == NULL) break; if (!strcmp(token, "ns")) time_unit *= 1E3; else if (!strcmp(token, "us")) time_unit *= 1E6; else if (!strcmp(token, "fs")) time_unit *= 1E-3; else if (strcmp(token, "ps")) fprintf(stderr, "Don't understand time units \"%s\"\n", token); } token = advancetoken(flib, ';'); } else if (!strcasecmp(token, "capacitive_load_unit")) { char *metric; token = advancetoken(flib, 0); if (token == NULL) break; if (!strcmp(token, "(")) { token = advancetoken(flib, ')'); if (token == NULL) break; } cap_unit = strtod(token, &metric); if (*metric != '\0') { while (isspace(*metric)) metric++; if (*metric == ',') metric++; while ((*metric != '\0') && isspace(*metric)) metric++; if (!strcasecmp(metric, "af")) cap_unit *= 1E-3; else if (!strcasecmp(metric, "pf")) cap_unit *= 1000; else if (!strcasecmp(metric, "nf")) cap_unit *= 1E6; else if (!strcasecmp(metric, "uf")) cap_unit *= 1E9; else if (strcasecmp(metric, "ff")) fprintf(stderr, "Don't understand capacitive units \"%s\"\n", token); } else { token = advancetoken(flib, 0); if (token == NULL) break; if (!strcasecmp(token, "af")) cap_unit *= 1E-3; else if (!strcasecmp(token, "pf")) cap_unit *= 1000; else if (!strcasecmp(token, "nf")) cap_unit *= 1E6; else if (!strcasecmp(token, "uf")) cap_unit *= 1E9; else if (strcasecmp(token, "ff")) fprintf(stderr, "Don't understand capacitive units \"%s\"\n", token); } token = advancetoken(flib, ';'); } else { // For unhandled tokens, read in tokens. If it is // a definition or function, read to end-of-line. If // it is a block definition, read to end-of-block. while (1) { token = advancetoken(flib, 0); if (token == NULL) break; if (!strcmp(token, ";")) break; if (!strcmp(token, "\"")) token = advancetoken(flib, '\"'); if (!strcmp(token, "{")) { token = advancetoken(flib, '}'); break; } } } break; case CELLDEF: if (!strcmp(token, "}")) { section = LIBBLOCK; // End of cell def } else if (!strcasecmp(token, "pin")) { token = advancetoken(flib, 0); // Open parens if (!strcmp(token, "(")) token = advancetoken(flib, ')'); // Close parens newpin = parse_pin(newcell, token, SENSE_NONE); token = advancetoken(flib, 0); // Find start of block if (strcmp(token, "{")) fprintf(stderr, "Error: failed to find start of block\n"); section = PINDEF; } else if (!strcasecmp(token, "area")) { token = advancetoken(flib, 0); // Colon token = advancetoken(flib, ';'); // To end-of-statement sscanf(token, "%lg", &newcell->area); } else if (!strcasecmp(token, "ff")) { newcell->type |= DFF; token = advancetoken(flib, '{'); section = FLOPDEF; } else if (!strcasecmp(token, "latch")) { newcell->type |= LATCH; token = advancetoken(flib, '{'); section = LATCHDEF; } else { // For unhandled tokens, read in tokens. If it is // a definition or function, read to end-of-line. If // it is a block definition, read to end-of-block. while (1) { token = advancetoken(flib, 0); if (token == NULL) break; if (!strcmp(token, ";")) break; if (!strcmp(token, "\"")) token = advancetoken(flib, '\"'); if (!strcmp(token, "(")) token = advancetoken(flib, ')'); if (!strcmp(token, "{")) { token = advancetoken(flib, '}'); break; } } } break; case FLOPDEF: if (!strcmp(token, "}")) { section = CELLDEF; // End of flop def } else if (!strcasecmp(token, "next_state")) { token = advancetoken(flib, 0); // Colon token = advancetoken(flib, ';'); // To end-of-statement newpin = parse_pin(newcell, token, SENSE_NONE); newpin->type |= DFFIN; } else if (!strcasecmp(token, "clocked_on")) { token = advancetoken(flib, 0); // Colon token = advancetoken(flib, ';'); // To end-of-statement if (strchr(token, '\'') != NULL) newcell->type |= CLK_SENSE_MASK; else if (strchr(token, '!') != NULL) newcell->type |= CLK_SENSE_MASK; newpin = parse_pin(newcell, token, SENSE_NONE); newpin->type |= DFFCLK; } else if (!strcasecmp(token, "clear")) { newcell->type |= RST_MASK; token = advancetoken(flib, 0); // Colon token = advancetoken(flib, ';'); // To end-of-statement if (strchr(token, '\'') != NULL) newcell->type |= RST_SENSE_MASK; else if (strchr(token, '!') != NULL) newcell->type |= RST_SENSE_MASK; newpin = parse_pin(newcell, token, SENSE_NONE); newpin->type |= DFFRST; } else if (!strcasecmp(token, "preset")) { newcell->type |= SET_MASK; token = advancetoken(flib, 0); // Colon token = advancetoken(flib, ';'); // To end-of-statement if (strchr(token, '\'') != NULL) newcell->type |= SET_SENSE_MASK; else if (strchr(token, '!') != NULL) newcell->type |= SET_SENSE_MASK; newpin = parse_pin(newcell, token, SENSE_NONE); newpin->type |= DFFSET; } else token = advancetoken(flib, ';'); // Read to end-of-statement break; case LATCHDEF: if (!strcmp(token, "}")) { section = CELLDEF; // End of flop def } else if (!strcasecmp(token, "data_in")) { token = advancetoken(flib, 0); // Colon token = advancetoken(flib, ';'); // To end-of-statement newpin = parse_pin(newcell, token, SENSE_NONE); newpin->type |= LATCHIN; } else if (!strcasecmp(token, "enable")) { token = advancetoken(flib, 0); // Colon token = advancetoken(flib, ';'); // To end-of-statement if (strchr(token, '\'') != NULL) newcell->type |= EN_SENSE_MASK; else if (strchr(token, '!') != NULL) newcell->type |= EN_SENSE_MASK; newpin = parse_pin(newcell, token, SENSE_NONE); newpin->type |= LATCHEN; } else token = advancetoken(flib, ';'); // Read to end-of-statement break; case PINDEF: if (!strcmp(token, "}")) { section = CELLDEF; // End of pin def } else if (!strcasecmp(token, "capacitance")) { token = advancetoken(flib, 0); // Colon token = advancetoken(flib, ';'); // To end-of-statement sscanf(token, "%lg", &newpin->capr); newpin->capr *= cap_unit; } else if (!strcasecmp(token, "rise_capacitance")) { token = advancetoken(flib, 0); // Colon token = advancetoken(flib, ';'); // To end-of-statement sscanf(token, "%lg", &newpin->capr); newpin->capr *= cap_unit; } else if (!strcasecmp(token, "fall_capacitance")) { token = advancetoken(flib, 0); // Colon token = advancetoken(flib, ';'); // To end-of-statement sscanf(token, "%lg", &newpin->capf); newpin->capf *= cap_unit; } else if (!strcasecmp(token, "function")) { token = advancetoken(flib, 0); // Colon token = advancetoken(flib, 0); // Open quote if (!strcmp(token, "\"")) token = advancetoken(flib, '\"'); // Find function string if (newpin->type & OUTPUT) { newcell->function = strdup(token); } token = advancetoken(flib, 0); if (strcmp(token, ";")) { if (!strcmp(token, "}")) section = CELLDEF; // End of pin def else fprintf(stderr, "Expected end-of-statement.\n"); } } else if (!strcasecmp(token, "direction")) { token = advancetoken(flib, 0); // Colon token = advancetoken(flib, ';'); if (!strcasecmp(token, "input")) { newpin->type |= INPUT; } else if (!strcasecmp(token, "output")) { newpin->type |= OUTPUT; if (newcell->type & DFF) newpin->type |= DFFOUT; if (newcell->type & LATCH) newpin->type |= LATCHOUT; } } else if (!strcasecmp(token, "max_transition")) { token = advancetoken(flib, 0); // Colon token = advancetoken(flib, ';'); // To end-of-statement sscanf(token, "%lg", &newcell->maxtrans); newcell->maxtrans *= time_unit; } else if (!strcasecmp(token, "max_capacitance")) { token = advancetoken(flib, 0); // Colon token = advancetoken(flib, ';'); // To end-of-statement sscanf(token, "%lg", &newcell->maxcap); newcell->maxcap *= cap_unit; } else if (!strcasecmp(token, "timing")) { token = advancetoken(flib, 0); // Arguments, if any if (strcmp(token, "(")) fprintf(stderr, "Error: failed to find start of block\n"); else token = advancetoken(flib, ')'); // Arguments, if any token = advancetoken(flib, 0); // Find start of block if (strcmp(token, "{")) fprintf(stderr, "Error: failed to find start of block\n"); testpin = NULL; sense_type = SENSE_NONE; section = TIMING; } else { // For unhandled tokens, read in tokens. If it is // a definition or function, read to end-of-line. If // it is a block definition, read to end-of-block. while (1) { token = advancetoken(flib, 0); if (token == NULL) break; if (!strcmp(token, ";")) break; if (!strcmp(token, "\"")) token = advancetoken(flib, '\"'); if (!strcmp(token, "{")) { token = advancetoken(flib, '}'); break; } } } break; case TIMING: if (!strcmp(token, "}")) { section = PINDEF; // End of timing def } else if (!strcasecmp(token, "related_pin")) { token = advancetoken(flib, 0); // Colon token = advancetoken(flib, ';'); // Read to end of statement // Create the related pin if needed testpin = parse_pin(newcell, token, sense_type); } else if (!strcasecmp(token, "timing_sense")) { token = advancetoken(flib, 0); // Colon token = advancetoken(flib, ';'); // Read to end of statement if (!strcasecmp(token, "positive_unate")) { if (testpin) testpin->sense = SENSE_POSITIVE; else sense_type = SENSE_POSITIVE; } else if (!strcasecmp(token, "negative_unate")) { if (testpin) testpin->sense = SENSE_NEGATIVE; else sense_type = SENSE_NEGATIVE; } else if (!strcasecmp(token, "non_unate")) { if (testpin) testpin->sense = SENSE_NONE; else sense_type = SENSE_NONE; } } else if (!strcasecmp(token, "timing_type")) { token = advancetoken(flib, 0); // Colon token = advancetoken(flib, ';'); // Read to end of statement // Note: Timing type is apparently redundant information; // e.g., "falling_edge" can be determined by "clocked_on : !CLK" // in the ff {} block. How reliable is this? if (!strcasecmp(token, "rising_edge")) timing_type = TIMING_PROP_TRANS; else if (!strcasecmp(token, "falling_edge")) timing_type = TIMING_PROP_TRANS; else if (!strcasecmp(token, "hold_rising")) timing_type = TIMING_HOLD; else if (!strcasecmp(token, "hold_falling")) timing_type = TIMING_HOLD; else if (!strcasecmp(token, "setup_rising")) timing_type = TIMING_SETUP; else if (!strcasecmp(token, "setup_falling")) timing_type = TIMING_SETUP; else if (!strcasecmp(token, "clear")) timing_type = TIMING_SET_RESET; else if (!strcasecmp(token, "preset")) timing_type = TIMING_SET_RESET; else if (!strcasecmp(token, "recovery_rising")) timing_type = TIMING_RECOVERY; else if (!strcasecmp(token, "recovery_falling")) timing_type = TIMING_RECOVERY; else if (!strcasecmp(token, "removal_rising")) timing_type = TIMING_REMOVAL; else if (!strcasecmp(token, "removal_falling")) timing_type = TIMING_REMOVAL; else if (!strcasecmp(token, "three_state_enable")) timing_type = TIMING_TRISTATE; else if (!strcasecmp(token, "three_state_disable")) timing_type = TIMING_TRISTATE; } else if ((!strcasecmp(token, "cell_rise")) || (!strcasecmp(token, "cell_fall")) || (!strcasecmp(token, "rise_transition")) || (!strcasecmp(token, "fall_transition")) || (!strcasecmp(token, "rise_constraint")) || (!strcasecmp(token, "fall_constraint"))) { tableptr = (lutable *)malloc(sizeof(lutable)); tableptr->name = NULL; // Not used tableptr->invert = 0; tableptr->var1 = UNKNOWN; tableptr->var2 = UNKNOWN; tableptr->size1 = 0; tableptr->size2 = 0; tableptr->idx1.times = NULL; tableptr->idx2.caps = NULL; tableptr->values = NULL; tableptr->next = NULL; // Not used // Note that propagation delays (cell rise, cell fall) and // transition times (rise transition, fall transition) have // their lookup tables stored in the "related pin" pin record. // Setup and hold times (rise constraint, fall constraint) // have their lookup tables stored in the original pin record. // These should not overlap. // Recovery and removal tables are not yet handled. . . if (!strcasecmp(token, "cell_rise")) testpin->propdelr = tableptr; else if (!strcasecmp(token, "cell_fall")) testpin->propdelf = tableptr; else if (!strcasecmp(token, "rise_transition")) testpin->transr = tableptr; else if (!strcasecmp(token, "fall_transition")) testpin->transf = tableptr; else if (!strcasecmp(token, "rise_constraint")) { if (timing_type == TIMING_SETUP) newpin->propdelr = tableptr; else if (timing_type == TIMING_HOLD) newpin->transr = tableptr; } else if (!strcasecmp(token, "fall_constraint")) { if (timing_type == TIMING_SETUP) newpin->propdelf = tableptr; else if (timing_type == TIMING_HOLD) newpin->transf = tableptr; } token = advancetoken(flib, 0); // Open parens if (!strcmp(token, "(")) token = advancetoken(flib, ')'); for (reftable = *tablelist; reftable; reftable = reftable->next) if (!strcmp(reftable->name, token)) break; if (reftable == NULL) fprintf(stderr, "Failed to find a valid table \"%s\"\n", token); else { // Fill in default values from template reftable tableptr->invert = reftable->invert; if (reftable->size1 > 0) { tableptr->var1 = reftable->var1; tableptr->size1 = reftable->size1; tableptr->idx1.times = (double *)malloc(tableptr->size1 * sizeof(double)); memcpy(tableptr->idx1.times, reftable->idx1.times, tableptr->size1 * sizeof(double)); } if (reftable->size2 > 0) { tableptr->var2 = reftable->var2; tableptr->size2 = reftable->size2; tableptr->idx2.caps = (double *)malloc(tableptr->size2 * sizeof(double)); memcpy(tableptr->idx2.caps, reftable->idx2.caps, tableptr->size2 * sizeof(double)); } } token = advancetoken(flib, 0); if (strcmp(token, "{")) fprintf(stderr, "Failed to find start of timing block\n"); while (*token != '}') { token = advancetoken(flib, 0); if (!strcasecmp(token, "index_1")) { // Local index values override those in the template token = advancetoken(flib, 0); // Open parens token = advancetoken(flib, 0); // Quote if (!strcmp(token, "\"")) token = advancetoken(flib, '\"'); //------------------------- if (reftable && (reftable->invert == 1)) { // Entries had better match the ref table iptr = token; i = 0; sscanf(iptr, "%lg", &tableptr->idx2.caps[0]); if (tableptr->var2 == OUTPUT_CAP) tableptr->idx2.caps[0] *= cap_unit; else tableptr->idx2.cons[0] *= time_unit; while ((iptr = strchr(iptr, ',')) != NULL) { iptr++; i++; sscanf(iptr, "%lg", &tableptr->idx2.caps[i]); if (tableptr->var2 == OUTPUT_CAP) tableptr->idx2.caps[i] *= cap_unit; else tableptr->idx2.cons[i] *= time_unit; } } else if (reftable && (reftable->invert == 0)) { iptr = token; i = 0; sscanf(iptr, "%lg", &tableptr->idx1.times[0]); tableptr->idx1.times[0] *= time_unit; while ((iptr = strchr(iptr, ',')) != NULL) { iptr++; i++; sscanf(iptr, "%lg", &tableptr->idx1.times[i]); tableptr->idx1.times[i] *= time_unit; } } token = advancetoken(flib, ')'); // Close paren token = advancetoken(flib, ';'); // EOL semicolon } else if (!strcasecmp(token, "index_2")) { // Local index values override those in the template token = advancetoken(flib, 0); // Open parens token = advancetoken(flib, 0); // Quote if (!strcmp(token, "\"")) token = advancetoken(flib, '\"'); //------------------------- if (reftable && (reftable->invert == 1)) { // Entries had better match the ref table iptr = token; i = 0; sscanf(iptr, "%lg", &tableptr->idx1.times[0]); tableptr->idx1.times[0] *= time_unit; while ((iptr = strchr(iptr, ',')) != NULL) { iptr++; i++; sscanf(iptr, "%lg", &tableptr->idx1.times[i]); tableptr->idx1.times[i] *= time_unit; } } else if (reftable && (reftable->invert == 0)) { iptr = token; i = 0; sscanf(iptr, "%lg", &tableptr->idx2.caps[0]); tableptr->idx2.caps[0] *= cap_unit; while ((iptr = strchr(iptr, ',')) != NULL) { iptr++; i++; sscanf(iptr, "%lg", &tableptr->idx2.caps[i]); tableptr->idx2.caps[i] *= cap_unit; } } token = advancetoken(flib, ')'); // Close paren token = advancetoken(flib, ';'); // EOL semicolon } else if (!strcasecmp(token, "values")) { token = advancetoken(flib, 0); if (strcmp(token, "(")) fprintf(stderr, "Failed to find start of" " value table\n"); token = advancetoken(flib, ')'); // Parse the string of values and enter it into the // table "values", which is size size2 x size1 if (reftable && reftable->size1 > 0) { int locsize2; locsize2 = (reftable->size2 > 0) ? reftable->size2 : 1; if (reftable->invert) { tableptr->values = (double *)malloc(locsize2 * reftable->size1 * sizeof(double)); iptr = token; for (i = 0; i < reftable->size1; i++) { for (j = 0; j < locsize2; j++) { while (*iptr == ' ' || *iptr == '\"' || *iptr == ',') iptr++; sscanf(iptr, "%lg", &gval); *(tableptr->values + j * reftable->size1 + i) = gval * time_unit; while (*iptr != ' ' && *iptr != '\"' && *iptr != ',') iptr++; } } } else { tableptr->values = (double *)malloc(locsize2 * reftable->size1 * sizeof(double)); iptr = token; for (j = 0; j < locsize2; j++) { for (i = 0; i < reftable->size1; i++) { while (*iptr == ' ' || *iptr == '\"' || *iptr == ',') iptr++; sscanf(iptr, "%lg", &gval); *(tableptr->values + j * reftable->size1 + i) = gval * time_unit; while (*iptr != ' ' && *iptr != '\"' && *iptr != ',') iptr++; } } } } token = advancetoken(flib, 0); if (strcmp(token, ";")) fprintf(stderr, "Failed to find end of value table\n"); token = advancetoken(flib, 0); } else if (strcmp(token, "{")) fprintf(stderr, "Failed to find end of timing block\n"); } } else { // For unhandled tokens, read in tokens. If it is // a definition or function, read to end-of-line. If // it is a block definition, read to end-of-block. while (1) { token = advancetoken(flib, 0); if (token == NULL) break; if (!strcmp(token, ";")) break; if (!strcmp(token, "\"")) token = advancetoken(flib, '\"'); if (!strcmp(token, "{")) { token = advancetoken(flib, '}'); break; } } } break; } token = advancetoken(flib, 0); } } /*--------------------------------------------------------------*/ /* Read a verilog netlist and collect information about the */ /* cells instantiated and the network structure */ /*--------------------------------------------------------------*/ void verilogRead(FILE *fsrc, cell *cells, net **netlist, instance **instlist, connect **inputlist, connect **outputlist) { char *token; char *modname = NULL; int section = MODULE; instptr newinst; netptr newnet, testnet; cellptr testcell; connptr newconn, testconn; pinptr testpin; int vstart, vend, vtarget, isinput; struct hashlist *Nethash[OBJHASHSIZE]; /* See hash.c for these routines and variables */ hashfunc = hash; matchfunc = match; /* Initialize net hash table */ InitializeHashTable(Nethash); /* Read tokens off of the line */ token = advancetoken(fsrc, 0); while (token != NULL) { switch (section) { case MODULE: if (!strcasecmp(token, "module")) { token = advancetoken(fsrc, 0); fprintf(stderr, "Parsing module \"%s\"\n", token); token = advancetoken(fsrc, 0); if (strcmp(token, "(")) fprintf(stderr, "Module not followed by pin list\n"); else token = advancetoken(fsrc, ')'); token = advancetoken(fsrc, ';'); // Get end-of-line // Ignore the pin list, go straight to the input/output declarations section = IOLIST; } break; case IOLIST: if (!strcasecmp(token, "input") || !strcasecmp(token, "output")) { testconn = NULL; vstart = vend = 0; if (!strcasecmp(token, "input")) { isinput = 1; } else { // output isinput = 0; } token = advancetoken(fsrc, 0); if (*token == '[') { sscanf(token + 1, "%d", &vstart); token = advancetoken(fsrc, ':'); token = advancetoken(fsrc, ']'); // Read to end of vector sscanf(token, "%d", &vend); token = advancetoken(fsrc, 0); // Read signal name } // Create a net entry for the input or output, add to the list of nets if (vstart == 0 && vend == 0) { newnet = create_net(netlist); newnet->name = strdup(token); HashPtrInstall(newnet->name, newnet, Nethash); testconn = (connptr)malloc(sizeof(connect)); testconn->refnet = newnet; testconn->refpin = NULL; // No associated pin testconn->refinst = NULL; // No associated instance testconn->tag = NULL; testconn->metric = -1.0; testconn->prvector = NULL; testconn->pfvector = NULL; testconn->trvector = NULL; testconn->tfvector = NULL; if (isinput) { // driver (input) testconn->next = *inputlist; *inputlist = testconn; } else { // receiver (output) testconn->next = *outputlist; *outputlist = testconn; } } else { vtarget = vend + (vstart < vend) ? 1 : -1; while (vstart != vtarget) { newnet = create_net(netlist); newnet->name = (char *)malloc(strlen(token) + 6); sprintf(newnet->name, "%s[%d]", token, vstart); HashPtrInstall(newnet->name, newnet, Nethash); vstart += (vtarget > vend) ? 1 : -1; testconn = (connptr)malloc(sizeof(connect)); testconn->refnet = newnet; testconn->refpin = NULL; // No associated pin testconn->refinst = NULL; // No associated instance testconn->tag = NULL; testconn->metric = -1.0; testconn->prvector = NULL; testconn->pfvector = NULL; testconn->trvector = NULL; testconn->tfvector = NULL; if (isinput) { // driver (input) testconn->next = *inputlist; *inputlist = testconn; } else { // receiver (output) testconn->next = *outputlist; *outputlist = testconn; } } } token = advancetoken(fsrc, ';'); // Get rest of input/output entry break; } /* Drop through on anything that isn't an input, output, or blank line */ case GATELIST: if (!strcasecmp(token, "endmodule")) { section = MODULE; break; } /* Confirm that the token is a known cell, and continue parsing line if so */ /* Otherwise, parse to semicolon line end and continue */ for (testcell = cells; testcell; testcell = testcell->next) if (!strcasecmp(testcell->name, token)) break; if (testcell != NULL) { section = INSTANCE; newinst = (instptr)malloc(sizeof(instance)); newinst->next = *instlist; *instlist = newinst; newinst->refcell = testcell; newinst->in_connects = NULL; newinst->out_connects = NULL; } else { /* Ignore all wire and assign statements */ /* Qflow does not generate these, but other */ /* synthesis tools may. */ if (!strcasecmp(token, "assign") && (verbose > 0)) { fprintf(stdout, "Wire assignments are not handled!\n"); } else if (strcasecmp(token, "wire") && (verbose > 0)) { fprintf(stdout, "Unknown cell \"%s\" instanced.\n", token); } token = advancetoken(fsrc, ';'); // Get rest of entry, and ignore } break; case INSTANCE: newinst->name = strdup(token); token = advancetoken(fsrc, '('); // Find beginning of pin list section = INSTPIN; break; case INSTPIN: if (*token == '.') { newconn = (connptr)malloc(sizeof(connect)); // Pin name is in (token + 1) for (testpin = testcell->pins; testpin; testpin = testpin->next) { if (!strcmp(testpin->name, token + 1)) break; } // Sanity check if (testpin == NULL) { fprintf(stderr, "No such pin \"%s\" in cell \"%s\"!\n", token + 1, testcell->name); } else { if (testpin->type & OUTPUT) { newconn->next = newinst->out_connects; newinst->out_connects = newconn; } else { newconn->next = newinst->in_connects; newinst->in_connects = newconn; } } newconn->refinst = newinst; newconn->refpin = testpin; newconn->refnet = NULL; newconn->tag = NULL; newconn->metric = -1.0; newconn->prvector = NULL; newconn->pfvector = NULL; newconn->trvector = NULL; newconn->tfvector = NULL; token = advancetoken(fsrc, '('); // Read to beginning of pin name section = PINCONN; } else if (*token == ';') { // End of instance record section = GATELIST; } else if (*token != ',' && *token != ')') { fprintf(stderr, "Unexpected entry in instance pin connection list!\n"); token = advancetoken(fsrc, ';'); // Read to end-of-line section = GATELIST; } break; case PINCONN: // Token is net name testnet = (netptr)HashLookup(token, Nethash); if (testnet == NULL) { // This is a new net, and we need to record it newnet = create_net(netlist); newnet->name = strdup(token); HashPtrInstall(newnet->name, newnet, Nethash); newconn->refnet = newnet; } else newconn->refnet = testnet; section = INSTPIN; break; } if (section == PINCONN) token = advancetoken(fsrc, ')'); // Name token parsing else token = advancetoken(fsrc, 0); } /* Hash table no longer needed */ HashKill(Nethash); } /*--------------------------------------------------------------*/ /* For each net, go through the list of receivers and add the */ /* contributions of each to the total load. This is either */ /* the input pin capacitance, if the receiver is a pin, or the */ /* designated output load (given on the command line), if the */ /* receiver is an output pin. */ /*--------------------------------------------------------------*/ void computeLoads(netptr netlist, instptr instlist, double out_load) { instptr testinst; pinptr testpin; netptr testnet, driver, loadnet; connptr testconn; int i; for (testnet = netlist; testnet; testnet = testnet->next) { for (i = 0; i < testnet->fanout; i++) { testconn = testnet->receivers[i]; testpin = testconn->refpin; if (testpin == NULL) { testnet->loadr += out_load; testnet->loadf += out_load; } else { testnet->loadr += testpin->capr; testnet->loadf += testpin->capf; } } } // For each instance input pin, collapse the pin's lookup table // to a vector by interpolating/extrapolating the table at the // calculated output load. Save this vector in the connection // record for the pin. for (testinst = instlist; testinst; testinst = testinst->next) { loadnet = testinst->out_connects->refnet; for (testconn = testinst->in_connects; testconn; testconn = testconn->next) { testpin = testconn->refpin; if (testpin->propdelr) testconn->prvector = table_collapse(testpin->propdelr, loadnet->loadr); if (testpin->propdelf) testconn->pfvector = table_collapse(testpin->propdelf, loadnet->loadf); if (testpin->transr) testconn->trvector = table_collapse(testpin->transr, loadnet->loadr); if (testpin->transf) testconn->tfvector = table_collapse(testpin->transf, loadnet->loadf); } } } /*--------------------------------------------------------------*/ /* Assign types to each net. This identifies which nets are */ /* clock inputs, which are latch enable inputs, and which are */ /* asynchronous set/reset inputs,. */ /* */ /* Whenever a clock input to a flop is found, add the */ /* connection record to clockedlist */ /* */ /* For diagnostics, return the number of entries in clockedlist */ /*--------------------------------------------------------------*/ int assign_net_types(netptr netlist, connlistptr *clockedlist) { int i, numterms; netptr testnet; connptr testrcvr; pinptr testpin; connlistptr newclocked; numterms = 0; for (testnet = netlist; testnet; testnet = testnet->next) { for (i = 0; i < testnet->fanout; i++) { testrcvr = testnet->receivers[i]; testpin = testrcvr->refpin; if (testpin == NULL) testnet->type |= OUTTERM; else { switch (testpin->type & (DFFMASK | LATCHMASK)) { case DFFCLK: testnet->type |= CLOCK; newclocked = (connlistptr)malloc(sizeof(connlist)); newclocked->connection = testrcvr; newclocked->next = *clockedlist; *clockedlist = newclocked; numterms++; break; case DFFIN: testnet->type |= TERMINAL; break; case DFFSET: case DFFRST: testnet->type |= ASYNC; break; case LATCHIN: testnet->type |= LATCHTERM; break; case LATCHEN: testnet->type |= ENABLE; break; } } } } return numterms; } /*--------------------------------------------------------------*/ /* Create the links representing the netlist connections. */ /* */ /* The verilogRead() routine added all nets and instances, and */ /* for each instance, generated a list of net connections to */ /* each pin. To make the netlist easily traversible, this */ /* routine does the following: */ /* */ /* For each instance, work through the list of pin */ /* connections. If the pin is an output, then add the */ /* connection as the net's driver entry. If the pin is */ /* an input, then add the connection to the list of the */ /* net's receivers, and increment the net's fanout. */ /* */ /* For each module input, add the input connection as the */ /* net's driver (flag an error if the net already has a */ /* driver). */ /* */ /* For each module output, add the output connection as one of */ /* the net's receivers (it may be the only one). */ /* */ /*--------------------------------------------------------------*/ void createLinks(netptr netlist, instptr instlist, connptr inputlist, connptr outputlist) { netptr testnet; instptr testinst; connptr testconn; for (testinst = instlist; testinst; testinst = testinst->next) { for (testconn = testinst->in_connects; testconn; testconn = testconn->next) { testnet = testconn->refnet; testnet->fanout++; if (testnet->receivers == NULL) testnet->receivers = (connptr *)malloc(sizeof(connptr)); else testnet->receivers = (connptr *)realloc(testnet->receivers, testnet->fanout * sizeof(connptr)); testnet->receivers[testnet->fanout - 1] = testconn; } for (testconn = testinst->out_connects; testconn; testconn = testconn->next) { testnet = testconn->refnet; testnet->driver = testconn; } } for (testconn = inputlist; testconn; testconn = testconn->next) { testnet = testconn->refnet; if (testnet->driver != NULL) fprintf(stderr, "Error: Input pin \"%s\" has an internal driver!\n", testnet->name); // else // testnet->driver = testconn; // Don't do this, makes connectivity circular } for (testconn = outputlist; testconn; testconn = testconn->next) { testnet = testconn->refnet; testnet->fanout++; if (testnet->receivers == NULL) testnet->receivers = (connptr *)malloc(sizeof(connptr)); else testnet->receivers = (connptr *)realloc(testnet->receivers, testnet->fanout * sizeof(connptr)); testnet->receivers[testnet->fanout - 1] = testconn; } } /*--------------------------------------------------------------*/ /* Delay comparison used by qsort() to sort paths in order from */ /* longest to shortest propagation delay. */ /*--------------------------------------------------------------*/ int compdelay(ddataptr *a, ddataptr *b) { ddataptr p = *a; ddataptr q = *b; if (p->delay < q->delay) return (1); if (p->delay > q->delay) return (-1); return (0); } /*--------------------------------------------------------------*/ /* Main program */ /*--------------------------------------------------------------*/ int main(int objc, char *argv[]) { FILE *flib; FILE *fsrc; double period = 0.0; double outLoad = 0.0; double inTrans = 0.0; char *delayfile = NULL; int ival, firstarg = 1; // Liberty database lutable *tables = NULL; cell *cells = NULL; lutable *scalar; // Verilog netlist database instptr instlist = NULL; netptr netlist = NULL; connlistptr clockconnlist = NULL; connlistptr newinputconn, inputconnlist = NULL; connptr testconn, inputlist = NULL; connptr outputlist = NULL; // Timing path database ddataptr pathlist = NULL; ddataptr freeddata, testddata, *orderedpaths; btptr freebt, testbt; int numpaths, numterms, i; char badtiming; double slack; verbose = 0; exhaustive = 0; while ((firstarg < objc) && (*argv[firstarg] == '-')) { if (!strcmp(argv[firstarg], "-d") || !strcmp(argv[firstarg], "--delay")) { delayfile = strdup(argv[firstarg + 1]); firstarg += 2; } else if (!strcmp(argv[firstarg], "-p") || !strcmp(argv[firstarg], "--period")) { period = strtod(argv[firstarg + 1], NULL); firstarg += 2; } else if (!strcmp(argv[firstarg], "-l") || !strcmp(argv[firstarg], "--load")) { outLoad = strtod(argv[firstarg + 1], NULL); firstarg += 2; } else if (!strcmp(argv[firstarg], "-t") || !strcmp(argv[firstarg], "--trans")) { inTrans = strtod(argv[firstarg + 1], NULL); firstarg += 2; } else if (!strcmp(argv[firstarg], "-v") || !strcmp(argv[firstarg], "--verbose")) { sscanf(argv[firstarg + 1], "%d", &ival); verbose = (unsigned char)ival; firstarg += 2; } else if (!strcmp(argv[firstarg], "-e") || !strcmp(argv[firstarg], "--exhaustive")) { exhaustive = 1; firstarg++; } else if (!strcmp(argv[firstarg], "-V") || !strcmp(argv[firstarg], "--version")) { fprintf(stderr, "Vesta Static Timing Analzyer version 0.2\n"); exit(0); } else { fprintf(stderr, "Unknown option \"%s\"\n", argv[firstarg]); firstarg++; } } if (objc - firstarg != 2) { fprintf(stderr, "Usage: vesta [options] \n"); fprintf(stderr, "Options:\n"); fprintf(stderr, "--delay or -d \n"); fprintf(stderr, "--period or -p \n"); fprintf(stderr, "--load or -l \n"); fprintf(stderr, "--verbose or -v \n"); fprintf(stderr, "--exhaustive or -e\n"); fprintf(stderr, "--version or -V\n"); exit (1); } else { fflush(stdout); fprintf(stdout, "-----------------------------------------\n"); fprintf(stdout, "Vesta static timing analysis tool\n"); fprintf(stdout, "(c) 2013 Tim Edwards, Open Circuit Design\n"); fprintf(stdout, "-----------------------------------------\n\n"); fflush(stdout); } fsrc = fopen(argv[firstarg], "r"); if (fsrc == NULL) { fprintf(stderr, "Cannot open %s for reading\n", argv[firstarg]); exit (1); } flib = fopen(argv[firstarg + 1], "r"); if (flib == NULL) { fprintf(stderr, "Cannot open %s for reading\n", argv[firstarg + 1]); exit (1); } /*------------------------------------------------------------------*/ /* Generate one table template for the "scalar" case */ /*------------------------------------------------------------------*/ scalar = (lutable *)malloc(sizeof(lutable)); scalar->name = strdup("scalar"); scalar->invert = 0; scalar->var1 = CONSTRAINED_TIME; scalar->var2 = OUTPUT_CAP; scalar->size1 = 1; scalar->size2 = 1; scalar->idx1.times = (double *)malloc(sizeof(double)); scalar->idx2.caps = (double *)malloc(sizeof(double)); scalar->values = (double *)malloc(sizeof(double)); scalar->idx1.times[0] = 0.0; scalar->idx2.caps[0] = 0.0; scalar->values[0] = 0.0; scalar->next = NULL; tables = scalar; /*------------------------------------------------------------------*/ /* Read the liberty format file. This is not a rigorous parser! */ /*------------------------------------------------------------------*/ fileCurrentLine = 0; libertyRead(flib, &tables, &cells); fflush(stdout); fprintf(stdout, "Lib Read: Processed %d lines.\n", fileCurrentLine); if (flib != NULL) fclose(flib); /*--------------------------------------------------*/ /* Debug: Print summary of liberty database */ /*--------------------------------------------------*/ if (verbose > 2) { lutable *newtable; cell *newcell; pin *newpin; for (newtable = tables; newtable; newtable = newtable->next) { fprintf(stdout, "Table: %s\n", newtable->name); } for (newcell = cells; newcell; newcell = newcell->next) { fprintf(stdout, "Cell: %s\n", newcell->name); fprintf(stdout, " Function: %s\n", newcell->function); for (newpin = newcell->pins; newpin; newpin = newpin->next) { if (newpin->type == INPUT) fprintf(stdout, " Pin: %s cap=%g\n", newpin->name, newpin->capr); } fprintf(stdout, "\n"); } } /*------------------------------------------------------------------*/ /* Read verilog netlist. This is also not a rigorous parser! */ /*------------------------------------------------------------------*/ fileCurrentLine = 0; verilogRead(fsrc, cells, &netlist, &instlist, &inputlist, &outputlist); fflush(stdout); fprintf(stdout, "Verilog netlist read: Processed %d lines.\n", fileCurrentLine); if (fsrc != NULL) fclose(fsrc); /*--------------------------------------------------*/ /* Debug: Print summary of verilog source */ /*--------------------------------------------------*/ if (verbose > 1) { connect *testoutput; connect *testinput; net *testnet; instance *testinst; for (testinput = inputlist; testinput; testinput = testinput->next) { if (testinput->refnet) fprintf(stdout, " Input: %s\n", testinput->refnet->name); } for (testoutput = outputlist; testoutput; testoutput = testoutput->next) { if (testoutput->refnet) fprintf(stdout, " Output: %s\n", testoutput->refnet->name); } for (testnet = netlist; testnet; testnet = testnet->next) { fprintf(stdout, " Net: %s\n", testnet->name); } for (testinst = instlist; testinst; testinst = testinst->next) { fprintf(stdout, " Gate: %s\n", testinst->name); } } /*--------------------------------------------------*/ /* Generate internal links representing the network */ /*--------------------------------------------------*/ createLinks(netlist, instlist, inputlist, outputlist); /* Generate a connection list from inputlist */ for (testconn = inputlist; testconn; testconn = testconn->next) { newinputconn = (connlistptr)malloc(sizeof(connlist)); newinputconn->connection = testconn; newinputconn->next = inputconnlist; inputconnlist = newinputconn; } /*--------------------------------------------------*/ /* Calculate total load on each net */ /* To do: Add wire models or computed wire delays */ /*--------------------------------------------------*/ computeLoads(netlist, instlist, outLoad); /*--------------------------------------------------*/ /* Assign net types, mainly to identify clocks */ /* Return a list of clock nets */ /*--------------------------------------------------*/ numterms = assign_net_types(netlist, &clockconnlist); if (verbose > 1) fprintf(stdout, "Number of terminals to check: %d\n", numterms); /*--------------------------------------------------*/ /* Identify all clock-to-terminal paths */ /*--------------------------------------------------*/ numpaths = find_clock_to_term_paths(clockconnlist, &pathlist, netlist, MAXIMUM_TIME); fprintf(stdout, "Number of paths analyzed: %d\n", numpaths); /*--------------------------------------------------*/ /* Collect paths into a non-linked array so that */ /* they can be sorted by delay time */ /*--------------------------------------------------*/ orderedpaths = (ddataptr *)malloc(numpaths * sizeof(ddataptr)); i = 0; for (testddata = pathlist; testddata; testddata = testddata->next) { orderedpaths[i] = testddata; i++; } qsort(orderedpaths, numpaths, sizeof(ddataptr), (__compar_fn_t)compdelay); /*--------------------------------------------------*/ /* Report on top 20 maximum delay paths */ /*--------------------------------------------------*/ fprintf(stdout, "\nTop %d maximum delay paths:\n", (numpaths >= 20) ? 20 : numpaths); badtiming = 0; for (i = 0; ((i < 20) && (i < numpaths)); i++) { testddata = orderedpaths[i]; for (testbt = testddata->backtrace; testbt->next; testbt = testbt->next); if (testddata->backtrace->receiver->refinst != NULL) { fprintf(stdout, "Path %s/%s to %s/%s delay %g ps", testbt->receiver->refinst->name, testbt->receiver->refpin->name, testddata->backtrace->receiver->refinst->name, testddata->backtrace->receiver->refpin->name, testddata->delay); } else { fprintf(stdout, "Path %s/%s to output pin %s delay %g ps", testbt->receiver->refinst->name, testbt->receiver->refpin->name, testddata->backtrace->receiver->refnet->name, testddata->delay); } if (period > 0.0) { slack = period - testddata->delay; fprintf(stdout, " Slack = %g ps", slack); if (slack < 0.0) badtiming = 1; } fprintf(stdout, "\n"); } if (period > 0.0) { if (badtiming) { fprintf(stdout, "ERROR: Design fails timing requirements.\n"); } else { fprintf(stdout, "Design meets timing requirements.\n"); } } else if (orderedpaths[0] != NULL) { fprintf(stdout, "Computed maximum clock frequency (zero slack) = %g MHz\n", (1.0E6 / orderedpaths[0]->delay)); } fprintf(stdout, "-----------------------------------------\n\n"); fflush(stdout); /*--------------------------------------------------*/ /* Clean up the path list */ /*--------------------------------------------------*/ while (pathlist != NULL) { freeddata = pathlist; pathlist = pathlist->next; while (freeddata->backtrace != NULL) { freebt = freeddata->backtrace; freeddata->backtrace = freeddata->backtrace->next; freebt->refcnt--; if (freebt->refcnt == 0) free(freebt); } free(freeddata); } free(orderedpaths); /*--------------------------------------------------*/ /* Now calculate minimum delay paths */ /*--------------------------------------------------*/ numpaths = find_clock_to_term_paths(clockconnlist, &pathlist, netlist, MINIMUM_TIME); fprintf(stdout, "Number of paths analyzed: %d\n", numpaths); /*--------------------------------------------------*/ /* Collect paths into a non-linked array so that */ /* they can be sorted by delay time */ /*--------------------------------------------------*/ orderedpaths = (ddataptr *)malloc(numpaths * sizeof(ddataptr)); i = 0; for (testddata = pathlist; testddata; testddata = testddata->next) { orderedpaths[i] = testddata; i++; } qsort(orderedpaths, numpaths, sizeof(ddataptr), (__compar_fn_t)compdelay); /*--------------------------------------------------*/ /* Report on top 20 minimum delay paths */ /*--------------------------------------------------*/ fprintf(stdout, "\nTop %d minimum delay paths:\n", (numpaths >= 20) ? 20 : numpaths); badtiming = 0; for (i = numpaths; (i > (numpaths - 20)) && (i > 0); i--) { testddata = orderedpaths[i - 1]; for (testbt = testddata->backtrace; testbt->next; testbt = testbt->next); if (testddata->backtrace->receiver->refinst != NULL) { fprintf(stdout, "Path %s/%s to %s/%s delay %g ps\n", testbt->receiver->refinst->name, testbt->receiver->refpin->name, testddata->backtrace->receiver->refinst->name, testddata->backtrace->receiver->refpin->name, testddata->delay); } else { fprintf(stdout, "Path %s/%s to output pin %s delay %g ps\n", testbt->receiver->refinst->name, testbt->receiver->refpin->name, testddata->backtrace->receiver->refnet->name, testddata->delay); } if (testddata->delay < 0.0) badtiming = 1; } if (badtiming) fprintf(stdout, "ERROR: Design fails minimum hold timing.\n"); else fprintf(stdout, "Design meets minimum hold timing.\n"); fprintf(stdout, "-----------------------------------------\n\n"); fflush(stdout); /*--------------------------------------------------*/ /* Clean up the path list */ /*--------------------------------------------------*/ while (pathlist != NULL) { freeddata = pathlist; pathlist = pathlist->next; while (freeddata->backtrace != NULL) { freebt = freeddata->backtrace; freeddata->backtrace = freeddata->backtrace->next; freebt->refcnt--; if (freebt->refcnt == 0) free(freebt); } free(freeddata); } free(orderedpaths); for (testconn = inputlist; testconn; testconn = testconn->next) { testconn->tag = NULL; testconn->metric = -1; } /*--------------------------------------------------*/ /* Identify all input-to-terminal paths */ /*--------------------------------------------------*/ numpaths = find_clock_to_term_paths(inputconnlist, &pathlist, netlist, MAXIMUM_TIME); fprintf(stdout, "Number of paths analyzed: %d\n", numpaths); /*--------------------------------------------------*/ /* Collect paths into a non-linked array so that */ /* they can be sorted by delay time */ /*--------------------------------------------------*/ orderedpaths = (ddataptr *)malloc(numpaths * sizeof(ddataptr)); i = 0; for (testddata = pathlist; testddata; testddata = testddata->next) { orderedpaths[i] = testddata; i++; } qsort(orderedpaths, numpaths, sizeof(ddataptr), (__compar_fn_t)compdelay); /*--------------------------------------------------*/ /* Report on top 20 maximum delay paths */ /*--------------------------------------------------*/ fprintf(stdout, "\nTop %d maximum delay paths:\n", (numpaths >= 20) ? 20 : numpaths); for (i = 0; ((i < 20) && (i < numpaths)); i++) { testddata = orderedpaths[i]; for (testbt = testddata->backtrace; testbt->next; testbt = testbt->next); if (testddata->backtrace->receiver->refinst != NULL) { fprintf(stdout, "Path input pin %s to %s/%s delay %g ps\n", testbt->receiver->refnet->name, testddata->backtrace->receiver->refinst->name, testddata->backtrace->receiver->refpin->name, testddata->delay); } else { fprintf(stdout, "Path input pin %s to output pin %s delay %g ps\n", testbt->receiver->refnet->name, testddata->backtrace->receiver->refnet->name, testddata->delay); } } fprintf(stdout, "-----------------------------------------\n\n"); fflush(stdout); /*--------------------------------------------------*/ /* Clean up the path list */ /*--------------------------------------------------*/ while (pathlist != NULL) { freeddata = pathlist; pathlist = pathlist->next; while (freeddata->backtrace != NULL) { freebt = freeddata->backtrace; freeddata->backtrace = freeddata->backtrace->next; freebt->refcnt--; if (freebt->refcnt == 0) free(freebt); } free(freeddata); } free(orderedpaths); for (testconn = inputlist; testconn; testconn = testconn->next) { testconn->tag = NULL; testconn->metric = 1E50; } /*--------------------------------------------------*/ /* Now calculate minimum delay paths from inputs */ /*--------------------------------------------------*/ numpaths = find_clock_to_term_paths(inputconnlist, &pathlist, netlist, MINIMUM_TIME); fprintf(stdout, "Number of paths analyzed: %d\n", numpaths); /*--------------------------------------------------*/ /* Collect paths into a non-linked array so that */ /* they can be sorted by delay time */ /*--------------------------------------------------*/ orderedpaths = (ddataptr *)malloc(numpaths * sizeof(ddataptr)); i = 0; for (testddata = pathlist; testddata; testddata = testddata->next) { orderedpaths[i] = testddata; i++; } qsort(orderedpaths, numpaths, sizeof(ddataptr), (__compar_fn_t)compdelay); /*--------------------------------------------------*/ /* Report on top 20 minimum delay paths */ /*--------------------------------------------------*/ fprintf(stdout, "\nTop %d minimum delay paths:\n", (numpaths >= 20) ? 20 : numpaths); for (i = numpaths; (i > (numpaths - 20)) && (i > 0); i--) { testddata = orderedpaths[i - 1]; for (testbt = testddata->backtrace; testbt->next; testbt = testbt->next); if (testddata->backtrace->receiver->refinst != NULL) { fprintf(stdout, "Path input pin %s to %s/%s delay %g ps\n", testbt->receiver->refnet->name, testddata->backtrace->receiver->refinst->name, testddata->backtrace->receiver->refpin->name, testddata->delay); } else { fprintf(stdout, "Path input pin %s to output pin %s delay %g ps\n", testbt->receiver->refnet->name, testddata->backtrace->receiver->refnet->name, testddata->delay); } } fprintf(stdout, "-----------------------------------------\n\n"); fflush(stdout); /*--------------------------------------------------*/ /* Clean up the path list */ /*--------------------------------------------------*/ while (pathlist != NULL) { freeddata = pathlist; pathlist = pathlist->next; while (freeddata->backtrace != NULL) { freebt = freeddata->backtrace; freeddata->backtrace = freeddata->backtrace->next; freebt->refcnt--; if (freebt->refcnt == 0) free(freebt); } free(freeddata); } free(orderedpaths); return 0; } qflow-1.1.23/src/blifFanout.c0000664000175000001440000011662112533334370014476 0ustar timusers/* *--------------------------------------------------------------------------- * blifFanout blif_input [blif_output] * * blifFanout[.c] parses a .blif netlist (typically, but not necessarily, * from synthesized verilog). The fanout is analyzed, and fanout of each gate * is counted. A value to parameterize the driving cell will be output. * Fanouts exceeding a maximum are broken into (possibly hierarchical) * buffer trees. Eventually, a critical path can be identified, and the * gates sized to improve it. * * Original: fanout.c by Steve Beccue * New: blifFanout.c by Tim Edwards. * changes: 1) Input and output format changed from RTL verilog to BDNET * for compatibility with the existing digital design flow. * 2) Gate format changed to facilitate entering IBM data * 3) Code changed/optimized in too many ways to list here. * * Update 4/8/2013: * Removing dependence upon the naming convention of the original * technology used with this tool. Instead, the format of the naming * convention is passed to the tool using "-s ", and parsing * the remaining name for unique identifiers. * * Update 10/8/2013: * Changed input file format from BDNET to BLIF * * Update 10/21/2013: * Removed most of the dependencies on fixed-length arrays * * Update 5/13/2015: * Added hash functions, which have been on the "to do" list for a * while. Greatly speeds up the processing, especially for large * netlists. * * Replaced the gate.cfg file parser with the liberty file parser * from the "liberty2tech" code, which is no longer needed. The * gate.cfg format was essentially useless as it failed to track * which pins in a cell are inputs and which are outputs. * * Moving the clock tree generator into this module, because I have * figured out a way to do this in one stage instead of two, using * the swap_group capability of the graywolf placement tool to find * the optimal groupings. *--------------------------------------------------------------------------- * * Revision 1.3 2008/09/09 21:24:30 steve_beccue * changed gate strengths in code. Inserted inverters. 2nd pass on * insert inverters does not work. * * Revision 1.2 2008/09/04 14:25:59 steve_beccue * added helpmessage and id * *--------------------------------------------------------------------------- */ #include #include #include /* for getopt() */ #include #include /* for isdigit() */ #include #include "hash.h" /* for hash table functions */ #include "readliberty.h" /* liberty file database */ #define FALSE 0 #define TRUE 1 #define MAXLINE 2000 char *Inputfname; char *Outputfname; char *Buffername = NULL; char *buf_in_pin = NULL; char *buf_out_pin = NULL; char *Gatepath = NULL; char *Ignorepath = NULL; char *Separator = NULL; char SuffixIsNumeric; int GatePrintFlag = 0; int NodePrintFlag = 0; int VerboseFlag = 0; int skip_eol = 0; static char default_sep = '\0'; int Topfanout = 0; int Inputfanout = 0; double Topload = 0.0; double Inputload = 0.0; double Topratio = 0.0; int Changed_count = 0; // number of gates changed int Buffer_count = 0; // number of buffers added int stren_err_counter = 0; double MaxOverload = 0.0; int MaxFanout = 16; // Maximum fanout per node allowed without // additional buffering. double MaxLatency = 100.0; // Maximum variable latency (ps) for which we // are solving. Represents the largest delay // allowed for any gate caused by total load // capacitance. This is empirically derived. double MaxOutputCap = 18.0; // Maximum capacitance for an output node (fF). // Outputs should be able to drive this much // capacitance within MaxLatency time (ps). double WireCap = 10.0; // Base capacitance for an output node, estimate // of average wire capacitance (fF). struct Gatelist { char *gatename; Cell *gatecell; char *suffix; // points to position in gatename, not allocated int num_inputs; double Cint; double delay; double strength; } Gatelist_; struct hashlist *Gatehash[OBJHASHSIZE]; struct Nodelist { char ignore; char *nodename; struct Gatelist *outputgate; double outputgatestrength; int type; int num_inputs; double total_load; double ratio; // drive strength to total_load ratio // For net buffer trees int num_buf; // Number of buffers to split the net int curcount; // Active count for fanout buffering trees } Nodelist_; struct hashlist *Nodehash[OBJHASHSIZE]; struct Drivelist { char *DriveType; // Suffix name (e.g., "X1") int NgatesIn; // Number of gates with this suffix in input int NgatesOut; // Number of gates with this suffix in output } Drivelist_; struct hashlist *Drivehash[OBJHASHSIZE]; struct Baselist { char *BaseName; // gate base name (e.g., "INV") int Ndrives; // number of different drive types for this gate struct Gatelist **gates; // list of pointers to gates with } Baselist_; struct hashlist *Basehash[OBJHASHSIZE]; enum states_ {NONE, INPUTS, OUTPUTS, GATENAME, PINNAME, INPUTNODE, OUTPUTNODE, ENDMODEL, ERROR}; enum nodetype_ {UNKNOWN, INPUT, OUTPUT, INPUTPIN, OUTPUTPIN}; int read_gate_file(char *gate_file_name); void read_ignore_file(char *ignore_file_name); struct Gatelist *GatelistAlloc(); struct Nodelist *NodelistAlloc(); struct Drivelist *DrivelistAlloc(); struct Baselist *BaselistAlloc(); void showgatelist(void); void helpmessage(void); void registernode(char *nodename, int type, struct Gatelist *gl, char *pinname); void shownodes(void); void write_output(FILE *infptr, FILE *outfptr); struct Gatelist *best_size(struct Gatelist *gl, double amount, char *overload); void count_gatetype(struct Gatelist *gl, int num_in, int num_out); /* *--------------------------------------------------------------------------- * find_suffix --- * * Given a gate name, return the part of the name corresponding to the * suffix. That is, find the last occurrance of the string Separator * (global variable), and return a pointer to the following character. *--------------------------------------------------------------------------- */ char *find_suffix(char *gatename) { char *tsuf, *gptr; char *suffix = NULL; if (Separator == NULL || (*Separator == '\0')) { suffix = gatename + strlen(gatename) - 1; while (isdigit(*suffix)) suffix--; suffix++; } else { gptr = gatename; while ((tsuf = strstr(gptr, Separator)) != NULL) { suffix = tsuf; gptr = tsuf + 1; } if (suffix != NULL) suffix += strlen(Separator); } return suffix; } /* *--------------------------------------------------------------------------- *--------------------------------------------------------------------------- */ int main (int argc, char *argv[]) { int i, j, k; int state; int inputcount; int gateinputs; int gatecount; char *pinname; char *test; char *s, *t; FILE *infptr, *outfptr; char line[MAXLINE]; struct Gatelist *gl = NULL; struct Nodelist *nl = NULL, *nlmax, *nlimax; struct Drivelist *dl = NULL; SuffixIsNumeric = TRUE; // By default, assume numeric suffixes Separator = NULL; // By default, assume no separator /* Note: To-Do, have an option that sets the case-insensitive */ /* hash & match functions. */ hashfunc = hash; matchfunc = match; InitializeHashTable(Nodehash); InitializeHashTable(Drivehash); InitializeHashTable(Gatehash); while ((i = getopt(argc, argv, "gnhvl:c:b:i:o:p:s:f:F:")) != EOF) { switch (i) { case 'b': Buffername = strdup(optarg); break; case 'i': buf_in_pin = strdup(optarg); break; case 'o': buf_out_pin = strdup(optarg); break; case 'p': Gatepath = strdup(optarg); break; case 'f': Ignorepath = strdup(optarg); break; case 'F': MaxFanout = atoi(optarg); break; case 'l': MaxLatency = atof(optarg); break; case 'c': MaxOutputCap = atof(optarg); break; case 's': Separator = strdup(optarg); break; case 'g': GatePrintFlag = 1; break; case 'n': NodePrintFlag = 1; break; case 'v': VerboseFlag = 1; break; case 'h': helpmessage(); return -3; break; default: break; } } Inputfname = Outputfname = NULL; infptr = stdin; outfptr = stdout; i = optind; if (i < argc) { Inputfname = strdup(argv[i]); if (!(infptr = fopen(Inputfname, "r"))) { fprintf(stderr, "blifFanout: Couldn't open %s for reading.\n", Inputfname); return -1; } } i++; if (i < argc) { Outputfname = strdup(argv[i]); if (!(outfptr = fopen(Outputfname, "w"))) { fprintf(stderr, "blifFanout: Couldn't open %s for writing.\n", Outputfname); return -1; } } i++; // Make sure we have a valid gate file path if (Gatepath == NULL) { fprintf(stderr, "blifFanout: No liberty file specified.\n"); return -1; } gatecount = read_gate_file(Gatepath); // Make sure we have a non-NULL separator. if (Separator == NULL) Separator = &default_sep; // Determine if suffix is numeric or alphabetic if (gatecount > 0) { char *suffix; gl = (struct Gatelist *)HashFirst(Gatehash); while (gl && gl->suffix == NULL) gl = (struct Gatelist *)HashNext(Gatehash); if (gl && gl->suffix && !isdigit(*gl->suffix)) SuffixIsNumeric = FALSE; } if (gatecount == 0) { fprintf(stderr, "blifFanout: No gates found in %s file!\n", Gatepath); return -1; } if (GatePrintFlag) { showgatelist(); return 0; } if (buf_in_pin == NULL || buf_out_pin == NULL) { Pin *curpin; gl = (struct Gatelist *)NULL; if (Buffername != NULL) { gl = (struct Gatelist *)HashLookup(Buffername, Gatehash); if (gl == NULL) { fprintf(stderr, "No buffer \"%s\" found in gate list\n", Buffername); fprintf(stderr, "Searching gate list for suitable buffer.\n"); } } if ((gl == NULL) || (Buffername == NULL)) { // Find a suitable buffer gl = (struct Gatelist *)HashFirst(Gatehash); while (gl != NULL) { Cell *ctest; // Find the first gate with one input, one output, // and a function string that matches the input pin name. ctest = gl->gatecell; if (ctest->pins && ctest->pins->next && !ctest->pins->next->next) { if (ctest->pins->type == PIN_INPUT && ctest->pins->next->type == PIN_OUTPUT) { if (!strcmp(ctest->function, ctest->pins->name)) { fprintf(stdout, "Using cell \"%s\" for buffers.\n", ctest->name); break; } } else if (ctest->pins->type == PIN_OUTPUT && ctest->pins->next->type == PIN_INPUT) { if (!strcmp(ctest->function, ctest->pins->next->name)) { fprintf(stdout, "Using cell \"%s\" for buffers.\n", ctest->name); break; } } } gl = (struct Gatelist *)HashNext(Gatehash); } } else gl = (struct Gatelist *)HashLookup(Buffername, Gatehash); if (gl == NULL) { fprintf(stderr, "blifFanout: Buffer cell %s cannot be found.\n", Buffername); return -1; } for (curpin = gl->gatecell->pins; curpin; curpin = curpin->next) { if (curpin->type == PIN_INPUT) { if (buf_in_pin == NULL) buf_in_pin = strdup(curpin->name); } else if (curpin->type == PIN_INPUT) { if (buf_out_pin == NULL) buf_out_pin = strdup(curpin->name); } } if (buf_in_pin == NULL || buf_out_pin == NULL) { fprintf(stderr, "blifFanout: Could not parse I/O pins " "of buffer cell %s.\n", Buffername); return -1; } } pinname = (char *)malloc(1); state = NONE; while ((s = fgets(line, MAXLINE, infptr)) != NULL) { t = strtok(s, " \t=\n"); while (t) { switch (state) { case GATENAME: gl = (struct Gatelist *)HashLookup(t, Gatehash); if (gl != NULL) { if (VerboseFlag) printf("\n\n%s", t); gateinputs = gl->num_inputs; state = PINNAME; } break; case INPUTS: if (!strcmp(t, ".gate")) state = GATENAME; else if (!strcmp(t, ".outputs")) state = OUTPUTS; else if (t) { if (VerboseFlag) printf("\nInput pin %s", t); registernode(t, INPUTPIN, gl, pinname); } break; case OUTPUTS: if (!strcmp(t, ".gate")) state = GATENAME; else if (t) { if (VerboseFlag) printf("\nOutput pin %s", t); registernode(t, OUTPUTPIN, gl, pinname); } break; case PINNAME: if (!strcmp(t, ".gate")) state = GATENAME; // new gate else if (!strcmp(t, ".end")) state = ENDMODEL; // last gate else { int cur_pintype; free(pinname); pinname = strdup(t); if (gl == NULL) state = ERROR; else if ((cur_pintype = get_pintype(gl->gatecell, t)) == PIN_OUTPUT) state = OUTPUTNODE; else if (cur_pintype == PIN_INPUT) state = INPUTNODE; else state = ERROR; // Probably want error handling here. . . } break; case INPUTNODE: if (VerboseFlag) printf("\nInput node %s", t); registernode(t, INPUT, gl, pinname); state = PINNAME; break; case OUTPUTNODE: if (VerboseFlag) printf("\nOutput node %s", t); registernode(t, OUTPUT, gl, pinname); state = PINNAME; break; case ERROR: default: if (t[0] == '#') skip_eol = 1; else if (!strcmp(t, ".gate")) state = GATENAME; else if (!strcmp(t, ".inputs")) state = INPUTS; else if (!strcmp(t, ".outputs")) state = OUTPUTS; break; } if (skip_eol == 1) { skip_eol = 0; break; } t = strtok(NULL, " \t=\n"); // Ignore continuation lines if (t && (!strcmp(t, "\\"))) t = strtok(NULL, " \t=\n"); } } free(pinname); /* get list of nets to ignore, if there is one, and mark nets to ignore */ if (Ignorepath != NULL) read_ignore_file(Ignorepath); if (NodePrintFlag) { shownodes(); return 0; } /* Show top fanout gate */ nlmax = NULL; nlimax = NULL; nl = (struct Nodelist *)HashFirst(Nodehash); while (nl != NULL) { if (nl->outputgatestrength != 0.0) { nl->ratio = nl->total_load / nl->outputgatestrength; } if (nl->ignore == FALSE) { if ((nl->num_inputs >= Topfanout) && (nl->outputgatestrength != 0.0)) { Topfanout = nl->num_inputs; nlmax = nl; } else if ((nl->num_inputs >= Inputfanout) && (nl->type == INPUTPIN)) { Inputfanout = nl->num_inputs; nlimax = nl; } if ((nl->ratio >= Topratio) && (nl->outputgatestrength != 0.0)) { Topratio = nl->ratio; } if ((nl->total_load >= Topload) && (nl->outputgatestrength != 0.0)) { Topload = nl->total_load; } else if ((nl->total_load >= Inputload) && (nl->type == INPUTPIN)) { Inputload = nl->total_load; } } nl = (struct Nodelist *)HashNext(Nodehash); } if (VerboseFlag) printf("\n"); fflush(stdout); fprintf(stderr, "Top internal fanout is %d (load %g) from node %s,\n" "driven by %s with strength %g\n", Topfanout, Topload, nlmax->nodename, nlmax->outputgate->gatename, nlmax->outputgatestrength); fprintf(stderr, "Top fanout load-to-strength ratio is %g\n", Topratio); fprintf(stderr, "Top input node fanout is %d (load %g) from node %s.\n", Inputfanout, Inputload, nlimax->nodename); Buffer_count = 0; if ((Topfanout > MaxFanout) || (Inputfanout > MaxFanout)) { /* Insert buffer trees */ nl = (struct Nodelist *)HashFirst(Nodehash); while (nl != NULL) { if (nl->ignore == FALSE) { // Nets with no driver must be module inputs. Mainly, // this condition rejects power and ground nodes. if ((nl->num_inputs > MaxFanout) && ((nl->outputgatestrength != 0.0) || (nl->type == INPUTPIN))) { double d; int stages, n, mfan; // Find number of hierarchical stages (plus one) needed mfan = nl->num_inputs; stages = 1; n = MaxFanout; while (mfan > MaxFanout) { mfan = nl->num_inputs / n; n *= MaxFanout; stages++; } // Find the floor of the number of fanouts per buffer d = pow((double)nl->num_inputs, (double)(1.0 / stages)); n = (int)((double)nl->num_inputs / d); // Split network into reasonably balanced groups of // the same (or almost) fanout. nl->num_buf = n; nl->curcount = n - 1; Buffer_count += n; } } nl = (struct Nodelist *)HashNext(Nodehash); } } write_output(infptr, outfptr); fprintf(stderr, "%d gates exceed specified minimum load.\n", stren_err_counter); fprintf(stderr, "%d buffers were added.\n", Buffer_count); fprintf(stderr, "%d gates were changed.\n", Changed_count); fprintf(stderr, "\nGate counts by drive strength:\n\n"); dl = (struct Drivelist *)HashFirst(Drivehash); while (dl != NULL) { if (dl->NgatesIn > 0) { fprintf(stderr, "\t\"%s%s\" gates\tIn: %d \tOut: %d \t%+d\n", Separator, dl->DriveType, dl->NgatesIn, dl->NgatesOut, (dl->NgatesOut - dl->NgatesIn)); } dl = (struct Drivelist *)HashNext(Drivehash); } fprintf(stderr, "\n"); if (infptr != stdin) fclose(infptr); if (outfptr != stdout) fclose(outfptr); // return with number of gates changed so we can iterate until // this is zero. return (Changed_count + Buffer_count); } /* *--------------------------------------------------------------------------- * Read a file of nets for which we should ignore fanout. Typically this * would include the power and ground nets, but may include other static * nets with non-critical timing. *--------------------------------------------------------------------------- */ void read_ignore_file(char *ignore_file_name) { struct Nodelist *nl; FILE *ignorefptr; char line[MAXLINE]; char *s, *sp; if (!(ignorefptr = fopen(ignore_file_name, "r"))) { fprintf(stderr, "blifFanout: Couldn't open %s as ignore file.\n", ignore_file_name); fflush(stderr); return; // This is only a warning. It will not stop execution of blifFanout } while ((s = fgets(line, MAXLINE, ignorefptr)) != NULL) { // One net name per line while (isspace(*s)) s++; sp = s; while (*sp != '\0' && *sp != '\n' && !isspace(*sp)) sp++; *sp = '\0'; nl = (struct Nodelist *)HashLookup(s, Nodehash); if (nl != NULL) { nl->ignore = (char)1; } } fclose(ignorefptr); } /* *--------------------------------------------------------------------------- * * Call read_liberty() to read in cell information from a Liberty file, * and then hash the resulting list. * *--------------------------------------------------------------------------- */ int read_gate_file(char *gate_file_name) { int i, j, k, ind, format = -1; int gatecount; char *s, *t, *ss, ssave; struct Gatelist *gl; struct Baselist *bl; Cell *cells, *curcell; Pin *curpin; gatecount = 0; cells = read_liberty(gate_file_name, NULL); for (curcell = cells; curcell != NULL; curcell = curcell->next) { if (curcell->name == NULL) continue; /* "dont_use" cell */ gl = GatelistAlloc(); gl->gatename = strdup(curcell->name); gl->suffix = find_suffix(gl->gatename); gl->gatecell = curcell; get_values(curcell, &gl->delay, &gl->Cint); gl->num_inputs = 0; for (curpin = curcell->pins; curpin; curpin = curpin->next) if (curpin->type == INPUT) gl->num_inputs++; /* The "MaxLatency" is empirically derived. Since gl->delay */ /* is in ps/fF, and strength is compared directly to total */ /* load capacitance, MaxLatency is effectively in units of ps */ /* and represents the maximum latency due to load capacitance */ /* for any gate in the circuit after making gate strength */ /* substitutions (this does not include internal, constant */ /* delays in each gate). */ gl->strength = MaxLatency / gl->delay; HashPtrInstall(gl->gatename, gl, Gatehash); gatecount++; /* Install prefix in Basehash */ if ((s = gl->suffix) == NULL) ind = strlen(gl->gatename); else ind = (int)(s - gl->gatename); ssave = gl->gatename[ind]; gl->gatename[ind] = '\0'; bl = (struct Baselist *)HashLookup(gl->gatename, Basehash); if (bl == NULL) { bl = BaselistAlloc(); HashPtrInstall(gl->gatename, bl, Basehash); bl->BaseName = strdup(gl->gatename); } gl->gatename[ind] = ssave; // Note: this code assumes that there are no repeats in // the liberty file gate list (there shouldn't be). if (bl->Ndrives == 0) bl->gates = (struct Gatelist **)malloc(sizeof(struct Gatelist *)); else bl->gates = (struct Gatelist **)realloc(bl->gates, (bl->Ndrives + 1) * sizeof(struct Gatelist *)); bl->gates[bl->Ndrives] = gl; bl->Ndrives++; } return gatecount; } /* *--------------------------------------------------------------------------- *--------------------------------------------------------------------------- */ struct Gatelist* GatelistAlloc() { struct Gatelist *gl; gl = (struct Gatelist*)malloc(sizeof(struct Gatelist)); gl->gatename = NULL; gl->suffix = 0; gl->num_inputs = 0; gl->Cint = 0.0; gl->delay = 0.0; gl->strength = 0.0; return gl; } /* *--------------------------------------------------------------------------- *--------------------------------------------------------------------------- */ struct Drivelist *DrivelistAlloc() { struct Drivelist *dl; dl = (struct Drivelist *)malloc(sizeof(struct Drivelist)); dl->NgatesIn = 0; dl->NgatesOut = 0; dl->DriveType = NULL; return dl; } /* *--------------------------------------------------------------------------- *--------------------------------------------------------------------------- */ struct Nodelist* NodelistAlloc() { struct Nodelist *nl; nl = (struct Nodelist *)malloc(sizeof(struct Nodelist)); nl->nodename = NULL; nl->ignore = FALSE; nl->outputgate = NULL; nl->outputgatestrength = 0.0; nl->type = UNKNOWN; nl->total_load = 0.0; nl->num_inputs = 0; nl->num_buf = 0; // Tree expansion of node nl->curcount = 0; return nl; } /* *--------------------------------------------------------------------------- *--------------------------------------------------------------------------- */ struct Baselist *BaselistAlloc() { struct Baselist *bl; bl = (struct Baselist *)malloc(sizeof(struct Baselist)); bl->BaseName = NULL; bl->Ndrives = 0; bl->gates = NULL; return bl; } /* *--------------------------------------------------------------------------- *--------------------------------------------------------------------------- */ void showgatelist(void) { struct Gatelist *gl; Cell *curcell; Pin *curpin; double pincap; gl = (struct Gatelist *)HashFirst(Gatehash); while (gl != NULL) { printf("\n\ngate: %s with %d inputs and %g drive strength\n", gl->gatename, gl->num_inputs, gl->strength); printf("%g ", gl->Cint); curcell = gl->gatecell; for (curpin = curcell->pins; curpin; curpin = curpin->next) { if (curpin->type == INPUT) { get_pincap(curcell, curpin->name, &pincap); printf("%g ", pincap); } } gl = (struct Gatelist *)HashNext(Gatehash); } } /* *--------------------------------------------------------------------------- *--------------------------------------------------------------------------- */ void registernode(char *nodename, int type, struct Gatelist *gl, char *pinname) { struct Nodelist *nl; double pincap; nl = (struct Nodelist *)HashLookup(nodename, Nodehash); if (nl == NULL) { nl = NodelistAlloc(); nl->nodename = strdup(nodename); if (type == OUTPUT) nl->outputgate = NULL; HashPtrInstall(nodename, nl, Nodehash); nl->type = type; } if (type == OUTPUT) { nl->outputgate = gl; if (gl != NULL) { nl->outputgatestrength = gl->strength; nl->total_load += gl->Cint; count_gatetype(gl, 1, 1); } } else if (type == INPUT) { if (gl != NULL) { get_pincap(gl->gatecell, pinname, &pincap); nl->total_load += pincap; nl->num_inputs++; } } if ((nl->type != OUTPUTPIN) && (gl == NULL)) { fprintf(stderr, "\nError: no output gate for net %s\n", nodename); fflush(stderr); } } /* *--------------------------------------------------------------------------- *--------------------------------------------------------------------------- */ void count_gatetype(struct Gatelist *gl, int num_in, int num_out) { struct Drivelist *dl; char *s, *nptr, *tsuf; int g; if ((s = gl->suffix) == NULL) return; dl = (struct Drivelist *)HashLookup(s, Drivehash); if (dl == NULL) { // New drive type found dl = DrivelistAlloc(); HashPtrInstall(s, dl, Drivehash); dl->DriveType = strdup(s); } dl->NgatesIn += num_in; // Number of these gates before processing dl->NgatesOut += num_out; // Number of these gates after processing } /* *--------------------------------------------------------------------------- *--------------------------------------------------------------------------- */ void shownodes(void) { struct Nodelist *nl; int i; nl = (struct Nodelist *)HashFirst(Nodehash); while (nl != NULL) { printf("\n\nnode: %s with %d fanout and %g cap", nl->nodename, nl->num_inputs, nl->total_load); printf("\ndriven by %s, with %g strength.\n", nl->outputgate->gatename, nl->outputgatestrength); nl = (struct Nodelist *)HashNext(Nodehash); } } /* *--------------------------------------------------------------------------- *--------------------------------------------------------------------------- */ void write_output(FILE *infptr, FILE *outfptr) { char *s, *t; char line[MAXLINE]; char inputline[MAXLINE]; char bufferline[MAXLINE]; char nodename[MAXLINE]; char *gateline; char *stren, *orig; int firstseen; int state, i; int gateinputs; int pincount; int needscorrecting; int slen; int hier; char *spos; struct Nodelist *nltest; struct Gatelist *gl; struct Gatelist *glbest, *bbest; struct Gatelist *glbuf; struct Nodelist *nl; struct Drivelist *dl; double inv_size; Changed_count = 0; state = NONE; needscorrecting = 0; firstseen = 0; // Find the gate record corresponding to the buffer name glbuf = (struct Gatelist *)HashLookup(Buffername, Gatehash); rewind(infptr); gateline = (char *)malloc(1); gateline[0] = '\0'; while ((s = fgets(line, MAXLINE, infptr)) != NULL) { strcpy(inputline, s); // save this for later t = strtok(s, " \t=\n"); while (t) { switch (state) { case GATENAME: if (firstseen == 0) { /* Insert any added buffers (before 1st gate) */ nl = (struct Nodelist *)HashFirst(Nodehash); while (nl != NULL) { for (i = nl->num_buf - 1; i >= 0; i--) { hier = 0; nltest = nl; sprintf(nodename, "%s", nl->nodename); while (nltest != NULL) { slen = strlen(nodename); spos = nodename + slen - 1; if (*spos == ']') { /* Avoid downstream problems: */ /* recast "[X]_bF$bufN" as [X_bF$bufN]" */ sprintf(spos, "_bF$buf%d]", i); } else if (*spos == '>') { /* Avoid downstream problems: */ /* recast "_bF$bufN" as _X_bF$bufN" */ char *dptr = nodename + slen - 1; while (dptr >= nodename && *dptr != '<') dptr--; if (dptr >= nodename) *dptr = '_'; sprintf(spos, "_bF$buf%d", i); } else { spos++; sprintf(spos, "_bF$buf%d", i); } /* For buffer trees of depth > 1, there will be */ /* an existing node name wih the _bufN extension */ /* that is in the node hash table. If so, then */ /* add the prefix "_hierM". Test again in case */ /* the buffer tree is even deeper, incrementing */ /* M until the name is unique. */ nltest = (struct Nodelist *)HashLookup(nodename, Nodehash); if (nltest != NULL) { sprintf(nodename, "%s_hier%d", nl->nodename, hier); hier++; } } fprintf(outfptr, ".gate %s %s=%s %s=%s\n", Buffername, buf_in_pin, nl->nodename, buf_out_pin, nodename); } nl = (struct Nodelist *)HashNext(Nodehash); } firstseen = 1; } gl = (struct Gatelist *)HashLookup(t, Gatehash); if (gl != NULL) { gateinputs = gl->num_inputs; needscorrecting = 0; pincount = 0; state = PINNAME; } break; case PINNAME: if (!strcmp(t, ".gate")) state = GATENAME; // new gate else if (!strcmp(t, ".end")) state = ENDMODEL; // last gate else if (gl == NULL) state = ERROR; else { int cur_pintype; if ((cur_pintype = get_pintype(gl->gatecell, t)) == PIN_OUTPUT) { state = OUTPUTNODE; pincount++; } else if (cur_pintype == PIN_INPUT) { state = INPUTNODE; pincount++; } else state = ERROR; // Probably want error handling here. . . } break; case INPUTNODE: if (VerboseFlag) printf("\nInput node %s", t); nl = (struct Nodelist *)HashLookup(t, Nodehash); if (nl->num_buf > 0) { hier = 0; nltest = nl; sprintf(nodename, "%s", nl->nodename); while (nltest != NULL) { slen = strlen(nodename); spos = nodename + slen - 1; if (*spos == ']') { /* Avoid downstream problems: */ /* recast "[X]_bF$bufN" as [X_bF$bufN]" */ sprintf(spos, "_bF$buf%d]", nl->curcount); } else if (*spos == '>') { /* Avoid downstream problems: */ /* recast "_bF$bufN" as _X_bF$bufN" */ char *dptr = nodename + slen - 1; while (dptr >= nodename && *dptr != '<') dptr--; if (dptr >= nodename) *dptr = '_'; sprintf(spos, "_bF$buf%d", nl->curcount); } else { spos++; sprintf(spos, "_bF$buf%d", nl->curcount); } /* For buffer trees of depth > 1, there will be */ /* an existing node name wih the _bufN extension */ /* that is in the node hash table. If so, then */ /* add the prefix "_hierM". Test again in case */ /* the buffer tree is even deeper, incrementing M */ /* until the name is unique. */ nltest = (struct Nodelist *)HashLookup(nodename, Nodehash); if (nltest != NULL) { sprintf(nodename, "%s_hier%d", nl->nodename, hier); hier++; } } nl->curcount--; if (nl->curcount < 0) nl->curcount = nl->num_buf - 1; // Splice the suffix into the original line slen = strlen(nodename); s = strchr(inputline, '='); for (i = 1; i < pincount; i++) s = strchr(s + 1, '='); s++; while (*s == ' ' || *s == '\t') s++; memmove(s + slen - strlen(nl->nodename), s, strlen(s) + 1); strncpy(s, nodename, slen); } state = PINNAME; break; case OUTPUTNODE: if (VerboseFlag) printf("\nOutput node %s", t); nl = (struct Nodelist *)HashLookup(t, Nodehash); if (nl != NULL) { if ((nl->ignore == FALSE) && (nl->ratio > 1.0)) { if (VerboseFlag) printf("\nGate should be %g times stronger", nl->ratio); needscorrecting = TRUE; orig = gl->suffix; glbest = best_size(gl, nl->total_load + WireCap, NULL); if (glbest && VerboseFlag) printf("\nGate changed from %s to %s\n", gl->gatename, glbest->gatename); inv_size = nl->total_load; } // Is this node an output pin? Check required output drive. if ((nl->ignore == FALSE) && (nl->type == OUTPUTPIN)) { orig = gl->suffix; glbest = best_size(gl, nl->total_load + MaxOutputCap + WireCap, NULL); if (glbest && (glbest != gl)) { needscorrecting = TRUE; if (VerboseFlag) printf("\nOutput Gate changed from %s to %s\n", gl->gatename, glbest->gatename); } } // Don't attempt to correct gates for which we cannot find a suffix if (orig == NULL) needscorrecting = FALSE; } state = PINNAME; break; case ERROR: default: if (t[0] == '#') skip_eol = 1; if (!strcmp(t, ".gate")) state = GATENAME; break; } if (skip_eol == 1) { skip_eol = 0; break; } t = strtok(NULL, " \t=\n"); // Ignore continuation lines if (t && (!strcmp(t, "\\"))) t = strtok(NULL, " \t=\n"); if (state == GATENAME || state == ENDMODEL) { /* dump output for the last gate */ bufferline[0] = 0; if (needscorrecting) { if (glbest == NULL) { // return val to insert inverters if (VerboseFlag) printf("\nInsert buffers %s - %g\n", s, inv_size); s = strstr(gateline, nl->nodename); // get output node s = strtok(s, " \\\t"); // strip it clean if (*s == '[') { char *p = strchr(s, ']'); if (p != NULL) strcpy(p, "_bF$buf]\";\n"); // rename it else strcat(s, "_bF%buf\";\n"); } else strcat(s, "_bF$buf\";\n"); // rename it bbest = best_size(glbuf, inv_size + WireCap, NULL); /* If bbest->suffix is NULL, then we will have to break up */ /* this network. */ /* Buffer trees will be inserted by downstream tools, after */ /* analyzing the placement of the network. This error needs */ /* to be passed down to those tools. . . */ if (bbest == NULL) { fprintf(stderr, "Fatal error: No gates found for %s\n", glbuf->gatename); fprintf(stderr, "May need to add information to gate.cfg file\n"); } dl = (struct Drivelist *)HashLookup(bbest->suffix, Drivehash); if (dl != NULL) dl->NgatesOut++; /* Recompute size of the gate driving the buffer */ sprintf(bufferline, "%s", bbest->gatename); if (nl != NULL) { get_pincap(bbest->gatecell, buf_in_pin, &nl->total_load); if (gl != NULL) { nl->total_load += gl->Cint; } } orig = gl->suffix; glbest = best_size(gl, nl->total_load + WireCap, NULL); sprintf(bufferline, ".gate %s %s=%s %s=%s\n", bbest->gatename, buf_in_pin, s, buf_out_pin, nl->nodename); } if (gl != glbest) { s = strstr(gateline, gl->gatename); if (s) { int glen = strlen(gl->gatename); int slen = strlen(glbest->gatename); if (glen != slen) { // The size of the gatename increased, so reallocate if (slen > glen) { gateline = (char *)realloc(gateline, strlen(gateline) + 1 + slen - glen); s = strstr(gateline, gl->gatename); } memmove(s + slen, s + glen, strlen(s + glen) + 1); } strncpy(s, glbest->gatename, slen); Changed_count++; /* Adjust the gate count for "in" and "out" types */ count_gatetype(gl, 0, -1); count_gatetype(glbest, 0, 1); } } } else { stren = NULL; } if (strlen(gateline) > 0) gateline[strlen(gateline) - 1] = 0; fprintf(outfptr, "%s\n", gateline); fprintf(outfptr, "%s", bufferline); bufferline[0] = '\0'; gateline[0] = '\0'; /* Starting a new gate */ if (state == ENDMODEL) fprintf(outfptr, "%s", inputline); } else if (state == NONE) { /* Print line and reset so we don't overflow gateline */ fprintf(outfptr, "%s", gateline); gateline[0] = '\0'; /* Start a new line */ } } /* Append input line to gate */ gateline = (char *)realloc(gateline, strlen(gateline) + strlen(inputline) + 1); strcat(gateline, inputline); /* Append input line to gate */ } if (VerboseFlag) printf("\n"); fflush(stdout); } /* *--------------------------------------------------------------------------- * Return a pointer to the gate with the drive strength that is the * minimum necessary to drive the load "amount". * * If the load exceeds the available gate sizes, then return the maximum * strength gate available, and set "overload" to TRUE. Otherwise, FALSE * is returned in "overload". *--------------------------------------------------------------------------- */ struct Gatelist *best_size(struct Gatelist *gl, double amount, char *overload) { char *s; char ssave; int ind, i; double amax = 1.0E10; // Assuming no gate is this big! double gmax = 0.0; struct Gatelist *newgl, *glbest = NULL, *glsave = NULL; struct Baselist *bl; if (overload) *overload = FALSE; if ((s = gl->suffix) == NULL) return NULL; ind = (int)(s - gl->gatename); // Compare out to and including the suffix ssave = gl->gatename[ind]; gl->gatename[ind] = '\0'; bl = (struct Baselist *)HashLookup(gl->gatename, Basehash); gl->gatename[ind] = ssave; for (i = 0; bl && (i < bl->Ndrives); i++) { newgl = bl->gates[i]; if (newgl->strength >= gmax) { gmax = newgl->strength; glsave = newgl; } if (amount <= newgl->strength) { if (newgl->strength < amax) { if (newgl->suffix) { glbest = newgl; amax = newgl->strength; } } } } if (amax == 1.0E10) { double oratio; stren_err_counter++; if (overload) *overload = TRUE; if (glsave != NULL) glbest = glsave; else glbest = NULL; if (gmax > 0.0) { oratio = (double)(amount / gmax); if (oratio > MaxOverload) { fprintf(stderr, "Warning %d: load of %g is %g times greater " "than strongest gate %s\n", stren_err_counter, amount, oratio, glsave->gatename); if (MaxOverload == 0.0) fprintf(stderr, "This warning will only be repeated for " "larger overload ratios. Warning count reflects\n" "the total number of overloaded nets.\n"); MaxOverload = oratio; } } } return glbest; } /* *--------------------------------------------------------------------------- *--------------------------------------------------------------------------- */ void helpmessage(void) { printf("\nblifFanout:\n\n"); printf("blifFanout looks at a synthesized BLIF netlist.\n"); printf("Node fanout is measured, and gate size is adjusted.\n"); printf("File \"gate.cfg\" is used to describe the RTL gates.\n\n"); printf("\tUsage: blifFanout [-switches] blif_in [blif_out].\n\n"); printf("blifFanout returns the number of gate substitutions made.\n"); printf("Typically, it will be iterated until convergence (return value 0).\n\n"); printf("valid switches are:\n"); printf("\t-g\t\tDebug mode: parse and print the gate.cfg table\n"); printf("\t-n\t\tDebug mode: parse and print the node list\n"); printf("\t-v\t\tDebug mode: verbose output\n"); printf("\t-l latency\tSet the maximum variable latency (ps). (default %g)\n", MaxLatency); printf("\t-F value\tSet the maximum fanout per node (default %g)\n", MaxFanout); printf("\t-b buffername\tSet the name of a buffer gate\n"); printf("\t-s separator\tGate names have \"separator\" before drive strength\n"); printf("\t-o value\tSet the maximum output capacitance (fF). (default %g)\n", MaxOutputCap); printf("\t-p filepath\tSpecify an alternate path and filename for gate.cfg\n"); printf("\t-f filepath\tSpecify a path and filename for list of nets to ignore\n"); printf("\t-h\t\tprint this help message\n\n"); printf("This will not work at all for tristate gates.\n"); printf("Nodes with multiple outputs are assumed to be in parallel.\n"); } /* end of blifFanout.c */ qflow-1.1.23/src/readliberty.h0000644000175000001440000000426112526236535014720 0ustar timusers/*--------------------------------------------------------------*/ /* readliberty.h --- */ /* */ /* Header file for readliberty.c */ /*--------------------------------------------------------------*/ #define LIB_LINE_MAX 65535 #define INIT 0 #define LIBBLOCK 1 #define CELLDEF 2 #define PINDEF 3 #define TIMING 4 // Pin types #define PIN_UNKNOWN -1 #define PIN_INPUT 0 #define PIN_OUTPUT 1 // Function translation #define GROUPBEGIN 1 #define GROUPEND 2 #define SIGNAL 3 #define OPERATOR 4 #define XOPERATOR 5 #define SEPARATOR 6 /*--------------------------------------------------------------*/ /* Database */ /*--------------------------------------------------------------*/ typedef struct _lutable *lutableptr; typedef struct _lutable { char *name; char invert; // 0 if times x caps, 1 if caps x times char *var1; // Name of array in index1 char *var2; // Name of array in index2 int tsize; // Number of entries in time array int csize; // Number of entries in cap array double *times; // Time array (units fF) double *caps; // Cap array (units ps) lutableptr next; } LUTable; /*--------------------------------------------------------------*/ typedef struct _pin *pinptr; typedef struct _pin { char *name; int type; double cap; double maxtrans; double maxcap; pinptr next; } Pin; /*--------------------------------------------------------------*/ typedef struct _cell *cellptr; typedef struct _cell { char *name; char *function; Pin *pins; double area; double slope; double mintrans; LUTable *reftable; double *times; // Local values for time indexes, if given double *caps; // Local values for cap indexes, if given double *values; // Matrix of all values cellptr next; } Cell; /*--------------------------------------------------------------*/ extern int get_pintype(Cell *curcell, char *pinname); extern int get_pincap(Cell *curcell, char *pinname, double *retcap); extern int get_values(Cell *curcell, double *retdelay, double *retcap); extern Cell *read_liberty(char *libfile, char *pattern); /*--------------------------------------------------------------*/ qflow-1.1.23/src/hash.c0000644000175000001440000002646312526236535013340 0ustar timusers/* Hash table functions, originally for netgen Copyright (C) 1989, 1990 Massimo A. Sivilotti Modified for blifFanout by keeping hash table size constant. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation (any version). This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; see the file copying. If not, write to the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ /* hash.c -- hash table support functions */ #include #include /* For strdup() */ #include #include "hash.h" unsigned long (*hashfunc)(char *) = NULL; int (*matchfunc)(char *, char *) = NULL; int (*matchintfunc)(char *, char *, int, int) = NULL; /* Add match functions: These are just strcmp() and */ /* strcasecmp() with inverted outputs. */ int match(char *st1, char *st2) { if (!strcmp(st1, st2)) return 1; else return 0; } int matchnocase(char *st1, char *st2) { if (!strcasecmp(st1, st2)) return 1; else return 0; } void InitializeHashTable(struct hashlist **tab) { int i; for (i = 0; i < OBJHASHSIZE; i++) tab[i] = NULL; } int RecurseHashTable(struct hashlist **hashtab, int (*func)(struct hashlist *elem)) /* returns the sum of the return values of (*func) */ { int i, sum; struct hashlist *p; sum = 0; for (i = 0; i < OBJHASHSIZE; i++) for (p = hashtab[i]; p != NULL; p = p->next) sum += (*func)(p); return(sum); } /* Variation on RecurseHashTable() that passes an additional * type int value to the function. */ int RecurseHashTableValue(struct hashlist **hashtab, int (*func)(struct hashlist *elem, int), int value) { int i, sum; struct hashlist *p; sum = 0; for (i = 0; i < OBJHASHSIZE; i++) for (p = hashtab[i]; p != NULL; p = p->next) sum += (*func)(p, value); return(sum); } /* Another variation on RecurseHashTable() that passes one pointer * type value to the function, so that the pointer may be to a * structure, allowing any number of values to be passed to the * function through that structure. */ struct nlist *RecurseHashTablePointer(struct hashlist **hashtab, struct nlist *(*func)(struct hashlist *elem, void *), void *pointer) { int i; struct hashlist *p; struct nlist *tp; for (i = 0; i < OBJHASHSIZE; i++) { for (p = hashtab[i]; p != NULL; p = p->next) { tp = (*func)(p, pointer); if (tp != NULL) return tp; } } return NULL; } int CountHashTableEntries(struct hashlist *p) { return ((p != NULL) ? 1 : 0); } int CountHashTableBinsUsed(struct hashlist *p) { if (p->next == NULL) return (1); return(0); } static unsigned char uppercase[] = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 0x60, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f }; // Hash functions of the stupid-simple accumulate-the-character-codes // method replaced by the more sophisticated SDBM hash. Otherwise // horrible things can happen, as, for example, names AOI12 and OAI12 // have exactly the same hash result. Lousy for binning and even // lousier for generating class magic numbers. unsigned long hashnocase(char *s) { unsigned long hashval; for (hashval = 0; *s != '\0'; ) hashval = uppercase[*s++] + (hashval << 6) + (hashval << 16) - hashval; return (hashval % OBJHASHSIZE); } unsigned long hash(char *s) { unsigned long hashval; for (hashval = 0; *s != '\0'; ) hashval = (*s++) + (hashval << 6) + (hashval << 16) - hashval; return (hashval % OBJHASHSIZE); } /*----------------------------------------------------------------------*/ /* HashLookup -- */ /* return the 'ptr' field of the hash table entry, or NULL if not found */ /*----------------------------------------------------------------------*/ void *HashLookup(char *s, struct hashlist **hashtab) { struct hashlist *np; unsigned long hashval; hashval = (*hashfunc)(s); for (np = hashtab[hashval]; np != NULL; np = np->next) if ((*matchfunc)(s, np->name)) return (np->ptr); /* correct match */ return (NULL); /* not found */ } /*----------------------------------------------------------------------*/ /* HashIntLookup -- */ /* return the 'ptr' field of the hash table entry, or NULL if not found */ /* HashIntLookup treats *ptr as an integer and compares it to the */ /* passed integer value i */ /*----------------------------------------------------------------------*/ void *HashIntLookup(char *s, int i, struct hashlist **hashtab) { struct hashlist *np; unsigned long hashval; hashval = (*hashfunc)(s); for (np = hashtab[hashval]; np != NULL; np = np->next) { if (np->ptr == NULL) { if ((*matchintfunc)(s, np->name, i, -1)) return NULL; } else { if ((*matchintfunc)(s, np->name, i, (int)(*((int *)np->ptr)))) return (np->ptr); /* correct match */ } } return (NULL); /* not found */ } /*----------------------------------------------------------------------*/ /* return the hashlist entry, after (re)initializing its 'ptr' field */ /*----------------------------------------------------------------------*/ struct hashlist *HashPtrInstall(char *name, void *ptr, struct hashlist **hashtab) { struct hashlist *np; unsigned long hashval; hashval = (*hashfunc)(name); for (np = hashtab[hashval]; np != NULL; np = np->next) if ((*matchfunc)(name, np->name)) { np->ptr = ptr; return (np); /* match found in hash table */ } /* not in table, so install it */ if ((np = (struct hashlist *) calloc(1,sizeof(struct hashlist))) == NULL) return (NULL); if ((np->name = strdup(name)) == NULL) return (NULL); np->ptr = ptr; np->next = hashtab[hashval]; return(hashtab[hashval] = np); } /*----------------------------------------------------------------------*/ /* Like HashLookup, a separate routine is needed when using an */ /* additional value for the matching. */ /*----------------------------------------------------------------------*/ struct hashlist *HashIntPtrInstall(char *name, int value, void *ptr, struct hashlist **hashtab) { struct hashlist *np; unsigned long hashval; hashval = (*hashfunc)(name); for (np = hashtab[hashval]; np != NULL; np = np->next) if ((*matchintfunc)(name, np->name, value, (int)(*((int *)np->ptr)))) { np->ptr = ptr; return (np); /* match found in hash table */ } /* not in table, so install it */ if ((np = (struct hashlist *) calloc(1,sizeof(struct hashlist))) == NULL) return (NULL); if ((np->name = strdup(name)) == NULL) return (NULL); np->ptr = ptr; np->next = hashtab[hashval]; return(hashtab[hashval] = np); } /*----------------------------------------------------------------------*/ /* destroy a hash table, freeing associated memory */ /*----------------------------------------------------------------------*/ void *HashKill(struct hashlist **hashtab) { struct hashlist *np, *p; int i; for (i = 0; i < OBJHASHSIZE; i++) { for (p = hashtab[i]; p != NULL; ) { np = p->next; free(p->name); free(p); p = np; } } } /*----------------------------------------------------------------------*/ /* Basic hash install, leaving a NULL pointer but returning a pointer */ /* to the new hash entry. */ /*----------------------------------------------------------------------*/ struct hashlist *HashInstall(char *name, struct hashlist **hashtab) { struct hashlist *np; unsigned long hashval; hashval = (*hashfunc)(name); for (np = hashtab[hashval]; np != NULL; np = np->next) if ((*matchfunc)(name, np->name)) return (np); /* match found in hash table */ /* not in table, so install it */ if ((np = (struct hashlist *) calloc(1,sizeof(struct hashlist))) == NULL) return (NULL); if ((np->name = strdup(name)) == NULL) return (NULL); np->ptr = NULL; np->next = hashtab[hashval]; return(hashtab[hashval] = np); } /*----------------------------------------------------------------------*/ /* frees a hash table entry, (but not the 'ptr' field) */ /*----------------------------------------------------------------------*/ void HashDelete(char *name, struct hashlist **hashtab) { unsigned long hashval; struct hashlist *np; struct hashlist *np2; hashval = (*hashfunc)(name); np = hashtab[hashval]; if (np == NULL) return; if ((*matchfunc)(name, np->name)) { /* it is the first element in the list */ hashtab[hashval] = np->next; free(np->name); free(np); return; } /* else, traverse the list, deleting the appropriate element */ while (np->next != NULL) { if ((*matchfunc)(name, np->next->name)) { np2 = np->next; np->next = np2->next; free(np2->name); free(np2); return; } np = np->next; } } /*----------------------------------------------------------------------*/ /* HashDelete with additional integer value matching */ /*----------------------------------------------------------------------*/ void HashIntDelete(char *name, int value, struct hashlist **hashtab) { unsigned long hashval; struct hashlist *np; struct hashlist *np2; hashval = (*hashfunc)(name); np = hashtab[hashval]; if (np == NULL) return; if ((*matchintfunc)(name, np->name, value, (int)(*((int *)np->ptr)))) { /* it is the first element in the list */ hashtab[hashval] = np->next; free(np->name); free(np); return; } /* else, traverse the list, deleting the appropriate element */ while (np->next != NULL) { if ((*matchintfunc)(name, np->next->name, value, (int)(*((int *)np->next->ptr)))) { np2 = np->next; np->next = np2->next; free(np2->name); free(np2); return; } np = np->next; } } /*----------------------------------------------------------------------*/ static int hashfirstindex; /* was long */ static struct hashlist *hashfirstptr; void *HashNext(struct hashlist **hashtab) /* returns 'ptr' field of next element, NULL when done */ { if (hashfirstptr != NULL && hashfirstptr->next != NULL) { hashfirstptr = hashfirstptr->next; return(hashfirstptr->ptr); } while (hashfirstindex < OBJHASHSIZE) { if ((hashfirstptr = hashtab[hashfirstindex++]) != NULL) { return(hashfirstptr->ptr); } } hashfirstindex = 0; hashfirstptr = NULL; return(NULL); } void *HashFirst(struct hashlist **hashtab) { hashfirstindex = 0; hashfirstptr = NULL; return(HashNext(hashtab)); } qflow-1.1.23/src/readliberty.c0000664000175000001440000010431212610210625014675 0ustar timusers/*--------------------------------------------------------------*/ /* readliberty.c --- */ /* */ /* Routines to parse a liberty file for cell information to be */ /* used by blifFanout for timing adjustments and clock tree/ */ /* buffer tree insertion. */ /*--------------------------------------------------------------*/ #include #include #include #include #include #include #include "readliberty.h" /*--------------------------------------------------------------*/ int libCurrentLine; /*--------------------------------------------------------------*/ /* Grab a token from the input */ /* Return the token, or NULL if we have reached end-of-file. */ /*--------------------------------------------------------------*/ char * advancetoken(FILE *flib, char delimiter) { static char token[LIB_LINE_MAX]; static char line[LIB_LINE_MAX]; static char *linepos = NULL; char *lineptr = linepos; char *lptr, *tptr; char *result; int commentblock, concat, nest; commentblock = 0; concat = 0; nest = 0; while (1) { /* Keep processing until we get a token or hit EOF */ if (lineptr != NULL && *lineptr == '/' && *(lineptr + 1) == '*') { commentblock = 1; } if (commentblock == 1) { if ((lptr = strstr(lineptr, "*/")) != NULL) { lineptr = lptr + 2; commentblock = 0; } else lineptr = NULL; } if (lineptr == NULL || *lineptr == '\n' || *lineptr == '\0') { result = fgets(line, LIB_LINE_MAX, flib); libCurrentLine++; if (result == NULL) return NULL; /* Keep pulling stuff in if the line ends with a continuation character */ lptr = line; while (*lptr != '\n' && *lptr != '\0') { if (*lptr == '\\') { // If there is anything besides whitespace between the // backslash and end-of-line, then don't treat as a // continuation character. char *eptr = lptr + 1; while (isspace(*eptr)) eptr++; if (*eptr == '\0') { result = fgets(lptr, LIB_LINE_MAX - (lptr - line), flib); libCurrentLine++; if (result == NULL) break; } else lptr++; } else lptr++; } if (result == NULL) return NULL; lineptr = line; } if (commentblock == 1) continue; while (isspace(*lineptr)) lineptr++; if (concat == 0) tptr = token; // Find the next token and return just the token. Update linepos // to the position just beyond the token. All delimiters like // parentheses, quotes, etc., are returned as single tokens // If delimiter is declared, then we stop when we reach the // delimiter character, and return all the text preceding it // as the token. If delimiter is 0, then we look for standard // delimiters, and separate them out and return them as tokens // if found. while (1) { if (*lineptr == '\n' || *lineptr == '\0') break; if (*lineptr == '/' && *(lineptr + 1) == '*') break; if (delimiter != 0 && *lineptr == delimiter) { if (nest > 0) nest--; else break; } // Watch for nested delimiters! if (delimiter == '}' && *lineptr == '{') nest++; if (delimiter == ')' && *lineptr == '(') nest++; if (delimiter == 0) if (*lineptr == ' ' || *lineptr == '\t') break; if (delimiter == 0) { if (*lineptr == '(' || *lineptr == ')') { if (tptr == token) *tptr++ = *lineptr++; break; } if (*lineptr == '{' || *lineptr == '}') { if (tptr == token) *tptr++ = *lineptr++; break; } if (*lineptr == '\"' || *lineptr == ':' || *lineptr == ';') { if (tptr == token) *tptr++ = *lineptr++; break; } } *tptr++ = *lineptr++; } *tptr = '\0'; if ((delimiter != 0) && (*lineptr != delimiter)) concat = 1; else if ((delimiter != 0) && (*lineptr == delimiter)) break; else if (tptr > token) break; } if (delimiter != 0) lineptr++; while (isspace(*lineptr)) lineptr++; linepos = lineptr; // Final: Remove trailing whitespace tptr = token + strlen(token) - 1; while (isspace(*tptr)) { *tptr = '\0'; tptr--; } return token; } /*--------------------------------------------------------------*/ /* Expansion of XOR operator "^" into and/or/invert */ /*--------------------------------------------------------------*/ char * xor_expand(char *lib_func) { static char newfunc[16384]; char savfunc[16384]; char *xptr, *sptr, *fptr, *rest, *start; int nest, lhsnests, rhsnests; char *rhs = NULL; char *lhs = NULL; strcpy(newfunc, lib_func); while ((xptr = strchr(newfunc, '^')) != NULL) { /* find expression on RHS */ sptr = xptr + 1; while (*sptr == ' ' || *sptr == '\t') sptr++; fptr = sptr; rhsnests = 0; if (*sptr == '(') { rhsnests = 1; nest = 1; while ((*sptr != ')') || (nest > 0)) { sptr++; if (*sptr == '(') nest++; if (*sptr == ')') nest--; } } else { while (*sptr != ' ' && *sptr != '\t' && *sptr != '\0' && *sptr != ')') sptr++; if (*sptr == ')') sptr--; } // If argument is a single character, then don't bother with parentheses if (sptr - fptr == 0) rhsnests = 1; if (rhsnests == 1) { rhs = (char *)malloc(sptr - fptr + 2); strncpy(rhs, fptr, sptr - fptr + 1); *(rhs + (int)(sptr - fptr + 1)) = '\0'; } else { /* Add parentheses around RHS */ rhs = (char *)malloc(sptr - fptr + 4); *rhs = '('; strncpy(rhs + 1, fptr, sptr - fptr + 1); *(rhs + (int)(sptr - fptr + 2)) = ')'; *(rhs + (int)(sptr - fptr + 3)) = '\0'; } rest = sptr + 1; /* find expression on LHS */ sptr = xptr - 1; while (*sptr == ' ' || *sptr == '\t') sptr--; fptr = sptr; lhsnests = 0; if (*sptr == ')') { lhsnests = 1; nest = 1; while ((*sptr != '(') || (nest > 0)) { sptr--; if (*sptr == ')') nest++; if (*sptr == '(') nest--; } } else { while (*sptr != ' ' && *sptr != '\t' && sptr != lib_func && *sptr != '(') sptr--; if (*sptr == '(') sptr++; } // If argument is a single character, then don't bother with parentheses if (fptr - sptr == 0) lhsnests = 1; if (lhsnests == 1) { lhs = (char *)malloc(fptr - sptr + 2); strncpy(lhs, sptr, fptr - sptr + 1); *(lhs + (int)(fptr - sptr + 1)) = '\0'; } else { lhs = (char *)malloc(fptr - sptr + 4); *lhs = '('; strncpy(lhs + 1, sptr, fptr - sptr + 1); *(lhs + (int)(fptr - sptr + 2)) = ')'; *(lhs + (int)(fptr - sptr + 3)) = '\0'; } strcpy(savfunc, newfunc); start = savfunc + (sptr - newfunc); sprintf(start, "(%s*!%s + !%s*%s) %s", lhs, rhs, lhs, rhs, rest); if (rhs != NULL) free(rhs); if (lhs != NULL) free(lhs); strcpy(newfunc, savfunc); } return newfunc; } /*--------------------------------------------------------------*/ /* Turn a liberty-format function string into one recognized by */ /* genlib. This means, for the most part, replacing forms of */ /* "A B" with "A * B", and "A ^ B" with "A * !B + !A * B" */ /*--------------------------------------------------------------*/ char * get_function(char *out_name, char *lib_func) { static char newfunc[16384]; char *fptr, *sptr; int nest; int state = INIT; fptr = newfunc; sptr = out_name; while (*sptr != '\0') *fptr++ = *sptr++; *fptr++ = ' '; *fptr++ = '='; *fptr++ = ' '; sptr = xor_expand(lib_func); // genlib can't handle "^" while (*sptr != '\0') { if (*sptr == '(') { if (state == SIGNAL || state == GROUPEND) { *fptr++ = '*'; // Implicit AND; genlib wants to see *fptr++ = ' '; // this written out explicitly. } state = GROUPBEGIN; *fptr++ = *sptr++; } else if (*sptr == ')') { state = GROUPEND; *fptr++ = *sptr++; } else if (*sptr == '!' || *sptr == '*' || *sptr == '+' || *sptr == '\'') { state = OPERATOR; *fptr++ = *sptr++; } else if (*sptr == ' ' || *sptr == '\t') { if (state == SIGNAL) { state = SEPARATOR; } *fptr++ = *sptr++; } else if (*sptr == '^') { state = XOPERATOR; } else { if (state == SEPARATOR || state == GROUPEND) { *fptr++ = '*'; // Implicit AND; genlib wants to see *fptr++ = ' '; // this written out explicitly. } state = SIGNAL; *fptr++ = *sptr++; } } *fptr = '\0'; // Process single-quote-as-inversion. That is, A' --> !A // The number of characters remains the same, so we can apply // the changes directly to newfunc with careful use of memmove while ((sptr = strchr(newfunc, '\'')) != NULL) { fptr = sptr - 1; while (isspace(*fptr)) fptr--; if (*fptr == ')') { nest = 1; while (nest > 0) { fptr--; if (*fptr == ')') nest++; else if (*fptr == '(') nest--; else if (fptr == newfunc) break; } } else { while (*fptr != '!' && *fptr != '*' && *fptr != '+' && !isspace(*fptr) && (fptr > newfunc) && *fptr != '(' && *fptr != ')') fptr--; if (fptr > newfunc) fptr++; } memmove(fptr + 1, fptr, (size_t)(sptr - fptr)); *fptr = '!'; } return newfunc; } /*--------------------------------------------------------------*/ /* Name pattern matching. This is used to restrict the */ /* entries that are placed in genlib. It understands a few */ /* wildcard characters: "^" (matches beginning-of-string), and */ /* "$" (matches end-of-string). */ /* */ /* May want to add "|" and "&" (OR, AND) functions, but maybe */ /* it's not necessary. Also standard wildcards like "." and */ /* "*". */ /*--------------------------------------------------------------*/ int pattern_match(char *name, char *pattern) { char *sptr; int plen = strlen(pattern); int rval = 0; int matchend = 0; if (*(pattern + plen - 1) == '$') { matchend = 1; *(pattern + plen - 1) = '\0'; } if (*pattern == '^') { sptr = pattern + 1; if (matchend) { if (!strcmp(name, sptr)) rval = 1; else rval = 0; } else { if (!strncmp(name, sptr, plen - 2)) rval = 1; else rval = 0; } } else { if (matchend) { sptr = name + strlen(name) - plen + 1; if (!strcmp(sptr, pattern)) rval = 1; else rval = 0; } else { if (strstr(name, pattern) != NULL) rval = 1; else rval = 0; } } if (matchend) *(pattern + plen - 1) = '$'; return rval; } /*--------------------------------------------------------------*/ /* Read the liberty file and generate the cell database */ /* If "pattern" is non-NULL, then use the pattern to filter the */ /* cell results. */ /*--------------------------------------------------------------*/ Cell * read_liberty(char *libfile, char *pattern) { FILE *flib; char *token; char *libname = NULL; int section = INIT; LUTable *tables = NULL; Cell *cells = NULL; double time_unit = 1.0; // Time unit multiplier, to get ps double cap_unit = 1.0; // Capacitive unit multiplier, to get fF int i, j; double gval; char *iptr; LUTable *newtable, *reftable, *scalar; Cell *newcell, *lastcell; Pin *newpin, *lastpin; char *curfunc; flib = fopen(libfile, "r"); if (flib == NULL) { fprintf(stderr, "Cannot open %s for reading\n", libfile); return NULL; } /* Generate one table template for the "scalar" case */ scalar = (LUTable *)malloc(sizeof(LUTable)); scalar->name = strdup("scalar"); scalar->invert = 0; scalar->var1 = strdup("transition"); scalar->var2 = strdup("capacitance"); scalar->tsize = 1; scalar->csize = 1; scalar->times = (double *)malloc(sizeof(double)); scalar->caps = (double *)malloc(sizeof(double)); scalar->times[0] = 0.0; scalar->caps[0] = 0.0; scalar->next = NULL; tables = scalar; /* Read the file. This is not a rigorous parser! */ libCurrentLine = 0; lastcell = NULL; /* Read tokens off of the line */ token = advancetoken(flib, 0); while (token != NULL) { switch (section) { case INIT: if (!strcasecmp(token, "library")) { token = advancetoken(flib, 0); if (strcmp(token, "(")) fprintf(stderr, "Library not followed by name\n"); else token = advancetoken(flib, ')'); fprintf(stderr, "Parsing library \"%s\"\n", token); libname = strdup(token); token = advancetoken(flib, 0); if (strcmp(token, "{")) { fprintf(stderr, "Did not find opening brace " "on library block\n"); exit(1); } section = LIBBLOCK; } else fprintf(stderr, "Unknown input \"%s\", looking for " "\"library\"\n", token); break; case LIBBLOCK: // Here we check for the main blocks, again not rigorously. . . if (!strcasecmp(token, "}")) { fprintf(stdout, "End of library at line %d\n", libCurrentLine); section = INIT; // End of library block } else if (!strcasecmp(token, "delay_model")) { token = advancetoken(flib, 0); if (strcmp(token, ":")) fprintf(stderr, "Input missing colon\n"); token = advancetoken(flib, ';'); if (strcasecmp(token, "table_lookup")) { fprintf(stderr, "Sorry, only know how to " "handle table lookup!\n"); exit(1); } } else if (!strcasecmp(token, "lu_table_template")) { // Read in template information; newtable = (LUTable *)malloc(sizeof(LUTable)); newtable->var1 = NULL; newtable->var2 = NULL; newtable->tsize = 0; newtable->csize = 0; newtable->times = NULL; newtable->caps = NULL; newtable->next = tables; tables = newtable; token = advancetoken(flib, 0); if (strcmp(token, "(")) fprintf(stderr, "Input missing open parens\n"); else token = advancetoken(flib, ')'); newtable->name = strdup(token); while (*token != '}') { token = advancetoken(flib, 0); if (!strcasecmp(token, "variable_1")) { token = advancetoken(flib, 0); token = advancetoken(flib, ';'); newtable->var1 = strdup(token); if (strstr(token, "capacitance") != NULL) newtable->invert = 1; } else if (!strcasecmp(token, "variable_2")) { token = advancetoken(flib, 0); token = advancetoken(flib, ';'); newtable->var2 = strdup(token); if (strstr(token, "transition") != NULL) newtable->invert = 1; } else if (!strcasecmp(token, "index_1")) { token = advancetoken(flib, 0); // Open parens token = advancetoken(flib, 0); // Quote if (!strcmp(token, "\"")) token = advancetoken(flib, '\"'); if (newtable->invert == 1) { // Count entries iptr = token; newtable->csize = 1; while ((iptr = strchr(iptr, ',')) != NULL) { iptr++; newtable->csize++; } newtable->caps = (double *)malloc(newtable->csize * sizeof(double)); newtable->csize = 0; iptr = token; sscanf(iptr, "%lg", &newtable->caps[0]); newtable->caps[0] *= cap_unit; while ((iptr = strchr(iptr, ',')) != NULL) { iptr++; newtable->csize++; sscanf(iptr, "%lg", &newtable->caps[newtable->csize]); newtable->caps[newtable->csize] *= cap_unit; } newtable->csize++; } else { // newtable->invert = 0 // Count entries iptr = token; newtable->tsize = 1; while ((iptr = strchr(iptr, ',')) != NULL) { iptr++; newtable->tsize++; } newtable->times = (double *)malloc(newtable->tsize * sizeof(double)); newtable->tsize = 0; iptr = token; sscanf(iptr, "%lg", &newtable->times[0]); newtable->times[0] *= time_unit; while ((iptr = strchr(iptr, ',')) != NULL) { iptr++; newtable->tsize++; sscanf(iptr, "%lg", &newtable->times[newtable->tsize]); newtable->times[newtable->tsize] *= time_unit; } newtable->tsize++; } token = advancetoken(flib, ';'); // EOL semicolon } else if (!strcasecmp(token, "index_2")) { token = advancetoken(flib, 0); // Open parens token = advancetoken(flib, 0); // Quote if (!strcmp(token, "\"")) token = advancetoken(flib, '\"'); if (newtable->invert == 0) { // Count entries iptr = token; newtable->csize = 1; while ((iptr = strchr(iptr, ',')) != NULL) { iptr++; newtable->csize++; } newtable->caps = (double *)malloc(newtable->csize * sizeof(double)); newtable->csize = 0; iptr = token; sscanf(iptr, "%lg", &newtable->caps[0]); newtable->caps[0] *= cap_unit; while ((iptr = strchr(iptr, ',')) != NULL) { iptr++; newtable->csize++; sscanf(iptr, "%lg", &newtable->caps[newtable->csize]); newtable->caps[newtable->csize] *= cap_unit; } newtable->csize++; } else { // newtable->invert == 1 // Count entries iptr = token; newtable->tsize = 1; while ((iptr = strchr(iptr, ',')) != NULL) { iptr++; newtable->tsize++; } newtable->times = (double *)malloc(newtable->tsize * sizeof(double)); newtable->tsize = 0; iptr = token; sscanf(iptr, "%lg", &newtable->times[0]); newtable->times[0] *= time_unit; while ((iptr = strchr(iptr, ',')) != NULL) { iptr++; newtable->tsize++; sscanf(iptr, "%lg", &newtable->times[newtable->tsize]); newtable->times[newtable->tsize] *= time_unit; } newtable->tsize++; } token = advancetoken(flib, ';'); // EOL semicolon } } } else if (!strcasecmp(token, "cell")) { newcell = (Cell *)malloc(sizeof(Cell)); newcell->next = NULL; if (lastcell != NULL) lastcell->next = newcell; else cells = newcell; lastcell = newcell; token = advancetoken(flib, 0); // Open parens if (!strcmp(token, "(")) token = advancetoken(flib, ')'); // Cellname newcell->name = strdup(token); token = advancetoken(flib, 0); // Find start of block if (strcmp(token, "{")) fprintf(stderr, "Error: failed to find start of block\n"); newcell->reftable = NULL; newcell->function = NULL; newcell->pins = NULL; newcell->area = 1.0; newcell->slope = 1.0; newcell->mintrans = 0.0; newcell->times = NULL; newcell->caps = NULL; newcell->values = NULL; lastpin = NULL; section = CELLDEF; } else if (!strcasecmp(token, "time_unit")) { char *metric; token = advancetoken(flib, 0); if (token == NULL) break; if (!strcmp(token, ":")) { token = advancetoken(flib, 0); if (token == NULL) break; } if (!strcmp(token, "\"")) { token = advancetoken(flib, '\"'); if (token == NULL) break; } time_unit = strtod(token, &metric); if (*metric != '\0') { if (!strcmp(metric, "ns")) time_unit *= 1E3; else if (!strcmp(metric, "us")) time_unit *= 1E6; else if (!strcmp(metric, "fs")) time_unit *= 1E-3; else if (strcmp(metric, "ps")) fprintf(stderr, "Don't understand time units \"%s\"\n", token); } else { token = advancetoken(flib, 0); if (token == NULL) break; if (!strcmp(token, "ns")) time_unit *= 1E3; else if (!strcmp(token, "us")) time_unit *= 1E6; else if (!strcmp(token, "fs")) time_unit *= 1E-3; else if (strcmp(token, "ps")) fprintf(stderr, "Don't understand time units \"%s\"\n", token); } token = advancetoken(flib, ';'); } else if (!strcasecmp(token, "capacitive_load_unit")) { char *metric; token = advancetoken(flib, 0); if (token == NULL) break; if (!strcmp(token, "(")) { token = advancetoken(flib, ')'); if (token == NULL) break; } cap_unit = strtod(token, &metric); if (*metric != '\0') { while (isspace(*metric)) metric++; if (*metric == ',') metric++; while ((*metric != '\0') && isspace(*metric)) metric++; if (!strcasecmp(metric, "af")) cap_unit *= 1E-3; else if (!strcasecmp(metric, "pf")) cap_unit *= 1000; else if (!strcasecmp(metric, "nf")) cap_unit *= 1E6; else if (!strcasecmp(metric, "uf")) cap_unit *= 1E9; else if (strcasecmp(metric, "ff")) fprintf(stderr, "Don't understand capacitive units \"%s\"\n", token); } else { token = advancetoken(flib, 0); if (token == NULL) break; if (!strcasecmp(token, "af")) cap_unit *= 1E-3; else if (!strcasecmp(token, "pf")) cap_unit *= 1000; else if (!strcasecmp(token, "nf")) cap_unit *= 1E6; else if (!strcasecmp(token, "uf")) cap_unit *= 1E9; else if (strcasecmp(token, "ff")) fprintf(stderr, "Don't understand capacitive units \"%s\"\n", token); } token = advancetoken(flib, ';'); } else { // For unhandled tokens, read in tokens. If it is // a definition or function, read to end-of-line. If // it is a block definition, read to end-of-block. while (1) { token = advancetoken(flib, 0); if (token == NULL) break; if (!strcmp(token, ";")) break; if (!strcmp(token, "\"")) token = advancetoken(flib, '\"'); if (!strcmp(token, "{")) { token = advancetoken(flib, '}'); break; } } } break; case CELLDEF: if (!strcmp(token, "}")) { section = LIBBLOCK; // End of cell def } else if (!strcasecmp(token, "dont_use")) { free(newcell->name); newcell->name == NULL; } else if (!strcasecmp(token, "pin")) { token = advancetoken(flib, 0); // Open parens if (!strcmp(token, "(")) token = advancetoken(flib, ')'); // Close parens newpin = (Pin *)malloc(sizeof(Pin)); newpin->name = strdup(token); newpin->next = NULL; if (lastpin != NULL) lastpin->next = newpin; else newcell->pins = newpin; lastpin = newpin; token = advancetoken(flib, 0); // Find start of block if (strcmp(token, "{")) fprintf(stderr, "Error: failed to find start of block\n"); newpin->type = PIN_UNKNOWN; newpin->cap = 0.0; newpin->maxcap = 0.0; newpin->maxtrans = 0.0; section = PINDEF; } else if (!strcasecmp(token, "area")) { token = advancetoken(flib, 0); // Colon token = advancetoken(flib, ';'); // To end-of-statement sscanf(token, "%lg", &newcell->area); } else { // For unhandled tokens, read in tokens. If it is // a definition or function, read to end-of-line. If // it is a block definition, read to end-of-block. while (1) { token = advancetoken(flib, 0); if (token == NULL) break; if (!strcmp(token, ";")) break; if (!strcmp(token, "\"")) token = advancetoken(flib, '\"'); if (!strcmp(token, "{")) { token = advancetoken(flib, '}'); break; } } } break; case PINDEF: if (!strcmp(token, "}")) { section = CELLDEF; // End of pin def } else if (!strcasecmp(token, "capacitance")) { token = advancetoken(flib, 0); // Colon token = advancetoken(flib, ';'); // To end-of-statement sscanf(token, "%lg", &newpin->cap); newpin->cap *= cap_unit; } else if (!strcasecmp(token, "function")) { token = advancetoken(flib, 0); // Colon token = advancetoken(flib, 0); // Open quote if (!strcmp(token, "\"")) token = advancetoken(flib, '\"'); // Find function string if (newpin->type == PIN_OUTPUT) { char *rfunc = get_function(newpin->name, token); newcell->function = strdup(rfunc); } token = advancetoken(flib, 0); if (strcmp(token, ";")) { if (!strcmp(token, "}")) section = CELLDEF; else fprintf(stderr, "Expected end-of-statement.\n"); } } else if (!strcasecmp(token, "direction")) { token = advancetoken(flib, 0); // Colon token = advancetoken(flib, ';'); if (!strcasecmp(token, "input")) { newpin->type = PIN_INPUT; } else if (!strcasecmp(token, "output")) { newpin->type = PIN_OUTPUT; } } else if (!strcasecmp(token, "max_transition")) { token = advancetoken(flib, 0); // Colon token = advancetoken(flib, ';'); // To end-of-statement sscanf(token, "%lg", &newpin->maxtrans); newpin->maxtrans *= time_unit; } else if (!strcasecmp(token, "max_capacitance")) { token = advancetoken(flib, 0); // Colon token = advancetoken(flib, ';'); // To end-of-statement sscanf(token, "%lg", &newpin->maxcap); newpin->maxcap *= cap_unit; } else if (!strcasecmp(token, "timing")) { token = advancetoken(flib, 0); // Arguments, if any if (strcmp(token, "(")) fprintf(stderr, "Error: failed to find start of block\n"); else token = advancetoken(flib, ')'); // Arguments, if any token = advancetoken(flib, 0); // Find start of block if (strcmp(token, "{")) fprintf(stderr, "Error: failed to find start of block\n"); section = TIMING; } else { // For unhandled tokens, read in tokens. If it is // a definition or function, read to end-of-line. If // it is a block definition, read to end-of-block. while (1) { token = advancetoken(flib, 0); if (token == NULL) break; if (!strcmp(token, ";")) break; if (!strcmp(token, "\"")) token = advancetoken(flib, '\"'); if (!strcmp(token, "{")) { token = advancetoken(flib, '}'); break; } } } break; case TIMING: if (!strcmp(token, "}")) { section = PINDEF; // End of timing def } else if (!strcasecmp(token, "cell_rise")) { token = advancetoken(flib, 0); // Open parens if (!strcmp(token, "(")) token = advancetoken(flib, ')'); for (reftable = tables; reftable; reftable = reftable->next) if (!strcmp(reftable->name, token)) break; if (reftable == NULL) fprintf(stderr, "Failed to find a valid table \"%s\"\n", token); else if (newcell->reftable == NULL) newcell->reftable = reftable; token = advancetoken(flib, 0); if (strcmp(token, "{")) fprintf(stderr, "Failed to find start of cell_rise block\n"); while (*token != '}') { token = advancetoken(flib, 0); if (!strcasecmp(token, "index_1")) { // Local index values override those in the template token = advancetoken(flib, 0); // Open parens token = advancetoken(flib, 0); // Quote if (!strcmp(token, "\"")) token = advancetoken(flib, '\"'); //------------------------- if (reftable && (reftable->invert == 1)) { // Entries had better match the ref table iptr = token; i = 0; newcell->caps = (double *)malloc(reftable->csize * sizeof(double)); sscanf(iptr, "%lg", &newcell->caps[0]); newcell->caps[0] *= cap_unit; while ((iptr = strchr(iptr, ',')) != NULL) { iptr++; i++; sscanf(iptr, "%lg", &newcell->caps[i]); newcell->caps[i] *= cap_unit; } } else if (reftable && (reftable->invert == 0)) { iptr = token; i = 0; newcell->times = (double *)malloc(reftable->tsize * sizeof(double)); sscanf(iptr, "%lg", &newcell->times[0]); newcell->times[0] *= time_unit; while ((iptr = strchr(iptr, ',')) != NULL) { iptr++; i++; sscanf(iptr, "%lg", &newcell->times[i]); newcell->times[i] *= time_unit; } } token = advancetoken(flib, ')'); // Close paren token = advancetoken(flib, ';'); // EOL semicolon } else if (!strcasecmp(token, "index_2")) { // Local index values override those in the template token = advancetoken(flib, 0); // Open parens token = advancetoken(flib, 0); // Quote if (!strcmp(token, "\"")) token = advancetoken(flib, '\"'); //------------------------- if (reftable && (reftable->invert == 1)) { // Entries had better match the ref table iptr = token; i = 0; newcell->times = (double *)malloc(reftable->tsize * sizeof(double)); sscanf(iptr, "%lg", &newcell->times[0]); newcell->times[0] *= time_unit; while ((iptr = strchr(iptr, ',')) != NULL) { iptr++; i++; sscanf(iptr, "%lg", &newcell->times[i]); newcell->times[i] *= time_unit; } } else if (reftable && (reftable->invert == 0)) { iptr = token; i = 0; newcell->caps = (double *)malloc(reftable->csize * sizeof(double)); sscanf(iptr, "%lg", &newcell->caps[0]); newcell->caps[0] *= cap_unit; while ((iptr = strchr(iptr, ',')) != NULL) { iptr++; i++; sscanf(iptr, "%lg", &newcell->caps[i]); newcell->caps[i] *= cap_unit; } } token = advancetoken(flib, ')'); // Close paren token = advancetoken(flib, ';'); // EOL semicolon } else if (!strcasecmp(token, "values")) { token = advancetoken(flib, 0); if (strcmp(token, "(")) fprintf(stderr, "Failed to find start of" " value table\n"); token = advancetoken(flib, ')'); // Parse the string of values and enter it into the // table "values", which is size csize x tsize if (reftable && reftable->csize > 0 && reftable->tsize > 0) { if (reftable->invert) { newcell->values = (double *)malloc(reftable->csize * reftable->tsize * sizeof(double)); iptr = token; for (i = 0; i < reftable->tsize; i++) { for (j = 0; j < reftable->csize; j++) { while (*iptr == ' ' || *iptr == '\"' || *iptr == ',') iptr++; sscanf(iptr, "%lg", &gval); *(newcell->values + j * reftable->tsize + i) = gval * time_unit; while (*iptr != ' ' && *iptr != '\"' && *iptr != ',') iptr++; } } } else { newcell->values = (double *)malloc(reftable->csize * reftable->tsize * sizeof(double)); iptr = token; for (j = 0; j < reftable->csize; j++) { for (i = 0; i < reftable->tsize; i++) { while (*iptr == ' ' || *iptr == '\"' || *iptr == ',') iptr++; sscanf(iptr, "%lg", &gval); *(newcell->values + j * reftable->tsize + i) = gval * time_unit; while (*iptr != ' ' && *iptr != '\"' && *iptr != ',') iptr++; } } } } token = advancetoken(flib, 0); if (strcmp(token, ";")) fprintf(stderr, "Failed to find end of value table\n"); token = advancetoken(flib, 0); } else if (strcmp(token, "{")) fprintf(stderr, "Failed to find end of timing block\n"); } } else { // For unhandled tokens, read in tokens. If it is // a definition or function, read to end-of-line. If // it is a block definition, read to end-of-block. while (1) { token = advancetoken(flib, 0); if (token == NULL) break; if (!strcmp(token, ";")) break; if (!strcmp(token, "\"")) token = advancetoken(flib, '\"'); if (!strcmp(token, "{")) { token = advancetoken(flib, '}'); break; } } } break; } token = advancetoken(flib, 0); } fprintf(stdout, "Lib Read: Processed %d lines.\n", libCurrentLine); if (flib != NULL) fclose(flib); return cells; } /*----------------------------------------------------------------------*/ /* Get the propagation delay and internal capacitance of the specified */ /* cell. Return the delay in "retdelay", and the capacitance in */ /* "retcap". Return 0 on success, or -1 on error. */ /*----------------------------------------------------------------------*/ int get_values(Cell *curcell, double *retdelay, double *retcap) { double *times, *caps; double mintrans, mincap, maxcap, mintrise, maxtrise; double loaddelay, intcap; // If this cell does not have a timing table or timing values, ignore it. if (curcell->reftable == NULL || curcell->values == NULL) return -1; if (curcell->times != NULL) times = curcell->times; else times = curcell->reftable->times; if (curcell->caps != NULL) caps = curcell->caps; else caps = curcell->reftable->caps; // Find the smallest value in the input net transition table. // Assume it is the first value, therefore we want to parse the // first row of the cell table. If that's not true, then we need // to add more sophisticated parsing code here! mintrans = *times; // Find the smallest and largest values in the output net capacitance table mincap = *caps; maxcap = *(caps + curcell->reftable->csize - 1); // Pick up values for rise time under maximum and minimum loads in // the template. mintrise = *curcell->values; maxtrise = *(curcell->values + curcell->reftable->csize - 1); // Calculate delay per load. Note that cap at this point should be // in fF, and trise should be in ps. // So the value of loaddelay is in ps/fF. loaddelay = (maxtrise - mintrise) / (maxcap - mincap); curcell->slope = loaddelay; curcell->mintrans = mintrise; // Calculate internal capacitance // risetime is ps, so (risetime / loaddelay) is fF. // mincap is in fF. intcap = (mintrise / loaddelay) - mincap; // Pass values back to caller if (retdelay != NULL) *retdelay = loaddelay; if (retcap != NULL) *retcap = intcap; return 0; } /*----------------------------------------------------------------------*/ /* Get the input capacitance of the named pin of the specified cell. */ /* Return cap value in "retcap". */ /* Return 0 on success, 1 if the requested pin was not an input, and */ /* -1 if the requested pin was not found. */ /*----------------------------------------------------------------------*/ int get_pincap(Cell *curcell, char *pinname, double *retcap) { Pin *curpin; for (curpin = curcell->pins; curpin; curpin = curpin->next) { if (!strcmp(curpin->name, pinname)) { if (curpin->type == PIN_INPUT) { *retcap = curpin->cap; return 0; } else { *retcap = 0.0; return 1; /* pin is an output */ } } } *retcap = 0.0; return -1; /* Error: no such pin */ } /*--------------------------------------------------------------------*/ int get_pintype(Cell *curcell, char *pinname) { Pin *curpin; for (curpin = curcell->pins; curpin; curpin = curpin->next) { if (!strcmp(curpin->name, pinname)) { return curpin->type; } } return PIN_UNKNOWN; } /*--------------------------------------------------------------------*/ qflow-1.1.23/src/blif2BSpice.c0000644000175000001440000003664612526236535014505 0ustar timusers//-------------------------------------------------------------- // blif2BSpice // // Revision 0, 2006-11-11: First release by R. Timothy Edwards. // Revision 1, 2009-07-13: Minor cleanups by Philipp Klaus Krause. // Revision 2, 2013-05-10: Modified to take a library of subcell // definitions to use for determining port order. // Revision 3, 2013-10-09: Changed from BDnet2BSpice to // blif2BSpice // //-------------------------------------------------------------- #include #include #include #include #include #include #define EXIT_SUCCESS 0 #define EXIT_FAILURE 1 #define EXIT_HELP 2 #define TRUE 1 #define FALSE 0 #define NMOS 1 #define PMOS 0 #define LengthOfLine 16384 #define LengthOfNodeName 512 /* getopt stuff */ extern int optind, getopt(); extern char *optarg; void ReadNetlistAndConvert(FILE *, FILE *, FILE *, char *, char *, char *); void CleanupString(char text[]); float getnumber(char *strpntbegin); int loc_getline(char s[], int lim, FILE *fp); void helpmessage(); //-------------------------------------------------------- // Structures for maintaining port order for subcircuits // read from a SPICE library //-------------------------------------------------------- typedef struct _portrec *portrecp; typedef struct _portrec { portrecp next; char *name; char signal[LengthOfNodeName]; // Instance can write signal name here } portrec; typedef struct _subcircuit *subcircuitp; typedef struct _subcircuit { subcircuitp next; char *name; portrecp ports; int gatecount; } subcircuit; //-------------------------------------------------------- int main (int argc, char *argv[]) { FILE *NET1 = NULL; FILE *NET2 = NULL; FILE *outfile; int i; char *Net1name = NULL; char *Net2name = NULL; char *vddnet = NULL; char *gndnet = NULL; char *subnet = NULL; // Use implicit power if power and ground nodes are global in SPICE // Otherwise, use "-p". while ((i = getopt( argc, argv, "hHl:p:g:s:" )) != EOF) { switch (i) { case 'p': vddnet = strdup(optarg); break; case 'g': gndnet = strdup(optarg); break; case 's': subnet = strdup(optarg); break; case 'l': Net2name = strdup(optarg); break; case 'h': case 'H': helpmessage(); break; default: fprintf(stderr, "\nbad switch %d\n", i); helpmessage(); break; } } if (optind < argc) { Net1name = strdup(argv[optind]); optind++; } else { fprintf(stderr, "Couldn't find a filename as input\n"); exit(EXIT_FAILURE); } optind++; if (Net1name) NET1 = fopen(Net1name,"r"); if (NET1 == NULL) { fprintf(stderr, "Couldn't open %s for reading\n", Net1name); exit(EXIT_FAILURE); } if (Net2name) { NET2 = fopen(Net2name, "r"); if (NET2 == NULL) fprintf(stderr, "Couldn't open %s for reading\n", Net2name); } outfile = stdout; ReadNetlistAndConvert(NET1, NET2, outfile, vddnet, gndnet, subnet); return 0; } /*--------------------------------------------------------------*/ /*C *Alloc - Allocates memory for linked list elements */ /* */ /* ARGS: RETURNS: 1 to OS SIDE EFFECTS: \*--------------------------------------------------------------*/ void ReadNetlistAndConvert(FILE *netfile, FILE *libfile, FILE *outfile, char *vddnet, char *gndnet, char *subnet) { int i, NumberOfInputs, NumberOfOutputs; char *lptr; char line[LengthOfLine]; char InputName[LengthOfNodeName]; char OutputName[LengthOfNodeName]; char MainSubcktName[LengthOfNodeName]; char InstanceName[LengthOfNodeName]; char InstancePortName[LengthOfNodeName]; char InstancePortWire[LengthOfNodeName]; subcircuitp subcktlib = NULL, tsub; portrecp tport; int uniquenode = 1000; // Read a SPICE library of subcircuits if (libfile != NULL) { char *sp, *sp2; subcircuitp newsubckt; portrecp newport, lastport; /* If we specify a library, then we need to make sure that */ /* "vddnet" and "gndnet" are non-NULL, so that they will be */ /* filled in correctly. If not specified on the command */ /* line, they default to "vdd" and "vss". */ if (vddnet == NULL) vddnet = strdup("vdd"); if (gndnet == NULL) gndnet = strdup("gnd"); /* Read SPICE library of subcircuits, if one is specified. */ /* Retain the name and order of ports passed to each */ /* subcircuit. */ while (loc_getline(line, sizeof(line), libfile) > 0) { if (!strncasecmp(line, ".subckt", 7)) { /* Read cellname */ sp = line + 7; while (isspace(*sp) && (*sp != '\n')) sp++; sp2 = sp; while (!isspace(*sp2) && (*sp2 != '\n')) sp2++; *sp2 = '\0'; newsubckt = (subcircuitp)malloc(sizeof(subcircuit)); newsubckt->name = strdup(sp); newsubckt->next = subcktlib; subcktlib = newsubckt; newsubckt->ports = NULL; newsubckt->gatecount = 0; sp = sp2 + 1; while (isspace(*sp) && (*sp != '\n') && (*sp != '\0')) sp++; while (1) { /* Move string pointer to next port name */ if (*sp == '\n' || *sp == '\0') { loc_getline(line, sizeof(line), libfile); if (*line == '+') { sp = line + 1; while (isspace(*sp) && (*sp != '\n')) sp++; } else break; } /* Terminate port name and advance pointer */ sp2 = sp; while (!isspace(*sp2) && (*sp2 != '\n')) sp2++; *sp2 = '\0'; /* Get next port */ newport = (portrecp)malloc(sizeof(portrec)); newport->next = NULL; newport->name = strdup(sp); /* This is a bit of a hack. It's difficult to */ /* tell what the standard cell set is going to */ /* use for power bus names. It's okay to fill in */ /* signals with similar names here, as they will */ /* (should!) match up to port names in the BLIF */ /* file, and will be overwritten later. Well */ /* connections are not considered here, but maybe */ /* they should be? */ if (!strncasecmp(sp, "vdd", 3)) strcpy(newport->signal, vddnet); else if (!strncasecmp(sp, "vss", 3)) strcpy(newport->signal, gndnet); else if (!strncasecmp(sp, "gnd", 3)) strcpy(newport->signal, gndnet); else if (!strncasecmp(sp, "sub", 3)) { if (subnet != NULL) strcpy(newport->signal, subnet); } else newport->signal[0] = '\0'; if (newsubckt->ports == NULL) newsubckt->ports = newport; else lastport->next = newport; lastport = newport; sp = sp2 + 1; } /* Read input to end of subcircuit */ if (strncasecmp(line, ".ends", 4)) { while (loc_getline(line, sizeof(line), libfile) > 0) if (!strncasecmp(line, ".ends", 4)) break; } } } } /* Read in line by line */ while (loc_getline(line, sizeof(line), netfile) > 0 ) { if (strstr(line, ".model") != NULL ) { if (sscanf(line, ".model %s", MainSubcktName) == 1) { CleanupString(MainSubcktName); fprintf(outfile, "*SPICE netlist created from BLIF module " "%s by blif2BSpice\n", MainSubcktName); fprintf(outfile, ""); if (subcktlib != NULL) { /* Write out the subcircuit library file verbatim */ rewind(libfile); while (loc_getline(line, sizeof(line), libfile) > 0) fputs(line, outfile); fclose(libfile); fprintf(outfile, ""); } fprintf(outfile, ".subckt %s ", MainSubcktName); if (vddnet == NULL) fprintf(outfile, "vdd "); else fprintf(outfile, "%s ", vddnet); if (gndnet == NULL) fprintf(outfile, "vss "); else fprintf(outfile, "%s ", gndnet); if ((subnet != NULL) && strcasecmp(subnet, gndnet)) fprintf(outfile, "%s ", subnet); } else if (strstr(line, ".ends") != NULL) { fprintf(outfile, ".ends %s\n ", MainSubcktName); } } if (strstr(line, ".inputs") != NULL) { NumberOfInputs = 0; lptr = line; while (!isspace(*lptr)) lptr++; while (isspace(*lptr)) lptr++; while (1) { if (strstr(lptr, ".outputs")) break; while (sscanf(lptr, "%s", InputName) == 1) { CleanupString(InputName); fprintf(outfile, "%s ", InputName); NumberOfInputs++; while (!isspace(*lptr)) lptr++; while (isspace(*lptr)) lptr++; if (*lptr == '\\') break; } if (loc_getline(line, sizeof(line), netfile) <= 1 ) break; else lptr = line; } } if (strstr(line, ".outputs") != NULL) { NumberOfOutputs = 0; lptr = line; while (!isspace(*lptr)) lptr++; while (isspace(*lptr)) lptr++; while (1) { if (strstr(lptr, ".gate") || strstr(lptr, ".subckt")) break; while (sscanf(lptr, "%s", OutputName) == 1) { CleanupString(OutputName); fprintf(outfile,"%s ", OutputName); NumberOfOutputs++; while (!isspace(*lptr)) lptr++; while (isspace(*lptr)) lptr++; if (*lptr == '\\') break; } if (loc_getline(line, sizeof(line), netfile) <= 1) break; else lptr = line; } fprintf(outfile, "\n"); } if (strstr(line, ".gate") != NULL || strstr(line, ".subckt") != NULL) { lptr = line; while (isspace(*lptr)) lptr++; if (sscanf(lptr, ".%*s %s", InstanceName) == 1) { CleanupString(InstanceName); /* Search library records for subcircuit */ for (tsub = subcktlib; tsub; tsub = tsub->next) { if (!strcasecmp(InstanceName, tsub->name)) break; } if (tsub == NULL) { // Create an entry so we can track instances tsub = (subcircuitp)malloc(sizeof(subcircuit)); tsub->next = subcktlib; subcktlib = tsub; tsub->name = strdup(InstanceName); tsub->gatecount = 1; tsub->ports = NULL; } else tsub->gatecount++; fprintf(outfile, "X%s_%d ", tsub->name, tsub->gatecount); if (tsub == NULL) { if (vddnet == NULL) fprintf(outfile,"vdd "); if (gndnet == NULL) fprintf(outfile,"vss "); } while (!isspace(*lptr)) lptr++; while (isspace(*lptr)) lptr++; while (!isspace(*lptr)) lptr++; while (isspace(*lptr)) lptr++; while (1) { char *eptr; eptr = strchr(lptr, '='); if (eptr == NULL) break; *eptr = '\0'; if (sscanf(lptr, "%s", InstancePortName) != 1) break; lptr = eptr + 1; if (sscanf(lptr, "%s", InstancePortWire) != 1) break; CleanupString(InstancePortWire); if (tsub == NULL) fprintf(outfile,"%s ", InstancePortWire); else { // Find port name in list CleanupString(InstancePortName); for (tport = tsub->ports; tport; tport = tport->next) { if (!strcmp(tport->name, InstancePortName)) { sprintf(tport->signal, InstancePortWire); break; } } if (tport == NULL) /* This will likely screw everything up. . . */ fprintf(outfile,"%s ", InstancePortWire); } while (!isspace(*lptr)) lptr++; while (isspace(*lptr)) lptr++; if (*lptr == '\\') { if (loc_getline(line, sizeof(line), netfile) <= 1) break; lptr = line; } else if (*lptr == '\n') break; } } /* Done with I/O section, add instance name to subckt line */ if (tsub != NULL) { /* Write out all ports in proper order */ for (tport = tsub->ports; tport; tport = tport->next) { if (tport->signal[0] == '\0') fprintf(outfile,"%d ", uniquenode++); else fprintf(outfile,"%s ", tport->signal); } } fprintf(outfile,"%s\n",InstanceName); } } } /*--------------------------------------------------------------*/ /*--------------------------------------------------------------*/ void CleanupString(char text[LengthOfNodeName]) { int i; char *CitationPnt; CitationPnt=strchr(text,'"'); if( CitationPnt != NULL) { i=0; while( CitationPnt[i+1] != '"' ) { CitationPnt[i]=CitationPnt[i+1]; i++; } CitationPnt[i]='\0'; CitationPnt=strchr(text,'['); if(CitationPnt != NULL) { i=0; while( CitationPnt[i+1] != ']' ) { CitationPnt[i]=CitationPnt[i+1]; i++; } CitationPnt[i]='\0'; } } } /*--------------------------------------------------------------*/ /*C getnumber - gets number pointed by strpntbegin */ /* */ /* ARGS: strpntbegin - number expected after '=' */ /* RETURNS: 1 to OS SIDE EFFECTS: \*--------------------------------------------------------------*/ float getnumber(char *strpntbegin) { int i; char *strpnt,magn1,magn2; float number; strpnt=strpntbegin; strpnt=strchr(strpntbegin,'='); if(strpnt == NULL) { fprintf(stderr,"Error: getnumber: Didn't find '=' in string " "%s\n",strpntbegin); return DBL_MAX; } strpnt=strpnt+1; if(sscanf(strpnt,"%f%c%c",&number,&magn1, &magn2)!=3) { if(sscanf(strpnt,"%f%c",&number,&magn1)!=2) { fprintf(stderr,"Error: getnumber : Couldn't read number in " "%s %s\n",strpntbegin,strpnt); return DBL_MAX; } } switch( magn1 ) { case 'f': number *= 1e-15; break; case 'p': number *= 1e-12; break; case 'n': number *= 1e-9; break; case 'u': number *= 1e-6; break; case 'm': if(magn2='e') number *= 1e6; else number *= 1e-3; break; case 'k': number *= 1e3; break; case 'g': number *= 1e9; break; case ' ': default: return number; } return number; } /*--------------------------------------------------------------*/ /*C loc_getline: read a line, return length */ /* */ /* ARGS: RETURNS: 1 to OS SIDE EFFECTS: \*--------------------------------------------------------------*/ int loc_getline( char s[], int lim, FILE *fp) { int c, i; i=0; while(--lim > 0 && (c=getc(fp)) != EOF && c != '\n') s[i++] = c; if (c == '\n'); s[i++] = c; s[i] = '\0'; if ( c == EOF ) i=0; return i; } /*--------------------------------------------------------------*/ /*C helpmessage - tell user how to use the program */ /* */ /* ARGS: RETURNS: 1 to OS SIDE EFFECTS: \*--------------------------------------------------------------*/ void helpmessage() { fprintf(stderr,"blif2BSpice [-options] netlist \n"); fprintf(stderr,"\n"); fprintf(stderr,"blif2BSpice converts a netlist in blif format \n"); fprintf(stderr,"to BSpice subcircuit format. Output on stdout\n"); fprintf(stderr,"\n"); fprintf(stderr,"option, -h this message\n"); fprintf(stderr,"option, -p means: don't add power nodes to instances\n"); fprintf(stderr," only nodes present in the .gate statement used\n"); exit( EXIT_HELP ); } /* helpmessage() */ qflow-1.1.23/tech/0000755000175000001440000000000012535603240012361 5ustar timusersqflow-1.1.23/tech/osu050/0000755000175000001440000000000012535603557013427 5ustar timusersqflow-1.1.23/tech/osu050/Makefile.in0000644000175000001440000000167212526236535015500 0ustar timusers# # qflow project included technology osu050 files # # Main compiler arguments CFLAGS = @CFLAGS@ DEFS = @DEFS@ LIBS = @LIBS@ LDFLAGS = @LDFLAGS@ INSTALL = @INSTALL@ QFLOW_LIB_DIR = @QFLOW_LIB_DIR@ TECH_FILES = osu050.par osu050_stdcells.lef osu050.sh TECH_FILES += osu050_stdcells.sp osu050.magicrc osu050.prm TECH_FILES += SCN3ME_SUBM.30.tech osu05_stdcells.lib TECH_FILES += osu05_stdcells.v TECHINSTALL = ${QFLOW_LIB_DIR}/tech # Substitute the target qflow tech directory name in .magicrc so that magic # can find the OSU050 techfile all: osu050.magicrc.in $(RM) -f osu050.magicrc cat osu050.magicrc.in | sed -e \ '/QFLOW_LIB_DIR/s#QFLOW_LIB_DIR#$(QFLOW_LIB_DIR)#' \ > osu050.magicrc install: ${TECH_FILES} @echo "Installing osu050 tech files" $(INSTALL) -d $(DESTDIR)$(TECHINSTALL)/osu050 for target in $(TECH_FILES); do \ $(INSTALL) $$target $(DESTDIR)$(TECHINSTALL)/osu050 ;\ done clean: $(RM) -f osu050.magicrc uninstall: qflow-1.1.23/tech/osu050/osu050.prm0000644000175000001440000000156412526236535015206 0ustar timusers; ; configuration file for osu050 (0.50um process) ; Note that these values are totally bogus! ; lambda 0.01 ; length scaling, microns (1 lambda = 1 centimicron) capga .0115 ; gate capacitance, pF/micron^2 capda 0.0012 capdp 0.0013 cappda 0.00260 cappdp 0.00090 lowthresh 0.5 ; logic low threshold as a normalized voltage highthresh 0.5 ; logic high threshold as a normalized voltage cntpullup 0 ; irrelevant, cmos technology; no depletion transistors diffperim 0 ; don't include diffusion perimeters for sidewall cap. subparea 0 ; poly over transistor won't count as part pf bulk-poly cap. diffext 0 ; diffusion extension for each transistor resistance n-channel static 3 0.6 3858.26 resistance p-channel static 8.7 0.6 2874.04 resistance n-channel dynamic-high 3 0.6 7794.00 resistance p-channel dynamic-low 8.7 0.6 6568.70 qflow-1.1.23/tech/osu050/osu050.magicrc.in0000755000175000001440000000047712526236535016427 0ustar timusers#----------------------------------------------------- # .magicrc startup file for OSU050 project under qflow #----------------------------------------------------- path sys +QFLOW_LIB_DIR/tech/osu050 tech load SCN3ME_SUBM.30 -noprompt scalegrid 1 4 set GND gnd set VDD vdd drc euclidean on drc off addpath digital qflow-1.1.23/tech/osu050/osu050.par0000755000175000001440000000301512526236535015166 0ustar timusers# osu050.par --- Parameter file for GrayWolf # NOTE: all distance units are in centimicrons unless otherwise stated RULES # Values are resistance in ohms/sq, and capacitance in fF/um^2 layer metal1 0.09 0.032 horizontal layer metal2 0.09 0.016 vertical layer metal3 0.05 0.010 horizontal via via12 metal1 metal2 via via23 metal2 metal3 width metal1 90 width metal2 90 width metal3 150 width via12 150 width via23 150 # Note: width + spacing = track pitch, as far as GrayWolf is # concerned. So adjust spacing to make the correct pitch. # A track pitch < actual track pitch may cause pins to overlap! # Track pitches for the preferred routing direction are: # metal1: 300, metal2: 240, metal3: 300 spacing metal1 metal1 210 spacing metal2 metal2 150 spacing metal3 metal3 150 # Stacked vias allowed spacing via12 via23 0 overhang via12 metal1 8 overhang via12 metal2 6 overhang via23 metal2 8 overhang via23 metal3 6 ENDRULES *vertical_wire_weight : 1.0 *vertical_path_weight : 1.0 *padspacing : variable *rowSep : 0.0 0 *track.pitch : 0.0 *graphics.wait : off *last_chance.wait : off *random.seed : 12345 TWMC*chip.aspect.ratio : 0.75 TWSC*feedThruWidth : 240 layer 1 TWSC*do.global.route : on TWSC*ignore_feeds : true TWSC*call_row_evener : true TWSC*even_rows_maximally : true # TWSC*no.graphics : on GENR*row_to_tile_spacing: 1 # GENR*numrows : 6 GENR*flip_alternate_rows : 1 qflow-1.1.23/tech/osu050/Makefile0000664000175000001440000000247212533671314015070 0ustar timusers# # qflow project included technology osu050 files # # Main compiler arguments CFLAGS = -g -O2 DEFS = -DPACKAGE_NAME=\"\" -DPACKAGE_TARNAME=\"\" -DPACKAGE_VERSION=\"\" -DPACKAGE_STRING=\"\" -DPACKAGE_BUGREPORT=\"\" -DPACKAGE_URL=\"\" -DSTDC_HEADERS=1 -DHAVE_SETENV=1 -DHAVE_PUTENV=1 -DTCLSH_PATH=\"/bin/tclsh\" -DQFLOW_MAGIC_PATH=\"/usr/local/bin/magic\" -DQFLOW_QROUTER_PATH=\"/usr/local/bin/qrouter\" -DQFLOW_GRAYWOLF_PATH=\"/usr/local/bin/graywolf\" -DQFLOW_YOSYS_PATH=\"/usr/local/bin/yosys\" LIBS = LDFLAGS = INSTALL = /bin/install -c QFLOW_LIB_DIR = /usr/local/share/qflow TECH_FILES = osu050.par osu050_stdcells.lef osu050.sh TECH_FILES += osu050_stdcells.sp osu050.magicrc osu050.prm TECH_FILES += SCN3ME_SUBM.30.tech osu05_stdcells.lib TECH_FILES += osu05_stdcells.v TECHINSTALL = ${QFLOW_LIB_DIR}/tech # Substitute the target qflow tech directory name in .magicrc so that magic # can find the OSU050 techfile all: osu050.magicrc.in $(RM) -f osu050.magicrc cat osu050.magicrc.in | sed -e \ '/QFLOW_LIB_DIR/s#QFLOW_LIB_DIR#$(QFLOW_LIB_DIR)#' \ > osu050.magicrc install: ${TECH_FILES} @echo "Installing osu050 tech files" $(INSTALL) -d $(DESTDIR)$(TECHINSTALL)/osu050 for target in $(TECH_FILES); do \ $(INSTALL) $$target $(DESTDIR)$(TECHINSTALL)/osu050 ;\ done clean: $(RM) -f osu050.magicrc uninstall: qflow-1.1.23/tech/osu050/osu050_stdcells.lef0000664000175000001440000024054512535603557017063 0ustar timusers# LEF file generated by Abstract Generator version 5.5.10 on Jul 31 16:51:52 2004 # # Contains LEF for all bins. # Options: [x] Antenna # [x] Geometry # [x] Technology VERSION 5.4 ; NAMESCASESENSITIVE ON ; BUSBITCHARS "[]" ; DIVIDERCHAR "/" ; UNITS DATABASE MICRONS 1000 ; END UNITS USEMINSPACING OBS ON ; USEMINSPACING PIN OFF ; CLEARANCEMEASURE EUCLIDEAN ; MANUFACTURINGGRID 0.15 ; LAYER nwell TYPE MASTERSLICE ; END nwell LAYER nactive TYPE MASTERSLICE ; END nactive LAYER pactive TYPE MASTERSLICE ; END pactive LAYER poly TYPE MASTERSLICE ; END poly LAYER cc TYPE CUT ; SPACING 0.9 ; END cc LAYER metal1 TYPE ROUTING ; DIRECTION HORIZONTAL ; PITCH 3 ; OFFSET 1.5 ; WIDTH 0.9 ; SPACING 0.9 ; RESISTANCE RPERSQ 0.09 ; CAPACITANCE CPERSQDIST 3.2e-05 ; END metal1 LAYER via TYPE CUT ; SPACING 0.9 ; END via LAYER metal2 TYPE ROUTING ; DIRECTION VERTICAL ; PITCH 2.4 ; OFFSET 1.2 ; WIDTH 0.9 ; SPACING 0.9 ; RESISTANCE RPERSQ 0.09 ; CAPACITANCE CPERSQDIST 1.6e-05 ; END metal2 LAYER via2 TYPE CUT ; SPACING 0.9 ; END via2 LAYER metal3 TYPE ROUTING ; DIRECTION HORIZONTAL ; PITCH 3 ; OFFSET 1.5 ; WIDTH 1.5 ; SPACING 0.9 ; RESISTANCE RPERSQ 0.05 ; CAPACITANCE CPERSQDIST 1e-05 ; END metal3 SPACING SAMENET cc via 0.150 ; SAMENET via via2 0.150 ; END SPACING VIA M2_M1 DEFAULT LAYER metal1 ; RECT -0.600 -0.600 0.600 0.600 ; LAYER via ; RECT -0.300 -0.300 0.300 0.300 ; LAYER metal2 ; RECT -0.600 -0.600 0.600 0.600 ; END M2_M1 VIA M3_M2 DEFAULT LAYER metal2 ; RECT -0.600 -0.600 0.600 0.600 ; LAYER via2 ; RECT -0.300 -0.300 0.300 0.300 ; LAYER metal3 ; RECT -0.900 -0.900 0.900 0.900 ; END M3_M2 VIARULE viagen21 GENERATE LAYER metal1 ; DIRECTION HORIZONTAL ; WIDTH 1.2 TO 120 ; OVERHANG 0.3 ; METALOVERHANG 0 ; LAYER metal2 ; DIRECTION VERTICAL ; WIDTH 1.2 TO 120 ; OVERHANG 0.3 ; METALOVERHANG 0 ; LAYER via ; RECT -0.3 -0.3 0.3 0.3 ; SPACING 1.5 BY 1.5 ; END viagen21 VIARULE viagen32 GENERATE LAYER metal3 ; DIRECTION HORIZONTAL ; WIDTH 1.8 TO 180 ; OVERHANG 0.6 ; METALOVERHANG 0 ; LAYER metal2 ; DIRECTION VERTICAL ; WIDTH 1.2 TO 120 ; OVERHANG 0.6 ; METALOVERHANG 0 ; LAYER via2 ; RECT -0.3 -0.3 0.3 0.3 ; SPACING 2.1 BY 2.1 ; END viagen32 VIARULE TURN1 GENERATE LAYER metal1 ; DIRECTION HORIZONTAL ; LAYER metal1 ; DIRECTION VERTICAL ; END TURN1 VIARULE TURN2 GENERATE LAYER metal2 ; DIRECTION HORIZONTAL ; LAYER metal2 ; DIRECTION VERTICAL ; END TURN2 VIARULE TURN3 GENERATE LAYER metal3 ; DIRECTION HORIZONTAL ; LAYER metal3 ; DIRECTION VERTICAL ; END TURN3 SITE corner CLASS PAD ; SYMMETRY R90 Y ; SIZE 300.000 BY 300.000 ; END corner SITE IO CLASS PAD ; SYMMETRY Y ; SIZE 90.000 BY 300.000 ; END IO SITE core CLASS CORE ; SYMMETRY Y ; SIZE 2.400 BY 30.000 ; END core MACRO FILL CLASS CORE ; FOREIGN FILL 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 2.400 BY 30.000 ; SYMMETRY X Y ; SITE core ; PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.600 -0.900 3.000 0.900 ; END END gnd PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.600 29.100 3.000 30.900 ; END END vdd END FILL MACRO AND2X1 CLASS CORE ; FOREIGN AND2X1 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 9.600 BY 30.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.600 9.900 1.800 11.100 ; END END A PIN B DIRECTION INPUT ; PORT LAYER metal1 ; RECT 3.000 15.900 4.200 17.100 ; END END B PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.600 -0.900 10.200 0.900 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 7.800 18.900 9.000 20.100 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.600 29.100 10.200 30.900 ; END END vdd OBS LAYER metal1 ; RECT 0.600 22.200 1.800 28.200 ; RECT 0.600 12.000 1.800 12.300 ; RECT 3.900 14.700 5.100 15.000 ; RECT 4.500 1.800 5.700 7.800 ; RECT 5.400 22.200 6.600 28.200 ; RECT 0.600 1.800 1.800 7.800 ; RECT 0.900 7.800 3.600 8.700 ; RECT 2.700 7.800 3.600 9.900 ; RECT 6.000 8.700 7.200 9.900 ; RECT 2.700 9.000 7.200 9.900 ; RECT 6.000 8.700 6.900 21.300 ; RECT 3.300 20.400 6.900 21.300 ; RECT 3.300 20.400 4.200 28.200 ; RECT 3.000 22.200 4.200 28.200 ; RECT 8.100 21.000 9.000 28.200 ; RECT 7.800 22.200 9.000 28.200 ; RECT 6.900 1.800 8.100 5.700 ; RECT 8.100 4.800 9.000 18.000 ; END END AND2X1 MACRO AND2X2 CLASS CORE ; FOREIGN AND2X2 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 9.600 BY 30.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.600 9.900 1.800 11.100 ; END END A PIN B DIRECTION INPUT ; PORT LAYER metal1 ; RECT 3.000 12.900 4.200 14.100 ; END END B PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.600 -0.900 10.200 0.900 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 7.800 12.900 9.000 14.100 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.600 29.100 10.200 30.900 ; END END vdd OBS LAYER metal1 ; RECT 0.600 22.200 1.800 28.200 ; RECT 0.600 12.000 1.800 12.300 ; RECT 3.600 10.500 4.800 11.700 ; RECT 3.300 10.800 4.200 12.000 ; RECT 4.500 1.800 5.700 7.500 ; RECT 5.400 16.800 6.600 28.200 ; RECT 0.600 1.800 1.800 7.800 ; RECT 0.900 1.800 1.800 9.000 ; RECT 0.900 8.100 3.600 9.000 ; RECT 2.700 8.700 7.200 9.600 ; RECT 6.000 8.700 7.200 9.900 ; RECT 6.000 8.700 6.900 15.900 ; RECT 3.300 15.000 6.900 15.900 ; RECT 3.300 15.000 4.200 28.200 ; RECT 3.000 22.200 4.200 28.200 ; RECT 8.100 15.000 9.000 28.200 ; RECT 7.800 16.200 9.000 28.200 ; RECT 6.900 1.800 8.100 7.800 ; RECT 8.100 6.300 9.000 12.000 ; END END AND2X2 MACRO AOI21X1 CLASS CORE ; FOREIGN AOI21X1 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 9.600 BY 30.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.600 12.900 1.800 14.100 ; END END A PIN B DIRECTION INPUT ; PORT LAYER metal1 ; RECT 3.000 9.900 4.200 11.100 ; END END B PIN C DIRECTION INPUT ; PORT LAYER metal1 ; RECT 7.800 6.900 9.000 8.100 ; END END C PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.600 -0.900 10.200 0.900 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 7.800 12.900 9.000 14.100 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.600 29.100 10.200 30.900 ; END END vdd OBS LAYER metal1 ; RECT 1.500 1.800 2.700 7.800 ; RECT 2.700 13.200 3.000 14.700 ; RECT 3.000 18.000 4.200 28.200 ; RECT 3.000 12.000 4.200 12.300 ; RECT 0.600 16.200 6.600 17.100 ; RECT 0.600 16.200 1.800 28.200 ; RECT 5.400 16.200 6.600 28.200 ; RECT 5.400 1.800 6.600 7.800 ; RECT 5.400 1.800 6.300 14.100 ; RECT 5.400 13.200 6.900 14.100 ; RECT 7.500 5.700 8.700 6.000 ; RECT 7.800 15.000 8.700 28.200 ; RECT 7.800 16.200 9.000 28.200 ; RECT 7.800 1.800 9.000 4.800 ; END END AOI21X1 MACRO AOI22X1 CLASS CORE ; FOREIGN AOI22X1 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 12.000 BY 30.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.600 12.900 1.800 14.100 ; END END A PIN B DIRECTION INPUT ; PORT LAYER metal1 ; RECT 3.000 9.900 4.200 11.100 ; END END B PIN C DIRECTION INPUT ; PORT LAYER metal1 ; RECT 10.200 12.900 11.400 14.100 ; END END C PIN D DIRECTION INPUT ; PORT LAYER metal1 ; RECT 7.800 9.900 9.000 11.100 ; END END D PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.600 -0.900 12.600 0.900 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 5.400 12.900 6.600 14.100 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.600 29.100 12.600 30.900 ; END END vdd OBS LAYER metal1 ; RECT 1.200 1.800 2.400 7.800 ; RECT 2.700 13.200 3.000 14.700 ; RECT 3.000 18.000 4.200 28.200 ; RECT 3.000 12.000 4.200 12.300 ; RECT 5.100 1.800 7.500 7.800 ; RECT 5.700 1.800 6.600 12.000 ; RECT 7.500 12.000 8.700 12.900 ; RECT 7.500 14.400 8.700 15.300 ; RECT 5.700 15.000 8.700 15.300 ; RECT 7.800 14.400 8.700 26.400 ; RECT 7.800 16.200 9.000 26.400 ; RECT 0.600 16.200 6.600 17.100 ; RECT 5.400 16.200 6.600 28.200 ; RECT 0.600 16.200 1.800 28.200 ; RECT 10.200 16.200 11.400 28.200 ; RECT 5.400 27.300 11.400 28.200 ; RECT 10.200 15.000 11.400 15.300 ; RECT 10.200 1.800 11.400 7.800 ; END END AOI22X1 MACRO BUFX2 CLASS CORE ; FOREIGN BUFX2 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 7.200 BY 30.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.600 12.900 1.800 14.100 ; END END A PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.600 -0.900 7.800 0.900 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 5.400 9.900 6.600 11.100 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.600 29.100 7.800 30.900 ; END END vdd OBS LAYER metal1 ; RECT 0.600 11.700 1.800 12.000 ; RECT 3.000 18.000 4.200 28.200 ; RECT 3.000 1.800 4.200 7.800 ; RECT 0.600 1.800 1.800 9.600 ; RECT 0.600 8.700 3.900 9.600 ; RECT 3.000 14.100 4.800 15.300 ; RECT 3.000 8.700 3.900 17.100 ; RECT 0.600 16.200 3.900 17.100 ; RECT 0.600 16.200 1.800 28.200 ; RECT 5.400 12.000 6.600 12.900 ; RECT 5.700 12.000 6.600 28.200 ; RECT 5.400 16.200 6.600 28.200 ; RECT 5.400 1.800 6.600 9.000 ; END END BUFX2 MACRO BUFX4 CLASS CORE ; FOREIGN BUFX4 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 9.600 BY 30.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.600 12.900 1.800 14.100 ; END END A PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.600 -0.900 10.200 0.900 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 5.400 9.900 6.600 11.100 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.600 29.100 10.200 30.900 ; END END vdd OBS LAYER metal1 ; RECT 0.900 11.700 2.100 12.000 ; RECT 3.000 18.000 4.200 28.200 ; RECT 3.000 1.800 4.200 7.800 ; RECT 0.600 1.800 1.800 9.600 ; RECT 0.600 8.700 4.500 9.600 ; RECT 3.600 12.000 5.100 13.200 ; RECT 3.600 8.700 4.500 17.100 ; RECT 0.600 16.200 4.500 17.100 ; RECT 0.600 16.200 1.800 28.200 ; RECT 6.000 12.000 6.900 17.700 ; RECT 5.400 16.200 6.600 28.200 ; RECT 5.400 1.800 6.600 7.800 ; RECT 6.000 6.900 6.900 9.000 ; RECT 7.800 16.200 9.000 28.200 ; RECT 7.800 1.800 9.000 7.800 ; END END BUFX4 MACRO DFFNEGX1 CLASS CORE ; FOREIGN DFFNEGX1 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 28.800 BY 30.000 ; SYMMETRY X Y ; SITE core ; PIN Q DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 27.000 12.900 28.200 14.100 ; END END Q PIN CLK DIRECTION INPUT ; PORT LAYER metal1 ; RECT 3.000 9.900 4.200 11.100 ; END END CLK PIN D DIRECTION INPUT ; PORT LAYER metal1 ; RECT 10.200 12.900 11.400 14.100 ; END END D PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.600 -0.900 29.400 0.900 ; END END gnd PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.600 29.100 29.400 30.900 ; END END vdd OBS LAYER metal2 ; RECT 0.600 7.800 1.800 16.200 ; RECT 5.400 4.800 6.600 15.000 ; RECT 5.400 4.800 6.300 22.200 ; RECT 5.400 16.200 6.600 22.200 ; RECT 7.800 10.200 9.000 20.100 ; RECT 19.800 4.800 21.000 17.100 ; RECT 19.800 4.800 20.700 22.200 ; RECT 19.800 18.300 21.000 22.200 ; LAYER metal1 ; RECT 0.600 1.800 1.800 9.000 ; RECT 1.800 9.900 2.100 11.100 ; RECT 3.000 16.500 4.200 28.200 ; RECT 3.000 1.800 4.200 7.800 ; RECT 5.400 21.000 6.600 23.100 ; RECT 5.400 22.200 8.400 23.100 ; RECT 7.200 22.200 8.400 28.200 ; RECT 7.200 1.800 8.400 4.800 ; RECT 5.400 3.900 8.400 4.800 ; RECT 5.400 3.900 6.600 6.000 ; RECT 7.800 18.900 9.000 20.100 ; RECT 8.100 20.100 9.300 21.300 ; RECT 4.200 12.600 5.400 13.800 ; RECT 4.200 12.900 9.300 13.800 ; RECT 11.400 22.200 12.600 28.200 ; RECT 11.100 1.800 12.600 4.800 ; RECT 5.400 17.100 13.500 18.000 ; RECT 5.400 17.100 6.600 18.300 ; RECT 12.300 17.100 13.500 18.300 ; RECT 13.800 1.800 15.000 4.800 ; RECT 13.800 1.800 14.700 6.600 ; RECT 10.500 5.700 14.700 6.600 ; RECT 10.500 5.700 11.700 6.900 ; RECT 10.500 20.100 11.700 21.300 ; RECT 14.700 20.100 15.900 21.300 ; RECT 10.500 20.400 15.900 21.300 ; RECT 13.800 20.400 14.700 28.200 ; RECT 13.800 22.200 15.000 28.200 ; RECT 16.200 22.200 17.400 28.200 ; RECT 16.200 1.800 17.400 4.800 ; RECT 6.300 6.900 7.500 8.100 ; RECT 6.000 8.100 7.200 11.100 ; RECT 18.000 9.900 19.200 11.100 ; RECT 5.100 10.200 19.200 11.100 ; RECT 7.800 10.200 9.000 11.400 ; RECT 19.800 21.000 21.000 22.200 ; RECT 20.100 22.200 21.900 28.200 ; RECT 0.600 14.700 7.500 15.600 ; RECT 6.300 15.300 17.100 16.200 ; RECT 16.200 15.300 17.100 18.300 ; RECT 16.200 17.100 21.900 18.000 ; RECT 16.200 17.100 17.700 18.300 ; RECT 20.700 17.100 21.900 18.300 ; RECT 0.600 14.700 1.800 28.200 ; RECT 20.100 1.800 21.900 4.800 ; RECT 19.800 3.900 21.000 6.000 ; RECT 19.800 12.000 21.000 13.200 ; RECT 19.800 12.300 25.500 13.200 ; RECT 24.300 12.300 25.500 13.500 ; RECT 24.600 16.200 25.800 28.200 ; RECT 24.600 1.800 25.800 7.500 ; RECT 21.900 14.100 23.100 15.300 ; RECT 21.900 14.400 26.100 15.300 ; RECT 21.900 15.000 28.200 15.300 ; RECT 27.000 15.000 28.200 28.200 ; RECT 22.500 8.100 23.700 9.300 ; RECT 22.500 8.400 28.200 9.300 ; RECT 27.000 1.800 28.200 12.000 ; LAYER via ; RECT 0.900 15.300 1.500 15.900 ; RECT 0.900 8.100 1.500 8.700 ; RECT 5.700 21.300 6.300 21.900 ; RECT 5.700 17.400 6.300 18.000 ; RECT 5.700 5.100 6.300 5.700 ; RECT 8.100 19.200 8.700 19.800 ; RECT 8.100 10.500 8.700 11.100 ; RECT 20.100 21.300 20.700 21.900 ; RECT 20.100 12.300 20.700 12.900 ; RECT 20.100 5.100 20.700 5.700 ; END END DFFNEGX1 MACRO NOR3X1 CLASS CORE ; FOREIGN NOR3X1 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 19.200 BY 30.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 3.000 6.900 4.200 8.100 ; END END A PIN B DIRECTION INPUT ; PORT LAYER metal1 ; RECT 5.400 9.900 6.600 11.100 ; END END B PIN C DIRECTION INPUT ; PORT LAYER metal1 ; RECT 7.800 12.900 9.000 14.100 ; END END C PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.600 -0.900 19.800 0.900 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 15.000 15.900 16.200 17.100 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.600 29.100 19.800 30.900 ; END END vdd OBS LAYER metal1 ; RECT 3.000 19.200 4.200 28.200 ; RECT 3.000 1.800 4.200 4.800 ; RECT 5.100 6.900 5.700 8.100 ; RECT 7.500 9.900 7.800 11.100 ; RECT 7.800 1.800 9.000 4.200 ; RECT 9.900 12.900 10.200 14.100 ; RECT 0.900 17.400 6.300 18.300 ; RECT 5.400 17.400 6.300 28.200 ; RECT 5.400 19.200 6.600 28.200 ; RECT 0.900 17.400 1.800 28.200 ; RECT 0.600 19.200 1.800 28.200 ; RECT 10.200 19.500 11.400 28.200 ; RECT 5.400 27.300 11.400 28.200 ; RECT 5.400 1.800 6.600 4.800 ; RECT 6.000 3.900 6.900 6.000 ; RECT 10.200 1.800 11.400 6.000 ; RECT 6.000 5.100 12.000 6.000 ; RECT 11.100 4.800 12.000 16.800 ; RECT 11.100 15.900 14.100 16.800 ; RECT 15.000 18.000 16.200 26.400 ; RECT 8.100 17.700 13.500 18.600 ; RECT 8.100 17.700 9.000 26.400 ; RECT 7.800 19.200 9.000 26.400 ; RECT 12.600 18.000 13.800 27.000 ; RECT 17.400 18.000 18.600 27.000 ; RECT 12.900 18.000 13.800 28.200 ; RECT 17.400 18.000 18.300 28.200 ; RECT 12.900 27.300 18.300 28.200 ; END END NOR3X1 MACRO DFFPOSX1 CLASS CORE ; FOREIGN DFFPOSX1 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 28.800 BY 30.000 ; SYMMETRY X Y ; SITE core ; PIN Q DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 27.000 12.900 28.200 14.100 ; END END Q PIN CLK DIRECTION INPUT ; PORT LAYER metal1 ; RECT 3.000 9.900 4.200 11.100 ; END END CLK PIN D DIRECTION INPUT ; PORT LAYER metal1 ; RECT 10.200 12.900 11.400 14.100 ; END END D PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.600 -0.900 29.400 0.900 ; END END gnd PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.600 29.100 29.400 30.900 ; END END vdd OBS LAYER metal2 ; RECT 0.600 7.800 1.800 16.200 ; RECT 5.400 4.800 6.600 22.200 ; RECT 19.800 4.800 21.000 22.200 ; LAYER metal1 ; RECT 0.600 1.800 1.800 9.000 ; RECT 1.800 9.900 2.100 11.100 ; RECT 3.000 16.500 4.200 28.200 ; RECT 3.000 1.800 4.200 7.800 ; RECT 5.400 21.000 6.600 23.100 ; RECT 5.400 22.200 8.400 23.100 ; RECT 7.200 22.200 8.400 28.200 ; RECT 7.200 1.800 8.400 4.800 ; RECT 5.400 3.900 8.400 4.800 ; RECT 5.400 3.900 6.600 6.000 ; RECT 3.900 12.600 5.100 13.800 ; RECT 3.900 12.900 9.300 13.800 ; RECT 11.400 22.200 12.600 28.200 ; RECT 11.100 1.800 12.600 4.800 ; RECT 5.400 17.100 13.500 18.000 ; RECT 5.400 17.100 6.600 18.300 ; RECT 12.300 17.100 13.500 18.300 ; RECT 13.800 1.800 15.000 4.800 ; RECT 13.800 1.800 14.700 6.600 ; RECT 10.500 5.700 14.700 6.600 ; RECT 10.500 5.700 11.700 6.900 ; RECT 10.500 20.100 11.700 21.300 ; RECT 14.700 20.100 15.900 21.300 ; RECT 10.500 20.400 15.900 21.300 ; RECT 13.800 20.400 14.700 28.200 ; RECT 13.800 22.200 15.000 28.200 ; RECT 16.200 22.200 17.400 28.200 ; RECT 16.200 1.800 17.400 4.800 ; RECT 0.600 15.000 9.300 15.600 ; RECT 0.600 14.700 9.000 15.600 ; RECT 8.100 15.300 15.300 16.200 ; RECT 14.400 15.300 15.300 18.900 ; RECT 16.500 17.700 17.700 18.900 ; RECT 14.400 18.000 17.700 18.900 ; RECT 0.600 14.700 1.800 28.200 ; RECT 19.800 21.000 21.000 22.200 ; RECT 20.100 22.200 21.900 28.200 ; RECT 20.100 1.800 21.900 4.800 ; RECT 19.800 3.900 21.000 6.000 ; RECT 7.800 5.700 9.000 6.900 ; RECT 8.100 5.700 9.000 11.100 ; RECT 16.500 9.900 17.700 11.100 ; RECT 5.100 10.200 18.300 11.100 ; RECT 6.300 10.200 7.500 11.400 ; RECT 17.400 10.200 18.300 16.800 ; RECT 17.400 15.900 21.000 16.800 ; RECT 20.100 15.900 21.000 19.500 ; RECT 20.100 18.300 22.200 19.500 ; RECT 19.800 12.000 21.000 13.200 ; RECT 19.800 12.300 25.500 13.200 ; RECT 24.300 12.300 25.500 13.500 ; RECT 24.600 16.200 25.800 28.200 ; RECT 24.600 1.800 25.800 7.500 ; RECT 21.900 14.100 23.100 15.300 ; RECT 21.900 14.400 26.100 15.300 ; RECT 21.900 15.000 28.200 15.300 ; RECT 27.000 15.000 28.200 28.200 ; RECT 22.500 8.100 23.700 9.300 ; RECT 22.500 8.400 28.200 9.300 ; RECT 27.000 1.800 28.200 12.000 ; LAYER via ; RECT 0.900 15.300 1.500 15.900 ; RECT 0.900 8.100 1.500 8.700 ; RECT 5.700 21.300 6.300 21.900 ; RECT 5.700 17.400 6.300 18.000 ; RECT 5.700 5.100 6.300 5.700 ; RECT 20.100 21.300 20.700 21.900 ; RECT 20.100 12.300 20.700 12.900 ; RECT 20.100 5.100 20.700 5.700 ; END END DFFPOSX1 MACRO FAX1 CLASS CORE ; FOREIGN FAX1 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 36.000 BY 30.000 ; SYMMETRY X Y ; SITE core ; PIN YC DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 34.200 9.900 35.400 11.100 ; END END YC PIN YS DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 31.800 6.900 33.000 8.100 ; END END YS PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.600 9.900 1.800 11.100 ; END END A PIN B DIRECTION INPUT ; PORT LAYER metal1 ; RECT 3.000 12.900 4.200 14.100 ; END END B PIN C DIRECTION INPUT ; PORT LAYER metal1 ; RECT 5.400 12.900 6.600 14.100 ; END END C PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.600 -0.900 36.600 0.900 ; END END gnd PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.600 29.100 36.600 30.900 ; END END vdd OBS LAYER metal2 ; RECT 21.600 6.300 22.800 7.500 ; RECT 21.900 11.700 30.300 12.600 ; RECT 29.100 11.700 30.300 12.900 ; RECT 21.900 6.300 22.800 15.300 ; RECT 21.600 14.100 22.800 15.300 ; RECT 7.800 6.600 9.000 7.800 ; RECT 18.000 14.400 19.200 17.100 ; RECT 31.200 15.900 32.400 17.100 ; RECT 7.800 16.200 32.400 17.100 ; RECT 8.100 6.600 9.000 17.400 ; RECT 7.800 16.200 9.000 17.400 ; LAYER metal1 ; RECT 3.000 18.000 4.200 28.200 ; RECT 3.000 1.800 4.200 6.000 ; RECT 0.600 16.200 6.600 17.100 ; RECT 0.600 16.200 1.800 28.200 ; RECT 5.400 16.200 6.600 28.200 ; RECT 0.600 1.800 1.800 7.800 ; RECT 5.400 1.800 6.600 7.800 ; RECT 0.600 6.900 6.600 7.800 ; RECT 7.800 16.200 9.000 28.200 ; RECT 7.800 1.800 9.000 7.800 ; RECT 11.700 16.200 12.900 28.200 ; RECT 11.700 1.800 12.900 7.200 ; RECT 16.500 19.200 17.700 28.200 ; RECT 16.500 1.800 17.700 5.700 ; RECT 14.100 17.400 20.100 18.300 ; RECT 14.100 16.200 15.300 28.200 ; RECT 18.900 17.400 20.100 28.200 ; RECT 14.100 1.800 15.300 7.500 ; RECT 18.900 1.800 20.100 7.500 ; RECT 14.100 6.600 20.100 7.500 ; RECT 19.200 14.100 20.400 15.300 ; RECT 18.000 14.400 19.200 15.600 ; RECT 21.600 14.100 22.800 28.200 ; RECT 21.300 15.300 22.800 28.200 ; RECT 15.600 12.300 22.800 13.200 ; RECT 21.600 12.000 22.800 13.200 ; RECT 7.500 12.900 17.700 13.500 ; RECT 7.500 12.900 16.500 13.800 ; RECT 7.500 12.900 7.800 14.100 ; RECT 21.300 1.800 22.800 6.300 ; RECT 21.600 1.800 22.800 7.500 ; RECT 4.200 10.500 25.200 11.100 ; RECT 14.100 10.200 25.200 11.100 ; RECT 3.300 10.800 15.300 11.400 ; RECT 24.000 10.200 25.200 11.400 ; RECT 3.300 10.800 5.400 11.700 ; RECT 8.700 10.500 9.900 11.700 ; RECT 3.300 10.800 4.200 12.000 ; RECT 1.800 8.700 27.600 9.000 ; RECT 11.100 8.400 27.600 9.300 ; RECT 2.700 8.700 12.300 9.600 ; RECT 2.700 8.700 3.000 9.900 ; RECT 26.700 8.400 27.600 11.400 ; RECT 26.700 10.200 27.900 11.400 ; RECT 27.000 13.800 28.200 28.200 ; RECT 27.000 1.800 28.200 7.500 ; RECT 29.100 10.500 30.300 12.900 ; RECT 31.200 9.000 32.100 14.700 ; RECT 29.100 13.800 32.100 14.700 ; RECT 29.100 13.800 30.000 23.100 ; RECT 29.400 22.200 30.600 28.200 ; RECT 29.400 1.800 30.600 4.800 ; RECT 29.700 1.800 30.600 6.600 ; RECT 29.700 5.700 32.100 6.000 ; RECT 29.700 5.700 30.900 6.600 ; RECT 31.800 22.200 33.000 28.200 ; RECT 31.800 1.800 33.000 4.800 ; RECT 31.200 15.900 33.600 17.100 ; RECT 34.500 12.000 35.400 28.200 ; RECT 34.200 22.200 35.400 28.200 ; RECT 34.200 1.800 35.400 4.800 ; RECT 34.500 1.800 35.400 9.000 ; LAYER via ; RECT 8.100 16.500 8.700 17.100 ; RECT 8.100 6.900 8.700 7.500 ; RECT 18.300 14.700 18.900 15.300 ; RECT 21.900 14.400 22.500 15.000 ; RECT 21.900 6.600 22.500 7.200 ; RECT 29.400 12.000 30.000 12.600 ; RECT 31.500 16.200 32.100 16.800 ; END END FAX1 MACRO HAX1 CLASS CORE ; FOREIGN HAX1 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 24.000 BY 30.000 ; SYMMETRY X Y ; SITE core ; PIN YC DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 7.800 15.900 9.000 17.100 ; END END YC PIN YS DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 19.800 15.900 21.000 17.100 ; END END YS PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.600 9.900 1.800 11.100 ; END END A PIN B DIRECTION INPUT ; PORT LAYER metal1 ; RECT 3.000 12.900 4.200 14.100 ; END END B PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.600 -0.900 24.600 0.900 ; END END gnd PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.600 29.100 24.600 30.900 ; END END vdd OBS LAYER metal2 ; RECT 5.700 6.900 6.900 8.100 ; RECT 5.700 6.900 6.600 13.800 ; RECT 5.700 12.600 6.900 13.800 ; RECT 6.900 4.800 9.000 6.000 ; RECT 8.100 4.800 9.000 13.800 ; RECT 7.800 12.600 9.000 13.800 ; LAYER metal1 ; RECT 0.600 1.800 1.800 7.800 ; RECT 1.200 8.700 2.400 9.000 ; RECT 3.000 22.800 4.200 28.200 ; RECT 5.700 12.600 6.900 13.800 ; RECT 0.900 21.000 6.600 21.900 ; RECT 0.900 21.000 1.800 28.200 ; RECT 0.600 22.200 1.800 28.200 ; RECT 5.700 12.600 6.600 28.200 ; RECT 5.400 21.000 6.600 28.200 ; RECT 6.900 1.800 8.100 6.000 ; RECT 4.500 1.800 5.700 7.800 ; RECT 5.700 6.900 8.400 8.100 ; RECT 7.800 18.000 9.000 28.200 ; RECT 7.800 12.600 9.000 15.000 ; RECT 9.300 1.800 10.500 7.500 ; RECT 10.200 22.200 11.400 28.200 ; RECT 3.600 10.800 11.700 11.700 ; RECT 3.600 10.800 4.800 12.000 ; RECT 10.800 11.700 13.800 12.600 ; RECT 12.600 11.700 13.800 12.900 ; RECT 2.700 9.000 13.500 9.900 ; RECT 12.600 9.900 16.200 10.800 ; RECT 15.000 9.900 16.200 11.100 ; RECT 16.500 16.200 17.700 28.200 ; RECT 11.700 1.800 17.700 2.700 ; RECT 16.500 1.800 17.700 7.200 ; RECT 11.700 1.800 12.900 7.800 ; RECT 14.100 3.600 15.300 7.800 ; RECT 14.400 3.600 15.300 9.000 ; RECT 14.400 8.100 18.900 9.000 ; RECT 17.100 8.100 18.900 9.300 ; RECT 17.100 8.100 18.000 15.300 ; RECT 12.900 14.400 18.000 15.300 ; RECT 12.900 14.400 13.800 28.200 ; RECT 12.600 16.200 13.800 28.200 ; RECT 18.900 22.200 20.100 28.200 ; RECT 18.900 1.800 20.100 4.800 ; RECT 20.100 18.000 21.000 21.300 ; RECT 20.100 20.400 22.500 21.300 ; RECT 21.600 20.400 22.500 28.200 ; RECT 21.300 22.200 22.500 28.200 ; RECT 21.300 1.800 22.500 4.800 ; RECT 21.600 1.800 22.500 6.900 ; RECT 20.100 6.000 22.500 6.900 ; RECT 20.100 6.000 21.000 15.000 ; LAYER via ; RECT 6.000 12.900 6.600 13.500 ; RECT 6.000 7.200 6.600 7.800 ; RECT 7.200 5.100 7.800 5.700 ; RECT 8.100 12.900 8.700 13.500 ; END END HAX1 MACRO INVX1 CLASS CORE ; FOREIGN INVX1 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 4.800 BY 30.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.600 6.900 1.800 8.100 ; END END A PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.600 -0.900 5.400 0.900 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 3.000 9.900 4.200 11.100 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.600 29.100 5.400 30.900 ; END END vdd OBS LAYER metal1 ; RECT 0.600 22.200 1.800 28.200 ; RECT 0.600 5.700 1.800 6.000 ; RECT 0.600 1.800 1.800 4.800 ; RECT 3.000 12.000 4.200 28.200 ; RECT 3.000 1.800 4.200 9.000 ; END END INVX1 MACRO INVX2 CLASS CORE ; FOREIGN INVX2 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 4.800 BY 30.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.600 9.900 1.800 11.100 ; END END A PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.600 -0.900 5.400 0.900 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 3.000 12.900 4.200 14.100 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.600 29.100 5.400 30.900 ; END END vdd OBS LAYER metal1 ; RECT 0.600 16.200 1.800 28.200 ; RECT 0.600 8.700 1.800 9.000 ; RECT 0.600 1.800 1.800 7.800 ; RECT 3.000 15.000 4.200 28.200 ; RECT 3.000 1.800 4.200 12.000 ; END END INVX2 MACRO INVX4 CLASS CORE ; FOREIGN INVX4 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 7.200 BY 30.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.600 9.900 1.800 11.100 ; END END A PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.600 -0.900 7.800 0.900 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 3.000 12.900 4.200 14.100 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.600 29.100 7.800 30.900 ; END END vdd OBS LAYER metal1 ; RECT 0.600 16.200 1.800 28.200 ; RECT 0.600 8.700 1.800 9.000 ; RECT 0.600 1.800 1.800 7.800 ; RECT 3.000 15.000 4.200 28.200 ; RECT 3.000 1.800 4.200 12.000 ; RECT 5.400 16.200 6.600 28.200 ; RECT 5.400 1.800 6.600 7.800 ; END END INVX4 MACRO INVX8 CLASS CORE ; FOREIGN INVX8 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 12.000 BY 30.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.600 9.900 1.800 11.100 ; END END A PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.600 -0.900 12.600 0.900 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 7.800 12.900 9.000 14.100 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.600 29.100 12.600 30.900 ; END END vdd OBS LAYER metal1 ; RECT 0.600 16.200 1.800 28.200 ; RECT 0.600 8.700 1.800 9.000 ; RECT 0.600 1.800 1.800 7.800 ; RECT 5.400 16.200 6.600 28.200 ; RECT 5.400 1.800 6.600 7.800 ; RECT 3.000 14.100 6.900 15.300 ; RECT 3.000 15.000 9.000 15.300 ; RECT 3.000 14.100 4.200 28.200 ; RECT 7.800 15.000 9.000 28.200 ; RECT 3.000 1.800 4.200 9.900 ; RECT 3.000 8.700 9.000 9.900 ; RECT 7.800 1.800 9.000 12.000 ; RECT 10.200 16.200 11.400 28.200 ; RECT 10.200 1.800 11.400 7.800 ; END END INVX8 MACRO NAND2X1 CLASS CORE ; FOREIGN NAND2X1 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 7.200 BY 30.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.600 9.900 1.800 11.100 ; END END A PIN B DIRECTION INPUT ; PORT LAYER metal1 ; RECT 5.400 15.900 6.600 17.100 ; END END B PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.600 -0.900 7.800 0.900 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 3.000 12.900 4.200 14.100 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.600 29.100 7.800 30.900 ; END END vdd OBS LAYER metal1 ; RECT 0.600 22.200 1.800 28.200 ; RECT 0.600 8.700 1.800 9.000 ; RECT 0.600 1.800 1.800 7.800 ; RECT 3.000 15.000 4.200 28.200 ; RECT 4.500 1.800 5.700 7.800 ; RECT 3.000 6.900 5.700 7.800 ; RECT 3.000 6.900 4.200 12.000 ; RECT 5.400 22.200 6.600 28.200 ; RECT 5.400 18.000 6.600 18.300 ; END END NAND2X1 MACRO NAND3X1 CLASS CORE ; FOREIGN NAND3X1 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 9.600 BY 30.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.600 15.900 1.800 17.100 ; END END A PIN B DIRECTION INPUT ; PORT LAYER metal1 ; RECT 3.000 12.900 4.200 14.100 ; END END B PIN C DIRECTION INPUT ; PORT LAYER metal1 ; RECT 5.400 18.900 6.600 20.100 ; END END C PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.600 -0.900 10.200 0.900 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 7.800 15.900 9.000 17.100 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.600 29.100 10.200 30.900 ; END END vdd OBS LAYER metal1 ; RECT 0.600 22.200 1.800 28.200 ; RECT 0.600 14.700 1.800 15.000 ; RECT 0.600 1.800 1.800 10.800 ; RECT 5.100 12.900 5.400 14.100 ; RECT 5.400 22.800 6.600 28.200 ; RECT 5.400 17.700 6.600 18.000 ; RECT 6.000 1.800 7.200 10.800 ; RECT 6.300 10.200 8.700 11.100 ; RECT 7.800 10.200 8.700 15.000 ; RECT 3.300 21.000 8.700 21.900 ; RECT 7.800 18.000 8.700 28.200 ; RECT 3.300 21.000 4.200 28.200 ; RECT 3.000 22.200 4.200 28.200 ; RECT 7.800 22.200 9.000 28.200 ; END END NAND3X1 MACRO NOR2X1 CLASS CORE ; FOREIGN NOR2X1 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 7.200 BY 30.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.600 6.900 1.800 8.100 ; END END A PIN B DIRECTION INPUT ; PORT LAYER metal1 ; RECT 5.400 12.900 6.600 14.100 ; END END B PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.600 -0.900 7.800 0.900 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 3.000 9.900 4.200 11.100 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.600 29.100 7.800 30.900 ; END END vdd OBS LAYER metal1 ; RECT 0.600 16.200 1.800 28.200 ; RECT 0.600 5.700 1.800 6.000 ; RECT 0.600 1.800 1.800 4.800 ; RECT 3.000 1.800 4.200 4.800 ; RECT 3.300 1.800 4.200 9.000 ; RECT 3.300 12.000 4.200 17.400 ; RECT 3.000 16.200 5.700 17.400 ; RECT 4.500 16.200 5.700 28.200 ; RECT 5.400 15.000 6.600 15.300 ; RECT 5.400 1.800 6.600 4.800 ; END END NOR2X1 MACRO OAI21X1 CLASS CORE ; FOREIGN OAI21X1 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 9.600 BY 30.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.600 9.900 1.800 11.100 ; END END A PIN B DIRECTION INPUT ; PORT LAYER metal1 ; RECT 3.000 12.900 4.200 14.100 ; END END B PIN C DIRECTION INPUT ; PORT LAYER metal1 ; RECT 7.800 15.900 9.000 17.100 ; END END C PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.600 -0.900 10.200 0.900 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 7.800 9.900 9.000 11.100 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.600 29.100 10.200 30.900 ; END END vdd OBS LAYER metal1 ; RECT 0.600 16.200 1.800 28.200 ; RECT 2.700 9.300 3.000 10.800 ; RECT 3.000 11.700 4.200 12.000 ; RECT 3.000 1.800 4.200 6.600 ; RECT 0.600 1.800 1.800 7.800 ; RECT 5.400 1.800 6.600 7.800 ; RECT 0.900 7.500 6.300 8.400 ; RECT 5.100 9.900 6.900 11.100 ; RECT 5.100 9.900 6.000 17.100 ; RECT 4.500 16.200 5.700 28.200 ; RECT 6.900 18.000 7.800 20.100 ; RECT 6.600 18.900 7.800 20.100 ; RECT 6.900 22.200 8.100 28.200 ; RECT 7.800 1.800 9.000 7.800 ; RECT 7.800 1.800 8.700 9.000 ; END END OAI21X1 MACRO OAI22X1 CLASS CORE ; FOREIGN OAI22X1 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 12.000 BY 30.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.600 9.900 1.800 11.100 ; END END A PIN B DIRECTION INPUT ; PORT LAYER metal1 ; RECT 3.000 12.900 4.200 14.100 ; END END B PIN C DIRECTION INPUT ; PORT LAYER metal1 ; RECT 10.200 9.900 11.400 11.100 ; END END C PIN D DIRECTION INPUT ; PORT LAYER metal1 ; RECT 7.800 12.900 9.000 14.100 ; END END D PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.600 -0.900 12.600 0.900 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 5.400 9.900 6.600 11.100 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.600 29.100 12.600 30.900 ; END END vdd OBS LAYER metal1 ; RECT 0.600 16.200 1.800 28.200 ; RECT 2.700 9.300 3.000 10.800 ; RECT 3.000 11.700 4.200 12.000 ; RECT 3.000 1.800 4.200 6.600 ; RECT 5.400 12.000 6.300 28.200 ; RECT 4.500 16.200 7.500 28.200 ; RECT 7.800 11.700 9.000 12.000 ; RECT 7.800 3.600 9.000 7.800 ; RECT 8.100 3.600 9.000 10.800 ; RECT 7.500 9.900 9.000 10.800 ; RECT 10.200 16.200 11.400 28.200 ; RECT 10.200 12.000 11.400 12.300 ; RECT 5.400 1.800 11.400 2.700 ; RECT 0.600 1.800 1.800 7.800 ; RECT 5.400 1.800 6.600 7.800 ; RECT 10.200 1.800 11.400 7.800 ; RECT 0.900 7.500 6.300 8.400 ; END END OAI22X1 MACRO OR2X1 CLASS CORE ; FOREIGN OR2X1 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 9.600 BY 30.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.600 6.900 1.800 8.100 ; END END A PIN B DIRECTION INPUT ; PORT LAYER metal1 ; RECT 3.000 9.900 4.200 11.100 ; END END B PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.600 -0.900 10.200 0.900 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 7.800 12.900 9.000 14.100 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.600 29.100 10.200 30.900 ; END END vdd OBS LAYER metal1 ; RECT 0.600 5.700 1.800 6.000 ; RECT 0.600 1.800 1.800 4.800 ; RECT 3.300 8.700 5.400 9.000 ; RECT 5.100 8.700 5.400 9.900 ; RECT 4.500 16.200 5.700 28.200 ; RECT 5.400 1.800 6.600 4.800 ; RECT 3.000 1.800 4.200 4.800 ; RECT 3.300 1.800 4.200 7.200 ; RECT 3.300 6.300 7.200 7.200 ; RECT 6.300 6.300 7.200 11.700 ; RECT 5.700 10.800 6.600 15.300 ; RECT 5.700 14.100 6.900 15.300 ; RECT 0.600 14.400 6.900 15.300 ; RECT 0.600 14.400 1.800 28.200 ; RECT 7.200 21.300 9.000 22.200 ; RECT 8.100 15.000 9.000 22.200 ; RECT 6.900 22.200 8.100 28.200 ; RECT 7.800 1.800 9.000 4.800 ; RECT 8.100 1.800 9.000 12.000 ; END END OR2X1 MACRO OR2X2 CLASS CORE ; FOREIGN OR2X2 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 9.600 BY 30.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.600 6.900 1.800 8.100 ; END END A PIN B DIRECTION INPUT ; PORT LAYER metal1 ; RECT 3.000 9.900 4.200 11.100 ; END END B PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.600 -0.900 10.200 0.900 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 7.800 12.900 9.000 14.100 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.600 29.100 10.200 30.900 ; END END vdd OBS LAYER metal1 ; RECT 0.600 5.700 1.800 6.000 ; RECT 0.600 1.800 1.800 4.800 ; RECT 3.600 12.000 4.800 12.300 ; RECT 4.500 16.200 5.700 28.200 ; RECT 5.400 1.800 6.600 7.200 ; RECT 3.000 1.800 4.200 4.800 ; RECT 3.300 1.800 4.200 9.000 ; RECT 3.300 8.100 6.900 9.000 ; RECT 5.700 13.500 6.900 14.700 ; RECT 6.000 8.100 6.900 14.700 ; RECT 0.600 14.400 6.600 15.300 ; RECT 0.600 14.400 1.800 28.200 ; RECT 8.100 15.000 9.000 17.100 ; RECT 6.900 16.200 8.100 28.200 ; RECT 7.800 1.800 9.000 7.800 ; RECT 8.100 1.800 9.000 12.000 ; END END OR2X2 MACRO TBUFX1 CLASS CORE ; FOREIGN TBUFX1 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 12.000 BY 30.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 10.200 9.900 11.400 11.100 ; END END A PIN EN DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.600 18.900 1.800 20.100 ; END END EN PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.600 -0.900 12.600 0.900 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 5.400 12.900 6.600 14.100 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.600 29.100 12.600 30.900 ; END END vdd OBS LAYER metal1 ; RECT 0.600 22.200 1.800 28.200 ; RECT 0.600 1.800 1.800 4.800 ; RECT 2.700 18.900 3.000 20.100 ; RECT 3.000 1.800 4.200 4.800 ; RECT 3.900 9.900 5.100 11.100 ; RECT 3.900 3.600 4.800 12.000 ; RECT 3.600 11.100 4.500 15.900 ; RECT 3.900 15.000 4.800 23.100 ; RECT 3.000 22.200 4.200 28.200 ; RECT 6.000 15.000 6.900 28.200 ; RECT 5.700 16.200 6.900 28.200 ; RECT 5.700 1.800 6.900 7.800 ; RECT 6.000 1.800 6.900 12.000 ; RECT 9.000 9.900 9.300 11.100 ; RECT 9.600 16.200 10.800 28.200 ; RECT 9.600 1.800 10.800 7.800 ; END END TBUFX1 MACRO TBUFX2 CLASS CORE ; FOREIGN TBUFX2 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 16.800 BY 30.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 15.000 9.900 16.200 11.100 ; END END A PIN EN DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.600 12.900 1.800 14.100 ; END END EN PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.600 -0.900 17.400 0.900 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 7.800 12.900 9.000 14.100 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.600 29.100 17.400 30.900 ; END END vdd OBS LAYER metal1 ; RECT 0.600 16.200 1.800 28.200 ; RECT 0.600 15.000 1.800 15.300 ; RECT 0.600 1.800 1.800 7.800 ; RECT 0.600 8.700 2.100 9.900 ; RECT 0.600 8.700 1.500 12.000 ; RECT 3.000 1.800 4.200 7.800 ; RECT 3.000 12.300 4.200 13.500 ; RECT 3.000 1.800 3.900 28.200 ; RECT 3.000 16.200 4.200 28.200 ; RECT 7.800 15.000 8.700 26.400 ; RECT 7.800 16.200 9.000 26.400 ; RECT 7.800 3.600 9.000 7.800 ; RECT 7.800 3.600 8.700 12.000 ; RECT 12.600 18.300 13.800 28.200 ; RECT 12.600 1.800 13.800 6.900 ; RECT 13.500 9.900 14.100 11.100 ; RECT 10.200 16.200 16.200 17.400 ; RECT 5.400 16.200 6.600 28.200 ; RECT 10.200 16.200 11.400 28.200 ; RECT 5.400 27.300 11.400 28.200 ; RECT 15.000 16.200 16.200 28.200 ; RECT 5.400 1.800 11.400 2.700 ; RECT 15.000 1.800 16.200 6.900 ; RECT 10.200 1.800 11.400 8.700 ; RECT 5.400 1.800 6.600 7.800 ; RECT 15.300 1.800 16.200 8.700 ; RECT 10.200 7.800 16.200 8.700 ; END END TBUFX2 MACRO XOR2X1 CLASS CORE ; FOREIGN XOR2X1 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 16.800 BY 30.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.600 9.900 1.800 11.100 ; END END A PIN B DIRECTION INPUT ; PORT LAYER metal1 ; RECT 15.000 9.900 16.200 11.100 ; END END B PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.600 -0.900 17.400 0.900 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 7.800 12.900 9.000 14.100 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.600 29.100 17.400 30.900 ; END END vdd OBS LAYER metal2 ; RECT 3.300 7.800 4.500 9.000 ; RECT 3.300 8.100 11.700 9.000 ; RECT 5.400 8.100 6.600 9.300 ; RECT 10.500 8.100 11.700 9.300 ; RECT 3.300 7.800 4.200 17.400 ; RECT 3.300 16.200 4.500 17.400 ; RECT 12.600 7.800 13.800 9.000 ; RECT 5.400 10.200 13.800 11.100 ; RECT 5.400 10.200 6.300 14.400 ; RECT 5.100 13.200 6.300 14.400 ; RECT 12.900 7.800 13.800 17.400 ; RECT 12.600 16.200 13.800 17.400 ; LAYER metal1 ; RECT 3.000 18.300 4.500 28.200 ; RECT 0.600 16.200 4.500 17.100 ; RECT 3.300 16.200 4.500 17.400 ; RECT 0.600 16.200 1.800 28.200 ; RECT 0.600 1.800 1.800 8.700 ; RECT 0.600 7.800 4.500 8.700 ; RECT 3.300 7.800 4.500 9.000 ; RECT 3.000 1.800 4.500 6.900 ; RECT 3.900 12.900 5.100 14.100 ; RECT 5.100 13.200 6.300 14.400 ; RECT 2.700 10.200 3.900 11.100 ; RECT 2.700 9.900 3.000 11.100 ; RECT 3.000 10.500 7.200 11.400 ; RECT 6.000 10.500 7.200 11.700 ; RECT 5.400 8.100 7.800 9.300 ; RECT 8.100 15.000 9.000 28.200 ; RECT 7.200 16.200 9.600 28.200 ; RECT 7.200 1.800 9.600 7.200 ; RECT 8.700 1.800 9.600 11.100 ; RECT 8.100 10.200 9.000 12.000 ; RECT 10.500 8.100 11.700 9.300 ; RECT 10.800 8.100 11.700 11.100 ; RECT 10.800 9.900 12.000 11.100 ; RECT 12.300 18.300 13.800 28.200 ; RECT 12.300 1.800 13.800 6.900 ; RECT 13.800 9.900 14.100 11.100 ; RECT 12.600 16.200 16.200 17.100 ; RECT 12.600 16.200 13.800 17.400 ; RECT 15.000 16.200 16.200 28.200 ; RECT 15.000 1.800 16.200 8.700 ; RECT 12.600 7.800 16.200 8.700 ; RECT 12.600 7.800 13.800 9.000 ; LAYER via ; RECT 3.600 16.500 4.200 17.100 ; RECT 3.600 8.100 4.200 8.700 ; RECT 5.400 13.500 6.000 14.100 ; RECT 5.700 8.400 6.300 9.000 ; RECT 10.800 8.400 11.400 9.000 ; RECT 12.900 16.500 13.500 17.100 ; RECT 12.900 8.100 13.500 8.700 ; END END XOR2X1 MACRO MUX2X1 CLASS CORE ; FOREIGN MUX2X1 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 14.400 BY 30.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 10.200 12.900 11.400 14.100 ; END END A PIN B DIRECTION INPUT ; PORT LAYER metal1 ; RECT 3.000 12.900 4.200 14.100 ; END END B PIN S DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.600 12.900 1.800 14.100 ; END END S PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.600 -0.900 15.000 0.900 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 10.200 9.900 11.400 11.100 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.600 29.100 15.000 30.900 ; END END vdd OBS LAYER metal1 ; RECT 0.600 11.700 1.800 12.000 ; RECT 3.000 16.800 4.200 28.200 ; RECT 3.000 11.700 4.200 12.000 ; RECT 3.000 1.800 4.200 8.400 ; RECT 0.600 3.000 1.800 6.000 ; RECT 0.600 3.000 1.500 10.200 ; RECT 0.600 9.300 6.900 10.200 ; RECT 5.400 9.300 6.900 12.000 ; RECT 5.400 10.800 7.500 12.000 ; RECT 5.400 9.300 6.300 15.900 ; RECT 0.600 15.000 6.300 15.900 ; RECT 0.600 15.000 1.500 27.000 ; RECT 0.600 21.000 1.800 27.000 ; RECT 6.900 3.000 8.100 8.400 ; RECT 8.100 7.500 9.300 9.000 ; RECT 8.400 7.500 9.300 17.700 ; RECT 6.900 16.800 9.300 17.700 ; RECT 6.900 16.800 8.100 28.200 ; RECT 10.200 15.000 11.400 15.300 ; RECT 10.800 16.200 12.000 28.200 ; RECT 10.800 1.800 12.000 9.000 ; END END MUX2X1 MACRO XNOR2X1 CLASS CORE ; FOREIGN XNOR2X1 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 16.800 BY 30.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.600 9.900 1.800 11.100 ; END END A PIN B DIRECTION INPUT ; PORT LAYER metal1 ; RECT 15.000 9.900 16.200 11.100 ; END END B PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.600 -0.900 17.400 0.900 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 10.200 12.900 11.400 14.100 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.600 29.100 17.400 30.900 ; END END vdd OBS LAYER metal2 ; RECT 2.700 7.800 3.900 9.000 ; RECT 2.700 7.800 3.600 17.400 ; RECT 2.700 16.200 3.900 17.400 ; RECT 5.400 8.100 11.700 9.000 ; RECT 5.400 8.100 6.600 9.300 ; RECT 10.500 8.100 11.700 9.300 ; RECT 12.600 7.800 13.800 9.000 ; RECT 6.600 10.200 13.800 11.100 ; RECT 6.600 10.200 7.800 11.400 ; RECT 12.900 7.800 13.800 17.400 ; RECT 12.600 16.200 13.800 17.400 ; LAYER metal1 ; RECT 0.600 1.800 1.800 8.700 ; RECT 0.600 7.800 3.900 8.700 ; RECT 2.700 7.800 3.900 9.000 ; RECT 3.000 18.300 4.500 28.200 ; RECT 3.000 1.800 4.500 6.900 ; RECT 6.600 10.200 7.800 11.400 ; RECT 6.600 10.200 7.500 13.200 ; RECT 3.600 12.300 7.500 13.200 ; RECT 3.600 12.300 4.800 13.500 ; RECT 5.400 8.100 7.800 9.300 ; RECT 4.800 8.400 5.700 10.800 ; RECT 2.700 9.900 5.700 10.800 ; RECT 2.700 9.900 3.000 11.100 ; RECT 6.900 14.100 8.100 15.300 ; RECT 3.000 14.400 8.100 15.300 ; RECT 0.600 16.200 3.900 17.100 ; RECT 3.000 14.400 3.900 17.400 ; RECT 2.700 16.200 3.900 17.400 ; RECT 0.600 16.200 1.800 28.200 ; RECT 7.200 1.800 9.600 7.200 ; RECT 8.700 1.800 9.600 12.000 ; RECT 8.700 1.800 9.300 13.200 ; RECT 9.300 15.000 10.200 17.100 ; RECT 7.200 16.200 9.600 28.200 ; RECT 10.500 8.100 11.700 9.300 ; RECT 10.800 8.100 11.700 11.100 ; RECT 10.800 9.900 12.000 11.100 ; RECT 12.300 18.300 13.800 28.200 ; RECT 12.300 1.800 13.800 6.900 ; RECT 13.800 9.900 14.100 11.100 ; RECT 12.600 16.200 16.200 17.100 ; RECT 12.600 16.200 13.800 17.400 ; RECT 15.000 16.200 16.200 28.200 ; RECT 15.000 1.800 16.200 8.700 ; RECT 12.600 7.800 16.200 8.700 ; RECT 12.600 7.800 13.800 9.000 ; LAYER via ; RECT 3.000 16.500 3.600 17.100 ; RECT 3.000 8.100 3.600 8.700 ; RECT 5.700 8.400 6.300 9.000 ; RECT 6.900 10.500 7.500 11.100 ; RECT 10.800 8.400 11.400 9.000 ; RECT 12.900 16.500 13.500 17.100 ; RECT 12.900 8.100 13.500 8.700 ; END END XNOR2X1 MACRO LATCH CLASS CORE ; FOREIGN LATCH 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 16.800 BY 30.000 ; SYMMETRY X Y ; SITE core ; PIN Q DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 15.000 12.900 16.200 14.100 ; END END Q PIN CLK DIRECTION INPUT ; PORT LAYER metal1 ; RECT 3.000 9.900 4.200 11.100 ; END END CLK PIN D DIRECTION INPUT ; PORT LAYER metal1 ; RECT 5.400 15.900 6.600 17.100 ; END END D PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.600 -0.900 17.400 0.900 ; END END gnd PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.600 29.100 17.400 30.900 ; END END vdd OBS LAYER metal2 ; RECT 0.600 7.800 1.800 16.200 ; RECT 7.800 4.800 9.000 22.200 ; LAYER metal1 ; RECT 0.600 14.700 1.800 28.200 ; RECT 0.600 1.800 1.800 9.000 ; RECT 1.800 9.900 2.100 11.100 ; RECT 3.000 16.200 4.200 28.200 ; RECT 3.000 1.800 4.200 7.800 ; RECT 3.900 14.100 6.600 15.000 ; RECT 3.900 14.100 4.500 15.300 ; RECT 0.600 12.000 7.500 12.900 ; RECT 0.600 12.000 1.800 13.200 ; RECT 6.300 12.000 7.500 13.200 ; RECT 7.800 21.000 9.000 28.200 ; RECT 7.500 22.200 9.300 28.200 ; RECT 7.500 1.800 9.300 4.800 ; RECT 7.800 1.800 9.000 6.000 ; RECT 6.600 6.900 7.800 10.800 ; RECT 5.100 9.900 9.900 10.800 ; RECT 8.700 9.900 9.900 12.300 ; RECT 12.600 16.200 13.800 28.200 ; RECT 12.600 1.800 13.800 7.800 ; RECT 7.800 14.100 14.100 15.300 ; RECT 15.000 15.000 16.200 28.200 ; RECT 15.000 1.800 16.200 12.000 ; RECT 11.100 11.400 16.200 12.000 ; RECT 11.100 11.400 14.100 12.600 ; LAYER via ; RECT 0.900 15.300 1.500 15.900 ; RECT 0.900 12.300 1.500 12.900 ; RECT 0.900 8.100 1.500 8.700 ; RECT 8.100 21.300 8.700 21.900 ; RECT 8.100 14.400 8.700 15.000 ; RECT 8.100 5.100 8.700 5.700 ; END END LATCH MACRO DFFSR CLASS CORE ; FOREIGN DFFSR 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 52.800 BY 30.000 ; SYMMETRY X Y ; SITE core ; PIN Q DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 48.600 18.900 49.800 20.100 ; END END Q PIN CLK DIRECTION INPUT ; PORT LAYER metal1 ; RECT 24.600 6.900 25.800 8.100 ; END END CLK PIN R DIRECTION INPUT ; PORT LAYER metal1 ; RECT 10.200 12.900 11.400 14.100 ; END END R PIN S DIRECTION INPUT ; PORT LAYER metal1 ; RECT 5.400 15.900 6.600 17.100 ; END END S PIN D DIRECTION INPUT ; PORT LAYER metal1 ; RECT 19.800 9.900 21.000 11.100 ; END END D PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.600 -0.900 53.400 0.900 ; END END gnd PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.600 29.100 53.400 30.900 ; RECT 5.400 22.200 6.600 30.900 ; END END vdd OBS LAYER metal2 ; RECT 12.600 4.800 13.800 25.200 ; RECT 15.000 4.800 16.200 25.200 ; RECT 17.400 4.800 18.600 22.200 ; RECT 22.200 4.800 23.400 22.200 ; RECT 27.000 4.800 28.200 22.200 ; RECT 29.400 4.800 30.600 25.200 ; RECT 31.800 4.800 33.000 25.200 ; RECT 34.200 4.800 35.400 25.200 ; LAYER metal1 ; RECT 0.600 22.200 1.800 28.200 ; RECT 5.400 1.800 6.600 7.800 ; RECT 2.700 13.200 3.900 14.400 ; RECT 2.700 13.500 9.300 14.400 ; RECT 10.200 22.200 11.400 28.200 ; RECT 10.200 1.800 11.400 7.800 ; RECT 7.500 6.600 11.400 7.800 ; RECT 7.500 6.600 8.700 9.900 ; RECT 4.200 8.700 8.700 9.900 ; RECT 12.600 24.000 13.800 28.200 ; RECT 0.600 10.800 13.800 12.000 ; RECT 0.600 1.800 1.800 21.300 ; RECT 0.600 20.400 3.600 21.300 ; RECT 2.700 20.400 3.600 23.100 ; RECT 3.000 22.200 4.200 28.200 ; RECT 12.600 1.800 13.800 6.000 ; RECT 15.000 24.000 16.200 28.200 ; RECT 8.100 17.400 16.200 18.300 ; RECT 15.000 17.100 16.200 18.300 ; RECT 6.900 18.000 9.000 19.200 ; RECT 15.000 1.800 16.200 6.000 ; RECT 17.400 21.000 18.600 28.200 ; RECT 17.400 1.800 18.600 6.000 ; RECT 19.800 22.200 21.000 28.200 ; RECT 19.800 8.700 21.000 9.000 ; RECT 19.800 1.800 21.000 4.800 ; RECT 22.200 21.000 23.400 28.200 ; RECT 19.500 18.900 23.400 20.100 ; RECT 16.500 6.900 23.400 7.800 ; RECT 22.200 6.900 23.400 8.100 ; RECT 16.500 6.900 17.700 12.600 ; RECT 14.700 11.400 17.700 12.600 ; RECT 22.200 1.800 23.400 6.000 ; RECT 24.600 22.200 25.800 28.200 ; RECT 24.600 1.800 25.800 4.800 ; RECT 26.700 6.900 27.000 8.100 ; RECT 27.000 18.900 28.200 28.200 ; RECT 23.400 11.400 28.200 12.600 ; RECT 27.000 1.800 28.200 6.000 ; RECT 22.200 9.000 23.400 10.200 ; RECT 22.200 9.300 28.800 10.200 ; RECT 27.600 9.300 28.800 10.500 ; RECT 29.400 24.000 30.600 28.200 ; RECT 17.700 17.100 30.600 18.000 ; RECT 29.400 17.100 30.600 18.300 ; RECT 3.000 18.300 5.400 19.500 ; RECT 4.500 18.300 5.400 21.300 ; RECT 9.900 19.200 18.600 20.100 ; RECT 17.700 17.100 18.600 20.100 ; RECT 4.500 20.100 10.800 21.300 ; RECT 7.800 20.100 9.000 28.200 ; RECT 29.400 1.800 30.600 6.000 ; RECT 31.800 24.000 33.000 28.200 ; RECT 31.500 6.900 33.000 8.100 ; RECT 31.800 6.900 33.000 12.300 ; RECT 31.800 1.800 33.000 6.000 ; RECT 34.200 24.000 35.400 28.200 ; RECT 34.200 1.800 35.400 6.000 ; RECT 36.600 22.200 37.800 28.200 ; RECT 36.600 12.600 37.800 14.400 ; RECT 12.300 13.500 37.800 14.400 ; RECT 31.800 20.100 38.100 21.300 ; RECT 41.400 22.200 42.600 28.200 ; RECT 41.400 1.800 42.600 7.800 ; RECT 39.000 18.900 42.900 20.100 ; RECT 39.000 18.900 40.200 28.200 ; RECT 44.700 15.000 45.900 16.200 ; RECT 7.500 15.300 45.900 16.200 ; RECT 10.500 15.300 11.700 16.500 ; RECT 36.600 1.800 37.800 7.800 ; RECT 36.600 6.600 40.200 7.800 ; RECT 39.000 6.600 40.200 9.600 ; RECT 39.000 8.700 41.700 9.600 ; RECT 40.500 8.700 41.700 12.600 ; RECT 40.500 11.400 46.200 12.600 ; RECT 46.200 22.200 47.400 28.200 ; RECT 46.200 1.800 47.400 10.500 ; RECT 47.100 9.600 48.000 14.400 ; RECT 34.200 17.100 47.700 18.000 ; RECT 34.200 17.100 35.400 18.300 ; RECT 46.800 13.500 47.700 21.300 ; RECT 43.800 20.400 47.700 21.300 ; RECT 43.800 20.400 45.000 28.200 ; RECT 48.600 21.000 49.800 28.200 ; RECT 48.600 1.800 49.800 8.700 ; RECT 48.900 7.500 50.100 16.500 ; RECT 48.600 15.300 49.800 18.000 ; RECT 51.000 22.200 52.200 28.200 ; RECT 51.000 1.800 52.200 4.800 ; LAYER via ; RECT 12.900 24.300 13.500 24.900 ; RECT 12.900 11.100 13.500 11.700 ; RECT 12.900 5.100 13.500 5.700 ; RECT 15.300 24.300 15.900 24.900 ; RECT 15.300 17.400 15.900 18.000 ; RECT 15.300 5.100 15.900 5.700 ; RECT 17.700 21.300 18.300 21.900 ; RECT 17.700 5.100 18.300 5.700 ; RECT 22.500 21.300 23.100 21.900 ; RECT 22.500 19.200 23.100 19.800 ; RECT 22.500 9.300 23.100 9.900 ; RECT 22.500 5.100 23.100 5.700 ; RECT 27.300 21.300 27.900 21.900 ; RECT 27.300 11.700 27.900 12.300 ; RECT 27.300 5.100 27.900 5.700 ; RECT 29.700 24.300 30.300 24.900 ; RECT 29.700 17.400 30.300 18.000 ; RECT 29.700 5.100 30.300 5.700 ; RECT 32.100 24.300 32.700 24.900 ; RECT 32.100 20.400 32.700 21.000 ; RECT 32.100 5.100 32.700 5.700 ; RECT 34.500 24.300 35.100 24.900 ; RECT 34.500 17.400 35.100 18.000 ; RECT 34.500 5.100 35.100 5.700 ; END END DFFSR MACRO CLKBUF1 CLASS CORE ; FOREIGN CLKBUF1 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 21.600 BY 30.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.600 9.900 1.800 11.100 ; END END A PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.600 -0.900 22.200 0.900 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 19.800 12.900 21.000 14.100 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.600 29.100 22.200 30.900 ; END END vdd OBS LAYER metal1 ; RECT 0.600 16.200 1.800 28.200 ; RECT 0.600 1.800 1.800 7.800 ; RECT 2.700 10.800 3.300 12.000 ; RECT 5.400 16.200 6.600 28.200 ; RECT 5.400 1.800 6.600 7.800 ; RECT 3.000 1.800 4.200 9.900 ; RECT 3.000 8.700 5.700 9.900 ; RECT 4.500 10.800 8.400 12.000 ; RECT 4.500 8.700 5.700 15.300 ; RECT 3.000 14.100 5.700 15.300 ; RECT 3.000 14.100 4.200 28.200 ; RECT 10.200 16.200 11.400 28.200 ; RECT 10.200 1.800 11.400 7.800 ; RECT 7.800 1.800 9.000 9.900 ; RECT 7.800 8.700 11.100 9.900 ; RECT 9.900 10.800 13.500 12.000 ; RECT 9.900 8.700 11.100 15.300 ; RECT 7.800 14.100 11.100 15.300 ; RECT 7.800 14.100 9.000 28.200 ; RECT 15.000 16.200 16.200 28.200 ; RECT 15.000 1.800 16.200 7.800 ; RECT 12.600 1.800 13.800 9.900 ; RECT 12.600 8.700 15.900 9.900 ; RECT 14.700 10.800 18.600 12.000 ; RECT 14.700 8.700 15.900 15.300 ; RECT 12.600 14.100 15.900 15.300 ; RECT 12.600 14.100 13.800 28.200 ; RECT 19.800 16.200 21.000 28.200 ; RECT 17.400 14.100 18.900 15.300 ; RECT 17.400 15.000 21.000 15.300 ; RECT 17.400 14.100 18.600 28.200 ; RECT 17.400 1.800 18.600 9.900 ; RECT 17.400 8.700 21.000 9.900 ; RECT 19.800 8.700 21.000 12.000 ; RECT 19.800 1.800 21.000 7.800 ; END END CLKBUF1 MACRO CLKBUF2 CLASS CORE ; FOREIGN CLKBUF2 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 31.200 BY 30.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.600 9.900 1.800 11.100 ; END END A PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.600 -0.900 31.800 0.900 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 29.400 12.900 30.600 14.100 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.600 29.100 31.800 30.900 ; END END vdd OBS LAYER metal1 ; RECT 0.600 16.200 1.800 28.200 ; RECT 0.600 1.800 1.800 7.800 ; RECT 2.700 10.800 3.300 12.000 ; RECT 5.400 16.200 6.600 28.200 ; RECT 5.400 1.800 6.600 7.800 ; RECT 3.000 1.800 4.200 9.900 ; RECT 3.000 8.700 5.700 9.900 ; RECT 4.500 10.800 8.400 12.000 ; RECT 4.500 8.700 5.700 15.300 ; RECT 3.000 14.100 5.700 15.300 ; RECT 3.000 14.100 4.200 28.200 ; RECT 10.200 16.200 11.400 28.200 ; RECT 10.200 1.800 11.400 7.800 ; RECT 7.800 1.800 9.000 9.900 ; RECT 7.800 8.700 11.100 9.900 ; RECT 9.900 10.800 13.500 12.000 ; RECT 9.900 8.700 11.100 15.300 ; RECT 7.800 14.100 11.100 15.300 ; RECT 7.800 14.100 9.000 28.200 ; RECT 15.000 16.200 16.200 28.200 ; RECT 15.000 1.800 16.200 7.800 ; RECT 12.600 1.800 13.800 9.900 ; RECT 12.600 8.700 15.900 9.900 ; RECT 14.700 10.800 18.600 12.000 ; RECT 14.700 8.700 15.900 15.300 ; RECT 12.600 14.100 15.900 15.300 ; RECT 12.600 14.100 13.800 28.200 ; RECT 19.800 16.200 21.000 28.200 ; RECT 19.800 1.800 21.000 7.800 ; RECT 17.400 1.800 18.600 9.900 ; RECT 17.400 8.700 21.000 9.900 ; RECT 19.800 10.800 22.500 12.000 ; RECT 19.800 8.700 21.000 15.300 ; RECT 17.400 14.100 21.000 15.300 ; RECT 17.400 14.100 18.600 28.200 ; RECT 24.600 16.200 25.800 28.200 ; RECT 24.600 1.800 25.800 7.800 ; RECT 22.200 1.800 23.400 9.900 ; RECT 22.200 8.700 24.900 9.900 ; RECT 23.700 10.800 27.600 12.000 ; RECT 23.700 8.700 24.900 15.300 ; RECT 22.200 14.100 24.900 15.300 ; RECT 22.200 14.100 23.400 28.200 ; RECT 29.400 16.200 30.600 28.200 ; RECT 27.000 14.100 28.500 15.300 ; RECT 27.000 15.000 30.600 15.300 ; RECT 27.000 14.100 28.200 28.200 ; RECT 27.000 1.800 28.200 9.900 ; RECT 27.000 8.700 30.600 9.900 ; RECT 29.400 8.700 30.600 12.000 ; RECT 29.400 1.800 30.600 7.800 ; END END CLKBUF2 MACRO CLKBUF3 CLASS CORE ; FOREIGN CLKBUF3 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 40.800 BY 30.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.600 9.900 1.800 11.100 ; END END A PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.600 -0.900 41.400 0.900 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 39.000 12.900 40.200 14.100 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.600 29.100 41.400 30.900 ; END END vdd OBS LAYER metal1 ; RECT 0.600 16.200 1.800 28.200 ; RECT 0.600 1.800 1.800 7.800 ; RECT 2.700 10.800 3.300 12.000 ; RECT 5.400 16.200 6.600 28.200 ; RECT 5.400 1.800 6.600 7.800 ; RECT 3.000 1.800 4.200 9.900 ; RECT 3.000 8.700 5.700 9.900 ; RECT 4.500 10.800 8.400 12.000 ; RECT 4.500 8.700 5.700 15.300 ; RECT 3.000 14.100 5.700 15.300 ; RECT 3.000 14.100 4.200 28.200 ; RECT 10.200 16.200 11.400 28.200 ; RECT 10.200 1.800 11.400 7.800 ; RECT 7.800 1.800 9.000 9.900 ; RECT 7.800 8.700 11.100 9.900 ; RECT 9.900 10.800 13.500 12.000 ; RECT 9.900 8.700 11.100 15.300 ; RECT 7.800 14.100 11.100 15.300 ; RECT 7.800 14.100 9.000 28.200 ; RECT 15.000 16.200 16.200 28.200 ; RECT 15.000 1.800 16.200 7.800 ; RECT 12.600 1.800 13.800 9.900 ; RECT 12.600 8.700 15.900 9.900 ; RECT 14.700 10.800 18.600 12.000 ; RECT 14.700 8.700 15.900 15.300 ; RECT 12.600 14.100 15.900 15.300 ; RECT 12.600 14.100 13.800 28.200 ; RECT 19.800 16.200 21.000 28.200 ; RECT 19.800 1.800 21.000 7.800 ; RECT 17.400 1.800 18.600 9.900 ; RECT 17.400 8.700 21.000 9.900 ; RECT 19.800 10.800 22.500 12.000 ; RECT 19.800 8.700 21.000 15.300 ; RECT 17.400 14.100 21.000 15.300 ; RECT 17.400 14.100 18.600 28.200 ; RECT 24.600 16.200 25.800 28.200 ; RECT 24.600 1.800 25.800 7.800 ; RECT 22.200 1.800 23.400 9.900 ; RECT 22.200 8.700 24.900 9.900 ; RECT 23.700 10.800 27.600 12.000 ; RECT 23.700 8.700 24.900 15.300 ; RECT 22.200 14.100 24.900 15.300 ; RECT 22.200 14.100 23.400 28.200 ; RECT 29.400 16.200 30.600 28.200 ; RECT 29.400 1.800 30.600 7.800 ; RECT 27.000 1.800 28.200 9.900 ; RECT 27.000 8.700 30.300 9.900 ; RECT 29.100 10.800 32.700 12.000 ; RECT 29.100 8.700 30.300 15.300 ; RECT 27.000 14.100 30.300 15.300 ; RECT 27.000 14.100 28.200 28.200 ; RECT 34.200 16.200 35.400 28.200 ; RECT 34.200 1.800 35.400 7.800 ; RECT 31.800 1.800 33.000 9.900 ; RECT 31.800 8.700 35.100 9.900 ; RECT 33.900 10.800 37.800 12.000 ; RECT 33.900 8.700 35.100 15.300 ; RECT 31.800 14.100 35.100 15.300 ; RECT 31.800 14.100 33.000 28.200 ; RECT 39.000 16.200 40.200 28.200 ; RECT 36.600 14.100 38.100 15.300 ; RECT 36.600 15.000 40.200 15.300 ; RECT 36.600 14.100 37.800 28.200 ; RECT 36.600 1.800 37.800 9.900 ; RECT 36.600 8.700 40.200 9.900 ; RECT 39.000 8.700 40.200 12.000 ; RECT 39.000 1.800 40.200 7.800 ; END END CLKBUF3 MACRO PADFC CLASS ENDCAP TOPLEFT ; FOREIGN PADFC 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 300.000 BY 300.000 ; SYMMETRY X Y R90 ; SITE corner ; OBS LAYER metal3 ; RECT 0.900 0.900 299.100 299.100 ; LAYER metal2 ; RECT 99.000 0.000 168.000 299.100 ; RECT 172.800 0.000 196.500 299.100 ; RECT 202.200 0.000 225.900 299.100 ; RECT 230.700 0.000 300.000 69.000 ; RECT 0.900 73.800 300.000 98.100 ; RECT 0.900 103.200 300.000 126.900 ; RECT 0.900 132.300 300.000 201.000 ; RECT 0.900 0.900 299.100 299.100 ; LAYER metal1 ; RECT 99.000 0.000 196.500 299.100 ; RECT 202.200 0.000 300.000 98.100 ; RECT 0.900 103.200 300.000 201.000 ; RECT 0.900 0.900 299.100 299.100 ; END END PADFC MACRO PADGND CLASS PAD ; FOREIGN PADGND 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 90.000 BY 300.000 ; SYMMETRY R90 ; SITE IO ; PIN YPAD DIRECTION OUTPUT ; PORT LAYER metal3 ; RECT 43.200 260.400 50.100 267.300 ; END END YPAD PIN gnd DIRECTION INOUT ; USE GROUND ; PORT CLASS CORE ; LAYER metal1 ; RECT 30.600 0.000 59.400 1.200 ; END END gnd OBS LAYER metal3 ; RECT 0.900 0.900 89.100 258.600 ; RECT 0.900 0.900 41.400 299.100 ; RECT 51.900 0.900 89.100 299.100 ; RECT 0.900 269.100 89.100 299.100 ; LAYER metal2 ; RECT 0.000 0.000 90.000 69.000 ; RECT 0.000 73.800 90.000 97.800 ; RECT 0.000 103.200 90.000 127.200 ; RECT 0.000 132.000 90.000 201.000 ; RECT 0.900 0.000 89.100 299.100 ; RECT 6.000 0.000 84.000 300.000 ; LAYER metal1 ; RECT 0.000 0.300 29.700 97.800 ; RECT 60.300 0.300 90.000 97.800 ; RECT 0.000 103.200 90.000 201.000 ; RECT 0.900 2.700 89.100 299.100 ; RECT 6.000 2.700 84.000 300.000 ; END END PADGND MACRO PADINC CLASS PAD ; FOREIGN PADINC 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 90.000 BY 300.000 ; SYMMETRY R90 ; SITE IO ; PIN YPAD DIRECTION OUTPUT ; PORT LAYER metal3 ; RECT 42.900 263.400 44.700 265.200 ; END END YPAD PIN DI DIRECTION OUTPUT ; PORT LAYER metal2 ; RECT 77.700 -0.600 78.900 0.600 ; RECT 77.100 0.000 79.800 0.600 ; END END DI OBS LAYER metal3 ; RECT 0.900 0.900 75.300 261.600 ; RECT 0.900 0.900 41.100 299.100 ; RECT 46.500 2.400 89.100 299.100 ; RECT 81.600 0.900 89.100 299.100 ; RECT 0.900 267.000 89.100 299.100 ; LAYER metal2 ; RECT 0.000 0.000 36.900 69.000 ; RECT 38.400 0.000 51.600 300.000 ; RECT 52.800 0.000 72.000 300.000 ; RECT 73.200 0.000 75.900 300.000 ; RECT 0.000 0.900 75.900 69.000 ; RECT 81.000 0.000 90.000 69.000 ; RECT 0.000 73.800 90.000 97.800 ; RECT 0.000 102.900 90.000 126.600 ; RECT 0.000 131.700 90.000 201.000 ; RECT 0.900 2.100 89.100 299.100 ; RECT 6.000 2.100 84.000 300.000 ; LAYER metal1 ; RECT 0.000 0.000 90.000 99.600 ; RECT 0.000 102.300 90.000 200.700 ; RECT 0.900 0.000 89.100 299.100 ; RECT 6.000 0.000 84.000 300.000 ; END END PADINC MACRO PADOUT CLASS PAD ; FOREIGN PADOUT 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 90.000 BY 300.000 ; SYMMETRY R90 ; SITE IO ; PIN YPAD DIRECTION OUTPUT ; PORT LAYER metal3 ; RECT 41.700 259.500 43.500 261.300 ; END END YPAD PIN DO DIRECTION INPUT ; PORT LAYER metal2 ; RECT 13.800 -0.600 15.000 0.600 ; RECT 13.200 0.000 15.900 0.600 ; END END DO OBS LAYER metal3 ; RECT 0.900 0.900 11.400 299.100 ; RECT 17.700 0.900 89.100 257.700 ; RECT 0.900 2.400 39.900 299.100 ; RECT 45.300 0.900 89.100 299.100 ; RECT 0.900 263.100 89.100 299.100 ; LAYER metal2 ; RECT 0.000 0.000 2.100 69.000 ; RECT 17.100 0.000 36.900 300.000 ; RECT 38.400 0.000 51.600 300.000 ; RECT 52.800 0.000 72.000 300.000 ; RECT 73.200 0.000 75.900 300.000 ; RECT 77.100 0.000 79.800 300.000 ; RECT 7.200 0.000 12.000 300.000 ; RECT 0.000 0.900 12.000 69.000 ; RECT 17.100 0.900 90.000 69.000 ; RECT 81.000 0.000 90.000 69.000 ; RECT 0.000 73.800 90.000 97.800 ; RECT 0.000 102.900 90.000 126.600 ; RECT 0.000 131.700 90.000 201.000 ; RECT 0.900 2.100 89.100 299.100 ; RECT 6.000 2.100 84.000 300.000 ; LAYER metal1 ; RECT 0.000 0.000 90.000 99.600 ; RECT 0.000 102.300 90.000 200.700 ; RECT 0.900 0.000 89.100 299.100 ; RECT 6.000 0.000 84.000 300.000 ; END END PADOUT MACRO PADNC CLASS PAD ; FOREIGN PADNC 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 90.000 BY 300.000 ; SYMMETRY R90 ; SITE IO ; OBS LAYER metal3 ; RECT 0.900 0.900 89.100 299.100 ; LAYER metal2 ; RECT 0.000 0.000 90.000 69.000 ; RECT 0.000 73.800 90.000 97.800 ; RECT 0.000 103.200 90.000 127.200 ; RECT 0.000 132.000 90.000 201.000 ; RECT 0.900 0.000 89.100 299.100 ; RECT 6.000 0.000 84.000 300.000 ; LAYER metal1 ; RECT 0.000 0.300 90.000 97.800 ; RECT 0.000 103.200 90.000 201.000 ; RECT 0.900 0.300 89.100 299.100 ; RECT 6.000 0.300 84.000 300.000 ; END END PADNC MACRO PADVDD CLASS PAD ; FOREIGN PADVDD 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 90.000 BY 300.000 ; SYMMETRY R90 ; SITE IO ; PIN YPAD DIRECTION OUTPUT ; PORT LAYER metal3 ; RECT 39.000 256.500 42.900 260.400 ; END END YPAD PIN vdd DIRECTION INOUT ; USE POWER ; PORT CLASS CORE ; LAYER metal1 ; RECT 30.600 0.000 59.400 1.200 ; END END vdd OBS LAYER metal3 ; RECT 0.900 0.900 89.100 254.700 ; RECT 6.900 0.900 37.200 299.100 ; RECT 44.700 0.900 89.100 299.100 ; RECT 0.900 262.200 89.100 299.100 ; LAYER metal2 ; RECT 0.000 0.000 29.400 69.000 ; RECT 60.600 0.000 90.000 69.000 ; RECT 0.000 73.800 90.000 97.800 ; RECT 0.000 103.200 90.000 127.200 ; RECT 0.000 132.000 90.000 201.000 ; RECT 0.900 2.100 89.100 299.100 ; RECT 6.000 2.100 84.000 300.000 ; LAYER metal1 ; RECT 0.000 0.000 29.700 97.800 ; RECT 60.300 0.000 90.000 97.800 ; RECT 0.000 103.200 90.000 201.000 ; RECT 0.900 2.700 89.100 299.100 ; RECT 6.000 2.700 84.000 300.000 ; END END PADVDD MACRO PADINOUT CLASS PAD ; FOREIGN PADINOUT 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 90.000 BY 300.000 ; SYMMETRY R90 ; SITE IO ; PIN YPAD DIRECTION OUTPUT ; PORT LAYER metal3 ; RECT 38.100 252.600 43.500 257.700 ; END END YPAD PIN DO DIRECTION INPUT ; PORT LAYER metal2 ; RECT 13.800 -0.600 15.000 0.600 ; RECT 13.200 0.000 15.900 0.600 ; END END DO PIN DI DIRECTION OUTPUT ; PORT LAYER metal2 ; RECT 77.700 -0.600 78.900 0.600 ; RECT 77.100 0.000 79.800 0.600 ; END END DI PIN OEN DIRECTION INPUT ; PORT LAYER metal2 ; RECT 3.900 -0.600 5.100 0.600 ; RECT 3.300 0.000 6.000 0.600 ; END END OEN OBS LAYER metal3 ; RECT 0.900 0.900 1.500 250.800 ; RECT 7.800 0.900 11.400 299.100 ; RECT 17.700 0.900 75.300 250.800 ; RECT 0.900 2.400 89.100 250.800 ; RECT 6.900 2.400 36.300 299.100 ; RECT 45.300 2.400 89.100 299.100 ; RECT 81.600 0.900 89.100 299.100 ; RECT 0.900 259.500 89.100 299.100 ; LAYER metal2 ; RECT 17.100 0.000 36.900 300.000 ; RECT 38.400 0.000 51.600 300.000 ; RECT 52.800 0.000 72.000 300.000 ; RECT 0.000 0.000 2.100 69.000 ; RECT 7.200 0.000 12.000 300.000 ; RECT 73.200 0.000 75.900 300.000 ; RECT 17.100 0.900 75.900 300.000 ; RECT 81.000 0.000 90.000 69.000 ; RECT 0.000 73.800 90.000 97.800 ; RECT 0.000 102.900 90.000 126.600 ; RECT 0.000 131.700 90.000 201.000 ; RECT 0.900 2.100 89.100 299.100 ; RECT 6.000 2.100 84.000 300.000 ; LAYER metal1 ; RECT 0.000 0.000 90.000 99.600 ; RECT 0.000 102.300 90.000 200.700 ; RECT 0.900 0.000 89.100 299.100 ; RECT 6.000 0.000 84.000 300.000 ; END END PADINOUT END LIBRARY qflow-1.1.23/tech/osu050/osu05_stdcells.lib0000755000175000001440000077425312526236535017012 0ustar timusers/* delay model : typ check model : typ power model : typ capacitance model : typ other model : typ */ library(osu05_stdcells) { delay_model : table_lookup; in_place_swap_mode : match_footprint; /* unit attributes */ time_unit : "1ns"; voltage_unit : "1V"; current_unit : "1uA"; pulling_resistance_unit : "1kohm"; leakage_power_unit : "1nW"; capacitive_load_unit (1,pf); slew_upper_threshold_pct_rise : 80; slew_lower_threshold_pct_rise : 20; slew_upper_threshold_pct_fall : 80; slew_lower_threshold_pct_fall : 20; input_threshold_pct_rise : 50; input_threshold_pct_fall : 50; output_threshold_pct_rise : 50; output_threshold_pct_fall : 50; nom_process : 1; nom_voltage : 5; nom_temperature : 25; operating_conditions ( typical ) { process : 1; voltage : 5; temperature : 25; } default_operating_conditions : typical; lu_table_template(delay_template_5x1) { variable_1 : input_net_transition; index_1 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0"); } lu_table_template(delay_template_5x5) { variable_1 : total_output_net_capacitance; variable_2 : input_net_transition; index_1 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0"); index_2 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0"); } lu_table_template(delay_template_5x6) { variable_1 : total_output_net_capacitance; variable_2 : input_net_transition; index_1 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0"); index_2 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"); } lu_table_template(delay_template_6x1) { variable_1 : input_net_transition; index_1 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"); } lu_table_template(delay_template_6x6) { variable_1 : total_output_net_capacitance; variable_2 : input_net_transition; index_1 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"); index_2 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"); } power_lut_template(energy_template_5x5) { variable_1 : total_output_net_capacitance; variable_2 : input_transition_time; index_1 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0"); index_2 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0"); } power_lut_template(energy_template_5x6) { variable_1 : total_output_net_capacitance; variable_2 : input_transition_time; index_1 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0"); index_2 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"); } power_lut_template(energy_template_6x6) { variable_1 : total_output_net_capacitance; variable_2 : input_transition_time; index_1 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"); index_2 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"); } lu_table_template(hold_template_3x5) { variable_1 : related_pin_transition; variable_2 : constrained_pin_transition; index_1 ("1000.0, 1001.0, 1002.0"); index_2 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0"); } lu_table_template(hold_template_3x6) { variable_1 : related_pin_transition; variable_2 : constrained_pin_transition; index_1 ("1000.0, 1001.0, 1002.0"); index_2 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"); } power_lut_template(passive_energy_template_5x1) { variable_1 : input_transition_time; index_1 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0"); } power_lut_template(passive_energy_template_6x1) { variable_1 : input_transition_time; index_1 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"); } lu_table_template(recovery_template_3x6) { variable_1 : related_pin_transition; variable_2 : constrained_pin_transition; index_1 ("1000.0, 1001.0, 1002.0"); index_2 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"); } lu_table_template(recovery_template_6x6) { variable_1 : related_pin_transition; variable_2 : constrained_pin_transition; index_1 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"); index_2 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"); } lu_table_template(removal_template_3x6) { variable_1 : related_pin_transition; variable_2 : constrained_pin_transition; index_1 ("1000.0, 1001.0, 1002.0"); index_2 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"); } lu_table_template(setup_template_3x5) { variable_1 : related_pin_transition; variable_2 : constrained_pin_transition; index_1 ("1000.0, 1001.0, 1002.0"); index_2 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0"); } lu_table_template(setup_template_3x6) { variable_1 : related_pin_transition; variable_2 : constrained_pin_transition; index_1 ("1000.0, 1001.0, 1002.0"); index_2 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"); } /* --------------- * * Design : AND2X1 * * --------------- */ cell (AND2X1) { area : 288; cell_leakage_power : 0.1173; pin(A) { direction : input; capacitance : 0.021636; rise_capacitance : 0.021558; fall_capacitance : 0.021636; } pin(B) { direction : input; capacitance : 0.021487; rise_capacitance : 0.0214248; fall_capacitance : 0.021487; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.412286; function : "(A B)"; timing() { related_pin : "A"; timing_sense : positive_unate; cell_rise(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.135468, 0.140265, 0.143242, 0.13881, 0.114394", \ "0.183319, 0.188338, 0.192664, 0.189481, 0.166138", \ "0.273479, 0.278684, 0.28851, 0.283829, 0.263192", \ "0.633258, 0.642891, 0.649771, 0.649274, 0.635584", \ "1.17327, 1.18296, 1.18962, 1.18895, 1.17762"); } rise_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0882, 0.0924, 0.0966, 0.099, 0.1194", \ "0.15, 0.153, 0.1608, 0.1644, 0.1788", \ "0.2802, 0.282, 0.2862, 0.2916, 0.3078", \ "0.816, 0.816, 0.8178, 0.8202, 0.8334", \ "1.6218, 1.6218, 1.6218, 1.6224, 1.6278"); } cell_fall(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.167177, 0.202284, 0.265877, 0.308151, 0.430135", \ "0.224319, 0.259107, 0.322892, 0.36637, 0.491938", \ "0.335646, 0.36992, 0.433808, 0.478536, 0.607888", \ "0.780065, 0.81504, 0.877625, 0.920222, 1.05187", \ "1.44281, 1.47773, 1.54009, 1.58262, 1.71347"); } fall_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0924, 0.093, 0.1026, 0.1098, 0.123", \ "0.1596, 0.1602, 0.1626, 0.1692, 0.1848", \ "0.3, 0.2994, 0.3024, 0.3054, 0.3198", \ "0.8784, 0.8778, 0.8778, 0.879, 0.8832", \ "1.7466, 1.7466, 1.7472, 1.7466, 1.7472"); } } timing() { related_pin : "B"; timing_sense : positive_unate; cell_rise(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.136152, 0.134149, 0.125177, 0.110593, 0.042182", \ "0.183231, 0.182144, 0.17419, 0.160977, 0.096749", \ "0.274689, 0.272369, 0.266243, 0.255334, 0.19685", \ "0.634485, 0.635477, 0.627876, 0.618186, 0.573561", \ "1.17451, 1.17509, 1.1673, 1.15736, 1.11436"); } rise_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0882, 0.0924, 0.1062, 0.1128, 0.1254", \ "0.15, 0.1518, 0.162, 0.168, 0.1836", \ "0.2796, 0.2814, 0.2874, 0.2922, 0.3132", \ "0.8166, 0.816, 0.8166, 0.819, 0.8364", \ "1.6218, 1.6218, 1.6218, 1.6224, 1.6278"); } cell_fall(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.184677, 0.225252, 0.305561, 0.360668, 0.524913", \ "0.242571, 0.284064, 0.362196, 0.417523, 0.585336", \ "0.35573, 0.394873, 0.473847, 0.52801, 0.697587", \ "0.797996, 0.837006, 0.915518, 0.968772, 1.13728", \ "1.46119, 1.49974, 1.57798, 1.63114, 1.79857"); } fall_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0948, 0.0966, 0.1014, 0.1044, 0.1242", \ "0.1602, 0.1602, 0.1626, 0.168, 0.1854", \ "0.3012, 0.3012, 0.3024, 0.3042, 0.3144", \ "0.8784, 0.8784, 0.8784, 0.8784, 0.8808", \ "1.7466, 1.7472, 1.7472, 1.7466, 1.7472"); } } internal_power() { related_pin : "A"; rise_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.175608, 0.272801, 0.56388, 0.796823, 1.60912", \ "0.179968, 0.272459, 0.560982, 0.787696, 1.58173", \ "0.183768, 0.275337, 0.554906, 0.779866, 1.55639", \ "0.186245, 0.28634, 0.555533, 0.774262, 1.53242", \ "0.187373, 0.286781, 0.556141, 0.773763, 1.52594"); } fall_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.682097, 0.778941, 1.07036, 1.30235, 2.11129", \ "0.689417, 0.782563, 1.06662, 1.29547, 2.08731", \ "0.695489, 0.786172, 1.06565, 1.29154, 2.06909", \ "0.695343, 0.788895, 1.06847, 1.29133, 2.05413", \ "0.69663, 0.790587, 1.06979, 1.29218, 2.05161"); } } internal_power() { related_pin : "B"; rise_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.160502, 0.275229, 0.589983, 0.855199, 1.76734", \ "0.167535, 0.276072, 0.579905, 0.83989, 1.73518", \ "0.172685, 0.276093, 0.574742, 0.828704, 1.70676", \ "0.177439, 0.274921, 0.574026, 0.821518, 1.67723", \ "0.178672, 0.274961, 0.57311, 0.818917, 1.66749"); } fall_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.849374, 0.958819, 1.29574, 1.55392, 2.45958", \ "0.857665, 0.975853, 1.28725, 1.54387, 2.4309", \ "0.863952, 0.977353, 1.28374, 1.53701, 2.40901", \ "0.87666, 0.981387, 1.28499, 1.53302, 2.38627", \ "0.872437, 0.982928, 1.28642, 1.53364, 2.3813"); } } } } /* --------------- * * Design : AND2X2 * * --------------- */ cell (AND2X2) { area : 288; cell_leakage_power : 0.117282; pin(A) { direction : input; capacitance : 0.021674; rise_capacitance : 0.021579; fall_capacitance : 0.021674; } pin(B) { direction : input; capacitance : 0.0214177; rise_capacitance : 0.0214177; fall_capacitance : 0.0214044; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.924889; function : "(A B)"; timing() { related_pin : "A"; timing_sense : positive_unate; cell_rise(delay_template_5x5) { index_1 ("0.05, 0.1, 0.2, 0.6, 1.2"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.16526, 0.180035, 0.193325, 0.200733, 0.189787", \ "0.212238, 0.22752, 0.241381, 0.247528, 0.240223", \ "0.299235, 0.31434, 0.330401, 0.33598, 0.331624", \ "0.646012, 0.658718, 0.676894, 0.681547, 0.681522", \ "1.16308, 1.17522, 1.19322, 1.19738, 1.19816"); } rise_transition(delay_template_5x5) { index_1 ("0.05, 0.1, 0.2, 0.6, 1.2"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.096, 0.0966, 0.102, 0.1152, 0.1284", \ "0.1506, 0.153, 0.1608, 0.1638, 0.1806", \ "0.273, 0.2736, 0.2796, 0.2832, 0.2988", \ "0.7842, 0.7842, 0.786, 0.7878, 0.798", \ "1.5558, 1.5564, 1.5558, 1.5564, 1.5612"); } cell_fall(delay_template_5x5) { index_1 ("0.05, 0.1, 0.2, 0.6, 1.2"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.197548, 0.231544, 0.306209, 0.354388, 0.49364", \ "0.249715, 0.286902, 0.358967, 0.408648, 0.550371", \ "0.349848, 0.385404, 0.458573, 0.506863, 0.651114", \ "0.743952, 0.778747, 0.850043, 0.897371, 1.04067", \ "1.3333, 1.36811, 1.4389, 1.48577, 1.62697"); } fall_transition(delay_template_5x5) { index_1 ("0.05, 0.1, 0.2, 0.6, 1.2"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0972, 0.0936, 0.102, 0.1134, 0.1296", \ "0.1506, 0.1512, 0.156, 0.1632, 0.1806", \ "0.2724, 0.2712, 0.2742, 0.2772, 0.2916", \ "0.7854, 0.7854, 0.7854, 0.786, 0.7896", \ "1.5582, 1.5588, 1.5582, 1.5588, 1.5594"); } } timing() { related_pin : "B"; timing_sense : positive_unate; cell_rise(delay_template_5x5) { index_1 ("0.05, 0.1, 0.2, 0.6, 1.2"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.165586, 0.166809, 0.166253, 0.157225, 0.104642", \ "0.211339, 0.215068, 0.214009, 0.20615, 0.157", \ "0.299964, 0.303444, 0.303219, 0.296412, 0.251118", \ "0.645329, 0.647501, 0.647076, 0.640889, 0.605902", \ "1.16218, 1.16501, 1.16328, 1.15657, 1.12223"); } rise_transition(delay_template_5x5) { index_1 ("0.05, 0.1, 0.2, 0.6, 1.2"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0954, 0.0978, 0.111, 0.1164, 0.1356", \ "0.1506, 0.1512, 0.162, 0.1692, 0.186", \ "0.2718, 0.2742, 0.279, 0.2844, 0.3054", \ "0.7842, 0.7848, 0.7848, 0.7866, 0.8022", \ "1.5564, 1.5564, 1.5564, 1.5564, 1.5618"); } cell_fall(delay_template_5x5) { index_1 ("0.05, 0.1, 0.2, 0.6, 1.2"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.21246, 0.254797, 0.338379, 0.39659, 0.572482", \ "0.267132, 0.307439, 0.39168, 0.450338, 0.629499", \ "0.366797, 0.406971, 0.48993, 0.548577, 0.728192", \ "0.760704, 0.799639, 0.88134, 0.937988, 1.11466", \ "1.35006, 1.38878, 1.47003, 1.52613, 1.70059"); } fall_transition(delay_template_5x5) { index_1 ("0.05, 0.1, 0.2, 0.6, 1.2"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1002, 0.0966, 0.105, 0.1134, 0.132", \ "0.1554, 0.1542, 0.1584, 0.1638, 0.1842", \ "0.2742, 0.2742, 0.276, 0.2778, 0.2922", \ "0.7854, 0.7854, 0.7848, 0.7854, 0.7884", \ "1.5588, 1.5588, 1.5588, 1.5588, 1.5594"); } } internal_power() { related_pin : "A"; rise_power(energy_template_5x5) { index_1 ("0.05, 0.1, 0.2, 0.6, 1.2"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.550436, 0.664023, 0.96665, 1.23134, 2.15451", \ "0.544768, 0.651863, 0.933768, 1.18069, 2.06101", \ "0.550936, 0.64341, 0.913994, 1.14231, 1.97533", \ "0.547375, 0.639463, 0.888303, 1.10629, 1.87794", \ "0.550038, 0.638493, 0.883497, 1.09518, 1.84421"); } fall_power(energy_template_5x5) { index_1 ("0.05, 0.1, 0.2, 0.6, 1.2"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.990991, 1.08013, 1.39516, 1.66179, 2.58247", \ "0.992902, 1.08392, 1.36624, 1.61767, 2.49374", \ "1.00434, 1.07979, 1.35237, 1.5849, 2.41827", \ "1.00127, 1.08168, 1.33875, 1.55753, 2.33651", \ "1.00395, 1.08255, 1.3361, 1.55098, 2.3112"); } } internal_power() { related_pin : "B"; rise_power(energy_template_5x5) { index_1 ("0.05, 0.1, 0.2, 0.6, 1.2"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.521776, 0.637392, 0.990058, 1.28424, 2.3133", \ "0.50981, 0.630318, 0.952322, 1.22979, 2.21669", \ "0.519249, 0.637226, 0.92901, 1.19034, 2.12887", \ "0.530496, 0.631393, 0.905822, 1.15057, 2.02578", \ "0.534133, 0.623731, 0.899503, 1.13791, 1.98904"); } fall_power(energy_template_5x5) { index_1 ("0.05, 0.1, 0.2, 0.6, 1.2"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "1.1656, 1.28796, 1.6285, 1.92597, 2.9544", \ "1.1669, 1.27683, 1.59573, 1.8772, 2.86498", \ "1.16814, 1.27073, 1.56835, 1.83873, 2.77892", \ "1.17044, 1.26729, 1.55186, 1.80184, 2.67927", \ "1.1715, 1.26705, 1.54774, 1.79243, 2.64577"); } } } } /* ---------------- * * Design : AOI21X1 * * ---------------- */ cell (AOI21X1) { area : 288; cell_leakage_power : 0.0702509; pin(A) { direction : input; capacitance : 0.0323272; rise_capacitance : 0.0320917; fall_capacitance : 0.0323272; } pin(B) { direction : input; capacitance : 0.032547; rise_capacitance : 0.032239; fall_capacitance : 0.032547; } pin(C) { direction : input; capacitance : 0.0276516; rise_capacitance : 0.0276516; fall_capacitance : 0.0276422; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.375698; function : "(!((A B)+C))"; timing() { related_pin : "A"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.110736, 0.116546, 0.125238, 0.128187, 0.126309", \ "0.149473, 0.155697, 0.169115, 0.176143, 0.184264", \ "0.225055, 0.228474, 0.24576, 0.258762, 0.284295", \ "0.519861, 0.522087, 0.531809, 0.545778, 0.599723", \ "0.965237, 0.961468, 0.965839, 0.974167, 1.02087"); } fall_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.114, 0.1368, 0.1998, 0.2538, 0.4158", \ "0.168, 0.18, 0.2376, 0.2868, 0.4566", \ "0.2718, 0.276, 0.315, 0.36, 0.5298", \ "0.6918, 0.6918, 0.6984, 0.7134, 0.825", \ "1.323, 1.323, 1.323, 1.326, 1.3668"); } cell_rise(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.119567, 0.134511, 0.170117, 0.194609, 0.264796", \ "0.157895, 0.176979, 0.215572, 0.243856, 0.32476", \ "0.242825, 0.254443, 0.29654, 0.329958, 0.427664", \ "0.562378, 0.573998, 0.60582, 0.637254, 0.757475", \ "1.0436, 1.05541, 1.08013, 1.10453, 1.20926"); } rise_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1158, 0.1368, 0.2004, 0.2508, 0.411", \ "0.177, 0.1884, 0.2406, 0.2898, 0.4572", \ "0.2994, 0.3024, 0.3366, 0.3774, 0.5406", \ "0.789, 0.789, 0.7932, 0.8052, 0.9024", \ "1.5234, 1.5234, 1.5234, 1.524, 1.5588"); } } timing() { related_pin : "B"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.110229, 0.133439, 0.167846, 0.187453, 0.239349", \ "0.148929, 0.171947, 0.215725, 0.240118, 0.305039", \ "0.222966, 0.245313, 0.297516, 0.329599, 0.413836", \ "0.517156, 0.537962, 0.584459, 0.624459, 0.755747", \ "0.960257, 0.977772, 1.01904, 1.05393, 1.18664"); } fall_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.114, 0.1386, 0.2022, 0.2472, 0.396", \ "0.1674, 0.1806, 0.2436, 0.2904, 0.447", \ "0.2718, 0.2742, 0.3216, 0.369, 0.5292", \ "0.6918, 0.6918, 0.6978, 0.7188, 0.8472", \ "1.323, 1.323, 1.3224, 1.3236, 1.383"); } cell_rise(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.105819, 0.119117, 0.141437, 0.154159, 0.184093", \ "0.14773, 0.163023, 0.192298, 0.210563, 0.254656", \ "0.232402, 0.243627, 0.279571, 0.304886, 0.370791", \ "0.55558, 0.564857, 0.594142, 0.622588, 0.725951", \ "1.03727, 1.04696, 1.07031, 1.09314, 1.18884"); } rise_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0948, 0.1146, 0.1752, 0.2208, 0.3522", \ "0.1554, 0.1662, 0.2178, 0.2622, 0.4074", \ "0.2766, 0.279, 0.3132, 0.354, 0.5022", \ "0.7656, 0.765, 0.7692, 0.783, 0.8766", \ "1.5, 1.5, 1.5, 1.5006, 1.5366"); } } timing() { related_pin : "C"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.120576, 0.147646, 0.196084, 0.226332, 0.307893", \ "0.180713, 0.204616, 0.264302, 0.300184, 0.401908", \ "0.294861, 0.316986, 0.378034, 0.424821, 0.552437", \ "0.743315, 0.762377, 0.812552, 0.856597, 1.01961", \ "1.40713, 1.42661, 1.4727, 1.51154, 1.6565"); } fall_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1074, 0.12, 0.1713, 0.2052, 0.3102", \ "0.1767, 0.1824, 0.228, 0.2649, 0.3819", \ "0.3216, 0.3216, 0.3447, 0.3792, 0.5052", \ "0.8997, 0.8997, 0.8997, 0.9039, 0.9753", \ "1.7679, 1.7679, 1.7682, 1.7679, 1.7787"); } cell_rise(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.085249, 0.108994, 0.132902, 0.14321, 0.158167", \ "0.121403, 0.150257, 0.188769, 0.20723, 0.243054", \ "0.192009, 0.221072, 0.277881, 0.30843, 0.376533", \ "0.474451, 0.502132, 0.56228, 0.610196, 0.751808", \ "0.898213, 0.924335, 0.981235, 1.02633, 1.18532"); } rise_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0933, 0.1224, 0.1746, 0.2073, 0.3105", \ "0.1452, 0.1647, 0.2211, 0.2598, 0.3798", \ "0.2517, 0.2592, 0.3063, 0.3498, 0.4848", \ "0.6816, 0.6819, 0.6888, 0.7119, 0.8361", \ "1.3266, 1.3266, 1.3266, 1.3284, 1.389"); } } internal_power() { related_pin : "A"; fall_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.29687, 0.222655, 0.122605, 0.436342, 1.57895", \ "0.293242, 0.237274, 0.057812, 0.345188, 1.43489", \ "0.289841, 0.252855, 0.019205, 0.224042, 1.21193", \ "0.28506, 0.269709, 0.138659, 0.015985, 0.728423", \ "0.284319, 0.276829, 0.195883, 0.093314, 0.419142"); } rise_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "1.27972, 1.34109, 1.71482, 2.04087, 3.21173", \ "1.28883, 1.34929, 1.65335, 1.95687, 3.08518", \ "1.30955, 1.33248, 1.58042, 1.83715, 2.88206", \ "1.30666, 1.32739, 1.45959, 1.62967, 2.41518", \ "1.30968, 1.31218, 1.40205, 1.5165, 2.09617"); } } internal_power() { related_pin : "B"; fall_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.290731, 0.222857, 0.072844, 0.340664, 1.30932", \ "0.289007, 0.238743, 0.01643, 0.259548, 1.18173", \ "0.289195, 0.250037, 0.053785, 0.151325, 0.984675", \ "0.285856, 0.270345, 0.161142, 0.032868, 0.561902", \ "0.283066, 0.275765, 0.211523, 0.127681, 0.294485"); } rise_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "1.10171, 1.17164, 1.48495, 1.76347, 2.76103", \ "1.12798, 1.17505, 1.43601, 1.69444, 2.65289", \ "1.1618, 1.1713, 1.38233, 1.59926, 2.48281", \ "1.18045, 1.18411, 1.29476, 1.44191, 2.11398", \ "1.18614, 1.17527, 1.25437, 1.35498, 1.8622"); } } internal_power() { related_pin : "C"; fall_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.297115, 0.247614, 0.052811, 0.12478, 0.764071", \ "0.270615, 0.247149, 0.088965, 0.069217, 0.668455", \ "0.240987, 0.239092, 0.12664, 0.009379, 0.53465", \ "0.214124, 0.217256, 0.167843, 0.094038, 0.273445", \ "0.205678, 0.207736, 0.18114, 0.135431, 0.117978"); } rise_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.728773, 0.784537, 1.00022, 1.17587, 1.80773", \ "0.732113, 0.776167, 0.957843, 1.11957, 1.71993", \ "0.738964, 0.767825, 0.909699, 1.04731, 1.5904", \ "0.74827, 0.760769, 0.83915, 0.927185, 1.32418", \ "0.751637, 0.757303, 0.8061, 0.864341, 1.15225"); } } } } /* ---------------- * * Design : AOI22X1 * * ---------------- */ cell (AOI22X1) { area : 360; cell_leakage_power : 0.0919588; pin(A) { direction : input; capacitance : 0.0323074; rise_capacitance : 0.0320974; fall_capacitance : 0.0323074; } pin(B) { direction : input; capacitance : 0.0325293; rise_capacitance : 0.0322408; fall_capacitance : 0.0325293; } pin(C) { direction : input; capacitance : 0.0330061; rise_capacitance : 0.0330061; fall_capacitance : 0.0329569; } pin(D) { direction : input; capacitance : 0.0331821; rise_capacitance : 0.0331737; fall_capacitance : 0.0331821; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.478959; function : "(!((A B)+(C D)))"; timing() { related_pin : "A"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.133942, 0.139404, 0.153411, 0.160854, 0.171855", \ "0.173177, 0.177028, 0.194646, 0.205409, 0.225845", \ "0.248094, 0.250987, 0.269538, 0.284487, 0.320305", \ "0.545638, 0.545061, 0.555391, 0.569777, 0.62771", \ "0.988558, 0.985025, 0.989934, 0.998578, 1.0475"); } fall_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1419, 0.1575, 0.222, 0.2742, 0.4305", \ "0.1935, 0.2037, 0.2577, 0.3087, 0.4728", \ "0.2979, 0.3015, 0.3369, 0.381, 0.5454", \ "0.7188, 0.7188, 0.7242, 0.7371, 0.8472", \ "1.3497, 1.3497, 1.3497, 1.3521, 1.3902"); } cell_rise(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.131377, 0.149582, 0.187374, 0.213689, 0.28829", \ "0.166138, 0.184826, 0.227862, 0.257652, 0.3416", \ "0.237079, 0.254949, 0.301357, 0.3355, 0.435552", \ "0.51926, 0.535104, 0.575388, 0.611278, 0.738875", \ "0.941452, 0.957737, 0.991798, 1.02232, 1.14372"); } rise_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1332, 0.15, 0.2121, 0.2622, 0.4269", \ "0.1866, 0.1983, 0.2502, 0.2985, 0.4668", \ "0.2937, 0.2976, 0.333, 0.3747, 0.5385", \ "0.723, 0.723, 0.729, 0.7443, 0.8505", \ "1.3662, 1.3665, 1.3668, 1.3683, 1.4127"); } } timing() { related_pin : "B"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.133469, 0.156828, 0.198161, 0.223143, 0.287376", \ "0.172125, 0.194604, 0.242959, 0.271679, 0.346918", \ "0.246527, 0.267786, 0.32206, 0.35708, 0.450743", \ "0.540513, 0.561325, 0.60795, 0.648235, 0.784765", \ "0.983908, 1.00167, 1.04303, 1.07824, 1.21254"); } fall_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1416, 0.1599, 0.2241, 0.2745, 0.4179", \ "0.1929, 0.204, 0.2643, 0.3126, 0.4641", \ "0.2982, 0.2997, 0.3438, 0.3912, 0.5469", \ "0.7188, 0.7185, 0.723, 0.7425, 0.8694", \ "1.3497, 1.35, 1.3497, 1.3503, 1.4064"); } cell_rise(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.120762, 0.137158, 0.163494, 0.17898, 0.214673", \ "0.156844, 0.173968, 0.208266, 0.228831, 0.278458", \ "0.228853, 0.24494, 0.286421, 0.314022, 0.384289", \ "0.511562, 0.52698, 0.564964, 0.598494, 0.710528", \ "0.934743, 0.950317, 0.983248, 1.01224, 1.12575"); } rise_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1155, 0.1323, 0.1893, 0.2343, 0.3702", \ "0.168, 0.1767, 0.2307, 0.2751, 0.4233", \ "0.2739, 0.2772, 0.3141, 0.3546, 0.5043", \ "0.7023, 0.7026, 0.7089, 0.7248, 0.8289", \ "1.3461, 1.3461, 1.3461, 1.3482, 1.3938"); } } timing() { related_pin : "C"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.094805, 0.098112, 0.097165, 0.089902, 0.057001", \ "0.13492, 0.137899, 0.145042, 0.143383, 0.125334", \ "0.210258, 0.212772, 0.226472, 0.232624, 0.23676", \ "0.511062, 0.507938, 0.516994, 0.528639, 0.570254", \ "0.952153, 0.948322, 0.952303, 0.959873, 0.999257"); } fall_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0906, 0.111, 0.1695, 0.216, 0.3444", \ "0.1446, 0.1563, 0.2088, 0.2517, 0.3939", \ "0.2472, 0.2517, 0.2895, 0.3291, 0.477", \ "0.6678, 0.6675, 0.6738, 0.6885, 0.792", \ "1.2984, 1.299, 1.2984, 1.3014, 1.3407"); } cell_rise(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.107957, 0.140423, 0.199308, 0.238722, 0.35358", \ "0.143267, 0.176041, 0.242979, 0.286583, 0.414347", \ "0.213791, 0.245251, 0.318747, 0.368548, 0.516322", \ "0.496468, 0.524697, 0.591383, 0.646603, 0.83256", \ "0.920304, 0.946905, 1.0077, 1.05753, 1.24003"); } rise_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1209, 0.1449, 0.2025, 0.2418, 0.372", \ "0.1734, 0.1869, 0.2421, 0.2844, 0.4233", \ "0.2811, 0.285, 0.3252, 0.3666, 0.5115", \ "0.711, 0.711, 0.7161, 0.7332, 0.8436", \ "1.3557, 1.356, 1.356, 1.3572, 1.4049"); } } timing() { related_pin : "D"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.093716, 0.114399, 0.134085, 0.142044, 0.155595", \ "0.133812, 0.155092, 0.187912, 0.202717, 0.234887", \ "0.209328, 0.22982, 0.277122, 0.301806, 0.360104", \ "0.506307, 0.523849, 0.56927, 0.607543, 0.72615", \ "0.947465, 0.964314, 1.00524, 1.03973, 1.16646"); } fall_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0933, 0.1161, 0.1734, 0.2118, 0.3303", \ "0.1437, 0.1569, 0.2151, 0.2568, 0.3897", \ "0.2487, 0.2508, 0.2991, 0.3429, 0.4824", \ "0.6675, 0.6678, 0.6738, 0.6948, 0.8205", \ "1.2984, 1.2984, 1.2984, 1.2996, 1.3593"); } cell_rise(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.097961, 0.126761, 0.171037, 0.199143, 0.273357", \ "0.133073, 0.165308, 0.220632, 0.255106, 0.346934", \ "0.206093, 0.234995, 0.303405, 0.346441, 0.464455", \ "0.489408, 0.516775, 0.581029, 0.634034, 0.806549", \ "0.913538, 0.939506, 0.999094, 1.04759, 1.22358"); } rise_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1029, 0.1239, 0.1773, 0.2124, 0.3261", \ "0.1554, 0.1668, 0.2241, 0.2631, 0.3879", \ "0.261, 0.2652, 0.3072, 0.3477, 0.4839", \ "0.6906, 0.6909, 0.696, 0.7146, 0.8268", \ "1.3356, 1.3356, 1.3356, 1.3365, 1.3872"); } } internal_power() { related_pin : "A"; fall_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.258876, 0.1976, 0.125317, 0.428745, 1.55188", \ "0.255714, 0.209038, 0.073819, 0.353847, 1.42816", \ "0.251722, 0.221317, 0.031873, 0.248835, 1.23083", \ "0.247485, 0.232519, 0.10103, 0.056029, 0.782186", \ "0.245874, 0.238796, 0.156228, 0.049934, 0.480762"); } rise_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "1.58073, 1.62417, 1.9712, 2.29074, 3.45755", \ "1.58493, 1.61459, 1.91329, 2.21156, 3.33688", \ "1.59216, 1.60095, 1.84515, 2.09928, 3.1391", \ "1.5888, 1.59712, 1.73371, 1.90247, 2.68532", \ "1.59198, 1.58715, 1.67944, 1.79298, 2.3722"); } } internal_power() { related_pin : "B"; fall_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.253975, 0.200975, 0.079448, 0.337626, 1.28592", \ "0.251568, 0.207984, 0.033417, 0.27057, 1.17638", \ "0.249888, 0.218555, 0.031128, 0.17622, 1.00281", \ "0.247012, 0.234655, 0.124052, 0.040025, 0.612091", \ "0.245084, 0.238562, 0.172384, 0.085585, 0.351591"); } rise_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "1.40296, 1.44811, 1.74186, 2.01351, 3.00692", \ "1.42043, 1.43279, 1.69857, 1.95043, 2.90417", \ "1.44146, 1.4387, 1.64776, 1.86283, 2.74109", \ "1.46267, 1.45205, 1.56942, 1.71448, 2.38354", \ "1.4611, 1.4512, 1.53174, 1.63181, 2.13746"); } } internal_power() { related_pin : "C"; fall_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.285626, 0.193461, 0.130731, 0.418857, 1.44825", \ "0.263278, 0.203088, 0.075179, 0.340098, 1.3221", \ "0.240518, 0.204635, 0.013109, 0.236969, 1.12894", \ "0.215155, 0.199002, 0.078185, 0.067182, 0.724109", \ "0.206241, 0.196789, 0.12078, 0.022451, 0.463224"); } rise_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "1.04933, 1.13985, 1.47009, 1.75007, 2.76679", \ "1.05149, 1.12147, 1.41263, 1.67105, 2.64813", \ "1.05918, 1.10576, 1.33964, 1.56505, 2.45844", \ "1.06998, 1.09125, 1.22203, 1.3702, 2.03437", \ "1.07354, 1.08347, 1.16503, 1.26326, 1.74818"); } } internal_power() { related_pin : "D"; fall_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.28082, 0.194848, 0.086609, 0.336541, 1.22985", \ "0.258331, 0.200666, 0.036043, 0.264216, 1.11227", \ "0.238623, 0.206684, 0.021122, 0.170671, 0.937248", \ "0.21439, 0.203397, 0.102253, 0.019017, 0.576123", \ "0.206348, 0.2001, 0.138064, 0.057957, 0.345998"); } rise_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.882481, 0.963731, 1.25453, 1.49962, 2.37203", \ "0.898584, 0.952551, 1.20575, 1.43514, 2.26902", \ "0.915432, 0.944591, 1.1488, 1.34606, 2.11565", \ "0.935943, 0.948848, 1.05968, 1.18999, 1.77331", \ "0.942835, 0.948406, 1.01792, 1.10544, 1.53781"); } } } } /* -------------- * * Design : BUFX2 * * -------------- */ cell (BUFX2) { cell_footprint : buf; area : 216; cell_leakage_power : 0.0809721; pin(A) { direction : input; capacitance : 0.0161375; rise_capacitance : 0.0160881; fall_capacitance : 0.0161375; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.924801; function : "A"; timing() { related_pin : "A"; timing_sense : positive_unate; cell_rise(delay_template_5x5) { index_1 ("0.05, 0.1, 0.2, 0.6, 1.2"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.190325, 0.216056, 0.26074, 0.287074, 0.351181", \ "0.234315, 0.260074, 0.307124, 0.333203, 0.39978", \ "0.3214, 0.34692, 0.393164, 0.419512, 0.487611", \ "0.665339, 0.691956, 0.735686, 0.761221, 0.828256", \ "1.18375, 1.20853, 1.25168, 1.27682, 1.34254"); } rise_transition(delay_template_5x5) { index_1 ("0.05, 0.1, 0.2, 0.6, 1.2"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.099, 0.0966, 0.1098, 0.114, 0.1314", \ "0.1518, 0.153, 0.1584, 0.1668, 0.18", \ "0.2742, 0.2742, 0.276, 0.2796, 0.291", \ "0.7854, 0.7854, 0.7848, 0.786, 0.7902", \ "1.5564, 1.5564, 1.5564, 1.557, 1.5576"); } cell_fall(delay_template_5x5) { index_1 ("0.05, 0.1, 0.2, 0.6, 1.2"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.184353, 0.217728, 0.270187, 0.303335, 0.38378", \ "0.235989, 0.268542, 0.322913, 0.356567, 0.440069", \ "0.336318, 0.368633, 0.422414, 0.454204, 0.539954", \ "0.730027, 0.761404, 0.81343, 0.844475, 0.929557", \ "1.31946, 1.35049, 1.40208, 1.43256, 1.51581"); } fall_transition(delay_template_5x5) { index_1 ("0.05, 0.1, 0.2, 0.6, 1.2"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0942, 0.0954, 0.1068, 0.111, 0.1314", \ "0.1506, 0.1518, 0.156, 0.1644, 0.183", \ "0.2706, 0.273, 0.276, 0.2778, 0.294", \ "0.7854, 0.7848, 0.7854, 0.786, 0.7902", \ "1.5588, 1.5588, 1.5582, 1.5588, 1.56"); } } internal_power() { related_pin : "A"; rise_power(energy_template_5x5) { index_1 ("0.05, 0.1, 0.2, 0.6, 1.2"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.551657, 0.63377, 0.87801, 1.08251, 1.8116", \ "0.546195, 0.61657, 0.834861, 1.02955, 1.71636", \ "0.554851, 0.606647, 0.809922, 0.985103, 1.62802", \ "0.554584, 0.601755, 0.784366, 0.946842, 1.52367", \ "0.548723, 0.600775, 0.778583, 0.934625, 1.48924"); } fall_power(energy_template_5x5) { index_1 ("0.05, 0.1, 0.2, 0.6, 1.2"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.869491, 0.960076, 1.20771, 1.41637, 2.15226", \ "0.880931, 0.952646, 1.17617, 1.37483, 2.06021", \ "0.879651, 0.957525, 1.15792, 1.33949, 1.97958", \ "0.889355, 0.956152, 1.1432, 1.30846, 1.89439", \ "0.892702, 0.956454, 1.14086, 1.30064, 1.86633"); } } } } /* -------------- * * Design : BUFX4 * * -------------- */ cell (BUFX4) { cell_footprint : buf; area : 288; cell_leakage_power : 0.112274; pin(A) { direction : input; capacitance : 0.0247079; rise_capacitance : 0.0246304; fall_capacitance : 0.0247079; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 1.84805; function : "A"; timing() { related_pin : "A"; timing_sense : positive_unate; cell_rise(delay_template_5x5) { index_1 ("0.1, 0.2, 0.4, 1.2, 2.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.206474, 0.232894, 0.278073, 0.305279, 0.367866", \ "0.253522, 0.279189, 0.32518, 0.352259, 0.417491", \ "0.340848, 0.365561, 0.412811, 0.43896, 0.504769", \ "0.686975, 0.710488, 0.754864, 0.77997, 0.844549", \ "1.20353, 1.22695, 1.27097, 1.29523, 1.35804"); } rise_transition(delay_template_5x5) { index_1 ("0.1, 0.2, 0.4, 1.2, 2.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1044, 0.1032, 0.108, 0.117, 0.1386", \ "0.156, 0.1572, 0.1632, 0.1698, 0.186", \ "0.2766, 0.2772, 0.2808, 0.2826, 0.297", \ "0.786, 0.786, 0.786, 0.7872, 0.7908", \ "1.5576, 1.5576, 1.5582, 1.5576, 1.5588"); } cell_fall(delay_template_5x5) { index_1 ("0.1, 0.2, 0.4, 1.2, 2.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.204188, 0.239046, 0.302821, 0.341028, 0.441807", \ "0.25833, 0.293505, 0.357014, 0.395703, 0.498973", \ "0.359092, 0.392998, 0.45567, 0.494151, 0.599202", \ "0.752802, 0.785757, 0.846603, 0.883499, 0.986702", \ "1.34241, 1.37495, 1.43512, 1.4713, 1.57211"); } fall_transition(delay_template_5x5) { index_1 ("0.1, 0.2, 0.4, 1.2, 2.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.102, 0.0984, 0.1068, 0.1188, 0.1374", \ "0.1542, 0.1548, 0.1638, 0.168, 0.1884", \ "0.2754, 0.2754, 0.2778, 0.282, 0.297", \ "0.7866, 0.786, 0.7866, 0.7866, 0.7914", \ "1.56, 1.56, 1.56, 1.56, 1.5606"); } } internal_power() { related_pin : "A"; rise_power(energy_template_5x5) { index_1 ("0.1, 0.2, 0.4, 1.2, 2.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "1.21884, 1.36285, 1.79645, 2.18187, 3.50201", \ "1.20907, 1.30938, 1.7077, 2.05528, 3.28369", \ "1.18153, 1.27573, 1.63319, 1.94608, 3.07973", \ "1.18518, 1.26362, 1.56877, 1.83476, 2.83405", \ "1.18331, 1.26107, 1.5508, 1.803, 2.74614"); } fall_power(energy_template_5x5) { index_1 ("0.1, 0.2, 0.4, 1.2, 2.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "1.63512, 1.78318, 2.24202, 2.61251, 3.93548", \ "1.62542, 1.76007, 2.15492, 2.49742, 3.72607", \ "1.63918, 1.74332, 2.10025, 2.4086, 3.53675", \ "1.63918, 1.73662, 2.05373, 2.32859, 3.32485", \ "1.64289, 1.73637, 2.04173, 2.30518, 3.25377"); } } } } /* ---------------- * * Design : CLKBUF1 * * ---------------- */ cell (CLKBUF1) { cell_footprint : buf; area : 648; cell_leakage_power : 0.357836; pin(A) { direction : input; capacitance : 0.0667175; rise_capacitance : 0.0664987; fall_capacitance : 0.0667175; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 1.85327; function : "A"; timing() { related_pin : "A"; timing_sense : positive_unate; cell_rise(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.254868, 0.280123, 0.302911, 0.327524, 0.336479, 0.352921", \ "0.429701, 0.455468, 0.476542, 0.501112, 0.513182, 0.526916", \ "0.730952, 0.756883, 0.782016, 0.806295, 0.814636, 0.827973", \ "1.50606, 1.5319, 1.55736, 1.58178, 1.59008, 1.6071", \ "1.93657, 1.96274, 1.98784, 2.01241, 2.02057, 2.03794", \ "2.36746, 2.39346, 2.41855, 2.44323, 2.45136, 2.46879"); } rise_transition(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.0858, 0.0828, 0.0876, 0.0882, 0.0828, 0.0828", \ "0.3318, 0.333, 0.333, 0.3336, 0.3324, 0.3324", \ "0.7824, 0.7824, 0.7824, 0.7824, 0.7824, 0.7824", \ "1.9404, 1.941, 1.9398, 1.9404, 1.9404, 1.941", \ "2.5836, 2.5842, 2.5842, 2.5836, 2.5836, 2.5836", \ "3.2274, 3.2274, 3.2274, 3.2274, 3.2274, 3.2274"); } cell_fall(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.262935, 0.306442, 0.347206, 0.409454, 0.44062, 0.498908", \ "0.462532, 0.506176, 0.552227, 0.613017, 0.644448, 0.704269", \ "0.806485, 0.852272, 0.896178, 0.957099, 0.98849, 1.0483", \ "1.6903, 1.73612, 1.77996, 1.84122, 1.8724, 1.93198", \ "2.18104, 2.22706, 2.27074, 2.33213, 2.36351, 2.4228", \ "2.67207, 2.71797, 2.76152, 2.82272, 2.85443, 2.9139"); } fall_transition(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.0828, 0.0846, 0.0834, 0.0858, 0.0852, 0.0852", \ "0.333, 0.333, 0.333, 0.3324, 0.3324, 0.333", \ "0.783, 0.783, 0.783, 0.783, 0.783, 0.7824", \ "1.9434, 1.9434, 1.9434, 1.9434, 1.9434, 1.9434", \ "2.5884, 2.5884, 2.5884, 2.5884, 2.5884, 2.5884", \ "3.2328, 3.2334, 3.2334, 3.2334, 3.2328, 3.2334"); } } internal_power() { related_pin : "A"; rise_power(energy_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "3.10502, 3.73111, 4.81821, 6.87917, 8.40509, 11.5137", \ "3.2163, 3.76455, 4.88668, 6.94699, 8.47503, 11.5028", \ "3.22334, 3.77813, 4.91662, 6.97688, 8.48353, 11.5059", \ "3.22652, 3.78517, 4.92312, 6.98404, 8.48745, 11.4783", \ "3.22731, 3.78599, 4.92423, 6.98506, 8.48915, 11.4797", \ "3.22749, 3.78806, 4.9249, 6.98583, 8.4887, 11.4805"); } fall_power(energy_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "4.80123, 5.47708, 6.61471, 8.72719, 10.1404, 13.1527", \ "4.8404, 5.54398, 6.7013, 8.79741, 10.2485, 13.2711", \ "4.85166, 5.54709, 6.71028, 8.81233, 10.2602, 13.2848", \ "4.85747, 5.55556, 6.715, 8.81963, 10.2664, 13.2902", \ "4.85844, 5.5575, 6.71562, 8.82111, 10.2668, 13.291", \ "4.85977, 5.55844, 6.71567, 8.82229, 10.2679, 13.2918"); } } } } /* ---------------- * * Design : CLKBUF2 * * ---------------- */ cell (CLKBUF2) { cell_footprint : buf; area : 936; cell_leakage_power : 0.558643; pin(A) { direction : input; capacitance : 0.0667747; rise_capacitance : 0.0664973; fall_capacitance : 0.0667747; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 1.85153; function : "A"; timing() { related_pin : "A"; timing_sense : positive_unate; cell_rise(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.372019, 0.398903, 0.418122, 0.443436, 0.455353, 0.470131", \ "0.546107, 0.571798, 0.594512, 0.618848, 0.628752, 0.644543", \ "0.847391, 0.87535, 0.895511, 0.920304, 0.92994, 0.945991", \ "1.62251, 1.65074, 1.67066, 1.69548, 1.70479, 1.72126", \ "2.05322, 2.08141, 2.10108, 2.12589, 2.13555, 2.15194", \ "2.48405, 2.51224, 2.53187, 2.55669, 2.5661, 2.58277"); } rise_transition(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.084, 0.087, 0.0828, 0.0852, 0.0876, 0.0852", \ "0.333, 0.333, 0.333, 0.333, 0.3324, 0.333", \ "0.7818, 0.7818, 0.7824, 0.7824, 0.7824, 0.7818", \ "1.941, 1.941, 1.9404, 1.9404, 1.941, 1.941", \ "2.5836, 2.5836, 2.5836, 2.5836, 2.5836, 2.5836", \ "3.2274, 3.2268, 3.2274, 3.2274, 3.2274, 3.2268"); } cell_fall(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.381695, 0.424124, 0.464899, 0.525359, 0.557132, 0.617115", \ "0.58061, 0.623064, 0.667135, 0.728582, 0.75901, 0.818559", \ "0.925943, 0.968512, 1.01115, 1.07255, 1.10294, 1.16247", \ "1.81004, 1.85261, 1.89503, 1.95622, 1.98677, 2.04612", \ "2.30097, 2.34339, 2.38614, 2.44738, 2.47775, 2.53735", \ "2.79146, 2.8341, 2.8768, 2.93843, 2.96869, 3.02789"); } fall_transition(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.081, 0.0834, 0.0846, 0.0834, 0.0852, 0.0846", \ "0.333, 0.333, 0.333, 0.3318, 0.3336, 0.333", \ "0.783, 0.783, 0.783, 0.783, 0.783, 0.783", \ "1.9434, 1.9434, 1.9434, 1.9428, 1.9434, 1.9434", \ "2.589, 2.589, 2.589, 2.589, 2.5884, 2.5884", \ "3.2334, 3.2334, 3.2334, 3.2334, 3.2334, 3.2334"); } } internal_power() { related_pin : "A"; rise_power(energy_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "5.52555, 6.08091, 7.19304, 9.25987, 10.7011, 13.818", \ "5.56934, 6.14778, 7.31021, 9.3843, 10.8323, 13.8603", \ "5.58129, 6.16543, 7.31153, 9.38554, 10.8395, 13.8751", \ "5.58765, 6.17374, 7.3129, 9.38729, 10.8426, 13.8821", \ "5.58912, 6.1762, 7.31315, 9.38786, 10.8445, 13.8833", \ "5.59118, 6.17613, 7.31336, 9.3884, 10.8441, 13.8854"); } fall_power(energy_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "7.1577, 7.87162, 8.97121, 11.1352, 12.5324, 15.5151", \ "7.23306, 7.95283, 9.0226, 11.1843, 12.6197, 15.6133", \ "7.2375, 7.94903, 9.0341, 11.1968, 12.6313, 15.6246", \ "7.24398, 7.95517, 9.04048, 11.2027, 12.6375, 15.6294", \ "7.24468, 7.95589, 9.04172, 11.2033, 12.6386, 15.6305", \ "7.24619, 7.9574, 9.04256, 11.2056, 12.6398, 15.6312"); } } } } /* ---------------- * * Design : CLKBUF3 * * ---------------- */ cell (CLKBUF3) { cell_footprint : buf; area : 1224; cell_leakage_power : 0.759446; pin(A) { direction : input; capacitance : 0.0668053; rise_capacitance : 0.0665051; fall_capacitance : 0.0668053; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 1.85038; function : "A"; timing() { related_pin : "A"; timing_sense : positive_unate; cell_rise(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.490149, 0.519458, 0.53729, 0.562904, 0.574298, 0.588053", \ "0.664121, 0.692798, 0.710479, 0.735212, 0.746007, 0.763925", \ "0.968826, 0.999965, 1.01188, 1.03665, 1.04685, 1.06528", \ "1.74431, 1.77537, 1.78713, 1.81181, 1.8221, 1.84064", \ "2.1749, 2.2059, 2.21779, 2.24212, 2.25235, 2.2711", \ "2.60541, 2.63651, 2.64862, 2.6728, 2.68315, 2.7019"); } rise_transition(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.0852, 0.0828, 0.0822, 0.0846, 0.0846, 0.0852", \ "0.3324, 0.333, 0.333, 0.333, 0.3324, 0.3324", \ "0.7824, 0.7824, 0.7818, 0.7824, 0.7818, 0.7824", \ "1.9404, 1.9398, 1.941, 1.9404, 1.9404, 1.9404", \ "2.5836, 2.5842, 2.5836, 2.5836, 2.5836, 2.5836", \ "3.2274, 3.2274, 3.2268, 3.2274, 3.2274, 3.2274"); } cell_fall(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.499249, 0.541933, 0.582432, 0.643913, 0.67457, 0.73444", \ "0.700886, 0.743824, 0.78728, 0.845529, 0.874714, 0.937293", \ "1.04482, 1.08786, 1.13109, 1.18945, 1.2188, 1.28107", \ "1.92855, 1.97153, 2.01488, 2.07315, 2.10271, 2.16466", \ "2.41976, 2.46255, 2.50594, 2.56438, 2.59371, 2.65591", \ "2.91039, 2.95338, 2.99681, 3.055, 3.08438, 3.1465"); } fall_transition(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.0846, 0.0852, 0.0846, 0.0846, 0.0828, 0.0852", \ "0.333, 0.3336, 0.333, 0.333, 0.3318, 0.333", \ "0.783, 0.783, 0.7824, 0.783, 0.783, 0.7824", \ "1.9434, 1.9434, 1.9434, 1.9434, 1.9434, 1.9434", \ "2.5884, 2.5884, 2.5884, 2.5884, 2.589, 2.5884", \ "3.2328, 3.2328, 3.2328, 3.2328, 3.2334, 3.2328"); } } internal_power() { related_pin : "A"; rise_power(energy_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "7.88836, 8.53591, 9.59582, 11.6228, 13.1598, 16.1504", \ "7.92389, 8.58368, 9.64339, 11.7337, 13.2038, 16.2678", \ "7.91904, 8.58243, 9.65661, 11.7374, 13.2073, 16.2716", \ "7.92603, 8.58816, 9.663, 11.7389, 13.2087, 16.2727", \ "7.9263, 8.58964, 9.66519, 11.7399, 13.2115, 16.2721", \ "7.92781, 8.58981, 9.66448, 11.7421, 13.2137, 16.2739"); } fall_power(energy_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "9.5159, 10.2284, 11.3367, 13.4659, 14.9356, 17.8706", \ "9.60708, 10.3125, 11.4202, 13.5623, 14.9847, 17.98", \ "9.61843, 10.3247, 11.4288, 13.5736, 14.9988, 17.9881", \ "9.62454, 10.3325, 11.4336, 13.5796, 15.0149, 17.9917", \ "9.62573, 10.3332, 11.4347, 13.581, 15.0161, 17.9916", \ "9.62735, 10.3357, 11.4349, 13.5806, 15.0159, 17.9951"); } } } } /* ----------------- * * Design : DFFNEGX1 * * ----------------- */ cell (DFFNEGX1) { area : 864; cell_leakage_power : 0.247166; ff (DS0000,P0002) { next_state : "D"; clocked_on : "(!CLK)"; } pin(CLK) { direction : input; capacitance : 0.0533315; rise_capacitance : 0.0528376; fall_capacitance : 0.0533315; clock : true; internal_power() { rise_power(passive_energy_template_6x1) { index_1 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ("0.43048, 0.604166, 0.986856, 1.90386, 2.59977, 4.10376"); } fall_power(passive_energy_template_6x1) { index_1 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ("1.22761, 1.56996, 2.08673, 3.00379, 3.65007, 4.99153"); } } min_pulse_width_high : 0.175165; min_pulse_width_low : 0.20336; } pin(D) { direction : input; capacitance : 0.015721; rise_capacitance : 0.0156555; fall_capacitance : 0.015721; internal_power() { rise_power(passive_energy_template_5x1) { index_1 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ("0.443641, 0.50145, 0.664591, 0.837859, 1.41454"); } fall_power(passive_energy_template_5x1) { index_1 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ("1.40409, 1.44941, 1.62063, 1.78882, 2.38589"); } } timing() { related_pin : "CLK"; timing_type : hold_falling; rise_constraint(hold_template_3x5) { index_1 ("0.06, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "-0.09375, -0.0875, -0.16875, -0.1125, -0.175", \ "-0.2, -0.19375, -0.18125, -0.21875, -0.28125", \ "-0.2625, -0.25625, -0.24375, -0.28125, -0.34375"); } fall_constraint(hold_template_3x5) { index_1 ("0.06, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "-0.09375, -0.0875, -0.16875, -0.20625, -0.26875", \ "-0.0125, -0.1, -0.0875, -0.125, -0.1875", \ "-0.075, -0.06875, -0.05625, -0.09375, -0.15625"); } } timing() { related_pin : "CLK"; timing_type : setup_falling; rise_constraint(setup_template_3x5) { index_1 ("0.06, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.28125, 0.36875, 0.35625, 0.39375, 0.45625", \ "0.29375, 0.38125, 0.36875, 0.40625, 0.46875", \ "0.45, 0.5375, 0.43125, 0.46875, 0.53125"); } fall_constraint(setup_template_3x5) { index_1 ("0.06, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.375, 0.36875, 0.35625, 0.39375, 0.55", \ "0.3875, 0.38125, 0.36875, 0.40625, 0.5625", \ "0.35625, 0.35, 0.43125, 0.46875, 0.53125"); } } } pin(Q) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.897488; function : "DS0000"; timing() { related_pin : "CLK"; timing_sense : non_unate; timing_type : falling_edge; cell_rise(delay_template_5x6) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.265606, 0.304731, 0.352577, 0.40608, 0.437106, 0.48837", \ "0.295763, 0.335311, 0.380186, 0.435702, 0.467178, 0.518194", \ "0.346039, 0.386532, 0.430955, 0.4859, 0.51727, 0.56866", \ "0.52807, 0.568106, 0.611551, 0.66646, 0.69805, 0.749601", \ "0.786911, 0.827389, 0.870608, 0.92511, 0.956446, 1.00945"); } rise_transition(delay_template_5x6) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.1044, 0.1056, 0.0984, 0.1002, 0.0984, 0.102", \ "0.1332, 0.132, 0.1254, 0.1272, 0.1308, 0.1314", \ "0.1884, 0.1872, 0.186, 0.1848, 0.1848, 0.1872", \ "0.4284, 0.4278, 0.4272, 0.4266, 0.4272, 0.4272", \ "0.8058, 0.8058, 0.8058, 0.8052, 0.8052, 0.8052"); } cell_fall(delay_template_5x6) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.235277, 0.283427, 0.340808, 0.425355, 0.477691, 0.564328", \ "0.270359, 0.316342, 0.373862, 0.459096, 0.512145, 0.599663", \ "0.330298, 0.375374, 0.433589, 0.518356, 0.571781, 0.662747", \ "0.536426, 0.580473, 0.637617, 0.722938, 0.777084, 0.871917", \ "0.831293, 0.874954, 0.930885, 1.01519, 1.06951, 1.16509"); } fall_transition(delay_template_5x6) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.1044, 0.108, 0.1176, 0.1302, 0.1458, 0.1662", \ "0.1332, 0.132, 0.1422, 0.162, 0.1734, 0.1938", \ "0.1908, 0.1914, 0.198, 0.2124, 0.2262, 0.2454", \ "0.4272, 0.4266, 0.4302, 0.4404, 0.4464, 0.4644", \ "0.8052, 0.8052, 0.8058, 0.8106, 0.8142, 0.8262"); } } internal_power() { related_pin : "CLK"; rise_power(energy_template_5x6) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "2.25786, 2.61013, 3.12931, 4.07246, 4.75188, 6.11166", \ "2.19775, 2.5463, 3.05916, 4.01875, 4.69684, 6.05818", \ "2.12673, 2.4957, 3.01207, 3.96698, 4.63384, 6.00788", \ "2.06455, 2.43306, 2.95708, 3.90463, 4.58082, 5.93222", \ "2.0415, 2.41186, 2.93678, 3.88355, 4.55874, 5.91238"); } fall_power(energy_template_5x6) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "2.18124, 2.60271, 3.34009, 4.72039, 5.68145, 7.55723", \ "2.12656, 2.54763, 3.26945, 4.61282, 5.57744, 7.45269", \ "2.08877, 2.49861, 3.19695, 4.49854, 5.45425, 7.31935", \ "2.05808, 2.45292, 3.11699, 4.35281, 5.26033, 7.09736", \ "2.04235, 2.4338, 3.08269, 4.28931, 5.17274, 6.96379"); } } } } /* ----------------- * * Design : DFFPOSX1 * * ----------------- */ cell (DFFPOSX1) { area : 864; cell_leakage_power : 0.243265; ff (DS0000,P0002) { next_state : "D"; clocked_on : "CLK"; } pin(CLK) { direction : input; capacitance : 0.049929; rise_capacitance : 0.049929; fall_capacitance : 0.0499011; clock : true; internal_power() { rise_power(passive_energy_template_6x1) { index_1 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ("0.183508, 0.139904, 0.615529, 1.5152, 2.17053, 3.47363"); } fall_power(passive_energy_template_6x1) { index_1 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ("1.53983, 1.93563, 2.53013, 3.60642, 4.36464, 5.88175"); } } min_pulse_width_high : 0.203847; min_pulse_width_low : 0.179122; } pin(D) { direction : input; capacitance : 0.0156852; rise_capacitance : 0.015643; fall_capacitance : 0.0156852; internal_power() { rise_power(passive_energy_template_5x1) { index_1 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ("0.556912, 0.602656, 0.78662, 0.940539, 1.52959"); } fall_power(passive_energy_template_5x1) { index_1 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ("1.27049, 1.31497, 1.49231, 1.66671, 2.27263"); } } timing() { related_pin : "CLK"; timing_type : hold_rising; rise_constraint(hold_template_3x5) { index_1 ("0.06, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "-0.09375, -0.0875, -0.075, -0.1125, -0.175", \ "-0.10625, -0.1, -0.0875, -0.125, -0.09375", \ "-0.075, -0.06875, -0.15, -0.09375, -0.0625"); } fall_constraint(hold_template_3x5) { index_1 ("0.06, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "-0.09375, -0.0875, -0.16875, -0.20625, -0.26875", \ "-0.2, -0.19375, -0.275, -0.3125, -0.375", \ "-0.2625, -0.25625, -0.3375, -0.375, -0.4375"); } } timing() { related_pin : "CLK"; timing_type : setup_rising; rise_constraint(setup_template_3x5) { index_1 ("0.06, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.28125, 0.36875, 0.35625, 0.39375, 0.3625", \ "0.3875, 0.38125, 0.36875, 0.40625, 0.46875", \ "0.45, 0.5375, 0.525, 0.5625, 0.625"); } fall_constraint(setup_template_3x5) { index_1 ("0.06, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.28125, 0.36875, 0.35625, 0.39375, 0.45625", \ "0.29375, 0.38125, 5.9, 0.40625, 0.46875", \ "0.45, 0.44375, 0.43125, 0.46875, 5.5"); } } } pin(Q) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.896771; function : "DS0000"; timing() { related_pin : "CLK"; timing_sense : non_unate; timing_type : rising_edge; cell_rise(delay_template_5x6) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.210303, 0.241522, 0.261631, 0.268296, 0.258043, 0.216218", \ "0.240095, 0.270575, 0.291189, 0.298091, 0.289631, 0.249579", \ "0.291978, 0.322347, 0.343279, 0.350262, 0.34206, 0.304495", \ "0.474691, 0.503172, 0.524078, 0.531806, 0.523264, 0.487319", \ "0.733757, 0.761487, 0.78242, 0.789389, 0.781123, 0.748001"); } rise_transition(delay_template_5x6) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.1044, 0.1032, 0.1164, 0.1338, 0.1416, 0.1614", \ "0.1308, 0.135, 0.1416, 0.159, 0.1692, 0.1896", \ "0.1848, 0.1884, 0.1962, 0.2112, 0.2202, 0.2388", \ "0.4278, 0.4284, 0.432, 0.4404, 0.4476, 0.4632", \ "0.8058, 0.8052, 0.8064, 0.8124, 0.8172, 0.8292"); } cell_fall(delay_template_5x6) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.303149, 0.322627, 0.347188, 0.368888, 0.378125, 0.386128", \ "0.337858, 0.356312, 0.380282, 0.401886, 0.41091, 0.419264", \ "0.396682, 0.416244, 0.438962, 0.46015, 0.469605, 0.478097", \ "0.603284, 0.622428, 0.64428, 0.666224, 0.674929, 0.684876", \ "0.898338, 0.917426, 0.939281, 0.96087, 0.969525, 0.98112"); } fall_transition(delay_template_5x6) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.1062, 0.1098, 0.1002, 0.1032, 0.0996, 0.1002", \ "0.1344, 0.132, 0.1314, 0.132, 0.132, 0.1332", \ "0.189, 0.1908, 0.1878, 0.1872, 0.1902, 0.189", \ "0.4272, 0.4266, 0.4266, 0.4266, 0.4278, 0.429", \ "0.8052, 0.8058, 0.8052, 0.8052, 0.8046, 0.807"); } } internal_power() { related_pin : "CLK"; rise_power(energy_template_5x6) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.738447, 1.13955, 1.81255, 3.06436, 3.94466, 5.6651", \ "0.682919, 1.06968, 1.73359, 2.96785, 3.83555, 5.5528", \ "0.628524, 1.01355, 1.64626, 2.85289, 3.71358, 5.40924", \ "0.587532, 0.95378, 1.55083, 2.67643, 3.51508, 5.19076", \ "0.568173, 0.925679, 1.50894, 2.60253, 3.41433, 5.06145"); } fall_power(energy_template_5x6) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.901564, 1.19181, 1.68846, 2.61034, 3.29825, 4.65361", \ "0.84858, 1.13986, 1.63259, 2.56306, 3.23363, 4.58751", \ "0.802682, 1.09744, 1.60019, 2.52049, 3.18799, 4.54508", \ "0.767736, 1.06134, 1.55728, 2.47799, 3.14439, 4.49318", \ "0.752786, 1.04649, 1.54374, 2.46449, 3.12926, 4.47698"); } } } } /* -------------- * * Design : DFFSR * * -------------- */ cell (DFFSR) { area : 1584; cell_leakage_power : 0.532978; ff (P0002,P0003) { next_state : "D"; clocked_on : "CLK"; clear : "(!R)"; preset : "(!S)"; clear_preset_var1 : L; } pin(CLK) { direction : input; capacitance : 0.0161478; rise_capacitance : 0.0161127; fall_capacitance : 0.0161478; clock : true; internal_power() { rise_power(passive_energy_template_6x1) { index_1 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ("0.533084, 0.64859, 0.872439, 1.29672, 1.60272, 2.23251"); } fall_power(passive_energy_template_6x1) { index_1 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ("1.59914, 1.73861, 1.95938, 2.42184, 2.74605, 3.39366"); } } min_pulse_width_high : 0.488409; min_pulse_width_low : 0.332997; } pin(D) { direction : input; capacitance : 0.0162024; rise_capacitance : 0.0161472; fall_capacitance : 0.0162024; internal_power() { rise_power(passive_energy_template_6x1) { index_1 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ("1.06131, 1.19865, 1.41985, 1.85576, 2.17858, 2.86795"); } fall_power(passive_energy_template_6x1) { index_1 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ("1.58853, 1.70659, 1.95734, 2.4411, 2.79646, 3.5042"); } } timing() { related_pin : "CLK"; timing_type : hold_rising; when : "S&R"; sdf_cond : "S\&R"; rise_constraint(hold_template_3x6) { index_1 ("0.06, 0.3, 0.6"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0, -0.0375, -0.11875, -0.14375, -0.175, -0.2375", \ "-0.0125, -0.05, -0.0375, -0.15625, -0.1875, -0.15625", \ "0.01875, -0.01875, -0.1, -0.125, -0.15625, -0.21875"); } fall_constraint(hold_template_3x6) { index_1 ("0.06, 0.3, 0.6"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.09375, 0.05625, -0.025, -0.05, -0.08125, -0.14375", \ "0.08125, 0.04375, 0.05625, -0.0625, -0.09375, -0.0625", \ "0.1125, 0.16875, 0.0875, 0.0625, 0.03125, -0.125"); } } timing() { related_pin : "CLK"; timing_type : setup_rising; when : "S&R"; sdf_cond : "S\&R"; rise_constraint(setup_template_3x6) { index_1 ("0.06, 0.3, 0.6"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.1875, 0.225, 0.2125, 0.33125, 0.3625, 0.425", \ "0.10625, 0.14375, 0.225, 0.25, 0.28125, 0.34375", \ "0.16875, 0.20625, 0.19375, 0.21875, 0.25, 0.3125"); } fall_constraint(setup_template_3x6) { index_1 ("0.06, 0.3, 0.6"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.09375, 0.13125, 0.2125, 0.2375, 0.26875, 0.33125", \ "0.10625, 0.14375, 0.225, 0.25, 0.28125, 0.34375", \ "0.075, 0.1125, 0.19375, 0.21875, 0.25, 0.3125"); } } } pin(Q) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.408128; function : "P0002"; timing() { related_pin : "CLK"; timing_sense : non_unate; timing_type : rising_edge; cell_rise(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.573866, 0.613176, 0.655984, 0.714226, 0.742853, 0.794575", \ "1.29445, 1.33373, 1.3766, 1.43492, 1.46396, 1.51551", \ "2.55414, 2.59348, 2.63587, 2.6946, 2.72373, 2.77505", \ "5.79314, 5.83241, 5.87514, 5.93343, 5.96176, 6.01425", \ "7.5931, 7.63237, 7.67518, 7.73353, 7.76191, 7.81415", \ "9.39247, 9.43174, 9.47303, 9.53288, 9.562, 9.61348"); } rise_transition(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.291, 0.291, 0.291, 0.2916, 0.2904, 0.291", \ "1.3536, 1.3536, 1.3536, 1.3536, 1.3536, 1.3536", \ "3.2346, 3.2346, 3.2346, 3.2346, 3.2346, 3.2346", \ "8.0712, 8.0712, 8.0712, 8.0712, 8.0718, 8.0706", \ "10.7562, 10.7562, 10.7562, 10.7562, 10.758, 10.7568", \ "13.443, 13.443, 13.4472, 13.4436, 13.4448, 13.443"); } cell_fall(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.652297, 0.688969, 0.731579, 0.782333, 0.809637, 0.850367", \ "1.53586, 1.57254, 1.61549, 1.66614, 1.69348, 1.73373", \ "3.0819, 3.11825, 3.16119, 3.21197, 3.23944, 3.27961", \ "7.05664, 7.09318, 7.13613, 7.18652, 7.21418, 7.25432", \ "9.26432, 9.30186, 9.34482, 9.39504, 9.42123, 9.46198", \ "11.4734, 11.5091, 11.552, 11.6041, 11.6309, 11.6711"); } fall_transition(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.3054, 0.306, 0.3048, 0.3054, 0.306, 0.3054", \ "1.4568, 1.4574, 1.4574, 1.4568, 1.4574, 1.4574", \ "3.4848, 3.4848, 3.4848, 3.4848, 3.4848, 3.4842", \ "8.6994, 8.6976, 8.6976, 8.6982, 8.6994, 8.6994", \ "11.5956, 11.5932, 11.5932, 11.5938, 11.595, 11.5956", \ "14.4882, 14.4924, 14.4924, 14.4894, 14.4888, 14.4882"); } } timing() { related_pin : "R"; timing_sense : positive_unate; timing_type : clear; cell_rise(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.32923, 0.32424, 0.31922, 0.298039, 0.272872, 0.210149", \ "1.05001, 1.04429, 1.03913, 1.02237, 1.00443, 0.961593", \ "2.3096, 2.30362, 2.29853, 2.28091, 2.26278, 2.2205", \ "5.54809, 5.54303, 5.53711, 5.51981, 5.50103, 5.45706", \ "7.34778, 7.34256, 7.33732, 7.31937, 7.30081, 7.25725", \ "9.14753, 9.14253, 9.1367, 9.11851, 9.09828, 9.05603"); } rise_transition(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.2856, 0.2868, 0.2934, 0.3072, 0.3174, 0.3336", \ "1.3536, 1.3536, 1.3536, 1.356, 1.3602, 1.3776", \ "3.2346, 3.2352, 3.2346, 3.2346, 3.2352, 3.2376", \ "8.0724, 8.0706, 8.0724, 8.0694, 8.0712, 8.0718", \ "10.7586, 10.7574, 10.7562, 10.7574, 10.7568, 10.7568", \ "13.4466, 13.4442, 13.4436, 13.4466, 13.4478, 13.4478"); } cell_fall(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.40782, 0.469834, 0.553986, 0.686965, 0.77489, 0.926916", \ "1.29173, 1.35311, 1.43532, 1.56495, 1.64896, 1.80245", \ "2.83757, 2.89908, 2.98085, 3.10968, 3.19332, 3.34563", \ "6.81244, 6.87364, 6.95546, 7.084, 7.16725, 7.3192", \ "9.02052, 9.08236, 9.16271, 9.29202, 9.37504, 9.52728", \ "11.2282, 11.2906, 11.3722, 11.4997, 11.5832, 11.7352"); } fall_transition(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.3066, 0.306, 0.3069, 0.3093, 0.3138, 0.3213", \ "1.4565, 1.4565, 1.4568, 1.4565, 1.4571, 1.4583", \ "3.4842, 3.4839, 3.4833, 3.4839, 3.4836, 3.4839", \ "8.6979, 8.6976, 8.6979, 8.6979, 8.6976, 8.6982", \ "11.5935, 11.5929, 11.5932, 11.5947, 11.5947, 11.5944", \ "14.4891, 14.4906, 14.4888, 14.49, 14.4918, 14.4897"); } } timing() { related_pin : "S"; timing_sense : negative_unate; timing_type : preset; cell_rise(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.463437, 0.517037, 0.57933, 0.679292, 0.743623, 0.858841", \ "1.18362, 1.23865, 1.30004, 1.39947, 1.46366, 1.5784", \ "2.44307, 2.4983, 2.55977, 2.65878, 2.72336, 2.83787", \ "5.68203, 5.73599, 5.79805, 5.89815, 5.96192, 6.07673", \ "7.4807, 7.53452, 7.59867, 7.69806, 7.76148, 7.87684", \ "9.28009, 9.33419, 9.3981, 9.49752, 9.55964, 9.67629"); } rise_transition(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.2871, 0.2871, 0.2874, 0.2883, 0.288, 0.2898", \ "1.3533, 1.3536, 1.3536, 1.3536, 1.3533, 1.3533", \ "3.2346, 3.2349, 3.2346, 3.2346, 3.2346, 3.2343", \ "8.0715, 8.0712, 8.0718, 8.0709, 8.0712, 8.0712", \ "10.7604, 10.7604, 10.7562, 10.7562, 10.758, 10.7562", \ "13.4472, 13.4472, 13.4436, 13.443, 13.4478, 13.4436"); } } internal_power() { related_pin : "CLK"; rise_power(energy_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "2.08141, 2.18952, 2.42948, 2.89115, 3.22293, 3.90308", \ "2.07713, 2.18521, 2.42592, 2.88704, 3.21934, 3.90205", \ "2.07653, 2.18536, 2.42632, 2.88654, 3.22006, 3.90205", \ "2.07946, 2.18796, 2.4276, 2.89043, 3.2205, 3.90555", \ "2.07995, 2.18803, 2.42927, 2.89068, 3.22266, 3.90807", \ "2.08132, 2.18861, 2.43034, 2.89094, 3.22096, 3.91014"); } fall_power(energy_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "1.85143, 1.97358, 2.1981, 2.64177, 2.94988, 3.60177", \ "1.85234, 1.96648, 2.20018, 2.64376, 2.95145, 3.60189", \ "1.8539, 1.96721, 2.20162, 2.64488, 2.95307, 3.60263", \ "1.85341, 1.96892, 2.20245, 2.64631, 2.95448, 3.60164", \ "1.85549, 1.96944, 2.20408, 2.6469, 2.95483, 3.60365", \ "1.85463, 1.96702, 2.20272, 2.64757, 2.9543, 3.60432"); } } internal_power() { related_pin : "R"; rise_power(energy_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.540841, 0.858627, 1.46125, 2.57686, 3.39555, 5.06212", \ "0.541809, 0.857503, 1.44739, 2.54238, 3.34595, 4.97569", \ "0.543116, 0.859338, 1.44704, 2.5366, 3.33505, 4.95529", \ "0.545225, 0.860908, 1.44925, 2.53482, 3.32966, 4.94629", \ "0.544411, 0.865325, 1.44705, 2.53352, 3.32919, 4.94674", \ "0.546808, 0.86465, 1.44665, 2.53122, 3.32987, 4.94405"); } fall_power(energy_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "2.07839, 2.44842, 3.10475, 4.18568, 4.86251, 6.02632", \ "2.07957, 2.44625, 3.09266, 4.14788, 4.81134, 5.9572", \ "2.08021, 2.44745, 3.09216, 4.14372, 4.80416, 5.94547", \ "2.08037, 2.44766, 3.09184, 4.14268, 4.80147, 5.94312", \ "2.07952, 2.4473, 3.09178, 4.14358, 4.80194, 5.94337", \ "2.08075, 2.44503, 3.09326, 4.14357, 4.80106, 5.9429"); } } internal_power() { related_pin : "S"; power(energy_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "2.06608, 2.349, 2.83626, 3.76572, 4.37409, 5.50456", \ "2.06327, 2.34828, 2.83433, 3.76073, 4.36721, 5.49504", \ "2.06361, 2.3497, 2.83553, 3.76117, 4.36687, 5.49494", \ "2.06528, 2.35224, 2.83623, 3.76414, 4.36664, 5.49468", \ "2.06287, 2.35455, 2.83688, 3.76482, 4.3669, 5.49524", \ "2.06527, 2.35404, 2.83651, 3.76557, 4.36575, 5.49696"); } } } pin(R) { direction : input; capacitance : 0.0430178; rise_capacitance : 0.0430178; fall_capacitance : 0.0386243; min_pulse_width_low : 0.22713; timing() { related_pin : "CLK"; timing_type : recovery_rising; when : "D&S"; sdf_cond : "D\&S"; rise_constraint(recovery_template_3x6) { index_1 ("0.06, 0.3, 0.6"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "-0.1875, -0.15, -0.1625, -0.04375, 0.08125, 0.2375", \ "-0.175, -0.23125, -0.15, -0.125, 0, 0.25", \ "-0.20625, -0.2625, -0.18125, -0.0625, -0.03125, 0.125"); } } timing() { related_pin : "S"; timing_type : recovery_rising; rise_constraint(recovery_template_6x6) { index_1 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0, 0.05625, 0.06875, 0.1375, 0.10625, 0.23125", \ "0.0375, 0.046875, 0.0125, 0.08125, 0.14375, 0.26875", \ "0.025, 0.034375, 0.046875, 0.06875, 0.13125, 0.209375", \ "0.003125, 0.0125, 0.025, 0.09375, 0.109375, 0.1875", \ "-0.059375, -0.003125, -0.0375, 0.03125, 0.09375, 0.171875", \ "-0.090625, -0.034375, -0.06875, 0, 0.015625, 0.140625"); } } timing() { related_pin : "CLK"; timing_type : removal_rising; when : "D&S"; sdf_cond : "D\&S"; rise_constraint(removal_template_3x6) { index_1 ("0.06, 0.3, 0.6"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.28125, 0.3375, 0.35, 0.41875, 0.48125, 0.60625", \ "0.3625, 0.41875, 0.43125, 0.5, 0.5625, 0.59375", \ "0.39375, 0.45, 0.4625, 0.53125, 0.59375, 0.71875"); } } } pin(S) { direction : input; capacitance : 0.0391758; rise_capacitance : 0.0267845; fall_capacitance : 0.0391758; internal_power() { rise_power(passive_energy_template_6x1) { index_1 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ("0.516746, 0.520821, 0.516314, 0.497548, 0.51356, 0.50767"); } fall_power(passive_energy_template_6x1) { index_1 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ("0, 0, 0, 0, 0, 0"); } } min_pulse_width_low : 0.264082; timing() { related_pin : "CLK"; timing_type : recovery_rising; when : "!D&R"; sdf_cond : "\~D\&R"; rise_constraint(recovery_template_3x6) { index_1 ("0.06, 0.3, 0.6"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0, 0.0375, 0.025, 0.05, 0.08125, 0.2375", \ "-0.08125, -0.04375, -0.05625, 0.0625, 0, 0.15625", \ "-0.1125, -0.075, -0.0875, 0.03125, 0.0625, 0.125"); } } timing() { related_pin : "R"; timing_type : recovery_rising; rise_constraint(recovery_template_6x6) { index_1 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.09375, 0.05625, 0.06875, 0.090625, 0.153125, 0.184375", \ "0.0375, 0.09375, 0.059375, 0.08125, 0.096875, 0.128125", \ "0.025, 0.08125, 0.09375, 0.06875, 0.13125, 0.1625", \ "0.003125, 0.0125, 0.025, 0.046875, 0.0625, 0.09375", \ "-0.0125, -0.003125, 0.009375, -0.015625, 0.046875, 0.078125", \ "-0.090625, -0.08125, -0.06875, -0.046875, -0.03125, 0"); } } timing() { related_pin : "CLK"; timing_type : removal_rising; when : "!D&R"; sdf_cond : "\~D\&R"; rise_constraint(removal_template_3x6) { index_1 ("0.06, 0.3, 0.6"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.1875, 0.15, 0.1625, 0.1375, 0.10625, 0.1375", \ "0.175, 0.1375, 0.15, 0.125, 0.1875, 0.125", \ "0.3, 0.2625, 0.18125, 0.15625, 0.21875, 0.15625"); } } } } /* ------------- * * Design : FAX1 * * ------------- */ cell (FAX1) { area : 1080; cell_leakage_power : 0.364299; pin(A) { direction : input; capacitance : 0.123442; rise_capacitance : 0.122014; fall_capacitance : 0.123442; } pin(B) { direction : input; capacitance : 0.111035; rise_capacitance : 0.111035; fall_capacitance : 0.105217; } pin(C) { direction : input; capacitance : 0.0786577; rise_capacitance : 0.0786577; fall_capacitance : 0.0784684; } pin(YC) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.408882; function : "(((A B)+(B C))+(C A))"; timing() { related_pin : "A"; timing_sense : positive_unate; cell_rise(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.242292, 0.246603, 0.268885, 0.28311, 0.310866", \ "0.296314, 0.300633, 0.323201, 0.337781, 0.37052", \ "0.39527, 0.399189, 0.42212, 0.437668, 0.476229", \ "0.76302, 0.766332, 0.788868, 0.804417, 0.848294", \ "1.30322, 1.30665, 1.32873, 1.34374, 1.38665"); } rise_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1095, 0.1092, 0.1164, 0.1239, 0.1446", \ "0.1683, 0.1707, 0.1761, 0.1809, 0.2055", \ "0.2994, 0.2988, 0.303, 0.306, 0.3285", \ "0.8226, 0.8229, 0.8232, 0.825, 0.8355", \ "1.623, 1.623, 1.623, 1.6236, 1.6263"); } cell_fall(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.269289, 0.28515, 0.333894, 0.368482, 0.468653", \ "0.336013, 0.351981, 0.400635, 0.435701, 0.541894", \ "0.456213, 0.471545, 0.519905, 0.555166, 0.667397", \ "0.900977, 0.915844, 0.962475, 0.997684, 1.11037", \ "1.56322, 1.57805, 1.62408, 1.65882, 1.76893"); } fall_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1167, 0.1176, 0.123, 0.1293, 0.1572", \ "0.1842, 0.1821, 0.1887, 0.195, 0.2238", \ "0.3186, 0.3186, 0.321, 0.3258, 0.3492", \ "0.8805, 0.8805, 0.8808, 0.8814, 0.8877", \ "1.7466, 1.7469, 1.7466, 1.7466, 1.7481"); } } timing() { related_pin : "B"; timing_sense : positive_unate; cell_rise(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.252597, 0.261402, 0.287423, 0.302068, 0.332683", \ "0.306967, 0.315322, 0.342951, 0.35833, 0.393014", \ "0.405846, 0.41439, 0.444381, 0.460933, 0.499274", \ "0.774223, 0.782436, 0.811945, 0.8305, 0.874711", \ "1.31399, 1.32252, 1.35163, 1.36956, 1.41534"); } rise_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1083, 0.1077, 0.1143, 0.1209, 0.1392", \ "0.1689, 0.1695, 0.1779, 0.18, 0.1998", \ "0.2994, 0.2997, 0.3045, 0.3102, 0.327", \ "0.8232, 0.8229, 0.8238, 0.8262, 0.837", \ "1.623, 1.623, 1.6227, 1.6233, 1.6281"); } cell_fall(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.280266, 0.300866, 0.352232, 0.386423, 0.490973", \ "0.348225, 0.369756, 0.422647, 0.458228, 0.56571", \ "0.469882, 0.491171, 0.544898, 0.582938, 0.695301", \ "0.916161, 0.937476, 0.990275, 1.02887, 1.14758", \ "1.57818, 1.59964, 1.65194, 1.69001, 1.8075"); } fall_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1188, 0.1194, 0.1305, 0.1332, 0.1521", \ "0.1872, 0.1875, 0.198, 0.2034, 0.2241", \ "0.3216, 0.3225, 0.3276, 0.3354, 0.3552", \ "0.8823, 0.8823, 0.8829, 0.8841, 0.8952", \ "1.7469, 1.7469, 1.7469, 1.7469, 1.7502"); } } timing() { related_pin : "C"; timing_sense : positive_unate; cell_rise(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.233744, 0.255656, 0.294191, 0.316125, 0.364591", \ "0.287421, 0.310044, 0.349861, 0.371061, 0.422201", \ "0.387065, 0.408897, 0.450463, 0.472899, 0.527056", \ "0.754693, 0.776207, 0.816357, 0.839473, 0.895593", \ "1.29468, 1.31606, 1.35531, 1.37852, 1.43484"); } rise_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.108, 0.1086, 0.1107, 0.1182, 0.1386", \ "0.1698, 0.1701, 0.1761, 0.1791, 0.1986", \ "0.2988, 0.2994, 0.303, 0.3075, 0.3225", \ "0.8223, 0.8223, 0.8223, 0.8235, 0.8304", \ "1.6224, 1.6224, 1.6224, 1.6224, 1.6254"); } cell_fall(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.260837, 0.292746, 0.360159, 0.404097, 0.531034", \ "0.328878, 0.359592, 0.428584, 0.472935, 0.602672", \ "0.450662, 0.481333, 0.549774, 0.594844, 0.726969", \ "0.897233, 0.928071, 0.994943, 1.03975, 1.17282", \ "1.55947, 1.59025, 1.6566, 1.70107, 1.83201"); } fall_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1188, 0.1176, 0.1236, 0.1314, 0.1512", \ "0.1863, 0.1863, 0.195, 0.2001, 0.2181", \ "0.3228, 0.3222, 0.3255, 0.3303, 0.3459", \ "0.8826, 0.8826, 0.8826, 0.8832, 0.8901", \ "1.7469, 1.7472, 1.7472, 1.7472, 1.7487"); } } internal_power() { related_pin : "A"; rise_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.010739, 0.040504, 0.244642, 0.444822, 1.18646", \ "0.010661, 0.037955, 0.244643, 0.436291, 1.15249", \ "0.007331, 0.033337, 0.234699, 0.422407, 1.12231", \ "0.00211, 0.026926, 0.224644, 0.406084, 1.0852", \ "-0.000559, 0.024226, 0.221085, 0.400663, 1.07115"); } fall_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "2.08822, 2.12027, 2.34309, 2.5481, 3.29771", \ "2.08638, 2.11545, 2.3342, 2.53707, 3.26308", \ "2.08414, 2.11124, 2.32445, 2.52405, 3.24458", \ "2.08221, 2.1079, 2.31656, 2.51119, 3.2123", \ "2.08134, 2.10645, 2.31447, 2.50735, 3.20041"); } } internal_power() { related_pin : "B"; rise_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.255228, 0.256598, 0.412717, 0.563576, 1.16624", \ "0.256534, 0.257108, 0.408427, 0.558628, 1.13546", \ "0.254562, 0.253053, 0.40245, 0.547476, 1.11121", \ "0.249552, 0.247497, 0.392987, 0.535276, 1.08325", \ "0.246437, 0.245499, 0.389727, 0.531843, 1.07292"); } fall_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "1.94495, 1.95578, 2.12986, 2.29079, 2.9021", \ "1.94176, 1.95461, 2.12398, 2.28412, 2.87772", \ "1.9358, 1.94613, 2.11336, 2.27189, 2.86309", \ "1.93032, 1.94014, 2.10266, 2.25744, 2.83462", \ "1.92835, 1.93826, 2.09945, 2.25314, 2.82449"); } } internal_power() { related_pin : "C"; rise_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.469577, 0.493949, 0.632215, 0.765932, 1.30558", \ "0.467605, 0.492035, 0.627105, 0.757894, 1.27729", \ "0.466099, 0.490037, 0.619411, 0.749122, 1.25622", \ "0.464805, 0.488498, 0.612673, 0.739015, 1.23036", \ "0.464731, 0.488306, 0.611883, 0.736154, 1.2218"); } fall_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "1.64279, 1.67014, 1.83587, 1.97713, 2.52334", \ "1.63858, 1.66412, 1.82583, 1.96798, 2.49929", \ "1.62976, 1.65624, 1.81426, 1.95399, 2.4814", \ "1.62428, 1.65122, 1.80132, 1.9392, 2.45206", \ "1.62289, 1.64977, 1.79819, 1.93524, 2.44152"); } } } pin(YS) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.411416; function : "((A^B)^C)"; timing() { related_pin : "A"; timing_sense : non_unate; cell_rise(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.362431, 0.377398, 0.424203, 0.454396, 0.545715", \ "0.41108, 0.42815, 0.472969, 0.504082, 0.594695", \ "0.50274, 0.520065, 0.565379, 0.596062, 0.686206", \ "0.862874, 0.879704, 0.925517, 0.956054, 1.04613", \ "1.40268, 1.41955, 1.46532, 1.49553, 1.58592"); } rise_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1017, 0.0984, 0.0999, 0.0981, 0.1032", \ "0.1584, 0.159, 0.1599, 0.1605, 0.162", \ "0.2853, 0.2853, 0.2853, 0.2865, 0.2862", \ "0.8169, 0.8172, 0.8172, 0.8169, 0.8175", \ "1.6221, 1.6221, 1.6221, 1.6224, 1.6224"); } cell_fall(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.383533, 0.388226, 0.409407, 0.423772, 0.451988", \ "0.446502, 0.451184, 0.472296, 0.486073, 0.513326", \ "0.562116, 0.566927, 0.588217, 0.601247, 0.627995", \ "1.00537, 1.01039, 1.03139, 1.0444, 1.07027", \ "1.66753, 1.67246, 1.69341, 1.70649, 1.73207"); } fall_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1149, 0.1143, 0.1131, 0.1143, 0.1161", \ "0.1773, 0.1788, 0.1794, 0.1785, 0.18", \ "0.312, 0.3126, 0.3132, 0.3132, 0.3132", \ "0.8802, 0.8805, 0.8808, 0.8805, 0.8805", \ "1.7469, 1.7466, 1.7469, 1.7472, 1.7469"); } } timing() { related_pin : "B"; timing_sense : non_unate; cell_rise(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.382649, 0.40016, 0.447348, 0.483762, 0.582925", \ "0.432687, 0.452006, 0.498207, 0.532544, 0.632118", \ "0.525962, 0.544593, 0.590847, 0.625689, 0.723475", \ "0.887201, 0.905637, 0.95212, 0.985969, 1.08282", \ "1.4275, 1.44585, 1.49223, 1.52564, 1.62223"); } rise_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1053, 0.1056, 0.1056, 0.102, 0.1032", \ "0.1647, 0.1629, 0.1644, 0.1623, 0.1638", \ "0.2892, 0.2895, 0.2901, 0.288, 0.2871", \ "0.8184, 0.8184, 0.8184, 0.8184, 0.8178", \ "1.623, 1.6227, 1.623, 1.6227, 1.6224"); } cell_fall(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.398666, 0.405198, 0.428581, 0.444208, 0.47717", \ "0.461919, 0.468628, 0.491478, 0.506179, 0.538525", \ "0.577429, 0.584285, 0.608242, 0.622243, 0.65293", \ "1.02077, 1.02778, 1.05178, 1.06578, 1.09491", \ "1.68269, 1.68997, 1.71389, 1.72907, 1.75689"); } fall_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1167, 0.1173, 0.1164, 0.1158, 0.1152", \ "0.1782, 0.1788, 0.1785, 0.1779, 0.1782", \ "0.3132, 0.3132, 0.3132, 0.3123, 0.3123", \ "0.8802, 0.8805, 0.8805, 0.8805, 0.8799", \ "1.7469, 1.7469, 1.7469, 1.7469, 1.7472"); } } timing() { related_pin : "C"; timing_sense : non_unate; cell_rise(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.37741, 0.405374, 0.463961, 0.504876, 0.619267", \ "0.426525, 0.455362, 0.513807, 0.554451, 0.667026", \ "0.519068, 0.547986, 0.606648, 0.646173, 0.75912", \ "0.87925, 0.907882, 0.967429, 1.00829, 1.12094", \ "1.41959, 1.44808, 1.50764, 1.54831, 1.66165"); } rise_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1062, 0.1047, 0.1062, 0.1041, 0.1014", \ "0.1632, 0.1638, 0.1641, 0.1626, 0.1611", \ "0.2898, 0.2892, 0.2892, 0.2898, 0.2886", \ "0.8187, 0.8187, 0.8184, 0.819, 0.8214", \ "1.623, 1.623, 1.623, 1.6233, 1.6251"); } cell_fall(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.375669, 0.39497, 0.425638, 0.445484, 0.491002", \ "0.435996, 0.455692, 0.487137, 0.504893, 0.549334", \ "0.548958, 0.569019, 0.6004, 0.619287, 0.661906", \ "0.991287, 1.01154, 1.04196, 1.06186, 1.10346", \ "1.65388, 1.67395, 1.70423, 1.72439, 1.76577"); } fall_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.108, 0.1089, 0.108, 0.1026, 0.1056", \ "0.1725, 0.1731, 0.1716, 0.1695, 0.1701", \ "0.3072, 0.3072, 0.3066, 0.3072, 0.3063", \ "0.879, 0.879, 0.879, 0.8796, 0.8796", \ "1.7466, 1.7466, 1.7466, 1.7469, 1.7472"); } } internal_power() { related_pin : "A"; rise_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "2.08822, 2.12027, 2.34309, 2.5481, 3.29771", \ "2.08638, 2.11545, 2.3342, 2.53707, 3.26308", \ "2.08414, 2.11124, 2.32445, 2.52405, 3.24458", \ "2.08221, 2.1079, 2.31656, 2.51119, 3.2123", \ "2.08134, 2.10645, 2.31447, 2.50735, 3.20041"); } fall_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.010739, 0.040504, 0.244642, 0.444822, 1.18646", \ "0.010661, 0.037955, 0.244643, 0.436291, 1.15249", \ "0.007331, 0.033337, 0.234699, 0.422407, 1.12231", \ "0.00211, 0.026926, 0.224644, 0.406084, 1.0852", \ "-0.000559, 0.024226, 0.221085, 0.400663, 1.07115"); } } internal_power() { related_pin : "B"; rise_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "1.94495, 1.95578, 2.12986, 2.29079, 2.9021", \ "1.94176, 1.95461, 2.12398, 2.28412, 2.87772", \ "1.9358, 1.94613, 2.11336, 2.27189, 2.86309", \ "1.93032, 1.94014, 2.10266, 2.25744, 2.83462", \ "1.92835, 1.93826, 2.09945, 2.25314, 2.82449"); } fall_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.255228, 0.256598, 0.412717, 0.563576, 1.16624", \ "0.256534, 0.257108, 0.408427, 0.558628, 1.13546", \ "0.254562, 0.253053, 0.40245, 0.547476, 1.11121", \ "0.249552, 0.247497, 0.392987, 0.535276, 1.08325", \ "0.246437, 0.245499, 0.389727, 0.531843, 1.07292"); } } internal_power() { related_pin : "C"; rise_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "1.64279, 1.67014, 1.83587, 1.97713, 2.52334", \ "1.63858, 1.66412, 1.82583, 1.96798, 2.49929", \ "1.62976, 1.65624, 1.81426, 1.95399, 2.4814", \ "1.62428, 1.65122, 1.80132, 1.9392, 2.45206", \ "1.62289, 1.64977, 1.79819, 1.93524, 2.44152"); } fall_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.469577, 0.493949, 0.632215, 0.765932, 1.30558", \ "0.467605, 0.492035, 0.627105, 0.757894, 1.27729", \ "0.466099, 0.490037, 0.619411, 0.749122, 1.25622", \ "0.464805, 0.488498, 0.612673, 0.739015, 1.23036", \ "0.464731, 0.488306, 0.611883, 0.736154, 1.2218"); } } } } /* ------------- * * Design : HAX1 * * ------------- */ cell (HAX1) { area : 720; cell_leakage_power : 0.266037; pin(A) { direction : input; capacitance : 0.0473955; rise_capacitance : 0.0471036; fall_capacitance : 0.0473955; } pin(B) { direction : input; capacitance : 0.0377864; rise_capacitance : 0.0377864; fall_capacitance : 0.0375514; } pin(YC) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.412434; function : "(A B)"; timing() { related_pin : "A"; timing_sense : positive_unate; cell_rise(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.176848, 0.17568, 0.176663, 0.167718, 0.116869", \ "0.226931, 0.226134, 0.228998, 0.22186, 0.174528", \ "0.320491, 0.32071, 0.323719, 0.318425, 0.277488", \ "0.682743, 0.682667, 0.685643, 0.680942, 0.650334", \ "1.22259, 1.22256, 1.22516, 1.21979, 1.18993"); } rise_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0984, 0.0984, 0.1128, 0.1206, 0.1326", \ "0.1578, 0.1596, 0.1668, 0.174, 0.195", \ "0.288, 0.288, 0.2928, 0.2988, 0.3198", \ "0.8178, 0.8178, 0.8178, 0.8196, 0.834", \ "1.6218, 1.6218, 1.6218, 1.6218, 1.626"); } cell_fall(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.234103, 0.27268, 0.360803, 0.421477, 0.605709", \ "0.296367, 0.334034, 0.42297, 0.483924, 0.67057", \ "0.409813, 0.447381, 0.535182, 0.596014, 0.78383", \ "0.852157, 0.889677, 0.976319, 1.03599, 1.22068", \ "1.5149, 1.55228, 1.63854, 1.6978, 1.88065"); } fall_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1086, 0.1092, 0.1122, 0.1188, 0.1404", \ "0.1722, 0.171, 0.177, 0.1818, 0.1974", \ "0.3066, 0.3066, 0.3084, 0.309, 0.3204", \ "0.8784, 0.8784, 0.879, 0.8784, 0.8808", \ "1.7466, 1.7466, 1.7466, 1.7466, 1.7472"); } } timing() { related_pin : "B"; timing_sense : positive_unate; cell_rise(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.174874, 0.191465, 0.206444, 0.211398, 0.206628", \ "0.226284, 0.242661, 0.258652, 0.264901, 0.261197", \ "0.319614, 0.3357, 0.35434, 0.360841, 0.361721", \ "0.681652, 0.697298, 0.716009, 0.724065, 0.729389", \ "1.22144, 1.23708, 1.25536, 1.26337, 1.26998"); } rise_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0972, 0.1008, 0.105, 0.1122, 0.1326", \ "0.1584, 0.159, 0.1656, 0.1716, 0.1896", \ "0.2868, 0.288, 0.2934, 0.2976, 0.3138", \ "0.8178, 0.8178, 0.8178, 0.8196, 0.8298", \ "1.6218, 1.6218, 1.6218, 1.6218, 1.626"); } cell_fall(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.21535, 0.250001, 0.327714, 0.378974, 0.526267", \ "0.276754, 0.311292, 0.38975, 0.441289, 0.592582", \ "0.391268, 0.425078, 0.502941, 0.554343, 0.708552", \ "0.833733, 0.868781, 0.944901, 0.995183, 1.14827", \ "1.49626, 1.53142, 1.60716, 1.65718, 1.80832"); } fall_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1014, 0.1038, 0.1104, 0.1152, 0.1356", \ "0.1704, 0.1686, 0.174, 0.1806, 0.1974", \ "0.306, 0.306, 0.3078, 0.3108, 0.324", \ "0.8784, 0.879, 0.8784, 0.879, 0.8814", \ "1.7466, 1.7466, 1.7466, 1.7466, 1.7466"); } } internal_power() { related_pin : "A"; rise_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.438705, 0.452702, 0.615383, 0.753782, 1.26492", \ "0.436024, 0.44073, 0.603116, 0.742654, 1.24095", \ "0.435564, 0.441746, 0.597683, 0.733783, 1.2201", \ "0.438858, 0.442388, 0.595529, 0.725684, 1.1991", \ "0.438946, 0.442332, 0.593887, 0.72284, 1.19112"); } fall_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "1.07764, 1.12602, 1.30813, 1.46039, 1.99741", \ "1.07918, 1.12694, 1.30064, 1.45271, 1.97584", \ "1.08147, 1.12621, 1.29608, 1.44704, 1.95368", \ "1.08295, 1.12769, 1.29103, 1.43525, 1.93346", \ "1.07912, 1.12432, 1.29125, 1.43452, 1.92709"); } } internal_power() { related_pin : "B"; rise_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.618805, 0.646434, 0.774365, 0.898379, 1.38237", \ "0.620484, 0.645936, 0.768692, 0.888841, 1.35905", \ "0.622048, 0.643946, 0.760409, 0.880413, 1.34433", \ "0.623372, 0.646963, 0.757394, 0.873719, 1.32819", \ "0.624126, 0.647431, 0.757282, 0.872129, 1.32258"); } fall_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.930125, 0.963032, 1.11759, 1.24364, 1.70648", \ "0.928932, 0.958281, 1.10892, 1.23451, 1.68524", \ "0.927827, 0.958175, 1.10468, 1.22762, 1.66871", \ "0.930064, 0.96024, 1.10265, 1.22057, 1.6517", \ "0.931526, 0.961414, 1.10283, 1.22002, 1.64621"); } } } pin(YS) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.412596; function : "(A^B)"; timing() { related_pin : "A"; timing_sense : non_unate; cell_rise(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.266939, 0.304475, 0.386415, 0.442753, 0.615263", \ "0.312855, 0.352386, 0.434008, 0.490652, 0.661817", \ "0.40806, 0.443433, 0.523837, 0.58175, 0.752702", \ "0.767369, 0.803078, 0.886491, 0.942962, 1.11071", \ "1.30842, 1.34442, 1.42661, 1.48282, 1.65015"); } rise_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0948, 0.0936, 0.0924, 0.0936, 0.1044", \ "0.1518, 0.1524, 0.1536, 0.1542, 0.1578", \ "0.282, 0.2814, 0.2814, 0.282, 0.2832", \ "0.816, 0.816, 0.816, 0.8166, 0.816", \ "1.6218, 1.6218, 1.6218, 1.6218, 1.6218"); } cell_fall(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.315483, 0.310052, 0.315076, 0.310981, 0.273186", \ "0.371941, 0.367032, 0.370263, 0.36661, 0.328172", \ "0.482312, 0.478242, 0.480482, 0.476503, 0.437129", \ "0.924723, 0.920029, 0.923425, 0.91839, 0.879048", \ "1.58736, 1.58255, 1.58593, 1.58076, 1.54107"); } fall_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1002, 0.1044, 0.0972, 0.102, 0.1044", \ "0.165, 0.1632, 0.162, 0.1626, 0.1656", \ "0.3024, 0.3012, 0.3012, 0.3018, 0.3018", \ "0.8784, 0.8778, 0.8784, 0.8784, 0.8778", \ "1.7466, 1.7466, 1.7466, 1.7466, 1.746"); } } timing() { related_pin : "B"; timing_sense : non_unate; cell_rise(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.274678, 0.308533, 0.380047, 0.426924, 0.56097", \ "0.322154, 0.356554, 0.428347, 0.474552, 0.608195", \ "0.415972, 0.447243, 0.518292, 0.564186, 0.698007", \ "0.77602, 0.810029, 0.879762, 0.926034, 1.05858", \ "1.31628, 1.35, 1.41982, 1.4657, 1.59867"); } rise_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0966, 0.0978, 0.0966, 0.096, 0.0948", \ "0.156, 0.153, 0.156, 0.1548, 0.1566", \ "0.2832, 0.2832, 0.282, 0.2826, 0.282", \ "0.8166, 0.8166, 0.8166, 0.8166, 0.816", \ "1.6218, 1.6224, 1.6218, 1.6218, 1.6218"); } cell_fall(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.314653, 0.325966, 0.343603, 0.352852, 0.36001", \ "0.370389, 0.381524, 0.397815, 0.40806, 0.414744", \ "0.482641, 0.493435, 0.509995, 0.517088, 0.527", \ "0.924095, 0.936068, 0.951705, 0.959153, 0.966679", \ "1.58667, 1.59858, 1.61426, 1.62147, 1.62867"); } fall_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1044, 0.1008, 0.1008, 0.099, 0.1038", \ "0.1656, 0.1638, 0.1638, 0.1608, 0.1644", \ "0.3018, 0.3012, 0.3012, 0.3012, 0.3048", \ "0.8784, 0.8778, 0.8784, 0.8784, 0.8772", \ "1.7466, 1.7472, 1.7466, 1.7466, 1.7454"); } } internal_power() { related_pin : "A"; rise_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "1.07764, 1.12602, 1.30813, 1.46039, 1.99741", \ "1.07918, 1.12694, 1.30064, 1.45271, 1.97584", \ "1.08147, 1.12621, 1.29608, 1.44704, 1.95368", \ "1.08295, 1.12769, 1.29103, 1.43525, 1.93346", \ "1.07912, 1.12432, 1.29125, 1.43452, 1.92709"); } fall_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.438705, 0.452702, 0.615383, 0.753782, 1.26492", \ "0.436024, 0.44073, 0.603116, 0.742654, 1.24095", \ "0.435564, 0.441746, 0.597683, 0.733783, 1.2201", \ "0.438858, 0.442388, 0.595529, 0.725684, 1.1991", \ "0.438946, 0.442332, 0.593887, 0.72284, 1.19112"); } } internal_power() { related_pin : "B"; rise_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.930125, 0.963032, 1.11759, 1.24364, 1.70648", \ "0.928932, 0.958281, 1.10892, 1.23451, 1.68524", \ "0.927827, 0.958175, 1.10468, 1.22762, 1.66871", \ "0.930064, 0.96024, 1.10265, 1.22057, 1.6517", \ "0.931526, 0.961414, 1.10283, 1.22002, 1.64621"); } fall_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.618805, 0.646434, 0.774365, 0.898379, 1.38237", \ "0.620484, 0.645936, 0.768692, 0.888841, 1.35905", \ "0.622048, 0.643946, 0.760409, 0.880413, 1.34433", \ "0.623372, 0.646963, 0.757394, 0.873719, 1.32819", \ "0.624126, 0.647431, 0.757282, 0.872129, 1.32258"); } } } } /* -------------- * * Design : INVX1 * * -------------- */ cell (INVX1) { cell_footprint : inv; area : 144; cell_leakage_power : 0.0305626; pin(A) { direction : input; capacitance : 0.0161217; rise_capacitance : 0.0160794; fall_capacitance : 0.0161217; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.413265; function : "(!A)"; timing() { related_pin : "A"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.090898, 0.115756, 0.145869, 0.162653, 0.199669", \ "0.147365, 0.172864, 0.220037, 0.245573, 0.306527", \ "0.257882, 0.281798, 0.340327, 0.378483, 0.472095", \ "0.701464, 0.722825, 0.772632, 0.813658, 0.96464", \ "1.36414, 1.38488, 1.43094, 1.46814, 1.60403"); } fall_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0858, 0.1068, 0.1632, 0.2004, 0.3084", \ "0.156, 0.165, 0.2226, 0.2622, 0.39", \ "0.2988, 0.2988, 0.333, 0.375, 0.5166", \ "0.8766, 0.876, 0.876, 0.8838, 0.9738", \ "1.7442, 1.7448, 1.7448, 1.7442, 1.7616"); } cell_rise(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.080957, 0.111593, 0.153676, 0.177004, 0.237284", \ "0.126092, 0.160006, 0.219486, 0.253547, 0.338469", \ "0.214701, 0.248631, 0.322851, 0.369581, 0.49094", \ "0.575556, 0.606287, 0.675059, 0.729478, 0.91754", \ "1.11528, 1.1456, 1.21089, 1.26141, 1.44129"); } rise_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0822, 0.1092, 0.1626, 0.195, 0.2934", \ "0.1434, 0.1584, 0.2148, 0.255, 0.375", \ "0.2784, 0.2802, 0.3192, 0.36, 0.4962", \ "0.8136, 0.8142, 0.8148, 0.8268, 0.924", \ "1.62, 1.62, 1.62, 1.6194, 1.6458"); } } internal_power() { related_pin : "A"; fall_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.149124, 0.103889, 0.065581, 0.213422, 0.743673", \ "0.142684, 0.114165, 0.020951, 0.148986, 0.637577", \ "0.135438, 0.120808, 0.023229, 0.07864, 0.499028", \ "0.130792, 0.124974, 0.07773, 0.019895, 0.2568", \ "0.129134, 0.126447, 0.099441, 0.063638, 0.123478"); } rise_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.32222, 0.385137, 0.570786, 0.726655, 1.27293", \ "0.327438, 0.368924, 0.525453, 0.666949, 1.18498", \ "0.326183, 0.355986, 0.476794, 0.595332, 1.06073", \ "0.336369, 0.344098, 0.408896, 0.48186, 0.813711", \ "0.337753, 0.340554, 0.379247, 0.426295, 0.661487"); } } } } /* -------------- * * Design : INVX2 * * -------------- */ cell (INVX2) { cell_footprint : inv; area : 144; cell_leakage_power : 0.0306994; pin(A) { direction : input; capacitance : 0.0332518; rise_capacitance : 0.0331672; fall_capacitance : 0.0332518; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.928422; function : "(!A)"; timing() { related_pin : "A"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.05, 0.1, 0.2, 0.6, 1.2"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.083236, 0.103084, 0.125348, 0.135937, 0.155045", \ "0.132874, 0.157409, 0.195144, 0.214543, 0.255179", \ "0.231997, 0.253027, 0.30693, 0.33798, 0.41082", \ "0.625331, 0.644501, 0.690884, 0.729703, 0.86777", \ "1.21478, 1.23307, 1.27536, 1.30959, 1.43757"); } fall_transition(delay_template_5x5) { index_1 ("0.05, 0.1, 0.2, 0.6, 1.2"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0786, 0.1044, 0.1626, 0.1992, 0.3102", \ "0.138, 0.156, 0.2148, 0.2562, 0.3864", \ "0.267, 0.2682, 0.3096, 0.3558, 0.5022", \ "0.7812, 0.7812, 0.7824, 0.7956, 0.9042", \ "1.5546, 1.5546, 1.5546, 1.5546, 1.5858"); } cell_rise(delay_template_5x5) { index_1 ("0.05, 0.1, 0.2, 0.6, 1.2"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.079457, 0.1113, 0.157905, 0.184435, 0.2581", \ "0.122568, 0.157546, 0.220185, 0.257332, 0.354083", \ "0.207027, 0.241994, 0.318368, 0.367435, 0.498731", \ "0.552667, 0.583829, 0.653592, 0.70967, 0.903657", \ "1.06958, 1.09964, 1.16529, 1.2172, 1.40202"); } rise_transition(delay_template_5x5) { index_1 ("0.05, 0.1, 0.2, 0.6, 1.2"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0792, 0.1074, 0.1614, 0.1956, 0.2946", \ "0.1374, 0.1542, 0.2106, 0.2514, 0.3714", \ "0.2664, 0.2694, 0.309, 0.3504, 0.4878", \ "0.78, 0.7806, 0.7812, 0.7944, 0.8934", \ "1.5522, 1.5522, 1.5522, 1.5522, 1.5804"); } } internal_power() { related_pin : "A"; fall_power(energy_template_5x5) { index_1 ("0.05, 0.1, 0.2, 0.6, 1.2"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.29714, 0.17188, 0.232966, 0.586464, 1.83852", \ "0.281905, 0.201325, 0.129881, 0.439085, 1.60494", \ "0.272175, 0.224799, 0.021923, 0.273163, 1.28927", \ "0.261216, 0.242096, 0.11753, 0.030104, 0.718006", \ "0.257947, 0.24855, 0.175658, 0.082362, 0.392101"); } rise_power(energy_template_5x5) { index_1 ("0.05, 0.1, 0.2, 0.6, 1.2"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.670779, 0.828663, 1.27275, 1.64418, 2.92862", \ "0.681458, 0.788986, 1.17101, 1.51062, 2.7397", \ "0.678498, 0.752628, 1.0559, 1.34603, 2.46509", \ "0.700348, 0.721301, 0.88851, 1.07286, 1.89356", \ "0.703724, 0.712367, 0.812973, 0.933758, 1.52607"); } } } } /* -------------- * * Design : INVX4 * * -------------- */ cell (INVX4) { cell_footprint : inv; area : 216; cell_leakage_power : 0.0613992; pin(A) { direction : input; capacitance : 0.0665036; rise_capacitance : 0.0663344; fall_capacitance : 0.0665036; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 1.85684; function : "(!A)"; timing() { related_pin : "A"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.1, 0.2, 0.4, 1.2, 2.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.083236, 0.103084, 0.125348, 0.135937, 0.155045", \ "0.132874, 0.157409, 0.195144, 0.214543, 0.255179", \ "0.231997, 0.253027, 0.30693, 0.33798, 0.41082", \ "0.625331, 0.644501, 0.690884, 0.729703, 0.86777", \ "1.21478, 1.23307, 1.27536, 1.30959, 1.43757"); } fall_transition(delay_template_5x5) { index_1 ("0.1, 0.2, 0.4, 1.2, 2.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0786, 0.1044, 0.1626, 0.1992, 0.3102", \ "0.138, 0.156, 0.2148, 0.2562, 0.3864", \ "0.267, 0.2682, 0.3096, 0.3558, 0.5022", \ "0.7812, 0.7812, 0.7824, 0.7956, 0.9042", \ "1.5546, 1.5546, 1.5546, 1.5546, 1.5858"); } cell_rise(delay_template_5x5) { index_1 ("0.1, 0.2, 0.4, 1.2, 2.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.079457, 0.1113, 0.157905, 0.184435, 0.2581", \ "0.122568, 0.157546, 0.220185, 0.257332, 0.354083", \ "0.207027, 0.241994, 0.318368, 0.367435, 0.498731", \ "0.552667, 0.583829, 0.653592, 0.70967, 0.903657", \ "1.06958, 1.09964, 1.16529, 1.2172, 1.40202"); } rise_transition(delay_template_5x5) { index_1 ("0.1, 0.2, 0.4, 1.2, 2.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0792, 0.1074, 0.1614, 0.1956, 0.2946", \ "0.1374, 0.1542, 0.2106, 0.2514, 0.3714", \ "0.2664, 0.2694, 0.309, 0.3504, 0.4878", \ "0.78, 0.7806, 0.7812, 0.7944, 0.8934", \ "1.5522, 1.5522, 1.5522, 1.5522, 1.5804"); } } internal_power() { related_pin : "A"; fall_power(energy_template_5x5) { index_1 ("0.1, 0.2, 0.4, 1.2, 2.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.594281, 0.343761, 0.465933, 1.17293, 3.67705", \ "0.563811, 0.40265, 0.259761, 0.87817, 3.20987", \ "0.54435, 0.449598, 0.043846, 0.546325, 2.57854", \ "0.522432, 0.484193, 0.235059, 0.060208, 1.43601", \ "0.515894, 0.4971, 0.351316, 0.164725, 0.784202"); } rise_power(energy_template_5x5) { index_1 ("0.1, 0.2, 0.4, 1.2, 2.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "1.34156, 1.65732, 2.54551, 3.28836, 5.85724", \ "1.36292, 1.57797, 2.34201, 3.02123, 5.4794", \ "1.357, 1.50526, 2.11181, 2.69206, 4.93018", \ "1.4007, 1.4426, 1.77702, 2.14573, 3.78713", \ "1.40745, 1.42473, 1.62595, 1.86752, 3.05214"); } } } } /* -------------- * * Design : INVX8 * * -------------- */ cell (INVX8) { cell_footprint : inv; area : 360; cell_leakage_power : 0.122801; pin(A) { direction : input; capacitance : 0.133007; rise_capacitance : 0.132669; fall_capacitance : 0.133007; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 3.71369; function : "(!A)"; timing() { related_pin : "A"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.2, 0.4, 0.8, 2.4, 4.8"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.083236, 0.103084, 0.125348, 0.135937, 0.155045", \ "0.132874, 0.157409, 0.195144, 0.214543, 0.255179", \ "0.231997, 0.253027, 0.30693, 0.33798, 0.41082", \ "0.625331, 0.644501, 0.690884, 0.729703, 0.86777", \ "1.21478, 1.23307, 1.27536, 1.30959, 1.43757"); } fall_transition(delay_template_5x5) { index_1 ("0.2, 0.4, 0.8, 2.4, 4.8"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0786, 0.1044, 0.1626, 0.1992, 0.3102", \ "0.138, 0.156, 0.2148, 0.2562, 0.3864", \ "0.267, 0.2682, 0.3096, 0.3558, 0.5022", \ "0.7812, 0.7812, 0.7824, 0.7956, 0.9042", \ "1.5546, 1.5546, 1.5546, 1.5546, 1.5858"); } cell_rise(delay_template_5x5) { index_1 ("0.2, 0.4, 0.8, 2.4, 4.8"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.079457, 0.1113, 0.157905, 0.184435, 0.2581", \ "0.122568, 0.157546, 0.220185, 0.257332, 0.354083", \ "0.207027, 0.241994, 0.318368, 0.367435, 0.498731", \ "0.552667, 0.583829, 0.653592, 0.70967, 0.903657", \ "1.06958, 1.09964, 1.16529, 1.2172, 1.40202"); } rise_transition(delay_template_5x5) { index_1 ("0.2, 0.4, 0.8, 2.4, 4.8"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0792, 0.1074, 0.1614, 0.1956, 0.2946", \ "0.1374, 0.1542, 0.2106, 0.2514, 0.3714", \ "0.2664, 0.2694, 0.309, 0.3504, 0.4878", \ "0.78, 0.7806, 0.7812, 0.7944, 0.8934", \ "1.5522, 1.5522, 1.5522, 1.5522, 1.5804"); } } internal_power() { related_pin : "A"; fall_power(energy_template_5x5) { index_1 ("0.2, 0.4, 0.8, 2.4, 4.8"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "1.18856, 0.687522, 0.931866, 2.34586, 7.35409", \ "1.12762, 0.8053, 0.519523, 1.75634, 6.41975", \ "1.0887, 0.899197, 0.087692, 1.09265, 5.15709", \ "1.04486, 0.968386, 0.470118, 0.120417, 2.87202", \ "1.03179, 0.9942, 0.702633, 0.329449, 1.5684"); } rise_power(energy_template_5x5) { index_1 ("0.2, 0.4, 0.8, 2.4, 4.8"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "2.68312, 3.31465, 5.09101, 6.57672, 11.7145", \ "2.72583, 3.15594, 4.68403, 6.04246, 10.9588", \ "2.71399, 3.01051, 4.22362, 5.38413, 9.86036", \ "2.80139, 2.88521, 3.55404, 4.29145, 7.57425", \ "2.8149, 2.84947, 3.25189, 3.73503, 6.10429"); } } } } /* -------------- * * Design : LATCH * * -------------- */ cell (LATCH) { area : 0; cell_leakage_power : 0.146615; latch (DS0000,P0000) { data_in : "D"; enable : "CLK"; } pin(CLK) { direction : input; capacitance : 0.0401037; rise_capacitance : 0.0397447; fall_capacitance : 0.0401037; clock : true; internal_power() { rise_power(passive_energy_template_6x1) { index_1 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ("0.193438, 0.165402, 0.65935, 1.5762, 2.23319, 3.5649"); } fall_power(passive_energy_template_6x1) { index_1 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ("0.815049, 1.19899, 1.70796, 2.63134, 3.28239, 4.62648"); } } min_pulse_width_high : 0.241222; } pin(D) { direction : input; capacitance : 0.0156832; rise_capacitance : 0.0156025; fall_capacitance : 0.0156832; timing() { related_pin : "CLK"; timing_type : hold_falling; rise_constraint(hold_template_3x6) { index_1 ("0.06, 0.3, 0.6"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "-0.1875, -0.225, -0.2125, -0.2375, -0.26875, -0.33125", \ "-0.2, -0.2375, -0.225, -0.25, -0.28125, -0.34375", \ "-0.2625, -0.3, -0.2875, -0.3125, -0.34375, -0.40625"); } fall_constraint(hold_template_3x6) { index_1 ("0.06, 0.3, 0.6"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "-0.09375, -0.13125, -0.2125, -0.2375, -0.26875, -0.33125", \ "-0.10625, -0.14375, -0.225, -0.25, -0.28125, -0.34375", \ "-0.075, -0.1125, -0.19375, -0.21875, -0.25, -0.3125"); } } timing() { related_pin : "CLK"; timing_type : setup_falling; rise_constraint(setup_template_3x6) { index_1 ("0.06, 0.3, 0.6"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.375, 0.31875, 0.4, 0.425, 0.45625, 0.51875", \ "0.3875, 0.425, 0.4125, 0.53125, 0.46875, 0.53125", \ "0.54375, 0.58125, 0.56875, 0.59375, 0.625, 0.6875"); } fall_constraint(setup_template_3x6) { index_1 ("0.06, 0.3, 0.6"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.28125, 0.31875, 0.4, 0.425, 0.45625, 0.70625", \ "0.29375, 0.33125, 0.31875, 0.4375, 0.46875, 0.90625", \ "0.2625, 0.3, 0.38125, 0.40625, 0.4375, 0.5"); } } } pin(Q) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.91041; function : "DS0000"; timing() { related_pin : "CLK"; timing_sense : non_unate; timing_type : rising_edge; cell_rise(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.291301, 0.32078, 0.342027, 0.347863, 0.339451, 0.303421", \ "0.646975, 0.674914, 0.694966, 0.701023, 0.69405, 0.661067", \ "1.24933, 1.27683, 1.29581, 1.30048, 1.29346, 1.26177", \ "2.79945, 2.82619, 2.84465, 2.84814, 2.8397, 2.80717", \ "3.66088, 3.68775, 3.70634, 3.70949, 3.70027, 3.66754", \ "4.52221, 4.54896, 4.56661, 4.57043, 4.56101, 4.52707"); } rise_transition(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.1884, 0.1878, 0.1974, 0.2112, 0.2226, 0.2418", \ "0.6786, 0.6792, 0.6804, 0.687, 0.693, 0.7056", \ "1.575, 1.5744, 1.5744, 1.5768, 1.5792, 1.587", \ "3.8904, 3.8898, 3.8904, 3.8904, 3.8904, 3.8922", \ "5.1774, 5.178, 5.1774, 5.1774, 5.1768, 5.178", \ "6.4644, 6.465, 6.4638, 6.4644, 6.4638, 6.4632"); } cell_fall(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.379079, 0.391961, 0.41014, 0.422903, 0.425332, 0.425441", \ "0.782119, 0.795156, 0.812043, 0.824891, 0.827695, 0.830193", \ "1.46913, 1.48207, 1.49897, 1.51176, 1.51435, 1.51685", \ "3.23611, 3.24895, 3.26596, 3.27859, 3.28103, 3.28352", \ "4.21781, 4.23045, 4.24743, 4.26004, 4.26322, 4.26544", \ "5.19881, 5.21215, 5.22888, 5.24209, 5.2444, 5.24694"); } fall_transition(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.1908, 0.1896, 0.1884, 0.1884, 0.1896, 0.1908", \ "0.678, 0.678, 0.6774, 0.678, 0.678, 0.6804", \ "1.5762, 1.5762, 1.5762, 1.5762, 1.5756, 1.5756", \ "3.8982, 3.8982, 3.8976, 3.8982, 3.8982, 3.8964", \ "5.1882, 5.1882, 5.1876, 5.1882, 5.1882, 5.1882", \ "6.4776, 6.4782, 6.4776, 6.4776, 6.4782, 6.4776"); } } timing() { related_pin : "D"; timing_sense : positive_unate; cell_rise(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.354606, 0.369426, 0.398928, 0.44665, 0.474528, 0.519339", \ "0.709096, 0.7223, 0.751269, 0.799278, 0.830235, 0.88482", \ "1.31115, 1.32454, 1.35231, 1.39933, 1.42915, 1.48391", \ "2.86088, 2.87387, 2.90179, 2.94691, 2.97606, 3.02874", \ "3.7227, 3.7356, 3.76311, 3.80834, 3.83708, 3.88908", \ "4.58306, 4.59603, 4.6244, 4.66928, 4.69766, 4.74965"); } rise_transition(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.189, 0.1896, 0.1938, 0.2082, 0.2178, 0.2394", \ "0.6786, 0.6786, 0.6798, 0.6846, 0.6906, 0.7086", \ "1.575, 1.5744, 1.575, 1.5756, 1.5774, 1.584", \ "3.891, 3.891, 3.8898, 3.891, 3.8904, 3.8916", \ "5.178, 5.1774, 5.1774, 5.178, 5.178, 5.1774", \ "6.4632, 6.4632, 6.4644, 6.4644, 6.4644, 6.465"); } cell_fall(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.367567, 0.389291, 0.430695, 0.4994, 0.54195, 0.616616", \ "0.770446, 0.791195, 0.830828, 0.899334, 0.945189, 1.03121", \ "1.45725, 1.47759, 1.51619, 1.58196, 1.62616, 1.71014", \ "3.22413, 3.24426, 3.28242, 3.34641, 3.38892, 3.46949", \ "4.20588, 4.22571, 4.26385, 4.32772, 4.37005, 4.44994", \ "5.18692, 5.20804, 5.24524, 5.30932, 5.35142, 5.43092"); } fall_transition(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.1902, 0.1914, 0.195, 0.2136, 0.2292, 0.2544", \ "0.678, 0.6774, 0.6786, 0.684, 0.69, 0.7104", \ "1.5762, 1.5762, 1.5762, 1.5768, 1.578, 1.5828", \ "3.8982, 3.8976, 3.8976, 3.8982, 3.897, 3.8976", \ "5.1876, 5.1876, 5.187, 5.1882, 5.1882, 5.1876", \ "6.4776, 6.477, 6.4782, 6.477, 6.4776, 6.477"); } } internal_power() { related_pin : "CLK"; rise_power(energy_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.601528, 1.01688, 1.67541, 2.89355, 3.75382, 5.46027", \ "0.534357, 0.921882, 1.53432, 2.65395, 3.47241, 5.13839", \ "0.515107, 0.894256, 1.4905, 2.58412, 3.37792, 4.99502", \ "0.504143, 0.878623, 1.46853, 2.54441, 3.32586, 4.91182", \ "0.502197, 0.875852, 1.46428, 2.53732, 3.31627, 4.89575", \ "0.500972, 0.873732, 1.46176, 2.53284, 3.31017, 4.88586"); } fall_power(energy_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.7916, 1.12174, 1.63632, 2.57109, 3.23991, 4.60126", \ "0.74397, 1.07473, 1.58647, 2.52084, 3.18529, 4.53824", \ "0.733409, 1.06379, 1.57629, 2.508, 3.17412, 4.52676", \ "0.728217, 1.05901, 1.57145, 2.5028, 3.16976, 4.52166", \ "0.727374, 1.05818, 1.57045, 2.50202, 3.169, 4.52075", \ "0.726946, 1.05798, 1.5702, 2.50171, 3.16869, 4.52022"); } } internal_power() { related_pin : "D"; rise_power(energy_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.790516, 0.866641, 1.06516, 1.5261, 1.88035, 2.62344", \ "0.712004, 0.769635, 0.930933, 1.30515, 1.60171, 2.2273", \ "0.689773, 0.744433, 0.89421, 1.23441, 1.5031, 2.07095", \ "0.67732, 0.73019, 0.874107, 1.19594, 1.4474, 1.97575", \ "0.673663, 0.727513, 0.870447, 1.18859, 1.43698, 1.95719", \ "0.673472, 0.725778, 0.868071, 1.18416, 1.43022, 1.94545"); } fall_power(energy_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "1.38475, 1.44701, 1.64764, 2.12154, 2.48645, 3.23743", \ "1.33332, 1.37809, 1.53994, 1.92002, 2.22021, 2.84977", \ "1.32031, 1.36168, 1.51179, 1.85918, 2.13142, 2.70347", \ "1.31342, 1.35312, 1.49833, 1.82668, 2.08289, 2.61677", \ "1.31214, 1.35169, 1.49586, 1.82122, 2.07394, 2.60061", \ "1.31129, 1.35083, 1.49418, 1.81739, 2.06847, 2.58979"); } } } } /* --------------- * * Design : MUX2X1 * * --------------- */ cell (MUX2X1) { area : 432; cell_leakage_power : 0.130158; pin(A) { direction : input; capacitance : 0.0322422; rise_capacitance : 0.0321228; fall_capacitance : 0.0322422; } pin(B) { direction : input; capacitance : 0.032256; rise_capacitance : 0.0320934; fall_capacitance : 0.032256; } pin(S) { direction : input; capacitance : 0.0364492; rise_capacitance : 0.0364492; fall_capacitance : 0.0363017; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.464852; function : "(!((S A) + (!S B)))"; timing() { related_pin : "A"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.105022, 0.114182, 0.124989, 0.129021, 0.129458", \ "0.146777, 0.152307, 0.168306, 0.176412, 0.18675", \ "0.222752, 0.226783, 0.244827, 0.258479, 0.285894", \ "0.519329, 0.521995, 0.531957, 0.545988, 0.600255", \ "0.965011, 0.962082, 0.966391, 0.974788, 1.02143"); } fall_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1236, 0.1446, 0.2076, 0.2586, 0.423", \ "0.1758, 0.186, 0.243, 0.291, 0.4626", \ "0.279, 0.2832, 0.321, 0.3648, 0.534", \ "0.6972, 0.6966, 0.7032, 0.7176, 0.828", \ "1.3266, 1.3266, 1.3266, 1.3296, 1.3698"); } cell_rise(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.130958, 0.139119, 0.175824, 0.200499, 0.271386", \ "0.174051, 0.183988, 0.221588, 0.249937, 0.331466", \ "0.254152, 0.264167, 0.302725, 0.335809, 0.43441", \ "0.576168, 0.58317, 0.613403, 0.6443, 0.7639", \ "1.05777, 1.06373, 1.08794, 1.11216, 1.21655"); } rise_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1296, 0.1464, 0.2082, 0.2586, 0.42", \ "0.1914, 0.1992, 0.249, 0.297, 0.4662", \ "0.312, 0.3156, 0.3474, 0.3882, 0.5502", \ "0.8022, 0.8022, 0.8064, 0.8196, 0.9144", \ "1.5366, 1.5372, 1.5366, 1.5378, 1.5726"); } } timing() { related_pin : "B"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.117626, 0.120695, 0.128507, 0.131738, 0.130251", \ "0.15653, 0.16032, 0.172513, 0.179427, 0.187951", \ "0.232048, 0.234017, 0.24932, 0.261955, 0.287551", \ "0.527174, 0.52772, 0.536444, 0.549891, 0.602741", \ "0.967861, 0.967464, 0.970992, 0.978928, 1.02474"); } fall_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1224, 0.1404, 0.2034, 0.2544, 0.4188", \ "0.174, 0.1854, 0.24, 0.288, 0.4596", \ "0.2778, 0.2826, 0.3198, 0.363, 0.5322", \ "0.6984, 0.6984, 0.705, 0.7194, 0.8292", \ "1.329, 1.329, 1.329, 1.332, 1.3722"); } cell_rise(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.118089, 0.135902, 0.172866, 0.197943, 0.27024", \ "0.160615, 0.176502, 0.217853, 0.247005, 0.329431", \ "0.242046, 0.255367, 0.298509, 0.332331, 0.43177", \ "0.564527, 0.575469, 0.607827, 0.639446, 0.760217", \ "1.04584, 1.05694, 1.08196, 1.10653, 1.21181"); } rise_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1266, 0.1482, 0.2094, 0.2592, 0.4194", \ "0.1884, 0.1962, 0.2496, 0.2988, 0.4668", \ "0.3096, 0.3126, 0.3456, 0.387, 0.549", \ "0.798, 0.798, 0.8022, 0.8148, 0.9114", \ "1.5324, 1.5318, 1.5318, 1.533, 1.5672"); } } timing() { related_pin : "S"; timing_sense : non_unate; cell_rise(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.205605, 0.228528, 0.270885, 0.297854, 0.359734", \ "0.247448, 0.268651, 0.309325, 0.33701, 0.400235", \ "0.321959, 0.345702, 0.386142, 0.413561, 0.479882", \ "0.638469, 0.660483, 0.701132, 0.725056, 0.789407", \ "1.11619, 1.13893, 1.17885, 1.20221, 1.2613"); } rise_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1338, 0.1368, 0.1314, 0.1356, 0.147", \ "0.1908, 0.195, 0.1938, 0.1908, 0.1968", \ "0.3126, 0.3126, 0.3108, 0.3072, 0.3114", \ "0.8016, 0.8022, 0.8022, 0.7986, 0.7944", \ "1.5372, 1.5366, 1.5372, 1.5372, 1.5312"); } cell_fall(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.199127, 0.227798, 0.28355, 0.318118, 0.400501", \ "0.233998, 0.265858, 0.320444, 0.355834, 0.441001", \ "0.305293, 0.335585, 0.388706, 0.424947, 0.516132", \ "0.590378, 0.624025, 0.676171, 0.707555, 0.798168", \ "1.02862, 1.06062, 1.1121, 1.14263, 1.22582"); } fall_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1284, 0.1308, 0.1248, 0.1242, 0.1356", \ "0.18, 0.183, 0.177, 0.174, 0.18", \ "0.2802, 0.2814, 0.2766, 0.2736, 0.279", \ "0.6984, 0.6984, 0.699, 0.6936, 0.6888", \ "1.329, 1.329, 1.329, 1.329, 1.3212"); } } internal_power() { related_pin : "A"; fall_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.301854, 0.220605, 0.132525, 0.447181, 1.58454", \ "0.297387, 0.238422, 0.066906, 0.354321, 1.44104", \ "0.29347, 0.250154, 0.012574, 0.231273, 1.218", \ "0.288635, 0.269346, 0.135522, 0.020126, 0.732909", \ "0.287609, 0.277253, 0.1941, 0.090698, 0.422579"); } rise_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "1.3268, 1.37409, 1.75491, 2.08088, 3.24873", \ "1.33006, 1.38944, 1.69575, 1.99823, 3.12574", \ "1.33637, 1.37756, 1.62317, 1.8838, 2.9238", \ "1.34058, 1.36142, 1.50389, 1.67466, 2.46003", \ "1.34247, 1.35526, 1.44467, 1.55873, 2.14008"); } } internal_power() { related_pin : "B"; fall_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.041837, 0.025574, 0.370451, 0.683242, 1.82212", \ "0.037489, 0.015348, 0.308239, 0.593812, 1.6802", \ "0.033242, 0.000169, 0.23312, 0.475141, 1.45999", \ "0.028331, 0.017288, 0.11394, 0.26879, 0.980621", \ "0.026551, 0.024341, 0.056827, 0.159342, 0.672331"); } rise_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "1.08087, 1.13483, 1.51327, 1.84087, 3.00743", \ "1.08691, 1.13195, 1.45222, 1.753, 2.88197", \ "1.06952, 1.12094, 1.37592, 1.6357, 2.67925", \ "1.07825, 1.112, 1.24982, 1.42363, 2.21222", \ "1.07987, 1.0941, 1.18942, 1.30678, 1.89111"); } } internal_power() { related_pin : "S"; rise_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.700972, 0.749398, 0.923832, 1.094, 1.72264", \ "0.684326, 0.724693, 0.908085, 1.07523, 1.68301", \ "0.649549, 0.691535, 0.885821, 1.05182, 1.63999", \ "0.584662, 0.643173, 0.831085, 0.994073, 1.57425", \ "0.55897, 0.615667, 0.801554, 0.961577, 1.52921"); } fall_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "1.25833, 1.31326, 1.52653, 1.70275, 2.33861", \ "1.22713, 1.29251, 1.50315, 1.67989, 2.30043", \ "1.19392, 1.25487, 1.46515, 1.64259, 2.25808", \ "1.12307, 1.18267, 1.39451, 1.57115, 2.16938", \ "1.08727, 1.15187, 1.35747, 1.52489, 2.11147"); } } } } /* ---------------- * * Design : NAND2X1 * * ---------------- */ cell (NAND2X1) { area : 216; cell_leakage_power : 0.0551262; pin(A) { direction : input; capacitance : 0.0214197; rise_capacitance : 0.0214197; fall_capacitance : 0.0213977; } pin(B) { direction : input; capacitance : 0.0216455; rise_capacitance : 0.0215843; fall_capacitance : 0.0216455; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.437228; function : "(!(A B))"; timing() { related_pin : "A"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.071061, 0.070113, 0.052678, 0.034071, -0.042334", \ "0.108132, 0.112469, 0.10616, 0.093963, 0.032786", \ "0.182732, 0.186017, 0.19129, 0.18965, 0.156031", \ "0.476185, 0.477706, 0.483851, 0.492027, 0.51122", \ "0.92129, 0.917058, 0.919376, 0.923971, 0.950878"); } fall_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0762, 0.1068, 0.1596, 0.2034, 0.3222", \ "0.1242, 0.1422, 0.1956, 0.24, 0.375", \ "0.2286, 0.2352, 0.2766, 0.318, 0.4626", \ "0.6474, 0.6468, 0.6546, 0.6714, 0.7818", \ "1.278, 1.278, 1.278, 1.2816, 1.326"); } cell_rise(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.103824, 0.146211, 0.22309, 0.275582, 0.435527", \ "0.149608, 0.189555, 0.274068, 0.331723, 0.507857", \ "0.240087, 0.275933, 0.362515, 0.427581, 0.623913", \ "0.600941, 0.63278, 0.707193, 0.768494, 0.99041", \ "1.14129, 1.17193, 1.24021, 1.29582, 1.49728"); } rise_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1092, 0.1254, 0.1788, 0.213, 0.3252", \ "0.174, 0.1848, 0.228, 0.2676, 0.39", \ "0.309, 0.3084, 0.3366, 0.3708, 0.4974", \ "0.8454, 0.8454, 0.8454, 0.8532, 0.9282", \ "1.6518, 1.6512, 1.6512, 1.6512, 1.6686"); } } timing() { related_pin : "B"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.071875, 0.082705, 0.083365, 0.077777, 0.043041", \ "0.107939, 0.129629, 0.144592, 0.147656, 0.132204", \ "0.183139, 0.202172, 0.240275, 0.256063, 0.272306", \ "0.476291, 0.494387, 0.537527, 0.573135, 0.668724", \ "0.916416, 0.933768, 0.973253, 1.00523, 1.12261"); } fall_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0756, 0.105, 0.162, 0.1998, 0.315", \ "0.1218, 0.1452, 0.2088, 0.249, 0.3828", \ "0.228, 0.237, 0.2916, 0.3366, 0.4848", \ "0.6468, 0.6474, 0.6564, 0.6834, 0.8244", \ "1.278, 1.278, 1.278, 1.2798, 1.3524"); } cell_rise(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.092157, 0.129001, 0.190913, 0.23225, 0.353029", \ "0.138796, 0.175046, 0.250101, 0.299209, 0.44027", \ "0.229497, 0.263007, 0.345624, 0.404387, 0.574901", \ "0.591846, 0.622248, 0.694391, 0.753405, 0.966014", \ "1.1327, 1.16244, 1.22942, 1.28322, 1.47954"); } rise_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0852, 0.1068, 0.156, 0.192, 0.2928", \ "0.1512, 0.1608, 0.2088, 0.2466, 0.3654", \ "0.2832, 0.285, 0.3144, 0.3516, 0.4788", \ "0.8202, 0.8196, 0.8202, 0.8286, 0.909", \ "1.626, 1.626, 1.626, 1.626, 1.6446"); } } internal_power() { related_pin : "A"; fall_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.149175, 0.07742, 0.188134, 0.417963, 1.23562", \ "0.141018, 0.089689, 0.129356, 0.335138, 1.10549", \ "0.13489, 0.102498, 0.066249, 0.236539, 0.920574", \ "0.129655, 0.114867, 0.021891, 0.084556, 0.565404", \ "0.129489, 0.120371, 0.062778, 0.008159, 0.354296"); } rise_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.595007, 0.691005, 0.972361, 1.21134, 2.04367", \ "0.599546, 0.673513, 0.916588, 1.13763, 1.94051", \ "0.603852, 0.645761, 0.846255, 1.03784, 1.77788", \ "0.614357, 0.629162, 0.738157, 0.860189, 1.40868", \ "0.616042, 0.623842, 0.688453, 0.767739, 1.16141"); } } internal_power() { related_pin : "B"; fall_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.146214, 0.072766, 0.166251, 0.371609, 1.09952", \ "0.139294, 0.088083, 0.107823, 0.290841, 0.973342", \ "0.134453, 0.101816, 0.047742, 0.196758, 0.797024", \ "0.129929, 0.115514, 0.035851, 0.055185, 0.469246", \ "0.128548, 0.121075, 0.072743, 0.013593, 0.278599"); } rise_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.431685, 0.509648, 0.764655, 0.978372, 1.72233", \ "0.447514, 0.498831, 0.715533, 0.912684, 1.62662", \ "0.45785, 0.485817, 0.657954, 0.827125, 1.48187", \ "0.48057, 0.484868, 0.576647, 0.683842, 1.1699", \ "0.486373, 0.486922, 0.541572, 0.611509, 0.9641"); } } } } /* ---------------- * * Design : NAND3X1 * * ---------------- */ cell (NAND3X1) { area : 324; cell_leakage_power : 0.0798204; pin(A) { direction : input; capacitance : 0.0268969; rise_capacitance : 0.0268969; fall_capacitance : 0.0267882; } pin(B) { direction : input; capacitance : 0.0268552; rise_capacitance : 0.0268552; fall_capacitance : 0.0268206; } pin(C) { direction : input; capacitance : 0.0271539; rise_capacitance : 0.027089; fall_capacitance : 0.0271539; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.416025; function : "(!((A B) C))"; timing() { related_pin : "A"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.078129, 0.068111, 0.028567, -0.005328, -0.133459", \ "0.113182, 0.102431, 0.071696, 0.042599, -0.073843", \ "0.176082, 0.165756, 0.143916, 0.122483, 0.027114", \ "0.429946, 0.417186, 0.397459, 0.385149, 0.333998", \ "0.808375, 0.795712, 0.771353, 0.756847, 0.717769"); } fall_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0798, 0.1116, 0.165, 0.2064, 0.339", \ "0.1266, 0.1434, 0.1992, 0.2412, 0.378", \ "0.222, 0.228, 0.27, 0.3084, 0.4524", \ "0.6, 0.6006, 0.6108, 0.63, 0.7392", \ "1.1694, 1.1694, 1.1712, 1.176, 1.2318"); } cell_rise(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.145957, 0.188451, 0.283441, 0.352235, 0.567895", \ "0.192486, 0.232245, 0.327561, 0.398451, 0.623682", \ "0.283846, 0.319269, 0.40983, 0.484174, 0.720393", \ "0.646037, 0.677736, 0.754242, 0.818722, 1.05662", \ "1.18661, 1.21653, 1.28669, 1.34441, 1.55721"); } rise_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1638, 0.1752, 0.2172, 0.252, 0.3708", \ "0.2316, 0.2328, 0.2694, 0.3054, 0.4254", \ "0.3654, 0.366, 0.3852, 0.4122, 0.5292", \ "0.9036, 0.9036, 0.9042, 0.9084, 0.9684", \ "1.7106, 1.7106, 1.7106, 1.7106, 1.722"); } } timing() { related_pin : "B"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.076387, 0.072643, 0.050601, 0.029015, -0.060984", \ "0.106865, 0.108692, 0.099403, 0.083484, 0.008872", \ "0.172115, 0.175281, 0.17862, 0.173023, 0.123517", \ "0.425812, 0.426242, 0.436938, 0.446201, 0.457852", \ "0.80403, 0.804366, 0.811038, 0.818798, 0.851276"); } fall_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0858, 0.1224, 0.177, 0.2184, 0.348", \ "0.129, 0.1494, 0.2088, 0.2532, 0.3942", \ "0.2208, 0.2334, 0.2826, 0.3252, 0.474", \ "0.6, 0.6006, 0.6144, 0.6384, 0.7656", \ "1.1694, 1.1694, 1.1706, 1.1772, 1.2438"); } cell_rise(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.126844, 0.166561, 0.252964, 0.312741, 0.494425", \ "0.173525, 0.211798, 0.300763, 0.364724, 0.56113", \ "0.264376, 0.29975, 0.386827, 0.456426, 0.670746", \ "0.62749, 0.658366, 0.733236, 0.795739, 1.02592", \ "1.16819, 1.19826, 1.26672, 1.32323, 1.53137"); } rise_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1284, 0.138, 0.1842, 0.2202, 0.3294", \ "0.1944, 0.198, 0.2388, 0.2736, 0.3912", \ "0.3288, 0.3282, 0.351, 0.3792, 0.498", \ "0.8658, 0.8658, 0.8658, 0.8706, 0.936", \ "1.6716, 1.6716, 1.6716, 1.6716, 1.6848"); } } timing() { related_pin : "C"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.065013, 0.07004, 0.06139, 0.04602, -0.019095", \ "0.098855, 0.114379, 0.116858, 0.110203, 0.06373", \ "0.162166, 0.18076, 0.20436, 0.210204, 0.19395", \ "0.414442, 0.430888, 0.469878, 0.501031, 0.561677", \ "0.792885, 0.808095, 0.843839, 0.873016, 0.977012"); } fall_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0846, 0.1182, 0.1686, 0.2058, 0.3216", \ "0.1248, 0.1548, 0.2094, 0.252, 0.3858", \ "0.222, 0.2328, 0.2904, 0.3336, 0.48", \ "0.5994, 0.6, 0.6168, 0.6492, 0.795", \ "1.1694, 1.1694, 1.1694, 1.1766, 1.2708"); } cell_rise(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.101279, 0.142771, 0.214184, 0.263004, 0.410015", \ "0.150493, 0.1882, 0.269212, 0.324764, 0.49137", \ "0.243085, 0.276568, 0.361191, 0.425575, 0.618138", \ "0.608091, 0.637998, 0.710608, 0.771628, 0.994313", \ "1.14963, 1.17918, 1.24616, 1.30168, 1.50443"); } rise_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0882, 0.1068, 0.156, 0.1848, 0.2856", \ "0.1548, 0.1638, 0.2058, 0.2418, 0.3558", \ "0.2898, 0.2892, 0.315, 0.345, 0.4674", \ "0.8256, 0.8262, 0.8256, 0.8316, 0.9036", \ "1.632, 1.6314, 1.6314, 1.6314, 1.6464"); } } internal_power() { related_pin : "A"; fall_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.154531, 0.097534, 0.198471, 0.461689, 1.41633", \ "0.146332, 0.104474, 0.147417, 0.385269, 1.29092", \ "0.138548, 0.105627, 0.088378, 0.290486, 1.10833", \ "0.130541, 0.116521, 0.00214, 0.130794, 0.732379", \ "0.128439, 0.124003, 0.047452, 0.044401, 0.491652"); } rise_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "1.08638, 1.1792, 1.48487, 1.75762, 2.72857", \ "1.09187, 1.1663, 1.43434, 1.69095, 2.62799", \ "1.09918, 1.14101, 1.36719, 1.58987, 2.46174", \ "1.11546, 1.12937, 1.25308, 1.39762, 2.05637", \ "1.11898, 1.12332, 1.19734, 1.2927, 1.76901"); } } internal_power() { related_pin : "B"; fall_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.148827, 0.076785, 0.202019, 0.446138, 1.31995", \ "0.142904, 0.089085, 0.144659, 0.364707, 1.19071", \ "0.13563, 0.09927, 0.080573, 0.265231, 1.0034", \ "0.131159, 0.114791, 0.011233, 0.105825, 0.632861", \ "0.128968, 0.119688, 0.055301, 0.02356, 0.406512"); } rise_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.822929, 0.899906, 1.19354, 1.4454, 2.33276", \ "0.838464, 0.901889, 1.14633, 1.38044, 2.23927", \ "0.852348, 0.888251, 1.08543, 1.2903, 2.08712", \ "0.873343, 0.882302, 0.991594, 1.12361, 1.72558", \ "0.877704, 0.883198, 0.947463, 1.0344, 1.47303"); } } internal_power() { related_pin : "C"; fall_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.138901, 0.058894, 0.211725, 0.441809, 1.2572", \ "0.138196, 0.073333, 0.150705, 0.357026, 1.12583", \ "0.133117, 0.091014, 0.082059, 0.254358, 0.938112", \ "0.129248, 0.109929, 0.013198, 0.094318, 0.575759", \ "0.12805, 0.117711, 0.057698, 0.013689, 0.359219"); } rise_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.536545, 0.620185, 0.894649, 1.13091, 1.96028", \ "0.565005, 0.620168, 0.848997, 1.06808, 1.86612", \ "0.588406, 0.609006, 0.795581, 0.984722, 1.72078", \ "0.624626, 0.625973, 0.721582, 0.841673, 1.39533", \ "0.635753, 0.635924, 0.69156, 0.770083, 1.17411"); } } } } /* --------------- * * Design : NOR2X1 * * --------------- */ cell (NOR2X1) { area : 216; cell_leakage_power : 0.0509603; pin(A) { direction : input; capacitance : 0.0270218; rise_capacitance : 0.026769; fall_capacitance : 0.0270218; } pin(B) { direction : input; capacitance : 0.0276513; rise_capacitance : 0.0276513; fall_capacitance : 0.0276084; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.393161; function : "(!(A+B))"; timing() { related_pin : "A"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.150074, 0.177605, 0.240576, 0.281574, 0.4057", \ "0.205882, 0.233431, 0.30009, 0.345764, 0.481277", \ "0.318018, 0.343679, 0.406984, 0.459769, 0.612545", \ "0.763675, 0.784143, 0.837418, 0.882577, 1.05397", \ "1.42651, 1.44647, 1.49447, 1.53448, 1.68449"); } fall_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1416, 0.1512, 0.2028, 0.2406, 0.357", \ "0.213, 0.2148, 0.2556, 0.2982, 0.4218", \ "0.357, 0.3576, 0.378, 0.4098, 0.5394", \ "0.936, 0.936, 0.936, 0.9396, 1.008", \ "1.8042, 1.8048, 1.8048, 1.8042, 1.815"); } cell_rise(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.093471, 0.105246, 0.10909, 0.106691, 0.084397", \ "0.135596, 0.148646, 0.163368, 0.167984, 0.162752", \ "0.215973, 0.229543, 0.253866, 0.268057, 0.288828", \ "0.539577, 0.548619, 0.573407, 0.595469, 0.665399", \ "1.02087, 1.03022, 1.0504, 1.06907, 1.14299"); } rise_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0912, 0.1164, 0.1722, 0.21, 0.3258", \ "0.153, 0.1656, 0.2178, 0.2586, 0.3834", \ "0.2736, 0.2784, 0.315, 0.3534, 0.486", \ "0.7626, 0.7632, 0.7692, 0.783, 0.876", \ "1.4976, 1.497, 1.497, 1.4988, 1.5378"); } } timing() { related_pin : "B"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.116136, 0.141213, 0.184506, 0.212926, 0.287939", \ "0.175024, 0.198472, 0.255186, 0.289615, 0.386509", \ "0.288906, 0.310984, 0.370468, 0.416167, 0.540884", \ "0.737669, 0.75684, 0.805762, 0.848772, 1.01158", \ "1.40149, 1.42102, 1.46645, 1.50461, 1.64837"); } fall_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.093, 0.105, 0.153, 0.1872, 0.2886", \ "0.1626, 0.1668, 0.2124, 0.249, 0.3684", \ "0.3048, 0.3054, 0.3294, 0.3648, 0.492", \ "0.8832, 0.8832, 0.8832, 0.8874, 0.9618", \ "1.7514, 1.7514, 1.7514, 1.7514, 1.7628"); } cell_rise(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.086072, 0.106592, 0.132203, 0.145177, 0.168482", \ "0.126215, 0.154476, 0.194422, 0.216541, 0.262564", \ "0.205216, 0.234739, 0.292908, 0.32624, 0.40648", \ "0.52802, 0.553487, 0.611772, 0.658779, 0.809342", \ "1.00913, 1.03421, 1.08875, 1.13241, 1.28828"); } rise_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0924, 0.1236, 0.1734, 0.2082, 0.3048", \ "0.153, 0.168, 0.228, 0.2646, 0.3822", \ "0.2742, 0.2772, 0.3234, 0.3672, 0.4992", \ "0.7632, 0.7626, 0.7668, 0.7854, 0.8976", \ "1.497, 1.4976, 1.4976, 1.4976, 1.5426"); } } internal_power() { related_pin : "A"; fall_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.298395, 0.261452, 0.062218, 0.119597, 0.791788", \ "0.298898, 0.267185, 0.103201, 0.061582, 0.694768", \ "0.294136, 0.274582, 0.151168, 0.015105, 0.549481", \ "0.287209, 0.28202, 0.219175, 0.138648, 0.250443", \ "0.285074, 0.283287, 0.247904, 0.197623, 0.069121"); } rise_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.996171, 1.02306, 1.2442, 1.43437, 2.13215", \ "1.00259, 1.01693, 1.20831, 1.37907, 2.04072", \ "1.00845, 1.02149, 1.16558, 1.30975, 1.91047", \ "1.00428, 1.01698, 1.09307, 1.19261, 1.64057", \ "1.00569, 1.0055, 1.06035, 1.12826, 1.46238"); } } internal_power() { related_pin : "B"; fall_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.285912, 0.245194, 0.058754, 0.111418, 0.729936", \ "0.253157, 0.236317, 0.092462, 0.056827, 0.632515", \ "0.224935, 0.227801, 0.126156, 0.006333, 0.498582", \ "0.199564, 0.202468, 0.159621, 0.092763, 0.248633", \ "0.191115, 0.192758, 0.169449, 0.128861, 0.104685"); } rise_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.605996, 0.665924, 0.893344, 1.07356, 1.71228", \ "0.611981, 0.659276, 0.846355, 1.01277, 1.6198", \ "0.620342, 0.650074, 0.79521, 0.935203, 1.48451", \ "0.630236, 0.641971, 0.72128, 0.810149, 1.20997", \ "0.632785, 0.638606, 0.687759, 0.746283, 1.03558"); } } } } /* --------------- * * Design : NOR3X1 * * --------------- */ cell (NOR3X1) { area : 576; cell_leakage_power : 0.13516; pin(A) { direction : input; capacitance : 0.0376635; rise_capacitance : 0.0372401; fall_capacitance : 0.0376635; } pin(B) { direction : input; capacitance : 0.0375667; rise_capacitance : 0.0373598; fall_capacitance : 0.0375667; } pin(C) { direction : input; capacitance : 0.0386539; rise_capacitance : 0.0386539; fall_capacitance : 0.0385214; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.357419; function : "(!((A+B)+C))"; timing() { related_pin : "A"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.240857, 0.263963, 0.335706, 0.39084, 0.560112", \ "0.301169, 0.323387, 0.391001, 0.448426, 0.623399", \ "0.415679, 0.437797, 0.499929, 0.554948, 0.740299", \ "0.866844, 0.884749, 0.937853, 0.983583, 1.16052", \ "1.53191, 1.55075, 1.59813, 1.63857, 1.79265"); } fall_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.2358, 0.2376, 0.2706, 0.306, 0.4338", \ "0.3108, 0.312, 0.3336, 0.3666, 0.4938", \ "0.4584, 0.459, 0.4686, 0.4914, 0.6102", \ "1.0416, 1.0422, 1.0422, 1.0434, 1.0956", \ "1.9122, 1.9122, 1.9116, 1.9116, 1.9182"); } cell_rise(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.134381, 0.136225, 0.126988, 0.113227, 0.053218", \ "0.172608, 0.178187, 0.175799, 0.167924, 0.120676", \ "0.254115, 0.258307, 0.262792, 0.262444, 0.235626", \ "0.574303, 0.579267, 0.583494, 0.588047, 0.602523", \ "1.05472, 1.06149, 1.06064, 1.06147, 1.07921"); } rise_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.126, 0.1416, 0.1902, 0.2298, 0.3624", \ "0.1854, 0.1914, 0.234, 0.273, 0.4098", \ "0.306, 0.3084, 0.3372, 0.3714, 0.5052", \ "0.795, 0.795, 0.801, 0.8136, 0.9018", \ "1.5294, 1.5294, 1.53, 1.5324, 1.5702"); } } timing() { related_pin : "B"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.202035, 0.223278, 0.288279, 0.333265, 0.467918", \ "0.261096, 0.280861, 0.346233, 0.39479, 0.540557", \ "0.375164, 0.393594, 0.453559, 0.506537, 0.667992", \ "0.82061, 0.839283, 0.890117, 0.934059, 1.10457", \ "1.48433, 1.5039, 1.55012, 1.58932, 1.73912"); } fall_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1692, 0.1716, 0.2124, 0.249, 0.3606", \ "0.2424, 0.2412, 0.2712, 0.3078, 0.426", \ "0.3876, 0.3876, 0.3984, 0.426, 0.5454", \ "0.9672, 0.9666, 0.9666, 0.9684, 1.0272", \ "1.836, 1.836, 1.836, 1.836, 1.8426"); } cell_rise(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.122952, 0.128631, 0.135156, 0.135376, 0.12211", \ "0.164343, 0.175515, 0.188853, 0.195586, 0.197929", \ "0.244616, 0.255862, 0.280724, 0.29533, 0.32331", \ "0.564733, 0.576414, 0.603061, 0.627167, 0.700129", \ "1.04515, 1.05692, 1.08029, 1.10052, 1.18075"); } rise_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.126, 0.1512, 0.2064, 0.249, 0.3732", \ "0.1836, 0.1998, 0.2574, 0.2946, 0.426", \ "0.306, 0.3114, 0.3504, 0.3918, 0.5226", \ "0.7956, 0.7956, 0.8034, 0.819, 0.9126", \ "1.5294, 1.5294, 1.5294, 1.5318, 1.5726"); } } timing() { related_pin : "C"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.135743, 0.163306, 0.21245, 0.243388, 0.332819", \ "0.198295, 0.220839, 0.279903, 0.317937, 0.427524", \ "0.316866, 0.336776, 0.394505, 0.442531, 0.577465", \ "0.769029, 0.786536, 0.835023, 0.877341, 1.04242", \ "1.43464, 1.45323, 1.49843, 1.53626, 1.6812"); } fall_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0984, 0.1074, 0.1512, 0.18, 0.276", \ "0.1686, 0.1686, 0.2082, 0.2442, 0.3534", \ "0.3114, 0.3096, 0.3282, 0.3582, 0.4794", \ "0.8892, 0.8886, 0.8886, 0.8904, 0.957", \ "1.7574, 1.7574, 1.7574, 1.7574, 1.7658"); } cell_rise(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.085661, 0.105524, 0.127392, 0.136521, 0.149452", \ "0.128732, 0.154603, 0.187721, 0.206183, 0.239983", \ "0.209225, 0.234836, 0.286106, 0.314458, 0.381183", \ "0.530486, 0.553915, 0.606227, 0.649252, 0.781668", \ "1.01217, 1.03397, 1.08245, 1.1218, 1.26396"); } rise_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1182, 0.15, 0.1986, 0.2292, 0.3252", \ "0.1812, 0.1986, 0.2586, 0.2868, 0.4026", \ "0.3042, 0.309, 0.3534, 0.3978, 0.5202", \ "0.795, 0.7956, 0.7992, 0.8178, 0.9288", \ "1.5294, 1.5294, 1.5294, 1.5294, 1.5762"); } } internal_power() { related_pin : "A"; fall_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.39643, 0.382982, 0.211539, 0.032463, 0.667671", \ "0.394775, 0.388384, 0.241382, 0.07867, 0.585638", \ "0.396928, 0.392353, 0.280619, 0.143202, 0.455488", \ "0.386202, 0.400321, 0.341258, 0.257887, 0.16329", \ "0.385746, 0.402077, 0.368606, 0.316943, 0.025344"); } rise_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "1.98705, 1.99065, 2.16916, 2.35265, 3.07612", \ "1.99617, 1.9924, 2.14767, 2.30818, 3.00195", \ "2.00177, 1.99674, 2.11808, 2.25697, 2.88691", \ "2.00519, 2.00446, 2.0711, 2.16618, 2.64732", \ "2.00606, 1.99419, 2.04793, 2.11317, 2.48108"); } } internal_power() { related_pin : "B"; fall_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.375107, 0.368914, 0.204031, 0.033483, 0.624038", \ "0.362623, 0.365552, 0.228697, 0.075936, 0.544315", \ "0.350334, 0.357052, 0.255181, 0.130063, 0.424312", \ "0.336914, 0.339318, 0.290995, 0.217444, 0.167462", \ "0.332456, 0.331023, 0.302692, 0.258048, 0.00788"); } rise_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "1.4485, 1.4562, 1.66651, 1.85032, 2.5499", \ "1.45007, 1.47533, 1.63587, 1.80404, 2.46243", \ "1.45404, 1.47281, 1.59489, 1.73909, 2.33506", \ "1.45787, 1.47318, 1.53836, 1.63161, 2.07231", \ "1.45866, 1.45691, 1.51087, 1.57387, 1.89962"); } } internal_power() { related_pin : "C"; fall_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.4201, 0.376422, 0.206384, 0.0372, 0.600653", \ "0.376125, 0.371623, 0.228293, 0.080367, 0.514291", \ "0.329902, 0.333418, 0.246904, 0.129075, 0.392623", \ "0.279684, 0.286595, 0.252016, 0.187843, 0.163967", \ "0.262813, 0.261626, 0.245932, 0.206859, 0.03244"); } rise_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.87566, 0.939844, 1.17874, 1.36919, 2.04263", \ "0.88793, 0.93755, 1.13619, 1.30886, 1.94882", \ "0.896378, 0.930542, 1.08392, 1.23198, 1.81184", \ "0.907622, 0.925106, 1.00934, 1.10383, 1.52896", \ "0.915504, 0.921482, 0.974132, 1.0372, 1.34683"); } } } } /* ---------------- * * Design : OAI21X1 * * ---------------- */ cell (OAI21X1) { area : 207; cell_leakage_power : 0.0720872; pin(A) { direction : input; capacitance : 0.0323034; rise_capacitance : 0.0321164; fall_capacitance : 0.0323034; } pin(B) { direction : input; capacitance : 0.0329964; rise_capacitance : 0.0329964; fall_capacitance : 0.0329316; } pin(C) { direction : input; capacitance : 0.0216377; rise_capacitance : 0.0215874; fall_capacitance : 0.0216377; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.433556; function : "(!((A+B) C))"; timing() { related_pin : "A"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.110401, 0.116701, 0.124593, 0.12774, 0.126245", \ "0.148763, 0.154209, 0.168493, 0.175478, 0.183615", \ "0.224031, 0.227036, 0.244739, 0.257801, 0.283412", \ "0.522991, 0.520666, 0.530551, 0.544564, 0.598228", \ "0.963615, 0.960206, 0.964312, 0.972795, 1.01934"); } fall_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.111, 0.1344, 0.198, 0.2508, 0.4128", \ "0.165, 0.177, 0.2346, 0.2838, 0.4554", \ "0.2688, 0.273, 0.3114, 0.357, 0.5274", \ "0.6888, 0.6888, 0.6954, 0.7104, 0.8214", \ "1.32, 1.3194, 1.3194, 1.323, 1.3632"); } cell_rise(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.118532, 0.135307, 0.171007, 0.195542, 0.26662", \ "0.160217, 0.175596, 0.216154, 0.244811, 0.32622", \ "0.238709, 0.253888, 0.296764, 0.330308, 0.428896", \ "0.563419, 0.573168, 0.605394, 0.637236, 0.757836", \ "1.04447, 1.0544, 1.07936, 1.10397, 1.20927"); } rise_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1212, 0.1428, 0.2052, 0.2538, 0.414", \ "0.1818, 0.1908, 0.2454, 0.2946, 0.4626", \ "0.3036, 0.3066, 0.3408, 0.3828, 0.546", \ "0.7926, 0.7926, 0.7968, 0.81, 0.9072", \ "1.5276, 1.527, 1.527, 1.5282, 1.563"); } } timing() { related_pin : "B"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.088944, 0.091981, 0.085301, 0.075756, 0.029997", \ "0.129963, 0.133805, 0.135688, 0.13213, 0.100942", \ "0.205348, 0.207458, 0.218428, 0.223929, 0.217341", \ "0.50611, 0.502658, 0.510025, 0.52154, 0.559331", \ "0.947127, 0.943286, 0.946034, 0.952754, 0.991657"); } fall_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0756, 0.1026, 0.153, 0.198, 0.3216", \ "0.129, 0.1416, 0.1956, 0.2364, 0.3756", \ "0.231, 0.2352, 0.2736, 0.315, 0.4626", \ "0.6516, 0.6516, 0.6576, 0.672, 0.7788", \ "1.2816, 1.2822, 1.2822, 1.2852, 1.3254"); } cell_rise(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.106728, 0.142979, 0.203811, 0.246175, 0.373422", \ "0.148368, 0.181689, 0.251224, 0.298886, 0.440326", \ "0.22955, 0.260195, 0.335655, 0.388211, 0.550255", \ "0.551571, 0.578412, 0.642914, 0.697526, 0.891381", \ "1.03286, 1.05837, 1.11687, 1.16546, 1.34604"); } rise_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1218, 0.1452, 0.198, 0.2364, 0.3594", \ "0.18, 0.192, 0.2478, 0.2868, 0.4194", \ "0.303, 0.3048, 0.342, 0.3798, 0.5172", \ "0.7926, 0.7926, 0.795, 0.8082, 0.903", \ "1.5276, 1.5276, 1.5276, 1.5276, 1.56"); } } timing() { related_pin : "C"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.082292, 0.096874, 0.101885, 0.097413, 0.060477", \ "0.117849, 0.137037, 0.155529, 0.158467, 0.139753", \ "0.18465, 0.206164, 0.242999, 0.257161, 0.268051", \ "0.453095, 0.471926, 0.515668, 0.55128, 0.639319", \ "0.853993, 0.871968, 0.912403, 0.945077, 1.06324"); } fall_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0876, 0.117, 0.1725, 0.2115, 0.3306", \ "0.1341, 0.1521, 0.2133, 0.2568, 0.3912", \ "0.2247, 0.2346, 0.2895, 0.3345, 0.4839", \ "0.6009, 0.6006, 0.6135, 0.6429, 0.7896", \ "1.1658, 1.1655, 1.1658, 1.17, 1.254"); } cell_rise(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.098751, 0.137287, 0.206704, 0.252291, 0.384098", \ "0.147252, 0.184107, 0.262877, 0.314885, 0.464773", \ "0.239395, 0.273825, 0.356666, 0.417205, 0.593024", \ "0.603462, 0.634042, 0.70701, 0.766013, 0.978703", \ "1.14407, 1.17418, 1.2421, 1.2962, 1.49231"); } rise_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1161, 0.1347, 0.1905, 0.2262, 0.3354", \ "0.1824, 0.1926, 0.2373, 0.2787, 0.3978", \ "0.3156, 0.3168, 0.3447, 0.3798, 0.5052", \ "0.8523, 0.8523, 0.8526, 0.8604, 0.9369", \ "1.6581, 1.6578, 1.6581, 1.6581, 1.6758"); } } internal_power() { related_pin : "A"; fall_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.302058, 0.219846, 0.11778, 0.433147, 1.57746", \ "0.297421, 0.244632, 0.054332, 0.342238, 1.43325", \ "0.293121, 0.258777, 0.022286, 0.221147, 1.21009", \ "0.288808, 0.271064, 0.140733, 0.013832, 0.726257", \ "0.286847, 0.277897, 0.197305, 0.094872, 0.417311"); } rise_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "1.28198, 1.33492, 1.71433, 2.04136, 3.21364", \ "1.28819, 1.33179, 1.65177, 1.95508, 3.08793", \ "1.29331, 1.3215, 1.57718, 1.83787, 2.8849", \ "1.2934, 1.31421, 1.45212, 1.626, 2.41636", \ "1.29526, 1.29737, 1.39158, 1.50938, 2.09419"); } } internal_power() { related_pin : "B"; fall_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.28009, 0.196409, 0.108406, 0.382532, 1.35986", \ "0.250928, 0.196992, 0.056706, 0.304626, 1.23302", \ "0.226064, 0.193164, 0.000093, 0.206979, 1.04347", \ "0.199565, 0.188292, 0.079844, 0.052835, 0.659375", \ "0.19077, 0.184631, 0.116447, 0.027339, 0.41865"); } rise_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.893656, 0.992369, 1.33586, 1.61909, 2.61443", \ "0.902395, 0.967478, 1.27221, 1.53664, 2.49949", \ "0.907789, 0.958415, 1.19344, 1.4239, 2.31445", \ "0.918971, 0.938979, 1.07067, 1.22027, 1.88982", \ "0.92215, 0.931777, 1.01344, 1.11202, 1.59938"); } } internal_power() { related_pin : "C"; fall_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.118765, 0.056186, 0.177117, 0.37866, 1.11005", \ "0.114565, 0.068771, 0.121394, 0.309404, 0.996067", \ "0.110685, 0.080627, 0.061107, 0.215029, 0.832436", \ "0.106834, 0.092829, 0.020418, 0.073657, 0.502961", \ "0.105527, 0.098153, 0.050578, 0.01732, 0.305235"); } rise_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.651689, 0.727809, 0.984805, 1.19745, 1.93861", \ "0.663996, 0.724184, 0.93805, 1.13507, 1.84523", \ "0.675781, 0.708245, 0.881716, 1.04997, 1.70424", \ "0.69982, 0.705478, 0.803757, 0.91034, 1.39543", \ "0.705618, 0.706667, 0.766966, 0.838759, 1.19078"); } } } } /* ---------------- * * Design : OAI22X1 * * ---------------- */ cell (OAI22X1) { area : 360; cell_leakage_power : 0.0923334; pin(A) { direction : input; capacitance : 0.032315; rise_capacitance : 0.0321; fall_capacitance : 0.032315; } pin(B) { direction : input; capacitance : 0.0329905; rise_capacitance : 0.0329905; fall_capacitance : 0.0329118; } pin(C) { direction : input; capacitance : 0.0325267; rise_capacitance : 0.0322759; fall_capacitance : 0.0325267; } pin(D) { direction : input; capacitance : 0.0331734; rise_capacitance : 0.0331734; fall_capacitance : 0.033147; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.448195; function : "(!((A+B) (C+D)))"; timing() { related_pin : "A"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.123608, 0.13546, 0.149659, 0.155176, 0.159732", \ "0.157218, 0.169455, 0.189685, 0.199871, 0.213928", \ "0.224455, 0.233269, 0.260135, 0.276101, 0.308246", \ "0.48029, 0.487993, 0.513005, 0.536687, 0.605515", \ "0.862854, 0.87004, 0.890246, 0.909554, 0.988613"); } fall_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1281, 0.1491, 0.2106, 0.2628, 0.4287", \ "0.1731, 0.1878, 0.2439, 0.2937, 0.4665", \ "0.2643, 0.27, 0.3138, 0.3588, 0.5307", \ "0.6309, 0.6303, 0.642, 0.6639, 0.7923", \ "1.1817, 1.1814, 1.1817, 1.1877, 1.2534"); } cell_rise(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.131748, 0.148562, 0.18804, 0.215493, 0.295256", \ "0.172422, 0.188823, 0.231696, 0.262793, 0.351689", \ "0.252403, 0.267935, 0.311314, 0.346536, 0.451881", \ "0.578471, 0.588197, 0.620284, 0.652156, 0.77667", \ "1.05981, 1.0696, 1.0945, 1.1192, 1.22739"); } rise_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.156, 0.1746, 0.2373, 0.2877, 0.4431", \ "0.2163, 0.225, 0.2769, 0.3279, 0.4887", \ "0.3384, 0.3411, 0.3735, 0.4149, 0.5712", \ "0.8277, 0.8277, 0.8319, 0.8448, 0.9402", \ "1.5624, 1.5624, 1.5621, 1.5633, 1.5975"); } } timing() { related_pin : "B"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.104778, 0.114118, 0.114342, 0.108014, 0.0709", \ "0.139944, 0.150658, 0.160536, 0.160019, 0.136385", \ "0.205443, 0.216262, 0.236678, 0.245272, 0.246535", \ "0.464539, 0.472364, 0.495512, 0.516745, 0.569501", \ "0.847551, 0.855153, 0.874507, 0.892467, 0.9642"); } fall_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0978, 0.117, 0.1725, 0.2148, 0.3444", \ "0.1416, 0.1554, 0.21, 0.252, 0.3939", \ "0.2316, 0.2367, 0.2805, 0.3231, 0.4731", \ "0.5982, 0.5985, 0.6093, 0.6315, 0.7542", \ "1.1487, 1.1487, 1.149, 1.1547, 1.2213"); } cell_rise(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.121859, 0.156062, 0.222367, 0.267645, 0.404357", \ "0.161833, 0.194798, 0.268075, 0.317745, 0.466267", \ "0.243248, 0.27421, 0.350029, 0.404789, 0.572771", \ "0.566584, 0.593367, 0.657741, 0.712574, 0.909965", \ "1.04817, 1.07365, 1.13198, 1.18052, 1.36356"); } rise_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.156, 0.1776, 0.234, 0.2757, 0.3999", \ "0.2163, 0.2247, 0.2796, 0.3222, 0.4521", \ "0.3381, 0.3387, 0.3756, 0.4122, 0.5481", \ "0.8277, 0.8277, 0.8298, 0.843, 0.9366", \ "1.5624, 1.5624, 1.5627, 1.5624, 1.5948"); } } timing() { related_pin : "C"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.119006, 0.141628, 0.175842, 0.194761, 0.238492", \ "0.153471, 0.177461, 0.219004, 0.242202, 0.297661", \ "0.220851, 0.244215, 0.294788, 0.324753, 0.399492", \ "0.488862, 0.510184, 0.557455, 0.597551, 0.721296", \ "0.892227, 0.910232, 0.952815, 0.988452, 1.12181"); } fall_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1254, 0.1446, 0.2091, 0.2538, 0.4071", \ "0.1701, 0.1848, 0.2445, 0.2919, 0.4515", \ "0.2634, 0.2685, 0.3153, 0.3633, 0.5277", \ "0.6402, 0.6399, 0.6483, 0.6726, 0.8109", \ "1.2048, 1.2051, 1.2054, 1.2078, 1.2789"); } cell_rise(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.112429, 0.126838, 0.155629, 0.172277, 0.212399", \ "0.155218, 0.171922, 0.204594, 0.225325, 0.278339", \ "0.238318, 0.25236, 0.290145, 0.317595, 0.391112", \ "0.565506, 0.574555, 0.605024, 0.63362, 0.738624", \ "1.04742, 1.05661, 1.08106, 1.10412, 1.20012"); } rise_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1266, 0.1452, 0.2073, 0.2529, 0.39", \ "0.1887, 0.2001, 0.2505, 0.2937, 0.4404", \ "0.3102, 0.3138, 0.3462, 0.3846, 0.5295", \ "0.7995, 0.7995, 0.8037, 0.8166, 0.9069", \ "1.5336, 1.5336, 1.5336, 1.5345, 1.5687"); } } timing() { related_pin : "D"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.100185, 0.119749, 0.13696, 0.142163, 0.140893", \ "0.135931, 0.15815, 0.187019, 0.19901, 0.214009", \ "0.204966, 0.225643, 0.269594, 0.291856, 0.333517", \ "0.474706, 0.49417, 0.538995, 0.577229, 0.685292", \ "0.877385, 0.895139, 0.93617, 0.970436, 1.09806"); } fall_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0933, 0.1122, 0.1674, 0.204, 0.3276", \ "0.1365, 0.1515, 0.207, 0.2499, 0.3852", \ "0.231, 0.2352, 0.2823, 0.3285, 0.4728", \ "0.6063, 0.6066, 0.6153, 0.6399, 0.7776", \ "1.1712, 1.1715, 1.1712, 1.1739, 1.2474"); } cell_rise(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.102059, 0.134905, 0.187804, 0.221858, 0.317486", \ "0.146189, 0.177421, 0.240264, 0.280338, 0.392555", \ "0.228827, 0.25724, 0.329475, 0.376801, 0.514195", \ "0.553778, 0.579692, 0.642713, 0.694929, 0.876547", \ "1.03582, 1.06071, 1.11855, 1.16582, 1.33974"); } rise_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1284, 0.1509, 0.2064, 0.2421, 0.3561", \ "0.189, 0.201, 0.2538, 0.2919, 0.4149", \ "0.3099, 0.3129, 0.3486, 0.3858, 0.5166", \ "0.7995, 0.7995, 0.8013, 0.8148, 0.9087", \ "1.5339, 1.5336, 1.5339, 1.5336, 1.5672"); } } internal_power() { related_pin : "A"; fall_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.275558, 0.215109, 0.10053, 0.399069, 1.51295", \ "0.272057, 0.224924, 0.046901, 0.32221, 1.38375", \ "0.265367, 0.233624, 0.019068, 0.213043, 1.1803", \ "0.259138, 0.250421, 0.124783, 0.02449, 0.721848", \ "0.257606, 0.255213, 0.178069, 0.077933, 0.425665"); } rise_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "1.55828, 1.60686, 1.97669, 2.305, 3.46917", \ "1.56257, 1.60853, 1.922, 2.22131, 3.34844", \ "1.57312, 1.60012, 1.84872, 2.10708, 3.1488", \ "1.57328, 1.59299, 1.72958, 1.90244, 2.68837", \ "1.57548, 1.57691, 1.67042, 1.78778, 2.37056"); } } internal_power() { related_pin : "B"; fall_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.243965, 0.17946, 0.095024, 0.355457, 1.30521", \ "0.221494, 0.179952, 0.054544, 0.291477, 1.19303", \ "0.201962, 0.178041, 0.013152, 0.205008, 1.02237", \ "0.181241, 0.169991, 0.062856, 0.065854, 0.659658", \ "0.174459, 0.164387, 0.097072, 0.02082, 0.429416"); } rise_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "1.17408, 1.26509, 1.59926, 1.88153, 2.87202", \ "1.17726, 1.2444, 1.53971, 1.80383, 2.7599", \ "1.18707, 1.23645, 1.46683, 1.6946, 2.58032", \ "1.19796, 1.21831, 1.34868, 1.49699, 2.16322", \ "1.20205, 1.21161, 1.2923, 1.39036, 1.87584"); } } internal_power() { related_pin : "C"; fall_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.271011, 0.205809, 0.094038, 0.363785, 1.35534", \ "0.270991, 0.216235, 0.038173, 0.289655, 1.23461", \ "0.268455, 0.23015, 0.034452, 0.182051, 1.0446", \ "0.265144, 0.247302, 0.140399, 0.017067, 0.618534", \ "0.262323, 0.254268, 0.189111, 0.10599, 0.337837"); } rise_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "1.32909, 1.38197, 1.70879, 1.9877, 2.9827", \ "1.34647, 1.3975, 1.66355, 1.91708, 2.87684", \ "1.36781, 1.38923, 1.60949, 1.82929, 2.7114", \ "1.38285, 1.39678, 1.52009, 1.67036, 2.34569", \ "1.38937, 1.3861, 1.47674, 1.58125, 2.09238"); } } internal_power() { related_pin : "D"; fall_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.231861, 0.166277, 0.095056, 0.334936, 1.20139", \ "0.21633, 0.167083, 0.046314, 0.270513, 1.09132", \ "0.194192, 0.171743, 0.01555, 0.178181, 0.926543", \ "0.175352, 0.163686, 0.077598, 0.031834, 0.575785", \ "0.167918, 0.160732, 0.107932, 0.036022, 0.352291"); } rise_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.950276, 1.03974, 1.3428, 1.59282, 2.46304", \ "0.967897, 1.03383, 1.29238, 1.52426, 2.36347", \ "0.984326, 1.02069, 1.23217, 1.43283, 2.20818", \ "1.00903, 1.02245, 1.14133, 1.27304, 1.85873", \ "1.01629, 1.02208, 1.09851, 1.18742, 1.62102"); } } } } /* -------------- * * Design : OR2X1 * * -------------- */ cell (OR2X1) { area : 288; cell_leakage_power : 0.105606; pin(A) { direction : input; capacitance : 0.0276945; rise_capacitance : 0.0276945; fall_capacitance : 0.0276318; } pin(B) { direction : input; capacitance : 0.0270172; rise_capacitance : 0.0267846; fall_capacitance : 0.0270172; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.412521; function : "(A+B)"; timing() { related_pin : "A"; timing_sense : positive_unate; cell_rise(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.168124, 0.194863, 0.243568, 0.269642, 0.349991", \ "0.215406, 0.242019, 0.288561, 0.317689, 0.400657", \ "0.305581, 0.331637, 0.379749, 0.408223, 0.494526", \ "0.665148, 0.69168, 0.739474, 0.769024, 0.856639", \ "1.20691, 1.23177, 1.27941, 1.30883, 1.39678"); } rise_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0858, 0.0912, 0.099, 0.1062, 0.1158", \ "0.15, 0.1488, 0.156, 0.1584, 0.174", \ "0.2802, 0.2808, 0.282, 0.2856, 0.2964", \ "0.8166, 0.8166, 0.8166, 0.8172, 0.8226", \ "1.6218, 1.6218, 1.6218, 1.6218, 1.6236"); } cell_fall(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.167235, 0.183125, 0.207461, 0.220554, 0.244132", \ "0.225725, 0.242382, 0.268265, 0.282233, 0.307408", \ "0.33762, 0.359373, 0.385586, 0.397183, 0.425573", \ "0.781205, 0.801497, 0.828672, 0.842904, 0.878058", \ "1.44393, 1.46412, 1.49125, 1.50498, 1.54152"); } fall_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.096, 0.102, 0.1068, 0.1116, 0.1242", \ "0.1626, 0.1626, 0.1698, 0.1758, 0.1872", \ "0.3012, 0.3018, 0.309, 0.3132, 0.327", \ "0.8778, 0.8778, 0.8784, 0.8814, 0.8922", \ "1.7466, 1.7466, 1.7466, 1.7466, 1.7514"); } } timing() { related_pin : "B"; timing_sense : positive_unate; cell_rise(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.217882, 0.246664, 0.31295, 0.357293, 0.487574", \ "0.265234, 0.294318, 0.358924, 0.404147, 0.537089", \ "0.354871, 0.383919, 0.449834, 0.493378, 0.626227", \ "0.715591, 0.744095, 0.808667, 0.852047, 0.984106", \ "1.25529, 1.28427, 1.34831, 1.39144, 1.52337"); } rise_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0984, 0.0984, 0.1032, 0.1038, 0.1218", \ "0.1542, 0.1536, 0.1578, 0.1614, 0.1698", \ "0.282, 0.282, 0.2838, 0.2844, 0.2922", \ "0.8166, 0.8166, 0.8172, 0.8178, 0.8202", \ "1.6224, 1.6224, 1.6224, 1.6224, 1.6236"); } cell_fall(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.178768, 0.184275, 0.194645, 0.195275, 0.178761", \ "0.236996, 0.24691, 0.255526, 0.258655, 0.246326", \ "0.349597, 0.358376, 0.369039, 0.373149, 0.367184", \ "0.792036, 0.802519, 0.81274, 0.816178, 0.819354", \ "1.45516, 1.46515, 1.47515, 1.47808, 1.48125"); } fall_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0942, 0.0984, 0.1116, 0.1176, 0.1344", \ "0.1596, 0.1638, 0.171, 0.1788, 0.1992", \ "0.3012, 0.3012, 0.3072, 0.3126, 0.3336", \ "0.8784, 0.8778, 0.8784, 0.8802, 0.8922", \ "1.7466, 1.7466, 1.7466, 1.7466, 1.7496"); } } internal_power() { related_pin : "A"; rise_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.013149, 0.070887, 0.32262, 0.514137, 1.21018", \ "0.026271, 0.07461, 0.315629, 0.502573, 1.18508", \ "0.031193, 0.089177, 0.307366, 0.496227, 1.1641", \ "0.034543, 0.091278, 0.308944, 0.493762, 1.14359", \ "0.027238, 0.091917, 0.309898, 0.493386, 1.13826"); } fall_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.855353, 0.940041, 1.19294, 1.38873, 2.10134", \ "0.863621, 0.941992, 1.19522, 1.3934, 2.07531", \ "0.870439, 0.954282, 1.19748, 1.39068, 2.0626", \ "0.870243, 0.957009, 1.19982, 1.39085, 2.04754", \ "0.871806, 0.958163, 1.20118, 1.39115, 2.04376"); } } internal_power() { related_pin : "B"; rise_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.038192, 0.087727, 0.33766, 0.554247, 1.31377", \ "0.03014, 0.082891, 0.322236, 0.536492, 1.2793", \ "0.031365, 0.080551, 0.318112, 0.521335, 1.24755", \ "0.035498, 0.081458, 0.310135, 0.507432, 1.21311", \ "0.035595, 0.081965, 0.308747, 0.504304, 1.20218"); } fall_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "1.23912, 1.27797, 1.54398, 1.76412, 2.55167", \ "1.24565, 1.29441, 1.54364, 1.75725, 2.52147", \ "1.25985, 1.29653, 1.54334, 1.7511, 2.49796", \ "1.2626, 1.30397, 1.54457, 1.74766, 2.47536", \ "1.25405, 1.30509, 1.54467, 1.74518, 2.46832"); } } } } /* -------------- * * Design : OR2X2 * * -------------- */ cell (OR2X2) { area : 288; cell_leakage_power : 0.106154; pin(A) { direction : input; capacitance : 0.0276578; rise_capacitance : 0.0276578; fall_capacitance : 0.0276256; } pin(B) { direction : input; capacitance : 0.0270241; rise_capacitance : 0.0267791; fall_capacitance : 0.0270241; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.924545; function : "(A+B)"; timing() { related_pin : "A"; timing_sense : positive_unate; cell_rise(delay_template_5x5) { index_1 ("0.05, 0.1, 0.2, 0.6, 1.2"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.21564, 0.241265, 0.298867, 0.33374, 0.434389", \ "0.261354, 0.287848, 0.343545, 0.380026, 0.483983", \ "0.348904, 0.375124, 0.43041, 0.467602, 0.571926", \ "0.693677, 0.719559, 0.774544, 0.809949, 0.913076", \ "1.21038, 1.23611, 1.2908, 1.3258, 1.42782"); } rise_transition(delay_template_5x5) { index_1 ("0.05, 0.1, 0.2, 0.6, 1.2"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0978, 0.0996, 0.1044, 0.1092, 0.1278", \ "0.1524, 0.1536, 0.159, 0.1638, 0.1788", \ "0.2742, 0.273, 0.2778, 0.2802, 0.2916", \ "0.7854, 0.7848, 0.7854, 0.786, 0.7896", \ "1.557, 1.557, 1.5564, 1.557, 1.5576"); } cell_fall(delay_template_5x5) { index_1 ("0.05, 0.1, 0.2, 0.6, 1.2"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.192162, 0.218373, 0.250139, 0.271515, 0.313317", \ "0.246453, 0.271638, 0.306271, 0.326753, 0.370283", \ "0.347887, 0.371758, 0.409279, 0.428535, 0.473442", \ "0.742207, 0.764459, 0.801868, 0.822401, 0.869574", \ "1.33167, 1.35359, 1.39071, 1.41068, 1.45802"); } fall_transition(delay_template_5x5) { index_1 ("0.05, 0.1, 0.2, 0.6, 1.2"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0996, 0.1002, 0.1098, 0.1152, 0.1332", \ "0.1512, 0.1542, 0.1626, 0.1686, 0.1854", \ "0.2748, 0.276, 0.2808, 0.2868, 0.3018", \ "0.7854, 0.7854, 0.786, 0.7884, 0.798", \ "1.5582, 1.5582, 1.5588, 1.5582, 1.563"); } } timing() { related_pin : "B"; timing_sense : positive_unate; cell_rise(delay_template_5x5) { index_1 ("0.05, 0.1, 0.2, 0.6, 1.2"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.26144, 0.288823, 0.359491, 0.409256, 0.552897", \ "0.309414, 0.336969, 0.406731, 0.456017, 0.601402", \ "0.396325, 0.424187, 0.493377, 0.541876, 0.68752", \ "0.739694, 0.76766, 0.835562, 0.882957, 1.02592", \ "1.25621, 1.28425, 1.35152, 1.39857, 1.54018"); } rise_transition(delay_template_5x5) { index_1 ("0.05, 0.1, 0.2, 0.6, 1.2"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1092, 0.1086, 0.108, 0.1158, 0.1326", \ "0.1596, 0.1596, 0.1632, 0.1674, 0.1794", \ "0.2766, 0.2772, 0.2778, 0.2808, 0.288", \ "0.7854, 0.7854, 0.7854, 0.786, 0.7884", \ "1.557, 1.557, 1.557, 1.557, 1.5582"); } cell_fall(delay_template_5x5) { index_1 ("0.05, 0.1, 0.2, 0.6, 1.2"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.199666, 0.213894, 0.227156, 0.232159, 0.22723", \ "0.255687, 0.268344, 0.283586, 0.290278, 0.288812", \ "0.357257, 0.368792, 0.386136, 0.39276, 0.396453", \ "0.75217, 0.763315, 0.778759, 0.785492, 0.795631", \ "1.34162, 1.3526, 1.36728, 1.37373, 1.38308"); } fall_transition(delay_template_5x5) { index_1 ("0.05, 0.1, 0.2, 0.6, 1.2"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0978, 0.0996, 0.1098, 0.12, 0.1386", \ "0.1536, 0.1554, 0.1632, 0.1716, 0.1956", \ "0.2754, 0.276, 0.2808, 0.2856, 0.3084", \ "0.7854, 0.7854, 0.7854, 0.7872, 0.7992", \ "1.5588, 1.5582, 1.5582, 1.5588, 1.5618"); } } internal_power() { related_pin : "A"; rise_power(energy_template_5x5) { index_1 ("0.05, 0.1, 0.2, 0.6, 1.2"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.425189, 0.483416, 0.742834, 0.95789, 1.76384", \ "0.412974, 0.466119, 0.701139, 0.912391, 1.67404", \ "0.417985, 0.466382, 0.672775, 0.873298, 1.59235", \ "0.414313, 0.464914, 0.660023, 0.840318, 1.50158", \ "0.415408, 0.4641, 0.654377, 0.830426, 1.47077"); } fall_power(energy_template_5x5) { index_1 ("0.05, 0.1, 0.2, 0.6, 1.2"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "1.16522, 1.25761, 1.52948, 1.7546, 2.5874", \ "1.17044, 1.25625, 1.507, 1.72864, 2.49849", \ "1.16652, 1.24917, 1.48695, 1.68971, 2.42303", \ "1.177, 1.24456, 1.47314, 1.66066, 2.33507", \ "1.1793, 1.24335, 1.46934, 1.65337, 2.30724"); } } internal_power() { related_pin : "B"; rise_power(energy_template_5x5) { index_1 ("0.05, 0.1, 0.2, 0.6, 1.2"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.483931, 0.523788, 0.797915, 1.04259, 1.90649", \ "0.453152, 0.489714, 0.748775, 0.979793, 1.80831", \ "0.431599, 0.46763, 0.705374, 0.92154, 1.71289", \ "0.41388, 0.451283, 0.664952, 0.863765, 1.59041", \ "0.408433, 0.44571, 0.654886, 0.847453, 1.5488"); } fall_power(energy_template_5x5) { index_1 ("0.05, 0.1, 0.2, 0.6, 1.2"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "1.52818, 1.60798, 1.88215, 2.13584, 3.03532", \ "1.55059, 1.60324, 1.85831, 2.09288, 2.94152", \ "1.55476, 1.60008, 1.8394, 2.05693, 2.85428", \ "1.55988, 1.5957, 1.82466, 2.02667, 2.76843", \ "1.56168, 1.59565, 1.82047, 2.01724, 2.73674"); } } } } /* --------------- * * Design : PADINC * * --------------- */ cell (PADINC) { pad_cell : true; area : 27000; cell_leakage_power : 1.31655; pin(DI) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 7.31841; function : "YPAD"; timing() { related_pin : "YPAD"; timing_sense : positive_unate; cell_rise(delay_template_5x5) { index_1 ("0.1, 0.2, 0.4, 1.2, 2.4"); index_2 ("0.06, 0.18, 0.36, 0.78, 1.8"); values ( \ "0.108026, 0.12458, 0.139385, 0.146833, 0.127273", \ "0.120044, 0.137086, 0.151778, 0.160511, 0.144859", \ "0.14417, 0.159323, 0.175259, 0.188959, 0.175725", \ "0.234294, 0.248147, 0.264149, 0.278119, 0.27083", \ "0.365474, 0.38007, 0.396959, 0.410779, 0.407667"); } rise_transition(delay_template_5x5) { index_1 ("0.1, 0.2, 0.4, 1.2, 2.4"); index_2 ("0.06, 0.18, 0.36, 0.78, 1.8"); values ( \ "0.037589, 0.045521, 0.059557, 0.0696, 0.0966", \ "0.054145, 0.056744, 0.0744, 0.087, 0.1056", \ "0.0846, 0.0828, 0.096, 0.1074, 0.1278", \ "0.207, 0.2088, 0.2124, 0.2226, 0.2406", \ "0.4032, 0.4026, 0.4038, 0.4098, 0.4332"); } cell_fall(delay_template_5x5) { index_1 ("0.1, 0.2, 0.4, 1.2, 2.4"); index_2 ("0.06, 0.18, 0.36, 0.78, 1.8"); values ( \ "0.115822, 0.143129, 0.187914, 0.262157, 0.398888", \ "0.125949, 0.157667, 0.199642, 0.276522, 0.418238", \ "0.149806, 0.181843, 0.226066, 0.304689, 0.448991", \ "0.236178, 0.268548, 0.313787, 0.39551, 0.548125", \ "0.3625, 0.397138, 0.440579, 0.522875, 0.682247"); } fall_transition(delay_template_5x5) { index_1 ("0.1, 0.2, 0.4, 1.2, 2.4"); index_2 ("0.06, 0.18, 0.36, 0.78, 1.8"); values ( \ "0.044776, 0.038311, 0.057684, 0.0672, 0.093", \ "0.048211, 0.051984, 0.0666, 0.0816, 0.1026", \ "0.072, 0.0738, 0.0876, 0.099, 0.1272", \ "0.1758, 0.1776, 0.1818, 0.1926, 0.2196", \ "0.3396, 0.3408, 0.3408, 0.3486, 0.3774"); } } internal_power() { related_pin : "YPAD"; rise_power(energy_template_5x5) { index_1 ("0.1, 0.2, 0.4, 1.2, 2.4"); index_2 ("0.06, 0.18, 0.36, 0.78, 1.8"); values ( \ "0.307483, 2.1999, 6.26737, 15.2408, 37.3802", \ "0.297863, 2.02134, 5.91233, 14.8326, 36.8731", \ "0.312306, 2.28179, 5.51785, 14.4314, 36.1575", \ "0.529378, 2.26119, 5.39966, 13.7334, 34.9225", \ "0.62087, 2.30596, 5.39155, 13.4891, 34.1645"); } fall_power(energy_template_5x5) { index_1 ("0.1, 0.2, 0.4, 1.2, 2.4"); index_2 ("0.06, 0.18, 0.36, 0.78, 1.8"); values ( \ "12.233, 14.5646, 18.1598, 27.6503, 50.0488", \ "12.2901, 14.3999, 17.9757, 27.2248, 49.4884", \ "12.3494, 14.3848, 17.9689, 26.7693, 48.7104", \ "12.521, 14.3728, 17.8547, 26.3005, 47.3872", \ "12.7159, 14.5039, 17.8187, 26.0453, 46.6569"); } } } pin(YPAD) { is_pad : true; direction : input; capacitance : 0.450177; rise_capacitance : 0.450177; fall_capacitance : 0.449686; } } /* ----------------- * * Design : PADINOUT * * ----------------- */ cell (PADINOUT) { pad_cell : true; area : 27000; cell_leakage_power : 1.24078; pin(DI) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 7.37282; function : "YPAD"; timing() { related_pin : "YPAD"; timing_sense : positive_unate; cell_rise(delay_template_5x5) { index_1 ("0.1, 0.2, 0.4, 1.2, 2.4"); index_2 ("0.06, 0.18, 0.36, 0.78, 1.8"); values ( \ "0.107478, 0.12458, 0.139385, 0.146833, 0.127273", \ "0.120527, 0.137086, 0.151778, 0.160511, 0.144859", \ "0.145399, 0.159323, 0.175259, 0.188959, 0.175725", \ "0.233464, 0.248147, 0.264149, 0.278119, 0.27083", \ "0.365501, 0.380071, 0.396959, 0.410779, 0.407667"); } rise_transition(delay_template_5x5) { index_1 ("0.1, 0.2, 0.4, 1.2, 2.4"); index_2 ("0.06, 0.18, 0.36, 0.78, 1.8"); values ( \ "0.037183, 0.045521, 0.059557, 0.0696, 0.0966", \ "0.05598, 0.056744, 0.0744, 0.087, 0.1056", \ "0.0804, 0.0828, 0.096, 0.1074, 0.1278", \ "0.2088, 0.2088, 0.2124, 0.2226, 0.2406", \ "0.4026, 0.4026, 0.4038, 0.4098, 0.4332"); } cell_fall(delay_template_5x5) { index_1 ("0.1, 0.2, 0.4, 1.2, 2.4"); index_2 ("0.06, 0.18, 0.36, 0.78, 1.8"); values ( \ "0.115822, 0.143129, 0.187914, 0.262157, 0.398888", \ "0.125949, 0.157667, 0.199642, 0.276522, 0.418238", \ "0.149806, 0.181843, 0.226066, 0.304689, 0.448991", \ "0.236178, 0.268548, 0.313787, 0.39551, 0.548125", \ "0.3625, 0.397123, 0.440575, 0.522875, 0.682247"); } fall_transition(delay_template_5x5) { index_1 ("0.1, 0.2, 0.4, 1.2, 2.4"); index_2 ("0.06, 0.18, 0.36, 0.78, 1.8"); values ( \ "0.044776, 0.038311, 0.057684, 0.0672, 0.093", \ "0.048211, 0.051984, 0.0666, 0.0816, 0.1026", \ "0.072, 0.0738, 0.0876, 0.099, 0.1272", \ "0.1758, 0.1776, 0.1812, 0.1926, 0.2196", \ "0.3396, 0.3408, 0.3408, 0.3486, 0.3774"); } } internal_power() { related_pin : "YPAD"; rise_power(energy_template_5x5) { index_1 ("0.1, 0.2, 0.4, 1.2, 2.4"); index_2 ("0.06, 0.18, 0.36, 0.78, 1.8"); values ( \ "0.456015, 2.31963, 6.48176, 15.3382, 37.4196", \ "0.394933, 2.19304, 6.12904, 14.9317, 36.9136", \ "0.497392, 2.31921, 5.56884, 14.5289, 36.1976", \ "0.689239, 2.27169, 5.40067, 13.7489, 34.9627", \ "0.78394, 2.31534, 5.39229, 13.4934, 34.2046"); } fall_power(energy_template_5x5) { index_1 ("0.1, 0.2, 0.4, 1.2, 2.4"); index_2 ("0.06, 0.18, 0.36, 0.78, 1.8"); values ( \ "12.1831, 14.533, 18.1222, 27.6336, 50.0407", \ "12.2423, 14.3661, 17.9382, 27.2078, 49.4803", \ "12.3231, 14.3711, 17.9466, 26.7524, 48.7033", \ "12.5182, 14.3738, 17.8542, 26.2963, 47.379", \ "12.7189, 14.5008, 17.8159, 26.0455, 46.6487"); } } } pin(DO) { direction : input; capacitance : 0.22845; rise_capacitance : 0.228417; fall_capacitance : 0.22845; } pin(OEN) { direction : input; capacitance : 0.0456812; rise_capacitance : 0.0456812; fall_capacitance : 0.0455713; internal_power() { rise_power(passive_energy_template_6x1) { index_1 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ("0, 0, 0, 0, 0, 0"); } fall_power(passive_energy_template_6x1) { index_1 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ("28.653, 29.0519, 29.9452, 31.7079, 33.0651, 35.8802"); } } } pin(YPAD) { is_pad : true; direction : inout; drive_current : 2.0; capacitance : 0.45018; rise_capacitance : 0.45018; fall_capacitance : 0.449481; max_capacitance : 19.0972; function : "DO"; three_state : "(!OEN)"; timing() { related_pin : "DO"; timing_sense : positive_unate; cell_rise(delay_template_5x5) { index_1 ("5, 10, 20, 50, 75"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.693264, 0.711993, 0.756444, 0.788969, 0.87149", \ "0.915557, 0.933896, 0.977268, 1.00828, 1.08886", \ "1.33244, 1.35061, 1.39316, 1.42327, 1.50046", \ "2.55773, 2.57606, 2.61827, 2.64807, 2.72247", \ "3.57499, 3.59327, 3.63579, 3.66522, 3.73885"); } rise_transition(delay_template_5x5) { index_1 ("5, 10, 20, 50, 75"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.4008, 0.4008, 0.4014, 0.4032, 0.4116", \ "0.6858, 0.6852, 0.6858, 0.687, 0.6936", \ "1.2726, 1.2726, 1.2726, 1.2732, 1.2756", \ "3.0726, 3.0726, 3.0726, 3.0726, 3.0726", \ "4.5798, 4.5798, 4.5798, 4.5786, 4.5786"); } cell_fall(delay_template_5x5) { index_1 ("5, 10, 20, 50, 75"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.50214, 0.534553, 0.607003, 0.660879, 0.82261", \ "0.630631, 0.663138, 0.734772, 0.788884, 0.95466", \ "0.842301, 0.874641, 0.946619, 1.00085, 1.16964", \ "1.39749, 1.43009, 1.50205, 1.55642, 1.72626", \ "1.84498, 1.87738, 1.94957, 2.00364, 2.17328"); } fall_transition(delay_template_5x5) { index_1 ("5, 10, 20, 50, 75"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.2232, 0.2238, 0.2262, 0.2298, 0.2526", \ "0.342, 0.3426, 0.345, 0.3468, 0.3636", \ "0.567, 0.567, 0.5682, 0.57, 0.5814", \ "1.2486, 1.2486, 1.2492, 1.2498, 1.2528", \ "1.8324, 1.8324, 1.8324, 1.833, 1.8342"); } } timing() { related_pin : "OEN"; timing_sense : positive_unate; timing_type : three_state_enable; cell_rise(delay_template_5x6) { index_1 ("5, 10, 20, 50, 75"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.86038, 0.895739, 0.941475, 0.994384, 1.02158, 1.06019", \ "1.08035, 1.11566, 1.16128, 1.21437, 1.24176, 1.28042", \ "1.49331, 1.52876, 1.57449, 1.62758, 1.65478, 1.69347", \ "2.71407, 2.7495, 2.7952, 2.84833, 2.87566, 2.91431", \ "3.7295, 3.76491, 3.81072, 3.86385, 3.89137, 3.93003"); } rise_transition(delay_template_5x6) { index_1 ("5, 10, 20, 50, 75"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.4032, 0.402, 0.4026, 0.4032, 0.402, 0.4026", \ "0.6864, 0.687, 0.687, 0.687, 0.687, 0.6864", \ "1.2732, 1.2732, 1.2732, 1.2738, 1.2732, 1.2732", \ "3.0726, 3.0726, 3.0726, 3.0726, 3.0726, 3.0726", \ "4.5792, 4.5786, 4.5786, 4.5786, 4.5798, 4.5792"); } cell_fall(delay_template_5x6) { index_1 ("5, 10, 20, 50, 75"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.558941, 0.594874, 0.645316, 0.703703, 0.73434, 0.77872", \ "0.682419, 0.719081, 0.768787, 0.828215, 0.859919, 0.905075", \ "0.889844, 0.926741, 0.976572, 1.03645, 1.06805, 1.11407", \ "1.44324, 1.48009, 1.53001, 1.59012, 1.62196, 1.66841", \ "1.8905, 1.92724, 1.97718, 2.03732, 2.06923, 2.1157"); } fall_transition(delay_template_5x6) { index_1 ("5, 10, 20, 50, 75"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.2118, 0.2112, 0.2124, 0.2142, 0.2148, 0.2172", \ "0.3318, 0.3312, 0.3318, 0.333, 0.3336, 0.3354", \ "0.5598, 0.5598, 0.5598, 0.5604, 0.5604, 0.5628", \ "1.2462, 1.2462, 1.2462, 1.2468, 1.2474, 1.2474", \ "1.8318, 1.8318, 1.8318, 1.8318, 1.8318, 1.8324"); } } timing() { related_pin : "OEN"; timing_type : three_state_disable; timing_sense : negative_unate; cell_rise(delay_template_6x1) { index_1 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ("0.486388, 0.542539, 0.621882, 0.740975, 0.818135, 0.951685"); } rise_transition(delay_template_6x1) { index_1 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ("0.486388, 0.542539, 0.621882, 0.740975, 0.818135, 0.951685"); } cell_fall(delay_template_6x1) { index_1 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ("0.619694, 0.676982, 0.75257, 0.860164, 0.928958, 1.0493"); } fall_transition(delay_template_6x1) { index_1 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ("0.619694, 0.676982, 0.75257, 0.860164, 0.928958, 1.0493"); } } internal_power() { related_pin : "DO"; rise_power(energy_template_5x5) { index_1 ("5, 10, 20, 50, 75"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "45.8568, 45.9907, 47.7495, 50.1728, 59.9758", \ "52.2483, 52.2245, 53.5412, 55.5713, 64.0977", \ "65.0754, 64.9779, 66.0894, 67.7051, 74.9903", \ "102.16, 102.149, 103.19, 104.602, 111.057", \ "132.221, 132.266, 133.341, 134.726, 141.1"); } fall_power(energy_template_5x5) { index_1 ("5, 10, 20, 50, 75"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "75.688, 76.1577, 77.7922, 78.9615, 83.7956", \ "78.3358, 78.8473, 80.7363, 82.2034, 88.0684", \ "83.3462, 83.7883, 85.639, 87.3059, 93.9248", \ "98.666, 99.0379, 100.869, 102.644, 109.694", \ "111.501, 111.916, 113.692, 115.507, 122.73"); } } internal_power() { related_pin : "OEN"; rise_power(energy_template_5x6) { index_1 ("5, 10, 20, 50, 75"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "52.3141, 52.6164, 53.5175, 55.4393, 56.8229, 59.747", \ "57.7148, 58.0219, 59.0499, 60.8771, 62.4145, 65.198", \ "69.2703, 69.6314, 70.5858, 72.4949, 73.9367, 76.8238", \ "104.881, 105.23, 106.19, 108.105, 109.549, 112.472", \ "134.529, 134.847, 135.808, 137.739, 139.209, 142.129"); } fall_power(energy_template_5x6) { index_1 ("5, 10, 20, 50, 75"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "43.5129, 43.9824, 45.1275, 47.424, 49.0349, 52.463", \ "46.2164, 46.5748, 47.6861, 49.9179, 51.6625, 54.9757", \ "51.1426, 51.5727, 52.6421, 54.9628, 56.6611, 59.9801", \ "66.3621, 66.7687, 67.9133, 70.2148, 71.812, 75.1594", \ "79.2306, 79.6349, 80.7833, 83.0219, 84.6835, 88.0202"); } } } } /* --------------- * * Design : PADOUT * * --------------- */ cell (PADOUT) { pad_cell : true; area : 27000; cell_leakage_power : 1.74691; pin(DO) { direction : input; capacitance : 0.228397; rise_capacitance : 0.228397; fall_capacitance : 0.227217; } pin(YPAD) { is_pad : true; direction : output; drive_current : 2.0; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 19.1162; function : "DO"; timing() { related_pin : "DO"; timing_sense : positive_unate; cell_rise(delay_template_5x5) { index_1 ("5, 10, 20, 50, 75"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.693264, 0.711993, 0.756444, 0.788969, 0.87149", \ "0.915557, 0.933896, 0.977268, 1.00828, 1.08886", \ "1.33244, 1.35061, 1.39316, 1.42327, 1.50046", \ "2.55773, 2.57606, 2.61827, 2.64807, 2.72247", \ "3.57499, 3.59327, 3.63579, 3.66522, 3.73885"); } rise_transition(delay_template_5x5) { index_1 ("5, 10, 20, 50, 75"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.4008, 0.4008, 0.4014, 0.4032, 0.4116", \ "0.6858, 0.6852, 0.6858, 0.687, 0.6936", \ "1.2726, 1.2726, 1.2726, 1.2732, 1.2756", \ "3.0726, 3.0726, 3.0726, 3.0726, 3.0726", \ "4.5798, 4.5798, 4.5798, 4.5786, 4.5786"); } cell_fall(delay_template_5x5) { index_1 ("5, 10, 20, 50, 75"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.50214, 0.534553, 0.607003, 0.660879, 0.82261", \ "0.630631, 0.663138, 0.734772, 0.788884, 0.95466", \ "0.842301, 0.874641, 0.946619, 1.00085, 1.16964", \ "1.39749, 1.43009, 1.50205, 1.55642, 1.72626", \ "1.84498, 1.87738, 1.94957, 2.00364, 2.17328"); } fall_transition(delay_template_5x5) { index_1 ("5, 10, 20, 50, 75"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.2232, 0.2238, 0.2262, 0.2298, 0.2526", \ "0.342, 0.3426, 0.345, 0.3468, 0.3636", \ "0.567, 0.567, 0.5682, 0.57, 0.5814", \ "1.2486, 1.2486, 1.2492, 1.2498, 1.2528", \ "1.8324, 1.8324, 1.8324, 1.833, 1.8342"); } } internal_power() { related_pin : "DO"; rise_power(energy_template_5x5) { index_1 ("5, 10, 20, 50, 75"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "45.761, 45.8976, 47.6542, 50.0729, 59.8828", \ "52.2483, 52.2244, 53.5413, 55.5709, 64.0975", \ "65.0754, 64.9781, 66.0895, 67.7046, 74.99", \ "102.161, 102.149, 103.19, 104.603, 111.057", \ "132.22, 132.266, 133.339, 134.726, 141.099"); } fall_power(energy_template_5x5) { index_1 ("5, 10, 20, 50, 75"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "71.6358, 72.576, 73.8788, 75.3071, 79.8288", \ "76.8916, 77.335, 79.3764, 80.7658, 86.4507", \ "83.0538, 83.4957, 85.3709, 87.0335, 93.6319", \ "98.6665, 99.0384, 100.869, 102.644, 109.694", \ "111.501, 111.916, 113.692, 115.507, 122.73"); } } } } /* --------------- * * Design : TBUFX1 * * --------------- */ cell (TBUFX1) { area : 360; cell_leakage_power : 0.0784113; pin(A) { direction : input; capacitance : 0.0322637; rise_capacitance : 0.0321199; fall_capacitance : 0.0322637; } pin(EN) { direction : input; capacitance : 0.0229726; rise_capacitance : 0.0228037; fall_capacitance : 0.0229726; internal_power() { rise_power(passive_energy_template_5x1) { index_1 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ("0, 0, 0, 0, 0"); } fall_power(passive_energy_template_5x1) { index_1 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ("0.369556, 0.474898, 0.686291, 0.848452, 1.40576"); } } } pin(Y) { direction : output; capacitance : 0.00446886; rise_capacitance : 0.00445715; fall_capacitance : 0.00446886; max_capacitance : 0.471807; function : "(!A)"; three_state : "(!EN)"; timing() { related_pin : "A"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.0294689, 0.0544689, 0.104469, 0.304469, 0.604469"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.098021, 0.107738, 0.116848, 0.120411, 0.118928", \ "0.140457, 0.145944, 0.161229, 0.168852, 0.177237", \ "0.216515, 0.221175, 0.238623, 0.251679, 0.277825", \ "0.512906, 0.515622, 0.525679, 0.539971, 0.593822", \ "0.958519, 0.955565, 0.959932, 0.968405, 1.01544"); } fall_transition(delay_template_5x5) { index_1 ("0.0294689, 0.0544689, 0.104469, 0.304469, 0.604469"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1152, 0.138, 0.2004, 0.2526, 0.414", \ "0.1674, 0.18, 0.2358, 0.2856, 0.4548", \ "0.27, 0.2742, 0.3132, 0.3576, 0.5274", \ "0.687, 0.6876, 0.6942, 0.7092, 0.8208", \ "1.317, 1.317, 1.317, 1.3206, 1.3614"); } cell_rise(delay_template_5x5) { index_1 ("0.0294572, 0.0544572, 0.104457, 0.304457, 0.604457"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.123226, 0.131082, 0.166965, 0.190626, 0.259838", \ "0.165302, 0.176316, 0.213526, 0.241284, 0.321293", \ "0.247103, 0.256534, 0.295519, 0.32842, 0.425565", \ "0.567964, 0.574885, 0.605587, 0.636985, 0.756804", \ "1.04962, 1.05558, 1.0801, 1.10439, 1.20921"); } rise_transition(delay_template_5x5) { index_1 ("0.0294572, 0.0544572, 0.104457, 0.304457, 0.604457"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1188, 0.1362, 0.1998, 0.2508, 0.4098", \ "0.1776, 0.189, 0.2424, 0.2892, 0.4578", \ "0.3006, 0.3036, 0.339, 0.3792, 0.5418", \ "0.7908, 0.7908, 0.7956, 0.8082, 0.9054", \ "1.5252, 1.5252, 1.5252, 1.5264, 1.5612"); } } timing() { related_pin : "EN"; timing_sense : positive_unate; timing_type : three_state_enable; cell_rise(delay_template_5x5) { index_1 ("0.0294572, 0.0544572, 0.104457, 0.304457, 0.604457"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.137042, 0.157652, 0.189621, 0.206279, 0.231899", \ "0.181003, 0.201393, 0.234633, 0.252271, 0.287121", \ "0.260671, 0.283211, 0.314648, 0.335023, 0.37539", \ "0.581692, 0.602335, 0.634508, 0.652095, 0.700254", \ "1.06286, 1.08346, 1.11555, 1.13348, 1.17772"); } rise_transition(delay_template_5x5) { index_1 ("0.0294572, 0.0544572, 0.104457, 0.304457, 0.604457"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1344, 0.1332, 0.135, 0.1452, 0.165", \ "0.1842, 0.1866, 0.1848, 0.189, 0.2046", \ "0.3012, 0.3024, 0.2988, 0.2976, 0.3102", \ "0.7908, 0.7908, 0.7896, 0.7872, 0.7878", \ "1.5252, 1.5258, 1.5258, 1.5258, 1.521"); } cell_fall(delay_template_5x5) { index_1 ("0.0294689, 0.0544689, 0.104469, 0.304469, 0.604469"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.052815, 0.04887, -0.002152, -0.056425, -0.277479", \ "0.084052, 0.097748, 0.072696, 0.036499, -0.138455", \ "0.146108, 0.166259, 0.176816, 0.164578, 0.056047", \ "0.443213, 0.459199, 0.493305, 0.518351, 0.536787", \ "0.884403, 0.900331, 0.934367, 0.95994, 1.04314"); } fall_transition(delay_template_5x5) { index_1 ("0.0294689, 0.0544689, 0.104469, 0.304469, 0.604469"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0666, 0.1038, 0.1464, 0.1776, 0.2622", \ "0.1224, 0.1506, 0.2028, 0.2364, 0.3438", \ "0.2376, 0.2496, 0.3066, 0.3474, 0.4692", \ "0.684, 0.6828, 0.7008, 0.7332, 0.8706", \ "1.3176, 1.3176, 1.317, 1.3248, 1.4322"); } } timing() { related_pin : "EN"; timing_type : three_state_disable; timing_sense : negative_unate; cell_rise(delay_template_5x1) { index_1 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ("0.0555, 0.0925, 0.1665, 0.222, 0.407"); } rise_transition(delay_template_5x1) { index_1 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ("0.0555, 0.0925, 0.1665, 0.222, 0.407"); } cell_fall(delay_template_5x1) { index_1 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ("0.106389, 0.146248, 0.201349, 0.237018, 0.330092"); } fall_transition(delay_template_5x1) { index_1 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ("0.106389, 0.146248, 0.201349, 0.237018, 0.330092"); } } internal_power() { related_pin : "A"; fall_power(energy_template_5x5) { index_1 ("0.0294689, 0.0544689, 0.104469, 0.304469, 0.604469"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.303293, 0.216925, 0.145765, 0.46456, 1.61129", \ "0.299046, 0.237348, 0.074951, 0.367204, 1.46299", \ "0.294363, 0.249803, 0.008308, 0.238744, 1.23376", \ "0.289411, 0.269841, 0.134871, 0.02196, 0.73892", \ "0.288355, 0.277887, 0.194297, 0.090405, 0.424881"); } rise_power(energy_template_5x5) { index_1 ("0.0294572, 0.0544572, 0.104457, 0.304457, 0.604457"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "1.21904, 1.26549, 1.65619, 1.98636, 3.16346", \ "1.22655, 1.27795, 1.593, 1.90025, 3.03493", \ "1.23287, 1.26775, 1.51686, 1.78123, 2.82971", \ "1.23223, 1.25117, 1.3952, 1.56666, 2.3568", \ "1.23412, 1.24456, 1.33483, 1.44923, 2.03286"); } } internal_power() { related_pin : "EN"; rise_power(energy_template_5x5) { index_1 ("0.0294572, 0.0544572, 0.104457, 0.304457, 0.604457"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.410643, 0.479311, 0.67716, 0.833466, 1.37944", \ "0.412498, 0.481639, 0.678387, 0.837674, 1.38596", \ "0.421603, 0.483073, 0.682245, 0.842239, 1.38916", \ "0.420363, 0.487675, 0.687978, 0.847442, 1.39688", \ "0.425109, 0.492924, 0.692828, 0.852225, 1.40173"); } fall_power(energy_template_5x5) { index_1 ("0.0294689, 0.0544689, 0.104469, 0.304469, 0.604469"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.079802, 0.003798, 0.229804, 0.408379, 0.992249", \ "0.08152, 0.002682, 0.214221, 0.385773, 0.973036", \ "0.078941, 0.005357, 0.203527, 0.371739, 0.947971", \ "0.082535, 0.009593, 0.192819, 0.355536, 0.919532", \ "0.080729, 0.010678, 0.187963, 0.349018, 0.906816"); } } } } /* --------------- * * Design : TBUFX2 * * --------------- */ cell (TBUFX2) { area : 504; cell_leakage_power : 0.120618; pin(A) { direction : input; capacitance : 0.0645226; rise_capacitance : 0.0642363; fall_capacitance : 0.0645226; } pin(EN) { direction : input; capacitance : 0.0469583; rise_capacitance : 0.0466327; fall_capacitance : 0.0469583; internal_power() { rise_power(passive_energy_template_5x1) { index_1 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ("0, 0, 0, 0, 0"); } fall_power(passive_energy_template_5x1) { index_1 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ("0.767242, 1.0106, 1.51264, 1.89325, 3.1995"); } } } pin(Y) { direction : output; capacitance : 0.00893819; rise_capacitance : 0.00892753; fall_capacitance : 0.00893819; max_capacitance : 0.944821; function : "(!A)"; three_state : "(!EN)"; timing() { related_pin : "A"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.0589382, 0.108938, 0.208938, 0.608938, 1.20894"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.098903, 0.108219, 0.11723, 0.120667, 0.119075", \ "0.141032, 0.146402, 0.161545, 0.169096, 0.177376", \ "0.216889, 0.221502, 0.238875, 0.251876, 0.277952", \ "0.513056, 0.515752, 0.525794, 0.540079, 0.593915", \ "0.958609, 0.955635, 0.959995, 0.968463, 1.01549"); } fall_transition(delay_template_5x5) { index_1 ("0.0589382, 0.108938, 0.208938, 0.608938, 1.20894"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1128, 0.1374, 0.1998, 0.252, 0.4134", \ "0.1668, 0.1794, 0.2364, 0.285, 0.4542", \ "0.2694, 0.2736, 0.3132, 0.357, 0.5274", \ "0.687, 0.687, 0.6936, 0.7092, 0.8208", \ "1.317, 1.317, 1.317, 1.32, 1.3608"); } cell_rise(delay_template_5x5) { index_1 ("0.0589275, 0.108928, 0.208928, 0.608928, 1.20893"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.121959, 0.13073, 0.166838, 0.190548, 0.259834", \ "0.164193, 0.175801, 0.213311, 0.241122, 0.321197", \ "0.24579, 0.255908, 0.295226, 0.328186, 0.42539", \ "0.566624, 0.574162, 0.605092, 0.636569, 0.756513", \ "1.04823, 1.05481, 1.07956, 1.1039, 1.2088"); } rise_transition(delay_template_5x5) { index_1 ("0.0589275, 0.108928, 0.208928, 0.608928, 1.20893"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1188, 0.1362, 0.1998, 0.2514, 0.4098", \ "0.177, 0.189, 0.2424, 0.2892, 0.4578", \ "0.3, 0.3036, 0.3384, 0.3792, 0.5418", \ "0.7902, 0.7902, 0.795, 0.8076, 0.9048", \ "1.5246, 1.5246, 1.5246, 1.5258, 1.5612"); } } timing() { related_pin : "EN"; timing_sense : positive_unate; timing_type : three_state_enable; cell_rise(delay_template_5x5) { index_1 ("0.0589275, 0.108928, 0.208928, 0.608928, 1.20893"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.130082, 0.147999, 0.174782, 0.180978, 0.189421", \ "0.172644, 0.189047, 0.218101, 0.228951, 0.24478", \ "0.254334, 0.271543, 0.297521, 0.311322, 0.333816", \ "0.574451, 0.591898, 0.616344, 0.628714, 0.660972", \ "1.05573, 1.0774, 1.09735, 1.10993, 1.13806"); } rise_transition(delay_template_5x5) { index_1 ("0.0589275, 0.108928, 0.208928, 0.608928, 1.20893"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1296, 0.1338, 0.1362, 0.138, 0.1566", \ "0.1812, 0.1806, 0.1836, 0.1878, 0.2022", \ "0.3012, 0.3006, 0.297, 0.297, 0.309", \ "0.7902, 0.7902, 0.789, 0.786, 0.7878", \ "1.5246, 1.5252, 1.5252, 1.5252, 1.5204"); } cell_fall(delay_template_5x5) { index_1 ("0.0589382, 0.108938, 0.208938, 0.608938, 1.20894"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.052168, 0.04806, -0.003375, -0.057358, -0.278269", \ "0.08274, 0.095879, 0.071204, 0.034637, -0.13939", \ "0.145792, 0.16532, 0.174017, 0.160578, 0.053284", \ "0.443447, 0.45933, 0.493445, 0.518782, 0.53691", \ "0.884621, 0.900617, 0.934561, 0.959997, 1.04328"); } fall_transition(delay_template_5x5) { index_1 ("0.0589382, 0.108938, 0.208938, 0.608938, 1.20894"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0672, 0.1044, 0.1452, 0.1764, 0.2622", \ "0.1272, 0.1524, 0.204, 0.237, 0.342", \ "0.2394, 0.252, 0.3084, 0.3486, 0.4716", \ "0.6846, 0.684, 0.7044, 0.7386, 0.8778", \ "1.317, 1.317, 1.317, 1.3248, 1.4334"); } } timing() { related_pin : "EN"; timing_type : three_state_disable; timing_sense : negative_unate; cell_rise(delay_template_5x1) { index_1 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ("0.0555, 0.0925, 0.1665, 0.222, 0.407"); } rise_transition(delay_template_5x1) { index_1 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ("0.0555, 0.0925, 0.1665, 0.222, 0.407"); } cell_fall(delay_template_5x1) { index_1 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ("0.104296, 0.145328, 0.204946, 0.246006, 0.350915"); } fall_transition(delay_template_5x1) { index_1 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ("0.104296, 0.145328, 0.204946, 0.246006, 0.350915"); } } internal_power() { related_pin : "A"; fall_power(energy_template_5x5) { index_1 ("0.0589382, 0.108938, 0.208938, 0.608938, 1.20894"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.604404, 0.435211, 0.289022, 0.926257, 3.21992", \ "0.597585, 0.475625, 0.14946, 0.732269, 2.9237", \ "0.588435, 0.500093, 0.017754, 0.476091, 2.4658", \ "0.578607, 0.539837, 0.270174, 0.043375, 1.4771", \ "0.576519, 0.555838, 0.388825, 0.181079, 0.849372"); } rise_power(energy_template_5x5) { index_1 ("0.0589275, 0.108928, 0.208928, 0.608928, 1.20893"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "2.43872, 2.53133, 3.31348, 3.97383, 6.32753", \ "2.4536, 2.56015, 3.18683, 3.8014, 6.07061", \ "2.46759, 2.53604, 3.03434, 3.56307, 5.66005", \ "2.46658, 2.50213, 2.79079, 3.13374, 4.71406", \ "2.47034, 2.48943, 2.6699, 2.89866, 4.06593"); } } internal_power() { related_pin : "EN"; rise_power(energy_template_5x5) { index_1 ("0.0589275, 0.108928, 0.208928, 0.608928, 1.20893"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.826353, 0.9904, 1.46541, 1.83328, 3.11825", \ "0.831124, 1.00205, 1.46606, 1.84197, 3.13275", \ "0.85364, 1.00081, 1.4765, 1.84869, 3.13624", \ "0.840676, 1.01914, 1.48551, 1.86015, 3.14869", \ "0.846269, 1.03344, 1.49035, 1.8652, 3.15426"); } fall_power(energy_template_5x5) { index_1 ("0.0589382, 0.108938, 0.208938, 0.608938, 1.20894"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.156545, 0.043308, 0.570883, 0.983493, 2.34676", \ "0.159742, 0.033274, 0.540673, 0.941187, 2.30401", \ "0.156888, 0.027837, 0.520334, 0.913578, 2.25548", \ "0.148944, 0.01808, 0.50017, 0.88034, 2.20047", \ "0.151, 0.015757, 0.492507, 0.869781, 2.1738"); } } } } /* ---------------- * * Design : XNOR2X1 * * ---------------- */ cell (XNOR2X1) { area : 504; cell_leakage_power : 0.180094; pin(A) { direction : input; capacitance : 0.0535404; rise_capacitance : 0.0535404; fall_capacitance : 0.0535055; } pin(B) { direction : input; capacitance : 0.0637184; rise_capacitance : 0.0633381; fall_capacitance : 0.0637184; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.466943; function : "(!(A^B))"; timing() { related_pin : "A"; timing_sense : non_unate; cell_rise(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.156815, 0.168635, 0.197452, 0.21047, 0.232596", \ "0.194158, 0.207479, 0.236289, 0.251148, 0.274946", \ "0.271755, 0.285004, 0.31214, 0.327643, 0.357371", \ "0.587483, 0.603312, 0.628449, 0.640453, 0.674732", \ "1.06666, 1.08749, 1.10685, 1.11901, 1.14692"); } rise_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1272, 0.1272, 0.1218, 0.1248, 0.132", \ "0.1884, 0.1878, 0.177, 0.183, 0.1914", \ "0.3102, 0.3108, 0.303, 0.2982, 0.3084", \ "0.7998, 0.7998, 0.798, 0.7944, 0.7926", \ "1.5348, 1.5342, 1.5348, 1.5348, 1.5276"); } cell_fall(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.15237, 0.18153, 0.235044, 0.264221, 0.33857", \ "0.189822, 0.217119, 0.270178, 0.301769, 0.379032", \ "0.258812, 0.28758, 0.336456, 0.374426, 0.456087", \ "0.548689, 0.575975, 0.623495, 0.655808, 0.747211", \ "0.986731, 1.01384, 1.06355, 1.09108, 1.1756"); } fall_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1218, 0.1224, 0.114, 0.114, 0.126", \ "0.1746, 0.1728, 0.1632, 0.1662, 0.1722", \ "0.2772, 0.2778, 0.2688, 0.2658, 0.273", \ "0.6966, 0.696, 0.6948, 0.6894, 0.6888", \ "1.3272, 1.3272, 1.3272, 1.3272, 1.3188"); } } timing() { related_pin : "B"; timing_sense : non_unate; cell_rise(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.183189, 0.195986, 0.21573, 0.228851, 0.250022", \ "0.22312, 0.241713, 0.257875, 0.270548, 0.289713", \ "0.304039, 0.321093, 0.337266, 0.350062, 0.3686", \ "0.624939, 0.642758, 0.661355, 0.671081, 0.689436", \ "1.10616, 1.12379, 1.1425, 1.15198, 1.16936"); } rise_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1278, 0.1296, 0.1362, 0.1404, 0.1512", \ "0.1884, 0.189, 0.1926, 0.1962, 0.2082", \ "0.3102, 0.3102, 0.312, 0.3138, 0.321", \ "0.7992, 0.7992, 0.7998, 0.7998, 0.8034", \ "1.5342, 1.5342, 1.5342, 1.5342, 1.5354"); } cell_fall(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.17143, 0.19627, 0.235216, 0.260735, 0.328707", \ "0.208833, 0.23481, 0.275085, 0.299678, 0.366235", \ "0.285206, 0.311212, 0.348208, 0.37467, 0.438929", \ "0.58048, 0.60631, 0.645913, 0.6673, 0.730857", \ "1.02165, 1.04701, 1.08655, 1.10736, 1.1697"); } fall_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1236, 0.1266, 0.1296, 0.1374, 0.156", \ "0.1728, 0.1734, 0.1806, 0.1842, 0.1944", \ "0.2778, 0.2778, 0.2784, 0.2808, 0.288", \ "0.6954, 0.696, 0.696, 0.6966, 0.6996", \ "1.326, 1.3266, 1.326, 1.3266, 1.3272"); } } internal_power() { related_pin : "A"; rise_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.487457, 0.627581, 1.12141, 1.50487, 2.91454", \ "0.459386, 0.633978, 1.11016, 1.49584, 2.8559", \ "0.426321, 0.618469, 1.09432, 1.48154, 2.82693", \ "0.391676, 0.585895, 1.06397, 1.45125, 2.78124", \ "0.380331, 0.57136, 1.04295, 1.42867, 2.75352"); } fall_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "1.51029, 1.72107, 2.23442, 2.6399, 4.02808", \ "1.47807, 1.70001, 2.21717, 2.6298, 4.00545", \ "1.46333, 1.67992, 2.19081, 2.60383, 3.97213", \ "1.42822, 1.63792, 2.14833, 2.54787, 3.90828", \ "1.41181, 1.61596, 2.1133, 2.51328, 3.86202"); } } internal_power() { related_pin : "B"; rise_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.577067, 0.720188, 1.21631, 1.63084, 3.00399", \ "0.579951, 0.753343, 1.21614, 1.61434, 2.97855", \ "0.583121, 0.759428, 1.21544, 1.60767, 2.94652", \ "0.585539, 0.763991, 1.23494, 1.60475, 2.91767", \ "0.58503, 0.764169, 1.23395, 1.60437, 2.90455"); } fall_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "1.62916, 1.85198, 2.36299, 2.76931, 4.17349", \ "1.6394, 1.85334, 2.34369, 2.75261, 4.14111", \ "1.64475, 1.85693, 2.35332, 2.74407, 4.10747", \ "1.65195, 1.86161, 2.34971, 2.73592, 4.06734", \ "1.65435, 1.86353, 2.34993, 2.73236, 4.05299"); } } } } /* --------------- * * Design : XOR2X1 * * --------------- */ cell (XOR2X1) { area : 504; cell_leakage_power : 0.180289; pin(A) { direction : input; capacitance : 0.0535547; rise_capacitance : 0.0535547; fall_capacitance : 0.0535109; } pin(B) { direction : input; capacitance : 0.0637104; rise_capacitance : 0.0633463; fall_capacitance : 0.0637104; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.467136; function : "(A^B)"; timing() { related_pin : "A"; timing_sense : non_unate; cell_rise(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.157363, 0.169, 0.19768, 0.210662, 0.232738", \ "0.194581, 0.208526, 0.236561, 0.251375, 0.275111", \ "0.273232, 0.285301, 0.312378, 0.327851, 0.357541", \ "0.587769, 0.603537, 0.628628, 0.640606, 0.674851", \ "1.0669, 1.0877, 1.107, 1.11915, 1.14702"); } rise_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1272, 0.1278, 0.1218, 0.1248, 0.132", \ "0.1884, 0.1866, 0.177, 0.183, 0.1914", \ "0.3102, 0.3108, 0.3024, 0.2976, 0.3078", \ "0.7992, 0.7998, 0.7974, 0.7938, 0.792", \ "1.5342, 1.5342, 1.5342, 1.5342, 1.527"); } cell_fall(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.152464, 0.181415, 0.234956, 0.264144, 0.338519", \ "0.189626, 0.216979, 0.270104, 0.301658, 0.378991", \ "0.259283, 0.287329, 0.336494, 0.374417, 0.456594", \ "0.548556, 0.575889, 0.623585, 0.65588, 0.747306", \ "0.986782, 1.01381, 1.0636, 1.09184, 1.17571"); } fall_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.123, 0.1224, 0.114, 0.114, 0.126", \ "0.1752, 0.1728, 0.1638, 0.1662, 0.1722", \ "0.276, 0.2784, 0.2688, 0.2658, 0.2718", \ "0.6966, 0.6966, 0.6954, 0.6894, 0.6888", \ "1.3272, 1.3272, 1.3272, 1.3272, 1.3194"); } } timing() { related_pin : "B"; timing_sense : non_unate; cell_rise(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.17819, 0.191684, 0.211853, 0.225459, 0.247486", \ "0.218389, 0.232241, 0.253756, 0.266906, 0.286721", \ "0.298667, 0.313698, 0.333939, 0.346635, 0.365724", \ "0.619787, 0.634793, 0.657175, 0.667575, 0.686228", \ "1.1007, 1.12195, 1.13843, 1.1486, 1.16604"); } rise_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1278, 0.1308, 0.1356, 0.1404, 0.1512", \ "0.189, 0.1902, 0.1914, 0.1956, 0.2076", \ "0.309, 0.3096, 0.3114, 0.3126, 0.3198", \ "0.7974, 0.798, 0.7986, 0.798, 0.8016", \ "1.5324, 1.5324, 1.5318, 1.5324, 1.5336"); } cell_fall(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.176759, 0.200097, 0.241946, 0.265844, 0.3319", \ "0.214667, 0.2392, 0.277726, 0.303067, 0.36912", \ "0.288831, 0.316555, 0.351802, 0.37714, 0.44161", \ "0.583944, 0.611047, 0.648785, 0.670153, 0.73331", \ "1.02426, 1.05181, 1.08923, 1.10995, 1.17212"); } fall_transition(delay_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1212, 0.1236, 0.1326, 0.1356, 0.1542", \ "0.1728, 0.1734, 0.1788, 0.183, 0.1926", \ "0.2766, 0.2766, 0.2784, 0.2802, 0.2874", \ "0.6966, 0.6966, 0.6966, 0.6972, 0.7008", \ "1.3272, 1.3278, 1.3272, 1.3278, 1.329"); } } internal_power() { related_pin : "A"; rise_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.447111, 0.588045, 1.08134, 1.46614, 2.85941", \ "0.419444, 0.589856, 1.07007, 1.45578, 2.8157", \ "0.401755, 0.576484, 1.05417, 1.44142, 2.78654", \ "0.351294, 0.54505, 1.02372, 1.41084, 2.74059", \ "0.339678, 0.530918, 1.00304, 1.38834, 2.71305"); } fall_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "1.5661, 1.78089, 2.29173, 2.69441, 4.08626", \ "1.53739, 1.75849, 2.27504, 2.68689, 4.06256", \ "1.52137, 1.73657, 2.24954, 2.66269, 4.0303", \ "1.48776, 1.69543, 2.20835, 2.60798, 3.96792", \ "1.47194, 1.67407, 2.17408, 2.57294, 3.92242"); } } internal_power() { related_pin : "B"; rise_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.360055, 0.464771, 0.949218, 1.36182, 2.74127", \ "0.368048, 0.466736, 0.948832, 1.34496, 2.71383", \ "0.374026, 0.470427, 0.950304, 1.34015, 2.68093", \ "0.337153, 0.474521, 0.965715, 1.34207, 2.65064", \ "0.337793, 0.468256, 0.965353, 1.34075, 2.63791"); } fall_power(energy_template_5x5) { index_1 ("0.025, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "1.88821, 2.09474, 2.60683, 3.01209, 4.4239", \ "1.89246, 2.09064, 2.59176, 3.00054, 4.39187", \ "1.90207, 2.12092, 2.5993, 2.99902, 4.35773", \ "1.90385, 2.12564, 2.60292, 2.9874, 4.31866", \ "1.91034, 2.12743, 2.60287, 2.98428, 4.30552"); } } } } cell (PADFC) { area : 27000; dont_touch : true; } cell (PADNC) { area : 27000; dont_touch : true; } cell (PADVDD) { area : 27000; dont_touch : true; } cell (PADGND) { area : 27000; dont_touch : true; } } qflow-1.1.23/tech/osu050/osu050.sh0000755000175000001440000000617112526236535015024 0ustar timusers#!/bin/tcsh #--------------------------------------------------------------- # Shell script setting up all variables used by the qflow scripts # for this project #--------------------------------------------------------------- # The LEF file containing standard cell macros set leffile=osu050_stdcells.lef # The SPICE netlist containing subcell definitions for all the standard cells set spicefile=osu050_stdcells.sp # The liberty format file containing standard cell timing and function information set libertyfile=osu05_stdcells.lib # If there is another LEF file containing technology information # that is separate from the file containing standard cell macros, # set this. Otherwise, leave it defined as an empty string. set techleffile="" # All cells below should be the lowest output drive strength value, # if the standard cell set has multiple cells with different drive # strengths. Comment out any cells that do not exist. set flopcell=DFFPOSX1 ;# Standard positive-clocked DFF, no set or reset # set flopset=DFFS ;# DFF with preset, if available # set flopreset=DFFSR ;# DFF with clear, if available set flopsetreset=DFFSR ;# DFF with both set and clear set setpin=S ;# The name of the set pin on DFFs set resetpin=R ;# The name of the clear/reset pin on DFFs set setpininvert=1 ;# Set this to 1 if the set pin is inverted (!set) set resetpininvert=1 ;# Set this to 1 if the reset pin is inverted (!reset) set floppinout=Q ;# Name of the output pin on DFFs set floppinin=D ;# Name of the input pin on DFFs set floppinclk=CLK ;# Name of the clock pin on DFFs set bufcell=BUFX2 ;# Minimum drive strength buffer cell set bufpin_in=A ;# Name of input port to buffer cell set bufpin_out=Y ;# Name of output port to buffer cell set inverter=INVX1 ;# Minimum drive strength inverter cell set invertpin_in=A ;# Name of input port to inverter cell set invertpin_out=Y ;# Name of output port to inverter cell set norgate=NOR2X1 ;# 2-input NOR gate, minimum drive strength set norpin_in1=A ;# Name of first input pin to NOR gate set norpin_in2=B ;# Name of second input pin to NOR gate set norpin_out=Y ;# Name of output pin from OR gate set nandgate=NAND2X1 ;# 2-input NAND gate, minimum drive strength set nandpin_in1=A ;# Name of first input pin to NAND gate set nandpin_in2=B ;# Name of second input pin to NAND gate set nandpin_out=Y ;# Name of output pin from NAND gate set fillcell=FILL ;# Spacer (filler) cell (prefix, if more than one) set tiehi="" ;# Cell to connect to power, if one exists set tiehipin_out="" ;# Output pin name of tiehi cell, if it exists set tielo="" ;# Cell to connect to ground, if one exists set tielopin_out="" ;# Output pin name of tielo cell, if it exists set gndnet=gnd ;# Name used for ground pins in standard cells set vddnet=vdd ;# Name used for power pins in standard cells set separator="" ;# Separator between gate names and drive strengths set techfile=SCN3ME_SUBM.30 ;# magic techfile set magicrc=osu050.magicrc ;# magic startup script set gdsfile=osu05_stdcells.gds ;# GDS database of standard cells set fanout_options="-l 300 -c 75" ;# blifFanout target maximum latency ;# per gate 300ps, output load set to 75fF qflow-1.1.23/tech/osu050/SCN3ME_SUBM.30.tech0000644000175000001440000035477212526236535016313 0ustar timuserstech format 32 scmos end version version 2002a description "SCMOS: Submit as technology.lambda: SCN3ME_SUBM.30 [to process: AMIc5]" end planes well,w implant,i select,s cap,c active,a metal1,m1 metal2,m2 metal3,m3 oxide,ox comment xp contact via1,v1 via2,v2 fill end types well nwell,nw well pwell,pw implant n_field_implant,nfi implant p_field_implant,pfi select nselect,ns select pselect,ps cap electrode,poly2,el,p2 cap electrodecontact,poly2contact,poly2c,p2c,elc cap p2m12contact,p2m12c cap electrodecap,ecap,poly2cap,p2cap,pcap contact genericpoly2contact,gc2 active ntransistor,nfet active ptransistor,pfet active diffusion,diff active transistor,fet active ndiffusion,ndif,green active pdiffusion,pdif,brown active ndcontact,ndc active pdcontact,pdc active psubstratepdiff,pohmicdiff,pod,ppdiff,ppd,psd active nsubstratendiff,nohmicdiff,nod,nndiff,nnd,nsd active psubstratepcontact,pohmiccontact,poc,pwcontact,pwc,psc active nsubstratencontact,nohmiccontact,noc,nwcontact,nwc,nsc active polysilicon,red,poly,p active polycontact,pcontact,polycut,pc contact genericcontact,gcontact,gc metal1 metal1,m1,blue metal1 pseudo_rmetal1,prm1 metal1 rmetal1,rm1 metal1 fillm1,fm1 metal1 m2contact,m2cut,m2c,via1,v1 metal2 metal2,m2,purple metal2 pseudo_rmetal2,prm2 metal2 rmetal2,rm2 metal2 fillm2,fm2 via1 gv1 metal2 m3contact,m3cut,m3c,via2,v2 metal3 metal3,m3,cyan metal3 pseudo_rmetal3,prm3 metal3 rmetal3,rm3 metal3 fillm3,fm3 via2 gv2 metal3 pad oxide glass cap high_resist,hr cap poly2_high_resist,phr active pseudo_rpoly,prp active rpoly,rp cap pseudo_rpoly2,prp2 cap rpoly2,rp2 active pseudo_rndiffusion,prnd active rndiffusion,rndiff,rnd active pseudo_rpdiffusion,prpd active rpdiffusion,rpdiff,rpd active pseudo_rnwell,prnwell,prnw active rnwell,rnw implant filln,fn fill filla,fa fill fillb,fb active fillp,fp active fillapm,fapm xp xp xp m1p xp m2p xp m3p comment comment comment bb end contact pc poly metal1 ndc ndiff metal1 pdc pdiff metal1 nsc nsd metal1 psc psd metal1 m2c metal1 metal2 m3c metal2 metal3 stackable pc m2c pm12contact,pm12c stackable pdc m2c pdm12contact,pdm12c stackable psc m2c psm12contact,psm12c,pom12c,pwm12c stackable ndc m2c ndm12contact,ndm12c stackable nsc m2c nsm12contact,nsm12c,nom12c,nwm12c stackable m2c m3c m123contact,m123c end styles styletype mos nwell 12 pwell 13 nfi 53 pfi 54 nselect 43 pselect 44 diff 25 tran 2 4 ndiff 2 pdiff 4 nsd 3 psd 5 nfet 6 7 pfet 8 9 ndc 2 20 32 pdc 4 20 32 nsc 3 20 32 psc 5 20 32 poly 1 pcontact 1 20 32 gc 32 metal1 20 rm1 20 48 prm1 48 m1p 20 34 fm1 20 34 fp 1 34 fa 32 fb 45 34 fn 45 34 fapm 1 20 21 34 gv1 55 m2contact 20 21 55 p2m12contact 14 20 21 32 55 metal2 21 rm2 21 48 prm2 48 m2p 21 34 fm2 21 34 gv2 56 m3contact 21 22 56 metal3 22 rm3 22 48 prm3 48 m3p 22 34 fm3 22 34 pad 22 23 34 38 glass 34 xp 25 34 ecap 10 14 poly2 14 p2c 14 20 32 gc2 19 hr 10 phr 14 48 rp 47 48 prp 48 rp2 14 48 prp2 48 rnd 2 48 prnd 48 rpd 4 53 prpd 53 rnw 12 53 prnw 54 comment 45 bb 32 error_p 42 error_s 42 error_ps 42 magnet 54 rotate 57 fence 59 end compose compose nfet poly ndiff compose pfet poly pdiff paint diff nselect ndiff paint diff pselect pdiff compose tran poly diff paint tran nselect nfet paint tran pselect pfet paint psd ns ndiff paint nsd ps pdiff paint ndiff ps psd paint pdiff ns nsd paint pad m1 pad paint pad m2 pad paint pad m2c pad paint pfi nwell nfi paint nfi pwell pfi paint ndc nwell pdc paint nfet nwell pfet paint ndiff nwell pdiff paint psd nwell nsd paint psc nwell nsc paint pdc pwell ndc paint pfet pwell nfet paint pdiff pwell ndiff paint nsd pwell psd paint nsc pwell psc paint poly2 poly ecap erase ecap poly poly2 paint p2c poly2 p2c paint p2c ecap p2c paint p2m12c poly2 p2m12c paint p2m12c ecap p2m12c paint pad m3 pad compose phr poly2 hr paint hr poly2 phr paint poly2 hr phr erase phr hr poly2 #CRE/CRM compose rm1 prm1 m1 compose rm2 prm2 m2 compose rm3 prm3 m3 compose rp prp poly compose rp2 prp2 poly2 compose rnd prnd ndiff compose rpd prpd pdiff paint nwell rnw space paint nwell prnw space paint poly fp fp paint m1 fm1 fm1 paint m2 fm2 fm2 paint m3 fm3 fm3 end connect nwell,nsc/a,nsd nwell,nsc/a,nsd pwell,psc/a,psd pwell,psc/a,psd m1,fm1,fapm,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 m1,fm1,fapm,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 m2,fm2,fapm,m2c/m2,m3c/m2,m3c/m2 m2,fm2,fapm,m2c/m2,m3c/m2,m3c/m2 m3,fm3,fapm,m3c/m3 m3,fm3,fapm,m3c/m3 ndiff,ndc/a,pdiff,pdc/a ndiff,ndc/a,pdiff,pdc/a poly,fp,nfet,pfet,fet,fapm,pc/a poly,fp,nfet,pfet,fet,fapm,pc/a gc2 poly2,ecap,metal1 p2c poly2,ecap,m1,fm1,fapm,m2c/m1 p2m12c poly2,ecap,m1,fm1,fapm,m2c/m1,m2,fm2,fapm,m2c/m2,m3c/m2 poly2,ecap,p2c,p2m12c poly2,ecap,p2c,p2m12c gc2 poly2,ecap,m1,fm1,fapm,m2c/m1 gc poly,fp,ndiff,pdiff,nsd,psd,m1,fm1,fapm,m2c/m1 gv1 m1,fm1,fapm,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2,fm2,fapm,m3c/m2 gv2 m2,fm2,fapm,m2c/m2,m3c/m2,m3,fm3,fapm pad m1,fm1,m2,fm2,m3,fm3 rm1 prm1 rm2 prm2 rm3 prm3 rnw prnw rp prp rp2 prp2 rnd prnd rpd prpd phr hr end cifoutput style lambda=0.30(p) scalefactor 30 15 layer CWN nwell,rnw bloat-or pdiff,rpd,pdc/a,pfet * 180 bloat-or nsd,nsc/a * 90 bloat-or nfi * 120 grow 90 shrink 90 labels nwell,rnw calma 42 0 layer CWP pwell bloat-or ndiff,rnd,ndc/a,nfet * 180 bloat-or psd,psc/a * 90 bloat-or pfi * 120 grow 90 shrink 90 and-not CWN labels pwell calma 41 0 templayer TNS ns templayer TPS ps #we give priority to selects autogenerated around diffusions (vrs. ohmics) #XDP = (pdiff*60) Or ps #XDN = (ndiff*60) Or ns #FSP = ((pdiff*60,psc*60) Or XDP And-Not XDN Or ps shrink-grow #FSN = ((ndiff*60,nsc*60) Or XDN And-Not FDP Or ns shrink-grow #CSN = FSN #CSP = FSP #diffusion auto-nselect (will have priority) templayer XDN bloat-or ndiff,rnd,ndc/a * 60 psd,psc/a 0 or TNS #diffusion auto-pselect (will have priority) templayer XDP bloat-or pdiff,rpd,pdc/a * 60 nsd,nsc/a 0 or TPS #final pselect templayer FSP bloat-or pdiff,rpd,pfet,psd,pdc/a,psc/a,pfet * 60 ndiff,rnd,ndc/a,nsd,nsc/a,nfet 0 or XDP #give diff nselect priority and-not XDN or TPS shrink 15 grow 15 grow 15 shrink 15 #final nselect templayer FSN bloat-or ndiff,rnd,nfet,nsd,ndc/a,nsc/a,nfet * 60 pdiff,rpd,pdc/a,psd,psc/a,pfet 0 or XDN #never conflict with final pselect and-not FSP #drawn select always goes or TNS shrink 15 grow 15 grow 15 shrink 15 layer CSN FSN calma 45 0 layer CSP FSP calma 44 0 layer CAA diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a,pfet,pfet,fet labels diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a,pfet,pfet,fet calma 43 0 layer CCA ndc/m1,nsc/m1 squares 30 60 90 calma 48 0 layer CCA pdc/m1,psc/m1 squares 30 60 90 calma 48 0 layer CPG poly,rp,nfet,pfet,fet,pc/a labels poly,rp,nfet,pfet,fet,pc/a calma 46 0 layer CCP pc/m1 squares 30 60 90 calma 47 0 layer CCE gc2 squares 0 60 90 calma 55 0 layer CCE p2c,p2m12c squares 30 60 90 calma 55 0 layer CCE gc2 squares 0 60 90 calma 55 0 layer CCC gc squares 0 60 90 calma 25 0 layer CV1 m2c/m1,p2m12c squares 30 60 90 calma 50 0 layer CV1 gv1 squares 0 60 90 calma 50 0 layer CV2 m3c/m2 squares 30 60 90 calma 61 0 layer CV2 gv2 squares 0 60 90 calma 61 0 templayer XPAD1 pad shrink 180 templayer XPAD2 XPAD1 shrink 180 layer CM3 pad labels pad calma 62 0 layer CV2 XPAD2 squares 240 60 300 calma 61 0 layer CM2 pad labels pad calma 51 0 layer CV1 XPAD2 squares 60 60 300 calma 50 0 layer CM1 pad calma 49 0 layer CM1 m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1,p2c,p2m12c labels m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1,p2c,p2m12c calma 49 0 layer CM2 m2,rm2,m2c/m2,m3c/m2,m3c/m2,p2m12c labels m2,rm2,m2c/m2,m3c/m2,m3c/m2,p2m12c calma 51 0 layer CMFP m1p labels m1p calma 81 0 layer CMSP m2p labels m2p calma 82 0 layer 100 fp labels fp calma 100 0 layer 101 fm1 labels fm1 calma 101 0 layer 102 fm2 labels fm2 calma 102 0 layer 103 fm3 labels fm3 calma 103 0 layer 109 fa or fb squares 0 210 120 labels fa calma 109 0 layer 119 fn calma 119 0 layer 110 fapm labels fapm calma 110 0 # layer CPG fp layer CPG fp,fapm squares 0 210 120 labels fp calma 46 0 # layer CM1 fm1 layer CM1 fm1,fapm squares 0 210 120 labels fm1 calma 49 0 # layer CM2 fm2 layer CM2 fm2,fapm squares 0 210 120 labels fm2 calma 51 0 # layer CM3 fm3 layer CM3 fm3,fapm squares 0 210 120 labels fm3 calma 62 0 layer CM3 m3,rm3,m3c/m3 labels m3,rm3,m3c/m3 calma 62 0 layer CMTP m3p labels m3p calma 83 0 layer COG pad shrink 600 labels pad calma 52 0 layer COG glass labels glass calma 52 0 layer CFI nfi,pfi labels nfi,pfi calma 27 0 layer CHR hr,phr labels hr,phr calma 34 0 layer CEL poly2,ecap,phr,p2c,p2m12c labels poly2,ecap,phr,p2c,p2m12c calma 56 0 #CRE/CRM layer CRW rnw,prnw labels rnw,prnw calma 65 0 layer CRG rp,prp labels rp,prp calma 67 0 layer CRD rnd,rpd,prnd,prpd labels rnd,rpd,prnd,prpd calma 66 0 layer CRE rnw,rp,rnd,rpd,rp2 labels rnw,rp,rnd,rpd,rp2 calma 64 0 layer CRF rm1,prm1 labels rm1,prm1 calma 71 0 layer CRS rm2,prm2 labels rm2,prm2 calma 72 0 layer CRG2 rp2,prp2 labels rp2,prp2 calma 68 0 layer CRT rm3,prm3 labels rm3,prm3 calma 73 0 #CRE/CRM layer CRM rm1,prm1,rm2,prm2,rm3,prm3 #CRE/CRM calma 70 0 layer CX comment labels comment calma 63 0 layer XP pad,xp labels pad,xp calma 26 0 style fill-only scalefactor 30 15 layer 100 fp calma 100 0 layer 101 fm1 calma 101 0 layer 102 fm2 calma 102 0 layer 103 fm3 calma 103 0 layer 109 fa or fb calma 109 0 layer 119 fn calma 119 0 style fapm-boxes # this output style creates fill boxes automatically (to meet minimum # density requirements for poly and metal layers) 5 microns outside of # drawn layout IF: 1. you have a flattened version of your chip # 2. over which you paint the special fill layer 'fa', preferably with # a size that is a multiple of 7 + n * (7 + 4), 3. set 'cif # ostype fapm-boxes' and cif out to a file (this actually creates the # fill boxes on cif/strm layer '110' using the magic 'squares' # command), 4. cif in the resulting file (which creates boxes on magic # layer 'fapm') and place this cell onto your chip (and verify absence # of drc errors or shorts), then 5. cif out under your regular cif out # style, where the 'fapm' layer creates fill boxes on poly and all # metal layers. scalefactor 30 15 templayer CRIT fapm,fn,diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a,pfet,pfet,fet,poly,rp,nfet,pfet,fet,pc/a,poly2,ecap,phr,p2c,p2m12c or fm1,m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1,p2c,p2m12c or fm2,m2,rm2,m2c/m2,m3c/m2,m3c/m2,p2m12c or fm3,m3,rm3,m3c/m3 or glass,pad grow 510 and fa layer 110 fa squares 0 210 120 and-not CRIT shrink 90 grow 90 or fapm labels fapm calma 110 0 style fapm-stripes scalefactor 30 15 # this output style creates the above layer 110 as stripes for reduced size # HOWEVER it requires each 'fa' box to first be an exact multiple as above # and then *replacing* the left side (1-lambda wide) stripe of each 'fa' box # to be a 1-lambda wide layer 'fb' box -- else you won't get strips! templayer CRIT fapm,fn,diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a,pfet,pfet,fet,poly,rp,nfet,pfet,fet,pc/a,poly2,ecap,phr,p2c,p2m12c or fm1,m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1,p2c,p2m12c or fm2,m2,rm2,m2c/m2,m3c/m2,m3c/m2,p2m12c or fm3,m3,rm3,m3c/m3 or glass,pad grow 510 and fa templayer FB fa or fb squares 0 210 120 and-not CRIT layer 110 fa squares 0 210 120 and-not CRIT or FB shrink 90 grow 90 or fapm labels fapm calma 110 0 style lambda=0.30(cp) scalefactor 30 15 layer CWN nwell,rnw bloat-or pdiff,rpd,pdc/a,pfet * 180 bloat-or nsd,nsc/a * 90 bloat-or nfi * 120 grow 90 shrink 90 labels nwell,rnw calma 42 0 layer CWP pwell bloat-or ndiff,rnd,ndc/a,nfet * 180 bloat-or psd,psc/a * 90 bloat-or pfi * 120 grow 90 shrink 90 and-not CWN labels pwell calma 41 0 templayer TNS ns templayer TPS ps #we give priority to selects autogenerated around diffusions (vrs. ohmics) #XDP = (pdiff*60) Or ps #XDN = (ndiff*60) Or ns #FSP = ((pdiff*60,psc*60) Or XDP And-Not XDN Or ps shrink-grow #FSN = ((ndiff*60,nsc*60) Or XDN And-Not FDP Or ns shrink-grow #CSN = FSN #CSP = FSP #diffusion auto-nselect (will have priority) templayer XDN bloat-or ndiff,rnd,ndc/a * 60 psd,psc/a 0 or TNS #diffusion auto-pselect (will have priority) templayer XDP bloat-or pdiff,rpd,pdc/a * 60 nsd,nsc/a 0 or TPS #final pselect templayer FSP bloat-or pdiff,rpd,pfet,psd,pdc/a,psc/a,pfet * 60 ndiff,rnd,ndc/a,nsd,nsc/a,nfet 0 or XDP #give diff nselect priority and-not XDN or TPS shrink 15 grow 15 grow 15 shrink 15 #final nselect templayer FSN bloat-or ndiff,rnd,nfet,nsd,ndc/a,nsc/a,nfet * 60 pdiff,rpd,pdc/a,psd,psc/a,pfet 0 or XDN #never conflict with final pselect and-not FSP #drawn select always goes or TNS shrink 15 grow 15 grow 15 shrink 15 layer CSN FSN calma 45 0 layer CSP FSP calma 44 0 layer CAA diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a,pfet,pfet,fet labels diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a,pfet,pfet,fet calma 43 0 layer CCC ndc/m1,nsc/m1 squares 30 60 90 calma 25 0 layer CCC pdc/m1,psc/m1 squares 30 60 90 calma 25 0 layer CPG poly,rp,nfet,pfet,fet,pc/a labels poly,rp,nfet,pfet,fet,pc/a calma 46 0 layer CCC pc/m1 squares 30 60 90 calma 25 0 layer CCC gc2 squares 0 60 90 calma 25 0 layer CCC p2c,p2m12c squares 30 60 90 calma 25 0 layer CCC gc2 squares 0 60 90 calma 25 0 layer CCC gc squares 0 60 90 calma 25 0 layer CV1 m2c/m1,p2m12c squares 30 60 90 calma 50 0 layer CV1 gv1 squares 0 60 90 calma 50 0 layer CV2 m3c/m2 squares 30 60 90 calma 61 0 layer CV2 gv2 squares 0 60 90 calma 61 0 templayer XPAD1 pad shrink 180 templayer XPAD2 XPAD1 shrink 180 layer CM3 pad labels pad calma 62 0 layer CV2 XPAD2 squares 240 60 300 calma 61 0 layer CM2 pad labels pad calma 51 0 layer CV1 XPAD2 squares 60 60 300 calma 50 0 layer CM1 pad calma 49 0 layer CM1 m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1,p2c,p2m12c labels m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1,p2c,p2m12c calma 49 0 layer CM2 m2,rm2,m2c/m2,m3c/m2,m3c/m2,p2m12c labels m2,rm2,m2c/m2,m3c/m2,m3c/m2,p2m12c calma 51 0 layer CMFP m1p labels m1p calma 81 0 layer CMSP m2p labels m2p calma 82 0 layer 100 fp labels fp calma 100 0 layer 101 fm1 labels fm1 calma 101 0 layer 102 fm2 labels fm2 calma 102 0 layer 103 fm3 labels fm3 calma 103 0 layer 109 fa or fb squares 0 210 120 labels fa calma 109 0 layer 119 fn calma 119 0 layer 110 fapm labels fapm calma 110 0 # layer CPG fp layer CPG fp,fapm squares 0 210 120 labels fp calma 46 0 # layer CM1 fm1 layer CM1 fm1,fapm squares 0 210 120 labels fm1 calma 49 0 # layer CM2 fm2 layer CM2 fm2,fapm squares 0 210 120 labels fm2 calma 51 0 # layer CM3 fm3 layer CM3 fm3,fapm squares 0 210 120 labels fm3 calma 62 0 layer CM3 m3,rm3,m3c/m3 labels m3,rm3,m3c/m3 calma 62 0 layer CMTP m3p labels m3p calma 83 0 layer COG pad shrink 600 labels pad calma 52 0 layer COG glass labels glass calma 52 0 layer CFI nfi,pfi labels nfi,pfi calma 27 0 layer CHR hr,phr labels hr,phr calma 34 0 layer CEL poly2,ecap,phr,p2c,p2m12c labels poly2,ecap,phr,p2c,p2m12c calma 56 0 #CRE/CRM layer CRW rnw,prnw labels rnw,prnw calma 65 0 layer CRG rp,prp labels rp,prp calma 67 0 layer CRD rnd,rpd,prnd,prpd labels rnd,rpd,prnd,prpd calma 66 0 layer CRE rnw,rp,rnd,rpd,rp2 labels rnw,rp,rnd,rpd,rp2 calma 64 0 layer CRF rm1,prm1 labels rm1,prm1 calma 71 0 layer CRS rm2,prm2 labels rm2,prm2 calma 72 0 layer CRG2 rp2,prp2 labels rp2,prp2 calma 68 0 layer CRT rm3,prm3 labels rm3,prm3 calma 73 0 #CRE/CRM layer CRM rm1,prm1,rm2,prm2,rm3,prm3 #CRE/CRM calma 70 0 layer CX comment labels comment calma 63 0 layer XP pad,xp labels pad,xp calma 26 0 style lambda=0.30(c) scalefactor 30 15 layer CWN nwell,rnw bloat-or pdiff,rpd,pdc/a,pfet * 180 bloat-or nsd,nsc/a * 90 bloat-or nfi * 120 grow 90 shrink 90 labels nwell,rnw calma 42 0 templayer TNS ns templayer TPS ps #we give priority to selects autogenerated around diffusions (vrs. ohmics) #XDP = (pdiff*60) Or ps #XDN = (ndiff*60) Or ns #FSP = ((pdiff*60,psc*60) Or XDP And-Not XDN Or ps shrink-grow #FSN = ((ndiff*60,nsc*60) Or XDN And-Not FDP Or ns shrink-grow #CSN = FSN #CSP = FSP #diffusion auto-nselect (will have priority) templayer XDN bloat-or ndiff,rnd,ndc/a * 60 psd,psc/a 0 or TNS #diffusion auto-pselect (will have priority) templayer XDP bloat-or pdiff,rpd,pdc/a * 60 nsd,nsc/a 0 or TPS #final pselect templayer FSP bloat-or pdiff,rpd,pfet,psd,pdc/a,psc/a,pfet * 60 ndiff,rnd,ndc/a,nsd,nsc/a,nfet 0 or XDP #give diff nselect priority and-not XDN or TPS shrink 15 grow 15 grow 15 shrink 15 #final nselect templayer FSN bloat-or ndiff,rnd,nfet,nsd,ndc/a,nsc/a,nfet * 60 pdiff,rpd,pdc/a,psd,psc/a,pfet 0 or XDN #never conflict with final pselect and-not FSP #drawn select always goes or TNS shrink 15 grow 15 grow 15 shrink 15 layer CSN FSN calma 45 0 layer CSP FSP calma 44 0 layer CAA diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a,pfet,pfet,fet labels diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a,pfet,pfet,fet calma 43 0 layer CCC ndc/m1,nsc/m1 squares 30 60 90 calma 25 0 layer CCC pdc/m1,psc/m1 squares 30 60 90 calma 25 0 layer CPG poly,rp,nfet,pfet,fet,pc/a labels poly,rp,nfet,pfet,fet,pc/a calma 46 0 layer CCC pc/m1 squares 30 60 90 calma 25 0 layer CCC gc2 squares 0 60 90 calma 25 0 layer CCC p2c,p2m12c squares 30 60 90 calma 25 0 layer CCC gc2 squares 0 60 90 calma 25 0 layer CCC gc squares 0 60 90 calma 25 0 layer CV1 m2c/m1,p2m12c squares 30 60 90 calma 50 0 layer CV1 gv1 squares 0 60 90 calma 50 0 layer CV2 m3c/m2 squares 30 60 90 calma 61 0 layer CV2 gv2 squares 0 60 90 calma 61 0 templayer XPAD1 pad shrink 180 templayer XPAD2 XPAD1 shrink 180 layer CM3 pad labels pad calma 62 0 layer CV2 XPAD2 squares 240 60 300 calma 61 0 layer CM2 pad labels pad calma 51 0 layer CV1 XPAD2 squares 60 60 300 calma 50 0 layer CM1 pad calma 49 0 layer CM1 m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1,p2c,p2m12c labels m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1,p2c,p2m12c calma 49 0 layer CM2 m2,rm2,m2c/m2,m3c/m2,m3c/m2,p2m12c labels m2,rm2,m2c/m2,m3c/m2,m3c/m2,p2m12c calma 51 0 layer CMFP m1p labels m1p calma 81 0 layer CMSP m2p labels m2p calma 82 0 layer 100 fp labels fp calma 100 0 layer 101 fm1 labels fm1 calma 101 0 layer 102 fm2 labels fm2 calma 102 0 layer 103 fm3 labels fm3 calma 103 0 layer 109 fa or fb squares 0 210 120 labels fa calma 109 0 layer 119 fn calma 119 0 layer 110 fapm labels fapm calma 110 0 # layer CPG fp layer CPG fp,fapm squares 0 210 120 labels fp calma 46 0 # layer CM1 fm1 layer CM1 fm1,fapm squares 0 210 120 labels fm1 calma 49 0 # layer CM2 fm2 layer CM2 fm2,fapm squares 0 210 120 labels fm2 calma 51 0 # layer CM3 fm3 layer CM3 fm3,fapm squares 0 210 120 labels fm3 calma 62 0 layer CM3 m3,rm3,m3c/m3 labels m3,rm3,m3c/m3 calma 62 0 layer CMTP m3p labels m3p calma 83 0 layer COG pad shrink 600 labels pad calma 52 0 layer COG glass labels glass calma 52 0 layer CFI nfi,pfi labels nfi,pfi calma 27 0 layer CHR hr,phr labels hr,phr calma 34 0 layer CEL poly2,ecap,phr,p2c,p2m12c labels poly2,ecap,phr,p2c,p2m12c calma 56 0 #CRE/CRM layer CRW rnw,prnw labels rnw,prnw calma 65 0 layer CRG rp,prp labels rp,prp calma 67 0 layer CRD rnd,rpd,prnd,prpd labels rnd,rpd,prnd,prpd calma 66 0 layer CRE rnw,rp,rnd,rpd,rp2 labels rnw,rp,rnd,rpd,rp2 calma 64 0 layer CRF rm1,prm1 labels rm1,prm1 calma 71 0 layer CRS rm2,prm2 labels rm2,prm2 calma 72 0 layer CRG2 rp2,prp2 labels rp2,prp2 calma 68 0 layer CRT rm3,prm3 labels rm3,prm3 calma 73 0 #CRE/CRM layer CRM rm1,prm1,rm2,prm2,rm3,prm3 #CRE/CRM calma 70 0 layer CX comment labels comment calma 63 0 layer XP pad,xp labels pad,xp calma 26 0 style lambda=0.30() scalefactor 30 15 layer CWN nwell,rnw bloat-or pdiff,rpd,pdc/a,pfet * 180 bloat-or nsd,nsc/a * 90 bloat-or nfi * 120 grow 90 shrink 90 labels nwell,rnw calma 42 0 templayer TNS ns templayer TPS ps #we give priority to selects autogenerated around diffusions (vrs. ohmics) #XDP = (pdiff*60) Or ps #XDN = (ndiff*60) Or ns #FSP = ((pdiff*60,psc*60) Or XDP And-Not XDN Or ps shrink-grow #FSN = ((ndiff*60,nsc*60) Or XDN And-Not FDP Or ns shrink-grow #CSN = FSN #CSP = FSP #diffusion auto-nselect (will have priority) templayer XDN bloat-or ndiff,rnd,ndc/a * 60 psd,psc/a 0 or TNS #diffusion auto-pselect (will have priority) templayer XDP bloat-or pdiff,rpd,pdc/a * 60 nsd,nsc/a 0 or TPS #final pselect templayer FSP bloat-or pdiff,rpd,pfet,psd,pdc/a,psc/a,pfet * 60 ndiff,rnd,ndc/a,nsd,nsc/a,nfet 0 or XDP #give diff nselect priority and-not XDN or TPS shrink 15 grow 15 grow 15 shrink 15 #final nselect templayer FSN bloat-or ndiff,rnd,nfet,nsd,ndc/a,nsc/a,nfet * 60 pdiff,rpd,pdc/a,psd,psc/a,pfet 0 or XDN #never conflict with final pselect and-not FSP #drawn select always goes or TNS shrink 15 grow 15 grow 15 shrink 15 layer CSN FSN calma 45 0 layer CSP FSP calma 44 0 layer CAA diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a,pfet,pfet,fet labels diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a,pfet,pfet,fet calma 43 0 layer CCA ndc/m1,nsc/m1 squares 30 60 90 calma 48 0 layer CCA pdc/m1,psc/m1 squares 30 60 90 calma 48 0 layer CPG poly,rp,nfet,pfet,fet,pc/a labels poly,rp,nfet,pfet,fet,pc/a calma 46 0 layer CCP pc/m1 squares 30 60 90 calma 47 0 layer CCE gc2 squares 0 60 90 calma 55 0 layer CCE p2c,p2m12c squares 30 60 90 calma 55 0 layer CCE gc2 squares 0 60 90 calma 55 0 layer CCC gc squares 0 60 90 calma 25 0 layer CV1 m2c/m1,p2m12c squares 30 60 90 calma 50 0 layer CV1 gv1 squares 0 60 90 calma 50 0 layer CV2 m3c/m2 squares 30 60 90 calma 61 0 layer CV2 gv2 squares 0 60 90 calma 61 0 templayer XPAD1 pad shrink 180 templayer XPAD2 XPAD1 shrink 180 layer CM3 pad labels pad calma 62 0 layer CV2 XPAD2 squares 240 60 300 calma 61 0 layer CM2 pad labels pad calma 51 0 layer CV1 XPAD2 squares 60 60 300 calma 50 0 layer CM1 pad calma 49 0 layer CM1 m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1,p2c,p2m12c labels m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1,p2c,p2m12c calma 49 0 layer CM2 m2,rm2,m2c/m2,m3c/m2,m3c/m2,p2m12c labels m2,rm2,m2c/m2,m3c/m2,m3c/m2,p2m12c calma 51 0 layer CMFP m1p labels m1p calma 81 0 layer CMSP m2p labels m2p calma 82 0 layer 100 fp labels fp calma 100 0 layer 101 fm1 labels fm1 calma 101 0 layer 102 fm2 labels fm2 calma 102 0 layer 103 fm3 labels fm3 calma 103 0 layer 109 fa or fb squares 0 210 120 labels fa calma 109 0 layer 119 fn calma 119 0 layer 110 fapm labels fapm calma 110 0 # layer CPG fp layer CPG fp,fapm squares 0 210 120 labels fp calma 46 0 # layer CM1 fm1 layer CM1 fm1,fapm squares 0 210 120 labels fm1 calma 49 0 # layer CM2 fm2 layer CM2 fm2,fapm squares 0 210 120 labels fm2 calma 51 0 # layer CM3 fm3 layer CM3 fm3,fapm squares 0 210 120 labels fm3 calma 62 0 layer CM3 m3,rm3,m3c/m3 labels m3,rm3,m3c/m3 calma 62 0 layer CMTP m3p labels m3p calma 83 0 layer COG pad shrink 600 labels pad calma 52 0 layer COG glass labels glass calma 52 0 layer CFI nfi,pfi labels nfi,pfi calma 27 0 layer CHR hr,phr labels hr,phr calma 34 0 layer CEL poly2,ecap,phr,p2c,p2m12c labels poly2,ecap,phr,p2c,p2m12c calma 56 0 #CRE/CRM layer CRW rnw,prnw labels rnw,prnw calma 65 0 layer CRG rp,prp labels rp,prp calma 67 0 layer CRD rnd,rpd,prnd,prpd labels rnd,rpd,prnd,prpd calma 66 0 layer CRE rnw,rp,rnd,rpd,rp2 labels rnw,rp,rnd,rpd,rp2 calma 64 0 layer CRF rm1,prm1 labels rm1,prm1 calma 71 0 layer CRS rm2,prm2 labels rm2,prm2 calma 72 0 layer CRG2 rp2,prp2 labels rp2,prp2 calma 68 0 layer CRT rm3,prm3 labels rm3,prm3 calma 73 0 #CRE/CRM layer CRM rm1,prm1,rm2,prm2,rm3,prm3 #CRE/CRM calma 70 0 layer CX comment labels comment calma 63 0 layer XP pad,xp labels pad,xp calma 26 0 end cifinput style lambda=0.30(p) scalefactor 30 layer nwell CWN and-not CWNR and-not CTA labels CWN calma CWN 42 * layer rnw CWN and-not CWNR and CRE and-not CSB and-not CRD and-not CAA and-not CPG calma CWN 42 * layer rnw CWN and-not CWNR and CRW and-not CRD and-not CAA and-not CPG calma CWN 42 * layer pseudo_rnwell CRW and-not CRE calma CRW 65 * layer pwell CWP and-not CTA labels CWP calma CWP 41 * layer diff CAA and-not CTA and-not CPG and-not CWNR and-not COP and-not CSN and-not CSP labels CAA calma CAA 43 * layer tran CAA and-not CTA and CPG and-not CWNR and-not COP and-not CSN and-not CSP labels CAA calma CAA 43 * calma CSN 45 * calma CSP 44 * layer ndiff CAA and CSN and-not CWNR and-not CTA and-not CRE and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer rnd CAA and CSN and-not CWNR and CRE and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA calma CAA 43 * layer rnd CAA and CSN and-not CWNR and CRD and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA calma CAA 43 * layer pseudo_rndiff CRD and-not CRE and-not CAA and-not CSB and-not CPG and-not CWN and-not CSP and CSN and-not CBA calma CRD 66 * layer pdiff CAA and CSP and-not CWNR and-not CTA and-not CRE and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer rpd CAA and CSP and-not CWNR and CRE and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CAA 43 * layer rpd CAA and CSP and-not CWNR and CRD and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CAA 43 * layer pseudo_rpdiff CRD and-not CRE and-not CAA and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CRD 66 * layer nfet CAA and CSN and-not CWNR and-not CTA and CPG and-not CEL and-not CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer pfet CAA and CSP and-not CWNR and-not CTA and CPG and-not CEL and CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer nsd CAA and CSN and-not CWNR and-not CTA and CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer psd CAA and CSP and-not CWNR and-not CTA and-not CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer ndc CAA and CSN and CCA and-not CV1 and-not CWNR and-not CTA and-not CWN and CM1 grow 30 grow 15 shrink 15 calma CCA 48 * layer ndc CAA and CSN and CCC and-not CV1 and-not CWNR and-not CTA and-not CWN and CM1 grow 30 grow 15 shrink 15 calma CCC 25 * layer nsc CAA and CSN and CCA and-not CV1 and-not CWNR and-not CTA and CWN and CM1 grow 30 grow 15 shrink 15 calma CCA 48 * layer nsc CAA and CSN and CCC and-not CV1 and-not CWNR and-not CTA and CWN and CM1 grow 30 grow 15 shrink 15 calma CCC 25 * layer pdc CAA and CSP and CCA and-not CV1 and-not CTA and-not CPS and CWN and CM1 grow 30 grow 15 shrink 15 calma CCA 48 * layer pdc CAA and CSP and CCC and-not CV1 and-not CTA and-not CPS and CWN and CM1 grow 30 grow 15 shrink 15 calma CCC 25 * layer psc CAA and CSP and CCA and-not CV1 and-not CTA and-not CPS and-not CWN and CM1 grow 30 grow 15 shrink 15 calma CCA 48 * layer psc CAA and CSP and CCC and-not CV1 and-not CWNR and-not CTA and-not CPS and-not CWN and CM1 grow 30 grow 15 shrink 15 calma CCC 25 * layer ndc CAA and CSN and CCA and CV1 and CV2 and-not CWNR and-not CTA and-not CWN and CM1 grow 30 grow 15 shrink 15 calma CCA 48 * layer ndc CAA and CSN and CCC and CV1 and CV2 and-not CWNR and-not CTA and-not CWN and CM1 grow 30 grow 15 shrink 15 calma CCC 25 * layer nsc CAA and CSN and CCA and CV1 and CV2 and-not CWNR and-not CTA and CWN and CM1 grow 30 grow 15 shrink 15 calma CCA 48 * layer nsc CAA and CSN and CCC and CV1 and CV2 and-not CWNR and-not CTA and CWN and CM1 grow 30 grow 15 shrink 15 calma CCC 25 * layer pdc CAA and CSP and CCA and CV1 and CV2 and-not CTA and-not CPS and CWN and CM1 grow 30 grow 15 shrink 15 calma CCA 48 * layer pdc CAA and CSP and CCC and CV1 and CV2 and-not CTA and-not CPS and CWN and CM1 grow 30 grow 15 shrink 15 calma CCC 25 * layer psc CAA and CSP and CCA and CV1 and CV2 and-not CTA and-not CPS and-not CWN and CM1 grow 30 grow 15 shrink 15 calma CCA 48 * layer psc CAA and CSP and CCC and CV1 and CV2 and-not CWNR and-not CTA and-not CPS and-not CWN and CM1 grow 30 grow 15 shrink 15 calma CCC 25 * layer poly CPG and-not CRE labels CPG calma CPG 46 * layer rp CPG and CRE and-not CSB calma CPG 46 * layer rp CPG and CRG calma CPG 46 * layer pseudo_rpoly CRG and-not CRE calma CRG 67 * layer pc CCP and-not CV1 and CPG and-not CPC and-not CEL and-not CAA grow 30 and CM1 grow 15 shrink 15 calma CCP 47 * layer pc CCC and-not CV1 and CPG and-not CPC and-not CEL and-not CAA grow 30 and CM1 grow 15 shrink 15 calma CCC 25 * layer pc CCP and CV1 and CV2 and CPG and-not CPC and-not CEL and-not CAA grow 30 and CM1 grow 15 shrink 15 calma CCP 47 * layer pc CCC and CV1 and CV2 and CPG and-not CPC and-not CEL and-not CAA grow 30 and CM1 grow 15 shrink 15 calma CCC 25 * layer p2c CCE and-not CV1 and CPG and CEL and-not CPC and-not CAA grow 30 and CM1 grow 15 shrink 15 calma CCE 55 * layer p2c CCC and-not CV1 and CPG and CEL and-not CPC and-not CAA grow 30 and CM1 grow 15 shrink 15 calma CCC 25 * layer p2c CCE and CV1 and CV2 and CPG and CEL and-not CPC and-not CAA grow 30 and CM1 grow 15 shrink 15 calma CCE 55 * layer p2c CCC and CV1 and CV2 and CPG and CEL and-not CPC and-not CAA grow 30 and CM1 grow 15 shrink 15 calma CCC 25 * layer gc CCP and-not CPG and-not CPC calma CCP 47 * layer gc CCP and-not CM1 calma CCP 47 * layer gc CCA and-not COP and-not CAA and-not CBA calma CCA 48 * layer gc CCA and-not COP and-not CM1 calma CCA 48 * layer gc CCC and-not COP and-not CPG and-not CPC and-not CEL and-not CAA and-not CBA calma CCC 25 * layer gc CCC and-not COP and-not CM1 calma CCC 25 * layer gc2 CCE and-not CPC and-not CEL calma CCE 55 * layer gc2 CCE and-not CM1 calma CCE 55 * layer gv1 CV1 and-not COP and-not CM1 calma CV1 50 * layer gv1 CV1 and-not COP and-not CM2 calma CV1 50 * layer gv2 CV2 and-not COP and-not CM2 calma CV2 61 * layer gv2 CV2 and-not COP and-not CM3 calma CV2 61 * layer m2c CV1 and-not CV2 and-not CCC and-not CCE and-not CCP and-not CCA and-not XP grow 30 and CM2 and CM1 grow 15 shrink 15 calma CV1 50 * layer p2m12c CV1 and-not CV2 and CCE grow 30 and CM2 and CM1 and CPG and CEL grow 15 shrink 15 calma CV1 50 * layer p2m12c CV1 and-not CV2 and CCC grow 30 and CM2 and CM1 and CPG and CEL grow 15 shrink 15 calma CV1 50 * layer m1 CM1 and-not CRM and-not CRF and-not XP labels CM1 calma CM1 49 * layer rm1 CRM and CM1 calma CRM 70 * layer rm1 CRF and CM1 calma CRF 71 * layer pseudo_rmetal1 CRF and-not rm1 calma CRF 71 * layer m1p CMFP labels CMFP calma CMFP 81 * layer m2 CM2 and-not CRM and-not CRS and-not XP labels CM2 calma CM2 51 * layer rm2 CRM and CM2 calma CRM 70 * layer rm2 CRS and CM2 calma CRS 72 * layer pseudo_rmetal2 CRS and-not rm2 calma CRS 72 * layer m2p CMSP labels CMSP calma CMSP 82 * layer fp 100 calma 100 100 * layer fm1 101 calma 101 101 * layer fm2 102 calma 102 102 * layer fm3 103 calma 103 103 * layer fa 109 calma 109 109 * layer fn 119 calma 119 119 * layer fapm 110 calma 110 110 * layer m3c CV2 and-not CV1 and-not XP grow 30 and CM3 and CM2 grow 15 shrink 15 calma CV2 61 * layer m3 CM3 and-not CRM and-not CRT and-not XP labels CM3 calma CM3 62 * layer rm3 CRM and CM3 calma CRM 70 * layer rm3 CRT and CM3 calma CRT 73 * layer pseudo_rmetal3 CRT and-not rm3 calma CRT 73 * layer m3p CMTP labels CMTP calma CMTP 83 * layer pad XP labels pad calma XP 26 * layer glass COG and-not COP and-not XP labels COG calma COG 52 * layer nfi CFI and CWN labels CFI calma CFI 27 * layer pfi CFI and-not CWN labels CFI calma CFI 27 * layer hr CHR labels CHR calma CHR 34 * layer phr CEL and CHR calma CEL 56 * layer ecap CEL and CPG labels CEL calma CEL 56 * layer poly2 CEL and-not CPG labels CEL calma CEL 56 * layer rp2 CEL and CRG2 calma CEL 56 * layer pseudo_rpoly2 CRG2 and-not CRE calma CRG2 68 * layer comment CX labels CX calma CX 63 * calma CTA 60 * calma CRW 65 * calma CRG 67 * calma CRD 66 * calma CRE 64 * calma CRF 71 * calma CRS 72 * calma CRT 73 * calma CRM 70 * style lambda=0.30(s) scalefactor 30 layer nwell CWN and-not CWNR and-not CTA labels CWN calma CWN 42 * layer rnw CWN and-not CWNR and CRE and-not CSB and-not CRD and-not CAA and-not CPG calma CWN 42 * layer rnw CWN and-not CWNR and CRW and-not CRD and-not CAA and-not CPG calma CWN 42 * layer pseudo_rnwell CRW and-not CRE calma CRW 65 * ignore CWP calma CWP 41 * layer diff CAA and-not CTA and-not CPG and-not CWNR and-not COP and-not CSN and-not CSP labels CAA calma CAA 43 * layer tran CAA and-not CTA and CPG and-not CWNR and-not COP and-not CSN and-not CSP labels CAA calma CAA 43 * layer nselect CSN calma CSN 45 * layer pselect CSP calma CSP 44 * layer ndiff CAA and CSN and-not CWNR and-not CTA and-not CRE and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer rnd CAA and CSN and-not CWNR and CRE and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA calma CAA 43 * layer rnd CAA and CSN and-not CWNR and CRD and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA calma CAA 43 * layer pseudo_rndiff CRD and-not CRE and-not CAA and-not CSB and-not CPG and-not CWN and-not CSP and CSN and-not CBA calma CRD 66 * layer pdiff CAA and CSP and-not CWNR and-not CTA and-not CRE and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer rpd CAA and CSP and-not CWNR and CRE and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CAA 43 * layer rpd CAA and CSP and-not CWNR and CRD and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CAA 43 * layer pseudo_rpdiff CRD and-not CRE and-not CAA and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CRD 66 * layer nfet CAA and CSN and-not CWNR and-not CTA and CPG and-not CEL and-not CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer pfet CAA and CSP and-not CWNR and-not CTA and CPG and-not CEL and CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer nsd CAA and CSN and-not CWNR and-not CTA and CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer psd CAA and CSP and-not CWNR and-not CTA and-not CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer ndc CAA and CSN and CCA and-not CV1 and-not CWNR and-not CTA and-not CWN and CM1 grow 30 grow 15 shrink 15 calma CCA 48 * layer ndc CAA and CSN and CCC and-not CV1 and-not CWNR and-not CTA and-not CWN and CM1 grow 30 grow 15 shrink 15 calma CCC 25 * layer nsc CAA and CSN and CCA and-not CV1 and-not CWNR and-not CTA and CWN and CM1 grow 30 grow 15 shrink 15 calma CCA 48 * layer nsc CAA and CSN and CCC and-not CV1 and-not CWNR and-not CTA and CWN and CM1 grow 30 grow 15 shrink 15 calma CCC 25 * layer pdc CAA and CSP and CCA and-not CV1 and-not CTA and-not CPS and CWN and CM1 grow 30 grow 15 shrink 15 calma CCA 48 * layer pdc CAA and CSP and CCC and-not CV1 and-not CTA and-not CPS and CWN and CM1 grow 30 grow 15 shrink 15 calma CCC 25 * layer psc CAA and CSP and CCA and-not CV1 and-not CTA and-not CPS and-not CWN and CM1 grow 30 grow 15 shrink 15 calma CCA 48 * layer psc CAA and CSP and CCC and-not CV1 and-not CWNR and-not CTA and-not CPS and-not CWN and CM1 grow 30 grow 15 shrink 15 calma CCC 25 * layer ndc CAA and CSN and CCA and CV1 and CV2 and-not CWNR and-not CTA and-not CWN and CM1 grow 30 grow 15 shrink 15 calma CCA 48 * layer ndc CAA and CSN and CCC and CV1 and CV2 and-not CWNR and-not CTA and-not CWN and CM1 grow 30 grow 15 shrink 15 calma CCC 25 * layer nsc CAA and CSN and CCA and CV1 and CV2 and-not CWNR and-not CTA and CWN and CM1 grow 30 grow 15 shrink 15 calma CCA 48 * layer nsc CAA and CSN and CCC and CV1 and CV2 and-not CWNR and-not CTA and CWN and CM1 grow 30 grow 15 shrink 15 calma CCC 25 * layer pdc CAA and CSP and CCA and CV1 and CV2 and-not CTA and-not CPS and CWN and CM1 grow 30 grow 15 shrink 15 calma CCA 48 * layer pdc CAA and CSP and CCC and CV1 and CV2 and-not CTA and-not CPS and CWN and CM1 grow 30 grow 15 shrink 15 calma CCC 25 * layer psc CAA and CSP and CCA and CV1 and CV2 and-not CTA and-not CPS and-not CWN and CM1 grow 30 grow 15 shrink 15 calma CCA 48 * layer psc CAA and CSP and CCC and CV1 and CV2 and-not CWNR and-not CTA and-not CPS and-not CWN and CM1 grow 30 grow 15 shrink 15 calma CCC 25 * layer poly CPG and-not CRE labels CPG calma CPG 46 * layer rp CPG and CRE and-not CSB calma CPG 46 * layer rp CPG and CRG calma CPG 46 * layer pseudo_rpoly CRG and-not CRE calma CRG 67 * layer pc CCP and-not CV1 and CPG and-not CPC and-not CEL and-not CAA grow 30 and CM1 grow 15 shrink 15 calma CCP 47 * layer pc CCC and-not CV1 and CPG and-not CPC and-not CEL and-not CAA grow 30 and CM1 grow 15 shrink 15 calma CCC 25 * layer pc CCP and CV1 and CV2 and CPG and-not CPC and-not CEL and-not CAA grow 30 and CM1 grow 15 shrink 15 calma CCP 47 * layer pc CCC and CV1 and CV2 and CPG and-not CPC and-not CEL and-not CAA grow 30 and CM1 grow 15 shrink 15 calma CCC 25 * layer p2c CCE and-not CV1 and CPG and CEL and-not CPC and-not CAA grow 30 and CM1 grow 15 shrink 15 calma CCE 55 * layer p2c CCC and-not CV1 and CPG and CEL and-not CPC and-not CAA grow 30 and CM1 grow 15 shrink 15 calma CCC 25 * layer p2c CCE and CV1 and CV2 and CPG and CEL and-not CPC and-not CAA grow 30 and CM1 grow 15 shrink 15 calma CCE 55 * layer p2c CCC and CV1 and CV2 and CPG and CEL and-not CPC and-not CAA grow 30 and CM1 grow 15 shrink 15 calma CCC 25 * layer gc CCP and-not CPG and-not CPC calma CCP 47 * layer gc CCP and-not CM1 calma CCP 47 * layer gc CCA and-not COP and-not CAA and-not CBA calma CCA 48 * layer gc CCA and-not COP and-not CM1 calma CCA 48 * layer gc CCC and-not COP and-not CPG and-not CPC and-not CEL and-not CAA and-not CBA calma CCC 25 * layer gc CCC and-not COP and-not CM1 calma CCC 25 * layer gc2 CCE and-not CPC and-not CEL calma CCE 55 * layer gc2 CCE and-not CM1 calma CCE 55 * layer gv1 CV1 and-not COP and-not CM1 calma CV1 50 * layer gv1 CV1 and-not COP and-not CM2 calma CV1 50 * layer gv2 CV2 and-not COP and-not CM2 calma CV2 61 * layer gv2 CV2 and-not COP and-not CM3 calma CV2 61 * layer m2c CV1 and-not CV2 and-not CCC and-not CCE and-not CCP and-not CCA and-not XP grow 30 and CM2 and CM1 grow 15 shrink 15 calma CV1 50 * layer p2m12c CV1 and-not CV2 and CCE grow 30 and CM2 and CM1 and CPG and CEL grow 15 shrink 15 calma CV1 50 * layer p2m12c CV1 and-not CV2 and CCC grow 30 and CM2 and CM1 and CPG and CEL grow 15 shrink 15 calma CV1 50 * layer m1 CM1 and-not CRM and-not CRF and-not XP labels CM1 calma CM1 49 * layer rm1 CRM and CM1 calma CRM 70 * layer rm1 CRF and CM1 calma CRF 71 * layer pseudo_rmetal1 CRF and-not rm1 calma CRF 71 * layer m1p CMFP labels CMFP calma CMFP 81 * layer m2 CM2 and-not CRM and-not CRS and-not XP labels CM2 calma CM2 51 * layer rm2 CRM and CM2 calma CRM 70 * layer rm2 CRS and CM2 calma CRS 72 * layer pseudo_rmetal2 CRS and-not rm2 calma CRS 72 * layer m2p CMSP labels CMSP calma CMSP 82 * layer fp 100 calma 100 100 * layer fm1 101 calma 101 101 * layer fm2 102 calma 102 102 * layer fm3 103 calma 103 103 * layer fa 109 calma 109 109 * layer fn 119 calma 119 119 * layer fapm 110 calma 110 110 * layer m3c CV2 and-not CV1 and-not XP grow 30 and CM3 and CM2 grow 15 shrink 15 calma CV2 61 * layer m3 CM3 and-not CRM and-not CRT and-not XP labels CM3 calma CM3 62 * layer rm3 CRM and CM3 calma CRM 70 * layer rm3 CRT and CM3 calma CRT 73 * layer pseudo_rmetal3 CRT and-not rm3 calma CRT 73 * layer m3p CMTP labels CMTP calma CMTP 83 * layer pad XP labels pad calma XP 26 * layer glass COG and-not COP and-not XP labels COG calma COG 52 * layer nfi CFI and CWN labels CFI calma CFI 27 * layer pfi CFI and-not CWN labels CFI calma CFI 27 * layer hr CHR labels CHR calma CHR 34 * layer phr CEL and CHR calma CEL 56 * layer ecap CEL and CPG labels CEL calma CEL 56 * layer poly2 CEL and-not CPG labels CEL calma CEL 56 * layer rp2 CEL and CRG2 calma CEL 56 * layer pseudo_rpoly2 CRG2 and-not CRE calma CRG2 68 * layer comment CX labels CX calma CX 63 * calma CTA 60 * calma CRW 65 * calma CRG 67 * calma CRD 66 * calma CRE 64 * calma CRF 71 * calma CRS 72 * calma CRT 73 * calma CRM 70 * style lambda=0.30(ps) scalefactor 30 layer nwell CWN and-not CWNR and-not CTA labels CWN calma CWN 42 * layer rnw CWN and-not CWNR and CRE and-not CSB and-not CRD and-not CAA and-not CPG calma CWN 42 * layer rnw CWN and-not CWNR and CRW and-not CRD and-not CAA and-not CPG calma CWN 42 * layer pseudo_rnwell CRW and-not CRE calma CRW 65 * layer pwell CWP and-not CTA labels CWP calma CWP 41 * layer diff CAA and-not CTA and-not CPG and-not CWNR and-not COP and-not CSN and-not CSP labels CAA calma CAA 43 * layer tran CAA and-not CTA and CPG and-not CWNR and-not COP and-not CSN and-not CSP labels CAA calma CAA 43 * layer nselect CSN calma CSN 45 * layer pselect CSP calma CSP 44 * layer ndiff CAA and CSN and-not CWNR and-not CTA and-not CRE and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer rnd CAA and CSN and-not CWNR and CRE and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA calma CAA 43 * layer rnd CAA and CSN and-not CWNR and CRD and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA calma CAA 43 * layer pseudo_rndiff CRD and-not CRE and-not CAA and-not CSB and-not CPG and-not CWN and-not CSP and CSN and-not CBA calma CRD 66 * layer pdiff CAA and CSP and-not CWNR and-not CTA and-not CRE and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer rpd CAA and CSP and-not CWNR and CRE and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CAA 43 * layer rpd CAA and CSP and-not CWNR and CRD and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CAA 43 * layer pseudo_rpdiff CRD and-not CRE and-not CAA and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CRD 66 * layer nfet CAA and CSN and-not CWNR and-not CTA and CPG and-not CEL and-not CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer pfet CAA and CSP and-not CWNR and-not CTA and CPG and-not CEL and CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer nsd CAA and CSN and-not CWNR and-not CTA and CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer psd CAA and CSP and-not CWNR and-not CTA and-not CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer ndc CAA and CSN and CCA and-not CV1 and-not CWNR and-not CTA and-not CWN and CM1 grow 30 grow 15 shrink 15 calma CCA 48 * layer ndc CAA and CSN and CCC and-not CV1 and-not CWNR and-not CTA and-not CWN and CM1 grow 30 grow 15 shrink 15 calma CCC 25 * layer nsc CAA and CSN and CCA and-not CV1 and-not CWNR and-not CTA and CWN and CM1 grow 30 grow 15 shrink 15 calma CCA 48 * layer nsc CAA and CSN and CCC and-not CV1 and-not CWNR and-not CTA and CWN and CM1 grow 30 grow 15 shrink 15 calma CCC 25 * layer pdc CAA and CSP and CCA and-not CV1 and-not CTA and-not CPS and CWN and CM1 grow 30 grow 15 shrink 15 calma CCA 48 * layer pdc CAA and CSP and CCC and-not CV1 and-not CTA and-not CPS and CWN and CM1 grow 30 grow 15 shrink 15 calma CCC 25 * layer psc CAA and CSP and CCA and-not CV1 and-not CTA and-not CPS and-not CWN and CM1 grow 30 grow 15 shrink 15 calma CCA 48 * layer psc CAA and CSP and CCC and-not CV1 and-not CWNR and-not CTA and-not CPS and-not CWN and CM1 grow 30 grow 15 shrink 15 calma CCC 25 * layer ndc CAA and CSN and CCA and CV1 and CV2 and-not CWNR and-not CTA and-not CWN and CM1 grow 30 grow 15 shrink 15 calma CCA 48 * layer ndc CAA and CSN and CCC and CV1 and CV2 and-not CWNR and-not CTA and-not CWN and CM1 grow 30 grow 15 shrink 15 calma CCC 25 * layer nsc CAA and CSN and CCA and CV1 and CV2 and-not CWNR and-not CTA and CWN and CM1 grow 30 grow 15 shrink 15 calma CCA 48 * layer nsc CAA and CSN and CCC and CV1 and CV2 and-not CWNR and-not CTA and CWN and CM1 grow 30 grow 15 shrink 15 calma CCC 25 * layer pdc CAA and CSP and CCA and CV1 and CV2 and-not CTA and-not CPS and CWN and CM1 grow 30 grow 15 shrink 15 calma CCA 48 * layer pdc CAA and CSP and CCC and CV1 and CV2 and-not CTA and-not CPS and CWN and CM1 grow 30 grow 15 shrink 15 calma CCC 25 * layer psc CAA and CSP and CCA and CV1 and CV2 and-not CTA and-not CPS and-not CWN and CM1 grow 30 grow 15 shrink 15 calma CCA 48 * layer psc CAA and CSP and CCC and CV1 and CV2 and-not CWNR and-not CTA and-not CPS and-not CWN and CM1 grow 30 grow 15 shrink 15 calma CCC 25 * layer poly CPG and-not CRE labels CPG calma CPG 46 * layer rp CPG and CRE and-not CSB calma CPG 46 * layer rp CPG and CRG calma CPG 46 * layer pseudo_rpoly CRG and-not CRE calma CRG 67 * layer pc CCP and-not CV1 and CPG and-not CPC and-not CEL and-not CAA grow 30 and CM1 grow 15 shrink 15 calma CCP 47 * layer pc CCC and-not CV1 and CPG and-not CPC and-not CEL and-not CAA grow 30 and CM1 grow 15 shrink 15 calma CCC 25 * layer pc CCP and CV1 and CV2 and CPG and-not CPC and-not CEL and-not CAA grow 30 and CM1 grow 15 shrink 15 calma CCP 47 * layer pc CCC and CV1 and CV2 and CPG and-not CPC and-not CEL and-not CAA grow 30 and CM1 grow 15 shrink 15 calma CCC 25 * layer p2c CCE and-not CV1 and CPG and CEL and-not CPC and-not CAA grow 30 and CM1 grow 15 shrink 15 calma CCE 55 * layer p2c CCC and-not CV1 and CPG and CEL and-not CPC and-not CAA grow 30 and CM1 grow 15 shrink 15 calma CCC 25 * layer p2c CCE and CV1 and CV2 and CPG and CEL and-not CPC and-not CAA grow 30 and CM1 grow 15 shrink 15 calma CCE 55 * layer p2c CCC and CV1 and CV2 and CPG and CEL and-not CPC and-not CAA grow 30 and CM1 grow 15 shrink 15 calma CCC 25 * layer gc CCP and-not CPG and-not CPC calma CCP 47 * layer gc CCP and-not CM1 calma CCP 47 * layer gc CCA and-not COP and-not CAA and-not CBA calma CCA 48 * layer gc CCA and-not COP and-not CM1 calma CCA 48 * layer gc CCC and-not COP and-not CPG and-not CPC and-not CEL and-not CAA and-not CBA calma CCC 25 * layer gc CCC and-not COP and-not CM1 calma CCC 25 * layer gc2 CCE and-not CPC and-not CEL calma CCE 55 * layer gc2 CCE and-not CM1 calma CCE 55 * layer gv1 CV1 and-not COP and-not CM1 calma CV1 50 * layer gv1 CV1 and-not COP and-not CM2 calma CV1 50 * layer gv2 CV2 and-not COP and-not CM2 calma CV2 61 * layer gv2 CV2 and-not COP and-not CM3 calma CV2 61 * layer m2c CV1 and-not CV2 and-not CCC and-not CCE and-not CCP and-not CCA and-not XP grow 30 and CM2 and CM1 grow 15 shrink 15 calma CV1 50 * layer p2m12c CV1 and-not CV2 and CCE grow 30 and CM2 and CM1 and CPG and CEL grow 15 shrink 15 calma CV1 50 * layer p2m12c CV1 and-not CV2 and CCC grow 30 and CM2 and CM1 and CPG and CEL grow 15 shrink 15 calma CV1 50 * layer m1 CM1 and-not CRM and-not CRF and-not XP labels CM1 calma CM1 49 * layer rm1 CRM and CM1 calma CRM 70 * layer rm1 CRF and CM1 calma CRF 71 * layer pseudo_rmetal1 CRF and-not rm1 calma CRF 71 * layer m1p CMFP labels CMFP calma CMFP 81 * layer m2 CM2 and-not CRM and-not CRS and-not XP labels CM2 calma CM2 51 * layer rm2 CRM and CM2 calma CRM 70 * layer rm2 CRS and CM2 calma CRS 72 * layer pseudo_rmetal2 CRS and-not rm2 calma CRS 72 * layer m2p CMSP labels CMSP calma CMSP 82 * layer fp 100 calma 100 100 * layer fm1 101 calma 101 101 * layer fm2 102 calma 102 102 * layer fm3 103 calma 103 103 * layer fa 109 calma 109 109 * layer fn 119 calma 119 119 * layer fapm 110 calma 110 110 * layer m3c CV2 and-not CV1 and-not XP grow 30 and CM3 and CM2 grow 15 shrink 15 calma CV2 61 * layer m3 CM3 and-not CRM and-not CRT and-not XP labels CM3 calma CM3 62 * layer rm3 CRM and CM3 calma CRM 70 * layer rm3 CRT and CM3 calma CRT 73 * layer pseudo_rmetal3 CRT and-not rm3 calma CRT 73 * layer m3p CMTP labels CMTP calma CMTP 83 * layer pad XP labels pad calma XP 26 * layer glass COG and-not COP and-not XP labels COG calma COG 52 * layer nfi CFI and CWN labels CFI calma CFI 27 * layer pfi CFI and-not CWN labels CFI calma CFI 27 * layer hr CHR labels CHR calma CHR 34 * layer phr CEL and CHR calma CEL 56 * layer ecap CEL and CPG labels CEL calma CEL 56 * layer poly2 CEL and-not CPG labels CEL calma CEL 56 * layer rp2 CEL and CRG2 calma CEL 56 * layer pseudo_rpoly2 CRG2 and-not CRE calma CRG2 68 * layer comment CX labels CX calma CX 63 * calma CTA 60 * calma CRW 65 * calma CRG 67 * calma CRD 66 * calma CRE 64 * calma CRF 71 * calma CRS 72 * calma CRT 73 * calma CRM 70 * style lambda=0.30() scalefactor 30 layer nwell CWN and-not CWNR and-not CTA labels CWN calma CWN 42 * layer rnw CWN and-not CWNR and CRE and-not CSB and-not CRD and-not CAA and-not CPG calma CWN 42 * layer rnw CWN and-not CWNR and CRW and-not CRD and-not CAA and-not CPG calma CWN 42 * layer pseudo_rnwell CRW and-not CRE calma CRW 65 * ignore CWP calma CWP 41 * layer diff CAA and-not CTA and-not CPG and-not CWNR and-not COP and-not CSN and-not CSP labels CAA calma CAA 43 * layer tran CAA and-not CTA and CPG and-not CWNR and-not COP and-not CSN and-not CSP labels CAA calma CAA 43 * calma CSN 45 * calma CSP 44 * layer ndiff CAA and CSN and-not CWNR and-not CTA and-not CRE and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer rnd CAA and CSN and-not CWNR and CRE and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA calma CAA 43 * layer rnd CAA and CSN and-not CWNR and CRD and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA calma CAA 43 * layer pseudo_rndiff CRD and-not CRE and-not CAA and-not CSB and-not CPG and-not CWN and-not CSP and CSN and-not CBA calma CRD 66 * layer pdiff CAA and CSP and-not CWNR and-not CTA and-not CRE and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer rpd CAA and CSP and-not CWNR and CRE and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CAA 43 * layer rpd CAA and CSP and-not CWNR and CRD and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CAA 43 * layer pseudo_rpdiff CRD and-not CRE and-not CAA and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CRD 66 * layer nfet CAA and CSN and-not CWNR and-not CTA and CPG and-not CEL and-not CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer pfet CAA and CSP and-not CWNR and-not CTA and CPG and-not CEL and CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer nsd CAA and CSN and-not CWNR and-not CTA and CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer psd CAA and CSP and-not CWNR and-not CTA and-not CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer ndc CAA and CSN and CCA and-not CV1 and-not CWNR and-not CTA and-not CWN and CM1 grow 30 grow 15 shrink 15 calma CCA 48 * layer ndc CAA and CSN and CCC and-not CV1 and-not CWNR and-not CTA and-not CWN and CM1 grow 30 grow 15 shrink 15 calma CCC 25 * layer nsc CAA and CSN and CCA and-not CV1 and-not CWNR and-not CTA and CWN and CM1 grow 30 grow 15 shrink 15 calma CCA 48 * layer nsc CAA and CSN and CCC and-not CV1 and-not CWNR and-not CTA and CWN and CM1 grow 30 grow 15 shrink 15 calma CCC 25 * layer pdc CAA and CSP and CCA and-not CV1 and-not CTA and-not CPS and CWN and CM1 grow 30 grow 15 shrink 15 calma CCA 48 * layer pdc CAA and CSP and CCC and-not CV1 and-not CTA and-not CPS and CWN and CM1 grow 30 grow 15 shrink 15 calma CCC 25 * layer psc CAA and CSP and CCA and-not CV1 and-not CTA and-not CPS and-not CWN and CM1 grow 30 grow 15 shrink 15 calma CCA 48 * layer psc CAA and CSP and CCC and-not CV1 and-not CWNR and-not CTA and-not CPS and-not CWN and CM1 grow 30 grow 15 shrink 15 calma CCC 25 * layer ndc CAA and CSN and CCA and CV1 and CV2 and-not CWNR and-not CTA and-not CWN and CM1 grow 30 grow 15 shrink 15 calma CCA 48 * layer ndc CAA and CSN and CCC and CV1 and CV2 and-not CWNR and-not CTA and-not CWN and CM1 grow 30 grow 15 shrink 15 calma CCC 25 * layer nsc CAA and CSN and CCA and CV1 and CV2 and-not CWNR and-not CTA and CWN and CM1 grow 30 grow 15 shrink 15 calma CCA 48 * layer nsc CAA and CSN and CCC and CV1 and CV2 and-not CWNR and-not CTA and CWN and CM1 grow 30 grow 15 shrink 15 calma CCC 25 * layer pdc CAA and CSP and CCA and CV1 and CV2 and-not CTA and-not CPS and CWN and CM1 grow 30 grow 15 shrink 15 calma CCA 48 * layer pdc CAA and CSP and CCC and CV1 and CV2 and-not CTA and-not CPS and CWN and CM1 grow 30 grow 15 shrink 15 calma CCC 25 * layer psc CAA and CSP and CCA and CV1 and CV2 and-not CTA and-not CPS and-not CWN and CM1 grow 30 grow 15 shrink 15 calma CCA 48 * layer psc CAA and CSP and CCC and CV1 and CV2 and-not CWNR and-not CTA and-not CPS and-not CWN and CM1 grow 30 grow 15 shrink 15 calma CCC 25 * layer poly CPG and-not CRE labels CPG calma CPG 46 * layer rp CPG and CRE and-not CSB calma CPG 46 * layer rp CPG and CRG calma CPG 46 * layer pseudo_rpoly CRG and-not CRE calma CRG 67 * layer pc CCP and-not CV1 and CPG and-not CPC and-not CEL and-not CAA grow 30 and CM1 grow 15 shrink 15 calma CCP 47 * layer pc CCC and-not CV1 and CPG and-not CPC and-not CEL and-not CAA grow 30 and CM1 grow 15 shrink 15 calma CCC 25 * layer pc CCP and CV1 and CV2 and CPG and-not CPC and-not CEL and-not CAA grow 30 and CM1 grow 15 shrink 15 calma CCP 47 * layer pc CCC and CV1 and CV2 and CPG and-not CPC and-not CEL and-not CAA grow 30 and CM1 grow 15 shrink 15 calma CCC 25 * layer p2c CCE and-not CV1 and CPG and CEL and-not CPC and-not CAA grow 30 and CM1 grow 15 shrink 15 calma CCE 55 * layer p2c CCC and-not CV1 and CPG and CEL and-not CPC and-not CAA grow 30 and CM1 grow 15 shrink 15 calma CCC 25 * layer p2c CCE and CV1 and CV2 and CPG and CEL and-not CPC and-not CAA grow 30 and CM1 grow 15 shrink 15 calma CCE 55 * layer p2c CCC and CV1 and CV2 and CPG and CEL and-not CPC and-not CAA grow 30 and CM1 grow 15 shrink 15 calma CCC 25 * layer gc CCP and-not CPG and-not CPC calma CCP 47 * layer gc CCP and-not CM1 calma CCP 47 * layer gc CCA and-not COP and-not CAA and-not CBA calma CCA 48 * layer gc CCA and-not COP and-not CM1 calma CCA 48 * layer gc CCC and-not COP and-not CPG and-not CPC and-not CEL and-not CAA and-not CBA calma CCC 25 * layer gc CCC and-not COP and-not CM1 calma CCC 25 * layer gc2 CCE and-not CPC and-not CEL calma CCE 55 * layer gc2 CCE and-not CM1 calma CCE 55 * layer gv1 CV1 and-not COP and-not CM1 calma CV1 50 * layer gv1 CV1 and-not COP and-not CM2 calma CV1 50 * layer gv2 CV2 and-not COP and-not CM2 calma CV2 61 * layer gv2 CV2 and-not COP and-not CM3 calma CV2 61 * layer m2c CV1 and-not CV2 and-not CCC and-not CCE and-not CCP and-not CCA and-not XP grow 30 and CM2 and CM1 grow 15 shrink 15 calma CV1 50 * layer p2m12c CV1 and-not CV2 and CCE grow 30 and CM2 and CM1 and CPG and CEL grow 15 shrink 15 calma CV1 50 * layer p2m12c CV1 and-not CV2 and CCC grow 30 and CM2 and CM1 and CPG and CEL grow 15 shrink 15 calma CV1 50 * layer m1 CM1 and-not CRM and-not CRF and-not XP labels CM1 calma CM1 49 * layer rm1 CRM and CM1 calma CRM 70 * layer rm1 CRF and CM1 calma CRF 71 * layer pseudo_rmetal1 CRF and-not rm1 calma CRF 71 * layer m1p CMFP labels CMFP calma CMFP 81 * layer m2 CM2 and-not CRM and-not CRS and-not XP labels CM2 calma CM2 51 * layer rm2 CRM and CM2 calma CRM 70 * layer rm2 CRS and CM2 calma CRS 72 * layer pseudo_rmetal2 CRS and-not rm2 calma CRS 72 * layer m2p CMSP labels CMSP calma CMSP 82 * layer fp 100 calma 100 100 * layer fm1 101 calma 101 101 * layer fm2 102 calma 102 102 * layer fm3 103 calma 103 103 * layer fa 109 calma 109 109 * layer fn 119 calma 119 119 * layer fapm 110 calma 110 110 * layer m3c CV2 and-not CV1 and-not XP grow 30 and CM3 and CM2 grow 15 shrink 15 calma CV2 61 * layer m3 CM3 and-not CRM and-not CRT and-not XP labels CM3 calma CM3 62 * layer rm3 CRM and CM3 calma CRM 70 * layer rm3 CRT and CM3 calma CRT 73 * layer pseudo_rmetal3 CRT and-not rm3 calma CRT 73 * layer m3p CMTP labels CMTP calma CMTP 83 * layer pad XP labels pad calma XP 26 * layer glass COG and-not COP and-not XP labels COG calma COG 52 * layer nfi CFI and CWN labels CFI calma CFI 27 * layer pfi CFI and-not CWN labels CFI calma CFI 27 * layer hr CHR labels CHR calma CHR 34 * layer phr CEL and CHR calma CEL 56 * layer ecap CEL and CPG labels CEL calma CEL 56 * layer poly2 CEL and-not CPG labels CEL calma CEL 56 * layer rp2 CEL and CRG2 calma CEL 56 * layer pseudo_rpoly2 CRG2 and-not CRE calma CRG2 68 * layer comment CX labels CX calma CX 63 * calma CTA 60 * calma CRW 65 * calma CRG 67 * calma CRD 66 * calma CRE 64 * calma CRF 71 * calma CRS 72 * calma CRT 73 * calma CRM 70 * style lambda=0.30(c) scalefactor 30 layer nwell CWN and-not CWNR and-not CTA labels CWN calma CWN 42 * layer rnw CWN and-not CWNR and CRE and-not CSB and-not CRD and-not CAA and-not CPG calma CWN 42 * layer rnw CWN and-not CWNR and CRW and-not CRD and-not CAA and-not CPG calma CWN 42 * layer pseudo_rnwell CRW and-not CRE calma CRW 65 * ignore CWP calma CWP 41 * layer diff CAA and-not CTA and-not CPG and-not CWNR and-not COP and-not CSN and-not CSP labels CAA calma CAA 43 * layer tran CAA and-not CTA and CPG and-not CWNR and-not COP and-not CSN and-not CSP labels CAA calma CAA 43 * calma CSN 45 * calma CSP 44 * layer ndiff CAA and CSN and-not CWNR and-not CTA and-not CRE and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer rnd CAA and CSN and-not CWNR and CRE and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA calma CAA 43 * layer rnd CAA and CSN and-not CWNR and CRD and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA calma CAA 43 * layer pseudo_rndiff CRD and-not CRE and-not CAA and-not CSB and-not CPG and-not CWN and-not CSP and CSN and-not CBA calma CRD 66 * layer pdiff CAA and CSP and-not CWNR and-not CTA and-not CRE and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer rpd CAA and CSP and-not CWNR and CRE and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CAA 43 * layer rpd CAA and CSP and-not CWNR and CRD and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CAA 43 * layer pseudo_rpdiff CRD and-not CRE and-not CAA and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CRD 66 * layer nfet CAA and CSN and-not CWNR and-not CTA and CPG and-not CEL and-not CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer pfet CAA and CSP and-not CWNR and-not CTA and CPG and-not CEL and CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer nsd CAA and CSN and-not CWNR and-not CTA and CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer psd CAA and CSP and-not CWNR and-not CTA and-not CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer gc2 CCA and CEL calma CCA 48 * layer gc2 CCP and CEL calma CCP 47 * layer gc2 CCC and CEL calma CCC 25 * layer gc2 CCE and CEL calma CCE 55 * layer gc2 CCA and CPC and-not CPG calma CCA 48 * layer gc2 CCP and CPC and-not CPG calma CCP 47 * layer gc2 CCC and CPC and-not CPG calma CCC 25 * layer gc2 CCE and CPC and-not CPG calma CCE 55 * layer gc CCA and CPG and-not CEL calma CCA 48 * layer gc CCP and CPG and-not CEL calma CCP 47 * layer gc CCC and CPG and-not CEL calma CCC 25 * layer gc CCE and CPG and-not CEL calma CCE 55 * layer gc CCA and-not COP and-not CPC and-not CEL calma CCA 48 * layer gc CCP and-not COP and-not CPC and-not CEL calma CCP 47 * layer gc CCC and-not COP and-not CPC and-not CEL calma CCC 25 * layer gc CCE and-not COP and-not CPC and-not CEL calma CCE 55 * layer poly CPG and-not CRE labels CPG calma CPG 46 * layer rp CPG and CRE and-not CSB calma CPG 46 * layer rp CPG and CRG calma CPG 46 * layer pseudo_rpoly CRG and-not CRE calma CRG 67 * layer m1 CM1 and-not CRM and-not CRF labels CM1 calma CM1 49 * layer rm1 CRM and CM1 calma CRM 70 * layer rm1 CRF and CM1 calma CRF 71 * layer pseudo_rmetal1 CRF and-not rm1 calma CRF 71 * layer m1p CMFP labels CMFP calma CMFP 81 * layer gv1 CV1 calma CV1 50 * layer m2 CM2 and-not CRM and-not CRS labels CM2 calma CM2 51 * layer rm2 CRM and CM2 calma CRM 70 * layer rm2 CRS and CM2 calma CRS 72 * layer pseudo_rmetal2 CRS and-not rm2 calma CRS 72 * layer m2p CMSP labels CMSP calma CMSP 82 * layer fp 100 calma 100 100 * layer fm1 101 calma 101 101 * layer fm2 102 calma 102 102 * layer fm3 103 calma 103 103 * layer fa 109 calma 109 109 * layer fn 119 calma 119 119 * layer fapm 110 calma 110 110 * layer gv2 CV2 calma CV2 61 * layer m3 CM3 and-not CRM and-not CRT labels CM3 calma CM3 62 * layer rm3 CRM and CM3 calma CRM 70 * layer rm3 CRT and CM3 calma CRT 73 * layer pseudo_rmetal3 CRT and-not rm3 calma CRT 73 * layer m3p CMTP labels CMTP calma CMTP 83 * layer xp XP calma XP 26 * layer glass COG and-not COP labels COG calma COG 52 * layer nfi CFI and CWN labels CFI calma CFI 27 * layer pfi CFI and-not CWN labels CFI calma CFI 27 * layer hr CHR labels CHR calma CHR 34 * layer phr CEL and CHR calma CEL 56 * layer ecap CEL and CPG labels CEL calma CEL 56 * layer poly2 CEL and-not CPG labels CEL calma CEL 56 * layer rp2 CEL and CRG2 calma CEL 56 * layer pseudo_rpoly2 CRG2 and-not CRE calma CRG2 68 * layer comment CX labels CX calma CX 63 * calma CTA 60 * calma CRW 65 * calma CRG 67 * calma CRD 66 * calma CRE 64 * calma CRF 71 * calma CRS 72 * calma CRT 73 * calma CRM 70 * style lambda=0.30(cs) scalefactor 30 layer nwell CWN and-not CWNR and-not CTA labels CWN calma CWN 42 * layer rnw CWN and-not CWNR and CRE and-not CSB and-not CRD and-not CAA and-not CPG calma CWN 42 * layer rnw CWN and-not CWNR and CRW and-not CRD and-not CAA and-not CPG calma CWN 42 * layer pseudo_rnwell CRW and-not CRE calma CRW 65 * ignore CWP calma CWP 41 * layer diff CAA and-not CTA and-not CPG and-not CWNR and-not COP and-not CSN and-not CSP labels CAA calma CAA 43 * layer tran CAA and-not CTA and CPG and-not CWNR and-not COP and-not CSN and-not CSP labels CAA calma CAA 43 * layer nselect CSN calma CSN 45 * layer pselect CSP calma CSP 44 * layer ndiff CAA and CSN and-not CWNR and-not CTA and-not CRE and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer rnd CAA and CSN and-not CWNR and CRE and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA calma CAA 43 * layer rnd CAA and CSN and-not CWNR and CRD and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA calma CAA 43 * layer pseudo_rndiff CRD and-not CRE and-not CAA and-not CSB and-not CPG and-not CWN and-not CSP and CSN and-not CBA calma CRD 66 * layer pdiff CAA and CSP and-not CWNR and-not CTA and-not CRE and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer rpd CAA and CSP and-not CWNR and CRE and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CAA 43 * layer rpd CAA and CSP and-not CWNR and CRD and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CAA 43 * layer pseudo_rpdiff CRD and-not CRE and-not CAA and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CRD 66 * layer nfet CAA and CSN and-not CWNR and-not CTA and CPG and-not CEL and-not CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer pfet CAA and CSP and-not CWNR and-not CTA and CPG and-not CEL and CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer nsd CAA and CSN and-not CWNR and-not CTA and CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer psd CAA and CSP and-not CWNR and-not CTA and-not CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer gc2 CCA and CEL calma CCA 48 * layer gc2 CCP and CEL calma CCP 47 * layer gc2 CCC and CEL calma CCC 25 * layer gc2 CCE and CEL calma CCE 55 * layer gc2 CCA and CPC and-not CPG calma CCA 48 * layer gc2 CCP and CPC and-not CPG calma CCP 47 * layer gc2 CCC and CPC and-not CPG calma CCC 25 * layer gc2 CCE and CPC and-not CPG calma CCE 55 * layer gc CCA and CPG and-not CEL calma CCA 48 * layer gc CCP and CPG and-not CEL calma CCP 47 * layer gc CCC and CPG and-not CEL calma CCC 25 * layer gc CCE and CPG and-not CEL calma CCE 55 * layer gc CCA and-not COP and-not CPC and-not CEL calma CCA 48 * layer gc CCP and-not COP and-not CPC and-not CEL calma CCP 47 * layer gc CCC and-not COP and-not CPC and-not CEL calma CCC 25 * layer gc CCE and-not COP and-not CPC and-not CEL calma CCE 55 * layer poly CPG and-not CRE labels CPG calma CPG 46 * layer rp CPG and CRE and-not CSB calma CPG 46 * layer rp CPG and CRG calma CPG 46 * layer pseudo_rpoly CRG and-not CRE calma CRG 67 * layer m1 CM1 and-not CRM and-not CRF labels CM1 calma CM1 49 * layer rm1 CRM and CM1 calma CRM 70 * layer rm1 CRF and CM1 calma CRF 71 * layer pseudo_rmetal1 CRF and-not rm1 calma CRF 71 * layer m1p CMFP labels CMFP calma CMFP 81 * layer gv1 CV1 calma CV1 50 * layer m2 CM2 and-not CRM and-not CRS labels CM2 calma CM2 51 * layer rm2 CRM and CM2 calma CRM 70 * layer rm2 CRS and CM2 calma CRS 72 * layer pseudo_rmetal2 CRS and-not rm2 calma CRS 72 * layer m2p CMSP labels CMSP calma CMSP 82 * layer fp 100 calma 100 100 * layer fm1 101 calma 101 101 * layer fm2 102 calma 102 102 * layer fm3 103 calma 103 103 * layer fa 109 calma 109 109 * layer fn 119 calma 119 119 * layer fapm 110 calma 110 110 * layer gv2 CV2 calma CV2 61 * layer m3 CM3 and-not CRM and-not CRT labels CM3 calma CM3 62 * layer rm3 CRM and CM3 calma CRM 70 * layer rm3 CRT and CM3 calma CRT 73 * layer pseudo_rmetal3 CRT and-not rm3 calma CRT 73 * layer m3p CMTP labels CMTP calma CMTP 83 * layer xp XP calma XP 26 * layer glass COG and-not COP labels COG calma COG 52 * layer nfi CFI and CWN labels CFI calma CFI 27 * layer pfi CFI and-not CWN labels CFI calma CFI 27 * layer hr CHR labels CHR calma CHR 34 * layer phr CEL and CHR calma CEL 56 * layer ecap CEL and CPG labels CEL calma CEL 56 * layer poly2 CEL and-not CPG labels CEL calma CEL 56 * layer rp2 CEL and CRG2 calma CEL 56 * layer pseudo_rpoly2 CRG2 and-not CRE calma CRG2 68 * layer comment CX labels CX calma CX 63 * calma CTA 60 * calma CRW 65 * calma CRG 67 * calma CRD 66 * calma CRE 64 * calma CRF 71 * calma CRS 72 * calma CRT 73 * calma CRM 70 * style lambda=0.30(cps) scalefactor 30 layer nwell CWN and-not CWNR and-not CTA labels CWN calma CWN 42 * layer rnw CWN and-not CWNR and CRE and-not CSB and-not CRD and-not CAA and-not CPG calma CWN 42 * layer rnw CWN and-not CWNR and CRW and-not CRD and-not CAA and-not CPG calma CWN 42 * layer pseudo_rnwell CRW and-not CRE calma CRW 65 * layer pwell CWP and-not CTA labels CWP calma CWP 41 * layer diff CAA and-not CTA and-not CPG and-not CWNR and-not COP and-not CSN and-not CSP labels CAA calma CAA 43 * layer tran CAA and-not CTA and CPG and-not CWNR and-not COP and-not CSN and-not CSP labels CAA calma CAA 43 * layer nselect CSN calma CSN 45 * layer pselect CSP calma CSP 44 * layer ndiff CAA and CSN and-not CWNR and-not CTA and-not CRE and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer rnd CAA and CSN and-not CWNR and CRE and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA calma CAA 43 * layer rnd CAA and CSN and-not CWNR and CRD and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA calma CAA 43 * layer pseudo_rndiff CRD and-not CRE and-not CAA and-not CSB and-not CPG and-not CWN and-not CSP and CSN and-not CBA calma CRD 66 * layer pdiff CAA and CSP and-not CWNR and-not CTA and-not CRE and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer rpd CAA and CSP and-not CWNR and CRE and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CAA 43 * layer rpd CAA and CSP and-not CWNR and CRD and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CAA 43 * layer pseudo_rpdiff CRD and-not CRE and-not CAA and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CRD 66 * layer nfet CAA and CSN and-not CWNR and-not CTA and CPG and-not CEL and-not CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer pfet CAA and CSP and-not CWNR and-not CTA and CPG and-not CEL and CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer nsd CAA and CSN and-not CWNR and-not CTA and CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer psd CAA and CSP and-not CWNR and-not CTA and-not CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer gc2 CCA and CEL calma CCA 48 * layer gc2 CCP and CEL calma CCP 47 * layer gc2 CCC and CEL calma CCC 25 * layer gc2 CCE and CEL calma CCE 55 * layer gc2 CCA and CPC and-not CPG calma CCA 48 * layer gc2 CCP and CPC and-not CPG calma CCP 47 * layer gc2 CCC and CPC and-not CPG calma CCC 25 * layer gc2 CCE and CPC and-not CPG calma CCE 55 * layer gc CCA and CPG and-not CEL calma CCA 48 * layer gc CCP and CPG and-not CEL calma CCP 47 * layer gc CCC and CPG and-not CEL calma CCC 25 * layer gc CCE and CPG and-not CEL calma CCE 55 * layer gc CCA and-not COP and-not CPC and-not CEL calma CCA 48 * layer gc CCP and-not COP and-not CPC and-not CEL calma CCP 47 * layer gc CCC and-not COP and-not CPC and-not CEL calma CCC 25 * layer gc CCE and-not COP and-not CPC and-not CEL calma CCE 55 * layer poly CPG and-not CRE labels CPG calma CPG 46 * layer rp CPG and CRE and-not CSB calma CPG 46 * layer rp CPG and CRG calma CPG 46 * layer pseudo_rpoly CRG and-not CRE calma CRG 67 * layer m1 CM1 and-not CRM and-not CRF labels CM1 calma CM1 49 * layer rm1 CRM and CM1 calma CRM 70 * layer rm1 CRF and CM1 calma CRF 71 * layer pseudo_rmetal1 CRF and-not rm1 calma CRF 71 * layer m1p CMFP labels CMFP calma CMFP 81 * layer gv1 CV1 calma CV1 50 * layer m2 CM2 and-not CRM and-not CRS labels CM2 calma CM2 51 * layer rm2 CRM and CM2 calma CRM 70 * layer rm2 CRS and CM2 calma CRS 72 * layer pseudo_rmetal2 CRS and-not rm2 calma CRS 72 * layer m2p CMSP labels CMSP calma CMSP 82 * layer fp 100 calma 100 100 * layer fm1 101 calma 101 101 * layer fm2 102 calma 102 102 * layer fm3 103 calma 103 103 * layer fa 109 calma 109 109 * layer fn 119 calma 119 119 * layer fapm 110 calma 110 110 * layer gv2 CV2 calma CV2 61 * layer m3 CM3 and-not CRM and-not CRT labels CM3 calma CM3 62 * layer rm3 CRM and CM3 calma CRM 70 * layer rm3 CRT and CM3 calma CRT 73 * layer pseudo_rmetal3 CRT and-not rm3 calma CRT 73 * layer m3p CMTP labels CMTP calma CMTP 83 * layer xp XP calma XP 26 * layer glass COG and-not COP labels COG calma COG 52 * layer nfi CFI and CWN labels CFI calma CFI 27 * layer pfi CFI and-not CWN labels CFI calma CFI 27 * layer hr CHR labels CHR calma CHR 34 * layer phr CEL and CHR calma CEL 56 * layer ecap CEL and CPG labels CEL calma CEL 56 * layer poly2 CEL and-not CPG labels CEL calma CEL 56 * layer rp2 CEL and CRG2 calma CEL 56 * layer pseudo_rpoly2 CRG2 and-not CRE calma CRG2 68 * layer comment CX labels CX calma CX 63 * calma CTA 60 * calma CRW 65 * calma CRG 67 * calma CRD 66 * calma CRE 64 * calma CRF 71 * calma CRS 72 * calma CRT 73 * calma CRM 70 * style lambda=0.30(cp) scalefactor 30 layer nwell CWN and-not CWNR and-not CTA labels CWN calma CWN 42 * layer rnw CWN and-not CWNR and CRE and-not CSB and-not CRD and-not CAA and-not CPG calma CWN 42 * layer rnw CWN and-not CWNR and CRW and-not CRD and-not CAA and-not CPG calma CWN 42 * layer pseudo_rnwell CRW and-not CRE calma CRW 65 * layer pwell CWP and-not CTA labels CWP calma CWP 41 * layer diff CAA and-not CTA and-not CPG and-not CWNR and-not COP and-not CSN and-not CSP labels CAA calma CAA 43 * layer tran CAA and-not CTA and CPG and-not CWNR and-not COP and-not CSN and-not CSP labels CAA calma CAA 43 * calma CSN 45 * calma CSP 44 * layer ndiff CAA and CSN and-not CWNR and-not CTA and-not CRE and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer rnd CAA and CSN and-not CWNR and CRE and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA calma CAA 43 * layer rnd CAA and CSN and-not CWNR and CRD and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA calma CAA 43 * layer pseudo_rndiff CRD and-not CRE and-not CAA and-not CSB and-not CPG and-not CWN and-not CSP and CSN and-not CBA calma CRD 66 * layer pdiff CAA and CSP and-not CWNR and-not CTA and-not CRE and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer rpd CAA and CSP and-not CWNR and CRE and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CAA 43 * layer rpd CAA and CSP and-not CWNR and CRD and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CAA 43 * layer pseudo_rpdiff CRD and-not CRE and-not CAA and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CRD 66 * layer nfet CAA and CSN and-not CWNR and-not CTA and CPG and-not CEL and-not CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer pfet CAA and CSP and-not CWNR and-not CTA and CPG and-not CEL and CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer nsd CAA and CSN and-not CWNR and-not CTA and CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer psd CAA and CSP and-not CWNR and-not CTA and-not CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer gc2 CCA and CEL calma CCA 48 * layer gc2 CCP and CEL calma CCP 47 * layer gc2 CCC and CEL calma CCC 25 * layer gc2 CCE and CEL calma CCE 55 * layer gc2 CCA and CPC and-not CPG calma CCA 48 * layer gc2 CCP and CPC and-not CPG calma CCP 47 * layer gc2 CCC and CPC and-not CPG calma CCC 25 * layer gc2 CCE and CPC and-not CPG calma CCE 55 * layer gc CCA and CPG and-not CEL calma CCA 48 * layer gc CCP and CPG and-not CEL calma CCP 47 * layer gc CCC and CPG and-not CEL calma CCC 25 * layer gc CCE and CPG and-not CEL calma CCE 55 * layer gc CCA and-not COP and-not CPC and-not CEL calma CCA 48 * layer gc CCP and-not COP and-not CPC and-not CEL calma CCP 47 * layer gc CCC and-not COP and-not CPC and-not CEL calma CCC 25 * layer gc CCE and-not COP and-not CPC and-not CEL calma CCE 55 * layer poly CPG and-not CRE labels CPG calma CPG 46 * layer rp CPG and CRE and-not CSB calma CPG 46 * layer rp CPG and CRG calma CPG 46 * layer pseudo_rpoly CRG and-not CRE calma CRG 67 * layer m1 CM1 and-not CRM and-not CRF labels CM1 calma CM1 49 * layer rm1 CRM and CM1 calma CRM 70 * layer rm1 CRF and CM1 calma CRF 71 * layer pseudo_rmetal1 CRF and-not rm1 calma CRF 71 * layer m1p CMFP labels CMFP calma CMFP 81 * layer gv1 CV1 calma CV1 50 * layer m2 CM2 and-not CRM and-not CRS labels CM2 calma CM2 51 * layer rm2 CRM and CM2 calma CRM 70 * layer rm2 CRS and CM2 calma CRS 72 * layer pseudo_rmetal2 CRS and-not rm2 calma CRS 72 * layer m2p CMSP labels CMSP calma CMSP 82 * layer fp 100 calma 100 100 * layer fm1 101 calma 101 101 * layer fm2 102 calma 102 102 * layer fm3 103 calma 103 103 * layer fa 109 calma 109 109 * layer fn 119 calma 119 119 * layer fapm 110 calma 110 110 * layer gv2 CV2 calma CV2 61 * layer m3 CM3 and-not CRM and-not CRT labels CM3 calma CM3 62 * layer rm3 CRM and CM3 calma CRM 70 * layer rm3 CRT and CM3 calma CRT 73 * layer pseudo_rmetal3 CRT and-not rm3 calma CRT 73 * layer m3p CMTP labels CMTP calma CMTP 83 * layer xp XP calma XP 26 * layer glass COG and-not COP labels COG calma COG 52 * layer nfi CFI and CWN labels CFI calma CFI 27 * layer pfi CFI and-not CWN labels CFI calma CFI 27 * layer hr CHR labels CHR calma CHR 34 * layer phr CEL and CHR calma CEL 56 * layer ecap CEL and CPG labels CEL calma CEL 56 * layer poly2 CEL and-not CPG labels CEL calma CEL 56 * layer rp2 CEL and CRG2 calma CEL 56 * layer pseudo_rpoly2 CRG2 and-not CRE calma CRG2 68 * layer comment CX labels CX calma CX 63 * calma CTA 60 * calma CRW 65 * calma CRG 67 * calma CRD 66 * calma CRE 64 * calma CRF 71 * calma CRS 72 * calma CRT 73 * calma CRM 70 * style fill-only scalefactor 30 # scalefactor 100 layer fp 100 calma 100 100 * layer fm1 101 calma 101 101 * layer fm2 102 calma 102 102 * layer fm3 103 calma 103 103 * layer fa 109 or fb calma 109 109 * layer fn 119 calma 119 119 * layer fapm 110 calma 110 110 * end mzrouter style irouter # layer hCost vCost jogCost hintCost layer metal3 1 2 2 1 layer metal2 2 1 2 1 layer metal1 2 3 2 1 layer poly 10 10 11 1 contact m3contact metal3 metal2 5 contact m2contact metal2 metal1 6 contact pcontact metal1 poly 7 notactive poly pcontact style garouter layer m2 32 64 256 1 layer m1 64 32 256 1 contact m2contact metal1 metal2 1024 end drc width nwell 12 \ "N-well width < 12 (Mosis #1.1)" width rnw 12 \ "rnwell (for resistor L/W extraction) width < 12 (Mosis #1.1)" width pwell 12 \ "P-well width < 12 (Mosis #1.1)" width diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a 3 \ "Diffusion width < 3 (Mosis #2.1)" width poly,fp,rp,pc/a,nfet,pfet,fet 2 \ "Poly width < 2 (Mosis #3.1)" width nselect 2 \ "N-Select width < 2 (Mosis #4.4)" width pselect 2 \ "P-Select width < 2 (Mosis #4.4)" width pc/m1 4 \ "Poly contact width < 4 (Mosis #5.1)" width gc 2 \ "GC contact width < 2 (Mosis #6.1)" width ndc/m1 4 \ "Diffusion contact width < 4 (Mosis #6.1)" width nsc/m1 4 \ "Diffusion contact width < 4 (Mosis #6.1)" width pdc/m1 4 \ "Diffusion contact width < 4 (Mosis #6.1)" width psc/m1 4 \ "Diffusion contact width < 4 (Mosis #6.1)" width m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 3 \ "Metal1 width < 3 (Mosis #7.1)" width gv1 2 \ "GV1 via width < 2 (Mosis #8.1)" width m2c/m1 4 \ "Metal2 contact width < 4 (Mosis #8.1)" width p2m12c 4 \ "Metal2 contact width < 4 (Mosis #8.1)" width p2m12c 4 \ "stacked p2m12c width < 4 (Mosis #8.1)" width m2,fm2,rm2,m2c/m2,m3c/m2 3 \ "Metal2 width < 3 (Mosis #9.1)" width poly2,ecap,phr,p2c,p2m12c,p2c,p2m12c 5 \ "Poly2 width < 5 (Mosis #11.1)" width gc2 2 \ "Generic contact2 width < 2 (Mosis #13.1)" width p2c 4 \ "Poly2 contact width < 4 (Mosis #13.1)" width p2m12c 4 \ "Poly2 contact width < 4 (Mosis #13.1)" width gv2 2 \ "GV2 via width < 2 (Mosis #14.1)" width m3c/m2 4 \ "Metal3 contact width < 4 (Mosis #14.1)" width m3,fm3,rm3,m3c/m3,pad 5 \ "Metal3 width < 5 (Mosis #15.1)" width hr,phr 4 \ "High-Resist width < 4 (Mosis #27.1)" width phr 5 \ "High-Resist poly2R width < 5 (Mosis #27.7)" width nfi,pfi 4 \ "N/P_field-implant width < 4 (Mosis #29.1)" spacing nwell nwell 6 touching_ok \ "N-well(at-same-potential) spacing < 6 (Mosis #1.3)" spacing pwell pwell 6 touching_ok \ "P-well(at-same-potential) spacing < 6 (Mosis #1.3)" spacing rnw nwell 18 touching_illegal \ "rnw (for resistor L/W extraction) spacing to N-well < 18 (Mosis #2.3)" edge4way ~(pwell)/well pwell 1 ~(rnw)/active 0 0 \ "P-well cannot touch rnw (for resistor L/W extraction) (Mosis #1.4)" active spacing diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a 3 touching_ok \ "Diffusion spacing < 3 (Mosis #2.2)" spacing nwell ndiff,rnd,nfet,ndc/a 6 touching_illegal \ "N-well spacing to N-Diffusion < 6 (Mosis #2.3)" spacing pwell pdiff,rpd,pfet,pdc/a 6 touching_illegal \ "P-well spacing to P-Diffusion < 6 (Mosis #2.3)" spacing ndiff,rnd,nfet,ndc/a pdiff,rpd,pfet,pdc/a 12 touching_illegal \ "N-Diffusion spacing to P-Diffusion < 12 (Mosis #2.3+2.3)" edge4way ~(nwell)/well nwell 6 ~(pdiff,rpd,pfet,pdc/a)/active nwell 6 \ "N-well overlap of P-Diffusion < 6 (Mosis #2.4)" active edge4way ~(pwell)/well pwell 6 ~(ndiff,rnd,nfet,ndc/a)/active pwell 6 \ "P-well overlap of N-Diffusion < 6 (Mosis #2.4)" active edge4way ~(nwell)/well nwell 3 ~(nsd,nsc/a)/active nwell 3 \ "N-well overlap of N-Ohmic < 3 (Mosis #2.4)" active edge4way ~(pwell)/well pwell 3 ~(psd,psc/a)/active pwell 3 \ "P-well overlap of P-Ohmic < 3 (Mosis #2.4)" active spacing ndiff,rnd,ndc/a nsd,nsc/a 9 touching_illegal \ "N-Diffusion spacing to N-Ohmic < 9 (Mosis #2.3+2.4)" spacing pdiff,rpd,pdc/a psd,psc/a 9 touching_illegal \ "P-Diffusion spacing to P-Ohmic < 9 (Mosis #2.3+2.4)" spacing nwell psd,psc/a 3 touching_illegal \ "N-well spacing to P-Ohmic < 3 (Mosis #2.4)" spacing pwell nsd,nsc/a 3 touching_illegal \ "P-well spacing to N-Ohmic < 3 (Mosis #2.4)" spacing psd,psc/a rnw,prnw 3 touching_illegal \ "P-Ohmic spacing to rnw,prnw < 3 (Mosis #2.4)" spacing nsd,nsc/a psd,psc/a 6 touching_illegal \ "N-Ohmic spacing to P-Ohmic < 6 (Mosis #2.4+2.4)" spacing ndiff,rnd,nfet,ndc/a,nfet psd,psc/a 4 touching_ok \ "N-Diffusion spacing to P-Ohmic < 4 (Mosis #2.5)" spacing pdiff,rpd,pfet,pdc/a,pfet nsd,nsc/a 4 touching_ok \ "P-Diffusion spacing to N-Ohmic < 4 (Mosis #2.5)" spacing poly,rp,pc/a,nfet,pfet,fet poly,rp,pc/a,nfet,pfet,fet 3 touching_ok \ "Poly spacing < 3 (Mosis #3.2)" spacing poly,rp,pc/a,nfet,pfet,fet fp,fapm 3 touching_illegal \ "Poly spacing to fill layer (fp) < 3 (Mosis #3.2)" spacing fp fp 4 touching_ok \ "Poly fill layer (fp) spacing < 4 (Mosis #0)" edge4way nfet,pfet,fet space/active,poly,fp,rp,pc/a 2 poly,fp,rp,pc/a 0 0 \ "Poly overhang of Transistor < 2 (Mosis #3.3)" active edge4way nfet,pfet,fet space/active,ndiff,rnd,ndc/a,pdiff,rpd,pdc/a 3 ndiff,rnd,ndc/a,pdiff,rpd,pdc/a,nfet,pfet,fet 0 0 \ "N-Diffusion,P-Diffusion overhang of Transistor < 3 (Mosis #3.4)" active edge4way poly,fp,rp,pc/a ~(poly,fp,rp,pc/a,nfet,pfet,fet,prp)/active 1 space space 1 \ "Poly spacing to Diffusion < 1 (Mosis #3.5)" edge4way nfet ~(nfet)/active 3 ~(pselect)/select ~(nfet)/active 3 \ "N-Transistor space to P-Select < 3 (Mosis #4.1)" select edge4way pfet ~(pfet)/active 3 ~(nselect)/select ~(pfet)/active 3 \ "P-Transistor space to N-Select < 3 (Mosis #4.1)" select edge4way nfet ~(nfet)/active 3 ~(psd,psc/a)/active ~(nfet)/active 2 \ "N-Transistor space to P-Ohmic < 3 (Mosis #4.1)" active edge4way pfet ~(pfet)/active 3 ~(nsd,nsc/a)/active ~(pfet)/active 2 \ "P-Transistor space to N-Ohmic < 3 (Mosis #4.1)" active #PEZ edge4way psd,psc/a space ~(nfet)/active space \ #PEZ "P-Ohmic space to N-Transistor < (Mosis #4.1)" active #PEZ edge4way nsd,nsc/a space ~(pfet)/active space \ #PEZ "N-Ohmic space to P-Transistor < (Mosis #4.1)" active edge4way ~(nselect,pselect)/select nselect,pselect 2 ~(diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a)/active nselect,pselect 2 \ "N-Select,P-Select overlap of Diffusion < 2 (Mosis #4.2_)" active edge4way space nselect,pselect 2 ~(ndiff,rnd,nfet,ndc/a)/active nselect 2 \ "N-Select space to N-Diffusion < 2 (Mosis #4.2a)" active edge4way nselect,pselect space 2 ~(ndiff,rnd,nfet,ndc/a)/active nselect 2 \ "N-Select space to N-Diffusion < 2 (Mosis #4.2b)" active edge4way nselect,pselect space 2 ~(ndiff,rnd,nfet,ndc/a)/active space,nselect,pselect 2 \ "N-Select space to N-Diffusion < 2 (Mosis #4.2c)" active edge4way space nselect,pselect 2 ~(pdiff,rpd,pfet,pdc/a)/active pselect 2 \ "P-Select space to P-Diffusion < 2 (Mosis #4.2aa)" active edge4way nselect,pselect space 2 ~(pdiff,rpd,pfet,pdc/a)/active pselect 2 \ "P-Select space to P-Diffusion < 2 (Mosis #4.2bb)" active edge4way nselect,pselect space 2 ~(pdiff,rpd,pfet,pdc/a)/active space,nselect,pselect 2 \ "P-Select space to P-Diffusion < 2 (Mosis #4.2cc)" active edge4way diff space 2 nselect space 2 \ "N-Select must overlap Diffusion by 2 (Mosis #4.2)" select edge4way diff space 2 pselect space 2 \ "P-Select must overlap Diffusion by 2 (Mosis #4.2)" select edge4way ndiff,rnd,nfet,ndc/a space 2 ~(pselect)/select space 2 \ "P-Select space to N-Diffusion < 2 (Mosis #4.2e)" select edge4way pdiff,rpd,pfet,pdc/a space 2 ~(nselect)/select space 2 \ "N-Select space to P-Diffusion < 2 (Mosis #4.2e)" select edge4way ~(pdiff,rpd,pfet,pdc/a,psd,psc/a)/active pdiff,rpd,pfet,pdc/a,psd,psc/a 1 ~(nselect)/select 0 0 \ "N-Select cannot touch P-Diffusion,P-Ohmic (Mosis #4.2f)" select edge4way ~(ndiff,rnd,nfet,ndc/a,nsd,nsc/a)/active ndiff,rnd,nfet,ndc/a,nsd,nsc/a 1 ~(pselect)/select 0 0 \ "P-Select cannot touch N-Diffusion,N-Ohmic (Mosis #4.2f)" select width nsd,nsc/a,psd,psc/a 2 \ "N-Ohmic,P-Ohmic width < 2 (Mosis #4.1)" spacing nselect nselect 2 touching_ok \ "N-Select spacing < 2 (Mosis #4.4)" spacing pselect pselect 2 touching_ok \ "P-Select spacing < 2 (Mosis #4.4)" edge4way ndiff,rnd,ndc/a psd,psc/a 2 ~(ndiff,rnd,ndc/a)/active 0 0 \ "P-Ohmic(that touches N-Diffusion) width < 2 (Mosis #4.4)" edge4way pdiff,rpd,pdc/a nsd,nsc/a 2 ~(pdiff,rpd,pdc/a)/active 0 0 \ "N-Ohmic(that touches P-Diffusion) width < 2 (Mosis #4.4)" edge4way gc ~(gc)/contact 1 poly,fp,rp,pc/a,diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a ~(gc)/contact 1 \ "Poly,Diffusion overlap of GC contact < 1 (Mosis #5.2)" active edge4way gc space 1 poly,fp,rp,pc/a,diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a space 1 \ "one of: Poly,Diffusion must overlap GC contact by 1 (Mosis #5.2a,6.2a)" active edge4way ~(poly,fp,rp,pc/a,diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a)/active poly,fp,rp,pc/a,diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a 1 ~(gc)/contact 0 0 \ "Edge to one of: Poly,Diffusion cannot touch GC contact (Mosis #5.2a,6.2a)" contact spacing gc gc 3 touching_ok \ "Generic contact spacing < 3 (Mosis #5.3)" edge4way ~(gc)/contact gc 1 ~(ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1)/metal1 0 0 \ "GC contact cannot touch Metal1 contacts (Mosis #0)" metal1 edge4way ~(gc2)/contact gc2 1 ~(ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1)/metal1 0 0 \ "Generic contact2 cannot touch Metal1 contacts (Mosis #0)" metal1 spacing gv1 m2c/m2 2 touching_illegal \ "GV1 via spacing to Metal2 contacts < 2 (Mosis #14.2)" spacing poly,fp,rp,pc/a pc/a 4 touching_ok \ "Poly spacing to Poly contact < 4 (Mosis #5.5.b)" edge4way gc ~(gc)/contact 1 diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a,poly,fp,rp,pc/a ~(gc)/contact 1 \ "Diffusion,Poly overlap of GC contact < 1 (Mosis #6.2)" active spacing gc pc/a,ndc/a,pdc/a,psc/a,nsc/a 2 touching_illegal \ "Generic contact spacing to Poly contact,Diffusion contact < 2 (Mosis #5.3)" spacing nsc/m1 pdc/m1 1 touching_illegal \ "nsc spacing to pdc < 1 (Mosis #6.3)" spacing psc/m1 ndc/m1 1 touching_illegal \ "psc spacing to ndc < 1 (Mosis #6.3)" spacing nfet,pfet ndc/a,pdc/a,psc/a,nsc/a 1 touching_illegal \ "N-Transistor,P-Transistor spacing to Diffusion contact < 1 (Mosis #6.4)" spacing nfet,pfet gc 2 touching_illegal \ "N-Transistor,P-Transistor spacing to Generic contact < 2 (Mosis #6.4)" spacing diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a pc/a 1 touching_illegal \ "Diffusion spacing to Poly contact < 1 (Mosis #6.5.b)" spacing diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a,nfet,pfet ndc/a,pdc/a,psc/a,nsc/a 4 touching_ok \ "Diffusion spacing to Diffusion contact < 4 (Mosis #6.5.b)" spacing pc/a ndc/a,pdc/a,psc/a,nsc/a 2 touching_illegal \ "pc/a,pm12c/a spacing to ndc/a,pdc/a,psc/a,nsc/a < 2 (Mosis #6.7)" spacing m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 3 touching_ok \ "Metal1 spacing < 3 (Mosis #7.2)" spacing m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 fm1,fapm 3 touching_illegal \ "Metal1 spacing to fill layer (fm1) < 3 (Mosis #7.2)" spacing fm1 fm1 4 touching_ok \ "Metal1 fill layer (fm1) spacing < 4 (Mosis #0)" edge4way gc space 1 m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 space 1 \ "Metal1 must overlap GC contact by 1 (Mosis #7.3,7.4)" metal1 edge4way ~(m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1)/metal1 m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 1 ~(gc)/contact 0 0 \ "Metal1(edge) cannot touch GC contact (Mosis #7.3+7.4)" contact spacing gv1 gv1 3 touching_ok \ "GV1 via spacing < 3 (Mosis #8.2)" edge4way gv1 ~(gv1)/via1 1 m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 ~(gv1)/via1 1 \ "Metal1 overlap of GV1 via < 1 (Mosis #8.3)" metal1 edge4way gv1 space 1 m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 space 1 \ "Metal1 must overlap GV1 via by 1 (Mosis #8.3)" metal1 edge4way ~(m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1)/metal1 m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 1 ~(gv1)/via1 0 0 \ "Metal1(edge) cannot touch GV1 via (Mosis #8.3)" via1 spacing m2,rm2,m2c/m2,m3c/m2 m2,rm2,m2c/m2,m3c/m2 3 touching_ok \ "Metal2 spacing < 3 (Mosis #9.2)" spacing m2,rm2,m2c/m2,m3c/m2 fm2,fapm 3 touching_illegal \ "Metal2 spacing to fill layer (fm2) < 3 (Mosis #9.2)" spacing fm2 fm2 4 touching_ok \ "Metal2 fill layer (fm2) spacing < 4 (Mosis #0)" edge4way gv1 space 1 m2,fm2,rm2,m2c/m2,m3c/m2 space 1 \ "Metal2 must overlap GV1 via by 1 (Mosis #9.3)" metal2 edge4way ~(m2,fm2,rm2,m2c/m2,m3c/m2)/metal2 m2,fm2,rm2,m2c/m2,m3c/m2 1 ~(gv1)/via1 0 0 \ "Metal2(edge) cannot touch GV1 via (Mosis #9.3)" via1 width glass 10 \ "COG width < 10 (Mosis #10.2)" edge4way ~(pad)/metal3 pad 20 ~(glass)/oxide pad 20 \ "pad overlap of COG < 20 (Mosis #10.3)" oxide spacing ecap ecap 3 touching_ok \ "Ecap spacing < 3 (Mosis #11.2)" edge4way ecap ~(ecap)/cap 5 poly,fp,rp,pc/a ~(ecap)/cap 5 \ "Poly overlap of Ecap < 5 (Mosis #11.3)" active edge4way ~(ecap)/cap ecap 1 poly,fp,rp,pc/a 0 0 \ "Ecap must touch Poly (Mosis #11.3x)" active edge4way poly2,phr,p2c,p2m12c space 5 ~(poly,fp,rp,pc/a)/active space 5 \ "Poly2 spacing to Poly < 5 (Mosis #11.3c)" active spacing ecap pc/a 2 touching_illegal \ "Ecap spacing to Poly contact < 2 (Mosis #11.5)" spacing ecap gc 3 touching_illegal \ "Ecap spacing to Generic contact < 3 (Mosis #11.5)" spacing poly2,ecap,phr,p2c,p2m12c poly2,ecap,phr,p2c,p2m12c 3 touching_ok \ "Poly2 spacing < 3 (Mosis #11.2)" spacing poly2,ecap,phr,p2c,p2m12c pc/a,ndc/a,pdc/a,psc/a,nsc/a 2 touching_illegal \ "Poly2 spacing to Poly contact,Diffusion contact < 2 (Mosis #11.5)" spacing poly2,ecap,phr,p2c,p2m12c gc,gc 3 touching_illegal \ "Poly2 spacing to GC contact < 3 (Mosis #11.5)" spacing gc2 gc2 3 touching_ok \ "Generic contact2 spacing < 3 (Mosis #13.2)" edge4way ~(ecap)/cap ecap 3 ~(gc2)/contact ecap 3 \ "Ecap overlap of Generic contact2 < 3 (Mosis #13.3)" contact edge4way ~(ecap)/cap ecap 2 ~(p2c,p2m12c)/cap ecap 2 \ "Ecap overlap of Poly2 contact < 2 (Mosis #13.3)" cap edge4way gc2 space 1 m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 space 1 \ "Metal1 must overlap Generic contact2 by 1 (Mosis #13.4)" metal1 edge4way ~(m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1)/metal1 m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 1 ~(gc2)/contact 0 0 \ "Metal1(edge) cannot touch Generic contact2 (Mosis #13.4)" contact edge4way ~(poly2,ecap,phr,p2c,p2m12c)/cap poly2,ecap,phr,p2c,p2m12c 1 ~(p2c,p2m12c)/cap poly2,ecap,phr,p2c,p2m12c 1 \ "Poly2 overlap of Poly2 contact < 1 (Mosis #13.4)" cap spacing gv2 gv2 3 touching_ok \ "GV2 via spacing < 3 (Mosis #14.2)" spacing gv2 m3c/m2 2 touching_illegal \ "GV2 via spacing to Metal3 contact < 2 (Mosis #14.2)" edge4way gv2 space 1 m2,fm2,rm2,m2c/m2,m3c/m2 space 1 \ "Metal2 must overlap GV2 via by 1 (Mosis #14.3)" metal2 edge4way ~(m2,fm2,rm2,m2c/m2,m3c/m2)/metal2 m2,fm2,rm2,m2c/m2,m3c/m2 1 ~(gv2)/via2 0 0 \ "Metal2(edge) cannot touch GV2 via (Mosis #14.3)" via2 spacing m3,rm3,m3c/m3,pad m3,rm3,m3c/m3,pad 3 touching_ok \ "Metal3 spacing < 3 (Mosis #15.2)" spacing m3,rm3,m3c/m3,pad fm3,fapm 3 touching_illegal \ "Metal3 spacing to fill layer (fm3) < 3 (Mosis #15.2)" spacing fm3 fm3 4 touching_ok \ "Metal3 fill layer (fm3) spacing < 4 (Mosis #0)" edge4way m3c/m2 ~(m3c/m2)/metal2 1 m3,fm3,rm3,m3c/m3,pad ~(m3c/m2)/metal2 1 \ "Metal3 overlap of Metal3 contact < 1 (Mosis #15.3)" metal3 edge4way gv2 space 2 m3,fm3,rm3,m3c/m3,pad space 2 \ "Metal3 must overlap GV2 via by 2 (Mosis #15.3)" metal3 edge4way ~(m3,fm3,rm3,m3c/m3,pad)/metal3 m3,fm3,rm3,m3c/m3,pad 1 ~(gv2)/via2 0 0 \ "Metal3(edge) cannot touch GV2 via (Mosis #15.3)" via2 spacing hr,phr hr,phr 4 touching_ok \ "High-Resist spacing < 4 (Mosis #27.2)" spacing hr,phr,phr p2c,p2m12c 2 touching_illegal \ "High-Resist spacing to Poly2 contact < 2 (Mosis #27.3)" spacing hr,phr,phr gc 2 touching_illegal \ "High-Resist spacing to GC contact < 2 (Mosis #27.3)" edge4way hr,phr space 2 ~(ndiff,rnd,ndc/a,pdiff,rpd,pdc/a)/active 0 2 \ "High-Resist space to Diffusion < 2 (Mosis #27.4)" active spacing hr,phr,phr poly2,ecap,phr,p2c,p2m12c 2 touching_ok \ "High-Resist spacing to other Poly2 < 2 (Mosis #27.5)" edge4way hr,phr space 2 ~(poly2,ecap,phr,p2c,p2m12c)/contact hr,phr 2 \ "High-Resist space to Poly2 < 2 (Mosis #27.5x)" contact spacing nwell phr 4 touching_illegal \ "N-well spacing to Silicide-Block poly2R < 4 (Mosis #27.6)" spacing phr phr 7 touching_ok \ "High-Resist poly2R spacing < 7 (Mosis #27.13)" edge4way phr space/active,hr 2 hr hr 2 \ "High-Resist overlap of High-Resist poly2R < 2 (Mosis #27.15)" spacing nfi nfi 4 touching_ok \ "N_field-implant spacing < 4 (Mosis #35.2)" spacing pfi pfi 4 touching_ok \ "P_field-implant spacing < 4 (Mosis #35.2)" spacing nfi pfi 4 touching_illegal \ "N_field-implant spacing to P_field-implant < 4 (Mosis #35.2)" spacing nwell,pdiff,rpd,pfet,pdc/a pfi 4 touching_illegal \ "N-well,P-Diffusion spacing to P_field-implant < 4 (Mosis #2.1)" spacing pwell,ndiff,rnd,nfet,ndc/a nfi 4 touching_illegal \ "P-well,N-Diffusion spacing to N_field-implant < 4 (Mosis #2.1)" edge4way ~(nwell)/well nwell 4 ~(nfi)/implant nwell 4 \ "N-well overlap of N_field-implant < 4 (Mosis #21.2)" implant edge4way ~(pwell)/well pwell 4 ~(pfi)/implant pwell 4 \ "P-well overlap of P_field-implant < 4 (Mosis #21.2)" implant spacing fa fapm 4 touching_illegal \ "fill layer fa spacing to fill layer fapm < 4 (Mosis #0)" width fa 7 \ "filla width < 7 (Mosis #0)" width fapm 7 \ "fillapm width < 7 (Mosis #0)" width fp 7 \ "fillp width < 7 (Mosis #0)" width fm1 7 \ "fillm1 width < 7 (Mosis #0)" width fm2 7 \ "fillm2 width < 7 (Mosis #0)" width fm3 7 \ "fillm3 width < 7 (Mosis #0)" edge4way fa ~(fa)/fill 1 ~(fa)/fill (~(fa),fa)/fill 1 \ "Contact not rectangular (Magic rule)" edge4way fb ~(fb)/fill 1 ~(fb)/fill (~(fb),fb)/fill 1 \ "Contact not rectangular (Magic rule)" edge4way fapm ~(fapm)/active 1 ~(fapm)/active (~(fapm),fapm)/active 1 \ "Contact not rectangular (Magic rule)" edge4way fp ~(fp)/active 1 ~(fp)/active (~(fp),fp)/active 1 \ "Contact not rectangular (Magic rule)" edge4way fm1 ~(fm1)/metal1 1 ~(fm1)/metal1 (~(fm1),fm1)/metal1 1 \ "Contact not rectangular (Magic rule)" edge4way fm2 ~(fm2)/metal2 1 ~(fm2)/metal2 (~(fm2),fm2)/metal2 1 \ "Contact not rectangular (Magic rule)" edge4way fm3 ~(fm3)/metal3 1 ~(fm3)/metal3 (~(fm3),fm3)/metal3 1 \ "Contact not rectangular (Magic rule)" edge4way rp space/active 1 prp 0 0 \ "prp overhang of rpoly (for resistor L/W extraction) < 1 (Mosis #0)" active edge4way rp2 space/cap 1 prp2 0 0 \ "prp2 overhang of rpoly2 (for resistor L/W extraction) < 1 (Mosis #0)" cap edge4way rnw space/active 1 prnw 0 0 \ "prnw overhang of rnwell (for resistor L/W extraction) < 1 (Mosis #0)" active edge4way rpd space/active 1 prpd 0 0 \ "prpd overhang of rpdiff (for resistor L/W extraction) < 1 (Mosis #0)" active edge4way rnd space/active 1 prnd 0 0 \ "prnd overhang of rndiff (for resistor L/W extraction) < 1 (Mosis #0)" active edge4way rm1 space/metal1 1 prm1 0 0 \ "prm1 overhang of rmetal1 (for resistor L/W extraction) < 1 (Mosis #0)" metal1 edge4way rm2 space/metal2 1 prm2 0 0 \ "prm2 overhang of rmetal2 (for resistor L/W extraction) < 1 (Mosis #0)" metal2 edge4way rm3 space/metal3 1 prm3 0 0 \ "prm3 overhang of rmetal3 (for resistor L/W extraction) < 1 (Mosis #0)" metal3 edge4way ndc/a,nsc/a ~(ndc/a,nsc/a)/active 1 ~(ndc/a,nsc/a)/active (~(ndc/a,nsc/a),ndc/a,nsc/a)/active 1 \ "Contact not rectangular (Magic rule)" edge4way pdc/a,psc/a ~(pdc/a,psc/a)/active 1 ~(pdc/a,psc/a)/active (~(pdc/a,psc/a),pdc/a,psc/a)/active 1 \ "Contact not rectangular (Magic rule)" edge4way pc/a ~(pc/a)/active 1 ~(pc/a)/active (~(pc/a),pc/a)/active 1 \ "Contact not rectangular (Magic rule)" edge4way gc2 ~(gc2)/contact 1 ~(gc2)/contact (~(gc2),gc2)/contact 1 \ "Contact not rectangular (Magic rule)" edge4way p2c,p2m12c ~(p2c,p2m12c)/cap 1 ~(p2c,p2m12c)/cap (~(p2c,p2m12c),p2c,p2m12c)/cap 1 \ "Contact not rectangular (Magic rule)" edge4way gc ~(gc)/contact 1 ~(gc)/contact (~(gc),gc)/contact 1 \ "Contact not rectangular (Magic rule)" edge4way gv1 ~(gv1)/via1 1 ~(gv1)/via1 (~(gv1),gv1)/via1 1 \ "Contact not rectangular (Magic rule)" edge4way m2c/m1 ~(m2c/m1)/metal1 1 ~(m2c/m1)/metal1 (~(m2c/m1),m2c/m1)/metal1 1 \ "Contact not rectangular (Magic rule)" edge4way gv2 ~(gv2)/via2 1 ~(gv2)/via2 (~(gv2),gv2)/via2 1 \ "Contact not rectangular (Magic rule)" edge4way m3c/m2 ~(m3c/m2)/metal2 1 ~(m3c/m2)/metal2 (~(m3c/m2),m3c/m2)/metal2 1 \ "Contact not rectangular (Magic rule)" exact_overlap gc,ndc/a,pdc/a,psc/a,nsc/a,gc,pc/a,gc exact_overlap gc2,p2c,p2m12c edge4way pad ~(pad)/m3 1 ~(pad)/m3 (~(pad),pad)/m3 1 \ "Contact not rectangular (Magic rule)" exact_overlap ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1 exact_overlap m2c/m2 exact_overlap m3c/m3 exact_overlap gv1 exact_overlap gv2 width m1p 4 \ "Metal1 PIN width < 4 (do_pins)" spacing m1p m1p 4 touching_ok \ "Metal1 PIN spacing < 4 (do_pins)" width m2p 4 \ "Metal2 PIN width < 4 (do_pins)" spacing m2p m2p 4 touching_ok \ "Metal2 PIN spacing < 4 (do_pins)" width m3p 6 \ "Metal3 PIN width < 6 (do_pins)" spacing m3p m3p 4 touching_ok \ "Metal3 PIN spacing < 4 (do_pins)" #CC cifstyle lambda=0.30(p) #CC cifwidth CWN 360 \ #CC "generated CIF layer CWN width will be < 12 (';cif see CWN')" #CC cifspacing CWN CWN 180 touching_ok \ #CC "generated CIF layer CWN spacing will be < 6 (';cif see CWN')" #CC cifwidth CWP 360 \ #CC "generated CIF layer CWP width will be < 12 (';cif see CWP')" #CC cifspacing CWP CWP 180 touching_ok \ #CC "generated CIF layer CWP spacing will be < 6 (';cif see CWP')" #CC cifwidth CSN 60 \ #CC "generated CIF layer CSN width will be < 2 (';cif see CSN')" #CC cifspacing CSN CSN 60 touching_ok \ #CC "generated CIF layer CSN spacing will be < 2 (';cif see CSN')" #CC cifwidth CSP 60 \ #CC "generated CIF layer CSP width will be < 2 (';cif see CSP')" #CC cifspacing CSP CSP 60 touching_ok \ #CC "generated CIF layer CSP spacing will be < 2 (';cif see CSP')" stepsize 400 end #--------------------------------------------------- # LEF format definitions #--------------------------------------------------- lef ignore PC ignore CA routing m1 M1 m1 met1 routing m2 M2 m2 met2 routing m3 M3 m3 met3 contact m2c via via1 V1 v1 contact m3c via2 V2 v2 end extract style AMI0.5um(amic5)from:T24H cscale 1 lambda 30 step 100 sidehalo 8 planeorder well 0 planeorder implant 1 planeorder select 2 planeorder cap 3 planeorder active 4 planeorder metal1 5 planeorder metal2 6 planeorder metal3 7 planeorder oxide 8 planeorder xp 9 planeorder comment 10 planeorder contact 11 planeorder via1 12 planeorder via2 13 planeorder fill 14 resist (ndiff,rnd,ndc,nsd,nsc)/active 82200 resist (pdiff,rpd,pdc,psd,psc)/active 105200 resist (nwell)/well 808000 resist (rnw)/active 808000 resist (pwell)/well 1 resist (poly,fp,rp,pc,pc,nfet,pfet,fet)/active 22000 resist (poly2,ecap,p2c,p2m12c,p2c,p2m12c)/cap 40300 resist (phr)/cap 40300 resist (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c,m2c)/metal1 90 resist (m2,fm2,rm2,m2c,m3c,m3c)/metal2 90 resist (m3,fm3,rm3,m3c,pad)/metal3 50 contact ndc 4 62700 contact pdc 4 160000 contact pc 4 15600 contact p2c 4 26100 contact m2c 4 910 contact m3c 4 830 #poly2 overlap (poly,fp,rp,pc,pc)/active (poly2,ecap,phr,p2c,p2m12c,p2c,p2m12c)/cap 84.960 #nwell,cwell,pwell areacap (nwell)/well 3.600 #rnw areacap (rnw)/active 3.600 #ndiff # MODEL HANDLES THIS: areacap (ndiff,ndc)/active 38.430 # MODEL HANDLES THIS: overlap (ndiff,ndc)/active ~space/w 38.430 # MODEL HANDLES THIS: perimc (ndiff,ndc)/active ~(ndiff,ndc,nfet,pfet,fet)/active 94.800 # MODEL HANDLES THIS: sideoverlap (ndiff,ndc)/active ~(ndiff,ndc,nfet,pfet,fet)/active ~space/w 94.800 areacap (rnd)/active 38.430 overlap (rnd)/active ~space/w 38.430 perimc (rnd)/active ~(rnd)/active 94.800 sideoverlap (rnd)/active ~(rnd)/active ~space/w 94.800 #pdiff # MODEL HANDLES THIS: areacap (pdiff,pdc)/active 65.880 # MODEL HANDLES THIS: overlap (pdiff,pdc)/active ~space/w 65.880 # MODEL HANDLES THIS: perimc (pdiff,pdc)/active ~(pdiff,pdc,nfet,pfet,fet)/active 75.300 # MODEL HANDLES THIS: sideoverlap (pdiff,pdc)/active ~(pdiff,pdc,nfet,pfet,fet)/active ~space/w 75.300 areacap (rpd)/active 65.880 overlap (rpd)/active ~space/w 65.880 perimc (rpd)/active ~(rpd)/active 75.300 sideoverlap (rpd)/active ~(rpd)/active ~space/w 75.300 #rnw #poly # MODEL HANDLES THIS: overlap (nfet)/active (ndiff,rnd,ndc)/active 221.670 # MODEL HANDLES THIS: sideoverlap (nfet)/active ~(nfet)/active (ndiff,rnd,ndc)/active 58.500 # MODEL HANDLES THIS: overlap (pfet)/active (pdiff,rpd,pdc)/active 213.480 # MODEL HANDLES THIS: sideoverlap (pfet)/active ~(pfet)/active (pdiff,rpd,pdc)/active 82.800 areacap (poly,fp,rp,pc)/active 7.740 overlap (poly,fp,rp,pc)/active ~space/w 7.740 #poly2 #rnw #metal1 areacap (m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 2.700 #metal1-sub blocked by ~space/a,~space/c overlap (m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 ~space/w 2.700 ~space/a,~space/c perimc (m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 20.700 sideoverlap (m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 ~space/w 20.700 ~space/a,~space/c #rnw overlap (m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 rnw/active 2.700 ~space/c sideoverlap (m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 rnw/active 20.700 ~space/c #metal1-diff blocked by ~space/c overlap (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 (ndiff,rnd,ndc)/active 3.150 ~space/c sideoverlap (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 (ndiff,rnd,ndc)/active 20.700 ~space/c overlap (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 (pdiff,rpd,pdc)/active 3.150 ~space/c sideoverlap (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 (pdiff,rpd,pdc)/active 20.700 ~space/c #metal1-poly blocked by ~space/c overlap (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 (poly,fp,rp,pc,nfet,pfet,fet)/active 4.590 ~space/c sideoverlap (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 (poly,fp,rp,pc,nfet,pfet,fet)/active 15.900 ~space/c sideoverlap (poly,fp,rp,pc,nfet,pfet,fet)/active ~(poly,fp,rp,pc,nfet,pfet,fet)/active (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 15.900 ~space/c #metal1-poly2 not blocked overlap (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 (poly2,ecap,phr,p2c,p2m12c)/cap 3.960 #metal2 areacap (m2,fm2,rm2,m3c)/metal2 1.350 #metal2-sub blocked by overlap (m2,fm2,rm2,m3c)/metal2 ~space/w 1.350 ~space/a,~space/m1,~space/c perimc (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 15.900 sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 ~space/w 15.900 ~space/a,~space/m1,~space/c overlap (m2,fm2,rm2,m3c)/metal2 rnw/active 1.350 ~space/m1,~space/c sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 rnw/active 15.900 ~space/m1,~space/c #metal2-*diff blocked by ~space/m1,~space/c overlap (m2,fm2,rm2,m3c)/metal2 (ndiff,rnd,ndc)/active 1.350 ~space/m1,~space/c sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 (ndiff,rnd,ndc)/active 15.900 ~space/m1,~space/c overlap (m2,fm2,rm2,m2c,m3c)/metal2 (pdiff,rpd,pdc)/active 1.350 ~space/m1,~space/c sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 (pdiff,rpd,pdc)/active 15.900 ~space/m1,~space/c #metal2-poly blocked by ~space/m1,~space/c overlap (m2,fm2,rm2,m3c)/metal2 (poly,fp,rp,pc,nfet,pfet,fet)/active 1.350 ~space/m1,~space/c sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 (poly,fp,rp,pc,nfet,pfet,fet)/active 10.800 ~space/m1,~space/c sideoverlap (poly,fp,rp,pc,nfet,pfet,fet)/active ~(poly,fp,rp,pc,nfet,pfet,fet)/active (m2,fm2,rm2,m2c,m3c)/metal2 10.800 ~space/m1,~space/c #metal2-poly2 blocked by ~space/m1 #M2->M1 overlap (m2,fm2,rm2,m3c)/metal2 (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 2.520 sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 14.700 sideoverlap (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 (m2,fm2,rm2,m2c,m3c)/metal2 14.700 #metal3 areacap (m3,fm3,rm3,pad)/metal3 0.900 #metal3-sub blocked by ~space/a,~space/m1,~space/m2,~space/c overlap (m3,fm3,rm3,pad)/metal3 ~space/w 0.900 ~space/a,~space/m1,~space/m2,~space/c perimc (m3,fm3,rm3,m3c,pad)/metal3 ~(m3,fm3,rm3,m3c,pad)/metal3 10.500 sideoverlap (m3,fm3,rm3,m3c,pad)/metal3 ~(m3,fm3,rm3,m3c,pad)/metal3 ~space/w 10.500 ~space/a,~space/m1,~space/m2,~space/c #rnw overlap (m3,fm3,rm3,pad)/metal3 rnw/active 0.900 ~space/m1,~space/m2,~space/c sideoverlap (m3,fm3,rm3,m3c,pad)/metal3 ~(m3,fm3,rm3,m3c,pad)/metal3 rnw/active 10.500 ~space/m1,~space/m2,~space/c #metal3-*diff blocked by ~space/m1,~space/m2,~space/c overlap (m3,fm3,rm3,pad)/metal3 (ndiff,rnd,ndc)/active 0.990 ~space/m1,~space/m2,~space/c sideoverlap (m3,fm3,rm3,m3c,pad)/metal3 ~(m3,fm3,rm3,m3c,pad)/metal3 (ndiff,rnd,ndc)/active 10.500 ~space/m1,~space/m2,~space/c overlap (m3,fm3,rm3,pad)/metal3 (pdiff,rpd,pdc)/active 0.990 ~space/m1,~space/m2,~space/c sideoverlap (m3,fm3,rm3,m3c,pad)/metal3 ~(m3,fm3,rm3,m3c,pad)/metal3 (pdiff,rpd,pdc)/active 10.500 ~space/m1,~space/m2,~space/c #metal3-poly blocked by ~space/m1,~space/m2,~space/c overlap (m3,fm3,rm3,pad)/metal3 (poly,fp,rp,pc,nfet,pfet,fet)/active 0.810 ~space/m1,~space/m2,~space/c sideoverlap (m3,fm3,rm3,m3c,pad)/metal3 ~(m3,fm3,rm3,m3c,pad)/metal3 (poly,fp,rp,pc,nfet,pfet,fet)/active 8.100 ~space/m1,~space/m2,~space/c sideoverlap (poly,fp,rp,pc,nfet,pfet,fet)/active ~(poly,fp,rp,pc,nfet,pfet,fet)/active (m3,fm3,rm3,m3c,pad)/metal3 8.100 ~space/m1,~space/m2,~space/c #metal3-poly2 blocked by ~space/m1,~space/m2 #M3->M1 overlap (m3,fm3,rm3,pad)/metal3 (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 1.080 ~space/m2 #metal3-metal1 blocked by ~space/m2 sideoverlap (m3,fm3,rm3,m3c,pad)/metal3 ~(m3,fm3,rm3,m3c,pad)/metal3 (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 9.900 ~space/m2 sideoverlap (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 (m3,fm3,rm3,m3c,pad)/metal3 9.900 ~space/m2 #M3->M2 overlap (m3,fm3,rm3,pad)/metal3 (m2,fm2,rm2,m2c,m3c)/metal2 3.060 sideoverlap (m3,fm3,rm3,m3c,pad)/metal3 ~(m3,fm3,rm3,m3c,pad)/metal3 (m2,fm2,rm2,m2c,m3c)/metal2 16.800 sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 (m3,fm3,rm3,m3c,pad)/metal3 16.800 #metal4 #metal5 #metal6 #metal7 #metali #fets # fet pfet pdiff,pdc 2 pfet Vdd! nwell 83 213 # fet pfet pdiff,pdc 1 pfet Vdd! nwell 83 213 device mosfet pfet pfet pdiff,pdc nwell $VDD 83 213 # fet nfet ndiff,ndc 2 nfet Gnd! pwell 59 222 # fet nfet ndiff,ndc 1 nfet Gnd! pwell 59 222 device mosfet nfet nfet ndiff,ndc pwell $GND 59 222 fetresis pfet linear 20996 fetresis pfet saturation 20996 fetresis nfet linear 6144 fetresis nfet saturation 6144 # fet rnwell nsd,nsc 2 nwellResistor Gnd! nwell,pwell 0 0 # fet rpoly poly,pc 2 polyResistor Gnd! nwell,pwell 0 0 # fet rpoly2 poly2,p2c 2 poly2Resistor Gnd! nwell,pwell 0 0 # fet rndiff ndiff,ndc 2 ndiffResistor Gnd! nwell,pwell 0 0 # fet rpdiff pdiff,pdc 2 pdiffResistor Gnd! nwell,pwell 0 0 device resistor None rnwell nsd,nsc device resistor None rpoly poly,pc device resistor None rpoly2 poly2,p2c device resistor None rndiff ndiff,ndc device resistor None rpdiff pdiff,pdc # fet rmetal1 metal1 2 metal1Resistor Gnd! nwell,pwell 0 0 # fet rmetal2 metal2 2 metal2Resistor Gnd! nwell,pwell 0 0 # fet rmetal3 metal3 2 metal3Resistor Gnd! nwell,pwell 0 0 # fet phr poly2,p2c 2 phrResistor Gnd! nwell,pwell 0 0 device resistor None rmetal1 *metal1 device resistor None rmetal2 *metal2 device resistor None rmetal3 *metal3 device resistor None phr poly2,p2c end wiring contact pdcontact 4 metal1 0 pdiff 0 contact ndcontact 4 metal1 0 ndiff 0 contact pcontact 4 metal1 0 poly 0 contact m2contact 4 metal1 0 metal2 0 contact m3contact 5 metal2 0 metal3 1 end router layer2 metal2 3 m2,fm2,rm2,m2c/m2,m3c/m2,m3c/m2 4 poly,fp,rp,ndiff,rnd,nsd,pdiff,rpd,psd,m1,fm1,rm1 1 layer1 metal1 3 m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 3 contacts m2contact 4 gridspacing 8 end plowing fixed nfet,pfet,glass,pad covered nfet,pfet drag nfet,pfet end plot style colorversatec ndiff,rnd,ndc/a yellow \ 5555 AAAA 5555 AAAA \ 5555 AAAA 5555 AAAA \ 5555 AAAA 5555 AAAA \ 5555 AAAA 5555 AAAA ndiff,rnd,ndc/a cyan \ 0000 5555 0000 5555 \ 0000 5555 0000 5555 \ 0000 5555 0000 5555 \ 0000 5555 0000 5555 nsd,nsc/a yellow \ 1515 2A2A 5151 A2A2 \ 1515 2A2A 5151 A2A2 \ 1515 2A2A 5151 A2A2 \ 1515 2A2A 5151 A2A2 nsd,nsc/a cyan \ 0000 1515 0000 5151 \ 0000 1515 0000 5151 \ 0000 1515 0000 5151 \ 0000 1515 0000 5151 pdiff,rpd,pdc/a yellow \ 5555 AAAA 5555 AAAA \ 5555 AAAA 5555 AAAA \ 5555 AAAA 5555 AAAA \ 5555 AAAA 5555 AAAA pdiff,rpd,pdc/a cyan \ 0000 5555 0000 5555 \ 0000 5555 0000 5555 \ 0000 5555 0000 5555 \ 0000 5555 0000 5555 pdiff,rpd,pdc/a magenta \ AAAA 0000 AAAA 0000 \ AAAA 0000 AAAA 0000 \ AAAA 0000 AAAA 0000 \ AAAA 0000 AAAA 0000 psd,psc/a yellow \ 1515 2A2A 5151 A2A2 \ 1515 2A2A 5151 A2A2 \ 1515 2A2A 5151 A2A2 \ 1515 2A2A 5151 A2A2 psd,psc/a cyan \ 0000 1515 0000 5151 \ 0000 1515 0000 5151 \ 0000 1515 0000 5151 \ 0000 1515 0000 5151 psd,psc/a magenta \ 2A2A 0000 A2A2 0000 \ 2A2A 0000 A2A2 0000 \ 2A2A 0000 A2A2 0000 \ 2A2A 0000 A2A2 0000 poly,fp,rp,pc/a magenta \ 5555 AAAA 5555 AAAA \ 5555 AAAA 5555 AAAA \ 5555 AAAA 5555 AAAA \ 5555 AAAA 5555 AAAA nfet yellow \ 0505 8282 1414 0A0A \ 5050 2828 4141 A0A0 \ 0505 8282 1414 0A0A \ 5050 2828 4141 A0A0 nfet cyan \ 0000 0505 0000 1414 \ 0000 5050 0000 4141 \ 0000 0505 0000 1414 \ 0000 5050 0000 4141 nfet magenta \ 5050 2828 4141 A0A0 \ 0505 8282 1414 0A0A \ 5050 2828 4141 A0A0 \ 0505 8282 1414 0A0A pfet yellow \ 6363 A0A0 5050 2828 \ 3636 0A0A 0505 8282 \ 6363 A0A0 5050 2828 \ 3636 0A0A 0505 8282 pfet cyan \ 0000 5151 0000 5454 \ 0000 1515 0000 1515 \ 0000 5151 0000 5454 \ 0000 1515 0000 1515 pfet magenta \ 9494 0A0A 2525 8282 \ 4949 A0A0 5252 2828 \ 9494 0A0A 2525 8282 \ 4949 A0A0 5252 2828 poly2,ecap,phr,p2c,p2m12c yellow \ FFFF FFFF FFFF FFFF \ FFFF FFFF FFFF FFFF \ FFFF FFFF FFFF FFFF \ FFFF FFFF FFFF FFFF m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 cyan \ AAAA 0000 AAAA 0000 \ AAAA 0000 AAAA 0000 \ AAAA 0000 AAAA 0000 \ AAAA 0000 AAAA 0000 m2,fm2,rm2,m2c/m2,m3c/m2 cyan \ 0000 1111 0000 4444 \ 0000 1111 0000 4444 \ 0000 1111 0000 4444 \ 0000 1111 0000 4444 m2,fm2,rm2,m2c/m2,m3c/m2 magenta \ 0000 4444 0000 1111 \ 0000 4444 0000 1111 \ 0000 4444 0000 1111 \ 0000 4444 0000 1111 m2c/m1,gv1 black \ 0000 6666 6666 0000 \ 0000 9999 9999 0000 \ 0000 6666 6666 0000 \ 0000 9999 9999 0000 pad,glass black \ 0300 0700 0E00 1C00 \ 3800 7000 E000 C000 \ 00C0 00E0 0070 0038 \ 001C 000E 0007 0003 nwell yellow \ 0800 1000 2000 4000 \ 8000 0001 0002 0004 \ 0008 0010 0020 0040 \ 0080 0010 0200 0400 nwell cyan \ 1000 2000 4000 8000 \ 0001 0002 0004 0008 \ 0010 0020 0040 0080 \ 0100 0200 0400 0800 pwell yellow \ 1000 0400 0400 0100 \ 0100 0040 0040 0010 \ 0010 0004 0004 0001 \ 0001 4000 4000 1000 pwell cyan \ 0000 0800 0000 0200 \ 0000 0080 0000 0020 \ 0000 0008 0000 0002 \ 0000 8000 0000 2000 pwell magenta \ 0800 0000 0200 0000 \ 0080 0000 0020 0000 \ 0008 0000 0002 0000 \ 8000 0000 2000 0000 m3c/m2,gv2 black \ 0100 0000 0000 0000 \ 1010 0000 0000 0000 \ 0001 0000 0000 0000 \ 1010 0000 0000 0000 m3c/m2,gv2 cyan \ 0280 0000 0820 0000 \ 2008 0000 8002 0000 \ 8002 0000 2008 0000 \ 0820 0000 0280 0000 m3c/m2,gv2 magenta \ 0100 06C0 0440 1830 \ 1010 600C 4004 8003 \ 0001 C006 4004 3018 \ 1010 0C60 0440 0380 m3c/m2,gv2 black \ 0820 0820 0820 0FE0 \ E00F 2008 2008 2008 \ 2008 2008 2008 E00F \ 0000 0FE0 0820 0820 error_p,error_s,error_ps black \ 0000 3C3C 4646 4A4A \ 5252 6262 3C3C 0000 \ 0000 3C3C 4646 4A4A \ 5252 6262 3C3C 0000 magnet yellow \ AAAA 0000 5555 0000 \ AAAA 0000 5555 0000 \ AAAA 0000 5555 0000 \ AAAA 0000 5555 0000 fence magenta \ FFFF 0000 0000 0000 \ 0000 0000 0000 0000 \ FFFF 0000 0000 0000 \ 0000 0000 0000 0000 rotate cyan \ 0000 E0E0 E0E0 E0E0 \ 0000 0000 0000 0000 \ 0000 E0E0 E0E0 E0E0 \ 0000 0000 0000 0000 pc/a,ndc/a,pdc/a,psc/a,nsc/a,gc,gc,gc X style versatec pfet \ 07c0 0f80 1f00 3e00 \ 7c00 f800 f001 e003 \ c007 800f 001f 003e \ 00c7 00f8 01f0 03e0 nfet \ 1f00 0f80 07c0 03e0 \ 01f0 00f8 007c 003e \ 001f 800f c007 e003 \ f001 f800 7c00 3e00 gv1 \ c3c3 c3c3 0000 0000 \ 0000 0000 c3c3 c3c3 \ c3c3 c3c3 0000 0000 \ 0000 0000 c3c3 c3c3 pwell \ 2020 2020 2020 2020 \ 2020 2020 2020 2020 \ 0000 0000 0000 0000 \ 0000 0000 0000 0000 nwell \ 0808 0404 0202 0101 \ 0000 0000 0000 0000 \ 0808 0404 0202 0101 \ 0000 0000 0000 0000 poly,fp,rp,pc/a,nfet,pfet \ 0808 0400 0202 0101 \ 8080 4000 2020 1010 \ 0808 0004 0202 0101 \ 8080 0040 2020 1010 m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 \ 8080 0000 0000 0000 \ 0808 0000 0000 0000 \ 8080 0000 0000 0000 \ 0808 0000 0000 0000 pad,glass \ 0000 0000 1c1c 3e3e \ 3636 3e3e 1c1c 0000 \ 0000 0000 1c1c 3e3e \ 3636 3e3e 1c1c 0000 nsd,nsc/a \ 0808 1414 2222 4141 \ 8080 4040 2020 1010 \ 0808 1414 2222 4141 \ 8080 4040 2020 1010 m2,fm2,rm2,m2c/m2,m3c/m2 \ 0000 1111 0000 0000 \ 0000 1111 0000 0000 \ 0000 1111 0000 0000 \ 0000 1111 0000 0000 pdiff,rpd,pdc/a,pfet \ 0000 0808 5555 8080 \ 0000 8080 5555 0808 \ 0000 0808 5555 8080 \ 0000 8080 5555 0808 psd,psc/a \ 1414 2222 0000 2222 \ 4141 2222 0000 2222 \ 1414 2222 0000 2222 \ 4141 2222 0000 2222 ndiff,rnd,ndc/a,nfet \ 0808 1010 2020 4040 \ 8080 4141 2222 1414 \ 0808 1010 2020 4040 \ 8080 4141 2222 1414 pc/a,ndc/a,pdc/a,psc/a,nsc/a,gc,gc,gc X style gremlin pfet 9 nfet 10 gv1 11 pwell 15 nwell 16 poly,fp,rp,pc/a,nfet,pfet 19 pc/a,ndc/a,pdc/a,psc/a,nsc/a,gc,gc,gc 22 pad,glass 23 nsd,nsc/a 24 gv1 28 pdiff,rpd,pdc/a,pfet 29 psd,psc/a 30 ndiff,rnd,ndc/a,nfet 31 pc/a,ndc/a,pdc/a,psc/a,nsc/a,gc,gc,gc,gv1 X end qflow-1.1.23/tech/osu050/osu050_stdcells.sp0000644000175000001440000012524012526236535016725 0ustar timusers .subckt AND2X1 Y B vdd gnd A M0 a_2_6# A vdd vdd pfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M1 vdd B a_2_6# vdd pfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M2 Y a_2_6# vdd vdd pfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M3 a_9_6# A a_2_6# gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M4 gnd B a_9_6# gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M5 Y a_2_6# gnd gnd nfet w=3u l=0.6u + ad=0p pd=0u as=0p ps=0u .ends AND2X1 .subckt AND2X2 vdd gnd A B Y M0 a_2_6# A vdd vdd pfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M1 vdd B a_2_6# vdd pfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M2 Y a_2_6# vdd vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M3 a_9_6# A a_2_6# gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M4 gnd B a_9_6# gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M5 Y a_2_6# gnd gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u .ends AND2X2 .subckt AOI21X1 gnd vdd A B Y C M0 vdd A a_2_54# vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M1 a_2_54# B vdd vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M2 Y C a_2_54# vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M3 a_12_6# A gnd gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M4 Y B a_12_6# gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M5 gnd C Y gnd nfet w=3u l=0.6u + ad=0p pd=0u as=0p ps=0u .ends AOI21X1 .subckt AOI22X1 gnd vdd C D Y A B M0 vdd A a_2_54# vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M1 a_2_54# B vdd vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M2 Y D a_2_54# vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M3 a_2_54# C Y vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M4 a_11_6# A gnd gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M5 Y B a_11_6# gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M6 a_28_6# D Y gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M7 gnd C a_28_6# gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u .ends AOI22X1 .subckt BUFX2 vdd gnd A Y M0 vdd A a_2_6# vdd pfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M1 Y a_2_6# vdd vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M2 gnd A a_2_6# gnd nfet w=3u l=0.6u + ad=0p pd=0u as=0p ps=0u M3 Y a_2_6# gnd gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u .ends BUFX2 .subckt BUFX4 vdd gnd A Y M0 vdd A a_2_6# vdd pfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M1 Y a_2_6# vdd vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M2 vdd a_2_6# Y vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M3 gnd A a_2_6# gnd nfet w=4.5u l=0.6u + ad=0p pd=0u as=0p ps=0u M4 Y a_2_6# gnd gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M5 gnd a_2_6# Y gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u .ends BUFX4 .subckt CLKBUF1 A vdd gnd Y M0 a_9_6# A vdd vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M1 vdd A a_9_6# vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M2 a_25_6# a_9_6# vdd vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M3 vdd a_9_6# a_25_6# vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M4 a_41_6# a_25_6# vdd vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M5 vdd a_25_6# a_41_6# vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M6 Y a_41_6# vdd vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M7 vdd a_41_6# Y vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M8 a_9_6# A gnd gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M9 gnd A a_9_6# gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M10 a_25_6# a_9_6# gnd gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M11 gnd a_9_6# a_25_6# gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M12 a_41_6# a_25_6# gnd gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M13 gnd a_25_6# a_41_6# gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M14 Y a_41_6# gnd gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M15 gnd a_41_6# Y gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u .ends CLKBUF1 .subckt CLKBUF2 vdd gnd A Y M0 a_9_6# A vdd vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M1 vdd A a_9_6# vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M2 a_25_6# a_9_6# vdd vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M3 vdd a_9_6# a_25_6# vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M4 a_41_6# a_25_6# vdd vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M5 vdd a_25_6# a_41_6# vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M6 a_57_6# a_41_6# vdd vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M7 vdd a_41_6# a_57_6# vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M8 a_73_6# a_57_6# vdd vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M9 vdd a_57_6# a_73_6# vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M10 Y a_73_6# vdd vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M11 vdd a_73_6# Y vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M12 a_9_6# A gnd gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M13 gnd A a_9_6# gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M14 a_25_6# a_9_6# gnd gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M15 gnd a_9_6# a_25_6# gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M16 a_41_6# a_25_6# gnd gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M17 gnd a_25_6# a_41_6# gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M18 a_57_6# a_41_6# gnd gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M19 gnd a_41_6# a_57_6# gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M20 a_73_6# a_57_6# gnd gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M21 gnd a_57_6# a_73_6# gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M22 Y a_73_6# gnd gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M23 gnd a_73_6# Y gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u .ends CLKBUF2 .subckt CLKBUF3 gnd vdd A Y M0 a_9_6# A vdd vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M1 vdd A a_9_6# vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M2 a_25_6# a_9_6# vdd vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M3 vdd a_9_6# a_25_6# vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M4 a_41_6# a_25_6# vdd vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M5 vdd a_25_6# a_41_6# vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M6 a_57_6# a_41_6# vdd vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M7 vdd a_41_6# a_57_6# vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M8 a_73_6# a_57_6# vdd vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M9 vdd a_57_6# a_73_6# vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M10 a_89_6# a_73_6# vdd vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M11 vdd a_73_6# a_89_6# vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M12 a_105_6# a_89_6# vdd vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M13 vdd a_89_6# a_105_6# vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M14 Y a_105_6# vdd vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M15 vdd a_105_6# Y vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M16 a_9_6# A gnd gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M17 gnd A a_9_6# gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M18 a_25_6# a_9_6# gnd gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M19 gnd a_9_6# a_25_6# gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M20 a_41_6# a_25_6# gnd gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M21 gnd a_25_6# a_41_6# gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M22 a_57_6# a_41_6# gnd gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M23 gnd a_41_6# a_57_6# gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M24 a_73_6# a_57_6# gnd gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M25 gnd a_57_6# a_73_6# gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M26 a_89_6# a_73_6# gnd gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M27 gnd a_73_6# a_89_6# gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M28 a_105_6# a_89_6# gnd gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M29 gnd a_89_6# a_105_6# gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M30 Y a_105_6# gnd gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M31 gnd a_105_6# Y gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u .ends CLKBUF3 .subckt DFFNEGX1 CLK vdd D gnd Q M0 vdd CLK a_2_6# vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M1 a_17_74# D vdd vdd pfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M2 a_23_6# a_2_6# a_17_74# vdd pfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M3 a_31_74# CLK a_23_6# vdd pfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M4 vdd a_34_4# a_31_74# vdd pfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M5 a_34_4# a_23_6# vdd vdd pfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M6 a_61_74# a_34_4# vdd vdd pfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M7 a_66_6# CLK a_61_74# vdd pfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M8 a_76_84# a_2_6# a_66_6# vdd pfet w=3u l=0.6u + ad=0p pd=0u as=0p ps=0u M9 vdd Q a_76_84# vdd pfet w=3u l=0.6u + ad=0p pd=0u as=0p ps=0u M10 gnd CLK a_2_6# gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M11 Q a_66_6# vdd vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M12 a_17_6# D gnd gnd nfet w=3u l=0.6u + ad=0p pd=0u as=0p ps=0u M13 a_23_6# CLK a_17_6# gnd nfet w=3u l=0.6u + ad=0p pd=0u as=0p ps=0u M14 a_31_6# a_2_6# a_23_6# gnd nfet w=3u l=0.6u + ad=0p pd=0u as=0p ps=0u M15 gnd a_34_4# a_31_6# gnd nfet w=3u l=0.6u + ad=0p pd=0u as=0p ps=0u M16 a_34_4# a_23_6# gnd gnd nfet w=3u l=0.6u + ad=0p pd=0u as=0p ps=0u M17 a_61_6# a_34_4# gnd gnd nfet w=3u l=0.6u + ad=0p pd=0u as=0p ps=0u M18 a_66_6# a_2_6# a_61_6# gnd nfet w=3u l=0.6u + ad=0p pd=0u as=0p ps=0u M19 a_76_6# CLK a_66_6# gnd nfet w=3u l=0.6u + ad=0p pd=0u as=0p ps=0u M20 gnd Q a_76_6# gnd nfet w=3u l=0.6u + ad=0p pd=0u as=0p ps=0u M21 Q a_66_6# gnd gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u .ends DFFNEGX1 .subckt DFFPOSX1 vdd D gnd Q CLK M0 vdd CLK a_2_6# vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M1 a_17_74# D vdd vdd pfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M2 a_22_6# CLK a_17_74# vdd pfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M3 a_31_74# a_2_6# a_22_6# vdd pfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M4 vdd a_34_4# a_31_74# vdd pfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M5 a_34_4# a_22_6# vdd vdd pfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M6 a_61_74# a_34_4# vdd vdd pfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M7 a_66_6# a_2_6# a_61_74# vdd pfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M8 a_76_84# CLK a_66_6# vdd pfet w=3u l=0.6u + ad=0p pd=0u as=0p ps=0u M9 vdd Q a_76_84# vdd pfet w=3u l=0.6u + ad=0p pd=0u as=0p ps=0u M10 gnd CLK a_2_6# gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M11 Q a_66_6# vdd vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M12 a_17_6# D gnd gnd nfet w=3u l=0.6u + ad=0p pd=0u as=0p ps=0u M13 a_22_6# a_2_6# a_17_6# gnd nfet w=3u l=0.6u + ad=0p pd=0u as=0p ps=0u M14 a_31_6# CLK a_22_6# gnd nfet w=3u l=0.6u + ad=0p pd=0u as=0p ps=0u M15 gnd a_34_4# a_31_6# gnd nfet w=3u l=0.6u + ad=0p pd=0u as=0p ps=0u M16 a_34_4# a_22_6# gnd gnd nfet w=3u l=0.6u + ad=0p pd=0u as=0p ps=0u M17 a_61_6# a_34_4# gnd gnd nfet w=3u l=0.6u + ad=0p pd=0u as=0p ps=0u M18 a_66_6# CLK a_61_6# gnd nfet w=3u l=0.6u + ad=0p pd=0u as=0p ps=0u M19 a_76_6# a_2_6# a_66_6# gnd nfet w=3u l=0.6u + ad=0p pd=0u as=0p ps=0u M20 gnd Q a_76_6# gnd nfet w=3u l=0.6u + ad=0p pd=0u as=0p ps=0u M21 Q a_66_6# gnd gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u .ends DFFPOSX1 .subckt DFFSR gnd vdd D S R Q CLK M0 a_2_6# R vdd vdd pfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M1 vdd a_10_61# a_2_6# vdd pfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M2 a_10_61# a_23_27# vdd vdd pfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M3 vdd S a_10_61# vdd pfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M4 a_23_27# a_47_71# a_2_6# vdd pfet w=3u l=0.6u + ad=0p pd=0u as=0p ps=0u M5 a_57_6# a_47_4# a_23_27# vdd pfet w=3u l=0.6u + ad=0p pd=0u as=0p ps=0u M6 vdd D a_57_6# vdd pfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M7 vdd a_47_71# a_47_4# vdd pfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M8 a_47_71# CLK vdd vdd pfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M9 a_105_6# a_47_71# a_10_61# vdd pfet w=3u l=0.6u + ad=0p pd=0u as=0p ps=0u M10 a_113_6# a_47_4# a_105_6# vdd pfet w=3u l=0.6u + ad=0p pd=0u as=0p ps=0u M11 a_122_6# a_105_6# vdd vdd pfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M12 vdd R a_122_6# vdd pfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M13 a_113_6# a_122_6# vdd vdd pfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M14 vdd S a_113_6# vdd pfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M15 vdd a_122_6# Q vdd pfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M16 a_10_6# R a_2_6# gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M17 gnd a_10_61# a_10_6# gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M18 a_26_6# a_23_27# gnd gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M19 a_10_61# S a_26_6# gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M20 a_23_27# a_47_4# a_2_6# gnd nfet w=3u l=0.6u + ad=0p pd=0u as=0p ps=0u M21 a_57_6# a_47_71# a_23_27# gnd nfet w=3u l=0.6u + ad=0p pd=0u as=0p ps=0u M22 gnd D a_57_6# gnd nfet w=3u l=0.6u + ad=0p pd=0u as=0p ps=0u M23 gnd a_47_71# a_47_4# gnd nfet w=3u l=0.6u + ad=0p pd=0u as=0p ps=0u M24 a_47_71# CLK gnd gnd nfet w=3u l=0.6u + ad=0p pd=0u as=0p ps=0u M25 a_105_6# a_47_4# a_10_61# gnd nfet w=3u l=0.6u + ad=0p pd=0u as=0p ps=0u M26 a_113_6# a_47_71# a_105_6# gnd nfet w=3u l=0.6u + ad=0p pd=0u as=0p ps=0u M27 a_130_6# a_105_6# a_122_6# gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M28 gnd R a_130_6# gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M29 a_146_6# a_122_6# gnd gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M30 a_113_6# S a_146_6# gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M31 gnd a_122_6# Q gnd nfet w=3u l=0.6u + ad=0p pd=0u as=0p ps=0u .ends DFFSR .subckt FAX1 gnd vdd A B C YC YS M0 vdd A a_2_54# vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M1 a_2_54# B vdd vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M2 a_25_6# C a_2_54# vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M3 a_33_54# B a_25_6# vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M4 vdd A a_33_54# vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M5 a_46_54# A vdd vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M6 vdd B a_46_54# vdd pfet w=10.8u l=0.6u + ad=0p pd=0u as=0p ps=0u M7 a_46_54# C vdd vdd pfet w=10.8u l=0.6u + ad=0p pd=0u as=0p ps=0u M8 a_70_6# a_25_6# a_46_54# vdd pfet w=10.8u l=0.6u + ad=0p pd=0u as=0p ps=0u M9 a_79_46# C a_70_6# vdd pfet w=14.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M10 a_84_46# B a_79_46# vdd pfet w=14.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M11 vdd A a_84_46# vdd pfet w=14.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M12 YS a_70_6# vdd vdd pfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M13 YC a_25_6# vdd vdd pfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M14 gnd A a_2_6# gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M15 a_2_6# B gnd gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M16 a_25_6# C a_2_6# gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M17 a_33_6# B a_25_6# gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M18 gnd A a_33_6# gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M19 a_46_6# A gnd gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M20 gnd B a_46_6# gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M21 a_46_6# C gnd gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M22 a_70_6# a_25_6# a_46_6# gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M23 a_79_6# C a_70_6# gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M24 a_84_6# B a_79_6# gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M25 gnd A a_84_6# gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M26 YS a_70_6# gnd gnd nfet w=3u l=0.6u + ad=0p pd=0u as=0p ps=0u M27 YC a_25_6# gnd gnd nfet w=3u l=0.6u + ad=0p pd=0u as=0p ps=0u .ends FAX1 .subckt HAX1 vdd gnd YC A B YS M0 vdd A a_2_74# vdd pfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M1 a_2_74# B vdd vdd pfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M2 vdd a_2_74# YC vdd pfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M3 a_41_74# a_2_74# vdd vdd pfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M4 a_49_54# B a_41_74# vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M5 vdd A a_49_54# vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M6 YS a_41_74# vdd vdd pfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M7 a_9_6# A gnd gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M8 a_2_74# B a_9_6# gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M9 gnd a_2_74# YC gnd nfet w=3u l=0.6u + ad=0p pd=0u as=0p ps=0u M10 a_38_6# a_2_74# gnd gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M11 a_41_74# B a_38_6# gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M12 a_38_6# A a_41_74# gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M13 YS a_41_74# gnd gnd nfet w=3u l=0.6u + ad=0p pd=0u as=0p ps=0u .ends HAX1 .subckt INVX1 A Y vdd gnd M0 Y A vdd vdd pfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M1 Y A gnd gnd nfet w=3u l=0.6u + ad=0p pd=0u as=0p ps=0u .ends INVX1 .subckt INVX2 vdd gnd Y A M0 Y A vdd vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M1 Y A gnd gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u .ends INVX2 .subckt INVX4 vdd gnd Y A M0 Y A vdd vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M1 vdd A Y vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M2 Y A gnd gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M3 gnd A Y gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u .ends INVX4 .subckt INVX8 vdd gnd A Y M0 Y A vdd vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M1 vdd A Y vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M2 Y A vdd vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M3 vdd A Y vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M4 Y A gnd gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M5 gnd A Y gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M6 Y A gnd gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M7 gnd A Y gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u .ends INVX8 .subckt LATCH D Q gnd vdd CLK M0 vdd CLK a_2_6# vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M1 a_18_74# D vdd vdd pfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M2 a_23_6# a_2_6# a_18_74# vdd pfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M3 a_35_84# CLK a_23_6# vdd pfet w=3u l=0.6u + ad=0p pd=0u as=0p ps=0u M4 vdd Q a_35_84# vdd pfet w=3u l=0.6u + ad=0p pd=0u as=0p ps=0u M5 gnd CLK a_2_6# gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M6 Q a_23_6# vdd vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M7 a_18_6# D gnd gnd nfet w=3u l=0.6u + ad=0p pd=0u as=0p ps=0u M8 a_23_6# CLK a_18_6# gnd nfet w=3u l=0.6u + ad=0p pd=0u as=0p ps=0u M9 a_35_6# a_2_6# a_23_6# gnd nfet w=3u l=0.6u + ad=0p pd=0u as=0p ps=0u M10 gnd Q a_35_6# gnd nfet w=3u l=0.6u + ad=0p pd=0u as=0p ps=0u M11 Q a_23_6# gnd gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u .ends LATCH .subckt MUX2X1 S vdd gnd Y A B M0 vdd S a_2_10# vdd pfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M1 a_17_50# B vdd vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M2 Y S a_17_50# vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M3 a_30_54# a_2_10# Y vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M4 vdd A a_30_54# vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M5 gnd S a_2_10# gnd nfet w=3u l=0.6u + ad=0p pd=0u as=0p ps=0u M6 a_17_10# B gnd gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M7 Y a_2_10# a_17_10# gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M8 a_30_10# S Y gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M9 gnd A a_30_10# gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u .ends MUX2X1 .subckt NAND2X1 vdd Y gnd A B M0 Y A vdd vdd pfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M1 vdd B Y vdd pfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M2 a_9_6# A gnd gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M3 Y B a_9_6# gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u .ends NAND2X1 .subckt NAND3X1 B vdd gnd A C Y M0 Y A vdd vdd pfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M1 vdd B Y vdd pfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M2 Y C vdd vdd pfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M3 a_9_6# A gnd gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M4 a_14_6# B a_9_6# gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M5 Y C a_14_6# gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u .ends NAND3X1 .subckt NOR2X1 vdd B gnd Y A M0 a_9_54# A vdd vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M1 Y B a_9_54# vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M2 Y A gnd gnd nfet w=3u l=0.6u + ad=0p pd=0u as=0p ps=0u M3 gnd B Y gnd nfet w=3u l=0.6u + ad=0p pd=0u as=0p ps=0u .ends NOR2X1 .subckt NOR3X1 vdd gnd B C A Y M0 vdd A a_2_64# vdd pfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M1 a_2_64# A vdd vdd pfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M2 a_25_64# B a_2_64# vdd pfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M3 a_2_64# B a_25_64# vdd pfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M4 Y C a_25_64# vdd pfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M5 a_25_64# C Y vdd pfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M6 Y A gnd gnd nfet w=3u l=0.6u + ad=0p pd=0u as=0p ps=0u M7 gnd B Y gnd nfet w=3u l=0.6u + ad=0p pd=0u as=0p ps=0u M8 Y C gnd gnd nfet w=3u l=0.6u + ad=0p pd=0u as=0p ps=0u .ends NOR3X1 .subckt OAI21X1 gnd vdd A B Y C M0 a_9_54# A vdd vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M1 Y B a_9_54# vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M2 vdd C Y vdd pfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M3 gnd A a_2_6# gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M4 a_2_6# B gnd gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M5 Y C a_2_6# gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u .ends OAI21X1 .subckt OAI22X1 gnd vdd D C A B Y M0 a_9_54# A vdd vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M1 Y B a_9_54# vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M2 a_28_54# D Y vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M3 vdd C a_28_54# vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M4 gnd A a_2_6# gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M5 a_2_6# B gnd gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M6 Y D a_2_6# gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M7 a_2_6# C Y gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u .ends OAI22X1 .subckt OR2X1 Y B vdd gnd A M0 a_9_54# A a_2_54# vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M1 vdd B a_9_54# vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M2 Y a_2_54# vdd vdd pfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M3 a_2_54# A gnd gnd nfet w=3u l=0.6u + ad=0p pd=0u as=0p ps=0u M4 gnd B a_2_54# gnd nfet w=3u l=0.6u + ad=0p pd=0u as=0p ps=0u M5 Y a_2_54# gnd gnd nfet w=3u l=0.6u + ad=0p pd=0u as=0p ps=0u .ends OR2X1 .subckt OR2X2 Y B vdd gnd A M0 a_9_54# A a_2_54# vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M1 vdd B a_9_54# vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M2 Y a_2_54# vdd vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M3 a_2_54# A gnd gnd nfet w=3u l=0.6u + ad=0p pd=0u as=0p ps=0u M4 gnd B a_2_54# gnd nfet w=3u l=0.6u + ad=0p pd=0u as=0p ps=0u M5 Y a_2_54# gnd gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u .ends OR2X2 .subckt PADINC DI vdd2 gnd vdd gnd2 YPAD M0 vdd2 a_31_451# YPAD vdd2 pfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M1 YPAD a_31_451# vdd2 vdd2 pfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M2 vdd2 a_31_451# YPAD vdd2 pfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M3 YPAD a_31_451# vdd2 vdd2 pfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M4 vdd2 a_31_451# YPAD vdd2 pfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M5 YPAD a_31_451# vdd2 vdd2 pfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M6 vdd2 a_31_451# YPAD vdd2 pfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M7 YPAD a_31_451# vdd2 vdd2 pfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M8 vdd2 a_31_451# YPAD vdd2 pfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M9 YPAD a_31_451# vdd2 vdd2 pfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M10 vdd2 a_31_451# YPAD vdd2 pfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M11 YPAD a_31_451# vdd2 vdd2 pfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M12 gnd gnd2 a_13_269# gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M13 a_29_269# a_13_269# gnd gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M14 gnd gnd2 a_31_41# gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M15 a_31_41# gnd2 gnd gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M16 gnd gnd2 a_31_41# gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M17 a_31_41# gnd2 gnd gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M18 gnd gnd2 a_31_41# gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M19 a_31_41# a_13_269# gnd gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M20 gnd a_13_269# a_31_41# gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M21 a_31_41# a_13_269# gnd gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M22 gnd a_13_269# a_31_41# gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M23 a_31_41# a_13_269# gnd gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M24 a_31_451# a_29_269# a_31_41# gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M25 a_31_41# a_29_269# a_31_451# gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M26 a_31_451# a_29_269# a_31_41# gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M27 a_31_41# a_29_269# a_31_451# gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M28 a_200_269# a_191_395# gnd gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M29 gnd a_191_395# a_200_269# gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M30 a_200_269# a_191_395# gnd gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M31 gnd a_191_395# a_200_269# gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M32 a_200_269# a_191_395# gnd gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M33 gnd a_191_395# a_200_269# gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M34 DI a_200_269# gnd gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M35 gnd a_200_269# DI gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M36 DI a_200_269# gnd gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M37 gnd a_200_269# DI gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M38 DI a_200_269# gnd gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M39 gnd a_200_269# DI gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M40 vdd gnd2 a_13_269# vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M41 a_29_269# a_13_269# vdd vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M42 vdd gnd2 a_31_451# vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M43 a_31_451# gnd2 vdd vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M44 vdd gnd2 a_31_451# vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M45 a_31_451# gnd2 vdd vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M46 vdd gnd2 a_31_451# vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M47 a_31_451# a_29_269# vdd vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M48 vdd a_29_269# a_31_451# vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M49 a_31_451# a_29_269# vdd vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M50 vdd a_29_269# a_31_451# vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M51 a_31_451# a_29_269# vdd vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M52 a_31_41# a_13_269# a_31_451# vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M53 a_31_451# a_13_269# a_31_41# vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M54 a_31_41# a_13_269# a_31_451# vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M55 a_31_451# a_13_269# a_31_41# vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M56 a_200_269# a_191_395# vdd vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M57 vdd a_191_395# a_200_269# vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M58 a_200_269# a_191_395# vdd vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M59 vdd a_191_395# a_200_269# vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M60 a_200_269# a_191_395# vdd vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M61 vdd a_191_395# a_200_269# vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M62 DI a_200_269# vdd vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M63 vdd a_200_269# DI vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M64 DI a_200_269# vdd vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M65 vdd a_200_269# DI vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M66 DI a_200_269# vdd vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M67 vdd a_200_269# DI vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M68 gnd2 a_31_41# YPAD gnd2 nfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M69 YPAD a_31_41# gnd2 gnd2 nfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M70 gnd2 a_31_41# YPAD gnd2 nfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M71 YPAD a_31_41# gnd2 gnd2 nfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M72 gnd2 a_31_41# YPAD gnd2 nfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M73 YPAD a_31_41# gnd2 gnd2 nfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M74 gnd2 a_31_41# YPAD gnd2 nfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M75 YPAD a_31_41# gnd2 gnd2 nfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M76 gnd2 a_31_41# YPAD gnd2 nfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M77 YPAD a_31_41# gnd2 gnd2 nfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M78 gnd2 a_31_41# YPAD gnd2 nfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M79 YPAD a_31_41# gnd2 gnd2 nfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u R0 YPAD a_191_395# 100 R1 a_191_395# YPAD 100 .ends PADINC .subckt PADINOUT DO DI OEN gnd2 vdd2 vdd gnd YPAD M0 vdd2 a_31_451# YPAD vdd2 pfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M1 YPAD a_31_451# vdd2 vdd2 pfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M2 vdd2 a_31_451# YPAD vdd2 pfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M3 YPAD a_31_451# vdd2 vdd2 pfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M4 vdd2 a_31_451# YPAD vdd2 pfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M5 YPAD a_31_451# vdd2 vdd2 pfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M6 vdd2 a_31_451# YPAD vdd2 pfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M7 YPAD a_31_451# vdd2 vdd2 pfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M8 vdd2 a_31_451# YPAD vdd2 pfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M9 YPAD a_31_451# vdd2 vdd2 pfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M10 vdd2 a_31_451# YPAD vdd2 pfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M11 YPAD a_31_451# vdd2 vdd2 pfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M12 gnd OEN a_13_269# gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M13 a_29_269# a_13_269# gnd gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M14 gnd DO a_31_41# gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M15 a_31_41# DO gnd gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M16 gnd DO a_31_41# gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M17 a_31_41# DO gnd gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M18 gnd DO a_31_41# gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M19 a_31_41# a_13_269# gnd gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M20 gnd a_13_269# a_31_41# gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M21 a_31_41# a_13_269# gnd gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M22 gnd a_13_269# a_31_41# gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M23 a_31_41# a_13_269# gnd gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M24 a_31_451# a_29_269# a_31_41# gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M25 a_31_41# a_29_269# a_31_451# gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M26 a_31_451# a_29_269# a_31_41# gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M27 a_31_41# a_29_269# a_31_451# gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M28 a_200_269# a_191_395# gnd gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M29 gnd a_191_395# a_200_269# gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M30 a_200_269# a_191_395# gnd gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M31 gnd a_191_395# a_200_269# gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M32 a_200_269# a_191_395# gnd gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M33 gnd a_191_395# a_200_269# gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M34 DI a_200_269# gnd gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M35 gnd a_200_269# DI gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M36 DI a_200_269# gnd gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M37 gnd a_200_269# DI gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M38 DI a_200_269# gnd gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M39 gnd a_200_269# DI gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M40 vdd OEN a_13_269# vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M41 a_29_269# a_13_269# vdd vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M42 vdd DO a_31_451# vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M43 a_31_451# DO vdd vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M44 vdd DO a_31_451# vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M45 a_31_451# DO vdd vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M46 vdd DO a_31_451# vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M47 a_31_451# a_29_269# vdd vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M48 vdd a_29_269# a_31_451# vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M49 a_31_451# a_29_269# vdd vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M50 vdd a_29_269# a_31_451# vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M51 a_31_451# a_29_269# vdd vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M52 a_31_41# a_13_269# a_31_451# vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M53 a_31_451# a_13_269# a_31_41# vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M54 a_31_41# a_13_269# a_31_451# vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M55 a_31_451# a_13_269# a_31_41# vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M56 a_200_269# a_191_395# vdd vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M57 vdd a_191_395# a_200_269# vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M58 a_200_269# a_191_395# vdd vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M59 vdd a_191_395# a_200_269# vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M60 a_200_269# a_191_395# vdd vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M61 vdd a_191_395# a_200_269# vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M62 DI a_200_269# vdd vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M63 vdd a_200_269# DI vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M64 DI a_200_269# vdd vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M65 vdd a_200_269# DI vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M66 DI a_200_269# vdd vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M67 vdd a_200_269# DI vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M68 gnd2 a_31_41# YPAD gnd2 nfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M69 YPAD a_31_41# gnd2 gnd2 nfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M70 gnd2 a_31_41# YPAD gnd2 nfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M71 YPAD a_31_41# gnd2 gnd2 nfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M72 gnd2 a_31_41# YPAD gnd2 nfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M73 YPAD a_31_41# gnd2 gnd2 nfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M74 gnd2 a_31_41# YPAD gnd2 nfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M75 YPAD a_31_41# gnd2 gnd2 nfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M76 gnd2 a_31_41# YPAD gnd2 nfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M77 YPAD a_31_41# gnd2 gnd2 nfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M78 gnd2 a_31_41# YPAD gnd2 nfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M79 YPAD a_31_41# gnd2 gnd2 nfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u R0 YPAD a_191_395# 100 R1 a_191_395# YPAD 100 .ends PADINOUT .subckt PADOUT DO vdd2 gnd2 vdd gnd YPAD M0 vdd2 a_31_451# YPAD vdd2 pfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M1 YPAD a_31_451# vdd2 vdd2 pfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M2 vdd2 a_31_451# YPAD vdd2 pfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M3 YPAD a_31_451# vdd2 vdd2 pfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M4 vdd2 a_31_451# YPAD vdd2 pfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M5 YPAD a_31_451# vdd2 vdd2 pfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M6 vdd2 a_31_451# YPAD vdd2 pfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M7 YPAD a_31_451# vdd2 vdd2 pfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M8 vdd2 a_31_451# YPAD vdd2 pfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M9 YPAD a_31_451# vdd2 vdd2 pfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M10 vdd2 a_31_451# YPAD vdd2 pfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M11 YPAD a_31_451# vdd2 vdd2 pfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M12 gnd vdd a_13_269# gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M13 a_29_269# a_13_269# gnd gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M14 gnd DO a_31_41# gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M15 a_31_41# DO gnd gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M16 gnd DO a_31_41# gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M17 a_31_41# DO gnd gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M18 gnd DO a_31_41# gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M19 a_31_41# a_13_269# gnd gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M20 gnd a_13_269# a_31_41# gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M21 a_31_41# a_13_269# gnd gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M22 gnd a_13_269# a_31_41# gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M23 a_31_41# a_13_269# gnd gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M24 a_31_451# a_29_269# a_31_41# gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M25 a_31_41# a_29_269# a_31_451# gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M26 a_31_451# a_29_269# a_31_41# gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M27 a_31_41# a_29_269# a_31_451# gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M28 a_200_269# a_191_395# gnd gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M29 gnd a_191_395# a_200_269# gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M30 a_200_269# a_191_395# gnd gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M31 gnd a_191_395# a_200_269# gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M32 a_200_269# a_191_395# gnd gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M33 gnd a_191_395# a_200_269# gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M34 a_248_269# a_200_269# gnd gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M35 gnd a_200_269# a_248_269# gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M36 a_248_269# a_200_269# gnd gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M37 gnd a_200_269# a_248_269# gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M38 a_248_269# a_200_269# gnd gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M39 gnd a_200_269# a_248_269# gnd nfet w=9u l=0.6u + ad=0p pd=0u as=0p ps=0u M40 vdd vdd a_13_269# vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M41 a_29_269# a_13_269# vdd vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M42 vdd DO a_31_451# vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M43 a_31_451# DO vdd vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M44 vdd DO a_31_451# vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M45 a_31_451# DO vdd vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M46 vdd DO a_31_451# vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M47 a_31_451# a_29_269# vdd vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M48 vdd a_29_269# a_31_451# vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M49 a_31_451# a_29_269# vdd vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M50 vdd a_29_269# a_31_451# vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M51 a_31_451# a_29_269# vdd vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M52 a_31_41# a_13_269# a_31_451# vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M53 a_31_451# a_13_269# a_31_41# vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M54 a_31_41# a_13_269# a_31_451# vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M55 a_31_451# a_13_269# a_31_41# vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M56 a_200_269# a_191_395# vdd vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M57 vdd a_191_395# a_200_269# vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M58 a_200_269# a_191_395# vdd vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M59 vdd a_191_395# a_200_269# vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M60 a_200_269# a_191_395# vdd vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M61 vdd a_191_395# a_200_269# vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M62 a_248_269# a_200_269# vdd vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M63 vdd a_200_269# a_248_269# vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M64 a_248_269# a_200_269# vdd vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M65 vdd a_200_269# a_248_269# vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M66 a_248_269# a_200_269# vdd vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M67 vdd a_200_269# a_248_269# vdd pfet w=15.6u l=0.6u + ad=0p pd=0u as=0p ps=0u M68 gnd2 a_31_41# YPAD gnd2 nfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M69 YPAD a_31_41# gnd2 gnd2 nfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M70 gnd2 a_31_41# YPAD gnd2 nfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M71 YPAD a_31_41# gnd2 gnd2 nfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M72 gnd2 a_31_41# YPAD gnd2 nfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M73 YPAD a_31_41# gnd2 gnd2 nfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M74 gnd2 a_31_41# YPAD gnd2 nfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M75 YPAD a_31_41# gnd2 gnd2 nfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M76 gnd2 a_31_41# YPAD gnd2 nfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M77 YPAD a_31_41# gnd2 gnd2 nfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M78 gnd2 a_31_41# YPAD gnd2 nfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u M79 YPAD a_31_41# gnd2 gnd2 nfet w=30u l=0.9u + ad=0p pd=0u as=0p ps=0u R0 YPAD a_191_395# 100 R1 a_191_395# YPAD 100 .ends PADOUT .subckt TBUFX1 vdd gnd EN A Y M0 a_9_6# EN vdd vdd pfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M1 a_26_54# a_9_6# Y vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M2 vdd A a_26_54# vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M3 a_9_6# EN gnd gnd nfet w=3u l=0.6u + ad=0p pd=0u as=0p ps=0u M4 a_26_6# EN Y gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M5 gnd A a_26_6# gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u .ends TBUFX1 .subckt TBUFX2 vdd gnd A EN Y M0 a_9_6# EN vdd vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M1 Y a_9_6# a_18_54# vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M2 a_18_54# a_9_6# Y vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M3 vdd A a_18_54# vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M4 a_18_54# A vdd vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M5 a_9_6# EN gnd gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M6 Y EN a_18_6# gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M7 a_18_6# EN Y gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M8 gnd A a_18_6# gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M9 a_18_6# A gnd gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u .ends TBUFX2 .subckt XNOR2X1 A B gnd vdd Y M0 vdd A a_2_6# vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M1 a_18_54# a_12_41# vdd vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M2 Y a_2_6# a_18_54# vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M3 a_35_54# A Y vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M4 vdd B a_35_54# vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M5 a_12_41# B vdd vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M6 gnd A a_2_6# gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M7 a_18_6# a_12_41# gnd gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M8 Y A a_18_6# gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M9 a_35_6# a_2_6# Y gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M10 gnd B a_35_6# gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M11 a_12_41# B gnd gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u .ends XNOR2X1 .subckt XOR2X1 Y vdd B A gnd M0 vdd A a_2_6# vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M1 a_18_54# a_13_43# vdd vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M2 Y A a_18_54# vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M3 a_35_54# a_2_6# Y vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M4 vdd B a_35_54# vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M5 a_13_43# B vdd vdd pfet w=12u l=0.6u + ad=0p pd=0u as=0p ps=0u M6 gnd A a_2_6# gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M7 a_18_6# a_13_43# gnd gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M8 Y a_2_6# a_18_6# gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M9 a_35_6# A Y gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M10 gnd B a_35_6# gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M11 a_13_43# B gnd gnd nfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u .ends XOR2X1 qflow-1.1.23/tech/osu050/osu05_stdcells.v0000755000175000001440000005651212526236535016500 0ustar timusers`timescale 1ns/10ps `celldefine module AND2X1 (A, B, Y); input A ; input B ; output Y ; and (Y, A, B); specify // delay parameters specparam tpllh$B$Y = 0.14:0.14:0.14, tphhl$B$Y = 0.18:0.18:0.18, tpllh$A$Y = 0.14:0.14:0.14, tphhl$A$Y = 0.17:0.17:0.17; // path delays (A *> Y) = (tpllh$A$Y, tphhl$A$Y); (B *> Y) = (tpllh$B$Y, tphhl$B$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module AND2X2 (A, B, Y); input A ; input B ; output Y ; and (Y, A, B); specify // delay parameters specparam tpllh$A$Y = 0.17:0.17:0.17, tphhl$A$Y = 0.2:0.2:0.2, tpllh$B$Y = 0.17:0.17:0.17, tphhl$B$Y = 0.21:0.21:0.21; // path delays (A *> Y) = (tpllh$A$Y, tphhl$A$Y); (B *> Y) = (tpllh$B$Y, tphhl$B$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module AOI21X1 (A, B, C, Y); input A ; input B ; input C ; output Y ; and (I0_out, A, B); or (I1_out, I0_out, C); not (Y, I1_out); specify // delay parameters specparam tplhl$A$Y = 0.11:0.11:0.11, tphlh$A$Y = 0.12:0.12:0.12, tplhl$B$Y = 0.11:0.11:0.11, tphlh$B$Y = 0.11:0.11:0.11, tplhl$C$Y = 0.11:0.12:0.13, tphlh$C$Y = 0.069:0.085:0.1; // path delays (A *> Y) = (tphlh$A$Y, tplhl$A$Y); (B *> Y) = (tphlh$B$Y, tplhl$B$Y); (C *> Y) = (tphlh$C$Y, tplhl$C$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module AOI22X1 (A, B, C, D, Y); input A ; input B ; input C ; input D ; output Y ; and (I0_out, A, B); and (I1_out, C, D); or (I2_out, I0_out, I1_out); not (Y, I2_out); specify // delay parameters specparam tplhl$C$Y = 0.089:0.095:0.1, tphlh$C$Y = 0.089:0.11:0.13, tplhl$D$Y = 0.089:0.094:0.099, tphlh$D$Y = 0.081:0.098:0.11, tplhl$A$Y = 0.12:0.13:0.15, tphlh$A$Y = 0.12:0.13:0.15, tplhl$B$Y = 0.12:0.13:0.15, tphlh$B$Y = 0.11:0.12:0.13; // path delays (A *> Y) = (tphlh$A$Y, tplhl$A$Y); (B *> Y) = (tphlh$B$Y, tplhl$B$Y); (C *> Y) = (tphlh$C$Y, tplhl$C$Y); (D *> Y) = (tphlh$D$Y, tplhl$D$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module BUFX2 (A, Y); input A ; output Y ; buf (Y, A); specify // delay parameters specparam tpllh$A$Y = 0.19:0.19:0.19, tphhl$A$Y = 0.18:0.18:0.18; // path delays (A *> Y) = (tpllh$A$Y, tphhl$A$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module BUFX4 (A, Y); input A ; output Y ; buf (Y, A); specify // delay parameters specparam tpllh$A$Y = 0.21:0.21:0.21, tphhl$A$Y = 0.2:0.2:0.2; // path delays (A *> Y) = (tpllh$A$Y, tphhl$A$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module CLKBUF1 (A, Y); input A ; output Y ; buf (Y, A); specify // delay parameters specparam tpllh$A$Y = 0.25:0.25:0.25, tphhl$A$Y = 0.26:0.26:0.26; // path delays (A *> Y) = (tpllh$A$Y, tphhl$A$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module CLKBUF2 (A, Y); input A ; output Y ; buf (Y, A); specify // delay parameters specparam tpllh$A$Y = 0.37:0.37:0.37, tphhl$A$Y = 0.38:0.38:0.38; // path delays (A *> Y) = (tpllh$A$Y, tphhl$A$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module CLKBUF3 (A, Y); input A ; output Y ; buf (Y, A); specify // delay parameters specparam tpllh$A$Y = 0.49:0.49:0.49, tphhl$A$Y = 0.5:0.5:0.5; // path delays (A *> Y) = (tpllh$A$Y, tphhl$A$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module DFFNEGX1 (CLK, D, Q); input CLK ; input D ; output Q ; reg NOTIFIER ; not (I0_CLOCK, CLK); udp_dff (DS0000, D, I0_CLOCK, 1'B0, 1'B0, NOTIFIER); not (P0002, DS0000); buf (Q, DS0000); specify // delay parameters specparam tphlh$CLK$Q = 0.27:0.27:0.27, tphhl$CLK$Q = 0.24:0.24:0.24, tminpwh$CLK = 0.077:0.18:0.27, tminpwl$CLK = 0.14:0.2:0.27, tsetup_negedge$D$CLK = 0.38:0.38:0.38, thold_negedge$D$CLK = -0.094:-0.094:-0.094, tsetup_posedge$D$CLK = 0.28:0.28:0.28, thold_posedge$D$CLK = -0.094:-0.094:-0.094; // path delays (CLK *> Q) = (tphlh$CLK$Q, tphhl$CLK$Q); $setup(negedge D, negedge CLK, tsetup_negedge$D$CLK, NOTIFIER); $hold (negedge D, negedge CLK, thold_negedge$D$CLK, NOTIFIER); $setup(posedge D, negedge CLK, tsetup_posedge$D$CLK, NOTIFIER); $hold (posedge D, negedge CLK, thold_posedge$D$CLK, NOTIFIER); $width(posedge CLK, tminpwh$CLK, 0, NOTIFIER); $width(negedge CLK, tminpwl$CLK, 0, NOTIFIER); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module DFFPOSX1 (CLK, D, Q); input CLK ; input D ; output Q ; reg NOTIFIER ; udp_dff (DS0000, D, CLK, 1'B0, 1'B0, NOTIFIER); not (P0002, DS0000); buf (Q, DS0000); specify // delay parameters specparam tpllh$CLK$Q = 0.21:0.21:0.21, tplhl$CLK$Q = 0.3:0.3:0.3, tminpwh$CLK = 0.1:0.2:0.3, tminpwl$CLK = 0.085:0.18:0.27, tsetup_negedge$D$CLK = 0.28:0.28:0.28, thold_negedge$D$CLK = -0.094:-0.094:-0.094, tsetup_posedge$D$CLK = 0.28:0.28:0.28, thold_posedge$D$CLK = -0.094:-0.094:-0.094; // path delays (CLK *> Q) = (tpllh$CLK$Q, tplhl$CLK$Q); $setup(negedge D, posedge CLK, tsetup_negedge$D$CLK, NOTIFIER); $hold (negedge D, posedge CLK, thold_negedge$D$CLK, NOTIFIER); $setup(posedge D, posedge CLK, tsetup_posedge$D$CLK, NOTIFIER); $hold (posedge D, posedge CLK, thold_posedge$D$CLK, NOTIFIER); $width(posedge CLK, tminpwh$CLK, 0, NOTIFIER); $width(negedge CLK, tminpwl$CLK, 0, NOTIFIER); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module DFFSR (CLK, D, R, S, Q); input CLK ; input D ; input R ; input S ; output Q ; reg NOTIFIER ; not (I0_CLEAR, R); not (I0_SET, S); udp_dff (P0003, D_, CLK, I0_SET, I0_CLEAR, NOTIFIER); not (D_, D); not (P0002, P0003); buf (Q, P0002); and (\D&S , D, S); not (I7_out, D); and (\~D&R , I7_out, R); and (\S&R , S, R); specify // delay parameters specparam tphlh$S$Q = 0.46:0.46:0.46, tpllh$R$Q = 0.33:0.33:0.33, tphhl$R$Q = 0.4:0.41:0.41, tpllh$CLK$Q = 0.57:0.57:0.57, tplhl$CLK$Q = 0.65:0.65:0.65, tminpwl$S = 0.064:0.26:0.46, tminpwl$R = 0.043:0.23:0.41, tminpwh$CLK = 0.32:0.49:0.65, tminpwl$CLK = 0.3:0.33:0.37, tsetup_negedge$D$CLK = 0.094:0.094:0.094, thold_negedge$D$CLK = 0.094:0.094:0.094, tsetup_posedge$D$CLK = 0.19:0.19:0.19, thold_posedge$D$CLK = 0.000000062:0.000000062:0.000000062, trec$R$CLK = -0.19:-0.19:-0.19, trem$R$CLK = 0.28:0.28:0.28, trec$R$S = 0.000000062:0.000000062:0.000000062, trec$S$CLK = 0:0:0, trem$S$CLK = 0.19:0.19:0.19, trec$S$R = 0.094:0.094:0.094; // path delays (CLK *> Q) = (tpllh$CLK$Q, tplhl$CLK$Q); (R *> Q) = (tpllh$R$Q, tphhl$R$Q); (S *> Q) = (tphlh$S$Q, 0); $setup(negedge D, posedge CLK &&& \S&R , tsetup_negedge$D$CLK, NOTIFIER); $hold (negedge D, posedge CLK &&& \S&R , thold_negedge$D$CLK, NOTIFIER); $setup(posedge D, posedge CLK &&& \S&R , tsetup_posedge$D$CLK, NOTIFIER); $hold (posedge D, posedge CLK &&& \S&R , thold_posedge$D$CLK, NOTIFIER); $recovery(posedge R, posedge CLK &&& \D&S , trec$R$CLK, NOTIFIER); $removal (posedge R, posedge CLK &&& \D&S , trem$R$CLK, NOTIFIER); $recovery(posedge R, posedge S, trec$R$S, NOTIFIER); $recovery(posedge S, posedge CLK &&& \~D&R , trec$S$CLK, NOTIFIER); $removal (posedge S, posedge CLK &&& \~D&R , trem$S$CLK, NOTIFIER); $recovery(posedge S, posedge R, trec$S$R, NOTIFIER); $width(negedge S, tminpwl$S, 0, NOTIFIER); $width(negedge R, tminpwl$R, 0, NOTIFIER); $width(posedge CLK, tminpwh$CLK, 0, NOTIFIER); $width(negedge CLK, tminpwl$CLK, 0, NOTIFIER); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module FAX1 (A, B, C, YC, YS); input A ; input B ; input C ; output YC ; output YS ; and (I0_out, A, B); and (I1_out, B, C); and (I3_out, C, A); or (YC, I0_out, I1_out, I3_out); xor (I5_out, A, B); xor (YS, I5_out, C); specify // delay parameters specparam tpllh$A$YS = 0.34:0.36:0.38, tplhl$A$YS = 0.38:0.38:0.39, tpllh$A$YC = 0.24:0.24:0.24, tphhl$A$YC = 0.27:0.27:0.27, tpllh$B$YS = 0.35:0.38:0.41, tplhl$B$YS = 0.37:0.4:0.42, tpllh$B$YC = 0.23:0.25:0.28, tphhl$B$YC = 0.28:0.28:0.28, tpllh$C$YS = 0.36:0.38:0.39, tplhl$C$YS = 0.37:0.38:0.38, tpllh$C$YC = 0.22:0.23:0.25, tphhl$C$YC = 0.26:0.26:0.26; // path delays (A *> YC) = (tpllh$A$YC, tphhl$A$YC); (A *> YS) = (tpllh$A$YS, tplhl$A$YS); (B *> YC) = (tpllh$B$YC, tphhl$B$YC); (B *> YS) = (tpllh$B$YS, tplhl$B$YS); (C *> YC) = (tpllh$C$YC, tphhl$C$YC); (C *> YS) = (tpllh$C$YS, tplhl$C$YS); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module HAX1 (A, B, YC, YS); input A ; input B ; output YC ; output YS ; and (YC, A, B); xor (YS, A, B); specify // delay parameters specparam tpllh$A$YS = 0.27:0.27:0.27, tplhl$A$YS = 0.32:0.32:0.32, tpllh$A$YC = 0.18:0.18:0.18, tphhl$A$YC = 0.23:0.23:0.23, tpllh$B$YS = 0.27:0.27:0.27, tplhl$B$YS = 0.31:0.31:0.31, tpllh$B$YC = 0.17:0.17:0.17, tphhl$B$YC = 0.22:0.22:0.22; // path delays (A *> YC) = (tpllh$A$YC, tphhl$A$YC); (A *> YS) = (tpllh$A$YS, tplhl$A$YS); (B *> YC) = (tpllh$B$YC, tphhl$B$YC); (B *> YS) = (tpllh$B$YS, tplhl$B$YS); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module INVX1 (A, Y); input A ; output Y ; not (Y, A); specify // delay parameters specparam tplhl$A$Y = 0.091:0.091:0.091, tphlh$A$Y = 0.081:0.081:0.081; // path delays (A *> Y) = (tphlh$A$Y, tplhl$A$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module INVX2 (A, Y); input A ; output Y ; not (Y, A); specify // delay parameters specparam tplhl$A$Y = 0.083:0.083:0.083, tphlh$A$Y = 0.079:0.079:0.079; // path delays (A *> Y) = (tphlh$A$Y, tplhl$A$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module INVX4 (A, Y); input A ; output Y ; not (Y, A); specify // delay parameters specparam tplhl$A$Y = 0.083:0.083:0.083, tphlh$A$Y = 0.079:0.079:0.079; // path delays (A *> Y) = (tphlh$A$Y, tplhl$A$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module INVX8 (A, Y); input A ; output Y ; not (Y, A); specify // delay parameters specparam tplhl$A$Y = 0.083:0.083:0.083, tphlh$A$Y = 0.079:0.079:0.079; // path delays (A *> Y) = (tphlh$A$Y, tplhl$A$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module LATCH (CLK, D, Q); input CLK ; input D ; output Q ; reg NOTIFIER ; udp_tlat (DS0000, D, CLK, 1'B0, 1'B0, NOTIFIER); not (P0000, DS0000); buf (Q, DS0000); specify // delay parameters specparam tpllh$D$Q = 0.35:0.35:0.35, tphhl$D$Q = 0.37:0.37:0.37, tpllh$CLK$Q = 0.29:0.29:0.29, tplhl$CLK$Q = 0.38:0.38:0.38, tminpwh$CLK = 0.1:0.24:0.38, tsetup_negedge$D$CLK = 0.28:0.28:0.28, thold_negedge$D$CLK = -0.094:-0.094:-0.094, tsetup_posedge$D$CLK = 0.38:0.38:0.38, thold_posedge$D$CLK = -0.19:-0.19:-0.19; // path delays (CLK *> Q) = (tpllh$CLK$Q, tplhl$CLK$Q); (D *> Q) = (tpllh$D$Q, tphhl$D$Q); $setup(negedge D, negedge CLK, tsetup_negedge$D$CLK, NOTIFIER); $hold (negedge D, negedge CLK, thold_negedge$D$CLK, NOTIFIER); $setup(posedge D, negedge CLK, tsetup_posedge$D$CLK, NOTIFIER); $hold (posedge D, negedge CLK, thold_posedge$D$CLK, NOTIFIER); $width(posedge CLK, tminpwh$CLK, 0, NOTIFIER); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module MUX2X1 (A, B, S, Y); input A ; input B ; input S ; output Y ; udp_mux2 (I0_out, B, A, S); not (Y, I0_out); specify // delay parameters specparam tpllh$S$Y = 0.21:0.21:0.21, tplhl$S$Y = 0.2:0.2:0.2, tplhl$A$Y = 0.11:0.11:0.11, tphlh$A$Y = 0.13:0.13:0.13, tplhl$B$Y = 0.12:0.12:0.12, tphlh$B$Y = 0.12:0.12:0.12; // path delays (A *> Y) = (tphlh$A$Y, tplhl$A$Y); (B *> Y) = (tphlh$B$Y, tplhl$B$Y); (S *> Y) = (tpllh$S$Y, tplhl$S$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module NAND2X1 (A, B, Y); input A ; input B ; output Y ; and (I0_out, A, B); not (Y, I0_out); specify // delay parameters specparam tplhl$A$Y = 0.071:0.071:0.071, tphlh$A$Y = 0.1:0.1:0.1, tplhl$B$Y = 0.072:0.072:0.072, tphlh$B$Y = 0.092:0.092:0.092; // path delays (A *> Y) = (tphlh$A$Y, tplhl$A$Y); (B *> Y) = (tphlh$B$Y, tplhl$B$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module NAND3X1 (A, B, C, Y); input A ; input B ; input C ; output Y ; and (I1_out, A, B, C); not (Y, I1_out); specify // delay parameters specparam tplhl$B$Y = 0.076:0.076:0.076, tphlh$B$Y = 0.13:0.13:0.13, tplhl$A$Y = 0.078:0.078:0.078, tphlh$A$Y = 0.15:0.15:0.15, tplhl$C$Y = 0.065:0.065:0.065, tphlh$C$Y = 0.1:0.1:0.1; // path delays (A *> Y) = (tphlh$A$Y, tplhl$A$Y); (B *> Y) = (tphlh$B$Y, tplhl$B$Y); (C *> Y) = (tphlh$C$Y, tplhl$C$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module NOR2X1 (A, B, Y); input A ; input B ; output Y ; or (I0_out, A, B); not (Y, I0_out); specify // delay parameters specparam tplhl$B$Y = 0.12:0.12:0.12, tphlh$B$Y = 0.086:0.086:0.086, tplhl$A$Y = 0.15:0.15:0.15, tphlh$A$Y = 0.093:0.093:0.093; // path delays (A *> Y) = (tphlh$A$Y, tplhl$A$Y); (B *> Y) = (tphlh$B$Y, tplhl$B$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module NOR3X1 (A, B, C, Y); input A ; input B ; input C ; output Y ; or (I1_out, A, B, C); not (Y, I1_out); specify // delay parameters specparam tplhl$B$Y = 0.2:0.2:0.2, tphlh$B$Y = 0.12:0.12:0.12, tplhl$C$Y = 0.14:0.14:0.14, tphlh$C$Y = 0.086:0.086:0.086, tplhl$A$Y = 0.24:0.24:0.24, tphlh$A$Y = 0.13:0.13:0.13; // path delays (A *> Y) = (tphlh$A$Y, tplhl$A$Y); (B *> Y) = (tphlh$B$Y, tplhl$B$Y); (C *> Y) = (tphlh$C$Y, tplhl$C$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module OAI21X1 (A, B, C, Y); input A ; input B ; input C ; output Y ; or (I0_out, A, B); and (I1_out, I0_out, C); not (Y, I1_out); specify // delay parameters specparam tplhl$A$Y = 0.11:0.11:0.11, tphlh$A$Y = 0.12:0.12:0.12, tplhl$B$Y = 0.089:0.089:0.089, tphlh$B$Y = 0.11:0.11:0.11, tplhl$C$Y = 0.063:0.082:0.1, tphlh$C$Y = 0.094:0.099:0.1; // path delays (A *> Y) = (tphlh$A$Y, tplhl$A$Y); (B *> Y) = (tphlh$B$Y, tplhl$B$Y); (C *> Y) = (tphlh$C$Y, tplhl$C$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module OAI22X1 (A, B, C, D, Y); input A ; input B ; input C ; input D ; output Y ; or (I0_out, A, B); or (I1_out, C, D); and (I2_out, I0_out, I1_out); not (Y, I2_out); specify // delay parameters specparam tplhl$D$Y = 0.078:0.1:0.12, tphlh$D$Y = 0.097:0.1:0.11, tplhl$C$Y = 0.094:0.12:0.14, tphlh$C$Y = 0.11:0.11:0.12, tplhl$A$Y = 0.1:0.12:0.15, tphlh$A$Y = 0.13:0.13:0.14, tplhl$B$Y = 0.083:0.1:0.13, tphlh$B$Y = 0.11:0.12:0.13; // path delays (A *> Y) = (tphlh$A$Y, tplhl$A$Y); (B *> Y) = (tphlh$B$Y, tplhl$B$Y); (C *> Y) = (tphlh$C$Y, tplhl$C$Y); (D *> Y) = (tphlh$D$Y, tplhl$D$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module OR2X1 (A, B, Y); input A ; input B ; output Y ; or (Y, A, B); specify // delay parameters specparam tpllh$B$Y = 0.22:0.22:0.22, tphhl$B$Y = 0.18:0.18:0.18, tpllh$A$Y = 0.17:0.17:0.17, tphhl$A$Y = 0.17:0.17:0.17; // path delays (A *> Y) = (tpllh$A$Y, tphhl$A$Y); (B *> Y) = (tpllh$B$Y, tphhl$B$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module OR2X2 (A, B, Y); input A ; input B ; output Y ; or (Y, A, B); specify // delay parameters specparam tpllh$B$Y = 0.26:0.26:0.26, tphhl$B$Y = 0.2:0.2:0.2, tpllh$A$Y = 0.22:0.22:0.22, tphhl$A$Y = 0.19:0.19:0.19; // path delays (A *> Y) = (tpllh$A$Y, tphhl$A$Y); (B *> Y) = (tpllh$B$Y, tphhl$B$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module PADINC (YPAD, DI); input YPAD ; output DI ; buf (DI, YPAD); specify // delay parameters specparam tpllh$YPAD$DI = 0.11:0.11:0.11, tphhl$YPAD$DI = 0.12:0.12:0.12; // path delays (YPAD *> DI) = (tpllh$YPAD$DI, tphhl$YPAD$DI); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module PADINOUT (DO, OEN, DI, YPAD); input DO ; input OEN ; output DI ; inout YPAD ; bufif1 (YPAD, DO, OEN); buf (DI, YPAD); specify // delay parameters specparam tpllh$DO$YPAD = 0.69:0.69:0.69, tphhl$DO$YPAD = 0.5:0.5:0.5, tpzh$OEN$YPAD = 0.86:0.86:0.86, tpzl$OEN$YPAD = 0.56:0.56:0.56, tplz$OEN$YPAD = 0.49:0.49:0.49, tphz$OEN$YPAD = 0.62:0.62:0.62, tpllh$YPAD$DI = 0.11:0.11:0.11, tphhl$YPAD$DI = 0.12:0.12:0.12; // path delays (DO *> YPAD) = (tpllh$DO$YPAD, tphhl$DO$YPAD); (OEN *> YPAD) = (0, 0, tplz$OEN$YPAD, tpzh$OEN$YPAD, tphz$OEN$YPAD, tpzl$OEN$YPAD); (YPAD *> DI) = (tpllh$YPAD$DI, tphhl$YPAD$DI); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module PADOUT (DO, YPAD); input DO ; output YPAD ; buf (YPAD, DO); specify // delay parameters specparam tpllh$DO$YPAD = 0.69:0.69:0.69, tphhl$DO$YPAD = 0.5:0.5:0.5; // path delays (DO *> YPAD) = (tpllh$DO$YPAD, tphhl$DO$YPAD); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module TBUFX1 (A, EN, Y); input A ; input EN ; output Y ; not (I0_out, A); bufif1 (Y, I0_out, EN); specify // delay parameters specparam tpzh$EN$Y = 0.14:0.14:0.14, tpzl$EN$Y = 0.053:0.053:0.053, tplz$EN$Y = 0.056:0.056:0.056, tphz$EN$Y = 0.11:0.11:0.11, tplhl$A$Y = 0.098:0.098:0.098, tphlh$A$Y = 0.12:0.12:0.12; // path delays (A *> Y) = (tphlh$A$Y, tplhl$A$Y); (EN *> Y) = (0, 0, tplz$EN$Y, tpzh$EN$Y, tphz$EN$Y, tpzl$EN$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module TBUFX2 (A, EN, Y); input A ; input EN ; output Y ; not (I0_out, A); bufif1 (Y, I0_out, EN); specify // delay parameters specparam tplhl$A$Y = 0.099:0.099:0.099, tphlh$A$Y = 0.12:0.12:0.12, tpzh$EN$Y = 0.13:0.13:0.13, tpzl$EN$Y = 0.052:0.052:0.052, tplz$EN$Y = 0.056:0.056:0.056, tphz$EN$Y = 0.1:0.1:0.1; // path delays (A *> Y) = (tphlh$A$Y, tplhl$A$Y); (EN *> Y) = (0, 0, tplz$EN$Y, tpzh$EN$Y, tphz$EN$Y, tpzl$EN$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module XNOR2X1 (A, B, Y); input A ; input B ; output Y ; xor (I0_out, A, B); not (Y, I0_out); specify // delay parameters specparam tpllh$A$Y = 0.16:0.16:0.16, tplhl$A$Y = 0.15:0.15:0.15, tpllh$B$Y = 0.18:0.18:0.18, tplhl$B$Y = 0.17:0.17:0.17; // path delays (A *> Y) = (tpllh$A$Y, tplhl$A$Y); (B *> Y) = (tpllh$B$Y, tplhl$B$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module XOR2X1 (A, B, Y); input A ; input B ; output Y ; xor (Y, A, B); specify // delay parameters specparam tpllh$B$Y = 0.18:0.18:0.18, tplhl$B$Y = 0.18:0.18:0.18, tpllh$A$Y = 0.16:0.16:0.16, tplhl$A$Y = 0.15:0.15:0.15; // path delays (A *> Y) = (tpllh$A$Y, tplhl$A$Y); (B *> Y) = (tpllh$B$Y, tplhl$B$Y); endspecify endmodule `endcelldefine primitive udp_dff (out, in, clk, clr, set, NOTIFIER); output out; input in, clk, clr, set, NOTIFIER; reg out; table // in clk clr set NOT : Qt : Qt+1 // 0 r ? 0 ? : ? : 0 ; // clock in 0 1 r 0 ? ? : ? : 1 ; // clock in 1 1 * 0 ? ? : 1 : 1 ; // reduce pessimism 0 * ? 0 ? : 0 : 0 ; // reduce pessimism ? f ? ? ? : ? : - ; // no changes on negedge clk * b ? ? ? : ? : - ; // no changes when in switches ? ? ? 1 ? : ? : 1 ; // set output ? b 0 * ? : 1 : 1 ; // cover all transistions on set 1 x 0 * ? : 1 : 1 ; // cover all transistions on set ? ? 1 0 ? : ? : 0 ; // reset output ? b * 0 ? : 0 : 0 ; // cover all transistions on clr 0 x * 0 ? : 0 : 0 ; // cover all transistions on clr ? ? ? ? * : ? : x ; // any notifier changed endtable endprimitive // udp_dff primitive udp_tlat (out, in, enable, clr, set, NOTIFIER); output out; input in, enable, clr, set, NOTIFIER; reg out; table // in enable clr set NOT : Qt : Qt+1 // 1 1 0 ? ? : ? : 1 ; // 0 1 ? 0 ? : ? : 0 ; // 1 * 0 ? ? : 1 : 1 ; // reduce pessimism 0 * ? 0 ? : 0 : 0 ; // reduce pessimism * 0 ? ? ? : ? : - ; // no changes when in switches ? ? ? 1 ? : ? : 1 ; // set output ? 0 0 * ? : 1 : 1 ; // cover all transistions on set 1 ? 0 * ? : 1 : 1 ; // cover all transistions on set ? ? 1 0 ? : ? : 0 ; // reset output ? 0 * 0 ? : 0 : 0 ; // cover all transistions on clr 0 ? * 0 ? : 0 : 0 ; // cover all transistions on clr ? ? ? ? * : ? : x ; // any notifier changed endtable endprimitive // udp_tlat primitive udp_rslat (out, clr, set, NOTIFIER); output out; input clr, set, NOTIFIER; reg out; table // clr set NOT : Qt : Qt+1 // ? 1 ? : ? : 1 ; // set output 0 * ? : 1 : 1 ; // cover all transistions on set 1 0 ? : ? : 0 ; // reset output * 0 ? : 0 : 0 ; // cover all transistions on clr ? ? * : ? : x ; // any notifier changed endtable endprimitive // udp_tlat primitive udp_mux2 (out, in0, in1, sel); output out; input in0, in1, sel; table // in0 in1 sel : out // 1 ? 0 : 1 ; 0 ? 0 : 0 ; ? 1 1 : 1 ; ? 0 1 : 0 ; 0 0 x : 0 ; 1 1 x : 1 ; endtable endprimitive // udp_mux2 module PADNC(); endmodule module PADFC(); endmodule module PADGND(); endmodule module PADVDD(); endmodule qflow-1.1.23/tech/Makefile.in0000664000175000001440000000135412535603240014433 0ustar timusers# # qflow project tech makefile # # Main compiler arguments CFLAGS = @CFLAGS@ DEFS = @DEFS@ LIBS = @LIBS@ LDFLAGS = @LDFLAGS@ INSTALL = @INSTALL@ QFLOW_LIB_DIR = @QFLOW_LIB_DIR@ TECH_DIRS = osu050 osu035 osu018 TECHINSTALL = ${QFLOW_LIB_DIR}/tech all: @echo "Making all in tech directories" for target in $(TECH_DIRS); do \ (cd $$target ; $(MAKE) all) ;\ done install: @echo "Installing built-in tech files" $(INSTALL) -d $(DESTDIR)${TECHINSTALL} for target in $(TECH_DIRS); do \ (cd $$target ; $(MAKE) install) ;\ done clean: @echo "Cleaning up built-in tech files" for target in $(TECH_DIRS); do \ (cd $$target ; $(MAKE) clean) ;\ done uninstall: @echo "Uninstalling built-in tech files $(RM) -rf ${TECHINSTALL} qflow-1.1.23/tech/osu018/0000775000175000001440000000000012535603557013435 5ustar timusersqflow-1.1.23/tech/osu018/osu018_stdcells.lef0000775000175000001440000021174212535603557017073 0ustar timusers# LEF file generated by Abstract Generator version 5.5.10 on Jul 28 14:07:14 2004 # # Contains LEF for all bins. # Options: [x] Antenna # [x] Geometry # [x] Technology VERSION 5.4 ; NAMESCASESENSITIVE ON ; BUSBITCHARS "[]" ; DIVIDERCHAR "/" ; UNITS DATABASE MICRONS 1000 ; END UNITS USEMINSPACING OBS ON ; USEMINSPACING PIN OFF ; CLEARANCEMEASURE EUCLIDEAN ; MANUFACTURINGGRID 0.05 ; LAYER nwell TYPE MASTERSLICE ; END nwell LAYER nactive TYPE MASTERSLICE ; END nactive LAYER pactive TYPE MASTERSLICE ; END pactive LAYER poly TYPE MASTERSLICE ; END poly LAYER cc TYPE CUT ; SPACING 0.45 ; END cc LAYER metal1 TYPE ROUTING ; DIRECTION HORIZONTAL ; PITCH 1 ; OFFSET 0.5 ; WIDTH 0.3 ; SPACING 0.3 ; RESISTANCE RPERSQ 0.08 ; CAPACITANCE CPERSQDIST 3.8e-05 ; EDGECAPACITANCE 8.000000e-05 ; END metal1 LAYER via TYPE CUT ; SPACING 0.3 ; END via LAYER metal2 TYPE ROUTING ; DIRECTION VERTICAL ; PITCH 0.8 ; OFFSET 0.4 ; WIDTH 0.3 ; SPACING 0.3 ; RESISTANCE RPERSQ 0.08 ; CAPACITANCE CPERSQDIST 1.9e-05 ; EDGECAPACITANCE 6.000000e-05 ; END metal2 LAYER via2 TYPE CUT ; SPACING 0.3 ; END via2 LAYER metal3 TYPE ROUTING ; DIRECTION HORIZONTAL ; PITCH 1 ; OFFSET 0.5 ; WIDTH 0.3 ; SPACING 0.3 ; RESISTANCE RPERSQ 0.08 ; CAPACITANCE CPERSQDIST 1.3e-05 ; EDGECAPACITANCE 5.400000e-05 ; END metal3 LAYER via3 TYPE CUT ; SPACING 0.4 ; END via3 LAYER metal4 TYPE ROUTING ; DIRECTION VERTICAL ; PITCH 0.8 ; OFFSET 0.4 ; WIDTH 0.3 ; SPACING 0.3 ; RESISTANCE RPERSQ 0.07 ; CAPACITANCE CPERSQDIST 8e-06 ; EDGECAPACITANCE 4.100000e-05 ; END metal4 LAYER via4 TYPE CUT ; SPACING 0.3 ; END via4 LAYER metal5 TYPE ROUTING ; DIRECTION HORIZONTAL ; PITCH 1 ; OFFSET 0.5 ; WIDTH 0.3 ; SPACING 0.3 ; RESISTANCE RPERSQ 0.07 ; CAPACITANCE CPERSQDIST 8e-06 ; EDGECAPACITANCE 2.400000e-05 ; END metal5 LAYER via5 TYPE CUT ; SPACING 0.4 ; END via5 LAYER metal6 TYPE ROUTING ; DIRECTION VERTICAL ; PITCH 1.6 ; OFFSET 0.8 ; WIDTH 0.5 ; SPACING 0.5 ; RESISTANCE RPERSQ 0.03 ; CAPACITANCE CPERSQDIST 3e-06 ; EDGECAPACITANCE 2.000000e-05 ; END metal6 VIA M2_M1 DEFAULT LAYER metal1 ; RECT -0.200 -0.200 0.200 0.200 ; LAYER via ; RECT -0.100 -0.100 0.100 0.100 ; LAYER metal2 ; RECT -0.200 -0.200 0.200 0.200 ; END M2_M1 VIA M3_M2 DEFAULT LAYER metal2 ; RECT -0.200 -0.200 0.200 0.200 ; LAYER via2 ; RECT -0.100 -0.100 0.100 0.100 ; LAYER metal3 ; RECT -0.200 -0.200 0.200 0.200 ; END M3_M2 VIA M4_M3 DEFAULT LAYER metal3 ; RECT -0.200 -0.200 0.200 0.200 ; LAYER via3 ; RECT -0.100 -0.100 0.100 0.100 ; LAYER metal4 ; RECT -0.200 -0.200 0.200 0.200 ; END M4_M3 VIA M5_M4 DEFAULT LAYER metal4 ; RECT -0.200 -0.200 0.200 0.200 ; LAYER via4 ; RECT -0.100 -0.100 0.100 0.100 ; LAYER metal5 ; RECT -0.200 -0.200 0.200 0.200 ; END M5_M4 VIA M6_M5 DEFAULT LAYER metal5 ; RECT -0.250 -0.250 0.250 0.250 ; LAYER via5 ; RECT -0.150 -0.150 0.150 0.150 ; LAYER metal6 ; RECT -0.250 -0.250 0.250 0.250 ; END M6_M5 VIARULE viagen21 GENERATE LAYER metal1 ; DIRECTION HORIZONTAL ; WIDTH 0.3 TO 60 ; OVERHANG 0.1 ; METALOVERHANG 0 ; LAYER metal2 ; DIRECTION VERTICAL ; WIDTH 0.3 TO 60 ; OVERHANG 0.1 ; METALOVERHANG 0 ; LAYER via ; RECT -0.1 -0.1 0.1 0.1 ; SPACING 0.5 BY 0.5 ; END viagen21 VIARULE viagen32 GENERATE LAYER metal3 ; DIRECTION HORIZONTAL ; WIDTH 0.3 TO 60 ; OVERHANG 0.1 ; METALOVERHANG 0 ; LAYER metal2 ; DIRECTION VERTICAL ; WIDTH 0.3 TO 60 ; OVERHANG 0.1 ; METALOVERHANG 0 ; LAYER via2 ; RECT -0.1 -0.1 0.1 0.1 ; SPACING 0.5 BY 0.5 ; END viagen32 VIARULE viagen43 GENERATE LAYER metal3 ; DIRECTION HORIZONTAL ; WIDTH 0.3 TO 60 ; OVERHANG 0.1 ; METALOVERHANG 0 ; LAYER metal4 ; DIRECTION VERTICAL ; WIDTH 0.3 TO 60 ; OVERHANG 0.1 ; METALOVERHANG 0 ; LAYER via3 ; RECT -0.1 -0.1 0.1 0.1 ; SPACING 0.6 BY 0.6 ; END viagen43 VIARULE viagen54 GENERATE LAYER metal5 ; DIRECTION HORIZONTAL ; WIDTH 0.3 TO 60 ; OVERHANG 0.1 ; METALOVERHANG 0 ; LAYER metal4 ; DIRECTION VERTICAL ; WIDTH 0.3 TO 60 ; OVERHANG 0.1 ; METALOVERHANG 0 ; LAYER via4 ; RECT -0.1 -0.1 0.1 0.1 ; SPACING 0.5 BY 0.5 ; END viagen54 VIARULE viagen65 GENERATE LAYER metal5 ; DIRECTION HORIZONTAL ; WIDTH 0.5 TO 60 ; OVERHANG 0.1 ; METALOVERHANG 0 ; LAYER metal6 ; DIRECTION VERTICAL ; WIDTH 0.5 TO 60 ; OVERHANG 0.1 ; METALOVERHANG 0 ; LAYER via5 ; RECT -0.15 -0.15 0.15 0.15 ; SPACING 0.7 BY 0.7 ; END viagen65 VIARULE TURN1 GENERATE LAYER metal1 ; DIRECTION HORIZONTAL ; LAYER metal1 ; DIRECTION VERTICAL ; END TURN1 VIARULE TURN2 GENERATE LAYER metal2 ; DIRECTION HORIZONTAL ; LAYER metal2 ; DIRECTION VERTICAL ; END TURN2 VIARULE TURN3 GENERATE LAYER metal3 ; DIRECTION HORIZONTAL ; LAYER metal3 ; DIRECTION VERTICAL ; END TURN3 VIARULE TURN4 GENERATE LAYER metal4 ; DIRECTION HORIZONTAL ; LAYER metal4 ; DIRECTION VERTICAL ; END TURN4 VIARULE TURN5 GENERATE LAYER metal5 ; DIRECTION HORIZONTAL ; LAYER metal5 ; DIRECTION VERTICAL ; END TURN5 VIARULE TURN6 GENERATE LAYER metal6 ; DIRECTION HORIZONTAL ; LAYER metal6 ; DIRECTION VERTICAL ; END TURN6 SITE core CLASS CORE ; SYMMETRY Y ; SIZE 0.800 BY 10.000 ; END core MACRO FILL CLASS CORE ; FOREIGN FILL 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 0.800 BY 10.000 ; SYMMETRY X Y ; SITE core ; PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.200 -0.300 1.000 0.300 ; END END gnd PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.200 9.700 1.000 10.300 ; END END vdd END FILL MACRO AND2X1 CLASS CORE ; FOREIGN AND2X1 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 3.200 BY 10.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.200 3.300 0.600 4.100 ; END END A PIN B DIRECTION INPUT ; PORT LAYER metal1 ; RECT 1.300 4.900 1.700 5.700 ; RECT 1.000 5.300 1.700 5.700 ; END END B PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 1.500 -0.300 1.900 2.600 ; RECT -0.200 -0.300 3.400 0.300 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 2.600 6.300 3.000 6.700 ; RECT 2.600 7.400 3.000 9.400 ; RECT 2.700 1.600 3.000 9.400 ; RECT 2.300 0.600 2.700 1.900 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.200 7.400 0.600 10.300 ; RECT -0.200 9.700 3.400 10.300 ; RECT 1.800 7.400 2.200 10.300 ; END END vdd OBS LAYER metal1 ; RECT 0.200 0.600 0.600 2.600 ; RECT 0.300 2.600 1.200 2.900 ; RECT 0.900 2.600 1.200 3.300 ; RECT 2.000 2.900 2.400 3.300 ; RECT 0.900 3.000 2.400 3.300 ; RECT 2.000 2.900 2.300 7.100 ; RECT 1.100 6.800 2.300 7.100 ; RECT 1.100 6.800 1.400 9.400 ; RECT 1.000 7.400 1.400 9.400 ; END END AND2X1 MACRO AND2X2 CLASS CORE ; FOREIGN AND2X2 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 3.200 BY 10.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.200 3.300 0.600 4.100 ; END END A PIN B DIRECTION INPUT ; PORT LAYER metal1 ; RECT 1.100 3.600 1.400 4.700 ; RECT 1.200 3.500 1.600 3.900 ; RECT 1.000 4.300 1.400 4.700 ; END END B PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 1.500 -0.300 1.900 2.500 ; RECT -0.200 -0.300 3.400 0.300 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 2.600 4.300 3.000 4.700 ; RECT 2.600 5.400 3.000 9.400 ; RECT 2.700 2.100 3.000 9.400 ; RECT 2.300 0.600 2.700 2.600 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.200 7.400 0.600 10.300 ; RECT -0.200 9.700 3.400 10.300 ; RECT 1.800 5.600 2.200 10.300 ; END END vdd OBS LAYER metal1 ; RECT 0.200 0.600 0.600 2.600 ; RECT 0.300 0.600 0.600 3.000 ; RECT 0.300 2.700 1.200 3.000 ; RECT 0.900 2.900 2.400 3.200 ; RECT 2.000 2.900 2.400 3.300 ; RECT 2.000 2.900 2.300 5.300 ; RECT 1.100 5.000 2.300 5.300 ; RECT 1.100 5.000 1.400 9.400 ; RECT 1.000 7.400 1.400 9.400 ; END END AND2X2 MACRO AOI21X1 CLASS CORE ; FOREIGN AOI21X1 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 3.200 BY 10.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.200 4.300 0.600 4.700 ; RECT 0.600 4.400 1.000 4.900 ; END END A PIN B DIRECTION INPUT ; PORT LAYER metal1 ; RECT 1.000 3.300 1.400 4.100 ; END END B PIN C DIRECTION INPUT ; PORT LAYER metal1 ; RECT 2.500 1.900 2.900 2.300 ; RECT 2.600 2.300 3.000 2.700 ; END END C PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.500 -0.300 0.900 2.600 ; RECT -0.200 -0.300 3.400 0.300 ; RECT 2.600 -0.300 3.000 1.600 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 1.800 0.600 2.100 4.700 ; RECT 2.600 5.400 3.000 9.400 ; RECT 1.800 4.400 3.000 4.700 ; RECT 2.600 4.300 3.000 4.700 ; RECT 2.600 4.300 2.900 9.400 ; RECT 1.800 0.600 2.200 2.600 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 1.000 6.000 1.400 10.300 ; RECT -0.200 9.700 3.400 10.300 ; END END vdd OBS LAYER metal1 ; RECT 0.200 5.400 2.200 5.700 ; RECT 0.200 5.400 0.600 9.400 ; RECT 1.800 5.400 2.200 9.400 ; END END AOI21X1 MACRO AOI22X1 CLASS CORE ; FOREIGN AOI22X1 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 4.000 BY 10.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.200 4.300 0.600 4.700 ; RECT 0.600 4.400 1.000 4.900 ; END END A PIN B DIRECTION INPUT ; PORT LAYER metal1 ; RECT 1.000 3.300 1.400 4.100 ; END END B PIN C DIRECTION INPUT ; PORT LAYER metal1 ; RECT 3.400 4.300 3.800 5.100 ; END END C PIN D DIRECTION INPUT ; PORT LAYER metal1 ; RECT 2.600 3.300 2.900 4.300 ; RECT 2.600 3.300 3.000 3.700 ; RECT 2.500 3.900 2.900 4.300 ; END END D PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.400 -0.300 0.800 2.600 ; RECT -0.200 -0.300 4.200 0.300 ; RECT 3.400 -0.300 3.800 2.600 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 1.800 4.300 2.200 4.700 ; RECT 2.600 5.400 3.000 8.800 ; RECT 2.600 4.800 2.900 8.800 ; RECT 1.900 4.800 2.900 5.100 ; RECT 1.700 0.600 2.500 2.600 ; RECT 1.900 0.600 2.200 5.100 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 1.000 6.000 1.400 10.300 ; RECT -0.200 9.700 4.200 10.300 ; END END vdd OBS LAYER metal1 ; RECT 0.200 5.400 2.200 5.700 ; RECT 1.800 5.400 2.200 9.400 ; RECT 0.200 5.400 0.600 9.400 ; RECT 3.400 5.400 3.800 9.400 ; RECT 1.800 9.100 3.800 9.400 ; END END AOI22X1 MACRO BUFX2 CLASS CORE ; FOREIGN BUFX2 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 2.400 BY 10.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.200 3.900 0.600 4.700 ; END END A PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 1.000 -0.300 1.400 2.600 ; RECT -0.200 -0.300 2.600 0.300 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 1.800 0.600 2.200 4.300 ; RECT 1.800 5.400 2.200 9.400 ; RECT 1.900 0.600 2.200 9.400 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 1.000 6.000 1.400 10.300 ; RECT -0.200 9.700 2.600 10.300 ; END END vdd OBS LAYER metal1 ; RECT 0.200 0.600 0.600 3.200 ; RECT 0.200 2.900 1.300 3.200 ; RECT 1.000 4.700 1.600 5.100 ; RECT 1.000 2.900 1.300 5.700 ; RECT 0.200 5.400 1.300 5.700 ; RECT 0.200 5.400 0.600 9.400 ; END END BUFX2 MACRO BUFX4 CLASS CORE ; FOREIGN BUFX4 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 3.200 BY 10.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.300 3.900 0.700 4.700 ; RECT 0.200 4.300 0.700 4.700 ; END END A PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 1.000 -0.300 1.400 2.600 ; RECT -0.200 -0.300 3.400 0.300 ; RECT 2.600 -0.300 3.000 2.600 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 1.800 0.600 2.200 2.600 ; RECT 2.000 2.300 2.300 5.900 ; RECT 1.800 5.400 2.200 9.400 ; RECT 1.800 3.300 2.300 3.700 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 1.000 6.000 1.400 10.300 ; RECT -0.200 9.700 3.400 10.300 ; RECT 2.600 5.400 3.000 10.300 ; END END vdd OBS LAYER metal1 ; RECT 0.200 0.600 0.600 3.200 ; RECT 0.200 2.900 1.500 3.200 ; RECT 1.200 4.000 1.700 4.400 ; RECT 1.200 2.900 1.500 5.700 ; RECT 0.200 5.400 1.500 5.700 ; RECT 0.200 5.400 0.600 9.400 ; END END BUFX4 MACRO DFFNEGX1 CLASS CORE ; FOREIGN DFFNEGX1 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 9.600 BY 10.000 ; SYMMETRY X Y ; SITE core ; PIN Q DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 7.300 4.700 7.700 5.100 ; RECT 9.000 0.600 9.400 9.400 ; RECT 7.300 4.800 9.400 5.100 ; RECT 7.500 2.800 9.400 3.100 ; RECT 7.500 2.700 7.900 3.100 ; END END Q PIN CLK DIRECTION INPUT ; USE CLOCK ; PORT LAYER metal2 ; RECT 2.600 3.400 3.000 6.700 ; LAYER via ; RECT 2.700 6.400 2.900 6.600 ; RECT 2.700 3.500 2.900 3.700 ; LAYER metal1 ; RECT 2.600 6.300 3.000 6.700 ; RECT 0.600 3.400 6.400 3.700 ; RECT 6.000 3.300 6.400 3.700 ; RECT 2.600 3.400 3.000 3.800 ; RECT 2.100 2.300 2.500 2.700 ; RECT 2.000 2.700 2.400 3.700 ; RECT 0.600 3.300 1.400 3.700 ; RECT 2.700 6.700 3.100 7.100 ; END END CLK PIN D DIRECTION INPUT ; PORT LAYER metal1 ; RECT 1.400 4.200 1.800 4.600 ; RECT 3.400 4.300 3.800 4.700 ; RECT 1.400 4.300 3.800 4.600 ; END END D PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 1.000 -0.300 1.400 2.600 ; RECT -0.200 -0.300 9.800 0.300 ; RECT 8.200 -0.300 8.600 2.500 ; RECT 5.400 -0.300 5.800 1.600 ; RECT 3.700 -0.300 4.200 1.600 ; END END gnd PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 1.000 5.500 1.400 10.300 ; RECT -0.200 9.700 9.800 10.300 ; RECT 8.200 5.400 8.600 10.300 ; RECT 5.400 7.400 5.800 10.300 ; RECT 3.800 7.400 4.200 10.300 ; END END vdd OBS LAYER metal2 ; RECT 0.200 2.600 0.600 5.400 ; RECT 1.800 1.600 2.200 5.000 ; RECT 1.800 1.600 2.100 7.400 ; RECT 1.800 5.400 2.200 7.400 ; RECT 6.600 1.600 7.000 5.700 ; RECT 6.600 1.600 6.900 7.400 ; RECT 6.600 6.100 7.000 7.400 ; LAYER metal1 ; RECT 0.200 0.600 0.600 3.000 ; RECT 1.800 7.000 2.200 7.700 ; RECT 1.800 7.400 2.800 7.700 ; RECT 2.400 7.400 2.800 9.400 ; RECT 2.400 0.600 2.800 1.600 ; RECT 1.800 1.300 2.800 1.600 ; RECT 1.800 1.300 2.200 2.000 ; RECT 1.800 5.700 4.500 6.000 ; RECT 1.800 5.700 2.200 6.100 ; RECT 4.100 5.700 4.500 6.100 ; RECT 4.600 0.600 5.000 1.600 ; RECT 4.600 0.600 4.900 2.200 ; RECT 3.500 1.900 4.900 2.200 ; RECT 3.500 1.900 3.900 2.300 ; RECT 3.500 6.700 3.900 7.100 ; RECT 4.900 6.700 5.300 7.100 ; RECT 3.500 6.800 5.300 7.100 ; RECT 4.600 6.800 4.900 9.400 ; RECT 4.600 7.400 5.000 9.400 ; RECT 6.600 7.000 7.000 7.400 ; RECT 6.700 7.400 7.300 9.400 ; RECT 0.200 4.900 2.500 5.200 ; RECT 2.100 5.100 5.700 5.400 ; RECT 5.400 5.100 5.700 6.100 ; RECT 5.400 5.700 7.300 6.000 ; RECT 5.400 5.700 5.900 6.100 ; RECT 6.900 5.700 7.300 6.100 ; RECT 0.200 4.900 0.600 9.400 ; RECT 6.700 0.600 7.300 1.600 ; RECT 6.600 1.300 7.000 2.000 ; RECT 6.600 4.000 7.000 4.400 ; RECT 6.600 4.100 8.500 4.400 ; RECT 8.100 4.100 8.500 4.500 ; LAYER via ; RECT 0.300 5.100 0.500 5.300 ; RECT 0.300 2.700 0.500 2.900 ; RECT 1.900 7.100 2.100 7.300 ; RECT 1.900 5.800 2.100 6.000 ; RECT 1.900 1.700 2.100 1.900 ; RECT 6.700 7.100 6.900 7.300 ; RECT 6.700 4.100 6.900 4.300 ; RECT 6.700 1.700 6.900 1.900 ; END END DFFNEGX1 MACRO NOR3X1 CLASS CORE ; FOREIGN NOR3X1 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 6.400 BY 10.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 1.000 2.300 1.900 2.700 ; END END A PIN B DIRECTION INPUT ; PORT LAYER metal1 ; RECT 1.800 3.300 2.600 3.700 ; END END B PIN C DIRECTION INPUT ; PORT LAYER metal1 ; RECT 2.600 4.300 3.400 4.700 ; END END C PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 1.000 -0.300 1.400 1.600 ; RECT -0.200 -0.300 6.600 0.300 ; RECT 2.600 -0.300 3.000 1.400 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 1.800 0.600 2.200 1.600 ; RECT 5.000 6.000 5.400 8.800 ; RECT 5.000 5.300 5.400 5.700 ; RECT 5.000 5.300 5.300 8.800 ; RECT 3.700 5.300 5.400 5.600 ; RECT 3.700 1.600 4.000 5.600 ; RECT 3.400 0.600 3.800 2.000 ; RECT 2.000 1.700 4.000 2.000 ; RECT 2.000 1.300 2.300 2.000 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 1.000 6.400 1.400 10.300 ; RECT -0.200 9.700 6.600 10.300 ; END END vdd OBS LAYER metal1 ; RECT 0.300 5.800 2.100 6.100 ; RECT 1.800 5.800 2.100 9.400 ; RECT 1.800 6.400 2.200 9.400 ; RECT 0.300 5.800 0.600 9.400 ; RECT 0.200 6.400 0.600 9.400 ; RECT 3.400 6.500 3.800 9.400 ; RECT 1.800 9.100 3.800 9.400 ; RECT 2.700 5.900 4.500 6.200 ; RECT 2.700 5.900 3.000 8.800 ; RECT 2.600 6.400 3.000 8.800 ; RECT 4.200 6.000 4.600 9.000 ; RECT 5.800 6.000 6.200 9.000 ; RECT 4.300 6.000 4.600 9.400 ; RECT 5.800 6.000 6.100 9.400 ; RECT 4.300 9.100 6.100 9.400 ; END END NOR3X1 MACRO DFFPOSX1 CLASS CORE ; FOREIGN DFFPOSX1 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 9.600 BY 10.000 ; SYMMETRY X Y ; SITE core ; PIN Q DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 7.300 4.700 7.700 5.100 ; RECT 9.000 0.600 9.400 9.400 ; RECT 7.300 4.800 9.400 5.100 ; RECT 7.500 2.800 9.400 3.100 ; RECT 7.500 2.700 7.900 3.100 ; END END Q PIN CLK DIRECTION INPUT ; USE CLOCK ; PORT LAYER metal1 ; RECT 0.600 3.300 1.400 3.700 ; RECT 6.700 6.100 7.400 6.500 ; RECT 6.700 5.300 7.000 6.500 ; RECT 5.800 5.300 7.000 5.600 ; RECT 5.800 3.400 6.100 5.600 ; RECT 5.500 3.300 5.900 3.700 ; RECT 0.600 3.400 6.100 3.700 ; RECT 2.700 1.900 3.000 3.700 ; RECT 2.600 1.900 3.000 2.300 ; RECT 2.100 3.400 2.500 3.800 ; END END CLK PIN D DIRECTION INPUT ; PORT LAYER metal1 ; RECT 1.300 4.200 1.700 4.600 ; RECT 3.400 4.300 3.800 4.700 ; RECT 1.300 4.300 3.800 4.600 ; END END D PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 1.000 -0.300 1.400 2.600 ; RECT -0.200 -0.300 9.800 0.300 ; RECT 8.200 -0.300 8.600 2.500 ; RECT 5.400 -0.300 5.800 1.600 ; RECT 3.700 -0.300 4.200 1.600 ; END END gnd PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 1.000 5.500 1.400 10.300 ; RECT -0.200 9.700 9.800 10.300 ; RECT 8.200 5.400 8.600 10.300 ; RECT 5.400 7.400 5.800 10.300 ; RECT 3.800 7.400 4.200 10.300 ; END END vdd OBS LAYER metal2 ; RECT 0.200 2.600 0.600 5.400 ; RECT 1.800 1.600 2.200 7.400 ; RECT 6.600 1.600 7.000 7.400 ; LAYER metal1 ; RECT 0.200 0.600 0.600 3.000 ; RECT 1.800 7.000 2.200 7.700 ; RECT 1.800 7.400 2.800 7.700 ; RECT 2.400 7.400 2.800 9.400 ; RECT 2.400 0.600 2.800 1.600 ; RECT 1.800 1.300 2.800 1.600 ; RECT 1.800 1.300 2.200 2.000 ; RECT 1.800 5.700 4.500 6.000 ; RECT 1.800 5.700 2.200 6.100 ; RECT 4.100 5.700 4.500 6.100 ; RECT 4.600 0.600 5.000 1.600 ; RECT 4.600 0.600 4.900 2.200 ; RECT 3.500 1.900 4.900 2.200 ; RECT 3.500 1.900 3.900 2.300 ; RECT 3.500 6.700 3.900 7.100 ; RECT 4.900 6.700 5.300 7.100 ; RECT 3.500 6.800 5.300 7.100 ; RECT 4.600 6.800 4.900 9.400 ; RECT 4.600 7.400 5.000 9.400 ; RECT 0.200 5.000 3.100 5.200 ; RECT 0.200 4.900 3.000 5.200 ; RECT 2.700 5.100 5.100 5.400 ; RECT 4.800 5.100 5.100 6.300 ; RECT 5.500 5.900 5.900 6.300 ; RECT 4.800 6.000 5.900 6.300 ; RECT 0.200 4.900 0.600 9.400 ; RECT 6.600 7.000 7.000 7.400 ; RECT 6.700 7.400 7.300 9.400 ; RECT 6.700 0.600 7.300 1.600 ; RECT 6.600 1.300 7.000 2.000 ; RECT 6.600 4.000 7.000 4.400 ; RECT 6.600 4.100 8.500 4.400 ; RECT 8.100 4.100 8.500 4.500 ; LAYER via ; RECT 0.300 5.100 0.500 5.300 ; RECT 0.300 2.700 0.500 2.900 ; RECT 1.900 7.100 2.100 7.300 ; RECT 1.900 5.800 2.100 6.000 ; RECT 1.900 1.700 2.100 1.900 ; RECT 6.700 7.100 6.900 7.300 ; RECT 6.700 4.100 6.900 4.300 ; RECT 6.700 1.700 6.900 1.900 ; END END DFFPOSX1 MACRO FAX1 CLASS CORE ; FOREIGN FAX1 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 12.000 BY 10.000 ; SYMMETRY X Y ; SITE core ; PIN YC DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 11.400 0.600 11.800 1.600 ; RECT 11.400 7.400 11.800 9.400 ; RECT 11.500 0.600 11.800 9.400 ; RECT 11.400 3.300 11.800 3.700 ; END END YC PIN YS DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 9.800 0.600 10.200 1.600 ; RECT 10.400 2.300 11.000 2.700 ; RECT 9.700 4.600 10.700 4.900 ; RECT 10.400 1.900 10.700 4.900 ; RECT 9.900 1.900 10.700 2.200 ; RECT 9.800 7.400 10.200 9.400 ; RECT 9.900 0.600 10.200 2.200 ; RECT 9.700 4.600 10.000 7.700 ; END END YS PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.300 3.000 1.000 3.300 ; RECT 8.900 3.400 9.300 3.800 ; RECT 8.900 2.800 9.200 3.800 ; RECT 3.700 2.800 9.200 3.100 ; RECT 0.300 3.000 4.100 3.200 ; RECT 0.600 2.900 9.200 3.100 ; RECT 0.200 3.300 0.600 3.700 ; END END A PIN B DIRECTION INPUT ; PORT LAYER metal1 ; RECT 1.100 3.600 1.400 4.700 ; RECT 8.000 3.400 8.400 3.800 ; RECT 4.700 3.400 8.400 3.700 ; RECT 1.100 3.600 5.100 3.800 ; RECT 1.400 3.500 8.400 3.700 ; RECT 2.900 3.500 3.300 3.900 ; RECT 1.100 3.600 1.800 3.900 ; RECT 1.000 4.300 1.400 4.700 ; END END B PIN C DIRECTION INPUT ; PORT LAYER metal1 ; RECT 1.800 4.300 2.600 4.700 ; RECT 7.200 4.000 7.600 4.400 ; RECT 5.200 4.100 7.600 4.400 ; RECT 1.800 4.300 5.900 4.500 ; RECT 1.800 4.300 5.500 4.600 ; END END C PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 1.000 -0.300 1.400 2.000 ; RECT -0.200 -0.300 12.200 0.300 ; RECT 10.600 -0.300 11.000 1.600 ; RECT 9.000 -0.300 9.400 2.500 ; RECT 5.500 -0.300 5.900 1.900 ; RECT 3.900 -0.300 4.300 2.400 ; END END gnd PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 1.000 6.000 1.400 10.300 ; RECT -0.200 9.700 12.200 10.300 ; RECT 10.600 7.400 11.000 10.300 ; RECT 9.000 4.600 9.400 10.300 ; RECT 5.500 6.400 5.900 10.300 ; RECT 3.900 5.400 4.300 10.300 ; END END vdd OBS LAYER metal2 ; RECT 7.200 2.100 7.600 2.500 ; RECT 7.300 3.900 10.100 4.200 ; RECT 9.700 3.900 10.100 4.300 ; RECT 7.300 2.100 7.600 5.100 ; RECT 7.200 4.700 7.600 5.100 ; RECT 2.600 2.200 3.000 2.600 ; RECT 6.000 4.800 6.400 5.700 ; RECT 10.400 5.300 10.800 5.700 ; RECT 2.600 5.400 10.800 5.700 ; RECT 2.700 2.200 3.000 5.800 ; RECT 2.600 5.400 3.000 5.800 ; LAYER metal1 ; RECT 0.200 5.400 2.200 5.700 ; RECT 0.200 5.400 0.600 9.400 ; RECT 1.800 5.400 2.200 9.400 ; RECT 0.200 0.600 0.600 2.600 ; RECT 1.800 0.600 2.200 2.600 ; RECT 0.200 2.300 2.200 2.600 ; RECT 2.600 5.400 3.000 9.400 ; RECT 2.600 0.600 3.000 2.600 ; RECT 4.700 5.800 6.700 6.100 ; RECT 4.700 5.400 5.100 9.400 ; RECT 6.300 5.800 6.700 9.400 ; RECT 4.700 0.600 5.100 2.500 ; RECT 6.300 0.600 6.700 2.500 ; RECT 4.700 2.200 6.700 2.500 ; RECT 6.400 4.700 6.800 5.100 ; RECT 6.000 4.800 6.400 5.200 ; RECT 7.200 4.700 7.600 9.400 ; RECT 7.100 5.100 7.600 9.400 ; RECT 7.100 0.600 7.600 2.100 ; RECT 7.200 0.600 7.600 2.500 ; RECT 9.700 3.500 10.100 4.300 ; RECT 10.400 5.300 11.200 5.700 ; LAYER via ; RECT 2.700 5.500 2.900 5.700 ; RECT 2.700 2.300 2.900 2.500 ; RECT 6.100 4.900 6.300 5.100 ; RECT 7.300 4.800 7.500 5.000 ; RECT 7.300 2.200 7.500 2.400 ; RECT 9.800 4.000 10.000 4.200 ; RECT 10.500 5.400 10.700 5.600 ; END END FAX1 MACRO HAX1 CLASS CORE ; FOREIGN HAX1 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 8.000 BY 10.000 ; SYMMETRY X Y ; SITE core ; PIN YC DIRECTION OUTPUT ; PORT LAYER metal2 ; RECT 2.300 1.600 3.000 2.000 ; RECT 2.600 4.200 3.000 4.600 ; RECT 2.700 1.600 3.000 4.600 ; LAYER via ; RECT 2.400 1.700 2.600 1.900 ; RECT 2.700 4.300 2.900 4.500 ; LAYER metal1 ; RECT 2.300 0.600 2.700 2.000 ; RECT 2.600 4.200 3.000 9.400 ; END END YC PIN YS DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 6.600 5.300 7.000 5.700 ; RECT 7.100 7.400 7.500 9.400 ; RECT 7.200 6.800 7.500 9.400 ; RECT 6.700 2.000 7.500 2.300 ; RECT 7.200 0.600 7.500 2.300 ; RECT 6.700 6.800 7.500 7.100 ; RECT 7.100 0.600 7.500 1.600 ; RECT 6.700 2.000 7.000 7.100 ; END END YS PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.200 3.000 0.600 3.700 ; RECT 5.000 3.300 5.400 3.700 ; RECT 4.200 3.300 5.400 3.600 ; RECT 0.200 3.000 4.500 3.300 ; RECT 0.400 2.900 0.800 3.300 ; END END A PIN B DIRECTION INPUT ; PORT LAYER metal1 ; RECT 1.100 4.000 1.500 4.300 ; RECT 4.200 3.900 4.600 4.300 ; RECT 3.600 3.900 4.600 4.200 ; RECT 1.200 3.600 3.900 3.900 ; RECT 1.200 3.600 1.600 4.000 ; RECT 1.000 4.300 1.400 4.700 ; END END B PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.200 -0.300 0.600 2.600 ; RECT -0.200 -0.300 8.200 0.300 ; RECT 6.300 -0.300 6.700 1.600 ; RECT 3.100 -0.300 3.500 2.500 ; END END gnd PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 1.000 7.600 1.400 10.300 ; RECT -0.200 9.700 8.200 10.300 ; RECT 6.300 7.400 6.700 10.300 ; RECT 5.500 5.400 5.900 10.300 ; RECT 3.400 7.400 3.800 10.300 ; END END vdd OBS LAYER metal2 ; RECT 1.900 2.300 2.300 2.700 ; RECT 1.900 2.300 2.200 4.600 ; RECT 1.900 4.200 2.300 4.600 ; LAYER metal1 ; RECT 1.900 4.200 2.300 4.600 ; RECT 0.300 7.000 2.200 7.300 ; RECT 0.300 7.000 0.600 9.400 ; RECT 0.200 7.400 0.600 9.400 ; RECT 1.900 4.200 2.200 9.400 ; RECT 1.800 7.000 2.200 9.400 ; RECT 1.500 0.600 1.900 2.600 ; RECT 1.900 2.300 2.800 2.700 ; RECT 3.900 0.600 5.900 0.900 ; RECT 5.500 0.600 5.900 2.400 ; RECT 3.900 0.600 4.300 2.600 ; RECT 4.700 1.200 5.100 2.600 ; RECT 4.800 1.200 5.100 3.000 ; RECT 4.800 2.700 6.300 3.000 ; RECT 5.700 2.700 6.300 3.100 ; RECT 5.700 2.700 6.000 5.100 ; RECT 4.300 4.800 6.000 5.100 ; RECT 4.300 4.800 4.600 9.400 ; RECT 4.200 5.400 4.600 9.400 ; LAYER via ; RECT 2.000 4.300 2.200 4.500 ; RECT 2.000 2.400 2.200 2.600 ; END END HAX1 MACRO INVX1 CLASS CORE ; FOREIGN INVX1 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 1.600 BY 10.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.200 1.900 0.600 2.700 ; END END A PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.200 -0.300 0.600 1.600 ; RECT -0.200 -0.300 1.800 0.300 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 1.000 0.600 1.400 9.400 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.200 7.400 0.600 10.300 ; RECT -0.200 9.700 1.800 10.300 ; END END vdd END INVX1 MACRO INVX2 CLASS CORE ; FOREIGN INVX2 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 1.600 BY 10.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.200 2.900 0.600 3.700 ; END END A PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.200 -0.300 0.600 2.600 ; RECT -0.200 -0.300 1.800 0.300 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 1.000 0.600 1.400 9.400 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.200 5.400 0.600 10.300 ; RECT -0.200 9.700 1.800 10.300 ; END END vdd END INVX2 MACRO INVX4 CLASS CORE ; FOREIGN INVX4 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 2.400 BY 10.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.200 2.900 0.600 3.700 ; END END A PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.200 -0.300 0.600 2.600 ; RECT -0.200 -0.300 2.600 0.300 ; RECT 1.800 -0.300 2.200 2.600 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 1.000 0.600 1.400 9.400 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.200 5.400 0.600 10.300 ; RECT -0.200 9.700 2.600 10.300 ; RECT 1.800 5.400 2.200 10.300 ; END END vdd END INVX4 MACRO INVX8 CLASS CORE ; FOREIGN INVX8 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 4.000 BY 10.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.200 2.900 0.600 3.700 ; END END A PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.200 -0.300 0.600 2.600 ; RECT -0.200 -0.300 4.200 0.300 ; RECT 3.400 -0.300 3.800 2.600 ; RECT 1.800 -0.300 2.200 2.600 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 1.000 0.600 1.400 3.300 ; RECT 2.600 0.600 3.000 9.400 ; RECT 1.000 4.700 3.000 5.100 ; RECT 1.000 2.900 3.000 3.300 ; RECT 1.000 4.700 1.400 9.400 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.200 5.400 0.600 10.300 ; RECT -0.200 9.700 4.200 10.300 ; RECT 3.400 5.400 3.800 10.300 ; RECT 1.800 5.400 2.200 10.300 ; END END vdd END INVX8 MACRO NAND2X1 CLASS CORE ; FOREIGN NAND2X1 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 2.400 BY 10.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.200 2.900 0.600 3.700 ; END END A PIN B DIRECTION INPUT ; PORT LAYER metal1 ; RECT 1.800 5.300 2.200 6.100 ; END END B PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.200 -0.300 0.600 2.600 ; RECT -0.200 -0.300 2.600 0.300 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 1.000 2.300 1.400 9.400 ; RECT 1.000 2.300 1.900 2.600 ; RECT 1.500 0.600 1.900 2.600 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.200 7.400 0.600 10.300 ; RECT -0.200 9.700 2.600 10.300 ; RECT 1.800 7.400 2.200 10.300 ; END END vdd END NAND2X1 MACRO NAND3X1 CLASS CORE ; FOREIGN NAND3X1 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 3.200 BY 10.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.200 4.900 0.600 5.700 ; END END A PIN B DIRECTION INPUT ; PORT LAYER metal1 ; RECT 1.000 4.300 1.800 4.700 ; END END B PIN C DIRECTION INPUT ; PORT LAYER metal1 ; RECT 1.800 5.900 2.200 6.700 ; END END C PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.200 -0.300 0.600 3.600 ; RECT -0.200 -0.300 3.400 0.300 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 1.100 7.000 1.400 9.400 ; RECT 2.600 7.400 3.000 9.400 ; RECT 2.600 5.300 3.000 5.700 ; RECT 2.600 3.400 2.900 9.400 ; RECT 1.100 7.000 2.900 7.300 ; RECT 2.100 3.400 2.900 3.700 ; RECT 2.000 0.600 2.400 3.600 ; RECT 1.000 7.400 1.400 9.400 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.200 7.400 0.600 10.300 ; RECT -0.200 9.700 3.400 10.300 ; RECT 1.800 7.600 2.200 10.300 ; END END vdd END NAND3X1 MACRO NOR2X1 CLASS CORE ; FOREIGN NOR2X1 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 2.400 BY 10.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.200 1.900 0.600 2.700 ; END END A PIN B DIRECTION INPUT ; PORT LAYER metal1 ; RECT 1.800 4.300 2.200 5.100 ; END END B PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.200 -0.300 0.600 1.600 ; RECT -0.200 -0.300 2.600 0.300 ; RECT 1.800 -0.300 2.200 1.600 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 1.000 0.600 1.400 1.600 ; RECT 1.500 5.400 1.900 9.400 ; RECT 1.000 5.400 1.900 5.800 ; RECT 1.100 0.600 1.400 5.800 ; RECT 1.000 3.300 1.400 3.700 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.200 5.400 0.600 10.300 ; RECT -0.200 9.700 2.600 10.300 ; END END vdd END NOR2X1 MACRO OAI21X1 CLASS CORE ; FOREIGN OAI21X1 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 3.200 BY 10.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.200 3.300 0.600 3.700 ; RECT 0.600 3.100 1.000 3.600 ; END END A PIN B DIRECTION INPUT ; PORT LAYER metal1 ; RECT 1.000 3.900 1.400 4.700 ; END END B PIN C DIRECTION INPUT ; PORT LAYER metal1 ; RECT 2.300 5.400 2.600 6.700 ; RECT 2.600 5.300 3.000 5.700 ; RECT 2.200 6.300 2.600 6.700 ; END END C PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 1.000 -0.300 1.400 2.200 ; RECT -0.200 -0.300 3.400 0.300 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 1.500 5.400 1.900 9.400 ; RECT 1.700 3.300 3.000 3.700 ; RECT 2.600 0.600 3.000 2.600 ; RECT 2.600 0.600 2.900 3.700 ; RECT 1.700 3.300 2.000 5.700 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.200 5.400 0.600 10.300 ; RECT -0.200 9.700 3.400 10.300 ; RECT 2.300 7.400 2.700 10.300 ; END END vdd OBS LAYER metal1 ; RECT 0.200 0.600 0.600 2.600 ; RECT 1.800 0.600 2.200 2.600 ; RECT 0.300 2.500 2.100 2.800 ; END END OAI21X1 MACRO OAI22X1 CLASS CORE ; FOREIGN OAI22X1 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 4.000 BY 10.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.200 3.300 0.600 3.700 ; RECT 0.600 3.100 1.000 3.600 ; END END A PIN B DIRECTION INPUT ; PORT LAYER metal1 ; RECT 1.000 3.900 1.400 4.700 ; END END B PIN C DIRECTION INPUT ; PORT LAYER metal1 ; RECT 3.400 3.300 3.800 4.100 ; END END C PIN D DIRECTION INPUT ; PORT LAYER metal1 ; RECT 2.600 3.900 3.000 4.700 ; END END D PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 1.000 -0.300 1.400 2.200 ; RECT -0.200 -0.300 4.200 0.300 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 1.800 3.300 2.100 9.400 ; RECT 1.800 3.300 3.000 3.600 ; RECT 2.700 1.200 3.000 3.600 ; RECT 2.600 1.200 3.000 2.600 ; RECT 1.500 5.400 2.500 9.400 ; RECT 1.800 3.300 2.200 3.700 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.200 5.400 0.600 10.300 ; RECT -0.200 9.700 4.200 10.300 ; RECT 3.400 5.400 3.800 10.300 ; END END vdd OBS LAYER metal1 ; RECT 1.800 0.600 3.800 0.900 ; RECT 0.200 0.600 0.600 2.600 ; RECT 1.800 0.600 2.200 2.600 ; RECT 3.400 0.600 3.800 2.600 ; RECT 0.300 2.500 2.100 2.800 ; END END OAI22X1 MACRO OR2X1 CLASS CORE ; FOREIGN OR2X1 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 3.200 BY 10.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.200 1.900 0.600 2.700 ; END END A PIN B DIRECTION INPUT ; PORT LAYER metal1 ; RECT 1.000 3.300 1.400 3.700 ; RECT 1.100 2.900 1.800 3.300 ; END END B PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.200 -0.300 0.600 1.600 ; RECT -0.200 -0.300 3.400 0.300 ; RECT 1.800 -0.300 2.200 1.600 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 2.600 0.600 3.000 1.600 ; RECT 2.700 0.600 3.000 7.400 ; RECT 2.300 7.400 2.700 9.400 ; RECT 2.400 7.100 3.000 7.400 ; RECT 2.600 4.300 3.000 4.700 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 1.500 5.400 1.900 10.300 ; RECT -0.200 9.700 3.400 10.300 ; END END vdd OBS LAYER metal1 ; RECT 1.000 0.600 1.400 1.600 ; RECT 1.100 0.600 1.400 2.400 ; RECT 1.100 2.100 2.400 2.400 ; RECT 2.100 2.100 2.400 3.900 ; RECT 1.900 3.600 2.200 5.100 ; RECT 1.900 4.700 2.300 5.100 ; RECT 0.200 4.800 2.300 5.100 ; RECT 0.200 4.800 0.600 9.400 ; END END OR2X1 MACRO OR2X2 CLASS CORE ; FOREIGN OR2X2 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 3.200 BY 10.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.200 1.900 0.600 2.700 ; END END A PIN B DIRECTION INPUT ; PORT LAYER metal1 ; RECT 1.000 3.300 1.500 3.700 ; RECT 1.200 3.700 1.600 4.100 ; END END B PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.200 -0.300 0.600 1.600 ; RECT -0.200 -0.300 3.400 0.300 ; RECT 1.800 -0.300 2.200 2.400 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 2.600 0.600 3.000 2.600 ; RECT 2.700 0.600 3.000 5.700 ; RECT 2.300 5.400 2.700 9.400 ; RECT 2.600 4.300 3.000 4.700 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 1.500 5.400 1.900 10.300 ; RECT -0.200 9.700 3.400 10.300 ; END END vdd OBS LAYER metal1 ; RECT 1.000 0.600 1.400 1.600 ; RECT 1.100 0.600 1.400 3.000 ; RECT 1.100 2.700 2.300 3.000 ; RECT 1.900 4.500 2.300 4.900 ; RECT 2.000 2.700 2.300 4.900 ; RECT 0.200 4.800 2.200 5.100 ; RECT 0.200 4.800 0.600 9.400 ; END END OR2X2 MACRO TBUFX1 CLASS CORE ; FOREIGN TBUFX1 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 4.000 BY 10.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 3.000 3.300 3.800 3.700 ; END END A PIN EN DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.200 6.300 1.000 6.700 ; END END EN PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.200 -0.300 0.600 1.600 ; RECT -0.200 -0.300 4.200 0.300 ; RECT 3.200 -0.300 3.600 2.600 ; END END gnd PIN Y DIRECTION OUTPUT TRISTATE ; PORT LAYER metal1 ; RECT 1.900 0.600 2.300 2.600 ; RECT 1.900 5.400 2.300 9.400 ; RECT 2.000 0.600 2.300 9.400 ; RECT 1.800 4.300 2.300 4.700 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.200 7.400 0.600 10.300 ; RECT -0.200 9.700 4.200 10.300 ; RECT 3.200 5.400 3.600 10.300 ; END END vdd OBS LAYER metal1 ; RECT 1.000 0.600 1.400 1.600 ; RECT 1.300 3.300 1.700 3.700 ; RECT 1.300 1.200 1.600 4.000 ; RECT 1.200 3.700 1.500 5.300 ; RECT 1.300 5.000 1.600 7.700 ; RECT 1.000 7.400 1.400 9.400 ; END END TBUFX1 MACRO TBUFX2 CLASS CORE ; FOREIGN TBUFX2 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 5.600 BY 10.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 4.500 3.300 5.400 3.700 ; END END A PIN EN DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.200 2.900 0.500 5.100 ; RECT 0.200 2.900 0.700 3.300 ; RECT 0.200 4.300 0.600 5.100 ; END END EN PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.200 -0.300 0.600 2.600 ; RECT -0.200 -0.300 5.800 0.300 ; RECT 4.200 -0.300 4.600 2.300 ; END END gnd PIN Y DIRECTION OUTPUT TRISTATE ; PORT LAYER metal1 ; RECT 2.600 1.200 2.900 8.800 ; RECT 2.600 5.400 3.000 8.800 ; RECT 2.600 4.300 3.000 4.700 ; RECT 2.600 1.200 3.000 2.600 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.200 5.400 0.600 10.300 ; RECT -0.200 9.700 5.800 10.300 ; RECT 4.200 6.100 4.600 10.300 ; END END vdd OBS LAYER metal1 ; RECT 1.000 0.600 1.400 2.600 ; RECT 1.000 4.100 1.400 4.500 ; RECT 1.000 0.600 1.300 9.400 ; RECT 1.000 5.400 1.400 9.400 ; RECT 3.400 5.400 5.400 5.800 ; RECT 1.800 5.400 2.200 9.400 ; RECT 3.400 5.400 3.800 9.400 ; RECT 1.800 9.100 3.800 9.400 ; RECT 5.000 5.400 5.400 9.400 ; RECT 1.800 0.600 3.800 0.900 ; RECT 5.000 0.600 5.400 2.300 ; RECT 3.400 0.600 3.800 2.900 ; RECT 1.800 0.600 2.200 2.600 ; RECT 5.100 0.600 5.400 2.900 ; RECT 3.400 2.600 5.400 2.900 ; END END TBUFX2 MACRO XOR2X1 CLASS CORE ; FOREIGN XOR2X1 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 5.600 BY 10.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.200 3.300 1.000 3.700 ; RECT 2.000 3.500 2.400 3.900 ; RECT 1.000 3.500 2.400 3.800 ; RECT 0.200 3.400 1.300 3.700 ; END END A PIN B DIRECTION INPUT ; PORT LAYER metal1 ; RECT 4.600 3.300 5.400 3.700 ; END END B PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 1.100 -0.300 1.500 2.300 ; RECT -0.200 -0.300 5.800 0.300 ; RECT 4.100 -0.300 4.600 2.300 ; RECT 1.000 0.600 1.500 2.300 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 2.600 4.300 3.000 4.700 ; RECT 2.400 5.400 3.200 9.400 ; RECT 2.900 0.600 3.200 3.700 ; RECT 2.700 3.400 3.000 9.400 ; RECT 2.400 0.600 3.200 2.400 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 1.000 6.100 1.500 9.400 ; RECT -0.200 9.700 5.800 10.300 ; RECT 4.100 6.100 4.600 10.300 ; RECT 1.100 6.100 1.500 10.300 ; END END vdd OBS LAYER metal2 ; RECT 1.100 2.600 1.500 3.000 ; RECT 1.100 2.700 3.900 3.000 ; RECT 1.800 2.700 2.200 3.100 ; RECT 3.500 2.700 3.900 3.100 ; RECT 1.100 2.600 1.400 5.800 ; RECT 1.100 5.400 1.500 5.800 ; RECT 4.200 2.600 4.600 3.000 ; RECT 1.800 3.400 4.600 3.700 ; RECT 1.800 3.400 2.100 4.800 ; RECT 1.700 4.400 2.100 4.800 ; RECT 4.300 2.600 4.600 5.800 ; RECT 4.200 5.400 4.600 5.800 ; LAYER metal1 ; RECT 0.200 5.400 1.500 5.700 ; RECT 1.100 5.400 1.500 5.800 ; RECT 0.200 5.400 0.600 9.400 ; RECT 0.200 0.600 0.600 2.900 ; RECT 0.200 2.600 1.500 2.900 ; RECT 1.100 2.600 1.500 3.000 ; RECT 1.300 4.300 1.700 4.700 ; RECT 1.700 4.400 2.100 4.800 ; RECT 1.800 2.700 2.600 3.100 ; RECT 3.500 2.700 3.900 3.100 ; RECT 3.600 2.700 3.900 3.700 ; RECT 3.600 3.300 4.000 3.700 ; RECT 4.200 5.400 5.400 5.700 ; RECT 4.200 5.400 4.600 5.800 ; RECT 5.000 5.400 5.400 9.400 ; RECT 5.000 0.600 5.400 2.900 ; RECT 4.200 2.600 5.400 2.900 ; RECT 4.200 2.600 4.600 3.000 ; LAYER via ; RECT 1.200 5.500 1.400 5.700 ; RECT 1.200 2.700 1.400 2.900 ; RECT 1.800 4.500 2.000 4.700 ; RECT 1.900 2.800 2.100 3.000 ; RECT 3.600 2.800 3.800 3.000 ; RECT 4.300 5.500 4.500 5.700 ; RECT 4.300 2.700 4.500 2.900 ; END END XOR2X1 MACRO MUX2X1 CLASS CORE ; FOREIGN MUX2X1 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 4.800 BY 10.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 3.400 4.300 3.800 5.100 ; END END A PIN B DIRECTION INPUT ; PORT LAYER metal1 ; RECT 1.000 3.900 1.400 4.700 ; END END B PIN S DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.200 3.900 0.600 4.700 ; END END S PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 1.000 -0.300 1.400 2.800 ; RECT -0.200 -0.300 5.000 0.300 ; RECT 3.600 -0.300 4.000 3.000 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 2.300 1.000 2.700 2.800 ; RECT 2.800 3.300 3.800 3.700 ; RECT 2.300 5.600 3.100 5.900 ; RECT 2.800 2.500 3.100 5.900 ; RECT 2.700 2.500 3.100 3.000 ; RECT 2.300 5.600 2.700 9.400 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 1.000 5.600 1.400 10.300 ; RECT -0.200 9.700 5.000 10.300 ; RECT 3.600 5.400 4.000 10.300 ; END END vdd OBS LAYER metal1 ; RECT 0.200 1.000 0.600 2.000 ; RECT 0.200 1.000 0.500 3.400 ; RECT 0.200 3.100 2.300 3.400 ; RECT 1.800 3.100 2.300 4.000 ; RECT 1.800 3.600 2.500 4.000 ; RECT 1.800 3.100 2.100 5.300 ; RECT 0.200 5.000 2.100 5.300 ; RECT 0.200 5.000 0.500 9.000 ; RECT 0.200 7.000 0.600 9.000 ; END END MUX2X1 MACRO XNOR2X1 CLASS CORE ; FOREIGN XNOR2X1 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 5.600 BY 10.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal2 ; RECT 1.800 2.700 2.200 3.100 ; RECT 3.500 2.700 3.900 3.100 ; RECT 1.800 2.700 3.900 3.000 ; LAYER via ; RECT 1.900 2.800 2.100 3.000 ; RECT 3.600 2.800 3.800 3.000 ; LAYER metal1 ; RECT 0.200 3.300 1.000 3.700 ; RECT 3.600 3.300 4.000 3.700 ; RECT 3.600 2.700 3.900 3.700 ; RECT 3.500 2.700 3.900 3.100 ; RECT 1.800 2.700 2.600 3.100 ; RECT 0.200 3.300 1.900 3.600 ; RECT 1.600 2.800 1.900 3.600 ; END END A PIN B DIRECTION INPUT ; PORT LAYER metal1 ; RECT 4.600 3.300 5.400 3.700 ; END END B PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 1.100 -0.300 1.500 2.300 ; RECT -0.200 -0.300 5.800 0.300 ; RECT 4.100 -0.300 4.600 2.300 ; RECT 1.000 0.600 1.500 2.300 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 2.400 0.600 3.200 2.400 ; RECT 3.100 4.300 3.800 4.700 ; RECT 3.100 4.100 3.400 5.700 ; RECT 2.400 5.400 3.200 9.400 ; RECT 2.900 0.600 3.200 4.400 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 1.000 6.100 1.500 9.400 ; RECT -0.200 9.700 5.800 10.300 ; RECT 4.100 6.100 4.600 10.300 ; RECT 1.100 6.100 1.500 10.300 ; END END vdd OBS LAYER metal2 ; RECT 0.900 2.600 1.300 3.000 ; RECT 0.900 2.600 1.200 5.800 ; RECT 0.900 5.400 1.300 5.800 ; RECT 4.200 2.600 4.600 3.000 ; RECT 2.200 3.400 4.600 3.700 ; RECT 2.200 3.400 2.600 3.800 ; RECT 4.300 2.600 4.600 5.800 ; RECT 4.200 5.400 4.600 5.800 ; LAYER metal1 ; RECT 0.200 0.600 0.600 2.900 ; RECT 0.200 2.600 1.300 2.900 ; RECT 0.900 2.600 1.300 3.000 ; RECT 2.200 3.400 2.600 3.800 ; RECT 2.200 3.400 2.500 4.400 ; RECT 1.200 4.100 2.500 4.400 ; RECT 1.200 4.100 1.600 4.500 ; RECT 2.300 4.700 2.700 5.100 ; RECT 1.000 4.800 2.700 5.100 ; RECT 0.200 5.400 1.300 5.700 ; RECT 1.000 4.800 1.300 5.800 ; RECT 0.900 5.400 1.300 5.800 ; RECT 0.200 5.400 0.600 9.400 ; RECT 4.200 5.400 5.400 5.700 ; RECT 4.200 5.400 4.600 5.800 ; RECT 5.000 5.400 5.400 9.400 ; RECT 5.000 0.600 5.400 2.900 ; RECT 4.200 2.600 5.400 2.900 ; RECT 4.200 2.600 4.600 3.000 ; LAYER via ; RECT 1.000 5.500 1.200 5.700 ; RECT 1.000 2.700 1.200 2.900 ; RECT 2.300 3.500 2.500 3.700 ; RECT 4.300 5.500 4.500 5.700 ; RECT 4.300 2.700 4.500 2.900 ; END END XNOR2X1 MACRO LATCH CLASS CORE ; FOREIGN LATCH 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 5.600 BY 10.000 ; SYMMETRY X Y ; SITE core ; PIN Q DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 3.700 3.800 5.400 4.200 ; RECT 5.000 0.600 5.400 9.400 ; END END Q PIN CLK DIRECTION INPUT ; USE CLOCK ; PORT LAYER metal1 ; RECT 0.600 3.300 1.400 3.700 ; RECT 2.900 3.300 3.300 4.100 ; RECT 0.600 3.300 3.300 3.600 ; RECT 2.200 2.300 2.600 3.600 ; END END CLK PIN D DIRECTION INPUT ; PORT LAYER metal1 ; RECT 1.300 4.700 2.200 5.100 ; RECT 1.800 4.700 2.200 5.700 ; END END D PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 1.000 -0.300 1.400 2.600 ; RECT -0.200 -0.300 5.800 0.300 ; RECT 4.200 -0.300 4.600 2.600 ; END END gnd PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 1.000 5.400 1.400 10.300 ; RECT -0.200 9.700 5.800 10.300 ; RECT 4.200 5.400 4.600 10.300 ; END END vdd OBS LAYER metal2 ; RECT 0.200 2.600 0.600 5.400 ; RECT 2.600 1.600 3.000 7.400 ; LAYER metal1 ; RECT 0.200 4.900 0.600 9.400 ; RECT 0.200 0.600 0.600 3.000 ; RECT 0.200 4.000 2.500 4.300 ; RECT 0.200 4.000 0.600 4.400 ; RECT 2.100 4.000 2.500 4.400 ; RECT 2.600 7.000 3.000 9.400 ; RECT 2.500 7.400 3.100 9.400 ; RECT 2.500 0.600 3.100 1.600 ; RECT 2.600 0.600 3.000 2.000 ; RECT 2.600 4.700 4.700 5.100 ; LAYER via ; RECT 0.300 5.100 0.500 5.300 ; RECT 0.300 4.100 0.500 4.300 ; RECT 0.300 2.700 0.500 2.900 ; RECT 2.700 7.100 2.900 7.300 ; RECT 2.700 4.800 2.900 5.000 ; RECT 2.700 1.700 2.900 1.900 ; END END LATCH MACRO DFFSR CLASS CORE ; FOREIGN DFFSR 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 17.600 BY 10.000 ; SYMMETRY X Y ; SITE core ; PIN Q DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 16.200 0.600 16.600 2.900 ; RECT 16.300 2.500 16.700 5.500 ; RECT 16.200 5.100 16.600 9.400 ; END END Q PIN CLK DIRECTION INPUT ; USE CLOCK ; PORT LAYER metal1 ; RECT 8.200 2.300 9.000 2.700 ; END END CLK PIN R DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.900 4.400 1.300 4.800 ; RECT 0.900 4.500 12.600 4.800 ; RECT 12.200 4.200 12.600 4.800 ; RECT 3.400 4.300 3.800 4.800 ; END END R PIN S DIRECTION INPUT ; PORT LAYER metal1 ; RECT 1.800 5.100 2.200 5.700 ; RECT 1.800 5.100 15.300 5.400 ; RECT 14.900 5.000 15.300 5.400 ; RECT 3.500 5.100 3.900 5.500 ; END END S PIN D DIRECTION INPUT ; PORT LAYER metal1 ; RECT 6.600 2.900 7.000 3.700 ; END END D PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 1.800 -0.300 2.200 2.600 ; RECT -0.200 -0.300 17.800 0.300 ; RECT 17.000 -0.300 17.400 1.600 ; RECT 13.800 -0.300 14.200 2.600 ; RECT 8.200 -0.300 8.600 1.600 ; RECT 6.600 -0.300 7.000 1.600 ; END END gnd PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.200 7.400 0.600 10.300 ; RECT -0.200 9.700 17.800 10.300 ; RECT 17.000 7.400 17.400 10.300 ; RECT 15.400 7.400 15.800 10.300 ; RECT 13.800 7.400 14.200 10.300 ; RECT 12.200 7.400 12.600 10.300 ; RECT 8.200 7.400 8.600 10.300 ; RECT 6.600 7.400 7.000 10.300 ; RECT 3.400 7.400 3.800 10.300 ; RECT 1.800 7.400 2.200 10.300 ; END END vdd OBS LAYER metal2 ; RECT 4.200 1.600 4.600 8.400 ; RECT 5.000 1.600 5.400 8.400 ; RECT 5.800 1.600 6.200 7.400 ; RECT 7.400 1.600 7.800 7.400 ; RECT 9.000 1.600 9.400 7.400 ; RECT 9.800 1.600 10.200 8.400 ; RECT 10.600 1.600 11.000 8.400 ; RECT 11.400 1.600 11.800 8.400 ; LAYER metal1 ; RECT 3.400 0.600 3.800 2.600 ; RECT 2.500 2.200 3.800 2.600 ; RECT 2.500 2.200 2.900 3.300 ; RECT 1.400 2.900 2.900 3.300 ; RECT 4.200 8.000 4.600 9.400 ; RECT 0.200 3.600 4.600 4.000 ; RECT 0.200 0.600 0.600 7.100 ; RECT 0.200 6.800 1.200 7.100 ; RECT 0.900 6.800 1.200 7.700 ; RECT 1.000 7.400 1.400 9.400 ; RECT 4.200 0.600 4.600 2.000 ; RECT 5.000 8.000 5.400 9.400 ; RECT 2.700 5.800 5.400 6.100 ; RECT 5.000 5.700 5.400 6.100 ; RECT 2.300 6.000 3.000 6.400 ; RECT 5.000 0.600 5.400 2.000 ; RECT 5.800 7.000 6.200 9.400 ; RECT 5.800 0.600 6.200 2.000 ; RECT 7.400 7.000 7.800 9.400 ; RECT 6.500 6.300 7.800 6.700 ; RECT 5.500 2.300 7.800 2.600 ; RECT 7.400 2.300 7.800 2.700 ; RECT 5.500 2.300 5.900 4.200 ; RECT 4.900 3.800 5.900 4.200 ; RECT 7.400 0.600 7.800 2.000 ; RECT 9.000 6.300 9.400 9.400 ; RECT 7.800 3.800 9.400 4.200 ; RECT 9.000 0.600 9.400 2.000 ; RECT 7.400 3.000 7.800 3.400 ; RECT 7.400 3.100 9.600 3.400 ; RECT 9.200 3.100 9.600 3.500 ; RECT 9.800 8.000 10.200 9.400 ; RECT 5.900 5.700 10.200 6.000 ; RECT 9.800 5.700 10.200 6.100 ; RECT 1.000 6.100 1.800 6.500 ; RECT 1.500 6.100 1.800 7.100 ; RECT 3.300 6.400 6.200 6.700 ; RECT 5.900 5.700 6.200 6.700 ; RECT 1.500 6.700 3.600 7.100 ; RECT 2.600 6.700 3.000 9.400 ; RECT 9.800 0.600 10.200 2.000 ; RECT 10.600 8.000 11.000 9.400 ; RECT 10.500 2.300 11.000 2.700 ; RECT 10.600 2.300 11.000 4.100 ; RECT 10.600 0.600 11.000 2.000 ; RECT 11.400 8.000 11.800 9.400 ; RECT 11.400 0.600 11.800 2.000 ; RECT 10.600 6.700 12.700 7.100 ; RECT 13.000 6.300 14.300 6.700 ; RECT 13.000 6.300 13.400 9.400 ; RECT 12.200 0.600 12.600 2.600 ; RECT 12.200 2.200 13.400 2.600 ; RECT 13.000 2.200 13.400 3.200 ; RECT 13.000 2.900 13.900 3.200 ; RECT 13.500 2.900 13.900 4.200 ; RECT 13.500 3.800 15.400 4.200 ; RECT 15.400 0.600 15.800 3.500 ; RECT 15.700 3.200 16.000 4.800 ; RECT 11.400 5.700 15.900 6.000 ; RECT 11.400 5.700 11.800 6.100 ; RECT 15.600 4.500 15.900 7.100 ; RECT 14.600 6.800 15.900 7.100 ; RECT 14.600 6.800 15.000 9.400 ; LAYER via ; RECT 4.300 8.100 4.500 8.300 ; RECT 4.300 3.700 4.500 3.900 ; RECT 4.300 1.700 4.500 1.900 ; RECT 5.100 8.100 5.300 8.300 ; RECT 5.100 5.800 5.300 6.000 ; RECT 5.100 1.700 5.300 1.900 ; RECT 5.900 7.100 6.100 7.300 ; RECT 5.900 1.700 6.100 1.900 ; RECT 7.500 7.100 7.700 7.300 ; RECT 7.500 6.400 7.700 6.600 ; RECT 7.500 3.100 7.700 3.300 ; RECT 7.500 1.700 7.700 1.900 ; RECT 9.100 7.100 9.300 7.300 ; RECT 9.100 3.900 9.300 4.100 ; RECT 9.100 1.700 9.300 1.900 ; RECT 9.900 8.100 10.100 8.300 ; RECT 9.900 5.800 10.100 6.000 ; RECT 9.900 1.700 10.100 1.900 ; RECT 10.700 8.100 10.900 8.300 ; RECT 10.700 6.800 10.900 7.000 ; RECT 10.700 1.700 10.900 1.900 ; RECT 11.500 8.100 11.700 8.300 ; RECT 11.500 5.800 11.700 6.000 ; RECT 11.500 1.700 11.700 1.900 ; END END DFFSR MACRO CLKBUF1 CLASS CORE ; FOREIGN CLKBUF1 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 7.200 BY 10.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.200 3.300 0.600 4.000 ; RECT 0.200 3.600 1.100 4.000 ; END END A PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.200 -0.300 0.600 2.600 ; RECT -0.200 -0.300 7.400 0.300 ; RECT 6.600 -0.300 7.000 2.600 ; RECT 5.000 -0.300 5.400 2.600 ; RECT 3.400 -0.300 3.800 2.600 ; RECT 1.800 -0.300 2.200 2.600 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 5.800 0.600 6.200 3.300 ; RECT 5.800 4.700 7.000 5.100 ; RECT 6.600 2.900 7.000 5.100 ; RECT 5.800 2.900 7.000 3.300 ; RECT 5.800 4.700 6.200 9.400 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.200 5.400 0.600 10.300 ; RECT -0.200 9.700 7.400 10.300 ; RECT 6.600 5.400 7.000 10.300 ; RECT 5.000 5.400 5.400 10.300 ; RECT 3.400 5.400 3.800 10.300 ; RECT 1.800 5.400 2.200 10.300 ; END END vdd OBS LAYER metal1 ; RECT 1.000 0.600 1.400 3.300 ; RECT 1.000 2.900 1.900 3.300 ; RECT 1.500 3.600 2.800 4.000 ; RECT 1.500 2.900 1.900 5.100 ; RECT 1.000 4.700 1.900 5.100 ; RECT 1.000 4.700 1.400 9.400 ; RECT 2.600 0.600 3.000 3.300 ; RECT 2.600 2.900 3.700 3.300 ; RECT 3.300 3.600 4.500 4.000 ; RECT 3.300 2.900 3.700 5.100 ; RECT 2.600 4.700 3.700 5.100 ; RECT 2.600 4.700 3.000 9.400 ; RECT 4.200 0.600 4.600 3.300 ; RECT 4.200 2.900 5.300 3.300 ; RECT 4.900 3.600 6.200 4.000 ; RECT 4.900 2.900 5.300 5.100 ; RECT 4.200 4.700 5.300 5.100 ; RECT 4.200 4.700 4.600 9.400 ; END END CLKBUF1 MACRO CLKBUF2 CLASS CORE ; FOREIGN CLKBUF2 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 10.400 BY 10.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.200 3.300 0.600 4.000 ; RECT 0.200 3.600 1.100 4.000 ; END END A PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.200 -0.300 0.600 2.600 ; RECT -0.200 -0.300 10.600 0.300 ; RECT 9.800 -0.300 10.200 2.600 ; RECT 8.200 -0.300 8.600 2.600 ; RECT 6.600 -0.300 7.000 2.600 ; RECT 5.000 -0.300 5.400 2.600 ; RECT 3.400 -0.300 3.800 2.600 ; RECT 1.800 -0.300 2.200 2.600 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 9.000 0.600 9.400 3.300 ; RECT 9.000 4.700 10.200 5.100 ; RECT 9.800 2.900 10.200 5.100 ; RECT 9.000 2.900 10.200 3.300 ; RECT 9.000 4.700 9.400 9.400 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.200 5.400 0.600 10.300 ; RECT -0.200 9.700 10.600 10.300 ; RECT 9.800 5.400 10.200 10.300 ; RECT 8.200 5.400 8.600 10.300 ; RECT 6.600 5.400 7.000 10.300 ; RECT 5.000 5.400 5.400 10.300 ; RECT 3.400 5.400 3.800 10.300 ; RECT 1.800 5.400 2.200 10.300 ; END END vdd OBS LAYER metal1 ; RECT 1.000 0.600 1.400 3.300 ; RECT 1.000 2.900 1.900 3.300 ; RECT 1.500 3.600 2.800 4.000 ; RECT 1.500 2.900 1.900 5.100 ; RECT 1.000 4.700 1.900 5.100 ; RECT 1.000 4.700 1.400 9.400 ; RECT 2.600 0.600 3.000 3.300 ; RECT 2.600 2.900 3.700 3.300 ; RECT 3.300 3.600 4.500 4.000 ; RECT 3.300 2.900 3.700 5.100 ; RECT 2.600 4.700 3.700 5.100 ; RECT 2.600 4.700 3.000 9.400 ; RECT 4.200 0.600 4.600 3.300 ; RECT 4.200 2.900 5.300 3.300 ; RECT 4.900 3.600 6.200 4.000 ; RECT 4.900 2.900 5.300 5.100 ; RECT 4.200 4.700 5.300 5.100 ; RECT 4.200 4.700 4.600 9.400 ; RECT 5.800 0.600 6.200 3.300 ; RECT 5.800 2.900 7.000 3.300 ; RECT 6.600 3.600 7.500 4.000 ; RECT 6.600 2.900 7.000 5.100 ; RECT 5.800 4.700 7.000 5.100 ; RECT 5.800 4.700 6.200 9.400 ; RECT 7.400 0.600 7.800 3.300 ; RECT 7.400 2.900 8.300 3.300 ; RECT 7.900 3.600 9.200 4.000 ; RECT 7.900 2.900 8.300 5.100 ; RECT 7.400 4.700 8.300 5.100 ; RECT 7.400 4.700 7.800 9.400 ; END END CLKBUF2 MACRO CLKBUF3 CLASS CORE ; FOREIGN CLKBUF3 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 13.600 BY 10.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.200 3.300 0.600 4.000 ; RECT 0.200 3.600 1.100 4.000 ; END END A PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.200 -0.300 0.600 2.600 ; RECT -0.200 -0.300 13.800 0.300 ; RECT 13.000 -0.300 13.400 2.600 ; RECT 11.400 -0.300 11.800 2.600 ; RECT 9.800 -0.300 10.200 2.600 ; RECT 8.200 -0.300 8.600 2.600 ; RECT 6.600 -0.300 7.000 2.600 ; RECT 5.000 -0.300 5.400 2.600 ; RECT 3.400 -0.300 3.800 2.600 ; RECT 1.800 -0.300 2.200 2.600 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 12.200 0.600 12.600 3.300 ; RECT 12.200 4.700 13.400 5.100 ; RECT 13.000 2.900 13.400 5.100 ; RECT 12.200 2.900 13.400 3.300 ; RECT 12.200 4.700 12.600 9.400 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.200 5.400 0.600 10.300 ; RECT -0.200 9.700 13.800 10.300 ; RECT 13.000 5.400 13.400 10.300 ; RECT 11.400 5.400 11.800 10.300 ; RECT 9.800 5.400 10.200 10.300 ; RECT 8.200 5.400 8.600 10.300 ; RECT 6.600 5.400 7.000 10.300 ; RECT 5.000 5.400 5.400 10.300 ; RECT 3.400 5.400 3.800 10.300 ; RECT 1.800 5.400 2.200 10.300 ; END END vdd OBS LAYER metal1 ; RECT 1.000 0.600 1.400 3.300 ; RECT 1.000 2.900 1.900 3.300 ; RECT 1.500 3.600 2.800 4.000 ; RECT 1.500 2.900 1.900 5.100 ; RECT 1.000 4.700 1.900 5.100 ; RECT 1.000 4.700 1.400 9.400 ; RECT 2.600 0.600 3.000 3.300 ; RECT 2.600 2.900 3.700 3.300 ; RECT 3.300 3.600 4.500 4.000 ; RECT 3.300 2.900 3.700 5.100 ; RECT 2.600 4.700 3.700 5.100 ; RECT 2.600 4.700 3.000 9.400 ; RECT 4.200 0.600 4.600 3.300 ; RECT 4.200 2.900 5.300 3.300 ; RECT 4.900 3.600 6.200 4.000 ; RECT 4.900 2.900 5.300 5.100 ; RECT 4.200 4.700 5.300 5.100 ; RECT 4.200 4.700 4.600 9.400 ; RECT 5.800 0.600 6.200 3.300 ; RECT 5.800 2.900 7.000 3.300 ; RECT 6.600 3.600 7.500 4.000 ; RECT 6.600 2.900 7.000 5.100 ; RECT 5.800 4.700 7.000 5.100 ; RECT 5.800 4.700 6.200 9.400 ; RECT 7.400 0.600 7.800 3.300 ; RECT 7.400 2.900 8.300 3.300 ; RECT 7.900 3.600 9.200 4.000 ; RECT 7.900 2.900 8.300 5.100 ; RECT 7.400 4.700 8.300 5.100 ; RECT 7.400 4.700 7.800 9.400 ; RECT 9.000 0.600 9.400 3.300 ; RECT 9.000 2.900 10.100 3.300 ; RECT 9.700 3.600 10.900 4.000 ; RECT 9.700 2.900 10.100 5.100 ; RECT 9.000 4.700 10.100 5.100 ; RECT 9.000 4.700 9.400 9.400 ; RECT 10.600 0.600 11.000 3.300 ; RECT 10.600 2.900 11.700 3.300 ; RECT 11.300 3.600 12.600 4.000 ; RECT 11.300 2.900 11.700 5.100 ; RECT 10.600 4.700 11.700 5.100 ; RECT 10.600 4.700 11.000 9.400 ; END END CLKBUF3 END LIBRARY qflow-1.1.23/tech/osu018/Makefile.in0000664000175000001440000000167312535603240015476 0ustar timusers# # qflow project included technology osu018 files # # Main compiler arguments CFLAGS = @CFLAGS@ DEFS = @DEFS@ LIBS = @LIBS@ LDFLAGS = @LDFLAGS@ INSTALL = @INSTALL@ QFLOW_LIB_DIR = @QFLOW_LIB_DIR@ TECH_FILES = osu018.par osu018_stdcells.lef osu018.sh TECH_FILES += osu018_stdcells.sp osu018.magicrc osu018.prm TECH_FILES += SCN6M_DEEP.09.tech osu018_stdcells.lib TECH_FILES += osu018_stdcells.v TECHINSTALL = ${QFLOW_LIB_DIR}/tech # Substitute the target qflow tech directory name in .magicrc so that magic # can find the OSU018 techfile all: osu018.magicrc.in $(RM) -f osu018.magicrc cat osu018.magicrc.in | sed -e \ '/QFLOW_LIB_DIR/s#QFLOW_LIB_DIR#$(QFLOW_LIB_DIR)#' \ > osu018.magicrc install: ${TECH_FILES} @echo "Installing osu018 tech files" $(INSTALL) -d $(DESTDIR)$(TECHINSTALL)/osu018 for target in $(TECH_FILES); do \ $(INSTALL) $$target $(DESTDIR)$(TECHINSTALL)/osu018 ;\ done clean: $(RM) -f osu018.magicrc uninstall: qflow-1.1.23/tech/osu018/osu018_stdcells.v0000775000175000001440000005405212535603240016556 0ustar timusers`timescale 1ns/10ps `celldefine module AND2X1 (A, B, Y); input A ; input B ; output Y ; and (Y, A, B); specify // delay parameters specparam tpllh$B$Y = 0.065:0.065:0.065, tphhl$B$Y = 0.086:0.086:0.086, tpllh$A$Y = 0.064:0.064:0.064, tphhl$A$Y = 0.076:0.076:0.076; // path delays (A *> Y) = (tpllh$A$Y, tphhl$A$Y); (B *> Y) = (tpllh$B$Y, tphhl$B$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module AND2X2 (A, B, Y); input A ; input B ; output Y ; and (Y, A, B); specify // delay parameters specparam tpllh$A$Y = 0.079:0.079:0.079, tphhl$A$Y = 0.094:0.094:0.094, tpllh$B$Y = 0.082:0.082:0.082, tphhl$B$Y = 0.1:0.1:0.1; // path delays (A *> Y) = (tpllh$A$Y, tphhl$A$Y); (B *> Y) = (tpllh$B$Y, tphhl$B$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module AOI21X1 (A, B, C, Y); input A ; input B ; input C ; output Y ; and (I0_out, A, B); or (I1_out, I0_out, C); not (Y, I1_out); specify // delay parameters specparam tplhl$A$Y = 0.048:0.048:0.048, tphlh$A$Y = 0.065:0.065:0.065, tplhl$B$Y = 0.049:0.049:0.049, tphlh$B$Y = 0.055:0.055:0.055, tplhl$C$Y = 0.039:0.041:0.043, tphlh$C$Y = 0.039:0.048:0.056; // path delays (A *> Y) = (tphlh$A$Y, tplhl$A$Y); (B *> Y) = (tphlh$B$Y, tplhl$B$Y); (C *> Y) = (tphlh$C$Y, tplhl$C$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module AOI22X1 (A, B, C, D, Y); input A ; input B ; input C ; input D ; output Y ; and (I0_out, A, B); and (I1_out, C, D); or (I2_out, I0_out, I1_out); not (Y, I2_out); specify // delay parameters specparam tplhl$C$Y = 0.042:0.043:0.045, tphlh$C$Y = 0.054:0.064:0.073, tplhl$D$Y = 0.041:0.043:0.044, tphlh$D$Y = 0.047:0.055:0.064, tplhl$A$Y = 0.055:0.06:0.064, tphlh$A$Y = 0.068:0.077:0.086, tplhl$B$Y = 0.056:0.06:0.065, tphlh$B$Y = 0.06:0.069:0.079; // path delays (A *> Y) = (tphlh$A$Y, tplhl$A$Y); (B *> Y) = (tphlh$B$Y, tplhl$B$Y); (C *> Y) = (tphlh$C$Y, tplhl$C$Y); (D *> Y) = (tphlh$D$Y, tplhl$D$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module BUFX2 (A, Y); input A ; output Y ; buf (Y, A); specify // delay parameters specparam tpllh$A$Y = 0.08:0.08:0.08, tphhl$A$Y = 0.09:0.09:0.09; // path delays (A *> Y) = (tpllh$A$Y, tphhl$A$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module BUFX4 (A, Y); input A ; output Y ; buf (Y, A); specify // delay parameters specparam tpllh$A$Y = 0.094:0.094:0.094, tphhl$A$Y = 0.097:0.097:0.097; // path delays (A *> Y) = (tpllh$A$Y, tphhl$A$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module CLKBUF1 (A, Y); input A ; output Y ; buf (Y, A); specify // delay parameters specparam tpllh$A$Y = 0.17:0.17:0.17, tphhl$A$Y = 0.17:0.17:0.17; // path delays (A *> Y) = (tpllh$A$Y, tphhl$A$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module CLKBUF2 (A, Y); input A ; output Y ; buf (Y, A); specify // delay parameters specparam tpllh$A$Y = 0.23:0.23:0.23, tphhl$A$Y = 0.24:0.24:0.24; // path delays (A *> Y) = (tpllh$A$Y, tphhl$A$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module CLKBUF3 (A, Y); input A ; output Y ; buf (Y, A); specify // delay parameters specparam tpllh$A$Y = 0.29:0.29:0.29, tphhl$A$Y = 0.3:0.3:0.3; // path delays (A *> Y) = (tpllh$A$Y, tphhl$A$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module DFFNEGX1 (CLK, D, Q); input CLK ; input D ; output Q ; reg NOTIFIER ; not (I0_CLOCK, CLK); udp_dff (DS0000, D, I0_CLOCK, 1'B0, 1'B0, NOTIFIER); not (P0002, DS0000); buf (Q, DS0000); specify // delay parameters specparam tphlh$CLK$Q = 0.13:0.13:0.13, tphhl$CLK$Q = 0.12:0.12:0.12, tminpwh$CLK = 0.043:0.094:0.14, tminpwl$CLK = 0.082:0.1:0.13, tsetup_negedge$D$CLK = 0.19:0.19:0.19, thold_negedge$D$CLK = 0.000000061:0.000000061:0.000000061, tsetup_posedge$D$CLK = 0.19:0.19:0.19, thold_posedge$D$CLK = 0.000000062:0.000000062:0.000000062; // path delays (CLK *> Q) = (tphlh$CLK$Q, tphhl$CLK$Q); $setup(negedge D, negedge CLK, tsetup_negedge$D$CLK, NOTIFIER); $hold (negedge D, negedge CLK, thold_negedge$D$CLK, NOTIFIER); $setup(posedge D, negedge CLK, tsetup_posedge$D$CLK, NOTIFIER); $hold (posedge D, negedge CLK, thold_posedge$D$CLK, NOTIFIER); $width(posedge CLK, tminpwh$CLK, 0, NOTIFIER); $width(negedge CLK, tminpwl$CLK, 0, NOTIFIER); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module DFFPOSX1 (CLK, D, Q); input CLK ; input D ; output Q ; reg NOTIFIER ; udp_dff (DS0000, D, CLK, 1'B0, 1'B0, NOTIFIER); not (P0002, DS0000); buf (Q, DS0000); specify // delay parameters specparam tpllh$CLK$Q = 0.094:0.094:0.094, tplhl$CLK$Q = 0.16:0.16:0.16, tminpwh$CLK = 0.054:0.11:0.16, tminpwl$CLK = 0.057:0.099:0.14, tsetup_negedge$D$CLK = 0.19:0.19:0.19, thold_negedge$D$CLK = -0.094:-0.094:-0.094, tsetup_posedge$D$CLK = 0.19:0.19:0.19, thold_posedge$D$CLK = 0.00000006:0.00000006:0.00000006; // path delays (CLK *> Q) = (tpllh$CLK$Q, tplhl$CLK$Q); $setup(negedge D, posedge CLK, tsetup_negedge$D$CLK, NOTIFIER); $hold (negedge D, posedge CLK, thold_negedge$D$CLK, NOTIFIER); $setup(posedge D, posedge CLK, tsetup_posedge$D$CLK, NOTIFIER); $hold (posedge D, posedge CLK, thold_posedge$D$CLK, NOTIFIER); $width(posedge CLK, tminpwh$CLK, 0, NOTIFIER); $width(negedge CLK, tminpwl$CLK, 0, NOTIFIER); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module DFFSR (CLK, D, R, S, Q); input CLK ; input D ; input R ; input S ; output Q ; reg NOTIFIER ; not (I0_CLEAR, R); not (I0_SET, S); udp_dff (P0003, D_, CLK, I0_SET, I0_CLEAR, NOTIFIER); not (D_, D); not (P0002, P0003); buf (Q, P0002); and (\D&S , D, S); not (I7_out, D); and (\~D&R , I7_out, R); and (\S&R , S, R); specify // delay parameters specparam tphlh$S$Q = 0.34:0.34:0.35, tpllh$R$Q = 0.26:0.26:0.26, tphhl$R$Q = 0.26:0.26:0.27, tpllh$CLK$Q = 0.39:0.39:0.39, tplhl$CLK$Q = 0.38:0.38:0.38, tminpwl$S = 0.053:0.2:0.35, tminpwl$R = 0.037:0.15:0.27, tminpwh$CLK = 0.18:0.28:0.39, tminpwl$CLK = 0.18:0.21:0.24, tsetup_negedge$D$CLK = 0.094:0.094:0.094, thold_negedge$D$CLK = 0.000000058:0.000000058:0.000000058, tsetup_posedge$D$CLK = 0.094:0.094:0.094, thold_posedge$D$CLK = 0.00000006:0.00000006:0.00000006, trec$R$CLK = -0.094:-0.094:-0.094, trem$R$CLK = 0.19:0.19:0.19, trec$R$S = 0.00000006:0.00000006:0.00000006, trec$S$CLK = 0:0:0, trem$S$CLK = 0.094:0.094:0.094, trec$S$R = 0.094:0.094:0.094; // path delays (CLK *> Q) = (tpllh$CLK$Q, tplhl$CLK$Q); (R *> Q) = (tpllh$R$Q, tphhl$R$Q); (S *> Q) = (tphlh$S$Q, 0); $setup(negedge D, posedge CLK &&& \S&R , tsetup_negedge$D$CLK, NOTIFIER); $hold (negedge D, posedge CLK &&& \S&R , thold_negedge$D$CLK, NOTIFIER); $setup(posedge D, posedge CLK &&& \S&R , tsetup_posedge$D$CLK, NOTIFIER); $hold (posedge D, posedge CLK &&& \S&R , thold_posedge$D$CLK, NOTIFIER); $recovery(posedge R, posedge CLK &&& \D&S , trec$R$CLK, NOTIFIER); $removal (posedge R, posedge CLK &&& \D&S , trem$R$CLK, NOTIFIER); $recovery(posedge R, posedge S, trec$R$S, NOTIFIER); $recovery(posedge S, posedge CLK &&& \~D&R , trec$S$CLK, NOTIFIER); $removal (posedge S, posedge CLK &&& \~D&R , trem$S$CLK, NOTIFIER); $recovery(posedge S, posedge R, trec$S$R, NOTIFIER); $width(negedge S, tminpwl$S, 0, NOTIFIER); $width(negedge R, tminpwl$R, 0, NOTIFIER); $width(posedge CLK, tminpwh$CLK, 0, NOTIFIER); $width(negedge CLK, tminpwl$CLK, 0, NOTIFIER); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module FAX1 (A, B, C, YC, YS); input A ; input B ; input C ; output YC ; output YS ; and (I0_out, A, B); and (I1_out, B, C); and (I3_out, C, A); or (YC, I0_out, I1_out, I3_out); xor (I5_out, A, B); xor (YS, I5_out, C); specify // delay parameters specparam tpllh$A$YS = 0.19:0.2:0.2, tplhl$A$YS = 0.18:0.18:0.18, tpllh$A$YC = 0.11:0.11:0.11, tphhl$A$YC = 0.13:0.13:0.13, tpllh$B$YS = 0.19:0.2:0.21, tplhl$B$YS = 0.19:0.19:0.19, tpllh$B$YC = 0.11:0.11:0.12, tphhl$B$YC = 0.13:0.13:0.14, tpllh$C$YS = 0.19:0.2:0.2, tplhl$C$YS = 0.18:0.18:0.18, tpllh$C$YC = 0.1:0.11:0.12, tphhl$C$YC = 0.12:0.12:0.13; // path delays (A *> YC) = (tpllh$A$YC, tphhl$A$YC); (A *> YS) = (tpllh$A$YS, tplhl$A$YS); (B *> YC) = (tpllh$B$YC, tphhl$B$YC); (B *> YS) = (tpllh$B$YS, tplhl$B$YS); (C *> YC) = (tpllh$C$YC, tphhl$C$YC); (C *> YS) = (tpllh$C$YS, tplhl$C$YS); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module HAX1 (A, B, YC, YS); input A ; input B ; output YC ; output YS ; and (YC, A, B); xor (YS, A, B); specify // delay parameters specparam tpllh$A$YS = 0.15:0.15:0.15, tplhl$A$YS = 0.15:0.15:0.15, tpllh$A$YC = 0.085:0.085:0.085, tphhl$A$YC = 0.11:0.11:0.11, tpllh$B$YS = 0.14:0.14:0.14, tplhl$B$YS = 0.15:0.15:0.15, tpllh$B$YC = 0.083:0.083:0.083, tphhl$B$YC = 0.097:0.097:0.097; // path delays (A *> YC) = (tpllh$A$YC, tphhl$A$YC); (A *> YS) = (tpllh$A$YS, tplhl$A$YS); (B *> YC) = (tpllh$B$YC, tphhl$B$YC); (B *> YS) = (tpllh$B$YS, tplhl$B$YS); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module INVX1 (A, Y); input A ; output Y ; not (Y, A); specify // delay parameters specparam tplhl$A$Y = 0.031:0.031:0.031, tphlh$A$Y = 0.038:0.038:0.038; // path delays (A *> Y) = (tphlh$A$Y, tplhl$A$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module INVX2 (A, Y); input A ; output Y ; not (Y, A); specify // delay parameters specparam tplhl$A$Y = 0.033:0.033:0.033, tphlh$A$Y = 0.038:0.038:0.038; // path delays (A *> Y) = (tphlh$A$Y, tplhl$A$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module INVX4 (A, Y); input A ; output Y ; not (Y, A); specify // delay parameters specparam tplhl$A$Y = 0.033:0.033:0.033, tphlh$A$Y = 0.038:0.038:0.038; // path delays (A *> Y) = (tphlh$A$Y, tplhl$A$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module INVX8 (A, Y); input A ; output Y ; not (Y, A); specify // delay parameters specparam tplhl$A$Y = 0.033:0.033:0.033, tphlh$A$Y = 0.038:0.038:0.038; // path delays (A *> Y) = (tphlh$A$Y, tplhl$A$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module LATCH (CLK, D, Q); input CLK ; input D ; output Q ; reg NOTIFIER ; udp_tlat (DS0000, D, CLK, 1'B0, 1'B0, NOTIFIER); not (P0000, DS0000); buf (Q, DS0000); specify // delay parameters specparam tpllh$D$Q = 0.21:0.21:0.21, tphhl$D$Q = 0.24:0.24:0.24, tpllh$CLK$Q = 0.19:0.19:0.19, tplhl$CLK$Q = 0.25:0.25:0.25, tminpwh$CLK = 0.053:0.15:0.25, tsetup_negedge$D$CLK = 0.19:0.19:0.19, thold_negedge$D$CLK = -0.094:-0.094:-0.094, tsetup_posedge$D$CLK = 0.19:0.19:0.19, thold_posedge$D$CLK = -0.094:-0.094:-0.094; // path delays (CLK *> Q) = (tpllh$CLK$Q, tplhl$CLK$Q); (D *> Q) = (tpllh$D$Q, tphhl$D$Q); $setup(negedge D, negedge CLK, tsetup_negedge$D$CLK, NOTIFIER); $hold (negedge D, negedge CLK, thold_negedge$D$CLK, NOTIFIER); $setup(posedge D, negedge CLK, tsetup_posedge$D$CLK, NOTIFIER); $hold (posedge D, negedge CLK, thold_posedge$D$CLK, NOTIFIER); $width(posedge CLK, tminpwh$CLK, 0, NOTIFIER); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module MUX2X1 (A, B, S, Y); input A ; input B ; input S ; output Y ; udp_mux2 (I0_out, B, A, S); not (Y, I0_out); specify // delay parameters specparam tpllh$S$Y = 0.1:0.1:0.1, tplhl$S$Y = 0.099:0.099:0.099, tplhl$A$Y = 0.05:0.05:0.05, tphlh$A$Y = 0.072:0.072:0.072, tplhl$B$Y = 0.055:0.055:0.055, tphlh$B$Y = 0.066:0.066:0.066; // path delays (A *> Y) = (tphlh$A$Y, tplhl$A$Y); (B *> Y) = (tphlh$B$Y, tplhl$B$Y); (S *> Y) = (tpllh$S$Y, tplhl$S$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module NAND2X1 (A, B, Y); input A ; input B ; output Y ; and (I0_out, A, B); not (Y, I0_out); specify // delay parameters specparam tplhl$A$Y = 0.033:0.033:0.033, tphlh$A$Y = 0.054:0.054:0.054, tplhl$B$Y = 0.031:0.031:0.031, tphlh$B$Y = 0.046:0.046:0.046; // path delays (A *> Y) = (tphlh$A$Y, tplhl$A$Y); (B *> Y) = (tphlh$B$Y, tplhl$B$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module NAND3X1 (A, B, C, Y); input A ; input B ; input C ; output Y ; and (I1_out, A, B, C); not (Y, I1_out); specify // delay parameters specparam tplhl$B$Y = 0.039:0.039:0.039, tphlh$B$Y = 0.066:0.066:0.066, tplhl$A$Y = 0.041:0.041:0.041, tphlh$A$Y = 0.077:0.077:0.077, tplhl$C$Y = 0.033:0.033:0.033, tphlh$C$Y = 0.052:0.052:0.052; // path delays (A *> Y) = (tphlh$A$Y, tplhl$A$Y); (B *> Y) = (tphlh$B$Y, tplhl$B$Y); (C *> Y) = (tphlh$C$Y, tplhl$C$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module NOR2X1 (A, B, Y); input A ; input B ; output Y ; or (I0_out, A, B); not (Y, I0_out); specify // delay parameters specparam tplhl$B$Y = 0.038:0.038:0.038, tphlh$B$Y = 0.044:0.044:0.044, tplhl$A$Y = 0.052:0.052:0.052, tphlh$A$Y = 0.049:0.049:0.049; // path delays (A *> Y) = (tphlh$A$Y, tplhl$A$Y); (B *> Y) = (tphlh$B$Y, tplhl$B$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module NOR3X1 (A, B, C, Y); input A ; input B ; input C ; output Y ; or (I1_out, A, B, C); not (Y, I1_out); specify // delay parameters specparam tplhl$B$Y = 0.069:0.069:0.069, tphlh$B$Y = 0.065:0.065:0.065, tplhl$C$Y = 0.049:0.049:0.049, tphlh$C$Y = 0.048:0.048:0.048, tplhl$A$Y = 0.077:0.077:0.077, tphlh$A$Y = 0.07:0.07:0.07; // path delays (A *> Y) = (tphlh$A$Y, tplhl$A$Y); (B *> Y) = (tphlh$B$Y, tplhl$B$Y); (C *> Y) = (tphlh$C$Y, tplhl$C$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module OAI21X1 (A, B, C, Y); input A ; input B ; input C ; output Y ; or (I0_out, A, B); and (I1_out, I0_out, C); not (Y, I1_out); specify // delay parameters specparam tplhl$A$Y = 0.05:0.05:0.05, tphlh$A$Y = 0.066:0.066:0.066, tplhl$B$Y = 0.04:0.04:0.04, tphlh$B$Y = 0.061:0.061:0.061, tplhl$C$Y = 0.03:0.038:0.046, tphlh$C$Y = 0.048:0.049:0.05; // path delays (A *> Y) = (tphlh$A$Y, tplhl$A$Y); (B *> Y) = (tphlh$B$Y, tplhl$B$Y); (C *> Y) = (tphlh$C$Y, tplhl$C$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module OAI22X1 (A, B, C, D, Y); input A ; input B ; input C ; input D ; output Y ; or (I0_out, A, B); or (I1_out, C, D); and (I2_out, I0_out, I1_out); not (Y, I2_out); specify // delay parameters specparam tplhl$D$Y = 0.038:0.047:0.055, tphlh$D$Y = 0.055:0.055:0.056, tplhl$C$Y = 0.044:0.054:0.064, tphlh$C$Y = 0.059:0.059:0.06, tplhl$A$Y = 0.051:0.06:0.07, tphlh$A$Y = 0.075:0.078:0.081, tplhl$B$Y = 0.044:0.052:0.059, tphlh$B$Y = 0.071:0.073:0.076; // path delays (A *> Y) = (tphlh$A$Y, tplhl$A$Y); (B *> Y) = (tphlh$B$Y, tplhl$B$Y); (C *> Y) = (tphlh$C$Y, tplhl$C$Y); (D *> Y) = (tphlh$D$Y, tplhl$D$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module OR2X1 (A, B, Y); input A ; input B ; output Y ; or (Y, A, B); specify // delay parameters specparam tpllh$B$Y = 0.086:0.086:0.086, tphhl$B$Y = 0.081:0.081:0.081, tpllh$A$Y = 0.074:0.074:0.074, tphhl$A$Y = 0.076:0.076:0.076; // path delays (A *> Y) = (tpllh$A$Y, tphhl$A$Y); (B *> Y) = (tpllh$B$Y, tphhl$B$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module OR2X2 (A, B, Y); input A ; input B ; output Y ; or (Y, A, B); specify // delay parameters specparam tpllh$B$Y = 0.1:0.1:0.1, tphhl$B$Y = 0.099:0.099:0.099, tpllh$A$Y = 0.093:0.093:0.093, tphhl$A$Y = 0.094:0.094:0.094; // path delays (A *> Y) = (tpllh$A$Y, tphhl$A$Y); (B *> Y) = (tpllh$B$Y, tphhl$B$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module TBUFX1 (A, EN, Y); input A ; input EN ; output Y ; not (I0_out, A); bufif1 (Y, I0_out, EN); specify // delay parameters specparam tpzh$EN$Y = 0.064:0.064:0.064, tpzl$EN$Y = 0.021:0.021:0.021, tplz$EN$Y = 0.044:0.044:0.044, tphz$EN$Y = 0.059:0.059:0.059, tplhl$A$Y = 0.043:0.043:0.043, tphlh$A$Y = 0.062:0.062:0.062; // path delays (A *> Y) = (tphlh$A$Y, tplhl$A$Y); (EN *> Y) = (0, 0, tplz$EN$Y, tpzh$EN$Y, tphz$EN$Y, tpzl$EN$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module TBUFX2 (A, EN, Y); input A ; input EN ; output Y ; not (I0_out, A); bufif1 (Y, I0_out, EN); specify // delay parameters specparam tplhl$A$Y = 0.045:0.045:0.045, tphlh$A$Y = 0.062:0.062:0.062, tpzh$EN$Y = 0.067:0.067:0.067, tpzl$EN$Y = 0.021:0.021:0.021, tplz$EN$Y = 0.044:0.044:0.044, tphz$EN$Y = 0.06:0.06:0.06; // path delays (A *> Y) = (tphlh$A$Y, tplhl$A$Y); (EN *> Y) = (0, 0, tplz$EN$Y, tpzh$EN$Y, tphz$EN$Y, tpzl$EN$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module XNOR2X1 (A, B, Y); input A ; input B ; output Y ; xor (I0_out, A, B); not (Y, I0_out); specify // delay parameters specparam tpllh$A$Y = 0.085:0.085:0.085, tplhl$A$Y = 0.081:0.081:0.081, tpllh$B$Y = 0.1:0.1:0.1, tplhl$B$Y = 0.089:0.089:0.089; // path delays (A *> Y) = (tpllh$A$Y, tplhl$A$Y); (B *> Y) = (tpllh$B$Y, tplhl$B$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module XOR2X1 (A, B, Y); input A ; input B ; output Y ; xor (Y, A, B); specify // delay parameters specparam tpllh$B$Y = 0.096:0.096:0.096, tplhl$B$Y = 0.091:0.091:0.091, tpllh$A$Y = 0.085:0.085:0.085, tplhl$A$Y = 0.08:0.08:0.08; // path delays (A *> Y) = (tpllh$A$Y, tplhl$A$Y); (B *> Y) = (tpllh$B$Y, tplhl$B$Y); endspecify endmodule `endcelldefine primitive udp_dff (out, in, clk, clr, set, NOTIFIER); output out; input in, clk, clr, set, NOTIFIER; reg out; table // in clk clr set NOT : Qt : Qt+1 // 0 r ? 0 ? : ? : 0 ; // clock in 0 1 r 0 ? ? : ? : 1 ; // clock in 1 1 * 0 ? ? : 1 : 1 ; // reduce pessimism 0 * ? 0 ? : 0 : 0 ; // reduce pessimism ? f ? ? ? : ? : - ; // no changes on negedge clk * b ? ? ? : ? : - ; // no changes when in switches ? ? ? 1 ? : ? : 1 ; // set output ? b 0 * ? : 1 : 1 ; // cover all transistions on set 1 x 0 * ? : 1 : 1 ; // cover all transistions on set ? ? 1 0 ? : ? : 0 ; // reset output ? b * 0 ? : 0 : 0 ; // cover all transistions on clr 0 x * 0 ? : 0 : 0 ; // cover all transistions on clr ? ? ? ? * : ? : x ; // any notifier changed endtable endprimitive // udp_dff primitive udp_tlat (out, in, enable, clr, set, NOTIFIER); output out; input in, enable, clr, set, NOTIFIER; reg out; table // in enable clr set NOT : Qt : Qt+1 // 1 1 0 ? ? : ? : 1 ; // 0 1 ? 0 ? : ? : 0 ; // 1 * 0 ? ? : 1 : 1 ; // reduce pessimism 0 * ? 0 ? : 0 : 0 ; // reduce pessimism * 0 ? ? ? : ? : - ; // no changes when in switches ? ? ? 1 ? : ? : 1 ; // set output ? 0 0 * ? : 1 : 1 ; // cover all transistions on set 1 ? 0 * ? : 1 : 1 ; // cover all transistions on set ? ? 1 0 ? : ? : 0 ; // reset output ? 0 * 0 ? : 0 : 0 ; // cover all transistions on clr 0 ? * 0 ? : 0 : 0 ; // cover all transistions on clr ? ? ? ? * : ? : x ; // any notifier changed endtable endprimitive // udp_tlat primitive udp_rslat (out, clr, set, NOTIFIER); output out; input clr, set, NOTIFIER; reg out; table // clr set NOT : Qt : Qt+1 // ? 1 ? : ? : 1 ; // set output 0 * ? : 1 : 1 ; // cover all transistions on set 1 0 ? : ? : 0 ; // reset output * 0 ? : 0 : 0 ; // cover all transistions on clr ? ? * : ? : x ; // any notifier changed endtable endprimitive // udp_tlat primitive udp_mux2 (out, in0, in1, sel); output out; input in0, in1, sel; table // in0 in1 sel : out // 1 ? 0 : 1 ; 0 ? 0 : 0 ; ? 1 1 : 1 ; ? 0 1 : 0 ; 0 0 x : 0 ; 1 1 x : 1 ; endtable endprimitive // udp_mux2 qflow-1.1.23/tech/osu018/SCN6M_DEEP.09.tech0000664000175000001440000055346412535603240016162 0ustar timuserstech format 29 scmos end version version 2015a description "SCMOS: Submit as technology.lambda: SCN6M_DEEP.09 [to process: TSMC18]" end planes well,w implant,i select,s active,a metal1,m1 metal2,m2 metal3,m3 metal4,m4 metal5,m5 metal6,m6 metali,mi oxide,ox comment xp contact via1,v1 via2,v2 via3,v3 via4,v4 via5,v5 viai,vi fill end types well nwell,nw active nwr well pwell,pw implant n_field_implant,nfi implant p_field_implant,pfi select nselect,ns select pselect,ps active ntransistor,nfet active ptransistor,pfet active diffusion,diff active transistor,fet active ndiffusion,ndif,green active pdiffusion,pdif,brown active ndcontact,ndc active pdcontact,pdc active psubstratepdiff,pohmicdiff,pod,ppdiff,ppd,psd active nsubstratendiff,nohmicdiff,nod,nndiff,nnd,nsd active psubstratepcontact,pohmiccontact,poc,pwcontact,pwc,psc active nsubstratencontact,nohmiccontact,noc,nwcontact,nwc,nsc active nwsd active nwsc active polysilicon,red,poly,p active polycontact,pcontact,polycut,pc active polypplus,pp active polynplus,pn active polyppluscontact,ppcontact,ppc active polynpluscontact,pncontact,pnc contact genericcontact,gcontact,gc metal1 metal1,m1,blue metal1 pseudo_rmetal1,prm1 metal1 rmetal1,rm1 metal1 fillm1,fm1 metal1 m2contact,m2cut,m2c,via1,v1,via metal2 metal2,m2,purple metal2 pseudo_rmetal2,prm2 metal2 rmetal2,rm2 metal2 fillm2,fm2 via1 gv1 metal2 m3contact,m3cut,m3c,via2,v2 metal3 metal3,m3,cyan metal3 pseudo_rmetal3,prm3 metal3 rmetal3,rm3 metal3 fillm3,fm3 via2 gv2 metal3 m4contact,m4cut,m4c,via3,v3 metal4 metal4,m4,yellow metal4 pseudo_rmetal4,prm4 metal4 rmetal4,rm4 metal4 fillm4,fm4 via3 gv3 metal4 m5contact,m5cut,m5c,via4,v4 metal5 metal5,m5 metal5 pseudo_rmetal5,prm5 metal5 rmetal5,rm5 metal5 fillm5,fm5 via4 gv4 metal5 m6contact,m6cut,m6c,via5,v5 metal6 metal6,m6 metal6 pseudo_rmetal6,prm6 metal6 rmetal6,rm6 metal6 fillm6,fm6 via5 gv5 metal6 pad metal6 micontact,micut,mic,viai,vi metali metali,mim,mi mi pseudo_rmetali,prmi mi rmi viai gvi oxide glass active silicide_block,sb active poly_resist,pres active pseudo_rpoly,prp active rpoly,rp active pseudo_rndiffusion,prnd active rndiffusion,rndiff,rnd active pseudo_rpdiffusion,prpd active rpdiffusion,rpdiff,rpd active pseudo_rnwell,prnwell,prnw active rnwell,rnw active pseudo_nwr,pnwr implant filln,fn fill filla,fa fill fillb,fb active fillp,fp active fillapm,fapm active activen_resist,anres active activep_resist,apres xp xp xp m1p xp m2p xp m3p xp m4p xp m5p xp m6p comment comment comment bb end contact pc poly metal1 ppc pp metal1 pnc pn metal1 ndc ndiff metal1 pdc pdiff metal1 nsc nsd metal1 nwsc nwsd metal1 psc psd metal1 m2c metal1 metal2 m3c metal2 metal3 m4c metal3 metal4 m5c metal4 metal5 m6c metal5 metal6 mic metal6 metali stackable pc m2c pm12contact,pm12c stackable ppc m2c ppm12contact,ppm12c stackable pnc m2c pnm12contact,pnm12c stackable pdc m2c pdm12contact,pdm12c stackable psc m2c psm12contact,psm12c,pom12c,pwm12c stackable ndc m2c ndm12contact,ndm12c stackable nsc m2c nsm12contact,nsm12c,nom12c,nwm12c stackable nwsc m2c nwsm12contact,nwsm12c stackable m2c m3c m123contact,m123c stackable m3c m4c m234contact,m234c stackable m4c m5c m345contact,m345c stackable m5c m6c m456contact,m456c end styles styletype mos nwr 54 pnwr 53 nwsd 3 54 nwsc 3 20 32 54 nwell 12 pwell 13 nfi 53 pfi 54 nselect 43 pselect 44 diff 25 tran 2 4 ndiff 2 pdiff 4 nsd 3 psd 5 nfet 6 7 pfet 8 9 ndc 2 20 32 pdc 4 20 32 nsc 3 20 32 psc 5 20 32 poly 1 pp 1 44 pn 1 43 pcontact 1 20 32 gc 32 metal1 20 rm1 20 48 prm1 48 m1p 20 34 fm1 20 34 fp 1 34 fa 32 fb 45 34 fn 45 34 fapm 1 20 21 34 gv1 55 m2contact 20 21 55 metal2 21 rm2 21 48 prm2 48 m2p 21 34 fm2 21 34 gv2 56 m3contact 21 22 56 metal3 22 rm3 22 48 prm3 48 m3p 22 34 fm3 22 34 gv3 57 m4contact 22 23 57 metal4 23 rm4 23 48 prm4 48 m4p 23 34 fm4 23 34 gv4 58 m5contact 23 24 58 metal5 24 rm5 24 48 m5p 24 34 fm5 24 34 prm5 48 gv5 60 m6contact 24 26 60 metal6 26 rm6 26 48 m6p 26 34 fm6 26 34 prm6 48 gvi 61 micontact 26 27 61 mi 27 rmi 27 48 prmi 48 pad 22 23 34 38 glass 34 xp 25 34 sb 10 pres 47 48 rp 47 48 prp 48 anres 2 48 rnd 2 48 prnd 48 apres 4 53 rpd 4 53 prpd 53 rnw 12 53 prnw 54 comment 45 bb 32 error_p 42 error_s 42 error_ps 42 magnet 54 rotate 57 fence 59 end compose compose nfet poly ndiff compose pfet poly pdiff compose nfet pn ndiff compose pfet pp pdiff paint diff nselect ndiff paint diff pselect pdiff compose tran poly diff paint tran nselect nfet paint tran pselect pfet paint psd ns ndiff paint nsd ps pdiff paint ndiff ps psd paint pdiff ns nsd paint pad m1 pad paint pad m2 pad paint pad m2c pad paint pfi nwell nfi paint nfi pwell pfi paint anres nwell apres paint apres pwell anres paint ndc nwell pdc paint nfet nwell pfet paint ndiff nwell pdiff paint psd nwell nsd paint psc nwell nsc paint pdc pwell ndc paint pfet pwell nfet paint pdiff pwell ndiff paint nsd pwell psd paint nsc pwell psc paint pad m3 pad paint pad m4 pad paint pad m5 pad paint pad m6 pad compose pres poly sb paint sb poly pres paint poly sb pres erase pres sb poly compose anres ndiff sb paint sb ndiff anres paint ndiff sb anres erase anres sb ndiff compose apres pdiff sb paint sb pdiff apres paint pdiff sb apres erase apres sb pdiff #CRE/CRM compose rm1 prm1 m1 compose rm2 prm2 m2 compose rm3 prm3 m3 compose rm4 prm4 m4 compose rm5 prm5 m5 compose rm6 prm6 m6 compose rmi prmi mi compose rp prp poly compose rnd prnd ndiff compose rpd prpd pdiff paint nwell rnw space paint nwell nwr space paint nwell prnw space paint poly fp fp paint m1 fm1 fm1 paint m2 fm2 fm2 paint m3 fm3 fm3 paint m4 fm4 fm4 paint m5 fm5 fm5 paint m6 fm6 fm6 end connect nwell,nsc/a,nwsc/a,nsd,nwsd nwell,nsc/a,nwsc/a,nsd,nwsd pwell,psc/a,psd pwell,psc/a,psd m1,fm1,fapm,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,ppc/m1,pnc/m1,m2c/m1 m1,fm1,fapm,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,ppc/m1,pnc/m1,m2c/m1 m2,fm2,fapm,m2c/m2,m3c/m2,m3c/m2 m2,fm2,fapm,m2c/m2,m3c/m2,m3c/m2 m3,fm3,fapm,m3c/m3,m4c/m3,m4c/m3 m3,fm3,fapm,m3c/m3,m4c/m3,m4c/m3 m4,fm4,fapm,m4c/m4,m5c/m4,m5c/m4 m4,fm4,fapm,m4c/m4,m5c/m4,m5c/m4 m5,fm5,fapm,m5c/m5,m6c/m5,m6c/m5 m5,fm5,fapm,m5c/m5,m6c/m5,m6c/m5 m6,fm6,fapm,m6c/m6,mic/m6 m6,fm6,fapm,m6c/m6,mic/m6 mi,mic/mi mi,mic/mi ndiff,nsd,nwsd,ndc/a,nsc/a,nwsc/a,pdiff,psd,pdc/a,psc/a ndiff,nsd,nwsd,ndc/a,nsc/a,nwsc/a,pdiff,psd,pdc/a,psc/a poly,fp,pp,pn,nfet,pfet,fet,fapm,pc/a,ppc/a,pnc/a poly,fp,pp,pn,nfet,pfet,fet,fapm,pc/a,ppc/a,pnc/a gc poly,fp,pp,pn,ndiff,pdiff,nsd,nwsd,psd,m1,fm1,fapm,m2c/m1 gv1 m1,fm1,fapm,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,ppc/m1,pnc/m1,m2,fm2,fapm,m3c/m2 gv2 m2,fm2,fapm,m2c/m2,m3c/m2,m3,fm3,fapm,m4c/m3 gv3 m3,fm3,fapm,m3c/m3,m4c/m3,m4,fm4,fapm,m5c/m4 gv4 m4,fm4,fapm,m4c/m4,m5c/m4,m5,fm5,fapm,m6c/m5 gv5 m5,fm5,fapm,m5c/m5,m6c/m5,m6,fm6,fapm gvi m6,fm6,fapm,m6c/m6,mic/m6,mi pad m1,fm1,m2,fm2,m3,fm3,m4,fm4,m5,fm5,m6,fm6 rm1 prm1 rm2 prm2 rm3 prm3 rm4 prm4 rm5 prm5 rm6 prm6 rmi prmi rnw prnw nwr pnwr rp prp rnd prnd rpd prpd pres sb anres sb apres sb end cifoutput style lambda=0.09(p) scalefactor 9 layer CWN nwell,rnw,nwr,nwsd,nwsc bloat-or pdiff,apres,rpd,pdc/a,pfet * 54 bloat-or nsd,nsc/a * 27 bloat-or nfi * 36 grow 27 shrink 27 labels nwell,rnw,nwr,nwsd,nwsc calma 42 0 layer CWNR nwsd,nwsc,nwr grow 135 calma 91 0 layer CWND nwr labels nwr calma 92 0 layer CAA nwsd,nwsc,nwr grow 108 labels nwsd,nwsc calma 43 0 layer CSN bloat-or nwsd,nwsc * 72 nwr 0 calma 43 0 templayer TNWR bloat-or nwr * 108 nwsd,nwsc 45 templayer TCSB nwsd,nwsc grow 27 and-not TNWR layer CSB nwsd,nwsc,nwr grow 135 and-not TCSB calma 29 0 layer CRNW pnwr labels pnwr calma 93 0 layer CWP pwell bloat-or ndiff,anres,rnd,ndc/a,nfet * 54 bloat-or psd,psc/a * 27 bloat-or pfi * 36 grow 27 shrink 27 and-not CWN labels pwell calma 41 0 templayer TNS ndiff,anres,rnd,ndc/a,nsd,nsc/a and gc grow 9 or ndc/m1,nsc/m1,nwsc/m1 grow 5 or nselect templayer TPS pdiff,apres,rpd,pdc/a,psd,psc/a and gc grow 9 or pdc/m1,psc/m1 grow 5 or pselect #we give priority to selects autogenerated around diffusions (vrs. ohmics) #XDP = (pdiff*18) Or ps #XDN = (ndiff*18) Or ns #FSP = ((pdiff*18,psc*18) Or XDP And-Not XDN Or ps shrink-grow #FSN = ((ndiff*18,nsc*18) Or XDN And-Not FDP Or ns shrink-grow #CSN = FSN #CSP = FSP #diffusion auto-nselect (will have priority) templayer XDN bloat-or ndiff,anres,rnd,ndc/a * 18 psd,psc/a 0 bloat-or pn * 09 pp 0 or TNS #diffusion auto-pselect (will have priority) templayer XDP bloat-or pdiff,apres,rpd,pdc/a * 18 nsd,nsc/a 0 bloat-or pp * 09 pn 0 or TPS #final pselect templayer FSP bloat-or pdiff,apres,rpd,pfet,psd,pdc/a,psc/a,pfet * 18 ndiff,anres,rnd,ndc/a,nsd,nsc/a,nfet 0 or XDP #give diff nselect priority and-not XDN or TPS shrink 14 grow 14 grow 14 shrink 14 #final nselect templayer FSN bloat-or ndiff,anres,rnd,nfet,nsd,nwsd,ndc/a,nsc/a,nwsc/a,nfet * 18 pdiff,apres,rpd,pdc/a,psd,psc/a,pfet 0 and-not nwr or XDN #never conflict with final pselect and-not FSP #drawn select always goes or TNS shrink 14 grow 14 grow 14 shrink 14 layer CSN FSN calma 45 0 layer CSP FSP calma 44 0 layer CAA diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a,pfet,pfet,fet labels diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a,pfet,pfet,fet calma 43 0 layer CCA nwsc/m1 squares 18 18 36 calma 48 0 layer CCA ndc/m1,nsc/m1 squares 09 18 36 calma 48 0 layer CCA pdc/m1,psc/m1 squares 09 18 36 calma 48 0 layer CPG poly,pp,pn,pres,rp,nfet,pfet,fet,pc/a,ppc/a,pnc/a labels poly,pp,pn,pres,rp,nfet,pfet,fet,pc/a,ppc/a,pnc/a calma 46 0 layer CCP pc/m1,ppc/m1,pnc/m1 squares 09 18 36 calma 47 0 layer CCC gc squares 0 18 36 calma 25 0 layer CV1 m2c/m1 squares 10 20 20 calma 50 0 layer CV1 gv1 squares 0 20 20 calma 50 0 layer CV2 m3c/m2 squares 10 20 20 calma 61 0 layer CV2 gv2 squares 0 20 20 calma 61 0 layer CV3 m4c/m3 squares 10 20 20 calma 30 0 layer CV3 gv3 squares 0 20 20 calma 30 0 layer CV4 m5c/m4 squares 10 20 20 calma 32 0 layer CV4 gv4 squares 0 20 20 calma 32 0 layer CV5 m6c/m5 squares 10 30 30 calma 36 0 layer CV5 gv5 squares 0 30 30 calma 36 0 layer CV5 mic/mi squares 30 30 210 calma 36 0 layer CV5 gvi squares 0 30 210 calma 36 0 templayer XPAD1 pad shrink 54 templayer XPAD2 XPAD1 shrink 54 layer CM6 pad labels pad calma 37 0 layer CV5 XPAD2 squares 09 36 72 calma 36 0 layer CM5 pad labels pad calma 33 0 layer CV4 XPAD2 squares 72 27 81 calma 32 0 layer CM4 pad labels pad calma 31 0 layer CV3 XPAD2 squares 18 27 81 calma 30 0 layer CM3 pad labels pad calma 62 0 layer CV2 XPAD2 squares 72 27 81 calma 61 0 layer CM2 pad labels pad calma 51 0 layer CV1 XPAD2 squares 18 27 81 calma 50 0 layer CM1 pad calma 49 0 layer CM1 m1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,ppc/m1,pnc/m1,m2c/m1 labels m1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,ppc/m1,pnc/m1,m2c/m1 calma 49 0 layer CM2 m2,rm2,m2c/m2,m3c/m2,m3c/m2 labels m2,rm2,m2c/m2,m3c/m2,m3c/m2 calma 51 0 layer CMFP m1p labels m1p calma 81 0 layer CMSP m2p labels m2p calma 82 0 layer 100 fp labels fp calma 100 0 layer 101 fm1 labels fm1 calma 101 0 layer 102 fm2 labels fm2 calma 102 0 layer 103 fm3 labels fm3 calma 103 0 layer 104 fm4 labels fm4 calma 104 0 layer 105 fm5 labels fm5 calma 105 0 layer 106 fm6 labels fm6 calma 106 0 layer 109 fa or fb squares 0 207 36 labels fa calma 109 0 layer 119 fn calma 119 0 layer 110 fapm labels fapm calma 110 0 # layer CPG fp layer CPG fp,fapm squares 0 207 36 labels fp calma 46 0 # layer CM1 fm1 layer CM1 fm1,fapm squares 0 207 36 labels fm1 calma 49 0 # layer CM2 fm2 layer CM2 fm2,fapm squares 0 207 36 labels fm2 calma 51 0 # layer CM3 fm3 layer CM3 fm3,fapm squares 0 207 36 labels fm3 calma 62 0 layer CM3 m3,rm3,m3c/m3,m4c/m3,m4c/m3 labels m3,rm3,m3c/m3,m4c/m3,m4c/m3 calma 62 0 layer CMTP m3p labels m3p calma 83 0 layer CM4 m4,rm4,m4c/m4,m5c/m4,m5c/m4 labels m4,rm4,m4c/m4,m5c/m4,m5c/m4 calma 31 0 layer CMQP m4p labels m4p calma 84 0 # layer CM4 fm4 layer CM4 fm4,fapm squares 0 207 36 labels fm4 calma 31 0 layer CM5 m5,rm5,m5c/m5,m6c/m5,m6c/m5 labels m5,rm5,m5c/m5,m6c/m5,m6c/m5 calma 33 0 layer CMPP m5p labels m5p calma 85 0 # layer CM5 fm5 layer CM5 fm5,fapm squares 0 207 36 labels fm5 calma 33 0 layer CM6 m6,rm6,m6c/m6,mic/m6 labels m6,rm6,m6c/m6,mic/m6 calma 37 0 layer CM6P m6p labels m6p calma 85 0 # layer CM6 fm6 layer CM6 fm6,fapm squares 0 207 36 labels fm6 calma 37 0 layer CTM mi,mic/mi labels mi,mic/mi calma 35 0 layer COG pad shrink 504 labels pad calma 52 0 layer COG glass labels glass calma 52 0 layer CFI nfi,pfi labels nfi,pfi calma 27 0 layer CSB sb,pres,anres,apres labels sb,pres,anres,apres calma 29 0 #CRE/CRM layer CRW rnw,prnw labels rnw,prnw calma 65 0 layer CRG rp,prp,pres labels rp,prp,pres calma 67 0 layer CRD rnd,rpd,prnd,prpd,anres,apres labels rnd,rpd,prnd,prpd,anres,apres calma 66 0 layer CRE rnw,rp,rnd,rpd,pres,anres,apres labels rnw,rp,rnd,rpd,pres,anres,apres calma 64 0 layer CRF rm1,prm1 labels rm1,prm1 calma 71 0 layer CRS rm2,prm2 labels rm2,prm2 calma 72 0 layer CRT rm3,prm3 labels rm3,prm3 calma 73 0 layer CRQ rm4,prm4 labels rm4,prm4 calma 74 0 layer CRP rm5,prm5 labels rm5,prm5 calma 75 0 layer CR6 rm6,prm6 labels rm6,prm6 calma 76 0 layer CRI rmi,prmi labels rmi,prmi calma 79 0 #CRE/CRM layer CRM rm1,prm1,rm2,prm2,rm3,prm3,rm4,prm4,rm5,prm5,rm6,prm6,rmi,prmi #CRE/CRM calma 70 0 layer CX comment labels comment calma 63 0 layer XP pad,xp labels pad,xp calma 26 0 style fill-only scalefactor 9 layer 100 fp calma 100 0 layer 101 fm1 calma 101 0 layer 102 fm2 calma 102 0 layer 103 fm3 calma 103 0 layer 104 fm4 calma 104 0 layer 105 fm5 calma 105 0 layer 106 fm6 calma 106 0 layer 109 fa or fb calma 109 0 layer 119 fn calma 119 0 style fapm-boxes # this output style creates fill boxes automatically (to meet minimum # density requirements for poly and metal layers) 5 microns outside of # drawn layout IF: 1. you have a flattened version of your chip # 2. over which you paint the special fill layer 'fa', preferably with # a size that is a multiple of 23 + n * (23 + 4), 3. set 'cif # ostype fapm-boxes' and cif out to a file (this actually creates the # fill boxes on cif/strm layer '110' using the magic 'squares' # command), 4. cif in the resulting file (which creates boxes on magic # layer 'fapm') and place this cell onto your chip (and verify absence # of drc errors or shorts), then 5. cif out under your regular cif out # style, where the 'fapm' layer creates fill boxes on poly and all # metal layers. scalefactor 09 calmaonly templayer CRIT fapm,fn,diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a,pfet,pfet,fet,poly,pp,pn,pres,rp,nfet,pfet,fet,pc/a,ppc/a,pnc/a or fm1,m1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,ppc/m1,pnc/m1,m2c/m1 or fm2,m2,rm2,m2c/m2,m3c/m2,m3c/m2 or fm3,m3,rm3,m3c/m3,m4c/m3,m4c/m3 or fm4,m4,rm4,m4c/m4,m5c/m4,m5c/m4 or fm5,m5,rm5,m5c/m5,m6c/m5,m6c/m5 or fm6,m6,rm6,m6c/m6,mic/m6 or glass,pad grow 500 and fa layer 110 fa squares 0 207 36 and-not CRIT shrink 98.5 grow 98.5 or fapm labels fapm calma 110 0 style fapm-stripes scalefactor 9 # this output style creates the above layer 110 as stripes for reduced size # HOWEVER it requires each 'fa' box to first be an exact multiple as above # and then *replacing* the left side (1-lambda wide) stripe of each 'fa' box # to be a 1-lambda wide layer 'fb' box -- else you won't get strips! templayer CRIT fapm,fn,diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a,pfet,pfet,fet,poly,pp,pn,pres,rp,nfet,pfet,fet,pc/a,ppc/a,pnc/a or fm1,m1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,ppc/m1,pnc/m1,m2c/m1 or fm2,m2,rm2,m2c/m2,m3c/m2,m3c/m2 or fm3,m3,rm3,m3c/m3,m4c/m3,m4c/m3 or fm4,m4,rm4,m4c/m4,m5c/m4,m5c/m4 or fm5,m5,rm5,m5c/m5,m6c/m5,m6c/m5 or fm6,m6,rm6,m6c/m6,mic/m6 or glass,pad grow 500 and fa templayer FB fa or fb squares 0 207 36 and-not CRIT layer 110 fa squares 0 207 36 and-not CRIT or FB shrink 98.5 grow 98.5 or fapm labels fapm calma 110 0 style lambda=0.09(cp) scalefactor 9 layer CWN nwell,rnw,nwr,nwsd,nwsc bloat-or pdiff,apres,rpd,pdc/a,pfet * 54 bloat-or nsd,nsc/a * 27 bloat-or nfi * 36 grow 27 shrink 27 labels nwell,rnw,nwr,nwsd,nwsc calma 42 0 layer CWNR nwsd,nwsc,nwr grow 135 calma 91 0 layer CWND nwr labels nwr calma 92 0 layer CAA nwsd,nwsc,nwr grow 108 labels nwsd,nwsc calma 43 0 layer CSN bloat-or nwsd,nwsc * 72 nwr 0 calma 43 0 templayer TNWR bloat-or nwr * 108 nwsd,nwsc 45 templayer TCSB nwsd,nwsc grow 27 and-not TNWR layer CSB nwsd,nwsc,nwr grow 135 and-not TCSB calma 29 0 layer CRNW pnwr labels pnwr calma 93 0 layer CWP pwell bloat-or ndiff,anres,rnd,ndc/a,nfet * 54 bloat-or psd,psc/a * 27 bloat-or pfi * 36 grow 27 shrink 27 and-not CWN labels pwell calma 41 0 templayer TNS ndiff,anres,rnd,ndc/a,nsd,nsc/a and gc grow 9 or ndc/m1,nsc/m1,nwsc/m1 grow 5 or nselect templayer TPS pdiff,apres,rpd,pdc/a,psd,psc/a and gc grow 9 or pdc/m1,psc/m1 grow 5 or pselect #we give priority to selects autogenerated around diffusions (vrs. ohmics) #XDP = (pdiff*18) Or ps #XDN = (ndiff*18) Or ns #FSP = ((pdiff*18,psc*18) Or XDP And-Not XDN Or ps shrink-grow #FSN = ((ndiff*18,nsc*18) Or XDN And-Not FDP Or ns shrink-grow #CSN = FSN #CSP = FSP #diffusion auto-nselect (will have priority) templayer XDN bloat-or ndiff,anres,rnd,ndc/a * 18 psd,psc/a 0 bloat-or pn * 09 pp 0 or TNS #diffusion auto-pselect (will have priority) templayer XDP bloat-or pdiff,apres,rpd,pdc/a * 18 nsd,nsc/a 0 bloat-or pp * 09 pn 0 or TPS #final pselect templayer FSP bloat-or pdiff,apres,rpd,pfet,psd,pdc/a,psc/a,pfet * 18 ndiff,anres,rnd,ndc/a,nsd,nsc/a,nfet 0 or XDP #give diff nselect priority and-not XDN or TPS shrink 14 grow 14 grow 14 shrink 14 #final nselect templayer FSN bloat-or ndiff,anres,rnd,nfet,nsd,nwsd,ndc/a,nsc/a,nwsc/a,nfet * 18 pdiff,apres,rpd,pdc/a,psd,psc/a,pfet 0 and-not nwr or XDN #never conflict with final pselect and-not FSP #drawn select always goes or TNS shrink 14 grow 14 grow 14 shrink 14 layer CSN FSN calma 45 0 layer CSP FSP calma 44 0 layer CAA diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a,pfet,pfet,fet labels diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a,pfet,pfet,fet calma 43 0 layer CCC nwsc/m1 squares 18 18 36 calma 25 0 layer CCC ndc/m1,nsc/m1 squares 09 18 36 calma 25 0 layer CCC pdc/m1,psc/m1 squares 09 18 36 calma 25 0 layer CPG poly,pp,pn,pres,rp,nfet,pfet,fet,pc/a,ppc/a,pnc/a labels poly,pp,pn,pres,rp,nfet,pfet,fet,pc/a,ppc/a,pnc/a calma 46 0 layer CCC pc/m1,ppc/m1,pnc/m1 squares 09 18 36 calma 25 0 layer CCC gc squares 0 18 36 calma 25 0 layer CV1 m2c/m1 squares 09 27 27 calma 50 0 layer CV1 gv1 squares 0 27 27 calma 50 0 layer CV2 m3c/m2 squares 09 27 27 calma 61 0 layer CV2 gv2 squares 0 27 27 calma 61 0 layer CV3 m4c/m3 squares 09 27 27 calma 30 0 layer CV3 gv3 squares 0 27 27 calma 30 0 layer CV4 m5c/m4 squares 09 27 27 calma 32 0 layer CV4 gv4 squares 0 27 27 calma 32 0 layer CV5 m6c/m5 squares 18 36 36 calma 36 0 layer CV5 gv5 squares 0 36 36 calma 36 0 layer CV5 mic/mi squares 27 36 207 calma 36 0 layer CV5 gvi squares 0 36 207 calma 36 0 templayer XPAD1 pad shrink 54 templayer XPAD2 XPAD1 shrink 54 layer CM6 pad labels pad calma 37 0 layer CV5 XPAD2 squares 09 36 72 calma 36 0 layer CM5 pad labels pad calma 33 0 layer CV4 XPAD2 squares 72 27 81 calma 32 0 layer CM4 pad labels pad calma 31 0 layer CV3 XPAD2 squares 18 27 81 calma 30 0 layer CM3 pad labels pad calma 62 0 layer CV2 XPAD2 squares 72 27 81 calma 61 0 layer CM2 pad labels pad calma 51 0 layer CV1 XPAD2 squares 18 27 81 calma 50 0 layer CM1 pad calma 49 0 layer CM1 m1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,ppc/m1,pnc/m1,m2c/m1 labels m1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,ppc/m1,pnc/m1,m2c/m1 calma 49 0 layer CM2 m2,rm2,m2c/m2,m3c/m2,m3c/m2 labels m2,rm2,m2c/m2,m3c/m2,m3c/m2 calma 51 0 layer CMFP m1p labels m1p calma 81 0 layer CMSP m2p labels m2p calma 82 0 layer 100 fp labels fp calma 100 0 layer 101 fm1 labels fm1 calma 101 0 layer 102 fm2 labels fm2 calma 102 0 layer 103 fm3 labels fm3 calma 103 0 layer 104 fm4 labels fm4 calma 104 0 layer 105 fm5 labels fm5 calma 105 0 layer 106 fm6 labels fm6 calma 106 0 layer 109 fa or fb squares 0 207 36 labels fa calma 109 0 layer 119 fn calma 119 0 layer 110 fapm labels fapm calma 110 0 # layer CPG fp layer CPG fp,fapm squares 0 207 36 labels fp calma 46 0 # layer CM1 fm1 layer CM1 fm1,fapm squares 0 207 36 labels fm1 calma 49 0 # layer CM2 fm2 layer CM2 fm2,fapm squares 0 207 36 labels fm2 calma 51 0 # layer CM3 fm3 layer CM3 fm3,fapm squares 0 207 36 labels fm3 calma 62 0 layer CM3 m3,rm3,m3c/m3,m4c/m3,m4c/m3 labels m3,rm3,m3c/m3,m4c/m3,m4c/m3 calma 62 0 layer CMTP m3p labels m3p calma 83 0 layer CM4 m4,rm4,m4c/m4,m5c/m4,m5c/m4 labels m4,rm4,m4c/m4,m5c/m4,m5c/m4 calma 31 0 layer CMQP m4p labels m4p calma 84 0 # layer CM4 fm4 layer CM4 fm4,fapm squares 0 207 36 labels fm4 calma 31 0 layer CM5 m5,rm5,m5c/m5,m6c/m5,m6c/m5 labels m5,rm5,m5c/m5,m6c/m5,m6c/m5 calma 33 0 layer CMPP m5p labels m5p calma 85 0 # layer CM5 fm5 layer CM5 fm5,fapm squares 0 207 36 labels fm5 calma 33 0 layer CM6 m6,rm6,m6c/m6,mic/m6 labels m6,rm6,m6c/m6,mic/m6 calma 37 0 layer CM6P m6p labels m6p calma 85 0 # layer CM6 fm6 layer CM6 fm6,fapm squares 0 207 36 labels fm6 calma 37 0 layer CTM mi,mic/mi labels mi,mic/mi calma 35 0 layer COG pad shrink 504 labels pad calma 52 0 layer COG glass labels glass calma 52 0 layer CFI nfi,pfi labels nfi,pfi calma 27 0 layer CSB sb,pres,anres,apres labels sb,pres,anres,apres calma 29 0 #CRE/CRM layer CRW rnw,prnw labels rnw,prnw calma 65 0 layer CRG rp,prp,pres labels rp,prp,pres calma 67 0 layer CRD rnd,rpd,prnd,prpd,anres,apres labels rnd,rpd,prnd,prpd,anres,apres calma 66 0 layer CRE rnw,rp,rnd,rpd,pres,anres,apres labels rnw,rp,rnd,rpd,pres,anres,apres calma 64 0 layer CRF rm1,prm1 labels rm1,prm1 calma 71 0 layer CRS rm2,prm2 labels rm2,prm2 calma 72 0 layer CRT rm3,prm3 labels rm3,prm3 calma 73 0 layer CRQ rm4,prm4 labels rm4,prm4 calma 74 0 layer CRP rm5,prm5 labels rm5,prm5 calma 75 0 layer CR6 rm6,prm6 labels rm6,prm6 calma 76 0 layer CRI rmi,prmi labels rmi,prmi calma 79 0 #CRE/CRM layer CRM rm1,prm1,rm2,prm2,rm3,prm3,rm4,prm4,rm5,prm5,rm6,prm6,rmi,prmi #CRE/CRM calma 70 0 layer CX comment labels comment calma 63 0 layer XP pad,xp labels pad,xp calma 26 0 style lambda=0.09(c) scalefactor 9 layer CWN nwell,rnw,nwr,nwsd,nwsc bloat-or pdiff,apres,rpd,pdc/a,pfet * 54 bloat-or nsd,nsc/a * 27 bloat-or nfi * 36 grow 27 shrink 27 labels nwell,rnw,nwr,nwsd,nwsc calma 42 0 layer CWNR nwsd,nwsc,nwr grow 135 calma 91 0 layer CWND nwr labels nwr calma 92 0 layer CAA nwsd,nwsc,nwr grow 108 labels nwsd,nwsc calma 43 0 layer CSN bloat-or nwsd,nwsc * 72 nwr 0 calma 43 0 templayer TNWR bloat-or nwr * 108 nwsd,nwsc 45 templayer TCSB nwsd,nwsc grow 27 and-not TNWR layer CSB nwsd,nwsc,nwr grow 135 and-not TCSB calma 29 0 layer CRNW pnwr labels pnwr calma 93 0 templayer TNS ndiff,anres,rnd,ndc/a,nsd,nsc/a and gc grow 9 or ndc/m1,nsc/m1,nwsc/m1 grow 5 or nselect templayer TPS pdiff,apres,rpd,pdc/a,psd,psc/a and gc grow 9 or pdc/m1,psc/m1 grow 5 or pselect #we give priority to selects autogenerated around diffusions (vrs. ohmics) #XDP = (pdiff*18) Or ps #XDN = (ndiff*18) Or ns #FSP = ((pdiff*18,psc*18) Or XDP And-Not XDN Or ps shrink-grow #FSN = ((ndiff*18,nsc*18) Or XDN And-Not FDP Or ns shrink-grow #CSN = FSN #CSP = FSP #diffusion auto-nselect (will have priority) templayer XDN bloat-or ndiff,anres,rnd,ndc/a * 18 psd,psc/a 0 bloat-or pn * 09 pp 0 or TNS #diffusion auto-pselect (will have priority) templayer XDP bloat-or pdiff,apres,rpd,pdc/a * 18 nsd,nsc/a 0 bloat-or pp * 09 pn 0 or TPS #final pselect templayer FSP bloat-or pdiff,apres,rpd,pfet,psd,pdc/a,psc/a,pfet * 18 ndiff,anres,rnd,ndc/a,nsd,nsc/a,nfet 0 or XDP #give diff nselect priority and-not XDN or TPS shrink 14 grow 14 grow 14 shrink 14 #final nselect templayer FSN bloat-or ndiff,anres,rnd,nfet,nsd,nwsd,ndc/a,nsc/a,nwsc/a,nfet * 18 pdiff,apres,rpd,pdc/a,psd,psc/a,pfet 0 and-not nwr or XDN #never conflict with final pselect and-not FSP #drawn select always goes or TNS shrink 14 grow 14 grow 14 shrink 14 layer CSN FSN calma 45 0 layer CSP FSP calma 44 0 layer CAA diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a,pfet,pfet,fet labels diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a,pfet,pfet,fet calma 43 0 layer CCC nwsc/m1 squares 18 18 36 calma 25 0 layer CCC ndc/m1,nsc/m1 squares 09 18 36 calma 25 0 layer CCC pdc/m1,psc/m1 squares 09 18 36 calma 25 0 layer CPG poly,pp,pn,pres,rp,nfet,pfet,fet,pc/a,ppc/a,pnc/a labels poly,pp,pn,pres,rp,nfet,pfet,fet,pc/a,ppc/a,pnc/a calma 46 0 layer CCC pc/m1,ppc/m1,pnc/m1 squares 09 18 36 calma 25 0 layer CCC gc squares 0 18 36 calma 25 0 layer CV1 m2c/m1 squares 09 27 27 calma 50 0 layer CV1 gv1 squares 0 27 27 calma 50 0 layer CV2 m3c/m2 squares 09 27 27 calma 61 0 layer CV2 gv2 squares 0 27 27 calma 61 0 layer CV3 m4c/m3 squares 09 27 27 calma 30 0 layer CV3 gv3 squares 0 27 27 calma 30 0 layer CV4 m5c/m4 squares 09 27 27 calma 32 0 layer CV4 gv4 squares 0 27 27 calma 32 0 layer CV5 m6c/m5 squares 18 36 36 calma 36 0 layer CV5 gv5 squares 0 36 36 calma 36 0 layer CV5 mic/mi squares 27 36 207 calma 36 0 layer CV5 gvi squares 0 36 207 calma 36 0 templayer XPAD1 pad shrink 54 templayer XPAD2 XPAD1 shrink 54 layer CM6 pad labels pad calma 37 0 layer CV5 XPAD2 squares 09 36 72 calma 36 0 layer CM5 pad labels pad calma 33 0 layer CV4 XPAD2 squares 72 27 81 calma 32 0 layer CM4 pad labels pad calma 31 0 layer CV3 XPAD2 squares 18 27 81 calma 30 0 layer CM3 pad labels pad calma 62 0 layer CV2 XPAD2 squares 72 27 81 calma 61 0 layer CM2 pad labels pad calma 51 0 layer CV1 XPAD2 squares 18 27 81 calma 50 0 layer CM1 pad calma 49 0 layer CM1 m1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,ppc/m1,pnc/m1,m2c/m1 labels m1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,ppc/m1,pnc/m1,m2c/m1 calma 49 0 layer CM2 m2,rm2,m2c/m2,m3c/m2,m3c/m2 labels m2,rm2,m2c/m2,m3c/m2,m3c/m2 calma 51 0 layer CMFP m1p labels m1p calma 81 0 layer CMSP m2p labels m2p calma 82 0 layer 100 fp labels fp calma 100 0 layer 101 fm1 labels fm1 calma 101 0 layer 102 fm2 labels fm2 calma 102 0 layer 103 fm3 labels fm3 calma 103 0 layer 104 fm4 labels fm4 calma 104 0 layer 105 fm5 labels fm5 calma 105 0 layer 106 fm6 labels fm6 calma 106 0 layer 109 fa or fb squares 0 207 36 labels fa calma 109 0 layer 119 fn calma 119 0 layer 110 fapm labels fapm calma 110 0 # layer CPG fp layer CPG fp,fapm squares 0 207 36 labels fp calma 46 0 # layer CM1 fm1 layer CM1 fm1,fapm squares 0 207 36 labels fm1 calma 49 0 # layer CM2 fm2 layer CM2 fm2,fapm squares 0 207 36 labels fm2 calma 51 0 # layer CM3 fm3 layer CM3 fm3,fapm squares 0 207 36 labels fm3 calma 62 0 layer CM3 m3,rm3,m3c/m3,m4c/m3,m4c/m3 labels m3,rm3,m3c/m3,m4c/m3,m4c/m3 calma 62 0 layer CMTP m3p labels m3p calma 83 0 layer CM4 m4,rm4,m4c/m4,m5c/m4,m5c/m4 labels m4,rm4,m4c/m4,m5c/m4,m5c/m4 calma 31 0 layer CMQP m4p labels m4p calma 84 0 # layer CM4 fm4 layer CM4 fm4,fapm squares 0 207 36 labels fm4 calma 31 0 layer CM5 m5,rm5,m5c/m5,m6c/m5,m6c/m5 labels m5,rm5,m5c/m5,m6c/m5,m6c/m5 calma 33 0 layer CMPP m5p labels m5p calma 85 0 # layer CM5 fm5 layer CM5 fm5,fapm squares 0 207 36 labels fm5 calma 33 0 layer CM6 m6,rm6,m6c/m6,mic/m6 labels m6,rm6,m6c/m6,mic/m6 calma 37 0 layer CM6P m6p labels m6p calma 85 0 # layer CM6 fm6 layer CM6 fm6,fapm squares 0 207 36 labels fm6 calma 37 0 layer CTM mi,mic/mi labels mi,mic/mi calma 35 0 layer COG pad shrink 504 labels pad calma 52 0 layer COG glass labels glass calma 52 0 layer CFI nfi,pfi labels nfi,pfi calma 27 0 layer CSB sb,pres,anres,apres labels sb,pres,anres,apres calma 29 0 #CRE/CRM layer CRW rnw,prnw labels rnw,prnw calma 65 0 layer CRG rp,prp,pres labels rp,prp,pres calma 67 0 layer CRD rnd,rpd,prnd,prpd,anres,apres labels rnd,rpd,prnd,prpd,anres,apres calma 66 0 layer CRE rnw,rp,rnd,rpd,pres,anres,apres labels rnw,rp,rnd,rpd,pres,anres,apres calma 64 0 layer CRF rm1,prm1 labels rm1,prm1 calma 71 0 layer CRS rm2,prm2 labels rm2,prm2 calma 72 0 layer CRT rm3,prm3 labels rm3,prm3 calma 73 0 layer CRQ rm4,prm4 labels rm4,prm4 calma 74 0 layer CRP rm5,prm5 labels rm5,prm5 calma 75 0 layer CR6 rm6,prm6 labels rm6,prm6 calma 76 0 layer CRI rmi,prmi labels rmi,prmi calma 79 0 #CRE/CRM layer CRM rm1,prm1,rm2,prm2,rm3,prm3,rm4,prm4,rm5,prm5,rm6,prm6,rmi,prmi #CRE/CRM calma 70 0 layer CX comment labels comment calma 63 0 layer XP pad,xp labels pad,xp calma 26 0 style lambda=0.09() scalefactor 9 layer CWN nwell,rnw,nwr,nwsd,nwsc bloat-or pdiff,apres,rpd,pdc/a,pfet * 54 bloat-or nsd,nsc/a * 27 bloat-or nfi * 36 grow 27 shrink 27 labels nwell,rnw,nwr,nwsd,nwsc calma 42 0 layer CWNR nwsd,nwsc,nwr grow 135 calma 91 0 layer CWND nwr labels nwr calma 92 0 layer CAA nwsd,nwsc,nwr grow 108 labels nwsd,nwsc calma 43 0 layer CSN bloat-or nwsd,nwsc * 72 nwr 0 calma 43 0 templayer TNWR bloat-or nwr * 108 nwsd,nwsc 45 templayer TCSB nwsd,nwsc grow 27 and-not TNWR layer CSB nwsd,nwsc,nwr grow 135 and-not TCSB calma 29 0 layer CRNW pnwr labels pnwr calma 93 0 templayer TNS ndiff,anres,rnd,ndc/a,nsd,nsc/a and gc grow 9 or ndc/m1,nsc/m1,nwsc/m1 grow 5 or nselect templayer TPS pdiff,apres,rpd,pdc/a,psd,psc/a and gc grow 9 or pdc/m1,psc/m1 grow 5 or pselect #we give priority to selects autogenerated around diffusions (vrs. ohmics) #XDP = (pdiff*18) Or ps #XDN = (ndiff*18) Or ns #FSP = ((pdiff*18,psc*18) Or XDP And-Not XDN Or ps shrink-grow #FSN = ((ndiff*18,nsc*18) Or XDN And-Not FDP Or ns shrink-grow #CSN = FSN #CSP = FSP #diffusion auto-nselect (will have priority) templayer XDN bloat-or ndiff,anres,rnd,ndc/a * 18 psd,psc/a 0 bloat-or pn * 09 pp 0 or TNS #diffusion auto-pselect (will have priority) templayer XDP bloat-or pdiff,apres,rpd,pdc/a * 18 nsd,nsc/a 0 bloat-or pp * 09 pn 0 or TPS #final pselect templayer FSP bloat-or pdiff,apres,rpd,pfet,psd,pdc/a,psc/a,pfet * 18 ndiff,anres,rnd,ndc/a,nsd,nsc/a,nfet 0 or XDP #give diff nselect priority and-not XDN or TPS shrink 14 grow 14 grow 14 shrink 14 #final nselect templayer FSN bloat-or ndiff,anres,rnd,nfet,nsd,nwsd,ndc/a,nsc/a,nwsc/a,nfet * 18 pdiff,apres,rpd,pdc/a,psd,psc/a,pfet 0 and-not nwr or XDN #never conflict with final pselect and-not FSP #drawn select always goes or TNS shrink 14 grow 14 grow 14 shrink 14 layer CSN FSN calma 45 0 layer CSP FSP calma 44 0 layer CAA diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a,pfet,pfet,fet labels diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a,pfet,pfet,fet calma 43 0 layer CCA nwsc/m1 squares 18 18 36 calma 48 0 layer CCA ndc/m1,nsc/m1 squares 09 18 36 calma 48 0 layer CCA pdc/m1,psc/m1 squares 09 18 36 calma 48 0 layer CPG poly,pp,pn,pres,rp,nfet,pfet,fet,pc/a,ppc/a,pnc/a labels poly,pp,pn,pres,rp,nfet,pfet,fet,pc/a,ppc/a,pnc/a calma 46 0 layer CCP pc/m1,ppc/m1,pnc/m1 squares 09 18 36 calma 47 0 layer CCC gc squares 0 18 36 calma 25 0 layer CV1 m2c/m1 squares 09 27 27 calma 50 0 layer CV1 gv1 squares 0 27 27 calma 50 0 layer CV2 m3c/m2 squares 09 27 27 calma 61 0 layer CV2 gv2 squares 0 27 27 calma 61 0 layer CV3 m4c/m3 squares 09 27 27 calma 30 0 layer CV3 gv3 squares 0 27 27 calma 30 0 layer CV4 m5c/m4 squares 09 27 27 calma 32 0 layer CV4 gv4 squares 0 27 27 calma 32 0 layer CV5 m6c/m5 squares 18 36 36 calma 36 0 layer CV5 gv5 squares 0 36 36 calma 36 0 layer CV5 mic/mi squares 27 36 207 calma 36 0 layer CV5 gvi squares 0 36 207 calma 36 0 templayer XPAD1 pad shrink 54 templayer XPAD2 XPAD1 shrink 54 layer CM6 pad labels pad calma 37 0 layer CV5 XPAD2 squares 09 36 72 calma 36 0 layer CM5 pad labels pad calma 33 0 layer CV4 XPAD2 squares 72 27 81 calma 32 0 layer CM4 pad labels pad calma 31 0 layer CV3 XPAD2 squares 18 27 81 calma 30 0 layer CM3 pad labels pad calma 62 0 layer CV2 XPAD2 squares 72 27 81 calma 61 0 layer CM2 pad labels pad calma 51 0 layer CV1 XPAD2 squares 18 27 81 calma 50 0 layer CM1 pad calma 49 0 layer CM1 m1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,ppc/m1,pnc/m1,m2c/m1 labels m1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,ppc/m1,pnc/m1,m2c/m1 calma 49 0 layer CM2 m2,rm2,m2c/m2,m3c/m2,m3c/m2 labels m2,rm2,m2c/m2,m3c/m2,m3c/m2 calma 51 0 layer CMFP m1p labels m1p calma 81 0 layer CMSP m2p labels m2p calma 82 0 layer 100 fp labels fp calma 100 0 layer 101 fm1 labels fm1 calma 101 0 layer 102 fm2 labels fm2 calma 102 0 layer 103 fm3 labels fm3 calma 103 0 layer 104 fm4 labels fm4 calma 104 0 layer 105 fm5 labels fm5 calma 105 0 layer 106 fm6 labels fm6 calma 106 0 layer 109 fa or fb squares 0 207 36 labels fa calma 109 0 layer 119 fn calma 119 0 layer 110 fapm labels fapm calma 110 0 # layer CPG fp layer CPG fp,fapm squares 0 207 36 labels fp calma 46 0 # layer CM1 fm1 layer CM1 fm1,fapm squares 0 207 36 labels fm1 calma 49 0 # layer CM2 fm2 layer CM2 fm2,fapm squares 0 207 36 labels fm2 calma 51 0 # layer CM3 fm3 layer CM3 fm3,fapm squares 0 207 36 labels fm3 calma 62 0 layer CM3 m3,rm3,m3c/m3,m4c/m3,m4c/m3 labels m3,rm3,m3c/m3,m4c/m3,m4c/m3 calma 62 0 layer CMTP m3p labels m3p calma 83 0 layer CM4 m4,rm4,m4c/m4,m5c/m4,m5c/m4 labels m4,rm4,m4c/m4,m5c/m4,m5c/m4 calma 31 0 layer CMQP m4p labels m4p calma 84 0 # layer CM4 fm4 layer CM4 fm4,fapm squares 0 207 36 labels fm4 calma 31 0 layer CM5 m5,rm5,m5c/m5,m6c/m5,m6c/m5 labels m5,rm5,m5c/m5,m6c/m5,m6c/m5 calma 33 0 layer CMPP m5p labels m5p calma 85 0 # layer CM5 fm5 layer CM5 fm5,fapm squares 0 207 36 labels fm5 calma 33 0 layer CM6 m6,rm6,m6c/m6,mic/m6 labels m6,rm6,m6c/m6,mic/m6 calma 37 0 layer CM6P m6p labels m6p calma 85 0 # layer CM6 fm6 layer CM6 fm6,fapm squares 0 207 36 labels fm6 calma 37 0 layer CTM mi,mic/mi labels mi,mic/mi calma 35 0 layer COG pad shrink 504 labels pad calma 52 0 layer COG glass labels glass calma 52 0 layer CFI nfi,pfi labels nfi,pfi calma 27 0 layer CSB sb,pres,anres,apres labels sb,pres,anres,apres calma 29 0 #CRE/CRM layer CRW rnw,prnw labels rnw,prnw calma 65 0 layer CRG rp,prp,pres labels rp,prp,pres calma 67 0 layer CRD rnd,rpd,prnd,prpd,anres,apres labels rnd,rpd,prnd,prpd,anres,apres calma 66 0 layer CRE rnw,rp,rnd,rpd,pres,anres,apres labels rnw,rp,rnd,rpd,pres,anres,apres calma 64 0 layer CRF rm1,prm1 labels rm1,prm1 calma 71 0 layer CRS rm2,prm2 labels rm2,prm2 calma 72 0 layer CRT rm3,prm3 labels rm3,prm3 calma 73 0 layer CRQ rm4,prm4 labels rm4,prm4 calma 74 0 layer CRP rm5,prm5 labels rm5,prm5 calma 75 0 layer CR6 rm6,prm6 labels rm6,prm6 calma 76 0 layer CRI rmi,prmi labels rmi,prmi calma 79 0 #CRE/CRM layer CRM rm1,prm1,rm2,prm2,rm3,prm3,rm4,prm4,rm5,prm5,rm6,prm6,rmi,prmi #CRE/CRM calma 70 0 layer CX comment labels comment calma 63 0 layer XP pad,xp labels pad,xp calma 26 0 end cifinput style lambda=0.09(p) scalefactor 9 layer nwell CWN and-not CWNR and-not CTA labels CWN calma CWN 42 * layer rnw CWN and-not CWNR and CRE and-not CSB and-not CRD and-not CAA and-not CPG calma CWN 42 * layer rnw CWN and-not CWNR and CRW and-not CRD and-not CAA and-not CPG calma CWN 42 * layer pseudo_rnwell CRW and-not CRE calma CRW 65 * calma CWNR 91 * layer nwr CWND calma CWND 92 * layer pseudo_nwr CRNW calma CRNW 93 * layer pwell CWP and-not CTA labels CWP calma CWP 41 * layer diff CAA and-not CTA and-not CPG and-not CWNR and-not COP and-not CSN and-not CSP labels CAA calma CAA 43 * layer tran CAA and-not CTA and CPG and-not CWNR and-not COP and-not CSN and-not CSP labels CAA calma CAA 43 * calma CSN 45 * calma CSP 44 * layer ndiff CAA and CSN and-not CWNR and-not CTA and-not CRE and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer rnd CAA and CSN and-not CWNR and CRE and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA calma CAA 43 * layer rnd CAA and CSN and-not CWNR and CRD and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA calma CAA 43 * layer pseudo_rndiff CRD and-not CRE and-not CAA and-not CSB and-not CPG and-not CWN and-not CSP and CSN and-not CBA calma CRD 66 * layer pdiff CAA and CSP and-not CWNR and-not CTA and-not CRE and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer rpd CAA and CSP and-not CWNR and CRE and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CAA 43 * layer rpd CAA and CSP and-not CWNR and CRD and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CAA 43 * layer pseudo_rpdiff CRD and-not CRE and-not CAA and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CRD 66 * layer nfet CAA and CSN and-not CWNR and-not CTA and CPG and-not CEL and-not CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer pfet CAA and CSP and-not CWNR and-not CTA and CPG and-not CEL and CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer nsd CAA and CSN and-not CWNR and-not CTA and CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer psd CAA and CSP and-not CWNR and-not CTA and-not CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer nwsd CAA and CSN and CWNR shrink 108 and-not CTA and CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer ndc CAA and CSN and CCA and-not CV1 and-not CWNR and-not CTA and-not CWN and CM1 grow 09 grow 9 shrink 9 calma CCA 48 * layer ndc CAA and CSN and CCC and-not CV1 and-not CWNR and-not CTA and-not CWN and CM1 grow 09 grow 9 shrink 9 calma CCC 25 * layer nsc CAA and CSN and CCA and-not CV1 and-not CWNR and-not CTA and CWN and CM1 grow 09 grow 9 shrink 9 calma CCA 48 * layer nsc CAA and CSN and CCC and-not CV1 and-not CWNR and-not CTA and CWN and CM1 grow 09 grow 9 shrink 9 calma CCC 25 * layer nwsc CAA and CSN and-not CV1 and CWNR shrink 108 and-not CTA and CCA and CWN and CM1 grow 18 grow 9 shrink 9 calma CCA 48 * layer nwsc CAA and CSN and-not CV1 and CWNR shrink 105 and-not CTA and CCC and CWN and CM1 grow 18 grow 9 shrink 9 calma CCC 25 * layer pdc CAA and CSP and CCA and-not CV1 and-not CTA and-not CPS and CWN and CM1 grow 09 grow 9 shrink 9 calma CCA 48 * layer pdc CAA and CSP and CCC and-not CV1 and-not CTA and-not CPS and CWN and CM1 grow 09 grow 9 shrink 9 calma CCC 25 * layer psc CAA and CSP and CCA and-not CV1 and-not CTA and-not CPS and-not CWN and CM1 grow 09 grow 9 shrink 9 calma CCA 48 * layer psc CAA and CSP and CCC and-not CV1 and-not CWNR and-not CTA and-not CPS and-not CWN and CM1 grow 09 grow 9 shrink 9 calma CCC 25 * layer ndc CAA and CSN and CCA and CV1 and CV2 and-not CV3 and-not CWNR and-not CTA and-not CWN and CM1 grow 09 grow 9 shrink 9 calma CCA 48 * layer ndc CAA and CSN and CCC and CV1 and CV2 and-not CV3 and-not CWNR and-not CTA and-not CWN and CM1 grow 09 grow 9 shrink 9 calma CCC 25 * layer nsc CAA and CSN and CCA and CV1 and CV2 and-not CV3 and-not CWNR and-not CTA and CWN and CM1 grow 09 grow 9 shrink 9 calma CCA 48 * layer nsc CAA and CSN and CCC and CV1 and CV2 and-not CV3 and-not CWNR and-not CTA and CWN and CM1 grow 09 grow 9 shrink 9 calma CCC 25 * layer nwsc CAA and CSN and CV1 and CV2 and-not CV3 and CWNR shrink 108 and-not CTA and CCA and CWN and CM1 grow 18 grow 9 shrink 9 calma CCA 48 * layer nwsc CAA and CSN and CV1 and CV2 and-not CV3 and CWNR shrink 105 and-not CTA and CCC and CWN and CM1 grow 18 grow 9 shrink 9 calma CCC 25 * layer pdc CAA and CSP and CCA and CV1 and CV2 and-not CV3 and-not CTA and-not CPS and CWN and CM1 grow 09 grow 9 shrink 9 calma CCA 48 * layer pdc CAA and CSP and CCC and CV1 and CV2 and-not CV3 and-not CTA and-not CPS and CWN and CM1 grow 09 grow 9 shrink 9 calma CCC 25 * layer psc CAA and CSP and CCA and CV1 and CV2 and-not CV3 and-not CTA and-not CPS and-not CWN and CM1 grow 09 grow 9 shrink 9 calma CCA 48 * layer psc CAA and CSP and CCC and CV1 and CV2 and-not CV3 and-not CWNR and-not CTA and-not CPS and-not CWN and CM1 grow 09 grow 9 shrink 9 calma CCC 25 * layer ndc CAA and CSN and CCA and CV1 and CV2 and CV3 and CV4 and-not CV5 and-not CWNR and-not CTA and-not CWN and CM1 grow 09 grow 9 shrink 9 calma CCA 48 * layer ndc CAA and CSN and CCC and CV1 and CV2 and CV3 and CV4 and-not CV5 and-not CWNR and-not CTA and-not CWN and CM1 grow 09 grow 9 shrink 9 calma CCC 25 * layer nsc CAA and CSN and CCA and CV1 and CV2 and CV3 and CV4 and-not CV5 and-not CWNR and-not CTA and CWN and CM1 grow 09 grow 9 shrink 9 calma CCA 48 * layer nsc CAA and CSN and CCC and CV1 and CV2 and CV3 and CV4 and-not CV5 and-not CWNR and-not CTA and CWN and CM1 grow 09 grow 9 shrink 9 calma CCC 25 * layer nwsc CAA and CSN and CV1 and CV2 and CV3 and CV4 and-not CV5 and CWNR shrink 108 and-not CTA and CCA and CWN and CM1 grow 18 grow 9 shrink 9 calma CCA 48 * layer nwsc CAA and CSN and CV1 and CV2 and CV3 and CV4 and-not CV5 and CWNR shrink 105 and-not CTA and CCC and CWN and CM1 grow 18 grow 9 shrink 9 calma CCC 25 * layer pdc CAA and CSP and CCA and CV1 and CV2 and CV3 and CV4 and-not CV5 and-not CTA and-not CPS and CWN and CM1 grow 09 grow 9 shrink 9 calma CCA 48 * layer pdc CAA and CSP and CCC and CV1 and CV2 and CV3 and CV4 and-not CV5 and-not CTA and-not CPS and CWN and CM1 grow 09 grow 9 shrink 9 calma CCC 25 * layer psc CAA and CSP and CCA and CV1 and CV2 and CV3 and CV4 and-not CV5 and-not CTA and-not CPS and-not CWN and CM1 grow 09 grow 9 shrink 9 calma CCA 48 * layer psc CAA and CSP and CCC and CV1 and CV2 and CV3 and CV4 and-not CV5 and-not CWNR and-not CTA and-not CPS and-not CWN and CM1 grow 09 grow 9 shrink 9 calma CCC 25 * layer poly CPG and-not CRE labels CPG calma CPG 46 * layer rp CPG and CRE and-not CSB calma CPG 46 * layer rp CPG and CRG calma CPG 46 * layer pseudo_rpoly CRG and-not CRE calma CRG 67 * layer pc CCP and-not CV1 and CPG and-not CPC and-not CEL and-not CAA grow 09 and CM1 grow 9 shrink 9 calma CCP 47 * layer pc CCC and-not CV1 and CPG and-not CPC and-not CEL and-not CAA grow 09 and CM1 grow 9 shrink 9 calma CCC 25 * layer pc CCP and CV1 and CV2 and-not CV3 and CPG and-not CPC and-not CEL and-not CAA grow 09 and CM1 grow 9 shrink 9 calma CCP 47 * layer pc CCC and CV1 and CV2 and-not CV3 and CPG and-not CPC and-not CEL and-not CAA grow 09 and CM1 grow 9 shrink 9 calma CCC 25 * layer pc CCP and CV1 and CV2 and CV3 and CV4 and-not CV5 and CPG and-not CPC and-not CEL and-not CAA grow 09 and CM1 grow 9 shrink 9 calma CCP 47 * layer pc CCC and CV1 and CV2 and CV3 and CV4 and-not CV5 and CPG and-not CPC and-not CEL and-not CAA grow 09 and CM1 grow 9 shrink 9 calma CCC 25 * layer gc CCP and-not CPG and-not CPC calma CCP 47 * layer gc CCP and-not CM1 calma CCP 47 * layer gc CCA and-not COP and-not CAA and-not CBA calma CCA 48 * layer gc CCA and-not COP and-not CM1 calma CCA 48 * layer gc CCC and-not COP and-not CPG and-not CPC and-not CEL and-not CAA and-not CBA calma CCC 25 * layer gc CCC and-not COP and-not CM1 calma CCC 25 * layer gc CCE and-not CPC and-not CEL calma CCE 55 * layer gc CCE and-not CM1 calma CCE 55 * layer gv1 CV1 and-not COP and-not CM1 calma CV1 50 * layer gv1 CV1 and-not COP and-not CM2 calma CV1 50 * layer gv2 CV2 and-not COP and-not CM2 calma CV2 61 * layer gv2 CV2 and-not COP and-not CM3 calma CV2 61 * layer gv3 CV3 and-not COP and-not CM3 calma CV3 30 * layer gv3 CV3 and-not COP and-not CM4 calma CV3 30 * layer gv4 CV4 and-not CTM and-not COP and-not CM4 calma CV4 32 * layer gv4 CV4 and-not CTM and-not COP and-not CM5 calma CV4 32 * layer gv5 CV5 and-not CTM and-not COP and-not CM5 calma CV5 36 * layer gv5 CV5 and-not CTM and-not COP and-not CM6 calma CV5 36 * layer gvi CV5 and CTM and-not COP and-not CM6 calma CV5 36 * layer m2c CV1 and-not CV2 and-not CCC and-not CCE and-not CCP and-not CCA and-not XP grow 09 and CM2 and CM1 grow 5 shrink 5 calma CV1 50 * layer m2c CV1 and CV2 and CV3 and-not CV4 and-not CCC and-not CCE and-not CCP and-not CCA and-not XP grow 09 and CM2 and CM1 grow 5 shrink 5 calma CV1 50 * layer m2c CV1 and CV5 and CV4 and CV3 and CV2 and-not CCC and-not CCE and-not CCP and-not CCA and-not XP grow 09 and CM2 and CM1 grow 5 shrink 5 calma CV1 50 * layer m1 CM1 and-not CRM and-not CRF and-not XP labels CM1 calma CM1 49 * layer rm1 CRM and CM1 calma CRM 70 * layer rm1 CRF and CM1 calma CRF 71 * layer pseudo_rmetal1 CRF and-not rm1 calma CRF 71 * layer m1p CMFP labels CMFP calma CMFP 81 * layer m2 CM2 and-not CRM and-not CRS and-not XP labels CM2 calma CM2 51 * layer rm2 CRM and CM2 calma CRM 70 * layer rm2 CRS and CM2 calma CRS 72 * layer pseudo_rmetal2 CRS and-not rm2 calma CRS 72 * layer m2p CMSP labels CMSP calma CMSP 82 * layer fp 100 calma 100 100 * layer fm1 101 calma 101 101 * layer fm2 102 calma 102 102 * layer fm3 103 calma 103 103 * layer fm4 104 calma 104 104 * layer fm5 105 calma 105 105 * layer fm6 106 calma 106 106 * layer fa 109 calma 109 109 * layer fn 119 calma 119 119 * layer fapm 110 calma 110 110 * layer m3c CV2 and-not CV3 and-not CV1 and-not XP grow 09 and CM3 and CM2 grow 5 shrink 5 calma CV2 61 * layer m3c CV2 and CV3 and CV4 and-not CV5 and-not CV1 and-not XP grow 09 and CM3 and CM2 grow 5 shrink 5 calma CV2 61 * layer m3 CM3 and-not CRM and-not CRT and-not XP labels CM3 calma CM3 62 * layer rm3 CRM and CM3 calma CRM 70 * layer rm3 CRT and CM3 calma CRT 73 * layer pseudo_rmetal3 CRT and-not rm3 calma CRT 73 * layer m3p CMTP labels CMTP calma CMTP 83 * layer m4 CM4 and-not CRM and-not CRQ and-not XP labels CM4 calma CM4 31 * layer rm4 CRM and CM4 calma CRM 70 * layer rm4 CRQ and CM4 calma CRQ 74 * layer pseudo_rmetal4 CRQ and-not rm4 calma CRQ 74 * layer m4p CMQP labels CMQP calma CMQP 84 * layer m4c CV3 and-not CV4 and-not CV2 and-not XP grow 09 and CM4 and CM3 grow 09 shrink 09 calma CV3 30 * layer m4c CV3 and CV4 and CV5 and-not CV2 and-not XP grow 09 and CM4 and CM3 grow 09 shrink 09 calma CV3 30 * layer m5 CM5 and-not CRM and-not CRP and-not XP labels CM5 calma CM5 33 * layer rm5 CRM and CM5 calma CRM 70 * layer rm5 CRP and CM5 calma CRP 75 * layer pseudo_rmetal5 CRP and-not rm5 calma CRP 75 * layer m5p CMPP labels CMPP calma CMPP 85 * layer m5c CV4 and-not CV5 and-not CV3 and-not XP grow 09 and CM5 and CM4 grow 09 shrink 09 calma CV4 32 * layer m6 CM6 and-not CRM and-not CR6 and-not XP labels CM6 calma CM6 37 * layer rm6 CRM and CM6 calma CRM 70 * layer rm6 CR6 and CM6 calma CR6 76 * layer pseudo_rmetal6 CR6 and-not rm6 calma CR6 76 * layer m6p CM6P labels CM6P calma CM6P 85 * layer m6c CV5 and-not CTM shrink 09 and-not CV4 grow 09 and-not XP grow 09 and CM6 and CM5 grow 09 shrink 09 calma CV5 36 * layer mic CV5 and CTM and-not XP grow 27 and CTM layer mi CTM and-not CRM and-not CRI and-not XP labels CTM calma CTM 35 * layer rmi CRM and CTM calma CRM 70 * layer rmi CRI and CTM calma CRI 79 * layer pseudo_rmetali CRI and-not rmi calma CRI 79 * layer mic CV5 grow 5 and CTM and-not XP grow 103 and CTM and CM6 grow 09 shrink 09 calma CV5 36 * layer pad XP labels pad calma XP 26 * layer glass COG and-not COP and-not XP labels COG calma COG 52 * layer nfi CFI and CWN labels CFI calma CFI 27 * layer pfi CFI and-not CWN labels CFI calma CFI 27 * layer sb CSB and-not CWNR labels CSB calma CSB 29 * layer pres CPG and CSB calma CPG 46 * layer anres CAA and CSN and-not CWNR and-not CTA and CSB and-not CPG and-not CWN and-not CSP and-not CBA calma CAA 43 * layer apres CAA and CSP and-not CWNR and-not CTA and CSB and-not CPG and CWN and-not CSN and-not CPS and-not CBA calma CAA 43 * layer comment CX labels CX calma CX 63 * calma CTA 60 * calma CRW 65 * calma CRG 67 * calma CRD 66 * calma CRE 64 * calma CRF 71 * calma CRS 72 * calma CRT 73 * calma CRQ 74 * calma CRP 75 * calma CR6 76 * calma CRI 79 * calma CRM 70 * style lambda=0.09(s) scalefactor 9 layer nwell CWN and-not CWNR and-not CTA labels CWN calma CWN 42 * layer rnw CWN and-not CWNR and CRE and-not CSB and-not CRD and-not CAA and-not CPG calma CWN 42 * layer rnw CWN and-not CWNR and CRW and-not CRD and-not CAA and-not CPG calma CWN 42 * layer pseudo_rnwell CRW and-not CRE calma CRW 65 * calma CWNR 91 * layer nwr CWND calma CWND 92 * layer pseudo_nwr CRNW calma CRNW 93 * ignore CWP calma CWP 41 * layer diff CAA and-not CTA and-not CPG and-not CWNR and-not COP and-not CSN and-not CSP labels CAA calma CAA 43 * layer tran CAA and-not CTA and CPG and-not CWNR and-not COP and-not CSN and-not CSP labels CAA calma CAA 43 * layer nselect CSN calma CSN 45 * layer pselect CSP calma CSP 44 * layer ndiff CAA and CSN and-not CWNR and-not CTA and-not CRE and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer rnd CAA and CSN and-not CWNR and CRE and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA calma CAA 43 * layer rnd CAA and CSN and-not CWNR and CRD and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA calma CAA 43 * layer pseudo_rndiff CRD and-not CRE and-not CAA and-not CSB and-not CPG and-not CWN and-not CSP and CSN and-not CBA calma CRD 66 * layer pdiff CAA and CSP and-not CWNR and-not CTA and-not CRE and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer rpd CAA and CSP and-not CWNR and CRE and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CAA 43 * layer rpd CAA and CSP and-not CWNR and CRD and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CAA 43 * layer pseudo_rpdiff CRD and-not CRE and-not CAA and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CRD 66 * layer nfet CAA and CSN and-not CWNR and-not CTA and CPG and-not CEL and-not CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer pfet CAA and CSP and-not CWNR and-not CTA and CPG and-not CEL and CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer nsd CAA and CSN and-not CWNR and-not CTA and CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer psd CAA and CSP and-not CWNR and-not CTA and-not CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer nwsd CAA and CSN and CWNR shrink 108 and-not CTA and CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer ndc CAA and CSN and CCA and-not CV1 and-not CWNR and-not CTA and-not CWN and CM1 grow 09 grow 9 shrink 9 calma CCA 48 * layer ndc CAA and CSN and CCC and-not CV1 and-not CWNR and-not CTA and-not CWN and CM1 grow 09 grow 9 shrink 9 calma CCC 25 * layer nsc CAA and CSN and CCA and-not CV1 and-not CWNR and-not CTA and CWN and CM1 grow 09 grow 9 shrink 9 calma CCA 48 * layer nsc CAA and CSN and CCC and-not CV1 and-not CWNR and-not CTA and CWN and CM1 grow 09 grow 9 shrink 9 calma CCC 25 * layer nwsc CAA and CSN and-not CV1 and CWNR shrink 108 and-not CTA and CCA and CWN and CM1 grow 18 grow 9 shrink 9 calma CCA 48 * layer nwsc CAA and CSN and-not CV1 and CWNR shrink 105 and-not CTA and CCC and CWN and CM1 grow 18 grow 9 shrink 9 calma CCC 25 * layer pdc CAA and CSP and CCA and-not CV1 and-not CTA and-not CPS and CWN and CM1 grow 09 grow 9 shrink 9 calma CCA 48 * layer pdc CAA and CSP and CCC and-not CV1 and-not CTA and-not CPS and CWN and CM1 grow 09 grow 9 shrink 9 calma CCC 25 * layer psc CAA and CSP and CCA and-not CV1 and-not CTA and-not CPS and-not CWN and CM1 grow 09 grow 9 shrink 9 calma CCA 48 * layer psc CAA and CSP and CCC and-not CV1 and-not CWNR and-not CTA and-not CPS and-not CWN and CM1 grow 09 grow 9 shrink 9 calma CCC 25 * layer ndc CAA and CSN and CCA and CV1 and CV2 and-not CV3 and-not CWNR and-not CTA and-not CWN and CM1 grow 09 grow 9 shrink 9 calma CCA 48 * layer ndc CAA and CSN and CCC and CV1 and CV2 and-not CV3 and-not CWNR and-not CTA and-not CWN and CM1 grow 09 grow 9 shrink 9 calma CCC 25 * layer nsc CAA and CSN and CCA and CV1 and CV2 and-not CV3 and-not CWNR and-not CTA and CWN and CM1 grow 09 grow 9 shrink 9 calma CCA 48 * layer nsc CAA and CSN and CCC and CV1 and CV2 and-not CV3 and-not CWNR and-not CTA and CWN and CM1 grow 09 grow 9 shrink 9 calma CCC 25 * layer nwsc CAA and CSN and CV1 and CV2 and-not CV3 and CWNR shrink 108 and-not CTA and CCA and CWN and CM1 grow 18 grow 9 shrink 9 calma CCA 48 * layer nwsc CAA and CSN and CV1 and CV2 and-not CV3 and CWNR shrink 105 and-not CTA and CCC and CWN and CM1 grow 18 grow 9 shrink 9 calma CCC 25 * layer pdc CAA and CSP and CCA and CV1 and CV2 and-not CV3 and-not CTA and-not CPS and CWN and CM1 grow 09 grow 9 shrink 9 calma CCA 48 * layer pdc CAA and CSP and CCC and CV1 and CV2 and-not CV3 and-not CTA and-not CPS and CWN and CM1 grow 09 grow 9 shrink 9 calma CCC 25 * layer psc CAA and CSP and CCA and CV1 and CV2 and-not CV3 and-not CTA and-not CPS and-not CWN and CM1 grow 09 grow 9 shrink 9 calma CCA 48 * layer psc CAA and CSP and CCC and CV1 and CV2 and-not CV3 and-not CWNR and-not CTA and-not CPS and-not CWN and CM1 grow 09 grow 9 shrink 9 calma CCC 25 * layer ndc CAA and CSN and CCA and CV1 and CV2 and CV3 and CV4 and-not CV5 and-not CWNR and-not CTA and-not CWN and CM1 grow 09 grow 9 shrink 9 calma CCA 48 * layer ndc CAA and CSN and CCC and CV1 and CV2 and CV3 and CV4 and-not CV5 and-not CWNR and-not CTA and-not CWN and CM1 grow 09 grow 9 shrink 9 calma CCC 25 * layer nsc CAA and CSN and CCA and CV1 and CV2 and CV3 and CV4 and-not CV5 and-not CWNR and-not CTA and CWN and CM1 grow 09 grow 9 shrink 9 calma CCA 48 * layer nsc CAA and CSN and CCC and CV1 and CV2 and CV3 and CV4 and-not CV5 and-not CWNR and-not CTA and CWN and CM1 grow 09 grow 9 shrink 9 calma CCC 25 * layer nwsc CAA and CSN and CV1 and CV2 and CV3 and CV4 and-not CV5 and CWNR shrink 108 and-not CTA and CCA and CWN and CM1 grow 18 grow 9 shrink 9 calma CCA 48 * layer nwsc CAA and CSN and CV1 and CV2 and CV3 and CV4 and-not CV5 and CWNR shrink 105 and-not CTA and CCC and CWN and CM1 grow 18 grow 9 shrink 9 calma CCC 25 * layer pdc CAA and CSP and CCA and CV1 and CV2 and CV3 and CV4 and-not CV5 and-not CTA and-not CPS and CWN and CM1 grow 09 grow 9 shrink 9 calma CCA 48 * layer pdc CAA and CSP and CCC and CV1 and CV2 and CV3 and CV4 and-not CV5 and-not CTA and-not CPS and CWN and CM1 grow 09 grow 9 shrink 9 calma CCC 25 * layer psc CAA and CSP and CCA and CV1 and CV2 and CV3 and CV4 and-not CV5 and-not CTA and-not CPS and-not CWN and CM1 grow 09 grow 9 shrink 9 calma CCA 48 * layer psc CAA and CSP and CCC and CV1 and CV2 and CV3 and CV4 and-not CV5 and-not CWNR and-not CTA and-not CPS and-not CWN and CM1 grow 09 grow 9 shrink 9 calma CCC 25 * layer poly CPG and-not CRE labels CPG calma CPG 46 * layer rp CPG and CRE and-not CSB calma CPG 46 * layer rp CPG and CRG calma CPG 46 * layer pseudo_rpoly CRG and-not CRE calma CRG 67 * layer pc CCP and-not CV1 and CPG and-not CPC and-not CEL and-not CAA grow 09 and CM1 grow 9 shrink 9 calma CCP 47 * layer pc CCC and-not CV1 and CPG and-not CPC and-not CEL and-not CAA grow 09 and CM1 grow 9 shrink 9 calma CCC 25 * layer pc CCP and CV1 and CV2 and-not CV3 and CPG and-not CPC and-not CEL and-not CAA grow 09 and CM1 grow 9 shrink 9 calma CCP 47 * layer pc CCC and CV1 and CV2 and-not CV3 and CPG and-not CPC and-not CEL and-not CAA grow 09 and CM1 grow 9 shrink 9 calma CCC 25 * layer pc CCP and CV1 and CV2 and CV3 and CV4 and-not CV5 and CPG and-not CPC and-not CEL and-not CAA grow 09 and CM1 grow 9 shrink 9 calma CCP 47 * layer pc CCC and CV1 and CV2 and CV3 and CV4 and-not CV5 and CPG and-not CPC and-not CEL and-not CAA grow 09 and CM1 grow 9 shrink 9 calma CCC 25 * layer gc CCP and-not CPG and-not CPC calma CCP 47 * layer gc CCP and-not CM1 calma CCP 47 * layer gc CCA and-not COP and-not CAA and-not CBA calma CCA 48 * layer gc CCA and-not COP and-not CM1 calma CCA 48 * layer gc CCC and-not COP and-not CPG and-not CPC and-not CEL and-not CAA and-not CBA calma CCC 25 * layer gc CCC and-not COP and-not CM1 calma CCC 25 * layer gc CCE and-not CPC and-not CEL calma CCE 55 * layer gc CCE and-not CM1 calma CCE 55 * layer gv1 CV1 and-not COP and-not CM1 calma CV1 50 * layer gv1 CV1 and-not COP and-not CM2 calma CV1 50 * layer gv2 CV2 and-not COP and-not CM2 calma CV2 61 * layer gv2 CV2 and-not COP and-not CM3 calma CV2 61 * layer gv3 CV3 and-not COP and-not CM3 calma CV3 30 * layer gv3 CV3 and-not COP and-not CM4 calma CV3 30 * layer gv4 CV4 and-not CTM and-not COP and-not CM4 calma CV4 32 * layer gv4 CV4 and-not CTM and-not COP and-not CM5 calma CV4 32 * layer gv5 CV5 and-not CTM and-not COP and-not CM5 calma CV5 36 * layer gv5 CV5 and-not CTM and-not COP and-not CM6 calma CV5 36 * layer gvi CV5 and CTM and-not COP and-not CM6 calma CV5 36 * layer m2c CV1 and-not CV2 and-not CCC and-not CCE and-not CCP and-not CCA and-not XP grow 09 and CM2 and CM1 grow 5 shrink 5 calma CV1 50 * layer m2c CV1 and CV2 and CV3 and-not CV4 and-not CCC and-not CCE and-not CCP and-not CCA and-not XP grow 09 and CM2 and CM1 grow 5 shrink 5 calma CV1 50 * layer m2c CV1 and CV5 and CV4 and CV3 and CV2 and-not CCC and-not CCE and-not CCP and-not CCA and-not XP grow 09 and CM2 and CM1 grow 5 shrink 5 calma CV1 50 * layer m1 CM1 and-not CRM and-not CRF and-not XP labels CM1 calma CM1 49 * layer rm1 CRM and CM1 calma CRM 70 * layer rm1 CRF and CM1 calma CRF 71 * layer pseudo_rmetal1 CRF and-not rm1 calma CRF 71 * layer m1p CMFP labels CMFP calma CMFP 81 * layer m2 CM2 and-not CRM and-not CRS and-not XP labels CM2 calma CM2 51 * layer rm2 CRM and CM2 calma CRM 70 * layer rm2 CRS and CM2 calma CRS 72 * layer pseudo_rmetal2 CRS and-not rm2 calma CRS 72 * layer m2p CMSP labels CMSP calma CMSP 82 * layer fp 100 calma 100 100 * layer fm1 101 calma 101 101 * layer fm2 102 calma 102 102 * layer fm3 103 calma 103 103 * layer fm4 104 calma 104 104 * layer fm5 105 calma 105 105 * layer fm6 106 calma 106 106 * layer fa 109 calma 109 109 * layer fn 119 calma 119 119 * layer fapm 110 calma 110 110 * layer m3c CV2 and-not CV3 and-not CV1 and-not XP grow 09 and CM3 and CM2 grow 5 shrink 5 calma CV2 61 * layer m3c CV2 and CV3 and CV4 and-not CV5 and-not CV1 and-not XP grow 09 and CM3 and CM2 grow 5 shrink 5 calma CV2 61 * layer m3 CM3 and-not CRM and-not CRT and-not XP labels CM3 calma CM3 62 * layer rm3 CRM and CM3 calma CRM 70 * layer rm3 CRT and CM3 calma CRT 73 * layer pseudo_rmetal3 CRT and-not rm3 calma CRT 73 * layer m3p CMTP labels CMTP calma CMTP 83 * layer m4 CM4 and-not CRM and-not CRQ and-not XP labels CM4 calma CM4 31 * layer rm4 CRM and CM4 calma CRM 70 * layer rm4 CRQ and CM4 calma CRQ 74 * layer pseudo_rmetal4 CRQ and-not rm4 calma CRQ 74 * layer m4p CMQP labels CMQP calma CMQP 84 * layer m4c CV3 and-not CV4 and-not CV2 and-not XP grow 09 and CM4 and CM3 grow 09 shrink 09 calma CV3 30 * layer m4c CV3 and CV4 and CV5 and-not CV2 and-not XP grow 09 and CM4 and CM3 grow 09 shrink 09 calma CV3 30 * layer m5 CM5 and-not CRM and-not CRP and-not XP labels CM5 calma CM5 33 * layer rm5 CRM and CM5 calma CRM 70 * layer rm5 CRP and CM5 calma CRP 75 * layer pseudo_rmetal5 CRP and-not rm5 calma CRP 75 * layer m5p CMPP labels CMPP calma CMPP 85 * layer m5c CV4 and-not CV5 and-not CV3 and-not XP grow 09 and CM5 and CM4 grow 09 shrink 09 calma CV4 32 * layer m6 CM6 and-not CRM and-not CR6 and-not XP labels CM6 calma CM6 37 * layer rm6 CRM and CM6 calma CRM 70 * layer rm6 CR6 and CM6 calma CR6 76 * layer pseudo_rmetal6 CR6 and-not rm6 calma CR6 76 * layer m6p CM6P labels CM6P calma CM6P 85 * layer m6c CV5 and-not CTM shrink 09 and-not CV4 grow 09 and-not XP grow 09 and CM6 and CM5 grow 09 shrink 09 calma CV5 36 * layer mic CV5 and CTM and-not XP grow 27 and CTM layer mi CTM and-not CRM and-not CRI and-not XP labels CTM calma CTM 35 * layer rmi CRM and CTM calma CRM 70 * layer rmi CRI and CTM calma CRI 79 * layer pseudo_rmetali CRI and-not rmi calma CRI 79 * layer mic CV5 grow 5 and CTM and-not XP grow 103 and CTM and CM6 grow 09 shrink 09 calma CV5 36 * layer pad XP labels pad calma XP 26 * layer glass COG and-not COP and-not XP labels COG calma COG 52 * layer nfi CFI and CWN labels CFI calma CFI 27 * layer pfi CFI and-not CWN labels CFI calma CFI 27 * layer sb CSB and-not CWNR labels CSB calma CSB 29 * layer pres CPG and CSB calma CPG 46 * layer anres CAA and CSN and-not CWNR and-not CTA and CSB and-not CPG and-not CWN and-not CSP and-not CBA calma CAA 43 * layer apres CAA and CSP and-not CWNR and-not CTA and CSB and-not CPG and CWN and-not CSN and-not CPS and-not CBA calma CAA 43 * layer comment CX labels CX calma CX 63 * calma CTA 60 * calma CRW 65 * calma CRG 67 * calma CRD 66 * calma CRE 64 * calma CRF 71 * calma CRS 72 * calma CRT 73 * calma CRQ 74 * calma CRP 75 * calma CR6 76 * calma CRI 79 * calma CRM 70 * style lambda=0.09(ps) scalefactor 9 layer nwell CWN and-not CWNR and-not CTA labels CWN calma CWN 42 * layer rnw CWN and-not CWNR and CRE and-not CSB and-not CRD and-not CAA and-not CPG calma CWN 42 * layer rnw CWN and-not CWNR and CRW and-not CRD and-not CAA and-not CPG calma CWN 42 * layer pseudo_rnwell CRW and-not CRE calma CRW 65 * calma CWNR 91 * layer nwr CWND calma CWND 92 * layer pseudo_nwr CRNW calma CRNW 93 * layer pwell CWP and-not CTA labels CWP calma CWP 41 * layer diff CAA and-not CTA and-not CPG and-not CWNR and-not COP and-not CSN and-not CSP labels CAA calma CAA 43 * layer tran CAA and-not CTA and CPG and-not CWNR and-not COP and-not CSN and-not CSP labels CAA calma CAA 43 * layer nselect CSN calma CSN 45 * layer pselect CSP calma CSP 44 * layer ndiff CAA and CSN and-not CWNR and-not CTA and-not CRE and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer rnd CAA and CSN and-not CWNR and CRE and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA calma CAA 43 * layer rnd CAA and CSN and-not CWNR and CRD and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA calma CAA 43 * layer pseudo_rndiff CRD and-not CRE and-not CAA and-not CSB and-not CPG and-not CWN and-not CSP and CSN and-not CBA calma CRD 66 * layer pdiff CAA and CSP and-not CWNR and-not CTA and-not CRE and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer rpd CAA and CSP and-not CWNR and CRE and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CAA 43 * layer rpd CAA and CSP and-not CWNR and CRD and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CAA 43 * layer pseudo_rpdiff CRD and-not CRE and-not CAA and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CRD 66 * layer nfet CAA and CSN and-not CWNR and-not CTA and CPG and-not CEL and-not CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer pfet CAA and CSP and-not CWNR and-not CTA and CPG and-not CEL and CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer nsd CAA and CSN and-not CWNR and-not CTA and CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer psd CAA and CSP and-not CWNR and-not CTA and-not CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer nwsd CAA and CSN and CWNR shrink 108 and-not CTA and CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer ndc CAA and CSN and CCA and-not CV1 and-not CWNR and-not CTA and-not CWN and CM1 grow 09 grow 9 shrink 9 calma CCA 48 * layer ndc CAA and CSN and CCC and-not CV1 and-not CWNR and-not CTA and-not CWN and CM1 grow 09 grow 9 shrink 9 calma CCC 25 * layer nsc CAA and CSN and CCA and-not CV1 and-not CWNR and-not CTA and CWN and CM1 grow 09 grow 9 shrink 9 calma CCA 48 * layer nsc CAA and CSN and CCC and-not CV1 and-not CWNR and-not CTA and CWN and CM1 grow 09 grow 9 shrink 9 calma CCC 25 * layer nwsc CAA and CSN and-not CV1 and CWNR shrink 108 and-not CTA and CCA and CWN and CM1 grow 18 grow 9 shrink 9 calma CCA 48 * layer nwsc CAA and CSN and-not CV1 and CWNR shrink 105 and-not CTA and CCC and CWN and CM1 grow 18 grow 9 shrink 9 calma CCC 25 * layer pdc CAA and CSP and CCA and-not CV1 and-not CTA and-not CPS and CWN and CM1 grow 09 grow 9 shrink 9 calma CCA 48 * layer pdc CAA and CSP and CCC and-not CV1 and-not CTA and-not CPS and CWN and CM1 grow 09 grow 9 shrink 9 calma CCC 25 * layer psc CAA and CSP and CCA and-not CV1 and-not CTA and-not CPS and-not CWN and CM1 grow 09 grow 9 shrink 9 calma CCA 48 * layer psc CAA and CSP and CCC and-not CV1 and-not CWNR and-not CTA and-not CPS and-not CWN and CM1 grow 09 grow 9 shrink 9 calma CCC 25 * layer ndc CAA and CSN and CCA and CV1 and CV2 and-not CV3 and-not CWNR and-not CTA and-not CWN and CM1 grow 09 grow 9 shrink 9 calma CCA 48 * layer ndc CAA and CSN and CCC and CV1 and CV2 and-not CV3 and-not CWNR and-not CTA and-not CWN and CM1 grow 09 grow 9 shrink 9 calma CCC 25 * layer nsc CAA and CSN and CCA and CV1 and CV2 and-not CV3 and-not CWNR and-not CTA and CWN and CM1 grow 09 grow 9 shrink 9 calma CCA 48 * layer nsc CAA and CSN and CCC and CV1 and CV2 and-not CV3 and-not CWNR and-not CTA and CWN and CM1 grow 09 grow 9 shrink 9 calma CCC 25 * layer nwsc CAA and CSN and CV1 and CV2 and-not CV3 and CWNR shrink 108 and-not CTA and CCA and CWN and CM1 grow 18 grow 9 shrink 9 calma CCA 48 * layer nwsc CAA and CSN and CV1 and CV2 and-not CV3 and CWNR shrink 105 and-not CTA and CCC and CWN and CM1 grow 18 grow 9 shrink 9 calma CCC 25 * layer pdc CAA and CSP and CCA and CV1 and CV2 and-not CV3 and-not CTA and-not CPS and CWN and CM1 grow 09 grow 9 shrink 9 calma CCA 48 * layer pdc CAA and CSP and CCC and CV1 and CV2 and-not CV3 and-not CTA and-not CPS and CWN and CM1 grow 09 grow 9 shrink 9 calma CCC 25 * layer psc CAA and CSP and CCA and CV1 and CV2 and-not CV3 and-not CTA and-not CPS and-not CWN and CM1 grow 09 grow 9 shrink 9 calma CCA 48 * layer psc CAA and CSP and CCC and CV1 and CV2 and-not CV3 and-not CWNR and-not CTA and-not CPS and-not CWN and CM1 grow 09 grow 9 shrink 9 calma CCC 25 * layer ndc CAA and CSN and CCA and CV1 and CV2 and CV3 and CV4 and-not CV5 and-not CWNR and-not CTA and-not CWN and CM1 grow 09 grow 9 shrink 9 calma CCA 48 * layer ndc CAA and CSN and CCC and CV1 and CV2 and CV3 and CV4 and-not CV5 and-not CWNR and-not CTA and-not CWN and CM1 grow 09 grow 9 shrink 9 calma CCC 25 * layer nsc CAA and CSN and CCA and CV1 and CV2 and CV3 and CV4 and-not CV5 and-not CWNR and-not CTA and CWN and CM1 grow 09 grow 9 shrink 9 calma CCA 48 * layer nsc CAA and CSN and CCC and CV1 and CV2 and CV3 and CV4 and-not CV5 and-not CWNR and-not CTA and CWN and CM1 grow 09 grow 9 shrink 9 calma CCC 25 * layer nwsc CAA and CSN and CV1 and CV2 and CV3 and CV4 and-not CV5 and CWNR shrink 108 and-not CTA and CCA and CWN and CM1 grow 18 grow 9 shrink 9 calma CCA 48 * layer nwsc CAA and CSN and CV1 and CV2 and CV3 and CV4 and-not CV5 and CWNR shrink 105 and-not CTA and CCC and CWN and CM1 grow 18 grow 9 shrink 9 calma CCC 25 * layer pdc CAA and CSP and CCA and CV1 and CV2 and CV3 and CV4 and-not CV5 and-not CTA and-not CPS and CWN and CM1 grow 09 grow 9 shrink 9 calma CCA 48 * layer pdc CAA and CSP and CCC and CV1 and CV2 and CV3 and CV4 and-not CV5 and-not CTA and-not CPS and CWN and CM1 grow 09 grow 9 shrink 9 calma CCC 25 * layer psc CAA and CSP and CCA and CV1 and CV2 and CV3 and CV4 and-not CV5 and-not CTA and-not CPS and-not CWN and CM1 grow 09 grow 9 shrink 9 calma CCA 48 * layer psc CAA and CSP and CCC and CV1 and CV2 and CV3 and CV4 and-not CV5 and-not CWNR and-not CTA and-not CPS and-not CWN and CM1 grow 09 grow 9 shrink 9 calma CCC 25 * layer poly CPG and-not CRE labels CPG calma CPG 46 * layer rp CPG and CRE and-not CSB calma CPG 46 * layer rp CPG and CRG calma CPG 46 * layer pseudo_rpoly CRG and-not CRE calma CRG 67 * layer pc CCP and-not CV1 and CPG and-not CPC and-not CEL and-not CAA grow 09 and CM1 grow 9 shrink 9 calma CCP 47 * layer pc CCC and-not CV1 and CPG and-not CPC and-not CEL and-not CAA grow 09 and CM1 grow 9 shrink 9 calma CCC 25 * layer pc CCP and CV1 and CV2 and-not CV3 and CPG and-not CPC and-not CEL and-not CAA grow 09 and CM1 grow 9 shrink 9 calma CCP 47 * layer pc CCC and CV1 and CV2 and-not CV3 and CPG and-not CPC and-not CEL and-not CAA grow 09 and CM1 grow 9 shrink 9 calma CCC 25 * layer pc CCP and CV1 and CV2 and CV3 and CV4 and-not CV5 and CPG and-not CPC and-not CEL and-not CAA grow 09 and CM1 grow 9 shrink 9 calma CCP 47 * layer pc CCC and CV1 and CV2 and CV3 and CV4 and-not CV5 and CPG and-not CPC and-not CEL and-not CAA grow 09 and CM1 grow 9 shrink 9 calma CCC 25 * layer gc CCP and-not CPG and-not CPC calma CCP 47 * layer gc CCP and-not CM1 calma CCP 47 * layer gc CCA and-not COP and-not CAA and-not CBA calma CCA 48 * layer gc CCA and-not COP and-not CM1 calma CCA 48 * layer gc CCC and-not COP and-not CPG and-not CPC and-not CEL and-not CAA and-not CBA calma CCC 25 * layer gc CCC and-not COP and-not CM1 calma CCC 25 * layer gc CCE and-not CPC and-not CEL calma CCE 55 * layer gc CCE and-not CM1 calma CCE 55 * layer gv1 CV1 and-not COP and-not CM1 calma CV1 50 * layer gv1 CV1 and-not COP and-not CM2 calma CV1 50 * layer gv2 CV2 and-not COP and-not CM2 calma CV2 61 * layer gv2 CV2 and-not COP and-not CM3 calma CV2 61 * layer gv3 CV3 and-not COP and-not CM3 calma CV3 30 * layer gv3 CV3 and-not COP and-not CM4 calma CV3 30 * layer gv4 CV4 and-not CTM and-not COP and-not CM4 calma CV4 32 * layer gv4 CV4 and-not CTM and-not COP and-not CM5 calma CV4 32 * layer gv5 CV5 and-not CTM and-not COP and-not CM5 calma CV5 36 * layer gv5 CV5 and-not CTM and-not COP and-not CM6 calma CV5 36 * layer gvi CV5 and CTM and-not COP and-not CM6 calma CV5 36 * layer m2c CV1 and-not CV2 and-not CCC and-not CCE and-not CCP and-not CCA and-not XP grow 09 and CM2 and CM1 grow 5 shrink 5 calma CV1 50 * layer m2c CV1 and CV2 and CV3 and-not CV4 and-not CCC and-not CCE and-not CCP and-not CCA and-not XP grow 09 and CM2 and CM1 grow 5 shrink 5 calma CV1 50 * layer m2c CV1 and CV5 and CV4 and CV3 and CV2 and-not CCC and-not CCE and-not CCP and-not CCA and-not XP grow 09 and CM2 and CM1 grow 5 shrink 5 calma CV1 50 * layer m1 CM1 and-not CRM and-not CRF and-not XP labels CM1 calma CM1 49 * layer rm1 CRM and CM1 calma CRM 70 * layer rm1 CRF and CM1 calma CRF 71 * layer pseudo_rmetal1 CRF and-not rm1 calma CRF 71 * layer m1p CMFP labels CMFP calma CMFP 81 * layer m2 CM2 and-not CRM and-not CRS and-not XP labels CM2 calma CM2 51 * layer rm2 CRM and CM2 calma CRM 70 * layer rm2 CRS and CM2 calma CRS 72 * layer pseudo_rmetal2 CRS and-not rm2 calma CRS 72 * layer m2p CMSP labels CMSP calma CMSP 82 * layer fp 100 calma 100 100 * layer fm1 101 calma 101 101 * layer fm2 102 calma 102 102 * layer fm3 103 calma 103 103 * layer fm4 104 calma 104 104 * layer fm5 105 calma 105 105 * layer fm6 106 calma 106 106 * layer fa 109 calma 109 109 * layer fn 119 calma 119 119 * layer fapm 110 calma 110 110 * layer m3c CV2 and-not CV3 and-not CV1 and-not XP grow 09 and CM3 and CM2 grow 5 shrink 5 calma CV2 61 * layer m3c CV2 and CV3 and CV4 and-not CV5 and-not CV1 and-not XP grow 09 and CM3 and CM2 grow 5 shrink 5 calma CV2 61 * layer m3 CM3 and-not CRM and-not CRT and-not XP labels CM3 calma CM3 62 * layer rm3 CRM and CM3 calma CRM 70 * layer rm3 CRT and CM3 calma CRT 73 * layer pseudo_rmetal3 CRT and-not rm3 calma CRT 73 * layer m3p CMTP labels CMTP calma CMTP 83 * layer m4 CM4 and-not CRM and-not CRQ and-not XP labels CM4 calma CM4 31 * layer rm4 CRM and CM4 calma CRM 70 * layer rm4 CRQ and CM4 calma CRQ 74 * layer pseudo_rmetal4 CRQ and-not rm4 calma CRQ 74 * layer m4p CMQP labels CMQP calma CMQP 84 * layer m4c CV3 and-not CV4 and-not CV2 and-not XP grow 09 and CM4 and CM3 grow 09 shrink 09 calma CV3 30 * layer m4c CV3 and CV4 and CV5 and-not CV2 and-not XP grow 09 and CM4 and CM3 grow 09 shrink 09 calma CV3 30 * layer m5 CM5 and-not CRM and-not CRP and-not XP labels CM5 calma CM5 33 * layer rm5 CRM and CM5 calma CRM 70 * layer rm5 CRP and CM5 calma CRP 75 * layer pseudo_rmetal5 CRP and-not rm5 calma CRP 75 * layer m5p CMPP labels CMPP calma CMPP 85 * layer m5c CV4 and-not CV5 and-not CV3 and-not XP grow 09 and CM5 and CM4 grow 09 shrink 09 calma CV4 32 * layer m6 CM6 and-not CRM and-not CR6 and-not XP labels CM6 calma CM6 37 * layer rm6 CRM and CM6 calma CRM 70 * layer rm6 CR6 and CM6 calma CR6 76 * layer pseudo_rmetal6 CR6 and-not rm6 calma CR6 76 * layer m6p CM6P labels CM6P calma CM6P 85 * layer m6c CV5 and-not CTM shrink 09 and-not CV4 grow 09 and-not XP grow 09 and CM6 and CM5 grow 09 shrink 09 calma CV5 36 * layer mic CV5 and CTM and-not XP grow 27 and CTM layer mi CTM and-not CRM and-not CRI and-not XP labels CTM calma CTM 35 * layer rmi CRM and CTM calma CRM 70 * layer rmi CRI and CTM calma CRI 79 * layer pseudo_rmetali CRI and-not rmi calma CRI 79 * layer mic CV5 grow 5 and CTM and-not XP grow 103 and CTM and CM6 grow 09 shrink 09 calma CV5 36 * layer pad XP labels pad calma XP 26 * layer glass COG and-not COP and-not XP labels COG calma COG 52 * layer nfi CFI and CWN labels CFI calma CFI 27 * layer pfi CFI and-not CWN labels CFI calma CFI 27 * layer sb CSB and-not CWNR labels CSB calma CSB 29 * layer pres CPG and CSB calma CPG 46 * layer anres CAA and CSN and-not CWNR and-not CTA and CSB and-not CPG and-not CWN and-not CSP and-not CBA calma CAA 43 * layer apres CAA and CSP and-not CWNR and-not CTA and CSB and-not CPG and CWN and-not CSN and-not CPS and-not CBA calma CAA 43 * layer comment CX labels CX calma CX 63 * calma CTA 60 * calma CRW 65 * calma CRG 67 * calma CRD 66 * calma CRE 64 * calma CRF 71 * calma CRS 72 * calma CRT 73 * calma CRQ 74 * calma CRP 75 * calma CR6 76 * calma CRI 79 * calma CRM 70 * style lambda=0.09() scalefactor 9 layer nwell CWN and-not CWNR and-not CTA labels CWN calma CWN 42 * layer rnw CWN and-not CWNR and CRE and-not CSB and-not CRD and-not CAA and-not CPG calma CWN 42 * layer rnw CWN and-not CWNR and CRW and-not CRD and-not CAA and-not CPG calma CWN 42 * layer pseudo_rnwell CRW and-not CRE calma CRW 65 * calma CWNR 91 * layer nwr CWND calma CWND 92 * layer pseudo_nwr CRNW calma CRNW 93 * ignore CWP calma CWP 41 * layer diff CAA and-not CTA and-not CPG and-not CWNR and-not COP and-not CSN and-not CSP labels CAA calma CAA 43 * layer tran CAA and-not CTA and CPG and-not CWNR and-not COP and-not CSN and-not CSP labels CAA calma CAA 43 * calma CSN 45 * calma CSP 44 * layer ndiff CAA and CSN and-not CWNR and-not CTA and-not CRE and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer rnd CAA and CSN and-not CWNR and CRE and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA calma CAA 43 * layer rnd CAA and CSN and-not CWNR and CRD and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA calma CAA 43 * layer pseudo_rndiff CRD and-not CRE and-not CAA and-not CSB and-not CPG and-not CWN and-not CSP and CSN and-not CBA calma CRD 66 * layer pdiff CAA and CSP and-not CWNR and-not CTA and-not CRE and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer rpd CAA and CSP and-not CWNR and CRE and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CAA 43 * layer rpd CAA and CSP and-not CWNR and CRD and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CAA 43 * layer pseudo_rpdiff CRD and-not CRE and-not CAA and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CRD 66 * layer nfet CAA and CSN and-not CWNR and-not CTA and CPG and-not CEL and-not CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer pfet CAA and CSP and-not CWNR and-not CTA and CPG and-not CEL and CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer nsd CAA and CSN and-not CWNR and-not CTA and CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer psd CAA and CSP and-not CWNR and-not CTA and-not CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer nwsd CAA and CSN and CWNR shrink 108 and-not CTA and CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer ndc CAA and CSN and CCA and-not CV1 and-not CWNR and-not CTA and-not CWN and CM1 grow 09 grow 9 shrink 9 calma CCA 48 * layer ndc CAA and CSN and CCC and-not CV1 and-not CWNR and-not CTA and-not CWN and CM1 grow 09 grow 9 shrink 9 calma CCC 25 * layer nsc CAA and CSN and CCA and-not CV1 and-not CWNR and-not CTA and CWN and CM1 grow 09 grow 9 shrink 9 calma CCA 48 * layer nsc CAA and CSN and CCC and-not CV1 and-not CWNR and-not CTA and CWN and CM1 grow 09 grow 9 shrink 9 calma CCC 25 * layer nwsc CAA and CSN and-not CV1 and CWNR shrink 108 and-not CTA and CCA and CWN and CM1 grow 18 grow 9 shrink 9 calma CCA 48 * layer nwsc CAA and CSN and-not CV1 and CWNR shrink 105 and-not CTA and CCC and CWN and CM1 grow 18 grow 9 shrink 9 calma CCC 25 * layer pdc CAA and CSP and CCA and-not CV1 and-not CTA and-not CPS and CWN and CM1 grow 09 grow 9 shrink 9 calma CCA 48 * layer pdc CAA and CSP and CCC and-not CV1 and-not CTA and-not CPS and CWN and CM1 grow 09 grow 9 shrink 9 calma CCC 25 * layer psc CAA and CSP and CCA and-not CV1 and-not CTA and-not CPS and-not CWN and CM1 grow 09 grow 9 shrink 9 calma CCA 48 * layer psc CAA and CSP and CCC and-not CV1 and-not CWNR and-not CTA and-not CPS and-not CWN and CM1 grow 09 grow 9 shrink 9 calma CCC 25 * layer ndc CAA and CSN and CCA and CV1 and CV2 and-not CV3 and-not CWNR and-not CTA and-not CWN and CM1 grow 09 grow 9 shrink 9 calma CCA 48 * layer ndc CAA and CSN and CCC and CV1 and CV2 and-not CV3 and-not CWNR and-not CTA and-not CWN and CM1 grow 09 grow 9 shrink 9 calma CCC 25 * layer nsc CAA and CSN and CCA and CV1 and CV2 and-not CV3 and-not CWNR and-not CTA and CWN and CM1 grow 09 grow 9 shrink 9 calma CCA 48 * layer nsc CAA and CSN and CCC and CV1 and CV2 and-not CV3 and-not CWNR and-not CTA and CWN and CM1 grow 09 grow 9 shrink 9 calma CCC 25 * layer nwsc CAA and CSN and CV1 and CV2 and-not CV3 and CWNR shrink 108 and-not CTA and CCA and CWN and CM1 grow 18 grow 9 shrink 9 calma CCA 48 * layer nwsc CAA and CSN and CV1 and CV2 and-not CV3 and CWNR shrink 105 and-not CTA and CCC and CWN and CM1 grow 18 grow 9 shrink 9 calma CCC 25 * layer pdc CAA and CSP and CCA and CV1 and CV2 and-not CV3 and-not CTA and-not CPS and CWN and CM1 grow 09 grow 9 shrink 9 calma CCA 48 * layer pdc CAA and CSP and CCC and CV1 and CV2 and-not CV3 and-not CTA and-not CPS and CWN and CM1 grow 09 grow 9 shrink 9 calma CCC 25 * layer psc CAA and CSP and CCA and CV1 and CV2 and-not CV3 and-not CTA and-not CPS and-not CWN and CM1 grow 09 grow 9 shrink 9 calma CCA 48 * layer psc CAA and CSP and CCC and CV1 and CV2 and-not CV3 and-not CWNR and-not CTA and-not CPS and-not CWN and CM1 grow 09 grow 9 shrink 9 calma CCC 25 * layer ndc CAA and CSN and CCA and CV1 and CV2 and CV3 and CV4 and-not CV5 and-not CWNR and-not CTA and-not CWN and CM1 grow 09 grow 9 shrink 9 calma CCA 48 * layer ndc CAA and CSN and CCC and CV1 and CV2 and CV3 and CV4 and-not CV5 and-not CWNR and-not CTA and-not CWN and CM1 grow 09 grow 9 shrink 9 calma CCC 25 * layer nsc CAA and CSN and CCA and CV1 and CV2 and CV3 and CV4 and-not CV5 and-not CWNR and-not CTA and CWN and CM1 grow 09 grow 9 shrink 9 calma CCA 48 * layer nsc CAA and CSN and CCC and CV1 and CV2 and CV3 and CV4 and-not CV5 and-not CWNR and-not CTA and CWN and CM1 grow 09 grow 9 shrink 9 calma CCC 25 * layer nwsc CAA and CSN and CV1 and CV2 and CV3 and CV4 and-not CV5 and CWNR shrink 108 and-not CTA and CCA and CWN and CM1 grow 18 grow 9 shrink 9 calma CCA 48 * layer nwsc CAA and CSN and CV1 and CV2 and CV3 and CV4 and-not CV5 and CWNR shrink 105 and-not CTA and CCC and CWN and CM1 grow 18 grow 9 shrink 9 calma CCC 25 * layer pdc CAA and CSP and CCA and CV1 and CV2 and CV3 and CV4 and-not CV5 and-not CTA and-not CPS and CWN and CM1 grow 09 grow 9 shrink 9 calma CCA 48 * layer pdc CAA and CSP and CCC and CV1 and CV2 and CV3 and CV4 and-not CV5 and-not CTA and-not CPS and CWN and CM1 grow 09 grow 9 shrink 9 calma CCC 25 * layer psc CAA and CSP and CCA and CV1 and CV2 and CV3 and CV4 and-not CV5 and-not CTA and-not CPS and-not CWN and CM1 grow 09 grow 9 shrink 9 calma CCA 48 * layer psc CAA and CSP and CCC and CV1 and CV2 and CV3 and CV4 and-not CV5 and-not CWNR and-not CTA and-not CPS and-not CWN and CM1 grow 09 grow 9 shrink 9 calma CCC 25 * layer poly CPG and-not CRE labels CPG calma CPG 46 * layer rp CPG and CRE and-not CSB calma CPG 46 * layer rp CPG and CRG calma CPG 46 * layer pseudo_rpoly CRG and-not CRE calma CRG 67 * layer pc CCP and-not CV1 and CPG and-not CPC and-not CEL and-not CAA grow 09 and CM1 grow 9 shrink 9 calma CCP 47 * layer pc CCC and-not CV1 and CPG and-not CPC and-not CEL and-not CAA grow 09 and CM1 grow 9 shrink 9 calma CCC 25 * layer pc CCP and CV1 and CV2 and-not CV3 and CPG and-not CPC and-not CEL and-not CAA grow 09 and CM1 grow 9 shrink 9 calma CCP 47 * layer pc CCC and CV1 and CV2 and-not CV3 and CPG and-not CPC and-not CEL and-not CAA grow 09 and CM1 grow 9 shrink 9 calma CCC 25 * layer pc CCP and CV1 and CV2 and CV3 and CV4 and-not CV5 and CPG and-not CPC and-not CEL and-not CAA grow 09 and CM1 grow 9 shrink 9 calma CCP 47 * layer pc CCC and CV1 and CV2 and CV3 and CV4 and-not CV5 and CPG and-not CPC and-not CEL and-not CAA grow 09 and CM1 grow 9 shrink 9 calma CCC 25 * layer gc CCP and-not CPG and-not CPC calma CCP 47 * layer gc CCP and-not CM1 calma CCP 47 * layer gc CCA and-not COP and-not CAA and-not CBA calma CCA 48 * layer gc CCA and-not COP and-not CM1 calma CCA 48 * layer gc CCC and-not COP and-not CPG and-not CPC and-not CEL and-not CAA and-not CBA calma CCC 25 * layer gc CCC and-not COP and-not CM1 calma CCC 25 * layer gc CCE and-not CPC and-not CEL calma CCE 55 * layer gc CCE and-not CM1 calma CCE 55 * layer gv1 CV1 and-not COP and-not CM1 calma CV1 50 * layer gv1 CV1 and-not COP and-not CM2 calma CV1 50 * layer gv2 CV2 and-not COP and-not CM2 calma CV2 61 * layer gv2 CV2 and-not COP and-not CM3 calma CV2 61 * layer gv3 CV3 and-not COP and-not CM3 calma CV3 30 * layer gv3 CV3 and-not COP and-not CM4 calma CV3 30 * layer gv4 CV4 and-not CTM and-not COP and-not CM4 calma CV4 32 * layer gv4 CV4 and-not CTM and-not COP and-not CM5 calma CV4 32 * layer gv5 CV5 and-not CTM and-not COP and-not CM5 calma CV5 36 * layer gv5 CV5 and-not CTM and-not COP and-not CM6 calma CV5 36 * layer gvi CV5 and CTM and-not COP and-not CM6 calma CV5 36 * layer m2c CV1 and-not CV2 and-not CCC and-not CCE and-not CCP and-not CCA and-not XP grow 09 and CM2 and CM1 grow 5 shrink 5 calma CV1 50 * layer m2c CV1 and CV2 and CV3 and-not CV4 and-not CCC and-not CCE and-not CCP and-not CCA and-not XP grow 09 and CM2 and CM1 grow 5 shrink 5 calma CV1 50 * layer m2c CV1 and CV5 and CV4 and CV3 and CV2 and-not CCC and-not CCE and-not CCP and-not CCA and-not XP grow 09 and CM2 and CM1 grow 5 shrink 5 calma CV1 50 * layer m1 CM1 and-not CRM and-not CRF and-not XP labels CM1 calma CM1 49 * layer rm1 CRM and CM1 calma CRM 70 * layer rm1 CRF and CM1 calma CRF 71 * layer pseudo_rmetal1 CRF and-not rm1 calma CRF 71 * layer m1p CMFP labels CMFP calma CMFP 81 * layer m2 CM2 and-not CRM and-not CRS and-not XP labels CM2 calma CM2 51 * layer rm2 CRM and CM2 calma CRM 70 * layer rm2 CRS and CM2 calma CRS 72 * layer pseudo_rmetal2 CRS and-not rm2 calma CRS 72 * layer m2p CMSP labels CMSP calma CMSP 82 * layer fp 100 calma 100 100 * layer fm1 101 calma 101 101 * layer fm2 102 calma 102 102 * layer fm3 103 calma 103 103 * layer fm4 104 calma 104 104 * layer fm5 105 calma 105 105 * layer fm6 106 calma 106 106 * layer fa 109 calma 109 109 * layer fn 119 calma 119 119 * layer fapm 110 calma 110 110 * layer m3c CV2 and-not CV3 and-not CV1 and-not XP grow 09 and CM3 and CM2 grow 5 shrink 5 calma CV2 61 * layer m3c CV2 and CV3 and CV4 and-not CV5 and-not CV1 and-not XP grow 09 and CM3 and CM2 grow 5 shrink 5 calma CV2 61 * layer m3 CM3 and-not CRM and-not CRT and-not XP labels CM3 calma CM3 62 * layer rm3 CRM and CM3 calma CRM 70 * layer rm3 CRT and CM3 calma CRT 73 * layer pseudo_rmetal3 CRT and-not rm3 calma CRT 73 * layer m3p CMTP labels CMTP calma CMTP 83 * layer m4 CM4 and-not CRM and-not CRQ and-not XP labels CM4 calma CM4 31 * layer rm4 CRM and CM4 calma CRM 70 * layer rm4 CRQ and CM4 calma CRQ 74 * layer pseudo_rmetal4 CRQ and-not rm4 calma CRQ 74 * layer m4p CMQP labels CMQP calma CMQP 84 * layer m4c CV3 and-not CV4 and-not CV2 and-not XP grow 09 and CM4 and CM3 grow 09 shrink 09 calma CV3 30 * layer m4c CV3 and CV4 and CV5 and-not CV2 and-not XP grow 09 and CM4 and CM3 grow 09 shrink 09 calma CV3 30 * layer m5 CM5 and-not CRM and-not CRP and-not XP labels CM5 calma CM5 33 * layer rm5 CRM and CM5 calma CRM 70 * layer rm5 CRP and CM5 calma CRP 75 * layer pseudo_rmetal5 CRP and-not rm5 calma CRP 75 * layer m5p CMPP labels CMPP calma CMPP 85 * layer m5c CV4 and-not CV5 and-not CV3 and-not XP grow 09 and CM5 and CM4 grow 09 shrink 09 calma CV4 32 * layer m6 CM6 and-not CRM and-not CR6 and-not XP labels CM6 calma CM6 37 * layer rm6 CRM and CM6 calma CRM 70 * layer rm6 CR6 and CM6 calma CR6 76 * layer pseudo_rmetal6 CR6 and-not rm6 calma CR6 76 * layer m6p CM6P labels CM6P calma CM6P 85 * layer m6c CV5 and-not CTM shrink 09 and-not CV4 grow 09 and-not XP grow 09 and CM6 and CM5 grow 09 shrink 09 calma CV5 36 * layer mic CV5 and CTM and-not XP grow 27 and CTM layer mi CTM and-not CRM and-not CRI and-not XP labels CTM calma CTM 35 * layer rmi CRM and CTM calma CRM 70 * layer rmi CRI and CTM calma CRI 79 * layer pseudo_rmetali CRI and-not rmi calma CRI 79 * layer mic CV5 grow 5 and CTM and-not XP grow 103 and CTM and CM6 grow 09 shrink 09 calma CV5 36 * layer pad XP labels pad calma XP 26 * layer glass COG and-not COP and-not XP labels COG calma COG 52 * layer nfi CFI and CWN labels CFI calma CFI 27 * layer pfi CFI and-not CWN labels CFI calma CFI 27 * layer sb CSB and-not CWNR labels CSB calma CSB 29 * layer pres CPG and CSB calma CPG 46 * layer anres CAA and CSN and-not CWNR and-not CTA and CSB and-not CPG and-not CWN and-not CSP and-not CBA calma CAA 43 * layer apres CAA and CSP and-not CWNR and-not CTA and CSB and-not CPG and CWN and-not CSN and-not CPS and-not CBA calma CAA 43 * layer comment CX labels CX calma CX 63 * calma CTA 60 * calma CRW 65 * calma CRG 67 * calma CRD 66 * calma CRE 64 * calma CRF 71 * calma CRS 72 * calma CRT 73 * calma CRQ 74 * calma CRP 75 * calma CR6 76 * calma CRI 79 * calma CRM 70 * style lambda=0.09(c) scalefactor 9 layer nwell CWN and-not CWNR and-not CTA labels CWN calma CWN 42 * layer rnw CWN and-not CWNR and CRE and-not CSB and-not CRD and-not CAA and-not CPG calma CWN 42 * layer rnw CWN and-not CWNR and CRW and-not CRD and-not CAA and-not CPG calma CWN 42 * layer pseudo_rnwell CRW and-not CRE calma CRW 65 * calma CWNR 91 * layer nwr CWND calma CWND 92 * layer pseudo_nwr CRNW calma CRNW 93 * ignore CWP calma CWP 41 * layer diff CAA and-not CTA and-not CPG and-not CWNR and-not COP and-not CSN and-not CSP labels CAA calma CAA 43 * layer tran CAA and-not CTA and CPG and-not CWNR and-not COP and-not CSN and-not CSP labels CAA calma CAA 43 * calma CSN 45 * calma CSP 44 * layer ndiff CAA and CSN and-not CWNR and-not CTA and-not CRE and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer rnd CAA and CSN and-not CWNR and CRE and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA calma CAA 43 * layer rnd CAA and CSN and-not CWNR and CRD and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA calma CAA 43 * layer pseudo_rndiff CRD and-not CRE and-not CAA and-not CSB and-not CPG and-not CWN and-not CSP and CSN and-not CBA calma CRD 66 * layer pdiff CAA and CSP and-not CWNR and-not CTA and-not CRE and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer rpd CAA and CSP and-not CWNR and CRE and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CAA 43 * layer rpd CAA and CSP and-not CWNR and CRD and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CAA 43 * layer pseudo_rpdiff CRD and-not CRE and-not CAA and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CRD 66 * layer nfet CAA and CSN and-not CWNR and-not CTA and CPG and-not CEL and-not CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer pfet CAA and CSP and-not CWNR and-not CTA and CPG and-not CEL and CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer nsd CAA and CSN and-not CWNR and-not CTA and CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer psd CAA and CSP and-not CWNR and-not CTA and-not CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer nwsd CAA and CSN and CWNR shrink 108 and-not CTA and CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer gc CCA and CPG and-not CEL calma CCA 48 * layer gc CCP and CPG and-not CEL calma CCP 47 * layer gc CCC and CPG and-not CEL calma CCC 25 * layer gc CCE and CPG and-not CEL calma CCE 55 * layer gc CCA and-not COP and-not CPC and-not CEL calma CCA 48 * layer gc CCP and-not COP and-not CPC and-not CEL calma CCP 47 * layer gc CCC and-not COP and-not CPC and-not CEL calma CCC 25 * layer gc CCE and-not COP and-not CPC and-not CEL calma CCE 55 * layer poly CPG and-not CRE labels CPG calma CPG 46 * layer rp CPG and CRE and-not CSB calma CPG 46 * layer rp CPG and CRG calma CPG 46 * layer pseudo_rpoly CRG and-not CRE calma CRG 67 * layer m1 CM1 and-not CRM and-not CRF labels CM1 calma CM1 49 * layer rm1 CRM and CM1 calma CRM 70 * layer rm1 CRF and CM1 calma CRF 71 * layer pseudo_rmetal1 CRF and-not rm1 calma CRF 71 * layer m1p CMFP labels CMFP calma CMFP 81 * layer gv1 CV1 calma CV1 50 * layer m2 CM2 and-not CRM and-not CRS labels CM2 calma CM2 51 * layer rm2 CRM and CM2 calma CRM 70 * layer rm2 CRS and CM2 calma CRS 72 * layer pseudo_rmetal2 CRS and-not rm2 calma CRS 72 * layer m2p CMSP labels CMSP calma CMSP 82 * layer fp 100 calma 100 100 * layer fm1 101 calma 101 101 * layer fm2 102 calma 102 102 * layer fm3 103 calma 103 103 * layer fm4 104 calma 104 104 * layer fm5 105 calma 105 105 * layer fm6 106 calma 106 106 * layer fa 109 calma 109 109 * layer fn 119 calma 119 119 * layer fapm 110 calma 110 110 * layer gv2 CV2 calma CV2 61 * layer m3 CM3 and-not CRM and-not CRT labels CM3 calma CM3 62 * layer rm3 CRM and CM3 calma CRM 70 * layer rm3 CRT and CM3 calma CRT 73 * layer pseudo_rmetal3 CRT and-not rm3 calma CRT 73 * layer m3p CMTP labels CMTP calma CMTP 83 * layer gv3 CV3 calma CV3 30 * layer m4 CM4 and-not CRM and-not CRQ labels CM4 calma CM4 31 * layer rm4 CRM and CM4 calma CRM 70 * layer rm4 CRQ and CM4 calma CRQ 74 * layer pseudo_rmetal4 CRQ and-not rm4 calma CRQ 74 * layer m4p CMQP labels CMQP calma CMQP 84 * layer gv4 CV4 calma CV4 32 * layer m5 CM5 and-not CRM and-not CRP labels CM5 calma CM5 33 * layer rm5 CRM and CM5 calma CRM 70 * layer rm5 CRP and CM5 calma CRP 75 * layer pseudo_rmetal5 CRP and-not rm5 calma CRP 75 * layer m5p CMPP labels CMPP calma CMPP 85 * layer gv5 CV5 and-not CTM calma CV5 36 * layer m6 CM6 and-not CRM and-not CR6 labels CM6 calma CM6 37 * layer rm6 CRM and CM6 calma CRM 70 * layer rm6 CR6 and CM6 calma CR6 76 * layer pseudo_rmetal6 CR6 and-not rm6 calma CR6 76 * layer m6p CM6P labels CM6P calma CM6P 85 * layer gvi CV5 and CTM calma CV5 36 * layer mi CTM and-not CRM and-not CRI labels CTM calma CTM 35 * layer rmi CRM and CTM calma CRM 70 * layer rmi CRI and CTM calma CRI 79 * layer pseudo_rmetali CRI and-not rmi calma CRI 79 * layer xp XP calma XP 26 * layer glass COG and-not COP labels COG calma COG 52 * layer nfi CFI and CWN labels CFI calma CFI 27 * layer pfi CFI and-not CWN labels CFI calma CFI 27 * layer sb CSB and-not CWNR labels CSB calma CSB 29 * layer pres CPG and CSB calma CPG 46 * layer anres CAA and CSN and-not CWNR and-not CTA and CSB and-not CPG and-not CWN and-not CSP and-not CBA calma CAA 43 * layer apres CAA and CSP and-not CWNR and-not CTA and CSB and-not CPG and CWN and-not CSN and-not CPS and-not CBA calma CAA 43 * layer comment CX labels CX calma CX 63 * calma CTA 60 * calma CRW 65 * calma CRG 67 * calma CRD 66 * calma CRE 64 * calma CRF 71 * calma CRS 72 * calma CRT 73 * calma CRQ 74 * calma CRP 75 * calma CR6 76 * calma CRI 79 * calma CRM 70 * style lambda=0.09(cs) scalefactor 9 layer nwell CWN and-not CWNR and-not CTA labels CWN calma CWN 42 * layer rnw CWN and-not CWNR and CRE and-not CSB and-not CRD and-not CAA and-not CPG calma CWN 42 * layer rnw CWN and-not CWNR and CRW and-not CRD and-not CAA and-not CPG calma CWN 42 * layer pseudo_rnwell CRW and-not CRE calma CRW 65 * calma CWNR 91 * layer nwr CWND calma CWND 92 * layer pseudo_nwr CRNW calma CRNW 93 * ignore CWP calma CWP 41 * layer diff CAA and-not CTA and-not CPG and-not CWNR and-not COP and-not CSN and-not CSP labels CAA calma CAA 43 * layer tran CAA and-not CTA and CPG and-not CWNR and-not COP and-not CSN and-not CSP labels CAA calma CAA 43 * layer nselect CSN calma CSN 45 * layer pselect CSP calma CSP 44 * layer ndiff CAA and CSN and-not CWNR and-not CTA and-not CRE and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer rnd CAA and CSN and-not CWNR and CRE and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA calma CAA 43 * layer rnd CAA and CSN and-not CWNR and CRD and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA calma CAA 43 * layer pseudo_rndiff CRD and-not CRE and-not CAA and-not CSB and-not CPG and-not CWN and-not CSP and CSN and-not CBA calma CRD 66 * layer pdiff CAA and CSP and-not CWNR and-not CTA and-not CRE and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer rpd CAA and CSP and-not CWNR and CRE and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CAA 43 * layer rpd CAA and CSP and-not CWNR and CRD and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CAA 43 * layer pseudo_rpdiff CRD and-not CRE and-not CAA and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CRD 66 * layer nfet CAA and CSN and-not CWNR and-not CTA and CPG and-not CEL and-not CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer pfet CAA and CSP and-not CWNR and-not CTA and CPG and-not CEL and CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer nsd CAA and CSN and-not CWNR and-not CTA and CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer psd CAA and CSP and-not CWNR and-not CTA and-not CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer nwsd CAA and CSN and CWNR shrink 108 and-not CTA and CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer gc CCA and CPG and-not CEL calma CCA 48 * layer gc CCP and CPG and-not CEL calma CCP 47 * layer gc CCC and CPG and-not CEL calma CCC 25 * layer gc CCE and CPG and-not CEL calma CCE 55 * layer gc CCA and-not COP and-not CPC and-not CEL calma CCA 48 * layer gc CCP and-not COP and-not CPC and-not CEL calma CCP 47 * layer gc CCC and-not COP and-not CPC and-not CEL calma CCC 25 * layer gc CCE and-not COP and-not CPC and-not CEL calma CCE 55 * layer poly CPG and-not CRE labels CPG calma CPG 46 * layer rp CPG and CRE and-not CSB calma CPG 46 * layer rp CPG and CRG calma CPG 46 * layer pseudo_rpoly CRG and-not CRE calma CRG 67 * layer m1 CM1 and-not CRM and-not CRF labels CM1 calma CM1 49 * layer rm1 CRM and CM1 calma CRM 70 * layer rm1 CRF and CM1 calma CRF 71 * layer pseudo_rmetal1 CRF and-not rm1 calma CRF 71 * layer m1p CMFP labels CMFP calma CMFP 81 * layer gv1 CV1 calma CV1 50 * layer m2 CM2 and-not CRM and-not CRS labels CM2 calma CM2 51 * layer rm2 CRM and CM2 calma CRM 70 * layer rm2 CRS and CM2 calma CRS 72 * layer pseudo_rmetal2 CRS and-not rm2 calma CRS 72 * layer m2p CMSP labels CMSP calma CMSP 82 * layer fp 100 calma 100 100 * layer fm1 101 calma 101 101 * layer fm2 102 calma 102 102 * layer fm3 103 calma 103 103 * layer fm4 104 calma 104 104 * layer fm5 105 calma 105 105 * layer fm6 106 calma 106 106 * layer fa 109 calma 109 109 * layer fn 119 calma 119 119 * layer fapm 110 calma 110 110 * layer gv2 CV2 calma CV2 61 * layer m3 CM3 and-not CRM and-not CRT labels CM3 calma CM3 62 * layer rm3 CRM and CM3 calma CRM 70 * layer rm3 CRT and CM3 calma CRT 73 * layer pseudo_rmetal3 CRT and-not rm3 calma CRT 73 * layer m3p CMTP labels CMTP calma CMTP 83 * layer gv3 CV3 calma CV3 30 * layer m4 CM4 and-not CRM and-not CRQ labels CM4 calma CM4 31 * layer rm4 CRM and CM4 calma CRM 70 * layer rm4 CRQ and CM4 calma CRQ 74 * layer pseudo_rmetal4 CRQ and-not rm4 calma CRQ 74 * layer m4p CMQP labels CMQP calma CMQP 84 * layer gv4 CV4 calma CV4 32 * layer m5 CM5 and-not CRM and-not CRP labels CM5 calma CM5 33 * layer rm5 CRM and CM5 calma CRM 70 * layer rm5 CRP and CM5 calma CRP 75 * layer pseudo_rmetal5 CRP and-not rm5 calma CRP 75 * layer m5p CMPP labels CMPP calma CMPP 85 * layer gv5 CV5 and-not CTM calma CV5 36 * layer m6 CM6 and-not CRM and-not CR6 labels CM6 calma CM6 37 * layer rm6 CRM and CM6 calma CRM 70 * layer rm6 CR6 and CM6 calma CR6 76 * layer pseudo_rmetal6 CR6 and-not rm6 calma CR6 76 * layer m6p CM6P labels CM6P calma CM6P 85 * layer gvi CV5 and CTM calma CV5 36 * layer mi CTM and-not CRM and-not CRI labels CTM calma CTM 35 * layer rmi CRM and CTM calma CRM 70 * layer rmi CRI and CTM calma CRI 79 * layer pseudo_rmetali CRI and-not rmi calma CRI 79 * layer xp XP calma XP 26 * layer glass COG and-not COP labels COG calma COG 52 * layer nfi CFI and CWN labels CFI calma CFI 27 * layer pfi CFI and-not CWN labels CFI calma CFI 27 * layer sb CSB and-not CWNR labels CSB calma CSB 29 * layer pres CPG and CSB calma CPG 46 * layer anres CAA and CSN and-not CWNR and-not CTA and CSB and-not CPG and-not CWN and-not CSP and-not CBA calma CAA 43 * layer apres CAA and CSP and-not CWNR and-not CTA and CSB and-not CPG and CWN and-not CSN and-not CPS and-not CBA calma CAA 43 * layer comment CX labels CX calma CX 63 * calma CTA 60 * calma CRW 65 * calma CRG 67 * calma CRD 66 * calma CRE 64 * calma CRF 71 * calma CRS 72 * calma CRT 73 * calma CRQ 74 * calma CRP 75 * calma CR6 76 * calma CRI 79 * calma CRM 70 * style lambda=0.09(cps) scalefactor 9 layer nwell CWN and-not CWNR and-not CTA labels CWN calma CWN 42 * layer rnw CWN and-not CWNR and CRE and-not CSB and-not CRD and-not CAA and-not CPG calma CWN 42 * layer rnw CWN and-not CWNR and CRW and-not CRD and-not CAA and-not CPG calma CWN 42 * layer pseudo_rnwell CRW and-not CRE calma CRW 65 * calma CWNR 91 * layer nwr CWND calma CWND 92 * layer pseudo_nwr CRNW calma CRNW 93 * layer pwell CWP and-not CTA labels CWP calma CWP 41 * layer diff CAA and-not CTA and-not CPG and-not CWNR and-not COP and-not CSN and-not CSP labels CAA calma CAA 43 * layer tran CAA and-not CTA and CPG and-not CWNR and-not COP and-not CSN and-not CSP labels CAA calma CAA 43 * layer nselect CSN calma CSN 45 * layer pselect CSP calma CSP 44 * layer ndiff CAA and CSN and-not CWNR and-not CTA and-not CRE and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer rnd CAA and CSN and-not CWNR and CRE and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA calma CAA 43 * layer rnd CAA and CSN and-not CWNR and CRD and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA calma CAA 43 * layer pseudo_rndiff CRD and-not CRE and-not CAA and-not CSB and-not CPG and-not CWN and-not CSP and CSN and-not CBA calma CRD 66 * layer pdiff CAA and CSP and-not CWNR and-not CTA and-not CRE and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer rpd CAA and CSP and-not CWNR and CRE and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CAA 43 * layer rpd CAA and CSP and-not CWNR and CRD and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CAA 43 * layer pseudo_rpdiff CRD and-not CRE and-not CAA and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CRD 66 * layer nfet CAA and CSN and-not CWNR and-not CTA and CPG and-not CEL and-not CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer pfet CAA and CSP and-not CWNR and-not CTA and CPG and-not CEL and CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer nsd CAA and CSN and-not CWNR and-not CTA and CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer psd CAA and CSP and-not CWNR and-not CTA and-not CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer nwsd CAA and CSN and CWNR shrink 108 and-not CTA and CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer gc CCA and CPG and-not CEL calma CCA 48 * layer gc CCP and CPG and-not CEL calma CCP 47 * layer gc CCC and CPG and-not CEL calma CCC 25 * layer gc CCE and CPG and-not CEL calma CCE 55 * layer gc CCA and-not COP and-not CPC and-not CEL calma CCA 48 * layer gc CCP and-not COP and-not CPC and-not CEL calma CCP 47 * layer gc CCC and-not COP and-not CPC and-not CEL calma CCC 25 * layer gc CCE and-not COP and-not CPC and-not CEL calma CCE 55 * layer poly CPG and-not CRE labels CPG calma CPG 46 * layer rp CPG and CRE and-not CSB calma CPG 46 * layer rp CPG and CRG calma CPG 46 * layer pseudo_rpoly CRG and-not CRE calma CRG 67 * layer m1 CM1 and-not CRM and-not CRF labels CM1 calma CM1 49 * layer rm1 CRM and CM1 calma CRM 70 * layer rm1 CRF and CM1 calma CRF 71 * layer pseudo_rmetal1 CRF and-not rm1 calma CRF 71 * layer m1p CMFP labels CMFP calma CMFP 81 * layer gv1 CV1 calma CV1 50 * layer m2 CM2 and-not CRM and-not CRS labels CM2 calma CM2 51 * layer rm2 CRM and CM2 calma CRM 70 * layer rm2 CRS and CM2 calma CRS 72 * layer pseudo_rmetal2 CRS and-not rm2 calma CRS 72 * layer m2p CMSP labels CMSP calma CMSP 82 * layer fp 100 calma 100 100 * layer fm1 101 calma 101 101 * layer fm2 102 calma 102 102 * layer fm3 103 calma 103 103 * layer fm4 104 calma 104 104 * layer fm5 105 calma 105 105 * layer fm6 106 calma 106 106 * layer fa 109 calma 109 109 * layer fn 119 calma 119 119 * layer fapm 110 calma 110 110 * layer gv2 CV2 calma CV2 61 * layer m3 CM3 and-not CRM and-not CRT labels CM3 calma CM3 62 * layer rm3 CRM and CM3 calma CRM 70 * layer rm3 CRT and CM3 calma CRT 73 * layer pseudo_rmetal3 CRT and-not rm3 calma CRT 73 * layer m3p CMTP labels CMTP calma CMTP 83 * layer gv3 CV3 calma CV3 30 * layer m4 CM4 and-not CRM and-not CRQ labels CM4 calma CM4 31 * layer rm4 CRM and CM4 calma CRM 70 * layer rm4 CRQ and CM4 calma CRQ 74 * layer pseudo_rmetal4 CRQ and-not rm4 calma CRQ 74 * layer m4p CMQP labels CMQP calma CMQP 84 * layer gv4 CV4 calma CV4 32 * layer m5 CM5 and-not CRM and-not CRP labels CM5 calma CM5 33 * layer rm5 CRM and CM5 calma CRM 70 * layer rm5 CRP and CM5 calma CRP 75 * layer pseudo_rmetal5 CRP and-not rm5 calma CRP 75 * layer m5p CMPP labels CMPP calma CMPP 85 * layer gv5 CV5 and-not CTM calma CV5 36 * layer m6 CM6 and-not CRM and-not CR6 labels CM6 calma CM6 37 * layer rm6 CRM and CM6 calma CRM 70 * layer rm6 CR6 and CM6 calma CR6 76 * layer pseudo_rmetal6 CR6 and-not rm6 calma CR6 76 * layer m6p CM6P labels CM6P calma CM6P 85 * layer gvi CV5 and CTM calma CV5 36 * layer mi CTM and-not CRM and-not CRI labels CTM calma CTM 35 * layer rmi CRM and CTM calma CRM 70 * layer rmi CRI and CTM calma CRI 79 * layer pseudo_rmetali CRI and-not rmi calma CRI 79 * layer xp XP calma XP 26 * layer glass COG and-not COP labels COG calma COG 52 * layer nfi CFI and CWN labels CFI calma CFI 27 * layer pfi CFI and-not CWN labels CFI calma CFI 27 * layer sb CSB and-not CWNR labels CSB calma CSB 29 * layer pres CPG and CSB calma CPG 46 * layer anres CAA and CSN and-not CWNR and-not CTA and CSB and-not CPG and-not CWN and-not CSP and-not CBA calma CAA 43 * layer apres CAA and CSP and-not CWNR and-not CTA and CSB and-not CPG and CWN and-not CSN and-not CPS and-not CBA calma CAA 43 * layer comment CX labels CX calma CX 63 * calma CTA 60 * calma CRW 65 * calma CRG 67 * calma CRD 66 * calma CRE 64 * calma CRF 71 * calma CRS 72 * calma CRT 73 * calma CRQ 74 * calma CRP 75 * calma CR6 76 * calma CRI 79 * calma CRM 70 * style lambda=0.09(cp) scalefactor 9 layer nwell CWN and-not CWNR and-not CTA labels CWN calma CWN 42 * layer rnw CWN and-not CWNR and CRE and-not CSB and-not CRD and-not CAA and-not CPG calma CWN 42 * layer rnw CWN and-not CWNR and CRW and-not CRD and-not CAA and-not CPG calma CWN 42 * layer pseudo_rnwell CRW and-not CRE calma CRW 65 * calma CWNR 91 * layer nwr CWND calma CWND 92 * layer pseudo_nwr CRNW calma CRNW 93 * layer pwell CWP and-not CTA labels CWP calma CWP 41 * layer diff CAA and-not CTA and-not CPG and-not CWNR and-not COP and-not CSN and-not CSP labels CAA calma CAA 43 * layer tran CAA and-not CTA and CPG and-not CWNR and-not COP and-not CSN and-not CSP labels CAA calma CAA 43 * calma CSN 45 * calma CSP 44 * layer ndiff CAA and CSN and-not CWNR and-not CTA and-not CRE and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer rnd CAA and CSN and-not CWNR and CRE and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA calma CAA 43 * layer rnd CAA and CSN and-not CWNR and CRD and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA calma CAA 43 * layer pseudo_rndiff CRD and-not CRE and-not CAA and-not CSB and-not CPG and-not CWN and-not CSP and CSN and-not CBA calma CRD 66 * layer pdiff CAA and CSP and-not CWNR and-not CTA and-not CRE and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer rpd CAA and CSP and-not CWNR and CRE and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CAA 43 * layer rpd CAA and CSP and-not CWNR and CRD and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CAA 43 * layer pseudo_rpdiff CRD and-not CRE and-not CAA and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CRD 66 * layer nfet CAA and CSN and-not CWNR and-not CTA and CPG and-not CEL and-not CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer pfet CAA and CSP and-not CWNR and-not CTA and CPG and-not CEL and CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer nsd CAA and CSN and-not CWNR and-not CTA and CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer psd CAA and CSP and-not CWNR and-not CTA and-not CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer nwsd CAA and CSN and CWNR shrink 108 and-not CTA and CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer gc CCA and CPG and-not CEL calma CCA 48 * layer gc CCP and CPG and-not CEL calma CCP 47 * layer gc CCC and CPG and-not CEL calma CCC 25 * layer gc CCE and CPG and-not CEL calma CCE 55 * layer gc CCA and-not COP and-not CPC and-not CEL calma CCA 48 * layer gc CCP and-not COP and-not CPC and-not CEL calma CCP 47 * layer gc CCC and-not COP and-not CPC and-not CEL calma CCC 25 * layer gc CCE and-not COP and-not CPC and-not CEL calma CCE 55 * layer poly CPG and-not CRE labels CPG calma CPG 46 * layer rp CPG and CRE and-not CSB calma CPG 46 * layer rp CPG and CRG calma CPG 46 * layer pseudo_rpoly CRG and-not CRE calma CRG 67 * layer m1 CM1 and-not CRM and-not CRF labels CM1 calma CM1 49 * layer rm1 CRM and CM1 calma CRM 70 * layer rm1 CRF and CM1 calma CRF 71 * layer pseudo_rmetal1 CRF and-not rm1 calma CRF 71 * layer m1p CMFP labels CMFP calma CMFP 81 * layer gv1 CV1 calma CV1 50 * layer m2 CM2 and-not CRM and-not CRS labels CM2 calma CM2 51 * layer rm2 CRM and CM2 calma CRM 70 * layer rm2 CRS and CM2 calma CRS 72 * layer pseudo_rmetal2 CRS and-not rm2 calma CRS 72 * layer m2p CMSP labels CMSP calma CMSP 82 * layer fp 100 calma 100 100 * layer fm1 101 calma 101 101 * layer fm2 102 calma 102 102 * layer fm3 103 calma 103 103 * layer fm4 104 calma 104 104 * layer fm5 105 calma 105 105 * layer fm6 106 calma 106 106 * layer fa 109 calma 109 109 * layer fn 119 calma 119 119 * layer fapm 110 calma 110 110 * layer gv2 CV2 calma CV2 61 * layer m3 CM3 and-not CRM and-not CRT labels CM3 calma CM3 62 * layer rm3 CRM and CM3 calma CRM 70 * layer rm3 CRT and CM3 calma CRT 73 * layer pseudo_rmetal3 CRT and-not rm3 calma CRT 73 * layer m3p CMTP labels CMTP calma CMTP 83 * layer gv3 CV3 calma CV3 30 * layer m4 CM4 and-not CRM and-not CRQ labels CM4 calma CM4 31 * layer rm4 CRM and CM4 calma CRM 70 * layer rm4 CRQ and CM4 calma CRQ 74 * layer pseudo_rmetal4 CRQ and-not rm4 calma CRQ 74 * layer m4p CMQP labels CMQP calma CMQP 84 * layer gv4 CV4 calma CV4 32 * layer m5 CM5 and-not CRM and-not CRP labels CM5 calma CM5 33 * layer rm5 CRM and CM5 calma CRM 70 * layer rm5 CRP and CM5 calma CRP 75 * layer pseudo_rmetal5 CRP and-not rm5 calma CRP 75 * layer m5p CMPP labels CMPP calma CMPP 85 * layer gv5 CV5 and-not CTM calma CV5 36 * layer m6 CM6 and-not CRM and-not CR6 labels CM6 calma CM6 37 * layer rm6 CRM and CM6 calma CRM 70 * layer rm6 CR6 and CM6 calma CR6 76 * layer pseudo_rmetal6 CR6 and-not rm6 calma CR6 76 * layer m6p CM6P labels CM6P calma CM6P 85 * layer gvi CV5 and CTM calma CV5 36 * layer mi CTM and-not CRM and-not CRI labels CTM calma CTM 35 * layer rmi CRM and CTM calma CRM 70 * layer rmi CRI and CTM calma CRI 79 * layer pseudo_rmetali CRI and-not rmi calma CRI 79 * layer xp XP calma XP 26 * layer glass COG and-not COP labels COG calma COG 52 * layer nfi CFI and CWN labels CFI calma CFI 27 * layer pfi CFI and-not CWN labels CFI calma CFI 27 * layer sb CSB and-not CWNR labels CSB calma CSB 29 * layer pres CPG and CSB calma CPG 46 * layer anres CAA and CSN and-not CWNR and-not CTA and CSB and-not CPG and-not CWN and-not CSP and-not CBA calma CAA 43 * layer apres CAA and CSP and-not CWNR and-not CTA and CSB and-not CPG and CWN and-not CSN and-not CPS and-not CBA calma CAA 43 * layer comment CX labels CX calma CX 63 * calma CTA 60 * calma CRW 65 * calma CRG 67 * calma CRD 66 * calma CRE 64 * calma CRF 71 * calma CRS 72 * calma CRT 73 * calma CRQ 74 * calma CRP 75 * calma CR6 76 * calma CRI 79 * calma CRM 70 * style fill-only scalefactor 9 # scalefactor 100 layer fp 100 calma 100 100 * layer fm1 101 calma 101 101 * layer fm2 102 calma 102 102 * layer fm3 103 calma 103 103 * layer fm4 104 calma 104 104 * layer fm5 105 calma 105 105 * layer fm6 106 calma 106 106 * layer fa 109 or fb calma 109 109 * layer fn 119 calma 119 119 * layer fapm 110 calma 110 110 * end mzrouter style irouter # layer hCost vCost jogCost hintCost layer metal6 2 1 2 1 layer metal5 1 2 2 1 layer metal4 2 1 2 1 layer metal3 1 2 2 1 layer metal2 2 1 2 1 layer metal1 2 3 2 1 layer poly 10 10 11 1 contact m6contact metal6 metal5 2 contact m5contact metal5 metal4 3 contact m4contact metal4 metal3 4 contact m3contact metal3 metal2 5 contact m2contact metal2 metal1 6 contact pcontact metal1 poly 7 notactive poly pcontact style garouter layer m2 32 64 256 1 layer m1 64 32 256 1 contact m2contact metal1 metal2 1024 end drc style tsmc_180 scalefactor 90 width nwell 1080 \ "N-well width < 1.08um (Mosis #1.1)" width rnw 960 \ "rnwell (for resistor L/W extraction) width < 0.96um (Mosis #1.1)" width nwr 960 \ "nwr (for Fig1b resistor L/W extraction) width < 0.96 (Mosis #Fig1bX)" width pwell 1080 \ "P-well width < 1.08um (Mosis #1.1)" width diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a 270 \ "Diffusion width < 0.27um (Mosis #2.1)" edge4way nsd,nwsd,nsc/a,nwsc/a pdiff,apres,rpd,pdc/a 360 ~(nsd,nwsd,nsc/a,nwsc/a)/active pdiff,apres,rpd,pdc/a 360 \ "P-Diffusion width in N-Ohmic < 0.36um (Mosis #2.1)" active edge4way psd,psc/a ndiff,anres,rnd,ndc/a 360 ~(psd,psc/a)/active ndiff,anres,rnd,ndc/a 360 \ "N-Diffusion width in P-Ohmic < 0.36um (Mosis #2.1)" active edge4way pdiff,apres,rpd,pdc/a nsd,nwsd,nsc/a,nwsc/a 360 ~(pdiff,apres,rpd,pdc/a)/active nsd,nwsd,nsc/a,nwsc/a 360 \ "N-Ohmic width in P-Diffusion < 0.36um (Mosis #2.1)" active edge4way ndiff,anres,rnd,ndc/a psd,psc/a 360 ~(ndiff,anres,rnd,ndc/a)/active psd,psc/a 360 \ "P-Ohmic width in N-Diffusion < 0.36um (Mosis #2.1)" active width poly,fp,pp,pn,pres,rp,pc/a,ppc/a,pnc/a,nfet,pfet,fet 180 \ "Poly width < 0.18 (Mosis #3.1)" width nselect 360 \ "N-Select width < 0.36um (Mosis #4.4)" width pselect 360 \ "P-Select width < 0.36um (Mosis #4.4)" width ndiff,anres,rnd,ndc/a,nsd,nsc/a 270 \ "N-Diffusion,N-Ohmic width < 0.27um (Mosis #4.4)" width pdiff,apres,rpd,pdc/a,psd,psc/a 270 \ "P-Diffusion,P-Ohmic width < 0.27um (Mosis #4.4)" width pc/m1 360 \ "Poly contact width < 0.36um (Mosis #5.1)" width ppc/m1 360 \ "Poly contact width < 0.36um (Mosis #5.1)" width pnc/m1 360 \ "Poly contact width < 0.36um (Mosis #5.1)" width gc 180 \ "GC contact width < 0.18um (Mosis #6.1)" width ndc/m1 360 \ "Diffusion contact width < 0.36um (Mosis #6.1)" width nsc/m1 360 \ "Diffusion contact width < 0.36um (Mosis #6.1)" width nwsc/m1 3604 \ "Diffusion contact width < 0.36um (Mosis #6.1)" width nwsc 540 \ "nwr (for Fig1b resistor) active Contact width < 0.54um (Mosis #Fig1b)" width pdc/m1 360 \ "Diffusion contact width < 0.36um (Mosis #6.1)" width psc/m1 360 \ "Diffusion contact width < 0.36um (Mosis #6.1)" width m1,fm1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,ppc/m1,pnc/m1,m2c/m1 300 \ "Metal1 width < 0.3um (Mosis #7.1)" width gv1 200 \ "GV1 via width < 0.2um (Mosis #8.1)" width m2c/m1 400 \ "Metal2 contact width < 0.4um (Mosis #8.1)" width m2,fm2,rm2,m2c/m2,m3c/m2 300 \ "Metal2 width < 0.3um (Mosis #9.1)" width gv2 200 \ "GV2 via width < 0.2um (Mosis #14.1)" width m3c/m2 400 \ "Metal3 contact width < 0.4um (Mosis #14.1)" width m3,fm3,rm3,m3c/m3,m4c/m3 300 \ "Metal3 width < 0.3um (Mosis #15.1)" width sb,pres,anres,apres 360 \ "Silicide-Block width < 0.36 (Mosis #20.1)" width pres 450 \ "Silicide-Block polyR width < 0.45um (Mosis #20.6)" width anres,apres 540 \ "Silicide-Block activeR width < 0.54um (Mosis #20.16)" width gv3 200 \ "GV3 via width < 0.2um (Mosis #21.3)" width m4c/m3 400 \ "Metal4 contact width < 0.4um (Mosis #21.3)" width m4,fm4,rm4,m4c/m4,m5c/m4 300 \ "Metal4 width < 0.3um (Mosis #22.1)" width nfi,pfi 360 \ "N/P_field-implant width < 0.36um (Mosis #29.1)" width gv4 200 \ "GV4 via width < 0.2um (Mosis #25.4)" width m5c/m4 400 \ "Metal5 contact width < 0.4um (Mosis #25.4)" width m5,fm5,rm5,m5c/m5,m6c/m5 300 \ "Metal5 width < 0.3um (Mosis #26.2)" width gv5 300 \ "GV5 via width < 0.3um (Mosis #29.4)" width m6c/m5 500 \ "Metal6 contact width < 0.5um (Mosis #29.4)" width m6,fm6,rm6,m6c/m6,mic/m6,pad 500 \ "Metal6 width < 0.5um (Mosis #30.2)" width gvi 360 \ "MIM via width < 0.36um (Mosis #28.4)" width mic/mi 900 \ "MIM contact width < 0.9um (Mosis #28.4)" width mi,mic/mi 4050 \ "MIM width < 4.05um (Mosis #28.1)" #--------!--------- spacing nwell nwell 540 touching_ok \ "N-well(at-same-potential) spacing < 0.54um (Mosis #1.3)" spacing pwell pwell 540 touching_ok \ "P-well(at-same-potential) spacing < 0.54um (Mosis #1.3)" spacing rnw nwell 1620 touching_illegal \ "rnw (for resistor L/W extraction) spacing to N-well < 1.62um (Mosis #2.3)" spacing nwr nwell 1620 touching_illegal \ "nwr (for Fig1b resistor L/W extraction) spacing to N-well < 1.62um (Mosis #2.3)" edge4way ~(pwell)/well pwell 1 ~(rnw)/active 0 0 \ "P-well cannot touch rnw (for resistor L/W extraction) (Mosis #1.4)" active edge4way ~(pwell)/well pwell 1 ~(nwr)/active 0 0 \ "P-well cannot touch nwr (for Fig1b resistor L/W extraction) (Mosis #1.4)" active spacing diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a 270 touching_ok \ "Diffusion spacing < 0.27um (Mosis #2.2)" spacing nwell ndiff,anres,rnd,nfet,ndc/a 54 touching_illegal \ "N-well spacing to N-Diffusion < 0.54 (Mosis #2.3)" spacing pwell pdiff,apres,rpd,pfet,pdc/a 54 touching_illegal \ "P-well spacing to P-Diffusion < 0.54 (Mosis #2.3)" spacing ndiff,anres,rnd,nfet,ndc/a pdiff,apres,rpd,pfet,pdc/a 1080 touching_illegal \ "N-Diffusion spacing to P-Diffusion < 1.08um (Mosis #2.3+2.3)" edge4way ~(nwell)/well nwell 540 ~(pdiff,apres,rpd,pfet,pdc/a)/active nwell 540 \ "N-well overlap of P-Diffusion < 0.54um (Mosis #2.4)" active edge4way ~(pwell)/well pwell 540 ~(ndiff,anres,rnd,nfet,ndc/a)/active pwell 540 \ "P-well overlap of N-Diffusion < 0.54um (Mosis #2.4)" active edge4way ~(nwell)/well nwell 270 ~(nsd,nwsd,nsc/a,nwsc/a)/active nwell 270 \ "N-well overlap of N-Ohmic < 0.27um (Mosis #2.4)" active edge4way ~(pwell)/well pwell 270 ~(psd,psc/a)/active pwell 270 \ "P-well overlap of P-Ohmic < 0.27um (Mosis #2.4)" active spacing ndiff,anres,rnd,ndc/a nsd,nwsd,nsc/a,nwsc/a 810 touching_illegal \ "N-Diffusion spacing to N-Ohmic < 0.81um (Mosis #2.3+2.4)" spacing pdiff,apres,rpd,pdc/a psd,psc/a 810 touching_illegal \ "P-Diffusion spacing to P-Ohmic < 0.81um (Mosis #2.3+2.4)" spacing nwell psd,psc/a 270 touching_illegal \ "N-well spacing to P-Ohmic < 0.27um (Mosis #2.4)" spacing pwell nsd,nwsd,nsc/a,nwsc/a 270 touching_illegal \ "P-well spacing to N-Ohmic < 0.27um (Mosis #2.4)" spacing psd,psc/a rnw,prnw 270 touching_illegal \ "P-Ohmic spacing to rnw,prnw < 0.27um (Mosis #2.4)" spacing psd,psc/a nwr,pnwr 270 touching_illegal \ "P-Ohmic spacing to nwr,pnwr (for Fig1b Resistor) < 0.27um (Mosis #2.4)" spacing nsd,nwsd,nsc/a,nwsc/a psd,psc/a 540 touching_illegal \ "N-Ohmic spacing to P-Ohmic < 0.54um (Mosis #2.4+2.4)" spacing ndiff,anres,rnd,nfet,ndc/a,nfet psd,psc/a 360 touching_ok \ "N-Diffusion spacing to P-Ohmic < 0.36um (Mosis #2.5)" spacing pdiff,apres,rpd,pfet,pdc/a,pfet nsd,nwsd,nsc/a,nwsc/a 360 touching_ok \ "P-Diffusion spacing to N-Ohmic < 0.36um (Mosis #2.5)" spacing poly,pp,pn,pres,rp,pc/a,ppc/a,pnc/a,nfet,pfet,fet poly,pp,pn,pres,rp,pc/a,ppc/a,pnc/a,nfet,pfet,fet 270 touching_ok \ "Poly spacing < 0.27um (Mosis #3.2)" spacing poly,pp,pn,pres,rp,pc/a,ppc/a,pnc/a,nfet,pfet,fet fp,fapm 270 touching_illegal \ "Poly spacing to fill layer (fp) < 0.27um (Mosis #3.2)" spacing fp fp 360 touching_ok \ "Poly fill layer (fp) spacing < 0.36um (Mosis #0)" spacing nfet,pfet,fet nfet,pfet,fet 360 touching_ok \ "Poly spacing < 0.36um (Mosis #3.2.a)" edge4way nfet,pfet,fet space/active,poly,fp,pp,pn,pres,rp,pc/a,ppc/a,pnc/a 270 poly,fp,pp,pn,pres,rp,pc/a,ppc/a,pnc/a 0 0 \ "Poly overhang of Transistor < 0.27um (Mosis #3.3)" active edge4way nfet,pfet,fet space/active,ndiff,anres,rnd,ndc/a,pdiff,apres,rpd,pdc/a 360 ndiff,anres,rnd,ndc/a,pdiff,apres,rpd,pdc/a,nfet,pfet,fet 0 0 \ "N-Diffusion,P-Diffusion overhang of Transistor < 0.36um (Mosis #3.4)" active edge4way poly,fp,pp,pn,rp,pc/a,ppc/a,pnc/a ~(poly,fp,pp,pn,pres,rp,pc/a,ppc/a,pnc/a,nfet,pfet,fet,prp)/active 90 space space 90 \ "Poly spacing to Diffusion < 0.09um (Mosis #3.5)" edge4way nfet ~(nfet)/active 270 ~(pselect)/select ~(nfet)/active 270 \ "N-Transistor space to P-Select < 0.27um (Mosis #4.1)" select edge4way pfet ~(pfet)/active 270 ~(nselect)/select ~(pfet)/active 270 \ "P-Transistor space to N-Select < 0.27um (Mosis #4.1)" select edge4way nfet ~(nfet)/active 360 ~(psd,psc/a)/active ~(nfet)/active 270 \ "N-Transistor space to P-Ohmic < 0.36um (Mosis #4.1)" active edge4way pfet ~(pfet)/active 360 ~(nsd,nwsd,nsc/a,nwsc/a)/active ~(pfet)/active 270 \ "P-Transistor space to N-Ohmic < 0.36um (Mosis #4.1)" active #PEZ edge4way psd,psc/a space ~(nfet)/active space \ #PEZ "P-Ohmic space to N-Transistor < (Mosis #4.1)" active #PEZ edge4way nsd,nwsd,nsc/a,nwsc/a space ~(pfet)/active space \ #PEZ "N-Ohmic space to P-Transistor < (Mosis #4.1)" active edge4way ~(nselect,pselect)/select nselect,pselect 180 ~(diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a)/active nselect,pselect 180 \ "N-Select,P-Select overlap of Diffusion < 0.18um (Mosis #4.2_)" active edge4way ~(nselect,pselect)/select nselect,pselect 90 ~(pp,pn)/active nselect,pselect 90 \ "N-Select,P-Select overlap of poly biased with Nselect or Pselect < 0.09um (Mosis #4.2_)" active #SOC edge4way ~(nselect)/select nselect 1 ~(gc)/contact nselect 1 \ #SOC "N-Select overlap of Generic contact < 1 (Mosis #?.?__)" contact #SOC edge4way ~(pselect)/select pselect 1 ~(gc)/contact pselect 1 \ #SOC "P-Select overlap of Generic contact < 1 (Mosis #?.?__)" contact edge4way space nselect,pselect 180 ~(ndiff,anres,rnd,nfet,ndc/a)/active nselect 180 \ "N-Select space to N-Diffusion < 0.18um (Mosis #4.2a)" active edge4way nselect,pselect space 180 ~(ndiff,anres,rnd,nfet,ndc/a)/active nselect 180 \ "N-Select space to N-Diffusion < 0.18um (Mosis #4.2b)" active edge4way nselect,pselect space 180 ~(ndiff,anres,rnd,nfet,ndc/a)/active space,nselect,pselect 180 \ "N-Select space to N-Diffusion < 0.18um (Mosis #4.2c)" active edge4way space nselect,pselect 180 ~(pdiff,apres,rpd,pfet,pdc/a)/active pselect 180 \ "P-Select space to P-Diffusion < 0.18um (Mosis #4.2aa)" active edge4way nselect,pselect space 180 ~(pdiff,apres,rpd,pfet,pdc/a)/active pselect 180 \ "P-Select space to P-Diffusion < 0.18um (Mosis #4.2bb)" active edge4way nselect,pselect space 180 ~(pdiff,apres,rpd,pfet,pdc/a)/active space,nselect,pselect 180 \ "P-Select space to P-Diffusion < 0.18um (Mosis #4.2cc)" active #SOC edge4way ~(nselect)/select nselect 0 ~(ndc/a,pdc/a,psc/a,nsc/a,nwsc/a)/active nselect 0 \ #SOC "N-Select overlap of Diffusion contact < 0 (Mosis #?.?__)" active #SOC edge4way ~(pselect,dps)/select pselect,dps 0 ~(ndc/a,pdc/a,psc/a,nsc/a,nwsc/a)/active pselect,dps 0 \ #SOC "P-Select overlap of Diffusion contact < 0 (Mosis #?.?__)" active edge4way space nselect 90 ~(pn)/active nselect 90 \ "N-Select space to Poly < 0.09um (Mosis #4.2d)" active edge4way space pselect 90 ~(pp)/active pselect 90 \ "P-Select space to Poly < 0.09um (Mosis #4.2d)" active edge4way nselect space 90 ~(pn)/active nselect 90 \ "N-Select space to Poly < 0.09um (Mosis #4.2ep)" active edge4way pselect space 90 ~(pp)/active pselect 90 \ "P-Select space to Poly < 0.09um (Mosis #4.2ep)" active edge4way nselect space 90 ~(pn)/active space,nselect 90 \ "N-Select space to Poly < 0.09um (Mosis #4.2f)" active edge4way pselect space 90 ~(pp)/active space,pselect 90 \ "P-Select space to Poly < 0.09um (Mosis #4.2f)" active area nsd,nwsd,psd,nsc/a,nwsc/a,psc/a 1440 270 \ "Ohmic-Diffusion area < 1.44um^2 (Mosis #+++)" edge4way pn space 90 ~(pselect)/select space 90 \ "poly with Nselect spacing to P-Select < 0.9um (Mosis #4.2y)" select edge4way pp space 90 ~(nselect)/select space 90 \ "poly with Pselect spacing to N-Select < 0.9um (Mosis #4.2y)" select edge4way diff space 180 nselect space 180 \ "N-Select must overlap Diffusion by 2 (Mosis #4.2)" select edge4way diff space 180 pselect space 180 \ "P-Select must overlap Diffusion by 2 (Mosis #4.2)" select edge4way ndiff,anres,rnd,nfet,ndc/a space 180 ~(pselect)/select space 180 \ "P-Select space to N-Diffusion < 0.18um (Mosis #4.2e)" select edge4way pdiff,apres,rpd,pfet,pdc/a space 180 ~(nselect)/select space 180 \ "N-Select space to P-Diffusion < 0.18um (Mosis #4.2e)" select edge4way ~(pdiff,apres,rpd,pfet,pdc/a,psd,psc/a)/active pdiff,apres,rpd,pfet,pdc/a,psd,psc/a 1 ~(nselect)/select 0 0 \ "N-Select cannot touch P-Diffusion,P-Ohmic (Mosis #4.2f)" select edge4way ~(ndiff,anres,rnd,nfet,ndc/a,nsd,nwsd,nsc/a,nwsc/a)/active ndiff,anres,rnd,nfet,ndc/a,nsd,nwsd,nsc/a,nwsc/a 1 ~(pselect)/select 0 0 \ "P-Select cannot touch N-Diffusion,N-Ohmic (Mosis #4.2f)" select spacing nselect nselect 360 touching_ok \ "N-Select spacing < 0.36um (Mosis #4.4)" spacing pselect pselect 360 touching_ok \ "P-Select spacing < 0.36um (Mosis #4.4)" edge4way ndiff,anres,rnd,ndc/a psd,psc/a 180 ~(ndiff,anres,rnd,ndc/a)/active 0 0 \ "P-Ohmic(that touches N-Diffusion) width < 0.18um (Mosis #4.4)" edge4way pdiff,apres,rpd,pdc/a nsd,nwsd,nsc/a,nwsc/a 180 ~(pdiff,apres,rpd,pdc/a)/active 0 0 \ "N-Ohmic(that touches P-Diffusion) width < 0.18um (Mosis #4.4)" edge4way gc ~(gc)/contact 90 poly,fp,pp,pn,pres,rp,pc/a,ppc/a,pnc/a,diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a ~(gc)/contact 90 \ "Poly,Diffusion overlap of GC contact < 0.09um (Mosis #5.2)" active edge4way ~(nwsd)/active nwsd 180 ~(gc)/contact nwsd 180 \ "nwr (for Fig1b resistor) active overlap of GC contact < 0.18um (Mosis #Fig1b)" contact spacing nwr gc 450 touching_illegal \ "nwr (for Fig1b resistor) spacing to GC contact < 0.45um (Mosis #Fig1b)" spacing nwr ndc/a,nsc/a,nwsc/a 270 touching_illegal \ "nwr (for Fig1b resistor) spacing to Diffusion contact < 0.27um (Mosis #Fig1b)" edge4way gc space 1 poly,fp,pp,pn,pres,rp,pc/a,ppc/a,pnc/a,diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a space 1 \ "one of: Poly,Diffusion must overlap GC contact by 1 (Mosis #5.2a,6.2a)" active edge4way ~(poly,fp,pp,pn,pres,rp,pc/a,ppc/a,pnc/a,diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a)/active poly,fp,pp,pn,pres,rp,pc/a,ppc/a,pnc/a,diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a 1 ~(gc)/contact 0 0 \ "Edge to one of: Poly,Diffusion cannot touch GC contact (Mosis #5.2a,6.2a)" contact spacing gc gc 360 touching_ok \ "Generic contact spacing < 0.36um (Mosis #5.3)" edge4way ~(gc)/contact gc 1 ~(ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,ppc/m1,pnc/m1)/metal1 0 0 \ "GC contact cannot touch Metal1 contacts (Mosis #0)" metal1 spacing gv1 m2c/m2 180 touching_illegal \ "GV1 via spacing to Metal2 contacts < 0.18um (Mosis #14.2)" spacing poly,fp,pp,pn,pres,rp,pc/a,ppc/a,pnc/a pc/a,ppc/a,pnc/a 360 touching_ok \ "Poly spacing to Poly contact < 0.36um (Mosis #5.5.b)" edge4way gc ~(gc)/contact 90 diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a,poly,fp,pp,pn,pres,rp,pc/a,ppc/a,pnc/a ~(gc)/contact 90 \ "Diffusion,Poly overlap of GC contact < 0.09um (Mosis #6.2)" active spacing gc pc/a,ppc/a,pnc/a,ndc/a,pdc/a,psc/a,nsc/a,nwsc/a 270 touching_illegal \ "Generic contact spacing to Poly contact,Diffusion contact < 0.27um (Mosis #5.3)" spacing pc/a,ppc/a,pnc/a pc/a,ppc/a,pnc/a 180 touching_ok \ "Poly contact spacing < 0.18um (Mosis #6.3)" spacing ndc/a,pdc/a,psc/a,nsc/a,nwsc/a ndc/a,pdc/a,psc/a,nsc/a,nwsc/a 180 touching_ok \ "Diffusion contact spacing < 0.18um (Mosis #6.3)" edge4way ndiff,anres,rnd,ndc/a ~(ndiff,anres,rnd,ndc/a)/active 90 ~(gc)/contact ~(ndiff,anres,rnd,ndc/a)/active 90 \ "N-Diffusion space to Generic contact < 0.09um (Mosis #6.2x)" contact edge4way pdiff,apres,rpd,pdc/a ~(pdiff,apres,rpd,pdc/a)/active 90 ~(gc)/contact ~(pdiff,apres,rpd,pdc/a)/active 90 \ "P-Diffusion space to Generic contact < 0.09um (Mosis #6.2x)" contact edge4way nsd,nwsd,nsc/a,nwsc/a ~(nsd,nwsd,nsc/a,nwsc/a)/active 90 ~(gc)/contact ~(nsd,nwsd,nsc/a,nwsc/a)/active 90 \ "N-Ohmic space to Generic contact < 0.09um (Mosis #6.2x)" contact edge4way psd,psc/a ~(psd,psc/a)/active 90 ~(gc)/contact ~(psd,psc/a)/active 90 \ "P-Ohmic space to Generic contact < 0.09um (Mosis #6.2x)" contact spacing nsc/m1,nwsc/m1 pdc/m1 180 touching_illegal \ "nsc spacing to pdc < 0.18um (Mosis #6.3)" spacing psc/m1 ndc/m1 180 touching_illegal \ "psc spacing to ndc < 0.18um (Mosis #6.3)" spacing nfet,pfet ndc/a,pdc/a,psc/a,nsc/a,nwsc/a 90 touching_illegal \ "N-Transistor,P-Transistor spacing to Diffusion contact < 0.09um (Mosis #6.4)" spacing nfet,pfet gc 180 touching_illegal \ "N-Transistor,P-Transistor spacing to Generic contact < 0.18um (Mosis #6.4)" spacing diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a pc/a,ppc/a,pnc/a 90 touching_illegal \ "Diffusion spacing to Poly contact < 0.09um (Mosis #6.5.b)" spacing diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a,nfet,pfet ndc/a,pdc/a,psc/a,nsc/a,nwsc/a 360 touching_ok \ "Diffusion spacing to Diffusion contact < 0.36um (Mosis #6.5.b)" spacing pc/a,ppc/a,pnc/a ndc/a,pdc/a,psc/a,nsc/a,nwsc/a 180 touching_illegal \ "pc/a,ppc/a,pnc/a,pm12c/a,ppm12c/a,pnm12c/a spacing to ndc/a,pdc/a,psc/a,nsc/a,nwsc/a < 0.18um (Mosis #6.7)" spacing m1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,ppc/m1,pnc/m1,m2c/m1 m1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,ppc/m1,pnc/m1,m2c/m1 300 touching_ok \ "Metal1 spacing < 0.3um (Mosis #7.2)" spacing m1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,ppc/m1,pnc/m1,m2c/m1 fm1,fapm 300 touching_illegal \ "Metal1 spacing to fill layer (fm1) < 0.3um (Mosis #7.2)" spacing fm1 fm1 360 touching_ok \ "Metal1 fill layer (fm1) spacing < 0.36um (Mosis #0)" edge4way gc space 1 m1,fm1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,ppc/m1,pnc/m1,m2c/m1 space 100 \ "Metal1 must overlap GC contact by 0.1um (Mosis #7.3,7.4)" metal1 edge4way ~(m1,fm1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,ppc/m1,pnc/m1,m2c/m1)/metal1 m1,fm1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,ppc/m1,pnc/m1,m2c/m1 1 ~(gc)/contact 0 0 \ "Metal1(edge) cannot touch GC contact (Mosis #7.3+7.4)" contact spacing gv1 gv1 270 touching_ok \ "GV1 via spacing < 0.27um (Mosis #8.2)" edge4way gv1 ~(gv1)/via1 1 m1,fm1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,ppc/m1,pnc/m1,m2c/m1 ~(gv1)/via1 100 \ "Metal1 overlap of GV1 via < 0.1um (Mosis #8.3)" metal1 edge4way gv1 space 1 m1,fm1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,ppc/m1,pnc/m1,m2c/m1 space 100 \ "Metal1 must overlap GV1 via by 0.1um (Mosis #8.3)" metal1 edge4way ~(m1,fm1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,ppc/m1,pnc/m1,m2c/m1)/metal1 m1,fm1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,ppc/m1,pnc/m1,m2c/m1 1 ~(gv1)/via1 0 0 \ "Metal1(edge) cannot touch GV1 via (Mosis #8.3)" via1 spacing m2,rm2,m2c/m2,m3c/m2 m2,rm2,m2c/m2,m3c/m2 300 touching_ok \ "Metal2 spacing < 0.3um (Mosis #9.2)" spacing m2,rm2,m2c/m2,m3c/m2 fm2,fapm 360 touching_illegal \ "Metal2 spacing to fill layer (fm2) < 0.36um (Mosis #9.2)" spacing fm2 fm2 360 touching_ok \ "Metal2 fill layer (fm2) spacing < 0.36um (Mosis #0)" edge4way gv1 space 100 m2,fm2,rm2,m2c/m2,m3c/m2 space 100 \ "Metal2 must overlap GV1 via by 0.1um (Mosis #9.3)" metal2 edge4way ~(m2,fm2,rm2,m2c/m2,m3c/m2)/metal2 m2,fm2,rm2,m2c/m2,m3c/m2 1 ~(gv1)/via1 0 0 \ "Metal2(edge) cannot touch GV1 via (Mosis #9.3)" via1 width glass 900 \ "COG width < 0.9um (Mosis #10.2)" edge4way ~(pad)/metal6 pad 6030 ~(glass)/oxide pad 6030 \ "pad overlap of COG < 6.03um (Mosis #10.3)" oxide spacing gv2 gv2 300 touching_ok \ "GV2 via spacing < 0.3um (Mosis #14.2)" spacing gv2 m3c/m2 180 touching_illegal \ "GV2 via spacing to Metal3 contact < 0.18um (Mosis #14.2)" edge4way gv2 space 100 m2,fm2,rm2,m2c/m2,m3c/m2 space 100 \ "Metal2 must overlap GV2 via by 0.1um (Mosis #14.3)" metal2 edge4way ~(m2,fm2,rm2,m2c/m2,m3c/m2)/metal2 m2,fm2,rm2,m2c/m2,m3c/m2 1 ~(gv2)/via2 0 0 \ "Metal2(edge) cannot touch GV2 via (Mosis #14.3)" via2 spacing m3,rm3,m3c/m3,m4c/m3 m3,rm3,m3c/m3,m4c/m3 300 touching_ok \ "Metal3 spacing < 0.3um (Mosis #15.2)" spacing m3,rm3,m3c/m3,m4c/m3 fm3,fapm 360 touching_illegal \ "Metal3 spacing to fill layer (fm3) < 0.36um (Mosis #15.2)" spacing fm3 fm3 300 touching_ok \ "Metal3 fill layer (fm3) spacing < 0.3um (Mosis #0)" edge4way gv2 space 100 m3,fm3,rm3,m3c/m3,m4c/m3 space 100 \ "Metal3 must overlap GV2 via by 0.1um (Mosis #15.3)" metal3 edge4way ~(m3,fm3,rm3,m3c/m3,m4c/m3)/metal3 m3,fm3,rm3,m3c/m3,m4c/m3 1 ~(gv2)/via2 0 0 \ "Metal3(edge) cannot touch GV2 via (Mosis #15.3)" via2 spacing sb,pres,anres,apres sb,pres,anres,apres 360 touching_ok \ "Silicide-Block spacing < 0.36um (Mosis #20.2)" spacing sb,pres,anres,apres,pres,anres,apres pc/a,ppc/a,pnc/a,ndc/a,pdc/a,psc/a,nsc/a,nwsc/a 100 touching_illegal \ "Silicide-Block spacing to Diffusion contact,Poly contact < 0.1um (Mosis #20.3)" spacing sb,pres,anres,apres,pres,anres,apres gc 180 touching_illegal \ "Silicide-Block spacing to GC contact < 0.18um (Mosis #20.3)" edge4way sb,pres,anres,apres space 180 ~(diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a)/active 0 180 \ "Silicide-Block space to Diffusion < 0.18um (Mosis #20.4)" active spacing sb,pres,anres,apres,pres poly,fp,pp,pn,pres,rp,pc/a,ppc/a,pnc/a 180 touching_ok \ "Silicide-Block spacing to other Poly < 0.18um (Mosis #20.5)" edge4way sb,pres,anres,apres space 180 ~(poly,fp,pp,pn,pres,rp,pc/a,ppc/a,pnc/a)/contact sb,pres,anres,apres 180 \ "Silicide-Block space to Poly < 0.18um (Mosis #20.5x)" contact spacing sb,pres,anres,apres,pres nfet,pfet,fet 180 touching_ok \ "Silicide-Block spacing to other Transistor < 0.18um (Mosis #20.5)" edge4way sb,pres,anres,apres space 180 ~(nfet,pfet,fet)/contact sb,pres,anres,apres 180 \ "Silicide-Block space to Transistor < 0.18um (Mosis #20.5x)" contact spacing pres pres 630 touching_ok \ "Silicide-Block polyR spacing < 0.63um (Mosis #20.13)" edge4way pres,anres,apres space/active,sb 180 sb sb 180 \ "Silicide-Block overlap of Silicide-Block polyR/activeR < 0.18um (Mosis #20.15)" edge4way sb,pres,anres,apres diff,ndiff,rnd,nfet,nsd,nwsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a 270 diff,ndiff,rnd,nfet,nsd,nwsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a 0 0 \ "Diffusion overhang of Silicide-Block < 0.27um (Mosis #20.17) spacing gv3 gv3 300 touching_ok \ "GV3 via spacing < 0.3um (Mosis #21.2)" spacing gv3 m4c/m3 180 touching_illegal \ "GV3 via spacing to Metal4 contact < 0.18um (Mosis #21.2)" edge4way gv3 space 100 m3,fm3,rm3,m3c/m3,m4c/m3 space 100 \ "Metal3 must overlap GV3 via by 0.1um (Mosis #21.3)" metal3 edge4way ~(m3,fm3,rm3,m3c/m3,m4c/m3)/metal3 m3,fm3,rm3,m3c/m3,m4c/m3 1 ~(gv3)/via3 0 0 \ "Metal3(edge) cannot touch GV3 via (Mosis #21.3)" via3 spacing m4,rm4,m4c/m4,m5c/m4 m4,rm4,m4c/m4,m5c/m4 300 touching_ok \ "Metal4 spacing < 0.3um (Mosis #22.2)" spacing m4,rm4,m4c/m4,m5c/m4 fm4,fapm 300 touching_illegal \ "Metal4 spacing to fill layer (fm4) < 0.3um (Mosis #22.2)" spacing fm4 fm4 300 touching_ok \ "Metal4 fill layer (fm4) spacing < 0.3um (Mosis #0)" edge4way gv3 space 100 m4,fm4,rm4,m4c/m4,m5c/m4 space 100 \ "Metal4 must overlap GV3 via by 0.1um (Mosis #22.3)" metal4 edge4way ~(m4,fm4,rm4,m4c/m4,m5c/m4)/metal4 m4,fm4,rm4,m4c/m4,m5c/m4 1 ~(gv3)/via3 0 0 \ "Metal4(edge) cannot touch GV3 via (Mosis #22.3)" via3 spacing gv4 gv4 300 touching_ok \ "GV4 via spacing < 0.3um (Mosis #25.3)" edge4way ~(gv4)/via4 gv4 1 ~(m5c/m5)/metal5 0 0 \ "GV4 via cannot touch Metal5 contacts (Mosis #0)" metal5 edge4way gv4 space 100 m4,fm4,rm4,m4c/m4,m5c/m4 space 100 \ "Metal4 must overlap GV4 via by 0.1um (Mosis #25.4)" metal4 edge4way ~(m4,fm4,rm4,m4c/m4,m5c/m4)/metal4 m4,fm4,rm4,m4c/m4,m5c/m4 1 ~(gv4)/via4 0 0 \ "Metal4(edge) cannot touch GV4 via (Mosis #25.4)" via4 spacing m5,rm5,m5c/m5,m6c/m5 m5,rm5,m5c/m5,m6c/m5 300 touching_ok \ "Metal5 spacing < 0.3um (Mosis #26.3)" spacing m5,rm5,m5c/m5,m6c/m5 fm5,fapm 30 touching_illegal \ "Metal5 spacing to fill layer (fm5) < 0.3 (Mosis #26.3)" spacing fm5 fm5 300 touching_ok \ "Metal5 fill layer (fm5) spacing < 0.3 (Mosis #0)" edge4way space gv4 1 m5,fm5,rm5,m5c/m5,m6c/m5 0 0 \ "Metal5 must overlap GV4 via (Mosis #26.1)" metal5 edge4way gv4 space 100 m5,fm5,rm5,m5c/m5,m6c/m5 space 100 \ "Metal5 must overlap GV4 via by 0.1um (Mosis #26.1)" metal5 edge4way ~(m5,fm5,rm5,m5c/m5,m6c/m5)/metal5 m5,fm5,rm5,m5c/m5,m6c/m5 1 ~(gv4)/via4 0 0 \ "Metal5(edge) cannot touch GV4 via (Mosis #26.1)" via4 spacing gv5 gv5 300 touching_ok \ "GV5 via spacing < 0.3um (Mosis #29.3)" edge4way ~(gv5)/via5 gv5 1 ~(m6c/m6)/metal6 0 0 \ "GV5 via cannot touch Metal6 contacts (Mosis #0)" metal6 edge4way gv5 space 100 m5,fm5,rm5,m5c/m5,m6c/m5 space 100 \ "Metal5 must overlap GV5 via by 0.1um (Mosis #29.5)" metal5 edge4way ~(m5,fm5,rm5,m5c/m5,m6c/m5)/metal5 m5,fm5,rm5,m5c/m5,m6c/m5 1 ~(gv5)/via5 0 0 \ "Metal5(edge) cannot touch GV5 via (Mosis #29.5)" via5 spacing m6,rm6,m6c/m6,mic/m6,pad m6,rm6,m6c/m6,mic/m6,pad 500 touching_ok \ "Metal6 spacing < 0.5um (Mosis #30.3)" spacing m6,rm6,m6c/m6,mic/m6,pad fm6,fapm 500 touching_illegal \ "Metal6 spacing to fill layer (fm6) < 0.5um (Mosis #30.3)" spacing fm6 fm6 500 touching_ok \ "Metal6 fill layer (fm6) spacing < 0.5um (Mosis #0)" edge4way space gv5 1 m6,fm6,rm6,m6c/m6,mic/m6,pad 0 0 \ "Metal6 must overlap GV5 via (Mosis #30.1)" metal6 edge4way gv5 space 100 m6,fm6,rm6,m6c/m6,mic/m6,pad space 100 \ "Metal6 must overlap GV5 via by 0.1um (Mosis #30.1)" metal6 edge4way ~(m6,fm6,rm6,m6c/m6,mic/m6,pad)/metal6 m6,fm6,rm6,m6c/m6,mic/m6,pad 1 ~(gv5)/via5 0 0 \ "Metal6(edge) cannot touch GV5 via (Mosis #30.1)" via5 spacing mi,mic/mi mi,mic/mi 1260 touching_ok \ "MIM spacing < 1.26um (Mosis #28.2)" spacing gvi mic/mi 1800 touching_illegal \ "MIM via spacing to MIM contact < 1.8um (Mosis #28.2)" spacing mic/mi mic/mi 1530 touching_ok \ "MIM contact spacing < 1.53um (Mosis #28.2)" edge4way mi,mic/mi ~(mi,mic/mi)/metali 450 m5,fm5,rm5,m5c/m5,m6c/m5 ~(mi,mic/mi)/metali 450 \ "Metal5 overlap of MIM < 0.45um (Mosis #28.3)" metal5 edge4way gvi ~(gvi)/viai 180 m6,fm6,rm6,m6c/m6,mic/m6,pad ~(gvi)/viai 180 \ "Metal6 overlap of MIM via < 0.18um (Mosis #28.4)" metal6 spacing gvi gvi 2070 touching_ok \ "MIM via spacing < 2.07um (Mosis #28.4)" edge4way space gvi 1 mi,mic/mi 0 0 \ "MIM must overlap MIM via (Mosis #28.4)" metali edge4way ~(mi,mic/mi)/metali mi,mic/mi 1 ~(gvi)/viai 0 0 \ "MIM(edge) cannot touch MIM via (Mosis #28.4)" viai spacing mi,mic/mi m1,fm1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,ppc/m1,pnc/m1,m2c/m1 2700 touching_illegal \ "MIM spacing to Metal1 < 2.7um (Mosis #28.7)" spacing mi,mic/mi m2,fm2,rm2,m2c/m2,m3c/m2 2700 touching_illegal \ "MIM spacing to Metal2 < 2.7um (Mosis #28.7)" spacing mi,mic/mi m3,fm3,rm3,m3c/m3,m4c/m3 2700 touching_illegal \ "MIM spacing to Metal3 < 2.7um (Mosis #28.7)" spacing mi,mic/mi poly,fp,pp,pn,pres,rp,pc/a,ppc/a,pnc/a 2700 touching_illegal \ "MIM spacing to Poly < 2.7um (Mosis #28.7)" spacing mi,mic/mi diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a 2700 touching_illegal \ "MIM spacing to Diffusion < 2.7um (Mosis #28.7)" spacing mi,mic/mi gv4 450 touching_illegal \ "MIM spacing to GV4 via < 0.45um (Mosis #28.5)" spacing mi,mic/mi m5c/m4 360 touching_illegal \ "MIM spacing to Metal5 contact < 0.36um (Mosis #28.5)" spacing mi,mic/mi gv5 450 touching_illegal \ "MIM spacing to GV5 via < 0.45um (Mosis #28.5)" spacing mi,mic/mi m6c/m5 270 touching_illegal \ "MIM spacing to Metal6 contact < 0.27um (Mosis #28.5)" edge4way gvi space 270 mi,mic/mi space 270 \ "MIM must overlap MIM via by 0.27um (Mosis #28.5)" metali edge4way ~(mi,mic/mi)/metali mi,mic/mi 1 ~(gvi)/viai 0 0 \ "MIM(edge) cannot touch MIM via (Mosis #28.5)" viai spacing nfi nfi 360 touching_ok \ "N_field-implant spacing < 0.36um (Mosis #35.2)" spacing pfi pfi 360 touching_ok \ "P_field-implant spacing < 0.36um (Mosis #35.2)" spacing nfi pfi 360 touching_illegal \ "N_field-implant spacing to P_field-implant < 0.36um (Mosis #35.2)" spacing nwell,pdiff,apres,rpd,pfet,pdc/a pfi 360 touching_illegal \ "N-well,P-Diffusion spacing to P_field-implant < 0.36um (Mosis #2.1)" spacing pwell,ndiff,anres,rnd,nfet,ndc/a nfi 360 touching_illegal \ "P-well,N-Diffusion spacing to N_field-implant < 0.36um (Mosis #2.1)" edge4way ~(nwell)/well nwell 360 ~(nfi)/implant nwell 360 \ "N-well overlap of N_field-implant < 0.36um (Mosis #21.2)" implant edge4way ~(pwell)/well pwell 360 ~(pfi)/implant pwell 360 \ "P-well overlap of P_field-implant < 0.36um (Mosis #21.2)" implant spacing fa fapm 360 touching_illegal \ "fill layer fa spacing to fill layer fapm < 0.36um (Mosis #0)" width fa 2070 \ "filla width < 2.07um (Mosis #0)" width fapm 2070 \ "fillapm width < 2.07um (Mosis #0)" width fp 2070 \ "fillp width < 2.07um (Mosis #0)" width fm1 2070 \ "fillm1 width < 2.07um (Mosis #0)" width fm2 2070 \ "fillm2 width < 2.07um (Mosis #0)" width fm3 2070 \ "fillm3 width < 2.07um (Mosis #0)" width fm4 2070 \ "fillm4 width < 2.07um (Mosis #0)" width fm5 2070 \ "fillm5 width < 2.07um (Mosis #0)" width fm6 2070 \ "fillm6 width < 2.07um (Mosis #0)" edge4way fa ~(fa)/fill 1 ~(fa)/fill (~(fa),fa)/fill 1 \ "Contact not rectangular (Magic rule)" edge4way fb ~(fb)/fill 1 ~(fb)/fill (~(fb),fb)/fill 1 \ "Contact not rectangular (Magic rule)" edge4way fapm ~(fapm)/active 1 ~(fapm)/active (~(fapm),fapm)/active 1 \ "Contact not rectangular (Magic rule)" edge4way fp ~(fp)/active 1 ~(fp)/active (~(fp),fp)/active 1 \ "Contact not rectangular (Magic rule)" edge4way fm1 ~(fm1)/metal1 1 ~(fm1)/metal1 (~(fm1),fm1)/metal1 1 \ "Contact not rectangular (Magic rule)" edge4way fm2 ~(fm2)/metal2 1 ~(fm2)/metal2 (~(fm2),fm2)/metal2 1 \ "Contact not rectangular (Magic rule)" edge4way fm3 ~(fm3)/metal3 1 ~(fm3)/metal3 (~(fm3),fm3)/metal3 1 \ "Contact not rectangular (Magic rule)" edge4way fm4 ~(fm4)/metal4 1 ~(fm4)/metal4 (~(fm4),fm4)/metal4 1 \ "Contact not rectangular (Magic rule)" edge4way fm5 ~(fm5)/metal5 1 ~(fm5)/metal5 (~(fm5),fm5)/metal5 1 \ "Contact not rectangular (Magic rule)" edge4way fm6 ~(fm6)/metal6 1 ~(fm6)/metal6 (~(fm6),fm6)/metal6 1 \ "Contact not rectangular (Magic rule)" edge4way rp space/active 90 prp 0 0 \ "prp overhang of rpoly (for resistor L/W extraction) < 0.09um (Mosis #0)" active edge4way rnw space/active 90 prnw 0 0 \ "prnw overhang of rnwell (for resistor L/W extraction) < 0.09um (Mosis #0)" active edge4way nwr space/active 90 pnwr 0 0 \ "pnwr overhang of nwr (for Fig1b resistor L/W extraction) < 0.09um (Mosis #0)" active edge4way rpd space/active 90 prpd 0 0 \ "prpd overhang of rpdiff (for resistor L/W extraction) < 0.09um (Mosis #0)" active edge4way rnd space/active 90 prnd 0 0 \ "prnd overhang of rndiff (for resistor L/W extraction) < 0.09um (Mosis #0)" active edge4way rm1 space/metal1 90 prm1 0 0 \ "prm1 overhang of rmetal1 (for resistor L/W extraction) < 0.09um (Mosis #0)" metal1 edge4way rm2 space/metal2 90 prm2 0 0 \ "prm2 overhang of rmetal2 (for resistor L/W extraction) < 0.09um (Mosis #0)" metal2 edge4way rm3 space/metal3 90 prm3 0 0 \ "prm3 overhang of rmetal3 (for resistor L/W extraction) < 0.09um (Mosis #0)" metal3 edge4way rm4 space/metal4 90 prm4 0 0 \ "prm4 overhang of rmetal4 (for resistor L/W extraction) < 0.09um (Mosis #0)" metal4 edge4way rm5 space/metal5 90 prm5 0 0 \ "prm5 overhang of rmetal5 (for resistor L/W extraction) < 0.09um (Mosis #0)" metal5 edge4way rm6 space/metal6 90 prm6 0 0 \ "prm6 overhang of rmetal6 (for resistor L/W extraction) < 0.09um (Mosis #0)" metal6 edge4way rmi space/metali 90 prmi 0 0 \ "prmi overhang of rmetali (for resistor L/W extraction) < 0.09um (Mosis #0)" metali edge4way ndc/a,nsc/a,nwsc/a ~(ndc/a,nsc/a,nwsc/a)/active 1 ~(ndc/a,nsc/a,nwsc/a)/active (~(ndc/a,nsc/a,nwsc/a),ndc/a,nsc/a,nwsc/a)/active 1 \ "Contact not rectangular (Magic rule)" edge4way pdc/a,psc/a ~(pdc/a,psc/a)/active 1 ~(pdc/a,psc/a)/active (~(pdc/a,psc/a),pdc/a,psc/a)/active 1 \ "Contact not rectangular (Magic rule)" edge4way pc/a,ppc/a,pnc/a ~(pc/a,ppc/a,pnc/a)/active 1 ~(pc/a,ppc/a,pnc/a)/active (~(pc/a,ppc/a,pnc/a),pc/a,ppc/a,pnc/a)/active 1 \ "Contact not rectangular (Magic rule)" edge4way gc ~(gc)/contact 1 ~(gc)/contact (~(gc),gc)/contact 1 \ "Contact not rectangular (Magic rule)" edge4way gv1 ~(gv1)/via1 1 ~(gv1)/via1 (~(gv1),gv1)/via1 1 \ "Contact not rectangular (Magic rule)" edge4way m2c/m1 ~(m2c/m1)/metal1 1 ~(m2c/m1)/metal1 (~(m2c/m1),m2c/m1)/metal1 1 \ "Contact not rectangular (Magic rule)" edge4way gv2 ~(gv2)/via2 1 ~(gv2)/via2 (~(gv2),gv2)/via2 1 \ "Contact not rectangular (Magic rule)" edge4way m3c/m2 ~(m3c/m2)/metal2 1 ~(m3c/m2)/metal2 (~(m3c/m2),m3c/m2)/metal2 1 \ "Contact not rectangular (Magic rule)" edge4way gv3 ~(gv3)/via3 1 ~(gv3)/via3 (~(gv3),gv3)/via3 1 \ "Contact not rectangular (Magic rule)" edge4way m4c/m3 ~(m4c/m3)/metal3 1 ~(m4c/m3)/metal3 (~(m4c/m3),m4c/m3)/metal3 1 \ "Contact not rectangular (Magic rule)" edge4way gv4 ~(gv4)/via4 1 ~(gv4)/via4 (~(gv4),gv4)/via4 1 \ "Contact not rectangular (Magic rule)" edge4way m5c/m4 ~(m5c/m4)/metal4 1 ~(m5c/m4)/metal4 (~(m5c/m4),m5c/m4)/metal4 1 \ "Contact not rectangular (Magic rule)" edge4way gv5 ~(gv5)/via5 1 ~(gv5)/via5 (~(gv5),gv5)/via5 1 \ "Contact not rectangular (Magic rule)" edge4way m6c/m5 ~(m6c/m5)/metal5 1 ~(m6c/m5)/metal5 (~(m6c/m5),m6c/m5)/metal5 1 \ "Contact not rectangular (Magic rule)" edge4way gvi ~(gvi)/viai 1 ~(gvi)/viai (~(gvi),gvi)/viai 1 \ "Contact not rectangular (Magic rule)" edge4way mic/mi ~(mic/mi)/metali 1 ~(mic/mi)/metali (~(mic/mi),mic/mi)/metali 1 \ "Contact not rectangular (Magic rule)" exact_overlap gc,ndc/a,pdc/a,psc/a,nsc/a,nwsc/a,gc,pc/a,ppc/a,pnc/a,gc edge4way pad ~(pad)/m6 1 ~(pad)/m6 (~(pad),pad)/m6 1 \ "Contact not rectangular (Magic rule)" exact_overlap ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,ppc/m1,pnc/m1 exact_overlap m2c/m2 exact_overlap m3c/m3 exact_overlap m4c/m4 exact_overlap m5c/m5 exact_overlap m6c/m6 exact_overlap mic/mi exact_overlap gv1 exact_overlap gv2 exact_overlap gv3 exact_overlap gv4 exact_overlap gv5 exact_overlap gvi edge4way nfet,pfet,fet ~(nfet,pfet,fet)/active 1 ~(nfet,pfet,fet)/active nfet,pfet,fet 1 \ "Transistor cannot bend in this process (Mosis #?.?)" width m1p 36 \ "Metal1 PIN width < 0.36um (do_pins)" spacing m1p m1p 36 touching_ok \ "Metal1 PIN spacing < 0.36um (do_pins)" width m2p 36 \ "Metal2 PIN width < 0.36um (do_pins)" spacing m2p m2p 36 touching_ok \ "Metal2 PIN spacing < 0.36um (do_pins)" width m3p 36 \ "Metal3 PIN width < 0.36um (do_pins)" spacing m3p m3p 36 touching_ok \ "Metal3 PIN spacing < 0.36um (do_pins)" width m4p 36 \ "Metal4 PIN width < 0.36um (do_pins)" spacing m4p m4p 36 touching_ok \ "Metal4 PIN spacing < 0.36um (do_pins)" width m5p 36 \ "Metal5 PIN width < 0.36um (do_pins)" spacing m5p m5p 36 touching_ok \ "Metal5 PIN spacing < 0.36um (do_pins)" width m6p 540 \ "Metal6 PIN width < 0.54um (do_pins)" spacing m6p m6p 540 touching_ok \ "Metal6 PIN spacing < 0.54um (do_pins)" #CC cifstyle lambda=0.09(p) #CC cifwidth CWN 108 \ #CC "generated CIF layer CWN width will be < 12 (';cif see CWN')" #CC cifspacing CWN CWN 54 touching_ok \ #CC "generated CIF layer CWN spacing will be < 6 (';cif see CWN')" #CC cifwidth CWP 108 \ #CC "generated CIF layer CWP width will be < 12 (';cif see CWP')" #CC cifspacing CWP CWP 54 touching_ok \ #CC "generated CIF layer CWP spacing will be < 6 (';cif see CWP')" #CC cifwidth CSN 36 \ #CC "generated CIF layer CSN width will be < 4 (';cif see CSN')" #CC cifspacing CSN CSN 36 touching_ok \ #CC "generated CIF layer CSN spacing will be < 4 (';cif see CSN')" #CC cifwidth CSP 36 \ #CC "generated CIF layer CSP width will be < 4 (';cif see CSP')" #CC cifspacing CSP CSP 36 touching_ok \ #CC "generated CIF layer CSP spacing will be < 4 (';cif see CSP')" stepsize 36000 end #--------------------------------------------------- # LEF format definitions #--------------------------------------------------- lef ignore PC ignore CA routing m1 M1 m1 met1 routing m2 M2 m2 met2 routing m3 M3 m3 met3 routing m4 M4 m4 met4 routing m5 M5 m5 met5 routing m6 M6 m6 met6 contact m2c via1 V1 v1 contact m3c via2 V2 v2 contact m4c via3 V3 v3 contact m5c via4 V4 v4 contact m6c via5 V5 v5 end extract style TSMC0.18um(tsmc18)from:t24i cscale 1 lambda 9 step 100 sidehalo 8 planeorder well 0 planeorder implant 1 planeorder select 2 planeorder active 3 planeorder metal1 4 planeorder metal2 5 planeorder metal3 6 planeorder metal4 7 planeorder metal5 8 planeorder metal6 9 planeorder metali 10 planeorder oxide 11 planeorder xp 12 planeorder comment 13 planeorder contact 14 planeorder via1 15 planeorder via2 16 planeorder via3 17 planeorder via4 18 planeorder via5 19 planeorder viai 20 planeorder fill 21 resist (ndiff,anres,rnd,ndc,nsd,nwsd,nsc,nwsc)/active 6900 resist (pdiff,apres,rpd,pdc,psd,psc)/active 7800 resist (nwell)/well 946000 resist (rnw,nwr)/active 946000 resist (pwell)/well 1 resist (poly,fp,pp,pn,rp,pc,ppc,pnc,pc,ppc,pnc,nfet,pfet,fet)/active 8000 resist (pres)/active 8000 resist (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,ppc,pnc,m2c,m2c)/metal1 80 resist (m2,fm2,rm2,m2c,m3c,m3c)/metal2 80 resist (m3,fm3,rm3,m3c,m4c,m4c)/metal3 80 resist (m4,fm4,rm4,m4c,m5c,m5c)/metal4 80 resist (m5,fm5,rm5,m5c,m6c,m6c)/metal5 80 resist (m6,fm6,rm6,m6c,mic,pad)/metal6 40 contact ndc 4 11400 contact pdc 4 11900 contact pc 4 10100 contact m2c 4 5440 contact m3c 4 10560 contact m4c 4 15260 #nwell,cwell,pwell areacap (nwell)/well 0.583 #rnw areacap (rnw,nwr)/active 0.583 #ndiff # MODEL HANDLES THIS: areacap (ndiff,ndc)/active 8.092 # MODEL HANDLES THIS: overlap (ndiff,ndc)/active ~space/w 8.092 # MODEL HANDLES THIS: perimc (ndiff,ndc)/active ~(ndiff,ndc,nfet,pfet,fet)/active 23.310 # MODEL HANDLES THIS: sideoverlap (ndiff,ndc)/active ~(ndiff,ndc,nfet,pfet,fet)/active ~space/w 23.310 areacap (rnd,anres)/active 8.092 overlap (rnd,anres)/active ~space/w 8.092 perimc (rnd,anres)/active ~(rnd,anres)/active 23.310 sideoverlap (rnd,anres)/active ~(rnd,anres)/active ~space/w 23.310 #pdiff # MODEL HANDLES THIS: areacap (pdiff,pdc)/active 9.518 # MODEL HANDLES THIS: overlap (pdiff,pdc)/active ~space/w 9.518 # MODEL HANDLES THIS: perimc (pdiff,pdc)/active ~(pdiff,pdc,nfet,pfet,fet)/active 18.810 # MODEL HANDLES THIS: sideoverlap (pdiff,pdc)/active ~(pdiff,pdc,nfet,pfet,fet)/active ~space/w 18.810 areacap (rpd,apres)/active 9.518 overlap (rpd,apres)/active ~space/w 9.518 perimc (rpd,apres)/active ~(rpd,apres)/active 18.810 sideoverlap (rpd,apres)/active ~(rpd,apres)/active ~space/w 18.810 #rnw #poly # MODEL HANDLES THIS: overlap (nfet)/active (ndiff,anres,rnd,ndc)/active 68.364 # MODEL HANDLES THIS: sideoverlap (nfet)/active ~(nfet)/active (ndiff,anres,rnd,ndc)/active 62.820 # MODEL HANDLES THIS: overlap (pfet)/active (pdiff,apres,rpd,pdc)/active 66.161 # MODEL HANDLES THIS: sideoverlap (pfet)/active ~(pfet)/active (pdiff,apres,rpd,pdc)/active 61.110 sidewall (poly,fp,pp,pn,pres,rp,pc,ppc,pnc)/active ~(poly,fp,pp,pn,pres,rp,pc,ppc,pnc)/active ~(poly,fp,pp,pn,pres,rp,pc,ppc,pnc)/active (poly,fp,pp,pn,pres,rp,pc,ppc,pnc)/active 12.714 areacap (poly,fp,pp,pn,pres,rp,pc,ppc,pnc)/active 0.946 overlap (poly,fp,pp,pn,pres,rp,pc,ppc,pnc)/active ~space/w 0.946 perimc (poly,fp,pp,pn,pres,rp,pc,ppc,pnc)/active ~(poly,fp,pp,pn,pres,rp,pc,ppc,pnc)/active 2.316 sideoverlap (poly,fp,pp,pn,pres,rp,pc,ppc,pnc)/active ~(poly,fp,pp,pn,pres,rp,pc,ppc,pnc)/active ~space/w 2.316 #poly2 #rnw #metal1 sidewall (m1,fm1,rm1,ndc,pdc,pc,ppc,pnc,m2c)/metal1 ~(m1,fm1,rm1,ndc,pdc,pc,ppc,pnc,m2c)/metal1 ~(m1,fm1,rm1,ndc,pdc,pc,ppc,pnc,m2c)/metal1 (m1,fm1,rm1,ndc,pdc,pc,ppc,pnc,m2c)/metal1 23.087 areacap (m1,fm1,rm1,ndc,pdc,pc,ppc,pnc,m2c)/metal1 0.398 #metal1-sub blocked by ~space/a overlap (m1,fm1,rm1,ndc,pdc,pc,ppc,pnc,m2c)/metal1 ~space/w 0.398 ~space/a perimc (m1,fm1,rm1,ndc,pdc,pc,ppc,pnc,m2c)/metal1 ~(m1,fm1,rm1,ndc,pdc,pc,ppc,pnc,m2c)/metal1 1.162 sideoverlap (m1,fm1,rm1,ndc,pdc,pc,ppc,pnc,m2c)/metal1 ~(m1,fm1,rm1,ndc,pdc,pc,ppc,pnc,m2c)/metal1 ~space/w 1.162 ~space/a #rnw overlap (m1,fm1,rm1,ndc,pdc,pc,ppc,pnc,m2c)/metal1 rnw,nwr/active 0.398 sideoverlap (m1,fm1,rm1,ndc,pdc,pc,ppc,pnc,m2c)/metal1 ~(m1,fm1,rm1,ndc,pdc,pc,ppc,pnc,m2c)/metal1 rnw,nwr/active 1.162 #metal1-diff blocked by overlap (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,ppc,pnc,m2c)/metal1 (ndiff,anres,rnd,ndc)/active 0.421 sideoverlap (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,ppc,pnc,m2c)/metal1 ~(m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,ppc,pnc,m2c)/metal1 (ndiff,anres,rnd,ndc)/active 1.162 overlap (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,ppc,pnc,m2c)/metal1 (pdiff,apres,rpd,pdc)/active 0.421 sideoverlap (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,ppc,pnc,m2c)/metal1 ~(m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,ppc,pnc,m2c)/metal1 (pdiff,apres,rpd,pdc)/active 1.162 #metal1-poly blocked by overlap (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,ppc,pnc,m2c)/metal1 (poly,fp,pp,pn,pres,rp,pc,ppc,pnc,nfet,pfet,fet)/active 0.400 sideoverlap (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,ppc,pnc,m2c)/metal1 ~(m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,ppc,pnc,m2c)/metal1 (poly,fp,pp,pn,pres,rp,pc,ppc,pnc,nfet,pfet,fet)/active 1.166 sideoverlap (poly,fp,pp,pn,pres,rp,pc,ppc,pnc,nfet,pfet,fet)/active ~(poly,fp,pp,pn,pres,rp,pc,ppc,pnc,nfet,pfet,fet)/active (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,ppc,pnc,m2c)/metal1 1.166 #metal2 sidewall (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 (m2,fm2,rm2,m2c,m3c)/metal2 25.475 areacap (m2,fm2,rm2,m3c)/metal2 0.127 #metal2-sub blocked by overlap (m2,fm2,rm2,m3c)/metal2 ~space/w 0.127 ~space/a,~space/m1 perimc (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 0.407 sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 ~space/w 0.407 ~space/a,~space/m1 overlap (m2,fm2,rm2,m3c)/metal2 rnw,nwr/active 0.127 ~space/m1 sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 rnw,nwr/active 0.407 ~space/m1 #metal2-*diff blocked by ~space/m1 overlap (m2,fm2,rm2,m3c)/metal2 (ndiff,anres,rnd,ndc)/active 0.162 ~space/m1 sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 (ndiff,anres,rnd,ndc)/active 0.407 ~space/m1 overlap (m2,fm2,rm2,m2c,m3c)/metal2 (pdiff,apres,rpd,pdc)/active 0.162 ~space/m1 sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 (pdiff,apres,rpd,pdc)/active 0.407 ~space/m1 #metal2-poly blocked by ~space/m1 overlap (m2,fm2,rm2,m3c)/metal2 (poly,fp,pp,pn,pres,rp,pc,ppc,pnc,nfet,pfet,fet)/active 0.128 ~space/m1 sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 (poly,fp,pp,pn,pres,rp,pc,ppc,pnc,nfet,pfet,fet)/active 0.408 ~space/m1 sideoverlap (poly,fp,pp,pn,pres,rp,pc,ppc,pnc,nfet,pfet,fet)/active ~(poly,fp,pp,pn,pres,rp,pc,ppc,pnc,nfet,pfet,fet)/active (m2,fm2,rm2,m2c,m3c)/metal2 0.408 ~space/m1 #M2->M1 overlap (m2,fm2,rm2,m3c)/metal2 (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,ppc,pnc,m2c)/metal1 0.441 sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,ppc,pnc,m2c)/metal1 1.268 sideoverlap (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,ppc,pnc,m2c)/metal1 ~(m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,ppc,pnc,m2c)/metal1 (m2,fm2,rm2,m2c,m3c)/metal2 1.268 #metal3 sidewall (m3,fm3,rm3,m3c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m4c)/metal3 (m3,fm3,rm3,m3c,m4c)/metal3 26.825 areacap (m3,fm3,rm3,m4c)/metal3 0.076 #metal3-sub blocked by ~space/a,~space/m1,~space/m2 overlap (m3,fm3,rm3,m4c)/metal3 ~space/w 0.076 ~space/a,~space/m1,~space/m2 perimc (m3,fm3,rm3,m3c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m4c)/metal3 0.246 sideoverlap (m3,fm3,rm3,m3c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m4c)/metal3 ~space/w 0.246 ~space/a,~space/m1,~space/m2 #rnw overlap (m3,fm3,rm3,m4c)/metal3 rnw,nwr/active 0.076 ~space/m1,~space/m2 sideoverlap (m3,fm3,rm3,m3c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m4c)/metal3 rnw,nwr/active 0.246 ~space/m1,~space/m2 #metal3-*diff blocked by ~space/m1,~space/m2 overlap (m3,fm3,rm3,m4c)/metal3 (ndiff,anres,rnd,ndc)/active 0.105 ~space/m1,~space/m2 sideoverlap (m3,fm3,rm3,m3c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m4c)/metal3 (ndiff,anres,rnd,ndc)/active 0.246 ~space/m1,~space/m2 overlap (m3,fm3,rm3,m4c)/metal3 (pdiff,apres,rpd,pdc)/active 0.105 ~space/m1,~space/m2 sideoverlap (m3,fm3,rm3,m3c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m4c)/metal3 (pdiff,apres,rpd,pdc)/active 0.246 ~space/m1,~space/m2 #metal3-poly blocked by ~space/m1,~space/m2 overlap (m3,fm3,rm3,m4c)/metal3 (poly,fp,pp,pn,pres,rp,pc,ppc,pnc,nfet,pfet,fet)/active 0.076 ~space/m1,~space/m2 sideoverlap (m3,fm3,rm3,m3c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m4c)/metal3 (poly,fp,pp,pn,pres,rp,pc,ppc,pnc,nfet,pfet,fet)/active 0.246 ~space/m1,~space/m2 sideoverlap (poly,fp,pp,pn,pres,rp,pc,ppc,pnc,nfet,pfet,fet)/active ~(poly,fp,pp,pn,pres,rp,pc,ppc,pnc,nfet,pfet,fet)/active (m3,fm3,rm3,m3c,m4c)/metal3 0.246 ~space/m1,~space/m2 #M3->M1 #metal3-metal1 blocked by ~space/m2 overlap (m3,fm3,rm3,m4c)/metal3 (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,ppc,pnc,m2c)/metal1 0.132 ~space/m2 sideoverlap (m3,fm3,rm3,m3c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m4c)/metal3 (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,ppc,pnc,m2c)/metal1 0.420 ~space/m2 sideoverlap (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,ppc,pnc,m2c)/metal1 ~(m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,ppc,pnc,m2c)/metal1 (m3,fm3,rm3,m3c,m4c)/metal3 0.420 ~space/m2 #M3->M2 overlap (m3,fm3,rm3,m4c)/metal3 (m2,fm2,rm2,m2c,m3c)/metal2 0.441 sideoverlap (m3,fm3,rm3,m3c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m4c)/metal3 (m2,fm2,rm2,m2c,m3c)/metal2 1.268 sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 (m3,fm3,rm3,m3c,m4c)/metal3 1.268 #metal4 sidewall (m4,fm4,rm4,m4c,m5c)/metal4 ~(m4,fm4,rm4,m4c,m5c)/metal4 ~(m4,fm4,rm4,m4c,m5c)/metal4 (m4,fm4,rm4,m4c,m5c)/metal4 72.420 areacap (m4,fm4,rm4)/metal4 0.050 #metal4-sub blocked by ~space/a,~space/m1,~space/m2,~space/m3 overlap (m4,fm4,rm4)/metal4 ~space/w 0.050 ~space/a,~space/m1,~space/m2,~space/m3 perimc (m4,fm4,rm4,m4c,m5c)/metal4 ~(m4,fm4,rm4,m4c,m5c)/metal4 0.381 sideoverlap (m4,fm4,rm4,m4c,m5c)/metal4 ~(m4,fm4,rm4,m4c,m5c)/metal4 ~space/w 0.381 ~space/a,~space/m1,~space/m2,~space/m3 #rnw overlap (m4,fm4,rm4)/metal4 rnw,nwr/active 0.050 ~space/m1,~space/m2,~space/m3 sideoverlap (m4,fm4,rm4,m4c,m5c)/metal4 ~(m4,fm4,rm4,m4c,m5c)/metal4 rnw,nwr/active 0.381 ~space/m1,~space/m2,~space/m3 #metal4-*diff blocked by ~space/m1,~space/m2,~space/m3 overlap (m4,fm4,rm4)/metal4 (ndiff,anres,rnd,ndc)/active 0.089 ~space/m1,~space/m2,~space/m3 sideoverlap (m4,fm4,rm4,m4c,m5c)/metal4 ~(m4,fm4,rm4,m4c,m5c)/metal4 (ndiff,anres,rnd,ndc)/active 0.381 ~space/m1,~space/m2,~space/m3 overlap (m4,fm4,rm4)/metal4 (pdiff,apres,rpd,pdc)/active 0.089 ~space/m1,~space/m2,~space/m3 sideoverlap (m4,fm4,rm4,m4c,m5c)/metal4 ~(m4,fm4,rm4,m4c,m5c)/metal4 (pdiff,apres,rpd,pdc)/active 0.381 ~space/m1,~space/m2,~space/m3 #metal4-poly blocked by ~space/m1,~space/m2,~space/m3 overlap (m4,fm4,rm4)/metal4 (poly,fp,pp,pn,pres,rp,pc,ppc,pnc,nfet,pfet,fet)/active 0.058 ~space/m1,~space/m2,~space/m3 sideoverlap (m4,fm4,rm4,m4c,m5c)/metal4 ~(m4,fm4,rm4,m4c,m5c)/metal4 (poly,fp,pp,pn,pres,rp,pc,ppc,pnc,nfet,pfet,fet)/active 0.312 ~space/m1,~space/m2,~space/m3 sideoverlap (poly,fp,pp,pn,pres,rp,pc,ppc,pnc,nfet,pfet,fet)/active ~(poly,fp,pp,pn,pres,rp,pc,ppc,pnc,nfet,pfet,fet)/active (m4,fm4,rm4,m4c,m5c)/metal4 0.312 ~space/m1,~space/m2,~space/m3 #M4->M1 #metal4-metal1 blocked by ~space/m2,~space/m3 overlap (m4,fm4,rm4)/metal4 (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,ppc,pnc,m2c)/metal1 0.077 ~space/m2,~space/m3 sideoverlap (m4,fm4,rm4,m4c,m5c)/metal4 ~(m4,fm4,rm4,m4c,m5c)/metal4 (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,ppc,pnc,m2c)/metal1 0.495 ~space/m2,~space/m3 sideoverlap (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,ppc,pnc,m2c)/metal1 ~(m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,ppc,pnc,m2c)/metal1 (m4,fm4,rm4,m4c,m5c)/metal4 0.495 ~space/m2,~space/m3 #M4->M2 #metal4-metal2 blocked by ~space/m3 overlap (m4,fm4,rm4)/metal4 (m2,fm2,rm2,m2c,m3c)/metal2 0.132 ~space/m3 sideoverlap (m4,fm4,rm4,m4c,m5c)/metal4 ~(m4,fm4,rm4,m4c,m5c)/metal4 (m2,fm2,rm2,m2c,m3c)/metal2 0.824 ~space/m3 sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 (m4,fm4,rm4,m4c,m5c)/metal4 0.824 ~space/m3 #M4->M3 overlap (m4,fm4,rm4)/metal4 (m3,fm3,rm3,m3c,m4c)/metal3 0.440 sideoverlap (m4,fm4,rm4,m4c,m5c)/metal4 ~(m4,fm4,rm4,m4c,m5c)/metal4 (m3,fm3,rm3,m3c,m4c)/metal3 2.385 sideoverlap (m3,fm3,rm3,m3c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m4c)/metal3 (m4,fm4,rm4,m4c,m5c)/metal4 2.385 #metal5 sidewall (m5,fm5,rm5,m5c,m6c)/metal5 ~(m5,fm5,rm5,m5c,m6c)/metal5 ~(m5,fm5,rm5,m5c,m6c)/metal5 (m5,fm5,rm5,m5c,m6c)/metal5 12.750 areacap (m5,fm5,rm5)/metal5 0.065 #metal5-sub blocked by ~space/a,~space/m1,~space/m2,~space/m3,~space/m4 overlap (m5,fm5,rm5)/metal5 ~space/w 0.065 ~space/a,~space/m1,~space/m2,~space/m3,~space/m4 perimc (m5,fm5,rm5,m5c,m6c)/metal5 ~(m5,fm5,rm5,m5c,m6c)/metal5 2.070 sideoverlap (m5,fm5,rm5,m5c,m6c)/metal5 ~(m5,fm5,rm5,m5c,m6c)/metal5 ~space/w 2.070 ~space/a,~space/m1,~space/m2,~space/m3,~space/m4 #rnw overlap (m5,fm5,rm5)/metal5 rnw,nwr/active 0.065 ~space/m1,~space/m2,~space/m3,~space/m4 sideoverlap (m5,fm5,rm5,m5c,m6c)/metal5 ~(m5,fm5,rm5,m5c,m6c)/metal5 rnw,nwr/active 2.070 ~space/m1,~space/m2,~space/m3,~space/m4 #metal5-*diff blocked by ~space/m1,~space/m2,~space/m3,~space/m4 overlap (m5,fm5,rm5)/metal5 (ndiff,anres,rnd,ndc)/active 0.073 ~space/m1,~space/m2,~space/m3,~space/m4 sideoverlap (m5,fm5,rm5,m5c,m6c)/metal5 ~(m5,fm5,rm5,m5c,m6c)/metal5 (ndiff,anres,rnd,ndc)/active 2.070 ~space/m1,~space/m2,~space/m3,~space/m4 overlap (m5,fm5,rm5)/metal5 (pdiff,apres,rpd,pdc)/active 0.073 ~space/m1,~space/m2,~space/m3,~space/m4 sideoverlap (m5,fm5,rm5,m5c,m6c)/metal5 ~(m5,fm5,rm5,m5c,m6c)/metal5 (pdiff,apres,rpd,pdc)/active 2.070 ~space/m1,~space/m2,~space/m3,~space/m4 #metal5-poly blocked by ~space/m1,~space/m2,~space/m3,~space/m4 overlap (m5,fm5,rm5)/metal5 (poly,fp,pp,pn,pres,rp,pc,ppc,pnc,nfet,pfet,fet)/active 0.040 ~space/m1,~space/m2,~space/m3,~space/m4 sideoverlap (m5,fm5,rm5,m5c,m6c)/metal5 ~(m5,fm5,rm5,m5c,m6c)/metal5 (poly,fp,pp,pn,pres,rp,pc,ppc,pnc,nfet,pfet,fet)/active 1.800 ~space/m1,~space/m2,~space/m3,~space/m4 sideoverlap (poly,fp,pp,pn,pres,rp,pc,ppc,pnc,nfet,pfet,fet)/active ~(poly,fp,pp,pn,pres,rp,pc,ppc,pnc,nfet,pfet,fet)/active (m5,fm5,rm5,m5c,m6c)/metal5 1.800 ~space/m1,~space/m2,~space/m3,~space/m4 #M5->M1 #metal5-metal1 blocked by ~space/m2,~space/m3,~space/m4 overlap (m5,fm5,rm5)/metal5 (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,ppc,pnc,m2c)/metal1 0.073 ~space/m2,~space/m3,~space/m4 sideoverlap (m5,fm5,rm5,m5c,m6c)/metal5 ~(m5,fm5,rm5,m5c,m6c)/metal5 (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,ppc,pnc,m2c)/metal1 1.980 ~space/m2,~space/m3,~space/m4 sideoverlap (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,ppc,pnc,m2c)/metal1 ~(m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,ppc,pnc,m2c)/metal1 (m5,fm5,rm5,m5c,m6c)/metal5 1.980 ~space/m2,~space/m3,~space/m4 #M5->M2 #metal5-metal2 blocked by ~space/m3,~space/m4 overlap (m5,fm5,rm5)/metal5 (m2,fm2,rm2,m2c,m3c)/metal2 0.073 ~space/m3,~space/m4 sideoverlap (m5,fm5,rm5,m5c,m6c)/metal5 ~(m5,fm5,rm5,m5c,m6c)/metal5 (m2,fm2,rm2,m2c,m3c)/metal2 2.430 ~space/m3,~space/m4 sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 (m5,fm5,rm5,m5c,m6c)/metal5 2.430 ~space/m3,~space/m4 #M5->M3 #metal5-metal3 blocked by ~space/m4 overlap (m5,fm5,rm5)/metal5 (m3,fm3,rm3,m3c,m4c)/metal3 0.113 ~space/m4 sideoverlap (m5,fm5,rm5,m5c,m6c)/metal5 ~(m5,fm5,rm5,m5c,m6c)/metal5 (m3,fm3,rm3,m3c,m4c)/metal3 3.060 ~space/m4 sideoverlap (m3,fm3,rm3,m3c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m4c)/metal3 (m5,fm5,rm5,m5c,m6c)/metal5 3.060 ~space/m4 #M5->M4 overlap (m5,fm5,rm5)/metal5 (m4,fm4,rm4,m4c,m5c)/metal4 0.300 sideoverlap (m5,fm5,rm5,m5c,m6c)/metal5 ~(m5,fm5,rm5,m5c,m6c)/metal5 (m4,fm4,rm4,m4c,m5c)/metal4 4.860 sideoverlap (m4,fm4,rm4,m4c,m5c)/metal4 ~(m4,fm4,rm4,m4c,m5c)/metal4 (m5,fm5,rm5,m5c,m6c)/metal5 4.860 #metal6 sidewall (m6,fm6,rm6,m6c,mic,pad)/metal6 ~(m6,fm6,rm6,m6c,mic,pad)/metal6 ~(m6,fm6,rm6,m6c,mic,pad)/metal6 (m6,fm6,rm6,m6c,mic,pad)/metal6 27.675 areacap (m6,fm6,rm6,pad)/metal6 0.024 #metal6-sub blocked by ~space/a,~space/m1,~space/m2,~space/m3,~space/m4,~space/m5,~space/mi overlap (m6,fm6,rm6,pad)/metal6 ~space/w 0.024 ~space/a,~space/m1,~space/m2,~space/m3,~space/m4,~space/m5,~space/mi perimc (m6,fm6,rm6,m6c,mic,pad)/metal6 ~(m6,fm6,rm6,m6c,mic,pad)/metal6 3.780 sideoverlap (m6,fm6,rm6,m6c,mic,pad)/metal6 ~(m6,fm6,rm6,m6c,mic,pad)/metal6 ~space/w 3.780 ~space/a,~space/m1,~space/m2,~space/m3,~space/m4,~space/m5,~space/mi #rnw overlap (m6,fm6,rm6,pad)/metal6 rnw,nwr/active 0.024 ~space/m1,~space/m2,~space/m3,~space/m4,~space/m5,~space/mi sideoverlap (m6,fm6,rm6,m6c,mic,pad)/metal6 ~(m6,fm6,rm6,m6c,mic,pad)/metal6 rnw,nwr/active 3.780 ~space/m1,~space/m2,~space/m3,~space/m4,~space/m5,~space/mi #metal6-*diff blocked by ~space/m1,~space/m2,~space/m3,~space/m4,~space/m5,~space/mi overlap (m6,fm6,rm6,pad)/metal6 (ndiff,anres,rnd,ndc)/active 0.065 ~space/m1,~space/m2,~space/m3,~space/m4,~space/m5,~space/mi sideoverlap (m6,fm6,rm6,m6c,mic,pad)/metal6 ~(m6,fm6,rm6,m6c,mic,pad)/metal6 (ndiff,anres,rnd,ndc)/active 3.780 ~space/m1,~space/m2,~space/m3,~space/m4,~space/m5,~space/mi overlap (m6,fm6,rm6,pad)/metal6 (pdiff,apres,rpd,pdc)/active 0.065 ~space/m1,~space/m2,~space/m3,~space/m4,~space/m5,~space/mi sideoverlap (m6,fm6,rm6,m6c,mic,pad)/metal6 ~(m6,fm6,rm6,m6c,mic,pad)/metal6 (pdiff,apres,rpd,pdc)/active 3.780 ~space/m1,~space/m2,~space/m3,~space/m4,~space/m5,~space/mi #metal6-poly blocked by ~space/m1,~space/m2,~space/m3,~space/m4,~space/m5,~space/mi overlap (m6,fm6,rm6,pad)/metal6 (poly,fp,pp,pn,pres,rp,pc,ppc,pnc,nfet,pfet,fet)/active 0.032 ~space/m1,~space/m2,~space/m3,~space/m4,~space/m5,~space/mi sideoverlap (m6,fm6,rm6,m6c,mic,pad)/metal6 ~(m6,fm6,rm6,m6c,mic,pad)/metal6 (poly,fp,pp,pn,pres,rp,pc,ppc,pnc,nfet,pfet,fet)/active 1.530 ~space/m1,~space/m2,~space/m3,~space/m4,~space/m5,~space/mi sideoverlap (poly,fp,pp,pn,pres,rp,pc,ppc,pnc,nfet,pfet,fet)/active ~(poly,fp,pp,pn,pres,rp,pc,ppc,pnc,nfet,pfet,fet)/active (m6,fm6,rm6,m6c,mic,pad)/metal6 1.530 ~space/m1,~space/m2,~space/m3,~space/m4,~space/m5,~space/mi #M6->M1 #metal6-metal1 blocked by ~space/m2,~space/m3,~space/m4,~space/m5,~space/mi overlap (m6,fm6,rm6,pad)/metal6 (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,ppc,pnc,m2c)/metal1 0.049 ~space/m2,~space/m3,~space/m4,~space/m5,~space/mi sideoverlap (m6,fm6,rm6,m6c,mic,pad)/metal6 ~(m6,fm6,rm6,m6c,mic,pad)/metal6 (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,ppc,pnc,m2c)/metal1 1.710 ~space/m2,~space/m3,~space/m4,~space/m5,~space/mi sideoverlap (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,ppc,pnc,m2c)/metal1 ~(m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,ppc,pnc,m2c)/metal1 (m6,fm6,rm6,m6c,mic,pad)/metal6 1.710 ~space/m2,~space/m3,~space/m4,~space/m5,~space/mi #M6->M2 #metal6-metal2 blocked by ~space/m3,~space/m4,~space/m5,~space/mi overlap (m6,fm6,rm6,pad)/metal6 (m2,fm2,rm2,m2c,m3c)/metal2 0.049 ~space/m3,~space/m4,~space/m5,~space/mi sideoverlap (m6,fm6,rm6,m6c,mic,pad)/metal6 ~(m6,fm6,rm6,m6c,mic,pad)/metal6 (m2,fm2,rm2,m2c,m3c)/metal2 1.980 ~space/m3,~space/m4,~space/m5,~space/mi sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 (m6,fm6,rm6,m6c,mic,pad)/metal6 1.980 ~space/m3,~space/m4,~space/m5,~space/mi #M6->M3 #metal6-metal3 blocked by ~space/m4,~space/m5,~space/mi overlap (m6,fm6,rm6,pad)/metal6 (m3,fm3,rm3,m3c,m4c)/metal3 0.073 ~space/m4,~space/m5,~space/mi sideoverlap (m6,fm6,rm6,m6c,mic,pad)/metal6 ~(m6,fm6,rm6,m6c,mic,pad)/metal6 (m3,fm3,rm3,m3c,m4c)/metal3 2.430 ~space/m4,~space/m5,~space/mi sideoverlap (m3,fm3,rm3,m3c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m4c)/metal3 (m6,fm6,rm6,m6c,mic,pad)/metal6 2.430 ~space/m4,~space/m5,~space/mi #M6->M4 #metal6-metal4 blocked by ~space/m5,~space/mi overlap (m6,fm6,rm6,pad)/metal6 (m4,fm4,rm4,m4c,m5c)/metal4 0.113 ~space/m5,~space/mi sideoverlap (m6,fm6,rm6,m6c,mic,pad)/metal6 ~(m6,fm6,rm6,m6c,mic,pad)/metal6 (m4,fm4,rm4,m4c,m5c)/metal4 3.150 ~space/m5,~space/mi sideoverlap (m4,fm4,rm4,m4c,m5c)/metal4 ~(m4,fm4,rm4,m4c,m5c)/metal4 (m6,fm6,rm6,m6c,mic,pad)/metal6 3.150 ~space/m5,~space/mi #M6->M5 overlap (m6,fm6,rm6,pad)/metal6 (m5,fm5,rm5,m5c,m6c)/metal5 0.284 sideoverlap (m6,fm6,rm6,m6c,mic,pad)/metal6 ~(m6,fm6,rm6,m6c,mic,pad)/metal6 (m5,fm5,rm5,m5c,m6c)/metal5 5.130 ~space/mi sideoverlap (m5,fm5,rm5,m5c,m6c)/metal5 ~(m5,fm5,rm5,m5c,m6c)/metal5 (m6,fm6,rm6,m6c,mic,pad)/metal6 5.130 ~space/mi #metal7 #metali #Mi->M5 #Mi->M6 #fets fet pfet pdiff,pdc 2 pfet Vdd! nwell 61 66 fet pfet pdiff,pdc 1 pfet Vdd! nwell 61 66 fet nfet ndiff,ndc 2 nfet Gnd! pwell 63 68 fet nfet ndiff,ndc 1 nfet Gnd! pwell 63 68 fetresis pfet linear 28253 fetresis pfet saturation 28253 fetresis nfet linear 4769 fetresis nfet saturation 4769 fet rnwell nsd,nsc 2 nwellResistor Gnd! nwell,pwell 0 0 fet rpoly poly,pc 2 polyResistor Gnd! nwell,pwell 0 0 fet nwr nwsd 2 nwellFig1bResistor Gnd! nwell,pwell 0 0 fet rndiff ndiff,ndc 2 ndiffResistor Gnd! nwell,pwell 0 0 fet rpdiff pdiff,pdc 2 pdiffResistor Gnd! nwell,pwell 0 0 fet rmetal1 metal1 2 metal1Resistor Gnd! nwell,pwell 0 0 fet rmetal2 metal2 2 metal2Resistor Gnd! nwell,pwell 0 0 fet rmetal3 metal3 2 metal3Resistor Gnd! nwell,pwell 0 0 fet rmetal4 metal4 2 metal4Resistor Gnd! nwell,pwell 0 0 fet rmetal5 metal5 2 metal5Resistor Gnd! nwell,pwell 0 0 fet rmetal6 metal6 2 metal6Resistor Gnd! nwell,pwell 0 0 fet pres poly,pc 2 presResistor Gnd! nwell,pwell 0 0 fet anres ndiff,ndc 2 anresResistor Gnd! nwell,pwell 0 0 fet apres pdiff,pdc 2 apresResistor Gnd! nwell,pwell 0 0 end wiring contact pdcontact 4 metal1 0 pdiff 0 contact ndcontact 4 metal1 0 ndiff 0 contact pcontact 4 metal1 0 poly 0 contact m2contact 4 metal1 0 metal2 0 contact m3contact 5 metal2 0 metal3 1 contact m4contact 4 metal3 0 metal4 0 contact m5contact 5 metal4 0 metal5 0 contact m6contact 6 metal5 0 metal6 0 contact micontact 6 metal6 0 mi 0 end router layer2 metal2 3 m2,fm2,rm2,m2c/m2,m3c/m2,m3c/m2 4 poly,fp,pp,pn,pres,rp,ndiff,anres,rnd,nsd,nwsd,pdiff,apres,rpd,psd,m1,fm1,rm1 1 layer1 metal1 3 m1,fm1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,ppc/m1,pnc/m1,m2c/m1 3 contacts m2contact 4 gridspacing 8 end plowing fixed nfet,pfet,glass,pad covered nfet,pfet drag nfet,pfet end plot style colorversatec ndiff,anres,rnd,ndc/a yellow \ 5555 AAAA 5555 AAAA \ 5555 AAAA 5555 AAAA \ 5555 AAAA 5555 AAAA \ 5555 AAAA 5555 AAAA ndiff,anres,rnd,ndc/a cyan \ 0000 5555 0000 5555 \ 0000 5555 0000 5555 \ 0000 5555 0000 5555 \ 0000 5555 0000 5555 nsd,nwsd,nsc/a,nwsc/a yellow \ 1515 2A2A 5151 A2A2 \ 1515 2A2A 5151 A2A2 \ 1515 2A2A 5151 A2A2 \ 1515 2A2A 5151 A2A2 nsd,nwsd,nsc/a,nwsc/a cyan \ 0000 1515 0000 5151 \ 0000 1515 0000 5151 \ 0000 1515 0000 5151 \ 0000 1515 0000 5151 pdiff,apres,rpd,pdc/a yellow \ 5555 AAAA 5555 AAAA \ 5555 AAAA 5555 AAAA \ 5555 AAAA 5555 AAAA \ 5555 AAAA 5555 AAAA pdiff,apres,rpd,pdc/a cyan \ 0000 5555 0000 5555 \ 0000 5555 0000 5555 \ 0000 5555 0000 5555 \ 0000 5555 0000 5555 pdiff,apres,rpd,pdc/a magenta \ AAAA 0000 AAAA 0000 \ AAAA 0000 AAAA 0000 \ AAAA 0000 AAAA 0000 \ AAAA 0000 AAAA 0000 psd,psc/a yellow \ 1515 2A2A 5151 A2A2 \ 1515 2A2A 5151 A2A2 \ 1515 2A2A 5151 A2A2 \ 1515 2A2A 5151 A2A2 psd,psc/a cyan \ 0000 1515 0000 5151 \ 0000 1515 0000 5151 \ 0000 1515 0000 5151 \ 0000 1515 0000 5151 psd,psc/a magenta \ 2A2A 0000 A2A2 0000 \ 2A2A 0000 A2A2 0000 \ 2A2A 0000 A2A2 0000 \ 2A2A 0000 A2A2 0000 poly,fp,pp,pn,pres,rp,pc/a,ppc/a,pnc/a magenta \ 5555 AAAA 5555 AAAA \ 5555 AAAA 5555 AAAA \ 5555 AAAA 5555 AAAA \ 5555 AAAA 5555 AAAA nfet yellow \ 0505 8282 1414 0A0A \ 5050 2828 4141 A0A0 \ 0505 8282 1414 0A0A \ 5050 2828 4141 A0A0 nfet cyan \ 0000 0505 0000 1414 \ 0000 5050 0000 4141 \ 0000 0505 0000 1414 \ 0000 5050 0000 4141 nfet magenta \ 5050 2828 4141 A0A0 \ 0505 8282 1414 0A0A \ 5050 2828 4141 A0A0 \ 0505 8282 1414 0A0A pfet yellow \ 6363 A0A0 5050 2828 \ 3636 0A0A 0505 8282 \ 6363 A0A0 5050 2828 \ 3636 0A0A 0505 8282 pfet cyan \ 0000 5151 0000 5454 \ 0000 1515 0000 1515 \ 0000 5151 0000 5454 \ 0000 1515 0000 1515 pfet magenta \ 9494 0A0A 2525 8282 \ 4949 A0A0 5252 2828 \ 9494 0A0A 2525 8282 \ 4949 A0A0 5252 2828 m1,fm1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,ppc/m1,pnc/m1,m2c/m1 cyan \ AAAA 0000 AAAA 0000 \ AAAA 0000 AAAA 0000 \ AAAA 0000 AAAA 0000 \ AAAA 0000 AAAA 0000 m2,fm2,rm2,m2c/m2,m3c/m2 cyan \ 0000 1111 0000 4444 \ 0000 1111 0000 4444 \ 0000 1111 0000 4444 \ 0000 1111 0000 4444 m2,fm2,rm2,m2c/m2,m3c/m2 magenta \ 0000 4444 0000 1111 \ 0000 4444 0000 1111 \ 0000 4444 0000 1111 \ 0000 4444 0000 1111 m2c/m1,gv1 black \ 0000 6666 6666 0000 \ 0000 9999 9999 0000 \ 0000 6666 6666 0000 \ 0000 9999 9999 0000 pad,glass black \ 0300 0700 0E00 1C00 \ 3800 7000 E000 C000 \ 00C0 00E0 0070 0038 \ 001C 000E 0007 0003 nwell yellow \ 0800 1000 2000 4000 \ 8000 0001 0002 0004 \ 0008 0010 0020 0040 \ 0080 0010 0200 0400 nwell cyan \ 1000 2000 4000 8000 \ 0001 0002 0004 0008 \ 0010 0020 0040 0080 \ 0100 0200 0400 0800 pwell yellow \ 1000 0400 0400 0100 \ 0100 0040 0040 0010 \ 0010 0004 0004 0001 \ 0001 4000 4000 1000 pwell cyan \ 0000 0800 0000 0200 \ 0000 0080 0000 0020 \ 0000 0008 0000 0002 \ 0000 8000 0000 2000 pwell magenta \ 0800 0000 0200 0000 \ 0080 0000 0020 0000 \ 0008 0000 0002 0000 \ 8000 0000 2000 0000 m3c/m2,gv2 black \ 0100 0000 0000 0000 \ 1010 0000 0000 0000 \ 0001 0000 0000 0000 \ 1010 0000 0000 0000 m3c/m2,gv2 cyan \ 0280 0000 0820 0000 \ 2008 0000 8002 0000 \ 8002 0000 2008 0000 \ 0820 0000 0280 0000 m3c/m2,gv2 magenta \ 0100 06C0 0440 1830 \ 1010 600C 4004 8003 \ 0001 C006 4004 3018 \ 1010 0C60 0440 0380 m3c/m2,gv2 black \ 0820 0820 0820 0FE0 \ E00F 2008 2008 2008 \ 2008 2008 2008 E00F \ 0000 0FE0 0820 0820 error_p,error_s,error_ps black \ 0000 3C3C 4646 4A4A \ 5252 6262 3C3C 0000 \ 0000 3C3C 4646 4A4A \ 5252 6262 3C3C 0000 magnet yellow \ AAAA 0000 5555 0000 \ AAAA 0000 5555 0000 \ AAAA 0000 5555 0000 \ AAAA 0000 5555 0000 fence magenta \ FFFF 0000 0000 0000 \ 0000 0000 0000 0000 \ FFFF 0000 0000 0000 \ 0000 0000 0000 0000 rotate cyan \ 0000 E0E0 E0E0 E0E0 \ 0000 0000 0000 0000 \ 0000 E0E0 E0E0 E0E0 \ 0000 0000 0000 0000 pc/a,ppc/a,pnc/a,ndc/a,pdc/a,psc/a,nsc/a,nwsc/a,gc,gc,gc X style versatec pfet \ 07c0 0f80 1f00 3e00 \ 7c00 f800 f001 e003 \ c007 800f 001f 003e \ 00c7 00f8 01f0 03e0 nfet \ 1f00 0f80 07c0 03e0 \ 01f0 00f8 007c 003e \ 001f 800f c007 e003 \ f001 f800 7c00 3e00 gv1 \ c3c3 c3c3 0000 0000 \ 0000 0000 c3c3 c3c3 \ c3c3 c3c3 0000 0000 \ 0000 0000 c3c3 c3c3 pwell \ 2020 2020 2020 2020 \ 2020 2020 2020 2020 \ 0000 0000 0000 0000 \ 0000 0000 0000 0000 nwell \ 0808 0404 0202 0101 \ 0000 0000 0000 0000 \ 0808 0404 0202 0101 \ 0000 0000 0000 0000 poly,fp,pp,pn,pres,rp,pc/a,ppc/a,pnc/a,nfet,pfet \ 0808 0400 0202 0101 \ 8080 4000 2020 1010 \ 0808 0004 0202 0101 \ 8080 0040 2020 1010 m1,fm1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,ppc/m1,pnc/m1,m2c/m1 \ 8080 0000 0000 0000 \ 0808 0000 0000 0000 \ 8080 0000 0000 0000 \ 0808 0000 0000 0000 pad,glass \ 0000 0000 1c1c 3e3e \ 3636 3e3e 1c1c 0000 \ 0000 0000 1c1c 3e3e \ 3636 3e3e 1c1c 0000 nsd,nwsd,nsc/a,nwsc/a \ 0808 1414 2222 4141 \ 8080 4040 2020 1010 \ 0808 1414 2222 4141 \ 8080 4040 2020 1010 m2,fm2,rm2,m2c/m2,m3c/m2 \ 0000 1111 0000 0000 \ 0000 1111 0000 0000 \ 0000 1111 0000 0000 \ 0000 1111 0000 0000 pdiff,apres,rpd,pdc/a,pfet \ 0000 0808 5555 8080 \ 0000 8080 5555 0808 \ 0000 0808 5555 8080 \ 0000 8080 5555 0808 psd,psc/a \ 1414 2222 0000 2222 \ 4141 2222 0000 2222 \ 1414 2222 0000 2222 \ 4141 2222 0000 2222 ndiff,anres,rnd,ndc/a,nfet \ 0808 1010 2020 4040 \ 8080 4141 2222 1414 \ 0808 1010 2020 4040 \ 8080 4141 2222 1414 pc/a,ppc/a,pnc/a,ndc/a,pdc/a,psc/a,nsc/a,nwsc/a,gc,gc,gc X style gremlin pfet 9 nfet 10 gv1 11 pwell 15 nwell 16 poly,fp,pp,pn,pres,rp,pc/a,ppc/a,pnc/a,nfet,pfet 19 pc/a,ppc/a,pnc/a,ndc/a,pdc/a,psc/a,nsc/a,nwsc/a,gc,gc,gc 22 pad,glass 23 nsd,nwsd,nsc/a,nwsc/a 24 gv1 28 pdiff,apres,rpd,pdc/a,pfet 29 psd,psc/a 30 ndiff,anres,rnd,ndc/a,nfet 31 pc/a,ppc/a,pnc/a,ndc/a,pdc/a,psc/a,nsc/a,nwsc/a,gc,gc,gc,gv1 X end qflow-1.1.23/tech/osu018/osu018.magicrc.in0000664000175000001440000000047612535603240016424 0ustar timusers#----------------------------------------------------- # .magicrc startup file for OSU018 project under qflow #----------------------------------------------------- path sys +QFLOW_LIB_DIR/tech/osu018 tech load SCN6M_DEEP.09 -noprompt scalegrid 1 9 set GND gnd set VDD vdd drc euclidean on drc off addpath digital qflow-1.1.23/tech/osu018/Makefile0000664000175000001440000000247312535603240015070 0ustar timusers# # qflow project included technology osu018 files # # Main compiler arguments CFLAGS = -g -O2 DEFS = -DPACKAGE_NAME=\"\" -DPACKAGE_TARNAME=\"\" -DPACKAGE_VERSION=\"\" -DPACKAGE_STRING=\"\" -DPACKAGE_BUGREPORT=\"\" -DPACKAGE_URL=\"\" -DSTDC_HEADERS=1 -DHAVE_SETENV=1 -DHAVE_PUTENV=1 -DTCLSH_PATH=\"/bin/tclsh\" -DQFLOW_MAGIC_PATH=\"/usr/local/bin/magic\" -DQFLOW_QROUTER_PATH=\"/usr/local/bin/qrouter\" -DQFLOW_GRAYWOLF_PATH=\"/usr/local/bin/graywolf\" -DQFLOW_YOSYS_PATH=\"/usr/local/bin/yosys\" LIBS = LDFLAGS = INSTALL = /bin/install -c QFLOW_LIB_DIR = /usr/local/share/qflow TECH_FILES = osu018.par osu018_stdcells.lef osu018.sh TECH_FILES += osu018_stdcells.sp osu018.magicrc osu018.prm TECH_FILES += SCN6M_DEEP.09.tech osu018_stdcells.lib TECH_FILES += osu018_stdcells.v TECHINSTALL = ${QFLOW_LIB_DIR}/tech # Substitute the target qflow tech directory name in .magicrc so that magic # can find the OSU018 techfile all: osu018.magicrc.in $(RM) -f osu018.magicrc cat osu018.magicrc.in | sed -e \ '/QFLOW_LIB_DIR/s#QFLOW_LIB_DIR#$(QFLOW_LIB_DIR)#' \ > osu018.magicrc install: ${TECH_FILES} @echo "Installing osu018 tech files" $(INSTALL) -d $(DESTDIR)$(TECHINSTALL)/osu018 for target in $(TECH_FILES); do \ $(INSTALL) $$target $(DESTDIR)$(TECHINSTALL)/osu018 ;\ done clean: $(RM) -f osu018.magicrc uninstall: qflow-1.1.23/tech/osu018/osu018_stdcells.sp0000775000175000001440000006110412535603240016727 0ustar timusers .subckt AND2X1 Y B vdd gnd A M0 a_2_6# A vdd vdd pfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M1 vdd B a_2_6# vdd pfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M2 Y a_2_6# vdd vdd pfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M3 a_9_6# A a_2_6# Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M4 gnd B a_9_6# Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M5 Y a_2_6# gnd Gnd nfet w=1u l=0.2u + ad=0p pd=0u as=0p ps=0u .ends AND2X1 .subckt AND2X2 vdd gnd A B Y M0 a_2_6# A vdd vdd pfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M1 vdd B a_2_6# vdd pfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M2 Y a_2_6# vdd vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M3 a_9_6# A a_2_6# Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M4 gnd B a_9_6# Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M5 Y a_2_6# gnd Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u .ends AND2X2 .subckt AOI21X1 gnd vdd A B Y C M0 vdd A a_2_54# vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M1 a_2_54# B vdd vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M2 Y C a_2_54# vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M3 a_12_6# A gnd Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M4 Y B a_12_6# Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M5 gnd C Y Gnd nfet w=1u l=0.2u + ad=0p pd=0u as=0p ps=0u .ends AOI21X1 .subckt AOI22X1 gnd vdd C D Y A B M0 vdd A a_2_54# vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M1 a_2_54# B vdd vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M2 Y D a_2_54# vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M3 a_2_54# C Y vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M4 a_11_6# A gnd Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M5 Y B a_11_6# Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M6 a_28_6# D Y Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M7 gnd C a_28_6# Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u .ends AOI22X1 .subckt BUFX2 vdd gnd A Y M0 vdd A a_2_6# vdd pfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M1 Y a_2_6# vdd vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M2 gnd A a_2_6# Gnd nfet w=1u l=0.2u + ad=0p pd=0u as=0p ps=0u M3 Y a_2_6# gnd Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u .ends BUFX2 .subckt BUFX4 vdd gnd A Y M0 vdd A a_2_6# vdd pfet w=3u l=0.2u + ad=0p pd=0u as=0p ps=0u M1 Y a_2_6# vdd vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M2 vdd a_2_6# Y vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M3 gnd A a_2_6# Gnd nfet w=1.5u l=0.2u + ad=0p pd=0u as=0p ps=0u M4 Y a_2_6# gnd Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M5 gnd a_2_6# Y Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u .ends BUFX4 .subckt CLKBUF1 A vdd gnd Y M0 a_9_6# A vdd vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M1 vdd A a_9_6# vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M2 a_25_6# a_9_6# vdd vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M3 vdd a_9_6# a_25_6# vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M4 a_41_6# a_25_6# vdd vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M5 vdd a_25_6# a_41_6# vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M6 Y a_41_6# vdd vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M7 vdd a_41_6# Y vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M8 a_9_6# A gnd Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M9 gnd A a_9_6# Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M10 a_25_6# a_9_6# gnd Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M11 gnd a_9_6# a_25_6# Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M12 a_41_6# a_25_6# gnd Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M13 gnd a_25_6# a_41_6# Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M14 Y a_41_6# gnd Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M15 gnd a_41_6# Y Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u .ends CLKBUF1 .subckt CLKBUF2 vdd gnd A Y M0 a_9_6# A vdd vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M1 vdd A a_9_6# vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M2 a_25_6# a_9_6# vdd vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M3 vdd a_9_6# a_25_6# vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M4 a_41_6# a_25_6# vdd vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M5 vdd a_25_6# a_41_6# vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M6 a_57_6# a_41_6# vdd vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M7 vdd a_41_6# a_57_6# vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M8 a_73_6# a_57_6# vdd vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M9 vdd a_57_6# a_73_6# vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M10 Y a_73_6# vdd vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M11 vdd a_73_6# Y vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M12 a_9_6# A gnd Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M13 gnd A a_9_6# Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M14 a_25_6# a_9_6# gnd Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M15 gnd a_9_6# a_25_6# Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M16 a_41_6# a_25_6# gnd Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M17 gnd a_25_6# a_41_6# Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M18 a_57_6# a_41_6# gnd Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M19 gnd a_41_6# a_57_6# Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M20 a_73_6# a_57_6# gnd Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M21 gnd a_57_6# a_73_6# Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M22 Y a_73_6# gnd Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M23 gnd a_73_6# Y Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u .ends CLKBUF2 .subckt CLKBUF3 gnd vdd A Y M0 a_9_6# A vdd vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M1 vdd A a_9_6# vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M2 a_25_6# a_9_6# vdd vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M3 vdd a_9_6# a_25_6# vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M4 a_41_6# a_25_6# vdd vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M5 vdd a_25_6# a_41_6# vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M6 a_57_6# a_41_6# vdd vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M7 vdd a_41_6# a_57_6# vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M8 a_73_6# a_57_6# vdd vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M9 vdd a_57_6# a_73_6# vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M10 a_89_6# a_73_6# vdd vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M11 vdd a_73_6# a_89_6# vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M12 a_105_6# a_89_6# vdd vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M13 vdd a_89_6# a_105_6# vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M14 Y a_105_6# vdd vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M15 vdd a_105_6# Y vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M16 a_9_6# A gnd Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M17 gnd A a_9_6# Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M18 a_25_6# a_9_6# gnd Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M19 gnd a_9_6# a_25_6# Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M20 a_41_6# a_25_6# gnd Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M21 gnd a_25_6# a_41_6# Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M22 a_57_6# a_41_6# gnd Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M23 gnd a_41_6# a_57_6# Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M24 a_73_6# a_57_6# gnd Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M25 gnd a_57_6# a_73_6# Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M26 a_89_6# a_73_6# gnd Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M27 gnd a_73_6# a_89_6# Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M28 a_105_6# a_89_6# gnd Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M29 gnd a_89_6# a_105_6# Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M30 Y a_105_6# gnd Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M31 gnd a_105_6# Y Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u .ends CLKBUF3 .subckt DFFNEGX1 CLK vdd D gnd Q M0 vdd CLK a_2_6# vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M1 a_17_74# D vdd vdd pfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M2 a_23_6# a_2_6# a_17_74# vdd pfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M3 a_31_74# CLK a_23_6# vdd pfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M4 vdd a_34_4# a_31_74# vdd pfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M5 a_34_4# a_23_6# vdd vdd pfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M6 a_61_74# a_34_4# vdd vdd pfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M7 a_66_6# CLK a_61_74# vdd pfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M8 a_76_84# a_2_6# a_66_6# vdd pfet w=1u l=0.2u + ad=0p pd=0u as=0p ps=0u M9 vdd Q a_76_84# vdd pfet w=1u l=0.2u + ad=0p pd=0u as=0p ps=0u M10 gnd CLK a_2_6# Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M11 Q a_66_6# vdd vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M12 a_17_6# D gnd Gnd nfet w=1u l=0.2u + ad=0p pd=0u as=0p ps=0u M13 a_23_6# CLK a_17_6# Gnd nfet w=1u l=0.2u + ad=0p pd=0u as=0p ps=0u M14 a_31_6# a_2_6# a_23_6# Gnd nfet w=1u l=0.2u + ad=0p pd=0u as=0p ps=0u M15 gnd a_34_4# a_31_6# Gnd nfet w=1u l=0.2u + ad=0p pd=0u as=0p ps=0u M16 a_34_4# a_23_6# gnd Gnd nfet w=1u l=0.2u + ad=0p pd=0u as=0p ps=0u M17 a_61_6# a_34_4# gnd Gnd nfet w=1u l=0.2u + ad=0p pd=0u as=0p ps=0u M18 a_66_6# a_2_6# a_61_6# Gnd nfet w=1u l=0.2u + ad=0p pd=0u as=0p ps=0u M19 a_76_6# CLK a_66_6# Gnd nfet w=1u l=0.2u + ad=0p pd=0u as=0p ps=0u M20 gnd Q a_76_6# Gnd nfet w=1u l=0.2u + ad=0p pd=0u as=0p ps=0u M21 Q a_66_6# gnd Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u .ends DFFNEGX1 .subckt DFFPOSX1 vdd D gnd Q CLK M0 vdd CLK a_2_6# vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M1 a_17_74# D vdd vdd pfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M2 a_22_6# CLK a_17_74# vdd pfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M3 a_31_74# a_2_6# a_22_6# vdd pfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M4 vdd a_34_4# a_31_74# vdd pfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M5 a_34_4# a_22_6# vdd vdd pfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M6 a_61_74# a_34_4# vdd vdd pfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M7 a_66_6# a_2_6# a_61_74# vdd pfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M8 a_76_84# CLK a_66_6# vdd pfet w=1u l=0.2u + ad=0p pd=0u as=0p ps=0u M9 vdd Q a_76_84# vdd pfet w=1u l=0.2u + ad=0p pd=0u as=0p ps=0u M10 gnd CLK a_2_6# Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M11 Q a_66_6# vdd vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M12 a_17_6# D gnd Gnd nfet w=1u l=0.2u + ad=0p pd=0u as=0p ps=0u M13 a_22_6# a_2_6# a_17_6# Gnd nfet w=1u l=0.2u + ad=0p pd=0u as=0p ps=0u M14 a_31_6# CLK a_22_6# Gnd nfet w=1u l=0.2u + ad=0p pd=0u as=0p ps=0u M15 gnd a_34_4# a_31_6# Gnd nfet w=1u l=0.2u + ad=0p pd=0u as=0p ps=0u M16 a_34_4# a_22_6# gnd Gnd nfet w=1u l=0.2u + ad=0p pd=0u as=0p ps=0u M17 a_61_6# a_34_4# gnd Gnd nfet w=1u l=0.2u + ad=0p pd=0u as=0p ps=0u M18 a_66_6# CLK a_61_6# Gnd nfet w=1u l=0.2u + ad=0p pd=0u as=0p ps=0u M19 a_76_6# a_2_6# a_66_6# Gnd nfet w=1u l=0.2u + ad=0p pd=0u as=0p ps=0u M20 gnd Q a_76_6# Gnd nfet w=1u l=0.2u + ad=0p pd=0u as=0p ps=0u M21 Q a_66_6# gnd Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u .ends DFFPOSX1 .subckt DFFSR gnd vdd D S R Q CLK M0 a_2_6# R vdd vdd pfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M1 vdd a_10_61# a_2_6# vdd pfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M2 a_10_61# a_23_27# vdd vdd pfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M3 vdd S a_10_61# vdd pfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M4 a_23_27# a_47_71# a_2_6# vdd pfet w=1u l=0.2u + ad=0p pd=0u as=0p ps=0u M5 a_57_6# a_47_4# a_23_27# vdd pfet w=1u l=0.2u + ad=0p pd=0u as=0p ps=0u M6 vdd D a_57_6# vdd pfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M7 vdd a_47_71# a_47_4# vdd pfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M8 a_47_71# CLK vdd vdd pfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M9 a_105_6# a_47_71# a_10_61# vdd pfet w=1u l=0.2u + ad=0p pd=0u as=0p ps=0u M10 a_113_6# a_47_4# a_105_6# vdd pfet w=1u l=0.2u + ad=0p pd=0u as=0p ps=0u M11 a_122_6# a_105_6# vdd vdd pfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M12 vdd R a_122_6# vdd pfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M13 a_113_6# a_122_6# vdd vdd pfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M14 vdd S a_113_6# vdd pfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M15 vdd a_122_6# Q vdd pfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M16 a_10_6# R a_2_6# Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M17 gnd a_10_61# a_10_6# Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M18 a_26_6# a_23_27# gnd Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M19 a_10_61# S a_26_6# Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M20 a_23_27# a_47_4# a_2_6# Gnd nfet w=1u l=0.2u + ad=0p pd=0u as=0p ps=0u M21 a_57_6# a_47_71# a_23_27# Gnd nfet w=1u l=0.2u + ad=0p pd=0u as=0p ps=0u M22 gnd D a_57_6# Gnd nfet w=1u l=0.2u + ad=0p pd=0u as=0p ps=0u M23 gnd a_47_71# a_47_4# Gnd nfet w=1u l=0.2u + ad=0p pd=0u as=0p ps=0u M24 a_47_71# CLK gnd Gnd nfet w=1u l=0.2u + ad=0p pd=0u as=0p ps=0u M25 a_105_6# a_47_4# a_10_61# Gnd nfet w=1u l=0.2u + ad=0p pd=0u as=0p ps=0u M26 a_113_6# a_47_71# a_105_6# Gnd nfet w=1u l=0.2u + ad=0p pd=0u as=0p ps=0u M27 a_130_6# a_105_6# a_122_6# Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M28 gnd R a_130_6# Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M29 a_146_6# a_122_6# gnd Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M30 a_113_6# S a_146_6# Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M31 gnd a_122_6# Q Gnd nfet w=1u l=0.2u + ad=0p pd=0u as=0p ps=0u .ends DFFSR .subckt FAX1 gnd vdd A B C YC YS M0 vdd A a_2_54# vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M1 a_2_54# B vdd vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M2 a_25_6# C a_2_54# vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M3 a_33_54# B a_25_6# vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M4 vdd A a_33_54# vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M5 a_46_54# A vdd vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M6 vdd B a_46_54# vdd pfet w=3.6u l=0.2u + ad=0p pd=0u as=0p ps=0u M7 a_46_54# C vdd vdd pfet w=3.6u l=0.2u + ad=0p pd=0u as=0p ps=0u M8 a_70_6# a_25_6# a_46_54# vdd pfet w=3.6u l=0.2u + ad=0p pd=0u as=0p ps=0u M9 a_79_46# C a_70_6# vdd pfet w=4.8u l=0.2u + ad=0p pd=0u as=0p ps=0u M10 a_84_46# B a_79_46# vdd pfet w=4.8u l=0.2u + ad=0p pd=0u as=0p ps=0u M11 vdd A a_84_46# vdd pfet w=4.8u l=0.2u + ad=0p pd=0u as=0p ps=0u M12 YS a_70_6# vdd vdd pfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M13 YC a_25_6# vdd vdd pfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M14 gnd A a_2_6# Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M15 a_2_6# B gnd Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M16 a_25_6# C a_2_6# Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M17 a_33_6# B a_25_6# Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M18 gnd A a_33_6# Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M19 a_46_6# A gnd Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M20 gnd B a_46_6# Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M21 a_46_6# C gnd Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M22 a_70_6# a_25_6# a_46_6# Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M23 a_79_6# C a_70_6# Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M24 a_84_6# B a_79_6# Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M25 gnd A a_84_6# Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M26 YS a_70_6# gnd Gnd nfet w=1u l=0.2u + ad=0p pd=0u as=0p ps=0u M27 YC a_25_6# gnd Gnd nfet w=1u l=0.2u + ad=0p pd=0u as=0p ps=0u .ends FAX1 .subckt HAX1 vdd gnd YC A B YS M0 vdd A a_2_74# vdd pfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M1 a_2_74# B vdd vdd pfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M2 vdd a_2_74# YC vdd pfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M3 a_41_74# a_2_74# vdd vdd pfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M4 a_49_54# B a_41_74# vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M5 vdd A a_49_54# vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M6 YS a_41_74# vdd vdd pfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M7 a_9_6# A gnd Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M8 a_2_74# B a_9_6# Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M9 gnd a_2_74# YC Gnd nfet w=1u l=0.2u + ad=0p pd=0u as=0p ps=0u M10 a_38_6# a_2_74# gnd Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M11 a_41_74# B a_38_6# Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M12 a_38_6# A a_41_74# Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M13 YS a_41_74# gnd Gnd nfet w=1u l=0.2u + ad=0p pd=0u as=0p ps=0u .ends HAX1 .subckt INVX1 A Y vdd gnd M0 Y A vdd vdd pfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M1 Y A gnd Gnd nfet w=1u l=0.2u + ad=0p pd=0u as=0p ps=0u .ends INVX1 .subckt INVX2 vdd gnd Y A M0 Y A vdd vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M1 Y A gnd Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u .ends INVX2 .subckt INVX4 vdd gnd Y A M0 Y A vdd vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M1 vdd A Y vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M2 Y A gnd Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M3 gnd A Y Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u .ends INVX4 .subckt INVX8 vdd gnd A Y M0 Y A vdd vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M1 vdd A Y vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M2 Y A vdd vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M3 vdd A Y vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M4 Y A gnd Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M5 gnd A Y Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M6 Y A gnd Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M7 gnd A Y Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u .ends INVX8 .subckt LATCH D Q gnd vdd CLK M0 vdd CLK a_2_6# vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M1 a_18_74# D vdd vdd pfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M2 a_23_6# a_2_6# a_18_74# vdd pfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M3 a_35_84# CLK a_23_6# vdd pfet w=1u l=0.2u + ad=0p pd=0u as=0p ps=0u M4 vdd Q a_35_84# vdd pfet w=1u l=0.2u + ad=0p pd=0u as=0p ps=0u M5 gnd CLK a_2_6# Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M6 Q a_23_6# vdd vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M7 a_18_6# D gnd Gnd nfet w=1u l=0.2u + ad=0p pd=0u as=0p ps=0u M8 a_23_6# CLK a_18_6# Gnd nfet w=1u l=0.2u + ad=0p pd=0u as=0p ps=0u M9 a_35_6# a_2_6# a_23_6# Gnd nfet w=1u l=0.2u + ad=0p pd=0u as=0p ps=0u M10 gnd Q a_35_6# Gnd nfet w=1u l=0.2u + ad=0p pd=0u as=0p ps=0u M11 Q a_23_6# gnd Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u .ends LATCH .subckt MUX2X1 S vdd gnd Y A B M0 vdd S a_2_10# vdd pfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M1 a_17_50# B vdd vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M2 Y S a_17_50# vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M3 a_30_54# a_2_10# Y vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M4 vdd A a_30_54# vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M5 gnd S a_2_10# Gnd nfet w=1u l=0.2u + ad=0p pd=0u as=0p ps=0u M6 a_17_10# B gnd Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M7 Y a_2_10# a_17_10# Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M8 a_30_10# S Y Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M9 gnd A a_30_10# Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u .ends MUX2X1 .subckt NAND2X1 vdd Y gnd A B M0 Y A vdd vdd pfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M1 vdd B Y vdd pfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M2 a_9_6# A gnd Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M3 Y B a_9_6# Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u .ends NAND2X1 .subckt NAND3X1 B vdd gnd A C Y M0 Y A vdd vdd pfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M1 vdd B Y vdd pfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M2 Y C vdd vdd pfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M3 a_9_6# A gnd Gnd nfet w=3u l=0.2u + ad=0p pd=0u as=0p ps=0u M4 a_14_6# B a_9_6# Gnd nfet w=3u l=0.2u + ad=0p pd=0u as=0p ps=0u M5 Y C a_14_6# Gnd nfet w=3u l=0.2u + ad=0p pd=0u as=0p ps=0u .ends NAND3X1 .subckt NOR2X1 vdd B gnd Y A M0 a_9_54# A vdd vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M1 Y B a_9_54# vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M2 Y A gnd Gnd nfet w=1u l=0.2u + ad=0p pd=0u as=0p ps=0u M3 gnd B Y Gnd nfet w=1u l=0.2u + ad=0p pd=0u as=0p ps=0u .ends NOR2X1 .subckt NOR3X1 vdd gnd B C A Y M0 vdd A a_2_64# vdd pfet w=3u l=0.2u + ad=0p pd=0u as=0p ps=0u M1 a_2_64# A vdd vdd pfet w=3u l=0.2u + ad=0p pd=0u as=0p ps=0u M2 a_25_64# B a_2_64# vdd pfet w=3u l=0.2u + ad=0p pd=0u as=0p ps=0u M3 a_2_64# B a_25_64# vdd pfet w=3u l=0.2u + ad=0p pd=0u as=0p ps=0u M4 Y C a_25_64# vdd pfet w=3u l=0.2u + ad=0p pd=0u as=0p ps=0u M5 a_25_64# C Y vdd pfet w=3u l=0.2u + ad=0p pd=0u as=0p ps=0u M6 Y A gnd Gnd nfet w=1u l=0.2u + ad=0p pd=0u as=0p ps=0u M7 gnd B Y Gnd nfet w=1u l=0.2u + ad=0p pd=0u as=0p ps=0u M8 Y C gnd Gnd nfet w=1u l=0.2u + ad=0p pd=0u as=0p ps=0u .ends NOR3X1 .subckt OAI21X1 gnd vdd A B Y C M0 a_9_54# A vdd vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M1 Y B a_9_54# vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M2 vdd C Y vdd pfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M3 gnd A a_2_6# Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M4 a_2_6# B gnd Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M5 Y C a_2_6# Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u .ends OAI21X1 .subckt OAI22X1 gnd vdd D C A B Y M0 a_9_54# A vdd vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M1 Y B a_9_54# vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M2 a_28_54# D Y vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M3 vdd C a_28_54# vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M4 gnd A a_2_6# Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M5 a_2_6# B gnd Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M6 Y D a_2_6# Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M7 a_2_6# C Y Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u .ends OAI22X1 .subckt OR2X1 Y B vdd gnd A M0 a_9_54# A a_2_54# vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M1 vdd B a_9_54# vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M2 Y a_2_54# vdd vdd pfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M3 a_2_54# A gnd Gnd nfet w=1u l=0.2u + ad=0p pd=0u as=0p ps=0u M4 gnd B a_2_54# Gnd nfet w=1u l=0.2u + ad=0p pd=0u as=0p ps=0u M5 Y a_2_54# gnd Gnd nfet w=1u l=0.2u + ad=0p pd=0u as=0p ps=0u .ends OR2X1 .subckt OR2X2 Y B vdd gnd A M0 a_9_54# A a_2_54# vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M1 vdd B a_9_54# vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M2 Y a_2_54# vdd vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M3 a_2_54# A gnd Gnd nfet w=1u l=0.2u + ad=0p pd=0u as=0p ps=0u M4 gnd B a_2_54# Gnd nfet w=1u l=0.2u + ad=0p pd=0u as=0p ps=0u M5 Y a_2_54# gnd Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u .ends OR2X2 .subckt TBUFX1 vdd gnd EN A Y M0 a_9_6# EN vdd vdd pfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M1 a_26_54# a_9_6# Y vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M2 vdd A a_26_54# vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M3 a_9_6# EN gnd Gnd nfet w=1u l=0.2u + ad=0p pd=0u as=0p ps=0u M4 a_26_6# EN Y Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M5 gnd A a_26_6# Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u .ends TBUFX1 .subckt TBUFX2 vdd gnd A EN Y M0 a_9_6# EN vdd vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M1 Y a_9_6# a_18_54# vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M2 a_18_54# a_9_6# Y vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M3 vdd A a_18_54# vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M4 a_18_54# A vdd vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M5 a_9_6# EN gnd Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M6 Y EN a_18_6# Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M7 a_18_6# EN Y Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M8 gnd A a_18_6# Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M9 a_18_6# A gnd Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u .ends TBUFX2 .subckt XNOR2X1 A B gnd vdd Y M0 vdd A a_2_6# vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M1 a_18_54# a_12_41# vdd vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M2 Y a_2_6# a_18_54# vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M3 a_35_54# A Y vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M4 vdd B a_35_54# vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M5 a_12_41# B vdd vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M6 gnd A a_2_6# Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M7 a_18_6# a_12_41# gnd Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M8 Y A a_18_6# Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M9 a_35_6# a_2_6# Y Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M10 gnd B a_35_6# Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M11 a_12_41# B gnd Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u .ends XNOR2X1 .subckt XOR2X1 Y vdd B A gnd M0 vdd A a_2_6# vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M1 a_18_54# a_13_43# vdd vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M2 Y A a_18_54# vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M3 a_35_54# a_2_6# Y vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M4 vdd B a_35_54# vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M5 a_13_43# B vdd vdd pfet w=4u l=0.2u + ad=0p pd=0u as=0p ps=0u M6 gnd A a_2_6# Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M7 a_18_6# a_13_43# gnd Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M8 Y a_2_6# a_18_6# Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M9 a_35_6# A Y Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M10 gnd B a_35_6# Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u M11 a_13_43# B gnd Gnd nfet w=2u l=0.2u + ad=0p pd=0u as=0p ps=0u .ends XOR2X1 qflow-1.1.23/tech/osu018/osu018_stdcells.lib0000775000175000001440000074522712535603240017072 0ustar timusers/* delay model : typ check model : typ power model : typ capacitance model : typ other model : typ */ library(osu018_stdcells) { delay_model : table_lookup; in_place_swap_mode : match_footprint; /* unit attributes */ time_unit : "1ns"; voltage_unit : "1V"; current_unit : "1uA"; pulling_resistance_unit : "1kohm"; leakage_power_unit : "1nW"; capacitive_load_unit (1,pf); slew_upper_threshold_pct_rise : 80; slew_lower_threshold_pct_rise : 20; slew_upper_threshold_pct_fall : 80; slew_lower_threshold_pct_fall : 20; input_threshold_pct_rise : 50; input_threshold_pct_fall : 50; output_threshold_pct_rise : 50; output_threshold_pct_fall : 50; nom_process : 1; nom_voltage : 1.8; nom_temperature : 25; operating_conditions ( typical ) { process : 1; voltage : 1.8; temperature : 25; } default_operating_conditions : typical; lu_table_template(delay_template_5x1) { variable_1 : input_net_transition; index_1 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0"); } lu_table_template(delay_template_5x5) { variable_1 : total_output_net_capacitance; variable_2 : input_net_transition; index_1 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0"); index_2 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0"); } lu_table_template(delay_template_5x6) { variable_1 : total_output_net_capacitance; variable_2 : input_net_transition; index_1 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0"); index_2 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"); } lu_table_template(delay_template_6x6) { variable_1 : total_output_net_capacitance; variable_2 : input_net_transition; index_1 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"); index_2 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"); } power_lut_template(energy_template_5x5) { variable_1 : total_output_net_capacitance; variable_2 : input_transition_time; index_1 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0"); index_2 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0"); } power_lut_template(energy_template_5x6) { variable_1 : total_output_net_capacitance; variable_2 : input_transition_time; index_1 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0"); index_2 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"); } power_lut_template(energy_template_6x6) { variable_1 : total_output_net_capacitance; variable_2 : input_transition_time; index_1 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"); index_2 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"); } lu_table_template(hold_template_3x5) { variable_1 : related_pin_transition; variable_2 : constrained_pin_transition; index_1 ("1000.0, 1001.0, 1002.0"); index_2 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0"); } lu_table_template(hold_template_3x6) { variable_1 : related_pin_transition; variable_2 : constrained_pin_transition; index_1 ("1000.0, 1001.0, 1002.0"); index_2 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"); } power_lut_template(passive_energy_template_5x1) { variable_1 : input_transition_time; index_1 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0"); } power_lut_template(passive_energy_template_6x1) { variable_1 : input_transition_time; index_1 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"); } lu_table_template(recovery_template_3x6) { variable_1 : related_pin_transition; variable_2 : constrained_pin_transition; index_1 ("1000.0, 1001.0, 1002.0"); index_2 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"); } lu_table_template(recovery_template_6x6) { variable_1 : related_pin_transition; variable_2 : constrained_pin_transition; index_1 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"); index_2 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"); } lu_table_template(removal_template_3x6) { variable_1 : related_pin_transition; variable_2 : constrained_pin_transition; index_1 ("1000.0, 1001.0, 1002.0"); index_2 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"); } lu_table_template(setup_template_3x5) { variable_1 : related_pin_transition; variable_2 : constrained_pin_transition; index_1 ("1000.0, 1001.0, 1002.0"); index_2 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0"); } lu_table_template(setup_template_3x6) { variable_1 : related_pin_transition; variable_2 : constrained_pin_transition; index_1 ("1000.0, 1001.0, 1002.0"); index_2 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"); } /* --------------- * * Design : AND2X1 * * --------------- */ cell (AND2X1) { area : 32; cell_leakage_power : 0.0746794; pin(A) { direction : input; capacitance : 0.0129077; rise_capacitance : 0.0129077; fall_capacitance : 0.0128842; } pin(B) { direction : input; capacitance : 0.0125298; rise_capacitance : 0.0125298; fall_capacitance : 0.0122586; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.505476; function : "(A B)"; timing() { related_pin : "A"; timing_sense : positive_unate; cell_rise(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.06367, 0.070461, 0.076801, 0.076477, 0.064975", \ "0.078318, 0.085985, 0.097551, 0.097523, 0.084151", \ "0.101102, 0.106523, 0.116541, 0.12064, 0.109008", \ "0.186369, 0.192402, 0.20213, 0.204066, 0.197112", \ "0.311845, 0.327388, 0.329449, 0.331209, 0.325543"); } rise_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.03002, 0.034126, 0.049111, 0.051622, 0.058375", \ "0.043159, 0.047719, 0.05847, 0.0606, 0.075", \ "0.0738, 0.0726, 0.0786, 0.0882, 0.0936", \ "0.1884, 0.189, 0.1908, 0.192, 0.1968", \ "0.366, 0.3666, 0.3684, 0.369, 0.3732"); } cell_fall(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.076128, 0.106375, 0.152212, 0.183594, 0.267424", \ "0.089908, 0.120622, 0.171438, 0.198723, 0.290365", \ "0.111016, 0.141837, 0.194222, 0.221808, 0.312359", \ "0.184884, 0.217444, 0.268203, 0.297785, 0.394616", \ "0.295351, 0.333462, 0.380054, 0.411544, 0.506596"); } fall_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.023191, 0.030696, 0.049255, 0.05222, 0.0624", \ "0.038144, 0.042236, 0.054779, 0.066, 0.0702", \ "0.0648, 0.0642, 0.0744, 0.0744, 0.0876", \ "0.1506, 0.1512, 0.153, 0.1566, 0.1608", \ "0.291, 0.2916, 0.2928, 0.2928, 0.2964"); } } timing() { related_pin : "B"; timing_sense : positive_unate; cell_rise(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.065215, 0.070029, 0.065114, 0.06797, 0.030044", \ "0.080046, 0.085518, 0.084303, 0.085736, 0.052763", \ "0.102829, 0.108928, 0.108632, 0.109566, 0.080609", \ "0.188114, 0.194154, 0.19869, 0.195568, 0.171942", \ "0.313575, 0.323664, 0.32479, 0.321763, 0.301292"); } rise_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.02568, 0.030953, 0.040555, 0.052662, 0.058886", \ "0.04175, 0.049456, 0.06, 0.0696, 0.0768", \ "0.0738, 0.0714, 0.0804, 0.087, 0.093", \ "0.1884, 0.1878, 0.1908, 0.1926, 0.1992", \ "0.366, 0.3666, 0.3672, 0.3684, 0.3744"); } cell_fall(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.086342, 0.123374, 0.175522, 0.217083, 0.314459", \ "0.101176, 0.139097, 0.191667, 0.230985, 0.335929", \ "0.121305, 0.16117, 0.21439, 0.251706, 0.358423", \ "0.19482, 0.23553, 0.289847, 0.328581, 0.439064", \ "0.306582, 0.349002, 0.400715, 0.439677, 0.549921"); } fall_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.025127, 0.029204, 0.03336, 0.051446, 0.049241", \ "0.03916, 0.041168, 0.047199, 0.055391, 0.0648", \ "0.0636, 0.069, 0.0678, 0.078, 0.0774", \ "0.1512, 0.1518, 0.1536, 0.1548, 0.1578", \ "0.291, 0.2904, 0.291, 0.2928, 0.2946"); } } internal_power() { related_pin : "A"; rise_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.012351, 0.01753, 0.032859, 0.046092, 0.090803", \ "0.013339, 0.017698, 0.032616, 0.045498, 0.08953", \ "0.013729, 0.018863, 0.033136, 0.045572, 0.08851", \ "0.014763, 0.019558, 0.033444, 0.045067, 0.086251", \ "0.015252, 0.020471, 0.033879, 0.045469, 0.086416"); } fall_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.051843, 0.061484, 0.075909, 0.087394, 0.131465", \ "0.053948, 0.063015, 0.075339, 0.087007, 0.129259", \ "0.054045, 0.062985, 0.07537, 0.086885, 0.1283", \ "0.054653, 0.062832, 0.075179, 0.087109, 0.127955", \ "0.05485, 0.062533, 0.07543, 0.087243, 0.127915"); } } internal_power() { related_pin : "B"; rise_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.013537, 0.018652, 0.030058, 0.044763, 0.08865", \ "0.014079, 0.018327, 0.030221, 0.044563, 0.086591", \ "0.014302, 0.018522, 0.030189, 0.043793, 0.085708", \ "0.01524, 0.018832, 0.030544, 0.042699, 0.085217", \ "0.015577, 0.018888, 0.031139, 0.043193, 0.085027"); } fall_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.062565, 0.073373, 0.086577, 0.10111, 0.1452", \ "0.065226, 0.072689, 0.085935, 0.100245, 0.143405", \ "0.065879, 0.073131, 0.086345, 0.099667, 0.142411", \ "0.06752, 0.07374, 0.08798, 0.099495, 0.141641", \ "0.067305, 0.074406, 0.08846, 0.100126, 0.141826"); } } } } /* --------------- * * Design : AND2X2 * * --------------- */ cell (AND2X2) { area : 32; cell_leakage_power : 0.090278; pin(A) { direction : input; capacitance : 0.0129068; rise_capacitance : 0.0128698; fall_capacitance : 0.0129068; } pin(B) { direction : input; capacitance : 0.0125119; rise_capacitance : 0.0125119; fall_capacitance : 0.0122677; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.975557; function : "(A B)"; timing() { related_pin : "A"; timing_sense : positive_unate; cell_rise(delay_template_5x5) { index_1 ("0.01, 0.025, 0.05, 0.15, 0.3"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.079151, 0.091168, 0.112401, 0.116815, 0.110012", \ "0.094906, 0.109298, 0.130095, 0.135144, 0.12883", \ "0.119494, 0.131824, 0.155457, 0.159344, 0.157233", \ "0.206917, 0.222384, 0.241527, 0.246456, 0.248042", \ "0.336707, 0.351629, 0.370971, 0.375914, 0.378028"); } rise_transition(delay_template_5x5) { index_1 ("0.01, 0.025, 0.05, 0.15, 0.3"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.035696, 0.039511, 0.054169, 0.05627, 0.0702", \ "0.051008, 0.056876, 0.0702, 0.0726, 0.0798", \ "0.0756, 0.0798, 0.0894, 0.0918, 0.1056", \ "0.1932, 0.1968, 0.1974, 0.1992, 0.2058", \ "0.378, 0.378, 0.3798, 0.381, 0.384"); } cell_fall(delay_template_5x5) { index_1 ("0.01, 0.025, 0.05, 0.15, 0.3"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.093907, 0.13403, 0.18857, 0.218416, 0.32176", \ "0.109237, 0.15259, 0.205536, 0.241165, 0.340988", \ "0.132441, 0.175416, 0.229071, 0.263575, 0.366037", \ "0.214386, 0.257165, 0.311103, 0.348813, 0.453364", \ "0.334685, 0.376026, 0.432567, 0.46796, 0.572264"); } fall_transition(delay_template_5x5) { index_1 ("0.01, 0.025, 0.05, 0.15, 0.3"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.032309, 0.035034, 0.053938, 0.0618, 0.0654", \ "0.054496, 0.0581, 0.069, 0.0696, 0.0768", \ "0.0732, 0.075, 0.0786, 0.0876, 0.0978", \ "0.1632, 0.1662, 0.1668, 0.1704, 0.1764", \ "0.3156, 0.315, 0.3156, 0.3174, 0.3204"); } } timing() { related_pin : "B"; timing_sense : positive_unate; cell_rise(delay_template_5x5) { index_1 ("0.01, 0.025, 0.05, 0.15, 0.3"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.081559, 0.090357, 0.092534, 0.091354, 0.070717", \ "0.097397, 0.107931, 0.113633, 0.110762, 0.095186", \ "0.121832, 0.129937, 0.138311, 0.139972, 0.12199", \ "0.208737, 0.218082, 0.225122, 0.227706, 0.21528", \ "0.338379, 0.353386, 0.358576, 0.359126, 0.346878"); } rise_transition(delay_template_5x5) { index_1 ("0.01, 0.025, 0.05, 0.15, 0.3"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.036916, 0.048718, 0.047469, 0.059474, 0.0684", \ "0.05105, 0.055258, 0.063, 0.0684, 0.0792", \ "0.0756, 0.0792, 0.0906, 0.0912, 0.1014", \ "0.1938, 0.1962, 0.1968, 0.1992, 0.2064", \ "0.378, 0.378, 0.3792, 0.3804, 0.3852"); } cell_fall(delay_template_5x5) { index_1 ("0.01, 0.025, 0.05, 0.15, 0.3"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.103564, 0.145068, 0.207945, 0.242964, 0.357798", \ "0.119673, 0.162172, 0.227495, 0.263905, 0.381804", \ "0.143018, 0.187723, 0.250938, 0.290462, 0.406679", \ "0.224466, 0.268745, 0.332739, 0.372766, 0.491968", \ "0.345577, 0.387664, 0.45055, 0.491515, 0.610706"); } fall_transition(delay_template_5x5) { index_1 ("0.01, 0.025, 0.05, 0.15, 0.3"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.030793, 0.033285, 0.041193, 0.049891, 0.0606", \ "0.051182, 0.054372, 0.05968, 0.0696, 0.0726", \ "0.072, 0.069, 0.0846, 0.0876, 0.0924", \ "0.1668, 0.1668, 0.1686, 0.1686, 0.1722", \ "0.3156, 0.3156, 0.3168, 0.3168, 0.318"); } } internal_power() { related_pin : "A"; rise_power(energy_template_5x5) { index_1 ("0.01, 0.025, 0.05, 0.15, 0.3"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.035999, 0.038715, 0.059579, 0.073077, 0.118449", \ "0.037968, 0.039043, 0.059066, 0.07139, 0.11484", \ "0.038182, 0.039703, 0.057496, 0.069577, 0.112525", \ "0.039912, 0.043893, 0.056441, 0.06669, 0.107963", \ "0.040724, 0.04515, 0.056218, 0.067369, 0.107406"); } fall_power(energy_template_5x5) { index_1 ("0.01, 0.025, 0.05, 0.15, 0.3"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.074272, 0.081015, 0.097734, 0.112162, 0.158445", \ "0.073801, 0.081767, 0.096117, 0.108499, 0.153047", \ "0.076291, 0.082021, 0.095328, 0.107162, 0.149707", \ "0.078079, 0.082673, 0.096068, 0.107066, 0.147203", \ "0.0781, 0.083521, 0.096298, 0.107338, 0.147001"); } } internal_power() { related_pin : "B"; rise_power(energy_template_5x5) { index_1 ("0.01, 0.025, 0.05, 0.15, 0.3"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.038631, 0.040743, 0.05645, 0.068737, 0.116469", \ "0.040765, 0.040589, 0.055418, 0.067048, 0.112598", \ "0.040617, 0.040473, 0.054706, 0.06586, 0.110001", \ "0.041329, 0.041845, 0.054698, 0.065431, 0.10611", \ "0.041651, 0.042621, 0.054878, 0.065731, 0.105909"); } fall_power(energy_template_5x5) { index_1 ("0.01, 0.025, 0.05, 0.15, 0.3"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.084865, 0.09187, 0.111881, 0.123101, 0.172144", \ "0.087084, 0.092993, 0.111047, 0.120415, 0.168159", \ "0.088325, 0.09227, 0.108629, 0.121633, 0.165087", \ "0.090064, 0.094995, 0.109267, 0.120689, 0.161319", \ "0.090229, 0.095784, 0.109314, 0.120709, 0.161502"); } } } } /* ---------------- * * Design : AOI21X1 * * ---------------- */ cell (AOI21X1) { area : 32; cell_leakage_power : 0.0515209; pin(A) { direction : input; capacitance : 0.0173593; rise_capacitance : 0.0170698; fall_capacitance : 0.0173593; } pin(B) { direction : input; capacitance : 0.0179733; rise_capacitance : 0.0174936; fall_capacitance : 0.0179733; } pin(C) { direction : input; capacitance : 0.0150799; rise_capacitance : 0.0150575; fall_capacitance : 0.0150799; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.494067; function : "(!((A B)+C))"; timing() { related_pin : "A"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.047915, 0.060212, 0.067163, 0.069103, 0.070089", \ "0.05909, 0.074221, 0.08307, 0.09116, 0.096894", \ "0.076858, 0.094301, 0.110559, 0.120474, 0.134719", \ "0.13882, 0.160652, 0.194186, 0.212651, 0.254514", \ "0.231208, 0.253692, 0.295337, 0.321981, 0.388552"); } fall_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.034132, 0.063, 0.0906, 0.1116, 0.168", \ "0.052839, 0.0732, 0.108, 0.1272, 0.1932", \ "0.0672, 0.0882, 0.1242, 0.144, 0.219", \ "0.1464, 0.1536, 0.1878, 0.2166, 0.3024", \ "0.2676, 0.2688, 0.291, 0.3162, 0.4056"); } cell_rise(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.064718, 0.082701, 0.106751, 0.125102, 0.180744", \ "0.080174, 0.098818, 0.126855, 0.147241, 0.210669", \ "0.100295, 0.124476, 0.155884, 0.179478, 0.251019", \ "0.189553, 0.21113, 0.256309, 0.285843, 0.375986", \ "0.31622, 0.336614, 0.386991, 0.424065, 0.529812"); } rise_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.048645, 0.0678, 0.0918, 0.1146, 0.1578", \ "0.06, 0.0816, 0.1128, 0.1278, 0.1794", \ "0.09, 0.1068, 0.135, 0.153, 0.2148", \ "0.2082, 0.2124, 0.2388, 0.261, 0.3264", \ "0.3858, 0.3852, 0.3996, 0.4188, 0.492"); } } timing() { related_pin : "B"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.049492, 0.060665, 0.079308, 0.091203, 0.11301", \ "0.059982, 0.083223, 0.105699, 0.115734, 0.142968", \ "0.075933, 0.10303, 0.132388, 0.150129, 0.184911", \ "0.138897, 0.172235, 0.225315, 0.253245, 0.316038", \ "0.232339, 0.264177, 0.331505, 0.373206, 0.467627"); } fall_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.036341, 0.06, 0.102, 0.1212, 0.1794", \ "0.054499, 0.0828, 0.114, 0.1374, 0.201", \ "0.0666, 0.0948, 0.1344, 0.159, 0.2376", \ "0.1464, 0.1572, 0.2076, 0.2388, 0.3348", \ "0.2676, 0.2682, 0.303, 0.3408, 0.4542"); } cell_rise(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.055077, 0.073278, 0.084771, 0.098675, 0.132128", \ "0.070455, 0.087716, 0.1086, 0.124224, 0.167364", \ "0.092563, 0.114522, 0.141653, 0.160472, 0.214472", \ "0.181857, 0.201909, 0.245085, 0.272242, 0.351721", \ "0.309465, 0.3284, 0.377731, 0.413032, 0.511912"); } rise_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.039657, 0.057392, 0.0918, 0.1104, 0.1548", \ "0.051732, 0.075, 0.1008, 0.1248, 0.1794", \ "0.0828, 0.0966, 0.1284, 0.1518, 0.21", \ "0.1986, 0.2022, 0.2298, 0.2532, 0.3234", \ "0.3756, 0.3762, 0.3912, 0.411, 0.486"); } } timing() { related_pin : "C"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.040927, 0.054774, 0.07418, 0.082139, 0.103563", \ "0.055377, 0.076133, 0.100949, 0.114073, 0.146048", \ "0.074977, 0.103939, 0.138062, 0.157255, 0.201662", \ "0.150359, 0.185939, 0.249198, 0.282431, 0.362184", \ "0.263086, 0.297154, 0.37096, 0.422663, 0.541719"); } fall_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.032516, 0.062798, 0.0975, 0.1203, 0.1728", \ "0.048692, 0.0774, 0.1134, 0.1371, 0.2022", \ "0.0663, 0.0906, 0.138, 0.1641, 0.2382", \ "0.1602, 0.1671, 0.2166, 0.2541, 0.3528", \ "0.2994, 0.2997, 0.3258, 0.363, 0.4899"); } cell_rise(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.047529, 0.066647, 0.090407, 0.10183, 0.137361", \ "0.059937, 0.084705, 0.114419, 0.133901, 0.177228", \ "0.078431, 0.112276, 0.150614, 0.173776, 0.230771", \ "0.154015, 0.191568, 0.259108, 0.296207, 0.387531", \ "0.265695, 0.302125, 0.380136, 0.434427, 0.565985"); } rise_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.041826, 0.0747, 0.0897, 0.111, 0.1569", \ "0.053506, 0.0849, 0.1134, 0.1293, 0.1863", \ "0.0768, 0.1044, 0.141, 0.1611, 0.2268", \ "0.1791, 0.186, 0.2325, 0.2679, 0.3531", \ "0.3339, 0.3345, 0.3603, 0.3945, 0.5094"); } } internal_power() { related_pin : "A"; fall_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.01884, 0.015378, 0.002987, 0.018991, 0.076233", \ "0.018379, 0.014956, 0.000845, 0.016266, 0.071924", \ "0.018063, 0.015186, 0.00144, 0.012644, 0.065864", \ "0.017216, 0.016158, 0.006591, 0.004175, 0.04943", \ "0.016838, 0.016602, 0.009608, 0.001584, 0.035332"); } rise_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.091023, 0.091252, 0.108402, 0.124045, 0.182645", \ "0.089299, 0.091534, 0.10694, 0.121957, 0.179202", \ "0.090732, 0.091004, 0.104261, 0.118649, 0.174125", \ "0.09076, 0.090645, 0.100016, 0.111306, 0.158859", \ "0.091388, 0.091076, 0.097453, 0.106102, 0.145954"); } } internal_power() { related_pin : "B"; fall_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.018566, 0.013046, 0.004696, 0.020236, 0.074908", \ "0.018223, 0.01362, 0.002409, 0.017471, 0.070868", \ "0.017705, 0.013684, 0.00017, 0.013747, 0.065047", \ "0.017097, 0.015358, 0.005946, 0.004681, 0.048729", \ "0.016861, 0.016115, 0.009462, 0.001479, 0.034466"); } rise_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.076734, 0.079298, 0.095157, 0.110941, 0.166091", \ "0.077202, 0.07904, 0.09362, 0.10795, 0.162013", \ "0.0786, 0.078901, 0.091229, 0.10469, 0.156162", \ "0.080713, 0.079266, 0.087636, 0.097937, 0.14147", \ "0.082064, 0.080484, 0.085746, 0.093548, 0.129674"); } } internal_power() { related_pin : "C"; fall_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.018953, 0.013695, 0.002159, 0.014727, 0.058473", \ "0.018108, 0.014132, 0.000778, 0.011816, 0.054292", \ "0.016648, 0.014865, 0.002678, 0.008304, 0.048784", \ "0.014337, 0.014426, 0.007209, 0.000966, 0.034909", \ "0.013051, 0.013508, 0.00931, 0.00346, 0.023891"); } rise_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.052359, 0.058578, 0.072513, 0.084065, 0.125476", \ "0.052467, 0.057513, 0.070505, 0.081461, 0.121554", \ "0.052973, 0.056219, 0.067995, 0.078279, 0.116559", \ "0.054189, 0.054888, 0.063141, 0.071481, 0.104394", \ "0.054944, 0.055102, 0.060377, 0.066747, 0.094347"); } } } } /* ---------------- * * Design : AOI22X1 * * ---------------- */ cell (AOI22X1) { area : 40; cell_leakage_power : 0.0588648; pin(A) { direction : input; capacitance : 0.0173718; rise_capacitance : 0.0170846; fall_capacitance : 0.0173718; } pin(B) { direction : input; capacitance : 0.0179972; rise_capacitance : 0.0175034; fall_capacitance : 0.0179972; } pin(C) { direction : input; capacitance : 0.0182378; rise_capacitance : 0.0182378; fall_capacitance : 0.0180284; } pin(D) { direction : input; capacitance : 0.0186552; rise_capacitance : 0.0186345; fall_capacitance : 0.0186552; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.484829; function : "(!((A B)+(C D)))"; timing() { related_pin : "A"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.059558, 0.073754, 0.085031, 0.09237, 0.102238", \ "0.07058, 0.086236, 0.101938, 0.110973, 0.125485", \ "0.086388, 0.104904, 0.127903, 0.139455, 0.161089", \ "0.149571, 0.171416, 0.206445, 0.227382, 0.273242", \ "0.242188, 0.264574, 0.306552, 0.334379, 0.404558"); } fall_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.051245, 0.0717, 0.1065, 0.1296, 0.1908", \ "0.062189, 0.0804, 0.1167, 0.1398, 0.2076", \ "0.081, 0.0972, 0.1335, 0.1593, 0.2328", \ "0.1605, 0.1662, 0.2013, 0.2277, 0.3117", \ "0.2802, 0.2814, 0.3018, 0.3273, 0.4173"); } cell_rise(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.077033, 0.09881, 0.125826, 0.145776, 0.206338", \ "0.089617, 0.113047, 0.142975, 0.164835, 0.231783", \ "0.107809, 0.13482, 0.170236, 0.194768, 0.268272", \ "0.184454, 0.210985, 0.262028, 0.29356, 0.386243", \ "0.296011, 0.322621, 0.379046, 0.41979, 0.531586"); } rise_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.057564, 0.0732, 0.1017, 0.1257, 0.1743", \ "0.070588, 0.0864, 0.1191, 0.1395, 0.1953", \ "0.0957, 0.1083, 0.1437, 0.1635, 0.2259", \ "0.1986, 0.204, 0.2322, 0.2577, 0.33", \ "0.3549, 0.3546, 0.372, 0.3945, 0.4758"); } } timing() { related_pin : "B"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.060499, 0.083279, 0.106107, 0.118099, 0.147539", \ "0.070377, 0.096739, 0.123079, 0.139748, 0.17443", \ "0.086504, 0.115719, 0.152173, 0.169862, 0.213697", \ "0.149623, 0.18266, 0.239418, 0.268681, 0.337737", \ "0.243324, 0.274964, 0.342875, 0.386367, 0.485573"); } fall_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.051394, 0.0804, 0.1155, 0.1389, 0.204", \ "0.062424, 0.0867, 0.1257, 0.1533, 0.2229", \ "0.0816, 0.1029, 0.147, 0.1761, 0.2544", \ "0.1608, 0.1704, 0.219, 0.2526, 0.3495", \ "0.2802, 0.2817, 0.3138, 0.351, 0.4674"); } cell_rise(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.069362, 0.087059, 0.107361, 0.122199, 0.163316", \ "0.081873, 0.103323, 0.128196, 0.144999, 0.193609", \ "0.10122, 0.125231, 0.156939, 0.177262, 0.235215", \ "0.177716, 0.203377, 0.251819, 0.281169, 0.363544", \ "0.28987, 0.315506, 0.370789, 0.409941, 0.515064"); } rise_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.047614, 0.0672, 0.0957, 0.1209, 0.1779", \ "0.061365, 0.0798, 0.114, 0.1344, 0.1977", \ "0.0885, 0.1008, 0.1374, 0.1584, 0.225", \ "0.1905, 0.195, 0.2262, 0.2529, 0.3279", \ "0.3468, 0.3462, 0.3645, 0.387, 0.4719"); } } timing() { related_pin : "C"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.043116, 0.051263, 0.049222, 0.046851, 0.028806", \ "0.053362, 0.064879, 0.070894, 0.070263, 0.060648", \ "0.070468, 0.084656, 0.098411, 0.103026, 0.103853", \ "0.133327, 0.154566, 0.184787, 0.200938, 0.231736", \ "0.225667, 0.24762, 0.288028, 0.31323, 0.372808"); } fall_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.034602, 0.063, 0.0921, 0.1152, 0.1704", \ "0.048178, 0.075, 0.1044, 0.1269, 0.1893", \ "0.0657, 0.0882, 0.1206, 0.144, 0.2166", \ "0.1443, 0.1536, 0.1872, 0.2148, 0.2985", \ "0.2649, 0.2667, 0.2892, 0.3153, 0.4038"); } cell_rise(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.063545, 0.094871, 0.136401, 0.16142, 0.242981", \ "0.07483, 0.1105, 0.154295, 0.185845, 0.272672", \ "0.094749, 0.132305, 0.185895, 0.218339, 0.313591", \ "0.169409, 0.208046, 0.283047, 0.327487, 0.447253", \ "0.281497, 0.318212, 0.398529, 0.457162, 0.610092"); } rise_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.052268, 0.0828, 0.1041, 0.1233, 0.1653", \ "0.070018, 0.0924, 0.1254, 0.1383, 0.192", \ "0.0909, 0.1095, 0.1491, 0.1689, 0.2271", \ "0.195, 0.2016, 0.2415, 0.273, 0.3516", \ "0.3492, 0.3501, 0.3723, 0.4038, 0.5091"); } } timing() { related_pin : "D"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.042736, 0.053327, 0.064886, 0.066692, 0.066033", \ "0.054666, 0.069528, 0.085321, 0.092299, 0.100861", \ "0.070329, 0.094855, 0.118569, 0.128733, 0.148953", \ "0.133457, 0.165786, 0.215247, 0.238769, 0.290855", \ "0.227208, 0.258062, 0.324137, 0.363734, 0.449975"); } fall_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.036357, 0.0663, 0.0963, 0.1182, 0.1797", \ "0.049069, 0.0738, 0.117, 0.1359, 0.2046", \ "0.0672, 0.0945, 0.1338, 0.1596, 0.2355", \ "0.1443, 0.1563, 0.2049, 0.2382, 0.3345", \ "0.2649, 0.2661, 0.3012, 0.3399, 0.4542"); } cell_rise(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.055133, 0.083033, 0.112962, 0.137088, 0.19711", \ "0.066932, 0.099166, 0.13773, 0.161212, 0.231136", \ "0.087392, 0.123134, 0.169512, 0.198112, 0.27848", \ "0.163047, 0.200404, 0.272061, 0.313522, 0.422928", \ "0.275586, 0.31125, 0.390389, 0.44751, 0.592551"); } rise_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.045942, 0.0738, 0.1017, 0.1119, 0.1644", \ "0.059367, 0.0882, 0.1167, 0.1338, 0.189", \ "0.0834, 0.105, 0.1437, 0.165, 0.2268", \ "0.1872, 0.1923, 0.2361, 0.2679, 0.3495", \ "0.3417, 0.3423, 0.3654, 0.3975, 0.5052"); } } internal_power() { related_pin : "A"; fall_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.017252, 0.014504, 0.002012, 0.017593, 0.073678", \ "0.016991, 0.014085, 0.001121, 0.015296, 0.070035", \ "0.01643, 0.014244, 0.001354, 0.012311, 0.064843", \ "0.01571, 0.014909, 0.00564, 0.00501, 0.050029", \ "0.015323, 0.015251, 0.008357, 0.001706, 0.036823"); } rise_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.115446, 0.116135, 0.129847, 0.144513, 0.201731", \ "0.116415, 0.116075, 0.128039, 0.142387, 0.198152", \ "0.116086, 0.116647, 0.126483, 0.139869, 0.193572", \ "0.116179, 0.116861, 0.123363, 0.133721, 0.179649", \ "0.116614, 0.115892, 0.121362, 0.129414, 0.167706"); } } internal_power() { related_pin : "B"; fall_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.016981, 0.012866, 0.003748, 0.018859, 0.072511", \ "0.016622, 0.013066, 0.002135, 0.016484, 0.069066", \ "0.016337, 0.01353, 0.001276, 0.013404, 0.064006", \ "0.015625, 0.014455, 0.00495, 0.005528, 0.049308", \ "0.015302, 0.014761, 0.008174, 0.001762, 0.036019"); } rise_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.103614, 0.103917, 0.116687, 0.130781, 0.184576", \ "0.104035, 0.104344, 0.115506, 0.128643, 0.180928", \ "0.104894, 0.104706, 0.113914, 0.126271, 0.175692", \ "0.106145, 0.105647, 0.111102, 0.120551, 0.162396", \ "0.107214, 0.105361, 0.109731, 0.116971, 0.151643"); } } internal_power() { related_pin : "C"; fall_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.019796, 0.015099, 0.002586, 0.017576, 0.070439", \ "0.018534, 0.015991, 0.000882, 0.014832, 0.066302", \ "0.017084, 0.016253, 0.00167, 0.011388, 0.060581", \ "0.014548, 0.015105, 0.005856, 0.004036, 0.0455", \ "0.013335, 0.01384, 0.007841, 0.000506, 0.033248"); } rise_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.079176, 0.085628, 0.10238, 0.116879, 0.166948", \ "0.079246, 0.084479, 0.100338, 0.114328, 0.163665", \ "0.079457, 0.083914, 0.097961, 0.111276, 0.159308", \ "0.080706, 0.081878, 0.092798, 0.10383, 0.146816", \ "0.081347, 0.081968, 0.089357, 0.097961, 0.134919"); } } internal_power() { related_pin : "D"; fall_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.018921, 0.013487, 0.004758, 0.019294, 0.070418", \ "0.018072, 0.013734, 0.002565, 0.016448, 0.066247", \ "0.016721, 0.013837, 0.000845, 0.012859, 0.060584", \ "0.01445, 0.014048, 0.005005, 0.004885, 0.045461", \ "0.013184, 0.013269, 0.007554, 0.000456, 0.033016"); } rise_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.067102, 0.073574, 0.089864, 0.103549, 0.151461", \ "0.067404, 0.073003, 0.087748, 0.101072, 0.147805", \ "0.068244, 0.072128, 0.08545, 0.0979, 0.143101", \ "0.070645, 0.070678, 0.080594, 0.090759, 0.130749", \ "0.07195, 0.071514, 0.077661, 0.085554, 0.119758"); } } } } /* -------------- * * Design : BUFX2 * * -------------- */ cell (BUFX2) { cell_footprint : buf; area : 24; cell_leakage_power : 0.0660639; pin(A) { direction : input; capacitance : 0.00933171; rise_capacitance : 0.00930577; fall_capacitance : 0.00933171; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.975984; function : "A"; timing() { related_pin : "A"; timing_sense : positive_unate; cell_rise(delay_template_5x5) { index_1 ("0.01, 0.025, 0.05, 0.15, 0.3"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.080192, 0.099332, 0.125551, 0.141601, 0.160879", \ "0.09527, 0.119121, 0.146424, 0.159624, 0.180791", \ "0.119549, 0.142384, 0.170285, 0.182826, 0.208459", \ "0.206725, 0.226318, 0.258778, 0.269216, 0.29682", \ "0.336459, 0.356012, 0.387945, 0.399852, 0.425204"); } rise_transition(delay_template_5x5) { index_1 ("0.01, 0.025, 0.05, 0.15, 0.3"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.035642, 0.045563, 0.054071, 0.057308, 0.0714", \ "0.050072, 0.056113, 0.0636, 0.0738, 0.0786", \ "0.075, 0.084, 0.087, 0.0894, 0.1002", \ "0.1932, 0.1938, 0.1956, 0.198, 0.2046", \ "0.378, 0.378, 0.378, 0.3792, 0.3816"); } cell_fall(delay_template_5x5) { index_1 ("0.01, 0.025, 0.05, 0.15, 0.3"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.089994, 0.120328, 0.164981, 0.192952, 0.273426", \ "0.105036, 0.137433, 0.18812, 0.215291, 0.293841", \ "0.126393, 0.161711, 0.209388, 0.240117, 0.319216", \ "0.207389, 0.241744, 0.292741, 0.321104, 0.405447", \ "0.326255, 0.363651, 0.411543, 0.440746, 0.523808"); } fall_transition(delay_template_5x5) { index_1 ("0.01, 0.025, 0.05, 0.15, 0.3"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.039104, 0.036002, 0.057053, 0.0624, 0.0708", \ "0.045857, 0.047088, 0.0684, 0.0702, 0.0768", \ "0.0726, 0.0744, 0.0786, 0.084, 0.0972", \ "0.165, 0.1656, 0.1668, 0.1692, 0.1764", \ "0.315, 0.3156, 0.3168, 0.3162, 0.3198"); } } internal_power() { related_pin : "A"; rise_power(energy_template_5x5) { index_1 ("0.01, 0.025, 0.05, 0.15, 0.3"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.03658, 0.03891, 0.056883, 0.069415, 0.11089", \ "0.038085, 0.039057, 0.055117, 0.067529, 0.106812", \ "0.038003, 0.039633, 0.053668, 0.064651, 0.102782", \ "0.0397, 0.044023, 0.054656, 0.064068, 0.099339", \ "0.040525, 0.044916, 0.055363, 0.064444, 0.098589"); } fall_power(energy_template_5x5) { index_1 ("0.01, 0.025, 0.05, 0.15, 0.3"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.065076, 0.073013, 0.086097, 0.096905, 0.139646", \ "0.064781, 0.072449, 0.084139, 0.093176, 0.13361", \ "0.066108, 0.072526, 0.082909, 0.094136, 0.129964", \ "0.06771, 0.073062, 0.083144, 0.093032, 0.127476", \ "0.068291, 0.073042, 0.083768, 0.092995, 0.127196"); } } } } /* -------------- * * Design : BUFX4 * * -------------- */ cell (BUFX4) { cell_footprint : buf; area : 32; cell_leakage_power : 0.112874; pin(A) { direction : input; capacitance : 0.0139855; rise_capacitance : 0.0139855; fall_capacitance : 0.013977; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 1.95039; function : "A"; timing() { related_pin : "A"; timing_sense : positive_unate; cell_rise(delay_template_5x5) { index_1 ("0.02, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.094477, 0.118917, 0.151175, 0.170545, 0.198697", \ "0.108268, 0.136412, 0.17212, 0.189943, 0.218536", \ "0.131873, 0.161346, 0.197906, 0.213426, 0.248242", \ "0.219765, 0.24781, 0.283692, 0.300935, 0.338057", \ "0.352268, 0.380624, 0.412859, 0.429202, 0.465845"); } rise_transition(delay_template_5x5) { index_1 ("0.02, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.046281, 0.039491, 0.057229, 0.058188, 0.0714", \ "0.050589, 0.052795, 0.066, 0.0762, 0.0876", \ "0.0804, 0.0822, 0.0924, 0.096, 0.111", \ "0.1968, 0.195, 0.1986, 0.2004, 0.2088", \ "0.378, 0.3786, 0.3798, 0.3798, 0.3834"); } cell_fall(delay_template_5x5) { index_1 ("0.02, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.096657, 0.137402, 0.190461, 0.220804, 0.300489", \ "0.114807, 0.156287, 0.204939, 0.239659, 0.321534", \ "0.138395, 0.179398, 0.231548, 0.262645, 0.349399", \ "0.220463, 0.261654, 0.314512, 0.347774, 0.436449", \ "0.34088, 0.380615, 0.434973, 0.466641, 0.554835"); } fall_transition(delay_template_5x5) { index_1 ("0.02, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.042949, 0.037058, 0.05589, 0.056171, 0.0708", \ "0.05743, 0.0612, 0.0678, 0.0732, 0.0834", \ "0.0774, 0.0786, 0.0834, 0.0924, 0.1044", \ "0.1668, 0.1686, 0.1686, 0.1728, 0.1818", \ "0.3168, 0.3168, 0.3174, 0.3192, 0.3228"); } } internal_power() { related_pin : "A"; rise_power(energy_template_5x5) { index_1 ("0.02, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.079355, 0.092501, 0.114694, 0.133098, 0.19854", \ "0.08082, 0.089804, 0.108722, 0.12801, 0.185272", \ "0.081934, 0.089236, 0.106385, 0.124121, 0.177529", \ "0.085841, 0.089194, 0.104203, 0.115974, 0.170571", \ "0.086429, 0.090348, 0.104476, 0.116805, 0.167856"); } fall_power(energy_template_5x5) { index_1 ("0.02, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.113213, 0.128563, 0.154335, 0.175638, 0.240473", \ "0.118931, 0.129253, 0.143695, 0.166165, 0.225257", \ "0.120815, 0.128692, 0.144521, 0.161484, 0.21689", \ "0.123609, 0.128749, 0.144859, 0.158581, 0.208574", \ "0.123005, 0.130448, 0.145475, 0.15896, 0.207448"); } } } } /* ---------------- * * Design : CLKBUF1 * * ---------------- */ cell (CLKBUF1) { cell_footprint : buf; area : 72; cell_leakage_power : 0.352221; pin(A) { direction : input; capacitance : 0.0373913; rise_capacitance : 0.0373913; fall_capacitance : 0.0373758; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 1.95928; function : "A"; timing() { related_pin : "A"; timing_sense : positive_unate; cell_rise(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.168143, 0.183015, 0.204676, 0.218411, 0.224292, 0.227969", \ "0.340692, 0.35709, 0.379018, 0.392042, 0.404133, 0.411802", \ "0.642727, 0.659179, 0.681041, 0.704111, 0.705919, 0.713961", \ "1.41986, 1.43638, 1.45833, 1.48108, 1.48603, 1.49136", \ "1.85216, 1.86801, 1.88929, 1.9131, 1.91767, 1.92258", \ "2.28372, 2.30018, 2.32154, 2.34438, 2.34984, 2.35428"); } rise_transition(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.0768, 0.072, 0.0738, 0.0762, 0.0744, 0.0768", \ "0.3156, 0.3156, 0.315, 0.315, 0.3156, 0.3156", \ "0.7452, 0.7452, 0.744, 0.7452, 0.7452, 0.7446", \ "1.8504, 1.8504, 1.8504, 1.851, 1.8504, 1.851", \ "2.466, 2.4654, 2.466, 2.4666, 2.4648, 2.466", \ "3.0804, 3.081, 3.0798, 3.0798, 3.0804, 3.0804"); } cell_fall(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.171898, 0.209013, 0.238962, 0.289989, 0.323338, 0.374155", \ "0.330297, 0.368254, 0.398808, 0.448915, 0.482008, 0.538509", \ "0.606906, 0.645017, 0.675653, 0.725812, 0.758901, 0.815565", \ "1.31873, 1.35685, 1.38712, 1.43771, 1.47029, 1.52749", \ "1.71431, 1.75246, 1.78241, 1.83326, 1.86622, 1.92306", \ "2.10966, 2.14763, 2.17812, 2.22879, 2.26112, 2.31861"); } fall_transition(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.0648, 0.063, 0.0666, 0.0684, 0.0618, 0.0684", \ "0.2616, 0.2616, 0.2628, 0.2628, 0.2628, 0.2628", \ "0.6168, 0.6168, 0.6162, 0.6168, 0.6168, 0.6168", \ "1.5312, 1.53, 1.5306, 1.5312, 1.5312, 1.5306", \ "2.0394, 2.0394, 2.0382, 2.0394, 2.0394, 2.0388", \ "2.5476, 2.5476, 2.5464, 2.5476, 2.5458, 2.5476"); } } internal_power() { related_pin : "A"; rise_power(energy_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.230035, 0.255216, 0.321324, 0.420025, 0.492297, 0.633715", \ "0.234501, 0.258663, 0.327011, 0.423913, 0.490504, 0.638684", \ "0.235402, 0.259609, 0.328388, 0.412522, 0.491125, 0.64063", \ "0.234015, 0.260022, 0.328987, 0.41302, 0.488217, 0.641615", \ "0.233949, 0.26015, 0.32931, 0.41342, 0.48807, 0.64199", \ "0.23428, 0.26007, 0.32922, 0.413416, 0.488471, 0.642"); } fall_power(energy_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.353671, 0.385256, 0.429396, 0.538556, 0.609563, 0.759305", \ "0.35517, 0.38778, 0.431764, 0.541422, 0.612262, 0.761955", \ "0.355302, 0.388239, 0.432452, 0.541993, 0.613065, 0.763151", \ "0.355385, 0.388522, 0.432782, 0.542278, 0.613428, 0.763567", \ "0.355551, 0.388693, 0.433049, 0.542469, 0.613581, 0.763856", \ "0.3556, 0.388816, 0.432977, 0.542237, 0.61366, 0.763712"); } } } } /* ---------------- * * Design : CLKBUF2 * * ---------------- */ cell (CLKBUF2) { cell_footprint : buf; area : 104; cell_leakage_power : 0.548764; pin(A) { direction : input; capacitance : 0.037409; rise_capacitance : 0.037409; fall_capacitance : 0.0373773; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 1.96195; function : "A"; timing() { related_pin : "A"; timing_sense : positive_unate; cell_rise(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.231101, 0.25098, 0.270172, 0.286134, 0.291134, 0.293352", \ "0.407523, 0.424195, 0.441497, 0.457232, 0.464429, 0.467226", \ "0.709412, 0.726144, 0.743538, 0.759384, 0.766413, 0.772549", \ "1.48587, 1.50277, 1.52051, 1.53634, 1.54292, 1.54911", \ "1.9178, 1.93426, 1.95217, 1.96797, 1.97524, 1.98152", \ "2.34982, 2.36644, 2.38381, 2.40013, 2.40661, 2.41316"); } rise_transition(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.0756, 0.072, 0.072, 0.0738, 0.0726, 0.0726", \ "0.3144, 0.3156, 0.3156, 0.3156, 0.3156, 0.3156", \ "0.7446, 0.7446, 0.7446, 0.7452, 0.7446, 0.7446", \ "1.8498, 1.8504, 1.851, 1.8504, 1.8504, 1.8504", \ "2.4648, 2.466, 2.466, 2.4654, 2.4654, 2.4654", \ "3.0798, 3.0804, 3.0798, 3.081, 3.0804, 3.0792"); } cell_fall(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.237151, 0.273513, 0.303669, 0.357429, 0.38715, 0.439064", \ "0.395538, 0.432664, 0.462126, 0.516443, 0.546053, 0.597581", \ "0.672499, 0.712585, 0.739108, 0.79317, 0.822941, 0.874386", \ "1.38386, 1.42405, 1.45077, 1.50516, 1.53467, 1.58634", \ "1.77945, 1.81979, 1.84606, 1.9007, 1.93037, 1.98171", \ "2.17547, 2.21509, 2.24142, 2.29593, 2.32564, 2.37648"); } fall_transition(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.0624, 0.0678, 0.0654, 0.0618, 0.0666, 0.0642", \ "0.2622, 0.2622, 0.2616, 0.2628, 0.2628, 0.2628", \ "0.6168, 0.6168, 0.6168, 0.6168, 0.6162, 0.6168", \ "1.5312, 1.5306, 1.5306, 1.5312, 1.5306, 1.53", \ "2.0388, 2.0388, 2.0376, 2.0388, 2.0388, 2.0382", \ "2.5476, 2.5464, 2.5458, 2.5476, 2.5482, 2.5464"); } } internal_power() { related_pin : "A"; rise_power(energy_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.407535, 0.42745, 0.493283, 0.589349, 0.665537, 0.813485", \ "0.416735, 0.433198, 0.504101, 0.601088, 0.66997, 0.818487", \ "0.417986, 0.434291, 0.505001, 0.601282, 0.670891, 0.80778", \ "0.418682, 0.434887, 0.505709, 0.60217, 0.671759, 0.808482", \ "0.418933, 0.434931, 0.505977, 0.602236, 0.671561, 0.80855", \ "0.4189, 0.435265, 0.505945, 0.602361, 0.671877, 0.808502"); } fall_power(energy_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.528849, 0.563066, 0.602892, 0.706677, 0.780092, 0.934708", \ "0.532688, 0.567377, 0.606397, 0.71032, 0.783573, 0.937407", \ "0.533324, 0.559561, 0.606931, 0.711026, 0.784325, 0.937969", \ "0.533553, 0.560266, 0.607245, 0.711439, 0.784616, 0.938267", \ "0.533579, 0.560528, 0.6074, 0.711702, 0.784756, 0.938157", \ "0.533815, 0.559945, 0.607495, 0.711832, 0.784615, 0.938139"); } } } } /* ---------------- * * Design : CLKBUF3 * * ---------------- */ cell (CLKBUF3) { cell_footprint : buf; area : 136; cell_leakage_power : 0.745304; pin(A) { direction : input; capacitance : 0.0373938; rise_capacitance : 0.0373938; fall_capacitance : 0.0373674; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 1.96085; function : "A"; timing() { related_pin : "A"; timing_sense : positive_unate; cell_rise(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.294709, 0.31169, 0.33559, 0.351998, 0.355536, 0.360151", \ "0.476517, 0.48564, 0.50671, 0.522794, 0.529119, 0.533172", \ "0.778644, 0.787463, 0.808733, 0.824881, 0.831107, 0.835158", \ "1.55587, 1.56467, 1.58567, 1.60104, 1.60814, 1.61162", \ "1.98756, 1.99562, 2.01749, 2.03278, 2.03978, 2.04388", \ "2.41922, 2.42762, 2.44964, 2.46398, 2.47131, 2.47588"); } rise_transition(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.0762, 0.0738, 0.0738, 0.0738, 0.0762, 0.0744", \ "0.3156, 0.3144, 0.3156, 0.315, 0.3156, 0.3162", \ "0.7446, 0.7446, 0.7452, 0.7446, 0.744, 0.7446", \ "1.851, 1.8504, 1.8504, 1.8498, 1.8504, 1.8504", \ "2.466, 2.466, 2.4654, 2.466, 2.4654, 2.466", \ "3.0804, 3.081, 3.081, 3.0804, 3.0804, 3.0804"); } cell_fall(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.301525, 0.339234, 0.3677, 0.420709, 0.45207, 0.503376", \ "0.460268, 0.497618, 0.526095, 0.579533, 0.610902, 0.661892", \ "0.737156, 0.774426, 0.802781, 0.856206, 0.887576, 0.938553", \ "1.44891, 1.48629, 1.51461, 1.56821, 1.59963, 1.65006", \ "1.84423, 1.88188, 1.90953, 1.96378, 1.99519, 2.04617", \ "2.23985, 2.27754, 2.3052, 2.35909, 2.39074, 2.44139"); } fall_transition(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.0648, 0.0648, 0.0606, 0.0666, 0.0666, 0.0624", \ "0.2622, 0.2616, 0.2628, 0.2622, 0.2622, 0.2622", \ "0.6168, 0.6168, 0.6168, 0.6168, 0.6168, 0.6168", \ "1.53, 1.5312, 1.5306, 1.5312, 1.5312, 1.5306", \ "2.0388, 2.0394, 2.0388, 2.0388, 2.0388, 2.0388", \ "2.5464, 2.5476, 2.5458, 2.5482, 2.5476, 2.5476"); } } internal_power() { related_pin : "A"; rise_power(energy_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.584981, 0.606793, 0.669461, 0.761461, 0.842257, 0.980551", \ "0.577744, 0.611346, 0.681401, 0.773839, 0.845194, 0.985074", \ "0.579438, 0.612296, 0.681589, 0.774684, 0.846157, 0.985993", \ "0.580153, 0.612788, 0.683058, 0.77515, 0.846696, 0.986721", \ "0.580353, 0.613088, 0.683115, 0.775092, 0.84689, 0.986983", \ "0.580756, 0.612984, 0.683275, 0.775178, 0.846676, 0.987227"); } fall_power(energy_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.704098, 0.731354, 0.778711, 0.879269, 0.954459, 1.11027", \ "0.705941, 0.735162, 0.782427, 0.882782, 0.957859, 1.11224", \ "0.706445, 0.735857, 0.783021, 0.88338, 0.958398, 1.11296", \ "0.706452, 0.736107, 0.783299, 0.883745, 0.958796, 1.11318", \ "0.706528, 0.736197, 0.783541, 0.883923, 0.958804, 1.11305", \ "0.706534, 0.736049, 0.783693, 0.883944, 0.958701, 1.11345"); } } } } /* ----------------- * * Design : DFFNEGX1 * * ----------------- */ cell (DFFNEGX1) { area : 96; cell_leakage_power : 0.155885; ff (DS0000,P0002) { next_state : "D"; clocked_on : "(!CLK)"; } pin(CLK) { direction : input; capacitance : 0.0295634; rise_capacitance : 0.0293582; fall_capacitance : 0.0295634; clock : true; internal_power() { rise_power(passive_energy_template_6x1) { index_1 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ("0.037284, 0.04096, 0.059148, 0.107824, 0.1437, 0.218602"); } fall_power(passive_energy_template_6x1) { index_1 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ("0.086451, 0.105124, 0.131012, 0.175654, 0.209051, 0.277005"); } } min_pulse_width_high : 0.0939412; min_pulse_width_low : 0.104504; } pin(D) { direction : input; capacitance : 0.00890146; rise_capacitance : 0.00881587; fall_capacitance : 0.00890146; internal_power() { rise_power(passive_energy_template_5x1) { index_1 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ("0.030829, 0.032759, 0.042528, 0.055396, 0.083943"); } fall_power(passive_energy_template_5x1) { index_1 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ("0.097866, 0.100952, 0.108957, 0.117496, 0.148741"); } } timing() { related_pin : "CLK"; timing_type : hold_falling; rise_constraint(hold_template_3x5) { index_1 ("0.06, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0, -0.0875, -0.075, -0.1125, -0.08125", \ "-0.10625, -0.1, -0.0875, -0.125, -0.1875", \ "-0.16875, -0.1625, -0.15, -0.1875, -0.25"); } fall_constraint(hold_template_3x5) { index_1 ("0.06, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0, -0.0875, -0.075, -0.1125, -0.175", \ "-0.0125, -0.00625, -0.0875, -0.125, -0.1875", \ "0.01875, 0.025, -0.05625, -0.09375, -0.0625"); } } timing() { related_pin : "CLK"; timing_type : setup_falling; rise_constraint(setup_template_3x5) { index_1 ("0.06, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1875, 0.18125, 0.16875, 0.20625, 0.26875", \ "0.2, 0.19375, 0.18125, 0.21875, 0.28125", \ "0.2625, 0.44375, 0.24375, 0.28125, 0.71875"); } fall_constraint(setup_template_3x5) { index_1 ("0.06, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1875, 0.18125, 0.2625, 0.3, 0.3625", \ "0.2, 0.19375, 0.275, 0.21875, 0.375", \ "0.16875, 0.1625, 0.24375, 0.1875, 0.34375"); } } } pin(Q) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.992362; function : "DS0000"; timing() { related_pin : "CLK"; timing_sense : non_unate; timing_type : falling_edge; cell_rise(delay_template_5x6) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.127171, 0.157261, 0.193197, 0.242742, 0.272567, 0.320526", \ "0.138941, 0.168471, 0.203551, 0.253043, 0.281605, 0.331377", \ "0.152581, 0.183347, 0.217393, 0.266999, 0.293007, 0.344469", \ "0.202583, 0.230235, 0.266411, 0.316181, 0.341026, 0.393926", \ "0.268294, 0.296675, 0.332037, 0.382057, 0.409008, 0.460614"); } rise_transition(delay_template_5x6) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.035941, 0.036804, 0.041981, 0.042554, 0.039872, 0.044075", \ "0.047854, 0.048167, 0.048199, 0.048987, 0.049388, 0.059309", \ "0.057766, 0.0606, 0.0606, 0.0612, 0.063, 0.0624", \ "0.1194, 0.1182, 0.12, 0.1212, 0.12, 0.12", \ "0.2046, 0.2058, 0.204, 0.2058, 0.2058, 0.2064"); } cell_fall(delay_template_5x6) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.12194, 0.172988, 0.224116, 0.298592, 0.344721, 0.429327", \ "0.132048, 0.18302, 0.234315, 0.309127, 0.35693, 0.443335", \ "0.147217, 0.19846, 0.25123, 0.324558, 0.372696, 0.459914", \ "0.198327, 0.250554, 0.302789, 0.377794, 0.426431, 0.515884", \ "0.262685, 0.314083, 0.366272, 0.443553, 0.492671, 0.583101"); } fall_transition(delay_template_5x6) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.041908, 0.046796, 0.056173, 0.0744, 0.0762, 0.0888", \ "0.048334, 0.053789, 0.0618, 0.0792, 0.087, 0.0984", \ "0.0606, 0.066, 0.078, 0.084, 0.0942, 0.108", \ "0.1122, 0.1134, 0.12, 0.1314, 0.1374, 0.1476", \ "0.1794, 0.1812, 0.1878, 0.1932, 0.1974, 0.2064"); } } internal_power() { related_pin : "CLK"; rise_power(energy_template_5x6) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.146359, 0.162663, 0.190528, 0.240766, 0.277657, 0.349249", \ "0.146218, 0.162653, 0.191643, 0.241715, 0.277774, 0.348517", \ "0.146337, 0.162754, 0.191394, 0.240994, 0.276402, 0.34748", \ "0.146945, 0.163341, 0.19181, 0.241151, 0.277252, 0.346929", \ "0.148527, 0.163953, 0.193025, 0.242309, 0.277088, 0.347497"); } fall_power(energy_template_5x6) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.144274, 0.170803, 0.212085, 0.283695, 0.33617, 0.436977", \ "0.143072, 0.168248, 0.207577, 0.27871, 0.330148, 0.431632", \ "0.142643, 0.167591, 0.20368, 0.273148, 0.323676, 0.424924", \ "0.143936, 0.165886, 0.2005, 0.267703, 0.31655, 0.41505", \ "0.14445, 0.165176, 0.199606, 0.265547, 0.313716, 0.411094"); } } } } /* ----------------- * * Design : DFFPOSX1 * * ----------------- */ cell (DFFPOSX1) { area : 96; cell_leakage_power : 0.160725; ff (DS0000,P0002) { next_state : "D"; clocked_on : "CLK"; } pin(CLK) { direction : input; capacitance : 0.0279235; rise_capacitance : 0.0279235; fall_capacitance : 0.0274634; clock : true; internal_power() { rise_power(passive_energy_template_6x1) { index_1 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ("0.006865, 0.006943, 0.030508, 0.076138, 0.112244, 0.183321"); } fall_power(passive_energy_template_6x1) { index_1 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ("0.11034, 0.129769, 0.160216, 0.216283, 0.258089, 0.338194"); } } min_pulse_width_high : 0.106969; min_pulse_width_low : 0.09927; } pin(D) { direction : input; capacitance : 0.00882947; rise_capacitance : 0.00882947; fall_capacitance : 0.00881001; internal_power() { rise_power(passive_energy_template_5x1) { index_1 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ("0.045424, 0.045977, 0.055651, 0.063033, 0.096119"); } fall_power(passive_energy_template_5x1) { index_1 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ("0.08841, 0.087952, 0.097074, 0.107295, 0.139032"); } } timing() { related_pin : "CLK"; timing_type : hold_rising; rise_constraint(hold_template_3x5) { index_1 ("0.06, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0, 0.00625, -0.075, -0.01875, -0.08125", \ "-0.0125, -0.00625, 0.00625, -0.03125, 0", \ "0.01875, -0.06875, -0.05625, 0, -0.0625"); } fall_constraint(hold_template_3x5) { index_1 ("0.06, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "-0.09375, -0.0875, -0.075, -0.1125, -0.175", \ "-0.10625, -0.19375, -0.18125, -0.21875, -0.28125", \ "0.1125, 0.11875, -0.05625, -0.09375, -0.25"); } } timing() { related_pin : "CLK"; timing_type : setup_rising; rise_constraint(setup_template_3x5) { index_1 ("0.06, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1875, 0.18125, 0.16875, 0.20625, 0.26875", \ "0.2, 0.2875, 0.275, 0.3125, 0.28125", \ "0.45, 0.35, 0.3375, 0.46875, 0.53125"); } fall_constraint(setup_template_3x5) { index_1 ("0.06, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1875, 0.18125, 0.2625, 0.3, 0.3625", \ "0.29375, 0.2875, 0.275, 0.3125, 0.375", \ "0.91875, 0.35, 0.525, 0.65625, 0.4375"); } } } pin(Q) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.967534; function : "DS0000"; timing() { related_pin : "CLK"; timing_sense : non_unate; timing_type : rising_edge; cell_rise(delay_template_5x6) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.093526, 0.121034, 0.13421, 0.134398, 0.122773, 0.0926", \ "0.10403, 0.130762, 0.143181, 0.144557, 0.132377, 0.104697", \ "0.118023, 0.14606, 0.158231, 0.158041, 0.151991, 0.121227", \ "0.166235, 0.192972, 0.208222, 0.211247, 0.203428, 0.179357", \ "0.233467, 0.259728, 0.276539, 0.279342, 0.271987, 0.248208"); } rise_transition(delay_template_5x6) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.036088, 0.043386, 0.051719, 0.0678, 0.0702, 0.0774", \ "0.04409, 0.050885, 0.0606, 0.0762, 0.0762, 0.084", \ "0.057821, 0.0654, 0.0744, 0.0846, 0.096, 0.1026", \ "0.1182, 0.1224, 0.1284, 0.1368, 0.1398, 0.1476", \ "0.2052, 0.207, 0.2094, 0.216, 0.2208, 0.2286"); } cell_fall(delay_template_5x6) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.159821, 0.176886, 0.193318, 0.207708, 0.211849, 0.213209", \ "0.169871, 0.18774, 0.204315, 0.217111, 0.221269, 0.221151", \ "0.186934, 0.201494, 0.219369, 0.229968, 0.234471, 0.239765", \ "0.235597, 0.250463, 0.267087, 0.28101, 0.285745, 0.288909", \ "0.300793, 0.314188, 0.331092, 0.344623, 0.351457, 0.352857"); } fall_transition(delay_template_5x6) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.041962, 0.04207, 0.045013, 0.042772, 0.04261, 0.04369", \ "0.052151, 0.051175, 0.049987, 0.050183, 0.052505, 0.051007", \ "0.066, 0.0624, 0.0654, 0.0636, 0.0618, 0.0678", \ "0.1086, 0.1086, 0.1068, 0.1098, 0.108, 0.1116", \ "0.1794, 0.18, 0.1788, 0.1812, 0.1812, 0.1824"); } } internal_power() { related_pin : "CLK"; rise_power(energy_template_5x6) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.040752, 0.06407, 0.099137, 0.162883, 0.207764, 0.296269", \ "0.041217, 0.062027, 0.097688, 0.158665, 0.203554, 0.289681", \ "0.04099, 0.061849, 0.09519, 0.156194, 0.200043, 0.285303", \ "0.043452, 0.061538, 0.092194, 0.152786, 0.194912, 0.280997", \ "0.044433, 0.06208, 0.091836, 0.150899, 0.194246, 0.279888"); } fall_power(energy_template_5x6) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.064773, 0.076646, 0.104009, 0.152643, 0.185108, 0.255024", \ "0.063395, 0.075613, 0.102582, 0.150636, 0.183907, 0.254132", \ "0.060938, 0.076343, 0.099156, 0.149918, 0.183611, 0.25348", \ "0.062326, 0.075376, 0.099814, 0.149755, 0.183003, 0.253934", \ "0.062787, 0.07564, 0.100256, 0.149373, 0.182383, 0.253656"); } } } } /* -------------- * * Design : DFFSR * * -------------- */ cell (DFFSR) { area : 176; cell_leakage_power : 0.27727; ff (P0002,P0003) { next_state : "D"; clocked_on : "CLK"; clear : "(!R)"; preset : "(!S)"; clear_preset_var1 : L; } pin(CLK) { direction : input; capacitance : 0.00937511; rise_capacitance : 0.00932314; fall_capacitance : 0.00937511; clock : true; internal_power() { rise_power(passive_energy_template_6x1) { index_1 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ("0.041704, 0.046706, 0.061572, 0.084344, 0.106433, 0.145893"); } fall_power(passive_energy_template_6x1) { index_1 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ("0.123008, 0.130168, 0.141509, 0.16925, 0.188732, 0.226953"); } } min_pulse_width_high : 0.283301; min_pulse_width_low : 0.205581; } pin(D) { direction : input; capacitance : 0.00940895; rise_capacitance : 0.00940895; fall_capacitance : 0.00932956; internal_power() { rise_power(passive_energy_template_6x1) { index_1 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ("0.088283, 0.087505, 0.100628, 0.129385, 0.145716, 0.182119"); } fall_power(passive_energy_template_6x1) { index_1 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ("0.117272, 0.124444, 0.14019, 0.164994, 0.182539, 0.221408"); } } timing() { related_pin : "CLK"; timing_type : hold_rising; when : "S&R"; sdf_cond : "S\&R"; rise_constraint(hold_template_3x6) { index_1 ("0.06, 0.3, 0.6"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0, -0.0375, -0.025, -0.05, -0.08125, -0.05", \ "-0.0125, -0.05, -0.0375, -0.0625, -0.09375, -0.0625", \ "0.01875, -0.01875, -0.00625, -0.03125, -0.0625, -0.125"); } fall_constraint(hold_template_3x6) { index_1 ("0.06, 0.3, 0.6"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0, -0.0375, -0.025, -0.14375, -0.175, -0.2375", \ "0.08125, 0.04375, -0.0375, -0.0625, -0.09375, -0.15625", \ "0.1125, 0.075, -0.00625, -0.03125, -0.0625, -0.21875"); } } timing() { related_pin : "CLK"; timing_type : setup_rising; when : "S&R"; sdf_cond : "S\&R"; rise_constraint(setup_template_3x6) { index_1 ("0.06, 0.3, 0.6"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.09375, 0.13125, 0.2125, 0.2375, 0.175, 0.2375", \ "0.10625, 0.14375, 0.13125, 0.15625, 0.1875, 0.15625", \ "0.075, 0.1125, 0.1, 0.125, 0.15625, 0.21875"); } fall_constraint(setup_template_3x6) { index_1 ("0.06, 0.3, 0.6"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.09375, 0.13125, 0.2125, 0.2375, 0.26875, 0.33125", \ "0.10625, 0.14375, 0.13125, 0.25, 0.28125, 0.34375", \ "0.075, 0.1125, 0.19375, 0.21875, 0.25, 0.3125"); } } } pin(Q) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.468113; function : "P0002"; timing() { related_pin : "CLK"; timing_sense : non_unate; timing_type : rising_edge; cell_rise(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.387715, 0.4242, 0.449241, 0.479863, 0.493378, 0.510336", \ "1.0593, 1.0961, 1.12132, 1.15077, 1.16518, 1.18191", \ "2.23385, 2.27146, 2.29657, 2.32582, 2.33969, 2.35696", \ "5.2553, 5.2922, 5.31832, 5.34803, 5.36054, 5.37695", \ "6.93294, 6.96936, 6.99478, 7.02496, 7.04016, 7.05535", \ "8.61201, 8.64857, 8.67436, 8.70236, 8.71621, 8.73283"); } rise_transition(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.249, 0.249, 0.249, 0.249, 0.2478, 0.249", \ "1.2018, 1.2, 1.2024, 1.2006, 1.2018, 1.2006", \ "2.8728, 2.874, 2.8734, 2.8734, 2.8728, 2.874", \ "7.1718, 7.1718, 7.1724, 7.1712, 7.1724, 7.1724", \ "9.5604, 9.5604, 9.561, 9.5604, 9.5604, 9.561", \ "11.949, 11.949, 11.9484, 11.949, 11.9496, 11.949"); } cell_fall(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.381095, 0.414212, 0.432258, 0.455285, 0.464189, 0.473544", \ "0.969567, 1.00258, 1.02077, 1.04374, 1.05286, 1.06194", \ "1.99852, 2.03201, 2.05037, 2.07286, 2.0826, 2.09148", \ "4.64736, 4.68053, 4.69836, 4.72175, 4.73048, 4.74011", \ "6.11846, 6.15174, 6.16849, 6.19271, 6.2017, 6.20769", \ "7.5897, 7.62114, 7.63829, 7.66214, 7.67262, 7.67916"); } fall_transition(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.1992, 0.1998, 0.1992, 0.1998, 0.1992, 0.198", \ "0.9498, 0.9498, 0.9498, 0.9492, 0.9492, 0.9498", \ "2.271, 2.271, 2.2704, 2.271, 2.271, 2.2698", \ "5.6688, 5.6682, 5.6682, 5.6676, 5.6682, 5.6682", \ "7.5552, 7.5546, 7.5522, 7.5546, 7.5552, 7.5492", \ "9.4416, 9.441, 9.438, 9.441, 9.4416, 9.438"); } } timing() { related_pin : "R"; timing_sense : positive_unate; timing_type : clear; cell_rise(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.255245, 0.267211, 0.272748, 0.270558, 0.263299, 0.239588", \ "0.927233, 0.939028, 0.945323, 0.943953, 0.937484, 0.91901", \ "2.10242, 2.11391, 2.1206, 2.1188, 2.11337, 2.09441", \ "5.1226, 5.13558, 5.14239, 5.14108, 5.13447, 5.11702", \ "6.8014, 6.81238, 6.8206, 6.82046, 6.81426, 6.7949", \ "8.48041, 8.48981, 8.49679, 8.49628, 8.49257, 8.47179"); } rise_transition(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.2484, 0.2472, 0.2484, 0.2532, 0.2574, 0.2652", \ "1.2, 1.2006, 1.2012, 1.2018, 1.2024, 1.2048", \ "2.8746, 2.874, 2.874, 2.874, 2.874, 2.8722", \ "7.1724, 7.1712, 7.1724, 7.1724, 7.1718, 7.1724", \ "9.5604, 9.561, 9.5598, 9.5586, 9.5574, 9.5604", \ "11.9484, 11.949, 11.949, 11.9496, 11.949, 11.9496"); } cell_fall(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.262875, 0.324685, 0.387813, 0.478452, 0.536493, 0.645793", \ "0.851442, 0.913295, 0.975835, 1.06676, 1.12496, 1.23348", \ "1.88088, 1.94277, 2.00526, 2.09652, 2.15413, 2.26351", \ "4.52922, 4.59101, 4.65322, 4.74343, 4.80087, 4.91083", \ "6.00047, 6.06223, 6.12484, 6.2146, 6.27193, 6.38037", \ "7.47138, 7.53306, 7.59593, 7.68652, 7.74417, 7.85151"); } fall_transition(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.1992, 0.2007, 0.2013, 0.2028, 0.204, 0.2052", \ "0.9486, 0.9489, 0.9492, 0.9501, 0.9504, 0.951", \ "2.2698, 2.2707, 2.2698, 2.2698, 2.2704, 2.2704", \ "5.6664, 5.6679, 5.6652, 5.667, 5.6652, 5.6649", \ "7.5516, 7.5534, 7.5534, 7.5525, 7.5498, 7.5498", \ "9.4386, 9.4419, 9.4413, 9.4419, 9.4392, 9.4386"); } } timing() { related_pin : "S"; timing_sense : negative_unate; timing_type : preset; cell_rise(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.344773, 0.399864, 0.446316, 0.525767, 0.573992, 0.666461", \ "1.01865, 1.07188, 1.1183, 1.19933, 1.24819, 1.33808", \ "2.19343, 2.24681, 2.29288, 2.37423, 2.42321, 2.51328", \ "5.21504, 5.26772, 5.31423, 5.39634, 5.44478, 5.53429", \ "6.89381, 6.94555, 6.99241, 7.0739, 7.12265, 7.21244", \ "8.57089, 8.62568, 8.67173, 8.75022, 8.80049, 8.88991"); } rise_transition(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.2481, 0.2487, 0.2484, 0.2484, 0.2487, 0.2484", \ "1.2021, 1.2012, 1.2015, 1.2018, 1.2015, 1.2012", \ "2.8728, 2.8737, 2.8725, 2.8728, 2.8734, 2.8734", \ "7.1712, 7.1721, 7.1721, 7.1718, 7.1721, 7.1718", \ "9.5598, 9.5607, 9.5604, 9.5604, 9.5601, 9.5604", \ "11.9493, 11.9487, 11.949, 11.949, 11.9493, 11.949"); } } internal_power() { related_pin : "CLK"; rise_power(energy_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.151048, 0.158622, 0.171511, 0.198768, 0.218728, 0.261211", \ "0.151825, 0.159701, 0.172467, 0.200096, 0.219924, 0.261879", \ "0.15194, 0.160143, 0.172798, 0.200608, 0.220285, 0.262227", \ "0.151944, 0.160856, 0.173235, 0.201487, 0.221175, 0.262197", \ "0.152164, 0.161005, 0.173711, 0.201586, 0.222216, 0.26255", \ "0.15174, 0.161323, 0.173527, 0.201327, 0.220975, 0.263137"); } fall_power(energy_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.141227, 0.150979, 0.161428, 0.189053, 0.207561, 0.246194", \ "0.141671, 0.151133, 0.161697, 0.189503, 0.207945, 0.246892", \ "0.141959, 0.151299, 0.161897, 0.1897, 0.207945, 0.246928", \ "0.142566, 0.151503, 0.161463, 0.189777, 0.208281, 0.247071", \ "0.142479, 0.151289, 0.16179, 0.189948, 0.208155, 0.247255", \ "0.142818, 0.151617, 0.161884, 0.18964, 0.207948, 0.247395"); } } internal_power() { related_pin : "R"; rise_power(energy_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.045492, 0.062305, 0.088334, 0.143928, 0.185508, 0.269919", \ "0.046712, 0.063494, 0.089542, 0.145009, 0.186228, 0.269839", \ "0.047174, 0.063914, 0.089887, 0.145658, 0.186844, 0.270401", \ "0.047779, 0.064828, 0.090518, 0.146173, 0.187214, 0.271169", \ "0.048538, 0.064695, 0.090025, 0.14627, 0.188292, 0.270964", \ "0.049886, 0.064719, 0.090939, 0.145803, 0.187952, 0.271418"); } fall_power(energy_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.155704, 0.173754, 0.203811, 0.256892, 0.29055, 0.350772", \ "0.156347, 0.174395, 0.20423, 0.256484, 0.289596, 0.349078", \ "0.156642, 0.174668, 0.204576, 0.256703, 0.289826, 0.349161", \ "0.156902, 0.174751, 0.204971, 0.257079, 0.290016, 0.349805", \ "0.157086, 0.17465, 0.205296, 0.257578, 0.290391, 0.349282", \ "0.157219, 0.175227, 0.205143, 0.25757, 0.290435, 0.349746"); } } internal_power() { related_pin : "S"; power(energy_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.15628, 0.170156, 0.19269, 0.238568, 0.270569, 0.331301", \ "0.156928, 0.171426, 0.193829, 0.2389, 0.271492, 0.332601", \ "0.157284, 0.171847, 0.194132, 0.239121, 0.271853, 0.333062", \ "0.158082, 0.172581, 0.194372, 0.239638, 0.272424, 0.333474", \ "0.158841, 0.172592, 0.194391, 0.239616, 0.273092, 0.333673", \ "0.158095, 0.172153, 0.193866, 0.239884, 0.27239, 0.334038"); } } } pin(R) { direction : input; capacitance : 0.0255048; rise_capacitance : 0.0255048; fall_capacitance : 0.0220338; min_pulse_width_low : 0.152176; timing() { related_pin : "CLK"; timing_type : recovery_rising; when : "D&S"; sdf_cond : "D\&S"; rise_constraint(recovery_template_3x6) { index_1 ("0.06, 0.3, 0.6"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "-0.09375, -0.05625, 0.025, 0.05, 0.175, 0.33125", \ "-0.08125, -0.1375, -0.05625, -0.03125, 0, 0.25", \ "-0.1125, -0.16875, -0.0875, -0.0625, -0.03125, 0.125"); } } timing() { related_pin : "S"; timing_type : recovery_rising; rise_constraint(recovery_template_6x6) { index_1 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0, 0.05625, 0.06875, 0.04375, 0.10625, 0.1375", \ "0.0375, 0, 0.0125, 0.08125, 0.05, 0.128125", \ "0.025, 0.034375, 0, 0.06875, 0.084375, 0.115625", \ "0.003125, 0.0125, 0.025, 0.046875, 0.0625, 0.09375", \ "-0.0125, -0.003125, -0.0375, 0.03125, 0.046875, 0.078125", \ "-0.04375, -0.034375, -0.06875, 0, -0.03125, 0.046875"); } } timing() { related_pin : "CLK"; timing_type : removal_rising; when : "D&S"; sdf_cond : "D\&S"; rise_constraint(removal_template_3x6) { index_1 ("0.06, 0.3, 0.6"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.1875, 0.24375, 0.25625, 0.325, 0.3875, 0.41875", \ "0.26875, 0.23125, 0.24375, 0.3125, 0.375, 0.5", \ "0.3, 0.2625, 0.275, 0.34375, 0.40625, 0.4375"); } } } pin(S) { direction : input; capacitance : 0.0230606; rise_capacitance : 0.0141532; fall_capacitance : 0.0230606; internal_power() { rise_power(passive_energy_template_6x1) { index_1 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ("0.036159, 0.033603, 0.035396, 0.034302, 0.033581, 0.034303"); } fall_power(passive_energy_template_6x1) { index_1 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ("0, 0, 0, 0, 0, 0"); } } min_pulse_width_low : 0.199049; timing() { related_pin : "CLK"; timing_type : recovery_rising; when : "!D&R"; sdf_cond : "\~D\&R"; rise_constraint(recovery_template_3x6) { index_1 ("0.06, 0.3, 0.6"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0, 0.0375, 0.025, 0.14375, 0.08125, 0.2375", \ "0.0125, 0.05, 0.0375, 0.0625, 0.09375, 0.15625", \ "-0.01875, 0.01875, 0.00625, 0.03125, 0.0625, 0.21875"); } } timing() { related_pin : "R"; timing_type : recovery_rising; rise_constraint(recovery_template_6x6) { index_1 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.09375, 0.05625, 0.06875, 0.090625, 0.10625, 0.1375", \ "0.0375, 0.09375, 0.10625, 0.08125, 0.096875, 0.128125", \ "0.025, 0.08125, 0.09375, 0.06875, 0.084375, 0.1625", \ "0.05, 0.0125, 0.025, 0.046875, 0.0625, 0.09375", \ "0.034375, 0.04375, 0.009375, 0.03125, 0.046875, 0.125", \ "0.003125, -0.034375, -0.021875, 0, 0.015625, 0.046875"); } } timing() { related_pin : "CLK"; timing_type : removal_rising; when : "!D&R"; sdf_cond : "\~D\&R"; rise_constraint(removal_template_3x6) { index_1 ("0.06, 0.3, 0.6"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.09375, 0.05625, 0.06875, 0.04375, 0.10625, 0.04375", \ "0.175, 0.1375, 0.05625, 0.125, 0.09375, 0.125", \ "0.1125, 0.16875, 0.0875, 0.0625, 0.125, 0.15625"); } } } } /* ------------- * * Design : FAX1 * * ------------- */ cell (FAX1) { area : 120; cell_leakage_power : 0.230647; pin(A) { direction : input; capacitance : 0.0613054; rise_capacitance : 0.0606345; fall_capacitance : 0.0613054; } pin(B) { direction : input; capacitance : 0.05692; rise_capacitance : 0.05692; fall_capacitance : 0.0549316; } pin(C) { direction : input; capacitance : 0.0416003; rise_capacitance : 0.0416003; fall_capacitance : 0.04156; } pin(YC) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.497776; function : "(((A B)+(B C))+(C A))"; timing() { related_pin : "A"; timing_sense : positive_unate; cell_rise(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.110961, 0.128075, 0.1516, 0.167167, 0.190781", \ "0.130601, 0.147139, 0.171029, 0.186307, 0.212628", \ "0.154326, 0.172367, 0.200121, 0.213629, 0.243016", \ "0.244814, 0.262639, 0.291037, 0.305225, 0.339785", \ "0.372364, 0.389878, 0.418591, 0.432655, 0.468862"); } rise_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.034724, 0.036496, 0.040349, 0.05232, 0.05513", \ "0.05407, 0.054239, 0.058178, 0.0663, 0.0747", \ "0.0777, 0.0834, 0.0903, 0.0912, 0.1002", \ "0.1938, 0.1944, 0.1959, 0.1989, 0.2055", \ "0.3687, 0.369, 0.3705, 0.3714, 0.3747"); } cell_fall(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.133895, 0.155633, 0.191369, 0.2175, 0.293908", \ "0.152322, 0.174355, 0.212242, 0.238006, 0.316257", \ "0.177897, 0.200656, 0.239699, 0.266038, 0.34816", \ "0.263185, 0.285715, 0.327493, 0.355817, 0.442452", \ "0.375727, 0.398327, 0.440573, 0.470266, 0.558082"); } fall_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.039038, 0.038593, 0.050291, 0.051711, 0.061636", \ "0.052901, 0.050905, 0.0624, 0.061602, 0.0705", \ "0.0741, 0.0753, 0.0831, 0.0849, 0.0936", \ "0.1623, 0.1632, 0.1662, 0.1689, 0.1782", \ "0.2958, 0.2955, 0.2973, 0.2991, 0.303"); } } timing() { related_pin : "B"; timing_sense : positive_unate; cell_rise(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.11476, 0.135987, 0.16121, 0.173508, 0.200806", \ "0.133581, 0.154327, 0.181009, 0.194579, 0.222158", \ "0.159361, 0.180709, 0.209291, 0.223078, 0.25317", \ "0.249995, 0.271007, 0.30202, 0.316622, 0.350916", \ "0.377283, 0.398337, 0.43029, 0.445191, 0.480202"); } rise_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.038642, 0.039314, 0.045251, 0.043585, 0.058504", \ "0.052925, 0.054573, 0.0627, 0.0648, 0.0729", \ "0.0828, 0.0834, 0.0897, 0.0924, 0.1029", \ "0.195, 0.1956, 0.1992, 0.2007, 0.2079", \ "0.3693, 0.3684, 0.3711, 0.3729, 0.3762"); } cell_fall(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.134739, 0.162025, 0.20358, 0.230737, 0.313007", \ "0.153404, 0.181647, 0.223749, 0.253855, 0.339344", \ "0.180482, 0.208858, 0.251188, 0.283223, 0.369465", \ "0.267421, 0.295778, 0.342971, 0.375215, 0.465786", \ "0.380838, 0.409362, 0.458422, 0.491805, 0.583521"); } fall_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.044455, 0.036854, 0.041074, 0.047622, 0.056824", \ "0.052948, 0.053563, 0.05985, 0.063435, 0.0735", \ "0.078, 0.0804, 0.0834, 0.0906, 0.0966", \ "0.1638, 0.1659, 0.1713, 0.1746, 0.1815", \ "0.297, 0.2973, 0.3012, 0.3042, 0.3078"); } } timing() { related_pin : "C"; timing_sense : positive_unate; cell_rise(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.109702, 0.132682, 0.165136, 0.180248, 0.211225", \ "0.125675, 0.151973, 0.18654, 0.202286, 0.235363", \ "0.150952, 0.178149, 0.214452, 0.230656, 0.266633", \ "0.241765, 0.268351, 0.305137, 0.323826, 0.364625", \ "0.369534, 0.395458, 0.432847, 0.45156, 0.492283"); } rise_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.039084, 0.036944, 0.045434, 0.04891, 0.058904", \ "0.052615, 0.054065, 0.0651, 0.0708, 0.0816", \ "0.0798, 0.0807, 0.0933, 0.0957, 0.105", \ "0.1941, 0.1953, 0.1977, 0.2004, 0.2061", \ "0.369, 0.369, 0.3702, 0.3708, 0.3735"); } cell_fall(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.121862, 0.159349, 0.209459, 0.244319, 0.337679", \ "0.142508, 0.178687, 0.232523, 0.266623, 0.361761", \ "0.169443, 0.207156, 0.263743, 0.296007, 0.397463", \ "0.256454, 0.294002, 0.354327, 0.389602, 0.493712", \ "0.369994, 0.407462, 0.468873, 0.505373, 0.609741"); } fall_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.037254, 0.040396, 0.054151, 0.055881, 0.0714", \ "0.053461, 0.05241, 0.0633, 0.0687, 0.081", \ "0.075, 0.0774, 0.0861, 0.0894, 0.1032", \ "0.1662, 0.1653, 0.1716, 0.1731, 0.1815", \ "0.297, 0.2973, 0.2997, 0.3018, 0.3057"); } } internal_power() { related_pin : "A"; rise_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.007466, 0.006824, 0.019945, 0.030237, 0.060247", \ "0.007781, 0.009663, 0.019533, 0.028757, 0.058276", \ "0.009603, 0.01151, 0.02075, 0.028254, 0.057467", \ "0.011239, 0.012692, 0.020968, 0.028039, 0.056866", \ "0.011618, 0.012838, 0.020969, 0.028073, 0.056587"); } fall_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.137117, 0.137859, 0.147519, 0.1579, 0.188671", \ "0.139337, 0.139992, 0.146761, 0.155933, 0.187897", \ "0.140148, 0.140413, 0.148995, 0.155314, 0.186999", \ "0.140706, 0.141603, 0.149331, 0.156135, 0.186049", \ "0.141124, 0.14205, 0.149664, 0.156595, 0.186534"); } } internal_power() { related_pin : "B"; rise_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.020977, 0.016769, 0.028506, 0.037122, 0.06575", \ "0.021323, 0.021127, 0.027771, 0.037435, 0.064538", \ "0.02299, 0.02218, 0.028788, 0.036974, 0.06455", \ "0.024243, 0.02359, 0.029653, 0.036487, 0.063384", \ "0.024575, 0.024024, 0.029942, 0.036647, 0.062954"); } fall_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.127293, 0.127927, 0.133519, 0.143645, 0.173349", \ "0.128426, 0.128439, 0.136064, 0.144179, 0.172543", \ "0.129915, 0.129742, 0.136701, 0.143946, 0.171524", \ "0.130654, 0.130271, 0.137166, 0.14483, 0.170651", \ "0.131043, 0.130674, 0.137556, 0.14511, 0.171284"); } } internal_power() { related_pin : "C"; rise_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.035808, 0.035489, 0.044592, 0.051538, 0.079147", \ "0.036017, 0.035802, 0.043906, 0.051867, 0.077981", \ "0.037705, 0.036801, 0.044343, 0.051059, 0.077119", \ "0.039283, 0.038198, 0.044045, 0.051184, 0.076567", \ "0.039825, 0.03845, 0.044375, 0.051195, 0.07665"); } fall_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.109316, 0.111416, 0.117667, 0.128347, 0.156639", \ "0.112156, 0.112979, 0.120978, 0.127124, 0.155339", \ "0.112995, 0.114118, 0.121699, 0.126441, 0.153897", \ "0.113217, 0.114428, 0.121547, 0.127901, 0.152452", \ "0.113603, 0.114684, 0.121592, 0.127952, 0.152668"); } } } pin(YS) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.489093; function : "((A^B)^C)"; timing() { related_pin : "A"; timing_sense : non_unate; cell_rise(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.198183, 0.22063, 0.259412, 0.287266, 0.367605", \ "0.21377, 0.235995, 0.273259, 0.300061, 0.38353", \ "0.236314, 0.258625, 0.29837, 0.323221, 0.405175", \ "0.321968, 0.343793, 0.382244, 0.407984, 0.488959", \ "0.447254, 0.469405, 0.506264, 0.534698, 0.617398"); } rise_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.037797, 0.039201, 0.03673, 0.038477, 0.039783", \ "0.050172, 0.052297, 0.053855, 0.05436, 0.056819", \ "0.0762, 0.0774, 0.0756, 0.0789, 0.0789", \ "0.1899, 0.1905, 0.1896, 0.1887, 0.1908", \ "0.366, 0.3663, 0.3666, 0.3666, 0.3666"); } cell_fall(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.179906, 0.198864, 0.221325, 0.23664, 0.262513", \ "0.197175, 0.214473, 0.238905, 0.255863, 0.280951", \ "0.223018, 0.240051, 0.265965, 0.279625, 0.304494", \ "0.303623, 0.320228, 0.345878, 0.359077, 0.383134", \ "0.414797, 0.431443, 0.456678, 0.468045, 0.494199"); } fall_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.035764, 0.038967, 0.037141, 0.034726, 0.035765", \ "0.048585, 0.05173, 0.053486, 0.054128, 0.05515", \ "0.0723, 0.0732, 0.0756, 0.0759, 0.0768", \ "0.1581, 0.1584, 0.159, 0.1581, 0.1593", \ "0.2937, 0.2928, 0.2928, 0.2934, 0.2925"); } } timing() { related_pin : "B"; timing_sense : non_unate; cell_rise(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.202117, 0.231199, 0.276088, 0.304101, 0.392641", \ "0.218949, 0.245499, 0.292062, 0.321212, 0.408316", \ "0.24145, 0.268402, 0.310025, 0.343549, 0.42776", \ "0.32668, 0.35353, 0.395463, 0.42947, 0.513406", \ "0.452468, 0.479998, 0.521574, 0.555072, 0.63896"); } rise_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.037337, 0.044051, 0.039734, 0.040894, 0.035759", \ "0.050144, 0.055434, 0.055747, 0.057998, 0.05534", \ "0.0816, 0.0801, 0.0765, 0.0798, 0.0768", \ "0.1902, 0.1899, 0.1902, 0.1884, 0.1905", \ "0.3669, 0.3666, 0.3669, 0.3669, 0.3666"); } cell_fall(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.185393, 0.20353, 0.23274, 0.244705, 0.274081", \ "0.204116, 0.222138, 0.24931, 0.261169, 0.289819", \ "0.228238, 0.246207, 0.274022, 0.286163, 0.312778", \ "0.309031, 0.325896, 0.352465, 0.365124, 0.391495", \ "0.420284, 0.436555, 0.465196, 0.475751, 0.504204"); } fall_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.03854, 0.036548, 0.034395, 0.0348, 0.034625", \ "0.050765, 0.054813, 0.051472, 0.051291, 0.055094", \ "0.0738, 0.0738, 0.0741, 0.0744, 0.0783", \ "0.1569, 0.1578, 0.1557, 0.1566, 0.1581", \ "0.2937, 0.2937, 0.2928, 0.2925, 0.2934"); } } timing() { related_pin : "C"; timing_sense : non_unate; cell_rise(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.198886, 0.231292, 0.283268, 0.317909, 0.415721", \ "0.209685, 0.244193, 0.297881, 0.330434, 0.428519", \ "0.232007, 0.267345, 0.319887, 0.352255, 0.448891", \ "0.317976, 0.354153, 0.405449, 0.439606, 0.5336", \ "0.444198, 0.482263, 0.531046, 0.568327, 0.661703"); } rise_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.040325, 0.041068, 0.03271, 0.040722, 0.038196", \ "0.050494, 0.052706, 0.049769, 0.053343, 0.051024", \ "0.0774, 0.0783, 0.0741, 0.0759, 0.0783", \ "0.1896, 0.1908, 0.1899, 0.1893, 0.1905", \ "0.3678, 0.3669, 0.3678, 0.3678, 0.3675"); } cell_fall(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.182744, 0.205478, 0.235746, 0.249718, 0.282904", \ "0.199541, 0.21712, 0.251752, 0.267096, 0.300069", \ "0.221615, 0.240859, 0.273688, 0.287033, 0.320866", \ "0.299374, 0.317787, 0.349653, 0.363724, 0.396233", \ "0.410155, 0.430433, 0.460409, 0.475767, 0.50694"); } fall_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.031091, 0.038205, 0.032021, 0.031051, 0.033051", \ "0.044424, 0.05168, 0.051882, 0.048639, 0.054146", \ "0.0705, 0.0684, 0.0675, 0.0702, 0.0747", \ "0.1554, 0.1554, 0.1548, 0.1545, 0.1551", \ "0.2925, 0.2919, 0.2922, 0.2919, 0.2928"); } } internal_power() { related_pin : "A"; rise_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.137117, 0.137859, 0.147519, 0.1579, 0.188671", \ "0.139337, 0.139992, 0.146761, 0.155933, 0.187897", \ "0.140148, 0.140413, 0.148995, 0.155314, 0.186999", \ "0.140706, 0.141603, 0.149331, 0.156135, 0.186049", \ "0.141124, 0.14205, 0.149664, 0.156595, 0.186534"); } fall_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.007466, 0.006824, 0.019945, 0.030237, 0.060247", \ "0.007781, 0.009663, 0.019533, 0.028757, 0.058276", \ "0.009603, 0.01151, 0.02075, 0.028254, 0.057467", \ "0.011239, 0.012692, 0.020968, 0.028039, 0.056866", \ "0.011618, 0.012838, 0.020969, 0.028073, 0.056587"); } } internal_power() { related_pin : "B"; rise_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.127293, 0.127927, 0.133519, 0.143645, 0.173349", \ "0.128426, 0.128439, 0.136064, 0.144179, 0.172543", \ "0.129915, 0.129742, 0.136701, 0.143946, 0.171524", \ "0.130654, 0.130271, 0.137166, 0.14483, 0.170651", \ "0.131043, 0.130674, 0.137556, 0.14511, 0.171284"); } fall_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.020977, 0.016769, 0.028506, 0.037122, 0.06575", \ "0.021323, 0.021127, 0.027771, 0.037435, 0.064538", \ "0.02299, 0.02218, 0.028788, 0.036974, 0.06455", \ "0.024243, 0.02359, 0.029653, 0.036487, 0.063384", \ "0.024575, 0.024024, 0.029942, 0.036647, 0.062954"); } } internal_power() { related_pin : "C"; rise_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.109316, 0.111416, 0.117667, 0.128347, 0.156639", \ "0.112156, 0.112979, 0.120978, 0.127124, 0.155339", \ "0.112995, 0.114118, 0.121699, 0.126441, 0.153897", \ "0.113217, 0.114428, 0.121547, 0.127901, 0.152452", \ "0.113603, 0.114684, 0.121592, 0.127952, 0.152668"); } fall_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.035808, 0.035489, 0.044592, 0.051538, 0.079147", \ "0.036017, 0.035802, 0.043906, 0.051867, 0.077981", \ "0.037705, 0.036801, 0.044343, 0.051059, 0.077119", \ "0.039283, 0.038198, 0.044045, 0.051184, 0.076567", \ "0.039825, 0.03845, 0.044375, 0.051195, 0.07665"); } } } } /* ------------- * * Design : HAX1 * * ------------- */ cell (HAX1) { area : 80; cell_leakage_power : 0.161137; pin(A) { direction : input; capacitance : 0.0247171; rise_capacitance : 0.0246331; fall_capacitance : 0.0247171; } pin(B) { direction : input; capacitance : 0.0211106; rise_capacitance : 0.0211106; fall_capacitance : 0.0210191; } pin(YC) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.502594; function : "(A B)"; timing() { related_pin : "A"; timing_sense : positive_unate; cell_rise(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.085358, 0.094012, 0.100275, 0.099453, 0.082882", \ "0.101778, 0.112779, 0.119221, 0.119581, 0.104536", \ "0.125066, 0.13649, 0.147553, 0.148647, 0.135188", \ "0.211867, 0.22364, 0.234494, 0.238289, 0.228946", \ "0.338223, 0.349942, 0.361144, 0.364776, 0.35749"); } rise_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.029846, 0.033511, 0.039111, 0.042072, 0.0678", \ "0.047394, 0.054259, 0.056519, 0.059846, 0.0768", \ "0.0768, 0.078, 0.0858, 0.0888, 0.0966", \ "0.1902, 0.1908, 0.192, 0.1956, 0.2022", \ "0.3666, 0.3666, 0.3678, 0.369, 0.3732"); } cell_fall(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.108843, 0.148356, 0.210329, 0.252769, 0.367948", \ "0.125339, 0.1652, 0.233502, 0.272277, 0.389844", \ "0.1487, 0.188581, 0.257852, 0.298306, 0.419765", \ "0.227414, 0.267177, 0.338186, 0.379907, 0.504804", \ "0.338046, 0.377809, 0.449292, 0.490981, 0.616712"); } fall_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.030945, 0.034479, 0.041411, 0.043358, 0.069", \ "0.049692, 0.046589, 0.06, 0.058864, 0.0762", \ "0.066, 0.0696, 0.0768, 0.0786, 0.09", \ "0.1542, 0.1542, 0.159, 0.1608, 0.1692", \ "0.2916, 0.2922, 0.2922, 0.294, 0.297"); } } timing() { related_pin : "B"; timing_sense : positive_unate; cell_rise(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.083223, 0.097317, 0.114316, 0.119069, 0.118286", \ "0.099521, 0.115173, 0.133598, 0.139531, 0.142715", \ "0.122739, 0.137849, 0.15908, 0.168142, 0.170798", \ "0.209715, 0.226246, 0.247335, 0.256975, 0.264658", \ "0.336211, 0.352081, 0.374516, 0.383711, 0.391929"); } rise_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.029604, 0.034946, 0.039841, 0.042991, 0.056287", \ "0.047447, 0.05219, 0.059766, 0.059756, 0.075", \ "0.078, 0.078, 0.0834, 0.0888, 0.0954", \ "0.1902, 0.1908, 0.1926, 0.195, 0.2022", \ "0.3672, 0.3666, 0.369, 0.369, 0.372"); } cell_fall(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.097136, 0.136274, 0.188809, 0.226182, 0.327261", \ "0.114498, 0.156371, 0.207832, 0.245453, 0.35214", \ "0.137501, 0.179508, 0.235227, 0.272065, 0.380852", \ "0.216183, 0.258107, 0.316202, 0.356775, 0.466672", \ "0.327126, 0.3686, 0.427276, 0.468319, 0.579168"); } fall_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.029882, 0.039079, 0.036229, 0.045811, 0.052498", \ "0.044321, 0.053219, 0.054172, 0.056233, 0.0708", \ "0.0642, 0.066, 0.0762, 0.0786, 0.0924", \ "0.1542, 0.1536, 0.1578, 0.1596, 0.1674", \ "0.291, 0.2922, 0.294, 0.2946, 0.2982"); } } internal_power() { related_pin : "A"; rise_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.037026, 0.033786, 0.042761, 0.048825, 0.072809", \ "0.037638, 0.034849, 0.042862, 0.048604, 0.071392", \ "0.038414, 0.035234, 0.043727, 0.049392, 0.070211", \ "0.039016, 0.036021, 0.04298, 0.049002, 0.069506", \ "0.0393, 0.036454, 0.043253, 0.048934, 0.069391"); } fall_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.077084, 0.078004, 0.086945, 0.094421, 0.118606", \ "0.07744, 0.078311, 0.088214, 0.094018, 0.116461", \ "0.077756, 0.078449, 0.088388, 0.093451, 0.115465", \ "0.078677, 0.079201, 0.088598, 0.093644, 0.115553", \ "0.079144, 0.079244, 0.088865, 0.094032, 0.116101"); } } internal_power() { related_pin : "B"; rise_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.047187, 0.04301, 0.052467, 0.058987, 0.084861", \ "0.047188, 0.043824, 0.053109, 0.059138, 0.083706", \ "0.047529, 0.043539, 0.052945, 0.059775, 0.082777", \ "0.048555, 0.044674, 0.052352, 0.059345, 0.083031", \ "0.049041, 0.045208, 0.052753, 0.059207, 0.083092"); } fall_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.06765, 0.070247, 0.075598, 0.081985, 0.106254", \ "0.067897, 0.069771, 0.075292, 0.081491, 0.104973", \ "0.068347, 0.069856, 0.076452, 0.081147, 0.104028", \ "0.068946, 0.070314, 0.07664, 0.082397, 0.102172", \ "0.068601, 0.070691, 0.076904, 0.082678, 0.102693"); } } } pin(YS) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.481203; function : "(A^B)"; timing() { related_pin : "A"; timing_sense : non_unate; cell_rise(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.149058, 0.187598, 0.252874, 0.291453, 0.413224", \ "0.166689, 0.201554, 0.26849, 0.306329, 0.427747", \ "0.187902, 0.225297, 0.288655, 0.32755, 0.446103", \ "0.271378, 0.309285, 0.372234, 0.412365, 0.530283", \ "0.396693, 0.435959, 0.497742, 0.537539, 0.660354"); } rise_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.030674, 0.030087, 0.035974, 0.030274, 0.044562", \ "0.051086, 0.046192, 0.048796, 0.048319, 0.053992", \ "0.0726, 0.0714, 0.075, 0.0762, 0.078", \ "0.189, 0.1884, 0.189, 0.1872, 0.189", \ "0.3654, 0.3666, 0.3648, 0.3654, 0.366"); } cell_fall(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.152679, 0.15852, 0.169659, 0.172068, 0.1628", \ "0.167175, 0.176611, 0.183469, 0.185952, 0.174854", \ "0.186688, 0.194728, 0.207833, 0.209996, 0.196142", \ "0.261489, 0.269263, 0.281771, 0.283352, 0.268541", \ "0.371628, 0.379829, 0.391784, 0.396291, 0.377902"); } fall_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.033564, 0.036382, 0.028424, 0.032597, 0.0316", \ "0.043892, 0.044254, 0.042472, 0.043167, 0.044107", \ "0.0642, 0.0606, 0.0714, 0.0714, 0.0672", \ "0.1536, 0.1524, 0.15, 0.1506, 0.1542", \ "0.2904, 0.2916, 0.2904, 0.2898, 0.2898"); } } timing() { related_pin : "B"; timing_sense : non_unate; cell_rise(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.142672, 0.185479, 0.237913, 0.273327, 0.380148", \ "0.15828, 0.200628, 0.25144, 0.286961, 0.396714", \ "0.180359, 0.222974, 0.273734, 0.308942, 0.414381", \ "0.265809, 0.307628, 0.357495, 0.398085, 0.495232", \ "0.398108, 0.433179, 0.483931, 0.523541, 0.62621"); } rise_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.029969, 0.037745, 0.032326, 0.030433, 0.032778", \ "0.047823, 0.04903, 0.04912, 0.048363, 0.054818", \ "0.0726, 0.0732, 0.0756, 0.0744, 0.075", \ "0.1896, 0.1896, 0.1878, 0.1866, 0.1878", \ "0.3666, 0.3654, 0.366, 0.366, 0.366"); } cell_fall(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.148831, 0.160485, 0.184599, 0.192589, 0.200687", \ "0.163236, 0.176722, 0.199978, 0.204137, 0.213631", \ "0.182718, 0.193019, 0.220361, 0.225654, 0.232882", \ "0.257382, 0.268235, 0.292415, 0.298886, 0.307103", \ "0.367566, 0.378594, 0.401833, 0.41316, 0.417643"); } fall_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.032374, 0.037431, 0.032683, 0.031342, 0.037325", \ "0.044998, 0.044215, 0.050212, 0.04256, 0.045854", \ "0.0624, 0.0624, 0.0738, 0.0648, 0.0678", \ "0.153, 0.1506, 0.15, 0.15, 0.1542", \ "0.291, 0.2916, 0.2892, 0.2886, 0.2922"); } } internal_power() { related_pin : "A"; rise_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.077084, 0.078004, 0.086945, 0.094421, 0.118606", \ "0.07744, 0.078311, 0.088214, 0.094018, 0.116461", \ "0.077756, 0.078449, 0.088388, 0.093451, 0.115465", \ "0.078677, 0.079201, 0.088598, 0.093644, 0.115553", \ "0.079144, 0.079244, 0.088865, 0.094032, 0.116101"); } fall_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.037026, 0.033786, 0.042761, 0.048825, 0.072809", \ "0.037638, 0.034849, 0.042862, 0.048604, 0.071392", \ "0.038414, 0.035234, 0.043727, 0.049392, 0.070211", \ "0.039016, 0.036021, 0.04298, 0.049002, 0.069506", \ "0.0393, 0.036454, 0.043253, 0.048934, 0.069391"); } } internal_power() { related_pin : "B"; rise_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.06765, 0.070247, 0.075598, 0.081985, 0.106254", \ "0.067897, 0.069771, 0.075292, 0.081491, 0.104973", \ "0.068347, 0.069856, 0.076452, 0.081147, 0.104028", \ "0.068946, 0.070314, 0.07664, 0.082397, 0.102172", \ "0.068601, 0.070691, 0.076904, 0.082678, 0.102693"); } fall_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.047187, 0.04301, 0.052467, 0.058987, 0.084861", \ "0.047188, 0.043824, 0.053109, 0.059138, 0.083706", \ "0.047529, 0.043539, 0.052945, 0.059775, 0.082777", \ "0.048555, 0.044674, 0.052352, 0.059345, 0.083031", \ "0.049041, 0.045208, 0.052753, 0.059207, 0.083092"); } } } } /* -------------- * * Design : INVX1 * * -------------- */ cell (INVX1) { cell_footprint : inv; area : 16; cell_leakage_power : 0.0221741; pin(A) { direction : input; capacitance : 0.00932456; rise_capacitance : 0.00932196; fall_capacitance : 0.00932456; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.503808; function : "(!A)"; timing() { related_pin : "A"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.030906, 0.037434, 0.038584, 0.039088, 0.030318", \ "0.04464, 0.057551, 0.073142, 0.077841, 0.081003", \ "0.064368, 0.091076, 0.11557, 0.126352, 0.144944", \ "0.139135, 0.174422, 0.232659, 0.261317, 0.321043", \ "0.249412, 0.28434, 0.357694, 0.406534, 0.51187"); } fall_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.032269, 0.0648, 0.087, 0.1032, 0.1476", \ "0.036025, 0.0726, 0.1044, 0.1236, 0.183", \ "0.06, 0.0882, 0.1314, 0.1554, 0.2286", \ "0.1494, 0.1578, 0.2124, 0.2508, 0.3528", \ "0.288, 0.2892, 0.3192, 0.3576, 0.492"); } cell_rise(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.037639, 0.056898, 0.083401, 0.104927, 0.156652", \ "0.05258, 0.083003, 0.119028, 0.141927, 0.207952", \ "0.07402, 0.112622, 0.162437, 0.191122, 0.271755", \ "0.15767, 0.201007, 0.284096, 0.331746, 0.452958", \ "0.285016, 0.326868, 0.415086, 0.481337, 0.653064"); } rise_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.031447, 0.059488, 0.0846, 0.0918, 0.138", \ "0.047167, 0.0786, 0.1044, 0.1224, 0.1734", \ "0.072, 0.096, 0.1398, 0.1578, 0.222", \ "0.1866, 0.1914, 0.2358, 0.2748, 0.3696", \ "0.3648, 0.3648, 0.384, 0.4146, 0.5388"); } } internal_power() { related_pin : "A"; fall_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.009213, 0.004772, 0.00823, 0.018532, 0.054083", \ "0.009047, 0.005677, 0.005713, 0.015244, 0.049453", \ "0.008669, 0.006332, 0.002998, 0.01159, 0.04368", \ "0.007879, 0.007243, 0.001451, 0.004701, 0.030385", \ "0.007605, 0.007297, 0.003652, 0.000737, 0.020842"); } rise_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.023555, 0.029044, 0.041387, 0.051684, 0.087278", \ "0.023165, 0.028621, 0.039211, 0.048916, 0.083039", \ "0.023574, 0.02752, 0.036904, 0.045723, 0.077971", \ "0.024479, 0.025247, 0.032268, 0.039242, 0.066587", \ "0.024942, 0.025187, 0.029612, 0.034835, 0.057524"); } } } } /* -------------- * * Design : INVX2 * * -------------- */ cell (INVX2) { cell_footprint : inv; area : 16; cell_leakage_power : 0.0367509; pin(A) { direction : input; capacitance : 0.0186567; rise_capacitance : 0.0186461; fall_capacitance : 0.0186567; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.984408; function : "(!A)"; timing() { related_pin : "A"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.01, 0.025, 0.05, 0.15, 0.3"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.032632, 0.040337, 0.044681, 0.046667, 0.042356", \ "0.047211, 0.061414, 0.078874, 0.0856, 0.094405", \ "0.069131, 0.094604, 0.12277, 0.135433, 0.160039", \ "0.148168, 0.183302, 0.244679, 0.274903, 0.341248", \ "0.266972, 0.301575, 0.374804, 0.425712, 0.538987"); } fall_transition(delay_template_5x5) { index_1 ("0.01, 0.025, 0.05, 0.15, 0.3"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.032323, 0.0648, 0.0852, 0.102, 0.144", \ "0.036499, 0.0744, 0.1074, 0.1254, 0.189", \ "0.0636, 0.0924, 0.1332, 0.1566, 0.2328", \ "0.1608, 0.1686, 0.2196, 0.2592, 0.3624", \ "0.3114, 0.3108, 0.3372, 0.3738, 0.5076"); } cell_rise(delay_template_5x5) { index_1 ("0.01, 0.025, 0.05, 0.15, 0.3"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.038051, 0.057734, 0.082403, 0.102222, 0.150603", \ "0.0533, 0.083516, 0.118618, 0.140573, 0.203618", \ "0.075541, 0.113686, 0.162856, 0.190874, 0.268952", \ "0.161729, 0.204229, 0.286885, 0.334269, 0.453778", \ "0.292363, 0.333831, 0.421093, 0.486676, 0.657729"); } rise_transition(delay_template_5x5) { index_1 ("0.01, 0.025, 0.05, 0.15, 0.3"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.031721, 0.0672, 0.0858, 0.0948, 0.138", \ "0.04837, 0.0798, 0.1062, 0.1248, 0.1764", \ "0.0744, 0.0978, 0.1422, 0.1608, 0.2268", \ "0.1926, 0.1974, 0.24, 0.2802, 0.3768", \ "0.3744, 0.375, 0.3936, 0.4236, 0.5496"); } } internal_power() { related_pin : "A"; fall_power(energy_template_5x5) { index_1 ("0.01, 0.025, 0.05, 0.15, 0.3"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.018859, 0.010481, 0.014322, 0.033889, 0.10178", \ "0.018371, 0.012213, 0.009374, 0.027508, 0.092642", \ "0.017216, 0.013581, 0.004141, 0.020413, 0.081386", \ "0.015819, 0.01485, 0.0042, 0.007301, 0.055731", \ "0.01524, 0.014813, 0.00823, 0.000114, 0.03752"); } rise_power(energy_template_5x5) { index_1 ("0.01, 0.025, 0.05, 0.15, 0.3"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.046998, 0.056527, 0.081025, 0.100533, 0.168537", \ "0.046437, 0.05647, 0.076599, 0.095106, 0.160317", \ "0.047242, 0.054342, 0.072097, 0.088869, 0.150394", \ "0.049072, 0.050295, 0.063214, 0.076296, 0.128133", \ "0.049968, 0.050297, 0.05833, 0.067964, 0.110555"); } } } } /* -------------- * * Design : INVX4 * * -------------- */ cell (INVX4) { cell_footprint : inv; area : 24; cell_leakage_power : 0.0735019; pin(A) { direction : input; capacitance : 0.0373134; rise_capacitance : 0.0372921; fall_capacitance : 0.0373134; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 1.96882; function : "(!A)"; timing() { related_pin : "A"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.02, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.032632, 0.040337, 0.044681, 0.046667, 0.042356", \ "0.047211, 0.061414, 0.078874, 0.0856, 0.094405", \ "0.069131, 0.094604, 0.12277, 0.135433, 0.160039", \ "0.148168, 0.183302, 0.244679, 0.274903, 0.341248", \ "0.266972, 0.301575, 0.374804, 0.425712, 0.538987"); } fall_transition(delay_template_5x5) { index_1 ("0.02, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.032323, 0.0648, 0.0852, 0.102, 0.144", \ "0.036499, 0.0744, 0.1074, 0.1254, 0.189", \ "0.0636, 0.0924, 0.1332, 0.1566, 0.2328", \ "0.1608, 0.1686, 0.2196, 0.2592, 0.3624", \ "0.3114, 0.3108, 0.3372, 0.3738, 0.5076"); } cell_rise(delay_template_5x5) { index_1 ("0.02, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.038051, 0.057734, 0.082403, 0.102222, 0.150603", \ "0.0533, 0.083516, 0.118618, 0.140573, 0.203618", \ "0.075541, 0.113686, 0.162856, 0.190874, 0.268952", \ "0.161729, 0.204229, 0.286885, 0.334269, 0.453778", \ "0.292363, 0.333831, 0.421093, 0.486676, 0.657729"); } rise_transition(delay_template_5x5) { index_1 ("0.02, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.031721, 0.0672, 0.0858, 0.0948, 0.138", \ "0.04837, 0.0798, 0.1062, 0.1248, 0.1764", \ "0.0744, 0.0978, 0.1422, 0.1608, 0.2268", \ "0.1926, 0.1974, 0.24, 0.2802, 0.3768", \ "0.3744, 0.375, 0.3936, 0.4236, 0.5496"); } } internal_power() { related_pin : "A"; fall_power(energy_template_5x5) { index_1 ("0.02, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.037717, 0.020962, 0.028643, 0.067778, 0.20356", \ "0.036742, 0.024427, 0.018748, 0.055015, 0.185284", \ "0.034433, 0.027162, 0.008282, 0.040826, 0.162772", \ "0.031638, 0.0297, 0.0084, 0.014602, 0.111461", \ "0.030481, 0.029626, 0.016461, 0.000227, 0.075041"); } rise_power(energy_template_5x5) { index_1 ("0.02, 0.05, 0.1, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.093996, 0.113054, 0.16205, 0.201065, 0.337073", \ "0.092874, 0.11294, 0.153197, 0.190211, 0.320633", \ "0.094485, 0.108685, 0.144194, 0.177737, 0.300787", \ "0.098145, 0.10059, 0.126429, 0.152592, 0.256266", \ "0.099936, 0.100595, 0.116661, 0.135929, 0.221109"); } } } } /* -------------- * * Design : INVX8 * * -------------- */ cell (INVX8) { cell_footprint : inv; area : 40; cell_leakage_power : 0.147006; pin(A) { direction : input; capacitance : 0.0746269; rise_capacitance : 0.0745842; fall_capacitance : 0.0746269; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 3.93763; function : "(!A)"; timing() { related_pin : "A"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.04, 0.1, 0.2, 0.6, 1.2"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.032632, 0.040337, 0.044681, 0.046667, 0.042356", \ "0.047211, 0.061414, 0.078874, 0.0856, 0.094405", \ "0.069131, 0.094604, 0.12277, 0.135433, 0.160039", \ "0.148168, 0.183302, 0.244679, 0.274903, 0.341248", \ "0.266972, 0.301575, 0.374804, 0.425712, 0.538987"); } fall_transition(delay_template_5x5) { index_1 ("0.04, 0.1, 0.2, 0.6, 1.2"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.032323, 0.0648, 0.0852, 0.102, 0.144", \ "0.036499, 0.0744, 0.1074, 0.1254, 0.189", \ "0.0636, 0.0924, 0.1332, 0.1566, 0.2328", \ "0.1608, 0.1686, 0.2196, 0.2592, 0.3624", \ "0.3114, 0.3108, 0.3372, 0.3738, 0.5076"); } cell_rise(delay_template_5x5) { index_1 ("0.04, 0.1, 0.2, 0.6, 1.2"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.038051, 0.057734, 0.082403, 0.102222, 0.150603", \ "0.0533, 0.083516, 0.118618, 0.140573, 0.203618", \ "0.075541, 0.113686, 0.162856, 0.190874, 0.268952", \ "0.161729, 0.204229, 0.286885, 0.334269, 0.453778", \ "0.292363, 0.333831, 0.421093, 0.486676, 0.657729"); } rise_transition(delay_template_5x5) { index_1 ("0.04, 0.1, 0.2, 0.6, 1.2"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.031721, 0.0672, 0.0858, 0.0948, 0.138", \ "0.04837, 0.0798, 0.1062, 0.1248, 0.1764", \ "0.0744, 0.0978, 0.1422, 0.1608, 0.2268", \ "0.1926, 0.1974, 0.24, 0.2802, 0.3768", \ "0.3744, 0.375, 0.3936, 0.4236, 0.5496"); } } internal_power() { related_pin : "A"; fall_power(energy_template_5x5) { index_1 ("0.04, 0.1, 0.2, 0.6, 1.2"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.075435, 0.041924, 0.057286, 0.135557, 0.40712", \ "0.073484, 0.048853, 0.037496, 0.110031, 0.370568", \ "0.068865, 0.054324, 0.016565, 0.081653, 0.325545", \ "0.063277, 0.0594, 0.0168, 0.029205, 0.222922", \ "0.060961, 0.059253, 0.032921, 0.000455, 0.150081"); } rise_power(energy_template_5x5) { index_1 ("0.04, 0.1, 0.2, 0.6, 1.2"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.187992, 0.226109, 0.3241, 0.402131, 0.674147", \ "0.185747, 0.22588, 0.306395, 0.380423, 0.641267", \ "0.18897, 0.21737, 0.288388, 0.355474, 0.601575", \ "0.196289, 0.201179, 0.252858, 0.305184, 0.512532", \ "0.199872, 0.201189, 0.233321, 0.271857, 0.442219"); } } } } /* -------------- * * Design : LATCH * * -------------- */ cell (LATCH) { area : 0; cell_leakage_power : 0.103166; latch (DS0000,P0000) { data_in : "D"; enable : "CLK"; } pin(CLK) { direction : input; capacitance : 0.0222524; rise_capacitance : 0.0222524; fall_capacitance : 0.0222519; clock : true; internal_power() { rise_power(passive_energy_template_6x1) { index_1 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ("0.010031, 0.006536, 0.033284, 0.079262, 0.115653, 0.184439"); } fall_power(passive_energy_template_6x1) { index_1 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ("0.060818, 0.076387, 0.102454, 0.1481, 0.183716, 0.25319"); } } min_pulse_width_high : 0.149322; } pin(D) { direction : input; capacitance : 0.00873537; rise_capacitance : 0.00866992; fall_capacitance : 0.00873537; timing() { related_pin : "CLK"; timing_type : hold_falling; rise_constraint(hold_template_3x6) { index_1 ("0.06, 0.3, 0.6"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "-0.09375, -0.13125, -0.11875, -0.14375, -0.175, -0.14375", \ "-0.10625, -0.14375, -0.13125, -0.15625, -0.1875, -0.15625", \ "-0.16875, -0.20625, -0.19375, -0.21875, -0.25, -0.21875"); } fall_constraint(hold_template_3x6) { index_1 ("0.06, 0.3, 0.6"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "-0.09375, -0.13125, -0.11875, -0.14375, -0.26875, -0.33125", \ "-0.0125, -0.05, -0.13125, -0.15625, -0.1875, -0.25", \ "0.01875, -0.01875, -0.1, -0.125, -0.15625, -0.3125"); } } timing() { related_pin : "CLK"; timing_type : setup_falling; rise_constraint(setup_template_3x6) { index_1 ("0.06, 0.3, 0.6"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.1875, 0.225, 0.2125, 0.2375, 0.26875, 0.51875", \ "0.29375, 0.33125, 0.31875, 0.34375, 0.375, 0.71875", \ "0.45, 0.58125, 0.56875, 0.40625, 0.4375, 0.96875"); } fall_constraint(setup_template_3x6) { index_1 ("0.06, 0.3, 0.6"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.1875, 0.225, 0.30625, 0.33125, 0.3625, 0.51875", \ "0.2, 0.2375, 0.4125, 0.34375, 0.375, 0.4375", \ "0.16875, 0.20625, 0.2875, 0.3125, 0.34375, 0.40625"); } } } pin(Q) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.973513; function : "DS0000"; timing() { related_pin : "CLK"; timing_sense : non_unate; timing_type : rising_edge; cell_rise(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.18909, 0.218413, 0.23187, 0.233755, 0.226597, 0.200201", \ "0.536777, 0.565286, 0.578688, 0.580569, 0.573314, 0.549413", \ "1.14096, 1.16975, 1.18342, 1.18477, 1.17804, 1.15432", \ "2.69477, 2.72325, 2.73707, 2.73941, 2.73171, 2.70708", \ "3.55791, 3.58635, 3.59991, 3.6027, 3.5952, 3.57163", \ "4.42163, 4.44975, 4.46196, 4.46488, 4.45845, 4.43438"); } rise_transition(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.1458, 0.1488, 0.1566, 0.165, 0.1686, 0.18", \ "0.633, 0.6324, 0.6336, 0.6354, 0.6366, 0.6408", \ "1.4934, 1.4928, 1.4922, 1.4928, 1.494, 1.497", \ "3.705, 3.705, 3.7044, 3.7068, 3.7062, 3.7038", \ "4.9338, 4.9332, 4.9356, 4.9338, 4.935, 4.9344", \ "6.165, 6.165, 6.165, 6.1638, 6.1638, 6.1632"); } cell_fall(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.246125, 0.260752, 0.272064, 0.280557, 0.277834, 0.276812", \ "0.568379, 0.581956, 0.592678, 0.602286, 0.59883, 0.600004", \ "1.12243, 1.13602, 1.14693, 1.15599, 1.15224, 1.15283", \ "2.5462, 2.55973, 2.57084, 2.58001, 2.57619, 2.5754", \ "3.3372, 3.35076, 3.36199, 3.37103, 3.36612, 3.36578", \ "4.12779, 4.14172, 4.1528, 4.16223, 4.15678, 4.15809"); } fall_transition(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.1344, 0.1326, 0.1326, 0.135, 0.1338, 0.1326", \ "0.528, 0.528, 0.528, 0.5274, 0.528, 0.5286", \ "1.2384, 1.2378, 1.2378, 1.2384, 1.2366, 1.236", \ "3.0672, 3.0666, 3.0684, 3.0678, 3.0672, 3.0648", \ "4.0842, 4.0842, 4.0842, 4.0848, 4.0812, 4.0824", \ "5.1006, 5.1006, 5.1006, 5.1, 5.0976, 5.0964"); } } timing() { related_pin : "D"; timing_sense : positive_unate; cell_rise(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.210937, 0.237525, 0.263286, 0.292353, 0.303925, 0.321076", \ "0.557971, 0.585911, 0.611315, 0.638968, 0.652981, 0.673186", \ "1.16296, 1.19063, 1.2161, 1.2441, 1.25749, 1.27842", \ "2.71705, 2.7443, 2.76952, 2.79832, 2.81197, 2.83233", \ "3.57852, 3.60631, 3.63229, 3.66172, 3.67576, 3.69607", \ "4.4416, 4.47023, 4.49494, 4.52491, 4.5389, 4.55871"); } rise_transition(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.1476, 0.1494, 0.1506, 0.1584, 0.1596, 0.1716", \ "0.6324, 0.6318, 0.633, 0.6342, 0.6354, 0.6402", \ "1.4928, 1.4928, 1.4922, 1.494, 1.4928, 1.4946", \ "3.7062, 3.7038, 3.7044, 3.7074, 3.7056, 3.7074", \ "4.9344, 4.9338, 4.935, 4.9326, 4.9332, 4.9332", \ "6.1644, 6.1644, 6.1644, 6.1638, 6.1638, 6.162"); } cell_fall(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.244037, 0.281305, 0.320272, 0.387479, 0.430721, 0.509293", \ "0.564118, 0.601547, 0.642835, 0.711297, 0.754387, 0.837102", \ "1.11784, 1.15563, 1.19662, 1.26524, 1.30888, 1.391", \ "2.54141, 2.57949, 2.62027, 2.68836, 2.73272, 2.81466", \ "3.33236, 3.36895, 3.41105, 3.4799, 3.52322, 3.60448", \ "4.12332, 4.16064, 4.20241, 4.27068, 4.31274, 4.39483"); } fall_transition(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.1326, 0.1326, 0.1368, 0.1464, 0.1494, 0.1596", \ "0.528, 0.5274, 0.5286, 0.531, 0.5316, 0.5352", \ "1.2372, 1.2372, 1.2372, 1.2396, 1.2396, 1.2402", \ "3.0678, 3.0678, 3.0672, 3.0666, 3.0654, 3.0678", \ "4.0842, 4.0818, 4.0824, 4.0806, 4.0812, 4.0824", \ "5.1006, 5.0988, 5.1006, 5.0964, 5.0988, 5.0982"); } } internal_power() { related_pin : "CLK"; rise_power(energy_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.038408, 0.057367, 0.089036, 0.15147, 0.193, 0.278585", \ "0.040739, 0.058496, 0.089776, 0.148617, 0.191407, 0.279096", \ "0.041182, 0.059146, 0.090506, 0.149199, 0.191888, 0.27847", \ "0.041362, 0.059391, 0.090869, 0.149687, 0.192335, 0.278863", \ "0.041312, 0.059343, 0.090857, 0.149704, 0.192434, 0.278866", \ "0.041312, 0.059323, 0.090902, 0.149735, 0.192502, 0.279014"); } fall_power(energy_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.06354, 0.075317, 0.100798, 0.151019, 0.186273, 0.257456", \ "0.063927, 0.076894, 0.103062, 0.151788, 0.186149, 0.25675", \ "0.064656, 0.077581, 0.103802, 0.152681, 0.186584, 0.25713", \ "0.064959, 0.077968, 0.104174, 0.153068, 0.186931, 0.25752", \ "0.065018, 0.078043, 0.104238, 0.153221, 0.186986, 0.257588", \ "0.064996, 0.078001, 0.104263, 0.153232, 0.18705, 0.257639"); } } internal_power() { related_pin : "D"; rise_power(energy_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.047217, 0.052308, 0.061774, 0.0816, 0.096724, 0.130191", \ "0.050227, 0.053368, 0.061075, 0.080069, 0.094248, 0.124788", \ "0.050887, 0.053854, 0.061829, 0.080544, 0.094615, 0.124458", \ "0.051097, 0.054029, 0.062242, 0.080966, 0.095056, 0.124728", \ "0.051069, 0.054041, 0.062245, 0.081016, 0.095081, 0.124789", \ "0.051137, 0.054041, 0.062266, 0.081062, 0.095215, 0.124888"); } fall_power(energy_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.098675, 0.100019, 0.108217, 0.128369, 0.144286, 0.17707", \ "0.09899, 0.100602, 0.108735, 0.128095, 0.142828, 0.173275", \ "0.098898, 0.101152, 0.109334, 0.128556, 0.143306, 0.173336", \ "0.099044, 0.101398, 0.109702, 0.128973, 0.143726, 0.173639", \ "0.099079, 0.101443, 0.109769, 0.129053, 0.143888, 0.17369", \ "0.099072, 0.101448, 0.109865, 0.129071, 0.143883, 0.17368"); } } } } /* --------------- * * Design : MUX2X1 * * --------------- */ cell (MUX2X1) { area : 48; cell_leakage_power : 0.0870033; pin(A) { direction : input; capacitance : 0.0173455; rise_capacitance : 0.0170984; fall_capacitance : 0.0173455; } pin(B) { direction : input; capacitance : 0.0173537; rise_capacitance : 0.0170875; fall_capacitance : 0.0173537; } pin(S) { direction : input; capacitance : 0.0204132; rise_capacitance : 0.0203919; fall_capacitance : 0.0204132; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.488958; function : "(!((S A) + (!S B)))"; timing() { related_pin : "A"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.049841, 0.062439, 0.070817, 0.074619, 0.075764", \ "0.06038, 0.076407, 0.087308, 0.09453, 0.10352", \ "0.077941, 0.096048, 0.113817, 0.124416, 0.139745", \ "0.14017, 0.162075, 0.195951, 0.214682, 0.257299", \ "0.232475, 0.254972, 0.296829, 0.323596, 0.39058"); } fall_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.039692, 0.066, 0.0984, 0.1206, 0.18", \ "0.056615, 0.0756, 0.1122, 0.1332, 0.2004", \ "0.0714, 0.0918, 0.1272, 0.1488, 0.2238", \ "0.1506, 0.1566, 0.1926, 0.2196, 0.306", \ "0.2712, 0.2718, 0.294, 0.3186, 0.4092"); } cell_rise(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.072351, 0.086817, 0.114778, 0.134772, 0.193395", \ "0.086412, 0.103969, 0.133, 0.154627, 0.220414", \ "0.107326, 0.128553, 0.161634, 0.186654, 0.259106", \ "0.19325, 0.214026, 0.261158, 0.291116, 0.382551", \ "0.320216, 0.341082, 0.391527, 0.428828, 0.53531"); } rise_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.052306, 0.0762, 0.0984, 0.1164, 0.168", \ "0.075, 0.0882, 0.1194, 0.1338, 0.1878", \ "0.1002, 0.1158, 0.1422, 0.1638, 0.2208", \ "0.219, 0.2232, 0.2478, 0.27, 0.336", \ "0.396, 0.396, 0.4104, 0.4272, 0.4998"); } } timing() { related_pin : "B"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.054662, 0.063511, 0.071265, 0.074915, 0.075865", \ "0.065546, 0.078306, 0.08765, 0.094949, 0.104013", \ "0.082423, 0.097893, 0.114535, 0.125138, 0.140125", \ "0.146105, 0.164949, 0.197303, 0.215761, 0.257086", \ "0.2385, 0.258003, 0.298933, 0.325026, 0.391418"); } fall_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.04514, 0.0648, 0.0966, 0.1182, 0.1776", \ "0.058413, 0.0756, 0.1104, 0.1314, 0.1986", \ "0.0786, 0.0924, 0.1266, 0.1476, 0.2226", \ "0.1536, 0.159, 0.1938, 0.2202, 0.303", \ "0.2742, 0.2742, 0.2964, 0.321, 0.4092"); } cell_rise(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.066015, 0.08492, 0.11281, 0.132989, 0.191892", \ "0.081067, 0.100589, 0.131696, 0.153589, 0.219376", \ "0.102628, 0.125139, 0.16009, 0.185256, 0.258795", \ "0.189337, 0.211033, 0.259234, 0.289464, 0.381313", \ "0.316367, 0.338345, 0.389351, 0.427169, 0.534114"); } rise_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.053671, 0.072, 0.1002, 0.1182, 0.1668", \ "0.0702, 0.0888, 0.1206, 0.135, 0.1884", \ "0.0984, 0.1128, 0.1428, 0.1644, 0.2208", \ "0.2178, 0.222, 0.2472, 0.2694, 0.3342", \ "0.3942, 0.3942, 0.4086, 0.426, 0.4998"); } } timing() { related_pin : "S"; timing_sense : non_unate; cell_rise(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.100427, 0.115951, 0.142823, 0.157884, 0.17571", \ "0.113348, 0.128794, 0.159753, 0.171618, 0.192833", \ "0.13471, 0.151395, 0.180934, 0.194907, 0.216615", \ "0.215914, 0.238688, 0.26376, 0.275954, 0.299918", \ "0.34018, 0.36622, 0.388128, 0.399598, 0.424692"); } rise_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.05407, 0.05147, 0.05628, 0.0678, 0.072", \ "0.0696, 0.0666, 0.0816, 0.0804, 0.0924", \ "0.1008, 0.0996, 0.1014, 0.1044, 0.1134", \ "0.2184, 0.219, 0.2112, 0.2106, 0.2154", \ "0.3954, 0.396, 0.3906, 0.3888, 0.39"); } cell_fall(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.099458, 0.130249, 0.180656, 0.211869, 0.29018", \ "0.109448, 0.140076, 0.191393, 0.223325, 0.301373", \ "0.125309, 0.156202, 0.210391, 0.24179, 0.319929", \ "0.18479, 0.217556, 0.271307, 0.302384, 0.386655", \ "0.274707, 0.307295, 0.359763, 0.393482, 0.477327"); } fall_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.045961, 0.044488, 0.046733, 0.0684, 0.0726", \ "0.057213, 0.056881, 0.058283, 0.0702, 0.078", \ "0.078, 0.0786, 0.0852, 0.0864, 0.0912", \ "0.1548, 0.1548, 0.1506, 0.1536, 0.1584", \ "0.2742, 0.2736, 0.27, 0.2694, 0.2712"); } } internal_power() { related_pin : "A"; fall_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.01907, 0.014997, 0.002981, 0.018697, 0.075579", \ "0.018751, 0.014696, 0.000905, 0.01617, 0.07148", \ "0.018262, 0.014954, 0.001323, 0.01254, 0.065647", \ "0.017453, 0.016036, 0.006445, 0.00428, 0.049438", \ "0.017013, 0.016548, 0.009485, 0.001448, 0.035417"); } rise_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.095161, 0.097884, 0.115213, 0.131187, 0.18897", \ "0.095544, 0.097404, 0.113725, 0.12853, 0.185696", \ "0.09578, 0.097049, 0.110996, 0.12527, 0.180604", \ "0.096304, 0.095756, 0.10667, 0.118, 0.16602", \ "0.096814, 0.096191, 0.103844, 0.112461, 0.15306"); } } internal_power() { related_pin : "B"; fall_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.004462, 0.007633, 0.026336, 0.042227, 0.098755", \ "0.004829, 0.008638, 0.024477, 0.039507, 0.09467", \ "0.005725, 0.008503, 0.02219, 0.035927, 0.088849", \ "0.006188, 0.007371, 0.01687, 0.027553, 0.072835", \ "0.006544, 0.006814, 0.01381, 0.021918, 0.058831"); } rise_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.072685, 0.075745, 0.093126, 0.109042, 0.167212", \ "0.072538, 0.075094, 0.091529, 0.106543, 0.163512", \ "0.072993, 0.074866, 0.08859, 0.103206, 0.158549", \ "0.073629, 0.072972, 0.084054, 0.09549, 0.143675", \ "0.07412, 0.073345, 0.081069, 0.089851, 0.130439"); } } internal_power() { related_pin : "S"; rise_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.056455, 0.05297, 0.066123, 0.077991, 0.117024", \ "0.056071, 0.05269, 0.066661, 0.07747, 0.114947", \ "0.05456, 0.053053, 0.065867, 0.076629, 0.111982", \ "0.051875, 0.054102, 0.065763, 0.074375, 0.109935", \ "0.049442, 0.052849, 0.065156, 0.074353, 0.109384"); } fall_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.091443, 0.091747, 0.105716, 0.115072, 0.15201", \ "0.090143, 0.091197, 0.10563, 0.115065, 0.150487", \ "0.088359, 0.090468, 0.104825, 0.114881, 0.149389", \ "0.084078, 0.087722, 0.102949, 0.113106, 0.148234", \ "0.081489, 0.085188, 0.100644, 0.11098, 0.146933"); } } } } /* ---------------- * * Design : NAND2X1 * * ---------------- */ cell (NAND2X1) { area : 24; cell_leakage_power : 0.0393659; pin(A) { direction : input; capacitance : 0.0125; rise_capacitance : 0.0125; fall_capacitance : 0.0122726; } pin(B) { direction : input; capacitance : 0.0129035; rise_capacitance : 0.0129005; fall_capacitance : 0.0129035; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.499794; function : "(!(A B))"; timing() { related_pin : "A"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.032849, 0.032709, 0.02129, 0.009771, -0.035525", \ "0.046123, 0.052511, 0.044962, 0.037843, 0.002168", \ "0.059313, 0.074012, 0.077906, 0.076127, 0.052445", \ "0.121841, 0.143174, 0.169505, 0.18173, 0.193629", \ "0.212833, 0.235422, 0.274283, 0.296982, 0.343816"); } fall_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.025252, 0.049961, 0.081, 0.096, 0.1536", \ "0.037379, 0.0648, 0.0948, 0.117, 0.1728", \ "0.057307, 0.0822, 0.1146, 0.1368, 0.2046", \ "0.1332, 0.144, 0.1788, 0.2058, 0.2928", \ "0.252, 0.2556, 0.279, 0.3072, 0.4002"); } cell_rise(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.053827, 0.090888, 0.133161, 0.166997, 0.264866", \ "0.067464, 0.10657, 0.161276, 0.195685, 0.302267", \ "0.089222, 0.133733, 0.196269, 0.235206, 0.35182", \ "0.174217, 0.217849, 0.306733, 0.361281, 0.50781", \ "0.300777, 0.343074, 0.433282, 0.502219, 0.692285"); } rise_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.038295, 0.0738, 0.0972, 0.1008, 0.1476", \ "0.05811, 0.0834, 0.1116, 0.1308, 0.174", \ "0.0864, 0.102, 0.1446, 0.1656, 0.2214", \ "0.2022, 0.207, 0.2448, 0.279, 0.3666", \ "0.3792, 0.3786, 0.3942, 0.4224, 0.5364"); } } timing() { related_pin : "B"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.030722, 0.034691, 0.027547, 0.022497, -0.007891", \ "0.04353, 0.052352, 0.058464, 0.056301, 0.034194", \ "0.060204, 0.08031, 0.09353, 0.097676, 0.089812", \ "0.123247, 0.154435, 0.197787, 0.216233, 0.247288", \ "0.214218, 0.245642, 0.31052, 0.346173, 0.417032"); } fall_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.03134, 0.0672, 0.0882, 0.1032, 0.1488", \ "0.038445, 0.0696, 0.0984, 0.1206, 0.1824", \ "0.05896, 0.0882, 0.1254, 0.1482, 0.222", \ "0.1332, 0.15, 0.201, 0.2346, 0.3294", \ "0.252, 0.2562, 0.2928, 0.3342, 0.453"); } cell_rise(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.045793, 0.070459, 0.110903, 0.134724, 0.213257", \ "0.058061, 0.09551, 0.138201, 0.168916, 0.257647", \ "0.0816, 0.122132, 0.178125, 0.213621, 0.314956", \ "0.166583, 0.208768, 0.294841, 0.346518, 0.483296", \ "0.294084, 0.335175, 0.424091, 0.492226, 0.67506"); } rise_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.033941, 0.0678, 0.084, 0.1026, 0.1422", \ "0.051455, 0.0798, 0.1092, 0.1218, 0.1722", \ "0.078, 0.096, 0.1368, 0.1608, 0.2172", \ "0.1926, 0.1974, 0.237, 0.2736, 0.3624", \ "0.369, 0.3696, 0.387, 0.4146, 0.5334"); } } internal_power() { related_pin : "A"; fall_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.010032, 0.006113, 0.007211, 0.019388, 0.061254", \ "0.009375, 0.006717, 0.005324, 0.016391, 0.056772", \ "0.009041, 0.007682, 0.003309, 0.013056, 0.05095", \ "0.008135, 0.007795, 0.000701, 0.006495, 0.037106", \ "0.007774, 0.007571, 0.002795, 0.002532, 0.026865"); } rise_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.044515, 0.051923, 0.065621, 0.078039, 0.12025", \ "0.045446, 0.0506, 0.064109, 0.075644, 0.117275", \ "0.045658, 0.049805, 0.061891, 0.072736, 0.11295", \ "0.04651, 0.047725, 0.056845, 0.066045, 0.101402", \ "0.046968, 0.047565, 0.053711, 0.060733, 0.090902"); } } internal_power() { related_pin : "B"; fall_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.009782, 0.004814, 0.009821, 0.021834, 0.062952", \ "0.009413, 0.005752, 0.007389, 0.018537, 0.058347", \ "0.008958, 0.006344, 0.004695, 0.014766, 0.05239", \ "0.008019, 0.007148, 0.000149, 0.00726, 0.037972", \ "0.00768, 0.00724, 0.002621, 0.002774, 0.027187"); } rise_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.03356, 0.040104, 0.053535, 0.065719, 0.106691", \ "0.033477, 0.039273, 0.051799, 0.062943, 0.102839", \ "0.034205, 0.038195, 0.049476, 0.059868, 0.098022", \ "0.036401, 0.036373, 0.044702, 0.053256, 0.086446", \ "0.037565, 0.037037, 0.042043, 0.048458, 0.076596"); } } } } /* ---------------- * * Design : NAND3X1 * * ---------------- */ cell (NAND3X1) { area : 36; cell_leakage_power : 0.0560872; pin(A) { direction : input; capacitance : 0.0158812; rise_capacitance : 0.0158812; fall_capacitance : 0.0154645; } pin(B) { direction : input; capacitance : 0.0159247; rise_capacitance : 0.0159247; fall_capacitance : 0.0155495; } pin(C) { direction : input; capacitance : 0.0164926; rise_capacitance : 0.0164758; fall_capacitance : 0.0164926; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.490658; function : "(!((A B) C))"; timing() { related_pin : "A"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.04116, 0.040614, 0.023919, 0.003135, -0.064874", \ "0.049935, 0.052803, 0.04061, 0.0249, -0.035024", \ "0.065293, 0.074215, 0.066043, 0.056796, 0.007393", \ "0.124514, 0.134562, 0.144799, 0.145727, 0.128775", \ "0.208279, 0.220458, 0.239093, 0.247928, 0.259065"); } fall_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.02816, 0.050762, 0.0792, 0.1002, 0.1632", \ "0.03958, 0.0606, 0.087, 0.1092, 0.177", \ "0.055365, 0.0738, 0.1062, 0.1296, 0.195", \ "0.1314, 0.138, 0.1674, 0.1914, 0.2688", \ "0.2448, 0.246, 0.2676, 0.288, 0.366"); } cell_rise(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.077, 0.119013, 0.180545, 0.222936, 0.354109", \ "0.090156, 0.136337, 0.20562, 0.249079, 0.37915", \ "0.1133, 0.158718, 0.234505, 0.282237, 0.421754", \ "0.199333, 0.243004, 0.335391, 0.396853, 0.563156", \ "0.326751, 0.369094, 0.459816, 0.530231, 0.735888"); } rise_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.059051, 0.078, 0.1158, 0.129, 0.1692", \ "0.081, 0.0942, 0.1332, 0.1488, 0.195", \ "0.1062, 0.1188, 0.1614, 0.1842, 0.2406", \ "0.2256, 0.2274, 0.2568, 0.2922, 0.3798", \ "0.4026, 0.4026, 0.4152, 0.4386, 0.5466"); } } timing() { related_pin : "B"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.038822, 0.040187, 0.027228, 0.013603, -0.036291", \ "0.0494, 0.054505, 0.049118, 0.040383, -0.001952", \ "0.064463, 0.078196, 0.079944, 0.075989, 0.04532", \ "0.122908, 0.142917, 0.168173, 0.17767, 0.182216", \ "0.208718, 0.228463, 0.268061, 0.289581, 0.329475"); } fall_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.029743, 0.053801, 0.0918, 0.1074, 0.168", \ "0.042422, 0.0696, 0.0984, 0.123, 0.1872", \ "0.058678, 0.081, 0.1194, 0.1416, 0.2142", \ "0.132, 0.1434, 0.1812, 0.2112, 0.2964", \ "0.2442, 0.2484, 0.276, 0.3066, 0.4002"); } cell_rise(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.066118, 0.104122, 0.160287, 0.196007, 0.307907", \ "0.080033, 0.121617, 0.180486, 0.220316, 0.338661", \ "0.101665, 0.146495, 0.215252, 0.259065, 0.385102", \ "0.188061, 0.230673, 0.320771, 0.378484, 0.534861", \ "0.315536, 0.356535, 0.446461, 0.516294, 0.714324"); } rise_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.052328, 0.0756, 0.0984, 0.1188, 0.153", \ "0.063, 0.0834, 0.123, 0.141, 0.1854", \ "0.0936, 0.1086, 0.1542, 0.1716, 0.2262", \ "0.213, 0.216, 0.2496, 0.2826, 0.3708", \ "0.39, 0.3894, 0.4026, 0.4284, 0.5388"); } } timing() { related_pin : "C"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.032603, 0.036382, 0.026123, 0.018569, -0.022063", \ "0.044522, 0.052032, 0.053463, 0.047809, 0.016461", \ "0.059652, 0.07628, 0.085372, 0.085773, 0.067297", \ "0.118645, 0.14708, 0.183081, 0.19771, 0.215072", \ "0.202474, 0.232142, 0.290379, 0.320385, 0.375619"); } fall_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.034546, 0.0696, 0.0912, 0.105, 0.1602", \ "0.041983, 0.072, 0.1032, 0.1242, 0.1848", \ "0.06, 0.087, 0.1266, 0.1476, 0.2214", \ "0.1326, 0.1488, 0.1974, 0.228, 0.3228", \ "0.2454, 0.249, 0.2898, 0.3288, 0.4398"); } cell_rise(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.051521, 0.085749, 0.126629, 0.157693, 0.248486", \ "0.064751, 0.104177, 0.154098, 0.186653, 0.288056", \ "0.088648, 0.130864, 0.190543, 0.229086, 0.342298", \ "0.175149, 0.216689, 0.304292, 0.358342, 0.504462", \ "0.303176, 0.343349, 0.432222, 0.500994, 0.691157"); } rise_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.037306, 0.0714, 0.0918, 0.099, 0.1446", \ "0.053744, 0.081, 0.108, 0.1272, 0.1764", \ "0.0822, 0.0984, 0.1398, 0.1608, 0.219", \ "0.198, 0.2022, 0.2406, 0.2748, 0.3612", \ "0.3756, 0.3744, 0.3894, 0.417, 0.531"); } } internal_power() { related_pin : "A"; fall_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.010223, 0.007778, 0.004387, 0.015797, 0.060932", \ "0.009631, 0.007971, 0.003056, 0.013509, 0.057066", \ "0.008955, 0.008071, 0.000958, 0.011261, 0.052029", \ "0.008113, 0.007956, 0.001637, 0.006035, 0.039606", \ "0.007727, 0.007726, 0.003233, 0.002633, 0.029842"); } rise_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.078173, 0.0838, 0.098208, 0.112082, 0.158646", \ "0.078445, 0.083496, 0.09757, 0.110399, 0.156182", \ "0.07885, 0.082611, 0.096067, 0.107872, 0.152181", \ "0.08051, 0.081852, 0.091836, 0.101879, 0.141566", \ "0.081202, 0.082003, 0.088784, 0.096782, 0.131078"); } } internal_power() { related_pin : "B"; fall_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.009754, 0.006571, 0.005699, 0.018144, 0.061969", \ "0.009288, 0.006691, 0.004204, 0.015552, 0.057728", \ "0.008783, 0.006458, 0.002528, 0.01268, 0.052145", \ "0.00802, 0.00686, 0.000893, 0.006527, 0.038603", \ "0.007622, 0.007098, 0.002825, 0.002708, 0.028343"); } rise_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.062656, 0.067136, 0.082427, 0.094475, 0.139019", \ "0.062127, 0.06667, 0.080442, 0.09237, 0.136319", \ "0.063336, 0.066255, 0.078446, 0.090276, 0.132354", \ "0.06511, 0.065218, 0.07431, 0.083944, 0.121697", \ "0.066163, 0.065839, 0.071643, 0.079074, 0.111649"); } } internal_power() { related_pin : "C"; fall_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.010951, 0.005335, 0.009988, 0.022814, 0.066842", \ "0.009889, 0.006175, 0.007602, 0.019637, 0.062399", \ "0.00932, 0.006698, 0.005089, 0.015884, 0.056505", \ "0.008196, 0.007286, 0.000252, 0.00831, 0.041775", \ "0.007777, 0.007328, 0.002254, 0.00367, 0.030458"); } rise_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.042867, 0.050017, 0.064505, 0.076887, 0.121021", \ "0.043975, 0.049037, 0.062676, 0.074655, 0.117504", \ "0.044988, 0.048248, 0.060394, 0.071801, 0.112996", \ "0.048348, 0.04748, 0.056002, 0.065379, 0.101725", \ "0.050303, 0.048868, 0.053668, 0.060673, 0.091712"); } } } } /* --------------- * * Design : NOR2X1 * * --------------- */ cell (NOR2X1) { area : 24; cell_leakage_power : 0.035234; pin(A) { direction : input; capacitance : 0.0144193; rise_capacitance : 0.0139227; fall_capacitance : 0.0144193; } pin(B) { direction : input; capacitance : 0.0150643; rise_capacitance : 0.0150469; fall_capacitance : 0.0150643; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.499994; function : "(!(A+B))"; timing() { related_pin : "A"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.052024, 0.072786, 0.102719, 0.116867, 0.162886", \ "0.063687, 0.092509, 0.123179, 0.144568, 0.197323", \ "0.082815, 0.115218, 0.159103, 0.181266, 0.244335", \ "0.158166, 0.194702, 0.262053, 0.298892, 0.389987", \ "0.269742, 0.305373, 0.380148, 0.433551, 0.561665"); } fall_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.036399, 0.0738, 0.1002, 0.1128, 0.1722", \ "0.05475, 0.081, 0.1146, 0.135, 0.201", \ "0.0756, 0.0948, 0.138, 0.1656, 0.2394", \ "0.165, 0.1704, 0.2184, 0.255, 0.3552", \ "0.3054, 0.3054, 0.3306, 0.3654, 0.492"); } cell_rise(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.048757, 0.062084, 0.070199, 0.073994, 0.084854", \ "0.062221, 0.079679, 0.092833, 0.102291, 0.123883", \ "0.086501, 0.104512, 0.127895, 0.141506, 0.175016", \ "0.170492, 0.192451, 0.23367, 0.257634, 0.32148", \ "0.29667, 0.318563, 0.367261, 0.400499, 0.488101"); } rise_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.032304, 0.059129, 0.0888, 0.1104, 0.1554", \ "0.049568, 0.075, 0.1026, 0.126, 0.1812", \ "0.0816, 0.0948, 0.1284, 0.1518, 0.2148", \ "0.1962, 0.1998, 0.2292, 0.2544, 0.3288", \ "0.3732, 0.3738, 0.39, 0.411, 0.4908"); } } timing() { related_pin : "B"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.038401, 0.051255, 0.067423, 0.073413, 0.087652", \ "0.05399, 0.073396, 0.095386, 0.108254, 0.132269", \ "0.074059, 0.102031, 0.133828, 0.151972, 0.190359", \ "0.148582, 0.184191, 0.24634, 0.278312, 0.355503", \ "0.261225, 0.295056, 0.368683, 0.419628, 0.537104"); } fall_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.028747, 0.057397, 0.0822, 0.1038, 0.1494", \ "0.043383, 0.075, 0.105, 0.1242, 0.1842", \ "0.059564, 0.087, 0.129, 0.1548, 0.2262", \ "0.1536, 0.1602, 0.2112, 0.2484, 0.345", \ "0.2934, 0.2928, 0.3198, 0.357, 0.4842"); } cell_rise(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.044051, 0.061971, 0.08092, 0.095749, 0.131115", \ "0.058156, 0.083838, 0.112761, 0.129467, 0.17689", \ "0.081817, 0.112785, 0.15217, 0.174951, 0.236316", \ "0.166398, 0.201667, 0.271342, 0.309874, 0.406624", \ "0.293225, 0.328511, 0.404142, 0.460926, 0.599617"); } rise_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.037234, 0.072, 0.0924, 0.1056, 0.147", \ "0.055595, 0.0846, 0.1068, 0.1278, 0.1806", \ "0.0816, 0.105, 0.144, 0.1626, 0.225", \ "0.1962, 0.2016, 0.246, 0.2802, 0.3648", \ "0.3726, 0.3738, 0.3954, 0.4266, 0.5394"); } } internal_power() { related_pin : "A"; fall_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.018356, 0.0131, 0.001603, 0.014903, 0.06085", \ "0.018158, 0.013817, 0.000223, 0.01217, 0.057082", \ "0.01762, 0.014309, 0.002784, 0.00876, 0.051711", \ "0.017041, 0.01611, 0.008021, 0.000741, 0.037068", \ "0.016886, 0.016278, 0.011013, 0.004623, 0.024639"); } rise_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.066001, 0.069582, 0.082161, 0.09472, 0.141145", \ "0.065447, 0.06803, 0.080177, 0.091723, 0.136925", \ "0.066374, 0.067808, 0.078361, 0.088556, 0.131286", \ "0.067107, 0.067859, 0.074216, 0.082288, 0.117562", \ "0.067494, 0.066515, 0.072152, 0.078228, 0.107165"); } } internal_power() { related_pin : "B"; fall_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.018437, 0.013232, 0.001761, 0.013882, 0.056136", \ "0.017733, 0.013814, 0.000637, 0.010912, 0.051918", \ "0.016174, 0.014633, 0.003143, 0.007407, 0.046348", \ "0.013581, 0.01386, 0.007313, 0.000341, 0.03265", \ "0.012265, 0.012835, 0.009099, 0.003692, 0.02204"); } rise_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.042481, 0.049241, 0.064378, 0.076077, 0.118202", \ "0.043117, 0.048688, 0.062041, 0.073351, 0.113998", \ "0.042961, 0.047646, 0.059, 0.069816, 0.108553", \ "0.044725, 0.045628, 0.054048, 0.062479, 0.095792", \ "0.045588, 0.045761, 0.051097, 0.057527, 0.085382"); } } } } /* --------------- * * Design : NOR3X1 * * --------------- */ cell (NOR3X1) { area : 64; cell_leakage_power : 0.0544821; pin(A) { direction : input; capacitance : 0.019824; rise_capacitance : 0.018966; fall_capacitance : 0.019824; } pin(B) { direction : input; capacitance : 0.019861; rise_capacitance : 0.0191157; fall_capacitance : 0.019861; } pin(C) { direction : input; capacitance : 0.0207948; rise_capacitance : 0.0207948; fall_capacitance : 0.020788; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.496256; function : "(!((A+B)+C))"; timing() { related_pin : "A"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.076871, 0.10606, 0.158872, 0.183447, 0.266465", \ "0.088527, 0.125424, 0.174443, 0.208561, 0.294195", \ "0.111325, 0.148061, 0.206591, 0.238597, 0.331966", \ "0.189341, 0.225103, 0.29955, 0.34401, 0.460418", \ "0.302144, 0.337536, 0.412874, 0.4702, 0.618393"); } fall_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.058223, 0.081, 0.1194, 0.144, 0.207", \ "0.0774, 0.09, 0.1374, 0.1578, 0.2298", \ "0.0984, 0.111, 0.159, 0.186, 0.2628", \ "0.1926, 0.1968, 0.2334, 0.2718, 0.3708", \ "0.3324, 0.3318, 0.3528, 0.3828, 0.5046"); } cell_rise(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.069909, 0.073929, 0.08023, 0.076139, 0.052404", \ "0.085164, 0.09309, 0.099796, 0.096392, 0.083598", \ "0.104666, 0.115656, 0.125517, 0.129858, 0.12765", \ "0.187664, 0.200206, 0.223859, 0.234315, 0.259507", \ "0.312311, 0.329068, 0.354596, 0.371168, 0.413719"); } rise_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.045431, 0.063, 0.0876, 0.1122, 0.183", \ "0.0648, 0.0744, 0.1056, 0.1236, 0.1968", \ "0.0912, 0.1008, 0.1278, 0.1458, 0.2226", \ "0.2052, 0.2088, 0.231, 0.2508, 0.3216", \ "0.3798, 0.3798, 0.3936, 0.4098, 0.4764"); } } timing() { related_pin : "B"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.068849, 0.095688, 0.127268, 0.154714, 0.210724", \ "0.079996, 0.108585, 0.153332, 0.17427, 0.240398", \ "0.100051, 0.135085, 0.181355, 0.210878, 0.284047", \ "0.176406, 0.211894, 0.281169, 0.321477, 0.423449", \ "0.289198, 0.323504, 0.397401, 0.453334, 0.589861"); } fall_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.049642, 0.0732, 0.1068, 0.1236, 0.183", \ "0.058798, 0.081, 0.1206, 0.1452, 0.2052", \ "0.084, 0.0972, 0.1446, 0.1704, 0.2454", \ "0.1758, 0.1788, 0.2214, 0.2604, 0.357", \ "0.3144, 0.3156, 0.3366, 0.3696, 0.492"); } cell_rise(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.064655, 0.079822, 0.083453, 0.086884, 0.097565", \ "0.082182, 0.093537, 0.105767, 0.114885, 0.134595", \ "0.1018, 0.120256, 0.140036, 0.152587, 0.184222", \ "0.185832, 0.205941, 0.246301, 0.269893, 0.331185", \ "0.310591, 0.331576, 0.379585, 0.412394, 0.498942"); } rise_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.046543, 0.0708, 0.1026, 0.1218, 0.1818", \ "0.0642, 0.0834, 0.1134, 0.138, 0.2046", \ "0.0918, 0.1092, 0.1416, 0.1662, 0.2334", \ "0.2052, 0.2118, 0.2436, 0.2676, 0.3438", \ "0.3798, 0.3798, 0.3972, 0.42, 0.5022"); } } timing() { related_pin : "C"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.049253, 0.065453, 0.085113, 0.09859, 0.126765", \ "0.061801, 0.089237, 0.113584, 0.128372, 0.167715", \ "0.083005, 0.113224, 0.149947, 0.170137, 0.221808", \ "0.159204, 0.193903, 0.258385, 0.292894, 0.379522", \ "0.272977, 0.30599, 0.378974, 0.431398, 0.556954"); } fall_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.028055, 0.0648, 0.0918, 0.1056, 0.1566", \ "0.047042, 0.0744, 0.1002, 0.1254, 0.1842", \ "0.0672, 0.0882, 0.129, 0.1554, 0.2268", \ "0.1572, 0.1644, 0.2094, 0.2454, 0.3444", \ "0.2976, 0.297, 0.3216, 0.3558, 0.4812"); } cell_rise(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.048038, 0.060277, 0.081576, 0.094022, 0.121654", \ "0.061349, 0.083504, 0.110641, 0.124847, 0.163462", \ "0.084246, 0.111371, 0.146871, 0.167459, 0.218769", \ "0.168268, 0.200077, 0.262494, 0.296121, 0.38056", \ "0.294847, 0.325559, 0.394508, 0.445322, 0.567066"); } rise_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.047776, 0.0684, 0.1008, 0.114, 0.1614", \ "0.0612, 0.0882, 0.1146, 0.1338, 0.1878", \ "0.0906, 0.1116, 0.1494, 0.1686, 0.2322", \ "0.2052, 0.2112, 0.2556, 0.2856, 0.3654", \ "0.3798, 0.3798, 0.402, 0.4338, 0.5394"); } } internal_power() { related_pin : "A"; fall_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.025205, 0.02152, 0.006799, 0.007184, 0.058865", \ "0.024991, 0.022186, 0.008507, 0.005074, 0.055661", \ "0.024643, 0.022794, 0.010657, 0.002115, 0.050769", \ "0.024847, 0.023754, 0.015317, 0.005432, 0.036517", \ "0.024637, 0.02407, 0.018302, 0.010944, 0.023455"); } rise_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.129942, 0.128505, 0.139221, 0.151344, 0.201205", \ "0.129007, 0.129143, 0.137979, 0.149512, 0.197738", \ "0.130109, 0.129464, 0.136986, 0.147122, 0.192639", \ "0.129762, 0.129999, 0.133531, 0.141899, 0.180073", \ "0.130143, 0.128216, 0.132427, 0.138908, 0.170323"); } } internal_power() { related_pin : "B"; fall_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.025223, 0.020958, 0.007024, 0.006114, 0.053913", \ "0.024242, 0.021517, 0.00862, 0.004159, 0.050783", \ "0.023324, 0.02192, 0.010464, 0.001305, 0.046197", \ "0.021475, 0.021725, 0.014491, 0.005407, 0.033118", \ "0.020745, 0.020975, 0.01653, 0.009965, 0.021452"); } rise_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.098522, 0.098636, 0.110707, 0.123703, 0.171273", \ "0.097781, 0.098547, 0.109313, 0.121495, 0.167171", \ "0.098846, 0.098619, 0.107854, 0.118412, 0.1618", \ "0.09919, 0.09854, 0.104673, 0.112699, 0.148701", \ "0.09958, 0.098941, 0.102927, 0.10903, 0.138547"); } } internal_power() { related_pin : "C"; fall_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.027552, 0.020566, 0.006692, 0.006538, 0.05257", \ "0.025623, 0.021375, 0.008487, 0.003916, 0.048747", \ "0.023652, 0.022761, 0.010481, 0.000852, 0.043534", \ "0.019502, 0.020434, 0.014151, 0.005826, 0.030195", \ "0.01708, 0.018356, 0.015231, 0.009413, 0.019481"); } rise_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.061416, 0.068335, 0.085477, 0.098636, 0.144568", \ "0.062746, 0.067937, 0.08286, 0.095599, 0.140434", \ "0.063382, 0.066171, 0.080249, 0.092331, 0.135239", \ "0.065345, 0.065867, 0.075162, 0.08445, 0.121518", \ "0.066193, 0.066184, 0.07213, 0.079278, 0.11033"); } } } } /* ---------------- * * Design : OAI21X1 * * ---------------- */ cell (OAI21X1) { area : 23; cell_leakage_power : 0.0480948; pin(A) { direction : input; capacitance : 0.017346; rise_capacitance : 0.0170613; fall_capacitance : 0.017346; } pin(B) { direction : input; capacitance : 0.0182038; rise_capacitance : 0.0182038; fall_capacitance : 0.0180091; } pin(C) { direction : input; capacitance : 0.0129138; rise_capacitance : 0.0129026; fall_capacitance : 0.0129138; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.494927; function : "(!((A+B) C))"; timing() { related_pin : "A"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.050325, 0.057085, 0.066352, 0.068086, 0.066582", \ "0.060667, 0.071919, 0.082473, 0.088237, 0.094215", \ "0.078659, 0.093795, 0.11004, 0.119249, 0.133857", \ "0.139451, 0.160094, 0.193758, 0.21236, 0.252028", \ "0.233183, 0.251846, 0.294996, 0.321324, 0.387541"); } fall_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.035583, 0.0624, 0.09, 0.111, 0.171", \ "0.053443, 0.075, 0.1068, 0.1272, 0.1914", \ "0.066, 0.087, 0.123, 0.1476, 0.2196", \ "0.1452, 0.153, 0.186, 0.213, 0.2988", \ "0.2658, 0.2676, 0.2892, 0.3144, 0.4044"); } cell_rise(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.06636, 0.082462, 0.109861, 0.129336, 0.185817", \ "0.079896, 0.098822, 0.128611, 0.15018, 0.214932", \ "0.101528, 0.123397, 0.157357, 0.182618, 0.25519", \ "0.187502, 0.2091, 0.25695, 0.28718, 0.378424", \ "0.314294, 0.336292, 0.387248, 0.424793, 0.531463"); } rise_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.047893, 0.0708, 0.0936, 0.1122, 0.1578", \ "0.0684, 0.0846, 0.1152, 0.129, 0.1812", \ "0.0924, 0.1068, 0.1374, 0.1566, 0.2148", \ "0.2124, 0.2166, 0.2418, 0.2646, 0.3288", \ "0.3894, 0.3882, 0.4026, 0.4212, 0.4944"); } } timing() { related_pin : "B"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.040373, 0.047321, 0.038756, 0.033316, 0.00663", \ "0.05186, 0.059625, 0.063447, 0.059755, 0.041286", \ "0.06988, 0.083375, 0.091961, 0.095018, 0.087812", \ "0.132425, 0.151768, 0.181549, 0.195974, 0.221793", \ "0.225913, 0.244307, 0.284934, 0.309451, 0.36621"); } fall_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.025325, 0.0537, 0.0852, 0.1068, 0.1518", \ "0.039169, 0.0654, 0.0924, 0.1188, 0.1758", \ "0.058635, 0.0804, 0.114, 0.135, 0.2028", \ "0.1344, 0.1458, 0.1788, 0.2064, 0.2916", \ "0.2556, 0.2574, 0.2808, 0.3048, 0.3972"); } cell_rise(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.061377, 0.093315, 0.129089, 0.160577, 0.243063", \ "0.076361, 0.108471, 0.155686, 0.183668, 0.274717", \ "0.097182, 0.134979, 0.187382, 0.221318, 0.321338", \ "0.183636, 0.21995, 0.295982, 0.342008, 0.46732", \ "0.310652, 0.346271, 0.424503, 0.484776, 0.644796"); } rise_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.052219, 0.0798, 0.1026, 0.1104, 0.153", \ "0.0636, 0.0912, 0.1188, 0.135, 0.1824", \ "0.0936, 0.1116, 0.1476, 0.1698, 0.2244", \ "0.2124, 0.2166, 0.2544, 0.2868, 0.363", \ "0.3894, 0.3888, 0.4068, 0.4338, 0.5382"); } } timing() { related_pin : "C"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.037624, 0.043049, 0.044183, 0.040205, 0.013363", \ "0.048078, 0.061126, 0.067591, 0.067291, 0.048412", \ "0.063468, 0.08402, 0.100195, 0.104135, 0.097648", \ "0.11881, 0.151859, 0.195555, 0.213795, 0.242847", \ "0.202257, 0.234917, 0.299596, 0.334852, 0.402116"); } fall_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.033797, 0.0651, 0.0882, 0.1038, 0.1638", \ "0.044453, 0.0747, 0.1071, 0.1269, 0.1881", \ "0.059372, 0.0882, 0.1284, 0.1518, 0.2259", \ "0.1263, 0.1419, 0.1938, 0.2286, 0.3258", \ "0.234, 0.2373, 0.279, 0.3204, 0.4395"); } cell_rise(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.048662, 0.078567, 0.117933, 0.144234, 0.227348", \ "0.06066, 0.098848, 0.144445, 0.176018, 0.269238", \ "0.083527, 0.125211, 0.183347, 0.219699, 0.324741", \ "0.169097, 0.211738, 0.298397, 0.350866, 0.490398", \ "0.297295, 0.338311, 0.427365, 0.49554, 0.680418"); } rise_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.044344, 0.0792, 0.105, 0.1224, 0.1719", \ "0.06228, 0.0912, 0.1248, 0.1425, 0.1989", \ "0.0903, 0.1077, 0.1518, 0.1782, 0.2391", \ "0.2058, 0.2112, 0.2499, 0.2853, 0.3777", \ "0.3831, 0.3834, 0.4002, 0.4284, 0.5454"); } } internal_power() { related_pin : "A"; fall_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.018723, 0.014238, 0.001983, 0.018123, 0.07526", \ "0.018122, 0.014881, 0.000135, 0.015197, 0.070956", \ "0.017686, 0.015479, 0.002313, 0.011625, 0.064988", \ "0.016929, 0.015839, 0.007254, 0.003499, 0.048592", \ "0.016853, 0.016207, 0.010085, 0.002104, 0.034591"); } rise_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.089044, 0.09085, 0.108868, 0.125145, 0.183339", \ "0.088461, 0.090928, 0.107231, 0.122356, 0.179741", \ "0.089179, 0.090498, 0.104539, 0.119015, 0.174668", \ "0.089631, 0.088873, 0.099997, 0.111464, 0.159659", \ "0.090342, 0.089451, 0.097192, 0.106057, 0.146696"); } } internal_power() { related_pin : "B"; fall_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.019052, 0.014394, 0.000774, 0.015232, 0.066066", \ "0.017746, 0.014642, 0.000829, 0.012586, 0.06178", \ "0.016049, 0.014626, 0.003057, 0.009235, 0.056008", \ "0.01347, 0.014441, 0.006801, 0.002407, 0.041314", \ "0.012413, 0.013303, 0.008302, 0.001594, 0.029812"); } rise_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.066762, 0.072538, 0.090248, 0.104895, 0.15546", \ "0.065332, 0.07199, 0.088088, 0.10237, 0.15216", \ "0.066238, 0.070774, 0.085574, 0.098853, 0.147574", \ "0.06737, 0.068716, 0.07991, 0.091097, 0.13453", \ "0.068412, 0.068914, 0.076394, 0.085061, 0.12233"); } } internal_power() { related_pin : "C"; fall_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.008486, 0.004525, 0.009596, 0.021217, 0.062131", \ "0.008129, 0.005131, 0.00757, 0.018451, 0.05811", \ "0.007702, 0.00548, 0.005134, 0.015205, 0.052773", \ "0.007117, 0.006209, 0.00069, 0.00793, 0.039352", \ "0.006723, 0.006292, 0.001795, 0.003483, 0.028537"); } rise_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.04756, 0.054784, 0.06802, 0.079563, 0.120585", \ "0.048287, 0.05366, 0.066094, 0.077303, 0.116962", \ "0.048478, 0.052817, 0.063736, 0.074433, 0.112426", \ "0.050771, 0.050991, 0.059436, 0.068012, 0.101195", \ "0.052018, 0.051602, 0.05697, 0.063407, 0.09142"); } } } } /* ---------------- * * Design : OAI22X1 * * ---------------- */ cell (OAI22X1) { area : 40; cell_leakage_power : 0.0603119; pin(A) { direction : input; capacitance : 0.0173495; rise_capacitance : 0.0170835; fall_capacitance : 0.0173495; } pin(B) { direction : input; capacitance : 0.0182258; rise_capacitance : 0.0182258; fall_capacitance : 0.0180022; } pin(C) { direction : input; capacitance : 0.0179862; rise_capacitance : 0.0175055; fall_capacitance : 0.0179862; } pin(D) { direction : input; capacitance : 0.0186431; rise_capacitance : 0.0186431; fall_capacitance : 0.0186325; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.485105; function : "(!((A+B) (C+D)))"; timing() { related_pin : "A"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.06016, 0.073032, 0.084423, 0.088825, 0.095558", \ "0.069165, 0.086162, 0.100108, 0.108628, 0.118443", \ "0.083119, 0.102253, 0.126173, 0.135763, 0.154182", \ "0.139063, 0.163394, 0.202734, 0.223668, 0.266586", \ "0.220012, 0.245088, 0.296496, 0.326863, 0.397378"); } fall_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.045128, 0.0705, 0.1002, 0.1218, 0.1881", \ "0.053045, 0.078, 0.1122, 0.1341, 0.2043", \ "0.068801, 0.0912, 0.1257, 0.1542, 0.2283", \ "0.1386, 0.1482, 0.1875, 0.2157, 0.3045", \ "0.2445, 0.2484, 0.2748, 0.3051, 0.4032"); } cell_rise(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.077733, 0.095387, 0.125319, 0.146992, 0.211626", \ "0.090794, 0.111725, 0.14383, 0.167047, 0.236529", \ "0.11225, 0.13473, 0.171245, 0.19712, 0.273778", \ "0.198101, 0.220017, 0.268744, 0.299981, 0.394127", \ "0.32536, 0.346952, 0.397934, 0.436406, 0.545596"); } rise_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.065334, 0.0852, 0.1182, 0.1323, 0.186", \ "0.087, 0.1008, 0.1332, 0.1497, 0.2085", \ "0.1131, 0.1254, 0.1575, 0.1794, 0.2379", \ "0.2319, 0.2352, 0.2604, 0.2832, 0.3498", \ "0.4092, 0.4095, 0.4236, 0.4407, 0.5142"); } } timing() { related_pin : "B"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.05151, 0.060465, 0.063048, 0.061274, 0.042453", \ "0.061943, 0.074237, 0.082147, 0.082626, 0.07071", \ "0.076815, 0.094316, 0.108959, 0.114803, 0.112485", \ "0.132159, 0.155919, 0.191293, 0.208379, 0.238377", \ "0.213665, 0.238067, 0.287659, 0.315888, 0.37701"); } fall_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.036093, 0.061975, 0.0915, 0.1128, 0.1704", \ "0.046244, 0.0702, 0.1026, 0.1242, 0.1884", \ "0.062251, 0.0858, 0.12, 0.1422, 0.2157", \ "0.1308, 0.1395, 0.1812, 0.2097, 0.2982", \ "0.2352, 0.2379, 0.2673, 0.2979, 0.396"); } cell_rise(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.073247, 0.105332, 0.151373, 0.179464, 0.270525", \ "0.086142, 0.121936, 0.171264, 0.20496, 0.301166", \ "0.107653, 0.146587, 0.204129, 0.239319, 0.344187", \ "0.194237, 0.230621, 0.308492, 0.356446, 0.485377", \ "0.321779, 0.35694, 0.435344, 0.49608, 0.660458"); } rise_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.067236, 0.0966, 0.1254, 0.138, 0.1899", \ "0.0852, 0.1068, 0.1431, 0.1599, 0.2142", \ "0.1128, 0.1293, 0.1713, 0.1941, 0.2514", \ "0.2313, 0.2352, 0.2721, 0.3045, 0.3867", \ "0.4098, 0.4092, 0.4254, 0.4539, 0.5586"); } } timing() { related_pin : "C"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.05398, 0.07243, 0.092176, 0.099839, 0.122773", \ "0.06352, 0.085993, 0.108984, 0.123743, 0.147693", \ "0.077727, 0.106334, 0.137729, 0.151751, 0.186886", \ "0.134309, 0.168377, 0.221736, 0.247548, 0.307417", \ "0.217388, 0.251301, 0.319304, 0.359668, 0.44986"); } fall_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.041495, 0.0732, 0.1023, 0.1275, 0.1899", \ "0.053381, 0.0834, 0.1194, 0.1398, 0.2118", \ "0.072, 0.0948, 0.1371, 0.1641, 0.2397", \ "0.1401, 0.1506, 0.2013, 0.2367, 0.3324", \ "0.2466, 0.2508, 0.2865, 0.3255, 0.4416"); } cell_rise(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.059449, 0.075272, 0.094237, 0.111085, 0.154366", \ "0.074351, 0.090094, 0.11758, 0.13541, 0.185901", \ "0.096161, 0.117012, 0.147609, 0.168548, 0.229845", \ "0.182886, 0.204011, 0.249368, 0.27744, 0.362175", \ "0.310322, 0.33117, 0.381313, 0.417547, 0.519562"); } rise_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.053455, 0.0759, 0.1062, 0.1299, 0.1845", \ "0.0705, 0.0888, 0.1227, 0.1431, 0.2034", \ "0.099, 0.1128, 0.147, 0.168, 0.2313", \ "0.2163, 0.222, 0.2487, 0.2727, 0.3414", \ "0.3951, 0.3948, 0.4095, 0.4287, 0.5037"); } } timing() { related_pin : "D"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.04673, 0.058194, 0.06633, 0.069168, 0.063403", \ "0.055969, 0.073908, 0.089203, 0.093486, 0.094877", \ "0.0714, 0.096729, 0.118099, 0.128717, 0.140128", \ "0.12742, 0.160859, 0.20843, 0.23155, 0.275782", \ "0.211177, 0.244102, 0.310118, 0.347777, 0.427534"); } fall_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.038192, 0.063, 0.0969, 0.1149, 0.1716", \ "0.04292, 0.0765, 0.1071, 0.1314, 0.1932", \ "0.064449, 0.0891, 0.1275, 0.1521, 0.228", \ "0.1317, 0.1422, 0.1959, 0.2277, 0.3231", \ "0.2385, 0.2415, 0.2787, 0.3186, 0.4344"); } cell_rise(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.055444, 0.082719, 0.116205, 0.138642, 0.208765", \ "0.069406, 0.101469, 0.139643, 0.167417, 0.245163", \ "0.09181, 0.127057, 0.175951, 0.207243, 0.295839", \ "0.178669, 0.214068, 0.288041, 0.331864, 0.450015", \ "0.306614, 0.341553, 0.418676, 0.47777, 0.632508"); } rise_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.05714, 0.0876, 0.1119, 0.1308, 0.183", \ "0.071635, 0.1014, 0.1317, 0.1494, 0.2067", \ "0.0996, 0.1194, 0.1596, 0.1815, 0.2433", \ "0.2166, 0.222, 0.261, 0.2955, 0.3756", \ "0.3948, 0.3945, 0.414, 0.4416, 0.5484"); } } internal_power() { related_pin : "A"; fall_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.017562, 0.014759, 0.000335, 0.015012, 0.070477", \ "0.017111, 0.015126, 0.001669, 0.012611, 0.066817", \ "0.016697, 0.015541, 0.003658, 0.009814, 0.061505", \ "0.016252, 0.015715, 0.007546, 0.002529, 0.046659", \ "0.015931, 0.015886, 0.009905, 0.002384, 0.033457"); } rise_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.112422, 0.113974, 0.13104, 0.146958, 0.205294", \ "0.112574, 0.114271, 0.12979, 0.144487, 0.201913", \ "0.113257, 0.114203, 0.127288, 0.141996, 0.19699", \ "0.113691, 0.112943, 0.123627, 0.135019, 0.182798", \ "0.114525, 0.113647, 0.121258, 0.130044, 0.170212"); } } internal_power() { related_pin : "B"; fall_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.017144, 0.014619, 0.001271, 0.012193, 0.061306", \ "0.016197, 0.014525, 0.002611, 0.010221, 0.057711", \ "0.014629, 0.014265, 0.004191, 0.007549, 0.052747", \ "0.012586, 0.013349, 0.006915, 0.001708, 0.039693", \ "0.011452, 0.01241, 0.007994, 0.001671, 0.028757"); } rise_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.089981, 0.096048, 0.11241, 0.12728, 0.177386", \ "0.089727, 0.094778, 0.110532, 0.124845, 0.174326", \ "0.090205, 0.094819, 0.108963, 0.121594, 0.169905", \ "0.091397, 0.092843, 0.103634, 0.114649, 0.157667", \ "0.092604, 0.093016, 0.100361, 0.108956, 0.145889"); } } internal_power() { related_pin : "C"; fall_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.017478, 0.012462, 0.004997, 0.020509, 0.075758", \ "0.017135, 0.012897, 0.003169, 0.017899, 0.072007", \ "0.016892, 0.013031, 0.000911, 0.01465, 0.066586", \ "0.016253, 0.014443, 0.005125, 0.005913, 0.051036", \ "0.015931, 0.015161, 0.008589, 0.000735, 0.03691"); } rise_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.093156, 0.095361, 0.111723, 0.127152, 0.182382", \ "0.092831, 0.095022, 0.110357, 0.124792, 0.178611", \ "0.093798, 0.095787, 0.108621, 0.121669, 0.173221", \ "0.096133, 0.095927, 0.104496, 0.11501, 0.158922", \ "0.09738, 0.095435, 0.102503, 0.110385, 0.147241"); } } internal_power() { related_pin : "D"; fall_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.016831, 0.012249, 0.004293, 0.018126, 0.067473", \ "0.015778, 0.012371, 0.002509, 0.015742, 0.063722", \ "0.014726, 0.012727, 0.00071, 0.012528, 0.058456", \ "0.012623, 0.01242, 0.004521, 0.005026, 0.044403", \ "0.011431, 0.011595, 0.006595, 0.000886, 0.032474"); } rise_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.069807, 0.077626, 0.093855, 0.107715, 0.156254", \ "0.069992, 0.077089, 0.091752, 0.105239, 0.152541", \ "0.07069, 0.076043, 0.089621, 0.10225, 0.147737", \ "0.07366, 0.074231, 0.084359, 0.094964, 0.135221", \ "0.075428, 0.07496, 0.081679, 0.089612, 0.12401"); } } } } /* -------------- * * Design : OR2X1 * * -------------- */ cell (OR2X1) { area : 32; cell_leakage_power : 0.0748155; pin(A) { direction : input; capacitance : 0.0150616; rise_capacitance : 0.0150616; fall_capacitance : 0.0150113; } pin(B) { direction : input; capacitance : 0.0144258; rise_capacitance : 0.0139523; fall_capacitance : 0.0144258; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.496203; function : "(A+B)"; timing() { related_pin : "A"; timing_sense : positive_unate; cell_rise(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.074088, 0.088543, 0.114376, 0.128922, 0.160855", \ "0.087117, 0.103311, 0.131779, 0.14954, 0.180326", \ "0.108726, 0.125541, 0.16074, 0.174611, 0.206457", \ "0.194003, 0.212138, 0.244354, 0.255317, 0.293178", \ "0.319717, 0.338201, 0.370455, 0.38497, 0.420931"); } rise_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0246, 0.031921, 0.039648, 0.052834, 0.059059", \ "0.041267, 0.047301, 0.059193, 0.0606, 0.0756", \ "0.0726, 0.0714, 0.0822, 0.0864, 0.0948", \ "0.1878, 0.1884, 0.1878, 0.1914, 0.1968", \ "0.3666, 0.366, 0.3672, 0.3678, 0.3708"); } cell_fall(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.076098, 0.093906, 0.122996, 0.138911, 0.191344", \ "0.093089, 0.112754, 0.143254, 0.161889, 0.206502", \ "0.111772, 0.135006, 0.166691, 0.18567, 0.234", \ "0.1872, 0.2083, 0.240171, 0.262003, 0.315947", \ "0.297543, 0.318547, 0.352616, 0.37448, 0.42893"); } fall_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.027491, 0.035329, 0.047022, 0.053044, 0.0636", \ "0.044071, 0.051605, 0.05612, 0.059508, 0.069", \ "0.0672, 0.0672, 0.0756, 0.0786, 0.0888", \ "0.1506, 0.1542, 0.1578, 0.1572, 0.1644", \ "0.2916, 0.291, 0.294, 0.2952, 0.2994"); } } timing() { related_pin : "B"; timing_sense : positive_unate; cell_rise(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.086234, 0.112975, 0.148468, 0.168584, 0.226102", \ "0.100057, 0.127593, 0.169077, 0.188679, 0.248868", \ "0.122236, 0.149125, 0.191451, 0.212179, 0.2719", \ "0.207921, 0.234475, 0.273261, 0.298511, 0.359211", \ "0.335749, 0.368066, 0.400532, 0.424288, 0.485293"); } rise_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.027031, 0.032091, 0.046796, 0.046293, 0.056707", \ "0.04331, 0.044407, 0.058669, 0.0606, 0.0708", \ "0.075, 0.075, 0.0858, 0.0876, 0.0888", \ "0.189, 0.189, 0.1896, 0.1908, 0.195", \ "0.3654, 0.3666, 0.3666, 0.3678, 0.3696"); } cell_fall(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.080548, 0.09117, 0.112416, 0.114419, 0.140167", \ "0.098565, 0.111047, 0.127873, 0.139055, 0.157277", \ "0.117853, 0.13063, 0.151745, 0.16073, 0.187337", \ "0.193063, 0.20683, 0.230881, 0.243181, 0.274411", \ "0.303476, 0.324185, 0.34253, 0.35438, 0.389078"); } fall_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.033557, 0.03517, 0.050033, 0.053557, 0.0636", \ "0.042412, 0.052454, 0.0648, 0.066, 0.0714", \ "0.0678, 0.0636, 0.0744, 0.0816, 0.0924", \ "0.1506, 0.1536, 0.1554, 0.1572, 0.1692", \ "0.2916, 0.2916, 0.2928, 0.2928, 0.3012"); } } internal_power() { related_pin : "A"; rise_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.004755, 0.008056, 0.024782, 0.03847, 0.084138", \ "0.005505, 0.007831, 0.024786, 0.03784, 0.082816", \ "0.005661, 0.008241, 0.024988, 0.037645, 0.081888", \ "0.006986, 0.011904, 0.024903, 0.037263, 0.080331", \ "0.007316, 0.012522, 0.025505, 0.038129, 0.079708"); } fall_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.062057, 0.066892, 0.084137, 0.097042, 0.142031", \ "0.063442, 0.069887, 0.08367, 0.097934, 0.140457", \ "0.06445, 0.070032, 0.08388, 0.097493, 0.139831", \ "0.065119, 0.071216, 0.085353, 0.097511, 0.138904", \ "0.065286, 0.071412, 0.085769, 0.097685, 0.138986"); } } internal_power() { related_pin : "B"; rise_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.004733, 0.01101, 0.026233, 0.039317, 0.088493", \ "0.005232, 0.010867, 0.0258, 0.038812, 0.086891", \ "0.005494, 0.010867, 0.02575, 0.038564, 0.08606", \ "0.006589, 0.011051, 0.02548, 0.038324, 0.084742", \ "0.006416, 0.011798, 0.026405, 0.038696, 0.084448"); } fall_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.08415, 0.087001, 0.103508, 0.116397, 0.164914", \ "0.086183, 0.088562, 0.103184, 0.1157, 0.163291", \ "0.08758, 0.089603, 0.102913, 0.115221, 0.162843", \ "0.088158, 0.090514, 0.103925, 0.115995, 0.162004", \ "0.088394, 0.090653, 0.104301, 0.116544, 0.162066"); } } } } /* -------------- * * Design : OR2X2 * * -------------- */ cell (OR2X2) { area : 32; cell_leakage_power : 0.0895797; pin(A) { direction : input; capacitance : 0.015065; rise_capacitance : 0.015065; fall_capacitance : 0.0150152; } pin(B) { direction : input; capacitance : 0.0143643; rise_capacitance : 0.0139823; fall_capacitance : 0.0143643; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.966451; function : "(A+B)"; timing() { related_pin : "A"; timing_sense : positive_unate; cell_rise(delay_template_5x5) { index_1 ("0.01, 0.025, 0.05, 0.15, 0.3"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.092748, 0.11534, 0.147044, 0.170377, 0.209236", \ "0.105163, 0.131964, 0.168501, 0.188932, 0.229679", \ "0.127873, 0.154473, 0.192015, 0.212224, 0.256945", \ "0.215635, 0.243019, 0.279405, 0.299185, 0.347166", \ "0.348599, 0.377045, 0.40953, 0.42806, 0.47578"); } rise_transition(delay_template_5x5) { index_1 ("0.01, 0.025, 0.05, 0.15, 0.3"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.036098, 0.03661, 0.052655, 0.055718, 0.0708", \ "0.048273, 0.050006, 0.0636, 0.0732, 0.078", \ "0.0774, 0.078, 0.0906, 0.0918, 0.1062", \ "0.195, 0.1932, 0.1968, 0.1986, 0.2046", \ "0.3774, 0.378, 0.3792, 0.3792, 0.3822"); } cell_fall(delay_template_5x5) { index_1 ("0.01, 0.025, 0.05, 0.15, 0.3"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.094395, 0.121405, 0.162844, 0.183048, 0.241838", \ "0.110629, 0.139466, 0.179953, 0.200199, 0.259153", \ "0.134446, 0.165239, 0.203714, 0.225755, 0.288823", \ "0.217269, 0.247281, 0.287395, 0.311905, 0.375816", \ "0.337989, 0.369425, 0.408627, 0.431979, 0.495641"); } fall_transition(delay_template_5x5) { index_1 ("0.01, 0.025, 0.05, 0.15, 0.3"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.03261, 0.036977, 0.054118, 0.0648, 0.0684", \ "0.055949, 0.04937, 0.0696, 0.066, 0.0816", \ "0.075, 0.0768, 0.0864, 0.0852, 0.0942", \ "0.1668, 0.1662, 0.1716, 0.1734, 0.1794", \ "0.3156, 0.315, 0.3186, 0.3192, 0.3222"); } } timing() { related_pin : "B"; timing_sense : positive_unate; cell_rise(delay_template_5x5) { index_1 ("0.01, 0.025, 0.05, 0.15, 0.3"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.100325, 0.136854, 0.175223, 0.201311, 0.270082", \ "0.116601, 0.155024, 0.196406, 0.222548, 0.290586", \ "0.14118, 0.178808, 0.219855, 0.246222, 0.315043", \ "0.228893, 0.262516, 0.308898, 0.333366, 0.403605", \ "0.361227, 0.39236, 0.438202, 0.461073, 0.532183"); } rise_transition(delay_template_5x5) { index_1 ("0.01, 0.025, 0.05, 0.15, 0.3"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.042962, 0.04223, 0.05303, 0.056197, 0.0606", \ "0.055203, 0.0612, 0.063, 0.0654, 0.0786", \ "0.0804, 0.084, 0.09, 0.0924, 0.1008", \ "0.1956, 0.1962, 0.1968, 0.1974, 0.2022", \ "0.378, 0.3774, 0.378, 0.3798, 0.381"); } cell_fall(delay_template_5x5) { index_1 ("0.01, 0.025, 0.05, 0.15, 0.3"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.099191, 0.112322, 0.139636, 0.148957, 0.184156", \ "0.11846, 0.134406, 0.157571, 0.171043, 0.202547", \ "0.139498, 0.158523, 0.181649, 0.196023, 0.233489", \ "0.223423, 0.241205, 0.266009, 0.284006, 0.325223", \ "0.342801, 0.360178, 0.387822, 0.403561, 0.446859"); } fall_transition(delay_template_5x5) { index_1 ("0.01, 0.025, 0.05, 0.15, 0.3"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.045354, 0.034645, 0.05259, 0.063, 0.069", \ "0.050227, 0.054125, 0.0684, 0.0678, 0.0792", \ "0.0738, 0.0744, 0.0804, 0.0852, 0.0942", \ "0.165, 0.1674, 0.168, 0.1734, 0.183", \ "0.315, 0.3162, 0.3162, 0.3186, 0.324"); } } internal_power() { related_pin : "A"; rise_power(energy_template_5x5) { index_1 ("0.01, 0.025, 0.05, 0.15, 0.3"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.028268, 0.036539, 0.051709, 0.065795, 0.112807", \ "0.029479, 0.035527, 0.05, 0.063866, 0.108982", \ "0.030782, 0.035705, 0.049051, 0.062111, 0.106378", \ "0.032939, 0.035902, 0.048567, 0.059235, 0.1018", \ "0.03234, 0.036435, 0.048527, 0.059887, 0.101074"); } fall_power(energy_template_5x5) { index_1 ("0.01, 0.025, 0.05, 0.15, 0.3"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.082522, 0.094224, 0.109379, 0.120218, 0.16859", \ "0.084899, 0.090599, 0.107506, 0.116691, 0.16386", \ "0.085614, 0.091836, 0.105569, 0.115473, 0.160612", \ "0.088428, 0.093183, 0.105805, 0.117227, 0.157955", \ "0.087152, 0.093443, 0.106217, 0.117485, 0.157884"); } } internal_power() { related_pin : "B"; rise_power(energy_template_5x5) { index_1 ("0.01, 0.025, 0.05, 0.15, 0.3"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.026845, 0.035611, 0.05086, 0.066854, 0.118216", \ "0.027091, 0.035137, 0.049317, 0.064078, 0.114832", \ "0.028048, 0.034239, 0.048794, 0.063426, 0.111912", \ "0.030188, 0.034382, 0.048649, 0.061691, 0.10665", \ "0.031509, 0.035609, 0.049233, 0.06168, 0.105996"); } fall_power(energy_template_5x5) { index_1 ("0.01, 0.025, 0.05, 0.15, 0.3"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.101072, 0.099311, 0.124491, 0.138346, 0.190263", \ "0.106213, 0.105045, 0.123271, 0.135463, 0.185861", \ "0.108396, 0.107939, 0.124352, 0.134467, 0.182935", \ "0.109445, 0.113301, 0.124705, 0.136106, 0.180962", \ "0.110309, 0.113879, 0.124997, 0.136365, 0.180642"); } } } } /* --------------- * * Design : TBUFX1 * * --------------- */ cell (TBUFX1) { area : 40; cell_leakage_power : 0.0466889; pin(A) { direction : input; capacitance : 0.0173531; rise_capacitance : 0.0170972; fall_capacitance : 0.0173531; } pin(EN) { direction : input; capacitance : 0.0137604; rise_capacitance : 0.0135189; fall_capacitance : 0.0137604; internal_power() { rise_power(passive_energy_template_5x1) { index_1 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ("0, 0, 0, 0, 0"); } fall_power(passive_energy_template_5x1) { index_1 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ("0.031447, 0.037009, 0.050629, 0.060911, 0.096281"); } } } pin(Y) { direction : output; capacitance : 0.00453706; rise_capacitance : 0.0045197; fall_capacitance : 0.00453706; max_capacitance : 0.498495; function : "(!A)"; three_state : "(!EN)"; timing() { related_pin : "A"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.00953706, 0.0170371, 0.0295371, 0.0795371, 0.154537"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.043176, 0.05518, 0.060921, 0.062454, 0.060269", \ "0.054804, 0.067387, 0.077411, 0.084234, 0.086866", \ "0.072569, 0.089938, 0.106777, 0.113667, 0.126816", \ "0.134726, 0.15668, 0.18973, 0.207478, 0.247926", \ "0.227061, 0.249623, 0.291187, 0.317493, 0.383277"); } fall_transition(delay_template_5x5) { index_1 ("0.00953706, 0.0170371, 0.0295371, 0.0795371, 0.154537"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.033122, 0.063, 0.0888, 0.1068, 0.1638", \ "0.047344, 0.0732, 0.105, 0.1236, 0.1866", \ "0.0642, 0.0864, 0.1194, 0.1416, 0.2148", \ "0.1434, 0.1506, 0.1854, 0.2118, 0.2988", \ "0.2634, 0.2658, 0.288, 0.3138, 0.402"); } cell_rise(delay_template_5x5) { index_1 ("0.0095197, 0.0170197, 0.0295197, 0.0795197, 0.15452"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.062271, 0.077788, 0.100334, 0.118909, 0.175323", \ "0.07723, 0.093371, 0.122319, 0.143131, 0.204215", \ "0.099178, 0.119908, 0.152326, 0.175597, 0.245967", \ "0.185036, 0.205418, 0.252499, 0.28202, 0.37234", \ "0.311685, 0.332857, 0.383618, 0.420732, 0.526388"); } rise_transition(delay_template_5x5) { index_1 ("0.0095197, 0.0170197, 0.0295197, 0.0795197, 0.15452"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.045342, 0.0618, 0.0894, 0.1098, 0.1506", \ "0.058523, 0.081, 0.1062, 0.1212, 0.1752", \ "0.0924, 0.1056, 0.1338, 0.1518, 0.207", \ "0.2082, 0.2124, 0.2376, 0.261, 0.3246", \ "0.3846, 0.384, 0.399, 0.4182, 0.489"); } } timing() { related_pin : "EN"; timing_sense : positive_unate; timing_type : three_state_enable; cell_rise(delay_template_5x5) { index_1 ("0.0095197, 0.0170197, 0.0295197, 0.0795197, 0.15452"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.064314, 0.075634, 0.088454, 0.091437, 0.095397", \ "0.077397, 0.090966, 0.107025, 0.113114, 0.117077", \ "0.099421, 0.119163, 0.132762, 0.137814, 0.147518", \ "0.185263, 0.202177, 0.218933, 0.22496, 0.236135", \ "0.311767, 0.327156, 0.34382, 0.351651, 0.363551"); } rise_transition(delay_template_5x5) { index_1 ("0.0095197, 0.0170197, 0.0295197, 0.0795197, 0.15452"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.050547, 0.048832, 0.05962, 0.0624, 0.0828", \ "0.0606, 0.0612, 0.0684, 0.0732, 0.093", \ "0.0888, 0.0924, 0.0978, 0.0966, 0.111", \ "0.2076, 0.2046, 0.2004, 0.2028, 0.2094", \ "0.3846, 0.3846, 0.3798, 0.3792, 0.381"); } cell_fall(delay_template_5x5) { index_1 ("0.00953706, 0.0170371, 0.0295371, 0.0795371, 0.154537"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.021064, 0.015498, -0.019901, -0.055757, -0.191401", \ "0.032761, 0.034951, 0.012881, -0.013632, -0.126721", \ "0.049862, 0.060812, 0.053914, 0.036454, -0.04865", \ "0.108674, 0.137861, 0.169017, 0.174161, 0.1442", \ "0.199976, 0.230503, 0.291584, 0.319131, 0.349211"); } fall_transition(delay_template_5x5) { index_1 ("0.00953706, 0.0170371, 0.0295371, 0.0795371, 0.154537"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.022631, 0.054736, 0.0756, 0.0906, 0.1446", \ "0.03673, 0.0714, 0.0888, 0.114, 0.1746", \ "0.053948, 0.0852, 0.12, 0.141, 0.2142", \ "0.1374, 0.1566, 0.2124, 0.2478, 0.3432", \ "0.2634, 0.2694, 0.3186, 0.366, 0.4902"); } } timing() { related_pin : "EN"; timing_type : three_state_disable; timing_sense : negative_unate; cell_rise(delay_template_5x1) { index_1 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ("0.044417, 0.074028, 0.13325, 0.177667, 0.325722"); } rise_transition(delay_template_5x1) { index_1 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ("0.044417, 0.074028, 0.13325, 0.177667, 0.325722"); } cell_fall(delay_template_5x1) { index_1 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ("0.058908, 0.097486, 0.140526, 0.16786, 0.242557"); } fall_transition(delay_template_5x1) { index_1 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ("0.058908, 0.097486, 0.140526, 0.16786, 0.242557"); } } internal_power() { related_pin : "A"; fall_power(energy_template_5x5) { index_1 ("0.00953706, 0.0170371, 0.0295371, 0.0795371, 0.154537"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.019351, 0.014825, 0.003997, 0.020433, 0.078322", \ "0.018837, 0.015273, 0.001933, 0.017405, 0.07378", \ "0.018469, 0.014849, 0.000845, 0.013604, 0.067528", \ "0.017526, 0.016039, 0.006211, 0.004735, 0.050506", \ "0.017053, 0.016587, 0.009417, 0.001248, 0.036027"); } rise_power(energy_template_5x5) { index_1 ("0.0095197, 0.0170197, 0.0295197, 0.0795197, 0.15452"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.081639, 0.083922, 0.101537, 0.118189, 0.176864", \ "0.080072, 0.083431, 0.099818, 0.115188, 0.172995", \ "0.081234, 0.082681, 0.097459, 0.111718, 0.167725", \ "0.081747, 0.081121, 0.092339, 0.103912, 0.152468", \ "0.082336, 0.081605, 0.089401, 0.098251, 0.139201"); } } internal_power() { related_pin : "EN"; rise_power(energy_template_5x5) { index_1 ("0.0095197, 0.0170197, 0.0295197, 0.0795197, 0.15452"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.028687, 0.030603, 0.045048, 0.054651, 0.090733", \ "0.028319, 0.03161, 0.045186, 0.055485, 0.090639", \ "0.028929, 0.033082, 0.045696, 0.055971, 0.09119", \ "0.029286, 0.033243, 0.045698, 0.056076, 0.091671", \ "0.029608, 0.033829, 0.046152, 0.056419, 0.091818"); } fall_power(energy_template_5x5) { index_1 ("0.00953706, 0.0170371, 0.0295371, 0.0795371, 0.154537"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.00698, 0.000216, 0.014399, 0.025998, 0.064783", \ "0.00622, 0.001328, 0.012957, 0.024394, 0.06269", \ "0.006376, 0.001583, 0.012128, 0.023177, 0.060675", \ "0.006415, 0.001927, 0.011265, 0.022, 0.058368", \ "0.006522, 0.00224, 0.0112, 0.021529, 0.057516"); } } } } /* --------------- * * Design : TBUFX2 * * --------------- */ cell (TBUFX2) { area : 56; cell_leakage_power : 0.0853032; pin(A) { direction : input; capacitance : 0.0347058; rise_capacitance : 0.0341954; fall_capacitance : 0.0347058; } pin(EN) { direction : input; capacitance : 0.0275005; rise_capacitance : 0.027043; fall_capacitance : 0.0275005; internal_power() { rise_power(passive_energy_template_5x1) { index_1 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ("0, 0, 0, 0, 0"); } fall_power(passive_energy_template_5x1) { index_1 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ("0.062739, 0.073294, 0.098928, 0.119047, 0.186594"); } } } pin(Y) { direction : output; capacitance : 0.00906655; rise_capacitance : 0.00901605; fall_capacitance : 0.00906655; max_capacitance : 0.997443; function : "(!A)"; three_state : "(!EN)"; timing() { related_pin : "A"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.0190665, 0.0340666, 0.0590665, 0.159067, 0.309067"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.04457, 0.055083, 0.060858, 0.062407, 0.060244", \ "0.054697, 0.06733, 0.077377, 0.084191, 0.086853", \ "0.072464, 0.089869, 0.106729, 0.113639, 0.126801", \ "0.134688, 0.156645, 0.189702, 0.207454, 0.247911", \ "0.22704, 0.249605, 0.29117, 0.317427, 0.383264"); } fall_transition(delay_template_5x5) { index_1 ("0.0190665, 0.0340666, 0.0590665, 0.159067, 0.309067"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.033796, 0.0636, 0.0888, 0.1074, 0.1638", \ "0.0474, 0.0732, 0.1056, 0.1236, 0.1866", \ "0.0648, 0.0864, 0.12, 0.1416, 0.2148", \ "0.1434, 0.1512, 0.1854, 0.2118, 0.2988", \ "0.2634, 0.2658, 0.288, 0.3138, 0.402"); } cell_rise(delay_template_5x5) { index_1 ("0.019016, 0.034016, 0.0590161, 0.159016, 0.309016"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.06247, 0.077821, 0.100341, 0.118895, 0.175315", \ "0.078889, 0.093447, 0.122337, 0.14314, 0.204216", \ "0.099451, 0.119999, 0.152375, 0.175636, 0.245983", \ "0.18532, 0.20559, 0.25259, 0.282085, 0.372382", \ "0.311985, 0.333031, 0.38374, 0.420831, 0.526453"); } rise_transition(delay_template_5x5) { index_1 ("0.019016, 0.034016, 0.0590161, 0.159016, 0.309016"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.045431, 0.0618, 0.0894, 0.1098, 0.1506", \ "0.059153, 0.081, 0.1062, 0.1212, 0.1746", \ "0.0924, 0.1056, 0.1338, 0.1518, 0.207", \ "0.2082, 0.2124, 0.2376, 0.261, 0.3246", \ "0.3852, 0.384, 0.399, 0.4182, 0.4896"); } } timing() { related_pin : "EN"; timing_sense : positive_unate; timing_type : three_state_enable; cell_rise(delay_template_5x5) { index_1 ("0.019016, 0.034016, 0.0590161, 0.159016, 0.309016"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.066588, 0.080398, 0.094432, 0.100823, 0.106736", \ "0.079877, 0.097954, 0.1125, 0.120284, 0.13082", \ "0.102207, 0.119803, 0.137962, 0.147594, 0.158875", \ "0.187132, 0.203404, 0.222751, 0.232505, 0.249202", \ "0.313694, 0.330805, 0.349255, 0.358947, 0.376056"); } rise_transition(delay_template_5x5) { index_1 ("0.019016, 0.034016, 0.0590161, 0.159016, 0.309016"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.052406, 0.050364, 0.05533, 0.058774, 0.084", \ "0.063, 0.0708, 0.0714, 0.075, 0.0906", \ "0.0882, 0.0876, 0.0948, 0.099, 0.1134", \ "0.2076, 0.2052, 0.2016, 0.2034, 0.2076", \ "0.3846, 0.3846, 0.3804, 0.3798, 0.381"); } cell_fall(delay_template_5x5) { index_1 ("0.0190665, 0.0340666, 0.0590665, 0.159067, 0.309067"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.021354, 0.015834, -0.019419, -0.055411, -0.191188", \ "0.033098, 0.035485, 0.013371, -0.013026, -0.126362", \ "0.050079, 0.061022, 0.054814, 0.037301, -0.047837", \ "0.108148, 0.138809, 0.169548, 0.174168, 0.14517", \ "0.200483, 0.229963, 0.29106, 0.319072, 0.349126"); } fall_transition(delay_template_5x5) { index_1 ("0.0190665, 0.0340666, 0.0590665, 0.159067, 0.309067"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.022651, 0.054683, 0.0762, 0.0912, 0.1446", \ "0.036458, 0.0714, 0.0888, 0.1146, 0.1752", \ "0.053472, 0.0846, 0.1194, 0.141, 0.2148", \ "0.1362, 0.1566, 0.2112, 0.2466, 0.3426", \ "0.2634, 0.2694, 0.318, 0.3648, 0.4872"); } } timing() { related_pin : "EN"; timing_type : three_state_disable; timing_sense : negative_unate; cell_rise(delay_template_5x1) { index_1 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ("0.044417, 0.074028, 0.13325, 0.177667, 0.325722"); } rise_transition(delay_template_5x1) { index_1 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ("0.044417, 0.074028, 0.13325, 0.177667, 0.325722"); } cell_fall(delay_template_5x1) { index_1 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ("0.059734, 0.09796, 0.140369, 0.166485, 0.239306"); } fall_transition(delay_template_5x1) { index_1 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ("0.059734, 0.09796, 0.140369, 0.166485, 0.239306"); } } internal_power() { related_pin : "A"; fall_power(energy_template_5x5) { index_1 ("0.0190665, 0.0340666, 0.0590665, 0.159067, 0.309067"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.038244, 0.029621, 0.008064, 0.040933, 0.156704", \ "0.037693, 0.030513, 0.003916, 0.034866, 0.147679", \ "0.036945, 0.02967, 0.001652, 0.02725, 0.135151", \ "0.035059, 0.032067, 0.012407, 0.009487, 0.101033", \ "0.034108, 0.033171, 0.018826, 0.002481, 0.072067"); } rise_power(energy_template_5x5) { index_1 ("0.019016, 0.034016, 0.0590161, 0.159016, 0.309016"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.163232, 0.167827, 0.20305, 0.236356, 0.353708", \ "0.160526, 0.166881, 0.199619, 0.230353, 0.345985", \ "0.162813, 0.165372, 0.1949, 0.223452, 0.335436", \ "0.163482, 0.162264, 0.184678, 0.207814, 0.304926", \ "0.164667, 0.16323, 0.178799, 0.1965, 0.278394"); } } internal_power() { related_pin : "EN"; rise_power(energy_template_5x5) { index_1 ("0.019016, 0.034016, 0.0590161, 0.159016, 0.309016"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.056886, 0.060621, 0.088211, 0.105801, 0.173874", \ "0.057098, 0.06319, 0.088306, 0.107701, 0.1749", \ "0.058831, 0.065433, 0.088894, 0.107365, 0.175218", \ "0.058212, 0.065873, 0.088645, 0.109154, 0.176158", \ "0.05872, 0.066891, 0.089925, 0.109705, 0.176717"); } fall_power(energy_template_5x5) { index_1 ("0.0190665, 0.0340666, 0.0590665, 0.159067, 0.309067"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.014255, 0.000418, 0.026879, 0.049231, 0.123502", \ "0.012904, 0.003527, 0.023934, 0.04587, 0.119437", \ "0.013059, 0.004035, 0.022247, 0.043362, 0.115328", \ "0.013488, 0.004551, 0.020922, 0.040849, 0.110477", \ "0.013268, 0.005206, 0.020131, 0.040127, 0.108755"); } } } } /* ---------------- * * Design : XNOR2X1 * * ---------------- */ cell (XNOR2X1) { area : 56; cell_leakage_power : 0.160592; pin(A) { direction : input; capacitance : 0.0296656; rise_capacitance : 0.0296531; fall_capacitance : 0.0296656; } pin(B) { direction : input; capacitance : 0.0342715; rise_capacitance : 0.0339946; fall_capacitance : 0.0342715; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.484641; function : "(!(A^B))"; timing() { related_pin : "A"; timing_sense : non_unate; cell_rise(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.084544, 0.100187, 0.114213, 0.123541, 0.136185", \ "0.097758, 0.113674, 0.126363, 0.138852, 0.150601", \ "0.119347, 0.133769, 0.150698, 0.160444, 0.175328", \ "0.200286, 0.209259, 0.234451, 0.245612, 0.260619", \ "0.324789, 0.342562, 0.359971, 0.370257, 0.387423"); } rise_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.052523, 0.057076, 0.053423, 0.0618, 0.0738", \ "0.0714, 0.069, 0.0708, 0.081, 0.0828", \ "0.102, 0.099, 0.0972, 0.1014, 0.1062", \ "0.2178, 0.2148, 0.207, 0.2094, 0.213", \ "0.3948, 0.3954, 0.3894, 0.387, 0.3894"); } cell_fall(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.080598, 0.104814, 0.14407, 0.16646, 0.230823", \ "0.090007, 0.114398, 0.158715, 0.18125, 0.244904", \ "0.105009, 0.129684, 0.174764, 0.197639, 0.261251", \ "0.164452, 0.191059, 0.235757, 0.25945, 0.326304", \ "0.254746, 0.281259, 0.324243, 0.349894, 0.419368"); } fall_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.04529, 0.040774, 0.050768, 0.044716, 0.0696", \ "0.053465, 0.052244, 0.0624, 0.063, 0.0738", \ "0.0756, 0.069, 0.0774, 0.0792, 0.084", \ "0.1512, 0.1512, 0.1482, 0.1488, 0.1536", \ "0.2724, 0.273, 0.2682, 0.2652, 0.27"); } } timing() { related_pin : "B"; timing_sense : non_unate; cell_rise(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.10043, 0.112224, 0.127373, 0.134943, 0.151", \ "0.114693, 0.125678, 0.141086, 0.148733, 0.165698", \ "0.134581, 0.147375, 0.163947, 0.172141, 0.187238", \ "0.219625, 0.233512, 0.248511, 0.256184, 0.272455", \ "0.34583, 0.360056, 0.375552, 0.389966, 0.399734"); } rise_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.057964, 0.053126, 0.056893, 0.057661, 0.0684", \ "0.0702, 0.0684, 0.0708, 0.075, 0.084", \ "0.0996, 0.0978, 0.1014, 0.1038, 0.111", \ "0.2184, 0.2184, 0.2172, 0.219, 0.2214", \ "0.3948, 0.3954, 0.3948, 0.3954, 0.3966"); } cell_fall(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.088851, 0.113426, 0.147155, 0.170376, 0.234997", \ "0.099159, 0.123811, 0.160163, 0.180288, 0.246878", \ "0.11593, 0.140664, 0.175175, 0.198865, 0.265918", \ "0.178962, 0.203622, 0.239327, 0.262263, 0.328548", \ "0.270984, 0.295933, 0.331436, 0.354428, 0.421444"); } fall_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.038498, 0.040763, 0.053891, 0.049019, 0.0624", \ "0.051011, 0.050726, 0.0624, 0.059128, 0.0684", \ "0.0708, 0.0738, 0.0786, 0.078, 0.0876", \ "0.15, 0.1524, 0.1512, 0.1536, 0.1566", \ "0.2712, 0.2712, 0.2718, 0.2706, 0.273"); } } internal_power() { related_pin : "A"; rise_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.04347, 0.047419, 0.069645, 0.092194, 0.168622", \ "0.043836, 0.046995, 0.070428, 0.091803, 0.165958", \ "0.042241, 0.046473, 0.070214, 0.091468, 0.162393", \ "0.039645, 0.047232, 0.070839, 0.092026, 0.158857", \ "0.037719, 0.046566, 0.071058, 0.091224, 0.158921"); } fall_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.109542, 0.118976, 0.14587, 0.165122, 0.23287", \ "0.108958, 0.118223, 0.145165, 0.165146, 0.232197", \ "0.108499, 0.117602, 0.144445, 0.164886, 0.231277", \ "0.103556, 0.114346, 0.142765, 0.163112, 0.230403", \ "0.101638, 0.111971, 0.14061, 0.160075, 0.229342"); } } internal_power() { related_pin : "B"; rise_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.051682, 0.059125, 0.082205, 0.101964, 0.173332", \ "0.050197, 0.059498, 0.08273, 0.102347, 0.172834", \ "0.050515, 0.060544, 0.082443, 0.101904, 0.172822", \ "0.050393, 0.061573, 0.083208, 0.102791, 0.171525", \ "0.050581, 0.062061, 0.083892, 0.102759, 0.171009"); } fall_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.110748, 0.120302, 0.144257, 0.164108, 0.234096", \ "0.111537, 0.120649, 0.14374, 0.164163, 0.233653", \ "0.11211, 0.121157, 0.144867, 0.163574, 0.233201", \ "0.112552, 0.122391, 0.145428, 0.164597, 0.232813", \ "0.112929, 0.122933, 0.146023, 0.165021, 0.23239"); } } } } /* --------------- * * Design : XOR2X1 * * --------------- */ cell (XOR2X1) { area : 56; cell_leakage_power : 0.161354; pin(A) { direction : input; capacitance : 0.0296528; rise_capacitance : 0.029651; fall_capacitance : 0.0296528; } pin(B) { direction : input; capacitance : 0.0342661; rise_capacitance : 0.0339918; fall_capacitance : 0.0342661; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.484395; function : "(A^B)"; timing() { related_pin : "A"; timing_sense : non_unate; cell_rise(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.084668, 0.100252, 0.11425, 0.123569, 0.136197", \ "0.097915, 0.113723, 0.126398, 0.138879, 0.150616", \ "0.119426, 0.133803, 0.150727, 0.160469, 0.175347", \ "0.200291, 0.21109, 0.234434, 0.245604, 0.260628", \ "0.324762, 0.343132, 0.359931, 0.370218, 0.387403"); } rise_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.052475, 0.0571, 0.053443, 0.0618, 0.0738", \ "0.0714, 0.069, 0.0708, 0.081, 0.0828", \ "0.102, 0.0984, 0.0972, 0.1014, 0.1062", \ "0.2178, 0.2148, 0.2064, 0.2094, 0.213", \ "0.3942, 0.3948, 0.3894, 0.387, 0.3894"); } cell_fall(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.080217, 0.104741, 0.14405, 0.166439, 0.230805", \ "0.089887, 0.114359, 0.158704, 0.181241, 0.244897", \ "0.104894, 0.129666, 0.174768, 0.197644, 0.261257", \ "0.164496, 0.19114, 0.235815, 0.259502, 0.326338", \ "0.254884, 0.281399, 0.324471, 0.350019, 0.419374"); } fall_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.041331, 0.040781, 0.050767, 0.044749, 0.0696", \ "0.053453, 0.052285, 0.0624, 0.063, 0.0738", \ "0.0756, 0.069, 0.078, 0.0792, 0.084", \ "0.1518, 0.1512, 0.1482, 0.1488, 0.1536", \ "0.273, 0.273, 0.2682, 0.2652, 0.27"); } } timing() { related_pin : "B"; timing_sense : non_unate; cell_rise(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.095856, 0.109639, 0.124914, 0.132649, 0.149393", \ "0.112134, 0.122918, 0.138721, 0.14656, 0.164175", \ "0.132565, 0.144856, 0.161456, 0.170028, 0.185654", \ "0.217554, 0.231394, 0.246536, 0.255419, 0.27072", \ "0.343798, 0.357936, 0.373613, 0.388316, 0.398061"); } rise_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.058266, 0.053422, 0.056738, 0.058408, 0.0684", \ "0.0696, 0.0684, 0.0714, 0.0756, 0.0846", \ "0.0996, 0.0984, 0.1008, 0.1026, 0.111", \ "0.2178, 0.2184, 0.216, 0.2184, 0.2208", \ "0.3942, 0.3942, 0.3942, 0.3942, 0.3954"); } cell_fall(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.090864, 0.115106, 0.148564, 0.176005, 0.236451", \ "0.101631, 0.126046, 0.162396, 0.186432, 0.247857", \ "0.118398, 0.142704, 0.177128, 0.20129, 0.267362", \ "0.181148, 0.206, 0.241266, 0.265038, 0.330296", \ "0.273354, 0.298267, 0.333521, 0.3571, 0.42352"); } fall_transition(delay_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.038733, 0.04056, 0.054628, 0.057339, 0.0624", \ "0.051463, 0.051355, 0.063, 0.0618, 0.0684", \ "0.0732, 0.0744, 0.0792, 0.0774, 0.0882", \ "0.1524, 0.1542, 0.1518, 0.1542, 0.1584", \ "0.2724, 0.2724, 0.2736, 0.2724, 0.2748"); } } internal_power() { related_pin : "A"; rise_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.039147, 0.043066, 0.065269, 0.087649, 0.161009", \ "0.039465, 0.042689, 0.06602, 0.087383, 0.159416", \ "0.037848, 0.042114, 0.065867, 0.087082, 0.157005", \ "0.035203, 0.043327, 0.066417, 0.087567, 0.154421", \ "0.033256, 0.041973, 0.066668, 0.086833, 0.154458"); } fall_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.115486, 0.124065, 0.150891, 0.17016, 0.238191", \ "0.11447, 0.12322, 0.150245, 0.170238, 0.237468", \ "0.113772, 0.122815, 0.149439, 0.170003, 0.236493", \ "0.108866, 0.119919, 0.148098, 0.168247, 0.235659", \ "0.107123, 0.117629, 0.146091, 0.165491, 0.234547"); } } internal_power() { related_pin : "B"; rise_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.026559, 0.03559, 0.058419, 0.078185, 0.149262", \ "0.025608, 0.036149, 0.058793, 0.078541, 0.148897", \ "0.026126, 0.037049, 0.058739, 0.078407, 0.148412", \ "0.026155, 0.037809, 0.059428, 0.078443, 0.14767", \ "0.026354, 0.038386, 0.060015, 0.078495, 0.146955"); } fall_power(energy_template_5x5) { index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.135123, 0.144361, 0.167778, 0.18777, 0.258031", \ "0.135422, 0.144299, 0.167404, 0.187571, 0.257476", \ "0.135526, 0.145303, 0.167795, 0.187325, 0.256994", \ "0.135659, 0.146275, 0.168727, 0.18804, 0.256332", \ "0.135952, 0.146808, 0.169391, 0.1885, 0.255797"); } } } } } qflow-1.1.23/tech/osu018/osu018.par0000664000175000001440000000316012535603240015165 0ustar timusers# osu018.par --- Parameter file for GrayWolf # NOTE: all distance units are in centimicrons unless otherwise stated RULES # values are resistance in ohms/sq and capacitance in fF/um^2 layer metal1 0.07 0.030 horizontal layer metal2 0.07 0.017 vertical layer metal3 0.07 0.006 horizontal layer metal4 0.04 0.004 vertical via via12 metal1 metal2 via via23 metal2 metal3 via via34 metal3 metal4 width metal1 60 width metal2 60 width metal3 60 width metal4 120 width via12 60 width via23 60 width via34 120 # Set spacing = track pitch - width, so that GrayWolf places pins # on the right pitch. # Pitches are (in um): # metal1 = 200, metal2 = 160, metal3 = 200, metal4 = 320 spacing metal1 metal1 140 spacing metal2 metal2 100 spacing metal3 metal3 140 spacing metal4 metal4 200 # Stacked vias allowed spacing via12 via23 0 spacing via23 via34 0 overhang via12 metal1 8 overhang via12 metal2 6 overhang via23 metal2 8 overhang via23 metal3 6 overhang via34 metal3 14 overhang via34 metal4 16 ENDRULES *vertical_wire_weight : 1.0 *vertical_path_weight : 1.0 *padspacing : variable *rowSep : 0.0 0 *track.pitch : 80 *graphics.wait : off *last_chance.wait : off *random.seed : 12345 TWMC*chip.aspect.ratio : 0.75 TWSC*feedThruWidth : 80 layer 1 TWSC*do.global.route : on TWSC*ignore_feeds : true TWSC*call_row_evener : true TWSC*even_rows_maximally : true # TWSC*no.graphics : on GENR*row_to_tile_spacing: 1 # GENR*numrows : 6 GENR*flip_alternate_rows : 1 qflow-1.1.23/tech/osu018/osu018.sh0000664000175000001440000000617312535603240015024 0ustar timusers#!/bin/tcsh #--------------------------------------------------------------- # Shell script setting up all variables used by the qflow scripts # for this project #--------------------------------------------------------------- # The LEF file containing standard cell macros set leffile=osu018_stdcells.lef # The SPICE netlist containing subcell definitions for all the standard cells set spicefile=osu018_stdcells.sp # The liberty format file containing standard cell timing and function information set libertyfile=osu018_stdcells.lib # If there is another LEF file containing technology information # that is separate from the file containing standard cell macros, # set this. Otherwise, leave it defined as an empty string. set techleffile="" # All cells below should be the lowest output drive strength value, # if the standard cell set has multiple cells with different drive # strengths. Comment out any cells that do not exist. set flopcell=DFFPOSX1 ;# Standard positive-clocked DFF, no set or reset # set flopset=DFFS ;# DFF with preset, if available # set flopreset=DFFSR ;# DFF with clear, if available set flopsetreset=DFFSR ;# DFF with both set and clear set setpin=S ;# The name of the set pin on DFFs set resetpin=R ;# The name of the clear/reset pin on DFFs set setpininvert=1 ;# Set this to 1 if the set pin is inverted (!set) set resetpininvert=1 ;# Set this to 1 if the reset pin is inverted (!reset) set floppinout=Q ;# Name of the output pin on DFFs set floppinin=D ;# Name of the output pin on DFFs set floppinclk=CLK ;# Name of the clock pin on DFFs set bufcell=BUFX2 ;# Minimum drive strength buffer cell set bufpin_in=A ;# Name of input port to buffer cell set bufpin_out=Y ;# Name of output port to buffer cell set inverter=INVX1 ;# Minimum drive strength inverter cell set invertpin_in=A ;# Name of input port to inverter cell set invertpin_out=Y ;# Name of output port to inverter cell set norgate=NOR2X1 ;# 2-input NOR gate, minimum drive strength set norpin_in1=A ;# Name of first input pin to NOR gate set norpin_in2=B ;# Name of second input pin to NOR gate set norpin_out=Y ;# Name of output pin from OR gate set nandgate=NAND2X1 ;# 2-input NAND gate, minimum drive strength set nandpin_in1=A ;# Name of first input pin to NAND gate set nandpin_in2=B ;# Name of second input pin to NAND gate set nandpin_out=Y ;# Name of output pin from NAND gate set fillcell=FILL ;# Spacer (filler) cell (prefix, if more than one) set tiehi="" ;# Cell to connect to power, if one exists set tiehipin_out="" ;# Output pin name of tiehi cell, if it exists set tielo="" ;# Cell to connect to ground, if one exists set tielopin_out="" ;# Output pin name of tielo cell, if it exists set gndnet=gnd ;# Name used for ground pins in standard cells set vddnet=vdd ;# Name used for power pins in standard cells set separator="" ;# Separator between gate names and drive strengths set techfile=SCN4M_SUBM.20 ;# magic techfile set magicrc=osu018.magicrc ;# magic startup script set gdsfile=osu018_stdcells.gds ;# GDS database of standard cells set fanout_options="-l 200 -c 50" ;# blifFanout target maximum latency ;# per gate 200ps, output load set to 50fF qflow-1.1.23/tech/osu018/osu018.prm0000775000175000001440000000160512535603240015206 0ustar timusers; ; configuration file for osu018 (0.18um process) ; Note that these values are totally bogus! ; lambda 0.01 ; length scaling, microns (1 lambda = 1 centimicron) capga .0115 ; gate capacitance, pF/micron^2 capda 0.0012 capdp 0.0013 cappda 0.00260 cappdp 0.00090 lowthresh 0.5 ; logic low threshold as a normalized voltage highthresh 0.5 ; logic high threshold as a normalized voltage cntpullup 0 ; irrelevant, cmos technology; no depletion transistors diffperim 0 ; don't include diffusion perimeters for sidewall cap. subparea 0 ; poly over transistor won't count as part pf bulk-poly cap. diffext 0 ; diffusion extension for each transistor resistance n-channel dynamic-low 2 0.4 1844.70 resistance p-channel dynamic-high 6.2 0.4 1489.10 resistance n-channel static 2 0.4 2203.94 resistance p-channel static 6.2 0.4 1693.37 qflow-1.1.23/tech/Makefile0000664000175000001440000000215412535603240014025 0ustar timusers# # qflow project tech makefile # # Main compiler arguments CFLAGS = -g -O2 DEFS = -DPACKAGE_NAME=\"\" -DPACKAGE_TARNAME=\"\" -DPACKAGE_VERSION=\"\" -DPACKAGE_STRING=\"\" -DPACKAGE_BUGREPORT=\"\" -DPACKAGE_URL=\"\" -DSTDC_HEADERS=1 -DHAVE_SETENV=1 -DHAVE_PUTENV=1 -DTCLSH_PATH=\"/bin/tclsh\" -DQFLOW_MAGIC_PATH=\"/usr/local/bin/magic\" -DQFLOW_QROUTER_PATH=\"/usr/local/bin/qrouter\" -DQFLOW_GRAYWOLF_PATH=\"/usr/local/bin/graywolf\" -DQFLOW_YOSYS_PATH=\"/usr/local/bin/yosys\" LIBS = LDFLAGS = INSTALL = /bin/install -c QFLOW_LIB_DIR = /usr/local/share/qflow TECH_DIRS = osu050 osu035 osu018 TECHINSTALL = ${QFLOW_LIB_DIR}/tech all: @echo "Making all in tech directories" for target in $(TECH_DIRS); do \ (cd $$target ; $(MAKE) all) ;\ done install: @echo "Installing built-in tech files" $(INSTALL) -d $(DESTDIR)${TECHINSTALL} for target in $(TECH_DIRS); do \ (cd $$target ; $(MAKE) install) ;\ done clean: @echo "Cleaning up built-in tech files" for target in $(TECH_DIRS); do \ (cd $$target ; $(MAKE) clean) ;\ done uninstall: @echo "Uninstalling built-in tech files $(RM) -rf ${TECHINSTALL} qflow-1.1.23/tech/osu035/0000755000175000001440000000000012535603557013432 5ustar timusersqflow-1.1.23/tech/osu035/osu035_stdcells.sp0000755000175000001440000013405312526236535016740 0ustar timusers .subckt AND2X1 Y B vdd gnd A M0 a_2_6# A vdd vdd pfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M1 vdd B a_2_6# vdd pfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M2 Y a_2_6# vdd vdd pfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M3 a_9_6# A a_2_6# gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M4 gnd B a_9_6# gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M5 Y a_2_6# gnd gnd nfet w=2u l=0.4u + ad=0p pd=0u as=0p ps=0u .ends AND2X1 .subckt AND2X2 vdd gnd A B Y M0 a_2_6# A vdd vdd pfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M1 vdd B a_2_6# vdd pfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M2 Y a_2_6# vdd vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M3 a_9_6# A a_2_6# gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M4 gnd B a_9_6# gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M5 Y a_2_6# gnd gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u .ends AND2X2 .subckt AOI21X1 gnd vdd A B Y C M0 vdd A a_2_54# vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M1 a_2_54# B vdd vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M2 Y C a_2_54# vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M3 a_12_6# A gnd gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M4 Y B a_12_6# gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M5 gnd C Y gnd nfet w=2u l=0.4u + ad=0p pd=0u as=0p ps=0u .ends AOI21X1 .subckt AOI22X1 gnd vdd C D Y A B M0 vdd A a_2_54# vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M1 a_2_54# B vdd vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M2 Y D a_2_54# vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M3 a_2_54# C Y vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M4 a_11_6# A gnd gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M5 Y B a_11_6# gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M6 a_28_6# D Y gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M7 gnd C a_28_6# gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u .ends AOI22X1 .subckt BUFX2 vdd gnd A Y M0 vdd A a_2_6# vdd pfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M1 Y a_2_6# vdd vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M2 gnd A a_2_6# gnd nfet w=2u l=0.4u + ad=0p pd=0u as=0p ps=0u M3 Y a_2_6# gnd gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u .ends BUFX2 .subckt BUFX4 vdd gnd A Y M0 vdd A a_2_6# vdd pfet w=6u l=0.4u + ad=0p pd=0u as=0p ps=0u M1 Y a_2_6# vdd vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M2 vdd a_2_6# Y vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M3 gnd A a_2_6# gnd nfet w=3u l=0.4u + ad=0p pd=0u as=0p ps=0u M4 Y a_2_6# gnd gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M5 gnd a_2_6# Y gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u .ends BUFX4 .subckt CLKBUF1 A vdd gnd Y M0 a_9_6# A vdd vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M1 vdd A a_9_6# vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M2 a_25_6# a_9_6# vdd vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M3 vdd a_9_6# a_25_6# vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M4 a_41_6# a_25_6# vdd vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M5 vdd a_25_6# a_41_6# vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M6 Y a_41_6# vdd vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M7 vdd a_41_6# Y vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M8 a_9_6# A gnd gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M9 gnd A a_9_6# gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M10 a_25_6# a_9_6# gnd gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M11 gnd a_9_6# a_25_6# gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M12 a_41_6# a_25_6# gnd gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M13 gnd a_25_6# a_41_6# gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M14 Y a_41_6# gnd gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M15 gnd a_41_6# Y gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u .ends CLKBUF1 .subckt CLKBUF2 vdd gnd A Y M0 a_9_6# A vdd vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M1 vdd A a_9_6# vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M2 a_25_6# a_9_6# vdd vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M3 vdd a_9_6# a_25_6# vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M4 a_41_6# a_25_6# vdd vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M5 vdd a_25_6# a_41_6# vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M6 a_57_6# a_41_6# vdd vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M7 vdd a_41_6# a_57_6# vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M8 a_73_6# a_57_6# vdd vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M9 vdd a_57_6# a_73_6# vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M10 Y a_73_6# vdd vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M11 vdd a_73_6# Y vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M12 a_9_6# A gnd gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M13 gnd A a_9_6# gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M14 a_25_6# a_9_6# gnd gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M15 gnd a_9_6# a_25_6# gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M16 a_41_6# a_25_6# gnd gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M17 gnd a_25_6# a_41_6# gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M18 a_57_6# a_41_6# gnd gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M19 gnd a_41_6# a_57_6# gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M20 a_73_6# a_57_6# gnd gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M21 gnd a_57_6# a_73_6# gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M22 Y a_73_6# gnd gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M23 gnd a_73_6# Y gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u .ends CLKBUF2 .subckt CLKBUF3 gnd vdd A Y M0 a_9_6# A vdd vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M1 vdd A a_9_6# vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M2 a_25_6# a_9_6# vdd vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M3 vdd a_9_6# a_25_6# vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M4 a_41_6# a_25_6# vdd vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M5 vdd a_25_6# a_41_6# vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M6 a_57_6# a_41_6# vdd vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M7 vdd a_41_6# a_57_6# vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M8 a_73_6# a_57_6# vdd vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M9 vdd a_57_6# a_73_6# vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M10 a_89_6# a_73_6# vdd vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M11 vdd a_73_6# a_89_6# vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M12 a_105_6# a_89_6# vdd vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M13 vdd a_89_6# a_105_6# vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M14 Y a_105_6# vdd vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M15 vdd a_105_6# Y vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M16 a_9_6# A gnd gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M17 gnd A a_9_6# gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M18 a_25_6# a_9_6# gnd gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M19 gnd a_9_6# a_25_6# gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M20 a_41_6# a_25_6# gnd gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M21 gnd a_25_6# a_41_6# gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M22 a_57_6# a_41_6# gnd gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M23 gnd a_41_6# a_57_6# gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M24 a_73_6# a_57_6# gnd gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M25 gnd a_57_6# a_73_6# gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M26 a_89_6# a_73_6# gnd gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M27 gnd a_73_6# a_89_6# gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M28 a_105_6# a_89_6# gnd gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M29 gnd a_89_6# a_105_6# gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M30 Y a_105_6# gnd gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M31 gnd a_105_6# Y gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u .ends CLKBUF3 .subckt DFFNEGX1 CLK vdd D gnd Q M0 vdd CLK a_2_6# vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M1 a_17_74# D vdd vdd pfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M2 a_23_6# a_2_6# a_17_74# vdd pfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M3 a_31_74# CLK a_23_6# vdd pfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M4 vdd a_34_4# a_31_74# vdd pfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M5 a_34_4# a_23_6# vdd vdd pfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M6 a_61_74# a_34_4# vdd vdd pfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M7 a_66_6# CLK a_61_74# vdd pfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M8 a_76_84# a_2_6# a_66_6# vdd pfet w=2u l=0.4u + ad=0p pd=0u as=0p ps=0u M9 vdd Q a_76_84# vdd pfet w=2u l=0.4u + ad=0p pd=0u as=0p ps=0u M10 gnd CLK a_2_6# gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M11 Q a_66_6# vdd vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M12 a_17_6# D gnd gnd nfet w=2u l=0.4u + ad=0p pd=0u as=0p ps=0u M13 a_23_6# CLK a_17_6# gnd nfet w=2u l=0.4u + ad=0p pd=0u as=0p ps=0u M14 a_31_6# a_2_6# a_23_6# gnd nfet w=2u l=0.4u + ad=0p pd=0u as=0p ps=0u M15 gnd a_34_4# a_31_6# gnd nfet w=2u l=0.4u + ad=0p pd=0u as=0p ps=0u M16 a_34_4# a_23_6# gnd gnd nfet w=2u l=0.4u + ad=0p pd=0u as=0p ps=0u M17 a_61_6# a_34_4# gnd gnd nfet w=2u l=0.4u + ad=0p pd=0u as=0p ps=0u M18 a_66_6# a_2_6# a_61_6# gnd nfet w=2u l=0.4u + ad=0p pd=0u as=0p ps=0u M19 a_76_6# CLK a_66_6# gnd nfet w=2u l=0.4u + ad=0p pd=0u as=0p ps=0u M20 gnd Q a_76_6# gnd nfet w=2u l=0.4u + ad=0p pd=0u as=0p ps=0u M21 Q a_66_6# gnd gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u .ends DFFNEGX1 .subckt DFFPOSX1 vdd D gnd Q CLK M0 vdd CLK a_2_6# vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M1 a_17_74# D vdd vdd pfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M2 a_22_6# CLK a_17_74# vdd pfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M3 a_31_74# a_2_6# a_22_6# vdd pfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M4 vdd a_34_4# a_31_74# vdd pfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M5 a_34_4# a_22_6# vdd vdd pfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M6 a_61_74# a_34_4# vdd vdd pfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M7 a_66_6# a_2_6# a_61_74# vdd pfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M8 a_76_84# CLK a_66_6# vdd pfet w=2u l=0.4u + ad=0p pd=0u as=0p ps=0u M9 vdd Q a_76_84# vdd pfet w=2u l=0.4u + ad=0p pd=0u as=0p ps=0u M10 gnd CLK a_2_6# gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M11 Q a_66_6# vdd vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M12 a_17_6# D gnd gnd nfet w=2u l=0.4u + ad=0p pd=0u as=0p ps=0u M13 a_22_6# a_2_6# a_17_6# gnd nfet w=2u l=0.4u + ad=0p pd=0u as=0p ps=0u M14 a_31_6# CLK a_22_6# gnd nfet w=2u l=0.4u + ad=0p pd=0u as=0p ps=0u M15 gnd a_34_4# a_31_6# gnd nfet w=2u l=0.4u + ad=0p pd=0u as=0p ps=0u M16 a_34_4# a_22_6# gnd gnd nfet w=2u l=0.4u + ad=0p pd=0u as=0p ps=0u M17 a_61_6# a_34_4# gnd gnd nfet w=2u l=0.4u + ad=0p pd=0u as=0p ps=0u M18 a_66_6# CLK a_61_6# gnd nfet w=2u l=0.4u + ad=0p pd=0u as=0p ps=0u M19 a_76_6# a_2_6# a_66_6# gnd nfet w=2u l=0.4u + ad=0p pd=0u as=0p ps=0u M20 gnd Q a_76_6# gnd nfet w=2u l=0.4u + ad=0p pd=0u as=0p ps=0u M21 Q a_66_6# gnd gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u .ends DFFPOSX1 .subckt DFFSR gnd vdd D S R Q CLK M0 a_2_6# R vdd vdd pfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M1 vdd a_10_61# a_2_6# vdd pfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M2 a_10_61# a_23_27# vdd vdd pfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M3 vdd S a_10_61# vdd pfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M4 a_23_27# a_47_71# a_2_6# vdd pfet w=2u l=0.4u + ad=0p pd=0u as=0p ps=0u M5 a_57_6# a_47_4# a_23_27# vdd pfet w=2u l=0.4u + ad=0p pd=0u as=0p ps=0u M6 vdd D a_57_6# vdd pfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M7 vdd a_47_71# a_47_4# vdd pfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M8 a_47_71# CLK vdd vdd pfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M9 a_105_6# a_47_71# a_10_61# vdd pfet w=2u l=0.4u + ad=0p pd=0u as=0p ps=0u M10 a_113_6# a_47_4# a_105_6# vdd pfet w=2u l=0.4u + ad=0p pd=0u as=0p ps=0u M11 a_122_6# a_105_6# vdd vdd pfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M12 vdd R a_122_6# vdd pfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M13 a_113_6# a_122_6# vdd vdd pfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M14 vdd S a_113_6# vdd pfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M15 vdd a_122_6# Q vdd pfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M16 a_10_6# R a_2_6# gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M17 gnd a_10_61# a_10_6# gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M18 a_26_6# a_23_27# gnd gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M19 a_10_61# S a_26_6# gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M20 a_23_27# a_47_4# a_2_6# gnd nfet w=2u l=0.4u + ad=0p pd=0u as=0p ps=0u M21 a_57_6# a_47_71# a_23_27# gnd nfet w=2u l=0.4u + ad=0p pd=0u as=0p ps=0u M22 gnd D a_57_6# gnd nfet w=2u l=0.4u + ad=0p pd=0u as=0p ps=0u M23 gnd a_47_71# a_47_4# gnd nfet w=2u l=0.4u + ad=0p pd=0u as=0p ps=0u M24 a_47_71# CLK gnd gnd nfet w=2u l=0.4u + ad=0p pd=0u as=0p ps=0u M25 a_105_6# a_47_4# a_10_61# gnd nfet w=2u l=0.4u + ad=0p pd=0u as=0p ps=0u M26 a_113_6# a_47_71# a_105_6# gnd nfet w=2u l=0.4u + ad=0p pd=0u as=0p ps=0u M27 a_130_6# a_105_6# a_122_6# gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M28 gnd R a_130_6# gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M29 a_146_6# a_122_6# gnd gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M30 a_113_6# S a_146_6# gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M31 gnd a_122_6# Q gnd nfet w=2u l=0.4u + ad=0p pd=0u as=0p ps=0u .ends DFFSR .subckt FAX1 gnd vdd A B C YC YS M0 vdd A a_2_54# vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M1 a_2_54# B vdd vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M2 a_25_6# C a_2_54# vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M3 a_33_54# B a_25_6# vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M4 vdd A a_33_54# vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M5 a_46_54# A vdd vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M6 vdd B a_46_54# vdd pfet w=7.2u l=0.4u + ad=0p pd=0u as=0p ps=0u M7 a_46_54# C vdd vdd pfet w=7.2u l=0.4u + ad=0p pd=0u as=0p ps=0u M8 a_70_6# a_25_6# a_46_54# vdd pfet w=7.2u l=0.4u + ad=0p pd=0u as=0p ps=0u M9 a_79_46# C a_70_6# vdd pfet w=9.6u l=0.4u + ad=0p pd=0u as=0p ps=0u M10 a_84_46# B a_79_46# vdd pfet w=9.6u l=0.4u + ad=0p pd=0u as=0p ps=0u M11 vdd A a_84_46# vdd pfet w=9.6u l=0.4u + ad=0p pd=0u as=0p ps=0u M12 YS a_70_6# vdd vdd pfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M13 YC a_25_6# vdd vdd pfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M14 gnd A a_2_6# gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M15 a_2_6# B gnd gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M16 a_25_6# C a_2_6# gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M17 a_33_6# B a_25_6# gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M18 gnd A a_33_6# gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M19 a_46_6# A gnd gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M20 gnd B a_46_6# gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M21 a_46_6# C gnd gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M22 a_70_6# a_25_6# a_46_6# gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M23 a_79_6# C a_70_6# gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M24 a_84_6# B a_79_6# gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M25 gnd A a_84_6# gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M26 YS a_70_6# gnd gnd nfet w=2u l=0.4u + ad=0p pd=0u as=0p ps=0u M27 YC a_25_6# gnd gnd nfet w=2u l=0.4u + ad=0p pd=0u as=0p ps=0u .ends FAX1 .subckt HAX1 vdd gnd YC A B YS M0 vdd A a_2_74# vdd pfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M1 a_2_74# B vdd vdd pfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M2 vdd a_2_74# YC vdd pfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M3 a_41_74# a_2_74# vdd vdd pfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M4 a_49_54# B a_41_74# vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M5 vdd A a_49_54# vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M6 YS a_41_74# vdd vdd pfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M7 a_9_6# A gnd gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M8 a_2_74# B a_9_6# gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M9 gnd a_2_74# YC gnd nfet w=2u l=0.4u + ad=0p pd=0u as=0p ps=0u M10 a_38_6# a_2_74# gnd gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M11 a_41_74# B a_38_6# gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M12 a_38_6# A a_41_74# gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M13 YS a_41_74# gnd gnd nfet w=2u l=0.4u + ad=0p pd=0u as=0p ps=0u .ends HAX1 .subckt INVX1 A Y vdd gnd M0 Y A vdd vdd pfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M1 Y A gnd gnd nfet w=2u l=0.4u + ad=0p pd=0u as=0p ps=0u .ends INVX1 .subckt INVX2 vdd gnd Y A M0 Y A vdd vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M1 Y A gnd gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u .ends INVX2 .subckt INVX4 vdd gnd Y A M0 Y A vdd vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M1 vdd A Y vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M2 Y A gnd gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M3 gnd A Y gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u .ends INVX4 .subckt INVX8 vdd gnd A Y M0 Y A vdd vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M1 vdd A Y vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M2 Y A vdd vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M3 vdd A Y vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M4 Y A gnd gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M5 gnd A Y gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M6 Y A gnd gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M7 gnd A Y gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u .ends INVX8 .subckt LATCH D Q gnd vdd CLK M0 vdd CLK a_2_6# vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M1 a_18_74# D vdd vdd pfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M2 a_23_6# a_2_6# a_18_74# vdd pfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M3 a_35_84# CLK a_23_6# vdd pfet w=2u l=0.4u + ad=0p pd=0u as=0p ps=0u M4 vdd Q a_35_84# vdd pfet w=2u l=0.4u + ad=0p pd=0u as=0p ps=0u M5 gnd CLK a_2_6# gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M6 Q a_23_6# vdd vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M7 a_18_6# D gnd gnd nfet w=2u l=0.4u + ad=0p pd=0u as=0p ps=0u M8 a_23_6# CLK a_18_6# gnd nfet w=2u l=0.4u + ad=0p pd=0u as=0p ps=0u M9 a_35_6# a_2_6# a_23_6# gnd nfet w=2u l=0.4u + ad=0p pd=0u as=0p ps=0u M10 gnd Q a_35_6# gnd nfet w=2u l=0.4u + ad=0p pd=0u as=0p ps=0u M11 Q a_23_6# gnd gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u .ends LATCH .subckt MUX2X1 S vdd gnd Y A B M0 vdd S a_2_10# vdd pfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M1 a_17_50# B vdd vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M2 Y S a_17_50# vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M3 a_30_54# a_2_10# Y vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M4 vdd A a_30_54# vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M5 gnd S a_2_10# gnd nfet w=2u l=0.4u + ad=0p pd=0u as=0p ps=0u M6 a_17_10# B gnd gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M7 Y a_2_10# a_17_10# gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M8 a_30_10# S Y gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M9 gnd A a_30_10# gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u .ends MUX2X1 .subckt NAND2X1 vdd Y gnd A B M0 Y A vdd vdd pfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M1 vdd B Y vdd pfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M2 a_9_6# A gnd gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M3 Y B a_9_6# gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u .ends NAND2X1 .subckt NAND3X1 B vdd gnd A C Y M0 Y A vdd vdd pfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M1 vdd B Y vdd pfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M2 Y C vdd vdd pfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M3 a_9_6# A gnd gnd nfet w=6u l=0.4u + ad=0p pd=0u as=0p ps=0u M4 a_14_6# B a_9_6# gnd nfet w=6u l=0.4u + ad=0p pd=0u as=0p ps=0u M5 Y C a_14_6# gnd nfet w=6u l=0.4u + ad=0p pd=0u as=0p ps=0u .ends NAND3X1 .subckt NOR2X1 vdd B gnd Y A M0 a_9_54# A vdd vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M1 Y B a_9_54# vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M2 Y A gnd gnd nfet w=2u l=0.4u + ad=0p pd=0u as=0p ps=0u M3 gnd B Y gnd nfet w=2u l=0.4u + ad=0p pd=0u as=0p ps=0u .ends NOR2X1 .subckt NOR3X1 vdd gnd B C A Y M0 vdd A a_2_64# vdd pfet w=6u l=0.4u + ad=0p pd=0u as=0p ps=0u M1 a_2_64# A vdd vdd pfet w=6u l=0.4u + ad=0p pd=0u as=0p ps=0u M2 a_25_64# B a_2_64# vdd pfet w=6u l=0.4u + ad=0p pd=0u as=0p ps=0u M3 a_2_64# B a_25_64# vdd pfet w=6u l=0.4u + ad=0p pd=0u as=0p ps=0u M4 Y C a_25_64# vdd pfet w=6u l=0.4u + ad=0p pd=0u as=0p ps=0u M5 a_25_64# C Y vdd pfet w=6u l=0.4u + ad=0p pd=0u as=0p ps=0u M6 Y A gnd gnd nfet w=2u l=0.4u + ad=0p pd=0u as=0p ps=0u M7 gnd B Y gnd nfet w=2u l=0.4u + ad=0p pd=0u as=0p ps=0u M8 Y C gnd gnd nfet w=2u l=0.4u + ad=0p pd=0u as=0p ps=0u .ends NOR3X1 .subckt OAI21X1 gnd vdd A B Y C M0 a_9_54# A vdd vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M1 Y B a_9_54# vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M2 vdd C Y vdd pfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M3 gnd A a_2_6# gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M4 a_2_6# B gnd gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M5 Y C a_2_6# gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u .ends OAI21X1 .subckt OAI22X1 gnd vdd D C A B Y M0 a_9_54# A vdd vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M1 Y B a_9_54# vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M2 a_28_54# D Y vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M3 vdd C a_28_54# vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M4 gnd A a_2_6# gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M5 a_2_6# B gnd gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M6 Y D a_2_6# gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M7 a_2_6# C Y gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u .ends OAI22X1 .subckt OR2X1 Y B vdd gnd A M0 a_9_54# A a_2_54# vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M1 vdd B a_9_54# vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M2 Y a_2_54# vdd vdd pfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M3 a_2_54# A gnd gnd nfet w=2u l=0.4u + ad=0p pd=0u as=0p ps=0u M4 gnd B a_2_54# gnd nfet w=2u l=0.4u + ad=0p pd=0u as=0p ps=0u M5 Y a_2_54# gnd gnd nfet w=2u l=0.4u + ad=0p pd=0u as=0p ps=0u .ends OR2X1 .subckt OR2X2 Y B vdd gnd A M0 a_9_54# A a_2_54# vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M1 vdd B a_9_54# vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M2 Y a_2_54# vdd vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M3 a_2_54# A gnd gnd nfet w=2u l=0.4u + ad=0p pd=0u as=0p ps=0u M4 gnd B a_2_54# gnd nfet w=2u l=0.4u + ad=0p pd=0u as=0p ps=0u M5 Y a_2_54# gnd gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u .ends OR2X2 .subckt PADINC DI vdd2 gnd2 vdd gnd YPAD M0 vdd2 vdd2 YPAD vdd2 hpfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M1 vdd2 vdd2 YPAD vdd2 hpfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M2 YPAD vdd2 vdd2 vdd2 hpfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M3 YPAD vdd2 vdd2 vdd2 hpfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M4 vdd2 vdd2 YPAD vdd2 hpfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M5 vdd2 vdd2 YPAD vdd2 hpfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M6 YPAD vdd2 vdd2 vdd2 hpfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M7 YPAD vdd2 vdd2 vdd2 hpfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M8 vdd2 vdd2 YPAD vdd2 hpfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M9 vdd2 vdd2 YPAD vdd2 hpfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M10 YPAD vdd2 vdd2 vdd2 hpfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M11 YPAD vdd2 vdd2 vdd2 hpfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M12 vdd2 a_31_658# YPAD vdd2 hpfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M13 vdd2 a_31_658# YPAD vdd2 hpfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M14 YPAD a_31_658# vdd2 vdd2 hpfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M15 YPAD a_31_658# vdd2 vdd2 hpfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M16 gnd gnd2 a_15_420# gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M17 a_32_420# a_15_420# gnd gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M18 gnd gnd2 a_41_540# gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M19 a_41_540# gnd2 gnd gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M20 gnd gnd2 a_41_540# gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M21 a_41_540# gnd2 gnd gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M22 gnd gnd2 a_41_540# gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M23 a_41_540# a_15_420# gnd gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M24 gnd a_15_420# a_41_540# gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M25 a_41_540# a_15_420# gnd gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M26 gnd a_15_420# a_41_540# gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M27 a_41_540# a_15_420# gnd gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M28 a_41_420# a_32_420# a_41_540# gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M29 a_41_540# a_32_420# a_41_420# gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M30 a_41_420# a_32_420# a_41_540# gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M31 a_41_540# a_32_420# a_41_420# gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M32 gnd a_176_413# a_31_658# gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M33 a_176_413# a_41_420# gnd gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M34 gnd a_202_572# a_31_343# gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M35 a_202_572# a_41_540# gnd gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M36 a_329_420# a_326_417# gnd gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M37 gnd a_326_417# a_329_420# gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M38 a_329_420# a_326_417# gnd gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M39 gnd a_326_417# a_329_420# gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M40 a_329_420# a_326_417# gnd gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M41 gnd a_326_417# a_329_420# gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M42 DI a_329_420# gnd gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M43 gnd a_329_420# DI gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M44 DI a_329_420# gnd gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M45 gnd a_329_420# DI gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M46 DI a_329_420# gnd gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M47 gnd a_329_420# DI gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M48 vdd gnd2 a_15_420# vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M49 a_32_420# a_15_420# vdd vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M50 vdd gnd2 a_41_420# vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M51 a_41_420# gnd2 vdd vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M52 vdd gnd2 a_41_420# vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M53 a_41_420# gnd2 vdd vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M54 vdd gnd2 a_41_420# vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M55 a_41_420# a_32_420# vdd vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M56 vdd a_32_420# a_41_420# vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M57 a_41_420# a_32_420# vdd vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M58 vdd a_32_420# a_41_420# vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M59 a_41_420# a_32_420# vdd vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M60 a_41_540# a_15_420# a_41_420# vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M61 a_41_420# a_15_420# a_41_540# vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M62 a_41_540# a_15_420# a_41_420# vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M63 a_41_420# a_15_420# a_41_540# vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M64 vdd a_176_413# a_31_658# vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M65 a_176_413# a_41_420# vdd vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M66 vdd a_202_572# a_31_343# vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M67 a_202_572# a_41_540# vdd vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M68 a_329_420# a_326_417# vdd vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M69 vdd a_326_417# a_329_420# vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M70 a_329_420# a_326_417# vdd vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M71 vdd a_326_417# a_329_420# vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M72 a_329_420# a_326_417# vdd vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M73 vdd a_326_417# a_329_420# vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M74 DI a_329_420# vdd vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M75 vdd a_329_420# DI vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M76 DI a_329_420# vdd vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M77 vdd a_329_420# DI vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M78 DI a_329_420# vdd vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M79 vdd a_329_420# DI vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M80 gnd2 a_31_343# YPAD gnd2 hnfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M81 gnd2 a_31_343# YPAD gnd2 hnfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M82 YPAD gnd2 gnd2 gnd2 hnfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M83 YPAD gnd2 gnd2 gnd2 hnfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M84 gnd2 gnd2 YPAD gnd2 hnfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M85 gnd2 gnd2 YPAD gnd2 hnfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M86 YPAD gnd2 gnd2 gnd2 hnfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M87 gnd2 gnd2 YPAD gnd2 hnfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M88 YPAD gnd2 gnd2 gnd2 hnfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M89 gnd2 gnd2 YPAD gnd2 hnfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M90 YPAD gnd2 gnd2 gnd2 hnfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M91 YPAD gnd2 gnd2 gnd2 hnfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M92 gnd2 gnd2 YPAD gnd2 hnfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M93 gnd2 gnd2 YPAD gnd2 hnfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M94 YPAD gnd2 gnd2 gnd2 hnfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M95 YPAD gnd2 gnd2 gnd2 hnfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u R0 YPAD a_326_417# 100 .ends PADINC .subckt PADINOUT DI DO vdd2 gnd2 OEN vdd gnd YPAD M0 vdd2 vdd2 YPAD vdd2 hpfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M1 vdd2 vdd2 YPAD vdd2 hpfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M2 YPAD vdd2 vdd2 vdd2 hpfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M3 YPAD vdd2 vdd2 vdd2 hpfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M4 vdd2 vdd2 YPAD vdd2 hpfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M5 vdd2 vdd2 YPAD vdd2 hpfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M6 YPAD vdd2 vdd2 vdd2 hpfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M7 YPAD vdd2 vdd2 vdd2 hpfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M8 vdd2 vdd2 YPAD vdd2 hpfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M9 vdd2 vdd2 YPAD vdd2 hpfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M10 YPAD vdd2 vdd2 vdd2 hpfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M11 YPAD vdd2 vdd2 vdd2 hpfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M12 vdd2 a_31_658# YPAD vdd2 hpfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M13 vdd2 a_31_658# YPAD vdd2 hpfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M14 YPAD a_31_658# vdd2 vdd2 hpfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M15 YPAD a_31_658# vdd2 vdd2 hpfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M16 gnd OEN a_15_420# gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M17 a_32_420# a_15_420# gnd gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M18 gnd DO a_41_540# gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M19 a_41_540# DO gnd gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M20 gnd DO a_41_540# gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M21 a_41_540# DO gnd gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M22 gnd DO a_41_540# gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M23 a_41_540# a_15_420# gnd gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M24 gnd a_15_420# a_41_540# gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M25 a_41_540# a_15_420# gnd gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M26 gnd a_15_420# a_41_540# gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M27 a_41_540# a_15_420# gnd gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M28 a_41_420# a_32_420# a_41_540# gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M29 a_41_540# a_32_420# a_41_420# gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M30 a_41_420# a_32_420# a_41_540# gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M31 a_41_540# a_32_420# a_41_420# gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M32 gnd a_176_413# a_31_658# gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M33 a_176_413# a_41_420# gnd gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M34 gnd a_202_572# a_31_343# gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M35 a_202_572# a_41_540# gnd gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M36 a_329_420# a_326_417# gnd gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M37 gnd a_326_417# a_329_420# gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M38 a_329_420# a_326_417# gnd gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M39 gnd a_326_417# a_329_420# gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M40 a_329_420# a_326_417# gnd gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M41 gnd a_326_417# a_329_420# gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M42 DI a_329_420# gnd gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M43 gnd a_329_420# DI gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M44 DI a_329_420# gnd gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M45 gnd a_329_420# DI gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M46 DI a_329_420# gnd gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M47 gnd a_329_420# DI gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M48 vdd OEN a_15_420# vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M49 a_32_420# a_15_420# vdd vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M50 vdd DO a_41_420# vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M51 a_41_420# DO vdd vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M52 vdd DO a_41_420# vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M53 a_41_420# DO vdd vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M54 vdd DO a_41_420# vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M55 a_41_420# a_32_420# vdd vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M56 vdd a_32_420# a_41_420# vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M57 a_41_420# a_32_420# vdd vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M58 vdd a_32_420# a_41_420# vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M59 a_41_420# a_32_420# vdd vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M60 a_41_540# a_15_420# a_41_420# vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M61 a_41_420# a_15_420# a_41_540# vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M62 a_41_540# a_15_420# a_41_420# vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M63 a_41_420# a_15_420# a_41_540# vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M64 vdd a_176_413# a_31_658# vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M65 a_176_413# a_41_420# vdd vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M66 vdd a_202_572# a_31_343# vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M67 a_202_572# a_41_540# vdd vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M68 a_329_420# a_326_417# vdd vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M69 vdd a_326_417# a_329_420# vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M70 a_329_420# a_326_417# vdd vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M71 vdd a_326_417# a_329_420# vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M72 a_329_420# a_326_417# vdd vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M73 vdd a_326_417# a_329_420# vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M74 DI a_329_420# vdd vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M75 vdd a_329_420# DI vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M76 DI a_329_420# vdd vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M77 vdd a_329_420# DI vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M78 DI a_329_420# vdd vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M79 vdd a_329_420# DI vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M80 gnd2 a_31_343# YPAD gnd2 hnfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M81 gnd2 a_31_343# YPAD gnd2 hnfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M82 YPAD gnd2 gnd2 gnd2 hnfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M83 YPAD gnd2 gnd2 gnd2 hnfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M84 gnd2 gnd2 YPAD gnd2 hnfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M85 gnd2 gnd2 YPAD gnd2 hnfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M86 YPAD gnd2 gnd2 gnd2 hnfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M87 gnd2 gnd2 YPAD gnd2 hnfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M88 YPAD gnd2 gnd2 gnd2 hnfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M89 gnd2 gnd2 YPAD gnd2 hnfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M90 YPAD gnd2 gnd2 gnd2 hnfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M91 YPAD gnd2 gnd2 gnd2 hnfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M92 gnd2 gnd2 YPAD gnd2 hnfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M93 gnd2 gnd2 YPAD gnd2 hnfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M94 YPAD gnd2 gnd2 gnd2 hnfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M95 YPAD gnd2 gnd2 gnd2 hnfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u R0 YPAD a_326_417# 100 .ends PADINOUT .subckt PADOUT DO vdd2 gnd2 vdd gnd YPAD M0 vdd2 vdd2 YPAD vdd2 hpfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M1 vdd2 vdd2 YPAD vdd2 hpfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M2 YPAD vdd2 vdd2 vdd2 hpfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M3 YPAD vdd2 vdd2 vdd2 hpfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M4 vdd2 vdd2 YPAD vdd2 hpfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M5 vdd2 vdd2 YPAD vdd2 hpfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M6 YPAD vdd2 vdd2 vdd2 hpfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M7 YPAD vdd2 vdd2 vdd2 hpfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M8 vdd2 vdd2 YPAD vdd2 hpfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M9 vdd2 vdd2 YPAD vdd2 hpfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M10 YPAD vdd2 vdd2 vdd2 hpfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M11 YPAD vdd2 vdd2 vdd2 hpfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M12 vdd2 a_31_658# YPAD vdd2 hpfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M13 vdd2 a_31_658# YPAD vdd2 hpfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M14 YPAD a_31_658# vdd2 vdd2 hpfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M15 YPAD a_31_658# vdd2 vdd2 hpfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M16 gnd vdd a_15_420# gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M17 a_32_420# a_15_420# gnd gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M18 gnd DO a_41_540# gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M19 a_41_540# DO gnd gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M20 gnd DO a_41_540# gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M21 a_41_540# DO gnd gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M22 gnd DO a_41_540# gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M23 a_41_540# a_15_420# gnd gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M24 gnd a_15_420# a_41_540# gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M25 a_41_540# a_15_420# gnd gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M26 gnd a_15_420# a_41_540# gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M27 a_41_540# a_15_420# gnd gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M28 a_41_420# a_32_420# a_41_540# gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M29 a_41_540# a_32_420# a_41_420# gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M30 a_41_420# a_32_420# a_41_540# gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M31 a_41_540# a_32_420# a_41_420# gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M32 gnd a_176_413# a_31_658# gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M33 a_176_413# a_41_420# gnd gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M34 gnd a_202_572# a_31_343# gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M35 a_202_572# a_41_540# gnd gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M36 a_329_420# a_326_417# gnd gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M37 gnd a_326_417# a_329_420# gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M38 a_329_420# a_326_417# gnd gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M39 gnd a_326_417# a_329_420# gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M40 a_329_420# a_326_417# gnd gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M41 gnd a_326_417# a_329_420# gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M42 a_383_420# a_329_420# gnd gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M43 gnd a_329_420# a_383_420# gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M44 a_383_420# a_329_420# gnd gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M45 gnd a_329_420# a_383_420# gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M46 a_383_420# a_329_420# gnd gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M47 gnd a_329_420# a_383_420# gnd hnfet w=6u l=0.6u + ad=0p pd=0u as=0p ps=0u M48 vdd vdd a_15_420# vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M49 a_32_420# a_15_420# vdd vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M50 vdd DO a_41_420# vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M51 a_41_420# DO vdd vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M52 vdd DO a_41_420# vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M53 a_41_420# DO vdd vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M54 vdd DO a_41_420# vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M55 a_41_420# a_32_420# vdd vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M56 vdd a_32_420# a_41_420# vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M57 a_41_420# a_32_420# vdd vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M58 vdd a_32_420# a_41_420# vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M59 a_41_420# a_32_420# vdd vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M60 a_41_540# a_15_420# a_41_420# vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M61 a_41_420# a_15_420# a_41_540# vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M62 a_41_540# a_15_420# a_41_420# vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M63 a_41_420# a_15_420# a_41_540# vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M64 vdd a_176_413# a_31_658# vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M65 a_176_413# a_41_420# vdd vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M66 vdd a_202_572# a_31_343# vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M67 a_202_572# a_41_540# vdd vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M68 a_329_420# a_326_417# vdd vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M69 vdd a_326_417# a_329_420# vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M70 a_329_420# a_326_417# vdd vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M71 vdd a_326_417# a_329_420# vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M72 a_329_420# a_326_417# vdd vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M73 vdd a_326_417# a_329_420# vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M74 a_383_420# a_329_420# vdd vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M75 vdd a_329_420# a_383_420# vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M76 a_383_420# a_329_420# vdd vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M77 vdd a_329_420# a_383_420# vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M78 a_383_420# a_329_420# vdd vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M79 vdd a_329_420# a_383_420# vdd hpfet w=10.4u l=0.6u + ad=0p pd=0u as=0p ps=0u M80 gnd2 a_31_343# YPAD gnd2 hnfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M81 gnd2 a_31_343# YPAD gnd2 hnfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M82 YPAD gnd2 gnd2 gnd2 hnfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M83 YPAD gnd2 gnd2 gnd2 hnfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M84 gnd2 gnd2 YPAD gnd2 hnfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M85 gnd2 gnd2 YPAD gnd2 hnfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M86 YPAD gnd2 gnd2 gnd2 hnfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M87 gnd2 gnd2 YPAD gnd2 hnfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M88 YPAD gnd2 gnd2 gnd2 hnfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M89 gnd2 gnd2 YPAD gnd2 hnfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M90 YPAD gnd2 gnd2 gnd2 hnfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M91 YPAD gnd2 gnd2 gnd2 hnfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M92 gnd2 gnd2 YPAD gnd2 hnfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M93 gnd2 gnd2 YPAD gnd2 hnfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M94 YPAD gnd2 gnd2 gnd2 hnfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u M95 YPAD gnd2 gnd2 gnd2 hnfet w=35u l=0.6u + ad=0p pd=0u as=0p ps=0u R0 YPAD a_326_417# 100 .ends PADOUT .subckt TBUFX1 vdd gnd EN A Y M0 a_9_6# EN vdd vdd pfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M1 a_26_54# a_9_6# Y vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M2 vdd A a_26_54# vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M3 a_9_6# EN gnd gnd nfet w=2u l=0.4u + ad=0p pd=0u as=0p ps=0u M4 a_26_6# EN Y gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M5 gnd A a_26_6# gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u .ends TBUFX1 .subckt TBUFX2 vdd gnd A EN Y M0 a_9_6# EN vdd vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M1 Y a_9_6# a_18_54# vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M2 a_18_54# a_9_6# Y vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M3 vdd A a_18_54# vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M4 a_18_54# A vdd vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M5 a_9_6# EN gnd gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M6 Y EN a_18_6# gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M7 a_18_6# EN Y gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M8 gnd A a_18_6# gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M9 a_18_6# A gnd gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u .ends TBUFX2 .subckt XNOR2X1 A B gnd vdd Y M0 vdd A a_2_6# vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M1 a_18_54# a_12_41# vdd vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M2 Y a_2_6# a_18_54# vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M3 a_35_54# A Y vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M4 vdd B a_35_54# vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M5 a_12_41# B vdd vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M6 gnd A a_2_6# gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M7 a_18_6# a_12_41# gnd gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M8 Y A a_18_6# gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M9 a_35_6# a_2_6# Y gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M10 gnd B a_35_6# gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M11 a_12_41# B gnd gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u .ends XNOR2X1 .subckt XOR2X1 Y vdd B A gnd M0 vdd A a_2_6# vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M1 a_18_54# a_13_43# vdd vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M2 Y A a_18_54# vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M3 a_35_54# a_2_6# Y vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M4 vdd B a_35_54# vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M5 a_13_43# B vdd vdd pfet w=8u l=0.4u + ad=0p pd=0u as=0p ps=0u M6 gnd A a_2_6# gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M7 a_18_6# a_13_43# gnd gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M8 Y a_2_6# a_18_6# gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M9 a_35_6# A Y gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M10 gnd B a_35_6# gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u M11 a_13_43# B gnd gnd nfet w=4u l=0.4u + ad=0p pd=0u as=0p ps=0u .ends XOR2X1 qflow-1.1.23/tech/osu035/Makefile.in0000644000175000001440000000167312526236535015504 0ustar timusers# # qflow project included technology osu035 files # # Main compiler arguments CFLAGS = @CFLAGS@ DEFS = @DEFS@ LIBS = @LIBS@ LDFLAGS = @LDFLAGS@ INSTALL = @INSTALL@ QFLOW_LIB_DIR = @QFLOW_LIB_DIR@ TECH_FILES = osu035.par osu035_stdcells.lef osu035.sh TECH_FILES += osu035_stdcells.sp osu035.magicrc osu035.prm TECH_FILES += SCN4M_SUBM.20.tech osu035_stdcells.lib TECH_FILES += osu035_stdcells.v TECHINSTALL = ${QFLOW_LIB_DIR}/tech # Substitute the target qflow tech directory name in .magicrc so that magic # can find the OSU035 techfile all: osu035.magicrc.in $(RM) -f osu035.magicrc cat osu035.magicrc.in | sed -e \ '/QFLOW_LIB_DIR/s#QFLOW_LIB_DIR#$(QFLOW_LIB_DIR)#' \ > osu035.magicrc install: ${TECH_FILES} @echo "Installing osu035 tech files" $(INSTALL) -d $(DESTDIR)$(TECHINSTALL)/osu035 for target in $(TECH_FILES); do \ $(INSTALL) $$target $(DESTDIR)$(TECHINSTALL)/osu035 ;\ done clean: $(RM) -f osu035.magicrc uninstall: qflow-1.1.23/tech/osu035/osu035_stdcells.lib0000755000175000001440000100746312526236535017071 0ustar timusers/* delay model : typ check model : typ power model : typ capacitance model : typ other model : typ */ library(osu035_stdcells) { delay_model : table_lookup; in_place_swap_mode : match_footprint; /* unit attributes */ time_unit : "1ns"; voltage_unit : "1V"; current_unit : "1uA"; pulling_resistance_unit : "1kohm"; leakage_power_unit : "1nW"; capacitive_load_unit (1,pf); slew_upper_threshold_pct_rise : 80; slew_lower_threshold_pct_rise : 20; slew_upper_threshold_pct_fall : 80; slew_lower_threshold_pct_fall : 20; input_threshold_pct_rise : 50; input_threshold_pct_fall : 50; output_threshold_pct_rise : 50; output_threshold_pct_fall : 50; nom_process : 1; nom_voltage : 3.3; nom_temperature : 25; operating_conditions ( typical ) { process : 1; voltage : 3.3; temperature : 25; } default_operating_conditions : typical; lu_table_template(delay_template_5x1) { variable_1 : input_net_transition; index_1 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0"); } lu_table_template(delay_template_5x5) { variable_1 : total_output_net_capacitance; variable_2 : input_net_transition; index_1 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0"); index_2 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0"); } lu_table_template(delay_template_5x6) { variable_1 : total_output_net_capacitance; variable_2 : input_net_transition; index_1 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0"); index_2 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"); } lu_table_template(delay_template_6x1) { variable_1 : input_net_transition; index_1 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"); } lu_table_template(delay_template_6x6) { variable_1 : total_output_net_capacitance; variable_2 : input_net_transition; index_1 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"); index_2 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"); } power_lut_template(energy_template_5x5) { variable_1 : total_output_net_capacitance; variable_2 : input_transition_time; index_1 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0"); index_2 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0"); } power_lut_template(energy_template_5x6) { variable_1 : total_output_net_capacitance; variable_2 : input_transition_time; index_1 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0"); index_2 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"); } power_lut_template(energy_template_6x6) { variable_1 : total_output_net_capacitance; variable_2 : input_transition_time; index_1 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"); index_2 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"); } lu_table_template(hold_template_3x5) { variable_1 : related_pin_transition; variable_2 : constrained_pin_transition; index_1 ("1000.0, 1001.0, 1002.0"); index_2 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0"); } lu_table_template(hold_template_3x6) { variable_1 : related_pin_transition; variable_2 : constrained_pin_transition; index_1 ("1000.0, 1001.0, 1002.0"); index_2 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"); } power_lut_template(passive_energy_template_5x1) { variable_1 : input_transition_time; index_1 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0"); } power_lut_template(passive_energy_template_6x1) { variable_1 : input_transition_time; index_1 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"); } lu_table_template(recovery_template_3x6) { variable_1 : related_pin_transition; variable_2 : constrained_pin_transition; index_1 ("1000.0, 1001.0, 1002.0"); index_2 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"); } lu_table_template(recovery_template_6x6) { variable_1 : related_pin_transition; variable_2 : constrained_pin_transition; index_1 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"); index_2 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"); } lu_table_template(removal_template_3x6) { variable_1 : related_pin_transition; variable_2 : constrained_pin_transition; index_1 ("1000.0, 1001.0, 1002.0"); index_2 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"); } lu_table_template(setup_template_3x5) { variable_1 : related_pin_transition; variable_2 : constrained_pin_transition; index_1 ("1000.0, 1001.0, 1002.0"); index_2 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0"); } lu_table_template(setup_template_3x6) { variable_1 : related_pin_transition; variable_2 : constrained_pin_transition; index_1 ("1000.0, 1001.0, 1002.0"); index_2 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"); } /* --------------- * * Design : AND2X1 * * --------------- */ cell (AND2X1) { area : 128; cell_leakage_power : 0.0513347; pin(A) { direction : input; capacitance : 0.0180284; rise_capacitance : 0.0179311; fall_capacitance : 0.0180284; } pin(B) { direction : input; capacitance : 0.0177842; rise_capacitance : 0.0177262; fall_capacitance : 0.0177842; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.411047; function : "(A B)"; timing() { related_pin : "A"; timing_sense : positive_unate; cell_rise(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.108267, 0.115227, 0.116641, 0.115085, 0.094443", \ "0.158679, 0.162618, 0.169052, 0.170926, 0.152952", \ "0.235934, 0.242278, 0.247779, 0.251431, 0.236307", \ "0.468696, 0.475393, 0.482452, 0.486731, 0.476102", \ "0.857048, 0.863687, 0.875958, 0.875848, 0.866711"); } rise_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0678, 0.0708, 0.081, 0.0852, 0.0936", \ "0.1338, 0.1392, 0.1434, 0.1494, 0.1584", \ "0.2478, 0.2508, 0.2538, 0.2568, 0.2676", \ "0.5982, 0.5988, 0.6006, 0.6024, 0.6108", \ "1.1832, 1.1826, 1.1832, 1.1844, 1.1892"); } cell_fall(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.123474, 0.150705, 0.20696, 0.245293, 0.349578", \ "0.167426, 0.200178, 0.257706, 0.295507, 0.406035", \ "0.23671, 0.269962, 0.32774, 0.366248, 0.481671", \ "0.442621, 0.478354, 0.535098, 0.573893, 0.691812", \ "0.783324, 0.81935, 0.875945, 0.91488, 1.03407"); } fall_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.058568, 0.06, 0.0696, 0.0756, 0.0882", \ "0.111, 0.1134, 0.1218, 0.1236, 0.1368", \ "0.2004, 0.2004, 0.2052, 0.2064, 0.2196", \ "0.4806, 0.4806, 0.4812, 0.483, 0.4896", \ "0.9504, 0.9504, 0.9504, 0.951, 0.9546"); } } timing() { related_pin : "B"; timing_sense : positive_unate; cell_rise(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.107423, 0.107813, 0.099498, 0.087485, 0.034653", \ "0.157773, 0.157638, 0.153984, 0.144848, 0.097323", \ "0.234481, 0.242097, 0.232902, 0.226536, 0.181775", \ "0.46756, 0.474869, 0.468841, 0.460915, 0.424671", \ "0.855999, 0.863097, 0.857077, 0.849535, 0.815209"); } rise_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0678, 0.0732, 0.0828, 0.0864, 0.102", \ "0.1338, 0.1392, 0.1446, 0.1506, 0.1596", \ "0.2478, 0.2502, 0.2544, 0.2568, 0.2718", \ "0.5982, 0.5982, 0.6, 0.6012, 0.6126", \ "1.1832, 1.1826, 1.1826, 1.1832, 1.1886"); } cell_fall(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.137572, 0.177392, 0.246292, 0.292726, 0.431469", \ "0.187201, 0.224568, 0.294037, 0.342471, 0.486923", \ "0.256505, 0.296893, 0.364747, 0.413359, 0.560093", \ "0.462713, 0.501671, 0.571649, 0.61918, 0.766806", \ "0.80352, 0.842527, 0.9126, 0.959694, 1.10837"); } fall_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0606, 0.0624, 0.0744, 0.0768, 0.09", \ "0.1146, 0.1152, 0.1164, 0.1212, 0.1314", \ "0.201, 0.2004, 0.2052, 0.2058, 0.2148", \ "0.48, 0.4806, 0.4812, 0.4824, 0.4866", \ "0.9504, 0.9504, 0.9504, 0.951, 0.9534"); } } internal_power() { related_pin : "A"; rise_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.069489, 0.094628, 0.172783, 0.242566, 0.48434", \ "0.06923, 0.096961, 0.174926, 0.23878, 0.474601", \ "0.073424, 0.097432, 0.174179, 0.237701, 0.46775", \ "0.074019, 0.098168, 0.173908, 0.236995, 0.461853", \ "0.074108, 0.098378, 0.171142, 0.237264, 0.459949"); } fall_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.254311, 0.278202, 0.357205, 0.427364, 0.668783", \ "0.256995, 0.278773, 0.359187, 0.425411, 0.661228", \ "0.258334, 0.280603, 0.363645, 0.425442, 0.656188", \ "0.256529, 0.284011, 0.362775, 0.427305, 0.653995", \ "0.2572, 0.284942, 0.363314, 0.427933, 0.653552"); } } internal_power() { related_pin : "B"; rise_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.065427, 0.086108, 0.177844, 0.254002, 0.515592", \ "0.063198, 0.086789, 0.179034, 0.248707, 0.504837", \ "0.06412, 0.091234, 0.176518, 0.244691, 0.497017", \ "0.065099, 0.091507, 0.172647, 0.2435, 0.490834", \ "0.065457, 0.09167, 0.17286, 0.243129, 0.488613"); } fall_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.312337, 0.342239, 0.434071, 0.511259, 0.775046", \ "0.318575, 0.34494, 0.433356, 0.506027, 0.764892", \ "0.321264, 0.351026, 0.433373, 0.507129, 0.759555", \ "0.321388, 0.352838, 0.436822, 0.507263, 0.756243", \ "0.322341, 0.353608, 0.437701, 0.507994, 0.755192"); } } } } /* --------------- * * Design : AND2X2 * * --------------- */ cell (AND2X2) { area : 128; cell_leakage_power : 0.0522786; pin(A) { direction : input; capacitance : 0.0180033; rise_capacitance : 0.0179578; fall_capacitance : 0.0180033; } pin(B) { direction : input; capacitance : 0.0177358; rise_capacitance : 0.0177358; fall_capacitance : 0.0177159; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.831032; function : "(A B)"; timing() { related_pin : "A"; timing_sense : positive_unate; cell_rise(delay_template_5x5) { index_1 ("0.03, 0.08, 0.16, 0.4, 0.8"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.13066, 0.141518, 0.159321, 0.165492, 0.164762", \ "0.181574, 0.199647, 0.215336, 0.221674, 0.221527", \ "0.260293, 0.278099, 0.297021, 0.301113, 0.301757", \ "0.489974, 0.506691, 0.527325, 0.532019, 0.534884", \ "0.872706, 0.889359, 0.909559, 0.914605, 0.918514"); } rise_transition(delay_template_5x5) { index_1 ("0.03, 0.08, 0.16, 0.4, 0.8"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0762, 0.0762, 0.0828, 0.0918, 0.1014", \ "0.1404, 0.1398, 0.1488, 0.1494, 0.1608", \ "0.2496, 0.2508, 0.255, 0.2574, 0.267", \ "0.5928, 0.5928, 0.5952, 0.5964, 0.603", \ "1.17, 1.1706, 1.17, 1.1712, 1.1748"); } cell_fall(delay_template_5x5) { index_1 ("0.03, 0.08, 0.16, 0.4, 0.8"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.154045, 0.189588, 0.254769, 0.298209, 0.422264", \ "0.205871, 0.243003, 0.308255, 0.35275, 0.479943", \ "0.278538, 0.314963, 0.381175, 0.426137, 0.555773", \ "0.485682, 0.522106, 0.589474, 0.633809, 0.765165", \ "0.830154, 0.866196, 0.933544, 0.977651, 1.10933"); } fall_transition(delay_template_5x5) { index_1 ("0.03, 0.08, 0.16, 0.4, 0.8"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0702, 0.0702, 0.0822, 0.0786, 0.0966", \ "0.1236, 0.1206, 0.1272, 0.1326, 0.1416", \ "0.2088, 0.2076, 0.2118, 0.2154, 0.2268", \ "0.4884, 0.4884, 0.4896, 0.4908, 0.4962", \ "0.9642, 0.9636, 0.9642, 0.9642, 0.9666"); } } timing() { related_pin : "B"; timing_sense : positive_unate; cell_rise(delay_template_5x5) { index_1 ("0.03, 0.08, 0.16, 0.4, 0.8"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.130915, 0.133142, 0.134654, 0.127567, 0.091505", \ "0.182107, 0.187685, 0.190787, 0.185927, 0.150964", \ "0.26079, 0.268191, 0.270531, 0.266214, 0.234452", \ "0.490507, 0.497373, 0.500426, 0.496844, 0.47083", \ "0.873234, 0.880733, 0.883008, 0.879476, 0.854232"); } rise_transition(delay_template_5x5) { index_1 ("0.03, 0.08, 0.16, 0.4, 0.8"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0762, 0.081, 0.0852, 0.0936, 0.1038", \ "0.1404, 0.1434, 0.1494, 0.1548, 0.165", \ "0.2496, 0.2502, 0.255, 0.2568, 0.2724", \ "0.5928, 0.5934, 0.594, 0.5952, 0.6054", \ "1.17, 1.17, 1.1706, 1.1712, 1.1748"); } cell_fall(delay_template_5x5) { index_1 ("0.03, 0.08, 0.16, 0.4, 0.8"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.172065, 0.211593, 0.287991, 0.33826, 0.488621", \ "0.224455, 0.264242, 0.340571, 0.391515, 0.547494", \ "0.296521, 0.336837, 0.413898, 0.464626, 0.622647", \ "0.504477, 0.544344, 0.620921, 0.672375, 0.829926", \ "0.84905, 0.888591, 0.964821, 1.01638, 1.1743"); } fall_transition(delay_template_5x5) { index_1 ("0.03, 0.08, 0.16, 0.4, 0.8"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0696, 0.0678, 0.0804, 0.0828, 0.0984", \ "0.12, 0.1212, 0.126, 0.1314, 0.1446", \ "0.21, 0.2106, 0.213, 0.2148, 0.2238", \ "0.4884, 0.489, 0.4896, 0.4908, 0.4938", \ "0.9642, 0.9642, 0.9636, 0.9642, 0.9666"); } } internal_power() { related_pin : "A"; rise_power(energy_template_5x5) { index_1 ("0.03, 0.08, 0.16, 0.4, 0.8"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.191386, 0.220141, 0.302119, 0.38125, 0.649766", \ "0.192708, 0.228606, 0.296429, 0.366311, 0.617792", \ "0.19518, 0.225555, 0.292713, 0.357425, 0.596341", \ "0.197951, 0.223997, 0.290232, 0.352333, 0.578013", \ "0.199091, 0.223655, 0.290196, 0.351458, 0.570641"); } fall_power(energy_template_5x5) { index_1 ("0.03, 0.08, 0.16, 0.4, 0.8"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.352165, 0.377359, 0.461322, 0.543161, 0.801606", \ "0.357912, 0.382511, 0.45639, 0.527585, 0.773309", \ "0.360119, 0.383461, 0.455593, 0.521738, 0.757801", \ "0.362513, 0.384961, 0.456244, 0.519398, 0.746868", \ "0.363536, 0.385342, 0.457162, 0.519414, 0.742395"); } } internal_power() { related_pin : "B"; rise_power(energy_template_5x5) { index_1 ("0.03, 0.08, 0.16, 0.4, 0.8"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.186549, 0.208247, 0.312831, 0.388838, 0.675493", \ "0.188994, 0.208555, 0.304332, 0.374946, 0.644439", \ "0.192059, 0.222091, 0.295401, 0.365145, 0.624402", \ "0.195221, 0.220386, 0.292889, 0.35993, 0.606836", \ "0.196468, 0.216487, 0.292537, 0.358451, 0.599333"); } fall_power(energy_template_5x5) { index_1 ("0.03, 0.08, 0.16, 0.4, 0.8"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.421093, 0.458642, 0.541568, 0.624263, 0.909001", \ "0.42761, 0.453206, 0.536699, 0.610622, 0.88008", \ "0.427004, 0.453258, 0.533096, 0.604239, 0.8622", \ "0.427683, 0.455049, 0.531753, 0.600298, 0.848374", \ "0.429226, 0.456344, 0.532193, 0.600176, 0.843903"); } } } } /* ---------------- * * Design : AOI21X1 * * ---------------- */ cell (AOI21X1) { area : 128; cell_leakage_power : 0.034284; pin(A) { direction : input; capacitance : 0.0265613; rise_capacitance : 0.0263291; fall_capacitance : 0.0265613; } pin(B) { direction : input; capacitance : 0.0268633; rise_capacitance : 0.0265595; fall_capacitance : 0.0268633; } pin(C) { direction : input; capacitance : 0.02277; rise_capacitance : 0.0227506; fall_capacitance : 0.02277; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.426205; function : "(!((A B)+C))"; timing() { related_pin : "A"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.087618, 0.09475, 0.102291, 0.104779, 0.101472", \ "0.124538, 0.135237, 0.150345, 0.157869, 0.167436", \ "0.184919, 0.194894, 0.215981, 0.228906, 0.254643", \ "0.365214, 0.371165, 0.394076, 0.412908, 0.464888", \ "0.657342, 0.662922, 0.682715, 0.700587, 0.766988"); } fall_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0882, 0.1056, 0.15, 0.1878, 0.3012", \ "0.1386, 0.1512, 0.1932, 0.2274, 0.3516", \ "0.2208, 0.2274, 0.2592, 0.2922, 0.417", \ "0.4722, 0.4722, 0.4854, 0.507, 0.6102", \ "0.8922, 0.8922, 0.894, 0.9024, 0.9648"); } cell_rise(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.099015, 0.116682, 0.147162, 0.170512, 0.238637", \ "0.145385, 0.163565, 0.199902, 0.227241, 0.308469", \ "0.219304, 0.237206, 0.277108, 0.306991, 0.401688", \ "0.440862, 0.45634, 0.492584, 0.525568, 0.634552", \ "0.806783, 0.822064, 0.853273, 0.881643, 0.992471"); } rise_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1002, 0.1188, 0.1644, 0.1968, 0.3078", \ "0.1668, 0.177, 0.2142, 0.2496, 0.3648", \ "0.2772, 0.2802, 0.3072, 0.3372, 0.4476", \ "0.6066, 0.6066, 0.615, 0.6294, 0.7116", \ "1.1574, 1.1574, 1.1574, 1.1622, 1.2024"); } } timing() { related_pin : "B"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.086164, 0.110475, 0.138653, 0.157256, 0.198103", \ "0.124925, 0.151978, 0.192747, 0.215703, 0.271675", \ "0.185335, 0.211863, 0.264991, 0.294572, 0.36979", \ "0.361079, 0.386852, 0.443911, 0.489563, 0.60474", \ "0.65428, 0.67804, 0.732408, 0.775585, 0.927407"); } fall_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0852, 0.1098, 0.1512, 0.186, 0.2964", \ "0.1386, 0.1512, 0.204, 0.2382, 0.3576", \ "0.2196, 0.2262, 0.2718, 0.3108, 0.435", \ "0.4722, 0.4716, 0.489, 0.5184, 0.6456", \ "0.8922, 0.8922, 0.8922, 0.9024, 0.9948"); } cell_rise(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.084371, 0.099785, 0.118599, 0.12948, 0.161497", \ "0.133229, 0.148324, 0.177997, 0.197072, 0.246334", \ "0.20742, 0.223489, 0.257524, 0.282441, 0.352494", \ "0.429408, 0.444366, 0.47828, 0.50845, 0.603133", \ "0.796062, 0.810794, 0.840782, 0.867448, 0.970592"); } rise_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0822, 0.1044, 0.1434, 0.1806, 0.2772", \ "0.1494, 0.1602, 0.2004, 0.231, 0.3408", \ "0.2562, 0.2622, 0.2916, 0.3204, 0.4278", \ "0.5874, 0.5868, 0.5964, 0.6108, 0.6966", \ "1.1376, 1.1376, 1.1382, 1.143, 1.185"); } } timing() { related_pin : "C"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.070954, 0.093903, 0.122041, 0.135649, 0.170849", \ "0.117379, 0.147024, 0.191139, 0.215587, 0.275038", \ "0.187744, 0.217517, 0.278986, 0.312922, 0.399388", \ "0.395389, 0.423626, 0.486829, 0.53804, 0.679382", \ "0.73718, 0.765368, 0.825912, 0.874051, 1.04455"); } fall_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.061848, 0.0843, 0.1278, 0.1572, 0.2454", \ "0.1194, 0.1317, 0.1827, 0.2145, 0.3192", \ "0.2121, 0.2163, 0.258, 0.2967, 0.4131", \ "0.4935, 0.4938, 0.5028, 0.5295, 0.6549", \ "0.9642, 0.9642, 0.9642, 0.9666, 1.0425"); } cell_rise(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.068175, 0.09122, 0.120176, 0.137237, 0.175512", \ "0.109921, 0.139817, 0.185467, 0.210452, 0.272412", \ "0.173343, 0.206154, 0.266447, 0.30177, 0.390562", \ "0.366349, 0.396637, 0.46394, 0.515671, 0.655905", \ "0.687071, 0.716557, 0.780913, 0.831257, 1.00428"); } rise_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0798, 0.1095, 0.1458, 0.1713, 0.2526", \ "0.1374, 0.1575, 0.204, 0.234, 0.3315", \ "0.2337, 0.2406, 0.2838, 0.3207, 0.4296", \ "0.5235, 0.5229, 0.5385, 0.5652, 0.6837", \ "1.0065, 1.0065, 1.0071, 1.0137, 1.0923"); } } internal_power() { related_pin : "A"; fall_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.100823, 0.087045, 0.006401, 0.096521, 0.424421", \ "0.099968, 0.091549, 0.013981, 0.065184, 0.371941", \ "0.098985, 0.094319, 0.032831, 0.032912, 0.309467", \ "0.095757, 0.095376, 0.058906, 0.012867, 0.198853", \ "0.095067, 0.097446, 0.074512, 0.043242, 0.112119"); } rise_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.473605, 0.489085, 0.590811, 0.687265, 1.02644", \ "0.473461, 0.482789, 0.569246, 0.655504, 0.979048", \ "0.476256, 0.480142, 0.549952, 0.623455, 0.92084", \ "0.476311, 0.478982, 0.523227, 0.576287, 0.811951", \ "0.477202, 0.477839, 0.506981, 0.543667, 0.722082"); } } internal_power() { related_pin : "B"; fall_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.099127, 0.08326, 0.000775, 0.076252, 0.36314", \ "0.09789, 0.090238, 0.021153, 0.047055, 0.315384", \ "0.097362, 0.09091, 0.039821, 0.017813, 0.258237", \ "0.096484, 0.09539, 0.063866, 0.024442, 0.158322", \ "0.096575, 0.097464, 0.077924, 0.051987, 0.080718"); } rise_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.404524, 0.417707, 0.513502, 0.596259, 0.893842", \ "0.412701, 0.418437, 0.49412, 0.569094, 0.84951", \ "0.41945, 0.419123, 0.47871, 0.542892, 0.798752", \ "0.422722, 0.42352, 0.46038, 0.506418, 0.709844", \ "0.425263, 0.42573, 0.449881, 0.482142, 0.638213"); } } internal_power() { related_pin : "C"; fall_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.104134, 0.085997, 0.017844, 0.045581, 0.272726", \ "0.093704, 0.087138, 0.034174, 0.019968, 0.229454", \ "0.086315, 0.083197, 0.046386, 0.003507, 0.182764", \ "0.079069, 0.078, 0.057946, 0.029295, 0.109005", \ "0.075771, 0.07461, 0.062624, 0.044435, 0.054769"); } rise_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.266803, 0.29138, 0.365337, 0.428456, 0.649385", \ "0.268757, 0.285375, 0.346817, 0.402783, 0.609673", \ "0.270631, 0.282469, 0.330171, 0.378015, 0.565204", \ "0.272716, 0.278597, 0.308597, 0.342435, 0.48996", \ "0.27328, 0.276798, 0.295991, 0.319156, 0.429769"); } } } } /* ---------------- * * Design : AOI22X1 * * ---------------- */ cell (AOI22X1) { area : 160; cell_leakage_power : 0.0438097; pin(A) { direction : input; capacitance : 0.0265618; rise_capacitance : 0.0263333; fall_capacitance : 0.0265618; } pin(B) { direction : input; capacitance : 0.0268737; rise_capacitance : 0.0265584; fall_capacitance : 0.0268737; } pin(C) { direction : input; capacitance : 0.0270661; rise_capacitance : 0.0270605; fall_capacitance : 0.0270661; } pin(D) { direction : input; capacitance : 0.0273706; rise_capacitance : 0.0273045; fall_capacitance : 0.0273706; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.422357; function : "(!((A B)+(C D)))"; timing() { related_pin : "A"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.106909, 0.115781, 0.128493, 0.135567, 0.14291", \ "0.145212, 0.15487, 0.173234, 0.184021, 0.203556", \ "0.20457, 0.214935, 0.23739, 0.251756, 0.285491", \ "0.38525, 0.391013, 0.414084, 0.433968, 0.489935", \ "0.677791, 0.683212, 0.703022, 0.721231, 0.789888"); } fall_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.105, 0.1218, 0.1659, 0.2067, 0.3198", \ "0.1587, 0.1689, 0.2109, 0.2463, 0.3684", \ "0.2415, 0.2466, 0.2775, 0.3117, 0.4341", \ "0.4935, 0.4935, 0.5058, 0.5247, 0.6282", \ "0.9138, 0.9138, 0.9156, 0.9231, 0.9825"); } cell_rise(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.111371, 0.132737, 0.167078, 0.191499, 0.264069", \ "0.153817, 0.173961, 0.214255, 0.242503, 0.326191", \ "0.218928, 0.238535, 0.283222, 0.314807, 0.412178", \ "0.412229, 0.432587, 0.475431, 0.512087, 0.627626", \ "0.734361, 0.753947, 0.793299, 0.826904, 0.951672"); } rise_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1176, 0.1332, 0.1749, 0.2073, 0.3237", \ "0.177, 0.1848, 0.225, 0.2598, 0.3771", \ "0.273, 0.2763, 0.3063, 0.3372, 0.4494", \ "0.5616, 0.5619, 0.5721, 0.5892, 0.681", \ "1.0449, 1.0446, 1.0455, 1.0515, 1.1019"); } } timing() { related_pin : "B"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.106382, 0.13236, 0.168836, 0.189506, 0.242319", \ "0.144604, 0.171506, 0.218423, 0.244293, 0.310572", \ "0.204796, 0.231558, 0.287379, 0.319961, 0.403296", \ "0.381199, 0.406817, 0.4638, 0.509995, 0.631889", \ "0.674335, 0.698803, 0.752645, 0.795994, 0.949886"); } fall_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1044, 0.1272, 0.174, 0.2109, 0.3246", \ "0.1581, 0.1686, 0.2223, 0.2595, 0.3786", \ "0.2415, 0.2454, 0.2892, 0.3288, 0.4542", \ "0.4935, 0.4932, 0.5079, 0.5367, 0.6654", \ "0.9138, 0.9135, 0.9138, 0.9219, 1.0119"); } cell_rise(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.100585, 0.119085, 0.141737, 0.156101, 0.194213", \ "0.143648, 0.160783, 0.194226, 0.215391, 0.270214", \ "0.20844, 0.225996, 0.267184, 0.293557, 0.367534", \ "0.402576, 0.421839, 0.462618, 0.497283, 0.5994", \ "0.724914, 0.744277, 0.7823, 0.814622, 0.93226"); } rise_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1005, 0.1185, 0.1584, 0.1974, 0.3", \ "0.1608, 0.171, 0.2127, 0.2442, 0.3531", \ "0.2556, 0.2598, 0.2907, 0.3225, 0.4323", \ "0.5445, 0.5445, 0.5553, 0.5727, 0.6675", \ "1.0272, 1.0278, 1.0284, 1.0344, 1.0872"); } } timing() { related_pin : "C"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.068551, 0.074864, 0.071423, 0.064457, 0.031897", \ "0.1087, 0.117473, 0.12521, 0.125516, 0.111597", \ "0.169619, 0.179278, 0.195645, 0.202872, 0.210214", \ "0.349303, 0.35577, 0.378008, 0.394453, 0.434701", \ "0.642286, 0.648544, 0.667744, 0.685318, 0.744546"); } fall_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.068278, 0.0909, 0.1335, 0.1653, 0.2556", \ "0.1197, 0.1344, 0.1743, 0.2055, 0.3126", \ "0.2013, 0.2091, 0.2418, 0.273, 0.3858", \ "0.4536, 0.4539, 0.4674, 0.4878, 0.5868", \ "0.873, 0.873, 0.8754, 0.8838, 0.9456"); } cell_rise(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.090762, 0.124192, 0.176377, 0.211966, 0.318488", \ "0.130527, 0.165816, 0.228193, 0.269286, 0.390606", \ "0.195948, 0.229228, 0.300907, 0.34764, 0.485438", \ "0.388654, 0.419843, 0.490637, 0.547081, 0.717716", \ "0.709605, 0.73957, 0.805851, 0.858985, 1.04713"); } rise_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1044, 0.1254, 0.1656, 0.1926, 0.2793", \ "0.1638, 0.1737, 0.2199, 0.2493, 0.3465", \ "0.2589, 0.2634, 0.3, 0.3318, 0.4353", \ "0.5484, 0.5487, 0.5598, 0.5823, 0.6867", \ "1.0323, 1.0317, 1.032, 1.0377, 1.104"); } } timing() { related_pin : "D"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.068235, 0.086318, 0.10175, 0.106816, 0.111444", \ "0.108152, 0.133515, 0.164053, 0.177637, 0.204588", \ "0.168204, 0.195279, 0.242155, 0.265441, 0.31821", \ "0.344946, 0.371698, 0.4277, 0.47127, 0.572169", \ "0.639948, 0.6641, 0.717219, 0.759988, 0.905949"); } fall_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.068248, 0.0942, 0.1359, 0.1644, 0.2556", \ "0.1194, 0.1338, 0.1851, 0.2166, 0.3234", \ "0.2031, 0.207, 0.255, 0.291, 0.4071", \ "0.4533, 0.4539, 0.4713, 0.5022, 0.6276", \ "0.873, 0.873, 0.8736, 0.8832, 0.9774"); } cell_rise(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.078061, 0.105426, 0.147103, 0.172747, 0.243204", \ "0.119963, 0.152406, 0.205875, 0.239787, 0.330752", \ "0.184706, 0.217548, 0.283524, 0.324879, 0.439751", \ "0.378973, 0.409134, 0.478102, 0.53253, 0.690209", \ "0.700613, 0.729821, 0.79489, 0.846754, 1.0292"); } rise_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0852, 0.1098, 0.1482, 0.1713, 0.2526", \ "0.1461, 0.1593, 0.2055, 0.2322, 0.3276", \ "0.2418, 0.2457, 0.2862, 0.3195, 0.4221", \ "0.5313, 0.5316, 0.5436, 0.5664, 0.6762", \ "1.0146, 1.0146, 1.0149, 1.0203, 1.0905"); } } internal_power() { related_pin : "A"; fall_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.08862, 0.077942, 0.009309, 0.094769, 0.416256", \ "0.087155, 0.081498, 0.00904, 0.069347, 0.371149", \ "0.086437, 0.081108, 0.023659, 0.041628, 0.315723", \ "0.083247, 0.082654, 0.046296, 0.01383, 0.213842", \ "0.082383, 0.084215, 0.060908, 0.028818, 0.130631"); } rise_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.574879, 0.58766, 0.686407, 0.777311, 1.11607", \ "0.573858, 0.582092, 0.665057, 0.748138, 1.07063", \ "0.575903, 0.580414, 0.647797, 0.718789, 1.01427", \ "0.578132, 0.580154, 0.623373, 0.67411, 0.908349", \ "0.579062, 0.579264, 0.608528, 0.64349, 0.820706"); } } internal_power() { related_pin : "B"; fall_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.086888, 0.077144, 0.006265, 0.075576, 0.355605", \ "0.085484, 0.08022, 0.014359, 0.05201, 0.314743", \ "0.084649, 0.079307, 0.029782, 0.02673, 0.264414", \ "0.083459, 0.082606, 0.051245, 0.013287, 0.172953", \ "0.083621, 0.084198, 0.064426, 0.037771, 0.098546"); } rise_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.504789, 0.5202, 0.607008, 0.687078, 0.982391", \ "0.511868, 0.517758, 0.590948, 0.662743, 0.940649", \ "0.518589, 0.519778, 0.577438, 0.638741, 0.892104", \ "0.525042, 0.524655, 0.560862, 0.604726, 0.806265", \ "0.527668, 0.52723, 0.551626, 0.582048, 0.736708"); } } internal_power() { related_pin : "C"; fall_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.103246, 0.080197, 0.009441, 0.092711, 0.391211", \ "0.093989, 0.082217, 0.008749, 0.064219, 0.342882", \ "0.087005, 0.079435, 0.024106, 0.037093, 0.287374", \ "0.079894, 0.074891, 0.04103, 0.002314, 0.193829", \ "0.076237, 0.072442, 0.05063, 0.021537, 0.122637"); } rise_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.382637, 0.412968, 0.505327, 0.586004, 0.877529", \ "0.383556, 0.403556, 0.484526, 0.557975, 0.833523", \ "0.385631, 0.399852, 0.464029, 0.528555, 0.781062", \ "0.387493, 0.39469, 0.436012, 0.48254, 0.685772", \ "0.388573, 0.392556, 0.418669, 0.450603, 0.604142"); } } internal_power() { related_pin : "D"; fall_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.100747, 0.081524, 0.004462, 0.076373, 0.344227", \ "0.092456, 0.080816, 0.016033, 0.049265, 0.297734", \ "0.085654, 0.078117, 0.03005, 0.023541, 0.245356", \ "0.078806, 0.074639, 0.046256, 0.009926, 0.159509", \ "0.07486, 0.072485, 0.054778, 0.030343, 0.094374"); } rise_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.31926, 0.344088, 0.429797, 0.502557, 0.760593", \ "0.324361, 0.340262, 0.411143, 0.477624, 0.721729", \ "0.329665, 0.339745, 0.395094, 0.452168, 0.676577", \ "0.335571, 0.33954, 0.373924, 0.414908, 0.595218", \ "0.338322, 0.340362, 0.362063, 0.390105, 0.527079"); } } } } /* -------------- * * Design : BUFX2 * * -------------- */ cell (BUFX2) { cell_footprint : buf; area : 96; cell_leakage_power : 0.0381689; pin(A) { direction : input; capacitance : 0.0134147; rise_capacitance : 0.0133626; fall_capacitance : 0.0134147; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.831224; function : "A"; timing() { related_pin : "A"; timing_sense : positive_unate; cell_rise(delay_template_5x5) { index_1 ("0.03, 0.08, 0.16, 0.4, 0.8"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.133137, 0.154559, 0.190018, 0.203029, 0.231747", \ "0.18185, 0.207778, 0.240227, 0.257765, 0.289299", \ "0.259107, 0.284588, 0.318472, 0.334377, 0.36909", \ "0.489567, 0.516198, 0.547039, 0.562723, 0.597803", \ "0.872314, 0.898781, 0.929312, 0.944672, 0.979724"); } rise_transition(delay_template_5x5) { index_1 ("0.03, 0.08, 0.16, 0.4, 0.8"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0726, 0.0732, 0.0852, 0.0954, 0.1068", \ "0.1374, 0.138, 0.144, 0.15, 0.1626", \ "0.2478, 0.2478, 0.2514, 0.2532, 0.264", \ "0.5928, 0.5928, 0.5928, 0.594, 0.5982", \ "1.17, 1.17, 1.1706, 1.1706, 1.1724"); } cell_fall(delay_template_5x5) { index_1 ("0.03, 0.08, 0.16, 0.4, 0.8"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.145384, 0.178566, 0.231467, 0.270548, 0.365483", \ "0.193553, 0.229676, 0.287701, 0.323216, 0.421557", \ "0.265945, 0.302361, 0.359906, 0.395447, 0.49735", \ "0.473948, 0.509259, 0.567157, 0.60388, 0.706799", \ "0.818489, 0.853514, 0.911751, 0.947501, 1.05108"); } fall_transition(delay_template_5x5) { index_1 ("0.03, 0.08, 0.16, 0.4, 0.8"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0696, 0.0702, 0.0756, 0.084, 0.0942", \ "0.1188, 0.123, 0.126, 0.1308, 0.1452", \ "0.2076, 0.2076, 0.2124, 0.2136, 0.228", \ "0.489, 0.4884, 0.4896, 0.4914, 0.4974", \ "0.9642, 0.9636, 0.9636, 0.9648, 0.9672"); } } internal_power() { related_pin : "A"; rise_power(energy_template_5x5) { index_1 ("0.03, 0.08, 0.16, 0.4, 0.8"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.202271, 0.224707, 0.298267, 0.362152, 0.597273", \ "0.200651, 0.219543, 0.287291, 0.347882, 0.564936", \ "0.200676, 0.217103, 0.282401, 0.336491, 0.545011", \ "0.19765, 0.216643, 0.278566, 0.329387, 0.525948", \ "0.198941, 0.217398, 0.277368, 0.327414, 0.517438"); } fall_power(energy_template_5x5) { index_1 ("0.03, 0.08, 0.16, 0.4, 0.8"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.311936, 0.339705, 0.42546, 0.48532, 0.72018", \ "0.319514, 0.339947, 0.412677, 0.471692, 0.688796", \ "0.322872, 0.345658, 0.409983, 0.464941, 0.67147", \ "0.326115, 0.346682, 0.409135, 0.462979, 0.658831", \ "0.327123, 0.347526, 0.410173, 0.4626, 0.654153"); } } } } /* -------------- * * Design : BUFX4 * * -------------- */ cell (BUFX4) { cell_footprint : buf; area : 128; cell_leakage_power : 0.0543119; pin(A) { direction : input; capacitance : 0.0204034; rise_capacitance : 0.0203782; fall_capacitance : 0.0204034; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 1.66099; function : "A"; timing() { related_pin : "A"; timing_sense : positive_unate; cell_rise(delay_template_5x5) { index_1 ("0.06, 0.16, 0.32, 0.8, 1.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.150497, 0.17864, 0.215212, 0.235777, 0.278738", \ "0.203356, 0.232307, 0.271157, 0.292104, 0.337126", \ "0.281752, 0.309697, 0.34909, 0.370388, 0.417398", \ "0.512861, 0.539664, 0.578386, 0.598535, 0.645108", \ "0.895447, 0.92211, 0.9604, 0.980318, 1.02619"); } rise_transition(delay_template_5x5) { index_1 ("0.06, 0.16, 0.32, 0.8, 1.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0834, 0.0834, 0.0918, 0.0984, 0.1116", \ "0.1428, 0.1446, 0.1494, 0.1554, 0.1668", \ "0.2508, 0.2514, 0.255, 0.2562, 0.2676", \ "0.594, 0.594, 0.5946, 0.5952, 0.5994", \ "1.1712, 1.1712, 1.1712, 1.1712, 1.173"); } cell_fall(delay_template_5x5) { index_1 ("0.06, 0.16, 0.32, 0.8, 1.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.162386, 0.200466, 0.262237, 0.29644, 0.398076", \ "0.216856, 0.253596, 0.315342, 0.352882, 0.458057", \ "0.290174, 0.326517, 0.38822, 0.427141, 0.534734", \ "0.498213, 0.533642, 0.596155, 0.634742, 0.742901", \ "0.842732, 0.877791, 0.940266, 0.978316, 1.08687"); } fall_transition(delay_template_5x5) { index_1 ("0.06, 0.16, 0.32, 0.8, 1.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0744, 0.072, 0.0822, 0.0852, 0.1032", \ "0.1254, 0.1266, 0.1308, 0.1386, 0.1536", \ "0.21, 0.2124, 0.2148, 0.2196, 0.2304", \ "0.4908, 0.4902, 0.4914, 0.4926, 0.498", \ "0.9654, 0.9654, 0.9654, 0.966, 0.969"); } } internal_power() { related_pin : "A"; rise_power(energy_template_5x5) { index_1 ("0.06, 0.16, 0.32, 0.8, 1.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.419664, 0.460709, 0.591849, 0.700961, 1.09146", \ "0.422118, 0.448441, 0.566528, 0.660692, 1.01434", \ "0.4253, 0.446926, 0.544091, 0.639169, 0.965864", \ "0.430336, 0.451156, 0.534922, 0.619211, 0.917899", \ "0.431139, 0.45054, 0.533304, 0.611753, 0.896223"); } fall_power(energy_template_5x5) { index_1 ("0.06, 0.16, 0.32, 0.8, 1.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.586039, 0.630263, 0.746719, 0.856922, 1.24606", \ "0.58888, 0.627326, 0.726733, 0.824342, 1.17152", \ "0.585971, 0.62438, 0.718648, 0.80387, 1.12725", \ "0.592444, 0.624051, 0.712925, 0.79305, 1.09202", \ "0.595263, 0.624501, 0.713627, 0.790707, 1.07935"); } } } } /* ---------------- * * Design : CLKBUF1 * * ---------------- */ cell (CLKBUF1) { cell_footprint : buf; area : 288; cell_leakage_power : 0.165423; pin(A) { direction : input; capacitance : 0.0549205; rise_capacitance : 0.0548901; fall_capacitance : 0.0549205; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 1.66707; function : "A"; timing() { related_pin : "A"; timing_sense : positive_unate; cell_rise(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.224332, 0.243111, 0.264592, 0.276805, 0.286372, 0.290021", \ "0.417271, 0.440455, 0.455374, 0.474513, 0.478431, 0.482835", \ "0.751644, 0.775047, 0.79633, 0.809058, 0.818679, 0.823959", \ "1.61299, 1.63627, 1.65805, 1.67039, 1.67992, 1.68522", \ "2.09146, 2.11495, 2.13666, 2.14892, 2.15859, 2.16383", \ "2.57016, 2.5936, 2.61494, 2.62757, 2.63722, 2.64244"); } rise_transition(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.096, 0.0942, 0.0912, 0.09, 0.0912, 0.0948", \ "0.375, 0.3744, 0.375, 0.3744, 0.375, 0.375", \ "0.8802, 0.8802, 0.8802, 0.8802, 0.8802, 0.8802", \ "2.1804, 2.1798, 2.1804, 2.1804, 2.1804, 2.1798", \ "2.9028, 2.9028, 2.9016, 2.9028, 2.9028, 2.9022", \ "3.6258, 3.6258, 3.624, 3.6252, 3.6258, 3.6246"); } cell_fall(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.232224, 0.267876, 0.30847, 0.363348, 0.400538, 0.463001", \ "0.406571, 0.441926, 0.485759, 0.540694, 0.578987, 0.636862", \ "0.707684, 0.743121, 0.785839, 0.841971, 0.880349, 0.941556", \ "1.48242, 1.51791, 1.56053, 1.61659, 1.65509, 1.71625", \ "1.91225, 1.94772, 1.99073, 2.04644, 2.0852, 2.1464", \ "2.34265, 2.37815, 2.42065, 2.47674, 2.51574, 2.5763"); } fall_transition(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.0798, 0.0792, 0.0804, 0.0804, 0.0804, 0.0804", \ "0.3084, 0.3084, 0.3078, 0.309, 0.3084, 0.3078", \ "0.7242, 0.7242, 0.7236, 0.7236, 0.7242, 0.7242", \ "1.7964, 1.7964, 1.7958, 1.7964, 1.7964, 1.7958", \ "2.391, 2.391, 2.3916, 2.391, 2.3916, 2.3916", \ "2.9868, 2.9868, 2.988, 2.9862, 2.988, 2.9874"); } } internal_power() { related_pin : "A"; rise_power(energy_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "1.11593, 1.27601, 1.63949, 2.21709, 2.66388, 3.51996", \ "1.17146, 1.29221, 1.64495, 2.21995, 2.66684, 3.52434", \ "1.17342, 1.29647, 1.64745, 2.22163, 2.66176, 3.51406", \ "1.17423, 1.29854, 1.63412, 2.2232, 2.66429, 3.51668", \ "1.17513, 1.2987, 1.63467, 2.22403, 2.66479, 3.51694", \ "1.17481, 1.2992, 1.63521, 2.22395, 2.66526, 3.51751"); } fall_power(energy_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "1.79422, 1.91322, 2.24419, 2.82487, 3.28384, 4.18362", \ "1.8097, 1.93625, 2.2816, 2.86427, 3.30394, 4.18368", \ "1.81377, 1.93928, 2.2801, 2.86625, 3.30861, 4.17442", \ "1.81636, 1.94165, 2.28099, 2.86685, 3.31017, 4.17568", \ "1.81642, 1.94184, 2.28129, 2.86718, 3.31079, 4.17561", \ "1.81749, 1.94222, 2.2816, 2.86748, 3.31121, 4.17631"); } } } } /* ---------------- * * Design : CLKBUF2 * * ---------------- */ cell (CLKBUF2) { cell_footprint : buf; area : 416; cell_leakage_power : 0.257476; pin(A) { direction : input; capacitance : 0.0549339; rise_capacitance : 0.0549339; fall_capacitance : 0.0549141; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 1.66571; function : "A"; timing() { related_pin : "A"; timing_sense : positive_unate; cell_rise(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.321199, 0.343529, 0.363213, 0.376051, 0.385003, 0.391058", \ "0.518808, 0.536599, 0.554454, 0.573676, 0.577216, 0.581919", \ "0.853279, 0.873575, 0.895214, 0.908146, 0.917184, 0.922869", \ "1.71446, 1.73599, 1.75621, 1.76933, 1.77838, 1.7841", \ "2.19313, 2.21467, 2.23518, 2.24801, 2.25704, 2.26281", \ "2.67178, 2.69332, 2.71364, 2.72665, 2.73567, 2.74132"); } rise_transition(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.09, 0.093, 0.09, 0.09, 0.093, 0.0936", \ "0.375, 0.3744, 0.3756, 0.375, 0.3744, 0.375", \ "0.8802, 0.8796, 0.8796, 0.8802, 0.8802, 0.8802", \ "2.1798, 2.1798, 2.1798, 2.1798, 2.1798, 2.1798", \ "2.9028, 2.9028, 2.9016, 2.9028, 2.9028, 2.9022", \ "3.6252, 3.6252, 3.6252, 3.6252, 3.6258, 3.6246"); } cell_fall(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.331235, 0.369022, 0.406196, 0.462716, 0.498865, 0.56249", \ "0.505866, 0.541977, 0.586624, 0.64, 0.677712, 0.736427", \ "0.810551, 0.842957, 0.887983, 0.940963, 0.97894, 1.03761", \ "1.58542, 1.61764, 1.66286, 1.71555, 1.75337, 1.81231", \ "2.01526, 2.0474, 2.09262, 2.1454, 2.18367, 2.24238", \ "2.44561, 2.4778, 2.52305, 2.57567, 2.61361, 2.6724"); } fall_transition(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.0798, 0.0804, 0.0762, 0.0798, 0.0798, 0.0792", \ "0.3078, 0.309, 0.309, 0.3084, 0.3084, 0.309", \ "0.7242, 0.7242, 0.7242, 0.7236, 0.7242, 0.7236", \ "1.7958, 1.7964, 1.7964, 1.7964, 1.7964, 1.7964", \ "2.3916, 2.391, 2.391, 2.391, 2.3916, 2.3916", \ "2.9874, 2.9868, 2.9868, 2.9862, 2.988, 2.9862"); } } internal_power() { related_pin : "A"; rise_power(energy_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "2.01187, 2.17062, 2.53108, 3.0698, 3.56216, 4.406", \ "2.01007, 2.17916, 2.53623, 3.06713, 3.5648, 4.4108", \ "2.0137, 2.14572, 2.53166, 3.07087, 3.55276, 4.39416", \ "2.01546, 2.17835, 2.53421, 3.07243, 3.55459, 4.39658", \ "2.01565, 2.17912, 2.53484, 3.07268, 3.55546, 4.39685", \ "2.01643, 2.17838, 2.5351, 3.07308, 3.55579, 4.39802"); } fall_power(energy_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "2.70066, 2.81519, 3.10037, 3.68829, 4.15259, 5.08299", \ "2.71164, 2.82137, 3.12019, 3.71744, 4.16655, 5.0839", \ "2.68872, 2.82243, 3.12471, 3.71938, 4.16762, 5.09126", \ "2.69201, 2.82328, 3.12693, 3.71956, 4.16839, 5.09384", \ "2.69213, 2.82321, 3.12775, 3.71982, 4.16844, 5.0937", \ "2.69309, 2.82409, 3.12743, 3.71942, 4.16919, 5.09352"); } } } } /* ---------------- * * Design : CLKBUF3 * * ---------------- */ cell (CLKBUF3) { cell_footprint : buf; area : 544; cell_leakage_power : 0.349527; pin(A) { direction : input; capacitance : 0.0549337; rise_capacitance : 0.0549337; fall_capacitance : 0.0549228; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 1.66565; function : "A"; timing() { related_pin : "A"; timing_sense : positive_unate; cell_rise(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.420438, 0.443171, 0.462181, 0.475299, 0.483621, 0.490154", \ "0.618136, 0.635526, 0.655634, 0.673013, 0.676178, 0.681177", \ "0.952623, 0.969882, 0.990146, 1.0075, 1.01599, 1.02169", \ "1.81382, 1.83374, 1.85134, 1.8687, 1.87717, 1.88291", \ "2.29249, 2.31248, 2.32995, 2.34738, 2.3558, 2.36161", \ "2.77115, 2.79077, 2.80858, 2.82602, 2.83438, 2.83988"); } rise_transition(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.0906, 0.0942, 0.0936, 0.0906, 0.0924, 0.0936", \ "0.375, 0.3744, 0.3744, 0.375, 0.3744, 0.375", \ "0.8802, 0.8802, 0.8802, 0.8802, 0.8802, 0.8796", \ "2.1798, 2.1804, 2.1804, 2.1798, 2.1804, 2.1804", \ "2.9028, 2.9022, 2.9028, 2.9028, 2.9028, 2.9022", \ "3.6252, 3.6258, 3.6258, 3.6252, 3.6246, 3.6258"); } cell_fall(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.431168, 0.464082, 0.505975, 0.56074, 0.600775, 0.661525", \ "0.605199, 0.642286, 0.683384, 0.736658, 0.772834, 0.835433", \ "0.906277, 0.943592, 0.984739, 1.03799, 1.07401, 1.13661", \ "1.68098, 1.71847, 1.75965, 1.8126, 1.84874, 1.91132", \ "2.11095, 2.14863, 2.19, 2.24248, 2.27868, 2.3412", \ "2.54127, 2.57896, 2.61993, 2.67301, 2.70901, 2.77138"); } fall_transition(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.0798, 0.0798, 0.0798, 0.0828, 0.0798, 0.0792", \ "0.3084, 0.3084, 0.309, 0.3078, 0.309, 0.309", \ "0.7242, 0.7236, 0.7236, 0.7236, 0.7242, 0.7242", \ "1.7964, 1.7958, 1.7964, 1.7964, 1.7964, 1.7964", \ "2.391, 2.3916, 2.3916, 2.3916, 2.391, 2.3916", \ "2.9874, 2.988, 2.988, 2.9862, 2.9874, 2.9862"); } } internal_power() { related_pin : "A"; rise_power(energy_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "2.8632, 3.00127, 3.40811, 3.92053, 4.46223, 5.29368", \ "2.85991, 3.04573, 3.41615, 3.91754, 4.46447, 5.29839", \ "2.86386, 3.04668, 3.41771, 3.92175, 4.4477, 5.2994", \ "2.86579, 3.00475, 3.41845, 3.92406, 4.45015, 5.30123", \ "2.86674, 3.0051, 3.41906, 3.92505, 4.45045, 5.30213", \ "2.86755, 3.00559, 3.41874, 3.92502, 4.45071, 5.30228"); } fall_power(energy_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "3.59541, 3.65815, 3.95854, 4.52621, 5.03298, 5.98166", \ "3.60073, 3.66618, 3.97078, 4.57387, 5.05721, 5.98513", \ "3.60534, 3.67055, 3.97511, 4.57645, 5.06066, 5.99037", \ "3.60829, 3.6729, 3.97688, 4.57773, 5.06339, 5.99294", \ "3.60853, 3.67397, 3.97745, 4.57773, 5.06401, 5.99383", \ "3.60942, 3.67415, 3.97778, 4.57938, 5.06429, 5.99409"); } } } } /* ----------------- * * Design : DFFNEGX1 * * ----------------- */ cell (DFFNEGX1) { area : 384; cell_leakage_power : 0.113357; ff (DS0000,P0002) { next_state : "D"; clocked_on : "(!CLK)"; } pin(CLK) { direction : input; capacitance : 0.04321; rise_capacitance : 0.0427558; fall_capacitance : 0.04321; clock : true; internal_power() { rise_power(passive_energy_template_6x1) { index_1 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ("0.163587, 0.216373, 0.297888, 0.575101, 0.776867, 1.21926"); } fall_power(passive_energy_template_6x1) { index_1 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ("0.436919, 0.547759, 0.694889, 0.961071, 1.16, 1.57122"); } } min_pulse_width_high : 0.140686; min_pulse_width_low : 0.163576; } pin(D) { direction : input; capacitance : 0.013091; rise_capacitance : 0.0129706; fall_capacitance : 0.013091; internal_power() { rise_power(passive_energy_template_5x1) { index_1 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ("0.16207, 0.177108, 0.229913, 0.283368, 0.463246"); } fall_power(passive_energy_template_5x1) { index_1 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ("0.518077, 0.535304, 0.586976, 0.642473, 0.828541"); } } timing() { related_pin : "CLK"; timing_type : hold_falling; rise_constraint(hold_template_3x5) { index_1 ("0.06, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "-0.09375, -0.0875, -0.075, -0.1125, -0.175", \ "-0.2, -0.19375, -0.18125, -0.21875, -0.1875", \ "-0.16875, -0.25625, -0.24375, -0.28125, -0.25"); } fall_constraint(hold_template_3x5) { index_1 ("0.06, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "-0.09375, -0.0875, -0.16875, -0.20625, -0.26875", \ "-0.0125, -0.1, -0.0875, -0.125, -0.1875", \ "-0.075, -0.06875, -0.05625, -0.09375, -0.15625"); } } timing() { related_pin : "CLK"; timing_type : setup_falling; rise_constraint(setup_template_3x5) { index_1 ("0.06, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.28125, 0.275, 0.2625, 0.3, 0.3625", \ "0.29375, 0.2875, 0.36875, 0.3125, 0.375", \ "0.35625, 0.35, 0.3375, 0.375, 0.4375"); } fall_constraint(setup_template_3x5) { index_1 ("0.06, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.28125, 0.275, 0.35625, 0.39375, 0.45625", \ "0.29375, 0.2875, 0.36875, 0.40625, 0.46875", \ "0.2625, 0.35, 0.3375, 0.375, 0.4375"); } } } pin(Q) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.808965; function : "DS0000"; timing() { related_pin : "CLK"; timing_sense : non_unate; timing_type : falling_edge; cell_rise(delay_template_5x6) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.202117, 0.235682, 0.278481, 0.330026, 0.363478, 0.413314", \ "0.233234, 0.267436, 0.309217, 0.361196, 0.393216, 0.445908", \ "0.278169, 0.312131, 0.354152, 0.406801, 0.438335, 0.490417", \ "0.400645, 0.43358, 0.474955, 0.527766, 0.559505, 0.613427", \ "0.593235, 0.626181, 0.667405, 0.719368, 0.753264, 0.806306"); } rise_transition(delay_template_5x6) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.081, 0.0786, 0.0738, 0.0774, 0.0786, 0.0828", \ "0.1134, 0.1098, 0.111, 0.1086, 0.1098, 0.1122", \ "0.1662, 0.165, 0.1626, 0.1632, 0.1626, 0.1662", \ "0.3282, 0.3276, 0.3264, 0.327, 0.3282, 0.3294", \ "0.6108, 0.6108, 0.6108, 0.6102, 0.6102, 0.6114"); } cell_fall(delay_template_5x6) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.198542, 0.249691, 0.309001, 0.404914, 0.463968, 0.569663", \ "0.233985, 0.283559, 0.344772, 0.439081, 0.501044, 0.609074", \ "0.282365, 0.330228, 0.393398, 0.487308, 0.547648, 0.657172", \ "0.399168, 0.447622, 0.511789, 0.606075, 0.668496, 0.781668", \ "0.575754, 0.62385, 0.687193, 0.784757, 0.846136, 0.961283"); } fall_transition(delay_template_5x6) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.0756, 0.0786, 0.0858, 0.1056, 0.117, 0.1254", \ "0.1098, 0.108, 0.1158, 0.1308, 0.1398, 0.1554", \ "0.156, 0.1512, 0.162, 0.171, 0.1776, 0.1926", \ "0.2832, 0.285, 0.2892, 0.2964, 0.3036, 0.318", \ "0.51, 0.51, 0.5124, 0.5196, 0.5232, 0.5328"); } } internal_power() { related_pin : "CLK"; rise_power(energy_template_5x6) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.764154, 0.854058, 1.03011, 1.31441, 1.52037, 1.92556", \ "0.742505, 0.84881, 1.01612, 1.3007, 1.50941, 1.91203", \ "0.737126, 0.840224, 0.999697, 1.28675, 1.49052, 1.90406", \ "0.729767, 0.835803, 0.994157, 1.28113, 1.48556, 1.89454", \ "0.72581, 0.831138, 0.99214, 1.27818, 1.4812, 1.89133"); } fall_power(energy_template_5x6) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.757465, 0.897208, 1.11154, 1.52514, 1.82082, 2.39776", \ "0.743543, 0.87883, 1.08134, 1.48923, 1.78168, 2.35525", \ "0.734104, 0.865228, 1.06518, 1.45852, 1.74795, 2.31759", \ "0.730865, 0.857216, 1.05072, 1.42877, 1.70803, 2.27226", \ "0.727549, 0.853525, 1.04292, 1.41506, 1.68628, 2.23822"); } } } } /* ----------------- * * Design : DFFPOSX1 * * ----------------- */ cell (DFFPOSX1) { area : 384; cell_leakage_power : 0.112978; ff (DS0000,P0002) { next_state : "D"; clocked_on : "CLK"; } pin(CLK) { direction : input; capacitance : 0.0405158; rise_capacitance : 0.0403976; fall_capacitance : 0.0405158; clock : true; internal_power() { rise_power(passive_energy_template_6x1) { index_1 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ("0.064753, 0.023177, 0.164137, 0.430755, 0.628444, 1.02121"); } fall_power(passive_energy_template_6x1) { index_1 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ("0.552255, 0.681659, 0.849137, 1.17901, 1.40943, 1.87724"); } } min_pulse_width_high : 0.166496; min_pulse_width_low : 0.151234; } pin(D) { direction : input; capacitance : 0.0130794; rise_capacitance : 0.0130318; fall_capacitance : 0.0130794; internal_power() { rise_power(passive_energy_template_5x1) { index_1 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ("0.21215, 0.222443, 0.274423, 0.326727, 0.505608"); } fall_power(passive_energy_template_5x1) { index_1 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ("0.473607, 0.489211, 0.536851, 0.588019, 0.781043"); } } timing() { related_pin : "CLK"; timing_type : hold_rising; rise_constraint(hold_template_3x5) { index_1 ("0.06, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "-0.09375, -0.0875, -0.075, -0.1125, -0.08125", \ "-0.0125, -0.00625, -0.0875, -0.03125, -0.09375", \ "-0.075, -0.06875, -0.05625, -0.09375, -0.0625"); } fall_constraint(hold_template_3x5) { index_1 ("0.06, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "-0.09375, -0.0875, -0.16875, -0.20625, -0.26875", \ "-0.2, -0.19375, -0.275, -0.3125, -0.375", \ "-0.2625, -0.25625, -0.3375, -0.375, -0.4375"); } } timing() { related_pin : "CLK"; timing_type : setup_rising; rise_constraint(setup_template_3x5) { index_1 ("0.06, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.28125, 0.275, 0.35625, 0.3, 0.3625", \ "0.29375, 0.38125, 0.36875, 0.40625, 0.375", \ "0.45, 0.44375, 0.525, 0.46875, 0.53125"); } fall_constraint(setup_template_3x5) { index_1 ("0.06, 0.3, 0.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.28125, 0.275, 0.35625, 0.3, 0.45625", \ "0.29375, 0.2875, 0.36875, 0.40625, 0.46875", \ "0.45, 0.44375, 0.43125, 0.65625, 0.71875"); } } } pin(Q) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.809569; function : "DS0000"; timing() { related_pin : "CLK"; timing_sense : non_unate; timing_type : rising_edge; cell_rise(delay_template_5x6) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.155157, 0.185043, 0.200943, 0.199225, 0.183875, 0.136501", \ "0.187733, 0.216666, 0.232876, 0.232403, 0.218026, 0.173249", \ "0.233455, 0.261446, 0.278507, 0.277236, 0.264079, 0.220551", \ "0.35604, 0.383739, 0.400674, 0.400086, 0.387318, 0.34478", \ "0.548234, 0.575647, 0.594155, 0.592191, 0.579607, 0.53882"); } rise_transition(delay_template_5x6) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.0756, 0.0798, 0.0918, 0.108, 0.108, 0.1212", \ "0.1086, 0.1164, 0.1218, 0.1302, 0.1404, 0.1584", \ "0.1638, 0.168, 0.1728, 0.1824, 0.1896, 0.2046", \ "0.3276, 0.3282, 0.3324, 0.339, 0.3456, 0.3564", \ "0.6102, 0.6108, 0.6126, 0.6162, 0.6204, 0.63"); } cell_fall(delay_template_5x6) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.252448, 0.268754, 0.287605, 0.305023, 0.310473, 0.312851", \ "0.287515, 0.303626, 0.320722, 0.338982, 0.34431, 0.346762", \ "0.335443, 0.351085, 0.367249, 0.385665, 0.392484, 0.394748", \ "0.452852, 0.468111, 0.484539, 0.502748, 0.509707, 0.511646", \ "0.629629, 0.644574, 0.661197, 0.678628, 0.686318, 0.689721"); } fall_transition(delay_template_5x6) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.0864, 0.075, 0.075, 0.0756, 0.078, 0.078", \ "0.1098, 0.1104, 0.105, 0.105, 0.1044, 0.1062", \ "0.1536, 0.153, 0.1506, 0.153, 0.156, 0.1566", \ "0.2838, 0.2844, 0.2826, 0.2838, 0.2844, 0.285", \ "0.5106, 0.5106, 0.51, 0.5094, 0.5106, 0.5124"); } } internal_power() { related_pin : "CLK"; rise_power(energy_template_5x6) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.218029, 0.333901, 0.540957, 0.908081, 1.17532, 1.69014", \ "0.209825, 0.322234, 0.512691, 0.877257, 1.13397, 1.64705", \ "0.204201, 0.312703, 0.493395, 0.85371, 1.10896, 1.61315", \ "0.201393, 0.302564, 0.479152, 0.820183, 1.07552, 1.57677", \ "0.197652, 0.297942, 0.467065, 0.800769, 1.04916, 1.55238"); } fall_power(energy_template_5x6) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.316675, 0.400097, 0.535739, 0.809463, 1.01265, 1.41974", \ "0.302645, 0.37725, 0.521619, 0.793054, 0.996677, 1.4034", \ "0.290029, 0.369578, 0.514175, 0.783816, 0.984621, 1.38972", \ "0.28417, 0.363618, 0.505936, 0.777901, 0.978745, 1.38439", \ "0.281585, 0.360364, 0.502708, 0.775338, 0.976405, 1.37888"); } } } } /* -------------- * * Design : DFFSR * * -------------- */ cell (DFFSR) { area : 704; cell_leakage_power : 0.247939; ff (P0002,P0003) { next_state : "D"; clocked_on : "CLK"; clear : "(!R)"; preset : "(!S)"; clear_preset_var1 : L; } pin(CLK) { direction : input; capacitance : 0.0134469; rise_capacitance : 0.0133798; fall_capacitance : 0.0134469; clock : true; internal_power() { rise_power(passive_energy_template_6x1) { index_1 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ("0.190997, 0.223621, 0.300287, 0.442835, 0.552417, 0.765449"); } fall_power(passive_energy_template_6x1) { index_1 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ("0.580077, 0.612991, 0.694086, 0.84286, 0.948037, 1.16752"); } } min_pulse_width_high : 0.393155; min_pulse_width_low : 0.288592; } pin(D) { direction : input; capacitance : 0.0135592; rise_capacitance : 0.0134699; fall_capacitance : 0.0135592; internal_power() { rise_power(passive_energy_template_6x1) { index_1 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ("0.382749, 0.422566, 0.488682, 0.630591, 0.740418, 0.955367"); } fall_power(passive_energy_template_6x1) { index_1 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ("0.567677, 0.611799, 0.702822, 0.853421, 0.960626, 1.18171"); } } timing() { related_pin : "CLK"; timing_type : hold_rising; when : "S&R"; sdf_cond : "S\&R"; rise_constraint(hold_template_3x6) { index_1 ("0.06, 0.3, 0.6"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0, -0.0375, -0.11875, -0.14375, -0.08125, -0.14375", \ "-0.0125, -0.05, -0.0375, -0.0625, -0.09375, -0.15625", \ "0.01875, -0.01875, -0.1, -0.125, -0.0625, -0.125"); } fall_constraint(hold_template_3x6) { index_1 ("0.06, 0.3, 0.6"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0, -0.0375, -0.025, -0.14375, -0.175, -0.2375", \ "0.08125, 0.04375, -0.0375, -0.0625, -0.1875, -0.15625", \ "0.1125, 0.075, -0.00625, -0.03125, -0.15625, -0.21875"); } } timing() { related_pin : "CLK"; timing_type : setup_rising; when : "S&R"; sdf_cond : "S\&R"; rise_constraint(setup_template_3x6) { index_1 ("0.06, 0.3, 0.6"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.1875, 0.225, 0.2125, 0.2375, 0.26875, 0.33125", \ "0.10625, 0.14375, 0.225, 0.25, 0.28125, 0.25", \ "0.16875, 0.1125, 0.19375, 0.21875, 0.25, 0.21875"); } fall_constraint(setup_template_3x6) { index_1 ("0.06, 0.3, 0.6"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.09375, 0.225, 0.2125, 0.33125, 0.3625, 0.425", \ "0.10625, 0.14375, 0.225, 0.25, 0.28125, 0.34375", \ "0.2625, 0.20625, 0.38125, 0.3125, 0.34375, 0.40625"); } } } pin(Q) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.40972; function : "P0002"; timing() { related_pin : "CLK"; timing_sense : non_unate; timing_type : rising_edge; cell_rise(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.518879, 0.553894, 0.583445, 0.615694, 0.634389, 0.651872", \ "1.29638, 1.33222, 1.36145, 1.39384, 1.41225, 1.42977", \ "2.6562, 2.69237, 2.72133, 2.75364, 2.77216, 2.78915", \ "6.15258, 6.18845, 6.21703, 6.24944, 6.26788, 6.28573", \ "8.09674, 8.13276, 8.16185, 8.19416, 8.21256, 8.23019", \ "10.0402, 10.0731, 10.1021, 10.1347, 10.1559, 10.1735"); } rise_transition(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.3126, 0.3132, 0.3132, 0.3126, 0.3132, 0.3126", \ "1.4754, 1.4748, 1.476, 1.476, 1.476, 1.4754", \ "3.5232, 3.5226, 3.5232, 3.5232, 3.5232, 3.5232", \ "8.79, 8.79, 8.7906, 8.7906, 8.79, 8.79", \ "11.7132, 11.7126, 11.7132, 11.7132, 11.7132, 11.7126", \ "14.6388, 14.643, 14.6424, 14.643, 14.6394, 14.6388"); } cell_fall(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.519927, 0.556111, 0.58011, 0.611746, 0.621438, 0.62794", \ "1.20214, 1.23863, 1.26253, 1.29378, 1.30349, 1.31059", \ "2.39475, 2.43129, 2.45532, 2.48646, 2.49622, 2.50316", \ "5.46036, 5.49838, 5.52184, 5.55295, 5.56307, 5.56885", \ "7.16466, 7.2019, 7.22477, 7.25581, 7.26615, 7.27223", \ "8.86707, 8.90533, 8.92863, 8.95971, 8.96994, 8.97664"); } fall_transition(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.2544, 0.2544, 0.2526, 0.252, 0.2532, 0.2538", \ "1.1856, 1.1856, 1.1856, 1.1856, 1.1856, 1.1856", \ "2.8338, 2.8332, 2.8344, 2.8344, 2.8344, 2.8338", \ "7.0728, 7.0734, 7.0704, 7.0704, 7.071, 7.0728", \ "9.4266, 9.4278, 9.4248, 9.4242, 9.4248, 9.423", \ "11.7804, 11.7798, 11.781, 11.781, 11.781, 11.781"); } } timing() { related_pin : "R"; timing_sense : positive_unate; timing_type : clear; cell_rise(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.321669, 0.321788, 0.322489, 0.311115, 0.293392, 0.249131", \ "1.0998, 1.09849, 1.10067, 1.09032, 1.07656, 1.04435", \ "2.46004, 2.45864, 2.46035, 2.44954, 2.43583, 2.40415", \ "5.95606, 5.95515, 5.95685, 5.94587, 5.93186, 5.89944", \ "7.89835, 7.8992, 7.90039, 7.88931, 7.87652, 7.84381", \ "9.84213, 9.84196, 9.84286, 9.83281, 9.8179, 9.78743"); } rise_transition(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.3108, 0.3102, 0.3132, 0.3228, 0.3306, 0.3426", \ "1.4754, 1.476, 1.4754, 1.4766, 1.4784, 1.4862", \ "3.5232, 3.5232, 3.5232, 3.5238, 3.5238, 3.5238", \ "8.7906, 8.7894, 8.7906, 8.7912, 8.7906, 8.7906", \ "11.7162, 11.7132, 11.715, 11.7162, 11.712, 11.712", \ "14.6418, 14.64, 14.6418, 14.6412, 14.6418, 14.6346"); } cell_fall(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.341552, 0.401313, 0.477445, 0.593647, 0.671278, 0.807284", \ "1.02414, 1.08349, 1.15886, 1.27467, 1.35041, 1.48904", \ "2.21686, 2.27606, 2.35149, 2.46681, 2.54262, 2.68056", \ "5.28312, 5.34237, 5.41771, 5.53253, 5.60932, 5.74716", \ "6.98608, 7.0459, 7.12111, 7.23609, 7.31199, 7.45038", \ "8.68916, 8.74948, 8.82442, 8.94122, 9.01489, 9.154"); } fall_transition(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.2544, 0.255, 0.2559, 0.258, 0.2604, 0.2649", \ "1.185, 1.185, 1.1853, 1.1859, 1.1865, 1.1874", \ "2.8329, 2.8326, 2.8332, 2.8323, 2.8329, 2.8335", \ "7.0704, 7.0722, 7.0716, 7.071, 7.0713, 7.071", \ "9.4236, 9.4254, 9.4257, 9.4245, 9.4251, 9.4257", \ "11.7798, 11.7807, 11.7786, 11.781, 11.7786, 11.781"); } } timing() { related_pin : "S"; timing_sense : negative_unate; timing_type : preset; cell_rise(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.448887, 0.497874, 0.554617, 0.644514, 0.701256, 0.808065", \ "1.22768, 1.27813, 1.3329, 1.42238, 1.48055, 1.58552", \ "2.58751, 2.63778, 2.69281, 2.7822, 2.84034, 2.94563", \ "6.08394, 6.1344, 6.18894, 6.27837, 6.33707, 6.44195", \ "8.02794, 8.07784, 8.13334, 8.2228, 8.28107, 8.38629", \ "9.97156, 10.0211, 10.0756, 10.166, 10.2233, 10.3279"); } rise_transition(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.3114, 0.3117, 0.312, 0.3123, 0.3126, 0.312", \ "1.4757, 1.4754, 1.476, 1.4757, 1.4751, 1.4748", \ "3.5232, 3.5232, 3.5229, 3.5229, 3.5229, 3.5229", \ "8.7903, 8.79, 8.79, 8.7906, 8.79, 8.79", \ "11.7141, 11.7141, 11.7132, 11.7132, 11.7132, 11.7126", \ "14.6394, 14.6406, 14.64, 14.6394, 14.6406, 14.6409"); } } internal_power() { related_pin : "CLK"; rise_power(energy_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.73592, 0.767062, 0.847522, 0.998322, 1.11965, 1.33817", \ "0.740712, 0.766766, 0.847568, 0.997792, 1.11847, 1.33816", \ "0.742001, 0.76771, 0.848199, 0.99926, 1.11864, 1.33904", \ "0.742234, 0.769158, 0.851447, 0.998907, 1.12025, 1.33929", \ "0.743252, 0.769001, 0.850027, 1.00164, 1.119, 1.3393", \ "0.743022, 0.769319, 0.849512, 1.00253, 1.12015, 1.33815"); } fall_power(energy_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.652746, 0.679211, 0.762324, 0.917066, 1.02414, 1.23933", \ "0.653612, 0.680163, 0.763623, 0.917016, 1.02384, 1.24061", \ "0.654181, 0.680476, 0.763811, 0.917453, 1.02408, 1.24124", \ "0.656278, 0.681096, 0.764012, 0.918748, 1.02496, 1.2418", \ "0.655477, 0.681019, 0.764226, 0.919351, 1.02519, 1.24235", \ "0.655734, 0.681445, 0.765133, 0.920448, 1.02507, 1.24272"); } } internal_power() { related_pin : "R"; rise_power(energy_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.20615, 0.290682, 0.456057, 0.779003, 1.01785, 1.50463", \ "0.207625, 0.289428, 0.454932, 0.77241, 1.00773, 1.48583", \ "0.208681, 0.289756, 0.455714, 0.772039, 1.00659, 1.48294", \ "0.211731, 0.290253, 0.457481, 0.771521, 1.00683, 1.48247", \ "0.211832, 0.288517, 0.456976, 0.770572, 1.00623, 1.48266", \ "0.209139, 0.288574, 0.457661, 0.770983, 1.00597, 1.48139"); } fall_power(energy_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.759664, 0.856842, 1.03816, 1.35291, 1.54871, 1.88746", \ "0.75968, 0.856286, 1.0364, 1.34526, 1.53472, 1.87098", \ "0.759784, 0.856702, 1.03644, 1.34488, 1.53358, 1.8692", \ "0.760096, 0.856528, 1.03619, 1.34576, 1.53368, 1.86998", \ "0.759313, 0.855817, 1.03631, 1.34498, 1.53304, 1.86983", \ "0.760394, 0.856357, 1.03605, 1.34518, 1.53299, 1.86998"); } } internal_power() { related_pin : "S"; power(energy_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.764103, 0.832183, 0.96869, 1.23199, 1.41228, 1.74388", \ "0.762519, 0.831107, 0.968504, 1.2326, 1.41061, 1.74354", \ "0.76294, 0.831724, 0.969316, 1.23278, 1.41143, 1.74383", \ "0.763088, 0.832069, 0.970481, 1.23304, 1.41227, 1.74375", \ "0.763189, 0.831805, 0.970165, 1.23362, 1.41264, 1.74461", \ "0.762444, 0.831836, 0.970262, 1.23402, 1.41094, 1.74334"); } } } pin(R) { direction : input; capacitance : 0.0357813; rise_capacitance : 0.0357813; fall_capacitance : 0.0317563; min_pulse_width_low : 0.192019; timing() { related_pin : "CLK"; timing_type : recovery_rising; when : "D&S"; sdf_cond : "D\&S"; rise_constraint(recovery_template_3x6) { index_1 ("0.06, 0.3, 0.6"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "-0.09375, -0.15, -0.06875, 0.05, 0.175, 0.33125", \ "-0.08125, -0.1375, -0.05625, 0.0625, 0.1875, 0.15625", \ "-0.20625, -0.16875, -0.18125, -0.0625, -0.03125, 0.21875"); } } timing() { related_pin : "S"; timing_type : recovery_rising; rise_constraint(recovery_template_6x6) { index_1 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0, 0.05625, 0.06875, 0.04375, 0.10625, 0.184375", \ "0.0375, 0, 0.0125, 0.08125, 0.14375, 0.175", \ "0.025, 0.034375, 0, 0.06875, 0.13125, 0.1625", \ "0.003125, 0.0125, 0.025, 0.046875, 0.0625, 0.140625", \ "-0.0125, -0.003125, 0.009375, 0.03125, 0.09375, 0.125", \ "-0.04375, -0.034375, -0.021875, 0, 0.015625, 0.09375"); } } timing() { related_pin : "CLK"; timing_type : removal_rising; when : "D&S"; sdf_cond : "D\&S"; rise_constraint(removal_template_3x6) { index_1 ("0.06, 0.3, 0.6"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.28125, 0.24375, 0.35, 0.41875, 0.3875, 0.5125", \ "0.26875, 0.325, 0.3375, 0.40625, 0.46875, 0.59375", \ "0.3, 0.35625, 0.36875, 0.4375, 0.5, 0.625"); } } } pin(S) { direction : input; capacitance : 0.0323255; rise_capacitance : 0.021334; fall_capacitance : 0.0323255; internal_power() { rise_power(passive_energy_template_6x1) { index_1 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ("0.19773, 0.187624, 0.18974, 0.198762, 0.197079, 0.201817"); } fall_power(passive_energy_template_6x1) { index_1 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ("0, 0, 0, 0, 0, 0"); } } min_pulse_width_low : 0.255376; timing() { related_pin : "CLK"; timing_type : recovery_rising; when : "!D&R"; sdf_cond : "\~D\&R"; rise_constraint(recovery_template_3x6) { index_1 ("0.06, 0.3, 0.6"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0, 0.0375, 0.025, 0.05, 0.08125, 0.2375", \ "0.0125, -0.04375, 0.0375, 0.0625, 0.09375, 0.15625", \ "0.075, 0.01875, 0.00625, 0.40625, 0.15625, 0.40625"); } } timing() { related_pin : "R"; timing_type : recovery_rising; rise_constraint(recovery_template_6x6) { index_1 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.09375, 0.05625, 0.06875, 0.090625, 0.10625, 0.1375", \ "0.0375, 0.09375, 0.059375, 0.08125, 0.096875, 0.128125", \ "0.071875, 0.08125, 0.09375, 0.06875, 0.084375, 0.115625", \ "0.05, 0.0125, 0.025, 0.046875, 0.0625, 0.09375", \ "0.034375, -0.003125, 0.009375, 0.03125, 0.046875, 0.078125", \ "-0.04375, -0.034375, -0.021875, -0.046875, 0.015625, 0.046875"); } } timing() { related_pin : "CLK"; timing_type : removal_rising; when : "!D&R"; sdf_cond : "\~D\&R"; rise_constraint(removal_template_3x6) { index_1 ("0.06, 0.3, 0.6"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.09375, 0.15, 0.06875, 0.04375, 0.10625, 0.04375", \ "0.175, 0.1375, 0.15, 0.125, 0.09375, 0.125", \ "0.20625, 0.16875, 0.18125, 0.15625, 0.125, 0.15625"); } } } } /* ------------- * * Design : FAX1 * * ------------- */ cell (FAX1) { area : 480; cell_leakage_power : 0.162133; pin(A) { direction : input; capacitance : 0.101702; rise_capacitance : 0.100648; fall_capacitance : 0.101702; } pin(B) { direction : input; capacitance : 0.0912748; rise_capacitance : 0.0912748; fall_capacitance : 0.0860056; } pin(C) { direction : input; capacitance : 0.064336; rise_capacitance : 0.064336; fall_capacitance : 0.064233; } pin(YC) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.405612; function : "(((A B)+(B C))+(C A))"; timing() { related_pin : "A"; timing_sense : positive_unate; cell_rise(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.192937, 0.202293, 0.222417, 0.23603, 0.262001", \ "0.252032, 0.261902, 0.282854, 0.297212, 0.327113", \ "0.336688, 0.345538, 0.368228, 0.382804, 0.417572", \ "0.575869, 0.585084, 0.608065, 0.623073, 0.660902", \ "0.965229, 0.974557, 0.997456, 1.01213, 1.05025"); } rise_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0816, 0.0804, 0.0879, 0.0939, 0.1068", \ "0.1503, 0.1476, 0.1527, 0.1587, 0.1722", \ "0.2637, 0.2625, 0.2661, 0.2682, 0.2817", \ "0.606, 0.606, 0.6069, 0.6087, 0.6159", \ "1.185, 1.185, 1.185, 1.1856, 1.1886"); } cell_fall(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.212316, 0.230368, 0.271993, 0.301851, 0.392584", \ "0.274262, 0.291144, 0.334346, 0.364751, 0.461587", \ "0.355791, 0.3728, 0.417563, 0.448945, 0.550937", \ "0.569312, 0.586364, 0.631171, 0.663795, 0.770166", \ "0.910578, 0.927654, 0.972381, 1.00471, 1.11225"); } fall_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0756, 0.0777, 0.0837, 0.0891, 0.105", \ "0.1362, 0.1368, 0.1386, 0.1446, 0.162", \ "0.2247, 0.2247, 0.2292, 0.2319, 0.2487", \ "0.4911, 0.4911, 0.4917, 0.4947, 0.5031", \ "0.9528, 0.9528, 0.9528, 0.9534, 0.957"); } } timing() { related_pin : "B"; timing_sense : positive_unate; cell_rise(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.201655, 0.213928, 0.238544, 0.251321, 0.282216", \ "0.259034, 0.272741, 0.300326, 0.314485, 0.347352", \ "0.344335, 0.358175, 0.387437, 0.402523, 0.438405", \ "0.584089, 0.597845, 0.62806, 0.645074, 0.683716", \ "0.97336, 0.98699, 1.01703, 1.03436, 1.07543"); } rise_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0831, 0.0819, 0.0876, 0.0897, 0.0969", \ "0.15, 0.1515, 0.1563, 0.1596, 0.1704", \ "0.2637, 0.264, 0.2691, 0.2715, 0.2832", \ "0.6066, 0.6066, 0.6081, 0.6102, 0.6186", \ "1.185, 1.185, 1.185, 1.1859, 1.1907"); } cell_fall(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.221213, 0.240731, 0.285449, 0.315389, 0.41356", \ "0.283246, 0.303871, 0.352007, 0.382508, 0.482071", \ "0.366584, 0.387835, 0.439518, 0.471404, 0.573799", \ "0.583619, 0.604617, 0.657663, 0.693503, 0.801186", \ "0.925474, 0.94676, 0.999626, 1.03604, 1.14957"); } fall_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0786, 0.0768, 0.0831, 0.0906, 0.1008", \ "0.1389, 0.1404, 0.1467, 0.1485, 0.1608", \ "0.2298, 0.2289, 0.2367, 0.2424, 0.2532", \ "0.495, 0.4953, 0.4974, 0.5025, 0.5145", \ "0.9543, 0.9549, 0.9546, 0.9561, 0.966"); } } timing() { related_pin : "C"; timing_sense : positive_unate; cell_rise(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.185775, 0.210399, 0.245686, 0.266778, 0.312469", \ "0.243892, 0.27024, 0.307336, 0.328971, 0.375209", \ "0.329181, 0.355023, 0.394669, 0.415937, 0.465802", \ "0.568872, 0.594357, 0.633929, 0.655734, 0.706132", \ "0.957725, 0.98325, 1.0226, 1.04421, 1.09553"); } rise_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0852, 0.0807, 0.0921, 0.0945, 0.1008", \ "0.1524, 0.1509, 0.1548, 0.1602, 0.1707", \ "0.2637, 0.2634, 0.2685, 0.2706, 0.2817", \ "0.606, 0.606, 0.606, 0.6081, 0.6135", \ "1.1841, 1.1844, 1.1841, 1.1847, 1.188"); } cell_fall(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.203317, 0.232392, 0.29518, 0.334702, 0.453856", \ "0.264792, 0.295214, 0.360803, 0.400337, 0.521061", \ "0.348261, 0.378841, 0.445571, 0.486885, 0.609869", \ "0.565673, 0.595953, 0.662919, 0.706274, 0.83131", \ "0.90777, 0.938204, 1.00512, 1.04815, 1.17621"); } fall_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0792, 0.0765, 0.0843, 0.0912, 0.1044", \ "0.1365, 0.1401, 0.1476, 0.1494, 0.162", \ "0.2298, 0.2289, 0.2343, 0.2388, 0.2496", \ "0.4947, 0.495, 0.4965, 0.4998, 0.5079", \ "0.9543, 0.9546, 0.9546, 0.9552, 0.9612"); } } internal_power() { related_pin : "A"; rise_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "-0.007976, -0.001582, 0.046036, 0.096632, 0.303378", \ "0.003901, 0.006036, 0.053579, 0.102898, 0.293237", \ "0.004187, 0.006911, 0.054089, 0.101705, 0.286621", \ "0.002743, 0.005395, 0.051254, 0.098395, 0.279569", \ "0.001821, 0.004696, 0.050175, 0.096875, 0.276158"); } fall_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.751435, 0.756822, 0.815911, 0.870229, 1.07082", \ "0.753113, 0.756525, 0.814098, 0.868209, 1.05967", \ "0.752309, 0.755483, 0.812912, 0.865268, 1.05629", \ "0.751447, 0.754547, 0.811504, 0.863135, 1.04992", \ "0.751138, 0.754253, 0.811014, 0.862398, 1.04726"); } } internal_power() { related_pin : "B"; rise_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.079095, 0.071988, 0.108511, 0.145461, 0.323354", \ "0.087668, 0.081948, 0.11915, 0.154305, 0.313515", \ "0.088238, 0.082519, 0.119066, 0.154328, 0.306697", \ "0.086954, 0.081108, 0.116745, 0.152259, 0.302454", \ "0.086343, 0.080371, 0.115854, 0.151083, 0.299904"); } fall_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.697594, 0.691911, 0.738172, 0.776694, 0.94822", \ "0.698733, 0.693453, 0.736748, 0.780343, 0.935934", \ "0.69733, 0.692467, 0.734847, 0.777073, 0.936829", \ "0.694698, 0.690931, 0.732109, 0.774157, 0.931782", \ "0.694056, 0.690307, 0.731288, 0.773142, 0.929401"); } } internal_power() { related_pin : "C"; rise_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.163673, 0.165668, 0.189463, 0.22829, 0.390871", \ "0.165439, 0.17055, 0.197339, 0.235655, 0.382059", \ "0.166138, 0.169989, 0.199144, 0.23583, 0.377468", \ "0.166578, 0.169587, 0.197806, 0.233484, 0.371962", \ "0.166896, 0.169673, 0.197451, 0.232882, 0.369249"); } fall_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.583181, 0.587626, 0.631498, 0.669882, 0.82487", \ "0.585184, 0.588504, 0.631341, 0.669054, 0.811996", \ "0.585161, 0.586867, 0.628181, 0.667229, 0.810344", \ "0.582139, 0.584993, 0.625643, 0.66373, 0.805293", \ "0.581744, 0.584612, 0.625012, 0.662479, 0.802606"); } } } pin(YS) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.409456; function : "((A^B)^C)"; timing() { related_pin : "A"; timing_sense : non_unate; cell_rise(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.311797, 0.328706, 0.370858, 0.401209, 0.489974", \ "0.367147, 0.383417, 0.426146, 0.453648, 0.544812", \ "0.446564, 0.463136, 0.505936, 0.532612, 0.62307", \ "0.679909, 0.69597, 0.739454, 0.766625, 0.856786", \ "1.06837, 1.08444, 1.12769, 1.15482, 1.24479"); } rise_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0762, 0.0753, 0.0768, 0.0777, 0.078", \ "0.1437, 0.1443, 0.1437, 0.1428, 0.1455", \ "0.2535, 0.2544, 0.2544, 0.2538, 0.2538", \ "0.5994, 0.5994, 0.5997, 0.5997, 0.6", \ "1.1832, 1.1832, 1.1829, 1.1835, 1.1832"); } cell_fall(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.299535, 0.309958, 0.329301, 0.341262, 0.363669", \ "0.357539, 0.367622, 0.38617, 0.399449, 0.421082", \ "0.434309, 0.445615, 0.464819, 0.476385, 0.49848", \ "0.644759, 0.656249, 0.67551, 0.68687, 0.70887", \ "0.985959, 0.997573, 1.01673, 1.02809, 1.04987"); } fall_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0753, 0.0756, 0.0726, 0.0774, 0.0798", \ "0.1323, 0.1299, 0.1314, 0.1329, 0.1341", \ "0.2184, 0.2187, 0.2187, 0.2184, 0.2187", \ "0.4881, 0.4881, 0.4884, 0.4887, 0.4884", \ "0.9525, 0.9525, 0.9528, 0.9531, 0.9525"); } } timing() { related_pin : "B"; timing_sense : non_unate; cell_rise(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.326354, 0.343646, 0.392103, 0.426361, 0.525078", \ "0.381898, 0.400236, 0.44672, 0.478563, 0.576663", \ "0.462937, 0.480605, 0.527821, 0.559818, 0.65523", \ "0.698543, 0.715548, 0.762286, 0.793601, 0.888746", \ "1.08749, 1.10456, 1.15106, 1.18221, 1.27704"); } rise_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0774, 0.0786, 0.0801, 0.0822, 0.0807", \ "0.1482, 0.1467, 0.1479, 0.1461, 0.1464", \ "0.2568, 0.2568, 0.2571, 0.2553, 0.2547", \ "0.6012, 0.6012, 0.6012, 0.6006, 0.6003", \ "1.1838, 1.1841, 1.1841, 1.1838, 1.1838"); } cell_fall(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.311475, 0.321628, 0.34643, 0.359418, 0.388969", \ "0.368563, 0.378796, 0.403685, 0.415647, 0.443952", \ "0.446227, 0.456405, 0.482051, 0.493458, 0.521028", \ "0.656751, 0.667049, 0.692618, 0.704328, 0.731082", \ "0.998102, 1.00844, 1.03396, 1.04592, 1.07192"); } fall_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0771, 0.0768, 0.075, 0.0765, 0.0768", \ "0.1341, 0.1341, 0.1326, 0.1314, 0.1314", \ "0.219, 0.2187, 0.2178, 0.2187, 0.2172", \ "0.4881, 0.4884, 0.4881, 0.4881, 0.4875", \ "0.9531, 0.9531, 0.9528, 0.9528, 0.9522"); } } timing() { related_pin : "C"; timing_sense : non_unate; cell_rise(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.322002, 0.346854, 0.408441, 0.447656, 0.560705", \ "0.376032, 0.403646, 0.463433, 0.50045, 0.613575", \ "0.455609, 0.483999, 0.542842, 0.580766, 0.69238", \ "0.690799, 0.71776, 0.777098, 0.815784, 0.926969", \ "1.07981, 1.10678, 1.16586, 1.20454, 1.31715"); } rise_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0783, 0.0798, 0.0804, 0.0753, 0.0765", \ "0.1482, 0.1461, 0.1461, 0.1443, 0.1443", \ "0.2562, 0.2568, 0.2565, 0.2565, 0.255", \ "0.6012, 0.6012, 0.6018, 0.6021, 0.603", \ "1.1844, 1.1844, 1.1841, 1.1844, 1.1862"); } cell_fall(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.296791, 0.3165, 0.344383, 0.367168, 0.404984", \ "0.350874, 0.372846, 0.399754, 0.421069, 0.455738", \ "0.424904, 0.447341, 0.475681, 0.494426, 0.531328", \ "0.632276, 0.654496, 0.683205, 0.702501, 0.738492", \ "0.973424, 0.995389, 1.02414, 1.04363, 1.07937"); } fall_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.072, 0.0708, 0.0678, 0.0759, 0.0699", \ "0.1242, 0.1236, 0.1236, 0.1236, 0.1218", \ "0.2118, 0.2118, 0.2118, 0.21, 0.2106", \ "0.4839, 0.4839, 0.4842, 0.4848, 0.4839", \ "0.9513, 0.9516, 0.9519, 0.9519, 0.9519"); } } internal_power() { related_pin : "A"; rise_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.751435, 0.756822, 0.815911, 0.870229, 1.07082", \ "0.753113, 0.756525, 0.814098, 0.868209, 1.05967", \ "0.752309, 0.755483, 0.812912, 0.865268, 1.05629", \ "0.751447, 0.754547, 0.811504, 0.863135, 1.04992", \ "0.751138, 0.754253, 0.811014, 0.862398, 1.04726"); } fall_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "-0.007976, -0.001582, 0.046036, 0.096632, 0.303378", \ "0.003901, 0.006036, 0.053579, 0.102898, 0.293237", \ "0.004187, 0.006911, 0.054089, 0.101705, 0.286621", \ "0.002743, 0.005395, 0.051254, 0.098395, 0.279569", \ "0.001821, 0.004696, 0.050175, 0.096875, 0.276158"); } } internal_power() { related_pin : "B"; rise_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.697594, 0.691911, 0.738172, 0.776694, 0.94822", \ "0.698733, 0.693453, 0.736748, 0.780343, 0.935934", \ "0.69733, 0.692467, 0.734847, 0.777073, 0.936829", \ "0.694698, 0.690931, 0.732109, 0.774157, 0.931782", \ "0.694056, 0.690307, 0.731288, 0.773142, 0.929401"); } fall_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.079095, 0.071988, 0.108511, 0.145461, 0.323354", \ "0.087668, 0.081948, 0.11915, 0.154305, 0.313515", \ "0.088238, 0.082519, 0.119066, 0.154328, 0.306697", \ "0.086954, 0.081108, 0.116745, 0.152259, 0.302454", \ "0.086343, 0.080371, 0.115854, 0.151083, 0.299904"); } } internal_power() { related_pin : "C"; rise_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.583181, 0.587626, 0.631498, 0.669882, 0.82487", \ "0.585184, 0.588504, 0.631341, 0.669054, 0.811996", \ "0.585161, 0.586867, 0.628181, 0.667229, 0.810344", \ "0.582139, 0.584993, 0.625643, 0.66373, 0.805293", \ "0.581744, 0.584612, 0.625012, 0.662479, 0.802606"); } fall_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.163673, 0.165668, 0.189463, 0.22829, 0.390871", \ "0.165439, 0.17055, 0.197339, 0.235655, 0.382059", \ "0.166138, 0.169989, 0.199144, 0.23583, 0.377468", \ "0.166578, 0.169587, 0.197806, 0.233484, 0.371962", \ "0.166896, 0.169673, 0.197451, 0.232882, 0.369249"); } } } } /* ------------- * * Design : HAX1 * * ------------- */ cell (HAX1) { area : 320; cell_leakage_power : 0.119043; pin(A) { direction : input; capacitance : 0.0388022; rise_capacitance : 0.0386075; fall_capacitance : 0.0388022; } pin(B) { direction : input; capacitance : 0.0305266; rise_capacitance : 0.0305266; fall_capacitance : 0.0303638; } pin(YC) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.409798; function : "(A B)"; timing() { related_pin : "A"; timing_sense : positive_unate; cell_rise(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.140081, 0.141507, 0.145815, 0.141975, 0.105465", \ "0.192758, 0.200282, 0.205017, 0.200982, 0.169417", \ "0.273446, 0.281692, 0.28655, 0.283745, 0.257017", \ "0.508344, 0.515827, 0.521407, 0.519244, 0.498649", \ "0.897028, 0.904153, 0.909429, 0.9075, 0.887575"); } rise_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0762, 0.078, 0.0852, 0.0876, 0.1026", \ "0.1416, 0.1452, 0.1524, 0.1554, 0.1668", \ "0.2544, 0.2544, 0.2598, 0.2634, 0.2772", \ "0.5994, 0.6, 0.6012, 0.603, 0.6126", \ "1.1832, 1.1832, 1.1826, 1.1832, 1.1874"); } cell_fall(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.177776, 0.21539, 0.292039, 0.344016, 0.503526", \ "0.233812, 0.271739, 0.350776, 0.403476, 0.564403", \ "0.308649, 0.346346, 0.425841, 0.47909, 0.641612", \ "0.515371, 0.552913, 0.632453, 0.686181, 0.849006", \ "0.85623, 0.893748, 0.973013, 1.02703, 1.19026"); } fall_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0708, 0.069, 0.0774, 0.0792, 0.0936", \ "0.123, 0.1272, 0.1296, 0.1332, 0.147", \ "0.2112, 0.2124, 0.2136, 0.2178, 0.2274", \ "0.483, 0.483, 0.4836, 0.4836, 0.4884", \ "0.951, 0.951, 0.951, 0.951, 0.9534"); } } timing() { related_pin : "B"; timing_sense : positive_unate; cell_rise(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.139715, 0.15581, 0.175213, 0.182298, 0.18117", \ "0.192261, 0.211131, 0.230293, 0.236731, 0.243006", \ "0.272931, 0.292124, 0.312354, 0.319517, 0.327988", \ "0.507829, 0.526401, 0.547907, 0.55753, 0.566311", \ "0.896495, 0.914845, 0.936268, 0.945993, 0.956004"); } rise_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0762, 0.0762, 0.0852, 0.087, 0.102", \ "0.141, 0.1434, 0.1506, 0.1506, 0.1656", \ "0.2544, 0.2544, 0.2592, 0.2628, 0.2718", \ "0.5994, 0.5994, 0.6018, 0.6036, 0.609", \ "1.1832, 1.1832, 1.1832, 1.1838, 1.1874"); } cell_fall(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.160211, 0.196061, 0.260214, 0.304966, 0.432663", \ "0.214866, 0.250091, 0.317945, 0.36421, 0.49646", \ "0.288617, 0.324615, 0.393692, 0.440081, 0.575944", \ "0.495085, 0.531067, 0.601112, 0.647765, 0.78546", \ "0.835833, 0.871869, 0.941836, 0.988954, 1.12754"); } fall_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0672, 0.0666, 0.0744, 0.0762, 0.093", \ "0.1242, 0.126, 0.1272, 0.1326, 0.147", \ "0.2082, 0.21, 0.213, 0.216, 0.2298", \ "0.4824, 0.483, 0.4836, 0.4854, 0.4902", \ "0.951, 0.951, 0.951, 0.951, 0.9534"); } } internal_power() { related_pin : "A"; rise_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.160514, 0.158463, 0.199779, 0.237029, 0.37704", \ "0.160504, 0.164431, 0.197887, 0.235585, 0.367328", \ "0.160164, 0.163356, 0.195988, 0.232262, 0.363547", \ "0.160314, 0.162774, 0.194761, 0.230046, 0.358362", \ "0.160403, 0.162513, 0.1944, 0.227908, 0.356257"); } fall_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.396875, 0.404062, 0.452447, 0.492602, 0.643019", \ "0.397423, 0.40069, 0.450249, 0.492511, 0.632396", \ "0.397506, 0.402443, 0.448683, 0.490893, 0.629695", \ "0.398133, 0.401943, 0.447108, 0.489025, 0.624878", \ "0.398197, 0.402345, 0.447218, 0.487214, 0.62227"); } } internal_power() { related_pin : "B"; rise_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.224658, 0.22892, 0.261757, 0.297231, 0.433047", \ "0.225463, 0.230122, 0.257896, 0.290358, 0.423966", \ "0.2258, 0.22928, 0.257436, 0.29253, 0.419676", \ "0.226698, 0.22981, 0.258413, 0.291162, 0.415098", \ "0.227315, 0.229978, 0.258481, 0.289359, 0.413455"); } fall_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.330044, 0.338208, 0.379681, 0.415719, 0.549072", \ "0.329278, 0.337061, 0.380366, 0.416585, 0.543336", \ "0.33099, 0.338175, 0.378926, 0.414532, 0.538716", \ "0.331315, 0.338473, 0.377401, 0.4134, 0.534897", \ "0.331856, 0.339051, 0.377815, 0.412232, 0.532665"); } } } pin(YS) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.410646; function : "(A^B)"; timing() { related_pin : "A"; timing_sense : non_unate; cell_rise(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.226483, 0.264825, 0.335188, 0.385169, 0.539641", \ "0.279458, 0.314273, 0.387161, 0.439429, 0.591255", \ "0.357283, 0.392988, 0.465122, 0.517341, 0.668378", \ "0.590066, 0.627756, 0.700682, 0.749613, 0.900129", \ "0.97829, 1.01614, 1.08881, 1.14012, 1.28984"); } rise_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0744, 0.0726, 0.0732, 0.075, 0.0798", \ "0.1386, 0.1398, 0.1386, 0.1398, 0.1416", \ "0.2502, 0.2496, 0.2508, 0.2502, 0.2514", \ "0.5988, 0.5988, 0.5988, 0.5982, 0.5976", \ "1.1826, 1.1826, 1.1826, 1.1826, 1.1826"); } cell_fall(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.245071, 0.245767, 0.25396, 0.249775, 0.222849", \ "0.294656, 0.297167, 0.301037, 0.298483, 0.271082", \ "0.364286, 0.367589, 0.372678, 0.368259, 0.338349", \ "0.568746, 0.572204, 0.577076, 0.571975, 0.544754", \ "0.909275, 0.913048, 0.917501, 0.913574, 0.884601"); } fall_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0696, 0.0654, 0.0642, 0.0684, 0.0648", \ "0.117, 0.1188, 0.1134, 0.1146, 0.1194", \ "0.204, 0.2028, 0.2034, 0.2028, 0.2046", \ "0.4812, 0.4812, 0.4806, 0.48, 0.4806", \ "0.9504, 0.9504, 0.9504, 0.9504, 0.9498"); } } timing() { related_pin : "B"; timing_sense : non_unate; cell_rise(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.223106, 0.258079, 0.322791, 0.367532, 0.490477", \ "0.274891, 0.311397, 0.377288, 0.420411, 0.542851", \ "0.357884, 0.392727, 0.454702, 0.498672, 0.62117", \ "0.590898, 0.625574, 0.690412, 0.731576, 0.853157", \ "0.979674, 1.01443, 1.07902, 1.12177, 1.24272"); } rise_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0774, 0.0762, 0.072, 0.075, 0.0792", \ "0.1428, 0.1422, 0.1368, 0.138, 0.141", \ "0.2514, 0.252, 0.2502, 0.2508, 0.2514", \ "0.5988, 0.5982, 0.5988, 0.5994, 0.5982", \ "1.1832, 1.1832, 1.1832, 1.1832, 1.1832"); } cell_fall(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.245491, 0.258393, 0.280463, 0.287808, 0.297282", \ "0.295235, 0.307083, 0.324249, 0.334572, 0.34247", \ "0.365064, 0.377362, 0.393697, 0.402759, 0.413535", \ "0.569651, 0.581639, 0.599156, 0.608359, 0.619514", \ "0.910265, 0.922458, 0.940059, 0.950117, 0.958697"); } fall_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0696, 0.063, 0.0642, 0.0678, 0.0648", \ "0.117, 0.1194, 0.114, 0.1194, 0.1182", \ "0.204, 0.2028, 0.2016, 0.2016, 0.2064", \ "0.4812, 0.4812, 0.4806, 0.48, 0.4806", \ "0.951, 0.951, 0.9504, 0.9504, 0.9486"); } } internal_power() { related_pin : "A"; rise_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.396875, 0.404062, 0.452447, 0.492602, 0.643019", \ "0.397423, 0.40069, 0.450249, 0.492511, 0.632396", \ "0.397506, 0.402443, 0.448683, 0.490893, 0.629695", \ "0.398133, 0.401943, 0.447108, 0.489025, 0.624878", \ "0.398197, 0.402345, 0.447218, 0.487214, 0.62227"); } fall_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.160514, 0.158463, 0.199779, 0.237029, 0.37704", \ "0.160504, 0.164431, 0.197887, 0.235585, 0.367328", \ "0.160164, 0.163356, 0.195988, 0.232262, 0.363547", \ "0.160314, 0.162774, 0.194761, 0.230046, 0.358362", \ "0.160403, 0.162513, 0.1944, 0.227908, 0.356257"); } } internal_power() { related_pin : "B"; rise_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.330044, 0.338208, 0.379681, 0.415719, 0.549072", \ "0.329278, 0.337061, 0.380366, 0.416585, 0.543336", \ "0.33099, 0.338175, 0.378926, 0.414532, 0.538716", \ "0.331315, 0.338473, 0.377401, 0.4134, 0.534897", \ "0.331856, 0.339051, 0.377815, 0.412232, 0.532665"); } fall_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.224658, 0.22892, 0.261757, 0.297231, 0.433047", \ "0.225463, 0.230122, 0.257896, 0.290358, 0.423966", \ "0.2258, 0.22928, 0.257436, 0.29253, 0.419676", \ "0.226698, 0.22981, 0.258413, 0.291162, 0.415098", \ "0.227315, 0.229978, 0.258481, 0.289359, 0.413455"); } } } } /* -------------- * * Design : INVX1 * * -------------- */ cell (INVX1) { cell_footprint : inv; area : 64; cell_leakage_power : 0.0152465; pin(A) { direction : input; capacitance : 0.0134094; rise_capacitance : 0.0133816; fall_capacitance : 0.0134094; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.411688; function : "(!A)"; timing() { related_pin : "A"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.052639, 0.068333, 0.081478, 0.085569, 0.084748", \ "0.097195, 0.126587, 0.16039, 0.17465, 0.201755", \ "0.165859, 0.196317, 0.252434, 0.279356, 0.337341", \ "0.370193, 0.400018, 0.462928, 0.51244, 0.636385", \ "0.711823, 0.740267, 0.800617, 0.847739, 1.01201"); } fall_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.052483, 0.081, 0.1224, 0.147, 0.2352", \ "0.102, 0.126, 0.1776, 0.2118, 0.3198", \ "0.198, 0.2016, 0.2544, 0.2964, 0.4182", \ "0.4782, 0.4782, 0.4926, 0.5226, 0.6624", \ "0.9486, 0.9486, 0.9486, 0.9534, 1.0398"); } cell_rise(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.058149, 0.090142, 0.128455, 0.154985, 0.223129", \ "0.108058, 0.145152, 0.205349, 0.241092, 0.338706", \ "0.186156, 0.222784, 0.298417, 0.345512, 0.472922", \ "0.418848, 0.453345, 0.529245, 0.588239, 0.771661", \ "0.8072, 0.841235, 0.913651, 0.969975, 1.16561"); } rise_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.063, 0.0918, 0.129, 0.1566, 0.2322", \ "0.1314, 0.1458, 0.1926, 0.2262, 0.3234", \ "0.2472, 0.2508, 0.2874, 0.3252, 0.4368", \ "0.597, 0.5964, 0.6042, 0.624, 0.7302", \ "1.1808, 1.1814, 1.1814, 1.1826, 1.236"); } } internal_power() { related_pin : "A"; fall_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.049646, 0.035086, 0.026031, 0.078193, 0.265592", \ "0.048186, 0.0394, 0.00589, 0.049663, 0.218626", \ "0.046864, 0.041207, 0.008276, 0.026567, 0.17172", \ "0.04576, 0.042684, 0.023921, 0.001348, 0.103465", \ "0.0448, 0.043548, 0.032279, 0.017652, 0.056285"); } rise_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.119298, 0.145859, 0.211551, 0.266374, 0.457786", \ "0.122167, 0.136701, 0.19091, 0.239316, 0.417647", \ "0.123064, 0.133133, 0.174199, 0.215185, 0.375367", \ "0.124147, 0.128553, 0.153734, 0.182116, 0.306417", \ "0.124642, 0.126623, 0.142218, 0.161175, 0.252866"); } } } } /* -------------- * * Design : INVX2 * * -------------- */ cell (INVX2) { cell_footprint : inv; area : 64; cell_leakage_power : 0.0157446; pin(A) { direction : input; capacitance : 0.0274396; rise_capacitance : 0.0273864; fall_capacitance : 0.0274396; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.833389; function : "(!A)"; timing() { related_pin : "A"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.03, 0.08, 0.16, 0.4, 0.8"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.053273, 0.06978, 0.084273, 0.089866, 0.093537", \ "0.098224, 0.127946, 0.162893, 0.178321, 0.209513", \ "0.167714, 0.1981, 0.255068, 0.282839, 0.344741", \ "0.374102, 0.403842, 0.466889, 0.516504, 0.643132", \ "0.719218, 0.747557, 0.807921, 0.854974, 1.01972"); } fall_transition(delay_template_5x5) { index_1 ("0.03, 0.08, 0.16, 0.4, 0.8"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.05309, 0.081, 0.1224, 0.1458, 0.234", \ "0.1038, 0.1266, 0.1782, 0.213, 0.3204", \ "0.2004, 0.2046, 0.2556, 0.2976, 0.4182", \ "0.4836, 0.4842, 0.498, 0.5274, 0.6642", \ "0.96, 0.96, 0.96, 0.9642, 1.0488"); } cell_rise(delay_template_5x5) { index_1 ("0.03, 0.08, 0.16, 0.4, 0.8"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.057563, 0.088297, 0.124843, 0.148937, 0.213231", \ "0.106557, 0.143139, 0.200715, 0.235009, 0.327528", \ "0.183803, 0.21972, 0.293462, 0.338716, 0.461012", \ "0.412816, 0.446995, 0.521494, 0.579617, 0.757738", \ "0.795462, 0.828949, 0.900107, 0.95544, 1.14805"); } rise_transition(delay_template_5x5) { index_1 ("0.03, 0.08, 0.16, 0.4, 0.8"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0624, 0.0912, 0.1284, 0.1548, 0.2304", \ "0.1302, 0.1458, 0.1926, 0.2256, 0.3228", \ "0.2442, 0.2478, 0.2862, 0.324, 0.4344", \ "0.5898, 0.5898, 0.5976, 0.6186, 0.7266", \ "1.167, 1.1676, 1.167, 1.1682, 1.2246"); } } internal_power() { related_pin : "A"; fall_power(energy_template_5x5) { index_1 ("0.03, 0.08, 0.16, 0.4, 0.8"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.101724, 0.071701, 0.051374, 0.157485, 0.537212", \ "0.098082, 0.080785, 0.011251, 0.099968, 0.442596", \ "0.095359, 0.083957, 0.017501, 0.053193, 0.347889", \ "0.09303, 0.086987, 0.049073, 0.003257, 0.209651", \ "0.091167, 0.088673, 0.065853, 0.03622, 0.114007"); } rise_power(energy_template_5x5) { index_1 ("0.03, 0.08, 0.16, 0.4, 0.8"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.243651, 0.297099, 0.429621, 0.541015, 0.928771", \ "0.249269, 0.278856, 0.388479, 0.486386, 0.8477", \ "0.251342, 0.27161, 0.354766, 0.437759, 0.762223", \ "0.253549, 0.262561, 0.313436, 0.370899, 0.622707", \ "0.254513, 0.258642, 0.290179, 0.328649, 0.514457"); } } } } /* -------------- * * Design : INVX4 * * -------------- */ cell (INVX4) { cell_footprint : inv; area : 96; cell_leakage_power : 0.0314893; pin(A) { direction : input; capacitance : 0.0548793; rise_capacitance : 0.0547729; fall_capacitance : 0.0548793; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 1.66678; function : "(!A)"; timing() { related_pin : "A"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.06, 0.16, 0.32, 0.8, 1.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.053273, 0.06978, 0.084273, 0.089866, 0.093537", \ "0.098224, 0.127946, 0.162893, 0.178321, 0.209513", \ "0.167714, 0.1981, 0.255068, 0.282839, 0.344741", \ "0.374102, 0.403842, 0.466889, 0.516504, 0.643132", \ "0.719218, 0.747557, 0.807921, 0.854974, 1.01972"); } fall_transition(delay_template_5x5) { index_1 ("0.06, 0.16, 0.32, 0.8, 1.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.05309, 0.081, 0.1224, 0.1458, 0.234", \ "0.1038, 0.1266, 0.1782, 0.213, 0.3204", \ "0.2004, 0.2046, 0.2556, 0.2976, 0.4182", \ "0.4836, 0.4842, 0.498, 0.5274, 0.6642", \ "0.96, 0.96, 0.96, 0.9642, 1.0488"); } cell_rise(delay_template_5x5) { index_1 ("0.06, 0.16, 0.32, 0.8, 1.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.057563, 0.088297, 0.124843, 0.148937, 0.213231", \ "0.106557, 0.143139, 0.200715, 0.235009, 0.327528", \ "0.183803, 0.21972, 0.293462, 0.338716, 0.461012", \ "0.412816, 0.446995, 0.521494, 0.579617, 0.757738", \ "0.795462, 0.828949, 0.900107, 0.95544, 1.14805"); } rise_transition(delay_template_5x5) { index_1 ("0.06, 0.16, 0.32, 0.8, 1.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0624, 0.0912, 0.1284, 0.1548, 0.2304", \ "0.1302, 0.1458, 0.1926, 0.2256, 0.3228", \ "0.2442, 0.2478, 0.2862, 0.324, 0.4344", \ "0.5898, 0.5898, 0.5976, 0.6186, 0.7266", \ "1.167, 1.1676, 1.167, 1.1682, 1.2246"); } } internal_power() { related_pin : "A"; fall_power(energy_template_5x5) { index_1 ("0.06, 0.16, 0.32, 0.8, 1.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.203448, 0.143402, 0.102748, 0.314969, 1.07442", \ "0.196163, 0.16157, 0.022503, 0.199936, 0.885191", \ "0.190719, 0.167915, 0.035001, 0.106387, 0.695778", \ "0.186059, 0.173974, 0.098145, 0.006513, 0.419303", \ "0.182333, 0.177347, 0.131707, 0.07244, 0.228013"); } rise_power(energy_template_5x5) { index_1 ("0.06, 0.16, 0.32, 0.8, 1.6"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.487301, 0.594198, 0.859243, 1.08203, 1.85754", \ "0.498537, 0.557713, 0.776959, 0.972772, 1.6954", \ "0.502684, 0.54322, 0.709532, 0.875517, 1.52445", \ "0.507097, 0.525122, 0.626871, 0.741798, 1.24541", \ "0.509027, 0.517285, 0.580358, 0.657299, 1.02891"); } } } } /* -------------- * * Design : INVX8 * * -------------- */ cell (INVX8) { cell_footprint : inv; area : 160; cell_leakage_power : 0.0629795; pin(A) { direction : input; capacitance : 0.109759; rise_capacitance : 0.109546; fall_capacitance : 0.109759; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 3.33356; function : "(!A)"; timing() { related_pin : "A"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.12, 0.32, 0.64, 1.6, 3.2"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.053273, 0.06978, 0.084273, 0.089866, 0.093537", \ "0.098224, 0.127946, 0.162893, 0.178321, 0.209513", \ "0.167714, 0.1981, 0.255068, 0.282839, 0.344741", \ "0.374102, 0.403842, 0.466889, 0.516504, 0.643132", \ "0.719218, 0.747557, 0.807921, 0.854974, 1.01972"); } fall_transition(delay_template_5x5) { index_1 ("0.12, 0.32, 0.64, 1.6, 3.2"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.05309, 0.081, 0.1224, 0.1458, 0.234", \ "0.1038, 0.1266, 0.1782, 0.213, 0.3204", \ "0.2004, 0.2046, 0.2556, 0.2976, 0.4182", \ "0.4836, 0.4842, 0.498, 0.5274, 0.6642", \ "0.96, 0.96, 0.96, 0.9642, 1.0488"); } cell_rise(delay_template_5x5) { index_1 ("0.12, 0.32, 0.64, 1.6, 3.2"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.057563, 0.088297, 0.124843, 0.148937, 0.213231", \ "0.106557, 0.143139, 0.200715, 0.235009, 0.327528", \ "0.183803, 0.21972, 0.293462, 0.338716, 0.461012", \ "0.412816, 0.446995, 0.521494, 0.579617, 0.757738", \ "0.795462, 0.828949, 0.900107, 0.95544, 1.14805"); } rise_transition(delay_template_5x5) { index_1 ("0.12, 0.32, 0.64, 1.6, 3.2"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0624, 0.0912, 0.1284, 0.1548, 0.2304", \ "0.1302, 0.1458, 0.1926, 0.2256, 0.3228", \ "0.2442, 0.2478, 0.2862, 0.324, 0.4344", \ "0.5898, 0.5898, 0.5976, 0.6186, 0.7266", \ "1.167, 1.1676, 1.167, 1.1682, 1.2246"); } } internal_power() { related_pin : "A"; fall_power(energy_template_5x5) { index_1 ("0.12, 0.32, 0.64, 1.6, 3.2"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.406897, 0.286803, 0.205496, 0.629939, 2.14885", \ "0.392327, 0.32314, 0.045005, 0.399872, 1.77038", \ "0.381437, 0.33583, 0.070003, 0.212774, 1.39156", \ "0.372119, 0.347949, 0.196291, 0.013026, 0.838605", \ "0.364666, 0.354693, 0.263414, 0.14488, 0.456026"); } rise_power(energy_template_5x5) { index_1 ("0.12, 0.32, 0.64, 1.6, 3.2"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.974603, 1.1884, 1.71849, 2.16406, 3.71509", \ "0.997075, 1.11543, 1.55392, 1.94554, 3.3908", \ "1.00537, 1.08644, 1.41906, 1.75103, 3.04889", \ "1.01419, 1.05024, 1.25374, 1.4836, 2.49083", \ "1.01805, 1.03457, 1.16071, 1.3146, 2.05783"); } } } } /* -------------- * * Design : LATCH * * -------------- */ cell (LATCH) { area : 0; cell_leakage_power : 0.0663071; latch (DS0000,P0000) { data_in : "D"; enable : "CLK"; } pin(CLK) { direction : input; capacitance : 0.0323725; rise_capacitance : 0.0323724; fall_capacitance : 0.0323725; clock : true; internal_power() { rise_power(passive_energy_template_6x1) { index_1 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ("0.059791, 0.025688, 0.175257, 0.444134, 0.646377, 1.04931"); } fall_power(passive_energy_template_6x1) { index_1 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ("0.291395, 0.407135, 0.555759, 0.828325, 1.03184, 1.42916"); } } min_pulse_width_high : 0.211198; } pin(D) { direction : input; capacitance : 0.0130297; rise_capacitance : 0.0129486; fall_capacitance : 0.0130297; timing() { related_pin : "CLK"; timing_type : hold_falling; rise_constraint(hold_template_3x6) { index_1 ("0.06, 0.3, 0.6"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "-0.09375, -0.13125, -0.11875, -0.14375, -0.175, -0.2375", \ "-0.2, -0.2375, -0.225, -0.25, -0.28125, -0.25", \ "-0.2625, -0.20625, -0.2875, -0.3125, -0.25, -0.3125"); } fall_constraint(hold_template_3x6) { index_1 ("0.06, 0.3, 0.6"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "-0.09375, -0.13125, -0.2125, -0.2375, -0.3625, -0.425001", \ "-0.10625, -0.14375, -0.225, -0.25, -0.28125, -0.4375", \ "-0.075, -0.1125, -0.19375, -0.21875, -0.25, -0.40625"); } } timing() { related_pin : "CLK"; timing_type : setup_falling; rise_constraint(setup_template_3x6) { index_1 ("0.06, 0.3, 0.6"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.28125, 0.31875, 0.30625, 5.3, 5.05, 0.425", \ "0.3875, 0.33125, 0.4125, 5.5, 5.25, 0.4375", \ "0.54375, 0.58125, 0.56875, 5.75, 5.5, 0.59375"); } fall_constraint(setup_template_3x6) { index_1 ("0.06, 0.3, 0.6"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.28125, 0.31875, 0.4, 0.425, 0.55, 0.6125", \ "0.29375, 0.33125, 0.31875, 0.4375, 0.46875, 0.625", \ "0.2625, 0.3, 0.2875, 0.40625, 0.4375, 0.59375"); } } } pin(Q) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.818968; function : "DS0000"; timing() { related_pin : "CLK"; timing_sense : non_unate; timing_type : rising_edge; cell_rise(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.25464, 0.2835, 0.298283, 0.296756, 0.284761, 0.240906", \ "0.643501, 0.671746, 0.687301, 0.686064, 0.673915, 0.634005", \ "1.31317, 1.34122, 1.35641, 1.35465, 1.3425, 1.30297", \ "3.03589, 3.06385, 3.07825, 3.07582, 3.06349, 3.0233", \ "3.99267, 4.01974, 4.03514, 4.03266, 4.02008, 3.97966", \ "4.94867, 4.97632, 4.99091, 4.98907, 4.97723, 4.93703"); } rise_transition(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.1902, 0.1938, 0.198, 0.2094, 0.2154, 0.2292", \ "0.7536, 0.7536, 0.7548, 0.759, 0.762, 0.7704", \ "1.764, 1.7646, 1.7634, 1.7646, 1.7664, 1.7706", \ "4.3644, 4.3644, 4.3644, 4.3638, 4.3644, 4.3656", \ "5.8098, 5.8098, 5.8092, 5.8092, 5.8086, 5.8086", \ "7.254, 7.2546, 7.254, 7.2516, 7.254, 7.2534"); } cell_fall(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.34292, 0.353051, 0.363153, 0.373403, 0.372831, 0.368803", \ "0.702397, 0.712669, 0.72171, 0.731291, 0.732274, 0.730637", \ "1.30518, 1.31549, 1.32428, 1.33377, 1.334, 1.33334", \ "2.85453, 2.86442, 2.87348, 2.88288, 2.88302, 2.88211", \ "3.71469, 3.72488, 3.73381, 3.74351, 3.74339, 3.74315", \ "4.57506, 4.5854, 4.59471, 4.60389, 4.60393, 4.60374"); } fall_transition(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.1758, 0.1746, 0.1722, 0.177, 0.1728, 0.1764", \ "0.627, 0.6264, 0.627, 0.6264, 0.627, 0.6294", \ "1.455, 1.455, 1.4556, 1.455, 1.455, 1.455", \ "3.6, 3.6, 3.5988, 3.6, 3.6, 3.597", \ "4.7916, 4.7916, 4.7916, 4.791, 4.791, 4.7904", \ "5.982, 5.9814, 5.9832, 5.9832, 5.9826, 5.9826"); } } timing() { related_pin : "D"; timing_sense : positive_unate; cell_rise(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.300641, 0.31834, 0.340922, 0.369343, 0.382949, 0.398324", \ "0.689617, 0.706549, 0.729, 0.758451, 0.775012, 0.80033", \ "1.35926, 1.3759, 1.39862, 1.4273, 1.44395, 1.4694", \ "3.08177, 3.09825, 3.12049, 3.1489, 3.16546, 3.1899", \ "4.03799, 4.05438, 4.07784, 4.10619, 4.12184, 4.14697", \ "4.99553, 5.01232, 5.03452, 5.06177, 5.07893, 5.1039"); } rise_transition(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.192, 0.1932, 0.195, 0.2052, 0.2118, 0.2268", \ "0.7536, 0.7536, 0.7548, 0.7572, 0.7608, 0.7722", \ "1.764, 1.7646, 1.7634, 1.7652, 1.7652, 1.7694", \ "4.3644, 4.3644, 4.3644, 4.3644, 4.3644, 4.365", \ "5.8098, 5.8098, 5.8074, 5.8092, 5.8092, 5.8086", \ "7.254, 7.2516, 7.2516, 7.2546, 7.2528, 7.2534"); } cell_fall(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.339721, 0.368889, 0.413603, 0.491982, 0.543438, 0.637333", \ "0.699252, 0.727242, 0.77337, 0.854433, 0.909488, 1.01496", \ "1.30198, 1.32974, 1.37567, 1.45604, 1.51127, 1.61737", \ "2.85088, 2.87853, 2.92432, 3.00443, 3.05907, 3.16397", \ "3.71135, 3.73927, 3.7846, 3.86474, 3.91943, 4.02378", \ "4.57185, 4.59953, 4.64532, 4.72577, 4.78023, 4.88453"); } fall_transition(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.1752, 0.1776, 0.1806, 0.192, 0.1998, 0.2172", \ "0.6264, 0.627, 0.6282, 0.6312, 0.6354, 0.648", \ "1.455, 1.455, 1.455, 1.4562, 1.4574, 1.461", \ "3.6, 3.5994, 3.5994, 3.5982, 3.5982, 3.5994", \ "4.7916, 4.7916, 4.7916, 4.7892, 4.7904, 4.7898", \ "5.982, 5.9808, 5.9808, 5.9826, 5.9832, 5.9826"); } } internal_power() { related_pin : "CLK"; rise_power(energy_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.190029, 0.305976, 0.492549, 0.854761, 1.11302, 1.61867", \ "0.185583, 0.289465, 0.468692, 0.806324, 1.05352, 1.55671", \ "0.184676, 0.286908, 0.46158, 0.794558, 1.03749, 1.52959", \ "0.183352, 0.285398, 0.45868, 0.789028, 1.02919, 1.51625", \ "0.18321, 0.28508, 0.457956, 0.787972, 1.02765, 1.51377", \ "0.182915, 0.284624, 0.457563, 0.787111, 1.02673, 1.51217"); } fall_power(energy_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.287213, 0.368803, 0.519199, 0.799488, 0.996622, 1.40398", \ "0.280584, 0.361752, 0.513087, 0.789597, 0.988926, 1.39659", \ "0.279699, 0.360527, 0.512231, 0.787954, 0.988822, 1.39557", \ "0.279358, 0.360466, 0.51216, 0.787522, 0.988785, 1.39539", \ "0.279131, 0.360447, 0.512292, 0.787568, 0.98868, 1.39552", \ "0.279119, 0.360267, 0.512126, 0.787376, 0.988563, 1.39555"); } } internal_power() { related_pin : "D"; rise_power(energy_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.259848, 0.280556, 0.335552, 0.464372, 0.566057, 0.777638", \ "0.249441, 0.267287, 0.313721, 0.424518, 0.512153, 0.697198", \ "0.246869, 0.263503, 0.30924, 0.414796, 0.497609, 0.672024", \ "0.245701, 0.261794, 0.307041, 0.409745, 0.48997, 0.658745", \ "0.245338, 0.261378, 0.306469, 0.408779, 0.488668, 0.656337", \ "0.245052, 0.261023, 0.306059, 0.407953, 0.487684, 0.654768"); } fall_power(energy_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.494134, 0.514952, 0.569224, 0.699783, 0.800885, 1.01195", \ "0.486881, 0.502107, 0.552319, 0.664401, 0.753247, 0.938851", \ "0.485371, 0.499685, 0.548709, 0.657185, 0.741676, 0.918246", \ "0.484307, 0.498995, 0.54689, 0.653587, 0.736264, 0.908222", \ "0.484301, 0.498814, 0.54661, 0.652877, 0.735419, 0.906522", \ "0.484004, 0.498865, 0.546297, 0.652729, 0.734997, 0.905378"); } } } } /* --------------- * * Design : MUX2X1 * * --------------- */ cell (MUX2X1) { area : 192; cell_leakage_power : 0.0613993; pin(A) { direction : input; capacitance : 0.0265929; rise_capacitance : 0.0263548; fall_capacitance : 0.0265929; } pin(B) { direction : input; capacitance : 0.0265339; rise_capacitance : 0.0263422; fall_capacitance : 0.0265339; } pin(S) { direction : input; capacitance : 0.0295792; rise_capacitance : 0.0295792; fall_capacitance : 0.029555; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.411779; function : "(!((S A) + (!S B)))"; timing() { related_pin : "A"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.082336, 0.089775, 0.10243, 0.105517, 0.104045", \ "0.121841, 0.133302, 0.149609, 0.157831, 0.169164", \ "0.183321, 0.193781, 0.215459, 0.228459, 0.255794", \ "0.364819, 0.37103, 0.393957, 0.413017, 0.465415", \ "0.657797, 0.663229, 0.683063, 0.700999, 0.767603"); } fall_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0936, 0.108, 0.156, 0.1944, 0.3072", \ "0.1452, 0.159, 0.1992, 0.2322, 0.3564", \ "0.2268, 0.2334, 0.2646, 0.297, 0.4212", \ "0.477, 0.477, 0.4902, 0.5106, 0.6138", \ "0.8958, 0.8958, 0.8976, 0.906, 0.9678"); } cell_rise(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.106454, 0.123537, 0.153215, 0.175541, 0.244758", \ "0.157152, 0.170526, 0.20586, 0.232608, 0.31443", \ "0.229941, 0.243556, 0.281655, 0.312069, 0.40731", \ "0.450496, 0.462126, 0.498543, 0.531292, 0.640031", \ "0.81666, 0.827512, 0.859418, 0.887589, 0.998108"); } rise_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1086, 0.1254, 0.1668, 0.201, 0.3144", \ "0.1788, 0.189, 0.2244, 0.2568, 0.3714", \ "0.2874, 0.2916, 0.3168, 0.3462, 0.4554", \ "0.6174, 0.6174, 0.6264, 0.6402, 0.7218", \ "1.1688, 1.1682, 1.1682, 1.1736, 1.2138"); } } timing() { related_pin : "B"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.093802, 0.098897, 0.105613, 0.108217, 0.105219", \ "0.131752, 0.139637, 0.153538, 0.160935, 0.17077", \ "0.192565, 0.199873, 0.219392, 0.231947, 0.257536", \ "0.368648, 0.376833, 0.398401, 0.416656, 0.46774", \ "0.661744, 0.668804, 0.687294, 0.705066, 0.77052"); } fall_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0918, 0.1092, 0.1506, 0.1896, 0.303", \ "0.144, 0.1566, 0.1968, 0.2298, 0.354", \ "0.2262, 0.234, 0.264, 0.297, 0.42", \ "0.4788, 0.4782, 0.492, 0.5124, 0.6144", \ "0.8982, 0.8982, 0.9006, 0.909, 0.9702"); } cell_rise(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.096297, 0.115488, 0.149039, 0.173485, 0.243713", \ "0.146697, 0.164524, 0.202557, 0.229598, 0.312694", \ "0.219348, 0.23835, 0.277782, 0.309044, 0.40514", \ "0.44378, 0.456353, 0.494291, 0.527464, 0.637409", \ "0.810029, 0.823437, 0.854837, 0.883393, 0.994754"); } rise_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1104, 0.1296, 0.174, 0.204, 0.3162", \ "0.1794, 0.1884, 0.228, 0.258, 0.3726", \ "0.2868, 0.2898, 0.3168, 0.3462, 0.4554", \ "0.615, 0.6156, 0.624, 0.6378, 0.7194", \ "1.1658, 1.1658, 1.1658, 1.1706, 1.2108"); } } timing() { related_pin : "S"; timing_sense : non_unate; cell_rise(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.152242, 0.167035, 0.202409, 0.215544, 0.241432", \ "0.197231, 0.215666, 0.248914, 0.264347, 0.291801", \ "0.266861, 0.287321, 0.317916, 0.335817, 0.366422", \ "0.481234, 0.505295, 0.5338, 0.546357, 0.582994", \ "0.844084, 0.868446, 0.896951, 0.909845, 0.939374"); } rise_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1098, 0.1104, 0.108, 0.1116, 0.1146", \ "0.1806, 0.1806, 0.1686, 0.174, 0.1806", \ "0.2874, 0.2886, 0.282, 0.276, 0.2832", \ "0.6168, 0.6174, 0.6138, 0.6102, 0.6066", \ "1.1682, 1.1688, 1.1682, 1.1658, 1.1592"); } cell_fall(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.159088, 0.192223, 0.252428, 0.289023, 0.384499", \ "0.19869, 0.228037, 0.291557, 0.330549, 0.428269", \ "0.25647, 0.292463, 0.348003, 0.389077, 0.491427", \ "0.428045, 0.463565, 0.522072, 0.557314, 0.666379", \ "0.717641, 0.753579, 0.810918, 0.846254, 0.948856"); } fall_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1002, 0.1044, 0.0954, 0.0936, 0.1014", \ "0.1524, 0.1542, 0.1428, 0.1428, 0.1458", \ "0.2298, 0.2322, 0.2274, 0.222, 0.2286", \ "0.4788, 0.4788, 0.4776, 0.4734, 0.4698", \ "0.8982, 0.8982, 0.8988, 0.897, 0.8898"); } } internal_power() { related_pin : "A"; fall_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.102317, 0.080679, 0.011467, 0.099937, 0.426621", \ "0.101225, 0.09026, 0.011397, 0.068034, 0.374193", \ "0.099971, 0.093586, 0.030819, 0.035158, 0.311526", \ "0.096747, 0.094935, 0.057755, 0.011457, 0.200415", \ "0.095844, 0.09724, 0.073778, 0.042294, 0.113322"); } rise_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.484138, 0.50293, 0.606859, 0.701526, 1.04066", \ "0.487225, 0.498023, 0.584734, 0.670559, 0.994423", \ "0.489114, 0.49524, 0.564729, 0.639285, 0.936755", \ "0.491075, 0.492445, 0.537952, 0.591309, 0.82816", \ "0.492158, 0.491412, 0.520662, 0.558249, 0.737838"); } } internal_power() { related_pin : "B"; fall_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.005158, 0.008434, 0.101793, 0.190899, 0.51801", \ "0.003299, 0.004385, 0.081909, 0.160558, 0.466463", \ "0.002279, 0.002613, 0.063212, 0.128765, 0.404632", \ "0.000822, 0.000485, 0.037414, 0.083377, 0.294884", \ "0.000188, 0.001586, 0.0218, 0.053148, 0.208492"); } rise_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.385984, 0.408189, 0.513619, 0.60983, 0.948413", \ "0.388736, 0.404395, 0.491864, 0.57777, 0.901913", \ "0.390578, 0.401354, 0.470255, 0.545481, 0.842904", \ "0.391557, 0.39692, 0.442683, 0.496422, 0.733841", \ "0.392442, 0.394668, 0.425226, 0.462881, 0.64279"); } } internal_power() { related_pin : "S"; rise_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.248758, 0.251756, 0.318847, 0.369557, 0.579522", \ "0.238293, 0.248767, 0.313665, 0.364025, 0.566288", \ "0.229945, 0.242006, 0.307564, 0.35791, 0.555719", \ "0.215231, 0.227409, 0.294036, 0.348422, 0.544486", \ "0.206745, 0.219959, 0.286035, 0.340133, 0.533789"); } fall_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.447295, 0.465965, 0.531806, 0.588429, 0.797614", \ "0.435318, 0.445604, 0.525208, 0.58552, 0.787916", \ "0.421378, 0.442286, 0.516509, 0.574096, 0.776779", \ "0.405478, 0.425694, 0.498665, 0.557992, 0.761159", \ "0.395778, 0.414763, 0.486195, 0.544194, 0.745836"); } } } } /* ---------------- * * Design : NAND2X1 * * ---------------- */ cell (NAND2X1) { area : 96; cell_leakage_power : 0.0261623; pin(A) { direction : input; capacitance : 0.0177118; rise_capacitance : 0.0177118; fall_capacitance : 0.0177083; } pin(B) { direction : input; capacitance : 0.0180112; rise_capacitance : 0.0179539; fall_capacitance : 0.0180112; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.403083; function : "(!(A B))"; timing() { related_pin : "A"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.050618, 0.05299, 0.037559, 0.021262, -0.044862", \ "0.090341, 0.097952, 0.096887, 0.089145, 0.044217", \ "0.149272, 0.15804, 0.16938, 0.171209, 0.152043", \ "0.323475, 0.333667, 0.353625, 0.366459, 0.389536", \ "0.619139, 0.625153, 0.643098, 0.658467, 0.708391"); } fall_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.057532, 0.0888, 0.1224, 0.1554, 0.2406", \ "0.1026, 0.1212, 0.1632, 0.1986, 0.2976", \ "0.1866, 0.195, 0.2328, 0.2646, 0.3756", \ "0.4362, 0.4374, 0.4536, 0.477, 0.579", \ "0.8568, 0.8568, 0.8592, 0.8688, 0.9354"); } cell_rise(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.08412, 0.122658, 0.187644, 0.23227, 0.368234", \ "0.133223, 0.173084, 0.249212, 0.299945, 0.453624", \ "0.210356, 0.24844, 0.332414, 0.390414, 0.561828", \ "0.444258, 0.479574, 0.557949, 0.620954, 0.829115", \ "0.832864, 0.867038, 0.941334, 1.00001, 1.20776"); } rise_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0876, 0.105, 0.1416, 0.1686, 0.2448", \ "0.156, 0.165, 0.207, 0.2358, 0.3252", \ "0.273, 0.2742, 0.3048, 0.3348, 0.4338", \ "0.6228, 0.6228, 0.6276, 0.6438, 0.732", \ "1.2078, 1.2078, 1.2078, 1.2078, 1.2522"); } } timing() { related_pin : "B"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.050994, 0.0599, 0.061444, 0.055413, 0.021324", \ "0.089805, 0.112829, 0.130014, 0.134585, 0.12642", \ "0.147571, 0.174805, 0.214511, 0.230068, 0.252106", \ "0.322786, 0.349291, 0.404088, 0.444179, 0.525043", \ "0.616501, 0.640746, 0.693265, 0.734586, 0.871398"); } fall_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.055756, 0.0834, 0.1218, 0.1494, 0.2394", \ "0.1026, 0.1296, 0.1752, 0.2088, 0.3162", \ "0.1848, 0.1968, 0.2496, 0.2862, 0.4074", \ "0.4374, 0.4362, 0.4596, 0.4938, 0.6306", \ "0.8562, 0.8568, 0.858, 0.8706, 0.9756"); } cell_rise(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0686, 0.102791, 0.153802, 0.187324, 0.287725", \ "0.119023, 0.156792, 0.224118, 0.267771, 0.393386", \ "0.196982, 0.234136, 0.313565, 0.366261, 0.517613", \ "0.432759, 0.466376, 0.542876, 0.603709, 0.801824", \ "0.821787, 0.854876, 0.927876, 0.985407, 1.1885"); } rise_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0624, 0.093, 0.1284, 0.1476, 0.2256", \ "0.135, 0.1494, 0.1932, 0.2196, 0.3126", \ "0.2514, 0.255, 0.2874, 0.3198, 0.4218", \ "0.6024, 0.6024, 0.6066, 0.6246, 0.7194", \ "1.1868, 1.1862, 1.1868, 1.1874, 1.2336"); } } internal_power() { related_pin : "A"; fall_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.05243, 0.035902, 0.041885, 0.108596, 0.347428", \ "0.049415, 0.038277, 0.020757, 0.078056, 0.29691", \ "0.047477, 0.040295, 0.004607, 0.05133, 0.243265", \ "0.045429, 0.041369, 0.014147, 0.017436, 0.160098", \ "0.0449, 0.042425, 0.025204, 0.003547, 0.100727"); } rise_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.222098, 0.250472, 0.331364, 0.40047, 0.645498", \ "0.221978, 0.242516, 0.311104, 0.374246, 0.606873", \ "0.223326, 0.236671, 0.291136, 0.346414, 0.560211", \ "0.225693, 0.230999, 0.26554, 0.30424, 0.474407", \ "0.226379, 0.228756, 0.249957, 0.276102, 0.402794"); } } internal_power() { related_pin : "B"; fall_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.048835, 0.032491, 0.039931, 0.10133, 0.320198", \ "0.047414, 0.03488, 0.018367, 0.070529, 0.270044", \ "0.04617, 0.039208, 0.002135, 0.044184, 0.217706", \ "0.044908, 0.04099, 0.01672, 0.011339, 0.138869", \ "0.044852, 0.04235, 0.027389, 0.008647, 0.083186"); } rise_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.156889, 0.181307, 0.258189, 0.32237, 0.545524", \ "0.162309, 0.178133, 0.238944, 0.296493, 0.506332", \ "0.166899, 0.175783, 0.22275, 0.271915, 0.463457", \ "0.173637, 0.175479, 0.203495, 0.237439, 0.389238", \ "0.176006, 0.176438, 0.193341, 0.215966, 0.329132"); } } } } /* ---------------- * * Design : NAND3X1 * * ---------------- */ cell (NAND3X1) { area : 144; cell_leakage_power : 0.0371207; pin(A) { direction : input; capacitance : 0.0222511; rise_capacitance : 0.0222511; fall_capacitance : 0.0221072; } pin(B) { direction : input; capacitance : 0.022204; rise_capacitance : 0.022204; fall_capacitance : 0.0221403; } pin(C) { direction : input; capacitance : 0.0226301; rise_capacitance : 0.0225324; fall_capacitance : 0.0226301; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.386439; function : "(!((A B) C))"; timing() { related_pin : "A"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.063065, 0.058467, 0.028759, 0.002227, -0.096807", \ "0.100322, 0.097286, 0.078741, 0.059139, -0.023316", \ "0.156628, 0.154548, 0.1444, 0.131618, 0.069258", \ "0.321295, 0.320508, 0.317084, 0.312099, 0.282799", \ "0.598619, 0.596485, 0.590934, 0.589206, 0.579448"); } fall_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0666, 0.09, 0.129, 0.1572, 0.2562", \ "0.114, 0.1296, 0.1644, 0.1974, 0.3", \ "0.1914, 0.2004, 0.231, 0.2598, 0.3666", \ "0.432, 0.4338, 0.4488, 0.4692, 0.5586", \ "0.8352, 0.8346, 0.8388, 0.8484, 0.9102"); } cell_rise(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.124147, 0.164561, 0.246678, 0.304128, 0.479718", \ "0.175141, 0.212995, 0.300527, 0.361018, 0.547992", \ "0.253843, 0.290844, 0.377535, 0.443662, 0.642004", \ "0.488942, 0.523451, 0.603166, 0.667691, 0.890972", \ "0.878173, 0.911994, 0.986901, 1.04676, 1.26092"); } rise_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1314, 0.1434, 0.18, 0.2058, 0.2802", \ "0.204, 0.2094, 0.2418, 0.27, 0.354", \ "0.3204, 0.3204, 0.3414, 0.3678, 0.4602", \ "0.6708, 0.6708, 0.6732, 0.6852, 0.762", \ "1.2558, 1.2558, 1.2558, 1.2558, 1.2918"); } } timing() { related_pin : "B"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.060178, 0.060331, 0.045491, 0.029091, -0.038005", \ "0.097654, 0.10274, 0.102664, 0.09515, 0.047732", \ "0.153403, 0.162733, 0.174782, 0.176451, 0.15465", \ "0.318194, 0.329239, 0.352701, 0.366113, 0.390753", \ "0.594217, 0.604663, 0.626442, 0.644563, 0.699437"); } fall_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.066, 0.0924, 0.1356, 0.1704, 0.2646", \ "0.1146, 0.1362, 0.1776, 0.213, 0.3192", \ "0.1932, 0.204, 0.2424, 0.2754, 0.3906", \ "0.432, 0.4332, 0.4524, 0.4794, 0.5874", \ "0.8346, 0.8346, 0.8388, 0.8508, 0.9252"); } cell_rise(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.103758, 0.142637, 0.214764, 0.263466, 0.412065", \ "0.154097, 0.192381, 0.27275, 0.326708, 0.491256", \ "0.233115, 0.269494, 0.353233, 0.414663, 0.5956", \ "0.468607, 0.502046, 0.580242, 0.643115, 0.857417", \ "0.857634, 0.890945, 0.964489, 1.02344, 1.23363"); } rise_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0984, 0.1134, 0.156, 0.1776, 0.2496", \ "0.1716, 0.1788, 0.2154, 0.2436, 0.3288", \ "0.288, 0.2898, 0.3138, 0.3432, 0.4374", \ "0.639, 0.639, 0.6414, 0.6558, 0.738", \ "1.224, 1.2234, 1.224, 1.224, 1.2624"); } } timing() { related_pin : "C"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.052574, 0.057961, 0.052516, 0.041428, -0.005342", \ "0.08508, 0.105469, 0.118295, 0.117778, 0.093831", \ "0.141905, 0.16599, 0.197503, 0.209114, 0.213802", \ "0.30662, 0.331356, 0.381447, 0.414428, 0.476457", \ "0.584826, 0.606219, 0.654025, 0.691932, 0.809832"); } fall_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0648, 0.093, 0.1284, 0.153, 0.2466", \ "0.1134, 0.1362, 0.1812, 0.2118, 0.3198", \ "0.1926, 0.2022, 0.2544, 0.2874, 0.4074", \ "0.4326, 0.4326, 0.459, 0.4944, 0.6228", \ "0.8346, 0.8346, 0.8364, 0.8526, 0.9606"); } cell_rise(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.076463, 0.113801, 0.170603, 0.20997, 0.324975", \ "0.128923, 0.166587, 0.237823, 0.284793, 0.42485", \ "0.209418, 0.244544, 0.32564, 0.381097, 0.544265", \ "0.446454, 0.479009, 0.554949, 0.616878, 0.822055", \ "0.836244, 0.868808, 0.941201, 0.998972, 1.20528"); } rise_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0684, 0.0876, 0.126, 0.1524, 0.2214", \ "0.1416, 0.1476, 0.1914, 0.2196, 0.3042", \ "0.2568, 0.258, 0.2886, 0.3186, 0.4158", \ "0.6072, 0.6072, 0.6102, 0.6264, 0.7152", \ "1.1922, 1.1922, 1.1922, 1.1916, 1.2342"); } } internal_power() { related_pin : "A"; fall_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.055521, 0.040775, 0.03436, 0.106269, 0.37116", \ "0.051123, 0.04417, 0.018152, 0.079727, 0.323968", \ "0.048514, 0.043811, 0.003845, 0.055658, 0.272607", \ "0.046277, 0.042892, 0.013231, 0.02298, 0.188781", \ "0.04439, 0.044045, 0.023706, 0.001739, 0.125735"); } rise_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.39656, 0.419399, 0.502791, 0.578856, 0.85004", \ "0.399282, 0.415937, 0.486771, 0.55634, 0.81442", \ "0.401056, 0.413041, 0.469933, 0.53044, 0.769979", \ "0.403276, 0.408759, 0.444555, 0.487864, 0.681315", \ "0.404304, 0.405619, 0.428297, 0.457889, 0.60292"); } } internal_power() { related_pin : "B"; fall_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.053459, 0.038189, 0.038344, 0.105744, 0.350996", \ "0.049885, 0.041746, 0.018987, 0.076689, 0.301486", \ "0.047474, 0.04189, 0.003546, 0.051007, 0.248281", \ "0.045998, 0.041779, 0.014474, 0.017682, 0.164775", \ "0.045131, 0.042536, 0.025206, 0.003192, 0.104499"); } rise_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.300109, 0.317913, 0.400251, 0.469746, 0.721102", \ "0.30405, 0.317618, 0.383775, 0.448337, 0.687082", \ "0.307957, 0.315832, 0.368245, 0.424418, 0.645347", \ "0.313037, 0.31588, 0.348129, 0.387408, 0.565113", \ "0.317472, 0.317023, 0.336234, 0.36274, 0.496095"); } } internal_power() { related_pin : "C"; fall_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.050643, 0.03145, 0.046323, 0.112211, 0.346305", \ "0.046794, 0.034369, 0.024412, 0.08096, 0.295526", \ "0.045674, 0.038069, 0.007659, 0.05344, 0.241358", \ "0.044505, 0.041187, 0.012637, 0.018344, 0.15786", \ "0.044531, 0.042453, 0.024445, 0.003487, 0.097954"); } rise_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.196567, 0.219393, 0.295041, 0.363049, 0.60089", \ "0.201831, 0.216187, 0.278552, 0.339013, 0.564111", \ "0.210789, 0.216731, 0.264087, 0.31658, 0.52259", \ "0.222925, 0.221746, 0.248983, 0.284661, 0.448838", \ "0.227537, 0.226371, 0.242053, 0.265531, 0.388051"); } } } } /* --------------- * * Design : NOR2X1 * * --------------- */ cell (NOR2X1) { area : 96; cell_leakage_power : 0.0252328; pin(A) { direction : input; capacitance : 0.0222369; rise_capacitance : 0.0219827; fall_capacitance : 0.0222369; } pin(B) { direction : input; capacitance : 0.0227534; rise_capacitance : 0.0227534; fall_capacitance : 0.0227451; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.427702; function : "(!(A+B))"; timing() { related_pin : "A"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.094223, 0.122979, 0.16574, 0.193293, 0.267001", \ "0.138995, 0.168762, 0.224888, 0.258293, 0.348349", \ "0.207887, 0.238263, 0.304627, 0.345288, 0.454567", \ "0.413428, 0.441918, 0.506489, 0.558761, 0.714238", \ "0.754586, 0.782418, 0.843585, 0.892655, 1.06707"); } fall_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0846, 0.0984, 0.1524, 0.1812, 0.2772", \ "0.1416, 0.1518, 0.201, 0.2352, 0.3486", \ "0.2352, 0.2382, 0.2766, 0.3168, 0.4368", \ "0.516, 0.5172, 0.5256, 0.5502, 0.6726", \ "0.987, 0.9876, 0.9876, 0.99, 1.0632"); } cell_rise(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.07466, 0.08727, 0.096671, 0.101886, 0.105469", \ "0.122371, 0.137942, 0.159104, 0.17134, 0.195559", \ "0.194672, 0.211483, 0.241865, 0.261172, 0.307247", \ "0.416818, 0.430715, 0.462887, 0.490222, 0.567975", \ "0.782968, 0.796016, 0.825108, 0.849861, 0.942236"); } rise_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0834, 0.1074, 0.1512, 0.183, 0.276", \ "0.147, 0.162, 0.2016, 0.234, 0.3402", \ "0.2544, 0.2598, 0.291, 0.3216, 0.4308", \ "0.5838, 0.585, 0.5952, 0.6108, 0.7002", \ "1.1352, 1.1352, 1.1352, 1.1412, 1.1874"); } } timing() { related_pin : "B"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.069698, 0.09223, 0.114912, 0.125897, 0.154857", \ "0.115517, 0.144789, 0.185713, 0.209021, 0.261995", \ "0.18518, 0.214744, 0.274435, 0.307898, 0.389318", \ "0.392571, 0.420854, 0.483288, 0.533959, 0.673864", \ "0.734171, 0.762343, 0.822754, 0.870133, 1.04028"); } fall_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.05093, 0.0738, 0.1128, 0.1422, 0.2226", \ "0.1104, 0.1206, 0.1704, 0.2022, 0.3072", \ "0.2004, 0.2058, 0.2466, 0.2862, 0.402", \ "0.4824, 0.4824, 0.4914, 0.5178, 0.6468", \ "0.9528, 0.9528, 0.9522, 0.9552, 1.0326"); } cell_rise(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.06257, 0.085847, 0.117312, 0.133773, 0.178664", \ "0.112082, 0.142406, 0.188502, 0.216886, 0.28721", \ "0.184816, 0.216357, 0.27928, 0.316598, 0.415703", \ "0.404717, 0.434101, 0.499511, 0.551588, 0.702157", \ "0.771036, 0.799061, 0.861229, 0.910339, 1.08346"); } rise_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0816, 0.1098, 0.141, 0.1668, 0.2466", \ "0.1434, 0.1632, 0.21, 0.2382, 0.3336", \ "0.2544, 0.2598, 0.3012, 0.3378, 0.4428", \ "0.5844, 0.585, 0.594, 0.618, 0.7302", \ "1.1352, 1.1352, 1.1352, 1.1376, 1.203"); } } internal_power() { related_pin : "A"; fall_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.100086, 0.08835, 0.021973, 0.042922, 0.282125", \ "0.099939, 0.094558, 0.038313, 0.017965, 0.239918", \ "0.099186, 0.09476, 0.053908, 0.007207, 0.190259", \ "0.097375, 0.097924, 0.073708, 0.042464, 0.105685", \ "0.096817, 0.099208, 0.084503, 0.064405, 0.04125"); } rise_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.361304, 0.375347, 0.456966, 0.526368, 0.774725", \ "0.363138, 0.373451, 0.439158, 0.500149, 0.731911", \ "0.365323, 0.372084, 0.42303, 0.475274, 0.684444", \ "0.366137, 0.36892, 0.403071, 0.440931, 0.605128", \ "0.366777, 0.36826, 0.390885, 0.417747, 0.542588"); } } internal_power() { related_pin : "B"; fall_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.100184, 0.08453, 0.020046, 0.040552, 0.258492", \ "0.08927, 0.082951, 0.035156, 0.015414, 0.215319", \ "0.08175, 0.079365, 0.04614, 0.005274, 0.169368", \ "0.074412, 0.073407, 0.055576, 0.029446, 0.098956", \ "0.071195, 0.069708, 0.059057, 0.042539, 0.04887"); } rise_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.222695, 0.247471, 0.326606, 0.392012, 0.61604", \ "0.224907, 0.242664, 0.30644, 0.363794, 0.573359", \ "0.227185, 0.239084, 0.288028, 0.33667, 0.526271", \ "0.22894, 0.234764, 0.26538, 0.299626, 0.448438", \ "0.229797, 0.232968, 0.252228, 0.275546, 0.386926"); } } } } /* --------------- * * Design : NOR3X1 * * --------------- */ cell (NOR3X1) { area : 256; cell_leakage_power : 0.0625284; pin(A) { direction : input; capacitance : 0.0310602; rise_capacitance : 0.0305923; fall_capacitance : 0.0310602; } pin(B) { direction : input; capacitance : 0.0311174; rise_capacitance : 0.0306756; fall_capacitance : 0.0311174; } pin(C) { direction : input; capacitance : 0.0317844; rise_capacitance : 0.0317844; fall_capacitance : 0.0317601; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.419287; function : "(!((A+B)+C))"; timing() { related_pin : "A"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.152754, 0.180457, 0.247088, 0.287541, 0.407435", \ "0.200512, 0.228206, 0.298269, 0.343387, 0.471277", \ "0.27368, 0.300685, 0.369742, 0.421872, 0.563179", \ "0.483973, 0.510391, 0.574414, 0.626723, 0.80235", \ "0.827612, 0.854153, 0.914819, 0.963549, 1.1408"); } fall_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1482, 0.1518, 0.1998, 0.2346, 0.3426", \ "0.2064, 0.2106, 0.246, 0.2862, 0.4026", \ "0.3042, 0.3024, 0.3294, 0.3642, 0.4872", \ "0.5868, 0.5874, 0.591, 0.6096, 0.7188", \ "1.059, 1.059, 1.059, 1.0602, 1.1202"); } cell_rise(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.111162, 0.11659, 0.115847, 0.110573, 0.078725", \ "0.157555, 0.162776, 0.171299, 0.171274, 0.155812", \ "0.229493, 0.239709, 0.24888, 0.253926, 0.257246", \ "0.447117, 0.455693, 0.468917, 0.479141, 0.507478", \ "0.808867, 0.817906, 0.828051, 0.836125, 0.873727"); } rise_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.114, 0.1338, 0.1668, 0.201, 0.3204", \ "0.1776, 0.1878, 0.2196, 0.2508, 0.3684", \ "0.2832, 0.2874, 0.3132, 0.3384, 0.45", \ "0.6084, 0.609, 0.618, 0.6318, 0.714", \ "1.152, 1.152, 1.1526, 1.1586, 1.2012"); } } timing() { related_pin : "B"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.128504, 0.156723, 0.208181, 0.238346, 0.323305", \ "0.174353, 0.202681, 0.262965, 0.299368, 0.399343", \ "0.24442, 0.272432, 0.338528, 0.383135, 0.501193", \ "0.451667, 0.478959, 0.54169, 0.592924, 0.755369", \ "0.793543, 0.820899, 0.880872, 0.929276, 1.10302"); } fall_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.105, 0.1098, 0.1584, 0.186, 0.2826", \ "0.1596, 0.1662, 0.2064, 0.2412, 0.3498", \ "0.2556, 0.2544, 0.2862, 0.3216, 0.4398", \ "0.5376, 0.5376, 0.543, 0.5634, 0.6774", \ "1.008, 1.0086, 1.0086, 1.0098, 1.0746"); } cell_rise(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.099134, 0.110661, 0.120065, 0.127915, 0.141346", \ "0.144803, 0.160931, 0.182812, 0.196907, 0.228736", \ "0.219572, 0.236418, 0.2653, 0.285933, 0.34025", \ "0.436457, 0.45205, 0.488798, 0.518428, 0.60083", \ "0.798336, 0.815172, 0.847517, 0.87517, 0.976568"); } rise_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1146, 0.1416, 0.183, 0.216, 0.3186", \ "0.1782, 0.1926, 0.2376, 0.2652, 0.3774", \ "0.2826, 0.2904, 0.3246, 0.3582, 0.4644", \ "0.6084, 0.609, 0.6222, 0.6396, 0.7344", \ "1.152, 1.152, 1.1526, 1.1598, 1.2084"); } } timing() { related_pin : "C"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.08301, 0.109772, 0.137035, 0.154933, 0.193345", \ "0.129516, 0.159882, 0.206652, 0.231278, 0.296385", \ "0.202683, 0.23089, 0.292905, 0.328253, 0.419645", \ "0.412006, 0.440002, 0.501383, 0.551917, 0.69869", \ "0.754706, 0.783562, 0.842947, 0.890235, 1.0612"); } fall_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.059164, 0.0714, 0.1116, 0.1362, 0.2124", \ "0.1134, 0.1206, 0.1674, 0.1974, 0.294", \ "0.2052, 0.2058, 0.243, 0.2808, 0.3906", \ "0.486, 0.4866, 0.4938, 0.5166, 0.6372", \ "0.957, 0.957, 0.957, 0.9588, 1.0284"); } cell_rise(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.06395, 0.086552, 0.113071, 0.126885, 0.164031", \ "0.111545, 0.140241, 0.181419, 0.206979, 0.267804", \ "0.185132, 0.212086, 0.270257, 0.303683, 0.392876", \ "0.401038, 0.428874, 0.48948, 0.5381, 0.674042", \ "0.764447, 0.790188, 0.846857, 0.892475, 1.05398"); } rise_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1032, 0.1386, 0.162, 0.186, 0.2634", \ "0.1716, 0.186, 0.2364, 0.2586, 0.3516", \ "0.2808, 0.2862, 0.3258, 0.3636, 0.4578", \ "0.609, 0.6078, 0.618, 0.6414, 0.753", \ "1.152, 1.152, 1.152, 1.1544, 1.2204"); } } internal_power() { related_pin : "A"; fall_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.131065, 0.131611, 0.073869, 0.011834, 0.237163", \ "0.129315, 0.132488, 0.086616, 0.031049, 0.201598", \ "0.128831, 0.134652, 0.098841, 0.051978, 0.157648", \ "0.128206, 0.136966, 0.115238, 0.083835, 0.076353", \ "0.127994, 0.138045, 0.125952, 0.105383, 0.010031"); } rise_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.735777, 0.731908, 0.804381, 0.870758, 1.12931", \ "0.735821, 0.732413, 0.792006, 0.850206, 1.09287", \ "0.739806, 0.736356, 0.781242, 0.830825, 1.05035", \ "0.741399, 0.735498, 0.767423, 0.804083, 0.978528", \ "0.741922, 0.736246, 0.759107, 0.785704, 0.920807"); } } internal_power() { related_pin : "B"; fall_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.128196, 0.127751, 0.072673, 0.013607, 0.218591", \ "0.123813, 0.124764, 0.082707, 0.030787, 0.185128", \ "0.11947, 0.122491, 0.091122, 0.048125, 0.144488", \ "0.115159, 0.118347, 0.100359, 0.072257, 0.073501", \ "0.113173, 0.115457, 0.104917, 0.086698, 0.017981"); } rise_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.530429, 0.537729, 0.612321, 0.678689, 0.926266", \ "0.534233, 0.542837, 0.59752, 0.655483, 0.8855", \ "0.537091, 0.540931, 0.58478, 0.63404, 0.83976", \ "0.539785, 0.539628, 0.568191, 0.603192, 0.763737", \ "0.540302, 0.538374, 0.557991, 0.582507, 0.703668"); } } internal_power() { related_pin : "C"; fall_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.153385, 0.13477, 0.072153, 0.013196, 0.21246", \ "0.135576, 0.129487, 0.08411, 0.03299, 0.174229", \ "0.121696, 0.120814, 0.089029, 0.048567, 0.132365", \ "0.105399, 0.105208, 0.089866, 0.064886, 0.068317", \ "0.098687, 0.095768, 0.087049, 0.071252, 0.022819"); } rise_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.321292, 0.345217, 0.432191, 0.50093, 0.736904", \ "0.322384, 0.342056, 0.412164, 0.472551, 0.694948", \ "0.328056, 0.337857, 0.393229, 0.445136, 0.646544", \ "0.331253, 0.335912, 0.369846, 0.406444, 0.565268", \ "0.331784, 0.334815, 0.35633, 0.38128, 0.50085"); } } } } /* ---------------- * * Design : OAI21X1 * * ---------------- */ cell (OAI21X1) { area : 92; cell_leakage_power : 0.0336415; pin(A) { direction : input; capacitance : 0.0265312; rise_capacitance : 0.0263596; fall_capacitance : 0.0265312; } pin(B) { direction : input; capacitance : 0.0270702; rise_capacitance : 0.0270702; fall_capacitance : 0.0270424; } pin(C) { direction : input; capacitance : 0.0180101; rise_capacitance : 0.017967; fall_capacitance : 0.0180101; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.405483; function : "(!((A+B) C))"; timing() { related_pin : "A"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.086997, 0.09469, 0.102524, 0.104145, 0.101809", \ "0.124165, 0.134819, 0.149625, 0.157113, 0.166509", \ "0.18421, 0.194317, 0.21523, 0.22805, 0.253975", \ "0.364258, 0.370313, 0.3933, 0.411967, 0.463753", \ "0.65629, 0.661956, 0.681604, 0.699621, 0.765878"); } fall_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0864, 0.1038, 0.1506, 0.186, 0.2982", \ "0.1368, 0.1488, 0.189, 0.2262, 0.3468", \ "0.219, 0.225, 0.258, 0.2898, 0.4158", \ "0.4704, 0.4704, 0.4842, 0.5046, 0.6066", \ "0.8898, 0.8898, 0.8922, 0.9006, 0.9624"); } cell_rise(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.098103, 0.117874, 0.148161, 0.172002, 0.24093", \ "0.144665, 0.164218, 0.201587, 0.228311, 0.310109", \ "0.218633, 0.237403, 0.276575, 0.307662, 0.403045", \ "0.442142, 0.455856, 0.492552, 0.52567, 0.63554", \ "0.8081, 0.821415, 0.852807, 0.8814, 0.992737"); } rise_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1032, 0.1236, 0.168, 0.1998, 0.3096", \ "0.1698, 0.1824, 0.2208, 0.2532, 0.3672", \ "0.2802, 0.2826, 0.3102, 0.3408, 0.4506", \ "0.6102, 0.6102, 0.618, 0.633, 0.7152", \ "1.161, 1.1604, 1.161, 1.1658, 1.206"); } } timing() { related_pin : "B"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.06432, 0.070213, 0.062711, 0.052966, 0.00977", \ "0.105016, 0.114343, 0.119459, 0.117466, 0.093522", \ "0.166101, 0.175949, 0.190355, 0.196655, 0.196028", \ "0.34585, 0.352109, 0.373467, 0.389253, 0.425856", \ "0.638719, 0.644948, 0.663437, 0.68045, 0.73914"); } fall_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.054971, 0.0792, 0.1182, 0.1476, 0.2352", \ "0.1074, 0.123, 0.1602, 0.1908, 0.297", \ "0.1878, 0.1962, 0.2304, 0.2592, 0.3726", \ "0.4392, 0.4392, 0.4548, 0.4746, 0.5754", \ "0.8598, 0.8592, 0.8616, 0.8706, 0.933"); } cell_rise(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.090256, 0.121527, 0.176544, 0.215503, 0.329655", \ "0.136801, 0.168698, 0.234643, 0.278287, 0.410338", \ "0.209246, 0.242068, 0.315199, 0.364289, 0.513075", \ "0.430049, 0.459284, 0.52881, 0.58535, 0.765595", \ "0.796105, 0.824558, 0.888846, 0.940851, 1.12828"); } rise_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1014, 0.1248, 0.162, 0.1866, 0.2694", \ "0.171, 0.183, 0.2268, 0.2502, 0.3414", \ "0.2802, 0.2826, 0.3168, 0.348, 0.4446", \ "0.6102, 0.6102, 0.6174, 0.636, 0.7308", \ "1.161, 1.1604, 1.161, 1.1622, 1.2168"); } } timing() { related_pin : "C"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.062445, 0.07627, 0.080305, 0.076248, 0.045807", \ "0.0965, 0.121046, 0.141542, 0.14639, 0.136477", \ "0.149691, 0.176355, 0.216122, 0.231754, 0.249743", \ "0.304756, 0.332395, 0.388844, 0.426989, 0.502251", \ "0.565487, 0.591129, 0.645979, 0.68865, 0.822292"); } fall_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.065559, 0.0921, 0.1341, 0.1623, 0.2556", \ "0.1107, 0.1308, 0.1812, 0.2142, 0.324", \ "0.1803, 0.1929, 0.2454, 0.282, 0.405", \ "0.4035, 0.4041, 0.4305, 0.468, 0.6063", \ "0.7746, 0.7749, 0.7779, 0.7944, 0.9102"); } cell_rise(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.075551, 0.111276, 0.168153, 0.20587, 0.31593", \ "0.12605, 0.164605, 0.234824, 0.280912, 0.413407", \ "0.205143, 0.242753, 0.32323, 0.377329, 0.532734", \ "0.441966, 0.475828, 0.553012, 0.613798, 0.813628", \ "0.831556, 0.864818, 0.938309, 0.995977, 1.19903"); } rise_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0939, 0.117, 0.1605, 0.1887, 0.2727", \ "0.1644, 0.177, 0.2211, 0.2508, 0.3453", \ "0.2805, 0.2844, 0.3162, 0.3474, 0.4503", \ "0.6318, 0.6318, 0.6363, 0.6534, 0.7452", \ "1.2162, 1.2162, 1.2162, 1.2168, 1.2618"); } } internal_power() { related_pin : "A"; fall_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.103691, 0.088921, 0.00587, 0.094878, 0.423345", \ "0.101372, 0.093043, 0.014434, 0.063568, 0.370708", \ "0.100096, 0.095484, 0.034286, 0.031396, 0.308173", \ "0.096567, 0.09617, 0.059529, 0.014047, 0.197569", \ "0.095796, 0.098049, 0.075069, 0.044124, 0.110987"); } rise_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.465664, 0.487167, 0.590949, 0.687686, 1.02707", \ "0.466245, 0.481291, 0.56913, 0.655701, 0.980548", \ "0.468949, 0.479052, 0.548495, 0.623572, 0.921915", \ "0.470223, 0.474638, 0.52103, 0.574755, 0.81244", \ "0.471349, 0.473321, 0.503764, 0.541347, 0.721374"); } } internal_power() { related_pin : "B"; fall_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.102089, 0.081899, 0.004099, 0.081889, 0.364067", \ "0.091104, 0.081433, 0.013893, 0.05433, 0.316314", \ "0.082948, 0.076999, 0.026844, 0.028762, 0.262565", \ "0.075627, 0.071226, 0.041145, 0.003101, 0.174623", \ "0.071982, 0.068232, 0.048929, 0.022647, 0.109431"); } rise_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.327471, 0.359665, 0.456073, 0.538038, 0.827306", \ "0.328715, 0.348434, 0.432924, 0.50892, 0.785124", \ "0.330943, 0.345576, 0.411051, 0.477251, 0.732958", \ "0.33314, 0.340104, 0.38188, 0.429048, 0.634249", \ "0.334316, 0.338068, 0.364148, 0.396284, 0.550801"); } } internal_power() { related_pin : "C"; fall_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.039917, 0.025421, 0.044056, 0.10395, 0.321615", \ "0.038445, 0.027707, 0.02289, 0.076886, 0.277398", \ "0.03745, 0.030634, 0.008031, 0.050014, 0.229433", \ "0.036262, 0.032418, 0.008947, 0.018318, 0.149657", \ "0.036161, 0.033715, 0.019044, 0.005086, 0.091927"); } rise_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.23864, 0.260149, 0.337369, 0.401465, 0.623264", \ "0.241704, 0.259122, 0.319202, 0.377187, 0.586033", \ "0.246207, 0.256253, 0.304379, 0.353436, 0.544489", \ "0.253474, 0.256182, 0.285822, 0.319753, 0.471382", \ "0.256034, 0.256796, 0.275212, 0.298605, 0.411567"); } } } } /* ---------------- * * Design : OAI22X1 * * ---------------- */ cell (OAI22X1) { area : 160; cell_leakage_power : 0.0438451; pin(A) { direction : input; capacitance : 0.0265291; rise_capacitance : 0.0263982; fall_capacitance : 0.0265291; } pin(B) { direction : input; capacitance : 0.0271075; rise_capacitance : 0.0271075; fall_capacitance : 0.0270484; } pin(C) { direction : input; capacitance : 0.026839; rise_capacitance : 0.026597; fall_capacitance : 0.026839; } pin(D) { direction : input; capacitance : 0.027353; rise_capacitance : 0.0273351; fall_capacitance : 0.027353; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.399598; function : "(!((A+B) (C+D)))"; timing() { related_pin : "A"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.099682, 0.111241, 0.125707, 0.130958, 0.134725", \ "0.133657, 0.147421, 0.168529, 0.178751, 0.194475", \ "0.186331, 0.200256, 0.228547, 0.244158, 0.276178", \ "0.341116, 0.35475, 0.388144, 0.412575, 0.474104", \ "0.597603, 0.610573, 0.641493, 0.667358, 0.75262"); } fall_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0975, 0.1137, 0.1611, 0.1959, 0.3141", \ "0.1443, 0.1539, 0.2004, 0.2361, 0.36", \ "0.216, 0.2229, 0.2595, 0.2937, 0.4203", \ "0.4365, 0.4368, 0.4539, 0.4788, 0.5916", \ "0.8049, 0.8052, 0.8082, 0.8196, 0.8982"); } cell_rise(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.113978, 0.132569, 0.165967, 0.191954, 0.267294", \ "0.159849, 0.178686, 0.216762, 0.246098, 0.333534", \ "0.23333, 0.250801, 0.291932, 0.323369, 0.423869", \ "0.456313, 0.469707, 0.506912, 0.540647, 0.65344", \ "0.822465, 0.835691, 0.867524, 0.896344, 1.00984"); } rise_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1371, 0.1512, 0.1992, 0.2316, 0.3435", \ "0.2043, 0.2148, 0.2514, 0.285, 0.3963", \ "0.3135, 0.3171, 0.342, 0.3723, 0.4794", \ "0.6429, 0.6429, 0.6513, 0.6651, 0.7473", \ "1.1937, 1.194, 1.1937, 1.1988, 1.2387"); } } timing() { related_pin : "B"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.081539, 0.090955, 0.09112, 0.085746, 0.052372", \ "0.11656, 0.129773, 0.141137, 0.143475, 0.128017", \ "0.170085, 0.183583, 0.206376, 0.21591, 0.222654", \ "0.324717, 0.33956, 0.370637, 0.392359, 0.439292", \ "0.582037, 0.596115, 0.625681, 0.650638, 0.72841"); } fall_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0716, 0.0927, 0.1332, 0.1608, 0.2559", \ "0.117, 0.1326, 0.1737, 0.2064, 0.3123", \ "0.1893, 0.1971, 0.2352, 0.2667, 0.3822", \ "0.4101, 0.4098, 0.4284, 0.4539, 0.5637", \ "0.7782, 0.7782, 0.7815, 0.7935, 0.873"); } cell_rise(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.103071, 0.136511, 0.196033, 0.2371, 0.359202", \ "0.149747, 0.184296, 0.251687, 0.297222, 0.434936", \ "0.223843, 0.255702, 0.330577, 0.381283, 0.534627", \ "0.444205, 0.473707, 0.543223, 0.600074, 0.78456", \ "0.810436, 0.838855, 0.903388, 0.955822, 1.14488"); } rise_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.135, 0.153, 0.198, 0.2253, 0.3162", \ "0.2025, 0.2139, 0.2574, 0.2862, 0.381", \ "0.3132, 0.3162, 0.3477, 0.378, 0.4806", \ "0.6429, 0.6429, 0.6501, 0.6681, 0.7626", \ "1.1937, 1.194, 1.1937, 1.1955, 1.2489"); } } timing() { related_pin : "C"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.094011, 0.119345, 0.148763, 0.164912, 0.201711", \ "0.128233, 0.155704, 0.19659, 0.218118, 0.268019", \ "0.181365, 0.209177, 0.26149, 0.290178, 0.358289", \ "0.337698, 0.364705, 0.423741, 0.467916, 0.576285", \ "0.598193, 0.623495, 0.679723, 0.724465, 0.873648"); } fall_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0906, 0.1125, 0.1605, 0.1959, 0.3093", \ "0.1383, 0.1539, 0.2022, 0.2397, 0.3633", \ "0.2118, 0.2196, 0.2652, 0.3048, 0.4323", \ "0.4347, 0.4344, 0.4554, 0.4878, 0.621", \ "0.8061, 0.8064, 0.8082, 0.822, 0.9252"); } cell_rise(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.089831, 0.10456, 0.130648, 0.146494, 0.187159", \ "0.138797, 0.156647, 0.187489, 0.209048, 0.265441", \ "0.213914, 0.231533, 0.267672, 0.292988, 0.368118", \ "0.439506, 0.452477, 0.487515, 0.518101, 0.614453", \ "0.80675, 0.819261, 0.850083, 0.877145, 0.98101"); } rise_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1125, 0.1308, 0.1749, 0.2145, 0.3174", \ "0.1797, 0.1911, 0.2307, 0.2616, 0.372", \ "0.288, 0.294, 0.3207, 0.3498, 0.4554", \ "0.6189, 0.6189, 0.6282, 0.6426, 0.7239", \ "1.1697, 1.1697, 1.1697, 1.1748, 1.2153"); } } timing() { related_pin : "D"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.076469, 0.096747, 0.109204, 0.113571, 0.107963", \ "0.111465, 0.13694, 0.165492, 0.177281, 0.19249", \ "0.16471, 0.191876, 0.23748, 0.258745, 0.298946", \ "0.321282, 0.349002, 0.406075, 0.447386, 0.539527", \ "0.583104, 0.608856, 0.663873, 0.707588, 0.849903"); } fall_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.07007, 0.0894, 0.1296, 0.159, 0.2499", \ "0.114, 0.1296, 0.1755, 0.2103, 0.3156", \ "0.1869, 0.1923, 0.2391, 0.2784, 0.3966", \ "0.408, 0.408, 0.4296, 0.4629, 0.5955", \ "0.7794, 0.7791, 0.7809, 0.795, 0.9009"); } cell_rise(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.081842, 0.111738, 0.157035, 0.187577, 0.274964", \ "0.130091, 0.16249, 0.22058, 0.258801, 0.366375", \ "0.20441, 0.236522, 0.305139, 0.350263, 0.480249", \ "0.427694, 0.456012, 0.523688, 0.57838, 0.747793", \ "0.794838, 0.822428, 0.886097, 0.93691, 1.11868"); } rise_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1128, 0.1395, 0.1785, 0.2028, 0.2886", \ "0.18, 0.1911, 0.2379, 0.2661, 0.3585", \ "0.2883, 0.2925, 0.3264, 0.3606, 0.4584", \ "0.6189, 0.6189, 0.6267, 0.6462, 0.7434", \ "1.1697, 1.17, 1.1697, 1.1712, 1.2267"); } } internal_power() { related_pin : "A"; fall_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.093005, 0.080247, 0.001934, 0.085385, 0.403434", \ "0.090562, 0.084903, 0.014984, 0.05941, 0.35681", \ "0.088775, 0.088039, 0.031366, 0.030932, 0.30022", \ "0.087613, 0.088242, 0.053589, 0.009783, 0.195844", \ "0.086783, 0.089764, 0.067932, 0.037722, 0.114082"); } rise_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.567336, 0.585153, 0.689057, 0.784135, 1.1216", \ "0.568835, 0.582947, 0.667664, 0.754389, 1.0767", \ "0.571537, 0.580912, 0.648621, 0.723309, 1.02002", \ "0.573152, 0.57716, 0.623394, 0.676483, 0.913095", \ "0.574389, 0.57618, 0.606405, 0.643855, 0.823087"); } } internal_power() { related_pin : "B"; fall_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.088523, 0.074773, 0.001582, 0.074304, 0.346332", \ "0.079427, 0.073381, 0.012304, 0.051299, 0.305006", \ "0.073028, 0.069307, 0.022515, 0.030143, 0.257198", \ "0.066606, 0.062886, 0.034537, 0.006264, 0.175", \ "0.063588, 0.059838, 0.041326, 0.01578, 0.113547"); } rise_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.430123, 0.457734, 0.554171, 0.634838, 0.922629", \ "0.43099, 0.452905, 0.53215, 0.60695, 0.882694", \ "0.433449, 0.44714, 0.511884, 0.57748, 0.831513", \ "0.436012, 0.442804, 0.48414, 0.530831, 0.735056", \ "0.437427, 0.441044, 0.466852, 0.498768, 0.652605"); } } internal_power() { related_pin : "C"; fall_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.090603, 0.078026, 0.007481, 0.084047, 0.3759", \ "0.089934, 0.082741, 0.014161, 0.057582, 0.331297", \ "0.089344, 0.082945, 0.033617, 0.027111, 0.276966", \ "0.088647, 0.087095, 0.056246, 0.017279, 0.17628", \ "0.088603, 0.08911, 0.069647, 0.044049, 0.094834"); } rise_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.481415, 0.498377, 0.596217, 0.678989, 0.974821", \ "0.487389, 0.499611, 0.577622, 0.652428, 0.93267", \ "0.494185, 0.499163, 0.562962, 0.62723, 0.88359", \ "0.501207, 0.502203, 0.544424, 0.590529, 0.795418", \ "0.50424, 0.504592, 0.532487, 0.565813, 0.723169"); } } internal_power() { related_pin : "D"; fall_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.084454, 0.07014, 0.007653, 0.07698, 0.333208", \ "0.077041, 0.068312, 0.011785, 0.052152, 0.291466", \ "0.07137, 0.065161, 0.024364, 0.026952, 0.243531", \ "0.065249, 0.061466, 0.036845, 0.006308, 0.160212", \ "0.061641, 0.059102, 0.043482, 0.021601, 0.097281"); } rise_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.346181, 0.372918, 0.463552, 0.537378, 0.797827", \ "0.351602, 0.370931, 0.443684, 0.511436, 0.758151", \ "0.35689, 0.369502, 0.426648, 0.485184, 0.711665", \ "0.364201, 0.368483, 0.405549, 0.447039, 0.628421", \ "0.366958, 0.369421, 0.393291, 0.42183, 0.559392"); } } } } /* -------------- * * Design : OR2X1 * * -------------- */ cell (OR2X1) { area : 128; cell_leakage_power : 0.0494157; pin(A) { direction : input; capacitance : 0.0228029; rise_capacitance : 0.0228029; fall_capacitance : 0.0226707; } pin(B) { direction : input; capacitance : 0.0222093; rise_capacitance : 0.0221164; fall_capacitance : 0.0222093; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.409507; function : "(A+B)"; timing() { related_pin : "A"; timing_sense : positive_unate; cell_rise(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.116621, 0.141019, 0.171773, 0.182263, 0.225689", \ "0.169773, 0.19202, 0.219578, 0.239302, 0.281571", \ "0.246589, 0.272622, 0.29888, 0.317902, 0.362902", \ "0.479521, 0.506335, 0.535004, 0.551825, 0.599689", \ "0.869562, 0.895033, 0.923384, 0.940276, 0.989101"); } rise_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0696, 0.072, 0.0816, 0.0798, 0.0978", \ "0.1332, 0.1356, 0.1404, 0.1434, 0.1542", \ "0.2478, 0.249, 0.2508, 0.2538, 0.2634", \ "0.5982, 0.5982, 0.5994, 0.5994, 0.6054", \ "1.1826, 1.1832, 1.1826, 1.1832, 1.1856"); } cell_fall(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.122276, 0.135675, 0.17137, 0.193173, 0.240241", \ "0.171985, 0.193193, 0.225337, 0.245767, 0.298625", \ "0.242362, 0.266203, 0.300365, 0.320535, 0.377601", \ "0.448049, 0.470992, 0.511035, 0.534031, 0.594333", \ "0.788885, 0.811967, 0.851586, 0.875565, 0.940598"); } fall_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0648, 0.0606, 0.0738, 0.0768, 0.0876", \ "0.1176, 0.1176, 0.126, 0.1284, 0.1398", \ "0.2034, 0.207, 0.2136, 0.2148, 0.2262", \ "0.4812, 0.4812, 0.486, 0.4884, 0.4992", \ "0.9504, 0.9504, 0.9516, 0.9534, 0.9624"); } } timing() { related_pin : "B"; timing_sense : positive_unate; cell_rise(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.151161, 0.179944, 0.232366, 0.259262, 0.344699", \ "0.202914, 0.231278, 0.282411, 0.312468, 0.40075", \ "0.282686, 0.310784, 0.359634, 0.391715, 0.47917", \ "0.516346, 0.543933, 0.593682, 0.624603, 0.712439", \ "0.904994, 0.932467, 0.982343, 1.01297, 1.10095"); } rise_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0726, 0.069, 0.0816, 0.09, 0.0924", \ "0.1362, 0.1386, 0.1404, 0.1464, 0.1524", \ "0.2484, 0.2502, 0.2514, 0.2532, 0.258", \ "0.5988, 0.5988, 0.5994, 0.6006, 0.603", \ "1.1832, 1.1832, 1.1838, 1.1838, 1.185"); } cell_fall(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.133001, 0.1391, 0.156334, 0.165958, 0.175645", \ "0.181856, 0.19189, 0.212139, 0.223187, 0.239212", \ "0.2521, 0.264486, 0.288531, 0.300354, 0.322806", \ "0.458413, 0.474315, 0.496047, 0.509051, 0.5424", \ "0.799487, 0.815231, 0.836946, 0.850252, 0.886582"); } fall_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0624, 0.0648, 0.0804, 0.0804, 0.0972", \ "0.1182, 0.117, 0.1284, 0.1344, 0.1476", \ "0.2022, 0.207, 0.2112, 0.2172, 0.2346", \ "0.4806, 0.4812, 0.4836, 0.4866, 0.5022", \ "0.9504, 0.9504, 0.951, 0.9522, 0.9594"); } } internal_power() { related_pin : "A"; rise_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.017102, 0.034419, 0.107899, 0.180566, 0.418477", \ "0.018728, 0.0344, 0.111465, 0.175924, 0.407725", \ "0.019969, 0.036876, 0.109863, 0.173038, 0.401608", \ "0.020865, 0.037922, 0.108322, 0.172868, 0.397457", \ "0.017177, 0.03847, 0.108832, 0.172878, 0.396039"); } fall_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.312329, 0.342105, 0.425274, 0.49504, 0.742271", \ "0.316757, 0.351907, 0.431906, 0.490856, 0.732378", \ "0.319372, 0.353006, 0.431303, 0.496617, 0.726868", \ "0.320371, 0.353453, 0.433133, 0.498296, 0.72632", \ "0.320848, 0.353964, 0.433844, 0.498794, 0.725373"); } } internal_power() { related_pin : "B"; rise_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.015274, 0.033162, 0.119309, 0.185392, 0.451048", \ "0.016943, 0.031026, 0.11302, 0.180911, 0.440258", \ "0.0214, 0.03617, 0.109436, 0.177422, 0.431534", \ "0.022433, 0.036916, 0.108068, 0.174535, 0.422962", \ "0.022904, 0.037408, 0.108385, 0.174146, 0.419879"); } fall_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.447211, 0.469718, 0.557633, 0.637211, 0.910248", \ "0.456807, 0.472787, 0.560509, 0.633945, 0.898334", \ "0.459226, 0.475175, 0.561583, 0.635482, 0.892014", \ "0.458211, 0.478494, 0.561743, 0.63445, 0.887859", \ "0.458879, 0.478706, 0.562633, 0.634448, 0.886057"); } } } } /* -------------- * * Design : OR2X2 * * -------------- */ cell (OR2X2) { area : 128; cell_leakage_power : 0.0500804; pin(A) { direction : input; capacitance : 0.0228068; rise_capacitance : 0.0228068; fall_capacitance : 0.02268; } pin(B) { direction : input; capacitance : 0.0221869; rise_capacitance : 0.0220189; fall_capacitance : 0.0221869; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.830878; function : "(A+B)"; timing() { related_pin : "A"; timing_sense : positive_unate; cell_rise(delay_template_5x5) { index_1 ("0.03, 0.08, 0.16, 0.4, 0.8"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.149923, 0.175661, 0.214279, 0.240462, 0.293201", \ "0.199427, 0.226702, 0.268998, 0.29309, 0.351953", \ "0.278739, 0.306228, 0.346649, 0.370717, 0.432611", \ "0.508794, 0.535027, 0.576267, 0.599595, 0.661745", \ "0.89133, 0.917648, 0.958436, 0.981751, 1.04404"); } rise_transition(delay_template_5x5) { index_1 ("0.03, 0.08, 0.16, 0.4, 0.8"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0756, 0.0792, 0.087, 0.0894, 0.1032", \ "0.1398, 0.1398, 0.1452, 0.1494, 0.1632", \ "0.2478, 0.249, 0.252, 0.2532, 0.2646", \ "0.5928, 0.5922, 0.5934, 0.594, 0.5988", \ "1.17, 1.17, 1.17, 1.17, 1.1724"); } cell_fall(delay_template_5x5) { index_1 ("0.03, 0.08, 0.16, 0.4, 0.8"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.151974, 0.179103, 0.219752, 0.247739, 0.316746", \ "0.206425, 0.233336, 0.277136, 0.304366, 0.374008", \ "0.28184, 0.311448, 0.354366, 0.381045, 0.453258", \ "0.490585, 0.520089, 0.565364, 0.594056, 0.668795", \ "0.835088, 0.864651, 0.909519, 0.938399, 1.0172"); } fall_transition(delay_template_5x5) { index_1 ("0.03, 0.08, 0.16, 0.4, 0.8"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0738, 0.0732, 0.0798, 0.0864, 0.0948", \ "0.1242, 0.126, 0.132, 0.138, 0.1464", \ "0.2124, 0.2142, 0.2214, 0.2214, 0.2346", \ "0.4902, 0.4902, 0.4932, 0.4968, 0.5046", \ "0.9642, 0.9642, 0.9648, 0.966, 0.9732"); } } timing() { related_pin : "B"; timing_sense : positive_unate; cell_rise(delay_template_5x5) { index_1 ("0.03, 0.08, 0.16, 0.4, 0.8"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.183048, 0.213362, 0.265391, 0.301296, 0.396946", \ "0.232641, 0.263758, 0.320597, 0.356245, 0.454443", \ "0.310805, 0.341355, 0.398071, 0.433587, 0.532794", \ "0.541276, 0.570536, 0.62756, 0.661687, 0.759848", \ "0.924026, 0.953291, 1.00993, 1.0439, 1.1419"); } rise_transition(delay_template_5x5) { index_1 ("0.03, 0.08, 0.16, 0.4, 0.8"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0804, 0.0804, 0.09, 0.09, 0.1008", \ "0.1422, 0.1416, 0.147, 0.15, 0.1608", \ "0.2508, 0.2508, 0.2532, 0.2556, 0.2622", \ "0.5934, 0.5934, 0.594, 0.5946, 0.597", \ "1.1706, 1.1706, 1.1706, 1.1712, 1.1718"); } cell_fall(delay_template_5x5) { index_1 ("0.03, 0.08, 0.16, 0.4, 0.8"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.161913, 0.175793, 0.198165, 0.211427, 0.233117", \ "0.216632, 0.23218, 0.254804, 0.269345, 0.298561", \ "0.290588, 0.306249, 0.331226, 0.348782, 0.382841", \ "0.499534, 0.515937, 0.542813, 0.559284, 0.601717", \ "0.844164, 0.860559, 0.886871, 0.903663, 0.948099"); } fall_transition(delay_template_5x5) { index_1 ("0.03, 0.08, 0.16, 0.4, 0.8"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0738, 0.0714, 0.0846, 0.0852, 0.1044", \ "0.126, 0.126, 0.1332, 0.1392, 0.1572", \ "0.213, 0.2136, 0.2178, 0.2238, 0.2406", \ "0.4902, 0.4902, 0.4926, 0.495, 0.5082", \ "0.9642, 0.9642, 0.9648, 0.9654, 0.9714"); } } internal_power() { related_pin : "A"; rise_power(energy_template_5x5) { index_1 ("0.03, 0.08, 0.16, 0.4, 0.8"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.143606, 0.159455, 0.247567, 0.323718, 0.583509", \ "0.146236, 0.159361, 0.239709, 0.307446, 0.554686", \ "0.151142, 0.166343, 0.233162, 0.300645, 0.535376", \ "0.152838, 0.166825, 0.23068, 0.293997, 0.516851", \ "0.15358, 0.166966, 0.230603, 0.291821, 0.509766"); } fall_power(energy_template_5x5) { index_1 ("0.03, 0.08, 0.16, 0.4, 0.8"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.412259, 0.447604, 0.512618, 0.603395, 0.875806", \ "0.422527, 0.451273, 0.530228, 0.60005, 0.844451", \ "0.425524, 0.455382, 0.526235, 0.593507, 0.826909", \ "0.428475, 0.455919, 0.527383, 0.589655, 0.817678", \ "0.429846, 0.456069, 0.528202, 0.589279, 0.812706"); } } internal_power() { related_pin : "B"; rise_power(energy_template_5x5) { index_1 ("0.03, 0.08, 0.16, 0.4, 0.8"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.158475, 0.176916, 0.258663, 0.340389, 0.62443", \ "0.15613, 0.171011, 0.246698, 0.323213, 0.593404", \ "0.154116, 0.166576, 0.235641, 0.307781, 0.570045", \ "0.151151, 0.164221, 0.230976, 0.298574, 0.546499", \ "0.151983, 0.163875, 0.230365, 0.295306, 0.537133"); } fall_power(energy_template_5x5) { index_1 ("0.03, 0.08, 0.16, 0.4, 0.8"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.542212, 0.568381, 0.653969, 0.748461, 1.04478", \ "0.563282, 0.58098, 0.658463, 0.73345, 1.01195", \ "0.565298, 0.582109, 0.658657, 0.730383, 0.994315", \ "0.564066, 0.581296, 0.658311, 0.726096, 0.98029", \ "0.566105, 0.581601, 0.657839, 0.725935, 0.974505"); } } } } /* --------------- * * Design : PADINC * * --------------- */ cell (PADINC) { pad_cell : true; area : 12000; cell_leakage_power : 0.748445; pin(DI) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 4.89099; function : "YPAD"; timing() { related_pin : "YPAD"; timing_sense : positive_unate; cell_rise(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.152534, 0.179221, 0.20102, 0.224548, 0.227205, 0.223333", \ "0.22519, 0.257474, 0.280681, 0.299959, 0.305456, 0.30549", \ "0.340609, 0.372848, 0.396474, 0.417671, 0.424803, 0.427446", \ "0.632929, 0.668257, 0.691791, 0.710987, 0.718586, 0.725458", \ "0.795209, 0.830454, 0.853988, 0.873846, 0.881408, 0.888529", \ "0.957336, 0.992869, 1.01641, 1.03607, 1.04444, 1.05094"); } rise_transition(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.0618, 0.058956, 0.069, 0.0768, 0.0822, 0.0876", \ "0.15, 0.1536, 0.159, 0.1656, 0.1692, 0.1764", \ "0.3162, 0.3174, 0.3204, 0.324, 0.3288, 0.3378", \ "0.7536, 0.7536, 0.7542, 0.7566, 0.759, 0.7656", \ "0.9972, 0.9966, 0.9972, 0.999, 1.0008, 1.0068", \ "1.2402, 1.2402, 1.2402, 1.2414, 1.2432, 1.2474"); } cell_fall(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.172083, 0.219014, 0.273229, 0.36053, 0.413009, 0.504921", \ "0.231464, 0.283317, 0.342902, 0.428156, 0.483676, 0.581767", \ "0.318245, 0.371457, 0.43331, 0.522719, 0.579321, 0.681297", \ "0.530621, 0.585515, 0.648208, 0.738671, 0.796486, 0.903578", \ "0.647548, 0.702226, 0.765212, 0.856545, 0.914527, 1.02242", \ "0.764219, 0.819181, 0.882102, 0.973635, 1.03241, 1.14013"); } fall_transition(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.045496, 0.049778, 0.057394, 0.0636, 0.0666, 0.0756", \ "0.1128, 0.114, 0.1158, 0.1272, 0.1302, 0.1386", \ "0.2178, 0.219, 0.222, 0.2286, 0.2328, 0.2442", \ "0.5058, 0.507, 0.5088, 0.513, 0.516, 0.5238", \ "0.6696, 0.6702, 0.6702, 0.6744, 0.6762, 0.6828", \ "0.8328, 0.8328, 0.8334, 0.8364, 0.8382, 0.8442"); } } internal_power() { related_pin : "YPAD"; rise_power(energy_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "2.41284, 2.65791, 3.496, 5.03716, 6.18986, 8.56649", \ "2.42437, 2.66532, 3.38914, 4.88648, 6.00418, 8.29957", \ "2.4729, 2.68743, 3.36438, 4.7715, 5.88312, 8.17552", \ "2.5142, 2.71198, 3.36768, 4.77117, 5.84479, 8.04955", \ "2.52137, 2.72219, 3.37948, 4.77758, 5.84596, 8.03764", \ "2.52545, 2.72845, 3.38799, 4.78235, 5.84811, 8.03265"); } fall_power(energy_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "6.55365, 6.90576, 7.72103, 9.41953, 10.6374, 13.1264", \ "6.62455, 6.98144, 7.72955, 9.25512, 10.4623, 12.8509", \ "6.70304, 7.03546, 7.78007, 9.33944, 10.4694, 12.75", \ "6.74823, 7.07908, 7.83794, 9.36067, 10.4783, 12.7397", \ "6.75673, 7.088, 7.84989, 9.36809, 10.483, 12.7368", \ "6.76159, 7.09342, 7.85793, 9.37331, 10.4879, 12.7372"); } } } pin(YPAD) { is_pad : true; direction : input; capacitance : 0.6369; rise_capacitance : 0.6369; fall_capacitance : 0.635915; } } /* ----------------- * * Design : PADINOUT * * ----------------- */ cell (PADINOUT) { pad_cell : true; area : 12000; cell_leakage_power : 0.766836; pin(DI) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 4.89099; function : "YPAD"; timing() { related_pin : "YPAD"; timing_sense : positive_unate; cell_rise(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.152534, 0.179221, 0.20102, 0.224548, 0.227205, 0.223333", \ "0.22519, 0.257474, 0.280681, 0.299959, 0.305456, 0.30549", \ "0.340609, 0.372848, 0.396474, 0.417671, 0.424803, 0.427446", \ "0.632929, 0.668257, 0.691791, 0.710987, 0.718586, 0.725458", \ "0.795209, 0.830454, 0.853988, 0.873846, 0.881408, 0.888529", \ "0.957336, 0.992869, 1.01641, 1.03607, 1.04444, 1.05094"); } rise_transition(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.0618, 0.058956, 0.069, 0.0768, 0.0822, 0.0876", \ "0.15, 0.1536, 0.159, 0.1656, 0.1692, 0.1764", \ "0.3162, 0.3174, 0.3204, 0.324, 0.3288, 0.3378", \ "0.7536, 0.7536, 0.7542, 0.7566, 0.759, 0.7656", \ "0.9972, 0.9966, 0.9972, 0.999, 1.0008, 1.0068", \ "1.2402, 1.2402, 1.2402, 1.2414, 1.2432, 1.2474"); } cell_fall(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.172083, 0.219014, 0.273229, 0.36053, 0.413009, 0.504921", \ "0.231464, 0.283317, 0.342902, 0.428156, 0.483676, 0.581767", \ "0.318245, 0.371457, 0.43331, 0.522719, 0.579321, 0.681297", \ "0.530621, 0.585515, 0.648208, 0.738671, 0.796486, 0.903578", \ "0.647548, 0.702226, 0.765212, 0.856545, 0.914527, 1.02242", \ "0.764219, 0.819181, 0.882102, 0.973635, 1.03241, 1.14013"); } fall_transition(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.045496, 0.049778, 0.057394, 0.0636, 0.0666, 0.0756", \ "0.1128, 0.114, 0.1158, 0.1272, 0.1302, 0.1386", \ "0.2178, 0.219, 0.222, 0.2286, 0.2328, 0.2442", \ "0.5058, 0.507, 0.5088, 0.513, 0.516, 0.5238", \ "0.6696, 0.6702, 0.6702, 0.6744, 0.6762, 0.6828", \ "0.8328, 0.8328, 0.8334, 0.8364, 0.8382, 0.8442"); } } internal_power() { related_pin : "YPAD"; rise_power(energy_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "2.41281, 2.65792, 3.49596, 5.03709, 6.18999, 8.56634", \ "2.42436, 2.66526, 3.38904, 4.88673, 6.00412, 8.29948", \ "2.47281, 2.68712, 3.36427, 4.77196, 5.88273, 8.17544", \ "2.51386, 2.71212, 3.3668, 4.77168, 5.84351, 8.0495", \ "2.52086, 2.7224, 3.37831, 4.77813, 5.84384, 8.03767", \ "2.52476, 2.72887, 3.3865, 4.78295, 5.84519, 8.03276"); } fall_power(energy_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "6.55368, 6.90568, 7.7209, 9.41948, 10.6373, 13.1263", \ "6.62462, 6.98136, 7.72936, 9.25511, 10.4624, 12.8511", \ "6.70324, 7.03534, 7.77985, 9.33938, 10.4696, 12.7501", \ "6.74878, 7.07907, 7.83803, 9.36065, 10.4785, 12.7398", \ "6.75747, 7.08801, 7.8501, 9.36817, 10.4833, 12.7368", \ "6.76252, 7.09344, 7.85825, 9.37348, 10.4884, 12.737"); } } } pin(DO) { direction : input; capacitance : 0.252195; rise_capacitance : 0.251023; fall_capacitance : 0.252195; } pin(OEN) { direction : input; capacitance : 0.0502646; rise_capacitance : 0.0502646; fall_capacitance : 0.0500636; internal_power() { rise_power(passive_energy_template_6x1) { index_1 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ("0, 0, 0, 0, 0, 0"); } fall_power(passive_energy_template_6x1) { index_1 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ("10.2397, 10.2835, 10.3871, 10.7385, 11.0196, 11.557"); } } } pin(YPAD) { is_pad : true; direction : inout; drive_current : 2.0; capacitance : 0.636904; rise_capacitance : 0.636904; fall_capacitance : 0.635915; max_capacitance : 9.39352; function : "DO"; three_state : "(!OEN)"; timing() { related_pin : "DO"; timing_sense : positive_unate; cell_rise(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.592524, 0.620346, 0.641214, 0.663974, 0.66899, 0.671428", \ "0.646934, 0.674846, 0.695651, 0.719378, 0.724583, 0.727539", \ "0.725028, 0.753077, 0.774274, 0.797934, 0.803839, 0.807345", \ "0.888457, 0.916215, 0.937559, 0.96169, 0.967811, 0.971692", \ "0.969026, 0.996925, 1.01844, 1.04264, 1.04857, 1.05254", \ "1.04685, 1.07464, 1.09595, 1.12035, 1.12647, 1.13049"); } rise_transition(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.1746, 0.1764, 0.1722, 0.1752, 0.1788, 0.18", \ "0.2214, 0.2208, 0.222, 0.222, 0.2226, 0.2238", \ "0.297, 0.2976, 0.2988, 0.2982, 0.2982, 0.2994", \ "0.4812, 0.4812, 0.4818, 0.4818, 0.4818, 0.4818", \ "0.582, 0.582, 0.582, 0.582, 0.5826, 0.582", \ "0.6828, 0.6828, 0.6828, 0.6828, 0.6834, 0.6828"); } cell_fall(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.58905, 0.639829, 0.693677, 0.779719, 0.834977, 0.933865", \ "0.626019, 0.676719, 0.731176, 0.817648, 0.872564, 0.971599", \ "0.683105, 0.733828, 0.788131, 0.87412, 0.929892, 1.02901", \ "0.805329, 0.856124, 0.910615, 0.996383, 1.05249, 1.15196", \ "0.866553, 0.917379, 0.971785, 1.05805, 1.11418, 1.21361", \ "0.925606, 0.976455, 1.03104, 1.11719, 1.17367, 1.27317"); } fall_transition(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.2256, 0.2244, 0.2226, 0.2202, 0.2154, 0.2088", \ "0.2508, 0.249, 0.2472, 0.2454, 0.2394, 0.2352", \ "0.2952, 0.2946, 0.2934, 0.2898, 0.285, 0.282", \ "0.4092, 0.4086, 0.408, 0.4056, 0.4032, 0.3996", \ "0.477, 0.4758, 0.4764, 0.474, 0.4716, 0.4698", \ "0.5496, 0.549, 0.5484, 0.5466, 0.546, 0.5424"); } } timing() { related_pin : "OEN"; timing_sense : positive_unate; timing_type : three_state_enable; cell_rise(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "1.07279, 1.12151, 1.18206, 1.26323, 1.3023, 1.36449", \ "1.13026, 1.179, 1.23933, 1.32131, 1.36041, 1.42189", \ "1.21044, 1.25924, 1.31955, 1.40114, 1.44009, 1.50202", \ "1.37436, 1.4231, 1.48297, 1.5651, 1.60386, 1.666", \ "1.45489, 1.50365, 1.56369, 1.6459, 1.68486, 1.74679", \ "1.53262, 1.58137, 1.6412, 1.72342, 1.76224, 1.82435"); } rise_transition(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.1848, 0.1842, 0.186, 0.1848, 0.1872, 0.1842", \ "0.2304, 0.2304, 0.231, 0.2304, 0.2304, 0.231", \ "0.3048, 0.3048, 0.3048, 0.3042, 0.3036, 0.3048", \ "0.4854, 0.4854, 0.486, 0.486, 0.486, 0.486", \ "0.5856, 0.5856, 0.5856, 0.5862, 0.5856, 0.5856", \ "0.6858, 0.6852, 0.6858, 0.6852, 0.6852, 0.6858"); } cell_fall(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.65438, 0.704742, 0.772802, 0.852188, 0.893105, 0.956762", \ "0.70321, 0.753575, 0.821632, 0.900806, 0.941926, 1.00558", \ "0.771359, 0.821715, 0.889757, 0.968599, 1.00989, 1.0735", \ "0.910023, 0.960378, 1.02848, 1.10741, 1.14866, 1.21243", \ "0.978483, 1.02884, 1.09687, 1.17587, 1.21716, 1.28072", \ "1.04406, 1.09441, 1.16238, 1.24124, 1.28272, 1.34633"); } fall_transition(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.1392, 0.1398, 0.1392, 0.138, 0.1398, 0.1386", \ "0.1704, 0.1704, 0.1716, 0.1722, 0.171, 0.1734", \ "0.2322, 0.2322, 0.231, 0.231, 0.2316, 0.231", \ "0.3738, 0.3738, 0.3732, 0.3738, 0.3732, 0.3732", \ "0.4518, 0.4518, 0.4512, 0.4518, 0.4512, 0.4518", \ "0.531, 0.531, 0.5316, 0.531, 0.531, 0.5316"); } } timing() { related_pin : "OEN"; timing_type : three_state_disable; timing_sense : negative_unate; cell_rise(delay_template_6x1) { index_1 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ("0.81801, 0.875159, 0.960552, 1.09692, 1.18016, 1.33249"); } rise_transition(delay_template_6x1) { index_1 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ("0.81801, 0.875159, 0.960552, 1.09692, 1.18016, 1.33249"); } cell_fall(delay_template_6x1) { index_1 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ("1.45459, 1.51654, 1.59578, 1.71923, 1.79743, 1.94063"); } fall_transition(delay_template_6x1) { index_1 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ("1.45459, 1.51654, 1.59578, 1.71923, 1.79743, 1.94063"); } } internal_power() { related_pin : "DO"; rise_power(energy_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "13.3693, 13.5644, 13.9316, 15.0257, 15.9455, 17.6391", \ "13.4393, 13.6138, 13.9801, 15.1337, 15.9931, 17.7663", \ "13.6731, 13.7663, 14.197, 15.3749, 16.1769, 17.9779", \ "14.2581, 14.3969, 14.8963, 15.9839, 16.8333, 18.6771", \ "14.6069, 14.783, 15.2305, 16.3535, 17.2164, 19.0077", \ "14.982, 15.1434, 15.6147, 16.7487, 17.5969, 19.4049"); } fall_power(energy_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "28.3762, 28.4342, 28.909, 29.7262, 30.1816, 31.4312", \ "27.2939, 27.3651, 27.8909, 28.7373, 29.1882, 30.4528", \ "25.992, 26.0566, 26.4998, 27.4051, 27.8885, 29.294", \ "23.9139, 24.017, 24.5617, 25.4326, 26.0431, 27.546", \ "23.3001, 23.4155, 23.9275, 24.942, 25.5264, 27.0459", \ "22.9255, 23.0457, 23.5486, 24.5807, 25.2163, 26.7967"); } } internal_power() { related_pin : "OEN"; rise_power(energy_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "17.3333, 17.3941, 17.4597, 17.8279, 17.9936, 18.523", \ "17.5137, 17.529, 17.6008, 17.8267, 18.0859, 18.5803", \ "17.6438, 17.6853, 17.7615, 18.0874, 18.3221, 18.7593", \ "18.2105, 18.2195, 18.3238, 18.5898, 18.834, 19.2867", \ "18.5235, 18.5293, 18.6632, 18.9447, 19.1604, 19.6392", \ "18.8792, 18.8846, 18.9951, 19.2784, 19.52, 19.9748"); } fall_power(energy_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "12.2986, 12.3559, 12.5851, 12.9559, 13.2653, 13.9614", \ "12.4284, 12.4803, 12.622, 13.1296, 13.3974, 14.0072", \ "12.6672, 12.7027, 12.7732, 13.2912, 13.5598, 14.158", \ "13.0905, 13.1278, 13.2864, 13.7133, 13.9951, 14.6463", \ "13.3787, 13.4146, 13.5793, 14.0081, 14.2874, 14.9475", \ "13.6474, 13.684, 13.8724, 14.3059, 14.6134, 15.2231"); } } } } /* --------------- * * Design : PADOUT * * --------------- */ cell (PADOUT) { pad_cell : true; area : 12000; cell_leakage_power : 1.00545; pin(DO) { direction : input; capacitance : 0.25215; rise_capacitance : 0.251005; fall_capacitance : 0.25215; } pin(YPAD) { is_pad : true; direction : output; drive_current : 2.0; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 9.44634; function : "DO"; timing() { related_pin : "DO"; timing_sense : positive_unate; cell_rise(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.592524, 0.620346, 0.641214, 0.663974, 0.66899, 0.671428", \ "0.646934, 0.674846, 0.695651, 0.719378, 0.724583, 0.727539", \ "0.725028, 0.753077, 0.774274, 0.797934, 0.803839, 0.807345", \ "0.888457, 0.916215, 0.937559, 0.96169, 0.967811, 0.971692", \ "0.969026, 0.996925, 1.01844, 1.04264, 1.04857, 1.05254", \ "1.04685, 1.07464, 1.09595, 1.12035, 1.12647, 1.13049"); } rise_transition(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.1746, 0.1764, 0.1722, 0.1752, 0.1788, 0.18", \ "0.2214, 0.2208, 0.222, 0.222, 0.2226, 0.2238", \ "0.297, 0.2976, 0.2988, 0.2982, 0.2982, 0.2994", \ "0.4812, 0.4812, 0.4818, 0.4818, 0.4818, 0.4818", \ "0.582, 0.582, 0.582, 0.582, 0.5826, 0.582", \ "0.6828, 0.6828, 0.6828, 0.6828, 0.6834, 0.6828"); } cell_fall(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.58905, 0.639829, 0.693677, 0.779719, 0.834977, 0.933865", \ "0.626019, 0.676719, 0.731176, 0.817648, 0.872564, 0.971599", \ "0.683105, 0.733828, 0.788131, 0.87412, 0.929892, 1.02901", \ "0.805329, 0.856124, 0.910615, 0.996383, 1.05249, 1.15196", \ "0.866553, 0.917379, 0.971785, 1.05805, 1.11418, 1.21361", \ "0.925606, 0.976455, 1.03104, 1.11719, 1.17367, 1.27317"); } fall_transition(delay_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "0.2256, 0.2244, 0.2226, 0.2202, 0.2154, 0.2088", \ "0.2508, 0.249, 0.2472, 0.2454, 0.2394, 0.2352", \ "0.2952, 0.2946, 0.2934, 0.2898, 0.285, 0.282", \ "0.4092, 0.4086, 0.408, 0.4056, 0.4032, 0.3996", \ "0.477, 0.4758, 0.4764, 0.474, 0.4716, 0.4698", \ "0.5496, 0.549, 0.5484, 0.5466, 0.546, 0.5424"); } } internal_power() { related_pin : "DO"; rise_power(energy_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "13.0671, 13.2376, 13.6266, 14.7085, 15.6789, 17.5639", \ "13.197, 13.3591, 13.775, 14.9332, 15.7929, 17.6686", \ "13.5471, 13.6264, 14.0609, 15.2442, 16.0641, 17.8557", \ "14.2296, 14.3675, 14.8685, 15.9554, 16.8048, 18.658", \ "14.601, 14.7819, 15.2319, 16.354, 17.2162, 19.0078", \ "14.9845, 15.1423, 15.616, 16.7493, 17.5969, 19.4049"); } fall_power(energy_template_6x6) { index_1 ("0.1, 0.5, 1.2, 3, 4, 5"); index_2 ("0.06, 0.24, 0.48, 0.9, 1.2, 1.8"); values ( \ "28.1289, 28.1433, 28.6709, 29.442, 29.9409, 31.2284", \ "27.1056, 27.1221, 27.6502, 28.5, 28.9893, 30.2259", \ "25.8458, 25.9108, 26.3779, 27.2622, 27.7613, 29.1385", \ "23.871, 23.9753, 24.5218, 25.3883, 25.9884, 27.506", \ "23.2737, 23.3975, 23.9098, 24.9162, 25.5, 27.0176", \ "22.9163, 23.0373, 23.5396, 24.5726, 25.2084, 26.7964"); } } } } /* --------------- * * Design : TBUFX1 * * --------------- */ cell (TBUFX1) { area : 160; cell_leakage_power : 0.0371798; pin(A) { direction : input; capacitance : 0.0265851; rise_capacitance : 0.0263529; fall_capacitance : 0.0265851; } pin(EN) { direction : input; capacitance : 0.0188377; rise_capacitance : 0.0185919; fall_capacitance : 0.0188377; internal_power() { rise_power(passive_energy_template_5x1) { index_1 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ("0, 0, 0, 0, 0"); } fall_power(passive_energy_template_5x1) { index_1 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ("0.140165, 0.17407, 0.245999, 0.301738, 0.494453"); } } } pin(Y) { direction : output; capacitance : 0.00361644; rise_capacitance : 0.00361644; fall_capacitance : 0.00360475; max_capacitance : 0.419492; function : "(!A)"; three_state : "(!EN)"; timing() { related_pin : "A"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.0186047, 0.0436048, 0.0836047, 0.203605, 0.403605"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.076828, 0.084201, 0.094381, 0.097456, 0.094047", \ "0.117173, 0.126665, 0.143616, 0.151084, 0.160578", \ "0.177971, 0.188904, 0.210149, 0.222756, 0.248764", \ "0.359557, 0.365852, 0.388987, 0.407904, 0.459819", \ "0.652641, 0.657987, 0.677926, 0.695959, 0.76241"); } fall_transition(delay_template_5x5) { index_1 ("0.0186047, 0.0436048, 0.0836047, 0.203605, 0.403605"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0858, 0.1032, 0.15, 0.1872, 0.3", \ "0.1362, 0.1464, 0.1926, 0.2268, 0.3498", \ "0.2196, 0.225, 0.258, 0.2898, 0.4146", \ "0.4692, 0.4692, 0.4824, 0.504, 0.6078", \ "0.888, 0.888, 0.8904, 0.8988, 0.9612"); } cell_rise(delay_template_5x5) { index_1 ("0.0186164, 0.0436164, 0.0836164, 0.203616, 0.403616"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.099288, 0.115332, 0.143742, 0.166674, 0.233705", \ "0.149629, 0.162947, 0.198575, 0.224753, 0.305215", \ "0.222986, 0.237122, 0.274689, 0.305122, 0.399352", \ "0.442935, 0.455158, 0.491737, 0.52437, 0.633345", \ "0.809218, 0.820335, 0.852257, 0.880571, 0.991413"); } rise_transition(delay_template_5x5) { index_1 ("0.0186164, 0.0436164, 0.0836164, 0.203616, 0.403616"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0984, 0.1188, 0.1626, 0.1962, 0.3048", \ "0.168, 0.1788, 0.2172, 0.2496, 0.363", \ "0.276, 0.2802, 0.3078, 0.3372, 0.447", \ "0.6072, 0.6072, 0.6156, 0.6306, 0.7128", \ "1.158, 1.158, 1.158, 1.1634, 1.2036"); } } timing() { related_pin : "EN"; timing_sense : positive_unate; timing_type : three_state_enable; cell_rise(delay_template_5x5) { index_1 ("0.0186164, 0.0436164, 0.0836164, 0.203616, 0.403616"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.095408, 0.112526, 0.130521, 0.133493, 0.131664", \ "0.145862, 0.161494, 0.181367, 0.189341, 0.196055", \ "0.217972, 0.23754, 0.255784, 0.265788, 0.276245", \ "0.436765, 0.456917, 0.473495, 0.480871, 0.501758", \ "0.802871, 0.823056, 0.839344, 0.847499, 0.864799"); } rise_transition(delay_template_5x5) { index_1 ("0.0186164, 0.0436164, 0.0836164, 0.203616, 0.403616"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1194, 0.105, 0.1098, 0.1134, 0.1314", \ "0.1734, 0.1686, 0.1674, 0.1728, 0.183", \ "0.2772, 0.2778, 0.2712, 0.2724, 0.2796", \ "0.6072, 0.6072, 0.603, 0.6006, 0.6012", \ "1.158, 1.1586, 1.1586, 1.155, 1.1508"); } cell_fall(delay_template_5x5) { index_1 ("0.0186047, 0.0436048, 0.0836047, 0.203605, 0.403605"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.03734, 0.02978, -0.014201, -0.061021, -0.249089", \ "0.068572, 0.083281, 0.071454, 0.044672, -0.087179", \ "0.12057, 0.145265, 0.160477, 0.153379, 0.079668", \ "0.296755, 0.321408, 0.369814, 0.397731, 0.412678", \ "0.590795, 0.613491, 0.662734, 0.6994, 0.804899"); } fall_transition(delay_template_5x5) { index_1 ("0.0186047, 0.0436048, 0.0836047, 0.203605, 0.403605"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.051481, 0.072, 0.1158, 0.1422, 0.2172", \ "0.1062, 0.1314, 0.1824, 0.213, 0.306", \ "0.195, 0.2124, 0.2682, 0.303, 0.4176", \ "0.4632, 0.4644, 0.5022, 0.5442, 0.6804", \ "0.888, 0.888, 0.8934, 0.9162, 1.0566"); } } timing() { related_pin : "EN"; timing_type : three_state_disable; timing_sense : negative_unate; cell_rise(delay_template_5x1) { index_1 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ("0.052455, 0.087424, 0.157364, 0.209818, 0.384667"); } rise_transition(delay_template_5x1) { index_1 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ("0.052455, 0.087424, 0.157364, 0.209818, 0.384667"); } cell_fall(delay_template_5x1) { index_1 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ("0.09424, 0.135387, 0.192558, 0.226641, 0.331784"); } fall_transition(delay_template_5x1) { index_1 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ("0.09424, 0.135387, 0.192558, 0.226641, 0.331784"); } } internal_power() { related_pin : "A"; fall_power(energy_template_5x5) { index_1 ("0.0186047, 0.0436048, 0.0836047, 0.203605, 0.403605"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.103192, 0.080326, 0.014281, 0.1047, 0.434172", \ "0.101882, 0.088224, 0.010258, 0.07087, 0.379852", \ "0.100717, 0.094126, 0.030307, 0.036591, 0.315426", \ "0.097476, 0.095575, 0.058042, 0.01135, 0.201919", \ "0.096551, 0.097929, 0.074327, 0.042678, 0.113631"); } rise_power(energy_template_5x5) { index_1 ("0.0186164, 0.0436164, 0.0836164, 0.203616, 0.403616"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.44505, 0.465527, 0.571316, 0.668858, 1.01007", \ "0.44847, 0.460463, 0.549299, 0.636232, 0.961654", \ "0.450577, 0.458122, 0.527809, 0.602928, 0.902677", \ "0.452697, 0.454258, 0.499982, 0.55395, 0.792169", \ "0.453817, 0.452771, 0.482423, 0.520229, 0.700471"); } } internal_power() { related_pin : "EN"; rise_power(energy_template_5x5) { index_1 ("0.0186164, 0.0436164, 0.0836164, 0.203616, 0.403616"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.149767, 0.168073, 0.236399, 0.289922, 0.480324", \ "0.149165, 0.170713, 0.236598, 0.290711, 0.481841", \ "0.151761, 0.172631, 0.237164, 0.292365, 0.483494", \ "0.153272, 0.175021, 0.239532, 0.294092, 0.485565", \ "0.155067, 0.176832, 0.241418, 0.296884, 0.487316"); } fall_power(energy_template_5x5) { index_1 ("0.0186047, 0.0436048, 0.0836047, 0.203605, 0.403605"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.027381, 0.000426, 0.073369, 0.134651, 0.337276", \ "0.027559, 0.006006, 0.067777, 0.12626, 0.327413", \ "0.027984, 0.004733, 0.064516, 0.122395, 0.321035", \ "0.027156, 0.006521, 0.062465, 0.118152, 0.313884", \ "0.026177, 0.004992, 0.062272, 0.116596, 0.309454"); } } } } /* --------------- * * Design : TBUFX2 * * --------------- */ cell (TBUFX2) { area : 224; cell_leakage_power : 0.0568702; pin(A) { direction : input; capacitance : 0.0531702; rise_capacitance : 0.0527065; fall_capacitance : 0.0531702; } pin(EN) { direction : input; capacitance : 0.0383233; rise_capacitance : 0.0378359; fall_capacitance : 0.0383233; internal_power() { rise_power(passive_energy_template_5x1) { index_1 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ("0, 0, 0, 0, 0"); } fall_power(passive_energy_template_5x1) { index_1 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ("0.28509, 0.355139, 0.498984, 0.611731, 1.00214"); } } } pin(Y) { direction : output; capacitance : 0.00723131; rise_capacitance : 0.00723131; fall_capacitance : 0.00721944; max_capacitance : 0.839062; function : "(!A)"; three_state : "(!EN)"; timing() { related_pin : "A"; timing_sense : negative_unate; cell_fall(delay_template_5x5) { index_1 ("0.0372194, 0.0872194, 0.167219, 0.407219, 0.807219"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.076715, 0.084118, 0.094321, 0.097406, 0.094015", \ "0.11709, 0.126595, 0.143561, 0.151055, 0.160547", \ "0.177904, 0.188852, 0.210104, 0.222716, 0.248739", \ "0.359531, 0.365827, 0.388963, 0.407884, 0.459801", \ "0.652626, 0.657974, 0.677915, 0.695948, 0.762399"); } fall_transition(delay_template_5x5) { index_1 ("0.0372194, 0.0872194, 0.167219, 0.407219, 0.807219"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0858, 0.1032, 0.15, 0.1872, 0.3", \ "0.1362, 0.1464, 0.1932, 0.2274, 0.3498", \ "0.2196, 0.225, 0.258, 0.2898, 0.4152", \ "0.4692, 0.4692, 0.4824, 0.504, 0.6078", \ "0.888, 0.888, 0.8904, 0.8988, 0.9612"); } cell_rise(delay_template_5x5) { index_1 ("0.0372313, 0.0872313, 0.167231, 0.407231, 0.807231"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.099401, 0.115389, 0.143753, 0.166679, 0.233701", \ "0.149795, 0.163017, 0.198605, 0.224773, 0.305224", \ "0.22315, 0.237211, 0.274733, 0.305156, 0.399374", \ "0.443122, 0.455261, 0.491804, 0.524427, 0.633382", \ "0.809407, 0.820445, 0.852334, 0.88064, 0.991465"); } rise_transition(delay_template_5x5) { index_1 ("0.0372313, 0.0872313, 0.167231, 0.407231, 0.807231"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0984, 0.1188, 0.1626, 0.1962, 0.3048", \ "0.168, 0.1788, 0.2178, 0.2496, 0.363", \ "0.276, 0.2802, 0.3078, 0.3378, 0.447", \ "0.6072, 0.6072, 0.6156, 0.6306, 0.7128", \ "1.158, 1.158, 1.1586, 1.1634, 1.2042"); } } timing() { related_pin : "EN"; timing_sense : positive_unate; timing_type : three_state_enable; cell_rise(delay_template_5x5) { index_1 ("0.0372313, 0.0872313, 0.167231, 0.407231, 0.807231"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.096136, 0.112637, 0.133551, 0.137455, 0.139567", \ "0.144511, 0.162967, 0.184621, 0.193597, 0.204492", \ "0.218832, 0.234844, 0.259985, 0.270485, 0.2851", \ "0.437616, 0.458768, 0.476618, 0.485323, 0.510655", \ "0.803742, 0.824872, 0.842612, 0.851602, 0.873426"); } rise_transition(delay_template_5x5) { index_1 ("0.0372313, 0.0872313, 0.167231, 0.407231, 0.807231"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.12, 0.1044, 0.1194, 0.1146, 0.1314", \ "0.171, 0.1698, 0.168, 0.1716, 0.1842", \ "0.2772, 0.276, 0.2724, 0.2724, 0.2814", \ "0.6072, 0.6072, 0.603, 0.6006, 0.6018", \ "1.158, 1.158, 1.1586, 1.155, 1.1514"); } cell_fall(delay_template_5x5) { index_1 ("0.0372194, 0.0872194, 0.167219, 0.407219, 0.807219"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.037439, 0.028422, -0.01399, -0.060808, -0.248974", \ "0.068812, 0.083575, 0.071764, 0.045145, -0.086873", \ "0.120654, 0.145382, 0.160899, 0.15403, 0.08029", \ "0.296766, 0.321403, 0.369785, 0.397677, 0.412731", \ "0.589755, 0.613454, 0.662091, 0.69935, 0.80482"); } fall_transition(delay_template_5x5) { index_1 ("0.0372194, 0.0872194, 0.167219, 0.407219, 0.807219"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.051386, 0.0774, 0.1164, 0.1422, 0.2172", \ "0.1056, 0.1308, 0.1818, 0.2124, 0.3066", \ "0.1944, 0.2118, 0.2676, 0.3024, 0.417", \ "0.4632, 0.4644, 0.5016, 0.543, 0.6786", \ "0.888, 0.888, 0.8934, 0.9162, 1.0554"); } } timing() { related_pin : "EN"; timing_type : three_state_disable; timing_sense : negative_unate; cell_rise(delay_template_5x1) { index_1 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ("0.052455, 0.087424, 0.157364, 0.209818, 0.384667"); } rise_transition(delay_template_5x1) { index_1 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ("0.052455, 0.087424, 0.157364, 0.209818, 0.384667"); } cell_fall(delay_template_5x1) { index_1 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ("0.093579, 0.13382, 0.187658, 0.221575, 0.321724"); } fall_transition(delay_template_5x1) { index_1 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ("0.093579, 0.13382, 0.187658, 0.221575, 0.321724"); } } internal_power() { related_pin : "A"; fall_power(energy_template_5x5) { index_1 ("0.0372194, 0.0872194, 0.167219, 0.407219, 0.807219"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.206392, 0.160627, 0.028715, 0.20956, 0.868512", \ "0.203794, 0.176425, 0.020593, 0.141853, 0.759855", \ "0.201451, 0.188242, 0.060548, 0.073254, 0.630942", \ "0.194957, 0.191149, 0.116051, 0.02267, 0.403868", \ "0.193114, 0.195856, 0.14864, 0.08534, 0.227286"); } rise_power(energy_template_5x5) { index_1 ("0.0372313, 0.0872313, 0.167231, 0.407231, 0.807231"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.890081, 0.931027, 1.14258, 1.33767, 2.0201", \ "0.896904, 0.920914, 1.09856, 1.27242, 1.92327", \ "0.901126, 0.916224, 1.0556, 1.20582, 1.80532", \ "0.90537, 0.908499, 0.999949, 1.10789, 1.58431", \ "0.907609, 0.905515, 0.964827, 1.04042, 1.4009"); } } internal_power() { related_pin : "EN"; rise_power(energy_template_5x5) { index_1 ("0.0372313, 0.0872313, 0.167231, 0.407231, 0.807231"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.296874, 0.334665, 0.465475, 0.581634, 0.965345", \ "0.297407, 0.339405, 0.472578, 0.583168, 0.968954", \ "0.300652, 0.336319, 0.474833, 0.585379, 0.972432", \ "0.302877, 0.346556, 0.476963, 0.588082, 0.975624", \ "0.305037, 0.348694, 0.479497, 0.591584, 0.97741"); } fall_power(energy_template_5x5) { index_1 ("0.0372194, 0.0872194, 0.167219, 0.407219, 0.807219"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.056852, 0.005349, 0.147184, 0.271491, 0.68152", \ "0.057367, 0.013421, 0.135852, 0.254239, 0.661972", \ "0.058412, 0.01095, 0.129586, 0.246448, 0.648837", \ "0.056676, 0.014518, 0.124877, 0.237779, 0.634648", \ "0.056276, 0.011181, 0.125738, 0.234929, 0.625799"); } } } } /* ---------------- * * Design : XNOR2X1 * * ---------------- */ cell (XNOR2X1) { area : 224; cell_leakage_power : 0.0845795; pin(A) { direction : input; capacitance : 0.0435905; rise_capacitance : 0.0435905; fall_capacitance : 0.0435166; } pin(B) { direction : input; capacitance : 0.0524659; rise_capacitance : 0.0522323; fall_capacitance : 0.0524659; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.413242; function : "(!(A^B))"; timing() { related_pin : "A"; timing_sense : non_unate; cell_rise(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.122672, 0.134136, 0.157188, 0.16667, 0.178502", \ "0.166322, 0.179567, 0.201718, 0.215511, 0.229878", \ "0.237559, 0.251304, 0.273205, 0.287008, 0.304247", \ "0.453679, 0.468398, 0.486993, 0.497346, 0.525865", \ "0.817445, 0.837677, 0.854341, 0.863129, 0.884568"); } rise_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1092, 0.102, 0.1026, 0.1074, 0.1074", \ "0.1758, 0.1734, 0.1668, 0.1692, 0.177", \ "0.2862, 0.285, 0.276, 0.2742, 0.282", \ "0.6156, 0.6162, 0.6102, 0.6072, 0.606", \ "1.167, 1.167, 1.167, 1.1628, 1.1574"); } cell_fall(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.12246, 0.144057, 0.198046, 0.224615, 0.297657", \ "0.158576, 0.18501, 0.236012, 0.265766, 0.34284", \ "0.215829, 0.243984, 0.292198, 0.32574, 0.405693", \ "0.388115, 0.419023, 0.46212, 0.494234, 0.584898", \ "0.67894, 0.709262, 0.754666, 0.784086, 0.870071"); } fall_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0936, 0.0882, 0.0846, 0.087, 0.0918", \ "0.147, 0.141, 0.1356, 0.1362, 0.1422", \ "0.228, 0.2262, 0.2178, 0.2154, 0.2202", \ "0.477, 0.477, 0.4716, 0.468, 0.4674", \ "0.8964, 0.8964, 0.897, 0.8922, 0.8868"); } } timing() { related_pin : "B"; timing_sense : non_unate; cell_rise(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.148249, 0.161582, 0.180211, 0.191581, 0.199407", \ "0.195238, 0.208939, 0.228777, 0.23772, 0.247217", \ "0.267251, 0.283307, 0.30294, 0.310666, 0.32178", \ "0.487144, 0.50224, 0.525354, 0.527584, 0.542364", \ "0.852816, 0.868304, 0.891146, 0.896413, 0.907998"); } rise_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.108, 0.111, 0.1146, 0.123, 0.1296", \ "0.177, 0.1776, 0.1788, 0.183, 0.189", \ "0.2856, 0.285, 0.288, 0.2886, 0.294", \ "0.6156, 0.6156, 0.6156, 0.6162, 0.6198", \ "1.1664, 1.1664, 1.1664, 1.1664, 1.1676"); } cell_fall(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.138356, 0.164181, 0.203649, 0.229776, 0.296225", \ "0.178593, 0.203332, 0.242689, 0.268427, 0.338395", \ "0.239262, 0.264316, 0.303597, 0.329232, 0.399082", \ "0.415903, 0.444943, 0.480073, 0.50553, 0.575885", \ "0.709428, 0.737467, 0.776009, 0.801086, 0.868476"); } fall_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0948, 0.0978, 0.105, 0.1056, 0.1128", \ "0.1458, 0.1458, 0.15, 0.1494, 0.1608", \ "0.2268, 0.2274, 0.2298, 0.2298, 0.2352", \ "0.4758, 0.4758, 0.4764, 0.4776, 0.4812", \ "0.8958, 0.8958, 0.8958, 0.8958, 0.8976"); } } internal_power() { related_pin : "A"; rise_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.176339, 0.212627, 0.343655, 0.46314, 0.874668", \ "0.166374, 0.212124, 0.344345, 0.460558, 0.858811", \ "0.157822, 0.207839, 0.341546, 0.456905, 0.850535", \ "0.148254, 0.199135, 0.334008, 0.449413, 0.845296", \ "0.1422, 0.190283, 0.327241, 0.440273, 0.838154"); } fall_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.543678, 0.594587, 0.74769, 0.862867, 1.27447", \ "0.522047, 0.586707, 0.746389, 0.860343, 1.26799", \ "0.514338, 0.580995, 0.735615, 0.859754, 1.2608", \ "0.506836, 0.568046, 0.724235, 0.843447, 1.25031", \ "0.501893, 0.562084, 0.713302, 0.832769, 1.23805"); } } internal_power() { related_pin : "B"; rise_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.220702, 0.253713, 0.395656, 0.507623, 0.91275", \ "0.221657, 0.259022, 0.394993, 0.504711, 0.905113", \ "0.222337, 0.260683, 0.392106, 0.505526, 0.900384", \ "0.222792, 0.26222, 0.398756, 0.506637, 0.895323", \ "0.222654, 0.262338, 0.398927, 0.505337, 0.89301"); } fall_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.60089, 0.647689, 0.79509, 0.913318, 1.32612", \ "0.600574, 0.652003, 0.793614, 0.917726, 1.32106", \ "0.602594, 0.653287, 0.800245, 0.912524, 1.31313", \ "0.604516, 0.660143, 0.79977, 0.915825, 1.31046", \ "0.603772, 0.661082, 0.801002, 0.916516, 1.30907"); } } } } /* --------------- * * Design : XOR2X1 * * --------------- */ cell (XOR2X1) { area : 224; cell_leakage_power : 0.0854615; pin(A) { direction : input; capacitance : 0.0435889; rise_capacitance : 0.0435889; fall_capacitance : 0.0434863; } pin(B) { direction : input; capacitance : 0.0524749; rise_capacitance : 0.0522388; fall_capacitance : 0.0524749; } pin(Y) { direction : output; capacitance : 0; rise_capacitance : 0; fall_capacitance : 0; max_capacitance : 0.413518; function : "(A^B)"; timing() { related_pin : "A"; timing_sense : non_unate; cell_rise(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.122933, 0.134344, 0.157356, 0.166768, 0.178571", \ "0.166602, 0.179836, 0.201919, 0.215673, 0.229997", \ "0.237832, 0.251535, 0.273395, 0.287252, 0.304389", \ "0.453374, 0.46857, 0.487147, 0.497486, 0.525974", \ "0.817112, 0.837843, 0.854446, 0.86324, 0.884739"); } rise_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1092, 0.1026, 0.1032, 0.108, 0.1074", \ "0.1758, 0.1734, 0.1668, 0.1692, 0.177", \ "0.2856, 0.285, 0.276, 0.2742, 0.2814", \ "0.6156, 0.6162, 0.6102, 0.6072, 0.606", \ "1.167, 1.167, 1.167, 1.1628, 1.1574"); } cell_fall(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.122337, 0.146792, 0.198101, 0.224566, 0.297637", \ "0.15842, 0.18488, 0.236171, 0.26573, 0.34282", \ "0.215693, 0.243863, 0.292092, 0.325723, 0.405691", \ "0.38858, 0.419048, 0.46219, 0.494294, 0.584956", \ "0.679087, 0.70933, 0.754762, 0.784192, 0.870189"); } fall_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.0936, 0.0882, 0.0846, 0.087, 0.0918", \ "0.147, 0.141, 0.1338, 0.1362, 0.1428", \ "0.2286, 0.2262, 0.2178, 0.2154, 0.2202", \ "0.477, 0.477, 0.4716, 0.4686, 0.468", \ "0.897, 0.8964, 0.897, 0.8928, 0.8874"); } } timing() { related_pin : "B"; timing_sense : non_unate; cell_rise(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.144619, 0.156874, 0.176484, 0.186124, 0.196814", \ "0.191768, 0.205607, 0.225107, 0.23382, 0.244483", \ "0.263881, 0.28074, 0.299368, 0.307457, 0.318682", \ "0.483447, 0.505972, 0.521648, 0.527949, 0.539474", \ "0.849092, 0.872211, 0.887562, 0.894031, 0.90509"); } rise_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.1104, 0.1134, 0.1164, 0.1236, 0.132", \ "0.1776, 0.1782, 0.1788, 0.1818, 0.1926", \ "0.285, 0.285, 0.288, 0.2886, 0.294", \ "0.6144, 0.6144, 0.615, 0.6156, 0.6186", \ "1.1652, 1.1652, 1.1652, 1.1658, 1.1664"); } cell_fall(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.145193, 0.167445, 0.207025, 0.23445, 0.300689", \ "0.183018, 0.208158, 0.246245, 0.272205, 0.341196", \ "0.24309, 0.268668, 0.307056, 0.331972, 0.401932", \ "0.419484, 0.444925, 0.483225, 0.508163, 0.578534", \ "0.712649, 0.737261, 0.77892, 0.803399, 0.871081"); } fall_transition(delay_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.093, 0.0954, 0.1008, 0.102, 0.1164", \ "0.1446, 0.1446, 0.1476, 0.1482, 0.1602", \ "0.2268, 0.2268, 0.2292, 0.231, 0.2352", \ "0.4764, 0.477, 0.477, 0.4782, 0.4818", \ "0.897, 0.897, 0.897, 0.897, 0.8988"); } } internal_power() { related_pin : "A"; rise_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.16223, 0.19924, 0.330891, 0.450355, 0.85608", \ "0.15295, 0.198387, 0.331072, 0.447385, 0.845471", \ "0.144331, 0.194114, 0.328312, 0.443791, 0.837433", \ "0.133885, 0.18547, 0.320769, 0.436208, 0.832024", \ "0.128526, 0.177405, 0.314082, 0.427065, 0.824831"); } fall_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.559534, 0.610414, 0.765392, 0.879553, 1.29246", \ "0.540068, 0.604521, 0.758941, 0.877728, 1.28568", \ "0.532821, 0.599493, 0.753499, 0.877692, 1.2785", \ "0.523761, 0.587193, 0.743433, 0.862109, 1.269", \ "0.519548, 0.58142, 0.732494, 0.851847, 1.25709"); } } internal_power() { related_pin : "B"; rise_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.119288, 0.152651, 0.292972, 0.406205, 0.812813", \ "0.121522, 0.153145, 0.29344, 0.402596, 0.804257", \ "0.122482, 0.154474, 0.290082, 0.404108, 0.799275", \ "0.123254, 0.155663, 0.297868, 0.407272, 0.794032", \ "0.123314, 0.156069, 0.298135, 0.407284, 0.791857"); } fall_power(energy_template_5x5) { index_1 ("0.015, 0.04, 0.08, 0.2, 0.4"); index_2 ("0.06, 0.18, 0.42, 0.6, 1.2"); values ( \ "0.696383, 0.740188, 0.886317, 1.00972, 1.42237", \ "0.698037, 0.748875, 0.88776, 1.01308, 1.41685", \ "0.699985, 0.750658, 0.895898, 1.0131, 1.40899", \ "0.701806, 0.752479, 0.895906, 1.01155, 1.40644", \ "0.700092, 0.753668, 0.896398, 1.01464, 1.40504"); } } } } cell (PADFC) { area : 27000; dont_touch : true; } cell (PADNC) { area : 27000; dont_touch : true; } cell (PADVDD) { area : 27000; dont_touch : true; } cell (PADGND) { area : 27000; dont_touch : true; } } qflow-1.1.23/tech/osu035/osu035.prm0000755000175000001440000000160512526236535015213 0ustar timusers; ; configuration file for osu035 (0.35um process) ; Note that these values are totally bogus! ; lambda 0.01 ; length scaling, microns (1 lambda = 1 centimicron) capga .0115 ; gate capacitance, pF/micron^2 capda 0.0012 capdp 0.0013 cappda 0.00260 cappdp 0.00090 lowthresh 0.5 ; logic low threshold as a normalized voltage highthresh 0.5 ; logic high threshold as a normalized voltage cntpullup 0 ; irrelevant, cmos technology; no depletion transistors diffperim 0 ; don't include diffusion perimeters for sidewall cap. subparea 0 ; poly over transistor won't count as part pf bulk-poly cap. diffext 0 ; diffusion extension for each transistor resistance n-channel dynamic-low 2 0.4 1844.70 resistance p-channel dynamic-high 6.2 0.4 1489.10 resistance n-channel static 2 0.4 2203.94 resistance p-channel static 6.2 0.4 1693.37 qflow-1.1.23/tech/osu035/Makefile0000664000175000001440000000247312533671314015074 0ustar timusers# # qflow project included technology osu035 files # # Main compiler arguments CFLAGS = -g -O2 DEFS = -DPACKAGE_NAME=\"\" -DPACKAGE_TARNAME=\"\" -DPACKAGE_VERSION=\"\" -DPACKAGE_STRING=\"\" -DPACKAGE_BUGREPORT=\"\" -DPACKAGE_URL=\"\" -DSTDC_HEADERS=1 -DHAVE_SETENV=1 -DHAVE_PUTENV=1 -DTCLSH_PATH=\"/bin/tclsh\" -DQFLOW_MAGIC_PATH=\"/usr/local/bin/magic\" -DQFLOW_QROUTER_PATH=\"/usr/local/bin/qrouter\" -DQFLOW_GRAYWOLF_PATH=\"/usr/local/bin/graywolf\" -DQFLOW_YOSYS_PATH=\"/usr/local/bin/yosys\" LIBS = LDFLAGS = INSTALL = /bin/install -c QFLOW_LIB_DIR = /usr/local/share/qflow TECH_FILES = osu035.par osu035_stdcells.lef osu035.sh TECH_FILES += osu035_stdcells.sp osu035.magicrc osu035.prm TECH_FILES += SCN4M_SUBM.20.tech osu035_stdcells.lib TECH_FILES += osu035_stdcells.v TECHINSTALL = ${QFLOW_LIB_DIR}/tech # Substitute the target qflow tech directory name in .magicrc so that magic # can find the OSU035 techfile all: osu035.magicrc.in $(RM) -f osu035.magicrc cat osu035.magicrc.in | sed -e \ '/QFLOW_LIB_DIR/s#QFLOW_LIB_DIR#$(QFLOW_LIB_DIR)#' \ > osu035.magicrc install: ${TECH_FILES} @echo "Installing osu035 tech files" $(INSTALL) -d $(DESTDIR)$(TECHINSTALL)/osu035 for target in $(TECH_FILES); do \ $(INSTALL) $$target $(DESTDIR)$(TECHINSTALL)/osu035 ;\ done clean: $(RM) -f osu035.magicrc uninstall: qflow-1.1.23/tech/osu035/SCN4M_SUBM.20.tech0000644000175000001440000051673712526236535016212 0ustar timuserstech format 32 scmos end version version 2001a description "SCMOS: Submit as technology.lambda: SCN4M_SUBM.20 [to process: TSMC35]" end planes well,w implant,i select,s active,a metal1,m1 metal2,m2 metal3,m3 metal4,m4 oxide,ox comment xp contact via1,v1 via2,v2 via3,v3 fill end types well nwell,nw active nwr well pwell,pw implant n_field_implant,nfi implant p_field_implant,pfi select nselect,ns select pselect,ps active ntransistor,nfet active ptransistor,pfet active diffusion,diff active transistor,fet active ndiffusion,ndif,green active pdiffusion,pdif,brown active ndcontact,ndc active pdcontact,pdc active psubstratepdiff,pohmicdiff,pod,ppdiff,ppd,psd active nsubstratendiff,nohmicdiff,nod,nndiff,nnd,nsd active psubstratepcontact,pohmiccontact,poc,pwcontact,pwc,psc active nsubstratencontact,nohmiccontact,noc,nwcontact,nwc,nsc active nwsd active nwsc active polysilicon,red,poly,p active polycontact,pcontact,polycut,pc contact genericcontact,gcontact,gc metal1 metal1,m1,blue metal1 pseudo_rmetal1,prm1 metal1 rmetal1,rm1 metal1 fillm1,fm1 metal1 m2contact,m2cut,m2c,via1,v1,via metal1 pm12contact,pm12c metal1 pdm12contact,pdm12c metal1 psm12contact,psm12c,pom12c,pwm12c metal1 ndm12contact,ndm12c metal1 nsm12contact,nsm12c,nom12c,nwm12c metal1 nwsm12contact,nwsm12c metal2 metal2,m2,purple metal2 pseudo_rmetal2,prm2 metal2 rmetal2,rm2 metal2 fillm2,fm2 via1 gv1 metal2 m3contact,m3cut,m3c,via2,v2 metal2 m123contact,m123c metal3 metal3,m3,cyan metal3 pseudo_rmetal3,prm3 metal3 rmetal3,rm3 metal3 fillm3,fm3 via2 gv2 metal3 m234contact,m234c metal3 m4contact,m4cut,m4c,via3,v3 metal4 metal4,m4,yellow metal4 pseudo_rmetal4,prm4 metal4 rmetal4,rm4 metal4 fillm4,fm4 via3 gv3 metal4 pad oxide glass active silicide_block,sb active poly_resist,pres active pseudo_rpoly,prp active rpoly,rp active pseudo_rndiffusion,prnd active rndiffusion,rndiff,rnd active pseudo_rpdiffusion,prpd active rpdiffusion,rpdiff,rpd active pseudo_rnwell,prnwell,prnw active rnwell,rnw active pseudo_nwr,pnwr implant filln,fn fill filla,fa fill fillb,fb active fillp,fp active fillapm,fapm active activen_resist,anres active activep_resist,apres xp xp xp m1p xp m2p xp m3p xp m4p comment comment comment bb end contact pc poly metal1 ndc ndiff metal1 pdc pdiff metal1 nsc nsd metal1 nwsc nwsd metal1 psc psd metal1 m2c metal1 metal2 m3c metal2 metal3 m4c metal3 metal4 # pm12c poly metal1 metal2 # pdm12c pdiff metal1 metal2 # psm12c psd metal1 metal2 # ndm12c ndiff metal1 metal2 # nsm12c nsd metal1 metal2 # nwsm12c nwsd metal1 metal2 # m123c metal1 metal2 metal3 # m234c metal2 metal3 metal4 stackable pc m2c pm12c stackable pdc m2c pdm12c stackable psc m2c psm12c stackable ndc m2c ndm12c stackable nsc m2c nsm12c stackable nwsc m2c nwsm12c stackable m2c m3c m123c stackable m3c m4c m234c end styles styletype mos nwr 54 pnwr 53 nwsd 3 nwsd 54 nwsc 3 nwsc 20 nwsc 32 nwsc 54 nwell 12 pwell 13 nfi 53 pfi 54 nselect 43 pselect 44 diff 25 tran 2 tran 4 ndiff 2 pdiff 4 nsd 3 psd 5 nfet 6 nfet 7 pfet 8 pfet 9 ndc 2 ndc 20 ndc 32 pdc 4 pdc 20 pdc 32 nsc 3 nsc 20 nsc 32 psc 5 psc 20 psc 32 poly 1 pcontact 1 pcontact 20 pcontact 32 gc 32 metal1 20 rm1 20 rm1 48 prm1 48 m1p 20 m1p 34 fm1 20 fm1 34 fp 1 fp 34 fa 32 fb 45 fb 34 fn 45 fn 34 fapm 1 fapm 20 fapm 21 fapm 34 gv1 55 m2contact 20 m2contact 21 m2contact 55 pm12contact 1 pm12contact 20 pm12contact 21 pm12contact 32 pm12contact 55 ndm12c 2 ndm12c 20 ndm12c 21 ndm12c 32 ndm12c 55 nsm12c 3 nsm12c 20 nsm12c 21 nsm12c 32 nsm12c 55 nwsm12c 3 nwsm12c 20 nwsm12c 21 nwsm12c 32 nwsm12c 55 nwsm12c 54 pdm12c 4 pdm12c 20 pdm12c 21 pdm12c 32 pdm12c 55 psm12c 5 psm12c 20 psm12c 21 psm12c 32 psm12c 55 metal2 21 rm2 21 rm2 48 prm2 48 m2p 21 m2p 34 fm2 21 fm2 34 gv2 56 m3contact 21 m3contact 22 m3contact 56 m123c 20 m123c 21 m123c 22 m123c 55 m123c 56 metal3 22 rm3 22 rm3 48 prm3 48 m3p 22 m3p 34 fm3 22 fm3 34 gv3 57 m4contact 22 m4contact 23 m4contact 57 m234contact 21 m234contact 22 m234contact 23 m234contact 56 m234contact 57 metal4 23 rm4 23 rm4 48 prm4 48 m4p 23 m4p 34 fm4 23 fm4 34 pad 22 pad 23 pad 34 pad 38 glass 34 xp 25 xp 34 sb 10 pres 47 pres 48 rp 47 rp 48 prp 48 anres 2 anres 48 rnd 2 rnd 48 prnd 48 apres 4 apres 53 rpd 4 rpd 53 prpd 53 rnw 12 rnw 53 prnw 54 comment 45 bb 32 error_p 42 error_s 42 error_ps 42 magnet 54 rotate 57 fence 59 end compose compose nfet poly ndiff compose pfet poly pdiff paint diff nselect ndiff paint diff pselect pdiff compose tran poly diff paint tran nselect nfet paint tran pselect pfet paint psd ns ndiff paint nsd ps pdiff paint ndiff ps psd paint pdiff ns nsd paint pad m1 pad paint pad m2 pad paint pad m2c pad paint pfi nwell nfi paint nfi pwell pfi paint anres nwell apres paint apres pwell anres paint ndc nwell pdc paint nfet nwell pfet paint ndiff nwell pdiff paint psd nwell nsd paint psc nwell nsc paint pdc pwell ndc paint pfet pwell nfet paint pdiff pwell ndiff paint nsd pwell psd paint nsc pwell psc paint pad m3 pad paint pad m4 pad compose pres poly sb paint sb poly pres paint poly sb pres erase pres sb poly compose anres ndiff sb paint sb ndiff anres paint ndiff sb anres erase anres sb ndiff compose apres pdiff sb paint sb pdiff apres paint pdiff sb apres erase apres sb pdiff #CRE/CRM compose rm1 prm1 m1 compose rm2 prm2 m2 compose rm3 prm3 m3 compose rm4 prm4 m4 compose rp prp poly compose rnd prnd ndiff compose rpd prpd pdiff paint nwell rnw space paint nwell nwr space paint nwell prnw space paint poly fp fp paint m1 fm1 fm1 paint m2 fm2 fm2 paint m3 fm3 fm3 paint m4 fm4 fm4 end connect nwell,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,nsd,nwsd nwell,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,nsd,nwsd pwell,psc/a,psm12c/a,psd pwell,psc/a,psm12c/a,psd m1,fm1,fapm,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1 m1,fm1,fapm,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1 m2,fm2,fapm,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m123c/m2,m234c/m2,m3c/m2,m123c/m2,m234c/m2 m2,fm2,fapm,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m123c/m2,m234c/m2,m3c/m2,m123c/m2,m234c/m2 m3,fm3,fapm,m3c/m3,m123c/m3,m234c/m3,m4c/m3,m234c/m3,m4c/m3,m234c/m3 m3,fm3,fapm,m3c/m3,m123c/m3,m234c/m3,m4c/m3,m234c/m3,m4c/m3,m234c/m3 m4,fm4,fapm,m4c/m4,m234c/m4 m4,fm4,fapm,m4c/m4,m234c/m4 ndiff,nsd,nwsd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdiff,psd,pdc/a,pdm12c/a,psc/a,psm12c/a ndiff,nsd,nwsd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdiff,psd,pdc/a,pdm12c/a,psc/a,psm12c/a poly,fp,nfet,pfet,fet,fapm,pc/a,pm12c/a poly,fp,nfet,pfet,fet,fapm,pc/a,pm12c/a gc poly,fp,ndiff,pdiff,nsd,nwsd,psd,m1,fm1,fapm,m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1 gv1 m1,fm1,fapm,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2,fm2,fapm,m3c/m2,m123c/m2,m234c/m2 gv2 m2,fm2,fapm,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m123c/m2,m234c/m2,m3,fm3,fapm,m4c/m3,m234c/m3 gv3 m3,fm3,fapm,m3c/m3,m123c/m3,m234c/m3,m4c/m3,m234c/m3,m4,fm4,fapm pad m1,fm1,m2,fm2,m3,fm3,m4,fm4 rm1 prm1 rm2 prm2 rm3 prm3 rm4 prm4 rnw prnw nwr pnwr rp prp rnd prnd rpd prpd pres sb anres sb apres sb end cifoutput style lambda=0.20(p) scalefactor 20 10 layer CWN nwell,rnw,nwr,nwsd,nwsc bloat-or pdiff,apres,rpd,pdc/a,pdm12c/a,pfet * 120 bloat-or nsd,nsc/a,nsm12c/a * 60 bloat-or nfi * 80 grow 60 shrink 60 labels nwell,rnw,nwr,nwsd,nwsc calma 42 0 layer CWNR nwsd,nwsc,nwr grow 140 calma 91 0 layer CWND nwr labels nwr calma 92 0 layer CAA nwsd,nwsc,nwr grow 100 labels nwsd,nwsc calma 43 0 layer CSN bloat-or nwsd,nwsc * 80 nwr 0 calma 43 0 templayer TNWR bloat-or nwr * 100 nwsd,nwsc 40 templayer TCSB nwsd,nwsc grow 40 and-not TNWR layer CSB nwsd,nwsc,nwr grow 140 and-not TCSB calma 29 0 layer CRNW pnwr labels pnwr calma 93 0 layer CWP pwell bloat-or ndiff,anres,rnd,ndc/a,ndm12c/a,nfet * 120 bloat-or psd,psc/a,psm12c/a * 60 bloat-or pfi * 80 grow 60 shrink 60 and-not CWN labels pwell calma 41 0 templayer TNS ns templayer TPS ps #we give priority to selects autogenerated around diffusions (vrs. ohmics) #XDP = (pdiff*40) Or ps #XDN = (ndiff*40) Or ns #FSP = ((pdiff*40,psc*40) Or XDP And-Not XDN Or ps shrink-grow #FSN = ((ndiff*40,nsc*40) Or XDN And-Not FDP Or ns shrink-grow #CSN = FSN #CSP = FSP #diffusion auto-nselect (will have priority) templayer XDN bloat-or ndiff,anres,rnd,ndc/a,ndm12c/a * 40 psd,psc/a,psm12c/a 0 or TNS #diffusion auto-pselect (will have priority) templayer XDP bloat-or pdiff,apres,rpd,pdc/a,pdm12c/a * 40 nsd,nsc/a,nsm12c/a 0 or TPS #final pselect templayer FSP bloat-or pdiff,apres,rpd,pfet,psd,pdc/a,pdm12c/a,psc/a,psm12c/a,pfet * 40 ndiff,anres,rnd,ndc/a,ndm12c/a,nsd,nsc/a,nsm12c/a,nfet 0 or XDP #give diff nselect priority and-not XDN or TPS shrink 20 grow 20 grow 20 shrink 20 #final nselect templayer FSN bloat-or ndiff,anres,rnd,nfet,nsd,nwsd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,nfet * 40 pdiff,apres,rpd,pdc/a,pdm12c/a,psd,psc/a,psm12c/a,pfet 0 and-not nwr or XDN #never conflict with final pselect and-not FSP #drawn select always goes or TNS shrink 20 grow 20 grow 20 shrink 20 layer CSN FSN calma 45 0 layer CSP FSP calma 44 0 layer CAA diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,pfet,pfet,fet labels diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,pfet,pfet,fet calma 43 0 layer CCA nwsc/m1,nwsm12c/m1 squares 40 40 60 calma 48 0 layer CCA ndc/m1,ndm12c/m1,nsc/m1,nsm12c/m1 squares 20 40 60 calma 48 0 layer CCA pdc/m1,pdm12c/m1,psc/m1,psm12c/m1 squares 20 40 60 calma 48 0 layer CPG poly,pres,rp,nfet,pfet,fet,pc/a,pm12c/a labels poly,pres,rp,nfet,pfet,fet,pc/a,pm12c/a calma 46 0 layer CCP pc/m1,pm12c/m1 squares 20 40 60 calma 47 0 layer CCC gc squares 0 40 60 calma 25 0 layer CV1 m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1 squares 20 40 60 calma 50 0 layer CV1 gv1 squares 0 40 60 calma 50 0 layer CV2 m3c/m2,m123c/m2,m234c/m2 squares 20 40 60 calma 61 0 layer CV2 gv2 squares 0 40 60 calma 61 0 layer CV3 m4c/m3,m234c/m3 squares 20 40 60 calma 30 0 layer CV3 gv3 squares 0 40 60 calma 30 0 templayer XPAD1 pad shrink 120 templayer XPAD2 XPAD1 shrink 120 layer CM4 pad labels pad calma 31 0 layer CV3 XPAD2 squares 40 40 200 calma 30 0 layer CM3 pad labels pad calma 62 0 layer CV2 XPAD2 squares 160 40 200 calma 61 0 layer CM2 pad labels pad calma 51 0 layer CV1 XPAD2 squares 40 40 200 calma 50 0 layer CM1 pad calma 49 0 layer CM1 m1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1 labels m1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1 calma 49 0 layer CM2 m2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m123c/m2,m234c/m2,m3c/m2,m123c/m2,m234c/m2 labels m2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m123c/m2,m234c/m2,m3c/m2,m123c/m2,m234c/m2 calma 51 0 layer CMFP m1p labels m1p calma 81 0 layer CMSP m2p labels m2p calma 82 0 layer 100 fp labels fp calma 100 0 layer 101 fm1 labels fm1 calma 101 0 layer 102 fm2 labels fm2 calma 102 0 layer 103 fm3 labels fm3 calma 103 0 layer 104 fm4 labels fm4 calma 104 0 layer 109 fa or fb squares 0 200 80 labels fa calma 109 0 layer 119 fn calma 119 0 layer 110 fapm labels fapm calma 110 0 # layer CPG fp layer CPG fp,fapm squares 0 200 80 labels fp calma 46 0 # layer CM1 fm1 layer CM1 fm1,fapm squares 0 200 80 labels fm1 calma 49 0 # layer CM2 fm2 layer CM2 fm2,fapm squares 0 200 80 labels fm2 calma 51 0 # layer CM3 fm3 layer CM3 fm3,fapm squares 0 200 80 labels fm3 calma 62 0 layer CM3 m3,rm3,m3c/m3,m123c/m3,m234c/m3,m4c/m3,m234c/m3,m4c/m3,m234c/m3 labels m3,rm3,m3c/m3,m123c/m3,m234c/m3,m4c/m3,m234c/m3,m4c/m3,m234c/m3 calma 62 0 layer CMTP m3p labels m3p calma 83 0 layer CM4 m4,rm4,m4c/m4,m234c/m4 labels m4,rm4,m4c/m4,m234c/m4 calma 31 0 layer CMQP m4p labels m4p calma 84 0 # layer CM4 fm4 layer CM4 fm4,fapm squares 0 200 80 labels fm4 calma 31 0 layer COG pad shrink 500 labels pad calma 52 0 layer COG glass labels glass calma 52 0 layer CFI nfi,pfi labels nfi,pfi calma 27 0 layer CSB sb,pres,anres,apres labels sb,pres,anres,apres calma 29 0 #CRE/CRM layer CRW rnw,prnw labels rnw,prnw calma 65 0 layer CRG rp,prp,pres labels rp,prp,pres calma 67 0 layer CRD rnd,rpd,prnd,prpd,anres,apres labels rnd,rpd,prnd,prpd,anres,apres calma 66 0 layer CRE rnw,rp,rnd,rpd,pres,anres,apres labels rnw,rp,rnd,rpd,pres,anres,apres calma 64 0 layer CRF rm1,prm1 labels rm1,prm1 calma 71 0 layer CRS rm2,prm2 labels rm2,prm2 calma 72 0 layer CRT rm3,prm3 labels rm3,prm3 calma 73 0 layer CRQ rm4,prm4 labels rm4,prm4 calma 74 0 #CRE/CRM layer CRM rm1,prm1,rm2,prm2,rm3,prm3,rm4,prm4 #CRE/CRM calma 70 0 layer CX comment labels comment calma 63 0 layer XP pad,xp labels pad,xp calma 26 0 style fill-only scalefactor 20 10 layer 100 fp calma 100 0 layer 101 fm1 calma 101 0 layer 102 fm2 calma 102 0 layer 103 fm3 calma 103 0 layer 104 fm4 calma 104 0 layer 109 fa or fb calma 109 0 layer 119 fn calma 119 0 style fapm-boxes # this output style creates fill boxes automatically (to meet minimum # density requirements for poly and metal layers) 5 microns outside of # drawn layout IF: 1. you have a flattened version of your chip, # 2. over which you paint the special fill layer 'fa', preferably with # a size that is a multiple of 10 + n * (10 + 4), 3. set 'cif # ostype fapm-boxes' and cif out to a file (this actually creates the # fill boxes on cif/strm layer '110' using the magic 'squares' # command), 4. cif in the resulting file (which creates boxes on magic # layer 'fapm') and place this cell onto your chip (and verify absence # of drc errors or shorts), then 5. cif out under your regular cif out # style, where the 'fapm' layer creates fill boxes on poly and all # metal layers. scalefactor 20 10 templayer CRIT fapm,fn,diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,pfet,pfet,fet,poly,pres,rp,nfet,pfet,fet,pc/a,pm12c/a or fm1,m1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1 or fm2,m2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m123c/m2,m234c/m2,m3c/m2,m123c/m2,m234c/m2 or fm3,m3,rm3,m3c/m3,m123c/m3,m234c/m3,m4c/m3,m234c/m3,m4c/m3,m234c/m3 or fm4,m4,rm4,m4c/m4,m234c/m4 or glass,pad grow 500 and fa layer 110 fa squares 0 200 80 and-not CRIT shrink 90 grow 90 or fapm labels fapm calma 110 0 style fapm-stripes scalefactor 20 10 # this output style creates the above layer 110 as stripes for reduced size # HOWEVER it requires each 'fa' box to first be an exact multiple as above # and then *replacing* the left side (1-lambda wide) stripe of each 'fa' box # to be a 1-lambda wide layer 'fb' box -- else you won't get strips! templayer CRIT fapm,fn,diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,pfet,pfet,fet,poly,pres,rp,nfet,pfet,fet,pc/a,pm12c/a or fm1,m1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1 or fm2,m2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m123c/m2,m234c/m2,m3c/m2,m123c/m2,m234c/m2 or fm3,m3,rm3,m3c/m3,m123c/m3,m234c/m3,m4c/m3,m234c/m3,m4c/m3,m234c/m3 or fm4,m4,rm4,m4c/m4,m234c/m4 or glass,pad grow 500 and fa templayer FB fa or fb squares 0 200 80 and-not CRIT layer 110 fa squares 0 200 80 and-not CRIT or FB shrink 90 grow 90 or fapm labels fapm calma 110 0 style lambda=0.20(cp) scalefactor 20 10 layer CWN nwell,rnw,nwr,nwsd,nwsc bloat-or pdiff,apres,rpd,pdc/a,pdm12c/a,pfet * 120 bloat-or nsd,nsc/a,nsm12c/a * 60 bloat-or nfi * 80 grow 60 shrink 60 labels nwell,rnw,nwr,nwsd,nwsc calma 42 0 layer CWNR nwsd,nwsc,nwr grow 140 calma 91 0 layer CWND nwr labels nwr calma 92 0 layer CAA nwsd,nwsc,nwr grow 100 labels nwsd,nwsc calma 43 0 layer CSN bloat-or nwsd,nwsc * 80 nwr 0 calma 43 0 templayer TNWR bloat-or nwr * 100 nwsd,nwsc 40 templayer TCSB nwsd,nwsc grow 40 and-not TNWR layer CSB nwsd,nwsc,nwr grow 140 and-not TCSB calma 29 0 layer CRNW pnwr labels pnwr calma 93 0 layer CWP pwell bloat-or ndiff,anres,rnd,ndc/a,ndm12c/a,nfet * 120 bloat-or psd,psc/a,psm12c/a * 60 bloat-or pfi * 80 grow 60 shrink 60 and-not CWN labels pwell calma 41 0 templayer TNS ns templayer TPS ps #we give priority to selects autogenerated around diffusions (vrs. ohmics) #XDP = (pdiff*40) Or ps #XDN = (ndiff*40) Or ns #FSP = ((pdiff*40,psc*40) Or XDP And-Not XDN Or ps shrink-grow #FSN = ((ndiff*40,nsc*40) Or XDN And-Not FDP Or ns shrink-grow #CSN = FSN #CSP = FSP #diffusion auto-nselect (will have priority) templayer XDN bloat-or ndiff,anres,rnd,ndc/a,ndm12c/a * 40 psd,psc/a,psm12c/a 0 or TNS #diffusion auto-pselect (will have priority) templayer XDP bloat-or pdiff,apres,rpd,pdc/a,pdm12c/a * 40 nsd,nsc/a,nsm12c/a 0 or TPS #final pselect templayer FSP bloat-or pdiff,apres,rpd,pfet,psd,pdc/a,pdm12c/a,psc/a,psm12c/a,pfet * 40 ndiff,anres,rnd,ndc/a,ndm12c/a,nsd,nsc/a,nsm12c/a,nfet 0 or XDP #give diff nselect priority and-not XDN or TPS shrink 20 grow 20 grow 20 shrink 20 #final nselect templayer FSN bloat-or ndiff,anres,rnd,nfet,nsd,nwsd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,nfet * 40 pdiff,apres,rpd,pdc/a,pdm12c/a,psd,psc/a,psm12c/a,pfet 0 and-not nwr or XDN #never conflict with final pselect and-not FSP #drawn select always goes or TNS shrink 20 grow 20 grow 20 shrink 20 layer CSN FSN calma 45 0 layer CSP FSP calma 44 0 layer CAA diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,pfet,pfet,fet labels diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,pfet,pfet,fet calma 43 0 layer CCC nwsc/m1,nwsm12c/m1 squares 40 40 60 calma 25 0 layer CCC ndc/m1,ndm12c/m1,nsc/m1,nsm12c/m1 squares 20 40 60 calma 25 0 layer CCC pdc/m1,pdm12c/m1,psc/m1,psm12c/m1 squares 20 40 60 calma 25 0 layer CPG poly,pres,rp,nfet,pfet,fet,pc/a,pm12c/a labels poly,pres,rp,nfet,pfet,fet,pc/a,pm12c/a calma 46 0 layer CCC pc/m1,pm12c/m1 squares 20 40 60 calma 25 0 layer CCC gc squares 0 40 60 calma 25 0 layer CV1 m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1 squares 20 40 60 calma 50 0 layer CV1 gv1 squares 0 40 60 calma 50 0 layer CV2 m3c/m2,m123c/m2,m234c/m2 squares 20 40 60 calma 61 0 layer CV2 gv2 squares 0 40 60 calma 61 0 layer CV3 m4c/m3,m234c/m3 squares 20 40 60 calma 30 0 layer CV3 gv3 squares 0 40 60 calma 30 0 templayer XPAD1 pad shrink 120 templayer XPAD2 XPAD1 shrink 120 layer CM4 pad labels pad calma 31 0 layer CV3 XPAD2 squares 40 40 200 calma 30 0 layer CM3 pad labels pad calma 62 0 layer CV2 XPAD2 squares 160 40 200 calma 61 0 layer CM2 pad labels pad calma 51 0 layer CV1 XPAD2 squares 40 40 200 calma 50 0 layer CM1 pad calma 49 0 layer CM1 m1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1 labels m1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1 calma 49 0 layer CM2 m2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m123c/m2,m234c/m2,m3c/m2,m123c/m2,m234c/m2 labels m2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m123c/m2,m234c/m2,m3c/m2,m123c/m2,m234c/m2 calma 51 0 layer CMFP m1p labels m1p calma 81 0 layer CMSP m2p labels m2p calma 82 0 layer 100 fp labels fp calma 100 0 layer 101 fm1 labels fm1 calma 101 0 layer 102 fm2 labels fm2 calma 102 0 layer 103 fm3 labels fm3 calma 103 0 layer 104 fm4 labels fm4 calma 104 0 layer 109 fa or fb squares 0 200 80 labels fa calma 109 0 layer 119 fn calma 119 0 layer 110 fapm labels fapm calma 110 0 # layer CPG fp layer CPG fp,fapm squares 0 200 80 labels fp calma 46 0 # layer CM1 fm1 layer CM1 fm1,fapm squares 0 200 80 labels fm1 calma 49 0 # layer CM2 fm2 layer CM2 fm2,fapm squares 0 200 80 labels fm2 calma 51 0 # layer CM3 fm3 layer CM3 fm3,fapm squares 0 200 80 labels fm3 calma 62 0 layer CM3 m3,rm3,m3c/m3,m123c/m3,m234c/m3,m4c/m3,m234c/m3,m4c/m3,m234c/m3 labels m3,rm3,m3c/m3,m123c/m3,m234c/m3,m4c/m3,m234c/m3,m4c/m3,m234c/m3 calma 62 0 layer CMTP m3p labels m3p calma 83 0 layer CM4 m4,rm4,m4c/m4,m234c/m4 labels m4,rm4,m4c/m4,m234c/m4 calma 31 0 layer CMQP m4p labels m4p calma 84 0 # layer CM4 fm4 layer CM4 fm4,fapm squares 0 200 80 labels fm4 calma 31 0 layer COG pad shrink 500 labels pad calma 52 0 layer COG glass labels glass calma 52 0 layer CFI nfi,pfi labels nfi,pfi calma 27 0 layer CSB sb,pres,anres,apres labels sb,pres,anres,apres calma 29 0 #CRE/CRM layer CRW rnw,prnw labels rnw,prnw calma 65 0 layer CRG rp,prp,pres labels rp,prp,pres calma 67 0 layer CRD rnd,rpd,prnd,prpd,anres,apres labels rnd,rpd,prnd,prpd,anres,apres calma 66 0 layer CRE rnw,rp,rnd,rpd,pres,anres,apres labels rnw,rp,rnd,rpd,pres,anres,apres calma 64 0 layer CRF rm1,prm1 labels rm1,prm1 calma 71 0 layer CRS rm2,prm2 labels rm2,prm2 calma 72 0 layer CRT rm3,prm3 labels rm3,prm3 calma 73 0 layer CRQ rm4,prm4 labels rm4,prm4 calma 74 0 #CRE/CRM layer CRM rm1,prm1,rm2,prm2,rm3,prm3,rm4,prm4 #CRE/CRM calma 70 0 layer CX comment labels comment calma 63 0 layer XP pad,xp labels pad,xp calma 26 0 style lambda=0.20(c) scalefactor 20 10 layer CWN nwell,rnw,nwr,nwsd,nwsc bloat-or pdiff,apres,rpd,pdc/a,pdm12c/a,pfet * 120 bloat-or nsd,nsc/a,nsm12c/a * 60 bloat-or nfi * 80 grow 60 shrink 60 labels nwell,rnw,nwr,nwsd,nwsc calma 42 0 layer CWNR nwsd,nwsc,nwr grow 140 calma 91 0 layer CWND nwr labels nwr calma 92 0 layer CAA nwsd,nwsc,nwr grow 100 labels nwsd,nwsc calma 43 0 layer CSN bloat-or nwsd,nwsc * 80 nwr 0 calma 43 0 templayer TNWR bloat-or nwr * 100 nwsd,nwsc 40 templayer TCSB nwsd,nwsc grow 40 and-not TNWR layer CSB nwsd,nwsc,nwr grow 140 and-not TCSB calma 29 0 layer CRNW pnwr labels pnwr calma 93 0 templayer TNS ns templayer TPS ps #we give priority to selects autogenerated around diffusions (vrs. ohmics) #XDP = (pdiff*40) Or ps #XDN = (ndiff*40) Or ns #FSP = ((pdiff*40,psc*40) Or XDP And-Not XDN Or ps shrink-grow #FSN = ((ndiff*40,nsc*40) Or XDN And-Not FDP Or ns shrink-grow #CSN = FSN #CSP = FSP #diffusion auto-nselect (will have priority) templayer XDN bloat-or ndiff,anres,rnd,ndc/a,ndm12c/a * 40 psd,psc/a,psm12c/a 0 or TNS #diffusion auto-pselect (will have priority) templayer XDP bloat-or pdiff,apres,rpd,pdc/a,pdm12c/a * 40 nsd,nsc/a,nsm12c/a 0 or TPS #final pselect templayer FSP bloat-or pdiff,apres,rpd,pfet,psd,pdc/a,pdm12c/a,psc/a,psm12c/a,pfet * 40 ndiff,anres,rnd,ndc/a,ndm12c/a,nsd,nsc/a,nsm12c/a,nfet 0 or XDP #give diff nselect priority and-not XDN or TPS shrink 20 grow 20 grow 20 shrink 20 #final nselect templayer FSN bloat-or ndiff,anres,rnd,nfet,nsd,nwsd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,nfet * 40 pdiff,apres,rpd,pdc/a,pdm12c/a,psd,psc/a,psm12c/a,pfet 0 and-not nwr or XDN #never conflict with final pselect and-not FSP #drawn select always goes or TNS shrink 20 grow 20 grow 20 shrink 20 layer CSN FSN calma 45 0 layer CSP FSP calma 44 0 layer CAA diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,pfet,pfet,fet labels diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,pfet,pfet,fet calma 43 0 layer CCC nwsc/m1,nwsm12c/m1 squares 40 40 60 calma 25 0 layer CCC ndc/m1,ndm12c/m1,nsc/m1,nsm12c/m1 squares 20 40 60 calma 25 0 layer CCC pdc/m1,pdm12c/m1,psc/m1,psm12c/m1 squares 20 40 60 calma 25 0 layer CPG poly,pres,rp,nfet,pfet,fet,pc/a,pm12c/a labels poly,pres,rp,nfet,pfet,fet,pc/a,pm12c/a calma 46 0 layer CCC pc/m1,pm12c/m1 squares 20 40 60 calma 25 0 layer CCC gc squares 0 40 60 calma 25 0 layer CV1 m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1 squares 20 40 60 calma 50 0 layer CV1 gv1 squares 0 40 60 calma 50 0 layer CV2 m3c/m2,m123c/m2,m234c/m2 squares 20 40 60 calma 61 0 layer CV2 gv2 squares 0 40 60 calma 61 0 layer CV3 m4c/m3,m234c/m3 squares 20 40 60 calma 30 0 layer CV3 gv3 squares 0 40 60 calma 30 0 templayer XPAD1 pad shrink 120 templayer XPAD2 XPAD1 shrink 120 layer CM4 pad labels pad calma 31 0 layer CV3 XPAD2 squares 40 40 200 calma 30 0 layer CM3 pad labels pad calma 62 0 layer CV2 XPAD2 squares 160 40 200 calma 61 0 layer CM2 pad labels pad calma 51 0 layer CV1 XPAD2 squares 40 40 200 calma 50 0 layer CM1 pad calma 49 0 layer CM1 m1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1 labels m1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1 calma 49 0 layer CM2 m2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m123c/m2,m234c/m2,m3c/m2,m123c/m2,m234c/m2 labels m2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m123c/m2,m234c/m2,m3c/m2,m123c/m2,m234c/m2 calma 51 0 layer CMFP m1p labels m1p calma 81 0 layer CMSP m2p labels m2p calma 82 0 layer 100 fp labels fp calma 100 0 layer 101 fm1 labels fm1 calma 101 0 layer 102 fm2 labels fm2 calma 102 0 layer 103 fm3 labels fm3 calma 103 0 layer 104 fm4 labels fm4 calma 104 0 layer 109 fa or fb squares 0 200 80 labels fa calma 109 0 layer 119 fn calma 119 0 layer 110 fapm labels fapm calma 110 0 # layer CPG fp layer CPG fp,fapm squares 0 200 80 labels fp calma 46 0 # layer CM1 fm1 layer CM1 fm1,fapm squares 0 200 80 labels fm1 calma 49 0 # layer CM2 fm2 layer CM2 fm2,fapm squares 0 200 80 labels fm2 calma 51 0 # layer CM3 fm3 layer CM3 fm3,fapm squares 0 200 80 labels fm3 calma 62 0 layer CM3 m3,rm3,m3c/m3,m123c/m3,m234c/m3,m4c/m3,m234c/m3,m4c/m3,m234c/m3 labels m3,rm3,m3c/m3,m123c/m3,m234c/m3,m4c/m3,m234c/m3,m4c/m3,m234c/m3 calma 62 0 layer CMTP m3p labels m3p calma 83 0 layer CM4 m4,rm4,m4c/m4,m234c/m4 labels m4,rm4,m4c/m4,m234c/m4 calma 31 0 layer CMQP m4p labels m4p calma 84 0 # layer CM4 fm4 layer CM4 fm4,fapm squares 0 200 80 labels fm4 calma 31 0 layer COG pad shrink 500 labels pad calma 52 0 layer COG glass labels glass calma 52 0 layer CFI nfi,pfi labels nfi,pfi calma 27 0 layer CSB sb,pres,anres,apres labels sb,pres,anres,apres calma 29 0 #CRE/CRM layer CRW rnw,prnw labels rnw,prnw calma 65 0 layer CRG rp,prp,pres labels rp,prp,pres calma 67 0 layer CRD rnd,rpd,prnd,prpd,anres,apres labels rnd,rpd,prnd,prpd,anres,apres calma 66 0 layer CRE rnw,rp,rnd,rpd,pres,anres,apres labels rnw,rp,rnd,rpd,pres,anres,apres calma 64 0 layer CRF rm1,prm1 labels rm1,prm1 calma 71 0 layer CRS rm2,prm2 labels rm2,prm2 calma 72 0 layer CRT rm3,prm3 labels rm3,prm3 calma 73 0 layer CRQ rm4,prm4 labels rm4,prm4 calma 74 0 #CRE/CRM layer CRM rm1,prm1,rm2,prm2,rm3,prm3,rm4,prm4 #CRE/CRM calma 70 0 layer CX comment labels comment calma 63 0 layer XP pad,xp labels pad,xp calma 26 0 style lambda=0.20() scalefactor 20 10 layer CWN nwell,rnw,nwr,nwsd,nwsc bloat-or pdiff,apres,rpd,pdc/a,pdm12c/a,pfet * 120 bloat-or nsd,nsc/a,nsm12c/a * 60 bloat-or nfi * 80 grow 60 shrink 60 labels nwell,rnw,nwr,nwsd,nwsc calma 42 0 layer CWNR nwsd,nwsc,nwr grow 140 calma 91 0 layer CWND nwr labels nwr calma 92 0 layer CAA nwsd,nwsc,nwr grow 100 labels nwsd,nwsc calma 43 0 layer CSN bloat-or nwsd,nwsc * 80 nwr 0 calma 43 0 templayer TNWR bloat-or nwr * 100 nwsd,nwsc 40 templayer TCSB nwsd,nwsc grow 40 and-not TNWR layer CSB nwsd,nwsc,nwr grow 140 and-not TCSB calma 29 0 layer CRNW pnwr labels pnwr calma 93 0 templayer TNS ns templayer TPS ps #we give priority to selects autogenerated around diffusions (vrs. ohmics) #XDP = (pdiff*40) Or ps #XDN = (ndiff*40) Or ns #FSP = ((pdiff*40,psc*40) Or XDP And-Not XDN Or ps shrink-grow #FSN = ((ndiff*40,nsc*40) Or XDN And-Not FDP Or ns shrink-grow #CSN = FSN #CSP = FSP #diffusion auto-nselect (will have priority) templayer XDN bloat-or ndiff,anres,rnd,ndc/a,ndm12c/a * 40 psd,psc/a,psm12c/a 0 or TNS #diffusion auto-pselect (will have priority) templayer XDP bloat-or pdiff,apres,rpd,pdc/a,pdm12c/a * 40 nsd,nsc/a,nsm12c/a 0 or TPS #final pselect templayer FSP bloat-or pdiff,apres,rpd,pfet,psd,pdc/a,pdm12c/a,psc/a,psm12c/a,pfet * 40 ndiff,anres,rnd,ndc/a,ndm12c/a,nsd,nsc/a,nsm12c/a,nfet 0 or XDP #give diff nselect priority and-not XDN or TPS shrink 20 grow 20 grow 20 shrink 20 #final nselect templayer FSN bloat-or ndiff,anres,rnd,nfet,nsd,nwsd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,nfet * 40 pdiff,apres,rpd,pdc/a,pdm12c/a,psd,psc/a,psm12c/a,pfet 0 and-not nwr or XDN #never conflict with final pselect and-not FSP #drawn select always goes or TNS shrink 20 grow 20 grow 20 shrink 20 layer CSN FSN calma 45 0 layer CSP FSP calma 44 0 layer CAA diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,pfet,pfet,fet labels diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,pfet,pfet,fet calma 43 0 layer CCA nwsc/m1,nwsm12c/m1 squares 40 40 60 calma 48 0 layer CCA ndc/m1,ndm12c/m1,nsc/m1,nsm12c/m1 squares 20 40 60 calma 48 0 layer CCA pdc/m1,pdm12c/m1,psc/m1,psm12c/m1 squares 20 40 60 calma 48 0 layer CPG poly,pres,rp,nfet,pfet,fet,pc/a,pm12c/a labels poly,pres,rp,nfet,pfet,fet,pc/a,pm12c/a calma 46 0 layer CCP pc/m1,pm12c/m1 squares 20 40 60 calma 47 0 layer CCC gc squares 0 40 60 calma 25 0 layer CV1 m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1 squares 20 40 60 calma 50 0 layer CV1 gv1 squares 0 40 60 calma 50 0 layer CV2 m3c/m2,m123c/m2,m234c/m2 squares 20 40 60 calma 61 0 layer CV2 gv2 squares 0 40 60 calma 61 0 layer CV3 m4c/m3,m234c/m3 squares 20 40 60 calma 30 0 layer CV3 gv3 squares 0 40 60 calma 30 0 templayer XPAD1 pad shrink 120 templayer XPAD2 XPAD1 shrink 120 layer CM4 pad labels pad calma 31 0 layer CV3 XPAD2 squares 40 40 200 calma 30 0 layer CM3 pad labels pad calma 62 0 layer CV2 XPAD2 squares 160 40 200 calma 61 0 layer CM2 pad labels pad calma 51 0 layer CV1 XPAD2 squares 40 40 200 calma 50 0 layer CM1 pad calma 49 0 layer CM1 m1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1 labels m1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1 calma 49 0 layer CM2 m2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m123c/m2,m234c/m2,m3c/m2,m123c/m2,m234c/m2 labels m2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m123c/m2,m234c/m2,m3c/m2,m123c/m2,m234c/m2 calma 51 0 layer CMFP m1p labels m1p calma 81 0 layer CMSP m2p labels m2p calma 82 0 layer 100 fp labels fp calma 100 0 layer 101 fm1 labels fm1 calma 101 0 layer 102 fm2 labels fm2 calma 102 0 layer 103 fm3 labels fm3 calma 103 0 layer 104 fm4 labels fm4 calma 104 0 layer 109 fa or fb squares 0 200 80 labels fa calma 109 0 layer 119 fn calma 119 0 layer 110 fapm labels fapm calma 110 0 # layer CPG fp layer CPG fp,fapm squares 0 200 80 labels fp calma 46 0 # layer CM1 fm1 layer CM1 fm1,fapm squares 0 200 80 labels fm1 calma 49 0 # layer CM2 fm2 layer CM2 fm2,fapm squares 0 200 80 labels fm2 calma 51 0 # layer CM3 fm3 layer CM3 fm3,fapm squares 0 200 80 labels fm3 calma 62 0 layer CM3 m3,rm3,m3c/m3,m123c/m3,m234c/m3,m4c/m3,m234c/m3,m4c/m3,m234c/m3 labels m3,rm3,m3c/m3,m123c/m3,m234c/m3,m4c/m3,m234c/m3,m4c/m3,m234c/m3 calma 62 0 layer CMTP m3p labels m3p calma 83 0 layer CM4 m4,rm4,m4c/m4,m234c/m4 labels m4,rm4,m4c/m4,m234c/m4 calma 31 0 layer CMQP m4p labels m4p calma 84 0 # layer CM4 fm4 layer CM4 fm4,fapm squares 0 200 80 labels fm4 calma 31 0 layer COG pad shrink 500 labels pad calma 52 0 layer COG glass labels glass calma 52 0 layer CFI nfi,pfi labels nfi,pfi calma 27 0 layer CSB sb,pres,anres,apres labels sb,pres,anres,apres calma 29 0 #CRE/CRM layer CRW rnw,prnw labels rnw,prnw calma 65 0 layer CRG rp,prp,pres labels rp,prp,pres calma 67 0 layer CRD rnd,rpd,prnd,prpd,anres,apres labels rnd,rpd,prnd,prpd,anres,apres calma 66 0 layer CRE rnw,rp,rnd,rpd,pres,anres,apres labels rnw,rp,rnd,rpd,pres,anres,apres calma 64 0 layer CRF rm1,prm1 labels rm1,prm1 calma 71 0 layer CRS rm2,prm2 labels rm2,prm2 calma 72 0 layer CRT rm3,prm3 labels rm3,prm3 calma 73 0 layer CRQ rm4,prm4 labels rm4,prm4 calma 74 0 #CRE/CRM layer CRM rm1,prm1,rm2,prm2,rm3,prm3,rm4,prm4 #CRE/CRM calma 70 0 layer CX comment labels comment calma 63 0 layer XP pad,xp labels pad,xp calma 26 0 end cifinput style lambda=0.20(p) scalefactor 20 layer nwell CWN and-not CWNR and-not CTA labels CWN calma CWN 42 * layer rnw CWN and-not CWNR and CRE and-not CSB and-not CRD and-not CAA and-not CPG calma CWN 42 * layer rnw CWN and-not CWNR and CRW and-not CRD and-not CAA and-not CPG calma CWN 42 * layer pseudo_rnwell CRW and-not CRE calma CRW 65 * calma CWNR 91 * layer nwr CWND calma CWND 92 * layer pseudo_nwr CRNW calma CRNW 93 * layer pwell CWP and-not CTA labels CWP calma CWP 41 * layer diff CAA and-not CTA and-not CPG and-not CWNR and-not COP and-not CSN and-not CSP labels CAA calma CAA 43 * layer tran CAA and-not CTA and CPG and-not CWNR and-not COP and-not CSN and-not CSP labels CAA calma CAA 43 * calma CSN 45 * calma CSP 44 * layer ndiff CAA and CSN and-not CWNR and-not CTA and-not CRE and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer rnd CAA and CSN and-not CWNR and CRE and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA calma CAA 43 * layer rnd CAA and CSN and-not CWNR and CRD and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA calma CAA 43 * layer pseudo_rndiff CRD and-not CRE and-not CAA and-not CSB and-not CPG and-not CWN and-not CSP and CSN and-not CBA calma CRD 66 * layer pdiff CAA and CSP and-not CWNR and-not CTA and-not CRE and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer rpd CAA and CSP and-not CWNR and CRE and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CAA 43 * layer rpd CAA and CSP and-not CWNR and CRD and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CAA 43 * layer pseudo_rpdiff CRD and-not CRE and-not CAA and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CRD 66 * layer nfet CAA and CSN and-not CWNR and-not CTA and CPG and-not CEL and-not CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer pfet CAA and CSP and-not CWNR and-not CTA and CPG and-not CEL and CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer nsd CAA and CSN and-not CWNR and-not CTA and CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer psd CAA and CSP and-not CWNR and-not CTA and-not CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer nwsd CAA and CSN and CWNR shrink 100 and-not CTA and CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer ndc CAA and CSN and CCA and-not CV1 and-not CWNR and-not CTA and-not CWN and CM1 grow 20 grow 10 shrink 10 calma CCA 48 * layer ndc CAA and CSN and CCC and-not CV1 and-not CWNR and-not CTA and-not CWN and CM1 grow 20 grow 10 shrink 10 calma CCC 25 * layer nsc CAA and CSN and CCA and-not CV1 and-not CWNR and-not CTA and CWN and CM1 grow 20 grow 10 shrink 10 calma CCA 48 * layer nsc CAA and CSN and CCC and-not CV1 and-not CWNR and-not CTA and CWN and CM1 grow 20 grow 10 shrink 10 calma CCC 25 * layer nwsc CAA and CSN and-not CV1 and CWNR shrink 100 and-not CTA and CCA and CWN and CM1 grow 40 grow 10 shrink 10 calma CCA 48 * layer nwsc CAA and CSN and-not CV1 and CWNR shrink 105 and-not CTA and CCC and CWN and CM1 grow 40 grow 10 shrink 10 calma CCC 25 * layer pdc CAA and CSP and CCA and-not CV1 and-not CTA and-not CPS and CWN and CM1 grow 20 grow 10 shrink 10 calma CCA 48 * layer pdc CAA and CSP and CCC and-not CV1 and-not CTA and-not CPS and CWN and CM1 grow 20 grow 10 shrink 10 calma CCC 25 * layer psc CAA and CSP and CCA and-not CV1 and-not CTA and-not CPS and-not CWN and CM1 grow 20 grow 10 shrink 10 calma CCA 48 * layer psc CAA and CSP and CCC and-not CV1 and-not CWNR and-not CTA and-not CPS and-not CWN and CM1 grow 20 grow 10 shrink 10 calma CCC 25 * layer ndc CAA and CSN and CCA and CV1 and CV2 and-not CV3 and-not CWNR and-not CTA and-not CWN and CM1 grow 20 grow 10 shrink 10 calma CCA 48 * layer ndc CAA and CSN and CCC and CV1 and CV2 and-not CV3 and-not CWNR and-not CTA and-not CWN and CM1 grow 20 grow 10 shrink 10 calma CCC 25 * layer nsc CAA and CSN and CCA and CV1 and CV2 and-not CV3 and-not CWNR and-not CTA and CWN and CM1 grow 20 grow 10 shrink 10 calma CCA 48 * layer nsc CAA and CSN and CCC and CV1 and CV2 and-not CV3 and-not CWNR and-not CTA and CWN and CM1 grow 20 grow 10 shrink 10 calma CCC 25 * layer nwsc CAA and CSN and CV1 and CV2 and-not CV3 and CWNR shrink 100 and-not CTA and CCA and CWN and CM1 grow 40 grow 10 shrink 10 calma CCA 48 * layer nwsc CAA and CSN and CV1 and CV2 and-not CV3 and CWNR shrink 105 and-not CTA and CCC and CWN and CM1 grow 40 grow 10 shrink 10 calma CCC 25 * layer pdc CAA and CSP and CCA and CV1 and CV2 and-not CV3 and-not CTA and-not CPS and CWN and CM1 grow 20 grow 10 shrink 10 calma CCA 48 * layer pdc CAA and CSP and CCC and CV1 and CV2 and-not CV3 and-not CTA and-not CPS and CWN and CM1 grow 20 grow 10 shrink 10 calma CCC 25 * layer psc CAA and CSP and CCA and CV1 and CV2 and-not CV3 and-not CTA and-not CPS and-not CWN and CM1 grow 20 grow 10 shrink 10 calma CCA 48 * layer psc CAA and CSP and CCC and CV1 and CV2 and-not CV3 and-not CWNR and-not CTA and-not CPS and-not CWN and CM1 grow 20 grow 10 shrink 10 calma CCC 25 * layer poly CPG and-not CRE labels CPG calma CPG 46 * layer rp CPG and CRE and-not CSB calma CPG 46 * layer rp CPG and CRG calma CPG 46 * layer pseudo_rpoly CRG and-not CRE calma CRG 67 * layer pc CCP and-not CV1 and CPG and-not CPC and-not CEL and-not CAA grow 20 and CM1 grow 10 shrink 10 calma CCP 47 * layer pc CCC and-not CV1 and CPG and-not CPC and-not CEL and-not CAA grow 20 and CM1 grow 10 shrink 10 calma CCC 25 * layer pc CCP and CV1 and CV2 and-not CV3 and CPG and-not CPC and-not CEL and-not CAA grow 20 and CM1 grow 10 shrink 10 calma CCP 47 * layer pc CCC and CV1 and CV2 and-not CV3 and CPG and-not CPC and-not CEL and-not CAA grow 20 and CM1 grow 10 shrink 10 calma CCC 25 * layer gc CCP and-not CPG and-not CPC calma CCP 47 * layer gc CCP and-not CM1 calma CCP 47 * layer gc CCA and-not COP and-not CAA and-not CBA calma CCA 48 * layer gc CCA and-not COP and-not CM1 calma CCA 48 * layer gc CCC and-not COP and-not CPG and-not CPC and-not CEL and-not CAA and-not CBA calma CCC 25 * layer gc CCC and-not COP and-not CM1 calma CCC 25 * layer gc CCE and-not CPC and-not CEL calma CCE 55 * layer gc CCE and-not CM1 calma CCE 55 * layer gv1 CV1 and-not COP and-not CM1 calma CV1 50 * layer gv1 CV1 and-not COP and-not CM2 calma CV1 50 * layer gv2 CV2 and-not COP and-not CM2 calma CV2 61 * layer gv2 CV2 and-not COP and-not CM3 calma CV2 61 * layer gv3 CV3 and-not COP and-not CM3 calma CV3 30 * layer gv3 CV3 and-not COP and-not CM4 calma CV3 30 * layer m2c CV1 and-not CV2 and-not CCC and-not CCP and-not CCA and-not XP grow 20 and CM2 and CM1 grow 10 shrink 10 calma CV1 50 * layer m2c CV1 and CV2 and CV3 and-not CCC and-not CCP and-not CCA and-not XP grow 20 and CM2 and CM1 grow 10 shrink 10 calma CV1 50 * layer pm12c CV1 and-not CV2 and CCP grow 20 and CM2 and CM1 and CPG grow 10 shrink 10 calma CV1 50 * layer pm12c CV1 and-not CV2 and CCC grow 20 and CM2 and CM1 and CPG grow 10 shrink 10 calma CV1 50 * layer pm12c CV1 and CV2 and CV3 and CCP grow 20 and CM2 and CM1 and CPG grow 10 shrink 10 calma CV1 50 * layer pm12c CV1 and CV2 and CV3 and CCC grow 20 and CM2 and CM1 and CPG grow 10 shrink 10 calma CV1 50 * layer m1 CM1 and-not CRM and-not CRF and-not XP labels CM1 calma CM1 49 * layer rm1 CRM and CM1 calma CRM 70 * layer rm1 CRF and CM1 calma CRF 71 * layer pseudo_rmetal1 CRF and-not rm1 calma CRF 71 * layer m1p CMFP labels CMFP calma CMFP 81 * layer m2 CM2 and-not CRM and-not CRS and-not XP labels CM2 calma CM2 51 * layer rm2 CRM and CM2 calma CRM 70 * layer rm2 CRS and CM2 calma CRS 72 * layer pseudo_rmetal2 CRS and-not rm2 calma CRS 72 * layer m2p CMSP labels CMSP calma CMSP 82 * layer ndm12c CAA and CSN and CV1 and-not CV2 and-not CWNR and-not CTA and CCA grow 20 and CM1 and CM2 and-not CWN grow 10 shrink 10 calma CV1 50 * layer ndm12c CAA and CSN and CV1 and-not CV2 and-not CWNR and-not CTA and CCC grow 20 and CM1 and CM2 grow 10 shrink 10 calma CV1 50 * layer pdm12c CAA and CSP and CV1 and-not CV2 and-not CTA and CCA grow 20 and CM1 and CM2 and CWN grow 10 shrink 10 calma CV1 50 * layer pdm12c CAA and CSP and CV1 and-not CV2 and-not CTA and CCC grow 20 and CM1 and CM2 and CWN grow 10 shrink 10 calma CV1 50 * layer nsm12c CAA and CSN and CV1 and-not CV2 and-not CWNR and-not CTA and CCA grow 20 and CM1 and CM2 and CWN grow 10 shrink 10 calma CV1 50 * layer nsm12c CAA and CSN and CV1 and-not CV2 and-not CWNR and-not CTA and CCC grow 20 and CM1 and CM2 and CWN grow 10 shrink 10 calma CV1 50 * layer psm12c CAA and CSP and CV1 and-not CV2 and-not CTA and CCA grow 20 and CM1 and CM2 and-not CWN grow 10 shrink 10 calma CV1 50 * layer psm12c CAA and CSP and CV1 and-not CV2 and-not CTA and CCC grow 20 and CM1 and CM2 and-not CWN grow 10 shrink 10 calma CV1 50 * layer nwsm12c CAA and CSN and CV1 and-not CV2 and CWNR and-not CTA and CCA grow 20 and CM1 and CM2 and CWN grow 10 shrink 10 calma CV1 50 * layer nwsm12c CAA and CSN and CV1 and-not CV2 and CWNR and-not CTA and CCC grow 20 and CM1 and CM2 and CWN grow 10 shrink 10 calma CV1 50 * layer ndm12c CAA and CSN and CV1 and CV2 and CV3 and-not CWNR and-not CTA and CCA grow 20 and CM1 and CM2 and-not CWN grow 10 shrink 10 calma CV1 50 * layer ndm12c CAA and CSN and CV1 and CV2 and CV3 and-not CWNR and-not CTA and CCC grow 20 and CM1 and CM2 grow 10 shrink 10 calma CV1 50 * layer pdm12c CAA and CSP and CV1 and CV2 and CV3 and-not CTA and CCA grow 20 and CM1 and CM2 and CWN grow 10 shrink 10 calma CV1 50 * layer pdm12c CAA and CSP and CV1 and CV2 and CV3 and-not CTA and CCC grow 20 and CM1 and CM2 and CWN grow 10 shrink 10 calma CV1 50 * layer nsm12c CAA and CSN and CV1 and CV2 and CV3 and-not CWNR and-not CTA and CCA grow 20 and CM1 and CM2 and CWN grow 10 shrink 10 calma CV1 50 * layer nsm12c CAA and CSN and CV1 and CV2 and CV3 and-not CWNR and-not CTA and CCC grow 20 and CM1 and CM2 and CWN grow 10 shrink 10 calma CV1 50 * layer psm12c CAA and CSP and CV1 and CV2 and CV3 and-not CTA and CCA grow 20 and CM1 and CM2 and-not CWN grow 10 shrink 10 calma CV1 50 * layer psm12c CAA and CSP and CV1 and CV2 and CV3 and-not CTA and CCC grow 20 and CM1 and CM2 and-not CWN grow 10 shrink 10 calma CV1 50 * layer nwsm12c CAA and CSN and CV1 and CV2 and CV3 and CWNR and-not CTA and CCA grow 20 and CM1 and CM2 and CWN grow 10 shrink 10 calma CV1 50 * layer nwsm12c CAA and CSN and CV1 and CV2 and CV3 and CWNR and-not CTA and CCC grow 20 and CM1 and CM2 and CWN grow 10 shrink 10 calma CV1 50 * layer fp 100 calma 100 100 * layer fm1 101 calma 101 101 * layer fm2 102 calma 102 102 * layer fm3 103 calma 103 103 * layer fm4 104 calma 104 104 * layer fa 109 calma 109 109 * layer fn 119 calma 119 119 * layer fapm 110 calma 110 110 * layer m3c CV2 and-not CV3 and-not CV1 and-not XP grow 20 and CM3 and CM2 grow 10 shrink 10 calma CV2 61 * layer m123c CV2 and-not CV3 and CV1 and-not XP grow 20 and CM3 and CM2 and CM1 grow 10 shrink 10 calma CV2 61 * layer m3 CM3 and-not CRM and-not CRT and-not XP labels CM3 calma CM3 62 * layer rm3 CRM and CM3 calma CRM 70 * layer rm3 CRT and CM3 calma CRT 73 * layer pseudo_rmetal3 CRT and-not rm3 calma CRT 73 * layer m3p CMTP labels CMTP calma CMTP 83 * layer m234c CV3 and CV2 and-not XP grow 20 and CM4 and CM3 and CM2 grow 20 shrink 20 calma CV3 30 * layer m4 CM4 and-not CRM and-not CRQ and-not XP labels CM4 calma CM4 31 * layer rm4 CRM and CM4 calma CRM 70 * layer rm4 CRQ and CM4 calma CRQ 74 * layer pseudo_rmetal4 CRQ and-not rm4 calma CRQ 74 * layer m4p CMQP labels CMQP calma CMQP 84 * layer m4c CV3 and-not CV2 and-not XP grow 20 and CM4 and CM3 grow 20 shrink 20 calma CV3 30 * layer pad XP labels pad calma XP 26 * layer glass COG and-not COP and-not XP labels COG calma COG 52 * layer nfi CFI and CWN labels CFI calma CFI 27 * layer pfi CFI and-not CWN labels CFI calma CFI 27 * layer sb CSB and-not CWNR labels CSB calma CSB 29 * layer pres CPG and CSB calma CPG 46 * layer anres CAA and CSN and-not CWNR and-not CTA and CSB and-not CPG and-not CWN and-not CSP and-not CBA calma CAA 43 * layer apres CAA and CSP and-not CWNR and-not CTA and CSB and-not CPG and CWN and-not CSN and-not CPS and-not CBA calma CAA 43 * layer comment CX labels CX calma CX 63 * calma CTA 60 * #CRE/CRM calma CRW 65 * calma CRG 67 * calma CRD 66 * calma CRE 64 * calma CRF 71 * calma CRS 72 * calma CRT 73 * calma CRQ 74 * calma CRM 70 * style lambda=0.20(s) scalefactor 20 layer nwell CWN and-not CWNR and-not CTA labels CWN calma CWN 42 * layer rnw CWN and-not CWNR and CRE and-not CSB and-not CRD and-not CAA and-not CPG calma CWN 42 * layer rnw CWN and-not CWNR and CRW and-not CRD and-not CAA and-not CPG calma CWN 42 * layer pseudo_rnwell CRW and-not CRE calma CRW 65 * calma CWNR 91 * layer nwr CWND calma CWND 92 * layer pseudo_nwr CRNW calma CRNW 93 * ignore CWP calma CWP 41 * layer diff CAA and-not CTA and-not CPG and-not CWNR and-not COP and-not CSN and-not CSP labels CAA calma CAA 43 * layer tran CAA and-not CTA and CPG and-not CWNR and-not COP and-not CSN and-not CSP labels CAA calma CAA 43 * layer nselect CSN calma CSN 45 * layer pselect CSP calma CSP 44 * layer ndiff CAA and CSN and-not CWNR and-not CTA and-not CRE and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer rnd CAA and CSN and-not CWNR and CRE and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA calma CAA 43 * layer rnd CAA and CSN and-not CWNR and CRD and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA calma CAA 43 * layer pseudo_rndiff CRD and-not CRE and-not CAA and-not CSB and-not CPG and-not CWN and-not CSP and CSN and-not CBA calma CRD 66 * layer pdiff CAA and CSP and-not CWNR and-not CTA and-not CRE and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer rpd CAA and CSP and-not CWNR and CRE and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CAA 43 * layer rpd CAA and CSP and-not CWNR and CRD and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CAA 43 * layer pseudo_rpdiff CRD and-not CRE and-not CAA and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CRD 66 * layer nfet CAA and CSN and-not CWNR and-not CTA and CPG and-not CEL and-not CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer pfet CAA and CSP and-not CWNR and-not CTA and CPG and-not CEL and CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer nsd CAA and CSN and-not CWNR and-not CTA and CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer psd CAA and CSP and-not CWNR and-not CTA and-not CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer nwsd CAA and CSN and CWNR shrink 100 and-not CTA and CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer ndc CAA and CSN and CCA and-not CV1 and-not CWNR and-not CTA and-not CWN and CM1 grow 20 grow 10 shrink 10 calma CCA 48 * layer ndc CAA and CSN and CCC and-not CV1 and-not CWNR and-not CTA and-not CWN and CM1 grow 20 grow 10 shrink 10 calma CCC 25 * layer nsc CAA and CSN and CCA and-not CV1 and-not CWNR and-not CTA and CWN and CM1 grow 20 grow 10 shrink 10 calma CCA 48 * layer nsc CAA and CSN and CCC and-not CV1 and-not CWNR and-not CTA and CWN and CM1 grow 20 grow 10 shrink 10 calma CCC 25 * layer nwsc CAA and CSN and-not CV1 and CWNR shrink 100 and-not CTA and CCA and CWN and CM1 grow 40 grow 10 shrink 10 calma CCA 48 * layer nwsc CAA and CSN and-not CV1 and CWNR shrink 105 and-not CTA and CCC and CWN and CM1 grow 40 grow 10 shrink 10 calma CCC 25 * layer pdc CAA and CSP and CCA and-not CV1 and-not CTA and-not CPS and CWN and CM1 grow 20 grow 10 shrink 10 calma CCA 48 * layer pdc CAA and CSP and CCC and-not CV1 and-not CTA and-not CPS and CWN and CM1 grow 20 grow 10 shrink 10 calma CCC 25 * layer psc CAA and CSP and CCA and-not CV1 and-not CTA and-not CPS and-not CWN and CM1 grow 20 grow 10 shrink 10 calma CCA 48 * layer psc CAA and CSP and CCC and-not CV1 and-not CWNR and-not CTA and-not CPS and-not CWN and CM1 grow 20 grow 10 shrink 10 calma CCC 25 * layer ndc CAA and CSN and CCA and CV1 and CV2 and-not CV3 and-not CWNR and-not CTA and-not CWN and CM1 grow 20 grow 10 shrink 10 calma CCA 48 * layer ndc CAA and CSN and CCC and CV1 and CV2 and-not CV3 and-not CWNR and-not CTA and-not CWN and CM1 grow 20 grow 10 shrink 10 calma CCC 25 * layer nsc CAA and CSN and CCA and CV1 and CV2 and-not CV3 and-not CWNR and-not CTA and CWN and CM1 grow 20 grow 10 shrink 10 calma CCA 48 * layer nsc CAA and CSN and CCC and CV1 and CV2 and-not CV3 and-not CWNR and-not CTA and CWN and CM1 grow 20 grow 10 shrink 10 calma CCC 25 * layer nwsc CAA and CSN and CV1 and CV2 and-not CV3 and CWNR shrink 100 and-not CTA and CCA and CWN and CM1 grow 40 grow 10 shrink 10 calma CCA 48 * layer nwsc CAA and CSN and CV1 and CV2 and-not CV3 and CWNR shrink 105 and-not CTA and CCC and CWN and CM1 grow 40 grow 10 shrink 10 calma CCC 25 * layer pdc CAA and CSP and CCA and CV1 and CV2 and-not CV3 and-not CTA and-not CPS and CWN and CM1 grow 20 grow 10 shrink 10 calma CCA 48 * layer pdc CAA and CSP and CCC and CV1 and CV2 and-not CV3 and-not CTA and-not CPS and CWN and CM1 grow 20 grow 10 shrink 10 calma CCC 25 * layer psc CAA and CSP and CCA and CV1 and CV2 and-not CV3 and-not CTA and-not CPS and-not CWN and CM1 grow 20 grow 10 shrink 10 calma CCA 48 * layer psc CAA and CSP and CCC and CV1 and CV2 and-not CV3 and-not CWNR and-not CTA and-not CPS and-not CWN and CM1 grow 20 grow 10 shrink 10 calma CCC 25 * layer poly CPG and-not CRE labels CPG calma CPG 46 * layer rp CPG and CRE and-not CSB calma CPG 46 * layer rp CPG and CRG calma CPG 46 * layer pseudo_rpoly CRG and-not CRE calma CRG 67 * layer pc CCP and-not CV1 and CPG and-not CPC and-not CEL and-not CAA grow 20 and CM1 grow 10 shrink 10 calma CCP 47 * layer pc CCC and-not CV1 and CPG and-not CPC and-not CEL and-not CAA grow 20 and CM1 grow 10 shrink 10 calma CCC 25 * layer pc CCP and CV1 and CV2 and-not CV3 and CPG and-not CPC and-not CEL and-not CAA grow 20 and CM1 grow 10 shrink 10 calma CCP 47 * layer pc CCC and CV1 and CV2 and-not CV3 and CPG and-not CPC and-not CEL and-not CAA grow 20 and CM1 grow 10 shrink 10 calma CCC 25 * layer gc CCP and-not CPG and-not CPC calma CCP 47 * layer gc CCP and-not CM1 calma CCP 47 * layer gc CCA and-not COP and-not CAA and-not CBA calma CCA 48 * layer gc CCA and-not COP and-not CM1 calma CCA 48 * layer gc CCC and-not COP and-not CPG and-not CPC and-not CEL and-not CAA and-not CBA calma CCC 25 * layer gc CCC and-not COP and-not CM1 calma CCC 25 * layer gc CCE and-not CPC and-not CEL calma CCE 55 * layer gc CCE and-not CM1 calma CCE 55 * layer gv1 CV1 and-not COP and-not CM1 calma CV1 50 * layer gv1 CV1 and-not COP and-not CM2 calma CV1 50 * layer gv2 CV2 and-not COP and-not CM2 calma CV2 61 * layer gv2 CV2 and-not COP and-not CM3 calma CV2 61 * layer gv3 CV3 and-not COP and-not CM3 calma CV3 30 * layer gv3 CV3 and-not COP and-not CM4 calma CV3 30 * layer m2c CV1 and-not CV2 and-not CCC and-not CCP and-not CCA and-not XP grow 20 and CM2 and CM1 grow 10 shrink 10 calma CV1 50 * layer m2c CV1 and CV2 and CV3 and-not CCC and-not CCP and-not CCA and-not XP grow 20 and CM2 and CM1 grow 10 shrink 10 calma CV1 50 * layer pm12c CV1 and-not CV2 and CCP grow 20 and CM2 and CM1 and CPG grow 10 shrink 10 calma CV1 50 * layer pm12c CV1 and-not CV2 and CCC grow 20 and CM2 and CM1 and CPG grow 10 shrink 10 calma CV1 50 * layer pm12c CV1 and CV2 and CV3 and CCP grow 20 and CM2 and CM1 and CPG grow 10 shrink 10 calma CV1 50 * layer pm12c CV1 and CV2 and CV3 and CCC grow 20 and CM2 and CM1 and CPG grow 10 shrink 10 calma CV1 50 * layer m1 CM1 and-not CRM and-not CRF and-not XP labels CM1 calma CM1 49 * layer rm1 CRM and CM1 calma CRM 70 * layer rm1 CRF and CM1 calma CRF 71 * layer pseudo_rmetal1 CRF and-not rm1 calma CRF 71 * layer m1p CMFP labels CMFP calma CMFP 81 * layer m2 CM2 and-not CRM and-not CRS and-not XP labels CM2 calma CM2 51 * layer rm2 CRM and CM2 calma CRM 70 * layer rm2 CRS and CM2 calma CRS 72 * layer pseudo_rmetal2 CRS and-not rm2 calma CRS 72 * layer m2p CMSP labels CMSP calma CMSP 82 * layer ndm12c CAA and CSN and CV1 and-not CV2 and-not CWNR and-not CTA and CCA grow 20 and CM1 and CM2 and-not CWN grow 10 shrink 10 calma CV1 50 * layer ndm12c CAA and CSN and CV1 and-not CV2 and-not CWNR and-not CTA and CCC grow 20 and CM1 and CM2 grow 10 shrink 10 calma CV1 50 * layer pdm12c CAA and CSP and CV1 and-not CV2 and-not CTA and CCA grow 20 and CM1 and CM2 and CWN grow 10 shrink 10 calma CV1 50 * layer pdm12c CAA and CSP and CV1 and-not CV2 and-not CTA and CCC grow 20 and CM1 and CM2 and CWN grow 10 shrink 10 calma CV1 50 * layer nsm12c CAA and CSN and CV1 and-not CV2 and-not CWNR and-not CTA and CCA grow 20 and CM1 and CM2 and CWN grow 10 shrink 10 calma CV1 50 * layer nsm12c CAA and CSN and CV1 and-not CV2 and-not CWNR and-not CTA and CCC grow 20 and CM1 and CM2 and CWN grow 10 shrink 10 calma CV1 50 * layer psm12c CAA and CSP and CV1 and-not CV2 and-not CTA and CCA grow 20 and CM1 and CM2 and-not CWN grow 10 shrink 10 calma CV1 50 * layer psm12c CAA and CSP and CV1 and-not CV2 and-not CTA and CCC grow 20 and CM1 and CM2 and-not CWN grow 10 shrink 10 calma CV1 50 * layer nwsm12c CAA and CSN and CV1 and-not CV2 and CWNR and-not CTA and CCA grow 20 and CM1 and CM2 and CWN grow 10 shrink 10 calma CV1 50 * layer nwsm12c CAA and CSN and CV1 and-not CV2 and CWNR and-not CTA and CCC grow 20 and CM1 and CM2 and CWN grow 10 shrink 10 calma CV1 50 * layer ndm12c CAA and CSN and CV1 and CV2 and CV3 and-not CWNR and-not CTA and CCA grow 20 and CM1 and CM2 and-not CWN grow 10 shrink 10 calma CV1 50 * layer ndm12c CAA and CSN and CV1 and CV2 and CV3 and-not CWNR and-not CTA and CCC grow 20 and CM1 and CM2 grow 10 shrink 10 calma CV1 50 * layer pdm12c CAA and CSP and CV1 and CV2 and CV3 and-not CTA and CCA grow 20 and CM1 and CM2 and CWN grow 10 shrink 10 calma CV1 50 * layer pdm12c CAA and CSP and CV1 and CV2 and CV3 and-not CTA and CCC grow 20 and CM1 and CM2 and CWN grow 10 shrink 10 calma CV1 50 * layer nsm12c CAA and CSN and CV1 and CV2 and CV3 and-not CWNR and-not CTA and CCA grow 20 and CM1 and CM2 and CWN grow 10 shrink 10 calma CV1 50 * layer nsm12c CAA and CSN and CV1 and CV2 and CV3 and-not CWNR and-not CTA and CCC grow 20 and CM1 and CM2 and CWN grow 10 shrink 10 calma CV1 50 * layer psm12c CAA and CSP and CV1 and CV2 and CV3 and-not CTA and CCA grow 20 and CM1 and CM2 and-not CWN grow 10 shrink 10 calma CV1 50 * layer psm12c CAA and CSP and CV1 and CV2 and CV3 and-not CTA and CCC grow 20 and CM1 and CM2 and-not CWN grow 10 shrink 10 calma CV1 50 * layer nwsm12c CAA and CSN and CV1 and CV2 and CV3 and CWNR and-not CTA and CCA grow 20 and CM1 and CM2 and CWN grow 10 shrink 10 calma CV1 50 * layer nwsm12c CAA and CSN and CV1 and CV2 and CV3 and CWNR and-not CTA and CCC grow 20 and CM1 and CM2 and CWN grow 10 shrink 10 calma CV1 50 * layer fp 100 calma 100 100 * layer fm1 101 calma 101 101 * layer fm2 102 calma 102 102 * layer fm3 103 calma 103 103 * layer fm4 104 calma 104 104 * layer fa 109 calma 109 109 * layer fn 119 calma 119 119 * layer fapm 110 calma 110 110 * layer m3c CV2 and-not CV3 and-not CV1 and-not XP grow 20 and CM3 and CM2 grow 10 shrink 10 calma CV2 61 * layer m123c CV2 and-not CV3 and CV1 and-not XP grow 20 and CM3 and CM2 and CM1 grow 10 shrink 10 calma CV2 61 * layer m3 CM3 and-not CRM and-not CRT and-not XP labels CM3 calma CM3 62 * layer rm3 CRM and CM3 calma CRM 70 * layer rm3 CRT and CM3 calma CRT 73 * layer pseudo_rmetal3 CRT and-not rm3 calma CRT 73 * layer m3p CMTP labels CMTP calma CMTP 83 * layer m234c CV3 and CV2 and-not XP grow 20 and CM4 and CM3 and CM2 grow 20 shrink 20 calma CV3 30 * layer m4 CM4 and-not CRM and-not CRQ and-not XP labels CM4 calma CM4 31 * layer rm4 CRM and CM4 calma CRM 70 * layer rm4 CRQ and CM4 calma CRQ 74 * layer pseudo_rmetal4 CRQ and-not rm4 calma CRQ 74 * layer m4p CMQP labels CMQP calma CMQP 84 * layer m4c CV3 and-not CV2 and-not XP grow 20 and CM4 and CM3 grow 20 shrink 20 calma CV3 30 * layer pad XP labels pad calma XP 26 * layer glass COG and-not COP and-not XP labels COG calma COG 52 * layer nfi CFI and CWN labels CFI calma CFI 27 * layer pfi CFI and-not CWN labels CFI calma CFI 27 * layer sb CSB and-not CWNR labels CSB calma CSB 29 * layer pres CPG and CSB calma CPG 46 * layer anres CAA and CSN and-not CWNR and-not CTA and CSB and-not CPG and-not CWN and-not CSP and-not CBA calma CAA 43 * layer apres CAA and CSP and-not CWNR and-not CTA and CSB and-not CPG and CWN and-not CSN and-not CPS and-not CBA calma CAA 43 * layer comment CX labels CX calma CX 63 * calma CTA 60 * #CRE/CRM calma CRW 65 * calma CRG 67 * calma CRD 66 * calma CRE 64 * calma CRF 71 * calma CRS 72 * calma CRT 73 * calma CRQ 74 * calma CRM 70 * style lambda=0.20(ps) scalefactor 20 layer nwell CWN and-not CWNR and-not CTA labels CWN calma CWN 42 * layer rnw CWN and-not CWNR and CRE and-not CSB and-not CRD and-not CAA and-not CPG calma CWN 42 * layer rnw CWN and-not CWNR and CRW and-not CRD and-not CAA and-not CPG calma CWN 42 * layer pseudo_rnwell CRW and-not CRE calma CRW 65 * calma CWNR 91 * layer nwr CWND calma CWND 92 * layer pseudo_nwr CRNW calma CRNW 93 * layer pwell CWP and-not CTA labels CWP calma CWP 41 * layer diff CAA and-not CTA and-not CPG and-not CWNR and-not COP and-not CSN and-not CSP labels CAA calma CAA 43 * layer tran CAA and-not CTA and CPG and-not CWNR and-not COP and-not CSN and-not CSP labels CAA calma CAA 43 * layer nselect CSN calma CSN 45 * layer pselect CSP calma CSP 44 * layer ndiff CAA and CSN and-not CWNR and-not CTA and-not CRE and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer rnd CAA and CSN and-not CWNR and CRE and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA calma CAA 43 * layer rnd CAA and CSN and-not CWNR and CRD and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA calma CAA 43 * layer pseudo_rndiff CRD and-not CRE and-not CAA and-not CSB and-not CPG and-not CWN and-not CSP and CSN and-not CBA calma CRD 66 * layer pdiff CAA and CSP and-not CWNR and-not CTA and-not CRE and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer rpd CAA and CSP and-not CWNR and CRE and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CAA 43 * layer rpd CAA and CSP and-not CWNR and CRD and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CAA 43 * layer pseudo_rpdiff CRD and-not CRE and-not CAA and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CRD 66 * layer nfet CAA and CSN and-not CWNR and-not CTA and CPG and-not CEL and-not CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer pfet CAA and CSP and-not CWNR and-not CTA and CPG and-not CEL and CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer nsd CAA and CSN and-not CWNR and-not CTA and CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer psd CAA and CSP and-not CWNR and-not CTA and-not CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer nwsd CAA and CSN and CWNR shrink 100 and-not CTA and CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer ndc CAA and CSN and CCA and-not CV1 and-not CWNR and-not CTA and-not CWN and CM1 grow 20 grow 10 shrink 10 calma CCA 48 * layer ndc CAA and CSN and CCC and-not CV1 and-not CWNR and-not CTA and-not CWN and CM1 grow 20 grow 10 shrink 10 calma CCC 25 * layer nsc CAA and CSN and CCA and-not CV1 and-not CWNR and-not CTA and CWN and CM1 grow 20 grow 10 shrink 10 calma CCA 48 * layer nsc CAA and CSN and CCC and-not CV1 and-not CWNR and-not CTA and CWN and CM1 grow 20 grow 10 shrink 10 calma CCC 25 * layer nwsc CAA and CSN and-not CV1 and CWNR shrink 100 and-not CTA and CCA and CWN and CM1 grow 40 grow 10 shrink 10 calma CCA 48 * layer nwsc CAA and CSN and-not CV1 and CWNR shrink 105 and-not CTA and CCC and CWN and CM1 grow 40 grow 10 shrink 10 calma CCC 25 * layer pdc CAA and CSP and CCA and-not CV1 and-not CTA and-not CPS and CWN and CM1 grow 20 grow 10 shrink 10 calma CCA 48 * layer pdc CAA and CSP and CCC and-not CV1 and-not CTA and-not CPS and CWN and CM1 grow 20 grow 10 shrink 10 calma CCC 25 * layer psc CAA and CSP and CCA and-not CV1 and-not CTA and-not CPS and-not CWN and CM1 grow 20 grow 10 shrink 10 calma CCA 48 * layer psc CAA and CSP and CCC and-not CV1 and-not CWNR and-not CTA and-not CPS and-not CWN and CM1 grow 20 grow 10 shrink 10 calma CCC 25 * layer ndc CAA and CSN and CCA and CV1 and CV2 and-not CV3 and-not CWNR and-not CTA and-not CWN and CM1 grow 20 grow 10 shrink 10 calma CCA 48 * layer ndc CAA and CSN and CCC and CV1 and CV2 and-not CV3 and-not CWNR and-not CTA and-not CWN and CM1 grow 20 grow 10 shrink 10 calma CCC 25 * layer nsc CAA and CSN and CCA and CV1 and CV2 and-not CV3 and-not CWNR and-not CTA and CWN and CM1 grow 20 grow 10 shrink 10 calma CCA 48 * layer nsc CAA and CSN and CCC and CV1 and CV2 and-not CV3 and-not CWNR and-not CTA and CWN and CM1 grow 20 grow 10 shrink 10 calma CCC 25 * layer nwsc CAA and CSN and CV1 and CV2 and-not CV3 and CWNR shrink 100 and-not CTA and CCA and CWN and CM1 grow 40 grow 10 shrink 10 calma CCA 48 * layer nwsc CAA and CSN and CV1 and CV2 and-not CV3 and CWNR shrink 105 and-not CTA and CCC and CWN and CM1 grow 40 grow 10 shrink 10 calma CCC 25 * layer pdc CAA and CSP and CCA and CV1 and CV2 and-not CV3 and-not CTA and-not CPS and CWN and CM1 grow 20 grow 10 shrink 10 calma CCA 48 * layer pdc CAA and CSP and CCC and CV1 and CV2 and-not CV3 and-not CTA and-not CPS and CWN and CM1 grow 20 grow 10 shrink 10 calma CCC 25 * layer psc CAA and CSP and CCA and CV1 and CV2 and-not CV3 and-not CTA and-not CPS and-not CWN and CM1 grow 20 grow 10 shrink 10 calma CCA 48 * layer psc CAA and CSP and CCC and CV1 and CV2 and-not CV3 and-not CWNR and-not CTA and-not CPS and-not CWN and CM1 grow 20 grow 10 shrink 10 calma CCC 25 * layer poly CPG and-not CRE labels CPG calma CPG 46 * layer rp CPG and CRE and-not CSB calma CPG 46 * layer rp CPG and CRG calma CPG 46 * layer pseudo_rpoly CRG and-not CRE calma CRG 67 * layer pc CCP and-not CV1 and CPG and-not CPC and-not CEL and-not CAA grow 20 and CM1 grow 10 shrink 10 calma CCP 47 * layer pc CCC and-not CV1 and CPG and-not CPC and-not CEL and-not CAA grow 20 and CM1 grow 10 shrink 10 calma CCC 25 * layer pc CCP and CV1 and CV2 and-not CV3 and CPG and-not CPC and-not CEL and-not CAA grow 20 and CM1 grow 10 shrink 10 calma CCP 47 * layer pc CCC and CV1 and CV2 and-not CV3 and CPG and-not CPC and-not CEL and-not CAA grow 20 and CM1 grow 10 shrink 10 calma CCC 25 * layer gc CCP and-not CPG and-not CPC calma CCP 47 * layer gc CCP and-not CM1 calma CCP 47 * layer gc CCA and-not COP and-not CAA and-not CBA calma CCA 48 * layer gc CCA and-not COP and-not CM1 calma CCA 48 * layer gc CCC and-not COP and-not CPG and-not CPC and-not CEL and-not CAA and-not CBA calma CCC 25 * layer gc CCC and-not COP and-not CM1 calma CCC 25 * layer gc CCE and-not CPC and-not CEL calma CCE 55 * layer gc CCE and-not CM1 calma CCE 55 * layer gv1 CV1 and-not COP and-not CM1 calma CV1 50 * layer gv1 CV1 and-not COP and-not CM2 calma CV1 50 * layer gv2 CV2 and-not COP and-not CM2 calma CV2 61 * layer gv2 CV2 and-not COP and-not CM3 calma CV2 61 * layer gv3 CV3 and-not COP and-not CM3 calma CV3 30 * layer gv3 CV3 and-not COP and-not CM4 calma CV3 30 * layer m2c CV1 and-not CV2 and-not CCC and-not CCP and-not CCA and-not XP grow 20 and CM2 and CM1 grow 10 shrink 10 calma CV1 50 * layer m2c CV1 and CV2 and CV3 and-not CCC and-not CCP and-not CCA and-not XP grow 20 and CM2 and CM1 grow 10 shrink 10 calma CV1 50 * layer pm12c CV1 and-not CV2 and CCP grow 20 and CM2 and CM1 and CPG grow 10 shrink 10 calma CV1 50 * layer pm12c CV1 and-not CV2 and CCC grow 20 and CM2 and CM1 and CPG grow 10 shrink 10 calma CV1 50 * layer pm12c CV1 and CV2 and CV3 and CCP grow 20 and CM2 and CM1 and CPG grow 10 shrink 10 calma CV1 50 * layer pm12c CV1 and CV2 and CV3 and CCC grow 20 and CM2 and CM1 and CPG grow 10 shrink 10 calma CV1 50 * layer m1 CM1 and-not CRM and-not CRF and-not XP labels CM1 calma CM1 49 * layer rm1 CRM and CM1 calma CRM 70 * layer rm1 CRF and CM1 calma CRF 71 * layer pseudo_rmetal1 CRF and-not rm1 calma CRF 71 * layer m1p CMFP labels CMFP calma CMFP 81 * layer m2 CM2 and-not CRM and-not CRS and-not XP labels CM2 calma CM2 51 * layer rm2 CRM and CM2 calma CRM 70 * layer rm2 CRS and CM2 calma CRS 72 * layer pseudo_rmetal2 CRS and-not rm2 calma CRS 72 * layer m2p CMSP labels CMSP calma CMSP 82 * layer ndm12c CAA and CSN and CV1 and-not CV2 and-not CWNR and-not CTA and CCA grow 20 and CM1 and CM2 and-not CWN grow 10 shrink 10 calma CV1 50 * layer ndm12c CAA and CSN and CV1 and-not CV2 and-not CWNR and-not CTA and CCC grow 20 and CM1 and CM2 grow 10 shrink 10 calma CV1 50 * layer pdm12c CAA and CSP and CV1 and-not CV2 and-not CTA and CCA grow 20 and CM1 and CM2 and CWN grow 10 shrink 10 calma CV1 50 * layer pdm12c CAA and CSP and CV1 and-not CV2 and-not CTA and CCC grow 20 and CM1 and CM2 and CWN grow 10 shrink 10 calma CV1 50 * layer nsm12c CAA and CSN and CV1 and-not CV2 and-not CWNR and-not CTA and CCA grow 20 and CM1 and CM2 and CWN grow 10 shrink 10 calma CV1 50 * layer nsm12c CAA and CSN and CV1 and-not CV2 and-not CWNR and-not CTA and CCC grow 20 and CM1 and CM2 and CWN grow 10 shrink 10 calma CV1 50 * layer psm12c CAA and CSP and CV1 and-not CV2 and-not CTA and CCA grow 20 and CM1 and CM2 and-not CWN grow 10 shrink 10 calma CV1 50 * layer psm12c CAA and CSP and CV1 and-not CV2 and-not CTA and CCC grow 20 and CM1 and CM2 and-not CWN grow 10 shrink 10 calma CV1 50 * layer nwsm12c CAA and CSN and CV1 and-not CV2 and CWNR and-not CTA and CCA grow 20 and CM1 and CM2 and CWN grow 10 shrink 10 calma CV1 50 * layer nwsm12c CAA and CSN and CV1 and-not CV2 and CWNR and-not CTA and CCC grow 20 and CM1 and CM2 and CWN grow 10 shrink 10 calma CV1 50 * layer ndm12c CAA and CSN and CV1 and CV2 and CV3 and-not CWNR and-not CTA and CCA grow 20 and CM1 and CM2 and-not CWN grow 10 shrink 10 calma CV1 50 * layer ndm12c CAA and CSN and CV1 and CV2 and CV3 and-not CWNR and-not CTA and CCC grow 20 and CM1 and CM2 grow 10 shrink 10 calma CV1 50 * layer pdm12c CAA and CSP and CV1 and CV2 and CV3 and-not CTA and CCA grow 20 and CM1 and CM2 and CWN grow 10 shrink 10 calma CV1 50 * layer pdm12c CAA and CSP and CV1 and CV2 and CV3 and-not CTA and CCC grow 20 and CM1 and CM2 and CWN grow 10 shrink 10 calma CV1 50 * layer nsm12c CAA and CSN and CV1 and CV2 and CV3 and-not CWNR and-not CTA and CCA grow 20 and CM1 and CM2 and CWN grow 10 shrink 10 calma CV1 50 * layer nsm12c CAA and CSN and CV1 and CV2 and CV3 and-not CWNR and-not CTA and CCC grow 20 and CM1 and CM2 and CWN grow 10 shrink 10 calma CV1 50 * layer psm12c CAA and CSP and CV1 and CV2 and CV3 and-not CTA and CCA grow 20 and CM1 and CM2 and-not CWN grow 10 shrink 10 calma CV1 50 * layer psm12c CAA and CSP and CV1 and CV2 and CV3 and-not CTA and CCC grow 20 and CM1 and CM2 and-not CWN grow 10 shrink 10 calma CV1 50 * layer nwsm12c CAA and CSN and CV1 and CV2 and CV3 and CWNR and-not CTA and CCA grow 20 and CM1 and CM2 and CWN grow 10 shrink 10 calma CV1 50 * layer nwsm12c CAA and CSN and CV1 and CV2 and CV3 and CWNR and-not CTA and CCC grow 20 and CM1 and CM2 and CWN grow 10 shrink 10 calma CV1 50 * layer fp 100 calma 100 100 * layer fm1 101 calma 101 101 * layer fm2 102 calma 102 102 * layer fm3 103 calma 103 103 * layer fm4 104 calma 104 104 * layer fa 109 calma 109 109 * layer fn 119 calma 119 119 * layer fapm 110 calma 110 110 * layer m3c CV2 and-not CV3 and-not CV1 and-not XP grow 20 and CM3 and CM2 grow 10 shrink 10 calma CV2 61 * layer m123c CV2 and-not CV3 and CV1 and-not XP grow 20 and CM3 and CM2 and CM1 grow 10 shrink 10 calma CV2 61 * layer m3 CM3 and-not CRM and-not CRT and-not XP labels CM3 calma CM3 62 * layer rm3 CRM and CM3 calma CRM 70 * layer rm3 CRT and CM3 calma CRT 73 * layer pseudo_rmetal3 CRT and-not rm3 calma CRT 73 * layer m3p CMTP labels CMTP calma CMTP 83 * layer m234c CV3 and CV2 and-not XP grow 20 and CM4 and CM3 and CM2 grow 20 shrink 20 calma CV3 30 * layer m4 CM4 and-not CRM and-not CRQ and-not XP labels CM4 calma CM4 31 * layer rm4 CRM and CM4 calma CRM 70 * layer rm4 CRQ and CM4 calma CRQ 74 * layer pseudo_rmetal4 CRQ and-not rm4 calma CRQ 74 * layer m4p CMQP labels CMQP calma CMQP 84 * layer m4c CV3 and-not CV2 and-not XP grow 20 and CM4 and CM3 grow 20 shrink 20 calma CV3 30 * layer pad XP labels pad calma XP 26 * layer glass COG and-not COP and-not XP labels COG calma COG 52 * layer nfi CFI and CWN labels CFI calma CFI 27 * layer pfi CFI and-not CWN labels CFI calma CFI 27 * layer sb CSB and-not CWNR labels CSB calma CSB 29 * layer pres CPG and CSB calma CPG 46 * layer anres CAA and CSN and-not CWNR and-not CTA and CSB and-not CPG and-not CWN and-not CSP and-not CBA calma CAA 43 * layer apres CAA and CSP and-not CWNR and-not CTA and CSB and-not CPG and CWN and-not CSN and-not CPS and-not CBA calma CAA 43 * layer comment CX labels CX calma CX 63 * calma CTA 60 * #CRE/CRM calma CRW 65 * calma CRG 67 * calma CRD 66 * calma CRE 64 * calma CRF 71 * calma CRS 72 * calma CRT 73 * calma CRQ 74 * calma CRM 70 * style lambda=0.20() scalefactor 20 layer nwell CWN and-not CWNR and-not CTA labels CWN calma CWN 42 * layer rnw CWN and-not CWNR and CRE and-not CSB and-not CRD and-not CAA and-not CPG calma CWN 42 * layer rnw CWN and-not CWNR and CRW and-not CRD and-not CAA and-not CPG calma CWN 42 * layer pseudo_rnwell CRW and-not CRE calma CRW 65 * calma CWNR 91 * layer nwr CWND calma CWND 92 * layer pseudo_nwr CRNW calma CRNW 93 * ignore CWP calma CWP 41 * layer diff CAA and-not CTA and-not CPG and-not CWNR and-not COP and-not CSN and-not CSP labels CAA calma CAA 43 * layer tran CAA and-not CTA and CPG and-not CWNR and-not COP and-not CSN and-not CSP labels CAA calma CAA 43 * calma CSN 45 * calma CSP 44 * layer ndiff CAA and CSN and-not CWNR and-not CTA and-not CRE and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer rnd CAA and CSN and-not CWNR and CRE and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA calma CAA 43 * layer rnd CAA and CSN and-not CWNR and CRD and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA calma CAA 43 * layer pseudo_rndiff CRD and-not CRE and-not CAA and-not CSB and-not CPG and-not CWN and-not CSP and CSN and-not CBA calma CRD 66 * layer pdiff CAA and CSP and-not CWNR and-not CTA and-not CRE and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer rpd CAA and CSP and-not CWNR and CRE and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CAA 43 * layer rpd CAA and CSP and-not CWNR and CRD and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CAA 43 * layer pseudo_rpdiff CRD and-not CRE and-not CAA and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CRD 66 * layer nfet CAA and CSN and-not CWNR and-not CTA and CPG and-not CEL and-not CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer pfet CAA and CSP and-not CWNR and-not CTA and CPG and-not CEL and CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer nsd CAA and CSN and-not CWNR and-not CTA and CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer psd CAA and CSP and-not CWNR and-not CTA and-not CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer nwsd CAA and CSN and CWNR shrink 100 and-not CTA and CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer ndc CAA and CSN and CCA and-not CV1 and-not CWNR and-not CTA and-not CWN and CM1 grow 20 grow 10 shrink 10 calma CCA 48 * layer ndc CAA and CSN and CCC and-not CV1 and-not CWNR and-not CTA and-not CWN and CM1 grow 20 grow 10 shrink 10 calma CCC 25 * layer nsc CAA and CSN and CCA and-not CV1 and-not CWNR and-not CTA and CWN and CM1 grow 20 grow 10 shrink 10 calma CCA 48 * layer nsc CAA and CSN and CCC and-not CV1 and-not CWNR and-not CTA and CWN and CM1 grow 20 grow 10 shrink 10 calma CCC 25 * layer nwsc CAA and CSN and-not CV1 and CWNR shrink 100 and-not CTA and CCA and CWN and CM1 grow 40 grow 10 shrink 10 calma CCA 48 * layer nwsc CAA and CSN and-not CV1 and CWNR shrink 105 and-not CTA and CCC and CWN and CM1 grow 40 grow 10 shrink 10 calma CCC 25 * layer pdc CAA and CSP and CCA and-not CV1 and-not CTA and-not CPS and CWN and CM1 grow 20 grow 10 shrink 10 calma CCA 48 * layer pdc CAA and CSP and CCC and-not CV1 and-not CTA and-not CPS and CWN and CM1 grow 20 grow 10 shrink 10 calma CCC 25 * layer psc CAA and CSP and CCA and-not CV1 and-not CTA and-not CPS and-not CWN and CM1 grow 20 grow 10 shrink 10 calma CCA 48 * layer psc CAA and CSP and CCC and-not CV1 and-not CWNR and-not CTA and-not CPS and-not CWN and CM1 grow 20 grow 10 shrink 10 calma CCC 25 * layer ndc CAA and CSN and CCA and CV1 and CV2 and-not CV3 and-not CWNR and-not CTA and-not CWN and CM1 grow 20 grow 10 shrink 10 calma CCA 48 * layer ndc CAA and CSN and CCC and CV1 and CV2 and-not CV3 and-not CWNR and-not CTA and-not CWN and CM1 grow 20 grow 10 shrink 10 calma CCC 25 * layer nsc CAA and CSN and CCA and CV1 and CV2 and-not CV3 and-not CWNR and-not CTA and CWN and CM1 grow 20 grow 10 shrink 10 calma CCA 48 * layer nsc CAA and CSN and CCC and CV1 and CV2 and-not CV3 and-not CWNR and-not CTA and CWN and CM1 grow 20 grow 10 shrink 10 calma CCC 25 * layer nwsc CAA and CSN and CV1 and CV2 and-not CV3 and CWNR shrink 100 and-not CTA and CCA and CWN and CM1 grow 40 grow 10 shrink 10 calma CCA 48 * layer nwsc CAA and CSN and CV1 and CV2 and-not CV3 and CWNR shrink 105 and-not CTA and CCC and CWN and CM1 grow 40 grow 10 shrink 10 calma CCC 25 * layer pdc CAA and CSP and CCA and CV1 and CV2 and-not CV3 and-not CTA and-not CPS and CWN and CM1 grow 20 grow 10 shrink 10 calma CCA 48 * layer pdc CAA and CSP and CCC and CV1 and CV2 and-not CV3 and-not CTA and-not CPS and CWN and CM1 grow 20 grow 10 shrink 10 calma CCC 25 * layer psc CAA and CSP and CCA and CV1 and CV2 and-not CV3 and-not CTA and-not CPS and-not CWN and CM1 grow 20 grow 10 shrink 10 calma CCA 48 * layer psc CAA and CSP and CCC and CV1 and CV2 and-not CV3 and-not CWNR and-not CTA and-not CPS and-not CWN and CM1 grow 20 grow 10 shrink 10 calma CCC 25 * layer poly CPG and-not CRE labels CPG calma CPG 46 * layer rp CPG and CRE and-not CSB calma CPG 46 * layer rp CPG and CRG calma CPG 46 * layer pseudo_rpoly CRG and-not CRE calma CRG 67 * layer pc CCP and-not CV1 and CPG and-not CPC and-not CEL and-not CAA grow 20 and CM1 grow 10 shrink 10 calma CCP 47 * layer pc CCC and-not CV1 and CPG and-not CPC and-not CEL and-not CAA grow 20 and CM1 grow 10 shrink 10 calma CCC 25 * layer pc CCP and CV1 and CV2 and-not CV3 and CPG and-not CPC and-not CEL and-not CAA grow 20 and CM1 grow 10 shrink 10 calma CCP 47 * layer pc CCC and CV1 and CV2 and-not CV3 and CPG and-not CPC and-not CEL and-not CAA grow 20 and CM1 grow 10 shrink 10 calma CCC 25 * layer gc CCP and-not CPG and-not CPC calma CCP 47 * layer gc CCP and-not CM1 calma CCP 47 * layer gc CCA and-not COP and-not CAA and-not CBA calma CCA 48 * layer gc CCA and-not COP and-not CM1 calma CCA 48 * layer gc CCC and-not COP and-not CPG and-not CPC and-not CEL and-not CAA and-not CBA calma CCC 25 * layer gc CCC and-not COP and-not CM1 calma CCC 25 * layer gc CCE and-not CPC and-not CEL calma CCE 55 * layer gc CCE and-not CM1 calma CCE 55 * layer gv1 CV1 and-not COP and-not CM1 calma CV1 50 * layer gv1 CV1 and-not COP and-not CM2 calma CV1 50 * layer gv2 CV2 and-not COP and-not CM2 calma CV2 61 * layer gv2 CV2 and-not COP and-not CM3 calma CV2 61 * layer gv3 CV3 and-not COP and-not CM3 calma CV3 30 * layer gv3 CV3 and-not COP and-not CM4 calma CV3 30 * layer m2c CV1 and-not CV2 and-not CCC and-not CCP and-not CCA and-not XP grow 20 and CM2 and CM1 grow 10 shrink 10 calma CV1 50 * layer m2c CV1 and CV2 and CV3 and-not CCC and-not CCP and-not CCA and-not XP grow 20 and CM2 and CM1 grow 10 shrink 10 calma CV1 50 * layer pm12c CV1 and-not CV2 and CCP grow 20 and CM2 and CM1 and CPG grow 10 shrink 10 calma CV1 50 * layer pm12c CV1 and-not CV2 and CCC grow 20 and CM2 and CM1 and CPG grow 10 shrink 10 calma CV1 50 * layer pm12c CV1 and CV2 and CV3 and CCP grow 20 and CM2 and CM1 and CPG grow 10 shrink 10 calma CV1 50 * layer pm12c CV1 and CV2 and CV3 and CCC grow 20 and CM2 and CM1 and CPG grow 10 shrink 10 calma CV1 50 * layer m1 CM1 and-not CRM and-not CRF and-not XP labels CM1 calma CM1 49 * layer rm1 CRM and CM1 calma CRM 70 * layer rm1 CRF and CM1 calma CRF 71 * layer pseudo_rmetal1 CRF and-not rm1 calma CRF 71 * layer m1p CMFP labels CMFP calma CMFP 81 * layer m2 CM2 and-not CRM and-not CRS and-not XP labels CM2 calma CM2 51 * layer rm2 CRM and CM2 calma CRM 70 * layer rm2 CRS and CM2 calma CRS 72 * layer pseudo_rmetal2 CRS and-not rm2 calma CRS 72 * layer m2p CMSP labels CMSP calma CMSP 82 * layer ndm12c CAA and CSN and CV1 and-not CV2 and-not CWNR and-not CTA and CCA grow 20 and CM1 and CM2 and-not CWN grow 10 shrink 10 calma CV1 50 * layer ndm12c CAA and CSN and CV1 and-not CV2 and-not CWNR and-not CTA and CCC grow 20 and CM1 and CM2 grow 10 shrink 10 calma CV1 50 * layer pdm12c CAA and CSP and CV1 and-not CV2 and-not CTA and CCA grow 20 and CM1 and CM2 and CWN grow 10 shrink 10 calma CV1 50 * layer pdm12c CAA and CSP and CV1 and-not CV2 and-not CTA and CCC grow 20 and CM1 and CM2 and CWN grow 10 shrink 10 calma CV1 50 * layer nsm12c CAA and CSN and CV1 and-not CV2 and-not CWNR and-not CTA and CCA grow 20 and CM1 and CM2 and CWN grow 10 shrink 10 calma CV1 50 * layer nsm12c CAA and CSN and CV1 and-not CV2 and-not CWNR and-not CTA and CCC grow 20 and CM1 and CM2 and CWN grow 10 shrink 10 calma CV1 50 * layer psm12c CAA and CSP and CV1 and-not CV2 and-not CTA and CCA grow 20 and CM1 and CM2 and-not CWN grow 10 shrink 10 calma CV1 50 * layer psm12c CAA and CSP and CV1 and-not CV2 and-not CTA and CCC grow 20 and CM1 and CM2 and-not CWN grow 10 shrink 10 calma CV1 50 * layer nwsm12c CAA and CSN and CV1 and-not CV2 and CWNR and-not CTA and CCA grow 20 and CM1 and CM2 and CWN grow 10 shrink 10 calma CV1 50 * layer nwsm12c CAA and CSN and CV1 and-not CV2 and CWNR and-not CTA and CCC grow 20 and CM1 and CM2 and CWN grow 10 shrink 10 calma CV1 50 * layer ndm12c CAA and CSN and CV1 and CV2 and CV3 and-not CWNR and-not CTA and CCA grow 20 and CM1 and CM2 and-not CWN grow 10 shrink 10 calma CV1 50 * layer ndm12c CAA and CSN and CV1 and CV2 and CV3 and-not CWNR and-not CTA and CCC grow 20 and CM1 and CM2 grow 10 shrink 10 calma CV1 50 * layer pdm12c CAA and CSP and CV1 and CV2 and CV3 and-not CTA and CCA grow 20 and CM1 and CM2 and CWN grow 10 shrink 10 calma CV1 50 * layer pdm12c CAA and CSP and CV1 and CV2 and CV3 and-not CTA and CCC grow 20 and CM1 and CM2 and CWN grow 10 shrink 10 calma CV1 50 * layer nsm12c CAA and CSN and CV1 and CV2 and CV3 and-not CWNR and-not CTA and CCA grow 20 and CM1 and CM2 and CWN grow 10 shrink 10 calma CV1 50 * layer nsm12c CAA and CSN and CV1 and CV2 and CV3 and-not CWNR and-not CTA and CCC grow 20 and CM1 and CM2 and CWN grow 10 shrink 10 calma CV1 50 * layer psm12c CAA and CSP and CV1 and CV2 and CV3 and-not CTA and CCA grow 20 and CM1 and CM2 and-not CWN grow 10 shrink 10 calma CV1 50 * layer psm12c CAA and CSP and CV1 and CV2 and CV3 and-not CTA and CCC grow 20 and CM1 and CM2 and-not CWN grow 10 shrink 10 calma CV1 50 * layer nwsm12c CAA and CSN and CV1 and CV2 and CV3 and CWNR and-not CTA and CCA grow 20 and CM1 and CM2 and CWN grow 10 shrink 10 calma CV1 50 * layer nwsm12c CAA and CSN and CV1 and CV2 and CV3 and CWNR and-not CTA and CCC grow 20 and CM1 and CM2 and CWN grow 10 shrink 10 calma CV1 50 * layer fp 100 calma 100 100 * layer fm1 101 calma 101 101 * layer fm2 102 calma 102 102 * layer fm3 103 calma 103 103 * layer fm4 104 calma 104 104 * layer fa 109 calma 109 109 * layer fn 119 calma 119 119 * layer fapm 110 calma 110 110 * layer m3c CV2 and-not CV3 and-not CV1 and-not XP grow 20 and CM3 and CM2 grow 10 shrink 10 calma CV2 61 * layer m123c CV2 and-not CV3 and CV1 and-not XP grow 20 and CM3 and CM2 and CM1 grow 10 shrink 10 calma CV2 61 * layer m3 CM3 and-not CRM and-not CRT and-not XP labels CM3 calma CM3 62 * layer rm3 CRM and CM3 calma CRM 70 * layer rm3 CRT and CM3 calma CRT 73 * layer pseudo_rmetal3 CRT and-not rm3 calma CRT 73 * layer m3p CMTP labels CMTP calma CMTP 83 * layer m234c CV3 and CV2 and-not XP grow 20 and CM4 and CM3 and CM2 grow 20 shrink 20 calma CV3 30 * layer m4 CM4 and-not CRM and-not CRQ and-not XP labels CM4 calma CM4 31 * layer rm4 CRM and CM4 calma CRM 70 * layer rm4 CRQ and CM4 calma CRQ 74 * layer pseudo_rmetal4 CRQ and-not rm4 calma CRQ 74 * layer m4p CMQP labels CMQP calma CMQP 84 * layer m4c CV3 and-not CV2 and-not XP grow 20 and CM4 and CM3 grow 20 shrink 20 calma CV3 30 * layer pad XP labels pad calma XP 26 * layer glass COG and-not COP and-not XP labels COG calma COG 52 * layer nfi CFI and CWN labels CFI calma CFI 27 * layer pfi CFI and-not CWN labels CFI calma CFI 27 * layer sb CSB and-not CWNR labels CSB calma CSB 29 * layer pres CPG and CSB calma CPG 46 * layer anres CAA and CSN and-not CWNR and-not CTA and CSB and-not CPG and-not CWN and-not CSP and-not CBA calma CAA 43 * layer apres CAA and CSP and-not CWNR and-not CTA and CSB and-not CPG and CWN and-not CSN and-not CPS and-not CBA calma CAA 43 * layer comment CX labels CX calma CX 63 * calma CTA 60 * #CRE/CRM calma CRW 65 * calma CRG 67 * calma CRD 66 * calma CRE 64 * calma CRF 71 * calma CRS 72 * calma CRT 73 * calma CRQ 74 * calma CRM 70 * style lambda=0.20(c) scalefactor 20 layer nwell CWN and-not CWNR and-not CTA labels CWN calma CWN 42 * layer rnw CWN and-not CWNR and CRE and-not CSB and-not CRD and-not CAA and-not CPG calma CWN 42 * layer rnw CWN and-not CWNR and CRW and-not CRD and-not CAA and-not CPG calma CWN 42 * layer pseudo_rnwell CRW and-not CRE calma CRW 65 * calma CWNR 91 * layer nwr CWND calma CWND 92 * layer pseudo_nwr CRNW calma CRNW 93 * ignore CWP calma CWP 41 * layer diff CAA and-not CTA and-not CPG and-not CWNR and-not COP and-not CSN and-not CSP labels CAA calma CAA 43 * layer tran CAA and-not CTA and CPG and-not CWNR and-not COP and-not CSN and-not CSP labels CAA calma CAA 43 * calma CSN 45 * calma CSP 44 * layer ndiff CAA and CSN and-not CWNR and-not CTA and-not CRE and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer rnd CAA and CSN and-not CWNR and CRE and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA calma CAA 43 * layer rnd CAA and CSN and-not CWNR and CRD and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA calma CAA 43 * layer pseudo_rndiff CRD and-not CRE and-not CAA and-not CSB and-not CPG and-not CWN and-not CSP and CSN and-not CBA calma CRD 66 * layer pdiff CAA and CSP and-not CWNR and-not CTA and-not CRE and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer rpd CAA and CSP and-not CWNR and CRE and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CAA 43 * layer rpd CAA and CSP and-not CWNR and CRD and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CAA 43 * layer pseudo_rpdiff CRD and-not CRE and-not CAA and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CRD 66 * layer nfet CAA and CSN and-not CWNR and-not CTA and CPG and-not CEL and-not CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer pfet CAA and CSP and-not CWNR and-not CTA and CPG and-not CEL and CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer nsd CAA and CSN and-not CWNR and-not CTA and CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer psd CAA and CSP and-not CWNR and-not CTA and-not CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer nwsd CAA and CSN and CWNR shrink 100 and-not CTA and CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer gc CCA and CPG and-not CEL calma CCA 48 * layer gc CCP and CPG and-not CEL calma CCP 47 * layer gc CCC and CPG and-not CEL calma CCC 25 * layer gc CCE and CPG and-not CEL calma CCE 55 * layer gc CCA and-not COP and-not CPC and-not CEL calma CCA 48 * layer gc CCP and-not COP and-not CPC and-not CEL calma CCP 47 * layer gc CCC and-not COP and-not CPC and-not CEL calma CCC 25 * layer gc CCE and-not COP and-not CPC and-not CEL calma CCE 55 * layer poly CPG and-not CRE labels CPG calma CPG 46 * layer rp CPG and CRE and-not CSB calma CPG 46 * layer rp CPG and CRG calma CPG 46 * layer pseudo_rpoly CRG and-not CRE calma CRG 67 * layer m1 CM1 and-not CRM and-not CRF labels CM1 calma CM1 49 * layer rm1 CRM and CM1 calma CRM 70 * layer rm1 CRF and CM1 calma CRF 71 * layer pseudo_rmetal1 CRF and-not rm1 calma CRF 71 * layer m1p CMFP labels CMFP calma CMFP 81 * layer gv1 CV1 calma CV1 50 * layer m2 CM2 and-not CRM and-not CRS labels CM2 calma CM2 51 * layer rm2 CRM and CM2 calma CRM 70 * layer rm2 CRS and CM2 calma CRS 72 * layer pseudo_rmetal2 CRS and-not rm2 calma CRS 72 * layer m2p CMSP labels CMSP calma CMSP 82 * layer fp 100 calma 100 100 * layer fm1 101 calma 101 101 * layer fm2 102 calma 102 102 * layer fm3 103 calma 103 103 * layer fm4 104 calma 104 104 * layer fa 109 calma 109 109 * layer fn 119 calma 119 119 * layer fapm 110 calma 110 110 * layer gv2 CV2 calma CV2 61 * layer m3 CM3 and-not CRM and-not CRT labels CM3 calma CM3 62 * layer rm3 CRM and CM3 calma CRM 70 * layer rm3 CRT and CM3 calma CRT 73 * layer pseudo_rmetal3 CRT and-not rm3 calma CRT 73 * layer m3p CMTP labels CMTP calma CMTP 83 * layer gv3 CV3 calma CV3 30 * layer m4 CM4 and-not CRM and-not CRQ labels CM4 calma CM4 31 * layer rm4 CRM and CM4 calma CRM 70 * layer rm4 CRQ and CM4 calma CRQ 74 * layer pseudo_rmetal4 CRQ and-not rm4 calma CRQ 74 * layer m4p CMQP labels CMQP calma CMQP 84 * layer xp XP calma XP 26 * layer glass COG and-not COP labels COG calma COG 52 * layer nfi CFI and CWN labels CFI calma CFI 27 * layer pfi CFI and-not CWN labels CFI calma CFI 27 * layer sb CSB and-not CWNR labels CSB calma CSB 29 * layer pres CPG and CSB calma CPG 46 * layer anres CAA and CSN and-not CWNR and-not CTA and CSB and-not CPG and-not CWN and-not CSP and-not CBA calma CAA 43 * layer apres CAA and CSP and-not CWNR and-not CTA and CSB and-not CPG and CWN and-not CSN and-not CPS and-not CBA calma CAA 43 * layer comment CX labels CX calma CX 63 * calma CTA 60 * #CRE/CRM calma CRW 65 * calma CRG 67 * calma CRD 66 * calma CRE 64 * calma CRF 71 * calma CRS 72 * calma CRT 73 * calma CRQ 74 * calma CRM 70 * style lambda=0.20(cs) scalefactor 20 layer nwell CWN and-not CWNR and-not CTA labels CWN calma CWN 42 * layer rnw CWN and-not CWNR and CRE and-not CSB and-not CRD and-not CAA and-not CPG calma CWN 42 * layer rnw CWN and-not CWNR and CRW and-not CRD and-not CAA and-not CPG calma CWN 42 * layer pseudo_rnwell CRW and-not CRE calma CRW 65 * calma CWNR 91 * layer nwr CWND calma CWND 92 * layer pseudo_nwr CRNW calma CRNW 93 * ignore CWP calma CWP 41 * layer diff CAA and-not CTA and-not CPG and-not CWNR and-not COP and-not CSN and-not CSP labels CAA calma CAA 43 * layer tran CAA and-not CTA and CPG and-not CWNR and-not COP and-not CSN and-not CSP labels CAA calma CAA 43 * layer nselect CSN calma CSN 45 * layer pselect CSP calma CSP 44 * layer ndiff CAA and CSN and-not CWNR and-not CTA and-not CRE and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer rnd CAA and CSN and-not CWNR and CRE and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA calma CAA 43 * layer rnd CAA and CSN and-not CWNR and CRD and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA calma CAA 43 * layer pseudo_rndiff CRD and-not CRE and-not CAA and-not CSB and-not CPG and-not CWN and-not CSP and CSN and-not CBA calma CRD 66 * layer pdiff CAA and CSP and-not CWNR and-not CTA and-not CRE and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer rpd CAA and CSP and-not CWNR and CRE and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CAA 43 * layer rpd CAA and CSP and-not CWNR and CRD and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CAA 43 * layer pseudo_rpdiff CRD and-not CRE and-not CAA and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CRD 66 * layer nfet CAA and CSN and-not CWNR and-not CTA and CPG and-not CEL and-not CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer pfet CAA and CSP and-not CWNR and-not CTA and CPG and-not CEL and CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer nsd CAA and CSN and-not CWNR and-not CTA and CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer psd CAA and CSP and-not CWNR and-not CTA and-not CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer nwsd CAA and CSN and CWNR shrink 100 and-not CTA and CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer gc CCA and CPG and-not CEL calma CCA 48 * layer gc CCP and CPG and-not CEL calma CCP 47 * layer gc CCC and CPG and-not CEL calma CCC 25 * layer gc CCE and CPG and-not CEL calma CCE 55 * layer gc CCA and-not COP and-not CPC and-not CEL calma CCA 48 * layer gc CCP and-not COP and-not CPC and-not CEL calma CCP 47 * layer gc CCC and-not COP and-not CPC and-not CEL calma CCC 25 * layer gc CCE and-not COP and-not CPC and-not CEL calma CCE 55 * layer poly CPG and-not CRE labels CPG calma CPG 46 * layer rp CPG and CRE and-not CSB calma CPG 46 * layer rp CPG and CRG calma CPG 46 * layer pseudo_rpoly CRG and-not CRE calma CRG 67 * layer m1 CM1 and-not CRM and-not CRF labels CM1 calma CM1 49 * layer rm1 CRM and CM1 calma CRM 70 * layer rm1 CRF and CM1 calma CRF 71 * layer pseudo_rmetal1 CRF and-not rm1 calma CRF 71 * layer m1p CMFP labels CMFP calma CMFP 81 * layer gv1 CV1 calma CV1 50 * layer m2 CM2 and-not CRM and-not CRS labels CM2 calma CM2 51 * layer rm2 CRM and CM2 calma CRM 70 * layer rm2 CRS and CM2 calma CRS 72 * layer pseudo_rmetal2 CRS and-not rm2 calma CRS 72 * layer m2p CMSP labels CMSP calma CMSP 82 * layer fp 100 calma 100 100 * layer fm1 101 calma 101 101 * layer fm2 102 calma 102 102 * layer fm3 103 calma 103 103 * layer fm4 104 calma 104 104 * layer fa 109 calma 109 109 * layer fn 119 calma 119 119 * layer fapm 110 calma 110 110 * layer gv2 CV2 calma CV2 61 * layer m3 CM3 and-not CRM and-not CRT labels CM3 calma CM3 62 * layer rm3 CRM and CM3 calma CRM 70 * layer rm3 CRT and CM3 calma CRT 73 * layer pseudo_rmetal3 CRT and-not rm3 calma CRT 73 * layer m3p CMTP labels CMTP calma CMTP 83 * layer gv3 CV3 calma CV3 30 * layer m4 CM4 and-not CRM and-not CRQ labels CM4 calma CM4 31 * layer rm4 CRM and CM4 calma CRM 70 * layer rm4 CRQ and CM4 calma CRQ 74 * layer pseudo_rmetal4 CRQ and-not rm4 calma CRQ 74 * layer m4p CMQP labels CMQP calma CMQP 84 * layer xp XP calma XP 26 * layer glass COG and-not COP labels COG calma COG 52 * layer nfi CFI and CWN labels CFI calma CFI 27 * layer pfi CFI and-not CWN labels CFI calma CFI 27 * layer sb CSB and-not CWNR labels CSB calma CSB 29 * layer pres CPG and CSB calma CPG 46 * layer anres CAA and CSN and-not CWNR and-not CTA and CSB and-not CPG and-not CWN and-not CSP and-not CBA calma CAA 43 * layer apres CAA and CSP and-not CWNR and-not CTA and CSB and-not CPG and CWN and-not CSN and-not CPS and-not CBA calma CAA 43 * layer comment CX labels CX calma CX 63 * calma CTA 60 * #CRE/CRM calma CRW 65 * calma CRG 67 * calma CRD 66 * calma CRE 64 * calma CRF 71 * calma CRS 72 * calma CRT 73 * calma CRQ 74 * calma CRM 70 * style lambda=0.20(cps) scalefactor 20 layer nwell CWN and-not CWNR and-not CTA labels CWN calma CWN 42 * layer rnw CWN and-not CWNR and CRE and-not CSB and-not CRD and-not CAA and-not CPG calma CWN 42 * layer rnw CWN and-not CWNR and CRW and-not CRD and-not CAA and-not CPG calma CWN 42 * layer pseudo_rnwell CRW and-not CRE calma CRW 65 * calma CWNR 91 * layer nwr CWND calma CWND 92 * layer pseudo_nwr CRNW calma CRNW 93 * layer pwell CWP and-not CTA labels CWP calma CWP 41 * layer diff CAA and-not CTA and-not CPG and-not CWNR and-not COP and-not CSN and-not CSP labels CAA calma CAA 43 * layer tran CAA and-not CTA and CPG and-not CWNR and-not COP and-not CSN and-not CSP labels CAA calma CAA 43 * layer nselect CSN calma CSN 45 * layer pselect CSP calma CSP 44 * layer ndiff CAA and CSN and-not CWNR and-not CTA and-not CRE and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer rnd CAA and CSN and-not CWNR and CRE and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA calma CAA 43 * layer rnd CAA and CSN and-not CWNR and CRD and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA calma CAA 43 * layer pseudo_rndiff CRD and-not CRE and-not CAA and-not CSB and-not CPG and-not CWN and-not CSP and CSN and-not CBA calma CRD 66 * layer pdiff CAA and CSP and-not CWNR and-not CTA and-not CRE and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer rpd CAA and CSP and-not CWNR and CRE and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CAA 43 * layer rpd CAA and CSP and-not CWNR and CRD and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CAA 43 * layer pseudo_rpdiff CRD and-not CRE and-not CAA and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CRD 66 * layer nfet CAA and CSN and-not CWNR and-not CTA and CPG and-not CEL and-not CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer pfet CAA and CSP and-not CWNR and-not CTA and CPG and-not CEL and CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer nsd CAA and CSN and-not CWNR and-not CTA and CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer psd CAA and CSP and-not CWNR and-not CTA and-not CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer nwsd CAA and CSN and CWNR shrink 100 and-not CTA and CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer gc CCA and CPG and-not CEL calma CCA 48 * layer gc CCP and CPG and-not CEL calma CCP 47 * layer gc CCC and CPG and-not CEL calma CCC 25 * layer gc CCE and CPG and-not CEL calma CCE 55 * layer gc CCA and-not COP and-not CPC and-not CEL calma CCA 48 * layer gc CCP and-not COP and-not CPC and-not CEL calma CCP 47 * layer gc CCC and-not COP and-not CPC and-not CEL calma CCC 25 * layer gc CCE and-not COP and-not CPC and-not CEL calma CCE 55 * layer poly CPG and-not CRE labels CPG calma CPG 46 * layer rp CPG and CRE and-not CSB calma CPG 46 * layer rp CPG and CRG calma CPG 46 * layer pseudo_rpoly CRG and-not CRE calma CRG 67 * layer m1 CM1 and-not CRM and-not CRF labels CM1 calma CM1 49 * layer rm1 CRM and CM1 calma CRM 70 * layer rm1 CRF and CM1 calma CRF 71 * layer pseudo_rmetal1 CRF and-not rm1 calma CRF 71 * layer m1p CMFP labels CMFP calma CMFP 81 * layer gv1 CV1 calma CV1 50 * layer m2 CM2 and-not CRM and-not CRS labels CM2 calma CM2 51 * layer rm2 CRM and CM2 calma CRM 70 * layer rm2 CRS and CM2 calma CRS 72 * layer pseudo_rmetal2 CRS and-not rm2 calma CRS 72 * layer m2p CMSP labels CMSP calma CMSP 82 * layer fp 100 calma 100 100 * layer fm1 101 calma 101 101 * layer fm2 102 calma 102 102 * layer fm3 103 calma 103 103 * layer fm4 104 calma 104 104 * layer fa 109 calma 109 109 * layer fn 119 calma 119 119 * layer fapm 110 calma 110 110 * layer gv2 CV2 calma CV2 61 * layer m3 CM3 and-not CRM and-not CRT labels CM3 calma CM3 62 * layer rm3 CRM and CM3 calma CRM 70 * layer rm3 CRT and CM3 calma CRT 73 * layer pseudo_rmetal3 CRT and-not rm3 calma CRT 73 * layer m3p CMTP labels CMTP calma CMTP 83 * layer gv3 CV3 calma CV3 30 * layer m4 CM4 and-not CRM and-not CRQ labels CM4 calma CM4 31 * layer rm4 CRM and CM4 calma CRM 70 * layer rm4 CRQ and CM4 calma CRQ 74 * layer pseudo_rmetal4 CRQ and-not rm4 calma CRQ 74 * layer m4p CMQP labels CMQP calma CMQP 84 * layer xp XP calma XP 26 * layer glass COG and-not COP labels COG calma COG 52 * layer nfi CFI and CWN labels CFI calma CFI 27 * layer pfi CFI and-not CWN labels CFI calma CFI 27 * layer sb CSB and-not CWNR labels CSB calma CSB 29 * layer pres CPG and CSB calma CPG 46 * layer anres CAA and CSN and-not CWNR and-not CTA and CSB and-not CPG and-not CWN and-not CSP and-not CBA calma CAA 43 * layer apres CAA and CSP and-not CWNR and-not CTA and CSB and-not CPG and CWN and-not CSN and-not CPS and-not CBA calma CAA 43 * layer comment CX labels CX calma CX 63 * calma CTA 60 * #CRE/CRM calma CRW 65 * calma CRG 67 * calma CRD 66 * calma CRE 64 * calma CRF 71 * calma CRS 72 * calma CRT 73 * calma CRQ 74 * calma CRM 70 * style lambda=0.20(cp) scalefactor 20 layer nwell CWN and-not CWNR and-not CTA labels CWN calma CWN 42 * layer rnw CWN and-not CWNR and CRE and-not CSB and-not CRD and-not CAA and-not CPG calma CWN 42 * layer rnw CWN and-not CWNR and CRW and-not CRD and-not CAA and-not CPG calma CWN 42 * layer pseudo_rnwell CRW and-not CRE calma CRW 65 * calma CWNR 91 * layer nwr CWND calma CWND 92 * layer pseudo_nwr CRNW calma CRNW 93 * layer pwell CWP and-not CTA labels CWP calma CWP 41 * layer diff CAA and-not CTA and-not CPG and-not CWNR and-not COP and-not CSN and-not CSP labels CAA calma CAA 43 * layer tran CAA and-not CTA and CPG and-not CWNR and-not COP and-not CSN and-not CSP labels CAA calma CAA 43 * calma CSN 45 * calma CSP 44 * layer ndiff CAA and CSN and-not CWNR and-not CTA and-not CRE and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer rnd CAA and CSN and-not CWNR and CRE and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA calma CAA 43 * layer rnd CAA and CSN and-not CWNR and CRD and-not CSB and-not CPG and-not CWN and-not CSP and-not CBA calma CAA 43 * layer pseudo_rndiff CRD and-not CRE and-not CAA and-not CSB and-not CPG and-not CWN and-not CSP and CSN and-not CBA calma CRD 66 * layer pdiff CAA and CSP and-not CWNR and-not CTA and-not CRE and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer rpd CAA and CSP and-not CWNR and CRE and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CAA 43 * layer rpd CAA and CSP and-not CWNR and CRD and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CAA 43 * layer pseudo_rpdiff CRD and-not CRE and-not CAA and-not CSB and-not CPG and CWN and-not CSN and-not CPS and CSP and-not CBA calma CRD 66 * layer nfet CAA and CSN and-not CWNR and-not CTA and CPG and-not CEL and-not CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer pfet CAA and CSP and-not CWNR and-not CTA and CPG and-not CEL and CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer nsd CAA and CSN and-not CWNR and-not CTA and CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer psd CAA and CSP and-not CWNR and-not CTA and-not CWN and-not CSN and-not CPS and CSP and-not CBA labels CAA calma CAA 43 * layer nwsd CAA and CSN and CWNR shrink 100 and-not CTA and CWN and-not CSP and-not CBA labels CAA calma CAA 43 * layer gc CCA and CPG and-not CEL calma CCA 48 * layer gc CCP and CPG and-not CEL calma CCP 47 * layer gc CCC and CPG and-not CEL calma CCC 25 * layer gc CCE and CPG and-not CEL calma CCE 55 * layer gc CCA and-not COP and-not CPC and-not CEL calma CCA 48 * layer gc CCP and-not COP and-not CPC and-not CEL calma CCP 47 * layer gc CCC and-not COP and-not CPC and-not CEL calma CCC 25 * layer gc CCE and-not COP and-not CPC and-not CEL calma CCE 55 * layer poly CPG and-not CRE labels CPG calma CPG 46 * layer rp CPG and CRE and-not CSB calma CPG 46 * layer rp CPG and CRG calma CPG 46 * layer pseudo_rpoly CRG and-not CRE calma CRG 67 * layer m1 CM1 and-not CRM and-not CRF labels CM1 calma CM1 49 * layer rm1 CRM and CM1 calma CRM 70 * layer rm1 CRF and CM1 calma CRF 71 * layer pseudo_rmetal1 CRF and-not rm1 calma CRF 71 * layer m1p CMFP labels CMFP calma CMFP 81 * layer gv1 CV1 calma CV1 50 * layer m2 CM2 and-not CRM and-not CRS labels CM2 calma CM2 51 * layer rm2 CRM and CM2 calma CRM 70 * layer rm2 CRS and CM2 calma CRS 72 * layer pseudo_rmetal2 CRS and-not rm2 calma CRS 72 * layer m2p CMSP labels CMSP calma CMSP 82 * layer fp 100 calma 100 100 * layer fm1 101 calma 101 101 * layer fm2 102 calma 102 102 * layer fm3 103 calma 103 103 * layer fm4 104 calma 104 104 * layer fa 109 calma 109 109 * layer fn 119 calma 119 119 * layer fapm 110 calma 110 110 * layer gv2 CV2 calma CV2 61 * layer m3 CM3 and-not CRM and-not CRT labels CM3 calma CM3 62 * layer rm3 CRM and CM3 calma CRM 70 * layer rm3 CRT and CM3 calma CRT 73 * layer pseudo_rmetal3 CRT and-not rm3 calma CRT 73 * layer m3p CMTP labels CMTP calma CMTP 83 * layer gv3 CV3 calma CV3 30 * layer m4 CM4 and-not CRM and-not CRQ labels CM4 calma CM4 31 * layer rm4 CRM and CM4 calma CRM 70 * layer rm4 CRQ and CM4 calma CRQ 74 * layer pseudo_rmetal4 CRQ and-not rm4 calma CRQ 74 * layer m4p CMQP labels CMQP calma CMQP 84 * layer xp XP calma XP 26 * layer glass COG and-not COP labels COG calma COG 52 * layer nfi CFI and CWN labels CFI calma CFI 27 * layer pfi CFI and-not CWN labels CFI calma CFI 27 * layer sb CSB and-not CWNR labels CSB calma CSB 29 * layer pres CPG and CSB calma CPG 46 * layer anres CAA and CSN and-not CWNR and-not CTA and CSB and-not CPG and-not CWN and-not CSP and-not CBA calma CAA 43 * layer apres CAA and CSP and-not CWNR and-not CTA and CSB and-not CPG and CWN and-not CSN and-not CPS and-not CBA calma CAA 43 * layer comment CX labels CX calma CX 63 * calma CTA 60 * #CRE/CRM calma CRW 65 * calma CRG 67 * calma CRD 66 * calma CRE 64 * calma CRF 71 * calma CRS 72 * calma CRT 73 * calma CRQ 74 * calma CRM 70 * style fill-only scalefactor 20 # scalefactor 100 layer fp 100 calma 100 100 * layer fm1 101 calma 101 101 * layer fm2 102 calma 102 102 * layer fm3 103 calma 103 103 * layer fm4 104 calma 104 104 * layer fa 109 or fb calma 109 109 * layer fn 119 calma 119 119 * layer fapm 110 calma 110 110 * end mzrouter style irouter # layer hCost vCost jogCost hintCost layer metal4 2 1 2 1 layer metal3 1 2 2 1 layer metal2 2 1 2 1 layer metal1 2 3 2 1 layer poly 10 10 11 1 contact m4contact metal4 metal3 4 contact m3contact metal3 metal2 5 contact m2contact metal2 metal1 6 contact pcontact metal1 poly 7 notactive poly pcontact style garouter layer m2 32 64 256 1 layer m1 64 32 256 1 contact m2contact metal1 metal2 1024 end drc width nwell 12 \ "N-well width < 12 (Mosis #1.1)" width rnw 12 \ "rnwell (for resistor L/W extraction) width < 12 (Mosis #1.1)" width nwr 12 \ "nwr (for Fig1b resistor L/W extraction) width < 12 (Mosis #Fig1bX)" width pwell 12 \ "P-well width < 12 (Mosis #1.1)" width diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a 3 \ "Diffusion width < 3 (Mosis #2.1)" edge4way nsd,nwsd,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a pdiff,apres,rpd,pdc/a,pdm12c/a 3 ~(nsd,nwsd,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a)/active pdiff,apres,rpd,pdc/a,pdm12c/a 3 \ "P-Diffusion width in N-Ohmic < 3 (Mosis #2.1)" active edge4way psd,psc/a,psm12c/a ndiff,anres,rnd,ndc/a,ndm12c/a 3 ~(psd,psc/a,psm12c/a)/active ndiff,anres,rnd,ndc/a,ndm12c/a 3 \ "N-Diffusion width in P-Ohmic < 3 (Mosis #2.1)" active edge4way pdiff,apres,rpd,pdc/a,pdm12c/a nsd,nwsd,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a 3 ~(pdiff,apres,rpd,pdc/a,pdm12c/a)/active nsd,nwsd,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a 3 \ "N-Ohmic width in P-Diffusion < 3 (Mosis #2.1)" active edge4way ndiff,anres,rnd,ndc/a,ndm12c/a psd,psc/a,psm12c/a 3 ~(ndiff,anres,rnd,ndc/a,ndm12c/a)/active psd,psc/a,psm12c/a 3 \ "P-Ohmic width in N-Diffusion < 3 (Mosis #2.1)" active width poly,fp,pres,rp,pc/a,pm12c/a,nfet,pfet,fet 2 \ "Poly width < 2 (Mosis #3.1)" width nselect 3 \ "N-Select width < 3 (Mosis #4.4)" width pselect 3 \ "P-Select width < 3 (Mosis #4.4)" width ndiff,anres,rnd,ndc/a,ndm12c/a,nsd,nsc/a,nsm12c/a 3 \ "N-Diffusion,N-Ohmic width < 3 (Mosis #4.4)" width pdiff,apres,rpd,pdc/a,pdm12c/a,psd,psc/a,psm12c/a 3 \ "P-Diffusion,P-Ohmic width < 3 (Mosis #4.4)" width pc/m1 4 \ "Poly contact width < 4 (Mosis #5.1)" width pm12c/m1 4 \ "Poly contact width < 4 (Mosis #5.1)" width gc 2 \ "GC contact width < 2 (Mosis #6.1)" width ndc/m1 4 \ "Diffusion contact width < 4 (Mosis #6.1)" width ndm12c/m1 4 \ "Diffusion contact width < 4 (Mosis #6.1)" width nsc/m1 4 \ "Diffusion contact width < 4 (Mosis #6.1)" width nwsc/m1 4 \ "Diffusion contact width < 4 (Mosis #6.1)" width nsm12c/m1 4 \ "Diffusion contact width < 4 (Mosis #6.1)" width nwsm12c/m1 4 \ "Diffusion contact width < 4 (Mosis #6.1)" width nwsc 6 \ "nwr (for Fig1b resistor) active Contact width < 6 (Mosis #Fig1b)" width pdc/m1 4 \ "Diffusion contact width < 4 (Mosis #6.1)" width pdm12c/m1 4 \ "Diffusion contact width < 4 (Mosis #6.1)" width psc/m1 4 \ "Diffusion contact width < 4 (Mosis #6.1)" width psm12c/m1 4 \ "Diffusion contact width < 4 (Mosis #6.1)" width m1,fm1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,m123c/m1 3 \ "Metal1 width < 3 (Mosis #7.1)" width gv1 2 \ "GV1 via width < 2 (Mosis #8.1)" width m2c/m1 4 \ "Metal2 contact width < 4 (Mosis #8.1)" width pdm12c/m1 4 \ "Metal2 contact width < 4 (Mosis #8.1)" width ndm12c/m1 4 \ "Metal2 contact width < 4 (Mosis #8.1)" width psm12c/m1 4 \ "Metal2 contact width < 4 (Mosis #8.1)" width nsm12c/m1 4 \ "Metal2 contact width < 4 (Mosis #8.1)" width pm12c/m1 4 \ "Metal2 contact width < 4 (Mosis #8.1)" width m123c/m1 4 \ "Metal2 contact width < 4 (Mosis #8.1)" width nwsm12c/m1 4 \ "Metal2 contact width < 4 (Mosis #8.1)" width m2,fm2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m234c/m2 3 \ "Metal2 width < 3 (Mosis #9.1)" width gv2 2 \ "GV2 via width < 2 (Mosis #14.1)" width m3c/m2 4 \ "Metal3 contact width < 4 (Mosis #14.1)" width m123c/m2 4 \ "Metal3 contact width < 4 (Mosis #14.1)" width m234c/m2 4 \ "Metal3 contact width < 4 (Mosis #14.1)" width m3,fm3,rm3,m3c/m3,m123c/m3,m234c/m3,m4c/m3 3 \ "Metal3 width < 3 (Mosis #15.1)" width sb,pres,anres,apres 4 \ "Silicide-Block width < 4 (Mosis #20.1)" width pres 5 \ "Silicide-Block polyR width < 5 (Mosis #20.6)" width anres,apres 6 \ "Silicide-Block activeR width < 6 (Mosis #20.16)" width gv3 2 \ "GV3 via width < 2 (Mosis #21.3)" width m4c/m3 4 \ "Metal4 contact width < 4 (Mosis #21.3)" width m234c/m3 4 \ "Metal4 contact width < 4 (Mosis #21.3)" width m4,fm4,rm4,m4c/m4,m234c/m4,pad 3 \ "Metal4 width < 3 (Mosis #22.1)" width nfi,pfi 4 \ "N/P_field-implant width < 4 (Mosis #29.1)" spacing nwell nwell 6 touching_ok \ "N-well(at-same-potential) spacing < 6 (Mosis #1.3)" spacing pwell pwell 6 touching_ok \ "P-well(at-same-potential) spacing < 6 (Mosis #1.3)" spacing rnw nwell 18 touching_illegal \ "rnw (for resistor L/W extraction) spacing to N-well < 18 (Mosis #2.3)" spacing nwr nwell 18 touching_illegal \ "nwr (for Fig1b resistor L/W extraction) spacing to N-well < 18 (Mosis #2.3)" edge4way ~(pwell)/well pwell 1 ~(rnw)/active 0 0 \ "P-well cannot touch rnw (for resistor L/W extraction) (Mosis #1.4)" active edge4way ~(pwell)/well pwell 1 ~(nwr)/active 0 0 \ "P-well cannot touch nwr (for Fig1b resistor L/W extraction) (Mosis #1.4)" active spacing diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a 3 touching_ok \ "Diffusion spacing < 3 (Mosis #2.2)" spacing nwell ndiff,anres,rnd,nfet,ndc/a,ndm12c/a 6 touching_illegal \ "N-well spacing to N-Diffusion < 6 (Mosis #2.3)" spacing pwell pdiff,apres,rpd,pfet,pdc/a,pdm12c/a 6 touching_illegal \ "P-well spacing to P-Diffusion < 6 (Mosis #2.3)" spacing ndiff,anres,rnd,nfet,ndc/a,ndm12c/a pdiff,apres,rpd,pfet,pdc/a,pdm12c/a 12 touching_illegal \ "N-Diffusion spacing to P-Diffusion < 12 (Mosis #2.3+2.3)" edge4way ~(nwell)/well nwell 6 ~(pdiff,apres,rpd,pfet,pdc/a,pdm12c/a)/active nwell 6 \ "N-well overlap of P-Diffusion < 6 (Mosis #2.4)" active edge4way ~(pwell)/well pwell 6 ~(ndiff,anres,rnd,nfet,ndc/a,ndm12c/a)/active pwell 6 \ "P-well overlap of N-Diffusion < 6 (Mosis #2.4)" active edge4way ~(nwell)/well nwell 3 ~(nsd,nwsd,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a)/active nwell 3 \ "N-well overlap of N-Ohmic < 3 (Mosis #2.4)" active edge4way ~(pwell)/well pwell 3 ~(psd,psc/a,psm12c/a)/active pwell 3 \ "P-well overlap of P-Ohmic < 3 (Mosis #2.4)" active spacing ndiff,anres,rnd,ndc/a,ndm12c/a nsd,nwsd,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a 9 touching_illegal \ "N-Diffusion spacing to N-Ohmic < 9 (Mosis #2.3+2.4)" spacing pdiff,apres,rpd,pdc/a,pdm12c/a psd,psc/a,psm12c/a 9 touching_illegal \ "P-Diffusion spacing to P-Ohmic < 9 (Mosis #2.3+2.4)" spacing nwell psd,psc/a,psm12c/a 3 touching_illegal \ "N-well spacing to P-Ohmic < 3 (Mosis #2.4)" spacing pwell nsd,nwsd,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a 3 touching_illegal \ "P-well spacing to N-Ohmic < 3 (Mosis #2.4)" spacing psd,psc/a,psm12c/a rnw,prnw 3 touching_illegal \ "P-Ohmic spacing to rnw,prnw < 3 (Mosis #2.4)" spacing psd,psc/a,psm12c/a nwr,pnwr 3 touching_illegal \ "P-Ohmic spacing to nwr,pnwr (for Fig1b Resistor) < 3 (Mosis #2.4)" spacing nsd,nwsd,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a psd,psc/a,psm12c/a 6 touching_illegal \ "N-Ohmic spacing to P-Ohmic < 6 (Mosis #2.4+2.4)" spacing ndiff,anres,rnd,nfet,ndc/a,ndm12c/a,nfet psd,psc/a,psm12c/a 4 touching_ok \ "N-Diffusion spacing to P-Ohmic < 4 (Mosis #2.5)" spacing pdiff,apres,rpd,pfet,pdc/a,pdm12c/a,pfet nsd,nwsd,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a 4 touching_ok \ "P-Diffusion spacing to N-Ohmic < 4 (Mosis #2.5)" spacing poly,pres,rp,pc/a,pm12c/a,nfet,pfet,fet poly,pres,rp,pc/a,pm12c/a,nfet,pfet,fet 3 touching_ok \ "Poly spacing < 3 (Mosis #3.2)" spacing poly,pres,rp,pc/a,pm12c/a,nfet,pfet,fet fp,fapm 3 touching_illegal \ "Poly spacing to fill layer (fp) < 3 (Mosis #3.2)" spacing fp fp 4 touching_ok \ "Poly fill layer (fp) spacing < 4 (Mosis #0)" edge4way nfet,pfet,fet space/active,poly,fp,pres,rp,pc/a,pm12c/a 2 poly,fp,pres,rp,pc/a,pm12c/a 0 0 \ "Poly overhang of Transistor < 2 (Mosis #3.3)" active edge4way nfet,pfet,fet space/active,ndiff,anres,rnd,ndc/a,ndm12c/a,pdiff,apres,rpd,pdc/a,pdm12c/a 3 ndiff,anres,rnd,ndc/a,ndm12c/a,pdiff,apres,rpd,pdc/a,pdm12c/a,nfet,pfet,fet 0 0 \ "N-Diffusion,P-Diffusion overhang of Transistor < 3 (Mosis #3.4)" active edge4way poly,fp,rp,pc/a,pm12c/a ~(poly,fp,pres,rp,pc/a,pm12c/a,nfet,pfet,fet,prp)/active 1 space space 1 \ "Poly spacing to Diffusion < 1 (Mosis #3.5)" edge4way nfet ~(nfet)/active 2 ~(pselect)/select ~(nfet)/active 2 \ "N-Transistor space to P-Select < 2 (Mosis #4.1)" select edge4way pfet ~(pfet)/active 2 ~(nselect)/select ~(pfet)/active 2 \ "P-Transistor space to N-Select < 2 (Mosis #4.1)" select edge4way nfet ~(nfet)/active 3 ~(psd,psc/a,psm12c/a)/active ~(nfet)/active 2 \ "N-Transistor space to P-Ohmic < 3 (Mosis #4.1)" active edge4way pfet ~(pfet)/active 3 ~(nsd,nwsd,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a)/active ~(pfet)/active 2 \ "P-Transistor space to N-Ohmic < 3 (Mosis #4.1)" active #PEZ edge4way psd,psc/a,psm12c/a space ~(nfet)/active space \ #PEZ "P-Ohmic space to N-Transistor < (Mosis #4.1)" active #PEZ edge4way nsd,nwsd,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a space ~(pfet)/active space \ #PEZ "N-Ohmic space to P-Transistor < (Mosis #4.1)" active edge4way ~(nselect,pselect)/select nselect,pselect 2 ~(diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a)/active nselect,pselect 2 \ "N-Select,P-Select overlap of Diffusion < 2 (Mosis #4.2_)" active edge4way space nselect,pselect 2 ~(ndiff,anres,rnd,nfet,ndc/a,ndm12c/a)/active nselect 2 \ "N-Select space to N-Diffusion < 2 (Mosis #4.2a)" active edge4way nselect,pselect space 2 ~(ndiff,anres,rnd,nfet,ndc/a,ndm12c/a)/active nselect 2 \ "N-Select space to N-Diffusion < 2 (Mosis #4.2b)" active edge4way nselect,pselect space 2 ~(ndiff,anres,rnd,nfet,ndc/a,ndm12c/a)/active space,nselect,pselect 2 \ "N-Select space to N-Diffusion < 2 (Mosis #4.2c)" active edge4way space nselect,pselect 2 ~(pdiff,apres,rpd,pfet,pdc/a,pdm12c/a)/active pselect 2 \ "P-Select space to P-Diffusion < 2 (Mosis #4.2aa)" active edge4way nselect,pselect space 2 ~(pdiff,apres,rpd,pfet,pdc/a,pdm12c/a)/active pselect 2 \ "P-Select space to P-Diffusion < 2 (Mosis #4.2bb)" active edge4way nselect,pselect space 2 ~(pdiff,apres,rpd,pfet,pdc/a,pdm12c/a)/active space,nselect,pselect 2 \ "P-Select space to P-Diffusion < 2 (Mosis #4.2cc)" active area nsd,nwsd,psd,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,psc/a,psm12c/a 16 3 \ "Ohmic-Diffusion area < 16 (Mosis #+++)" edge4way diff space 2 nselect space 2 \ "N-Select must overlap Diffusion by 2 (Mosis #4.2)" select edge4way diff space 2 pselect space 2 \ "P-Select must overlap Diffusion by 2 (Mosis #4.2)" select edge4way ndiff,anres,rnd,nfet,ndc/a,ndm12c/a space 2 ~(pselect)/select space 2 \ "P-Select space to N-Diffusion < 2 (Mosis #4.2e)" select edge4way pdiff,apres,rpd,pfet,pdc/a,pdm12c/a space 2 ~(nselect)/select space 2 \ "N-Select space to P-Diffusion < 2 (Mosis #4.2e)" select edge4way ~(pdiff,apres,rpd,pfet,pdc/a,pdm12c/a,psd,psc/a,psm12c/a)/active pdiff,apres,rpd,pfet,pdc/a,pdm12c/a,psd,psc/a,psm12c/a 1 ~(nselect)/select 0 0 \ "N-Select cannot touch P-Diffusion,P-Ohmic (Mosis #4.2f)" select edge4way ~(ndiff,anres,rnd,nfet,ndc/a,ndm12c/a,nsd,nwsd,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a)/active ndiff,anres,rnd,nfet,ndc/a,ndm12c/a,nsd,nwsd,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a 1 ~(pselect)/select 0 0 \ "P-Select cannot touch N-Diffusion,N-Ohmic (Mosis #4.2f)" select spacing nselect nselect 3 touching_ok \ "N-Select spacing < 3 (Mosis #4.4)" spacing pselect pselect 3 touching_ok \ "P-Select spacing < 3 (Mosis #4.4)" edge4way ndiff,anres,rnd,ndc/a,ndm12c/a psd,psc/a,psm12c/a 2 ~(ndiff,anres,rnd,ndc/a,ndm12c/a)/active 0 0 \ "P-Ohmic(that touches N-Diffusion) width < 2 (Mosis #4.4)" edge4way pdiff,apres,rpd,pdc/a,pdm12c/a nsd,nwsd,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a 2 ~(pdiff,apres,rpd,pdc/a,pdm12c/a)/active 0 0 \ "N-Ohmic(that touches P-Diffusion) width < 2 (Mosis #4.4)" edge4way gc ~(gc)/contact 1 poly,fp,pres,rp,pc/a,pm12c/a,diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a ~(gc)/contact 1 \ "Poly,Diffusion overlap of GC contact < 1 (Mosis #5.2)" active edge4way ~(nwsd)/active nwsd 2 ~(gc)/contact nwsd 2 \ "nwr (for Fig1b resistor) active overlap of GC contact < 2 (Mosis #Fig1b)" contact spacing nwr gc 5 touching_illegal \ "nwr (for Fig1b resistor) spacing to GC contact < 5 (Mosis #Fig1b)" spacing nwr ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a 3 touching_illegal \ "nwr (for Fig1b resistor) spacing to Diffusion contact < 3 (Mosis #Fig1b)" edge4way gc space 1 poly,fp,pres,rp,pc/a,pm12c/a,diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a space 1 \ "one of: Poly,Diffusion must overlap GC contact by 1 (Mosis #5.2a,6.2a)" active edge4way ~(poly,fp,pres,rp,pc/a,pm12c/a,diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a)/active poly,fp,pres,rp,pc/a,pm12c/a,diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a 1 ~(gc)/contact 0 0 \ "Edge to one of: Poly,Diffusion cannot touch GC contact (Mosis #5.2a,6.2a)" contact spacing gc gc 3 touching_ok \ "Generic contact spacing < 3 (Mosis #5.3)" edge4way ~(gc)/contact gc 1 ~(ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1)/metal1 0 0 \ "GC contact cannot touch Metal1 contacts (Mosis #0)" metal1 spacing gv1 m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2 2 touching_illegal \ "GV1 via spacing to Metal2 contacts < 2 (Mosis #14.2)" #PSC spacing poly,fp,pres,rp,pc/a,pm12c/a pc/a,pm12c/a 4 touching_ok \ #PSC "Poly spacing to Poly contact < 4 (Mosis #5.5.b)" edge4way gc ~(gc)/contact 1 diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,poly,fp,pres,rp,pc/a,pm12c/a ~(gc)/contact 1 \ "Diffusion,Poly overlap of GC contact < 1 (Mosis #6.2)" active spacing gc pc/a,pm12c/a,ndc/a,ndm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a 2 touching_illegal \ "Generic contact spacing to Poly contact,Diffusion contact < 2 (Mosis #5.3)" spacing nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1 pdc/m1,pdm12c/m1 1 touching_illegal \ "nsc spacing to pdc < 1 (Mosis #6.3)" spacing psc/m1,psm12c/m1 ndc/m1,ndm12c/m1 1 touching_illegal \ "psc spacing to ndc < 1 (Mosis #6.3)" spacing pdm12c/m1 pdc/m1,m2c/m1,nsm12c/m1 1 touching_illegal \ "pdm12c spacing to pdc or m2c or nsm12c < 1 (Mosis #6.3)" spacing psm12c/m1 psc/m1,m2c/m1 1 touching_illegal \ "psm12c spacing to psc or m2c < 1 (Mosis #6.3)" spacing ndm12c/m1 ndc/m1,m2c/m1,nsm12c/m1 1 touching_illegal \ "ndm12c spacing to ndc or m2c or nsm12c < 1 (Mosis #6.3)" spacing nsm12c/m1 nsc/m1,m2c/m1 1 touching_illegal \ "nsm12c spacing to nsc or m2c < 1 (Mosis #6.3)" spacing pm12c/m1 pc/m1,m2c/m1 1 touching_illegal \ "pm12c spacing to pc or m2c < 1 (Mosis #6.3)" spacing m123c/m2 pdm12c/m2,psm12c/m2,ndm12c/m2,nsm12c/m2,pm12c/m2,m2c/m2,m3c/m2 1 touching_illegal \ "m123c spacing to *m12c or m2c or m3c < 1 (Mosis #6.3)" spacing m234c/m3 m3c/m3,m4c/m3,m123c/m3 1 touching_illegal \ "m234c spacing to m3c or m4c or m123c < 1 (Mosis #6.3)" spacing nfet,pfet ndc/a,ndm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a 1 touching_illegal \ "N-Transistor,P-Transistor spacing to Diffusion contact < 1 (Mosis #6.4)" spacing nfet,pfet gc 2 touching_illegal \ "N-Transistor,P-Transistor spacing to Generic contact < 2 (Mosis #6.4)" spacing diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a pc/a,pm12c/a 1 touching_illegal \ "Diffusion spacing to Poly contact < 1 (Mosis #6.5.b)" spacing diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,nfet,pfet ndc/a,ndm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a 4 touching_ok \ "Diffusion spacing to Diffusion contact < 4 (Mosis #6.5.b)" spacing pc/a,pm12c/a ndc/a,ndm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a 2 touching_illegal \ "pc/a,pm12c/a spacing to ndc/a,ndm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a < 2 (Mosis #6.7)" spacing m1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,m123c/m1 m1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,m123c/m1 3 touching_ok \ "Metal1 spacing < 3 (Mosis #7.2)" spacing m1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,m123c/m1 fm1,fapm 3 touching_illegal \ "Metal1 spacing to fill layer (fm1) < 3 (Mosis #7.2)" spacing fm1 fm1 4 touching_ok \ "Metal1 fill layer (fm1) spacing < 4 (Mosis #0)" edge4way gc space 1 m1,fm1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,m123c/m1 space 1 \ "Metal1 must overlap GC contact by 1 (Mosis #7.3,7.4)" metal1 edge4way ~(m1,fm1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,m123c/m1)/metal1 m1,fm1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,m123c/m1 1 ~(gc)/contact 0 0 \ "Metal1(edge) cannot touch GC contact (Mosis #7.3+7.4)" contact spacing gv1 gv1 3 touching_ok \ "GV1 via spacing < 3 (Mosis #8.2)" edge4way gv1 ~(gv1)/via1 1 m1,fm1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,m123c/m1 ~(gv1)/via1 1 \ "Metal1 overlap of GV1 via < 1 (Mosis #8.3)" metal1 edge4way gv1 space 1 m1,fm1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,m123c/m1 space 1 \ "Metal1 must overlap GV1 via by 1 (Mosis #8.3)" metal1 edge4way ~(m1,fm1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,m123c/m1)/metal1 m1,fm1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,m123c/m1 1 ~(gv1)/via1 0 0 \ "Metal1(edge) cannot touch GV1 via (Mosis #8.3)" via1 spacing m2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m234c/m2 m2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m234c/m2 3 touching_ok \ "Metal2 spacing < 3 (Mosis #9.2)" spacing m2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m234c/m2 fm2,fapm 3 touching_illegal \ "Metal2 spacing to fill layer (fm2) < 3 (Mosis #9.2)" spacing fm2 fm2 4 touching_ok \ "Metal2 fill layer (fm2) spacing < 4 (Mosis #0)" edge4way gv1 space 1 m2,fm2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m234c/m2 space 1 \ "Metal2 must overlap GV1 via by 1 (Mosis #9.3)" metal2 edge4way ~(m2,fm2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m234c/m2)/metal2 m2,fm2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m234c/m2 1 ~(gv1)/via1 0 0 \ "Metal2(edge) cannot touch GV1 via (Mosis #9.3)" via1 width glass 10 \ "COG width < 10 (Mosis #10.2)" edge4way ~(pad)/metal4 pad 30 ~(glass)/oxide pad 30 \ "pad overlap of COG < 30 (Mosis #10.3)" oxide spacing gv2 gv2 3 touching_ok \ "GV2 via spacing < 3 (Mosis #14.2)" spacing gv2 m3c/m2,m123c/m2,m234c/m2 2 touching_illegal \ "GV2 via spacing to Metal3 contact < 2 (Mosis #14.2)" edge4way gv2 space 1 m2,fm2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m234c/m2 space 1 \ "Metal2 must overlap GV2 via by 1 (Mosis #14.3)" metal2 edge4way ~(m2,fm2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m234c/m2)/metal2 m2,fm2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m234c/m2 1 ~(gv2)/via2 0 0 \ "Metal2(edge) cannot touch GV2 via (Mosis #14.3)" via2 spacing m3,rm3,m3c/m3,m123c/m3,m234c/m3,m4c/m3 m3,rm3,m3c/m3,m123c/m3,m234c/m3,m4c/m3 3 touching_ok \ "Metal3 spacing < 3 (Mosis #15.2)" spacing m3,rm3,m3c/m3,m123c/m3,m234c/m3,m4c/m3 fm3,fapm 3 touching_illegal \ "Metal3 spacing to fill layer (fm3) < 3 (Mosis #15.2)" spacing fm3 fm3 4 touching_ok \ "Metal3 fill layer (fm3) spacing < 4 (Mosis #0)" edge4way gv2 space 1 m3,fm3,rm3,m3c/m3,m123c/m3,m234c/m3,m4c/m3 space 1 \ "Metal3 must overlap GV2 via by 1 (Mosis #15.3)" metal3 edge4way ~(m3,fm3,rm3,m3c/m3,m123c/m3,m234c/m3,m4c/m3)/metal3 m3,fm3,rm3,m3c/m3,m123c/m3,m234c/m3,m4c/m3 1 ~(gv2)/via2 0 0 \ "Metal3(edge) cannot touch GV2 via (Mosis #15.3)" via2 spacing sb,pres,anres,apres sb,pres,anres,apres 4 touching_ok \ "Silicide-Block spacing < 4 (Mosis #20.2)" spacing sb,pres,anres,apres,pres,anres,apres pc/a,pm12c/a,ndc/a,ndm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a 1 touching_illegal \ "Silicide-Block spacing to Diffusion contact,Poly contact < 1 (Mosis #20.3)" spacing sb,pres,anres,apres,pres,anres,apres gc 2 touching_illegal \ "Silicide-Block spacing to GC contact < 2 (Mosis #20.3)" edge4way sb,pres,anres,apres space 2 ~(diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a)/active 0 2 \ "Silicide-Block space to Diffusion < 2 (Mosis #20.4)" active spacing sb,pres,anres,apres,pres poly,fp,pres,rp,pc/a,pm12c/a 2 touching_ok \ "Silicide-Block spacing to other Poly < 2 (Mosis #20.5)" edge4way sb,pres,anres,apres space 2 ~(poly,fp,pres,rp,pc/a,pm12c/a)/contact sb,pres,anres,apres 2 \ "Silicide-Block space to Poly < 2 (Mosis #20.5x)" contact spacing sb,pres,anres,apres,pres nfet,pfet,fet 2 touching_ok \ "Silicide-Block spacing to other Transistor < 2 (Mosis #20.5)" edge4way sb,pres,anres,apres space 2 ~(nfet,pfet,fet)/contact sb,pres,anres,apres 2 \ "Silicide-Block space to Transistor < 2 (Mosis #20.5x)" contact spacing pres pres 7 touching_ok \ "Silicide-Block polyR spacing < 7 (Mosis #20.13)" edge4way pres,anres,apres space/active,sb 2 sb sb 2 \ "Silicide-Block overlap of Silicide-Block polyR/activeR < 2 (Mosis #20.15)" edge4way sb,pres,anres,apres diff,ndiff,rnd,nfet,nsd,nwsd,pdiff,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a 3 diff,ndiff,rnd,nfet,nsd,nwsd,pdiff,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a 0 0 \ "Diffusion overhang of Silicide-Block < 3 (Mosis #20.17) spacing gv3 gv3 3 touching_ok \ "GV3 via spacing < 3 (Mosis #21.2)" spacing gv3 m4c/m3,m234c/m3 2 touching_illegal \ "GV3 via spacing to Metal4 contact < 2 (Mosis #21.2)" edge4way gv3 space 1 m3,fm3,rm3,m3c/m3,m123c/m3,m234c/m3,m4c/m3 space 1 \ "Metal3 must overlap GV3 via by 1 (Mosis #21.3)" metal3 edge4way ~(m3,fm3,rm3,m3c/m3,m123c/m3,m234c/m3,m4c/m3)/metal3 m3,fm3,rm3,m3c/m3,m123c/m3,m234c/m3,m4c/m3 1 ~(gv3)/via3 0 0 \ "Metal3(edge) cannot touch GV3 via (Mosis #21.3)" via3 spacing m4,rm4,m4c/m4,m234c/m4,pad m4,rm4,m4c/m4,m234c/m4,pad 3 touching_ok \ "Metal4 spacing < 3 (Mosis #22.2)" spacing m4,rm4,m4c/m4,m234c/m4,pad fm4,fapm 3 touching_illegal \ "Metal4 spacing to fill layer (fm4) < 3 (Mosis #22.2)" spacing fm4 fm4 4 touching_ok \ "Metal4 fill layer (fm4) spacing < 4 (Mosis #0)" edge4way gv3 space 1 m4,fm4,rm4,m4c/m4,m234c/m4,pad space 1 \ "Metal4 must overlap GV3 via by 1 (Mosis #22.3)" metal4 edge4way ~(m4,fm4,rm4,m4c/m4,m234c/m4,pad)/metal4 m4,fm4,rm4,m4c/m4,m234c/m4,pad 1 ~(gv3)/via3 0 0 \ "Metal4(edge) cannot touch GV3 via (Mosis #22.3)" via3 spacing nfi nfi 4 touching_ok \ "N_field-implant spacing < 4 (Mosis #35.2)" spacing pfi pfi 4 touching_ok \ "P_field-implant spacing < 4 (Mosis #35.2)" spacing nfi pfi 4 touching_illegal \ "N_field-implant spacing to P_field-implant < 4 (Mosis #35.2)" spacing nwell,pdiff,apres,rpd,pfet,pdc/a,pdm12c/a pfi 4 touching_illegal \ "N-well,P-Diffusion spacing to P_field-implant < 4 (Mosis #2.1)" spacing pwell,ndiff,anres,rnd,nfet,ndc/a,ndm12c/a nfi 4 touching_illegal \ "P-well,N-Diffusion spacing to N_field-implant < 4 (Mosis #2.1)" edge4way ~(nwell)/well nwell 4 ~(nfi)/implant nwell 4 \ "N-well overlap of N_field-implant < 4 (Mosis #21.2)" implant edge4way ~(pwell)/well pwell 4 ~(pfi)/implant pwell 4 \ "P-well overlap of P_field-implant < 4 (Mosis #21.2)" implant spacing fa fapm 4 touching_illegal \ "fill layer fa spacing to fill layer fapm < 4 (Mosis #0)" width fa 10 \ "filla width < 10 (Mosis #0)" width fapm 10 \ "fillapm width < 10 (Mosis #0)" width fp 10 \ "fillp width < 10 (Mosis #0)" width fm1 10 \ "fillm1 width < 10 (Mosis #0)" width fm2 10 \ "fillm2 width < 10 (Mosis #0)" width fm3 10 \ "fillm3 width < 10 (Mosis #0)" width fm4 10 \ "fillm4 width < 10 (Mosis #0)" edge4way fa ~(fa)/fill 1 ~(fa)/fill (~(fa),fa)/fill 1 \ "Contact not rectangular (Magic rule)" edge4way fb ~(fb)/fill 1 ~(fb)/fill (~(fb),fb)/fill 1 \ "Contact not rectangular (Magic rule)" edge4way fapm ~(fapm)/active 1 ~(fapm)/active (~(fapm),fapm)/active 1 \ "Contact not rectangular (Magic rule)" edge4way fp ~(fp)/active 1 ~(fp)/active (~(fp),fp)/active 1 \ "Contact not rectangular (Magic rule)" edge4way fm1 ~(fm1)/metal1 1 ~(fm1)/metal1 (~(fm1),fm1)/metal1 1 \ "Contact not rectangular (Magic rule)" edge4way fm2 ~(fm2)/metal2 1 ~(fm2)/metal2 (~(fm2),fm2)/metal2 1 \ "Contact not rectangular (Magic rule)" edge4way fm3 ~(fm3)/metal3 1 ~(fm3)/metal3 (~(fm3),fm3)/metal3 1 \ "Contact not rectangular (Magic rule)" edge4way fm4 ~(fm4)/metal4 1 ~(fm4)/metal4 (~(fm4),fm4)/metal4 1 \ "Contact not rectangular (Magic rule)" edge4way rp space/active 1 prp 0 0 \ "prp overhang of rpoly (for resistor L/W extraction) < 1 (Mosis #0)" active edge4way rnw space/active 1 prnw 0 0 \ "prnw overhang of rnwell (for resistor L/W extraction) < 1 (Mosis #0)" active edge4way nwr space/active 1 pnwr 0 0 \ "pnwr overhang of nwr (for Fig1b resistor L/W extraction) < 1 (Mosis #0)" active edge4way rpd space/active 1 prpd 0 0 \ "prpd overhang of rpdiff (for resistor L/W extraction) < 1 (Mosis #0)" active edge4way rnd space/active 1 prnd 0 0 \ "prnd overhang of rndiff (for resistor L/W extraction) < 1 (Mosis #0)" active edge4way rm1 space/metal1 1 prm1 0 0 \ "prm1 overhang of rmetal1 (for resistor L/W extraction) < 1 (Mosis #0)" metal1 edge4way rm2 space/metal2 1 prm2 0 0 \ "prm2 overhang of rmetal2 (for resistor L/W extraction) < 1 (Mosis #0)" metal2 edge4way rm3 space/metal3 1 prm3 0 0 \ "prm3 overhang of rmetal3 (for resistor L/W extraction) < 1 (Mosis #0)" metal3 edge4way rm4 space/metal4 1 prm4 0 0 \ "prm4 overhang of rmetal4 (for resistor L/W extraction) < 1 (Mosis #0)" metal4 edge4way ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a ~(ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a)/active 1 ~(ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a)/active (~(ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a),ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a)/active 1 \ "Contact not rectangular (Magic rule)" edge4way pdc/a,pdm12c/a,psc/a,psm12c/a ~(pdc/a,pdm12c/a,psc/a,psm12c/a)/active 1 ~(pdc/a,pdm12c/a,psc/a,psm12c/a)/active (~(pdc/a,pdm12c/a,psc/a,psm12c/a),pdc/a,pdm12c/a,psc/a,psm12c/a)/active 1 \ "Contact not rectangular (Magic rule)" edge4way pc/a,pm12c/a ~(pc/a,pm12c/a)/active 1 ~(pc/a,pm12c/a)/active (~(pc/a,pm12c/a),pc/a,pm12c/a)/active 1 \ "Contact not rectangular (Magic rule)" edge4way gc ~(gc)/contact 1 ~(gc)/contact (~(gc),gc)/contact 1 \ "Contact not rectangular (Magic rule)" edge4way gv1 ~(gv1)/via1 1 ~(gv1)/via1 (~(gv1),gv1)/via1 1 \ "Contact not rectangular (Magic rule)" edge4way m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1 ~(m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1)/metal1 1 ~(m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1)/metal1 (~(m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1),m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1)/metal1 1 \ "Contact not rectangular (Magic rule)" edge4way gv2 ~(gv2)/via2 1 ~(gv2)/via2 (~(gv2),gv2)/via2 1 \ "Contact not rectangular (Magic rule)" edge4way m3c/m2,m123c/m2,m234c/m2 ~(m3c/m2,m123c/m2,m234c/m2)/metal2 1 ~(m3c/m2,m123c/m2,m234c/m2)/metal2 (~(m3c/m2,m123c/m2,m234c/m2),m3c/m2,m123c/m2,m234c/m2)/metal2 1 \ "Contact not rectangular (Magic rule)" edge4way gv3 ~(gv3)/via3 1 ~(gv3)/via3 (~(gv3),gv3)/via3 1 \ "Contact not rectangular (Magic rule)" edge4way m4c/m3,m234c/m3 ~(m4c/m3,m234c/m3)/metal3 1 ~(m4c/m3,m234c/m3)/metal3 (~(m4c/m3,m234c/m3),m4c/m3,m234c/m3)/metal3 1 \ "Contact not rectangular (Magic rule)" exact_overlap gc,ndc/a,ndm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,gc,pc/a,pm12c/a,gc edge4way pad ~(pad)/m4 1 ~(pad)/m4 (~(pad),pad)/m4 1 \ "Contact not rectangular (Magic rule)" exact_overlap ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1 exact_overlap m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2 exact_overlap m3c/m3,m123c/m3,m234c/m3 exact_overlap m4c/m4,m234c/m4 exact_overlap gv1 exact_overlap gv2 exact_overlap gv3 edge4way nfet,pfet,fet ~(nfet,pfet,fet)/active 1 ~(nfet,pfet,fet)/active nfet,pfet,fet 1 \ "Transistor cannot bend in this process (Mosis #?.?)" width m1p 4 \ "Metal1 PIN width < 4 (do_pins)" spacing m1p m1p 4 touching_ok \ "Metal1 PIN spacing < 4 (do_pins)" width m2p 4 \ "Metal2 PIN width < 4 (do_pins)" spacing m2p m2p 4 touching_ok \ "Metal2 PIN spacing < 4 (do_pins)" width m3p 4 \ "Metal3 PIN width < 4 (do_pins)" spacing m3p m3p 4 touching_ok \ "Metal3 PIN spacing < 4 (do_pins)" width m4p 4 \ "Metal4 PIN width < 4 (do_pins)" spacing m4p m4p 4 touching_ok \ "Metal4 PIN spacing < 4 (do_pins)" #CC cifstyle lambda=0.20(p) #CC cifwidth CWN 240 \ #CC "generated CIF layer CWN width will be < 12 (';cif see CWN')" #CC cifspacing CWN CWN 120 touching_ok \ #CC "generated CIF layer CWN spacing will be < 6 (';cif see CWN')" #CC cifwidth CWP 240 \ #CC "generated CIF layer CWP width will be < 12 (';cif see CWP')" #CC cifspacing CWP CWP 120 touching_ok \ #CC "generated CIF layer CWP spacing will be < 6 (';cif see CWP')" #CC cifwidth CSN 60 \ #CC "generated CIF layer CSN width will be < 3 (';cif see CSN')" #CC cifspacing CSN CSN 60 touching_ok \ #CC "generated CIF layer CSN spacing will be < 3 (';cif see CSN')" #CC cifwidth CSP 60 \ #CC "generated CIF layer CSP width will be < 3 (';cif see CSP')" #CC cifspacing CSP CSP 60 touching_ok \ #CC "generated CIF layer CSP spacing will be < 3 (';cif see CSP')" stepsize 400 end #--------------------------------------------------- # LEF format definitions #--------------------------------------------------- lef ignore PC ignore CA routing m1 M1 m1 met1 routing m2 M2 m2 met2 routing m3 M3 m3 met3 routing m4 M4 m4 met4 contact m2c via1 V1 v1 contact m3c via2 V2 v2 contact m4c via3 V3 v3 end #--------------------------------------------------- extract style TSMC0.35um(tsmc35)from:t11c cscale 1 lambda 20 step 100 sidehalo 8 planeorder well 0 planeorder implant 1 planeorder select 2 planeorder active 3 planeorder metal1 4 planeorder metal2 5 planeorder metal3 6 planeorder metal4 7 planeorder oxide 8 planeorder xp 9 planeorder comment 10 planeorder contact 11 planeorder via1 12 planeorder via2 13 planeorder via3 14 planeorder fill 15 resist (ndiff,anres,rnd,ndc,ndm12c,nsd,nwsd,nsc,nwsc,nsm12c,nwsm12c)/active 3700 resist (pdiff,apres,rpd,pdc,pdm12c,psd,psc,psm12c)/active 2800 resist (nwell)/well 1018000 resist (rnw,nwr)/active 1018000 resist (pwell)/well 1 resist (poly,fp,rp,pc,pm12c,pc,pm12c,nfet,pfet,fet)/active 6000 resist (pres)/active 6000 resist (m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c)/metal1 80 resist (m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c,m3c,m123c,m234c)/metal2 70 resist (m3,fm3,rm3,m3c,m123c,m234c,m4c,m4c,m234c)/metal3 80 resist (m4,fm4,rm4,m4c,m234c,pad)/metal4 40 contact ndc 4 4100 contact pdc 4 3400 contact pc 4 4600 contact m2c 4 1300 contact m3c 4 1170 contact m4c 4 1110 #nwell,cwell,pwell areacap (nwell)/well 2.360 #rnw areacap (rnw,nwr)/active 2.360 #ndiff # MODEL HANDLES THIS: areacap (ndiff,ndc,ndm12c)/active 43.160 # MODEL HANDLES THIS: overlap (ndiff,ndc,ndm12c)/active ~space/w 43.160 # MODEL HANDLES THIS: perimc (ndiff,ndc,ndm12c)/active ~(ndiff,ndc,ndm12c,nfet,pfet,fet)/active 64.200 # MODEL HANDLES THIS: sideoverlap (ndiff,ndc,ndm12c)/active ~(ndiff,ndc,ndm12c,nfet,pfet,fet)/active ~space/w 64.200 areacap (rnd,anres)/active 43.160 overlap (rnd,anres)/active ~space/w 43.160 perimc (rnd,anres)/active ~(rnd,anres)/active 64.200 sideoverlap (rnd,anres)/active ~(rnd,anres)/active ~space/w 64.200 #pdiff # MODEL HANDLES THIS: areacap (pdiff,pdc,pdm12c)/active 55.880 # MODEL HANDLES THIS: overlap (pdiff,pdc,pdm12c)/active ~space/w 55.880 # MODEL HANDLES THIS: perimc (pdiff,pdc,pdm12c)/active ~(pdiff,pdc,pdm12c,nfet,pfet,fet)/active 81.800 # MODEL HANDLES THIS: sideoverlap (pdiff,pdc,pdm12c)/active ~(pdiff,pdc,pdm12c,nfet,pfet,fet)/active ~space/w 81.800 areacap (rpd,apres)/active 55.880 overlap (rpd,apres)/active ~space/w 55.880 perimc (rpd,apres)/active ~(rpd,apres)/active 81.800 sideoverlap (rpd,apres)/active ~(rpd,apres)/active ~space/w 81.800 #rnw #poly # MODEL HANDLES THIS: overlap (nfet)/active (ndiff,anres,rnd,ndc,ndm12c)/active 181.800 # MODEL HANDLES THIS: sideoverlap (nfet)/active ~(nfet)/active (ndiff,anres,rnd,ndc,ndm12c)/active 55.400 # MODEL HANDLES THIS: overlap (pfet)/active (pdiff,apres,rpd,pdc,pdm12c)/active 181.160 # MODEL HANDLES THIS: sideoverlap (pfet)/active ~(pfet)/active (pdiff,apres,rpd,pdc,pdm12c)/active 52.200 sidewall (poly,fp,pres,rp,pc,pm12c)/active ~(poly,fp,pres,rp,pc,pm12c)/active ~(poly,fp,pres,rp,pc,pm12c)/active (poly,fp,pres,rp,pc,pm12c)/active 11.331 areacap (poly,fp,pres,rp,pc,pm12c)/active 4.074 overlap (poly,fp,pres,rp,pc,pm12c)/active ~space/w 4.074 perimc (poly,fp,pres,rp,pc,pm12c)/active ~(poly,fp,pres,rp,pc,pm12c)/active 4.622 sideoverlap (poly,fp,pres,rp,pc,pm12c)/active ~(poly,fp,pres,rp,pc,pm12c)/active ~space/w 4.622 #poly2 #rnw #metal1 sidewall (m1,fm1,rm1,ndc,ndm12c,pdc,pdm12c,pc,pm12c,m2c,m123c)/metal1 ~(m1,fm1,rm1,ndc,ndm12c,pdc,pdm12c,pc,pm12c,m2c,m123c)/metal1 ~(m1,fm1,rm1,ndc,ndm12c,pdc,pdm12c,pc,pm12c,m2c,m123c)/metal1 (m1,fm1,rm1,ndc,ndm12c,pdc,pdm12c,pc,pm12c,m2c,m123c)/metal1 20.619 areacap (m1,fm1,rm1,ndc,ndm12c,pdc,pdm12c,pc,pm12c,m2c,m123c)/metal1 1.666 #metal1-sub blocked by ~space/a overlap (m1,fm1,rm1,ndc,ndm12c,pdc,pdm12c,pc,pm12c,m2c,m123c)/metal1 ~space/w 1.666 ~space/a perimc (m1,fm1,rm1,ndc,ndm12c,pdc,pdm12c,pc,pm12c,m2c,m123c)/metal1 ~(m1,fm1,rm1,ndc,ndm12c,pdc,pdm12c,pc,pm12c,m2c,m123c)/metal1 2.226 sideoverlap (m1,fm1,rm1,ndc,ndm12c,pdc,pdm12c,pc,pm12c,m2c,m123c)/metal1 ~(m1,fm1,rm1,ndc,ndm12c,pdc,pdm12c,pc,pm12c,m2c,m123c)/metal1 ~space/w 2.226 ~space/a #rnw overlap (m1,fm1,rm1,ndc,ndm12c,pdc,pdm12c,pc,pm12c,m2c,m123c)/metal1 rnw,nwr/active 1.666 sideoverlap (m1,fm1,rm1,ndc,ndm12c,pdc,pdm12c,pc,pm12c,m2c,m123c)/metal1 ~(m1,fm1,rm1,ndc,ndm12c,pdc,pdm12c,pc,pm12c,m2c,m123c)/metal1 rnw,nwr/active 2.226 #metal1-diff blocked by overlap (m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c)/metal1 (ndiff,anres,rnd,ndc,ndm12c)/active 1.640 sideoverlap (m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c)/metal1 ~(m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c)/metal1 (ndiff,anres,rnd,ndc,ndm12c)/active 2.226 overlap (m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c)/metal1 (pdiff,apres,rpd,pdc,pdm12c)/active 1.640 sideoverlap (m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c)/metal1 ~(m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c)/metal1 (pdiff,apres,rpd,pdc,pdm12c)/active 2.226 #metal1-poly blocked by overlap (m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c)/metal1 (poly,fp,pres,rp,pc,pm12c,nfet,pfet,fet)/active 1.687 sideoverlap (m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c)/metal1 ~(m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c)/metal1 (poly,fp,pres,rp,pc,pm12c,nfet,pfet,fet)/active 2.250 sideoverlap (poly,fp,pres,rp,pc,pm12c,nfet,pfet,fet)/active ~(poly,fp,pres,rp,pc,pm12c,nfet,pfet,fet)/active (m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c)/metal1 2.250 #metal2 sidewall (m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 ~(m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 ~(m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 (m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 23.532 areacap (m2,fm2,rm2,m3c,m123c,m234c)/metal2 0.581 #metal2-sub blocked by overlap (m2,fm2,rm2,m3c,m123c,m234c)/metal2 ~space/w 0.581 ~space/a,~space/m1 perimc (m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 ~(m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 0.836 sideoverlap (m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 ~(m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 ~space/w 0.836 ~space/a,~space/m1 overlap (m2,fm2,rm2,m3c,m123c,m234c)/metal2 rnw,nwr/active 0.581 ~space/m1 sideoverlap (m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 ~(m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 rnw,nwr/active 0.836 ~space/m1 #metal2-*diff blocked by ~space/m1 overlap (m2,fm2,rm2,m3c,m123c,m234c)/metal2 (ndiff,anres,rnd,ndc,ndm12c)/active 0.720 ~space/m1 sideoverlap (m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 ~(m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 (ndiff,anres,rnd,ndc,ndm12c)/active 0.836 ~space/m1 overlap (m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 (pdiff,apres,rpd,pdc,pdm12c)/active 0.720 ~space/m1 sideoverlap (m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 ~(m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 (pdiff,apres,rpd,pdc,pdm12c)/active 0.836 ~space/m1 #metal2-poly blocked by ~space/m1 overlap (m2,fm2,rm2,m3c,m123c,m234c)/metal2 (poly,fp,pres,rp,pc,pm12c,nfet,pfet,fet)/active 0.583 ~space/m1 sideoverlap (m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 ~(m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 (poly,fp,pres,rp,pc,pm12c,nfet,pfet,fet)/active 0.840 ~space/m1 sideoverlap (poly,fp,pres,rp,pc,pm12c,nfet,pfet,fet)/active ~(poly,fp,pres,rp,pc,pm12c,nfet,pfet,fet)/active (m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 0.840 ~space/m1 #M2->M1 overlap (m2,fm2,rm2,m3c,m123c,m234c)/metal2 (m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c)/metal1 1.844 sideoverlap (m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 ~(m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 (m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c)/metal1 2.432 sideoverlap (m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c)/metal1 ~(m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c)/metal1 (m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 2.432 #metal3 sidewall (m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 (m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 24.216 areacap (m3,fm3,rm3,m4c,m234c)/metal3 0.352 #metal3-sub blocked by ~space/a,~space/m1,~space/m2 overlap (m3,fm3,rm3,m4c,m234c)/metal3 ~space/w 0.352 ~space/a,~space/m1,~space/m2 perimc (m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 0.514 sideoverlap (m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 ~space/w 0.514 ~space/a,~space/m1,~space/m2 #rnw overlap (m3,fm3,rm3,m4c,m234c)/metal3 rnw,nwr/active 0.352 ~space/m1,~space/m2 sideoverlap (m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 rnw,nwr/active 0.514 ~space/m1,~space/m2 #metal3-*diff blocked by ~space/m1,~space/m2 overlap (m3,fm3,rm3,m4c,m234c)/metal3 (ndiff,anres,rnd,ndc,ndm12c)/active 0.520 ~space/m1,~space/m2 sideoverlap (m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 (ndiff,anres,rnd,ndc,ndm12c)/active 0.514 ~space/m1,~space/m2 overlap (m3,fm3,rm3,m4c,m234c)/metal3 (pdiff,apres,rpd,pdc,pdm12c)/active 0.520 ~space/m1,~space/m2 sideoverlap (m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 (pdiff,apres,rpd,pdc,pdm12c)/active 0.514 ~space/m1,~space/m2 #metal3-poly blocked by ~space/m1,~space/m2 overlap (m3,fm3,rm3,m4c,m234c)/metal3 (poly,fp,pres,rp,pc,pm12c,nfet,pfet,fet)/active 0.352 ~space/m1,~space/m2 sideoverlap (m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 (poly,fp,pres,rp,pc,pm12c,nfet,pfet,fet)/active 0.516 ~space/m1,~space/m2 sideoverlap (poly,fp,pres,rp,pc,pm12c,nfet,pfet,fet)/active ~(poly,fp,pres,rp,pc,pm12c,nfet,pfet,fet)/active (m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 0.516 ~space/m1,~space/m2 #M3->M1 #metal3-metal1 blocked by ~space/m2 overlap (m3,fm3,rm3,m4c,m234c)/metal3 (m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c)/metal1 0.601 ~space/m2 sideoverlap (m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 (m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c)/metal1 0.864 ~space/m2 sideoverlap (m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c)/metal1 ~(m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c)/metal1 (m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 0.864 ~space/m2 #M3->M2 overlap (m3,fm3,rm3,m4c,m234c)/metal3 (m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 1.844 sideoverlap (m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 (m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 2.430 sideoverlap (m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 ~(m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 (m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 2.430 #metal4 sidewall (m4,fm4,rm4,m4c,m234c,pad)/metal4 ~(m4,fm4,rm4,m4c,m234c,pad)/metal4 ~(m4,fm4,rm4,m4c,m234c,pad)/metal4 (m4,fm4,rm4,m4c,m234c,pad)/metal4 64.860 areacap (m4,fm4,rm4,pad)/metal4 0.235 #metal4-sub blocked by ~space/a,~space/m1,~space/m2,~space/m3 overlap (m4,fm4,rm4,pad)/metal4 ~space/w 0.235 ~space/a,~space/m1,~space/m2,~space/m3 perimc (m4,fm4,rm4,m4c,m234c,pad)/metal4 ~(m4,fm4,rm4,m4c,m234c,pad)/metal4 0.802 sideoverlap (m4,fm4,rm4,m4c,m234c,pad)/metal4 ~(m4,fm4,rm4,m4c,m234c,pad)/metal4 ~space/w 0.802 ~space/a,~space/m1,~space/m2,~space/m3 #rnw overlap (m4,fm4,rm4,pad)/metal4 rnw,nwr/active 0.235 ~space/m1,~space/m2,~space/m3 sideoverlap (m4,fm4,rm4,m4c,m234c,pad)/metal4 ~(m4,fm4,rm4,m4c,m234c,pad)/metal4 rnw,nwr/active 0.802 ~space/m1,~space/m2,~space/m3 #metal4-*diff blocked by ~space/m1,~space/m2,~space/m3 overlap (m4,fm4,rm4,pad)/metal4 (ndiff,anres,rnd,ndc,ndm12c)/active 0.400 ~space/m1,~space/m2,~space/m3 sideoverlap (m4,fm4,rm4,m4c,m234c,pad)/metal4 ~(m4,fm4,rm4,m4c,m234c,pad)/metal4 (ndiff,anres,rnd,ndc,ndm12c)/active 0.802 ~space/m1,~space/m2,~space/m3 overlap (m4,fm4,rm4,pad)/metal4 (pdiff,apres,rpd,pdc,pdm12c)/active 0.400 ~space/m1,~space/m2,~space/m3 sideoverlap (m4,fm4,rm4,m4c,m234c,pad)/metal4 ~(m4,fm4,rm4,m4c,m234c,pad)/metal4 (pdiff,apres,rpd,pdc,pdm12c)/active 0.802 ~space/m1,~space/m2,~space/m3 #metal4-poly blocked by ~space/m1,~space/m2,~space/m3 overlap (m4,fm4,rm4,pad)/metal4 (poly,fp,pres,rp,pc,pm12c,nfet,pfet,fet)/active 0.271 ~space/m1,~space/m2,~space/m3 sideoverlap (m4,fm4,rm4,m4c,m234c,pad)/metal4 ~(m4,fm4,rm4,m4c,m234c,pad)/metal4 (poly,fp,pres,rp,pc,pm12c,nfet,pfet,fet)/active 0.666 ~space/m1,~space/m2,~space/m3 sideoverlap (poly,fp,pres,rp,pc,pm12c,nfet,pfet,fet)/active ~(poly,fp,pres,rp,pc,pm12c,nfet,pfet,fet)/active (m4,fm4,rm4,m4c,m234c,pad)/metal4 0.666 ~space/m1,~space/m2,~space/m3 #M4->M1 #metal4-metal1 blocked by ~space/m2,~space/m3 overlap (m4,fm4,rm4,pad)/metal4 (m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c)/metal1 0.359 ~space/m2,~space/m3 sideoverlap (m4,fm4,rm4,m4c,m234c,pad)/metal4 ~(m4,fm4,rm4,m4c,m234c,pad)/metal4 (m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c)/metal1 1.038 ~space/m2,~space/m3 sideoverlap (m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c)/metal1 ~(m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c)/metal1 (m4,fm4,rm4,m4c,m234c,pad)/metal4 1.038 ~space/m2,~space/m3 #M4->M2 #metal4-metal2 blocked by ~space/m3 overlap (m4,fm4,rm4,pad)/metal4 (m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 0.601 ~space/m3 sideoverlap (m4,fm4,rm4,m4c,m234c,pad)/metal4 ~(m4,fm4,rm4,m4c,m234c,pad)/metal4 (m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 1.698 ~space/m3 sideoverlap (m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 ~(m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 (m4,fm4,rm4,m4c,m234c,pad)/metal4 1.698 ~space/m3 #M4->M3 overlap (m4,fm4,rm4,pad)/metal4 (m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 1.844 sideoverlap (m4,fm4,rm4,m4c,m234c,pad)/metal4 ~(m4,fm4,rm4,m4c,m234c,pad)/metal4 (m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 4.604 sideoverlap (m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 (m4,fm4,rm4,m4c,m234c,pad)/metal4 4.604 #metal5 #metal6 #metal7 #metali #fets # fet pfet pdiff,pdc 2 pfet Vdd! nwell 52 181 # fet pfet pdiff,pdc 1 pfet Vdd! nwell 52 181 device mosfet pfet pfet pdiff,pdc nwell $VDD 52 181 # fet nfet ndiff,ndc 2 nfet Gnd! pwell 55 182 # fet nfet ndiff,ndc 1 nfet Gnd! pwell 55 182 device mosfet nfet nfet ndiff,ndc pwell $GND 55 182 fetresis pfet linear 12182 fetresis pfet saturation 12182 fetresis nfet linear 3961 fetresis nfet saturation 3961 # fet rnwell nsd,nsc 2 nwellResistor Gnd! nwell,pwell 0 0 # fet rpoly poly,pc 2 polyResistor Gnd! nwell,pwell 0 0 # fet nwr nwsd 2 nwellFig1bResistor Gnd! nwell,pwell 0 0 # fet rndiff ndiff,ndc 2 ndiffResistor Gnd! nwell,pwell 0 0 # fet rpdiff pdiff,pdc 2 pdiffResistor Gnd! nwell,pwell 0 0 device resistor None rnwell nsd,nsc device resistor None rpoly poly,pc device resistor None nwr nwsd device resistor None rndiff ndiff,ndc device resistor None rpdiff pdiff,pdc # fet rmetal1 metal1 2 metal1Resistor Gnd! nwell,pwell 0 0 # fet rmetal2 metal2 2 metal2Resistor Gnd! nwell,pwell 0 0 # fet rmetal3 metal3 2 metal3Resistor Gnd! nwell,pwell 0 0 # fet rmetal4 metal4 2 metal4Resistor Gnd! nwell,pwell 0 0 device resistor None rmetal1 *metal1 device resistor None rmetal2 *metal2 device resistor None rmetal3 *metal3 device resistor None rmetal4 *metal4 # fet pres poly,pc 2 presResistor Gnd! nwell,pwell 0 0 # fet anres ndiff,ndc 2 anresResistor Gnd! nwell,pwell 0 0 # fet apres pdiff,pdc 2 apresResistor Gnd! nwell,pwell 0 0 device resistor None pres poly,pc device resistor None anres ndiff,ndc device resistor None apres pdiff,pdc end wiring contact pdcontact 4 metal1 0 pdiff 0 contact ndcontact 4 metal1 0 ndiff 0 contact pcontact 4 metal1 0 poly 0 contact m2contact 4 metal1 0 metal2 0 contact m3contact 5 metal2 0 metal3 1 contact m4contact 4 metal3 0 metal4 0 end router layer2 metal2 3 m2,fm2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m123c/m2,m234c/m2,m3c/m2,m123c/m2,m234c/m2 4 poly,fp,pres,rp,ndiff,anres,rnd,nsd,nwsd,pdiff,apres,rpd,psd,m1,fm1,rm1 1 layer1 metal1 3 m1,fm1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1 3 contacts m2contact 4 gridspacing 8 end plowing fixed nfet,pfet,glass,pad covered nfet,pfet drag nfet,pfet end plot style colorversatec ndiff,anres,rnd,ndc/a,ndm12c/a yellow \ 5555 AAAA 5555 AAAA \ 5555 AAAA 5555 AAAA \ 5555 AAAA 5555 AAAA \ 5555 AAAA 5555 AAAA ndiff,anres,rnd,ndc/a,ndm12c/a cyan \ 0000 5555 0000 5555 \ 0000 5555 0000 5555 \ 0000 5555 0000 5555 \ 0000 5555 0000 5555 nsd,nwsd,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a yellow \ 1515 2A2A 5151 A2A2 \ 1515 2A2A 5151 A2A2 \ 1515 2A2A 5151 A2A2 \ 1515 2A2A 5151 A2A2 nsd,nwsd,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a cyan \ 0000 1515 0000 5151 \ 0000 1515 0000 5151 \ 0000 1515 0000 5151 \ 0000 1515 0000 5151 pdiff,apres,rpd,pdc/a,pdm12c/a yellow \ 5555 AAAA 5555 AAAA \ 5555 AAAA 5555 AAAA \ 5555 AAAA 5555 AAAA \ 5555 AAAA 5555 AAAA pdiff,apres,rpd,pdc/a,pdm12c/a cyan \ 0000 5555 0000 5555 \ 0000 5555 0000 5555 \ 0000 5555 0000 5555 \ 0000 5555 0000 5555 pdiff,apres,rpd,pdc/a,pdm12c/a magenta \ AAAA 0000 AAAA 0000 \ AAAA 0000 AAAA 0000 \ AAAA 0000 AAAA 0000 \ AAAA 0000 AAAA 0000 psd,psc/a,psm12c/a yellow \ 1515 2A2A 5151 A2A2 \ 1515 2A2A 5151 A2A2 \ 1515 2A2A 5151 A2A2 \ 1515 2A2A 5151 A2A2 psd,psc/a,psm12c/a cyan \ 0000 1515 0000 5151 \ 0000 1515 0000 5151 \ 0000 1515 0000 5151 \ 0000 1515 0000 5151 psd,psc/a,psm12c/a magenta \ 2A2A 0000 A2A2 0000 \ 2A2A 0000 A2A2 0000 \ 2A2A 0000 A2A2 0000 \ 2A2A 0000 A2A2 0000 poly,fp,pres,rp,pc/a,pm12c/a magenta \ 5555 AAAA 5555 AAAA \ 5555 AAAA 5555 AAAA \ 5555 AAAA 5555 AAAA \ 5555 AAAA 5555 AAAA nfet yellow \ 0505 8282 1414 0A0A \ 5050 2828 4141 A0A0 \ 0505 8282 1414 0A0A \ 5050 2828 4141 A0A0 nfet cyan \ 0000 0505 0000 1414 \ 0000 5050 0000 4141 \ 0000 0505 0000 1414 \ 0000 5050 0000 4141 nfet magenta \ 5050 2828 4141 A0A0 \ 0505 8282 1414 0A0A \ 5050 2828 4141 A0A0 \ 0505 8282 1414 0A0A pfet yellow \ 6363 A0A0 5050 2828 \ 3636 0A0A 0505 8282 \ 6363 A0A0 5050 2828 \ 3636 0A0A 0505 8282 pfet cyan \ 0000 5151 0000 5454 \ 0000 1515 0000 1515 \ 0000 5151 0000 5454 \ 0000 1515 0000 1515 pfet magenta \ 9494 0A0A 2525 8282 \ 4949 A0A0 5252 2828 \ 9494 0A0A 2525 8282 \ 4949 A0A0 5252 2828 m1,fm1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,m123c/m1 cyan \ AAAA 0000 AAAA 0000 \ AAAA 0000 AAAA 0000 \ AAAA 0000 AAAA 0000 \ AAAA 0000 AAAA 0000 m2,fm2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m234c/m2 cyan \ 0000 1111 0000 4444 \ 0000 1111 0000 4444 \ 0000 1111 0000 4444 \ 0000 1111 0000 4444 m2,fm2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m234c/m2 magenta \ 0000 4444 0000 1111 \ 0000 4444 0000 1111 \ 0000 4444 0000 1111 \ 0000 4444 0000 1111 m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1,gv1 black \ 0000 6666 6666 0000 \ 0000 9999 9999 0000 \ 0000 6666 6666 0000 \ 0000 9999 9999 0000 pad,glass black \ 0300 0700 0E00 1C00 \ 3800 7000 E000 C000 \ 00C0 00E0 0070 0038 \ 001C 000E 0007 0003 nwell yellow \ 0800 1000 2000 4000 \ 8000 0001 0002 0004 \ 0008 0010 0020 0040 \ 0080 0010 0200 0400 nwell cyan \ 1000 2000 4000 8000 \ 0001 0002 0004 0008 \ 0010 0020 0040 0080 \ 0100 0200 0400 0800 pwell yellow \ 1000 0400 0400 0100 \ 0100 0040 0040 0010 \ 0010 0004 0004 0001 \ 0001 4000 4000 1000 pwell cyan \ 0000 0800 0000 0200 \ 0000 0080 0000 0020 \ 0000 0008 0000 0002 \ 0000 8000 0000 2000 pwell magenta \ 0800 0000 0200 0000 \ 0080 0000 0020 0000 \ 0008 0000 0002 0000 \ 8000 0000 2000 0000 m3c/m2,m123c/m2,m234c/m2,gv2 black \ 0100 0000 0000 0000 \ 1010 0000 0000 0000 \ 0001 0000 0000 0000 \ 1010 0000 0000 0000 m3c/m2,m123c/m2,m234c/m2,gv2 cyan \ 0280 0000 0820 0000 \ 2008 0000 8002 0000 \ 8002 0000 2008 0000 \ 0820 0000 0280 0000 m3c/m2,m123c/m2,m234c/m2,gv2 magenta \ 0100 06C0 0440 1830 \ 1010 600C 4004 8003 \ 0001 C006 4004 3018 \ 1010 0C60 0440 0380 m3c/m2,m123c/m2,m234c/m2,gv2 black \ 0820 0820 0820 0FE0 \ E00F 2008 2008 2008 \ 2008 2008 2008 E00F \ 0000 0FE0 0820 0820 error_p,error_s,error_ps black \ 0000 3C3C 4646 4A4A \ 5252 6262 3C3C 0000 \ 0000 3C3C 4646 4A4A \ 5252 6262 3C3C 0000 magnet yellow \ AAAA 0000 5555 0000 \ AAAA 0000 5555 0000 \ AAAA 0000 5555 0000 \ AAAA 0000 5555 0000 fence magenta \ FFFF 0000 0000 0000 \ 0000 0000 0000 0000 \ FFFF 0000 0000 0000 \ 0000 0000 0000 0000 rotate cyan \ 0000 E0E0 E0E0 E0E0 \ 0000 0000 0000 0000 \ 0000 E0E0 E0E0 E0E0 \ 0000 0000 0000 0000 pc/a,pm12c/a,ndc/a,ndm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,gc,gc,gc X style versatec pfet \ 07c0 0f80 1f00 3e00 \ 7c00 f800 f001 e003 \ c007 800f 001f 003e \ 00c7 00f8 01f0 03e0 nfet \ 1f00 0f80 07c0 03e0 \ 01f0 00f8 007c 003e \ 001f 800f c007 e003 \ f001 f800 7c00 3e00 gv1 \ c3c3 c3c3 0000 0000 \ 0000 0000 c3c3 c3c3 \ c3c3 c3c3 0000 0000 \ 0000 0000 c3c3 c3c3 pwell \ 2020 2020 2020 2020 \ 2020 2020 2020 2020 \ 0000 0000 0000 0000 \ 0000 0000 0000 0000 nwell \ 0808 0404 0202 0101 \ 0000 0000 0000 0000 \ 0808 0404 0202 0101 \ 0000 0000 0000 0000 poly,fp,pres,rp,pc/a,pm12c/a,nfet,pfet \ 0808 0400 0202 0101 \ 8080 4000 2020 1010 \ 0808 0004 0202 0101 \ 8080 0040 2020 1010 m1,fm1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,m123c/m1 \ 8080 0000 0000 0000 \ 0808 0000 0000 0000 \ 8080 0000 0000 0000 \ 0808 0000 0000 0000 pad,glass \ 0000 0000 1c1c 3e3e \ 3636 3e3e 1c1c 0000 \ 0000 0000 1c1c 3e3e \ 3636 3e3e 1c1c 0000 nsd,nwsd,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a \ 0808 1414 2222 4141 \ 8080 4040 2020 1010 \ 0808 1414 2222 4141 \ 8080 4040 2020 1010 m2,fm2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m234c/m2 \ 0000 1111 0000 0000 \ 0000 1111 0000 0000 \ 0000 1111 0000 0000 \ 0000 1111 0000 0000 pdiff,apres,rpd,pdc/a,pdm12c/a,pfet \ 0000 0808 5555 8080 \ 0000 8080 5555 0808 \ 0000 0808 5555 8080 \ 0000 8080 5555 0808 psd,psc/a,psm12c/a \ 1414 2222 0000 2222 \ 4141 2222 0000 2222 \ 1414 2222 0000 2222 \ 4141 2222 0000 2222 ndiff,anres,rnd,ndc/a,ndm12c/a,nfet \ 0808 1010 2020 4040 \ 8080 4141 2222 1414 \ 0808 1010 2020 4040 \ 8080 4141 2222 1414 pc/a,pm12c/a,ndc/a,ndm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,gc,gc,gc X style gremlin pfet 9 nfet 10 gv1 11 pwell 15 nwell 16 poly,fp,pres,rp,pc/a,pm12c/a,nfet,pfet 19 pc/a,pm12c/a,ndc/a,ndm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,gc,gc,gc 22 pad,glass 23 nsd,nwsd,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a 24 gv1 28 pdiff,apres,rpd,pdc/a,pdm12c/a,pfet 29 psd,psc/a,psm12c/a 30 ndiff,anres,rnd,ndc/a,ndm12c/a,nfet 31 pc/a,pm12c/a,ndc/a,ndm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,gc,gc,gc,gv1 X end qflow-1.1.23/tech/osu035/osu035_stdcells.v0000755000175000001440000005670712526236535016574 0ustar timusers`timescale 1ns/10ps `celldefine module AND2X1 (A, B, Y); input A ; input B ; output Y ; and (Y, A, B); specify // delay parameters specparam tpllh$B$Y = 0.11:0.11:0.11, tphhl$B$Y = 0.14:0.14:0.14, tpllh$A$Y = 0.11:0.11:0.11, tphhl$A$Y = 0.12:0.12:0.12; // path delays (A *> Y) = (tpllh$A$Y, tphhl$A$Y); (B *> Y) = (tpllh$B$Y, tphhl$B$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module AND2X2 (A, B, Y); input A ; input B ; output Y ; and (Y, A, B); specify // delay parameters specparam tpllh$A$Y = 0.13:0.13:0.13, tphhl$A$Y = 0.15:0.15:0.15, tpllh$B$Y = 0.13:0.13:0.13, tphhl$B$Y = 0.17:0.17:0.17; // path delays (A *> Y) = (tpllh$A$Y, tphhl$A$Y); (B *> Y) = (tpllh$B$Y, tphhl$B$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module AOI21X1 (A, B, C, Y); input A ; input B ; input C ; output Y ; and (I0_out, A, B); or (I1_out, I0_out, C); not (Y, I1_out); specify // delay parameters specparam tplhl$A$Y = 0.088:0.088:0.088, tphlh$A$Y = 0.099:0.099:0.099, tplhl$B$Y = 0.086:0.086:0.086, tphlh$B$Y = 0.084:0.084:0.084, tplhl$C$Y = 0.068:0.071:0.074, tphlh$C$Y = 0.051:0.068:0.085; // path delays (A *> Y) = (tphlh$A$Y, tplhl$A$Y); (B *> Y) = (tphlh$B$Y, tplhl$B$Y); (C *> Y) = (tphlh$C$Y, tplhl$C$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module AOI22X1 (A, B, C, D, Y); input A ; input B ; input C ; input D ; output Y ; and (I0_out, A, B); and (I1_out, C, D); or (I2_out, I0_out, I1_out); not (Y, I2_out); specify // delay parameters specparam tplhl$C$Y = 0.066:0.069:0.071, tphlh$C$Y = 0.073:0.091:0.11, tplhl$D$Y = 0.065:0.068:0.071, tphlh$D$Y = 0.061:0.078:0.095, tplhl$A$Y = 0.095:0.11:0.12, tphlh$A$Y = 0.095:0.11:0.13, tplhl$B$Y = 0.094:0.11:0.12, tphlh$B$Y = 0.087:0.1:0.11; // path delays (A *> Y) = (tphlh$A$Y, tplhl$A$Y); (B *> Y) = (tphlh$B$Y, tplhl$B$Y); (C *> Y) = (tphlh$C$Y, tplhl$C$Y); (D *> Y) = (tphlh$D$Y, tplhl$D$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module BUFX2 (A, Y); input A ; output Y ; buf (Y, A); specify // delay parameters specparam tpllh$A$Y = 0.13:0.13:0.13, tphhl$A$Y = 0.15:0.15:0.15; // path delays (A *> Y) = (tpllh$A$Y, tphhl$A$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module BUFX4 (A, Y); input A ; output Y ; buf (Y, A); specify // delay parameters specparam tpllh$A$Y = 0.15:0.15:0.15, tphhl$A$Y = 0.16:0.16:0.16; // path delays (A *> Y) = (tpllh$A$Y, tphhl$A$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module CLKBUF1 (A, Y); input A ; output Y ; buf (Y, A); specify // delay parameters specparam tpllh$A$Y = 0.22:0.22:0.22, tphhl$A$Y = 0.23:0.23:0.23; // path delays (A *> Y) = (tpllh$A$Y, tphhl$A$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module CLKBUF2 (A, Y); input A ; output Y ; buf (Y, A); specify // delay parameters specparam tpllh$A$Y = 0.32:0.32:0.32, tphhl$A$Y = 0.33:0.33:0.33; // path delays (A *> Y) = (tpllh$A$Y, tphhl$A$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module CLKBUF3 (A, Y); input A ; output Y ; buf (Y, A); specify // delay parameters specparam tpllh$A$Y = 0.42:0.42:0.42, tphhl$A$Y = 0.43:0.43:0.43; // path delays (A *> Y) = (tpllh$A$Y, tphhl$A$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module DFFNEGX1 (CLK, D, Q); input CLK ; input D ; output Q ; reg NOTIFIER ; not (I0_CLOCK, CLK); udp_dff (DS0000, D, I0_CLOCK, 1'B0, 1'B0, NOTIFIER); not (P0002, DS0000); buf (Q, DS0000); specify // delay parameters specparam tphlh$CLK$Q = 0.2:0.2:0.2, tphhl$CLK$Q = 0.2:0.2:0.2, tminpwh$CLK = 0.061:0.14:0.22, tminpwl$CLK = 0.13:0.16:0.2, tsetup_negedge$D$CLK = 0.28:0.28:0.28, thold_negedge$D$CLK = -0.094:-0.094:-0.094, tsetup_posedge$D$CLK = 0.28:0.28:0.28, thold_posedge$D$CLK = -0.094:-0.094:-0.094; // path delays (CLK *> Q) = (tphlh$CLK$Q, tphhl$CLK$Q); $setup(negedge D, negedge CLK, tsetup_negedge$D$CLK, NOTIFIER); $hold (negedge D, negedge CLK, thold_negedge$D$CLK, NOTIFIER); $setup(posedge D, negedge CLK, tsetup_posedge$D$CLK, NOTIFIER); $hold (posedge D, negedge CLK, thold_posedge$D$CLK, NOTIFIER); $width(posedge CLK, tminpwh$CLK, 0, NOTIFIER); $width(negedge CLK, tminpwl$CLK, 0, NOTIFIER); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module DFFPOSX1 (CLK, D, Q); input CLK ; input D ; output Q ; reg NOTIFIER ; udp_dff (DS0000, D, CLK, 1'B0, 1'B0, NOTIFIER); not (P0002, DS0000); buf (Q, DS0000); specify // delay parameters specparam tpllh$CLK$Q = 0.16:0.16:0.16, tplhl$CLK$Q = 0.25:0.25:0.25, tminpwh$CLK = 0.081:0.17:0.25, tminpwl$CLK = 0.079:0.15:0.22, tsetup_negedge$D$CLK = 0.28:0.28:0.28, thold_negedge$D$CLK = -0.094:-0.094:-0.094, tsetup_posedge$D$CLK = 0.28:0.28:0.28, thold_posedge$D$CLK = -0.094:-0.094:-0.094; // path delays (CLK *> Q) = (tpllh$CLK$Q, tplhl$CLK$Q); $setup(negedge D, posedge CLK, tsetup_negedge$D$CLK, NOTIFIER); $hold (negedge D, posedge CLK, thold_negedge$D$CLK, NOTIFIER); $setup(posedge D, posedge CLK, tsetup_posedge$D$CLK, NOTIFIER); $hold (posedge D, posedge CLK, thold_posedge$D$CLK, NOTIFIER); $width(posedge CLK, tminpwh$CLK, 0, NOTIFIER); $width(negedge CLK, tminpwl$CLK, 0, NOTIFIER); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module DFFSR (CLK, D, R, S, Q); input CLK ; input D ; input R ; input S ; output Q ; reg NOTIFIER ; not (I0_CLEAR, R); not (I0_SET, S); udp_dff (P0003, D_, CLK, I0_SET, I0_CLEAR, NOTIFIER); not (D_, D); not (P0002, P0003); buf (Q, P0002); and (\D&S , D, S); not (I7_out, D); and (\~D&R , I7_out, R); and (\S&R , S, R); specify // delay parameters specparam tphlh$S$Q = 0.45:0.45:0.45, tpllh$R$Q = 0.32:0.32:0.32, tphhl$R$Q = 0.34:0.34:0.35, tpllh$CLK$Q = 0.52:0.52:0.52, tplhl$CLK$Q = 0.52:0.52:0.52, tminpwl$S = 0.062:0.26:0.45, tminpwl$R = 0.038:0.19:0.35, tminpwh$CLK = 0.27:0.39:0.52, tminpwl$CLK = 0.26:0.29:0.32, tsetup_negedge$D$CLK = 0.094:0.094:0.094, thold_negedge$D$CLK = 0.000000059:0.000000059:0.000000059, tsetup_posedge$D$CLK = 0.19:0.19:0.19, thold_posedge$D$CLK = 0.000000061:0.000000061:0.000000061, trec$R$CLK = -0.094:-0.094:-0.094, trem$R$CLK = 0.28:0.28:0.28, trec$R$S = 0.000000061:0.000000061:0.000000061, trec$S$CLK = 0:0:0, trem$S$CLK = 0.094:0.094:0.094, trec$S$R = 0.094:0.094:0.094; // path delays (CLK *> Q) = (tpllh$CLK$Q, tplhl$CLK$Q); (R *> Q) = (tpllh$R$Q, tphhl$R$Q); (S *> Q) = (tphlh$S$Q, 0); $setup(negedge D, posedge CLK &&& \S&R , tsetup_negedge$D$CLK, NOTIFIER); $hold (negedge D, posedge CLK &&& \S&R , thold_negedge$D$CLK, NOTIFIER); $setup(posedge D, posedge CLK &&& \S&R , tsetup_posedge$D$CLK, NOTIFIER); $hold (posedge D, posedge CLK &&& \S&R , thold_posedge$D$CLK, NOTIFIER); $recovery(posedge R, posedge CLK &&& \D&S , trec$R$CLK, NOTIFIER); $removal (posedge R, posedge CLK &&& \D&S , trem$R$CLK, NOTIFIER); $recovery(posedge R, posedge S, trec$R$S, NOTIFIER); $recovery(posedge S, posedge CLK &&& \~D&R , trec$S$CLK, NOTIFIER); $removal (posedge S, posedge CLK &&& \~D&R , trem$S$CLK, NOTIFIER); $recovery(posedge S, posedge R, trec$S$R, NOTIFIER); $width(negedge S, tminpwl$S, 0, NOTIFIER); $width(negedge R, tminpwl$R, 0, NOTIFIER); $width(posedge CLK, tminpwh$CLK, 0, NOTIFIER); $width(negedge CLK, tminpwl$CLK, 0, NOTIFIER); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module FAX1 (A, B, C, YC, YS); input A ; input B ; input C ; output YC ; output YS ; and (I0_out, A, B); and (I1_out, B, C); and (I3_out, C, A); or (YC, I0_out, I1_out, I3_out); xor (I5_out, A, B); xor (YS, I5_out, C); specify // delay parameters specparam tpllh$A$YS = 0.29:0.31:0.33, tplhl$A$YS = 0.3:0.3:0.3, tpllh$A$YC = 0.19:0.19:0.19, tphhl$A$YC = 0.21:0.21:0.21, tpllh$B$YS = 0.3:0.33:0.35, tplhl$B$YS = 0.29:0.31:0.33, tpllh$B$YC = 0.18:0.2:0.22, tphhl$B$YC = 0.22:0.22:0.22, tpllh$C$YS = 0.31:0.32:0.33, tplhl$C$YS = 0.29:0.3:0.3, tpllh$C$YC = 0.17:0.19:0.2, tphhl$C$YC = 0.2:0.2:0.2; // path delays (A *> YC) = (tpllh$A$YC, tphhl$A$YC); (A *> YS) = (tpllh$A$YS, tplhl$A$YS); (B *> YC) = (tpllh$B$YC, tphhl$B$YC); (B *> YS) = (tpllh$B$YS, tplhl$B$YS); (C *> YC) = (tpllh$C$YC, tphhl$C$YC); (C *> YS) = (tpllh$C$YS, tplhl$C$YS); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module HAX1 (A, B, YC, YS); input A ; input B ; output YC ; output YS ; and (YC, A, B); xor (YS, A, B); specify // delay parameters specparam tpllh$A$YS = 0.23:0.23:0.23, tplhl$A$YS = 0.25:0.25:0.25, tpllh$A$YC = 0.14:0.14:0.14, tphhl$A$YC = 0.18:0.18:0.18, tpllh$B$YS = 0.22:0.22:0.22, tplhl$B$YS = 0.25:0.25:0.25, tpllh$B$YC = 0.14:0.14:0.14, tphhl$B$YC = 0.16:0.16:0.16; // path delays (A *> YC) = (tpllh$A$YC, tphhl$A$YC); (A *> YS) = (tpllh$A$YS, tplhl$A$YS); (B *> YC) = (tpllh$B$YC, tphhl$B$YC); (B *> YS) = (tpllh$B$YS, tplhl$B$YS); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module INVX1 (A, Y); input A ; output Y ; not (Y, A); specify // delay parameters specparam tplhl$A$Y = 0.053:0.053:0.053, tphlh$A$Y = 0.058:0.058:0.058; // path delays (A *> Y) = (tphlh$A$Y, tplhl$A$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module INVX2 (A, Y); input A ; output Y ; not (Y, A); specify // delay parameters specparam tplhl$A$Y = 0.053:0.053:0.053, tphlh$A$Y = 0.058:0.058:0.058; // path delays (A *> Y) = (tphlh$A$Y, tplhl$A$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module INVX4 (A, Y); input A ; output Y ; not (Y, A); specify // delay parameters specparam tplhl$A$Y = 0.053:0.053:0.053, tphlh$A$Y = 0.058:0.058:0.058; // path delays (A *> Y) = (tphlh$A$Y, tplhl$A$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module INVX8 (A, Y); input A ; output Y ; not (Y, A); specify // delay parameters specparam tplhl$A$Y = 0.053:0.053:0.053, tphlh$A$Y = 0.058:0.058:0.058; // path delays (A *> Y) = (tphlh$A$Y, tplhl$A$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module LATCH (CLK, D, Q); input CLK ; input D ; output Q ; reg NOTIFIER ; udp_tlat (DS0000, D, CLK, 1'B0, 1'B0, NOTIFIER); not (P0000, DS0000); buf (Q, DS0000); specify // delay parameters specparam tpllh$D$Q = 0.3:0.3:0.3, tphhl$D$Q = 0.34:0.34:0.34, tpllh$CLK$Q = 0.25:0.25:0.25, tplhl$CLK$Q = 0.34:0.34:0.34, tminpwh$CLK = 0.079:0.21:0.34, tsetup_negedge$D$CLK = 0.28:0.28:0.28, thold_negedge$D$CLK = -0.094:-0.094:-0.094, tsetup_posedge$D$CLK = 0.28:0.28:0.28, thold_posedge$D$CLK = -0.094:-0.094:-0.094; // path delays (CLK *> Q) = (tpllh$CLK$Q, tplhl$CLK$Q); (D *> Q) = (tpllh$D$Q, tphhl$D$Q); $setup(negedge D, negedge CLK, tsetup_negedge$D$CLK, NOTIFIER); $hold (negedge D, negedge CLK, thold_negedge$D$CLK, NOTIFIER); $setup(posedge D, negedge CLK, tsetup_posedge$D$CLK, NOTIFIER); $hold (posedge D, negedge CLK, thold_posedge$D$CLK, NOTIFIER); $width(posedge CLK, tminpwh$CLK, 0, NOTIFIER); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module MUX2X1 (A, B, S, Y); input A ; input B ; input S ; output Y ; udp_mux2 (I0_out, B, A, S); not (Y, I0_out); specify // delay parameters specparam tpllh$S$Y = 0.15:0.15:0.15, tplhl$S$Y = 0.16:0.16:0.16, tplhl$A$Y = 0.082:0.082:0.082, tphlh$A$Y = 0.11:0.11:0.11, tplhl$B$Y = 0.094:0.094:0.094, tphlh$B$Y = 0.096:0.096:0.096; // path delays (A *> Y) = (tphlh$A$Y, tplhl$A$Y); (B *> Y) = (tphlh$B$Y, tplhl$B$Y); (S *> Y) = (tpllh$S$Y, tplhl$S$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module NAND2X1 (A, B, Y); input A ; input B ; output Y ; and (I0_out, A, B); not (Y, I0_out); specify // delay parameters specparam tplhl$A$Y = 0.051:0.051:0.051, tphlh$A$Y = 0.084:0.084:0.084, tplhl$B$Y = 0.051:0.051:0.051, tphlh$B$Y = 0.069:0.069:0.069; // path delays (A *> Y) = (tphlh$A$Y, tplhl$A$Y); (B *> Y) = (tphlh$B$Y, tplhl$B$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module NAND3X1 (A, B, C, Y); input A ; input B ; input C ; output Y ; and (I1_out, A, B, C); not (Y, I1_out); specify // delay parameters specparam tplhl$B$Y = 0.06:0.06:0.06, tphlh$B$Y = 0.1:0.1:0.1, tplhl$A$Y = 0.063:0.063:0.063, tphlh$A$Y = 0.12:0.12:0.12, tplhl$C$Y = 0.053:0.053:0.053, tphlh$C$Y = 0.076:0.076:0.076; // path delays (A *> Y) = (tphlh$A$Y, tplhl$A$Y); (B *> Y) = (tphlh$B$Y, tplhl$B$Y); (C *> Y) = (tphlh$C$Y, tplhl$C$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module NOR2X1 (A, B, Y); input A ; input B ; output Y ; or (I0_out, A, B); not (Y, I0_out); specify // delay parameters specparam tplhl$B$Y = 0.07:0.07:0.07, tphlh$B$Y = 0.063:0.063:0.063, tplhl$A$Y = 0.094:0.094:0.094, tphlh$A$Y = 0.075:0.075:0.075; // path delays (A *> Y) = (tphlh$A$Y, tplhl$A$Y); (B *> Y) = (tphlh$B$Y, tplhl$B$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module NOR3X1 (A, B, C, Y); input A ; input B ; input C ; output Y ; or (I1_out, A, B, C); not (Y, I1_out); specify // delay parameters specparam tplhl$B$Y = 0.13:0.13:0.13, tphlh$B$Y = 0.099:0.099:0.099, tplhl$C$Y = 0.083:0.083:0.083, tphlh$C$Y = 0.064:0.064:0.064, tplhl$A$Y = 0.15:0.15:0.15, tphlh$A$Y = 0.11:0.11:0.11; // path delays (A *> Y) = (tphlh$A$Y, tplhl$A$Y); (B *> Y) = (tphlh$B$Y, tplhl$B$Y); (C *> Y) = (tphlh$C$Y, tplhl$C$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module OAI21X1 (A, B, C, Y); input A ; input B ; input C ; output Y ; or (I0_out, A, B); and (I1_out, I0_out, C); not (Y, I1_out); specify // delay parameters specparam tplhl$A$Y = 0.087:0.087:0.087, tphlh$A$Y = 0.098:0.098:0.098, tplhl$B$Y = 0.064:0.064:0.064, tphlh$B$Y = 0.09:0.09:0.09, tplhl$C$Y = 0.046:0.062:0.079, tphlh$C$Y = 0.07:0.076:0.081; // path delays (A *> Y) = (tphlh$A$Y, tplhl$A$Y); (B *> Y) = (tphlh$B$Y, tplhl$B$Y); (C *> Y) = (tphlh$C$Y, tplhl$C$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module OAI22X1 (A, B, C, D, Y); input A ; input B ; input C ; input D ; output Y ; or (I0_out, A, B); or (I1_out, C, D); and (I2_out, I0_out, I1_out); not (Y, I2_out); specify // delay parameters specparam tplhl$D$Y = 0.057:0.076:0.096, tphlh$D$Y = 0.078:0.082:0.086, tplhl$C$Y = 0.072:0.094:0.12, tphlh$C$Y = 0.085:0.09:0.094, tplhl$A$Y = 0.08:0.1:0.12, tphlh$A$Y = 0.11:0.11:0.12, tplhl$B$Y = 0.063:0.082:0.1, tphlh$B$Y = 0.096:0.1:0.11; // path delays (A *> Y) = (tphlh$A$Y, tplhl$A$Y); (B *> Y) = (tphlh$B$Y, tplhl$B$Y); (C *> Y) = (tphlh$C$Y, tplhl$C$Y); (D *> Y) = (tphlh$D$Y, tplhl$D$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module OR2X1 (A, B, Y); input A ; input B ; output Y ; or (Y, A, B); specify // delay parameters specparam tpllh$B$Y = 0.15:0.15:0.15, tphhl$B$Y = 0.13:0.13:0.13, tpllh$A$Y = 0.12:0.12:0.12, tphhl$A$Y = 0.12:0.12:0.12; // path delays (A *> Y) = (tpllh$A$Y, tphhl$A$Y); (B *> Y) = (tpllh$B$Y, tphhl$B$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module OR2X2 (A, B, Y); input A ; input B ; output Y ; or (Y, A, B); specify // delay parameters specparam tpllh$B$Y = 0.18:0.18:0.18, tphhl$B$Y = 0.16:0.16:0.16, tpllh$A$Y = 0.15:0.15:0.15, tphhl$A$Y = 0.15:0.15:0.15; // path delays (A *> Y) = (tpllh$A$Y, tphhl$A$Y); (B *> Y) = (tpllh$B$Y, tphhl$B$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module PADINC (YPAD, DI); input YPAD ; output DI ; buf (DI, YPAD); specify // delay parameters specparam tpllh$YPAD$DI = 0.15:0.15:0.15, tphhl$YPAD$DI = 0.17:0.17:0.17; // path delays (YPAD *> DI) = (tpllh$YPAD$DI, tphhl$YPAD$DI); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module PADINOUT (DO, OEN, DI, YPAD); input DO ; input OEN ; output DI ; inout YPAD ; bufif1 (YPAD, DO, OEN); buf (DI, YPAD); specify // delay parameters specparam tpllh$DO$YPAD = 0.59:0.59:0.59, tphhl$DO$YPAD = 0.59:0.59:0.59, tpzh$OEN$YPAD = 1.1:1.1:1.1, tpzl$OEN$YPAD = 0.65:0.65:0.65, tplz$OEN$YPAD = 0.82:0.82:0.82, tphz$OEN$YPAD = 1.5:1.5:1.5, tpllh$YPAD$DI = 0.15:0.15:0.15, tphhl$YPAD$DI = 0.17:0.17:0.17; // path delays (DO *> YPAD) = (tpllh$DO$YPAD, tphhl$DO$YPAD); (OEN *> YPAD) = (0, 0, tplz$OEN$YPAD, tpzh$OEN$YPAD, tphz$OEN$YPAD, tpzl$OEN$YPAD); (YPAD *> DI) = (tpllh$YPAD$DI, tphhl$YPAD$DI); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module PADOUT (DO, YPAD); input DO ; output YPAD ; buf (YPAD, DO); specify // delay parameters specparam tpllh$DO$YPAD = 0.59:0.59:0.59, tphhl$DO$YPAD = 0.59:0.59:0.59; // path delays (DO *> YPAD) = (tpllh$DO$YPAD, tphhl$DO$YPAD); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module TBUFX1 (A, EN, Y); input A ; input EN ; output Y ; not (I0_out, A); bufif1 (Y, I0_out, EN); specify // delay parameters specparam tpzh$EN$Y = 0.095:0.095:0.095, tpzl$EN$Y = 0.037:0.037:0.037, tplz$EN$Y = 0.052:0.052:0.052, tphz$EN$Y = 0.094:0.094:0.094, tplhl$A$Y = 0.077:0.077:0.077, tphlh$A$Y = 0.099:0.099:0.099; // path delays (A *> Y) = (tphlh$A$Y, tplhl$A$Y); (EN *> Y) = (0, 0, tplz$EN$Y, tpzh$EN$Y, tphz$EN$Y, tpzl$EN$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module TBUFX2 (A, EN, Y); input A ; input EN ; output Y ; not (I0_out, A); bufif1 (Y, I0_out, EN); specify // delay parameters specparam tplhl$A$Y = 0.077:0.077:0.077, tphlh$A$Y = 0.099:0.099:0.099, tpzh$EN$Y = 0.096:0.096:0.096, tpzl$EN$Y = 0.037:0.037:0.037, tplz$EN$Y = 0.052:0.052:0.052, tphz$EN$Y = 0.094:0.094:0.094; // path delays (A *> Y) = (tphlh$A$Y, tplhl$A$Y); (EN *> Y) = (0, 0, tplz$EN$Y, tpzh$EN$Y, tphz$EN$Y, tpzl$EN$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module XNOR2X1 (A, B, Y); input A ; input B ; output Y ; xor (I0_out, A, B); not (Y, I0_out); specify // delay parameters specparam tpllh$A$Y = 0.12:0.12:0.12, tplhl$A$Y = 0.12:0.12:0.12, tpllh$B$Y = 0.15:0.15:0.15, tplhl$B$Y = 0.14:0.14:0.14; // path delays (A *> Y) = (tpllh$A$Y, tplhl$A$Y); (B *> Y) = (tpllh$B$Y, tplhl$B$Y); endspecify endmodule `endcelldefine `timescale 1ns/10ps `celldefine module XOR2X1 (A, B, Y); input A ; input B ; output Y ; xor (Y, A, B); specify // delay parameters specparam tpllh$B$Y = 0.14:0.14:0.14, tplhl$B$Y = 0.15:0.15:0.15, tpllh$A$Y = 0.12:0.12:0.12, tplhl$A$Y = 0.12:0.12:0.12; // path delays (A *> Y) = (tpllh$A$Y, tplhl$A$Y); (B *> Y) = (tpllh$B$Y, tplhl$B$Y); endspecify endmodule `endcelldefine primitive udp_dff (out, in, clk, clr, set, NOTIFIER); output out; input in, clk, clr, set, NOTIFIER; reg out; table // in clk clr set NOT : Qt : Qt+1 // 0 r ? 0 ? : ? : 0 ; // clock in 0 1 r 0 ? ? : ? : 1 ; // clock in 1 1 * 0 ? ? : 1 : 1 ; // reduce pessimism 0 * ? 0 ? : 0 : 0 ; // reduce pessimism ? f ? ? ? : ? : - ; // no changes on negedge clk * b ? ? ? : ? : - ; // no changes when in switches ? ? ? 1 ? : ? : 1 ; // set output ? b 0 * ? : 1 : 1 ; // cover all transistions on set 1 x 0 * ? : 1 : 1 ; // cover all transistions on set ? ? 1 0 ? : ? : 0 ; // reset output ? b * 0 ? : 0 : 0 ; // cover all transistions on clr 0 x * 0 ? : 0 : 0 ; // cover all transistions on clr ? ? ? ? * : ? : x ; // any notifier changed endtable endprimitive // udp_dff primitive udp_tlat (out, in, enable, clr, set, NOTIFIER); output out; input in, enable, clr, set, NOTIFIER; reg out; table // in enable clr set NOT : Qt : Qt+1 // 1 1 0 ? ? : ? : 1 ; // 0 1 ? 0 ? : ? : 0 ; // 1 * 0 ? ? : 1 : 1 ; // reduce pessimism 0 * ? 0 ? : 0 : 0 ; // reduce pessimism * 0 ? ? ? : ? : - ; // no changes when in switches ? ? ? 1 ? : ? : 1 ; // set output ? 0 0 * ? : 1 : 1 ; // cover all transistions on set 1 ? 0 * ? : 1 : 1 ; // cover all transistions on set ? ? 1 0 ? : ? : 0 ; // reset output ? 0 * 0 ? : 0 : 0 ; // cover all transistions on clr 0 ? * 0 ? : 0 : 0 ; // cover all transistions on clr ? ? ? ? * : ? : x ; // any notifier changed endtable endprimitive // udp_tlat primitive udp_rslat (out, clr, set, NOTIFIER); output out; input clr, set, NOTIFIER; reg out; table // clr set NOT : Qt : Qt+1 // ? 1 ? : ? : 1 ; // set output 0 * ? : 1 : 1 ; // cover all transistions on set 1 0 ? : ? : 0 ; // reset output * 0 ? : 0 : 0 ; // cover all transistions on clr ? ? * : ? : x ; // any notifier changed endtable endprimitive // udp_tlat primitive udp_mux2 (out, in0, in1, sel); output out; input in0, in1, sel; table // in0 in1 sel : out // 1 ? 0 : 1 ; 0 ? 0 : 0 ; ? 1 1 : 1 ; ? 0 1 : 0 ; 0 0 x : 0 ; 1 1 x : 1 ; endtable endprimitive // udp_mux2 module PADNC(); endmodule module PADFC(); endmodule module PADGND(); endmodule module PADVDD(); endmodule qflow-1.1.23/tech/osu035/osu035.sh0000644000175000001440000000617312526236535015031 0ustar timusers#!/bin/tcsh #--------------------------------------------------------------- # Shell script setting up all variables used by the qflow scripts # for this project #--------------------------------------------------------------- # The LEF file containing standard cell macros set leffile=osu035_stdcells.lef # The SPICE netlist containing subcell definitions for all the standard cells set spicefile=osu035_stdcells.sp # The liberty format file containing standard cell timing and function information set libertyfile=osu035_stdcells.lib # If there is another LEF file containing technology information # that is separate from the file containing standard cell macros, # set this. Otherwise, leave it defined as an empty string. set techleffile="" # All cells below should be the lowest output drive strength value, # if the standard cell set has multiple cells with different drive # strengths. Comment out any cells that do not exist. set flopcell=DFFPOSX1 ;# Standard positive-clocked DFF, no set or reset # set flopset=DFFS ;# DFF with preset, if available # set flopreset=DFFSR ;# DFF with clear, if available set flopsetreset=DFFSR ;# DFF with both set and clear set setpin=S ;# The name of the set pin on DFFs set resetpin=R ;# The name of the clear/reset pin on DFFs set setpininvert=1 ;# Set this to 1 if the set pin is inverted (!set) set resetpininvert=1 ;# Set this to 1 if the reset pin is inverted (!reset) set floppinout=Q ;# Name of the output pin on DFFs set floppinin=D ;# Name of the output pin on DFFs set floppinclk=CLK ;# Name of the clock pin on DFFs set bufcell=BUFX2 ;# Minimum drive strength buffer cell set bufpin_in=A ;# Name of input port to buffer cell set bufpin_out=Y ;# Name of output port to buffer cell set inverter=INVX1 ;# Minimum drive strength inverter cell set invertpin_in=A ;# Name of input port to inverter cell set invertpin_out=Y ;# Name of output port to inverter cell set norgate=NOR2X1 ;# 2-input NOR gate, minimum drive strength set norpin_in1=A ;# Name of first input pin to NOR gate set norpin_in2=B ;# Name of second input pin to NOR gate set norpin_out=Y ;# Name of output pin from OR gate set nandgate=NAND2X1 ;# 2-input NAND gate, minimum drive strength set nandpin_in1=A ;# Name of first input pin to NAND gate set nandpin_in2=B ;# Name of second input pin to NAND gate set nandpin_out=Y ;# Name of output pin from NAND gate set fillcell=FILL ;# Spacer (filler) cell (prefix, if more than one) set tiehi="" ;# Cell to connect to power, if one exists set tiehipin_out="" ;# Output pin name of tiehi cell, if it exists set tielo="" ;# Cell to connect to ground, if one exists set tielopin_out="" ;# Output pin name of tielo cell, if it exists set gndnet=gnd ;# Name used for ground pins in standard cells set vddnet=vdd ;# Name used for power pins in standard cells set separator="" ;# Separator between gate names and drive strengths set techfile=SCN4M_SUBM.20 ;# magic techfile set magicrc=osu035.magicrc ;# magic startup script set gdsfile=osu035_stdcells.gds ;# GDS database of standard cells set fanout_options="-l 200 -c 50" ;# blifFanout target maximum latency ;# per gate 200ps, output load set to 50fF qflow-1.1.23/tech/osu035/osu035.magicrc.in0000644000175000001440000000047612526236535016431 0ustar timusers#----------------------------------------------------- # .magicrc startup file for OSU035 project under qflow #----------------------------------------------------- path sys +QFLOW_LIB_DIR/tech/osu035 tech load SCN4M_SUBM.20 -noprompt scalegrid 1 4 set GND gnd set VDD vdd drc euclidean on drc off addpath digital qflow-1.1.23/tech/osu035/osu035.par0000644000175000001440000000316212526236535015174 0ustar timusers# osu035.par --- Parameter file for GrayWolf # NOTE: all distance units are in centimicrons unless otherwise stated RULES # values are resistance in ohms/sq and capacitance in fF/um^2 layer metal1 0.07 0.030 horizontal layer metal2 0.07 0.017 vertical layer metal3 0.07 0.006 horizontal layer metal4 0.04 0.004 vertical via via12 metal1 metal2 via via23 metal2 metal3 via via34 metal3 metal4 width metal1 60 width metal2 60 width metal3 60 width metal4 120 width via12 60 width via23 60 width via34 120 # Set spacing = track pitch - width, so that GrayWolf places pins # on the right pitch. # Pitches are (in um): # metal1 = 200, metal2 = 160, metal3 = 200, metal4 = 320 spacing metal1 metal1 140 spacing metal2 metal2 100 spacing metal3 metal3 140 spacing metal4 metal4 200 # Stacked vias allowed spacing via12 via23 0 spacing via23 via34 0 overhang via12 metal1 8 overhang via12 metal2 6 overhang via23 metal2 8 overhang via23 metal3 6 overhang via34 metal3 14 overhang via34 metal4 16 ENDRULES *vertical_wire_weight : 1.0 *vertical_path_weight : 1.0 *padspacing : variable *rowSep : 0.0 0 *track.pitch : 160 *graphics.wait : off *last_chance.wait : off *random.seed : 12345 TWMC*chip.aspect.ratio : 0.75 TWSC*feedThruWidth : 160 layer 1 TWSC*do.global.route : on TWSC*ignore_feeds : true TWSC*call_row_evener : true TWSC*even_rows_maximally : true # TWSC*no.graphics : on GENR*row_to_tile_spacing: 1 # GENR*numrows : 6 GENR*flip_alternate_rows : 1 qflow-1.1.23/tech/osu035/osu035_stdcells.lef0000664000175000001440000023261512535603557017070 0ustar timusers# LEF file generated by Abstract Generator version 5.5.10 on Jul 30 14:47:58 2004 # # Contains LEF for all bins. # Options: [x] Antenna # [x] Geometry # [x] Technology VERSION 5.4 ; NAMESCASESENSITIVE ON ; BUSBITCHARS "[]" ; DIVIDERCHAR "/" ; UNITS DATABASE MICRONS 1000 ; END UNITS USEMINSPACING OBS ON ; USEMINSPACING PIN OFF ; CLEARANCEMEASURE EUCLIDEAN ; MANUFACTURINGGRID 0.1 ; LAYER nwell TYPE MASTERSLICE ; END nwell LAYER nactive TYPE MASTERSLICE ; END nactive LAYER pactive TYPE MASTERSLICE ; END pactive LAYER poly TYPE MASTERSLICE ; END poly LAYER cc TYPE CUT ; SPACING 0.9 ; END cc LAYER metal1 TYPE ROUTING ; DIRECTION HORIZONTAL ; PITCH 2 ; OFFSET 1 ; WIDTH 0.6 ; SPACING 0.6 ; RESISTANCE RPERSQ 0.07 ; CAPACITANCE CPERSQDIST 3e-05 ; END metal1 LAYER via1 TYPE CUT ; SPACING 0.6 ; END via1 LAYER metal2 TYPE ROUTING ; DIRECTION VERTICAL ; PITCH 1.6 ; OFFSET 0.8 ; WIDTH 0.6 ; SPACING 0.6 ; RESISTANCE RPERSQ 0.07 ; CAPACITANCE CPERSQDIST 1.7e-05 ; END metal2 LAYER via2 TYPE CUT ; SPACING 0.6 ; END via2 LAYER metal3 TYPE ROUTING ; DIRECTION HORIZONTAL ; PITCH 2 ; OFFSET 1 ; WIDTH 0.6 ; SPACING 0.6 ; RESISTANCE RPERSQ 0.07 ; CAPACITANCE CPERSQDIST 7e-06 ; END metal3 LAYER via3 TYPE CUT ; SPACING 0.8 ; END via3 LAYER metal4 TYPE ROUTING ; DIRECTION VERTICAL ; PITCH 3.2 ; OFFSET 1.6 ; WIDTH 1.2 ; SPACING 1.2 ; RESISTANCE RPERSQ 0.04 ; CAPACITANCE CPERSQDIST 4e-06 ; END metal4 VIA M2_M1 DEFAULT LAYER metal1 ; RECT -0.400 -0.400 0.400 0.400 ; LAYER via1 ; RECT -0.200 -0.200 0.200 0.200 ; LAYER metal2 ; RECT -0.400 -0.400 0.400 0.400 ; END M2_M1 VIA M3_M2 DEFAULT LAYER metal2 ; RECT -0.400 -0.400 0.400 0.400 ; LAYER via2 ; RECT -0.200 -0.200 0.200 0.200 ; LAYER metal3 ; RECT -0.400 -0.400 0.400 0.400 ; END M3_M2 VIA M4_M3 DEFAULT LAYER metal3 ; RECT -0.400 -0.400 0.400 0.400 ; LAYER via3 ; RECT -0.200 -0.200 0.200 0.200 ; LAYER metal4 ; RECT -0.600 -0.600 0.600 0.600 ; END M4_M3 VIARULE viagen21 GENERATE LAYER metal1 ; DIRECTION HORIZONTAL ; WIDTH 0.6 TO 60 ; OVERHANG 0.2 ; METALOVERHANG 0 ; LAYER metal2 ; DIRECTION VERTICAL ; WIDTH 0.6 TO 60 ; OVERHANG 0.2 ; METALOVERHANG 0 ; LAYER via1 ; RECT -0.2 -0.2 0.2 0.2 ; SPACING 1 BY 1 ; END viagen21 VIARULE viagen32 GENERATE LAYER metal3 ; DIRECTION HORIZONTAL ; WIDTH 0.6 TO 60 ; OVERHANG 0.2 ; METALOVERHANG 0 ; LAYER metal2 ; DIRECTION VERTICAL ; WIDTH 0.6 TO 60 ; OVERHANG 0.2 ; METALOVERHANG 0 ; LAYER via2 ; RECT -0.2 -0.2 0.2 0.2 ; SPACING 1 BY 1 ; END viagen32 VIARULE viagen43 GENERATE LAYER metal3 ; DIRECTION HORIZONTAL ; WIDTH 0.6 TO 60 ; OVERHANG 0.4 ; METALOVERHANG 0 ; LAYER metal4 ; DIRECTION VERTICAL ; WIDTH 0.6 TO 60 ; OVERHANG 0.4 ; METALOVERHANG 0 ; LAYER via3 ; RECT -0.2 -0.2 0.2 0.2 ; SPACING 1.2 BY 1.2 ; END viagen43 VIARULE TURN1 GENERATE LAYER metal1 ; DIRECTION HORIZONTAL ; LAYER metal1 ; DIRECTION VERTICAL ; END TURN1 VIARULE TURN2 GENERATE LAYER metal2 ; DIRECTION HORIZONTAL ; LAYER metal2 ; DIRECTION VERTICAL ; END TURN2 VIARULE TURN3 GENERATE LAYER metal3 ; DIRECTION HORIZONTAL ; LAYER metal3 ; DIRECTION VERTICAL ; END TURN3 VIARULE TURN4 GENERATE LAYER metal4 ; DIRECTION HORIZONTAL ; LAYER metal4 ; DIRECTION VERTICAL ; END TURN4 SITE corner CLASS PAD ; SYMMETRY R90 Y ; SIZE 300.000 BY 300.000 ; END corner SITE IO CLASS PAD ; SYMMETRY Y ; SIZE 90.000 BY 300.000 ; END IO SITE core CLASS CORE ; SYMMETRY Y ; SIZE 1.600 BY 20.000 ; END core MACRO FILL CLASS CORE ; FOREIGN FILL 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 1.600 BY 20.000 ; SYMMETRY X Y ; SITE core ; PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.400 -0.600 2.000 0.600 ; END END gnd PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT -0.400 19.400 2.000 20.600 ; END END vdd END FILL MACRO AND2X1 CLASS CORE ; FOREIGN AND2X1 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 6.400 BY 20.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.400 6.600 1.200 8.200 ; END END A PIN B DIRECTION INPUT ; PORT LAYER metal1 ; RECT 2.600 9.800 3.400 11.400 ; RECT 2.000 10.600 3.400 11.400 ; END END B PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 3.000 -0.600 3.800 5.200 ; RECT -0.400 -0.600 6.800 0.600 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 5.200 12.600 6.000 13.400 ; RECT 5.200 14.800 6.000 18.800 ; RECT 5.400 3.200 6.000 18.800 ; RECT 4.600 1.200 5.400 3.800 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.400 14.800 1.200 20.600 ; RECT -0.400 19.400 6.800 20.600 ; RECT 3.600 14.800 4.400 20.600 ; END END vdd OBS LAYER metal1 ; RECT 0.400 1.200 1.200 5.200 ; RECT 0.600 5.200 2.400 5.800 ; RECT 1.800 5.200 2.400 6.600 ; RECT 4.000 5.800 4.800 6.600 ; RECT 1.800 6.000 4.800 6.600 ; RECT 4.000 5.800 4.600 14.200 ; RECT 2.200 13.600 4.600 14.200 ; RECT 2.200 13.600 2.800 18.800 ; RECT 2.000 14.800 2.800 18.800 ; END END AND2X1 MACRO AND2X2 CLASS CORE ; FOREIGN AND2X2 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 6.400 BY 20.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.400 6.600 1.200 8.200 ; END END A PIN B DIRECTION INPUT ; PORT LAYER metal1 ; RECT 2.200 7.200 2.800 9.400 ; RECT 2.400 7.000 3.200 7.800 ; RECT 2.000 8.600 2.800 9.400 ; END END B PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 3.000 -0.600 3.800 5.000 ; RECT -0.400 -0.600 6.800 0.600 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 5.200 8.600 6.000 9.400 ; RECT 5.200 10.800 6.000 18.800 ; RECT 5.400 4.200 6.000 18.800 ; RECT 4.600 1.200 5.400 5.200 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.400 14.800 1.200 20.600 ; RECT -0.400 19.400 6.800 20.600 ; RECT 3.600 11.200 4.400 20.600 ; END END vdd OBS LAYER metal1 ; RECT 0.400 1.200 1.200 5.200 ; RECT 0.600 1.200 1.200 6.000 ; RECT 0.600 5.400 2.400 6.000 ; RECT 1.800 5.800 4.800 6.400 ; RECT 4.000 5.800 4.800 6.600 ; RECT 4.000 5.800 4.600 10.600 ; RECT 2.200 10.000 4.600 10.600 ; RECT 2.200 10.000 2.800 18.800 ; RECT 2.000 14.800 2.800 18.800 ; END END AND2X2 MACRO AOI21X1 CLASS CORE ; FOREIGN AOI21X1 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 6.400 BY 20.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.400 8.600 1.200 9.400 ; RECT 1.200 8.800 2.000 9.800 ; END END A PIN B DIRECTION INPUT ; PORT LAYER metal1 ; RECT 2.000 6.600 2.800 8.200 ; END END B PIN C DIRECTION INPUT ; PORT LAYER metal1 ; RECT 5.000 3.800 5.800 4.600 ; RECT 5.200 4.600 6.000 5.400 ; END END C PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 1.000 -0.600 1.800 5.200 ; RECT -0.400 -0.600 6.800 0.600 ; RECT 5.200 -0.600 6.000 3.200 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 3.600 1.200 4.200 9.400 ; RECT 5.200 10.800 6.000 18.800 ; RECT 3.600 8.800 6.000 9.400 ; RECT 5.200 8.600 6.000 9.400 ; RECT 5.200 8.600 5.800 18.800 ; RECT 3.600 1.200 4.400 5.200 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 2.000 12.000 2.800 20.600 ; RECT -0.400 19.400 6.800 20.600 ; END END vdd OBS LAYER metal1 ; RECT 0.400 10.800 4.400 11.400 ; RECT 0.400 10.800 1.200 18.800 ; RECT 3.600 10.800 4.400 18.800 ; END END AOI21X1 MACRO AOI22X1 CLASS CORE ; FOREIGN AOI22X1 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 8.000 BY 20.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.400 8.600 1.200 9.400 ; RECT 1.200 8.800 2.000 9.800 ; END END A PIN B DIRECTION INPUT ; PORT LAYER metal1 ; RECT 2.000 6.600 2.800 8.200 ; END END B PIN C DIRECTION INPUT ; PORT LAYER metal1 ; RECT 6.800 8.600 7.600 10.200 ; END END C PIN D DIRECTION INPUT ; PORT LAYER metal1 ; RECT 5.200 6.600 5.800 8.600 ; RECT 5.200 6.600 6.000 7.400 ; RECT 5.000 7.800 5.800 8.600 ; END END D PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.800 -0.600 1.600 5.200 ; RECT -0.400 -0.600 8.400 0.600 ; RECT 6.800 -0.600 7.600 5.200 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 3.600 8.600 4.400 9.400 ; RECT 5.200 10.800 6.000 17.600 ; RECT 5.200 9.600 5.800 17.600 ; RECT 3.800 9.600 5.800 10.200 ; RECT 3.400 1.200 5.000 5.200 ; RECT 3.800 1.200 4.400 10.200 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 2.000 12.000 2.800 20.600 ; RECT -0.400 19.400 8.400 20.600 ; END END vdd OBS LAYER metal1 ; RECT 0.400 10.800 4.400 11.400 ; RECT 3.600 10.800 4.400 18.800 ; RECT 0.400 10.800 1.200 18.800 ; RECT 6.800 10.800 7.600 18.800 ; RECT 3.600 18.200 7.600 18.800 ; END END AOI22X1 MACRO BUFX2 CLASS CORE ; FOREIGN BUFX2 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 4.800 BY 20.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.400 7.800 1.200 9.400 ; END END A PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 2.000 -0.600 2.800 5.200 ; RECT -0.400 -0.600 5.200 0.600 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 3.600 1.200 4.400 8.600 ; RECT 3.600 10.800 4.400 18.800 ; RECT 3.800 1.200 4.400 18.800 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 2.000 12.000 2.800 20.600 ; RECT -0.400 19.400 5.200 20.600 ; END END vdd OBS LAYER metal1 ; RECT 0.400 1.200 1.200 6.400 ; RECT 0.400 5.800 2.600 6.400 ; RECT 2.000 9.400 3.200 10.200 ; RECT 2.000 5.800 2.600 11.400 ; RECT 0.400 10.800 2.600 11.400 ; RECT 0.400 10.800 1.200 18.800 ; END END BUFX2 MACRO BUFX4 CLASS CORE ; FOREIGN BUFX4 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 6.400 BY 20.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.600 7.800 1.400 9.400 ; RECT 0.400 8.600 1.400 9.400 ; END END A PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 2.000 -0.600 2.800 5.200 ; RECT -0.400 -0.600 6.800 0.600 ; RECT 5.200 -0.600 6.000 5.200 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 3.600 1.200 4.400 5.200 ; RECT 4.000 4.600 4.600 11.800 ; RECT 3.600 10.800 4.400 18.800 ; RECT 3.600 6.600 4.600 7.400 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 2.000 12.000 2.800 20.600 ; RECT -0.400 19.400 6.800 20.600 ; RECT 5.200 10.800 6.000 20.600 ; END END vdd OBS LAYER metal1 ; RECT 0.400 1.200 1.200 6.400 ; RECT 0.400 5.800 3.000 6.400 ; RECT 2.400 8.000 3.400 8.800 ; RECT 2.400 5.800 3.000 11.400 ; RECT 0.400 10.800 3.000 11.400 ; RECT 0.400 10.800 1.200 18.800 ; END END BUFX4 MACRO DFFNEGX1 CLASS CORE ; FOREIGN DFFNEGX1 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 19.200 BY 20.000 ; SYMMETRY X Y ; SITE core ; PIN Q DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 14.600 9.400 15.400 10.200 ; RECT 18.000 1.200 18.800 18.800 ; RECT 14.600 9.600 18.800 10.200 ; RECT 15.000 5.600 18.800 6.200 ; RECT 15.000 5.400 15.800 6.200 ; END END Q PIN CLK DIRECTION INPUT ; PORT LAYER metal2 ; RECT 5.200 6.800 6.000 13.400 ; LAYER via1 ; RECT 5.400 12.800 5.800 13.200 ; RECT 5.400 7.000 5.800 7.400 ; LAYER metal1 ; RECT 5.200 12.600 6.000 13.400 ; RECT 1.200 6.800 12.800 7.400 ; RECT 12.000 6.600 12.800 7.400 ; RECT 5.200 6.800 6.000 7.600 ; RECT 4.200 4.600 5.000 5.400 ; RECT 4.000 5.400 4.800 7.400 ; RECT 1.200 6.600 2.800 7.400 ; RECT 5.400 13.400 6.200 14.200 ; END END CLK PIN D DIRECTION INPUT ; PORT LAYER metal1 ; RECT 2.800 8.400 3.600 9.200 ; RECT 6.800 8.600 7.600 9.400 ; RECT 2.800 8.600 7.600 9.200 ; END END D PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 2.000 -0.600 2.800 5.200 ; RECT -0.400 -0.600 19.600 0.600 ; RECT 16.400 -0.600 17.200 5.000 ; RECT 10.800 -0.600 11.600 3.200 ; RECT 7.400 -0.600 8.400 3.200 ; END END gnd PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 2.000 11.000 2.800 20.600 ; RECT -0.400 19.400 19.600 20.600 ; RECT 16.400 10.800 17.200 20.600 ; RECT 10.800 14.800 11.600 20.600 ; RECT 7.600 14.800 8.400 20.600 ; END END vdd OBS LAYER metal2 ; RECT 0.400 5.200 1.200 10.800 ; RECT 3.600 3.200 4.400 10.000 ; RECT 3.600 3.200 4.200 14.800 ; RECT 3.600 10.800 4.400 14.800 ; RECT 13.200 3.200 14.000 11.400 ; RECT 13.200 3.200 13.800 14.800 ; RECT 13.200 12.200 14.000 14.800 ; LAYER metal1 ; RECT 0.400 1.200 1.200 6.000 ; RECT 3.600 14.000 4.400 15.400 ; RECT 3.600 14.800 5.600 15.400 ; RECT 4.800 14.800 5.600 18.800 ; RECT 4.800 1.200 5.600 3.200 ; RECT 3.600 2.600 5.600 3.200 ; RECT 3.600 2.600 4.400 4.000 ; RECT 3.600 11.400 9.000 12.000 ; RECT 3.600 11.400 4.400 12.200 ; RECT 8.200 11.400 9.000 12.200 ; RECT 9.200 1.200 10.000 3.200 ; RECT 9.200 1.200 9.800 4.400 ; RECT 7.000 3.800 9.800 4.400 ; RECT 7.000 3.800 7.800 4.600 ; RECT 7.000 13.400 7.800 14.200 ; RECT 9.800 13.400 10.600 14.200 ; RECT 7.000 13.600 10.600 14.200 ; RECT 9.200 13.600 9.800 18.800 ; RECT 9.200 14.800 10.000 18.800 ; RECT 13.200 14.000 14.000 14.800 ; RECT 13.400 14.800 14.600 18.800 ; RECT 0.400 9.800 5.000 10.400 ; RECT 4.200 10.200 11.400 10.800 ; RECT 10.800 10.200 11.400 12.200 ; RECT 10.800 11.400 14.600 12.000 ; RECT 10.800 11.400 11.800 12.200 ; RECT 13.800 11.400 14.600 12.200 ; RECT 0.400 9.800 1.200 18.800 ; RECT 13.400 1.200 14.600 3.200 ; RECT 13.200 2.600 14.000 4.000 ; RECT 13.200 8.000 14.000 8.800 ; RECT 13.200 8.200 17.000 8.800 ; RECT 16.200 8.200 17.000 9.000 ; LAYER via1 ; RECT 0.600 10.200 1.000 10.600 ; RECT 0.600 5.400 1.000 5.800 ; RECT 3.800 14.200 4.200 14.600 ; RECT 3.800 11.600 4.200 12.000 ; RECT 3.800 3.400 4.200 3.800 ; RECT 13.400 14.200 13.800 14.600 ; RECT 13.400 8.200 13.800 8.600 ; RECT 13.400 3.400 13.800 3.800 ; END END DFFNEGX1 MACRO NOR3X1 CLASS CORE ; FOREIGN NOR3X1 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 12.800 BY 20.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 2.000 4.600 3.800 5.400 ; END END A PIN B DIRECTION INPUT ; PORT LAYER metal1 ; RECT 3.600 6.600 5.200 7.400 ; END END B PIN C DIRECTION INPUT ; PORT LAYER metal1 ; RECT 5.200 8.600 6.800 9.400 ; END END C PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 2.000 -0.600 2.800 3.200 ; RECT -0.400 -0.600 13.200 0.600 ; RECT 5.200 -0.600 6.000 2.800 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 3.600 1.200 4.400 3.200 ; RECT 10.000 12.000 10.800 17.600 ; RECT 10.000 10.600 10.800 11.400 ; RECT 10.000 10.600 10.600 17.600 ; RECT 7.400 10.600 10.800 11.200 ; RECT 7.400 3.200 8.000 11.200 ; RECT 6.800 1.200 7.600 4.000 ; RECT 4.000 3.400 8.000 4.000 ; RECT 4.000 2.600 4.600 4.000 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 2.000 12.800 2.800 20.600 ; RECT -0.400 19.400 13.200 20.600 ; END END vdd OBS LAYER metal1 ; RECT 0.600 11.600 4.200 12.200 ; RECT 3.600 11.600 4.200 18.800 ; RECT 3.600 12.800 4.400 18.800 ; RECT 0.600 11.600 1.200 18.800 ; RECT 0.400 12.800 1.200 18.800 ; RECT 6.800 13.000 7.600 18.800 ; RECT 3.600 18.200 7.600 18.800 ; RECT 5.400 11.800 9.000 12.400 ; RECT 5.400 11.800 6.000 17.600 ; RECT 5.200 12.800 6.000 17.600 ; RECT 8.400 12.000 9.200 18.000 ; RECT 11.600 12.000 12.400 18.000 ; RECT 8.600 12.000 9.200 18.800 ; RECT 11.600 12.000 12.200 18.800 ; RECT 8.600 18.200 12.200 18.800 ; END END NOR3X1 MACRO DFFPOSX1 CLASS CORE ; FOREIGN DFFPOSX1 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 19.200 BY 20.000 ; SYMMETRY X Y ; SITE core ; PIN Q DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 14.600 9.400 15.400 10.200 ; RECT 18.000 1.200 18.800 18.800 ; RECT 14.600 9.600 18.800 10.200 ; RECT 15.000 5.600 18.800 6.200 ; RECT 15.000 5.400 15.800 6.200 ; END END Q PIN CLK DIRECTION INPUT ; PORT LAYER metal1 ; RECT 1.200 6.600 2.800 7.400 ; RECT 13.400 12.200 14.800 13.000 ; RECT 13.400 10.600 14.000 13.000 ; RECT 11.600 10.600 14.000 11.200 ; RECT 11.600 6.800 12.200 11.200 ; RECT 11.000 6.600 11.800 7.400 ; RECT 1.200 6.800 12.200 7.400 ; RECT 5.400 3.800 6.000 7.400 ; RECT 5.200 3.800 6.000 4.600 ; RECT 4.200 6.800 5.000 7.600 ; END END CLK PIN D DIRECTION INPUT ; PORT LAYER metal1 ; RECT 2.600 8.400 3.400 9.200 ; RECT 6.800 8.600 7.600 9.400 ; RECT 2.600 8.600 7.600 9.200 ; END END D PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 2.000 -0.600 2.800 5.200 ; RECT -0.400 -0.600 19.600 0.600 ; RECT 16.400 -0.600 17.200 5.000 ; RECT 10.800 -0.600 11.600 3.200 ; RECT 7.400 -0.600 8.400 3.200 ; END END gnd PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 2.000 11.000 2.800 20.600 ; RECT -0.400 19.400 19.600 20.600 ; RECT 16.400 10.800 17.200 20.600 ; RECT 10.800 14.800 11.600 20.600 ; RECT 7.600 14.800 8.400 20.600 ; END END vdd OBS LAYER metal2 ; RECT 0.400 5.200 1.200 10.800 ; RECT 3.600 3.200 4.400 14.800 ; RECT 13.200 3.200 14.000 14.800 ; LAYER metal1 ; RECT 0.400 1.200 1.200 6.000 ; RECT 3.600 14.000 4.400 15.400 ; RECT 3.600 14.800 5.600 15.400 ; RECT 4.800 14.800 5.600 18.800 ; RECT 4.800 1.200 5.600 3.200 ; RECT 3.600 2.600 5.600 3.200 ; RECT 3.600 2.600 4.400 4.000 ; RECT 3.600 11.400 9.000 12.000 ; RECT 3.600 11.400 4.400 12.200 ; RECT 8.200 11.400 9.000 12.200 ; RECT 9.200 1.200 10.000 3.200 ; RECT 9.200 1.200 9.800 4.400 ; RECT 7.000 3.800 9.800 4.400 ; RECT 7.000 3.800 7.800 4.600 ; RECT 7.000 13.400 7.800 14.200 ; RECT 9.800 13.400 10.600 14.200 ; RECT 7.000 13.600 10.600 14.200 ; RECT 9.200 13.600 9.800 18.800 ; RECT 9.200 14.800 10.000 18.800 ; RECT 0.400 10.000 6.200 10.400 ; RECT 0.400 9.800 6.000 10.400 ; RECT 5.400 10.200 10.200 10.800 ; RECT 9.600 10.200 10.200 12.600 ; RECT 11.000 11.800 11.800 12.600 ; RECT 9.600 12.000 11.800 12.600 ; RECT 0.400 9.800 1.200 18.800 ; RECT 13.200 14.000 14.000 14.800 ; RECT 13.400 14.800 14.600 18.800 ; RECT 13.400 1.200 14.600 3.200 ; RECT 13.200 2.600 14.000 4.000 ; RECT 13.200 8.000 14.000 8.800 ; RECT 13.200 8.200 17.000 8.800 ; RECT 16.200 8.200 17.000 9.000 ; LAYER via1 ; RECT 0.600 10.200 1.000 10.600 ; RECT 0.600 5.400 1.000 5.800 ; RECT 3.800 14.200 4.200 14.600 ; RECT 3.800 11.600 4.200 12.000 ; RECT 3.800 3.400 4.200 3.800 ; RECT 13.400 14.200 13.800 14.600 ; RECT 13.400 8.200 13.800 8.600 ; RECT 13.400 3.400 13.800 3.800 ; END END DFFPOSX1 MACRO FAX1 CLASS CORE ; FOREIGN FAX1 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 24.000 BY 20.000 ; SYMMETRY X Y ; SITE core ; PIN YC DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 22.800 1.200 23.600 3.200 ; RECT 22.800 14.800 23.600 18.800 ; RECT 23.000 1.200 23.600 18.800 ; RECT 22.800 6.600 23.600 7.400 ; END END YC PIN YS DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 19.600 1.200 20.400 3.200 ; RECT 20.800 4.600 22.000 5.400 ; RECT 19.400 9.200 21.400 9.800 ; RECT 20.800 3.800 21.400 9.800 ; RECT 19.800 3.800 21.400 4.400 ; RECT 19.600 14.800 20.400 18.800 ; RECT 19.800 1.200 20.400 4.400 ; RECT 19.400 9.200 20.000 15.400 ; END END YS PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.600 6.000 2.000 6.600 ; RECT 17.800 6.800 18.600 7.600 ; RECT 17.800 5.600 18.400 7.600 ; RECT 7.400 5.600 18.400 6.200 ; RECT 0.600 6.000 8.200 6.400 ; RECT 1.200 5.800 18.400 6.200 ; RECT 0.400 6.600 1.200 7.400 ; END END A PIN B DIRECTION INPUT ; PORT LAYER metal1 ; RECT 2.200 7.200 2.800 9.400 ; RECT 16.000 6.800 16.800 7.600 ; RECT 9.400 6.800 16.800 7.400 ; RECT 2.200 7.200 10.200 7.600 ; RECT 2.800 7.000 16.800 7.400 ; RECT 5.800 7.000 6.600 7.800 ; RECT 2.200 7.200 3.600 7.800 ; RECT 2.000 8.600 2.800 9.400 ; END END B PIN C DIRECTION INPUT ; PORT LAYER metal1 ; RECT 3.600 8.600 5.200 9.400 ; RECT 14.400 8.000 15.200 8.800 ; RECT 10.400 8.200 15.200 8.800 ; RECT 3.600 8.600 11.800 9.000 ; RECT 3.600 8.600 11.000 9.200 ; END END C PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 2.000 -0.600 2.800 4.000 ; RECT -0.400 -0.600 24.400 0.600 ; RECT 21.200 -0.600 22.000 3.200 ; RECT 18.000 -0.600 18.800 5.000 ; RECT 11.000 -0.600 11.800 3.800 ; RECT 7.800 -0.600 8.600 4.800 ; END END gnd PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 2.000 12.000 2.800 20.600 ; RECT -0.400 19.400 24.400 20.600 ; RECT 21.200 14.800 22.000 20.600 ; RECT 18.000 9.200 18.800 20.600 ; RECT 11.000 12.800 11.800 20.600 ; RECT 7.800 10.800 8.600 20.600 ; END END vdd OBS LAYER metal2 ; RECT 14.400 4.200 15.200 5.000 ; RECT 14.600 7.800 20.200 8.400 ; RECT 19.400 7.800 20.200 8.600 ; RECT 14.600 4.200 15.200 10.200 ; RECT 14.400 9.400 15.200 10.200 ; RECT 5.200 4.400 6.000 5.200 ; RECT 12.000 9.600 12.800 11.400 ; RECT 20.800 10.600 21.600 11.400 ; RECT 5.200 10.800 21.600 11.400 ; RECT 5.400 4.400 6.000 11.600 ; RECT 5.200 10.800 6.000 11.600 ; LAYER metal1 ; RECT 0.400 10.800 4.400 11.400 ; RECT 0.400 10.800 1.200 18.800 ; RECT 3.600 10.800 4.400 18.800 ; RECT 0.400 1.200 1.200 5.200 ; RECT 3.600 1.200 4.400 5.200 ; RECT 0.400 4.600 4.400 5.200 ; RECT 5.200 10.800 6.000 18.800 ; RECT 5.200 1.200 6.000 5.200 ; RECT 9.400 11.600 13.400 12.200 ; RECT 9.400 10.800 10.200 18.800 ; RECT 12.600 11.600 13.400 18.800 ; RECT 9.400 1.200 10.200 5.000 ; RECT 12.600 1.200 13.400 5.000 ; RECT 9.400 4.400 13.400 5.000 ; RECT 12.800 9.400 13.600 10.200 ; RECT 12.000 9.600 12.800 10.400 ; RECT 14.400 9.400 15.200 18.800 ; RECT 14.200 10.200 15.200 18.800 ; RECT 14.200 1.200 15.200 4.200 ; RECT 14.400 1.200 15.200 5.000 ; RECT 19.400 7.000 20.200 8.600 ; RECT 20.800 10.600 22.400 11.400 ; LAYER via1 ; RECT 5.400 11.000 5.800 11.400 ; RECT 5.400 4.600 5.800 5.000 ; RECT 12.200 9.800 12.600 10.200 ; RECT 14.600 9.600 15.000 10.000 ; RECT 14.600 4.400 15.000 4.800 ; RECT 19.600 8.000 20.000 8.400 ; RECT 21.000 10.800 21.400 11.200 ; END END FAX1 MACRO HAX1 CLASS CORE ; FOREIGN HAX1 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 16.000 BY 20.000 ; SYMMETRY X Y ; SITE core ; PIN YC DIRECTION OUTPUT ; PORT LAYER metal2 ; RECT 4.600 3.200 6.000 4.000 ; RECT 5.200 8.400 6.000 9.200 ; RECT 5.400 3.200 6.000 9.200 ; LAYER via1 ; RECT 4.800 3.400 5.200 3.800 ; RECT 5.400 8.600 5.800 9.000 ; LAYER metal1 ; RECT 4.600 1.200 5.400 4.000 ; RECT 5.200 8.400 6.000 18.800 ; END END YC PIN YS DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 13.200 10.600 14.000 11.400 ; RECT 14.200 14.800 15.000 18.800 ; RECT 14.400 13.600 15.000 18.800 ; RECT 13.400 4.000 15.000 4.600 ; RECT 14.400 1.200 15.000 4.600 ; RECT 13.400 13.600 15.000 14.200 ; RECT 14.200 1.200 15.000 3.200 ; RECT 13.400 4.000 14.000 14.200 ; END END YS PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.400 6.000 1.200 7.400 ; RECT 10.000 6.600 10.800 7.400 ; RECT 8.400 6.600 10.800 7.200 ; RECT 0.400 6.000 9.000 6.600 ; RECT 0.800 5.800 1.600 6.600 ; END END A PIN B DIRECTION INPUT ; PORT LAYER metal1 ; RECT 2.200 8.000 3.000 8.600 ; RECT 8.400 7.800 9.200 8.600 ; RECT 7.200 7.800 9.200 8.400 ; RECT 2.400 7.200 7.800 7.800 ; RECT 2.400 7.200 3.200 8.000 ; RECT 2.000 8.600 2.800 9.400 ; END END B PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.400 -0.600 1.200 5.200 ; RECT -0.400 -0.600 16.400 0.600 ; RECT 12.600 -0.600 13.400 3.200 ; RECT 6.200 -0.600 7.000 5.000 ; END END gnd PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 2.000 15.200 2.800 20.600 ; RECT -0.400 19.400 16.400 20.600 ; RECT 12.600 14.800 13.400 20.600 ; RECT 11.000 10.800 11.800 20.600 ; RECT 6.800 14.800 7.600 20.600 ; END END vdd OBS LAYER metal2 ; RECT 3.800 4.600 4.600 5.400 ; RECT 3.800 4.600 4.400 9.200 ; RECT 3.800 8.400 4.600 9.200 ; LAYER metal1 ; RECT 3.800 8.400 4.600 9.200 ; RECT 0.600 14.000 4.400 14.600 ; RECT 0.600 14.000 1.200 18.800 ; RECT 0.400 14.800 1.200 18.800 ; RECT 3.800 8.400 4.400 18.800 ; RECT 3.600 14.000 4.400 18.800 ; RECT 3.000 1.200 3.800 5.200 ; RECT 3.800 4.600 5.600 5.400 ; RECT 7.800 1.200 11.800 1.800 ; RECT 11.000 1.200 11.800 4.800 ; RECT 7.800 1.200 8.600 5.200 ; RECT 9.400 2.400 10.200 5.200 ; RECT 9.600 2.400 10.200 6.000 ; RECT 9.600 5.400 12.600 6.000 ; RECT 11.400 5.400 12.600 6.200 ; RECT 11.400 5.400 12.000 10.200 ; RECT 8.600 9.600 12.000 10.200 ; RECT 8.600 9.600 9.200 18.800 ; RECT 8.400 10.800 9.200 18.800 ; LAYER via1 ; RECT 4.000 8.600 4.400 9.000 ; RECT 4.000 4.800 4.400 5.200 ; END END HAX1 MACRO INVX1 CLASS CORE ; FOREIGN INVX1 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 3.200 BY 20.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.400 3.800 1.200 5.400 ; END END A PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.400 -0.600 1.200 3.200 ; RECT -0.400 -0.600 3.600 0.600 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 2.000 1.200 2.800 18.800 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.400 14.800 1.200 20.600 ; RECT -0.400 19.400 3.600 20.600 ; END END vdd END INVX1 MACRO INVX2 CLASS CORE ; FOREIGN INVX2 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 3.200 BY 20.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.400 5.800 1.200 7.400 ; END END A PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.400 -0.600 1.200 5.200 ; RECT -0.400 -0.600 3.600 0.600 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 2.000 1.200 2.800 18.800 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.400 10.800 1.200 20.600 ; RECT -0.400 19.400 3.600 20.600 ; END END vdd END INVX2 MACRO INVX4 CLASS CORE ; FOREIGN INVX4 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 4.800 BY 20.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.400 5.800 1.200 7.400 ; END END A PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.400 -0.600 1.200 5.200 ; RECT -0.400 -0.600 5.200 0.600 ; RECT 3.600 -0.600 4.400 5.200 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 2.000 1.200 2.800 18.800 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.400 10.800 1.200 20.600 ; RECT -0.400 19.400 5.200 20.600 ; RECT 3.600 10.800 4.400 20.600 ; END END vdd END INVX4 MACRO INVX8 CLASS CORE ; FOREIGN INVX8 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 8.000 BY 20.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.400 5.800 1.200 7.400 ; END END A PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.400 -0.600 1.200 5.200 ; RECT -0.400 -0.600 8.400 0.600 ; RECT 6.800 -0.600 7.600 5.200 ; RECT 3.600 -0.600 4.400 5.200 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 2.000 1.200 2.800 6.600 ; RECT 5.200 1.200 6.000 18.800 ; RECT 2.000 9.400 6.000 10.200 ; RECT 2.000 5.800 6.000 6.600 ; RECT 2.000 9.400 2.800 18.800 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.400 10.800 1.200 20.600 ; RECT -0.400 19.400 8.400 20.600 ; RECT 6.800 10.800 7.600 20.600 ; RECT 3.600 10.800 4.400 20.600 ; END END vdd END INVX8 MACRO NAND2X1 CLASS CORE ; FOREIGN NAND2X1 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 4.800 BY 20.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.400 5.800 1.200 7.400 ; END END A PIN B DIRECTION INPUT ; PORT LAYER metal1 ; RECT 3.600 10.600 4.400 12.200 ; END END B PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.400 -0.600 1.200 5.200 ; RECT -0.400 -0.600 5.200 0.600 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 2.000 4.600 2.800 18.800 ; RECT 2.000 4.600 3.800 5.200 ; RECT 3.000 1.200 3.800 5.200 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.400 14.800 1.200 20.600 ; RECT -0.400 19.400 5.200 20.600 ; RECT 3.600 14.800 4.400 20.600 ; END END vdd END NAND2X1 MACRO NAND3X1 CLASS CORE ; FOREIGN NAND3X1 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 6.400 BY 20.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.400 9.800 1.200 11.400 ; END END A PIN B DIRECTION INPUT ; PORT LAYER metal1 ; RECT 2.000 8.600 3.600 9.400 ; END END B PIN C DIRECTION INPUT ; PORT LAYER metal1 ; RECT 3.600 11.800 4.400 13.400 ; END END C PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.400 -0.600 1.200 7.200 ; RECT -0.400 -0.600 6.800 0.600 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 2.200 14.000 2.800 18.800 ; RECT 5.200 14.800 6.000 18.800 ; RECT 5.200 10.600 6.000 11.400 ; RECT 5.200 6.800 5.800 18.800 ; RECT 2.200 14.000 5.800 14.600 ; RECT 4.200 6.800 5.800 7.400 ; RECT 4.000 1.200 4.800 7.200 ; RECT 2.000 14.800 2.800 18.800 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.400 14.800 1.200 20.600 ; RECT -0.400 19.400 6.800 20.600 ; RECT 3.600 15.200 4.400 20.600 ; END END vdd END NAND3X1 MACRO NOR2X1 CLASS CORE ; FOREIGN NOR2X1 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 4.800 BY 20.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.400 3.800 1.200 5.400 ; END END A PIN B DIRECTION INPUT ; PORT LAYER metal1 ; RECT 3.600 8.600 4.400 10.200 ; END END B PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.400 -0.600 1.200 3.200 ; RECT -0.400 -0.600 5.200 0.600 ; RECT 3.600 -0.600 4.400 3.200 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 2.000 1.200 2.800 3.200 ; RECT 3.000 10.800 3.800 18.800 ; RECT 2.000 10.800 3.800 11.600 ; RECT 2.200 1.200 2.800 11.600 ; RECT 2.000 6.600 2.800 7.400 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.400 10.800 1.200 20.600 ; RECT -0.400 19.400 5.200 20.600 ; END END vdd END NOR2X1 MACRO OAI21X1 CLASS CORE ; FOREIGN OAI21X1 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 6.400 BY 20.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.400 6.600 1.200 7.400 ; RECT 1.200 6.200 2.000 7.200 ; END END A PIN B DIRECTION INPUT ; PORT LAYER metal1 ; RECT 2.000 7.800 2.800 9.400 ; END END B PIN C DIRECTION INPUT ; PORT LAYER metal1 ; RECT 4.600 10.800 5.200 13.400 ; RECT 5.200 10.600 6.000 11.400 ; RECT 4.400 12.600 5.200 13.400 ; END END C PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 2.000 -0.600 2.800 4.400 ; RECT -0.400 -0.600 6.800 0.600 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 3.000 10.800 3.800 18.800 ; RECT 3.400 6.600 6.000 7.400 ; RECT 5.200 1.200 6.000 5.200 ; RECT 5.200 1.200 5.800 7.400 ; RECT 3.400 6.600 4.000 11.400 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.400 10.800 1.200 20.600 ; RECT -0.400 19.400 6.800 20.600 ; RECT 4.600 14.800 5.400 20.600 ; END END vdd OBS LAYER metal1 ; RECT 0.400 1.200 1.200 5.200 ; RECT 3.600 1.200 4.400 5.200 ; RECT 0.600 5.000 4.200 5.600 ; END END OAI21X1 MACRO OAI22X1 CLASS CORE ; FOREIGN OAI22X1 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 8.000 BY 20.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.400 6.600 1.200 7.400 ; RECT 1.200 6.200 2.000 7.200 ; END END A PIN B DIRECTION INPUT ; PORT LAYER metal1 ; RECT 2.000 7.800 2.800 9.400 ; END END B PIN C DIRECTION INPUT ; PORT LAYER metal1 ; RECT 6.800 6.600 7.600 8.200 ; END END C PIN D DIRECTION INPUT ; PORT LAYER metal1 ; RECT 5.200 7.800 6.000 9.400 ; END END D PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 2.000 -0.600 2.800 4.400 ; RECT -0.400 -0.600 8.400 0.600 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 3.600 6.600 4.200 18.800 ; RECT 3.600 6.600 6.000 7.200 ; RECT 5.400 2.400 6.000 7.200 ; RECT 5.200 2.400 6.000 5.200 ; RECT 3.000 10.800 5.000 18.800 ; RECT 3.600 6.600 4.400 7.400 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.400 10.800 1.200 20.600 ; RECT -0.400 19.400 8.400 20.600 ; RECT 6.800 10.800 7.600 20.600 ; END END vdd OBS LAYER metal1 ; RECT 3.600 1.200 7.600 1.800 ; RECT 0.400 1.200 1.200 5.200 ; RECT 3.600 1.200 4.400 5.200 ; RECT 6.800 1.200 7.600 5.200 ; RECT 0.600 5.000 4.200 5.600 ; END END OAI22X1 MACRO OR2X1 CLASS CORE ; FOREIGN OR2X1 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 6.400 BY 20.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.400 3.800 1.200 5.400 ; END END A PIN B DIRECTION INPUT ; PORT LAYER metal1 ; RECT 2.000 6.600 2.800 7.400 ; RECT 2.200 5.800 3.600 6.600 ; END END B PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.400 -0.600 1.200 3.200 ; RECT -0.400 -0.600 6.800 0.600 ; RECT 3.600 -0.600 4.400 3.200 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 5.200 1.200 6.000 3.200 ; RECT 5.400 1.200 6.000 14.800 ; RECT 4.600 14.800 5.400 18.800 ; RECT 4.800 14.200 6.000 14.800 ; RECT 5.200 8.600 6.000 9.400 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 3.000 10.800 3.800 20.600 ; RECT -0.400 19.400 6.800 20.600 ; END END vdd OBS LAYER metal1 ; RECT 2.000 1.200 2.800 3.200 ; RECT 2.200 1.200 2.800 4.800 ; RECT 2.200 4.200 4.800 4.800 ; RECT 4.200 4.200 4.800 7.800 ; RECT 3.800 7.200 4.400 10.200 ; RECT 3.800 9.400 4.600 10.200 ; RECT 0.400 9.600 4.600 10.200 ; RECT 0.400 9.600 1.200 18.800 ; END END OR2X1 MACRO OR2X2 CLASS CORE ; FOREIGN OR2X2 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 6.400 BY 20.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.400 3.800 1.200 5.400 ; END END A PIN B DIRECTION INPUT ; PORT LAYER metal1 ; RECT 2.000 6.600 3.000 7.400 ; RECT 2.400 7.400 3.200 8.200 ; END END B PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.400 -0.600 1.200 3.200 ; RECT -0.400 -0.600 6.800 0.600 ; RECT 3.600 -0.600 4.400 4.800 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 5.200 1.200 6.000 5.200 ; RECT 5.400 1.200 6.000 11.400 ; RECT 4.600 10.800 5.400 18.800 ; RECT 5.200 8.600 6.000 9.400 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 3.000 10.800 3.800 20.600 ; RECT -0.400 19.400 6.800 20.600 ; END END vdd OBS LAYER metal1 ; RECT 2.000 1.200 2.800 3.200 ; RECT 2.200 1.200 2.800 6.000 ; RECT 2.200 5.400 4.600 6.000 ; RECT 3.800 9.000 4.600 9.800 ; RECT 4.000 5.400 4.600 9.800 ; RECT 0.400 9.600 4.400 10.200 ; RECT 0.400 9.600 1.200 18.800 ; END END OR2X2 MACRO TBUFX1 CLASS CORE ; FOREIGN TBUFX1 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 8.000 BY 20.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 6.000 6.600 7.600 7.400 ; END END A PIN EN DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.400 12.600 2.000 13.400 ; END END EN PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.400 -0.600 1.200 3.200 ; RECT -0.400 -0.600 8.400 0.600 ; RECT 6.400 -0.600 7.200 5.200 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 3.800 1.200 4.600 5.200 ; RECT 3.800 10.800 4.600 18.800 ; RECT 4.000 1.200 4.600 18.800 ; RECT 3.600 8.600 4.600 9.400 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.400 14.800 1.200 20.600 ; RECT -0.400 19.400 8.400 20.600 ; RECT 6.400 10.800 7.200 20.600 ; END END vdd OBS LAYER metal1 ; RECT 2.000 1.200 2.800 3.200 ; RECT 2.600 6.600 3.400 7.400 ; RECT 2.600 2.400 3.200 8.000 ; RECT 2.400 7.400 3.000 10.600 ; RECT 2.600 10.000 3.200 15.400 ; RECT 2.000 14.800 2.800 18.800 ; END END TBUFX1 MACRO TBUFX2 CLASS CORE ; FOREIGN TBUFX2 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 11.200 BY 20.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 9.000 6.600 10.800 7.400 ; END END A PIN EN DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.400 5.800 1.000 10.200 ; RECT 0.400 5.800 1.400 6.600 ; RECT 0.400 8.600 1.200 10.200 ; END END EN PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.400 -0.600 1.200 5.200 ; RECT -0.400 -0.600 11.600 0.600 ; RECT 8.400 -0.600 9.200 4.600 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 5.200 2.400 5.800 17.600 ; RECT 5.200 10.800 6.000 17.600 ; RECT 5.200 8.600 6.000 9.400 ; RECT 5.200 2.400 6.000 5.200 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.400 10.800 1.200 20.600 ; RECT -0.400 19.400 11.600 20.600 ; RECT 8.400 12.200 9.200 20.600 ; END END vdd OBS LAYER metal1 ; RECT 2.000 1.200 2.800 5.200 ; RECT 2.000 8.200 2.800 9.000 ; RECT 2.000 1.200 2.600 18.800 ; RECT 2.000 10.800 2.800 18.800 ; RECT 6.800 10.800 10.800 11.600 ; RECT 3.600 10.800 4.400 18.800 ; RECT 6.800 10.800 7.600 18.800 ; RECT 3.600 18.200 7.600 18.800 ; RECT 10.000 10.800 10.800 18.800 ; RECT 3.600 1.200 7.600 1.800 ; RECT 10.000 1.200 10.800 4.600 ; RECT 6.800 1.200 7.600 5.800 ; RECT 3.600 1.200 4.400 5.200 ; RECT 10.200 1.200 10.800 5.800 ; RECT 6.800 5.200 10.800 5.800 ; END END TBUFX2 MACRO XOR2X1 CLASS CORE ; FOREIGN XOR2X1 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 11.200 BY 20.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.400 6.600 2.000 7.400 ; RECT 4.000 7.000 4.800 7.800 ; RECT 2.000 7.000 4.800 7.600 ; RECT 0.400 6.800 2.600 7.400 ; END END A PIN B DIRECTION INPUT ; PORT LAYER metal1 ; RECT 9.200 6.600 10.800 7.400 ; END END B PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 2.200 -0.600 3.000 4.600 ; RECT -0.400 -0.600 11.600 0.600 ; RECT 8.200 -0.600 9.200 4.600 ; RECT 2.000 1.200 3.000 4.600 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 5.200 8.600 6.000 9.400 ; RECT 4.800 10.800 6.400 18.800 ; RECT 5.800 1.200 6.400 7.400 ; RECT 5.400 6.800 6.000 18.800 ; RECT 4.800 1.200 6.400 4.800 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 2.000 12.200 3.000 18.800 ; RECT -0.400 19.400 11.600 20.600 ; RECT 8.200 12.200 9.200 20.600 ; RECT 2.200 12.200 3.000 20.600 ; END END vdd OBS LAYER metal2 ; RECT 2.200 5.200 3.000 6.000 ; RECT 2.200 5.400 7.800 6.000 ; RECT 3.600 5.400 4.400 6.200 ; RECT 7.000 5.400 7.800 6.200 ; RECT 2.200 5.200 2.800 11.600 ; RECT 2.200 10.800 3.000 11.600 ; RECT 8.400 5.200 9.200 6.000 ; RECT 3.600 6.800 9.200 7.400 ; RECT 3.600 6.800 4.200 9.600 ; RECT 3.400 8.800 4.200 9.600 ; RECT 8.600 5.200 9.200 11.600 ; RECT 8.400 10.800 9.200 11.600 ; LAYER metal1 ; RECT 0.400 10.800 3.000 11.400 ; RECT 2.200 10.800 3.000 11.600 ; RECT 0.400 10.800 1.200 18.800 ; RECT 0.400 1.200 1.200 5.800 ; RECT 0.400 5.200 3.000 5.800 ; RECT 2.200 5.200 3.000 6.000 ; RECT 2.600 8.600 3.400 9.400 ; RECT 3.400 8.800 4.200 9.600 ; RECT 3.600 5.400 5.200 6.200 ; RECT 7.000 5.400 7.800 6.200 ; RECT 7.200 5.400 7.800 7.400 ; RECT 7.200 6.600 8.000 7.400 ; RECT 8.400 10.800 10.800 11.400 ; RECT 8.400 10.800 9.200 11.600 ; RECT 10.000 10.800 10.800 18.800 ; RECT 10.000 1.200 10.800 5.800 ; RECT 8.400 5.200 10.800 5.800 ; RECT 8.400 5.200 9.200 6.000 ; LAYER via1 ; RECT 2.400 11.000 2.800 11.400 ; RECT 2.400 5.400 2.800 5.800 ; RECT 3.600 9.000 4.000 9.400 ; RECT 3.800 5.600 4.200 6.000 ; RECT 7.200 5.600 7.600 6.000 ; RECT 8.600 11.000 9.000 11.400 ; RECT 8.600 5.400 9.000 5.800 ; END END XOR2X1 MACRO MUX2X1 CLASS CORE ; FOREIGN MUX2X1 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 9.600 BY 20.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 6.800 8.600 7.600 10.200 ; END END A PIN B DIRECTION INPUT ; PORT LAYER metal1 ; RECT 2.000 7.800 2.800 9.400 ; END END B PIN S DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.400 7.800 1.200 9.400 ; END END S PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 2.000 -0.600 2.800 5.600 ; RECT -0.400 -0.600 10.000 0.600 ; RECT 7.200 -0.600 8.000 6.000 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 4.600 2.000 5.400 5.600 ; RECT 5.600 6.600 7.600 7.400 ; RECT 4.600 11.200 6.200 11.800 ; RECT 5.600 5.000 6.200 11.800 ; RECT 5.400 5.000 6.200 6.000 ; RECT 4.600 11.200 5.400 18.800 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 2.000 11.200 2.800 20.600 ; RECT -0.400 19.400 10.000 20.600 ; RECT 7.200 10.800 8.000 20.600 ; END END vdd OBS LAYER metal1 ; RECT 0.400 2.000 1.200 4.000 ; RECT 0.400 2.000 1.000 6.800 ; RECT 0.400 6.200 4.600 6.800 ; RECT 3.600 6.200 4.600 8.000 ; RECT 3.600 7.200 5.000 8.000 ; RECT 3.600 6.200 4.200 10.600 ; RECT 0.400 10.000 4.200 10.600 ; RECT 0.400 10.000 1.000 18.000 ; RECT 0.400 14.000 1.200 18.000 ; END END MUX2X1 MACRO XNOR2X1 CLASS CORE ; FOREIGN XNOR2X1 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 11.200 BY 20.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal2 ; RECT 3.600 5.400 4.400 6.200 ; RECT 7.000 5.400 7.800 6.200 ; RECT 3.600 5.400 7.800 6.000 ; LAYER via1 ; RECT 3.800 5.600 4.200 6.000 ; RECT 7.200 5.600 7.600 6.000 ; LAYER metal1 ; RECT 0.400 6.600 2.000 7.400 ; RECT 7.200 6.600 8.000 7.400 ; RECT 7.200 5.400 7.800 7.400 ; RECT 7.000 5.400 7.800 6.200 ; RECT 3.600 5.400 5.200 6.200 ; RECT 0.400 6.600 3.800 7.200 ; RECT 3.200 5.600 3.800 7.200 ; END END A PIN B DIRECTION INPUT ; PORT LAYER metal1 ; RECT 9.200 6.600 10.800 7.400 ; END END B PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 2.200 -0.600 3.000 4.600 ; RECT -0.400 -0.600 11.600 0.600 ; RECT 8.200 -0.600 9.200 4.600 ; RECT 2.000 1.200 3.000 4.600 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 4.800 1.200 6.400 4.800 ; RECT 6.200 8.600 7.600 9.400 ; RECT 6.200 8.200 6.800 11.400 ; RECT 4.800 10.800 6.400 18.800 ; RECT 5.800 1.200 6.400 8.800 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 2.000 12.200 3.000 18.800 ; RECT -0.400 19.400 11.600 20.600 ; RECT 8.200 12.200 9.200 20.600 ; RECT 2.200 12.200 3.000 20.600 ; END END vdd OBS LAYER metal2 ; RECT 1.800 5.200 2.600 6.000 ; RECT 1.800 5.200 2.400 11.600 ; RECT 1.800 10.800 2.600 11.600 ; RECT 8.400 5.200 9.200 6.000 ; RECT 4.400 6.800 9.200 7.400 ; RECT 4.400 6.800 5.200 7.600 ; RECT 8.600 5.200 9.200 11.600 ; RECT 8.400 10.800 9.200 11.600 ; LAYER metal1 ; RECT 0.400 1.200 1.200 5.800 ; RECT 0.400 5.200 2.600 5.800 ; RECT 1.800 5.200 2.600 6.000 ; RECT 4.400 6.800 5.200 7.600 ; RECT 4.400 6.800 5.000 8.800 ; RECT 2.400 8.200 5.000 8.800 ; RECT 2.400 8.200 3.200 9.000 ; RECT 4.600 9.400 5.400 10.200 ; RECT 2.000 9.600 5.400 10.200 ; RECT 0.400 10.800 2.600 11.400 ; RECT 2.000 9.600 2.600 11.600 ; RECT 1.800 10.800 2.600 11.600 ; RECT 0.400 10.800 1.200 18.800 ; RECT 8.400 10.800 10.800 11.400 ; RECT 8.400 10.800 9.200 11.600 ; RECT 10.000 10.800 10.800 18.800 ; RECT 10.000 1.200 10.800 5.800 ; RECT 8.400 5.200 10.800 5.800 ; RECT 8.400 5.200 9.200 6.000 ; LAYER via1 ; RECT 2.000 11.000 2.400 11.400 ; RECT 2.000 5.400 2.400 5.800 ; RECT 4.600 7.000 5.000 7.400 ; RECT 8.600 11.000 9.000 11.400 ; RECT 8.600 5.400 9.000 5.800 ; END END XNOR2X1 MACRO LATCH CLASS CORE ; FOREIGN LATCH 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 11.200 BY 20.000 ; SYMMETRY X Y ; SITE core ; PIN Q DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 7.400 7.600 10.800 8.400 ; RECT 10.000 1.200 10.800 18.800 ; END END Q PIN CLK DIRECTION INPUT ; PORT LAYER metal1 ; RECT 1.200 6.600 2.800 7.400 ; RECT 5.800 6.600 6.600 8.200 ; RECT 1.200 6.600 6.600 7.200 ; RECT 4.400 4.600 5.200 7.200 ; END END CLK PIN D DIRECTION INPUT ; PORT LAYER metal1 ; RECT 2.600 9.400 4.400 10.200 ; RECT 3.600 9.400 4.400 11.400 ; END END D PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 2.000 -0.600 2.800 5.200 ; RECT -0.400 -0.600 11.600 0.600 ; RECT 8.400 -0.600 9.200 5.200 ; END END gnd PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 2.000 10.800 2.800 20.600 ; RECT -0.400 19.400 11.600 20.600 ; RECT 8.400 10.800 9.200 20.600 ; END END vdd OBS LAYER metal2 ; RECT 0.400 5.200 1.200 10.800 ; RECT 5.200 3.200 6.000 14.800 ; LAYER metal1 ; RECT 0.400 9.800 1.200 18.800 ; RECT 0.400 1.200 1.200 6.000 ; RECT 0.400 8.000 5.000 8.600 ; RECT 0.400 8.000 1.200 8.800 ; RECT 4.200 8.000 5.000 8.800 ; RECT 5.200 14.000 6.000 18.800 ; RECT 5.000 14.800 6.200 18.800 ; RECT 5.000 1.200 6.200 3.200 ; RECT 5.200 1.200 6.000 4.000 ; RECT 5.200 9.400 9.400 10.200 ; LAYER via1 ; RECT 0.600 10.200 1.000 10.600 ; RECT 0.600 8.200 1.000 8.600 ; RECT 0.600 5.400 1.000 5.800 ; RECT 5.400 14.200 5.800 14.600 ; RECT 5.400 9.600 5.800 10.000 ; RECT 5.400 3.400 5.800 3.800 ; END END LATCH MACRO DFFSR CLASS CORE ; FOREIGN DFFSR 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 35.200 BY 20.000 ; SYMMETRY X Y ; SITE core ; PIN Q DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 32.400 1.200 33.200 5.800 ; RECT 32.600 5.000 33.400 11.000 ; RECT 32.400 10.200 33.200 18.800 ; END END Q PIN CLK DIRECTION INPUT ; PORT LAYER metal1 ; RECT 16.400 4.600 18.000 5.400 ; END END CLK PIN R DIRECTION INPUT ; PORT LAYER metal1 ; RECT 1.800 8.800 2.600 9.600 ; RECT 1.800 9.000 25.200 9.600 ; RECT 24.400 8.400 25.200 9.600 ; RECT 6.800 8.600 7.600 9.600 ; END END R PIN S DIRECTION INPUT ; PORT LAYER metal1 ; RECT 3.600 10.200 4.400 11.400 ; RECT 3.600 10.200 30.600 10.800 ; RECT 29.800 10.000 30.600 10.800 ; RECT 7.000 10.200 7.800 11.000 ; END END S PIN D DIRECTION INPUT ; PORT LAYER metal1 ; RECT 13.200 5.800 14.000 7.400 ; END END D PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 3.600 -0.600 4.400 5.200 ; RECT -0.400 -0.600 35.600 0.600 ; RECT 34.000 -0.600 34.800 3.200 ; RECT 27.600 -0.600 28.400 5.200 ; RECT 16.400 -0.600 17.200 3.200 ; RECT 13.200 -0.600 14.000 3.200 ; END END gnd PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.400 14.800 1.200 20.600 ; RECT -0.400 19.400 35.600 20.600 ; RECT 34.000 14.800 34.800 20.600 ; RECT 30.800 14.800 31.600 20.600 ; RECT 27.600 14.800 28.400 20.600 ; RECT 24.400 14.800 25.200 20.600 ; RECT 16.400 14.800 17.200 20.600 ; RECT 13.200 14.800 14.000 20.600 ; RECT 6.800 14.800 7.600 20.600 ; RECT 3.600 14.800 4.400 20.600 ; END END vdd OBS LAYER metal2 ; RECT 8.400 3.200 9.200 16.800 ; RECT 10.000 3.200 10.800 16.800 ; RECT 11.600 3.200 12.400 14.800 ; RECT 14.800 3.200 15.600 14.800 ; RECT 18.000 3.200 18.800 14.800 ; RECT 19.600 3.200 20.400 16.800 ; RECT 21.200 3.200 22.000 16.800 ; RECT 22.800 3.200 23.600 16.800 ; LAYER metal1 ; RECT 6.800 1.200 7.600 5.200 ; RECT 5.000 4.400 7.600 5.200 ; RECT 5.000 4.400 5.800 6.600 ; RECT 2.800 5.800 5.800 6.600 ; RECT 8.400 16.000 9.200 18.800 ; RECT 0.400 7.200 9.200 8.000 ; RECT 0.400 1.200 1.200 14.200 ; RECT 0.400 13.600 2.400 14.200 ; RECT 1.800 13.600 2.400 15.400 ; RECT 2.000 14.800 2.800 18.800 ; RECT 8.400 1.200 9.200 4.000 ; RECT 10.000 16.000 10.800 18.800 ; RECT 5.400 11.600 10.800 12.200 ; RECT 10.000 11.400 10.800 12.200 ; RECT 4.600 12.000 6.000 12.800 ; RECT 10.000 1.200 10.800 4.000 ; RECT 11.600 14.000 12.400 18.800 ; RECT 11.600 1.200 12.400 4.000 ; RECT 14.800 14.000 15.600 18.800 ; RECT 13.000 12.600 15.600 13.400 ; RECT 11.000 4.600 15.600 5.200 ; RECT 14.800 4.600 15.600 5.400 ; RECT 11.000 4.600 11.800 8.400 ; RECT 9.800 7.600 11.800 8.400 ; RECT 14.800 1.200 15.600 4.000 ; RECT 18.000 12.600 18.800 18.800 ; RECT 15.600 7.600 18.800 8.400 ; RECT 18.000 1.200 18.800 4.000 ; RECT 14.800 6.000 15.600 6.800 ; RECT 14.800 6.200 19.200 6.800 ; RECT 18.400 6.200 19.200 7.000 ; RECT 19.600 16.000 20.400 18.800 ; RECT 11.800 11.400 20.400 12.000 ; RECT 19.600 11.400 20.400 12.200 ; RECT 2.000 12.200 3.600 13.000 ; RECT 3.000 12.200 3.600 14.200 ; RECT 6.600 12.800 12.400 13.400 ; RECT 11.800 11.400 12.400 13.400 ; RECT 3.000 13.400 7.200 14.200 ; RECT 5.200 13.400 6.000 18.800 ; RECT 19.600 1.200 20.400 4.000 ; RECT 21.200 16.000 22.000 18.800 ; RECT 21.000 4.600 22.000 5.400 ; RECT 21.200 4.600 22.000 8.200 ; RECT 21.200 1.200 22.000 4.000 ; RECT 22.800 16.000 23.600 18.800 ; RECT 22.800 1.200 23.600 4.000 ; RECT 21.200 13.400 25.400 14.200 ; RECT 26.000 12.600 28.600 13.400 ; RECT 26.000 12.600 26.800 18.800 ; RECT 24.400 1.200 25.200 5.200 ; RECT 24.400 4.400 26.800 5.200 ; RECT 26.000 4.400 26.800 6.400 ; RECT 26.000 5.800 27.800 6.400 ; RECT 27.000 5.800 27.800 8.400 ; RECT 27.000 7.600 30.800 8.400 ; RECT 30.800 1.200 31.600 7.000 ; RECT 31.400 6.400 32.000 9.600 ; RECT 22.800 11.400 31.800 12.000 ; RECT 22.800 11.400 23.600 12.200 ; RECT 31.200 9.000 31.800 14.200 ; RECT 29.200 13.600 31.800 14.200 ; RECT 29.200 13.600 30.000 18.800 ; LAYER via1 ; RECT 8.600 16.200 9.000 16.600 ; RECT 8.600 7.400 9.000 7.800 ; RECT 8.600 3.400 9.000 3.800 ; RECT 10.200 16.200 10.600 16.600 ; RECT 10.200 11.600 10.600 12.000 ; RECT 10.200 3.400 10.600 3.800 ; RECT 11.800 14.200 12.200 14.600 ; RECT 11.800 3.400 12.200 3.800 ; RECT 15.000 14.200 15.400 14.600 ; RECT 15.000 12.800 15.400 13.200 ; RECT 15.000 6.200 15.400 6.600 ; RECT 15.000 3.400 15.400 3.800 ; RECT 18.200 14.200 18.600 14.600 ; RECT 18.200 7.800 18.600 8.200 ; RECT 18.200 3.400 18.600 3.800 ; RECT 19.800 16.200 20.200 16.600 ; RECT 19.800 11.600 20.200 12.000 ; RECT 19.800 3.400 20.200 3.800 ; RECT 21.400 16.200 21.800 16.600 ; RECT 21.400 13.600 21.800 14.000 ; RECT 21.400 3.400 21.800 3.800 ; RECT 23.000 16.200 23.400 16.600 ; RECT 23.000 11.600 23.400 12.000 ; RECT 23.000 3.400 23.400 3.800 ; END END DFFSR MACRO CLKBUF1 CLASS CORE ; FOREIGN CLKBUF1 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 14.400 BY 20.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.400 6.600 1.200 8.000 ; RECT 0.400 7.200 2.200 8.000 ; END END A PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.400 -0.600 1.200 5.200 ; RECT -0.400 -0.600 14.800 0.600 ; RECT 13.200 -0.600 14.000 5.200 ; RECT 10.000 -0.600 10.800 5.200 ; RECT 6.800 -0.600 7.600 5.200 ; RECT 3.600 -0.600 4.400 5.200 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 11.600 1.200 12.400 6.600 ; RECT 11.600 9.400 14.000 10.200 ; RECT 13.200 5.800 14.000 10.200 ; RECT 11.600 5.800 14.000 6.600 ; RECT 11.600 9.400 12.400 18.800 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.400 10.800 1.200 20.600 ; RECT -0.400 19.400 14.800 20.600 ; RECT 13.200 10.800 14.000 20.600 ; RECT 10.000 10.800 10.800 20.600 ; RECT 6.800 10.800 7.600 20.600 ; RECT 3.600 10.800 4.400 20.600 ; END END vdd OBS LAYER metal1 ; RECT 2.000 1.200 2.800 6.600 ; RECT 2.000 5.800 3.800 6.600 ; RECT 3.000 7.200 5.600 8.000 ; RECT 3.000 5.800 3.800 10.200 ; RECT 2.000 9.400 3.800 10.200 ; RECT 2.000 9.400 2.800 18.800 ; RECT 5.200 1.200 6.000 6.600 ; RECT 5.200 5.800 7.400 6.600 ; RECT 6.600 7.200 9.000 8.000 ; RECT 6.600 5.800 7.400 10.200 ; RECT 5.200 9.400 7.400 10.200 ; RECT 5.200 9.400 6.000 18.800 ; RECT 8.400 1.200 9.200 6.600 ; RECT 8.400 5.800 10.600 6.600 ; RECT 9.800 7.200 12.400 8.000 ; RECT 9.800 5.800 10.600 10.200 ; RECT 8.400 9.400 10.600 10.200 ; RECT 8.400 9.400 9.200 18.800 ; END END CLKBUF1 MACRO CLKBUF2 CLASS CORE ; FOREIGN CLKBUF2 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 20.800 BY 20.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.400 6.600 1.200 8.000 ; RECT 0.400 7.200 2.200 8.000 ; END END A PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.400 -0.600 1.200 5.200 ; RECT -0.400 -0.600 21.200 0.600 ; RECT 19.600 -0.600 20.400 5.200 ; RECT 16.400 -0.600 17.200 5.200 ; RECT 13.200 -0.600 14.000 5.200 ; RECT 10.000 -0.600 10.800 5.200 ; RECT 6.800 -0.600 7.600 5.200 ; RECT 3.600 -0.600 4.400 5.200 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 18.000 1.200 18.800 6.600 ; RECT 18.000 9.400 20.400 10.200 ; RECT 19.600 5.800 20.400 10.200 ; RECT 18.000 5.800 20.400 6.600 ; RECT 18.000 9.400 18.800 18.800 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.400 10.800 1.200 20.600 ; RECT -0.400 19.400 21.200 20.600 ; RECT 19.600 10.800 20.400 20.600 ; RECT 16.400 10.800 17.200 20.600 ; RECT 13.200 10.800 14.000 20.600 ; RECT 10.000 10.800 10.800 20.600 ; RECT 6.800 10.800 7.600 20.600 ; RECT 3.600 10.800 4.400 20.600 ; END END vdd OBS LAYER metal1 ; RECT 2.000 1.200 2.800 6.600 ; RECT 2.000 5.800 3.800 6.600 ; RECT 3.000 7.200 5.600 8.000 ; RECT 3.000 5.800 3.800 10.200 ; RECT 2.000 9.400 3.800 10.200 ; RECT 2.000 9.400 2.800 18.800 ; RECT 5.200 1.200 6.000 6.600 ; RECT 5.200 5.800 7.400 6.600 ; RECT 6.600 7.200 9.000 8.000 ; RECT 6.600 5.800 7.400 10.200 ; RECT 5.200 9.400 7.400 10.200 ; RECT 5.200 9.400 6.000 18.800 ; RECT 8.400 1.200 9.200 6.600 ; RECT 8.400 5.800 10.600 6.600 ; RECT 9.800 7.200 12.400 8.000 ; RECT 9.800 5.800 10.600 10.200 ; RECT 8.400 9.400 10.600 10.200 ; RECT 8.400 9.400 9.200 18.800 ; RECT 11.600 1.200 12.400 6.600 ; RECT 11.600 5.800 14.000 6.600 ; RECT 13.200 7.200 15.000 8.000 ; RECT 13.200 5.800 14.000 10.200 ; RECT 11.600 9.400 14.000 10.200 ; RECT 11.600 9.400 12.400 18.800 ; RECT 14.800 1.200 15.600 6.600 ; RECT 14.800 5.800 16.600 6.600 ; RECT 15.800 7.200 18.400 8.000 ; RECT 15.800 5.800 16.600 10.200 ; RECT 14.800 9.400 16.600 10.200 ; RECT 14.800 9.400 15.600 18.800 ; END END CLKBUF2 MACRO CLKBUF3 CLASS CORE ; FOREIGN CLKBUF3 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 27.200 BY 20.000 ; SYMMETRY X Y ; SITE core ; PIN A DIRECTION INPUT ; PORT LAYER metal1 ; RECT 0.400 6.600 1.200 8.000 ; RECT 0.400 7.200 2.200 8.000 ; END END A PIN gnd DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.400 -0.600 1.200 5.200 ; RECT -0.400 -0.600 27.600 0.600 ; RECT 26.000 -0.600 26.800 5.200 ; RECT 22.800 -0.600 23.600 5.200 ; RECT 19.600 -0.600 20.400 5.200 ; RECT 16.400 -0.600 17.200 5.200 ; RECT 13.200 -0.600 14.000 5.200 ; RECT 10.000 -0.600 10.800 5.200 ; RECT 6.800 -0.600 7.600 5.200 ; RECT 3.600 -0.600 4.400 5.200 ; END END gnd PIN Y DIRECTION OUTPUT ; PORT LAYER metal1 ; RECT 24.400 1.200 25.200 6.600 ; RECT 24.400 9.400 26.800 10.200 ; RECT 26.000 5.800 26.800 10.200 ; RECT 24.400 5.800 26.800 6.600 ; RECT 24.400 9.400 25.200 18.800 ; END END Y PIN vdd DIRECTION INOUT ; USE POWER ; SHAPE ABUTMENT ; PORT LAYER metal1 ; RECT 0.400 10.800 1.200 20.600 ; RECT -0.400 19.400 27.600 20.600 ; RECT 26.000 10.800 26.800 20.600 ; RECT 22.800 10.800 23.600 20.600 ; RECT 19.600 10.800 20.400 20.600 ; RECT 16.400 10.800 17.200 20.600 ; RECT 13.200 10.800 14.000 20.600 ; RECT 10.000 10.800 10.800 20.600 ; RECT 6.800 10.800 7.600 20.600 ; RECT 3.600 10.800 4.400 20.600 ; END END vdd OBS LAYER metal1 ; RECT 2.000 1.200 2.800 6.600 ; RECT 2.000 5.800 3.800 6.600 ; RECT 3.000 7.200 5.600 8.000 ; RECT 3.000 5.800 3.800 10.200 ; RECT 2.000 9.400 3.800 10.200 ; RECT 2.000 9.400 2.800 18.800 ; RECT 5.200 1.200 6.000 6.600 ; RECT 5.200 5.800 7.400 6.600 ; RECT 6.600 7.200 9.000 8.000 ; RECT 6.600 5.800 7.400 10.200 ; RECT 5.200 9.400 7.400 10.200 ; RECT 5.200 9.400 6.000 18.800 ; RECT 8.400 1.200 9.200 6.600 ; RECT 8.400 5.800 10.600 6.600 ; RECT 9.800 7.200 12.400 8.000 ; RECT 9.800 5.800 10.600 10.200 ; RECT 8.400 9.400 10.600 10.200 ; RECT 8.400 9.400 9.200 18.800 ; RECT 11.600 1.200 12.400 6.600 ; RECT 11.600 5.800 14.000 6.600 ; RECT 13.200 7.200 15.000 8.000 ; RECT 13.200 5.800 14.000 10.200 ; RECT 11.600 9.400 14.000 10.200 ; RECT 11.600 9.400 12.400 18.800 ; RECT 14.800 1.200 15.600 6.600 ; RECT 14.800 5.800 16.600 6.600 ; RECT 15.800 7.200 18.400 8.000 ; RECT 15.800 5.800 16.600 10.200 ; RECT 14.800 9.400 16.600 10.200 ; RECT 14.800 9.400 15.600 18.800 ; RECT 18.000 1.200 18.800 6.600 ; RECT 18.000 5.800 20.200 6.600 ; RECT 19.400 7.200 21.800 8.000 ; RECT 19.400 5.800 20.200 10.200 ; RECT 18.000 9.400 20.200 10.200 ; RECT 18.000 9.400 18.800 18.800 ; RECT 21.200 1.200 22.000 6.600 ; RECT 21.200 5.800 23.400 6.600 ; RECT 22.600 7.200 25.200 8.000 ; RECT 22.600 5.800 23.400 10.200 ; RECT 21.200 9.400 23.400 10.200 ; RECT 21.200 9.400 22.000 18.800 ; END END CLKBUF3 MACRO PADFC CLASS ENDCAP TOPLEFT ; FOREIGN PADFC 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 300.000 BY 300.000 ; SYMMETRY X Y R90 ; SITE corner ; OBS LAYER metal4 ; RECT 0.600 0.600 299.400 299.400 ; LAYER metal3 ; RECT 0.600 0.600 299.400 299.400 ; LAYER metal2 ; RECT 98.000 0.000 170.400 299.400 ; RECT 174.800 0.000 195.800 299.400 ; RECT 202.200 0.000 223.200 299.400 ; RECT 227.600 0.000 300.000 72.400 ; RECT 0.600 76.800 300.000 97.800 ; RECT 0.600 104.000 300.000 125.200 ; RECT 0.600 129.600 300.000 202.000 ; RECT 0.600 0.600 299.400 299.400 ; LAYER metal1 ; RECT 98.000 0.000 195.800 299.400 ; RECT 202.200 0.000 300.000 97.800 ; RECT 0.600 104.000 300.000 202.000 ; RECT 0.600 0.600 299.400 299.400 ; END END PADFC MACRO PADGND CLASS PAD ; FOREIGN PADGND 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 90.000 BY 300.000 ; SYMMETRY R90 ; SITE IO ; PIN YPAD DIRECTION OUTPUT ; PORT LAYER metal4 ; RECT 37.400 254.800 51.200 269.800 ; END END YPAD PIN gnd DIRECTION INOUT ; USE GROUND ; PORT CLASS CORE ; LAYER metal1 ; RECT 34.800 0.000 54.800 0.800 ; END END gnd OBS LAYER metal4 ; RECT 0.600 0.600 89.400 253.000 ; RECT 0.600 271.600 89.400 299.000 ; RECT 0.600 0.600 35.600 299.400 ; RECT 53.000 0.600 89.400 299.400 ; LAYER metal3 ; RECT 0.600 0.600 89.400 299.400 ; LAYER metal2 ; RECT 0.000 0.000 90.000 72.400 ; RECT 0.600 76.600 89.600 97.800 ; RECT 0.000 76.800 90.000 97.800 ; RECT 0.000 104.200 90.000 125.200 ; RECT 0.000 129.600 90.000 202.000 ; RECT 0.600 0.000 89.400 299.400 ; RECT 6.000 0.000 84.000 300.000 ; LAYER metal1 ; RECT 0.000 0.000 34.200 97.800 ; RECT 55.600 0.000 90.000 97.800 ; RECT 0.000 104.200 90.000 202.000 ; RECT 0.600 1.800 89.400 299.400 ; RECT 6.000 1.800 84.000 300.000 ; END END PADGND MACRO PADVDD CLASS PAD ; FOREIGN PADVDD 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 90.000 BY 300.000 ; SYMMETRY R90 ; SITE IO ; PIN YPAD DIRECTION OUTPUT ; PORT LAYER metal4 ; RECT 42.200 266.000 44.400 268.400 ; END END YPAD PIN vdd DIRECTION INOUT ; USE POWER ; PORT CLASS CORE ; LAYER metal1 ; RECT 35.400 0.000 54.600 0.800 ; END END vdd OBS LAYER metal4 ; RECT 0.600 0.600 89.400 264.200 ; RECT 0.600 270.200 89.400 299.000 ; RECT 0.600 0.600 40.400 299.400 ; RECT 46.200 0.600 89.400 299.400 ; LAYER metal3 ; RECT 0.600 0.600 89.400 299.400 ; LAYER metal2 ; RECT 0.000 0.000 34.400 72.400 ; RECT 35.400 0.000 54.600 300.000 ; RECT 55.600 0.000 90.000 72.400 ; RECT 0.000 76.800 90.000 97.800 ; RECT 0.000 104.200 90.000 125.200 ; RECT 0.000 129.600 90.000 202.000 ; RECT 0.600 1.800 89.400 299.400 ; RECT 6.000 1.800 84.000 300.000 ; LAYER metal1 ; RECT 0.000 0.000 34.400 97.800 ; RECT 55.600 0.000 90.000 97.800 ; RECT 0.000 104.200 90.000 202.000 ; RECT 0.600 1.800 89.400 299.400 ; RECT 6.000 1.800 84.000 300.000 ; END END PADVDD MACRO PADINC CLASS PAD ; FOREIGN PADINC 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 90.000 BY 300.000 ; SYMMETRY R90 ; SITE IO ; PIN YPAD DIRECTION OUTPUT ; PORT LAYER metal4 ; RECT 42.200 266.000 44.400 268.400 ; END END YPAD PIN DI DIRECTION OUTPUT ; PORT LAYER metal2 ; RECT 82.200 -0.400 83.000 0.400 ; RECT 81.600 0.000 83.400 0.400 ; END END DI OBS LAYER metal4 ; RECT 0.600 0.600 89.400 264.200 ; RECT 0.600 270.200 89.400 299.000 ; RECT 0.600 0.600 40.400 299.400 ; RECT 46.200 0.600 89.400 299.400 ; LAYER metal3 ; RECT 0.600 0.600 80.600 299.400 ; RECT 84.400 0.600 89.400 299.400 ; RECT 0.600 1.400 89.400 299.400 ; LAYER metal2 ; RECT 0.000 0.000 34.400 72.400 ; RECT 35.400 0.000 54.600 300.000 ; RECT 55.600 0.000 78.200 300.000 ; RECT 79.000 0.000 80.800 300.000 ; RECT 0.000 0.600 80.800 72.400 ; RECT 84.200 0.000 90.000 72.400 ; RECT 0.000 76.800 90.000 97.800 ; RECT 0.000 104.200 90.000 125.200 ; RECT 0.000 129.600 90.000 202.000 ; RECT 0.600 1.400 89.400 299.400 ; RECT 6.000 1.400 84.000 300.000 ; LAYER metal1 ; RECT 0.000 0.000 90.000 97.800 ; RECT 0.000 104.200 90.000 202.000 ; RECT 0.600 0.000 89.400 299.400 ; RECT 6.000 0.000 84.000 300.000 ; END END PADINC MACRO PADINOUT CLASS PAD ; FOREIGN PADINOUT 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 90.000 BY 300.000 ; SYMMETRY R90 ; SITE IO ; PIN YPAD DIRECTION OUTPUT ; PORT LAYER metal4 ; RECT 42.200 266.000 44.400 268.400 ; END END YPAD PIN DO DIRECTION INPUT ; PORT LAYER metal2 ; RECT 8.200 -0.400 9.000 0.400 ; RECT 7.600 0.000 9.400 0.400 ; END END DO PIN DI DIRECTION OUTPUT ; PORT LAYER metal2 ; RECT 82.200 -0.400 83.000 0.400 ; RECT 81.600 0.000 83.400 0.400 ; END END DI PIN OEN DIRECTION INPUT ; PORT LAYER metal2 ; RECT 2.600 -0.400 3.400 0.400 ; RECT 2.200 0.000 4.000 0.400 ; END END OEN OBS LAYER metal4 ; RECT 0.600 0.600 89.400 264.200 ; RECT 0.600 270.200 89.400 299.000 ; RECT 0.600 0.600 40.400 299.400 ; RECT 46.200 0.600 89.400 299.400 ; LAYER metal3 ; RECT 0.600 0.600 1.200 299.400 ; RECT 5.000 0.600 6.600 299.400 ; RECT 10.400 0.600 80.600 299.400 ; RECT 84.400 0.600 89.400 299.400 ; RECT 0.600 1.400 89.400 299.400 ; LAYER metal2 ; RECT 10.200 0.000 34.400 300.000 ; RECT 35.400 0.000 54.600 300.000 ; RECT 55.600 0.000 78.200 300.000 ; RECT 0.000 0.000 1.400 72.400 ; RECT 4.800 0.000 6.800 299.400 ; RECT 79.000 0.000 80.800 300.000 ; RECT 10.200 0.600 80.800 300.000 ; RECT 84.200 0.000 90.000 72.400 ; RECT 0.000 76.800 90.000 97.800 ; RECT 0.000 104.200 90.000 125.200 ; RECT 0.000 129.600 90.000 202.000 ; RECT 0.600 1.400 89.400 299.400 ; RECT 6.000 1.400 84.000 300.000 ; LAYER metal1 ; RECT 0.000 0.000 90.000 97.800 ; RECT 0.000 104.200 90.000 202.000 ; RECT 0.600 0.000 89.400 299.400 ; RECT 6.000 0.000 84.000 300.000 ; END END PADINOUT MACRO PADNC CLASS PAD ; FOREIGN PADNC 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 90.000 BY 300.000 ; SYMMETRY R90 ; SITE IO ; OBS LAYER metal4 ; RECT 0.600 0.600 89.400 299.400 ; LAYER metal3 ; RECT 0.600 0.600 89.400 299.400 ; LAYER metal2 ; RECT 0.000 0.000 90.000 72.400 ; RECT 0.000 76.800 90.000 97.800 ; RECT 0.000 104.200 90.000 125.200 ; RECT 0.000 129.600 90.000 202.000 ; RECT 0.600 0.000 89.400 299.400 ; LAYER metal1 ; RECT 0.000 0.000 90.000 97.800 ; RECT 0.000 104.200 90.000 202.000 ; RECT 0.600 0.000 89.400 299.400 ; END END PADNC MACRO PADOUT CLASS PAD ; FOREIGN PADOUT 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 90.000 BY 300.000 ; SYMMETRY R90 ; SITE IO ; PIN YPAD DIRECTION OUTPUT ; PORT LAYER metal4 ; RECT 42.200 266.000 44.400 268.400 ; END END YPAD PIN DO DIRECTION INPUT ; PORT LAYER metal2 ; RECT 8.200 -0.400 9.000 0.400 ; RECT 7.600 0.000 9.400 0.400 ; END END DO OBS LAYER metal4 ; RECT 0.600 0.600 89.400 264.200 ; RECT 0.600 270.200 89.400 299.000 ; RECT 0.600 0.600 40.400 299.400 ; RECT 46.200 0.600 89.400 299.400 ; LAYER metal3 ; RECT 0.600 0.600 6.600 299.400 ; RECT 10.400 0.600 89.400 299.400 ; RECT 0.600 1.400 89.400 299.400 ; LAYER metal2 ; RECT 0.000 0.000 1.400 72.400 ; RECT 2.200 0.000 4.000 299.400 ; RECT 4.800 0.000 6.800 299.400 ; RECT 10.200 0.000 34.400 300.000 ; RECT 35.400 0.000 54.600 300.000 ; RECT 55.600 0.000 78.200 300.000 ; RECT 79.000 0.000 80.800 300.000 ; RECT 81.600 0.000 83.400 300.000 ; RECT 0.000 0.600 6.800 72.400 ; RECT 10.200 0.600 90.000 72.400 ; RECT 84.200 0.000 90.000 72.400 ; RECT 0.000 76.800 90.000 97.800 ; RECT 0.000 104.200 90.000 125.200 ; RECT 0.000 129.600 90.000 202.000 ; RECT 0.600 1.400 89.400 299.400 ; RECT 6.000 1.400 84.000 300.000 ; LAYER metal1 ; RECT 0.000 0.000 90.000 97.800 ; RECT 0.000 104.200 90.000 202.000 ; RECT 0.600 0.000 89.400 299.400 ; RECT 6.000 0.000 84.000 300.000 ; END END PADOUT END LIBRARY qflow-1.1.23/README0000644000175000001440000000427012526236535012332 0ustar timusersqflow v.1.1 --------------------------------------------------------------- Tim Edwards Open Circuit Design v1.0 April 2013 v1.1 May 2015 --------------------------------------------------------------- GPL Copyright (c) 2015 --------------------------------------------------------------- Default technology uses OSU open source digital cell libraries See http://vlsiarch.ecen.okstate.edu/flows/ --------------------------------------------------------------- To compile and install: ./configure make make install See full instructions on http://opencircuitdesign.com/qflow/ The ./configure needs arguments for each tool of the tool chain that is not in the standard search path. Qflow will need to be able to find the following tools: yosys graywolf qrouter magic All of these tools typically install in a standard location that is in the normal user path, such as /usr/local/bin/. -------------------------------------------------------------- "qflow" is the original verilog digital flow from opencircuitdesign, reorganized for the following reasons: (1) All the technology-independent scripts and programs can be organized in one place, and not be copied for every project. (2) All the technology-dependent files can be organized under a single tech directory, with the technology specified on the command-line, or even pulled from a file in the layout directory. (3) Various working directories can be reassigned by setting environment variables (4) The C source code files can be compiled under a standard "make" process (5) The compile and install process can be put under gnu automake/autoconf. (6) The location of external programs (e.g., qrouter and graywolf) can be searched for by autoconf, or passed as arguments to the configure script (7) Try to convert and handle all files in standard formats: mainly RTL verilog, LEF, and DEF. (8) Consolidate all configuration information into a single config file that can call out each tool or tools for which the configuration information applies, much like graywolf does, except extended to include the other tools in qflow. -------------------------------------------------------------- qflow-1.1.23/Makefile0000644000175000001440000000102512526236535013105 0ustar timusers# # qflow project main Makefile # SHELL = /bin/sh EXEEXT = TARGETS = src scripts tech all: $(TARGETS) @for target in $(TARGETS); do\ (cd $$target ; $(MAKE) all) ;\ done install: @for target in $(TARGETS); do\ (cd $$target ; $(MAKE) install) ;\ done clean: @for target in $(TARGETS); do\ (cd $$target ; $(MAKE) clean) ;\ done distclean: @for target in $(TARGETS); do\ (cd $$target ; $(MAKE) distclean) ;\ done uninstall: @for target in $(TARGETS); do\ (cd $$target ; $(MAKE) uninstall) ;\ done qflow-1.1.23/config.sub0000755000175000001440000006700512526236535013442 0ustar timusers#! /bin/sh # Configuration validation subroutine script. # Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001 # Free Software Foundation, Inc. timestamp='2001-08-13' # This file is (in principle) common to ALL GNU software. # The presence of a machine in this file suggests that SOME GNU software # can handle that machine. It does not imply ALL GNU software can. # # This file is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 59 Temple Place - Suite 330, # Boston, MA 02111-1307, USA. # As a special exception to the GNU General Public License, if you # distribute this file as part of a program that contains a # configuration script generated by Autoconf, you may include it under # the same distribution terms that you use for the rest of that program. # Please send patches to . # # Configuration subroutine to validate and canonicalize a configuration type. # Supply the specified configuration type as an argument. # If it is invalid, we print an error message on stderr and exit with code 1. # Otherwise, we print the canonical config type on stdout and succeed. # This file is supposed to be the same for all GNU packages # and recognize all the CPU types, system types and aliases # that are meaningful with *any* GNU software. # Each package is responsible for reporting which valid configurations # it does not support. The user should be able to distinguish # a failure to support a valid configuration from a meaningless # configuration. # The goal of this file is to map all the various variations of a given # machine specification into a single specification in the form: # CPU_TYPE-MANUFACTURER-OPERATING_SYSTEM # or in some cases, the newer four-part form: # CPU_TYPE-MANUFACTURER-KERNEL-OPERATING_SYSTEM # It is wrong to echo any other type of specification. me=`echo "$0" | sed -e 's,.*/,,'` usage="\ Usage: $0 [OPTION] CPU-MFR-OPSYS $0 [OPTION] ALIAS Canonicalize a configuration name. Operation modes: -h, --help print this help, then exit -t, --time-stamp print date of last modification, then exit -v, --version print version number, then exit Report bugs and patches to ." version="\ GNU config.sub ($timestamp) Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. This is free software; see the source for copying conditions. There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE." help=" Try \`$me --help' for more information." # Parse command line while test $# -gt 0 ; do case $1 in --time-stamp | --time* | -t ) echo "$timestamp" ; exit 0 ;; --version | -v ) echo "$version" ; exit 0 ;; --help | --h* | -h ) echo "$usage"; exit 0 ;; -- ) # Stop option processing shift; break ;; - ) # Use stdin as input. break ;; -* ) echo "$me: invalid option $1$help" exit 1 ;; *local*) # First pass through any local machine types. echo $1 exit 0;; * ) break ;; esac done case $# in 0) echo "$me: missing argument$help" >&2 exit 1;; 1) ;; *) echo "$me: too many arguments$help" >&2 exit 1;; esac # Separate what the user gave into CPU-COMPANY and OS or KERNEL-OS (if any). # Here we must recognize all the valid KERNEL-OS combinations. maybe_os=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\2/'` case $maybe_os in nto-qnx* | linux-gnu* | storm-chaos* | os2-emx* | windows32-*) os=-$maybe_os basic_machine=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\1/'` ;; *) basic_machine=`echo $1 | sed 's/-[^-]*$//'` if [ $basic_machine != $1 ] then os=`echo $1 | sed 's/.*-/-/'` else os=; fi ;; esac ### Let's recognize common machines as not being operating systems so ### that things like config.sub decstation-3100 work. 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m6811 | m68hc11 | m6812 | m68hc12) # Motorola 68HC11/12. basic_machine=$basic_machine-unknown os=-none ;; m88110 | m680[12346]0 | m683?2 | m68360 | m5200 | v70 | w65 | z8k) ;; # We use `pc' rather than `unknown' # because (1) that's what they normally are, and # (2) the word "unknown" tends to confuse beginning users. i*86 | x86_64) basic_machine=$basic_machine-pc ;; # Object if more than one company name word. *-*-*) echo Invalid configuration \`$1\': machine \`$basic_machine\' not recognized 1>&2 exit 1 ;; # Recognize the basic CPU types with company name. 580-* \ | a29k-* \ | alpha-* | alphaev[4-8]-* | alphaev56-* | alphaev6[78]-* \ | alphapca5[67]-* | arc-* \ | arm-* | armbe-* | armle-* | armv*-* \ | bs2000-* \ | c[123]* | c30-* | [cjt]90-* | c54x-* \ | clipper-* | cray2-* | cydra-* \ | d10v-* | d30v-* \ | elxsi-* \ | f30[01]-* | f700-* | fr30-* | fx80-* \ | h8300-* | h8500-* \ | hppa-* | hppa1.[01]-* | hppa2.0-* | hppa2.0[nw]-* | hppa64-* \ | i*86-* | i860-* | i960-* | ia64-* \ | m32r-* \ | m68000-* | m680[01234]0-* | m68360-* | m683?2-* | m68k-* \ | m88110-* | m88k-* | mcore-* \ | mips-* | mips16-* | mips64-* | mips64el-* | mips64orion-* \ | mips64orionel-* | mips64vr4100-* | mips64vr4100el-* \ | mips64vr4300-* | mips64vr4300el-* | mipsbe-* | mipsel-* \ | mipsle-* | mipstx39-* | mipstx39el-* \ | none-* | np1-* | ns16k-* | ns32k-* \ | orion-* \ | pdp10-* | pdp11-* | pj-* | pjl-* | pn-* | power-* \ | powerpc-* | powerpc64-* | powerpc64le-* | powerpcle-* | ppcbe-* \ | pyramid-* \ | romp-* | rs6000-* \ | s390-* | s390x-* \ | sh-* | sh[34]-* | sh[34]eb-* | shbe-* | shle-* \ | sparc-* | sparc64-* | sparc86x-* | sparclite-* \ | sparcv9-* | sparcv9b-* | strongarm-* | sv1-* \ | t3e-* | tahoe-* | thumb-* | tic30-* | tic54x-* | tic80-* | tron-* \ | v850-* | vax-* \ | we32k-* \ | x86-* | x86_64-* | xmp-* | xps100-* | xscale-* \ | ymp-* \ | z8k-*) ;; # Recognize the various machine names and aliases which stand # for a CPU type and a company and sometimes even an OS. 386bsd) basic_machine=i386-unknown os=-bsd ;; 3b1 | 7300 | 7300-att | att-7300 | pc7300 | safari | unixpc) basic_machine=m68000-att ;; 3b*) basic_machine=we32k-att ;; a29khif) basic_machine=a29k-amd os=-udi ;; adobe68k) basic_machine=m68010-adobe os=-scout ;; alliant | fx80) basic_machine=fx80-alliant ;; altos | altos3068) basic_machine=m68k-altos ;; am29k) basic_machine=a29k-none os=-bsd ;; amdahl) basic_machine=580-amdahl os=-sysv ;; amiga | amiga-*) basic_machine=m68k-unknown ;; amigaos | amigados) basic_machine=m68k-unknown os=-amigaos ;; amigaunix | amix) basic_machine=m68k-unknown os=-sysv4 ;; apollo68) basic_machine=m68k-apollo os=-sysv ;; apollo68bsd) basic_machine=m68k-apollo os=-bsd ;; aux) basic_machine=m68k-apple os=-aux ;; balance) basic_machine=ns32k-sequent os=-dynix ;; convex-c1) basic_machine=c1-convex os=-bsd ;; convex-c2) basic_machine=c2-convex os=-bsd ;; convex-c32) basic_machine=c32-convex os=-bsd ;; convex-c34) basic_machine=c34-convex os=-bsd ;; convex-c38) basic_machine=c38-convex os=-bsd ;; cray | ymp) basic_machine=ymp-cray os=-unicos ;; cray2) basic_machine=cray2-cray os=-unicos ;; [cjt]90) basic_machine=${basic_machine}-cray os=-unicos ;; crds | unos) basic_machine=m68k-crds ;; cris | cris-* | etrax*) basic_machine=cris-axis ;; da30 | da30-*) basic_machine=m68k-da30 ;; decstation | decstation-3100 | pmax | pmax-* | pmin | dec3100 | decstatn) basic_machine=mips-dec ;; delta | 3300 | motorola-3300 | motorola-delta \ | 3300-motorola | delta-motorola) basic_machine=m68k-motorola ;; delta88) basic_machine=m88k-motorola os=-sysv3 ;; dpx20 | dpx20-*) basic_machine=rs6000-bull os=-bosx ;; dpx2* | dpx2*-bull) basic_machine=m68k-bull os=-sysv3 ;; ebmon29k) basic_machine=a29k-amd os=-ebmon ;; elxsi) basic_machine=elxsi-elxsi os=-bsd ;; encore | umax | mmax) basic_machine=ns32k-encore ;; es1800 | OSE68k | ose68k | ose | OSE) basic_machine=m68k-ericsson os=-ose ;; fx2800) basic_machine=i860-alliant ;; genix) basic_machine=ns32k-ns ;; gmicro) basic_machine=tron-gmicro os=-sysv ;; go32) basic_machine=i386-pc os=-go32 ;; h3050r* | hiux*) basic_machine=hppa1.1-hitachi os=-hiuxwe2 ;; h8300hms) basic_machine=h8300-hitachi os=-hms ;; h8300xray) basic_machine=h8300-hitachi os=-xray ;; h8500hms) basic_machine=h8500-hitachi os=-hms ;; harris) basic_machine=m88k-harris os=-sysv3 ;; hp300-*) basic_machine=m68k-hp ;; hp300bsd) basic_machine=m68k-hp os=-bsd ;; hp300hpux) basic_machine=m68k-hp os=-hpux ;; hp3k9[0-9][0-9] | hp9[0-9][0-9]) basic_machine=hppa1.0-hp ;; hp9k2[0-9][0-9] | hp9k31[0-9]) basic_machine=m68000-hp ;; hp9k3[2-9][0-9]) basic_machine=m68k-hp ;; hp9k6[0-9][0-9] | hp6[0-9][0-9]) basic_machine=hppa1.0-hp ;; hp9k7[0-79][0-9] | hp7[0-79][0-9]) basic_machine=hppa1.1-hp ;; hp9k78[0-9] | hp78[0-9]) # FIXME: really hppa2.0-hp basic_machine=hppa1.1-hp ;; hp9k8[67]1 | hp8[67]1 | hp9k80[24] | hp80[24] | hp9k8[78]9 | hp8[78]9 | hp9k893 | hp893) # FIXME: really hppa2.0-hp basic_machine=hppa1.1-hp ;; hp9k8[0-9][13679] | hp8[0-9][13679]) basic_machine=hppa1.1-hp ;; hp9k8[0-9][0-9] | hp8[0-9][0-9]) basic_machine=hppa1.0-hp ;; hppa-next) os=-nextstep3 ;; hppaosf) basic_machine=hppa1.1-hp os=-osf ;; hppro) basic_machine=hppa1.1-hp os=-proelf ;; i370-ibm* | ibm*) basic_machine=i370-ibm ;; # I'm not sure what "Sysv32" means. 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ppcle | powerpclittle | ppc-le | powerpc-little) basic_machine=powerpcle-unknown ;; ppcle-* | powerpclittle-*) basic_machine=powerpcle-`echo $basic_machine | sed 's/^[^-]*-//'` ;; ppc64) basic_machine=powerpc64-unknown ;; ppc64-*) basic_machine=powerpc64-`echo $basic_machine | sed 's/^[^-]*-//'` ;; ppc64le | powerpc64little | ppc64-le | powerpc64-little) basic_machine=powerpc64le-unknown ;; ppc64le-* | powerpc64little-*) basic_machine=powerpc64le-`echo $basic_machine | sed 's/^[^-]*-//'` ;; ps2) basic_machine=i386-ibm ;; pw32) basic_machine=i586-unknown os=-pw32 ;; rom68k) basic_machine=m68k-rom68k os=-coff ;; rm[46]00) basic_machine=mips-siemens ;; rtpc | rtpc-*) basic_machine=romp-ibm ;; sa29200) basic_machine=a29k-amd os=-udi ;; sequent) basic_machine=i386-sequent ;; sh) basic_machine=sh-hitachi os=-hms ;; sparclite-wrs) basic_machine=sparclite-wrs os=-vxworks ;; sps7) basic_machine=m68k-bull os=-sysv2 ;; spur) basic_machine=spur-unknown ;; st2000) basic_machine=m68k-tandem ;; stratus) basic_machine=i860-stratus os=-sysv4 ;; sun2) basic_machine=m68000-sun ;; sun2os3) basic_machine=m68000-sun os=-sunos3 ;; sun2os4) basic_machine=m68000-sun os=-sunos4 ;; sun3os3) basic_machine=m68k-sun os=-sunos3 ;; sun3os4) basic_machine=m68k-sun os=-sunos4 ;; sun4os3) basic_machine=sparc-sun os=-sunos3 ;; sun4os4) basic_machine=sparc-sun os=-sunos4 ;; sun4sol2) basic_machine=sparc-sun os=-solaris2 ;; sun3 | sun3-*) basic_machine=m68k-sun ;; sun4) basic_machine=sparc-sun ;; sun386 | sun386i | roadrunner) basic_machine=i386-sun ;; sv1) basic_machine=sv1-cray os=-unicos ;; symmetry) basic_machine=i386-sequent os=-dynix ;; t3e) basic_machine=t3e-cray os=-unicos ;; tic54x | c54x*) basic_machine=tic54x-unknown os=-coff ;; tx39) basic_machine=mipstx39-unknown ;; tx39el) basic_machine=mipstx39el-unknown ;; tower | tower-32) basic_machine=m68k-ncr ;; udi29k) basic_machine=a29k-amd os=-udi ;; ultra3) basic_machine=a29k-nyu os=-sym1 ;; v810 | necv810) basic_machine=v810-nec os=-none ;; vaxv) basic_machine=vax-dec os=-sysv ;; vms) basic_machine=vax-dec os=-vms ;; vpp*|vx|vx-*) basic_machine=f301-fujitsu ;; vxworks960) basic_machine=i960-wrs os=-vxworks ;; vxworks68) basic_machine=m68k-wrs os=-vxworks ;; vxworks29k) basic_machine=a29k-wrs os=-vxworks ;; w65*) basic_machine=w65-wdc os=-none ;; w89k-*) basic_machine=hppa1.1-winbond os=-proelf ;; windows32) basic_machine=i386-pc os=-windows32-msvcrt ;; xmp) basic_machine=xmp-cray os=-unicos ;; xps | xps100) basic_machine=xps100-honeywell ;; z8k-*-coff) basic_machine=z8k-unknown os=-sim ;; none) basic_machine=none-none os=-none ;; # Here we handle the default manufacturer of certain CPU types. It is in # some cases the only manufacturer, in others, it is the most popular. w89k) basic_machine=hppa1.1-winbond ;; op50n) basic_machine=hppa1.1-oki ;; op60c) basic_machine=hppa1.1-oki ;; mips) if [ x$os = x-linux-gnu ]; then basic_machine=mips-unknown else basic_machine=mips-mips fi ;; romp) basic_machine=romp-ibm ;; rs6000) basic_machine=rs6000-ibm ;; vax) basic_machine=vax-dec ;; pdp10) # there are many clones, so DEC is not a safe bet basic_machine=pdp10-unknown ;; pdp11) basic_machine=pdp11-dec ;; we32k) basic_machine=we32k-att ;; sh3 | sh4 | sh3eb | sh4eb) basic_machine=sh-unknown ;; sparc | sparcv9 | sparcv9b) basic_machine=sparc-sun ;; cydra) basic_machine=cydra-cydrome ;; orion) basic_machine=orion-highlevel ;; orion105) basic_machine=clipper-highlevel ;; mac | mpw | mac-mpw) basic_machine=m68k-apple ;; pmac | pmac-mpw) basic_machine=powerpc-apple ;; c4x*) basic_machine=c4x-none os=-coff ;; *-unknown) # Make sure to match an already-canonicalized machine name. ;; *) echo Invalid configuration \`$1\': machine \`$basic_machine\' not recognized 1>&2 exit 1 ;; esac # Here we canonicalize certain aliases for manufacturers. case $basic_machine in *-digital*) basic_machine=`echo $basic_machine | sed 's/digital.*/dec/'` ;; *-commodore*) basic_machine=`echo $basic_machine | sed 's/commodore.*/cbm/'` ;; *) ;; esac # Decode manufacturer-specific aliases for certain operating systems. if [ x"$os" != x"" ] then case $os in # First match some system type aliases # that might get confused with valid system types. # -solaris* is a basic system type, with this one exception. -solaris1 | -solaris1.*) os=`echo $os | sed -e 's|solaris1|sunos4|'` ;; -solaris) os=-solaris2 ;; -svr4*) os=-sysv4 ;; -unixware*) os=-sysv4.2uw ;; -gnu/linux*) os=`echo $os | sed -e 's|gnu/linux|linux-gnu|'` ;; # First accept the basic system types. # The portable systems comes first. # Each alternative MUST END IN A *, to match a version number. # -sysv* is not here because it comes later, after sysvr4. -gnu* | -bsd* | -mach* | -minix* | -genix* | -ultrix* | -irix* \ | -*vms* | -sco* | -esix* | -isc* | -aix* | -sunos | -sunos[34]*\ | -hpux* | -unos* | -osf* | -luna* | -dgux* | -solaris* | -sym* \ | -amigaos* | -amigados* | -msdos* | -newsos* | -unicos* | -aof* \ | -aos* \ | -nindy* | -vxsim* | -vxworks* | -ebmon* | -hms* | -mvs* \ | -clix* | -riscos* | -uniplus* | -iris* | -rtu* | -xenix* \ | -hiux* | -386bsd* | -netbsd* | -openbsd* | -freebsd* | -riscix* \ | -lynxos* | -bosx* | -nextstep* | -cxux* | -aout* | -elf* | -oabi* \ | -ptx* | -coff* | -ecoff* | -winnt* | -domain* | -vsta* \ | -udi* | -eabi* | -lites* | -ieee* | -go32* | -aux* \ | -chorusos* | -chorusrdb* \ | -cygwin* | -pe* | -psos* | -moss* | -proelf* | -rtems* \ | -mingw32* | -linux-gnu* | -uxpv* | -beos* | -mpeix* | -udk* \ | -interix* | -uwin* | -rhapsody* | -darwin* | -opened* \ | -openstep* | -oskit* | -conix* | -pw32* | -nonstopux* \ | -storm-chaos* | -tops10* | -tenex* | -tops20* | -its* \ | -os2* | -vos*) # Remember, each alternative MUST END IN *, to match a version number. ;; -qnx*) case $basic_machine in x86-* | i*86-*) ;; *) os=-nto$os ;; esac ;; -nto*) os=-nto-qnx ;; -sim | -es1800* | -hms* | -xray | -os68k* | -none* | -v88r* \ | -windows* | -osx | -abug | -netware* | -os9* | -beos* \ | -macos* | -mpw* | -magic* | -mmixware* | -mon960* | -lnews*) ;; -mac*) os=`echo $os | sed -e 's|mac|macos|'` ;; -linux*) os=`echo $os | sed -e 's|linux|linux-gnu|'` ;; -sunos5*) os=`echo $os | sed -e 's|sunos5|solaris2|'` ;; -sunos6*) os=`echo $os | sed -e 's|sunos6|solaris3|'` ;; -opened*) os=-openedition ;; -wince*) os=-wince ;; -osfrose*) os=-osfrose ;; -osf*) os=-osf ;; -utek*) os=-bsd ;; -dynix*) os=-bsd ;; -acis*) os=-aos ;; -386bsd) os=-bsd ;; -ctix* | -uts*) os=-sysv ;; -ns2 ) os=-nextstep2 ;; -nsk*) os=-nsk ;; # Preserve the version number of sinix5. -sinix5.*) os=`echo $os | sed -e 's|sinix|sysv|'` ;; -sinix*) os=-sysv4 ;; -triton*) os=-sysv3 ;; -oss*) os=-sysv3 ;; -svr4) os=-sysv4 ;; -svr3) os=-sysv3 ;; -sysvr4) os=-sysv4 ;; # This must come after -sysvr4. -sysv*) ;; -ose*) os=-ose ;; -es1800*) os=-ose ;; -xenix) os=-xenix ;; -*mint | -mint[0-9]* | -*MiNT | -MiNT[0-9]*) os=-mint ;; -none) ;; *) # Get rid of the `-' at the beginning of $os. os=`echo $os | sed 's/[^-]*-//'` echo Invalid configuration \`$1\': system \`$os\' not recognized 1>&2 exit 1 ;; esac else # Here we handle the default operating systems that come with various machines. # The value should be what the vendor currently ships out the door with their # machine or put another way, the most popular os provided with the machine. # Note that if you're going to try to match "-MANUFACTURER" here (say, # "-sun"), then you have to tell the case statement up towards the top # that MANUFACTURER isn't an operating system. Otherwise, code above # will signal an error saying that MANUFACTURER isn't an operating # system, and we'll never get to this point. case $basic_machine in *-acorn) os=-riscix1.2 ;; arm*-rebel) os=-linux ;; arm*-semi) os=-aout ;; pdp10-*) os=-tops20 ;; pdp11-*) os=-none ;; *-dec | vax-*) os=-ultrix4.2 ;; m68*-apollo) os=-domain ;; i386-sun) os=-sunos4.0.2 ;; m68000-sun) os=-sunos3 # This also exists in the configure program, but was not the # default. # os=-sunos4 ;; m68*-cisco) os=-aout ;; mips*-cisco) os=-elf ;; mips*-*) os=-elf ;; *-tti) # must be before sparc entry or we get the wrong os. os=-sysv3 ;; sparc-* | *-sun) os=-sunos4.1.1 ;; *-be) os=-beos ;; *-ibm) os=-aix ;; *-wec) os=-proelf ;; *-winbond) os=-proelf ;; *-oki) os=-proelf ;; *-hp) os=-hpux ;; *-hitachi) os=-hiux ;; i860-* | *-att | *-ncr | *-altos | *-motorola | *-convergent) os=-sysv ;; *-cbm) os=-amigaos ;; *-dg) os=-dgux ;; *-dolphin) os=-sysv3 ;; m68k-ccur) os=-rtu ;; m88k-omron*) os=-luna ;; *-next ) os=-nextstep ;; *-sequent) os=-ptx ;; *-crds) os=-unos ;; *-ns) os=-genix ;; i370-*) os=-mvs ;; *-next) os=-nextstep3 ;; *-gould) os=-sysv ;; *-highlevel) os=-bsd ;; *-encore) os=-bsd ;; *-sgi) os=-irix ;; *-siemens) os=-sysv4 ;; *-masscomp) os=-rtu ;; f30[01]-fujitsu | f700-fujitsu) os=-uxpv ;; *-rom68k) os=-coff ;; *-*bug) os=-coff ;; *-apple) os=-macos ;; *-atari*) os=-mint ;; *) os=-none ;; esac fi # Here we handle the case where we know the os, and the CPU type, but not the # manufacturer. We pick the logical manufacturer. vendor=unknown case $basic_machine in *-unknown) case $os in -riscix*) vendor=acorn ;; -sunos*) vendor=sun ;; -aix*) vendor=ibm ;; -beos*) vendor=be ;; -hpux*) vendor=hp ;; -mpeix*) vendor=hp ;; -hiux*) vendor=hitachi ;; -unos*) vendor=crds ;; -dgux*) vendor=dg ;; -luna*) vendor=omron ;; -genix*) vendor=ns ;; -mvs* | -opened*) vendor=ibm ;; -ptx*) vendor=sequent ;; -vxsim* | -vxworks*) vendor=wrs ;; -aux*) vendor=apple ;; -hms*) vendor=hitachi ;; -mpw* | -macos*) vendor=apple ;; -*mint | -mint[0-9]* | -*MiNT | -MiNT[0-9]*) vendor=atari ;; -vos*) vendor=stratus ;; esac basic_machine=`echo $basic_machine | sed "s/unknown/$vendor/"` ;; esac echo $basic_machine$os exit 0 # Local variables: # eval: (add-hook 'write-file-hooks 'time-stamp) # time-stamp-start: "timestamp='" # time-stamp-format: "%:y-%02m-%02d" # time-stamp-end: "'" # End: qflow-1.1.23/install-sh0000755000175000001440000001273612526236535013464 0ustar timusers#!/bin/sh # # install - install a program, script, or datafile # This comes from X11R5 (mit/util/scripts/install.sh). # # Copyright 1991 by the Massachusetts Institute of Technology # # Permission to use, copy, modify, distribute, and sell this software and its # documentation for any purpose is hereby granted without fee, provided that # the above copyright notice appear in all copies and that both that # copyright notice and this permission notice appear in supporting # documentation, and that the name of M.I.T. not be used in advertising or # publicity pertaining to distribution of the software without specific, # written prior permission. M.I.T. makes no representations about the # suitability of this software for any purpose. It is provided "as is" # without express or implied warranty. # # Calling this script install-sh is preferred over install.sh, to prevent # `make' implicit rules from creating a file called install from it # when there is no Makefile. # # This script is compatible with the BSD install script, but was written # from scratch. It can only install one file at a time, a restriction # shared with many OS's install programs. # set DOITPROG to echo to test this script # Don't use :- since 4.3BSD and earlier shells don't like it. doit="${DOITPROG-}" # put in absolute paths if you don't have them in your path; or use env. vars. mvprog="${MVPROG-mv}" cpprog="${CPPROG-cp}" chmodprog="${CHMODPROG-chmod}" chownprog="${CHOWNPROG-chown}" chgrpprog="${CHGRPPROG-chgrp}" stripprog="${STRIPPROG-strip}" rmprog="${RMPROG-rm}" mkdirprog="${MKDIRPROG-mkdir}" transformbasename="" transform_arg="" instcmd="$mvprog" chmodcmd="$chmodprog 0755" chowncmd="" chgrpcmd="" stripcmd="" rmcmd="$rmprog -f" mvcmd="$mvprog" src="" dst="" dir_arg="" while [ x"$1" != x ]; do case $1 in -c) instcmd="$cpprog" shift continue;; -d) dir_arg=true shift continue;; -m) chmodcmd="$chmodprog $2" shift shift continue;; -o) chowncmd="$chownprog $2" shift shift continue;; -g) chgrpcmd="$chgrpprog $2" shift shift continue;; -s) stripcmd="$stripprog" shift continue;; -t=*) transformarg=`echo $1 | sed 's/-t=//'` shift continue;; -b=*) transformbasename=`echo $1 | sed 's/-b=//'` shift continue;; *) if [ x"$src" = x ] then src=$1 else # this colon is to work around a 386BSD /bin/sh bug : dst=$1 fi shift continue;; esac done if [ x"$src" = x ] then echo "install: no input file specified" exit 1 else true fi if [ x"$dir_arg" != x ]; then dst=$src src="" if [ -d $dst ]; then instcmd=: chmodcmd="" else instcmd=mkdir fi else # Waiting for this to be detected by the "$instcmd $src $dsttmp" command # might cause directories to be created, which would be especially bad # if $src (and thus $dsttmp) contains '*'. if [ -f $src -o -d $src ] then true else echo "install: $src does not exist" exit 1 fi if [ x"$dst" = x ] then echo "install: no destination specified" exit 1 else true fi # If destination is a directory, append the input filename; if your system # does not like double slashes in filenames, you may need to add some logic if [ -d $dst ] then dst="$dst"/`basename $src` else true fi fi ## this sed command emulates the dirname command dstdir=`echo $dst | sed -e 's,[^/]*$,,;s,/$,,;s,^$,.,'` # Make sure that the destination directory exists. # this part is taken from Noah Friedman's mkinstalldirs script # Skip lots of stat calls in the usual case. if [ ! -d "$dstdir" ]; then defaultIFS=' ' IFS="${IFS-${defaultIFS}}" oIFS="${IFS}" # Some sh's can't handle IFS=/ for some reason. IFS='%' set - `echo ${dstdir} | sed -e 's@/@%@g' -e 's@^%@/@'` IFS="${oIFS}" pathcomp='' while [ $# -ne 0 ] ; do pathcomp="${pathcomp}${1}" shift if [ ! -d "${pathcomp}" ] ; then $mkdirprog "${pathcomp}" else true fi pathcomp="${pathcomp}/" done fi if [ x"$dir_arg" != x ] then $doit $instcmd $dst && if [ x"$chowncmd" != x ]; then $doit $chowncmd $dst; else true ; fi && if [ x"$chgrpcmd" != x ]; then $doit $chgrpcmd $dst; else true ; fi && if [ x"$stripcmd" != x ]; then $doit $stripcmd $dst; else true ; fi && if [ x"$chmodcmd" != x ]; then $doit $chmodcmd $dst; else true ; fi else # If we're going to rename the final executable, determine the name now. if [ x"$transformarg" = x ] then dstfile=`basename $dst` else dstfile=`basename $dst $transformbasename | sed $transformarg`$transformbasename fi # don't allow the sed command to completely eliminate the filename if [ x"$dstfile" = x ] then dstfile=`basename $dst` else true fi # Make a temp file name in the proper directory. dsttmp=$dstdir/#inst.$$# # Move or copy the file name to the temp name $doit $instcmd $src $dsttmp && trap "rm -f ${dsttmp}" 0 && # and set any options; do chmod last to preserve setuid bits # If any of these fail, we abort the whole thing. If we want to # ignore errors from any of these, just make sure not to ignore # errors from the above "$doit $instcmd $src $dsttmp" command. if [ x"$chowncmd" != x ]; then $doit $chowncmd $dsttmp; else true;fi && if [ x"$chgrpcmd" != x ]; then $doit $chgrpcmd $dsttmp; else true;fi && if [ x"$stripcmd" != x ]; then $doit $stripcmd $dsttmp; else true;fi && if [ x"$chmodcmd" != x ]; then $doit $chmodcmd $dsttmp; else true;fi && # Now rename the file to the real destination. $doit $rmcmd -f $dstdir/$dstfile && $doit $mvcmd $dsttmp $dstdir/$dstfile fi && exit 0 qflow-1.1.23/scripts/0000755000175000001440000000000012624357164013137 5ustar timusersqflow-1.1.23/scripts/place2def2.tcl.in0000775000175000001440000005422012533671313016161 0ustar timusers#!TCLSH_PATH #--------------------------------------------------------------------------- # place2def2.tcl --- # # Read a GrayWolf .pl1 cell placement output file, and write a # DEF file of placed COMPONENTS and PINS, and unrouted NETS. # add ROW, TRACKS, and DIEAREA statements, as needed. # # Modified 11/15/2012 # Corrected declaration of tracks and placment of obstruction layers and # pins for the conditions of > 3 routing layers, or for reversed routing # layer orientations. # # Modified 12/06/2012 # Correction to use track offset information from the technology LEF file # instead of assuming a 1/2 track pitch offset. Also, corrected the pin # positions, which were not subtracting off the offset used for the cell # positions. # # Modified 3/29/2013 # Correction for pin positions when the cell boundary is not on a track # position, and the track offset information is in the OFFSET line for # the route layer in the technology LEF file. #--------------------------------------------------------------------------- if {$argc < 3} { puts stdout "Usage: place2def2 ..." exit 0 } # NOTE: There is no scaling. GrayWolf values are in centimicrons, # as are DEF values (UNITS DISTANCE MICRONS 100) puts stdout "Running place2def2.tcl" set topname [lindex $argv 0] set pl1name ${topname}.pl1 set pl2name ${topname}.pl2 set parname ${topname}.par set pinname ${topname}.pin set defname ${topname}.def set cfgname ${topname}.cfg set infoname ${topname}.info # Number of layers we want to use for routing is determined # by counting the layers listed in the .par file. if [catch {open $parname r} fpar] { puts stderr "Error: can't open file $parname for input" return } set qrouter_path [lindex $argv 1] set leffiles [lrange $argv 2 end] #----------------------------------------------------------------- # Pick up the width of a feedthrough cell from the .par file # Also find the number of routing layers to use by counting # "layer" lines #----------------------------------------------------------------- set paramval 0 set numlayers 0 set rulesection 0 while {[gets $fpar line] >= 0} { regexp {^[ \t]*TWSC[*.]feedThruWidth[ \t]*:[ \t]*([^ ]+)[ \t]+} $line lmatch \ paramval if {[regexp {^[ \t]*RULES} $line lmatch] == 1} { set rulesection 1 } if {$rulesection == 1} { if {[regexp {^[ \t]*layer[ \t]*} $line lmatch] == 1} { incr numlayers } if {[regexp {^[ \t]*ENDRULES} $line lmatch] == 1} { set rulesection 0 } } } close $fpar if {$paramval > 0} { puts stdout "Adjusting to feedthrough width of $paramval" } if {$numlayers == 0} { puts stdout "No layers specified in .par file. Using default 3" set numlayers 3 } if [catch {open $pl1name r} fpl1] { puts stderr "Error: can't open file $pl1name for input" return } if [catch {open $pl2name r} fpl2] { puts stderr "Error: can't open file $pl2name for input" return } if [catch {open $defname w} fdef] { puts stderr "Error: can't open file $defname for output" return } if [catch {open $cfgname w} fcfg] { puts stderr "Error: can't open file $cfgname for output" return } #----------------------------------------------------------------- # DEF file header #----------------------------------------------------------------- puts $fdef "VERSION 5.6 ;" puts $fdef "NAMESCASESENSITIVE ON ;" puts $fdef "DIVIDERCHAR \"/\" ;" puts $fdef "BUSBITCHARS \"<>\" ;" puts $fdef "DESIGN $topname ;" puts $fdef "UNITS DISTANCE MICRONS 100 ;" puts $fdef "" #----------------------------------------------------------------- # Part 1: Area and routing tracks #----------------------------------------------------------------- #----------------------------------------------------------------- # Read the .pl1 file to get pin position corrections due to # feedthroughs (i.e., count the number of feedthroughs used per row) #----------------------------------------------------------------- set rowyvals {} while {[gets $fpl1 line] >= 0} { regexp {^[ \t]*([^ ]+)[ \t]+([^ ]+)[ \t]+([^ ]+)} $line lmatch \ instance feedx feedy if {[string equal -length 6 $instance twfeed]} { set rowidx [lsearch $rowyvals $feedy] if {$rowidx < 0} { set rowidx [llength $rowyvals] lappend rowyvals $feedy incr rowidx set rowxoff($rowidx) $paramval } else { incr rowidx incr rowxoff($rowidx) $paramval } } } close $fpl1 set fpl1 [open $pl1name r] ;# reopen for next pass #----------------------------------------------------------------- # Generate route configuration file #----------------------------------------------------------------- puts $fcfg "# route configuration file" puts $fcfg "# for project ${topname}" puts $fcfg "" puts $fcfg "Num_layers $numlayers" # NOTE: Use the following to prevent via stacks that the # technology disallows. puts $fcfg "stack 2" puts $fcfg "" foreach leffile $leffiles {puts $fcfg "lef ${leffile}"} puts $fcfg "" flush $fcfg #----------------------------------------------------------------- # Read the .pl2 file and get the full die area (components only) #----------------------------------------------------------------- # To avoid having to parse a LEF file from a Tcl script, I have # made a qrouter "-i" option to print out route layer information; # this should be found in file ${topname}.info catch {exec $qrouter_path -i $infoname -c $cfgname} set finf [open $infoname r] if {$finf != {}} { set i 0 while {[gets $finf line] >= 0} { # Older versions of qrouter assumed a track offset of 1/2 track pitch. # Newer versions correctly take the offset from the LEF file and dump the # value to the info file. Also the newer version records the track width, # although this is not used. if {[regexp {^[ \t]*([^ ]+)[ \t]+([^ ]+)[ \t]+([^ ]+)[ \t]+([^ ]+)[ \t]+([^ ]+)} \ $line lmatch layer pitch offset width orient] <= 0} { regexp {^[ \t]*([^ ]+)[ \t]+([^ ]+)[ \t]+([^ ]+)} $line lmatch \ layer pitch orient set offset [expr 0.5 * $pitch] set width $pitch } incr i set metal${i}(name) $layer set metal${i}(pitch) $pitch set metal${i}(orient) $orient set metal${i}(offset) $offset set metal${i}(width) $width } close $finf # NOTE: Treating all pitches the same for all layers in the same # direction. This is good for doing various calculations on cell # and pin positions. The track positions themselves will be placed # according to the given route layer pitch. if {$metal1(orient) == "horizontal"} { set pitchx [expr 100 * $metal2(pitch)] set pitchy [expr 100 * $metal1(pitch)] set offsetx [expr 100 * $metal2(offset)] set offsety [expr 100 * $metal1(offset)] set widthx [expr 100 * $metal2(width)] set widthy [expr 100 * $metal1(width)] } else { set pitchx [expr 100 * $metal1(pitch)] set pitchy [expr 100 * $metal2(pitch)] set offsetx [expr 100 * $metal1(offset)] set offsety [expr 100 * $metal2(offset)] set widthx [expr 100 * $metal1(width)] set widthy [expr 100 * $metal2(width)] } } else { puts stdout "Warning: No file $infoname generated, using defaults." set pitchx 160 set pitchy 200 set offsetx 80 set offsety 100 set widthx 160 set widthy 200 } # Add numlayers to the configuration file now that we know it set halfpitchx [expr $pitchx / 2]; set halfpitchy [expr $pitchy / 2]; set halfwidthx [expr $widthx / 2]; set halfwidthy [expr $widthy / 2]; set xbot 1000 set ybot 1000 set cellxbot 1000 set cellybot 1000 set xtop 0 set postxtop 0 set ytop 0 set smash 0 while {[gets $fpl2 line] >= 0} { regexp {^[ \t]*([^ ]+)[ \t]+([^ ]+)[ \t]+([^ ]+)[ \t]+([^ ]+)[ \t]+([^ ]+)[ \t]+[^ ]+[ \t]+([^ ]+)} \ $line lmatch rowidx llx lly urx ury align set pline [regexp {^[ \t]*twpin} $line lmatch] if {$pline > 0} { # Re-align pins to remove feedthrough offsets if {$align != -1} { set llx [expr $llx - $smash] set urx [expr $urx - $smash] } # Re-align pins to the nearest track pitch. Set pin size to be # equal to a route width. set pincx [expr ($llx + $urx) / 2] set pincy [expr ($lly + $ury) / 2] set pincx [expr $pincx - $halfpitchx - $offsetx] set pincy [expr $pincy - $halfpitchy - $offsety] set xgrid [expr 1 + floor($pincx / $pitchx)] set ygrid [expr 1 + floor($pincy / $pitchy)] set pincx [expr $xgrid * $pitchx + $offsetx] set pincy [expr $ygrid * $pitchy + $offsety] set llx [expr $pincx - $halfwidthx] set lly [expr $pincy - $halfwidthy] set urx [expr $pincx + $halfwidthx] set ury [expr $pincy + $halfwidthy] set posturx $urx # puts stdout "At twpin: llx=$llx pincx=$pincx urx=$urx posturx=$posturx" # puts stdout "smash=$smash halfpitch=($halfpitchx,$halfpitchy)" } else { # For each row, subtract the feedthrough correction set posturx [expr $urx] set yvals($rowidx) [list $lly $ury] if {$llx < $cellxbot} {set cellxbot $llx} if {$lly < $cellybot} {set cellybot $lly} } if {$llx < $xbot} {set xbot $llx} if {$lly < $ybot} {set ybot $lly} if {$urx > $xtop} {set xtop $urx} if {$posturx > $postxtop} {set postxtop $posturx} if {$ury > $ytop} {set ytop $ury} if {$pline <= 0} { if {$xtop != $postxtop} { set smash [expr $xtop - $postxtop - $pitchx] } set corexbot $xbot set corextop $postxtop set coreybot $ybot set coreytop $ytop # puts stdout "At row: smash=$smash corexbot=$corexbot" # puts stdout "xtop=$xtop postxtop=$postxtop pitch=($pitchx, $pitchy)" } } close $fpl2 puts stdout "Limits: xbot = $xbot ybot = $ybot xtop = $xtop ytop = $ytop" # Move cells down and left by the track offset. set cellxbot [expr $cellxbot - $offsetx] set cellybot [expr $cellybot - $offsety] # Also adjust core values to put lower left corner at offsetx,offsety set corextop [expr $offsetx + $corextop - $corexbot] set coreytop [expr $offsety + $coreytop - $coreybot] set corexbot $offsetx set coreybot $offsety puts stdout "Core values: $corexbot $coreybot $corextop $coreytop" puts stdout "Offsets: $offsetx $offsety" # Expand die dimensions by a half pitch in all directions, then snap to # the track grid (assumes that the origin (0, 0) is a track position) set diexbot [expr $xbot - $cellxbot - $halfpitchx] set xgrid [expr floor($diexbot / $pitchx)] set diexbot [expr $xgrid * $pitchx] set dieybot [expr $ybot - $cellybot - $halfpitchy] set ygrid [expr floor($dieybot / $pitchy)] set dieybot [expr $ygrid * $pitchy] set diextop [expr $postxtop - $cellxbot + $halfpitchx] set xgrid [expr floor($diextop / $pitchx)] set diextop [expr $xgrid * $pitchx] set dieytop [expr $ytop - $cellybot + $halfpitchy] set ygrid [expr floor($dieytop / $pitchy)] set dieytop [expr $ygrid * $pitchy] puts $fdef "DIEAREA ( $diexbot $dieybot ) ( $diextop $dieytop ) ;" puts $fdef "" #------------------------------------------------------------------ # Write the tracks (we need to match the coordinate positions. . .) #------------------------------------------------------------------ set width [expr $diextop - $diexbot] set height [expr $dieytop - $dieybot] for {set i 1} {$i <= $numlayers} {incr i} { set mname [subst \$metal${i}(name)] set mpitch [expr 100 * [subst \$metal${i}(pitch)]] if {[subst \$metal${i}(orient)] == "vertical"} { set xtracks [expr 1 + int($width / $mpitch)]; puts $fdef "TRACKS X $diexbot DO $xtracks STEP $mpitch LAYER $mname ;" } else { set ytracks [expr 1 + int($height / $mpitch)]; puts $fdef "TRACKS Y $dieybot DO $ytracks STEP $mpitch LAYER $mname ;" } } puts $fdef "" # diagnostic puts stdout "$numlayers routing layers" set xtracks [expr int($width / $pitchx)]; set ytracks [expr int($height / $pitchy)]; if {$metal1(orient) == "horizontal"} { puts stdout \ "$ytracks horizontal tracks from $dieybot to $dieytop step $pitchy (M1, M3, ...)" puts stdout \ "$xtracks vertical tracks from $diexbot to $diextop step $pitchx (M2, M4, ...)" } else { puts stdout \ "$ytracks horizontal tracks from $dieybot to $dieytop step $pitchy (M2, M4, ...)" puts stdout \ "$xtracks vertical tracks from $diexbot to $diextop step $pitchx (M1, M3, ...)" } # generate obstruction around pin areas, so these will not have vias # dropped on top of the pin labels (convert values to microns) set diexbot_um [expr ($diexbot - $pitchx) / 100.0] set diextop_um [expr ($diextop + $pitchx) / 100.0] set dieybot_um [expr ($dieybot - $pitchy) / 100.0] set dieytop_um [expr ($dieytop + $pitchy) / 100.0] set corexbot_um [expr $corexbot / 100.0] set corextop_um [expr ($corextop + $pitchx) / 100.0] set coreybot_um [expr $coreybot / 100.0] set coreytop_um [expr ($coreytop + $pitchy) / 100.0] # Obstruct all positions in metal1, unless there are only 2 routing layers defined. if {$numlayers > 2} { set mname $metal1(name) # 1. Top puts $fcfg \ "obstruction $diexbot_um $coreytop_um $diextop_um $dieytop_um $mname" # 2. Bottom puts $fcfg \ "obstruction $diexbot_um $dieybot_um $diextop_um $coreybot_um $mname" # 3. Left puts $fcfg \ "obstruction $diexbot_um $dieybot_um $corexbot_um $dieytop_um $mname" # 4. Right puts $fcfg \ "obstruction $corextop_um $dieybot_um $diextop_um $dieytop_um $mname" } # Place obstructions along top and bottom, or left and right, on the layers that # are between pin layers. if {$metal2(orient) == "vertical"} { for {set i 3} {$i <= $numlayers} {incr i 2} { set mname [subst \$metal${i}(name)] # 1. Top puts $fcfg \ "obstruction $corexbot_um $coreytop_um $corextop_um $dieytop_um $mname" # 2. Bottom puts $fcfg \ "obstruction $corexbot_um $dieybot_um $corextop_um $coreybot_um $mname" } for {set i 2} {$i <= $numlayers} {incr i 2} { set mname [subst \$metal${i}(name)] # 3. Left puts $fcfg \ "obstruction $diexbot_um $coreybot_um $corexbot_um $coreytop_um $mname" # 4. Right puts $fcfg \ "obstruction $corextop_um $coreybot_um $diextop_um $coreytop_um $mname" } } else { for {set i 3} {$i <= $numlayers} {incr i 2} { set mname [subst \$metal${i}(name)] # 1. Left puts $fcfg \ "obstruction $diexbot_um $coreybot_um $corexbot_um $coreytop_um $mname" # 2. Right puts $fcfg \ "obstruction $corextop_um $coreybot_um $diextop_um $coreytop_um $mname" } for {set i 2} {$i <= $numlayers} {incr i 2} { set mname [subst \$metal${i}(name)] # 3. Top puts $fcfg \ "obstruction $corexbot_um $coreytop_um $corextop_um $dieytop_um $mname" # 3. Bottom puts $fcfg \ "obstruction $corexbot_um $dieybot_um $corextop_um $coreybot_um $mname" } } # (test) generate blockages between power buses # This gets the router stuck. Too hard! Limit to a small strip in # the middle, enough to ensure placement of a substrate/well contact row. # (This code not relevant to the OSU standard cell set, where power buses # overlap.) set i 1 while {![catch {set yvals($i)}]} { set oddrow [expr {$i % 2}] set y1 [lindex $yvals($i) 0] # if {$oddrow} { # set y2 [expr {$y1 + 196}] # } else { # set y2 [expr {$y1 + 84}] # } set y2 [expr {$y1 + 40}] set y3 [lindex $yvals($i) 1] # if {$oddrow} { # set y4 [expr {$y3 - 84}] # } else { # set y4 [expr {$y3 - 196}] # } set y4 [expr {$y3 - 40}] # puts $fcfg "obstruction $corexbot $y1 $corextop $y2 $metal1(name)" # puts $fcfg "obstruction $corexbot $y4 $corextop $y3 $metal1(name)" incr i } close $fcfg #----------------------------------------------------------------- # Part 2: Components and pins (placed) #----------------------------------------------------------------- #----------------------------------------------------------------- # Pass number 1: Read the .pl1 file and get the number of components and pins #----------------------------------------------------------------- set numpins 0 set numcomps 0 while {[gets $fpl1 line] >= 0} { # We only care about the first word on each line in this pass regexp {^[ \t]*([^ ]+)[ \t]+} $line lmatch instance if {[string equal -length 6 $instance twpin_]} { incr numpins } elseif {![string equal -length 6 $instance twfeed]} { incr numcomps } } close $fpl1 # The .pl1 file always has components first, then pins puts $fdef "COMPONENTS $numcomps ;" #----------------------------------------------------------------- # Pass number 2: Re-read the .pl1 file #----------------------------------------------------------------- set fpl1 [open $pl1name r] set lastrow -1 # Use layers 2 and 3 for pin placement, according to the routing # orientation. For now, we only allow pins on those layers # (need to relax this requirement). If only 2 routing layers are # defined, use the metal1 layer for pins if {$metal2(orient) == "vertical"} { set vlayer $metal2(name) if {$numlayers < 3} { set hlayer $metal1(name) } else { set hlayer $metal3(name) } } else { set hlayer $metal2(name) if {$numlayers < 3} { set vlayer $metal1(name) } else { set vlayer $metal3(name) } } while {[gets $fpl1 line] >= 0} { # Each line in the file is regexp \ {^[ \t]*([^ ]+)[ \t]+([^ ]+)[ \t]+([^ ]+)[ \t]+([^ ]+)[ \t]+([^ ]+)[ \t]+([^ ]+)[ \t]+([^ ]+)} \ $line lmatch instance llx lly urx ury orient row switch $orient { 0 {set ostr "N"} 1 {set ostr "FS"} 2 {set ostr "FN"} 3 {set ostr "S"} 4 {set ostr "FE"} 5 {set ostr "FW"} 6 {set ostr "W"} 7 {set ostr "E"} } if {$lastrow != $row} { set feedoffset 0 } set lastrow $row # Handle the "cells" named "twpin_*" if {[string equal -length 6 $instance twpin_]} { set labname [string range $instance 6 end] if {$row == -1 || $row == -2} { set labtype $hlayer } else { set labtype $vlayer } # Only deal with pin center position set pincx [expr ($llx + $urx) / 2] set pincy [expr ($lly + $ury) / 2] # Reposition the pins to account for feedthrough removal and # cell repositioning set pincx [expr $pincx - $feedoffset - $cellxbot] set pincy [expr $pincy - $cellybot] # Reposition the pins to match track positions. Make pins point labels. # Do NOT offset by (offsetx, offsety) because the offset has been applied # to the cell positions. # set pincx [expr $pincx - $halfpitchx - $offsetx] # set pincy [expr $pincy - $halfpitchy - $offsety] set pincx [expr $pincx - $halfpitchx] set pincy [expr $pincy - $halfpitchy] set xgrid [expr 1 + floor($pincx / $pitchx)] set ygrid [expr 1 + floor($pincy / $pitchy)] # set llx [expr $xgrid * $pitchx + $offsetx] # set lly [expr $ygrid * $pitchy + $offsety] set llx [expr $xgrid * $pitchx] set lly [expr $ygrid * $pitchy] puts $fdef "- $labname + NET $labname" # puts $fdef " + LAYER $labtype ( -14 -14 ) ( 14 14 )" puts $fdef " + LAYER $labtype ( 0 0 ) ( 1 1 )" puts $fdef " + PLACED ( $llx $lly ) N ;" } else { if {[string equal -length 6 $instance twfeed]} { # Ignore the cells named "twfeed*", except to adjust the X offset # of all cells that come after it. incr feedoffset $paramval } else { # Get cellname from instance name. regsub {([^_]+)_[\d]+} $instance {\1} cellname set llxoff [expr $llx - $feedoffset - $cellxbot] set llyoff [expr $lly - $cellybot] puts $fdef "- $instance $cellname + PLACED ( $llxoff $llyoff ) $ostr ;" incr numcomps -1 if {$numcomps == 0} { puts $fdef "END COMPONENTS" puts $fdef "" puts $fdef "PINS $numpins ;" } } } } close $fpl1 #--------------------------------------------------------------------------- # Part 3: Nets (unrouted) #--------------------------------------------------------------------------- # Read a GrayWolf .pin netlist file and produce a DEF netlist file for # use with lithoroute. The routine is the same as place2net2.tcl (for # generating a netlist for the Magic interactive maze router), but the # output format is DEF. #--------------------------------------------------------------------------- set pinfile ${topname}.pin if [catch {open $pinfile r} fpin] { puts stderr "Error: can't open file $pinfile for input" exit 0 } #----------------------------------------------------------------- # Pass #1: Parse the .pin file, and count the total number of nets #----------------------------------------------------------------- set numnets 0 set curnet {} while {[gets $fpin line] >= 0} { regexp {^([^ ]+)[ \t]+} $line lmatch netname if {"$netname" != "$curnet"} { incr numnets set curnet $netname } } puts $fdef "END PINS" puts $fdef "" puts -nonewline $fdef "NETS $numnets " #-------------------------------------------------------------- # Pass #2: Parse the .pin file, writing one line of output for # each line of input. # While we're at it, enumerate the cells used. #-------------------------------------------------------------- set curnet {} set netblock {} set newnet 0 set fpin [open $pinfile r] set maclist {} while {[gets $fpin line] >= 0} { # Each line in the file is: # regexp {^([^ ]+)[ \t]+(\d+)[ \t]+([^ ]+)[ \t]+([^ ]+)[ \t]+([^ ]+)[ \t]+([^ ]+)[ \t]+[^ ]+[ \t]+[^ ]+[ \t]+([^ ]+)} \ $line lmatch netname subnet instance pinname px py layer if {"$netname" != "$curnet"} { set newnet 1 set curnet $netname puts $fdef ";" puts $fdef "- $netname" } if {[string first twfeed ${instance}] == -1} { if {[string first twpin_ ${instance}] == 0} { if {$newnet == 0} { puts $fdef "" ;# end each net component with newline } puts -nonewline $fdef " ( PIN ${pinname} ) " set newnet 0 } elseif {$instance != "PSEUDO_CELL"} { if {$newnet == 0} { puts $fdef "" ;# end each net component with newline } puts -nonewline $fdef " ( ${instance} ${pinname} ) " set newnet 0 regexp {(.+)_[^_]+} $instance lmatch macro lappend maclist $macro } } } puts $fdef ";" puts $fdef "END NETS" puts $fdef "" puts $fdef "END DESIGN" close $fpin close $fdef puts stdout "Done with place2def2.tcl" qflow-1.1.23/scripts/Makefile.in0000664000175000001440000000605612606477746015226 0ustar timusers# # qflow project scripts makefile # # Main compiler arguments CFLAGS = @CFLAGS@ DEFS = @DEFS@ LIBS = @LIBS@ LDFLAGS = @LDFLAGS@ INSTALL = @INSTALL@ VERSION = @VERSION@ REVISION = @REVISION@ QFLOW_LIB_DIR = @QFLOW_LIB_DIR@ QFLOW_BIN_DIR = @QFLOW_BIN_DIR@ TCLSH_PATH = @TCLSH_PATH@ DEFAULTPARSER = @QFLOW_DEFAULT_PARSER@ TCL_SCRIPTS = blif2cel.tcl place2def.tcl place2lef2.tcl TCL_SCRIPTS += place2net2.tcl ypostproc.tcl ybuffer.tcl TCL_SCRIPTS += decongest.tcl addspacers.tcl getfillcell.tcl TCL_SCRIPTS += blifanno.tcl SHELL_SCRIPTS = synthesize.sh placement.sh router.sh vesta.sh SHELL_SCRIPTS += qflow.sh checkdirs.sh SHELL_SCRIPTS += cleanup.sh display.sh createGDS.sh MAIN_SCRIPT = qflow SCRIPTINSTALL = ${QFLOW_LIB_DIR}/scripts TECHINSTALL = ${QFLOW_LIB_DIR}/tech QFLOWEXECPATH = ${QFLOW_LIB_DIR}/bin EXECINSTALL = ${QFLOW_BIN_DIR} all: $(MAIN_SCRIPT).in qflow.sh $(MAKE) launcher launcher: $(MAIN_SCRIPT).in sed -e '/QFLOW_SCRIPT_DIR/s#QFLOW_SCRIPT_DIR#$(SCRIPTINSTALL)#' \ $(MAIN_SCRIPT).in > $(MAIN_SCRIPT) checkdirs.sh: checkdirs.sh.in sed -e '/SUBST_TECH_DIR/s#SUBST_TECH_DIR#$(TECHINSTALL)#' \ -e '/SUBST_SCRIPT_DIR/s#SUBST_SCRIPT_DIR#$(SCRIPTINSTALL)#' \ -e '/SUBST_BIN_DIR/s#SUBST_BIN_DIR#$(QFLOWEXECPATH)#' \ checkdirs.sh.in > checkdirs.sh qflow.sh: qflow.sh.in sed -e '/QFLOW_SCRIPT_DIR/s#QFLOW_SCRIPT_DIR#$(SCRIPTINSTALL)#' \ -e '/QFLOW_DEFAULT_PARSER/s#QFLOW_DEFAULT_PARSER#$(DEFAULTPARSER)#' \ -e '/QFLOW_REVISION/s#QFLOW_REVISION#$(REVISION)#' \ -e '/QFLOW_VERSION/s#QFLOW_VERSION#$(VERSION)#' \ qflow.sh.in > qflow.sh blif2cel.tcl: blif2cel.tcl.in sed -e 's#TCLSH_PATH#$(TCLSH_PATH)#' blif2cel.tcl.in > $@ place2def.tcl: place2def.tcl.in sed -e 's#TCLSH_PATH#$(TCLSH_PATH)#' place2def.tcl.in > $@ place2lef2.tcl: place2def2.tcl.in sed -e 's#TCLSH_PATH#$(TCLSH_PATH)#' place2lef2.tcl.in > $@ place2net2.tcl: place2net2.tcl.in sed -e 's#TCLSH_PATH#$(TCLSH_PATH)#' place2net2.tcl.in > $@ ypostproc.tcl: ypostproc.tcl.in sed -e 's#TCLSH_PATH#$(TCLSH_PATH)#' ypostproc.tcl.in > $@ ybuffer.tcl: ybuffer.tcl.in sed -e 's#TCLSH_PATH#$(TCLSH_PATH)#' ybuffer.tcl.in > $@ decongest.tcl: decongest.tcl.in sed -e 's#TCLSH_PATH#$(TCLSH_PATH)#' decongest.tcl.in > $@ addspacers.tcl: addspacers.tcl.in sed -e 's#TCLSH_PATH#$(TCLSH_PATH)#' addspacers.tcl.in > $@ getfillcell.tcl: getfillcell.tcl.in sed -e 's#TCLSH_PATH#$(TCLSH_PATH)#' getfillcell.tcl.in > $@ blifanno.tcl: blifanno.tcl.in sed -e 's#TCLSH_PATH#$(TCLSH_PATH)#' blifanno.tcl.in > $@ install: $(TCL_SCRIPTS) $(SHELL_SCRIPTS) $(MAIN_SCRIPT) @echo "Installing qflow scripts" $(INSTALL) -d $(DESTDIR)${SCRIPTINSTALL} for target in $(TCL_SCRIPTS); do \ $(INSTALL) $$target $(DESTDIR)${SCRIPTINSTALL} ;\ done for target in $(SHELL_SCRIPTS); do \ $(INSTALL) $$target $(DESTDIR)${SCRIPTINSTALL} ;\ done @echo "Installing qflow executable" $(INSTALL) -d $(DESTDIR)${EXECINSTALL} $(INSTALL) ${MAIN_SCRIPT} $(DESTDIR)${EXECINSTALL} clean: $(RM) $(MAIN_SCRIPT) $(RM) checkdirs.sh $(RM) qflow.sh $(RM) $(TCL_SCRIPTS) uninstall: $(RM) -rf ${SCRIPTINSTALL} $(RM) ${EXECINSTALL}/${MAIN_SCRIPT} qflow-1.1.23/scripts/blif2sim.tcl.in0000775000175000001440000001503412533671313015761 0ustar timusers#!TCLSH_PATH # # Usage: # blif2sim.tcl [] # # If cel_filename is not specified, then name will be the root name # of the .blif file with the .sim extension. # # "dir" is the directory where .sim views of the standard cells are # located. If .sim views are not available but .mag files are, the # .sim files will be generated automatically. # #------------------------------------------------------------ # Written by Tim Edwards February 12, 2007 # MultiGiG, Inc. #------------------------------------------------------------ set bliffile [lindex $argv 0] set cellname [file rootname $bliffile] if {"$cellname" == "$bliffile"} { set bliffile ${cellname}.blif } set prefix "" if {$argc > 2} { if {[lindex $argv [expr {$argc - 2}]] == "-prefix"} { set prefix [lindex $argv [expr {$argc - 1}]]/ incr argc -2 } } if {$argc > 1} { set magdir [lindex $argv 1] } else { set magdir /home/tim/projects/multigig/digital_flow/layout/digital2 } if {$argc == 3} { set simfile [lindex $argv 2] } else { set simfile ${cellname}.sim } set scriptdir [file dirname $argv0] #------------------------------------------------------------- # Open files for read and write if [catch {open $bliffile r} fnet] { puts stderr "Error: can't open file $bliffile for reading!" exit 0 } #---------------------------------------------------------------- # First, parse the contents of the .blif file and get a list # of all macro names used. #---------------------------------------------------------------- puts stdout "1st pass of blif file ${bliffile}. . ." flush stdout set macrolist {} while {[gets $fnet line] >= 0} { if [regexp {^INSTANCE[ \t]+"([^"]+)"} $line lmatch macro] { lappend macrolist $macro } } set macrolist [lsort -unique $macrolist] close $fnet set needsims {} foreach macro $macrolist { if {[glob -nocomplain ${magdir}/${macro}.sim] == {}} { lappend needsims ${macro} } elseif {[file size ${magdir}/${macro}.ext] == 0} { lappend needsims ${macro} } } if {$needsims != {}} { puts stdout "Generating .sim views. . ." flush stdout foreach macro $needsims { puts stdout "Generating ${macro}.sim" flush stdout catch {exec ${scriptdir}/makesim.sh ${magdir}/$macro} } } if [catch {open $simfile w} fsim] { puts stderr "Error: can't open file $simfile for writing!" exit 0 } puts $fsim "| SIM file $simfile generated by blif2sim" #---------------------------------------------------------------- # Procedure to dump the contents of a subcircuit .sim file to the # top-level .sim file, replacing pin names with net names. #---------------------------------------------------------------- proc dump_sim {fsim mode magdir prefix} { # Pick up variable definition from top-level upvar $mode mname # Make VDD, VSS, and GND show up as globals set mname(VDD) VDD set mname(VDD!) VDD set mname(VSS) VSS set mname(VSS!) VSS set mname(GND) GND set mname(GND!) GND set fsub [open ${magdir}/${mode}.sim r] while {[gets $fsub line] >= 0} { set mtype [string index $line 0] # Parse .sim file lines. Ignore lumped "R", which is not used by IRSIM. switch -exact $mtype { n - p { regexp {^[pn] ([^ ]+) ([^ ]+) ([^ ]+) (.*)} $line valid \ gate drain source rest puts -nonewline $fsim "$mtype " if {[catch {puts -nonewline $fsim "${prefix}$mname(${gate}) "}]} { puts -nonewline $fsim "${prefix}${mode}$mname(count)/$gate " } if {[catch {puts -nonewline $fsim "${prefix}$mname(${drain}) "}]} { puts -nonewline $fsim "${prefix}${mode}$mname(count)/$drain " } if {[catch {puts -nonewline $fsim "${prefix}$mname(${source}) "}]} { puts -nonewline $fsim "${prefix}${mode}$mname(count)/$source " } puts $fsim $rest } r { regexp {^r ([^ ]+) ([^ ]+) (.*)} $line valid r1 r2 rest puts -nonewline $fsim "r " if {[catch {puts -nonewline $fsim "${prefix}$mname(${r1}) "}]} { puts -nonewline $fsim "${prefix}${mode}$mname(count)/$r1 " } if {[catch {puts -nonewline $fsim "${prefix}$mname(${r2}) "}]} { puts -nonewline $fsim "${prefix}${mode}$mname(count)/$r2 " } puts $fsim $rest } C { regexp {^C ([^ ]+) ([^ ]+) (.*)} $line valid top bottom rest puts -nonewline $fsim "C " if {[catch {puts -nonewline $fsim "${prefix}$mname(${top}) "}]} { puts -nonewline $fsim "${prefix}${mode}$mname(count)/$top " } if {[catch {puts -nonewline $fsim "${prefix}$mname(${bottom}) "}]} { puts -nonewline $fsim "${prefix}${mode}$mname(count)/$bottom " } puts $fsim $rest } | { puts $fsim $line } } } close $fsub } #---------------------------------------------------------------- # Parse the contents of the .blif file again and dump each cell # instance to the .sim file output. puts stdout "2nd pass of blif file. . ." flush stdout set fnet [open $bliffile r] set mode none while {[gets $fnet line] >= 0} { if [regexp {^INSTANCE[ \t]+"([^"]+)"[ \t]*:[ \t]*"([^"]+)"} $line \ lmatch macroname macrotype] { # New instance. First dump the current instance to the sim file if {$mode != "pins" && $mode != "none"} { dump_sim $fsim $mode $magdir $prefix} # (There is now a valid mag/ext/sim file for TIELO and TIEHI) # if [string equal $macroname TIELO] {gets $fnet line; continue} # if [string equal $macroname TIEHI] {gets $fnet line; continue} set mode $macroname if {[catch {incr ${mode}(count)}]} {set ${mode}(count) 0} } elseif [regexp {^ENDMODEL} $line lmatch] { # Dump last "mode" output if {$mode != "pins"} { dump_sim $fsim $mode $magdir $prefix} } elseif [regexp {^INPUT} $line lmatch] { set mode "pins" } elseif [regexp {^OUTPUT} $line lmatch] { set mode "pins" } elseif [regexp {^MODEL[ \t]+"([^"]+)"} $line lmatch cellverify] { if {"$cellname" != "$cellverify"} { puts -nonewline stderr "WARNING: MODEL name ${cellverify} does not" puts stderr " match filename ${cellname}!" } } elseif {"$mode" == "pins"} { if [regexp {"([^"]+)"[ \t]*:[ \t]*"([^"]+)"} $line lmatch pinname netname] { # Don't do anything with these. } } else { # In the middle of parsing an instance; mode = instance name (in lowercase). if [regexp {"([^"]+)"[ \t]*:[ \t]*"([^"]+)"} $line lmatch pinname netname] { set ${mode}(${pinname}) $netname } } } # Dump the final instance to the sim file, if there was one. if {$mode != "pins" && $mode != "none"} { dump_sim $fsim $mode $magdir $prefix} close $fnet puts stdout "Done!" qflow-1.1.23/scripts/addspacers.tcl.in0000775000175000001440000003121212533671313016357 0ustar timusers#!TCLSH_PATH #--------------------------------------------------------------------------- # addspacers.tcl --- # # Read LEF file and parse for fill cells; get the number and width of # the different fill cells available. # Read the DEF file once, to find the number of rows and the endpoint # of each row. This is not a general purpose script. . . we assume # output is from GrayWolf and place2def, so cells are aligned on # the left, and components appear in order, row by row, from left # to right. # Read the DEF file again, up to the COMPONENTS section. # Modify the COMPONENTS section to add the spacer cells, and write out # the annotated DEF file. # #--------------------------------------------------------------------------- namespace path {::tcl::mathop ::tcl::mathfunc} if {$argc < 3} { puts stdout "Usage: addspacers " exit 0 } puts stdout "Running addspacers.tcl" # NOTE: There is no scaling. GrayWolf values are in centimicrons, # as are DEF values (UNITS DISTANCE MICRONS 100) set topname [file rootname [lindex $argv 0]] set lefname [lindex $argv 1] set fillcell [lindex $argv 2] set defname ${topname}.def set defoutname ${topname}_filled.def set units 100 ;# write centimicron units into the DEF file #----------------------------------------------------------------- # Open all files for reading and writing #----------------------------------------------------------------- if [catch {open $lefname r} flef] { puts stderr "Error: can't open file $lefname for input" return } if [catch {open $defname r} fdef] { puts stderr "Error: can't open file $defname for input" return } #---------------------------------------------------------------- # Read through a LEF file section that we don't care about. #---------------------------------------------------------------- proc skip_section {leffile sectionname} { while {[gets $leffile line] >= 0} { if [regexp {[ \t]*END[ \t]+(.+)[ \t]*$} $line lmatch sectiontest] { if {"$sectiontest" != "$sectionname"} { puts -nonewline stderr "Unexpected END statement $line " puts stderr "while reading section $sectionname" } break } } } #---------------------------------------------------------------- # Parse the macro contents of the LEF file and retain the information # about cell size and pin positions. #---------------------------------------------------------------- proc parse_macro {leffile macroname} { global $macroname units while {[gets $leffile line] >= 0} { if [regexp {[ \t]*SYMMETRY[ \t]+(.+)[ \t]*;} $line lmatch symmetry] { set ${macroname}(symmetry) $symmetry } elseif [regexp {[ \t]*ORIGIN[ \t]+(.+)[ \t]+(.+)[ \t]*;} $line lmatch x y] { set x [expr {int($x * $units)}] set y [expr {int($y * $units)}] set ${macroname}(x) $x set ${macroname}(y) $y } elseif [regexp {[ \t]*SIZE[ \t]+(.+)[ \t]+BY[ \t]+(.+)[ \t]*;} \ $line lmatch w h] { set w [expr {int($w * $units)}] set h [expr {int($h * $units)}] set ${macroname}(w) $w set ${macroname}(h) $h } elseif [regexp {[ \t]*PIN[ \t]+(.+)[ \t]*$} $line lmatch pinname] { # The fill cell is not expected to have any usable pins skip_section $leffile $pinname } elseif [regexp {[ \t]*END[ \t]+(.+)[ \t]*$} $line lmatch macrotest] { if {"$macrotest" == "$macroname"} { break } else { puts stderr "Unexpected END statement $line while reading macro $macroname" } } } } #----------------------------------------------------------------- # Read the lef macro file and get the fill cells and their widths #----------------------------------------------------------------- puts stdout "Reading ${fillcell} macros from LEF file." flush stdout set fillcells {} while {[gets $flef line] >= 0} { if [regexp {[ \t]*MACRO[ \t]+(.+)[ \t]*$} $line lmatch macroname] { # Parse the "macro" statement parse_macro $flef $macroname if {[string first $fillcell $macroname] == 0} { # Remember this for later if it's a fill cell lappend fillcells $macroname } } elseif [regexp {[ \t]*LAYER[ \t]+([^ \t]+)} $line lmatch layername] { skip_section $flef $layername } elseif [regexp {[ \t]*VIA[ \t]+([^ \t]+)} $line lmatch vianame] { skip_section $flef $vianame } elseif [regexp {[ \t]*VIARULE[ \t]+([^ \t]+)} $line lmatch viarulename] { skip_section $flef $viarulename } elseif [regexp {[ \t]*SITE[ \t]+(.+)[ \t]*$} $line lmatch sitename] { skip_section $flef $sitename } elseif [regexp {[ \t]*UNITS[ \t]*$} $line lmatch] { skip_section $flef UNITS } elseif [regexp {[ \t]*SPACING[ \t]*$} $line lmatch] { skip_section $flef SPACING } elseif [regexp {[ \t]*END[ \t]+LIBRARY[ \t]*$} $line lmatch] { break } elseif [regexp {^[ \t]*#} $line lmatch] { # Comment line, ignore. } elseif ![regexp {^[ \t]*$} $line lmatch] { # Other things we don't care about set matches 0 if [regexp {[ \t]*NAMESCASESENSITIVE} $line lmatch] { incr matches } elseif [regexp {[ \t]*VERSION} $line lmatch] { incr matches } elseif [regexp {[ \t]*BUSBITCHARS} $line lmatch] { incr matches } elseif [regexp {[ \t]*DIVIDERCHAR} $line lmatch] { incr matches } elseif [regexp {[ \t]*USEMINSPACING} $line lmatch] { incr matches } elseif [regexp {[ \t]*CLEARANCEMEASURE} $line lmatch] { incr matches } elseif [regexp {[ \t]*MANUFACTURINGGRID} $line lmatch] { incr matches } else { puts stderr "Unexpected input in LEF file: Only macro defs were expected!" puts -nonewline stdout "Line is: $line" flush stdout } } } # If the macro file doesn't define any fill cells, there's not a # whole lot we can do. . . if {[llength $fillcells] == 0} { puts stdout "No fill cells (${fillname}) found in macro file ${lefname}!" exit 1 } #----------------------------------------------------------------- # Parse the COMPONENTS section of the DEF file # Assuming this file was generated by place2def, each component # should be on a single line. #----------------------------------------------------------------- proc parse_components {deffile rows} { upvar $rows rdict while {[gets $deffile line] >= 0} { if [regexp {[ \t]*END[ \t]+(.+)[ \t]*$} $line lmatch sectiontest] { if {"$sectiontest" != "COMPONENTS"} { puts -nonewline stderr "Unexpected END statement $line " puts stderr "while reading section COMPONENTS" } break } elseif [regexp {[ \t]*-[ \t]+([^ \t]+)[ \t]+([^ \t]+)[ \t]+\+[ \t]+PLACED[ \t]+\([ \t]+([^ \t]+)[ \t]+([^ \t]+)[ \t]+\)[ \t]+([^ \t]+)[ \t]+;} $line lmatch \ instance macro px py orient] { if [catch {set row [dict get $rdict $py]}] { dict set rdict $py [list $px $instance $macro $orient] } else { set rowmax [lindex $row 0] if {$px > $rowmax} { dict set rdict $py [list $px $instance $macro $orient] } } } else { puts -nonewline stderr "Unexpected statement $line " puts stderr "while reading section COMPONENTS" } } } #----------------------------------------------------------------- # Read the DEF file once to get the number of rows and the length # of each row #----------------------------------------------------------------- puts stdout "Reading DEF file ${defname}. . ." flush stdout while {[gets $fdef line] >= 0} { if [regexp {[ \t]*COMPONENTS[ \t]+([^ \t]+)[ \t]*;} $line lmatch number] { set rows [dict create] # Parse the "COMPONENTS" statement parse_components $fdef rows } elseif [regexp {[ \t]*NETS[ \t]+([^ \t]+)} $line lmatch netnums] { skip_section $fdef NETS } elseif [regexp {[ \t]*SPECIALNETS[ \t]+([^ \t]+)} $line lmatch netnums] { skip_section $fdef SPECIALNETS } elseif [regexp {[ \t]*PINS[ \t]+([^ \t]+)} $line lmatch pinnum] { skip_section $fdef PINS } elseif [regexp {[ \t]*VIARULE[ \t]+([^ \t]+)} $line lmatch viarulename] { skip_section $fdef $viarulename } elseif [regexp {[ \t]*VIA[ \t]+(.+)[ \t]*$} $line lmatch sitename] { skip_section $fdef $sitename } elseif [regexp {[ \t]*END[ \t]+DESIGN[ \t]*$} $line lmatch] { break } elseif [regexp {^[ \t]*#} $line lmatch] { # Comment line, ignore. } elseif ![regexp {^[ \t]*$} $line lmatch] { # Other things we don't care about set matches 0 if [regexp {[ \t]*NAMESCASESENSITIVE} $line lmatch] { incr matches } elseif [regexp {[ \t]*VERSION} $line lmatch] { incr matches } elseif [regexp {[ \t]*BUSBITCHARS} $line lmatch] { incr matches } elseif [regexp {[ \t]*DIVIDERCHAR} $line lmatch] { incr matches } elseif [regexp {[ \t]*USEMINSPACING} $line lmatch] { incr matches } elseif [regexp {[ \t]*CLEARANCEMEASURE} $line lmatch] { incr matches } elseif [regexp {[ \t]*MANUFACTURINGGRID} $line lmatch] { incr matches } elseif [regexp {[ \t]*UNITS} $line lmatch] { incr matches } elseif [regexp {[ \t]*DESIGN} $line lmatch] { incr matches } elseif [regexp {[ \t]*DIEAREA} $line lmatch] { incr matches } elseif [regexp {[ \t]*TRACKS} $line lmatch] { incr matches } else { puts stderr "Unexpected input in DEF file:" puts stdout "Line is: $line" } } } close $flef close $fdef # Sort array of fill cells by width set fillwidths {} foreach macro $fillcells { lappend fillwidths [list $macro [subst \$${macro}(w)]] } set fillwidths [lsort -decreasing -index 1 $fillwidths] # For each row, add the width of the last cell in that row # to get the row end X value dict for {row rowvals} $rows { set xmax [lindex $rowvals 0] set macro [lindex $rowvals 2] set xmax [+ $xmax [subst \$${macro}(w)]] set rowvals [lreplace $rowvals 0 0 $xmax] dict set rows $row $rowvals } # Find longest row set rowmax 0 dict for {row rowvals} $rows { set xmax [lindex $rowvals 0] if {$xmax > $rowmax} {set rowmax $xmax} } puts stdout "Longest row is width $rowmax" # Now, for each row, find the difference between the row end and row max, # and create a list of how many of each fill macro it takes to fill the # row out to the maximum distance set numfills 0 dict for {row rowvals} $rows { set xmax [lindex $rowvals 0] set xd [- $rowmax $xmax] set fills {} foreach fillset $fillwidths { set fw [lindex $fillset 1] set fn [floor [/ $xd $fw]] lappend fills [list [lindex $fillset 0] [int $fn]] set xd [- $xd [* $fn $fw]] incr numfills [int $fn] } lappend rowvals $fills dict set rows $row $rowvals } set numcomps [+ $number $numfills] # Diagnostic puts stdout "Analysis of DEF file:" puts stdout "Number of components = $number" puts stdout "New number of components = $numcomps" puts stdout "Number of rows = [llength [dict keys $rows]]" set fdef [open $defname r] if [catch {open $defoutname w} fanno] { puts stderr "Error: can't open file $defoutname for output" return } #----------------------------------------------------------------- # Read the DEF file a second time to get the number of rows and the length # of each row #----------------------------------------------------------------- while {[gets $fdef line] >= 0} { if [regexp {[ \t]*COMPONENTS[ \t]+([^ \t]+)[ \t]*;} $line lmatch number] { puts $fanno "COMPONENTS $numcomps ;" set r 0 while {[gets $fdef line] >= 0} { puts $fanno $line if [regexp {[ \t]*END[ \t]+(.+)[ \t]*$} $line lmatch sectiontest] { break } elseif [regexp {[ \t]*-[ \t]+([^ \t]+)[ \t]+([^ \t]+)[ \t]+\+[ \t]+PLACED[ \t]+\([ \t]+([^ \t]+)[ \t]+([^ \t]+)[ \t]+\)[ \t]+([^ \t]+)[ \t]+;} $line lmatch \ instance macro px py orient] { # Check if there is a match to the last instance in the row set rowvals [dict get $rows $py] set rowinst [lindex $rowvals 1] if {[string equal $instance $rowinst]} { incr r set xpos [lindex $rowvals 0] set fills [lindex $rowvals 4] # Get orientation of row (N or S); # remove "F" if last cell was flipped set orient [string index [lindex $rowvals 3] end] foreach fpair $fills { set fmacro [lindex $fpair 0] set fw [subst \$${fmacro}(w)] set fn [lindex $fpair 1] for {set i 1} {$i <= $fn} {incr i} { puts $fanno "- ${fmacro}_${r}_${i} ${fmacro} + PLACED ( $xpos $py ) $orient ;" set xpos [+ $xpos $fw] } } } } } } else { puts $fanno $line } } close $fanno close $fdef puts stdout "Done with addspacers.tcl" qflow-1.1.23/scripts/blifanno.tcl.in0000775000175000001440000001560312533671313016044 0ustar timusers#!TCLSH_PATH #--------------------------------------------------------------------------- # blifanno.tcl --- # # Read a BLIF file and a post-placement DEF file. The placement stage is # assumed to have rewired buffer trees for optimal placement, making the # BLIF file netlist invalid. The contents of the DEF file are used to # back-annotate the correct buffer tree connections to the BLIF netlist. # The output is a corrected BLIF netlist. # #--------------------------------------------------------------------------- namespace path {::tcl::mathop ::tcl::mathfunc} if {$argc < 2} { puts stdout "Usage: blifanno.tcl \[\]" exit 0 } puts stdout "Running blifanno.tcl" # NOTE: There is no scaling. GrayWolf values are in centimicrons, # as are DEF values (UNITS DISTANCE MICRONS 100) set blifinname [lindex $argv 0] set defname [lindex $argv 1] set units 100 ;# write centimicron units into the DEF file #----------------------------------------------------------------- # Open all files for reading and writing #----------------------------------------------------------------- if [catch {open $defname r} fdef] { puts stderr "Error: can't open file $defname for input" return } if [catch {open $blifinname r} fnet] { puts stderr "Error: can't open file $blifinname for input" return } if {$argc == 3} { set blifoutname [lindex $argv 2] if [catch {open $blifoutname w} fout] { puts stderr "Error: can't open file $blifoutname for output" return } } else { set fout stdout } #---------------------------------------------------------------- # Read through a LEF file section that we don't care about. #---------------------------------------------------------------- proc skip_section {leffile sectionname} { while {[gets $leffile line] >= 0} { if [regexp {[ \t]*END[ \t]+(.+)[ \t]*$} $line lmatch sectiontest] { if {"$sectiontest" != "$sectionname"} { puts -nonewline stderr "Unexpected END statement $line " puts stderr "while reading section $sectionname" } break } } } #----------------------------------------------------------------- # Parse the NETS section of the DEF file # Assuming this file was generated by place2def, each net # connection should be on a separate line. #----------------------------------------------------------------- proc parse_nets {deffile nets} { upvar $nets rdict set ignore 0 while {[gets $deffile line] >= 0} { if [regexp {[ \t]*END[ \t]+(.+)[ \t\n]*$} $line lmatch sectiontest] { if {"$sectiontest" == "NETS"} { break } else { puts -nonewline stderr "Unexpected END statement $line " puts stderr "while reading section NETS" } break } elseif [regexp {[ \t]*-[ \t]+([^ \t]+)} $line lmatch netname] { set ignore 0 } elseif [regexp {[ \t]*\+[ \t]+([^ \t]+)} $line lmatch option] { set ignore 1 } elseif {$ignore == 0} { if [regexp {[ \t]*\([ \t]*([^ \t]+)[ \t]+([^ \t]+)[ \t]*\)[ \t\n]*$} \ $line lmatch instname pinname] { dict set rdict ${instname}/${pinname} $netname } } } } #----------------------------------------------------------------- # Read the DEF file once to get the number of rows and the length # of each row #----------------------------------------------------------------- puts stdout "Reading DEF file ${defname}. . ." flush stdout while {[gets $fdef line] >= 0} { if [regexp {[ \t]*COMPONENTS[ \t]+([^ \t]+)[ \t]*;} $line lmatch number] { skip_section $fdef COMPONENTS } elseif [regexp {[ \t]*SPECIALNETS[ \t]+([^ \t]+)} $line lmatch netnums] { skip_section $fdef SPECIALNETS } elseif [regexp {[ \t]*NETS[ \t]+([^ \t]+)} $line lmatch netnums] { set nets [dict create] # Parse the "NETS" section parse_nets $fdef nets # puts stdout "Done with NETS section, dict size is [dict size $nets]" } elseif [regexp {[ \t]*PINS[ \t]+([^ \t]+)} $line lmatch pinnum] { skip_section $fdef PINS } elseif [regexp {[ \t]*VIARULE[ \t]+([^ \t]+)} $line lmatch viarulename] { skip_section $fdef $viarulename } elseif [regexp {[ \t]*VIA[ \t]+(.+)[ \t]*$} $line lmatch sitename] { skip_section $fdef $sitename } elseif [regexp {[ \t]*END[ \t]+DESIGN[ \t]*$} $line lmatch] { break } elseif [regexp {^[ \t]*#} $line lmatch] { # Comment line, ignore. } elseif ![regexp {^[ \t]*$} $line lmatch] { # Other things we don't care about set matches 0 if [regexp {[ \t]*NAMESCASESENSITIVE} $line lmatch] { incr matches } elseif [regexp {[ \t]*VERSION} $line lmatch] { incr matches } elseif [regexp {[ \t]*BUSBITCHARS} $line lmatch] { incr matches } elseif [regexp {[ \t]*DIVIDERCHAR} $line lmatch] { incr matches } elseif [regexp {[ \t]*USEMINSPACING} $line lmatch] { incr matches } elseif [regexp {[ \t]*CLEARANCEMEASURE} $line lmatch] { incr matches } elseif [regexp {[ \t]*MANUFACTURINGGRID} $line lmatch] { incr matches } elseif [regexp {[ \t]*UNITS} $line lmatch] { incr matches } elseif [regexp {[ \t]*DESIGN} $line lmatch] { incr matches } elseif [regexp {[ \t]*DIEAREA} $line lmatch] { incr matches } elseif [regexp {[ \t]*TRACKS} $line lmatch] { incr matches } else { puts stderr "Unexpected input in DEF file:" puts stdout "Line is: $line" } } } close $fdef #----------------------------------------------------------------- # Now read the BLIF netlist, and rewrite all net connections from # the list found in the DEF file #----------------------------------------------------------------- set instcount [dict create] while {[gets $fnet line] >= 0} { if [regexp {^[ \t]*\.gate[ \t]+([^ \t]+)[ \t]+(.*)$} \ $line lmatch macroname rest] { if {[dict exists $instcount $macroname]} { set iidx [dict get $instcount $macroname] incr iidx dict set instcount $macroname $iidx } else { dict set instcount $macroname 1 set iidx 1 } set gateline ".gate $macroname" while {[regexp {[ \t]*([^ \t]+)[ \t]*=[ \t]*([^ \t]+)[ \t]*(.*)$} \ $rest lmatch pinname netname nextconn] > 0} { if {[catch {set newnet [dict get $nets ${macroname}_${iidx}/${pinname}]}]} { # NOTE: Dangling buffer outputs (for debug) do not show up in # graywolf output. They cannot be sorted, so just copy them # as they are in the original blif file. set gateline "${gateline} ${pinname}=${netname}" } else { set gateline "${gateline} ${pinname}=${newnet}" } set rest $nextconn } puts $fout "$gateline" } else { puts $fout $line } } #----------------------------------------------------------------- #----------------------------------------------------------------- close $fnet if {$fout != "stdout"} {close $fout} puts stdout "Done with blifanno.tcl" qflow-1.1.23/scripts/makesim.sh0000755000175000001440000000123212526236535015121 0ustar timusers#!/bin/tcsh -f # # makesim.sh cellname # #--------------------------------------------------------------- # Run magic in batch mode to extract and generate a .sim view # for the argument cellname #--------------------------------------------------------------- if ($#argv < 1) then echo "Usage: makesim.sh " exit 1 endif set magdir=${argv[1]:h} if ("$magdir" == "$argv[1]") then set magdir="." endif set cellname=${argv[1]:t:r} cd $magdir rm -f ${cellname}.ext rm -f ${cellname}.sim /usr/local/bin/magic -dnull -noconsole <" exit 0 } set topname [file rootname [lindex $argv 0]] set pinfile ${topname}.pin set netfile ${topname}.list if [catch {open $pinfile r} fpin] { puts stderr "Error: can't open file $pinfile for input" exit 0 } if [catch {open $netfile w} fnet] { puts stderr "Error: can't open file $netfile for output" exit 0 } #-------------------------------------------------------------- puts -nonewline $fnet " Netlist File" # Parse the .pin file, writing one line of output for each line of input. set curnet {} set netblock {} while {[gets $fpin line] >= 0} { # Each line in the file is: # regexp {^([^ ]+)[ \t]+(\d+)[ \t]+([^ ]+)[ \t]+([^ ]+)[ \t]+([^ ]+)[ \t]+([^ ]+)[ \t]+[^ ]+[ \t]+[^ ]+[ \t]+([^ ]+)} \ $line lmatch netname subnet instance pinname px py layer if {"$netname" != "$curnet"} { set curnet $netname puts $fnet "" } if {[string first twfeed ${instance}] == -1} { if {[string first twpin_ ${instance}] == 0} { puts $fnet ${pinname} } elseif {$instance != "PSEUDO_CELL"} { puts $fnet ${instance}/${pinname} } } } close $fpin close $fnet qflow-1.1.23/scripts/Makefile0000664000175000001440000000663512614150373014603 0ustar timusers# # qflow project scripts makefile # # Main compiler arguments CFLAGS = -g -O2 DEFS = -DPACKAGE_NAME=\"\" -DPACKAGE_TARNAME=\"\" -DPACKAGE_VERSION=\"\" -DPACKAGE_STRING=\"\" -DPACKAGE_BUGREPORT=\"\" -DPACKAGE_URL=\"\" -DSTDC_HEADERS=1 -DHAVE_SETENV=1 -DHAVE_PUTENV=1 -DTCLSH_PATH=\"/bin/tclsh\" -DQFLOW_MAGIC_PATH=\"/usr/local/bin/magic\" -DQFLOW_QROUTER_PATH=\"/usr/local/bin/qrouter\" -DQFLOW_GRAYWOLF_PATH=\"/usr/local/bin/graywolf\" -DQFLOW_YOSYS_PATH=\"/usr/local/bin/yosys\" LIBS = LDFLAGS = INSTALL = /bin/install -c VERSION = 1.1 REVISION = 14 QFLOW_LIB_DIR = /usr/local/share/qflow QFLOW_BIN_DIR = /usr/local/bin TCLSH_PATH = /bin/tclsh DEFAULTPARSER = @QFLOW_DEFAULT_PARSER@ TCL_SCRIPTS = blif2cel.tcl place2def.tcl place2lef2.tcl TCL_SCRIPTS += place2net2.tcl ypostproc.tcl ybuffer.tcl TCL_SCRIPTS += decongest.tcl addspacers.tcl getfillcell.tcl TCL_SCRIPTS += blifanno.tcl SHELL_SCRIPTS = synthesize.sh placement.sh router.sh vesta.sh SHELL_SCRIPTS += qflow.sh checkdirs.sh SHELL_SCRIPTS += cleanup.sh display.sh createGDS.sh MAIN_SCRIPT = qflow SCRIPTINSTALL = ${QFLOW_LIB_DIR}/scripts TECHINSTALL = ${QFLOW_LIB_DIR}/tech QFLOWEXECPATH = ${QFLOW_LIB_DIR}/bin EXECINSTALL = ${QFLOW_BIN_DIR} all: $(MAIN_SCRIPT).in qflow.sh $(MAKE) launcher launcher: $(MAIN_SCRIPT).in sed -e '/QFLOW_SCRIPT_DIR/s#QFLOW_SCRIPT_DIR#$(SCRIPTINSTALL)#' \ $(MAIN_SCRIPT).in > $(MAIN_SCRIPT) checkdirs.sh: checkdirs.sh.in sed -e '/SUBST_TECH_DIR/s#SUBST_TECH_DIR#$(TECHINSTALL)#' \ -e '/SUBST_SCRIPT_DIR/s#SUBST_SCRIPT_DIR#$(SCRIPTINSTALL)#' \ -e '/SUBST_BIN_DIR/s#SUBST_BIN_DIR#$(QFLOWEXECPATH)#' \ checkdirs.sh.in > checkdirs.sh qflow.sh: qflow.sh.in sed -e '/QFLOW_SCRIPT_DIR/s#QFLOW_SCRIPT_DIR#$(SCRIPTINSTALL)#' \ -e '/QFLOW_DEFAULT_PARSER/s#QFLOW_DEFAULT_PARSER#$(DEFAULTPARSER)#' \ -e '/QFLOW_REVISION/s#QFLOW_REVISION#$(REVISION)#' \ -e '/QFLOW_VERSION/s#QFLOW_VERSION#$(VERSION)#' \ qflow.sh.in > qflow.sh blif2cel.tcl: blif2cel.tcl.in sed -e 's#TCLSH_PATH#$(TCLSH_PATH)#' blif2cel.tcl.in > $@ place2def.tcl: place2def.tcl.in sed -e 's#TCLSH_PATH#$(TCLSH_PATH)#' place2def.tcl.in > $@ place2lef2.tcl: place2def2.tcl.in sed -e 's#TCLSH_PATH#$(TCLSH_PATH)#' place2lef2.tcl.in > $@ place2net2.tcl: place2net2.tcl.in sed -e 's#TCLSH_PATH#$(TCLSH_PATH)#' place2net2.tcl.in > $@ ypostproc.tcl: ypostproc.tcl.in sed -e 's#TCLSH_PATH#$(TCLSH_PATH)#' ypostproc.tcl.in > $@ ybuffer.tcl: ybuffer.tcl.in sed -e 's#TCLSH_PATH#$(TCLSH_PATH)#' ybuffer.tcl.in > $@ decongest.tcl: decongest.tcl.in sed -e 's#TCLSH_PATH#$(TCLSH_PATH)#' decongest.tcl.in > $@ addspacers.tcl: addspacers.tcl.in sed -e 's#TCLSH_PATH#$(TCLSH_PATH)#' addspacers.tcl.in > $@ getfillcell.tcl: getfillcell.tcl.in sed -e 's#TCLSH_PATH#$(TCLSH_PATH)#' getfillcell.tcl.in > $@ blifanno.tcl: blifanno.tcl.in sed -e 's#TCLSH_PATH#$(TCLSH_PATH)#' blifanno.tcl.in > $@ install: $(TCL_SCRIPTS) $(SHELL_SCRIPTS) $(MAIN_SCRIPT) @echo "Installing qflow scripts" $(INSTALL) -d $(DESTDIR)${SCRIPTINSTALL} for target in $(TCL_SCRIPTS); do \ $(INSTALL) $$target $(DESTDIR)${SCRIPTINSTALL} ;\ done for target in $(SHELL_SCRIPTS); do \ $(INSTALL) $$target $(DESTDIR)${SCRIPTINSTALL} ;\ done @echo "Installing qflow executable" $(INSTALL) -d $(DESTDIR)${EXECINSTALL} $(INSTALL) ${MAIN_SCRIPT} $(DESTDIR)${EXECINSTALL} clean: $(RM) $(MAIN_SCRIPT) $(RM) checkdirs.sh $(RM) qflow.sh $(RM) $(TCL_SCRIPTS) uninstall: $(RM) -rf ${SCRIPTINSTALL} $(RM) ${EXECINSTALL}/${MAIN_SCRIPT} qflow-1.1.23/scripts/ybuffer.tcl.in0000775000175000001440000001017712533671313015717 0ustar timusers#!TCLSH_PATH #------------------------------------------------------------------------- # ybuffer --- post-process a mapped .blif file generated by yosys # # Note that this file handles mapped blif files ONLY. The only statements # allowed in the file are ".model", ".inputs", ".outputs", ".latch", # ".gate" (or ".subckt"), and ".end". # # All output nets are recorded # Buffers are inserted before each output # The existing output name is appended with "_RAW" and becomes an # internal net. # #------------------------------------------------------------------------- # Written by Tim Edwards October 25, 2013 # Open Circuit Design #------------------------------------------------------------------------- if {$argc < 3} { puts stderr \ "Usage: ybuffer.tcl input_blif_file output_blif_file variables_file" exit 1 } puts stdout "Buffering all outputs of module" set mbliffile [lindex $argv 0] set cellname [file rootname $mbliffile] if {"$cellname" == "$mbliffile"} { set mbliffile ${cellname}.blif } set rootname ${cellname} set outfile [lindex $argv 1] set varsfile [lindex $argv 2] #------------------------------------------------------------- # Open files for read and write if [catch {open $mbliffile r} bnet] { puts stderr "Error: can't open file $mbliffile for reading!" exit 1 } if [catch {open $varsfile r} vfd] { puts stderr "Error: can't open file $varsfile for reading!" exit 1 } if [catch {open $outfile w} onet] { puts stderr "Error: can't open file $outfile for writing!" exit 1 } #------------------------------------------------------------- # The variables file is a UNIX tcsh script, but it can be # processed like a Tcl script if we substitute space for '=' # in the "set" commands. Then all the variables are in Tcl # variable space. #------------------------------------------------------------- while {[gets $vfd line] >= 0} { set tcmd [string map {= \ } $line] eval $tcmd } #------------------------------------------------------------- # Yosys first pass of the blif file # Parse all outputs and remember names. #------------------------------------------------------------- set outputs {} set mode none while {[gets $bnet line] >= 0} { if [regexp {^.outputs[ \t]*(.*)$} $line lmatch rest] { set mode outputs set line $rest } if {$mode == "outputs"} { while {[regexp {^[ \t]*([^ \t]+)(.*)$} $line lmatch signame rest] > 0} { lappend outputs $signame set line $rest } if {![regexp {^\\[ \n\t]*$} $line lmatch]} { set mode none } } } seek $bnet 0 #------------------------------------------------------------- # Now post-process the blif file # The main thing to remember is that internal signals will be # outputs of flops, but external pin names have to be translated # to their internal names by looking at the OUTPUT section. #------------------------------------------------------------- while {[gets $bnet line] >= 0} { if [regexp {^[ \t]*\.gate} $line lmatch] { break } puts $onet $line } # Add buffers foreach signal $outputs { puts $onet " .gate ${bufcell} ${bufpin_in}=${signal}_RAW ${bufpin_out}=${signal}" } # Reorder the outputs in decreasing order, such that outputs that are substrings # of other outputs come after those outputs. That way it will always match to # the longest matching output name. set outputs [lsort -decreasing $outputs] while {1} { # All references to any signal in the output list have "_RAW" appended to the name if [regexp {^[ \t]*\.gate} $line lmatch] { set fidx 0 foreach signal $outputs { while {1} { set sidx [string first ${signal} $line $fidx] if {$sidx < 0} { break } else { set fidx [string first " " $line $sidx] if {$fidx < 0} { if {[expr {[string length $line] - $sidx}] == [string length $signal]} { set line "${line}_RAW" } break } else { if {[expr {$fidx - $sidx}] == [string length $signal]} { set line [string replace $line $fidx $fidx "_RAW "] } } } } } } puts $onet $line if [regexp {^[ \t]*.end} $line lmatch] break if {[gets $bnet line] < 0} break } close $bnet close $onet qflow-1.1.23/scripts/synthesize.sh0000775000175000001440000004266512621423711015707 0ustar timusers#!/bin/tcsh -f # # synthesize.sh: #------------------------------------------------------------------------- # # This script synthesizes verilog files for qflow using yosys # #------------------------------------------------------------------------- # November 2006 # Steve Beccue and Tim Edwards # MultiGiG, Inc. # Scotts Valley, CA # Updated 2013 Tim Edwards # Open Circuit Design #------------------------------------------------------------------------- if ($#argv == 2) then set projectpath=$argv[1] set sourcename=$argv[2] else echo Usage: synthesize.sh echo echo where echo echo is the name of the project directory containing echo a file called qflow_vars.sh. echo echo is the root name of the verilog file, and echo echo Options are set from project_vars.sh. Use the following echo variable names: echo echo $yosys_options for yosys echo $yosys_script for yosys echo $nobuffers to bypass ybuffer echo $fanout_options for blifFanout exit 1 endif set rootname=${sourcename:h} #--------------------------------------------------------------------- # This script is called with the first argument , which should # have file "qflow_vars.sh". Get all of our standard variable definitions # from the qflow_vars.sh file. #--------------------------------------------------------------------- if (! -f ${projectpath}/qflow_vars.sh ) then echo "Error: Cannot find file qflow_vars.sh in path ${projectpath}" exit 1 endif source ${projectpath}/qflow_vars.sh source ${techdir}/${techname}.sh cd ${projectpath} # Reset the logfile rm -f ${synthlog} >& /dev/null touch ${synthlog} # Prepend techdir to libertyfile unless libertyfile begins with "/" set abspath=`echo ${libertyfile} | cut -c1` if ( "${abspath}" == "/" ) then set libertypath=${libertyfile} else set libertypath=${techdir}/${libertyfile} endif # Prepend techdir to spicefile unless spicefile begins with "/" set abspath=`echo ${spicefile} | cut -c1` if ( "${abspath}" == "/" ) then set spicepath=${spicefile} else set spicepath=${techdir}/${spicefile} endif # Prepend techdir to leffile unless leffile begins with "/" set abspath=`echo ${leffile} | cut -c1` if ( "${abspath}" == "/" ) then set lefpath=${leffile} else set lefpath=${techdir}/${leffile} endif #--------------------------------------------------------------------- # Determine hierarchy by running yosys with a simple script to check # hierarchy. Add files until yosys no longer reports an error. # Any error not related to a missing source file causes the script # to rerun yosys and dump error information into the log file, and # exit. #--------------------------------------------------------------------- cd ${sourcedir} set uniquedeplist = "" set yerrcnt = 2 while ($yerrcnt > 1) # Note: While the use of read_liberty to allow structural verilog only # works in yosys 0.3.1 and newer, the following line works for the # purpose of querying the hierarchy in all versions. if ( !( -f ${rootname}.v )) then echo "Error: Verilog source file ${rootname}.v cannot be found!" \ |& tee -a ${synthlog} endif cat > ${rootname}.ys << EOF # Synthesis script for yosys created by qflow read_liberty -lib -ignore_miss_dir -setattr blackbox ${libertypath} read_verilog ${rootname}.v EOF foreach subname ( $uniquedeplist ) if ( !( -f ${subname}.v )) then echo "Error: Verilog source file ${subname}.v cannot be found!" \ |& tee -a ${synthlog} endif echo "read_verilog ${subname}.v" >> ${rootname}.ys end cat >> ${rootname}.ys << EOF # Hierarchy check hierarchy -check EOF set yerrors = `eval ${bindir}/yosys -s ${rootname}.ys |& sed -e "/\\/s#\\#/#g" \ | grep ERROR` set yerrcnt = `echo $yerrors | wc -c` if ($yerrcnt > 1) then set yvalid = `echo $yerrors | grep "referenced in module" | wc -c` if ($yvalid > 1) then set newdep = `echo $yerrors | cut -d " " -f 3 | cut -c3- | cut -d "'" -f 1` set uniquedeplist = "${uniquedeplist} ${newdep}" else ${bindir}/yosys -s ${rootname}.ys >& ${synthlog} echo "Errors detected in verilog source, need to be corrected." \ |& tee -a ${synthlog} echo "See file ${synthlog} for error output." echo "Synthesis flow stopped due to error condition." >> ${synthlog} exit 1 endif endif # end while ($yerrcnt > 1) end #--------------------------------------------------------------------- # Generate the main yosys script #--------------------------------------------------------------------- set blif_opts = "" # Set option for generating buffers set blif_opts = "${blif_opts} -buf ${bufcell} ${bufpin_in} ${bufpin_out}" # Set option for generating only the flattened top-level cell # set blif_opts = "${blif_opts} ${rootname}" # Determine version of yosys set versionstring = `${bindir}/yosys -V | cut -d' ' -f2` set major = `echo $versionstring | cut -d. -f1` set minor = `echo $versionstring | cut -d. -f2` # Sigh. . . versioning doesn't follow any fixed standard set minortest = `echo $minor | cut -d+ -f2` if ( ${minortest} == "" ) then set revisionstring = `echo $versionstring | cut -d. -f3` if ( ${revisionstring} == "" ) set revisionstring = 0 set revision = `echo $revisionstring | cut -d+ -f1` set subrevision = `echo $revisionstring | cut -d+ -f2` if ( ${subrevision} == "" ) set subrevision = 0 else set revision = 0 set minor = `echo $minor | cut -d+ -f1` set subrevision = ${minortest} endif cat > ${rootname}.ys << EOF # Synthesis script for yosys created by qflow EOF # From yosys version 3.0.0+514, structural verilog using cells from the # the same standard cell set that is mapped by abc is supported. if (( ${major} == 0 && ${minor} == 3 && ${revision} == 0 && ${subrevision} >= 514) || \ ( ${major} == 0 && ${minor} == 3 && ${revision} > 0 ) || \ ( ${major} == 0 && ${minor} > 3 ) || \ ( ${major} > 0) ) then cat > ${rootname}.ys << EOF read_liberty -lib -ignore_miss_dir -setattr blackbox ${libertypath} EOF endif cat > ${rootname}.ys << EOF read_liberty -lib -ignore_miss_dir -setattr blackbox ${libertypath} read_verilog ${rootname}.v EOF foreach subname ( $uniquedeplist ) echo "read_verilog ${subname}.v" >> ${rootname}.ys end # Will not support yosys 0.0.x syntax; flag a warning instead if ( ${major} == 0 && ${minor} == 0 ) then echo "Warning: yosys 0.0.x unsupported. Please update!" echo "Output is likely to be incompatible with qflow." endif if ( ${major} == 0 && ${minor} < 5 ) then cat >> ${rootname}.ys << EOF # High-level synthesis hierarchy -top ${rootname} EOF endif if ( ${?yosys_script} ) then if ( -f ${yosys_script} ) then cat ${yosys_script} >> ${rootname}.ys else echo "Error: yosys script ${yosys_script} specified but not found" endif else if ( ${major} != 0 || ${minor} >= 5 ) then cat >> ${rootname}.ys << EOF # High-level synthesis synth -top ${rootname} EOF else cat >> ${rootname}.ys << EOF # High-level synthesis proc; memory; opt; fsm; opt # Map to internal cell library techmap; opt EOF endif cat >> ${rootname}.ys << EOF # Map register flops dfflibmap -liberty ${libertypath} opt EOF if ( ${?abc_script} ) then if ( ${abc_script} != "" ) then cat >> ${rootname}.ys << EOF abc -liberty ${libertypath} -script ${abc_script} flatten EOF else echo "Warning: no abc script ${abc_script}, using default, no script" \ |& tee -a ${synthlog} cat >> ${rootname}.ys << EOF abc -liberty ${libertypath} flatten EOF endif else cat >> ${rootname}.ys << EOF # Map combinatorial cells, standard script abc -liberty ${libertypath} -script +strash;scorr;ifraig;retime,{D};strash;dch,-f;map,-M,1,{D} flatten EOF endif # Purge buffering of internal net name aliases. Option "debug" # retains all internal names by buffering them, resulting in a # larger layout (especially for layouts derived from hierarchical # source), but one in which all signal names from the source can # be probed. if ( ! ${?yosys_debug} ) then cat >> ${rootname}.ys << EOF clean -purge EOF endif # Map tiehi and tielo, if they are defined if ( ${?tiehi} && ${?tiehipin_out} ) then if ( "${tiehi}" != "" ) then echo "hilomap -hicell $tiehi $tiehipin_out" >> ${rootname}.ys endif endif if ( ${?tielo} && ${?tielopin_out} ) then if ( "${tielo}" != "" ) then echo "hilomap -locell $tielo $tielopin_out" >> ${rootname}.ys endif endif # Output buffering, if not specifically prevented if ( ${major} > 0 || ${minor} > 1 ) then if (!($?nobuffers)) then cat >> ${rootname}.ys << EOF # Output buffering iopadmap -outpad ${bufcell} ${bufpin_in}:${bufpin_out} -bits EOF endif endif cat >> ${rootname}.ys << EOF # Cleanup opt clean write_blif ${blif_opts} ${rootname}_mapped.blif EOF #--------------------------------------------------------------------- # Yosys synthesis #--------------------------------------------------------------------- if ( ! ${?yosys_options} ) then set yosys_options = "" endif # Check if "yosys_options" specifies a script to use for yosys. # If not, call yosys with the default script. set usescript = `echo ${yosys_options} | grep -- -s | wc -l` # If there is a file ${rootname}_mapped.blif, move it to a temporary # place so we can see if yosys generates a new one or not. if ( -f ${rootname}_mapped.blif ) then mv ${rootname}_mapped.blif ${rootname}_mapped_orig.blif endif echo "Running yosys for verilog parsing and synthesis" |& tee -a ${synthlog} if ( ${usescript} == 1 ) then eval ${bindir}/yosys ${yosys_options} |& tee -a ${synthlog} else eval ${bindir}/yosys ${yosys_options} -s ${rootname}.ys |& tee -a ${synthlog} endif #--------------------------------------------------------------------- # Spot check: Did yosys produce file ${rootname}_mapped.blif? #--------------------------------------------------------------------- if ( !( -f ${rootname}_mapped.blif )) then echo "outputprep failure: No file ${rootname}_mapped.blif." \ |& tee -a ${synthlog} echo "Premature exit." |& tee -a ${synthlog} echo "Synthesis flow stopped due to error condition." >> ${synthlog} # Replace the old blif file, if we had moved it if ( -f ${rootname}_mapped_orig.blif ) then mv ${rootname}_mapped_orig.blif ${rootname}_mapped.blif endif exit 1 else # Remove the old blif file, if we had moved it if ( -f ${rootname}_mapped_orig.blif ) then rm ${rootname}_mapped_orig.blif endif endif echo "Cleaning up output syntax" |& tee -a ${synthlog} ${scriptdir}/ypostproc.tcl ${rootname}_mapped.blif ${rootname} \ ${techdir}/${techname}.sh #---------------------------------------------------------------------- # Add buffers in front of all outputs (for yosys versions before 0.2.0) #---------------------------------------------------------------------- if ( ${major} == 0 && ${minor} < 2 ) then if ($?nobuffers) then set final_blif = "${rootname}_mapped_tmp.blif" else echo "Adding output buffers" ${scriptdir}/ybuffer.tcl ${rootname}_mapped_tmp.blif \ ${rootname}_mapped_buf.blif ${techdir}/${techname}.sh set final_blif = "${rootname}_mapped_buf.blif" endif else # Buffers already handled within yosys set final_blif = "${rootname}_mapped_tmp.blif" endif #--------------------------------------------------------------------- # The following definitions will replace "LOGIC0" and "LOGIC1" # with buffers from gnd and vdd, respectively. This takes care # of technologies where tie-low and tie-high cells are not # defined. #--------------------------------------------------------------------- echo "Cleaning Up blif file syntax" |& tee -a ${synthlog} if ( "$tielo" == "") then set subs0a="/LOGIC0/s/O=/${bufpin_in}=gnd ${bufpin_out}=/" set subs0b="/LOGIC0/s/LOGIC0/${bufcell}/" else set subs0a="" set subs0b="" endif if ( "$tiehi" == "") then set subs1a="/LOGIC1/s/O=/${bufpin_in}=vdd ${bufpin_out}=/" set subs1b="/LOGIC1/s/LOGIC1/${bufcell}/" else set subs1a="" set subs1b="" endif #--------------------------------------------------------------------- # Remove backslashes, references to "$techmap", and # make local input nodes of the form $0node into the # form node_FF_INPUT #--------------------------------------------------------------------- cat ${final_blif} | sed \ -e "$subs0a" -e "$subs0b" -e "$subs1a" -e "$subs1b" \ -e 's/\\\([^$]\)/\1/g' \ -e 's/$techmap//g' \ -e 's/$0\([^ \t<]*\)<[0-9]*:[0-9]*>\([^ \t]*\)/\1\2_FF_INPUT/g' \ > ${synthdir}/${rootname}.blif # Switch to synthdir for processing of the BDNET netlist cd ${synthdir} #--------------------------------------------------------------------- # Make a copy of the original blif file, as this will be overwritten # by the fanout handling process #--------------------------------------------------------------------- cp ${rootname}.blif ${rootname}_bak.blif #--------------------------------------------------------------------- # Check all gates for fanout load, and adjust gate strengths as # necessary. Iterate this step until all gates satisfy drive # requirements. # # Use option "-o value" to force a value for the (maximum expected) # output load, in fF. Currently, there is no way to do this from the # command line (default is 18fF). . . #--------------------------------------------------------------------- rm -f ${rootname}_nofanout touch ${rootname}_nofanout if ($?gndnet) then echo $gndnet >> ${rootname}_nofanout endif if ($?vddnet) then echo $vddnet >> ${rootname}_nofanout endif if (! $?fanout_options) then set fanout_options="-l 75 -c 25" endif echo "Running blifFanout (iterative)" |& tee -a ${synthlog} echo "" >> ${synthlog} if (-f ${libertypath} && -f ${bindir}/blifFanout ) then set nchanged=1000 while ($nchanged > 0) mv ${rootname}.blif tmp.blif if ("x${separator}" == "x") then set sepoption="" else set sepoption="-s ${separator}" endif if ("x${bufcell}" == "x") then set bufoption="" else set bufoption="-b ${bufcell} -i ${bufpin_in} -o ${bufpin_out}" endif ${bindir}/blifFanout ${fanout_options} -f ${rootname}_nofanout \ -p ${libertypath} ${sepoption} ${bufoption} \ tmp.blif ${rootname}.blif >>& ${synthlog} set nchanged=$status echo "gates resized: $nchanged" |& tee -a ${synthlog} end else set nchanged=0 endif #--------------------------------------------------------------------- # Spot check: Did blifFanout produce an error? #--------------------------------------------------------------------- if ( $nchanged < 0 ) then echo "blifFanout failure. See file ${synthlog} for error messages." \ |& tee -a ${synthlog} echo "Premature exit." |& tee -a ${synthlog} echo "Synthesis flow stopped due to error condition." >> ${synthlog} exit 1 endif echo "" >> ${synthlog} echo "Generating RTL verilog and SPICE netlist file in directory" \ |& tee -a ${synthlog} echo " ${synthdir}" |& tee -a ${synthlog} echo "Files:" |& tee -a ${synthlog} echo " Verilog: ${synthdir}/${rootname}.rtl.v" |& tee -a ${synthlog} echo " Verilog: ${synthdir}/${rootname}.rtlnopwr.v" |& tee -a ${synthlog} echo " Spice: ${synthdir}/${rootname}.spc" |& tee -a ${synthlog} echo "" >> ${synthlog} echo "Running blif2Verilog." |& tee -a ${synthlog} ${bindir}/blif2Verilog -c -v ${vddnet} -g ${gndnet} ${rootname}.blif \ > ${rootname}.rtl.v ${bindir}/blif2Verilog -c -p -v ${vddnet} -g ${gndnet} ${rootname}.blif \ > ${rootname}.rtlnopwr.v echo "Running blif2BSpice." |& tee -a ${synthlog} if ("x${spicefile}" == "x") then set spiceopt="" else set spiceopt="-l ${spicepath}" endif ${bindir}/blif2BSpice -p ${vddnet} -g ${gndnet} ${spiceopt} \ ${rootname}.blif > ${rootname}.spc #--------------------------------------------------------------------- # Spot check: Did blif2Verilog or blif2BSpice exit with an error? # Note that these files are not critical to the main synthesis flow, # so if they are missing, we flag a warning but do not exit. #--------------------------------------------------------------------- if ( !( -f ${rootname}.rtl.v || \ ( -M ${rootname}.rtl.v < -M ${rootname}.blif ))) then echo "blif2Verilog failure: No file ${rootname}.rtl.v created." \ |& tee -a ${synthlog} endif if ( !( -f ${rootname}.rtlnopwr.v || \ ( -M ${rootname}.rtlnopwr.v < -M ${rootname}.blif ))) then echo "blif2Verilog failure: No file ${rootname}.rtlnopwr.v created." \ |& tee -a ${synthlog} endif if ( !( -f ${rootname}.spc || \ ( -M ${rootname}.spc < -M ${rootname}.blif ))) then echo "blif2BSpice failure: No file ${rootname}.spc created." \ |& tee -a ${synthlog} echo "Premature exit." |& tee -a ${synthlog} echo "Synthesis flow stopped due to error condition." >> ${synthlog} exit 1 endif #--------------------------------------------------------------------- # Spot check: Did blif2cel produce file ${rootname}.cel? #--------------------------------------------------------------------- if ( !( -f ${layoutdir}/${rootname}.cel || ( -M ${layoutdir}/${rootname}.cel \ < -M ${rootname}.blif ))) then echo "blif2cel failure: No file ${rootname}.cel." |& tee -a ${synthlog} echo "blif2cel was called with arguments: ${synthdir}/${rootname}.blif " echo " ${lefpath} ${layoutdir}/${rootname}.cel" echo "Premature exit." |& tee -a ${synthlog} echo "Synthesis flow stopped due to error condition." >> ${synthlog} exit 1 endif #--------------------------------------------------------------------- cd ${projectpath} set endtime = `date` echo "Synthesis script ended on $endtime" >> $synthlog qflow-1.1.23/scripts/ypostproc.tcl.in0000775000175000001440000001025012533671313016307 0ustar timusers#!TCLSH_PATH #------------------------------------------------------------------------- # ypostproc --- post-process a mapped .blif file generated by yosys # # Note that this file handles mapped blif files ONLY. The only statements # allowed in the file are ".model", ".inputs", ".outputs", ".latch", # ".gate" (or ".subckt"), and ".end". # # Lines using "$false" or "$true" are replaced with the net names for # power and ground buses in the tech script (to be expanded to handle # TIEHI and TIELO cells, if available in the standard cell set) # #------------------------------------------------------------------------- # Written by Tim Edwards October 8-9, 2013 # Open Circuit Design # Modified for yosys, October 24, 2013 #------------------------------------------------------------------------- if {$argc < 3} { puts stderr \ "Usage: ypostproc.tcl mapped_blif_file root_modname variables_file" exit 1 } puts stdout "Yosys syntax postprocessing" set mbliffile [lindex $argv 0] set cellname [file rootname $mbliffile] if {"$cellname" == "$mbliffile"} { set mbliffile ${cellname}.blif } set outfile ${cellname}_tmp.blif set rootname [lindex $argv 1] set varsfile [lindex $argv 2] #------------------------------------------------------------- # Open files for read and write if [catch {open $mbliffile r} bnet] { puts stderr "Error: can't open file $mbliffile for reading!" exit 1 } if [catch {open $varsfile r} vfd] { puts stderr "Error: can't open file $varsfile for reading!" exit 1 } if [catch {open $outfile w} onet] { puts stderr "Error: can't open file $outfile for writing!" exit 1 } #------------------------------------------------------------- # The variables file is a UNIX tcsh script, but it can be # processed like a Tcl script if we substitute space for '=' # in the "set" commands. Then all the variables are in Tcl # variable space. #------------------------------------------------------------- while {[gets $vfd line] >= 0} { set tcmd [string map {= \ } $line] eval $tcmd } #------------------------------------------------------------- # Yosys first pass of the blif file # Look for all ".names x y" records and remember y as an # alias for x. #------------------------------------------------------------- while {[gets $bnet line] >= 0} { set line [string map {\[ \< \] \>} $line] if [regexp {^.names[ \t]+([^ \t]+)[ \t]+([^ \t]+)[ \t]*$} $line lmatch signame sigalias] { # Technically, should check if the next line is "1 1" but I don't think there are # any exceptions in yosys output. if [catch {set ${signame}(alias)}] { set ${signame}(alias) {} } lappend ${signame}(alias) $sigalias } } seek $bnet 0 #------------------------------------------------------------- # Now post-process the blif file # The main thing to remember is that internal signals will be # outputs of flops, but external pin names have to be translated # to their internal names by looking at the OUTPUT section. #------------------------------------------------------------- set cycle 0 while {[gets $bnet line] >= 0} { set line [string map {\[ \< \] \> \.subckt \.gate} $line] if [regexp {^.gate} $line lmatch] { break } elseif [regexp {^.names} $line lmatch] { break } elseif [regexp {^.latch} $line lmatch] { break } puts $onet $line } # Replace all .latch statements with .gate, with the appropriate gate type and pins, # and copy all .gate statements as-is. while {1} { # All lines starting with ".names" are converted into buffers. These should be # pruned. . . if [regexp {^.names} $line lmatch] { if {[regexp {\$true$} $line lmatch]} { set line [string map [subst {\\\$false $gndnet \\\$true $vddnet}] $line] if [regexp {^.names[ \t]+([^ \t]+)[ \t]+([^ \t]+)[ \t]*$} $line lmatch sigin sigout] { puts $onet ".gate ${bufcell} ${bufpin_in}=${sigin} ${bufpin_out}=${sigout}" } gets $bnet line } } else { set line [string map [subst {\\\$false $gndnet \\\$true $vddnet}] $line] puts $onet $line } if [regexp {^.end} $line lmatch] break if {[gets $bnet line] < 0} break set line [string map {\[ \< \] \> \.subckt \.gate} $line] } close $bnet qflow-1.1.23/scripts/place2lef2.tcl.in0000775000175000001440000000636712533671313016202 0ustar timusers#!TCLSH_PATH #--------------------------------------------------------------------------- # place2lef2.tcl --- # # Read a GrayWolf .pl1 cell placement output file into Magic, using # cells from the LEF database. If there are feedthroughs, then we also # need the .pin file so we know where to draw the two pins of the feedthrough. # # Source this file into Magic and then call function "place2lef " # # Written by Tim Edwards, July 25, 2006, for MultiGiG, Inc. # # Modified from place2lef.tcl: This version assumes the existance of the # LEF views of each digital cell if the LEF file is not specified, and also # does not generate twfeed cells. #--------------------------------------------------------------------------- proc place2lef {topcell {leffile {}} {refdir "."}} { addpath ../digital box values 0 0 0 0 set topname [file rootname $topcell] set pl1name ${refdir}/${topname}.pl1 set pinname ${refdir}/${topname}.pin if [catch {open $pl1name r} fpl1] { puts stderr "Error: can't open file $pl1name for input" return } if {$leffile != {}} { set lefname [file rootname $leffile] if {[file dirname ${lefname}] == "."} { set lefname ${refdir}/${lefname}.lef } else { set lefname ${lefname}.lef } if {[glob -nocomplain -- $lefname] == {}} { set leflist [glob ${refdir}/*.lef] if {[llength $leflist] == 1} { set lefname [lindex $leflist 0] } else { puts stderr "Error: Couldn't find LEF file ${lefname} and" puts stderr "no (or too many) LEF files in reference directory ${refdir}" } } if [catch {lef read $lefname}] { puts stderr "Error reading LEF file ${lefname}" return } } while {[gets $fpl1 line] >= 0} { # Each line in the file is regexp \ {^[ \t]*([^ ]+)[ \t]+([^ ]+)[ \t]+([^ ]+)[ \t]+([^ ]+)[ \t]+([^ ]+)[ \t]+([^ ]+)} \ $line lmatch instance llx lly urx ury orient switch $orient { 0 {set ostr ""} 1 {set ostr "v"} 2 {set ostr "h"} 3 {set ostr "180"} 4 {set ostr "90h"} 5 {set ostr "90v"} 6 {set ostr "270"} 7 {set ostr "90"} } # Handle the "cells" named "twpin_*" if {[string equal -length 6 $instance twpin_]} { set llxnm [expr {$llx * 25}] set llynm [expr {$lly * 25}] set urxnm [expr {$urx * 25}] set urynm [expr {$ury * 25}] set labname [string range $instance 6 end] box size 0.50um 0.50um box position ${llxnm}nm ${llynm}nm box move ne 0.50um paint m2 label $labname n m2 } else { # Ignore the cells named "twfeed*" if {![string equal -length 6 $instance twfeed]} { # Get cellname from instance name. regsub {([^_]+)_[\d]+} $instance {\1} cellname set llxnm [expr {$llx * 25}] set llynm [expr {$lly * 25}] box position ${llxnm}nm ${llynm}nm if {$ostr == ""} { getcell $cellname } else { getcell $cellname $ostr } identify $instance } } } close $fpl1 view select top cell expand } qflow-1.1.23/scripts/checkdirs.sh.in0000755000175000001440000000755612526236535016056 0ustar timusers#!/bin/tcsh -f # #------------------------------------------------------------------------- # checkdirs.sh #------------------------------------------------------------------------- # April 2013 # Tim Edwards, Open Circuit Design #------------------------------------------------------------------------- # # This script searches for technology directories and project directories. # It sets variables associated with each directory for other scripts to # use. # # The directory hierarchy is expected to be set up as follows: # # ----> source/ # ----> synthesis/ # ----> layout/ # ----> tech/ (optional) # # "tech" is optional if the technology is in the qflow install location, # QFLOW_TECH_DIR/ # # Optionally, techfiles may be in subdirectory without the # intervening "tech" directory. i.e., # # ----> # # Optionally, "tech" may point directly to the directory containing techfile # data, i.e., # # ----> tech/ # # If is not specified on the command line, then it is assumed # to be the current working directory. If any standard subdirectories # "source", "synthesis", or "layout" are not found, they will be set to # the project directory. The techfile directory must be found, or # synthesis cannot proceed. # # Source this file using "source" to add variables to the existing shell # environment. # #------------------------------------------------------------------------- # Environment variables override everything else: # QFLOW_TECH_DIR path to technology directory # QFLOW_TECH name of technology # QFLOW_PROJECT_ROOT path to project top level directory # # The second two are checked before calling this routine so # that there are known values for the two arguments passed # to it. if ($#argv != 1 && $#argv != 2) then echo Usage: checkdirs.sh exit 1 endif set techname=${argv[1]} if ($#argv == 2) then set projectpath=${argv[2]} else set projectpath=`pwd` endif #---------------------------------------------------- # Check for standard working directories #---------------------------------------------------- if ( -d ${projectpath}/source ) then set sourcedir=${projectpath}/source else set sourcedir=${projectpath} endif if ( -d ${projectpath}/synthesis ) then set synthdir=${projectpath}/synthesis else set synthdir=${projectpath} endif if ( -d ${projectpath}/layout ) then set layoutdir=${projectpath}/layout else set layoutdir=${projectpath} endif #---------------------------------------------------- # Set variables from install locations here, so we # don't have to do it in every script separately. # Track path to scripts and binaries used by qflow #---------------------------------------------------- set scriptdir=SUBST_SCRIPT_DIR set bindir=SUBST_BIN_DIR #---------------------------------------------------- # Check for the techfile (see comments at top) #---------------------------------------------------- set techdir=`printenv QFLOW_TECH_DIR` if ($techdir != "") then if ( !(-d ${techdir}/${techname}.sh )) then if ( -d ${techdir}/${techname} ) then set techdir=${techdir}/${techname} else set techdir="" endif endif endif if ($techdir != "") then exit 0 endif if ( -d ${projectpath}/tech/${techname} ) then set techdir=${projectpath}/tech/${techname} else if ( -d ${projectpath}/${techname} ) then set techdir=${projectpath}/${techname} else if ( -d ${projectpath}/tech && -r ${projectpath}/tech/${techname}.sh ) then set techdir=${projectpath}/tech else if ( -d SUBST_TECH_DIR/${techname} ) then set techdir=SUBST_TECH_DIR/${techname} else echo "Don't know about technology '${techname}'" echo "Check SUBST_TECH_DIR/ for known technologies" endif endif endif endif exit 0 #---------------------------------------------------- qflow-1.1.23/scripts/createGDS.sh0000775000175000001440000000531012614152167015273 0ustar timusers#!/bin/tcsh -f #---------------------------------------------------------- # Qflow layout GDS generation script using magic-8.0 #---------------------------------------------------------- # Tim Edwards, April 2013 #---------------------------------------------------------- if ($#argv < 2) then echo Usage: display.sh [options] exit 1 endif # Split out options from the main arguments set argline=(`getopt "nr" $argv[1-]`) set options=`echo "$argline" | awk 'BEGIN {FS = "-- "} END {print $1}'` set cmdargs=`echo "$argline" | awk 'BEGIN {FS = "-- "} END {print $2}'` set argc=`echo $cmdargs | wc -w` if ($argc == 2) then set argv1=`echo $cmdargs | cut -d' ' -f1` set argv2=`echo $cmdargs | cut -d' ' -f2` else echo Usage: display.sh [options] echo where echo is the name of the project directory containing echo a file called qflow_vars.sh. echo is the root name of the verilog file, and exit 1 endif set projectpath=$argv1 set sourcename=$argv2 set rootname=${sourcename:h} # This script is called with the first argument , which should # have file "qflow_vars.sh". Get all of our standard variable definitions # from the qflow_vars.sh file. if (! -f ${projectpath}/qflow_vars.sh ) then echo "Error: Cannot find file qflow_vars.sh in path ${projectpath}" exit 1 endif source ${projectpath}/qflow_vars.sh source ${techdir}/${techname}.sh cd ${projectpath} # Prepend techdir to gdsfile unless gdsfile begins with "/" set abspath=`echo ${gdsfile} | cut -c1` if ( "${abspath}" == "/" ) then set gdspath=${gdsfile} else set gdspath=${techdir}/${gdsfile} endif # Prepend techdir to techfile unless techfile begins with "/" set abspath=`echo ${techfile} | cut -c1` if ( "${abspath}" == "/" ) then set techpath=${techfile} else set techpath=${techdir}/${techfile} endif #---------------------------------------------------------- # Done with initialization #---------------------------------------------------------- cd ${layoutdir} #--------------------------------------------------- # Generate GDS from the magic file. This time, # we do not read the LEF file, so that we pick # up the vendor GDS database for the standard # cells. # # Use magic version 8.0 to make nice labels #--------------------------------------------------- ${bindir}/magic -dnull -noconsole -T ${techpath} < exit 1 endif # Split out options from the main arguments set argline=(`getopt "nr" $argv[1-]`) set options=`echo "$argline" | awk 'BEGIN {FS = "-- "} END {print $1}'` set cmdargs=`echo "$argline" | awk 'BEGIN {FS = "-- "} END {print $2}'` set argc=`echo $cmdargs | wc -w` if ($argc >= 2) then set argv1=`echo $cmdargs | cut -d' ' -f1` set argv2=`echo $cmdargs | cut -d' ' -f2` if ($argc == 3) then set statusin = `echo $cmdargs | cut -d' ' -f3` if ($statusin == 2) then echo "Qrouter completed on first iteration, no need to run again." exit 0 endif endif else echo Usage: router.sh [options] echo where echo is the name of the project directory containing echo a file called qflow_vars.sh. echo is the root name of the verilog file exit 1 endif set projectpath=$argv1 set sourcename=$argv2 set rootname=${sourcename:h} # This script is called with the first argument , which should # have file "qflow_vars.sh". Get all of our standard variable definitions # from the qflow_vars.sh file. if (! -f ${projectpath}/qflow_vars.sh ) then echo "Error: Cannot find file qflow_vars.sh in path ${projectpath}" exit 1 endif source ${projectpath}/qflow_vars.sh source ${techdir}/${techname}.sh cd ${projectpath} if (! ${?qrouter_options} ) then set qrouter_options = ${options} endif # Check if last line of log file says "error condition" set errcond = `tail -1 ${synthlog} | grep "error condition" | wc -l` if ( ${errcond} == 1 ) then echo "Synthesis flow stopped on error condition. Detail routing" echo "will not proceed until error condition is cleared." exit 1 endif # Prepend techdir to leffile unless leffile begins with "/" set abspath=`echo ${leffile} | cut -c1` if ( "${abspath}" == "/" ) then set lefpath=${leffile} else set lefpath=${techdir}/${leffile} endif #---------------------------------------------------------- # Done with initialization #---------------------------------------------------------- cd ${layoutdir} #------------------------------------------------------------------ # Determine the version number and availability of scripting #------------------------------------------------------------------ set version=`${bindir}/qrouter -v 0 -h | tail -1` set major=`echo $version | cut -d. -f1` set minor=`echo $version | cut -d. -f2` set subv=`echo $version | cut -d. -f3` set scripting=`echo $version | cut -d. -f4` # If there is a file called (project)_unroute.def, copy it # to the primary .def file to be used by the router. This # overwrites any previously generated route solution. if ( -f ${rootname}_unroute.def ) then cp ${rootname}_unroute.def ${rootname}.def endif if (${scripting} == "T") then #------------------------------------------------------------------ # Scripted qrouter. Given qrouter with Tcl/Tk scripting capability, # create a script to perform the routing. The script will allow # the graphics to display, keep the output to the console at a # minimum, and generate a file with congestion information in the # case of route failure. #------------------------------------------------------------------ echo "Running qrouter $version" ${bindir}/qrouter -noc -s ${rootname}.cfg ${qrouter_options} \ |& tee -a ${synthlog} | \ grep - -e fail -e Progress -e remaining.\*00\$ \ -e remaining:\ \[1-9\]0\\\?\$ else #------------------------------------------------------------------ # Create the detailed route. Monitor the output and print errors # to the output, as well as writing the "commit" line for every # 100th route, so the end-user can track the progress. #------------------------------------------------------------------ echo "Running qrouter $version" ${bindir}/qrouter -c ${rootname}.cfg -p ${vddnet} -g ${gndnet} \ ${qrouter_options} ${rootname} |& tee -a ${synthlog} | \ grep - -e fail -e Progress -e remaining.\*00\$ \ -e remaining:\ \[1-9\]0\\\?\$ endif #--------------------------------------------------------------------- # Spot check: Did qrouter produce file ${rootname}_route.def? #--------------------------------------------------------------------- if ( !( -f ${rootname}_route.def || ( -M ${rootname}_route.def \ < -M ${rootname}.def ))) then echo "qrouter failure: No file ${rootname}_route.def." |& tee -a ${synthlog} echo "Premature exit." |& tee -a ${synthlog} echo "Synthesis flow stopped due to error condition." >> ${synthlog} exit 1 endif #--------------------------------------------------------------------- # If qrouter generated a ".cinfo" file, then annotate the ".cel" # file, re-run placement, and re-run routing. #--------------------------------------------------------------------- if (${scripting} == "T") then if ( -f ${rootname}.cinfo && ( -M ${rootname}.cinfo \ > -M ${rootname}.def )) then ${scriptdir}/decongest.tcl ${rootname} ${lefpath} \ ${fillcell} |& tee -a ${synthlog} endif endif rm ${rootname}.def mv ${rootname}_route.def ${rootname}.def #------------------------------------------------------------ # Done! #------------------------------------------------------------ set endtime = `date` echo "Router script ended on $endtime" >> $synthlog exit 0 qflow-1.1.23/scripts/rtl2sim.tcl.in0000775000175000001440000001703712533671313015653 0ustar timusers#!TCLSH_PATH # # Usage: # rtl2sim.tcl [] # # If cel_filename is not specified, then name will be the root name # of the verilog RTL file with the .sim extension. # # "dir" is the directory where .sim views of the standard cells are # located. If .sim views are not available but .mag files are, the # .sim files will be generated automatically. # #------------------------------------------------------------ # Original bdnet2sim.tcl Written by Tim Edwards February 12, 2007 # Modified for Verilog RTL input, Tim Edwards, April 25, 2011 #------------------------------------------------------------ set rtlfile [lindex $argv 0] set cellname [file rootname $rtlfile] if {"$cellname" == "$rtlfile"} { set rtlfile ${cellname}.rtl.v } set prefix "" if {$argc > 2} { if {[lindex $argv [expr {$argc - 2}]] == "-prefix"} { set prefix [lindex $argv [expr {$argc - 1}]]/ incr argc -2 } } if {$argc > 1} { set magdir [lindex $argv 1] } else { set magdir /home/tim/projects/multigig/digital_flow/layout/digital2 } if {$argc == 3} { set simfile [lindex $argv 2] } else { set simfile ${cellname}.sim } set scriptdir [file dirname $argv0] #------------------------------------------------------------- # Open files for read and write if [catch {open $rtlfile r} fnet] { puts stderr "Error: can't open file $rtlfile for reading!" exit 0 } #---------------------------------------------------------------- # First, parse the contents of the RTL file and get a list # of all macro names used. Use also to get the module name, # which we will use for the .sim file name. #---------------------------------------------------------------- puts stdout "1st pass of RTL file ${rtlfile}. . ." flush stdout set macrolist {} while {[gets $fnet line] >= 0} { if [regexp {^[ \t]*//} $line lmatch] { # Comment line---do nothing } elseif [regexp {^module[ \t]+([^ \t]+)[ \t]*\(} $line lmatch cellverify] { if {"$cellname" != "$cellverify"} { puts -nonewline stderr "WARNING: MODEL name ${cellverify} does not" puts stderr " match filename ${cellname}!" set cellname $cellverify if {$argc != 3} {set simfile ${cellname}.sim} } } elseif [regexp {^[ \t]*([^ \t]+)[ \t]+([^ \t]+)[ \t]+\(} $line lmatch macro inst] { if {"$macro" != "module"} { lappend macrolist $macro } } } set macrolist [lsort -unique $macrolist] close $fnet set needsims {} foreach macro $macrolist { if {[glob -nocomplain ${magdir}/${macro}.sim] == {}} { lappend needsims ${macro} } elseif {[file size ${magdir}/${macro}.ext] == 0} { lappend needsims ${macro} } } if {$needsims != {}} { puts stdout "Generating .sim views. . ." flush stdout foreach macro $needsims { puts stdout "Generating ${macro}.sim" flush stdout catch {exec ${scriptdir}/makesim.sh ${magdir}/$macro} } } if [catch {open $simfile w} fsim] { puts stderr "Error: can't open file $simfile for writing!" exit 0 } puts $fsim "| SIM file $simfile generated by rtl2sim" #---------------------------------------------------------------- # Procedure to dump the contents of a subcircuit .sim file to the # top-level .sim file, replacing pin names with net names. #---------------------------------------------------------------- proc dump_sim {fsim mode magdir prefix} { # Pick up variable definition from top-level upvar $mode mname # Make VDD, VSS, and GND show up as globals set mname(VDD) VDD set mname(VDD!) VDD set mname(VSS) VSS set mname(VSS!) VSS set mname(GND) GND set mname(GND!) GND puts $fsim "| ${mode} $mname(count) = $mname(instance)" set fsub [open ${magdir}/${mode}.sim r] while {[gets $fsub line] >= 0} { set mtype [string index $line 0] # Parse .sim file lines. Ignore lumped "R", which is not used by IRSIM. switch -exact $mtype { n - p { regexp {^[pn] ([^ ]+) ([^ ]+) ([^ ]+) (.*)} $line valid \ gate drain source rest puts -nonewline $fsim "$mtype " if {[catch {puts -nonewline $fsim "${prefix}$mname(${gate}) "}]} { puts -nonewline $fsim "${prefix}$mname(instance)/$gate " } if {[catch {puts -nonewline $fsim "${prefix}$mname(${drain}) "}]} { puts -nonewline $fsim "${prefix}$mname(instance)/$drain " } if {[catch {puts -nonewline $fsim "${prefix}$mname(${source}) "}]} { puts -nonewline $fsim "${prefix}$mname(instance)/$source " } puts $fsim $rest } r { regexp {^r ([^ ]+) ([^ ]+) (.*)} $line valid r1 r2 rest puts -nonewline $fsim "r " if {[catch {puts -nonewline $fsim "${prefix}$mname(${r1}) "}]} { puts -nonewline $fsim "${prefix}$mname(instance)/$r1 " } if {[catch {puts -nonewline $fsim "${prefix}$mname(${r2}) "}]} { puts -nonewline $fsim "${prefix}$mname(instance)/$r2 " } puts $fsim $rest } C { regexp {^C ([^ ]+) ([^ ]+) (.*)} $line valid top bottom rest puts -nonewline $fsim "C " if {[catch {puts -nonewline $fsim "${prefix}$mname(${top}) "}]} { puts -nonewline $fsim "${prefix}$mname(instance)/$top " } if {[catch {puts -nonewline $fsim "${prefix}$mname(${bottom}) "}]} { puts -nonewline $fsim "${prefix}$mname(instance)/$bottom " } puts $fsim $rest } | { puts $fsim $line } } } close $fsub } #---------------------------------------------------------------- # Parse the contents of the RTL file again and dump each cell # instance to the .sim file output. puts stdout "2nd pass of RTL file. . ." flush stdout set fnet [open $rtlfile r] set mode none while {[gets $fnet line] >= 0} { if [regexp {^[ \t]*//} $line lmatch] { # Comment line---do nothing } elseif [regexp {^module[ \t]+([^ \t]+)[ \t]*\(} $line lmatch cellverify] { if {"$cellname" != "$cellverify"} { puts -nonewline stderr "WARNING: MODEL name ${cellverify} does not" puts stderr " match filename ${cellname}!" } } elseif [regexp {^[ \t]*([^ \t]+)[ \t]+([^ \t]+)[ \t]+\((.*)$} $line \ lmatch macroname instname rest] { # New instance. First dump the current instance to the sim file if {$mode != "pins" && $mode != "none" && $mode != "wires"} { dump_sim $fsim $mode $magdir $prefix } set mode $macroname if {[catch {incr ${mode}(count)}]} { set ${mode}(count) 0 } else { # Clear pin assignments so that unconnected outputs don't get shorted # to the last instance set qcount [set ${mode}(count)] array unset ${mode} set ${mode}(count) $qcount } set ${mode}(instance) $instname # parse "rest" for any pin information on the first line while {[regexp {[ \t]*.([^(]+)\(([^) \t]+)[ \t]*\),*(.*)$} $rest \ lmatch pinname netname more] > 0} { # puts stderr "pin: ${mode}(${pinname}) $netname" set ${mode}(${pinname}) $netname set rest $more } } elseif [regexp {^endmodule} $line lmatch] { # Dump last "mode" output if {$mode != "pins"} { dump_sim $fsim $mode $magdir $prefix} } elseif [regexp {^[ \t]*input} $line lmatch] { set mode "pins" } elseif [regexp {^[ \t]*output} $line lmatch] { set mode "pins" } elseif [regexp {^[ \t]*wire} $line lmatch] { set mode "wires" } else { while {[regexp {[ \t]*.([^(]+)\(([^) \t]+)[ \t]*\),*(.*)$} $line \ lmatch pinname netname rest] > 0} { # puts stderr "pin: ${mode}(${pinname}) $netname" set ${mode}(${pinname}) $netname set line $rest } } } # Dump the final instance to the sim file, if there was one. if {$mode != "pins" && $mode != "none"} { dump_sim $fsim $mode $magdir $prefix} close $fnet puts stdout "Done!" qflow-1.1.23/scripts/cleanup.sh0000755000175000001440000000671312526236535015133 0ustar timusers#!/bin/tcsh -f #---------------------------------------------------------- # Workspace cleanup script for qflow #---------------------------------------------------------- # Tim Edwards, April 2013 #---------------------------------------------------------- if ($#argv < 2) then echo Usage: cleanup.sh [options] exit 1 endif # Split out options from the main arguments (no options---this is a placeholder) set argline=(`getopt "" $argv[1-]`) set cmdargs=`echo "$argline" | awk 'BEGIN {FS = "-- "} END {print $2}'` set argc=`echo $cmdargs | wc -w` if ($argc == 2) then set argv1=`echo $cmdargs | cut -d' ' -f1` set argv2=`echo $cmdargs | cut -d' ' -f2` else echo Usage: cleanup.sh echo where echo is the name of the project directory containing echo a file called qflow_vars.sh. echo is the root name of the verilog file, and exit 1 endif foreach option (${argline}) switch (${option}) case --: break endsw end set projectpath=$argv1 set sourcename=$argv2 set rootname=${sourcename:h} # This script is called with the first argument , which should # have file "qflow_vars.sh". Get all of our standard variable definitions # from the qflow_vars.sh file. if (! -f ${projectpath}/qflow_vars.sh ) then echo "Error: Cannot find file qflow_vars.sh in path ${projectpath}" exit 1 endif source ${projectpath}/qflow_vars.sh cd ${projectpath} #---------------------------------------------------------- # Cleanup verilog parsing files. Leave the original source! #---------------------------------------------------------- cd ${layoutdir} # Check if rootname needs a "_buf" suffix, which we use # when AddIO2blif is told to double-buffer the outputs. set origname=${rootname} if ( ! -f ${rootname}.cel && -f ${rootname}_buf.cel ) then set rootname=${rootname}_buf endif cd ${sourcedir} rm -f ${origname}.blif rm -f ${origname}.xml rm -f ${origname}_tmp.blif rm -f ${origname}_mapped.blif rm -f ${origname}_mapped_tmp.blif rm -f ${origname}.clk rm -f ${origname}.enc rm -f ${origname}.init rm -f ${origname}_tmp.v #---------------------------------------------------------- # Clean up files from synthesis. Leave the final buffered # .blif netlist and the RTL verilog files #---------------------------------------------------------- cd ${synthdir} # rm -f ${origname}.blif rm -f ${origname}_bak.blif rm -f ${origname}_tmp.blif rm -f ${rootname}_orig.blif rm -f ${rootname}_nofanout #---------------------------------------------------------- # Clean up the (excessively numerous) GrayWolf files # Keep the input .cel and .par files, and the input # _unroute.def file and the final output .def file. #---------------------------------------------------------- cd ${layoutdir} rm -f ${rootname}.blk ${rootname}.gen ${rootname}.gsav ${rootname}.history rm -f ${rootname}.log ${rootname}.mcel ${rootname}.mdat ${rootname}.mgeo rm -f ${rootname}.mout ${rootname}.mpin ${rootname}.mpth ${rootname}.msav rm -f ${rootname}.mver ${rootname}.mvio ${rootname}.stat ${rootname}.out rm -f ${rootname}.pth ${rootname}.sav ${rootname}.scel rm -f ${rootname}.txt ${rootname}.info rm -f ${rootname}.pin ${rootname}.pl1 ${rootname}.pl2 rm -f ${rootname}.cfg # rm -f ${origname}_unroute.def rm -f cn rm -f failed #------------------------------------------------------------ # Done! #------------------------------------------------------------ qflow-1.1.23/scripts/qflow.in0000755000175000001440000000034412526236535014622 0ustar timusers#!/bin/tcsh -f # #------------------------------------------------------------------ # qflow --- main program launcher #------------------------------------------------------------------ QFLOW_SCRIPT_DIR/qflow.sh $argv exit 0 qflow-1.1.23/scripts/place2def.tcl.in0000775000175000001440000005422312621233301016067 0ustar timusers#!TCLSH_PATH #--------------------------------------------------------------------------- # place2def.tcl --- # # Read a GrayWolf .pl1 cell placement output file, and write a # DEF file of placed COMPONENTS and PINS, and unrouted NETS. # add ROW, TRACKS, and DIEAREA statements, as needed. # # This routine is like place2def2 but turns "twfeed" cells into # fill cells instead of removing them. It should be used when the # standard cell set defines a filler cell. "twfeed" connections in # the .pin file are still ignored, as before. # # Modified 11/23/2013 to include support for the "decongest.tcl" script. # That routine modifies instance names and widths to create a fake cell # incorporating extra fill space that GrayWolf cannot optimize out. # It is then the responsibility of place2def.tcl to split the cell back # into the original cell plus the filler cell in front. #--------------------------------------------------------------------------- if {$argc < 2} { puts -nonewline stdout "Usage: place2def " puts stdout " \[\]" exit 0 } # NOTE: There is no scaling. GrayWolf values are in centimicrons, # as are DEF values (UNITS DISTANCE MICRONS 100) puts stdout "Running place2def.tcl" set topname [lindex $argv 0] set fill_cell [lindex $argv 1] set numlayers 0 if {$argc > 2} { set numlayers [lindex $argv 2] } set pl1name ${topname}.pl1 set pl2name ${topname}.pl2 set pinname ${topname}.pin set defname ${topname}.def set obsname ${topname}.obs set infoname ${topname}.info if [catch {open $pl1name r} fpl1] { puts stderr "Error: can't open file $pl1name for input" return } if [catch {open $pl2name r} fpl2] { puts stderr "Error: can't open file $pl2name for input" return } if [catch {open $defname w} fdef] { puts stderr "Error: can't open file $defname for output" return } if [catch {open $obsname w} fobs] { puts stderr "Error: can't open file $obsname for output" return } #----------------------------------------------------------------- # DEF file header #----------------------------------------------------------------- puts $fdef "VERSION 5.6 ;" puts $fdef "NAMESCASESENSITIVE ON ;" puts $fdef "DIVIDERCHAR \"/\" ;" puts $fdef "BUSBITCHARS \"<>\" ;" puts $fdef "DESIGN $topname ;" puts $fdef "UNITS DISTANCE MICRONS 100 ;" puts $fdef "" #----------------------------------------------------------------- # Part 1: Area and routing tracks #----------------------------------------------------------------- #----------------------------------------------------------------- # Read the .pl2 file and get the full die area (components only) #----------------------------------------------------------------- # If a number of route layers wasn't specified in the project_vars.sh # script, then use the number of layers defined in the config file. if [catch {open $infoname r} finf] { puts stdout "Warning: No file $infoname generated, using defaults." set pitchx 160 set pitchy 200 set offsetx 80 set offsety 100 set widthx 160 set widthy 200 set numlayers 3 for {set i 1} {$i <= $numlayers} {incr i 2} { set metal${i}(name) metal${i} set metal${i}(pitch) $pitchx set metal${i}(orient) horizontal set metal${i}(offset) $offsetx set metal${i}(width) $widthx set metal${i}(skip) 1 } for {set i 2} {$i <= $numlayers} {incr i 2} { set metal${i}(name) metal${i} set metal${i}(pitch) $pitchy set metal${i}(orient) vertical set metal${i}(offset) $offsety set metal${i}(width) $widthy set metal${i}(skip) 1 } } else { set i 0 while {[gets $finf line] >= 0} { # Versions of qrouter since 1.2.3 provide version information, including # whether or not qrouter was compiled with Tcl/Tk and supports scripting if {![regexp {qrouter ([0-9]+)\.([0-9]+)\.([0-9]+)(.*)} $line lmatch \ major minor subv rest]} { # Older versions of qrouter assumed a track offset of 1/2 track pitch. # Newer versions correctly take the offset from the LEF file and dump the # value to the info file. Also the newer version records the track width, # although this is not used. if {[regexp {^[ \t]*([^ ]+)[ \t]+([^ ]+)[ \t]+([^ ]+)[ \t]+([^ ]+)[ \t]+([^ ]+)(.*)} \ $line lmatch layer pitch offset width orient rest] <= 0} { regexp {^[ \t]*([^ ]+)[ \t]+([^ ]+)[ \t]+([^ ]+)} $line lmatch \ layer pitch orient set offset [expr 0.5 * $pitch] set width $pitch set skip 1 } if {![regexp {[ \t]*([^ ]+)} $rest lmatch skip]} { set skip 1 } incr i set metal${i}(name) $layer set metal${i}(pitch) $pitch set metal${i}(orient) $orient set metal${i}(offset) $offset set metal${i}(width) $width set metal${i}(skip) $skip } } close $finf if {($numlayers == 0) || ($numlayers > $i)} {set numlayers $i} } # NOTE: Treating all pitches the same for all layers in the same # direction. This is good for doing various calculations on cell # and pin positions. The track positions themselves will be placed # according to the given route layer pitch. if {$metal1(orient) == "horizontal"} { set pitchx [expr 100 * $metal2(pitch)] set pitchy [expr 100 * $metal1(pitch)] set offsetx [expr 100 * $metal2(offset)] set offsety [expr 100 * $metal1(offset)] set widthx [expr 100 * $metal2(width)] set widthy [expr 100 * $metal1(width)] } else { set pitchx [expr 100 * $metal1(pitch)] set pitchy [expr 100 * $metal2(pitch)] set offsetx [expr 100 * $metal1(offset)] set offsety [expr 100 * $metal2(offset)] set widthx [expr 100 * $metal1(width)] set widthy [expr 100 * $metal2(width)] } # Add numlayers to the configuration file now that we know it set halfpitchx [expr $pitchx / 2]; set halfpitchy [expr $pitchy / 2]; set halfwidthx [expr $widthx / 2]; set halfwidthy [expr $widthy / 2]; set xbot 1000 set ybot 1000 set cellxbot 1000 set cellybot 1000 set xtop 0 set ytop 0 while {[gets $fpl2 line] >= 0} { regexp {^[ \t]*([^ ]+)[ \t]+([^ ]+)[ \t]+([^ ]+)[ \t]+([^ ]+)[ \t]+([^ ]+)[ \t]+[^ ]+[ \t]+([^ ]+)} \ $line lmatch rowidx llx lly urx ury align set pline [regexp {^[ \t]*twpin} $line lmatch] if {$pline > 0} { # Re-align pins to the nearest track pitch. Set pin size to be # equal to a route width. set pincx [expr ($llx + $urx) / 2] set pincy [expr ($lly + $ury) / 2] set pincx [expr $pincx - $halfpitchx - $offsetx] set pincy [expr $pincy - $halfpitchy - $offsety] set xgrid [expr 1 + floor($pincx / $pitchx)] set ygrid [expr 1 + floor($pincy / $pitchy)] set pincx [expr $xgrid * $pitchx + $offsetx] set pincy [expr $ygrid * $pitchy + $offsety] set llx [expr $pincx - $halfwidthx] set lly [expr $pincy - $halfwidthy] set urx [expr $pincx + $halfwidthx] set ury [expr $pincy + $halfwidthy] } else { set yvals($rowidx) [list $lly $ury] if {$llx < $cellxbot} {set cellxbot $llx} if {$lly < $cellybot} {set cellybot $lly} } if {$llx < $xbot} {set xbot $llx} if {$lly < $ybot} {set ybot $lly} if {$urx > $xtop} {set xtop $urx} if {$ury > $ytop} {set ytop $ury} if {$pline <= 0} { set corexbot $xbot set corextop $xtop set coreybot $ybot set coreytop $ytop } } close $fpl2 puts stdout "Limits: xbot = $xbot ybot = $ybot xtop = $xtop ytop = $ytop" # Move cells down and left by the track offset. set cellxbot [expr $cellxbot - $offsetx] set cellybot [expr $cellybot - $offsety] # Also adjust core values to put lower left corner at offsetx,offsety set corextop [expr $offsetx + $corextop - $corexbot] set coreytop [expr $offsety + $coreytop - $coreybot] set corexbot $offsetx set coreybot $offsety puts stdout "Core values: $corexbot $coreybot $corextop $coreytop" puts stdout "Offsets: $offsetx $offsety" # Expand die dimensions by a half pitch in all directions, then snap to # the track grid (assumes that the origin (0, 0) is a track position) set diexbot [expr $xbot - $cellxbot - $halfpitchx] set xgrid [expr floor($diexbot / $pitchx)] set diexbot [expr $xgrid * $pitchx] set dieybot [expr $ybot - $cellybot - $halfpitchy] set ygrid [expr floor($dieybot / $pitchy)] set dieybot [expr $ygrid * $pitchy] set diextop [expr $xtop - $cellxbot + $halfpitchx] set xgrid [expr floor($diextop / $pitchx)] set diextop [expr $xgrid * $pitchx] set dieytop [expr $ytop - $cellybot + $halfpitchy] set ygrid [expr floor($dieytop / $pitchy)] set dieytop [expr $ygrid * $pitchy] puts $fdef "DIEAREA ( $diexbot $dieybot ) ( $diextop $dieytop ) ;" puts $fdef "" #------------------------------------------------------------------ # Write the tracks (we need to match the coordinate positions. . .) #------------------------------------------------------------------ set width [expr $diextop - $diexbot] set height [expr $dieytop - $dieybot] for {set i 1} {$i <= $numlayers} {incr i} { set mname [subst \$metal${i}(name)] set mpitch [expr 100 * [subst \$metal${i}(pitch)]] if {[subst \$metal${i}(orient)] == "vertical"} { set xtracks [expr 1 + int($width / $mpitch)]; puts $fdef "TRACKS X $diexbot DO $xtracks STEP $mpitch LAYER $mname ;" } else { set ytracks [expr 1 + int($height / $mpitch)]; puts $fdef "TRACKS Y $dieybot DO $ytracks STEP $mpitch LAYER $mname ;" } } puts $fdef "" # diagnostic puts stdout "$numlayers routing layers" set xtracks [expr int($width / $pitchx)]; set ytracks [expr int($height / $pitchy)]; if {$metal1(orient) == "horizontal"} { puts stdout \ "$ytracks horizontal tracks from $dieybot to $dieytop step $pitchy (M1, M3, ...)" puts stdout \ "$xtracks vertical tracks from $diexbot to $diextop step $pitchx (M2, M4, ...)" } else { puts stdout \ "$ytracks horizontal tracks from $dieybot to $dieytop step $pitchy (M2, M4, ...)" puts stdout \ "$xtracks vertical tracks from $diexbot to $diextop step $pitchx (M1, M3, ...)" } # generate obstruction around pin areas, so these will not have vias # dropped on top of the pin labels (convert values to microns) set diexbot_um [expr ($diexbot - $pitchx) / 100.0] set diextop_um [expr ($diextop + $pitchx) / 100.0] set dieybot_um [expr ($dieybot - $pitchy) / 100.0] set dieytop_um [expr ($dieytop + $pitchy) / 100.0] set corexbot_um [expr $corexbot / 100.0] set corextop_um [expr ($corextop + $pitchx) / 100.0] set coreybot_um [expr $coreybot / 100.0] set coreytop_um [expr ($coreytop + $pitchy) / 100.0] #----------------------------------------------------------------- # Finish route configuration file #----------------------------------------------------------------- # Obstruct all positions in metal1, unless there are only 2 routing layers defined. # (This syntax is common to the Tcl and non-Tcl versions of qrouter) if {$numlayers > 2} { set mname $metal1(name) # 1. Top puts $fobs \ "obstruction $diexbot_um $coreytop_um $diextop_um $dieytop_um $mname" # 2. Bottom puts $fobs \ "obstruction $diexbot_um $dieybot_um $diextop_um $coreybot_um $mname" # 3. Left puts $fobs \ "obstruction $diexbot_um $dieybot_um $corexbot_um $dieytop_um $mname" # 4. Right puts $fobs \ "obstruction $corextop_um $dieybot_um $diextop_um $dieytop_um $mname" } # Place obstructions along top and bottom, or left and right, on the layers that # are between pin layers. if {$metal2(orient) == "vertical"} { for {set i 3} {$i <= $numlayers} {incr i 2} { set mname [subst \$metal${i}(name)] # 1. Top puts $fobs \ "obstruction $corexbot_um $coreytop_um $corextop_um $dieytop_um $mname" # 2. Bottom puts $fobs \ "obstruction $corexbot_um $dieybot_um $corextop_um $coreybot_um $mname" } for {set i 2} {$i <= $numlayers} {incr i 2} { set mname [subst \$metal${i}(name)] # 3. Left puts $fobs \ "obstruction $diexbot_um $coreybot_um $corexbot_um $coreytop_um $mname" # 4. Right puts $fobs \ "obstruction $corextop_um $coreybot_um $diextop_um $coreytop_um $mname" } } else { for {set i 3} {$i <= $numlayers} {incr i 2} { set mname [subst \$metal${i}(name)] # 1. Left puts $fobs \ "obstruction $diexbot_um $coreybot_um $corexbot_um $coreytop_um $mname" # 2. Right puts $fobs \ "obstruction $corextop_um $coreybot_um $diextop_um $coreytop_um $mname" } for {set i 2} {$i <= $numlayers} {incr i 2} { set mname [subst \$metal${i}(name)] # 3. Top puts $fobs \ "obstruction $corexbot_um $coreytop_um $corextop_um $dieytop_um $mname" # 3. Bottom puts $fobs \ "obstruction $corexbot_um $dieybot_um $corextop_um $coreybot_um $mname" } } # (test) generate blockages between power buses # This gets the router stuck. Too hard! Limit to a small strip in # the middle, enough to ensure placement of a substrate/well contact row. # (This code not relevant to the OSU standard cell set, where power buses # overlap.) set i 1 while {![catch {set yvals($i)}]} { set oddrow [expr {$i % 2}] set y1 [lindex $yvals($i) 0] # if {$oddrow} { # set y2 [expr {$y1 + 196}] # } else { # set y2 [expr {$y1 + 84}] # } set y2 [expr {$y1 + 40}] set y3 [lindex $yvals($i) 1] # if {$oddrow} { # set y4 [expr {$y3 - 84}] # } else { # set y4 [expr {$y3 - 196}] # } set y4 [expr {$y3 - 40}] # puts $fobs "obstruction $corexbot $y1 $corextop $y2 $metal1(name)" # puts $fobs "obstruction $corexbot $y4 $corextop $y3 $metal1(name)" incr i } close $fobs #----------------------------------------------------------------- # Part 2: Components and pins (placed) #----------------------------------------------------------------- #----------------------------------------------------------------- # Pass number 1: Read the .pl1 file and get the number of components and pins #----------------------------------------------------------------- set numpins 0 set numcomps 0 while {[gets $fpl1 line] >= 0} { # We only care about the first word on each line in this pass regexp {^[ \t]*([^ ]+)[ \t]+} $line lmatch instance if {[string equal -length 6 $instance twpin_]} { incr numpins } else { incr numcomps if [regexp {^[ \t]*[^ \t.]+\.([^ \t.]+)\.[^ \t.]+[ \t]+} $line lmatch fsize] { if [regexp {[0-9]+X([0-9]+)} $fsize lmatch fmult] { incr numcomps $fmult } else { incr numcomps } } } } close $fpl1 # The .pl1 file always has components first, then pins puts $fdef "COMPONENTS $numcomps ;" #----------------------------------------------------------------- # Pass number 2: Re-read the .pl1 file #----------------------------------------------------------------- set fpl1 [open $pl1name r] set lastrow -1 # Use layers 2 and 3 for pin placement, according to the routing # orientation. For now, we only allow pins on those layers # (need to relax this requirement). If only 2 routing layers are # defined, use the metal1 layer for pins if {$metal2(orient) == "vertical"} { set vlayer $metal2(name) set hskip $metal2(skip) if {$numlayers < 3} { set hlayer $metal1(name) set vskip $metal1(skip) } else { set hlayer $metal3(name) set vskip $metal3(skip) } } else { set hlayer $metal2(name) set vskip $metal2(skip) if {$numlayers < 3} { set vlayer $metal1(name) set hskip $metal1(skip) } else { set vlayer $metal3(name) set hskip $metal3(skip) } } while {[gets $fpl1 line] >= 0} { # Each line in the file is regexp \ {^[ \t]*([^ ]+)[ \t]+([^ ]+)[ \t]+([^ ]+)[ \t]+([^ ]+)[ \t]+([^ ]+)[ \t]+([^ ]+)[ \t]+([^ ]+)} \ $line lmatch instance llx lly urx ury orient row switch $orient { 0 {set ostr "N"} 1 {set ostr "FS"} 2 {set ostr "FN"} 3 {set ostr "S"} 4 {set ostr "FE"} 5 {set ostr "FW"} 6 {set ostr "W"} 7 {set ostr "E"} } set lastrow $row # Handle the "cells" named "twpin_*" if {[string equal -length 6 $instance twpin_]} { set labname [string range $instance 6 end] if {$row == -1 || $row == -2} { set labtype $hlayer set pinpitchx $pitchx set pinpitchy [expr $vskip * $pitchy] } else { set labtype $vlayer set pinpitchx [expr $hskip * $pitchx] set pinpitchy $pitchy } # Only deal with pin center position set pincx [expr ($llx + $urx) / 2] set pincy [expr ($lly + $ury) / 2] set pincx [expr $pincx - $cellxbot] set pincy [expr $pincy - $cellybot] # Reposition the pins to match track positions. Make pins point labels. # Do NOT offset by (offsetx, offsety) because the offset has been applied # to the cell positions. GrayWolf may violate track pitch, so record # positions used and avoid overlap. set pincx [expr $pincx - $halfpitchx] set pincy [expr $pincy - $halfpitchy] set xgrid [expr 1 + floor($pincx / $pinpitchx)] set ygrid [expr 1 + floor($pincy / $pinpitchy)] set llx [expr $xgrid * $pinpitchx] set lly [expr $ygrid * $pinpitchy] while {![catch {eval [subst {set posused(${llx},${lly})}]}]} { puts -nonewline stdout "Caught GrayWolf being bad: " puts stdout "Pin $labname overlaps pin $posused(${llx},${lly})" if {$row == -1 || $row == -2} { set lly [expr $lly + $pinpitchy] } else { set llx [expr $llx + $pinpitchx] } } set posused(${llx},${lly}) $labname puts $fdef "- $labname + NET $labname" puts $fdef " + LAYER $labtype ( 0 0 ) ( 1 1 )" puts $fdef " + PLACED ( $llx $lly ) N ;" } else { if {[string equal -length 6 $instance twfeed]} { # Replace twfeed with name of filler cell set cellname ${fill_cell} } else { # Pull out the fill cell if one was spliced into # the component name if [regexp {([^ \t.]+)\.([^ \t.]+)\.([^ \t.]+)} $instance \ lmatch fillcell fillwidth baseinst] { if {![regexp {([0-9]+)X([0-9]+)} $fillwidth lmatch fillnom fmult]} { set fillnom $fillwidth set fmult 1 } set cellname $fillcell set instance $baseinst set fillname $cellname set llyoff [expr $lly - $cellybot] for {set i 0} {$i < $fmult} {incr i} { set llxoff [expr $llx - $cellxbot] puts $fdef "- ${fillname}_$baseinst $cellname + PLACED ( $llxoff $llyoff ) $ostr ;" incr numcomps -1 set llx [expr $llx + $fillnom] set fillname "${cellname}$i" } } # Get cellname from instance name. regsub {(.+)_[\d]+$} $instance {\1} cellname } set llxoff [expr $llx - $cellxbot] set llyoff [expr $lly - $cellybot] puts $fdef "- $instance $cellname + PLACED ( $llxoff $llyoff ) $ostr ;" incr numcomps -1 if {$numcomps == 0} { puts $fdef "END COMPONENTS" puts $fdef "" puts $fdef "PINS $numpins ;" } } } close $fpl1 #--------------------------------------------------------------------------- # Part 3: Nets (unrouted) #--------------------------------------------------------------------------- # Read a GrayWolf .pin netlist file and produce a DEF netlist file for # use with lithoroute. The routine is the same as place2net2.tcl (for # generating a netlist for the Magic interactive maze router), but the # output format is DEF. #--------------------------------------------------------------------------- set pinfile ${topname}.pin if [catch {open $pinfile r} fpin] { puts stderr "Error: can't open file $pinfile for input" exit 0 } #----------------------------------------------------------------- # Pass #1: Parse the .pin file, and count the total number of nets #----------------------------------------------------------------- set numnets 0 set curnet {} while {[gets $fpin line] >= 0} { regexp {^([^ ]+)[ \t]+} $line lmatch netname if {"$netname" != "$curnet"} { incr numnets set curnet $netname } } puts $fdef "END PINS" puts $fdef "" puts -nonewline $fdef "NETS $numnets " #-------------------------------------------------------------- # Pass #2: Parse the .pin file, writing one line of output for # each line of input. # While we're at it, enumerate the cells used. #-------------------------------------------------------------- set curnet {} set netblock {} set newnet 0 set fpin [open $pinfile r] set maclist {} set lastinst "" set lastpin "" set skip 0 while {[gets $fpin line] >= 0} { # Each line in the file is: # regexp {^([^ ]+)[ \t]+(\d+)[ \t]+([^ ]+)[ \t]+([^ ]+)[ \t]+([^ ]+)[ \t]+([^ ]+)[ \t]+[^ ]+[ \t]+[^ ]+[ \t]+([^ ]+)} \ $line lmatch netname subnet instance pinname px py layer if {"$netname" != "$curnet"} { set newnet 1 set curnet $netname puts $fdef ";" puts $fdef "- $netname" } # Rip the filler cell name off the beginning of instances where # they were spliced in if [regexp {([^ \t.]+)\.([^ \t.]+)\.([^ \t.]+)} $instance \ lmatch fillcell fillwidth baseinst] { set instance $baseinst } if {([string first twfeed ${instance}] == -1) && ([string first twfeed ${pinname}] != 0)} { if {[string first twpin_ ${instance}] == 0} { if {$newnet == 0} { puts $fdef "" ;# end each net component with newline } puts -nonewline $fdef " ( PIN ${pinname} ) " set newnet 0 } elseif {$instance != "PSEUDO_CELL"} { # If pinname contains "bF$pin/", pin name follows this text if {[regexp {.+bF\$pin/(.*)$} $pinname lmatch shortname]} { set pinname $shortname } # Avoid output for redundant entries generated by graywolf for # pins it wants to route through both top and bottom. if {"${lastinst}" == "${instance}" && "${lastpin}" == "${pinname}"} { set skip 1 } else { set skip 0 set lastinst $instance set lastpin $pinname } if {$newnet == 0 && $skip == 0} { puts $fdef "" ;# end each net component with newline } # Avoid output for redundant entries generated by graywolf for # pins it wants to route through both top and bottom. if {$skip == 0} { puts -nonewline $fdef " ( ${instance} ${pinname} ) " } set newnet 0 regexp {(.+)_[^_]+} $instance lmatch macro lappend maclist $macro } } } puts $fdef ";" puts $fdef "END NETS" puts $fdef "" puts $fdef "END DESIGN" close $fpin close $fdef puts stdout "Done with place2def.tcl" qflow-1.1.23/scripts/temp.txt0000775000175000001440000000422612614667460014660 0ustar timusers#------------------------------------------------------------------------- # Create the .cel file for GrayWolf #------------------------------------------------------------------------- cd ${projectpath} echo "Running blif2cel.tcl" |& tee -a ${synthlog} ${scriptdir}/blif2cel.tcl ${synthdir}/${rootname}.blif \ ${lefpath} ${layoutdir}/${rootname}.cel >>& ${synthlog} #--------------------------------------------------------------------- # Spot check: Did blif2cel produce file ${rootname}.cel? #--------------------------------------------------------------------- if ( !( -f ${layoutdir}/${rootname}.cel || ( -M ${layoutdir}/${rootname}.cel \ < -M ${rootname}.blif ))) then echo "blif2cel failure: No file ${rootname}.cel." |& tee -a ${synthlog} echo "blif2cel was called with arguments: ${synthdir}/${rootname}.blif " echo " ${lefpath} ${layoutdir}/${rootname}.cel" echo "Premature exit." |& tee -a ${synthlog} echo "Synthesis flow stopped due to error condition." >> ${synthlog} exit 1 endif #------------------------------------------------------------------------- # If placement option "initial_density" is set, run the decongest # script. This will annotate the .cel file with fill cells to pad # out the area to the specified density. #------------------------------------------------------------------------- cd ${layoutdir} if ( ${?initial_density} ) then echo "Running decongest to set initial density of ${initial_density}" ${scriptdir}/decongest.tcl ${rootname} ${lefpath} \ ${fillcell} ${initial_density} |& tee -a ${synthlog} cp ${rootname}.cel ${rootname}.cel.bak mv ${rootname}.acel ${rootname}.cel endif cd ${projectpath} #------------------------------------------------------------------------- # Notice about editing should be replaced with automatic handling of # user directions about what to put in the .par file, like number of # rows or cell aspect ratio, etc., etc. #------------------------------------------------------------------------- # echo "Edit ${layoutdir}/${rootname}.par, then run placement and route" \ # |& tee -a ${synthlog} set endtime = `date` echo "Synthesis script ended on $endtime" >> $synthlog qflow-1.1.23/scripts/decongest.tcl.in0000775000175000001440000003257412614411007016225 0ustar timusers#!TCLSH_PATH # # Usage: # decongest.tcl [ ] # # Take information produced by qrouter's "congested" command, # and use it to add fill-cell padding to the most congested # instances in the .cel file. # # or # decongest.tcl # # Take the existing .cel file for graywolf input, # and pad the area out with randomly-assigned fill cells # to reduce the density of actively routed cells in the design. # # This procedure is necessary because GrayWolf does not # have a way (apparently) to reduce internal density by # adding spacers. So we use feedback from the router to # find targeted areas to add extra fill. Since GrayWolf # only looks at the contents of the .cel file, padding can # be added by rewriting the cell width for specific cells # to include the width of one or more filler cells. By # annotating the cell instance name, it becomes easy to # add the fill cells into the DEF file after placement. # # "scale" gives a scalefactor which is the amount of # increase in congestion that will cause an additional fill # cell to be added. Default is 0.1. Scale will be adjusted # upward according to the percentage of failing nets. # "offset" is the amount of congestion in the .cinfo file # that is the baseline for adding fill. Should be equal to # the minimum amount of congestion for which a fill cell is # added. Default is 0.6. # # "density" is a fraction of the area of the design that # is made up of actively routed cells; that is, the area # given to fill cells is (1 - density). It is used in place # of " ", and does not expect a ".cinfo" file # of congestion information. The fill cells will be randomly # placed. There is no default density. # #------------------------------------------------------------ # Written by Tim Edwards, November 23, 2013 #------------------------------------------------------------ # LEF dimensions are microns unless otherwise stated. if {$argc != 3 && $argc != 4 && $argc != 5} { puts stderr "Bad argument list" puts stderr "Usage: decongest.tcl [ ]" puts stderr "or: decongest.tcl " exit 1 } set units 100 set scale 0.1 set offset 0.5 set cellname [file rootname [lindex $argv 0]] set celfile ${cellname}.cel set annofile ${cellname}.acel set cinfofile ${cellname}.cinfo set lefname [lindex $argv 1] set fillcell [lindex $argv 2] if {$argc == 4} { set density [lindex $argv 3] set scale 0.0 ;# scale 0 used to denote density planning } elseif {$argc == 5} { set scale [lindex $argv 3] set offset [lindex $argv 4] } if [catch {open $lefname r} flef] { puts stderr "Error: can't open file $lefname for input" return } if [catch {open $celfile r} fcel] { puts stderr "Error: can't open file $celfile for input" return } if {$scale > 0.0} { if [catch {open $cinfofile r} finf] { puts stderr "Error: can't open file $cinfofile for input" return } } if [catch {open $annofile w} fanno] { puts stderr "Error: can't open file $annofile for output" return } #---------------------------------------------------------------- # Read through a LEF file section that we don't care about. #---------------------------------------------------------------- proc skip_section {leffile sectionname} { while {[gets $leffile line] >= 0} { if [regexp {[ \t]*END[ \t]+(.+)[ \t]*$} $line lmatch sectiontest] { if {"$sectiontest" != "$sectionname"} { puts -nonewline stderr "Unexpected END statement $line " puts stderr "while reading section $sectionname" } break } } } #---------------------------------------------------------------- # Parse the macro contents of the LEF file and retain the information # about cell size and pin positions. #---------------------------------------------------------------- proc parse_macro {leffile macroname} { global $macroname units while {[gets $leffile line] >= 0} { if [regexp {[ \t]*SYMMETRY[ \t]+(.+)[ \t]*;} $line lmatch symmetry] { set ${macroname}(symmetry) $symmetry } elseif [regexp {[ \t]*ORIGIN[ \t]+(.+)[ \t]+(.+)[ \t]*;} $line lmatch x y] { set x [expr {int($x * $units + 0.5)}] set y [expr {int($y * $units + 0.5)}] set ${macroname}(x) $x set ${macroname}(y) $y } elseif [regexp {[ \t]*SIZE[ \t]+(.+)[ \t]+BY[ \t]+(.+)[ \t]*;} \ $line lmatch w h] { set w [expr {int($w * $units + 0.5)}] set h [expr {int($h * $units + 0.5)}] set ${macroname}(w) $w set ${macroname}(h) $h } elseif [regexp {[ \t]*PIN[ \t]+(.+)[ \t]*$} $line lmatch pinname] { # The fill cell is not expected to have any usable pins skip_section $leffile $pinname } elseif [regexp {[ \t]*END[ \t]+(.+)[ \t]*$} $line lmatch macrotest] { if {"$macrotest" == "$macroname"} { break } else { puts stderr "Unexpected END statement $line while reading macro $macroname" } } } } #----------------------------------------------------------------- # Read the lef macro file and get the fill cells and their widths #----------------------------------------------------------------- puts stdout "Reading ${fillcell} macros from LEF file." flush stdout set fillcells {} while {[gets $flef line] >= 0} { if [regexp {[ \t]*MACRO[ \t]+(.+)[ \t]*$} $line lmatch macroname] { # Parse the "macro" statement parse_macro $flef $macroname if {[string first $fillcell $macroname] == 0} { # Remember this for later if it's a fill cell lappend fillcells $macroname } } elseif [regexp {[ \t]*LAYER[ \t]+([^ \t]+)} $line lmatch layername] { skip_section $flef $layername } elseif [regexp {[ \t]*VIA[ \t]+([^ \t]+)} $line lmatch vianame] { skip_section $flef $vianame } elseif [regexp {[ \t]*VIARULE[ \t]+([^ \t]+)} $line lmatch viarulename] { skip_section $flef $viarulename } elseif [regexp {[ \t]*SITE[ \t]+(.+)[ \t]*$} $line lmatch sitename] { skip_section $flef $sitename } elseif [regexp {[ \t]*UNITS[ \t]*$} $line lmatch] { skip_section $flef UNITS } elseif [regexp {[ \t]*SPACING[ \t]*$} $line lmatch] { skip_section $flef SPACING } elseif [regexp {[ \t]*END[ \t]+LIBRARY[ \t]*$} $line lmatch] { break } elseif [regexp {^[ \t]*#} $line lmatch] { # Comment line, ignore. } elseif ![regexp {^[ \t]*$} $line lmatch] { # Other things we don't care about set matches 0 if [regexp {[ \t]*NAMESCASESENSITIVE} $line lmatch] { incr matches } elseif [regexp {[ \t]*VERSION} $line lmatch] { incr matches } elseif [regexp {[ \t]*BUSBITCHARS} $line lmatch] { incr matches } elseif [regexp {[ \t]*DIVIDERCHAR} $line lmatch] { incr matches } elseif [regexp {[ \t]*USEMINSPACING} $line lmatch] { incr matches } elseif [regexp {[ \t]*CLEARANCEMEASURE} $line lmatch] { incr matches } elseif [regexp {[ \t]*MANUFACTURINGGRID} $line lmatch] { incr matches } else { puts stderr "Unexpected input in LEF file: Only macro defs were expected!" puts -nonewline stdout "Line is: $line" flush stdout } } } # If the macro file doesn't define any fill cells, there's not a # whole lot we can do. . . if {[llength $fillcells] == 0} { puts stdout "No fill cells (${fillname}) found in macro file ${lefname}!" exit 1 } close $flef # Sort array of fill cells by width set fillwidths {} foreach macro $fillcells { lappend fillwidths [list $macro [subst \$${macro}(w)]] } set fillwidths [lsort -decreasing -index 1 $fillwidths] set fillinfo [lindex $fillwidths 0] set fillmacro [lindex $fillinfo 0] set fillvalue [lindex $fillinfo 1] set halfvalue [expr {$fillvalue / 2}] #------------------------------------------------------------------------ # Now read the contents of the cinfo file so that we have a list of the # cells to add padding to #------------------------------------------------------------------------ if {$scale > 0.0} { gets $finf line ;# Throw-away line gets $finf line ;# Throw-away line gets $finf line ;# Failures: X Y if {![regexp {[ \t]*Failures:[ \t]+([0-9]+)[ \t]+([0-9]+)} $line \ lmatch failures numnets]} { puts stdout "Cannot parse number of route failures from .cinfo file!" exit 1 } gets $finf line ;# Throw-away line #------------------------------------------------------------------------ # Scale and offset adjustments #------------------------------------------------------------------------ set failratio [expr {($failures + 0.0) / $numnets}] # Redefine scale and offset so that the calculations are easier # Adjust the scale according to the fail ratio set scale [expr {1.0 / $scale}] set scale [expr {$scale + 60 * $failratio}] set offset [expr {$offset - (1.0 / $scale)}] #------------------------------------------------------------------------ set instlist {} set filllist {} while {[gets $finf line] >= 0} { if [regexp {[ \t]*([^ \t]+)[ \t]+([^ \t]+)} $line lmatch instname congest] { set numfill [expr {int(($congest - $offset) * $scale + 0.5)}] if {$numfill > 0} { lappend instlist $instname lappend filllist $numfill } } } close $finf } else { #------------------------------------------------------------------------ # Fixed density planning (No .cinfo file, just fixed density value) # Read .cel file to get a list of all instances. Record the total width # of all cells. Determine how many fill cells need to be added to # reduce the density of actively routed cells to the specified amount. # Randomly assign fill cells until the density requirement is met. #------------------------------------------------------------------------ set totalwidth 0 set instlist {} set filllist {} while {[gets $fcel line] >= 0} { if [regexp {[ \t]*cell[ \t]*([0-9]+)[ \t]+([^ \t]+)} $line \ lmatch instnum instname] { lappend instlist $instname gets $fcel line regexp {[ \t]*left[ \t]+([-]*[0-9]+)[ \t]+right[ \t]+([-]*[0-9]+)} $line \ lmatch left right incr totalwidth [expr {$right - $left}] } } set filltotal [expr {$totalwidth * ((1.0 / $density) - 1.0)}] set numfills [expr {int($filltotal / $fillvalue + 0.5)}] set numcells [llength $instlist] set basefills 0 # If there are multiple entries in the fill cell list, choose # a width such that the number of fill cells and number of # standard cells is more or less the same, preferably with # more fill cells than standard cells. Distribute the # fill cells among the standard cells. if {($numfills < $numcells) && ([llength $fillwidths] > 1)} { foreach fillinfo $fillwidths { set fillmacro [lindex $fillinfo 0] set fillvalue [lindex $fillinfo 1] set numfills [expr {int($filltotal / $fillvalue + 0.5)}] set numcells [llength $instlist] set halfvalue [expr {$fillvalue / 2}] if {$numfills > $numcells} {break} } } # Diagnostic information puts stdout "" puts stdout "decongest.tcl:" puts stdout "Fixed density planning, density = $density" puts stdout "Number of cells = $numcells, total width = $totalwidth" puts stdout "Width of fill = $fillvalue, total fill cells added = $numfills" puts stdout "" if {$numfills > $numcells} { while {$numfills > $numcells} { incr basefills set numfills [expr {$numfills - $numcells}] } set numfills [expr {$numcells - $numfills}] } incr basefills 1 for {set i 0} {$i < $numfills} {incr i} { lappend filllist $basefills } incr basefills -1 for {} {$i < $numcells} {incr i} { lappend filllist $basefills } # Rewind the cel file for the next step seek $fcel 0 start } #------------------------------------------------------------------------ # Now read the contents of the cel file. When a cell is found that is # in the "instlist" list of cells, annotate the next line to increase # the width by an amount equal to the width of a fill cell. # # To do: Use different fill cell widths according to congestion amount; # or use multiple fill cells (if different widths are not available). #------------------------------------------------------------------------ while {[gets $fcel line] >= 0} { if [regexp {[ \t]*cell[ \t]*([0-9]+)[ \t]+([^ \t]+)} $line lmatch instnum instname] { set instidx [lsearch $instlist $instname] if {$instidx >= 0} { set fillnum [lindex $filllist $instidx] if {$fillnum > 1} { puts $fanno "cell $instnum ${fillmacro}.${fillvalue}X${fillnum}.${instname}" set adjust [expr {$fillnum * $halfvalue}] } elseif {$fillnum == 0} { puts $fanno "cell $instnum ${instname}" set adjust 0 } else { puts $fanno "cell $instnum ${fillmacro}.${fillvalue}.${instname}" set adjust $halfvalue } gets $fcel line if [regexp {[ \t]*left[ \t]+([^ \t]+)[ \t]+right[ \t]+([^ \t]+)[ \t]+(.*)} $line \ lmatch left right rest] { set fleft [expr {$left - $adjust}] set fright [expr {$right + $adjust}] puts $fanno "left $fleft right $fright $rest" } else { puts $fanno $line ;# failed to parse, so ignore it } } else { puts $fanno $line } } else { puts $fanno $line } } puts stdout "Done!" qflow-1.1.23/scripts/blif2cel.tcl.in0000775000175000001440000003672712575541241015752 0ustar timusers#!TCLSH_PATH # # Usage: # blif2cel.tcl [] # # If cel_filename is not specified, then name will be the root name # of the .blif file with the .cel extension. # # NOTE: Cells must be placed relative to the LEF bounding box during # physical placement! # #------------------------------------------------------------ # Format translation between: # 1) LEF library file (input), # 2) .blif (mapped) netlist file (input), and # 3) .cel (output) file for GrayWolf placement #------------------------------------------------------------ # # Written by Tim Edwards July 25, 2006 MultiGiG, Inc. # Modified October 8, 2013 to use blif netlists as input #------------------------------------------------------------ # LEF dimensions are microns unless otherwise stated. set units 100 set pitchx 0 ;# value overridden from LEF file set pitchy 0 ;# value overridden from LEF file set trackskip 0 ;# reduce number of implicit feedthroughs ;# to avoid routing congestion set bliffile [lindex $argv 0] set cellname [file rootname [file tail $bliffile]] if {"$cellname" == "$bliffile"} { set bliffile ${cellname}.blif } if {$argc > 1} { set leffile [lindex $argv 1] } else { set leffile "-" } if {$argc == 3} { set celfile [lindex $argv 2] } else { set celfile ${cellname}.cel } #------------------------------------------------------------- set lefname [file rootname $leffile] if {"$lefname" == "$leffile"} { set leffile ${lefname}.lef } #------------------------------------------------------------- # Open files for read and write if [catch {open $leffile r} flef] { puts stderr "Error: second argument is not a LEF file!" exit 0 } if [catch {open $bliffile r} fnet] { puts stderr "Error: can't open file $bliffile for reading!" exit 0 } if [catch {open $celfile w} fcel] { puts stderr "Error: can't open file $celfile for writing!" exit 0 } #---------------------------------------------------------------- # First, parse the contents of the .blif file and get a list # of all macro names used. #---------------------------------------------------------------- puts stdout "1st pass of blif file ${bliffile}. . ." flush stdout set macrolist {} while {[gets $fnet line] >= 0} { if [regexp {^[ \t]*\.gate[ \t]+([^ \t]+)} $line lmatch macro] { lappend macrolist $macro } } set macrolist [lsort -unique $macrolist] close $fnet #---------------------------------------------------------------- # Parse port information for a macro pin from the LEF MACRO block # # Note that all of the geometry of each port gets whittled down # to a single point. Maybe GrayWolf can be made to work on # more complicated port geometry? #---------------------------------------------------------------- proc parse_port {pinname macroname leffile ox oy} { global $macroname units while {[gets $leffile line] >= 0} { if [regexp {[ \t]*LAYER[ \t]+(.+)[\t ]*;} $line lmatch layername] { if {![regexp {.*(\d).*} $layername lmatch layernum]} {set layernum 0} set ${macroname}(${pinname},layer) $layernum } elseif [regexp {[ \t]*RECT[ \t]+(.+)[ \t]+(.+)[ \t]+(.+)[ \t]+(.+)[ \t]*;} \ $line lmatch llx lly urx ury] { set llx [expr {int($llx * $units)}] set lly [expr {int($lly * $units)}] set urx [expr {int($urx * $units)}] set ury [expr {int($ury * $units)}] set xp [expr {(($llx + $urx) / 2) - $ox}] set yp [expr {(($lly + $ury) / 2) - $oy}] set ${macroname}(${pinname},xp) $xp set ${macroname}(${pinname},yp) $yp } elseif [regexp {[ \t]*POLYGON[ \t]+([^ \t]+)[ \t]+([^ \t]+)[ \t]+.*;} \ $line lmatch llx lly] { set llx [expr {int($llx * $units)}] set lly [expr {int($lly * $units)}] set xp [expr {$llx - $ox}] set yp [expr {$lly - $oy}] set ${macroname}(${pinname},xp) $xp set ${macroname}(${pinname},yp) $yp } elseif [regexp {[ \t]*END[ \t]*$} $line lmatch] { break } } puts -nonewline stdout "${pinname}" puts -nonewline stdout " [set ${macroname}(${pinname},xp)]" puts -nonewline stdout " [set ${macroname}(${pinname},yp)]" puts -nonewline stdout " [set ${macroname}(${pinname},layer)]" puts stdout "" } #---------------------------------------------------------------- # Parse pin information from the LEF MACRO block #---------------------------------------------------------------- proc parse_pin {pinname macroname leffile ox oy} { global $macroname while {[gets $leffile line] >= 0} { if [regexp {[ \t]*PORT} $line lmatch] { parse_port $pinname $macroname $leffile $ox $oy } elseif [regexp {[ \t]*DIRECTION[ \t]+([^ \t]+)[ \t]*;} $line lmatch porttype] { set ${macroname}(${pinname},type) $porttype } elseif [regexp {[ \t]*END[ \t]+([^ \t]+)[ \t]*$} $line lmatch pintest] { if {"$pintest" == "$pinname"} { break } else { puts stdout "Unexpected END statement $line while parsing pin $pinname" } } } } #---------------------------------------------------------------- # Read through a section that we don't care about. #---------------------------------------------------------------- proc skip_section {leffile sectionname} { while {[gets $leffile line] >= 0} { if [regexp {[ \t]*END[ \t]+(.+)[ \t]*$} $line lmatch sectiontest] { if {"$sectiontest" != "$sectionname"} { puts -nonewline stderr "Unexpected END statement $line " puts stderr "while reading section $sectionname" } break } } } #---------------------------------------------------------------- # Parse a layer section for routing information #---------------------------------------------------------------- proc parse_layer {leffile layername} { global pitchx pitchy units set pitch 0 set type NONE while {[gets $leffile line] >= 0} { regexp {[ \t]*TYPE[ \t]+(.+)[ \t]*;} $line lmatch type regexp {[ \t]*DIRECTION[ \t]+(.+)[ \t]*;} $line lmatch direc regexp {[ \t]*WIDTH[ \t]+(.+)[ \t]*;} $line lmatch width regexp {[ \t]*SPACING[ \t]+(.+)[ \t]*;} $line lmatch space set p2 [regexp {[ \t]*PITCH[ \t]+(.+)[ \t]+(.+)[ \t]*;} $line \ lmatch xpitch ypitch] set p1 [regexp {[ \t]*PITCH[ \t]+(.+)[ \t]*;} $line lmatch pitch] if [regexp {[ \t]*END[ \t]+(.+)[ \t]*$} $line lmatch layertest] { if {"$layertest" != "$layername"} { puts stderr "Unexpected END statement $line while reading layer $layername" } break } } # All we want to do here is determine the horizontal and vertical # route pitches if {$p2 == 1} { set tpitch [expr int($units * $xpitch)] set pitchx $tpitch set tpitch [expr int($units * $ypitch)] set pitchy $tpitch } elseif {$p1 == 1} { set tpitch [expr int($units * $pitch)] if {$tpitch > 0} { if {[string first "HORIZONTAL" $direc] == 0} { if {$pitchy == 0} { puts stdout "LEF file specifies route layer Y pitch as $pitch" set pitchy $tpitch } elseif {$tpitch < $pitchy} { set pitchy $tpitch puts stdout "LEF file specifies route layer Y pitch as $pitch" } } else { if {$pitchx == 0} { puts stdout "LEF file specifies route layer X pitch as $pitch" set pitchx $tpitch } elseif {$tpitch < $pitchx} { puts stdout "LEF file specifies route layer X pitch as $pitch" set pitchx $tpitch } } } } elseif {$type == "ROUTING"} { puts stdout "LEF file route layer ${layername} has no pitch information" } } #---------------------------------------------------------------- # Parse the macro contents of the LEF file and retain the information # about cell size and pin positions. #---------------------------------------------------------------- proc parse_macro {leffile macroname} { global $macroname units puts stderr "Parsing macro $macroname: Ports are:" while {[gets $leffile line] >= 0} { if [regexp {[ \t]*SYMMETRY[ \t]+(.+)[ \t]*;} $line lmatch symmetry] { set ${macroname}(symmetry) $symmetry } elseif [regexp {[ \t]*ORIGIN[ \t]+(.+)[ \t]+(.+)[ \t]*;} $line lmatch x y] { set x [expr {round($x * $units)}] set y [expr {round($y * $units)}] set ${macroname}(x) $x set ${macroname}(y) $y } elseif [regexp {[ \t]*SIZE[ \t]+(.+)[ \t]+BY[ \t]+(.+)[ \t]*;} \ $line lmatch w h] { set w [expr {round($w * $units)}] set h [expr {round($h * $units)}] set ${macroname}(w) $w set ${macroname}(h) $h # Compute derived values # ox, oy are the LEF coordinates where GrayWolf expects the "origin" set ox [expr {$x + ($w / 2)}] set oy [expr {$y + ($h / 2)}] set left [expr {-($w / 2)}] set right [expr {$left + $w}] set bottom [expr {-($h / 2)}] set top [expr {$bottom + $h}] set ${macroname}(ox) $ox set ${macroname}(oy) $oy set ${macroname}(left) $left set ${macroname}(right) $right set ${macroname}(top) $top set ${macroname}(bottom) $bottom } elseif [regexp {[ \t]*PIN[ \t]+(.+)[ \t]*$} $line lmatch pinname] { # Ignore additional information from LEF version 5.6 syntax set pinname [lindex $pinname 0] parse_pin $pinname $macroname $leffile $ox $oy } elseif [regexp {[ \t]*END[ \t]+(.+)[ \t]*$} $line lmatch macrotest] { if {"$macrotest" == "$macroname"} { break } else { puts stderr "Unexpected END statement $line while reading macro $macroname" } } } } puts stdout "Reading macros from LEF file. . ." flush stdout while {[gets $flef line] >= 0} { if [regexp {[ \t]*LAYER[ \t]+(.+)[ \t]*$} $line lmatch layername] { parse_layer $flef $layername } elseif [regexp {[ \t]*MACRO[ \t]+(.+)[ \t]*$} $line lmatch macroname] { if {[lsearch $macrolist $macroname] >= 0} { # Parse the "macro" statement parse_macro $flef $macroname } else { # This macro is not used. . . skip to end of macro while {[gets $flef line] >= 0} { if [regexp {[ \t]*END[ \t]+(.+)[ \t]*$} $line lmatch macrotest] { if {"$macroname" == "$macrotest"} { break } } } } } elseif [regexp {[ \t]*VIA[ \t]+([^ \t]+)} $line lmatch vianame] { skip_section $flef $vianame } elseif [regexp {[ \t]*VIARULE[ \t]+([^ \t]+)} $line lmatch viarulename] { skip_section $flef $viarulename } elseif [regexp {[ \t]*NONDEFAULTRULE[ \t]+([^ \t]+)} $line lmatch rulename] { skip_section $flef $rulename } elseif [regexp {[ \t]*SITE[ \t]+(.+)[ \t]*$} $line lmatch sitename] { skip_section $flef $sitename } elseif [regexp {[ \t]*UNITS[ \t]*$} $line lmatch] { skip_section $flef UNITS } elseif [regexp {[ \t]*SPACING[ \t]*$} $line lmatch] { skip_section $flef SPACING } elseif [regexp {[ \t]*PROPERTYDEFINITIONS[ \t]*$} $line lmatch] { skip_section $flef PROPERTYDEFINITIONS } elseif [regexp {[ \t]*END[ \t]+LIBRARY[ \t]*$} $line lmatch] { break } elseif [regexp {^[ \t]*#} $line lmatch] { # Comment line, ignore. } elseif ![regexp {^[ \t]*$} $line lmatch] { # Other things we don't care about set matches 0 if [regexp {[ \t]*NAMESCASESENSITIVE} $line lmatch] { incr matches } elseif [regexp {[ \t]*VERSION} $line lmatch] { incr matches } elseif [regexp {[ \t]*BUSBITCHARS} $line lmatch] { incr matches } elseif [regexp {[ \t]*DIVIDERCHAR} $line lmatch] { incr matches } elseif [regexp {[ \t]*USEMINSPACING} $line lmatch] { incr matches } elseif [regexp {[ \t]*CLEARANCEMEASURE} $line lmatch] { incr matches } elseif [regexp {[ \t]*MANUFACTURINGGRID} $line lmatch] { incr matches } elseif [regexp {[ \t]*MAXVIASTACK} $line lmatch] { # We *should* care about this one; need to pass it on to the router incr matches } else { puts stderr "Unexpected input in LEF file: Only macro defs were expected!" puts stdout "Line is: $line" } } } # If leffile didn't set pitch, then use defaults if {$pitchx == 0} { set pitchx 160 } if {$pitchy == 0} { set pitchy 200 } #---------------------------------------------------------------- # Parse the contents of the .blif file again and dump each cell # instance to the .cel file output. puts stdout "2nd pass of blif file. . ." flush stdout set fnet [open $bliffile r] set mode none set i 0 while {[gets $fnet line] >= 0} { if [regexp {^[ \t]*\.gate[ \t]+([^ \t]+)[ \t]+(.*)$} $line lmatch macroname rest] { set mode $macroname set left [set ${mode}(left)] set right [set ${mode}(right)] set width [set ${mode}(w)] set top [set ${mode}(top)] set bottom [set ${mode}(bottom)] if {[catch {incr ${mode}(count)}]} {set ${mode}(count) 0} set j [set ${mode}(count)] puts $fcel "cell $i ${mode}_$j" puts $fcel "left $left right $right bottom $bottom top $top" incr i # Follow this with implicit feedthroughs, as many as will fit # set feedx [expr {$left + ($pitchx / 2)}] set feedx [expr {$left + ($pitchx / 2) + ($trackskip * $pitchx)}] set k 1 while {$feedx < $right} { puts $fcel "pin name twfeed${k} signal TW_PASS_THRU layer 1 $feedx $bottom" puts $fcel " equiv name twfeed${k} layer 1 $feedx $top" set feedx [expr {$feedx + $pitchx}] incr k } # In the middle of parsing an instance; mode = instance name (in lowercase). foreach pinsig $rest { if [regexp {([^ \t=]+)=([^ \t]+)} $pinsig lmatch pinname netname] { set pinx [set ${mode}(${pinname},xp)] set piny [set ${mode}(${pinname},yp)] set pinlayer [set ${mode}(${pinname},layer)] set pintype [set ${mode}(${pinname},type)] # Is signal a buffer tree? If so, make it swappable, if it's an input if [regexp {(.*)_bF\$buf[0-9]+$} $netname lmatch sigpfix] { if {$pintype == "INPUT"} { puts $fcel "pin_group" puts $fcel "pin name ${sigpfix}_bF\$pin/$pinname signal $netname layer $pinlayer $pinx $piny" puts $fcel "end_pin_group" } else { puts $fcel "pin name $pinname signal $netname layer $pinlayer $pinx $piny" } } else { puts $fcel "pin name $pinname signal $netname layer $pinlayer $pinx $piny" } } } } elseif [regexp {^[ \t]*\.inputs} $line lmatch] { set mode "pins" } elseif [regexp {^[ \t]*\.outputs} $line lmatch] { set mode "pins" } elseif [regexp {^[ \t]*\.model[ \t]+([^ \t]+)} $line lmatch cellverify] { if {"$cellname" != "$cellverify"} { puts -nonewline stderr "WARNING: model name ${cellverify} does not" puts stderr " match filename ${cellname}!" } } } close $fnet #---------------------------------------------------------------- # Parse the contents of the .blif file again and dump each input or output # to the .cel file as a "pad". puts stdout "3rd pass of blif file. . ." flush stdout set px [expr int($pitchx / 2)] set py [expr int($pitchy / 2)] set fnet [open $bliffile r] set mode none set padnum 1 while {[gets $fnet line] >= 0} { if [regexp {^[ \t]*\.inputs[ \t]+(.*)$} $line lmatch rest] { set mode inputs set line $rest } elseif [regexp {^[ \t]*\.outputs[ \t]+(.*)$} $line lmatch rest] { set mode outputs set line $rest } elseif [regexp {^[\ t]*\.gate} $line lmatch] { break; } elseif [regexp {^[\ t]*\.end} $line lmatch] { break; } if [regexp {^(.*)[\\]+$} $line lmatch rest] { set line $rest } if {$mode == "inputs" || $mode == "outputs"} { foreach pinname $line { puts $fcel "pad $padnum name twpin_$pinname" puts $fcel "corners 4 -$px -$py -$px $py $px $py $px -$py" puts $fcel "pin name $pinname signal $pinname layer 1 0 0" puts $fcel "" incr padnum } } } puts stdout "Done!" qflow-1.1.23/scripts/placement.sh0000775000175000001440000004413612624355606015457 0ustar timusers#!/bin/tcsh -f #---------------------------------------------------------- # Placement script using GrayWolf # # This script assumes the existence of the pre-GrayWolf # ".cel" and ".par" files. It will run GrayWolf for the # placement. #---------------------------------------------------------- # Tim Edwards, 5/16/11, for Open Circuit Design # Modified April 2013 for use with qflow # Modified November 2013 for congestion feedback #---------------------------------------------------------- if ($#argv < 2) then echo Usage: placement.sh exit 1 endif # Split out options from the main arguments set argline=(`getopt "kdf" $argv[1-]`) set cmdargs=`echo "$argline" | awk 'BEGIN {FS = "-- "} END {print $2}'` set argc=`echo $cmdargs | wc -w` if ($argc == 2) then set argv1=`echo $cmdargs | cut -d' ' -f1` set argv2=`echo $cmdargs | cut -d' ' -f2` else echo Usage: placement.sh [options] echo where echo is the name of the project directory containing echo a file called qflow_vars.sh. echo is the root name of the verilog file, and echo [options] are: echo -k keep working files echo -d generate DEF file for routing echo -f final placement. Don't run if routing succeeded echo echo Options to specific tools can be specified with the following echo variables in project_vars.sh: echo echo exit 1 endif set keep=0 set makedef=0 set final = 0 foreach option (${argline}) switch (${option}) case -k: set keep=1 breaksw case -d: set makedef=1 breaksw case -f: set final=1 breaksw case --: break endsw end set projectpath=$argv1 set sourcename=$argv2 set rootname=${sourcename:h} # This script is called with the first argument , which should # have file "qflow_vars.sh". Get all of our standard variable definitions # from the qflow_vars.sh file. if (! -f ${projectpath}/qflow_vars.sh ) then echo "Error: Cannot find file qflow_vars.sh in path ${projectpath}" exit 1 endif source ${projectpath}/qflow_vars.sh source ${techdir}/${techname}.sh cd ${projectpath} # Prepend techdir to leffile unless leffile begins with "/" set abspath=`echo ${leffile} | cut -c1` if ( "${abspath}" == "/" ) then set lefpath=${leffile} else set lefpath=${techdir}/${leffile} endif # Prepend techdir to techleffile unless techleffile begins with "/" set abspath=`echo ${techleffile} | cut -c1` if ( "${abspath}" == "/" ) then set techlefpath=${techleffile} else set techlefpath=${techdir}/${techleffile} endif # Prepend techdir to spicefile unless spicefile begins with "/" set abspath=`echo ${spicefile} | cut -c1` if ( "${abspath}" == "/" ) then set spicepath=${spicefile} else set spicepath=${techdir}/${spicefile} endif #---------------------------------------------------------- # Done with initialization #---------------------------------------------------------- # Check if last line of log file says "error condition" set errcond = `tail -1 ${synthlog} | grep "error condition" | wc -l` if ( ${errcond} == 1 ) then echo "Synthesis flow stopped on error condition. Placement will not proceed" echo "until error condition is cleared." exit 1 endif #------------------------------------------------------------------------- # Create the .cel file for GrayWolf #------------------------------------------------------------------------- cd ${projectpath} echo "Running blif2cel.tcl" |& tee -a ${synthlog} ${scriptdir}/blif2cel.tcl ${synthdir}/${rootname}.blif \ ${lefpath} ${layoutdir}/${rootname}.cel >>& ${synthlog} #--------------------------------------------------------------------- # Spot check: Did blif2cel produce file ${rootname}.cel? #--------------------------------------------------------------------- if ( !( -f ${layoutdir}/${rootname}.cel || ( -M ${layoutdir}/${rootname}.cel \ < -M ${rootname}.blif ))) then echo "blif2cel failure: No file ${rootname}.cel." |& tee -a ${synthlog} echo "blif2cel was called with arguments: ${synthdir}/${rootname}.blif " echo " ${lefpath} ${layoutdir}/${rootname}.cel" echo "Premature exit." |& tee -a ${synthlog} echo "Synthesis flow stopped due to error condition." >> ${synthlog} exit 1 endif #------------------------------------------------------------------------- # If placement option "initial_density" is set, run the decongest # script. This will annotate the .cel file with fill cells to pad # out the area to the specified density. #------------------------------------------------------------------------- cd ${layoutdir} if ( ${?initial_density} ) then echo "Running decongest to set initial density of ${initial_density}" ${scriptdir}/decongest.tcl ${rootname} ${lefpath} \ ${fillcell} ${initial_density} |& tee -a ${synthlog} cp ${rootname}.cel ${rootname}.cel.bak mv ${rootname}.acel ${rootname}.cel endif # Check if a .acel file exists. This file is produced by qrouter and # its existance indicates that qrouter is passing back congestion # information to GrayWolf for a final placement pass using fill to # break up congested areas. if ( -f ${rootname}.acel && ( -M ${rootname}.acel > -M ${rootname}.cel )) then cp ${rootname}.cel ${rootname}.cel.bak mv ${rootname}.acel ${rootname}.cel set final = 1 else if ( ${final} == 1 ) then # Called for final time, but routing already succeeded, so just exit echo "First attempt routing succeeded; final placement iteration is unnecessary." exit 2 endif endif # Check if a .cel2 file exists and needs to be appended to .cel # If the .cel2 file is newer than .cel, then truncate .cel and # re-append. if ( -f ${rootname}.cel2 ) then echo "Preparing pin placement hints from ${rootname}.cel2" |& tee -a ${synthlog} if ( `grep -c padgroup ${rootname}.cel` == "0" ) then cat ${rootname}.cel2 >> ${rootname}.cel else if ( -M ${rootname}.cel2 > -M ${rootname}.cel ) then # Truncate .cel file to first line containing "padgroup" cat ${rootname}.cel | sed -e "/padgroup/Q" > ${rootname}_tmp.cel cat ${rootname}_tmp.cel ${rootname}.cel2 > ${rootname}.cel rm -f ${rootname}_tmp.cel endif else echo -n "No ${rootname}.cel2 file found for project. . . " \ |& tee -a ${synthlog} echo "continuing without pin placement hints" |& tee -a ${synthlog} endif #----------------------------------------------- # 1) Run GrayWolf #----------------------------------------------- if ( !( ${?graywolf_options} )) then if ( !( ${?DISPLAY} )) then set graywolf_options = "-n" else set graywolf_options = "" endif endif echo "Running GrayWolf placement" |& tee -a ${synthlog} ${bindir}/graywolf ${graywolf_options} $rootname >>& ${synthlog} endif #--------------------------------------------------------------------- # Spot check: Did GrayWolf produce file ${rootname}.pin? #--------------------------------------------------------------------- if ( !( -f ${rootname}.pin || ( -M ${rootname}.pin < -M ${rootname}.cel ))) then echo "GrayWolf failure: No file ${rootname}.pin." |& tee -a ${synthlog} echo "Premature exit." |& tee -a ${synthlog} echo "Synthesis flow stopped due to error condition." >> ${synthlog} exit 1 endif #--------------------------------------------------- # 2) Prepare DEF and .cfg files for qrouter #--------------------------------------------------- # First prepare a simple .cfg file that can be used to point qrouter # to the LEF files when generating layer information using the "-i" option. if ($makedef == 1) then #------------------------------------------------------------------ # Determine the version number and availability of scripting # in qrouter. #------------------------------------------------------------------ set version=`${bindir}/qrouter -v 0 -h | tail -1` set major=`echo $version | cut -d. -f1` set minor=`echo $version | cut -d. -f2` set subv=`echo $version | cut -d. -f3` set scripting=`echo $version | cut -d. -f4` # Create the initial (bootstrap) configuration file if ( $scripting == "T" ) then if ( "$techleffile" == "" ) then echo "read_lef ${lefpath}" > ${rootname}.cfg else echo "read_lef ${techlefpath}" > ${rootname}.cfg endif else if ( "$techleffile" == "" ) then echo "lef ${lefpath}" > ${rootname}.cfg else echo "lef ${techlefpath}" > ${rootname}.cfg endif endif ${bindir}/qrouter -i ${rootname}.info -c ${rootname}.cfg #--------------------------------------------------------------------- # Spot check: Did qrouter produce file ${rootname}.info? #--------------------------------------------------------------------- if ( !( -f ${rootname}.info || ( -M ${rootname}.info < -M ${rootname}.pin ))) then echo "qrouter (-i) failure: No file ${rootname}.info." |& tee -a ${synthlog} echo "Premature exit." |& tee -a ${synthlog} echo "Synthesis flow stopped due to error condition." >> ${synthlog} exit 1 endif # Run getfillcell to determine which cell should be used for fill to # match the width specified for feedthroughs in the .par file. If # nothing is returned by getfillcell, then either feedthroughs have # been disabled, or else we'll try passing $fillcell directly to # place2def echo "Running getfillcell.tcl" |& tee -a ${synthlog} set usefillcell = `${scriptdir}/getfillcell.tcl $rootname \ ${lefpath} $fillcell | grep fill= | cut -d= -f2` if ( "${usefillcell}" == "" ) then set usefillcell = $fillcell endif echo "Using cell ${usefillcell} for fill" |& tee -a ${synthlog} # Run place2def to turn the GrayWolf output into a DEF file if ( ${?route_layers} ) then ${scriptdir}/place2def.tcl $rootname $usefillcell ${route_layers} \ >>& ${synthlog} else ${scriptdir}/place2def.tcl $rootname $usefillcell >>& ${synthlog} endif #--------------------------------------------------------------------- # Spot check: Did place2def produce file ${rootname}.def? #--------------------------------------------------------------------- if ( !( -f ${rootname}.def || ( -M ${rootname}.def < -M ${rootname}.pin ))) then echo "place2def failure: No file ${rootname}.def." |& tee -a ${synthlog} echo "Premature exit." |& tee -a ${synthlog} echo "Synthesis flow stopped due to error condition." >> ${synthlog} exit 1 endif # Copy the .def file to a backup called "unroute" (temporary) cp ${rootname}.def ${rootname}_unroute.def # If the user didn't specify a number of layers for routing as part of # the project variables, then the info file created by qrouter will have # as many lines as there are route layers defined in the technology LEF # file. if ( !( ${?route_layers} )) then set route_layers = `cat ${rootname}.info | grep -e horizontal -e vertical | wc -l` endif # Create the main configuration file # Variables "via_pattern" (none, normal, invert) and "via_stacks" # can be specified in the tech script, and are appended to the # qrouter configuration file. via_stacks defaults to 2 if not # specified. It can be overridden from the user's .cfg2 file. if (${scripting} == "T") then echo "# qrouter runtime script for project ${rootname}" > ${rootname}.cfg echo "" >> ${rootname}.cfg echo "verbose 1" >> ${rootname}.cfg if ( "$techleffile" != "" ) then echo "read_lef ${techlefpath}" >> ${rootname}.cfg endif echo "read_lef ${lefpath}" >> ${rootname}.cfg echo "layers ${route_layers}" >> ${rootname}.cfg if ( ${?via_pattern} ) then echo "" >> ${rootname}.cfg echo "via pattern ${via_pattern}" >> ${rootname}.cfg endif if (! ${?via_stacks} ) then set via_stacks=2 echo "via stack ${via_stacks}" >> ${rootname}.cfg endif if ( ${?vddnet} ) then echo "vdd $vddnet" >> ${rootname}.cfg endif if ( ${?gndnet} ) then echo "gnd $gndnet" >> ${rootname}.cfg endif else echo "# qrouter configuration for project ${rootname}" > ${rootname}.cfg echo "" >> ${rootname}.cfg if ( "$techleffile" != "" ) then echo "lef ${techlefpath}" >> ${rootname}.cfg endif echo "lef ${lefpath}" >> ${rootname}.cfg echo "num_layers ${route_layers}" >> ${rootname}.cfg if ( ${?via_pattern} ) then echo "" >> ${rootname}.cfg echo "via pattern ${via_pattern}" >> ${rootname}.cfg endif if (! ${?via_stacks} ) then set via_stacks=2 echo "stack ${via_stacks}" >> ${rootname}.cfg endif endif # Add obstruction fence around design, created by place2def.tcl if ( -f ${rootname}.obs ) then cat ${rootname}.obs >> ${rootname}.cfg endif # Scripted version continues with the read-in of the DEF file if (${scripting} == "T") then echo "read_def ${rootname}.def" >> ${rootname}.cfg endif # If there is a file called ${rootname}.cfg2, then append it to the # ${rootname}.cfg file. It will be used to define all routing behavior. # Otherwise, if using scripting, then append the appropriate routing # command or procedure based on whether this is a pre-congestion # estimate of routing or the final routing pass. if ( -f ${rootname}.cfg2 ) then cat ${rootname}.cfg2 >> ${rootname}.cfg else if (${scripting} == "T") then if (${final} == 0) then echo "qrouter::congestion_route ${rootname}.cinfo" >> ${rootname}.cfg else echo "qrouter::standard_route" >> ${rootname}.cfg # Standard route falls back to the interpreter on failure, # so make sure that qrouter actually exits. echo "quit" >> ${rootname}.cfg endif endif endif #------------------------------------------------------------------ # Automatic optimization of buffer tree placement causes the # original BLIF netlist, with tentative buffer assignments, to # be invalid. Use the blifanno.tcl script to back-annotate the # correct assignments into the original BLIF netlist, then # use that BLIF netlist to regenerate the SPICE and RTL verilog # netlists. #------------------------------------------------------------------ ${scriptdir}/blifanno.tcl ${synthdir}/${rootname}.blif ${rootname}.def \ ${synthdir}/${rootname}_anno.blif >>& ${synthlog} #------------------------------------------------------------------ # Spot check: Did blifanno.tcl produce an output file? #------------------------------------------------------------------ if ( !( -f ${synthdir}/${rootname}_anno.blif )) then echo "blifanno.tcl failure: No file ${rootname}_anno.blif." \ |& tee -a ${synthlog} echo "RTL verilog and SPICE netlists may be invalid if there" \ |& tee -a ${synthlog} echo "were buffer trees optimized by placement." |& tee -a ${synthlog} echo "Synthesis flow continuing, condition not fatal." >> ${synthlog} else echo "" >> ${synthlog} echo "Generating RTL verilog and SPICE netlist file in directory" \ |& tee -a ${synthlog} echo " ${synthdir}" |& tee -a ${synthlog} echo "Files:" |& tee -a ${synthlog} echo " Verilog: ${synthdir}/${rootname}.rtl.v" |& tee -a ${synthlog} echo " Verilog: ${synthdir}/${rootname}.rtlnopwr.v" |& tee -a ${synthlog} echo " Spice: ${synthdir}/${rootname}.spc" |& tee -a ${synthlog} echo "" >> ${synthlog} cd ${synthdir} echo "Running blif2Verilog." |& tee -a ${synthlog} ${bindir}/blif2Verilog -c -v ${vddnet} -g ${gndnet} \ ${rootname}_anno.blif > ${rootname}.rtl.v ${bindir}/blif2Verilog -c -p -v ${vddnet} -g ${gndnet} \ ${rootname}_anno.blif > ${rootname}.rtlnopwr.v echo "Running blif2BSpice." |& tee -a ${synthlog} ${bindir}/blif2BSpice -p ${vddnet} -g ${gndnet} -l \ ${spicepath} ${rootname}_anno.blif \ > ${rootname}.spc #------------------------------------------------------------------ # Spot check: Did blif2Verilog or blif2BSpice exit with an error? #------------------------------------------------------------------ if ( !( -f ${rootname}.rtl.v || \ ( -M ${rootname}.rtl.v < -M ${rootname}.blif ))) then echo "blif2Verilog failure: No file ${rootname}.rtl.v created." \ |& tee -a ${synthlog} endif if ( !( -f ${rootname}.rtlnopwr.v || \ ( -M ${rootname}.rtlnopwr.v < -M ${rootname}.blif ))) then echo "blif2Verilog failure: No file ${rootname}.rtlnopwr.v created." \ |& tee -a ${synthlog} endif if ( !( -f ${rootname}.spc || \ ( -M ${rootname}.spc < -M ${rootname}.blif ))) then echo "blif2BSpice failure: No file ${rootname}.spc created." \ |& tee -a ${synthlog} endif # Return to the layout directory cd ${layoutdir} endif endif #--------------------------------------------------- # 3) Add spacer cells to create a straight border on # the right side #--------------------------------------------------- if ($makedef == 1) then if ( -f ${scriptdir}/addspacers.tcl ) then echo "Running addspacers.tcl" ${scriptdir}/addspacers.tcl ${rootname} ${lefpath} \ $fillcell >>& ${synthlog} if ( -f ${rootname}_filled.def ) then mv ${rootname}_filled.def ${rootname}.def # Copy the .def file to a backup called "unroute" (final) cp ${rootname}.def ${rootname}_unroute.def endif endif endif #--------------------------------------------------- # 4) Remove working files (except for the main # output files .pin, .pl1, and .pl2 #--------------------------------------------------- if ($keep == 0) then rm -f ${rootname}.blk ${rootname}.gen ${rootname}.gsav ${rootname}.history rm -f ${rootname}.log ${rootname}.mcel ${rootname}.mdat ${rootname}.mgeo rm -f ${rootname}.mout ${rootname}.mpin ${rootname}.mpth ${rootname}.msav rm -f ${rootname}.mver ${rootname}.mvio ${rootname}.stat ${rootname}.out rm -f ${rootname}.pth ${rootname}.sav ${rootname}.scel ${rootname}.txt endif #------------------------------------------------------------ # Done! #------------------------------------------------------------ set endtime = `date` echo "Placement script ended on $endtime" >> $synthlog exit 0 qflow-1.1.23/scripts/getfillcell.tcl.in0000775000175000001440000001431112533671313016535 0ustar timusers#!TCLSH_PATH #--------------------------------------------------------------------------- # getfillcell.tcl --- # # Read the .par file and find the feedthru width # Read LEF file and parse for fill cells; find the one that # corresponds to the feedthru width and return its name # # NOTE: The eventual goal is to have the .par file automatically # generated, in which case we really want to do this process in # reverse. # #--------------------------------------------------------------------------- namespace path {::tcl::mathop ::tcl::mathfunc} if {$argc < 3} { puts stdout "Usage: getfillcell " exit 0 } puts stdout "Running getfillcell.tcl" set topname [file rootname [lindex $argv 0]] set lefname [lindex $argv 1] set fillcell [lindex $argv 2] set parname ${topname}.par set units 100 ;# read micron units from the LEF file ;# and convert to centimicrons #----------------------------------------------------------------- # Open all files for reading and writing #----------------------------------------------------------------- if [catch {open $lefname r} flef] { puts stderr "Error: can't open file $lefname for input" return } if [catch {open $parname r} fpar] { puts stderr "Error: can't open file $parname for input" return } #----------------------------------------------------------------- # Read the .par file and look for "feedThruWidth". #----------------------------------------------------------------- puts stdout "Reading .par file ${parname}. . ." flush stdout set fwidth 0 while {[gets $fpar line] >= 0} { if {![regexp {[ \t]*#} $line lmatch]} { if [regexp {feedThruWidth[ \t]*:[ \t]*([0-9]+)} $line lmatch fwidth] { break } } } if {$fwidth == 0} { puts stdout "(no feedthroughs or width defined as zero)" } #---------------------------------------------------------------- # Read through a LEF file section that we don't care about. #---------------------------------------------------------------- proc skip_section {leffile sectionname} { while {[gets $leffile line] >= 0} { if [regexp {[ \t]*END[ \t]+(.+)[ \t]*$} $line lmatch sectiontest] { if {"$sectiontest" != "$sectionname"} { puts -nonewline stderr "Unexpected END statement $line " puts stderr "while reading section $sectionname" } break } } } #---------------------------------------------------------------- # Parse the macro contents of the LEF file and retain the information # about cell size and pin positions. #---------------------------------------------------------------- proc parse_macro {leffile macroname} { global $macroname units while {[gets $leffile line] >= 0} { if [regexp {[ \t]*SYMMETRY[ \t]+(.+)[ \t]*;} $line lmatch symmetry] { set ${macroname}(symmetry) $symmetry } elseif [regexp {[ \t]*ORIGIN[ \t]+(.+)[ \t]+(.+)[ \t]*;} $line lmatch x y] { set x [expr {int($x * $units)}] set y [expr {int($y * $units)}] set ${macroname}(x) $x set ${macroname}(y) $y } elseif [regexp {[ \t]*SIZE[ \t]+(.+)[ \t]+BY[ \t]+(.+)[ \t]*;} \ $line lmatch w h] { set w [expr {int($w * $units)}] set h [expr {int($h * $units)}] set ${macroname}(w) $w set ${macroname}(h) $h } elseif [regexp {[ \t]*PIN[ \t]+(.+)[ \t]*$} $line lmatch pinname] { # The fill cell is not expected to have any usable pins skip_section $leffile $pinname } elseif [regexp {[ \t]*END[ \t]+(.+)[ \t]*$} $line lmatch macrotest] { if {"$macrotest" == "$macroname"} { break } else { puts stderr "Unexpected END statement $line while reading macro $macroname" } } } } #----------------------------------------------------------------- # Read the lef macro file and get the fill cells and their widths #----------------------------------------------------------------- puts stdout "Reading ${fillcell} macros from LEF file." flush stdout puts stdout "Diagnostic: fill cell width from .par file is $fwidth" set usefillcell {} while {[gets $flef line] >= 0} { if [regexp {[ \t]*MACRO[ \t]+(.+)[ \t]*$} $line lmatch macroname] { # Parse the "macro" statement parse_macro $flef $macroname if {[string first $fillcell $macroname] == 0} { # Check width against feedthrough width puts stdout "Diagnostic: macro $macroname width = [subst \$${macroname}(w)]" if {[subst \$${macroname}(w)] == $fwidth} { set usefillcell $macroname } } } elseif [regexp {[ \t]*LAYER[ \t]+([^ \t]+)} $line lmatch layername] { skip_section $flef $layername } elseif [regexp {[ \t]*VIA[ \t]+([^ \t]+)} $line lmatch vianame] { skip_section $flef $vianame } elseif [regexp {[ \t]*VIARULE[ \t]+([^ \t]+)} $line lmatch viarulename] { skip_section $flef $viarulename } elseif [regexp {[ \t]*SITE[ \t]+(.+)[ \t]*$} $line lmatch sitename] { skip_section $flef $sitename } elseif [regexp {[ \t]*SPACING[ \t]*$} $line lmatch] { skip_section $flef SPACING } elseif [regexp {[ \t]*UNITS[ \t]*$} $line lmatch] { skip_section $flef UNITS } elseif [regexp {[ \t]*END[ \t]+LIBRARY[ \t]*$} $line lmatch] { break } elseif [regexp {^[ \t]*#} $line lmatch] { # Comment line, ignore. } elseif ![regexp {^[ \t]*$} $line lmatch] { # Other things we don't care about set matches 0 if [regexp {[ \t]*NAMESCASESENSITIVE} $line lmatch] { incr matches } elseif [regexp {[ \t]*VERSION} $line lmatch] { incr matches } elseif [regexp {[ \t]*BUSBITCHARS} $line lmatch] { incr matches } elseif [regexp {[ \t]*DIVIDERCHAR} $line lmatch] { incr matches } elseif [regexp {[ \t]*USEMINSPACING} $line lmatch] { incr matches } elseif [regexp {[ \t]*CLEARANCEMEASURE} $line lmatch] { incr matches } elseif [regexp {[ \t]*MANUFACTURINGGRID} $line lmatch] { incr matches } else { puts stderr "Unexpected input in LEF file: Only macro defs were expected!" puts -nonewline stdout "Line is: $line" flush stdout } } } close $flef close $fpar puts stdout "fill=$usefillcell" puts stdout "Done with getfillcell.tcl" qflow-1.1.23/scripts/display.sh0000775000175000001440000001217312614152167015144 0ustar timusers#!/bin/tcsh -f #---------------------------------------------------------- # Qflow layout display script using magic-8.0 #---------------------------------------------------------- # Tim Edwards, April 2013 #---------------------------------------------------------- if ($#argv < 2) then echo Usage: display.sh [options] exit 1 endif # Split out options from the main arguments (no options---placeholder only) set argline=(`getopt "" $argv[1-]`) set cmdargs=`echo "$argline" | awk 'BEGIN {FS = "-- "} END {print $2}'` set argc=`echo $cmdargs | wc -w` if ($argc == 2) then set argv1=`echo $cmdargs | cut -d' ' -f1` set argv2=`echo $cmdargs | cut -d' ' -f2` else echo Usage: display.sh [options] echo where echo is the name of the project directory containing echo a file called qflow_vars.sh. echo is the root name of the verilog file, and exit 1 endif foreach option (${argline}) switch (${option}) case --: break endsw end set projectpath=$argv1 set sourcename=$argv2 set rootname=${sourcename:h} # This script is called with the first argument , which should # have file "qflow_vars.sh". Get all of our standard variable definitions # from the qflow_vars.sh file. if (! -f ${projectpath}/qflow_vars.sh ) then echo "Error: Cannot find file qflow_vars.sh in path ${projectpath}" exit 1 endif source ${projectpath}/qflow_vars.sh source ${techdir}/${techname}.sh cd ${projectpath} # Prepend techdir to magicrc unless magicrc begins with "/" set abspath=`echo ${magicrc} | cut -c1` if ( "${abspath}" == "/" ) then set magicrcpath=${magicrc} else set magicrcpath=${techdir}/${magicrc} endif # Prepend techdir to leffile unless leffile begins with "/" set abspath=`echo ${leffile} | cut -c1` if ( "${abspath}" == "/" ) then set lefpath=${leffile} else set lefpath=${techdir}/${leffile} endif # Prepend techdir to techleffile unless techleffile begins with "/" set abspath=`echo ${techleffile} | cut -c1` if ( "${abspath}" == "/" ) then set techlefpath=${techleffile} else set techlefpath=${techdir}/${techleffile} endif #---------------------------------------------------------- # Copy the .magicrc file from the tech directory to the # layout directory, if it does not have one. This file # automatically loads the correct technology file. #---------------------------------------------------------- if (! -f ${layoutdir}/.magicrc ) then if ( -f ${magicrcpath} ) then cp ${magicrcpath} ${layoutdir}/.magicrc endif endif #---------------------------------------------------------- # Done with initialization #---------------------------------------------------------- cd ${layoutdir} #--------------------------------------------------- # Create magic layout (.mag file) using the # technology LEF file to determine route widths # and other parameters. #--------------------------------------------------- if ($techleffile == "") then set lefcmd="lef read ${lefpath}" else set lefcmd="lef read ${techlefpath}\nlef read ${lefpath}" endif # Timestamp handling: If the .mag file is more recent # than the .def file, then print a message and do not # overwrite. set docreate=1 if ( -f ${rootname}.def && -f ${rootname}.mag) then set defstamp=`stat --format="%Y" ${rootname}.def` set magstamp=`stat --format="%Y" ${rootname}.mag` if ( $magstamp > $defstamp ) then echo "Magic database file ${rootname}.mag is more recent than DEF file." echo "If you want to recreate the .mag file, remove or rename the existing one." set docreate=0 endif endif # The following script reads in the DEF file and modifies labels so # that they are rotated outward from the cell, since DEF files don't # indicate label geometry. if ( ${docreate} == 1) then ${bindir}/magic -dnull -noconsole <& .magic_displays exit EOF set magicogl=`cat .magic_displays | grep OGL | wc -l` set magicx11=`cat .magic_displays | grep X11 | wc -l` rm -f .magic_displays # Run magic again, this time interactively. The script # exits when the user exits magic. if ( ${magicogl} >= 1 ) then ${bindir}/magic -d OGL ${rootname} else if ( ${magicx11} >= 1) then ${bindir}/magic -d X11 ${rootname} else echo "Magic does not support OpenGL or X11 graphics on this host." endif #------------------------------------------------------------ # Done! #------------------------------------------------------------ qflow-1.1.23/scripts/qflow.sh.in0000664000175000001440000003045612623664452015242 0ustar timusers#!/bin/tcsh -f # #------------------------------------------------------------------ # qflow.sh --- main program shell script #------------------------------------------------------------------ # Environment variable overrides the tech type in all cases except # when the technology is specified on the command line by -T. If # the environment variable is not set, the technology defaults to # the technology that is issued with the qflow distribution. set tech=`printenv QFLOW_TECH` set has_tech=0 if ( $tech == "" ) then # But. . . check if there is already a "qflow_vars.sh". If so, # parse it for "techname", and use that preferentially over the # default technology. if ( -f qflow_vars.sh ) then set tech=`cat qflow_vars.sh | grep techname | cut -d= -f2` set has_tech=1 else set tech=osu035 set has_tech=-1 endif endif # Environment variable overrides the project root path in all cases # except when the project root path is specified on the command line # by -p. If the environment variable does not exist, the project # root directory is assumed to be the current working directory. set project=`printenv QFLOW_PROJECT_ROOT` if ( $project == "" ) then set project=`pwd` endif # Source file is not specified unless given on the command line, # or if there is only one source file in the source directory. set vsource="" # Don't do anything unless told to on the command line set actions=0 set dohelp=0 set doversion=0 set dosynth=0 set doplace=0 set dosta=0 set doroute=0 set dodecongest=0 set doclean=0 set dodisplay=0 while ($#argv > 0) switch($argv[1]:q) case -T: case --tech: shift set tech=$argv[1] set has_tech=0 shift breaksw case -p: case --project: shift set project=$argv[1] shift breaksw case -h: case --help: set dohelp=1 shift breaksw case -v: case --version: set doversion=1 shift breaksw case synth: case synthesize: set dosynth=1 set actions=1 shift breaksw case place: set doplace=1 set actions=1 shift breaksw case sta: set dosta=1 set actions=1 shift breaksw case route: set doroute=1 set actions=1 shift breaksw case decongest: set dodecongest=1 shift breaksw case build: set dosynth=1 set doplace=1 set doroute=1 set dodecongest=1 set actions=1 shift breaksw case all: set dosynth=1 set doplace=1 set dosta=1 set doroute=1 set dodecongest=1 set doclean=1 set dodisplay=1 set actions=1 shift breaksw case clean: case cleanup: set doclean=1 shift breaksw case display: set dodisplay=1 shift breaksw default: if ($vsource != "") then break else set vsource=$argv[1] shift endif breaksw endsw end if ($doversion == 1 || $dohelp == 1) then echo "Qflow version QFLOW_VERSION revision QFLOW_REVISION" echo "" if ($doversion == 1) then exit 0 endif endif if ($dohelp == 1 || $#argv != 0) then echo "Usage: qflow [processes] [options] " echo "Processes: synthesize Synthesize verilog source" echo " place Run initial placement" echo " sta Static timing analysis" echo " route Run placement and route" echo " decongest Run congestion analysis, final place and route" echo " clean Remove temporary working files" echo " display Display routed result" echo "" echo " build Run scripts synthesize to route" echo " all Run scripts synthesize to display" echo "" echo "Options: -T, --tech Use technology " echo " -p, --project Project root directory is " if ($dohelp == 1) then exit 0 else exit 1 endif endif echo "" echo "--------------------------------" echo "Qflow project setup" echo "--------------------------------" echo "" if ($has_tech == 1) then echo "Technology set to $tech from existing qflow_vars.sh file" else if ($has_tech == -1) then echo "No technology specified or found; using default technology $tech" else echo "Technology set to $tech" endif source QFLOW_SCRIPT_DIR/checkdirs.sh ${tech} ${project} if ($vsource == "") then if (`ls ${sourcedir}/*.v | wc -l` == 1) then set vsource=`ls ${sourcedir}/*.v` else echo "Error: No verilog source file or module name has been specified" echo "and directory ${sourcedir} contains multiple verilog files." exit 1 endif endif # Module name is the root name of the verilog source file. set modulename=${vsource:r} #------------------------------------------------------------------ # Source the technology initialization script #------------------------------------------------------------------ if ( -f ${techdir}/${tech}.sh ) then source $techdir/${tech}.sh else echo "Error: Cannot find tech init script ${techdir}/${tech}.sh to source" exit 1 endif #------------------------------------------------------------------ # Prepare the script file to run in the project directory. We # specify all steps of the process and comment out those that # have not been selected. Finally, source the script. #------------------------------------------------------------------ set varfile=${projectpath}/qflow_vars.sh set execfile=${projectpath}/qflow_exec.sh set userfile=${projectpath}/project_vars.sh #------------------------------------------------------------------ # Check if a variables file exists. If so, note that we are # regenerating the flow, source the file, check if the technology # is being changed, and report if so. #------------------------------------------------------------------ set newtech = 0 if ( -f $varfile ) then set techorig=`cat $varfile | grep techname= | cut -d= -f2` if ( "${tech}" != "${techorig}" ) then echo "Warning: Project technology changed from ${techorig} to ${tech}" set newtech = 1 else echo "Regenerating files for existing project ${modulename}" endif endif echo "#\!/bin/tcsh" > ${varfile} echo "#-------------------------------------------" >> ${varfile} echo "# qflow variables for project ${project}" >> ${varfile} echo "#-------------------------------------------" >> ${varfile} echo "" >> ${varfile} echo "set projectpath=${projectpath}" >> ${varfile} echo "set techdir=${techdir}" >> ${varfile} echo "set sourcedir=${sourcedir}" >> ${varfile} echo "set synthdir=${synthdir}" >> ${varfile} echo "set layoutdir=${layoutdir}" >> ${varfile} echo "set techname=${techname}" >> ${varfile} echo "set scriptdir=${scriptdir}" >> ${varfile} echo "set bindir=${bindir}" >> ${varfile} echo "set synthlog=${projectpath}/synth.log" >> ${varfile} echo "if (-f ${projectpath}/project_vars.sh) then" >> ${varfile} echo " source ${projectpath}/project_vars.sh" >> ${varfile} echo "endif" >> ${varfile} echo "#-------------------------------------------" >> ${varfile} echo "" >> ${varfile} echo "#\!/bin/tcsh" > ${execfile} echo "#-------------------------------------------" >> ${execfile} echo "# qflow exec script for project ${project}" >> ${execfile} echo "#-------------------------------------------" >> ${execfile} echo "" >> ${execfile} #----------------------------------------------------- # The file "project_vars.sh" will ONLY be written if # one does not already exist, and then it will be an # empty file with a few pointers to values that can # be set by the user. #----------------------------------------------------- if ( ! -f ${userfile} ) then echo "#\!/bin/tcsh" > ${userfile} echo "#------------------------------------------------------------" >> ${userfile} echo "# project variables for project ${project}" >> ${userfile} echo "#------------------------------------------------------------" >> ${userfile} echo "" >> ${userfile} echo "# Synthesis command options:" >> ${userfile} echo "# -------------------------------------------" >> ${userfile} echo "# set yosys_options = " >> ${userfile} echo "# set yosys_script = " >> ${userfile} echo "# set yosys_debug = " >> ${userfile} echo "# set abc_script = " >> ${userfile} echo "# set nobuffers = " >> ${userfile} echo "# set fanout_options = " >> ${userfile} echo "" >> ${userfile} echo "# Placement command options:" >> ${userfile} echo "# -------------------------------------------" >> ${userfile} echo "# set initial_density = " >> ${userfile} echo "# set graywolf_options = " >> ${userfile} echo "" >> ${userfile} echo "# Router command options:" >> ${userfile} echo "# -------------------------------------------" >> ${userfile} echo "# set route_layers = " >> ${userfile} echo "# set via_stacks = " >> ${userfile} echo "# set qrouter_options = " >> ${userfile} echo "" echo "" >> ${userfile} echo "# Minimum operating period of the clock (in ps)" >> ${userfile} echo "# set vesta_options = --period 1E5" >> ${userfile} echo "" >> ${userfile} echo "#------------------------------------------------------------" >> ${userfile} echo "" >> ${userfile} endif if ($dosynth == 0) then echo -n "# " >> ${execfile} endif echo "${scriptdir}/synthesize.sh ${projectpath} ${modulename}" >> ${execfile} if ($doplace == 0) then echo -n "# " >> ${execfile} endif # Use -d because the user may decide not to run fanout buffering, # and the files generated by place2def.tcl are required for routing. echo "${scriptdir}/placement.sh -d ${projectpath} ${modulename}" >> ${execfile} if ($dosta == 0) then echo -n "# " >> ${execfile} endif echo "${scriptdir}/vesta.sh ${projectpath} ${modulename}" >> ${execfile} if ($doroute == 0) then echo -n "# " >> ${execfile} endif echo "${scriptdir}/router.sh ${projectpath} ${modulename}" >> ${execfile} if ($dodecongest == 0) then echo -n "# " >> ${execfile} endif echo "${scriptdir}/placement.sh -f -d ${projectpath} ${modulename}" >> ${execfile} if ($dodecongest == 0) then echo -n "# " >> ${execfile} endif echo -n "${scriptdir}/router.sh ${projectpath} ${modulename}" >> ${execfile} echo ' $status' >> ${execfile} if ($doclean == 0) then echo -n "# " >> ${execfile} endif echo "${scriptdir}/cleanup.sh ${projectpath} ${modulename}" >> ${execfile} if ($dodisplay == 0) then echo -n "# " >> ${execfile} endif echo "${scriptdir}/display.sh ${projectpath} ${modulename}" >> ${execfile} if ( $actions == 0 ) then echo "No actions specified on command line;" echo "creating qflow script file ${execfile} only." echo "Uncomment lines in this file and source the file to run the flow." endif chmod u+x ${execfile} # Drop the magic startup file into the layout directory if it does not exist # If it exists but the technology directory has a newer file, or if we are # changing technologies, then copy the old file to a backup and create a new # one. if (-d ${layoutdir}) then if (!(-f ${layoutdir}/.magicrc)) then cp ${techdir}/${magicrc} ${layoutdir}/.magicrc else if ( $newtech == 1 ) then echo "Technology changed: Old .magicrc file moved to .magicrc.orig" cp ${layoutdir}/.magicrc ${layoutdir}/.magicrc.orig cp ${techdir}/${magicrc} ${layoutdir}/.magicrc else if ( -M ${techdir}/${magicrc} > -M ${layoutdir}/.magicrc ) then echo -n "Technology .magicrc file has been updated. " echo "Old .magicrc file moved to .magicrc.orig" cp ${layoutdir}/.magicrc ${layoutdir}/.magicrc.orig cp ${techdir}/${magicrc} ${layoutdir}/.magicrc endif endif # Drop the GrayWolf parameter file into the layout directory if it does not # exist. Like the above, check if the techdir has a newer version, or if we # are changing technologies. if (-d ${layoutdir}) then if (!(-f ${layoutdir}/${modulename}.par)) then cp ${techdir}/${techname}.par ${layoutdir}/${modulename}.par else if ( $newtech == 1 ) then echo "Technology changed: Old .par file moved to .par.orig" cp ${layoutdir}/${modulename}.par ${layoutdir}/${modulename}.par.orig cp ${techdir}/${techname}.par ${layoutdir}/${modulename}.par else if ( -M ${techdir}/${techname}.par > -M ${layoutdir}/${modulename}.par ) then echo "Technology .par file has been updated. Old .par file moved to .par.orig" cp ${layoutdir}/${modulename}.par ${layoutdir}/${modulename}.par.orig cp ${techdir}/${techname}.par ${layoutdir}/${modulename}.par endif endif # Execute the script file to run any command that has not been commented out exec ${execfile} exit 0 qflow-1.1.23/scripts/vesta.sh0000775000175000001440000000536112614152167014622 0ustar timusers#!/bin/tcsh -f #---------------------------------------------------------- # Static timing analysis script using vesta #---------------------------------------------------------- # Tim Edwards, 10/29/13, for Open Circuit Design #---------------------------------------------------------- if ($#argv < 2) then echo Usage: vesta.sh [options] exit 1 endif # Split out options from the main arguments set argline=(`getopt "nr" $argv[1-]`) set options=`echo "$argline" | awk 'BEGIN {FS = "-- "} END {print $1}'` set cmdargs=`echo "$argline" | awk 'BEGIN {FS = "-- "} END {print $2}'` set argc=`echo $cmdargs | wc -w` if ($argc == 2) then set argv1=`echo $cmdargs | cut -d' ' -f1` set argv2=`echo $cmdargs | cut -d' ' -f2` else echo Usage: vesta.sh [options] echo where echo is the name of the project directory containing echo a file called qflow_vars.sh. echo is the root name of the verilog file exit 1 endif set projectpath=$argv1 set sourcename=$argv2 set rootname=${sourcename:h} # This script is called with the first argument , which should # have file "qflow_vars.sh". Get all of our standard variable definitions # from the qflow_vars.sh file. if (! -f ${projectpath}/qflow_vars.sh ) then echo "Error: Cannot find file qflow_vars.sh in path ${projectpath}" exit 1 endif source ${projectpath}/qflow_vars.sh source ${techdir}/${techname}.sh cd ${projectpath} if (! ${?vesta_options} ) then set vesta_options = ${options} endif # Check if last line of log file says "error condition" set errcond = `tail -1 ${synthlog} | grep "error condition" | wc -l` if ( ${errcond} == 1 ) then echo "Synthesis flow stopped on error condition. Static timing analysis" echo "will not proceed until error condition is cleared." exit 1 endif # Prepend techdir to libertyfile unless libertyfile begins with "/" set abspath=`echo ${libertyfile} | cut -c1` if ( "${abspath}" == "/" ) then set libertypath=${libertyfile} else set libertypath=${techdir}/${libertyfile} endif #---------------------------------------------------------- # Done with initialization #---------------------------------------------------------- cd ${synthdir} #------------------------------------------------------------------ # Generate the static timing analysis results #------------------------------------------------------------------ echo "" echo "Running vesta static timing analysis" echo "" ${bindir}/vesta ${vesta_options} ${rootname}.rtlnopwr.v \ ${libertypath} |& tee -a ${synthlog} echo "" #------------------------------------------------------------ # Done! #------------------------------------------------------------ qflow-1.1.23/config.guess0000755000175000001440000011302012526236535013764 0ustar timusers#! /bin/sh # Attempt to guess a canonical system name. # Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001 # Free Software Foundation, Inc. timestamp='2001-08-21' # This file is free software; you can redistribute it and/or modify it # under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, but # WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU # General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. # # As a special exception to the GNU General Public License, if you # distribute this file as part of a program that contains a # configuration script generated by Autoconf, you may include it under # the same distribution terms that you use for the rest of that program. # Written by Per Bothner . # Please send patches to . # # This script attempts to guess a canonical system name similar to # config.sub. If it succeeds, it prints the system name on stdout, and # exits with 0. Otherwise, it exits with 1. # # The plan is that this can be called by configure scripts if you # don't specify an explicit build system type. me=`echo "$0" | sed -e 's,.*/,,'` usage="\ Usage: $0 [OPTION] Output the configuration name of the system \`$me' is run on. Operation modes: -h, --help print this help, then exit -t, --time-stamp print date of last modification, then exit -v, --version print version number, then exit Report bugs and patches to ." version="\ GNU config.guess ($timestamp) Originally written by Per Bothner. Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. This is free software; see the source for copying conditions. There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE." help=" Try \`$me --help' for more information." # Parse command line while test $# -gt 0 ; do case $1 in --time-stamp | --time* | -t ) echo "$timestamp" ; exit 0 ;; --version | -v ) echo "$version" ; exit 0 ;; --help | --h* | -h ) echo "$usage"; exit 0 ;; -- ) # Stop option processing shift; break ;; - ) # Use stdin as input. break ;; -* ) echo "$me: invalid option $1$help" >&2 exit 1 ;; * ) break ;; esac done if test $# != 0; then echo "$me: too many arguments$help" >&2 exit 1 fi dummy=dummy-$$ trap 'rm -f $dummy.c $dummy.o $dummy.rel $dummy; exit 1' 1 2 15 # CC_FOR_BUILD -- compiler used by this script. # Historically, `CC_FOR_BUILD' used to be named `HOST_CC'. We still # use `HOST_CC' if defined, but it is deprecated. set_cc_for_build='case $CC_FOR_BUILD,$HOST_CC,$CC in ,,) echo "int dummy(){}" > $dummy.c ; for c in cc gcc c89 ; do ($c $dummy.c -c -o $dummy.o) >/dev/null 2>&1 ; if test $? = 0 ; then CC_FOR_BUILD="$c"; break ; fi ; done ; rm -f $dummy.c $dummy.o $dummy.rel ; if test x"$CC_FOR_BUILD" = x ; then CC_FOR_BUILD=no_compiler_found ; fi ;; ,,*) CC_FOR_BUILD=$CC ;; ,*,*) CC_FOR_BUILD=$HOST_CC ;; esac' # This is needed to find uname on a Pyramid OSx when run in the BSD universe. # (ghazi@noc.rutgers.edu 1994-08-24) if (test -f /.attbin/uname) >/dev/null 2>&1 ; then PATH=$PATH:/.attbin ; export PATH fi UNAME_MACHINE=`(uname -m) 2>/dev/null` || UNAME_MACHINE=unknown UNAME_RELEASE=`(uname -r) 2>/dev/null` || UNAME_RELEASE=unknown UNAME_SYSTEM=`(uname -s) 2>/dev/null` || UNAME_SYSTEM=unknown UNAME_VERSION=`(uname -v) 2>/dev/null` || UNAME_VERSION=unknown # Note: order is significant - the case branches are not exclusive. case "${UNAME_MACHINE}:${UNAME_SYSTEM}:${UNAME_RELEASE}:${UNAME_VERSION}" in *:NetBSD:*:*) # Netbsd (nbsd) targets should (where applicable) match one or # more of the tupples: *-*-netbsdelf*, *-*-netbsdaout*, # *-*-netbsdecoff* and *-*-netbsd*. For targets that recently # switched to ELF, *-*-netbsd* would select the old # object file format. This provides both forward # compatibility and a consistent mechanism for selecting the # object file format. # Determine the machine/vendor (is the vendor relevant). case "${UNAME_MACHINE}" in amiga) machine=m68k-unknown ;; arm32) machine=arm-unknown ;; atari*) machine=m68k-atari ;; sun3*) machine=m68k-sun ;; mac68k) machine=m68k-apple ;; macppc) machine=powerpc-apple ;; hp3[0-9][05]) machine=m68k-hp ;; ibmrt|romp-ibm) machine=romp-ibm ;; *) machine=${UNAME_MACHINE}-unknown ;; esac # The Operating System including object format, if it has switched # to ELF recently, or will in the future. case "${UNAME_MACHINE}" in i386|sparc|amiga|arm*|hp300|mvme68k|vax|atari|luna68k|mac68k|news68k|next68k|pc532|sun3*|x68k) eval $set_cc_for_build if echo __ELF__ | $CC_FOR_BUILD -E - 2>/dev/null \ | grep __ELF__ >/dev/null then # Once all utilities can be ECOFF (netbsdecoff) or a.out (netbsdaout). # Return netbsd for either. FIX? os=netbsd else os=netbsdelf fi ;; *) os=netbsd ;; esac # The OS release release=`echo ${UNAME_RELEASE}|sed -e 's/[-_].*/\./'` # Since CPU_TYPE-MANUFACTURER-KERNEL-OPERATING_SYSTEM: # contains redundant information, the shorter form: # CPU_TYPE-MANUFACTURER-OPERATING_SYSTEM is used. echo "${machine}-${os}${release}" exit 0 ;; alpha:OSF1:*:*) if test $UNAME_RELEASE = "V4.0"; then UNAME_RELEASE=`/usr/sbin/sizer -v | awk '{print $3}'` fi # A Vn.n version is a released version. # A Tn.n version is a released field test version. # A Xn.n version is an unreleased experimental baselevel. # 1.2 uses "1.2" for uname -r. cat <$dummy.s .data \$Lformat: .byte 37,100,45,37,120,10,0 # "%d-%x\n" .text .globl main .align 4 .ent main main: .frame \$30,16,\$26,0 ldgp \$29,0(\$27) .prologue 1 .long 0x47e03d80 # implver \$0 lda \$2,-1 .long 0x47e20c21 # amask \$2,\$1 lda \$16,\$Lformat mov \$0,\$17 not \$1,\$18 jsr \$26,printf ldgp \$29,0(\$26) mov 0,\$16 jsr \$26,exit .end main EOF eval $set_cc_for_build $CC_FOR_BUILD $dummy.s -o $dummy 2>/dev/null if test "$?" = 0 ; then case `./$dummy` in 0-0) UNAME_MACHINE="alpha" ;; 1-0) UNAME_MACHINE="alphaev5" ;; 1-1) UNAME_MACHINE="alphaev56" ;; 1-101) UNAME_MACHINE="alphapca56" ;; 2-303) UNAME_MACHINE="alphaev6" ;; 2-307) UNAME_MACHINE="alphaev67" ;; 2-1307) UNAME_MACHINE="alphaev68" ;; esac fi rm -f $dummy.s $dummy echo ${UNAME_MACHINE}-dec-osf`echo ${UNAME_RELEASE} | sed -e 's/^[VTX]//' | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz'` exit 0 ;; Alpha\ *:Windows_NT*:*) # How do we know it's Interix rather than the generic POSIX subsystem? # Should we change UNAME_MACHINE based on the output of uname instead # of the specific Alpha model? echo alpha-pc-interix exit 0 ;; 21064:Windows_NT:50:3) echo alpha-dec-winnt3.5 exit 0 ;; Amiga*:UNIX_System_V:4.0:*) echo m68k-unknown-sysv4 exit 0;; amiga:OpenBSD:*:*) echo m68k-unknown-openbsd${UNAME_RELEASE} exit 0 ;; *:[Aa]miga[Oo][Ss]:*:*) echo ${UNAME_MACHINE}-unknown-amigaos exit 0 ;; arc64:OpenBSD:*:*) echo mips64el-unknown-openbsd${UNAME_RELEASE} exit 0 ;; arc:OpenBSD:*:*) echo mipsel-unknown-openbsd${UNAME_RELEASE} exit 0 ;; hkmips:OpenBSD:*:*) echo mips-unknown-openbsd${UNAME_RELEASE} exit 0 ;; pmax:OpenBSD:*:*) echo mipsel-unknown-openbsd${UNAME_RELEASE} exit 0 ;; sgi:OpenBSD:*:*) echo mips-unknown-openbsd${UNAME_RELEASE} exit 0 ;; wgrisc:OpenBSD:*:*) echo mipsel-unknown-openbsd${UNAME_RELEASE} exit 0 ;; *:OS/390:*:*) echo i370-ibm-openedition exit 0 ;; arm:RISC*:1.[012]*:*|arm:riscix:1.[012]*:*) echo arm-acorn-riscix${UNAME_RELEASE} exit 0;; SR2?01:HI-UX/MPP:*:* | SR8000:HI-UX/MPP:*:*) echo hppa1.1-hitachi-hiuxmpp exit 0;; Pyramid*:OSx*:*:* | MIS*:OSx*:*:* | MIS*:SMP_DC-OSx*:*:*) # akee@wpdis03.wpafb.af.mil (Earle F. Ake) contributed MIS and NILE. if test "`(/bin/universe) 2>/dev/null`" = att ; then echo pyramid-pyramid-sysv3 else echo pyramid-pyramid-bsd fi exit 0 ;; NILE*:*:*:dcosx) echo pyramid-pyramid-svr4 exit 0 ;; sun4H:SunOS:5.*:*) echo sparc-hal-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` exit 0 ;; sun4*:SunOS:5.*:* | tadpole*:SunOS:5.*:*) echo sparc-sun-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` exit 0 ;; i86pc:SunOS:5.*:*) echo i386-pc-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` exit 0 ;; sun4*:SunOS:6*:*) # According to config.sub, this is the proper way to canonicalize # SunOS6. Hard to guess exactly what SunOS6 will be like, but # it's likely to be more like Solaris than SunOS4. echo sparc-sun-solaris3`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` exit 0 ;; sun4*:SunOS:*:*) case "`/usr/bin/arch -k`" in Series*|S4*) UNAME_RELEASE=`uname -v` ;; esac # Japanese Language versions have a version number like `4.1.3-JL'. echo sparc-sun-sunos`echo ${UNAME_RELEASE}|sed -e 's/-/_/'` exit 0 ;; sun3*:SunOS:*:*) echo m68k-sun-sunos${UNAME_RELEASE} exit 0 ;; sun*:*:4.2BSD:*) UNAME_RELEASE=`(head -1 /etc/motd | awk '{print substr($5,1,3)}') 2>/dev/null` test "x${UNAME_RELEASE}" = "x" && UNAME_RELEASE=3 case "`/bin/arch`" in sun3) echo m68k-sun-sunos${UNAME_RELEASE} ;; sun4) echo sparc-sun-sunos${UNAME_RELEASE} ;; esac exit 0 ;; aushp:SunOS:*:*) echo sparc-auspex-sunos${UNAME_RELEASE} exit 0 ;; sparc*:NetBSD:*) echo `uname -p`-unknown-netbsd${UNAME_RELEASE} exit 0 ;; atari*:OpenBSD:*:*) echo m68k-unknown-openbsd${UNAME_RELEASE} exit 0 ;; # The situation for MiNT is a little confusing. The machine name # can be virtually everything (everything which is not # "atarist" or "atariste" at least should have a processor # > m68000). The system name ranges from "MiNT" over "FreeMiNT" # to the lowercase version "mint" (or "freemint"). Finally # the system name "TOS" denotes a system which is actually not # MiNT. But MiNT is downward compatible to TOS, so this should # be no problem. atarist[e]:*MiNT:*:* | atarist[e]:*mint:*:* | atarist[e]:*TOS:*:*) echo m68k-atari-mint${UNAME_RELEASE} exit 0 ;; atari*:*MiNT:*:* | atari*:*mint:*:* | atarist[e]:*TOS:*:*) echo m68k-atari-mint${UNAME_RELEASE} exit 0 ;; *falcon*:*MiNT:*:* | *falcon*:*mint:*:* | *falcon*:*TOS:*:*) echo m68k-atari-mint${UNAME_RELEASE} exit 0 ;; milan*:*MiNT:*:* | milan*:*mint:*:* | *milan*:*TOS:*:*) echo m68k-milan-mint${UNAME_RELEASE} exit 0 ;; hades*:*MiNT:*:* | hades*:*mint:*:* | *hades*:*TOS:*:*) echo m68k-hades-mint${UNAME_RELEASE} exit 0 ;; *:*MiNT:*:* | *:*mint:*:* | *:*TOS:*:*) echo m68k-unknown-mint${UNAME_RELEASE} exit 0 ;; sun3*:OpenBSD:*:*) echo m68k-unknown-openbsd${UNAME_RELEASE} exit 0 ;; mac68k:OpenBSD:*:*) echo m68k-unknown-openbsd${UNAME_RELEASE} exit 0 ;; mvme68k:OpenBSD:*:*) echo m68k-unknown-openbsd${UNAME_RELEASE} exit 0 ;; mvme88k:OpenBSD:*:*) echo m88k-unknown-openbsd${UNAME_RELEASE} exit 0 ;; powerpc:machten:*:*) echo powerpc-apple-machten${UNAME_RELEASE} exit 0 ;; RISC*:Mach:*:*) echo mips-dec-mach_bsd4.3 exit 0 ;; RISC*:ULTRIX:*:*) echo mips-dec-ultrix${UNAME_RELEASE} exit 0 ;; VAX*:ULTRIX*:*:*) echo vax-dec-ultrix${UNAME_RELEASE} exit 0 ;; 2020:CLIX:*:* | 2430:CLIX:*:*) echo clipper-intergraph-clix${UNAME_RELEASE} exit 0 ;; mips:*:*:UMIPS | mips:*:*:RISCos) sed 's/^ //' << EOF >$dummy.c #ifdef __cplusplus #include /* for printf() prototype */ int main (int argc, char *argv[]) { #else int main (argc, argv) int argc; char *argv[]; { #endif #if defined (host_mips) && defined (MIPSEB) #if defined (SYSTYPE_SYSV) printf ("mips-mips-riscos%ssysv\n", argv[1]); exit (0); #endif #if defined (SYSTYPE_SVR4) printf ("mips-mips-riscos%ssvr4\n", argv[1]); exit (0); #endif #if defined (SYSTYPE_BSD43) || defined(SYSTYPE_BSD) printf ("mips-mips-riscos%sbsd\n", argv[1]); exit (0); #endif #endif exit (-1); } EOF eval $set_cc_for_build $CC_FOR_BUILD $dummy.c -o $dummy \ && ./$dummy `echo "${UNAME_RELEASE}" | sed -n 's/\([0-9]*\).*/\1/p'` \ && rm -f $dummy.c $dummy && exit 0 rm -f $dummy.c $dummy echo mips-mips-riscos${UNAME_RELEASE} exit 0 ;; Motorola:PowerMAX_OS:*:*) echo powerpc-motorola-powermax exit 0 ;; Night_Hawk:Power_UNIX:*:*) echo powerpc-harris-powerunix exit 0 ;; m88k:CX/UX:7*:*) echo m88k-harris-cxux7 exit 0 ;; m88k:*:4*:R4*) echo m88k-motorola-sysv4 exit 0 ;; m88k:*:3*:R3*) echo m88k-motorola-sysv3 exit 0 ;; AViiON:dgux:*:*) # DG/UX returns AViiON for all architectures UNAME_PROCESSOR=`/usr/bin/uname -p` if [ $UNAME_PROCESSOR = mc88100 ] || [ $UNAME_PROCESSOR = mc88110 ] then if [ ${TARGET_BINARY_INTERFACE}x = m88kdguxelfx ] || \ [ ${TARGET_BINARY_INTERFACE}x = x ] then echo m88k-dg-dgux${UNAME_RELEASE} else echo m88k-dg-dguxbcs${UNAME_RELEASE} fi else echo i586-dg-dgux${UNAME_RELEASE} fi exit 0 ;; M88*:DolphinOS:*:*) # DolphinOS (SVR3) echo m88k-dolphin-sysv3 exit 0 ;; M88*:*:R3*:*) # Delta 88k system running SVR3 echo m88k-motorola-sysv3 exit 0 ;; XD88*:*:*:*) # Tektronix XD88 system running UTekV (SVR3) echo m88k-tektronix-sysv3 exit 0 ;; Tek43[0-9][0-9]:UTek:*:*) # Tektronix 4300 system running UTek (BSD) echo m68k-tektronix-bsd exit 0 ;; *:IRIX*:*:*) echo mips-sgi-irix`echo ${UNAME_RELEASE}|sed -e 's/-/_/g'` exit 0 ;; ????????:AIX?:[12].1:2) # AIX 2.2.1 or AIX 2.1.1 is RT/PC AIX. echo romp-ibm-aix # uname -m gives an 8 hex-code CPU id exit 0 ;; # Note that: echo "'`uname -s`'" gives 'AIX ' i*86:AIX:*:*) echo i386-ibm-aix exit 0 ;; ia64:AIX:*:*) if [ -x /usr/bin/oslevel ] ; then IBM_REV=`/usr/bin/oslevel` else IBM_REV=${UNAME_VERSION}.${UNAME_RELEASE} fi echo ${UNAME_MACHINE}-ibm-aix${IBM_REV} exit 0 ;; *:AIX:2:3) if grep bos325 /usr/include/stdio.h >/dev/null 2>&1; then sed 's/^ //' << EOF >$dummy.c #include main() { if (!__power_pc()) exit(1); puts("powerpc-ibm-aix3.2.5"); exit(0); } EOF eval $set_cc_for_build $CC_FOR_BUILD $dummy.c -o $dummy && ./$dummy && rm -f $dummy.c $dummy && exit 0 rm -f $dummy.c $dummy echo rs6000-ibm-aix3.2.5 elif grep bos324 /usr/include/stdio.h >/dev/null 2>&1; then echo rs6000-ibm-aix3.2.4 else echo rs6000-ibm-aix3.2 fi exit 0 ;; *:AIX:*:[45]) IBM_CPU_ID=`/usr/sbin/lsdev -C -c processor -S available | head -1 | awk '{ print $1 }'` if /usr/sbin/lsattr -El ${IBM_CPU_ID} | grep ' POWER' >/dev/null 2>&1; then IBM_ARCH=rs6000 else IBM_ARCH=powerpc fi if [ -x /usr/bin/oslevel ] ; then IBM_REV=`/usr/bin/oslevel` else IBM_REV=${UNAME_VERSION}.${UNAME_RELEASE} fi echo ${IBM_ARCH}-ibm-aix${IBM_REV} exit 0 ;; *:AIX:*:*) echo rs6000-ibm-aix exit 0 ;; ibmrt:4.4BSD:*|romp-ibm:BSD:*) echo romp-ibm-bsd4.4 exit 0 ;; ibmrt:*BSD:*|romp-ibm:BSD:*) # covers RT/PC BSD and echo romp-ibm-bsd${UNAME_RELEASE} # 4.3 with uname added to exit 0 ;; # report: romp-ibm BSD 4.3 *:BOSX:*:*) echo rs6000-bull-bosx exit 0 ;; DPX/2?00:B.O.S.:*:*) echo m68k-bull-sysv3 exit 0 ;; 9000/[34]??:4.3bsd:1.*:*) echo m68k-hp-bsd exit 0 ;; hp300:4.4BSD:*:* | 9000/[34]??:4.3bsd:2.*:*) echo m68k-hp-bsd4.4 exit 0 ;; 9000/[34678]??:HP-UX:*:*) HPUX_REV=`echo ${UNAME_RELEASE}|sed -e 's/[^.]*.[0B]*//'` case "${UNAME_MACHINE}" in 9000/31? ) HP_ARCH=m68000 ;; 9000/[34]?? ) HP_ARCH=m68k ;; 9000/[678][0-9][0-9]) case "${HPUX_REV}" in 11.[0-9][0-9]) if [ -x /usr/bin/getconf ]; then sc_cpu_version=`/usr/bin/getconf SC_CPU_VERSION 2>/dev/null` sc_kernel_bits=`/usr/bin/getconf SC_KERNEL_BITS 2>/dev/null` case "${sc_cpu_version}" in 523) HP_ARCH="hppa1.0" ;; # CPU_PA_RISC1_0 528) HP_ARCH="hppa1.1" ;; # CPU_PA_RISC1_1 532) # CPU_PA_RISC2_0 case "${sc_kernel_bits}" in 32) HP_ARCH="hppa2.0n" ;; 64) HP_ARCH="hppa2.0w" ;; esac ;; esac fi ;; esac if [ "${HP_ARCH}" = "" ]; then sed 's/^ //' << EOF >$dummy.c #define _HPUX_SOURCE #include #include int main () { #if defined(_SC_KERNEL_BITS) long bits = sysconf(_SC_KERNEL_BITS); #endif long cpu = sysconf (_SC_CPU_VERSION); switch (cpu) { case CPU_PA_RISC1_0: puts ("hppa1.0"); break; case CPU_PA_RISC1_1: puts ("hppa1.1"); break; case CPU_PA_RISC2_0: #if defined(_SC_KERNEL_BITS) switch (bits) { case 64: puts ("hppa2.0w"); break; case 32: puts ("hppa2.0n"); break; default: puts ("hppa2.0"); break; } break; #else /* !defined(_SC_KERNEL_BITS) */ puts ("hppa2.0"); break; #endif default: puts ("hppa1.0"); break; } exit (0); } EOF eval $set_cc_for_build (CCOPTS= $CC_FOR_BUILD $dummy.c -o $dummy 2>/dev/null ) && HP_ARCH=`./$dummy` if test -z "$HP_ARCH"; then HP_ARCH=hppa; fi rm -f $dummy.c $dummy fi ;; esac echo ${HP_ARCH}-hp-hpux${HPUX_REV} exit 0 ;; ia64:HP-UX:*:*) HPUX_REV=`echo ${UNAME_RELEASE}|sed -e 's/[^.]*.[0B]*//'` echo ia64-hp-hpux${HPUX_REV} exit 0 ;; 3050*:HI-UX:*:*) sed 's/^ //' << EOF >$dummy.c #include int main () { long cpu = sysconf (_SC_CPU_VERSION); /* The order matters, because CPU_IS_HP_MC68K erroneously returns true for CPU_PA_RISC1_0. CPU_IS_PA_RISC returns correct results, however. */ if (CPU_IS_PA_RISC (cpu)) { switch (cpu) { case CPU_PA_RISC1_0: puts ("hppa1.0-hitachi-hiuxwe2"); break; case CPU_PA_RISC1_1: puts ("hppa1.1-hitachi-hiuxwe2"); break; case CPU_PA_RISC2_0: puts ("hppa2.0-hitachi-hiuxwe2"); break; default: puts ("hppa-hitachi-hiuxwe2"); break; } } else if (CPU_IS_HP_MC68K (cpu)) puts ("m68k-hitachi-hiuxwe2"); else puts ("unknown-hitachi-hiuxwe2"); exit (0); } EOF eval $set_cc_for_build $CC_FOR_BUILD $dummy.c -o $dummy && ./$dummy && rm -f $dummy.c $dummy && exit 0 rm -f $dummy.c $dummy echo unknown-hitachi-hiuxwe2 exit 0 ;; 9000/7??:4.3bsd:*:* | 9000/8?[79]:4.3bsd:*:* ) echo hppa1.1-hp-bsd exit 0 ;; 9000/8??:4.3bsd:*:*) echo hppa1.0-hp-bsd exit 0 ;; *9??*:MPE/iX:*:* | *3000*:MPE/iX:*:*) echo hppa1.0-hp-mpeix exit 0 ;; hp7??:OSF1:*:* | hp8?[79]:OSF1:*:* ) echo hppa1.1-hp-osf exit 0 ;; hp8??:OSF1:*:*) echo hppa1.0-hp-osf exit 0 ;; i*86:OSF1:*:*) if [ -x /usr/sbin/sysversion ] ; then echo ${UNAME_MACHINE}-unknown-osf1mk else echo ${UNAME_MACHINE}-unknown-osf1 fi exit 0 ;; parisc*:Lites*:*:*) echo hppa1.1-hp-lites exit 0 ;; hppa*:OpenBSD:*:*) echo hppa-unknown-openbsd exit 0 ;; C1*:ConvexOS:*:* | convex:ConvexOS:C1*:*) echo c1-convex-bsd exit 0 ;; C2*:ConvexOS:*:* | convex:ConvexOS:C2*:*) if getsysinfo -f scalar_acc then echo c32-convex-bsd else echo c2-convex-bsd fi exit 0 ;; C34*:ConvexOS:*:* | convex:ConvexOS:C34*:*) echo c34-convex-bsd exit 0 ;; C38*:ConvexOS:*:* | convex:ConvexOS:C38*:*) echo c38-convex-bsd exit 0 ;; C4*:ConvexOS:*:* | convex:ConvexOS:C4*:*) echo c4-convex-bsd exit 0 ;; CRAY*X-MP:*:*:*) echo xmp-cray-unicos exit 0 ;; CRAY*Y-MP:*:*:*) echo ymp-cray-unicos${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' exit 0 ;; CRAY*[A-Z]90:*:*:*) echo ${UNAME_MACHINE}-cray-unicos${UNAME_RELEASE} \ | sed -e 's/CRAY.*\([A-Z]90\)/\1/' \ -e y/ABCDEFGHIJKLMNOPQRSTUVWXYZ/abcdefghijklmnopqrstuvwxyz/ \ -e 's/\.[^.]*$/.X/' exit 0 ;; CRAY*TS:*:*:*) echo t90-cray-unicos${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' exit 0 ;; CRAY*T3D:*:*:*) echo alpha-cray-unicosmk${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' exit 0 ;; CRAY*T3E:*:*:*) echo alphaev5-cray-unicosmk${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' exit 0 ;; CRAY*SV1:*:*:*) echo sv1-cray-unicos${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' exit 0 ;; CRAY-2:*:*:*) echo cray2-cray-unicos exit 0 ;; F30[01]:UNIX_System_V:*:* | F700:UNIX_System_V:*:*) FUJITSU_PROC=`uname -m | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz'` FUJITSU_SYS=`uname -p | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz' | sed -e 's/\///'` FUJITSU_REL=`echo ${UNAME_RELEASE} | sed -e 's/ /_/'` echo "${FUJITSU_PROC}-fujitsu-${FUJITSU_SYS}${FUJITSU_REL}" exit 0 ;; hp300:OpenBSD:*:*) echo m68k-unknown-openbsd${UNAME_RELEASE} exit 0 ;; i*86:BSD/386:*:* | i*86:BSD/OS:*:* | *:Ascend\ Embedded/OS:*:*) echo ${UNAME_MACHINE}-pc-bsdi${UNAME_RELEASE} exit 0 ;; sparc*:BSD/OS:*:*) echo sparc-unknown-bsdi${UNAME_RELEASE} exit 0 ;; *:BSD/OS:*:*) echo ${UNAME_MACHINE}-unknown-bsdi${UNAME_RELEASE} exit 0 ;; *:FreeBSD:*:*) echo ${UNAME_MACHINE}-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` exit 0 ;; *:OpenBSD:*:*) echo ${UNAME_MACHINE}-unknown-openbsd`echo ${UNAME_RELEASE}|sed -e 's/[-_].*/\./'` exit 0 ;; i*:CYGWIN*:*) echo ${UNAME_MACHINE}-pc-cygwin exit 0 ;; i*:MINGW*:*) echo ${UNAME_MACHINE}-pc-mingw32 exit 0 ;; i*:PW*:*) echo ${UNAME_MACHINE}-pc-pw32 exit 0 ;; i*:Windows_NT*:* | Pentium*:Windows_NT*:*) # How do we know it's Interix rather than the generic POSIX subsystem? # It also conflicts with pre-2.0 versions of AT&T UWIN. Should we # UNAME_MACHINE based on the output of uname instead of i386? echo i386-pc-interix exit 0 ;; i*:UWIN*:*) echo ${UNAME_MACHINE}-pc-uwin exit 0 ;; p*:CYGWIN*:*) echo powerpcle-unknown-cygwin exit 0 ;; prep*:SunOS:5.*:*) echo powerpcle-unknown-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` exit 0 ;; *:GNU:*:*) echo `echo ${UNAME_MACHINE}|sed -e 's,[-/].*$,,'`-unknown-gnu`echo ${UNAME_RELEASE}|sed -e 's,/.*$,,'` exit 0 ;; i*86:Minix:*:*) echo ${UNAME_MACHINE}-pc-minix exit 0 ;; arm*:Linux:*:*) echo ${UNAME_MACHINE}-unknown-linux-gnu exit 0 ;; ia64:Linux:*:*) echo ${UNAME_MACHINE}-unknown-linux exit 0 ;; m68*:Linux:*:*) echo ${UNAME_MACHINE}-unknown-linux-gnu exit 0 ;; mips:Linux:*:*) case `sed -n '/^byte/s/^.*: \(.*\) endian/\1/p' < /proc/cpuinfo` in big) echo mips-unknown-linux-gnu && exit 0 ;; little) echo mipsel-unknown-linux-gnu && exit 0 ;; esac ;; ppc:Linux:*:*) echo powerpc-unknown-linux-gnu exit 0 ;; ppc64:Linux:*:*) echo powerpc64-unknown-linux-gnu exit 0 ;; alpha:Linux:*:*) case `sed -n '/^cpu model/s/^.*: \(.*\)/\1/p' < /proc/cpuinfo` in EV5) UNAME_MACHINE=alphaev5 ;; EV56) UNAME_MACHINE=alphaev56 ;; PCA56) UNAME_MACHINE=alphapca56 ;; PCA57) UNAME_MACHINE=alphapca56 ;; EV6) UNAME_MACHINE=alphaev6 ;; EV67) UNAME_MACHINE=alphaev67 ;; EV68*) UNAME_MACHINE=alphaev68 ;; esac objdump --private-headers /bin/sh | grep ld.so.1 >/dev/null if test "$?" = 0 ; then LIBC="libc1" ; else LIBC="" ; fi echo ${UNAME_MACHINE}-unknown-linux-gnu${LIBC} exit 0 ;; parisc:Linux:*:* | hppa:Linux:*:*) # Look for CPU level case `grep '^cpu[^a-z]*:' /proc/cpuinfo 2>/dev/null | cut -d' ' -f2` in PA7*) echo hppa1.1-unknown-linux-gnu ;; PA8*) echo hppa2.0-unknown-linux-gnu ;; *) echo hppa-unknown-linux-gnu ;; esac exit 0 ;; parisc64:Linux:*:* | hppa64:Linux:*:*) echo hppa64-unknown-linux-gnu exit 0 ;; s390:Linux:*:* | s390x:Linux:*:*) echo ${UNAME_MACHINE}-ibm-linux exit 0 ;; sh*:Linux:*:*) echo ${UNAME_MACHINE}-unknown-linux-gnu exit 0 ;; sparc:Linux:*:* | sparc64:Linux:*:*) echo ${UNAME_MACHINE}-unknown-linux-gnu exit 0 ;; x86_64:Linux:*:*) echo x86_64-unknown-linux-gnu exit 0 ;; i*86:Linux:*:*) # The BFD linker knows what the default object file format is, so # first see if it will tell us. cd to the root directory to prevent # problems with other programs or directories called `ld' in the path. ld_supported_targets=`cd /; ld --help 2>&1 \ | sed -ne '/supported targets:/!d s/[ ][ ]*/ /g s/.*supported targets: *// s/ .*// p'` case "$ld_supported_targets" in elf32-i386) TENTATIVE="${UNAME_MACHINE}-pc-linux-gnu" ;; a.out-i386-linux) echo "${UNAME_MACHINE}-pc-linux-gnuaout" exit 0 ;; coff-i386) echo "${UNAME_MACHINE}-pc-linux-gnucoff" exit 0 ;; "") # Either a pre-BFD a.out linker (linux-gnuoldld) or # one that does not give us useful --help. echo "${UNAME_MACHINE}-pc-linux-gnuoldld" exit 0 ;; esac # Determine whether the default compiler is a.out or elf cat >$dummy.c < #ifdef __cplusplus #include /* for printf() prototype */ int main (int argc, char *argv[]) { #else int main (argc, argv) int argc; char *argv[]; { #endif #ifdef __ELF__ # ifdef __GLIBC__ # if __GLIBC__ >= 2 printf ("%s-pc-linux-gnu\n", argv[1]); # else printf ("%s-pc-linux-gnulibc1\n", argv[1]); # endif # else printf ("%s-pc-linux-gnulibc1\n", argv[1]); # endif #else printf ("%s-pc-linux-gnuaout\n", argv[1]); #endif return 0; } EOF eval $set_cc_for_build $CC_FOR_BUILD $dummy.c -o $dummy 2>/dev/null && ./$dummy "${UNAME_MACHINE}" && rm -f $dummy.c $dummy && exit 0 rm -f $dummy.c $dummy test x"${TENTATIVE}" != x && echo "${TENTATIVE}" && exit 0 ;; i*86:DYNIX/ptx:4*:*) # ptx 4.0 does uname -s correctly, with DYNIX/ptx in there. # earlier versions are messed up and put the nodename in both # sysname and nodename. echo i386-sequent-sysv4 exit 0 ;; i*86:UNIX_SV:4.2MP:2.*) # Unixware is an offshoot of SVR4, but it has its own version # number series starting with 2... # I am not positive that other SVR4 systems won't match this, # I just have to hope. -- rms. # Use sysv4.2uw... so that sysv4* matches it. echo ${UNAME_MACHINE}-pc-sysv4.2uw${UNAME_VERSION} exit 0 ;; i*86:*:4.*:* | i*86:SYSTEM_V:4.*:*) UNAME_REL=`echo ${UNAME_RELEASE} | sed 's/\/MP$//'` if grep Novell /usr/include/link.h >/dev/null 2>/dev/null; then echo ${UNAME_MACHINE}-univel-sysv${UNAME_REL} else echo ${UNAME_MACHINE}-pc-sysv${UNAME_REL} fi exit 0 ;; i*86:*:5:[78]*) case `/bin/uname -X | grep "^Machine"` in *486*) UNAME_MACHINE=i486 ;; *Pentium) UNAME_MACHINE=i586 ;; *Pent*|*Celeron) UNAME_MACHINE=i686 ;; esac echo ${UNAME_MACHINE}-unknown-sysv${UNAME_RELEASE}${UNAME_SYSTEM}${UNAME_VERSION} exit 0 ;; i*86:*:3.2:*) if test -f /usr/options/cb.name; then UNAME_REL=`sed -n 's/.*Version //p' /dev/null >/dev/null ; then UNAME_REL=`(/bin/uname -X|egrep Release|sed -e 's/.*= //')` (/bin/uname -X|egrep i80486 >/dev/null) && UNAME_MACHINE=i486 (/bin/uname -X|egrep '^Machine.*Pentium' >/dev/null) \ && UNAME_MACHINE=i586 (/bin/uname -X|egrep '^Machine.*Pent ?II' >/dev/null) \ && UNAME_MACHINE=i686 (/bin/uname -X|egrep '^Machine.*Pentium Pro' >/dev/null) \ && UNAME_MACHINE=i686 echo ${UNAME_MACHINE}-pc-sco$UNAME_REL else echo ${UNAME_MACHINE}-pc-sysv32 fi exit 0 ;; i*86:*DOS:*:*) echo ${UNAME_MACHINE}-pc-msdosdjgpp exit 0 ;; pc:*:*:*) # Left here for compatibility: # uname -m prints for DJGPP always 'pc', but it prints nothing about # the processor, so we play safe by assuming i386. echo i386-pc-msdosdjgpp exit 0 ;; Intel:Mach:3*:*) echo i386-pc-mach3 exit 0 ;; paragon:*:*:*) echo i860-intel-osf1 exit 0 ;; i860:*:4.*:*) # i860-SVR4 if grep Stardent /usr/include/sys/uadmin.h >/dev/null 2>&1 ; then echo i860-stardent-sysv${UNAME_RELEASE} # Stardent Vistra i860-SVR4 else # Add other i860-SVR4 vendors below as they are discovered. echo i860-unknown-sysv${UNAME_RELEASE} # Unknown i860-SVR4 fi exit 0 ;; mini*:CTIX:SYS*5:*) # "miniframe" echo m68010-convergent-sysv exit 0 ;; M68*:*:R3V[567]*:*) test -r /sysV68 && echo 'm68k-motorola-sysv' && exit 0 ;; 3[34]??:*:4.0:3.0 | 3[34]??A:*:4.0:3.0 | 3[34]??,*:*:4.0:3.0 | 4850:*:4.0:3.0) OS_REL='' test -r /etc/.relid \ && OS_REL=.`sed -n 's/[^ ]* [^ ]* \([0-9][0-9]\).*/\1/p' < /etc/.relid` /bin/uname -p 2>/dev/null | grep 86 >/dev/null \ && echo i486-ncr-sysv4.3${OS_REL} && exit 0 /bin/uname -p 2>/dev/null | /bin/grep entium >/dev/null \ && echo i586-ncr-sysv4.3${OS_REL} && exit 0 ;; 3[34]??:*:4.0:* | 3[34]??,*:*:4.0:*) /bin/uname -p 2>/dev/null | grep 86 >/dev/null \ && echo i486-ncr-sysv4 && exit 0 ;; m68*:LynxOS:2.*:* | m68*:LynxOS:3.0*:*) echo m68k-unknown-lynxos${UNAME_RELEASE} exit 0 ;; mc68030:UNIX_System_V:4.*:*) echo m68k-atari-sysv4 exit 0 ;; i*86:LynxOS:2.*:* | i*86:LynxOS:3.[01]*:* | i*86:LynxOS:4.0*:*) echo i386-unknown-lynxos${UNAME_RELEASE} exit 0 ;; TSUNAMI:LynxOS:2.*:*) echo sparc-unknown-lynxos${UNAME_RELEASE} exit 0 ;; rs6000:LynxOS:2.*:*) echo rs6000-unknown-lynxos${UNAME_RELEASE} exit 0 ;; PowerPC:LynxOS:2.*:* | PowerPC:LynxOS:3.[01]*:* | PowerPC:LynxOS:4.0*:*) echo powerpc-unknown-lynxos${UNAME_RELEASE} exit 0 ;; SM[BE]S:UNIX_SV:*:*) echo mips-dde-sysv${UNAME_RELEASE} exit 0 ;; RM*:ReliantUNIX-*:*:*) echo mips-sni-sysv4 exit 0 ;; RM*:SINIX-*:*:*) echo mips-sni-sysv4 exit 0 ;; *:SINIX-*:*:*) if uname -p 2>/dev/null >/dev/null ; then UNAME_MACHINE=`(uname -p) 2>/dev/null` echo ${UNAME_MACHINE}-sni-sysv4 else echo ns32k-sni-sysv fi exit 0 ;; PENTIUM:*:4.0*:*) # Unisys `ClearPath HMP IX 4000' SVR4/MP effort # says echo i586-unisys-sysv4 exit 0 ;; *:UNIX_System_V:4*:FTX*) # From Gerald Hewes . # How about differentiating between stratus architectures? -djm echo hppa1.1-stratus-sysv4 exit 0 ;; *:*:*:FTX*) # From seanf@swdc.stratus.com. echo i860-stratus-sysv4 exit 0 ;; *:VOS:*:*) # From Paul.Green@stratus.com. echo hppa1.1-stratus-vos exit 0 ;; mc68*:A/UX:*:*) echo m68k-apple-aux${UNAME_RELEASE} exit 0 ;; news*:NEWS-OS:6*:*) echo mips-sony-newsos6 exit 0 ;; R[34]000:*System_V*:*:* | R4000:UNIX_SYSV:*:* | R*000:UNIX_SV:*:*) if [ -d /usr/nec ]; then echo mips-nec-sysv${UNAME_RELEASE} else echo mips-unknown-sysv${UNAME_RELEASE} fi exit 0 ;; BeBox:BeOS:*:*) # BeOS running on hardware made by Be, PPC only. echo powerpc-be-beos exit 0 ;; BeMac:BeOS:*:*) # BeOS running on Mac or Mac clone, PPC only. echo powerpc-apple-beos exit 0 ;; BePC:BeOS:*:*) # BeOS running on Intel PC compatible. echo i586-pc-beos exit 0 ;; SX-4:SUPER-UX:*:*) echo sx4-nec-superux${UNAME_RELEASE} exit 0 ;; SX-5:SUPER-UX:*:*) echo sx5-nec-superux${UNAME_RELEASE} exit 0 ;; Power*:Rhapsody:*:*) echo powerpc-apple-rhapsody${UNAME_RELEASE} exit 0 ;; *:Rhapsody:*:*) echo ${UNAME_MACHINE}-apple-rhapsody${UNAME_RELEASE} exit 0 ;; *:Darwin:*:*) echo `uname -p`-apple-darwin${UNAME_RELEASE} exit 0 ;; *:procnto*:*:* | *:QNX:[0123456789]*:*) if test "${UNAME_MACHINE}" = "x86pc"; then UNAME_MACHINE=pc fi echo `uname -p`-${UNAME_MACHINE}-nto-qnx exit 0 ;; *:QNX:*:4*) echo i386-pc-qnx exit 0 ;; NSR-[KW]:NONSTOP_KERNEL:*:*) echo nsr-tandem-nsk${UNAME_RELEASE} exit 0 ;; *:NonStop-UX:*:*) echo mips-compaq-nonstopux exit 0 ;; BS2000:POSIX*:*:*) echo bs2000-siemens-sysv exit 0 ;; DS/*:UNIX_System_V:*:*) echo ${UNAME_MACHINE}-${UNAME_SYSTEM}-${UNAME_RELEASE} exit 0 ;; *:Plan9:*:*) # "uname -m" is not consistent, so use $cputype instead. 386 # is converted to i386 for consistency with other x86 # operating systems. if test "$cputype" = "386"; then UNAME_MACHINE=i386 else UNAME_MACHINE="$cputype" fi echo ${UNAME_MACHINE}-unknown-plan9 exit 0 ;; i*86:OS/2:*:*) # If we were able to find `uname', then EMX Unix compatibility # is probably installed. echo ${UNAME_MACHINE}-pc-os2-emx exit 0 ;; *:TOPS-10:*:*) echo pdp10-unknown-tops10 exit 0 ;; *:TENEX:*:*) echo pdp10-unknown-tenex exit 0 ;; KS10:TOPS-20:*:* | KL10:TOPS-20:*:* | TYPE4:TOPS-20:*:*) echo pdp10-dec-tops20 exit 0 ;; XKL-1:TOPS-20:*:* | TYPE5:TOPS-20:*:*) echo pdp10-xkl-tops20 exit 0 ;; *:TOPS-20:*:*) echo pdp10-unknown-tops20 exit 0 ;; *:ITS:*:*) echo pdp10-unknown-its exit 0 ;; i*86:XTS-300:*:STOP) echo ${UNAME_MACHINE}-unknown-stop exit 0 ;; esac #echo '(No uname command or uname output not recognized.)' 1>&2 #echo "${UNAME_MACHINE}:${UNAME_SYSTEM}:${UNAME_RELEASE}:${UNAME_VERSION}" 1>&2 cat >$dummy.c < # include #endif main () { #if defined (sony) #if defined (MIPSEB) /* BFD wants "bsd" instead of "newsos". Perhaps BFD should be changed, I don't know.... */ printf ("mips-sony-bsd\n"); exit (0); #else #include printf ("m68k-sony-newsos%s\n", #ifdef NEWSOS4 "4" #else "" #endif ); exit (0); #endif #endif #if defined (__arm) && defined (__acorn) && defined (__unix) printf ("arm-acorn-riscix"); exit (0); #endif #if defined (hp300) && !defined (hpux) printf ("m68k-hp-bsd\n"); exit (0); #endif #if defined (NeXT) #if !defined (__ARCHITECTURE__) #define __ARCHITECTURE__ "m68k" #endif int version; version=`(hostinfo | sed -n 's/.*NeXT Mach \([0-9]*\).*/\1/p') 2>/dev/null`; if (version < 4) printf ("%s-next-nextstep%d\n", __ARCHITECTURE__, version); else printf ("%s-next-openstep%d\n", __ARCHITECTURE__, version); exit (0); #endif #if defined (MULTIMAX) || defined (n16) #if defined (UMAXV) printf ("ns32k-encore-sysv\n"); exit (0); #else #if defined (CMU) printf ("ns32k-encore-mach\n"); exit (0); #else printf ("ns32k-encore-bsd\n"); exit (0); #endif #endif #endif #if defined (__386BSD__) printf ("i386-pc-bsd\n"); exit (0); #endif #if defined (sequent) #if defined (i386) printf ("i386-sequent-dynix\n"); exit (0); #endif #if defined (ns32000) printf ("ns32k-sequent-dynix\n"); exit (0); #endif #endif #if defined (_SEQUENT_) struct utsname un; uname(&un); if (strncmp(un.version, "V2", 2) == 0) { printf ("i386-sequent-ptx2\n"); exit (0); } if (strncmp(un.version, "V1", 2) == 0) { /* XXX is V1 correct? */ printf ("i386-sequent-ptx1\n"); exit (0); } printf ("i386-sequent-ptx\n"); exit (0); #endif #if defined (vax) # if !defined (ultrix) # include # if defined (BSD) # if BSD == 43 printf ("vax-dec-bsd4.3\n"); exit (0); # else # if BSD == 199006 printf ("vax-dec-bsd4.3reno\n"); exit (0); # else printf ("vax-dec-bsd\n"); exit (0); # endif # endif # else printf ("vax-dec-bsd\n"); exit (0); # endif # else printf ("vax-dec-ultrix\n"); exit (0); # endif #endif #if defined (alliant) && defined (i860) printf ("i860-alliant-bsd\n"); exit (0); #endif exit (1); } EOF eval $set_cc_for_build $CC_FOR_BUILD $dummy.c -o $dummy 2>/dev/null && ./$dummy && rm -f $dummy.c $dummy && exit 0 rm -f $dummy.c $dummy # Apollos put the system type in the environment. test -d /usr/apollo && { echo ${ISP}-apollo-${SYSTYPE}; exit 0; } # Convex versions that predate uname can use getsysinfo(1) if [ -x /usr/convex/getsysinfo ] then case `getsysinfo -f cpu_type` in c1*) echo c1-convex-bsd exit 0 ;; c2*) if getsysinfo -f scalar_acc then echo c32-convex-bsd else echo c2-convex-bsd fi exit 0 ;; c34*) echo c34-convex-bsd exit 0 ;; c38*) echo c38-convex-bsd exit 0 ;; c4*) echo c4-convex-bsd exit 0 ;; esac fi cat >&2 < in order to provide the needed information to handle your system. config.guess timestamp = $timestamp uname -m = `(uname -m) 2>/dev/null || echo unknown` uname -r = `(uname -r) 2>/dev/null || echo unknown` uname -s = `(uname -s) 2>/dev/null || echo unknown` uname -v = `(uname -v) 2>/dev/null || echo unknown` /usr/bin/uname -p = `(/usr/bin/uname -p) 2>/dev/null` /bin/uname -X = `(/bin/uname -X) 2>/dev/null` hostinfo = `(hostinfo) 2>/dev/null` /bin/universe = `(/bin/universe) 2>/dev/null` /usr/bin/arch -k = `(/usr/bin/arch -k) 2>/dev/null` /bin/arch = `(/bin/arch) 2>/dev/null` /usr/bin/oslevel = `(/usr/bin/oslevel) 2>/dev/null` /usr/convex/getsysinfo = `(/usr/convex/getsysinfo) 2>/dev/null` UNAME_MACHINE = ${UNAME_MACHINE} UNAME_RELEASE = ${UNAME_RELEASE} UNAME_SYSTEM = ${UNAME_SYSTEM} UNAME_VERSION = ${UNAME_VERSION} EOF exit 1 # Local variables: # eval: (add-hook 'write-file-hooks 'time-stamp) # time-stamp-start: "timestamp='" # time-stamp-format: "%:y-%02m-%02d" # time-stamp-end: "'" # End: qflow-1.1.23/config.status0000775000175000001440000006206712614150373014172 0ustar timusers#! /bin/sh # Generated by configure. # Run this file to recreate the current configuration. # Compiler output produced by configure, useful for debugging # configure, is in config.log if it exists. debug=false ac_cs_recheck=false ac_cs_silent=false SHELL=${CONFIG_SHELL-/bin/sh} export SHELL ## -------------------- ## ## M4sh Initialization. ## ## -------------------- ## # Be more Bourne compatible DUALCASE=1; export DUALCASE # for MKS sh if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then : emulate sh NULLCMD=: # Pre-4.2 versions of Zsh do word splitting on ${1+"$@"}, which # is contrary to our usage. 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((c) | 0x40) : (c)) #endif #define XOR(e, f) (((e) && !(f)) || (!(e) && (f))) int main () { int i; for (i = 0; i < 256; i++) if (XOR (islower (i), ISLOWER (i)) || toupper (i) != TOUPPER (i)) return 2; return 0; } _ACEOF if ac_fn_c_try_run "$LINENO"; then : else ac_cv_header_stdc=no fi rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext \ conftest.$ac_objext conftest.beam conftest.$ac_ext fi fi fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_header_stdc" >&5 $as_echo "$ac_cv_header_stdc" >&6; } if test $ac_cv_header_stdc = yes; then $as_echo "#define STDC_HEADERS 1" >>confdefs.h fi for ac_func in setenv putenv do : as_ac_var=`$as_echo "ac_cv_func_$ac_func" | $as_tr_sh` ac_fn_c_check_func "$LINENO" "$ac_func" "$as_ac_var" if eval test \"x\$"$as_ac_var"\" = x"yes"; then : cat >>confdefs.h <<_ACEOF #define `$as_echo "HAVE_$ac_func" | $as_tr_cpp` 1 _ACEOF fi done # Options # ========================================= # Check whether --with-tclsh was given. if test "${with_tclsh+set}" = set; then : withval=$with_tclsh; if test -d "$withval"; then TCLSH_DIR=$withval elif test -f "$withval"; then # Path includes "/tclsh"; remove it TCLSH_DIR=${withval%/tclsh} else TCLSH_DIR=${PATH} fi # Extract the first word of "tclsh", so it can be a program name with args. set dummy tclsh; ac_word=$2 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 $as_echo_n "checking for $ac_word... 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" >&6; } if ${ac_cv_path_TCLSH_PATH+:} false; then : $as_echo_n "(cached) " >&6 else case $TCLSH_PATH in [\\/]* | ?:[\\/]*) ac_cv_path_TCLSH_PATH="$TCLSH_PATH" # Let the user override the test with a path. ;; *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then ac_cv_path_TCLSH_PATH="$as_dir/$ac_word$ac_exec_ext" $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi done done IFS=$as_save_IFS test -z "$ac_cv_path_TCLSH_PATH" && ac_cv_path_TCLSH_PATH="tclsh" ;; esac fi TCLSH_PATH=$ac_cv_path_TCLSH_PATH if test -n "$TCLSH_PATH"; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: $TCLSH_PATH" >&5 $as_echo "$TCLSH_PATH" >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } fi fi cat >>confdefs.h <<_ACEOF #define TCLSH_PATH "$TCLSH_PATH" _ACEOF # Check whether --with-magic was given. if test "${with_magic+set}" = set; then : withval=$with_magic; if test -d "$withval"; then QFLOW_MAGIC_DIR=$withval elif test -f "$withval"; then # Path includes "/magic"; remove it QFLOW_MAGIC_DIR=${withval%/magic} else QFLOW_MAGIC_DIR=${PATH} fi # Extract the first word of "magic", so it can be a program name with args. set dummy magic; ac_word=$2 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 $as_echo_n "checking for $ac_word... " >&6; } if ${ac_cv_path_QFLOW_MAGIC_PATH+:} false; then : $as_echo_n "(cached) " >&6 else case $QFLOW_MAGIC_PATH in [\\/]* | ?:[\\/]*) ac_cv_path_QFLOW_MAGIC_PATH="$QFLOW_MAGIC_PATH" # Let the user override the test with a path. ;; *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $QFLOW_MAGIC_DIR do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then ac_cv_path_QFLOW_MAGIC_PATH="$as_dir/$ac_word$ac_exec_ext" $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi done done IFS=$as_save_IFS ;; esac fi QFLOW_MAGIC_PATH=$ac_cv_path_QFLOW_MAGIC_PATH if test -n "$QFLOW_MAGIC_PATH"; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: $QFLOW_MAGIC_PATH" >&5 $as_echo "$QFLOW_MAGIC_PATH" >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } fi else # Extract the first word of "magic", so it can be a program name with args. set dummy magic; ac_word=$2 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 $as_echo_n "checking for $ac_word... " >&6; } if ${ac_cv_path_QFLOW_MAGIC_PATH+:} false; then : $as_echo_n "(cached) " >&6 else case $QFLOW_MAGIC_PATH in [\\/]* | ?:[\\/]*) ac_cv_path_QFLOW_MAGIC_PATH="$QFLOW_MAGIC_PATH" # Let the user override the test with a path. ;; *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then ac_cv_path_QFLOW_MAGIC_PATH="$as_dir/$ac_word$ac_exec_ext" $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi done done IFS=$as_save_IFS ;; esac fi QFLOW_MAGIC_PATH=$ac_cv_path_QFLOW_MAGIC_PATH if test -n "$QFLOW_MAGIC_PATH"; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: $QFLOW_MAGIC_PATH" >&5 $as_echo "$QFLOW_MAGIC_PATH" >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } fi fi cat >>confdefs.h <<_ACEOF #define QFLOW_MAGIC_PATH "$QFLOW_MAGIC_PATH" _ACEOF # Check whether --with-qrouter was given. if test "${with_qrouter+set}" = set; then : withval=$with_qrouter; if test -d "$withval"; then QFLOW_QROUTER_DIR=$withval elif test -f "$withval"; then # Path includes "/qrouter"; remove it QFLOW_QROUTER_DIR=${withval%/qrouter} else QFLOW_QROUTER_DIR=${PATH} fi # Extract the first word of "qrouter", so it can be a program name with args. set dummy qrouter; ac_word=$2 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 $as_echo_n "checking for $ac_word... " >&6; } if ${ac_cv_path_QFLOW_QROUTER_PATH+:} false; then : $as_echo_n "(cached) " >&6 else case $QFLOW_QROUTER_PATH in [\\/]* | ?:[\\/]*) ac_cv_path_QFLOW_QROUTER_PATH="$QFLOW_QROUTER_PATH" # Let the user override the test with a path. ;; *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $QFLOW_QROUTER_DIR do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then ac_cv_path_QFLOW_QROUTER_PATH="$as_dir/$ac_word$ac_exec_ext" $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi done done IFS=$as_save_IFS ;; esac fi QFLOW_QROUTER_PATH=$ac_cv_path_QFLOW_QROUTER_PATH if test -n "$QFLOW_QROUTER_PATH"; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: $QFLOW_QROUTER_PATH" >&5 $as_echo "$QFLOW_QROUTER_PATH" >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } fi else # Extract the first word of "qrouter", so it can be a program name with args. set dummy qrouter; ac_word=$2 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 $as_echo_n "checking for $ac_word... " >&6; } if ${ac_cv_path_QFLOW_QROUTER_PATH+:} false; then : $as_echo_n "(cached) " >&6 else case $QFLOW_QROUTER_PATH in [\\/]* | ?:[\\/]*) ac_cv_path_QFLOW_QROUTER_PATH="$QFLOW_QROUTER_PATH" # Let the user override the test with a path. ;; *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then ac_cv_path_QFLOW_QROUTER_PATH="$as_dir/$ac_word$ac_exec_ext" $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi done done IFS=$as_save_IFS ;; esac fi QFLOW_QROUTER_PATH=$ac_cv_path_QFLOW_QROUTER_PATH if test -n "$QFLOW_QROUTER_PATH"; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: $QFLOW_QROUTER_PATH" >&5 $as_echo "$QFLOW_QROUTER_PATH" >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } fi fi cat >>confdefs.h <<_ACEOF #define QFLOW_QROUTER_PATH "$QFLOW_QROUTER_PATH" _ACEOF # Check whether --with-graywolf was given. if test "${with_graywolf+set}" = set; then : withval=$with_graywolf; if test -d "$withval"; then QFLOW_GRAYWOLF_DIR=$withval elif test -f "$withval"; then # Path includes "/graywolf"; remove it QFLOW_GRAYWOLF_DIR=${withval%/graywolf} else QFLOW_GRAYWOLF_DIR=${PATH} fi # Extract the first word of "graywolf", so it can be a program name with args. set dummy graywolf; ac_word=$2 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 $as_echo_n "checking for $ac_word... " >&6; } if ${ac_cv_path_QFLOW_GRAYWOLF_PATH+:} false; then : $as_echo_n "(cached) " >&6 else case $QFLOW_GRAYWOLF_PATH in [\\/]* | ?:[\\/]*) ac_cv_path_QFLOW_GRAYWOLF_PATH="$QFLOW_GRAYWOLF_PATH" # Let the user override the test with a path. ;; *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $QFLOW_GRAYWOLF_DIR do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then ac_cv_path_QFLOW_GRAYWOLF_PATH="$as_dir/$ac_word$ac_exec_ext" $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi done done IFS=$as_save_IFS ;; esac fi QFLOW_GRAYWOLF_PATH=$ac_cv_path_QFLOW_GRAYWOLF_PATH if test -n "$QFLOW_GRAYWOLF_PATH"; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: $QFLOW_GRAYWOLF_PATH" >&5 $as_echo "$QFLOW_GRAYWOLF_PATH" >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } fi else # Extract the first word of "graywolf", so it can be a program name with args. set dummy graywolf; ac_word=$2 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 $as_echo_n "checking for $ac_word... " >&6; } if ${ac_cv_path_QFLOW_GRAYWOLF_PATH+:} false; then : $as_echo_n "(cached) " >&6 else case $QFLOW_GRAYWOLF_PATH in [\\/]* | ?:[\\/]*) ac_cv_path_QFLOW_GRAYWOLF_PATH="$QFLOW_GRAYWOLF_PATH" # Let the user override the test with a path. ;; *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then ac_cv_path_QFLOW_GRAYWOLF_PATH="$as_dir/$ac_word$ac_exec_ext" $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi done done IFS=$as_save_IFS ;; esac fi QFLOW_GRAYWOLF_PATH=$ac_cv_path_QFLOW_GRAYWOLF_PATH if test -n "$QFLOW_GRAYWOLF_PATH"; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: $QFLOW_GRAYWOLF_PATH" >&5 $as_echo "$QFLOW_GRAYWOLF_PATH" >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } fi fi cat >>confdefs.h <<_ACEOF #define QFLOW_GRAYWOLF_PATH "$QFLOW_GRAYWOLF_PATH" _ACEOF # Check whether --with-yosys was given. if test "${with_yosys+set}" = set; then : withval=$with_yosys; if test -d "$withval"; then QFLOW_YOSYS_DIR=$withval elif test -f "$withval"; then # Path includes "/yosys"; remove it QFLOW_YOSYS_DIR=${withval%/yosys} else QFLOW_YOSYS_DIR=${PATH} fi # Extract the first word of "yosys", so it can be a program name with args. set dummy yosys; ac_word=$2 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 $as_echo_n "checking for $ac_word... " >&6; } if ${ac_cv_path_QFLOW_YOSYS_PATH+:} false; then : $as_echo_n "(cached) " >&6 else case $QFLOW_YOSYS_PATH in [\\/]* | ?:[\\/]*) ac_cv_path_QFLOW_YOSYS_PATH="$QFLOW_YOSYS_PATH" # Let the user override the test with a path. ;; *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $QFLOW_YOSYS_DIR do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then ac_cv_path_QFLOW_YOSYS_PATH="$as_dir/$ac_word$ac_exec_ext" $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi done done IFS=$as_save_IFS ;; esac fi QFLOW_YOSYS_PATH=$ac_cv_path_QFLOW_YOSYS_PATH if test -n "$QFLOW_YOSYS_PATH"; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: $QFLOW_YOSYS_PATH" >&5 $as_echo "$QFLOW_YOSYS_PATH" >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } fi else # Extract the first word of "yosys", so it can be a program name with args. set dummy yosys; ac_word=$2 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 $as_echo_n "checking for $ac_word... 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If it contains results you don't # want to keep, you may remove or edit it. # # config.status only pays attention to the cache file if you give it # the --recheck option to rerun configure. # # `ac_cv_env_foo' variables (set or unset) will be overridden when # loading this file, other *unset* `ac_cv_foo' will be assigned the # following values. _ACEOF # The following way of writing the cache mishandles newlines in values, # but we know of no workaround that is simple, portable, and efficient. # So, we kill variables containing newlines. # Ultrix sh set writes to stderr and can't be redirected directly, # and sets the high bit in the cache file unless we assign to the vars. ( for ac_var in `(set) 2>&1 | sed -n 's/^\([a-zA-Z_][a-zA-Z0-9_]*\)=.*/\1/p'`; do eval ac_val=\$$ac_var case $ac_val in #( *${as_nl}*) case $ac_var in #( *_cv_*) { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: cache variable $ac_var contains a newline" >&5 $as_echo "$as_me: WARNING: cache variable $ac_var contains a newline" >&2;} ;; esac case $ac_var in #( _ | IFS | as_nl) ;; #( BASH_ARGV | BASH_SOURCE) eval $ac_var= ;; #( *) { eval $ac_var=; unset $ac_var;} ;; esac ;; esac done (set) 2>&1 | case $as_nl`(ac_space=' '; set) 2>&1` in #( *${as_nl}ac_space=\ *) # `set' does not quote correctly, so add quotes: double-quote # substitution turns \\\\ into \\, and sed turns \\ into \. sed -n \ "s/'/'\\\\''/g; s/^\\([_$as_cr_alnum]*_cv_[_$as_cr_alnum]*\\)=\\(.*\\)/\\1='\\2'/p" ;; #( *) # `set' quotes correctly as required by POSIX, so do not add quotes. sed -n "/^[_$as_cr_alnum]*_cv_[_$as_cr_alnum]*=/p" ;; esac | sort ) | sed ' /^ac_cv_env_/b end t clear :clear s/^\([^=]*\)=\(.*[{}].*\)$/test "${\1+set}" = set || &/ t end s/^\([^=]*\)=\(.*\)$/\1=${\1=\2}/ :end' >>confcache if diff "$cache_file" confcache >/dev/null 2>&1; then :; else if test -w "$cache_file"; then if test "x$cache_file" != "x/dev/null"; then { $as_echo "$as_me:${as_lineno-$LINENO}: updating cache $cache_file" >&5 $as_echo "$as_me: updating cache $cache_file" >&6;} if test ! -f "$cache_file" || test -h "$cache_file"; then cat confcache >"$cache_file" else case $cache_file in #( */* | ?:*) mv -f confcache "$cache_file"$$ && mv -f "$cache_file"$$ "$cache_file" ;; #( *) mv -f confcache "$cache_file" ;; esac fi fi else { $as_echo "$as_me:${as_lineno-$LINENO}: not updating unwritable cache $cache_file" >&5 $as_echo "$as_me: not updating unwritable cache $cache_file" >&6;} fi fi rm -f confcache test "x$prefix" = xNONE && prefix=$ac_default_prefix # Let make expand exec_prefix. test "x$exec_prefix" = xNONE && exec_prefix='${prefix}' # Transform confdefs.h into DEFS. # Protect against shell expansion while executing Makefile rules. # Protect against Makefile macro expansion. # # If the first sed substitution is executed (which looks for macros that # take arguments), then branch to the quote section. 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